2006.258.06:53:51.35;Log Opened: Mark IV Field System Version 9.7.7 2006.258.06:53:51.35;location,TSUKUB32,-140.09,36.10,61.0 2006.258.06:53:51.35;horizon1,0.,5.,360. 2006.258.06:53:51.35;antenna,32.0,180.0,180.0,10.0,710.0,5.0,88.0,azel 2006.258.06:53:51.35;equip,k42c/mk4,vlbab,vlbab,mk4,500.10,3,a/d,101,60,20,none,41,1,in,8bit,cdp,3 2006.258.06:53:51.35;drivev11,330,270,no 2006.258.06:53:51.35;drivev12,mvme117,0,11.400,2548.000,152.780,-6.655,0.014,152,10.000,54500 2006.258.06:53:51.35;drivev13,15.000,268,10.000,10.000,10.000 2006.258.06:53:51.35;drivev21,330,270,no 2006.258.06:53:51.35;drivev22,mvme117,0,11.500,2821.000,127.500,-8.640,0.015,152,14.000,54500 2006.258.06:53:51.35;drivev23,15.000,268,10.000,10.000,10.000 2006.258.06:53:51.35;head10,all,all,all,odd,adaptive,no,5.0000,1 2006.258.06:53:51.35;head11,131.5,16.4,-291.0,131.5,16.4,0.8,168.30,168.30 2006.258.06:53:51.35;head12,122.8,13.9,-150.8,122.8,14.7,2.5,167.61,167.61 2006.258.06:53:51.35;head20,all,all,all,odd,adaptive,no,5.0000,1 2006.258.06:53:51.35;head21,145.3,16.1,-209.3,137.2,16.1,58.9,165.28,165.28 2006.258.06:53:51.35;head22,157.5,17.4,-203.7,149.2,16.6,56.5,169.73,169.73 2006.258.06:53:51.35;time,-0.364,101.533,rate 2006.258.06:53:51.35;flagr,200 2006.258.06:53:51.35:" K06259 2006 TSUKUB32 T Ts 2006.258.06:53:51.35:" T TSUKUB32 AZEL .0000 180.0 14 10.0 710.0 180.0 14 5.0 88.0 32.0 Ts 108 2006.258.06:53:51.35:" Ts TSUKUB32 -3957408.75120 3310229.34660 3737494.83600 73452301 2006.258.06:53:51.35:" 108 TSUKUB32 14 17400 2006.258.06:53:51.35:" drudg version 050216 compiled under FS 9.7.07 2006.258.06:53:51.35:" Rack=K4-2/M4 Recorder 1=K5 Recorder 2=none 2006.258.06:53:51.35:exper_initi 2006.258.06:53:51.35&exper_initi/proc_library 2006.258.06:53:51.35&exper_initi/sched_initi 2006.258.06:53:51.35:!2006.259.06:29:50 2006.258.06:53:51.35&proc_library/" k06259 tsukub32 ts 2006.258.06:53:51.35&proc_library/" drudg version 050216 compiled under fs 9.7.7 2006.258.06:53:51.35&proc_library/"< k4-2/m4 rack >< k5 recorder 1> 2006.258.06:53:51.36&sched_initi/startcheck 2006.258.06:53:51.36&startcheck/sy=check_fsrun.pl & 2006.258.06:53:51.36&startcheck/" sy=/usr2/oper/temp/chmem.sh >& /dev/null & 2006.258.06:53:59.12;cable 2006.258.06:53:59.21/cable/+6.4565E-03 2006.258.06:54:56.71;cablelong 2006.258.06:54:56.80/cablelong/+7.0209E-03 2006.258.06:54:58.70;cablediff 2006.258.06:54:58.70/cablediff/564.4e-6,+ 2006.258.06:56:24.58;cable 2006.258.06:56:24.80/cable/+6.4589E-03 2006.258.06:56:27.77;wx 2006.258.06:56:27.78/wx/23.14,1015.3,69 2006.258.06:56:43.49;"Sky is fine. 2006.258.06:56:49.92;xfe 2006.258.06:56:50.01/xfe/off,on,15.2 2006.258.06:56:53.14;clockoff 2006.258.06:56:53.14&clockoff/"gps-fmout=1p 2006.258.06:56:53.14&clockoff/fmout-gps=1p 2006.258.06:56:54.07/fmout-gps/S +4.49E-07 2006.259.04:50:21.47?ERROR st -97 Trouble decoding pressure data 2006.259.04:50:21.48#wxget#03 2.0 4.3 24.59 681013.4 2006.259.06:29:50.00:sy=/usr2/oper/k5/bin/freeze_chk.pl & 2006.259.06:29:50.02:!2006.259.07:19:50 2006.259.07:19:50.00:unstow 2006.259.07:19:50.00&unstow/antenna=e 2006.259.07:19:50.00&unstow/!+10s 2006.259.07:19:50.00&unstow/antenna=m2 2006.259.07:20:02.01:scan_name=259-0730,k06259,60 2006.259.07:20:02.01:source=1128+385,113053.28,381518.5,2000.0,ccw 2006.259.07:20:02.02#antcn#PM 1 00019 2005 228 00 22 31 00 2006.259.07:20:02.02#antcn#PM 2 90.0000 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 2006.259.07:20:02.02#antcn#PM 2 -0.0279715 0.0000000 -0.0282214 -0.0241630 -0.0014011 2006.259.07:20:02.02#antcn#PM 3 -0.0059899 0.0042895 -0.0643783 0.0000000 0.0000000 2006.259.07:20:02.02#antcn#PM 4 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.259.07:20:02.02#antcn#PM 5 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.259.07:20:03.14:ready_k5 2006.259.07:20:03.14&ready_k5/obsinfo=st 2006.259.07:20:03.14&ready_k5/autoobs=1 2006.259.07:20:03.14&ready_k5/autoobs=2 2006.259.07:20:03.14&ready_k5/autoobs=3 2006.259.07:20:03.14&ready_k5/autoobs=4 2006.259.07:20:03.14&ready_k5/obsinfo 2006.259.07:20:03.14/obsinfo=st/error_log.tmp was not found (or not removed). 2006.259.07:20:03.15#flagr#flagr/antenna,new-source 2006.259.07:20:06.80/autoobs//k5ts1/ autoobs started! 2006.259.07:20:10.21/autoobs//k5ts2/ autoobs started! 2006.259.07:20:13.84/autoobs//k5ts3/ autoobs started! 2006.259.07:20:17.38/autoobs//k5ts4/ autoobs started! 2006.259.07:20:17.40/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.259.07:20:17.40:4f8m12a=1 2006.259.07:20:17.40&4f8m12a/xlog=on 2006.259.07:20:17.40&4f8m12a/echo=on 2006.259.07:20:17.40&4f8m12a/pcalon 2006.259.07:20:17.40&4f8m12a/"tpicd=stop 2006.259.07:20:17.40&4f8m12a/vc4f8 2006.259.07:20:17.40&4f8m12a/ifd4f 2006.259.07:20:17.40&4f8m12a/"form=m,16.000,1:2 2006.259.07:20:17.40&4f8m12a/"tpicd 2006.259.07:20:17.40&4f8m12a/echo=off 2006.259.07:20:17.40&4f8m12a/xlog=off 2006.259.07:20:17.40$4f8m12a/echo=on 2006.259.07:20:17.41$4f8m12a/pcalon 2006.259.07:20:17.41&pcalon/"no phase cal control is implemented here 2006.259.07:20:17.41$pcalon/"no phase cal control is implemented here 2006.259.07:20:17.41$4f8m12a/"tpicd=stop 2006.259.07:20:17.41$4f8m12a/vc4f8 2006.259.07:20:17.41&vc4f8/valo=1,532.99 2006.259.07:20:17.41&vc4f8/va=1,8 2006.259.07:20:17.41&vc4f8/valo=2,572.99 2006.259.07:20:17.41&vc4f8/va=2,7 2006.259.07:20:17.41&vc4f8/valo=3,672.99 2006.259.07:20:17.41&vc4f8/va=3,8 2006.259.07:20:17.41&vc4f8/valo=4,832.99 2006.259.07:20:17.41&vc4f8/va=4,7 2006.259.07:20:17.41&vc4f8/valo=5,652.99 2006.259.07:20:17.41&vc4f8/va=5,7 2006.259.07:20:17.41&vc4f8/valo=6,772.99 2006.259.07:20:17.41&vc4f8/va=6,6 2006.259.07:20:17.41&vc4f8/valo=7,832.99 2006.259.07:20:17.41&vc4f8/va=7,6 2006.259.07:20:17.41&vc4f8/valo=8,852.99 2006.259.07:20:17.41&vc4f8/va=8,6 2006.259.07:20:17.41&vc4f8/vblo=1,632.99 2006.259.07:20:17.41&vc4f8/vb=1,4 2006.259.07:20:17.41&vc4f8/vblo=2,640.99 2006.259.07:20:17.41&vc4f8/vb=2,5 2006.259.07:20:17.41&vc4f8/vblo=3,656.99 2006.259.07:20:17.41&vc4f8/vb=3,4 2006.259.07:20:17.41&vc4f8/vblo=4,712.99 2006.259.07:20:17.41&vc4f8/vb=4,5 2006.259.07:20:17.41&vc4f8/vblo=5,744.99 2006.259.07:20:17.41&vc4f8/vb=5,4 2006.259.07:20:17.41&vc4f8/vblo=6,752.99 2006.259.07:20:17.41&vc4f8/vb=6,4 2006.259.07:20:17.41&vc4f8/vabw=wide 2006.259.07:20:17.41&vc4f8/vbbw=wide 2006.259.07:20:17.41$vc4f8/valo=1,532.99 2006.259.07:20:17.41#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.259.07:20:17.41#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.259.07:20:17.41#ibcon#ireg 17 cls_cnt 0 2006.259.07:20:17.41#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.259.07:20:17.41#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.259.07:20:17.41#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.259.07:20:17.41#ibcon#enter wrdev, iclass 36, count 0 2006.259.07:20:17.41#ibcon#first serial, iclass 36, count 0 2006.259.07:20:17.41#ibcon#enter sib2, iclass 36, count 0 2006.259.07:20:17.41#ibcon#flushed, iclass 36, count 0 2006.259.07:20:17.41#ibcon#about to write, iclass 36, count 0 2006.259.07:20:17.41#ibcon#wrote, iclass 36, count 0 2006.259.07:20:17.41#ibcon#about to read 3, iclass 36, count 0 2006.259.07:20:17.45#ibcon#read 3, iclass 36, count 0 2006.259.07:20:17.45#ibcon#about to read 4, iclass 36, count 0 2006.259.07:20:17.45#ibcon#read 4, iclass 36, count 0 2006.259.07:20:17.45#ibcon#about to read 5, iclass 36, count 0 2006.259.07:20:17.45#ibcon#read 5, iclass 36, count 0 2006.259.07:20:17.45#ibcon#about to read 6, iclass 36, count 0 2006.259.07:20:17.45#ibcon#read 6, iclass 36, count 0 2006.259.07:20:17.45#ibcon#end of sib2, iclass 36, count 0 2006.259.07:20:17.45#ibcon#*mode == 0, iclass 36, count 0 2006.259.07:20:17.45#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.259.07:20:17.45#ibcon#[26=FRQ=01,532.99\r\n] 2006.259.07:20:17.45#ibcon#*before write, iclass 36, count 0 2006.259.07:20:17.45#ibcon#enter sib2, iclass 36, count 0 2006.259.07:20:17.45#ibcon#flushed, iclass 36, count 0 2006.259.07:20:17.45#ibcon#about to write, iclass 36, count 0 2006.259.07:20:17.45#ibcon#wrote, iclass 36, count 0 2006.259.07:20:17.45#ibcon#about to read 3, iclass 36, count 0 2006.259.07:20:17.51#ibcon#read 3, iclass 36, count 0 2006.259.07:20:17.51#ibcon#about to read 4, iclass 36, count 0 2006.259.07:20:17.51#ibcon#read 4, iclass 36, count 0 2006.259.07:20:17.51#ibcon#about to read 5, iclass 36, count 0 2006.259.07:20:17.51#ibcon#read 5, iclass 36, count 0 2006.259.07:20:17.51#ibcon#about to read 6, iclass 36, count 0 2006.259.07:20:17.51#ibcon#read 6, iclass 36, count 0 2006.259.07:20:17.51#ibcon#end of sib2, iclass 36, count 0 2006.259.07:20:17.51#ibcon#*after write, iclass 36, count 0 2006.259.07:20:17.51#ibcon#*before return 0, iclass 36, count 0 2006.259.07:20:17.51#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.259.07:20:17.51#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.259.07:20:17.51#ibcon#about to clear, iclass 36 cls_cnt 0 2006.259.07:20:17.51#ibcon#cleared, iclass 36 cls_cnt 0 2006.259.07:20:17.51$vc4f8/va=1,8 2006.259.07:20:17.51#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.259.07:20:17.51#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.259.07:20:17.51#ibcon#ireg 11 cls_cnt 2 2006.259.07:20:17.51#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.259.07:20:17.51#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.259.07:20:17.51#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.259.07:20:17.51#ibcon#enter wrdev, iclass 38, count 2 2006.259.07:20:17.51#ibcon#first serial, iclass 38, count 2 2006.259.07:20:17.51#ibcon#enter sib2, iclass 38, count 2 2006.259.07:20:17.51#ibcon#flushed, iclass 38, count 2 2006.259.07:20:17.51#ibcon#about to write, iclass 38, count 2 2006.259.07:20:17.51#ibcon#wrote, iclass 38, count 2 2006.259.07:20:17.51#ibcon#about to read 3, iclass 38, count 2 2006.259.07:20:17.53#ibcon#read 3, iclass 38, count 2 2006.259.07:20:17.53#ibcon#about to read 4, iclass 38, count 2 2006.259.07:20:17.53#ibcon#read 4, iclass 38, count 2 2006.259.07:20:17.53#ibcon#about to read 5, iclass 38, count 2 2006.259.07:20:17.53#ibcon#read 5, iclass 38, count 2 2006.259.07:20:17.53#ibcon#about to read 6, iclass 38, count 2 2006.259.07:20:17.53#ibcon#read 6, iclass 38, count 2 2006.259.07:20:17.53#ibcon#end of sib2, iclass 38, count 2 2006.259.07:20:17.53#ibcon#*mode == 0, iclass 38, count 2 2006.259.07:20:17.53#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.259.07:20:17.53#ibcon#[25=AT01-08\r\n] 2006.259.07:20:17.53#ibcon#*before write, iclass 38, count 2 2006.259.07:20:17.53#ibcon#enter sib2, iclass 38, count 2 2006.259.07:20:17.53#ibcon#flushed, iclass 38, count 2 2006.259.07:20:17.53#ibcon#about to write, iclass 38, count 2 2006.259.07:20:17.53#ibcon#wrote, iclass 38, count 2 2006.259.07:20:17.53#ibcon#about to read 3, iclass 38, count 2 2006.259.07:20:17.57#ibcon#read 3, iclass 38, count 2 2006.259.07:20:17.57#ibcon#about to read 4, iclass 38, count 2 2006.259.07:20:17.57#ibcon#read 4, iclass 38, count 2 2006.259.07:20:17.57#ibcon#about to read 5, iclass 38, count 2 2006.259.07:20:17.57#ibcon#read 5, iclass 38, count 2 2006.259.07:20:17.57#ibcon#about to read 6, iclass 38, count 2 2006.259.07:20:17.57#ibcon#read 6, iclass 38, count 2 2006.259.07:20:17.57#ibcon#end of sib2, iclass 38, count 2 2006.259.07:20:17.57#ibcon#*after write, iclass 38, count 2 2006.259.07:20:17.57#ibcon#*before return 0, iclass 38, count 2 2006.259.07:20:17.57#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.259.07:20:17.57#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.259.07:20:17.57#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.259.07:20:17.57#ibcon#ireg 7 cls_cnt 0 2006.259.07:20:17.57#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.259.07:20:17.69#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.259.07:20:17.69#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.259.07:20:17.69#ibcon#enter wrdev, iclass 38, count 0 2006.259.07:20:17.69#ibcon#first serial, iclass 38, count 0 2006.259.07:20:17.69#ibcon#enter sib2, iclass 38, count 0 2006.259.07:20:17.69#ibcon#flushed, iclass 38, count 0 2006.259.07:20:17.69#ibcon#about to write, iclass 38, count 0 2006.259.07:20:17.69#ibcon#wrote, iclass 38, count 0 2006.259.07:20:17.69#ibcon#about to read 3, iclass 38, count 0 2006.259.07:20:17.71#ibcon#read 3, iclass 38, count 0 2006.259.07:20:17.71#ibcon#about to read 4, iclass 38, count 0 2006.259.07:20:17.71#ibcon#read 4, iclass 38, count 0 2006.259.07:20:17.71#ibcon#about to read 5, iclass 38, count 0 2006.259.07:20:17.71#ibcon#read 5, iclass 38, count 0 2006.259.07:20:17.71#ibcon#about to read 6, iclass 38, count 0 2006.259.07:20:17.71#ibcon#read 6, iclass 38, count 0 2006.259.07:20:17.71#ibcon#end of sib2, iclass 38, count 0 2006.259.07:20:17.71#ibcon#*mode == 0, iclass 38, count 0 2006.259.07:20:17.71#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.259.07:20:17.71#ibcon#[25=USB\r\n] 2006.259.07:20:17.71#ibcon#*before write, iclass 38, count 0 2006.259.07:20:17.71#ibcon#enter sib2, iclass 38, count 0 2006.259.07:20:17.71#ibcon#flushed, iclass 38, count 0 2006.259.07:20:17.71#ibcon#about to write, iclass 38, count 0 2006.259.07:20:17.71#ibcon#wrote, iclass 38, count 0 2006.259.07:20:17.71#ibcon#about to read 3, iclass 38, count 0 2006.259.07:20:17.74#ibcon#read 3, iclass 38, count 0 2006.259.07:20:17.74#ibcon#about to read 4, iclass 38, count 0 2006.259.07:20:17.74#ibcon#read 4, iclass 38, count 0 2006.259.07:20:17.74#ibcon#about to read 5, iclass 38, count 0 2006.259.07:20:17.74#ibcon#read 5, iclass 38, count 0 2006.259.07:20:17.74#ibcon#about to read 6, iclass 38, count 0 2006.259.07:20:17.74#ibcon#read 6, iclass 38, count 0 2006.259.07:20:17.74#ibcon#end of sib2, iclass 38, count 0 2006.259.07:20:17.74#ibcon#*after write, iclass 38, count 0 2006.259.07:20:17.74#ibcon#*before return 0, iclass 38, count 0 2006.259.07:20:17.74#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.259.07:20:17.74#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.259.07:20:17.74#ibcon#about to clear, iclass 38 cls_cnt 0 2006.259.07:20:17.74#ibcon#cleared, iclass 38 cls_cnt 0 2006.259.07:20:17.74$vc4f8/valo=2,572.99 2006.259.07:20:17.74#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.259.07:20:17.74#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.259.07:20:17.74#ibcon#ireg 17 cls_cnt 0 2006.259.07:20:17.74#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.259.07:20:17.74#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.259.07:20:17.74#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.259.07:20:17.74#ibcon#enter wrdev, iclass 40, count 0 2006.259.07:20:17.74#ibcon#first serial, iclass 40, count 0 2006.259.07:20:17.74#ibcon#enter sib2, iclass 40, count 0 2006.259.07:20:17.74#ibcon#flushed, iclass 40, count 0 2006.259.07:20:17.74#ibcon#about to write, iclass 40, count 0 2006.259.07:20:17.74#ibcon#wrote, iclass 40, count 0 2006.259.07:20:17.74#ibcon#about to read 3, iclass 40, count 0 2006.259.07:20:17.76#ibcon#read 3, iclass 40, count 0 2006.259.07:20:17.76#ibcon#about to read 4, iclass 40, count 0 2006.259.07:20:17.76#ibcon#read 4, iclass 40, count 0 2006.259.07:20:17.76#ibcon#about to read 5, iclass 40, count 0 2006.259.07:20:17.76#ibcon#read 5, iclass 40, count 0 2006.259.07:20:17.76#ibcon#about to read 6, iclass 40, count 0 2006.259.07:20:17.76#ibcon#read 6, iclass 40, count 0 2006.259.07:20:17.76#ibcon#end of sib2, iclass 40, count 0 2006.259.07:20:17.76#ibcon#*mode == 0, iclass 40, count 0 2006.259.07:20:17.76#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.259.07:20:17.76#ibcon#[26=FRQ=02,572.99\r\n] 2006.259.07:20:17.76#ibcon#*before write, iclass 40, count 0 2006.259.07:20:17.76#ibcon#enter sib2, iclass 40, count 0 2006.259.07:20:17.76#ibcon#flushed, iclass 40, count 0 2006.259.07:20:17.76#ibcon#about to write, iclass 40, count 0 2006.259.07:20:17.76#ibcon#wrote, iclass 40, count 0 2006.259.07:20:17.76#ibcon#about to read 3, iclass 40, count 0 2006.259.07:20:17.80#ibcon#read 3, iclass 40, count 0 2006.259.07:20:17.80#ibcon#about to read 4, iclass 40, count 0 2006.259.07:20:17.80#ibcon#read 4, iclass 40, count 0 2006.259.07:20:17.80#ibcon#about to read 5, iclass 40, count 0 2006.259.07:20:17.80#ibcon#read 5, iclass 40, count 0 2006.259.07:20:17.80#ibcon#about to read 6, iclass 40, count 0 2006.259.07:20:17.80#ibcon#read 6, iclass 40, count 0 2006.259.07:20:17.80#ibcon#end of sib2, iclass 40, count 0 2006.259.07:20:17.80#ibcon#*after write, iclass 40, count 0 2006.259.07:20:17.80#ibcon#*before return 0, iclass 40, count 0 2006.259.07:20:17.80#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.259.07:20:17.80#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.259.07:20:17.80#ibcon#about to clear, iclass 40 cls_cnt 0 2006.259.07:20:17.80#ibcon#cleared, iclass 40 cls_cnt 0 2006.259.07:20:17.80$vc4f8/va=2,7 2006.259.07:20:17.80#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.259.07:20:17.80#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.259.07:20:17.80#ibcon#ireg 11 cls_cnt 2 2006.259.07:20:17.80#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.259.07:20:17.87#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.259.07:20:17.87#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.259.07:20:17.87#ibcon#enter wrdev, iclass 4, count 2 2006.259.07:20:17.87#ibcon#first serial, iclass 4, count 2 2006.259.07:20:17.87#ibcon#enter sib2, iclass 4, count 2 2006.259.07:20:17.87#ibcon#flushed, iclass 4, count 2 2006.259.07:20:17.87#ibcon#about to write, iclass 4, count 2 2006.259.07:20:17.87#ibcon#wrote, iclass 4, count 2 2006.259.07:20:17.87#ibcon#about to read 3, iclass 4, count 2 2006.259.07:20:17.89#ibcon#read 3, iclass 4, count 2 2006.259.07:20:17.89#ibcon#about to read 4, iclass 4, count 2 2006.259.07:20:17.89#ibcon#read 4, iclass 4, count 2 2006.259.07:20:17.89#ibcon#about to read 5, iclass 4, count 2 2006.259.07:20:17.89#ibcon#read 5, iclass 4, count 2 2006.259.07:20:17.89#ibcon#about to read 6, iclass 4, count 2 2006.259.07:20:17.89#ibcon#read 6, iclass 4, count 2 2006.259.07:20:17.89#ibcon#end of sib2, iclass 4, count 2 2006.259.07:20:17.89#ibcon#*mode == 0, iclass 4, count 2 2006.259.07:20:17.89#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.259.07:20:17.89#ibcon#[25=AT02-07\r\n] 2006.259.07:20:17.89#ibcon#*before write, iclass 4, count 2 2006.259.07:20:17.89#ibcon#enter sib2, iclass 4, count 2 2006.259.07:20:17.89#ibcon#flushed, iclass 4, count 2 2006.259.07:20:17.89#ibcon#about to write, iclass 4, count 2 2006.259.07:20:17.89#ibcon#wrote, iclass 4, count 2 2006.259.07:20:17.89#ibcon#about to read 3, iclass 4, count 2 2006.259.07:20:17.91#ibcon#read 3, iclass 4, count 2 2006.259.07:20:17.91#ibcon#about to read 4, iclass 4, count 2 2006.259.07:20:17.91#ibcon#read 4, iclass 4, count 2 2006.259.07:20:17.91#ibcon#about to read 5, iclass 4, count 2 2006.259.07:20:17.91#ibcon#read 5, iclass 4, count 2 2006.259.07:20:17.91#ibcon#about to read 6, iclass 4, count 2 2006.259.07:20:17.91#ibcon#read 6, iclass 4, count 2 2006.259.07:20:17.91#ibcon#end of sib2, iclass 4, count 2 2006.259.07:20:17.91#ibcon#*after write, iclass 4, count 2 2006.259.07:20:17.91#ibcon#*before return 0, iclass 4, count 2 2006.259.07:20:17.91#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.259.07:20:17.91#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.259.07:20:17.91#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.259.07:20:17.91#ibcon#ireg 7 cls_cnt 0 2006.259.07:20:17.91#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.259.07:20:18.03#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.259.07:20:18.03#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.259.07:20:18.03#ibcon#enter wrdev, iclass 4, count 0 2006.259.07:20:18.03#ibcon#first serial, iclass 4, count 0 2006.259.07:20:18.03#ibcon#enter sib2, iclass 4, count 0 2006.259.07:20:18.03#ibcon#flushed, iclass 4, count 0 2006.259.07:20:18.03#ibcon#about to write, iclass 4, count 0 2006.259.07:20:18.03#ibcon#wrote, iclass 4, count 0 2006.259.07:20:18.03#ibcon#about to read 3, iclass 4, count 0 2006.259.07:20:18.05#ibcon#read 3, iclass 4, count 0 2006.259.07:20:18.05#ibcon#about to read 4, iclass 4, count 0 2006.259.07:20:18.05#ibcon#read 4, iclass 4, count 0 2006.259.07:20:18.05#ibcon#about to read 5, iclass 4, count 0 2006.259.07:20:18.05#ibcon#read 5, iclass 4, count 0 2006.259.07:20:18.05#ibcon#about to read 6, iclass 4, count 0 2006.259.07:20:18.05#ibcon#read 6, iclass 4, count 0 2006.259.07:20:18.05#ibcon#end of sib2, iclass 4, count 0 2006.259.07:20:18.05#ibcon#*mode == 0, iclass 4, count 0 2006.259.07:20:18.05#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.259.07:20:18.05#ibcon#[25=USB\r\n] 2006.259.07:20:18.05#ibcon#*before write, iclass 4, count 0 2006.259.07:20:18.05#ibcon#enter sib2, iclass 4, count 0 2006.259.07:20:18.05#ibcon#flushed, iclass 4, count 0 2006.259.07:20:18.05#ibcon#about to write, iclass 4, count 0 2006.259.07:20:18.05#ibcon#wrote, iclass 4, count 0 2006.259.07:20:18.05#ibcon#about to read 3, iclass 4, count 0 2006.259.07:20:18.08#ibcon#read 3, iclass 4, count 0 2006.259.07:20:18.08#ibcon#about to read 4, iclass 4, count 0 2006.259.07:20:18.08#ibcon#read 4, iclass 4, count 0 2006.259.07:20:18.08#ibcon#about to read 5, iclass 4, count 0 2006.259.07:20:18.08#ibcon#read 5, iclass 4, count 0 2006.259.07:20:18.08#ibcon#about to read 6, iclass 4, count 0 2006.259.07:20:18.08#ibcon#read 6, iclass 4, count 0 2006.259.07:20:18.08#ibcon#end of sib2, iclass 4, count 0 2006.259.07:20:18.08#ibcon#*after write, iclass 4, count 0 2006.259.07:20:18.08#ibcon#*before return 0, iclass 4, count 0 2006.259.07:20:18.08#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.259.07:20:18.08#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.259.07:20:18.08#ibcon#about to clear, iclass 4 cls_cnt 0 2006.259.07:20:18.08#ibcon#cleared, iclass 4 cls_cnt 0 2006.259.07:20:18.08$vc4f8/valo=3,672.99 2006.259.07:20:18.08#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.259.07:20:18.08#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.259.07:20:18.08#ibcon#ireg 17 cls_cnt 0 2006.259.07:20:18.08#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.259.07:20:18.08#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.259.07:20:18.08#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.259.07:20:18.08#ibcon#enter wrdev, iclass 6, count 0 2006.259.07:20:18.08#ibcon#first serial, iclass 6, count 0 2006.259.07:20:18.08#ibcon#enter sib2, iclass 6, count 0 2006.259.07:20:18.08#ibcon#flushed, iclass 6, count 0 2006.259.07:20:18.08#ibcon#about to write, iclass 6, count 0 2006.259.07:20:18.08#ibcon#wrote, iclass 6, count 0 2006.259.07:20:18.08#ibcon#about to read 3, iclass 6, count 0 2006.259.07:20:18.10#ibcon#read 3, iclass 6, count 0 2006.259.07:20:18.10#ibcon#about to read 4, iclass 6, count 0 2006.259.07:20:18.10#ibcon#read 4, iclass 6, count 0 2006.259.07:20:18.10#ibcon#about to read 5, iclass 6, count 0 2006.259.07:20:18.10#ibcon#read 5, iclass 6, count 0 2006.259.07:20:18.10#ibcon#about to read 6, iclass 6, count 0 2006.259.07:20:18.10#ibcon#read 6, iclass 6, count 0 2006.259.07:20:18.10#ibcon#end of sib2, iclass 6, count 0 2006.259.07:20:18.10#ibcon#*mode == 0, iclass 6, count 0 2006.259.07:20:18.10#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.259.07:20:18.10#ibcon#[26=FRQ=03,672.99\r\n] 2006.259.07:20:18.10#ibcon#*before write, iclass 6, count 0 2006.259.07:20:18.10#ibcon#enter sib2, iclass 6, count 0 2006.259.07:20:18.10#ibcon#flushed, iclass 6, count 0 2006.259.07:20:18.10#ibcon#about to write, iclass 6, count 0 2006.259.07:20:18.10#ibcon#wrote, iclass 6, count 0 2006.259.07:20:18.10#ibcon#about to read 3, iclass 6, count 0 2006.259.07:20:18.14#ibcon#read 3, iclass 6, count 0 2006.259.07:20:18.14#ibcon#about to read 4, iclass 6, count 0 2006.259.07:20:18.14#ibcon#read 4, iclass 6, count 0 2006.259.07:20:18.14#ibcon#about to read 5, iclass 6, count 0 2006.259.07:20:18.14#ibcon#read 5, iclass 6, count 0 2006.259.07:20:18.14#ibcon#about to read 6, iclass 6, count 0 2006.259.07:20:18.14#ibcon#read 6, iclass 6, count 0 2006.259.07:20:18.14#ibcon#end of sib2, iclass 6, count 0 2006.259.07:20:18.14#ibcon#*after write, iclass 6, count 0 2006.259.07:20:18.14#ibcon#*before return 0, iclass 6, count 0 2006.259.07:20:18.14#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.259.07:20:18.14#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.259.07:20:18.14#ibcon#about to clear, iclass 6 cls_cnt 0 2006.259.07:20:18.14#ibcon#cleared, iclass 6 cls_cnt 0 2006.259.07:20:18.14$vc4f8/va=3,8 2006.259.07:20:18.14#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.259.07:20:18.14#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.259.07:20:18.14#ibcon#ireg 11 cls_cnt 2 2006.259.07:20:18.14#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.259.07:20:18.20#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.259.07:20:18.20#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.259.07:20:18.20#ibcon#enter wrdev, iclass 10, count 2 2006.259.07:20:18.20#ibcon#first serial, iclass 10, count 2 2006.259.07:20:18.20#ibcon#enter sib2, iclass 10, count 2 2006.259.07:20:18.20#ibcon#flushed, iclass 10, count 2 2006.259.07:20:18.20#ibcon#about to write, iclass 10, count 2 2006.259.07:20:18.20#ibcon#wrote, iclass 10, count 2 2006.259.07:20:18.20#ibcon#about to read 3, iclass 10, count 2 2006.259.07:20:18.22#ibcon#read 3, iclass 10, count 2 2006.259.07:20:18.22#ibcon#about to read 4, iclass 10, count 2 2006.259.07:20:18.22#ibcon#read 4, iclass 10, count 2 2006.259.07:20:18.22#ibcon#about to read 5, iclass 10, count 2 2006.259.07:20:18.22#ibcon#read 5, iclass 10, count 2 2006.259.07:20:18.22#ibcon#about to read 6, iclass 10, count 2 2006.259.07:20:18.22#ibcon#read 6, iclass 10, count 2 2006.259.07:20:18.22#ibcon#end of sib2, iclass 10, count 2 2006.259.07:20:18.22#ibcon#*mode == 0, iclass 10, count 2 2006.259.07:20:18.22#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.259.07:20:18.22#ibcon#[25=AT03-08\r\n] 2006.259.07:20:18.22#ibcon#*before write, iclass 10, count 2 2006.259.07:20:18.22#ibcon#enter sib2, iclass 10, count 2 2006.259.07:20:18.22#ibcon#flushed, iclass 10, count 2 2006.259.07:20:18.22#ibcon#about to write, iclass 10, count 2 2006.259.07:20:18.22#ibcon#wrote, iclass 10, count 2 2006.259.07:20:18.22#ibcon#about to read 3, iclass 10, count 2 2006.259.07:20:18.25#ibcon#read 3, iclass 10, count 2 2006.259.07:20:18.25#ibcon#about to read 4, iclass 10, count 2 2006.259.07:20:18.25#ibcon#read 4, iclass 10, count 2 2006.259.07:20:18.25#ibcon#about to read 5, iclass 10, count 2 2006.259.07:20:18.25#ibcon#read 5, iclass 10, count 2 2006.259.07:20:18.25#ibcon#about to read 6, iclass 10, count 2 2006.259.07:20:18.25#ibcon#read 6, iclass 10, count 2 2006.259.07:20:18.25#ibcon#end of sib2, iclass 10, count 2 2006.259.07:20:18.25#ibcon#*after write, iclass 10, count 2 2006.259.07:20:18.25#ibcon#*before return 0, iclass 10, count 2 2006.259.07:20:18.25#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.259.07:20:18.25#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.259.07:20:18.25#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.259.07:20:18.25#ibcon#ireg 7 cls_cnt 0 2006.259.07:20:18.25#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.259.07:20:18.37#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.259.07:20:18.37#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.259.07:20:18.37#ibcon#enter wrdev, iclass 10, count 0 2006.259.07:20:18.37#ibcon#first serial, iclass 10, count 0 2006.259.07:20:18.37#ibcon#enter sib2, iclass 10, count 0 2006.259.07:20:18.37#ibcon#flushed, iclass 10, count 0 2006.259.07:20:18.37#ibcon#about to write, iclass 10, count 0 2006.259.07:20:18.37#ibcon#wrote, iclass 10, count 0 2006.259.07:20:18.37#ibcon#about to read 3, iclass 10, count 0 2006.259.07:20:18.39#ibcon#read 3, iclass 10, count 0 2006.259.07:20:18.39#ibcon#about to read 4, iclass 10, count 0 2006.259.07:20:18.39#ibcon#read 4, iclass 10, count 0 2006.259.07:20:18.39#ibcon#about to read 5, iclass 10, count 0 2006.259.07:20:18.39#ibcon#read 5, iclass 10, count 0 2006.259.07:20:18.39#ibcon#about to read 6, iclass 10, count 0 2006.259.07:20:18.39#ibcon#read 6, iclass 10, count 0 2006.259.07:20:18.39#ibcon#end of sib2, iclass 10, count 0 2006.259.07:20:18.39#ibcon#*mode == 0, iclass 10, count 0 2006.259.07:20:18.39#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.259.07:20:18.39#ibcon#[25=USB\r\n] 2006.259.07:20:18.39#ibcon#*before write, iclass 10, count 0 2006.259.07:20:18.39#ibcon#enter sib2, iclass 10, count 0 2006.259.07:20:18.39#ibcon#flushed, iclass 10, count 0 2006.259.07:20:18.39#ibcon#about to write, iclass 10, count 0 2006.259.07:20:18.39#ibcon#wrote, iclass 10, count 0 2006.259.07:20:18.39#ibcon#about to read 3, iclass 10, count 0 2006.259.07:20:18.42#ibcon#read 3, iclass 10, count 0 2006.259.07:20:18.42#ibcon#about to read 4, iclass 10, count 0 2006.259.07:20:18.42#ibcon#read 4, iclass 10, count 0 2006.259.07:20:18.42#ibcon#about to read 5, iclass 10, count 0 2006.259.07:20:18.42#ibcon#read 5, iclass 10, count 0 2006.259.07:20:18.42#ibcon#about to read 6, iclass 10, count 0 2006.259.07:20:18.42#ibcon#read 6, iclass 10, count 0 2006.259.07:20:18.42#ibcon#end of sib2, iclass 10, count 0 2006.259.07:20:18.42#ibcon#*after write, iclass 10, count 0 2006.259.07:20:18.42#ibcon#*before return 0, iclass 10, count 0 2006.259.07:20:18.42#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.259.07:20:18.42#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.259.07:20:18.42#ibcon#about to clear, iclass 10 cls_cnt 0 2006.259.07:20:18.42#ibcon#cleared, iclass 10 cls_cnt 0 2006.259.07:20:18.42$vc4f8/valo=4,832.99 2006.259.07:20:18.42#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.259.07:20:18.42#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.259.07:20:18.42#ibcon#ireg 17 cls_cnt 0 2006.259.07:20:18.42#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.259.07:20:18.42#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.259.07:20:18.42#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.259.07:20:18.42#ibcon#enter wrdev, iclass 12, count 0 2006.259.07:20:18.42#ibcon#first serial, iclass 12, count 0 2006.259.07:20:18.42#ibcon#enter sib2, iclass 12, count 0 2006.259.07:20:18.42#ibcon#flushed, iclass 12, count 0 2006.259.07:20:18.42#ibcon#about to write, iclass 12, count 0 2006.259.07:20:18.42#ibcon#wrote, iclass 12, count 0 2006.259.07:20:18.42#ibcon#about to read 3, iclass 12, count 0 2006.259.07:20:18.44#ibcon#read 3, iclass 12, count 0 2006.259.07:20:18.44#ibcon#about to read 4, iclass 12, count 0 2006.259.07:20:18.44#ibcon#read 4, iclass 12, count 0 2006.259.07:20:18.44#ibcon#about to read 5, iclass 12, count 0 2006.259.07:20:18.44#ibcon#read 5, iclass 12, count 0 2006.259.07:20:18.44#ibcon#about to read 6, iclass 12, count 0 2006.259.07:20:18.44#ibcon#read 6, iclass 12, count 0 2006.259.07:20:18.44#ibcon#end of sib2, iclass 12, count 0 2006.259.07:20:18.44#ibcon#*mode == 0, iclass 12, count 0 2006.259.07:20:18.44#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.259.07:20:18.44#ibcon#[26=FRQ=04,832.99\r\n] 2006.259.07:20:18.44#ibcon#*before write, iclass 12, count 0 2006.259.07:20:18.44#ibcon#enter sib2, iclass 12, count 0 2006.259.07:20:18.44#ibcon#flushed, iclass 12, count 0 2006.259.07:20:18.44#ibcon#about to write, iclass 12, count 0 2006.259.07:20:18.44#ibcon#wrote, iclass 12, count 0 2006.259.07:20:18.44#ibcon#about to read 3, iclass 12, count 0 2006.259.07:20:18.48#ibcon#read 3, iclass 12, count 0 2006.259.07:20:18.48#ibcon#about to read 4, iclass 12, count 0 2006.259.07:20:18.48#ibcon#read 4, iclass 12, count 0 2006.259.07:20:18.48#ibcon#about to read 5, iclass 12, count 0 2006.259.07:20:18.48#ibcon#read 5, iclass 12, count 0 2006.259.07:20:18.48#ibcon#about to read 6, iclass 12, count 0 2006.259.07:20:18.48#ibcon#read 6, iclass 12, count 0 2006.259.07:20:18.48#ibcon#end of sib2, iclass 12, count 0 2006.259.07:20:18.48#ibcon#*after write, iclass 12, count 0 2006.259.07:20:18.48#ibcon#*before return 0, iclass 12, count 0 2006.259.07:20:18.48#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.259.07:20:18.48#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.259.07:20:18.48#ibcon#about to clear, iclass 12 cls_cnt 0 2006.259.07:20:18.48#ibcon#cleared, iclass 12 cls_cnt 0 2006.259.07:20:18.48$vc4f8/va=4,7 2006.259.07:20:18.48#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.259.07:20:18.48#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.259.07:20:18.48#ibcon#ireg 11 cls_cnt 2 2006.259.07:20:18.48#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.259.07:20:18.54#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.259.07:20:18.54#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.259.07:20:18.54#ibcon#enter wrdev, iclass 14, count 2 2006.259.07:20:18.54#ibcon#first serial, iclass 14, count 2 2006.259.07:20:18.54#ibcon#enter sib2, iclass 14, count 2 2006.259.07:20:18.54#ibcon#flushed, iclass 14, count 2 2006.259.07:20:18.54#ibcon#about to write, iclass 14, count 2 2006.259.07:20:18.54#ibcon#wrote, iclass 14, count 2 2006.259.07:20:18.54#ibcon#about to read 3, iclass 14, count 2 2006.259.07:20:18.56#ibcon#read 3, iclass 14, count 2 2006.259.07:20:18.56#ibcon#about to read 4, iclass 14, count 2 2006.259.07:20:18.56#ibcon#read 4, iclass 14, count 2 2006.259.07:20:18.56#ibcon#about to read 5, iclass 14, count 2 2006.259.07:20:18.56#ibcon#read 5, iclass 14, count 2 2006.259.07:20:18.56#ibcon#about to read 6, iclass 14, count 2 2006.259.07:20:18.56#ibcon#read 6, iclass 14, count 2 2006.259.07:20:18.56#ibcon#end of sib2, iclass 14, count 2 2006.259.07:20:18.56#ibcon#*mode == 0, iclass 14, count 2 2006.259.07:20:18.56#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.259.07:20:18.56#ibcon#[25=AT04-07\r\n] 2006.259.07:20:18.56#ibcon#*before write, iclass 14, count 2 2006.259.07:20:18.56#ibcon#enter sib2, iclass 14, count 2 2006.259.07:20:18.56#ibcon#flushed, iclass 14, count 2 2006.259.07:20:18.56#ibcon#about to write, iclass 14, count 2 2006.259.07:20:18.56#ibcon#wrote, iclass 14, count 2 2006.259.07:20:18.56#ibcon#about to read 3, iclass 14, count 2 2006.259.07:20:18.59#ibcon#read 3, iclass 14, count 2 2006.259.07:20:18.59#ibcon#about to read 4, iclass 14, count 2 2006.259.07:20:18.59#ibcon#read 4, iclass 14, count 2 2006.259.07:20:18.59#ibcon#about to read 5, iclass 14, count 2 2006.259.07:20:18.59#ibcon#read 5, iclass 14, count 2 2006.259.07:20:18.59#ibcon#about to read 6, iclass 14, count 2 2006.259.07:20:18.59#ibcon#read 6, iclass 14, count 2 2006.259.07:20:18.59#ibcon#end of sib2, iclass 14, count 2 2006.259.07:20:18.59#ibcon#*after write, iclass 14, count 2 2006.259.07:20:18.59#ibcon#*before return 0, iclass 14, count 2 2006.259.07:20:18.59#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.259.07:20:18.59#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.259.07:20:18.59#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.259.07:20:18.59#ibcon#ireg 7 cls_cnt 0 2006.259.07:20:18.59#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.259.07:20:18.71#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.259.07:20:18.71#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.259.07:20:18.71#ibcon#enter wrdev, iclass 14, count 0 2006.259.07:20:18.71#ibcon#first serial, iclass 14, count 0 2006.259.07:20:18.71#ibcon#enter sib2, iclass 14, count 0 2006.259.07:20:18.71#ibcon#flushed, iclass 14, count 0 2006.259.07:20:18.71#ibcon#about to write, iclass 14, count 0 2006.259.07:20:18.71#ibcon#wrote, iclass 14, count 0 2006.259.07:20:18.71#ibcon#about to read 3, iclass 14, count 0 2006.259.07:20:18.73#ibcon#read 3, iclass 14, count 0 2006.259.07:20:18.73#ibcon#about to read 4, iclass 14, count 0 2006.259.07:20:18.73#ibcon#read 4, iclass 14, count 0 2006.259.07:20:18.73#ibcon#about to read 5, iclass 14, count 0 2006.259.07:20:18.73#ibcon#read 5, iclass 14, count 0 2006.259.07:20:18.73#ibcon#about to read 6, iclass 14, count 0 2006.259.07:20:18.73#ibcon#read 6, iclass 14, count 0 2006.259.07:20:18.73#ibcon#end of sib2, iclass 14, count 0 2006.259.07:20:18.73#ibcon#*mode == 0, iclass 14, count 0 2006.259.07:20:18.73#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.259.07:20:18.73#ibcon#[25=USB\r\n] 2006.259.07:20:18.73#ibcon#*before write, iclass 14, count 0 2006.259.07:20:18.73#ibcon#enter sib2, iclass 14, count 0 2006.259.07:20:18.73#ibcon#flushed, iclass 14, count 0 2006.259.07:20:18.73#ibcon#about to write, iclass 14, count 0 2006.259.07:20:18.73#ibcon#wrote, iclass 14, count 0 2006.259.07:20:18.73#ibcon#about to read 3, iclass 14, count 0 2006.259.07:20:18.76#ibcon#read 3, iclass 14, count 0 2006.259.07:20:18.76#ibcon#about to read 4, iclass 14, count 0 2006.259.07:20:18.76#ibcon#read 4, iclass 14, count 0 2006.259.07:20:18.76#ibcon#about to read 5, iclass 14, count 0 2006.259.07:20:18.76#ibcon#read 5, iclass 14, count 0 2006.259.07:20:18.76#ibcon#about to read 6, iclass 14, count 0 2006.259.07:20:18.76#ibcon#read 6, iclass 14, count 0 2006.259.07:20:18.76#ibcon#end of sib2, iclass 14, count 0 2006.259.07:20:18.76#ibcon#*after write, iclass 14, count 0 2006.259.07:20:18.76#ibcon#*before return 0, iclass 14, count 0 2006.259.07:20:18.76#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.259.07:20:18.76#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.259.07:20:18.76#ibcon#about to clear, iclass 14 cls_cnt 0 2006.259.07:20:18.76#ibcon#cleared, iclass 14 cls_cnt 0 2006.259.07:20:18.76$vc4f8/valo=5,652.99 2006.259.07:20:18.76#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.259.07:20:18.76#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.259.07:20:18.76#ibcon#ireg 17 cls_cnt 0 2006.259.07:20:18.76#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.259.07:20:18.76#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.259.07:20:18.76#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.259.07:20:18.76#ibcon#enter wrdev, iclass 16, count 0 2006.259.07:20:18.76#ibcon#first serial, iclass 16, count 0 2006.259.07:20:18.76#ibcon#enter sib2, iclass 16, count 0 2006.259.07:20:18.76#ibcon#flushed, iclass 16, count 0 2006.259.07:20:18.76#ibcon#about to write, iclass 16, count 0 2006.259.07:20:18.76#ibcon#wrote, iclass 16, count 0 2006.259.07:20:18.76#ibcon#about to read 3, iclass 16, count 0 2006.259.07:20:18.78#ibcon#read 3, iclass 16, count 0 2006.259.07:20:18.78#ibcon#about to read 4, iclass 16, count 0 2006.259.07:20:18.78#ibcon#read 4, iclass 16, count 0 2006.259.07:20:18.78#ibcon#about to read 5, iclass 16, count 0 2006.259.07:20:18.78#ibcon#read 5, iclass 16, count 0 2006.259.07:20:18.78#ibcon#about to read 6, iclass 16, count 0 2006.259.07:20:18.78#ibcon#read 6, iclass 16, count 0 2006.259.07:20:18.78#ibcon#end of sib2, iclass 16, count 0 2006.259.07:20:18.78#ibcon#*mode == 0, iclass 16, count 0 2006.259.07:20:18.78#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.259.07:20:18.78#ibcon#[26=FRQ=05,652.99\r\n] 2006.259.07:20:18.78#ibcon#*before write, iclass 16, count 0 2006.259.07:20:18.78#ibcon#enter sib2, iclass 16, count 0 2006.259.07:20:18.78#ibcon#flushed, iclass 16, count 0 2006.259.07:20:18.78#ibcon#about to write, iclass 16, count 0 2006.259.07:20:18.78#ibcon#wrote, iclass 16, count 0 2006.259.07:20:18.78#ibcon#about to read 3, iclass 16, count 0 2006.259.07:20:18.82#ibcon#read 3, iclass 16, count 0 2006.259.07:20:18.82#ibcon#about to read 4, iclass 16, count 0 2006.259.07:20:18.82#ibcon#read 4, iclass 16, count 0 2006.259.07:20:18.82#ibcon#about to read 5, iclass 16, count 0 2006.259.07:20:18.82#ibcon#read 5, iclass 16, count 0 2006.259.07:20:18.82#ibcon#about to read 6, iclass 16, count 0 2006.259.07:20:18.82#ibcon#read 6, iclass 16, count 0 2006.259.07:20:18.82#ibcon#end of sib2, iclass 16, count 0 2006.259.07:20:18.82#ibcon#*after write, iclass 16, count 0 2006.259.07:20:18.82#ibcon#*before return 0, iclass 16, count 0 2006.259.07:20:18.82#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.259.07:20:18.82#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.259.07:20:18.82#ibcon#about to clear, iclass 16 cls_cnt 0 2006.259.07:20:18.82#ibcon#cleared, iclass 16 cls_cnt 0 2006.259.07:20:18.82$vc4f8/va=5,7 2006.259.07:20:18.82#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.259.07:20:18.82#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.259.07:20:18.82#ibcon#ireg 11 cls_cnt 2 2006.259.07:20:18.82#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.259.07:20:18.88#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.259.07:20:18.88#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.259.07:20:18.88#ibcon#enter wrdev, iclass 18, count 2 2006.259.07:20:18.88#ibcon#first serial, iclass 18, count 2 2006.259.07:20:18.88#ibcon#enter sib2, iclass 18, count 2 2006.259.07:20:18.88#ibcon#flushed, iclass 18, count 2 2006.259.07:20:18.88#ibcon#about to write, iclass 18, count 2 2006.259.07:20:18.88#ibcon#wrote, iclass 18, count 2 2006.259.07:20:18.88#ibcon#about to read 3, iclass 18, count 2 2006.259.07:20:18.90#ibcon#read 3, iclass 18, count 2 2006.259.07:20:18.90#ibcon#about to read 4, iclass 18, count 2 2006.259.07:20:18.90#ibcon#read 4, iclass 18, count 2 2006.259.07:20:18.90#ibcon#about to read 5, iclass 18, count 2 2006.259.07:20:18.90#ibcon#read 5, iclass 18, count 2 2006.259.07:20:18.90#ibcon#about to read 6, iclass 18, count 2 2006.259.07:20:18.90#ibcon#read 6, iclass 18, count 2 2006.259.07:20:18.90#ibcon#end of sib2, iclass 18, count 2 2006.259.07:20:18.90#ibcon#*mode == 0, iclass 18, count 2 2006.259.07:20:18.90#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.259.07:20:18.90#ibcon#[25=AT05-07\r\n] 2006.259.07:20:18.90#ibcon#*before write, iclass 18, count 2 2006.259.07:20:18.90#ibcon#enter sib2, iclass 18, count 2 2006.259.07:20:18.90#ibcon#flushed, iclass 18, count 2 2006.259.07:20:18.90#ibcon#about to write, iclass 18, count 2 2006.259.07:20:18.90#ibcon#wrote, iclass 18, count 2 2006.259.07:20:18.90#ibcon#about to read 3, iclass 18, count 2 2006.259.07:20:18.93#ibcon#read 3, iclass 18, count 2 2006.259.07:20:18.93#ibcon#about to read 4, iclass 18, count 2 2006.259.07:20:18.93#ibcon#read 4, iclass 18, count 2 2006.259.07:20:18.93#ibcon#about to read 5, iclass 18, count 2 2006.259.07:20:18.93#ibcon#read 5, iclass 18, count 2 2006.259.07:20:18.93#ibcon#about to read 6, iclass 18, count 2 2006.259.07:20:18.93#ibcon#read 6, iclass 18, count 2 2006.259.07:20:18.93#ibcon#end of sib2, iclass 18, count 2 2006.259.07:20:18.93#ibcon#*after write, iclass 18, count 2 2006.259.07:20:18.93#ibcon#*before return 0, iclass 18, count 2 2006.259.07:20:18.93#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.259.07:20:18.93#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.259.07:20:18.93#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.259.07:20:18.93#ibcon#ireg 7 cls_cnt 0 2006.259.07:20:18.93#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.259.07:20:19.05#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.259.07:20:19.05#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.259.07:20:19.05#ibcon#enter wrdev, iclass 18, count 0 2006.259.07:20:19.05#ibcon#first serial, iclass 18, count 0 2006.259.07:20:19.05#ibcon#enter sib2, iclass 18, count 0 2006.259.07:20:19.05#ibcon#flushed, iclass 18, count 0 2006.259.07:20:19.05#ibcon#about to write, iclass 18, count 0 2006.259.07:20:19.05#ibcon#wrote, iclass 18, count 0 2006.259.07:20:19.05#ibcon#about to read 3, iclass 18, count 0 2006.259.07:20:19.07#ibcon#read 3, iclass 18, count 0 2006.259.07:20:19.07#ibcon#about to read 4, iclass 18, count 0 2006.259.07:20:19.07#ibcon#read 4, iclass 18, count 0 2006.259.07:20:19.07#ibcon#about to read 5, iclass 18, count 0 2006.259.07:20:19.07#ibcon#read 5, iclass 18, count 0 2006.259.07:20:19.07#ibcon#about to read 6, iclass 18, count 0 2006.259.07:20:19.07#ibcon#read 6, iclass 18, count 0 2006.259.07:20:19.07#ibcon#end of sib2, iclass 18, count 0 2006.259.07:20:19.07#ibcon#*mode == 0, iclass 18, count 0 2006.259.07:20:19.07#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.259.07:20:19.07#ibcon#[25=USB\r\n] 2006.259.07:20:19.07#ibcon#*before write, iclass 18, count 0 2006.259.07:20:19.07#ibcon#enter sib2, iclass 18, count 0 2006.259.07:20:19.07#ibcon#flushed, iclass 18, count 0 2006.259.07:20:19.07#ibcon#about to write, iclass 18, count 0 2006.259.07:20:19.07#ibcon#wrote, iclass 18, count 0 2006.259.07:20:19.07#ibcon#about to read 3, iclass 18, count 0 2006.259.07:20:19.10#ibcon#read 3, iclass 18, count 0 2006.259.07:20:19.10#ibcon#about to read 4, iclass 18, count 0 2006.259.07:20:19.10#ibcon#read 4, iclass 18, count 0 2006.259.07:20:19.10#ibcon#about to read 5, iclass 18, count 0 2006.259.07:20:19.10#ibcon#read 5, iclass 18, count 0 2006.259.07:20:19.10#ibcon#about to read 6, iclass 18, count 0 2006.259.07:20:19.10#ibcon#read 6, iclass 18, count 0 2006.259.07:20:19.10#ibcon#end of sib2, iclass 18, count 0 2006.259.07:20:19.10#ibcon#*after write, iclass 18, count 0 2006.259.07:20:19.10#ibcon#*before return 0, iclass 18, count 0 2006.259.07:20:19.10#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.259.07:20:19.10#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.259.07:20:19.10#ibcon#about to clear, iclass 18 cls_cnt 0 2006.259.07:20:19.10#ibcon#cleared, iclass 18 cls_cnt 0 2006.259.07:20:19.10$vc4f8/valo=6,772.99 2006.259.07:20:19.10#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.259.07:20:19.10#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.259.07:20:19.10#ibcon#ireg 17 cls_cnt 0 2006.259.07:20:19.10#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.259.07:20:19.10#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.259.07:20:19.10#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.259.07:20:19.10#ibcon#enter wrdev, iclass 20, count 0 2006.259.07:20:19.10#ibcon#first serial, iclass 20, count 0 2006.259.07:20:19.10#ibcon#enter sib2, iclass 20, count 0 2006.259.07:20:19.10#ibcon#flushed, iclass 20, count 0 2006.259.07:20:19.10#ibcon#about to write, iclass 20, count 0 2006.259.07:20:19.10#ibcon#wrote, iclass 20, count 0 2006.259.07:20:19.10#ibcon#about to read 3, iclass 20, count 0 2006.259.07:20:19.12#ibcon#read 3, iclass 20, count 0 2006.259.07:20:19.12#ibcon#about to read 4, iclass 20, count 0 2006.259.07:20:19.12#ibcon#read 4, iclass 20, count 0 2006.259.07:20:19.12#ibcon#about to read 5, iclass 20, count 0 2006.259.07:20:19.12#ibcon#read 5, iclass 20, count 0 2006.259.07:20:19.12#ibcon#about to read 6, iclass 20, count 0 2006.259.07:20:19.12#ibcon#read 6, iclass 20, count 0 2006.259.07:20:19.12#ibcon#end of sib2, iclass 20, count 0 2006.259.07:20:19.12#ibcon#*mode == 0, iclass 20, count 0 2006.259.07:20:19.12#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.259.07:20:19.12#ibcon#[26=FRQ=06,772.99\r\n] 2006.259.07:20:19.12#ibcon#*before write, iclass 20, count 0 2006.259.07:20:19.12#ibcon#enter sib2, iclass 20, count 0 2006.259.07:20:19.12#ibcon#flushed, iclass 20, count 0 2006.259.07:20:19.12#ibcon#about to write, iclass 20, count 0 2006.259.07:20:19.12#ibcon#wrote, iclass 20, count 0 2006.259.07:20:19.12#ibcon#about to read 3, iclass 20, count 0 2006.259.07:20:19.16#ibcon#read 3, iclass 20, count 0 2006.259.07:20:19.16#ibcon#about to read 4, iclass 20, count 0 2006.259.07:20:19.16#ibcon#read 4, iclass 20, count 0 2006.259.07:20:19.16#ibcon#about to read 5, iclass 20, count 0 2006.259.07:20:19.16#ibcon#read 5, iclass 20, count 0 2006.259.07:20:19.16#ibcon#about to read 6, iclass 20, count 0 2006.259.07:20:19.16#ibcon#read 6, iclass 20, count 0 2006.259.07:20:19.16#ibcon#end of sib2, iclass 20, count 0 2006.259.07:20:19.16#ibcon#*after write, iclass 20, count 0 2006.259.07:20:19.16#ibcon#*before return 0, iclass 20, count 0 2006.259.07:20:19.16#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.259.07:20:19.16#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.259.07:20:19.16#ibcon#about to clear, iclass 20 cls_cnt 0 2006.259.07:20:19.16#ibcon#cleared, iclass 20 cls_cnt 0 2006.259.07:20:19.16$vc4f8/va=6,6 2006.259.07:20:19.16#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.259.07:20:19.16#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.259.07:20:19.16#ibcon#ireg 11 cls_cnt 2 2006.259.07:20:19.16#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.259.07:20:19.22#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.259.07:20:19.22#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.259.07:20:19.22#ibcon#enter wrdev, iclass 22, count 2 2006.259.07:20:19.22#ibcon#first serial, iclass 22, count 2 2006.259.07:20:19.22#ibcon#enter sib2, iclass 22, count 2 2006.259.07:20:19.22#ibcon#flushed, iclass 22, count 2 2006.259.07:20:19.22#ibcon#about to write, iclass 22, count 2 2006.259.07:20:19.22#ibcon#wrote, iclass 22, count 2 2006.259.07:20:19.22#ibcon#about to read 3, iclass 22, count 2 2006.259.07:20:19.24#ibcon#read 3, iclass 22, count 2 2006.259.07:20:19.24#ibcon#about to read 4, iclass 22, count 2 2006.259.07:20:19.24#ibcon#read 4, iclass 22, count 2 2006.259.07:20:19.24#ibcon#about to read 5, iclass 22, count 2 2006.259.07:20:19.24#ibcon#read 5, iclass 22, count 2 2006.259.07:20:19.24#ibcon#about to read 6, iclass 22, count 2 2006.259.07:20:19.24#ibcon#read 6, iclass 22, count 2 2006.259.07:20:19.24#ibcon#end of sib2, iclass 22, count 2 2006.259.07:20:19.24#ibcon#*mode == 0, iclass 22, count 2 2006.259.07:20:19.24#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.259.07:20:19.24#ibcon#[25=AT06-06\r\n] 2006.259.07:20:19.24#ibcon#*before write, iclass 22, count 2 2006.259.07:20:19.24#ibcon#enter sib2, iclass 22, count 2 2006.259.07:20:19.24#ibcon#flushed, iclass 22, count 2 2006.259.07:20:19.24#ibcon#about to write, iclass 22, count 2 2006.259.07:20:19.24#ibcon#wrote, iclass 22, count 2 2006.259.07:20:19.24#ibcon#about to read 3, iclass 22, count 2 2006.259.07:20:19.27#ibcon#read 3, iclass 22, count 2 2006.259.07:20:19.27#ibcon#about to read 4, iclass 22, count 2 2006.259.07:20:19.27#ibcon#read 4, iclass 22, count 2 2006.259.07:20:19.27#ibcon#about to read 5, iclass 22, count 2 2006.259.07:20:19.27#ibcon#read 5, iclass 22, count 2 2006.259.07:20:19.27#ibcon#about to read 6, iclass 22, count 2 2006.259.07:20:19.27#ibcon#read 6, iclass 22, count 2 2006.259.07:20:19.27#ibcon#end of sib2, iclass 22, count 2 2006.259.07:20:19.27#ibcon#*after write, iclass 22, count 2 2006.259.07:20:19.27#ibcon#*before return 0, iclass 22, count 2 2006.259.07:20:19.27#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.259.07:20:19.27#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.259.07:20:19.27#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.259.07:20:19.27#ibcon#ireg 7 cls_cnt 0 2006.259.07:20:19.27#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.259.07:20:19.39#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.259.07:20:19.39#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.259.07:20:19.39#ibcon#enter wrdev, iclass 22, count 0 2006.259.07:20:19.39#ibcon#first serial, iclass 22, count 0 2006.259.07:20:19.39#ibcon#enter sib2, iclass 22, count 0 2006.259.07:20:19.39#ibcon#flushed, iclass 22, count 0 2006.259.07:20:19.39#ibcon#about to write, iclass 22, count 0 2006.259.07:20:19.39#ibcon#wrote, iclass 22, count 0 2006.259.07:20:19.39#ibcon#about to read 3, iclass 22, count 0 2006.259.07:20:19.41#ibcon#read 3, iclass 22, count 0 2006.259.07:20:19.41#ibcon#about to read 4, iclass 22, count 0 2006.259.07:20:19.41#ibcon#read 4, iclass 22, count 0 2006.259.07:20:19.41#ibcon#about to read 5, iclass 22, count 0 2006.259.07:20:19.41#ibcon#read 5, iclass 22, count 0 2006.259.07:20:19.41#ibcon#about to read 6, iclass 22, count 0 2006.259.07:20:19.41#ibcon#read 6, iclass 22, count 0 2006.259.07:20:19.41#ibcon#end of sib2, iclass 22, count 0 2006.259.07:20:19.41#ibcon#*mode == 0, iclass 22, count 0 2006.259.07:20:19.41#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.259.07:20:19.41#ibcon#[25=USB\r\n] 2006.259.07:20:19.41#ibcon#*before write, iclass 22, count 0 2006.259.07:20:19.41#ibcon#enter sib2, iclass 22, count 0 2006.259.07:20:19.41#ibcon#flushed, iclass 22, count 0 2006.259.07:20:19.41#ibcon#about to write, iclass 22, count 0 2006.259.07:20:19.41#ibcon#wrote, iclass 22, count 0 2006.259.07:20:19.41#ibcon#about to read 3, iclass 22, count 0 2006.259.07:20:19.44#ibcon#read 3, iclass 22, count 0 2006.259.07:20:19.44#ibcon#about to read 4, iclass 22, count 0 2006.259.07:20:19.44#ibcon#read 4, iclass 22, count 0 2006.259.07:20:19.44#ibcon#about to read 5, iclass 22, count 0 2006.259.07:20:19.44#ibcon#read 5, iclass 22, count 0 2006.259.07:20:19.44#ibcon#about to read 6, iclass 22, count 0 2006.259.07:20:19.44#ibcon#read 6, iclass 22, count 0 2006.259.07:20:19.44#ibcon#end of sib2, iclass 22, count 0 2006.259.07:20:19.44#ibcon#*after write, iclass 22, count 0 2006.259.07:20:19.44#ibcon#*before return 0, iclass 22, count 0 2006.259.07:20:19.44#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.259.07:20:19.44#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.259.07:20:19.44#ibcon#about to clear, iclass 22 cls_cnt 0 2006.259.07:20:19.44#ibcon#cleared, iclass 22 cls_cnt 0 2006.259.07:20:19.44$vc4f8/valo=7,832.99 2006.259.07:20:19.44#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.259.07:20:19.44#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.259.07:20:19.44#ibcon#ireg 17 cls_cnt 0 2006.259.07:20:19.44#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.259.07:20:19.44#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.259.07:20:19.44#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.259.07:20:19.44#ibcon#enter wrdev, iclass 24, count 0 2006.259.07:20:19.44#ibcon#first serial, iclass 24, count 0 2006.259.07:20:19.44#ibcon#enter sib2, iclass 24, count 0 2006.259.07:20:19.44#ibcon#flushed, iclass 24, count 0 2006.259.07:20:19.44#ibcon#about to write, iclass 24, count 0 2006.259.07:20:19.44#ibcon#wrote, iclass 24, count 0 2006.259.07:20:19.44#ibcon#about to read 3, iclass 24, count 0 2006.259.07:20:19.46#ibcon#read 3, iclass 24, count 0 2006.259.07:20:19.46#ibcon#about to read 4, iclass 24, count 0 2006.259.07:20:19.46#ibcon#read 4, iclass 24, count 0 2006.259.07:20:19.46#ibcon#about to read 5, iclass 24, count 0 2006.259.07:20:19.46#ibcon#read 5, iclass 24, count 0 2006.259.07:20:19.46#ibcon#about to read 6, iclass 24, count 0 2006.259.07:20:19.46#ibcon#read 6, iclass 24, count 0 2006.259.07:20:19.46#ibcon#end of sib2, iclass 24, count 0 2006.259.07:20:19.46#ibcon#*mode == 0, iclass 24, count 0 2006.259.07:20:19.46#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.259.07:20:19.46#ibcon#[26=FRQ=07,832.99\r\n] 2006.259.07:20:19.46#ibcon#*before write, iclass 24, count 0 2006.259.07:20:19.46#ibcon#enter sib2, iclass 24, count 0 2006.259.07:20:19.46#ibcon#flushed, iclass 24, count 0 2006.259.07:20:19.46#ibcon#about to write, iclass 24, count 0 2006.259.07:20:19.46#ibcon#wrote, iclass 24, count 0 2006.259.07:20:19.46#ibcon#about to read 3, iclass 24, count 0 2006.259.07:20:19.50#ibcon#read 3, iclass 24, count 0 2006.259.07:20:19.50#ibcon#about to read 4, iclass 24, count 0 2006.259.07:20:19.50#ibcon#read 4, iclass 24, count 0 2006.259.07:20:19.50#ibcon#about to read 5, iclass 24, count 0 2006.259.07:20:19.50#ibcon#read 5, iclass 24, count 0 2006.259.07:20:19.50#ibcon#about to read 6, iclass 24, count 0 2006.259.07:20:19.50#ibcon#read 6, iclass 24, count 0 2006.259.07:20:19.50#ibcon#end of sib2, iclass 24, count 0 2006.259.07:20:19.50#ibcon#*after write, iclass 24, count 0 2006.259.07:20:19.50#ibcon#*before return 0, iclass 24, count 0 2006.259.07:20:19.50#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.259.07:20:19.50#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.259.07:20:19.50#ibcon#about to clear, iclass 24 cls_cnt 0 2006.259.07:20:19.50#ibcon#cleared, iclass 24 cls_cnt 0 2006.259.07:20:19.50$vc4f8/va=7,6 2006.259.07:20:19.50#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.259.07:20:19.50#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.259.07:20:19.50#ibcon#ireg 11 cls_cnt 2 2006.259.07:20:19.50#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.259.07:20:19.56#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.259.07:20:19.56#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.259.07:20:19.56#ibcon#enter wrdev, iclass 26, count 2 2006.259.07:20:19.56#ibcon#first serial, iclass 26, count 2 2006.259.07:20:19.56#ibcon#enter sib2, iclass 26, count 2 2006.259.07:20:19.56#ibcon#flushed, iclass 26, count 2 2006.259.07:20:19.56#ibcon#about to write, iclass 26, count 2 2006.259.07:20:19.56#ibcon#wrote, iclass 26, count 2 2006.259.07:20:19.56#ibcon#about to read 3, iclass 26, count 2 2006.259.07:20:19.58#ibcon#read 3, iclass 26, count 2 2006.259.07:20:19.58#ibcon#about to read 4, iclass 26, count 2 2006.259.07:20:19.58#ibcon#read 4, iclass 26, count 2 2006.259.07:20:19.58#ibcon#about to read 5, iclass 26, count 2 2006.259.07:20:19.58#ibcon#read 5, iclass 26, count 2 2006.259.07:20:19.58#ibcon#about to read 6, iclass 26, count 2 2006.259.07:20:19.58#ibcon#read 6, iclass 26, count 2 2006.259.07:20:19.58#ibcon#end of sib2, iclass 26, count 2 2006.259.07:20:19.58#ibcon#*mode == 0, iclass 26, count 2 2006.259.07:20:19.58#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.259.07:20:19.58#ibcon#[25=AT07-06\r\n] 2006.259.07:20:19.58#ibcon#*before write, iclass 26, count 2 2006.259.07:20:19.58#ibcon#enter sib2, iclass 26, count 2 2006.259.07:20:19.58#ibcon#flushed, iclass 26, count 2 2006.259.07:20:19.58#ibcon#about to write, iclass 26, count 2 2006.259.07:20:19.58#ibcon#wrote, iclass 26, count 2 2006.259.07:20:19.58#ibcon#about to read 3, iclass 26, count 2 2006.259.07:20:19.61#ibcon#read 3, iclass 26, count 2 2006.259.07:20:19.61#ibcon#about to read 4, iclass 26, count 2 2006.259.07:20:19.61#ibcon#read 4, iclass 26, count 2 2006.259.07:20:19.61#ibcon#about to read 5, iclass 26, count 2 2006.259.07:20:19.61#ibcon#read 5, iclass 26, count 2 2006.259.07:20:19.61#ibcon#about to read 6, iclass 26, count 2 2006.259.07:20:19.61#ibcon#read 6, iclass 26, count 2 2006.259.07:20:19.61#ibcon#end of sib2, iclass 26, count 2 2006.259.07:20:19.61#ibcon#*after write, iclass 26, count 2 2006.259.07:20:19.61#ibcon#*before return 0, iclass 26, count 2 2006.259.07:20:19.61#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.259.07:20:19.61#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.259.07:20:19.61#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.259.07:20:19.61#ibcon#ireg 7 cls_cnt 0 2006.259.07:20:19.61#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.259.07:20:19.73#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.259.07:20:19.73#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.259.07:20:19.73#ibcon#enter wrdev, iclass 26, count 0 2006.259.07:20:19.73#ibcon#first serial, iclass 26, count 0 2006.259.07:20:19.73#ibcon#enter sib2, iclass 26, count 0 2006.259.07:20:19.73#ibcon#flushed, iclass 26, count 0 2006.259.07:20:19.73#ibcon#about to write, iclass 26, count 0 2006.259.07:20:19.73#ibcon#wrote, iclass 26, count 0 2006.259.07:20:19.73#ibcon#about to read 3, iclass 26, count 0 2006.259.07:20:19.75#ibcon#read 3, iclass 26, count 0 2006.259.07:20:19.75#ibcon#about to read 4, iclass 26, count 0 2006.259.07:20:19.75#ibcon#read 4, iclass 26, count 0 2006.259.07:20:19.75#ibcon#about to read 5, iclass 26, count 0 2006.259.07:20:19.75#ibcon#read 5, iclass 26, count 0 2006.259.07:20:19.75#ibcon#about to read 6, iclass 26, count 0 2006.259.07:20:19.75#ibcon#read 6, iclass 26, count 0 2006.259.07:20:19.75#ibcon#end of sib2, iclass 26, count 0 2006.259.07:20:19.75#ibcon#*mode == 0, iclass 26, count 0 2006.259.07:20:19.75#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.259.07:20:19.75#ibcon#[25=USB\r\n] 2006.259.07:20:19.75#ibcon#*before write, iclass 26, count 0 2006.259.07:20:19.75#ibcon#enter sib2, iclass 26, count 0 2006.259.07:20:19.75#ibcon#flushed, iclass 26, count 0 2006.259.07:20:19.75#ibcon#about to write, iclass 26, count 0 2006.259.07:20:19.75#ibcon#wrote, iclass 26, count 0 2006.259.07:20:19.75#ibcon#about to read 3, iclass 26, count 0 2006.259.07:20:19.78#ibcon#read 3, iclass 26, count 0 2006.259.07:20:19.78#ibcon#about to read 4, iclass 26, count 0 2006.259.07:20:19.78#ibcon#read 4, iclass 26, count 0 2006.259.07:20:19.78#ibcon#about to read 5, iclass 26, count 0 2006.259.07:20:19.78#ibcon#read 5, iclass 26, count 0 2006.259.07:20:19.78#ibcon#about to read 6, iclass 26, count 0 2006.259.07:20:19.78#ibcon#read 6, iclass 26, count 0 2006.259.07:20:19.78#ibcon#end of sib2, iclass 26, count 0 2006.259.07:20:19.78#ibcon#*after write, iclass 26, count 0 2006.259.07:20:19.78#ibcon#*before return 0, iclass 26, count 0 2006.259.07:20:19.78#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.259.07:20:19.78#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.259.07:20:19.78#ibcon#about to clear, iclass 26 cls_cnt 0 2006.259.07:20:19.78#ibcon#cleared, iclass 26 cls_cnt 0 2006.259.07:20:19.78$vc4f8/valo=8,852.99 2006.259.07:20:19.78#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.259.07:20:19.78#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.259.07:20:19.78#ibcon#ireg 17 cls_cnt 0 2006.259.07:20:19.78#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.259.07:20:19.78#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.259.07:20:19.78#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.259.07:20:19.78#ibcon#enter wrdev, iclass 28, count 0 2006.259.07:20:19.78#ibcon#first serial, iclass 28, count 0 2006.259.07:20:19.78#ibcon#enter sib2, iclass 28, count 0 2006.259.07:20:19.78#ibcon#flushed, iclass 28, count 0 2006.259.07:20:19.78#ibcon#about to write, iclass 28, count 0 2006.259.07:20:19.78#ibcon#wrote, iclass 28, count 0 2006.259.07:20:19.78#ibcon#about to read 3, iclass 28, count 0 2006.259.07:20:19.80#ibcon#read 3, iclass 28, count 0 2006.259.07:20:19.80#ibcon#about to read 4, iclass 28, count 0 2006.259.07:20:19.80#ibcon#read 4, iclass 28, count 0 2006.259.07:20:19.80#ibcon#about to read 5, iclass 28, count 0 2006.259.07:20:19.80#ibcon#read 5, iclass 28, count 0 2006.259.07:20:19.80#ibcon#about to read 6, iclass 28, count 0 2006.259.07:20:19.80#ibcon#read 6, iclass 28, count 0 2006.259.07:20:19.80#ibcon#end of sib2, iclass 28, count 0 2006.259.07:20:19.80#ibcon#*mode == 0, iclass 28, count 0 2006.259.07:20:19.80#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.259.07:20:19.80#ibcon#[26=FRQ=08,852.99\r\n] 2006.259.07:20:19.80#ibcon#*before write, iclass 28, count 0 2006.259.07:20:19.80#ibcon#enter sib2, iclass 28, count 0 2006.259.07:20:19.80#ibcon#flushed, iclass 28, count 0 2006.259.07:20:19.80#ibcon#about to write, iclass 28, count 0 2006.259.07:20:19.80#ibcon#wrote, iclass 28, count 0 2006.259.07:20:19.80#ibcon#about to read 3, iclass 28, count 0 2006.259.07:20:19.84#ibcon#read 3, iclass 28, count 0 2006.259.07:20:19.84#ibcon#about to read 4, iclass 28, count 0 2006.259.07:20:19.84#ibcon#read 4, iclass 28, count 0 2006.259.07:20:19.84#ibcon#about to read 5, iclass 28, count 0 2006.259.07:20:19.84#ibcon#read 5, iclass 28, count 0 2006.259.07:20:19.84#ibcon#about to read 6, iclass 28, count 0 2006.259.07:20:19.84#ibcon#read 6, iclass 28, count 0 2006.259.07:20:19.84#ibcon#end of sib2, iclass 28, count 0 2006.259.07:20:19.84#ibcon#*after write, iclass 28, count 0 2006.259.07:20:19.84#ibcon#*before return 0, iclass 28, count 0 2006.259.07:20:19.84#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.259.07:20:19.84#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.259.07:20:19.84#ibcon#about to clear, iclass 28 cls_cnt 0 2006.259.07:20:19.84#ibcon#cleared, iclass 28 cls_cnt 0 2006.259.07:20:19.84$vc4f8/va=8,6 2006.259.07:20:19.84#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.259.07:20:19.84#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.259.07:20:19.84#ibcon#ireg 11 cls_cnt 2 2006.259.07:20:19.84#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.259.07:20:19.90#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.259.07:20:19.90#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.259.07:20:19.90#ibcon#enter wrdev, iclass 30, count 2 2006.259.07:20:19.90#ibcon#first serial, iclass 30, count 2 2006.259.07:20:19.90#ibcon#enter sib2, iclass 30, count 2 2006.259.07:20:19.90#ibcon#flushed, iclass 30, count 2 2006.259.07:20:19.90#ibcon#about to write, iclass 30, count 2 2006.259.07:20:19.90#ibcon#wrote, iclass 30, count 2 2006.259.07:20:19.90#ibcon#about to read 3, iclass 30, count 2 2006.259.07:20:19.92#ibcon#read 3, iclass 30, count 2 2006.259.07:20:19.92#ibcon#about to read 4, iclass 30, count 2 2006.259.07:20:19.92#ibcon#read 4, iclass 30, count 2 2006.259.07:20:19.92#ibcon#about to read 5, iclass 30, count 2 2006.259.07:20:19.92#ibcon#read 5, iclass 30, count 2 2006.259.07:20:19.92#ibcon#about to read 6, iclass 30, count 2 2006.259.07:20:19.92#ibcon#read 6, iclass 30, count 2 2006.259.07:20:19.92#ibcon#end of sib2, iclass 30, count 2 2006.259.07:20:19.92#ibcon#*mode == 0, iclass 30, count 2 2006.259.07:20:19.92#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.259.07:20:19.92#ibcon#[25=AT08-06\r\n] 2006.259.07:20:19.92#ibcon#*before write, iclass 30, count 2 2006.259.07:20:19.92#ibcon#enter sib2, iclass 30, count 2 2006.259.07:20:19.92#ibcon#flushed, iclass 30, count 2 2006.259.07:20:19.92#ibcon#about to write, iclass 30, count 2 2006.259.07:20:19.92#ibcon#wrote, iclass 30, count 2 2006.259.07:20:19.92#ibcon#about to read 3, iclass 30, count 2 2006.259.07:20:19.95#ibcon#read 3, iclass 30, count 2 2006.259.07:20:19.95#ibcon#about to read 4, iclass 30, count 2 2006.259.07:20:19.95#ibcon#read 4, iclass 30, count 2 2006.259.07:20:19.95#ibcon#about to read 5, iclass 30, count 2 2006.259.07:20:19.95#ibcon#read 5, iclass 30, count 2 2006.259.07:20:19.95#ibcon#about to read 6, iclass 30, count 2 2006.259.07:20:19.95#ibcon#read 6, iclass 30, count 2 2006.259.07:20:19.95#ibcon#end of sib2, iclass 30, count 2 2006.259.07:20:19.95#ibcon#*after write, iclass 30, count 2 2006.259.07:20:19.95#ibcon#*before return 0, iclass 30, count 2 2006.259.07:20:19.95#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.259.07:20:19.95#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.259.07:20:19.95#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.259.07:20:19.95#ibcon#ireg 7 cls_cnt 0 2006.259.07:20:19.95#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.259.07:20:20.07#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.259.07:20:20.07#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.259.07:20:20.07#ibcon#enter wrdev, iclass 30, count 0 2006.259.07:20:20.07#ibcon#first serial, iclass 30, count 0 2006.259.07:20:20.07#ibcon#enter sib2, iclass 30, count 0 2006.259.07:20:20.07#ibcon#flushed, iclass 30, count 0 2006.259.07:20:20.07#ibcon#about to write, iclass 30, count 0 2006.259.07:20:20.07#ibcon#wrote, iclass 30, count 0 2006.259.07:20:20.07#ibcon#about to read 3, iclass 30, count 0 2006.259.07:20:20.09#ibcon#read 3, iclass 30, count 0 2006.259.07:20:20.09#ibcon#about to read 4, iclass 30, count 0 2006.259.07:20:20.09#ibcon#read 4, iclass 30, count 0 2006.259.07:20:20.09#ibcon#about to read 5, iclass 30, count 0 2006.259.07:20:20.09#ibcon#read 5, iclass 30, count 0 2006.259.07:20:20.09#ibcon#about to read 6, iclass 30, count 0 2006.259.07:20:20.09#ibcon#read 6, iclass 30, count 0 2006.259.07:20:20.09#ibcon#end of sib2, iclass 30, count 0 2006.259.07:20:20.09#ibcon#*mode == 0, iclass 30, count 0 2006.259.07:20:20.09#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.259.07:20:20.09#ibcon#[25=USB\r\n] 2006.259.07:20:20.09#ibcon#*before write, iclass 30, count 0 2006.259.07:20:20.09#ibcon#enter sib2, iclass 30, count 0 2006.259.07:20:20.09#ibcon#flushed, iclass 30, count 0 2006.259.07:20:20.09#ibcon#about to write, iclass 30, count 0 2006.259.07:20:20.09#ibcon#wrote, iclass 30, count 0 2006.259.07:20:20.09#ibcon#about to read 3, iclass 30, count 0 2006.259.07:20:20.12#ibcon#read 3, iclass 30, count 0 2006.259.07:20:20.12#ibcon#about to read 4, iclass 30, count 0 2006.259.07:20:20.12#ibcon#read 4, iclass 30, count 0 2006.259.07:20:20.12#ibcon#about to read 5, iclass 30, count 0 2006.259.07:20:20.12#ibcon#read 5, iclass 30, count 0 2006.259.07:20:20.12#ibcon#about to read 6, iclass 30, count 0 2006.259.07:20:20.12#ibcon#read 6, iclass 30, count 0 2006.259.07:20:20.12#ibcon#end of sib2, iclass 30, count 0 2006.259.07:20:20.12#ibcon#*after write, iclass 30, count 0 2006.259.07:20:20.12#ibcon#*before return 0, iclass 30, count 0 2006.259.07:20:20.12#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.259.07:20:20.12#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.259.07:20:20.12#ibcon#about to clear, iclass 30 cls_cnt 0 2006.259.07:20:20.12#ibcon#cleared, iclass 30 cls_cnt 0 2006.259.07:20:20.12$vc4f8/vblo=1,632.99 2006.259.07:20:20.12#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.259.07:20:20.12#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.259.07:20:20.12#ibcon#ireg 17 cls_cnt 0 2006.259.07:20:20.12#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.259.07:20:20.12#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.259.07:20:20.12#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.259.07:20:20.12#ibcon#enter wrdev, iclass 32, count 0 2006.259.07:20:20.12#ibcon#first serial, iclass 32, count 0 2006.259.07:20:20.12#ibcon#enter sib2, iclass 32, count 0 2006.259.07:20:20.12#ibcon#flushed, iclass 32, count 0 2006.259.07:20:20.12#ibcon#about to write, iclass 32, count 0 2006.259.07:20:20.12#ibcon#wrote, iclass 32, count 0 2006.259.07:20:20.12#ibcon#about to read 3, iclass 32, count 0 2006.259.07:20:20.14#ibcon#read 3, iclass 32, count 0 2006.259.07:20:20.14#ibcon#about to read 4, iclass 32, count 0 2006.259.07:20:20.14#ibcon#read 4, iclass 32, count 0 2006.259.07:20:20.14#ibcon#about to read 5, iclass 32, count 0 2006.259.07:20:20.14#ibcon#read 5, iclass 32, count 0 2006.259.07:20:20.14#ibcon#about to read 6, iclass 32, count 0 2006.259.07:20:20.14#ibcon#read 6, iclass 32, count 0 2006.259.07:20:20.14#ibcon#end of sib2, iclass 32, count 0 2006.259.07:20:20.14#ibcon#*mode == 0, iclass 32, count 0 2006.259.07:20:20.14#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.259.07:20:20.14#ibcon#[28=FRQ=01,632.99\r\n] 2006.259.07:20:20.14#ibcon#*before write, iclass 32, count 0 2006.259.07:20:20.14#ibcon#enter sib2, iclass 32, count 0 2006.259.07:20:20.14#ibcon#flushed, iclass 32, count 0 2006.259.07:20:20.14#ibcon#about to write, iclass 32, count 0 2006.259.07:20:20.14#ibcon#wrote, iclass 32, count 0 2006.259.07:20:20.14#ibcon#about to read 3, iclass 32, count 0 2006.259.07:20:20.20#ibcon#read 3, iclass 32, count 0 2006.259.07:20:20.20#ibcon#about to read 4, iclass 32, count 0 2006.259.07:20:20.20#ibcon#read 4, iclass 32, count 0 2006.259.07:20:20.20#ibcon#about to read 5, iclass 32, count 0 2006.259.07:20:20.20#ibcon#read 5, iclass 32, count 0 2006.259.07:20:20.20#ibcon#about to read 6, iclass 32, count 0 2006.259.07:20:20.20#ibcon#read 6, iclass 32, count 0 2006.259.07:20:20.20#ibcon#end of sib2, iclass 32, count 0 2006.259.07:20:20.20#ibcon#*after write, iclass 32, count 0 2006.259.07:20:20.20#ibcon#*before return 0, iclass 32, count 0 2006.259.07:20:20.20#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.259.07:20:20.20#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.259.07:20:20.20#ibcon#about to clear, iclass 32 cls_cnt 0 2006.259.07:20:20.20#ibcon#cleared, iclass 32 cls_cnt 0 2006.259.07:20:20.20$vc4f8/vb=1,4 2006.259.07:20:20.20#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.259.07:20:20.20#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.259.07:20:20.20#ibcon#ireg 11 cls_cnt 2 2006.259.07:20:20.20#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.259.07:20:20.20#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.259.07:20:20.20#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.259.07:20:20.20#ibcon#enter wrdev, iclass 34, count 2 2006.259.07:20:20.20#ibcon#first serial, iclass 34, count 2 2006.259.07:20:20.20#ibcon#enter sib2, iclass 34, count 2 2006.259.07:20:20.20#ibcon#flushed, iclass 34, count 2 2006.259.07:20:20.20#ibcon#about to write, iclass 34, count 2 2006.259.07:20:20.20#ibcon#wrote, iclass 34, count 2 2006.259.07:20:20.20#ibcon#about to read 3, iclass 34, count 2 2006.259.07:20:20.22#ibcon#read 3, iclass 34, count 2 2006.259.07:20:20.22#ibcon#about to read 4, iclass 34, count 2 2006.259.07:20:20.22#ibcon#read 4, iclass 34, count 2 2006.259.07:20:20.22#ibcon#about to read 5, iclass 34, count 2 2006.259.07:20:20.22#ibcon#read 5, iclass 34, count 2 2006.259.07:20:20.22#ibcon#about to read 6, iclass 34, count 2 2006.259.07:20:20.22#ibcon#read 6, iclass 34, count 2 2006.259.07:20:20.22#ibcon#end of sib2, iclass 34, count 2 2006.259.07:20:20.22#ibcon#*mode == 0, iclass 34, count 2 2006.259.07:20:20.22#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.259.07:20:20.22#ibcon#[27=AT01-04\r\n] 2006.259.07:20:20.22#ibcon#*before write, iclass 34, count 2 2006.259.07:20:20.22#ibcon#enter sib2, iclass 34, count 2 2006.259.07:20:20.22#ibcon#flushed, iclass 34, count 2 2006.259.07:20:20.22#ibcon#about to write, iclass 34, count 2 2006.259.07:20:20.22#ibcon#wrote, iclass 34, count 2 2006.259.07:20:20.22#ibcon#about to read 3, iclass 34, count 2 2006.259.07:20:20.26#ibcon#read 3, iclass 34, count 2 2006.259.07:20:20.26#ibcon#about to read 4, iclass 34, count 2 2006.259.07:20:20.26#ibcon#read 4, iclass 34, count 2 2006.259.07:20:20.26#ibcon#about to read 5, iclass 34, count 2 2006.259.07:20:20.26#ibcon#read 5, iclass 34, count 2 2006.259.07:20:20.26#ibcon#about to read 6, iclass 34, count 2 2006.259.07:20:20.26#ibcon#read 6, iclass 34, count 2 2006.259.07:20:20.26#ibcon#end of sib2, iclass 34, count 2 2006.259.07:20:20.26#ibcon#*after write, iclass 34, count 2 2006.259.07:20:20.26#ibcon#*before return 0, iclass 34, count 2 2006.259.07:20:20.26#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.259.07:20:20.26#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.259.07:20:20.26#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.259.07:20:20.26#ibcon#ireg 7 cls_cnt 0 2006.259.07:20:20.26#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.259.07:20:20.38#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.259.07:20:20.38#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.259.07:20:20.38#ibcon#enter wrdev, iclass 34, count 0 2006.259.07:20:20.38#ibcon#first serial, iclass 34, count 0 2006.259.07:20:20.38#ibcon#enter sib2, iclass 34, count 0 2006.259.07:20:20.38#ibcon#flushed, iclass 34, count 0 2006.259.07:20:20.38#ibcon#about to write, iclass 34, count 0 2006.259.07:20:20.38#ibcon#wrote, iclass 34, count 0 2006.259.07:20:20.38#ibcon#about to read 3, iclass 34, count 0 2006.259.07:20:20.40#ibcon#read 3, iclass 34, count 0 2006.259.07:20:20.40#ibcon#about to read 4, iclass 34, count 0 2006.259.07:20:20.40#ibcon#read 4, iclass 34, count 0 2006.259.07:20:20.40#ibcon#about to read 5, iclass 34, count 0 2006.259.07:20:20.40#ibcon#read 5, iclass 34, count 0 2006.259.07:20:20.40#ibcon#about to read 6, iclass 34, count 0 2006.259.07:20:20.40#ibcon#read 6, iclass 34, count 0 2006.259.07:20:20.40#ibcon#end of sib2, iclass 34, count 0 2006.259.07:20:20.40#ibcon#*mode == 0, iclass 34, count 0 2006.259.07:20:20.40#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.259.07:20:20.40#ibcon#[27=USB\r\n] 2006.259.07:20:20.40#ibcon#*before write, iclass 34, count 0 2006.259.07:20:20.40#ibcon#enter sib2, iclass 34, count 0 2006.259.07:20:20.40#ibcon#flushed, iclass 34, count 0 2006.259.07:20:20.40#ibcon#about to write, iclass 34, count 0 2006.259.07:20:20.40#ibcon#wrote, iclass 34, count 0 2006.259.07:20:20.40#ibcon#about to read 3, iclass 34, count 0 2006.259.07:20:20.43#ibcon#read 3, iclass 34, count 0 2006.259.07:20:20.43#ibcon#about to read 4, iclass 34, count 0 2006.259.07:20:20.43#ibcon#read 4, iclass 34, count 0 2006.259.07:20:20.43#ibcon#about to read 5, iclass 34, count 0 2006.259.07:20:20.43#ibcon#read 5, iclass 34, count 0 2006.259.07:20:20.43#ibcon#about to read 6, iclass 34, count 0 2006.259.07:20:20.43#ibcon#read 6, iclass 34, count 0 2006.259.07:20:20.43#ibcon#end of sib2, iclass 34, count 0 2006.259.07:20:20.43#ibcon#*after write, iclass 34, count 0 2006.259.07:20:20.43#ibcon#*before return 0, iclass 34, count 0 2006.259.07:20:20.43#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.259.07:20:20.43#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.259.07:20:20.43#ibcon#about to clear, iclass 34 cls_cnt 0 2006.259.07:20:20.43#ibcon#cleared, iclass 34 cls_cnt 0 2006.259.07:20:20.43$vc4f8/vblo=2,640.99 2006.259.07:20:20.43#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.259.07:20:20.43#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.259.07:20:20.43#ibcon#ireg 17 cls_cnt 0 2006.259.07:20:20.43#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.259.07:20:20.43#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.259.07:20:20.43#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.259.07:20:20.43#ibcon#enter wrdev, iclass 36, count 0 2006.259.07:20:20.43#ibcon#first serial, iclass 36, count 0 2006.259.07:20:20.43#ibcon#enter sib2, iclass 36, count 0 2006.259.07:20:20.43#ibcon#flushed, iclass 36, count 0 2006.259.07:20:20.43#ibcon#about to write, iclass 36, count 0 2006.259.07:20:20.43#ibcon#wrote, iclass 36, count 0 2006.259.07:20:20.43#ibcon#about to read 3, iclass 36, count 0 2006.259.07:20:20.45#ibcon#read 3, iclass 36, count 0 2006.259.07:20:20.45#ibcon#about to read 4, iclass 36, count 0 2006.259.07:20:20.45#ibcon#read 4, iclass 36, count 0 2006.259.07:20:20.45#ibcon#about to read 5, iclass 36, count 0 2006.259.07:20:20.45#ibcon#read 5, iclass 36, count 0 2006.259.07:20:20.45#ibcon#about to read 6, iclass 36, count 0 2006.259.07:20:20.45#ibcon#read 6, iclass 36, count 0 2006.259.07:20:20.45#ibcon#end of sib2, iclass 36, count 0 2006.259.07:20:20.45#ibcon#*mode == 0, iclass 36, count 0 2006.259.07:20:20.45#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.259.07:20:20.45#ibcon#[28=FRQ=02,640.99\r\n] 2006.259.07:20:20.45#ibcon#*before write, iclass 36, count 0 2006.259.07:20:20.45#ibcon#enter sib2, iclass 36, count 0 2006.259.07:20:20.45#ibcon#flushed, iclass 36, count 0 2006.259.07:20:20.45#ibcon#about to write, iclass 36, count 0 2006.259.07:20:20.45#ibcon#wrote, iclass 36, count 0 2006.259.07:20:20.45#ibcon#about to read 3, iclass 36, count 0 2006.259.07:20:20.49#ibcon#read 3, iclass 36, count 0 2006.259.07:20:20.49#ibcon#about to read 4, iclass 36, count 0 2006.259.07:20:20.49#ibcon#read 4, iclass 36, count 0 2006.259.07:20:20.49#ibcon#about to read 5, iclass 36, count 0 2006.259.07:20:20.49#ibcon#read 5, iclass 36, count 0 2006.259.07:20:20.49#ibcon#about to read 6, iclass 36, count 0 2006.259.07:20:20.49#ibcon#read 6, iclass 36, count 0 2006.259.07:20:20.49#ibcon#end of sib2, iclass 36, count 0 2006.259.07:20:20.49#ibcon#*after write, iclass 36, count 0 2006.259.07:20:20.49#ibcon#*before return 0, iclass 36, count 0 2006.259.07:20:20.49#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.259.07:20:20.49#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.259.07:20:20.49#ibcon#about to clear, iclass 36 cls_cnt 0 2006.259.07:20:20.49#ibcon#cleared, iclass 36 cls_cnt 0 2006.259.07:20:20.49$vc4f8/vb=2,5 2006.259.07:20:20.49#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.259.07:20:20.49#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.259.07:20:20.49#ibcon#ireg 11 cls_cnt 2 2006.259.07:20:20.49#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.259.07:20:20.55#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.259.07:20:20.55#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.259.07:20:20.55#ibcon#enter wrdev, iclass 38, count 2 2006.259.07:20:20.55#ibcon#first serial, iclass 38, count 2 2006.259.07:20:20.55#ibcon#enter sib2, iclass 38, count 2 2006.259.07:20:20.55#ibcon#flushed, iclass 38, count 2 2006.259.07:20:20.55#ibcon#about to write, iclass 38, count 2 2006.259.07:20:20.55#ibcon#wrote, iclass 38, count 2 2006.259.07:20:20.55#ibcon#about to read 3, iclass 38, count 2 2006.259.07:20:20.57#ibcon#read 3, iclass 38, count 2 2006.259.07:20:20.57#ibcon#about to read 4, iclass 38, count 2 2006.259.07:20:20.57#ibcon#read 4, iclass 38, count 2 2006.259.07:20:20.57#ibcon#about to read 5, iclass 38, count 2 2006.259.07:20:20.57#ibcon#read 5, iclass 38, count 2 2006.259.07:20:20.57#ibcon#about to read 6, iclass 38, count 2 2006.259.07:20:20.57#ibcon#read 6, iclass 38, count 2 2006.259.07:20:20.57#ibcon#end of sib2, iclass 38, count 2 2006.259.07:20:20.57#ibcon#*mode == 0, iclass 38, count 2 2006.259.07:20:20.57#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.259.07:20:20.57#ibcon#[27=AT02-05\r\n] 2006.259.07:20:20.57#ibcon#*before write, iclass 38, count 2 2006.259.07:20:20.57#ibcon#enter sib2, iclass 38, count 2 2006.259.07:20:20.57#ibcon#flushed, iclass 38, count 2 2006.259.07:20:20.57#ibcon#about to write, iclass 38, count 2 2006.259.07:20:20.57#ibcon#wrote, iclass 38, count 2 2006.259.07:20:20.57#ibcon#about to read 3, iclass 38, count 2 2006.259.07:20:20.60#ibcon#read 3, iclass 38, count 2 2006.259.07:20:20.60#ibcon#about to read 4, iclass 38, count 2 2006.259.07:20:20.60#ibcon#read 4, iclass 38, count 2 2006.259.07:20:20.60#ibcon#about to read 5, iclass 38, count 2 2006.259.07:20:20.60#ibcon#read 5, iclass 38, count 2 2006.259.07:20:20.60#ibcon#about to read 6, iclass 38, count 2 2006.259.07:20:20.60#ibcon#read 6, iclass 38, count 2 2006.259.07:20:20.60#ibcon#end of sib2, iclass 38, count 2 2006.259.07:20:20.60#ibcon#*after write, iclass 38, count 2 2006.259.07:20:20.60#ibcon#*before return 0, iclass 38, count 2 2006.259.07:20:20.60#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.259.07:20:20.60#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.259.07:20:20.60#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.259.07:20:20.60#ibcon#ireg 7 cls_cnt 0 2006.259.07:20:20.60#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.259.07:20:20.72#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.259.07:20:20.72#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.259.07:20:20.72#ibcon#enter wrdev, iclass 38, count 0 2006.259.07:20:20.72#ibcon#first serial, iclass 38, count 0 2006.259.07:20:20.72#ibcon#enter sib2, iclass 38, count 0 2006.259.07:20:20.72#ibcon#flushed, iclass 38, count 0 2006.259.07:20:20.72#ibcon#about to write, iclass 38, count 0 2006.259.07:20:20.72#ibcon#wrote, iclass 38, count 0 2006.259.07:20:20.72#ibcon#about to read 3, iclass 38, count 0 2006.259.07:20:20.74#ibcon#read 3, iclass 38, count 0 2006.259.07:20:20.74#ibcon#about to read 4, iclass 38, count 0 2006.259.07:20:20.74#ibcon#read 4, iclass 38, count 0 2006.259.07:20:20.74#ibcon#about to read 5, iclass 38, count 0 2006.259.07:20:20.74#ibcon#read 5, iclass 38, count 0 2006.259.07:20:20.74#ibcon#about to read 6, iclass 38, count 0 2006.259.07:20:20.74#ibcon#read 6, iclass 38, count 0 2006.259.07:20:20.74#ibcon#end of sib2, iclass 38, count 0 2006.259.07:20:20.74#ibcon#*mode == 0, iclass 38, count 0 2006.259.07:20:20.74#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.259.07:20:20.74#ibcon#[27=USB\r\n] 2006.259.07:20:20.74#ibcon#*before write, iclass 38, count 0 2006.259.07:20:20.74#ibcon#enter sib2, iclass 38, count 0 2006.259.07:20:20.74#ibcon#flushed, iclass 38, count 0 2006.259.07:20:20.74#ibcon#about to write, iclass 38, count 0 2006.259.07:20:20.74#ibcon#wrote, iclass 38, count 0 2006.259.07:20:20.74#ibcon#about to read 3, iclass 38, count 0 2006.259.07:20:20.77#ibcon#read 3, iclass 38, count 0 2006.259.07:20:20.77#ibcon#about to read 4, iclass 38, count 0 2006.259.07:20:20.77#ibcon#read 4, iclass 38, count 0 2006.259.07:20:20.77#ibcon#about to read 5, iclass 38, count 0 2006.259.07:20:20.77#ibcon#read 5, iclass 38, count 0 2006.259.07:20:20.77#ibcon#about to read 6, iclass 38, count 0 2006.259.07:20:20.77#ibcon#read 6, iclass 38, count 0 2006.259.07:20:20.77#ibcon#end of sib2, iclass 38, count 0 2006.259.07:20:20.77#ibcon#*after write, iclass 38, count 0 2006.259.07:20:20.77#ibcon#*before return 0, iclass 38, count 0 2006.259.07:20:20.77#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.259.07:20:20.77#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.259.07:20:20.77#ibcon#about to clear, iclass 38 cls_cnt 0 2006.259.07:20:20.77#ibcon#cleared, iclass 38 cls_cnt 0 2006.259.07:20:20.77$vc4f8/vblo=3,656.99 2006.259.07:20:20.77#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.259.07:20:20.77#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.259.07:20:20.77#ibcon#ireg 17 cls_cnt 0 2006.259.07:20:20.77#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.259.07:20:20.77#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.259.07:20:20.77#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.259.07:20:20.77#ibcon#enter wrdev, iclass 40, count 0 2006.259.07:20:20.77#ibcon#first serial, iclass 40, count 0 2006.259.07:20:20.77#ibcon#enter sib2, iclass 40, count 0 2006.259.07:20:20.77#ibcon#flushed, iclass 40, count 0 2006.259.07:20:20.77#ibcon#about to write, iclass 40, count 0 2006.259.07:20:20.77#ibcon#wrote, iclass 40, count 0 2006.259.07:20:20.77#ibcon#about to read 3, iclass 40, count 0 2006.259.07:20:20.79#ibcon#read 3, iclass 40, count 0 2006.259.07:20:20.79#ibcon#about to read 4, iclass 40, count 0 2006.259.07:20:20.79#ibcon#read 4, iclass 40, count 0 2006.259.07:20:20.79#ibcon#about to read 5, iclass 40, count 0 2006.259.07:20:20.79#ibcon#read 5, iclass 40, count 0 2006.259.07:20:20.79#ibcon#about to read 6, iclass 40, count 0 2006.259.07:20:20.79#ibcon#read 6, iclass 40, count 0 2006.259.07:20:20.79#ibcon#end of sib2, iclass 40, count 0 2006.259.07:20:20.79#ibcon#*mode == 0, iclass 40, count 0 2006.259.07:20:20.79#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.259.07:20:20.79#ibcon#[28=FRQ=03,656.99\r\n] 2006.259.07:20:20.79#ibcon#*before write, iclass 40, count 0 2006.259.07:20:20.79#ibcon#enter sib2, iclass 40, count 0 2006.259.07:20:20.79#ibcon#flushed, iclass 40, count 0 2006.259.07:20:20.79#ibcon#about to write, iclass 40, count 0 2006.259.07:20:20.79#ibcon#wrote, iclass 40, count 0 2006.259.07:20:20.79#ibcon#about to read 3, iclass 40, count 0 2006.259.07:20:20.83#ibcon#read 3, iclass 40, count 0 2006.259.07:20:20.83#ibcon#about to read 4, iclass 40, count 0 2006.259.07:20:20.83#ibcon#read 4, iclass 40, count 0 2006.259.07:20:20.83#ibcon#about to read 5, iclass 40, count 0 2006.259.07:20:20.83#ibcon#read 5, iclass 40, count 0 2006.259.07:20:20.83#ibcon#about to read 6, iclass 40, count 0 2006.259.07:20:20.83#ibcon#read 6, iclass 40, count 0 2006.259.07:20:20.83#ibcon#end of sib2, iclass 40, count 0 2006.259.07:20:20.83#ibcon#*after write, iclass 40, count 0 2006.259.07:20:20.83#ibcon#*before return 0, iclass 40, count 0 2006.259.07:20:20.83#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.259.07:20:20.83#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.259.07:20:20.83#ibcon#about to clear, iclass 40 cls_cnt 0 2006.259.07:20:20.83#ibcon#cleared, iclass 40 cls_cnt 0 2006.259.07:20:20.83$vc4f8/vb=3,4 2006.259.07:20:20.83#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.259.07:20:20.83#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.259.07:20:20.83#ibcon#ireg 11 cls_cnt 2 2006.259.07:20:20.83#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.259.07:20:20.89#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.259.07:20:20.89#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.259.07:20:20.89#ibcon#enter wrdev, iclass 4, count 2 2006.259.07:20:20.89#ibcon#first serial, iclass 4, count 2 2006.259.07:20:20.89#ibcon#enter sib2, iclass 4, count 2 2006.259.07:20:20.89#ibcon#flushed, iclass 4, count 2 2006.259.07:20:20.89#ibcon#about to write, iclass 4, count 2 2006.259.07:20:20.89#ibcon#wrote, iclass 4, count 2 2006.259.07:20:20.89#ibcon#about to read 3, iclass 4, count 2 2006.259.07:20:20.91#ibcon#read 3, iclass 4, count 2 2006.259.07:20:20.91#ibcon#about to read 4, iclass 4, count 2 2006.259.07:20:20.91#ibcon#read 4, iclass 4, count 2 2006.259.07:20:20.91#ibcon#about to read 5, iclass 4, count 2 2006.259.07:20:20.91#ibcon#read 5, iclass 4, count 2 2006.259.07:20:20.91#ibcon#about to read 6, iclass 4, count 2 2006.259.07:20:20.91#ibcon#read 6, iclass 4, count 2 2006.259.07:20:20.91#ibcon#end of sib2, iclass 4, count 2 2006.259.07:20:20.91#ibcon#*mode == 0, iclass 4, count 2 2006.259.07:20:20.91#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.259.07:20:20.91#ibcon#[27=AT03-04\r\n] 2006.259.07:20:20.91#ibcon#*before write, iclass 4, count 2 2006.259.07:20:20.91#ibcon#enter sib2, iclass 4, count 2 2006.259.07:20:20.91#ibcon#flushed, iclass 4, count 2 2006.259.07:20:20.91#ibcon#about to write, iclass 4, count 2 2006.259.07:20:20.91#ibcon#wrote, iclass 4, count 2 2006.259.07:20:20.91#ibcon#about to read 3, iclass 4, count 2 2006.259.07:20:20.94#ibcon#read 3, iclass 4, count 2 2006.259.07:20:20.94#ibcon#about to read 4, iclass 4, count 2 2006.259.07:20:20.94#ibcon#read 4, iclass 4, count 2 2006.259.07:20:20.94#ibcon#about to read 5, iclass 4, count 2 2006.259.07:20:20.94#ibcon#read 5, iclass 4, count 2 2006.259.07:20:20.94#ibcon#about to read 6, iclass 4, count 2 2006.259.07:20:20.94#ibcon#read 6, iclass 4, count 2 2006.259.07:20:20.94#ibcon#end of sib2, iclass 4, count 2 2006.259.07:20:20.94#ibcon#*after write, iclass 4, count 2 2006.259.07:20:20.94#ibcon#*before return 0, iclass 4, count 2 2006.259.07:20:20.94#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.259.07:20:20.94#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.259.07:20:20.94#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.259.07:20:20.94#ibcon#ireg 7 cls_cnt 0 2006.259.07:20:20.94#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.259.07:20:21.06#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.259.07:20:21.06#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.259.07:20:21.06#ibcon#enter wrdev, iclass 4, count 0 2006.259.07:20:21.06#ibcon#first serial, iclass 4, count 0 2006.259.07:20:21.06#ibcon#enter sib2, iclass 4, count 0 2006.259.07:20:21.06#ibcon#flushed, iclass 4, count 0 2006.259.07:20:21.06#ibcon#about to write, iclass 4, count 0 2006.259.07:20:21.06#ibcon#wrote, iclass 4, count 0 2006.259.07:20:21.06#ibcon#about to read 3, iclass 4, count 0 2006.259.07:20:21.08#ibcon#read 3, iclass 4, count 0 2006.259.07:20:21.08#ibcon#about to read 4, iclass 4, count 0 2006.259.07:20:21.08#ibcon#read 4, iclass 4, count 0 2006.259.07:20:21.08#ibcon#about to read 5, iclass 4, count 0 2006.259.07:20:21.08#ibcon#read 5, iclass 4, count 0 2006.259.07:20:21.08#ibcon#about to read 6, iclass 4, count 0 2006.259.07:20:21.08#ibcon#read 6, iclass 4, count 0 2006.259.07:20:21.08#ibcon#end of sib2, iclass 4, count 0 2006.259.07:20:21.08#ibcon#*mode == 0, iclass 4, count 0 2006.259.07:20:21.08#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.259.07:20:21.08#ibcon#[27=USB\r\n] 2006.259.07:20:21.08#ibcon#*before write, iclass 4, count 0 2006.259.07:20:21.08#ibcon#enter sib2, iclass 4, count 0 2006.259.07:20:21.08#ibcon#flushed, iclass 4, count 0 2006.259.07:20:21.08#ibcon#about to write, iclass 4, count 0 2006.259.07:20:21.08#ibcon#wrote, iclass 4, count 0 2006.259.07:20:21.08#ibcon#about to read 3, iclass 4, count 0 2006.259.07:20:21.11#ibcon#read 3, iclass 4, count 0 2006.259.07:20:21.11#ibcon#about to read 4, iclass 4, count 0 2006.259.07:20:21.11#ibcon#read 4, iclass 4, count 0 2006.259.07:20:21.11#ibcon#about to read 5, iclass 4, count 0 2006.259.07:20:21.11#ibcon#read 5, iclass 4, count 0 2006.259.07:20:21.11#ibcon#about to read 6, iclass 4, count 0 2006.259.07:20:21.11#ibcon#read 6, iclass 4, count 0 2006.259.07:20:21.11#ibcon#end of sib2, iclass 4, count 0 2006.259.07:20:21.11#ibcon#*after write, iclass 4, count 0 2006.259.07:20:21.11#ibcon#*before return 0, iclass 4, count 0 2006.259.07:20:21.11#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.259.07:20:21.11#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.259.07:20:21.11#ibcon#about to clear, iclass 4 cls_cnt 0 2006.259.07:20:21.11#ibcon#cleared, iclass 4 cls_cnt 0 2006.259.07:20:21.11$vc4f8/vblo=4,712.99 2006.259.07:20:21.11#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.259.07:20:21.11#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.259.07:20:21.11#ibcon#ireg 17 cls_cnt 0 2006.259.07:20:21.11#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.259.07:20:21.11#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.259.07:20:21.11#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.259.07:20:21.11#ibcon#enter wrdev, iclass 6, count 0 2006.259.07:20:21.11#ibcon#first serial, iclass 6, count 0 2006.259.07:20:21.11#ibcon#enter sib2, iclass 6, count 0 2006.259.07:20:21.11#ibcon#flushed, iclass 6, count 0 2006.259.07:20:21.11#ibcon#about to write, iclass 6, count 0 2006.259.07:20:21.11#ibcon#wrote, iclass 6, count 0 2006.259.07:20:21.11#ibcon#about to read 3, iclass 6, count 0 2006.259.07:20:21.13#ibcon#read 3, iclass 6, count 0 2006.259.07:20:21.13#ibcon#about to read 4, iclass 6, count 0 2006.259.07:20:21.13#ibcon#read 4, iclass 6, count 0 2006.259.07:20:21.13#ibcon#about to read 5, iclass 6, count 0 2006.259.07:20:21.13#ibcon#read 5, iclass 6, count 0 2006.259.07:20:21.13#ibcon#about to read 6, iclass 6, count 0 2006.259.07:20:21.13#ibcon#read 6, iclass 6, count 0 2006.259.07:20:21.13#ibcon#end of sib2, iclass 6, count 0 2006.259.07:20:21.13#ibcon#*mode == 0, iclass 6, count 0 2006.259.07:20:21.13#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.259.07:20:21.13#ibcon#[28=FRQ=04,712.99\r\n] 2006.259.07:20:21.13#ibcon#*before write, iclass 6, count 0 2006.259.07:20:21.13#ibcon#enter sib2, iclass 6, count 0 2006.259.07:20:21.13#ibcon#flushed, iclass 6, count 0 2006.259.07:20:21.13#ibcon#about to write, iclass 6, count 0 2006.259.07:20:21.13#ibcon#wrote, iclass 6, count 0 2006.259.07:20:21.13#ibcon#about to read 3, iclass 6, count 0 2006.259.07:20:21.17#ibcon#read 3, iclass 6, count 0 2006.259.07:20:21.17#ibcon#about to read 4, iclass 6, count 0 2006.259.07:20:21.17#ibcon#read 4, iclass 6, count 0 2006.259.07:20:21.17#ibcon#about to read 5, iclass 6, count 0 2006.259.07:20:21.17#ibcon#read 5, iclass 6, count 0 2006.259.07:20:21.17#ibcon#about to read 6, iclass 6, count 0 2006.259.07:20:21.17#ibcon#read 6, iclass 6, count 0 2006.259.07:20:21.17#ibcon#end of sib2, iclass 6, count 0 2006.259.07:20:21.17#ibcon#*after write, iclass 6, count 0 2006.259.07:20:21.17#ibcon#*before return 0, iclass 6, count 0 2006.259.07:20:21.17#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.259.07:20:21.17#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.259.07:20:21.17#ibcon#about to clear, iclass 6 cls_cnt 0 2006.259.07:20:21.17#ibcon#cleared, iclass 6 cls_cnt 0 2006.259.07:20:21.17$vc4f8/vb=4,5 2006.259.07:20:21.17#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.259.07:20:21.17#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.259.07:20:21.17#ibcon#ireg 11 cls_cnt 2 2006.259.07:20:21.17#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.259.07:20:21.23#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.259.07:20:21.23#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.259.07:20:21.23#ibcon#enter wrdev, iclass 10, count 2 2006.259.07:20:21.23#ibcon#first serial, iclass 10, count 2 2006.259.07:20:21.23#ibcon#enter sib2, iclass 10, count 2 2006.259.07:20:21.23#ibcon#flushed, iclass 10, count 2 2006.259.07:20:21.23#ibcon#about to write, iclass 10, count 2 2006.259.07:20:21.23#ibcon#wrote, iclass 10, count 2 2006.259.07:20:21.23#ibcon#about to read 3, iclass 10, count 2 2006.259.07:20:21.25#ibcon#read 3, iclass 10, count 2 2006.259.07:20:21.25#ibcon#about to read 4, iclass 10, count 2 2006.259.07:20:21.25#ibcon#read 4, iclass 10, count 2 2006.259.07:20:21.25#ibcon#about to read 5, iclass 10, count 2 2006.259.07:20:21.25#ibcon#read 5, iclass 10, count 2 2006.259.07:20:21.25#ibcon#about to read 6, iclass 10, count 2 2006.259.07:20:21.25#ibcon#read 6, iclass 10, count 2 2006.259.07:20:21.25#ibcon#end of sib2, iclass 10, count 2 2006.259.07:20:21.25#ibcon#*mode == 0, iclass 10, count 2 2006.259.07:20:21.25#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.259.07:20:21.25#ibcon#[27=AT04-05\r\n] 2006.259.07:20:21.25#ibcon#*before write, iclass 10, count 2 2006.259.07:20:21.25#ibcon#enter sib2, iclass 10, count 2 2006.259.07:20:21.25#ibcon#flushed, iclass 10, count 2 2006.259.07:20:21.25#ibcon#about to write, iclass 10, count 2 2006.259.07:20:21.25#ibcon#wrote, iclass 10, count 2 2006.259.07:20:21.25#ibcon#about to read 3, iclass 10, count 2 2006.259.07:20:21.28#ibcon#read 3, iclass 10, count 2 2006.259.07:20:21.28#ibcon#about to read 4, iclass 10, count 2 2006.259.07:20:21.28#ibcon#read 4, iclass 10, count 2 2006.259.07:20:21.28#ibcon#about to read 5, iclass 10, count 2 2006.259.07:20:21.28#ibcon#read 5, iclass 10, count 2 2006.259.07:20:21.28#ibcon#about to read 6, iclass 10, count 2 2006.259.07:20:21.28#ibcon#read 6, iclass 10, count 2 2006.259.07:20:21.28#ibcon#end of sib2, iclass 10, count 2 2006.259.07:20:21.28#ibcon#*after write, iclass 10, count 2 2006.259.07:20:21.28#ibcon#*before return 0, iclass 10, count 2 2006.259.07:20:21.28#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.259.07:20:21.28#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.259.07:20:21.28#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.259.07:20:21.28#ibcon#ireg 7 cls_cnt 0 2006.259.07:20:21.28#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.259.07:20:21.40#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.259.07:20:21.40#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.259.07:20:21.40#ibcon#enter wrdev, iclass 10, count 0 2006.259.07:20:21.40#ibcon#first serial, iclass 10, count 0 2006.259.07:20:21.40#ibcon#enter sib2, iclass 10, count 0 2006.259.07:20:21.40#ibcon#flushed, iclass 10, count 0 2006.259.07:20:21.40#ibcon#about to write, iclass 10, count 0 2006.259.07:20:21.40#ibcon#wrote, iclass 10, count 0 2006.259.07:20:21.40#ibcon#about to read 3, iclass 10, count 0 2006.259.07:20:21.42#ibcon#read 3, iclass 10, count 0 2006.259.07:20:21.42#ibcon#about to read 4, iclass 10, count 0 2006.259.07:20:21.42#ibcon#read 4, iclass 10, count 0 2006.259.07:20:21.42#ibcon#about to read 5, iclass 10, count 0 2006.259.07:20:21.42#ibcon#read 5, iclass 10, count 0 2006.259.07:20:21.42#ibcon#about to read 6, iclass 10, count 0 2006.259.07:20:21.42#ibcon#read 6, iclass 10, count 0 2006.259.07:20:21.42#ibcon#end of sib2, iclass 10, count 0 2006.259.07:20:21.42#ibcon#*mode == 0, iclass 10, count 0 2006.259.07:20:21.42#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.259.07:20:21.42#ibcon#[27=USB\r\n] 2006.259.07:20:21.42#ibcon#*before write, iclass 10, count 0 2006.259.07:20:21.42#ibcon#enter sib2, iclass 10, count 0 2006.259.07:20:21.42#ibcon#flushed, iclass 10, count 0 2006.259.07:20:21.42#ibcon#about to write, iclass 10, count 0 2006.259.07:20:21.42#ibcon#wrote, iclass 10, count 0 2006.259.07:20:21.42#ibcon#about to read 3, iclass 10, count 0 2006.259.07:20:21.45#ibcon#read 3, iclass 10, count 0 2006.259.07:20:21.45#ibcon#about to read 4, iclass 10, count 0 2006.259.07:20:21.45#ibcon#read 4, iclass 10, count 0 2006.259.07:20:21.45#ibcon#about to read 5, iclass 10, count 0 2006.259.07:20:21.45#ibcon#read 5, iclass 10, count 0 2006.259.07:20:21.45#ibcon#about to read 6, iclass 10, count 0 2006.259.07:20:21.45#ibcon#read 6, iclass 10, count 0 2006.259.07:20:21.45#ibcon#end of sib2, iclass 10, count 0 2006.259.07:20:21.45#ibcon#*after write, iclass 10, count 0 2006.259.07:20:21.45#ibcon#*before return 0, iclass 10, count 0 2006.259.07:20:21.45#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.259.07:20:21.45#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.259.07:20:21.45#ibcon#about to clear, iclass 10 cls_cnt 0 2006.259.07:20:21.45#ibcon#cleared, iclass 10 cls_cnt 0 2006.259.07:20:21.45$vc4f8/vblo=5,744.99 2006.259.07:20:21.45#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.259.07:20:21.45#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.259.07:20:21.45#ibcon#ireg 17 cls_cnt 0 2006.259.07:20:21.45#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.259.07:20:21.45#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.259.07:20:21.45#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.259.07:20:21.45#ibcon#enter wrdev, iclass 12, count 0 2006.259.07:20:21.45#ibcon#first serial, iclass 12, count 0 2006.259.07:20:21.45#ibcon#enter sib2, iclass 12, count 0 2006.259.07:20:21.45#ibcon#flushed, iclass 12, count 0 2006.259.07:20:21.45#ibcon#about to write, iclass 12, count 0 2006.259.07:20:21.45#ibcon#wrote, iclass 12, count 0 2006.259.07:20:21.45#ibcon#about to read 3, iclass 12, count 0 2006.259.07:20:21.47#ibcon#read 3, iclass 12, count 0 2006.259.07:20:21.47#ibcon#about to read 4, iclass 12, count 0 2006.259.07:20:21.47#ibcon#read 4, iclass 12, count 0 2006.259.07:20:21.47#ibcon#about to read 5, iclass 12, count 0 2006.259.07:20:21.47#ibcon#read 5, iclass 12, count 0 2006.259.07:20:21.47#ibcon#about to read 6, iclass 12, count 0 2006.259.07:20:21.47#ibcon#read 6, iclass 12, count 0 2006.259.07:20:21.47#ibcon#end of sib2, iclass 12, count 0 2006.259.07:20:21.47#ibcon#*mode == 0, iclass 12, count 0 2006.259.07:20:21.47#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.259.07:20:21.47#ibcon#[28=FRQ=05,744.99\r\n] 2006.259.07:20:21.47#ibcon#*before write, iclass 12, count 0 2006.259.07:20:21.47#ibcon#enter sib2, iclass 12, count 0 2006.259.07:20:21.47#ibcon#flushed, iclass 12, count 0 2006.259.07:20:21.47#ibcon#about to write, iclass 12, count 0 2006.259.07:20:21.47#ibcon#wrote, iclass 12, count 0 2006.259.07:20:21.47#ibcon#about to read 3, iclass 12, count 0 2006.259.07:20:21.51#ibcon#read 3, iclass 12, count 0 2006.259.07:20:21.51#ibcon#about to read 4, iclass 12, count 0 2006.259.07:20:21.51#ibcon#read 4, iclass 12, count 0 2006.259.07:20:21.51#ibcon#about to read 5, iclass 12, count 0 2006.259.07:20:21.51#ibcon#read 5, iclass 12, count 0 2006.259.07:20:21.51#ibcon#about to read 6, iclass 12, count 0 2006.259.07:20:21.51#ibcon#read 6, iclass 12, count 0 2006.259.07:20:21.51#ibcon#end of sib2, iclass 12, count 0 2006.259.07:20:21.51#ibcon#*after write, iclass 12, count 0 2006.259.07:20:21.51#ibcon#*before return 0, iclass 12, count 0 2006.259.07:20:21.51#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.259.07:20:21.51#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.259.07:20:21.51#ibcon#about to clear, iclass 12 cls_cnt 0 2006.259.07:20:21.51#ibcon#cleared, iclass 12 cls_cnt 0 2006.259.07:20:21.51$vc4f8/vb=5,4 2006.259.07:20:21.51#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.259.07:20:21.51#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.259.07:20:21.51#ibcon#ireg 11 cls_cnt 2 2006.259.07:20:21.51#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.259.07:20:21.57#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.259.07:20:21.57#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.259.07:20:21.57#ibcon#enter wrdev, iclass 14, count 2 2006.259.07:20:21.57#ibcon#first serial, iclass 14, count 2 2006.259.07:20:21.57#ibcon#enter sib2, iclass 14, count 2 2006.259.07:20:21.57#ibcon#flushed, iclass 14, count 2 2006.259.07:20:21.57#ibcon#about to write, iclass 14, count 2 2006.259.07:20:21.57#ibcon#wrote, iclass 14, count 2 2006.259.07:20:21.57#ibcon#about to read 3, iclass 14, count 2 2006.259.07:20:21.59#ibcon#read 3, iclass 14, count 2 2006.259.07:20:21.59#ibcon#about to read 4, iclass 14, count 2 2006.259.07:20:21.59#ibcon#read 4, iclass 14, count 2 2006.259.07:20:21.59#ibcon#about to read 5, iclass 14, count 2 2006.259.07:20:21.59#ibcon#read 5, iclass 14, count 2 2006.259.07:20:21.59#ibcon#about to read 6, iclass 14, count 2 2006.259.07:20:21.59#ibcon#read 6, iclass 14, count 2 2006.259.07:20:21.59#ibcon#end of sib2, iclass 14, count 2 2006.259.07:20:21.59#ibcon#*mode == 0, iclass 14, count 2 2006.259.07:20:21.59#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.259.07:20:21.59#ibcon#[27=AT05-04\r\n] 2006.259.07:20:21.59#ibcon#*before write, iclass 14, count 2 2006.259.07:20:21.59#ibcon#enter sib2, iclass 14, count 2 2006.259.07:20:21.59#ibcon#flushed, iclass 14, count 2 2006.259.07:20:21.59#ibcon#about to write, iclass 14, count 2 2006.259.07:20:21.59#ibcon#wrote, iclass 14, count 2 2006.259.07:20:21.59#ibcon#about to read 3, iclass 14, count 2 2006.259.07:20:21.62#ibcon#read 3, iclass 14, count 2 2006.259.07:20:21.62#ibcon#about to read 4, iclass 14, count 2 2006.259.07:20:21.62#ibcon#read 4, iclass 14, count 2 2006.259.07:20:21.62#ibcon#about to read 5, iclass 14, count 2 2006.259.07:20:21.62#ibcon#read 5, iclass 14, count 2 2006.259.07:20:21.62#ibcon#about to read 6, iclass 14, count 2 2006.259.07:20:21.62#ibcon#read 6, iclass 14, count 2 2006.259.07:20:21.62#ibcon#end of sib2, iclass 14, count 2 2006.259.07:20:21.62#ibcon#*after write, iclass 14, count 2 2006.259.07:20:21.62#ibcon#*before return 0, iclass 14, count 2 2006.259.07:20:21.62#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.259.07:20:21.62#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.259.07:20:21.62#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.259.07:20:21.62#ibcon#ireg 7 cls_cnt 0 2006.259.07:20:21.62#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.259.07:20:21.74#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.259.07:20:21.74#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.259.07:20:21.74#ibcon#enter wrdev, iclass 14, count 0 2006.259.07:20:21.74#ibcon#first serial, iclass 14, count 0 2006.259.07:20:21.74#ibcon#enter sib2, iclass 14, count 0 2006.259.07:20:21.74#ibcon#flushed, iclass 14, count 0 2006.259.07:20:21.74#ibcon#about to write, iclass 14, count 0 2006.259.07:20:21.74#ibcon#wrote, iclass 14, count 0 2006.259.07:20:21.74#ibcon#about to read 3, iclass 14, count 0 2006.259.07:20:21.76#ibcon#read 3, iclass 14, count 0 2006.259.07:20:21.76#ibcon#about to read 4, iclass 14, count 0 2006.259.07:20:21.76#ibcon#read 4, iclass 14, count 0 2006.259.07:20:21.76#ibcon#about to read 5, iclass 14, count 0 2006.259.07:20:21.76#ibcon#read 5, iclass 14, count 0 2006.259.07:20:21.76#ibcon#about to read 6, iclass 14, count 0 2006.259.07:20:21.76#ibcon#read 6, iclass 14, count 0 2006.259.07:20:21.76#ibcon#end of sib2, iclass 14, count 0 2006.259.07:20:21.76#ibcon#*mode == 0, iclass 14, count 0 2006.259.07:20:21.76#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.259.07:20:21.76#ibcon#[27=USB\r\n] 2006.259.07:20:21.76#ibcon#*before write, iclass 14, count 0 2006.259.07:20:21.76#ibcon#enter sib2, iclass 14, count 0 2006.259.07:20:21.76#ibcon#flushed, iclass 14, count 0 2006.259.07:20:21.76#ibcon#about to write, iclass 14, count 0 2006.259.07:20:21.76#ibcon#wrote, iclass 14, count 0 2006.259.07:20:21.76#ibcon#about to read 3, iclass 14, count 0 2006.259.07:20:21.79#ibcon#read 3, iclass 14, count 0 2006.259.07:20:21.79#ibcon#about to read 4, iclass 14, count 0 2006.259.07:20:21.79#ibcon#read 4, iclass 14, count 0 2006.259.07:20:21.79#ibcon#about to read 5, iclass 14, count 0 2006.259.07:20:21.79#ibcon#read 5, iclass 14, count 0 2006.259.07:20:21.79#ibcon#about to read 6, iclass 14, count 0 2006.259.07:20:21.79#ibcon#read 6, iclass 14, count 0 2006.259.07:20:21.79#ibcon#end of sib2, iclass 14, count 0 2006.259.07:20:21.79#ibcon#*after write, iclass 14, count 0 2006.259.07:20:21.79#ibcon#*before return 0, iclass 14, count 0 2006.259.07:20:21.79#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.259.07:20:21.79#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.259.07:20:21.79#ibcon#about to clear, iclass 14 cls_cnt 0 2006.259.07:20:21.79#ibcon#cleared, iclass 14 cls_cnt 0 2006.259.07:20:21.79$vc4f8/vblo=6,752.99 2006.259.07:20:21.79#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.259.07:20:21.79#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.259.07:20:21.79#ibcon#ireg 17 cls_cnt 0 2006.259.07:20:21.79#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.259.07:20:21.79#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.259.07:20:21.79#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.259.07:20:21.79#ibcon#enter wrdev, iclass 16, count 0 2006.259.07:20:21.79#ibcon#first serial, iclass 16, count 0 2006.259.07:20:21.79#ibcon#enter sib2, iclass 16, count 0 2006.259.07:20:21.79#ibcon#flushed, iclass 16, count 0 2006.259.07:20:21.79#ibcon#about to write, iclass 16, count 0 2006.259.07:20:21.79#ibcon#wrote, iclass 16, count 0 2006.259.07:20:21.79#ibcon#about to read 3, iclass 16, count 0 2006.259.07:20:21.81#ibcon#read 3, iclass 16, count 0 2006.259.07:20:21.81#ibcon#about to read 4, iclass 16, count 0 2006.259.07:20:21.81#ibcon#read 4, iclass 16, count 0 2006.259.07:20:21.81#ibcon#about to read 5, iclass 16, count 0 2006.259.07:20:21.81#ibcon#read 5, iclass 16, count 0 2006.259.07:20:21.81#ibcon#about to read 6, iclass 16, count 0 2006.259.07:20:21.81#ibcon#read 6, iclass 16, count 0 2006.259.07:20:21.81#ibcon#end of sib2, iclass 16, count 0 2006.259.07:20:21.81#ibcon#*mode == 0, iclass 16, count 0 2006.259.07:20:21.81#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.259.07:20:21.81#ibcon#[28=FRQ=06,752.99\r\n] 2006.259.07:20:21.81#ibcon#*before write, iclass 16, count 0 2006.259.07:20:21.81#ibcon#enter sib2, iclass 16, count 0 2006.259.07:20:21.81#ibcon#flushed, iclass 16, count 0 2006.259.07:20:21.81#ibcon#about to write, iclass 16, count 0 2006.259.07:20:21.81#ibcon#wrote, iclass 16, count 0 2006.259.07:20:21.81#ibcon#about to read 3, iclass 16, count 0 2006.259.07:20:21.85#ibcon#read 3, iclass 16, count 0 2006.259.07:20:21.85#ibcon#about to read 4, iclass 16, count 0 2006.259.07:20:21.85#ibcon#read 4, iclass 16, count 0 2006.259.07:20:21.85#ibcon#about to read 5, iclass 16, count 0 2006.259.07:20:21.85#ibcon#read 5, iclass 16, count 0 2006.259.07:20:21.85#ibcon#about to read 6, iclass 16, count 0 2006.259.07:20:21.85#ibcon#read 6, iclass 16, count 0 2006.259.07:20:21.85#ibcon#end of sib2, iclass 16, count 0 2006.259.07:20:21.85#ibcon#*after write, iclass 16, count 0 2006.259.07:20:21.85#ibcon#*before return 0, iclass 16, count 0 2006.259.07:20:21.85#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.259.07:20:21.85#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.259.07:20:21.85#ibcon#about to clear, iclass 16 cls_cnt 0 2006.259.07:20:21.85#ibcon#cleared, iclass 16 cls_cnt 0 2006.259.07:20:21.85$vc4f8/vb=6,4 2006.259.07:20:21.85#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.259.07:20:21.85#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.259.07:20:21.85#ibcon#ireg 11 cls_cnt 2 2006.259.07:20:21.85#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.259.07:20:21.91#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.259.07:20:21.91#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.259.07:20:21.91#ibcon#enter wrdev, iclass 18, count 2 2006.259.07:20:21.91#ibcon#first serial, iclass 18, count 2 2006.259.07:20:21.91#ibcon#enter sib2, iclass 18, count 2 2006.259.07:20:21.91#ibcon#flushed, iclass 18, count 2 2006.259.07:20:21.91#ibcon#about to write, iclass 18, count 2 2006.259.07:20:21.91#ibcon#wrote, iclass 18, count 2 2006.259.07:20:21.91#ibcon#about to read 3, iclass 18, count 2 2006.259.07:20:21.93#ibcon#read 3, iclass 18, count 2 2006.259.07:20:21.93#ibcon#about to read 4, iclass 18, count 2 2006.259.07:20:21.93#ibcon#read 4, iclass 18, count 2 2006.259.07:20:21.93#ibcon#about to read 5, iclass 18, count 2 2006.259.07:20:21.93#ibcon#read 5, iclass 18, count 2 2006.259.07:20:21.93#ibcon#about to read 6, iclass 18, count 2 2006.259.07:20:21.93#ibcon#read 6, iclass 18, count 2 2006.259.07:20:21.93#ibcon#end of sib2, iclass 18, count 2 2006.259.07:20:21.93#ibcon#*mode == 0, iclass 18, count 2 2006.259.07:20:21.93#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.259.07:20:21.93#ibcon#[27=AT06-04\r\n] 2006.259.07:20:21.93#ibcon#*before write, iclass 18, count 2 2006.259.07:20:21.93#ibcon#enter sib2, iclass 18, count 2 2006.259.07:20:21.93#ibcon#flushed, iclass 18, count 2 2006.259.07:20:21.93#ibcon#about to write, iclass 18, count 2 2006.259.07:20:21.93#ibcon#wrote, iclass 18, count 2 2006.259.07:20:21.93#ibcon#about to read 3, iclass 18, count 2 2006.259.07:20:21.96#ibcon#read 3, iclass 18, count 2 2006.259.07:20:21.96#ibcon#about to read 4, iclass 18, count 2 2006.259.07:20:21.96#ibcon#read 4, iclass 18, count 2 2006.259.07:20:21.96#ibcon#about to read 5, iclass 18, count 2 2006.259.07:20:21.96#ibcon#read 5, iclass 18, count 2 2006.259.07:20:21.96#ibcon#about to read 6, iclass 18, count 2 2006.259.07:20:21.96#ibcon#read 6, iclass 18, count 2 2006.259.07:20:21.96#ibcon#end of sib2, iclass 18, count 2 2006.259.07:20:21.96#ibcon#*after write, iclass 18, count 2 2006.259.07:20:21.96#ibcon#*before return 0, iclass 18, count 2 2006.259.07:20:21.96#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.259.07:20:21.96#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.259.07:20:21.96#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.259.07:20:21.96#ibcon#ireg 7 cls_cnt 0 2006.259.07:20:21.96#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.259.07:20:22.08#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.259.07:20:22.08#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.259.07:20:22.08#ibcon#enter wrdev, iclass 18, count 0 2006.259.07:20:22.08#ibcon#first serial, iclass 18, count 0 2006.259.07:20:22.08#ibcon#enter sib2, iclass 18, count 0 2006.259.07:20:22.08#ibcon#flushed, iclass 18, count 0 2006.259.07:20:22.08#ibcon#about to write, iclass 18, count 0 2006.259.07:20:22.08#ibcon#wrote, iclass 18, count 0 2006.259.07:20:22.08#ibcon#about to read 3, iclass 18, count 0 2006.259.07:20:22.10#ibcon#read 3, iclass 18, count 0 2006.259.07:20:22.10#ibcon#about to read 4, iclass 18, count 0 2006.259.07:20:22.10#ibcon#read 4, iclass 18, count 0 2006.259.07:20:22.10#ibcon#about to read 5, iclass 18, count 0 2006.259.07:20:22.10#ibcon#read 5, iclass 18, count 0 2006.259.07:20:22.10#ibcon#about to read 6, iclass 18, count 0 2006.259.07:20:22.10#ibcon#read 6, iclass 18, count 0 2006.259.07:20:22.10#ibcon#end of sib2, iclass 18, count 0 2006.259.07:20:22.10#ibcon#*mode == 0, iclass 18, count 0 2006.259.07:20:22.10#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.259.07:20:22.10#ibcon#[27=USB\r\n] 2006.259.07:20:22.10#ibcon#*before write, iclass 18, count 0 2006.259.07:20:22.10#ibcon#enter sib2, iclass 18, count 0 2006.259.07:20:22.10#ibcon#flushed, iclass 18, count 0 2006.259.07:20:22.10#ibcon#about to write, iclass 18, count 0 2006.259.07:20:22.10#ibcon#wrote, iclass 18, count 0 2006.259.07:20:22.10#ibcon#about to read 3, iclass 18, count 0 2006.259.07:20:22.13#ibcon#read 3, iclass 18, count 0 2006.259.07:20:22.13#ibcon#about to read 4, iclass 18, count 0 2006.259.07:20:22.13#ibcon#read 4, iclass 18, count 0 2006.259.07:20:22.13#ibcon#about to read 5, iclass 18, count 0 2006.259.07:20:22.13#ibcon#read 5, iclass 18, count 0 2006.259.07:20:22.13#ibcon#about to read 6, iclass 18, count 0 2006.259.07:20:22.13#ibcon#read 6, iclass 18, count 0 2006.259.07:20:22.13#ibcon#end of sib2, iclass 18, count 0 2006.259.07:20:22.13#ibcon#*after write, iclass 18, count 0 2006.259.07:20:22.13#ibcon#*before return 0, iclass 18, count 0 2006.259.07:20:22.13#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.259.07:20:22.13#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.259.07:20:22.13#ibcon#about to clear, iclass 18 cls_cnt 0 2006.259.07:20:22.13#ibcon#cleared, iclass 18 cls_cnt 0 2006.259.07:20:22.13$vc4f8/vabw=wide 2006.259.07:20:22.13#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.259.07:20:22.13#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.259.07:20:22.13#ibcon#ireg 8 cls_cnt 0 2006.259.07:20:22.13#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.259.07:20:22.13#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.259.07:20:22.13#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.259.07:20:22.13#ibcon#enter wrdev, iclass 20, count 0 2006.259.07:20:22.13#ibcon#first serial, iclass 20, count 0 2006.259.07:20:22.13#ibcon#enter sib2, iclass 20, count 0 2006.259.07:20:22.13#ibcon#flushed, iclass 20, count 0 2006.259.07:20:22.13#ibcon#about to write, iclass 20, count 0 2006.259.07:20:22.13#ibcon#wrote, iclass 20, count 0 2006.259.07:20:22.13#ibcon#about to read 3, iclass 20, count 0 2006.259.07:20:22.15#ibcon#read 3, iclass 20, count 0 2006.259.07:20:22.15#ibcon#about to read 4, iclass 20, count 0 2006.259.07:20:22.15#ibcon#read 4, iclass 20, count 0 2006.259.07:20:22.15#ibcon#about to read 5, iclass 20, count 0 2006.259.07:20:22.15#ibcon#read 5, iclass 20, count 0 2006.259.07:20:22.15#ibcon#about to read 6, iclass 20, count 0 2006.259.07:20:22.15#ibcon#read 6, iclass 20, count 0 2006.259.07:20:22.15#ibcon#end of sib2, iclass 20, count 0 2006.259.07:20:22.15#ibcon#*mode == 0, iclass 20, count 0 2006.259.07:20:22.15#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.259.07:20:22.15#ibcon#[25=BW32\r\n] 2006.259.07:20:22.15#ibcon#*before write, iclass 20, count 0 2006.259.07:20:22.15#ibcon#enter sib2, iclass 20, count 0 2006.259.07:20:22.15#ibcon#flushed, iclass 20, count 0 2006.259.07:20:22.15#ibcon#about to write, iclass 20, count 0 2006.259.07:20:22.15#ibcon#wrote, iclass 20, count 0 2006.259.07:20:22.15#ibcon#about to read 3, iclass 20, count 0 2006.259.07:20:22.18#ibcon#read 3, iclass 20, count 0 2006.259.07:20:22.18#ibcon#about to read 4, iclass 20, count 0 2006.259.07:20:22.18#ibcon#read 4, iclass 20, count 0 2006.259.07:20:22.18#ibcon#about to read 5, iclass 20, count 0 2006.259.07:20:22.18#ibcon#read 5, iclass 20, count 0 2006.259.07:20:22.18#ibcon#about to read 6, iclass 20, count 0 2006.259.07:20:22.18#ibcon#read 6, iclass 20, count 0 2006.259.07:20:22.18#ibcon#end of sib2, iclass 20, count 0 2006.259.07:20:22.18#ibcon#*after write, iclass 20, count 0 2006.259.07:20:22.18#ibcon#*before return 0, iclass 20, count 0 2006.259.07:20:22.18#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.259.07:20:22.18#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.259.07:20:22.18#ibcon#about to clear, iclass 20 cls_cnt 0 2006.259.07:20:22.18#ibcon#cleared, iclass 20 cls_cnt 0 2006.259.07:20:22.18$vc4f8/vbbw=wide 2006.259.07:20:22.18#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.259.07:20:22.18#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.259.07:20:22.18#ibcon#ireg 8 cls_cnt 0 2006.259.07:20:22.18#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.259.07:20:22.25#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.259.07:20:22.25#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.259.07:20:22.25#ibcon#enter wrdev, iclass 22, count 0 2006.259.07:20:22.25#ibcon#first serial, iclass 22, count 0 2006.259.07:20:22.25#ibcon#enter sib2, iclass 22, count 0 2006.259.07:20:22.25#ibcon#flushed, iclass 22, count 0 2006.259.07:20:22.25#ibcon#about to write, iclass 22, count 0 2006.259.07:20:22.25#ibcon#wrote, iclass 22, count 0 2006.259.07:20:22.25#ibcon#about to read 3, iclass 22, count 0 2006.259.07:20:22.27#ibcon#read 3, iclass 22, count 0 2006.259.07:20:22.27#ibcon#about to read 4, iclass 22, count 0 2006.259.07:20:22.27#ibcon#read 4, iclass 22, count 0 2006.259.07:20:22.27#ibcon#about to read 5, iclass 22, count 0 2006.259.07:20:22.27#ibcon#read 5, iclass 22, count 0 2006.259.07:20:22.27#ibcon#about to read 6, iclass 22, count 0 2006.259.07:20:22.27#ibcon#read 6, iclass 22, count 0 2006.259.07:20:22.27#ibcon#end of sib2, iclass 22, count 0 2006.259.07:20:22.27#ibcon#*mode == 0, iclass 22, count 0 2006.259.07:20:22.27#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.259.07:20:22.27#ibcon#[27=BW32\r\n] 2006.259.07:20:22.27#ibcon#*before write, iclass 22, count 0 2006.259.07:20:22.27#ibcon#enter sib2, iclass 22, count 0 2006.259.07:20:22.27#ibcon#flushed, iclass 22, count 0 2006.259.07:20:22.27#ibcon#about to write, iclass 22, count 0 2006.259.07:20:22.27#ibcon#wrote, iclass 22, count 0 2006.259.07:20:22.27#ibcon#about to read 3, iclass 22, count 0 2006.259.07:20:22.30#ibcon#read 3, iclass 22, count 0 2006.259.07:20:22.30#ibcon#about to read 4, iclass 22, count 0 2006.259.07:20:22.30#ibcon#read 4, iclass 22, count 0 2006.259.07:20:22.30#ibcon#about to read 5, iclass 22, count 0 2006.259.07:20:22.30#ibcon#read 5, iclass 22, count 0 2006.259.07:20:22.30#ibcon#about to read 6, iclass 22, count 0 2006.259.07:20:22.30#ibcon#read 6, iclass 22, count 0 2006.259.07:20:22.30#ibcon#end of sib2, iclass 22, count 0 2006.259.07:20:22.30#ibcon#*after write, iclass 22, count 0 2006.259.07:20:22.30#ibcon#*before return 0, iclass 22, count 0 2006.259.07:20:22.30#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.259.07:20:22.30#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.259.07:20:22.30#ibcon#about to clear, iclass 22 cls_cnt 0 2006.259.07:20:22.30#ibcon#cleared, iclass 22 cls_cnt 0 2006.259.07:20:22.30$4f8m12a/ifd4f 2006.259.07:20:22.30&ifd4f/lo= 2006.259.07:20:22.30&ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.259.07:20:22.30&ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.259.07:20:22.30&ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.259.07:20:22.30&ifd4f/patch= 2006.259.07:20:22.30&ifd4f/patch=lo1,a1,a2,a3,a4 2006.259.07:20:22.30&ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.259.07:20:22.30&ifd4f/patch=lo3,a5,a6,a7,a8 2006.259.07:20:22.30$ifd4f/lo= 2006.259.07:20:22.30$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.259.07:20:22.30$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.259.07:20:22.30$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.259.07:20:22.30$ifd4f/patch= 2006.259.07:20:22.31$ifd4f/patch=lo1,a1,a2,a3,a4 2006.259.07:20:22.31$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.259.07:20:22.31$ifd4f/patch=lo3,a5,a6,a7,a8 2006.259.07:20:22.31$4f8m12a/"form=m,16.000,1:2 2006.259.07:20:22.31$4f8m12a/"tpicd 2006.259.07:20:22.31$4f8m12a/echo=off 2006.259.07:20:22.31$4f8m12a/xlog=off 2006.259.07:20:22.31:!2006.259.07:29:50 2006.259.07:20:34.14#trakl#Source acquired 2006.259.07:20:35.14#flagr#flagr/antenna,acquired 2006.259.07:29:50.00:preob 2006.259.07:29:50.00&preob/onsource 2006.259.07:29:51.14/onsource/TRACKING 2006.259.07:29:51.14:!2006.259.07:30:00 2006.259.07:30:00.00:data_valid=on 2006.259.07:30:00.00:midob 2006.259.07:30:00.00&midob/onsource 2006.259.07:30:00.00&midob/wx 2006.259.07:30:00.00&midob/cable 2006.259.07:30:00.00&midob/va 2006.259.07:30:00.00&midob/valo 2006.259.07:30:00.00&midob/vb 2006.259.07:30:00.00&midob/vblo 2006.259.07:30:00.00&midob/vabw 2006.259.07:30:00.00&midob/vbbw 2006.259.07:30:00.00&midob/"form 2006.259.07:30:00.00&midob/xfe 2006.259.07:30:00.00&midob/ifatt 2006.259.07:30:00.00&midob/clockoff 2006.259.07:30:00.00&midob/sy=logmail 2006.259.07:30:00.00&midob/"sy=run setcl adapt & 2006.259.07:30:00.14/onsource/TRACKING 2006.259.07:30:00.14/wx/22.41,1012.8,83 2006.259.07:30:00.31/cable/+6.4584E-03 2006.259.07:30:01.40/va/01,08,usb,yes,31,33 2006.259.07:30:01.40/va/02,07,usb,yes,31,33 2006.259.07:30:01.40/va/03,08,usb,yes,23,24 2006.259.07:30:01.40/va/04,07,usb,yes,32,35 2006.259.07:30:01.40/va/05,07,usb,yes,36,38 2006.259.07:30:01.40/va/06,06,usb,yes,35,35 2006.259.07:30:01.40/va/07,06,usb,yes,36,35 2006.259.07:30:01.40/va/08,06,usb,yes,38,37 2006.259.07:30:01.63/valo/01,532.99,yes,locked 2006.259.07:30:01.63/valo/02,572.99,yes,locked 2006.259.07:30:01.63/valo/03,672.99,yes,locked 2006.259.07:30:01.63/valo/04,832.99,yes,locked 2006.259.07:30:01.63/valo/05,652.99,yes,locked 2006.259.07:30:01.63/valo/06,772.99,yes,locked 2006.259.07:30:01.63/valo/07,832.99,yes,locked 2006.259.07:30:01.63/valo/08,852.99,yes,locked 2006.259.07:30:02.72/vb/01,04,usb,yes,31,29 2006.259.07:30:02.72/vb/02,05,usb,yes,29,30 2006.259.07:30:02.72/vb/03,04,usb,yes,29,32 2006.259.07:30:02.72/vb/04,05,usb,yes,26,26 2006.259.07:30:02.72/vb/05,04,usb,yes,28,32 2006.259.07:30:02.72/vb/06,04,usb,yes,29,32 2006.259.07:30:02.72/vb/07,04,usb,yes,31,31 2006.259.07:30:02.72/vb/08,04,usb,yes,28,32 2006.259.07:30:02.95/vblo/01,632.99,yes,locked 2006.259.07:30:02.95/vblo/02,640.99,yes,locked 2006.259.07:30:02.95/vblo/03,656.99,yes,locked 2006.259.07:30:02.95/vblo/04,712.99,yes,locked 2006.259.07:30:02.95/vblo/05,744.99,yes,locked 2006.259.07:30:02.95/vblo/06,752.99,yes,locked 2006.259.07:30:02.95/vblo/07,734.99,yes,locked 2006.259.07:30:02.95/vblo/08,744.99,yes,locked 2006.259.07:30:03.10/vabw/8 2006.259.07:30:03.25/vbbw/8 2006.259.07:30:03.34/xfe/off,on,15.2 2006.259.07:30:03.72/ifatt/23,28,28,28 2006.259.07:30:04.07/fmout-gps/S +4.50E-07 2006.259.07:30:04.12:!2006.259.07:31:00 2006.259.07:31:00.01:data_valid=off 2006.259.07:31:00.02:postob 2006.259.07:31:00.02&postob/cable 2006.259.07:31:00.02&postob/wx 2006.259.07:31:00.03&postob/clockoff 2006.259.07:31:00.23/cable/+6.4578E-03 2006.259.07:31:00.23/wx/22.40,1012.8,84 2006.259.07:31:00.29/fmout-gps/S +4.50E-07 2006.259.07:31:00.29:scan_name=259-0733,k06259,60 2006.259.07:31:00.30:source=0059+581,010245.76,582411.1,2000.0,cw 2006.259.07:31:01.13#flagr#flagr/antenna,new-source 2006.259.07:31:01.14:checkk5 2006.259.07:31:01.14&checkk5/chk_autoobs=1 2006.259.07:31:01.14&checkk5/chk_autoobs=2 2006.259.07:31:01.14&checkk5/chk_autoobs=3 2006.259.07:31:01.14&checkk5/chk_autoobs=4 2006.259.07:31:01.14&checkk5/chk_obsdata=1 2006.259.07:31:01.14&checkk5/chk_obsdata=2 2006.259.07:31:01.14&checkk5/chk_obsdata=3 2006.259.07:31:01.14&checkk5/chk_obsdata=4 2006.259.07:31:01.14&checkk5/k5log=1 2006.259.07:31:01.14&checkk5/k5log=2 2006.259.07:31:01.14&checkk5/k5log=3 2006.259.07:31:01.14&checkk5/k5log=4 2006.259.07:31:01.14&checkk5/obsinfo 2006.259.07:31:01.57/chk_autoobs//k5ts1/ autoobs is running! 2006.259.07:31:02.19/chk_autoobs//k5ts2/ autoobs is running! 2006.259.07:31:02.59/chk_autoobs//k5ts3/ autoobs is running! 2006.259.07:31:03.06/chk_autoobs//k5ts4/ autoobs is running! 2006.259.07:31:03.47/chk_obsdata//k5ts1/T2590730??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.259.07:31:03.87/chk_obsdata//k5ts2/T2590730??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.259.07:31:04.49/chk_obsdata//k5ts3/T2590730??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.259.07:31:04.91/chk_obsdata//k5ts4/T2590730??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.259.07:31:05.68/k5log//k5ts1_log_newline 2006.259.07:31:06.45/k5log//k5ts2_log_newline 2006.259.07:31:07.22/k5log//k5ts3_log_newline 2006.259.07:31:08.20/k5log//k5ts4_log_newline 2006.259.07:31:08.22/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.259.07:31:08.23:4f8m12a=1 2006.259.07:31:08.23$4f8m12a/echo=on 2006.259.07:31:08.23$4f8m12a/pcalon 2006.259.07:31:08.23$pcalon/"no phase cal control is implemented here 2006.259.07:31:08.23$4f8m12a/"tpicd=stop 2006.259.07:31:08.23$4f8m12a/vc4f8 2006.259.07:31:08.23$vc4f8/valo=1,532.99 2006.259.07:31:08.23#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.259.07:31:08.23#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.259.07:31:08.23#ibcon#ireg 17 cls_cnt 0 2006.259.07:31:08.23#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.259.07:31:08.23#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.259.07:31:08.23#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.259.07:31:08.23#ibcon#enter wrdev, iclass 29, count 0 2006.259.07:31:08.23#ibcon#first serial, iclass 29, count 0 2006.259.07:31:08.23#ibcon#enter sib2, iclass 29, count 0 2006.259.07:31:08.23#ibcon#flushed, iclass 29, count 0 2006.259.07:31:08.23#ibcon#about to write, iclass 29, count 0 2006.259.07:31:08.23#ibcon#wrote, iclass 29, count 0 2006.259.07:31:08.23#ibcon#about to read 3, iclass 29, count 0 2006.259.07:31:08.27#ibcon#read 3, iclass 29, count 0 2006.259.07:31:08.27#ibcon#about to read 4, iclass 29, count 0 2006.259.07:31:08.27#ibcon#read 4, iclass 29, count 0 2006.259.07:31:08.27#ibcon#about to read 5, iclass 29, count 0 2006.259.07:31:08.27#ibcon#read 5, iclass 29, count 0 2006.259.07:31:08.27#ibcon#about to read 6, iclass 29, count 0 2006.259.07:31:08.27#ibcon#read 6, iclass 29, count 0 2006.259.07:31:08.27#ibcon#end of sib2, iclass 29, count 0 2006.259.07:31:08.27#ibcon#*mode == 0, iclass 29, count 0 2006.259.07:31:08.27#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.259.07:31:08.27#ibcon#[26=FRQ=01,532.99\r\n] 2006.259.07:31:08.27#ibcon#*before write, iclass 29, count 0 2006.259.07:31:08.27#ibcon#enter sib2, iclass 29, count 0 2006.259.07:31:08.27#ibcon#flushed, iclass 29, count 0 2006.259.07:31:08.27#ibcon#about to write, iclass 29, count 0 2006.259.07:31:08.27#ibcon#wrote, iclass 29, count 0 2006.259.07:31:08.27#ibcon#about to read 3, iclass 29, count 0 2006.259.07:31:08.32#ibcon#read 3, iclass 29, count 0 2006.259.07:31:08.32#ibcon#about to read 4, iclass 29, count 0 2006.259.07:31:08.32#ibcon#read 4, iclass 29, count 0 2006.259.07:31:08.32#ibcon#about to read 5, iclass 29, count 0 2006.259.07:31:08.32#ibcon#read 5, iclass 29, count 0 2006.259.07:31:08.32#ibcon#about to read 6, iclass 29, count 0 2006.259.07:31:08.32#ibcon#read 6, iclass 29, count 0 2006.259.07:31:08.32#ibcon#end of sib2, iclass 29, count 0 2006.259.07:31:08.32#ibcon#*after write, iclass 29, count 0 2006.259.07:31:08.32#ibcon#*before return 0, iclass 29, count 0 2006.259.07:31:08.32#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.259.07:31:08.32#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.259.07:31:08.32#ibcon#about to clear, iclass 29 cls_cnt 0 2006.259.07:31:08.32#ibcon#cleared, iclass 29 cls_cnt 0 2006.259.07:31:08.32$vc4f8/va=1,8 2006.259.07:31:08.32#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.259.07:31:08.32#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.259.07:31:08.32#ibcon#ireg 11 cls_cnt 2 2006.259.07:31:08.32#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.259.07:31:08.32#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.259.07:31:08.32#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.259.07:31:08.32#ibcon#enter wrdev, iclass 31, count 2 2006.259.07:31:08.32#ibcon#first serial, iclass 31, count 2 2006.259.07:31:08.32#ibcon#enter sib2, iclass 31, count 2 2006.259.07:31:08.32#ibcon#flushed, iclass 31, count 2 2006.259.07:31:08.32#ibcon#about to write, iclass 31, count 2 2006.259.07:31:08.32#ibcon#wrote, iclass 31, count 2 2006.259.07:31:08.32#ibcon#about to read 3, iclass 31, count 2 2006.259.07:31:08.35#ibcon#read 3, iclass 31, count 2 2006.259.07:31:08.35#ibcon#about to read 4, iclass 31, count 2 2006.259.07:31:08.35#ibcon#read 4, iclass 31, count 2 2006.259.07:31:08.35#ibcon#about to read 5, iclass 31, count 2 2006.259.07:31:08.35#ibcon#read 5, iclass 31, count 2 2006.259.07:31:08.35#ibcon#about to read 6, iclass 31, count 2 2006.259.07:31:08.35#ibcon#read 6, iclass 31, count 2 2006.259.07:31:08.35#ibcon#end of sib2, iclass 31, count 2 2006.259.07:31:08.35#ibcon#*mode == 0, iclass 31, count 2 2006.259.07:31:08.35#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.259.07:31:08.35#ibcon#[25=AT01-08\r\n] 2006.259.07:31:08.35#ibcon#*before write, iclass 31, count 2 2006.259.07:31:08.35#ibcon#enter sib2, iclass 31, count 2 2006.259.07:31:08.35#ibcon#flushed, iclass 31, count 2 2006.259.07:31:08.35#ibcon#about to write, iclass 31, count 2 2006.259.07:31:08.35#ibcon#wrote, iclass 31, count 2 2006.259.07:31:08.35#ibcon#about to read 3, iclass 31, count 2 2006.259.07:31:08.38#ibcon#read 3, iclass 31, count 2 2006.259.07:31:08.38#ibcon#about to read 4, iclass 31, count 2 2006.259.07:31:08.38#ibcon#read 4, iclass 31, count 2 2006.259.07:31:08.38#ibcon#about to read 5, iclass 31, count 2 2006.259.07:31:08.38#ibcon#read 5, iclass 31, count 2 2006.259.07:31:08.38#ibcon#about to read 6, iclass 31, count 2 2006.259.07:31:08.38#ibcon#read 6, iclass 31, count 2 2006.259.07:31:08.38#ibcon#end of sib2, iclass 31, count 2 2006.259.07:31:08.38#ibcon#*after write, iclass 31, count 2 2006.259.07:31:08.38#ibcon#*before return 0, iclass 31, count 2 2006.259.07:31:08.38#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.259.07:31:08.38#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.259.07:31:08.38#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.259.07:31:08.38#ibcon#ireg 7 cls_cnt 0 2006.259.07:31:08.38#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.259.07:31:08.50#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.259.07:31:08.50#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.259.07:31:08.50#ibcon#enter wrdev, iclass 31, count 0 2006.259.07:31:08.50#ibcon#first serial, iclass 31, count 0 2006.259.07:31:08.50#ibcon#enter sib2, iclass 31, count 0 2006.259.07:31:08.50#ibcon#flushed, iclass 31, count 0 2006.259.07:31:08.50#ibcon#about to write, iclass 31, count 0 2006.259.07:31:08.50#ibcon#wrote, iclass 31, count 0 2006.259.07:31:08.50#ibcon#about to read 3, iclass 31, count 0 2006.259.07:31:08.52#ibcon#read 3, iclass 31, count 0 2006.259.07:31:08.52#ibcon#about to read 4, iclass 31, count 0 2006.259.07:31:08.52#ibcon#read 4, iclass 31, count 0 2006.259.07:31:08.52#ibcon#about to read 5, iclass 31, count 0 2006.259.07:31:08.52#ibcon#read 5, iclass 31, count 0 2006.259.07:31:08.52#ibcon#about to read 6, iclass 31, count 0 2006.259.07:31:08.52#ibcon#read 6, iclass 31, count 0 2006.259.07:31:08.52#ibcon#end of sib2, iclass 31, count 0 2006.259.07:31:08.52#ibcon#*mode == 0, iclass 31, count 0 2006.259.07:31:08.52#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.259.07:31:08.52#ibcon#[25=USB\r\n] 2006.259.07:31:08.52#ibcon#*before write, iclass 31, count 0 2006.259.07:31:08.52#ibcon#enter sib2, iclass 31, count 0 2006.259.07:31:08.52#ibcon#flushed, iclass 31, count 0 2006.259.07:31:08.52#ibcon#about to write, iclass 31, count 0 2006.259.07:31:08.52#ibcon#wrote, iclass 31, count 0 2006.259.07:31:08.52#ibcon#about to read 3, iclass 31, count 0 2006.259.07:31:08.55#ibcon#read 3, iclass 31, count 0 2006.259.07:31:08.55#ibcon#about to read 4, iclass 31, count 0 2006.259.07:31:08.55#ibcon#read 4, iclass 31, count 0 2006.259.07:31:08.55#ibcon#about to read 5, iclass 31, count 0 2006.259.07:31:08.55#ibcon#read 5, iclass 31, count 0 2006.259.07:31:08.55#ibcon#about to read 6, iclass 31, count 0 2006.259.07:31:08.55#ibcon#read 6, iclass 31, count 0 2006.259.07:31:08.55#ibcon#end of sib2, iclass 31, count 0 2006.259.07:31:08.55#ibcon#*after write, iclass 31, count 0 2006.259.07:31:08.55#ibcon#*before return 0, iclass 31, count 0 2006.259.07:31:08.55#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.259.07:31:08.55#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.259.07:31:08.55#ibcon#about to clear, iclass 31 cls_cnt 0 2006.259.07:31:08.55#ibcon#cleared, iclass 31 cls_cnt 0 2006.259.07:31:08.55$vc4f8/valo=2,572.99 2006.259.07:31:08.55#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.259.07:31:08.55#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.259.07:31:08.55#ibcon#ireg 17 cls_cnt 0 2006.259.07:31:08.55#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.259.07:31:08.55#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.259.07:31:08.55#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.259.07:31:08.55#ibcon#enter wrdev, iclass 33, count 0 2006.259.07:31:08.55#ibcon#first serial, iclass 33, count 0 2006.259.07:31:08.55#ibcon#enter sib2, iclass 33, count 0 2006.259.07:31:08.55#ibcon#flushed, iclass 33, count 0 2006.259.07:31:08.55#ibcon#about to write, iclass 33, count 0 2006.259.07:31:08.55#ibcon#wrote, iclass 33, count 0 2006.259.07:31:08.55#ibcon#about to read 3, iclass 33, count 0 2006.259.07:31:08.57#ibcon#read 3, iclass 33, count 0 2006.259.07:31:08.57#ibcon#about to read 4, iclass 33, count 0 2006.259.07:31:08.57#ibcon#read 4, iclass 33, count 0 2006.259.07:31:08.57#ibcon#about to read 5, iclass 33, count 0 2006.259.07:31:08.57#ibcon#read 5, iclass 33, count 0 2006.259.07:31:08.57#ibcon#about to read 6, iclass 33, count 0 2006.259.07:31:08.57#ibcon#read 6, iclass 33, count 0 2006.259.07:31:08.57#ibcon#end of sib2, iclass 33, count 0 2006.259.07:31:08.57#ibcon#*mode == 0, iclass 33, count 0 2006.259.07:31:08.57#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.259.07:31:08.57#ibcon#[26=FRQ=02,572.99\r\n] 2006.259.07:31:08.57#ibcon#*before write, iclass 33, count 0 2006.259.07:31:08.57#ibcon#enter sib2, iclass 33, count 0 2006.259.07:31:08.57#ibcon#flushed, iclass 33, count 0 2006.259.07:31:08.57#ibcon#about to write, iclass 33, count 0 2006.259.07:31:08.57#ibcon#wrote, iclass 33, count 0 2006.259.07:31:08.57#ibcon#about to read 3, iclass 33, count 0 2006.259.07:31:08.61#ibcon#read 3, iclass 33, count 0 2006.259.07:31:08.61#ibcon#about to read 4, iclass 33, count 0 2006.259.07:31:08.61#ibcon#read 4, iclass 33, count 0 2006.259.07:31:08.61#ibcon#about to read 5, iclass 33, count 0 2006.259.07:31:08.61#ibcon#read 5, iclass 33, count 0 2006.259.07:31:08.61#ibcon#about to read 6, iclass 33, count 0 2006.259.07:31:08.61#ibcon#read 6, iclass 33, count 0 2006.259.07:31:08.61#ibcon#end of sib2, iclass 33, count 0 2006.259.07:31:08.61#ibcon#*after write, iclass 33, count 0 2006.259.07:31:08.61#ibcon#*before return 0, iclass 33, count 0 2006.259.07:31:08.61#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.259.07:31:08.61#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.259.07:31:08.61#ibcon#about to clear, iclass 33 cls_cnt 0 2006.259.07:31:08.61#ibcon#cleared, iclass 33 cls_cnt 0 2006.259.07:31:08.61$vc4f8/va=2,7 2006.259.07:31:08.61#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.259.07:31:08.61#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.259.07:31:08.61#ibcon#ireg 11 cls_cnt 2 2006.259.07:31:08.61#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.259.07:31:08.68#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.259.07:31:08.68#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.259.07:31:08.68#ibcon#enter wrdev, iclass 35, count 2 2006.259.07:31:08.68#ibcon#first serial, iclass 35, count 2 2006.259.07:31:08.68#ibcon#enter sib2, iclass 35, count 2 2006.259.07:31:08.68#ibcon#flushed, iclass 35, count 2 2006.259.07:31:08.68#ibcon#about to write, iclass 35, count 2 2006.259.07:31:08.68#ibcon#wrote, iclass 35, count 2 2006.259.07:31:08.68#ibcon#about to read 3, iclass 35, count 2 2006.259.07:31:08.69#ibcon#read 3, iclass 35, count 2 2006.259.07:31:08.69#ibcon#about to read 4, iclass 35, count 2 2006.259.07:31:08.69#ibcon#read 4, iclass 35, count 2 2006.259.07:31:08.69#ibcon#about to read 5, iclass 35, count 2 2006.259.07:31:08.69#ibcon#read 5, iclass 35, count 2 2006.259.07:31:08.69#ibcon#about to read 6, iclass 35, count 2 2006.259.07:31:08.69#ibcon#read 6, iclass 35, count 2 2006.259.07:31:08.69#ibcon#end of sib2, iclass 35, count 2 2006.259.07:31:08.69#ibcon#*mode == 0, iclass 35, count 2 2006.259.07:31:08.69#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.259.07:31:08.69#ibcon#[25=AT02-07\r\n] 2006.259.07:31:08.69#ibcon#*before write, iclass 35, count 2 2006.259.07:31:08.69#ibcon#enter sib2, iclass 35, count 2 2006.259.07:31:08.69#ibcon#flushed, iclass 35, count 2 2006.259.07:31:08.69#ibcon#about to write, iclass 35, count 2 2006.259.07:31:08.69#ibcon#wrote, iclass 35, count 2 2006.259.07:31:08.69#ibcon#about to read 3, iclass 35, count 2 2006.259.07:31:08.72#ibcon#read 3, iclass 35, count 2 2006.259.07:31:08.72#ibcon#about to read 4, iclass 35, count 2 2006.259.07:31:08.72#ibcon#read 4, iclass 35, count 2 2006.259.07:31:08.72#ibcon#about to read 5, iclass 35, count 2 2006.259.07:31:08.72#ibcon#read 5, iclass 35, count 2 2006.259.07:31:08.72#ibcon#about to read 6, iclass 35, count 2 2006.259.07:31:08.72#ibcon#read 6, iclass 35, count 2 2006.259.07:31:08.72#ibcon#end of sib2, iclass 35, count 2 2006.259.07:31:08.72#ibcon#*after write, iclass 35, count 2 2006.259.07:31:08.72#ibcon#*before return 0, iclass 35, count 2 2006.259.07:31:08.72#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.259.07:31:08.72#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.259.07:31:08.72#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.259.07:31:08.72#ibcon#ireg 7 cls_cnt 0 2006.259.07:31:08.72#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.259.07:31:08.84#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.259.07:31:08.84#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.259.07:31:08.84#ibcon#enter wrdev, iclass 35, count 0 2006.259.07:31:08.84#ibcon#first serial, iclass 35, count 0 2006.259.07:31:08.84#ibcon#enter sib2, iclass 35, count 0 2006.259.07:31:08.84#ibcon#flushed, iclass 35, count 0 2006.259.07:31:08.84#ibcon#about to write, iclass 35, count 0 2006.259.07:31:08.84#ibcon#wrote, iclass 35, count 0 2006.259.07:31:08.84#ibcon#about to read 3, iclass 35, count 0 2006.259.07:31:08.86#ibcon#read 3, iclass 35, count 0 2006.259.07:31:08.86#ibcon#about to read 4, iclass 35, count 0 2006.259.07:31:08.86#ibcon#read 4, iclass 35, count 0 2006.259.07:31:08.86#ibcon#about to read 5, iclass 35, count 0 2006.259.07:31:08.86#ibcon#read 5, iclass 35, count 0 2006.259.07:31:08.86#ibcon#about to read 6, iclass 35, count 0 2006.259.07:31:08.86#ibcon#read 6, iclass 35, count 0 2006.259.07:31:08.86#ibcon#end of sib2, iclass 35, count 0 2006.259.07:31:08.86#ibcon#*mode == 0, iclass 35, count 0 2006.259.07:31:08.86#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.259.07:31:08.86#ibcon#[25=USB\r\n] 2006.259.07:31:08.86#ibcon#*before write, iclass 35, count 0 2006.259.07:31:08.86#ibcon#enter sib2, iclass 35, count 0 2006.259.07:31:08.86#ibcon#flushed, iclass 35, count 0 2006.259.07:31:08.86#ibcon#about to write, iclass 35, count 0 2006.259.07:31:08.86#ibcon#wrote, iclass 35, count 0 2006.259.07:31:08.86#ibcon#about to read 3, iclass 35, count 0 2006.259.07:31:08.89#ibcon#read 3, iclass 35, count 0 2006.259.07:31:08.89#ibcon#about to read 4, iclass 35, count 0 2006.259.07:31:08.89#ibcon#read 4, iclass 35, count 0 2006.259.07:31:08.89#ibcon#about to read 5, iclass 35, count 0 2006.259.07:31:08.89#ibcon#read 5, iclass 35, count 0 2006.259.07:31:08.89#ibcon#about to read 6, iclass 35, count 0 2006.259.07:31:08.89#ibcon#read 6, iclass 35, count 0 2006.259.07:31:08.89#ibcon#end of sib2, iclass 35, count 0 2006.259.07:31:08.89#ibcon#*after write, iclass 35, count 0 2006.259.07:31:08.89#ibcon#*before return 0, iclass 35, count 0 2006.259.07:31:08.89#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.259.07:31:08.89#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.259.07:31:08.89#ibcon#about to clear, iclass 35 cls_cnt 0 2006.259.07:31:08.89#ibcon#cleared, iclass 35 cls_cnt 0 2006.259.07:31:08.89$vc4f8/valo=3,672.99 2006.259.07:31:08.89#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.259.07:31:08.89#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.259.07:31:08.89#ibcon#ireg 17 cls_cnt 0 2006.259.07:31:08.89#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.259.07:31:08.89#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.259.07:31:08.89#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.259.07:31:08.89#ibcon#enter wrdev, iclass 37, count 0 2006.259.07:31:08.89#ibcon#first serial, iclass 37, count 0 2006.259.07:31:08.89#ibcon#enter sib2, iclass 37, count 0 2006.259.07:31:08.89#ibcon#flushed, iclass 37, count 0 2006.259.07:31:08.89#ibcon#about to write, iclass 37, count 0 2006.259.07:31:08.89#ibcon#wrote, iclass 37, count 0 2006.259.07:31:08.89#ibcon#about to read 3, iclass 37, count 0 2006.259.07:31:08.91#ibcon#read 3, iclass 37, count 0 2006.259.07:31:08.91#ibcon#about to read 4, iclass 37, count 0 2006.259.07:31:08.91#ibcon#read 4, iclass 37, count 0 2006.259.07:31:08.91#ibcon#about to read 5, iclass 37, count 0 2006.259.07:31:08.91#ibcon#read 5, iclass 37, count 0 2006.259.07:31:08.91#ibcon#about to read 6, iclass 37, count 0 2006.259.07:31:08.91#ibcon#read 6, iclass 37, count 0 2006.259.07:31:08.91#ibcon#end of sib2, iclass 37, count 0 2006.259.07:31:08.91#ibcon#*mode == 0, iclass 37, count 0 2006.259.07:31:08.91#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.259.07:31:08.91#ibcon#[26=FRQ=03,672.99\r\n] 2006.259.07:31:08.91#ibcon#*before write, iclass 37, count 0 2006.259.07:31:08.91#ibcon#enter sib2, iclass 37, count 0 2006.259.07:31:08.91#ibcon#flushed, iclass 37, count 0 2006.259.07:31:08.91#ibcon#about to write, iclass 37, count 0 2006.259.07:31:08.91#ibcon#wrote, iclass 37, count 0 2006.259.07:31:08.91#ibcon#about to read 3, iclass 37, count 0 2006.259.07:31:08.95#ibcon#read 3, iclass 37, count 0 2006.259.07:31:08.95#ibcon#about to read 4, iclass 37, count 0 2006.259.07:31:08.95#ibcon#read 4, iclass 37, count 0 2006.259.07:31:08.95#ibcon#about to read 5, iclass 37, count 0 2006.259.07:31:08.95#ibcon#read 5, iclass 37, count 0 2006.259.07:31:08.95#ibcon#about to read 6, iclass 37, count 0 2006.259.07:31:08.95#ibcon#read 6, iclass 37, count 0 2006.259.07:31:08.95#ibcon#end of sib2, iclass 37, count 0 2006.259.07:31:08.95#ibcon#*after write, iclass 37, count 0 2006.259.07:31:08.95#ibcon#*before return 0, iclass 37, count 0 2006.259.07:31:08.95#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.259.07:31:08.95#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.259.07:31:08.95#ibcon#about to clear, iclass 37 cls_cnt 0 2006.259.07:31:08.95#ibcon#cleared, iclass 37 cls_cnt 0 2006.259.07:31:08.95$vc4f8/va=3,8 2006.259.07:31:08.95#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.259.07:31:08.95#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.259.07:31:08.95#ibcon#ireg 11 cls_cnt 2 2006.259.07:31:08.95#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.259.07:31:09.02#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.259.07:31:09.02#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.259.07:31:09.02#ibcon#enter wrdev, iclass 39, count 2 2006.259.07:31:09.02#ibcon#first serial, iclass 39, count 2 2006.259.07:31:09.02#ibcon#enter sib2, iclass 39, count 2 2006.259.07:31:09.02#ibcon#flushed, iclass 39, count 2 2006.259.07:31:09.02#ibcon#about to write, iclass 39, count 2 2006.259.07:31:09.02#ibcon#wrote, iclass 39, count 2 2006.259.07:31:09.02#ibcon#about to read 3, iclass 39, count 2 2006.259.07:31:09.03#ibcon#read 3, iclass 39, count 2 2006.259.07:31:09.03#ibcon#about to read 4, iclass 39, count 2 2006.259.07:31:09.03#ibcon#read 4, iclass 39, count 2 2006.259.07:31:09.03#ibcon#about to read 5, iclass 39, count 2 2006.259.07:31:09.03#ibcon#read 5, iclass 39, count 2 2006.259.07:31:09.03#ibcon#about to read 6, iclass 39, count 2 2006.259.07:31:09.03#ibcon#read 6, iclass 39, count 2 2006.259.07:31:09.03#ibcon#end of sib2, iclass 39, count 2 2006.259.07:31:09.03#ibcon#*mode == 0, iclass 39, count 2 2006.259.07:31:09.03#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.259.07:31:09.03#ibcon#[25=AT03-08\r\n] 2006.259.07:31:09.03#ibcon#*before write, iclass 39, count 2 2006.259.07:31:09.03#ibcon#enter sib2, iclass 39, count 2 2006.259.07:31:09.03#ibcon#flushed, iclass 39, count 2 2006.259.07:31:09.03#ibcon#about to write, iclass 39, count 2 2006.259.07:31:09.03#ibcon#wrote, iclass 39, count 2 2006.259.07:31:09.03#ibcon#about to read 3, iclass 39, count 2 2006.259.07:31:09.06#ibcon#read 3, iclass 39, count 2 2006.259.07:31:09.06#ibcon#about to read 4, iclass 39, count 2 2006.259.07:31:09.06#ibcon#read 4, iclass 39, count 2 2006.259.07:31:09.06#ibcon#about to read 5, iclass 39, count 2 2006.259.07:31:09.06#ibcon#read 5, iclass 39, count 2 2006.259.07:31:09.06#ibcon#about to read 6, iclass 39, count 2 2006.259.07:31:09.06#ibcon#read 6, iclass 39, count 2 2006.259.07:31:09.06#ibcon#end of sib2, iclass 39, count 2 2006.259.07:31:09.06#ibcon#*after write, iclass 39, count 2 2006.259.07:31:09.06#ibcon#*before return 0, iclass 39, count 2 2006.259.07:31:09.06#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.259.07:31:09.06#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.259.07:31:09.06#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.259.07:31:09.06#ibcon#ireg 7 cls_cnt 0 2006.259.07:31:09.06#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.259.07:31:09.18#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.259.07:31:09.18#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.259.07:31:09.18#ibcon#enter wrdev, iclass 39, count 0 2006.259.07:31:09.18#ibcon#first serial, iclass 39, count 0 2006.259.07:31:09.18#ibcon#enter sib2, iclass 39, count 0 2006.259.07:31:09.18#ibcon#flushed, iclass 39, count 0 2006.259.07:31:09.18#ibcon#about to write, iclass 39, count 0 2006.259.07:31:09.18#ibcon#wrote, iclass 39, count 0 2006.259.07:31:09.18#ibcon#about to read 3, iclass 39, count 0 2006.259.07:31:09.20#ibcon#read 3, iclass 39, count 0 2006.259.07:31:09.20#ibcon#about to read 4, iclass 39, count 0 2006.259.07:31:09.20#ibcon#read 4, iclass 39, count 0 2006.259.07:31:09.20#ibcon#about to read 5, iclass 39, count 0 2006.259.07:31:09.20#ibcon#read 5, iclass 39, count 0 2006.259.07:31:09.20#ibcon#about to read 6, iclass 39, count 0 2006.259.07:31:09.20#ibcon#read 6, iclass 39, count 0 2006.259.07:31:09.20#ibcon#end of sib2, iclass 39, count 0 2006.259.07:31:09.20#ibcon#*mode == 0, iclass 39, count 0 2006.259.07:31:09.20#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.259.07:31:09.20#ibcon#[25=USB\r\n] 2006.259.07:31:09.20#ibcon#*before write, iclass 39, count 0 2006.259.07:31:09.20#ibcon#enter sib2, iclass 39, count 0 2006.259.07:31:09.20#ibcon#flushed, iclass 39, count 0 2006.259.07:31:09.20#ibcon#about to write, iclass 39, count 0 2006.259.07:31:09.20#ibcon#wrote, iclass 39, count 0 2006.259.07:31:09.20#ibcon#about to read 3, iclass 39, count 0 2006.259.07:31:09.23#ibcon#read 3, iclass 39, count 0 2006.259.07:31:09.23#ibcon#about to read 4, iclass 39, count 0 2006.259.07:31:09.23#ibcon#read 4, iclass 39, count 0 2006.259.07:31:09.23#ibcon#about to read 5, iclass 39, count 0 2006.259.07:31:09.23#ibcon#read 5, iclass 39, count 0 2006.259.07:31:09.23#ibcon#about to read 6, iclass 39, count 0 2006.259.07:31:09.23#ibcon#read 6, iclass 39, count 0 2006.259.07:31:09.23#ibcon#end of sib2, iclass 39, count 0 2006.259.07:31:09.23#ibcon#*after write, iclass 39, count 0 2006.259.07:31:09.23#ibcon#*before return 0, iclass 39, count 0 2006.259.07:31:09.23#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.259.07:31:09.23#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.259.07:31:09.23#ibcon#about to clear, iclass 39 cls_cnt 0 2006.259.07:31:09.23#ibcon#cleared, iclass 39 cls_cnt 0 2006.259.07:31:09.23$vc4f8/valo=4,832.99 2006.259.07:31:09.23#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.259.07:31:09.23#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.259.07:31:09.23#ibcon#ireg 17 cls_cnt 0 2006.259.07:31:09.23#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.259.07:31:09.23#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.259.07:31:09.23#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.259.07:31:09.23#ibcon#enter wrdev, iclass 3, count 0 2006.259.07:31:09.23#ibcon#first serial, iclass 3, count 0 2006.259.07:31:09.23#ibcon#enter sib2, iclass 3, count 0 2006.259.07:31:09.23#ibcon#flushed, iclass 3, count 0 2006.259.07:31:09.23#ibcon#about to write, iclass 3, count 0 2006.259.07:31:09.23#ibcon#wrote, iclass 3, count 0 2006.259.07:31:09.23#ibcon#about to read 3, iclass 3, count 0 2006.259.07:31:09.25#ibcon#read 3, iclass 3, count 0 2006.259.07:31:09.25#ibcon#about to read 4, iclass 3, count 0 2006.259.07:31:09.25#ibcon#read 4, iclass 3, count 0 2006.259.07:31:09.25#ibcon#about to read 5, iclass 3, count 0 2006.259.07:31:09.25#ibcon#read 5, iclass 3, count 0 2006.259.07:31:09.25#ibcon#about to read 6, iclass 3, count 0 2006.259.07:31:09.25#ibcon#read 6, iclass 3, count 0 2006.259.07:31:09.25#ibcon#end of sib2, iclass 3, count 0 2006.259.07:31:09.25#ibcon#*mode == 0, iclass 3, count 0 2006.259.07:31:09.25#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.259.07:31:09.25#ibcon#[26=FRQ=04,832.99\r\n] 2006.259.07:31:09.25#ibcon#*before write, iclass 3, count 0 2006.259.07:31:09.25#ibcon#enter sib2, iclass 3, count 0 2006.259.07:31:09.25#ibcon#flushed, iclass 3, count 0 2006.259.07:31:09.25#ibcon#about to write, iclass 3, count 0 2006.259.07:31:09.25#ibcon#wrote, iclass 3, count 0 2006.259.07:31:09.25#ibcon#about to read 3, iclass 3, count 0 2006.259.07:31:09.29#ibcon#read 3, iclass 3, count 0 2006.259.07:31:09.29#ibcon#about to read 4, iclass 3, count 0 2006.259.07:31:09.29#ibcon#read 4, iclass 3, count 0 2006.259.07:31:09.29#ibcon#about to read 5, iclass 3, count 0 2006.259.07:31:09.29#ibcon#read 5, iclass 3, count 0 2006.259.07:31:09.29#ibcon#about to read 6, iclass 3, count 0 2006.259.07:31:09.29#ibcon#read 6, iclass 3, count 0 2006.259.07:31:09.29#ibcon#end of sib2, iclass 3, count 0 2006.259.07:31:09.29#ibcon#*after write, iclass 3, count 0 2006.259.07:31:09.29#ibcon#*before return 0, iclass 3, count 0 2006.259.07:31:09.29#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.259.07:31:09.29#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.259.07:31:09.29#ibcon#about to clear, iclass 3 cls_cnt 0 2006.259.07:31:09.29#ibcon#cleared, iclass 3 cls_cnt 0 2006.259.07:31:09.29$vc4f8/va=4,7 2006.259.07:31:09.29#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.259.07:31:09.29#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.259.07:31:09.29#ibcon#ireg 11 cls_cnt 2 2006.259.07:31:09.29#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.259.07:31:09.35#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.259.07:31:09.35#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.259.07:31:09.35#ibcon#enter wrdev, iclass 5, count 2 2006.259.07:31:09.35#ibcon#first serial, iclass 5, count 2 2006.259.07:31:09.35#ibcon#enter sib2, iclass 5, count 2 2006.259.07:31:09.35#ibcon#flushed, iclass 5, count 2 2006.259.07:31:09.35#ibcon#about to write, iclass 5, count 2 2006.259.07:31:09.35#ibcon#wrote, iclass 5, count 2 2006.259.07:31:09.35#ibcon#about to read 3, iclass 5, count 2 2006.259.07:31:09.37#ibcon#read 3, iclass 5, count 2 2006.259.07:31:09.37#ibcon#about to read 4, iclass 5, count 2 2006.259.07:31:09.37#ibcon#read 4, iclass 5, count 2 2006.259.07:31:09.37#ibcon#about to read 5, iclass 5, count 2 2006.259.07:31:09.37#ibcon#read 5, iclass 5, count 2 2006.259.07:31:09.37#ibcon#about to read 6, iclass 5, count 2 2006.259.07:31:09.37#ibcon#read 6, iclass 5, count 2 2006.259.07:31:09.37#ibcon#end of sib2, iclass 5, count 2 2006.259.07:31:09.37#ibcon#*mode == 0, iclass 5, count 2 2006.259.07:31:09.37#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.259.07:31:09.37#ibcon#[25=AT04-07\r\n] 2006.259.07:31:09.37#ibcon#*before write, iclass 5, count 2 2006.259.07:31:09.37#ibcon#enter sib2, iclass 5, count 2 2006.259.07:31:09.37#ibcon#flushed, iclass 5, count 2 2006.259.07:31:09.37#ibcon#about to write, iclass 5, count 2 2006.259.07:31:09.37#ibcon#wrote, iclass 5, count 2 2006.259.07:31:09.37#ibcon#about to read 3, iclass 5, count 2 2006.259.07:31:09.40#ibcon#read 3, iclass 5, count 2 2006.259.07:31:09.40#ibcon#about to read 4, iclass 5, count 2 2006.259.07:31:09.40#ibcon#read 4, iclass 5, count 2 2006.259.07:31:09.40#ibcon#about to read 5, iclass 5, count 2 2006.259.07:31:09.40#ibcon#read 5, iclass 5, count 2 2006.259.07:31:09.40#ibcon#about to read 6, iclass 5, count 2 2006.259.07:31:09.40#ibcon#read 6, iclass 5, count 2 2006.259.07:31:09.40#ibcon#end of sib2, iclass 5, count 2 2006.259.07:31:09.40#ibcon#*after write, iclass 5, count 2 2006.259.07:31:09.40#ibcon#*before return 0, iclass 5, count 2 2006.259.07:31:09.40#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.259.07:31:09.40#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.259.07:31:09.40#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.259.07:31:09.40#ibcon#ireg 7 cls_cnt 0 2006.259.07:31:09.40#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.259.07:31:09.52#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.259.07:31:09.52#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.259.07:31:09.52#ibcon#enter wrdev, iclass 5, count 0 2006.259.07:31:09.52#ibcon#first serial, iclass 5, count 0 2006.259.07:31:09.52#ibcon#enter sib2, iclass 5, count 0 2006.259.07:31:09.52#ibcon#flushed, iclass 5, count 0 2006.259.07:31:09.52#ibcon#about to write, iclass 5, count 0 2006.259.07:31:09.52#ibcon#wrote, iclass 5, count 0 2006.259.07:31:09.52#ibcon#about to read 3, iclass 5, count 0 2006.259.07:31:09.54#ibcon#read 3, iclass 5, count 0 2006.259.07:31:09.54#ibcon#about to read 4, iclass 5, count 0 2006.259.07:31:09.54#ibcon#read 4, iclass 5, count 0 2006.259.07:31:09.54#ibcon#about to read 5, iclass 5, count 0 2006.259.07:31:09.54#ibcon#read 5, iclass 5, count 0 2006.259.07:31:09.54#ibcon#about to read 6, iclass 5, count 0 2006.259.07:31:09.54#ibcon#read 6, iclass 5, count 0 2006.259.07:31:09.54#ibcon#end of sib2, iclass 5, count 0 2006.259.07:31:09.54#ibcon#*mode == 0, iclass 5, count 0 2006.259.07:31:09.54#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.259.07:31:09.54#ibcon#[25=USB\r\n] 2006.259.07:31:09.54#ibcon#*before write, iclass 5, count 0 2006.259.07:31:09.54#ibcon#enter sib2, iclass 5, count 0 2006.259.07:31:09.54#ibcon#flushed, iclass 5, count 0 2006.259.07:31:09.54#ibcon#about to write, iclass 5, count 0 2006.259.07:31:09.54#ibcon#wrote, iclass 5, count 0 2006.259.07:31:09.54#ibcon#about to read 3, iclass 5, count 0 2006.259.07:31:09.57#ibcon#read 3, iclass 5, count 0 2006.259.07:31:09.57#ibcon#about to read 4, iclass 5, count 0 2006.259.07:31:09.57#ibcon#read 4, iclass 5, count 0 2006.259.07:31:09.57#ibcon#about to read 5, iclass 5, count 0 2006.259.07:31:09.57#ibcon#read 5, iclass 5, count 0 2006.259.07:31:09.57#ibcon#about to read 6, iclass 5, count 0 2006.259.07:31:09.57#ibcon#read 6, iclass 5, count 0 2006.259.07:31:09.57#ibcon#end of sib2, iclass 5, count 0 2006.259.07:31:09.57#ibcon#*after write, iclass 5, count 0 2006.259.07:31:09.57#ibcon#*before return 0, iclass 5, count 0 2006.259.07:31:09.57#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.259.07:31:09.57#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.259.07:31:09.57#ibcon#about to clear, iclass 5 cls_cnt 0 2006.259.07:31:09.57#ibcon#cleared, iclass 5 cls_cnt 0 2006.259.07:31:09.57$vc4f8/valo=5,652.99 2006.259.07:31:09.57#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.259.07:31:09.57#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.259.07:31:09.57#ibcon#ireg 17 cls_cnt 0 2006.259.07:31:09.57#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.259.07:31:09.57#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.259.07:31:09.57#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.259.07:31:09.57#ibcon#enter wrdev, iclass 7, count 0 2006.259.07:31:09.57#ibcon#first serial, iclass 7, count 0 2006.259.07:31:09.57#ibcon#enter sib2, iclass 7, count 0 2006.259.07:31:09.57#ibcon#flushed, iclass 7, count 0 2006.259.07:31:09.57#ibcon#about to write, iclass 7, count 0 2006.259.07:31:09.57#ibcon#wrote, iclass 7, count 0 2006.259.07:31:09.57#ibcon#about to read 3, iclass 7, count 0 2006.259.07:31:09.60#ibcon#read 3, iclass 7, count 0 2006.259.07:31:09.60#ibcon#about to read 4, iclass 7, count 0 2006.259.07:31:09.60#ibcon#read 4, iclass 7, count 0 2006.259.07:31:09.60#ibcon#about to read 5, iclass 7, count 0 2006.259.07:31:09.60#ibcon#read 5, iclass 7, count 0 2006.259.07:31:09.60#ibcon#about to read 6, iclass 7, count 0 2006.259.07:31:09.60#ibcon#read 6, iclass 7, count 0 2006.259.07:31:09.60#ibcon#end of sib2, iclass 7, count 0 2006.259.07:31:09.60#ibcon#*mode == 0, iclass 7, count 0 2006.259.07:31:09.60#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.259.07:31:09.60#ibcon#[26=FRQ=05,652.99\r\n] 2006.259.07:31:09.60#ibcon#*before write, iclass 7, count 0 2006.259.07:31:09.60#ibcon#enter sib2, iclass 7, count 0 2006.259.07:31:09.60#ibcon#flushed, iclass 7, count 0 2006.259.07:31:09.60#ibcon#about to write, iclass 7, count 0 2006.259.07:31:09.60#ibcon#wrote, iclass 7, count 0 2006.259.07:31:09.60#ibcon#about to read 3, iclass 7, count 0 2006.259.07:31:09.64#ibcon#read 3, iclass 7, count 0 2006.259.07:31:09.64#ibcon#about to read 4, iclass 7, count 0 2006.259.07:31:09.64#ibcon#read 4, iclass 7, count 0 2006.259.07:31:09.64#ibcon#about to read 5, iclass 7, count 0 2006.259.07:31:09.64#ibcon#read 5, iclass 7, count 0 2006.259.07:31:09.64#ibcon#about to read 6, iclass 7, count 0 2006.259.07:31:09.64#ibcon#read 6, iclass 7, count 0 2006.259.07:31:09.64#ibcon#end of sib2, iclass 7, count 0 2006.259.07:31:09.64#ibcon#*after write, iclass 7, count 0 2006.259.07:31:09.64#ibcon#*before return 0, iclass 7, count 0 2006.259.07:31:09.64#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.259.07:31:09.64#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.259.07:31:09.64#ibcon#about to clear, iclass 7 cls_cnt 0 2006.259.07:31:09.64#ibcon#cleared, iclass 7 cls_cnt 0 2006.259.07:31:09.64$vc4f8/va=5,7 2006.259.07:31:09.64#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.259.07:31:09.64#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.259.07:31:09.64#ibcon#ireg 11 cls_cnt 2 2006.259.07:31:09.64#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.259.07:31:09.69#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.259.07:31:09.69#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.259.07:31:09.69#ibcon#enter wrdev, iclass 11, count 2 2006.259.07:31:09.69#ibcon#first serial, iclass 11, count 2 2006.259.07:31:09.69#ibcon#enter sib2, iclass 11, count 2 2006.259.07:31:09.69#ibcon#flushed, iclass 11, count 2 2006.259.07:31:09.69#ibcon#about to write, iclass 11, count 2 2006.259.07:31:09.69#ibcon#wrote, iclass 11, count 2 2006.259.07:31:09.69#ibcon#about to read 3, iclass 11, count 2 2006.259.07:31:09.72#ibcon#read 3, iclass 11, count 2 2006.259.07:31:09.72#ibcon#about to read 4, iclass 11, count 2 2006.259.07:31:09.72#ibcon#read 4, iclass 11, count 2 2006.259.07:31:09.72#ibcon#about to read 5, iclass 11, count 2 2006.259.07:31:09.72#ibcon#read 5, iclass 11, count 2 2006.259.07:31:09.72#ibcon#about to read 6, iclass 11, count 2 2006.259.07:31:09.72#ibcon#read 6, iclass 11, count 2 2006.259.07:31:09.72#ibcon#end of sib2, iclass 11, count 2 2006.259.07:31:09.72#ibcon#*mode == 0, iclass 11, count 2 2006.259.07:31:09.72#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.259.07:31:09.72#ibcon#[25=AT05-07\r\n] 2006.259.07:31:09.72#ibcon#*before write, iclass 11, count 2 2006.259.07:31:09.72#ibcon#enter sib2, iclass 11, count 2 2006.259.07:31:09.72#ibcon#flushed, iclass 11, count 2 2006.259.07:31:09.72#ibcon#about to write, iclass 11, count 2 2006.259.07:31:09.72#ibcon#wrote, iclass 11, count 2 2006.259.07:31:09.72#ibcon#about to read 3, iclass 11, count 2 2006.259.07:31:09.75#ibcon#read 3, iclass 11, count 2 2006.259.07:31:09.75#ibcon#about to read 4, iclass 11, count 2 2006.259.07:31:09.75#ibcon#read 4, iclass 11, count 2 2006.259.07:31:09.75#ibcon#about to read 5, iclass 11, count 2 2006.259.07:31:09.75#ibcon#read 5, iclass 11, count 2 2006.259.07:31:09.75#ibcon#about to read 6, iclass 11, count 2 2006.259.07:31:09.75#ibcon#read 6, iclass 11, count 2 2006.259.07:31:09.75#ibcon#end of sib2, iclass 11, count 2 2006.259.07:31:09.75#ibcon#*after write, iclass 11, count 2 2006.259.07:31:09.75#ibcon#*before return 0, iclass 11, count 2 2006.259.07:31:09.75#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.259.07:31:09.75#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.259.07:31:09.75#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.259.07:31:09.75#ibcon#ireg 7 cls_cnt 0 2006.259.07:31:09.75#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.259.07:31:09.87#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.259.07:31:09.87#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.259.07:31:09.87#ibcon#enter wrdev, iclass 11, count 0 2006.259.07:31:09.87#ibcon#first serial, iclass 11, count 0 2006.259.07:31:09.87#ibcon#enter sib2, iclass 11, count 0 2006.259.07:31:09.87#ibcon#flushed, iclass 11, count 0 2006.259.07:31:09.87#ibcon#about to write, iclass 11, count 0 2006.259.07:31:09.87#ibcon#wrote, iclass 11, count 0 2006.259.07:31:09.87#ibcon#about to read 3, iclass 11, count 0 2006.259.07:31:09.89#ibcon#read 3, iclass 11, count 0 2006.259.07:31:09.89#ibcon#about to read 4, iclass 11, count 0 2006.259.07:31:09.89#ibcon#read 4, iclass 11, count 0 2006.259.07:31:09.89#ibcon#about to read 5, iclass 11, count 0 2006.259.07:31:09.89#ibcon#read 5, iclass 11, count 0 2006.259.07:31:09.89#ibcon#about to read 6, iclass 11, count 0 2006.259.07:31:09.89#ibcon#read 6, iclass 11, count 0 2006.259.07:31:09.89#ibcon#end of sib2, iclass 11, count 0 2006.259.07:31:09.89#ibcon#*mode == 0, iclass 11, count 0 2006.259.07:31:09.89#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.259.07:31:09.89#ibcon#[25=USB\r\n] 2006.259.07:31:09.89#ibcon#*before write, iclass 11, count 0 2006.259.07:31:09.89#ibcon#enter sib2, iclass 11, count 0 2006.259.07:31:09.89#ibcon#flushed, iclass 11, count 0 2006.259.07:31:09.89#ibcon#about to write, iclass 11, count 0 2006.259.07:31:09.89#ibcon#wrote, iclass 11, count 0 2006.259.07:31:09.89#ibcon#about to read 3, iclass 11, count 0 2006.259.07:31:09.92#ibcon#read 3, iclass 11, count 0 2006.259.07:31:09.92#ibcon#about to read 4, iclass 11, count 0 2006.259.07:31:09.92#ibcon#read 4, iclass 11, count 0 2006.259.07:31:09.92#ibcon#about to read 5, iclass 11, count 0 2006.259.07:31:09.92#ibcon#read 5, iclass 11, count 0 2006.259.07:31:09.92#ibcon#about to read 6, iclass 11, count 0 2006.259.07:31:09.92#ibcon#read 6, iclass 11, count 0 2006.259.07:31:09.92#ibcon#end of sib2, iclass 11, count 0 2006.259.07:31:09.92#ibcon#*after write, iclass 11, count 0 2006.259.07:31:09.92#ibcon#*before return 0, iclass 11, count 0 2006.259.07:31:09.92#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.259.07:31:09.92#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.259.07:31:09.92#ibcon#about to clear, iclass 11 cls_cnt 0 2006.259.07:31:09.92#ibcon#cleared, iclass 11 cls_cnt 0 2006.259.07:31:09.92$vc4f8/valo=6,772.99 2006.259.07:31:09.92#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.259.07:31:09.92#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.259.07:31:09.92#ibcon#ireg 17 cls_cnt 0 2006.259.07:31:09.92#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.259.07:31:09.92#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.259.07:31:09.92#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.259.07:31:09.92#ibcon#enter wrdev, iclass 13, count 0 2006.259.07:31:09.92#ibcon#first serial, iclass 13, count 0 2006.259.07:31:09.92#ibcon#enter sib2, iclass 13, count 0 2006.259.07:31:09.92#ibcon#flushed, iclass 13, count 0 2006.259.07:31:09.92#ibcon#about to write, iclass 13, count 0 2006.259.07:31:09.92#ibcon#wrote, iclass 13, count 0 2006.259.07:31:09.92#ibcon#about to read 3, iclass 13, count 0 2006.259.07:31:09.94#ibcon#read 3, iclass 13, count 0 2006.259.07:31:09.94#ibcon#about to read 4, iclass 13, count 0 2006.259.07:31:09.94#ibcon#read 4, iclass 13, count 0 2006.259.07:31:09.94#ibcon#about to read 5, iclass 13, count 0 2006.259.07:31:09.94#ibcon#read 5, iclass 13, count 0 2006.259.07:31:09.94#ibcon#about to read 6, iclass 13, count 0 2006.259.07:31:09.94#ibcon#read 6, iclass 13, count 0 2006.259.07:31:09.94#ibcon#end of sib2, iclass 13, count 0 2006.259.07:31:09.94#ibcon#*mode == 0, iclass 13, count 0 2006.259.07:31:09.94#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.259.07:31:09.94#ibcon#[26=FRQ=06,772.99\r\n] 2006.259.07:31:09.94#ibcon#*before write, iclass 13, count 0 2006.259.07:31:09.94#ibcon#enter sib2, iclass 13, count 0 2006.259.07:31:09.94#ibcon#flushed, iclass 13, count 0 2006.259.07:31:09.94#ibcon#about to write, iclass 13, count 0 2006.259.07:31:09.94#ibcon#wrote, iclass 13, count 0 2006.259.07:31:09.94#ibcon#about to read 3, iclass 13, count 0 2006.259.07:31:09.98#ibcon#read 3, iclass 13, count 0 2006.259.07:31:09.98#ibcon#about to read 4, iclass 13, count 0 2006.259.07:31:09.98#ibcon#read 4, iclass 13, count 0 2006.259.07:31:09.98#ibcon#about to read 5, iclass 13, count 0 2006.259.07:31:09.98#ibcon#read 5, iclass 13, count 0 2006.259.07:31:09.98#ibcon#about to read 6, iclass 13, count 0 2006.259.07:31:09.98#ibcon#read 6, iclass 13, count 0 2006.259.07:31:09.98#ibcon#end of sib2, iclass 13, count 0 2006.259.07:31:09.98#ibcon#*after write, iclass 13, count 0 2006.259.07:31:09.98#ibcon#*before return 0, iclass 13, count 0 2006.259.07:31:09.98#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.259.07:31:09.98#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.259.07:31:09.98#ibcon#about to clear, iclass 13 cls_cnt 0 2006.259.07:31:09.98#ibcon#cleared, iclass 13 cls_cnt 0 2006.259.07:31:09.98$vc4f8/va=6,6 2006.259.07:31:09.98#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.259.07:31:09.98#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.259.07:31:09.98#ibcon#ireg 11 cls_cnt 2 2006.259.07:31:09.98#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.259.07:31:10.04#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.259.07:31:10.04#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.259.07:31:10.04#ibcon#enter wrdev, iclass 15, count 2 2006.259.07:31:10.04#ibcon#first serial, iclass 15, count 2 2006.259.07:31:10.04#ibcon#enter sib2, iclass 15, count 2 2006.259.07:31:10.04#ibcon#flushed, iclass 15, count 2 2006.259.07:31:10.04#ibcon#about to write, iclass 15, count 2 2006.259.07:31:10.04#ibcon#wrote, iclass 15, count 2 2006.259.07:31:10.04#ibcon#about to read 3, iclass 15, count 2 2006.259.07:31:10.06#ibcon#read 3, iclass 15, count 2 2006.259.07:31:10.06#ibcon#about to read 4, iclass 15, count 2 2006.259.07:31:10.06#ibcon#read 4, iclass 15, count 2 2006.259.07:31:10.06#ibcon#about to read 5, iclass 15, count 2 2006.259.07:31:10.06#ibcon#read 5, iclass 15, count 2 2006.259.07:31:10.06#ibcon#about to read 6, iclass 15, count 2 2006.259.07:31:10.06#ibcon#read 6, iclass 15, count 2 2006.259.07:31:10.06#ibcon#end of sib2, iclass 15, count 2 2006.259.07:31:10.06#ibcon#*mode == 0, iclass 15, count 2 2006.259.07:31:10.06#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.259.07:31:10.06#ibcon#[25=AT06-06\r\n] 2006.259.07:31:10.06#ibcon#*before write, iclass 15, count 2 2006.259.07:31:10.06#ibcon#enter sib2, iclass 15, count 2 2006.259.07:31:10.06#ibcon#flushed, iclass 15, count 2 2006.259.07:31:10.06#ibcon#about to write, iclass 15, count 2 2006.259.07:31:10.06#ibcon#wrote, iclass 15, count 2 2006.259.07:31:10.06#ibcon#about to read 3, iclass 15, count 2 2006.259.07:31:10.09#ibcon#read 3, iclass 15, count 2 2006.259.07:31:10.09#ibcon#about to read 4, iclass 15, count 2 2006.259.07:31:10.09#ibcon#read 4, iclass 15, count 2 2006.259.07:31:10.09#ibcon#about to read 5, iclass 15, count 2 2006.259.07:31:10.09#ibcon#read 5, iclass 15, count 2 2006.259.07:31:10.09#ibcon#about to read 6, iclass 15, count 2 2006.259.07:31:10.09#ibcon#read 6, iclass 15, count 2 2006.259.07:31:10.09#ibcon#end of sib2, iclass 15, count 2 2006.259.07:31:10.09#ibcon#*after write, iclass 15, count 2 2006.259.07:31:10.09#ibcon#*before return 0, iclass 15, count 2 2006.259.07:31:10.09#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.259.07:31:10.09#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.259.07:31:10.09#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.259.07:31:10.09#ibcon#ireg 7 cls_cnt 0 2006.259.07:31:10.09#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.259.07:31:10.21#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.259.07:31:10.21#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.259.07:31:10.21#ibcon#enter wrdev, iclass 15, count 0 2006.259.07:31:10.21#ibcon#first serial, iclass 15, count 0 2006.259.07:31:10.21#ibcon#enter sib2, iclass 15, count 0 2006.259.07:31:10.21#ibcon#flushed, iclass 15, count 0 2006.259.07:31:10.21#ibcon#about to write, iclass 15, count 0 2006.259.07:31:10.21#ibcon#wrote, iclass 15, count 0 2006.259.07:31:10.21#ibcon#about to read 3, iclass 15, count 0 2006.259.07:31:10.23#ibcon#read 3, iclass 15, count 0 2006.259.07:31:10.23#ibcon#about to read 4, iclass 15, count 0 2006.259.07:31:10.23#ibcon#read 4, iclass 15, count 0 2006.259.07:31:10.23#ibcon#about to read 5, iclass 15, count 0 2006.259.07:31:10.23#ibcon#read 5, iclass 15, count 0 2006.259.07:31:10.23#ibcon#about to read 6, iclass 15, count 0 2006.259.07:31:10.23#ibcon#read 6, iclass 15, count 0 2006.259.07:31:10.23#ibcon#end of sib2, iclass 15, count 0 2006.259.07:31:10.23#ibcon#*mode == 0, iclass 15, count 0 2006.259.07:31:10.23#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.259.07:31:10.23#ibcon#[25=USB\r\n] 2006.259.07:31:10.23#ibcon#*before write, iclass 15, count 0 2006.259.07:31:10.23#ibcon#enter sib2, iclass 15, count 0 2006.259.07:31:10.23#ibcon#flushed, iclass 15, count 0 2006.259.07:31:10.23#ibcon#about to write, iclass 15, count 0 2006.259.07:31:10.23#ibcon#wrote, iclass 15, count 0 2006.259.07:31:10.23#ibcon#about to read 3, iclass 15, count 0 2006.259.07:31:10.26#ibcon#read 3, iclass 15, count 0 2006.259.07:31:10.26#ibcon#about to read 4, iclass 15, count 0 2006.259.07:31:10.26#ibcon#read 4, iclass 15, count 0 2006.259.07:31:10.26#ibcon#about to read 5, iclass 15, count 0 2006.259.07:31:10.26#ibcon#read 5, iclass 15, count 0 2006.259.07:31:10.26#ibcon#about to read 6, iclass 15, count 0 2006.259.07:31:10.26#ibcon#read 6, iclass 15, count 0 2006.259.07:31:10.26#ibcon#end of sib2, iclass 15, count 0 2006.259.07:31:10.26#ibcon#*after write, iclass 15, count 0 2006.259.07:31:10.26#ibcon#*before return 0, iclass 15, count 0 2006.259.07:31:10.26#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.259.07:31:10.26#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.259.07:31:10.26#ibcon#about to clear, iclass 15 cls_cnt 0 2006.259.07:31:10.26#ibcon#cleared, iclass 15 cls_cnt 0 2006.259.07:31:10.26$vc4f8/valo=7,832.99 2006.259.07:31:10.26#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.259.07:31:10.26#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.259.07:31:10.26#ibcon#ireg 17 cls_cnt 0 2006.259.07:31:10.26#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.259.07:31:10.26#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.259.07:31:10.26#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.259.07:31:10.26#ibcon#enter wrdev, iclass 17, count 0 2006.259.07:31:10.26#ibcon#first serial, iclass 17, count 0 2006.259.07:31:10.26#ibcon#enter sib2, iclass 17, count 0 2006.259.07:31:10.26#ibcon#flushed, iclass 17, count 0 2006.259.07:31:10.26#ibcon#about to write, iclass 17, count 0 2006.259.07:31:10.26#ibcon#wrote, iclass 17, count 0 2006.259.07:31:10.26#ibcon#about to read 3, iclass 17, count 0 2006.259.07:31:10.28#ibcon#read 3, iclass 17, count 0 2006.259.07:31:10.28#ibcon#about to read 4, iclass 17, count 0 2006.259.07:31:10.28#ibcon#read 4, iclass 17, count 0 2006.259.07:31:10.28#ibcon#about to read 5, iclass 17, count 0 2006.259.07:31:10.28#ibcon#read 5, iclass 17, count 0 2006.259.07:31:10.28#ibcon#about to read 6, iclass 17, count 0 2006.259.07:31:10.28#ibcon#read 6, iclass 17, count 0 2006.259.07:31:10.28#ibcon#end of sib2, iclass 17, count 0 2006.259.07:31:10.28#ibcon#*mode == 0, iclass 17, count 0 2006.259.07:31:10.28#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.259.07:31:10.28#ibcon#[26=FRQ=07,832.99\r\n] 2006.259.07:31:10.28#ibcon#*before write, iclass 17, count 0 2006.259.07:31:10.28#ibcon#enter sib2, iclass 17, count 0 2006.259.07:31:10.28#ibcon#flushed, iclass 17, count 0 2006.259.07:31:10.28#ibcon#about to write, iclass 17, count 0 2006.259.07:31:10.28#ibcon#wrote, iclass 17, count 0 2006.259.07:31:10.28#ibcon#about to read 3, iclass 17, count 0 2006.259.07:31:10.32#ibcon#read 3, iclass 17, count 0 2006.259.07:31:10.32#ibcon#about to read 4, iclass 17, count 0 2006.259.07:31:10.32#ibcon#read 4, iclass 17, count 0 2006.259.07:31:10.32#ibcon#about to read 5, iclass 17, count 0 2006.259.07:31:10.32#ibcon#read 5, iclass 17, count 0 2006.259.07:31:10.32#ibcon#about to read 6, iclass 17, count 0 2006.259.07:31:10.32#ibcon#read 6, iclass 17, count 0 2006.259.07:31:10.32#ibcon#end of sib2, iclass 17, count 0 2006.259.07:31:10.32#ibcon#*after write, iclass 17, count 0 2006.259.07:31:10.32#ibcon#*before return 0, iclass 17, count 0 2006.259.07:31:10.32#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.259.07:31:10.32#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.259.07:31:10.32#ibcon#about to clear, iclass 17 cls_cnt 0 2006.259.07:31:10.32#ibcon#cleared, iclass 17 cls_cnt 0 2006.259.07:31:10.32$vc4f8/va=7,6 2006.259.07:31:10.32#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.259.07:31:10.32#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.259.07:31:10.32#ibcon#ireg 11 cls_cnt 2 2006.259.07:31:10.32#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.259.07:31:10.38#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.259.07:31:10.38#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.259.07:31:10.38#ibcon#enter wrdev, iclass 19, count 2 2006.259.07:31:10.38#ibcon#first serial, iclass 19, count 2 2006.259.07:31:10.38#ibcon#enter sib2, iclass 19, count 2 2006.259.07:31:10.38#ibcon#flushed, iclass 19, count 2 2006.259.07:31:10.38#ibcon#about to write, iclass 19, count 2 2006.259.07:31:10.38#ibcon#wrote, iclass 19, count 2 2006.259.07:31:10.38#ibcon#about to read 3, iclass 19, count 2 2006.259.07:31:10.40#ibcon#read 3, iclass 19, count 2 2006.259.07:31:10.40#ibcon#about to read 4, iclass 19, count 2 2006.259.07:31:10.40#ibcon#read 4, iclass 19, count 2 2006.259.07:31:10.40#ibcon#about to read 5, iclass 19, count 2 2006.259.07:31:10.40#ibcon#read 5, iclass 19, count 2 2006.259.07:31:10.40#ibcon#about to read 6, iclass 19, count 2 2006.259.07:31:10.40#ibcon#read 6, iclass 19, count 2 2006.259.07:31:10.40#ibcon#end of sib2, iclass 19, count 2 2006.259.07:31:10.40#ibcon#*mode == 0, iclass 19, count 2 2006.259.07:31:10.40#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.259.07:31:10.40#ibcon#[25=AT07-06\r\n] 2006.259.07:31:10.40#ibcon#*before write, iclass 19, count 2 2006.259.07:31:10.40#ibcon#enter sib2, iclass 19, count 2 2006.259.07:31:10.40#ibcon#flushed, iclass 19, count 2 2006.259.07:31:10.40#ibcon#about to write, iclass 19, count 2 2006.259.07:31:10.40#ibcon#wrote, iclass 19, count 2 2006.259.07:31:10.40#ibcon#about to read 3, iclass 19, count 2 2006.259.07:31:10.43#ibcon#read 3, iclass 19, count 2 2006.259.07:31:10.43#ibcon#about to read 4, iclass 19, count 2 2006.259.07:31:10.43#ibcon#read 4, iclass 19, count 2 2006.259.07:31:10.43#ibcon#about to read 5, iclass 19, count 2 2006.259.07:31:10.43#ibcon#read 5, iclass 19, count 2 2006.259.07:31:10.43#ibcon#about to read 6, iclass 19, count 2 2006.259.07:31:10.43#ibcon#read 6, iclass 19, count 2 2006.259.07:31:10.43#ibcon#end of sib2, iclass 19, count 2 2006.259.07:31:10.43#ibcon#*after write, iclass 19, count 2 2006.259.07:31:10.43#ibcon#*before return 0, iclass 19, count 2 2006.259.07:31:10.43#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.259.07:31:10.43#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.259.07:31:10.43#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.259.07:31:10.43#ibcon#ireg 7 cls_cnt 0 2006.259.07:31:10.43#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.259.07:31:10.55#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.259.07:31:10.55#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.259.07:31:10.55#ibcon#enter wrdev, iclass 19, count 0 2006.259.07:31:10.55#ibcon#first serial, iclass 19, count 0 2006.259.07:31:10.55#ibcon#enter sib2, iclass 19, count 0 2006.259.07:31:10.55#ibcon#flushed, iclass 19, count 0 2006.259.07:31:10.55#ibcon#about to write, iclass 19, count 0 2006.259.07:31:10.55#ibcon#wrote, iclass 19, count 0 2006.259.07:31:10.55#ibcon#about to read 3, iclass 19, count 0 2006.259.07:31:10.57#ibcon#read 3, iclass 19, count 0 2006.259.07:31:10.57#ibcon#about to read 4, iclass 19, count 0 2006.259.07:31:10.57#ibcon#read 4, iclass 19, count 0 2006.259.07:31:10.57#ibcon#about to read 5, iclass 19, count 0 2006.259.07:31:10.57#ibcon#read 5, iclass 19, count 0 2006.259.07:31:10.57#ibcon#about to read 6, iclass 19, count 0 2006.259.07:31:10.57#ibcon#read 6, iclass 19, count 0 2006.259.07:31:10.57#ibcon#end of sib2, iclass 19, count 0 2006.259.07:31:10.57#ibcon#*mode == 0, iclass 19, count 0 2006.259.07:31:10.57#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.259.07:31:10.57#ibcon#[25=USB\r\n] 2006.259.07:31:10.57#ibcon#*before write, iclass 19, count 0 2006.259.07:31:10.57#ibcon#enter sib2, iclass 19, count 0 2006.259.07:31:10.57#ibcon#flushed, iclass 19, count 0 2006.259.07:31:10.57#ibcon#about to write, iclass 19, count 0 2006.259.07:31:10.57#ibcon#wrote, iclass 19, count 0 2006.259.07:31:10.57#ibcon#about to read 3, iclass 19, count 0 2006.259.07:31:10.60#ibcon#read 3, iclass 19, count 0 2006.259.07:31:10.60#ibcon#about to read 4, iclass 19, count 0 2006.259.07:31:10.60#ibcon#read 4, iclass 19, count 0 2006.259.07:31:10.60#ibcon#about to read 5, iclass 19, count 0 2006.259.07:31:10.60#ibcon#read 5, iclass 19, count 0 2006.259.07:31:10.60#ibcon#about to read 6, iclass 19, count 0 2006.259.07:31:10.60#ibcon#read 6, iclass 19, count 0 2006.259.07:31:10.60#ibcon#end of sib2, iclass 19, count 0 2006.259.07:31:10.60#ibcon#*after write, iclass 19, count 0 2006.259.07:31:10.60#ibcon#*before return 0, iclass 19, count 0 2006.259.07:31:10.60#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.259.07:31:10.60#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.259.07:31:10.60#ibcon#about to clear, iclass 19 cls_cnt 0 2006.259.07:31:10.60#ibcon#cleared, iclass 19 cls_cnt 0 2006.259.07:31:10.60$vc4f8/valo=8,852.99 2006.259.07:31:10.60#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.259.07:31:10.60#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.259.07:31:10.60#ibcon#ireg 17 cls_cnt 0 2006.259.07:31:10.60#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.259.07:31:10.60#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.259.07:31:10.60#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.259.07:31:10.60#ibcon#enter wrdev, iclass 21, count 0 2006.259.07:31:10.60#ibcon#first serial, iclass 21, count 0 2006.259.07:31:10.60#ibcon#enter sib2, iclass 21, count 0 2006.259.07:31:10.60#ibcon#flushed, iclass 21, count 0 2006.259.07:31:10.60#ibcon#about to write, iclass 21, count 0 2006.259.07:31:10.60#ibcon#wrote, iclass 21, count 0 2006.259.07:31:10.60#ibcon#about to read 3, iclass 21, count 0 2006.259.07:31:10.62#ibcon#read 3, iclass 21, count 0 2006.259.07:31:10.62#ibcon#about to read 4, iclass 21, count 0 2006.259.07:31:10.62#ibcon#read 4, iclass 21, count 0 2006.259.07:31:10.62#ibcon#about to read 5, iclass 21, count 0 2006.259.07:31:10.62#ibcon#read 5, iclass 21, count 0 2006.259.07:31:10.62#ibcon#about to read 6, iclass 21, count 0 2006.259.07:31:10.62#ibcon#read 6, iclass 21, count 0 2006.259.07:31:10.62#ibcon#end of sib2, iclass 21, count 0 2006.259.07:31:10.62#ibcon#*mode == 0, iclass 21, count 0 2006.259.07:31:10.62#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.259.07:31:10.62#ibcon#[26=FRQ=08,852.99\r\n] 2006.259.07:31:10.62#ibcon#*before write, iclass 21, count 0 2006.259.07:31:10.62#ibcon#enter sib2, iclass 21, count 0 2006.259.07:31:10.62#ibcon#flushed, iclass 21, count 0 2006.259.07:31:10.62#ibcon#about to write, iclass 21, count 0 2006.259.07:31:10.62#ibcon#wrote, iclass 21, count 0 2006.259.07:31:10.62#ibcon#about to read 3, iclass 21, count 0 2006.259.07:31:10.66#ibcon#read 3, iclass 21, count 0 2006.259.07:31:10.66#ibcon#about to read 4, iclass 21, count 0 2006.259.07:31:10.66#ibcon#read 4, iclass 21, count 0 2006.259.07:31:10.66#ibcon#about to read 5, iclass 21, count 0 2006.259.07:31:10.66#ibcon#read 5, iclass 21, count 0 2006.259.07:31:10.66#ibcon#about to read 6, iclass 21, count 0 2006.259.07:31:10.66#ibcon#read 6, iclass 21, count 0 2006.259.07:31:10.66#ibcon#end of sib2, iclass 21, count 0 2006.259.07:31:10.66#ibcon#*after write, iclass 21, count 0 2006.259.07:31:10.66#ibcon#*before return 0, iclass 21, count 0 2006.259.07:31:10.66#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.259.07:31:10.66#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.259.07:31:10.66#ibcon#about to clear, iclass 21 cls_cnt 0 2006.259.07:31:10.66#ibcon#cleared, iclass 21 cls_cnt 0 2006.259.07:31:10.66$vc4f8/va=8,6 2006.259.07:31:10.66#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.259.07:31:10.66#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.259.07:31:10.66#ibcon#ireg 11 cls_cnt 2 2006.259.07:31:10.66#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.259.07:31:10.72#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.259.07:31:10.72#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.259.07:31:10.72#ibcon#enter wrdev, iclass 23, count 2 2006.259.07:31:10.72#ibcon#first serial, iclass 23, count 2 2006.259.07:31:10.72#ibcon#enter sib2, iclass 23, count 2 2006.259.07:31:10.72#ibcon#flushed, iclass 23, count 2 2006.259.07:31:10.72#ibcon#about to write, iclass 23, count 2 2006.259.07:31:10.72#ibcon#wrote, iclass 23, count 2 2006.259.07:31:10.72#ibcon#about to read 3, iclass 23, count 2 2006.259.07:31:10.74#ibcon#read 3, iclass 23, count 2 2006.259.07:31:10.74#ibcon#about to read 4, iclass 23, count 2 2006.259.07:31:10.74#ibcon#read 4, iclass 23, count 2 2006.259.07:31:10.74#ibcon#about to read 5, iclass 23, count 2 2006.259.07:31:10.74#ibcon#read 5, iclass 23, count 2 2006.259.07:31:10.74#ibcon#about to read 6, iclass 23, count 2 2006.259.07:31:10.74#ibcon#read 6, iclass 23, count 2 2006.259.07:31:10.74#ibcon#end of sib2, iclass 23, count 2 2006.259.07:31:10.74#ibcon#*mode == 0, iclass 23, count 2 2006.259.07:31:10.74#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.259.07:31:10.74#ibcon#[25=AT08-06\r\n] 2006.259.07:31:10.74#ibcon#*before write, iclass 23, count 2 2006.259.07:31:10.74#ibcon#enter sib2, iclass 23, count 2 2006.259.07:31:10.74#ibcon#flushed, iclass 23, count 2 2006.259.07:31:10.74#ibcon#about to write, iclass 23, count 2 2006.259.07:31:10.74#ibcon#wrote, iclass 23, count 2 2006.259.07:31:10.74#ibcon#about to read 3, iclass 23, count 2 2006.259.07:31:10.77#ibcon#read 3, iclass 23, count 2 2006.259.07:31:10.77#ibcon#about to read 4, iclass 23, count 2 2006.259.07:31:10.77#ibcon#read 4, iclass 23, count 2 2006.259.07:31:10.77#ibcon#about to read 5, iclass 23, count 2 2006.259.07:31:10.77#ibcon#read 5, iclass 23, count 2 2006.259.07:31:10.77#ibcon#about to read 6, iclass 23, count 2 2006.259.07:31:10.77#ibcon#read 6, iclass 23, count 2 2006.259.07:31:10.77#ibcon#end of sib2, iclass 23, count 2 2006.259.07:31:10.77#ibcon#*after write, iclass 23, count 2 2006.259.07:31:10.77#ibcon#*before return 0, iclass 23, count 2 2006.259.07:31:10.77#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.259.07:31:10.77#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.259.07:31:10.77#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.259.07:31:10.77#ibcon#ireg 7 cls_cnt 0 2006.259.07:31:10.77#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.259.07:31:10.89#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.259.07:31:10.89#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.259.07:31:10.89#ibcon#enter wrdev, iclass 23, count 0 2006.259.07:31:10.89#ibcon#first serial, iclass 23, count 0 2006.259.07:31:10.89#ibcon#enter sib2, iclass 23, count 0 2006.259.07:31:10.89#ibcon#flushed, iclass 23, count 0 2006.259.07:31:10.89#ibcon#about to write, iclass 23, count 0 2006.259.07:31:10.89#ibcon#wrote, iclass 23, count 0 2006.259.07:31:10.89#ibcon#about to read 3, iclass 23, count 0 2006.259.07:31:10.91#ibcon#read 3, iclass 23, count 0 2006.259.07:31:10.91#ibcon#about to read 4, iclass 23, count 0 2006.259.07:31:10.91#ibcon#read 4, iclass 23, count 0 2006.259.07:31:10.91#ibcon#about to read 5, iclass 23, count 0 2006.259.07:31:10.91#ibcon#read 5, iclass 23, count 0 2006.259.07:31:10.91#ibcon#about to read 6, iclass 23, count 0 2006.259.07:31:10.91#ibcon#read 6, iclass 23, count 0 2006.259.07:31:10.91#ibcon#end of sib2, iclass 23, count 0 2006.259.07:31:10.91#ibcon#*mode == 0, iclass 23, count 0 2006.259.07:31:10.91#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.259.07:31:10.91#ibcon#[25=USB\r\n] 2006.259.07:31:10.91#ibcon#*before write, iclass 23, count 0 2006.259.07:31:10.91#ibcon#enter sib2, iclass 23, count 0 2006.259.07:31:10.91#ibcon#flushed, iclass 23, count 0 2006.259.07:31:10.91#ibcon#about to write, iclass 23, count 0 2006.259.07:31:10.91#ibcon#wrote, iclass 23, count 0 2006.259.07:31:10.91#ibcon#about to read 3, iclass 23, count 0 2006.259.07:31:10.94#ibcon#read 3, iclass 23, count 0 2006.259.07:31:10.94#ibcon#about to read 4, iclass 23, count 0 2006.259.07:31:10.94#ibcon#read 4, iclass 23, count 0 2006.259.07:31:10.94#ibcon#about to read 5, iclass 23, count 0 2006.259.07:31:10.94#ibcon#read 5, iclass 23, count 0 2006.259.07:31:10.94#ibcon#about to read 6, iclass 23, count 0 2006.259.07:31:10.94#ibcon#read 6, iclass 23, count 0 2006.259.07:31:10.94#ibcon#end of sib2, iclass 23, count 0 2006.259.07:31:10.94#ibcon#*after write, iclass 23, count 0 2006.259.07:31:10.94#ibcon#*before return 0, iclass 23, count 0 2006.259.07:31:10.94#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.259.07:31:10.94#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.259.07:31:10.94#ibcon#about to clear, iclass 23 cls_cnt 0 2006.259.07:31:10.94#ibcon#cleared, iclass 23 cls_cnt 0 2006.259.07:31:10.94$vc4f8/vblo=1,632.99 2006.259.07:31:10.94#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.259.07:31:10.94#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.259.07:31:10.94#ibcon#ireg 17 cls_cnt 0 2006.259.07:31:10.94#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.259.07:31:10.94#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.259.07:31:10.94#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.259.07:31:10.94#ibcon#enter wrdev, iclass 25, count 0 2006.259.07:31:10.94#ibcon#first serial, iclass 25, count 0 2006.259.07:31:10.94#ibcon#enter sib2, iclass 25, count 0 2006.259.07:31:10.94#ibcon#flushed, iclass 25, count 0 2006.259.07:31:10.94#ibcon#about to write, iclass 25, count 0 2006.259.07:31:10.94#ibcon#wrote, iclass 25, count 0 2006.259.07:31:10.94#ibcon#about to read 3, iclass 25, count 0 2006.259.07:31:10.96#ibcon#read 3, iclass 25, count 0 2006.259.07:31:10.96#ibcon#about to read 4, iclass 25, count 0 2006.259.07:31:10.96#ibcon#read 4, iclass 25, count 0 2006.259.07:31:10.96#ibcon#about to read 5, iclass 25, count 0 2006.259.07:31:10.96#ibcon#read 5, iclass 25, count 0 2006.259.07:31:10.96#ibcon#about to read 6, iclass 25, count 0 2006.259.07:31:10.96#ibcon#read 6, iclass 25, count 0 2006.259.07:31:10.96#ibcon#end of sib2, iclass 25, count 0 2006.259.07:31:10.96#ibcon#*mode == 0, iclass 25, count 0 2006.259.07:31:10.96#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.259.07:31:10.96#ibcon#[28=FRQ=01,632.99\r\n] 2006.259.07:31:10.96#ibcon#*before write, iclass 25, count 0 2006.259.07:31:10.96#ibcon#enter sib2, iclass 25, count 0 2006.259.07:31:10.96#ibcon#flushed, iclass 25, count 0 2006.259.07:31:10.96#ibcon#about to write, iclass 25, count 0 2006.259.07:31:10.96#ibcon#wrote, iclass 25, count 0 2006.259.07:31:10.96#ibcon#about to read 3, iclass 25, count 0 2006.259.07:31:11.00#ibcon#read 3, iclass 25, count 0 2006.259.07:31:11.00#ibcon#about to read 4, iclass 25, count 0 2006.259.07:31:11.00#ibcon#read 4, iclass 25, count 0 2006.259.07:31:11.00#ibcon#about to read 5, iclass 25, count 0 2006.259.07:31:11.00#ibcon#read 5, iclass 25, count 0 2006.259.07:31:11.00#ibcon#about to read 6, iclass 25, count 0 2006.259.07:31:11.00#ibcon#read 6, iclass 25, count 0 2006.259.07:31:11.00#ibcon#end of sib2, iclass 25, count 0 2006.259.07:31:11.00#ibcon#*after write, iclass 25, count 0 2006.259.07:31:11.00#ibcon#*before return 0, iclass 25, count 0 2006.259.07:31:11.00#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.259.07:31:11.00#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.259.07:31:11.00#ibcon#about to clear, iclass 25 cls_cnt 0 2006.259.07:31:11.00#ibcon#cleared, iclass 25 cls_cnt 0 2006.259.07:31:11.00$vc4f8/vb=1,4 2006.259.07:31:11.00#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.259.07:31:11.00#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.259.07:31:11.00#ibcon#ireg 11 cls_cnt 2 2006.259.07:31:11.00#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.259.07:31:11.00#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.259.07:31:11.00#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.259.07:31:11.00#ibcon#enter wrdev, iclass 27, count 2 2006.259.07:31:11.00#ibcon#first serial, iclass 27, count 2 2006.259.07:31:11.00#ibcon#enter sib2, iclass 27, count 2 2006.259.07:31:11.00#ibcon#flushed, iclass 27, count 2 2006.259.07:31:11.00#ibcon#about to write, iclass 27, count 2 2006.259.07:31:11.00#ibcon#wrote, iclass 27, count 2 2006.259.07:31:11.00#ibcon#about to read 3, iclass 27, count 2 2006.259.07:31:11.02#ibcon#read 3, iclass 27, count 2 2006.259.07:31:11.02#ibcon#about to read 4, iclass 27, count 2 2006.259.07:31:11.02#ibcon#read 4, iclass 27, count 2 2006.259.07:31:11.02#ibcon#about to read 5, iclass 27, count 2 2006.259.07:31:11.02#ibcon#read 5, iclass 27, count 2 2006.259.07:31:11.02#ibcon#about to read 6, iclass 27, count 2 2006.259.07:31:11.02#ibcon#read 6, iclass 27, count 2 2006.259.07:31:11.02#ibcon#end of sib2, iclass 27, count 2 2006.259.07:31:11.02#ibcon#*mode == 0, iclass 27, count 2 2006.259.07:31:11.02#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.259.07:31:11.02#ibcon#[27=AT01-04\r\n] 2006.259.07:31:11.02#ibcon#*before write, iclass 27, count 2 2006.259.07:31:11.02#ibcon#enter sib2, iclass 27, count 2 2006.259.07:31:11.02#ibcon#flushed, iclass 27, count 2 2006.259.07:31:11.02#ibcon#about to write, iclass 27, count 2 2006.259.07:31:11.02#ibcon#wrote, iclass 27, count 2 2006.259.07:31:11.02#ibcon#about to read 3, iclass 27, count 2 2006.259.07:31:11.05#ibcon#read 3, iclass 27, count 2 2006.259.07:31:11.05#ibcon#about to read 4, iclass 27, count 2 2006.259.07:31:11.05#ibcon#read 4, iclass 27, count 2 2006.259.07:31:11.05#ibcon#about to read 5, iclass 27, count 2 2006.259.07:31:11.05#ibcon#read 5, iclass 27, count 2 2006.259.07:31:11.05#ibcon#about to read 6, iclass 27, count 2 2006.259.07:31:11.05#ibcon#read 6, iclass 27, count 2 2006.259.07:31:11.05#ibcon#end of sib2, iclass 27, count 2 2006.259.07:31:11.05#ibcon#*after write, iclass 27, count 2 2006.259.07:31:11.05#ibcon#*before return 0, iclass 27, count 2 2006.259.07:31:11.05#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.259.07:31:11.05#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.259.07:31:11.05#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.259.07:31:11.05#ibcon#ireg 7 cls_cnt 0 2006.259.07:31:11.05#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.259.07:31:11.17#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.259.07:31:11.17#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.259.07:31:11.17#ibcon#enter wrdev, iclass 27, count 0 2006.259.07:31:11.17#ibcon#first serial, iclass 27, count 0 2006.259.07:31:11.17#ibcon#enter sib2, iclass 27, count 0 2006.259.07:31:11.17#ibcon#flushed, iclass 27, count 0 2006.259.07:31:11.17#ibcon#about to write, iclass 27, count 0 2006.259.07:31:11.17#ibcon#wrote, iclass 27, count 0 2006.259.07:31:11.17#ibcon#about to read 3, iclass 27, count 0 2006.259.07:31:11.19#ibcon#read 3, iclass 27, count 0 2006.259.07:31:11.19#ibcon#about to read 4, iclass 27, count 0 2006.259.07:31:11.19#ibcon#read 4, iclass 27, count 0 2006.259.07:31:11.19#ibcon#about to read 5, iclass 27, count 0 2006.259.07:31:11.19#ibcon#read 5, iclass 27, count 0 2006.259.07:31:11.19#ibcon#about to read 6, iclass 27, count 0 2006.259.07:31:11.19#ibcon#read 6, iclass 27, count 0 2006.259.07:31:11.19#ibcon#end of sib2, iclass 27, count 0 2006.259.07:31:11.19#ibcon#*mode == 0, iclass 27, count 0 2006.259.07:31:11.19#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.259.07:31:11.19#ibcon#[27=USB\r\n] 2006.259.07:31:11.19#ibcon#*before write, iclass 27, count 0 2006.259.07:31:11.19#ibcon#enter sib2, iclass 27, count 0 2006.259.07:31:11.19#ibcon#flushed, iclass 27, count 0 2006.259.07:31:11.19#ibcon#about to write, iclass 27, count 0 2006.259.07:31:11.19#ibcon#wrote, iclass 27, count 0 2006.259.07:31:11.19#ibcon#about to read 3, iclass 27, count 0 2006.259.07:31:11.22#ibcon#read 3, iclass 27, count 0 2006.259.07:31:11.22#ibcon#about to read 4, iclass 27, count 0 2006.259.07:31:11.22#ibcon#read 4, iclass 27, count 0 2006.259.07:31:11.22#ibcon#about to read 5, iclass 27, count 0 2006.259.07:31:11.22#ibcon#read 5, iclass 27, count 0 2006.259.07:31:11.22#ibcon#about to read 6, iclass 27, count 0 2006.259.07:31:11.22#ibcon#read 6, iclass 27, count 0 2006.259.07:31:11.22#ibcon#end of sib2, iclass 27, count 0 2006.259.07:31:11.22#ibcon#*after write, iclass 27, count 0 2006.259.07:31:11.22#ibcon#*before return 0, iclass 27, count 0 2006.259.07:31:11.22#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.259.07:31:11.22#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.259.07:31:11.22#ibcon#about to clear, iclass 27 cls_cnt 0 2006.259.07:31:11.22#ibcon#cleared, iclass 27 cls_cnt 0 2006.259.07:31:11.22$vc4f8/vblo=2,640.99 2006.259.07:31:11.22#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.259.07:31:11.22#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.259.07:31:11.22#ibcon#ireg 17 cls_cnt 0 2006.259.07:31:11.22#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.259.07:31:11.22#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.259.07:31:11.22#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.259.07:31:11.22#ibcon#enter wrdev, iclass 29, count 0 2006.259.07:31:11.22#ibcon#first serial, iclass 29, count 0 2006.259.07:31:11.22#ibcon#enter sib2, iclass 29, count 0 2006.259.07:31:11.22#ibcon#flushed, iclass 29, count 0 2006.259.07:31:11.22#ibcon#about to write, iclass 29, count 0 2006.259.07:31:11.22#ibcon#wrote, iclass 29, count 0 2006.259.07:31:11.22#ibcon#about to read 3, iclass 29, count 0 2006.259.07:31:11.24#ibcon#read 3, iclass 29, count 0 2006.259.07:31:11.24#ibcon#about to read 4, iclass 29, count 0 2006.259.07:31:11.24#ibcon#read 4, iclass 29, count 0 2006.259.07:31:11.24#ibcon#about to read 5, iclass 29, count 0 2006.259.07:31:11.24#ibcon#read 5, iclass 29, count 0 2006.259.07:31:11.24#ibcon#about to read 6, iclass 29, count 0 2006.259.07:31:11.24#ibcon#read 6, iclass 29, count 0 2006.259.07:31:11.24#ibcon#end of sib2, iclass 29, count 0 2006.259.07:31:11.24#ibcon#*mode == 0, iclass 29, count 0 2006.259.07:31:11.24#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.259.07:31:11.24#ibcon#[28=FRQ=02,640.99\r\n] 2006.259.07:31:11.24#ibcon#*before write, iclass 29, count 0 2006.259.07:31:11.24#ibcon#enter sib2, iclass 29, count 0 2006.259.07:31:11.24#ibcon#flushed, iclass 29, count 0 2006.259.07:31:11.24#ibcon#about to write, iclass 29, count 0 2006.259.07:31:11.24#ibcon#wrote, iclass 29, count 0 2006.259.07:31:11.24#ibcon#about to read 3, iclass 29, count 0 2006.259.07:31:11.28#ibcon#read 3, iclass 29, count 0 2006.259.07:31:11.28#ibcon#about to read 4, iclass 29, count 0 2006.259.07:31:11.28#ibcon#read 4, iclass 29, count 0 2006.259.07:31:11.28#ibcon#about to read 5, iclass 29, count 0 2006.259.07:31:11.28#ibcon#read 5, iclass 29, count 0 2006.259.07:31:11.28#ibcon#about to read 6, iclass 29, count 0 2006.259.07:31:11.28#ibcon#read 6, iclass 29, count 0 2006.259.07:31:11.28#ibcon#end of sib2, iclass 29, count 0 2006.259.07:31:11.28#ibcon#*after write, iclass 29, count 0 2006.259.07:31:11.28#ibcon#*before return 0, iclass 29, count 0 2006.259.07:31:11.28#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.259.07:31:11.28#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.259.07:31:11.28#ibcon#about to clear, iclass 29 cls_cnt 0 2006.259.07:31:11.28#ibcon#cleared, iclass 29 cls_cnt 0 2006.259.07:31:11.28$vc4f8/vb=2,5 2006.259.07:31:11.28#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.259.07:31:11.28#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.259.07:31:11.28#ibcon#ireg 11 cls_cnt 2 2006.259.07:31:11.28#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.259.07:31:11.34#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.259.07:31:11.34#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.259.07:31:11.34#ibcon#enter wrdev, iclass 31, count 2 2006.259.07:31:11.34#ibcon#first serial, iclass 31, count 2 2006.259.07:31:11.34#ibcon#enter sib2, iclass 31, count 2 2006.259.07:31:11.34#ibcon#flushed, iclass 31, count 2 2006.259.07:31:11.34#ibcon#about to write, iclass 31, count 2 2006.259.07:31:11.34#ibcon#wrote, iclass 31, count 2 2006.259.07:31:11.34#ibcon#about to read 3, iclass 31, count 2 2006.259.07:31:11.36#ibcon#read 3, iclass 31, count 2 2006.259.07:31:11.36#ibcon#about to read 4, iclass 31, count 2 2006.259.07:31:11.36#ibcon#read 4, iclass 31, count 2 2006.259.07:31:11.36#ibcon#about to read 5, iclass 31, count 2 2006.259.07:31:11.36#ibcon#read 5, iclass 31, count 2 2006.259.07:31:11.36#ibcon#about to read 6, iclass 31, count 2 2006.259.07:31:11.36#ibcon#read 6, iclass 31, count 2 2006.259.07:31:11.36#ibcon#end of sib2, iclass 31, count 2 2006.259.07:31:11.36#ibcon#*mode == 0, iclass 31, count 2 2006.259.07:31:11.36#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.259.07:31:11.36#ibcon#[27=AT02-05\r\n] 2006.259.07:31:11.36#ibcon#*before write, iclass 31, count 2 2006.259.07:31:11.36#ibcon#enter sib2, iclass 31, count 2 2006.259.07:31:11.36#ibcon#flushed, iclass 31, count 2 2006.259.07:31:11.36#ibcon#about to write, iclass 31, count 2 2006.259.07:31:11.36#ibcon#wrote, iclass 31, count 2 2006.259.07:31:11.36#ibcon#about to read 3, iclass 31, count 2 2006.259.07:31:11.39#ibcon#read 3, iclass 31, count 2 2006.259.07:31:11.39#ibcon#about to read 4, iclass 31, count 2 2006.259.07:31:11.39#ibcon#read 4, iclass 31, count 2 2006.259.07:31:11.39#ibcon#about to read 5, iclass 31, count 2 2006.259.07:31:11.39#ibcon#read 5, iclass 31, count 2 2006.259.07:31:11.39#ibcon#about to read 6, iclass 31, count 2 2006.259.07:31:11.39#ibcon#read 6, iclass 31, count 2 2006.259.07:31:11.39#ibcon#end of sib2, iclass 31, count 2 2006.259.07:31:11.39#ibcon#*after write, iclass 31, count 2 2006.259.07:31:11.39#ibcon#*before return 0, iclass 31, count 2 2006.259.07:31:11.39#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.259.07:31:11.39#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.259.07:31:11.39#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.259.07:31:11.39#ibcon#ireg 7 cls_cnt 0 2006.259.07:31:11.39#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.259.07:31:11.51#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.259.07:31:11.51#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.259.07:31:11.51#ibcon#enter wrdev, iclass 31, count 0 2006.259.07:31:11.51#ibcon#first serial, iclass 31, count 0 2006.259.07:31:11.51#ibcon#enter sib2, iclass 31, count 0 2006.259.07:31:11.51#ibcon#flushed, iclass 31, count 0 2006.259.07:31:11.51#ibcon#about to write, iclass 31, count 0 2006.259.07:31:11.51#ibcon#wrote, iclass 31, count 0 2006.259.07:31:11.51#ibcon#about to read 3, iclass 31, count 0 2006.259.07:31:11.53#ibcon#read 3, iclass 31, count 0 2006.259.07:31:11.53#ibcon#about to read 4, iclass 31, count 0 2006.259.07:31:11.53#ibcon#read 4, iclass 31, count 0 2006.259.07:31:11.53#ibcon#about to read 5, iclass 31, count 0 2006.259.07:31:11.53#ibcon#read 5, iclass 31, count 0 2006.259.07:31:11.53#ibcon#about to read 6, iclass 31, count 0 2006.259.07:31:11.53#ibcon#read 6, iclass 31, count 0 2006.259.07:31:11.53#ibcon#end of sib2, iclass 31, count 0 2006.259.07:31:11.53#ibcon#*mode == 0, iclass 31, count 0 2006.259.07:31:11.53#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.259.07:31:11.53#ibcon#[27=USB\r\n] 2006.259.07:31:11.53#ibcon#*before write, iclass 31, count 0 2006.259.07:31:11.53#ibcon#enter sib2, iclass 31, count 0 2006.259.07:31:11.53#ibcon#flushed, iclass 31, count 0 2006.259.07:31:11.53#ibcon#about to write, iclass 31, count 0 2006.259.07:31:11.53#ibcon#wrote, iclass 31, count 0 2006.259.07:31:11.53#ibcon#about to read 3, iclass 31, count 0 2006.259.07:31:11.56#ibcon#read 3, iclass 31, count 0 2006.259.07:31:11.56#ibcon#about to read 4, iclass 31, count 0 2006.259.07:31:11.56#ibcon#read 4, iclass 31, count 0 2006.259.07:31:11.56#ibcon#about to read 5, iclass 31, count 0 2006.259.07:31:11.56#ibcon#read 5, iclass 31, count 0 2006.259.07:31:11.56#ibcon#about to read 6, iclass 31, count 0 2006.259.07:31:11.56#ibcon#read 6, iclass 31, count 0 2006.259.07:31:11.56#ibcon#end of sib2, iclass 31, count 0 2006.259.07:31:11.56#ibcon#*after write, iclass 31, count 0 2006.259.07:31:11.56#ibcon#*before return 0, iclass 31, count 0 2006.259.07:31:11.56#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.259.07:31:11.56#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.259.07:31:11.56#ibcon#about to clear, iclass 31 cls_cnt 0 2006.259.07:31:11.56#ibcon#cleared, iclass 31 cls_cnt 0 2006.259.07:31:11.56$vc4f8/vblo=3,656.99 2006.259.07:31:11.56#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.259.07:31:11.56#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.259.07:31:11.56#ibcon#ireg 17 cls_cnt 0 2006.259.07:31:11.56#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.259.07:31:11.56#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.259.07:31:11.56#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.259.07:31:11.56#ibcon#enter wrdev, iclass 33, count 0 2006.259.07:31:11.56#ibcon#first serial, iclass 33, count 0 2006.259.07:31:11.56#ibcon#enter sib2, iclass 33, count 0 2006.259.07:31:11.56#ibcon#flushed, iclass 33, count 0 2006.259.07:31:11.56#ibcon#about to write, iclass 33, count 0 2006.259.07:31:11.56#ibcon#wrote, iclass 33, count 0 2006.259.07:31:11.56#ibcon#about to read 3, iclass 33, count 0 2006.259.07:31:11.58#ibcon#read 3, iclass 33, count 0 2006.259.07:31:11.58#ibcon#about to read 4, iclass 33, count 0 2006.259.07:31:11.58#ibcon#read 4, iclass 33, count 0 2006.259.07:31:11.58#ibcon#about to read 5, iclass 33, count 0 2006.259.07:31:11.58#ibcon#read 5, iclass 33, count 0 2006.259.07:31:11.58#ibcon#about to read 6, iclass 33, count 0 2006.259.07:31:11.58#ibcon#read 6, iclass 33, count 0 2006.259.07:31:11.58#ibcon#end of sib2, iclass 33, count 0 2006.259.07:31:11.58#ibcon#*mode == 0, iclass 33, count 0 2006.259.07:31:11.58#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.259.07:31:11.58#ibcon#[28=FRQ=03,656.99\r\n] 2006.259.07:31:11.58#ibcon#*before write, iclass 33, count 0 2006.259.07:31:11.58#ibcon#enter sib2, iclass 33, count 0 2006.259.07:31:11.58#ibcon#flushed, iclass 33, count 0 2006.259.07:31:11.58#ibcon#about to write, iclass 33, count 0 2006.259.07:31:11.58#ibcon#wrote, iclass 33, count 0 2006.259.07:31:11.58#ibcon#about to read 3, iclass 33, count 0 2006.259.07:31:11.62#ibcon#read 3, iclass 33, count 0 2006.259.07:31:11.62#ibcon#about to read 4, iclass 33, count 0 2006.259.07:31:11.62#ibcon#read 4, iclass 33, count 0 2006.259.07:31:11.62#ibcon#about to read 5, iclass 33, count 0 2006.259.07:31:11.62#ibcon#read 5, iclass 33, count 0 2006.259.07:31:11.62#ibcon#about to read 6, iclass 33, count 0 2006.259.07:31:11.62#ibcon#read 6, iclass 33, count 0 2006.259.07:31:11.62#ibcon#end of sib2, iclass 33, count 0 2006.259.07:31:11.62#ibcon#*after write, iclass 33, count 0 2006.259.07:31:11.62#ibcon#*before return 0, iclass 33, count 0 2006.259.07:31:11.62#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.259.07:31:11.62#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.259.07:31:11.62#ibcon#about to clear, iclass 33 cls_cnt 0 2006.259.07:31:11.62#ibcon#cleared, iclass 33 cls_cnt 0 2006.259.07:31:11.62$vc4f8/vb=3,4 2006.259.07:31:11.62#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.259.07:31:11.62#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.259.07:31:11.62#ibcon#ireg 11 cls_cnt 2 2006.259.07:31:11.62#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.259.07:31:11.68#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.259.07:31:11.68#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.259.07:31:11.68#ibcon#enter wrdev, iclass 35, count 2 2006.259.07:31:11.68#ibcon#first serial, iclass 35, count 2 2006.259.07:31:11.68#ibcon#enter sib2, iclass 35, count 2 2006.259.07:31:11.68#ibcon#flushed, iclass 35, count 2 2006.259.07:31:11.68#ibcon#about to write, iclass 35, count 2 2006.259.07:31:11.68#ibcon#wrote, iclass 35, count 2 2006.259.07:31:11.68#ibcon#about to read 3, iclass 35, count 2 2006.259.07:31:11.70#ibcon#read 3, iclass 35, count 2 2006.259.07:31:11.70#ibcon#about to read 4, iclass 35, count 2 2006.259.07:31:11.70#ibcon#read 4, iclass 35, count 2 2006.259.07:31:11.70#ibcon#about to read 5, iclass 35, count 2 2006.259.07:31:11.70#ibcon#read 5, iclass 35, count 2 2006.259.07:31:11.70#ibcon#about to read 6, iclass 35, count 2 2006.259.07:31:11.70#ibcon#read 6, iclass 35, count 2 2006.259.07:31:11.70#ibcon#end of sib2, iclass 35, count 2 2006.259.07:31:11.70#ibcon#*mode == 0, iclass 35, count 2 2006.259.07:31:11.70#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.259.07:31:11.70#ibcon#[27=AT03-04\r\n] 2006.259.07:31:11.70#ibcon#*before write, iclass 35, count 2 2006.259.07:31:11.70#ibcon#enter sib2, iclass 35, count 2 2006.259.07:31:11.70#ibcon#flushed, iclass 35, count 2 2006.259.07:31:11.70#ibcon#about to write, iclass 35, count 2 2006.259.07:31:11.70#ibcon#wrote, iclass 35, count 2 2006.259.07:31:11.70#ibcon#about to read 3, iclass 35, count 2 2006.259.07:31:11.73#ibcon#read 3, iclass 35, count 2 2006.259.07:31:11.73#ibcon#about to read 4, iclass 35, count 2 2006.259.07:31:11.73#ibcon#read 4, iclass 35, count 2 2006.259.07:31:11.73#ibcon#about to read 5, iclass 35, count 2 2006.259.07:31:11.73#ibcon#read 5, iclass 35, count 2 2006.259.07:31:11.73#ibcon#about to read 6, iclass 35, count 2 2006.259.07:31:11.73#ibcon#read 6, iclass 35, count 2 2006.259.07:31:11.73#ibcon#end of sib2, iclass 35, count 2 2006.259.07:31:11.73#ibcon#*after write, iclass 35, count 2 2006.259.07:31:11.73#ibcon#*before return 0, iclass 35, count 2 2006.259.07:31:11.73#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.259.07:31:11.73#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.259.07:31:11.73#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.259.07:31:11.73#ibcon#ireg 7 cls_cnt 0 2006.259.07:31:11.73#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.259.07:31:11.85#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.259.07:31:11.85#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.259.07:31:11.85#ibcon#enter wrdev, iclass 35, count 0 2006.259.07:31:11.85#ibcon#first serial, iclass 35, count 0 2006.259.07:31:11.85#ibcon#enter sib2, iclass 35, count 0 2006.259.07:31:11.85#ibcon#flushed, iclass 35, count 0 2006.259.07:31:11.85#ibcon#about to write, iclass 35, count 0 2006.259.07:31:11.85#ibcon#wrote, iclass 35, count 0 2006.259.07:31:11.85#ibcon#about to read 3, iclass 35, count 0 2006.259.07:31:11.87#ibcon#read 3, iclass 35, count 0 2006.259.07:31:11.87#ibcon#about to read 4, iclass 35, count 0 2006.259.07:31:11.87#ibcon#read 4, iclass 35, count 0 2006.259.07:31:11.87#ibcon#about to read 5, iclass 35, count 0 2006.259.07:31:11.87#ibcon#read 5, iclass 35, count 0 2006.259.07:31:11.87#ibcon#about to read 6, iclass 35, count 0 2006.259.07:31:11.87#ibcon#read 6, iclass 35, count 0 2006.259.07:31:11.87#ibcon#end of sib2, iclass 35, count 0 2006.259.07:31:11.87#ibcon#*mode == 0, iclass 35, count 0 2006.259.07:31:11.87#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.259.07:31:11.87#ibcon#[27=USB\r\n] 2006.259.07:31:11.87#ibcon#*before write, iclass 35, count 0 2006.259.07:31:11.87#ibcon#enter sib2, iclass 35, count 0 2006.259.07:31:11.87#ibcon#flushed, iclass 35, count 0 2006.259.07:31:11.87#ibcon#about to write, iclass 35, count 0 2006.259.07:31:11.87#ibcon#wrote, iclass 35, count 0 2006.259.07:31:11.87#ibcon#about to read 3, iclass 35, count 0 2006.259.07:31:11.90#ibcon#read 3, iclass 35, count 0 2006.259.07:31:11.90#ibcon#about to read 4, iclass 35, count 0 2006.259.07:31:11.90#ibcon#read 4, iclass 35, count 0 2006.259.07:31:11.90#ibcon#about to read 5, iclass 35, count 0 2006.259.07:31:11.90#ibcon#read 5, iclass 35, count 0 2006.259.07:31:11.90#ibcon#about to read 6, iclass 35, count 0 2006.259.07:31:11.90#ibcon#read 6, iclass 35, count 0 2006.259.07:31:11.90#ibcon#end of sib2, iclass 35, count 0 2006.259.07:31:11.90#ibcon#*after write, iclass 35, count 0 2006.259.07:31:11.90#ibcon#*before return 0, iclass 35, count 0 2006.259.07:31:11.90#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.259.07:31:11.90#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.259.07:31:11.90#ibcon#about to clear, iclass 35 cls_cnt 0 2006.259.07:31:11.90#ibcon#cleared, iclass 35 cls_cnt 0 2006.259.07:31:11.90$vc4f8/vblo=4,712.99 2006.259.07:31:11.90#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.259.07:31:11.90#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.259.07:31:11.90#ibcon#ireg 17 cls_cnt 0 2006.259.07:31:11.90#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.259.07:31:11.90#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.259.07:31:11.90#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.259.07:31:11.90#ibcon#enter wrdev, iclass 37, count 0 2006.259.07:31:11.90#ibcon#first serial, iclass 37, count 0 2006.259.07:31:11.90#ibcon#enter sib2, iclass 37, count 0 2006.259.07:31:11.90#ibcon#flushed, iclass 37, count 0 2006.259.07:31:11.90#ibcon#about to write, iclass 37, count 0 2006.259.07:31:11.90#ibcon#wrote, iclass 37, count 0 2006.259.07:31:11.90#ibcon#about to read 3, iclass 37, count 0 2006.259.07:31:11.92#ibcon#read 3, iclass 37, count 0 2006.259.07:31:11.92#ibcon#about to read 4, iclass 37, count 0 2006.259.07:31:11.92#ibcon#read 4, iclass 37, count 0 2006.259.07:31:11.92#ibcon#about to read 5, iclass 37, count 0 2006.259.07:31:11.92#ibcon#read 5, iclass 37, count 0 2006.259.07:31:11.92#ibcon#about to read 6, iclass 37, count 0 2006.259.07:31:11.92#ibcon#read 6, iclass 37, count 0 2006.259.07:31:11.92#ibcon#end of sib2, iclass 37, count 0 2006.259.07:31:11.92#ibcon#*mode == 0, iclass 37, count 0 2006.259.07:31:11.92#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.259.07:31:11.92#ibcon#[28=FRQ=04,712.99\r\n] 2006.259.07:31:11.92#ibcon#*before write, iclass 37, count 0 2006.259.07:31:11.92#ibcon#enter sib2, iclass 37, count 0 2006.259.07:31:11.92#ibcon#flushed, iclass 37, count 0 2006.259.07:31:11.92#ibcon#about to write, iclass 37, count 0 2006.259.07:31:11.92#ibcon#wrote, iclass 37, count 0 2006.259.07:31:11.92#ibcon#about to read 3, iclass 37, count 0 2006.259.07:31:11.96#ibcon#read 3, iclass 37, count 0 2006.259.07:31:11.96#ibcon#about to read 4, iclass 37, count 0 2006.259.07:31:11.96#ibcon#read 4, iclass 37, count 0 2006.259.07:31:11.96#ibcon#about to read 5, iclass 37, count 0 2006.259.07:31:11.96#ibcon#read 5, iclass 37, count 0 2006.259.07:31:11.96#ibcon#about to read 6, iclass 37, count 0 2006.259.07:31:11.96#ibcon#read 6, iclass 37, count 0 2006.259.07:31:11.96#ibcon#end of sib2, iclass 37, count 0 2006.259.07:31:11.96#ibcon#*after write, iclass 37, count 0 2006.259.07:31:11.96#ibcon#*before return 0, iclass 37, count 0 2006.259.07:31:11.96#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.259.07:31:11.96#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.259.07:31:11.96#ibcon#about to clear, iclass 37 cls_cnt 0 2006.259.07:31:11.96#ibcon#cleared, iclass 37 cls_cnt 0 2006.259.07:31:11.96$vc4f8/vb=4,5 2006.259.07:31:11.96#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.259.07:31:11.96#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.259.07:31:11.96#ibcon#ireg 11 cls_cnt 2 2006.259.07:31:11.96#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.259.07:31:12.02#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.259.07:31:12.02#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.259.07:31:12.02#ibcon#enter wrdev, iclass 39, count 2 2006.259.07:31:12.02#ibcon#first serial, iclass 39, count 2 2006.259.07:31:12.02#ibcon#enter sib2, iclass 39, count 2 2006.259.07:31:12.02#ibcon#flushed, iclass 39, count 2 2006.259.07:31:12.02#ibcon#about to write, iclass 39, count 2 2006.259.07:31:12.02#ibcon#wrote, iclass 39, count 2 2006.259.07:31:12.02#ibcon#about to read 3, iclass 39, count 2 2006.259.07:31:12.04#ibcon#read 3, iclass 39, count 2 2006.259.07:31:12.04#ibcon#about to read 4, iclass 39, count 2 2006.259.07:31:12.04#ibcon#read 4, iclass 39, count 2 2006.259.07:31:12.04#ibcon#about to read 5, iclass 39, count 2 2006.259.07:31:12.04#ibcon#read 5, iclass 39, count 2 2006.259.07:31:12.04#ibcon#about to read 6, iclass 39, count 2 2006.259.07:31:12.04#ibcon#read 6, iclass 39, count 2 2006.259.07:31:12.04#ibcon#end of sib2, iclass 39, count 2 2006.259.07:31:12.04#ibcon#*mode == 0, iclass 39, count 2 2006.259.07:31:12.04#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.259.07:31:12.04#ibcon#[27=AT04-05\r\n] 2006.259.07:31:12.04#ibcon#*before write, iclass 39, count 2 2006.259.07:31:12.04#ibcon#enter sib2, iclass 39, count 2 2006.259.07:31:12.04#ibcon#flushed, iclass 39, count 2 2006.259.07:31:12.04#ibcon#about to write, iclass 39, count 2 2006.259.07:31:12.04#ibcon#wrote, iclass 39, count 2 2006.259.07:31:12.04#ibcon#about to read 3, iclass 39, count 2 2006.259.07:31:12.07#ibcon#read 3, iclass 39, count 2 2006.259.07:31:12.07#ibcon#about to read 4, iclass 39, count 2 2006.259.07:31:12.07#ibcon#read 4, iclass 39, count 2 2006.259.07:31:12.07#ibcon#about to read 5, iclass 39, count 2 2006.259.07:31:12.07#ibcon#read 5, iclass 39, count 2 2006.259.07:31:12.07#ibcon#about to read 6, iclass 39, count 2 2006.259.07:31:12.07#ibcon#read 6, iclass 39, count 2 2006.259.07:31:12.07#ibcon#end of sib2, iclass 39, count 2 2006.259.07:31:12.07#ibcon#*after write, iclass 39, count 2 2006.259.07:31:12.07#ibcon#*before return 0, iclass 39, count 2 2006.259.07:31:12.07#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.259.07:31:12.07#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.259.07:31:12.07#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.259.07:31:12.07#ibcon#ireg 7 cls_cnt 0 2006.259.07:31:12.07#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.259.07:31:12.19#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.259.07:31:12.19#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.259.07:31:12.19#ibcon#enter wrdev, iclass 39, count 0 2006.259.07:31:12.19#ibcon#first serial, iclass 39, count 0 2006.259.07:31:12.19#ibcon#enter sib2, iclass 39, count 0 2006.259.07:31:12.19#ibcon#flushed, iclass 39, count 0 2006.259.07:31:12.19#ibcon#about to write, iclass 39, count 0 2006.259.07:31:12.19#ibcon#wrote, iclass 39, count 0 2006.259.07:31:12.19#ibcon#about to read 3, iclass 39, count 0 2006.259.07:31:12.21#ibcon#read 3, iclass 39, count 0 2006.259.07:31:12.21#ibcon#about to read 4, iclass 39, count 0 2006.259.07:31:12.21#ibcon#read 4, iclass 39, count 0 2006.259.07:31:12.21#ibcon#about to read 5, iclass 39, count 0 2006.259.07:31:12.21#ibcon#read 5, iclass 39, count 0 2006.259.07:31:12.21#ibcon#about to read 6, iclass 39, count 0 2006.259.07:31:12.21#ibcon#read 6, iclass 39, count 0 2006.259.07:31:12.21#ibcon#end of sib2, iclass 39, count 0 2006.259.07:31:12.21#ibcon#*mode == 0, iclass 39, count 0 2006.259.07:31:12.21#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.259.07:31:12.21#ibcon#[27=USB\r\n] 2006.259.07:31:12.21#ibcon#*before write, iclass 39, count 0 2006.259.07:31:12.21#ibcon#enter sib2, iclass 39, count 0 2006.259.07:31:12.21#ibcon#flushed, iclass 39, count 0 2006.259.07:31:12.21#ibcon#about to write, iclass 39, count 0 2006.259.07:31:12.21#ibcon#wrote, iclass 39, count 0 2006.259.07:31:12.21#ibcon#about to read 3, iclass 39, count 0 2006.259.07:31:12.24#ibcon#read 3, iclass 39, count 0 2006.259.07:31:12.24#ibcon#about to read 4, iclass 39, count 0 2006.259.07:31:12.24#ibcon#read 4, iclass 39, count 0 2006.259.07:31:12.24#ibcon#about to read 5, iclass 39, count 0 2006.259.07:31:12.24#ibcon#read 5, iclass 39, count 0 2006.259.07:31:12.24#ibcon#about to read 6, iclass 39, count 0 2006.259.07:31:12.24#ibcon#read 6, iclass 39, count 0 2006.259.07:31:12.24#ibcon#end of sib2, iclass 39, count 0 2006.259.07:31:12.24#ibcon#*after write, iclass 39, count 0 2006.259.07:31:12.24#ibcon#*before return 0, iclass 39, count 0 2006.259.07:31:12.24#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.259.07:31:12.24#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.259.07:31:12.24#ibcon#about to clear, iclass 39 cls_cnt 0 2006.259.07:31:12.24#ibcon#cleared, iclass 39 cls_cnt 0 2006.259.07:31:12.24$vc4f8/vblo=5,744.99 2006.259.07:31:12.24#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.259.07:31:12.24#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.259.07:31:12.24#ibcon#ireg 17 cls_cnt 0 2006.259.07:31:12.24#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.259.07:31:12.24#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.259.07:31:12.24#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.259.07:31:12.24#ibcon#enter wrdev, iclass 3, count 0 2006.259.07:31:12.24#ibcon#first serial, iclass 3, count 0 2006.259.07:31:12.24#ibcon#enter sib2, iclass 3, count 0 2006.259.07:31:12.24#ibcon#flushed, iclass 3, count 0 2006.259.07:31:12.24#ibcon#about to write, iclass 3, count 0 2006.259.07:31:12.24#ibcon#wrote, iclass 3, count 0 2006.259.07:31:12.24#ibcon#about to read 3, iclass 3, count 0 2006.259.07:31:12.26#ibcon#read 3, iclass 3, count 0 2006.259.07:31:12.26#ibcon#about to read 4, iclass 3, count 0 2006.259.07:31:12.26#ibcon#read 4, iclass 3, count 0 2006.259.07:31:12.26#ibcon#about to read 5, iclass 3, count 0 2006.259.07:31:12.26#ibcon#read 5, iclass 3, count 0 2006.259.07:31:12.26#ibcon#about to read 6, iclass 3, count 0 2006.259.07:31:12.26#ibcon#read 6, iclass 3, count 0 2006.259.07:31:12.26#ibcon#end of sib2, iclass 3, count 0 2006.259.07:31:12.26#ibcon#*mode == 0, iclass 3, count 0 2006.259.07:31:12.26#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.259.07:31:12.26#ibcon#[28=FRQ=05,744.99\r\n] 2006.259.07:31:12.26#ibcon#*before write, iclass 3, count 0 2006.259.07:31:12.26#ibcon#enter sib2, iclass 3, count 0 2006.259.07:31:12.26#ibcon#flushed, iclass 3, count 0 2006.259.07:31:12.26#ibcon#about to write, iclass 3, count 0 2006.259.07:31:12.26#ibcon#wrote, iclass 3, count 0 2006.259.07:31:12.26#ibcon#about to read 3, iclass 3, count 0 2006.259.07:31:12.30#ibcon#read 3, iclass 3, count 0 2006.259.07:31:12.30#ibcon#about to read 4, iclass 3, count 0 2006.259.07:31:12.30#ibcon#read 4, iclass 3, count 0 2006.259.07:31:12.30#ibcon#about to read 5, iclass 3, count 0 2006.259.07:31:12.30#ibcon#read 5, iclass 3, count 0 2006.259.07:31:12.30#ibcon#about to read 6, iclass 3, count 0 2006.259.07:31:12.30#ibcon#read 6, iclass 3, count 0 2006.259.07:31:12.30#ibcon#end of sib2, iclass 3, count 0 2006.259.07:31:12.30#ibcon#*after write, iclass 3, count 0 2006.259.07:31:12.30#ibcon#*before return 0, iclass 3, count 0 2006.259.07:31:12.30#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.259.07:31:12.30#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.259.07:31:12.30#ibcon#about to clear, iclass 3 cls_cnt 0 2006.259.07:31:12.30#ibcon#cleared, iclass 3 cls_cnt 0 2006.259.07:31:12.30$vc4f8/vb=5,4 2006.259.07:31:12.30#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.259.07:31:12.30#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.259.07:31:12.30#ibcon#ireg 11 cls_cnt 2 2006.259.07:31:12.30#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.259.07:31:12.36#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.259.07:31:12.36#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.259.07:31:12.36#ibcon#enter wrdev, iclass 5, count 2 2006.259.07:31:12.36#ibcon#first serial, iclass 5, count 2 2006.259.07:31:12.36#ibcon#enter sib2, iclass 5, count 2 2006.259.07:31:12.36#ibcon#flushed, iclass 5, count 2 2006.259.07:31:12.36#ibcon#about to write, iclass 5, count 2 2006.259.07:31:12.36#ibcon#wrote, iclass 5, count 2 2006.259.07:31:12.36#ibcon#about to read 3, iclass 5, count 2 2006.259.07:31:12.38#ibcon#read 3, iclass 5, count 2 2006.259.07:31:12.38#ibcon#about to read 4, iclass 5, count 2 2006.259.07:31:12.38#ibcon#read 4, iclass 5, count 2 2006.259.07:31:12.38#ibcon#about to read 5, iclass 5, count 2 2006.259.07:31:12.38#ibcon#read 5, iclass 5, count 2 2006.259.07:31:12.38#ibcon#about to read 6, iclass 5, count 2 2006.259.07:31:12.38#ibcon#read 6, iclass 5, count 2 2006.259.07:31:12.38#ibcon#end of sib2, iclass 5, count 2 2006.259.07:31:12.38#ibcon#*mode == 0, iclass 5, count 2 2006.259.07:31:12.38#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.259.07:31:12.38#ibcon#[27=AT05-04\r\n] 2006.259.07:31:12.38#ibcon#*before write, iclass 5, count 2 2006.259.07:31:12.38#ibcon#enter sib2, iclass 5, count 2 2006.259.07:31:12.38#ibcon#flushed, iclass 5, count 2 2006.259.07:31:12.38#ibcon#about to write, iclass 5, count 2 2006.259.07:31:12.38#ibcon#wrote, iclass 5, count 2 2006.259.07:31:12.38#ibcon#about to read 3, iclass 5, count 2 2006.259.07:31:12.41#ibcon#read 3, iclass 5, count 2 2006.259.07:31:12.41#ibcon#about to read 4, iclass 5, count 2 2006.259.07:31:12.41#ibcon#read 4, iclass 5, count 2 2006.259.07:31:12.41#ibcon#about to read 5, iclass 5, count 2 2006.259.07:31:12.41#ibcon#read 5, iclass 5, count 2 2006.259.07:31:12.41#ibcon#about to read 6, iclass 5, count 2 2006.259.07:31:12.41#ibcon#read 6, iclass 5, count 2 2006.259.07:31:12.41#ibcon#end of sib2, iclass 5, count 2 2006.259.07:31:12.41#ibcon#*after write, iclass 5, count 2 2006.259.07:31:12.41#ibcon#*before return 0, iclass 5, count 2 2006.259.07:31:12.41#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.259.07:31:12.41#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.259.07:31:12.41#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.259.07:31:12.41#ibcon#ireg 7 cls_cnt 0 2006.259.07:31:12.41#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.259.07:31:12.53#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.259.07:31:12.53#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.259.07:31:12.53#ibcon#enter wrdev, iclass 5, count 0 2006.259.07:31:12.53#ibcon#first serial, iclass 5, count 0 2006.259.07:31:12.53#ibcon#enter sib2, iclass 5, count 0 2006.259.07:31:12.53#ibcon#flushed, iclass 5, count 0 2006.259.07:31:12.53#ibcon#about to write, iclass 5, count 0 2006.259.07:31:12.53#ibcon#wrote, iclass 5, count 0 2006.259.07:31:12.53#ibcon#about to read 3, iclass 5, count 0 2006.259.07:31:12.55#ibcon#read 3, iclass 5, count 0 2006.259.07:31:12.55#ibcon#about to read 4, iclass 5, count 0 2006.259.07:31:12.55#ibcon#read 4, iclass 5, count 0 2006.259.07:31:12.55#ibcon#about to read 5, iclass 5, count 0 2006.259.07:31:12.55#ibcon#read 5, iclass 5, count 0 2006.259.07:31:12.55#ibcon#about to read 6, iclass 5, count 0 2006.259.07:31:12.55#ibcon#read 6, iclass 5, count 0 2006.259.07:31:12.55#ibcon#end of sib2, iclass 5, count 0 2006.259.07:31:12.55#ibcon#*mode == 0, iclass 5, count 0 2006.259.07:31:12.55#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.259.07:31:12.55#ibcon#[27=USB\r\n] 2006.259.07:31:12.55#ibcon#*before write, iclass 5, count 0 2006.259.07:31:12.55#ibcon#enter sib2, iclass 5, count 0 2006.259.07:31:12.55#ibcon#flushed, iclass 5, count 0 2006.259.07:31:12.55#ibcon#about to write, iclass 5, count 0 2006.259.07:31:12.55#ibcon#wrote, iclass 5, count 0 2006.259.07:31:12.55#ibcon#about to read 3, iclass 5, count 0 2006.259.07:31:12.58#ibcon#read 3, iclass 5, count 0 2006.259.07:31:12.58#ibcon#about to read 4, iclass 5, count 0 2006.259.07:31:12.58#ibcon#read 4, iclass 5, count 0 2006.259.07:31:12.58#ibcon#about to read 5, iclass 5, count 0 2006.259.07:31:12.58#ibcon#read 5, iclass 5, count 0 2006.259.07:31:12.58#ibcon#about to read 6, iclass 5, count 0 2006.259.07:31:12.58#ibcon#read 6, iclass 5, count 0 2006.259.07:31:12.58#ibcon#end of sib2, iclass 5, count 0 2006.259.07:31:12.58#ibcon#*after write, iclass 5, count 0 2006.259.07:31:12.58#ibcon#*before return 0, iclass 5, count 0 2006.259.07:31:12.58#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.259.07:31:12.58#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.259.07:31:12.58#ibcon#about to clear, iclass 5 cls_cnt 0 2006.259.07:31:12.58#ibcon#cleared, iclass 5 cls_cnt 0 2006.259.07:31:12.58$vc4f8/vblo=6,752.99 2006.259.07:31:12.58#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.259.07:31:12.58#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.259.07:31:12.58#ibcon#ireg 17 cls_cnt 0 2006.259.07:31:12.58#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.259.07:31:12.58#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.259.07:31:12.58#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.259.07:31:12.58#ibcon#enter wrdev, iclass 7, count 0 2006.259.07:31:12.58#ibcon#first serial, iclass 7, count 0 2006.259.07:31:12.58#ibcon#enter sib2, iclass 7, count 0 2006.259.07:31:12.58#ibcon#flushed, iclass 7, count 0 2006.259.07:31:12.58#ibcon#about to write, iclass 7, count 0 2006.259.07:31:12.58#ibcon#wrote, iclass 7, count 0 2006.259.07:31:12.58#ibcon#about to read 3, iclass 7, count 0 2006.259.07:31:12.60#ibcon#read 3, iclass 7, count 0 2006.259.07:31:12.60#ibcon#about to read 4, iclass 7, count 0 2006.259.07:31:12.60#ibcon#read 4, iclass 7, count 0 2006.259.07:31:12.60#ibcon#about to read 5, iclass 7, count 0 2006.259.07:31:12.60#ibcon#read 5, iclass 7, count 0 2006.259.07:31:12.60#ibcon#about to read 6, iclass 7, count 0 2006.259.07:31:12.60#ibcon#read 6, iclass 7, count 0 2006.259.07:31:12.60#ibcon#end of sib2, iclass 7, count 0 2006.259.07:31:12.60#ibcon#*mode == 0, iclass 7, count 0 2006.259.07:31:12.60#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.259.07:31:12.60#ibcon#[28=FRQ=06,752.99\r\n] 2006.259.07:31:12.60#ibcon#*before write, iclass 7, count 0 2006.259.07:31:12.60#ibcon#enter sib2, iclass 7, count 0 2006.259.07:31:12.60#ibcon#flushed, iclass 7, count 0 2006.259.07:31:12.60#ibcon#about to write, iclass 7, count 0 2006.259.07:31:12.60#ibcon#wrote, iclass 7, count 0 2006.259.07:31:12.60#ibcon#about to read 3, iclass 7, count 0 2006.259.07:31:12.64#ibcon#read 3, iclass 7, count 0 2006.259.07:31:12.64#ibcon#about to read 4, iclass 7, count 0 2006.259.07:31:12.64#ibcon#read 4, iclass 7, count 0 2006.259.07:31:12.64#ibcon#about to read 5, iclass 7, count 0 2006.259.07:31:12.64#ibcon#read 5, iclass 7, count 0 2006.259.07:31:12.64#ibcon#about to read 6, iclass 7, count 0 2006.259.07:31:12.64#ibcon#read 6, iclass 7, count 0 2006.259.07:31:12.64#ibcon#end of sib2, iclass 7, count 0 2006.259.07:31:12.64#ibcon#*after write, iclass 7, count 0 2006.259.07:31:12.64#ibcon#*before return 0, iclass 7, count 0 2006.259.07:31:12.64#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.259.07:31:12.64#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.259.07:31:12.64#ibcon#about to clear, iclass 7 cls_cnt 0 2006.259.07:31:12.64#ibcon#cleared, iclass 7 cls_cnt 0 2006.259.07:31:12.64$vc4f8/vb=6,4 2006.259.07:31:12.64#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.259.07:31:12.64#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.259.07:31:12.64#ibcon#ireg 11 cls_cnt 2 2006.259.07:31:12.64#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.259.07:31:12.70#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.259.07:31:12.70#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.259.07:31:12.70#ibcon#enter wrdev, iclass 11, count 2 2006.259.07:31:12.70#ibcon#first serial, iclass 11, count 2 2006.259.07:31:12.70#ibcon#enter sib2, iclass 11, count 2 2006.259.07:31:12.70#ibcon#flushed, iclass 11, count 2 2006.259.07:31:12.70#ibcon#about to write, iclass 11, count 2 2006.259.07:31:12.70#ibcon#wrote, iclass 11, count 2 2006.259.07:31:12.70#ibcon#about to read 3, iclass 11, count 2 2006.259.07:31:12.72#ibcon#read 3, iclass 11, count 2 2006.259.07:31:12.72#ibcon#about to read 4, iclass 11, count 2 2006.259.07:31:12.72#ibcon#read 4, iclass 11, count 2 2006.259.07:31:12.72#ibcon#about to read 5, iclass 11, count 2 2006.259.07:31:12.72#ibcon#read 5, iclass 11, count 2 2006.259.07:31:12.72#ibcon#about to read 6, iclass 11, count 2 2006.259.07:31:12.72#ibcon#read 6, iclass 11, count 2 2006.259.07:31:12.72#ibcon#end of sib2, iclass 11, count 2 2006.259.07:31:12.72#ibcon#*mode == 0, iclass 11, count 2 2006.259.07:31:12.72#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.259.07:31:12.72#ibcon#[27=AT06-04\r\n] 2006.259.07:31:12.72#ibcon#*before write, iclass 11, count 2 2006.259.07:31:12.72#ibcon#enter sib2, iclass 11, count 2 2006.259.07:31:12.72#ibcon#flushed, iclass 11, count 2 2006.259.07:31:12.72#ibcon#about to write, iclass 11, count 2 2006.259.07:31:12.72#ibcon#wrote, iclass 11, count 2 2006.259.07:31:12.72#ibcon#about to read 3, iclass 11, count 2 2006.259.07:31:12.75#ibcon#read 3, iclass 11, count 2 2006.259.07:31:12.75#ibcon#about to read 4, iclass 11, count 2 2006.259.07:31:12.75#ibcon#read 4, iclass 11, count 2 2006.259.07:31:12.75#ibcon#about to read 5, iclass 11, count 2 2006.259.07:31:12.75#ibcon#read 5, iclass 11, count 2 2006.259.07:31:12.75#ibcon#about to read 6, iclass 11, count 2 2006.259.07:31:12.75#ibcon#read 6, iclass 11, count 2 2006.259.07:31:12.75#ibcon#end of sib2, iclass 11, count 2 2006.259.07:31:12.75#ibcon#*after write, iclass 11, count 2 2006.259.07:31:12.75#ibcon#*before return 0, iclass 11, count 2 2006.259.07:31:12.75#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.259.07:31:12.75#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.259.07:31:12.75#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.259.07:31:12.75#ibcon#ireg 7 cls_cnt 0 2006.259.07:31:12.75#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.259.07:31:12.87#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.259.07:31:12.87#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.259.07:31:12.87#ibcon#enter wrdev, iclass 11, count 0 2006.259.07:31:12.87#ibcon#first serial, iclass 11, count 0 2006.259.07:31:12.87#ibcon#enter sib2, iclass 11, count 0 2006.259.07:31:12.87#ibcon#flushed, iclass 11, count 0 2006.259.07:31:12.87#ibcon#about to write, iclass 11, count 0 2006.259.07:31:12.87#ibcon#wrote, iclass 11, count 0 2006.259.07:31:12.87#ibcon#about to read 3, iclass 11, count 0 2006.259.07:31:12.89#ibcon#read 3, iclass 11, count 0 2006.259.07:31:12.89#ibcon#about to read 4, iclass 11, count 0 2006.259.07:31:12.89#ibcon#read 4, iclass 11, count 0 2006.259.07:31:12.89#ibcon#about to read 5, iclass 11, count 0 2006.259.07:31:12.89#ibcon#read 5, iclass 11, count 0 2006.259.07:31:12.89#ibcon#about to read 6, iclass 11, count 0 2006.259.07:31:12.89#ibcon#read 6, iclass 11, count 0 2006.259.07:31:12.89#ibcon#end of sib2, iclass 11, count 0 2006.259.07:31:12.89#ibcon#*mode == 0, iclass 11, count 0 2006.259.07:31:12.89#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.259.07:31:12.89#ibcon#[27=USB\r\n] 2006.259.07:31:12.89#ibcon#*before write, iclass 11, count 0 2006.259.07:31:12.89#ibcon#enter sib2, iclass 11, count 0 2006.259.07:31:12.89#ibcon#flushed, iclass 11, count 0 2006.259.07:31:12.89#ibcon#about to write, iclass 11, count 0 2006.259.07:31:12.89#ibcon#wrote, iclass 11, count 0 2006.259.07:31:12.89#ibcon#about to read 3, iclass 11, count 0 2006.259.07:31:12.92#ibcon#read 3, iclass 11, count 0 2006.259.07:31:12.92#ibcon#about to read 4, iclass 11, count 0 2006.259.07:31:12.92#ibcon#read 4, iclass 11, count 0 2006.259.07:31:12.92#ibcon#about to read 5, iclass 11, count 0 2006.259.07:31:12.92#ibcon#read 5, iclass 11, count 0 2006.259.07:31:12.92#ibcon#about to read 6, iclass 11, count 0 2006.259.07:31:12.92#ibcon#read 6, iclass 11, count 0 2006.259.07:31:12.92#ibcon#end of sib2, iclass 11, count 0 2006.259.07:31:12.92#ibcon#*after write, iclass 11, count 0 2006.259.07:31:12.92#ibcon#*before return 0, iclass 11, count 0 2006.259.07:31:12.92#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.259.07:31:12.92#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.259.07:31:12.92#ibcon#about to clear, iclass 11 cls_cnt 0 2006.259.07:31:12.92#ibcon#cleared, iclass 11 cls_cnt 0 2006.259.07:31:12.92$vc4f8/vabw=wide 2006.259.07:31:12.92#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.259.07:31:12.92#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.259.07:31:12.92#ibcon#ireg 8 cls_cnt 0 2006.259.07:31:12.92#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.259.07:31:12.92#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.259.07:31:12.92#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.259.07:31:12.92#ibcon#enter wrdev, iclass 13, count 0 2006.259.07:31:12.92#ibcon#first serial, iclass 13, count 0 2006.259.07:31:12.92#ibcon#enter sib2, iclass 13, count 0 2006.259.07:31:12.92#ibcon#flushed, iclass 13, count 0 2006.259.07:31:12.92#ibcon#about to write, iclass 13, count 0 2006.259.07:31:12.92#ibcon#wrote, iclass 13, count 0 2006.259.07:31:12.92#ibcon#about to read 3, iclass 13, count 0 2006.259.07:31:12.94#ibcon#read 3, iclass 13, count 0 2006.259.07:31:12.94#ibcon#about to read 4, iclass 13, count 0 2006.259.07:31:12.94#ibcon#read 4, iclass 13, count 0 2006.259.07:31:12.94#ibcon#about to read 5, iclass 13, count 0 2006.259.07:31:12.94#ibcon#read 5, iclass 13, count 0 2006.259.07:31:12.94#ibcon#about to read 6, iclass 13, count 0 2006.259.07:31:12.94#ibcon#read 6, iclass 13, count 0 2006.259.07:31:12.94#ibcon#end of sib2, iclass 13, count 0 2006.259.07:31:12.94#ibcon#*mode == 0, iclass 13, count 0 2006.259.07:31:12.94#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.259.07:31:12.94#ibcon#[25=BW32\r\n] 2006.259.07:31:12.94#ibcon#*before write, iclass 13, count 0 2006.259.07:31:12.94#ibcon#enter sib2, iclass 13, count 0 2006.259.07:31:12.94#ibcon#flushed, iclass 13, count 0 2006.259.07:31:12.94#ibcon#about to write, iclass 13, count 0 2006.259.07:31:12.94#ibcon#wrote, iclass 13, count 0 2006.259.07:31:12.94#ibcon#about to read 3, iclass 13, count 0 2006.259.07:31:12.97#ibcon#read 3, iclass 13, count 0 2006.259.07:31:12.97#ibcon#about to read 4, iclass 13, count 0 2006.259.07:31:12.97#ibcon#read 4, iclass 13, count 0 2006.259.07:31:12.97#ibcon#about to read 5, iclass 13, count 0 2006.259.07:31:12.97#ibcon#read 5, iclass 13, count 0 2006.259.07:31:12.97#ibcon#about to read 6, iclass 13, count 0 2006.259.07:31:12.97#ibcon#read 6, iclass 13, count 0 2006.259.07:31:12.97#ibcon#end of sib2, iclass 13, count 0 2006.259.07:31:12.97#ibcon#*after write, iclass 13, count 0 2006.259.07:31:12.97#ibcon#*before return 0, iclass 13, count 0 2006.259.07:31:12.97#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.259.07:31:12.97#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.259.07:31:12.97#ibcon#about to clear, iclass 13 cls_cnt 0 2006.259.07:31:12.97#ibcon#cleared, iclass 13 cls_cnt 0 2006.259.07:31:12.97$vc4f8/vbbw=wide 2006.259.07:31:12.97#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.259.07:31:12.97#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.259.07:31:12.97#ibcon#ireg 8 cls_cnt 0 2006.259.07:31:12.97#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.259.07:31:13.04#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.259.07:31:13.04#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.259.07:31:13.04#ibcon#enter wrdev, iclass 15, count 0 2006.259.07:31:13.04#ibcon#first serial, iclass 15, count 0 2006.259.07:31:13.04#ibcon#enter sib2, iclass 15, count 0 2006.259.07:31:13.04#ibcon#flushed, iclass 15, count 0 2006.259.07:31:13.04#ibcon#about to write, iclass 15, count 0 2006.259.07:31:13.04#ibcon#wrote, iclass 15, count 0 2006.259.07:31:13.04#ibcon#about to read 3, iclass 15, count 0 2006.259.07:31:13.06#ibcon#read 3, iclass 15, count 0 2006.259.07:31:13.06#ibcon#about to read 4, iclass 15, count 0 2006.259.07:31:13.06#ibcon#read 4, iclass 15, count 0 2006.259.07:31:13.06#ibcon#about to read 5, iclass 15, count 0 2006.259.07:31:13.06#ibcon#read 5, iclass 15, count 0 2006.259.07:31:13.06#ibcon#about to read 6, iclass 15, count 0 2006.259.07:31:13.06#ibcon#read 6, iclass 15, count 0 2006.259.07:31:13.06#ibcon#end of sib2, iclass 15, count 0 2006.259.07:31:13.06#ibcon#*mode == 0, iclass 15, count 0 2006.259.07:31:13.06#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.259.07:31:13.06#ibcon#[27=BW32\r\n] 2006.259.07:31:13.06#ibcon#*before write, iclass 15, count 0 2006.259.07:31:13.06#ibcon#enter sib2, iclass 15, count 0 2006.259.07:31:13.06#ibcon#flushed, iclass 15, count 0 2006.259.07:31:13.06#ibcon#about to write, iclass 15, count 0 2006.259.07:31:13.06#ibcon#wrote, iclass 15, count 0 2006.259.07:31:13.06#ibcon#about to read 3, iclass 15, count 0 2006.259.07:31:13.09#ibcon#read 3, iclass 15, count 0 2006.259.07:31:13.09#ibcon#about to read 4, iclass 15, count 0 2006.259.07:31:13.09#ibcon#read 4, iclass 15, count 0 2006.259.07:31:13.09#ibcon#about to read 5, iclass 15, count 0 2006.259.07:31:13.09#ibcon#read 5, iclass 15, count 0 2006.259.07:31:13.09#ibcon#about to read 6, iclass 15, count 0 2006.259.07:31:13.09#ibcon#read 6, iclass 15, count 0 2006.259.07:31:13.09#ibcon#end of sib2, iclass 15, count 0 2006.259.07:31:13.09#ibcon#*after write, iclass 15, count 0 2006.259.07:31:13.09#ibcon#*before return 0, iclass 15, count 0 2006.259.07:31:13.09#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.259.07:31:13.09#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.259.07:31:13.09#ibcon#about to clear, iclass 15 cls_cnt 0 2006.259.07:31:13.09#ibcon#cleared, iclass 15 cls_cnt 0 2006.259.07:31:13.09$4f8m12a/ifd4f 2006.259.07:31:13.09$ifd4f/lo= 2006.259.07:31:13.09$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.259.07:31:13.09$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.259.07:31:13.09$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.259.07:31:13.09$ifd4f/patch= 2006.259.07:31:13.09$ifd4f/patch=lo1,a1,a2,a3,a4 2006.259.07:31:13.09$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.259.07:31:13.09$ifd4f/patch=lo3,a5,a6,a7,a8 2006.259.07:31:13.09$4f8m12a/"form=m,16.000,1:2 2006.259.07:31:13.09$4f8m12a/"tpicd 2006.259.07:31:13.09$4f8m12a/echo=off 2006.259.07:31:13.09$4f8m12a/xlog=off 2006.259.07:31:13.09:!2006.259.07:33:20 2006.259.07:31:38.13#trakl#Source acquired 2006.259.07:31:39.13#flagr#flagr/antenna,acquired 2006.259.07:33:20.00:preob 2006.259.07:33:20.14/onsource/TRACKING 2006.259.07:33:20.14:!2006.259.07:33:30 2006.259.07:33:30.00:data_valid=on 2006.259.07:33:30.00:midob 2006.259.07:33:30.14/onsource/TRACKING 2006.259.07:33:30.14/wx/22.37,1012.8,84 2006.259.07:33:30.28/cable/+6.4574E-03 2006.259.07:33:31.37/va/01,08,usb,yes,34,35 2006.259.07:33:31.37/va/02,07,usb,yes,34,35 2006.259.07:33:31.37/va/03,08,usb,yes,26,26 2006.259.07:33:31.37/va/04,07,usb,yes,35,38 2006.259.07:33:31.37/va/05,07,usb,yes,39,41 2006.259.07:33:31.37/va/06,06,usb,yes,38,38 2006.259.07:33:31.37/va/07,06,usb,yes,39,38 2006.259.07:33:31.37/va/08,06,usb,yes,41,41 2006.259.07:33:31.60/valo/01,532.99,yes,locked 2006.259.07:33:31.60/valo/02,572.99,yes,locked 2006.259.07:33:31.60/valo/03,672.99,yes,locked 2006.259.07:33:31.60/valo/04,832.99,yes,locked 2006.259.07:33:31.60/valo/05,652.99,yes,locked 2006.259.07:33:31.60/valo/06,772.99,yes,locked 2006.259.07:33:31.60/valo/07,832.99,yes,locked 2006.259.07:33:31.60/valo/08,852.99,yes,locked 2006.259.07:33:32.69/vb/01,04,usb,yes,32,35 2006.259.07:33:32.69/vb/02,05,usb,yes,30,34 2006.259.07:33:32.69/vb/03,04,usb,yes,30,35 2006.259.07:33:32.69/vb/04,05,usb,yes,28,28 2006.259.07:33:32.69/vb/05,04,usb,yes,30,34 2006.259.07:33:32.69/vb/06,04,usb,yes,31,34 2006.259.07:33:32.69/vb/07,04,usb,yes,33,33 2006.259.07:33:32.69/vb/08,04,usb,yes,30,34 2006.259.07:33:32.93/vblo/01,632.99,yes,locked 2006.259.07:33:32.93/vblo/02,640.99,yes,locked 2006.259.07:33:32.93/vblo/03,656.99,yes,locked 2006.259.07:33:32.93/vblo/04,712.99,yes,locked 2006.259.07:33:32.93/vblo/05,744.99,yes,locked 2006.259.07:33:32.93/vblo/06,752.99,yes,locked 2006.259.07:33:32.93/vblo/07,734.99,yes,locked 2006.259.07:33:32.93/vblo/08,744.99,yes,locked 2006.259.07:33:33.08/vabw/8 2006.259.07:33:33.23/vbbw/8 2006.259.07:33:33.32/xfe/off,on,15.2 2006.259.07:33:33.69/ifatt/23,28,28,28 2006.259.07:33:34.07/fmout-gps/S +4.50E-07 2006.259.07:33:34.11:!2006.259.07:34:30 2006.259.07:34:30.01:data_valid=off 2006.259.07:34:30.01:postob 2006.259.07:34:30.20/cable/+6.4581E-03 2006.259.07:34:30.20/wx/22.35,1012.8,84 2006.259.07:34:31.08/fmout-gps/S +4.50E-07 2006.259.07:34:31.08:scan_name=259-0735,k06259,60 2006.259.07:34:31.09:source=1357+769,135755.37,764321.1,2000.0,ccw 2006.259.07:34:31.14#flagr#flagr/antenna,new-source 2006.259.07:34:32.14:checkk5 2006.259.07:34:32.54/chk_autoobs//k5ts1/ autoobs is running! 2006.259.07:34:32.95/chk_autoobs//k5ts2/ autoobs is running! 2006.259.07:34:33.41/chk_autoobs//k5ts3/ autoobs is running! 2006.259.07:34:33.82/chk_autoobs//k5ts4/ autoobs is running! 2006.259.07:34:34.24/chk_obsdata//k5ts1/T2590733??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.259.07:34:34.64/chk_obsdata//k5ts2/T2590733??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.259.07:34:35.08/chk_obsdata//k5ts3/T2590733??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.259.07:34:35.48/chk_obsdata//k5ts4/T2590733??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.259.07:34:36.23/k5log//k5ts1_log_newline 2006.259.07:34:36.96/k5log//k5ts2_log_newline 2006.259.07:34:37.71/k5log//k5ts3_log_newline 2006.259.07:34:38.58/k5log//k5ts4_log_newline 2006.259.07:34:38.61/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.259.07:34:38.61:4f8m12a=1 2006.259.07:34:38.61$4f8m12a/echo=on 2006.259.07:34:38.61$4f8m12a/pcalon 2006.259.07:34:38.61$pcalon/"no phase cal control is implemented here 2006.259.07:34:38.61$4f8m12a/"tpicd=stop 2006.259.07:34:38.61$4f8m12a/vc4f8 2006.259.07:34:38.61$vc4f8/valo=1,532.99 2006.259.07:34:38.61#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.259.07:34:38.61#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.259.07:34:38.61#ibcon#ireg 17 cls_cnt 0 2006.259.07:34:38.61#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.259.07:34:38.61#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.259.07:34:38.61#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.259.07:34:38.61#ibcon#enter wrdev, iclass 26, count 0 2006.259.07:34:38.61#ibcon#first serial, iclass 26, count 0 2006.259.07:34:38.61#ibcon#enter sib2, iclass 26, count 0 2006.259.07:34:38.61#ibcon#flushed, iclass 26, count 0 2006.259.07:34:38.61#ibcon#about to write, iclass 26, count 0 2006.259.07:34:38.61#ibcon#wrote, iclass 26, count 0 2006.259.07:34:38.61#ibcon#about to read 3, iclass 26, count 0 2006.259.07:34:38.66#ibcon#read 3, iclass 26, count 0 2006.259.07:34:38.66#ibcon#about to read 4, iclass 26, count 0 2006.259.07:34:38.66#ibcon#read 4, iclass 26, count 0 2006.259.07:34:38.66#ibcon#about to read 5, iclass 26, count 0 2006.259.07:34:38.66#ibcon#read 5, iclass 26, count 0 2006.259.07:34:38.66#ibcon#about to read 6, iclass 26, count 0 2006.259.07:34:38.66#ibcon#read 6, iclass 26, count 0 2006.259.07:34:38.66#ibcon#end of sib2, iclass 26, count 0 2006.259.07:34:38.66#ibcon#*mode == 0, iclass 26, count 0 2006.259.07:34:38.66#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.259.07:34:38.66#ibcon#[26=FRQ=01,532.99\r\n] 2006.259.07:34:38.66#ibcon#*before write, iclass 26, count 0 2006.259.07:34:38.66#ibcon#enter sib2, iclass 26, count 0 2006.259.07:34:38.66#ibcon#flushed, iclass 26, count 0 2006.259.07:34:38.66#ibcon#about to write, iclass 26, count 0 2006.259.07:34:38.66#ibcon#wrote, iclass 26, count 0 2006.259.07:34:38.66#ibcon#about to read 3, iclass 26, count 0 2006.259.07:34:38.70#ibcon#read 3, iclass 26, count 0 2006.259.07:34:38.70#ibcon#about to read 4, iclass 26, count 0 2006.259.07:34:38.70#ibcon#read 4, iclass 26, count 0 2006.259.07:34:38.70#ibcon#about to read 5, iclass 26, count 0 2006.259.07:34:38.70#ibcon#read 5, iclass 26, count 0 2006.259.07:34:38.70#ibcon#about to read 6, iclass 26, count 0 2006.259.07:34:38.70#ibcon#read 6, iclass 26, count 0 2006.259.07:34:38.70#ibcon#end of sib2, iclass 26, count 0 2006.259.07:34:38.70#ibcon#*after write, iclass 26, count 0 2006.259.07:34:38.70#ibcon#*before return 0, iclass 26, count 0 2006.259.07:34:38.70#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.259.07:34:38.70#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.259.07:34:38.70#ibcon#about to clear, iclass 26 cls_cnt 0 2006.259.07:34:38.70#ibcon#cleared, iclass 26 cls_cnt 0 2006.259.07:34:38.70$vc4f8/va=1,8 2006.259.07:34:38.70#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.259.07:34:38.70#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.259.07:34:38.70#ibcon#ireg 11 cls_cnt 2 2006.259.07:34:38.70#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.259.07:34:38.70#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.259.07:34:38.70#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.259.07:34:38.70#ibcon#enter wrdev, iclass 28, count 2 2006.259.07:34:38.70#ibcon#first serial, iclass 28, count 2 2006.259.07:34:38.70#ibcon#enter sib2, iclass 28, count 2 2006.259.07:34:38.70#ibcon#flushed, iclass 28, count 2 2006.259.07:34:38.70#ibcon#about to write, iclass 28, count 2 2006.259.07:34:38.70#ibcon#wrote, iclass 28, count 2 2006.259.07:34:38.70#ibcon#about to read 3, iclass 28, count 2 2006.259.07:34:38.72#ibcon#read 3, iclass 28, count 2 2006.259.07:34:38.72#ibcon#about to read 4, iclass 28, count 2 2006.259.07:34:38.72#ibcon#read 4, iclass 28, count 2 2006.259.07:34:38.72#ibcon#about to read 5, iclass 28, count 2 2006.259.07:34:38.72#ibcon#read 5, iclass 28, count 2 2006.259.07:34:38.72#ibcon#about to read 6, iclass 28, count 2 2006.259.07:34:38.72#ibcon#read 6, iclass 28, count 2 2006.259.07:34:38.72#ibcon#end of sib2, iclass 28, count 2 2006.259.07:34:38.72#ibcon#*mode == 0, iclass 28, count 2 2006.259.07:34:38.72#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.259.07:34:38.72#ibcon#[25=AT01-08\r\n] 2006.259.07:34:38.72#ibcon#*before write, iclass 28, count 2 2006.259.07:34:38.72#ibcon#enter sib2, iclass 28, count 2 2006.259.07:34:38.72#ibcon#flushed, iclass 28, count 2 2006.259.07:34:38.72#ibcon#about to write, iclass 28, count 2 2006.259.07:34:38.72#ibcon#wrote, iclass 28, count 2 2006.259.07:34:38.72#ibcon#about to read 3, iclass 28, count 2 2006.259.07:34:38.75#ibcon#read 3, iclass 28, count 2 2006.259.07:34:38.75#ibcon#about to read 4, iclass 28, count 2 2006.259.07:34:38.75#ibcon#read 4, iclass 28, count 2 2006.259.07:34:38.75#ibcon#about to read 5, iclass 28, count 2 2006.259.07:34:38.75#ibcon#read 5, iclass 28, count 2 2006.259.07:34:38.75#ibcon#about to read 6, iclass 28, count 2 2006.259.07:34:38.75#ibcon#read 6, iclass 28, count 2 2006.259.07:34:38.75#ibcon#end of sib2, iclass 28, count 2 2006.259.07:34:38.75#ibcon#*after write, iclass 28, count 2 2006.259.07:34:38.75#ibcon#*before return 0, iclass 28, count 2 2006.259.07:34:38.75#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.259.07:34:38.75#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.259.07:34:38.75#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.259.07:34:38.75#ibcon#ireg 7 cls_cnt 0 2006.259.07:34:38.75#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.259.07:34:38.87#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.259.07:34:38.87#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.259.07:34:38.87#ibcon#enter wrdev, iclass 28, count 0 2006.259.07:34:38.87#ibcon#first serial, iclass 28, count 0 2006.259.07:34:38.87#ibcon#enter sib2, iclass 28, count 0 2006.259.07:34:38.87#ibcon#flushed, iclass 28, count 0 2006.259.07:34:38.87#ibcon#about to write, iclass 28, count 0 2006.259.07:34:38.87#ibcon#wrote, iclass 28, count 0 2006.259.07:34:38.87#ibcon#about to read 3, iclass 28, count 0 2006.259.07:34:38.89#ibcon#read 3, iclass 28, count 0 2006.259.07:34:38.89#ibcon#about to read 4, iclass 28, count 0 2006.259.07:34:38.89#ibcon#read 4, iclass 28, count 0 2006.259.07:34:38.89#ibcon#about to read 5, iclass 28, count 0 2006.259.07:34:38.89#ibcon#read 5, iclass 28, count 0 2006.259.07:34:38.89#ibcon#about to read 6, iclass 28, count 0 2006.259.07:34:38.89#ibcon#read 6, iclass 28, count 0 2006.259.07:34:38.89#ibcon#end of sib2, iclass 28, count 0 2006.259.07:34:38.89#ibcon#*mode == 0, iclass 28, count 0 2006.259.07:34:38.89#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.259.07:34:38.89#ibcon#[25=USB\r\n] 2006.259.07:34:38.89#ibcon#*before write, iclass 28, count 0 2006.259.07:34:38.89#ibcon#enter sib2, iclass 28, count 0 2006.259.07:34:38.89#ibcon#flushed, iclass 28, count 0 2006.259.07:34:38.89#ibcon#about to write, iclass 28, count 0 2006.259.07:34:38.89#ibcon#wrote, iclass 28, count 0 2006.259.07:34:38.89#ibcon#about to read 3, iclass 28, count 0 2006.259.07:34:38.92#ibcon#read 3, iclass 28, count 0 2006.259.07:34:38.92#ibcon#about to read 4, iclass 28, count 0 2006.259.07:34:38.92#ibcon#read 4, iclass 28, count 0 2006.259.07:34:38.92#ibcon#about to read 5, iclass 28, count 0 2006.259.07:34:38.92#ibcon#read 5, iclass 28, count 0 2006.259.07:34:38.92#ibcon#about to read 6, iclass 28, count 0 2006.259.07:34:38.92#ibcon#read 6, iclass 28, count 0 2006.259.07:34:38.92#ibcon#end of sib2, iclass 28, count 0 2006.259.07:34:38.92#ibcon#*after write, iclass 28, count 0 2006.259.07:34:38.92#ibcon#*before return 0, iclass 28, count 0 2006.259.07:34:38.92#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.259.07:34:38.92#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.259.07:34:38.92#ibcon#about to clear, iclass 28 cls_cnt 0 2006.259.07:34:38.92#ibcon#cleared, iclass 28 cls_cnt 0 2006.259.07:34:38.92$vc4f8/valo=2,572.99 2006.259.07:34:38.92#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.259.07:34:38.92#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.259.07:34:38.92#ibcon#ireg 17 cls_cnt 0 2006.259.07:34:38.92#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.259.07:34:38.92#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.259.07:34:38.92#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.259.07:34:38.92#ibcon#enter wrdev, iclass 30, count 0 2006.259.07:34:38.92#ibcon#first serial, iclass 30, count 0 2006.259.07:34:38.92#ibcon#enter sib2, iclass 30, count 0 2006.259.07:34:38.92#ibcon#flushed, iclass 30, count 0 2006.259.07:34:38.92#ibcon#about to write, iclass 30, count 0 2006.259.07:34:38.92#ibcon#wrote, iclass 30, count 0 2006.259.07:34:38.92#ibcon#about to read 3, iclass 30, count 0 2006.259.07:34:38.94#ibcon#read 3, iclass 30, count 0 2006.259.07:34:38.94#ibcon#about to read 4, iclass 30, count 0 2006.259.07:34:38.94#ibcon#read 4, iclass 30, count 0 2006.259.07:34:38.94#ibcon#about to read 5, iclass 30, count 0 2006.259.07:34:38.94#ibcon#read 5, iclass 30, count 0 2006.259.07:34:38.94#ibcon#about to read 6, iclass 30, count 0 2006.259.07:34:38.94#ibcon#read 6, iclass 30, count 0 2006.259.07:34:38.94#ibcon#end of sib2, iclass 30, count 0 2006.259.07:34:38.94#ibcon#*mode == 0, iclass 30, count 0 2006.259.07:34:38.94#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.259.07:34:38.94#ibcon#[26=FRQ=02,572.99\r\n] 2006.259.07:34:38.94#ibcon#*before write, iclass 30, count 0 2006.259.07:34:38.94#ibcon#enter sib2, iclass 30, count 0 2006.259.07:34:38.94#ibcon#flushed, iclass 30, count 0 2006.259.07:34:38.94#ibcon#about to write, iclass 30, count 0 2006.259.07:34:38.94#ibcon#wrote, iclass 30, count 0 2006.259.07:34:38.94#ibcon#about to read 3, iclass 30, count 0 2006.259.07:34:38.97#abcon#<5=/04 3.1 5.8 22.35 841012.8\r\n> 2006.259.07:34:38.98#ibcon#read 3, iclass 30, count 0 2006.259.07:34:38.98#ibcon#about to read 4, iclass 30, count 0 2006.259.07:34:38.98#ibcon#read 4, iclass 30, count 0 2006.259.07:34:38.98#ibcon#about to read 5, iclass 30, count 0 2006.259.07:34:38.98#ibcon#read 5, iclass 30, count 0 2006.259.07:34:38.98#ibcon#about to read 6, iclass 30, count 0 2006.259.07:34:38.98#ibcon#read 6, iclass 30, count 0 2006.259.07:34:38.98#ibcon#end of sib2, iclass 30, count 0 2006.259.07:34:38.98#ibcon#*after write, iclass 30, count 0 2006.259.07:34:38.98#ibcon#*before return 0, iclass 30, count 0 2006.259.07:34:38.98#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.259.07:34:38.98#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.259.07:34:38.98#ibcon#about to clear, iclass 30 cls_cnt 0 2006.259.07:34:38.98#ibcon#cleared, iclass 30 cls_cnt 0 2006.259.07:34:38.98$vc4f8/va=2,7 2006.259.07:34:38.98#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.259.07:34:38.98#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.259.07:34:38.98#ibcon#ireg 11 cls_cnt 2 2006.259.07:34:38.98#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.259.07:34:38.99#abcon#{5=INTERFACE CLEAR} 2006.259.07:34:39.04#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.259.07:34:39.04#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.259.07:34:39.04#ibcon#enter wrdev, iclass 35, count 2 2006.259.07:34:39.04#ibcon#first serial, iclass 35, count 2 2006.259.07:34:39.04#ibcon#enter sib2, iclass 35, count 2 2006.259.07:34:39.04#ibcon#flushed, iclass 35, count 2 2006.259.07:34:39.04#ibcon#about to write, iclass 35, count 2 2006.259.07:34:39.04#ibcon#wrote, iclass 35, count 2 2006.259.07:34:39.04#ibcon#about to read 3, iclass 35, count 2 2006.259.07:34:39.05#abcon#[5=S1D000X0/0*\r\n] 2006.259.07:34:39.06#ibcon#read 3, iclass 35, count 2 2006.259.07:34:39.06#ibcon#about to read 4, iclass 35, count 2 2006.259.07:34:39.06#ibcon#read 4, iclass 35, count 2 2006.259.07:34:39.06#ibcon#about to read 5, iclass 35, count 2 2006.259.07:34:39.06#ibcon#read 5, iclass 35, count 2 2006.259.07:34:39.06#ibcon#about to read 6, iclass 35, count 2 2006.259.07:34:39.06#ibcon#read 6, iclass 35, count 2 2006.259.07:34:39.06#ibcon#end of sib2, iclass 35, count 2 2006.259.07:34:39.06#ibcon#*mode == 0, iclass 35, count 2 2006.259.07:34:39.06#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.259.07:34:39.06#ibcon#[25=AT02-07\r\n] 2006.259.07:34:39.06#ibcon#*before write, iclass 35, count 2 2006.259.07:34:39.06#ibcon#enter sib2, iclass 35, count 2 2006.259.07:34:39.06#ibcon#flushed, iclass 35, count 2 2006.259.07:34:39.06#ibcon#about to write, iclass 35, count 2 2006.259.07:34:39.06#ibcon#wrote, iclass 35, count 2 2006.259.07:34:39.06#ibcon#about to read 3, iclass 35, count 2 2006.259.07:34:39.09#ibcon#read 3, iclass 35, count 2 2006.259.07:34:39.09#ibcon#about to read 4, iclass 35, count 2 2006.259.07:34:39.09#ibcon#read 4, iclass 35, count 2 2006.259.07:34:39.09#ibcon#about to read 5, iclass 35, count 2 2006.259.07:34:39.09#ibcon#read 5, iclass 35, count 2 2006.259.07:34:39.09#ibcon#about to read 6, iclass 35, count 2 2006.259.07:34:39.09#ibcon#read 6, iclass 35, count 2 2006.259.07:34:39.09#ibcon#end of sib2, iclass 35, count 2 2006.259.07:34:39.09#ibcon#*after write, iclass 35, count 2 2006.259.07:34:39.09#ibcon#*before return 0, iclass 35, count 2 2006.259.07:34:39.09#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.259.07:34:39.09#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.259.07:34:39.09#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.259.07:34:39.09#ibcon#ireg 7 cls_cnt 0 2006.259.07:34:39.09#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.259.07:34:39.21#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.259.07:34:39.21#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.259.07:34:39.21#ibcon#enter wrdev, iclass 35, count 0 2006.259.07:34:39.21#ibcon#first serial, iclass 35, count 0 2006.259.07:34:39.21#ibcon#enter sib2, iclass 35, count 0 2006.259.07:34:39.21#ibcon#flushed, iclass 35, count 0 2006.259.07:34:39.21#ibcon#about to write, iclass 35, count 0 2006.259.07:34:39.21#ibcon#wrote, iclass 35, count 0 2006.259.07:34:39.21#ibcon#about to read 3, iclass 35, count 0 2006.259.07:34:39.23#ibcon#read 3, iclass 35, count 0 2006.259.07:34:39.23#ibcon#about to read 4, iclass 35, count 0 2006.259.07:34:39.23#ibcon#read 4, iclass 35, count 0 2006.259.07:34:39.23#ibcon#about to read 5, iclass 35, count 0 2006.259.07:34:39.23#ibcon#read 5, iclass 35, count 0 2006.259.07:34:39.23#ibcon#about to read 6, iclass 35, count 0 2006.259.07:34:39.23#ibcon#read 6, iclass 35, count 0 2006.259.07:34:39.23#ibcon#end of sib2, iclass 35, count 0 2006.259.07:34:39.23#ibcon#*mode == 0, iclass 35, count 0 2006.259.07:34:39.23#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.259.07:34:39.23#ibcon#[25=USB\r\n] 2006.259.07:34:39.23#ibcon#*before write, iclass 35, count 0 2006.259.07:34:39.23#ibcon#enter sib2, iclass 35, count 0 2006.259.07:34:39.23#ibcon#flushed, iclass 35, count 0 2006.259.07:34:39.23#ibcon#about to write, iclass 35, count 0 2006.259.07:34:39.23#ibcon#wrote, iclass 35, count 0 2006.259.07:34:39.23#ibcon#about to read 3, iclass 35, count 0 2006.259.07:34:39.26#ibcon#read 3, iclass 35, count 0 2006.259.07:34:39.26#ibcon#about to read 4, iclass 35, count 0 2006.259.07:34:39.26#ibcon#read 4, iclass 35, count 0 2006.259.07:34:39.26#ibcon#about to read 5, iclass 35, count 0 2006.259.07:34:39.26#ibcon#read 5, iclass 35, count 0 2006.259.07:34:39.26#ibcon#about to read 6, iclass 35, count 0 2006.259.07:34:39.26#ibcon#read 6, iclass 35, count 0 2006.259.07:34:39.26#ibcon#end of sib2, iclass 35, count 0 2006.259.07:34:39.26#ibcon#*after write, iclass 35, count 0 2006.259.07:34:39.26#ibcon#*before return 0, iclass 35, count 0 2006.259.07:34:39.26#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.259.07:34:39.26#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.259.07:34:39.26#ibcon#about to clear, iclass 35 cls_cnt 0 2006.259.07:34:39.26#ibcon#cleared, iclass 35 cls_cnt 0 2006.259.07:34:39.26$vc4f8/valo=3,672.99 2006.259.07:34:39.26#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.259.07:34:39.26#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.259.07:34:39.26#ibcon#ireg 17 cls_cnt 0 2006.259.07:34:39.26#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.259.07:34:39.26#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.259.07:34:39.26#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.259.07:34:39.26#ibcon#enter wrdev, iclass 38, count 0 2006.259.07:34:39.26#ibcon#first serial, iclass 38, count 0 2006.259.07:34:39.26#ibcon#enter sib2, iclass 38, count 0 2006.259.07:34:39.26#ibcon#flushed, iclass 38, count 0 2006.259.07:34:39.26#ibcon#about to write, iclass 38, count 0 2006.259.07:34:39.26#ibcon#wrote, iclass 38, count 0 2006.259.07:34:39.26#ibcon#about to read 3, iclass 38, count 0 2006.259.07:34:39.28#ibcon#read 3, iclass 38, count 0 2006.259.07:34:39.28#ibcon#about to read 4, iclass 38, count 0 2006.259.07:34:39.28#ibcon#read 4, iclass 38, count 0 2006.259.07:34:39.28#ibcon#about to read 5, iclass 38, count 0 2006.259.07:34:39.28#ibcon#read 5, iclass 38, count 0 2006.259.07:34:39.28#ibcon#about to read 6, iclass 38, count 0 2006.259.07:34:39.28#ibcon#read 6, iclass 38, count 0 2006.259.07:34:39.28#ibcon#end of sib2, iclass 38, count 0 2006.259.07:34:39.28#ibcon#*mode == 0, iclass 38, count 0 2006.259.07:34:39.28#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.259.07:34:39.28#ibcon#[26=FRQ=03,672.99\r\n] 2006.259.07:34:39.28#ibcon#*before write, iclass 38, count 0 2006.259.07:34:39.28#ibcon#enter sib2, iclass 38, count 0 2006.259.07:34:39.28#ibcon#flushed, iclass 38, count 0 2006.259.07:34:39.28#ibcon#about to write, iclass 38, count 0 2006.259.07:34:39.28#ibcon#wrote, iclass 38, count 0 2006.259.07:34:39.28#ibcon#about to read 3, iclass 38, count 0 2006.259.07:34:39.32#ibcon#read 3, iclass 38, count 0 2006.259.07:34:39.32#ibcon#about to read 4, iclass 38, count 0 2006.259.07:34:39.32#ibcon#read 4, iclass 38, count 0 2006.259.07:34:39.32#ibcon#about to read 5, iclass 38, count 0 2006.259.07:34:39.32#ibcon#read 5, iclass 38, count 0 2006.259.07:34:39.32#ibcon#about to read 6, iclass 38, count 0 2006.259.07:34:39.32#ibcon#read 6, iclass 38, count 0 2006.259.07:34:39.32#ibcon#end of sib2, iclass 38, count 0 2006.259.07:34:39.32#ibcon#*after write, iclass 38, count 0 2006.259.07:34:39.32#ibcon#*before return 0, iclass 38, count 0 2006.259.07:34:39.32#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.259.07:34:39.32#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.259.07:34:39.32#ibcon#about to clear, iclass 38 cls_cnt 0 2006.259.07:34:39.32#ibcon#cleared, iclass 38 cls_cnt 0 2006.259.07:34:39.32$vc4f8/va=3,8 2006.259.07:34:39.32#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.259.07:34:39.32#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.259.07:34:39.32#ibcon#ireg 11 cls_cnt 2 2006.259.07:34:39.32#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.259.07:34:39.39#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.259.07:34:39.39#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.259.07:34:39.39#ibcon#enter wrdev, iclass 40, count 2 2006.259.07:34:39.39#ibcon#first serial, iclass 40, count 2 2006.259.07:34:39.39#ibcon#enter sib2, iclass 40, count 2 2006.259.07:34:39.39#ibcon#flushed, iclass 40, count 2 2006.259.07:34:39.39#ibcon#about to write, iclass 40, count 2 2006.259.07:34:39.39#ibcon#wrote, iclass 40, count 2 2006.259.07:34:39.39#ibcon#about to read 3, iclass 40, count 2 2006.259.07:34:39.40#ibcon#read 3, iclass 40, count 2 2006.259.07:34:39.40#ibcon#about to read 4, iclass 40, count 2 2006.259.07:34:39.40#ibcon#read 4, iclass 40, count 2 2006.259.07:34:39.40#ibcon#about to read 5, iclass 40, count 2 2006.259.07:34:39.40#ibcon#read 5, iclass 40, count 2 2006.259.07:34:39.40#ibcon#about to read 6, iclass 40, count 2 2006.259.07:34:39.40#ibcon#read 6, iclass 40, count 2 2006.259.07:34:39.40#ibcon#end of sib2, iclass 40, count 2 2006.259.07:34:39.40#ibcon#*mode == 0, iclass 40, count 2 2006.259.07:34:39.40#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.259.07:34:39.40#ibcon#[25=AT03-08\r\n] 2006.259.07:34:39.40#ibcon#*before write, iclass 40, count 2 2006.259.07:34:39.40#ibcon#enter sib2, iclass 40, count 2 2006.259.07:34:39.40#ibcon#flushed, iclass 40, count 2 2006.259.07:34:39.40#ibcon#about to write, iclass 40, count 2 2006.259.07:34:39.40#ibcon#wrote, iclass 40, count 2 2006.259.07:34:39.40#ibcon#about to read 3, iclass 40, count 2 2006.259.07:34:39.43#ibcon#read 3, iclass 40, count 2 2006.259.07:34:39.43#ibcon#about to read 4, iclass 40, count 2 2006.259.07:34:39.43#ibcon#read 4, iclass 40, count 2 2006.259.07:34:39.43#ibcon#about to read 5, iclass 40, count 2 2006.259.07:34:39.43#ibcon#read 5, iclass 40, count 2 2006.259.07:34:39.43#ibcon#about to read 6, iclass 40, count 2 2006.259.07:34:39.43#ibcon#read 6, iclass 40, count 2 2006.259.07:34:39.43#ibcon#end of sib2, iclass 40, count 2 2006.259.07:34:39.43#ibcon#*after write, iclass 40, count 2 2006.259.07:34:39.43#ibcon#*before return 0, iclass 40, count 2 2006.259.07:34:39.43#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.259.07:34:39.43#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.259.07:34:39.43#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.259.07:34:39.43#ibcon#ireg 7 cls_cnt 0 2006.259.07:34:39.43#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.259.07:34:39.55#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.259.07:34:39.55#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.259.07:34:39.55#ibcon#enter wrdev, iclass 40, count 0 2006.259.07:34:39.55#ibcon#first serial, iclass 40, count 0 2006.259.07:34:39.55#ibcon#enter sib2, iclass 40, count 0 2006.259.07:34:39.55#ibcon#flushed, iclass 40, count 0 2006.259.07:34:39.55#ibcon#about to write, iclass 40, count 0 2006.259.07:34:39.55#ibcon#wrote, iclass 40, count 0 2006.259.07:34:39.55#ibcon#about to read 3, iclass 40, count 0 2006.259.07:34:39.57#ibcon#read 3, iclass 40, count 0 2006.259.07:34:39.57#ibcon#about to read 4, iclass 40, count 0 2006.259.07:34:39.57#ibcon#read 4, iclass 40, count 0 2006.259.07:34:39.57#ibcon#about to read 5, iclass 40, count 0 2006.259.07:34:39.57#ibcon#read 5, iclass 40, count 0 2006.259.07:34:39.57#ibcon#about to read 6, iclass 40, count 0 2006.259.07:34:39.57#ibcon#read 6, iclass 40, count 0 2006.259.07:34:39.57#ibcon#end of sib2, iclass 40, count 0 2006.259.07:34:39.57#ibcon#*mode == 0, iclass 40, count 0 2006.259.07:34:39.57#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.259.07:34:39.57#ibcon#[25=USB\r\n] 2006.259.07:34:39.57#ibcon#*before write, iclass 40, count 0 2006.259.07:34:39.57#ibcon#enter sib2, iclass 40, count 0 2006.259.07:34:39.57#ibcon#flushed, iclass 40, count 0 2006.259.07:34:39.57#ibcon#about to write, iclass 40, count 0 2006.259.07:34:39.57#ibcon#wrote, iclass 40, count 0 2006.259.07:34:39.57#ibcon#about to read 3, iclass 40, count 0 2006.259.07:34:39.60#ibcon#read 3, iclass 40, count 0 2006.259.07:34:39.60#ibcon#about to read 4, iclass 40, count 0 2006.259.07:34:39.60#ibcon#read 4, iclass 40, count 0 2006.259.07:34:39.60#ibcon#about to read 5, iclass 40, count 0 2006.259.07:34:39.60#ibcon#read 5, iclass 40, count 0 2006.259.07:34:39.60#ibcon#about to read 6, iclass 40, count 0 2006.259.07:34:39.60#ibcon#read 6, iclass 40, count 0 2006.259.07:34:39.60#ibcon#end of sib2, iclass 40, count 0 2006.259.07:34:39.60#ibcon#*after write, iclass 40, count 0 2006.259.07:34:39.60#ibcon#*before return 0, iclass 40, count 0 2006.259.07:34:39.60#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.259.07:34:39.60#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.259.07:34:39.60#ibcon#about to clear, iclass 40 cls_cnt 0 2006.259.07:34:39.60#ibcon#cleared, iclass 40 cls_cnt 0 2006.259.07:34:39.60$vc4f8/valo=4,832.99 2006.259.07:34:39.60#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.259.07:34:39.60#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.259.07:34:39.60#ibcon#ireg 17 cls_cnt 0 2006.259.07:34:39.60#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.259.07:34:39.60#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.259.07:34:39.60#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.259.07:34:39.60#ibcon#enter wrdev, iclass 4, count 0 2006.259.07:34:39.60#ibcon#first serial, iclass 4, count 0 2006.259.07:34:39.60#ibcon#enter sib2, iclass 4, count 0 2006.259.07:34:39.60#ibcon#flushed, iclass 4, count 0 2006.259.07:34:39.60#ibcon#about to write, iclass 4, count 0 2006.259.07:34:39.60#ibcon#wrote, iclass 4, count 0 2006.259.07:34:39.60#ibcon#about to read 3, iclass 4, count 0 2006.259.07:34:39.62#ibcon#read 3, iclass 4, count 0 2006.259.07:34:39.62#ibcon#about to read 4, iclass 4, count 0 2006.259.07:34:39.62#ibcon#read 4, iclass 4, count 0 2006.259.07:34:39.62#ibcon#about to read 5, iclass 4, count 0 2006.259.07:34:39.62#ibcon#read 5, iclass 4, count 0 2006.259.07:34:39.62#ibcon#about to read 6, iclass 4, count 0 2006.259.07:34:39.62#ibcon#read 6, iclass 4, count 0 2006.259.07:34:39.62#ibcon#end of sib2, iclass 4, count 0 2006.259.07:34:39.62#ibcon#*mode == 0, iclass 4, count 0 2006.259.07:34:39.62#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.259.07:34:39.62#ibcon#[26=FRQ=04,832.99\r\n] 2006.259.07:34:39.62#ibcon#*before write, iclass 4, count 0 2006.259.07:34:39.62#ibcon#enter sib2, iclass 4, count 0 2006.259.07:34:39.62#ibcon#flushed, iclass 4, count 0 2006.259.07:34:39.62#ibcon#about to write, iclass 4, count 0 2006.259.07:34:39.62#ibcon#wrote, iclass 4, count 0 2006.259.07:34:39.62#ibcon#about to read 3, iclass 4, count 0 2006.259.07:34:39.66#ibcon#read 3, iclass 4, count 0 2006.259.07:34:39.66#ibcon#about to read 4, iclass 4, count 0 2006.259.07:34:39.66#ibcon#read 4, iclass 4, count 0 2006.259.07:34:39.66#ibcon#about to read 5, iclass 4, count 0 2006.259.07:34:39.66#ibcon#read 5, iclass 4, count 0 2006.259.07:34:39.66#ibcon#about to read 6, iclass 4, count 0 2006.259.07:34:39.66#ibcon#read 6, iclass 4, count 0 2006.259.07:34:39.66#ibcon#end of sib2, iclass 4, count 0 2006.259.07:34:39.66#ibcon#*after write, iclass 4, count 0 2006.259.07:34:39.66#ibcon#*before return 0, iclass 4, count 0 2006.259.07:34:39.66#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.259.07:34:39.66#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.259.07:34:39.66#ibcon#about to clear, iclass 4 cls_cnt 0 2006.259.07:34:39.66#ibcon#cleared, iclass 4 cls_cnt 0 2006.259.07:34:39.66$vc4f8/va=4,7 2006.259.07:34:39.66#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.259.07:34:39.66#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.259.07:34:39.66#ibcon#ireg 11 cls_cnt 2 2006.259.07:34:39.66#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.259.07:34:39.72#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.259.07:34:39.72#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.259.07:34:39.72#ibcon#enter wrdev, iclass 6, count 2 2006.259.07:34:39.72#ibcon#first serial, iclass 6, count 2 2006.259.07:34:39.72#ibcon#enter sib2, iclass 6, count 2 2006.259.07:34:39.72#ibcon#flushed, iclass 6, count 2 2006.259.07:34:39.72#ibcon#about to write, iclass 6, count 2 2006.259.07:34:39.72#ibcon#wrote, iclass 6, count 2 2006.259.07:34:39.72#ibcon#about to read 3, iclass 6, count 2 2006.259.07:34:39.74#ibcon#read 3, iclass 6, count 2 2006.259.07:34:39.74#ibcon#about to read 4, iclass 6, count 2 2006.259.07:34:39.74#ibcon#read 4, iclass 6, count 2 2006.259.07:34:39.74#ibcon#about to read 5, iclass 6, count 2 2006.259.07:34:39.74#ibcon#read 5, iclass 6, count 2 2006.259.07:34:39.74#ibcon#about to read 6, iclass 6, count 2 2006.259.07:34:39.74#ibcon#read 6, iclass 6, count 2 2006.259.07:34:39.74#ibcon#end of sib2, iclass 6, count 2 2006.259.07:34:39.74#ibcon#*mode == 0, iclass 6, count 2 2006.259.07:34:39.74#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.259.07:34:39.74#ibcon#[25=AT04-07\r\n] 2006.259.07:34:39.74#ibcon#*before write, iclass 6, count 2 2006.259.07:34:39.74#ibcon#enter sib2, iclass 6, count 2 2006.259.07:34:39.74#ibcon#flushed, iclass 6, count 2 2006.259.07:34:39.74#ibcon#about to write, iclass 6, count 2 2006.259.07:34:39.74#ibcon#wrote, iclass 6, count 2 2006.259.07:34:39.74#ibcon#about to read 3, iclass 6, count 2 2006.259.07:34:39.77#ibcon#read 3, iclass 6, count 2 2006.259.07:34:39.77#ibcon#about to read 4, iclass 6, count 2 2006.259.07:34:39.77#ibcon#read 4, iclass 6, count 2 2006.259.07:34:39.77#ibcon#about to read 5, iclass 6, count 2 2006.259.07:34:39.77#ibcon#read 5, iclass 6, count 2 2006.259.07:34:39.77#ibcon#about to read 6, iclass 6, count 2 2006.259.07:34:39.77#ibcon#read 6, iclass 6, count 2 2006.259.07:34:39.77#ibcon#end of sib2, iclass 6, count 2 2006.259.07:34:39.77#ibcon#*after write, iclass 6, count 2 2006.259.07:34:39.77#ibcon#*before return 0, iclass 6, count 2 2006.259.07:34:39.77#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.259.07:34:39.77#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.259.07:34:39.77#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.259.07:34:39.77#ibcon#ireg 7 cls_cnt 0 2006.259.07:34:39.77#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.259.07:34:39.89#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.259.07:34:39.89#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.259.07:34:39.89#ibcon#enter wrdev, iclass 6, count 0 2006.259.07:34:39.89#ibcon#first serial, iclass 6, count 0 2006.259.07:34:39.89#ibcon#enter sib2, iclass 6, count 0 2006.259.07:34:39.89#ibcon#flushed, iclass 6, count 0 2006.259.07:34:39.89#ibcon#about to write, iclass 6, count 0 2006.259.07:34:39.89#ibcon#wrote, iclass 6, count 0 2006.259.07:34:39.89#ibcon#about to read 3, iclass 6, count 0 2006.259.07:34:39.91#ibcon#read 3, iclass 6, count 0 2006.259.07:34:39.91#ibcon#about to read 4, iclass 6, count 0 2006.259.07:34:39.91#ibcon#read 4, iclass 6, count 0 2006.259.07:34:39.91#ibcon#about to read 5, iclass 6, count 0 2006.259.07:34:39.91#ibcon#read 5, iclass 6, count 0 2006.259.07:34:39.91#ibcon#about to read 6, iclass 6, count 0 2006.259.07:34:39.91#ibcon#read 6, iclass 6, count 0 2006.259.07:34:39.91#ibcon#end of sib2, iclass 6, count 0 2006.259.07:34:39.91#ibcon#*mode == 0, iclass 6, count 0 2006.259.07:34:39.91#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.259.07:34:39.91#ibcon#[25=USB\r\n] 2006.259.07:34:39.91#ibcon#*before write, iclass 6, count 0 2006.259.07:34:39.91#ibcon#enter sib2, iclass 6, count 0 2006.259.07:34:39.91#ibcon#flushed, iclass 6, count 0 2006.259.07:34:39.91#ibcon#about to write, iclass 6, count 0 2006.259.07:34:39.91#ibcon#wrote, iclass 6, count 0 2006.259.07:34:39.91#ibcon#about to read 3, iclass 6, count 0 2006.259.07:34:39.94#ibcon#read 3, iclass 6, count 0 2006.259.07:34:39.94#ibcon#about to read 4, iclass 6, count 0 2006.259.07:34:39.94#ibcon#read 4, iclass 6, count 0 2006.259.07:34:39.94#ibcon#about to read 5, iclass 6, count 0 2006.259.07:34:39.94#ibcon#read 5, iclass 6, count 0 2006.259.07:34:39.94#ibcon#about to read 6, iclass 6, count 0 2006.259.07:34:39.94#ibcon#read 6, iclass 6, count 0 2006.259.07:34:39.94#ibcon#end of sib2, iclass 6, count 0 2006.259.07:34:39.94#ibcon#*after write, iclass 6, count 0 2006.259.07:34:39.94#ibcon#*before return 0, iclass 6, count 0 2006.259.07:34:39.94#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.259.07:34:39.94#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.259.07:34:39.94#ibcon#about to clear, iclass 6 cls_cnt 0 2006.259.07:34:39.94#ibcon#cleared, iclass 6 cls_cnt 0 2006.259.07:34:39.94$vc4f8/valo=5,652.99 2006.259.07:34:39.94#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.259.07:34:39.94#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.259.07:34:39.94#ibcon#ireg 17 cls_cnt 0 2006.259.07:34:39.94#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.259.07:34:39.94#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.259.07:34:39.94#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.259.07:34:39.94#ibcon#enter wrdev, iclass 10, count 0 2006.259.07:34:39.94#ibcon#first serial, iclass 10, count 0 2006.259.07:34:39.94#ibcon#enter sib2, iclass 10, count 0 2006.259.07:34:39.94#ibcon#flushed, iclass 10, count 0 2006.259.07:34:39.94#ibcon#about to write, iclass 10, count 0 2006.259.07:34:39.94#ibcon#wrote, iclass 10, count 0 2006.259.07:34:39.94#ibcon#about to read 3, iclass 10, count 0 2006.259.07:34:39.96#ibcon#read 3, iclass 10, count 0 2006.259.07:34:39.96#ibcon#about to read 4, iclass 10, count 0 2006.259.07:34:39.96#ibcon#read 4, iclass 10, count 0 2006.259.07:34:39.96#ibcon#about to read 5, iclass 10, count 0 2006.259.07:34:39.96#ibcon#read 5, iclass 10, count 0 2006.259.07:34:39.96#ibcon#about to read 6, iclass 10, count 0 2006.259.07:34:39.96#ibcon#read 6, iclass 10, count 0 2006.259.07:34:39.96#ibcon#end of sib2, iclass 10, count 0 2006.259.07:34:39.96#ibcon#*mode == 0, iclass 10, count 0 2006.259.07:34:39.96#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.259.07:34:39.96#ibcon#[26=FRQ=05,652.99\r\n] 2006.259.07:34:39.96#ibcon#*before write, iclass 10, count 0 2006.259.07:34:39.96#ibcon#enter sib2, iclass 10, count 0 2006.259.07:34:39.96#ibcon#flushed, iclass 10, count 0 2006.259.07:34:39.96#ibcon#about to write, iclass 10, count 0 2006.259.07:34:39.96#ibcon#wrote, iclass 10, count 0 2006.259.07:34:39.96#ibcon#about to read 3, iclass 10, count 0 2006.259.07:34:40.00#ibcon#read 3, iclass 10, count 0 2006.259.07:34:40.00#ibcon#about to read 4, iclass 10, count 0 2006.259.07:34:40.00#ibcon#read 4, iclass 10, count 0 2006.259.07:34:40.00#ibcon#about to read 5, iclass 10, count 0 2006.259.07:34:40.00#ibcon#read 5, iclass 10, count 0 2006.259.07:34:40.00#ibcon#about to read 6, iclass 10, count 0 2006.259.07:34:40.00#ibcon#read 6, iclass 10, count 0 2006.259.07:34:40.00#ibcon#end of sib2, iclass 10, count 0 2006.259.07:34:40.00#ibcon#*after write, iclass 10, count 0 2006.259.07:34:40.00#ibcon#*before return 0, iclass 10, count 0 2006.259.07:34:40.00#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.259.07:34:40.00#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.259.07:34:40.00#ibcon#about to clear, iclass 10 cls_cnt 0 2006.259.07:34:40.00#ibcon#cleared, iclass 10 cls_cnt 0 2006.259.07:34:40.00$vc4f8/va=5,7 2006.259.07:34:40.00#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.259.07:34:40.00#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.259.07:34:40.00#ibcon#ireg 11 cls_cnt 2 2006.259.07:34:40.00#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.259.07:34:40.06#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.259.07:34:40.06#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.259.07:34:40.06#ibcon#enter wrdev, iclass 12, count 2 2006.259.07:34:40.06#ibcon#first serial, iclass 12, count 2 2006.259.07:34:40.06#ibcon#enter sib2, iclass 12, count 2 2006.259.07:34:40.06#ibcon#flushed, iclass 12, count 2 2006.259.07:34:40.06#ibcon#about to write, iclass 12, count 2 2006.259.07:34:40.06#ibcon#wrote, iclass 12, count 2 2006.259.07:34:40.06#ibcon#about to read 3, iclass 12, count 2 2006.259.07:34:40.08#ibcon#read 3, iclass 12, count 2 2006.259.07:34:40.08#ibcon#about to read 4, iclass 12, count 2 2006.259.07:34:40.08#ibcon#read 4, iclass 12, count 2 2006.259.07:34:40.08#ibcon#about to read 5, iclass 12, count 2 2006.259.07:34:40.08#ibcon#read 5, iclass 12, count 2 2006.259.07:34:40.08#ibcon#about to read 6, iclass 12, count 2 2006.259.07:34:40.08#ibcon#read 6, iclass 12, count 2 2006.259.07:34:40.08#ibcon#end of sib2, iclass 12, count 2 2006.259.07:34:40.08#ibcon#*mode == 0, iclass 12, count 2 2006.259.07:34:40.08#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.259.07:34:40.08#ibcon#[25=AT05-07\r\n] 2006.259.07:34:40.08#ibcon#*before write, iclass 12, count 2 2006.259.07:34:40.08#ibcon#enter sib2, iclass 12, count 2 2006.259.07:34:40.08#ibcon#flushed, iclass 12, count 2 2006.259.07:34:40.08#ibcon#about to write, iclass 12, count 2 2006.259.07:34:40.08#ibcon#wrote, iclass 12, count 2 2006.259.07:34:40.08#ibcon#about to read 3, iclass 12, count 2 2006.259.07:34:40.11#ibcon#read 3, iclass 12, count 2 2006.259.07:34:40.11#ibcon#about to read 4, iclass 12, count 2 2006.259.07:34:40.11#ibcon#read 4, iclass 12, count 2 2006.259.07:34:40.11#ibcon#about to read 5, iclass 12, count 2 2006.259.07:34:40.11#ibcon#read 5, iclass 12, count 2 2006.259.07:34:40.11#ibcon#about to read 6, iclass 12, count 2 2006.259.07:34:40.11#ibcon#read 6, iclass 12, count 2 2006.259.07:34:40.11#ibcon#end of sib2, iclass 12, count 2 2006.259.07:34:40.11#ibcon#*after write, iclass 12, count 2 2006.259.07:34:40.11#ibcon#*before return 0, iclass 12, count 2 2006.259.07:34:40.11#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.259.07:34:40.11#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.259.07:34:40.11#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.259.07:34:40.11#ibcon#ireg 7 cls_cnt 0 2006.259.07:34:40.11#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.259.07:34:40.23#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.259.07:34:40.23#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.259.07:34:40.23#ibcon#enter wrdev, iclass 12, count 0 2006.259.07:34:40.23#ibcon#first serial, iclass 12, count 0 2006.259.07:34:40.23#ibcon#enter sib2, iclass 12, count 0 2006.259.07:34:40.23#ibcon#flushed, iclass 12, count 0 2006.259.07:34:40.23#ibcon#about to write, iclass 12, count 0 2006.259.07:34:40.23#ibcon#wrote, iclass 12, count 0 2006.259.07:34:40.23#ibcon#about to read 3, iclass 12, count 0 2006.259.07:34:40.27#ibcon#read 3, iclass 12, count 0 2006.259.07:34:40.27#ibcon#about to read 4, iclass 12, count 0 2006.259.07:34:40.27#ibcon#read 4, iclass 12, count 0 2006.259.07:34:40.27#ibcon#about to read 5, iclass 12, count 0 2006.259.07:34:40.27#ibcon#read 5, iclass 12, count 0 2006.259.07:34:40.27#ibcon#about to read 6, iclass 12, count 0 2006.259.07:34:40.27#ibcon#read 6, iclass 12, count 0 2006.259.07:34:40.27#ibcon#end of sib2, iclass 12, count 0 2006.259.07:34:40.27#ibcon#*mode == 0, iclass 12, count 0 2006.259.07:34:40.27#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.259.07:34:40.27#ibcon#[25=USB\r\n] 2006.259.07:34:40.27#ibcon#*before write, iclass 12, count 0 2006.259.07:34:40.27#ibcon#enter sib2, iclass 12, count 0 2006.259.07:34:40.27#ibcon#flushed, iclass 12, count 0 2006.259.07:34:40.27#ibcon#about to write, iclass 12, count 0 2006.259.07:34:40.27#ibcon#wrote, iclass 12, count 0 2006.259.07:34:40.27#ibcon#about to read 3, iclass 12, count 0 2006.259.07:34:40.30#ibcon#read 3, iclass 12, count 0 2006.259.07:34:40.30#ibcon#about to read 4, iclass 12, count 0 2006.259.07:34:40.30#ibcon#read 4, iclass 12, count 0 2006.259.07:34:40.30#ibcon#about to read 5, iclass 12, count 0 2006.259.07:34:40.30#ibcon#read 5, iclass 12, count 0 2006.259.07:34:40.30#ibcon#about to read 6, iclass 12, count 0 2006.259.07:34:40.30#ibcon#read 6, iclass 12, count 0 2006.259.07:34:40.30#ibcon#end of sib2, iclass 12, count 0 2006.259.07:34:40.30#ibcon#*after write, iclass 12, count 0 2006.259.07:34:40.30#ibcon#*before return 0, iclass 12, count 0 2006.259.07:34:40.30#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.259.07:34:40.30#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.259.07:34:40.30#ibcon#about to clear, iclass 12 cls_cnt 0 2006.259.07:34:40.30#ibcon#cleared, iclass 12 cls_cnt 0 2006.259.07:34:40.30$vc4f8/valo=6,772.99 2006.259.07:34:40.30#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.259.07:34:40.30#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.259.07:34:40.30#ibcon#ireg 17 cls_cnt 0 2006.259.07:34:40.30#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.259.07:34:40.30#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.259.07:34:40.30#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.259.07:34:40.30#ibcon#enter wrdev, iclass 14, count 0 2006.259.07:34:40.30#ibcon#first serial, iclass 14, count 0 2006.259.07:34:40.30#ibcon#enter sib2, iclass 14, count 0 2006.259.07:34:40.30#ibcon#flushed, iclass 14, count 0 2006.259.07:34:40.30#ibcon#about to write, iclass 14, count 0 2006.259.07:34:40.30#ibcon#wrote, iclass 14, count 0 2006.259.07:34:40.30#ibcon#about to read 3, iclass 14, count 0 2006.259.07:34:40.32#ibcon#read 3, iclass 14, count 0 2006.259.07:34:40.32#ibcon#about to read 4, iclass 14, count 0 2006.259.07:34:40.32#ibcon#read 4, iclass 14, count 0 2006.259.07:34:40.32#ibcon#about to read 5, iclass 14, count 0 2006.259.07:34:40.32#ibcon#read 5, iclass 14, count 0 2006.259.07:34:40.32#ibcon#about to read 6, iclass 14, count 0 2006.259.07:34:40.32#ibcon#read 6, iclass 14, count 0 2006.259.07:34:40.32#ibcon#end of sib2, iclass 14, count 0 2006.259.07:34:40.32#ibcon#*mode == 0, iclass 14, count 0 2006.259.07:34:40.32#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.259.07:34:40.32#ibcon#[26=FRQ=06,772.99\r\n] 2006.259.07:34:40.32#ibcon#*before write, iclass 14, count 0 2006.259.07:34:40.32#ibcon#enter sib2, iclass 14, count 0 2006.259.07:34:40.32#ibcon#flushed, iclass 14, count 0 2006.259.07:34:40.32#ibcon#about to write, iclass 14, count 0 2006.259.07:34:40.32#ibcon#wrote, iclass 14, count 0 2006.259.07:34:40.32#ibcon#about to read 3, iclass 14, count 0 2006.259.07:34:40.36#ibcon#read 3, iclass 14, count 0 2006.259.07:34:40.36#ibcon#about to read 4, iclass 14, count 0 2006.259.07:34:40.36#ibcon#read 4, iclass 14, count 0 2006.259.07:34:40.36#ibcon#about to read 5, iclass 14, count 0 2006.259.07:34:40.36#ibcon#read 5, iclass 14, count 0 2006.259.07:34:40.36#ibcon#about to read 6, iclass 14, count 0 2006.259.07:34:40.36#ibcon#read 6, iclass 14, count 0 2006.259.07:34:40.36#ibcon#end of sib2, iclass 14, count 0 2006.259.07:34:40.36#ibcon#*after write, iclass 14, count 0 2006.259.07:34:40.36#ibcon#*before return 0, iclass 14, count 0 2006.259.07:34:40.36#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.259.07:34:40.36#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.259.07:34:40.36#ibcon#about to clear, iclass 14 cls_cnt 0 2006.259.07:34:40.36#ibcon#cleared, iclass 14 cls_cnt 0 2006.259.07:34:40.36$vc4f8/va=6,6 2006.259.07:34:40.36#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.259.07:34:40.36#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.259.07:34:40.36#ibcon#ireg 11 cls_cnt 2 2006.259.07:34:40.36#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.259.07:34:40.42#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.259.07:34:40.42#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.259.07:34:40.42#ibcon#enter wrdev, iclass 16, count 2 2006.259.07:34:40.42#ibcon#first serial, iclass 16, count 2 2006.259.07:34:40.42#ibcon#enter sib2, iclass 16, count 2 2006.259.07:34:40.42#ibcon#flushed, iclass 16, count 2 2006.259.07:34:40.42#ibcon#about to write, iclass 16, count 2 2006.259.07:34:40.42#ibcon#wrote, iclass 16, count 2 2006.259.07:34:40.42#ibcon#about to read 3, iclass 16, count 2 2006.259.07:34:40.44#ibcon#read 3, iclass 16, count 2 2006.259.07:34:40.44#ibcon#about to read 4, iclass 16, count 2 2006.259.07:34:40.44#ibcon#read 4, iclass 16, count 2 2006.259.07:34:40.44#ibcon#about to read 5, iclass 16, count 2 2006.259.07:34:40.44#ibcon#read 5, iclass 16, count 2 2006.259.07:34:40.44#ibcon#about to read 6, iclass 16, count 2 2006.259.07:34:40.44#ibcon#read 6, iclass 16, count 2 2006.259.07:34:40.44#ibcon#end of sib2, iclass 16, count 2 2006.259.07:34:40.44#ibcon#*mode == 0, iclass 16, count 2 2006.259.07:34:40.44#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.259.07:34:40.44#ibcon#[25=AT06-06\r\n] 2006.259.07:34:40.44#ibcon#*before write, iclass 16, count 2 2006.259.07:34:40.44#ibcon#enter sib2, iclass 16, count 2 2006.259.07:34:40.44#ibcon#flushed, iclass 16, count 2 2006.259.07:34:40.44#ibcon#about to write, iclass 16, count 2 2006.259.07:34:40.44#ibcon#wrote, iclass 16, count 2 2006.259.07:34:40.44#ibcon#about to read 3, iclass 16, count 2 2006.259.07:34:40.47#ibcon#read 3, iclass 16, count 2 2006.259.07:34:40.47#ibcon#about to read 4, iclass 16, count 2 2006.259.07:34:40.47#ibcon#read 4, iclass 16, count 2 2006.259.07:34:40.47#ibcon#about to read 5, iclass 16, count 2 2006.259.07:34:40.47#ibcon#read 5, iclass 16, count 2 2006.259.07:34:40.47#ibcon#about to read 6, iclass 16, count 2 2006.259.07:34:40.47#ibcon#read 6, iclass 16, count 2 2006.259.07:34:40.47#ibcon#end of sib2, iclass 16, count 2 2006.259.07:34:40.47#ibcon#*after write, iclass 16, count 2 2006.259.07:34:40.47#ibcon#*before return 0, iclass 16, count 2 2006.259.07:34:40.47#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.259.07:34:40.47#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.259.07:34:40.47#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.259.07:34:40.47#ibcon#ireg 7 cls_cnt 0 2006.259.07:34:40.47#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.259.07:34:40.59#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.259.07:34:40.59#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.259.07:34:40.59#ibcon#enter wrdev, iclass 16, count 0 2006.259.07:34:40.59#ibcon#first serial, iclass 16, count 0 2006.259.07:34:40.59#ibcon#enter sib2, iclass 16, count 0 2006.259.07:34:40.59#ibcon#flushed, iclass 16, count 0 2006.259.07:34:40.59#ibcon#about to write, iclass 16, count 0 2006.259.07:34:40.59#ibcon#wrote, iclass 16, count 0 2006.259.07:34:40.59#ibcon#about to read 3, iclass 16, count 0 2006.259.07:34:40.61#ibcon#read 3, iclass 16, count 0 2006.259.07:34:40.61#ibcon#about to read 4, iclass 16, count 0 2006.259.07:34:40.61#ibcon#read 4, iclass 16, count 0 2006.259.07:34:40.61#ibcon#about to read 5, iclass 16, count 0 2006.259.07:34:40.61#ibcon#read 5, iclass 16, count 0 2006.259.07:34:40.61#ibcon#about to read 6, iclass 16, count 0 2006.259.07:34:40.61#ibcon#read 6, iclass 16, count 0 2006.259.07:34:40.61#ibcon#end of sib2, iclass 16, count 0 2006.259.07:34:40.61#ibcon#*mode == 0, iclass 16, count 0 2006.259.07:34:40.61#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.259.07:34:40.61#ibcon#[25=USB\r\n] 2006.259.07:34:40.61#ibcon#*before write, iclass 16, count 0 2006.259.07:34:40.61#ibcon#enter sib2, iclass 16, count 0 2006.259.07:34:40.61#ibcon#flushed, iclass 16, count 0 2006.259.07:34:40.61#ibcon#about to write, iclass 16, count 0 2006.259.07:34:40.61#ibcon#wrote, iclass 16, count 0 2006.259.07:34:40.61#ibcon#about to read 3, iclass 16, count 0 2006.259.07:34:40.64#ibcon#read 3, iclass 16, count 0 2006.259.07:34:40.64#ibcon#about to read 4, iclass 16, count 0 2006.259.07:34:40.64#ibcon#read 4, iclass 16, count 0 2006.259.07:34:40.64#ibcon#about to read 5, iclass 16, count 0 2006.259.07:34:40.64#ibcon#read 5, iclass 16, count 0 2006.259.07:34:40.64#ibcon#about to read 6, iclass 16, count 0 2006.259.07:34:40.64#ibcon#read 6, iclass 16, count 0 2006.259.07:34:40.64#ibcon#end of sib2, iclass 16, count 0 2006.259.07:34:40.64#ibcon#*after write, iclass 16, count 0 2006.259.07:34:40.64#ibcon#*before return 0, iclass 16, count 0 2006.259.07:34:40.64#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.259.07:34:40.64#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.259.07:34:40.64#ibcon#about to clear, iclass 16 cls_cnt 0 2006.259.07:34:40.64#ibcon#cleared, iclass 16 cls_cnt 0 2006.259.07:34:40.64$vc4f8/valo=7,832.99 2006.259.07:34:40.64#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.259.07:34:40.64#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.259.07:34:40.64#ibcon#ireg 17 cls_cnt 0 2006.259.07:34:40.64#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.259.07:34:40.64#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.259.07:34:40.64#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.259.07:34:40.64#ibcon#enter wrdev, iclass 18, count 0 2006.259.07:34:40.64#ibcon#first serial, iclass 18, count 0 2006.259.07:34:40.64#ibcon#enter sib2, iclass 18, count 0 2006.259.07:34:40.64#ibcon#flushed, iclass 18, count 0 2006.259.07:34:40.64#ibcon#about to write, iclass 18, count 0 2006.259.07:34:40.64#ibcon#wrote, iclass 18, count 0 2006.259.07:34:40.64#ibcon#about to read 3, iclass 18, count 0 2006.259.07:34:40.66#ibcon#read 3, iclass 18, count 0 2006.259.07:34:40.66#ibcon#about to read 4, iclass 18, count 0 2006.259.07:34:40.66#ibcon#read 4, iclass 18, count 0 2006.259.07:34:40.66#ibcon#about to read 5, iclass 18, count 0 2006.259.07:34:40.66#ibcon#read 5, iclass 18, count 0 2006.259.07:34:40.66#ibcon#about to read 6, iclass 18, count 0 2006.259.07:34:40.66#ibcon#read 6, iclass 18, count 0 2006.259.07:34:40.66#ibcon#end of sib2, iclass 18, count 0 2006.259.07:34:40.66#ibcon#*mode == 0, iclass 18, count 0 2006.259.07:34:40.66#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.259.07:34:40.66#ibcon#[26=FRQ=07,832.99\r\n] 2006.259.07:34:40.66#ibcon#*before write, iclass 18, count 0 2006.259.07:34:40.66#ibcon#enter sib2, iclass 18, count 0 2006.259.07:34:40.66#ibcon#flushed, iclass 18, count 0 2006.259.07:34:40.66#ibcon#about to write, iclass 18, count 0 2006.259.07:34:40.66#ibcon#wrote, iclass 18, count 0 2006.259.07:34:40.66#ibcon#about to read 3, iclass 18, count 0 2006.259.07:34:40.70#ibcon#read 3, iclass 18, count 0 2006.259.07:34:40.70#ibcon#about to read 4, iclass 18, count 0 2006.259.07:34:40.70#ibcon#read 4, iclass 18, count 0 2006.259.07:34:40.70#ibcon#about to read 5, iclass 18, count 0 2006.259.07:34:40.70#ibcon#read 5, iclass 18, count 0 2006.259.07:34:40.70#ibcon#about to read 6, iclass 18, count 0 2006.259.07:34:40.70#ibcon#read 6, iclass 18, count 0 2006.259.07:34:40.70#ibcon#end of sib2, iclass 18, count 0 2006.259.07:34:40.70#ibcon#*after write, iclass 18, count 0 2006.259.07:34:40.70#ibcon#*before return 0, iclass 18, count 0 2006.259.07:34:40.70#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.259.07:34:40.70#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.259.07:34:40.70#ibcon#about to clear, iclass 18 cls_cnt 0 2006.259.07:34:40.70#ibcon#cleared, iclass 18 cls_cnt 0 2006.259.07:34:40.70$vc4f8/va=7,6 2006.259.07:34:40.70#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.259.07:34:40.70#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.259.07:34:40.70#ibcon#ireg 11 cls_cnt 2 2006.259.07:34:40.70#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.259.07:34:40.76#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.259.07:34:40.76#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.259.07:34:40.76#ibcon#enter wrdev, iclass 20, count 2 2006.259.07:34:40.76#ibcon#first serial, iclass 20, count 2 2006.259.07:34:40.76#ibcon#enter sib2, iclass 20, count 2 2006.259.07:34:40.76#ibcon#flushed, iclass 20, count 2 2006.259.07:34:40.76#ibcon#about to write, iclass 20, count 2 2006.259.07:34:40.76#ibcon#wrote, iclass 20, count 2 2006.259.07:34:40.76#ibcon#about to read 3, iclass 20, count 2 2006.259.07:34:40.78#ibcon#read 3, iclass 20, count 2 2006.259.07:34:40.78#ibcon#about to read 4, iclass 20, count 2 2006.259.07:34:40.78#ibcon#read 4, iclass 20, count 2 2006.259.07:34:40.78#ibcon#about to read 5, iclass 20, count 2 2006.259.07:34:40.78#ibcon#read 5, iclass 20, count 2 2006.259.07:34:40.78#ibcon#about to read 6, iclass 20, count 2 2006.259.07:34:40.78#ibcon#read 6, iclass 20, count 2 2006.259.07:34:40.78#ibcon#end of sib2, iclass 20, count 2 2006.259.07:34:40.78#ibcon#*mode == 0, iclass 20, count 2 2006.259.07:34:40.78#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.259.07:34:40.78#ibcon#[25=AT07-06\r\n] 2006.259.07:34:40.78#ibcon#*before write, iclass 20, count 2 2006.259.07:34:40.78#ibcon#enter sib2, iclass 20, count 2 2006.259.07:34:40.78#ibcon#flushed, iclass 20, count 2 2006.259.07:34:40.78#ibcon#about to write, iclass 20, count 2 2006.259.07:34:40.78#ibcon#wrote, iclass 20, count 2 2006.259.07:34:40.78#ibcon#about to read 3, iclass 20, count 2 2006.259.07:34:40.81#ibcon#read 3, iclass 20, count 2 2006.259.07:34:40.81#ibcon#about to read 4, iclass 20, count 2 2006.259.07:34:40.81#ibcon#read 4, iclass 20, count 2 2006.259.07:34:40.81#ibcon#about to read 5, iclass 20, count 2 2006.259.07:34:40.81#ibcon#read 5, iclass 20, count 2 2006.259.07:34:40.81#ibcon#about to read 6, iclass 20, count 2 2006.259.07:34:40.81#ibcon#read 6, iclass 20, count 2 2006.259.07:34:40.81#ibcon#end of sib2, iclass 20, count 2 2006.259.07:34:40.81#ibcon#*after write, iclass 20, count 2 2006.259.07:34:40.81#ibcon#*before return 0, iclass 20, count 2 2006.259.07:34:40.81#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.259.07:34:40.81#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.259.07:34:40.81#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.259.07:34:40.81#ibcon#ireg 7 cls_cnt 0 2006.259.07:34:40.81#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.259.07:34:40.93#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.259.07:34:40.93#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.259.07:34:40.93#ibcon#enter wrdev, iclass 20, count 0 2006.259.07:34:40.93#ibcon#first serial, iclass 20, count 0 2006.259.07:34:40.93#ibcon#enter sib2, iclass 20, count 0 2006.259.07:34:40.93#ibcon#flushed, iclass 20, count 0 2006.259.07:34:40.93#ibcon#about to write, iclass 20, count 0 2006.259.07:34:40.93#ibcon#wrote, iclass 20, count 0 2006.259.07:34:40.93#ibcon#about to read 3, iclass 20, count 0 2006.259.07:34:40.95#ibcon#read 3, iclass 20, count 0 2006.259.07:34:40.95#ibcon#about to read 4, iclass 20, count 0 2006.259.07:34:40.95#ibcon#read 4, iclass 20, count 0 2006.259.07:34:40.95#ibcon#about to read 5, iclass 20, count 0 2006.259.07:34:40.95#ibcon#read 5, iclass 20, count 0 2006.259.07:34:40.95#ibcon#about to read 6, iclass 20, count 0 2006.259.07:34:40.95#ibcon#read 6, iclass 20, count 0 2006.259.07:34:40.95#ibcon#end of sib2, iclass 20, count 0 2006.259.07:34:40.95#ibcon#*mode == 0, iclass 20, count 0 2006.259.07:34:40.95#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.259.07:34:40.95#ibcon#[25=USB\r\n] 2006.259.07:34:40.95#ibcon#*before write, iclass 20, count 0 2006.259.07:34:40.95#ibcon#enter sib2, iclass 20, count 0 2006.259.07:34:40.95#ibcon#flushed, iclass 20, count 0 2006.259.07:34:40.95#ibcon#about to write, iclass 20, count 0 2006.259.07:34:40.95#ibcon#wrote, iclass 20, count 0 2006.259.07:34:40.95#ibcon#about to read 3, iclass 20, count 0 2006.259.07:34:40.98#ibcon#read 3, iclass 20, count 0 2006.259.07:34:40.98#ibcon#about to read 4, iclass 20, count 0 2006.259.07:34:40.98#ibcon#read 4, iclass 20, count 0 2006.259.07:34:40.98#ibcon#about to read 5, iclass 20, count 0 2006.259.07:34:40.98#ibcon#read 5, iclass 20, count 0 2006.259.07:34:40.98#ibcon#about to read 6, iclass 20, count 0 2006.259.07:34:40.98#ibcon#read 6, iclass 20, count 0 2006.259.07:34:40.98#ibcon#end of sib2, iclass 20, count 0 2006.259.07:34:40.98#ibcon#*after write, iclass 20, count 0 2006.259.07:34:40.98#ibcon#*before return 0, iclass 20, count 0 2006.259.07:34:40.98#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.259.07:34:40.98#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.259.07:34:40.98#ibcon#about to clear, iclass 20 cls_cnt 0 2006.259.07:34:40.98#ibcon#cleared, iclass 20 cls_cnt 0 2006.259.07:34:40.98$vc4f8/valo=8,852.99 2006.259.07:34:40.98#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.259.07:34:40.98#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.259.07:34:40.98#ibcon#ireg 17 cls_cnt 0 2006.259.07:34:40.98#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.259.07:34:40.98#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.259.07:34:40.98#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.259.07:34:40.98#ibcon#enter wrdev, iclass 22, count 0 2006.259.07:34:40.98#ibcon#first serial, iclass 22, count 0 2006.259.07:34:40.98#ibcon#enter sib2, iclass 22, count 0 2006.259.07:34:40.98#ibcon#flushed, iclass 22, count 0 2006.259.07:34:40.98#ibcon#about to write, iclass 22, count 0 2006.259.07:34:40.98#ibcon#wrote, iclass 22, count 0 2006.259.07:34:40.98#ibcon#about to read 3, iclass 22, count 0 2006.259.07:34:41.00#ibcon#read 3, iclass 22, count 0 2006.259.07:34:41.00#ibcon#about to read 4, iclass 22, count 0 2006.259.07:34:41.00#ibcon#read 4, iclass 22, count 0 2006.259.07:34:41.00#ibcon#about to read 5, iclass 22, count 0 2006.259.07:34:41.00#ibcon#read 5, iclass 22, count 0 2006.259.07:34:41.00#ibcon#about to read 6, iclass 22, count 0 2006.259.07:34:41.00#ibcon#read 6, iclass 22, count 0 2006.259.07:34:41.00#ibcon#end of sib2, iclass 22, count 0 2006.259.07:34:41.00#ibcon#*mode == 0, iclass 22, count 0 2006.259.07:34:41.00#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.259.07:34:41.00#ibcon#[26=FRQ=08,852.99\r\n] 2006.259.07:34:41.00#ibcon#*before write, iclass 22, count 0 2006.259.07:34:41.00#ibcon#enter sib2, iclass 22, count 0 2006.259.07:34:41.00#ibcon#flushed, iclass 22, count 0 2006.259.07:34:41.00#ibcon#about to write, iclass 22, count 0 2006.259.07:34:41.00#ibcon#wrote, iclass 22, count 0 2006.259.07:34:41.00#ibcon#about to read 3, iclass 22, count 0 2006.259.07:34:41.04#ibcon#read 3, iclass 22, count 0 2006.259.07:34:41.04#ibcon#about to read 4, iclass 22, count 0 2006.259.07:34:41.04#ibcon#read 4, iclass 22, count 0 2006.259.07:34:41.04#ibcon#about to read 5, iclass 22, count 0 2006.259.07:34:41.04#ibcon#read 5, iclass 22, count 0 2006.259.07:34:41.04#ibcon#about to read 6, iclass 22, count 0 2006.259.07:34:41.04#ibcon#read 6, iclass 22, count 0 2006.259.07:34:41.04#ibcon#end of sib2, iclass 22, count 0 2006.259.07:34:41.04#ibcon#*after write, iclass 22, count 0 2006.259.07:34:41.04#ibcon#*before return 0, iclass 22, count 0 2006.259.07:34:41.04#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.259.07:34:41.04#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.259.07:34:41.04#ibcon#about to clear, iclass 22 cls_cnt 0 2006.259.07:34:41.04#ibcon#cleared, iclass 22 cls_cnt 0 2006.259.07:34:41.04$vc4f8/va=8,6 2006.259.07:34:41.04#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.259.07:34:41.04#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.259.07:34:41.04#ibcon#ireg 11 cls_cnt 2 2006.259.07:34:41.04#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.259.07:34:41.11#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.259.07:34:41.11#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.259.07:34:41.11#ibcon#enter wrdev, iclass 24, count 2 2006.259.07:34:41.11#ibcon#first serial, iclass 24, count 2 2006.259.07:34:41.11#ibcon#enter sib2, iclass 24, count 2 2006.259.07:34:41.11#ibcon#flushed, iclass 24, count 2 2006.259.07:34:41.11#ibcon#about to write, iclass 24, count 2 2006.259.07:34:41.11#ibcon#wrote, iclass 24, count 2 2006.259.07:34:41.11#ibcon#about to read 3, iclass 24, count 2 2006.259.07:34:41.12#ibcon#read 3, iclass 24, count 2 2006.259.07:34:41.12#ibcon#about to read 4, iclass 24, count 2 2006.259.07:34:41.12#ibcon#read 4, iclass 24, count 2 2006.259.07:34:41.12#ibcon#about to read 5, iclass 24, count 2 2006.259.07:34:41.12#ibcon#read 5, iclass 24, count 2 2006.259.07:34:41.12#ibcon#about to read 6, iclass 24, count 2 2006.259.07:34:41.12#ibcon#read 6, iclass 24, count 2 2006.259.07:34:41.12#ibcon#end of sib2, iclass 24, count 2 2006.259.07:34:41.12#ibcon#*mode == 0, iclass 24, count 2 2006.259.07:34:41.12#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.259.07:34:41.12#ibcon#[25=AT08-06\r\n] 2006.259.07:34:41.12#ibcon#*before write, iclass 24, count 2 2006.259.07:34:41.12#ibcon#enter sib2, iclass 24, count 2 2006.259.07:34:41.12#ibcon#flushed, iclass 24, count 2 2006.259.07:34:41.12#ibcon#about to write, iclass 24, count 2 2006.259.07:34:41.12#ibcon#wrote, iclass 24, count 2 2006.259.07:34:41.12#ibcon#about to read 3, iclass 24, count 2 2006.259.07:34:41.15#ibcon#read 3, iclass 24, count 2 2006.259.07:34:41.15#ibcon#about to read 4, iclass 24, count 2 2006.259.07:34:41.15#ibcon#read 4, iclass 24, count 2 2006.259.07:34:41.15#ibcon#about to read 5, iclass 24, count 2 2006.259.07:34:41.15#ibcon#read 5, iclass 24, count 2 2006.259.07:34:41.15#ibcon#about to read 6, iclass 24, count 2 2006.259.07:34:41.15#ibcon#read 6, iclass 24, count 2 2006.259.07:34:41.15#ibcon#end of sib2, iclass 24, count 2 2006.259.07:34:41.15#ibcon#*after write, iclass 24, count 2 2006.259.07:34:41.15#ibcon#*before return 0, iclass 24, count 2 2006.259.07:34:41.15#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.259.07:34:41.15#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.259.07:34:41.15#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.259.07:34:41.15#ibcon#ireg 7 cls_cnt 0 2006.259.07:34:41.15#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.259.07:34:41.27#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.259.07:34:41.27#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.259.07:34:41.27#ibcon#enter wrdev, iclass 24, count 0 2006.259.07:34:41.27#ibcon#first serial, iclass 24, count 0 2006.259.07:34:41.27#ibcon#enter sib2, iclass 24, count 0 2006.259.07:34:41.27#ibcon#flushed, iclass 24, count 0 2006.259.07:34:41.27#ibcon#about to write, iclass 24, count 0 2006.259.07:34:41.27#ibcon#wrote, iclass 24, count 0 2006.259.07:34:41.27#ibcon#about to read 3, iclass 24, count 0 2006.259.07:34:41.29#ibcon#read 3, iclass 24, count 0 2006.259.07:34:41.29#ibcon#about to read 4, iclass 24, count 0 2006.259.07:34:41.29#ibcon#read 4, iclass 24, count 0 2006.259.07:34:41.29#ibcon#about to read 5, iclass 24, count 0 2006.259.07:34:41.29#ibcon#read 5, iclass 24, count 0 2006.259.07:34:41.29#ibcon#about to read 6, iclass 24, count 0 2006.259.07:34:41.29#ibcon#read 6, iclass 24, count 0 2006.259.07:34:41.29#ibcon#end of sib2, iclass 24, count 0 2006.259.07:34:41.29#ibcon#*mode == 0, iclass 24, count 0 2006.259.07:34:41.29#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.259.07:34:41.29#ibcon#[25=USB\r\n] 2006.259.07:34:41.29#ibcon#*before write, iclass 24, count 0 2006.259.07:34:41.29#ibcon#enter sib2, iclass 24, count 0 2006.259.07:34:41.29#ibcon#flushed, iclass 24, count 0 2006.259.07:34:41.29#ibcon#about to write, iclass 24, count 0 2006.259.07:34:41.29#ibcon#wrote, iclass 24, count 0 2006.259.07:34:41.29#ibcon#about to read 3, iclass 24, count 0 2006.259.07:34:41.32#ibcon#read 3, iclass 24, count 0 2006.259.07:34:41.32#ibcon#about to read 4, iclass 24, count 0 2006.259.07:34:41.32#ibcon#read 4, iclass 24, count 0 2006.259.07:34:41.32#ibcon#about to read 5, iclass 24, count 0 2006.259.07:34:41.32#ibcon#read 5, iclass 24, count 0 2006.259.07:34:41.32#ibcon#about to read 6, iclass 24, count 0 2006.259.07:34:41.32#ibcon#read 6, iclass 24, count 0 2006.259.07:34:41.32#ibcon#end of sib2, iclass 24, count 0 2006.259.07:34:41.32#ibcon#*after write, iclass 24, count 0 2006.259.07:34:41.32#ibcon#*before return 0, iclass 24, count 0 2006.259.07:34:41.32#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.259.07:34:41.32#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.259.07:34:41.32#ibcon#about to clear, iclass 24 cls_cnt 0 2006.259.07:34:41.32#ibcon#cleared, iclass 24 cls_cnt 0 2006.259.07:34:41.32$vc4f8/vblo=1,632.99 2006.259.07:34:41.32#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.259.07:34:41.32#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.259.07:34:41.32#ibcon#ireg 17 cls_cnt 0 2006.259.07:34:41.32#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.259.07:34:41.32#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.259.07:34:41.32#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.259.07:34:41.32#ibcon#enter wrdev, iclass 26, count 0 2006.259.07:34:41.32#ibcon#first serial, iclass 26, count 0 2006.259.07:34:41.32#ibcon#enter sib2, iclass 26, count 0 2006.259.07:34:41.32#ibcon#flushed, iclass 26, count 0 2006.259.07:34:41.32#ibcon#about to write, iclass 26, count 0 2006.259.07:34:41.32#ibcon#wrote, iclass 26, count 0 2006.259.07:34:41.32#ibcon#about to read 3, iclass 26, count 0 2006.259.07:34:41.34#ibcon#read 3, iclass 26, count 0 2006.259.07:34:41.34#ibcon#about to read 4, iclass 26, count 0 2006.259.07:34:41.34#ibcon#read 4, iclass 26, count 0 2006.259.07:34:41.34#ibcon#about to read 5, iclass 26, count 0 2006.259.07:34:41.34#ibcon#read 5, iclass 26, count 0 2006.259.07:34:41.34#ibcon#about to read 6, iclass 26, count 0 2006.259.07:34:41.34#ibcon#read 6, iclass 26, count 0 2006.259.07:34:41.34#ibcon#end of sib2, iclass 26, count 0 2006.259.07:34:41.34#ibcon#*mode == 0, iclass 26, count 0 2006.259.07:34:41.34#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.259.07:34:41.34#ibcon#[28=FRQ=01,632.99\r\n] 2006.259.07:34:41.34#ibcon#*before write, iclass 26, count 0 2006.259.07:34:41.34#ibcon#enter sib2, iclass 26, count 0 2006.259.07:34:41.34#ibcon#flushed, iclass 26, count 0 2006.259.07:34:41.34#ibcon#about to write, iclass 26, count 0 2006.259.07:34:41.34#ibcon#wrote, iclass 26, count 0 2006.259.07:34:41.34#ibcon#about to read 3, iclass 26, count 0 2006.259.07:34:41.38#ibcon#read 3, iclass 26, count 0 2006.259.07:34:41.38#ibcon#about to read 4, iclass 26, count 0 2006.259.07:34:41.38#ibcon#read 4, iclass 26, count 0 2006.259.07:34:41.38#ibcon#about to read 5, iclass 26, count 0 2006.259.07:34:41.38#ibcon#read 5, iclass 26, count 0 2006.259.07:34:41.38#ibcon#about to read 6, iclass 26, count 0 2006.259.07:34:41.38#ibcon#read 6, iclass 26, count 0 2006.259.07:34:41.38#ibcon#end of sib2, iclass 26, count 0 2006.259.07:34:41.38#ibcon#*after write, iclass 26, count 0 2006.259.07:34:41.38#ibcon#*before return 0, iclass 26, count 0 2006.259.07:34:41.38#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.259.07:34:41.38#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.259.07:34:41.38#ibcon#about to clear, iclass 26 cls_cnt 0 2006.259.07:34:41.38#ibcon#cleared, iclass 26 cls_cnt 0 2006.259.07:34:41.38$vc4f8/vb=1,4 2006.259.07:34:41.38#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.259.07:34:41.38#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.259.07:34:41.38#ibcon#ireg 11 cls_cnt 2 2006.259.07:34:41.38#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.259.07:34:41.38#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.259.07:34:41.38#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.259.07:34:41.38#ibcon#enter wrdev, iclass 28, count 2 2006.259.07:34:41.38#ibcon#first serial, iclass 28, count 2 2006.259.07:34:41.38#ibcon#enter sib2, iclass 28, count 2 2006.259.07:34:41.38#ibcon#flushed, iclass 28, count 2 2006.259.07:34:41.38#ibcon#about to write, iclass 28, count 2 2006.259.07:34:41.38#ibcon#wrote, iclass 28, count 2 2006.259.07:34:41.38#ibcon#about to read 3, iclass 28, count 2 2006.259.07:34:41.40#ibcon#read 3, iclass 28, count 2 2006.259.07:34:41.40#ibcon#about to read 4, iclass 28, count 2 2006.259.07:34:41.40#ibcon#read 4, iclass 28, count 2 2006.259.07:34:41.40#ibcon#about to read 5, iclass 28, count 2 2006.259.07:34:41.40#ibcon#read 5, iclass 28, count 2 2006.259.07:34:41.40#ibcon#about to read 6, iclass 28, count 2 2006.259.07:34:41.40#ibcon#read 6, iclass 28, count 2 2006.259.07:34:41.40#ibcon#end of sib2, iclass 28, count 2 2006.259.07:34:41.40#ibcon#*mode == 0, iclass 28, count 2 2006.259.07:34:41.40#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.259.07:34:41.40#ibcon#[27=AT01-04\r\n] 2006.259.07:34:41.40#ibcon#*before write, iclass 28, count 2 2006.259.07:34:41.40#ibcon#enter sib2, iclass 28, count 2 2006.259.07:34:41.40#ibcon#flushed, iclass 28, count 2 2006.259.07:34:41.40#ibcon#about to write, iclass 28, count 2 2006.259.07:34:41.40#ibcon#wrote, iclass 28, count 2 2006.259.07:34:41.40#ibcon#about to read 3, iclass 28, count 2 2006.259.07:34:41.43#ibcon#read 3, iclass 28, count 2 2006.259.07:34:41.43#ibcon#about to read 4, iclass 28, count 2 2006.259.07:34:41.43#ibcon#read 4, iclass 28, count 2 2006.259.07:34:41.43#ibcon#about to read 5, iclass 28, count 2 2006.259.07:34:41.43#ibcon#read 5, iclass 28, count 2 2006.259.07:34:41.43#ibcon#about to read 6, iclass 28, count 2 2006.259.07:34:41.43#ibcon#read 6, iclass 28, count 2 2006.259.07:34:41.43#ibcon#end of sib2, iclass 28, count 2 2006.259.07:34:41.43#ibcon#*after write, iclass 28, count 2 2006.259.07:34:41.43#ibcon#*before return 0, iclass 28, count 2 2006.259.07:34:41.43#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.259.07:34:41.43#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.259.07:34:41.43#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.259.07:34:41.43#ibcon#ireg 7 cls_cnt 0 2006.259.07:34:41.43#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.259.07:34:41.55#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.259.07:34:41.55#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.259.07:34:41.55#ibcon#enter wrdev, iclass 28, count 0 2006.259.07:34:41.55#ibcon#first serial, iclass 28, count 0 2006.259.07:34:41.55#ibcon#enter sib2, iclass 28, count 0 2006.259.07:34:41.55#ibcon#flushed, iclass 28, count 0 2006.259.07:34:41.55#ibcon#about to write, iclass 28, count 0 2006.259.07:34:41.55#ibcon#wrote, iclass 28, count 0 2006.259.07:34:41.55#ibcon#about to read 3, iclass 28, count 0 2006.259.07:34:41.57#ibcon#read 3, iclass 28, count 0 2006.259.07:34:41.57#ibcon#about to read 4, iclass 28, count 0 2006.259.07:34:41.57#ibcon#read 4, iclass 28, count 0 2006.259.07:34:41.57#ibcon#about to read 5, iclass 28, count 0 2006.259.07:34:41.57#ibcon#read 5, iclass 28, count 0 2006.259.07:34:41.57#ibcon#about to read 6, iclass 28, count 0 2006.259.07:34:41.57#ibcon#read 6, iclass 28, count 0 2006.259.07:34:41.57#ibcon#end of sib2, iclass 28, count 0 2006.259.07:34:41.57#ibcon#*mode == 0, iclass 28, count 0 2006.259.07:34:41.57#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.259.07:34:41.57#ibcon#[27=USB\r\n] 2006.259.07:34:41.57#ibcon#*before write, iclass 28, count 0 2006.259.07:34:41.57#ibcon#enter sib2, iclass 28, count 0 2006.259.07:34:41.57#ibcon#flushed, iclass 28, count 0 2006.259.07:34:41.57#ibcon#about to write, iclass 28, count 0 2006.259.07:34:41.57#ibcon#wrote, iclass 28, count 0 2006.259.07:34:41.57#ibcon#about to read 3, iclass 28, count 0 2006.259.07:34:41.60#ibcon#read 3, iclass 28, count 0 2006.259.07:34:41.60#ibcon#about to read 4, iclass 28, count 0 2006.259.07:34:41.60#ibcon#read 4, iclass 28, count 0 2006.259.07:34:41.60#ibcon#about to read 5, iclass 28, count 0 2006.259.07:34:41.60#ibcon#read 5, iclass 28, count 0 2006.259.07:34:41.60#ibcon#about to read 6, iclass 28, count 0 2006.259.07:34:41.60#ibcon#read 6, iclass 28, count 0 2006.259.07:34:41.60#ibcon#end of sib2, iclass 28, count 0 2006.259.07:34:41.60#ibcon#*after write, iclass 28, count 0 2006.259.07:34:41.60#ibcon#*before return 0, iclass 28, count 0 2006.259.07:34:41.60#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.259.07:34:41.60#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.259.07:34:41.60#ibcon#about to clear, iclass 28 cls_cnt 0 2006.259.07:34:41.60#ibcon#cleared, iclass 28 cls_cnt 0 2006.259.07:34:41.60$vc4f8/vblo=2,640.99 2006.259.07:34:41.60#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.259.07:34:41.60#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.259.07:34:41.60#ibcon#ireg 17 cls_cnt 0 2006.259.07:34:41.60#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.259.07:34:41.60#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.259.07:34:41.60#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.259.07:34:41.60#ibcon#enter wrdev, iclass 30, count 0 2006.259.07:34:41.60#ibcon#first serial, iclass 30, count 0 2006.259.07:34:41.60#ibcon#enter sib2, iclass 30, count 0 2006.259.07:34:41.60#ibcon#flushed, iclass 30, count 0 2006.259.07:34:41.60#ibcon#about to write, iclass 30, count 0 2006.259.07:34:41.60#ibcon#wrote, iclass 30, count 0 2006.259.07:34:41.60#ibcon#about to read 3, iclass 30, count 0 2006.259.07:34:41.62#ibcon#read 3, iclass 30, count 0 2006.259.07:34:41.62#ibcon#about to read 4, iclass 30, count 0 2006.259.07:34:41.62#ibcon#read 4, iclass 30, count 0 2006.259.07:34:41.62#ibcon#about to read 5, iclass 30, count 0 2006.259.07:34:41.62#ibcon#read 5, iclass 30, count 0 2006.259.07:34:41.62#ibcon#about to read 6, iclass 30, count 0 2006.259.07:34:41.62#ibcon#read 6, iclass 30, count 0 2006.259.07:34:41.62#ibcon#end of sib2, iclass 30, count 0 2006.259.07:34:41.62#ibcon#*mode == 0, iclass 30, count 0 2006.259.07:34:41.62#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.259.07:34:41.62#ibcon#[28=FRQ=02,640.99\r\n] 2006.259.07:34:41.62#ibcon#*before write, iclass 30, count 0 2006.259.07:34:41.62#ibcon#enter sib2, iclass 30, count 0 2006.259.07:34:41.62#ibcon#flushed, iclass 30, count 0 2006.259.07:34:41.62#ibcon#about to write, iclass 30, count 0 2006.259.07:34:41.62#ibcon#wrote, iclass 30, count 0 2006.259.07:34:41.62#ibcon#about to read 3, iclass 30, count 0 2006.259.07:34:41.66#ibcon#read 3, iclass 30, count 0 2006.259.07:34:41.66#ibcon#about to read 4, iclass 30, count 0 2006.259.07:34:41.66#ibcon#read 4, iclass 30, count 0 2006.259.07:34:41.66#ibcon#about to read 5, iclass 30, count 0 2006.259.07:34:41.66#ibcon#read 5, iclass 30, count 0 2006.259.07:34:41.66#ibcon#about to read 6, iclass 30, count 0 2006.259.07:34:41.66#ibcon#read 6, iclass 30, count 0 2006.259.07:34:41.66#ibcon#end of sib2, iclass 30, count 0 2006.259.07:34:41.66#ibcon#*after write, iclass 30, count 0 2006.259.07:34:41.66#ibcon#*before return 0, iclass 30, count 0 2006.259.07:34:41.66#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.259.07:34:41.66#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.259.07:34:41.66#ibcon#about to clear, iclass 30 cls_cnt 0 2006.259.07:34:41.66#ibcon#cleared, iclass 30 cls_cnt 0 2006.259.07:34:41.66$vc4f8/vb=2,5 2006.259.07:34:41.66#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.259.07:34:41.66#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.259.07:34:41.66#ibcon#ireg 11 cls_cnt 2 2006.259.07:34:41.66#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.259.07:34:41.72#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.259.07:34:41.72#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.259.07:34:41.72#ibcon#enter wrdev, iclass 32, count 2 2006.259.07:34:41.72#ibcon#first serial, iclass 32, count 2 2006.259.07:34:41.72#ibcon#enter sib2, iclass 32, count 2 2006.259.07:34:41.72#ibcon#flushed, iclass 32, count 2 2006.259.07:34:41.72#ibcon#about to write, iclass 32, count 2 2006.259.07:34:41.72#ibcon#wrote, iclass 32, count 2 2006.259.07:34:41.72#ibcon#about to read 3, iclass 32, count 2 2006.259.07:34:41.75#ibcon#read 3, iclass 32, count 2 2006.259.07:34:41.75#ibcon#about to read 4, iclass 32, count 2 2006.259.07:34:41.75#ibcon#read 4, iclass 32, count 2 2006.259.07:34:41.75#ibcon#about to read 5, iclass 32, count 2 2006.259.07:34:41.75#ibcon#read 5, iclass 32, count 2 2006.259.07:34:41.75#ibcon#about to read 6, iclass 32, count 2 2006.259.07:34:41.75#ibcon#read 6, iclass 32, count 2 2006.259.07:34:41.75#ibcon#end of sib2, iclass 32, count 2 2006.259.07:34:41.75#ibcon#*mode == 0, iclass 32, count 2 2006.259.07:34:41.75#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.259.07:34:41.75#ibcon#[27=AT02-05\r\n] 2006.259.07:34:41.75#ibcon#*before write, iclass 32, count 2 2006.259.07:34:41.75#ibcon#enter sib2, iclass 32, count 2 2006.259.07:34:41.75#ibcon#flushed, iclass 32, count 2 2006.259.07:34:41.75#ibcon#about to write, iclass 32, count 2 2006.259.07:34:41.75#ibcon#wrote, iclass 32, count 2 2006.259.07:34:41.75#ibcon#about to read 3, iclass 32, count 2 2006.259.07:34:41.78#ibcon#read 3, iclass 32, count 2 2006.259.07:34:41.78#ibcon#about to read 4, iclass 32, count 2 2006.259.07:34:41.78#ibcon#read 4, iclass 32, count 2 2006.259.07:34:41.78#ibcon#about to read 5, iclass 32, count 2 2006.259.07:34:41.78#ibcon#read 5, iclass 32, count 2 2006.259.07:34:41.78#ibcon#about to read 6, iclass 32, count 2 2006.259.07:34:41.78#ibcon#read 6, iclass 32, count 2 2006.259.07:34:41.78#ibcon#end of sib2, iclass 32, count 2 2006.259.07:34:41.78#ibcon#*after write, iclass 32, count 2 2006.259.07:34:41.78#ibcon#*before return 0, iclass 32, count 2 2006.259.07:34:41.78#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.259.07:34:41.78#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.259.07:34:41.78#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.259.07:34:41.78#ibcon#ireg 7 cls_cnt 0 2006.259.07:34:41.78#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.259.07:34:41.90#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.259.07:34:41.90#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.259.07:34:41.90#ibcon#enter wrdev, iclass 32, count 0 2006.259.07:34:41.90#ibcon#first serial, iclass 32, count 0 2006.259.07:34:41.90#ibcon#enter sib2, iclass 32, count 0 2006.259.07:34:41.90#ibcon#flushed, iclass 32, count 0 2006.259.07:34:41.90#ibcon#about to write, iclass 32, count 0 2006.259.07:34:41.90#ibcon#wrote, iclass 32, count 0 2006.259.07:34:41.90#ibcon#about to read 3, iclass 32, count 0 2006.259.07:34:41.92#ibcon#read 3, iclass 32, count 0 2006.259.07:34:41.92#ibcon#about to read 4, iclass 32, count 0 2006.259.07:34:41.92#ibcon#read 4, iclass 32, count 0 2006.259.07:34:41.92#ibcon#about to read 5, iclass 32, count 0 2006.259.07:34:41.92#ibcon#read 5, iclass 32, count 0 2006.259.07:34:41.92#ibcon#about to read 6, iclass 32, count 0 2006.259.07:34:41.92#ibcon#read 6, iclass 32, count 0 2006.259.07:34:41.92#ibcon#end of sib2, iclass 32, count 0 2006.259.07:34:41.92#ibcon#*mode == 0, iclass 32, count 0 2006.259.07:34:41.92#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.259.07:34:41.92#ibcon#[27=USB\r\n] 2006.259.07:34:41.92#ibcon#*before write, iclass 32, count 0 2006.259.07:34:41.92#ibcon#enter sib2, iclass 32, count 0 2006.259.07:34:41.92#ibcon#flushed, iclass 32, count 0 2006.259.07:34:41.92#ibcon#about to write, iclass 32, count 0 2006.259.07:34:41.92#ibcon#wrote, iclass 32, count 0 2006.259.07:34:41.92#ibcon#about to read 3, iclass 32, count 0 2006.259.07:34:41.95#ibcon#read 3, iclass 32, count 0 2006.259.07:34:41.95#ibcon#about to read 4, iclass 32, count 0 2006.259.07:34:41.95#ibcon#read 4, iclass 32, count 0 2006.259.07:34:41.95#ibcon#about to read 5, iclass 32, count 0 2006.259.07:34:41.95#ibcon#read 5, iclass 32, count 0 2006.259.07:34:41.95#ibcon#about to read 6, iclass 32, count 0 2006.259.07:34:41.95#ibcon#read 6, iclass 32, count 0 2006.259.07:34:41.95#ibcon#end of sib2, iclass 32, count 0 2006.259.07:34:41.95#ibcon#*after write, iclass 32, count 0 2006.259.07:34:41.95#ibcon#*before return 0, iclass 32, count 0 2006.259.07:34:41.95#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.259.07:34:41.95#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.259.07:34:41.95#ibcon#about to clear, iclass 32 cls_cnt 0 2006.259.07:34:41.95#ibcon#cleared, iclass 32 cls_cnt 0 2006.259.07:34:41.95$vc4f8/vblo=3,656.99 2006.259.07:34:41.95#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.259.07:34:41.95#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.259.07:34:41.95#ibcon#ireg 17 cls_cnt 0 2006.259.07:34:41.95#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.259.07:34:41.95#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.259.07:34:41.95#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.259.07:34:41.95#ibcon#enter wrdev, iclass 34, count 0 2006.259.07:34:41.95#ibcon#first serial, iclass 34, count 0 2006.259.07:34:41.95#ibcon#enter sib2, iclass 34, count 0 2006.259.07:34:41.95#ibcon#flushed, iclass 34, count 0 2006.259.07:34:41.95#ibcon#about to write, iclass 34, count 0 2006.259.07:34:41.95#ibcon#wrote, iclass 34, count 0 2006.259.07:34:41.95#ibcon#about to read 3, iclass 34, count 0 2006.259.07:34:41.97#ibcon#read 3, iclass 34, count 0 2006.259.07:34:41.97#ibcon#about to read 4, iclass 34, count 0 2006.259.07:34:41.97#ibcon#read 4, iclass 34, count 0 2006.259.07:34:41.97#ibcon#about to read 5, iclass 34, count 0 2006.259.07:34:41.97#ibcon#read 5, iclass 34, count 0 2006.259.07:34:41.97#ibcon#about to read 6, iclass 34, count 0 2006.259.07:34:41.97#ibcon#read 6, iclass 34, count 0 2006.259.07:34:41.97#ibcon#end of sib2, iclass 34, count 0 2006.259.07:34:41.97#ibcon#*mode == 0, iclass 34, count 0 2006.259.07:34:41.97#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.259.07:34:41.97#ibcon#[28=FRQ=03,656.99\r\n] 2006.259.07:34:41.97#ibcon#*before write, iclass 34, count 0 2006.259.07:34:41.97#ibcon#enter sib2, iclass 34, count 0 2006.259.07:34:41.97#ibcon#flushed, iclass 34, count 0 2006.259.07:34:41.97#ibcon#about to write, iclass 34, count 0 2006.259.07:34:41.97#ibcon#wrote, iclass 34, count 0 2006.259.07:34:41.97#ibcon#about to read 3, iclass 34, count 0 2006.259.07:34:42.01#ibcon#read 3, iclass 34, count 0 2006.259.07:34:42.01#ibcon#about to read 4, iclass 34, count 0 2006.259.07:34:42.01#ibcon#read 4, iclass 34, count 0 2006.259.07:34:42.01#ibcon#about to read 5, iclass 34, count 0 2006.259.07:34:42.01#ibcon#read 5, iclass 34, count 0 2006.259.07:34:42.01#ibcon#about to read 6, iclass 34, count 0 2006.259.07:34:42.01#ibcon#read 6, iclass 34, count 0 2006.259.07:34:42.01#ibcon#end of sib2, iclass 34, count 0 2006.259.07:34:42.01#ibcon#*after write, iclass 34, count 0 2006.259.07:34:42.01#ibcon#*before return 0, iclass 34, count 0 2006.259.07:34:42.01#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.259.07:34:42.01#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.259.07:34:42.01#ibcon#about to clear, iclass 34 cls_cnt 0 2006.259.07:34:42.01#ibcon#cleared, iclass 34 cls_cnt 0 2006.259.07:34:42.01$vc4f8/vb=3,4 2006.259.07:34:42.01#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.259.07:34:42.01#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.259.07:34:42.01#ibcon#ireg 11 cls_cnt 2 2006.259.07:34:42.01#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.259.07:34:42.07#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.259.07:34:42.07#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.259.07:34:42.07#ibcon#enter wrdev, iclass 36, count 2 2006.259.07:34:42.07#ibcon#first serial, iclass 36, count 2 2006.259.07:34:42.07#ibcon#enter sib2, iclass 36, count 2 2006.259.07:34:42.07#ibcon#flushed, iclass 36, count 2 2006.259.07:34:42.07#ibcon#about to write, iclass 36, count 2 2006.259.07:34:42.07#ibcon#wrote, iclass 36, count 2 2006.259.07:34:42.07#ibcon#about to read 3, iclass 36, count 2 2006.259.07:34:42.09#ibcon#read 3, iclass 36, count 2 2006.259.07:34:42.09#ibcon#about to read 4, iclass 36, count 2 2006.259.07:34:42.09#ibcon#read 4, iclass 36, count 2 2006.259.07:34:42.09#ibcon#about to read 5, iclass 36, count 2 2006.259.07:34:42.09#ibcon#read 5, iclass 36, count 2 2006.259.07:34:42.09#ibcon#about to read 6, iclass 36, count 2 2006.259.07:34:42.09#ibcon#read 6, iclass 36, count 2 2006.259.07:34:42.09#ibcon#end of sib2, iclass 36, count 2 2006.259.07:34:42.09#ibcon#*mode == 0, iclass 36, count 2 2006.259.07:34:42.09#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.259.07:34:42.09#ibcon#[27=AT03-04\r\n] 2006.259.07:34:42.09#ibcon#*before write, iclass 36, count 2 2006.259.07:34:42.09#ibcon#enter sib2, iclass 36, count 2 2006.259.07:34:42.09#ibcon#flushed, iclass 36, count 2 2006.259.07:34:42.09#ibcon#about to write, iclass 36, count 2 2006.259.07:34:42.09#ibcon#wrote, iclass 36, count 2 2006.259.07:34:42.09#ibcon#about to read 3, iclass 36, count 2 2006.259.07:34:42.12#ibcon#read 3, iclass 36, count 2 2006.259.07:34:42.12#ibcon#about to read 4, iclass 36, count 2 2006.259.07:34:42.12#ibcon#read 4, iclass 36, count 2 2006.259.07:34:42.12#ibcon#about to read 5, iclass 36, count 2 2006.259.07:34:42.12#ibcon#read 5, iclass 36, count 2 2006.259.07:34:42.12#ibcon#about to read 6, iclass 36, count 2 2006.259.07:34:42.12#ibcon#read 6, iclass 36, count 2 2006.259.07:34:42.12#ibcon#end of sib2, iclass 36, count 2 2006.259.07:34:42.12#ibcon#*after write, iclass 36, count 2 2006.259.07:34:42.12#ibcon#*before return 0, iclass 36, count 2 2006.259.07:34:42.12#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.259.07:34:42.12#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.259.07:34:42.12#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.259.07:34:42.12#ibcon#ireg 7 cls_cnt 0 2006.259.07:34:42.12#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.259.07:34:42.24#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.259.07:34:42.24#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.259.07:34:42.24#ibcon#enter wrdev, iclass 36, count 0 2006.259.07:34:42.24#ibcon#first serial, iclass 36, count 0 2006.259.07:34:42.24#ibcon#enter sib2, iclass 36, count 0 2006.259.07:34:42.24#ibcon#flushed, iclass 36, count 0 2006.259.07:34:42.24#ibcon#about to write, iclass 36, count 0 2006.259.07:34:42.24#ibcon#wrote, iclass 36, count 0 2006.259.07:34:42.24#ibcon#about to read 3, iclass 36, count 0 2006.259.07:34:42.26#ibcon#read 3, iclass 36, count 0 2006.259.07:34:42.26#ibcon#about to read 4, iclass 36, count 0 2006.259.07:34:42.26#ibcon#read 4, iclass 36, count 0 2006.259.07:34:42.26#ibcon#about to read 5, iclass 36, count 0 2006.259.07:34:42.26#ibcon#read 5, iclass 36, count 0 2006.259.07:34:42.26#ibcon#about to read 6, iclass 36, count 0 2006.259.07:34:42.26#ibcon#read 6, iclass 36, count 0 2006.259.07:34:42.26#ibcon#end of sib2, iclass 36, count 0 2006.259.07:34:42.26#ibcon#*mode == 0, iclass 36, count 0 2006.259.07:34:42.26#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.259.07:34:42.26#ibcon#[27=USB\r\n] 2006.259.07:34:42.26#ibcon#*before write, iclass 36, count 0 2006.259.07:34:42.26#ibcon#enter sib2, iclass 36, count 0 2006.259.07:34:42.26#ibcon#flushed, iclass 36, count 0 2006.259.07:34:42.26#ibcon#about to write, iclass 36, count 0 2006.259.07:34:42.26#ibcon#wrote, iclass 36, count 0 2006.259.07:34:42.26#ibcon#about to read 3, iclass 36, count 0 2006.259.07:34:42.29#ibcon#read 3, iclass 36, count 0 2006.259.07:34:42.29#ibcon#about to read 4, iclass 36, count 0 2006.259.07:34:42.29#ibcon#read 4, iclass 36, count 0 2006.259.07:34:42.29#ibcon#about to read 5, iclass 36, count 0 2006.259.07:34:42.29#ibcon#read 5, iclass 36, count 0 2006.259.07:34:42.29#ibcon#about to read 6, iclass 36, count 0 2006.259.07:34:42.29#ibcon#read 6, iclass 36, count 0 2006.259.07:34:42.29#ibcon#end of sib2, iclass 36, count 0 2006.259.07:34:42.29#ibcon#*after write, iclass 36, count 0 2006.259.07:34:42.29#ibcon#*before return 0, iclass 36, count 0 2006.259.07:34:42.29#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.259.07:34:42.29#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.259.07:34:42.29#ibcon#about to clear, iclass 36 cls_cnt 0 2006.259.07:34:42.29#ibcon#cleared, iclass 36 cls_cnt 0 2006.259.07:34:42.29$vc4f8/vblo=4,712.99 2006.259.07:34:42.29#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.259.07:34:42.29#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.259.07:34:42.29#ibcon#ireg 17 cls_cnt 0 2006.259.07:34:42.29#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.259.07:34:42.29#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.259.07:34:42.29#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.259.07:34:42.29#ibcon#enter wrdev, iclass 38, count 0 2006.259.07:34:42.29#ibcon#first serial, iclass 38, count 0 2006.259.07:34:42.29#ibcon#enter sib2, iclass 38, count 0 2006.259.07:34:42.29#ibcon#flushed, iclass 38, count 0 2006.259.07:34:42.29#ibcon#about to write, iclass 38, count 0 2006.259.07:34:42.29#ibcon#wrote, iclass 38, count 0 2006.259.07:34:42.29#ibcon#about to read 3, iclass 38, count 0 2006.259.07:34:42.31#ibcon#read 3, iclass 38, count 0 2006.259.07:34:42.31#ibcon#about to read 4, iclass 38, count 0 2006.259.07:34:42.31#ibcon#read 4, iclass 38, count 0 2006.259.07:34:42.31#ibcon#about to read 5, iclass 38, count 0 2006.259.07:34:42.31#ibcon#read 5, iclass 38, count 0 2006.259.07:34:42.31#ibcon#about to read 6, iclass 38, count 0 2006.259.07:34:42.31#ibcon#read 6, iclass 38, count 0 2006.259.07:34:42.31#ibcon#end of sib2, iclass 38, count 0 2006.259.07:34:42.31#ibcon#*mode == 0, iclass 38, count 0 2006.259.07:34:42.31#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.259.07:34:42.31#ibcon#[28=FRQ=04,712.99\r\n] 2006.259.07:34:42.31#ibcon#*before write, iclass 38, count 0 2006.259.07:34:42.31#ibcon#enter sib2, iclass 38, count 0 2006.259.07:34:42.31#ibcon#flushed, iclass 38, count 0 2006.259.07:34:42.31#ibcon#about to write, iclass 38, count 0 2006.259.07:34:42.31#ibcon#wrote, iclass 38, count 0 2006.259.07:34:42.31#ibcon#about to read 3, iclass 38, count 0 2006.259.07:34:42.35#ibcon#read 3, iclass 38, count 0 2006.259.07:34:42.35#ibcon#about to read 4, iclass 38, count 0 2006.259.07:34:42.35#ibcon#read 4, iclass 38, count 0 2006.259.07:34:42.35#ibcon#about to read 5, iclass 38, count 0 2006.259.07:34:42.35#ibcon#read 5, iclass 38, count 0 2006.259.07:34:42.35#ibcon#about to read 6, iclass 38, count 0 2006.259.07:34:42.35#ibcon#read 6, iclass 38, count 0 2006.259.07:34:42.35#ibcon#end of sib2, iclass 38, count 0 2006.259.07:34:42.35#ibcon#*after write, iclass 38, count 0 2006.259.07:34:42.35#ibcon#*before return 0, iclass 38, count 0 2006.259.07:34:42.35#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.259.07:34:42.35#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.259.07:34:42.35#ibcon#about to clear, iclass 38 cls_cnt 0 2006.259.07:34:42.35#ibcon#cleared, iclass 38 cls_cnt 0 2006.259.07:34:42.35$vc4f8/vb=4,5 2006.259.07:34:42.35#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.259.07:34:42.35#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.259.07:34:42.35#ibcon#ireg 11 cls_cnt 2 2006.259.07:34:42.35#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.259.07:34:42.42#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.259.07:34:42.42#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.259.07:34:42.42#ibcon#enter wrdev, iclass 40, count 2 2006.259.07:34:42.42#ibcon#first serial, iclass 40, count 2 2006.259.07:34:42.42#ibcon#enter sib2, iclass 40, count 2 2006.259.07:34:42.42#ibcon#flushed, iclass 40, count 2 2006.259.07:34:42.42#ibcon#about to write, iclass 40, count 2 2006.259.07:34:42.42#ibcon#wrote, iclass 40, count 2 2006.259.07:34:42.42#ibcon#about to read 3, iclass 40, count 2 2006.259.07:34:42.43#ibcon#read 3, iclass 40, count 2 2006.259.07:34:42.43#ibcon#about to read 4, iclass 40, count 2 2006.259.07:34:42.43#ibcon#read 4, iclass 40, count 2 2006.259.07:34:42.43#ibcon#about to read 5, iclass 40, count 2 2006.259.07:34:42.43#ibcon#read 5, iclass 40, count 2 2006.259.07:34:42.43#ibcon#about to read 6, iclass 40, count 2 2006.259.07:34:42.43#ibcon#read 6, iclass 40, count 2 2006.259.07:34:42.43#ibcon#end of sib2, iclass 40, count 2 2006.259.07:34:42.43#ibcon#*mode == 0, iclass 40, count 2 2006.259.07:34:42.43#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.259.07:34:42.43#ibcon#[27=AT04-05\r\n] 2006.259.07:34:42.43#ibcon#*before write, iclass 40, count 2 2006.259.07:34:42.43#ibcon#enter sib2, iclass 40, count 2 2006.259.07:34:42.43#ibcon#flushed, iclass 40, count 2 2006.259.07:34:42.43#ibcon#about to write, iclass 40, count 2 2006.259.07:34:42.43#ibcon#wrote, iclass 40, count 2 2006.259.07:34:42.43#ibcon#about to read 3, iclass 40, count 2 2006.259.07:34:42.46#ibcon#read 3, iclass 40, count 2 2006.259.07:34:42.46#ibcon#about to read 4, iclass 40, count 2 2006.259.07:34:42.46#ibcon#read 4, iclass 40, count 2 2006.259.07:34:42.46#ibcon#about to read 5, iclass 40, count 2 2006.259.07:34:42.46#ibcon#read 5, iclass 40, count 2 2006.259.07:34:42.46#ibcon#about to read 6, iclass 40, count 2 2006.259.07:34:42.46#ibcon#read 6, iclass 40, count 2 2006.259.07:34:42.46#ibcon#end of sib2, iclass 40, count 2 2006.259.07:34:42.46#ibcon#*after write, iclass 40, count 2 2006.259.07:34:42.46#ibcon#*before return 0, iclass 40, count 2 2006.259.07:34:42.46#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.259.07:34:42.46#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.259.07:34:42.46#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.259.07:34:42.46#ibcon#ireg 7 cls_cnt 0 2006.259.07:34:42.46#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.259.07:34:42.58#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.259.07:34:42.58#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.259.07:34:42.58#ibcon#enter wrdev, iclass 40, count 0 2006.259.07:34:42.58#ibcon#first serial, iclass 40, count 0 2006.259.07:34:42.58#ibcon#enter sib2, iclass 40, count 0 2006.259.07:34:42.58#ibcon#flushed, iclass 40, count 0 2006.259.07:34:42.58#ibcon#about to write, iclass 40, count 0 2006.259.07:34:42.58#ibcon#wrote, iclass 40, count 0 2006.259.07:34:42.58#ibcon#about to read 3, iclass 40, count 0 2006.259.07:34:42.60#ibcon#read 3, iclass 40, count 0 2006.259.07:34:42.60#ibcon#about to read 4, iclass 40, count 0 2006.259.07:34:42.60#ibcon#read 4, iclass 40, count 0 2006.259.07:34:42.60#ibcon#about to read 5, iclass 40, count 0 2006.259.07:34:42.60#ibcon#read 5, iclass 40, count 0 2006.259.07:34:42.60#ibcon#about to read 6, iclass 40, count 0 2006.259.07:34:42.60#ibcon#read 6, iclass 40, count 0 2006.259.07:34:42.60#ibcon#end of sib2, iclass 40, count 0 2006.259.07:34:42.60#ibcon#*mode == 0, iclass 40, count 0 2006.259.07:34:42.60#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.259.07:34:42.60#ibcon#[27=USB\r\n] 2006.259.07:34:42.60#ibcon#*before write, iclass 40, count 0 2006.259.07:34:42.60#ibcon#enter sib2, iclass 40, count 0 2006.259.07:34:42.60#ibcon#flushed, iclass 40, count 0 2006.259.07:34:42.60#ibcon#about to write, iclass 40, count 0 2006.259.07:34:42.60#ibcon#wrote, iclass 40, count 0 2006.259.07:34:42.60#ibcon#about to read 3, iclass 40, count 0 2006.259.07:34:42.63#ibcon#read 3, iclass 40, count 0 2006.259.07:34:42.63#ibcon#about to read 4, iclass 40, count 0 2006.259.07:34:42.63#ibcon#read 4, iclass 40, count 0 2006.259.07:34:42.63#ibcon#about to read 5, iclass 40, count 0 2006.259.07:34:42.63#ibcon#read 5, iclass 40, count 0 2006.259.07:34:42.63#ibcon#about to read 6, iclass 40, count 0 2006.259.07:34:42.63#ibcon#read 6, iclass 40, count 0 2006.259.07:34:42.63#ibcon#end of sib2, iclass 40, count 0 2006.259.07:34:42.63#ibcon#*after write, iclass 40, count 0 2006.259.07:34:42.63#ibcon#*before return 0, iclass 40, count 0 2006.259.07:34:42.63#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.259.07:34:42.63#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.259.07:34:42.63#ibcon#about to clear, iclass 40 cls_cnt 0 2006.259.07:34:42.63#ibcon#cleared, iclass 40 cls_cnt 0 2006.259.07:34:42.63$vc4f8/vblo=5,744.99 2006.259.07:34:42.63#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.259.07:34:42.63#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.259.07:34:42.63#ibcon#ireg 17 cls_cnt 0 2006.259.07:34:42.63#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.259.07:34:42.63#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.259.07:34:42.63#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.259.07:34:42.63#ibcon#enter wrdev, iclass 4, count 0 2006.259.07:34:42.63#ibcon#first serial, iclass 4, count 0 2006.259.07:34:42.63#ibcon#enter sib2, iclass 4, count 0 2006.259.07:34:42.63#ibcon#flushed, iclass 4, count 0 2006.259.07:34:42.63#ibcon#about to write, iclass 4, count 0 2006.259.07:34:42.63#ibcon#wrote, iclass 4, count 0 2006.259.07:34:42.63#ibcon#about to read 3, iclass 4, count 0 2006.259.07:34:42.65#ibcon#read 3, iclass 4, count 0 2006.259.07:34:42.65#ibcon#about to read 4, iclass 4, count 0 2006.259.07:34:42.65#ibcon#read 4, iclass 4, count 0 2006.259.07:34:42.65#ibcon#about to read 5, iclass 4, count 0 2006.259.07:34:42.65#ibcon#read 5, iclass 4, count 0 2006.259.07:34:42.65#ibcon#about to read 6, iclass 4, count 0 2006.259.07:34:42.65#ibcon#read 6, iclass 4, count 0 2006.259.07:34:42.65#ibcon#end of sib2, iclass 4, count 0 2006.259.07:34:42.65#ibcon#*mode == 0, iclass 4, count 0 2006.259.07:34:42.65#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.259.07:34:42.65#ibcon#[28=FRQ=05,744.99\r\n] 2006.259.07:34:42.65#ibcon#*before write, iclass 4, count 0 2006.259.07:34:42.65#ibcon#enter sib2, iclass 4, count 0 2006.259.07:34:42.65#ibcon#flushed, iclass 4, count 0 2006.259.07:34:42.65#ibcon#about to write, iclass 4, count 0 2006.259.07:34:42.65#ibcon#wrote, iclass 4, count 0 2006.259.07:34:42.65#ibcon#about to read 3, iclass 4, count 0 2006.259.07:34:42.69#ibcon#read 3, iclass 4, count 0 2006.259.07:34:42.69#ibcon#about to read 4, iclass 4, count 0 2006.259.07:34:42.69#ibcon#read 4, iclass 4, count 0 2006.259.07:34:42.69#ibcon#about to read 5, iclass 4, count 0 2006.259.07:34:42.69#ibcon#read 5, iclass 4, count 0 2006.259.07:34:42.69#ibcon#about to read 6, iclass 4, count 0 2006.259.07:34:42.69#ibcon#read 6, iclass 4, count 0 2006.259.07:34:42.69#ibcon#end of sib2, iclass 4, count 0 2006.259.07:34:42.69#ibcon#*after write, iclass 4, count 0 2006.259.07:34:42.69#ibcon#*before return 0, iclass 4, count 0 2006.259.07:34:42.69#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.259.07:34:42.69#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.259.07:34:42.69#ibcon#about to clear, iclass 4 cls_cnt 0 2006.259.07:34:42.69#ibcon#cleared, iclass 4 cls_cnt 0 2006.259.07:34:42.69$vc4f8/vb=5,4 2006.259.07:34:42.69#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.259.07:34:42.69#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.259.07:34:42.69#ibcon#ireg 11 cls_cnt 2 2006.259.07:34:42.69#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.259.07:34:42.75#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.259.07:34:42.75#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.259.07:34:42.75#ibcon#enter wrdev, iclass 6, count 2 2006.259.07:34:42.75#ibcon#first serial, iclass 6, count 2 2006.259.07:34:42.75#ibcon#enter sib2, iclass 6, count 2 2006.259.07:34:42.75#ibcon#flushed, iclass 6, count 2 2006.259.07:34:42.75#ibcon#about to write, iclass 6, count 2 2006.259.07:34:42.75#ibcon#wrote, iclass 6, count 2 2006.259.07:34:42.75#ibcon#about to read 3, iclass 6, count 2 2006.259.07:34:42.77#ibcon#read 3, iclass 6, count 2 2006.259.07:34:42.77#ibcon#about to read 4, iclass 6, count 2 2006.259.07:34:42.77#ibcon#read 4, iclass 6, count 2 2006.259.07:34:42.77#ibcon#about to read 5, iclass 6, count 2 2006.259.07:34:42.77#ibcon#read 5, iclass 6, count 2 2006.259.07:34:42.77#ibcon#about to read 6, iclass 6, count 2 2006.259.07:34:42.77#ibcon#read 6, iclass 6, count 2 2006.259.07:34:42.77#ibcon#end of sib2, iclass 6, count 2 2006.259.07:34:42.77#ibcon#*mode == 0, iclass 6, count 2 2006.259.07:34:42.77#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.259.07:34:42.77#ibcon#[27=AT05-04\r\n] 2006.259.07:34:42.77#ibcon#*before write, iclass 6, count 2 2006.259.07:34:42.77#ibcon#enter sib2, iclass 6, count 2 2006.259.07:34:42.77#ibcon#flushed, iclass 6, count 2 2006.259.07:34:42.77#ibcon#about to write, iclass 6, count 2 2006.259.07:34:42.77#ibcon#wrote, iclass 6, count 2 2006.259.07:34:42.77#ibcon#about to read 3, iclass 6, count 2 2006.259.07:34:42.80#ibcon#read 3, iclass 6, count 2 2006.259.07:34:42.80#ibcon#about to read 4, iclass 6, count 2 2006.259.07:34:42.80#ibcon#read 4, iclass 6, count 2 2006.259.07:34:42.80#ibcon#about to read 5, iclass 6, count 2 2006.259.07:34:42.80#ibcon#read 5, iclass 6, count 2 2006.259.07:34:42.80#ibcon#about to read 6, iclass 6, count 2 2006.259.07:34:42.80#ibcon#read 6, iclass 6, count 2 2006.259.07:34:42.80#ibcon#end of sib2, iclass 6, count 2 2006.259.07:34:42.80#ibcon#*after write, iclass 6, count 2 2006.259.07:34:42.80#ibcon#*before return 0, iclass 6, count 2 2006.259.07:34:42.80#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.259.07:34:42.80#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.259.07:34:42.80#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.259.07:34:42.80#ibcon#ireg 7 cls_cnt 0 2006.259.07:34:42.80#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.259.07:34:42.92#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.259.07:34:42.92#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.259.07:34:42.92#ibcon#enter wrdev, iclass 6, count 0 2006.259.07:34:42.92#ibcon#first serial, iclass 6, count 0 2006.259.07:34:42.92#ibcon#enter sib2, iclass 6, count 0 2006.259.07:34:42.92#ibcon#flushed, iclass 6, count 0 2006.259.07:34:42.92#ibcon#about to write, iclass 6, count 0 2006.259.07:34:42.92#ibcon#wrote, iclass 6, count 0 2006.259.07:34:42.92#ibcon#about to read 3, iclass 6, count 0 2006.259.07:34:42.94#ibcon#read 3, iclass 6, count 0 2006.259.07:34:42.94#ibcon#about to read 4, iclass 6, count 0 2006.259.07:34:42.94#ibcon#read 4, iclass 6, count 0 2006.259.07:34:42.94#ibcon#about to read 5, iclass 6, count 0 2006.259.07:34:42.94#ibcon#read 5, iclass 6, count 0 2006.259.07:34:42.94#ibcon#about to read 6, iclass 6, count 0 2006.259.07:34:42.94#ibcon#read 6, iclass 6, count 0 2006.259.07:34:42.94#ibcon#end of sib2, iclass 6, count 0 2006.259.07:34:42.94#ibcon#*mode == 0, iclass 6, count 0 2006.259.07:34:42.94#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.259.07:34:42.94#ibcon#[27=USB\r\n] 2006.259.07:34:42.94#ibcon#*before write, iclass 6, count 0 2006.259.07:34:42.94#ibcon#enter sib2, iclass 6, count 0 2006.259.07:34:42.94#ibcon#flushed, iclass 6, count 0 2006.259.07:34:42.94#ibcon#about to write, iclass 6, count 0 2006.259.07:34:42.94#ibcon#wrote, iclass 6, count 0 2006.259.07:34:42.94#ibcon#about to read 3, iclass 6, count 0 2006.259.07:34:42.97#ibcon#read 3, iclass 6, count 0 2006.259.07:34:42.97#ibcon#about to read 4, iclass 6, count 0 2006.259.07:34:42.97#ibcon#read 4, iclass 6, count 0 2006.259.07:34:42.97#ibcon#about to read 5, iclass 6, count 0 2006.259.07:34:42.97#ibcon#read 5, iclass 6, count 0 2006.259.07:34:42.97#ibcon#about to read 6, iclass 6, count 0 2006.259.07:34:42.97#ibcon#read 6, iclass 6, count 0 2006.259.07:34:42.97#ibcon#end of sib2, iclass 6, count 0 2006.259.07:34:42.97#ibcon#*after write, iclass 6, count 0 2006.259.07:34:42.97#ibcon#*before return 0, iclass 6, count 0 2006.259.07:34:42.97#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.259.07:34:42.97#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.259.07:34:42.97#ibcon#about to clear, iclass 6 cls_cnt 0 2006.259.07:34:42.97#ibcon#cleared, iclass 6 cls_cnt 0 2006.259.07:34:42.97$vc4f8/vblo=6,752.99 2006.259.07:34:42.97#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.259.07:34:42.97#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.259.07:34:42.97#ibcon#ireg 17 cls_cnt 0 2006.259.07:34:42.97#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.259.07:34:42.97#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.259.07:34:42.97#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.259.07:34:42.97#ibcon#enter wrdev, iclass 10, count 0 2006.259.07:34:42.97#ibcon#first serial, iclass 10, count 0 2006.259.07:34:42.97#ibcon#enter sib2, iclass 10, count 0 2006.259.07:34:42.97#ibcon#flushed, iclass 10, count 0 2006.259.07:34:42.97#ibcon#about to write, iclass 10, count 0 2006.259.07:34:42.97#ibcon#wrote, iclass 10, count 0 2006.259.07:34:42.97#ibcon#about to read 3, iclass 10, count 0 2006.259.07:34:42.99#ibcon#read 3, iclass 10, count 0 2006.259.07:34:42.99#ibcon#about to read 4, iclass 10, count 0 2006.259.07:34:42.99#ibcon#read 4, iclass 10, count 0 2006.259.07:34:42.99#ibcon#about to read 5, iclass 10, count 0 2006.259.07:34:42.99#ibcon#read 5, iclass 10, count 0 2006.259.07:34:42.99#ibcon#about to read 6, iclass 10, count 0 2006.259.07:34:42.99#ibcon#read 6, iclass 10, count 0 2006.259.07:34:42.99#ibcon#end of sib2, iclass 10, count 0 2006.259.07:34:42.99#ibcon#*mode == 0, iclass 10, count 0 2006.259.07:34:42.99#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.259.07:34:42.99#ibcon#[28=FRQ=06,752.99\r\n] 2006.259.07:34:42.99#ibcon#*before write, iclass 10, count 0 2006.259.07:34:42.99#ibcon#enter sib2, iclass 10, count 0 2006.259.07:34:42.99#ibcon#flushed, iclass 10, count 0 2006.259.07:34:42.99#ibcon#about to write, iclass 10, count 0 2006.259.07:34:42.99#ibcon#wrote, iclass 10, count 0 2006.259.07:34:42.99#ibcon#about to read 3, iclass 10, count 0 2006.259.07:34:43.03#ibcon#read 3, iclass 10, count 0 2006.259.07:34:43.03#ibcon#about to read 4, iclass 10, count 0 2006.259.07:34:43.03#ibcon#read 4, iclass 10, count 0 2006.259.07:34:43.03#ibcon#about to read 5, iclass 10, count 0 2006.259.07:34:43.03#ibcon#read 5, iclass 10, count 0 2006.259.07:34:43.03#ibcon#about to read 6, iclass 10, count 0 2006.259.07:34:43.03#ibcon#read 6, iclass 10, count 0 2006.259.07:34:43.03#ibcon#end of sib2, iclass 10, count 0 2006.259.07:34:43.03#ibcon#*after write, iclass 10, count 0 2006.259.07:34:43.03#ibcon#*before return 0, iclass 10, count 0 2006.259.07:34:43.03#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.259.07:34:43.03#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.259.07:34:43.03#ibcon#about to clear, iclass 10 cls_cnt 0 2006.259.07:34:43.03#ibcon#cleared, iclass 10 cls_cnt 0 2006.259.07:34:43.03$vc4f8/vb=6,4 2006.259.07:34:43.03#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.259.07:34:43.03#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.259.07:34:43.03#ibcon#ireg 11 cls_cnt 2 2006.259.07:34:43.03#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.259.07:34:43.10#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.259.07:34:43.10#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.259.07:34:43.10#ibcon#enter wrdev, iclass 12, count 2 2006.259.07:34:43.10#ibcon#first serial, iclass 12, count 2 2006.259.07:34:43.10#ibcon#enter sib2, iclass 12, count 2 2006.259.07:34:43.10#ibcon#flushed, iclass 12, count 2 2006.259.07:34:43.10#ibcon#about to write, iclass 12, count 2 2006.259.07:34:43.10#ibcon#wrote, iclass 12, count 2 2006.259.07:34:43.10#ibcon#about to read 3, iclass 12, count 2 2006.259.07:34:43.11#ibcon#read 3, iclass 12, count 2 2006.259.07:34:43.11#ibcon#about to read 4, iclass 12, count 2 2006.259.07:34:43.11#ibcon#read 4, iclass 12, count 2 2006.259.07:34:43.11#ibcon#about to read 5, iclass 12, count 2 2006.259.07:34:43.11#ibcon#read 5, iclass 12, count 2 2006.259.07:34:43.11#ibcon#about to read 6, iclass 12, count 2 2006.259.07:34:43.11#ibcon#read 6, iclass 12, count 2 2006.259.07:34:43.11#ibcon#end of sib2, iclass 12, count 2 2006.259.07:34:43.11#ibcon#*mode == 0, iclass 12, count 2 2006.259.07:34:43.11#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.259.07:34:43.11#ibcon#[27=AT06-04\r\n] 2006.259.07:34:43.11#ibcon#*before write, iclass 12, count 2 2006.259.07:34:43.11#ibcon#enter sib2, iclass 12, count 2 2006.259.07:34:43.11#ibcon#flushed, iclass 12, count 2 2006.259.07:34:43.11#ibcon#about to write, iclass 12, count 2 2006.259.07:34:43.11#ibcon#wrote, iclass 12, count 2 2006.259.07:34:43.11#ibcon#about to read 3, iclass 12, count 2 2006.259.07:34:43.14#ibcon#read 3, iclass 12, count 2 2006.259.07:34:43.14#ibcon#about to read 4, iclass 12, count 2 2006.259.07:34:43.14#ibcon#read 4, iclass 12, count 2 2006.259.07:34:43.14#ibcon#about to read 5, iclass 12, count 2 2006.259.07:34:43.14#ibcon#read 5, iclass 12, count 2 2006.259.07:34:43.14#ibcon#about to read 6, iclass 12, count 2 2006.259.07:34:43.14#ibcon#read 6, iclass 12, count 2 2006.259.07:34:43.14#ibcon#end of sib2, iclass 12, count 2 2006.259.07:34:43.14#ibcon#*after write, iclass 12, count 2 2006.259.07:34:43.14#ibcon#*before return 0, iclass 12, count 2 2006.259.07:34:43.14#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.259.07:34:43.14#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.259.07:34:43.14#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.259.07:34:43.14#ibcon#ireg 7 cls_cnt 0 2006.259.07:34:43.14#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.259.07:34:43.26#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.259.07:34:43.26#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.259.07:34:43.26#ibcon#enter wrdev, iclass 12, count 0 2006.259.07:34:43.26#ibcon#first serial, iclass 12, count 0 2006.259.07:34:43.26#ibcon#enter sib2, iclass 12, count 0 2006.259.07:34:43.26#ibcon#flushed, iclass 12, count 0 2006.259.07:34:43.26#ibcon#about to write, iclass 12, count 0 2006.259.07:34:43.26#ibcon#wrote, iclass 12, count 0 2006.259.07:34:43.26#ibcon#about to read 3, iclass 12, count 0 2006.259.07:34:43.28#ibcon#read 3, iclass 12, count 0 2006.259.07:34:43.28#ibcon#about to read 4, iclass 12, count 0 2006.259.07:34:43.28#ibcon#read 4, iclass 12, count 0 2006.259.07:34:43.28#ibcon#about to read 5, iclass 12, count 0 2006.259.07:34:43.28#ibcon#read 5, iclass 12, count 0 2006.259.07:34:43.28#ibcon#about to read 6, iclass 12, count 0 2006.259.07:34:43.28#ibcon#read 6, iclass 12, count 0 2006.259.07:34:43.28#ibcon#end of sib2, iclass 12, count 0 2006.259.07:34:43.28#ibcon#*mode == 0, iclass 12, count 0 2006.259.07:34:43.28#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.259.07:34:43.28#ibcon#[27=USB\r\n] 2006.259.07:34:43.28#ibcon#*before write, iclass 12, count 0 2006.259.07:34:43.28#ibcon#enter sib2, iclass 12, count 0 2006.259.07:34:43.28#ibcon#flushed, iclass 12, count 0 2006.259.07:34:43.28#ibcon#about to write, iclass 12, count 0 2006.259.07:34:43.28#ibcon#wrote, iclass 12, count 0 2006.259.07:34:43.28#ibcon#about to read 3, iclass 12, count 0 2006.259.07:34:43.31#ibcon#read 3, iclass 12, count 0 2006.259.07:34:43.31#ibcon#about to read 4, iclass 12, count 0 2006.259.07:34:43.31#ibcon#read 4, iclass 12, count 0 2006.259.07:34:43.31#ibcon#about to read 5, iclass 12, count 0 2006.259.07:34:43.31#ibcon#read 5, iclass 12, count 0 2006.259.07:34:43.31#ibcon#about to read 6, iclass 12, count 0 2006.259.07:34:43.31#ibcon#read 6, iclass 12, count 0 2006.259.07:34:43.31#ibcon#end of sib2, iclass 12, count 0 2006.259.07:34:43.31#ibcon#*after write, iclass 12, count 0 2006.259.07:34:43.31#ibcon#*before return 0, iclass 12, count 0 2006.259.07:34:43.31#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.259.07:34:43.31#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.259.07:34:43.31#ibcon#about to clear, iclass 12 cls_cnt 0 2006.259.07:34:43.31#ibcon#cleared, iclass 12 cls_cnt 0 2006.259.07:34:43.31$vc4f8/vabw=wide 2006.259.07:34:43.31#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.259.07:34:43.31#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.259.07:34:43.31#ibcon#ireg 8 cls_cnt 0 2006.259.07:34:43.31#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.259.07:34:43.31#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.259.07:34:43.31#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.259.07:34:43.31#ibcon#enter wrdev, iclass 14, count 0 2006.259.07:34:43.31#ibcon#first serial, iclass 14, count 0 2006.259.07:34:43.31#ibcon#enter sib2, iclass 14, count 0 2006.259.07:34:43.31#ibcon#flushed, iclass 14, count 0 2006.259.07:34:43.31#ibcon#about to write, iclass 14, count 0 2006.259.07:34:43.31#ibcon#wrote, iclass 14, count 0 2006.259.07:34:43.31#ibcon#about to read 3, iclass 14, count 0 2006.259.07:34:43.33#ibcon#read 3, iclass 14, count 0 2006.259.07:34:43.33#ibcon#about to read 4, iclass 14, count 0 2006.259.07:34:43.33#ibcon#read 4, iclass 14, count 0 2006.259.07:34:43.33#ibcon#about to read 5, iclass 14, count 0 2006.259.07:34:43.33#ibcon#read 5, iclass 14, count 0 2006.259.07:34:43.33#ibcon#about to read 6, iclass 14, count 0 2006.259.07:34:43.33#ibcon#read 6, iclass 14, count 0 2006.259.07:34:43.33#ibcon#end of sib2, iclass 14, count 0 2006.259.07:34:43.33#ibcon#*mode == 0, iclass 14, count 0 2006.259.07:34:43.33#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.259.07:34:43.33#ibcon#[25=BW32\r\n] 2006.259.07:34:43.33#ibcon#*before write, iclass 14, count 0 2006.259.07:34:43.33#ibcon#enter sib2, iclass 14, count 0 2006.259.07:34:43.33#ibcon#flushed, iclass 14, count 0 2006.259.07:34:43.33#ibcon#about to write, iclass 14, count 0 2006.259.07:34:43.33#ibcon#wrote, iclass 14, count 0 2006.259.07:34:43.33#ibcon#about to read 3, iclass 14, count 0 2006.259.07:34:43.36#ibcon#read 3, iclass 14, count 0 2006.259.07:34:43.36#ibcon#about to read 4, iclass 14, count 0 2006.259.07:34:43.36#ibcon#read 4, iclass 14, count 0 2006.259.07:34:43.36#ibcon#about to read 5, iclass 14, count 0 2006.259.07:34:43.36#ibcon#read 5, iclass 14, count 0 2006.259.07:34:43.36#ibcon#about to read 6, iclass 14, count 0 2006.259.07:34:43.36#ibcon#read 6, iclass 14, count 0 2006.259.07:34:43.36#ibcon#end of sib2, iclass 14, count 0 2006.259.07:34:43.36#ibcon#*after write, iclass 14, count 0 2006.259.07:34:43.36#ibcon#*before return 0, iclass 14, count 0 2006.259.07:34:43.36#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.259.07:34:43.36#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.259.07:34:43.36#ibcon#about to clear, iclass 14 cls_cnt 0 2006.259.07:34:43.36#ibcon#cleared, iclass 14 cls_cnt 0 2006.259.07:34:43.36$vc4f8/vbbw=wide 2006.259.07:34:43.36#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.259.07:34:43.36#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.259.07:34:43.36#ibcon#ireg 8 cls_cnt 0 2006.259.07:34:43.36#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.259.07:34:43.44#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.259.07:34:43.44#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.259.07:34:43.44#ibcon#enter wrdev, iclass 16, count 0 2006.259.07:34:43.44#ibcon#first serial, iclass 16, count 0 2006.259.07:34:43.44#ibcon#enter sib2, iclass 16, count 0 2006.259.07:34:43.44#ibcon#flushed, iclass 16, count 0 2006.259.07:34:43.44#ibcon#about to write, iclass 16, count 0 2006.259.07:34:43.44#ibcon#wrote, iclass 16, count 0 2006.259.07:34:43.44#ibcon#about to read 3, iclass 16, count 0 2006.259.07:34:43.45#ibcon#read 3, iclass 16, count 0 2006.259.07:34:43.45#ibcon#about to read 4, iclass 16, count 0 2006.259.07:34:43.45#ibcon#read 4, iclass 16, count 0 2006.259.07:34:43.45#ibcon#about to read 5, iclass 16, count 0 2006.259.07:34:43.45#ibcon#read 5, iclass 16, count 0 2006.259.07:34:43.45#ibcon#about to read 6, iclass 16, count 0 2006.259.07:34:43.45#ibcon#read 6, iclass 16, count 0 2006.259.07:34:43.45#ibcon#end of sib2, iclass 16, count 0 2006.259.07:34:43.45#ibcon#*mode == 0, iclass 16, count 0 2006.259.07:34:43.45#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.259.07:34:43.45#ibcon#[27=BW32\r\n] 2006.259.07:34:43.45#ibcon#*before write, iclass 16, count 0 2006.259.07:34:43.45#ibcon#enter sib2, iclass 16, count 0 2006.259.07:34:43.45#ibcon#flushed, iclass 16, count 0 2006.259.07:34:43.45#ibcon#about to write, iclass 16, count 0 2006.259.07:34:43.45#ibcon#wrote, iclass 16, count 0 2006.259.07:34:43.45#ibcon#about to read 3, iclass 16, count 0 2006.259.07:34:43.48#ibcon#read 3, iclass 16, count 0 2006.259.07:34:43.48#ibcon#about to read 4, iclass 16, count 0 2006.259.07:34:43.48#ibcon#read 4, iclass 16, count 0 2006.259.07:34:43.48#ibcon#about to read 5, iclass 16, count 0 2006.259.07:34:43.48#ibcon#read 5, iclass 16, count 0 2006.259.07:34:43.48#ibcon#about to read 6, iclass 16, count 0 2006.259.07:34:43.48#ibcon#read 6, iclass 16, count 0 2006.259.07:34:43.48#ibcon#end of sib2, iclass 16, count 0 2006.259.07:34:43.48#ibcon#*after write, iclass 16, count 0 2006.259.07:34:43.48#ibcon#*before return 0, iclass 16, count 0 2006.259.07:34:43.48#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.259.07:34:43.48#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.259.07:34:43.48#ibcon#about to clear, iclass 16 cls_cnt 0 2006.259.07:34:43.48#ibcon#cleared, iclass 16 cls_cnt 0 2006.259.07:34:43.48$4f8m12a/ifd4f 2006.259.07:34:43.48$ifd4f/lo= 2006.259.07:34:43.48$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.259.07:34:43.48$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.259.07:34:43.48$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.259.07:34:43.48$ifd4f/patch= 2006.259.07:34:43.48$ifd4f/patch=lo1,a1,a2,a3,a4 2006.259.07:34:43.48$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.259.07:34:43.48$ifd4f/patch=lo3,a5,a6,a7,a8 2006.259.07:34:43.48$4f8m12a/"form=m,16.000,1:2 2006.259.07:34:43.48$4f8m12a/"tpicd 2006.259.07:34:43.48$4f8m12a/echo=off 2006.259.07:34:43.48$4f8m12a/xlog=off 2006.259.07:34:43.48:!2006.259.07:35:10 2006.259.07:34:53.14#trakl#Source acquired 2006.259.07:34:55.14#flagr#flagr/antenna,acquired 2006.259.07:35:10.00:preob 2006.259.07:35:11.14/onsource/TRACKING 2006.259.07:35:11.14:!2006.259.07:35:20 2006.259.07:35:20.00:data_valid=on 2006.259.07:35:20.00:midob 2006.259.07:35:20.14/onsource/TRACKING 2006.259.07:35:20.14/wx/22.34,1012.8,84 2006.259.07:35:20.32/cable/+6.4578E-03 2006.259.07:35:21.41/va/01,08,usb,yes,31,32 2006.259.07:35:21.41/va/02,07,usb,yes,30,32 2006.259.07:35:21.41/va/03,08,usb,yes,23,23 2006.259.07:35:21.41/va/04,07,usb,yes,32,34 2006.259.07:35:21.41/va/05,07,usb,yes,35,37 2006.259.07:35:21.41/va/06,06,usb,yes,34,34 2006.259.07:35:21.41/va/07,06,usb,yes,35,34 2006.259.07:35:21.41/va/08,06,usb,yes,37,36 2006.259.07:35:21.64/valo/01,532.99,yes,locked 2006.259.07:35:21.64/valo/02,572.99,yes,locked 2006.259.07:35:21.64/valo/03,672.99,yes,locked 2006.259.07:35:21.64/valo/04,832.99,yes,locked 2006.259.07:35:21.64/valo/05,652.99,yes,locked 2006.259.07:35:21.64/valo/06,772.99,yes,locked 2006.259.07:35:21.64/valo/07,832.99,yes,locked 2006.259.07:35:21.64/valo/08,852.99,yes,locked 2006.259.07:35:22.73/vb/01,04,usb,yes,30,29 2006.259.07:35:22.73/vb/02,05,usb,yes,28,29 2006.259.07:35:22.73/vb/03,04,usb,yes,28,32 2006.259.07:35:22.73/vb/04,05,usb,yes,26,26 2006.259.07:35:22.73/vb/05,04,usb,yes,28,32 2006.259.07:35:22.73/vb/06,04,usb,yes,29,31 2006.259.07:35:22.73/vb/07,04,usb,yes,31,31 2006.259.07:35:22.73/vb/08,04,usb,yes,28,32 2006.259.07:35:22.96/vblo/01,632.99,yes,locked 2006.259.07:35:22.96/vblo/02,640.99,yes,locked 2006.259.07:35:22.96/vblo/03,656.99,yes,locked 2006.259.07:35:22.96/vblo/04,712.99,yes,locked 2006.259.07:35:22.96/vblo/05,744.99,yes,locked 2006.259.07:35:22.96/vblo/06,752.99,yes,locked 2006.259.07:35:22.96/vblo/07,734.99,yes,locked 2006.259.07:35:22.96/vblo/08,744.99,yes,locked 2006.259.07:35:23.11/vabw/8 2006.259.07:35:23.26/vbbw/8 2006.259.07:35:23.35/xfe/off,on,15.2 2006.259.07:35:23.72/ifatt/23,28,28,28 2006.259.07:35:24.08/fmout-gps/S +4.51E-07 2006.259.07:35:24.12:!2006.259.07:36:20 2006.259.07:36:20.00:data_valid=off 2006.259.07:36:20.00:postob 2006.259.07:36:20.17/cable/+6.4593E-03 2006.259.07:36:20.17/wx/22.33,1012.8,84 2006.259.07:36:21.08/fmout-gps/S +4.51E-07 2006.259.07:36:21.08:scan_name=259-0737,k06259,60 2006.259.07:36:21.08:source=1418+546,141946.60,542314.8,2000.0,ccw 2006.259.07:36:21.16#flagr#flagr/antenna,new-source 2006.259.07:36:22.14:checkk5 2006.259.07:36:22.57/chk_autoobs//k5ts1/ autoobs is running! 2006.259.07:36:23.00/chk_autoobs//k5ts2/ autoobs is running! 2006.259.07:36:23.44/chk_autoobs//k5ts3/ autoobs is running! 2006.259.07:36:23.92/chk_autoobs//k5ts4/ autoobs is running! 2006.259.07:36:24.37/chk_obsdata//k5ts1/T2590735??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.259.07:36:24.77/chk_obsdata//k5ts2/T2590735??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.259.07:36:25.22/chk_obsdata//k5ts3/T2590735??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.259.07:36:25.63/chk_obsdata//k5ts4/T2590735??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.259.07:36:26.78/k5log//k5ts1_log_newline 2006.259.07:36:27.70/k5log//k5ts2_log_newline 2006.259.07:36:28.69/k5log//k5ts3_log_newline 2006.259.07:36:29.46/k5log//k5ts4_log_newline 2006.259.07:36:29.48/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.259.07:36:29.48:4f8m12a=1 2006.259.07:36:29.48$4f8m12a/echo=on 2006.259.07:36:29.48$4f8m12a/pcalon 2006.259.07:36:29.48$pcalon/"no phase cal control is implemented here 2006.259.07:36:29.48$4f8m12a/"tpicd=stop 2006.259.07:36:29.48$4f8m12a/vc4f8 2006.259.07:36:29.48$vc4f8/valo=1,532.99 2006.259.07:36:29.48#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.259.07:36:29.48#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.259.07:36:29.48#ibcon#ireg 17 cls_cnt 0 2006.259.07:36:29.48#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.259.07:36:29.48#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.259.07:36:29.48#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.259.07:36:29.48#ibcon#enter wrdev, iclass 23, count 0 2006.259.07:36:29.48#ibcon#first serial, iclass 23, count 0 2006.259.07:36:29.48#ibcon#enter sib2, iclass 23, count 0 2006.259.07:36:29.48#ibcon#flushed, iclass 23, count 0 2006.259.07:36:29.48#ibcon#about to write, iclass 23, count 0 2006.259.07:36:29.48#ibcon#wrote, iclass 23, count 0 2006.259.07:36:29.48#ibcon#about to read 3, iclass 23, count 0 2006.259.07:36:29.50#ibcon#read 3, iclass 23, count 0 2006.259.07:36:29.50#ibcon#about to read 4, iclass 23, count 0 2006.259.07:36:29.50#ibcon#read 4, iclass 23, count 0 2006.259.07:36:29.50#ibcon#about to read 5, iclass 23, count 0 2006.259.07:36:29.50#ibcon#read 5, iclass 23, count 0 2006.259.07:36:29.50#ibcon#about to read 6, iclass 23, count 0 2006.259.07:36:29.50#ibcon#read 6, iclass 23, count 0 2006.259.07:36:29.50#ibcon#end of sib2, iclass 23, count 0 2006.259.07:36:29.50#ibcon#*mode == 0, iclass 23, count 0 2006.259.07:36:29.50#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.259.07:36:29.50#ibcon#[26=FRQ=01,532.99\r\n] 2006.259.07:36:29.50#ibcon#*before write, iclass 23, count 0 2006.259.07:36:29.50#ibcon#enter sib2, iclass 23, count 0 2006.259.07:36:29.50#ibcon#flushed, iclass 23, count 0 2006.259.07:36:29.50#ibcon#about to write, iclass 23, count 0 2006.259.07:36:29.50#ibcon#wrote, iclass 23, count 0 2006.259.07:36:29.50#ibcon#about to read 3, iclass 23, count 0 2006.259.07:36:29.55#ibcon#read 3, iclass 23, count 0 2006.259.07:36:29.55#ibcon#about to read 4, iclass 23, count 0 2006.259.07:36:29.55#ibcon#read 4, iclass 23, count 0 2006.259.07:36:29.55#ibcon#about to read 5, iclass 23, count 0 2006.259.07:36:29.55#ibcon#read 5, iclass 23, count 0 2006.259.07:36:29.55#ibcon#about to read 6, iclass 23, count 0 2006.259.07:36:29.55#ibcon#read 6, iclass 23, count 0 2006.259.07:36:29.55#ibcon#end of sib2, iclass 23, count 0 2006.259.07:36:29.55#ibcon#*after write, iclass 23, count 0 2006.259.07:36:29.55#ibcon#*before return 0, iclass 23, count 0 2006.259.07:36:29.55#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.259.07:36:29.55#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.259.07:36:29.55#ibcon#about to clear, iclass 23 cls_cnt 0 2006.259.07:36:29.55#ibcon#cleared, iclass 23 cls_cnt 0 2006.259.07:36:29.55$vc4f8/va=1,8 2006.259.07:36:29.55#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.259.07:36:29.55#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.259.07:36:29.55#ibcon#ireg 11 cls_cnt 2 2006.259.07:36:29.55#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.259.07:36:29.55#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.259.07:36:29.55#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.259.07:36:29.55#ibcon#enter wrdev, iclass 25, count 2 2006.259.07:36:29.55#ibcon#first serial, iclass 25, count 2 2006.259.07:36:29.55#ibcon#enter sib2, iclass 25, count 2 2006.259.07:36:29.55#ibcon#flushed, iclass 25, count 2 2006.259.07:36:29.55#ibcon#about to write, iclass 25, count 2 2006.259.07:36:29.55#ibcon#wrote, iclass 25, count 2 2006.259.07:36:29.55#ibcon#about to read 3, iclass 25, count 2 2006.259.07:36:29.57#ibcon#read 3, iclass 25, count 2 2006.259.07:36:29.57#ibcon#about to read 4, iclass 25, count 2 2006.259.07:36:29.57#ibcon#read 4, iclass 25, count 2 2006.259.07:36:29.57#ibcon#about to read 5, iclass 25, count 2 2006.259.07:36:29.57#ibcon#read 5, iclass 25, count 2 2006.259.07:36:29.57#ibcon#about to read 6, iclass 25, count 2 2006.259.07:36:29.57#ibcon#read 6, iclass 25, count 2 2006.259.07:36:29.57#ibcon#end of sib2, iclass 25, count 2 2006.259.07:36:29.57#ibcon#*mode == 0, iclass 25, count 2 2006.259.07:36:29.57#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.259.07:36:29.57#ibcon#[25=AT01-08\r\n] 2006.259.07:36:29.57#ibcon#*before write, iclass 25, count 2 2006.259.07:36:29.57#ibcon#enter sib2, iclass 25, count 2 2006.259.07:36:29.57#ibcon#flushed, iclass 25, count 2 2006.259.07:36:29.57#ibcon#about to write, iclass 25, count 2 2006.259.07:36:29.57#ibcon#wrote, iclass 25, count 2 2006.259.07:36:29.57#ibcon#about to read 3, iclass 25, count 2 2006.259.07:36:29.60#ibcon#read 3, iclass 25, count 2 2006.259.07:36:29.60#ibcon#about to read 4, iclass 25, count 2 2006.259.07:36:29.60#ibcon#read 4, iclass 25, count 2 2006.259.07:36:29.60#ibcon#about to read 5, iclass 25, count 2 2006.259.07:36:29.60#ibcon#read 5, iclass 25, count 2 2006.259.07:36:29.60#ibcon#about to read 6, iclass 25, count 2 2006.259.07:36:29.60#ibcon#read 6, iclass 25, count 2 2006.259.07:36:29.60#ibcon#end of sib2, iclass 25, count 2 2006.259.07:36:29.60#ibcon#*after write, iclass 25, count 2 2006.259.07:36:29.60#ibcon#*before return 0, iclass 25, count 2 2006.259.07:36:29.60#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.259.07:36:29.60#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.259.07:36:29.60#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.259.07:36:29.60#ibcon#ireg 7 cls_cnt 0 2006.259.07:36:29.60#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.259.07:36:29.72#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.259.07:36:29.72#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.259.07:36:29.72#ibcon#enter wrdev, iclass 25, count 0 2006.259.07:36:29.72#ibcon#first serial, iclass 25, count 0 2006.259.07:36:29.72#ibcon#enter sib2, iclass 25, count 0 2006.259.07:36:29.72#ibcon#flushed, iclass 25, count 0 2006.259.07:36:29.72#ibcon#about to write, iclass 25, count 0 2006.259.07:36:29.72#ibcon#wrote, iclass 25, count 0 2006.259.07:36:29.72#ibcon#about to read 3, iclass 25, count 0 2006.259.07:36:29.74#ibcon#read 3, iclass 25, count 0 2006.259.07:36:29.74#ibcon#about to read 4, iclass 25, count 0 2006.259.07:36:29.74#ibcon#read 4, iclass 25, count 0 2006.259.07:36:29.74#ibcon#about to read 5, iclass 25, count 0 2006.259.07:36:29.74#ibcon#read 5, iclass 25, count 0 2006.259.07:36:29.74#ibcon#about to read 6, iclass 25, count 0 2006.259.07:36:29.74#ibcon#read 6, iclass 25, count 0 2006.259.07:36:29.74#ibcon#end of sib2, iclass 25, count 0 2006.259.07:36:29.74#ibcon#*mode == 0, iclass 25, count 0 2006.259.07:36:29.74#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.259.07:36:29.74#ibcon#[25=USB\r\n] 2006.259.07:36:29.74#ibcon#*before write, iclass 25, count 0 2006.259.07:36:29.74#ibcon#enter sib2, iclass 25, count 0 2006.259.07:36:29.74#ibcon#flushed, iclass 25, count 0 2006.259.07:36:29.74#ibcon#about to write, iclass 25, count 0 2006.259.07:36:29.74#ibcon#wrote, iclass 25, count 0 2006.259.07:36:29.74#ibcon#about to read 3, iclass 25, count 0 2006.259.07:36:29.77#ibcon#read 3, iclass 25, count 0 2006.259.07:36:29.77#ibcon#about to read 4, iclass 25, count 0 2006.259.07:36:29.77#ibcon#read 4, iclass 25, count 0 2006.259.07:36:29.77#ibcon#about to read 5, iclass 25, count 0 2006.259.07:36:29.77#ibcon#read 5, iclass 25, count 0 2006.259.07:36:29.77#ibcon#about to read 6, iclass 25, count 0 2006.259.07:36:29.77#ibcon#read 6, iclass 25, count 0 2006.259.07:36:29.77#ibcon#end of sib2, iclass 25, count 0 2006.259.07:36:29.77#ibcon#*after write, iclass 25, count 0 2006.259.07:36:29.77#ibcon#*before return 0, iclass 25, count 0 2006.259.07:36:29.77#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.259.07:36:29.77#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.259.07:36:29.77#ibcon#about to clear, iclass 25 cls_cnt 0 2006.259.07:36:29.77#ibcon#cleared, iclass 25 cls_cnt 0 2006.259.07:36:29.77$vc4f8/valo=2,572.99 2006.259.07:36:29.77#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.259.07:36:29.77#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.259.07:36:29.77#ibcon#ireg 17 cls_cnt 0 2006.259.07:36:29.77#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.259.07:36:29.77#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.259.07:36:29.77#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.259.07:36:29.77#ibcon#enter wrdev, iclass 27, count 0 2006.259.07:36:29.77#ibcon#first serial, iclass 27, count 0 2006.259.07:36:29.77#ibcon#enter sib2, iclass 27, count 0 2006.259.07:36:29.77#ibcon#flushed, iclass 27, count 0 2006.259.07:36:29.77#ibcon#about to write, iclass 27, count 0 2006.259.07:36:29.77#ibcon#wrote, iclass 27, count 0 2006.259.07:36:29.77#ibcon#about to read 3, iclass 27, count 0 2006.259.07:36:29.79#ibcon#read 3, iclass 27, count 0 2006.259.07:36:29.79#ibcon#about to read 4, iclass 27, count 0 2006.259.07:36:29.79#ibcon#read 4, iclass 27, count 0 2006.259.07:36:29.79#ibcon#about to read 5, iclass 27, count 0 2006.259.07:36:29.79#ibcon#read 5, iclass 27, count 0 2006.259.07:36:29.79#ibcon#about to read 6, iclass 27, count 0 2006.259.07:36:29.79#ibcon#read 6, iclass 27, count 0 2006.259.07:36:29.79#ibcon#end of sib2, iclass 27, count 0 2006.259.07:36:29.79#ibcon#*mode == 0, iclass 27, count 0 2006.259.07:36:29.79#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.259.07:36:29.79#ibcon#[26=FRQ=02,572.99\r\n] 2006.259.07:36:29.79#ibcon#*before write, iclass 27, count 0 2006.259.07:36:29.79#ibcon#enter sib2, iclass 27, count 0 2006.259.07:36:29.79#ibcon#flushed, iclass 27, count 0 2006.259.07:36:29.79#ibcon#about to write, iclass 27, count 0 2006.259.07:36:29.79#ibcon#wrote, iclass 27, count 0 2006.259.07:36:29.79#ibcon#about to read 3, iclass 27, count 0 2006.259.07:36:29.83#ibcon#read 3, iclass 27, count 0 2006.259.07:36:29.83#ibcon#about to read 4, iclass 27, count 0 2006.259.07:36:29.83#ibcon#read 4, iclass 27, count 0 2006.259.07:36:29.83#ibcon#about to read 5, iclass 27, count 0 2006.259.07:36:29.83#ibcon#read 5, iclass 27, count 0 2006.259.07:36:29.83#ibcon#about to read 6, iclass 27, count 0 2006.259.07:36:29.83#ibcon#read 6, iclass 27, count 0 2006.259.07:36:29.83#ibcon#end of sib2, iclass 27, count 0 2006.259.07:36:29.83#ibcon#*after write, iclass 27, count 0 2006.259.07:36:29.83#ibcon#*before return 0, iclass 27, count 0 2006.259.07:36:29.83#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.259.07:36:29.83#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.259.07:36:29.83#ibcon#about to clear, iclass 27 cls_cnt 0 2006.259.07:36:29.83#ibcon#cleared, iclass 27 cls_cnt 0 2006.259.07:36:29.83$vc4f8/va=2,7 2006.259.07:36:29.83#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.259.07:36:29.83#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.259.07:36:29.83#ibcon#ireg 11 cls_cnt 2 2006.259.07:36:29.83#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.259.07:36:29.89#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.259.07:36:29.89#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.259.07:36:29.89#ibcon#enter wrdev, iclass 29, count 2 2006.259.07:36:29.89#ibcon#first serial, iclass 29, count 2 2006.259.07:36:29.89#ibcon#enter sib2, iclass 29, count 2 2006.259.07:36:29.89#ibcon#flushed, iclass 29, count 2 2006.259.07:36:29.89#ibcon#about to write, iclass 29, count 2 2006.259.07:36:29.89#ibcon#wrote, iclass 29, count 2 2006.259.07:36:29.89#ibcon#about to read 3, iclass 29, count 2 2006.259.07:36:29.92#ibcon#read 3, iclass 29, count 2 2006.259.07:36:29.92#ibcon#about to read 4, iclass 29, count 2 2006.259.07:36:29.92#ibcon#read 4, iclass 29, count 2 2006.259.07:36:29.92#ibcon#about to read 5, iclass 29, count 2 2006.259.07:36:29.92#ibcon#read 5, iclass 29, count 2 2006.259.07:36:29.92#ibcon#about to read 6, iclass 29, count 2 2006.259.07:36:29.92#ibcon#read 6, iclass 29, count 2 2006.259.07:36:29.92#ibcon#end of sib2, iclass 29, count 2 2006.259.07:36:29.92#ibcon#*mode == 0, iclass 29, count 2 2006.259.07:36:29.92#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.259.07:36:29.92#ibcon#[25=AT02-07\r\n] 2006.259.07:36:29.92#ibcon#*before write, iclass 29, count 2 2006.259.07:36:29.92#ibcon#enter sib2, iclass 29, count 2 2006.259.07:36:29.92#ibcon#flushed, iclass 29, count 2 2006.259.07:36:29.92#ibcon#about to write, iclass 29, count 2 2006.259.07:36:29.92#ibcon#wrote, iclass 29, count 2 2006.259.07:36:29.92#ibcon#about to read 3, iclass 29, count 2 2006.259.07:36:29.95#ibcon#read 3, iclass 29, count 2 2006.259.07:36:29.95#ibcon#about to read 4, iclass 29, count 2 2006.259.07:36:29.95#ibcon#read 4, iclass 29, count 2 2006.259.07:36:29.95#ibcon#about to read 5, iclass 29, count 2 2006.259.07:36:29.95#ibcon#read 5, iclass 29, count 2 2006.259.07:36:29.95#ibcon#about to read 6, iclass 29, count 2 2006.259.07:36:29.95#ibcon#read 6, iclass 29, count 2 2006.259.07:36:29.95#ibcon#end of sib2, iclass 29, count 2 2006.259.07:36:29.95#ibcon#*after write, iclass 29, count 2 2006.259.07:36:29.95#ibcon#*before return 0, iclass 29, count 2 2006.259.07:36:29.95#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.259.07:36:29.95#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.259.07:36:29.95#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.259.07:36:29.95#ibcon#ireg 7 cls_cnt 0 2006.259.07:36:29.95#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.259.07:36:30.07#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.259.07:36:30.07#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.259.07:36:30.07#ibcon#enter wrdev, iclass 29, count 0 2006.259.07:36:30.07#ibcon#first serial, iclass 29, count 0 2006.259.07:36:30.07#ibcon#enter sib2, iclass 29, count 0 2006.259.07:36:30.07#ibcon#flushed, iclass 29, count 0 2006.259.07:36:30.07#ibcon#about to write, iclass 29, count 0 2006.259.07:36:30.07#ibcon#wrote, iclass 29, count 0 2006.259.07:36:30.07#ibcon#about to read 3, iclass 29, count 0 2006.259.07:36:30.11#ibcon#read 3, iclass 29, count 0 2006.259.07:36:30.11#ibcon#about to read 4, iclass 29, count 0 2006.259.07:36:30.11#ibcon#read 4, iclass 29, count 0 2006.259.07:36:30.11#ibcon#about to read 5, iclass 29, count 0 2006.259.07:36:30.11#ibcon#read 5, iclass 29, count 0 2006.259.07:36:30.11#ibcon#about to read 6, iclass 29, count 0 2006.259.07:36:30.11#ibcon#read 6, iclass 29, count 0 2006.259.07:36:30.11#ibcon#end of sib2, iclass 29, count 0 2006.259.07:36:30.11#ibcon#*mode == 0, iclass 29, count 0 2006.259.07:36:30.11#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.259.07:36:30.11#ibcon#[25=USB\r\n] 2006.259.07:36:30.11#ibcon#*before write, iclass 29, count 0 2006.259.07:36:30.11#ibcon#enter sib2, iclass 29, count 0 2006.259.07:36:30.11#ibcon#flushed, iclass 29, count 0 2006.259.07:36:30.11#ibcon#about to write, iclass 29, count 0 2006.259.07:36:30.11#ibcon#wrote, iclass 29, count 0 2006.259.07:36:30.11#ibcon#about to read 3, iclass 29, count 0 2006.259.07:36:30.14#ibcon#read 3, iclass 29, count 0 2006.259.07:36:30.14#ibcon#about to read 4, iclass 29, count 0 2006.259.07:36:30.14#ibcon#read 4, iclass 29, count 0 2006.259.07:36:30.14#ibcon#about to read 5, iclass 29, count 0 2006.259.07:36:30.14#ibcon#read 5, iclass 29, count 0 2006.259.07:36:30.14#ibcon#about to read 6, iclass 29, count 0 2006.259.07:36:30.14#ibcon#read 6, iclass 29, count 0 2006.259.07:36:30.14#ibcon#end of sib2, iclass 29, count 0 2006.259.07:36:30.14#ibcon#*after write, iclass 29, count 0 2006.259.07:36:30.14#ibcon#*before return 0, iclass 29, count 0 2006.259.07:36:30.14#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.259.07:36:30.14#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.259.07:36:30.14#ibcon#about to clear, iclass 29 cls_cnt 0 2006.259.07:36:30.14#ibcon#cleared, iclass 29 cls_cnt 0 2006.259.07:36:30.14$vc4f8/valo=3,672.99 2006.259.07:36:30.14#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.259.07:36:30.14#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.259.07:36:30.14#ibcon#ireg 17 cls_cnt 0 2006.259.07:36:30.14#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.259.07:36:30.14#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.259.07:36:30.14#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.259.07:36:30.14#ibcon#enter wrdev, iclass 31, count 0 2006.259.07:36:30.14#ibcon#first serial, iclass 31, count 0 2006.259.07:36:30.14#ibcon#enter sib2, iclass 31, count 0 2006.259.07:36:30.14#ibcon#flushed, iclass 31, count 0 2006.259.07:36:30.14#ibcon#about to write, iclass 31, count 0 2006.259.07:36:30.14#ibcon#wrote, iclass 31, count 0 2006.259.07:36:30.14#ibcon#about to read 3, iclass 31, count 0 2006.259.07:36:30.16#ibcon#read 3, iclass 31, count 0 2006.259.07:36:30.16#ibcon#about to read 4, iclass 31, count 0 2006.259.07:36:30.16#ibcon#read 4, iclass 31, count 0 2006.259.07:36:30.16#ibcon#about to read 5, iclass 31, count 0 2006.259.07:36:30.16#ibcon#read 5, iclass 31, count 0 2006.259.07:36:30.16#ibcon#about to read 6, iclass 31, count 0 2006.259.07:36:30.16#ibcon#read 6, iclass 31, count 0 2006.259.07:36:30.16#ibcon#end of sib2, iclass 31, count 0 2006.259.07:36:30.16#ibcon#*mode == 0, iclass 31, count 0 2006.259.07:36:30.16#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.259.07:36:30.16#ibcon#[26=FRQ=03,672.99\r\n] 2006.259.07:36:30.16#ibcon#*before write, iclass 31, count 0 2006.259.07:36:30.16#ibcon#enter sib2, iclass 31, count 0 2006.259.07:36:30.16#ibcon#flushed, iclass 31, count 0 2006.259.07:36:30.16#ibcon#about to write, iclass 31, count 0 2006.259.07:36:30.16#ibcon#wrote, iclass 31, count 0 2006.259.07:36:30.16#ibcon#about to read 3, iclass 31, count 0 2006.259.07:36:30.20#ibcon#read 3, iclass 31, count 0 2006.259.07:36:30.20#ibcon#about to read 4, iclass 31, count 0 2006.259.07:36:30.20#ibcon#read 4, iclass 31, count 0 2006.259.07:36:30.20#ibcon#about to read 5, iclass 31, count 0 2006.259.07:36:30.20#ibcon#read 5, iclass 31, count 0 2006.259.07:36:30.20#ibcon#about to read 6, iclass 31, count 0 2006.259.07:36:30.20#ibcon#read 6, iclass 31, count 0 2006.259.07:36:30.20#ibcon#end of sib2, iclass 31, count 0 2006.259.07:36:30.20#ibcon#*after write, iclass 31, count 0 2006.259.07:36:30.20#ibcon#*before return 0, iclass 31, count 0 2006.259.07:36:30.20#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.259.07:36:30.20#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.259.07:36:30.20#ibcon#about to clear, iclass 31 cls_cnt 0 2006.259.07:36:30.20#ibcon#cleared, iclass 31 cls_cnt 0 2006.259.07:36:30.20$vc4f8/va=3,8 2006.259.07:36:30.20#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.259.07:36:30.20#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.259.07:36:30.20#ibcon#ireg 11 cls_cnt 2 2006.259.07:36:30.20#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.259.07:36:30.26#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.259.07:36:30.26#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.259.07:36:30.26#ibcon#enter wrdev, iclass 33, count 2 2006.259.07:36:30.26#ibcon#first serial, iclass 33, count 2 2006.259.07:36:30.26#ibcon#enter sib2, iclass 33, count 2 2006.259.07:36:30.26#ibcon#flushed, iclass 33, count 2 2006.259.07:36:30.26#ibcon#about to write, iclass 33, count 2 2006.259.07:36:30.26#ibcon#wrote, iclass 33, count 2 2006.259.07:36:30.26#ibcon#about to read 3, iclass 33, count 2 2006.259.07:36:30.28#ibcon#read 3, iclass 33, count 2 2006.259.07:36:30.28#ibcon#about to read 4, iclass 33, count 2 2006.259.07:36:30.28#ibcon#read 4, iclass 33, count 2 2006.259.07:36:30.28#ibcon#about to read 5, iclass 33, count 2 2006.259.07:36:30.28#ibcon#read 5, iclass 33, count 2 2006.259.07:36:30.28#ibcon#about to read 6, iclass 33, count 2 2006.259.07:36:30.28#ibcon#read 6, iclass 33, count 2 2006.259.07:36:30.28#ibcon#end of sib2, iclass 33, count 2 2006.259.07:36:30.28#ibcon#*mode == 0, iclass 33, count 2 2006.259.07:36:30.28#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.259.07:36:30.28#ibcon#[25=AT03-08\r\n] 2006.259.07:36:30.28#ibcon#*before write, iclass 33, count 2 2006.259.07:36:30.28#ibcon#enter sib2, iclass 33, count 2 2006.259.07:36:30.28#ibcon#flushed, iclass 33, count 2 2006.259.07:36:30.28#ibcon#about to write, iclass 33, count 2 2006.259.07:36:30.28#ibcon#wrote, iclass 33, count 2 2006.259.07:36:30.28#ibcon#about to read 3, iclass 33, count 2 2006.259.07:36:30.31#ibcon#read 3, iclass 33, count 2 2006.259.07:36:30.31#ibcon#about to read 4, iclass 33, count 2 2006.259.07:36:30.31#ibcon#read 4, iclass 33, count 2 2006.259.07:36:30.31#ibcon#about to read 5, iclass 33, count 2 2006.259.07:36:30.31#ibcon#read 5, iclass 33, count 2 2006.259.07:36:30.31#ibcon#about to read 6, iclass 33, count 2 2006.259.07:36:30.31#ibcon#read 6, iclass 33, count 2 2006.259.07:36:30.31#ibcon#end of sib2, iclass 33, count 2 2006.259.07:36:30.31#ibcon#*after write, iclass 33, count 2 2006.259.07:36:30.31#ibcon#*before return 0, iclass 33, count 2 2006.259.07:36:30.31#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.259.07:36:30.31#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.259.07:36:30.31#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.259.07:36:30.31#ibcon#ireg 7 cls_cnt 0 2006.259.07:36:30.31#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.259.07:36:30.43#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.259.07:36:30.43#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.259.07:36:30.43#ibcon#enter wrdev, iclass 33, count 0 2006.259.07:36:30.43#ibcon#first serial, iclass 33, count 0 2006.259.07:36:30.43#ibcon#enter sib2, iclass 33, count 0 2006.259.07:36:30.43#ibcon#flushed, iclass 33, count 0 2006.259.07:36:30.43#ibcon#about to write, iclass 33, count 0 2006.259.07:36:30.43#ibcon#wrote, iclass 33, count 0 2006.259.07:36:30.43#ibcon#about to read 3, iclass 33, count 0 2006.259.07:36:30.45#ibcon#read 3, iclass 33, count 0 2006.259.07:36:30.45#ibcon#about to read 4, iclass 33, count 0 2006.259.07:36:30.45#ibcon#read 4, iclass 33, count 0 2006.259.07:36:30.45#ibcon#about to read 5, iclass 33, count 0 2006.259.07:36:30.45#ibcon#read 5, iclass 33, count 0 2006.259.07:36:30.45#ibcon#about to read 6, iclass 33, count 0 2006.259.07:36:30.45#ibcon#read 6, iclass 33, count 0 2006.259.07:36:30.45#ibcon#end of sib2, iclass 33, count 0 2006.259.07:36:30.45#ibcon#*mode == 0, iclass 33, count 0 2006.259.07:36:30.45#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.259.07:36:30.45#ibcon#[25=USB\r\n] 2006.259.07:36:30.45#ibcon#*before write, iclass 33, count 0 2006.259.07:36:30.45#ibcon#enter sib2, iclass 33, count 0 2006.259.07:36:30.45#ibcon#flushed, iclass 33, count 0 2006.259.07:36:30.45#ibcon#about to write, iclass 33, count 0 2006.259.07:36:30.45#ibcon#wrote, iclass 33, count 0 2006.259.07:36:30.45#ibcon#about to read 3, iclass 33, count 0 2006.259.07:36:30.48#ibcon#read 3, iclass 33, count 0 2006.259.07:36:30.48#ibcon#about to read 4, iclass 33, count 0 2006.259.07:36:30.48#ibcon#read 4, iclass 33, count 0 2006.259.07:36:30.48#ibcon#about to read 5, iclass 33, count 0 2006.259.07:36:30.48#ibcon#read 5, iclass 33, count 0 2006.259.07:36:30.48#ibcon#about to read 6, iclass 33, count 0 2006.259.07:36:30.48#ibcon#read 6, iclass 33, count 0 2006.259.07:36:30.48#ibcon#end of sib2, iclass 33, count 0 2006.259.07:36:30.48#ibcon#*after write, iclass 33, count 0 2006.259.07:36:30.48#ibcon#*before return 0, iclass 33, count 0 2006.259.07:36:30.48#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.259.07:36:30.48#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.259.07:36:30.48#ibcon#about to clear, iclass 33 cls_cnt 0 2006.259.07:36:30.48#ibcon#cleared, iclass 33 cls_cnt 0 2006.259.07:36:30.48$vc4f8/valo=4,832.99 2006.259.07:36:30.48#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.259.07:36:30.48#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.259.07:36:30.48#ibcon#ireg 17 cls_cnt 0 2006.259.07:36:30.48#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.259.07:36:30.48#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.259.07:36:30.48#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.259.07:36:30.48#ibcon#enter wrdev, iclass 35, count 0 2006.259.07:36:30.48#ibcon#first serial, iclass 35, count 0 2006.259.07:36:30.48#ibcon#enter sib2, iclass 35, count 0 2006.259.07:36:30.48#ibcon#flushed, iclass 35, count 0 2006.259.07:36:30.48#ibcon#about to write, iclass 35, count 0 2006.259.07:36:30.48#ibcon#wrote, iclass 35, count 0 2006.259.07:36:30.48#ibcon#about to read 3, iclass 35, count 0 2006.259.07:36:30.50#ibcon#read 3, iclass 35, count 0 2006.259.07:36:30.50#ibcon#about to read 4, iclass 35, count 0 2006.259.07:36:30.50#ibcon#read 4, iclass 35, count 0 2006.259.07:36:30.50#ibcon#about to read 5, iclass 35, count 0 2006.259.07:36:30.50#ibcon#read 5, iclass 35, count 0 2006.259.07:36:30.50#ibcon#about to read 6, iclass 35, count 0 2006.259.07:36:30.50#ibcon#read 6, iclass 35, count 0 2006.259.07:36:30.50#ibcon#end of sib2, iclass 35, count 0 2006.259.07:36:30.50#ibcon#*mode == 0, iclass 35, count 0 2006.259.07:36:30.50#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.259.07:36:30.50#ibcon#[26=FRQ=04,832.99\r\n] 2006.259.07:36:30.50#ibcon#*before write, iclass 35, count 0 2006.259.07:36:30.50#ibcon#enter sib2, iclass 35, count 0 2006.259.07:36:30.50#ibcon#flushed, iclass 35, count 0 2006.259.07:36:30.50#ibcon#about to write, iclass 35, count 0 2006.259.07:36:30.50#ibcon#wrote, iclass 35, count 0 2006.259.07:36:30.50#ibcon#about to read 3, iclass 35, count 0 2006.259.07:36:30.54#ibcon#read 3, iclass 35, count 0 2006.259.07:36:30.54#ibcon#about to read 4, iclass 35, count 0 2006.259.07:36:30.54#ibcon#read 4, iclass 35, count 0 2006.259.07:36:30.54#ibcon#about to read 5, iclass 35, count 0 2006.259.07:36:30.54#ibcon#read 5, iclass 35, count 0 2006.259.07:36:30.54#ibcon#about to read 6, iclass 35, count 0 2006.259.07:36:30.54#ibcon#read 6, iclass 35, count 0 2006.259.07:36:30.54#ibcon#end of sib2, iclass 35, count 0 2006.259.07:36:30.54#ibcon#*after write, iclass 35, count 0 2006.259.07:36:30.54#ibcon#*before return 0, iclass 35, count 0 2006.259.07:36:30.54#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.259.07:36:30.54#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.259.07:36:30.54#ibcon#about to clear, iclass 35 cls_cnt 0 2006.259.07:36:30.54#ibcon#cleared, iclass 35 cls_cnt 0 2006.259.07:36:30.54$vc4f8/va=4,7 2006.259.07:36:30.54#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.259.07:36:30.54#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.259.07:36:30.54#ibcon#ireg 11 cls_cnt 2 2006.259.07:36:30.54#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.259.07:36:30.60#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.259.07:36:30.60#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.259.07:36:30.60#ibcon#enter wrdev, iclass 37, count 2 2006.259.07:36:30.60#ibcon#first serial, iclass 37, count 2 2006.259.07:36:30.60#ibcon#enter sib2, iclass 37, count 2 2006.259.07:36:30.60#ibcon#flushed, iclass 37, count 2 2006.259.07:36:30.60#ibcon#about to write, iclass 37, count 2 2006.259.07:36:30.60#ibcon#wrote, iclass 37, count 2 2006.259.07:36:30.60#ibcon#about to read 3, iclass 37, count 2 2006.259.07:36:30.62#ibcon#read 3, iclass 37, count 2 2006.259.07:36:30.62#ibcon#about to read 4, iclass 37, count 2 2006.259.07:36:30.62#ibcon#read 4, iclass 37, count 2 2006.259.07:36:30.62#ibcon#about to read 5, iclass 37, count 2 2006.259.07:36:30.62#ibcon#read 5, iclass 37, count 2 2006.259.07:36:30.62#ibcon#about to read 6, iclass 37, count 2 2006.259.07:36:30.62#ibcon#read 6, iclass 37, count 2 2006.259.07:36:30.62#ibcon#end of sib2, iclass 37, count 2 2006.259.07:36:30.62#ibcon#*mode == 0, iclass 37, count 2 2006.259.07:36:30.62#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.259.07:36:30.62#ibcon#[25=AT04-07\r\n] 2006.259.07:36:30.62#ibcon#*before write, iclass 37, count 2 2006.259.07:36:30.62#ibcon#enter sib2, iclass 37, count 2 2006.259.07:36:30.62#ibcon#flushed, iclass 37, count 2 2006.259.07:36:30.62#ibcon#about to write, iclass 37, count 2 2006.259.07:36:30.62#ibcon#wrote, iclass 37, count 2 2006.259.07:36:30.62#ibcon#about to read 3, iclass 37, count 2 2006.259.07:36:30.65#ibcon#read 3, iclass 37, count 2 2006.259.07:36:30.65#ibcon#about to read 4, iclass 37, count 2 2006.259.07:36:30.65#ibcon#read 4, iclass 37, count 2 2006.259.07:36:30.65#ibcon#about to read 5, iclass 37, count 2 2006.259.07:36:30.65#ibcon#read 5, iclass 37, count 2 2006.259.07:36:30.65#ibcon#about to read 6, iclass 37, count 2 2006.259.07:36:30.65#ibcon#read 6, iclass 37, count 2 2006.259.07:36:30.65#ibcon#end of sib2, iclass 37, count 2 2006.259.07:36:30.65#ibcon#*after write, iclass 37, count 2 2006.259.07:36:30.65#ibcon#*before return 0, iclass 37, count 2 2006.259.07:36:30.65#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.259.07:36:30.65#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.259.07:36:30.65#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.259.07:36:30.65#ibcon#ireg 7 cls_cnt 0 2006.259.07:36:30.65#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.259.07:36:30.77#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.259.07:36:30.77#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.259.07:36:30.77#ibcon#enter wrdev, iclass 37, count 0 2006.259.07:36:30.77#ibcon#first serial, iclass 37, count 0 2006.259.07:36:30.77#ibcon#enter sib2, iclass 37, count 0 2006.259.07:36:30.77#ibcon#flushed, iclass 37, count 0 2006.259.07:36:30.77#ibcon#about to write, iclass 37, count 0 2006.259.07:36:30.77#ibcon#wrote, iclass 37, count 0 2006.259.07:36:30.77#ibcon#about to read 3, iclass 37, count 0 2006.259.07:36:30.79#ibcon#read 3, iclass 37, count 0 2006.259.07:36:30.79#ibcon#about to read 4, iclass 37, count 0 2006.259.07:36:30.79#ibcon#read 4, iclass 37, count 0 2006.259.07:36:30.79#ibcon#about to read 5, iclass 37, count 0 2006.259.07:36:30.79#ibcon#read 5, iclass 37, count 0 2006.259.07:36:30.79#ibcon#about to read 6, iclass 37, count 0 2006.259.07:36:30.79#ibcon#read 6, iclass 37, count 0 2006.259.07:36:30.79#ibcon#end of sib2, iclass 37, count 0 2006.259.07:36:30.79#ibcon#*mode == 0, iclass 37, count 0 2006.259.07:36:30.79#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.259.07:36:30.79#ibcon#[25=USB\r\n] 2006.259.07:36:30.79#ibcon#*before write, iclass 37, count 0 2006.259.07:36:30.79#ibcon#enter sib2, iclass 37, count 0 2006.259.07:36:30.79#ibcon#flushed, iclass 37, count 0 2006.259.07:36:30.79#ibcon#about to write, iclass 37, count 0 2006.259.07:36:30.79#ibcon#wrote, iclass 37, count 0 2006.259.07:36:30.79#ibcon#about to read 3, iclass 37, count 0 2006.259.07:36:30.82#ibcon#read 3, iclass 37, count 0 2006.259.07:36:30.82#ibcon#about to read 4, iclass 37, count 0 2006.259.07:36:30.82#ibcon#read 4, iclass 37, count 0 2006.259.07:36:30.82#ibcon#about to read 5, iclass 37, count 0 2006.259.07:36:30.82#ibcon#read 5, iclass 37, count 0 2006.259.07:36:30.82#ibcon#about to read 6, iclass 37, count 0 2006.259.07:36:30.82#ibcon#read 6, iclass 37, count 0 2006.259.07:36:30.82#ibcon#end of sib2, iclass 37, count 0 2006.259.07:36:30.82#ibcon#*after write, iclass 37, count 0 2006.259.07:36:30.82#ibcon#*before return 0, iclass 37, count 0 2006.259.07:36:30.82#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.259.07:36:30.82#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.259.07:36:30.82#ibcon#about to clear, iclass 37 cls_cnt 0 2006.259.07:36:30.82#ibcon#cleared, iclass 37 cls_cnt 0 2006.259.07:36:30.82$vc4f8/valo=5,652.99 2006.259.07:36:30.82#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.259.07:36:30.82#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.259.07:36:30.82#ibcon#ireg 17 cls_cnt 0 2006.259.07:36:30.82#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.259.07:36:30.82#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.259.07:36:30.82#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.259.07:36:30.82#ibcon#enter wrdev, iclass 40, count 0 2006.259.07:36:30.82#ibcon#first serial, iclass 40, count 0 2006.259.07:36:30.82#ibcon#enter sib2, iclass 40, count 0 2006.259.07:36:30.82#ibcon#flushed, iclass 40, count 0 2006.259.07:36:30.82#ibcon#about to write, iclass 40, count 0 2006.259.07:36:30.82#ibcon#wrote, iclass 40, count 0 2006.259.07:36:30.82#ibcon#about to read 3, iclass 40, count 0 2006.259.07:36:30.84#ibcon#read 3, iclass 40, count 0 2006.259.07:36:30.84#ibcon#about to read 4, iclass 40, count 0 2006.259.07:36:30.84#ibcon#read 4, iclass 40, count 0 2006.259.07:36:30.84#ibcon#about to read 5, iclass 40, count 0 2006.259.07:36:30.84#ibcon#read 5, iclass 40, count 0 2006.259.07:36:30.84#ibcon#about to read 6, iclass 40, count 0 2006.259.07:36:30.84#ibcon#read 6, iclass 40, count 0 2006.259.07:36:30.84#ibcon#end of sib2, iclass 40, count 0 2006.259.07:36:30.84#ibcon#*mode == 0, iclass 40, count 0 2006.259.07:36:30.84#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.259.07:36:30.84#ibcon#[26=FRQ=05,652.99\r\n] 2006.259.07:36:30.84#ibcon#*before write, iclass 40, count 0 2006.259.07:36:30.84#ibcon#enter sib2, iclass 40, count 0 2006.259.07:36:30.84#ibcon#flushed, iclass 40, count 0 2006.259.07:36:30.84#ibcon#about to write, iclass 40, count 0 2006.259.07:36:30.84#ibcon#wrote, iclass 40, count 0 2006.259.07:36:30.84#ibcon#about to read 3, iclass 40, count 0 2006.259.07:36:30.85#abcon#<5=/04 2.9 5.8 22.33 841012.8\r\n> 2006.259.07:36:30.87#abcon#{5=INTERFACE CLEAR} 2006.259.07:36:30.88#ibcon#read 3, iclass 40, count 0 2006.259.07:36:30.88#ibcon#about to read 4, iclass 40, count 0 2006.259.07:36:30.88#ibcon#read 4, iclass 40, count 0 2006.259.07:36:30.88#ibcon#about to read 5, iclass 40, count 0 2006.259.07:36:30.88#ibcon#read 5, iclass 40, count 0 2006.259.07:36:30.88#ibcon#about to read 6, iclass 40, count 0 2006.259.07:36:30.88#ibcon#read 6, iclass 40, count 0 2006.259.07:36:30.88#ibcon#end of sib2, iclass 40, count 0 2006.259.07:36:30.88#ibcon#*after write, iclass 40, count 0 2006.259.07:36:30.88#ibcon#*before return 0, iclass 40, count 0 2006.259.07:36:30.88#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.259.07:36:30.88#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.259.07:36:30.88#ibcon#about to clear, iclass 40 cls_cnt 0 2006.259.07:36:30.88#ibcon#cleared, iclass 40 cls_cnt 0 2006.259.07:36:30.88$vc4f8/va=5,7 2006.259.07:36:30.88#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.259.07:36:30.88#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.259.07:36:30.88#ibcon#ireg 11 cls_cnt 2 2006.259.07:36:30.88#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.259.07:36:30.93#abcon#[5=S1D000X0/0*\r\n] 2006.259.07:36:30.94#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.259.07:36:30.94#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.259.07:36:30.94#ibcon#enter wrdev, iclass 6, count 2 2006.259.07:36:30.94#ibcon#first serial, iclass 6, count 2 2006.259.07:36:30.94#ibcon#enter sib2, iclass 6, count 2 2006.259.07:36:30.94#ibcon#flushed, iclass 6, count 2 2006.259.07:36:30.94#ibcon#about to write, iclass 6, count 2 2006.259.07:36:30.94#ibcon#wrote, iclass 6, count 2 2006.259.07:36:30.94#ibcon#about to read 3, iclass 6, count 2 2006.259.07:36:30.96#ibcon#read 3, iclass 6, count 2 2006.259.07:36:30.96#ibcon#about to read 4, iclass 6, count 2 2006.259.07:36:30.96#ibcon#read 4, iclass 6, count 2 2006.259.07:36:30.96#ibcon#about to read 5, iclass 6, count 2 2006.259.07:36:30.96#ibcon#read 5, iclass 6, count 2 2006.259.07:36:30.96#ibcon#about to read 6, iclass 6, count 2 2006.259.07:36:30.96#ibcon#read 6, iclass 6, count 2 2006.259.07:36:30.96#ibcon#end of sib2, iclass 6, count 2 2006.259.07:36:30.96#ibcon#*mode == 0, iclass 6, count 2 2006.259.07:36:30.96#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.259.07:36:30.96#ibcon#[25=AT05-07\r\n] 2006.259.07:36:30.96#ibcon#*before write, iclass 6, count 2 2006.259.07:36:30.96#ibcon#enter sib2, iclass 6, count 2 2006.259.07:36:30.96#ibcon#flushed, iclass 6, count 2 2006.259.07:36:30.96#ibcon#about to write, iclass 6, count 2 2006.259.07:36:30.96#ibcon#wrote, iclass 6, count 2 2006.259.07:36:30.96#ibcon#about to read 3, iclass 6, count 2 2006.259.07:36:30.99#ibcon#read 3, iclass 6, count 2 2006.259.07:36:30.99#ibcon#about to read 4, iclass 6, count 2 2006.259.07:36:30.99#ibcon#read 4, iclass 6, count 2 2006.259.07:36:30.99#ibcon#about to read 5, iclass 6, count 2 2006.259.07:36:30.99#ibcon#read 5, iclass 6, count 2 2006.259.07:36:30.99#ibcon#about to read 6, iclass 6, count 2 2006.259.07:36:30.99#ibcon#read 6, iclass 6, count 2 2006.259.07:36:30.99#ibcon#end of sib2, iclass 6, count 2 2006.259.07:36:30.99#ibcon#*after write, iclass 6, count 2 2006.259.07:36:30.99#ibcon#*before return 0, iclass 6, count 2 2006.259.07:36:30.99#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.259.07:36:30.99#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.259.07:36:30.99#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.259.07:36:30.99#ibcon#ireg 7 cls_cnt 0 2006.259.07:36:30.99#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.259.07:36:31.11#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.259.07:36:31.11#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.259.07:36:31.11#ibcon#enter wrdev, iclass 6, count 0 2006.259.07:36:31.11#ibcon#first serial, iclass 6, count 0 2006.259.07:36:31.11#ibcon#enter sib2, iclass 6, count 0 2006.259.07:36:31.11#ibcon#flushed, iclass 6, count 0 2006.259.07:36:31.11#ibcon#about to write, iclass 6, count 0 2006.259.07:36:31.11#ibcon#wrote, iclass 6, count 0 2006.259.07:36:31.11#ibcon#about to read 3, iclass 6, count 0 2006.259.07:36:31.13#ibcon#read 3, iclass 6, count 0 2006.259.07:36:31.13#ibcon#about to read 4, iclass 6, count 0 2006.259.07:36:31.13#ibcon#read 4, iclass 6, count 0 2006.259.07:36:31.13#ibcon#about to read 5, iclass 6, count 0 2006.259.07:36:31.13#ibcon#read 5, iclass 6, count 0 2006.259.07:36:31.13#ibcon#about to read 6, iclass 6, count 0 2006.259.07:36:31.13#ibcon#read 6, iclass 6, count 0 2006.259.07:36:31.13#ibcon#end of sib2, iclass 6, count 0 2006.259.07:36:31.13#ibcon#*mode == 0, iclass 6, count 0 2006.259.07:36:31.13#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.259.07:36:31.13#ibcon#[25=USB\r\n] 2006.259.07:36:31.13#ibcon#*before write, iclass 6, count 0 2006.259.07:36:31.13#ibcon#enter sib2, iclass 6, count 0 2006.259.07:36:31.13#ibcon#flushed, iclass 6, count 0 2006.259.07:36:31.13#ibcon#about to write, iclass 6, count 0 2006.259.07:36:31.13#ibcon#wrote, iclass 6, count 0 2006.259.07:36:31.13#ibcon#about to read 3, iclass 6, count 0 2006.259.07:36:31.16#ibcon#read 3, iclass 6, count 0 2006.259.07:36:31.16#ibcon#about to read 4, iclass 6, count 0 2006.259.07:36:31.16#ibcon#read 4, iclass 6, count 0 2006.259.07:36:31.16#ibcon#about to read 5, iclass 6, count 0 2006.259.07:36:31.16#ibcon#read 5, iclass 6, count 0 2006.259.07:36:31.16#ibcon#about to read 6, iclass 6, count 0 2006.259.07:36:31.16#ibcon#read 6, iclass 6, count 0 2006.259.07:36:31.16#ibcon#end of sib2, iclass 6, count 0 2006.259.07:36:31.16#ibcon#*after write, iclass 6, count 0 2006.259.07:36:31.16#ibcon#*before return 0, iclass 6, count 0 2006.259.07:36:31.16#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.259.07:36:31.16#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.259.07:36:31.16#ibcon#about to clear, iclass 6 cls_cnt 0 2006.259.07:36:31.16#ibcon#cleared, iclass 6 cls_cnt 0 2006.259.07:36:31.16$vc4f8/valo=6,772.99 2006.259.07:36:31.16#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.259.07:36:31.16#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.259.07:36:31.16#ibcon#ireg 17 cls_cnt 0 2006.259.07:36:31.16#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.259.07:36:31.16#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.259.07:36:31.16#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.259.07:36:31.16#ibcon#enter wrdev, iclass 11, count 0 2006.259.07:36:31.16#ibcon#first serial, iclass 11, count 0 2006.259.07:36:31.16#ibcon#enter sib2, iclass 11, count 0 2006.259.07:36:31.16#ibcon#flushed, iclass 11, count 0 2006.259.07:36:31.16#ibcon#about to write, iclass 11, count 0 2006.259.07:36:31.16#ibcon#wrote, iclass 11, count 0 2006.259.07:36:31.16#ibcon#about to read 3, iclass 11, count 0 2006.259.07:36:31.18#ibcon#read 3, iclass 11, count 0 2006.259.07:36:31.18#ibcon#about to read 4, iclass 11, count 0 2006.259.07:36:31.18#ibcon#read 4, iclass 11, count 0 2006.259.07:36:31.18#ibcon#about to read 5, iclass 11, count 0 2006.259.07:36:31.18#ibcon#read 5, iclass 11, count 0 2006.259.07:36:31.18#ibcon#about to read 6, iclass 11, count 0 2006.259.07:36:31.18#ibcon#read 6, iclass 11, count 0 2006.259.07:36:31.18#ibcon#end of sib2, iclass 11, count 0 2006.259.07:36:31.18#ibcon#*mode == 0, iclass 11, count 0 2006.259.07:36:31.18#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.259.07:36:31.18#ibcon#[26=FRQ=06,772.99\r\n] 2006.259.07:36:31.18#ibcon#*before write, iclass 11, count 0 2006.259.07:36:31.18#ibcon#enter sib2, iclass 11, count 0 2006.259.07:36:31.18#ibcon#flushed, iclass 11, count 0 2006.259.07:36:31.18#ibcon#about to write, iclass 11, count 0 2006.259.07:36:31.18#ibcon#wrote, iclass 11, count 0 2006.259.07:36:31.18#ibcon#about to read 3, iclass 11, count 0 2006.259.07:36:31.22#ibcon#read 3, iclass 11, count 0 2006.259.07:36:31.22#ibcon#about to read 4, iclass 11, count 0 2006.259.07:36:31.22#ibcon#read 4, iclass 11, count 0 2006.259.07:36:31.22#ibcon#about to read 5, iclass 11, count 0 2006.259.07:36:31.22#ibcon#read 5, iclass 11, count 0 2006.259.07:36:31.22#ibcon#about to read 6, iclass 11, count 0 2006.259.07:36:31.22#ibcon#read 6, iclass 11, count 0 2006.259.07:36:31.22#ibcon#end of sib2, iclass 11, count 0 2006.259.07:36:31.22#ibcon#*after write, iclass 11, count 0 2006.259.07:36:31.22#ibcon#*before return 0, iclass 11, count 0 2006.259.07:36:31.22#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.259.07:36:31.22#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.259.07:36:31.22#ibcon#about to clear, iclass 11 cls_cnt 0 2006.259.07:36:31.22#ibcon#cleared, iclass 11 cls_cnt 0 2006.259.07:36:31.22$vc4f8/va=6,6 2006.259.07:36:31.22#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.259.07:36:31.22#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.259.07:36:31.22#ibcon#ireg 11 cls_cnt 2 2006.259.07:36:31.22#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.259.07:36:31.28#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.259.07:36:31.28#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.259.07:36:31.28#ibcon#enter wrdev, iclass 13, count 2 2006.259.07:36:31.28#ibcon#first serial, iclass 13, count 2 2006.259.07:36:31.28#ibcon#enter sib2, iclass 13, count 2 2006.259.07:36:31.28#ibcon#flushed, iclass 13, count 2 2006.259.07:36:31.28#ibcon#about to write, iclass 13, count 2 2006.259.07:36:31.28#ibcon#wrote, iclass 13, count 2 2006.259.07:36:31.28#ibcon#about to read 3, iclass 13, count 2 2006.259.07:36:31.30#ibcon#read 3, iclass 13, count 2 2006.259.07:36:31.30#ibcon#about to read 4, iclass 13, count 2 2006.259.07:36:31.30#ibcon#read 4, iclass 13, count 2 2006.259.07:36:31.30#ibcon#about to read 5, iclass 13, count 2 2006.259.07:36:31.30#ibcon#read 5, iclass 13, count 2 2006.259.07:36:31.30#ibcon#about to read 6, iclass 13, count 2 2006.259.07:36:31.30#ibcon#read 6, iclass 13, count 2 2006.259.07:36:31.30#ibcon#end of sib2, iclass 13, count 2 2006.259.07:36:31.30#ibcon#*mode == 0, iclass 13, count 2 2006.259.07:36:31.30#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.259.07:36:31.30#ibcon#[25=AT06-06\r\n] 2006.259.07:36:31.30#ibcon#*before write, iclass 13, count 2 2006.259.07:36:31.30#ibcon#enter sib2, iclass 13, count 2 2006.259.07:36:31.30#ibcon#flushed, iclass 13, count 2 2006.259.07:36:31.30#ibcon#about to write, iclass 13, count 2 2006.259.07:36:31.30#ibcon#wrote, iclass 13, count 2 2006.259.07:36:31.30#ibcon#about to read 3, iclass 13, count 2 2006.259.07:36:31.33#ibcon#read 3, iclass 13, count 2 2006.259.07:36:31.33#ibcon#about to read 4, iclass 13, count 2 2006.259.07:36:31.33#ibcon#read 4, iclass 13, count 2 2006.259.07:36:31.33#ibcon#about to read 5, iclass 13, count 2 2006.259.07:36:31.33#ibcon#read 5, iclass 13, count 2 2006.259.07:36:31.33#ibcon#about to read 6, iclass 13, count 2 2006.259.07:36:31.33#ibcon#read 6, iclass 13, count 2 2006.259.07:36:31.33#ibcon#end of sib2, iclass 13, count 2 2006.259.07:36:31.33#ibcon#*after write, iclass 13, count 2 2006.259.07:36:31.33#ibcon#*before return 0, iclass 13, count 2 2006.259.07:36:31.33#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.259.07:36:31.33#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.259.07:36:31.33#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.259.07:36:31.33#ibcon#ireg 7 cls_cnt 0 2006.259.07:36:31.33#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.259.07:36:31.45#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.259.07:36:31.45#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.259.07:36:31.45#ibcon#enter wrdev, iclass 13, count 0 2006.259.07:36:31.45#ibcon#first serial, iclass 13, count 0 2006.259.07:36:31.45#ibcon#enter sib2, iclass 13, count 0 2006.259.07:36:31.45#ibcon#flushed, iclass 13, count 0 2006.259.07:36:31.45#ibcon#about to write, iclass 13, count 0 2006.259.07:36:31.45#ibcon#wrote, iclass 13, count 0 2006.259.07:36:31.45#ibcon#about to read 3, iclass 13, count 0 2006.259.07:36:31.47#ibcon#read 3, iclass 13, count 0 2006.259.07:36:31.47#ibcon#about to read 4, iclass 13, count 0 2006.259.07:36:31.47#ibcon#read 4, iclass 13, count 0 2006.259.07:36:31.47#ibcon#about to read 5, iclass 13, count 0 2006.259.07:36:31.47#ibcon#read 5, iclass 13, count 0 2006.259.07:36:31.47#ibcon#about to read 6, iclass 13, count 0 2006.259.07:36:31.47#ibcon#read 6, iclass 13, count 0 2006.259.07:36:31.47#ibcon#end of sib2, iclass 13, count 0 2006.259.07:36:31.47#ibcon#*mode == 0, iclass 13, count 0 2006.259.07:36:31.47#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.259.07:36:31.47#ibcon#[25=USB\r\n] 2006.259.07:36:31.47#ibcon#*before write, iclass 13, count 0 2006.259.07:36:31.47#ibcon#enter sib2, iclass 13, count 0 2006.259.07:36:31.47#ibcon#flushed, iclass 13, count 0 2006.259.07:36:31.47#ibcon#about to write, iclass 13, count 0 2006.259.07:36:31.47#ibcon#wrote, iclass 13, count 0 2006.259.07:36:31.47#ibcon#about to read 3, iclass 13, count 0 2006.259.07:36:31.50#ibcon#read 3, iclass 13, count 0 2006.259.07:36:31.50#ibcon#about to read 4, iclass 13, count 0 2006.259.07:36:31.50#ibcon#read 4, iclass 13, count 0 2006.259.07:36:31.50#ibcon#about to read 5, iclass 13, count 0 2006.259.07:36:31.50#ibcon#read 5, iclass 13, count 0 2006.259.07:36:31.50#ibcon#about to read 6, iclass 13, count 0 2006.259.07:36:31.50#ibcon#read 6, iclass 13, count 0 2006.259.07:36:31.50#ibcon#end of sib2, iclass 13, count 0 2006.259.07:36:31.50#ibcon#*after write, iclass 13, count 0 2006.259.07:36:31.50#ibcon#*before return 0, iclass 13, count 0 2006.259.07:36:31.50#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.259.07:36:31.50#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.259.07:36:31.50#ibcon#about to clear, iclass 13 cls_cnt 0 2006.259.07:36:31.50#ibcon#cleared, iclass 13 cls_cnt 0 2006.259.07:36:31.50$vc4f8/valo=7,832.99 2006.259.07:36:31.50#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.259.07:36:31.50#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.259.07:36:31.50#ibcon#ireg 17 cls_cnt 0 2006.259.07:36:31.50#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.259.07:36:31.50#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.259.07:36:31.50#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.259.07:36:31.50#ibcon#enter wrdev, iclass 15, count 0 2006.259.07:36:31.50#ibcon#first serial, iclass 15, count 0 2006.259.07:36:31.50#ibcon#enter sib2, iclass 15, count 0 2006.259.07:36:31.50#ibcon#flushed, iclass 15, count 0 2006.259.07:36:31.50#ibcon#about to write, iclass 15, count 0 2006.259.07:36:31.50#ibcon#wrote, iclass 15, count 0 2006.259.07:36:31.50#ibcon#about to read 3, iclass 15, count 0 2006.259.07:36:31.52#ibcon#read 3, iclass 15, count 0 2006.259.07:36:31.52#ibcon#about to read 4, iclass 15, count 0 2006.259.07:36:31.52#ibcon#read 4, iclass 15, count 0 2006.259.07:36:31.52#ibcon#about to read 5, iclass 15, count 0 2006.259.07:36:31.52#ibcon#read 5, iclass 15, count 0 2006.259.07:36:31.52#ibcon#about to read 6, iclass 15, count 0 2006.259.07:36:31.52#ibcon#read 6, iclass 15, count 0 2006.259.07:36:31.52#ibcon#end of sib2, iclass 15, count 0 2006.259.07:36:31.52#ibcon#*mode == 0, iclass 15, count 0 2006.259.07:36:31.52#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.259.07:36:31.52#ibcon#[26=FRQ=07,832.99\r\n] 2006.259.07:36:31.52#ibcon#*before write, iclass 15, count 0 2006.259.07:36:31.52#ibcon#enter sib2, iclass 15, count 0 2006.259.07:36:31.52#ibcon#flushed, iclass 15, count 0 2006.259.07:36:31.52#ibcon#about to write, iclass 15, count 0 2006.259.07:36:31.52#ibcon#wrote, iclass 15, count 0 2006.259.07:36:31.52#ibcon#about to read 3, iclass 15, count 0 2006.259.07:36:31.56#ibcon#read 3, iclass 15, count 0 2006.259.07:36:31.56#ibcon#about to read 4, iclass 15, count 0 2006.259.07:36:31.56#ibcon#read 4, iclass 15, count 0 2006.259.07:36:31.56#ibcon#about to read 5, iclass 15, count 0 2006.259.07:36:31.56#ibcon#read 5, iclass 15, count 0 2006.259.07:36:31.56#ibcon#about to read 6, iclass 15, count 0 2006.259.07:36:31.56#ibcon#read 6, iclass 15, count 0 2006.259.07:36:31.56#ibcon#end of sib2, iclass 15, count 0 2006.259.07:36:31.56#ibcon#*after write, iclass 15, count 0 2006.259.07:36:31.56#ibcon#*before return 0, iclass 15, count 0 2006.259.07:36:31.56#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.259.07:36:31.56#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.259.07:36:31.56#ibcon#about to clear, iclass 15 cls_cnt 0 2006.259.07:36:31.56#ibcon#cleared, iclass 15 cls_cnt 0 2006.259.07:36:31.56$vc4f8/va=7,6 2006.259.07:36:31.56#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.259.07:36:31.56#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.259.07:36:31.56#ibcon#ireg 11 cls_cnt 2 2006.259.07:36:31.56#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.259.07:36:31.62#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.259.07:36:31.62#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.259.07:36:31.62#ibcon#enter wrdev, iclass 17, count 2 2006.259.07:36:31.62#ibcon#first serial, iclass 17, count 2 2006.259.07:36:31.62#ibcon#enter sib2, iclass 17, count 2 2006.259.07:36:31.62#ibcon#flushed, iclass 17, count 2 2006.259.07:36:31.62#ibcon#about to write, iclass 17, count 2 2006.259.07:36:31.62#ibcon#wrote, iclass 17, count 2 2006.259.07:36:31.62#ibcon#about to read 3, iclass 17, count 2 2006.259.07:36:31.64#ibcon#read 3, iclass 17, count 2 2006.259.07:36:31.64#ibcon#about to read 4, iclass 17, count 2 2006.259.07:36:31.64#ibcon#read 4, iclass 17, count 2 2006.259.07:36:31.64#ibcon#about to read 5, iclass 17, count 2 2006.259.07:36:31.64#ibcon#read 5, iclass 17, count 2 2006.259.07:36:31.64#ibcon#about to read 6, iclass 17, count 2 2006.259.07:36:31.64#ibcon#read 6, iclass 17, count 2 2006.259.07:36:31.64#ibcon#end of sib2, iclass 17, count 2 2006.259.07:36:31.64#ibcon#*mode == 0, iclass 17, count 2 2006.259.07:36:31.64#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.259.07:36:31.64#ibcon#[25=AT07-06\r\n] 2006.259.07:36:31.64#ibcon#*before write, iclass 17, count 2 2006.259.07:36:31.64#ibcon#enter sib2, iclass 17, count 2 2006.259.07:36:31.64#ibcon#flushed, iclass 17, count 2 2006.259.07:36:31.64#ibcon#about to write, iclass 17, count 2 2006.259.07:36:31.64#ibcon#wrote, iclass 17, count 2 2006.259.07:36:31.64#ibcon#about to read 3, iclass 17, count 2 2006.259.07:36:31.67#ibcon#read 3, iclass 17, count 2 2006.259.07:36:31.67#ibcon#about to read 4, iclass 17, count 2 2006.259.07:36:31.67#ibcon#read 4, iclass 17, count 2 2006.259.07:36:31.67#ibcon#about to read 5, iclass 17, count 2 2006.259.07:36:31.67#ibcon#read 5, iclass 17, count 2 2006.259.07:36:31.67#ibcon#about to read 6, iclass 17, count 2 2006.259.07:36:31.67#ibcon#read 6, iclass 17, count 2 2006.259.07:36:31.67#ibcon#end of sib2, iclass 17, count 2 2006.259.07:36:31.67#ibcon#*after write, iclass 17, count 2 2006.259.07:36:31.67#ibcon#*before return 0, iclass 17, count 2 2006.259.07:36:31.67#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.259.07:36:31.67#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.259.07:36:31.67#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.259.07:36:31.67#ibcon#ireg 7 cls_cnt 0 2006.259.07:36:31.67#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.259.07:36:31.79#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.259.07:36:31.79#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.259.07:36:31.79#ibcon#enter wrdev, iclass 17, count 0 2006.259.07:36:31.79#ibcon#first serial, iclass 17, count 0 2006.259.07:36:31.79#ibcon#enter sib2, iclass 17, count 0 2006.259.07:36:31.79#ibcon#flushed, iclass 17, count 0 2006.259.07:36:31.79#ibcon#about to write, iclass 17, count 0 2006.259.07:36:31.79#ibcon#wrote, iclass 17, count 0 2006.259.07:36:31.79#ibcon#about to read 3, iclass 17, count 0 2006.259.07:36:31.81#ibcon#read 3, iclass 17, count 0 2006.259.07:36:31.81#ibcon#about to read 4, iclass 17, count 0 2006.259.07:36:31.81#ibcon#read 4, iclass 17, count 0 2006.259.07:36:31.81#ibcon#about to read 5, iclass 17, count 0 2006.259.07:36:31.81#ibcon#read 5, iclass 17, count 0 2006.259.07:36:31.81#ibcon#about to read 6, iclass 17, count 0 2006.259.07:36:31.81#ibcon#read 6, iclass 17, count 0 2006.259.07:36:31.81#ibcon#end of sib2, iclass 17, count 0 2006.259.07:36:31.81#ibcon#*mode == 0, iclass 17, count 0 2006.259.07:36:31.81#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.259.07:36:31.81#ibcon#[25=USB\r\n] 2006.259.07:36:31.81#ibcon#*before write, iclass 17, count 0 2006.259.07:36:31.81#ibcon#enter sib2, iclass 17, count 0 2006.259.07:36:31.81#ibcon#flushed, iclass 17, count 0 2006.259.07:36:31.81#ibcon#about to write, iclass 17, count 0 2006.259.07:36:31.81#ibcon#wrote, iclass 17, count 0 2006.259.07:36:31.81#ibcon#about to read 3, iclass 17, count 0 2006.259.07:36:31.84#ibcon#read 3, iclass 17, count 0 2006.259.07:36:31.84#ibcon#about to read 4, iclass 17, count 0 2006.259.07:36:31.84#ibcon#read 4, iclass 17, count 0 2006.259.07:36:31.84#ibcon#about to read 5, iclass 17, count 0 2006.259.07:36:31.84#ibcon#read 5, iclass 17, count 0 2006.259.07:36:31.84#ibcon#about to read 6, iclass 17, count 0 2006.259.07:36:31.84#ibcon#read 6, iclass 17, count 0 2006.259.07:36:31.84#ibcon#end of sib2, iclass 17, count 0 2006.259.07:36:31.84#ibcon#*after write, iclass 17, count 0 2006.259.07:36:31.84#ibcon#*before return 0, iclass 17, count 0 2006.259.07:36:31.84#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.259.07:36:31.84#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.259.07:36:31.84#ibcon#about to clear, iclass 17 cls_cnt 0 2006.259.07:36:31.84#ibcon#cleared, iclass 17 cls_cnt 0 2006.259.07:36:31.84$vc4f8/valo=8,852.99 2006.259.07:36:31.84#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.259.07:36:31.84#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.259.07:36:31.84#ibcon#ireg 17 cls_cnt 0 2006.259.07:36:31.84#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.259.07:36:31.84#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.259.07:36:31.84#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.259.07:36:31.84#ibcon#enter wrdev, iclass 19, count 0 2006.259.07:36:31.84#ibcon#first serial, iclass 19, count 0 2006.259.07:36:31.84#ibcon#enter sib2, iclass 19, count 0 2006.259.07:36:31.84#ibcon#flushed, iclass 19, count 0 2006.259.07:36:31.84#ibcon#about to write, iclass 19, count 0 2006.259.07:36:31.84#ibcon#wrote, iclass 19, count 0 2006.259.07:36:31.84#ibcon#about to read 3, iclass 19, count 0 2006.259.07:36:31.86#ibcon#read 3, iclass 19, count 0 2006.259.07:36:31.86#ibcon#about to read 4, iclass 19, count 0 2006.259.07:36:31.86#ibcon#read 4, iclass 19, count 0 2006.259.07:36:31.86#ibcon#about to read 5, iclass 19, count 0 2006.259.07:36:31.86#ibcon#read 5, iclass 19, count 0 2006.259.07:36:31.86#ibcon#about to read 6, iclass 19, count 0 2006.259.07:36:31.86#ibcon#read 6, iclass 19, count 0 2006.259.07:36:31.86#ibcon#end of sib2, iclass 19, count 0 2006.259.07:36:31.86#ibcon#*mode == 0, iclass 19, count 0 2006.259.07:36:31.86#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.259.07:36:31.86#ibcon#[26=FRQ=08,852.99\r\n] 2006.259.07:36:31.86#ibcon#*before write, iclass 19, count 0 2006.259.07:36:31.86#ibcon#enter sib2, iclass 19, count 0 2006.259.07:36:31.86#ibcon#flushed, iclass 19, count 0 2006.259.07:36:31.86#ibcon#about to write, iclass 19, count 0 2006.259.07:36:31.86#ibcon#wrote, iclass 19, count 0 2006.259.07:36:31.86#ibcon#about to read 3, iclass 19, count 0 2006.259.07:36:31.90#ibcon#read 3, iclass 19, count 0 2006.259.07:36:31.90#ibcon#about to read 4, iclass 19, count 0 2006.259.07:36:31.90#ibcon#read 4, iclass 19, count 0 2006.259.07:36:31.90#ibcon#about to read 5, iclass 19, count 0 2006.259.07:36:31.90#ibcon#read 5, iclass 19, count 0 2006.259.07:36:31.90#ibcon#about to read 6, iclass 19, count 0 2006.259.07:36:31.90#ibcon#read 6, iclass 19, count 0 2006.259.07:36:31.90#ibcon#end of sib2, iclass 19, count 0 2006.259.07:36:31.90#ibcon#*after write, iclass 19, count 0 2006.259.07:36:31.90#ibcon#*before return 0, iclass 19, count 0 2006.259.07:36:31.90#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.259.07:36:31.90#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.259.07:36:31.90#ibcon#about to clear, iclass 19 cls_cnt 0 2006.259.07:36:31.90#ibcon#cleared, iclass 19 cls_cnt 0 2006.259.07:36:31.90$vc4f8/va=8,6 2006.259.07:36:31.90#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.259.07:36:31.90#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.259.07:36:31.90#ibcon#ireg 11 cls_cnt 2 2006.259.07:36:31.90#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.259.07:36:31.96#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.259.07:36:31.96#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.259.07:36:31.96#ibcon#enter wrdev, iclass 21, count 2 2006.259.07:36:31.96#ibcon#first serial, iclass 21, count 2 2006.259.07:36:31.96#ibcon#enter sib2, iclass 21, count 2 2006.259.07:36:31.96#ibcon#flushed, iclass 21, count 2 2006.259.07:36:31.96#ibcon#about to write, iclass 21, count 2 2006.259.07:36:31.96#ibcon#wrote, iclass 21, count 2 2006.259.07:36:31.96#ibcon#about to read 3, iclass 21, count 2 2006.259.07:36:31.98#ibcon#read 3, iclass 21, count 2 2006.259.07:36:31.98#ibcon#about to read 4, iclass 21, count 2 2006.259.07:36:31.98#ibcon#read 4, iclass 21, count 2 2006.259.07:36:31.98#ibcon#about to read 5, iclass 21, count 2 2006.259.07:36:31.98#ibcon#read 5, iclass 21, count 2 2006.259.07:36:31.98#ibcon#about to read 6, iclass 21, count 2 2006.259.07:36:31.98#ibcon#read 6, iclass 21, count 2 2006.259.07:36:31.98#ibcon#end of sib2, iclass 21, count 2 2006.259.07:36:31.98#ibcon#*mode == 0, iclass 21, count 2 2006.259.07:36:31.98#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.259.07:36:31.98#ibcon#[25=AT08-06\r\n] 2006.259.07:36:31.98#ibcon#*before write, iclass 21, count 2 2006.259.07:36:31.98#ibcon#enter sib2, iclass 21, count 2 2006.259.07:36:31.98#ibcon#flushed, iclass 21, count 2 2006.259.07:36:31.98#ibcon#about to write, iclass 21, count 2 2006.259.07:36:31.98#ibcon#wrote, iclass 21, count 2 2006.259.07:36:31.98#ibcon#about to read 3, iclass 21, count 2 2006.259.07:36:32.01#ibcon#read 3, iclass 21, count 2 2006.259.07:36:32.01#ibcon#about to read 4, iclass 21, count 2 2006.259.07:36:32.01#ibcon#read 4, iclass 21, count 2 2006.259.07:36:32.01#ibcon#about to read 5, iclass 21, count 2 2006.259.07:36:32.01#ibcon#read 5, iclass 21, count 2 2006.259.07:36:32.01#ibcon#about to read 6, iclass 21, count 2 2006.259.07:36:32.01#ibcon#read 6, iclass 21, count 2 2006.259.07:36:32.01#ibcon#end of sib2, iclass 21, count 2 2006.259.07:36:32.01#ibcon#*after write, iclass 21, count 2 2006.259.07:36:32.01#ibcon#*before return 0, iclass 21, count 2 2006.259.07:36:32.01#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.259.07:36:32.01#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.259.07:36:32.01#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.259.07:36:32.01#ibcon#ireg 7 cls_cnt 0 2006.259.07:36:32.01#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.259.07:36:32.13#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.259.07:36:32.13#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.259.07:36:32.13#ibcon#enter wrdev, iclass 21, count 0 2006.259.07:36:32.13#ibcon#first serial, iclass 21, count 0 2006.259.07:36:32.13#ibcon#enter sib2, iclass 21, count 0 2006.259.07:36:32.13#ibcon#flushed, iclass 21, count 0 2006.259.07:36:32.13#ibcon#about to write, iclass 21, count 0 2006.259.07:36:32.13#ibcon#wrote, iclass 21, count 0 2006.259.07:36:32.13#ibcon#about to read 3, iclass 21, count 0 2006.259.07:36:32.15#ibcon#read 3, iclass 21, count 0 2006.259.07:36:32.15#ibcon#about to read 4, iclass 21, count 0 2006.259.07:36:32.15#ibcon#read 4, iclass 21, count 0 2006.259.07:36:32.15#ibcon#about to read 5, iclass 21, count 0 2006.259.07:36:32.15#ibcon#read 5, iclass 21, count 0 2006.259.07:36:32.15#ibcon#about to read 6, iclass 21, count 0 2006.259.07:36:32.15#ibcon#read 6, iclass 21, count 0 2006.259.07:36:32.15#ibcon#end of sib2, iclass 21, count 0 2006.259.07:36:32.15#ibcon#*mode == 0, iclass 21, count 0 2006.259.07:36:32.15#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.259.07:36:32.15#ibcon#[25=USB\r\n] 2006.259.07:36:32.15#ibcon#*before write, iclass 21, count 0 2006.259.07:36:32.15#ibcon#enter sib2, iclass 21, count 0 2006.259.07:36:32.15#ibcon#flushed, iclass 21, count 0 2006.259.07:36:32.15#ibcon#about to write, iclass 21, count 0 2006.259.07:36:32.15#ibcon#wrote, iclass 21, count 0 2006.259.07:36:32.15#ibcon#about to read 3, iclass 21, count 0 2006.259.07:36:32.18#ibcon#read 3, iclass 21, count 0 2006.259.07:36:32.18#ibcon#about to read 4, iclass 21, count 0 2006.259.07:36:32.18#ibcon#read 4, iclass 21, count 0 2006.259.07:36:32.18#ibcon#about to read 5, iclass 21, count 0 2006.259.07:36:32.18#ibcon#read 5, iclass 21, count 0 2006.259.07:36:32.18#ibcon#about to read 6, iclass 21, count 0 2006.259.07:36:32.18#ibcon#read 6, iclass 21, count 0 2006.259.07:36:32.18#ibcon#end of sib2, iclass 21, count 0 2006.259.07:36:32.18#ibcon#*after write, iclass 21, count 0 2006.259.07:36:32.18#ibcon#*before return 0, iclass 21, count 0 2006.259.07:36:32.18#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.259.07:36:32.18#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.259.07:36:32.18#ibcon#about to clear, iclass 21 cls_cnt 0 2006.259.07:36:32.18#ibcon#cleared, iclass 21 cls_cnt 0 2006.259.07:36:32.18$vc4f8/vblo=1,632.99 2006.259.07:36:32.18#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.259.07:36:32.18#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.259.07:36:32.18#ibcon#ireg 17 cls_cnt 0 2006.259.07:36:32.18#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.259.07:36:32.18#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.259.07:36:32.18#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.259.07:36:32.18#ibcon#enter wrdev, iclass 23, count 0 2006.259.07:36:32.18#ibcon#first serial, iclass 23, count 0 2006.259.07:36:32.18#ibcon#enter sib2, iclass 23, count 0 2006.259.07:36:32.18#ibcon#flushed, iclass 23, count 0 2006.259.07:36:32.18#ibcon#about to write, iclass 23, count 0 2006.259.07:36:32.18#ibcon#wrote, iclass 23, count 0 2006.259.07:36:32.18#ibcon#about to read 3, iclass 23, count 0 2006.259.07:36:32.20#ibcon#read 3, iclass 23, count 0 2006.259.07:36:32.20#ibcon#about to read 4, iclass 23, count 0 2006.259.07:36:32.20#ibcon#read 4, iclass 23, count 0 2006.259.07:36:32.20#ibcon#about to read 5, iclass 23, count 0 2006.259.07:36:32.20#ibcon#read 5, iclass 23, count 0 2006.259.07:36:32.20#ibcon#about to read 6, iclass 23, count 0 2006.259.07:36:32.20#ibcon#read 6, iclass 23, count 0 2006.259.07:36:32.20#ibcon#end of sib2, iclass 23, count 0 2006.259.07:36:32.20#ibcon#*mode == 0, iclass 23, count 0 2006.259.07:36:32.20#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.259.07:36:32.20#ibcon#[28=FRQ=01,632.99\r\n] 2006.259.07:36:32.20#ibcon#*before write, iclass 23, count 0 2006.259.07:36:32.20#ibcon#enter sib2, iclass 23, count 0 2006.259.07:36:32.20#ibcon#flushed, iclass 23, count 0 2006.259.07:36:32.20#ibcon#about to write, iclass 23, count 0 2006.259.07:36:32.20#ibcon#wrote, iclass 23, count 0 2006.259.07:36:32.20#ibcon#about to read 3, iclass 23, count 0 2006.259.07:36:32.24#ibcon#read 3, iclass 23, count 0 2006.259.07:36:32.24#ibcon#about to read 4, iclass 23, count 0 2006.259.07:36:32.24#ibcon#read 4, iclass 23, count 0 2006.259.07:36:32.24#ibcon#about to read 5, iclass 23, count 0 2006.259.07:36:32.24#ibcon#read 5, iclass 23, count 0 2006.259.07:36:32.24#ibcon#about to read 6, iclass 23, count 0 2006.259.07:36:32.24#ibcon#read 6, iclass 23, count 0 2006.259.07:36:32.24#ibcon#end of sib2, iclass 23, count 0 2006.259.07:36:32.24#ibcon#*after write, iclass 23, count 0 2006.259.07:36:32.24#ibcon#*before return 0, iclass 23, count 0 2006.259.07:36:32.24#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.259.07:36:32.24#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.259.07:36:32.24#ibcon#about to clear, iclass 23 cls_cnt 0 2006.259.07:36:32.24#ibcon#cleared, iclass 23 cls_cnt 0 2006.259.07:36:32.24$vc4f8/vb=1,4 2006.259.07:36:32.24#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.259.07:36:32.24#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.259.07:36:32.24#ibcon#ireg 11 cls_cnt 2 2006.259.07:36:32.24#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.259.07:36:32.24#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.259.07:36:32.24#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.259.07:36:32.24#ibcon#enter wrdev, iclass 25, count 2 2006.259.07:36:32.24#ibcon#first serial, iclass 25, count 2 2006.259.07:36:32.24#ibcon#enter sib2, iclass 25, count 2 2006.259.07:36:32.24#ibcon#flushed, iclass 25, count 2 2006.259.07:36:32.24#ibcon#about to write, iclass 25, count 2 2006.259.07:36:32.24#ibcon#wrote, iclass 25, count 2 2006.259.07:36:32.24#ibcon#about to read 3, iclass 25, count 2 2006.259.07:36:32.26#ibcon#read 3, iclass 25, count 2 2006.259.07:36:32.26#ibcon#about to read 4, iclass 25, count 2 2006.259.07:36:32.26#ibcon#read 4, iclass 25, count 2 2006.259.07:36:32.26#ibcon#about to read 5, iclass 25, count 2 2006.259.07:36:32.26#ibcon#read 5, iclass 25, count 2 2006.259.07:36:32.26#ibcon#about to read 6, iclass 25, count 2 2006.259.07:36:32.26#ibcon#read 6, iclass 25, count 2 2006.259.07:36:32.26#ibcon#end of sib2, iclass 25, count 2 2006.259.07:36:32.26#ibcon#*mode == 0, iclass 25, count 2 2006.259.07:36:32.26#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.259.07:36:32.26#ibcon#[27=AT01-04\r\n] 2006.259.07:36:32.26#ibcon#*before write, iclass 25, count 2 2006.259.07:36:32.26#ibcon#enter sib2, iclass 25, count 2 2006.259.07:36:32.26#ibcon#flushed, iclass 25, count 2 2006.259.07:36:32.26#ibcon#about to write, iclass 25, count 2 2006.259.07:36:32.26#ibcon#wrote, iclass 25, count 2 2006.259.07:36:32.26#ibcon#about to read 3, iclass 25, count 2 2006.259.07:36:32.29#ibcon#read 3, iclass 25, count 2 2006.259.07:36:32.29#ibcon#about to read 4, iclass 25, count 2 2006.259.07:36:32.29#ibcon#read 4, iclass 25, count 2 2006.259.07:36:32.29#ibcon#about to read 5, iclass 25, count 2 2006.259.07:36:32.29#ibcon#read 5, iclass 25, count 2 2006.259.07:36:32.29#ibcon#about to read 6, iclass 25, count 2 2006.259.07:36:32.29#ibcon#read 6, iclass 25, count 2 2006.259.07:36:32.29#ibcon#end of sib2, iclass 25, count 2 2006.259.07:36:32.29#ibcon#*after write, iclass 25, count 2 2006.259.07:36:32.29#ibcon#*before return 0, iclass 25, count 2 2006.259.07:36:32.29#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.259.07:36:32.29#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.259.07:36:32.29#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.259.07:36:32.29#ibcon#ireg 7 cls_cnt 0 2006.259.07:36:32.29#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.259.07:36:32.41#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.259.07:36:32.41#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.259.07:36:32.41#ibcon#enter wrdev, iclass 25, count 0 2006.259.07:36:32.41#ibcon#first serial, iclass 25, count 0 2006.259.07:36:32.41#ibcon#enter sib2, iclass 25, count 0 2006.259.07:36:32.41#ibcon#flushed, iclass 25, count 0 2006.259.07:36:32.41#ibcon#about to write, iclass 25, count 0 2006.259.07:36:32.41#ibcon#wrote, iclass 25, count 0 2006.259.07:36:32.41#ibcon#about to read 3, iclass 25, count 0 2006.259.07:36:32.43#ibcon#read 3, iclass 25, count 0 2006.259.07:36:32.43#ibcon#about to read 4, iclass 25, count 0 2006.259.07:36:32.43#ibcon#read 4, iclass 25, count 0 2006.259.07:36:32.43#ibcon#about to read 5, iclass 25, count 0 2006.259.07:36:32.43#ibcon#read 5, iclass 25, count 0 2006.259.07:36:32.43#ibcon#about to read 6, iclass 25, count 0 2006.259.07:36:32.43#ibcon#read 6, iclass 25, count 0 2006.259.07:36:32.43#ibcon#end of sib2, iclass 25, count 0 2006.259.07:36:32.43#ibcon#*mode == 0, iclass 25, count 0 2006.259.07:36:32.43#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.259.07:36:32.43#ibcon#[27=USB\r\n] 2006.259.07:36:32.43#ibcon#*before write, iclass 25, count 0 2006.259.07:36:32.43#ibcon#enter sib2, iclass 25, count 0 2006.259.07:36:32.43#ibcon#flushed, iclass 25, count 0 2006.259.07:36:32.43#ibcon#about to write, iclass 25, count 0 2006.259.07:36:32.43#ibcon#wrote, iclass 25, count 0 2006.259.07:36:32.43#ibcon#about to read 3, iclass 25, count 0 2006.259.07:36:32.46#ibcon#read 3, iclass 25, count 0 2006.259.07:36:32.46#ibcon#about to read 4, iclass 25, count 0 2006.259.07:36:32.46#ibcon#read 4, iclass 25, count 0 2006.259.07:36:32.46#ibcon#about to read 5, iclass 25, count 0 2006.259.07:36:32.46#ibcon#read 5, iclass 25, count 0 2006.259.07:36:32.46#ibcon#about to read 6, iclass 25, count 0 2006.259.07:36:32.46#ibcon#read 6, iclass 25, count 0 2006.259.07:36:32.46#ibcon#end of sib2, iclass 25, count 0 2006.259.07:36:32.46#ibcon#*after write, iclass 25, count 0 2006.259.07:36:32.46#ibcon#*before return 0, iclass 25, count 0 2006.259.07:36:32.46#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.259.07:36:32.46#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.259.07:36:32.46#ibcon#about to clear, iclass 25 cls_cnt 0 2006.259.07:36:32.46#ibcon#cleared, iclass 25 cls_cnt 0 2006.259.07:36:32.46$vc4f8/vblo=2,640.99 2006.259.07:36:32.46#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.259.07:36:32.46#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.259.07:36:32.46#ibcon#ireg 17 cls_cnt 0 2006.259.07:36:32.46#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.259.07:36:32.46#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.259.07:36:32.46#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.259.07:36:32.46#ibcon#enter wrdev, iclass 27, count 0 2006.259.07:36:32.46#ibcon#first serial, iclass 27, count 0 2006.259.07:36:32.46#ibcon#enter sib2, iclass 27, count 0 2006.259.07:36:32.46#ibcon#flushed, iclass 27, count 0 2006.259.07:36:32.46#ibcon#about to write, iclass 27, count 0 2006.259.07:36:32.46#ibcon#wrote, iclass 27, count 0 2006.259.07:36:32.46#ibcon#about to read 3, iclass 27, count 0 2006.259.07:36:32.48#ibcon#read 3, iclass 27, count 0 2006.259.07:36:32.48#ibcon#about to read 4, iclass 27, count 0 2006.259.07:36:32.48#ibcon#read 4, iclass 27, count 0 2006.259.07:36:32.48#ibcon#about to read 5, iclass 27, count 0 2006.259.07:36:32.48#ibcon#read 5, iclass 27, count 0 2006.259.07:36:32.48#ibcon#about to read 6, iclass 27, count 0 2006.259.07:36:32.48#ibcon#read 6, iclass 27, count 0 2006.259.07:36:32.48#ibcon#end of sib2, iclass 27, count 0 2006.259.07:36:32.48#ibcon#*mode == 0, iclass 27, count 0 2006.259.07:36:32.48#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.259.07:36:32.48#ibcon#[28=FRQ=02,640.99\r\n] 2006.259.07:36:32.48#ibcon#*before write, iclass 27, count 0 2006.259.07:36:32.48#ibcon#enter sib2, iclass 27, count 0 2006.259.07:36:32.48#ibcon#flushed, iclass 27, count 0 2006.259.07:36:32.48#ibcon#about to write, iclass 27, count 0 2006.259.07:36:32.48#ibcon#wrote, iclass 27, count 0 2006.259.07:36:32.48#ibcon#about to read 3, iclass 27, count 0 2006.259.07:36:32.52#ibcon#read 3, iclass 27, count 0 2006.259.07:36:32.52#ibcon#about to read 4, iclass 27, count 0 2006.259.07:36:32.52#ibcon#read 4, iclass 27, count 0 2006.259.07:36:32.52#ibcon#about to read 5, iclass 27, count 0 2006.259.07:36:32.52#ibcon#read 5, iclass 27, count 0 2006.259.07:36:32.52#ibcon#about to read 6, iclass 27, count 0 2006.259.07:36:32.52#ibcon#read 6, iclass 27, count 0 2006.259.07:36:32.52#ibcon#end of sib2, iclass 27, count 0 2006.259.07:36:32.52#ibcon#*after write, iclass 27, count 0 2006.259.07:36:32.52#ibcon#*before return 0, iclass 27, count 0 2006.259.07:36:32.52#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.259.07:36:32.52#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.259.07:36:32.52#ibcon#about to clear, iclass 27 cls_cnt 0 2006.259.07:36:32.52#ibcon#cleared, iclass 27 cls_cnt 0 2006.259.07:36:32.52$vc4f8/vb=2,5 2006.259.07:36:32.52#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.259.07:36:32.52#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.259.07:36:32.52#ibcon#ireg 11 cls_cnt 2 2006.259.07:36:32.52#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.259.07:36:32.58#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.259.07:36:32.58#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.259.07:36:32.58#ibcon#enter wrdev, iclass 29, count 2 2006.259.07:36:32.58#ibcon#first serial, iclass 29, count 2 2006.259.07:36:32.58#ibcon#enter sib2, iclass 29, count 2 2006.259.07:36:32.58#ibcon#flushed, iclass 29, count 2 2006.259.07:36:32.58#ibcon#about to write, iclass 29, count 2 2006.259.07:36:32.58#ibcon#wrote, iclass 29, count 2 2006.259.07:36:32.58#ibcon#about to read 3, iclass 29, count 2 2006.259.07:36:32.60#ibcon#read 3, iclass 29, count 2 2006.259.07:36:32.60#ibcon#about to read 4, iclass 29, count 2 2006.259.07:36:32.60#ibcon#read 4, iclass 29, count 2 2006.259.07:36:32.60#ibcon#about to read 5, iclass 29, count 2 2006.259.07:36:32.60#ibcon#read 5, iclass 29, count 2 2006.259.07:36:32.60#ibcon#about to read 6, iclass 29, count 2 2006.259.07:36:32.60#ibcon#read 6, iclass 29, count 2 2006.259.07:36:32.60#ibcon#end of sib2, iclass 29, count 2 2006.259.07:36:32.60#ibcon#*mode == 0, iclass 29, count 2 2006.259.07:36:32.60#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.259.07:36:32.60#ibcon#[27=AT02-05\r\n] 2006.259.07:36:32.60#ibcon#*before write, iclass 29, count 2 2006.259.07:36:32.60#ibcon#enter sib2, iclass 29, count 2 2006.259.07:36:32.60#ibcon#flushed, iclass 29, count 2 2006.259.07:36:32.60#ibcon#about to write, iclass 29, count 2 2006.259.07:36:32.60#ibcon#wrote, iclass 29, count 2 2006.259.07:36:32.60#ibcon#about to read 3, iclass 29, count 2 2006.259.07:36:32.63#ibcon#read 3, iclass 29, count 2 2006.259.07:36:32.63#ibcon#about to read 4, iclass 29, count 2 2006.259.07:36:32.63#ibcon#read 4, iclass 29, count 2 2006.259.07:36:32.63#ibcon#about to read 5, iclass 29, count 2 2006.259.07:36:32.63#ibcon#read 5, iclass 29, count 2 2006.259.07:36:32.63#ibcon#about to read 6, iclass 29, count 2 2006.259.07:36:32.63#ibcon#read 6, iclass 29, count 2 2006.259.07:36:32.63#ibcon#end of sib2, iclass 29, count 2 2006.259.07:36:32.63#ibcon#*after write, iclass 29, count 2 2006.259.07:36:32.63#ibcon#*before return 0, iclass 29, count 2 2006.259.07:36:32.63#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.259.07:36:32.63#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.259.07:36:32.63#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.259.07:36:32.63#ibcon#ireg 7 cls_cnt 0 2006.259.07:36:32.63#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.259.07:36:32.75#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.259.07:36:32.75#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.259.07:36:32.75#ibcon#enter wrdev, iclass 29, count 0 2006.259.07:36:32.75#ibcon#first serial, iclass 29, count 0 2006.259.07:36:32.75#ibcon#enter sib2, iclass 29, count 0 2006.259.07:36:32.75#ibcon#flushed, iclass 29, count 0 2006.259.07:36:32.75#ibcon#about to write, iclass 29, count 0 2006.259.07:36:32.75#ibcon#wrote, iclass 29, count 0 2006.259.07:36:32.75#ibcon#about to read 3, iclass 29, count 0 2006.259.07:36:32.77#ibcon#read 3, iclass 29, count 0 2006.259.07:36:32.77#ibcon#about to read 4, iclass 29, count 0 2006.259.07:36:32.77#ibcon#read 4, iclass 29, count 0 2006.259.07:36:32.77#ibcon#about to read 5, iclass 29, count 0 2006.259.07:36:32.77#ibcon#read 5, iclass 29, count 0 2006.259.07:36:32.77#ibcon#about to read 6, iclass 29, count 0 2006.259.07:36:32.77#ibcon#read 6, iclass 29, count 0 2006.259.07:36:32.77#ibcon#end of sib2, iclass 29, count 0 2006.259.07:36:32.77#ibcon#*mode == 0, iclass 29, count 0 2006.259.07:36:32.77#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.259.07:36:32.77#ibcon#[27=USB\r\n] 2006.259.07:36:32.77#ibcon#*before write, iclass 29, count 0 2006.259.07:36:32.77#ibcon#enter sib2, iclass 29, count 0 2006.259.07:36:32.77#ibcon#flushed, iclass 29, count 0 2006.259.07:36:32.77#ibcon#about to write, iclass 29, count 0 2006.259.07:36:32.77#ibcon#wrote, iclass 29, count 0 2006.259.07:36:32.77#ibcon#about to read 3, iclass 29, count 0 2006.259.07:36:32.80#ibcon#read 3, iclass 29, count 0 2006.259.07:36:32.80#ibcon#about to read 4, iclass 29, count 0 2006.259.07:36:32.80#ibcon#read 4, iclass 29, count 0 2006.259.07:36:32.80#ibcon#about to read 5, iclass 29, count 0 2006.259.07:36:32.80#ibcon#read 5, iclass 29, count 0 2006.259.07:36:32.80#ibcon#about to read 6, iclass 29, count 0 2006.259.07:36:32.80#ibcon#read 6, iclass 29, count 0 2006.259.07:36:32.80#ibcon#end of sib2, iclass 29, count 0 2006.259.07:36:32.80#ibcon#*after write, iclass 29, count 0 2006.259.07:36:32.80#ibcon#*before return 0, iclass 29, count 0 2006.259.07:36:32.80#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.259.07:36:32.80#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.259.07:36:32.80#ibcon#about to clear, iclass 29 cls_cnt 0 2006.259.07:36:32.80#ibcon#cleared, iclass 29 cls_cnt 0 2006.259.07:36:32.80$vc4f8/vblo=3,656.99 2006.259.07:36:32.80#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.259.07:36:32.80#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.259.07:36:32.80#ibcon#ireg 17 cls_cnt 0 2006.259.07:36:32.80#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.259.07:36:32.80#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.259.07:36:32.80#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.259.07:36:32.80#ibcon#enter wrdev, iclass 31, count 0 2006.259.07:36:32.80#ibcon#first serial, iclass 31, count 0 2006.259.07:36:32.80#ibcon#enter sib2, iclass 31, count 0 2006.259.07:36:32.80#ibcon#flushed, iclass 31, count 0 2006.259.07:36:32.80#ibcon#about to write, iclass 31, count 0 2006.259.07:36:32.80#ibcon#wrote, iclass 31, count 0 2006.259.07:36:32.80#ibcon#about to read 3, iclass 31, count 0 2006.259.07:36:32.82#ibcon#read 3, iclass 31, count 0 2006.259.07:36:32.82#ibcon#about to read 4, iclass 31, count 0 2006.259.07:36:32.82#ibcon#read 4, iclass 31, count 0 2006.259.07:36:32.82#ibcon#about to read 5, iclass 31, count 0 2006.259.07:36:32.82#ibcon#read 5, iclass 31, count 0 2006.259.07:36:32.82#ibcon#about to read 6, iclass 31, count 0 2006.259.07:36:32.82#ibcon#read 6, iclass 31, count 0 2006.259.07:36:32.82#ibcon#end of sib2, iclass 31, count 0 2006.259.07:36:32.82#ibcon#*mode == 0, iclass 31, count 0 2006.259.07:36:32.82#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.259.07:36:32.82#ibcon#[28=FRQ=03,656.99\r\n] 2006.259.07:36:32.82#ibcon#*before write, iclass 31, count 0 2006.259.07:36:32.82#ibcon#enter sib2, iclass 31, count 0 2006.259.07:36:32.82#ibcon#flushed, iclass 31, count 0 2006.259.07:36:32.82#ibcon#about to write, iclass 31, count 0 2006.259.07:36:32.82#ibcon#wrote, iclass 31, count 0 2006.259.07:36:32.82#ibcon#about to read 3, iclass 31, count 0 2006.259.07:36:32.86#ibcon#read 3, iclass 31, count 0 2006.259.07:36:32.86#ibcon#about to read 4, iclass 31, count 0 2006.259.07:36:32.86#ibcon#read 4, iclass 31, count 0 2006.259.07:36:32.86#ibcon#about to read 5, iclass 31, count 0 2006.259.07:36:32.86#ibcon#read 5, iclass 31, count 0 2006.259.07:36:32.86#ibcon#about to read 6, iclass 31, count 0 2006.259.07:36:32.86#ibcon#read 6, iclass 31, count 0 2006.259.07:36:32.86#ibcon#end of sib2, iclass 31, count 0 2006.259.07:36:32.86#ibcon#*after write, iclass 31, count 0 2006.259.07:36:32.86#ibcon#*before return 0, iclass 31, count 0 2006.259.07:36:32.86#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.259.07:36:32.86#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.259.07:36:32.86#ibcon#about to clear, iclass 31 cls_cnt 0 2006.259.07:36:32.86#ibcon#cleared, iclass 31 cls_cnt 0 2006.259.07:36:32.86$vc4f8/vb=3,4 2006.259.07:36:32.86#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.259.07:36:32.86#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.259.07:36:32.86#ibcon#ireg 11 cls_cnt 2 2006.259.07:36:32.86#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.259.07:36:32.92#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.259.07:36:32.92#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.259.07:36:32.92#ibcon#enter wrdev, iclass 33, count 2 2006.259.07:36:32.92#ibcon#first serial, iclass 33, count 2 2006.259.07:36:32.92#ibcon#enter sib2, iclass 33, count 2 2006.259.07:36:32.92#ibcon#flushed, iclass 33, count 2 2006.259.07:36:32.92#ibcon#about to write, iclass 33, count 2 2006.259.07:36:32.92#ibcon#wrote, iclass 33, count 2 2006.259.07:36:32.92#ibcon#about to read 3, iclass 33, count 2 2006.259.07:36:32.94#ibcon#read 3, iclass 33, count 2 2006.259.07:36:32.94#ibcon#about to read 4, iclass 33, count 2 2006.259.07:36:32.94#ibcon#read 4, iclass 33, count 2 2006.259.07:36:32.94#ibcon#about to read 5, iclass 33, count 2 2006.259.07:36:32.94#ibcon#read 5, iclass 33, count 2 2006.259.07:36:32.94#ibcon#about to read 6, iclass 33, count 2 2006.259.07:36:32.94#ibcon#read 6, iclass 33, count 2 2006.259.07:36:32.94#ibcon#end of sib2, iclass 33, count 2 2006.259.07:36:32.94#ibcon#*mode == 0, iclass 33, count 2 2006.259.07:36:32.94#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.259.07:36:32.94#ibcon#[27=AT03-04\r\n] 2006.259.07:36:32.94#ibcon#*before write, iclass 33, count 2 2006.259.07:36:32.94#ibcon#enter sib2, iclass 33, count 2 2006.259.07:36:32.94#ibcon#flushed, iclass 33, count 2 2006.259.07:36:32.94#ibcon#about to write, iclass 33, count 2 2006.259.07:36:32.94#ibcon#wrote, iclass 33, count 2 2006.259.07:36:32.94#ibcon#about to read 3, iclass 33, count 2 2006.259.07:36:32.97#ibcon#read 3, iclass 33, count 2 2006.259.07:36:32.97#ibcon#about to read 4, iclass 33, count 2 2006.259.07:36:32.97#ibcon#read 4, iclass 33, count 2 2006.259.07:36:32.97#ibcon#about to read 5, iclass 33, count 2 2006.259.07:36:32.97#ibcon#read 5, iclass 33, count 2 2006.259.07:36:32.97#ibcon#about to read 6, iclass 33, count 2 2006.259.07:36:32.97#ibcon#read 6, iclass 33, count 2 2006.259.07:36:32.97#ibcon#end of sib2, iclass 33, count 2 2006.259.07:36:32.97#ibcon#*after write, iclass 33, count 2 2006.259.07:36:32.97#ibcon#*before return 0, iclass 33, count 2 2006.259.07:36:32.97#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.259.07:36:32.97#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.259.07:36:32.97#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.259.07:36:32.97#ibcon#ireg 7 cls_cnt 0 2006.259.07:36:32.97#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.259.07:36:33.09#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.259.07:36:33.09#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.259.07:36:33.09#ibcon#enter wrdev, iclass 33, count 0 2006.259.07:36:33.09#ibcon#first serial, iclass 33, count 0 2006.259.07:36:33.09#ibcon#enter sib2, iclass 33, count 0 2006.259.07:36:33.09#ibcon#flushed, iclass 33, count 0 2006.259.07:36:33.09#ibcon#about to write, iclass 33, count 0 2006.259.07:36:33.09#ibcon#wrote, iclass 33, count 0 2006.259.07:36:33.09#ibcon#about to read 3, iclass 33, count 0 2006.259.07:36:33.11#ibcon#read 3, iclass 33, count 0 2006.259.07:36:33.11#ibcon#about to read 4, iclass 33, count 0 2006.259.07:36:33.11#ibcon#read 4, iclass 33, count 0 2006.259.07:36:33.11#ibcon#about to read 5, iclass 33, count 0 2006.259.07:36:33.11#ibcon#read 5, iclass 33, count 0 2006.259.07:36:33.11#ibcon#about to read 6, iclass 33, count 0 2006.259.07:36:33.11#ibcon#read 6, iclass 33, count 0 2006.259.07:36:33.11#ibcon#end of sib2, iclass 33, count 0 2006.259.07:36:33.11#ibcon#*mode == 0, iclass 33, count 0 2006.259.07:36:33.11#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.259.07:36:33.11#ibcon#[27=USB\r\n] 2006.259.07:36:33.11#ibcon#*before write, iclass 33, count 0 2006.259.07:36:33.11#ibcon#enter sib2, iclass 33, count 0 2006.259.07:36:33.11#ibcon#flushed, iclass 33, count 0 2006.259.07:36:33.11#ibcon#about to write, iclass 33, count 0 2006.259.07:36:33.11#ibcon#wrote, iclass 33, count 0 2006.259.07:36:33.11#ibcon#about to read 3, iclass 33, count 0 2006.259.07:36:33.14#ibcon#read 3, iclass 33, count 0 2006.259.07:36:33.14#ibcon#about to read 4, iclass 33, count 0 2006.259.07:36:33.14#ibcon#read 4, iclass 33, count 0 2006.259.07:36:33.14#ibcon#about to read 5, iclass 33, count 0 2006.259.07:36:33.14#ibcon#read 5, iclass 33, count 0 2006.259.07:36:33.14#ibcon#about to read 6, iclass 33, count 0 2006.259.07:36:33.14#ibcon#read 6, iclass 33, count 0 2006.259.07:36:33.14#ibcon#end of sib2, iclass 33, count 0 2006.259.07:36:33.14#ibcon#*after write, iclass 33, count 0 2006.259.07:36:33.14#ibcon#*before return 0, iclass 33, count 0 2006.259.07:36:33.14#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.259.07:36:33.14#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.259.07:36:33.14#ibcon#about to clear, iclass 33 cls_cnt 0 2006.259.07:36:33.14#ibcon#cleared, iclass 33 cls_cnt 0 2006.259.07:36:33.14$vc4f8/vblo=4,712.99 2006.259.07:36:33.14#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.259.07:36:33.14#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.259.07:36:33.14#ibcon#ireg 17 cls_cnt 0 2006.259.07:36:33.14#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.259.07:36:33.14#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.259.07:36:33.14#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.259.07:36:33.14#ibcon#enter wrdev, iclass 35, count 0 2006.259.07:36:33.14#ibcon#first serial, iclass 35, count 0 2006.259.07:36:33.14#ibcon#enter sib2, iclass 35, count 0 2006.259.07:36:33.14#ibcon#flushed, iclass 35, count 0 2006.259.07:36:33.14#ibcon#about to write, iclass 35, count 0 2006.259.07:36:33.14#ibcon#wrote, iclass 35, count 0 2006.259.07:36:33.14#ibcon#about to read 3, iclass 35, count 0 2006.259.07:36:33.16#ibcon#read 3, iclass 35, count 0 2006.259.07:36:33.16#ibcon#about to read 4, iclass 35, count 0 2006.259.07:36:33.16#ibcon#read 4, iclass 35, count 0 2006.259.07:36:33.16#ibcon#about to read 5, iclass 35, count 0 2006.259.07:36:33.16#ibcon#read 5, iclass 35, count 0 2006.259.07:36:33.16#ibcon#about to read 6, iclass 35, count 0 2006.259.07:36:33.16#ibcon#read 6, iclass 35, count 0 2006.259.07:36:33.16#ibcon#end of sib2, iclass 35, count 0 2006.259.07:36:33.16#ibcon#*mode == 0, iclass 35, count 0 2006.259.07:36:33.16#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.259.07:36:33.16#ibcon#[28=FRQ=04,712.99\r\n] 2006.259.07:36:33.16#ibcon#*before write, iclass 35, count 0 2006.259.07:36:33.16#ibcon#enter sib2, iclass 35, count 0 2006.259.07:36:33.16#ibcon#flushed, iclass 35, count 0 2006.259.07:36:33.16#ibcon#about to write, iclass 35, count 0 2006.259.07:36:33.16#ibcon#wrote, iclass 35, count 0 2006.259.07:36:33.16#ibcon#about to read 3, iclass 35, count 0 2006.259.07:36:33.20#ibcon#read 3, iclass 35, count 0 2006.259.07:36:33.20#ibcon#about to read 4, iclass 35, count 0 2006.259.07:36:33.20#ibcon#read 4, iclass 35, count 0 2006.259.07:36:33.20#ibcon#about to read 5, iclass 35, count 0 2006.259.07:36:33.20#ibcon#read 5, iclass 35, count 0 2006.259.07:36:33.20#ibcon#about to read 6, iclass 35, count 0 2006.259.07:36:33.20#ibcon#read 6, iclass 35, count 0 2006.259.07:36:33.20#ibcon#end of sib2, iclass 35, count 0 2006.259.07:36:33.20#ibcon#*after write, iclass 35, count 0 2006.259.07:36:33.20#ibcon#*before return 0, iclass 35, count 0 2006.259.07:36:33.20#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.259.07:36:33.20#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.259.07:36:33.20#ibcon#about to clear, iclass 35 cls_cnt 0 2006.259.07:36:33.20#ibcon#cleared, iclass 35 cls_cnt 0 2006.259.07:36:33.20$vc4f8/vb=4,5 2006.259.07:36:33.20#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.259.07:36:33.20#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.259.07:36:33.20#ibcon#ireg 11 cls_cnt 2 2006.259.07:36:33.20#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.259.07:36:33.26#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.259.07:36:33.26#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.259.07:36:33.26#ibcon#enter wrdev, iclass 37, count 2 2006.259.07:36:33.26#ibcon#first serial, iclass 37, count 2 2006.259.07:36:33.26#ibcon#enter sib2, iclass 37, count 2 2006.259.07:36:33.26#ibcon#flushed, iclass 37, count 2 2006.259.07:36:33.26#ibcon#about to write, iclass 37, count 2 2006.259.07:36:33.26#ibcon#wrote, iclass 37, count 2 2006.259.07:36:33.26#ibcon#about to read 3, iclass 37, count 2 2006.259.07:36:33.28#ibcon#read 3, iclass 37, count 2 2006.259.07:36:33.28#ibcon#about to read 4, iclass 37, count 2 2006.259.07:36:33.28#ibcon#read 4, iclass 37, count 2 2006.259.07:36:33.28#ibcon#about to read 5, iclass 37, count 2 2006.259.07:36:33.28#ibcon#read 5, iclass 37, count 2 2006.259.07:36:33.28#ibcon#about to read 6, iclass 37, count 2 2006.259.07:36:33.28#ibcon#read 6, iclass 37, count 2 2006.259.07:36:33.28#ibcon#end of sib2, iclass 37, count 2 2006.259.07:36:33.28#ibcon#*mode == 0, iclass 37, count 2 2006.259.07:36:33.28#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.259.07:36:33.28#ibcon#[27=AT04-05\r\n] 2006.259.07:36:33.28#ibcon#*before write, iclass 37, count 2 2006.259.07:36:33.28#ibcon#enter sib2, iclass 37, count 2 2006.259.07:36:33.28#ibcon#flushed, iclass 37, count 2 2006.259.07:36:33.28#ibcon#about to write, iclass 37, count 2 2006.259.07:36:33.28#ibcon#wrote, iclass 37, count 2 2006.259.07:36:33.28#ibcon#about to read 3, iclass 37, count 2 2006.259.07:36:33.31#ibcon#read 3, iclass 37, count 2 2006.259.07:36:33.31#ibcon#about to read 4, iclass 37, count 2 2006.259.07:36:33.31#ibcon#read 4, iclass 37, count 2 2006.259.07:36:33.31#ibcon#about to read 5, iclass 37, count 2 2006.259.07:36:33.31#ibcon#read 5, iclass 37, count 2 2006.259.07:36:33.31#ibcon#about to read 6, iclass 37, count 2 2006.259.07:36:33.31#ibcon#read 6, iclass 37, count 2 2006.259.07:36:33.31#ibcon#end of sib2, iclass 37, count 2 2006.259.07:36:33.31#ibcon#*after write, iclass 37, count 2 2006.259.07:36:33.31#ibcon#*before return 0, iclass 37, count 2 2006.259.07:36:33.31#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.259.07:36:33.31#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.259.07:36:33.31#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.259.07:36:33.31#ibcon#ireg 7 cls_cnt 0 2006.259.07:36:33.31#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.259.07:36:33.43#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.259.07:36:33.43#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.259.07:36:33.43#ibcon#enter wrdev, iclass 37, count 0 2006.259.07:36:33.43#ibcon#first serial, iclass 37, count 0 2006.259.07:36:33.43#ibcon#enter sib2, iclass 37, count 0 2006.259.07:36:33.43#ibcon#flushed, iclass 37, count 0 2006.259.07:36:33.43#ibcon#about to write, iclass 37, count 0 2006.259.07:36:33.43#ibcon#wrote, iclass 37, count 0 2006.259.07:36:33.43#ibcon#about to read 3, iclass 37, count 0 2006.259.07:36:33.45#ibcon#read 3, iclass 37, count 0 2006.259.07:36:33.45#ibcon#about to read 4, iclass 37, count 0 2006.259.07:36:33.45#ibcon#read 4, iclass 37, count 0 2006.259.07:36:33.45#ibcon#about to read 5, iclass 37, count 0 2006.259.07:36:33.45#ibcon#read 5, iclass 37, count 0 2006.259.07:36:33.45#ibcon#about to read 6, iclass 37, count 0 2006.259.07:36:33.45#ibcon#read 6, iclass 37, count 0 2006.259.07:36:33.45#ibcon#end of sib2, iclass 37, count 0 2006.259.07:36:33.45#ibcon#*mode == 0, iclass 37, count 0 2006.259.07:36:33.45#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.259.07:36:33.45#ibcon#[27=USB\r\n] 2006.259.07:36:33.45#ibcon#*before write, iclass 37, count 0 2006.259.07:36:33.45#ibcon#enter sib2, iclass 37, count 0 2006.259.07:36:33.45#ibcon#flushed, iclass 37, count 0 2006.259.07:36:33.45#ibcon#about to write, iclass 37, count 0 2006.259.07:36:33.45#ibcon#wrote, iclass 37, count 0 2006.259.07:36:33.45#ibcon#about to read 3, iclass 37, count 0 2006.259.07:36:33.48#ibcon#read 3, iclass 37, count 0 2006.259.07:36:33.48#ibcon#about to read 4, iclass 37, count 0 2006.259.07:36:33.48#ibcon#read 4, iclass 37, count 0 2006.259.07:36:33.48#ibcon#about to read 5, iclass 37, count 0 2006.259.07:36:33.48#ibcon#read 5, iclass 37, count 0 2006.259.07:36:33.48#ibcon#about to read 6, iclass 37, count 0 2006.259.07:36:33.48#ibcon#read 6, iclass 37, count 0 2006.259.07:36:33.48#ibcon#end of sib2, iclass 37, count 0 2006.259.07:36:33.48#ibcon#*after write, iclass 37, count 0 2006.259.07:36:33.48#ibcon#*before return 0, iclass 37, count 0 2006.259.07:36:33.48#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.259.07:36:33.48#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.259.07:36:33.48#ibcon#about to clear, iclass 37 cls_cnt 0 2006.259.07:36:33.48#ibcon#cleared, iclass 37 cls_cnt 0 2006.259.07:36:33.48$vc4f8/vblo=5,744.99 2006.259.07:36:33.48#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.259.07:36:33.48#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.259.07:36:33.48#ibcon#ireg 17 cls_cnt 0 2006.259.07:36:33.48#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.259.07:36:33.48#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.259.07:36:33.48#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.259.07:36:33.48#ibcon#enter wrdev, iclass 39, count 0 2006.259.07:36:33.48#ibcon#first serial, iclass 39, count 0 2006.259.07:36:33.48#ibcon#enter sib2, iclass 39, count 0 2006.259.07:36:33.48#ibcon#flushed, iclass 39, count 0 2006.259.07:36:33.48#ibcon#about to write, iclass 39, count 0 2006.259.07:36:33.48#ibcon#wrote, iclass 39, count 0 2006.259.07:36:33.48#ibcon#about to read 3, iclass 39, count 0 2006.259.07:36:33.50#ibcon#read 3, iclass 39, count 0 2006.259.07:36:33.50#ibcon#about to read 4, iclass 39, count 0 2006.259.07:36:33.50#ibcon#read 4, iclass 39, count 0 2006.259.07:36:33.50#ibcon#about to read 5, iclass 39, count 0 2006.259.07:36:33.50#ibcon#read 5, iclass 39, count 0 2006.259.07:36:33.50#ibcon#about to read 6, iclass 39, count 0 2006.259.07:36:33.50#ibcon#read 6, iclass 39, count 0 2006.259.07:36:33.50#ibcon#end of sib2, iclass 39, count 0 2006.259.07:36:33.50#ibcon#*mode == 0, iclass 39, count 0 2006.259.07:36:33.50#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.259.07:36:33.50#ibcon#[28=FRQ=05,744.99\r\n] 2006.259.07:36:33.50#ibcon#*before write, iclass 39, count 0 2006.259.07:36:33.50#ibcon#enter sib2, iclass 39, count 0 2006.259.07:36:33.50#ibcon#flushed, iclass 39, count 0 2006.259.07:36:33.50#ibcon#about to write, iclass 39, count 0 2006.259.07:36:33.50#ibcon#wrote, iclass 39, count 0 2006.259.07:36:33.50#ibcon#about to read 3, iclass 39, count 0 2006.259.07:36:33.54#ibcon#read 3, iclass 39, count 0 2006.259.07:36:33.54#ibcon#about to read 4, iclass 39, count 0 2006.259.07:36:33.54#ibcon#read 4, iclass 39, count 0 2006.259.07:36:33.54#ibcon#about to read 5, iclass 39, count 0 2006.259.07:36:33.54#ibcon#read 5, iclass 39, count 0 2006.259.07:36:33.54#ibcon#about to read 6, iclass 39, count 0 2006.259.07:36:33.54#ibcon#read 6, iclass 39, count 0 2006.259.07:36:33.54#ibcon#end of sib2, iclass 39, count 0 2006.259.07:36:33.54#ibcon#*after write, iclass 39, count 0 2006.259.07:36:33.54#ibcon#*before return 0, iclass 39, count 0 2006.259.07:36:33.54#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.259.07:36:33.54#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.259.07:36:33.54#ibcon#about to clear, iclass 39 cls_cnt 0 2006.259.07:36:33.54#ibcon#cleared, iclass 39 cls_cnt 0 2006.259.07:36:33.54$vc4f8/vb=5,4 2006.259.07:36:33.54#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.259.07:36:33.54#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.259.07:36:33.54#ibcon#ireg 11 cls_cnt 2 2006.259.07:36:33.54#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.259.07:36:33.60#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.259.07:36:33.60#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.259.07:36:33.60#ibcon#enter wrdev, iclass 3, count 2 2006.259.07:36:33.60#ibcon#first serial, iclass 3, count 2 2006.259.07:36:33.60#ibcon#enter sib2, iclass 3, count 2 2006.259.07:36:33.60#ibcon#flushed, iclass 3, count 2 2006.259.07:36:33.60#ibcon#about to write, iclass 3, count 2 2006.259.07:36:33.60#ibcon#wrote, iclass 3, count 2 2006.259.07:36:33.60#ibcon#about to read 3, iclass 3, count 2 2006.259.07:36:33.62#ibcon#read 3, iclass 3, count 2 2006.259.07:36:33.62#ibcon#about to read 4, iclass 3, count 2 2006.259.07:36:33.62#ibcon#read 4, iclass 3, count 2 2006.259.07:36:33.62#ibcon#about to read 5, iclass 3, count 2 2006.259.07:36:33.62#ibcon#read 5, iclass 3, count 2 2006.259.07:36:33.62#ibcon#about to read 6, iclass 3, count 2 2006.259.07:36:33.62#ibcon#read 6, iclass 3, count 2 2006.259.07:36:33.62#ibcon#end of sib2, iclass 3, count 2 2006.259.07:36:33.62#ibcon#*mode == 0, iclass 3, count 2 2006.259.07:36:33.62#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.259.07:36:33.62#ibcon#[27=AT05-04\r\n] 2006.259.07:36:33.62#ibcon#*before write, iclass 3, count 2 2006.259.07:36:33.62#ibcon#enter sib2, iclass 3, count 2 2006.259.07:36:33.62#ibcon#flushed, iclass 3, count 2 2006.259.07:36:33.62#ibcon#about to write, iclass 3, count 2 2006.259.07:36:33.62#ibcon#wrote, iclass 3, count 2 2006.259.07:36:33.62#ibcon#about to read 3, iclass 3, count 2 2006.259.07:36:33.65#ibcon#read 3, iclass 3, count 2 2006.259.07:36:33.65#ibcon#about to read 4, iclass 3, count 2 2006.259.07:36:33.65#ibcon#read 4, iclass 3, count 2 2006.259.07:36:33.65#ibcon#about to read 5, iclass 3, count 2 2006.259.07:36:33.65#ibcon#read 5, iclass 3, count 2 2006.259.07:36:33.65#ibcon#about to read 6, iclass 3, count 2 2006.259.07:36:33.65#ibcon#read 6, iclass 3, count 2 2006.259.07:36:33.65#ibcon#end of sib2, iclass 3, count 2 2006.259.07:36:33.65#ibcon#*after write, iclass 3, count 2 2006.259.07:36:33.65#ibcon#*before return 0, iclass 3, count 2 2006.259.07:36:33.65#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.259.07:36:33.65#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.259.07:36:33.65#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.259.07:36:33.65#ibcon#ireg 7 cls_cnt 0 2006.259.07:36:33.65#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.259.07:36:33.77#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.259.07:36:33.77#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.259.07:36:33.77#ibcon#enter wrdev, iclass 3, count 0 2006.259.07:36:33.77#ibcon#first serial, iclass 3, count 0 2006.259.07:36:33.77#ibcon#enter sib2, iclass 3, count 0 2006.259.07:36:33.77#ibcon#flushed, iclass 3, count 0 2006.259.07:36:33.77#ibcon#about to write, iclass 3, count 0 2006.259.07:36:33.77#ibcon#wrote, iclass 3, count 0 2006.259.07:36:33.77#ibcon#about to read 3, iclass 3, count 0 2006.259.07:36:33.79#ibcon#read 3, iclass 3, count 0 2006.259.07:36:33.79#ibcon#about to read 4, iclass 3, count 0 2006.259.07:36:33.79#ibcon#read 4, iclass 3, count 0 2006.259.07:36:33.79#ibcon#about to read 5, iclass 3, count 0 2006.259.07:36:33.79#ibcon#read 5, iclass 3, count 0 2006.259.07:36:33.79#ibcon#about to read 6, iclass 3, count 0 2006.259.07:36:33.79#ibcon#read 6, iclass 3, count 0 2006.259.07:36:33.79#ibcon#end of sib2, iclass 3, count 0 2006.259.07:36:33.79#ibcon#*mode == 0, iclass 3, count 0 2006.259.07:36:33.79#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.259.07:36:33.79#ibcon#[27=USB\r\n] 2006.259.07:36:33.79#ibcon#*before write, iclass 3, count 0 2006.259.07:36:33.79#ibcon#enter sib2, iclass 3, count 0 2006.259.07:36:33.79#ibcon#flushed, iclass 3, count 0 2006.259.07:36:33.79#ibcon#about to write, iclass 3, count 0 2006.259.07:36:33.79#ibcon#wrote, iclass 3, count 0 2006.259.07:36:33.79#ibcon#about to read 3, iclass 3, count 0 2006.259.07:36:33.82#ibcon#read 3, iclass 3, count 0 2006.259.07:36:33.82#ibcon#about to read 4, iclass 3, count 0 2006.259.07:36:33.82#ibcon#read 4, iclass 3, count 0 2006.259.07:36:33.82#ibcon#about to read 5, iclass 3, count 0 2006.259.07:36:33.82#ibcon#read 5, iclass 3, count 0 2006.259.07:36:33.82#ibcon#about to read 6, iclass 3, count 0 2006.259.07:36:33.82#ibcon#read 6, iclass 3, count 0 2006.259.07:36:33.82#ibcon#end of sib2, iclass 3, count 0 2006.259.07:36:33.82#ibcon#*after write, iclass 3, count 0 2006.259.07:36:33.82#ibcon#*before return 0, iclass 3, count 0 2006.259.07:36:33.82#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.259.07:36:33.82#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.259.07:36:33.82#ibcon#about to clear, iclass 3 cls_cnt 0 2006.259.07:36:33.82#ibcon#cleared, iclass 3 cls_cnt 0 2006.259.07:36:33.82$vc4f8/vblo=6,752.99 2006.259.07:36:33.82#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.259.07:36:33.82#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.259.07:36:33.82#ibcon#ireg 17 cls_cnt 0 2006.259.07:36:33.82#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.259.07:36:33.82#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.259.07:36:33.82#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.259.07:36:33.82#ibcon#enter wrdev, iclass 5, count 0 2006.259.07:36:33.82#ibcon#first serial, iclass 5, count 0 2006.259.07:36:33.82#ibcon#enter sib2, iclass 5, count 0 2006.259.07:36:33.82#ibcon#flushed, iclass 5, count 0 2006.259.07:36:33.82#ibcon#about to write, iclass 5, count 0 2006.259.07:36:33.82#ibcon#wrote, iclass 5, count 0 2006.259.07:36:33.82#ibcon#about to read 3, iclass 5, count 0 2006.259.07:36:33.84#ibcon#read 3, iclass 5, count 0 2006.259.07:36:33.84#ibcon#about to read 4, iclass 5, count 0 2006.259.07:36:33.84#ibcon#read 4, iclass 5, count 0 2006.259.07:36:33.84#ibcon#about to read 5, iclass 5, count 0 2006.259.07:36:33.84#ibcon#read 5, iclass 5, count 0 2006.259.07:36:33.84#ibcon#about to read 6, iclass 5, count 0 2006.259.07:36:33.84#ibcon#read 6, iclass 5, count 0 2006.259.07:36:33.84#ibcon#end of sib2, iclass 5, count 0 2006.259.07:36:33.84#ibcon#*mode == 0, iclass 5, count 0 2006.259.07:36:33.84#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.259.07:36:33.84#ibcon#[28=FRQ=06,752.99\r\n] 2006.259.07:36:33.84#ibcon#*before write, iclass 5, count 0 2006.259.07:36:33.84#ibcon#enter sib2, iclass 5, count 0 2006.259.07:36:33.84#ibcon#flushed, iclass 5, count 0 2006.259.07:36:33.84#ibcon#about to write, iclass 5, count 0 2006.259.07:36:33.84#ibcon#wrote, iclass 5, count 0 2006.259.07:36:33.84#ibcon#about to read 3, iclass 5, count 0 2006.259.07:36:33.88#ibcon#read 3, iclass 5, count 0 2006.259.07:36:33.88#ibcon#about to read 4, iclass 5, count 0 2006.259.07:36:33.88#ibcon#read 4, iclass 5, count 0 2006.259.07:36:33.88#ibcon#about to read 5, iclass 5, count 0 2006.259.07:36:33.88#ibcon#read 5, iclass 5, count 0 2006.259.07:36:33.88#ibcon#about to read 6, iclass 5, count 0 2006.259.07:36:33.88#ibcon#read 6, iclass 5, count 0 2006.259.07:36:33.88#ibcon#end of sib2, iclass 5, count 0 2006.259.07:36:33.88#ibcon#*after write, iclass 5, count 0 2006.259.07:36:33.88#ibcon#*before return 0, iclass 5, count 0 2006.259.07:36:33.88#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.259.07:36:33.88#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.259.07:36:33.88#ibcon#about to clear, iclass 5 cls_cnt 0 2006.259.07:36:33.88#ibcon#cleared, iclass 5 cls_cnt 0 2006.259.07:36:33.88$vc4f8/vb=6,4 2006.259.07:36:33.88#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.259.07:36:33.88#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.259.07:36:33.88#ibcon#ireg 11 cls_cnt 2 2006.259.07:36:33.88#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.259.07:36:33.94#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.259.07:36:33.94#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.259.07:36:33.94#ibcon#enter wrdev, iclass 7, count 2 2006.259.07:36:33.94#ibcon#first serial, iclass 7, count 2 2006.259.07:36:33.94#ibcon#enter sib2, iclass 7, count 2 2006.259.07:36:33.94#ibcon#flushed, iclass 7, count 2 2006.259.07:36:33.94#ibcon#about to write, iclass 7, count 2 2006.259.07:36:33.94#ibcon#wrote, iclass 7, count 2 2006.259.07:36:33.94#ibcon#about to read 3, iclass 7, count 2 2006.259.07:36:33.96#ibcon#read 3, iclass 7, count 2 2006.259.07:36:33.96#ibcon#about to read 4, iclass 7, count 2 2006.259.07:36:33.96#ibcon#read 4, iclass 7, count 2 2006.259.07:36:33.96#ibcon#about to read 5, iclass 7, count 2 2006.259.07:36:33.96#ibcon#read 5, iclass 7, count 2 2006.259.07:36:33.96#ibcon#about to read 6, iclass 7, count 2 2006.259.07:36:33.96#ibcon#read 6, iclass 7, count 2 2006.259.07:36:33.96#ibcon#end of sib2, iclass 7, count 2 2006.259.07:36:33.96#ibcon#*mode == 0, iclass 7, count 2 2006.259.07:36:33.96#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.259.07:36:33.96#ibcon#[27=AT06-04\r\n] 2006.259.07:36:33.96#ibcon#*before write, iclass 7, count 2 2006.259.07:36:33.96#ibcon#enter sib2, iclass 7, count 2 2006.259.07:36:33.96#ibcon#flushed, iclass 7, count 2 2006.259.07:36:33.96#ibcon#about to write, iclass 7, count 2 2006.259.07:36:33.96#ibcon#wrote, iclass 7, count 2 2006.259.07:36:33.96#ibcon#about to read 3, iclass 7, count 2 2006.259.07:36:33.99#ibcon#read 3, iclass 7, count 2 2006.259.07:36:33.99#ibcon#about to read 4, iclass 7, count 2 2006.259.07:36:33.99#ibcon#read 4, iclass 7, count 2 2006.259.07:36:33.99#ibcon#about to read 5, iclass 7, count 2 2006.259.07:36:33.99#ibcon#read 5, iclass 7, count 2 2006.259.07:36:33.99#ibcon#about to read 6, iclass 7, count 2 2006.259.07:36:33.99#ibcon#read 6, iclass 7, count 2 2006.259.07:36:33.99#ibcon#end of sib2, iclass 7, count 2 2006.259.07:36:33.99#ibcon#*after write, iclass 7, count 2 2006.259.07:36:33.99#ibcon#*before return 0, iclass 7, count 2 2006.259.07:36:33.99#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.259.07:36:33.99#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.259.07:36:33.99#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.259.07:36:33.99#ibcon#ireg 7 cls_cnt 0 2006.259.07:36:33.99#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.259.07:36:34.11#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.259.07:36:34.11#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.259.07:36:34.11#ibcon#enter wrdev, iclass 7, count 0 2006.259.07:36:34.11#ibcon#first serial, iclass 7, count 0 2006.259.07:36:34.11#ibcon#enter sib2, iclass 7, count 0 2006.259.07:36:34.11#ibcon#flushed, iclass 7, count 0 2006.259.07:36:34.11#ibcon#about to write, iclass 7, count 0 2006.259.07:36:34.11#ibcon#wrote, iclass 7, count 0 2006.259.07:36:34.11#ibcon#about to read 3, iclass 7, count 0 2006.259.07:36:34.13#ibcon#read 3, iclass 7, count 0 2006.259.07:36:34.13#ibcon#about to read 4, iclass 7, count 0 2006.259.07:36:34.13#ibcon#read 4, iclass 7, count 0 2006.259.07:36:34.13#ibcon#about to read 5, iclass 7, count 0 2006.259.07:36:34.13#ibcon#read 5, iclass 7, count 0 2006.259.07:36:34.13#ibcon#about to read 6, iclass 7, count 0 2006.259.07:36:34.13#ibcon#read 6, iclass 7, count 0 2006.259.07:36:34.13#ibcon#end of sib2, iclass 7, count 0 2006.259.07:36:34.13#ibcon#*mode == 0, iclass 7, count 0 2006.259.07:36:34.13#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.259.07:36:34.13#ibcon#[27=USB\r\n] 2006.259.07:36:34.13#ibcon#*before write, iclass 7, count 0 2006.259.07:36:34.13#ibcon#enter sib2, iclass 7, count 0 2006.259.07:36:34.13#ibcon#flushed, iclass 7, count 0 2006.259.07:36:34.13#ibcon#about to write, iclass 7, count 0 2006.259.07:36:34.13#ibcon#wrote, iclass 7, count 0 2006.259.07:36:34.13#ibcon#about to read 3, iclass 7, count 0 2006.259.07:36:34.16#ibcon#read 3, iclass 7, count 0 2006.259.07:36:34.16#ibcon#about to read 4, iclass 7, count 0 2006.259.07:36:34.16#ibcon#read 4, iclass 7, count 0 2006.259.07:36:34.16#ibcon#about to read 5, iclass 7, count 0 2006.259.07:36:34.16#ibcon#read 5, iclass 7, count 0 2006.259.07:36:34.16#ibcon#about to read 6, iclass 7, count 0 2006.259.07:36:34.16#ibcon#read 6, iclass 7, count 0 2006.259.07:36:34.16#ibcon#end of sib2, iclass 7, count 0 2006.259.07:36:34.16#ibcon#*after write, iclass 7, count 0 2006.259.07:36:34.16#ibcon#*before return 0, iclass 7, count 0 2006.259.07:36:34.16#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.259.07:36:34.16#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.259.07:36:34.16#ibcon#about to clear, iclass 7 cls_cnt 0 2006.259.07:36:34.16#ibcon#cleared, iclass 7 cls_cnt 0 2006.259.07:36:34.16$vc4f8/vabw=wide 2006.259.07:36:34.16#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.259.07:36:34.16#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.259.07:36:34.16#ibcon#ireg 8 cls_cnt 0 2006.259.07:36:34.16#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.259.07:36:34.16#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.259.07:36:34.16#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.259.07:36:34.16#ibcon#enter wrdev, iclass 11, count 0 2006.259.07:36:34.16#ibcon#first serial, iclass 11, count 0 2006.259.07:36:34.16#ibcon#enter sib2, iclass 11, count 0 2006.259.07:36:34.16#ibcon#flushed, iclass 11, count 0 2006.259.07:36:34.16#ibcon#about to write, iclass 11, count 0 2006.259.07:36:34.16#ibcon#wrote, iclass 11, count 0 2006.259.07:36:34.16#ibcon#about to read 3, iclass 11, count 0 2006.259.07:36:34.18#ibcon#read 3, iclass 11, count 0 2006.259.07:36:34.18#ibcon#about to read 4, iclass 11, count 0 2006.259.07:36:34.18#ibcon#read 4, iclass 11, count 0 2006.259.07:36:34.18#ibcon#about to read 5, iclass 11, count 0 2006.259.07:36:34.18#ibcon#read 5, iclass 11, count 0 2006.259.07:36:34.18#ibcon#about to read 6, iclass 11, count 0 2006.259.07:36:34.18#ibcon#read 6, iclass 11, count 0 2006.259.07:36:34.18#ibcon#end of sib2, iclass 11, count 0 2006.259.07:36:34.18#ibcon#*mode == 0, iclass 11, count 0 2006.259.07:36:34.18#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.259.07:36:34.18#ibcon#[25=BW32\r\n] 2006.259.07:36:34.18#ibcon#*before write, iclass 11, count 0 2006.259.07:36:34.18#ibcon#enter sib2, iclass 11, count 0 2006.259.07:36:34.18#ibcon#flushed, iclass 11, count 0 2006.259.07:36:34.18#ibcon#about to write, iclass 11, count 0 2006.259.07:36:34.18#ibcon#wrote, iclass 11, count 0 2006.259.07:36:34.18#ibcon#about to read 3, iclass 11, count 0 2006.259.07:36:34.21#ibcon#read 3, iclass 11, count 0 2006.259.07:36:34.21#ibcon#about to read 4, iclass 11, count 0 2006.259.07:36:34.21#ibcon#read 4, iclass 11, count 0 2006.259.07:36:34.21#ibcon#about to read 5, iclass 11, count 0 2006.259.07:36:34.21#ibcon#read 5, iclass 11, count 0 2006.259.07:36:34.21#ibcon#about to read 6, iclass 11, count 0 2006.259.07:36:34.21#ibcon#read 6, iclass 11, count 0 2006.259.07:36:34.21#ibcon#end of sib2, iclass 11, count 0 2006.259.07:36:34.21#ibcon#*after write, iclass 11, count 0 2006.259.07:36:34.21#ibcon#*before return 0, iclass 11, count 0 2006.259.07:36:34.21#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.259.07:36:34.21#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.259.07:36:34.21#ibcon#about to clear, iclass 11 cls_cnt 0 2006.259.07:36:34.21#ibcon#cleared, iclass 11 cls_cnt 0 2006.259.07:36:34.21$vc4f8/vbbw=wide 2006.259.07:36:34.21#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.259.07:36:34.21#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.259.07:36:34.21#ibcon#ireg 8 cls_cnt 0 2006.259.07:36:34.21#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.259.07:36:34.28#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.259.07:36:34.28#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.259.07:36:34.28#ibcon#enter wrdev, iclass 13, count 0 2006.259.07:36:34.28#ibcon#first serial, iclass 13, count 0 2006.259.07:36:34.28#ibcon#enter sib2, iclass 13, count 0 2006.259.07:36:34.28#ibcon#flushed, iclass 13, count 0 2006.259.07:36:34.28#ibcon#about to write, iclass 13, count 0 2006.259.07:36:34.28#ibcon#wrote, iclass 13, count 0 2006.259.07:36:34.28#ibcon#about to read 3, iclass 13, count 0 2006.259.07:36:34.30#ibcon#read 3, iclass 13, count 0 2006.259.07:36:34.30#ibcon#about to read 4, iclass 13, count 0 2006.259.07:36:34.30#ibcon#read 4, iclass 13, count 0 2006.259.07:36:34.30#ibcon#about to read 5, iclass 13, count 0 2006.259.07:36:34.30#ibcon#read 5, iclass 13, count 0 2006.259.07:36:34.30#ibcon#about to read 6, iclass 13, count 0 2006.259.07:36:34.30#ibcon#read 6, iclass 13, count 0 2006.259.07:36:34.30#ibcon#end of sib2, iclass 13, count 0 2006.259.07:36:34.30#ibcon#*mode == 0, iclass 13, count 0 2006.259.07:36:34.30#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.259.07:36:34.30#ibcon#[27=BW32\r\n] 2006.259.07:36:34.30#ibcon#*before write, iclass 13, count 0 2006.259.07:36:34.30#ibcon#enter sib2, iclass 13, count 0 2006.259.07:36:34.30#ibcon#flushed, iclass 13, count 0 2006.259.07:36:34.30#ibcon#about to write, iclass 13, count 0 2006.259.07:36:34.30#ibcon#wrote, iclass 13, count 0 2006.259.07:36:34.30#ibcon#about to read 3, iclass 13, count 0 2006.259.07:36:34.33#ibcon#read 3, iclass 13, count 0 2006.259.07:36:34.33#ibcon#about to read 4, iclass 13, count 0 2006.259.07:36:34.33#ibcon#read 4, iclass 13, count 0 2006.259.07:36:34.33#ibcon#about to read 5, iclass 13, count 0 2006.259.07:36:34.33#ibcon#read 5, iclass 13, count 0 2006.259.07:36:34.33#ibcon#about to read 6, iclass 13, count 0 2006.259.07:36:34.33#ibcon#read 6, iclass 13, count 0 2006.259.07:36:34.33#ibcon#end of sib2, iclass 13, count 0 2006.259.07:36:34.33#ibcon#*after write, iclass 13, count 0 2006.259.07:36:34.33#ibcon#*before return 0, iclass 13, count 0 2006.259.07:36:34.33#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.259.07:36:34.33#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.259.07:36:34.33#ibcon#about to clear, iclass 13 cls_cnt 0 2006.259.07:36:34.33#ibcon#cleared, iclass 13 cls_cnt 0 2006.259.07:36:34.33$4f8m12a/ifd4f 2006.259.07:36:34.33$ifd4f/lo= 2006.259.07:36:34.33$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.259.07:36:34.33$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.259.07:36:34.33$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.259.07:36:34.33$ifd4f/patch= 2006.259.07:36:34.33$ifd4f/patch=lo1,a1,a2,a3,a4 2006.259.07:36:34.33$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.259.07:36:34.33$ifd4f/patch=lo3,a5,a6,a7,a8 2006.259.07:36:34.33$4f8m12a/"form=m,16.000,1:2 2006.259.07:36:34.33$4f8m12a/"tpicd 2006.259.07:36:34.33$4f8m12a/echo=off 2006.259.07:36:34.33$4f8m12a/xlog=off 2006.259.07:36:34.33:!2006.259.07:37:00 2006.259.07:36:41.14#trakl#Source acquired 2006.259.07:36:42.14#flagr#flagr/antenna,acquired 2006.259.07:37:00.00:preob 2006.259.07:37:01.14/onsource/TRACKING 2006.259.07:37:01.14:!2006.259.07:37:10 2006.259.07:37:10.00:data_valid=on 2006.259.07:37:10.00:midob 2006.259.07:37:10.14/onsource/TRACKING 2006.259.07:37:10.14/wx/22.32,1012.9,84 2006.259.07:37:10.32/cable/+6.4587E-03 2006.259.07:37:11.41/va/01,08,usb,yes,30,32 2006.259.07:37:11.41/va/02,07,usb,yes,30,32 2006.259.07:37:11.41/va/03,08,usb,yes,23,23 2006.259.07:37:11.41/va/04,07,usb,yes,31,34 2006.259.07:37:11.41/va/05,07,usb,yes,35,37 2006.259.07:37:11.41/va/06,06,usb,yes,34,34 2006.259.07:37:11.41/va/07,06,usb,yes,35,35 2006.259.07:37:11.41/va/08,06,usb,yes,37,37 2006.259.07:37:11.64/valo/01,532.99,yes,locked 2006.259.07:37:11.64/valo/02,572.99,yes,locked 2006.259.07:37:11.64/valo/03,672.99,yes,locked 2006.259.07:37:11.64/valo/04,832.99,yes,locked 2006.259.07:37:11.64/valo/05,652.99,yes,locked 2006.259.07:37:11.64/valo/06,772.99,yes,locked 2006.259.07:37:11.64/valo/07,832.99,yes,locked 2006.259.07:37:11.64/valo/08,852.99,yes,locked 2006.259.07:37:12.73/vb/01,04,usb,yes,30,29 2006.259.07:37:12.73/vb/02,05,usb,yes,28,29 2006.259.07:37:12.73/vb/03,04,usb,yes,28,32 2006.259.07:37:12.73/vb/04,05,usb,yes,26,26 2006.259.07:37:12.73/vb/05,04,usb,yes,27,31 2006.259.07:37:12.73/vb/06,04,usb,yes,28,31 2006.259.07:37:12.73/vb/07,04,usb,yes,31,30 2006.259.07:37:12.73/vb/08,04,usb,yes,28,31 2006.259.07:37:12.97/vblo/01,632.99,yes,locked 2006.259.07:37:12.97/vblo/02,640.99,yes,locked 2006.259.07:37:12.97/vblo/03,656.99,yes,locked 2006.259.07:37:12.97/vblo/04,712.99,yes,locked 2006.259.07:37:12.97/vblo/05,744.99,yes,locked 2006.259.07:37:12.97/vblo/06,752.99,yes,locked 2006.259.07:37:12.97/vblo/07,734.99,yes,locked 2006.259.07:37:12.97/vblo/08,744.99,yes,locked 2006.259.07:37:13.12/vabw/8 2006.259.07:37:13.27/vbbw/8 2006.259.07:37:13.40/xfe/off,on,15.2 2006.259.07:37:13.77/ifatt/23,28,28,28 2006.259.07:37:14.08/fmout-gps/S +4.50E-07 2006.259.07:37:14.12:!2006.259.07:38:10 2006.259.07:38:10.00:data_valid=off 2006.259.07:38:10.00:postob 2006.259.07:38:10.20/cable/+6.4584E-03 2006.259.07:38:10.20/wx/22.31,1012.9,84 2006.259.07:38:11.08/fmout-gps/S +4.50E-07 2006.259.07:38:11.08:scan_name=259-0739,k06259,60 2006.259.07:38:11.09:source=0955+476,095819.67,472507.8,2000.0,ccw 2006.259.07:38:11.14#flagr#flagr/antenna,new-source 2006.259.07:38:12.14:checkk5 2006.259.07:38:12.58/chk_autoobs//k5ts1/ autoobs is running! 2006.259.07:38:13.24/chk_autoobs//k5ts2/ autoobs is running! 2006.259.07:38:13.69/chk_autoobs//k5ts3/ autoobs is running! 2006.259.07:38:14.11/chk_autoobs//k5ts4/ autoobs is running! 2006.259.07:38:14.51/chk_obsdata//k5ts1/T2590737??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.259.07:38:14.97/chk_obsdata//k5ts2/T2590737??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.259.07:38:15.40/chk_obsdata//k5ts3/T2590737??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.259.07:38:15.81/chk_obsdata//k5ts4/T2590737??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.259.07:38:16.59/k5log//k5ts1_log_newline 2006.259.07:38:17.54/k5log//k5ts2_log_newline 2006.259.07:38:18.31/k5log//k5ts3_log_newline 2006.259.07:38:19.09/k5log//k5ts4_log_newline 2006.259.07:38:19.12/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.259.07:38:19.12:4f8m12a=1 2006.259.07:38:19.12$4f8m12a/echo=on 2006.259.07:38:19.12$4f8m12a/pcalon 2006.259.07:38:19.12$pcalon/"no phase cal control is implemented here 2006.259.07:38:19.12$4f8m12a/"tpicd=stop 2006.259.07:38:19.12$4f8m12a/vc4f8 2006.259.07:38:19.12$vc4f8/valo=1,532.99 2006.259.07:38:19.12#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.259.07:38:19.12#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.259.07:38:19.12#ibcon#ireg 17 cls_cnt 0 2006.259.07:38:19.12#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.259.07:38:19.12#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.259.07:38:19.12#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.259.07:38:19.12#ibcon#enter wrdev, iclass 20, count 0 2006.259.07:38:19.12#ibcon#first serial, iclass 20, count 0 2006.259.07:38:19.12#ibcon#enter sib2, iclass 20, count 0 2006.259.07:38:19.12#ibcon#flushed, iclass 20, count 0 2006.259.07:38:19.12#ibcon#about to write, iclass 20, count 0 2006.259.07:38:19.12#ibcon#wrote, iclass 20, count 0 2006.259.07:38:19.12#ibcon#about to read 3, iclass 20, count 0 2006.259.07:38:19.13#ibcon#read 3, iclass 20, count 0 2006.259.07:38:19.13#ibcon#about to read 4, iclass 20, count 0 2006.259.07:38:19.13#ibcon#read 4, iclass 20, count 0 2006.259.07:38:19.13#ibcon#about to read 5, iclass 20, count 0 2006.259.07:38:19.13#ibcon#read 5, iclass 20, count 0 2006.259.07:38:19.13#ibcon#about to read 6, iclass 20, count 0 2006.259.07:38:19.13#ibcon#read 6, iclass 20, count 0 2006.259.07:38:19.13#ibcon#end of sib2, iclass 20, count 0 2006.259.07:38:19.13#ibcon#*mode == 0, iclass 20, count 0 2006.259.07:38:19.13#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.259.07:38:19.13#ibcon#[26=FRQ=01,532.99\r\n] 2006.259.07:38:19.13#ibcon#*before write, iclass 20, count 0 2006.259.07:38:19.13#ibcon#enter sib2, iclass 20, count 0 2006.259.07:38:19.13#ibcon#flushed, iclass 20, count 0 2006.259.07:38:19.13#ibcon#about to write, iclass 20, count 0 2006.259.07:38:19.13#ibcon#wrote, iclass 20, count 0 2006.259.07:38:19.13#ibcon#about to read 3, iclass 20, count 0 2006.259.07:38:19.18#ibcon#read 3, iclass 20, count 0 2006.259.07:38:19.18#ibcon#about to read 4, iclass 20, count 0 2006.259.07:38:19.18#ibcon#read 4, iclass 20, count 0 2006.259.07:38:19.18#ibcon#about to read 5, iclass 20, count 0 2006.259.07:38:19.18#ibcon#read 5, iclass 20, count 0 2006.259.07:38:19.18#ibcon#about to read 6, iclass 20, count 0 2006.259.07:38:19.18#ibcon#read 6, iclass 20, count 0 2006.259.07:38:19.18#ibcon#end of sib2, iclass 20, count 0 2006.259.07:38:19.18#ibcon#*after write, iclass 20, count 0 2006.259.07:38:19.18#ibcon#*before return 0, iclass 20, count 0 2006.259.07:38:19.18#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.259.07:38:19.18#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.259.07:38:19.18#ibcon#about to clear, iclass 20 cls_cnt 0 2006.259.07:38:19.18#ibcon#cleared, iclass 20 cls_cnt 0 2006.259.07:38:19.18$vc4f8/va=1,8 2006.259.07:38:19.18#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.259.07:38:19.18#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.259.07:38:19.18#ibcon#ireg 11 cls_cnt 2 2006.259.07:38:19.18#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.259.07:38:19.18#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.259.07:38:19.18#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.259.07:38:19.18#ibcon#enter wrdev, iclass 22, count 2 2006.259.07:38:19.18#ibcon#first serial, iclass 22, count 2 2006.259.07:38:19.18#ibcon#enter sib2, iclass 22, count 2 2006.259.07:38:19.18#ibcon#flushed, iclass 22, count 2 2006.259.07:38:19.18#ibcon#about to write, iclass 22, count 2 2006.259.07:38:19.18#ibcon#wrote, iclass 22, count 2 2006.259.07:38:19.18#ibcon#about to read 3, iclass 22, count 2 2006.259.07:38:19.20#ibcon#read 3, iclass 22, count 2 2006.259.07:38:19.20#ibcon#about to read 4, iclass 22, count 2 2006.259.07:38:19.20#ibcon#read 4, iclass 22, count 2 2006.259.07:38:19.20#ibcon#about to read 5, iclass 22, count 2 2006.259.07:38:19.20#ibcon#read 5, iclass 22, count 2 2006.259.07:38:19.20#ibcon#about to read 6, iclass 22, count 2 2006.259.07:38:19.20#ibcon#read 6, iclass 22, count 2 2006.259.07:38:19.20#ibcon#end of sib2, iclass 22, count 2 2006.259.07:38:19.20#ibcon#*mode == 0, iclass 22, count 2 2006.259.07:38:19.20#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.259.07:38:19.20#ibcon#[25=AT01-08\r\n] 2006.259.07:38:19.20#ibcon#*before write, iclass 22, count 2 2006.259.07:38:19.20#ibcon#enter sib2, iclass 22, count 2 2006.259.07:38:19.20#ibcon#flushed, iclass 22, count 2 2006.259.07:38:19.20#ibcon#about to write, iclass 22, count 2 2006.259.07:38:19.20#ibcon#wrote, iclass 22, count 2 2006.259.07:38:19.20#ibcon#about to read 3, iclass 22, count 2 2006.259.07:38:19.23#ibcon#read 3, iclass 22, count 2 2006.259.07:38:19.23#ibcon#about to read 4, iclass 22, count 2 2006.259.07:38:19.23#ibcon#read 4, iclass 22, count 2 2006.259.07:38:19.23#ibcon#about to read 5, iclass 22, count 2 2006.259.07:38:19.23#ibcon#read 5, iclass 22, count 2 2006.259.07:38:19.23#ibcon#about to read 6, iclass 22, count 2 2006.259.07:38:19.23#ibcon#read 6, iclass 22, count 2 2006.259.07:38:19.23#ibcon#end of sib2, iclass 22, count 2 2006.259.07:38:19.23#ibcon#*after write, iclass 22, count 2 2006.259.07:38:19.23#ibcon#*before return 0, iclass 22, count 2 2006.259.07:38:19.23#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.259.07:38:19.23#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.259.07:38:19.23#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.259.07:38:19.23#ibcon#ireg 7 cls_cnt 0 2006.259.07:38:19.23#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.259.07:38:19.36#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.259.07:38:19.36#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.259.07:38:19.36#ibcon#enter wrdev, iclass 22, count 0 2006.259.07:38:19.36#ibcon#first serial, iclass 22, count 0 2006.259.07:38:19.36#ibcon#enter sib2, iclass 22, count 0 2006.259.07:38:19.36#ibcon#flushed, iclass 22, count 0 2006.259.07:38:19.36#ibcon#about to write, iclass 22, count 0 2006.259.07:38:19.36#ibcon#wrote, iclass 22, count 0 2006.259.07:38:19.36#ibcon#about to read 3, iclass 22, count 0 2006.259.07:38:19.38#ibcon#read 3, iclass 22, count 0 2006.259.07:38:19.38#ibcon#about to read 4, iclass 22, count 0 2006.259.07:38:19.38#ibcon#read 4, iclass 22, count 0 2006.259.07:38:19.38#ibcon#about to read 5, iclass 22, count 0 2006.259.07:38:19.38#ibcon#read 5, iclass 22, count 0 2006.259.07:38:19.38#ibcon#about to read 6, iclass 22, count 0 2006.259.07:38:19.38#ibcon#read 6, iclass 22, count 0 2006.259.07:38:19.38#ibcon#end of sib2, iclass 22, count 0 2006.259.07:38:19.38#ibcon#*mode == 0, iclass 22, count 0 2006.259.07:38:19.38#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.259.07:38:19.38#ibcon#[25=USB\r\n] 2006.259.07:38:19.38#ibcon#*before write, iclass 22, count 0 2006.259.07:38:19.38#ibcon#enter sib2, iclass 22, count 0 2006.259.07:38:19.38#ibcon#flushed, iclass 22, count 0 2006.259.07:38:19.38#ibcon#about to write, iclass 22, count 0 2006.259.07:38:19.38#ibcon#wrote, iclass 22, count 0 2006.259.07:38:19.38#ibcon#about to read 3, iclass 22, count 0 2006.259.07:38:19.41#ibcon#read 3, iclass 22, count 0 2006.259.07:38:19.41#ibcon#about to read 4, iclass 22, count 0 2006.259.07:38:19.41#ibcon#read 4, iclass 22, count 0 2006.259.07:38:19.41#ibcon#about to read 5, iclass 22, count 0 2006.259.07:38:19.41#ibcon#read 5, iclass 22, count 0 2006.259.07:38:19.41#ibcon#about to read 6, iclass 22, count 0 2006.259.07:38:19.41#ibcon#read 6, iclass 22, count 0 2006.259.07:38:19.41#ibcon#end of sib2, iclass 22, count 0 2006.259.07:38:19.41#ibcon#*after write, iclass 22, count 0 2006.259.07:38:19.41#ibcon#*before return 0, iclass 22, count 0 2006.259.07:38:19.41#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.259.07:38:19.41#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.259.07:38:19.41#ibcon#about to clear, iclass 22 cls_cnt 0 2006.259.07:38:19.41#ibcon#cleared, iclass 22 cls_cnt 0 2006.259.07:38:19.41$vc4f8/valo=2,572.99 2006.259.07:38:19.41#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.259.07:38:19.41#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.259.07:38:19.41#ibcon#ireg 17 cls_cnt 0 2006.259.07:38:19.41#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.259.07:38:19.41#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.259.07:38:19.41#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.259.07:38:19.41#ibcon#enter wrdev, iclass 24, count 0 2006.259.07:38:19.41#ibcon#first serial, iclass 24, count 0 2006.259.07:38:19.41#ibcon#enter sib2, iclass 24, count 0 2006.259.07:38:19.41#ibcon#flushed, iclass 24, count 0 2006.259.07:38:19.41#ibcon#about to write, iclass 24, count 0 2006.259.07:38:19.41#ibcon#wrote, iclass 24, count 0 2006.259.07:38:19.41#ibcon#about to read 3, iclass 24, count 0 2006.259.07:38:19.43#ibcon#read 3, iclass 24, count 0 2006.259.07:38:19.43#ibcon#about to read 4, iclass 24, count 0 2006.259.07:38:19.43#ibcon#read 4, iclass 24, count 0 2006.259.07:38:19.43#ibcon#about to read 5, iclass 24, count 0 2006.259.07:38:19.43#ibcon#read 5, iclass 24, count 0 2006.259.07:38:19.43#ibcon#about to read 6, iclass 24, count 0 2006.259.07:38:19.43#ibcon#read 6, iclass 24, count 0 2006.259.07:38:19.43#ibcon#end of sib2, iclass 24, count 0 2006.259.07:38:19.43#ibcon#*mode == 0, iclass 24, count 0 2006.259.07:38:19.43#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.259.07:38:19.43#ibcon#[26=FRQ=02,572.99\r\n] 2006.259.07:38:19.43#ibcon#*before write, iclass 24, count 0 2006.259.07:38:19.43#ibcon#enter sib2, iclass 24, count 0 2006.259.07:38:19.43#ibcon#flushed, iclass 24, count 0 2006.259.07:38:19.43#ibcon#about to write, iclass 24, count 0 2006.259.07:38:19.43#ibcon#wrote, iclass 24, count 0 2006.259.07:38:19.43#ibcon#about to read 3, iclass 24, count 0 2006.259.07:38:19.47#ibcon#read 3, iclass 24, count 0 2006.259.07:38:19.47#ibcon#about to read 4, iclass 24, count 0 2006.259.07:38:19.47#ibcon#read 4, iclass 24, count 0 2006.259.07:38:19.47#ibcon#about to read 5, iclass 24, count 0 2006.259.07:38:19.47#ibcon#read 5, iclass 24, count 0 2006.259.07:38:19.47#ibcon#about to read 6, iclass 24, count 0 2006.259.07:38:19.47#ibcon#read 6, iclass 24, count 0 2006.259.07:38:19.47#ibcon#end of sib2, iclass 24, count 0 2006.259.07:38:19.47#ibcon#*after write, iclass 24, count 0 2006.259.07:38:19.47#ibcon#*before return 0, iclass 24, count 0 2006.259.07:38:19.47#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.259.07:38:19.47#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.259.07:38:19.47#ibcon#about to clear, iclass 24 cls_cnt 0 2006.259.07:38:19.47#ibcon#cleared, iclass 24 cls_cnt 0 2006.259.07:38:19.47$vc4f8/va=2,7 2006.259.07:38:19.47#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.259.07:38:19.47#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.259.07:38:19.47#ibcon#ireg 11 cls_cnt 2 2006.259.07:38:19.47#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.259.07:38:19.53#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.259.07:38:19.53#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.259.07:38:19.53#ibcon#enter wrdev, iclass 26, count 2 2006.259.07:38:19.53#ibcon#first serial, iclass 26, count 2 2006.259.07:38:19.53#ibcon#enter sib2, iclass 26, count 2 2006.259.07:38:19.53#ibcon#flushed, iclass 26, count 2 2006.259.07:38:19.53#ibcon#about to write, iclass 26, count 2 2006.259.07:38:19.53#ibcon#wrote, iclass 26, count 2 2006.259.07:38:19.53#ibcon#about to read 3, iclass 26, count 2 2006.259.07:38:19.55#ibcon#read 3, iclass 26, count 2 2006.259.07:38:19.55#ibcon#about to read 4, iclass 26, count 2 2006.259.07:38:19.55#ibcon#read 4, iclass 26, count 2 2006.259.07:38:19.55#ibcon#about to read 5, iclass 26, count 2 2006.259.07:38:19.55#ibcon#read 5, iclass 26, count 2 2006.259.07:38:19.55#ibcon#about to read 6, iclass 26, count 2 2006.259.07:38:19.55#ibcon#read 6, iclass 26, count 2 2006.259.07:38:19.55#ibcon#end of sib2, iclass 26, count 2 2006.259.07:38:19.55#ibcon#*mode == 0, iclass 26, count 2 2006.259.07:38:19.55#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.259.07:38:19.55#ibcon#[25=AT02-07\r\n] 2006.259.07:38:19.55#ibcon#*before write, iclass 26, count 2 2006.259.07:38:19.55#ibcon#enter sib2, iclass 26, count 2 2006.259.07:38:19.55#ibcon#flushed, iclass 26, count 2 2006.259.07:38:19.55#ibcon#about to write, iclass 26, count 2 2006.259.07:38:19.55#ibcon#wrote, iclass 26, count 2 2006.259.07:38:19.55#ibcon#about to read 3, iclass 26, count 2 2006.259.07:38:19.59#ibcon#read 3, iclass 26, count 2 2006.259.07:38:19.59#ibcon#about to read 4, iclass 26, count 2 2006.259.07:38:19.59#ibcon#read 4, iclass 26, count 2 2006.259.07:38:19.59#ibcon#about to read 5, iclass 26, count 2 2006.259.07:38:19.59#ibcon#read 5, iclass 26, count 2 2006.259.07:38:19.59#ibcon#about to read 6, iclass 26, count 2 2006.259.07:38:19.59#ibcon#read 6, iclass 26, count 2 2006.259.07:38:19.59#ibcon#end of sib2, iclass 26, count 2 2006.259.07:38:19.59#ibcon#*after write, iclass 26, count 2 2006.259.07:38:19.59#ibcon#*before return 0, iclass 26, count 2 2006.259.07:38:19.59#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.259.07:38:19.59#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.259.07:38:19.59#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.259.07:38:19.59#ibcon#ireg 7 cls_cnt 0 2006.259.07:38:19.59#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.259.07:38:19.71#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.259.07:38:19.71#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.259.07:38:19.71#ibcon#enter wrdev, iclass 26, count 0 2006.259.07:38:19.71#ibcon#first serial, iclass 26, count 0 2006.259.07:38:19.71#ibcon#enter sib2, iclass 26, count 0 2006.259.07:38:19.71#ibcon#flushed, iclass 26, count 0 2006.259.07:38:19.71#ibcon#about to write, iclass 26, count 0 2006.259.07:38:19.71#ibcon#wrote, iclass 26, count 0 2006.259.07:38:19.71#ibcon#about to read 3, iclass 26, count 0 2006.259.07:38:19.73#ibcon#read 3, iclass 26, count 0 2006.259.07:38:19.73#ibcon#about to read 4, iclass 26, count 0 2006.259.07:38:19.73#ibcon#read 4, iclass 26, count 0 2006.259.07:38:19.73#ibcon#about to read 5, iclass 26, count 0 2006.259.07:38:19.73#ibcon#read 5, iclass 26, count 0 2006.259.07:38:19.73#ibcon#about to read 6, iclass 26, count 0 2006.259.07:38:19.73#ibcon#read 6, iclass 26, count 0 2006.259.07:38:19.73#ibcon#end of sib2, iclass 26, count 0 2006.259.07:38:19.73#ibcon#*mode == 0, iclass 26, count 0 2006.259.07:38:19.73#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.259.07:38:19.73#ibcon#[25=USB\r\n] 2006.259.07:38:19.73#ibcon#*before write, iclass 26, count 0 2006.259.07:38:19.73#ibcon#enter sib2, iclass 26, count 0 2006.259.07:38:19.73#ibcon#flushed, iclass 26, count 0 2006.259.07:38:19.73#ibcon#about to write, iclass 26, count 0 2006.259.07:38:19.73#ibcon#wrote, iclass 26, count 0 2006.259.07:38:19.73#ibcon#about to read 3, iclass 26, count 0 2006.259.07:38:19.76#ibcon#read 3, iclass 26, count 0 2006.259.07:38:19.76#ibcon#about to read 4, iclass 26, count 0 2006.259.07:38:19.76#ibcon#read 4, iclass 26, count 0 2006.259.07:38:19.76#ibcon#about to read 5, iclass 26, count 0 2006.259.07:38:19.76#ibcon#read 5, iclass 26, count 0 2006.259.07:38:19.76#ibcon#about to read 6, iclass 26, count 0 2006.259.07:38:19.76#ibcon#read 6, iclass 26, count 0 2006.259.07:38:19.76#ibcon#end of sib2, iclass 26, count 0 2006.259.07:38:19.76#ibcon#*after write, iclass 26, count 0 2006.259.07:38:19.76#ibcon#*before return 0, iclass 26, count 0 2006.259.07:38:19.76#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.259.07:38:19.76#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.259.07:38:19.76#ibcon#about to clear, iclass 26 cls_cnt 0 2006.259.07:38:19.76#ibcon#cleared, iclass 26 cls_cnt 0 2006.259.07:38:19.76$vc4f8/valo=3,672.99 2006.259.07:38:19.76#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.259.07:38:19.76#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.259.07:38:19.76#ibcon#ireg 17 cls_cnt 0 2006.259.07:38:19.76#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.259.07:38:19.76#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.259.07:38:19.76#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.259.07:38:19.76#ibcon#enter wrdev, iclass 28, count 0 2006.259.07:38:19.76#ibcon#first serial, iclass 28, count 0 2006.259.07:38:19.76#ibcon#enter sib2, iclass 28, count 0 2006.259.07:38:19.76#ibcon#flushed, iclass 28, count 0 2006.259.07:38:19.76#ibcon#about to write, iclass 28, count 0 2006.259.07:38:19.76#ibcon#wrote, iclass 28, count 0 2006.259.07:38:19.76#ibcon#about to read 3, iclass 28, count 0 2006.259.07:38:19.79#ibcon#read 3, iclass 28, count 0 2006.259.07:38:19.79#ibcon#about to read 4, iclass 28, count 0 2006.259.07:38:19.79#ibcon#read 4, iclass 28, count 0 2006.259.07:38:19.79#ibcon#about to read 5, iclass 28, count 0 2006.259.07:38:19.79#ibcon#read 5, iclass 28, count 0 2006.259.07:38:19.79#ibcon#about to read 6, iclass 28, count 0 2006.259.07:38:19.79#ibcon#read 6, iclass 28, count 0 2006.259.07:38:19.79#ibcon#end of sib2, iclass 28, count 0 2006.259.07:38:19.79#ibcon#*mode == 0, iclass 28, count 0 2006.259.07:38:19.79#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.259.07:38:19.79#ibcon#[26=FRQ=03,672.99\r\n] 2006.259.07:38:19.79#ibcon#*before write, iclass 28, count 0 2006.259.07:38:19.79#ibcon#enter sib2, iclass 28, count 0 2006.259.07:38:19.79#ibcon#flushed, iclass 28, count 0 2006.259.07:38:19.79#ibcon#about to write, iclass 28, count 0 2006.259.07:38:19.79#ibcon#wrote, iclass 28, count 0 2006.259.07:38:19.79#ibcon#about to read 3, iclass 28, count 0 2006.259.07:38:19.83#ibcon#read 3, iclass 28, count 0 2006.259.07:38:19.83#ibcon#about to read 4, iclass 28, count 0 2006.259.07:38:19.83#ibcon#read 4, iclass 28, count 0 2006.259.07:38:19.83#ibcon#about to read 5, iclass 28, count 0 2006.259.07:38:19.83#ibcon#read 5, iclass 28, count 0 2006.259.07:38:19.83#ibcon#about to read 6, iclass 28, count 0 2006.259.07:38:19.83#ibcon#read 6, iclass 28, count 0 2006.259.07:38:19.83#ibcon#end of sib2, iclass 28, count 0 2006.259.07:38:19.83#ibcon#*after write, iclass 28, count 0 2006.259.07:38:19.83#ibcon#*before return 0, iclass 28, count 0 2006.259.07:38:19.83#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.259.07:38:19.83#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.259.07:38:19.83#ibcon#about to clear, iclass 28 cls_cnt 0 2006.259.07:38:19.83#ibcon#cleared, iclass 28 cls_cnt 0 2006.259.07:38:19.83$vc4f8/va=3,8 2006.259.07:38:19.83#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.259.07:38:19.83#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.259.07:38:19.83#ibcon#ireg 11 cls_cnt 2 2006.259.07:38:19.83#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.259.07:38:19.88#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.259.07:38:19.88#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.259.07:38:19.88#ibcon#enter wrdev, iclass 30, count 2 2006.259.07:38:19.88#ibcon#first serial, iclass 30, count 2 2006.259.07:38:19.88#ibcon#enter sib2, iclass 30, count 2 2006.259.07:38:19.88#ibcon#flushed, iclass 30, count 2 2006.259.07:38:19.88#ibcon#about to write, iclass 30, count 2 2006.259.07:38:19.88#ibcon#wrote, iclass 30, count 2 2006.259.07:38:19.88#ibcon#about to read 3, iclass 30, count 2 2006.259.07:38:19.90#ibcon#read 3, iclass 30, count 2 2006.259.07:38:19.90#ibcon#about to read 4, iclass 30, count 2 2006.259.07:38:19.90#ibcon#read 4, iclass 30, count 2 2006.259.07:38:19.90#ibcon#about to read 5, iclass 30, count 2 2006.259.07:38:19.90#ibcon#read 5, iclass 30, count 2 2006.259.07:38:19.90#ibcon#about to read 6, iclass 30, count 2 2006.259.07:38:19.90#ibcon#read 6, iclass 30, count 2 2006.259.07:38:19.90#ibcon#end of sib2, iclass 30, count 2 2006.259.07:38:19.90#ibcon#*mode == 0, iclass 30, count 2 2006.259.07:38:19.90#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.259.07:38:19.90#ibcon#[25=AT03-08\r\n] 2006.259.07:38:19.90#ibcon#*before write, iclass 30, count 2 2006.259.07:38:19.90#ibcon#enter sib2, iclass 30, count 2 2006.259.07:38:19.90#ibcon#flushed, iclass 30, count 2 2006.259.07:38:19.90#ibcon#about to write, iclass 30, count 2 2006.259.07:38:19.90#ibcon#wrote, iclass 30, count 2 2006.259.07:38:19.90#ibcon#about to read 3, iclass 30, count 2 2006.259.07:38:19.93#ibcon#read 3, iclass 30, count 2 2006.259.07:38:19.93#ibcon#about to read 4, iclass 30, count 2 2006.259.07:38:19.93#ibcon#read 4, iclass 30, count 2 2006.259.07:38:19.93#ibcon#about to read 5, iclass 30, count 2 2006.259.07:38:19.93#ibcon#read 5, iclass 30, count 2 2006.259.07:38:19.93#ibcon#about to read 6, iclass 30, count 2 2006.259.07:38:19.93#ibcon#read 6, iclass 30, count 2 2006.259.07:38:19.93#ibcon#end of sib2, iclass 30, count 2 2006.259.07:38:19.93#ibcon#*after write, iclass 30, count 2 2006.259.07:38:19.93#ibcon#*before return 0, iclass 30, count 2 2006.259.07:38:19.93#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.259.07:38:19.93#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.259.07:38:19.93#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.259.07:38:19.93#ibcon#ireg 7 cls_cnt 0 2006.259.07:38:19.93#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.259.07:38:20.05#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.259.07:38:20.05#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.259.07:38:20.05#ibcon#enter wrdev, iclass 30, count 0 2006.259.07:38:20.05#ibcon#first serial, iclass 30, count 0 2006.259.07:38:20.05#ibcon#enter sib2, iclass 30, count 0 2006.259.07:38:20.05#ibcon#flushed, iclass 30, count 0 2006.259.07:38:20.05#ibcon#about to write, iclass 30, count 0 2006.259.07:38:20.05#ibcon#wrote, iclass 30, count 0 2006.259.07:38:20.05#ibcon#about to read 3, iclass 30, count 0 2006.259.07:38:20.07#ibcon#read 3, iclass 30, count 0 2006.259.07:38:20.07#ibcon#about to read 4, iclass 30, count 0 2006.259.07:38:20.07#ibcon#read 4, iclass 30, count 0 2006.259.07:38:20.07#ibcon#about to read 5, iclass 30, count 0 2006.259.07:38:20.07#ibcon#read 5, iclass 30, count 0 2006.259.07:38:20.07#ibcon#about to read 6, iclass 30, count 0 2006.259.07:38:20.07#ibcon#read 6, iclass 30, count 0 2006.259.07:38:20.07#ibcon#end of sib2, iclass 30, count 0 2006.259.07:38:20.07#ibcon#*mode == 0, iclass 30, count 0 2006.259.07:38:20.07#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.259.07:38:20.07#ibcon#[25=USB\r\n] 2006.259.07:38:20.07#ibcon#*before write, iclass 30, count 0 2006.259.07:38:20.07#ibcon#enter sib2, iclass 30, count 0 2006.259.07:38:20.07#ibcon#flushed, iclass 30, count 0 2006.259.07:38:20.07#ibcon#about to write, iclass 30, count 0 2006.259.07:38:20.07#ibcon#wrote, iclass 30, count 0 2006.259.07:38:20.07#ibcon#about to read 3, iclass 30, count 0 2006.259.07:38:20.10#ibcon#read 3, iclass 30, count 0 2006.259.07:38:20.10#ibcon#about to read 4, iclass 30, count 0 2006.259.07:38:20.10#ibcon#read 4, iclass 30, count 0 2006.259.07:38:20.10#ibcon#about to read 5, iclass 30, count 0 2006.259.07:38:20.10#ibcon#read 5, iclass 30, count 0 2006.259.07:38:20.10#ibcon#about to read 6, iclass 30, count 0 2006.259.07:38:20.10#ibcon#read 6, iclass 30, count 0 2006.259.07:38:20.10#ibcon#end of sib2, iclass 30, count 0 2006.259.07:38:20.10#ibcon#*after write, iclass 30, count 0 2006.259.07:38:20.10#ibcon#*before return 0, iclass 30, count 0 2006.259.07:38:20.10#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.259.07:38:20.10#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.259.07:38:20.10#ibcon#about to clear, iclass 30 cls_cnt 0 2006.259.07:38:20.10#ibcon#cleared, iclass 30 cls_cnt 0 2006.259.07:38:20.10$vc4f8/valo=4,832.99 2006.259.07:38:20.10#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.259.07:38:20.10#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.259.07:38:20.10#ibcon#ireg 17 cls_cnt 0 2006.259.07:38:20.10#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.259.07:38:20.10#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.259.07:38:20.10#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.259.07:38:20.10#ibcon#enter wrdev, iclass 32, count 0 2006.259.07:38:20.10#ibcon#first serial, iclass 32, count 0 2006.259.07:38:20.10#ibcon#enter sib2, iclass 32, count 0 2006.259.07:38:20.10#ibcon#flushed, iclass 32, count 0 2006.259.07:38:20.10#ibcon#about to write, iclass 32, count 0 2006.259.07:38:20.10#ibcon#wrote, iclass 32, count 0 2006.259.07:38:20.10#ibcon#about to read 3, iclass 32, count 0 2006.259.07:38:20.12#ibcon#read 3, iclass 32, count 0 2006.259.07:38:20.12#ibcon#about to read 4, iclass 32, count 0 2006.259.07:38:20.12#ibcon#read 4, iclass 32, count 0 2006.259.07:38:20.12#ibcon#about to read 5, iclass 32, count 0 2006.259.07:38:20.12#ibcon#read 5, iclass 32, count 0 2006.259.07:38:20.12#ibcon#about to read 6, iclass 32, count 0 2006.259.07:38:20.12#ibcon#read 6, iclass 32, count 0 2006.259.07:38:20.12#ibcon#end of sib2, iclass 32, count 0 2006.259.07:38:20.12#ibcon#*mode == 0, iclass 32, count 0 2006.259.07:38:20.12#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.259.07:38:20.12#ibcon#[26=FRQ=04,832.99\r\n] 2006.259.07:38:20.12#ibcon#*before write, iclass 32, count 0 2006.259.07:38:20.12#ibcon#enter sib2, iclass 32, count 0 2006.259.07:38:20.12#ibcon#flushed, iclass 32, count 0 2006.259.07:38:20.12#ibcon#about to write, iclass 32, count 0 2006.259.07:38:20.12#ibcon#wrote, iclass 32, count 0 2006.259.07:38:20.12#ibcon#about to read 3, iclass 32, count 0 2006.259.07:38:20.16#ibcon#read 3, iclass 32, count 0 2006.259.07:38:20.16#ibcon#about to read 4, iclass 32, count 0 2006.259.07:38:20.16#ibcon#read 4, iclass 32, count 0 2006.259.07:38:20.16#ibcon#about to read 5, iclass 32, count 0 2006.259.07:38:20.16#ibcon#read 5, iclass 32, count 0 2006.259.07:38:20.16#ibcon#about to read 6, iclass 32, count 0 2006.259.07:38:20.16#ibcon#read 6, iclass 32, count 0 2006.259.07:38:20.16#ibcon#end of sib2, iclass 32, count 0 2006.259.07:38:20.16#ibcon#*after write, iclass 32, count 0 2006.259.07:38:20.16#ibcon#*before return 0, iclass 32, count 0 2006.259.07:38:20.16#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.259.07:38:20.16#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.259.07:38:20.16#ibcon#about to clear, iclass 32 cls_cnt 0 2006.259.07:38:20.16#ibcon#cleared, iclass 32 cls_cnt 0 2006.259.07:38:20.16$vc4f8/va=4,7 2006.259.07:38:20.16#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.259.07:38:20.16#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.259.07:38:20.16#ibcon#ireg 11 cls_cnt 2 2006.259.07:38:20.16#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.259.07:38:20.22#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.259.07:38:20.22#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.259.07:38:20.22#ibcon#enter wrdev, iclass 34, count 2 2006.259.07:38:20.22#ibcon#first serial, iclass 34, count 2 2006.259.07:38:20.22#ibcon#enter sib2, iclass 34, count 2 2006.259.07:38:20.22#ibcon#flushed, iclass 34, count 2 2006.259.07:38:20.22#ibcon#about to write, iclass 34, count 2 2006.259.07:38:20.22#ibcon#wrote, iclass 34, count 2 2006.259.07:38:20.22#ibcon#about to read 3, iclass 34, count 2 2006.259.07:38:20.24#ibcon#read 3, iclass 34, count 2 2006.259.07:38:20.24#ibcon#about to read 4, iclass 34, count 2 2006.259.07:38:20.24#ibcon#read 4, iclass 34, count 2 2006.259.07:38:20.24#ibcon#about to read 5, iclass 34, count 2 2006.259.07:38:20.24#ibcon#read 5, iclass 34, count 2 2006.259.07:38:20.24#ibcon#about to read 6, iclass 34, count 2 2006.259.07:38:20.24#ibcon#read 6, iclass 34, count 2 2006.259.07:38:20.24#ibcon#end of sib2, iclass 34, count 2 2006.259.07:38:20.24#ibcon#*mode == 0, iclass 34, count 2 2006.259.07:38:20.24#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.259.07:38:20.24#ibcon#[25=AT04-07\r\n] 2006.259.07:38:20.24#ibcon#*before write, iclass 34, count 2 2006.259.07:38:20.24#ibcon#enter sib2, iclass 34, count 2 2006.259.07:38:20.24#ibcon#flushed, iclass 34, count 2 2006.259.07:38:20.24#ibcon#about to write, iclass 34, count 2 2006.259.07:38:20.24#ibcon#wrote, iclass 34, count 2 2006.259.07:38:20.24#ibcon#about to read 3, iclass 34, count 2 2006.259.07:38:20.27#ibcon#read 3, iclass 34, count 2 2006.259.07:38:20.27#ibcon#about to read 4, iclass 34, count 2 2006.259.07:38:20.27#ibcon#read 4, iclass 34, count 2 2006.259.07:38:20.27#ibcon#about to read 5, iclass 34, count 2 2006.259.07:38:20.27#ibcon#read 5, iclass 34, count 2 2006.259.07:38:20.27#ibcon#about to read 6, iclass 34, count 2 2006.259.07:38:20.27#ibcon#read 6, iclass 34, count 2 2006.259.07:38:20.27#ibcon#end of sib2, iclass 34, count 2 2006.259.07:38:20.27#ibcon#*after write, iclass 34, count 2 2006.259.07:38:20.27#ibcon#*before return 0, iclass 34, count 2 2006.259.07:38:20.27#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.259.07:38:20.27#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.259.07:38:20.27#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.259.07:38:20.27#ibcon#ireg 7 cls_cnt 0 2006.259.07:38:20.27#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.259.07:38:20.39#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.259.07:38:20.39#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.259.07:38:20.39#ibcon#enter wrdev, iclass 34, count 0 2006.259.07:38:20.39#ibcon#first serial, iclass 34, count 0 2006.259.07:38:20.39#ibcon#enter sib2, iclass 34, count 0 2006.259.07:38:20.39#ibcon#flushed, iclass 34, count 0 2006.259.07:38:20.39#ibcon#about to write, iclass 34, count 0 2006.259.07:38:20.39#ibcon#wrote, iclass 34, count 0 2006.259.07:38:20.39#ibcon#about to read 3, iclass 34, count 0 2006.259.07:38:20.41#ibcon#read 3, iclass 34, count 0 2006.259.07:38:20.41#ibcon#about to read 4, iclass 34, count 0 2006.259.07:38:20.41#ibcon#read 4, iclass 34, count 0 2006.259.07:38:20.41#ibcon#about to read 5, iclass 34, count 0 2006.259.07:38:20.41#ibcon#read 5, iclass 34, count 0 2006.259.07:38:20.41#ibcon#about to read 6, iclass 34, count 0 2006.259.07:38:20.41#ibcon#read 6, iclass 34, count 0 2006.259.07:38:20.41#ibcon#end of sib2, iclass 34, count 0 2006.259.07:38:20.41#ibcon#*mode == 0, iclass 34, count 0 2006.259.07:38:20.41#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.259.07:38:20.41#ibcon#[25=USB\r\n] 2006.259.07:38:20.41#ibcon#*before write, iclass 34, count 0 2006.259.07:38:20.41#ibcon#enter sib2, iclass 34, count 0 2006.259.07:38:20.41#ibcon#flushed, iclass 34, count 0 2006.259.07:38:20.41#ibcon#about to write, iclass 34, count 0 2006.259.07:38:20.41#ibcon#wrote, iclass 34, count 0 2006.259.07:38:20.41#ibcon#about to read 3, iclass 34, count 0 2006.259.07:38:20.44#ibcon#read 3, iclass 34, count 0 2006.259.07:38:20.44#ibcon#about to read 4, iclass 34, count 0 2006.259.07:38:20.44#ibcon#read 4, iclass 34, count 0 2006.259.07:38:20.44#ibcon#about to read 5, iclass 34, count 0 2006.259.07:38:20.44#ibcon#read 5, iclass 34, count 0 2006.259.07:38:20.44#ibcon#about to read 6, iclass 34, count 0 2006.259.07:38:20.44#ibcon#read 6, iclass 34, count 0 2006.259.07:38:20.44#ibcon#end of sib2, iclass 34, count 0 2006.259.07:38:20.44#ibcon#*after write, iclass 34, count 0 2006.259.07:38:20.44#ibcon#*before return 0, iclass 34, count 0 2006.259.07:38:20.44#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.259.07:38:20.44#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.259.07:38:20.44#ibcon#about to clear, iclass 34 cls_cnt 0 2006.259.07:38:20.44#ibcon#cleared, iclass 34 cls_cnt 0 2006.259.07:38:20.44$vc4f8/valo=5,652.99 2006.259.07:38:20.44#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.259.07:38:20.44#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.259.07:38:20.44#ibcon#ireg 17 cls_cnt 0 2006.259.07:38:20.44#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.259.07:38:20.44#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.259.07:38:20.44#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.259.07:38:20.44#ibcon#enter wrdev, iclass 36, count 0 2006.259.07:38:20.44#ibcon#first serial, iclass 36, count 0 2006.259.07:38:20.44#ibcon#enter sib2, iclass 36, count 0 2006.259.07:38:20.44#ibcon#flushed, iclass 36, count 0 2006.259.07:38:20.44#ibcon#about to write, iclass 36, count 0 2006.259.07:38:20.44#ibcon#wrote, iclass 36, count 0 2006.259.07:38:20.44#ibcon#about to read 3, iclass 36, count 0 2006.259.07:38:20.46#ibcon#read 3, iclass 36, count 0 2006.259.07:38:20.46#ibcon#about to read 4, iclass 36, count 0 2006.259.07:38:20.46#ibcon#read 4, iclass 36, count 0 2006.259.07:38:20.46#ibcon#about to read 5, iclass 36, count 0 2006.259.07:38:20.46#ibcon#read 5, iclass 36, count 0 2006.259.07:38:20.46#ibcon#about to read 6, iclass 36, count 0 2006.259.07:38:20.46#ibcon#read 6, iclass 36, count 0 2006.259.07:38:20.46#ibcon#end of sib2, iclass 36, count 0 2006.259.07:38:20.46#ibcon#*mode == 0, iclass 36, count 0 2006.259.07:38:20.46#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.259.07:38:20.46#ibcon#[26=FRQ=05,652.99\r\n] 2006.259.07:38:20.46#ibcon#*before write, iclass 36, count 0 2006.259.07:38:20.46#ibcon#enter sib2, iclass 36, count 0 2006.259.07:38:20.46#ibcon#flushed, iclass 36, count 0 2006.259.07:38:20.46#ibcon#about to write, iclass 36, count 0 2006.259.07:38:20.46#ibcon#wrote, iclass 36, count 0 2006.259.07:38:20.46#ibcon#about to read 3, iclass 36, count 0 2006.259.07:38:20.50#ibcon#read 3, iclass 36, count 0 2006.259.07:38:20.50#ibcon#about to read 4, iclass 36, count 0 2006.259.07:38:20.50#ibcon#read 4, iclass 36, count 0 2006.259.07:38:20.50#ibcon#about to read 5, iclass 36, count 0 2006.259.07:38:20.50#ibcon#read 5, iclass 36, count 0 2006.259.07:38:20.50#ibcon#about to read 6, iclass 36, count 0 2006.259.07:38:20.50#ibcon#read 6, iclass 36, count 0 2006.259.07:38:20.50#ibcon#end of sib2, iclass 36, count 0 2006.259.07:38:20.50#ibcon#*after write, iclass 36, count 0 2006.259.07:38:20.50#ibcon#*before return 0, iclass 36, count 0 2006.259.07:38:20.50#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.259.07:38:20.50#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.259.07:38:20.50#ibcon#about to clear, iclass 36 cls_cnt 0 2006.259.07:38:20.50#ibcon#cleared, iclass 36 cls_cnt 0 2006.259.07:38:20.50$vc4f8/va=5,7 2006.259.07:38:20.50#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.259.07:38:20.50#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.259.07:38:20.50#ibcon#ireg 11 cls_cnt 2 2006.259.07:38:20.50#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.259.07:38:20.56#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.259.07:38:20.56#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.259.07:38:20.56#ibcon#enter wrdev, iclass 38, count 2 2006.259.07:38:20.56#ibcon#first serial, iclass 38, count 2 2006.259.07:38:20.56#ibcon#enter sib2, iclass 38, count 2 2006.259.07:38:20.56#ibcon#flushed, iclass 38, count 2 2006.259.07:38:20.56#ibcon#about to write, iclass 38, count 2 2006.259.07:38:20.56#ibcon#wrote, iclass 38, count 2 2006.259.07:38:20.56#ibcon#about to read 3, iclass 38, count 2 2006.259.07:38:20.58#ibcon#read 3, iclass 38, count 2 2006.259.07:38:20.58#ibcon#about to read 4, iclass 38, count 2 2006.259.07:38:20.58#ibcon#read 4, iclass 38, count 2 2006.259.07:38:20.58#ibcon#about to read 5, iclass 38, count 2 2006.259.07:38:20.58#ibcon#read 5, iclass 38, count 2 2006.259.07:38:20.58#ibcon#about to read 6, iclass 38, count 2 2006.259.07:38:20.58#ibcon#read 6, iclass 38, count 2 2006.259.07:38:20.58#ibcon#end of sib2, iclass 38, count 2 2006.259.07:38:20.58#ibcon#*mode == 0, iclass 38, count 2 2006.259.07:38:20.58#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.259.07:38:20.58#ibcon#[25=AT05-07\r\n] 2006.259.07:38:20.58#ibcon#*before write, iclass 38, count 2 2006.259.07:38:20.58#ibcon#enter sib2, iclass 38, count 2 2006.259.07:38:20.58#ibcon#flushed, iclass 38, count 2 2006.259.07:38:20.58#ibcon#about to write, iclass 38, count 2 2006.259.07:38:20.58#ibcon#wrote, iclass 38, count 2 2006.259.07:38:20.58#ibcon#about to read 3, iclass 38, count 2 2006.259.07:38:20.61#ibcon#read 3, iclass 38, count 2 2006.259.07:38:20.61#ibcon#about to read 4, iclass 38, count 2 2006.259.07:38:20.61#ibcon#read 4, iclass 38, count 2 2006.259.07:38:20.61#ibcon#about to read 5, iclass 38, count 2 2006.259.07:38:20.61#ibcon#read 5, iclass 38, count 2 2006.259.07:38:20.61#ibcon#about to read 6, iclass 38, count 2 2006.259.07:38:20.61#ibcon#read 6, iclass 38, count 2 2006.259.07:38:20.61#ibcon#end of sib2, iclass 38, count 2 2006.259.07:38:20.61#ibcon#*after write, iclass 38, count 2 2006.259.07:38:20.61#ibcon#*before return 0, iclass 38, count 2 2006.259.07:38:20.61#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.259.07:38:20.61#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.259.07:38:20.61#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.259.07:38:20.61#ibcon#ireg 7 cls_cnt 0 2006.259.07:38:20.61#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.259.07:38:20.73#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.259.07:38:20.73#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.259.07:38:20.73#ibcon#enter wrdev, iclass 38, count 0 2006.259.07:38:20.73#ibcon#first serial, iclass 38, count 0 2006.259.07:38:20.73#ibcon#enter sib2, iclass 38, count 0 2006.259.07:38:20.73#ibcon#flushed, iclass 38, count 0 2006.259.07:38:20.73#ibcon#about to write, iclass 38, count 0 2006.259.07:38:20.73#ibcon#wrote, iclass 38, count 0 2006.259.07:38:20.73#ibcon#about to read 3, iclass 38, count 0 2006.259.07:38:20.75#ibcon#read 3, iclass 38, count 0 2006.259.07:38:20.75#ibcon#about to read 4, iclass 38, count 0 2006.259.07:38:20.75#ibcon#read 4, iclass 38, count 0 2006.259.07:38:20.75#ibcon#about to read 5, iclass 38, count 0 2006.259.07:38:20.75#ibcon#read 5, iclass 38, count 0 2006.259.07:38:20.75#ibcon#about to read 6, iclass 38, count 0 2006.259.07:38:20.75#ibcon#read 6, iclass 38, count 0 2006.259.07:38:20.75#ibcon#end of sib2, iclass 38, count 0 2006.259.07:38:20.75#ibcon#*mode == 0, iclass 38, count 0 2006.259.07:38:20.75#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.259.07:38:20.75#ibcon#[25=USB\r\n] 2006.259.07:38:20.75#ibcon#*before write, iclass 38, count 0 2006.259.07:38:20.75#ibcon#enter sib2, iclass 38, count 0 2006.259.07:38:20.75#ibcon#flushed, iclass 38, count 0 2006.259.07:38:20.75#ibcon#about to write, iclass 38, count 0 2006.259.07:38:20.75#ibcon#wrote, iclass 38, count 0 2006.259.07:38:20.75#ibcon#about to read 3, iclass 38, count 0 2006.259.07:38:20.78#ibcon#read 3, iclass 38, count 0 2006.259.07:38:20.78#ibcon#about to read 4, iclass 38, count 0 2006.259.07:38:20.78#ibcon#read 4, iclass 38, count 0 2006.259.07:38:20.78#ibcon#about to read 5, iclass 38, count 0 2006.259.07:38:20.78#ibcon#read 5, iclass 38, count 0 2006.259.07:38:20.78#ibcon#about to read 6, iclass 38, count 0 2006.259.07:38:20.78#ibcon#read 6, iclass 38, count 0 2006.259.07:38:20.78#ibcon#end of sib2, iclass 38, count 0 2006.259.07:38:20.78#ibcon#*after write, iclass 38, count 0 2006.259.07:38:20.78#ibcon#*before return 0, iclass 38, count 0 2006.259.07:38:20.78#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.259.07:38:20.78#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.259.07:38:20.78#ibcon#about to clear, iclass 38 cls_cnt 0 2006.259.07:38:20.78#ibcon#cleared, iclass 38 cls_cnt 0 2006.259.07:38:20.78$vc4f8/valo=6,772.99 2006.259.07:38:20.78#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.259.07:38:20.78#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.259.07:38:20.78#ibcon#ireg 17 cls_cnt 0 2006.259.07:38:20.78#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.259.07:38:20.78#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.259.07:38:20.78#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.259.07:38:20.78#ibcon#enter wrdev, iclass 40, count 0 2006.259.07:38:20.78#ibcon#first serial, iclass 40, count 0 2006.259.07:38:20.78#ibcon#enter sib2, iclass 40, count 0 2006.259.07:38:20.78#ibcon#flushed, iclass 40, count 0 2006.259.07:38:20.78#ibcon#about to write, iclass 40, count 0 2006.259.07:38:20.78#ibcon#wrote, iclass 40, count 0 2006.259.07:38:20.78#ibcon#about to read 3, iclass 40, count 0 2006.259.07:38:20.80#ibcon#read 3, iclass 40, count 0 2006.259.07:38:20.80#ibcon#about to read 4, iclass 40, count 0 2006.259.07:38:20.80#ibcon#read 4, iclass 40, count 0 2006.259.07:38:20.80#ibcon#about to read 5, iclass 40, count 0 2006.259.07:38:20.80#ibcon#read 5, iclass 40, count 0 2006.259.07:38:20.80#ibcon#about to read 6, iclass 40, count 0 2006.259.07:38:20.80#ibcon#read 6, iclass 40, count 0 2006.259.07:38:20.80#ibcon#end of sib2, iclass 40, count 0 2006.259.07:38:20.80#ibcon#*mode == 0, iclass 40, count 0 2006.259.07:38:20.80#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.259.07:38:20.80#ibcon#[26=FRQ=06,772.99\r\n] 2006.259.07:38:20.80#ibcon#*before write, iclass 40, count 0 2006.259.07:38:20.80#ibcon#enter sib2, iclass 40, count 0 2006.259.07:38:20.80#ibcon#flushed, iclass 40, count 0 2006.259.07:38:20.80#ibcon#about to write, iclass 40, count 0 2006.259.07:38:20.80#ibcon#wrote, iclass 40, count 0 2006.259.07:38:20.80#ibcon#about to read 3, iclass 40, count 0 2006.259.07:38:20.84#ibcon#read 3, iclass 40, count 0 2006.259.07:38:20.84#ibcon#about to read 4, iclass 40, count 0 2006.259.07:38:20.84#ibcon#read 4, iclass 40, count 0 2006.259.07:38:20.84#ibcon#about to read 5, iclass 40, count 0 2006.259.07:38:20.84#ibcon#read 5, iclass 40, count 0 2006.259.07:38:20.84#ibcon#about to read 6, iclass 40, count 0 2006.259.07:38:20.84#ibcon#read 6, iclass 40, count 0 2006.259.07:38:20.84#ibcon#end of sib2, iclass 40, count 0 2006.259.07:38:20.84#ibcon#*after write, iclass 40, count 0 2006.259.07:38:20.84#ibcon#*before return 0, iclass 40, count 0 2006.259.07:38:20.84#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.259.07:38:20.84#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.259.07:38:20.84#ibcon#about to clear, iclass 40 cls_cnt 0 2006.259.07:38:20.84#ibcon#cleared, iclass 40 cls_cnt 0 2006.259.07:38:20.84$vc4f8/va=6,6 2006.259.07:38:20.84#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.259.07:38:20.84#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.259.07:38:20.84#ibcon#ireg 11 cls_cnt 2 2006.259.07:38:20.84#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.259.07:38:20.90#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.259.07:38:20.90#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.259.07:38:20.90#ibcon#enter wrdev, iclass 4, count 2 2006.259.07:38:20.90#ibcon#first serial, iclass 4, count 2 2006.259.07:38:20.90#ibcon#enter sib2, iclass 4, count 2 2006.259.07:38:20.90#ibcon#flushed, iclass 4, count 2 2006.259.07:38:20.90#ibcon#about to write, iclass 4, count 2 2006.259.07:38:20.90#ibcon#wrote, iclass 4, count 2 2006.259.07:38:20.90#ibcon#about to read 3, iclass 4, count 2 2006.259.07:38:20.92#ibcon#read 3, iclass 4, count 2 2006.259.07:38:20.92#ibcon#about to read 4, iclass 4, count 2 2006.259.07:38:20.92#ibcon#read 4, iclass 4, count 2 2006.259.07:38:20.92#ibcon#about to read 5, iclass 4, count 2 2006.259.07:38:20.92#ibcon#read 5, iclass 4, count 2 2006.259.07:38:20.92#ibcon#about to read 6, iclass 4, count 2 2006.259.07:38:20.92#ibcon#read 6, iclass 4, count 2 2006.259.07:38:20.92#ibcon#end of sib2, iclass 4, count 2 2006.259.07:38:20.92#ibcon#*mode == 0, iclass 4, count 2 2006.259.07:38:20.92#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.259.07:38:20.92#ibcon#[25=AT06-06\r\n] 2006.259.07:38:20.92#ibcon#*before write, iclass 4, count 2 2006.259.07:38:20.92#ibcon#enter sib2, iclass 4, count 2 2006.259.07:38:20.92#ibcon#flushed, iclass 4, count 2 2006.259.07:38:20.92#ibcon#about to write, iclass 4, count 2 2006.259.07:38:20.92#ibcon#wrote, iclass 4, count 2 2006.259.07:38:20.92#ibcon#about to read 3, iclass 4, count 2 2006.259.07:38:20.95#ibcon#read 3, iclass 4, count 2 2006.259.07:38:20.95#ibcon#about to read 4, iclass 4, count 2 2006.259.07:38:20.95#ibcon#read 4, iclass 4, count 2 2006.259.07:38:20.95#ibcon#about to read 5, iclass 4, count 2 2006.259.07:38:20.95#ibcon#read 5, iclass 4, count 2 2006.259.07:38:20.95#ibcon#about to read 6, iclass 4, count 2 2006.259.07:38:20.95#ibcon#read 6, iclass 4, count 2 2006.259.07:38:20.95#ibcon#end of sib2, iclass 4, count 2 2006.259.07:38:20.95#ibcon#*after write, iclass 4, count 2 2006.259.07:38:20.95#ibcon#*before return 0, iclass 4, count 2 2006.259.07:38:20.95#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.259.07:38:20.95#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.259.07:38:20.95#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.259.07:38:20.95#ibcon#ireg 7 cls_cnt 0 2006.259.07:38:20.95#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.259.07:38:21.07#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.259.07:38:21.07#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.259.07:38:21.07#ibcon#enter wrdev, iclass 4, count 0 2006.259.07:38:21.07#ibcon#first serial, iclass 4, count 0 2006.259.07:38:21.07#ibcon#enter sib2, iclass 4, count 0 2006.259.07:38:21.07#ibcon#flushed, iclass 4, count 0 2006.259.07:38:21.07#ibcon#about to write, iclass 4, count 0 2006.259.07:38:21.07#ibcon#wrote, iclass 4, count 0 2006.259.07:38:21.07#ibcon#about to read 3, iclass 4, count 0 2006.259.07:38:21.09#ibcon#read 3, iclass 4, count 0 2006.259.07:38:21.09#ibcon#about to read 4, iclass 4, count 0 2006.259.07:38:21.09#ibcon#read 4, iclass 4, count 0 2006.259.07:38:21.09#ibcon#about to read 5, iclass 4, count 0 2006.259.07:38:21.09#ibcon#read 5, iclass 4, count 0 2006.259.07:38:21.09#ibcon#about to read 6, iclass 4, count 0 2006.259.07:38:21.09#ibcon#read 6, iclass 4, count 0 2006.259.07:38:21.09#ibcon#end of sib2, iclass 4, count 0 2006.259.07:38:21.09#ibcon#*mode == 0, iclass 4, count 0 2006.259.07:38:21.09#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.259.07:38:21.09#ibcon#[25=USB\r\n] 2006.259.07:38:21.09#ibcon#*before write, iclass 4, count 0 2006.259.07:38:21.09#ibcon#enter sib2, iclass 4, count 0 2006.259.07:38:21.09#ibcon#flushed, iclass 4, count 0 2006.259.07:38:21.09#ibcon#about to write, iclass 4, count 0 2006.259.07:38:21.09#ibcon#wrote, iclass 4, count 0 2006.259.07:38:21.09#ibcon#about to read 3, iclass 4, count 0 2006.259.07:38:21.12#ibcon#read 3, iclass 4, count 0 2006.259.07:38:21.12#ibcon#about to read 4, iclass 4, count 0 2006.259.07:38:21.12#ibcon#read 4, iclass 4, count 0 2006.259.07:38:21.12#ibcon#about to read 5, iclass 4, count 0 2006.259.07:38:21.12#ibcon#read 5, iclass 4, count 0 2006.259.07:38:21.12#ibcon#about to read 6, iclass 4, count 0 2006.259.07:38:21.12#ibcon#read 6, iclass 4, count 0 2006.259.07:38:21.12#ibcon#end of sib2, iclass 4, count 0 2006.259.07:38:21.12#ibcon#*after write, iclass 4, count 0 2006.259.07:38:21.12#ibcon#*before return 0, iclass 4, count 0 2006.259.07:38:21.12#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.259.07:38:21.12#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.259.07:38:21.12#ibcon#about to clear, iclass 4 cls_cnt 0 2006.259.07:38:21.12#ibcon#cleared, iclass 4 cls_cnt 0 2006.259.07:38:21.12$vc4f8/valo=7,832.99 2006.259.07:38:21.12#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.259.07:38:21.12#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.259.07:38:21.12#ibcon#ireg 17 cls_cnt 0 2006.259.07:38:21.12#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.259.07:38:21.12#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.259.07:38:21.12#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.259.07:38:21.12#ibcon#enter wrdev, iclass 6, count 0 2006.259.07:38:21.12#ibcon#first serial, iclass 6, count 0 2006.259.07:38:21.12#ibcon#enter sib2, iclass 6, count 0 2006.259.07:38:21.12#ibcon#flushed, iclass 6, count 0 2006.259.07:38:21.12#ibcon#about to write, iclass 6, count 0 2006.259.07:38:21.12#ibcon#wrote, iclass 6, count 0 2006.259.07:38:21.12#ibcon#about to read 3, iclass 6, count 0 2006.259.07:38:21.14#ibcon#read 3, iclass 6, count 0 2006.259.07:38:21.14#ibcon#about to read 4, iclass 6, count 0 2006.259.07:38:21.14#ibcon#read 4, iclass 6, count 0 2006.259.07:38:21.14#ibcon#about to read 5, iclass 6, count 0 2006.259.07:38:21.14#ibcon#read 5, iclass 6, count 0 2006.259.07:38:21.14#ibcon#about to read 6, iclass 6, count 0 2006.259.07:38:21.14#ibcon#read 6, iclass 6, count 0 2006.259.07:38:21.14#ibcon#end of sib2, iclass 6, count 0 2006.259.07:38:21.14#ibcon#*mode == 0, iclass 6, count 0 2006.259.07:38:21.14#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.259.07:38:21.14#ibcon#[26=FRQ=07,832.99\r\n] 2006.259.07:38:21.14#ibcon#*before write, iclass 6, count 0 2006.259.07:38:21.14#ibcon#enter sib2, iclass 6, count 0 2006.259.07:38:21.14#ibcon#flushed, iclass 6, count 0 2006.259.07:38:21.14#ibcon#about to write, iclass 6, count 0 2006.259.07:38:21.14#ibcon#wrote, iclass 6, count 0 2006.259.07:38:21.14#ibcon#about to read 3, iclass 6, count 0 2006.259.07:38:21.18#ibcon#read 3, iclass 6, count 0 2006.259.07:38:21.18#ibcon#about to read 4, iclass 6, count 0 2006.259.07:38:21.18#ibcon#read 4, iclass 6, count 0 2006.259.07:38:21.18#ibcon#about to read 5, iclass 6, count 0 2006.259.07:38:21.18#ibcon#read 5, iclass 6, count 0 2006.259.07:38:21.18#ibcon#about to read 6, iclass 6, count 0 2006.259.07:38:21.18#ibcon#read 6, iclass 6, count 0 2006.259.07:38:21.18#ibcon#end of sib2, iclass 6, count 0 2006.259.07:38:21.18#ibcon#*after write, iclass 6, count 0 2006.259.07:38:21.18#ibcon#*before return 0, iclass 6, count 0 2006.259.07:38:21.18#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.259.07:38:21.18#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.259.07:38:21.18#ibcon#about to clear, iclass 6 cls_cnt 0 2006.259.07:38:21.18#ibcon#cleared, iclass 6 cls_cnt 0 2006.259.07:38:21.18$vc4f8/va=7,6 2006.259.07:38:21.18#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.259.07:38:21.18#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.259.07:38:21.18#ibcon#ireg 11 cls_cnt 2 2006.259.07:38:21.18#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.259.07:38:21.24#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.259.07:38:21.24#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.259.07:38:21.24#ibcon#enter wrdev, iclass 10, count 2 2006.259.07:38:21.24#ibcon#first serial, iclass 10, count 2 2006.259.07:38:21.24#ibcon#enter sib2, iclass 10, count 2 2006.259.07:38:21.24#ibcon#flushed, iclass 10, count 2 2006.259.07:38:21.24#ibcon#about to write, iclass 10, count 2 2006.259.07:38:21.24#ibcon#wrote, iclass 10, count 2 2006.259.07:38:21.24#ibcon#about to read 3, iclass 10, count 2 2006.259.07:38:21.26#ibcon#read 3, iclass 10, count 2 2006.259.07:38:21.26#ibcon#about to read 4, iclass 10, count 2 2006.259.07:38:21.26#ibcon#read 4, iclass 10, count 2 2006.259.07:38:21.26#ibcon#about to read 5, iclass 10, count 2 2006.259.07:38:21.26#ibcon#read 5, iclass 10, count 2 2006.259.07:38:21.26#ibcon#about to read 6, iclass 10, count 2 2006.259.07:38:21.26#ibcon#read 6, iclass 10, count 2 2006.259.07:38:21.26#ibcon#end of sib2, iclass 10, count 2 2006.259.07:38:21.26#ibcon#*mode == 0, iclass 10, count 2 2006.259.07:38:21.26#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.259.07:38:21.26#ibcon#[25=AT07-06\r\n] 2006.259.07:38:21.26#ibcon#*before write, iclass 10, count 2 2006.259.07:38:21.26#ibcon#enter sib2, iclass 10, count 2 2006.259.07:38:21.26#ibcon#flushed, iclass 10, count 2 2006.259.07:38:21.26#ibcon#about to write, iclass 10, count 2 2006.259.07:38:21.26#ibcon#wrote, iclass 10, count 2 2006.259.07:38:21.26#ibcon#about to read 3, iclass 10, count 2 2006.259.07:38:21.29#ibcon#read 3, iclass 10, count 2 2006.259.07:38:21.29#ibcon#about to read 4, iclass 10, count 2 2006.259.07:38:21.29#ibcon#read 4, iclass 10, count 2 2006.259.07:38:21.29#ibcon#about to read 5, iclass 10, count 2 2006.259.07:38:21.29#ibcon#read 5, iclass 10, count 2 2006.259.07:38:21.29#ibcon#about to read 6, iclass 10, count 2 2006.259.07:38:21.29#ibcon#read 6, iclass 10, count 2 2006.259.07:38:21.29#ibcon#end of sib2, iclass 10, count 2 2006.259.07:38:21.29#ibcon#*after write, iclass 10, count 2 2006.259.07:38:21.29#ibcon#*before return 0, iclass 10, count 2 2006.259.07:38:21.29#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.259.07:38:21.29#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.259.07:38:21.29#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.259.07:38:21.29#ibcon#ireg 7 cls_cnt 0 2006.259.07:38:21.29#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.259.07:38:21.41#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.259.07:38:21.41#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.259.07:38:21.41#ibcon#enter wrdev, iclass 10, count 0 2006.259.07:38:21.41#ibcon#first serial, iclass 10, count 0 2006.259.07:38:21.41#ibcon#enter sib2, iclass 10, count 0 2006.259.07:38:21.41#ibcon#flushed, iclass 10, count 0 2006.259.07:38:21.41#ibcon#about to write, iclass 10, count 0 2006.259.07:38:21.41#ibcon#wrote, iclass 10, count 0 2006.259.07:38:21.41#ibcon#about to read 3, iclass 10, count 0 2006.259.07:38:21.43#ibcon#read 3, iclass 10, count 0 2006.259.07:38:21.43#ibcon#about to read 4, iclass 10, count 0 2006.259.07:38:21.43#ibcon#read 4, iclass 10, count 0 2006.259.07:38:21.43#ibcon#about to read 5, iclass 10, count 0 2006.259.07:38:21.43#ibcon#read 5, iclass 10, count 0 2006.259.07:38:21.43#ibcon#about to read 6, iclass 10, count 0 2006.259.07:38:21.43#ibcon#read 6, iclass 10, count 0 2006.259.07:38:21.43#ibcon#end of sib2, iclass 10, count 0 2006.259.07:38:21.43#ibcon#*mode == 0, iclass 10, count 0 2006.259.07:38:21.43#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.259.07:38:21.43#ibcon#[25=USB\r\n] 2006.259.07:38:21.43#ibcon#*before write, iclass 10, count 0 2006.259.07:38:21.43#ibcon#enter sib2, iclass 10, count 0 2006.259.07:38:21.43#ibcon#flushed, iclass 10, count 0 2006.259.07:38:21.43#ibcon#about to write, iclass 10, count 0 2006.259.07:38:21.43#ibcon#wrote, iclass 10, count 0 2006.259.07:38:21.43#ibcon#about to read 3, iclass 10, count 0 2006.259.07:38:21.46#ibcon#read 3, iclass 10, count 0 2006.259.07:38:21.46#ibcon#about to read 4, iclass 10, count 0 2006.259.07:38:21.46#ibcon#read 4, iclass 10, count 0 2006.259.07:38:21.46#ibcon#about to read 5, iclass 10, count 0 2006.259.07:38:21.46#ibcon#read 5, iclass 10, count 0 2006.259.07:38:21.46#ibcon#about to read 6, iclass 10, count 0 2006.259.07:38:21.46#ibcon#read 6, iclass 10, count 0 2006.259.07:38:21.46#ibcon#end of sib2, iclass 10, count 0 2006.259.07:38:21.46#ibcon#*after write, iclass 10, count 0 2006.259.07:38:21.46#ibcon#*before return 0, iclass 10, count 0 2006.259.07:38:21.46#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.259.07:38:21.46#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.259.07:38:21.46#ibcon#about to clear, iclass 10 cls_cnt 0 2006.259.07:38:21.46#ibcon#cleared, iclass 10 cls_cnt 0 2006.259.07:38:21.46$vc4f8/valo=8,852.99 2006.259.07:38:21.46#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.259.07:38:21.46#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.259.07:38:21.46#ibcon#ireg 17 cls_cnt 0 2006.259.07:38:21.46#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.259.07:38:21.46#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.259.07:38:21.46#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.259.07:38:21.46#ibcon#enter wrdev, iclass 12, count 0 2006.259.07:38:21.46#ibcon#first serial, iclass 12, count 0 2006.259.07:38:21.46#ibcon#enter sib2, iclass 12, count 0 2006.259.07:38:21.46#ibcon#flushed, iclass 12, count 0 2006.259.07:38:21.46#ibcon#about to write, iclass 12, count 0 2006.259.07:38:21.46#ibcon#wrote, iclass 12, count 0 2006.259.07:38:21.46#ibcon#about to read 3, iclass 12, count 0 2006.259.07:38:21.48#ibcon#read 3, iclass 12, count 0 2006.259.07:38:21.48#ibcon#about to read 4, iclass 12, count 0 2006.259.07:38:21.48#ibcon#read 4, iclass 12, count 0 2006.259.07:38:21.48#ibcon#about to read 5, iclass 12, count 0 2006.259.07:38:21.48#ibcon#read 5, iclass 12, count 0 2006.259.07:38:21.48#ibcon#about to read 6, iclass 12, count 0 2006.259.07:38:21.48#ibcon#read 6, iclass 12, count 0 2006.259.07:38:21.48#ibcon#end of sib2, iclass 12, count 0 2006.259.07:38:21.48#ibcon#*mode == 0, iclass 12, count 0 2006.259.07:38:21.48#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.259.07:38:21.48#ibcon#[26=FRQ=08,852.99\r\n] 2006.259.07:38:21.48#ibcon#*before write, iclass 12, count 0 2006.259.07:38:21.48#ibcon#enter sib2, iclass 12, count 0 2006.259.07:38:21.48#ibcon#flushed, iclass 12, count 0 2006.259.07:38:21.48#ibcon#about to write, iclass 12, count 0 2006.259.07:38:21.48#ibcon#wrote, iclass 12, count 0 2006.259.07:38:21.48#ibcon#about to read 3, iclass 12, count 0 2006.259.07:38:21.52#ibcon#read 3, iclass 12, count 0 2006.259.07:38:21.52#ibcon#about to read 4, iclass 12, count 0 2006.259.07:38:21.52#ibcon#read 4, iclass 12, count 0 2006.259.07:38:21.52#ibcon#about to read 5, iclass 12, count 0 2006.259.07:38:21.52#ibcon#read 5, iclass 12, count 0 2006.259.07:38:21.52#ibcon#about to read 6, iclass 12, count 0 2006.259.07:38:21.52#ibcon#read 6, iclass 12, count 0 2006.259.07:38:21.52#ibcon#end of sib2, iclass 12, count 0 2006.259.07:38:21.52#ibcon#*after write, iclass 12, count 0 2006.259.07:38:21.52#ibcon#*before return 0, iclass 12, count 0 2006.259.07:38:21.52#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.259.07:38:21.52#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.259.07:38:21.52#ibcon#about to clear, iclass 12 cls_cnt 0 2006.259.07:38:21.52#ibcon#cleared, iclass 12 cls_cnt 0 2006.259.07:38:21.52$vc4f8/va=8,6 2006.259.07:38:21.52#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.259.07:38:21.52#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.259.07:38:21.52#ibcon#ireg 11 cls_cnt 2 2006.259.07:38:21.52#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.259.07:38:21.58#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.259.07:38:21.58#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.259.07:38:21.58#ibcon#enter wrdev, iclass 14, count 2 2006.259.07:38:21.58#ibcon#first serial, iclass 14, count 2 2006.259.07:38:21.58#ibcon#enter sib2, iclass 14, count 2 2006.259.07:38:21.58#ibcon#flushed, iclass 14, count 2 2006.259.07:38:21.58#ibcon#about to write, iclass 14, count 2 2006.259.07:38:21.58#ibcon#wrote, iclass 14, count 2 2006.259.07:38:21.58#ibcon#about to read 3, iclass 14, count 2 2006.259.07:38:21.60#ibcon#read 3, iclass 14, count 2 2006.259.07:38:21.60#ibcon#about to read 4, iclass 14, count 2 2006.259.07:38:21.60#ibcon#read 4, iclass 14, count 2 2006.259.07:38:21.60#ibcon#about to read 5, iclass 14, count 2 2006.259.07:38:21.60#ibcon#read 5, iclass 14, count 2 2006.259.07:38:21.60#ibcon#about to read 6, iclass 14, count 2 2006.259.07:38:21.60#ibcon#read 6, iclass 14, count 2 2006.259.07:38:21.60#ibcon#end of sib2, iclass 14, count 2 2006.259.07:38:21.60#ibcon#*mode == 0, iclass 14, count 2 2006.259.07:38:21.60#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.259.07:38:21.60#ibcon#[25=AT08-06\r\n] 2006.259.07:38:21.60#ibcon#*before write, iclass 14, count 2 2006.259.07:38:21.60#ibcon#enter sib2, iclass 14, count 2 2006.259.07:38:21.60#ibcon#flushed, iclass 14, count 2 2006.259.07:38:21.60#ibcon#about to write, iclass 14, count 2 2006.259.07:38:21.60#ibcon#wrote, iclass 14, count 2 2006.259.07:38:21.60#ibcon#about to read 3, iclass 14, count 2 2006.259.07:38:21.63#ibcon#read 3, iclass 14, count 2 2006.259.07:38:21.63#ibcon#about to read 4, iclass 14, count 2 2006.259.07:38:21.63#ibcon#read 4, iclass 14, count 2 2006.259.07:38:21.63#ibcon#about to read 5, iclass 14, count 2 2006.259.07:38:21.63#ibcon#read 5, iclass 14, count 2 2006.259.07:38:21.63#ibcon#about to read 6, iclass 14, count 2 2006.259.07:38:21.63#ibcon#read 6, iclass 14, count 2 2006.259.07:38:21.63#ibcon#end of sib2, iclass 14, count 2 2006.259.07:38:21.63#ibcon#*after write, iclass 14, count 2 2006.259.07:38:21.63#ibcon#*before return 0, iclass 14, count 2 2006.259.07:38:21.63#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.259.07:38:21.63#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.259.07:38:21.63#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.259.07:38:21.63#ibcon#ireg 7 cls_cnt 0 2006.259.07:38:21.63#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.259.07:38:21.75#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.259.07:38:21.75#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.259.07:38:21.75#ibcon#enter wrdev, iclass 14, count 0 2006.259.07:38:21.75#ibcon#first serial, iclass 14, count 0 2006.259.07:38:21.75#ibcon#enter sib2, iclass 14, count 0 2006.259.07:38:21.75#ibcon#flushed, iclass 14, count 0 2006.259.07:38:21.75#ibcon#about to write, iclass 14, count 0 2006.259.07:38:21.75#ibcon#wrote, iclass 14, count 0 2006.259.07:38:21.75#ibcon#about to read 3, iclass 14, count 0 2006.259.07:38:21.77#ibcon#read 3, iclass 14, count 0 2006.259.07:38:21.77#ibcon#about to read 4, iclass 14, count 0 2006.259.07:38:21.77#ibcon#read 4, iclass 14, count 0 2006.259.07:38:21.77#ibcon#about to read 5, iclass 14, count 0 2006.259.07:38:21.77#ibcon#read 5, iclass 14, count 0 2006.259.07:38:21.77#ibcon#about to read 6, iclass 14, count 0 2006.259.07:38:21.77#ibcon#read 6, iclass 14, count 0 2006.259.07:38:21.77#ibcon#end of sib2, iclass 14, count 0 2006.259.07:38:21.77#ibcon#*mode == 0, iclass 14, count 0 2006.259.07:38:21.77#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.259.07:38:21.77#ibcon#[25=USB\r\n] 2006.259.07:38:21.77#ibcon#*before write, iclass 14, count 0 2006.259.07:38:21.77#ibcon#enter sib2, iclass 14, count 0 2006.259.07:38:21.77#ibcon#flushed, iclass 14, count 0 2006.259.07:38:21.77#ibcon#about to write, iclass 14, count 0 2006.259.07:38:21.77#ibcon#wrote, iclass 14, count 0 2006.259.07:38:21.77#ibcon#about to read 3, iclass 14, count 0 2006.259.07:38:21.80#ibcon#read 3, iclass 14, count 0 2006.259.07:38:21.80#ibcon#about to read 4, iclass 14, count 0 2006.259.07:38:21.80#ibcon#read 4, iclass 14, count 0 2006.259.07:38:21.80#ibcon#about to read 5, iclass 14, count 0 2006.259.07:38:21.80#ibcon#read 5, iclass 14, count 0 2006.259.07:38:21.80#ibcon#about to read 6, iclass 14, count 0 2006.259.07:38:21.80#ibcon#read 6, iclass 14, count 0 2006.259.07:38:21.80#ibcon#end of sib2, iclass 14, count 0 2006.259.07:38:21.80#ibcon#*after write, iclass 14, count 0 2006.259.07:38:21.80#ibcon#*before return 0, iclass 14, count 0 2006.259.07:38:21.80#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.259.07:38:21.80#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.259.07:38:21.80#ibcon#about to clear, iclass 14 cls_cnt 0 2006.259.07:38:21.80#ibcon#cleared, iclass 14 cls_cnt 0 2006.259.07:38:21.80$vc4f8/vblo=1,632.99 2006.259.07:38:21.80#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.259.07:38:21.80#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.259.07:38:21.80#ibcon#ireg 17 cls_cnt 0 2006.259.07:38:21.80#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.259.07:38:21.80#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.259.07:38:21.80#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.259.07:38:21.80#ibcon#enter wrdev, iclass 16, count 0 2006.259.07:38:21.80#ibcon#first serial, iclass 16, count 0 2006.259.07:38:21.80#ibcon#enter sib2, iclass 16, count 0 2006.259.07:38:21.80#ibcon#flushed, iclass 16, count 0 2006.259.07:38:21.80#ibcon#about to write, iclass 16, count 0 2006.259.07:38:21.80#ibcon#wrote, iclass 16, count 0 2006.259.07:38:21.80#ibcon#about to read 3, iclass 16, count 0 2006.259.07:38:21.82#ibcon#read 3, iclass 16, count 0 2006.259.07:38:21.82#ibcon#about to read 4, iclass 16, count 0 2006.259.07:38:21.82#ibcon#read 4, iclass 16, count 0 2006.259.07:38:21.82#ibcon#about to read 5, iclass 16, count 0 2006.259.07:38:21.82#ibcon#read 5, iclass 16, count 0 2006.259.07:38:21.82#ibcon#about to read 6, iclass 16, count 0 2006.259.07:38:21.82#ibcon#read 6, iclass 16, count 0 2006.259.07:38:21.82#ibcon#end of sib2, iclass 16, count 0 2006.259.07:38:21.82#ibcon#*mode == 0, iclass 16, count 0 2006.259.07:38:21.82#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.259.07:38:21.82#ibcon#[28=FRQ=01,632.99\r\n] 2006.259.07:38:21.82#ibcon#*before write, iclass 16, count 0 2006.259.07:38:21.82#ibcon#enter sib2, iclass 16, count 0 2006.259.07:38:21.82#ibcon#flushed, iclass 16, count 0 2006.259.07:38:21.82#ibcon#about to write, iclass 16, count 0 2006.259.07:38:21.82#ibcon#wrote, iclass 16, count 0 2006.259.07:38:21.82#ibcon#about to read 3, iclass 16, count 0 2006.259.07:38:21.86#ibcon#read 3, iclass 16, count 0 2006.259.07:38:21.86#ibcon#about to read 4, iclass 16, count 0 2006.259.07:38:21.86#ibcon#read 4, iclass 16, count 0 2006.259.07:38:21.86#ibcon#about to read 5, iclass 16, count 0 2006.259.07:38:21.86#ibcon#read 5, iclass 16, count 0 2006.259.07:38:21.86#ibcon#about to read 6, iclass 16, count 0 2006.259.07:38:21.86#ibcon#read 6, iclass 16, count 0 2006.259.07:38:21.86#ibcon#end of sib2, iclass 16, count 0 2006.259.07:38:21.86#ibcon#*after write, iclass 16, count 0 2006.259.07:38:21.86#ibcon#*before return 0, iclass 16, count 0 2006.259.07:38:21.86#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.259.07:38:21.86#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.259.07:38:21.86#ibcon#about to clear, iclass 16 cls_cnt 0 2006.259.07:38:21.86#ibcon#cleared, iclass 16 cls_cnt 0 2006.259.07:38:21.86$vc4f8/vb=1,4 2006.259.07:38:21.86#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.259.07:38:21.86#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.259.07:38:21.86#ibcon#ireg 11 cls_cnt 2 2006.259.07:38:21.86#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.259.07:38:21.86#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.259.07:38:21.86#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.259.07:38:21.86#ibcon#enter wrdev, iclass 18, count 2 2006.259.07:38:21.86#ibcon#first serial, iclass 18, count 2 2006.259.07:38:21.86#ibcon#enter sib2, iclass 18, count 2 2006.259.07:38:21.86#ibcon#flushed, iclass 18, count 2 2006.259.07:38:21.86#ibcon#about to write, iclass 18, count 2 2006.259.07:38:21.86#ibcon#wrote, iclass 18, count 2 2006.259.07:38:21.86#ibcon#about to read 3, iclass 18, count 2 2006.259.07:38:21.88#ibcon#read 3, iclass 18, count 2 2006.259.07:38:21.88#ibcon#about to read 4, iclass 18, count 2 2006.259.07:38:21.88#ibcon#read 4, iclass 18, count 2 2006.259.07:38:21.88#ibcon#about to read 5, iclass 18, count 2 2006.259.07:38:21.88#ibcon#read 5, iclass 18, count 2 2006.259.07:38:21.88#ibcon#about to read 6, iclass 18, count 2 2006.259.07:38:21.88#ibcon#read 6, iclass 18, count 2 2006.259.07:38:21.88#ibcon#end of sib2, iclass 18, count 2 2006.259.07:38:21.88#ibcon#*mode == 0, iclass 18, count 2 2006.259.07:38:21.88#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.259.07:38:21.88#ibcon#[27=AT01-04\r\n] 2006.259.07:38:21.88#ibcon#*before write, iclass 18, count 2 2006.259.07:38:21.88#ibcon#enter sib2, iclass 18, count 2 2006.259.07:38:21.88#ibcon#flushed, iclass 18, count 2 2006.259.07:38:21.88#ibcon#about to write, iclass 18, count 2 2006.259.07:38:21.88#ibcon#wrote, iclass 18, count 2 2006.259.07:38:21.88#ibcon#about to read 3, iclass 18, count 2 2006.259.07:38:21.91#ibcon#read 3, iclass 18, count 2 2006.259.07:38:21.91#ibcon#about to read 4, iclass 18, count 2 2006.259.07:38:21.91#ibcon#read 4, iclass 18, count 2 2006.259.07:38:21.91#ibcon#about to read 5, iclass 18, count 2 2006.259.07:38:21.91#ibcon#read 5, iclass 18, count 2 2006.259.07:38:21.91#ibcon#about to read 6, iclass 18, count 2 2006.259.07:38:21.91#ibcon#read 6, iclass 18, count 2 2006.259.07:38:21.91#ibcon#end of sib2, iclass 18, count 2 2006.259.07:38:21.91#ibcon#*after write, iclass 18, count 2 2006.259.07:38:21.91#ibcon#*before return 0, iclass 18, count 2 2006.259.07:38:21.91#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.259.07:38:21.91#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.259.07:38:21.91#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.259.07:38:21.91#ibcon#ireg 7 cls_cnt 0 2006.259.07:38:21.91#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.259.07:38:22.03#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.259.07:38:22.03#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.259.07:38:22.03#ibcon#enter wrdev, iclass 18, count 0 2006.259.07:38:22.03#ibcon#first serial, iclass 18, count 0 2006.259.07:38:22.03#ibcon#enter sib2, iclass 18, count 0 2006.259.07:38:22.03#ibcon#flushed, iclass 18, count 0 2006.259.07:38:22.03#ibcon#about to write, iclass 18, count 0 2006.259.07:38:22.03#ibcon#wrote, iclass 18, count 0 2006.259.07:38:22.03#ibcon#about to read 3, iclass 18, count 0 2006.259.07:38:22.05#ibcon#read 3, iclass 18, count 0 2006.259.07:38:22.05#ibcon#about to read 4, iclass 18, count 0 2006.259.07:38:22.05#ibcon#read 4, iclass 18, count 0 2006.259.07:38:22.05#ibcon#about to read 5, iclass 18, count 0 2006.259.07:38:22.05#ibcon#read 5, iclass 18, count 0 2006.259.07:38:22.05#ibcon#about to read 6, iclass 18, count 0 2006.259.07:38:22.05#ibcon#read 6, iclass 18, count 0 2006.259.07:38:22.05#ibcon#end of sib2, iclass 18, count 0 2006.259.07:38:22.05#ibcon#*mode == 0, iclass 18, count 0 2006.259.07:38:22.05#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.259.07:38:22.05#ibcon#[27=USB\r\n] 2006.259.07:38:22.05#ibcon#*before write, iclass 18, count 0 2006.259.07:38:22.05#ibcon#enter sib2, iclass 18, count 0 2006.259.07:38:22.05#ibcon#flushed, iclass 18, count 0 2006.259.07:38:22.05#ibcon#about to write, iclass 18, count 0 2006.259.07:38:22.05#ibcon#wrote, iclass 18, count 0 2006.259.07:38:22.05#ibcon#about to read 3, iclass 18, count 0 2006.259.07:38:22.08#ibcon#read 3, iclass 18, count 0 2006.259.07:38:22.08#ibcon#about to read 4, iclass 18, count 0 2006.259.07:38:22.08#ibcon#read 4, iclass 18, count 0 2006.259.07:38:22.08#ibcon#about to read 5, iclass 18, count 0 2006.259.07:38:22.08#ibcon#read 5, iclass 18, count 0 2006.259.07:38:22.08#ibcon#about to read 6, iclass 18, count 0 2006.259.07:38:22.08#ibcon#read 6, iclass 18, count 0 2006.259.07:38:22.08#ibcon#end of sib2, iclass 18, count 0 2006.259.07:38:22.08#ibcon#*after write, iclass 18, count 0 2006.259.07:38:22.08#ibcon#*before return 0, iclass 18, count 0 2006.259.07:38:22.08#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.259.07:38:22.08#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.259.07:38:22.08#ibcon#about to clear, iclass 18 cls_cnt 0 2006.259.07:38:22.08#ibcon#cleared, iclass 18 cls_cnt 0 2006.259.07:38:22.08$vc4f8/vblo=2,640.99 2006.259.07:38:22.08#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.259.07:38:22.08#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.259.07:38:22.08#ibcon#ireg 17 cls_cnt 0 2006.259.07:38:22.08#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.259.07:38:22.08#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.259.07:38:22.08#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.259.07:38:22.08#ibcon#enter wrdev, iclass 20, count 0 2006.259.07:38:22.08#ibcon#first serial, iclass 20, count 0 2006.259.07:38:22.08#ibcon#enter sib2, iclass 20, count 0 2006.259.07:38:22.08#ibcon#flushed, iclass 20, count 0 2006.259.07:38:22.08#ibcon#about to write, iclass 20, count 0 2006.259.07:38:22.08#ibcon#wrote, iclass 20, count 0 2006.259.07:38:22.08#ibcon#about to read 3, iclass 20, count 0 2006.259.07:38:22.10#ibcon#read 3, iclass 20, count 0 2006.259.07:38:22.10#ibcon#about to read 4, iclass 20, count 0 2006.259.07:38:22.10#ibcon#read 4, iclass 20, count 0 2006.259.07:38:22.10#ibcon#about to read 5, iclass 20, count 0 2006.259.07:38:22.10#ibcon#read 5, iclass 20, count 0 2006.259.07:38:22.10#ibcon#about to read 6, iclass 20, count 0 2006.259.07:38:22.10#ibcon#read 6, iclass 20, count 0 2006.259.07:38:22.10#ibcon#end of sib2, iclass 20, count 0 2006.259.07:38:22.10#ibcon#*mode == 0, iclass 20, count 0 2006.259.07:38:22.10#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.259.07:38:22.10#ibcon#[28=FRQ=02,640.99\r\n] 2006.259.07:38:22.10#ibcon#*before write, iclass 20, count 0 2006.259.07:38:22.10#ibcon#enter sib2, iclass 20, count 0 2006.259.07:38:22.10#ibcon#flushed, iclass 20, count 0 2006.259.07:38:22.10#ibcon#about to write, iclass 20, count 0 2006.259.07:38:22.10#ibcon#wrote, iclass 20, count 0 2006.259.07:38:22.10#ibcon#about to read 3, iclass 20, count 0 2006.259.07:38:22.14#ibcon#read 3, iclass 20, count 0 2006.259.07:38:22.14#ibcon#about to read 4, iclass 20, count 0 2006.259.07:38:22.14#ibcon#read 4, iclass 20, count 0 2006.259.07:38:22.14#ibcon#about to read 5, iclass 20, count 0 2006.259.07:38:22.14#ibcon#read 5, iclass 20, count 0 2006.259.07:38:22.14#ibcon#about to read 6, iclass 20, count 0 2006.259.07:38:22.14#ibcon#read 6, iclass 20, count 0 2006.259.07:38:22.14#ibcon#end of sib2, iclass 20, count 0 2006.259.07:38:22.14#ibcon#*after write, iclass 20, count 0 2006.259.07:38:22.14#ibcon#*before return 0, iclass 20, count 0 2006.259.07:38:22.14#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.259.07:38:22.14#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.259.07:38:22.14#ibcon#about to clear, iclass 20 cls_cnt 0 2006.259.07:38:22.14#ibcon#cleared, iclass 20 cls_cnt 0 2006.259.07:38:22.14$vc4f8/vb=2,5 2006.259.07:38:22.14#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.259.07:38:22.14#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.259.07:38:22.14#ibcon#ireg 11 cls_cnt 2 2006.259.07:38:22.14#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.259.07:38:22.20#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.259.07:38:22.20#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.259.07:38:22.20#ibcon#enter wrdev, iclass 22, count 2 2006.259.07:38:22.20#ibcon#first serial, iclass 22, count 2 2006.259.07:38:22.20#ibcon#enter sib2, iclass 22, count 2 2006.259.07:38:22.20#ibcon#flushed, iclass 22, count 2 2006.259.07:38:22.20#ibcon#about to write, iclass 22, count 2 2006.259.07:38:22.20#ibcon#wrote, iclass 22, count 2 2006.259.07:38:22.20#ibcon#about to read 3, iclass 22, count 2 2006.259.07:38:22.22#ibcon#read 3, iclass 22, count 2 2006.259.07:38:22.22#ibcon#about to read 4, iclass 22, count 2 2006.259.07:38:22.22#ibcon#read 4, iclass 22, count 2 2006.259.07:38:22.22#ibcon#about to read 5, iclass 22, count 2 2006.259.07:38:22.22#ibcon#read 5, iclass 22, count 2 2006.259.07:38:22.22#ibcon#about to read 6, iclass 22, count 2 2006.259.07:38:22.22#ibcon#read 6, iclass 22, count 2 2006.259.07:38:22.22#ibcon#end of sib2, iclass 22, count 2 2006.259.07:38:22.22#ibcon#*mode == 0, iclass 22, count 2 2006.259.07:38:22.22#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.259.07:38:22.22#ibcon#[27=AT02-05\r\n] 2006.259.07:38:22.22#ibcon#*before write, iclass 22, count 2 2006.259.07:38:22.22#ibcon#enter sib2, iclass 22, count 2 2006.259.07:38:22.22#ibcon#flushed, iclass 22, count 2 2006.259.07:38:22.22#ibcon#about to write, iclass 22, count 2 2006.259.07:38:22.22#ibcon#wrote, iclass 22, count 2 2006.259.07:38:22.22#ibcon#about to read 3, iclass 22, count 2 2006.259.07:38:22.25#ibcon#read 3, iclass 22, count 2 2006.259.07:38:22.25#ibcon#about to read 4, iclass 22, count 2 2006.259.07:38:22.25#ibcon#read 4, iclass 22, count 2 2006.259.07:38:22.25#ibcon#about to read 5, iclass 22, count 2 2006.259.07:38:22.25#ibcon#read 5, iclass 22, count 2 2006.259.07:38:22.25#ibcon#about to read 6, iclass 22, count 2 2006.259.07:38:22.25#ibcon#read 6, iclass 22, count 2 2006.259.07:38:22.25#ibcon#end of sib2, iclass 22, count 2 2006.259.07:38:22.25#ibcon#*after write, iclass 22, count 2 2006.259.07:38:22.25#ibcon#*before return 0, iclass 22, count 2 2006.259.07:38:22.25#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.259.07:38:22.25#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.259.07:38:22.25#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.259.07:38:22.25#ibcon#ireg 7 cls_cnt 0 2006.259.07:38:22.25#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.259.07:38:22.37#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.259.07:38:22.37#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.259.07:38:22.37#ibcon#enter wrdev, iclass 22, count 0 2006.259.07:38:22.37#ibcon#first serial, iclass 22, count 0 2006.259.07:38:22.37#ibcon#enter sib2, iclass 22, count 0 2006.259.07:38:22.37#ibcon#flushed, iclass 22, count 0 2006.259.07:38:22.37#ibcon#about to write, iclass 22, count 0 2006.259.07:38:22.37#ibcon#wrote, iclass 22, count 0 2006.259.07:38:22.37#ibcon#about to read 3, iclass 22, count 0 2006.259.07:38:22.39#ibcon#read 3, iclass 22, count 0 2006.259.07:38:22.39#ibcon#about to read 4, iclass 22, count 0 2006.259.07:38:22.39#ibcon#read 4, iclass 22, count 0 2006.259.07:38:22.39#ibcon#about to read 5, iclass 22, count 0 2006.259.07:38:22.39#ibcon#read 5, iclass 22, count 0 2006.259.07:38:22.39#ibcon#about to read 6, iclass 22, count 0 2006.259.07:38:22.39#ibcon#read 6, iclass 22, count 0 2006.259.07:38:22.39#ibcon#end of sib2, iclass 22, count 0 2006.259.07:38:22.39#ibcon#*mode == 0, iclass 22, count 0 2006.259.07:38:22.39#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.259.07:38:22.39#ibcon#[27=USB\r\n] 2006.259.07:38:22.39#ibcon#*before write, iclass 22, count 0 2006.259.07:38:22.39#ibcon#enter sib2, iclass 22, count 0 2006.259.07:38:22.39#ibcon#flushed, iclass 22, count 0 2006.259.07:38:22.39#ibcon#about to write, iclass 22, count 0 2006.259.07:38:22.39#ibcon#wrote, iclass 22, count 0 2006.259.07:38:22.39#ibcon#about to read 3, iclass 22, count 0 2006.259.07:38:22.42#ibcon#read 3, iclass 22, count 0 2006.259.07:38:22.42#ibcon#about to read 4, iclass 22, count 0 2006.259.07:38:22.42#ibcon#read 4, iclass 22, count 0 2006.259.07:38:22.42#ibcon#about to read 5, iclass 22, count 0 2006.259.07:38:22.42#ibcon#read 5, iclass 22, count 0 2006.259.07:38:22.42#ibcon#about to read 6, iclass 22, count 0 2006.259.07:38:22.42#ibcon#read 6, iclass 22, count 0 2006.259.07:38:22.42#ibcon#end of sib2, iclass 22, count 0 2006.259.07:38:22.42#ibcon#*after write, iclass 22, count 0 2006.259.07:38:22.42#ibcon#*before return 0, iclass 22, count 0 2006.259.07:38:22.42#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.259.07:38:22.42#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.259.07:38:22.42#ibcon#about to clear, iclass 22 cls_cnt 0 2006.259.07:38:22.42#ibcon#cleared, iclass 22 cls_cnt 0 2006.259.07:38:22.42$vc4f8/vblo=3,656.99 2006.259.07:38:22.42#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.259.07:38:22.42#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.259.07:38:22.42#ibcon#ireg 17 cls_cnt 0 2006.259.07:38:22.42#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.259.07:38:22.42#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.259.07:38:22.42#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.259.07:38:22.42#ibcon#enter wrdev, iclass 24, count 0 2006.259.07:38:22.42#ibcon#first serial, iclass 24, count 0 2006.259.07:38:22.42#ibcon#enter sib2, iclass 24, count 0 2006.259.07:38:22.42#ibcon#flushed, iclass 24, count 0 2006.259.07:38:22.42#ibcon#about to write, iclass 24, count 0 2006.259.07:38:22.42#ibcon#wrote, iclass 24, count 0 2006.259.07:38:22.42#ibcon#about to read 3, iclass 24, count 0 2006.259.07:38:22.44#ibcon#read 3, iclass 24, count 0 2006.259.07:38:22.44#ibcon#about to read 4, iclass 24, count 0 2006.259.07:38:22.44#ibcon#read 4, iclass 24, count 0 2006.259.07:38:22.44#ibcon#about to read 5, iclass 24, count 0 2006.259.07:38:22.44#ibcon#read 5, iclass 24, count 0 2006.259.07:38:22.44#ibcon#about to read 6, iclass 24, count 0 2006.259.07:38:22.44#ibcon#read 6, iclass 24, count 0 2006.259.07:38:22.44#ibcon#end of sib2, iclass 24, count 0 2006.259.07:38:22.44#ibcon#*mode == 0, iclass 24, count 0 2006.259.07:38:22.44#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.259.07:38:22.44#ibcon#[28=FRQ=03,656.99\r\n] 2006.259.07:38:22.44#ibcon#*before write, iclass 24, count 0 2006.259.07:38:22.44#ibcon#enter sib2, iclass 24, count 0 2006.259.07:38:22.44#ibcon#flushed, iclass 24, count 0 2006.259.07:38:22.44#ibcon#about to write, iclass 24, count 0 2006.259.07:38:22.44#ibcon#wrote, iclass 24, count 0 2006.259.07:38:22.44#ibcon#about to read 3, iclass 24, count 0 2006.259.07:38:22.48#ibcon#read 3, iclass 24, count 0 2006.259.07:38:22.48#ibcon#about to read 4, iclass 24, count 0 2006.259.07:38:22.48#ibcon#read 4, iclass 24, count 0 2006.259.07:38:22.48#ibcon#about to read 5, iclass 24, count 0 2006.259.07:38:22.48#ibcon#read 5, iclass 24, count 0 2006.259.07:38:22.48#ibcon#about to read 6, iclass 24, count 0 2006.259.07:38:22.48#ibcon#read 6, iclass 24, count 0 2006.259.07:38:22.48#ibcon#end of sib2, iclass 24, count 0 2006.259.07:38:22.48#ibcon#*after write, iclass 24, count 0 2006.259.07:38:22.48#ibcon#*before return 0, iclass 24, count 0 2006.259.07:38:22.48#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.259.07:38:22.48#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.259.07:38:22.48#ibcon#about to clear, iclass 24 cls_cnt 0 2006.259.07:38:22.48#ibcon#cleared, iclass 24 cls_cnt 0 2006.259.07:38:22.48$vc4f8/vb=3,4 2006.259.07:38:22.48#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.259.07:38:22.48#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.259.07:38:22.48#ibcon#ireg 11 cls_cnt 2 2006.259.07:38:22.48#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.259.07:38:22.54#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.259.07:38:22.54#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.259.07:38:22.54#ibcon#enter wrdev, iclass 26, count 2 2006.259.07:38:22.54#ibcon#first serial, iclass 26, count 2 2006.259.07:38:22.54#ibcon#enter sib2, iclass 26, count 2 2006.259.07:38:22.54#ibcon#flushed, iclass 26, count 2 2006.259.07:38:22.54#ibcon#about to write, iclass 26, count 2 2006.259.07:38:22.54#ibcon#wrote, iclass 26, count 2 2006.259.07:38:22.54#ibcon#about to read 3, iclass 26, count 2 2006.259.07:38:22.56#ibcon#read 3, iclass 26, count 2 2006.259.07:38:22.56#ibcon#about to read 4, iclass 26, count 2 2006.259.07:38:22.56#ibcon#read 4, iclass 26, count 2 2006.259.07:38:22.56#ibcon#about to read 5, iclass 26, count 2 2006.259.07:38:22.56#ibcon#read 5, iclass 26, count 2 2006.259.07:38:22.56#ibcon#about to read 6, iclass 26, count 2 2006.259.07:38:22.56#ibcon#read 6, iclass 26, count 2 2006.259.07:38:22.56#ibcon#end of sib2, iclass 26, count 2 2006.259.07:38:22.56#ibcon#*mode == 0, iclass 26, count 2 2006.259.07:38:22.56#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.259.07:38:22.56#ibcon#[27=AT03-04\r\n] 2006.259.07:38:22.56#ibcon#*before write, iclass 26, count 2 2006.259.07:38:22.56#ibcon#enter sib2, iclass 26, count 2 2006.259.07:38:22.56#ibcon#flushed, iclass 26, count 2 2006.259.07:38:22.56#ibcon#about to write, iclass 26, count 2 2006.259.07:38:22.56#ibcon#wrote, iclass 26, count 2 2006.259.07:38:22.56#ibcon#about to read 3, iclass 26, count 2 2006.259.07:38:22.59#ibcon#read 3, iclass 26, count 2 2006.259.07:38:22.59#ibcon#about to read 4, iclass 26, count 2 2006.259.07:38:22.59#ibcon#read 4, iclass 26, count 2 2006.259.07:38:22.59#ibcon#about to read 5, iclass 26, count 2 2006.259.07:38:22.59#ibcon#read 5, iclass 26, count 2 2006.259.07:38:22.59#ibcon#about to read 6, iclass 26, count 2 2006.259.07:38:22.59#ibcon#read 6, iclass 26, count 2 2006.259.07:38:22.59#ibcon#end of sib2, iclass 26, count 2 2006.259.07:38:22.59#ibcon#*after write, iclass 26, count 2 2006.259.07:38:22.59#ibcon#*before return 0, iclass 26, count 2 2006.259.07:38:22.59#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.259.07:38:22.59#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.259.07:38:22.59#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.259.07:38:22.59#ibcon#ireg 7 cls_cnt 0 2006.259.07:38:22.59#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.259.07:38:22.71#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.259.07:38:22.71#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.259.07:38:22.71#ibcon#enter wrdev, iclass 26, count 0 2006.259.07:38:22.71#ibcon#first serial, iclass 26, count 0 2006.259.07:38:22.71#ibcon#enter sib2, iclass 26, count 0 2006.259.07:38:22.71#ibcon#flushed, iclass 26, count 0 2006.259.07:38:22.71#ibcon#about to write, iclass 26, count 0 2006.259.07:38:22.71#ibcon#wrote, iclass 26, count 0 2006.259.07:38:22.71#ibcon#about to read 3, iclass 26, count 0 2006.259.07:38:22.73#ibcon#read 3, iclass 26, count 0 2006.259.07:38:22.73#ibcon#about to read 4, iclass 26, count 0 2006.259.07:38:22.73#ibcon#read 4, iclass 26, count 0 2006.259.07:38:22.73#ibcon#about to read 5, iclass 26, count 0 2006.259.07:38:22.73#ibcon#read 5, iclass 26, count 0 2006.259.07:38:22.73#ibcon#about to read 6, iclass 26, count 0 2006.259.07:38:22.73#ibcon#read 6, iclass 26, count 0 2006.259.07:38:22.73#ibcon#end of sib2, iclass 26, count 0 2006.259.07:38:22.73#ibcon#*mode == 0, iclass 26, count 0 2006.259.07:38:22.73#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.259.07:38:22.73#ibcon#[27=USB\r\n] 2006.259.07:38:22.73#ibcon#*before write, iclass 26, count 0 2006.259.07:38:22.73#ibcon#enter sib2, iclass 26, count 0 2006.259.07:38:22.73#ibcon#flushed, iclass 26, count 0 2006.259.07:38:22.73#ibcon#about to write, iclass 26, count 0 2006.259.07:38:22.73#ibcon#wrote, iclass 26, count 0 2006.259.07:38:22.73#ibcon#about to read 3, iclass 26, count 0 2006.259.07:38:22.75#abcon#<5=/04 2.9 5.8 22.30 841012.9\r\n> 2006.259.07:38:22.76#ibcon#read 3, iclass 26, count 0 2006.259.07:38:22.76#ibcon#about to read 4, iclass 26, count 0 2006.259.07:38:22.76#ibcon#read 4, iclass 26, count 0 2006.259.07:38:22.76#ibcon#about to read 5, iclass 26, count 0 2006.259.07:38:22.76#ibcon#read 5, iclass 26, count 0 2006.259.07:38:22.76#ibcon#about to read 6, iclass 26, count 0 2006.259.07:38:22.76#ibcon#read 6, iclass 26, count 0 2006.259.07:38:22.76#ibcon#end of sib2, iclass 26, count 0 2006.259.07:38:22.76#ibcon#*after write, iclass 26, count 0 2006.259.07:38:22.76#ibcon#*before return 0, iclass 26, count 0 2006.259.07:38:22.76#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.259.07:38:22.76#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.259.07:38:22.76#ibcon#about to clear, iclass 26 cls_cnt 0 2006.259.07:38:22.76#ibcon#cleared, iclass 26 cls_cnt 0 2006.259.07:38:22.76$vc4f8/vblo=4,712.99 2006.259.07:38:22.76#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.259.07:38:22.76#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.259.07:38:22.76#ibcon#ireg 17 cls_cnt 0 2006.259.07:38:22.76#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.259.07:38:22.76#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.259.07:38:22.76#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.259.07:38:22.76#ibcon#enter wrdev, iclass 31, count 0 2006.259.07:38:22.76#ibcon#first serial, iclass 31, count 0 2006.259.07:38:22.76#ibcon#enter sib2, iclass 31, count 0 2006.259.07:38:22.76#ibcon#flushed, iclass 31, count 0 2006.259.07:38:22.76#ibcon#about to write, iclass 31, count 0 2006.259.07:38:22.76#ibcon#wrote, iclass 31, count 0 2006.259.07:38:22.76#ibcon#about to read 3, iclass 31, count 0 2006.259.07:38:22.77#abcon#{5=INTERFACE CLEAR} 2006.259.07:38:22.78#ibcon#read 3, iclass 31, count 0 2006.259.07:38:22.78#ibcon#about to read 4, iclass 31, count 0 2006.259.07:38:22.78#ibcon#read 4, iclass 31, count 0 2006.259.07:38:22.78#ibcon#about to read 5, iclass 31, count 0 2006.259.07:38:22.78#ibcon#read 5, iclass 31, count 0 2006.259.07:38:22.78#ibcon#about to read 6, iclass 31, count 0 2006.259.07:38:22.78#ibcon#read 6, iclass 31, count 0 2006.259.07:38:22.78#ibcon#end of sib2, iclass 31, count 0 2006.259.07:38:22.78#ibcon#*mode == 0, iclass 31, count 0 2006.259.07:38:22.78#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.259.07:38:22.78#ibcon#[28=FRQ=04,712.99\r\n] 2006.259.07:38:22.78#ibcon#*before write, iclass 31, count 0 2006.259.07:38:22.78#ibcon#enter sib2, iclass 31, count 0 2006.259.07:38:22.78#ibcon#flushed, iclass 31, count 0 2006.259.07:38:22.78#ibcon#about to write, iclass 31, count 0 2006.259.07:38:22.78#ibcon#wrote, iclass 31, count 0 2006.259.07:38:22.78#ibcon#about to read 3, iclass 31, count 0 2006.259.07:38:22.82#ibcon#read 3, iclass 31, count 0 2006.259.07:38:22.82#ibcon#about to read 4, iclass 31, count 0 2006.259.07:38:22.82#ibcon#read 4, iclass 31, count 0 2006.259.07:38:22.82#ibcon#about to read 5, iclass 31, count 0 2006.259.07:38:22.82#ibcon#read 5, iclass 31, count 0 2006.259.07:38:22.82#ibcon#about to read 6, iclass 31, count 0 2006.259.07:38:22.82#ibcon#read 6, iclass 31, count 0 2006.259.07:38:22.82#ibcon#end of sib2, iclass 31, count 0 2006.259.07:38:22.82#ibcon#*after write, iclass 31, count 0 2006.259.07:38:22.82#ibcon#*before return 0, iclass 31, count 0 2006.259.07:38:22.82#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.259.07:38:22.82#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.259.07:38:22.82#ibcon#about to clear, iclass 31 cls_cnt 0 2006.259.07:38:22.82#ibcon#cleared, iclass 31 cls_cnt 0 2006.259.07:38:22.82$vc4f8/vb=4,5 2006.259.07:38:22.82#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.259.07:38:22.82#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.259.07:38:22.82#ibcon#ireg 11 cls_cnt 2 2006.259.07:38:22.82#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.259.07:38:22.83#abcon#[5=S1D000X0/0*\r\n] 2006.259.07:38:22.88#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.259.07:38:22.88#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.259.07:38:22.88#ibcon#enter wrdev, iclass 34, count 2 2006.259.07:38:22.88#ibcon#first serial, iclass 34, count 2 2006.259.07:38:22.88#ibcon#enter sib2, iclass 34, count 2 2006.259.07:38:22.88#ibcon#flushed, iclass 34, count 2 2006.259.07:38:22.88#ibcon#about to write, iclass 34, count 2 2006.259.07:38:22.88#ibcon#wrote, iclass 34, count 2 2006.259.07:38:22.88#ibcon#about to read 3, iclass 34, count 2 2006.259.07:38:22.90#ibcon#read 3, iclass 34, count 2 2006.259.07:38:22.90#ibcon#about to read 4, iclass 34, count 2 2006.259.07:38:22.90#ibcon#read 4, iclass 34, count 2 2006.259.07:38:22.90#ibcon#about to read 5, iclass 34, count 2 2006.259.07:38:22.90#ibcon#read 5, iclass 34, count 2 2006.259.07:38:22.90#ibcon#about to read 6, iclass 34, count 2 2006.259.07:38:22.90#ibcon#read 6, iclass 34, count 2 2006.259.07:38:22.90#ibcon#end of sib2, iclass 34, count 2 2006.259.07:38:22.90#ibcon#*mode == 0, iclass 34, count 2 2006.259.07:38:22.90#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.259.07:38:22.90#ibcon#[27=AT04-05\r\n] 2006.259.07:38:22.90#ibcon#*before write, iclass 34, count 2 2006.259.07:38:22.90#ibcon#enter sib2, iclass 34, count 2 2006.259.07:38:22.90#ibcon#flushed, iclass 34, count 2 2006.259.07:38:22.90#ibcon#about to write, iclass 34, count 2 2006.259.07:38:22.90#ibcon#wrote, iclass 34, count 2 2006.259.07:38:22.90#ibcon#about to read 3, iclass 34, count 2 2006.259.07:38:22.93#ibcon#read 3, iclass 34, count 2 2006.259.07:38:22.93#ibcon#about to read 4, iclass 34, count 2 2006.259.07:38:22.93#ibcon#read 4, iclass 34, count 2 2006.259.07:38:22.93#ibcon#about to read 5, iclass 34, count 2 2006.259.07:38:22.93#ibcon#read 5, iclass 34, count 2 2006.259.07:38:22.93#ibcon#about to read 6, iclass 34, count 2 2006.259.07:38:22.93#ibcon#read 6, iclass 34, count 2 2006.259.07:38:22.93#ibcon#end of sib2, iclass 34, count 2 2006.259.07:38:22.93#ibcon#*after write, iclass 34, count 2 2006.259.07:38:22.93#ibcon#*before return 0, iclass 34, count 2 2006.259.07:38:22.93#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.259.07:38:22.93#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.259.07:38:22.93#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.259.07:38:22.93#ibcon#ireg 7 cls_cnt 0 2006.259.07:38:22.93#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.259.07:38:23.05#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.259.07:38:23.05#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.259.07:38:23.05#ibcon#enter wrdev, iclass 34, count 0 2006.259.07:38:23.05#ibcon#first serial, iclass 34, count 0 2006.259.07:38:23.05#ibcon#enter sib2, iclass 34, count 0 2006.259.07:38:23.05#ibcon#flushed, iclass 34, count 0 2006.259.07:38:23.05#ibcon#about to write, iclass 34, count 0 2006.259.07:38:23.05#ibcon#wrote, iclass 34, count 0 2006.259.07:38:23.05#ibcon#about to read 3, iclass 34, count 0 2006.259.07:38:23.07#ibcon#read 3, iclass 34, count 0 2006.259.07:38:23.07#ibcon#about to read 4, iclass 34, count 0 2006.259.07:38:23.07#ibcon#read 4, iclass 34, count 0 2006.259.07:38:23.07#ibcon#about to read 5, iclass 34, count 0 2006.259.07:38:23.07#ibcon#read 5, iclass 34, count 0 2006.259.07:38:23.07#ibcon#about to read 6, iclass 34, count 0 2006.259.07:38:23.07#ibcon#read 6, iclass 34, count 0 2006.259.07:38:23.07#ibcon#end of sib2, iclass 34, count 0 2006.259.07:38:23.07#ibcon#*mode == 0, iclass 34, count 0 2006.259.07:38:23.07#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.259.07:38:23.07#ibcon#[27=USB\r\n] 2006.259.07:38:23.07#ibcon#*before write, iclass 34, count 0 2006.259.07:38:23.07#ibcon#enter sib2, iclass 34, count 0 2006.259.07:38:23.07#ibcon#flushed, iclass 34, count 0 2006.259.07:38:23.07#ibcon#about to write, iclass 34, count 0 2006.259.07:38:23.07#ibcon#wrote, iclass 34, count 0 2006.259.07:38:23.07#ibcon#about to read 3, iclass 34, count 0 2006.259.07:38:23.10#ibcon#read 3, iclass 34, count 0 2006.259.07:38:23.10#ibcon#about to read 4, iclass 34, count 0 2006.259.07:38:23.10#ibcon#read 4, iclass 34, count 0 2006.259.07:38:23.10#ibcon#about to read 5, iclass 34, count 0 2006.259.07:38:23.10#ibcon#read 5, iclass 34, count 0 2006.259.07:38:23.10#ibcon#about to read 6, iclass 34, count 0 2006.259.07:38:23.10#ibcon#read 6, iclass 34, count 0 2006.259.07:38:23.10#ibcon#end of sib2, iclass 34, count 0 2006.259.07:38:23.10#ibcon#*after write, iclass 34, count 0 2006.259.07:38:23.10#ibcon#*before return 0, iclass 34, count 0 2006.259.07:38:23.10#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.259.07:38:23.10#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.259.07:38:23.10#ibcon#about to clear, iclass 34 cls_cnt 0 2006.259.07:38:23.10#ibcon#cleared, iclass 34 cls_cnt 0 2006.259.07:38:23.10$vc4f8/vblo=5,744.99 2006.259.07:38:23.10#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.259.07:38:23.10#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.259.07:38:23.10#ibcon#ireg 17 cls_cnt 0 2006.259.07:38:23.10#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.259.07:38:23.10#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.259.07:38:23.10#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.259.07:38:23.10#ibcon#enter wrdev, iclass 36, count 0 2006.259.07:38:23.10#ibcon#first serial, iclass 36, count 0 2006.259.07:38:23.10#ibcon#enter sib2, iclass 36, count 0 2006.259.07:38:23.10#ibcon#flushed, iclass 36, count 0 2006.259.07:38:23.10#ibcon#about to write, iclass 36, count 0 2006.259.07:38:23.10#ibcon#wrote, iclass 36, count 0 2006.259.07:38:23.10#ibcon#about to read 3, iclass 36, count 0 2006.259.07:38:23.12#ibcon#read 3, iclass 36, count 0 2006.259.07:38:23.12#ibcon#about to read 4, iclass 36, count 0 2006.259.07:38:23.12#ibcon#read 4, iclass 36, count 0 2006.259.07:38:23.12#ibcon#about to read 5, iclass 36, count 0 2006.259.07:38:23.12#ibcon#read 5, iclass 36, count 0 2006.259.07:38:23.12#ibcon#about to read 6, iclass 36, count 0 2006.259.07:38:23.12#ibcon#read 6, iclass 36, count 0 2006.259.07:38:23.12#ibcon#end of sib2, iclass 36, count 0 2006.259.07:38:23.12#ibcon#*mode == 0, iclass 36, count 0 2006.259.07:38:23.12#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.259.07:38:23.12#ibcon#[28=FRQ=05,744.99\r\n] 2006.259.07:38:23.12#ibcon#*before write, iclass 36, count 0 2006.259.07:38:23.12#ibcon#enter sib2, iclass 36, count 0 2006.259.07:38:23.12#ibcon#flushed, iclass 36, count 0 2006.259.07:38:23.12#ibcon#about to write, iclass 36, count 0 2006.259.07:38:23.12#ibcon#wrote, iclass 36, count 0 2006.259.07:38:23.12#ibcon#about to read 3, iclass 36, count 0 2006.259.07:38:23.16#ibcon#read 3, iclass 36, count 0 2006.259.07:38:23.16#ibcon#about to read 4, iclass 36, count 0 2006.259.07:38:23.16#ibcon#read 4, iclass 36, count 0 2006.259.07:38:23.16#ibcon#about to read 5, iclass 36, count 0 2006.259.07:38:23.16#ibcon#read 5, iclass 36, count 0 2006.259.07:38:23.16#ibcon#about to read 6, iclass 36, count 0 2006.259.07:38:23.16#ibcon#read 6, iclass 36, count 0 2006.259.07:38:23.16#ibcon#end of sib2, iclass 36, count 0 2006.259.07:38:23.16#ibcon#*after write, iclass 36, count 0 2006.259.07:38:23.16#ibcon#*before return 0, iclass 36, count 0 2006.259.07:38:23.16#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.259.07:38:23.16#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.259.07:38:23.16#ibcon#about to clear, iclass 36 cls_cnt 0 2006.259.07:38:23.16#ibcon#cleared, iclass 36 cls_cnt 0 2006.259.07:38:23.16$vc4f8/vb=5,4 2006.259.07:38:23.16#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.259.07:38:23.16#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.259.07:38:23.16#ibcon#ireg 11 cls_cnt 2 2006.259.07:38:23.16#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.259.07:38:23.22#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.259.07:38:23.22#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.259.07:38:23.22#ibcon#enter wrdev, iclass 38, count 2 2006.259.07:38:23.22#ibcon#first serial, iclass 38, count 2 2006.259.07:38:23.22#ibcon#enter sib2, iclass 38, count 2 2006.259.07:38:23.22#ibcon#flushed, iclass 38, count 2 2006.259.07:38:23.22#ibcon#about to write, iclass 38, count 2 2006.259.07:38:23.22#ibcon#wrote, iclass 38, count 2 2006.259.07:38:23.22#ibcon#about to read 3, iclass 38, count 2 2006.259.07:38:23.24#ibcon#read 3, iclass 38, count 2 2006.259.07:38:23.24#ibcon#about to read 4, iclass 38, count 2 2006.259.07:38:23.24#ibcon#read 4, iclass 38, count 2 2006.259.07:38:23.24#ibcon#about to read 5, iclass 38, count 2 2006.259.07:38:23.24#ibcon#read 5, iclass 38, count 2 2006.259.07:38:23.24#ibcon#about to read 6, iclass 38, count 2 2006.259.07:38:23.24#ibcon#read 6, iclass 38, count 2 2006.259.07:38:23.24#ibcon#end of sib2, iclass 38, count 2 2006.259.07:38:23.24#ibcon#*mode == 0, iclass 38, count 2 2006.259.07:38:23.24#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.259.07:38:23.24#ibcon#[27=AT05-04\r\n] 2006.259.07:38:23.24#ibcon#*before write, iclass 38, count 2 2006.259.07:38:23.24#ibcon#enter sib2, iclass 38, count 2 2006.259.07:38:23.24#ibcon#flushed, iclass 38, count 2 2006.259.07:38:23.24#ibcon#about to write, iclass 38, count 2 2006.259.07:38:23.24#ibcon#wrote, iclass 38, count 2 2006.259.07:38:23.24#ibcon#about to read 3, iclass 38, count 2 2006.259.07:38:23.27#ibcon#read 3, iclass 38, count 2 2006.259.07:38:23.27#ibcon#about to read 4, iclass 38, count 2 2006.259.07:38:23.27#ibcon#read 4, iclass 38, count 2 2006.259.07:38:23.27#ibcon#about to read 5, iclass 38, count 2 2006.259.07:38:23.27#ibcon#read 5, iclass 38, count 2 2006.259.07:38:23.27#ibcon#about to read 6, iclass 38, count 2 2006.259.07:38:23.27#ibcon#read 6, iclass 38, count 2 2006.259.07:38:23.27#ibcon#end of sib2, iclass 38, count 2 2006.259.07:38:23.27#ibcon#*after write, iclass 38, count 2 2006.259.07:38:23.27#ibcon#*before return 0, iclass 38, count 2 2006.259.07:38:23.27#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.259.07:38:23.27#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.259.07:38:23.27#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.259.07:38:23.27#ibcon#ireg 7 cls_cnt 0 2006.259.07:38:23.27#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.259.07:38:23.39#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.259.07:38:23.39#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.259.07:38:23.39#ibcon#enter wrdev, iclass 38, count 0 2006.259.07:38:23.39#ibcon#first serial, iclass 38, count 0 2006.259.07:38:23.39#ibcon#enter sib2, iclass 38, count 0 2006.259.07:38:23.39#ibcon#flushed, iclass 38, count 0 2006.259.07:38:23.39#ibcon#about to write, iclass 38, count 0 2006.259.07:38:23.39#ibcon#wrote, iclass 38, count 0 2006.259.07:38:23.39#ibcon#about to read 3, iclass 38, count 0 2006.259.07:38:23.41#ibcon#read 3, iclass 38, count 0 2006.259.07:38:23.41#ibcon#about to read 4, iclass 38, count 0 2006.259.07:38:23.41#ibcon#read 4, iclass 38, count 0 2006.259.07:38:23.41#ibcon#about to read 5, iclass 38, count 0 2006.259.07:38:23.41#ibcon#read 5, iclass 38, count 0 2006.259.07:38:23.41#ibcon#about to read 6, iclass 38, count 0 2006.259.07:38:23.41#ibcon#read 6, iclass 38, count 0 2006.259.07:38:23.41#ibcon#end of sib2, iclass 38, count 0 2006.259.07:38:23.41#ibcon#*mode == 0, iclass 38, count 0 2006.259.07:38:23.41#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.259.07:38:23.41#ibcon#[27=USB\r\n] 2006.259.07:38:23.41#ibcon#*before write, iclass 38, count 0 2006.259.07:38:23.41#ibcon#enter sib2, iclass 38, count 0 2006.259.07:38:23.41#ibcon#flushed, iclass 38, count 0 2006.259.07:38:23.41#ibcon#about to write, iclass 38, count 0 2006.259.07:38:23.41#ibcon#wrote, iclass 38, count 0 2006.259.07:38:23.41#ibcon#about to read 3, iclass 38, count 0 2006.259.07:38:23.44#ibcon#read 3, iclass 38, count 0 2006.259.07:38:23.44#ibcon#about to read 4, iclass 38, count 0 2006.259.07:38:23.44#ibcon#read 4, iclass 38, count 0 2006.259.07:38:23.44#ibcon#about to read 5, iclass 38, count 0 2006.259.07:38:23.44#ibcon#read 5, iclass 38, count 0 2006.259.07:38:23.44#ibcon#about to read 6, iclass 38, count 0 2006.259.07:38:23.44#ibcon#read 6, iclass 38, count 0 2006.259.07:38:23.44#ibcon#end of sib2, iclass 38, count 0 2006.259.07:38:23.44#ibcon#*after write, iclass 38, count 0 2006.259.07:38:23.44#ibcon#*before return 0, iclass 38, count 0 2006.259.07:38:23.44#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.259.07:38:23.44#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.259.07:38:23.44#ibcon#about to clear, iclass 38 cls_cnt 0 2006.259.07:38:23.44#ibcon#cleared, iclass 38 cls_cnt 0 2006.259.07:38:23.44$vc4f8/vblo=6,752.99 2006.259.07:38:23.44#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.259.07:38:23.44#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.259.07:38:23.44#ibcon#ireg 17 cls_cnt 0 2006.259.07:38:23.44#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.259.07:38:23.44#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.259.07:38:23.44#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.259.07:38:23.44#ibcon#enter wrdev, iclass 40, count 0 2006.259.07:38:23.44#ibcon#first serial, iclass 40, count 0 2006.259.07:38:23.44#ibcon#enter sib2, iclass 40, count 0 2006.259.07:38:23.44#ibcon#flushed, iclass 40, count 0 2006.259.07:38:23.44#ibcon#about to write, iclass 40, count 0 2006.259.07:38:23.44#ibcon#wrote, iclass 40, count 0 2006.259.07:38:23.44#ibcon#about to read 3, iclass 40, count 0 2006.259.07:38:23.46#ibcon#read 3, iclass 40, count 0 2006.259.07:38:23.46#ibcon#about to read 4, iclass 40, count 0 2006.259.07:38:23.46#ibcon#read 4, iclass 40, count 0 2006.259.07:38:23.46#ibcon#about to read 5, iclass 40, count 0 2006.259.07:38:23.46#ibcon#read 5, iclass 40, count 0 2006.259.07:38:23.46#ibcon#about to read 6, iclass 40, count 0 2006.259.07:38:23.46#ibcon#read 6, iclass 40, count 0 2006.259.07:38:23.46#ibcon#end of sib2, iclass 40, count 0 2006.259.07:38:23.46#ibcon#*mode == 0, iclass 40, count 0 2006.259.07:38:23.46#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.259.07:38:23.46#ibcon#[28=FRQ=06,752.99\r\n] 2006.259.07:38:23.46#ibcon#*before write, iclass 40, count 0 2006.259.07:38:23.46#ibcon#enter sib2, iclass 40, count 0 2006.259.07:38:23.46#ibcon#flushed, iclass 40, count 0 2006.259.07:38:23.46#ibcon#about to write, iclass 40, count 0 2006.259.07:38:23.46#ibcon#wrote, iclass 40, count 0 2006.259.07:38:23.46#ibcon#about to read 3, iclass 40, count 0 2006.259.07:38:23.50#ibcon#read 3, iclass 40, count 0 2006.259.07:38:23.50#ibcon#about to read 4, iclass 40, count 0 2006.259.07:38:23.50#ibcon#read 4, iclass 40, count 0 2006.259.07:38:23.50#ibcon#about to read 5, iclass 40, count 0 2006.259.07:38:23.50#ibcon#read 5, iclass 40, count 0 2006.259.07:38:23.50#ibcon#about to read 6, iclass 40, count 0 2006.259.07:38:23.50#ibcon#read 6, iclass 40, count 0 2006.259.07:38:23.50#ibcon#end of sib2, iclass 40, count 0 2006.259.07:38:23.50#ibcon#*after write, iclass 40, count 0 2006.259.07:38:23.50#ibcon#*before return 0, iclass 40, count 0 2006.259.07:38:23.50#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.259.07:38:23.50#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.259.07:38:23.50#ibcon#about to clear, iclass 40 cls_cnt 0 2006.259.07:38:23.50#ibcon#cleared, iclass 40 cls_cnt 0 2006.259.07:38:23.50$vc4f8/vb=6,4 2006.259.07:38:23.50#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.259.07:38:23.50#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.259.07:38:23.50#ibcon#ireg 11 cls_cnt 2 2006.259.07:38:23.50#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.259.07:38:23.56#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.259.07:38:23.56#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.259.07:38:23.56#ibcon#enter wrdev, iclass 4, count 2 2006.259.07:38:23.56#ibcon#first serial, iclass 4, count 2 2006.259.07:38:23.56#ibcon#enter sib2, iclass 4, count 2 2006.259.07:38:23.56#ibcon#flushed, iclass 4, count 2 2006.259.07:38:23.56#ibcon#about to write, iclass 4, count 2 2006.259.07:38:23.56#ibcon#wrote, iclass 4, count 2 2006.259.07:38:23.56#ibcon#about to read 3, iclass 4, count 2 2006.259.07:38:23.58#ibcon#read 3, iclass 4, count 2 2006.259.07:38:23.58#ibcon#about to read 4, iclass 4, count 2 2006.259.07:38:23.58#ibcon#read 4, iclass 4, count 2 2006.259.07:38:23.58#ibcon#about to read 5, iclass 4, count 2 2006.259.07:38:23.58#ibcon#read 5, iclass 4, count 2 2006.259.07:38:23.58#ibcon#about to read 6, iclass 4, count 2 2006.259.07:38:23.58#ibcon#read 6, iclass 4, count 2 2006.259.07:38:23.58#ibcon#end of sib2, iclass 4, count 2 2006.259.07:38:23.58#ibcon#*mode == 0, iclass 4, count 2 2006.259.07:38:23.58#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.259.07:38:23.58#ibcon#[27=AT06-04\r\n] 2006.259.07:38:23.58#ibcon#*before write, iclass 4, count 2 2006.259.07:38:23.58#ibcon#enter sib2, iclass 4, count 2 2006.259.07:38:23.58#ibcon#flushed, iclass 4, count 2 2006.259.07:38:23.58#ibcon#about to write, iclass 4, count 2 2006.259.07:38:23.58#ibcon#wrote, iclass 4, count 2 2006.259.07:38:23.58#ibcon#about to read 3, iclass 4, count 2 2006.259.07:38:23.61#ibcon#read 3, iclass 4, count 2 2006.259.07:38:23.61#ibcon#about to read 4, iclass 4, count 2 2006.259.07:38:23.61#ibcon#read 4, iclass 4, count 2 2006.259.07:38:23.61#ibcon#about to read 5, iclass 4, count 2 2006.259.07:38:23.61#ibcon#read 5, iclass 4, count 2 2006.259.07:38:23.61#ibcon#about to read 6, iclass 4, count 2 2006.259.07:38:23.61#ibcon#read 6, iclass 4, count 2 2006.259.07:38:23.61#ibcon#end of sib2, iclass 4, count 2 2006.259.07:38:23.61#ibcon#*after write, iclass 4, count 2 2006.259.07:38:23.61#ibcon#*before return 0, iclass 4, count 2 2006.259.07:38:23.61#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.259.07:38:23.61#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.259.07:38:23.61#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.259.07:38:23.61#ibcon#ireg 7 cls_cnt 0 2006.259.07:38:23.61#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.259.07:38:23.73#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.259.07:38:23.73#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.259.07:38:23.73#ibcon#enter wrdev, iclass 4, count 0 2006.259.07:38:23.73#ibcon#first serial, iclass 4, count 0 2006.259.07:38:23.73#ibcon#enter sib2, iclass 4, count 0 2006.259.07:38:23.73#ibcon#flushed, iclass 4, count 0 2006.259.07:38:23.73#ibcon#about to write, iclass 4, count 0 2006.259.07:38:23.73#ibcon#wrote, iclass 4, count 0 2006.259.07:38:23.73#ibcon#about to read 3, iclass 4, count 0 2006.259.07:38:23.75#ibcon#read 3, iclass 4, count 0 2006.259.07:38:23.75#ibcon#about to read 4, iclass 4, count 0 2006.259.07:38:23.75#ibcon#read 4, iclass 4, count 0 2006.259.07:38:23.75#ibcon#about to read 5, iclass 4, count 0 2006.259.07:38:23.75#ibcon#read 5, iclass 4, count 0 2006.259.07:38:23.75#ibcon#about to read 6, iclass 4, count 0 2006.259.07:38:23.75#ibcon#read 6, iclass 4, count 0 2006.259.07:38:23.75#ibcon#end of sib2, iclass 4, count 0 2006.259.07:38:23.75#ibcon#*mode == 0, iclass 4, count 0 2006.259.07:38:23.75#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.259.07:38:23.75#ibcon#[27=USB\r\n] 2006.259.07:38:23.75#ibcon#*before write, iclass 4, count 0 2006.259.07:38:23.75#ibcon#enter sib2, iclass 4, count 0 2006.259.07:38:23.75#ibcon#flushed, iclass 4, count 0 2006.259.07:38:23.75#ibcon#about to write, iclass 4, count 0 2006.259.07:38:23.75#ibcon#wrote, iclass 4, count 0 2006.259.07:38:23.75#ibcon#about to read 3, iclass 4, count 0 2006.259.07:38:23.78#ibcon#read 3, iclass 4, count 0 2006.259.07:38:23.78#ibcon#about to read 4, iclass 4, count 0 2006.259.07:38:23.78#ibcon#read 4, iclass 4, count 0 2006.259.07:38:23.78#ibcon#about to read 5, iclass 4, count 0 2006.259.07:38:23.78#ibcon#read 5, iclass 4, count 0 2006.259.07:38:23.78#ibcon#about to read 6, iclass 4, count 0 2006.259.07:38:23.78#ibcon#read 6, iclass 4, count 0 2006.259.07:38:23.78#ibcon#end of sib2, iclass 4, count 0 2006.259.07:38:23.78#ibcon#*after write, iclass 4, count 0 2006.259.07:38:23.78#ibcon#*before return 0, iclass 4, count 0 2006.259.07:38:23.78#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.259.07:38:23.78#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.259.07:38:23.78#ibcon#about to clear, iclass 4 cls_cnt 0 2006.259.07:38:23.78#ibcon#cleared, iclass 4 cls_cnt 0 2006.259.07:38:23.78$vc4f8/vabw=wide 2006.259.07:38:23.78#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.259.07:38:23.78#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.259.07:38:23.78#ibcon#ireg 8 cls_cnt 0 2006.259.07:38:23.78#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.259.07:38:23.78#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.259.07:38:23.78#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.259.07:38:23.78#ibcon#enter wrdev, iclass 6, count 0 2006.259.07:38:23.78#ibcon#first serial, iclass 6, count 0 2006.259.07:38:23.78#ibcon#enter sib2, iclass 6, count 0 2006.259.07:38:23.78#ibcon#flushed, iclass 6, count 0 2006.259.07:38:23.78#ibcon#about to write, iclass 6, count 0 2006.259.07:38:23.78#ibcon#wrote, iclass 6, count 0 2006.259.07:38:23.78#ibcon#about to read 3, iclass 6, count 0 2006.259.07:38:23.80#ibcon#read 3, iclass 6, count 0 2006.259.07:38:23.80#ibcon#about to read 4, iclass 6, count 0 2006.259.07:38:23.80#ibcon#read 4, iclass 6, count 0 2006.259.07:38:23.80#ibcon#about to read 5, iclass 6, count 0 2006.259.07:38:23.80#ibcon#read 5, iclass 6, count 0 2006.259.07:38:23.80#ibcon#about to read 6, iclass 6, count 0 2006.259.07:38:23.80#ibcon#read 6, iclass 6, count 0 2006.259.07:38:23.80#ibcon#end of sib2, iclass 6, count 0 2006.259.07:38:23.80#ibcon#*mode == 0, iclass 6, count 0 2006.259.07:38:23.80#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.259.07:38:23.80#ibcon#[25=BW32\r\n] 2006.259.07:38:23.80#ibcon#*before write, iclass 6, count 0 2006.259.07:38:23.80#ibcon#enter sib2, iclass 6, count 0 2006.259.07:38:23.80#ibcon#flushed, iclass 6, count 0 2006.259.07:38:23.80#ibcon#about to write, iclass 6, count 0 2006.259.07:38:23.80#ibcon#wrote, iclass 6, count 0 2006.259.07:38:23.80#ibcon#about to read 3, iclass 6, count 0 2006.259.07:38:23.83#ibcon#read 3, iclass 6, count 0 2006.259.07:38:23.83#ibcon#about to read 4, iclass 6, count 0 2006.259.07:38:23.83#ibcon#read 4, iclass 6, count 0 2006.259.07:38:23.83#ibcon#about to read 5, iclass 6, count 0 2006.259.07:38:23.83#ibcon#read 5, iclass 6, count 0 2006.259.07:38:23.83#ibcon#about to read 6, iclass 6, count 0 2006.259.07:38:23.83#ibcon#read 6, iclass 6, count 0 2006.259.07:38:23.83#ibcon#end of sib2, iclass 6, count 0 2006.259.07:38:23.83#ibcon#*after write, iclass 6, count 0 2006.259.07:38:23.83#ibcon#*before return 0, iclass 6, count 0 2006.259.07:38:23.83#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.259.07:38:23.83#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.259.07:38:23.83#ibcon#about to clear, iclass 6 cls_cnt 0 2006.259.07:38:23.83#ibcon#cleared, iclass 6 cls_cnt 0 2006.259.07:38:23.83$vc4f8/vbbw=wide 2006.259.07:38:23.83#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.259.07:38:23.83#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.259.07:38:23.83#ibcon#ireg 8 cls_cnt 0 2006.259.07:38:23.83#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.259.07:38:23.90#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.259.07:38:23.90#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.259.07:38:23.90#ibcon#enter wrdev, iclass 10, count 0 2006.259.07:38:23.90#ibcon#first serial, iclass 10, count 0 2006.259.07:38:23.90#ibcon#enter sib2, iclass 10, count 0 2006.259.07:38:23.90#ibcon#flushed, iclass 10, count 0 2006.259.07:38:23.90#ibcon#about to write, iclass 10, count 0 2006.259.07:38:23.90#ibcon#wrote, iclass 10, count 0 2006.259.07:38:23.90#ibcon#about to read 3, iclass 10, count 0 2006.259.07:38:23.92#ibcon#read 3, iclass 10, count 0 2006.259.07:38:23.92#ibcon#about to read 4, iclass 10, count 0 2006.259.07:38:23.92#ibcon#read 4, iclass 10, count 0 2006.259.07:38:23.92#ibcon#about to read 5, iclass 10, count 0 2006.259.07:38:23.92#ibcon#read 5, iclass 10, count 0 2006.259.07:38:23.92#ibcon#about to read 6, iclass 10, count 0 2006.259.07:38:23.92#ibcon#read 6, iclass 10, count 0 2006.259.07:38:23.92#ibcon#end of sib2, iclass 10, count 0 2006.259.07:38:23.92#ibcon#*mode == 0, iclass 10, count 0 2006.259.07:38:23.92#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.259.07:38:23.92#ibcon#[27=BW32\r\n] 2006.259.07:38:23.92#ibcon#*before write, iclass 10, count 0 2006.259.07:38:23.92#ibcon#enter sib2, iclass 10, count 0 2006.259.07:38:23.92#ibcon#flushed, iclass 10, count 0 2006.259.07:38:23.92#ibcon#about to write, iclass 10, count 0 2006.259.07:38:23.92#ibcon#wrote, iclass 10, count 0 2006.259.07:38:23.92#ibcon#about to read 3, iclass 10, count 0 2006.259.07:38:23.95#ibcon#read 3, iclass 10, count 0 2006.259.07:38:23.95#ibcon#about to read 4, iclass 10, count 0 2006.259.07:38:23.95#ibcon#read 4, iclass 10, count 0 2006.259.07:38:23.95#ibcon#about to read 5, iclass 10, count 0 2006.259.07:38:23.95#ibcon#read 5, iclass 10, count 0 2006.259.07:38:23.95#ibcon#about to read 6, iclass 10, count 0 2006.259.07:38:23.95#ibcon#read 6, iclass 10, count 0 2006.259.07:38:23.95#ibcon#end of sib2, iclass 10, count 0 2006.259.07:38:23.95#ibcon#*after write, iclass 10, count 0 2006.259.07:38:23.95#ibcon#*before return 0, iclass 10, count 0 2006.259.07:38:23.95#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.259.07:38:23.95#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.259.07:38:23.95#ibcon#about to clear, iclass 10 cls_cnt 0 2006.259.07:38:23.95#ibcon#cleared, iclass 10 cls_cnt 0 2006.259.07:38:23.95$4f8m12a/ifd4f 2006.259.07:38:23.95$ifd4f/lo= 2006.259.07:38:23.95$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.259.07:38:23.95$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.259.07:38:23.95$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.259.07:38:23.95$ifd4f/patch= 2006.259.07:38:23.95$ifd4f/patch=lo1,a1,a2,a3,a4 2006.259.07:38:23.95$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.259.07:38:23.95$ifd4f/patch=lo3,a5,a6,a7,a8 2006.259.07:38:23.95$4f8m12a/"form=m,16.000,1:2 2006.259.07:38:23.95$4f8m12a/"tpicd 2006.259.07:38:23.95$4f8m12a/echo=off 2006.259.07:38:23.95$4f8m12a/xlog=off 2006.259.07:38:23.95:!2006.259.07:38:50 2006.259.07:38:37.14#trakl#Source acquired 2006.259.07:38:38.14#flagr#flagr/antenna,acquired 2006.259.07:38:50.00:preob 2006.259.07:38:51.14/onsource/TRACKING 2006.259.07:38:51.14:!2006.259.07:39:00 2006.259.07:39:00.00:data_valid=on 2006.259.07:39:00.00:midob 2006.259.07:39:00.14/onsource/TRACKING 2006.259.07:39:00.14/wx/22.30,1012.9,84 2006.259.07:39:00.35/cable/+6.4597E-03 2006.259.07:39:01.44/va/01,08,usb,yes,33,34 2006.259.07:39:01.44/va/02,07,usb,yes,32,34 2006.259.07:39:01.44/va/03,08,usb,yes,25,25 2006.259.07:39:01.44/va/04,07,usb,yes,34,37 2006.259.07:39:01.44/va/05,07,usb,yes,38,40 2006.259.07:39:01.44/va/06,06,usb,yes,37,37 2006.259.07:39:01.44/va/07,06,usb,yes,37,37 2006.259.07:39:01.44/va/08,06,usb,yes,40,39 2006.259.07:39:01.67/valo/01,532.99,yes,locked 2006.259.07:39:01.67/valo/02,572.99,yes,locked 2006.259.07:39:01.67/valo/03,672.99,yes,locked 2006.259.07:39:01.67/valo/04,832.99,yes,locked 2006.259.07:39:01.67/valo/05,652.99,yes,locked 2006.259.07:39:01.67/valo/06,772.99,yes,locked 2006.259.07:39:01.67/valo/07,832.99,yes,locked 2006.259.07:39:01.67/valo/08,852.99,yes,locked 2006.259.07:39:02.76/vb/01,04,usb,yes,32,30 2006.259.07:39:02.76/vb/02,05,usb,yes,30,31 2006.259.07:39:02.76/vb/03,04,usb,yes,30,34 2006.259.07:39:02.76/vb/04,05,usb,yes,27,27 2006.259.07:39:02.76/vb/05,04,usb,yes,29,33 2006.259.07:39:02.76/vb/06,04,usb,yes,30,33 2006.259.07:39:02.76/vb/07,04,usb,yes,32,32 2006.259.07:39:02.76/vb/08,04,usb,yes,30,33 2006.259.07:39:02.99/vblo/01,632.99,yes,locked 2006.259.07:39:02.99/vblo/02,640.99,yes,locked 2006.259.07:39:02.99/vblo/03,656.99,yes,locked 2006.259.07:39:02.99/vblo/04,712.99,yes,locked 2006.259.07:39:02.99/vblo/05,744.99,yes,locked 2006.259.07:39:02.99/vblo/06,752.99,yes,locked 2006.259.07:39:02.99/vblo/07,734.99,yes,locked 2006.259.07:39:02.99/vblo/08,744.99,yes,locked 2006.259.07:39:03.14/vabw/8 2006.259.07:39:03.29/vbbw/8 2006.259.07:39:03.38/xfe/off,on,15.2 2006.259.07:39:03.76/ifatt/23,28,28,28 2006.259.07:39:04.08/fmout-gps/S +4.50E-07 2006.259.07:39:04.12:!2006.259.07:40:00 2006.259.07:40:00.00:data_valid=off 2006.259.07:40:00.00:postob 2006.259.07:40:00.23/cable/+6.4594E-03 2006.259.07:40:00.23/wx/22.29,1013.0,85 2006.259.07:40:01.08/fmout-gps/S +4.49E-07 2006.259.07:40:01.08:scan_name=259-0740,k06259,60 2006.259.07:40:01.09:source=1044+719,104827.62,714335.9,2000.0,ccw 2006.259.07:40:01.13#flagr#flagr/antenna,new-source 2006.259.07:40:02.13:checkk5 2006.259.07:40:02.52/chk_autoobs//k5ts1/ autoobs is running! 2006.259.07:40:02.90/chk_autoobs//k5ts2/ autoobs is running! 2006.259.07:40:03.38/chk_autoobs//k5ts3/ autoobs is running! 2006.259.07:40:03.79/chk_autoobs//k5ts4/ autoobs is running! 2006.259.07:40:04.21/chk_obsdata//k5ts1/T2590739??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.259.07:40:04.63/chk_obsdata//k5ts2/T2590739??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.259.07:40:05.01/chk_obsdata//k5ts3/T2590739??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.259.07:40:05.41/chk_obsdata//k5ts4/T2590739??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.259.07:40:06.22/k5log//k5ts1_log_newline 2006.259.07:40:07.56/k5log//k5ts2_log_newline 2006.259.07:40:08.56/k5log//k5ts3_log_newline 2006.259.07:40:09.30/k5log//k5ts4_log_newline 2006.259.07:40:09.32/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.259.07:40:09.32:4f8m12a=1 2006.259.07:40:09.32$4f8m12a/echo=on 2006.259.07:40:09.32$4f8m12a/pcalon 2006.259.07:40:09.32$pcalon/"no phase cal control is implemented here 2006.259.07:40:09.32$4f8m12a/"tpicd=stop 2006.259.07:40:09.32$4f8m12a/vc4f8 2006.259.07:40:09.32$vc4f8/valo=1,532.99 2006.259.07:40:09.32#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.259.07:40:09.32#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.259.07:40:09.32#ibcon#ireg 17 cls_cnt 0 2006.259.07:40:09.32#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.259.07:40:09.32#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.259.07:40:09.32#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.259.07:40:09.32#ibcon#enter wrdev, iclass 17, count 0 2006.259.07:40:09.32#ibcon#first serial, iclass 17, count 0 2006.259.07:40:09.32#ibcon#enter sib2, iclass 17, count 0 2006.259.07:40:09.32#ibcon#flushed, iclass 17, count 0 2006.259.07:40:09.32#ibcon#about to write, iclass 17, count 0 2006.259.07:40:09.32#ibcon#wrote, iclass 17, count 0 2006.259.07:40:09.32#ibcon#about to read 3, iclass 17, count 0 2006.259.07:40:09.37#ibcon#read 3, iclass 17, count 0 2006.259.07:40:09.37#ibcon#about to read 4, iclass 17, count 0 2006.259.07:40:09.37#ibcon#read 4, iclass 17, count 0 2006.259.07:40:09.37#ibcon#about to read 5, iclass 17, count 0 2006.259.07:40:09.37#ibcon#read 5, iclass 17, count 0 2006.259.07:40:09.37#ibcon#about to read 6, iclass 17, count 0 2006.259.07:40:09.37#ibcon#read 6, iclass 17, count 0 2006.259.07:40:09.37#ibcon#end of sib2, iclass 17, count 0 2006.259.07:40:09.37#ibcon#*mode == 0, iclass 17, count 0 2006.259.07:40:09.37#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.259.07:40:09.37#ibcon#[26=FRQ=01,532.99\r\n] 2006.259.07:40:09.37#ibcon#*before write, iclass 17, count 0 2006.259.07:40:09.37#ibcon#enter sib2, iclass 17, count 0 2006.259.07:40:09.37#ibcon#flushed, iclass 17, count 0 2006.259.07:40:09.37#ibcon#about to write, iclass 17, count 0 2006.259.07:40:09.37#ibcon#wrote, iclass 17, count 0 2006.259.07:40:09.37#ibcon#about to read 3, iclass 17, count 0 2006.259.07:40:09.42#ibcon#read 3, iclass 17, count 0 2006.259.07:40:09.42#ibcon#about to read 4, iclass 17, count 0 2006.259.07:40:09.42#ibcon#read 4, iclass 17, count 0 2006.259.07:40:09.42#ibcon#about to read 5, iclass 17, count 0 2006.259.07:40:09.42#ibcon#read 5, iclass 17, count 0 2006.259.07:40:09.42#ibcon#about to read 6, iclass 17, count 0 2006.259.07:40:09.42#ibcon#read 6, iclass 17, count 0 2006.259.07:40:09.42#ibcon#end of sib2, iclass 17, count 0 2006.259.07:40:09.42#ibcon#*after write, iclass 17, count 0 2006.259.07:40:09.42#ibcon#*before return 0, iclass 17, count 0 2006.259.07:40:09.42#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.259.07:40:09.42#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.259.07:40:09.42#ibcon#about to clear, iclass 17 cls_cnt 0 2006.259.07:40:09.42#ibcon#cleared, iclass 17 cls_cnt 0 2006.259.07:40:09.42$vc4f8/va=1,8 2006.259.07:40:09.42#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.259.07:40:09.42#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.259.07:40:09.42#ibcon#ireg 11 cls_cnt 2 2006.259.07:40:09.42#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.259.07:40:09.42#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.259.07:40:09.42#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.259.07:40:09.42#ibcon#enter wrdev, iclass 19, count 2 2006.259.07:40:09.42#ibcon#first serial, iclass 19, count 2 2006.259.07:40:09.42#ibcon#enter sib2, iclass 19, count 2 2006.259.07:40:09.42#ibcon#flushed, iclass 19, count 2 2006.259.07:40:09.42#ibcon#about to write, iclass 19, count 2 2006.259.07:40:09.42#ibcon#wrote, iclass 19, count 2 2006.259.07:40:09.42#ibcon#about to read 3, iclass 19, count 2 2006.259.07:40:09.44#ibcon#read 3, iclass 19, count 2 2006.259.07:40:09.44#ibcon#about to read 4, iclass 19, count 2 2006.259.07:40:09.44#ibcon#read 4, iclass 19, count 2 2006.259.07:40:09.44#ibcon#about to read 5, iclass 19, count 2 2006.259.07:40:09.44#ibcon#read 5, iclass 19, count 2 2006.259.07:40:09.44#ibcon#about to read 6, iclass 19, count 2 2006.259.07:40:09.44#ibcon#read 6, iclass 19, count 2 2006.259.07:40:09.44#ibcon#end of sib2, iclass 19, count 2 2006.259.07:40:09.44#ibcon#*mode == 0, iclass 19, count 2 2006.259.07:40:09.44#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.259.07:40:09.44#ibcon#[25=AT01-08\r\n] 2006.259.07:40:09.44#ibcon#*before write, iclass 19, count 2 2006.259.07:40:09.44#ibcon#enter sib2, iclass 19, count 2 2006.259.07:40:09.44#ibcon#flushed, iclass 19, count 2 2006.259.07:40:09.44#ibcon#about to write, iclass 19, count 2 2006.259.07:40:09.44#ibcon#wrote, iclass 19, count 2 2006.259.07:40:09.44#ibcon#about to read 3, iclass 19, count 2 2006.259.07:40:09.48#ibcon#read 3, iclass 19, count 2 2006.259.07:40:09.48#ibcon#about to read 4, iclass 19, count 2 2006.259.07:40:09.48#ibcon#read 4, iclass 19, count 2 2006.259.07:40:09.48#ibcon#about to read 5, iclass 19, count 2 2006.259.07:40:09.48#ibcon#read 5, iclass 19, count 2 2006.259.07:40:09.48#ibcon#about to read 6, iclass 19, count 2 2006.259.07:40:09.48#ibcon#read 6, iclass 19, count 2 2006.259.07:40:09.48#ibcon#end of sib2, iclass 19, count 2 2006.259.07:40:09.48#ibcon#*after write, iclass 19, count 2 2006.259.07:40:09.48#ibcon#*before return 0, iclass 19, count 2 2006.259.07:40:09.48#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.259.07:40:09.48#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.259.07:40:09.48#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.259.07:40:09.48#ibcon#ireg 7 cls_cnt 0 2006.259.07:40:09.48#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.259.07:40:09.60#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.259.07:40:09.60#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.259.07:40:09.60#ibcon#enter wrdev, iclass 19, count 0 2006.259.07:40:09.60#ibcon#first serial, iclass 19, count 0 2006.259.07:40:09.60#ibcon#enter sib2, iclass 19, count 0 2006.259.07:40:09.60#ibcon#flushed, iclass 19, count 0 2006.259.07:40:09.60#ibcon#about to write, iclass 19, count 0 2006.259.07:40:09.60#ibcon#wrote, iclass 19, count 0 2006.259.07:40:09.60#ibcon#about to read 3, iclass 19, count 0 2006.259.07:40:09.62#ibcon#read 3, iclass 19, count 0 2006.259.07:40:09.62#ibcon#about to read 4, iclass 19, count 0 2006.259.07:40:09.62#ibcon#read 4, iclass 19, count 0 2006.259.07:40:09.62#ibcon#about to read 5, iclass 19, count 0 2006.259.07:40:09.62#ibcon#read 5, iclass 19, count 0 2006.259.07:40:09.62#ibcon#about to read 6, iclass 19, count 0 2006.259.07:40:09.62#ibcon#read 6, iclass 19, count 0 2006.259.07:40:09.62#ibcon#end of sib2, iclass 19, count 0 2006.259.07:40:09.62#ibcon#*mode == 0, iclass 19, count 0 2006.259.07:40:09.62#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.259.07:40:09.62#ibcon#[25=USB\r\n] 2006.259.07:40:09.62#ibcon#*before write, iclass 19, count 0 2006.259.07:40:09.62#ibcon#enter sib2, iclass 19, count 0 2006.259.07:40:09.62#ibcon#flushed, iclass 19, count 0 2006.259.07:40:09.62#ibcon#about to write, iclass 19, count 0 2006.259.07:40:09.62#ibcon#wrote, iclass 19, count 0 2006.259.07:40:09.62#ibcon#about to read 3, iclass 19, count 0 2006.259.07:40:09.65#ibcon#read 3, iclass 19, count 0 2006.259.07:40:09.65#ibcon#about to read 4, iclass 19, count 0 2006.259.07:40:09.65#ibcon#read 4, iclass 19, count 0 2006.259.07:40:09.65#ibcon#about to read 5, iclass 19, count 0 2006.259.07:40:09.65#ibcon#read 5, iclass 19, count 0 2006.259.07:40:09.65#ibcon#about to read 6, iclass 19, count 0 2006.259.07:40:09.65#ibcon#read 6, iclass 19, count 0 2006.259.07:40:09.65#ibcon#end of sib2, iclass 19, count 0 2006.259.07:40:09.65#ibcon#*after write, iclass 19, count 0 2006.259.07:40:09.65#ibcon#*before return 0, iclass 19, count 0 2006.259.07:40:09.65#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.259.07:40:09.65#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.259.07:40:09.65#ibcon#about to clear, iclass 19 cls_cnt 0 2006.259.07:40:09.65#ibcon#cleared, iclass 19 cls_cnt 0 2006.259.07:40:09.65$vc4f8/valo=2,572.99 2006.259.07:40:09.65#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.259.07:40:09.65#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.259.07:40:09.65#ibcon#ireg 17 cls_cnt 0 2006.259.07:40:09.65#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.259.07:40:09.65#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.259.07:40:09.65#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.259.07:40:09.65#ibcon#enter wrdev, iclass 21, count 0 2006.259.07:40:09.65#ibcon#first serial, iclass 21, count 0 2006.259.07:40:09.65#ibcon#enter sib2, iclass 21, count 0 2006.259.07:40:09.65#ibcon#flushed, iclass 21, count 0 2006.259.07:40:09.65#ibcon#about to write, iclass 21, count 0 2006.259.07:40:09.65#ibcon#wrote, iclass 21, count 0 2006.259.07:40:09.65#ibcon#about to read 3, iclass 21, count 0 2006.259.07:40:09.67#ibcon#read 3, iclass 21, count 0 2006.259.07:40:09.67#ibcon#about to read 4, iclass 21, count 0 2006.259.07:40:09.67#ibcon#read 4, iclass 21, count 0 2006.259.07:40:09.67#ibcon#about to read 5, iclass 21, count 0 2006.259.07:40:09.67#ibcon#read 5, iclass 21, count 0 2006.259.07:40:09.67#ibcon#about to read 6, iclass 21, count 0 2006.259.07:40:09.67#ibcon#read 6, iclass 21, count 0 2006.259.07:40:09.67#ibcon#end of sib2, iclass 21, count 0 2006.259.07:40:09.67#ibcon#*mode == 0, iclass 21, count 0 2006.259.07:40:09.67#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.259.07:40:09.67#ibcon#[26=FRQ=02,572.99\r\n] 2006.259.07:40:09.67#ibcon#*before write, iclass 21, count 0 2006.259.07:40:09.67#ibcon#enter sib2, iclass 21, count 0 2006.259.07:40:09.67#ibcon#flushed, iclass 21, count 0 2006.259.07:40:09.67#ibcon#about to write, iclass 21, count 0 2006.259.07:40:09.67#ibcon#wrote, iclass 21, count 0 2006.259.07:40:09.67#ibcon#about to read 3, iclass 21, count 0 2006.259.07:40:09.71#ibcon#read 3, iclass 21, count 0 2006.259.07:40:09.71#ibcon#about to read 4, iclass 21, count 0 2006.259.07:40:09.71#ibcon#read 4, iclass 21, count 0 2006.259.07:40:09.71#ibcon#about to read 5, iclass 21, count 0 2006.259.07:40:09.71#ibcon#read 5, iclass 21, count 0 2006.259.07:40:09.71#ibcon#about to read 6, iclass 21, count 0 2006.259.07:40:09.71#ibcon#read 6, iclass 21, count 0 2006.259.07:40:09.71#ibcon#end of sib2, iclass 21, count 0 2006.259.07:40:09.71#ibcon#*after write, iclass 21, count 0 2006.259.07:40:09.71#ibcon#*before return 0, iclass 21, count 0 2006.259.07:40:09.71#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.259.07:40:09.71#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.259.07:40:09.71#ibcon#about to clear, iclass 21 cls_cnt 0 2006.259.07:40:09.71#ibcon#cleared, iclass 21 cls_cnt 0 2006.259.07:40:09.71$vc4f8/va=2,7 2006.259.07:40:09.71#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.259.07:40:09.71#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.259.07:40:09.71#ibcon#ireg 11 cls_cnt 2 2006.259.07:40:09.71#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.259.07:40:09.77#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.259.07:40:09.77#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.259.07:40:09.77#ibcon#enter wrdev, iclass 23, count 2 2006.259.07:40:09.77#ibcon#first serial, iclass 23, count 2 2006.259.07:40:09.77#ibcon#enter sib2, iclass 23, count 2 2006.259.07:40:09.77#ibcon#flushed, iclass 23, count 2 2006.259.07:40:09.77#ibcon#about to write, iclass 23, count 2 2006.259.07:40:09.77#ibcon#wrote, iclass 23, count 2 2006.259.07:40:09.77#ibcon#about to read 3, iclass 23, count 2 2006.259.07:40:09.80#ibcon#read 3, iclass 23, count 2 2006.259.07:40:09.80#ibcon#about to read 4, iclass 23, count 2 2006.259.07:40:09.80#ibcon#read 4, iclass 23, count 2 2006.259.07:40:09.80#ibcon#about to read 5, iclass 23, count 2 2006.259.07:40:09.80#ibcon#read 5, iclass 23, count 2 2006.259.07:40:09.80#ibcon#about to read 6, iclass 23, count 2 2006.259.07:40:09.80#ibcon#read 6, iclass 23, count 2 2006.259.07:40:09.80#ibcon#end of sib2, iclass 23, count 2 2006.259.07:40:09.80#ibcon#*mode == 0, iclass 23, count 2 2006.259.07:40:09.80#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.259.07:40:09.80#ibcon#[25=AT02-07\r\n] 2006.259.07:40:09.80#ibcon#*before write, iclass 23, count 2 2006.259.07:40:09.80#ibcon#enter sib2, iclass 23, count 2 2006.259.07:40:09.80#ibcon#flushed, iclass 23, count 2 2006.259.07:40:09.80#ibcon#about to write, iclass 23, count 2 2006.259.07:40:09.80#ibcon#wrote, iclass 23, count 2 2006.259.07:40:09.80#ibcon#about to read 3, iclass 23, count 2 2006.259.07:40:09.83#ibcon#read 3, iclass 23, count 2 2006.259.07:40:09.83#ibcon#about to read 4, iclass 23, count 2 2006.259.07:40:09.83#ibcon#read 4, iclass 23, count 2 2006.259.07:40:09.83#ibcon#about to read 5, iclass 23, count 2 2006.259.07:40:09.83#ibcon#read 5, iclass 23, count 2 2006.259.07:40:09.83#ibcon#about to read 6, iclass 23, count 2 2006.259.07:40:09.83#ibcon#read 6, iclass 23, count 2 2006.259.07:40:09.83#ibcon#end of sib2, iclass 23, count 2 2006.259.07:40:09.83#ibcon#*after write, iclass 23, count 2 2006.259.07:40:09.83#ibcon#*before return 0, iclass 23, count 2 2006.259.07:40:09.83#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.259.07:40:09.83#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.259.07:40:09.83#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.259.07:40:09.83#ibcon#ireg 7 cls_cnt 0 2006.259.07:40:09.83#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.259.07:40:09.95#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.259.07:40:09.95#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.259.07:40:09.95#ibcon#enter wrdev, iclass 23, count 0 2006.259.07:40:09.95#ibcon#first serial, iclass 23, count 0 2006.259.07:40:09.95#ibcon#enter sib2, iclass 23, count 0 2006.259.07:40:09.95#ibcon#flushed, iclass 23, count 0 2006.259.07:40:09.95#ibcon#about to write, iclass 23, count 0 2006.259.07:40:09.95#ibcon#wrote, iclass 23, count 0 2006.259.07:40:09.95#ibcon#about to read 3, iclass 23, count 0 2006.259.07:40:09.97#ibcon#read 3, iclass 23, count 0 2006.259.07:40:09.97#ibcon#about to read 4, iclass 23, count 0 2006.259.07:40:09.97#ibcon#read 4, iclass 23, count 0 2006.259.07:40:09.97#ibcon#about to read 5, iclass 23, count 0 2006.259.07:40:09.97#ibcon#read 5, iclass 23, count 0 2006.259.07:40:09.97#ibcon#about to read 6, iclass 23, count 0 2006.259.07:40:09.97#ibcon#read 6, iclass 23, count 0 2006.259.07:40:09.97#ibcon#end of sib2, iclass 23, count 0 2006.259.07:40:09.97#ibcon#*mode == 0, iclass 23, count 0 2006.259.07:40:09.97#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.259.07:40:09.97#ibcon#[25=USB\r\n] 2006.259.07:40:09.97#ibcon#*before write, iclass 23, count 0 2006.259.07:40:09.97#ibcon#enter sib2, iclass 23, count 0 2006.259.07:40:09.97#ibcon#flushed, iclass 23, count 0 2006.259.07:40:09.97#ibcon#about to write, iclass 23, count 0 2006.259.07:40:09.97#ibcon#wrote, iclass 23, count 0 2006.259.07:40:09.97#ibcon#about to read 3, iclass 23, count 0 2006.259.07:40:10.00#ibcon#read 3, iclass 23, count 0 2006.259.07:40:10.00#ibcon#about to read 4, iclass 23, count 0 2006.259.07:40:10.00#ibcon#read 4, iclass 23, count 0 2006.259.07:40:10.00#ibcon#about to read 5, iclass 23, count 0 2006.259.07:40:10.00#ibcon#read 5, iclass 23, count 0 2006.259.07:40:10.00#ibcon#about to read 6, iclass 23, count 0 2006.259.07:40:10.00#ibcon#read 6, iclass 23, count 0 2006.259.07:40:10.00#ibcon#end of sib2, iclass 23, count 0 2006.259.07:40:10.00#ibcon#*after write, iclass 23, count 0 2006.259.07:40:10.00#ibcon#*before return 0, iclass 23, count 0 2006.259.07:40:10.00#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.259.07:40:10.00#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.259.07:40:10.00#ibcon#about to clear, iclass 23 cls_cnt 0 2006.259.07:40:10.00#ibcon#cleared, iclass 23 cls_cnt 0 2006.259.07:40:10.00$vc4f8/valo=3,672.99 2006.259.07:40:10.00#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.259.07:40:10.00#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.259.07:40:10.00#ibcon#ireg 17 cls_cnt 0 2006.259.07:40:10.00#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.259.07:40:10.00#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.259.07:40:10.00#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.259.07:40:10.00#ibcon#enter wrdev, iclass 25, count 0 2006.259.07:40:10.00#ibcon#first serial, iclass 25, count 0 2006.259.07:40:10.00#ibcon#enter sib2, iclass 25, count 0 2006.259.07:40:10.00#ibcon#flushed, iclass 25, count 0 2006.259.07:40:10.00#ibcon#about to write, iclass 25, count 0 2006.259.07:40:10.00#ibcon#wrote, iclass 25, count 0 2006.259.07:40:10.00#ibcon#about to read 3, iclass 25, count 0 2006.259.07:40:10.02#ibcon#read 3, iclass 25, count 0 2006.259.07:40:10.02#ibcon#about to read 4, iclass 25, count 0 2006.259.07:40:10.02#ibcon#read 4, iclass 25, count 0 2006.259.07:40:10.02#ibcon#about to read 5, iclass 25, count 0 2006.259.07:40:10.02#ibcon#read 5, iclass 25, count 0 2006.259.07:40:10.02#ibcon#about to read 6, iclass 25, count 0 2006.259.07:40:10.02#ibcon#read 6, iclass 25, count 0 2006.259.07:40:10.02#ibcon#end of sib2, iclass 25, count 0 2006.259.07:40:10.02#ibcon#*mode == 0, iclass 25, count 0 2006.259.07:40:10.02#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.259.07:40:10.02#ibcon#[26=FRQ=03,672.99\r\n] 2006.259.07:40:10.02#ibcon#*before write, iclass 25, count 0 2006.259.07:40:10.02#ibcon#enter sib2, iclass 25, count 0 2006.259.07:40:10.02#ibcon#flushed, iclass 25, count 0 2006.259.07:40:10.02#ibcon#about to write, iclass 25, count 0 2006.259.07:40:10.02#ibcon#wrote, iclass 25, count 0 2006.259.07:40:10.02#ibcon#about to read 3, iclass 25, count 0 2006.259.07:40:10.06#ibcon#read 3, iclass 25, count 0 2006.259.07:40:10.06#ibcon#about to read 4, iclass 25, count 0 2006.259.07:40:10.06#ibcon#read 4, iclass 25, count 0 2006.259.07:40:10.06#ibcon#about to read 5, iclass 25, count 0 2006.259.07:40:10.06#ibcon#read 5, iclass 25, count 0 2006.259.07:40:10.06#ibcon#about to read 6, iclass 25, count 0 2006.259.07:40:10.06#ibcon#read 6, iclass 25, count 0 2006.259.07:40:10.06#ibcon#end of sib2, iclass 25, count 0 2006.259.07:40:10.06#ibcon#*after write, iclass 25, count 0 2006.259.07:40:10.06#ibcon#*before return 0, iclass 25, count 0 2006.259.07:40:10.06#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.259.07:40:10.06#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.259.07:40:10.06#ibcon#about to clear, iclass 25 cls_cnt 0 2006.259.07:40:10.06#ibcon#cleared, iclass 25 cls_cnt 0 2006.259.07:40:10.06$vc4f8/va=3,8 2006.259.07:40:10.06#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.259.07:40:10.06#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.259.07:40:10.06#ibcon#ireg 11 cls_cnt 2 2006.259.07:40:10.06#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.259.07:40:10.12#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.259.07:40:10.12#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.259.07:40:10.12#ibcon#enter wrdev, iclass 27, count 2 2006.259.07:40:10.12#ibcon#first serial, iclass 27, count 2 2006.259.07:40:10.12#ibcon#enter sib2, iclass 27, count 2 2006.259.07:40:10.12#ibcon#flushed, iclass 27, count 2 2006.259.07:40:10.12#ibcon#about to write, iclass 27, count 2 2006.259.07:40:10.12#ibcon#wrote, iclass 27, count 2 2006.259.07:40:10.12#ibcon#about to read 3, iclass 27, count 2 2006.259.07:40:10.15#ibcon#read 3, iclass 27, count 2 2006.259.07:40:10.15#ibcon#about to read 4, iclass 27, count 2 2006.259.07:40:10.15#ibcon#read 4, iclass 27, count 2 2006.259.07:40:10.15#ibcon#about to read 5, iclass 27, count 2 2006.259.07:40:10.15#ibcon#read 5, iclass 27, count 2 2006.259.07:40:10.15#ibcon#about to read 6, iclass 27, count 2 2006.259.07:40:10.15#ibcon#read 6, iclass 27, count 2 2006.259.07:40:10.15#ibcon#end of sib2, iclass 27, count 2 2006.259.07:40:10.15#ibcon#*mode == 0, iclass 27, count 2 2006.259.07:40:10.15#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.259.07:40:10.15#ibcon#[25=AT03-08\r\n] 2006.259.07:40:10.15#ibcon#*before write, iclass 27, count 2 2006.259.07:40:10.15#ibcon#enter sib2, iclass 27, count 2 2006.259.07:40:10.15#ibcon#flushed, iclass 27, count 2 2006.259.07:40:10.15#ibcon#about to write, iclass 27, count 2 2006.259.07:40:10.15#ibcon#wrote, iclass 27, count 2 2006.259.07:40:10.15#ibcon#about to read 3, iclass 27, count 2 2006.259.07:40:10.18#ibcon#read 3, iclass 27, count 2 2006.259.07:40:10.18#ibcon#about to read 4, iclass 27, count 2 2006.259.07:40:10.18#ibcon#read 4, iclass 27, count 2 2006.259.07:40:10.18#ibcon#about to read 5, iclass 27, count 2 2006.259.07:40:10.18#ibcon#read 5, iclass 27, count 2 2006.259.07:40:10.18#ibcon#about to read 6, iclass 27, count 2 2006.259.07:40:10.18#ibcon#read 6, iclass 27, count 2 2006.259.07:40:10.18#ibcon#end of sib2, iclass 27, count 2 2006.259.07:40:10.18#ibcon#*after write, iclass 27, count 2 2006.259.07:40:10.18#ibcon#*before return 0, iclass 27, count 2 2006.259.07:40:10.18#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.259.07:40:10.18#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.259.07:40:10.18#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.259.07:40:10.18#ibcon#ireg 7 cls_cnt 0 2006.259.07:40:10.18#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.259.07:40:10.30#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.259.07:40:10.30#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.259.07:40:10.30#ibcon#enter wrdev, iclass 27, count 0 2006.259.07:40:10.30#ibcon#first serial, iclass 27, count 0 2006.259.07:40:10.30#ibcon#enter sib2, iclass 27, count 0 2006.259.07:40:10.30#ibcon#flushed, iclass 27, count 0 2006.259.07:40:10.30#ibcon#about to write, iclass 27, count 0 2006.259.07:40:10.30#ibcon#wrote, iclass 27, count 0 2006.259.07:40:10.30#ibcon#about to read 3, iclass 27, count 0 2006.259.07:40:10.32#ibcon#read 3, iclass 27, count 0 2006.259.07:40:10.32#ibcon#about to read 4, iclass 27, count 0 2006.259.07:40:10.32#ibcon#read 4, iclass 27, count 0 2006.259.07:40:10.32#ibcon#about to read 5, iclass 27, count 0 2006.259.07:40:10.32#ibcon#read 5, iclass 27, count 0 2006.259.07:40:10.32#ibcon#about to read 6, iclass 27, count 0 2006.259.07:40:10.32#ibcon#read 6, iclass 27, count 0 2006.259.07:40:10.32#ibcon#end of sib2, iclass 27, count 0 2006.259.07:40:10.32#ibcon#*mode == 0, iclass 27, count 0 2006.259.07:40:10.32#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.259.07:40:10.32#ibcon#[25=USB\r\n] 2006.259.07:40:10.32#ibcon#*before write, iclass 27, count 0 2006.259.07:40:10.32#ibcon#enter sib2, iclass 27, count 0 2006.259.07:40:10.32#ibcon#flushed, iclass 27, count 0 2006.259.07:40:10.32#ibcon#about to write, iclass 27, count 0 2006.259.07:40:10.32#ibcon#wrote, iclass 27, count 0 2006.259.07:40:10.32#ibcon#about to read 3, iclass 27, count 0 2006.259.07:40:10.35#ibcon#read 3, iclass 27, count 0 2006.259.07:40:10.35#ibcon#about to read 4, iclass 27, count 0 2006.259.07:40:10.35#ibcon#read 4, iclass 27, count 0 2006.259.07:40:10.35#ibcon#about to read 5, iclass 27, count 0 2006.259.07:40:10.35#ibcon#read 5, iclass 27, count 0 2006.259.07:40:10.35#ibcon#about to read 6, iclass 27, count 0 2006.259.07:40:10.35#ibcon#read 6, iclass 27, count 0 2006.259.07:40:10.35#ibcon#end of sib2, iclass 27, count 0 2006.259.07:40:10.35#ibcon#*after write, iclass 27, count 0 2006.259.07:40:10.35#ibcon#*before return 0, iclass 27, count 0 2006.259.07:40:10.35#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.259.07:40:10.35#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.259.07:40:10.35#ibcon#about to clear, iclass 27 cls_cnt 0 2006.259.07:40:10.35#ibcon#cleared, iclass 27 cls_cnt 0 2006.259.07:40:10.35$vc4f8/valo=4,832.99 2006.259.07:40:10.35#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.259.07:40:10.35#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.259.07:40:10.35#ibcon#ireg 17 cls_cnt 0 2006.259.07:40:10.35#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.259.07:40:10.35#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.259.07:40:10.35#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.259.07:40:10.35#ibcon#enter wrdev, iclass 29, count 0 2006.259.07:40:10.35#ibcon#first serial, iclass 29, count 0 2006.259.07:40:10.35#ibcon#enter sib2, iclass 29, count 0 2006.259.07:40:10.35#ibcon#flushed, iclass 29, count 0 2006.259.07:40:10.35#ibcon#about to write, iclass 29, count 0 2006.259.07:40:10.35#ibcon#wrote, iclass 29, count 0 2006.259.07:40:10.35#ibcon#about to read 3, iclass 29, count 0 2006.259.07:40:10.37#ibcon#read 3, iclass 29, count 0 2006.259.07:40:10.37#ibcon#about to read 4, iclass 29, count 0 2006.259.07:40:10.37#ibcon#read 4, iclass 29, count 0 2006.259.07:40:10.37#ibcon#about to read 5, iclass 29, count 0 2006.259.07:40:10.37#ibcon#read 5, iclass 29, count 0 2006.259.07:40:10.37#ibcon#about to read 6, iclass 29, count 0 2006.259.07:40:10.37#ibcon#read 6, iclass 29, count 0 2006.259.07:40:10.37#ibcon#end of sib2, iclass 29, count 0 2006.259.07:40:10.37#ibcon#*mode == 0, iclass 29, count 0 2006.259.07:40:10.37#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.259.07:40:10.37#ibcon#[26=FRQ=04,832.99\r\n] 2006.259.07:40:10.37#ibcon#*before write, iclass 29, count 0 2006.259.07:40:10.37#ibcon#enter sib2, iclass 29, count 0 2006.259.07:40:10.37#ibcon#flushed, iclass 29, count 0 2006.259.07:40:10.37#ibcon#about to write, iclass 29, count 0 2006.259.07:40:10.37#ibcon#wrote, iclass 29, count 0 2006.259.07:40:10.37#ibcon#about to read 3, iclass 29, count 0 2006.259.07:40:10.41#ibcon#read 3, iclass 29, count 0 2006.259.07:40:10.41#ibcon#about to read 4, iclass 29, count 0 2006.259.07:40:10.41#ibcon#read 4, iclass 29, count 0 2006.259.07:40:10.41#ibcon#about to read 5, iclass 29, count 0 2006.259.07:40:10.41#ibcon#read 5, iclass 29, count 0 2006.259.07:40:10.41#ibcon#about to read 6, iclass 29, count 0 2006.259.07:40:10.41#ibcon#read 6, iclass 29, count 0 2006.259.07:40:10.41#ibcon#end of sib2, iclass 29, count 0 2006.259.07:40:10.41#ibcon#*after write, iclass 29, count 0 2006.259.07:40:10.41#ibcon#*before return 0, iclass 29, count 0 2006.259.07:40:10.41#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.259.07:40:10.41#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.259.07:40:10.41#ibcon#about to clear, iclass 29 cls_cnt 0 2006.259.07:40:10.41#ibcon#cleared, iclass 29 cls_cnt 0 2006.259.07:40:10.41$vc4f8/va=4,7 2006.259.07:40:10.41#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.259.07:40:10.41#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.259.07:40:10.41#ibcon#ireg 11 cls_cnt 2 2006.259.07:40:10.41#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.259.07:40:10.47#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.259.07:40:10.47#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.259.07:40:10.47#ibcon#enter wrdev, iclass 31, count 2 2006.259.07:40:10.47#ibcon#first serial, iclass 31, count 2 2006.259.07:40:10.47#ibcon#enter sib2, iclass 31, count 2 2006.259.07:40:10.47#ibcon#flushed, iclass 31, count 2 2006.259.07:40:10.47#ibcon#about to write, iclass 31, count 2 2006.259.07:40:10.47#ibcon#wrote, iclass 31, count 2 2006.259.07:40:10.47#ibcon#about to read 3, iclass 31, count 2 2006.259.07:40:10.49#ibcon#read 3, iclass 31, count 2 2006.259.07:40:10.49#ibcon#about to read 4, iclass 31, count 2 2006.259.07:40:10.49#ibcon#read 4, iclass 31, count 2 2006.259.07:40:10.49#ibcon#about to read 5, iclass 31, count 2 2006.259.07:40:10.49#ibcon#read 5, iclass 31, count 2 2006.259.07:40:10.49#ibcon#about to read 6, iclass 31, count 2 2006.259.07:40:10.49#ibcon#read 6, iclass 31, count 2 2006.259.07:40:10.49#ibcon#end of sib2, iclass 31, count 2 2006.259.07:40:10.49#ibcon#*mode == 0, iclass 31, count 2 2006.259.07:40:10.49#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.259.07:40:10.49#ibcon#[25=AT04-07\r\n] 2006.259.07:40:10.49#ibcon#*before write, iclass 31, count 2 2006.259.07:40:10.49#ibcon#enter sib2, iclass 31, count 2 2006.259.07:40:10.49#ibcon#flushed, iclass 31, count 2 2006.259.07:40:10.49#ibcon#about to write, iclass 31, count 2 2006.259.07:40:10.49#ibcon#wrote, iclass 31, count 2 2006.259.07:40:10.49#ibcon#about to read 3, iclass 31, count 2 2006.259.07:40:10.52#ibcon#read 3, iclass 31, count 2 2006.259.07:40:10.52#ibcon#about to read 4, iclass 31, count 2 2006.259.07:40:10.52#ibcon#read 4, iclass 31, count 2 2006.259.07:40:10.52#ibcon#about to read 5, iclass 31, count 2 2006.259.07:40:10.52#ibcon#read 5, iclass 31, count 2 2006.259.07:40:10.52#ibcon#about to read 6, iclass 31, count 2 2006.259.07:40:10.52#ibcon#read 6, iclass 31, count 2 2006.259.07:40:10.52#ibcon#end of sib2, iclass 31, count 2 2006.259.07:40:10.52#ibcon#*after write, iclass 31, count 2 2006.259.07:40:10.52#ibcon#*before return 0, iclass 31, count 2 2006.259.07:40:10.52#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.259.07:40:10.52#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.259.07:40:10.52#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.259.07:40:10.52#ibcon#ireg 7 cls_cnt 0 2006.259.07:40:10.52#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.259.07:40:10.64#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.259.07:40:10.64#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.259.07:40:10.64#ibcon#enter wrdev, iclass 31, count 0 2006.259.07:40:10.64#ibcon#first serial, iclass 31, count 0 2006.259.07:40:10.64#ibcon#enter sib2, iclass 31, count 0 2006.259.07:40:10.64#ibcon#flushed, iclass 31, count 0 2006.259.07:40:10.64#ibcon#about to write, iclass 31, count 0 2006.259.07:40:10.64#ibcon#wrote, iclass 31, count 0 2006.259.07:40:10.64#ibcon#about to read 3, iclass 31, count 0 2006.259.07:40:10.66#ibcon#read 3, iclass 31, count 0 2006.259.07:40:10.66#ibcon#about to read 4, iclass 31, count 0 2006.259.07:40:10.66#ibcon#read 4, iclass 31, count 0 2006.259.07:40:10.66#ibcon#about to read 5, iclass 31, count 0 2006.259.07:40:10.66#ibcon#read 5, iclass 31, count 0 2006.259.07:40:10.66#ibcon#about to read 6, iclass 31, count 0 2006.259.07:40:10.66#ibcon#read 6, iclass 31, count 0 2006.259.07:40:10.66#ibcon#end of sib2, iclass 31, count 0 2006.259.07:40:10.66#ibcon#*mode == 0, iclass 31, count 0 2006.259.07:40:10.66#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.259.07:40:10.66#ibcon#[25=USB\r\n] 2006.259.07:40:10.66#ibcon#*before write, iclass 31, count 0 2006.259.07:40:10.66#ibcon#enter sib2, iclass 31, count 0 2006.259.07:40:10.66#ibcon#flushed, iclass 31, count 0 2006.259.07:40:10.66#ibcon#about to write, iclass 31, count 0 2006.259.07:40:10.66#ibcon#wrote, iclass 31, count 0 2006.259.07:40:10.66#ibcon#about to read 3, iclass 31, count 0 2006.259.07:40:10.69#ibcon#read 3, iclass 31, count 0 2006.259.07:40:10.69#ibcon#about to read 4, iclass 31, count 0 2006.259.07:40:10.69#ibcon#read 4, iclass 31, count 0 2006.259.07:40:10.69#ibcon#about to read 5, iclass 31, count 0 2006.259.07:40:10.69#ibcon#read 5, iclass 31, count 0 2006.259.07:40:10.69#ibcon#about to read 6, iclass 31, count 0 2006.259.07:40:10.69#ibcon#read 6, iclass 31, count 0 2006.259.07:40:10.69#ibcon#end of sib2, iclass 31, count 0 2006.259.07:40:10.69#ibcon#*after write, iclass 31, count 0 2006.259.07:40:10.69#ibcon#*before return 0, iclass 31, count 0 2006.259.07:40:10.69#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.259.07:40:10.69#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.259.07:40:10.69#ibcon#about to clear, iclass 31 cls_cnt 0 2006.259.07:40:10.69#ibcon#cleared, iclass 31 cls_cnt 0 2006.259.07:40:10.69$vc4f8/valo=5,652.99 2006.259.07:40:10.69#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.259.07:40:10.69#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.259.07:40:10.69#ibcon#ireg 17 cls_cnt 0 2006.259.07:40:10.69#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.259.07:40:10.69#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.259.07:40:10.69#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.259.07:40:10.69#ibcon#enter wrdev, iclass 33, count 0 2006.259.07:40:10.69#ibcon#first serial, iclass 33, count 0 2006.259.07:40:10.69#ibcon#enter sib2, iclass 33, count 0 2006.259.07:40:10.69#ibcon#flushed, iclass 33, count 0 2006.259.07:40:10.69#ibcon#about to write, iclass 33, count 0 2006.259.07:40:10.69#ibcon#wrote, iclass 33, count 0 2006.259.07:40:10.69#ibcon#about to read 3, iclass 33, count 0 2006.259.07:40:10.71#ibcon#read 3, iclass 33, count 0 2006.259.07:40:10.71#ibcon#about to read 4, iclass 33, count 0 2006.259.07:40:10.71#ibcon#read 4, iclass 33, count 0 2006.259.07:40:10.71#ibcon#about to read 5, iclass 33, count 0 2006.259.07:40:10.71#ibcon#read 5, iclass 33, count 0 2006.259.07:40:10.71#ibcon#about to read 6, iclass 33, count 0 2006.259.07:40:10.71#ibcon#read 6, iclass 33, count 0 2006.259.07:40:10.71#ibcon#end of sib2, iclass 33, count 0 2006.259.07:40:10.71#ibcon#*mode == 0, iclass 33, count 0 2006.259.07:40:10.71#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.259.07:40:10.71#ibcon#[26=FRQ=05,652.99\r\n] 2006.259.07:40:10.71#ibcon#*before write, iclass 33, count 0 2006.259.07:40:10.71#ibcon#enter sib2, iclass 33, count 0 2006.259.07:40:10.71#ibcon#flushed, iclass 33, count 0 2006.259.07:40:10.71#ibcon#about to write, iclass 33, count 0 2006.259.07:40:10.71#ibcon#wrote, iclass 33, count 0 2006.259.07:40:10.71#ibcon#about to read 3, iclass 33, count 0 2006.259.07:40:10.75#ibcon#read 3, iclass 33, count 0 2006.259.07:40:10.75#ibcon#about to read 4, iclass 33, count 0 2006.259.07:40:10.75#ibcon#read 4, iclass 33, count 0 2006.259.07:40:10.75#ibcon#about to read 5, iclass 33, count 0 2006.259.07:40:10.75#ibcon#read 5, iclass 33, count 0 2006.259.07:40:10.75#ibcon#about to read 6, iclass 33, count 0 2006.259.07:40:10.75#ibcon#read 6, iclass 33, count 0 2006.259.07:40:10.75#ibcon#end of sib2, iclass 33, count 0 2006.259.07:40:10.75#ibcon#*after write, iclass 33, count 0 2006.259.07:40:10.75#ibcon#*before return 0, iclass 33, count 0 2006.259.07:40:10.75#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.259.07:40:10.75#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.259.07:40:10.75#ibcon#about to clear, iclass 33 cls_cnt 0 2006.259.07:40:10.75#ibcon#cleared, iclass 33 cls_cnt 0 2006.259.07:40:10.75$vc4f8/va=5,7 2006.259.07:40:10.75#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.259.07:40:10.75#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.259.07:40:10.75#ibcon#ireg 11 cls_cnt 2 2006.259.07:40:10.75#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.259.07:40:10.81#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.259.07:40:10.81#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.259.07:40:10.81#ibcon#enter wrdev, iclass 35, count 2 2006.259.07:40:10.81#ibcon#first serial, iclass 35, count 2 2006.259.07:40:10.81#ibcon#enter sib2, iclass 35, count 2 2006.259.07:40:10.81#ibcon#flushed, iclass 35, count 2 2006.259.07:40:10.81#ibcon#about to write, iclass 35, count 2 2006.259.07:40:10.81#ibcon#wrote, iclass 35, count 2 2006.259.07:40:10.81#ibcon#about to read 3, iclass 35, count 2 2006.259.07:40:10.83#ibcon#read 3, iclass 35, count 2 2006.259.07:40:10.83#ibcon#about to read 4, iclass 35, count 2 2006.259.07:40:10.83#ibcon#read 4, iclass 35, count 2 2006.259.07:40:10.83#ibcon#about to read 5, iclass 35, count 2 2006.259.07:40:10.83#ibcon#read 5, iclass 35, count 2 2006.259.07:40:10.83#ibcon#about to read 6, iclass 35, count 2 2006.259.07:40:10.83#ibcon#read 6, iclass 35, count 2 2006.259.07:40:10.83#ibcon#end of sib2, iclass 35, count 2 2006.259.07:40:10.83#ibcon#*mode == 0, iclass 35, count 2 2006.259.07:40:10.83#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.259.07:40:10.83#ibcon#[25=AT05-07\r\n] 2006.259.07:40:10.83#ibcon#*before write, iclass 35, count 2 2006.259.07:40:10.83#ibcon#enter sib2, iclass 35, count 2 2006.259.07:40:10.83#ibcon#flushed, iclass 35, count 2 2006.259.07:40:10.83#ibcon#about to write, iclass 35, count 2 2006.259.07:40:10.83#ibcon#wrote, iclass 35, count 2 2006.259.07:40:10.83#ibcon#about to read 3, iclass 35, count 2 2006.259.07:40:10.86#ibcon#read 3, iclass 35, count 2 2006.259.07:40:10.86#ibcon#about to read 4, iclass 35, count 2 2006.259.07:40:10.86#ibcon#read 4, iclass 35, count 2 2006.259.07:40:10.86#ibcon#about to read 5, iclass 35, count 2 2006.259.07:40:10.86#ibcon#read 5, iclass 35, count 2 2006.259.07:40:10.86#ibcon#about to read 6, iclass 35, count 2 2006.259.07:40:10.86#ibcon#read 6, iclass 35, count 2 2006.259.07:40:10.86#ibcon#end of sib2, iclass 35, count 2 2006.259.07:40:10.86#ibcon#*after write, iclass 35, count 2 2006.259.07:40:10.86#ibcon#*before return 0, iclass 35, count 2 2006.259.07:40:10.86#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.259.07:40:10.86#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.259.07:40:10.86#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.259.07:40:10.86#ibcon#ireg 7 cls_cnt 0 2006.259.07:40:10.86#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.259.07:40:10.98#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.259.07:40:10.98#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.259.07:40:10.98#ibcon#enter wrdev, iclass 35, count 0 2006.259.07:40:10.98#ibcon#first serial, iclass 35, count 0 2006.259.07:40:10.98#ibcon#enter sib2, iclass 35, count 0 2006.259.07:40:10.98#ibcon#flushed, iclass 35, count 0 2006.259.07:40:10.98#ibcon#about to write, iclass 35, count 0 2006.259.07:40:10.98#ibcon#wrote, iclass 35, count 0 2006.259.07:40:10.98#ibcon#about to read 3, iclass 35, count 0 2006.259.07:40:11.00#ibcon#read 3, iclass 35, count 0 2006.259.07:40:11.00#ibcon#about to read 4, iclass 35, count 0 2006.259.07:40:11.00#ibcon#read 4, iclass 35, count 0 2006.259.07:40:11.00#ibcon#about to read 5, iclass 35, count 0 2006.259.07:40:11.00#ibcon#read 5, iclass 35, count 0 2006.259.07:40:11.00#ibcon#about to read 6, iclass 35, count 0 2006.259.07:40:11.00#ibcon#read 6, iclass 35, count 0 2006.259.07:40:11.00#ibcon#end of sib2, iclass 35, count 0 2006.259.07:40:11.00#ibcon#*mode == 0, iclass 35, count 0 2006.259.07:40:11.00#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.259.07:40:11.00#ibcon#[25=USB\r\n] 2006.259.07:40:11.00#ibcon#*before write, iclass 35, count 0 2006.259.07:40:11.00#ibcon#enter sib2, iclass 35, count 0 2006.259.07:40:11.00#ibcon#flushed, iclass 35, count 0 2006.259.07:40:11.00#ibcon#about to write, iclass 35, count 0 2006.259.07:40:11.00#ibcon#wrote, iclass 35, count 0 2006.259.07:40:11.00#ibcon#about to read 3, iclass 35, count 0 2006.259.07:40:11.03#ibcon#read 3, iclass 35, count 0 2006.259.07:40:11.03#ibcon#about to read 4, iclass 35, count 0 2006.259.07:40:11.03#ibcon#read 4, iclass 35, count 0 2006.259.07:40:11.03#ibcon#about to read 5, iclass 35, count 0 2006.259.07:40:11.03#ibcon#read 5, iclass 35, count 0 2006.259.07:40:11.03#ibcon#about to read 6, iclass 35, count 0 2006.259.07:40:11.03#ibcon#read 6, iclass 35, count 0 2006.259.07:40:11.03#ibcon#end of sib2, iclass 35, count 0 2006.259.07:40:11.03#ibcon#*after write, iclass 35, count 0 2006.259.07:40:11.03#ibcon#*before return 0, iclass 35, count 0 2006.259.07:40:11.03#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.259.07:40:11.03#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.259.07:40:11.03#ibcon#about to clear, iclass 35 cls_cnt 0 2006.259.07:40:11.03#ibcon#cleared, iclass 35 cls_cnt 0 2006.259.07:40:11.03$vc4f8/valo=6,772.99 2006.259.07:40:11.03#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.259.07:40:11.03#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.259.07:40:11.03#ibcon#ireg 17 cls_cnt 0 2006.259.07:40:11.03#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.259.07:40:11.03#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.259.07:40:11.03#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.259.07:40:11.03#ibcon#enter wrdev, iclass 37, count 0 2006.259.07:40:11.03#ibcon#first serial, iclass 37, count 0 2006.259.07:40:11.03#ibcon#enter sib2, iclass 37, count 0 2006.259.07:40:11.03#ibcon#flushed, iclass 37, count 0 2006.259.07:40:11.03#ibcon#about to write, iclass 37, count 0 2006.259.07:40:11.03#ibcon#wrote, iclass 37, count 0 2006.259.07:40:11.03#ibcon#about to read 3, iclass 37, count 0 2006.259.07:40:11.05#ibcon#read 3, iclass 37, count 0 2006.259.07:40:11.05#ibcon#about to read 4, iclass 37, count 0 2006.259.07:40:11.05#ibcon#read 4, iclass 37, count 0 2006.259.07:40:11.05#ibcon#about to read 5, iclass 37, count 0 2006.259.07:40:11.05#ibcon#read 5, iclass 37, count 0 2006.259.07:40:11.05#ibcon#about to read 6, iclass 37, count 0 2006.259.07:40:11.05#ibcon#read 6, iclass 37, count 0 2006.259.07:40:11.05#ibcon#end of sib2, iclass 37, count 0 2006.259.07:40:11.05#ibcon#*mode == 0, iclass 37, count 0 2006.259.07:40:11.05#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.259.07:40:11.05#ibcon#[26=FRQ=06,772.99\r\n] 2006.259.07:40:11.05#ibcon#*before write, iclass 37, count 0 2006.259.07:40:11.05#ibcon#enter sib2, iclass 37, count 0 2006.259.07:40:11.05#ibcon#flushed, iclass 37, count 0 2006.259.07:40:11.05#ibcon#about to write, iclass 37, count 0 2006.259.07:40:11.05#ibcon#wrote, iclass 37, count 0 2006.259.07:40:11.05#ibcon#about to read 3, iclass 37, count 0 2006.259.07:40:11.09#ibcon#read 3, iclass 37, count 0 2006.259.07:40:11.09#ibcon#about to read 4, iclass 37, count 0 2006.259.07:40:11.09#ibcon#read 4, iclass 37, count 0 2006.259.07:40:11.09#ibcon#about to read 5, iclass 37, count 0 2006.259.07:40:11.09#ibcon#read 5, iclass 37, count 0 2006.259.07:40:11.09#ibcon#about to read 6, iclass 37, count 0 2006.259.07:40:11.09#ibcon#read 6, iclass 37, count 0 2006.259.07:40:11.09#ibcon#end of sib2, iclass 37, count 0 2006.259.07:40:11.09#ibcon#*after write, iclass 37, count 0 2006.259.07:40:11.09#ibcon#*before return 0, iclass 37, count 0 2006.259.07:40:11.09#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.259.07:40:11.09#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.259.07:40:11.09#ibcon#about to clear, iclass 37 cls_cnt 0 2006.259.07:40:11.09#ibcon#cleared, iclass 37 cls_cnt 0 2006.259.07:40:11.09$vc4f8/va=6,6 2006.259.07:40:11.09#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.259.07:40:11.09#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.259.07:40:11.09#ibcon#ireg 11 cls_cnt 2 2006.259.07:40:11.09#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.259.07:40:11.15#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.259.07:40:11.15#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.259.07:40:11.15#ibcon#enter wrdev, iclass 39, count 2 2006.259.07:40:11.15#ibcon#first serial, iclass 39, count 2 2006.259.07:40:11.15#ibcon#enter sib2, iclass 39, count 2 2006.259.07:40:11.15#ibcon#flushed, iclass 39, count 2 2006.259.07:40:11.15#ibcon#about to write, iclass 39, count 2 2006.259.07:40:11.15#ibcon#wrote, iclass 39, count 2 2006.259.07:40:11.15#ibcon#about to read 3, iclass 39, count 2 2006.259.07:40:11.17#ibcon#read 3, iclass 39, count 2 2006.259.07:40:11.17#ibcon#about to read 4, iclass 39, count 2 2006.259.07:40:11.17#ibcon#read 4, iclass 39, count 2 2006.259.07:40:11.17#ibcon#about to read 5, iclass 39, count 2 2006.259.07:40:11.17#ibcon#read 5, iclass 39, count 2 2006.259.07:40:11.17#ibcon#about to read 6, iclass 39, count 2 2006.259.07:40:11.17#ibcon#read 6, iclass 39, count 2 2006.259.07:40:11.17#ibcon#end of sib2, iclass 39, count 2 2006.259.07:40:11.17#ibcon#*mode == 0, iclass 39, count 2 2006.259.07:40:11.17#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.259.07:40:11.17#ibcon#[25=AT06-06\r\n] 2006.259.07:40:11.17#ibcon#*before write, iclass 39, count 2 2006.259.07:40:11.17#ibcon#enter sib2, iclass 39, count 2 2006.259.07:40:11.17#ibcon#flushed, iclass 39, count 2 2006.259.07:40:11.17#ibcon#about to write, iclass 39, count 2 2006.259.07:40:11.17#ibcon#wrote, iclass 39, count 2 2006.259.07:40:11.17#ibcon#about to read 3, iclass 39, count 2 2006.259.07:40:11.20#ibcon#read 3, iclass 39, count 2 2006.259.07:40:11.20#ibcon#about to read 4, iclass 39, count 2 2006.259.07:40:11.20#ibcon#read 4, iclass 39, count 2 2006.259.07:40:11.20#ibcon#about to read 5, iclass 39, count 2 2006.259.07:40:11.20#ibcon#read 5, iclass 39, count 2 2006.259.07:40:11.20#ibcon#about to read 6, iclass 39, count 2 2006.259.07:40:11.20#ibcon#read 6, iclass 39, count 2 2006.259.07:40:11.20#ibcon#end of sib2, iclass 39, count 2 2006.259.07:40:11.20#ibcon#*after write, iclass 39, count 2 2006.259.07:40:11.20#ibcon#*before return 0, iclass 39, count 2 2006.259.07:40:11.20#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.259.07:40:11.20#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.259.07:40:11.20#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.259.07:40:11.20#ibcon#ireg 7 cls_cnt 0 2006.259.07:40:11.20#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.259.07:40:11.32#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.259.07:40:11.32#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.259.07:40:11.32#ibcon#enter wrdev, iclass 39, count 0 2006.259.07:40:11.32#ibcon#first serial, iclass 39, count 0 2006.259.07:40:11.32#ibcon#enter sib2, iclass 39, count 0 2006.259.07:40:11.32#ibcon#flushed, iclass 39, count 0 2006.259.07:40:11.32#ibcon#about to write, iclass 39, count 0 2006.259.07:40:11.32#ibcon#wrote, iclass 39, count 0 2006.259.07:40:11.32#ibcon#about to read 3, iclass 39, count 0 2006.259.07:40:11.34#ibcon#read 3, iclass 39, count 0 2006.259.07:40:11.34#ibcon#about to read 4, iclass 39, count 0 2006.259.07:40:11.34#ibcon#read 4, iclass 39, count 0 2006.259.07:40:11.34#ibcon#about to read 5, iclass 39, count 0 2006.259.07:40:11.34#ibcon#read 5, iclass 39, count 0 2006.259.07:40:11.34#ibcon#about to read 6, iclass 39, count 0 2006.259.07:40:11.34#ibcon#read 6, iclass 39, count 0 2006.259.07:40:11.34#ibcon#end of sib2, iclass 39, count 0 2006.259.07:40:11.34#ibcon#*mode == 0, iclass 39, count 0 2006.259.07:40:11.34#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.259.07:40:11.34#ibcon#[25=USB\r\n] 2006.259.07:40:11.34#ibcon#*before write, iclass 39, count 0 2006.259.07:40:11.34#ibcon#enter sib2, iclass 39, count 0 2006.259.07:40:11.34#ibcon#flushed, iclass 39, count 0 2006.259.07:40:11.34#ibcon#about to write, iclass 39, count 0 2006.259.07:40:11.34#ibcon#wrote, iclass 39, count 0 2006.259.07:40:11.34#ibcon#about to read 3, iclass 39, count 0 2006.259.07:40:11.37#ibcon#read 3, iclass 39, count 0 2006.259.07:40:11.37#ibcon#about to read 4, iclass 39, count 0 2006.259.07:40:11.37#ibcon#read 4, iclass 39, count 0 2006.259.07:40:11.37#ibcon#about to read 5, iclass 39, count 0 2006.259.07:40:11.37#ibcon#read 5, iclass 39, count 0 2006.259.07:40:11.37#ibcon#about to read 6, iclass 39, count 0 2006.259.07:40:11.37#ibcon#read 6, iclass 39, count 0 2006.259.07:40:11.37#ibcon#end of sib2, iclass 39, count 0 2006.259.07:40:11.37#ibcon#*after write, iclass 39, count 0 2006.259.07:40:11.37#ibcon#*before return 0, iclass 39, count 0 2006.259.07:40:11.37#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.259.07:40:11.37#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.259.07:40:11.37#ibcon#about to clear, iclass 39 cls_cnt 0 2006.259.07:40:11.37#ibcon#cleared, iclass 39 cls_cnt 0 2006.259.07:40:11.37$vc4f8/valo=7,832.99 2006.259.07:40:11.37#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.259.07:40:11.37#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.259.07:40:11.37#ibcon#ireg 17 cls_cnt 0 2006.259.07:40:11.37#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.259.07:40:11.37#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.259.07:40:11.37#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.259.07:40:11.37#ibcon#enter wrdev, iclass 3, count 0 2006.259.07:40:11.37#ibcon#first serial, iclass 3, count 0 2006.259.07:40:11.37#ibcon#enter sib2, iclass 3, count 0 2006.259.07:40:11.37#ibcon#flushed, iclass 3, count 0 2006.259.07:40:11.37#ibcon#about to write, iclass 3, count 0 2006.259.07:40:11.37#ibcon#wrote, iclass 3, count 0 2006.259.07:40:11.37#ibcon#about to read 3, iclass 3, count 0 2006.259.07:40:11.39#ibcon#read 3, iclass 3, count 0 2006.259.07:40:11.39#ibcon#about to read 4, iclass 3, count 0 2006.259.07:40:11.39#ibcon#read 4, iclass 3, count 0 2006.259.07:40:11.39#ibcon#about to read 5, iclass 3, count 0 2006.259.07:40:11.39#ibcon#read 5, iclass 3, count 0 2006.259.07:40:11.39#ibcon#about to read 6, iclass 3, count 0 2006.259.07:40:11.39#ibcon#read 6, iclass 3, count 0 2006.259.07:40:11.39#ibcon#end of sib2, iclass 3, count 0 2006.259.07:40:11.39#ibcon#*mode == 0, iclass 3, count 0 2006.259.07:40:11.39#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.259.07:40:11.39#ibcon#[26=FRQ=07,832.99\r\n] 2006.259.07:40:11.39#ibcon#*before write, iclass 3, count 0 2006.259.07:40:11.39#ibcon#enter sib2, iclass 3, count 0 2006.259.07:40:11.39#ibcon#flushed, iclass 3, count 0 2006.259.07:40:11.39#ibcon#about to write, iclass 3, count 0 2006.259.07:40:11.39#ibcon#wrote, iclass 3, count 0 2006.259.07:40:11.39#ibcon#about to read 3, iclass 3, count 0 2006.259.07:40:11.43#ibcon#read 3, iclass 3, count 0 2006.259.07:40:11.43#ibcon#about to read 4, iclass 3, count 0 2006.259.07:40:11.43#ibcon#read 4, iclass 3, count 0 2006.259.07:40:11.43#ibcon#about to read 5, iclass 3, count 0 2006.259.07:40:11.43#ibcon#read 5, iclass 3, count 0 2006.259.07:40:11.43#ibcon#about to read 6, iclass 3, count 0 2006.259.07:40:11.43#ibcon#read 6, iclass 3, count 0 2006.259.07:40:11.43#ibcon#end of sib2, iclass 3, count 0 2006.259.07:40:11.43#ibcon#*after write, iclass 3, count 0 2006.259.07:40:11.43#ibcon#*before return 0, iclass 3, count 0 2006.259.07:40:11.43#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.259.07:40:11.43#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.259.07:40:11.43#ibcon#about to clear, iclass 3 cls_cnt 0 2006.259.07:40:11.43#ibcon#cleared, iclass 3 cls_cnt 0 2006.259.07:40:11.43$vc4f8/va=7,6 2006.259.07:40:11.43#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.259.07:40:11.43#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.259.07:40:11.43#ibcon#ireg 11 cls_cnt 2 2006.259.07:40:11.43#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.259.07:40:11.49#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.259.07:40:11.49#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.259.07:40:11.49#ibcon#enter wrdev, iclass 5, count 2 2006.259.07:40:11.49#ibcon#first serial, iclass 5, count 2 2006.259.07:40:11.49#ibcon#enter sib2, iclass 5, count 2 2006.259.07:40:11.49#ibcon#flushed, iclass 5, count 2 2006.259.07:40:11.49#ibcon#about to write, iclass 5, count 2 2006.259.07:40:11.49#ibcon#wrote, iclass 5, count 2 2006.259.07:40:11.49#ibcon#about to read 3, iclass 5, count 2 2006.259.07:40:11.51#ibcon#read 3, iclass 5, count 2 2006.259.07:40:11.51#ibcon#about to read 4, iclass 5, count 2 2006.259.07:40:11.51#ibcon#read 4, iclass 5, count 2 2006.259.07:40:11.51#ibcon#about to read 5, iclass 5, count 2 2006.259.07:40:11.51#ibcon#read 5, iclass 5, count 2 2006.259.07:40:11.51#ibcon#about to read 6, iclass 5, count 2 2006.259.07:40:11.51#ibcon#read 6, iclass 5, count 2 2006.259.07:40:11.51#ibcon#end of sib2, iclass 5, count 2 2006.259.07:40:11.51#ibcon#*mode == 0, iclass 5, count 2 2006.259.07:40:11.51#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.259.07:40:11.51#ibcon#[25=AT07-06\r\n] 2006.259.07:40:11.51#ibcon#*before write, iclass 5, count 2 2006.259.07:40:11.51#ibcon#enter sib2, iclass 5, count 2 2006.259.07:40:11.51#ibcon#flushed, iclass 5, count 2 2006.259.07:40:11.51#ibcon#about to write, iclass 5, count 2 2006.259.07:40:11.51#ibcon#wrote, iclass 5, count 2 2006.259.07:40:11.51#ibcon#about to read 3, iclass 5, count 2 2006.259.07:40:11.54#ibcon#read 3, iclass 5, count 2 2006.259.07:40:11.54#ibcon#about to read 4, iclass 5, count 2 2006.259.07:40:11.54#ibcon#read 4, iclass 5, count 2 2006.259.07:40:11.54#ibcon#about to read 5, iclass 5, count 2 2006.259.07:40:11.54#ibcon#read 5, iclass 5, count 2 2006.259.07:40:11.54#ibcon#about to read 6, iclass 5, count 2 2006.259.07:40:11.54#ibcon#read 6, iclass 5, count 2 2006.259.07:40:11.54#ibcon#end of sib2, iclass 5, count 2 2006.259.07:40:11.54#ibcon#*after write, iclass 5, count 2 2006.259.07:40:11.54#ibcon#*before return 0, iclass 5, count 2 2006.259.07:40:11.54#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.259.07:40:11.54#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.259.07:40:11.54#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.259.07:40:11.54#ibcon#ireg 7 cls_cnt 0 2006.259.07:40:11.54#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.259.07:40:11.66#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.259.07:40:11.66#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.259.07:40:11.66#ibcon#enter wrdev, iclass 5, count 0 2006.259.07:40:11.66#ibcon#first serial, iclass 5, count 0 2006.259.07:40:11.66#ibcon#enter sib2, iclass 5, count 0 2006.259.07:40:11.66#ibcon#flushed, iclass 5, count 0 2006.259.07:40:11.66#ibcon#about to write, iclass 5, count 0 2006.259.07:40:11.66#ibcon#wrote, iclass 5, count 0 2006.259.07:40:11.66#ibcon#about to read 3, iclass 5, count 0 2006.259.07:40:11.68#ibcon#read 3, iclass 5, count 0 2006.259.07:40:11.68#ibcon#about to read 4, iclass 5, count 0 2006.259.07:40:11.68#ibcon#read 4, iclass 5, count 0 2006.259.07:40:11.68#ibcon#about to read 5, iclass 5, count 0 2006.259.07:40:11.68#ibcon#read 5, iclass 5, count 0 2006.259.07:40:11.68#ibcon#about to read 6, iclass 5, count 0 2006.259.07:40:11.68#ibcon#read 6, iclass 5, count 0 2006.259.07:40:11.68#ibcon#end of sib2, iclass 5, count 0 2006.259.07:40:11.68#ibcon#*mode == 0, iclass 5, count 0 2006.259.07:40:11.68#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.259.07:40:11.68#ibcon#[25=USB\r\n] 2006.259.07:40:11.68#ibcon#*before write, iclass 5, count 0 2006.259.07:40:11.68#ibcon#enter sib2, iclass 5, count 0 2006.259.07:40:11.68#ibcon#flushed, iclass 5, count 0 2006.259.07:40:11.68#ibcon#about to write, iclass 5, count 0 2006.259.07:40:11.68#ibcon#wrote, iclass 5, count 0 2006.259.07:40:11.68#ibcon#about to read 3, iclass 5, count 0 2006.259.07:40:11.71#ibcon#read 3, iclass 5, count 0 2006.259.07:40:11.71#ibcon#about to read 4, iclass 5, count 0 2006.259.07:40:11.71#ibcon#read 4, iclass 5, count 0 2006.259.07:40:11.71#ibcon#about to read 5, iclass 5, count 0 2006.259.07:40:11.71#ibcon#read 5, iclass 5, count 0 2006.259.07:40:11.71#ibcon#about to read 6, iclass 5, count 0 2006.259.07:40:11.71#ibcon#read 6, iclass 5, count 0 2006.259.07:40:11.71#ibcon#end of sib2, iclass 5, count 0 2006.259.07:40:11.71#ibcon#*after write, iclass 5, count 0 2006.259.07:40:11.71#ibcon#*before return 0, iclass 5, count 0 2006.259.07:40:11.71#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.259.07:40:11.71#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.259.07:40:11.71#ibcon#about to clear, iclass 5 cls_cnt 0 2006.259.07:40:11.71#ibcon#cleared, iclass 5 cls_cnt 0 2006.259.07:40:11.71$vc4f8/valo=8,852.99 2006.259.07:40:11.71#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.259.07:40:11.71#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.259.07:40:11.71#ibcon#ireg 17 cls_cnt 0 2006.259.07:40:11.71#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.259.07:40:11.71#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.259.07:40:11.71#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.259.07:40:11.71#ibcon#enter wrdev, iclass 7, count 0 2006.259.07:40:11.71#ibcon#first serial, iclass 7, count 0 2006.259.07:40:11.71#ibcon#enter sib2, iclass 7, count 0 2006.259.07:40:11.71#ibcon#flushed, iclass 7, count 0 2006.259.07:40:11.71#ibcon#about to write, iclass 7, count 0 2006.259.07:40:11.71#ibcon#wrote, iclass 7, count 0 2006.259.07:40:11.71#ibcon#about to read 3, iclass 7, count 0 2006.259.07:40:11.73#ibcon#read 3, iclass 7, count 0 2006.259.07:40:11.73#ibcon#about to read 4, iclass 7, count 0 2006.259.07:40:11.73#ibcon#read 4, iclass 7, count 0 2006.259.07:40:11.73#ibcon#about to read 5, iclass 7, count 0 2006.259.07:40:11.73#ibcon#read 5, iclass 7, count 0 2006.259.07:40:11.73#ibcon#about to read 6, iclass 7, count 0 2006.259.07:40:11.73#ibcon#read 6, iclass 7, count 0 2006.259.07:40:11.73#ibcon#end of sib2, iclass 7, count 0 2006.259.07:40:11.73#ibcon#*mode == 0, iclass 7, count 0 2006.259.07:40:11.73#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.259.07:40:11.73#ibcon#[26=FRQ=08,852.99\r\n] 2006.259.07:40:11.73#ibcon#*before write, iclass 7, count 0 2006.259.07:40:11.73#ibcon#enter sib2, iclass 7, count 0 2006.259.07:40:11.73#ibcon#flushed, iclass 7, count 0 2006.259.07:40:11.73#ibcon#about to write, iclass 7, count 0 2006.259.07:40:11.73#ibcon#wrote, iclass 7, count 0 2006.259.07:40:11.73#ibcon#about to read 3, iclass 7, count 0 2006.259.07:40:11.77#ibcon#read 3, iclass 7, count 0 2006.259.07:40:11.77#ibcon#about to read 4, iclass 7, count 0 2006.259.07:40:11.77#ibcon#read 4, iclass 7, count 0 2006.259.07:40:11.77#ibcon#about to read 5, iclass 7, count 0 2006.259.07:40:11.77#ibcon#read 5, iclass 7, count 0 2006.259.07:40:11.77#ibcon#about to read 6, iclass 7, count 0 2006.259.07:40:11.77#ibcon#read 6, iclass 7, count 0 2006.259.07:40:11.77#ibcon#end of sib2, iclass 7, count 0 2006.259.07:40:11.77#ibcon#*after write, iclass 7, count 0 2006.259.07:40:11.77#ibcon#*before return 0, iclass 7, count 0 2006.259.07:40:11.77#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.259.07:40:11.77#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.259.07:40:11.77#ibcon#about to clear, iclass 7 cls_cnt 0 2006.259.07:40:11.77#ibcon#cleared, iclass 7 cls_cnt 0 2006.259.07:40:11.77$vc4f8/va=8,6 2006.259.07:40:11.77#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.259.07:40:11.77#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.259.07:40:11.77#ibcon#ireg 11 cls_cnt 2 2006.259.07:40:11.77#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.259.07:40:11.83#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.259.07:40:11.83#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.259.07:40:11.83#ibcon#enter wrdev, iclass 11, count 2 2006.259.07:40:11.83#ibcon#first serial, iclass 11, count 2 2006.259.07:40:11.83#ibcon#enter sib2, iclass 11, count 2 2006.259.07:40:11.83#ibcon#flushed, iclass 11, count 2 2006.259.07:40:11.83#ibcon#about to write, iclass 11, count 2 2006.259.07:40:11.83#ibcon#wrote, iclass 11, count 2 2006.259.07:40:11.83#ibcon#about to read 3, iclass 11, count 2 2006.259.07:40:11.85#ibcon#read 3, iclass 11, count 2 2006.259.07:40:11.85#ibcon#about to read 4, iclass 11, count 2 2006.259.07:40:11.85#ibcon#read 4, iclass 11, count 2 2006.259.07:40:11.85#ibcon#about to read 5, iclass 11, count 2 2006.259.07:40:11.85#ibcon#read 5, iclass 11, count 2 2006.259.07:40:11.85#ibcon#about to read 6, iclass 11, count 2 2006.259.07:40:11.85#ibcon#read 6, iclass 11, count 2 2006.259.07:40:11.85#ibcon#end of sib2, iclass 11, count 2 2006.259.07:40:11.85#ibcon#*mode == 0, iclass 11, count 2 2006.259.07:40:11.85#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.259.07:40:11.85#ibcon#[25=AT08-06\r\n] 2006.259.07:40:11.85#ibcon#*before write, iclass 11, count 2 2006.259.07:40:11.85#ibcon#enter sib2, iclass 11, count 2 2006.259.07:40:11.85#ibcon#flushed, iclass 11, count 2 2006.259.07:40:11.85#ibcon#about to write, iclass 11, count 2 2006.259.07:40:11.85#ibcon#wrote, iclass 11, count 2 2006.259.07:40:11.85#ibcon#about to read 3, iclass 11, count 2 2006.259.07:40:11.88#ibcon#read 3, iclass 11, count 2 2006.259.07:40:11.88#ibcon#about to read 4, iclass 11, count 2 2006.259.07:40:11.88#ibcon#read 4, iclass 11, count 2 2006.259.07:40:11.88#ibcon#about to read 5, iclass 11, count 2 2006.259.07:40:11.88#ibcon#read 5, iclass 11, count 2 2006.259.07:40:11.88#ibcon#about to read 6, iclass 11, count 2 2006.259.07:40:11.88#ibcon#read 6, iclass 11, count 2 2006.259.07:40:11.88#ibcon#end of sib2, iclass 11, count 2 2006.259.07:40:11.88#ibcon#*after write, iclass 11, count 2 2006.259.07:40:11.88#ibcon#*before return 0, iclass 11, count 2 2006.259.07:40:11.88#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.259.07:40:11.88#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.259.07:40:11.88#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.259.07:40:11.88#ibcon#ireg 7 cls_cnt 0 2006.259.07:40:11.88#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.259.07:40:12.00#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.259.07:40:12.00#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.259.07:40:12.00#ibcon#enter wrdev, iclass 11, count 0 2006.259.07:40:12.00#ibcon#first serial, iclass 11, count 0 2006.259.07:40:12.00#ibcon#enter sib2, iclass 11, count 0 2006.259.07:40:12.00#ibcon#flushed, iclass 11, count 0 2006.259.07:40:12.00#ibcon#about to write, iclass 11, count 0 2006.259.07:40:12.00#ibcon#wrote, iclass 11, count 0 2006.259.07:40:12.00#ibcon#about to read 3, iclass 11, count 0 2006.259.07:40:12.02#ibcon#read 3, iclass 11, count 0 2006.259.07:40:12.02#ibcon#about to read 4, iclass 11, count 0 2006.259.07:40:12.02#ibcon#read 4, iclass 11, count 0 2006.259.07:40:12.02#ibcon#about to read 5, iclass 11, count 0 2006.259.07:40:12.02#ibcon#read 5, iclass 11, count 0 2006.259.07:40:12.02#ibcon#about to read 6, iclass 11, count 0 2006.259.07:40:12.02#ibcon#read 6, iclass 11, count 0 2006.259.07:40:12.02#ibcon#end of sib2, iclass 11, count 0 2006.259.07:40:12.02#ibcon#*mode == 0, iclass 11, count 0 2006.259.07:40:12.02#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.259.07:40:12.02#ibcon#[25=USB\r\n] 2006.259.07:40:12.02#ibcon#*before write, iclass 11, count 0 2006.259.07:40:12.02#ibcon#enter sib2, iclass 11, count 0 2006.259.07:40:12.02#ibcon#flushed, iclass 11, count 0 2006.259.07:40:12.02#ibcon#about to write, iclass 11, count 0 2006.259.07:40:12.02#ibcon#wrote, iclass 11, count 0 2006.259.07:40:12.02#ibcon#about to read 3, iclass 11, count 0 2006.259.07:40:12.05#ibcon#read 3, iclass 11, count 0 2006.259.07:40:12.05#ibcon#about to read 4, iclass 11, count 0 2006.259.07:40:12.05#ibcon#read 4, iclass 11, count 0 2006.259.07:40:12.05#ibcon#about to read 5, iclass 11, count 0 2006.259.07:40:12.05#ibcon#read 5, iclass 11, count 0 2006.259.07:40:12.05#ibcon#about to read 6, iclass 11, count 0 2006.259.07:40:12.05#ibcon#read 6, iclass 11, count 0 2006.259.07:40:12.05#ibcon#end of sib2, iclass 11, count 0 2006.259.07:40:12.05#ibcon#*after write, iclass 11, count 0 2006.259.07:40:12.05#ibcon#*before return 0, iclass 11, count 0 2006.259.07:40:12.05#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.259.07:40:12.05#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.259.07:40:12.05#ibcon#about to clear, iclass 11 cls_cnt 0 2006.259.07:40:12.05#ibcon#cleared, iclass 11 cls_cnt 0 2006.259.07:40:12.05$vc4f8/vblo=1,632.99 2006.259.07:40:12.05#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.259.07:40:12.05#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.259.07:40:12.05#ibcon#ireg 17 cls_cnt 0 2006.259.07:40:12.05#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.259.07:40:12.05#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.259.07:40:12.05#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.259.07:40:12.05#ibcon#enter wrdev, iclass 13, count 0 2006.259.07:40:12.05#ibcon#first serial, iclass 13, count 0 2006.259.07:40:12.05#ibcon#enter sib2, iclass 13, count 0 2006.259.07:40:12.05#ibcon#flushed, iclass 13, count 0 2006.259.07:40:12.05#ibcon#about to write, iclass 13, count 0 2006.259.07:40:12.05#ibcon#wrote, iclass 13, count 0 2006.259.07:40:12.05#ibcon#about to read 3, iclass 13, count 0 2006.259.07:40:12.07#ibcon#read 3, iclass 13, count 0 2006.259.07:40:12.07#ibcon#about to read 4, iclass 13, count 0 2006.259.07:40:12.07#ibcon#read 4, iclass 13, count 0 2006.259.07:40:12.07#ibcon#about to read 5, iclass 13, count 0 2006.259.07:40:12.07#ibcon#read 5, iclass 13, count 0 2006.259.07:40:12.07#ibcon#about to read 6, iclass 13, count 0 2006.259.07:40:12.07#ibcon#read 6, iclass 13, count 0 2006.259.07:40:12.07#ibcon#end of sib2, iclass 13, count 0 2006.259.07:40:12.07#ibcon#*mode == 0, iclass 13, count 0 2006.259.07:40:12.07#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.259.07:40:12.07#ibcon#[28=FRQ=01,632.99\r\n] 2006.259.07:40:12.07#ibcon#*before write, iclass 13, count 0 2006.259.07:40:12.07#ibcon#enter sib2, iclass 13, count 0 2006.259.07:40:12.07#ibcon#flushed, iclass 13, count 0 2006.259.07:40:12.07#ibcon#about to write, iclass 13, count 0 2006.259.07:40:12.07#ibcon#wrote, iclass 13, count 0 2006.259.07:40:12.07#ibcon#about to read 3, iclass 13, count 0 2006.259.07:40:12.11#ibcon#read 3, iclass 13, count 0 2006.259.07:40:12.11#ibcon#about to read 4, iclass 13, count 0 2006.259.07:40:12.11#ibcon#read 4, iclass 13, count 0 2006.259.07:40:12.11#ibcon#about to read 5, iclass 13, count 0 2006.259.07:40:12.11#ibcon#read 5, iclass 13, count 0 2006.259.07:40:12.11#ibcon#about to read 6, iclass 13, count 0 2006.259.07:40:12.11#ibcon#read 6, iclass 13, count 0 2006.259.07:40:12.11#ibcon#end of sib2, iclass 13, count 0 2006.259.07:40:12.11#ibcon#*after write, iclass 13, count 0 2006.259.07:40:12.11#ibcon#*before return 0, iclass 13, count 0 2006.259.07:40:12.11#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.259.07:40:12.11#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.259.07:40:12.11#ibcon#about to clear, iclass 13 cls_cnt 0 2006.259.07:40:12.11#ibcon#cleared, iclass 13 cls_cnt 0 2006.259.07:40:12.11$vc4f8/vb=1,4 2006.259.07:40:12.11#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.259.07:40:12.11#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.259.07:40:12.11#ibcon#ireg 11 cls_cnt 2 2006.259.07:40:12.11#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.259.07:40:12.11#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.259.07:40:12.11#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.259.07:40:12.11#ibcon#enter wrdev, iclass 15, count 2 2006.259.07:40:12.11#ibcon#first serial, iclass 15, count 2 2006.259.07:40:12.11#ibcon#enter sib2, iclass 15, count 2 2006.259.07:40:12.11#ibcon#flushed, iclass 15, count 2 2006.259.07:40:12.11#ibcon#about to write, iclass 15, count 2 2006.259.07:40:12.11#ibcon#wrote, iclass 15, count 2 2006.259.07:40:12.11#ibcon#about to read 3, iclass 15, count 2 2006.259.07:40:12.13#ibcon#read 3, iclass 15, count 2 2006.259.07:40:12.13#ibcon#about to read 4, iclass 15, count 2 2006.259.07:40:12.13#ibcon#read 4, iclass 15, count 2 2006.259.07:40:12.13#ibcon#about to read 5, iclass 15, count 2 2006.259.07:40:12.13#ibcon#read 5, iclass 15, count 2 2006.259.07:40:12.13#ibcon#about to read 6, iclass 15, count 2 2006.259.07:40:12.13#ibcon#read 6, iclass 15, count 2 2006.259.07:40:12.13#ibcon#end of sib2, iclass 15, count 2 2006.259.07:40:12.13#ibcon#*mode == 0, iclass 15, count 2 2006.259.07:40:12.13#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.259.07:40:12.13#ibcon#[27=AT01-04\r\n] 2006.259.07:40:12.13#ibcon#*before write, iclass 15, count 2 2006.259.07:40:12.13#ibcon#enter sib2, iclass 15, count 2 2006.259.07:40:12.13#ibcon#flushed, iclass 15, count 2 2006.259.07:40:12.13#ibcon#about to write, iclass 15, count 2 2006.259.07:40:12.13#ibcon#wrote, iclass 15, count 2 2006.259.07:40:12.13#ibcon#about to read 3, iclass 15, count 2 2006.259.07:40:12.16#ibcon#read 3, iclass 15, count 2 2006.259.07:40:12.16#ibcon#about to read 4, iclass 15, count 2 2006.259.07:40:12.16#ibcon#read 4, iclass 15, count 2 2006.259.07:40:12.16#ibcon#about to read 5, iclass 15, count 2 2006.259.07:40:12.16#ibcon#read 5, iclass 15, count 2 2006.259.07:40:12.16#ibcon#about to read 6, iclass 15, count 2 2006.259.07:40:12.16#ibcon#read 6, iclass 15, count 2 2006.259.07:40:12.16#ibcon#end of sib2, iclass 15, count 2 2006.259.07:40:12.16#ibcon#*after write, iclass 15, count 2 2006.259.07:40:12.16#ibcon#*before return 0, iclass 15, count 2 2006.259.07:40:12.16#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.259.07:40:12.16#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.259.07:40:12.16#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.259.07:40:12.16#ibcon#ireg 7 cls_cnt 0 2006.259.07:40:12.16#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.259.07:40:12.28#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.259.07:40:12.28#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.259.07:40:12.28#ibcon#enter wrdev, iclass 15, count 0 2006.259.07:40:12.28#ibcon#first serial, iclass 15, count 0 2006.259.07:40:12.28#ibcon#enter sib2, iclass 15, count 0 2006.259.07:40:12.28#ibcon#flushed, iclass 15, count 0 2006.259.07:40:12.28#ibcon#about to write, iclass 15, count 0 2006.259.07:40:12.28#ibcon#wrote, iclass 15, count 0 2006.259.07:40:12.28#ibcon#about to read 3, iclass 15, count 0 2006.259.07:40:12.30#ibcon#read 3, iclass 15, count 0 2006.259.07:40:12.30#ibcon#about to read 4, iclass 15, count 0 2006.259.07:40:12.30#ibcon#read 4, iclass 15, count 0 2006.259.07:40:12.30#ibcon#about to read 5, iclass 15, count 0 2006.259.07:40:12.30#ibcon#read 5, iclass 15, count 0 2006.259.07:40:12.30#ibcon#about to read 6, iclass 15, count 0 2006.259.07:40:12.30#ibcon#read 6, iclass 15, count 0 2006.259.07:40:12.30#ibcon#end of sib2, iclass 15, count 0 2006.259.07:40:12.30#ibcon#*mode == 0, iclass 15, count 0 2006.259.07:40:12.30#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.259.07:40:12.30#ibcon#[27=USB\r\n] 2006.259.07:40:12.30#ibcon#*before write, iclass 15, count 0 2006.259.07:40:12.30#ibcon#enter sib2, iclass 15, count 0 2006.259.07:40:12.30#ibcon#flushed, iclass 15, count 0 2006.259.07:40:12.30#ibcon#about to write, iclass 15, count 0 2006.259.07:40:12.30#ibcon#wrote, iclass 15, count 0 2006.259.07:40:12.30#ibcon#about to read 3, iclass 15, count 0 2006.259.07:40:12.33#ibcon#read 3, iclass 15, count 0 2006.259.07:40:12.33#ibcon#about to read 4, iclass 15, count 0 2006.259.07:40:12.33#ibcon#read 4, iclass 15, count 0 2006.259.07:40:12.33#ibcon#about to read 5, iclass 15, count 0 2006.259.07:40:12.33#ibcon#read 5, iclass 15, count 0 2006.259.07:40:12.33#ibcon#about to read 6, iclass 15, count 0 2006.259.07:40:12.33#ibcon#read 6, iclass 15, count 0 2006.259.07:40:12.33#ibcon#end of sib2, iclass 15, count 0 2006.259.07:40:12.33#ibcon#*after write, iclass 15, count 0 2006.259.07:40:12.33#ibcon#*before return 0, iclass 15, count 0 2006.259.07:40:12.33#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.259.07:40:12.33#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.259.07:40:12.33#ibcon#about to clear, iclass 15 cls_cnt 0 2006.259.07:40:12.33#ibcon#cleared, iclass 15 cls_cnt 0 2006.259.07:40:12.33$vc4f8/vblo=2,640.99 2006.259.07:40:12.33#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.259.07:40:12.33#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.259.07:40:12.33#ibcon#ireg 17 cls_cnt 0 2006.259.07:40:12.33#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.259.07:40:12.33#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.259.07:40:12.33#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.259.07:40:12.33#ibcon#enter wrdev, iclass 17, count 0 2006.259.07:40:12.33#ibcon#first serial, iclass 17, count 0 2006.259.07:40:12.33#ibcon#enter sib2, iclass 17, count 0 2006.259.07:40:12.33#ibcon#flushed, iclass 17, count 0 2006.259.07:40:12.33#ibcon#about to write, iclass 17, count 0 2006.259.07:40:12.33#ibcon#wrote, iclass 17, count 0 2006.259.07:40:12.33#ibcon#about to read 3, iclass 17, count 0 2006.259.07:40:12.35#ibcon#read 3, iclass 17, count 0 2006.259.07:40:12.35#ibcon#about to read 4, iclass 17, count 0 2006.259.07:40:12.35#ibcon#read 4, iclass 17, count 0 2006.259.07:40:12.35#ibcon#about to read 5, iclass 17, count 0 2006.259.07:40:12.35#ibcon#read 5, iclass 17, count 0 2006.259.07:40:12.35#ibcon#about to read 6, iclass 17, count 0 2006.259.07:40:12.35#ibcon#read 6, iclass 17, count 0 2006.259.07:40:12.35#ibcon#end of sib2, iclass 17, count 0 2006.259.07:40:12.35#ibcon#*mode == 0, iclass 17, count 0 2006.259.07:40:12.35#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.259.07:40:12.35#ibcon#[28=FRQ=02,640.99\r\n] 2006.259.07:40:12.35#ibcon#*before write, iclass 17, count 0 2006.259.07:40:12.35#ibcon#enter sib2, iclass 17, count 0 2006.259.07:40:12.35#ibcon#flushed, iclass 17, count 0 2006.259.07:40:12.35#ibcon#about to write, iclass 17, count 0 2006.259.07:40:12.35#ibcon#wrote, iclass 17, count 0 2006.259.07:40:12.35#ibcon#about to read 3, iclass 17, count 0 2006.259.07:40:12.39#ibcon#read 3, iclass 17, count 0 2006.259.07:40:12.39#ibcon#about to read 4, iclass 17, count 0 2006.259.07:40:12.39#ibcon#read 4, iclass 17, count 0 2006.259.07:40:12.39#ibcon#about to read 5, iclass 17, count 0 2006.259.07:40:12.39#ibcon#read 5, iclass 17, count 0 2006.259.07:40:12.39#ibcon#about to read 6, iclass 17, count 0 2006.259.07:40:12.39#ibcon#read 6, iclass 17, count 0 2006.259.07:40:12.39#ibcon#end of sib2, iclass 17, count 0 2006.259.07:40:12.39#ibcon#*after write, iclass 17, count 0 2006.259.07:40:12.39#ibcon#*before return 0, iclass 17, count 0 2006.259.07:40:12.39#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.259.07:40:12.39#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.259.07:40:12.39#ibcon#about to clear, iclass 17 cls_cnt 0 2006.259.07:40:12.39#ibcon#cleared, iclass 17 cls_cnt 0 2006.259.07:40:12.39$vc4f8/vb=2,5 2006.259.07:40:12.39#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.259.07:40:12.39#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.259.07:40:12.39#ibcon#ireg 11 cls_cnt 2 2006.259.07:40:12.39#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.259.07:40:12.45#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.259.07:40:12.45#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.259.07:40:12.45#ibcon#enter wrdev, iclass 19, count 2 2006.259.07:40:12.45#ibcon#first serial, iclass 19, count 2 2006.259.07:40:12.45#ibcon#enter sib2, iclass 19, count 2 2006.259.07:40:12.45#ibcon#flushed, iclass 19, count 2 2006.259.07:40:12.45#ibcon#about to write, iclass 19, count 2 2006.259.07:40:12.45#ibcon#wrote, iclass 19, count 2 2006.259.07:40:12.45#ibcon#about to read 3, iclass 19, count 2 2006.259.07:40:12.47#ibcon#read 3, iclass 19, count 2 2006.259.07:40:12.47#ibcon#about to read 4, iclass 19, count 2 2006.259.07:40:12.47#ibcon#read 4, iclass 19, count 2 2006.259.07:40:12.47#ibcon#about to read 5, iclass 19, count 2 2006.259.07:40:12.47#ibcon#read 5, iclass 19, count 2 2006.259.07:40:12.47#ibcon#about to read 6, iclass 19, count 2 2006.259.07:40:12.47#ibcon#read 6, iclass 19, count 2 2006.259.07:40:12.47#ibcon#end of sib2, iclass 19, count 2 2006.259.07:40:12.47#ibcon#*mode == 0, iclass 19, count 2 2006.259.07:40:12.47#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.259.07:40:12.47#ibcon#[27=AT02-05\r\n] 2006.259.07:40:12.47#ibcon#*before write, iclass 19, count 2 2006.259.07:40:12.47#ibcon#enter sib2, iclass 19, count 2 2006.259.07:40:12.47#ibcon#flushed, iclass 19, count 2 2006.259.07:40:12.47#ibcon#about to write, iclass 19, count 2 2006.259.07:40:12.47#ibcon#wrote, iclass 19, count 2 2006.259.07:40:12.47#ibcon#about to read 3, iclass 19, count 2 2006.259.07:40:12.50#ibcon#read 3, iclass 19, count 2 2006.259.07:40:12.50#ibcon#about to read 4, iclass 19, count 2 2006.259.07:40:12.50#ibcon#read 4, iclass 19, count 2 2006.259.07:40:12.50#ibcon#about to read 5, iclass 19, count 2 2006.259.07:40:12.50#ibcon#read 5, iclass 19, count 2 2006.259.07:40:12.50#ibcon#about to read 6, iclass 19, count 2 2006.259.07:40:12.50#ibcon#read 6, iclass 19, count 2 2006.259.07:40:12.50#ibcon#end of sib2, iclass 19, count 2 2006.259.07:40:12.50#ibcon#*after write, iclass 19, count 2 2006.259.07:40:12.50#ibcon#*before return 0, iclass 19, count 2 2006.259.07:40:12.50#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.259.07:40:12.50#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.259.07:40:12.50#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.259.07:40:12.50#ibcon#ireg 7 cls_cnt 0 2006.259.07:40:12.50#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.259.07:40:12.62#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.259.07:40:12.62#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.259.07:40:12.62#ibcon#enter wrdev, iclass 19, count 0 2006.259.07:40:12.62#ibcon#first serial, iclass 19, count 0 2006.259.07:40:12.62#ibcon#enter sib2, iclass 19, count 0 2006.259.07:40:12.62#ibcon#flushed, iclass 19, count 0 2006.259.07:40:12.62#ibcon#about to write, iclass 19, count 0 2006.259.07:40:12.62#ibcon#wrote, iclass 19, count 0 2006.259.07:40:12.62#ibcon#about to read 3, iclass 19, count 0 2006.259.07:40:12.64#ibcon#read 3, iclass 19, count 0 2006.259.07:40:12.64#ibcon#about to read 4, iclass 19, count 0 2006.259.07:40:12.64#ibcon#read 4, iclass 19, count 0 2006.259.07:40:12.64#ibcon#about to read 5, iclass 19, count 0 2006.259.07:40:12.64#ibcon#read 5, iclass 19, count 0 2006.259.07:40:12.64#ibcon#about to read 6, iclass 19, count 0 2006.259.07:40:12.64#ibcon#read 6, iclass 19, count 0 2006.259.07:40:12.64#ibcon#end of sib2, iclass 19, count 0 2006.259.07:40:12.64#ibcon#*mode == 0, iclass 19, count 0 2006.259.07:40:12.64#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.259.07:40:12.64#ibcon#[27=USB\r\n] 2006.259.07:40:12.64#ibcon#*before write, iclass 19, count 0 2006.259.07:40:12.64#ibcon#enter sib2, iclass 19, count 0 2006.259.07:40:12.64#ibcon#flushed, iclass 19, count 0 2006.259.07:40:12.64#ibcon#about to write, iclass 19, count 0 2006.259.07:40:12.64#ibcon#wrote, iclass 19, count 0 2006.259.07:40:12.64#ibcon#about to read 3, iclass 19, count 0 2006.259.07:40:12.67#ibcon#read 3, iclass 19, count 0 2006.259.07:40:12.67#ibcon#about to read 4, iclass 19, count 0 2006.259.07:40:12.67#ibcon#read 4, iclass 19, count 0 2006.259.07:40:12.67#ibcon#about to read 5, iclass 19, count 0 2006.259.07:40:12.67#ibcon#read 5, iclass 19, count 0 2006.259.07:40:12.67#ibcon#about to read 6, iclass 19, count 0 2006.259.07:40:12.67#ibcon#read 6, iclass 19, count 0 2006.259.07:40:12.67#ibcon#end of sib2, iclass 19, count 0 2006.259.07:40:12.67#ibcon#*after write, iclass 19, count 0 2006.259.07:40:12.67#ibcon#*before return 0, iclass 19, count 0 2006.259.07:40:12.67#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.259.07:40:12.67#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.259.07:40:12.67#ibcon#about to clear, iclass 19 cls_cnt 0 2006.259.07:40:12.67#ibcon#cleared, iclass 19 cls_cnt 0 2006.259.07:40:12.67$vc4f8/vblo=3,656.99 2006.259.07:40:12.67#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.259.07:40:12.67#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.259.07:40:12.67#ibcon#ireg 17 cls_cnt 0 2006.259.07:40:12.67#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.259.07:40:12.67#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.259.07:40:12.67#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.259.07:40:12.67#ibcon#enter wrdev, iclass 21, count 0 2006.259.07:40:12.67#ibcon#first serial, iclass 21, count 0 2006.259.07:40:12.67#ibcon#enter sib2, iclass 21, count 0 2006.259.07:40:12.67#ibcon#flushed, iclass 21, count 0 2006.259.07:40:12.67#ibcon#about to write, iclass 21, count 0 2006.259.07:40:12.67#ibcon#wrote, iclass 21, count 0 2006.259.07:40:12.67#ibcon#about to read 3, iclass 21, count 0 2006.259.07:40:12.69#ibcon#read 3, iclass 21, count 0 2006.259.07:40:12.69#ibcon#about to read 4, iclass 21, count 0 2006.259.07:40:12.69#ibcon#read 4, iclass 21, count 0 2006.259.07:40:12.69#ibcon#about to read 5, iclass 21, count 0 2006.259.07:40:12.69#ibcon#read 5, iclass 21, count 0 2006.259.07:40:12.69#ibcon#about to read 6, iclass 21, count 0 2006.259.07:40:12.69#ibcon#read 6, iclass 21, count 0 2006.259.07:40:12.69#ibcon#end of sib2, iclass 21, count 0 2006.259.07:40:12.69#ibcon#*mode == 0, iclass 21, count 0 2006.259.07:40:12.69#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.259.07:40:12.69#ibcon#[28=FRQ=03,656.99\r\n] 2006.259.07:40:12.69#ibcon#*before write, iclass 21, count 0 2006.259.07:40:12.69#ibcon#enter sib2, iclass 21, count 0 2006.259.07:40:12.69#ibcon#flushed, iclass 21, count 0 2006.259.07:40:12.69#ibcon#about to write, iclass 21, count 0 2006.259.07:40:12.69#ibcon#wrote, iclass 21, count 0 2006.259.07:40:12.69#ibcon#about to read 3, iclass 21, count 0 2006.259.07:40:12.73#ibcon#read 3, iclass 21, count 0 2006.259.07:40:12.73#ibcon#about to read 4, iclass 21, count 0 2006.259.07:40:12.73#ibcon#read 4, iclass 21, count 0 2006.259.07:40:12.73#ibcon#about to read 5, iclass 21, count 0 2006.259.07:40:12.73#ibcon#read 5, iclass 21, count 0 2006.259.07:40:12.73#ibcon#about to read 6, iclass 21, count 0 2006.259.07:40:12.73#ibcon#read 6, iclass 21, count 0 2006.259.07:40:12.73#ibcon#end of sib2, iclass 21, count 0 2006.259.07:40:12.73#ibcon#*after write, iclass 21, count 0 2006.259.07:40:12.73#ibcon#*before return 0, iclass 21, count 0 2006.259.07:40:12.73#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.259.07:40:12.73#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.259.07:40:12.73#ibcon#about to clear, iclass 21 cls_cnt 0 2006.259.07:40:12.73#ibcon#cleared, iclass 21 cls_cnt 0 2006.259.07:40:12.73$vc4f8/vb=3,4 2006.259.07:40:12.73#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.259.07:40:12.73#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.259.07:40:12.73#ibcon#ireg 11 cls_cnt 2 2006.259.07:40:12.73#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.259.07:40:12.79#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.259.07:40:12.79#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.259.07:40:12.79#ibcon#enter wrdev, iclass 23, count 2 2006.259.07:40:12.79#ibcon#first serial, iclass 23, count 2 2006.259.07:40:12.79#ibcon#enter sib2, iclass 23, count 2 2006.259.07:40:12.79#ibcon#flushed, iclass 23, count 2 2006.259.07:40:12.79#ibcon#about to write, iclass 23, count 2 2006.259.07:40:12.79#ibcon#wrote, iclass 23, count 2 2006.259.07:40:12.79#ibcon#about to read 3, iclass 23, count 2 2006.259.07:40:12.81#ibcon#read 3, iclass 23, count 2 2006.259.07:40:12.81#ibcon#about to read 4, iclass 23, count 2 2006.259.07:40:12.81#ibcon#read 4, iclass 23, count 2 2006.259.07:40:12.81#ibcon#about to read 5, iclass 23, count 2 2006.259.07:40:12.81#ibcon#read 5, iclass 23, count 2 2006.259.07:40:12.81#ibcon#about to read 6, iclass 23, count 2 2006.259.07:40:12.81#ibcon#read 6, iclass 23, count 2 2006.259.07:40:12.81#ibcon#end of sib2, iclass 23, count 2 2006.259.07:40:12.81#ibcon#*mode == 0, iclass 23, count 2 2006.259.07:40:12.81#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.259.07:40:12.81#ibcon#[27=AT03-04\r\n] 2006.259.07:40:12.81#ibcon#*before write, iclass 23, count 2 2006.259.07:40:12.81#ibcon#enter sib2, iclass 23, count 2 2006.259.07:40:12.81#ibcon#flushed, iclass 23, count 2 2006.259.07:40:12.81#ibcon#about to write, iclass 23, count 2 2006.259.07:40:12.81#ibcon#wrote, iclass 23, count 2 2006.259.07:40:12.81#ibcon#about to read 3, iclass 23, count 2 2006.259.07:40:12.84#ibcon#read 3, iclass 23, count 2 2006.259.07:40:12.84#ibcon#about to read 4, iclass 23, count 2 2006.259.07:40:12.84#ibcon#read 4, iclass 23, count 2 2006.259.07:40:12.84#ibcon#about to read 5, iclass 23, count 2 2006.259.07:40:12.84#ibcon#read 5, iclass 23, count 2 2006.259.07:40:12.84#ibcon#about to read 6, iclass 23, count 2 2006.259.07:40:12.84#ibcon#read 6, iclass 23, count 2 2006.259.07:40:12.84#ibcon#end of sib2, iclass 23, count 2 2006.259.07:40:12.84#ibcon#*after write, iclass 23, count 2 2006.259.07:40:12.84#ibcon#*before return 0, iclass 23, count 2 2006.259.07:40:12.84#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.259.07:40:12.84#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.259.07:40:12.84#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.259.07:40:12.84#ibcon#ireg 7 cls_cnt 0 2006.259.07:40:12.84#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.259.07:40:12.96#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.259.07:40:12.96#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.259.07:40:12.96#ibcon#enter wrdev, iclass 23, count 0 2006.259.07:40:12.96#ibcon#first serial, iclass 23, count 0 2006.259.07:40:12.96#ibcon#enter sib2, iclass 23, count 0 2006.259.07:40:12.96#ibcon#flushed, iclass 23, count 0 2006.259.07:40:12.96#ibcon#about to write, iclass 23, count 0 2006.259.07:40:12.96#ibcon#wrote, iclass 23, count 0 2006.259.07:40:12.96#ibcon#about to read 3, iclass 23, count 0 2006.259.07:40:12.98#ibcon#read 3, iclass 23, count 0 2006.259.07:40:12.98#ibcon#about to read 4, iclass 23, count 0 2006.259.07:40:12.98#ibcon#read 4, iclass 23, count 0 2006.259.07:40:12.98#ibcon#about to read 5, iclass 23, count 0 2006.259.07:40:12.98#ibcon#read 5, iclass 23, count 0 2006.259.07:40:12.98#ibcon#about to read 6, iclass 23, count 0 2006.259.07:40:12.98#ibcon#read 6, iclass 23, count 0 2006.259.07:40:12.98#ibcon#end of sib2, iclass 23, count 0 2006.259.07:40:12.98#ibcon#*mode == 0, iclass 23, count 0 2006.259.07:40:12.98#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.259.07:40:12.98#ibcon#[27=USB\r\n] 2006.259.07:40:12.98#ibcon#*before write, iclass 23, count 0 2006.259.07:40:12.98#ibcon#enter sib2, iclass 23, count 0 2006.259.07:40:12.98#ibcon#flushed, iclass 23, count 0 2006.259.07:40:12.98#ibcon#about to write, iclass 23, count 0 2006.259.07:40:12.98#ibcon#wrote, iclass 23, count 0 2006.259.07:40:12.98#ibcon#about to read 3, iclass 23, count 0 2006.259.07:40:13.01#ibcon#read 3, iclass 23, count 0 2006.259.07:40:13.01#ibcon#about to read 4, iclass 23, count 0 2006.259.07:40:13.01#ibcon#read 4, iclass 23, count 0 2006.259.07:40:13.01#ibcon#about to read 5, iclass 23, count 0 2006.259.07:40:13.01#ibcon#read 5, iclass 23, count 0 2006.259.07:40:13.01#ibcon#about to read 6, iclass 23, count 0 2006.259.07:40:13.01#ibcon#read 6, iclass 23, count 0 2006.259.07:40:13.01#ibcon#end of sib2, iclass 23, count 0 2006.259.07:40:13.01#ibcon#*after write, iclass 23, count 0 2006.259.07:40:13.01#ibcon#*before return 0, iclass 23, count 0 2006.259.07:40:13.01#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.259.07:40:13.01#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.259.07:40:13.01#ibcon#about to clear, iclass 23 cls_cnt 0 2006.259.07:40:13.01#ibcon#cleared, iclass 23 cls_cnt 0 2006.259.07:40:13.01$vc4f8/vblo=4,712.99 2006.259.07:40:13.01#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.259.07:40:13.01#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.259.07:40:13.01#ibcon#ireg 17 cls_cnt 0 2006.259.07:40:13.01#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.259.07:40:13.01#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.259.07:40:13.01#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.259.07:40:13.01#ibcon#enter wrdev, iclass 25, count 0 2006.259.07:40:13.01#ibcon#first serial, iclass 25, count 0 2006.259.07:40:13.01#ibcon#enter sib2, iclass 25, count 0 2006.259.07:40:13.01#ibcon#flushed, iclass 25, count 0 2006.259.07:40:13.01#ibcon#about to write, iclass 25, count 0 2006.259.07:40:13.01#ibcon#wrote, iclass 25, count 0 2006.259.07:40:13.01#ibcon#about to read 3, iclass 25, count 0 2006.259.07:40:13.03#ibcon#read 3, iclass 25, count 0 2006.259.07:40:13.03#ibcon#about to read 4, iclass 25, count 0 2006.259.07:40:13.03#ibcon#read 4, iclass 25, count 0 2006.259.07:40:13.03#ibcon#about to read 5, iclass 25, count 0 2006.259.07:40:13.03#ibcon#read 5, iclass 25, count 0 2006.259.07:40:13.03#ibcon#about to read 6, iclass 25, count 0 2006.259.07:40:13.03#ibcon#read 6, iclass 25, count 0 2006.259.07:40:13.03#ibcon#end of sib2, iclass 25, count 0 2006.259.07:40:13.03#ibcon#*mode == 0, iclass 25, count 0 2006.259.07:40:13.03#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.259.07:40:13.03#ibcon#[28=FRQ=04,712.99\r\n] 2006.259.07:40:13.03#ibcon#*before write, iclass 25, count 0 2006.259.07:40:13.03#ibcon#enter sib2, iclass 25, count 0 2006.259.07:40:13.03#ibcon#flushed, iclass 25, count 0 2006.259.07:40:13.03#ibcon#about to write, iclass 25, count 0 2006.259.07:40:13.03#ibcon#wrote, iclass 25, count 0 2006.259.07:40:13.03#ibcon#about to read 3, iclass 25, count 0 2006.259.07:40:13.07#ibcon#read 3, iclass 25, count 0 2006.259.07:40:13.07#ibcon#about to read 4, iclass 25, count 0 2006.259.07:40:13.07#ibcon#read 4, iclass 25, count 0 2006.259.07:40:13.07#ibcon#about to read 5, iclass 25, count 0 2006.259.07:40:13.07#ibcon#read 5, iclass 25, count 0 2006.259.07:40:13.07#ibcon#about to read 6, iclass 25, count 0 2006.259.07:40:13.07#ibcon#read 6, iclass 25, count 0 2006.259.07:40:13.07#ibcon#end of sib2, iclass 25, count 0 2006.259.07:40:13.07#ibcon#*after write, iclass 25, count 0 2006.259.07:40:13.07#ibcon#*before return 0, iclass 25, count 0 2006.259.07:40:13.07#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.259.07:40:13.07#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.259.07:40:13.07#ibcon#about to clear, iclass 25 cls_cnt 0 2006.259.07:40:13.07#ibcon#cleared, iclass 25 cls_cnt 0 2006.259.07:40:13.07$vc4f8/vb=4,5 2006.259.07:40:13.07#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.259.07:40:13.07#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.259.07:40:13.07#ibcon#ireg 11 cls_cnt 2 2006.259.07:40:13.07#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.259.07:40:13.13#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.259.07:40:13.13#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.259.07:40:13.13#ibcon#enter wrdev, iclass 27, count 2 2006.259.07:40:13.13#ibcon#first serial, iclass 27, count 2 2006.259.07:40:13.13#ibcon#enter sib2, iclass 27, count 2 2006.259.07:40:13.13#ibcon#flushed, iclass 27, count 2 2006.259.07:40:13.13#ibcon#about to write, iclass 27, count 2 2006.259.07:40:13.13#ibcon#wrote, iclass 27, count 2 2006.259.07:40:13.13#ibcon#about to read 3, iclass 27, count 2 2006.259.07:40:13.15#ibcon#read 3, iclass 27, count 2 2006.259.07:40:13.15#ibcon#about to read 4, iclass 27, count 2 2006.259.07:40:13.15#ibcon#read 4, iclass 27, count 2 2006.259.07:40:13.15#ibcon#about to read 5, iclass 27, count 2 2006.259.07:40:13.15#ibcon#read 5, iclass 27, count 2 2006.259.07:40:13.15#ibcon#about to read 6, iclass 27, count 2 2006.259.07:40:13.15#ibcon#read 6, iclass 27, count 2 2006.259.07:40:13.15#ibcon#end of sib2, iclass 27, count 2 2006.259.07:40:13.15#ibcon#*mode == 0, iclass 27, count 2 2006.259.07:40:13.15#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.259.07:40:13.15#ibcon#[27=AT04-05\r\n] 2006.259.07:40:13.15#ibcon#*before write, iclass 27, count 2 2006.259.07:40:13.15#ibcon#enter sib2, iclass 27, count 2 2006.259.07:40:13.15#ibcon#flushed, iclass 27, count 2 2006.259.07:40:13.15#ibcon#about to write, iclass 27, count 2 2006.259.07:40:13.15#ibcon#wrote, iclass 27, count 2 2006.259.07:40:13.15#ibcon#about to read 3, iclass 27, count 2 2006.259.07:40:13.18#ibcon#read 3, iclass 27, count 2 2006.259.07:40:13.18#ibcon#about to read 4, iclass 27, count 2 2006.259.07:40:13.18#ibcon#read 4, iclass 27, count 2 2006.259.07:40:13.18#ibcon#about to read 5, iclass 27, count 2 2006.259.07:40:13.18#ibcon#read 5, iclass 27, count 2 2006.259.07:40:13.18#ibcon#about to read 6, iclass 27, count 2 2006.259.07:40:13.18#ibcon#read 6, iclass 27, count 2 2006.259.07:40:13.18#ibcon#end of sib2, iclass 27, count 2 2006.259.07:40:13.18#ibcon#*after write, iclass 27, count 2 2006.259.07:40:13.18#ibcon#*before return 0, iclass 27, count 2 2006.259.07:40:13.18#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.259.07:40:13.18#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.259.07:40:13.18#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.259.07:40:13.18#ibcon#ireg 7 cls_cnt 0 2006.259.07:40:13.18#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.259.07:40:13.30#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.259.07:40:13.30#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.259.07:40:13.30#ibcon#enter wrdev, iclass 27, count 0 2006.259.07:40:13.30#ibcon#first serial, iclass 27, count 0 2006.259.07:40:13.30#ibcon#enter sib2, iclass 27, count 0 2006.259.07:40:13.30#ibcon#flushed, iclass 27, count 0 2006.259.07:40:13.30#ibcon#about to write, iclass 27, count 0 2006.259.07:40:13.30#ibcon#wrote, iclass 27, count 0 2006.259.07:40:13.30#ibcon#about to read 3, iclass 27, count 0 2006.259.07:40:13.32#ibcon#read 3, iclass 27, count 0 2006.259.07:40:13.32#ibcon#about to read 4, iclass 27, count 0 2006.259.07:40:13.32#ibcon#read 4, iclass 27, count 0 2006.259.07:40:13.32#ibcon#about to read 5, iclass 27, count 0 2006.259.07:40:13.32#ibcon#read 5, iclass 27, count 0 2006.259.07:40:13.32#ibcon#about to read 6, iclass 27, count 0 2006.259.07:40:13.32#ibcon#read 6, iclass 27, count 0 2006.259.07:40:13.32#ibcon#end of sib2, iclass 27, count 0 2006.259.07:40:13.32#ibcon#*mode == 0, iclass 27, count 0 2006.259.07:40:13.32#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.259.07:40:13.32#ibcon#[27=USB\r\n] 2006.259.07:40:13.32#ibcon#*before write, iclass 27, count 0 2006.259.07:40:13.32#ibcon#enter sib2, iclass 27, count 0 2006.259.07:40:13.32#ibcon#flushed, iclass 27, count 0 2006.259.07:40:13.32#ibcon#about to write, iclass 27, count 0 2006.259.07:40:13.32#ibcon#wrote, iclass 27, count 0 2006.259.07:40:13.32#ibcon#about to read 3, iclass 27, count 0 2006.259.07:40:13.35#ibcon#read 3, iclass 27, count 0 2006.259.07:40:13.35#ibcon#about to read 4, iclass 27, count 0 2006.259.07:40:13.35#ibcon#read 4, iclass 27, count 0 2006.259.07:40:13.35#ibcon#about to read 5, iclass 27, count 0 2006.259.07:40:13.35#ibcon#read 5, iclass 27, count 0 2006.259.07:40:13.35#ibcon#about to read 6, iclass 27, count 0 2006.259.07:40:13.35#ibcon#read 6, iclass 27, count 0 2006.259.07:40:13.35#ibcon#end of sib2, iclass 27, count 0 2006.259.07:40:13.35#ibcon#*after write, iclass 27, count 0 2006.259.07:40:13.35#ibcon#*before return 0, iclass 27, count 0 2006.259.07:40:13.35#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.259.07:40:13.35#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.259.07:40:13.35#ibcon#about to clear, iclass 27 cls_cnt 0 2006.259.07:40:13.35#ibcon#cleared, iclass 27 cls_cnt 0 2006.259.07:40:13.35$vc4f8/vblo=5,744.99 2006.259.07:40:13.35#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.259.07:40:13.35#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.259.07:40:13.35#ibcon#ireg 17 cls_cnt 0 2006.259.07:40:13.35#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.259.07:40:13.35#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.259.07:40:13.35#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.259.07:40:13.35#ibcon#enter wrdev, iclass 29, count 0 2006.259.07:40:13.35#ibcon#first serial, iclass 29, count 0 2006.259.07:40:13.35#ibcon#enter sib2, iclass 29, count 0 2006.259.07:40:13.35#ibcon#flushed, iclass 29, count 0 2006.259.07:40:13.35#ibcon#about to write, iclass 29, count 0 2006.259.07:40:13.35#ibcon#wrote, iclass 29, count 0 2006.259.07:40:13.35#ibcon#about to read 3, iclass 29, count 0 2006.259.07:40:13.37#ibcon#read 3, iclass 29, count 0 2006.259.07:40:13.37#ibcon#about to read 4, iclass 29, count 0 2006.259.07:40:13.37#ibcon#read 4, iclass 29, count 0 2006.259.07:40:13.37#ibcon#about to read 5, iclass 29, count 0 2006.259.07:40:13.37#ibcon#read 5, iclass 29, count 0 2006.259.07:40:13.37#ibcon#about to read 6, iclass 29, count 0 2006.259.07:40:13.37#ibcon#read 6, iclass 29, count 0 2006.259.07:40:13.37#ibcon#end of sib2, iclass 29, count 0 2006.259.07:40:13.37#ibcon#*mode == 0, iclass 29, count 0 2006.259.07:40:13.37#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.259.07:40:13.37#ibcon#[28=FRQ=05,744.99\r\n] 2006.259.07:40:13.37#ibcon#*before write, iclass 29, count 0 2006.259.07:40:13.37#ibcon#enter sib2, iclass 29, count 0 2006.259.07:40:13.37#ibcon#flushed, iclass 29, count 0 2006.259.07:40:13.37#ibcon#about to write, iclass 29, count 0 2006.259.07:40:13.37#ibcon#wrote, iclass 29, count 0 2006.259.07:40:13.37#ibcon#about to read 3, iclass 29, count 0 2006.259.07:40:13.41#ibcon#read 3, iclass 29, count 0 2006.259.07:40:13.41#ibcon#about to read 4, iclass 29, count 0 2006.259.07:40:13.41#ibcon#read 4, iclass 29, count 0 2006.259.07:40:13.41#ibcon#about to read 5, iclass 29, count 0 2006.259.07:40:13.41#ibcon#read 5, iclass 29, count 0 2006.259.07:40:13.41#ibcon#about to read 6, iclass 29, count 0 2006.259.07:40:13.41#ibcon#read 6, iclass 29, count 0 2006.259.07:40:13.41#ibcon#end of sib2, iclass 29, count 0 2006.259.07:40:13.41#ibcon#*after write, iclass 29, count 0 2006.259.07:40:13.41#ibcon#*before return 0, iclass 29, count 0 2006.259.07:40:13.41#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.259.07:40:13.41#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.259.07:40:13.41#ibcon#about to clear, iclass 29 cls_cnt 0 2006.259.07:40:13.41#ibcon#cleared, iclass 29 cls_cnt 0 2006.259.07:40:13.41$vc4f8/vb=5,4 2006.259.07:40:13.41#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.259.07:40:13.41#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.259.07:40:13.41#ibcon#ireg 11 cls_cnt 2 2006.259.07:40:13.41#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.259.07:40:13.47#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.259.07:40:13.47#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.259.07:40:13.47#ibcon#enter wrdev, iclass 31, count 2 2006.259.07:40:13.47#ibcon#first serial, iclass 31, count 2 2006.259.07:40:13.47#ibcon#enter sib2, iclass 31, count 2 2006.259.07:40:13.47#ibcon#flushed, iclass 31, count 2 2006.259.07:40:13.47#ibcon#about to write, iclass 31, count 2 2006.259.07:40:13.47#ibcon#wrote, iclass 31, count 2 2006.259.07:40:13.47#ibcon#about to read 3, iclass 31, count 2 2006.259.07:40:13.49#ibcon#read 3, iclass 31, count 2 2006.259.07:40:13.49#ibcon#about to read 4, iclass 31, count 2 2006.259.07:40:13.49#ibcon#read 4, iclass 31, count 2 2006.259.07:40:13.49#ibcon#about to read 5, iclass 31, count 2 2006.259.07:40:13.49#ibcon#read 5, iclass 31, count 2 2006.259.07:40:13.49#ibcon#about to read 6, iclass 31, count 2 2006.259.07:40:13.49#ibcon#read 6, iclass 31, count 2 2006.259.07:40:13.49#ibcon#end of sib2, iclass 31, count 2 2006.259.07:40:13.49#ibcon#*mode == 0, iclass 31, count 2 2006.259.07:40:13.49#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.259.07:40:13.49#ibcon#[27=AT05-04\r\n] 2006.259.07:40:13.49#ibcon#*before write, iclass 31, count 2 2006.259.07:40:13.49#ibcon#enter sib2, iclass 31, count 2 2006.259.07:40:13.49#ibcon#flushed, iclass 31, count 2 2006.259.07:40:13.49#ibcon#about to write, iclass 31, count 2 2006.259.07:40:13.49#ibcon#wrote, iclass 31, count 2 2006.259.07:40:13.49#ibcon#about to read 3, iclass 31, count 2 2006.259.07:40:13.52#ibcon#read 3, iclass 31, count 2 2006.259.07:40:13.52#ibcon#about to read 4, iclass 31, count 2 2006.259.07:40:13.52#ibcon#read 4, iclass 31, count 2 2006.259.07:40:13.52#ibcon#about to read 5, iclass 31, count 2 2006.259.07:40:13.52#ibcon#read 5, iclass 31, count 2 2006.259.07:40:13.52#ibcon#about to read 6, iclass 31, count 2 2006.259.07:40:13.52#ibcon#read 6, iclass 31, count 2 2006.259.07:40:13.52#ibcon#end of sib2, iclass 31, count 2 2006.259.07:40:13.52#ibcon#*after write, iclass 31, count 2 2006.259.07:40:13.52#ibcon#*before return 0, iclass 31, count 2 2006.259.07:40:13.52#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.259.07:40:13.52#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.259.07:40:13.52#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.259.07:40:13.52#ibcon#ireg 7 cls_cnt 0 2006.259.07:40:13.52#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.259.07:40:13.64#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.259.07:40:13.64#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.259.07:40:13.64#ibcon#enter wrdev, iclass 31, count 0 2006.259.07:40:13.64#ibcon#first serial, iclass 31, count 0 2006.259.07:40:13.64#ibcon#enter sib2, iclass 31, count 0 2006.259.07:40:13.64#ibcon#flushed, iclass 31, count 0 2006.259.07:40:13.64#ibcon#about to write, iclass 31, count 0 2006.259.07:40:13.64#ibcon#wrote, iclass 31, count 0 2006.259.07:40:13.64#ibcon#about to read 3, iclass 31, count 0 2006.259.07:40:13.66#ibcon#read 3, iclass 31, count 0 2006.259.07:40:13.66#ibcon#about to read 4, iclass 31, count 0 2006.259.07:40:13.66#ibcon#read 4, iclass 31, count 0 2006.259.07:40:13.66#ibcon#about to read 5, iclass 31, count 0 2006.259.07:40:13.66#ibcon#read 5, iclass 31, count 0 2006.259.07:40:13.66#ibcon#about to read 6, iclass 31, count 0 2006.259.07:40:13.66#ibcon#read 6, iclass 31, count 0 2006.259.07:40:13.66#ibcon#end of sib2, iclass 31, count 0 2006.259.07:40:13.66#ibcon#*mode == 0, iclass 31, count 0 2006.259.07:40:13.66#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.259.07:40:13.66#ibcon#[27=USB\r\n] 2006.259.07:40:13.66#ibcon#*before write, iclass 31, count 0 2006.259.07:40:13.66#ibcon#enter sib2, iclass 31, count 0 2006.259.07:40:13.66#ibcon#flushed, iclass 31, count 0 2006.259.07:40:13.66#ibcon#about to write, iclass 31, count 0 2006.259.07:40:13.66#ibcon#wrote, iclass 31, count 0 2006.259.07:40:13.66#ibcon#about to read 3, iclass 31, count 0 2006.259.07:40:13.69#ibcon#read 3, iclass 31, count 0 2006.259.07:40:13.69#ibcon#about to read 4, iclass 31, count 0 2006.259.07:40:13.69#ibcon#read 4, iclass 31, count 0 2006.259.07:40:13.69#ibcon#about to read 5, iclass 31, count 0 2006.259.07:40:13.69#ibcon#read 5, iclass 31, count 0 2006.259.07:40:13.69#ibcon#about to read 6, iclass 31, count 0 2006.259.07:40:13.69#ibcon#read 6, iclass 31, count 0 2006.259.07:40:13.69#ibcon#end of sib2, iclass 31, count 0 2006.259.07:40:13.69#ibcon#*after write, iclass 31, count 0 2006.259.07:40:13.69#ibcon#*before return 0, iclass 31, count 0 2006.259.07:40:13.69#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.259.07:40:13.69#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.259.07:40:13.69#ibcon#about to clear, iclass 31 cls_cnt 0 2006.259.07:40:13.69#ibcon#cleared, iclass 31 cls_cnt 0 2006.259.07:40:13.69$vc4f8/vblo=6,752.99 2006.259.07:40:13.69#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.259.07:40:13.69#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.259.07:40:13.69#ibcon#ireg 17 cls_cnt 0 2006.259.07:40:13.69#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.259.07:40:13.69#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.259.07:40:13.69#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.259.07:40:13.69#ibcon#enter wrdev, iclass 33, count 0 2006.259.07:40:13.69#ibcon#first serial, iclass 33, count 0 2006.259.07:40:13.69#ibcon#enter sib2, iclass 33, count 0 2006.259.07:40:13.69#ibcon#flushed, iclass 33, count 0 2006.259.07:40:13.69#ibcon#about to write, iclass 33, count 0 2006.259.07:40:13.69#ibcon#wrote, iclass 33, count 0 2006.259.07:40:13.69#ibcon#about to read 3, iclass 33, count 0 2006.259.07:40:13.71#ibcon#read 3, iclass 33, count 0 2006.259.07:40:13.71#ibcon#about to read 4, iclass 33, count 0 2006.259.07:40:13.71#ibcon#read 4, iclass 33, count 0 2006.259.07:40:13.71#ibcon#about to read 5, iclass 33, count 0 2006.259.07:40:13.71#ibcon#read 5, iclass 33, count 0 2006.259.07:40:13.71#ibcon#about to read 6, iclass 33, count 0 2006.259.07:40:13.71#ibcon#read 6, iclass 33, count 0 2006.259.07:40:13.71#ibcon#end of sib2, iclass 33, count 0 2006.259.07:40:13.71#ibcon#*mode == 0, iclass 33, count 0 2006.259.07:40:13.71#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.259.07:40:13.71#ibcon#[28=FRQ=06,752.99\r\n] 2006.259.07:40:13.71#ibcon#*before write, iclass 33, count 0 2006.259.07:40:13.71#ibcon#enter sib2, iclass 33, count 0 2006.259.07:40:13.71#ibcon#flushed, iclass 33, count 0 2006.259.07:40:13.71#ibcon#about to write, iclass 33, count 0 2006.259.07:40:13.71#ibcon#wrote, iclass 33, count 0 2006.259.07:40:13.71#ibcon#about to read 3, iclass 33, count 0 2006.259.07:40:13.75#ibcon#read 3, iclass 33, count 0 2006.259.07:40:13.75#ibcon#about to read 4, iclass 33, count 0 2006.259.07:40:13.75#ibcon#read 4, iclass 33, count 0 2006.259.07:40:13.75#ibcon#about to read 5, iclass 33, count 0 2006.259.07:40:13.75#ibcon#read 5, iclass 33, count 0 2006.259.07:40:13.75#ibcon#about to read 6, iclass 33, count 0 2006.259.07:40:13.75#ibcon#read 6, iclass 33, count 0 2006.259.07:40:13.75#ibcon#end of sib2, iclass 33, count 0 2006.259.07:40:13.75#ibcon#*after write, iclass 33, count 0 2006.259.07:40:13.75#ibcon#*before return 0, iclass 33, count 0 2006.259.07:40:13.75#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.259.07:40:13.75#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.259.07:40:13.75#ibcon#about to clear, iclass 33 cls_cnt 0 2006.259.07:40:13.75#ibcon#cleared, iclass 33 cls_cnt 0 2006.259.07:40:13.75$vc4f8/vb=6,4 2006.259.07:40:13.75#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.259.07:40:13.75#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.259.07:40:13.75#ibcon#ireg 11 cls_cnt 2 2006.259.07:40:13.75#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.259.07:40:13.81#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.259.07:40:13.81#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.259.07:40:13.81#ibcon#enter wrdev, iclass 35, count 2 2006.259.07:40:13.81#ibcon#first serial, iclass 35, count 2 2006.259.07:40:13.81#ibcon#enter sib2, iclass 35, count 2 2006.259.07:40:13.81#ibcon#flushed, iclass 35, count 2 2006.259.07:40:13.81#ibcon#about to write, iclass 35, count 2 2006.259.07:40:13.81#ibcon#wrote, iclass 35, count 2 2006.259.07:40:13.81#ibcon#about to read 3, iclass 35, count 2 2006.259.07:40:13.83#ibcon#read 3, iclass 35, count 2 2006.259.07:40:13.83#ibcon#about to read 4, iclass 35, count 2 2006.259.07:40:13.83#ibcon#read 4, iclass 35, count 2 2006.259.07:40:13.83#ibcon#about to read 5, iclass 35, count 2 2006.259.07:40:13.83#ibcon#read 5, iclass 35, count 2 2006.259.07:40:13.83#ibcon#about to read 6, iclass 35, count 2 2006.259.07:40:13.83#ibcon#read 6, iclass 35, count 2 2006.259.07:40:13.83#ibcon#end of sib2, iclass 35, count 2 2006.259.07:40:13.83#ibcon#*mode == 0, iclass 35, count 2 2006.259.07:40:13.83#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.259.07:40:13.83#ibcon#[27=AT06-04\r\n] 2006.259.07:40:13.83#ibcon#*before write, iclass 35, count 2 2006.259.07:40:13.83#ibcon#enter sib2, iclass 35, count 2 2006.259.07:40:13.83#ibcon#flushed, iclass 35, count 2 2006.259.07:40:13.83#ibcon#about to write, iclass 35, count 2 2006.259.07:40:13.83#ibcon#wrote, iclass 35, count 2 2006.259.07:40:13.83#ibcon#about to read 3, iclass 35, count 2 2006.259.07:40:13.86#ibcon#read 3, iclass 35, count 2 2006.259.07:40:13.86#ibcon#about to read 4, iclass 35, count 2 2006.259.07:40:13.86#ibcon#read 4, iclass 35, count 2 2006.259.07:40:13.86#ibcon#about to read 5, iclass 35, count 2 2006.259.07:40:13.86#ibcon#read 5, iclass 35, count 2 2006.259.07:40:13.86#ibcon#about to read 6, iclass 35, count 2 2006.259.07:40:13.86#ibcon#read 6, iclass 35, count 2 2006.259.07:40:13.86#ibcon#end of sib2, iclass 35, count 2 2006.259.07:40:13.86#ibcon#*after write, iclass 35, count 2 2006.259.07:40:13.86#ibcon#*before return 0, iclass 35, count 2 2006.259.07:40:13.86#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.259.07:40:13.86#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.259.07:40:13.86#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.259.07:40:13.86#ibcon#ireg 7 cls_cnt 0 2006.259.07:40:13.86#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.259.07:40:13.98#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.259.07:40:13.98#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.259.07:40:13.98#ibcon#enter wrdev, iclass 35, count 0 2006.259.07:40:13.98#ibcon#first serial, iclass 35, count 0 2006.259.07:40:13.98#ibcon#enter sib2, iclass 35, count 0 2006.259.07:40:13.98#ibcon#flushed, iclass 35, count 0 2006.259.07:40:13.98#ibcon#about to write, iclass 35, count 0 2006.259.07:40:13.98#ibcon#wrote, iclass 35, count 0 2006.259.07:40:13.98#ibcon#about to read 3, iclass 35, count 0 2006.259.07:40:14.00#ibcon#read 3, iclass 35, count 0 2006.259.07:40:14.00#ibcon#about to read 4, iclass 35, count 0 2006.259.07:40:14.00#ibcon#read 4, iclass 35, count 0 2006.259.07:40:14.00#ibcon#about to read 5, iclass 35, count 0 2006.259.07:40:14.00#ibcon#read 5, iclass 35, count 0 2006.259.07:40:14.00#ibcon#about to read 6, iclass 35, count 0 2006.259.07:40:14.00#ibcon#read 6, iclass 35, count 0 2006.259.07:40:14.00#ibcon#end of sib2, iclass 35, count 0 2006.259.07:40:14.00#ibcon#*mode == 0, iclass 35, count 0 2006.259.07:40:14.00#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.259.07:40:14.00#ibcon#[27=USB\r\n] 2006.259.07:40:14.00#ibcon#*before write, iclass 35, count 0 2006.259.07:40:14.00#ibcon#enter sib2, iclass 35, count 0 2006.259.07:40:14.00#ibcon#flushed, iclass 35, count 0 2006.259.07:40:14.00#ibcon#about to write, iclass 35, count 0 2006.259.07:40:14.00#ibcon#wrote, iclass 35, count 0 2006.259.07:40:14.00#ibcon#about to read 3, iclass 35, count 0 2006.259.07:40:14.03#ibcon#read 3, iclass 35, count 0 2006.259.07:40:14.03#ibcon#about to read 4, iclass 35, count 0 2006.259.07:40:14.03#ibcon#read 4, iclass 35, count 0 2006.259.07:40:14.03#ibcon#about to read 5, iclass 35, count 0 2006.259.07:40:14.03#ibcon#read 5, iclass 35, count 0 2006.259.07:40:14.03#ibcon#about to read 6, iclass 35, count 0 2006.259.07:40:14.03#ibcon#read 6, iclass 35, count 0 2006.259.07:40:14.03#ibcon#end of sib2, iclass 35, count 0 2006.259.07:40:14.03#ibcon#*after write, iclass 35, count 0 2006.259.07:40:14.03#ibcon#*before return 0, iclass 35, count 0 2006.259.07:40:14.03#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.259.07:40:14.03#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.259.07:40:14.03#ibcon#about to clear, iclass 35 cls_cnt 0 2006.259.07:40:14.03#ibcon#cleared, iclass 35 cls_cnt 0 2006.259.07:40:14.03$vc4f8/vabw=wide 2006.259.07:40:14.03#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.259.07:40:14.03#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.259.07:40:14.03#ibcon#ireg 8 cls_cnt 0 2006.259.07:40:14.03#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.259.07:40:14.03#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.259.07:40:14.03#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.259.07:40:14.03#ibcon#enter wrdev, iclass 37, count 0 2006.259.07:40:14.03#ibcon#first serial, iclass 37, count 0 2006.259.07:40:14.03#ibcon#enter sib2, iclass 37, count 0 2006.259.07:40:14.03#ibcon#flushed, iclass 37, count 0 2006.259.07:40:14.03#ibcon#about to write, iclass 37, count 0 2006.259.07:40:14.03#ibcon#wrote, iclass 37, count 0 2006.259.07:40:14.03#ibcon#about to read 3, iclass 37, count 0 2006.259.07:40:14.05#ibcon#read 3, iclass 37, count 0 2006.259.07:40:14.05#ibcon#about to read 4, iclass 37, count 0 2006.259.07:40:14.05#ibcon#read 4, iclass 37, count 0 2006.259.07:40:14.05#ibcon#about to read 5, iclass 37, count 0 2006.259.07:40:14.05#ibcon#read 5, iclass 37, count 0 2006.259.07:40:14.05#ibcon#about to read 6, iclass 37, count 0 2006.259.07:40:14.05#ibcon#read 6, iclass 37, count 0 2006.259.07:40:14.05#ibcon#end of sib2, iclass 37, count 0 2006.259.07:40:14.05#ibcon#*mode == 0, iclass 37, count 0 2006.259.07:40:14.05#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.259.07:40:14.05#ibcon#[25=BW32\r\n] 2006.259.07:40:14.05#ibcon#*before write, iclass 37, count 0 2006.259.07:40:14.05#ibcon#enter sib2, iclass 37, count 0 2006.259.07:40:14.05#ibcon#flushed, iclass 37, count 0 2006.259.07:40:14.05#ibcon#about to write, iclass 37, count 0 2006.259.07:40:14.05#ibcon#wrote, iclass 37, count 0 2006.259.07:40:14.05#ibcon#about to read 3, iclass 37, count 0 2006.259.07:40:14.08#ibcon#read 3, iclass 37, count 0 2006.259.07:40:14.08#ibcon#about to read 4, iclass 37, count 0 2006.259.07:40:14.08#ibcon#read 4, iclass 37, count 0 2006.259.07:40:14.08#ibcon#about to read 5, iclass 37, count 0 2006.259.07:40:14.08#ibcon#read 5, iclass 37, count 0 2006.259.07:40:14.08#ibcon#about to read 6, iclass 37, count 0 2006.259.07:40:14.08#ibcon#read 6, iclass 37, count 0 2006.259.07:40:14.08#ibcon#end of sib2, iclass 37, count 0 2006.259.07:40:14.08#ibcon#*after write, iclass 37, count 0 2006.259.07:40:14.08#ibcon#*before return 0, iclass 37, count 0 2006.259.07:40:14.08#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.259.07:40:14.08#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.259.07:40:14.08#ibcon#about to clear, iclass 37 cls_cnt 0 2006.259.07:40:14.08#ibcon#cleared, iclass 37 cls_cnt 0 2006.259.07:40:14.08$vc4f8/vbbw=wide 2006.259.07:40:14.08#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.259.07:40:14.08#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.259.07:40:14.08#ibcon#ireg 8 cls_cnt 0 2006.259.07:40:14.08#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.259.07:40:14.15#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.259.07:40:14.15#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.259.07:40:14.15#ibcon#enter wrdev, iclass 39, count 0 2006.259.07:40:14.15#ibcon#first serial, iclass 39, count 0 2006.259.07:40:14.15#ibcon#enter sib2, iclass 39, count 0 2006.259.07:40:14.15#ibcon#flushed, iclass 39, count 0 2006.259.07:40:14.15#ibcon#about to write, iclass 39, count 0 2006.259.07:40:14.15#ibcon#wrote, iclass 39, count 0 2006.259.07:40:14.15#ibcon#about to read 3, iclass 39, count 0 2006.259.07:40:14.17#ibcon#read 3, iclass 39, count 0 2006.259.07:40:14.17#ibcon#about to read 4, iclass 39, count 0 2006.259.07:40:14.17#ibcon#read 4, iclass 39, count 0 2006.259.07:40:14.17#ibcon#about to read 5, iclass 39, count 0 2006.259.07:40:14.17#ibcon#read 5, iclass 39, count 0 2006.259.07:40:14.17#ibcon#about to read 6, iclass 39, count 0 2006.259.07:40:14.17#ibcon#read 6, iclass 39, count 0 2006.259.07:40:14.17#ibcon#end of sib2, iclass 39, count 0 2006.259.07:40:14.17#ibcon#*mode == 0, iclass 39, count 0 2006.259.07:40:14.17#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.259.07:40:14.17#ibcon#[27=BW32\r\n] 2006.259.07:40:14.17#ibcon#*before write, iclass 39, count 0 2006.259.07:40:14.17#ibcon#enter sib2, iclass 39, count 0 2006.259.07:40:14.17#ibcon#flushed, iclass 39, count 0 2006.259.07:40:14.17#ibcon#about to write, iclass 39, count 0 2006.259.07:40:14.17#ibcon#wrote, iclass 39, count 0 2006.259.07:40:14.17#ibcon#about to read 3, iclass 39, count 0 2006.259.07:40:14.20#ibcon#read 3, iclass 39, count 0 2006.259.07:40:14.20#ibcon#about to read 4, iclass 39, count 0 2006.259.07:40:14.20#ibcon#read 4, iclass 39, count 0 2006.259.07:40:14.20#ibcon#about to read 5, iclass 39, count 0 2006.259.07:40:14.20#ibcon#read 5, iclass 39, count 0 2006.259.07:40:14.20#ibcon#about to read 6, iclass 39, count 0 2006.259.07:40:14.20#ibcon#read 6, iclass 39, count 0 2006.259.07:40:14.20#ibcon#end of sib2, iclass 39, count 0 2006.259.07:40:14.20#ibcon#*after write, iclass 39, count 0 2006.259.07:40:14.20#ibcon#*before return 0, iclass 39, count 0 2006.259.07:40:14.20#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.259.07:40:14.20#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.259.07:40:14.20#ibcon#about to clear, iclass 39 cls_cnt 0 2006.259.07:40:14.20#ibcon#cleared, iclass 39 cls_cnt 0 2006.259.07:40:14.20$4f8m12a/ifd4f 2006.259.07:40:14.20$ifd4f/lo= 2006.259.07:40:14.20$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.259.07:40:14.20$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.259.07:40:14.20$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.259.07:40:14.20$ifd4f/patch= 2006.259.07:40:14.20$ifd4f/patch=lo1,a1,a2,a3,a4 2006.259.07:40:14.20$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.259.07:40:14.20$ifd4f/patch=lo3,a5,a6,a7,a8 2006.259.07:40:14.20$4f8m12a/"form=m,16.000,1:2 2006.259.07:40:14.20$4f8m12a/"tpicd 2006.259.07:40:14.20$4f8m12a/echo=off 2006.259.07:40:14.20$4f8m12a/xlog=off 2006.259.07:40:14.20:!2006.259.07:40:40 2006.259.07:40:19.13#trakl#Source acquired 2006.259.07:40:19.13#flagr#flagr/antenna,acquired 2006.259.07:40:40.00:preob 2006.259.07:40:41.13/onsource/TRACKING 2006.259.07:40:41.13:!2006.259.07:40:50 2006.259.07:40:50.00:data_valid=on 2006.259.07:40:50.00:midob 2006.259.07:40:50.13/onsource/TRACKING 2006.259.07:40:50.13/wx/22.28,1013.0,85 2006.259.07:40:50.21/cable/+6.4592E-03 2006.259.07:40:51.30/va/01,08,usb,yes,31,33 2006.259.07:40:51.30/va/02,07,usb,yes,31,33 2006.259.07:40:51.30/va/03,08,usb,yes,23,24 2006.259.07:40:51.30/va/04,07,usb,yes,32,35 2006.259.07:40:51.30/va/05,07,usb,yes,36,38 2006.259.07:40:51.30/va/06,06,usb,yes,35,35 2006.259.07:40:51.30/va/07,06,usb,yes,36,35 2006.259.07:40:51.30/va/08,06,usb,yes,38,37 2006.259.07:40:51.53/valo/01,532.99,yes,locked 2006.259.07:40:51.53/valo/02,572.99,yes,locked 2006.259.07:40:51.53/valo/03,672.99,yes,locked 2006.259.07:40:51.53/valo/04,832.99,yes,locked 2006.259.07:40:51.53/valo/05,652.99,yes,locked 2006.259.07:40:51.53/valo/06,772.99,yes,locked 2006.259.07:40:51.53/valo/07,832.99,yes,locked 2006.259.07:40:51.53/valo/08,852.99,yes,locked 2006.259.07:40:52.62/vb/01,04,usb,yes,31,29 2006.259.07:40:52.62/vb/02,05,usb,yes,29,30 2006.259.07:40:52.62/vb/03,04,usb,yes,29,33 2006.259.07:40:52.62/vb/04,05,usb,yes,26,26 2006.259.07:40:52.62/vb/05,04,usb,yes,28,32 2006.259.07:40:52.62/vb/06,04,usb,yes,29,32 2006.259.07:40:52.62/vb/07,04,usb,yes,31,31 2006.259.07:40:52.62/vb/08,04,usb,yes,29,32 2006.259.07:40:52.86/vblo/01,632.99,yes,locked 2006.259.07:40:52.86/vblo/02,640.99,yes,locked 2006.259.07:40:52.86/vblo/03,656.99,yes,locked 2006.259.07:40:52.86/vblo/04,712.99,yes,locked 2006.259.07:40:52.86/vblo/05,744.99,yes,locked 2006.259.07:40:52.86/vblo/06,752.99,yes,locked 2006.259.07:40:52.86/vblo/07,734.99,yes,locked 2006.259.07:40:52.86/vblo/08,744.99,yes,locked 2006.259.07:40:53.01/vabw/8 2006.259.07:40:53.16/vbbw/8 2006.259.07:40:53.25/xfe/off,on,15.2 2006.259.07:40:53.62/ifatt/23,28,28,28 2006.259.07:40:54.08/fmout-gps/S +4.49E-07 2006.259.07:40:54.12:!2006.259.07:41:50 2006.259.07:41:50.00:data_valid=off 2006.259.07:41:50.00:postob 2006.259.07:41:50.11/cable/+6.4585E-03 2006.259.07:41:50.11/wx/22.27,1013.0,85 2006.259.07:41:51.08/fmout-gps/S +4.48E-07 2006.259.07:41:51.08:scan_name=259-0742,k06259,60 2006.259.07:41:51.09:source=3c371,180650.68,694928.1,2000.0,cw 2006.259.07:41:51.14#flagr#flagr/antenna,new-source 2006.259.07:41:52.14:checkk5 2006.259.07:41:52.54/chk_autoobs//k5ts1/ autoobs is running! 2006.259.07:41:52.95/chk_autoobs//k5ts2/ autoobs is running! 2006.259.07:41:53.37/chk_autoobs//k5ts3/ autoobs is running! 2006.259.07:41:53.76/chk_autoobs//k5ts4/ autoobs is running! 2006.259.07:41:54.22/chk_obsdata//k5ts1/T2590740??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.259.07:41:54.63/chk_obsdata//k5ts2/T2590740??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.259.07:41:55.00/chk_obsdata//k5ts3/T2590740??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.259.07:41:55.43/chk_obsdata//k5ts4/T2590740??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.259.07:41:56.23/k5log//k5ts1_log_newline 2006.259.07:42:00.02/k5log//k5ts2_log_newline 2006.259.07:42:00.98/k5log//k5ts3_log_newline 2006.259.07:42:01.73/k5log//k5ts4_log_newline 2006.259.07:42:01.76/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.259.07:42:01.76:4f8m12a=1 2006.259.07:42:01.76$4f8m12a/echo=on 2006.259.07:42:01.76$4f8m12a/pcalon 2006.259.07:42:01.76$pcalon/"no phase cal control is implemented here 2006.259.07:42:01.76$4f8m12a/"tpicd=stop 2006.259.07:42:01.76$4f8m12a/vc4f8 2006.259.07:42:01.76$vc4f8/valo=1,532.99 2006.259.07:42:01.76#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.259.07:42:01.76#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.259.07:42:01.76#ibcon#ireg 17 cls_cnt 0 2006.259.07:42:01.76#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.259.07:42:01.76#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.259.07:42:01.76#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.259.07:42:01.76#ibcon#enter wrdev, iclass 14, count 0 2006.259.07:42:01.76#ibcon#first serial, iclass 14, count 0 2006.259.07:42:01.76#ibcon#enter sib2, iclass 14, count 0 2006.259.07:42:01.76#ibcon#flushed, iclass 14, count 0 2006.259.07:42:01.76#ibcon#about to write, iclass 14, count 0 2006.259.07:42:01.76#ibcon#wrote, iclass 14, count 0 2006.259.07:42:01.76#ibcon#about to read 3, iclass 14, count 0 2006.259.07:42:01.78#ibcon#read 3, iclass 14, count 0 2006.259.07:42:01.78#ibcon#about to read 4, iclass 14, count 0 2006.259.07:42:01.78#ibcon#read 4, iclass 14, count 0 2006.259.07:42:01.78#ibcon#about to read 5, iclass 14, count 0 2006.259.07:42:01.78#ibcon#read 5, iclass 14, count 0 2006.259.07:42:01.78#ibcon#about to read 6, iclass 14, count 0 2006.259.07:42:01.78#ibcon#read 6, iclass 14, count 0 2006.259.07:42:01.78#ibcon#end of sib2, iclass 14, count 0 2006.259.07:42:01.78#ibcon#*mode == 0, iclass 14, count 0 2006.259.07:42:01.78#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.259.07:42:01.78#ibcon#[26=FRQ=01,532.99\r\n] 2006.259.07:42:01.78#ibcon#*before write, iclass 14, count 0 2006.259.07:42:01.78#ibcon#enter sib2, iclass 14, count 0 2006.259.07:42:01.78#ibcon#flushed, iclass 14, count 0 2006.259.07:42:01.78#ibcon#about to write, iclass 14, count 0 2006.259.07:42:01.78#ibcon#wrote, iclass 14, count 0 2006.259.07:42:01.78#ibcon#about to read 3, iclass 14, count 0 2006.259.07:42:01.83#ibcon#read 3, iclass 14, count 0 2006.259.07:42:01.83#ibcon#about to read 4, iclass 14, count 0 2006.259.07:42:01.83#ibcon#read 4, iclass 14, count 0 2006.259.07:42:01.83#ibcon#about to read 5, iclass 14, count 0 2006.259.07:42:01.83#ibcon#read 5, iclass 14, count 0 2006.259.07:42:01.83#ibcon#about to read 6, iclass 14, count 0 2006.259.07:42:01.83#ibcon#read 6, iclass 14, count 0 2006.259.07:42:01.83#ibcon#end of sib2, iclass 14, count 0 2006.259.07:42:01.83#ibcon#*after write, iclass 14, count 0 2006.259.07:42:01.83#ibcon#*before return 0, iclass 14, count 0 2006.259.07:42:01.83#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.259.07:42:01.83#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.259.07:42:01.83#ibcon#about to clear, iclass 14 cls_cnt 0 2006.259.07:42:01.83#ibcon#cleared, iclass 14 cls_cnt 0 2006.259.07:42:01.83$vc4f8/va=1,8 2006.259.07:42:01.83#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.259.07:42:01.83#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.259.07:42:01.83#ibcon#ireg 11 cls_cnt 2 2006.259.07:42:01.83#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.259.07:42:01.83#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.259.07:42:01.83#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.259.07:42:01.83#ibcon#enter wrdev, iclass 16, count 2 2006.259.07:42:01.83#ibcon#first serial, iclass 16, count 2 2006.259.07:42:01.83#ibcon#enter sib2, iclass 16, count 2 2006.259.07:42:01.83#ibcon#flushed, iclass 16, count 2 2006.259.07:42:01.83#ibcon#about to write, iclass 16, count 2 2006.259.07:42:01.83#ibcon#wrote, iclass 16, count 2 2006.259.07:42:01.83#ibcon#about to read 3, iclass 16, count 2 2006.259.07:42:01.85#ibcon#read 3, iclass 16, count 2 2006.259.07:42:01.85#ibcon#about to read 4, iclass 16, count 2 2006.259.07:42:01.85#ibcon#read 4, iclass 16, count 2 2006.259.07:42:01.85#ibcon#about to read 5, iclass 16, count 2 2006.259.07:42:01.85#ibcon#read 5, iclass 16, count 2 2006.259.07:42:01.85#ibcon#about to read 6, iclass 16, count 2 2006.259.07:42:01.85#ibcon#read 6, iclass 16, count 2 2006.259.07:42:01.85#ibcon#end of sib2, iclass 16, count 2 2006.259.07:42:01.85#ibcon#*mode == 0, iclass 16, count 2 2006.259.07:42:01.85#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.259.07:42:01.85#ibcon#[25=AT01-08\r\n] 2006.259.07:42:01.85#ibcon#*before write, iclass 16, count 2 2006.259.07:42:01.85#ibcon#enter sib2, iclass 16, count 2 2006.259.07:42:01.85#ibcon#flushed, iclass 16, count 2 2006.259.07:42:01.85#ibcon#about to write, iclass 16, count 2 2006.259.07:42:01.85#ibcon#wrote, iclass 16, count 2 2006.259.07:42:01.85#ibcon#about to read 3, iclass 16, count 2 2006.259.07:42:01.88#ibcon#read 3, iclass 16, count 2 2006.259.07:42:01.88#ibcon#about to read 4, iclass 16, count 2 2006.259.07:42:01.88#ibcon#read 4, iclass 16, count 2 2006.259.07:42:01.88#ibcon#about to read 5, iclass 16, count 2 2006.259.07:42:01.88#ibcon#read 5, iclass 16, count 2 2006.259.07:42:01.88#ibcon#about to read 6, iclass 16, count 2 2006.259.07:42:01.88#ibcon#read 6, iclass 16, count 2 2006.259.07:42:01.88#ibcon#end of sib2, iclass 16, count 2 2006.259.07:42:01.88#ibcon#*after write, iclass 16, count 2 2006.259.07:42:01.88#ibcon#*before return 0, iclass 16, count 2 2006.259.07:42:01.88#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.259.07:42:01.88#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.259.07:42:01.88#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.259.07:42:01.88#ibcon#ireg 7 cls_cnt 0 2006.259.07:42:01.88#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.259.07:42:02.00#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.259.07:42:02.00#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.259.07:42:02.00#ibcon#enter wrdev, iclass 16, count 0 2006.259.07:42:02.00#ibcon#first serial, iclass 16, count 0 2006.259.07:42:02.00#ibcon#enter sib2, iclass 16, count 0 2006.259.07:42:02.00#ibcon#flushed, iclass 16, count 0 2006.259.07:42:02.00#ibcon#about to write, iclass 16, count 0 2006.259.07:42:02.00#ibcon#wrote, iclass 16, count 0 2006.259.07:42:02.00#ibcon#about to read 3, iclass 16, count 0 2006.259.07:42:02.02#ibcon#read 3, iclass 16, count 0 2006.259.07:42:02.02#ibcon#about to read 4, iclass 16, count 0 2006.259.07:42:02.02#ibcon#read 4, iclass 16, count 0 2006.259.07:42:02.02#ibcon#about to read 5, iclass 16, count 0 2006.259.07:42:02.02#ibcon#read 5, iclass 16, count 0 2006.259.07:42:02.02#ibcon#about to read 6, iclass 16, count 0 2006.259.07:42:02.02#ibcon#read 6, iclass 16, count 0 2006.259.07:42:02.02#ibcon#end of sib2, iclass 16, count 0 2006.259.07:42:02.02#ibcon#*mode == 0, iclass 16, count 0 2006.259.07:42:02.02#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.259.07:42:02.02#ibcon#[25=USB\r\n] 2006.259.07:42:02.02#ibcon#*before write, iclass 16, count 0 2006.259.07:42:02.02#ibcon#enter sib2, iclass 16, count 0 2006.259.07:42:02.02#ibcon#flushed, iclass 16, count 0 2006.259.07:42:02.02#ibcon#about to write, iclass 16, count 0 2006.259.07:42:02.02#ibcon#wrote, iclass 16, count 0 2006.259.07:42:02.02#ibcon#about to read 3, iclass 16, count 0 2006.259.07:42:02.05#ibcon#read 3, iclass 16, count 0 2006.259.07:42:02.05#ibcon#about to read 4, iclass 16, count 0 2006.259.07:42:02.05#ibcon#read 4, iclass 16, count 0 2006.259.07:42:02.05#ibcon#about to read 5, iclass 16, count 0 2006.259.07:42:02.05#ibcon#read 5, iclass 16, count 0 2006.259.07:42:02.05#ibcon#about to read 6, iclass 16, count 0 2006.259.07:42:02.05#ibcon#read 6, iclass 16, count 0 2006.259.07:42:02.05#ibcon#end of sib2, iclass 16, count 0 2006.259.07:42:02.05#ibcon#*after write, iclass 16, count 0 2006.259.07:42:02.05#ibcon#*before return 0, iclass 16, count 0 2006.259.07:42:02.05#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.259.07:42:02.05#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.259.07:42:02.05#ibcon#about to clear, iclass 16 cls_cnt 0 2006.259.07:42:02.05#ibcon#cleared, iclass 16 cls_cnt 0 2006.259.07:42:02.05$vc4f8/valo=2,572.99 2006.259.07:42:02.05#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.259.07:42:02.05#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.259.07:42:02.05#ibcon#ireg 17 cls_cnt 0 2006.259.07:42:02.05#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.259.07:42:02.05#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.259.07:42:02.05#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.259.07:42:02.05#ibcon#enter wrdev, iclass 18, count 0 2006.259.07:42:02.05#ibcon#first serial, iclass 18, count 0 2006.259.07:42:02.05#ibcon#enter sib2, iclass 18, count 0 2006.259.07:42:02.05#ibcon#flushed, iclass 18, count 0 2006.259.07:42:02.05#ibcon#about to write, iclass 18, count 0 2006.259.07:42:02.05#ibcon#wrote, iclass 18, count 0 2006.259.07:42:02.05#ibcon#about to read 3, iclass 18, count 0 2006.259.07:42:02.07#ibcon#read 3, iclass 18, count 0 2006.259.07:42:02.07#ibcon#about to read 4, iclass 18, count 0 2006.259.07:42:02.07#ibcon#read 4, iclass 18, count 0 2006.259.07:42:02.07#ibcon#about to read 5, iclass 18, count 0 2006.259.07:42:02.07#ibcon#read 5, iclass 18, count 0 2006.259.07:42:02.07#ibcon#about to read 6, iclass 18, count 0 2006.259.07:42:02.07#ibcon#read 6, iclass 18, count 0 2006.259.07:42:02.07#ibcon#end of sib2, iclass 18, count 0 2006.259.07:42:02.07#ibcon#*mode == 0, iclass 18, count 0 2006.259.07:42:02.07#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.259.07:42:02.07#ibcon#[26=FRQ=02,572.99\r\n] 2006.259.07:42:02.07#ibcon#*before write, iclass 18, count 0 2006.259.07:42:02.07#ibcon#enter sib2, iclass 18, count 0 2006.259.07:42:02.07#ibcon#flushed, iclass 18, count 0 2006.259.07:42:02.07#ibcon#about to write, iclass 18, count 0 2006.259.07:42:02.07#ibcon#wrote, iclass 18, count 0 2006.259.07:42:02.07#ibcon#about to read 3, iclass 18, count 0 2006.259.07:42:02.11#ibcon#read 3, iclass 18, count 0 2006.259.07:42:02.11#ibcon#about to read 4, iclass 18, count 0 2006.259.07:42:02.11#ibcon#read 4, iclass 18, count 0 2006.259.07:42:02.11#ibcon#about to read 5, iclass 18, count 0 2006.259.07:42:02.11#ibcon#read 5, iclass 18, count 0 2006.259.07:42:02.11#ibcon#about to read 6, iclass 18, count 0 2006.259.07:42:02.11#ibcon#read 6, iclass 18, count 0 2006.259.07:42:02.11#ibcon#end of sib2, iclass 18, count 0 2006.259.07:42:02.11#ibcon#*after write, iclass 18, count 0 2006.259.07:42:02.11#ibcon#*before return 0, iclass 18, count 0 2006.259.07:42:02.11#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.259.07:42:02.11#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.259.07:42:02.11#ibcon#about to clear, iclass 18 cls_cnt 0 2006.259.07:42:02.11#ibcon#cleared, iclass 18 cls_cnt 0 2006.259.07:42:02.11$vc4f8/va=2,7 2006.259.07:42:02.11#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.259.07:42:02.11#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.259.07:42:02.11#ibcon#ireg 11 cls_cnt 2 2006.259.07:42:02.11#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.259.07:42:02.17#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.259.07:42:02.17#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.259.07:42:02.17#ibcon#enter wrdev, iclass 20, count 2 2006.259.07:42:02.17#ibcon#first serial, iclass 20, count 2 2006.259.07:42:02.17#ibcon#enter sib2, iclass 20, count 2 2006.259.07:42:02.17#ibcon#flushed, iclass 20, count 2 2006.259.07:42:02.17#ibcon#about to write, iclass 20, count 2 2006.259.07:42:02.17#ibcon#wrote, iclass 20, count 2 2006.259.07:42:02.17#ibcon#about to read 3, iclass 20, count 2 2006.259.07:42:02.19#ibcon#read 3, iclass 20, count 2 2006.259.07:42:02.19#ibcon#about to read 4, iclass 20, count 2 2006.259.07:42:02.19#ibcon#read 4, iclass 20, count 2 2006.259.07:42:02.19#ibcon#about to read 5, iclass 20, count 2 2006.259.07:42:02.19#ibcon#read 5, iclass 20, count 2 2006.259.07:42:02.19#ibcon#about to read 6, iclass 20, count 2 2006.259.07:42:02.19#ibcon#read 6, iclass 20, count 2 2006.259.07:42:02.19#ibcon#end of sib2, iclass 20, count 2 2006.259.07:42:02.19#ibcon#*mode == 0, iclass 20, count 2 2006.259.07:42:02.19#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.259.07:42:02.19#ibcon#[25=AT02-07\r\n] 2006.259.07:42:02.19#ibcon#*before write, iclass 20, count 2 2006.259.07:42:02.19#ibcon#enter sib2, iclass 20, count 2 2006.259.07:42:02.19#ibcon#flushed, iclass 20, count 2 2006.259.07:42:02.19#ibcon#about to write, iclass 20, count 2 2006.259.07:42:02.19#ibcon#wrote, iclass 20, count 2 2006.259.07:42:02.19#ibcon#about to read 3, iclass 20, count 2 2006.259.07:42:02.22#ibcon#read 3, iclass 20, count 2 2006.259.07:42:02.22#ibcon#about to read 4, iclass 20, count 2 2006.259.07:42:02.22#ibcon#read 4, iclass 20, count 2 2006.259.07:42:02.22#ibcon#about to read 5, iclass 20, count 2 2006.259.07:42:02.22#ibcon#read 5, iclass 20, count 2 2006.259.07:42:02.22#ibcon#about to read 6, iclass 20, count 2 2006.259.07:42:02.22#ibcon#read 6, iclass 20, count 2 2006.259.07:42:02.22#ibcon#end of sib2, iclass 20, count 2 2006.259.07:42:02.22#ibcon#*after write, iclass 20, count 2 2006.259.07:42:02.22#ibcon#*before return 0, iclass 20, count 2 2006.259.07:42:02.22#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.259.07:42:02.22#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.259.07:42:02.22#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.259.07:42:02.22#ibcon#ireg 7 cls_cnt 0 2006.259.07:42:02.22#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.259.07:42:02.34#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.259.07:42:02.34#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.259.07:42:02.34#ibcon#enter wrdev, iclass 20, count 0 2006.259.07:42:02.34#ibcon#first serial, iclass 20, count 0 2006.259.07:42:02.34#ibcon#enter sib2, iclass 20, count 0 2006.259.07:42:02.34#ibcon#flushed, iclass 20, count 0 2006.259.07:42:02.34#ibcon#about to write, iclass 20, count 0 2006.259.07:42:02.34#ibcon#wrote, iclass 20, count 0 2006.259.07:42:02.34#ibcon#about to read 3, iclass 20, count 0 2006.259.07:42:02.36#ibcon#read 3, iclass 20, count 0 2006.259.07:42:02.36#ibcon#about to read 4, iclass 20, count 0 2006.259.07:42:02.36#ibcon#read 4, iclass 20, count 0 2006.259.07:42:02.36#ibcon#about to read 5, iclass 20, count 0 2006.259.07:42:02.36#ibcon#read 5, iclass 20, count 0 2006.259.07:42:02.36#ibcon#about to read 6, iclass 20, count 0 2006.259.07:42:02.36#ibcon#read 6, iclass 20, count 0 2006.259.07:42:02.36#ibcon#end of sib2, iclass 20, count 0 2006.259.07:42:02.36#ibcon#*mode == 0, iclass 20, count 0 2006.259.07:42:02.36#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.259.07:42:02.36#ibcon#[25=USB\r\n] 2006.259.07:42:02.36#ibcon#*before write, iclass 20, count 0 2006.259.07:42:02.36#ibcon#enter sib2, iclass 20, count 0 2006.259.07:42:02.36#ibcon#flushed, iclass 20, count 0 2006.259.07:42:02.36#ibcon#about to write, iclass 20, count 0 2006.259.07:42:02.36#ibcon#wrote, iclass 20, count 0 2006.259.07:42:02.36#ibcon#about to read 3, iclass 20, count 0 2006.259.07:42:02.39#ibcon#read 3, iclass 20, count 0 2006.259.07:42:02.39#ibcon#about to read 4, iclass 20, count 0 2006.259.07:42:02.39#ibcon#read 4, iclass 20, count 0 2006.259.07:42:02.39#ibcon#about to read 5, iclass 20, count 0 2006.259.07:42:02.39#ibcon#read 5, iclass 20, count 0 2006.259.07:42:02.39#ibcon#about to read 6, iclass 20, count 0 2006.259.07:42:02.39#ibcon#read 6, iclass 20, count 0 2006.259.07:42:02.39#ibcon#end of sib2, iclass 20, count 0 2006.259.07:42:02.39#ibcon#*after write, iclass 20, count 0 2006.259.07:42:02.39#ibcon#*before return 0, iclass 20, count 0 2006.259.07:42:02.39#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.259.07:42:02.39#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.259.07:42:02.39#ibcon#about to clear, iclass 20 cls_cnt 0 2006.259.07:42:02.39#ibcon#cleared, iclass 20 cls_cnt 0 2006.259.07:42:02.39$vc4f8/valo=3,672.99 2006.259.07:42:02.39#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.259.07:42:02.39#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.259.07:42:02.39#ibcon#ireg 17 cls_cnt 0 2006.259.07:42:02.39#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.259.07:42:02.39#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.259.07:42:02.39#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.259.07:42:02.39#ibcon#enter wrdev, iclass 22, count 0 2006.259.07:42:02.39#ibcon#first serial, iclass 22, count 0 2006.259.07:42:02.39#ibcon#enter sib2, iclass 22, count 0 2006.259.07:42:02.39#ibcon#flushed, iclass 22, count 0 2006.259.07:42:02.39#ibcon#about to write, iclass 22, count 0 2006.259.07:42:02.39#ibcon#wrote, iclass 22, count 0 2006.259.07:42:02.39#ibcon#about to read 3, iclass 22, count 0 2006.259.07:42:02.41#ibcon#read 3, iclass 22, count 0 2006.259.07:42:02.41#ibcon#about to read 4, iclass 22, count 0 2006.259.07:42:02.41#ibcon#read 4, iclass 22, count 0 2006.259.07:42:02.41#ibcon#about to read 5, iclass 22, count 0 2006.259.07:42:02.41#ibcon#read 5, iclass 22, count 0 2006.259.07:42:02.41#ibcon#about to read 6, iclass 22, count 0 2006.259.07:42:02.41#ibcon#read 6, iclass 22, count 0 2006.259.07:42:02.41#ibcon#end of sib2, iclass 22, count 0 2006.259.07:42:02.41#ibcon#*mode == 0, iclass 22, count 0 2006.259.07:42:02.41#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.259.07:42:02.41#ibcon#[26=FRQ=03,672.99\r\n] 2006.259.07:42:02.41#ibcon#*before write, iclass 22, count 0 2006.259.07:42:02.41#ibcon#enter sib2, iclass 22, count 0 2006.259.07:42:02.41#ibcon#flushed, iclass 22, count 0 2006.259.07:42:02.41#ibcon#about to write, iclass 22, count 0 2006.259.07:42:02.41#ibcon#wrote, iclass 22, count 0 2006.259.07:42:02.41#ibcon#about to read 3, iclass 22, count 0 2006.259.07:42:02.45#ibcon#read 3, iclass 22, count 0 2006.259.07:42:02.45#ibcon#about to read 4, iclass 22, count 0 2006.259.07:42:02.45#ibcon#read 4, iclass 22, count 0 2006.259.07:42:02.45#ibcon#about to read 5, iclass 22, count 0 2006.259.07:42:02.45#ibcon#read 5, iclass 22, count 0 2006.259.07:42:02.45#ibcon#about to read 6, iclass 22, count 0 2006.259.07:42:02.45#ibcon#read 6, iclass 22, count 0 2006.259.07:42:02.45#ibcon#end of sib2, iclass 22, count 0 2006.259.07:42:02.45#ibcon#*after write, iclass 22, count 0 2006.259.07:42:02.45#ibcon#*before return 0, iclass 22, count 0 2006.259.07:42:02.45#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.259.07:42:02.45#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.259.07:42:02.45#ibcon#about to clear, iclass 22 cls_cnt 0 2006.259.07:42:02.45#ibcon#cleared, iclass 22 cls_cnt 0 2006.259.07:42:02.45$vc4f8/va=3,8 2006.259.07:42:02.45#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.259.07:42:02.45#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.259.07:42:02.45#ibcon#ireg 11 cls_cnt 2 2006.259.07:42:02.45#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.259.07:42:02.51#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.259.07:42:02.51#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.259.07:42:02.51#ibcon#enter wrdev, iclass 24, count 2 2006.259.07:42:02.51#ibcon#first serial, iclass 24, count 2 2006.259.07:42:02.51#ibcon#enter sib2, iclass 24, count 2 2006.259.07:42:02.51#ibcon#flushed, iclass 24, count 2 2006.259.07:42:02.51#ibcon#about to write, iclass 24, count 2 2006.259.07:42:02.51#ibcon#wrote, iclass 24, count 2 2006.259.07:42:02.51#ibcon#about to read 3, iclass 24, count 2 2006.259.07:42:02.54#ibcon#read 3, iclass 24, count 2 2006.259.07:42:02.54#ibcon#about to read 4, iclass 24, count 2 2006.259.07:42:02.54#ibcon#read 4, iclass 24, count 2 2006.259.07:42:02.54#ibcon#about to read 5, iclass 24, count 2 2006.259.07:42:02.54#ibcon#read 5, iclass 24, count 2 2006.259.07:42:02.54#ibcon#about to read 6, iclass 24, count 2 2006.259.07:42:02.54#ibcon#read 6, iclass 24, count 2 2006.259.07:42:02.54#ibcon#end of sib2, iclass 24, count 2 2006.259.07:42:02.54#ibcon#*mode == 0, iclass 24, count 2 2006.259.07:42:02.54#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.259.07:42:02.54#ibcon#[25=AT03-08\r\n] 2006.259.07:42:02.54#ibcon#*before write, iclass 24, count 2 2006.259.07:42:02.54#ibcon#enter sib2, iclass 24, count 2 2006.259.07:42:02.54#ibcon#flushed, iclass 24, count 2 2006.259.07:42:02.54#ibcon#about to write, iclass 24, count 2 2006.259.07:42:02.54#ibcon#wrote, iclass 24, count 2 2006.259.07:42:02.54#ibcon#about to read 3, iclass 24, count 2 2006.259.07:42:02.57#ibcon#read 3, iclass 24, count 2 2006.259.07:42:02.57#ibcon#about to read 4, iclass 24, count 2 2006.259.07:42:02.57#ibcon#read 4, iclass 24, count 2 2006.259.07:42:02.57#ibcon#about to read 5, iclass 24, count 2 2006.259.07:42:02.57#ibcon#read 5, iclass 24, count 2 2006.259.07:42:02.57#ibcon#about to read 6, iclass 24, count 2 2006.259.07:42:02.57#ibcon#read 6, iclass 24, count 2 2006.259.07:42:02.57#ibcon#end of sib2, iclass 24, count 2 2006.259.07:42:02.57#ibcon#*after write, iclass 24, count 2 2006.259.07:42:02.57#ibcon#*before return 0, iclass 24, count 2 2006.259.07:42:02.57#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.259.07:42:02.57#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.259.07:42:02.57#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.259.07:42:02.57#ibcon#ireg 7 cls_cnt 0 2006.259.07:42:02.57#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.259.07:42:02.69#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.259.07:42:02.69#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.259.07:42:02.69#ibcon#enter wrdev, iclass 24, count 0 2006.259.07:42:02.69#ibcon#first serial, iclass 24, count 0 2006.259.07:42:02.69#ibcon#enter sib2, iclass 24, count 0 2006.259.07:42:02.69#ibcon#flushed, iclass 24, count 0 2006.259.07:42:02.69#ibcon#about to write, iclass 24, count 0 2006.259.07:42:02.69#ibcon#wrote, iclass 24, count 0 2006.259.07:42:02.69#ibcon#about to read 3, iclass 24, count 0 2006.259.07:42:02.71#ibcon#read 3, iclass 24, count 0 2006.259.07:42:02.71#ibcon#about to read 4, iclass 24, count 0 2006.259.07:42:02.71#ibcon#read 4, iclass 24, count 0 2006.259.07:42:02.71#ibcon#about to read 5, iclass 24, count 0 2006.259.07:42:02.71#ibcon#read 5, iclass 24, count 0 2006.259.07:42:02.71#ibcon#about to read 6, iclass 24, count 0 2006.259.07:42:02.71#ibcon#read 6, iclass 24, count 0 2006.259.07:42:02.71#ibcon#end of sib2, iclass 24, count 0 2006.259.07:42:02.71#ibcon#*mode == 0, iclass 24, count 0 2006.259.07:42:02.71#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.259.07:42:02.71#ibcon#[25=USB\r\n] 2006.259.07:42:02.71#ibcon#*before write, iclass 24, count 0 2006.259.07:42:02.71#ibcon#enter sib2, iclass 24, count 0 2006.259.07:42:02.71#ibcon#flushed, iclass 24, count 0 2006.259.07:42:02.71#ibcon#about to write, iclass 24, count 0 2006.259.07:42:02.71#ibcon#wrote, iclass 24, count 0 2006.259.07:42:02.71#ibcon#about to read 3, iclass 24, count 0 2006.259.07:42:02.74#ibcon#read 3, iclass 24, count 0 2006.259.07:42:02.74#ibcon#about to read 4, iclass 24, count 0 2006.259.07:42:02.74#ibcon#read 4, iclass 24, count 0 2006.259.07:42:02.74#ibcon#about to read 5, iclass 24, count 0 2006.259.07:42:02.74#ibcon#read 5, iclass 24, count 0 2006.259.07:42:02.74#ibcon#about to read 6, iclass 24, count 0 2006.259.07:42:02.74#ibcon#read 6, iclass 24, count 0 2006.259.07:42:02.74#ibcon#end of sib2, iclass 24, count 0 2006.259.07:42:02.74#ibcon#*after write, iclass 24, count 0 2006.259.07:42:02.74#ibcon#*before return 0, iclass 24, count 0 2006.259.07:42:02.74#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.259.07:42:02.74#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.259.07:42:02.74#ibcon#about to clear, iclass 24 cls_cnt 0 2006.259.07:42:02.74#ibcon#cleared, iclass 24 cls_cnt 0 2006.259.07:42:02.74$vc4f8/valo=4,832.99 2006.259.07:42:02.74#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.259.07:42:02.74#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.259.07:42:02.74#ibcon#ireg 17 cls_cnt 0 2006.259.07:42:02.74#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.259.07:42:02.74#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.259.07:42:02.74#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.259.07:42:02.74#ibcon#enter wrdev, iclass 26, count 0 2006.259.07:42:02.74#ibcon#first serial, iclass 26, count 0 2006.259.07:42:02.74#ibcon#enter sib2, iclass 26, count 0 2006.259.07:42:02.74#ibcon#flushed, iclass 26, count 0 2006.259.07:42:02.74#ibcon#about to write, iclass 26, count 0 2006.259.07:42:02.74#ibcon#wrote, iclass 26, count 0 2006.259.07:42:02.74#ibcon#about to read 3, iclass 26, count 0 2006.259.07:42:02.76#ibcon#read 3, iclass 26, count 0 2006.259.07:42:02.76#ibcon#about to read 4, iclass 26, count 0 2006.259.07:42:02.76#ibcon#read 4, iclass 26, count 0 2006.259.07:42:02.76#ibcon#about to read 5, iclass 26, count 0 2006.259.07:42:02.76#ibcon#read 5, iclass 26, count 0 2006.259.07:42:02.76#ibcon#about to read 6, iclass 26, count 0 2006.259.07:42:02.76#ibcon#read 6, iclass 26, count 0 2006.259.07:42:02.76#ibcon#end of sib2, iclass 26, count 0 2006.259.07:42:02.76#ibcon#*mode == 0, iclass 26, count 0 2006.259.07:42:02.76#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.259.07:42:02.76#ibcon#[26=FRQ=04,832.99\r\n] 2006.259.07:42:02.76#ibcon#*before write, iclass 26, count 0 2006.259.07:42:02.76#ibcon#enter sib2, iclass 26, count 0 2006.259.07:42:02.76#ibcon#flushed, iclass 26, count 0 2006.259.07:42:02.76#ibcon#about to write, iclass 26, count 0 2006.259.07:42:02.76#ibcon#wrote, iclass 26, count 0 2006.259.07:42:02.76#ibcon#about to read 3, iclass 26, count 0 2006.259.07:42:02.80#ibcon#read 3, iclass 26, count 0 2006.259.07:42:02.80#ibcon#about to read 4, iclass 26, count 0 2006.259.07:42:02.80#ibcon#read 4, iclass 26, count 0 2006.259.07:42:02.80#ibcon#about to read 5, iclass 26, count 0 2006.259.07:42:02.80#ibcon#read 5, iclass 26, count 0 2006.259.07:42:02.80#ibcon#about to read 6, iclass 26, count 0 2006.259.07:42:02.80#ibcon#read 6, iclass 26, count 0 2006.259.07:42:02.80#ibcon#end of sib2, iclass 26, count 0 2006.259.07:42:02.80#ibcon#*after write, iclass 26, count 0 2006.259.07:42:02.80#ibcon#*before return 0, iclass 26, count 0 2006.259.07:42:02.80#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.259.07:42:02.80#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.259.07:42:02.80#ibcon#about to clear, iclass 26 cls_cnt 0 2006.259.07:42:02.80#ibcon#cleared, iclass 26 cls_cnt 0 2006.259.07:42:02.80$vc4f8/va=4,7 2006.259.07:42:02.80#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.259.07:42:02.80#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.259.07:42:02.80#ibcon#ireg 11 cls_cnt 2 2006.259.07:42:02.80#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.259.07:42:02.86#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.259.07:42:02.86#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.259.07:42:02.86#ibcon#enter wrdev, iclass 28, count 2 2006.259.07:42:02.86#ibcon#first serial, iclass 28, count 2 2006.259.07:42:02.86#ibcon#enter sib2, iclass 28, count 2 2006.259.07:42:02.86#ibcon#flushed, iclass 28, count 2 2006.259.07:42:02.86#ibcon#about to write, iclass 28, count 2 2006.259.07:42:02.86#ibcon#wrote, iclass 28, count 2 2006.259.07:42:02.86#ibcon#about to read 3, iclass 28, count 2 2006.259.07:42:02.88#ibcon#read 3, iclass 28, count 2 2006.259.07:42:02.88#ibcon#about to read 4, iclass 28, count 2 2006.259.07:42:02.88#ibcon#read 4, iclass 28, count 2 2006.259.07:42:02.88#ibcon#about to read 5, iclass 28, count 2 2006.259.07:42:02.88#ibcon#read 5, iclass 28, count 2 2006.259.07:42:02.88#ibcon#about to read 6, iclass 28, count 2 2006.259.07:42:02.88#ibcon#read 6, iclass 28, count 2 2006.259.07:42:02.88#ibcon#end of sib2, iclass 28, count 2 2006.259.07:42:02.88#ibcon#*mode == 0, iclass 28, count 2 2006.259.07:42:02.88#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.259.07:42:02.88#ibcon#[25=AT04-07\r\n] 2006.259.07:42:02.88#ibcon#*before write, iclass 28, count 2 2006.259.07:42:02.88#ibcon#enter sib2, iclass 28, count 2 2006.259.07:42:02.88#ibcon#flushed, iclass 28, count 2 2006.259.07:42:02.88#ibcon#about to write, iclass 28, count 2 2006.259.07:42:02.88#ibcon#wrote, iclass 28, count 2 2006.259.07:42:02.88#ibcon#about to read 3, iclass 28, count 2 2006.259.07:42:02.91#ibcon#read 3, iclass 28, count 2 2006.259.07:42:02.91#ibcon#about to read 4, iclass 28, count 2 2006.259.07:42:02.91#ibcon#read 4, iclass 28, count 2 2006.259.07:42:02.91#ibcon#about to read 5, iclass 28, count 2 2006.259.07:42:02.91#ibcon#read 5, iclass 28, count 2 2006.259.07:42:02.91#ibcon#about to read 6, iclass 28, count 2 2006.259.07:42:02.91#ibcon#read 6, iclass 28, count 2 2006.259.07:42:02.91#ibcon#end of sib2, iclass 28, count 2 2006.259.07:42:02.91#ibcon#*after write, iclass 28, count 2 2006.259.07:42:02.91#ibcon#*before return 0, iclass 28, count 2 2006.259.07:42:02.91#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.259.07:42:02.91#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.259.07:42:02.91#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.259.07:42:02.91#ibcon#ireg 7 cls_cnt 0 2006.259.07:42:02.91#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.259.07:42:03.03#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.259.07:42:03.03#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.259.07:42:03.03#ibcon#enter wrdev, iclass 28, count 0 2006.259.07:42:03.03#ibcon#first serial, iclass 28, count 0 2006.259.07:42:03.03#ibcon#enter sib2, iclass 28, count 0 2006.259.07:42:03.03#ibcon#flushed, iclass 28, count 0 2006.259.07:42:03.03#ibcon#about to write, iclass 28, count 0 2006.259.07:42:03.03#ibcon#wrote, iclass 28, count 0 2006.259.07:42:03.03#ibcon#about to read 3, iclass 28, count 0 2006.259.07:42:03.05#ibcon#read 3, iclass 28, count 0 2006.259.07:42:03.05#ibcon#about to read 4, iclass 28, count 0 2006.259.07:42:03.05#ibcon#read 4, iclass 28, count 0 2006.259.07:42:03.05#ibcon#about to read 5, iclass 28, count 0 2006.259.07:42:03.05#ibcon#read 5, iclass 28, count 0 2006.259.07:42:03.05#ibcon#about to read 6, iclass 28, count 0 2006.259.07:42:03.05#ibcon#read 6, iclass 28, count 0 2006.259.07:42:03.05#ibcon#end of sib2, iclass 28, count 0 2006.259.07:42:03.05#ibcon#*mode == 0, iclass 28, count 0 2006.259.07:42:03.05#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.259.07:42:03.05#ibcon#[25=USB\r\n] 2006.259.07:42:03.05#ibcon#*before write, iclass 28, count 0 2006.259.07:42:03.05#ibcon#enter sib2, iclass 28, count 0 2006.259.07:42:03.05#ibcon#flushed, iclass 28, count 0 2006.259.07:42:03.05#ibcon#about to write, iclass 28, count 0 2006.259.07:42:03.05#ibcon#wrote, iclass 28, count 0 2006.259.07:42:03.05#ibcon#about to read 3, iclass 28, count 0 2006.259.07:42:03.08#ibcon#read 3, iclass 28, count 0 2006.259.07:42:03.08#ibcon#about to read 4, iclass 28, count 0 2006.259.07:42:03.08#ibcon#read 4, iclass 28, count 0 2006.259.07:42:03.08#ibcon#about to read 5, iclass 28, count 0 2006.259.07:42:03.08#ibcon#read 5, iclass 28, count 0 2006.259.07:42:03.08#ibcon#about to read 6, iclass 28, count 0 2006.259.07:42:03.08#ibcon#read 6, iclass 28, count 0 2006.259.07:42:03.08#ibcon#end of sib2, iclass 28, count 0 2006.259.07:42:03.08#ibcon#*after write, iclass 28, count 0 2006.259.07:42:03.08#ibcon#*before return 0, iclass 28, count 0 2006.259.07:42:03.08#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.259.07:42:03.08#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.259.07:42:03.08#ibcon#about to clear, iclass 28 cls_cnt 0 2006.259.07:42:03.08#ibcon#cleared, iclass 28 cls_cnt 0 2006.259.07:42:03.08$vc4f8/valo=5,652.99 2006.259.07:42:03.08#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.259.07:42:03.08#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.259.07:42:03.08#ibcon#ireg 17 cls_cnt 0 2006.259.07:42:03.08#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.259.07:42:03.08#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.259.07:42:03.08#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.259.07:42:03.08#ibcon#enter wrdev, iclass 30, count 0 2006.259.07:42:03.08#ibcon#first serial, iclass 30, count 0 2006.259.07:42:03.08#ibcon#enter sib2, iclass 30, count 0 2006.259.07:42:03.08#ibcon#flushed, iclass 30, count 0 2006.259.07:42:03.08#ibcon#about to write, iclass 30, count 0 2006.259.07:42:03.08#ibcon#wrote, iclass 30, count 0 2006.259.07:42:03.08#ibcon#about to read 3, iclass 30, count 0 2006.259.07:42:03.10#ibcon#read 3, iclass 30, count 0 2006.259.07:42:03.10#ibcon#about to read 4, iclass 30, count 0 2006.259.07:42:03.10#ibcon#read 4, iclass 30, count 0 2006.259.07:42:03.10#ibcon#about to read 5, iclass 30, count 0 2006.259.07:42:03.10#ibcon#read 5, iclass 30, count 0 2006.259.07:42:03.10#ibcon#about to read 6, iclass 30, count 0 2006.259.07:42:03.10#ibcon#read 6, iclass 30, count 0 2006.259.07:42:03.10#ibcon#end of sib2, iclass 30, count 0 2006.259.07:42:03.10#ibcon#*mode == 0, iclass 30, count 0 2006.259.07:42:03.10#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.259.07:42:03.10#ibcon#[26=FRQ=05,652.99\r\n] 2006.259.07:42:03.10#ibcon#*before write, iclass 30, count 0 2006.259.07:42:03.10#ibcon#enter sib2, iclass 30, count 0 2006.259.07:42:03.10#ibcon#flushed, iclass 30, count 0 2006.259.07:42:03.10#ibcon#about to write, iclass 30, count 0 2006.259.07:42:03.10#ibcon#wrote, iclass 30, count 0 2006.259.07:42:03.10#ibcon#about to read 3, iclass 30, count 0 2006.259.07:42:03.14#ibcon#read 3, iclass 30, count 0 2006.259.07:42:03.14#ibcon#about to read 4, iclass 30, count 0 2006.259.07:42:03.14#ibcon#read 4, iclass 30, count 0 2006.259.07:42:03.14#ibcon#about to read 5, iclass 30, count 0 2006.259.07:42:03.14#ibcon#read 5, iclass 30, count 0 2006.259.07:42:03.14#ibcon#about to read 6, iclass 30, count 0 2006.259.07:42:03.14#ibcon#read 6, iclass 30, count 0 2006.259.07:42:03.14#ibcon#end of sib2, iclass 30, count 0 2006.259.07:42:03.14#ibcon#*after write, iclass 30, count 0 2006.259.07:42:03.14#ibcon#*before return 0, iclass 30, count 0 2006.259.07:42:03.14#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.259.07:42:03.14#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.259.07:42:03.14#ibcon#about to clear, iclass 30 cls_cnt 0 2006.259.07:42:03.14#ibcon#cleared, iclass 30 cls_cnt 0 2006.259.07:42:03.14$vc4f8/va=5,7 2006.259.07:42:03.14#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.259.07:42:03.14#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.259.07:42:03.14#ibcon#ireg 11 cls_cnt 2 2006.259.07:42:03.14#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.259.07:42:03.20#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.259.07:42:03.20#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.259.07:42:03.20#ibcon#enter wrdev, iclass 32, count 2 2006.259.07:42:03.20#ibcon#first serial, iclass 32, count 2 2006.259.07:42:03.20#ibcon#enter sib2, iclass 32, count 2 2006.259.07:42:03.20#ibcon#flushed, iclass 32, count 2 2006.259.07:42:03.20#ibcon#about to write, iclass 32, count 2 2006.259.07:42:03.20#ibcon#wrote, iclass 32, count 2 2006.259.07:42:03.20#ibcon#about to read 3, iclass 32, count 2 2006.259.07:42:03.22#ibcon#read 3, iclass 32, count 2 2006.259.07:42:03.22#ibcon#about to read 4, iclass 32, count 2 2006.259.07:42:03.22#ibcon#read 4, iclass 32, count 2 2006.259.07:42:03.22#ibcon#about to read 5, iclass 32, count 2 2006.259.07:42:03.22#ibcon#read 5, iclass 32, count 2 2006.259.07:42:03.22#ibcon#about to read 6, iclass 32, count 2 2006.259.07:42:03.22#ibcon#read 6, iclass 32, count 2 2006.259.07:42:03.22#ibcon#end of sib2, iclass 32, count 2 2006.259.07:42:03.22#ibcon#*mode == 0, iclass 32, count 2 2006.259.07:42:03.22#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.259.07:42:03.22#ibcon#[25=AT05-07\r\n] 2006.259.07:42:03.22#ibcon#*before write, iclass 32, count 2 2006.259.07:42:03.22#ibcon#enter sib2, iclass 32, count 2 2006.259.07:42:03.22#ibcon#flushed, iclass 32, count 2 2006.259.07:42:03.22#ibcon#about to write, iclass 32, count 2 2006.259.07:42:03.22#ibcon#wrote, iclass 32, count 2 2006.259.07:42:03.22#ibcon#about to read 3, iclass 32, count 2 2006.259.07:42:03.25#ibcon#read 3, iclass 32, count 2 2006.259.07:42:03.25#ibcon#about to read 4, iclass 32, count 2 2006.259.07:42:03.25#ibcon#read 4, iclass 32, count 2 2006.259.07:42:03.25#ibcon#about to read 5, iclass 32, count 2 2006.259.07:42:03.25#ibcon#read 5, iclass 32, count 2 2006.259.07:42:03.25#ibcon#about to read 6, iclass 32, count 2 2006.259.07:42:03.25#ibcon#read 6, iclass 32, count 2 2006.259.07:42:03.25#ibcon#end of sib2, iclass 32, count 2 2006.259.07:42:03.25#ibcon#*after write, iclass 32, count 2 2006.259.07:42:03.25#ibcon#*before return 0, iclass 32, count 2 2006.259.07:42:03.25#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.259.07:42:03.25#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.259.07:42:03.25#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.259.07:42:03.25#ibcon#ireg 7 cls_cnt 0 2006.259.07:42:03.25#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.259.07:42:03.37#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.259.07:42:03.37#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.259.07:42:03.37#ibcon#enter wrdev, iclass 32, count 0 2006.259.07:42:03.37#ibcon#first serial, iclass 32, count 0 2006.259.07:42:03.37#ibcon#enter sib2, iclass 32, count 0 2006.259.07:42:03.37#ibcon#flushed, iclass 32, count 0 2006.259.07:42:03.37#ibcon#about to write, iclass 32, count 0 2006.259.07:42:03.37#ibcon#wrote, iclass 32, count 0 2006.259.07:42:03.37#ibcon#about to read 3, iclass 32, count 0 2006.259.07:42:03.39#ibcon#read 3, iclass 32, count 0 2006.259.07:42:03.39#ibcon#about to read 4, iclass 32, count 0 2006.259.07:42:03.39#ibcon#read 4, iclass 32, count 0 2006.259.07:42:03.39#ibcon#about to read 5, iclass 32, count 0 2006.259.07:42:03.39#ibcon#read 5, iclass 32, count 0 2006.259.07:42:03.39#ibcon#about to read 6, iclass 32, count 0 2006.259.07:42:03.39#ibcon#read 6, iclass 32, count 0 2006.259.07:42:03.39#ibcon#end of sib2, iclass 32, count 0 2006.259.07:42:03.39#ibcon#*mode == 0, iclass 32, count 0 2006.259.07:42:03.39#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.259.07:42:03.39#ibcon#[25=USB\r\n] 2006.259.07:42:03.39#ibcon#*before write, iclass 32, count 0 2006.259.07:42:03.39#ibcon#enter sib2, iclass 32, count 0 2006.259.07:42:03.39#ibcon#flushed, iclass 32, count 0 2006.259.07:42:03.39#ibcon#about to write, iclass 32, count 0 2006.259.07:42:03.39#ibcon#wrote, iclass 32, count 0 2006.259.07:42:03.39#ibcon#about to read 3, iclass 32, count 0 2006.259.07:42:03.43#ibcon#read 3, iclass 32, count 0 2006.259.07:42:03.43#ibcon#about to read 4, iclass 32, count 0 2006.259.07:42:03.43#ibcon#read 4, iclass 32, count 0 2006.259.07:42:03.43#ibcon#about to read 5, iclass 32, count 0 2006.259.07:42:03.43#ibcon#read 5, iclass 32, count 0 2006.259.07:42:03.43#ibcon#about to read 6, iclass 32, count 0 2006.259.07:42:03.43#ibcon#read 6, iclass 32, count 0 2006.259.07:42:03.43#ibcon#end of sib2, iclass 32, count 0 2006.259.07:42:03.43#ibcon#*after write, iclass 32, count 0 2006.259.07:42:03.43#ibcon#*before return 0, iclass 32, count 0 2006.259.07:42:03.43#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.259.07:42:03.43#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.259.07:42:03.43#ibcon#about to clear, iclass 32 cls_cnt 0 2006.259.07:42:03.43#ibcon#cleared, iclass 32 cls_cnt 0 2006.259.07:42:03.43$vc4f8/valo=6,772.99 2006.259.07:42:03.43#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.259.07:42:03.43#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.259.07:42:03.43#ibcon#ireg 17 cls_cnt 0 2006.259.07:42:03.43#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.259.07:42:03.43#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.259.07:42:03.43#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.259.07:42:03.43#ibcon#enter wrdev, iclass 34, count 0 2006.259.07:42:03.43#ibcon#first serial, iclass 34, count 0 2006.259.07:42:03.43#ibcon#enter sib2, iclass 34, count 0 2006.259.07:42:03.43#ibcon#flushed, iclass 34, count 0 2006.259.07:42:03.43#ibcon#about to write, iclass 34, count 0 2006.259.07:42:03.43#ibcon#wrote, iclass 34, count 0 2006.259.07:42:03.43#ibcon#about to read 3, iclass 34, count 0 2006.259.07:42:03.45#ibcon#read 3, iclass 34, count 0 2006.259.07:42:03.45#ibcon#about to read 4, iclass 34, count 0 2006.259.07:42:03.45#ibcon#read 4, iclass 34, count 0 2006.259.07:42:03.45#ibcon#about to read 5, iclass 34, count 0 2006.259.07:42:03.45#ibcon#read 5, iclass 34, count 0 2006.259.07:42:03.45#ibcon#about to read 6, iclass 34, count 0 2006.259.07:42:03.45#ibcon#read 6, iclass 34, count 0 2006.259.07:42:03.45#ibcon#end of sib2, iclass 34, count 0 2006.259.07:42:03.45#ibcon#*mode == 0, iclass 34, count 0 2006.259.07:42:03.45#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.259.07:42:03.45#ibcon#[26=FRQ=06,772.99\r\n] 2006.259.07:42:03.45#ibcon#*before write, iclass 34, count 0 2006.259.07:42:03.45#ibcon#enter sib2, iclass 34, count 0 2006.259.07:42:03.45#ibcon#flushed, iclass 34, count 0 2006.259.07:42:03.45#ibcon#about to write, iclass 34, count 0 2006.259.07:42:03.45#ibcon#wrote, iclass 34, count 0 2006.259.07:42:03.45#ibcon#about to read 3, iclass 34, count 0 2006.259.07:42:03.49#ibcon#read 3, iclass 34, count 0 2006.259.07:42:03.49#ibcon#about to read 4, iclass 34, count 0 2006.259.07:42:03.49#ibcon#read 4, iclass 34, count 0 2006.259.07:42:03.49#ibcon#about to read 5, iclass 34, count 0 2006.259.07:42:03.49#ibcon#read 5, iclass 34, count 0 2006.259.07:42:03.49#ibcon#about to read 6, iclass 34, count 0 2006.259.07:42:03.49#ibcon#read 6, iclass 34, count 0 2006.259.07:42:03.49#ibcon#end of sib2, iclass 34, count 0 2006.259.07:42:03.49#ibcon#*after write, iclass 34, count 0 2006.259.07:42:03.49#ibcon#*before return 0, iclass 34, count 0 2006.259.07:42:03.49#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.259.07:42:03.49#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.259.07:42:03.49#ibcon#about to clear, iclass 34 cls_cnt 0 2006.259.07:42:03.49#ibcon#cleared, iclass 34 cls_cnt 0 2006.259.07:42:03.49$vc4f8/va=6,6 2006.259.07:42:03.49#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.259.07:42:03.49#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.259.07:42:03.49#ibcon#ireg 11 cls_cnt 2 2006.259.07:42:03.49#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.259.07:42:03.55#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.259.07:42:03.55#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.259.07:42:03.55#ibcon#enter wrdev, iclass 36, count 2 2006.259.07:42:03.55#ibcon#first serial, iclass 36, count 2 2006.259.07:42:03.55#ibcon#enter sib2, iclass 36, count 2 2006.259.07:42:03.55#ibcon#flushed, iclass 36, count 2 2006.259.07:42:03.55#ibcon#about to write, iclass 36, count 2 2006.259.07:42:03.55#ibcon#wrote, iclass 36, count 2 2006.259.07:42:03.55#ibcon#about to read 3, iclass 36, count 2 2006.259.07:42:03.57#ibcon#read 3, iclass 36, count 2 2006.259.07:42:03.57#ibcon#about to read 4, iclass 36, count 2 2006.259.07:42:03.57#ibcon#read 4, iclass 36, count 2 2006.259.07:42:03.57#ibcon#about to read 5, iclass 36, count 2 2006.259.07:42:03.57#ibcon#read 5, iclass 36, count 2 2006.259.07:42:03.57#ibcon#about to read 6, iclass 36, count 2 2006.259.07:42:03.57#ibcon#read 6, iclass 36, count 2 2006.259.07:42:03.57#ibcon#end of sib2, iclass 36, count 2 2006.259.07:42:03.57#ibcon#*mode == 0, iclass 36, count 2 2006.259.07:42:03.57#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.259.07:42:03.57#ibcon#[25=AT06-06\r\n] 2006.259.07:42:03.57#ibcon#*before write, iclass 36, count 2 2006.259.07:42:03.57#ibcon#enter sib2, iclass 36, count 2 2006.259.07:42:03.57#ibcon#flushed, iclass 36, count 2 2006.259.07:42:03.57#ibcon#about to write, iclass 36, count 2 2006.259.07:42:03.57#ibcon#wrote, iclass 36, count 2 2006.259.07:42:03.57#ibcon#about to read 3, iclass 36, count 2 2006.259.07:42:03.60#ibcon#read 3, iclass 36, count 2 2006.259.07:42:03.60#ibcon#about to read 4, iclass 36, count 2 2006.259.07:42:03.60#ibcon#read 4, iclass 36, count 2 2006.259.07:42:03.60#ibcon#about to read 5, iclass 36, count 2 2006.259.07:42:03.60#ibcon#read 5, iclass 36, count 2 2006.259.07:42:03.60#ibcon#about to read 6, iclass 36, count 2 2006.259.07:42:03.60#ibcon#read 6, iclass 36, count 2 2006.259.07:42:03.60#ibcon#end of sib2, iclass 36, count 2 2006.259.07:42:03.60#ibcon#*after write, iclass 36, count 2 2006.259.07:42:03.60#ibcon#*before return 0, iclass 36, count 2 2006.259.07:42:03.60#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.259.07:42:03.60#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.259.07:42:03.60#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.259.07:42:03.60#ibcon#ireg 7 cls_cnt 0 2006.259.07:42:03.60#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.259.07:42:03.72#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.259.07:42:03.72#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.259.07:42:03.72#ibcon#enter wrdev, iclass 36, count 0 2006.259.07:42:03.72#ibcon#first serial, iclass 36, count 0 2006.259.07:42:03.72#ibcon#enter sib2, iclass 36, count 0 2006.259.07:42:03.72#ibcon#flushed, iclass 36, count 0 2006.259.07:42:03.72#ibcon#about to write, iclass 36, count 0 2006.259.07:42:03.72#ibcon#wrote, iclass 36, count 0 2006.259.07:42:03.72#ibcon#about to read 3, iclass 36, count 0 2006.259.07:42:03.74#ibcon#read 3, iclass 36, count 0 2006.259.07:42:03.74#ibcon#about to read 4, iclass 36, count 0 2006.259.07:42:03.74#ibcon#read 4, iclass 36, count 0 2006.259.07:42:03.74#ibcon#about to read 5, iclass 36, count 0 2006.259.07:42:03.74#ibcon#read 5, iclass 36, count 0 2006.259.07:42:03.74#ibcon#about to read 6, iclass 36, count 0 2006.259.07:42:03.74#ibcon#read 6, iclass 36, count 0 2006.259.07:42:03.74#ibcon#end of sib2, iclass 36, count 0 2006.259.07:42:03.74#ibcon#*mode == 0, iclass 36, count 0 2006.259.07:42:03.74#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.259.07:42:03.74#ibcon#[25=USB\r\n] 2006.259.07:42:03.74#ibcon#*before write, iclass 36, count 0 2006.259.07:42:03.74#ibcon#enter sib2, iclass 36, count 0 2006.259.07:42:03.74#ibcon#flushed, iclass 36, count 0 2006.259.07:42:03.74#ibcon#about to write, iclass 36, count 0 2006.259.07:42:03.74#ibcon#wrote, iclass 36, count 0 2006.259.07:42:03.74#ibcon#about to read 3, iclass 36, count 0 2006.259.07:42:03.77#ibcon#read 3, iclass 36, count 0 2006.259.07:42:03.77#ibcon#about to read 4, iclass 36, count 0 2006.259.07:42:03.77#ibcon#read 4, iclass 36, count 0 2006.259.07:42:03.77#ibcon#about to read 5, iclass 36, count 0 2006.259.07:42:03.77#ibcon#read 5, iclass 36, count 0 2006.259.07:42:03.77#ibcon#about to read 6, iclass 36, count 0 2006.259.07:42:03.77#ibcon#read 6, iclass 36, count 0 2006.259.07:42:03.77#ibcon#end of sib2, iclass 36, count 0 2006.259.07:42:03.77#ibcon#*after write, iclass 36, count 0 2006.259.07:42:03.77#ibcon#*before return 0, iclass 36, count 0 2006.259.07:42:03.77#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.259.07:42:03.77#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.259.07:42:03.77#ibcon#about to clear, iclass 36 cls_cnt 0 2006.259.07:42:03.77#ibcon#cleared, iclass 36 cls_cnt 0 2006.259.07:42:03.77$vc4f8/valo=7,832.99 2006.259.07:42:03.77#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.259.07:42:03.77#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.259.07:42:03.77#ibcon#ireg 17 cls_cnt 0 2006.259.07:42:03.77#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.259.07:42:03.77#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.259.07:42:03.77#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.259.07:42:03.77#ibcon#enter wrdev, iclass 38, count 0 2006.259.07:42:03.77#ibcon#first serial, iclass 38, count 0 2006.259.07:42:03.77#ibcon#enter sib2, iclass 38, count 0 2006.259.07:42:03.77#ibcon#flushed, iclass 38, count 0 2006.259.07:42:03.77#ibcon#about to write, iclass 38, count 0 2006.259.07:42:03.77#ibcon#wrote, iclass 38, count 0 2006.259.07:42:03.77#ibcon#about to read 3, iclass 38, count 0 2006.259.07:42:03.79#ibcon#read 3, iclass 38, count 0 2006.259.07:42:03.79#ibcon#about to read 4, iclass 38, count 0 2006.259.07:42:03.79#ibcon#read 4, iclass 38, count 0 2006.259.07:42:03.79#ibcon#about to read 5, iclass 38, count 0 2006.259.07:42:03.79#ibcon#read 5, iclass 38, count 0 2006.259.07:42:03.79#ibcon#about to read 6, iclass 38, count 0 2006.259.07:42:03.79#ibcon#read 6, iclass 38, count 0 2006.259.07:42:03.79#ibcon#end of sib2, iclass 38, count 0 2006.259.07:42:03.79#ibcon#*mode == 0, iclass 38, count 0 2006.259.07:42:03.79#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.259.07:42:03.79#ibcon#[26=FRQ=07,832.99\r\n] 2006.259.07:42:03.79#ibcon#*before write, iclass 38, count 0 2006.259.07:42:03.79#ibcon#enter sib2, iclass 38, count 0 2006.259.07:42:03.79#ibcon#flushed, iclass 38, count 0 2006.259.07:42:03.79#ibcon#about to write, iclass 38, count 0 2006.259.07:42:03.79#ibcon#wrote, iclass 38, count 0 2006.259.07:42:03.79#ibcon#about to read 3, iclass 38, count 0 2006.259.07:42:03.83#ibcon#read 3, iclass 38, count 0 2006.259.07:42:03.83#ibcon#about to read 4, iclass 38, count 0 2006.259.07:42:03.83#ibcon#read 4, iclass 38, count 0 2006.259.07:42:03.83#ibcon#about to read 5, iclass 38, count 0 2006.259.07:42:03.83#ibcon#read 5, iclass 38, count 0 2006.259.07:42:03.83#ibcon#about to read 6, iclass 38, count 0 2006.259.07:42:03.83#ibcon#read 6, iclass 38, count 0 2006.259.07:42:03.83#ibcon#end of sib2, iclass 38, count 0 2006.259.07:42:03.83#ibcon#*after write, iclass 38, count 0 2006.259.07:42:03.83#ibcon#*before return 0, iclass 38, count 0 2006.259.07:42:03.83#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.259.07:42:03.83#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.259.07:42:03.83#ibcon#about to clear, iclass 38 cls_cnt 0 2006.259.07:42:03.83#ibcon#cleared, iclass 38 cls_cnt 0 2006.259.07:42:03.83$vc4f8/va=7,6 2006.259.07:42:03.83#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.259.07:42:03.83#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.259.07:42:03.83#ibcon#ireg 11 cls_cnt 2 2006.259.07:42:03.83#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.259.07:42:03.89#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.259.07:42:03.89#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.259.07:42:03.89#ibcon#enter wrdev, iclass 40, count 2 2006.259.07:42:03.89#ibcon#first serial, iclass 40, count 2 2006.259.07:42:03.89#ibcon#enter sib2, iclass 40, count 2 2006.259.07:42:03.89#ibcon#flushed, iclass 40, count 2 2006.259.07:42:03.89#ibcon#about to write, iclass 40, count 2 2006.259.07:42:03.89#ibcon#wrote, iclass 40, count 2 2006.259.07:42:03.89#ibcon#about to read 3, iclass 40, count 2 2006.259.07:42:03.91#ibcon#read 3, iclass 40, count 2 2006.259.07:42:03.91#ibcon#about to read 4, iclass 40, count 2 2006.259.07:42:03.91#ibcon#read 4, iclass 40, count 2 2006.259.07:42:03.91#ibcon#about to read 5, iclass 40, count 2 2006.259.07:42:03.91#ibcon#read 5, iclass 40, count 2 2006.259.07:42:03.91#ibcon#about to read 6, iclass 40, count 2 2006.259.07:42:03.91#ibcon#read 6, iclass 40, count 2 2006.259.07:42:03.91#ibcon#end of sib2, iclass 40, count 2 2006.259.07:42:03.91#ibcon#*mode == 0, iclass 40, count 2 2006.259.07:42:03.91#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.259.07:42:03.91#ibcon#[25=AT07-06\r\n] 2006.259.07:42:03.91#ibcon#*before write, iclass 40, count 2 2006.259.07:42:03.91#ibcon#enter sib2, iclass 40, count 2 2006.259.07:42:03.91#ibcon#flushed, iclass 40, count 2 2006.259.07:42:03.91#ibcon#about to write, iclass 40, count 2 2006.259.07:42:03.91#ibcon#wrote, iclass 40, count 2 2006.259.07:42:03.91#ibcon#about to read 3, iclass 40, count 2 2006.259.07:42:03.94#ibcon#read 3, iclass 40, count 2 2006.259.07:42:03.94#ibcon#about to read 4, iclass 40, count 2 2006.259.07:42:03.94#ibcon#read 4, iclass 40, count 2 2006.259.07:42:03.94#ibcon#about to read 5, iclass 40, count 2 2006.259.07:42:03.94#ibcon#read 5, iclass 40, count 2 2006.259.07:42:03.94#ibcon#about to read 6, iclass 40, count 2 2006.259.07:42:03.94#ibcon#read 6, iclass 40, count 2 2006.259.07:42:03.94#ibcon#end of sib2, iclass 40, count 2 2006.259.07:42:03.94#ibcon#*after write, iclass 40, count 2 2006.259.07:42:03.94#ibcon#*before return 0, iclass 40, count 2 2006.259.07:42:03.94#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.259.07:42:03.94#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.259.07:42:03.94#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.259.07:42:03.94#ibcon#ireg 7 cls_cnt 0 2006.259.07:42:03.94#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.259.07:42:04.06#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.259.07:42:04.06#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.259.07:42:04.06#ibcon#enter wrdev, iclass 40, count 0 2006.259.07:42:04.06#ibcon#first serial, iclass 40, count 0 2006.259.07:42:04.06#ibcon#enter sib2, iclass 40, count 0 2006.259.07:42:04.06#ibcon#flushed, iclass 40, count 0 2006.259.07:42:04.06#ibcon#about to write, iclass 40, count 0 2006.259.07:42:04.06#ibcon#wrote, iclass 40, count 0 2006.259.07:42:04.06#ibcon#about to read 3, iclass 40, count 0 2006.259.07:42:04.08#ibcon#read 3, iclass 40, count 0 2006.259.07:42:04.08#ibcon#about to read 4, iclass 40, count 0 2006.259.07:42:04.08#ibcon#read 4, iclass 40, count 0 2006.259.07:42:04.08#ibcon#about to read 5, iclass 40, count 0 2006.259.07:42:04.08#ibcon#read 5, iclass 40, count 0 2006.259.07:42:04.08#ibcon#about to read 6, iclass 40, count 0 2006.259.07:42:04.08#ibcon#read 6, iclass 40, count 0 2006.259.07:42:04.08#ibcon#end of sib2, iclass 40, count 0 2006.259.07:42:04.08#ibcon#*mode == 0, iclass 40, count 0 2006.259.07:42:04.08#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.259.07:42:04.08#ibcon#[25=USB\r\n] 2006.259.07:42:04.08#ibcon#*before write, iclass 40, count 0 2006.259.07:42:04.08#ibcon#enter sib2, iclass 40, count 0 2006.259.07:42:04.08#ibcon#flushed, iclass 40, count 0 2006.259.07:42:04.08#ibcon#about to write, iclass 40, count 0 2006.259.07:42:04.08#ibcon#wrote, iclass 40, count 0 2006.259.07:42:04.08#ibcon#about to read 3, iclass 40, count 0 2006.259.07:42:04.11#ibcon#read 3, iclass 40, count 0 2006.259.07:42:04.11#ibcon#about to read 4, iclass 40, count 0 2006.259.07:42:04.11#ibcon#read 4, iclass 40, count 0 2006.259.07:42:04.11#ibcon#about to read 5, iclass 40, count 0 2006.259.07:42:04.11#ibcon#read 5, iclass 40, count 0 2006.259.07:42:04.11#ibcon#about to read 6, iclass 40, count 0 2006.259.07:42:04.11#ibcon#read 6, iclass 40, count 0 2006.259.07:42:04.11#ibcon#end of sib2, iclass 40, count 0 2006.259.07:42:04.11#ibcon#*after write, iclass 40, count 0 2006.259.07:42:04.11#ibcon#*before return 0, iclass 40, count 0 2006.259.07:42:04.11#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.259.07:42:04.11#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.259.07:42:04.11#ibcon#about to clear, iclass 40 cls_cnt 0 2006.259.07:42:04.11#ibcon#cleared, iclass 40 cls_cnt 0 2006.259.07:42:04.11$vc4f8/valo=8,852.99 2006.259.07:42:04.11#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.259.07:42:04.11#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.259.07:42:04.11#ibcon#ireg 17 cls_cnt 0 2006.259.07:42:04.11#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.259.07:42:04.11#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.259.07:42:04.11#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.259.07:42:04.11#ibcon#enter wrdev, iclass 4, count 0 2006.259.07:42:04.11#ibcon#first serial, iclass 4, count 0 2006.259.07:42:04.11#ibcon#enter sib2, iclass 4, count 0 2006.259.07:42:04.11#ibcon#flushed, iclass 4, count 0 2006.259.07:42:04.11#ibcon#about to write, iclass 4, count 0 2006.259.07:42:04.11#ibcon#wrote, iclass 4, count 0 2006.259.07:42:04.11#ibcon#about to read 3, iclass 4, count 0 2006.259.07:42:04.13#ibcon#read 3, iclass 4, count 0 2006.259.07:42:04.13#ibcon#about to read 4, iclass 4, count 0 2006.259.07:42:04.13#ibcon#read 4, iclass 4, count 0 2006.259.07:42:04.13#ibcon#about to read 5, iclass 4, count 0 2006.259.07:42:04.13#ibcon#read 5, iclass 4, count 0 2006.259.07:42:04.13#ibcon#about to read 6, iclass 4, count 0 2006.259.07:42:04.13#ibcon#read 6, iclass 4, count 0 2006.259.07:42:04.13#ibcon#end of sib2, iclass 4, count 0 2006.259.07:42:04.13#ibcon#*mode == 0, iclass 4, count 0 2006.259.07:42:04.13#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.259.07:42:04.13#ibcon#[26=FRQ=08,852.99\r\n] 2006.259.07:42:04.13#ibcon#*before write, iclass 4, count 0 2006.259.07:42:04.13#ibcon#enter sib2, iclass 4, count 0 2006.259.07:42:04.13#ibcon#flushed, iclass 4, count 0 2006.259.07:42:04.13#ibcon#about to write, iclass 4, count 0 2006.259.07:42:04.13#ibcon#wrote, iclass 4, count 0 2006.259.07:42:04.13#ibcon#about to read 3, iclass 4, count 0 2006.259.07:42:04.17#ibcon#read 3, iclass 4, count 0 2006.259.07:42:04.17#ibcon#about to read 4, iclass 4, count 0 2006.259.07:42:04.17#ibcon#read 4, iclass 4, count 0 2006.259.07:42:04.17#ibcon#about to read 5, iclass 4, count 0 2006.259.07:42:04.17#ibcon#read 5, iclass 4, count 0 2006.259.07:42:04.17#ibcon#about to read 6, iclass 4, count 0 2006.259.07:42:04.17#ibcon#read 6, iclass 4, count 0 2006.259.07:42:04.17#ibcon#end of sib2, iclass 4, count 0 2006.259.07:42:04.17#ibcon#*after write, iclass 4, count 0 2006.259.07:42:04.17#ibcon#*before return 0, iclass 4, count 0 2006.259.07:42:04.17#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.259.07:42:04.17#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.259.07:42:04.17#ibcon#about to clear, iclass 4 cls_cnt 0 2006.259.07:42:04.17#ibcon#cleared, iclass 4 cls_cnt 0 2006.259.07:42:04.17$vc4f8/va=8,6 2006.259.07:42:04.17#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.259.07:42:04.17#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.259.07:42:04.17#ibcon#ireg 11 cls_cnt 2 2006.259.07:42:04.17#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.259.07:42:04.23#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.259.07:42:04.23#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.259.07:42:04.23#ibcon#enter wrdev, iclass 6, count 2 2006.259.07:42:04.23#ibcon#first serial, iclass 6, count 2 2006.259.07:42:04.23#ibcon#enter sib2, iclass 6, count 2 2006.259.07:42:04.23#ibcon#flushed, iclass 6, count 2 2006.259.07:42:04.23#ibcon#about to write, iclass 6, count 2 2006.259.07:42:04.23#ibcon#wrote, iclass 6, count 2 2006.259.07:42:04.23#ibcon#about to read 3, iclass 6, count 2 2006.259.07:42:04.25#ibcon#read 3, iclass 6, count 2 2006.259.07:42:04.25#ibcon#about to read 4, iclass 6, count 2 2006.259.07:42:04.25#ibcon#read 4, iclass 6, count 2 2006.259.07:42:04.25#ibcon#about to read 5, iclass 6, count 2 2006.259.07:42:04.25#ibcon#read 5, iclass 6, count 2 2006.259.07:42:04.25#ibcon#about to read 6, iclass 6, count 2 2006.259.07:42:04.25#ibcon#read 6, iclass 6, count 2 2006.259.07:42:04.25#ibcon#end of sib2, iclass 6, count 2 2006.259.07:42:04.25#ibcon#*mode == 0, iclass 6, count 2 2006.259.07:42:04.25#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.259.07:42:04.25#ibcon#[25=AT08-06\r\n] 2006.259.07:42:04.25#ibcon#*before write, iclass 6, count 2 2006.259.07:42:04.25#ibcon#enter sib2, iclass 6, count 2 2006.259.07:42:04.25#ibcon#flushed, iclass 6, count 2 2006.259.07:42:04.25#ibcon#about to write, iclass 6, count 2 2006.259.07:42:04.25#ibcon#wrote, iclass 6, count 2 2006.259.07:42:04.25#ibcon#about to read 3, iclass 6, count 2 2006.259.07:42:04.28#ibcon#read 3, iclass 6, count 2 2006.259.07:42:04.28#ibcon#about to read 4, iclass 6, count 2 2006.259.07:42:04.28#ibcon#read 4, iclass 6, count 2 2006.259.07:42:04.28#ibcon#about to read 5, iclass 6, count 2 2006.259.07:42:04.28#ibcon#read 5, iclass 6, count 2 2006.259.07:42:04.28#ibcon#about to read 6, iclass 6, count 2 2006.259.07:42:04.28#ibcon#read 6, iclass 6, count 2 2006.259.07:42:04.28#ibcon#end of sib2, iclass 6, count 2 2006.259.07:42:04.28#ibcon#*after write, iclass 6, count 2 2006.259.07:42:04.28#ibcon#*before return 0, iclass 6, count 2 2006.259.07:42:04.28#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.259.07:42:04.28#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.259.07:42:04.28#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.259.07:42:04.28#ibcon#ireg 7 cls_cnt 0 2006.259.07:42:04.28#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.259.07:42:04.40#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.259.07:42:04.40#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.259.07:42:04.40#ibcon#enter wrdev, iclass 6, count 0 2006.259.07:42:04.40#ibcon#first serial, iclass 6, count 0 2006.259.07:42:04.40#ibcon#enter sib2, iclass 6, count 0 2006.259.07:42:04.40#ibcon#flushed, iclass 6, count 0 2006.259.07:42:04.40#ibcon#about to write, iclass 6, count 0 2006.259.07:42:04.40#ibcon#wrote, iclass 6, count 0 2006.259.07:42:04.40#ibcon#about to read 3, iclass 6, count 0 2006.259.07:42:04.42#ibcon#read 3, iclass 6, count 0 2006.259.07:42:04.42#ibcon#about to read 4, iclass 6, count 0 2006.259.07:42:04.42#ibcon#read 4, iclass 6, count 0 2006.259.07:42:04.42#ibcon#about to read 5, iclass 6, count 0 2006.259.07:42:04.42#ibcon#read 5, iclass 6, count 0 2006.259.07:42:04.42#ibcon#about to read 6, iclass 6, count 0 2006.259.07:42:04.42#ibcon#read 6, iclass 6, count 0 2006.259.07:42:04.42#ibcon#end of sib2, iclass 6, count 0 2006.259.07:42:04.42#ibcon#*mode == 0, iclass 6, count 0 2006.259.07:42:04.42#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.259.07:42:04.42#ibcon#[25=USB\r\n] 2006.259.07:42:04.42#ibcon#*before write, iclass 6, count 0 2006.259.07:42:04.42#ibcon#enter sib2, iclass 6, count 0 2006.259.07:42:04.42#ibcon#flushed, iclass 6, count 0 2006.259.07:42:04.42#ibcon#about to write, iclass 6, count 0 2006.259.07:42:04.42#ibcon#wrote, iclass 6, count 0 2006.259.07:42:04.42#ibcon#about to read 3, iclass 6, count 0 2006.259.07:42:04.45#ibcon#read 3, iclass 6, count 0 2006.259.07:42:04.45#ibcon#about to read 4, iclass 6, count 0 2006.259.07:42:04.45#ibcon#read 4, iclass 6, count 0 2006.259.07:42:04.45#ibcon#about to read 5, iclass 6, count 0 2006.259.07:42:04.45#ibcon#read 5, iclass 6, count 0 2006.259.07:42:04.45#ibcon#about to read 6, iclass 6, count 0 2006.259.07:42:04.45#ibcon#read 6, iclass 6, count 0 2006.259.07:42:04.45#ibcon#end of sib2, iclass 6, count 0 2006.259.07:42:04.45#ibcon#*after write, iclass 6, count 0 2006.259.07:42:04.45#ibcon#*before return 0, iclass 6, count 0 2006.259.07:42:04.45#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.259.07:42:04.45#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.259.07:42:04.45#ibcon#about to clear, iclass 6 cls_cnt 0 2006.259.07:42:04.45#ibcon#cleared, iclass 6 cls_cnt 0 2006.259.07:42:04.45$vc4f8/vblo=1,632.99 2006.259.07:42:04.45#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.259.07:42:04.45#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.259.07:42:04.45#ibcon#ireg 17 cls_cnt 0 2006.259.07:42:04.45#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.259.07:42:04.45#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.259.07:42:04.45#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.259.07:42:04.45#ibcon#enter wrdev, iclass 10, count 0 2006.259.07:42:04.45#ibcon#first serial, iclass 10, count 0 2006.259.07:42:04.45#ibcon#enter sib2, iclass 10, count 0 2006.259.07:42:04.45#ibcon#flushed, iclass 10, count 0 2006.259.07:42:04.45#ibcon#about to write, iclass 10, count 0 2006.259.07:42:04.45#ibcon#wrote, iclass 10, count 0 2006.259.07:42:04.45#ibcon#about to read 3, iclass 10, count 0 2006.259.07:42:04.47#ibcon#read 3, iclass 10, count 0 2006.259.07:42:04.47#ibcon#about to read 4, iclass 10, count 0 2006.259.07:42:04.47#ibcon#read 4, iclass 10, count 0 2006.259.07:42:04.47#ibcon#about to read 5, iclass 10, count 0 2006.259.07:42:04.47#ibcon#read 5, iclass 10, count 0 2006.259.07:42:04.47#ibcon#about to read 6, iclass 10, count 0 2006.259.07:42:04.47#ibcon#read 6, iclass 10, count 0 2006.259.07:42:04.47#ibcon#end of sib2, iclass 10, count 0 2006.259.07:42:04.47#ibcon#*mode == 0, iclass 10, count 0 2006.259.07:42:04.47#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.259.07:42:04.47#ibcon#[28=FRQ=01,632.99\r\n] 2006.259.07:42:04.47#ibcon#*before write, iclass 10, count 0 2006.259.07:42:04.47#ibcon#enter sib2, iclass 10, count 0 2006.259.07:42:04.47#ibcon#flushed, iclass 10, count 0 2006.259.07:42:04.47#ibcon#about to write, iclass 10, count 0 2006.259.07:42:04.47#ibcon#wrote, iclass 10, count 0 2006.259.07:42:04.47#ibcon#about to read 3, iclass 10, count 0 2006.259.07:42:04.51#ibcon#read 3, iclass 10, count 0 2006.259.07:42:04.51#ibcon#about to read 4, iclass 10, count 0 2006.259.07:42:04.51#ibcon#read 4, iclass 10, count 0 2006.259.07:42:04.51#ibcon#about to read 5, iclass 10, count 0 2006.259.07:42:04.51#ibcon#read 5, iclass 10, count 0 2006.259.07:42:04.51#ibcon#about to read 6, iclass 10, count 0 2006.259.07:42:04.51#ibcon#read 6, iclass 10, count 0 2006.259.07:42:04.51#ibcon#end of sib2, iclass 10, count 0 2006.259.07:42:04.51#ibcon#*after write, iclass 10, count 0 2006.259.07:42:04.51#ibcon#*before return 0, iclass 10, count 0 2006.259.07:42:04.51#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.259.07:42:04.51#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.259.07:42:04.51#ibcon#about to clear, iclass 10 cls_cnt 0 2006.259.07:42:04.51#ibcon#cleared, iclass 10 cls_cnt 0 2006.259.07:42:04.51$vc4f8/vb=1,4 2006.259.07:42:04.51#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.259.07:42:04.51#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.259.07:42:04.51#ibcon#ireg 11 cls_cnt 2 2006.259.07:42:04.51#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.259.07:42:04.51#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.259.07:42:04.51#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.259.07:42:04.51#ibcon#enter wrdev, iclass 12, count 2 2006.259.07:42:04.51#ibcon#first serial, iclass 12, count 2 2006.259.07:42:04.51#ibcon#enter sib2, iclass 12, count 2 2006.259.07:42:04.51#ibcon#flushed, iclass 12, count 2 2006.259.07:42:04.51#ibcon#about to write, iclass 12, count 2 2006.259.07:42:04.51#ibcon#wrote, iclass 12, count 2 2006.259.07:42:04.51#ibcon#about to read 3, iclass 12, count 2 2006.259.07:42:04.53#ibcon#read 3, iclass 12, count 2 2006.259.07:42:04.53#ibcon#about to read 4, iclass 12, count 2 2006.259.07:42:04.53#ibcon#read 4, iclass 12, count 2 2006.259.07:42:04.53#ibcon#about to read 5, iclass 12, count 2 2006.259.07:42:04.53#ibcon#read 5, iclass 12, count 2 2006.259.07:42:04.53#ibcon#about to read 6, iclass 12, count 2 2006.259.07:42:04.53#ibcon#read 6, iclass 12, count 2 2006.259.07:42:04.53#ibcon#end of sib2, iclass 12, count 2 2006.259.07:42:04.53#ibcon#*mode == 0, iclass 12, count 2 2006.259.07:42:04.53#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.259.07:42:04.53#ibcon#[27=AT01-04\r\n] 2006.259.07:42:04.53#ibcon#*before write, iclass 12, count 2 2006.259.07:42:04.53#ibcon#enter sib2, iclass 12, count 2 2006.259.07:42:04.53#ibcon#flushed, iclass 12, count 2 2006.259.07:42:04.53#ibcon#about to write, iclass 12, count 2 2006.259.07:42:04.53#ibcon#wrote, iclass 12, count 2 2006.259.07:42:04.53#ibcon#about to read 3, iclass 12, count 2 2006.259.07:42:04.56#ibcon#read 3, iclass 12, count 2 2006.259.07:42:04.56#ibcon#about to read 4, iclass 12, count 2 2006.259.07:42:04.56#ibcon#read 4, iclass 12, count 2 2006.259.07:42:04.56#ibcon#about to read 5, iclass 12, count 2 2006.259.07:42:04.56#ibcon#read 5, iclass 12, count 2 2006.259.07:42:04.56#ibcon#about to read 6, iclass 12, count 2 2006.259.07:42:04.56#ibcon#read 6, iclass 12, count 2 2006.259.07:42:04.56#ibcon#end of sib2, iclass 12, count 2 2006.259.07:42:04.56#ibcon#*after write, iclass 12, count 2 2006.259.07:42:04.56#ibcon#*before return 0, iclass 12, count 2 2006.259.07:42:04.56#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.259.07:42:04.56#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.259.07:42:04.56#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.259.07:42:04.56#ibcon#ireg 7 cls_cnt 0 2006.259.07:42:04.56#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.259.07:42:04.68#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.259.07:42:04.68#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.259.07:42:04.68#ibcon#enter wrdev, iclass 12, count 0 2006.259.07:42:04.68#ibcon#first serial, iclass 12, count 0 2006.259.07:42:04.68#ibcon#enter sib2, iclass 12, count 0 2006.259.07:42:04.68#ibcon#flushed, iclass 12, count 0 2006.259.07:42:04.68#ibcon#about to write, iclass 12, count 0 2006.259.07:42:04.68#ibcon#wrote, iclass 12, count 0 2006.259.07:42:04.68#ibcon#about to read 3, iclass 12, count 0 2006.259.07:42:04.70#ibcon#read 3, iclass 12, count 0 2006.259.07:42:04.70#ibcon#about to read 4, iclass 12, count 0 2006.259.07:42:04.70#ibcon#read 4, iclass 12, count 0 2006.259.07:42:04.70#ibcon#about to read 5, iclass 12, count 0 2006.259.07:42:04.70#ibcon#read 5, iclass 12, count 0 2006.259.07:42:04.70#ibcon#about to read 6, iclass 12, count 0 2006.259.07:42:04.70#ibcon#read 6, iclass 12, count 0 2006.259.07:42:04.70#ibcon#end of sib2, iclass 12, count 0 2006.259.07:42:04.70#ibcon#*mode == 0, iclass 12, count 0 2006.259.07:42:04.70#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.259.07:42:04.70#ibcon#[27=USB\r\n] 2006.259.07:42:04.70#ibcon#*before write, iclass 12, count 0 2006.259.07:42:04.70#ibcon#enter sib2, iclass 12, count 0 2006.259.07:42:04.70#ibcon#flushed, iclass 12, count 0 2006.259.07:42:04.70#ibcon#about to write, iclass 12, count 0 2006.259.07:42:04.70#ibcon#wrote, iclass 12, count 0 2006.259.07:42:04.70#ibcon#about to read 3, iclass 12, count 0 2006.259.07:42:04.73#ibcon#read 3, iclass 12, count 0 2006.259.07:42:04.73#ibcon#about to read 4, iclass 12, count 0 2006.259.07:42:04.73#ibcon#read 4, iclass 12, count 0 2006.259.07:42:04.73#ibcon#about to read 5, iclass 12, count 0 2006.259.07:42:04.73#ibcon#read 5, iclass 12, count 0 2006.259.07:42:04.73#ibcon#about to read 6, iclass 12, count 0 2006.259.07:42:04.73#ibcon#read 6, iclass 12, count 0 2006.259.07:42:04.73#ibcon#end of sib2, iclass 12, count 0 2006.259.07:42:04.73#ibcon#*after write, iclass 12, count 0 2006.259.07:42:04.73#ibcon#*before return 0, iclass 12, count 0 2006.259.07:42:04.73#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.259.07:42:04.73#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.259.07:42:04.73#ibcon#about to clear, iclass 12 cls_cnt 0 2006.259.07:42:04.73#ibcon#cleared, iclass 12 cls_cnt 0 2006.259.07:42:04.73$vc4f8/vblo=2,640.99 2006.259.07:42:04.73#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.259.07:42:04.73#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.259.07:42:04.73#ibcon#ireg 17 cls_cnt 0 2006.259.07:42:04.73#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.259.07:42:04.73#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.259.07:42:04.73#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.259.07:42:04.73#ibcon#enter wrdev, iclass 14, count 0 2006.259.07:42:04.73#ibcon#first serial, iclass 14, count 0 2006.259.07:42:04.73#ibcon#enter sib2, iclass 14, count 0 2006.259.07:42:04.73#ibcon#flushed, iclass 14, count 0 2006.259.07:42:04.73#ibcon#about to write, iclass 14, count 0 2006.259.07:42:04.73#ibcon#wrote, iclass 14, count 0 2006.259.07:42:04.73#ibcon#about to read 3, iclass 14, count 0 2006.259.07:42:04.75#ibcon#read 3, iclass 14, count 0 2006.259.07:42:04.75#ibcon#about to read 4, iclass 14, count 0 2006.259.07:42:04.75#ibcon#read 4, iclass 14, count 0 2006.259.07:42:04.75#ibcon#about to read 5, iclass 14, count 0 2006.259.07:42:04.75#ibcon#read 5, iclass 14, count 0 2006.259.07:42:04.75#ibcon#about to read 6, iclass 14, count 0 2006.259.07:42:04.75#ibcon#read 6, iclass 14, count 0 2006.259.07:42:04.75#ibcon#end of sib2, iclass 14, count 0 2006.259.07:42:04.75#ibcon#*mode == 0, iclass 14, count 0 2006.259.07:42:04.75#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.259.07:42:04.75#ibcon#[28=FRQ=02,640.99\r\n] 2006.259.07:42:04.75#ibcon#*before write, iclass 14, count 0 2006.259.07:42:04.75#ibcon#enter sib2, iclass 14, count 0 2006.259.07:42:04.75#ibcon#flushed, iclass 14, count 0 2006.259.07:42:04.75#ibcon#about to write, iclass 14, count 0 2006.259.07:42:04.75#ibcon#wrote, iclass 14, count 0 2006.259.07:42:04.75#ibcon#about to read 3, iclass 14, count 0 2006.259.07:42:04.79#ibcon#read 3, iclass 14, count 0 2006.259.07:42:04.79#ibcon#about to read 4, iclass 14, count 0 2006.259.07:42:04.79#ibcon#read 4, iclass 14, count 0 2006.259.07:42:04.79#ibcon#about to read 5, iclass 14, count 0 2006.259.07:42:04.79#ibcon#read 5, iclass 14, count 0 2006.259.07:42:04.79#ibcon#about to read 6, iclass 14, count 0 2006.259.07:42:04.79#ibcon#read 6, iclass 14, count 0 2006.259.07:42:04.79#ibcon#end of sib2, iclass 14, count 0 2006.259.07:42:04.79#ibcon#*after write, iclass 14, count 0 2006.259.07:42:04.79#ibcon#*before return 0, iclass 14, count 0 2006.259.07:42:04.79#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.259.07:42:04.79#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.259.07:42:04.79#ibcon#about to clear, iclass 14 cls_cnt 0 2006.259.07:42:04.79#ibcon#cleared, iclass 14 cls_cnt 0 2006.259.07:42:04.79$vc4f8/vb=2,5 2006.259.07:42:04.79#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.259.07:42:04.79#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.259.07:42:04.79#ibcon#ireg 11 cls_cnt 2 2006.259.07:42:04.79#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.259.07:42:04.85#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.259.07:42:04.85#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.259.07:42:04.85#ibcon#enter wrdev, iclass 16, count 2 2006.259.07:42:04.85#ibcon#first serial, iclass 16, count 2 2006.259.07:42:04.85#ibcon#enter sib2, iclass 16, count 2 2006.259.07:42:04.85#ibcon#flushed, iclass 16, count 2 2006.259.07:42:04.85#ibcon#about to write, iclass 16, count 2 2006.259.07:42:04.85#ibcon#wrote, iclass 16, count 2 2006.259.07:42:04.85#ibcon#about to read 3, iclass 16, count 2 2006.259.07:42:04.87#ibcon#read 3, iclass 16, count 2 2006.259.07:42:04.87#ibcon#about to read 4, iclass 16, count 2 2006.259.07:42:04.87#ibcon#read 4, iclass 16, count 2 2006.259.07:42:04.87#ibcon#about to read 5, iclass 16, count 2 2006.259.07:42:04.87#ibcon#read 5, iclass 16, count 2 2006.259.07:42:04.87#ibcon#about to read 6, iclass 16, count 2 2006.259.07:42:04.87#ibcon#read 6, iclass 16, count 2 2006.259.07:42:04.87#ibcon#end of sib2, iclass 16, count 2 2006.259.07:42:04.87#ibcon#*mode == 0, iclass 16, count 2 2006.259.07:42:04.87#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.259.07:42:04.87#ibcon#[27=AT02-05\r\n] 2006.259.07:42:04.87#ibcon#*before write, iclass 16, count 2 2006.259.07:42:04.87#ibcon#enter sib2, iclass 16, count 2 2006.259.07:42:04.87#ibcon#flushed, iclass 16, count 2 2006.259.07:42:04.87#ibcon#about to write, iclass 16, count 2 2006.259.07:42:04.87#ibcon#wrote, iclass 16, count 2 2006.259.07:42:04.87#ibcon#about to read 3, iclass 16, count 2 2006.259.07:42:04.90#ibcon#read 3, iclass 16, count 2 2006.259.07:42:04.90#ibcon#about to read 4, iclass 16, count 2 2006.259.07:42:04.90#ibcon#read 4, iclass 16, count 2 2006.259.07:42:04.90#ibcon#about to read 5, iclass 16, count 2 2006.259.07:42:04.90#ibcon#read 5, iclass 16, count 2 2006.259.07:42:04.90#ibcon#about to read 6, iclass 16, count 2 2006.259.07:42:04.90#ibcon#read 6, iclass 16, count 2 2006.259.07:42:04.90#ibcon#end of sib2, iclass 16, count 2 2006.259.07:42:04.90#ibcon#*after write, iclass 16, count 2 2006.259.07:42:04.90#ibcon#*before return 0, iclass 16, count 2 2006.259.07:42:04.90#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.259.07:42:04.90#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.259.07:42:04.90#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.259.07:42:04.90#ibcon#ireg 7 cls_cnt 0 2006.259.07:42:04.90#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.259.07:42:05.02#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.259.07:42:05.02#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.259.07:42:05.02#ibcon#enter wrdev, iclass 16, count 0 2006.259.07:42:05.02#ibcon#first serial, iclass 16, count 0 2006.259.07:42:05.02#ibcon#enter sib2, iclass 16, count 0 2006.259.07:42:05.02#ibcon#flushed, iclass 16, count 0 2006.259.07:42:05.02#ibcon#about to write, iclass 16, count 0 2006.259.07:42:05.02#ibcon#wrote, iclass 16, count 0 2006.259.07:42:05.02#ibcon#about to read 3, iclass 16, count 0 2006.259.07:42:05.04#ibcon#read 3, iclass 16, count 0 2006.259.07:42:05.04#ibcon#about to read 4, iclass 16, count 0 2006.259.07:42:05.04#ibcon#read 4, iclass 16, count 0 2006.259.07:42:05.04#ibcon#about to read 5, iclass 16, count 0 2006.259.07:42:05.04#ibcon#read 5, iclass 16, count 0 2006.259.07:42:05.04#ibcon#about to read 6, iclass 16, count 0 2006.259.07:42:05.04#ibcon#read 6, iclass 16, count 0 2006.259.07:42:05.04#ibcon#end of sib2, iclass 16, count 0 2006.259.07:42:05.04#ibcon#*mode == 0, iclass 16, count 0 2006.259.07:42:05.04#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.259.07:42:05.04#ibcon#[27=USB\r\n] 2006.259.07:42:05.04#ibcon#*before write, iclass 16, count 0 2006.259.07:42:05.04#ibcon#enter sib2, iclass 16, count 0 2006.259.07:42:05.04#ibcon#flushed, iclass 16, count 0 2006.259.07:42:05.04#ibcon#about to write, iclass 16, count 0 2006.259.07:42:05.04#ibcon#wrote, iclass 16, count 0 2006.259.07:42:05.04#ibcon#about to read 3, iclass 16, count 0 2006.259.07:42:05.07#ibcon#read 3, iclass 16, count 0 2006.259.07:42:05.07#ibcon#about to read 4, iclass 16, count 0 2006.259.07:42:05.07#ibcon#read 4, iclass 16, count 0 2006.259.07:42:05.07#ibcon#about to read 5, iclass 16, count 0 2006.259.07:42:05.07#ibcon#read 5, iclass 16, count 0 2006.259.07:42:05.07#ibcon#about to read 6, iclass 16, count 0 2006.259.07:42:05.07#ibcon#read 6, iclass 16, count 0 2006.259.07:42:05.07#ibcon#end of sib2, iclass 16, count 0 2006.259.07:42:05.07#ibcon#*after write, iclass 16, count 0 2006.259.07:42:05.07#ibcon#*before return 0, iclass 16, count 0 2006.259.07:42:05.07#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.259.07:42:05.07#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.259.07:42:05.07#ibcon#about to clear, iclass 16 cls_cnt 0 2006.259.07:42:05.07#ibcon#cleared, iclass 16 cls_cnt 0 2006.259.07:42:05.07$vc4f8/vblo=3,656.99 2006.259.07:42:05.07#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.259.07:42:05.07#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.259.07:42:05.07#ibcon#ireg 17 cls_cnt 0 2006.259.07:42:05.07#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.259.07:42:05.07#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.259.07:42:05.07#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.259.07:42:05.07#ibcon#enter wrdev, iclass 18, count 0 2006.259.07:42:05.07#ibcon#first serial, iclass 18, count 0 2006.259.07:42:05.07#ibcon#enter sib2, iclass 18, count 0 2006.259.07:42:05.07#ibcon#flushed, iclass 18, count 0 2006.259.07:42:05.07#ibcon#about to write, iclass 18, count 0 2006.259.07:42:05.07#ibcon#wrote, iclass 18, count 0 2006.259.07:42:05.07#ibcon#about to read 3, iclass 18, count 0 2006.259.07:42:05.09#ibcon#read 3, iclass 18, count 0 2006.259.07:42:05.09#ibcon#about to read 4, iclass 18, count 0 2006.259.07:42:05.09#ibcon#read 4, iclass 18, count 0 2006.259.07:42:05.09#ibcon#about to read 5, iclass 18, count 0 2006.259.07:42:05.09#ibcon#read 5, iclass 18, count 0 2006.259.07:42:05.09#ibcon#about to read 6, iclass 18, count 0 2006.259.07:42:05.09#ibcon#read 6, iclass 18, count 0 2006.259.07:42:05.09#ibcon#end of sib2, iclass 18, count 0 2006.259.07:42:05.09#ibcon#*mode == 0, iclass 18, count 0 2006.259.07:42:05.09#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.259.07:42:05.09#ibcon#[28=FRQ=03,656.99\r\n] 2006.259.07:42:05.09#ibcon#*before write, iclass 18, count 0 2006.259.07:42:05.09#ibcon#enter sib2, iclass 18, count 0 2006.259.07:42:05.09#ibcon#flushed, iclass 18, count 0 2006.259.07:42:05.09#ibcon#about to write, iclass 18, count 0 2006.259.07:42:05.09#ibcon#wrote, iclass 18, count 0 2006.259.07:42:05.09#ibcon#about to read 3, iclass 18, count 0 2006.259.07:42:05.13#ibcon#read 3, iclass 18, count 0 2006.259.07:42:05.13#ibcon#about to read 4, iclass 18, count 0 2006.259.07:42:05.13#ibcon#read 4, iclass 18, count 0 2006.259.07:42:05.13#ibcon#about to read 5, iclass 18, count 0 2006.259.07:42:05.13#ibcon#read 5, iclass 18, count 0 2006.259.07:42:05.13#ibcon#about to read 6, iclass 18, count 0 2006.259.07:42:05.13#ibcon#read 6, iclass 18, count 0 2006.259.07:42:05.13#ibcon#end of sib2, iclass 18, count 0 2006.259.07:42:05.13#ibcon#*after write, iclass 18, count 0 2006.259.07:42:05.13#ibcon#*before return 0, iclass 18, count 0 2006.259.07:42:05.13#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.259.07:42:05.13#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.259.07:42:05.13#ibcon#about to clear, iclass 18 cls_cnt 0 2006.259.07:42:05.13#ibcon#cleared, iclass 18 cls_cnt 0 2006.259.07:42:05.13$vc4f8/vb=3,4 2006.259.07:42:05.13#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.259.07:42:05.13#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.259.07:42:05.13#ibcon#ireg 11 cls_cnt 2 2006.259.07:42:05.13#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.259.07:42:05.19#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.259.07:42:05.19#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.259.07:42:05.19#ibcon#enter wrdev, iclass 20, count 2 2006.259.07:42:05.19#ibcon#first serial, iclass 20, count 2 2006.259.07:42:05.19#ibcon#enter sib2, iclass 20, count 2 2006.259.07:42:05.19#ibcon#flushed, iclass 20, count 2 2006.259.07:42:05.19#ibcon#about to write, iclass 20, count 2 2006.259.07:42:05.19#ibcon#wrote, iclass 20, count 2 2006.259.07:42:05.19#ibcon#about to read 3, iclass 20, count 2 2006.259.07:42:05.21#ibcon#read 3, iclass 20, count 2 2006.259.07:42:05.21#ibcon#about to read 4, iclass 20, count 2 2006.259.07:42:05.21#ibcon#read 4, iclass 20, count 2 2006.259.07:42:05.21#ibcon#about to read 5, iclass 20, count 2 2006.259.07:42:05.21#ibcon#read 5, iclass 20, count 2 2006.259.07:42:05.21#ibcon#about to read 6, iclass 20, count 2 2006.259.07:42:05.21#ibcon#read 6, iclass 20, count 2 2006.259.07:42:05.21#ibcon#end of sib2, iclass 20, count 2 2006.259.07:42:05.21#ibcon#*mode == 0, iclass 20, count 2 2006.259.07:42:05.21#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.259.07:42:05.21#ibcon#[27=AT03-04\r\n] 2006.259.07:42:05.21#ibcon#*before write, iclass 20, count 2 2006.259.07:42:05.21#ibcon#enter sib2, iclass 20, count 2 2006.259.07:42:05.21#ibcon#flushed, iclass 20, count 2 2006.259.07:42:05.21#ibcon#about to write, iclass 20, count 2 2006.259.07:42:05.21#ibcon#wrote, iclass 20, count 2 2006.259.07:42:05.21#ibcon#about to read 3, iclass 20, count 2 2006.259.07:42:05.24#ibcon#read 3, iclass 20, count 2 2006.259.07:42:05.24#ibcon#about to read 4, iclass 20, count 2 2006.259.07:42:05.24#ibcon#read 4, iclass 20, count 2 2006.259.07:42:05.24#ibcon#about to read 5, iclass 20, count 2 2006.259.07:42:05.24#ibcon#read 5, iclass 20, count 2 2006.259.07:42:05.24#ibcon#about to read 6, iclass 20, count 2 2006.259.07:42:05.24#ibcon#read 6, iclass 20, count 2 2006.259.07:42:05.24#ibcon#end of sib2, iclass 20, count 2 2006.259.07:42:05.24#ibcon#*after write, iclass 20, count 2 2006.259.07:42:05.24#ibcon#*before return 0, iclass 20, count 2 2006.259.07:42:05.24#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.259.07:42:05.24#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.259.07:42:05.24#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.259.07:42:05.24#ibcon#ireg 7 cls_cnt 0 2006.259.07:42:05.24#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.259.07:42:05.36#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.259.07:42:05.36#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.259.07:42:05.36#ibcon#enter wrdev, iclass 20, count 0 2006.259.07:42:05.36#ibcon#first serial, iclass 20, count 0 2006.259.07:42:05.36#ibcon#enter sib2, iclass 20, count 0 2006.259.07:42:05.36#ibcon#flushed, iclass 20, count 0 2006.259.07:42:05.36#ibcon#about to write, iclass 20, count 0 2006.259.07:42:05.36#ibcon#wrote, iclass 20, count 0 2006.259.07:42:05.36#ibcon#about to read 3, iclass 20, count 0 2006.259.07:42:05.38#ibcon#read 3, iclass 20, count 0 2006.259.07:42:05.38#ibcon#about to read 4, iclass 20, count 0 2006.259.07:42:05.38#ibcon#read 4, iclass 20, count 0 2006.259.07:42:05.38#ibcon#about to read 5, iclass 20, count 0 2006.259.07:42:05.38#ibcon#read 5, iclass 20, count 0 2006.259.07:42:05.38#ibcon#about to read 6, iclass 20, count 0 2006.259.07:42:05.38#ibcon#read 6, iclass 20, count 0 2006.259.07:42:05.38#ibcon#end of sib2, iclass 20, count 0 2006.259.07:42:05.38#ibcon#*mode == 0, iclass 20, count 0 2006.259.07:42:05.38#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.259.07:42:05.38#ibcon#[27=USB\r\n] 2006.259.07:42:05.38#ibcon#*before write, iclass 20, count 0 2006.259.07:42:05.38#ibcon#enter sib2, iclass 20, count 0 2006.259.07:42:05.38#ibcon#flushed, iclass 20, count 0 2006.259.07:42:05.38#ibcon#about to write, iclass 20, count 0 2006.259.07:42:05.38#ibcon#wrote, iclass 20, count 0 2006.259.07:42:05.38#ibcon#about to read 3, iclass 20, count 0 2006.259.07:42:05.41#ibcon#read 3, iclass 20, count 0 2006.259.07:42:05.41#ibcon#about to read 4, iclass 20, count 0 2006.259.07:42:05.41#ibcon#read 4, iclass 20, count 0 2006.259.07:42:05.41#ibcon#about to read 5, iclass 20, count 0 2006.259.07:42:05.41#ibcon#read 5, iclass 20, count 0 2006.259.07:42:05.41#ibcon#about to read 6, iclass 20, count 0 2006.259.07:42:05.41#ibcon#read 6, iclass 20, count 0 2006.259.07:42:05.41#ibcon#end of sib2, iclass 20, count 0 2006.259.07:42:05.41#ibcon#*after write, iclass 20, count 0 2006.259.07:42:05.41#ibcon#*before return 0, iclass 20, count 0 2006.259.07:42:05.41#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.259.07:42:05.41#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.259.07:42:05.41#ibcon#about to clear, iclass 20 cls_cnt 0 2006.259.07:42:05.41#ibcon#cleared, iclass 20 cls_cnt 0 2006.259.07:42:05.41$vc4f8/vblo=4,712.99 2006.259.07:42:05.41#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.259.07:42:05.41#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.259.07:42:05.41#ibcon#ireg 17 cls_cnt 0 2006.259.07:42:05.41#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.259.07:42:05.41#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.259.07:42:05.41#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.259.07:42:05.41#ibcon#enter wrdev, iclass 22, count 0 2006.259.07:42:05.41#ibcon#first serial, iclass 22, count 0 2006.259.07:42:05.41#ibcon#enter sib2, iclass 22, count 0 2006.259.07:42:05.41#ibcon#flushed, iclass 22, count 0 2006.259.07:42:05.41#ibcon#about to write, iclass 22, count 0 2006.259.07:42:05.41#ibcon#wrote, iclass 22, count 0 2006.259.07:42:05.41#ibcon#about to read 3, iclass 22, count 0 2006.259.07:42:05.43#ibcon#read 3, iclass 22, count 0 2006.259.07:42:05.43#ibcon#about to read 4, iclass 22, count 0 2006.259.07:42:05.43#ibcon#read 4, iclass 22, count 0 2006.259.07:42:05.43#ibcon#about to read 5, iclass 22, count 0 2006.259.07:42:05.43#ibcon#read 5, iclass 22, count 0 2006.259.07:42:05.43#ibcon#about to read 6, iclass 22, count 0 2006.259.07:42:05.43#ibcon#read 6, iclass 22, count 0 2006.259.07:42:05.43#ibcon#end of sib2, iclass 22, count 0 2006.259.07:42:05.43#ibcon#*mode == 0, iclass 22, count 0 2006.259.07:42:05.43#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.259.07:42:05.43#ibcon#[28=FRQ=04,712.99\r\n] 2006.259.07:42:05.43#ibcon#*before write, iclass 22, count 0 2006.259.07:42:05.43#ibcon#enter sib2, iclass 22, count 0 2006.259.07:42:05.43#ibcon#flushed, iclass 22, count 0 2006.259.07:42:05.43#ibcon#about to write, iclass 22, count 0 2006.259.07:42:05.43#ibcon#wrote, iclass 22, count 0 2006.259.07:42:05.43#ibcon#about to read 3, iclass 22, count 0 2006.259.07:42:05.47#ibcon#read 3, iclass 22, count 0 2006.259.07:42:05.47#ibcon#about to read 4, iclass 22, count 0 2006.259.07:42:05.47#ibcon#read 4, iclass 22, count 0 2006.259.07:42:05.47#ibcon#about to read 5, iclass 22, count 0 2006.259.07:42:05.47#ibcon#read 5, iclass 22, count 0 2006.259.07:42:05.47#ibcon#about to read 6, iclass 22, count 0 2006.259.07:42:05.47#ibcon#read 6, iclass 22, count 0 2006.259.07:42:05.47#ibcon#end of sib2, iclass 22, count 0 2006.259.07:42:05.47#ibcon#*after write, iclass 22, count 0 2006.259.07:42:05.47#ibcon#*before return 0, iclass 22, count 0 2006.259.07:42:05.47#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.259.07:42:05.47#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.259.07:42:05.47#ibcon#about to clear, iclass 22 cls_cnt 0 2006.259.07:42:05.47#ibcon#cleared, iclass 22 cls_cnt 0 2006.259.07:42:05.47$vc4f8/vb=4,5 2006.259.07:42:05.47#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.259.07:42:05.47#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.259.07:42:05.47#ibcon#ireg 11 cls_cnt 2 2006.259.07:42:05.47#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.259.07:42:05.53#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.259.07:42:05.53#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.259.07:42:05.53#ibcon#enter wrdev, iclass 24, count 2 2006.259.07:42:05.53#ibcon#first serial, iclass 24, count 2 2006.259.07:42:05.53#ibcon#enter sib2, iclass 24, count 2 2006.259.07:42:05.53#ibcon#flushed, iclass 24, count 2 2006.259.07:42:05.53#ibcon#about to write, iclass 24, count 2 2006.259.07:42:05.53#ibcon#wrote, iclass 24, count 2 2006.259.07:42:05.53#ibcon#about to read 3, iclass 24, count 2 2006.259.07:42:05.55#ibcon#read 3, iclass 24, count 2 2006.259.07:42:05.55#ibcon#about to read 4, iclass 24, count 2 2006.259.07:42:05.55#ibcon#read 4, iclass 24, count 2 2006.259.07:42:05.55#ibcon#about to read 5, iclass 24, count 2 2006.259.07:42:05.55#ibcon#read 5, iclass 24, count 2 2006.259.07:42:05.55#ibcon#about to read 6, iclass 24, count 2 2006.259.07:42:05.55#ibcon#read 6, iclass 24, count 2 2006.259.07:42:05.55#ibcon#end of sib2, iclass 24, count 2 2006.259.07:42:05.55#ibcon#*mode == 0, iclass 24, count 2 2006.259.07:42:05.55#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.259.07:42:05.55#ibcon#[27=AT04-05\r\n] 2006.259.07:42:05.55#ibcon#*before write, iclass 24, count 2 2006.259.07:42:05.55#ibcon#enter sib2, iclass 24, count 2 2006.259.07:42:05.55#ibcon#flushed, iclass 24, count 2 2006.259.07:42:05.55#ibcon#about to write, iclass 24, count 2 2006.259.07:42:05.55#ibcon#wrote, iclass 24, count 2 2006.259.07:42:05.55#ibcon#about to read 3, iclass 24, count 2 2006.259.07:42:05.58#ibcon#read 3, iclass 24, count 2 2006.259.07:42:05.58#ibcon#about to read 4, iclass 24, count 2 2006.259.07:42:05.58#ibcon#read 4, iclass 24, count 2 2006.259.07:42:05.58#ibcon#about to read 5, iclass 24, count 2 2006.259.07:42:05.58#ibcon#read 5, iclass 24, count 2 2006.259.07:42:05.58#ibcon#about to read 6, iclass 24, count 2 2006.259.07:42:05.58#ibcon#read 6, iclass 24, count 2 2006.259.07:42:05.58#ibcon#end of sib2, iclass 24, count 2 2006.259.07:42:05.58#ibcon#*after write, iclass 24, count 2 2006.259.07:42:05.58#ibcon#*before return 0, iclass 24, count 2 2006.259.07:42:05.58#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.259.07:42:05.58#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.259.07:42:05.58#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.259.07:42:05.58#ibcon#ireg 7 cls_cnt 0 2006.259.07:42:05.58#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.259.07:42:05.70#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.259.07:42:05.70#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.259.07:42:05.70#ibcon#enter wrdev, iclass 24, count 0 2006.259.07:42:05.70#ibcon#first serial, iclass 24, count 0 2006.259.07:42:05.70#ibcon#enter sib2, iclass 24, count 0 2006.259.07:42:05.70#ibcon#flushed, iclass 24, count 0 2006.259.07:42:05.70#ibcon#about to write, iclass 24, count 0 2006.259.07:42:05.70#ibcon#wrote, iclass 24, count 0 2006.259.07:42:05.70#ibcon#about to read 3, iclass 24, count 0 2006.259.07:42:05.72#ibcon#read 3, iclass 24, count 0 2006.259.07:42:05.72#ibcon#about to read 4, iclass 24, count 0 2006.259.07:42:05.72#ibcon#read 4, iclass 24, count 0 2006.259.07:42:05.72#ibcon#about to read 5, iclass 24, count 0 2006.259.07:42:05.72#ibcon#read 5, iclass 24, count 0 2006.259.07:42:05.72#ibcon#about to read 6, iclass 24, count 0 2006.259.07:42:05.72#ibcon#read 6, iclass 24, count 0 2006.259.07:42:05.72#ibcon#end of sib2, iclass 24, count 0 2006.259.07:42:05.72#ibcon#*mode == 0, iclass 24, count 0 2006.259.07:42:05.72#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.259.07:42:05.72#ibcon#[27=USB\r\n] 2006.259.07:42:05.72#ibcon#*before write, iclass 24, count 0 2006.259.07:42:05.72#ibcon#enter sib2, iclass 24, count 0 2006.259.07:42:05.72#ibcon#flushed, iclass 24, count 0 2006.259.07:42:05.72#ibcon#about to write, iclass 24, count 0 2006.259.07:42:05.72#ibcon#wrote, iclass 24, count 0 2006.259.07:42:05.72#ibcon#about to read 3, iclass 24, count 0 2006.259.07:42:05.75#ibcon#read 3, iclass 24, count 0 2006.259.07:42:05.75#ibcon#about to read 4, iclass 24, count 0 2006.259.07:42:05.75#ibcon#read 4, iclass 24, count 0 2006.259.07:42:05.75#ibcon#about to read 5, iclass 24, count 0 2006.259.07:42:05.75#ibcon#read 5, iclass 24, count 0 2006.259.07:42:05.75#ibcon#about to read 6, iclass 24, count 0 2006.259.07:42:05.75#ibcon#read 6, iclass 24, count 0 2006.259.07:42:05.75#ibcon#end of sib2, iclass 24, count 0 2006.259.07:42:05.75#ibcon#*after write, iclass 24, count 0 2006.259.07:42:05.75#ibcon#*before return 0, iclass 24, count 0 2006.259.07:42:05.75#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.259.07:42:05.75#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.259.07:42:05.75#ibcon#about to clear, iclass 24 cls_cnt 0 2006.259.07:42:05.75#ibcon#cleared, iclass 24 cls_cnt 0 2006.259.07:42:05.75$vc4f8/vblo=5,744.99 2006.259.07:42:05.75#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.259.07:42:05.75#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.259.07:42:05.75#ibcon#ireg 17 cls_cnt 0 2006.259.07:42:05.75#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.259.07:42:05.75#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.259.07:42:05.75#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.259.07:42:05.75#ibcon#enter wrdev, iclass 26, count 0 2006.259.07:42:05.75#ibcon#first serial, iclass 26, count 0 2006.259.07:42:05.75#ibcon#enter sib2, iclass 26, count 0 2006.259.07:42:05.75#ibcon#flushed, iclass 26, count 0 2006.259.07:42:05.75#ibcon#about to write, iclass 26, count 0 2006.259.07:42:05.75#ibcon#wrote, iclass 26, count 0 2006.259.07:42:05.75#ibcon#about to read 3, iclass 26, count 0 2006.259.07:42:05.77#ibcon#read 3, iclass 26, count 0 2006.259.07:42:05.77#ibcon#about to read 4, iclass 26, count 0 2006.259.07:42:05.77#ibcon#read 4, iclass 26, count 0 2006.259.07:42:05.77#ibcon#about to read 5, iclass 26, count 0 2006.259.07:42:05.77#ibcon#read 5, iclass 26, count 0 2006.259.07:42:05.77#ibcon#about to read 6, iclass 26, count 0 2006.259.07:42:05.77#ibcon#read 6, iclass 26, count 0 2006.259.07:42:05.77#ibcon#end of sib2, iclass 26, count 0 2006.259.07:42:05.77#ibcon#*mode == 0, iclass 26, count 0 2006.259.07:42:05.77#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.259.07:42:05.77#ibcon#[28=FRQ=05,744.99\r\n] 2006.259.07:42:05.77#ibcon#*before write, iclass 26, count 0 2006.259.07:42:05.77#ibcon#enter sib2, iclass 26, count 0 2006.259.07:42:05.77#ibcon#flushed, iclass 26, count 0 2006.259.07:42:05.77#ibcon#about to write, iclass 26, count 0 2006.259.07:42:05.77#ibcon#wrote, iclass 26, count 0 2006.259.07:42:05.77#ibcon#about to read 3, iclass 26, count 0 2006.259.07:42:05.81#ibcon#read 3, iclass 26, count 0 2006.259.07:42:05.81#ibcon#about to read 4, iclass 26, count 0 2006.259.07:42:05.81#ibcon#read 4, iclass 26, count 0 2006.259.07:42:05.81#ibcon#about to read 5, iclass 26, count 0 2006.259.07:42:05.81#ibcon#read 5, iclass 26, count 0 2006.259.07:42:05.81#ibcon#about to read 6, iclass 26, count 0 2006.259.07:42:05.81#ibcon#read 6, iclass 26, count 0 2006.259.07:42:05.81#ibcon#end of sib2, iclass 26, count 0 2006.259.07:42:05.81#ibcon#*after write, iclass 26, count 0 2006.259.07:42:05.81#ibcon#*before return 0, iclass 26, count 0 2006.259.07:42:05.81#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.259.07:42:05.81#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.259.07:42:05.81#ibcon#about to clear, iclass 26 cls_cnt 0 2006.259.07:42:05.81#ibcon#cleared, iclass 26 cls_cnt 0 2006.259.07:42:05.81$vc4f8/vb=5,4 2006.259.07:42:05.81#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.259.07:42:05.81#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.259.07:42:05.81#ibcon#ireg 11 cls_cnt 2 2006.259.07:42:05.81#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.259.07:42:05.87#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.259.07:42:05.87#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.259.07:42:05.87#ibcon#enter wrdev, iclass 28, count 2 2006.259.07:42:05.87#ibcon#first serial, iclass 28, count 2 2006.259.07:42:05.87#ibcon#enter sib2, iclass 28, count 2 2006.259.07:42:05.87#ibcon#flushed, iclass 28, count 2 2006.259.07:42:05.87#ibcon#about to write, iclass 28, count 2 2006.259.07:42:05.87#ibcon#wrote, iclass 28, count 2 2006.259.07:42:05.87#ibcon#about to read 3, iclass 28, count 2 2006.259.07:42:05.90#ibcon#read 3, iclass 28, count 2 2006.259.07:42:05.90#ibcon#about to read 4, iclass 28, count 2 2006.259.07:42:05.90#ibcon#read 4, iclass 28, count 2 2006.259.07:42:05.90#ibcon#about to read 5, iclass 28, count 2 2006.259.07:42:05.90#ibcon#read 5, iclass 28, count 2 2006.259.07:42:05.90#ibcon#about to read 6, iclass 28, count 2 2006.259.07:42:05.90#ibcon#read 6, iclass 28, count 2 2006.259.07:42:05.90#ibcon#end of sib2, iclass 28, count 2 2006.259.07:42:05.90#ibcon#*mode == 0, iclass 28, count 2 2006.259.07:42:05.90#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.259.07:42:05.90#ibcon#[27=AT05-04\r\n] 2006.259.07:42:05.90#ibcon#*before write, iclass 28, count 2 2006.259.07:42:05.90#ibcon#enter sib2, iclass 28, count 2 2006.259.07:42:05.90#ibcon#flushed, iclass 28, count 2 2006.259.07:42:05.90#ibcon#about to write, iclass 28, count 2 2006.259.07:42:05.90#ibcon#wrote, iclass 28, count 2 2006.259.07:42:05.90#ibcon#about to read 3, iclass 28, count 2 2006.259.07:42:05.93#ibcon#read 3, iclass 28, count 2 2006.259.07:42:05.93#ibcon#about to read 4, iclass 28, count 2 2006.259.07:42:05.93#ibcon#read 4, iclass 28, count 2 2006.259.07:42:05.93#ibcon#about to read 5, iclass 28, count 2 2006.259.07:42:05.93#ibcon#read 5, iclass 28, count 2 2006.259.07:42:05.93#ibcon#about to read 6, iclass 28, count 2 2006.259.07:42:05.93#ibcon#read 6, iclass 28, count 2 2006.259.07:42:05.93#ibcon#end of sib2, iclass 28, count 2 2006.259.07:42:05.93#ibcon#*after write, iclass 28, count 2 2006.259.07:42:05.93#ibcon#*before return 0, iclass 28, count 2 2006.259.07:42:05.93#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.259.07:42:05.93#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.259.07:42:05.93#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.259.07:42:05.93#ibcon#ireg 7 cls_cnt 0 2006.259.07:42:05.93#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.259.07:42:06.05#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.259.07:42:06.05#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.259.07:42:06.05#ibcon#enter wrdev, iclass 28, count 0 2006.259.07:42:06.05#ibcon#first serial, iclass 28, count 0 2006.259.07:42:06.05#ibcon#enter sib2, iclass 28, count 0 2006.259.07:42:06.05#ibcon#flushed, iclass 28, count 0 2006.259.07:42:06.05#ibcon#about to write, iclass 28, count 0 2006.259.07:42:06.05#ibcon#wrote, iclass 28, count 0 2006.259.07:42:06.05#ibcon#about to read 3, iclass 28, count 0 2006.259.07:42:06.07#ibcon#read 3, iclass 28, count 0 2006.259.07:42:06.07#ibcon#about to read 4, iclass 28, count 0 2006.259.07:42:06.07#ibcon#read 4, iclass 28, count 0 2006.259.07:42:06.07#ibcon#about to read 5, iclass 28, count 0 2006.259.07:42:06.07#ibcon#read 5, iclass 28, count 0 2006.259.07:42:06.07#ibcon#about to read 6, iclass 28, count 0 2006.259.07:42:06.07#ibcon#read 6, iclass 28, count 0 2006.259.07:42:06.07#ibcon#end of sib2, iclass 28, count 0 2006.259.07:42:06.07#ibcon#*mode == 0, iclass 28, count 0 2006.259.07:42:06.07#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.259.07:42:06.07#ibcon#[27=USB\r\n] 2006.259.07:42:06.07#ibcon#*before write, iclass 28, count 0 2006.259.07:42:06.07#ibcon#enter sib2, iclass 28, count 0 2006.259.07:42:06.07#ibcon#flushed, iclass 28, count 0 2006.259.07:42:06.07#ibcon#about to write, iclass 28, count 0 2006.259.07:42:06.07#ibcon#wrote, iclass 28, count 0 2006.259.07:42:06.07#ibcon#about to read 3, iclass 28, count 0 2006.259.07:42:06.10#ibcon#read 3, iclass 28, count 0 2006.259.07:42:06.10#ibcon#about to read 4, iclass 28, count 0 2006.259.07:42:06.10#ibcon#read 4, iclass 28, count 0 2006.259.07:42:06.10#ibcon#about to read 5, iclass 28, count 0 2006.259.07:42:06.10#ibcon#read 5, iclass 28, count 0 2006.259.07:42:06.10#ibcon#about to read 6, iclass 28, count 0 2006.259.07:42:06.10#ibcon#read 6, iclass 28, count 0 2006.259.07:42:06.10#ibcon#end of sib2, iclass 28, count 0 2006.259.07:42:06.10#ibcon#*after write, iclass 28, count 0 2006.259.07:42:06.10#ibcon#*before return 0, iclass 28, count 0 2006.259.07:42:06.10#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.259.07:42:06.10#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.259.07:42:06.10#ibcon#about to clear, iclass 28 cls_cnt 0 2006.259.07:42:06.10#ibcon#cleared, iclass 28 cls_cnt 0 2006.259.07:42:06.10$vc4f8/vblo=6,752.99 2006.259.07:42:06.10#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.259.07:42:06.10#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.259.07:42:06.10#ibcon#ireg 17 cls_cnt 0 2006.259.07:42:06.10#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.259.07:42:06.10#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.259.07:42:06.10#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.259.07:42:06.10#ibcon#enter wrdev, iclass 30, count 0 2006.259.07:42:06.10#ibcon#first serial, iclass 30, count 0 2006.259.07:42:06.10#ibcon#enter sib2, iclass 30, count 0 2006.259.07:42:06.10#ibcon#flushed, iclass 30, count 0 2006.259.07:42:06.10#ibcon#about to write, iclass 30, count 0 2006.259.07:42:06.10#ibcon#wrote, iclass 30, count 0 2006.259.07:42:06.10#ibcon#about to read 3, iclass 30, count 0 2006.259.07:42:06.12#ibcon#read 3, iclass 30, count 0 2006.259.07:42:06.12#ibcon#about to read 4, iclass 30, count 0 2006.259.07:42:06.12#ibcon#read 4, iclass 30, count 0 2006.259.07:42:06.12#ibcon#about to read 5, iclass 30, count 0 2006.259.07:42:06.12#ibcon#read 5, iclass 30, count 0 2006.259.07:42:06.12#ibcon#about to read 6, iclass 30, count 0 2006.259.07:42:06.12#ibcon#read 6, iclass 30, count 0 2006.259.07:42:06.12#ibcon#end of sib2, iclass 30, count 0 2006.259.07:42:06.12#ibcon#*mode == 0, iclass 30, count 0 2006.259.07:42:06.12#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.259.07:42:06.12#ibcon#[28=FRQ=06,752.99\r\n] 2006.259.07:42:06.12#ibcon#*before write, iclass 30, count 0 2006.259.07:42:06.12#ibcon#enter sib2, iclass 30, count 0 2006.259.07:42:06.12#ibcon#flushed, iclass 30, count 0 2006.259.07:42:06.12#ibcon#about to write, iclass 30, count 0 2006.259.07:42:06.12#ibcon#wrote, iclass 30, count 0 2006.259.07:42:06.12#ibcon#about to read 3, iclass 30, count 0 2006.259.07:42:06.16#ibcon#read 3, iclass 30, count 0 2006.259.07:42:06.16#ibcon#about to read 4, iclass 30, count 0 2006.259.07:42:06.16#ibcon#read 4, iclass 30, count 0 2006.259.07:42:06.16#ibcon#about to read 5, iclass 30, count 0 2006.259.07:42:06.16#ibcon#read 5, iclass 30, count 0 2006.259.07:42:06.16#ibcon#about to read 6, iclass 30, count 0 2006.259.07:42:06.16#ibcon#read 6, iclass 30, count 0 2006.259.07:42:06.16#ibcon#end of sib2, iclass 30, count 0 2006.259.07:42:06.16#ibcon#*after write, iclass 30, count 0 2006.259.07:42:06.16#ibcon#*before return 0, iclass 30, count 0 2006.259.07:42:06.16#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.259.07:42:06.16#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.259.07:42:06.16#ibcon#about to clear, iclass 30 cls_cnt 0 2006.259.07:42:06.16#ibcon#cleared, iclass 30 cls_cnt 0 2006.259.07:42:06.16$vc4f8/vb=6,4 2006.259.07:42:06.16#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.259.07:42:06.16#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.259.07:42:06.16#ibcon#ireg 11 cls_cnt 2 2006.259.07:42:06.16#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.259.07:42:06.22#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.259.07:42:06.22#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.259.07:42:06.22#ibcon#enter wrdev, iclass 32, count 2 2006.259.07:42:06.22#ibcon#first serial, iclass 32, count 2 2006.259.07:42:06.22#ibcon#enter sib2, iclass 32, count 2 2006.259.07:42:06.22#ibcon#flushed, iclass 32, count 2 2006.259.07:42:06.22#ibcon#about to write, iclass 32, count 2 2006.259.07:42:06.22#ibcon#wrote, iclass 32, count 2 2006.259.07:42:06.22#ibcon#about to read 3, iclass 32, count 2 2006.259.07:42:06.24#ibcon#read 3, iclass 32, count 2 2006.259.07:42:06.24#ibcon#about to read 4, iclass 32, count 2 2006.259.07:42:06.24#ibcon#read 4, iclass 32, count 2 2006.259.07:42:06.24#ibcon#about to read 5, iclass 32, count 2 2006.259.07:42:06.24#ibcon#read 5, iclass 32, count 2 2006.259.07:42:06.24#ibcon#about to read 6, iclass 32, count 2 2006.259.07:42:06.24#ibcon#read 6, iclass 32, count 2 2006.259.07:42:06.24#ibcon#end of sib2, iclass 32, count 2 2006.259.07:42:06.24#ibcon#*mode == 0, iclass 32, count 2 2006.259.07:42:06.24#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.259.07:42:06.24#ibcon#[27=AT06-04\r\n] 2006.259.07:42:06.24#ibcon#*before write, iclass 32, count 2 2006.259.07:42:06.24#ibcon#enter sib2, iclass 32, count 2 2006.259.07:42:06.24#ibcon#flushed, iclass 32, count 2 2006.259.07:42:06.24#ibcon#about to write, iclass 32, count 2 2006.259.07:42:06.24#ibcon#wrote, iclass 32, count 2 2006.259.07:42:06.24#ibcon#about to read 3, iclass 32, count 2 2006.259.07:42:06.27#ibcon#read 3, iclass 32, count 2 2006.259.07:42:06.27#ibcon#about to read 4, iclass 32, count 2 2006.259.07:42:06.27#ibcon#read 4, iclass 32, count 2 2006.259.07:42:06.27#ibcon#about to read 5, iclass 32, count 2 2006.259.07:42:06.27#ibcon#read 5, iclass 32, count 2 2006.259.07:42:06.27#ibcon#about to read 6, iclass 32, count 2 2006.259.07:42:06.27#ibcon#read 6, iclass 32, count 2 2006.259.07:42:06.27#ibcon#end of sib2, iclass 32, count 2 2006.259.07:42:06.27#ibcon#*after write, iclass 32, count 2 2006.259.07:42:06.27#ibcon#*before return 0, iclass 32, count 2 2006.259.07:42:06.27#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.259.07:42:06.27#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.259.07:42:06.27#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.259.07:42:06.27#ibcon#ireg 7 cls_cnt 0 2006.259.07:42:06.27#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.259.07:42:06.39#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.259.07:42:06.39#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.259.07:42:06.39#ibcon#enter wrdev, iclass 32, count 0 2006.259.07:42:06.39#ibcon#first serial, iclass 32, count 0 2006.259.07:42:06.39#ibcon#enter sib2, iclass 32, count 0 2006.259.07:42:06.39#ibcon#flushed, iclass 32, count 0 2006.259.07:42:06.39#ibcon#about to write, iclass 32, count 0 2006.259.07:42:06.39#ibcon#wrote, iclass 32, count 0 2006.259.07:42:06.39#ibcon#about to read 3, iclass 32, count 0 2006.259.07:42:06.41#ibcon#read 3, iclass 32, count 0 2006.259.07:42:06.41#ibcon#about to read 4, iclass 32, count 0 2006.259.07:42:06.41#ibcon#read 4, iclass 32, count 0 2006.259.07:42:06.41#ibcon#about to read 5, iclass 32, count 0 2006.259.07:42:06.41#ibcon#read 5, iclass 32, count 0 2006.259.07:42:06.41#ibcon#about to read 6, iclass 32, count 0 2006.259.07:42:06.41#ibcon#read 6, iclass 32, count 0 2006.259.07:42:06.41#ibcon#end of sib2, iclass 32, count 0 2006.259.07:42:06.41#ibcon#*mode == 0, iclass 32, count 0 2006.259.07:42:06.41#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.259.07:42:06.41#ibcon#[27=USB\r\n] 2006.259.07:42:06.41#ibcon#*before write, iclass 32, count 0 2006.259.07:42:06.41#ibcon#enter sib2, iclass 32, count 0 2006.259.07:42:06.41#ibcon#flushed, iclass 32, count 0 2006.259.07:42:06.41#ibcon#about to write, iclass 32, count 0 2006.259.07:42:06.41#ibcon#wrote, iclass 32, count 0 2006.259.07:42:06.41#ibcon#about to read 3, iclass 32, count 0 2006.259.07:42:06.44#ibcon#read 3, iclass 32, count 0 2006.259.07:42:06.44#ibcon#about to read 4, iclass 32, count 0 2006.259.07:42:06.44#ibcon#read 4, iclass 32, count 0 2006.259.07:42:06.44#ibcon#about to read 5, iclass 32, count 0 2006.259.07:42:06.44#ibcon#read 5, iclass 32, count 0 2006.259.07:42:06.44#ibcon#about to read 6, iclass 32, count 0 2006.259.07:42:06.44#ibcon#read 6, iclass 32, count 0 2006.259.07:42:06.44#ibcon#end of sib2, iclass 32, count 0 2006.259.07:42:06.44#ibcon#*after write, iclass 32, count 0 2006.259.07:42:06.44#ibcon#*before return 0, iclass 32, count 0 2006.259.07:42:06.44#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.259.07:42:06.44#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.259.07:42:06.44#ibcon#about to clear, iclass 32 cls_cnt 0 2006.259.07:42:06.44#ibcon#cleared, iclass 32 cls_cnt 0 2006.259.07:42:06.44$vc4f8/vabw=wide 2006.259.07:42:06.44#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.259.07:42:06.44#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.259.07:42:06.44#ibcon#ireg 8 cls_cnt 0 2006.259.07:42:06.44#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.259.07:42:06.44#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.259.07:42:06.44#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.259.07:42:06.44#ibcon#enter wrdev, iclass 34, count 0 2006.259.07:42:06.44#ibcon#first serial, iclass 34, count 0 2006.259.07:42:06.44#ibcon#enter sib2, iclass 34, count 0 2006.259.07:42:06.44#ibcon#flushed, iclass 34, count 0 2006.259.07:42:06.44#ibcon#about to write, iclass 34, count 0 2006.259.07:42:06.44#ibcon#wrote, iclass 34, count 0 2006.259.07:42:06.44#ibcon#about to read 3, iclass 34, count 0 2006.259.07:42:06.46#ibcon#read 3, iclass 34, count 0 2006.259.07:42:06.46#ibcon#about to read 4, iclass 34, count 0 2006.259.07:42:06.46#ibcon#read 4, iclass 34, count 0 2006.259.07:42:06.46#ibcon#about to read 5, iclass 34, count 0 2006.259.07:42:06.46#ibcon#read 5, iclass 34, count 0 2006.259.07:42:06.46#ibcon#about to read 6, iclass 34, count 0 2006.259.07:42:06.46#ibcon#read 6, iclass 34, count 0 2006.259.07:42:06.46#ibcon#end of sib2, iclass 34, count 0 2006.259.07:42:06.46#ibcon#*mode == 0, iclass 34, count 0 2006.259.07:42:06.46#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.259.07:42:06.46#ibcon#[25=BW32\r\n] 2006.259.07:42:06.46#ibcon#*before write, iclass 34, count 0 2006.259.07:42:06.46#ibcon#enter sib2, iclass 34, count 0 2006.259.07:42:06.46#ibcon#flushed, iclass 34, count 0 2006.259.07:42:06.46#ibcon#about to write, iclass 34, count 0 2006.259.07:42:06.46#ibcon#wrote, iclass 34, count 0 2006.259.07:42:06.46#ibcon#about to read 3, iclass 34, count 0 2006.259.07:42:06.49#ibcon#read 3, iclass 34, count 0 2006.259.07:42:06.49#ibcon#about to read 4, iclass 34, count 0 2006.259.07:42:06.49#ibcon#read 4, iclass 34, count 0 2006.259.07:42:06.49#ibcon#about to read 5, iclass 34, count 0 2006.259.07:42:06.49#ibcon#read 5, iclass 34, count 0 2006.259.07:42:06.49#ibcon#about to read 6, iclass 34, count 0 2006.259.07:42:06.49#ibcon#read 6, iclass 34, count 0 2006.259.07:42:06.49#ibcon#end of sib2, iclass 34, count 0 2006.259.07:42:06.49#ibcon#*after write, iclass 34, count 0 2006.259.07:42:06.49#ibcon#*before return 0, iclass 34, count 0 2006.259.07:42:06.49#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.259.07:42:06.49#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.259.07:42:06.49#ibcon#about to clear, iclass 34 cls_cnt 0 2006.259.07:42:06.49#ibcon#cleared, iclass 34 cls_cnt 0 2006.259.07:42:06.49$vc4f8/vbbw=wide 2006.259.07:42:06.49#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.259.07:42:06.49#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.259.07:42:06.49#ibcon#ireg 8 cls_cnt 0 2006.259.07:42:06.49#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.259.07:42:06.56#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.259.07:42:06.56#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.259.07:42:06.56#ibcon#enter wrdev, iclass 36, count 0 2006.259.07:42:06.56#ibcon#first serial, iclass 36, count 0 2006.259.07:42:06.56#ibcon#enter sib2, iclass 36, count 0 2006.259.07:42:06.56#ibcon#flushed, iclass 36, count 0 2006.259.07:42:06.56#ibcon#about to write, iclass 36, count 0 2006.259.07:42:06.56#ibcon#wrote, iclass 36, count 0 2006.259.07:42:06.56#ibcon#about to read 3, iclass 36, count 0 2006.259.07:42:06.58#ibcon#read 3, iclass 36, count 0 2006.259.07:42:06.58#ibcon#about to read 4, iclass 36, count 0 2006.259.07:42:06.58#ibcon#read 4, iclass 36, count 0 2006.259.07:42:06.58#ibcon#about to read 5, iclass 36, count 0 2006.259.07:42:06.58#ibcon#read 5, iclass 36, count 0 2006.259.07:42:06.58#ibcon#about to read 6, iclass 36, count 0 2006.259.07:42:06.58#ibcon#read 6, iclass 36, count 0 2006.259.07:42:06.58#ibcon#end of sib2, iclass 36, count 0 2006.259.07:42:06.58#ibcon#*mode == 0, iclass 36, count 0 2006.259.07:42:06.58#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.259.07:42:06.58#ibcon#[27=BW32\r\n] 2006.259.07:42:06.58#ibcon#*before write, iclass 36, count 0 2006.259.07:42:06.58#ibcon#enter sib2, iclass 36, count 0 2006.259.07:42:06.58#ibcon#flushed, iclass 36, count 0 2006.259.07:42:06.58#ibcon#about to write, iclass 36, count 0 2006.259.07:42:06.58#ibcon#wrote, iclass 36, count 0 2006.259.07:42:06.58#ibcon#about to read 3, iclass 36, count 0 2006.259.07:42:06.61#ibcon#read 3, iclass 36, count 0 2006.259.07:42:06.61#ibcon#about to read 4, iclass 36, count 0 2006.259.07:42:06.61#ibcon#read 4, iclass 36, count 0 2006.259.07:42:06.61#ibcon#about to read 5, iclass 36, count 0 2006.259.07:42:06.61#ibcon#read 5, iclass 36, count 0 2006.259.07:42:06.61#ibcon#about to read 6, iclass 36, count 0 2006.259.07:42:06.61#ibcon#read 6, iclass 36, count 0 2006.259.07:42:06.61#ibcon#end of sib2, iclass 36, count 0 2006.259.07:42:06.61#ibcon#*after write, iclass 36, count 0 2006.259.07:42:06.61#ibcon#*before return 0, iclass 36, count 0 2006.259.07:42:06.61#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.259.07:42:06.61#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.259.07:42:06.61#ibcon#about to clear, iclass 36 cls_cnt 0 2006.259.07:42:06.61#ibcon#cleared, iclass 36 cls_cnt 0 2006.259.07:42:06.61$4f8m12a/ifd4f 2006.259.07:42:06.61$ifd4f/lo= 2006.259.07:42:06.61$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.259.07:42:06.61$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.259.07:42:06.61$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.259.07:42:06.61$ifd4f/patch= 2006.259.07:42:06.61$ifd4f/patch=lo1,a1,a2,a3,a4 2006.259.07:42:06.61$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.259.07:42:06.61$ifd4f/patch=lo3,a5,a6,a7,a8 2006.259.07:42:06.61$4f8m12a/"form=m,16.000,1:2 2006.259.07:42:06.61$4f8m12a/"tpicd 2006.259.07:42:06.61$4f8m12a/echo=off 2006.259.07:42:06.61$4f8m12a/xlog=off 2006.259.07:42:06.61:!2006.259.07:42:30 2006.259.07:42:12.14#trakl#Source acquired 2006.259.07:42:12.14#flagr#flagr/antenna,acquired 2006.259.07:42:30.00:preob 2006.259.07:42:31.14/onsource/TRACKING 2006.259.07:42:31.14:!2006.259.07:42:40 2006.259.07:42:40.00:data_valid=on 2006.259.07:42:40.00:midob 2006.259.07:42:40.14/onsource/TRACKING 2006.259.07:42:40.14/wx/22.27,1012.9,85 2006.259.07:42:40.20/cable/+6.4585E-03 2006.259.07:42:41.29/va/01,08,usb,yes,30,32 2006.259.07:42:41.29/va/02,07,usb,yes,30,32 2006.259.07:42:41.29/va/03,08,usb,yes,23,23 2006.259.07:42:41.29/va/04,07,usb,yes,31,34 2006.259.07:42:41.29/va/05,07,usb,yes,35,37 2006.259.07:42:41.29/va/06,06,usb,yes,34,34 2006.259.07:42:41.29/va/07,06,usb,yes,35,35 2006.259.07:42:41.29/va/08,06,usb,yes,37,36 2006.259.07:42:41.52/valo/01,532.99,yes,locked 2006.259.07:42:41.52/valo/02,572.99,yes,locked 2006.259.07:42:41.52/valo/03,672.99,yes,locked 2006.259.07:42:41.52/valo/04,832.99,yes,locked 2006.259.07:42:41.52/valo/05,652.99,yes,locked 2006.259.07:42:41.52/valo/06,772.99,yes,locked 2006.259.07:42:41.52/valo/07,832.99,yes,locked 2006.259.07:42:41.52/valo/08,852.99,yes,locked 2006.259.07:42:42.61/vb/01,04,usb,yes,30,29 2006.259.07:42:42.61/vb/02,05,usb,yes,28,29 2006.259.07:42:42.61/vb/03,04,usb,yes,28,32 2006.259.07:42:42.61/vb/04,05,usb,yes,25,26 2006.259.07:42:42.61/vb/05,04,usb,yes,27,31 2006.259.07:42:42.61/vb/06,04,usb,yes,28,31 2006.259.07:42:42.61/vb/07,04,usb,yes,31,30 2006.259.07:42:42.61/vb/08,04,usb,yes,28,31 2006.259.07:42:42.85/vblo/01,632.99,yes,locked 2006.259.07:42:42.85/vblo/02,640.99,yes,locked 2006.259.07:42:42.85/vblo/03,656.99,yes,locked 2006.259.07:42:42.85/vblo/04,712.99,yes,locked 2006.259.07:42:42.85/vblo/05,744.99,yes,locked 2006.259.07:42:42.85/vblo/06,752.99,yes,locked 2006.259.07:42:42.85/vblo/07,734.99,yes,locked 2006.259.07:42:42.85/vblo/08,744.99,yes,locked 2006.259.07:42:43.00/vabw/8 2006.259.07:42:43.15/vbbw/8 2006.259.07:42:43.24/xfe/off,on,15.2 2006.259.07:42:43.61/ifatt/23,28,28,28 2006.259.07:42:44.08/fmout-gps/S +4.49E-07 2006.259.07:42:44.12:!2006.259.07:43:40 2006.259.07:43:40.00:data_valid=off 2006.259.07:43:40.00:postob 2006.259.07:43:40.11/cable/+6.4586E-03 2006.259.07:43:40.11/wx/22.26,1012.9,85 2006.259.07:43:41.08/fmout-gps/S +4.48E-07 2006.259.07:43:41.08:scan_name=259-0744,k06259,60 2006.259.07:43:41.08:source=nrao512,164029.63,394646.0,2000.0,ccw 2006.259.07:43:41.14#flagr#flagr/antenna,new-source 2006.259.07:43:42.14:checkk5 2006.259.07:43:42.53/chk_autoobs//k5ts1/ autoobs is running! 2006.259.07:43:42.93/chk_autoobs//k5ts2/ autoobs is running! 2006.259.07:43:43.34/chk_autoobs//k5ts3/ autoobs is running! 2006.259.07:43:43.73/chk_autoobs//k5ts4/ autoobs is running! 2006.259.07:43:44.14/chk_obsdata//k5ts1/T2590742??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.259.07:43:44.53/chk_obsdata//k5ts2/T2590742??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.259.07:43:44.92/chk_obsdata//k5ts3/T2590742??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.259.07:43:45.62/chk_obsdata//k5ts4/T2590742??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.259.07:43:46.63/k5log//k5ts1_log_newline 2006.259.07:43:47.41/k5log//k5ts2_log_newline 2006.259.07:43:48.22/k5log//k5ts3_log_newline 2006.259.07:43:48.98/k5log//k5ts4_log_newline 2006.259.07:43:49.00/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.259.07:43:49.00:4f8m12a=1 2006.259.07:43:49.00$4f8m12a/echo=on 2006.259.07:43:49.00$4f8m12a/pcalon 2006.259.07:43:49.00$pcalon/"no phase cal control is implemented here 2006.259.07:43:49.00$4f8m12a/"tpicd=stop 2006.259.07:43:49.00$4f8m12a/vc4f8 2006.259.07:43:49.00$vc4f8/valo=1,532.99 2006.259.07:43:49.01#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.259.07:43:49.01#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.259.07:43:49.01#ibcon#ireg 17 cls_cnt 0 2006.259.07:43:49.01#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.259.07:43:49.01#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.259.07:43:49.01#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.259.07:43:49.01#ibcon#enter wrdev, iclass 38, count 0 2006.259.07:43:49.01#ibcon#first serial, iclass 38, count 0 2006.259.07:43:49.01#ibcon#enter sib2, iclass 38, count 0 2006.259.07:43:49.01#ibcon#flushed, iclass 38, count 0 2006.259.07:43:49.01#ibcon#about to write, iclass 38, count 0 2006.259.07:43:49.01#ibcon#wrote, iclass 38, count 0 2006.259.07:43:49.01#ibcon#about to read 3, iclass 38, count 0 2006.259.07:43:49.05#ibcon#read 3, iclass 38, count 0 2006.259.07:43:49.05#ibcon#about to read 4, iclass 38, count 0 2006.259.07:43:49.05#ibcon#read 4, iclass 38, count 0 2006.259.07:43:49.05#ibcon#about to read 5, iclass 38, count 0 2006.259.07:43:49.05#ibcon#read 5, iclass 38, count 0 2006.259.07:43:49.05#ibcon#about to read 6, iclass 38, count 0 2006.259.07:43:49.05#ibcon#read 6, iclass 38, count 0 2006.259.07:43:49.05#ibcon#end of sib2, iclass 38, count 0 2006.259.07:43:49.05#ibcon#*mode == 0, iclass 38, count 0 2006.259.07:43:49.05#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.259.07:43:49.05#ibcon#[26=FRQ=01,532.99\r\n] 2006.259.07:43:49.05#ibcon#*before write, iclass 38, count 0 2006.259.07:43:49.05#ibcon#enter sib2, iclass 38, count 0 2006.259.07:43:49.05#ibcon#flushed, iclass 38, count 0 2006.259.07:43:49.05#ibcon#about to write, iclass 38, count 0 2006.259.07:43:49.05#ibcon#wrote, iclass 38, count 0 2006.259.07:43:49.05#ibcon#about to read 3, iclass 38, count 0 2006.259.07:43:49.10#ibcon#read 3, iclass 38, count 0 2006.259.07:43:49.10#ibcon#about to read 4, iclass 38, count 0 2006.259.07:43:49.10#ibcon#read 4, iclass 38, count 0 2006.259.07:43:49.10#ibcon#about to read 5, iclass 38, count 0 2006.259.07:43:49.10#ibcon#read 5, iclass 38, count 0 2006.259.07:43:49.10#ibcon#about to read 6, iclass 38, count 0 2006.259.07:43:49.10#ibcon#read 6, iclass 38, count 0 2006.259.07:43:49.10#ibcon#end of sib2, iclass 38, count 0 2006.259.07:43:49.10#ibcon#*after write, iclass 38, count 0 2006.259.07:43:49.10#ibcon#*before return 0, iclass 38, count 0 2006.259.07:43:49.10#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.259.07:43:49.10#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.259.07:43:49.10#ibcon#about to clear, iclass 38 cls_cnt 0 2006.259.07:43:49.10#ibcon#cleared, iclass 38 cls_cnt 0 2006.259.07:43:49.10$vc4f8/va=1,8 2006.259.07:43:49.10#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.259.07:43:49.10#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.259.07:43:49.10#ibcon#ireg 11 cls_cnt 2 2006.259.07:43:49.10#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.259.07:43:49.10#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.259.07:43:49.10#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.259.07:43:49.10#ibcon#enter wrdev, iclass 40, count 2 2006.259.07:43:49.10#ibcon#first serial, iclass 40, count 2 2006.259.07:43:49.10#ibcon#enter sib2, iclass 40, count 2 2006.259.07:43:49.10#ibcon#flushed, iclass 40, count 2 2006.259.07:43:49.10#ibcon#about to write, iclass 40, count 2 2006.259.07:43:49.10#ibcon#wrote, iclass 40, count 2 2006.259.07:43:49.10#ibcon#about to read 3, iclass 40, count 2 2006.259.07:43:49.12#ibcon#read 3, iclass 40, count 2 2006.259.07:43:49.12#ibcon#about to read 4, iclass 40, count 2 2006.259.07:43:49.12#ibcon#read 4, iclass 40, count 2 2006.259.07:43:49.12#ibcon#about to read 5, iclass 40, count 2 2006.259.07:43:49.12#ibcon#read 5, iclass 40, count 2 2006.259.07:43:49.12#ibcon#about to read 6, iclass 40, count 2 2006.259.07:43:49.12#ibcon#read 6, iclass 40, count 2 2006.259.07:43:49.12#ibcon#end of sib2, iclass 40, count 2 2006.259.07:43:49.12#ibcon#*mode == 0, iclass 40, count 2 2006.259.07:43:49.12#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.259.07:43:49.12#ibcon#[25=AT01-08\r\n] 2006.259.07:43:49.12#ibcon#*before write, iclass 40, count 2 2006.259.07:43:49.12#ibcon#enter sib2, iclass 40, count 2 2006.259.07:43:49.12#ibcon#flushed, iclass 40, count 2 2006.259.07:43:49.12#ibcon#about to write, iclass 40, count 2 2006.259.07:43:49.12#ibcon#wrote, iclass 40, count 2 2006.259.07:43:49.12#ibcon#about to read 3, iclass 40, count 2 2006.259.07:43:49.15#ibcon#read 3, iclass 40, count 2 2006.259.07:43:49.15#ibcon#about to read 4, iclass 40, count 2 2006.259.07:43:49.15#ibcon#read 4, iclass 40, count 2 2006.259.07:43:49.15#ibcon#about to read 5, iclass 40, count 2 2006.259.07:43:49.15#ibcon#read 5, iclass 40, count 2 2006.259.07:43:49.15#ibcon#about to read 6, iclass 40, count 2 2006.259.07:43:49.15#ibcon#read 6, iclass 40, count 2 2006.259.07:43:49.15#ibcon#end of sib2, iclass 40, count 2 2006.259.07:43:49.15#ibcon#*after write, iclass 40, count 2 2006.259.07:43:49.15#ibcon#*before return 0, iclass 40, count 2 2006.259.07:43:49.15#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.259.07:43:49.15#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.259.07:43:49.15#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.259.07:43:49.15#ibcon#ireg 7 cls_cnt 0 2006.259.07:43:49.15#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.259.07:43:49.27#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.259.07:43:49.27#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.259.07:43:49.27#ibcon#enter wrdev, iclass 40, count 0 2006.259.07:43:49.27#ibcon#first serial, iclass 40, count 0 2006.259.07:43:49.27#ibcon#enter sib2, iclass 40, count 0 2006.259.07:43:49.27#ibcon#flushed, iclass 40, count 0 2006.259.07:43:49.27#ibcon#about to write, iclass 40, count 0 2006.259.07:43:49.27#ibcon#wrote, iclass 40, count 0 2006.259.07:43:49.27#ibcon#about to read 3, iclass 40, count 0 2006.259.07:43:49.29#ibcon#read 3, iclass 40, count 0 2006.259.07:43:49.29#ibcon#about to read 4, iclass 40, count 0 2006.259.07:43:49.29#ibcon#read 4, iclass 40, count 0 2006.259.07:43:49.29#ibcon#about to read 5, iclass 40, count 0 2006.259.07:43:49.29#ibcon#read 5, iclass 40, count 0 2006.259.07:43:49.29#ibcon#about to read 6, iclass 40, count 0 2006.259.07:43:49.29#ibcon#read 6, iclass 40, count 0 2006.259.07:43:49.29#ibcon#end of sib2, iclass 40, count 0 2006.259.07:43:49.29#ibcon#*mode == 0, iclass 40, count 0 2006.259.07:43:49.29#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.259.07:43:49.29#ibcon#[25=USB\r\n] 2006.259.07:43:49.29#ibcon#*before write, iclass 40, count 0 2006.259.07:43:49.29#ibcon#enter sib2, iclass 40, count 0 2006.259.07:43:49.29#ibcon#flushed, iclass 40, count 0 2006.259.07:43:49.29#ibcon#about to write, iclass 40, count 0 2006.259.07:43:49.29#ibcon#wrote, iclass 40, count 0 2006.259.07:43:49.29#ibcon#about to read 3, iclass 40, count 0 2006.259.07:43:49.32#ibcon#read 3, iclass 40, count 0 2006.259.07:43:49.32#ibcon#about to read 4, iclass 40, count 0 2006.259.07:43:49.32#ibcon#read 4, iclass 40, count 0 2006.259.07:43:49.32#ibcon#about to read 5, iclass 40, count 0 2006.259.07:43:49.32#ibcon#read 5, iclass 40, count 0 2006.259.07:43:49.32#ibcon#about to read 6, iclass 40, count 0 2006.259.07:43:49.32#ibcon#read 6, iclass 40, count 0 2006.259.07:43:49.32#ibcon#end of sib2, iclass 40, count 0 2006.259.07:43:49.32#ibcon#*after write, iclass 40, count 0 2006.259.07:43:49.32#ibcon#*before return 0, iclass 40, count 0 2006.259.07:43:49.32#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.259.07:43:49.32#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.259.07:43:49.32#ibcon#about to clear, iclass 40 cls_cnt 0 2006.259.07:43:49.32#ibcon#cleared, iclass 40 cls_cnt 0 2006.259.07:43:49.32$vc4f8/valo=2,572.99 2006.259.07:43:49.32#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.259.07:43:49.32#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.259.07:43:49.32#ibcon#ireg 17 cls_cnt 0 2006.259.07:43:49.32#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.259.07:43:49.32#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.259.07:43:49.32#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.259.07:43:49.32#ibcon#enter wrdev, iclass 4, count 0 2006.259.07:43:49.32#ibcon#first serial, iclass 4, count 0 2006.259.07:43:49.32#ibcon#enter sib2, iclass 4, count 0 2006.259.07:43:49.32#ibcon#flushed, iclass 4, count 0 2006.259.07:43:49.32#ibcon#about to write, iclass 4, count 0 2006.259.07:43:49.32#ibcon#wrote, iclass 4, count 0 2006.259.07:43:49.32#ibcon#about to read 3, iclass 4, count 0 2006.259.07:43:49.34#ibcon#read 3, iclass 4, count 0 2006.259.07:43:49.34#ibcon#about to read 4, iclass 4, count 0 2006.259.07:43:49.34#ibcon#read 4, iclass 4, count 0 2006.259.07:43:49.34#ibcon#about to read 5, iclass 4, count 0 2006.259.07:43:49.34#ibcon#read 5, iclass 4, count 0 2006.259.07:43:49.34#ibcon#about to read 6, iclass 4, count 0 2006.259.07:43:49.34#ibcon#read 6, iclass 4, count 0 2006.259.07:43:49.34#ibcon#end of sib2, iclass 4, count 0 2006.259.07:43:49.34#ibcon#*mode == 0, iclass 4, count 0 2006.259.07:43:49.34#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.259.07:43:49.34#ibcon#[26=FRQ=02,572.99\r\n] 2006.259.07:43:49.34#ibcon#*before write, iclass 4, count 0 2006.259.07:43:49.34#ibcon#enter sib2, iclass 4, count 0 2006.259.07:43:49.34#ibcon#flushed, iclass 4, count 0 2006.259.07:43:49.34#ibcon#about to write, iclass 4, count 0 2006.259.07:43:49.34#ibcon#wrote, iclass 4, count 0 2006.259.07:43:49.34#ibcon#about to read 3, iclass 4, count 0 2006.259.07:43:49.38#ibcon#read 3, iclass 4, count 0 2006.259.07:43:49.38#ibcon#about to read 4, iclass 4, count 0 2006.259.07:43:49.38#ibcon#read 4, iclass 4, count 0 2006.259.07:43:49.38#ibcon#about to read 5, iclass 4, count 0 2006.259.07:43:49.38#ibcon#read 5, iclass 4, count 0 2006.259.07:43:49.38#ibcon#about to read 6, iclass 4, count 0 2006.259.07:43:49.38#ibcon#read 6, iclass 4, count 0 2006.259.07:43:49.38#ibcon#end of sib2, iclass 4, count 0 2006.259.07:43:49.38#ibcon#*after write, iclass 4, count 0 2006.259.07:43:49.38#ibcon#*before return 0, iclass 4, count 0 2006.259.07:43:49.38#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.259.07:43:49.38#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.259.07:43:49.38#ibcon#about to clear, iclass 4 cls_cnt 0 2006.259.07:43:49.38#ibcon#cleared, iclass 4 cls_cnt 0 2006.259.07:43:49.38$vc4f8/va=2,7 2006.259.07:43:49.38#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.259.07:43:49.38#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.259.07:43:49.38#ibcon#ireg 11 cls_cnt 2 2006.259.07:43:49.38#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.259.07:43:49.44#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.259.07:43:49.44#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.259.07:43:49.44#ibcon#enter wrdev, iclass 6, count 2 2006.259.07:43:49.44#ibcon#first serial, iclass 6, count 2 2006.259.07:43:49.44#ibcon#enter sib2, iclass 6, count 2 2006.259.07:43:49.44#ibcon#flushed, iclass 6, count 2 2006.259.07:43:49.44#ibcon#about to write, iclass 6, count 2 2006.259.07:43:49.44#ibcon#wrote, iclass 6, count 2 2006.259.07:43:49.44#ibcon#about to read 3, iclass 6, count 2 2006.259.07:43:49.46#ibcon#read 3, iclass 6, count 2 2006.259.07:43:49.46#ibcon#about to read 4, iclass 6, count 2 2006.259.07:43:49.46#ibcon#read 4, iclass 6, count 2 2006.259.07:43:49.46#ibcon#about to read 5, iclass 6, count 2 2006.259.07:43:49.46#ibcon#read 5, iclass 6, count 2 2006.259.07:43:49.46#ibcon#about to read 6, iclass 6, count 2 2006.259.07:43:49.46#ibcon#read 6, iclass 6, count 2 2006.259.07:43:49.46#ibcon#end of sib2, iclass 6, count 2 2006.259.07:43:49.46#ibcon#*mode == 0, iclass 6, count 2 2006.259.07:43:49.46#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.259.07:43:49.46#ibcon#[25=AT02-07\r\n] 2006.259.07:43:49.46#ibcon#*before write, iclass 6, count 2 2006.259.07:43:49.46#ibcon#enter sib2, iclass 6, count 2 2006.259.07:43:49.46#ibcon#flushed, iclass 6, count 2 2006.259.07:43:49.46#ibcon#about to write, iclass 6, count 2 2006.259.07:43:49.46#ibcon#wrote, iclass 6, count 2 2006.259.07:43:49.46#ibcon#about to read 3, iclass 6, count 2 2006.259.07:43:49.50#ibcon#read 3, iclass 6, count 2 2006.259.07:43:49.50#ibcon#about to read 4, iclass 6, count 2 2006.259.07:43:49.50#ibcon#read 4, iclass 6, count 2 2006.259.07:43:49.50#ibcon#about to read 5, iclass 6, count 2 2006.259.07:43:49.50#ibcon#read 5, iclass 6, count 2 2006.259.07:43:49.50#ibcon#about to read 6, iclass 6, count 2 2006.259.07:43:49.50#ibcon#read 6, iclass 6, count 2 2006.259.07:43:49.50#ibcon#end of sib2, iclass 6, count 2 2006.259.07:43:49.50#ibcon#*after write, iclass 6, count 2 2006.259.07:43:49.50#ibcon#*before return 0, iclass 6, count 2 2006.259.07:43:49.50#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.259.07:43:49.50#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.259.07:43:49.50#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.259.07:43:49.50#ibcon#ireg 7 cls_cnt 0 2006.259.07:43:49.50#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.259.07:43:49.62#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.259.07:43:49.62#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.259.07:43:49.62#ibcon#enter wrdev, iclass 6, count 0 2006.259.07:43:49.62#ibcon#first serial, iclass 6, count 0 2006.259.07:43:49.62#ibcon#enter sib2, iclass 6, count 0 2006.259.07:43:49.62#ibcon#flushed, iclass 6, count 0 2006.259.07:43:49.62#ibcon#about to write, iclass 6, count 0 2006.259.07:43:49.62#ibcon#wrote, iclass 6, count 0 2006.259.07:43:49.62#ibcon#about to read 3, iclass 6, count 0 2006.259.07:43:49.64#ibcon#read 3, iclass 6, count 0 2006.259.07:43:49.64#ibcon#about to read 4, iclass 6, count 0 2006.259.07:43:49.64#ibcon#read 4, iclass 6, count 0 2006.259.07:43:49.64#ibcon#about to read 5, iclass 6, count 0 2006.259.07:43:49.64#ibcon#read 5, iclass 6, count 0 2006.259.07:43:49.64#ibcon#about to read 6, iclass 6, count 0 2006.259.07:43:49.64#ibcon#read 6, iclass 6, count 0 2006.259.07:43:49.64#ibcon#end of sib2, iclass 6, count 0 2006.259.07:43:49.64#ibcon#*mode == 0, iclass 6, count 0 2006.259.07:43:49.64#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.259.07:43:49.64#ibcon#[25=USB\r\n] 2006.259.07:43:49.64#ibcon#*before write, iclass 6, count 0 2006.259.07:43:49.64#ibcon#enter sib2, iclass 6, count 0 2006.259.07:43:49.64#ibcon#flushed, iclass 6, count 0 2006.259.07:43:49.64#ibcon#about to write, iclass 6, count 0 2006.259.07:43:49.64#ibcon#wrote, iclass 6, count 0 2006.259.07:43:49.64#ibcon#about to read 3, iclass 6, count 0 2006.259.07:43:49.67#ibcon#read 3, iclass 6, count 0 2006.259.07:43:49.67#ibcon#about to read 4, iclass 6, count 0 2006.259.07:43:49.67#ibcon#read 4, iclass 6, count 0 2006.259.07:43:49.67#ibcon#about to read 5, iclass 6, count 0 2006.259.07:43:49.67#ibcon#read 5, iclass 6, count 0 2006.259.07:43:49.67#ibcon#about to read 6, iclass 6, count 0 2006.259.07:43:49.67#ibcon#read 6, iclass 6, count 0 2006.259.07:43:49.67#ibcon#end of sib2, iclass 6, count 0 2006.259.07:43:49.67#ibcon#*after write, iclass 6, count 0 2006.259.07:43:49.67#ibcon#*before return 0, iclass 6, count 0 2006.259.07:43:49.67#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.259.07:43:49.67#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.259.07:43:49.67#ibcon#about to clear, iclass 6 cls_cnt 0 2006.259.07:43:49.67#ibcon#cleared, iclass 6 cls_cnt 0 2006.259.07:43:49.67$vc4f8/valo=3,672.99 2006.259.07:43:49.67#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.259.07:43:49.67#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.259.07:43:49.67#ibcon#ireg 17 cls_cnt 0 2006.259.07:43:49.67#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.259.07:43:49.67#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.259.07:43:49.67#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.259.07:43:49.67#ibcon#enter wrdev, iclass 10, count 0 2006.259.07:43:49.67#ibcon#first serial, iclass 10, count 0 2006.259.07:43:49.67#ibcon#enter sib2, iclass 10, count 0 2006.259.07:43:49.67#ibcon#flushed, iclass 10, count 0 2006.259.07:43:49.67#ibcon#about to write, iclass 10, count 0 2006.259.07:43:49.67#ibcon#wrote, iclass 10, count 0 2006.259.07:43:49.67#ibcon#about to read 3, iclass 10, count 0 2006.259.07:43:49.69#ibcon#read 3, iclass 10, count 0 2006.259.07:43:49.69#ibcon#about to read 4, iclass 10, count 0 2006.259.07:43:49.69#ibcon#read 4, iclass 10, count 0 2006.259.07:43:49.69#ibcon#about to read 5, iclass 10, count 0 2006.259.07:43:49.69#ibcon#read 5, iclass 10, count 0 2006.259.07:43:49.69#ibcon#about to read 6, iclass 10, count 0 2006.259.07:43:49.69#ibcon#read 6, iclass 10, count 0 2006.259.07:43:49.69#ibcon#end of sib2, iclass 10, count 0 2006.259.07:43:49.69#ibcon#*mode == 0, iclass 10, count 0 2006.259.07:43:49.69#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.259.07:43:49.69#ibcon#[26=FRQ=03,672.99\r\n] 2006.259.07:43:49.69#ibcon#*before write, iclass 10, count 0 2006.259.07:43:49.69#ibcon#enter sib2, iclass 10, count 0 2006.259.07:43:49.69#ibcon#flushed, iclass 10, count 0 2006.259.07:43:49.69#ibcon#about to write, iclass 10, count 0 2006.259.07:43:49.69#ibcon#wrote, iclass 10, count 0 2006.259.07:43:49.69#ibcon#about to read 3, iclass 10, count 0 2006.259.07:43:49.73#ibcon#read 3, iclass 10, count 0 2006.259.07:43:49.73#ibcon#about to read 4, iclass 10, count 0 2006.259.07:43:49.73#ibcon#read 4, iclass 10, count 0 2006.259.07:43:49.73#ibcon#about to read 5, iclass 10, count 0 2006.259.07:43:49.73#ibcon#read 5, iclass 10, count 0 2006.259.07:43:49.73#ibcon#about to read 6, iclass 10, count 0 2006.259.07:43:49.73#ibcon#read 6, iclass 10, count 0 2006.259.07:43:49.73#ibcon#end of sib2, iclass 10, count 0 2006.259.07:43:49.73#ibcon#*after write, iclass 10, count 0 2006.259.07:43:49.73#ibcon#*before return 0, iclass 10, count 0 2006.259.07:43:49.73#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.259.07:43:49.73#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.259.07:43:49.73#ibcon#about to clear, iclass 10 cls_cnt 0 2006.259.07:43:49.73#ibcon#cleared, iclass 10 cls_cnt 0 2006.259.07:43:49.73$vc4f8/va=3,8 2006.259.07:43:49.73#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.259.07:43:49.73#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.259.07:43:49.73#ibcon#ireg 11 cls_cnt 2 2006.259.07:43:49.73#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.259.07:43:49.79#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.259.07:43:49.79#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.259.07:43:49.79#ibcon#enter wrdev, iclass 12, count 2 2006.259.07:43:49.79#ibcon#first serial, iclass 12, count 2 2006.259.07:43:49.79#ibcon#enter sib2, iclass 12, count 2 2006.259.07:43:49.79#ibcon#flushed, iclass 12, count 2 2006.259.07:43:49.79#ibcon#about to write, iclass 12, count 2 2006.259.07:43:49.79#ibcon#wrote, iclass 12, count 2 2006.259.07:43:49.79#ibcon#about to read 3, iclass 12, count 2 2006.259.07:43:49.81#ibcon#read 3, iclass 12, count 2 2006.259.07:43:49.81#ibcon#about to read 4, iclass 12, count 2 2006.259.07:43:49.81#ibcon#read 4, iclass 12, count 2 2006.259.07:43:49.81#ibcon#about to read 5, iclass 12, count 2 2006.259.07:43:49.81#ibcon#read 5, iclass 12, count 2 2006.259.07:43:49.81#ibcon#about to read 6, iclass 12, count 2 2006.259.07:43:49.81#ibcon#read 6, iclass 12, count 2 2006.259.07:43:49.81#ibcon#end of sib2, iclass 12, count 2 2006.259.07:43:49.81#ibcon#*mode == 0, iclass 12, count 2 2006.259.07:43:49.81#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.259.07:43:49.81#ibcon#[25=AT03-08\r\n] 2006.259.07:43:49.81#ibcon#*before write, iclass 12, count 2 2006.259.07:43:49.81#ibcon#enter sib2, iclass 12, count 2 2006.259.07:43:49.81#ibcon#flushed, iclass 12, count 2 2006.259.07:43:49.81#ibcon#about to write, iclass 12, count 2 2006.259.07:43:49.81#ibcon#wrote, iclass 12, count 2 2006.259.07:43:49.81#ibcon#about to read 3, iclass 12, count 2 2006.259.07:43:49.84#ibcon#read 3, iclass 12, count 2 2006.259.07:43:49.84#ibcon#about to read 4, iclass 12, count 2 2006.259.07:43:49.84#ibcon#read 4, iclass 12, count 2 2006.259.07:43:49.84#ibcon#about to read 5, iclass 12, count 2 2006.259.07:43:49.84#ibcon#read 5, iclass 12, count 2 2006.259.07:43:49.84#ibcon#about to read 6, iclass 12, count 2 2006.259.07:43:49.84#ibcon#read 6, iclass 12, count 2 2006.259.07:43:49.84#ibcon#end of sib2, iclass 12, count 2 2006.259.07:43:49.84#ibcon#*after write, iclass 12, count 2 2006.259.07:43:49.84#ibcon#*before return 0, iclass 12, count 2 2006.259.07:43:49.84#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.259.07:43:49.84#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.259.07:43:49.84#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.259.07:43:49.84#ibcon#ireg 7 cls_cnt 0 2006.259.07:43:49.84#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.259.07:43:49.96#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.259.07:43:49.96#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.259.07:43:49.96#ibcon#enter wrdev, iclass 12, count 0 2006.259.07:43:49.96#ibcon#first serial, iclass 12, count 0 2006.259.07:43:49.96#ibcon#enter sib2, iclass 12, count 0 2006.259.07:43:49.96#ibcon#flushed, iclass 12, count 0 2006.259.07:43:49.96#ibcon#about to write, iclass 12, count 0 2006.259.07:43:49.96#ibcon#wrote, iclass 12, count 0 2006.259.07:43:49.96#ibcon#about to read 3, iclass 12, count 0 2006.259.07:43:49.98#ibcon#read 3, iclass 12, count 0 2006.259.07:43:49.98#ibcon#about to read 4, iclass 12, count 0 2006.259.07:43:49.98#ibcon#read 4, iclass 12, count 0 2006.259.07:43:49.98#ibcon#about to read 5, iclass 12, count 0 2006.259.07:43:49.98#ibcon#read 5, iclass 12, count 0 2006.259.07:43:49.98#ibcon#about to read 6, iclass 12, count 0 2006.259.07:43:49.98#ibcon#read 6, iclass 12, count 0 2006.259.07:43:49.98#ibcon#end of sib2, iclass 12, count 0 2006.259.07:43:49.98#ibcon#*mode == 0, iclass 12, count 0 2006.259.07:43:49.98#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.259.07:43:49.98#ibcon#[25=USB\r\n] 2006.259.07:43:49.98#ibcon#*before write, iclass 12, count 0 2006.259.07:43:49.98#ibcon#enter sib2, iclass 12, count 0 2006.259.07:43:49.98#ibcon#flushed, iclass 12, count 0 2006.259.07:43:49.98#ibcon#about to write, iclass 12, count 0 2006.259.07:43:49.98#ibcon#wrote, iclass 12, count 0 2006.259.07:43:49.98#ibcon#about to read 3, iclass 12, count 0 2006.259.07:43:50.01#ibcon#read 3, iclass 12, count 0 2006.259.07:43:50.01#ibcon#about to read 4, iclass 12, count 0 2006.259.07:43:50.01#ibcon#read 4, iclass 12, count 0 2006.259.07:43:50.01#ibcon#about to read 5, iclass 12, count 0 2006.259.07:43:50.01#ibcon#read 5, iclass 12, count 0 2006.259.07:43:50.01#ibcon#about to read 6, iclass 12, count 0 2006.259.07:43:50.01#ibcon#read 6, iclass 12, count 0 2006.259.07:43:50.01#ibcon#end of sib2, iclass 12, count 0 2006.259.07:43:50.01#ibcon#*after write, iclass 12, count 0 2006.259.07:43:50.01#ibcon#*before return 0, iclass 12, count 0 2006.259.07:43:50.01#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.259.07:43:50.01#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.259.07:43:50.01#ibcon#about to clear, iclass 12 cls_cnt 0 2006.259.07:43:50.01#ibcon#cleared, iclass 12 cls_cnt 0 2006.259.07:43:50.01$vc4f8/valo=4,832.99 2006.259.07:43:50.01#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.259.07:43:50.01#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.259.07:43:50.01#ibcon#ireg 17 cls_cnt 0 2006.259.07:43:50.01#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.259.07:43:50.01#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.259.07:43:50.01#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.259.07:43:50.01#ibcon#enter wrdev, iclass 14, count 0 2006.259.07:43:50.01#ibcon#first serial, iclass 14, count 0 2006.259.07:43:50.01#ibcon#enter sib2, iclass 14, count 0 2006.259.07:43:50.01#ibcon#flushed, iclass 14, count 0 2006.259.07:43:50.01#ibcon#about to write, iclass 14, count 0 2006.259.07:43:50.01#ibcon#wrote, iclass 14, count 0 2006.259.07:43:50.01#ibcon#about to read 3, iclass 14, count 0 2006.259.07:43:50.03#ibcon#read 3, iclass 14, count 0 2006.259.07:43:50.03#ibcon#about to read 4, iclass 14, count 0 2006.259.07:43:50.03#ibcon#read 4, iclass 14, count 0 2006.259.07:43:50.03#ibcon#about to read 5, iclass 14, count 0 2006.259.07:43:50.03#ibcon#read 5, iclass 14, count 0 2006.259.07:43:50.03#ibcon#about to read 6, iclass 14, count 0 2006.259.07:43:50.03#ibcon#read 6, iclass 14, count 0 2006.259.07:43:50.03#ibcon#end of sib2, iclass 14, count 0 2006.259.07:43:50.03#ibcon#*mode == 0, iclass 14, count 0 2006.259.07:43:50.03#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.259.07:43:50.03#ibcon#[26=FRQ=04,832.99\r\n] 2006.259.07:43:50.03#ibcon#*before write, iclass 14, count 0 2006.259.07:43:50.03#ibcon#enter sib2, iclass 14, count 0 2006.259.07:43:50.03#ibcon#flushed, iclass 14, count 0 2006.259.07:43:50.03#ibcon#about to write, iclass 14, count 0 2006.259.07:43:50.03#ibcon#wrote, iclass 14, count 0 2006.259.07:43:50.03#ibcon#about to read 3, iclass 14, count 0 2006.259.07:43:50.07#ibcon#read 3, iclass 14, count 0 2006.259.07:43:50.07#ibcon#about to read 4, iclass 14, count 0 2006.259.07:43:50.07#ibcon#read 4, iclass 14, count 0 2006.259.07:43:50.07#ibcon#about to read 5, iclass 14, count 0 2006.259.07:43:50.07#ibcon#read 5, iclass 14, count 0 2006.259.07:43:50.07#ibcon#about to read 6, iclass 14, count 0 2006.259.07:43:50.07#ibcon#read 6, iclass 14, count 0 2006.259.07:43:50.07#ibcon#end of sib2, iclass 14, count 0 2006.259.07:43:50.07#ibcon#*after write, iclass 14, count 0 2006.259.07:43:50.07#ibcon#*before return 0, iclass 14, count 0 2006.259.07:43:50.07#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.259.07:43:50.07#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.259.07:43:50.07#ibcon#about to clear, iclass 14 cls_cnt 0 2006.259.07:43:50.07#ibcon#cleared, iclass 14 cls_cnt 0 2006.259.07:43:50.07$vc4f8/va=4,7 2006.259.07:43:50.07#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.259.07:43:50.07#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.259.07:43:50.07#ibcon#ireg 11 cls_cnt 2 2006.259.07:43:50.07#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.259.07:43:50.13#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.259.07:43:50.13#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.259.07:43:50.13#ibcon#enter wrdev, iclass 16, count 2 2006.259.07:43:50.13#ibcon#first serial, iclass 16, count 2 2006.259.07:43:50.13#ibcon#enter sib2, iclass 16, count 2 2006.259.07:43:50.13#ibcon#flushed, iclass 16, count 2 2006.259.07:43:50.13#ibcon#about to write, iclass 16, count 2 2006.259.07:43:50.13#ibcon#wrote, iclass 16, count 2 2006.259.07:43:50.13#ibcon#about to read 3, iclass 16, count 2 2006.259.07:43:50.15#ibcon#read 3, iclass 16, count 2 2006.259.07:43:50.15#ibcon#about to read 4, iclass 16, count 2 2006.259.07:43:50.15#ibcon#read 4, iclass 16, count 2 2006.259.07:43:50.15#ibcon#about to read 5, iclass 16, count 2 2006.259.07:43:50.15#ibcon#read 5, iclass 16, count 2 2006.259.07:43:50.15#ibcon#about to read 6, iclass 16, count 2 2006.259.07:43:50.15#ibcon#read 6, iclass 16, count 2 2006.259.07:43:50.15#ibcon#end of sib2, iclass 16, count 2 2006.259.07:43:50.15#ibcon#*mode == 0, iclass 16, count 2 2006.259.07:43:50.15#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.259.07:43:50.15#ibcon#[25=AT04-07\r\n] 2006.259.07:43:50.15#ibcon#*before write, iclass 16, count 2 2006.259.07:43:50.15#ibcon#enter sib2, iclass 16, count 2 2006.259.07:43:50.15#ibcon#flushed, iclass 16, count 2 2006.259.07:43:50.15#ibcon#about to write, iclass 16, count 2 2006.259.07:43:50.15#ibcon#wrote, iclass 16, count 2 2006.259.07:43:50.15#ibcon#about to read 3, iclass 16, count 2 2006.259.07:43:50.18#ibcon#read 3, iclass 16, count 2 2006.259.07:43:50.18#ibcon#about to read 4, iclass 16, count 2 2006.259.07:43:50.18#ibcon#read 4, iclass 16, count 2 2006.259.07:43:50.18#ibcon#about to read 5, iclass 16, count 2 2006.259.07:43:50.18#ibcon#read 5, iclass 16, count 2 2006.259.07:43:50.18#ibcon#about to read 6, iclass 16, count 2 2006.259.07:43:50.18#ibcon#read 6, iclass 16, count 2 2006.259.07:43:50.18#ibcon#end of sib2, iclass 16, count 2 2006.259.07:43:50.18#ibcon#*after write, iclass 16, count 2 2006.259.07:43:50.18#ibcon#*before return 0, iclass 16, count 2 2006.259.07:43:50.18#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.259.07:43:50.18#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.259.07:43:50.18#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.259.07:43:50.18#ibcon#ireg 7 cls_cnt 0 2006.259.07:43:50.18#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.259.07:43:50.30#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.259.07:43:50.30#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.259.07:43:50.30#ibcon#enter wrdev, iclass 16, count 0 2006.259.07:43:50.30#ibcon#first serial, iclass 16, count 0 2006.259.07:43:50.30#ibcon#enter sib2, iclass 16, count 0 2006.259.07:43:50.30#ibcon#flushed, iclass 16, count 0 2006.259.07:43:50.30#ibcon#about to write, iclass 16, count 0 2006.259.07:43:50.30#ibcon#wrote, iclass 16, count 0 2006.259.07:43:50.30#ibcon#about to read 3, iclass 16, count 0 2006.259.07:43:50.32#ibcon#read 3, iclass 16, count 0 2006.259.07:43:50.32#ibcon#about to read 4, iclass 16, count 0 2006.259.07:43:50.32#ibcon#read 4, iclass 16, count 0 2006.259.07:43:50.32#ibcon#about to read 5, iclass 16, count 0 2006.259.07:43:50.32#ibcon#read 5, iclass 16, count 0 2006.259.07:43:50.32#ibcon#about to read 6, iclass 16, count 0 2006.259.07:43:50.32#ibcon#read 6, iclass 16, count 0 2006.259.07:43:50.32#ibcon#end of sib2, iclass 16, count 0 2006.259.07:43:50.32#ibcon#*mode == 0, iclass 16, count 0 2006.259.07:43:50.32#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.259.07:43:50.32#ibcon#[25=USB\r\n] 2006.259.07:43:50.32#ibcon#*before write, iclass 16, count 0 2006.259.07:43:50.32#ibcon#enter sib2, iclass 16, count 0 2006.259.07:43:50.32#ibcon#flushed, iclass 16, count 0 2006.259.07:43:50.32#ibcon#about to write, iclass 16, count 0 2006.259.07:43:50.32#ibcon#wrote, iclass 16, count 0 2006.259.07:43:50.32#ibcon#about to read 3, iclass 16, count 0 2006.259.07:43:50.35#ibcon#read 3, iclass 16, count 0 2006.259.07:43:50.35#ibcon#about to read 4, iclass 16, count 0 2006.259.07:43:50.35#ibcon#read 4, iclass 16, count 0 2006.259.07:43:50.35#ibcon#about to read 5, iclass 16, count 0 2006.259.07:43:50.35#ibcon#read 5, iclass 16, count 0 2006.259.07:43:50.35#ibcon#about to read 6, iclass 16, count 0 2006.259.07:43:50.35#ibcon#read 6, iclass 16, count 0 2006.259.07:43:50.35#ibcon#end of sib2, iclass 16, count 0 2006.259.07:43:50.35#ibcon#*after write, iclass 16, count 0 2006.259.07:43:50.35#ibcon#*before return 0, iclass 16, count 0 2006.259.07:43:50.35#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.259.07:43:50.35#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.259.07:43:50.35#ibcon#about to clear, iclass 16 cls_cnt 0 2006.259.07:43:50.35#ibcon#cleared, iclass 16 cls_cnt 0 2006.259.07:43:50.35$vc4f8/valo=5,652.99 2006.259.07:43:50.35#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.259.07:43:50.35#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.259.07:43:50.35#ibcon#ireg 17 cls_cnt 0 2006.259.07:43:50.35#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.259.07:43:50.35#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.259.07:43:50.35#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.259.07:43:50.35#ibcon#enter wrdev, iclass 18, count 0 2006.259.07:43:50.35#ibcon#first serial, iclass 18, count 0 2006.259.07:43:50.35#ibcon#enter sib2, iclass 18, count 0 2006.259.07:43:50.35#ibcon#flushed, iclass 18, count 0 2006.259.07:43:50.35#ibcon#about to write, iclass 18, count 0 2006.259.07:43:50.35#ibcon#wrote, iclass 18, count 0 2006.259.07:43:50.35#ibcon#about to read 3, iclass 18, count 0 2006.259.07:43:50.37#ibcon#read 3, iclass 18, count 0 2006.259.07:43:50.37#ibcon#about to read 4, iclass 18, count 0 2006.259.07:43:50.37#ibcon#read 4, iclass 18, count 0 2006.259.07:43:50.37#ibcon#about to read 5, iclass 18, count 0 2006.259.07:43:50.37#ibcon#read 5, iclass 18, count 0 2006.259.07:43:50.37#ibcon#about to read 6, iclass 18, count 0 2006.259.07:43:50.37#ibcon#read 6, iclass 18, count 0 2006.259.07:43:50.37#ibcon#end of sib2, iclass 18, count 0 2006.259.07:43:50.37#ibcon#*mode == 0, iclass 18, count 0 2006.259.07:43:50.37#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.259.07:43:50.37#ibcon#[26=FRQ=05,652.99\r\n] 2006.259.07:43:50.37#ibcon#*before write, iclass 18, count 0 2006.259.07:43:50.37#ibcon#enter sib2, iclass 18, count 0 2006.259.07:43:50.37#ibcon#flushed, iclass 18, count 0 2006.259.07:43:50.37#ibcon#about to write, iclass 18, count 0 2006.259.07:43:50.37#ibcon#wrote, iclass 18, count 0 2006.259.07:43:50.37#ibcon#about to read 3, iclass 18, count 0 2006.259.07:43:50.41#ibcon#read 3, iclass 18, count 0 2006.259.07:43:50.41#ibcon#about to read 4, iclass 18, count 0 2006.259.07:43:50.41#ibcon#read 4, iclass 18, count 0 2006.259.07:43:50.41#ibcon#about to read 5, iclass 18, count 0 2006.259.07:43:50.41#ibcon#read 5, iclass 18, count 0 2006.259.07:43:50.41#ibcon#about to read 6, iclass 18, count 0 2006.259.07:43:50.41#ibcon#read 6, iclass 18, count 0 2006.259.07:43:50.41#ibcon#end of sib2, iclass 18, count 0 2006.259.07:43:50.41#ibcon#*after write, iclass 18, count 0 2006.259.07:43:50.41#ibcon#*before return 0, iclass 18, count 0 2006.259.07:43:50.41#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.259.07:43:50.41#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.259.07:43:50.41#ibcon#about to clear, iclass 18 cls_cnt 0 2006.259.07:43:50.41#ibcon#cleared, iclass 18 cls_cnt 0 2006.259.07:43:50.41$vc4f8/va=5,7 2006.259.07:43:50.41#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.259.07:43:50.41#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.259.07:43:50.41#ibcon#ireg 11 cls_cnt 2 2006.259.07:43:50.41#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.259.07:43:50.47#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.259.07:43:50.47#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.259.07:43:50.47#ibcon#enter wrdev, iclass 20, count 2 2006.259.07:43:50.47#ibcon#first serial, iclass 20, count 2 2006.259.07:43:50.47#ibcon#enter sib2, iclass 20, count 2 2006.259.07:43:50.47#ibcon#flushed, iclass 20, count 2 2006.259.07:43:50.47#ibcon#about to write, iclass 20, count 2 2006.259.07:43:50.47#ibcon#wrote, iclass 20, count 2 2006.259.07:43:50.47#ibcon#about to read 3, iclass 20, count 2 2006.259.07:43:50.49#ibcon#read 3, iclass 20, count 2 2006.259.07:43:50.49#ibcon#about to read 4, iclass 20, count 2 2006.259.07:43:50.49#ibcon#read 4, iclass 20, count 2 2006.259.07:43:50.49#ibcon#about to read 5, iclass 20, count 2 2006.259.07:43:50.49#ibcon#read 5, iclass 20, count 2 2006.259.07:43:50.49#ibcon#about to read 6, iclass 20, count 2 2006.259.07:43:50.49#ibcon#read 6, iclass 20, count 2 2006.259.07:43:50.49#ibcon#end of sib2, iclass 20, count 2 2006.259.07:43:50.49#ibcon#*mode == 0, iclass 20, count 2 2006.259.07:43:50.49#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.259.07:43:50.49#ibcon#[25=AT05-07\r\n] 2006.259.07:43:50.49#ibcon#*before write, iclass 20, count 2 2006.259.07:43:50.49#ibcon#enter sib2, iclass 20, count 2 2006.259.07:43:50.49#ibcon#flushed, iclass 20, count 2 2006.259.07:43:50.49#ibcon#about to write, iclass 20, count 2 2006.259.07:43:50.49#ibcon#wrote, iclass 20, count 2 2006.259.07:43:50.49#ibcon#about to read 3, iclass 20, count 2 2006.259.07:43:50.52#ibcon#read 3, iclass 20, count 2 2006.259.07:43:50.52#ibcon#about to read 4, iclass 20, count 2 2006.259.07:43:50.52#ibcon#read 4, iclass 20, count 2 2006.259.07:43:50.52#ibcon#about to read 5, iclass 20, count 2 2006.259.07:43:50.52#ibcon#read 5, iclass 20, count 2 2006.259.07:43:50.52#ibcon#about to read 6, iclass 20, count 2 2006.259.07:43:50.52#ibcon#read 6, iclass 20, count 2 2006.259.07:43:50.52#ibcon#end of sib2, iclass 20, count 2 2006.259.07:43:50.52#ibcon#*after write, iclass 20, count 2 2006.259.07:43:50.52#ibcon#*before return 0, iclass 20, count 2 2006.259.07:43:50.52#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.259.07:43:50.52#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.259.07:43:50.52#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.259.07:43:50.52#ibcon#ireg 7 cls_cnt 0 2006.259.07:43:50.52#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.259.07:43:50.64#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.259.07:43:50.64#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.259.07:43:50.64#ibcon#enter wrdev, iclass 20, count 0 2006.259.07:43:50.64#ibcon#first serial, iclass 20, count 0 2006.259.07:43:50.64#ibcon#enter sib2, iclass 20, count 0 2006.259.07:43:50.64#ibcon#flushed, iclass 20, count 0 2006.259.07:43:50.64#ibcon#about to write, iclass 20, count 0 2006.259.07:43:50.64#ibcon#wrote, iclass 20, count 0 2006.259.07:43:50.64#ibcon#about to read 3, iclass 20, count 0 2006.259.07:43:50.66#ibcon#read 3, iclass 20, count 0 2006.259.07:43:50.66#ibcon#about to read 4, iclass 20, count 0 2006.259.07:43:50.66#ibcon#read 4, iclass 20, count 0 2006.259.07:43:50.66#ibcon#about to read 5, iclass 20, count 0 2006.259.07:43:50.66#ibcon#read 5, iclass 20, count 0 2006.259.07:43:50.66#ibcon#about to read 6, iclass 20, count 0 2006.259.07:43:50.66#ibcon#read 6, iclass 20, count 0 2006.259.07:43:50.66#ibcon#end of sib2, iclass 20, count 0 2006.259.07:43:50.66#ibcon#*mode == 0, iclass 20, count 0 2006.259.07:43:50.66#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.259.07:43:50.66#ibcon#[25=USB\r\n] 2006.259.07:43:50.66#ibcon#*before write, iclass 20, count 0 2006.259.07:43:50.66#ibcon#enter sib2, iclass 20, count 0 2006.259.07:43:50.66#ibcon#flushed, iclass 20, count 0 2006.259.07:43:50.66#ibcon#about to write, iclass 20, count 0 2006.259.07:43:50.66#ibcon#wrote, iclass 20, count 0 2006.259.07:43:50.66#ibcon#about to read 3, iclass 20, count 0 2006.259.07:43:50.69#ibcon#read 3, iclass 20, count 0 2006.259.07:43:50.69#ibcon#about to read 4, iclass 20, count 0 2006.259.07:43:50.69#ibcon#read 4, iclass 20, count 0 2006.259.07:43:50.69#ibcon#about to read 5, iclass 20, count 0 2006.259.07:43:50.69#ibcon#read 5, iclass 20, count 0 2006.259.07:43:50.69#ibcon#about to read 6, iclass 20, count 0 2006.259.07:43:50.69#ibcon#read 6, iclass 20, count 0 2006.259.07:43:50.69#ibcon#end of sib2, iclass 20, count 0 2006.259.07:43:50.69#ibcon#*after write, iclass 20, count 0 2006.259.07:43:50.69#ibcon#*before return 0, iclass 20, count 0 2006.259.07:43:50.69#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.259.07:43:50.69#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.259.07:43:50.69#ibcon#about to clear, iclass 20 cls_cnt 0 2006.259.07:43:50.69#ibcon#cleared, iclass 20 cls_cnt 0 2006.259.07:43:50.69$vc4f8/valo=6,772.99 2006.259.07:43:50.69#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.259.07:43:50.69#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.259.07:43:50.69#ibcon#ireg 17 cls_cnt 0 2006.259.07:43:50.69#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.259.07:43:50.69#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.259.07:43:50.69#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.259.07:43:50.69#ibcon#enter wrdev, iclass 22, count 0 2006.259.07:43:50.69#ibcon#first serial, iclass 22, count 0 2006.259.07:43:50.69#ibcon#enter sib2, iclass 22, count 0 2006.259.07:43:50.69#ibcon#flushed, iclass 22, count 0 2006.259.07:43:50.69#ibcon#about to write, iclass 22, count 0 2006.259.07:43:50.69#ibcon#wrote, iclass 22, count 0 2006.259.07:43:50.69#ibcon#about to read 3, iclass 22, count 0 2006.259.07:43:50.71#ibcon#read 3, iclass 22, count 0 2006.259.07:43:50.71#ibcon#about to read 4, iclass 22, count 0 2006.259.07:43:50.71#ibcon#read 4, iclass 22, count 0 2006.259.07:43:50.71#ibcon#about to read 5, iclass 22, count 0 2006.259.07:43:50.71#ibcon#read 5, iclass 22, count 0 2006.259.07:43:50.71#ibcon#about to read 6, iclass 22, count 0 2006.259.07:43:50.71#ibcon#read 6, iclass 22, count 0 2006.259.07:43:50.71#ibcon#end of sib2, iclass 22, count 0 2006.259.07:43:50.71#ibcon#*mode == 0, iclass 22, count 0 2006.259.07:43:50.71#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.259.07:43:50.71#ibcon#[26=FRQ=06,772.99\r\n] 2006.259.07:43:50.71#ibcon#*before write, iclass 22, count 0 2006.259.07:43:50.71#ibcon#enter sib2, iclass 22, count 0 2006.259.07:43:50.71#ibcon#flushed, iclass 22, count 0 2006.259.07:43:50.71#ibcon#about to write, iclass 22, count 0 2006.259.07:43:50.71#ibcon#wrote, iclass 22, count 0 2006.259.07:43:50.71#ibcon#about to read 3, iclass 22, count 0 2006.259.07:43:50.75#ibcon#read 3, iclass 22, count 0 2006.259.07:43:50.75#ibcon#about to read 4, iclass 22, count 0 2006.259.07:43:50.75#ibcon#read 4, iclass 22, count 0 2006.259.07:43:50.75#ibcon#about to read 5, iclass 22, count 0 2006.259.07:43:50.75#ibcon#read 5, iclass 22, count 0 2006.259.07:43:50.75#ibcon#about to read 6, iclass 22, count 0 2006.259.07:43:50.75#ibcon#read 6, iclass 22, count 0 2006.259.07:43:50.75#ibcon#end of sib2, iclass 22, count 0 2006.259.07:43:50.75#ibcon#*after write, iclass 22, count 0 2006.259.07:43:50.75#ibcon#*before return 0, iclass 22, count 0 2006.259.07:43:50.75#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.259.07:43:50.75#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.259.07:43:50.75#ibcon#about to clear, iclass 22 cls_cnt 0 2006.259.07:43:50.75#ibcon#cleared, iclass 22 cls_cnt 0 2006.259.07:43:50.75$vc4f8/va=6,6 2006.259.07:43:50.75#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.259.07:43:50.75#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.259.07:43:50.75#ibcon#ireg 11 cls_cnt 2 2006.259.07:43:50.75#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.259.07:43:50.81#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.259.07:43:50.81#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.259.07:43:50.81#ibcon#enter wrdev, iclass 24, count 2 2006.259.07:43:50.81#ibcon#first serial, iclass 24, count 2 2006.259.07:43:50.81#ibcon#enter sib2, iclass 24, count 2 2006.259.07:43:50.81#ibcon#flushed, iclass 24, count 2 2006.259.07:43:50.81#ibcon#about to write, iclass 24, count 2 2006.259.07:43:50.81#ibcon#wrote, iclass 24, count 2 2006.259.07:43:50.81#ibcon#about to read 3, iclass 24, count 2 2006.259.07:43:50.83#ibcon#read 3, iclass 24, count 2 2006.259.07:43:50.83#ibcon#about to read 4, iclass 24, count 2 2006.259.07:43:50.83#ibcon#read 4, iclass 24, count 2 2006.259.07:43:50.83#ibcon#about to read 5, iclass 24, count 2 2006.259.07:43:50.83#ibcon#read 5, iclass 24, count 2 2006.259.07:43:50.83#ibcon#about to read 6, iclass 24, count 2 2006.259.07:43:50.83#ibcon#read 6, iclass 24, count 2 2006.259.07:43:50.83#ibcon#end of sib2, iclass 24, count 2 2006.259.07:43:50.83#ibcon#*mode == 0, iclass 24, count 2 2006.259.07:43:50.83#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.259.07:43:50.83#ibcon#[25=AT06-06\r\n] 2006.259.07:43:50.83#ibcon#*before write, iclass 24, count 2 2006.259.07:43:50.83#ibcon#enter sib2, iclass 24, count 2 2006.259.07:43:50.83#ibcon#flushed, iclass 24, count 2 2006.259.07:43:50.83#ibcon#about to write, iclass 24, count 2 2006.259.07:43:50.83#ibcon#wrote, iclass 24, count 2 2006.259.07:43:50.83#ibcon#about to read 3, iclass 24, count 2 2006.259.07:43:50.86#ibcon#read 3, iclass 24, count 2 2006.259.07:43:50.86#ibcon#about to read 4, iclass 24, count 2 2006.259.07:43:50.86#ibcon#read 4, iclass 24, count 2 2006.259.07:43:50.86#ibcon#about to read 5, iclass 24, count 2 2006.259.07:43:50.86#ibcon#read 5, iclass 24, count 2 2006.259.07:43:50.86#ibcon#about to read 6, iclass 24, count 2 2006.259.07:43:50.86#ibcon#read 6, iclass 24, count 2 2006.259.07:43:50.86#ibcon#end of sib2, iclass 24, count 2 2006.259.07:43:50.86#ibcon#*after write, iclass 24, count 2 2006.259.07:43:50.86#ibcon#*before return 0, iclass 24, count 2 2006.259.07:43:50.86#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.259.07:43:50.86#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.259.07:43:50.86#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.259.07:43:50.86#ibcon#ireg 7 cls_cnt 0 2006.259.07:43:50.86#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.259.07:43:50.98#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.259.07:43:50.98#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.259.07:43:50.98#ibcon#enter wrdev, iclass 24, count 0 2006.259.07:43:50.98#ibcon#first serial, iclass 24, count 0 2006.259.07:43:50.98#ibcon#enter sib2, iclass 24, count 0 2006.259.07:43:50.98#ibcon#flushed, iclass 24, count 0 2006.259.07:43:50.98#ibcon#about to write, iclass 24, count 0 2006.259.07:43:50.98#ibcon#wrote, iclass 24, count 0 2006.259.07:43:50.98#ibcon#about to read 3, iclass 24, count 0 2006.259.07:43:51.00#ibcon#read 3, iclass 24, count 0 2006.259.07:43:51.00#ibcon#about to read 4, iclass 24, count 0 2006.259.07:43:51.00#ibcon#read 4, iclass 24, count 0 2006.259.07:43:51.00#ibcon#about to read 5, iclass 24, count 0 2006.259.07:43:51.00#ibcon#read 5, iclass 24, count 0 2006.259.07:43:51.00#ibcon#about to read 6, iclass 24, count 0 2006.259.07:43:51.00#ibcon#read 6, iclass 24, count 0 2006.259.07:43:51.00#ibcon#end of sib2, iclass 24, count 0 2006.259.07:43:51.00#ibcon#*mode == 0, iclass 24, count 0 2006.259.07:43:51.00#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.259.07:43:51.00#ibcon#[25=USB\r\n] 2006.259.07:43:51.00#ibcon#*before write, iclass 24, count 0 2006.259.07:43:51.00#ibcon#enter sib2, iclass 24, count 0 2006.259.07:43:51.00#ibcon#flushed, iclass 24, count 0 2006.259.07:43:51.00#ibcon#about to write, iclass 24, count 0 2006.259.07:43:51.00#ibcon#wrote, iclass 24, count 0 2006.259.07:43:51.00#ibcon#about to read 3, iclass 24, count 0 2006.259.07:43:51.03#ibcon#read 3, iclass 24, count 0 2006.259.07:43:51.03#ibcon#about to read 4, iclass 24, count 0 2006.259.07:43:51.03#ibcon#read 4, iclass 24, count 0 2006.259.07:43:51.03#ibcon#about to read 5, iclass 24, count 0 2006.259.07:43:51.03#ibcon#read 5, iclass 24, count 0 2006.259.07:43:51.03#ibcon#about to read 6, iclass 24, count 0 2006.259.07:43:51.03#ibcon#read 6, iclass 24, count 0 2006.259.07:43:51.03#ibcon#end of sib2, iclass 24, count 0 2006.259.07:43:51.03#ibcon#*after write, iclass 24, count 0 2006.259.07:43:51.03#ibcon#*before return 0, iclass 24, count 0 2006.259.07:43:51.03#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.259.07:43:51.03#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.259.07:43:51.03#ibcon#about to clear, iclass 24 cls_cnt 0 2006.259.07:43:51.03#ibcon#cleared, iclass 24 cls_cnt 0 2006.259.07:43:51.03$vc4f8/valo=7,832.99 2006.259.07:43:51.03#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.259.07:43:51.03#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.259.07:43:51.03#ibcon#ireg 17 cls_cnt 0 2006.259.07:43:51.03#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.259.07:43:51.03#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.259.07:43:51.03#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.259.07:43:51.03#ibcon#enter wrdev, iclass 26, count 0 2006.259.07:43:51.03#ibcon#first serial, iclass 26, count 0 2006.259.07:43:51.03#ibcon#enter sib2, iclass 26, count 0 2006.259.07:43:51.03#ibcon#flushed, iclass 26, count 0 2006.259.07:43:51.03#ibcon#about to write, iclass 26, count 0 2006.259.07:43:51.03#ibcon#wrote, iclass 26, count 0 2006.259.07:43:51.03#ibcon#about to read 3, iclass 26, count 0 2006.259.07:43:51.05#ibcon#read 3, iclass 26, count 0 2006.259.07:43:51.05#ibcon#about to read 4, iclass 26, count 0 2006.259.07:43:51.05#ibcon#read 4, iclass 26, count 0 2006.259.07:43:51.05#ibcon#about to read 5, iclass 26, count 0 2006.259.07:43:51.05#ibcon#read 5, iclass 26, count 0 2006.259.07:43:51.05#ibcon#about to read 6, iclass 26, count 0 2006.259.07:43:51.05#ibcon#read 6, iclass 26, count 0 2006.259.07:43:51.05#ibcon#end of sib2, iclass 26, count 0 2006.259.07:43:51.05#ibcon#*mode == 0, iclass 26, count 0 2006.259.07:43:51.05#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.259.07:43:51.05#ibcon#[26=FRQ=07,832.99\r\n] 2006.259.07:43:51.05#ibcon#*before write, iclass 26, count 0 2006.259.07:43:51.05#ibcon#enter sib2, iclass 26, count 0 2006.259.07:43:51.05#ibcon#flushed, iclass 26, count 0 2006.259.07:43:51.05#ibcon#about to write, iclass 26, count 0 2006.259.07:43:51.05#ibcon#wrote, iclass 26, count 0 2006.259.07:43:51.05#ibcon#about to read 3, iclass 26, count 0 2006.259.07:43:51.09#ibcon#read 3, iclass 26, count 0 2006.259.07:43:51.09#ibcon#about to read 4, iclass 26, count 0 2006.259.07:43:51.09#ibcon#read 4, iclass 26, count 0 2006.259.07:43:51.09#ibcon#about to read 5, iclass 26, count 0 2006.259.07:43:51.09#ibcon#read 5, iclass 26, count 0 2006.259.07:43:51.09#ibcon#about to read 6, iclass 26, count 0 2006.259.07:43:51.09#ibcon#read 6, iclass 26, count 0 2006.259.07:43:51.09#ibcon#end of sib2, iclass 26, count 0 2006.259.07:43:51.09#ibcon#*after write, iclass 26, count 0 2006.259.07:43:51.09#ibcon#*before return 0, iclass 26, count 0 2006.259.07:43:51.09#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.259.07:43:51.09#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.259.07:43:51.09#ibcon#about to clear, iclass 26 cls_cnt 0 2006.259.07:43:51.09#ibcon#cleared, iclass 26 cls_cnt 0 2006.259.07:43:51.09$vc4f8/va=7,6 2006.259.07:43:51.09#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.259.07:43:51.09#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.259.07:43:51.09#ibcon#ireg 11 cls_cnt 2 2006.259.07:43:51.09#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.259.07:43:51.15#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.259.07:43:51.15#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.259.07:43:51.15#ibcon#enter wrdev, iclass 28, count 2 2006.259.07:43:51.15#ibcon#first serial, iclass 28, count 2 2006.259.07:43:51.15#ibcon#enter sib2, iclass 28, count 2 2006.259.07:43:51.15#ibcon#flushed, iclass 28, count 2 2006.259.07:43:51.15#ibcon#about to write, iclass 28, count 2 2006.259.07:43:51.15#ibcon#wrote, iclass 28, count 2 2006.259.07:43:51.15#ibcon#about to read 3, iclass 28, count 2 2006.259.07:43:51.17#ibcon#read 3, iclass 28, count 2 2006.259.07:43:51.17#ibcon#about to read 4, iclass 28, count 2 2006.259.07:43:51.17#ibcon#read 4, iclass 28, count 2 2006.259.07:43:51.17#ibcon#about to read 5, iclass 28, count 2 2006.259.07:43:51.17#ibcon#read 5, iclass 28, count 2 2006.259.07:43:51.17#ibcon#about to read 6, iclass 28, count 2 2006.259.07:43:51.17#ibcon#read 6, iclass 28, count 2 2006.259.07:43:51.17#ibcon#end of sib2, iclass 28, count 2 2006.259.07:43:51.17#ibcon#*mode == 0, iclass 28, count 2 2006.259.07:43:51.17#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.259.07:43:51.17#ibcon#[25=AT07-06\r\n] 2006.259.07:43:51.17#ibcon#*before write, iclass 28, count 2 2006.259.07:43:51.17#ibcon#enter sib2, iclass 28, count 2 2006.259.07:43:51.17#ibcon#flushed, iclass 28, count 2 2006.259.07:43:51.17#ibcon#about to write, iclass 28, count 2 2006.259.07:43:51.17#ibcon#wrote, iclass 28, count 2 2006.259.07:43:51.17#ibcon#about to read 3, iclass 28, count 2 2006.259.07:43:51.20#ibcon#read 3, iclass 28, count 2 2006.259.07:43:51.20#ibcon#about to read 4, iclass 28, count 2 2006.259.07:43:51.20#ibcon#read 4, iclass 28, count 2 2006.259.07:43:51.20#ibcon#about to read 5, iclass 28, count 2 2006.259.07:43:51.20#ibcon#read 5, iclass 28, count 2 2006.259.07:43:51.20#ibcon#about to read 6, iclass 28, count 2 2006.259.07:43:51.20#ibcon#read 6, iclass 28, count 2 2006.259.07:43:51.20#ibcon#end of sib2, iclass 28, count 2 2006.259.07:43:51.20#ibcon#*after write, iclass 28, count 2 2006.259.07:43:51.20#ibcon#*before return 0, iclass 28, count 2 2006.259.07:43:51.20#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.259.07:43:51.20#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.259.07:43:51.20#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.259.07:43:51.20#ibcon#ireg 7 cls_cnt 0 2006.259.07:43:51.20#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.259.07:43:51.32#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.259.07:43:51.32#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.259.07:43:51.32#ibcon#enter wrdev, iclass 28, count 0 2006.259.07:43:51.32#ibcon#first serial, iclass 28, count 0 2006.259.07:43:51.32#ibcon#enter sib2, iclass 28, count 0 2006.259.07:43:51.32#ibcon#flushed, iclass 28, count 0 2006.259.07:43:51.32#ibcon#about to write, iclass 28, count 0 2006.259.07:43:51.32#ibcon#wrote, iclass 28, count 0 2006.259.07:43:51.32#ibcon#about to read 3, iclass 28, count 0 2006.259.07:43:51.34#ibcon#read 3, iclass 28, count 0 2006.259.07:43:51.34#ibcon#about to read 4, iclass 28, count 0 2006.259.07:43:51.34#ibcon#read 4, iclass 28, count 0 2006.259.07:43:51.34#ibcon#about to read 5, iclass 28, count 0 2006.259.07:43:51.34#ibcon#read 5, iclass 28, count 0 2006.259.07:43:51.34#ibcon#about to read 6, iclass 28, count 0 2006.259.07:43:51.34#ibcon#read 6, iclass 28, count 0 2006.259.07:43:51.34#ibcon#end of sib2, iclass 28, count 0 2006.259.07:43:51.34#ibcon#*mode == 0, iclass 28, count 0 2006.259.07:43:51.34#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.259.07:43:51.34#ibcon#[25=USB\r\n] 2006.259.07:43:51.34#ibcon#*before write, iclass 28, count 0 2006.259.07:43:51.34#ibcon#enter sib2, iclass 28, count 0 2006.259.07:43:51.34#ibcon#flushed, iclass 28, count 0 2006.259.07:43:51.34#ibcon#about to write, iclass 28, count 0 2006.259.07:43:51.34#ibcon#wrote, iclass 28, count 0 2006.259.07:43:51.34#ibcon#about to read 3, iclass 28, count 0 2006.259.07:43:51.37#ibcon#read 3, iclass 28, count 0 2006.259.07:43:51.37#ibcon#about to read 4, iclass 28, count 0 2006.259.07:43:51.37#ibcon#read 4, iclass 28, count 0 2006.259.07:43:51.37#ibcon#about to read 5, iclass 28, count 0 2006.259.07:43:51.37#ibcon#read 5, iclass 28, count 0 2006.259.07:43:51.37#ibcon#about to read 6, iclass 28, count 0 2006.259.07:43:51.37#ibcon#read 6, iclass 28, count 0 2006.259.07:43:51.37#ibcon#end of sib2, iclass 28, count 0 2006.259.07:43:51.37#ibcon#*after write, iclass 28, count 0 2006.259.07:43:51.37#ibcon#*before return 0, iclass 28, count 0 2006.259.07:43:51.37#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.259.07:43:51.37#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.259.07:43:51.37#ibcon#about to clear, iclass 28 cls_cnt 0 2006.259.07:43:51.37#ibcon#cleared, iclass 28 cls_cnt 0 2006.259.07:43:51.37$vc4f8/valo=8,852.99 2006.259.07:43:51.37#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.259.07:43:51.37#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.259.07:43:51.37#ibcon#ireg 17 cls_cnt 0 2006.259.07:43:51.37#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.259.07:43:51.37#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.259.07:43:51.37#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.259.07:43:51.37#ibcon#enter wrdev, iclass 31, count 0 2006.259.07:43:51.37#ibcon#first serial, iclass 31, count 0 2006.259.07:43:51.37#ibcon#enter sib2, iclass 31, count 0 2006.259.07:43:51.37#ibcon#flushed, iclass 31, count 0 2006.259.07:43:51.37#ibcon#about to write, iclass 31, count 0 2006.259.07:43:51.37#ibcon#wrote, iclass 31, count 0 2006.259.07:43:51.37#ibcon#about to read 3, iclass 31, count 0 2006.259.07:43:51.39#ibcon#read 3, iclass 31, count 0 2006.259.07:43:51.39#ibcon#about to read 4, iclass 31, count 0 2006.259.07:43:51.39#ibcon#read 4, iclass 31, count 0 2006.259.07:43:51.39#ibcon#about to read 5, iclass 31, count 0 2006.259.07:43:51.39#ibcon#read 5, iclass 31, count 0 2006.259.07:43:51.39#ibcon#about to read 6, iclass 31, count 0 2006.259.07:43:51.39#ibcon#read 6, iclass 31, count 0 2006.259.07:43:51.39#ibcon#end of sib2, iclass 31, count 0 2006.259.07:43:51.39#ibcon#*mode == 0, iclass 31, count 0 2006.259.07:43:51.39#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.259.07:43:51.39#ibcon#[26=FRQ=08,852.99\r\n] 2006.259.07:43:51.39#ibcon#*before write, iclass 31, count 0 2006.259.07:43:51.39#ibcon#enter sib2, iclass 31, count 0 2006.259.07:43:51.39#ibcon#flushed, iclass 31, count 0 2006.259.07:43:51.39#ibcon#about to write, iclass 31, count 0 2006.259.07:43:51.39#ibcon#wrote, iclass 31, count 0 2006.259.07:43:51.39#ibcon#about to read 3, iclass 31, count 0 2006.259.07:43:51.41#abcon#<5=/04 2.4 5.6 22.25 851012.9\r\n> 2006.259.07:43:51.43#abcon#{5=INTERFACE CLEAR} 2006.259.07:43:51.43#ibcon#read 3, iclass 31, count 0 2006.259.07:43:51.43#ibcon#about to read 4, iclass 31, count 0 2006.259.07:43:51.43#ibcon#read 4, iclass 31, count 0 2006.259.07:43:51.43#ibcon#about to read 5, iclass 31, count 0 2006.259.07:43:51.43#ibcon#read 5, iclass 31, count 0 2006.259.07:43:51.43#ibcon#about to read 6, iclass 31, count 0 2006.259.07:43:51.43#ibcon#read 6, iclass 31, count 0 2006.259.07:43:51.43#ibcon#end of sib2, iclass 31, count 0 2006.259.07:43:51.43#ibcon#*after write, iclass 31, count 0 2006.259.07:43:51.43#ibcon#*before return 0, iclass 31, count 0 2006.259.07:43:51.43#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.259.07:43:51.43#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.259.07:43:51.43#ibcon#about to clear, iclass 31 cls_cnt 0 2006.259.07:43:51.43#ibcon#cleared, iclass 31 cls_cnt 0 2006.259.07:43:51.43$vc4f8/va=8,6 2006.259.07:43:51.43#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.259.07:43:51.43#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.259.07:43:51.43#ibcon#ireg 11 cls_cnt 2 2006.259.07:43:51.43#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.259.07:43:51.49#abcon#[5=S1D000X0/0*\r\n] 2006.259.07:43:51.49#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.259.07:43:51.49#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.259.07:43:51.49#ibcon#enter wrdev, iclass 35, count 2 2006.259.07:43:51.49#ibcon#first serial, iclass 35, count 2 2006.259.07:43:51.49#ibcon#enter sib2, iclass 35, count 2 2006.259.07:43:51.49#ibcon#flushed, iclass 35, count 2 2006.259.07:43:51.49#ibcon#about to write, iclass 35, count 2 2006.259.07:43:51.49#ibcon#wrote, iclass 35, count 2 2006.259.07:43:51.49#ibcon#about to read 3, iclass 35, count 2 2006.259.07:43:51.51#ibcon#read 3, iclass 35, count 2 2006.259.07:43:51.51#ibcon#about to read 4, iclass 35, count 2 2006.259.07:43:51.51#ibcon#read 4, iclass 35, count 2 2006.259.07:43:51.51#ibcon#about to read 5, iclass 35, count 2 2006.259.07:43:51.51#ibcon#read 5, iclass 35, count 2 2006.259.07:43:51.51#ibcon#about to read 6, iclass 35, count 2 2006.259.07:43:51.51#ibcon#read 6, iclass 35, count 2 2006.259.07:43:51.51#ibcon#end of sib2, iclass 35, count 2 2006.259.07:43:51.51#ibcon#*mode == 0, iclass 35, count 2 2006.259.07:43:51.51#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.259.07:43:51.51#ibcon#[25=AT08-06\r\n] 2006.259.07:43:51.51#ibcon#*before write, iclass 35, count 2 2006.259.07:43:51.51#ibcon#enter sib2, iclass 35, count 2 2006.259.07:43:51.51#ibcon#flushed, iclass 35, count 2 2006.259.07:43:51.51#ibcon#about to write, iclass 35, count 2 2006.259.07:43:51.51#ibcon#wrote, iclass 35, count 2 2006.259.07:43:51.51#ibcon#about to read 3, iclass 35, count 2 2006.259.07:43:51.54#ibcon#read 3, iclass 35, count 2 2006.259.07:43:51.54#ibcon#about to read 4, iclass 35, count 2 2006.259.07:43:51.54#ibcon#read 4, iclass 35, count 2 2006.259.07:43:51.54#ibcon#about to read 5, iclass 35, count 2 2006.259.07:43:51.54#ibcon#read 5, iclass 35, count 2 2006.259.07:43:51.54#ibcon#about to read 6, iclass 35, count 2 2006.259.07:43:51.54#ibcon#read 6, iclass 35, count 2 2006.259.07:43:51.54#ibcon#end of sib2, iclass 35, count 2 2006.259.07:43:51.54#ibcon#*after write, iclass 35, count 2 2006.259.07:43:51.54#ibcon#*before return 0, iclass 35, count 2 2006.259.07:43:51.54#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.259.07:43:51.54#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.259.07:43:51.54#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.259.07:43:51.54#ibcon#ireg 7 cls_cnt 0 2006.259.07:43:51.54#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.259.07:43:51.66#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.259.07:43:51.66#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.259.07:43:51.66#ibcon#enter wrdev, iclass 35, count 0 2006.259.07:43:51.66#ibcon#first serial, iclass 35, count 0 2006.259.07:43:51.66#ibcon#enter sib2, iclass 35, count 0 2006.259.07:43:51.66#ibcon#flushed, iclass 35, count 0 2006.259.07:43:51.66#ibcon#about to write, iclass 35, count 0 2006.259.07:43:51.66#ibcon#wrote, iclass 35, count 0 2006.259.07:43:51.66#ibcon#about to read 3, iclass 35, count 0 2006.259.07:43:51.68#ibcon#read 3, iclass 35, count 0 2006.259.07:43:51.68#ibcon#about to read 4, iclass 35, count 0 2006.259.07:43:51.68#ibcon#read 4, iclass 35, count 0 2006.259.07:43:51.68#ibcon#about to read 5, iclass 35, count 0 2006.259.07:43:51.68#ibcon#read 5, iclass 35, count 0 2006.259.07:43:51.68#ibcon#about to read 6, iclass 35, count 0 2006.259.07:43:51.68#ibcon#read 6, iclass 35, count 0 2006.259.07:43:51.68#ibcon#end of sib2, iclass 35, count 0 2006.259.07:43:51.68#ibcon#*mode == 0, iclass 35, count 0 2006.259.07:43:51.68#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.259.07:43:51.68#ibcon#[25=USB\r\n] 2006.259.07:43:51.68#ibcon#*before write, iclass 35, count 0 2006.259.07:43:51.68#ibcon#enter sib2, iclass 35, count 0 2006.259.07:43:51.68#ibcon#flushed, iclass 35, count 0 2006.259.07:43:51.68#ibcon#about to write, iclass 35, count 0 2006.259.07:43:51.68#ibcon#wrote, iclass 35, count 0 2006.259.07:43:51.68#ibcon#about to read 3, iclass 35, count 0 2006.259.07:43:51.71#ibcon#read 3, iclass 35, count 0 2006.259.07:43:51.71#ibcon#about to read 4, iclass 35, count 0 2006.259.07:43:51.71#ibcon#read 4, iclass 35, count 0 2006.259.07:43:51.71#ibcon#about to read 5, iclass 35, count 0 2006.259.07:43:51.71#ibcon#read 5, iclass 35, count 0 2006.259.07:43:51.71#ibcon#about to read 6, iclass 35, count 0 2006.259.07:43:51.71#ibcon#read 6, iclass 35, count 0 2006.259.07:43:51.71#ibcon#end of sib2, iclass 35, count 0 2006.259.07:43:51.71#ibcon#*after write, iclass 35, count 0 2006.259.07:43:51.71#ibcon#*before return 0, iclass 35, count 0 2006.259.07:43:51.71#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.259.07:43:51.71#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.259.07:43:51.71#ibcon#about to clear, iclass 35 cls_cnt 0 2006.259.07:43:51.71#ibcon#cleared, iclass 35 cls_cnt 0 2006.259.07:43:51.71$vc4f8/vblo=1,632.99 2006.259.07:43:51.71#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.259.07:43:51.71#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.259.07:43:51.71#ibcon#ireg 17 cls_cnt 0 2006.259.07:43:51.71#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.259.07:43:51.71#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.259.07:43:51.71#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.259.07:43:51.71#ibcon#enter wrdev, iclass 38, count 0 2006.259.07:43:51.71#ibcon#first serial, iclass 38, count 0 2006.259.07:43:51.71#ibcon#enter sib2, iclass 38, count 0 2006.259.07:43:51.71#ibcon#flushed, iclass 38, count 0 2006.259.07:43:51.71#ibcon#about to write, iclass 38, count 0 2006.259.07:43:51.71#ibcon#wrote, iclass 38, count 0 2006.259.07:43:51.71#ibcon#about to read 3, iclass 38, count 0 2006.259.07:43:51.73#ibcon#read 3, iclass 38, count 0 2006.259.07:43:51.73#ibcon#about to read 4, iclass 38, count 0 2006.259.07:43:51.73#ibcon#read 4, iclass 38, count 0 2006.259.07:43:51.73#ibcon#about to read 5, iclass 38, count 0 2006.259.07:43:51.73#ibcon#read 5, iclass 38, count 0 2006.259.07:43:51.73#ibcon#about to read 6, iclass 38, count 0 2006.259.07:43:51.73#ibcon#read 6, iclass 38, count 0 2006.259.07:43:51.73#ibcon#end of sib2, iclass 38, count 0 2006.259.07:43:51.73#ibcon#*mode == 0, iclass 38, count 0 2006.259.07:43:51.73#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.259.07:43:51.73#ibcon#[28=FRQ=01,632.99\r\n] 2006.259.07:43:51.73#ibcon#*before write, iclass 38, count 0 2006.259.07:43:51.73#ibcon#enter sib2, iclass 38, count 0 2006.259.07:43:51.73#ibcon#flushed, iclass 38, count 0 2006.259.07:43:51.73#ibcon#about to write, iclass 38, count 0 2006.259.07:43:51.73#ibcon#wrote, iclass 38, count 0 2006.259.07:43:51.73#ibcon#about to read 3, iclass 38, count 0 2006.259.07:43:51.77#ibcon#read 3, iclass 38, count 0 2006.259.07:43:51.77#ibcon#about to read 4, iclass 38, count 0 2006.259.07:43:51.77#ibcon#read 4, iclass 38, count 0 2006.259.07:43:51.77#ibcon#about to read 5, iclass 38, count 0 2006.259.07:43:51.77#ibcon#read 5, iclass 38, count 0 2006.259.07:43:51.77#ibcon#about to read 6, iclass 38, count 0 2006.259.07:43:51.77#ibcon#read 6, iclass 38, count 0 2006.259.07:43:51.77#ibcon#end of sib2, iclass 38, count 0 2006.259.07:43:51.77#ibcon#*after write, iclass 38, count 0 2006.259.07:43:51.77#ibcon#*before return 0, iclass 38, count 0 2006.259.07:43:51.77#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.259.07:43:51.77#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.259.07:43:51.77#ibcon#about to clear, iclass 38 cls_cnt 0 2006.259.07:43:51.77#ibcon#cleared, iclass 38 cls_cnt 0 2006.259.07:43:51.77$vc4f8/vb=1,4 2006.259.07:43:51.77#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.259.07:43:51.77#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.259.07:43:51.77#ibcon#ireg 11 cls_cnt 2 2006.259.07:43:51.77#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.259.07:43:51.77#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.259.07:43:51.77#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.259.07:43:51.77#ibcon#enter wrdev, iclass 40, count 2 2006.259.07:43:51.77#ibcon#first serial, iclass 40, count 2 2006.259.07:43:51.77#ibcon#enter sib2, iclass 40, count 2 2006.259.07:43:51.77#ibcon#flushed, iclass 40, count 2 2006.259.07:43:51.77#ibcon#about to write, iclass 40, count 2 2006.259.07:43:51.77#ibcon#wrote, iclass 40, count 2 2006.259.07:43:51.77#ibcon#about to read 3, iclass 40, count 2 2006.259.07:43:51.79#ibcon#read 3, iclass 40, count 2 2006.259.07:43:51.79#ibcon#about to read 4, iclass 40, count 2 2006.259.07:43:51.79#ibcon#read 4, iclass 40, count 2 2006.259.07:43:51.79#ibcon#about to read 5, iclass 40, count 2 2006.259.07:43:51.79#ibcon#read 5, iclass 40, count 2 2006.259.07:43:51.79#ibcon#about to read 6, iclass 40, count 2 2006.259.07:43:51.79#ibcon#read 6, iclass 40, count 2 2006.259.07:43:51.79#ibcon#end of sib2, iclass 40, count 2 2006.259.07:43:51.79#ibcon#*mode == 0, iclass 40, count 2 2006.259.07:43:51.79#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.259.07:43:51.79#ibcon#[27=AT01-04\r\n] 2006.259.07:43:51.79#ibcon#*before write, iclass 40, count 2 2006.259.07:43:51.79#ibcon#enter sib2, iclass 40, count 2 2006.259.07:43:51.79#ibcon#flushed, iclass 40, count 2 2006.259.07:43:51.79#ibcon#about to write, iclass 40, count 2 2006.259.07:43:51.79#ibcon#wrote, iclass 40, count 2 2006.259.07:43:51.79#ibcon#about to read 3, iclass 40, count 2 2006.259.07:43:51.82#ibcon#read 3, iclass 40, count 2 2006.259.07:43:51.82#ibcon#about to read 4, iclass 40, count 2 2006.259.07:43:51.82#ibcon#read 4, iclass 40, count 2 2006.259.07:43:51.82#ibcon#about to read 5, iclass 40, count 2 2006.259.07:43:51.82#ibcon#read 5, iclass 40, count 2 2006.259.07:43:51.82#ibcon#about to read 6, iclass 40, count 2 2006.259.07:43:51.82#ibcon#read 6, iclass 40, count 2 2006.259.07:43:51.82#ibcon#end of sib2, iclass 40, count 2 2006.259.07:43:51.82#ibcon#*after write, iclass 40, count 2 2006.259.07:43:51.82#ibcon#*before return 0, iclass 40, count 2 2006.259.07:43:51.82#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.259.07:43:51.82#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.259.07:43:51.82#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.259.07:43:51.82#ibcon#ireg 7 cls_cnt 0 2006.259.07:43:51.82#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.259.07:43:51.94#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.259.07:43:51.94#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.259.07:43:51.94#ibcon#enter wrdev, iclass 40, count 0 2006.259.07:43:51.94#ibcon#first serial, iclass 40, count 0 2006.259.07:43:51.94#ibcon#enter sib2, iclass 40, count 0 2006.259.07:43:51.94#ibcon#flushed, iclass 40, count 0 2006.259.07:43:51.94#ibcon#about to write, iclass 40, count 0 2006.259.07:43:51.94#ibcon#wrote, iclass 40, count 0 2006.259.07:43:51.94#ibcon#about to read 3, iclass 40, count 0 2006.259.07:43:51.96#ibcon#read 3, iclass 40, count 0 2006.259.07:43:51.96#ibcon#about to read 4, iclass 40, count 0 2006.259.07:43:51.96#ibcon#read 4, iclass 40, count 0 2006.259.07:43:51.96#ibcon#about to read 5, iclass 40, count 0 2006.259.07:43:51.96#ibcon#read 5, iclass 40, count 0 2006.259.07:43:51.96#ibcon#about to read 6, iclass 40, count 0 2006.259.07:43:51.96#ibcon#read 6, iclass 40, count 0 2006.259.07:43:51.96#ibcon#end of sib2, iclass 40, count 0 2006.259.07:43:51.96#ibcon#*mode == 0, iclass 40, count 0 2006.259.07:43:51.96#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.259.07:43:51.96#ibcon#[27=USB\r\n] 2006.259.07:43:51.96#ibcon#*before write, iclass 40, count 0 2006.259.07:43:51.96#ibcon#enter sib2, iclass 40, count 0 2006.259.07:43:51.96#ibcon#flushed, iclass 40, count 0 2006.259.07:43:51.96#ibcon#about to write, iclass 40, count 0 2006.259.07:43:51.96#ibcon#wrote, iclass 40, count 0 2006.259.07:43:51.96#ibcon#about to read 3, iclass 40, count 0 2006.259.07:43:51.99#ibcon#read 3, iclass 40, count 0 2006.259.07:43:51.99#ibcon#about to read 4, iclass 40, count 0 2006.259.07:43:51.99#ibcon#read 4, iclass 40, count 0 2006.259.07:43:51.99#ibcon#about to read 5, iclass 40, count 0 2006.259.07:43:51.99#ibcon#read 5, iclass 40, count 0 2006.259.07:43:51.99#ibcon#about to read 6, iclass 40, count 0 2006.259.07:43:51.99#ibcon#read 6, iclass 40, count 0 2006.259.07:43:51.99#ibcon#end of sib2, iclass 40, count 0 2006.259.07:43:51.99#ibcon#*after write, iclass 40, count 0 2006.259.07:43:51.99#ibcon#*before return 0, iclass 40, count 0 2006.259.07:43:51.99#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.259.07:43:51.99#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.259.07:43:51.99#ibcon#about to clear, iclass 40 cls_cnt 0 2006.259.07:43:51.99#ibcon#cleared, iclass 40 cls_cnt 0 2006.259.07:43:51.99$vc4f8/vblo=2,640.99 2006.259.07:43:51.99#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.259.07:43:51.99#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.259.07:43:51.99#ibcon#ireg 17 cls_cnt 0 2006.259.07:43:51.99#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.259.07:43:51.99#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.259.07:43:51.99#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.259.07:43:51.99#ibcon#enter wrdev, iclass 4, count 0 2006.259.07:43:51.99#ibcon#first serial, iclass 4, count 0 2006.259.07:43:51.99#ibcon#enter sib2, iclass 4, count 0 2006.259.07:43:51.99#ibcon#flushed, iclass 4, count 0 2006.259.07:43:51.99#ibcon#about to write, iclass 4, count 0 2006.259.07:43:51.99#ibcon#wrote, iclass 4, count 0 2006.259.07:43:51.99#ibcon#about to read 3, iclass 4, count 0 2006.259.07:43:52.01#ibcon#read 3, iclass 4, count 0 2006.259.07:43:52.01#ibcon#about to read 4, iclass 4, count 0 2006.259.07:43:52.01#ibcon#read 4, iclass 4, count 0 2006.259.07:43:52.01#ibcon#about to read 5, iclass 4, count 0 2006.259.07:43:52.01#ibcon#read 5, iclass 4, count 0 2006.259.07:43:52.01#ibcon#about to read 6, iclass 4, count 0 2006.259.07:43:52.01#ibcon#read 6, iclass 4, count 0 2006.259.07:43:52.01#ibcon#end of sib2, iclass 4, count 0 2006.259.07:43:52.01#ibcon#*mode == 0, iclass 4, count 0 2006.259.07:43:52.01#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.259.07:43:52.01#ibcon#[28=FRQ=02,640.99\r\n] 2006.259.07:43:52.01#ibcon#*before write, iclass 4, count 0 2006.259.07:43:52.01#ibcon#enter sib2, iclass 4, count 0 2006.259.07:43:52.01#ibcon#flushed, iclass 4, count 0 2006.259.07:43:52.01#ibcon#about to write, iclass 4, count 0 2006.259.07:43:52.01#ibcon#wrote, iclass 4, count 0 2006.259.07:43:52.01#ibcon#about to read 3, iclass 4, count 0 2006.259.07:43:52.05#ibcon#read 3, iclass 4, count 0 2006.259.07:43:52.05#ibcon#about to read 4, iclass 4, count 0 2006.259.07:43:52.05#ibcon#read 4, iclass 4, count 0 2006.259.07:43:52.05#ibcon#about to read 5, iclass 4, count 0 2006.259.07:43:52.05#ibcon#read 5, iclass 4, count 0 2006.259.07:43:52.05#ibcon#about to read 6, iclass 4, count 0 2006.259.07:43:52.05#ibcon#read 6, iclass 4, count 0 2006.259.07:43:52.05#ibcon#end of sib2, iclass 4, count 0 2006.259.07:43:52.05#ibcon#*after write, iclass 4, count 0 2006.259.07:43:52.05#ibcon#*before return 0, iclass 4, count 0 2006.259.07:43:52.05#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.259.07:43:52.05#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.259.07:43:52.05#ibcon#about to clear, iclass 4 cls_cnt 0 2006.259.07:43:52.05#ibcon#cleared, iclass 4 cls_cnt 0 2006.259.07:43:52.05$vc4f8/vb=2,5 2006.259.07:43:52.05#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.259.07:43:52.05#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.259.07:43:52.05#ibcon#ireg 11 cls_cnt 2 2006.259.07:43:52.05#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.259.07:43:52.11#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.259.07:43:52.11#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.259.07:43:52.11#ibcon#enter wrdev, iclass 6, count 2 2006.259.07:43:52.11#ibcon#first serial, iclass 6, count 2 2006.259.07:43:52.11#ibcon#enter sib2, iclass 6, count 2 2006.259.07:43:52.11#ibcon#flushed, iclass 6, count 2 2006.259.07:43:52.11#ibcon#about to write, iclass 6, count 2 2006.259.07:43:52.11#ibcon#wrote, iclass 6, count 2 2006.259.07:43:52.11#ibcon#about to read 3, iclass 6, count 2 2006.259.07:43:52.13#ibcon#read 3, iclass 6, count 2 2006.259.07:43:52.13#ibcon#about to read 4, iclass 6, count 2 2006.259.07:43:52.13#ibcon#read 4, iclass 6, count 2 2006.259.07:43:52.13#ibcon#about to read 5, iclass 6, count 2 2006.259.07:43:52.13#ibcon#read 5, iclass 6, count 2 2006.259.07:43:52.13#ibcon#about to read 6, iclass 6, count 2 2006.259.07:43:52.13#ibcon#read 6, iclass 6, count 2 2006.259.07:43:52.13#ibcon#end of sib2, iclass 6, count 2 2006.259.07:43:52.13#ibcon#*mode == 0, iclass 6, count 2 2006.259.07:43:52.13#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.259.07:43:52.13#ibcon#[27=AT02-05\r\n] 2006.259.07:43:52.13#ibcon#*before write, iclass 6, count 2 2006.259.07:43:52.13#ibcon#enter sib2, iclass 6, count 2 2006.259.07:43:52.13#ibcon#flushed, iclass 6, count 2 2006.259.07:43:52.13#ibcon#about to write, iclass 6, count 2 2006.259.07:43:52.13#ibcon#wrote, iclass 6, count 2 2006.259.07:43:52.13#ibcon#about to read 3, iclass 6, count 2 2006.259.07:43:52.16#ibcon#read 3, iclass 6, count 2 2006.259.07:43:52.16#ibcon#about to read 4, iclass 6, count 2 2006.259.07:43:52.16#ibcon#read 4, iclass 6, count 2 2006.259.07:43:52.16#ibcon#about to read 5, iclass 6, count 2 2006.259.07:43:52.16#ibcon#read 5, iclass 6, count 2 2006.259.07:43:52.16#ibcon#about to read 6, iclass 6, count 2 2006.259.07:43:52.16#ibcon#read 6, iclass 6, count 2 2006.259.07:43:52.16#ibcon#end of sib2, iclass 6, count 2 2006.259.07:43:52.16#ibcon#*after write, iclass 6, count 2 2006.259.07:43:52.16#ibcon#*before return 0, iclass 6, count 2 2006.259.07:43:52.16#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.259.07:43:52.16#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.259.07:43:52.16#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.259.07:43:52.16#ibcon#ireg 7 cls_cnt 0 2006.259.07:43:52.16#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.259.07:43:52.28#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.259.07:43:52.28#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.259.07:43:52.28#ibcon#enter wrdev, iclass 6, count 0 2006.259.07:43:52.28#ibcon#first serial, iclass 6, count 0 2006.259.07:43:52.28#ibcon#enter sib2, iclass 6, count 0 2006.259.07:43:52.28#ibcon#flushed, iclass 6, count 0 2006.259.07:43:52.28#ibcon#about to write, iclass 6, count 0 2006.259.07:43:52.28#ibcon#wrote, iclass 6, count 0 2006.259.07:43:52.28#ibcon#about to read 3, iclass 6, count 0 2006.259.07:43:52.30#ibcon#read 3, iclass 6, count 0 2006.259.07:43:52.30#ibcon#about to read 4, iclass 6, count 0 2006.259.07:43:52.30#ibcon#read 4, iclass 6, count 0 2006.259.07:43:52.30#ibcon#about to read 5, iclass 6, count 0 2006.259.07:43:52.30#ibcon#read 5, iclass 6, count 0 2006.259.07:43:52.30#ibcon#about to read 6, iclass 6, count 0 2006.259.07:43:52.30#ibcon#read 6, iclass 6, count 0 2006.259.07:43:52.30#ibcon#end of sib2, iclass 6, count 0 2006.259.07:43:52.30#ibcon#*mode == 0, iclass 6, count 0 2006.259.07:43:52.30#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.259.07:43:52.30#ibcon#[27=USB\r\n] 2006.259.07:43:52.30#ibcon#*before write, iclass 6, count 0 2006.259.07:43:52.30#ibcon#enter sib2, iclass 6, count 0 2006.259.07:43:52.30#ibcon#flushed, iclass 6, count 0 2006.259.07:43:52.30#ibcon#about to write, iclass 6, count 0 2006.259.07:43:52.30#ibcon#wrote, iclass 6, count 0 2006.259.07:43:52.30#ibcon#about to read 3, iclass 6, count 0 2006.259.07:43:52.33#ibcon#read 3, iclass 6, count 0 2006.259.07:43:52.33#ibcon#about to read 4, iclass 6, count 0 2006.259.07:43:52.33#ibcon#read 4, iclass 6, count 0 2006.259.07:43:52.33#ibcon#about to read 5, iclass 6, count 0 2006.259.07:43:52.33#ibcon#read 5, iclass 6, count 0 2006.259.07:43:52.33#ibcon#about to read 6, iclass 6, count 0 2006.259.07:43:52.33#ibcon#read 6, iclass 6, count 0 2006.259.07:43:52.33#ibcon#end of sib2, iclass 6, count 0 2006.259.07:43:52.33#ibcon#*after write, iclass 6, count 0 2006.259.07:43:52.33#ibcon#*before return 0, iclass 6, count 0 2006.259.07:43:52.33#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.259.07:43:52.33#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.259.07:43:52.33#ibcon#about to clear, iclass 6 cls_cnt 0 2006.259.07:43:52.33#ibcon#cleared, iclass 6 cls_cnt 0 2006.259.07:43:52.33$vc4f8/vblo=3,656.99 2006.259.07:43:52.33#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.259.07:43:52.33#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.259.07:43:52.33#ibcon#ireg 17 cls_cnt 0 2006.259.07:43:52.33#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.259.07:43:52.33#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.259.07:43:52.33#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.259.07:43:52.33#ibcon#enter wrdev, iclass 10, count 0 2006.259.07:43:52.33#ibcon#first serial, iclass 10, count 0 2006.259.07:43:52.33#ibcon#enter sib2, iclass 10, count 0 2006.259.07:43:52.33#ibcon#flushed, iclass 10, count 0 2006.259.07:43:52.33#ibcon#about to write, iclass 10, count 0 2006.259.07:43:52.33#ibcon#wrote, iclass 10, count 0 2006.259.07:43:52.33#ibcon#about to read 3, iclass 10, count 0 2006.259.07:43:52.35#ibcon#read 3, iclass 10, count 0 2006.259.07:43:52.35#ibcon#about to read 4, iclass 10, count 0 2006.259.07:43:52.35#ibcon#read 4, iclass 10, count 0 2006.259.07:43:52.35#ibcon#about to read 5, iclass 10, count 0 2006.259.07:43:52.35#ibcon#read 5, iclass 10, count 0 2006.259.07:43:52.35#ibcon#about to read 6, iclass 10, count 0 2006.259.07:43:52.35#ibcon#read 6, iclass 10, count 0 2006.259.07:43:52.35#ibcon#end of sib2, iclass 10, count 0 2006.259.07:43:52.35#ibcon#*mode == 0, iclass 10, count 0 2006.259.07:43:52.35#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.259.07:43:52.35#ibcon#[28=FRQ=03,656.99\r\n] 2006.259.07:43:52.35#ibcon#*before write, iclass 10, count 0 2006.259.07:43:52.35#ibcon#enter sib2, iclass 10, count 0 2006.259.07:43:52.35#ibcon#flushed, iclass 10, count 0 2006.259.07:43:52.35#ibcon#about to write, iclass 10, count 0 2006.259.07:43:52.35#ibcon#wrote, iclass 10, count 0 2006.259.07:43:52.35#ibcon#about to read 3, iclass 10, count 0 2006.259.07:43:52.39#ibcon#read 3, iclass 10, count 0 2006.259.07:43:52.39#ibcon#about to read 4, iclass 10, count 0 2006.259.07:43:52.39#ibcon#read 4, iclass 10, count 0 2006.259.07:43:52.39#ibcon#about to read 5, iclass 10, count 0 2006.259.07:43:52.39#ibcon#read 5, iclass 10, count 0 2006.259.07:43:52.39#ibcon#about to read 6, iclass 10, count 0 2006.259.07:43:52.39#ibcon#read 6, iclass 10, count 0 2006.259.07:43:52.39#ibcon#end of sib2, iclass 10, count 0 2006.259.07:43:52.39#ibcon#*after write, iclass 10, count 0 2006.259.07:43:52.39#ibcon#*before return 0, iclass 10, count 0 2006.259.07:43:52.39#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.259.07:43:52.39#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.259.07:43:52.39#ibcon#about to clear, iclass 10 cls_cnt 0 2006.259.07:43:52.39#ibcon#cleared, iclass 10 cls_cnt 0 2006.259.07:43:52.39$vc4f8/vb=3,4 2006.259.07:43:52.39#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.259.07:43:52.39#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.259.07:43:52.39#ibcon#ireg 11 cls_cnt 2 2006.259.07:43:52.39#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.259.07:43:52.45#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.259.07:43:52.45#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.259.07:43:52.45#ibcon#enter wrdev, iclass 12, count 2 2006.259.07:43:52.45#ibcon#first serial, iclass 12, count 2 2006.259.07:43:52.45#ibcon#enter sib2, iclass 12, count 2 2006.259.07:43:52.45#ibcon#flushed, iclass 12, count 2 2006.259.07:43:52.45#ibcon#about to write, iclass 12, count 2 2006.259.07:43:52.45#ibcon#wrote, iclass 12, count 2 2006.259.07:43:52.45#ibcon#about to read 3, iclass 12, count 2 2006.259.07:43:52.47#ibcon#read 3, iclass 12, count 2 2006.259.07:43:52.47#ibcon#about to read 4, iclass 12, count 2 2006.259.07:43:52.47#ibcon#read 4, iclass 12, count 2 2006.259.07:43:52.47#ibcon#about to read 5, iclass 12, count 2 2006.259.07:43:52.47#ibcon#read 5, iclass 12, count 2 2006.259.07:43:52.47#ibcon#about to read 6, iclass 12, count 2 2006.259.07:43:52.47#ibcon#read 6, iclass 12, count 2 2006.259.07:43:52.47#ibcon#end of sib2, iclass 12, count 2 2006.259.07:43:52.47#ibcon#*mode == 0, iclass 12, count 2 2006.259.07:43:52.47#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.259.07:43:52.47#ibcon#[27=AT03-04\r\n] 2006.259.07:43:52.47#ibcon#*before write, iclass 12, count 2 2006.259.07:43:52.47#ibcon#enter sib2, iclass 12, count 2 2006.259.07:43:52.47#ibcon#flushed, iclass 12, count 2 2006.259.07:43:52.47#ibcon#about to write, iclass 12, count 2 2006.259.07:43:52.47#ibcon#wrote, iclass 12, count 2 2006.259.07:43:52.47#ibcon#about to read 3, iclass 12, count 2 2006.259.07:43:52.50#ibcon#read 3, iclass 12, count 2 2006.259.07:43:52.50#ibcon#about to read 4, iclass 12, count 2 2006.259.07:43:52.50#ibcon#read 4, iclass 12, count 2 2006.259.07:43:52.50#ibcon#about to read 5, iclass 12, count 2 2006.259.07:43:52.50#ibcon#read 5, iclass 12, count 2 2006.259.07:43:52.50#ibcon#about to read 6, iclass 12, count 2 2006.259.07:43:52.50#ibcon#read 6, iclass 12, count 2 2006.259.07:43:52.50#ibcon#end of sib2, iclass 12, count 2 2006.259.07:43:52.50#ibcon#*after write, iclass 12, count 2 2006.259.07:43:52.50#ibcon#*before return 0, iclass 12, count 2 2006.259.07:43:52.50#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.259.07:43:52.50#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.259.07:43:52.50#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.259.07:43:52.50#ibcon#ireg 7 cls_cnt 0 2006.259.07:43:52.50#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.259.07:43:52.62#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.259.07:43:52.62#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.259.07:43:52.62#ibcon#enter wrdev, iclass 12, count 0 2006.259.07:43:52.62#ibcon#first serial, iclass 12, count 0 2006.259.07:43:52.62#ibcon#enter sib2, iclass 12, count 0 2006.259.07:43:52.62#ibcon#flushed, iclass 12, count 0 2006.259.07:43:52.62#ibcon#about to write, iclass 12, count 0 2006.259.07:43:52.62#ibcon#wrote, iclass 12, count 0 2006.259.07:43:52.62#ibcon#about to read 3, iclass 12, count 0 2006.259.07:43:52.64#ibcon#read 3, iclass 12, count 0 2006.259.07:43:52.64#ibcon#about to read 4, iclass 12, count 0 2006.259.07:43:52.64#ibcon#read 4, iclass 12, count 0 2006.259.07:43:52.64#ibcon#about to read 5, iclass 12, count 0 2006.259.07:43:52.64#ibcon#read 5, iclass 12, count 0 2006.259.07:43:52.64#ibcon#about to read 6, iclass 12, count 0 2006.259.07:43:52.64#ibcon#read 6, iclass 12, count 0 2006.259.07:43:52.64#ibcon#end of sib2, iclass 12, count 0 2006.259.07:43:52.64#ibcon#*mode == 0, iclass 12, count 0 2006.259.07:43:52.64#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.259.07:43:52.64#ibcon#[27=USB\r\n] 2006.259.07:43:52.64#ibcon#*before write, iclass 12, count 0 2006.259.07:43:52.64#ibcon#enter sib2, iclass 12, count 0 2006.259.07:43:52.64#ibcon#flushed, iclass 12, count 0 2006.259.07:43:52.64#ibcon#about to write, iclass 12, count 0 2006.259.07:43:52.64#ibcon#wrote, iclass 12, count 0 2006.259.07:43:52.64#ibcon#about to read 3, iclass 12, count 0 2006.259.07:43:52.67#ibcon#read 3, iclass 12, count 0 2006.259.07:43:52.67#ibcon#about to read 4, iclass 12, count 0 2006.259.07:43:52.67#ibcon#read 4, iclass 12, count 0 2006.259.07:43:52.67#ibcon#about to read 5, iclass 12, count 0 2006.259.07:43:52.67#ibcon#read 5, iclass 12, count 0 2006.259.07:43:52.67#ibcon#about to read 6, iclass 12, count 0 2006.259.07:43:52.67#ibcon#read 6, iclass 12, count 0 2006.259.07:43:52.67#ibcon#end of sib2, iclass 12, count 0 2006.259.07:43:52.67#ibcon#*after write, iclass 12, count 0 2006.259.07:43:52.67#ibcon#*before return 0, iclass 12, count 0 2006.259.07:43:52.67#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.259.07:43:52.67#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.259.07:43:52.67#ibcon#about to clear, iclass 12 cls_cnt 0 2006.259.07:43:52.67#ibcon#cleared, iclass 12 cls_cnt 0 2006.259.07:43:52.67$vc4f8/vblo=4,712.99 2006.259.07:43:52.67#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.259.07:43:52.67#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.259.07:43:52.67#ibcon#ireg 17 cls_cnt 0 2006.259.07:43:52.67#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.259.07:43:52.67#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.259.07:43:52.67#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.259.07:43:52.67#ibcon#enter wrdev, iclass 14, count 0 2006.259.07:43:52.67#ibcon#first serial, iclass 14, count 0 2006.259.07:43:52.67#ibcon#enter sib2, iclass 14, count 0 2006.259.07:43:52.67#ibcon#flushed, iclass 14, count 0 2006.259.07:43:52.67#ibcon#about to write, iclass 14, count 0 2006.259.07:43:52.67#ibcon#wrote, iclass 14, count 0 2006.259.07:43:52.67#ibcon#about to read 3, iclass 14, count 0 2006.259.07:43:52.69#ibcon#read 3, iclass 14, count 0 2006.259.07:43:52.69#ibcon#about to read 4, iclass 14, count 0 2006.259.07:43:52.69#ibcon#read 4, iclass 14, count 0 2006.259.07:43:52.69#ibcon#about to read 5, iclass 14, count 0 2006.259.07:43:52.69#ibcon#read 5, iclass 14, count 0 2006.259.07:43:52.69#ibcon#about to read 6, iclass 14, count 0 2006.259.07:43:52.69#ibcon#read 6, iclass 14, count 0 2006.259.07:43:52.69#ibcon#end of sib2, iclass 14, count 0 2006.259.07:43:52.69#ibcon#*mode == 0, iclass 14, count 0 2006.259.07:43:52.69#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.259.07:43:52.69#ibcon#[28=FRQ=04,712.99\r\n] 2006.259.07:43:52.69#ibcon#*before write, iclass 14, count 0 2006.259.07:43:52.69#ibcon#enter sib2, iclass 14, count 0 2006.259.07:43:52.69#ibcon#flushed, iclass 14, count 0 2006.259.07:43:52.69#ibcon#about to write, iclass 14, count 0 2006.259.07:43:52.69#ibcon#wrote, iclass 14, count 0 2006.259.07:43:52.69#ibcon#about to read 3, iclass 14, count 0 2006.259.07:43:52.73#ibcon#read 3, iclass 14, count 0 2006.259.07:43:52.73#ibcon#about to read 4, iclass 14, count 0 2006.259.07:43:52.73#ibcon#read 4, iclass 14, count 0 2006.259.07:43:52.73#ibcon#about to read 5, iclass 14, count 0 2006.259.07:43:52.73#ibcon#read 5, iclass 14, count 0 2006.259.07:43:52.73#ibcon#about to read 6, iclass 14, count 0 2006.259.07:43:52.73#ibcon#read 6, iclass 14, count 0 2006.259.07:43:52.73#ibcon#end of sib2, iclass 14, count 0 2006.259.07:43:52.73#ibcon#*after write, iclass 14, count 0 2006.259.07:43:52.73#ibcon#*before return 0, iclass 14, count 0 2006.259.07:43:52.73#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.259.07:43:52.73#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.259.07:43:52.73#ibcon#about to clear, iclass 14 cls_cnt 0 2006.259.07:43:52.73#ibcon#cleared, iclass 14 cls_cnt 0 2006.259.07:43:52.73$vc4f8/vb=4,5 2006.259.07:43:52.73#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.259.07:43:52.73#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.259.07:43:52.73#ibcon#ireg 11 cls_cnt 2 2006.259.07:43:52.73#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.259.07:43:52.79#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.259.07:43:52.79#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.259.07:43:52.79#ibcon#enter wrdev, iclass 16, count 2 2006.259.07:43:52.79#ibcon#first serial, iclass 16, count 2 2006.259.07:43:52.79#ibcon#enter sib2, iclass 16, count 2 2006.259.07:43:52.79#ibcon#flushed, iclass 16, count 2 2006.259.07:43:52.79#ibcon#about to write, iclass 16, count 2 2006.259.07:43:52.79#ibcon#wrote, iclass 16, count 2 2006.259.07:43:52.79#ibcon#about to read 3, iclass 16, count 2 2006.259.07:43:52.81#ibcon#read 3, iclass 16, count 2 2006.259.07:43:52.81#ibcon#about to read 4, iclass 16, count 2 2006.259.07:43:52.81#ibcon#read 4, iclass 16, count 2 2006.259.07:43:52.81#ibcon#about to read 5, iclass 16, count 2 2006.259.07:43:52.81#ibcon#read 5, iclass 16, count 2 2006.259.07:43:52.81#ibcon#about to read 6, iclass 16, count 2 2006.259.07:43:52.81#ibcon#read 6, iclass 16, count 2 2006.259.07:43:52.81#ibcon#end of sib2, iclass 16, count 2 2006.259.07:43:52.81#ibcon#*mode == 0, iclass 16, count 2 2006.259.07:43:52.81#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.259.07:43:52.81#ibcon#[27=AT04-05\r\n] 2006.259.07:43:52.81#ibcon#*before write, iclass 16, count 2 2006.259.07:43:52.81#ibcon#enter sib2, iclass 16, count 2 2006.259.07:43:52.81#ibcon#flushed, iclass 16, count 2 2006.259.07:43:52.81#ibcon#about to write, iclass 16, count 2 2006.259.07:43:52.81#ibcon#wrote, iclass 16, count 2 2006.259.07:43:52.81#ibcon#about to read 3, iclass 16, count 2 2006.259.07:43:52.84#ibcon#read 3, iclass 16, count 2 2006.259.07:43:52.84#ibcon#about to read 4, iclass 16, count 2 2006.259.07:43:52.84#ibcon#read 4, iclass 16, count 2 2006.259.07:43:52.84#ibcon#about to read 5, iclass 16, count 2 2006.259.07:43:52.84#ibcon#read 5, iclass 16, count 2 2006.259.07:43:52.84#ibcon#about to read 6, iclass 16, count 2 2006.259.07:43:52.84#ibcon#read 6, iclass 16, count 2 2006.259.07:43:52.84#ibcon#end of sib2, iclass 16, count 2 2006.259.07:43:52.84#ibcon#*after write, iclass 16, count 2 2006.259.07:43:52.84#ibcon#*before return 0, iclass 16, count 2 2006.259.07:43:52.84#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.259.07:43:52.84#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.259.07:43:52.84#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.259.07:43:52.84#ibcon#ireg 7 cls_cnt 0 2006.259.07:43:52.84#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.259.07:43:52.96#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.259.07:43:52.96#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.259.07:43:52.96#ibcon#enter wrdev, iclass 16, count 0 2006.259.07:43:52.96#ibcon#first serial, iclass 16, count 0 2006.259.07:43:52.96#ibcon#enter sib2, iclass 16, count 0 2006.259.07:43:52.96#ibcon#flushed, iclass 16, count 0 2006.259.07:43:52.96#ibcon#about to write, iclass 16, count 0 2006.259.07:43:52.96#ibcon#wrote, iclass 16, count 0 2006.259.07:43:52.96#ibcon#about to read 3, iclass 16, count 0 2006.259.07:43:52.98#ibcon#read 3, iclass 16, count 0 2006.259.07:43:52.98#ibcon#about to read 4, iclass 16, count 0 2006.259.07:43:52.98#ibcon#read 4, iclass 16, count 0 2006.259.07:43:52.98#ibcon#about to read 5, iclass 16, count 0 2006.259.07:43:52.98#ibcon#read 5, iclass 16, count 0 2006.259.07:43:52.98#ibcon#about to read 6, iclass 16, count 0 2006.259.07:43:52.98#ibcon#read 6, iclass 16, count 0 2006.259.07:43:52.98#ibcon#end of sib2, iclass 16, count 0 2006.259.07:43:52.98#ibcon#*mode == 0, iclass 16, count 0 2006.259.07:43:52.98#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.259.07:43:52.98#ibcon#[27=USB\r\n] 2006.259.07:43:52.98#ibcon#*before write, iclass 16, count 0 2006.259.07:43:52.98#ibcon#enter sib2, iclass 16, count 0 2006.259.07:43:52.98#ibcon#flushed, iclass 16, count 0 2006.259.07:43:52.98#ibcon#about to write, iclass 16, count 0 2006.259.07:43:52.98#ibcon#wrote, iclass 16, count 0 2006.259.07:43:52.98#ibcon#about to read 3, iclass 16, count 0 2006.259.07:43:53.01#ibcon#read 3, iclass 16, count 0 2006.259.07:43:53.01#ibcon#about to read 4, iclass 16, count 0 2006.259.07:43:53.01#ibcon#read 4, iclass 16, count 0 2006.259.07:43:53.01#ibcon#about to read 5, iclass 16, count 0 2006.259.07:43:53.01#ibcon#read 5, iclass 16, count 0 2006.259.07:43:53.01#ibcon#about to read 6, iclass 16, count 0 2006.259.07:43:53.01#ibcon#read 6, iclass 16, count 0 2006.259.07:43:53.01#ibcon#end of sib2, iclass 16, count 0 2006.259.07:43:53.01#ibcon#*after write, iclass 16, count 0 2006.259.07:43:53.01#ibcon#*before return 0, iclass 16, count 0 2006.259.07:43:53.01#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.259.07:43:53.01#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.259.07:43:53.01#ibcon#about to clear, iclass 16 cls_cnt 0 2006.259.07:43:53.01#ibcon#cleared, iclass 16 cls_cnt 0 2006.259.07:43:53.01$vc4f8/vblo=5,744.99 2006.259.07:43:53.01#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.259.07:43:53.01#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.259.07:43:53.01#ibcon#ireg 17 cls_cnt 0 2006.259.07:43:53.01#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.259.07:43:53.01#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.259.07:43:53.01#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.259.07:43:53.01#ibcon#enter wrdev, iclass 18, count 0 2006.259.07:43:53.01#ibcon#first serial, iclass 18, count 0 2006.259.07:43:53.01#ibcon#enter sib2, iclass 18, count 0 2006.259.07:43:53.01#ibcon#flushed, iclass 18, count 0 2006.259.07:43:53.01#ibcon#about to write, iclass 18, count 0 2006.259.07:43:53.01#ibcon#wrote, iclass 18, count 0 2006.259.07:43:53.01#ibcon#about to read 3, iclass 18, count 0 2006.259.07:43:53.03#ibcon#read 3, iclass 18, count 0 2006.259.07:43:53.03#ibcon#about to read 4, iclass 18, count 0 2006.259.07:43:53.03#ibcon#read 4, iclass 18, count 0 2006.259.07:43:53.03#ibcon#about to read 5, iclass 18, count 0 2006.259.07:43:53.03#ibcon#read 5, iclass 18, count 0 2006.259.07:43:53.03#ibcon#about to read 6, iclass 18, count 0 2006.259.07:43:53.03#ibcon#read 6, iclass 18, count 0 2006.259.07:43:53.03#ibcon#end of sib2, iclass 18, count 0 2006.259.07:43:53.03#ibcon#*mode == 0, iclass 18, count 0 2006.259.07:43:53.03#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.259.07:43:53.03#ibcon#[28=FRQ=05,744.99\r\n] 2006.259.07:43:53.03#ibcon#*before write, iclass 18, count 0 2006.259.07:43:53.03#ibcon#enter sib2, iclass 18, count 0 2006.259.07:43:53.03#ibcon#flushed, iclass 18, count 0 2006.259.07:43:53.03#ibcon#about to write, iclass 18, count 0 2006.259.07:43:53.03#ibcon#wrote, iclass 18, count 0 2006.259.07:43:53.03#ibcon#about to read 3, iclass 18, count 0 2006.259.07:43:53.07#ibcon#read 3, iclass 18, count 0 2006.259.07:43:53.07#ibcon#about to read 4, iclass 18, count 0 2006.259.07:43:53.07#ibcon#read 4, iclass 18, count 0 2006.259.07:43:53.07#ibcon#about to read 5, iclass 18, count 0 2006.259.07:43:53.07#ibcon#read 5, iclass 18, count 0 2006.259.07:43:53.07#ibcon#about to read 6, iclass 18, count 0 2006.259.07:43:53.07#ibcon#read 6, iclass 18, count 0 2006.259.07:43:53.07#ibcon#end of sib2, iclass 18, count 0 2006.259.07:43:53.07#ibcon#*after write, iclass 18, count 0 2006.259.07:43:53.07#ibcon#*before return 0, iclass 18, count 0 2006.259.07:43:53.07#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.259.07:43:53.07#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.259.07:43:53.07#ibcon#about to clear, iclass 18 cls_cnt 0 2006.259.07:43:53.07#ibcon#cleared, iclass 18 cls_cnt 0 2006.259.07:43:53.07$vc4f8/vb=5,4 2006.259.07:43:53.07#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.259.07:43:53.07#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.259.07:43:53.07#ibcon#ireg 11 cls_cnt 2 2006.259.07:43:53.07#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.259.07:43:53.13#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.259.07:43:53.13#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.259.07:43:53.13#ibcon#enter wrdev, iclass 20, count 2 2006.259.07:43:53.13#ibcon#first serial, iclass 20, count 2 2006.259.07:43:53.13#ibcon#enter sib2, iclass 20, count 2 2006.259.07:43:53.13#ibcon#flushed, iclass 20, count 2 2006.259.07:43:53.13#ibcon#about to write, iclass 20, count 2 2006.259.07:43:53.13#ibcon#wrote, iclass 20, count 2 2006.259.07:43:53.13#ibcon#about to read 3, iclass 20, count 2 2006.259.07:43:53.15#ibcon#read 3, iclass 20, count 2 2006.259.07:43:53.15#ibcon#about to read 4, iclass 20, count 2 2006.259.07:43:53.15#ibcon#read 4, iclass 20, count 2 2006.259.07:43:53.15#ibcon#about to read 5, iclass 20, count 2 2006.259.07:43:53.15#ibcon#read 5, iclass 20, count 2 2006.259.07:43:53.15#ibcon#about to read 6, iclass 20, count 2 2006.259.07:43:53.15#ibcon#read 6, iclass 20, count 2 2006.259.07:43:53.15#ibcon#end of sib2, iclass 20, count 2 2006.259.07:43:53.15#ibcon#*mode == 0, iclass 20, count 2 2006.259.07:43:53.15#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.259.07:43:53.15#ibcon#[27=AT05-04\r\n] 2006.259.07:43:53.15#ibcon#*before write, iclass 20, count 2 2006.259.07:43:53.15#ibcon#enter sib2, iclass 20, count 2 2006.259.07:43:53.15#ibcon#flushed, iclass 20, count 2 2006.259.07:43:53.15#ibcon#about to write, iclass 20, count 2 2006.259.07:43:53.15#ibcon#wrote, iclass 20, count 2 2006.259.07:43:53.15#ibcon#about to read 3, iclass 20, count 2 2006.259.07:43:53.18#ibcon#read 3, iclass 20, count 2 2006.259.07:43:53.18#ibcon#about to read 4, iclass 20, count 2 2006.259.07:43:53.18#ibcon#read 4, iclass 20, count 2 2006.259.07:43:53.18#ibcon#about to read 5, iclass 20, count 2 2006.259.07:43:53.18#ibcon#read 5, iclass 20, count 2 2006.259.07:43:53.18#ibcon#about to read 6, iclass 20, count 2 2006.259.07:43:53.18#ibcon#read 6, iclass 20, count 2 2006.259.07:43:53.18#ibcon#end of sib2, iclass 20, count 2 2006.259.07:43:53.18#ibcon#*after write, iclass 20, count 2 2006.259.07:43:53.18#ibcon#*before return 0, iclass 20, count 2 2006.259.07:43:53.18#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.259.07:43:53.18#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.259.07:43:53.18#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.259.07:43:53.18#ibcon#ireg 7 cls_cnt 0 2006.259.07:43:53.18#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.259.07:43:53.30#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.259.07:43:53.30#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.259.07:43:53.30#ibcon#enter wrdev, iclass 20, count 0 2006.259.07:43:53.30#ibcon#first serial, iclass 20, count 0 2006.259.07:43:53.30#ibcon#enter sib2, iclass 20, count 0 2006.259.07:43:53.30#ibcon#flushed, iclass 20, count 0 2006.259.07:43:53.30#ibcon#about to write, iclass 20, count 0 2006.259.07:43:53.30#ibcon#wrote, iclass 20, count 0 2006.259.07:43:53.30#ibcon#about to read 3, iclass 20, count 0 2006.259.07:43:53.32#ibcon#read 3, iclass 20, count 0 2006.259.07:43:53.32#ibcon#about to read 4, iclass 20, count 0 2006.259.07:43:53.32#ibcon#read 4, iclass 20, count 0 2006.259.07:43:53.32#ibcon#about to read 5, iclass 20, count 0 2006.259.07:43:53.32#ibcon#read 5, iclass 20, count 0 2006.259.07:43:53.32#ibcon#about to read 6, iclass 20, count 0 2006.259.07:43:53.32#ibcon#read 6, iclass 20, count 0 2006.259.07:43:53.32#ibcon#end of sib2, iclass 20, count 0 2006.259.07:43:53.32#ibcon#*mode == 0, iclass 20, count 0 2006.259.07:43:53.32#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.259.07:43:53.32#ibcon#[27=USB\r\n] 2006.259.07:43:53.32#ibcon#*before write, iclass 20, count 0 2006.259.07:43:53.32#ibcon#enter sib2, iclass 20, count 0 2006.259.07:43:53.32#ibcon#flushed, iclass 20, count 0 2006.259.07:43:53.32#ibcon#about to write, iclass 20, count 0 2006.259.07:43:53.32#ibcon#wrote, iclass 20, count 0 2006.259.07:43:53.32#ibcon#about to read 3, iclass 20, count 0 2006.259.07:43:53.35#ibcon#read 3, iclass 20, count 0 2006.259.07:43:53.35#ibcon#about to read 4, iclass 20, count 0 2006.259.07:43:53.35#ibcon#read 4, iclass 20, count 0 2006.259.07:43:53.35#ibcon#about to read 5, iclass 20, count 0 2006.259.07:43:53.35#ibcon#read 5, iclass 20, count 0 2006.259.07:43:53.35#ibcon#about to read 6, iclass 20, count 0 2006.259.07:43:53.35#ibcon#read 6, iclass 20, count 0 2006.259.07:43:53.35#ibcon#end of sib2, iclass 20, count 0 2006.259.07:43:53.35#ibcon#*after write, iclass 20, count 0 2006.259.07:43:53.35#ibcon#*before return 0, iclass 20, count 0 2006.259.07:43:53.35#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.259.07:43:53.35#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.259.07:43:53.35#ibcon#about to clear, iclass 20 cls_cnt 0 2006.259.07:43:53.35#ibcon#cleared, iclass 20 cls_cnt 0 2006.259.07:43:53.35$vc4f8/vblo=6,752.99 2006.259.07:43:53.35#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.259.07:43:53.35#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.259.07:43:53.35#ibcon#ireg 17 cls_cnt 0 2006.259.07:43:53.35#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.259.07:43:53.35#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.259.07:43:53.35#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.259.07:43:53.35#ibcon#enter wrdev, iclass 22, count 0 2006.259.07:43:53.35#ibcon#first serial, iclass 22, count 0 2006.259.07:43:53.35#ibcon#enter sib2, iclass 22, count 0 2006.259.07:43:53.35#ibcon#flushed, iclass 22, count 0 2006.259.07:43:53.35#ibcon#about to write, iclass 22, count 0 2006.259.07:43:53.35#ibcon#wrote, iclass 22, count 0 2006.259.07:43:53.35#ibcon#about to read 3, iclass 22, count 0 2006.259.07:43:53.37#ibcon#read 3, iclass 22, count 0 2006.259.07:43:53.37#ibcon#about to read 4, iclass 22, count 0 2006.259.07:43:53.37#ibcon#read 4, iclass 22, count 0 2006.259.07:43:53.37#ibcon#about to read 5, iclass 22, count 0 2006.259.07:43:53.37#ibcon#read 5, iclass 22, count 0 2006.259.07:43:53.37#ibcon#about to read 6, iclass 22, count 0 2006.259.07:43:53.37#ibcon#read 6, iclass 22, count 0 2006.259.07:43:53.37#ibcon#end of sib2, iclass 22, count 0 2006.259.07:43:53.37#ibcon#*mode == 0, iclass 22, count 0 2006.259.07:43:53.37#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.259.07:43:53.37#ibcon#[28=FRQ=06,752.99\r\n] 2006.259.07:43:53.37#ibcon#*before write, iclass 22, count 0 2006.259.07:43:53.37#ibcon#enter sib2, iclass 22, count 0 2006.259.07:43:53.37#ibcon#flushed, iclass 22, count 0 2006.259.07:43:53.37#ibcon#about to write, iclass 22, count 0 2006.259.07:43:53.37#ibcon#wrote, iclass 22, count 0 2006.259.07:43:53.37#ibcon#about to read 3, iclass 22, count 0 2006.259.07:43:53.41#ibcon#read 3, iclass 22, count 0 2006.259.07:43:53.41#ibcon#about to read 4, iclass 22, count 0 2006.259.07:43:53.41#ibcon#read 4, iclass 22, count 0 2006.259.07:43:53.41#ibcon#about to read 5, iclass 22, count 0 2006.259.07:43:53.41#ibcon#read 5, iclass 22, count 0 2006.259.07:43:53.41#ibcon#about to read 6, iclass 22, count 0 2006.259.07:43:53.41#ibcon#read 6, iclass 22, count 0 2006.259.07:43:53.41#ibcon#end of sib2, iclass 22, count 0 2006.259.07:43:53.41#ibcon#*after write, iclass 22, count 0 2006.259.07:43:53.41#ibcon#*before return 0, iclass 22, count 0 2006.259.07:43:53.41#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.259.07:43:53.41#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.259.07:43:53.41#ibcon#about to clear, iclass 22 cls_cnt 0 2006.259.07:43:53.41#ibcon#cleared, iclass 22 cls_cnt 0 2006.259.07:43:53.41$vc4f8/vb=6,4 2006.259.07:43:53.41#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.259.07:43:53.41#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.259.07:43:53.41#ibcon#ireg 11 cls_cnt 2 2006.259.07:43:53.41#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.259.07:43:53.47#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.259.07:43:53.47#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.259.07:43:53.47#ibcon#enter wrdev, iclass 24, count 2 2006.259.07:43:53.47#ibcon#first serial, iclass 24, count 2 2006.259.07:43:53.47#ibcon#enter sib2, iclass 24, count 2 2006.259.07:43:53.47#ibcon#flushed, iclass 24, count 2 2006.259.07:43:53.47#ibcon#about to write, iclass 24, count 2 2006.259.07:43:53.47#ibcon#wrote, iclass 24, count 2 2006.259.07:43:53.47#ibcon#about to read 3, iclass 24, count 2 2006.259.07:43:53.49#ibcon#read 3, iclass 24, count 2 2006.259.07:43:53.49#ibcon#about to read 4, iclass 24, count 2 2006.259.07:43:53.49#ibcon#read 4, iclass 24, count 2 2006.259.07:43:53.49#ibcon#about to read 5, iclass 24, count 2 2006.259.07:43:53.49#ibcon#read 5, iclass 24, count 2 2006.259.07:43:53.49#ibcon#about to read 6, iclass 24, count 2 2006.259.07:43:53.49#ibcon#read 6, iclass 24, count 2 2006.259.07:43:53.49#ibcon#end of sib2, iclass 24, count 2 2006.259.07:43:53.49#ibcon#*mode == 0, iclass 24, count 2 2006.259.07:43:53.49#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.259.07:43:53.49#ibcon#[27=AT06-04\r\n] 2006.259.07:43:53.49#ibcon#*before write, iclass 24, count 2 2006.259.07:43:53.49#ibcon#enter sib2, iclass 24, count 2 2006.259.07:43:53.49#ibcon#flushed, iclass 24, count 2 2006.259.07:43:53.49#ibcon#about to write, iclass 24, count 2 2006.259.07:43:53.49#ibcon#wrote, iclass 24, count 2 2006.259.07:43:53.49#ibcon#about to read 3, iclass 24, count 2 2006.259.07:43:53.52#ibcon#read 3, iclass 24, count 2 2006.259.07:43:53.52#ibcon#about to read 4, iclass 24, count 2 2006.259.07:43:53.52#ibcon#read 4, iclass 24, count 2 2006.259.07:43:53.52#ibcon#about to read 5, iclass 24, count 2 2006.259.07:43:53.52#ibcon#read 5, iclass 24, count 2 2006.259.07:43:53.52#ibcon#about to read 6, iclass 24, count 2 2006.259.07:43:53.52#ibcon#read 6, iclass 24, count 2 2006.259.07:43:53.52#ibcon#end of sib2, iclass 24, count 2 2006.259.07:43:53.52#ibcon#*after write, iclass 24, count 2 2006.259.07:43:53.52#ibcon#*before return 0, iclass 24, count 2 2006.259.07:43:53.52#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.259.07:43:53.52#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.259.07:43:53.52#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.259.07:43:53.52#ibcon#ireg 7 cls_cnt 0 2006.259.07:43:53.52#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.259.07:43:53.64#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.259.07:43:53.64#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.259.07:43:53.64#ibcon#enter wrdev, iclass 24, count 0 2006.259.07:43:53.64#ibcon#first serial, iclass 24, count 0 2006.259.07:43:53.64#ibcon#enter sib2, iclass 24, count 0 2006.259.07:43:53.64#ibcon#flushed, iclass 24, count 0 2006.259.07:43:53.64#ibcon#about to write, iclass 24, count 0 2006.259.07:43:53.64#ibcon#wrote, iclass 24, count 0 2006.259.07:43:53.64#ibcon#about to read 3, iclass 24, count 0 2006.259.07:43:53.66#ibcon#read 3, iclass 24, count 0 2006.259.07:43:53.66#ibcon#about to read 4, iclass 24, count 0 2006.259.07:43:53.66#ibcon#read 4, iclass 24, count 0 2006.259.07:43:53.66#ibcon#about to read 5, iclass 24, count 0 2006.259.07:43:53.66#ibcon#read 5, iclass 24, count 0 2006.259.07:43:53.66#ibcon#about to read 6, iclass 24, count 0 2006.259.07:43:53.66#ibcon#read 6, iclass 24, count 0 2006.259.07:43:53.66#ibcon#end of sib2, iclass 24, count 0 2006.259.07:43:53.66#ibcon#*mode == 0, iclass 24, count 0 2006.259.07:43:53.66#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.259.07:43:53.66#ibcon#[27=USB\r\n] 2006.259.07:43:53.66#ibcon#*before write, iclass 24, count 0 2006.259.07:43:53.66#ibcon#enter sib2, iclass 24, count 0 2006.259.07:43:53.66#ibcon#flushed, iclass 24, count 0 2006.259.07:43:53.66#ibcon#about to write, iclass 24, count 0 2006.259.07:43:53.66#ibcon#wrote, iclass 24, count 0 2006.259.07:43:53.66#ibcon#about to read 3, iclass 24, count 0 2006.259.07:43:53.69#ibcon#read 3, iclass 24, count 0 2006.259.07:43:53.69#ibcon#about to read 4, iclass 24, count 0 2006.259.07:43:53.69#ibcon#read 4, iclass 24, count 0 2006.259.07:43:53.69#ibcon#about to read 5, iclass 24, count 0 2006.259.07:43:53.69#ibcon#read 5, iclass 24, count 0 2006.259.07:43:53.69#ibcon#about to read 6, iclass 24, count 0 2006.259.07:43:53.69#ibcon#read 6, iclass 24, count 0 2006.259.07:43:53.69#ibcon#end of sib2, iclass 24, count 0 2006.259.07:43:53.69#ibcon#*after write, iclass 24, count 0 2006.259.07:43:53.69#ibcon#*before return 0, iclass 24, count 0 2006.259.07:43:53.69#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.259.07:43:53.69#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.259.07:43:53.69#ibcon#about to clear, iclass 24 cls_cnt 0 2006.259.07:43:53.69#ibcon#cleared, iclass 24 cls_cnt 0 2006.259.07:43:53.69$vc4f8/vabw=wide 2006.259.07:43:53.69#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.259.07:43:53.69#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.259.07:43:53.69#ibcon#ireg 8 cls_cnt 0 2006.259.07:43:53.69#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.259.07:43:53.69#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.259.07:43:53.69#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.259.07:43:53.69#ibcon#enter wrdev, iclass 26, count 0 2006.259.07:43:53.69#ibcon#first serial, iclass 26, count 0 2006.259.07:43:53.69#ibcon#enter sib2, iclass 26, count 0 2006.259.07:43:53.69#ibcon#flushed, iclass 26, count 0 2006.259.07:43:53.69#ibcon#about to write, iclass 26, count 0 2006.259.07:43:53.69#ibcon#wrote, iclass 26, count 0 2006.259.07:43:53.69#ibcon#about to read 3, iclass 26, count 0 2006.259.07:43:53.71#ibcon#read 3, iclass 26, count 0 2006.259.07:43:53.71#ibcon#about to read 4, iclass 26, count 0 2006.259.07:43:53.71#ibcon#read 4, iclass 26, count 0 2006.259.07:43:53.71#ibcon#about to read 5, iclass 26, count 0 2006.259.07:43:53.71#ibcon#read 5, iclass 26, count 0 2006.259.07:43:53.71#ibcon#about to read 6, iclass 26, count 0 2006.259.07:43:53.71#ibcon#read 6, iclass 26, count 0 2006.259.07:43:53.71#ibcon#end of sib2, iclass 26, count 0 2006.259.07:43:53.71#ibcon#*mode == 0, iclass 26, count 0 2006.259.07:43:53.71#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.259.07:43:53.71#ibcon#[25=BW32\r\n] 2006.259.07:43:53.71#ibcon#*before write, iclass 26, count 0 2006.259.07:43:53.71#ibcon#enter sib2, iclass 26, count 0 2006.259.07:43:53.71#ibcon#flushed, iclass 26, count 0 2006.259.07:43:53.71#ibcon#about to write, iclass 26, count 0 2006.259.07:43:53.71#ibcon#wrote, iclass 26, count 0 2006.259.07:43:53.71#ibcon#about to read 3, iclass 26, count 0 2006.259.07:43:53.74#ibcon#read 3, iclass 26, count 0 2006.259.07:43:53.74#ibcon#about to read 4, iclass 26, count 0 2006.259.07:43:53.74#ibcon#read 4, iclass 26, count 0 2006.259.07:43:53.74#ibcon#about to read 5, iclass 26, count 0 2006.259.07:43:53.74#ibcon#read 5, iclass 26, count 0 2006.259.07:43:53.74#ibcon#about to read 6, iclass 26, count 0 2006.259.07:43:53.74#ibcon#read 6, iclass 26, count 0 2006.259.07:43:53.74#ibcon#end of sib2, iclass 26, count 0 2006.259.07:43:53.74#ibcon#*after write, iclass 26, count 0 2006.259.07:43:53.74#ibcon#*before return 0, iclass 26, count 0 2006.259.07:43:53.74#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.259.07:43:53.74#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.259.07:43:53.74#ibcon#about to clear, iclass 26 cls_cnt 0 2006.259.07:43:53.74#ibcon#cleared, iclass 26 cls_cnt 0 2006.259.07:43:53.74$vc4f8/vbbw=wide 2006.259.07:43:53.74#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.259.07:43:53.74#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.259.07:43:53.74#ibcon#ireg 8 cls_cnt 0 2006.259.07:43:53.74#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.259.07:43:53.81#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.259.07:43:53.81#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.259.07:43:53.81#ibcon#enter wrdev, iclass 28, count 0 2006.259.07:43:53.81#ibcon#first serial, iclass 28, count 0 2006.259.07:43:53.81#ibcon#enter sib2, iclass 28, count 0 2006.259.07:43:53.81#ibcon#flushed, iclass 28, count 0 2006.259.07:43:53.81#ibcon#about to write, iclass 28, count 0 2006.259.07:43:53.81#ibcon#wrote, iclass 28, count 0 2006.259.07:43:53.81#ibcon#about to read 3, iclass 28, count 0 2006.259.07:43:53.83#ibcon#read 3, iclass 28, count 0 2006.259.07:43:53.83#ibcon#about to read 4, iclass 28, count 0 2006.259.07:43:53.83#ibcon#read 4, iclass 28, count 0 2006.259.07:43:53.83#ibcon#about to read 5, iclass 28, count 0 2006.259.07:43:53.83#ibcon#read 5, iclass 28, count 0 2006.259.07:43:53.83#ibcon#about to read 6, iclass 28, count 0 2006.259.07:43:53.83#ibcon#read 6, iclass 28, count 0 2006.259.07:43:53.83#ibcon#end of sib2, iclass 28, count 0 2006.259.07:43:53.83#ibcon#*mode == 0, iclass 28, count 0 2006.259.07:43:53.83#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.259.07:43:53.83#ibcon#[27=BW32\r\n] 2006.259.07:43:53.83#ibcon#*before write, iclass 28, count 0 2006.259.07:43:53.83#ibcon#enter sib2, iclass 28, count 0 2006.259.07:43:53.83#ibcon#flushed, iclass 28, count 0 2006.259.07:43:53.83#ibcon#about to write, iclass 28, count 0 2006.259.07:43:53.83#ibcon#wrote, iclass 28, count 0 2006.259.07:43:53.83#ibcon#about to read 3, iclass 28, count 0 2006.259.07:43:53.86#ibcon#read 3, iclass 28, count 0 2006.259.07:43:53.86#ibcon#about to read 4, iclass 28, count 0 2006.259.07:43:53.86#ibcon#read 4, iclass 28, count 0 2006.259.07:43:53.86#ibcon#about to read 5, iclass 28, count 0 2006.259.07:43:53.86#ibcon#read 5, iclass 28, count 0 2006.259.07:43:53.86#ibcon#about to read 6, iclass 28, count 0 2006.259.07:43:53.86#ibcon#read 6, iclass 28, count 0 2006.259.07:43:53.86#ibcon#end of sib2, iclass 28, count 0 2006.259.07:43:53.86#ibcon#*after write, iclass 28, count 0 2006.259.07:43:53.86#ibcon#*before return 0, iclass 28, count 0 2006.259.07:43:53.86#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.259.07:43:53.86#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.259.07:43:53.86#ibcon#about to clear, iclass 28 cls_cnt 0 2006.259.07:43:53.86#ibcon#cleared, iclass 28 cls_cnt 0 2006.259.07:43:53.86$4f8m12a/ifd4f 2006.259.07:43:53.86$ifd4f/lo= 2006.259.07:43:53.86$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.259.07:43:53.86$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.259.07:43:53.86$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.259.07:43:53.86$ifd4f/patch= 2006.259.07:43:53.86$ifd4f/patch=lo1,a1,a2,a3,a4 2006.259.07:43:53.86$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.259.07:43:53.86$ifd4f/patch=lo3,a5,a6,a7,a8 2006.259.07:43:53.86$4f8m12a/"form=m,16.000,1:2 2006.259.07:43:53.86$4f8m12a/"tpicd 2006.259.07:43:53.86$4f8m12a/echo=off 2006.259.07:43:53.86$4f8m12a/xlog=off 2006.259.07:43:53.86:!2006.259.07:44:20 2006.259.07:44:04.14#trakl#Source acquired 2006.259.07:44:05.14#flagr#flagr/antenna,acquired 2006.259.07:44:20.00:preob 2006.259.07:44:21.14/onsource/TRACKING 2006.259.07:44:21.14:!2006.259.07:44:30 2006.259.07:44:30.00:data_valid=on 2006.259.07:44:30.00:midob 2006.259.07:44:30.14/onsource/TRACKING 2006.259.07:44:30.14/wx/22.25,1012.9,85 2006.259.07:44:30.36/cable/+6.4594E-03 2006.259.07:44:31.45/va/01,08,usb,yes,30,32 2006.259.07:44:31.45/va/02,07,usb,yes,30,32 2006.259.07:44:31.45/va/03,08,usb,yes,23,23 2006.259.07:44:31.45/va/04,07,usb,yes,31,34 2006.259.07:44:31.45/va/05,07,usb,yes,35,37 2006.259.07:44:31.45/va/06,06,usb,yes,34,34 2006.259.07:44:31.45/va/07,06,usb,yes,34,34 2006.259.07:44:31.45/va/08,06,usb,yes,37,36 2006.259.07:44:31.68/valo/01,532.99,yes,locked 2006.259.07:44:31.68/valo/02,572.99,yes,locked 2006.259.07:44:31.68/valo/03,672.99,yes,locked 2006.259.07:44:31.68/valo/04,832.99,yes,locked 2006.259.07:44:31.68/valo/05,652.99,yes,locked 2006.259.07:44:31.68/valo/06,772.99,yes,locked 2006.259.07:44:31.68/valo/07,832.99,yes,locked 2006.259.07:44:31.68/valo/08,852.99,yes,locked 2006.259.07:44:32.77/vb/01,04,usb,yes,30,29 2006.259.07:44:32.77/vb/02,05,usb,yes,28,29 2006.259.07:44:32.77/vb/03,04,usb,yes,28,32 2006.259.07:44:32.77/vb/04,05,usb,yes,25,26 2006.259.07:44:32.77/vb/05,04,usb,yes,27,31 2006.259.07:44:32.77/vb/06,04,usb,yes,28,31 2006.259.07:44:32.77/vb/07,04,usb,yes,30,30 2006.259.07:44:32.77/vb/08,04,usb,yes,28,31 2006.259.07:44:33.01/vblo/01,632.99,yes,locked 2006.259.07:44:33.01/vblo/02,640.99,yes,locked 2006.259.07:44:33.01/vblo/03,656.99,yes,locked 2006.259.07:44:33.01/vblo/04,712.99,yes,locked 2006.259.07:44:33.01/vblo/05,744.99,yes,locked 2006.259.07:44:33.01/vblo/06,752.99,yes,locked 2006.259.07:44:33.01/vblo/07,734.99,yes,locked 2006.259.07:44:33.01/vblo/08,744.99,yes,locked 2006.259.07:44:33.16/vabw/8 2006.259.07:44:33.31/vbbw/8 2006.259.07:44:33.40/xfe/off,on,15.2 2006.259.07:44:33.77/ifatt/23,28,28,28 2006.259.07:44:34.08/fmout-gps/S +4.49E-07 2006.259.07:44:34.12:!2006.259.07:45:30 2006.259.07:45:30.00:data_valid=off 2006.259.07:45:30.00:postob 2006.259.07:45:30.13/cable/+6.4587E-03 2006.259.07:45:30.13/wx/22.24,1012.9,85 2006.259.07:45:31.08/fmout-gps/S +4.49E-07 2006.259.07:45:31.08:scan_name=259-0746,k06259,60 2006.259.07:45:31.08:source=1300+580,130252.47,574837.6,2000.0,ccw 2006.259.07:45:31.14#flagr#flagr/antenna,new-source 2006.259.07:45:32.14:checkk5 2006.259.07:45:32.55/chk_autoobs//k5ts1/ autoobs is running! 2006.259.07:45:33.02/chk_autoobs//k5ts2/ autoobs is running! 2006.259.07:45:33.44/chk_autoobs//k5ts3/ autoobs is running! 2006.259.07:45:33.85/chk_autoobs//k5ts4/ autoobs is running! 2006.259.07:45:34.48/chk_obsdata//k5ts1/T2590744??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.259.07:45:34.94/chk_obsdata//k5ts2/T2590744??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.259.07:45:35.35/chk_obsdata//k5ts3/T2590744??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.259.07:45:35.74/chk_obsdata//k5ts4/T2590744??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.259.07:45:36.50/k5log//k5ts1_log_newline 2006.259.07:45:37.29/k5log//k5ts2_log_newline 2006.259.07:45:38.13/k5log//k5ts3_log_newline 2006.259.07:45:38.89/k5log//k5ts4_log_newline 2006.259.07:45:38.91/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.259.07:45:38.91:4f8m12a=1 2006.259.07:45:38.91$4f8m12a/echo=on 2006.259.07:45:38.91$4f8m12a/pcalon 2006.259.07:45:38.91$pcalon/"no phase cal control is implemented here 2006.259.07:45:38.91$4f8m12a/"tpicd=stop 2006.259.07:45:38.91$4f8m12a/vc4f8 2006.259.07:45:38.92$vc4f8/valo=1,532.99 2006.259.07:45:38.92#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.259.07:45:38.92#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.259.07:45:38.92#ibcon#ireg 17 cls_cnt 0 2006.259.07:45:38.92#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.259.07:45:38.92#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.259.07:45:38.92#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.259.07:45:38.92#ibcon#enter wrdev, iclass 35, count 0 2006.259.07:45:38.92#ibcon#first serial, iclass 35, count 0 2006.259.07:45:38.92#ibcon#enter sib2, iclass 35, count 0 2006.259.07:45:38.92#ibcon#flushed, iclass 35, count 0 2006.259.07:45:38.92#ibcon#about to write, iclass 35, count 0 2006.259.07:45:38.92#ibcon#wrote, iclass 35, count 0 2006.259.07:45:38.92#ibcon#about to read 3, iclass 35, count 0 2006.259.07:45:38.96#ibcon#read 3, iclass 35, count 0 2006.259.07:45:38.96#ibcon#about to read 4, iclass 35, count 0 2006.259.07:45:38.96#ibcon#read 4, iclass 35, count 0 2006.259.07:45:38.96#ibcon#about to read 5, iclass 35, count 0 2006.259.07:45:38.96#ibcon#read 5, iclass 35, count 0 2006.259.07:45:38.96#ibcon#about to read 6, iclass 35, count 0 2006.259.07:45:38.96#ibcon#read 6, iclass 35, count 0 2006.259.07:45:38.96#ibcon#end of sib2, iclass 35, count 0 2006.259.07:45:38.96#ibcon#*mode == 0, iclass 35, count 0 2006.259.07:45:38.96#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.259.07:45:38.96#ibcon#[26=FRQ=01,532.99\r\n] 2006.259.07:45:38.96#ibcon#*before write, iclass 35, count 0 2006.259.07:45:38.96#ibcon#enter sib2, iclass 35, count 0 2006.259.07:45:38.96#ibcon#flushed, iclass 35, count 0 2006.259.07:45:38.96#ibcon#about to write, iclass 35, count 0 2006.259.07:45:38.96#ibcon#wrote, iclass 35, count 0 2006.259.07:45:38.96#ibcon#about to read 3, iclass 35, count 0 2006.259.07:45:39.01#ibcon#read 3, iclass 35, count 0 2006.259.07:45:39.01#ibcon#about to read 4, iclass 35, count 0 2006.259.07:45:39.01#ibcon#read 4, iclass 35, count 0 2006.259.07:45:39.01#ibcon#about to read 5, iclass 35, count 0 2006.259.07:45:39.01#ibcon#read 5, iclass 35, count 0 2006.259.07:45:39.01#ibcon#about to read 6, iclass 35, count 0 2006.259.07:45:39.01#ibcon#read 6, iclass 35, count 0 2006.259.07:45:39.01#ibcon#end of sib2, iclass 35, count 0 2006.259.07:45:39.01#ibcon#*after write, iclass 35, count 0 2006.259.07:45:39.01#ibcon#*before return 0, iclass 35, count 0 2006.259.07:45:39.01#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.259.07:45:39.01#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.259.07:45:39.01#ibcon#about to clear, iclass 35 cls_cnt 0 2006.259.07:45:39.01#ibcon#cleared, iclass 35 cls_cnt 0 2006.259.07:45:39.01$vc4f8/va=1,8 2006.259.07:45:39.01#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.259.07:45:39.01#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.259.07:45:39.01#ibcon#ireg 11 cls_cnt 2 2006.259.07:45:39.01#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.259.07:45:39.01#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.259.07:45:39.01#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.259.07:45:39.01#ibcon#enter wrdev, iclass 37, count 2 2006.259.07:45:39.01#ibcon#first serial, iclass 37, count 2 2006.259.07:45:39.01#ibcon#enter sib2, iclass 37, count 2 2006.259.07:45:39.01#ibcon#flushed, iclass 37, count 2 2006.259.07:45:39.01#ibcon#about to write, iclass 37, count 2 2006.259.07:45:39.01#ibcon#wrote, iclass 37, count 2 2006.259.07:45:39.01#ibcon#about to read 3, iclass 37, count 2 2006.259.07:45:39.03#ibcon#read 3, iclass 37, count 2 2006.259.07:45:39.03#ibcon#about to read 4, iclass 37, count 2 2006.259.07:45:39.03#ibcon#read 4, iclass 37, count 2 2006.259.07:45:39.03#ibcon#about to read 5, iclass 37, count 2 2006.259.07:45:39.03#ibcon#read 5, iclass 37, count 2 2006.259.07:45:39.03#ibcon#about to read 6, iclass 37, count 2 2006.259.07:45:39.03#ibcon#read 6, iclass 37, count 2 2006.259.07:45:39.03#ibcon#end of sib2, iclass 37, count 2 2006.259.07:45:39.03#ibcon#*mode == 0, iclass 37, count 2 2006.259.07:45:39.03#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.259.07:45:39.03#ibcon#[25=AT01-08\r\n] 2006.259.07:45:39.03#ibcon#*before write, iclass 37, count 2 2006.259.07:45:39.03#ibcon#enter sib2, iclass 37, count 2 2006.259.07:45:39.03#ibcon#flushed, iclass 37, count 2 2006.259.07:45:39.03#ibcon#about to write, iclass 37, count 2 2006.259.07:45:39.03#ibcon#wrote, iclass 37, count 2 2006.259.07:45:39.03#ibcon#about to read 3, iclass 37, count 2 2006.259.07:45:39.06#ibcon#read 3, iclass 37, count 2 2006.259.07:45:39.06#ibcon#about to read 4, iclass 37, count 2 2006.259.07:45:39.06#ibcon#read 4, iclass 37, count 2 2006.259.07:45:39.06#ibcon#about to read 5, iclass 37, count 2 2006.259.07:45:39.06#ibcon#read 5, iclass 37, count 2 2006.259.07:45:39.06#ibcon#about to read 6, iclass 37, count 2 2006.259.07:45:39.06#ibcon#read 6, iclass 37, count 2 2006.259.07:45:39.06#ibcon#end of sib2, iclass 37, count 2 2006.259.07:45:39.06#ibcon#*after write, iclass 37, count 2 2006.259.07:45:39.06#ibcon#*before return 0, iclass 37, count 2 2006.259.07:45:39.06#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.259.07:45:39.06#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.259.07:45:39.06#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.259.07:45:39.06#ibcon#ireg 7 cls_cnt 0 2006.259.07:45:39.06#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.259.07:45:39.18#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.259.07:45:39.18#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.259.07:45:39.18#ibcon#enter wrdev, iclass 37, count 0 2006.259.07:45:39.18#ibcon#first serial, iclass 37, count 0 2006.259.07:45:39.18#ibcon#enter sib2, iclass 37, count 0 2006.259.07:45:39.18#ibcon#flushed, iclass 37, count 0 2006.259.07:45:39.18#ibcon#about to write, iclass 37, count 0 2006.259.07:45:39.18#ibcon#wrote, iclass 37, count 0 2006.259.07:45:39.18#ibcon#about to read 3, iclass 37, count 0 2006.259.07:45:39.20#ibcon#read 3, iclass 37, count 0 2006.259.07:45:39.20#ibcon#about to read 4, iclass 37, count 0 2006.259.07:45:39.20#ibcon#read 4, iclass 37, count 0 2006.259.07:45:39.20#ibcon#about to read 5, iclass 37, count 0 2006.259.07:45:39.20#ibcon#read 5, iclass 37, count 0 2006.259.07:45:39.20#ibcon#about to read 6, iclass 37, count 0 2006.259.07:45:39.20#ibcon#read 6, iclass 37, count 0 2006.259.07:45:39.20#ibcon#end of sib2, iclass 37, count 0 2006.259.07:45:39.20#ibcon#*mode == 0, iclass 37, count 0 2006.259.07:45:39.20#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.259.07:45:39.20#ibcon#[25=USB\r\n] 2006.259.07:45:39.20#ibcon#*before write, iclass 37, count 0 2006.259.07:45:39.20#ibcon#enter sib2, iclass 37, count 0 2006.259.07:45:39.20#ibcon#flushed, iclass 37, count 0 2006.259.07:45:39.20#ibcon#about to write, iclass 37, count 0 2006.259.07:45:39.20#ibcon#wrote, iclass 37, count 0 2006.259.07:45:39.20#ibcon#about to read 3, iclass 37, count 0 2006.259.07:45:39.23#ibcon#read 3, iclass 37, count 0 2006.259.07:45:39.23#ibcon#about to read 4, iclass 37, count 0 2006.259.07:45:39.23#ibcon#read 4, iclass 37, count 0 2006.259.07:45:39.23#ibcon#about to read 5, iclass 37, count 0 2006.259.07:45:39.23#ibcon#read 5, iclass 37, count 0 2006.259.07:45:39.23#ibcon#about to read 6, iclass 37, count 0 2006.259.07:45:39.23#ibcon#read 6, iclass 37, count 0 2006.259.07:45:39.23#ibcon#end of sib2, iclass 37, count 0 2006.259.07:45:39.23#ibcon#*after write, iclass 37, count 0 2006.259.07:45:39.23#ibcon#*before return 0, iclass 37, count 0 2006.259.07:45:39.23#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.259.07:45:39.23#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.259.07:45:39.23#ibcon#about to clear, iclass 37 cls_cnt 0 2006.259.07:45:39.23#ibcon#cleared, iclass 37 cls_cnt 0 2006.259.07:45:39.23$vc4f8/valo=2,572.99 2006.259.07:45:39.23#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.259.07:45:39.23#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.259.07:45:39.23#ibcon#ireg 17 cls_cnt 0 2006.259.07:45:39.23#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.259.07:45:39.23#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.259.07:45:39.23#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.259.07:45:39.23#ibcon#enter wrdev, iclass 39, count 0 2006.259.07:45:39.23#ibcon#first serial, iclass 39, count 0 2006.259.07:45:39.23#ibcon#enter sib2, iclass 39, count 0 2006.259.07:45:39.23#ibcon#flushed, iclass 39, count 0 2006.259.07:45:39.23#ibcon#about to write, iclass 39, count 0 2006.259.07:45:39.23#ibcon#wrote, iclass 39, count 0 2006.259.07:45:39.23#ibcon#about to read 3, iclass 39, count 0 2006.259.07:45:39.25#ibcon#read 3, iclass 39, count 0 2006.259.07:45:39.25#ibcon#about to read 4, iclass 39, count 0 2006.259.07:45:39.25#ibcon#read 4, iclass 39, count 0 2006.259.07:45:39.25#ibcon#about to read 5, iclass 39, count 0 2006.259.07:45:39.25#ibcon#read 5, iclass 39, count 0 2006.259.07:45:39.25#ibcon#about to read 6, iclass 39, count 0 2006.259.07:45:39.25#ibcon#read 6, iclass 39, count 0 2006.259.07:45:39.25#ibcon#end of sib2, iclass 39, count 0 2006.259.07:45:39.25#ibcon#*mode == 0, iclass 39, count 0 2006.259.07:45:39.25#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.259.07:45:39.25#ibcon#[26=FRQ=02,572.99\r\n] 2006.259.07:45:39.25#ibcon#*before write, iclass 39, count 0 2006.259.07:45:39.25#ibcon#enter sib2, iclass 39, count 0 2006.259.07:45:39.25#ibcon#flushed, iclass 39, count 0 2006.259.07:45:39.25#ibcon#about to write, iclass 39, count 0 2006.259.07:45:39.25#ibcon#wrote, iclass 39, count 0 2006.259.07:45:39.25#ibcon#about to read 3, iclass 39, count 0 2006.259.07:45:39.29#ibcon#read 3, iclass 39, count 0 2006.259.07:45:39.29#ibcon#about to read 4, iclass 39, count 0 2006.259.07:45:39.29#ibcon#read 4, iclass 39, count 0 2006.259.07:45:39.29#ibcon#about to read 5, iclass 39, count 0 2006.259.07:45:39.29#ibcon#read 5, iclass 39, count 0 2006.259.07:45:39.29#ibcon#about to read 6, iclass 39, count 0 2006.259.07:45:39.29#ibcon#read 6, iclass 39, count 0 2006.259.07:45:39.29#ibcon#end of sib2, iclass 39, count 0 2006.259.07:45:39.29#ibcon#*after write, iclass 39, count 0 2006.259.07:45:39.29#ibcon#*before return 0, iclass 39, count 0 2006.259.07:45:39.29#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.259.07:45:39.29#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.259.07:45:39.29#ibcon#about to clear, iclass 39 cls_cnt 0 2006.259.07:45:39.29#ibcon#cleared, iclass 39 cls_cnt 0 2006.259.07:45:39.29$vc4f8/va=2,7 2006.259.07:45:39.29#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.259.07:45:39.29#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.259.07:45:39.29#ibcon#ireg 11 cls_cnt 2 2006.259.07:45:39.29#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.259.07:45:39.35#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.259.07:45:39.35#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.259.07:45:39.35#ibcon#enter wrdev, iclass 3, count 2 2006.259.07:45:39.35#ibcon#first serial, iclass 3, count 2 2006.259.07:45:39.35#ibcon#enter sib2, iclass 3, count 2 2006.259.07:45:39.35#ibcon#flushed, iclass 3, count 2 2006.259.07:45:39.35#ibcon#about to write, iclass 3, count 2 2006.259.07:45:39.35#ibcon#wrote, iclass 3, count 2 2006.259.07:45:39.35#ibcon#about to read 3, iclass 3, count 2 2006.259.07:45:39.37#ibcon#read 3, iclass 3, count 2 2006.259.07:45:39.37#ibcon#about to read 4, iclass 3, count 2 2006.259.07:45:39.37#ibcon#read 4, iclass 3, count 2 2006.259.07:45:39.37#ibcon#about to read 5, iclass 3, count 2 2006.259.07:45:39.37#ibcon#read 5, iclass 3, count 2 2006.259.07:45:39.37#ibcon#about to read 6, iclass 3, count 2 2006.259.07:45:39.37#ibcon#read 6, iclass 3, count 2 2006.259.07:45:39.37#ibcon#end of sib2, iclass 3, count 2 2006.259.07:45:39.37#ibcon#*mode == 0, iclass 3, count 2 2006.259.07:45:39.37#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.259.07:45:39.37#ibcon#[25=AT02-07\r\n] 2006.259.07:45:39.37#ibcon#*before write, iclass 3, count 2 2006.259.07:45:39.37#ibcon#enter sib2, iclass 3, count 2 2006.259.07:45:39.37#ibcon#flushed, iclass 3, count 2 2006.259.07:45:39.37#ibcon#about to write, iclass 3, count 2 2006.259.07:45:39.37#ibcon#wrote, iclass 3, count 2 2006.259.07:45:39.37#ibcon#about to read 3, iclass 3, count 2 2006.259.07:45:39.40#ibcon#read 3, iclass 3, count 2 2006.259.07:45:39.40#ibcon#about to read 4, iclass 3, count 2 2006.259.07:45:39.40#ibcon#read 4, iclass 3, count 2 2006.259.07:45:39.40#ibcon#about to read 5, iclass 3, count 2 2006.259.07:45:39.40#ibcon#read 5, iclass 3, count 2 2006.259.07:45:39.40#ibcon#about to read 6, iclass 3, count 2 2006.259.07:45:39.40#ibcon#read 6, iclass 3, count 2 2006.259.07:45:39.40#ibcon#end of sib2, iclass 3, count 2 2006.259.07:45:39.40#ibcon#*after write, iclass 3, count 2 2006.259.07:45:39.40#ibcon#*before return 0, iclass 3, count 2 2006.259.07:45:39.40#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.259.07:45:39.40#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.259.07:45:39.40#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.259.07:45:39.40#ibcon#ireg 7 cls_cnt 0 2006.259.07:45:39.40#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.259.07:45:39.52#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.259.07:45:39.52#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.259.07:45:39.52#ibcon#enter wrdev, iclass 3, count 0 2006.259.07:45:39.52#ibcon#first serial, iclass 3, count 0 2006.259.07:45:39.52#ibcon#enter sib2, iclass 3, count 0 2006.259.07:45:39.52#ibcon#flushed, iclass 3, count 0 2006.259.07:45:39.52#ibcon#about to write, iclass 3, count 0 2006.259.07:45:39.52#ibcon#wrote, iclass 3, count 0 2006.259.07:45:39.52#ibcon#about to read 3, iclass 3, count 0 2006.259.07:45:39.54#ibcon#read 3, iclass 3, count 0 2006.259.07:45:39.54#ibcon#about to read 4, iclass 3, count 0 2006.259.07:45:39.54#ibcon#read 4, iclass 3, count 0 2006.259.07:45:39.54#ibcon#about to read 5, iclass 3, count 0 2006.259.07:45:39.54#ibcon#read 5, iclass 3, count 0 2006.259.07:45:39.54#ibcon#about to read 6, iclass 3, count 0 2006.259.07:45:39.54#ibcon#read 6, iclass 3, count 0 2006.259.07:45:39.54#ibcon#end of sib2, iclass 3, count 0 2006.259.07:45:39.54#ibcon#*mode == 0, iclass 3, count 0 2006.259.07:45:39.54#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.259.07:45:39.54#ibcon#[25=USB\r\n] 2006.259.07:45:39.54#ibcon#*before write, iclass 3, count 0 2006.259.07:45:39.54#ibcon#enter sib2, iclass 3, count 0 2006.259.07:45:39.54#ibcon#flushed, iclass 3, count 0 2006.259.07:45:39.54#ibcon#about to write, iclass 3, count 0 2006.259.07:45:39.54#ibcon#wrote, iclass 3, count 0 2006.259.07:45:39.54#ibcon#about to read 3, iclass 3, count 0 2006.259.07:45:39.57#ibcon#read 3, iclass 3, count 0 2006.259.07:45:39.57#ibcon#about to read 4, iclass 3, count 0 2006.259.07:45:39.57#ibcon#read 4, iclass 3, count 0 2006.259.07:45:39.57#ibcon#about to read 5, iclass 3, count 0 2006.259.07:45:39.57#ibcon#read 5, iclass 3, count 0 2006.259.07:45:39.57#ibcon#about to read 6, iclass 3, count 0 2006.259.07:45:39.57#ibcon#read 6, iclass 3, count 0 2006.259.07:45:39.57#ibcon#end of sib2, iclass 3, count 0 2006.259.07:45:39.57#ibcon#*after write, iclass 3, count 0 2006.259.07:45:39.57#ibcon#*before return 0, iclass 3, count 0 2006.259.07:45:39.57#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.259.07:45:39.57#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.259.07:45:39.57#ibcon#about to clear, iclass 3 cls_cnt 0 2006.259.07:45:39.57#ibcon#cleared, iclass 3 cls_cnt 0 2006.259.07:45:39.57$vc4f8/valo=3,672.99 2006.259.07:45:39.57#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.259.07:45:39.57#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.259.07:45:39.57#ibcon#ireg 17 cls_cnt 0 2006.259.07:45:39.57#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.259.07:45:39.57#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.259.07:45:39.57#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.259.07:45:39.57#ibcon#enter wrdev, iclass 5, count 0 2006.259.07:45:39.57#ibcon#first serial, iclass 5, count 0 2006.259.07:45:39.57#ibcon#enter sib2, iclass 5, count 0 2006.259.07:45:39.57#ibcon#flushed, iclass 5, count 0 2006.259.07:45:39.57#ibcon#about to write, iclass 5, count 0 2006.259.07:45:39.57#ibcon#wrote, iclass 5, count 0 2006.259.07:45:39.57#ibcon#about to read 3, iclass 5, count 0 2006.259.07:45:39.59#ibcon#read 3, iclass 5, count 0 2006.259.07:45:39.59#ibcon#about to read 4, iclass 5, count 0 2006.259.07:45:39.59#ibcon#read 4, iclass 5, count 0 2006.259.07:45:39.59#ibcon#about to read 5, iclass 5, count 0 2006.259.07:45:39.59#ibcon#read 5, iclass 5, count 0 2006.259.07:45:39.59#ibcon#about to read 6, iclass 5, count 0 2006.259.07:45:39.59#ibcon#read 6, iclass 5, count 0 2006.259.07:45:39.59#ibcon#end of sib2, iclass 5, count 0 2006.259.07:45:39.59#ibcon#*mode == 0, iclass 5, count 0 2006.259.07:45:39.59#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.259.07:45:39.59#ibcon#[26=FRQ=03,672.99\r\n] 2006.259.07:45:39.59#ibcon#*before write, iclass 5, count 0 2006.259.07:45:39.59#ibcon#enter sib2, iclass 5, count 0 2006.259.07:45:39.59#ibcon#flushed, iclass 5, count 0 2006.259.07:45:39.59#ibcon#about to write, iclass 5, count 0 2006.259.07:45:39.59#ibcon#wrote, iclass 5, count 0 2006.259.07:45:39.59#ibcon#about to read 3, iclass 5, count 0 2006.259.07:45:39.63#ibcon#read 3, iclass 5, count 0 2006.259.07:45:39.63#ibcon#about to read 4, iclass 5, count 0 2006.259.07:45:39.63#ibcon#read 4, iclass 5, count 0 2006.259.07:45:39.63#ibcon#about to read 5, iclass 5, count 0 2006.259.07:45:39.63#ibcon#read 5, iclass 5, count 0 2006.259.07:45:39.63#ibcon#about to read 6, iclass 5, count 0 2006.259.07:45:39.63#ibcon#read 6, iclass 5, count 0 2006.259.07:45:39.63#ibcon#end of sib2, iclass 5, count 0 2006.259.07:45:39.63#ibcon#*after write, iclass 5, count 0 2006.259.07:45:39.63#ibcon#*before return 0, iclass 5, count 0 2006.259.07:45:39.63#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.259.07:45:39.63#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.259.07:45:39.63#ibcon#about to clear, iclass 5 cls_cnt 0 2006.259.07:45:39.63#ibcon#cleared, iclass 5 cls_cnt 0 2006.259.07:45:39.63$vc4f8/va=3,8 2006.259.07:45:39.63#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.259.07:45:39.63#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.259.07:45:39.63#ibcon#ireg 11 cls_cnt 2 2006.259.07:45:39.63#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.259.07:45:39.69#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.259.07:45:39.69#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.259.07:45:39.69#ibcon#enter wrdev, iclass 7, count 2 2006.259.07:45:39.69#ibcon#first serial, iclass 7, count 2 2006.259.07:45:39.69#ibcon#enter sib2, iclass 7, count 2 2006.259.07:45:39.69#ibcon#flushed, iclass 7, count 2 2006.259.07:45:39.69#ibcon#about to write, iclass 7, count 2 2006.259.07:45:39.69#ibcon#wrote, iclass 7, count 2 2006.259.07:45:39.69#ibcon#about to read 3, iclass 7, count 2 2006.259.07:45:39.71#ibcon#read 3, iclass 7, count 2 2006.259.07:45:39.71#ibcon#about to read 4, iclass 7, count 2 2006.259.07:45:39.71#ibcon#read 4, iclass 7, count 2 2006.259.07:45:39.71#ibcon#about to read 5, iclass 7, count 2 2006.259.07:45:39.71#ibcon#read 5, iclass 7, count 2 2006.259.07:45:39.71#ibcon#about to read 6, iclass 7, count 2 2006.259.07:45:39.71#ibcon#read 6, iclass 7, count 2 2006.259.07:45:39.71#ibcon#end of sib2, iclass 7, count 2 2006.259.07:45:39.71#ibcon#*mode == 0, iclass 7, count 2 2006.259.07:45:39.71#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.259.07:45:39.71#ibcon#[25=AT03-08\r\n] 2006.259.07:45:39.71#ibcon#*before write, iclass 7, count 2 2006.259.07:45:39.71#ibcon#enter sib2, iclass 7, count 2 2006.259.07:45:39.71#ibcon#flushed, iclass 7, count 2 2006.259.07:45:39.71#ibcon#about to write, iclass 7, count 2 2006.259.07:45:39.71#ibcon#wrote, iclass 7, count 2 2006.259.07:45:39.71#ibcon#about to read 3, iclass 7, count 2 2006.259.07:45:39.75#ibcon#read 3, iclass 7, count 2 2006.259.07:45:39.75#ibcon#about to read 4, iclass 7, count 2 2006.259.07:45:39.75#ibcon#read 4, iclass 7, count 2 2006.259.07:45:39.75#ibcon#about to read 5, iclass 7, count 2 2006.259.07:45:39.75#ibcon#read 5, iclass 7, count 2 2006.259.07:45:39.75#ibcon#about to read 6, iclass 7, count 2 2006.259.07:45:39.75#ibcon#read 6, iclass 7, count 2 2006.259.07:45:39.75#ibcon#end of sib2, iclass 7, count 2 2006.259.07:45:39.75#ibcon#*after write, iclass 7, count 2 2006.259.07:45:39.75#ibcon#*before return 0, iclass 7, count 2 2006.259.07:45:39.75#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.259.07:45:39.75#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.259.07:45:39.75#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.259.07:45:39.75#ibcon#ireg 7 cls_cnt 0 2006.259.07:45:39.75#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.259.07:45:39.87#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.259.07:45:39.87#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.259.07:45:39.87#ibcon#enter wrdev, iclass 7, count 0 2006.259.07:45:39.87#ibcon#first serial, iclass 7, count 0 2006.259.07:45:39.87#ibcon#enter sib2, iclass 7, count 0 2006.259.07:45:39.87#ibcon#flushed, iclass 7, count 0 2006.259.07:45:39.87#ibcon#about to write, iclass 7, count 0 2006.259.07:45:39.87#ibcon#wrote, iclass 7, count 0 2006.259.07:45:39.87#ibcon#about to read 3, iclass 7, count 0 2006.259.07:45:39.89#ibcon#read 3, iclass 7, count 0 2006.259.07:45:39.89#ibcon#about to read 4, iclass 7, count 0 2006.259.07:45:39.89#ibcon#read 4, iclass 7, count 0 2006.259.07:45:39.89#ibcon#about to read 5, iclass 7, count 0 2006.259.07:45:39.89#ibcon#read 5, iclass 7, count 0 2006.259.07:45:39.89#ibcon#about to read 6, iclass 7, count 0 2006.259.07:45:39.89#ibcon#read 6, iclass 7, count 0 2006.259.07:45:39.89#ibcon#end of sib2, iclass 7, count 0 2006.259.07:45:39.89#ibcon#*mode == 0, iclass 7, count 0 2006.259.07:45:39.89#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.259.07:45:39.89#ibcon#[25=USB\r\n] 2006.259.07:45:39.89#ibcon#*before write, iclass 7, count 0 2006.259.07:45:39.89#ibcon#enter sib2, iclass 7, count 0 2006.259.07:45:39.89#ibcon#flushed, iclass 7, count 0 2006.259.07:45:39.89#ibcon#about to write, iclass 7, count 0 2006.259.07:45:39.89#ibcon#wrote, iclass 7, count 0 2006.259.07:45:39.89#ibcon#about to read 3, iclass 7, count 0 2006.259.07:45:39.92#ibcon#read 3, iclass 7, count 0 2006.259.07:45:39.92#ibcon#about to read 4, iclass 7, count 0 2006.259.07:45:39.92#ibcon#read 4, iclass 7, count 0 2006.259.07:45:39.92#ibcon#about to read 5, iclass 7, count 0 2006.259.07:45:39.92#ibcon#read 5, iclass 7, count 0 2006.259.07:45:39.92#ibcon#about to read 6, iclass 7, count 0 2006.259.07:45:39.92#ibcon#read 6, iclass 7, count 0 2006.259.07:45:39.92#ibcon#end of sib2, iclass 7, count 0 2006.259.07:45:39.92#ibcon#*after write, iclass 7, count 0 2006.259.07:45:39.92#ibcon#*before return 0, iclass 7, count 0 2006.259.07:45:39.92#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.259.07:45:39.92#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.259.07:45:39.92#ibcon#about to clear, iclass 7 cls_cnt 0 2006.259.07:45:39.92#ibcon#cleared, iclass 7 cls_cnt 0 2006.259.07:45:39.92$vc4f8/valo=4,832.99 2006.259.07:45:39.92#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.259.07:45:39.92#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.259.07:45:39.92#ibcon#ireg 17 cls_cnt 0 2006.259.07:45:39.92#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.259.07:45:39.92#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.259.07:45:39.92#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.259.07:45:39.92#ibcon#enter wrdev, iclass 11, count 0 2006.259.07:45:39.92#ibcon#first serial, iclass 11, count 0 2006.259.07:45:39.92#ibcon#enter sib2, iclass 11, count 0 2006.259.07:45:39.92#ibcon#flushed, iclass 11, count 0 2006.259.07:45:39.92#ibcon#about to write, iclass 11, count 0 2006.259.07:45:39.92#ibcon#wrote, iclass 11, count 0 2006.259.07:45:39.92#ibcon#about to read 3, iclass 11, count 0 2006.259.07:45:39.94#ibcon#read 3, iclass 11, count 0 2006.259.07:45:39.94#ibcon#about to read 4, iclass 11, count 0 2006.259.07:45:39.94#ibcon#read 4, iclass 11, count 0 2006.259.07:45:39.94#ibcon#about to read 5, iclass 11, count 0 2006.259.07:45:39.94#ibcon#read 5, iclass 11, count 0 2006.259.07:45:39.94#ibcon#about to read 6, iclass 11, count 0 2006.259.07:45:39.94#ibcon#read 6, iclass 11, count 0 2006.259.07:45:39.94#ibcon#end of sib2, iclass 11, count 0 2006.259.07:45:39.94#ibcon#*mode == 0, iclass 11, count 0 2006.259.07:45:39.94#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.259.07:45:39.94#ibcon#[26=FRQ=04,832.99\r\n] 2006.259.07:45:39.94#ibcon#*before write, iclass 11, count 0 2006.259.07:45:39.94#ibcon#enter sib2, iclass 11, count 0 2006.259.07:45:39.94#ibcon#flushed, iclass 11, count 0 2006.259.07:45:39.94#ibcon#about to write, iclass 11, count 0 2006.259.07:45:39.94#ibcon#wrote, iclass 11, count 0 2006.259.07:45:39.94#ibcon#about to read 3, iclass 11, count 0 2006.259.07:45:39.98#ibcon#read 3, iclass 11, count 0 2006.259.07:45:39.98#ibcon#about to read 4, iclass 11, count 0 2006.259.07:45:39.98#ibcon#read 4, iclass 11, count 0 2006.259.07:45:39.98#ibcon#about to read 5, iclass 11, count 0 2006.259.07:45:39.98#ibcon#read 5, iclass 11, count 0 2006.259.07:45:39.98#ibcon#about to read 6, iclass 11, count 0 2006.259.07:45:39.98#ibcon#read 6, iclass 11, count 0 2006.259.07:45:39.98#ibcon#end of sib2, iclass 11, count 0 2006.259.07:45:39.98#ibcon#*after write, iclass 11, count 0 2006.259.07:45:39.98#ibcon#*before return 0, iclass 11, count 0 2006.259.07:45:39.98#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.259.07:45:39.98#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.259.07:45:39.98#ibcon#about to clear, iclass 11 cls_cnt 0 2006.259.07:45:39.98#ibcon#cleared, iclass 11 cls_cnt 0 2006.259.07:45:39.98$vc4f8/va=4,7 2006.259.07:45:39.98#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.259.07:45:39.98#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.259.07:45:39.98#ibcon#ireg 11 cls_cnt 2 2006.259.07:45:39.98#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.259.07:45:40.04#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.259.07:45:40.04#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.259.07:45:40.04#ibcon#enter wrdev, iclass 13, count 2 2006.259.07:45:40.04#ibcon#first serial, iclass 13, count 2 2006.259.07:45:40.04#ibcon#enter sib2, iclass 13, count 2 2006.259.07:45:40.04#ibcon#flushed, iclass 13, count 2 2006.259.07:45:40.04#ibcon#about to write, iclass 13, count 2 2006.259.07:45:40.04#ibcon#wrote, iclass 13, count 2 2006.259.07:45:40.04#ibcon#about to read 3, iclass 13, count 2 2006.259.07:45:40.06#ibcon#read 3, iclass 13, count 2 2006.259.07:45:40.06#ibcon#about to read 4, iclass 13, count 2 2006.259.07:45:40.06#ibcon#read 4, iclass 13, count 2 2006.259.07:45:40.06#ibcon#about to read 5, iclass 13, count 2 2006.259.07:45:40.06#ibcon#read 5, iclass 13, count 2 2006.259.07:45:40.06#ibcon#about to read 6, iclass 13, count 2 2006.259.07:45:40.06#ibcon#read 6, iclass 13, count 2 2006.259.07:45:40.06#ibcon#end of sib2, iclass 13, count 2 2006.259.07:45:40.06#ibcon#*mode == 0, iclass 13, count 2 2006.259.07:45:40.06#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.259.07:45:40.06#ibcon#[25=AT04-07\r\n] 2006.259.07:45:40.06#ibcon#*before write, iclass 13, count 2 2006.259.07:45:40.06#ibcon#enter sib2, iclass 13, count 2 2006.259.07:45:40.06#ibcon#flushed, iclass 13, count 2 2006.259.07:45:40.06#ibcon#about to write, iclass 13, count 2 2006.259.07:45:40.06#ibcon#wrote, iclass 13, count 2 2006.259.07:45:40.06#ibcon#about to read 3, iclass 13, count 2 2006.259.07:45:40.09#ibcon#read 3, iclass 13, count 2 2006.259.07:45:40.09#ibcon#about to read 4, iclass 13, count 2 2006.259.07:45:40.09#ibcon#read 4, iclass 13, count 2 2006.259.07:45:40.09#ibcon#about to read 5, iclass 13, count 2 2006.259.07:45:40.09#ibcon#read 5, iclass 13, count 2 2006.259.07:45:40.09#ibcon#about to read 6, iclass 13, count 2 2006.259.07:45:40.09#ibcon#read 6, iclass 13, count 2 2006.259.07:45:40.09#ibcon#end of sib2, iclass 13, count 2 2006.259.07:45:40.09#ibcon#*after write, iclass 13, count 2 2006.259.07:45:40.09#ibcon#*before return 0, iclass 13, count 2 2006.259.07:45:40.09#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.259.07:45:40.09#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.259.07:45:40.09#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.259.07:45:40.09#ibcon#ireg 7 cls_cnt 0 2006.259.07:45:40.09#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.259.07:45:40.21#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.259.07:45:40.21#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.259.07:45:40.21#ibcon#enter wrdev, iclass 13, count 0 2006.259.07:45:40.21#ibcon#first serial, iclass 13, count 0 2006.259.07:45:40.21#ibcon#enter sib2, iclass 13, count 0 2006.259.07:45:40.21#ibcon#flushed, iclass 13, count 0 2006.259.07:45:40.21#ibcon#about to write, iclass 13, count 0 2006.259.07:45:40.21#ibcon#wrote, iclass 13, count 0 2006.259.07:45:40.21#ibcon#about to read 3, iclass 13, count 0 2006.259.07:45:40.23#ibcon#read 3, iclass 13, count 0 2006.259.07:45:40.23#ibcon#about to read 4, iclass 13, count 0 2006.259.07:45:40.23#ibcon#read 4, iclass 13, count 0 2006.259.07:45:40.23#ibcon#about to read 5, iclass 13, count 0 2006.259.07:45:40.23#ibcon#read 5, iclass 13, count 0 2006.259.07:45:40.23#ibcon#about to read 6, iclass 13, count 0 2006.259.07:45:40.23#ibcon#read 6, iclass 13, count 0 2006.259.07:45:40.23#ibcon#end of sib2, iclass 13, count 0 2006.259.07:45:40.23#ibcon#*mode == 0, iclass 13, count 0 2006.259.07:45:40.23#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.259.07:45:40.23#ibcon#[25=USB\r\n] 2006.259.07:45:40.23#ibcon#*before write, iclass 13, count 0 2006.259.07:45:40.23#ibcon#enter sib2, iclass 13, count 0 2006.259.07:45:40.23#ibcon#flushed, iclass 13, count 0 2006.259.07:45:40.23#ibcon#about to write, iclass 13, count 0 2006.259.07:45:40.23#ibcon#wrote, iclass 13, count 0 2006.259.07:45:40.23#ibcon#about to read 3, iclass 13, count 0 2006.259.07:45:40.26#ibcon#read 3, iclass 13, count 0 2006.259.07:45:40.26#ibcon#about to read 4, iclass 13, count 0 2006.259.07:45:40.26#ibcon#read 4, iclass 13, count 0 2006.259.07:45:40.26#ibcon#about to read 5, iclass 13, count 0 2006.259.07:45:40.26#ibcon#read 5, iclass 13, count 0 2006.259.07:45:40.26#ibcon#about to read 6, iclass 13, count 0 2006.259.07:45:40.26#ibcon#read 6, iclass 13, count 0 2006.259.07:45:40.26#ibcon#end of sib2, iclass 13, count 0 2006.259.07:45:40.26#ibcon#*after write, iclass 13, count 0 2006.259.07:45:40.26#ibcon#*before return 0, iclass 13, count 0 2006.259.07:45:40.26#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.259.07:45:40.26#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.259.07:45:40.26#ibcon#about to clear, iclass 13 cls_cnt 0 2006.259.07:45:40.26#ibcon#cleared, iclass 13 cls_cnt 0 2006.259.07:45:40.26$vc4f8/valo=5,652.99 2006.259.07:45:40.26#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.259.07:45:40.26#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.259.07:45:40.26#ibcon#ireg 17 cls_cnt 0 2006.259.07:45:40.26#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.259.07:45:40.26#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.259.07:45:40.26#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.259.07:45:40.26#ibcon#enter wrdev, iclass 15, count 0 2006.259.07:45:40.26#ibcon#first serial, iclass 15, count 0 2006.259.07:45:40.26#ibcon#enter sib2, iclass 15, count 0 2006.259.07:45:40.26#ibcon#flushed, iclass 15, count 0 2006.259.07:45:40.26#ibcon#about to write, iclass 15, count 0 2006.259.07:45:40.26#ibcon#wrote, iclass 15, count 0 2006.259.07:45:40.26#ibcon#about to read 3, iclass 15, count 0 2006.259.07:45:40.28#ibcon#read 3, iclass 15, count 0 2006.259.07:45:40.28#ibcon#about to read 4, iclass 15, count 0 2006.259.07:45:40.28#ibcon#read 4, iclass 15, count 0 2006.259.07:45:40.28#ibcon#about to read 5, iclass 15, count 0 2006.259.07:45:40.28#ibcon#read 5, iclass 15, count 0 2006.259.07:45:40.28#ibcon#about to read 6, iclass 15, count 0 2006.259.07:45:40.28#ibcon#read 6, iclass 15, count 0 2006.259.07:45:40.28#ibcon#end of sib2, iclass 15, count 0 2006.259.07:45:40.28#ibcon#*mode == 0, iclass 15, count 0 2006.259.07:45:40.28#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.259.07:45:40.28#ibcon#[26=FRQ=05,652.99\r\n] 2006.259.07:45:40.28#ibcon#*before write, iclass 15, count 0 2006.259.07:45:40.28#ibcon#enter sib2, iclass 15, count 0 2006.259.07:45:40.28#ibcon#flushed, iclass 15, count 0 2006.259.07:45:40.28#ibcon#about to write, iclass 15, count 0 2006.259.07:45:40.28#ibcon#wrote, iclass 15, count 0 2006.259.07:45:40.28#ibcon#about to read 3, iclass 15, count 0 2006.259.07:45:40.32#ibcon#read 3, iclass 15, count 0 2006.259.07:45:40.32#ibcon#about to read 4, iclass 15, count 0 2006.259.07:45:40.32#ibcon#read 4, iclass 15, count 0 2006.259.07:45:40.32#ibcon#about to read 5, iclass 15, count 0 2006.259.07:45:40.32#ibcon#read 5, iclass 15, count 0 2006.259.07:45:40.32#ibcon#about to read 6, iclass 15, count 0 2006.259.07:45:40.32#ibcon#read 6, iclass 15, count 0 2006.259.07:45:40.32#ibcon#end of sib2, iclass 15, count 0 2006.259.07:45:40.32#ibcon#*after write, iclass 15, count 0 2006.259.07:45:40.32#ibcon#*before return 0, iclass 15, count 0 2006.259.07:45:40.32#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.259.07:45:40.32#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.259.07:45:40.32#ibcon#about to clear, iclass 15 cls_cnt 0 2006.259.07:45:40.32#ibcon#cleared, iclass 15 cls_cnt 0 2006.259.07:45:40.32$vc4f8/va=5,7 2006.259.07:45:40.32#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.259.07:45:40.32#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.259.07:45:40.32#ibcon#ireg 11 cls_cnt 2 2006.259.07:45:40.32#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.259.07:45:40.38#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.259.07:45:40.38#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.259.07:45:40.38#ibcon#enter wrdev, iclass 17, count 2 2006.259.07:45:40.38#ibcon#first serial, iclass 17, count 2 2006.259.07:45:40.38#ibcon#enter sib2, iclass 17, count 2 2006.259.07:45:40.38#ibcon#flushed, iclass 17, count 2 2006.259.07:45:40.38#ibcon#about to write, iclass 17, count 2 2006.259.07:45:40.38#ibcon#wrote, iclass 17, count 2 2006.259.07:45:40.38#ibcon#about to read 3, iclass 17, count 2 2006.259.07:45:40.40#ibcon#read 3, iclass 17, count 2 2006.259.07:45:40.40#ibcon#about to read 4, iclass 17, count 2 2006.259.07:45:40.40#ibcon#read 4, iclass 17, count 2 2006.259.07:45:40.40#ibcon#about to read 5, iclass 17, count 2 2006.259.07:45:40.40#ibcon#read 5, iclass 17, count 2 2006.259.07:45:40.40#ibcon#about to read 6, iclass 17, count 2 2006.259.07:45:40.40#ibcon#read 6, iclass 17, count 2 2006.259.07:45:40.40#ibcon#end of sib2, iclass 17, count 2 2006.259.07:45:40.40#ibcon#*mode == 0, iclass 17, count 2 2006.259.07:45:40.40#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.259.07:45:40.40#ibcon#[25=AT05-07\r\n] 2006.259.07:45:40.40#ibcon#*before write, iclass 17, count 2 2006.259.07:45:40.40#ibcon#enter sib2, iclass 17, count 2 2006.259.07:45:40.40#ibcon#flushed, iclass 17, count 2 2006.259.07:45:40.40#ibcon#about to write, iclass 17, count 2 2006.259.07:45:40.40#ibcon#wrote, iclass 17, count 2 2006.259.07:45:40.40#ibcon#about to read 3, iclass 17, count 2 2006.259.07:45:40.43#ibcon#read 3, iclass 17, count 2 2006.259.07:45:40.43#ibcon#about to read 4, iclass 17, count 2 2006.259.07:45:40.43#ibcon#read 4, iclass 17, count 2 2006.259.07:45:40.43#ibcon#about to read 5, iclass 17, count 2 2006.259.07:45:40.43#ibcon#read 5, iclass 17, count 2 2006.259.07:45:40.43#ibcon#about to read 6, iclass 17, count 2 2006.259.07:45:40.43#ibcon#read 6, iclass 17, count 2 2006.259.07:45:40.43#ibcon#end of sib2, iclass 17, count 2 2006.259.07:45:40.43#ibcon#*after write, iclass 17, count 2 2006.259.07:45:40.43#ibcon#*before return 0, iclass 17, count 2 2006.259.07:45:40.43#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.259.07:45:40.43#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.259.07:45:40.43#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.259.07:45:40.43#ibcon#ireg 7 cls_cnt 0 2006.259.07:45:40.43#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.259.07:45:40.55#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.259.07:45:40.55#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.259.07:45:40.55#ibcon#enter wrdev, iclass 17, count 0 2006.259.07:45:40.55#ibcon#first serial, iclass 17, count 0 2006.259.07:45:40.55#ibcon#enter sib2, iclass 17, count 0 2006.259.07:45:40.55#ibcon#flushed, iclass 17, count 0 2006.259.07:45:40.55#ibcon#about to write, iclass 17, count 0 2006.259.07:45:40.55#ibcon#wrote, iclass 17, count 0 2006.259.07:45:40.55#ibcon#about to read 3, iclass 17, count 0 2006.259.07:45:40.57#ibcon#read 3, iclass 17, count 0 2006.259.07:45:40.57#ibcon#about to read 4, iclass 17, count 0 2006.259.07:45:40.57#ibcon#read 4, iclass 17, count 0 2006.259.07:45:40.57#ibcon#about to read 5, iclass 17, count 0 2006.259.07:45:40.57#ibcon#read 5, iclass 17, count 0 2006.259.07:45:40.57#ibcon#about to read 6, iclass 17, count 0 2006.259.07:45:40.57#ibcon#read 6, iclass 17, count 0 2006.259.07:45:40.57#ibcon#end of sib2, iclass 17, count 0 2006.259.07:45:40.57#ibcon#*mode == 0, iclass 17, count 0 2006.259.07:45:40.57#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.259.07:45:40.57#ibcon#[25=USB\r\n] 2006.259.07:45:40.57#ibcon#*before write, iclass 17, count 0 2006.259.07:45:40.57#ibcon#enter sib2, iclass 17, count 0 2006.259.07:45:40.57#ibcon#flushed, iclass 17, count 0 2006.259.07:45:40.57#ibcon#about to write, iclass 17, count 0 2006.259.07:45:40.57#ibcon#wrote, iclass 17, count 0 2006.259.07:45:40.57#ibcon#about to read 3, iclass 17, count 0 2006.259.07:45:40.60#ibcon#read 3, iclass 17, count 0 2006.259.07:45:40.60#ibcon#about to read 4, iclass 17, count 0 2006.259.07:45:40.60#ibcon#read 4, iclass 17, count 0 2006.259.07:45:40.60#ibcon#about to read 5, iclass 17, count 0 2006.259.07:45:40.60#ibcon#read 5, iclass 17, count 0 2006.259.07:45:40.60#ibcon#about to read 6, iclass 17, count 0 2006.259.07:45:40.60#ibcon#read 6, iclass 17, count 0 2006.259.07:45:40.60#ibcon#end of sib2, iclass 17, count 0 2006.259.07:45:40.60#ibcon#*after write, iclass 17, count 0 2006.259.07:45:40.60#ibcon#*before return 0, iclass 17, count 0 2006.259.07:45:40.60#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.259.07:45:40.60#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.259.07:45:40.60#ibcon#about to clear, iclass 17 cls_cnt 0 2006.259.07:45:40.60#ibcon#cleared, iclass 17 cls_cnt 0 2006.259.07:45:40.60$vc4f8/valo=6,772.99 2006.259.07:45:40.60#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.259.07:45:40.60#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.259.07:45:40.60#ibcon#ireg 17 cls_cnt 0 2006.259.07:45:40.60#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.259.07:45:40.60#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.259.07:45:40.60#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.259.07:45:40.60#ibcon#enter wrdev, iclass 19, count 0 2006.259.07:45:40.60#ibcon#first serial, iclass 19, count 0 2006.259.07:45:40.60#ibcon#enter sib2, iclass 19, count 0 2006.259.07:45:40.60#ibcon#flushed, iclass 19, count 0 2006.259.07:45:40.60#ibcon#about to write, iclass 19, count 0 2006.259.07:45:40.60#ibcon#wrote, iclass 19, count 0 2006.259.07:45:40.60#ibcon#about to read 3, iclass 19, count 0 2006.259.07:45:40.62#ibcon#read 3, iclass 19, count 0 2006.259.07:45:40.62#ibcon#about to read 4, iclass 19, count 0 2006.259.07:45:40.62#ibcon#read 4, iclass 19, count 0 2006.259.07:45:40.62#ibcon#about to read 5, iclass 19, count 0 2006.259.07:45:40.62#ibcon#read 5, iclass 19, count 0 2006.259.07:45:40.62#ibcon#about to read 6, iclass 19, count 0 2006.259.07:45:40.62#ibcon#read 6, iclass 19, count 0 2006.259.07:45:40.62#ibcon#end of sib2, iclass 19, count 0 2006.259.07:45:40.62#ibcon#*mode == 0, iclass 19, count 0 2006.259.07:45:40.62#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.259.07:45:40.62#ibcon#[26=FRQ=06,772.99\r\n] 2006.259.07:45:40.62#ibcon#*before write, iclass 19, count 0 2006.259.07:45:40.62#ibcon#enter sib2, iclass 19, count 0 2006.259.07:45:40.62#ibcon#flushed, iclass 19, count 0 2006.259.07:45:40.62#ibcon#about to write, iclass 19, count 0 2006.259.07:45:40.62#ibcon#wrote, iclass 19, count 0 2006.259.07:45:40.62#ibcon#about to read 3, iclass 19, count 0 2006.259.07:45:40.66#ibcon#read 3, iclass 19, count 0 2006.259.07:45:40.66#ibcon#about to read 4, iclass 19, count 0 2006.259.07:45:40.66#ibcon#read 4, iclass 19, count 0 2006.259.07:45:40.66#ibcon#about to read 5, iclass 19, count 0 2006.259.07:45:40.66#ibcon#read 5, iclass 19, count 0 2006.259.07:45:40.66#ibcon#about to read 6, iclass 19, count 0 2006.259.07:45:40.66#ibcon#read 6, iclass 19, count 0 2006.259.07:45:40.66#ibcon#end of sib2, iclass 19, count 0 2006.259.07:45:40.66#ibcon#*after write, iclass 19, count 0 2006.259.07:45:40.66#ibcon#*before return 0, iclass 19, count 0 2006.259.07:45:40.66#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.259.07:45:40.66#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.259.07:45:40.66#ibcon#about to clear, iclass 19 cls_cnt 0 2006.259.07:45:40.66#ibcon#cleared, iclass 19 cls_cnt 0 2006.259.07:45:40.66$vc4f8/va=6,6 2006.259.07:45:40.66#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.259.07:45:40.66#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.259.07:45:40.66#ibcon#ireg 11 cls_cnt 2 2006.259.07:45:40.66#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.259.07:45:40.72#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.259.07:45:40.72#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.259.07:45:40.72#ibcon#enter wrdev, iclass 21, count 2 2006.259.07:45:40.72#ibcon#first serial, iclass 21, count 2 2006.259.07:45:40.72#ibcon#enter sib2, iclass 21, count 2 2006.259.07:45:40.72#ibcon#flushed, iclass 21, count 2 2006.259.07:45:40.72#ibcon#about to write, iclass 21, count 2 2006.259.07:45:40.72#ibcon#wrote, iclass 21, count 2 2006.259.07:45:40.72#ibcon#about to read 3, iclass 21, count 2 2006.259.07:45:40.74#ibcon#read 3, iclass 21, count 2 2006.259.07:45:40.74#ibcon#about to read 4, iclass 21, count 2 2006.259.07:45:40.74#ibcon#read 4, iclass 21, count 2 2006.259.07:45:40.74#ibcon#about to read 5, iclass 21, count 2 2006.259.07:45:40.74#ibcon#read 5, iclass 21, count 2 2006.259.07:45:40.74#ibcon#about to read 6, iclass 21, count 2 2006.259.07:45:40.74#ibcon#read 6, iclass 21, count 2 2006.259.07:45:40.74#ibcon#end of sib2, iclass 21, count 2 2006.259.07:45:40.74#ibcon#*mode == 0, iclass 21, count 2 2006.259.07:45:40.74#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.259.07:45:40.74#ibcon#[25=AT06-06\r\n] 2006.259.07:45:40.74#ibcon#*before write, iclass 21, count 2 2006.259.07:45:40.74#ibcon#enter sib2, iclass 21, count 2 2006.259.07:45:40.74#ibcon#flushed, iclass 21, count 2 2006.259.07:45:40.74#ibcon#about to write, iclass 21, count 2 2006.259.07:45:40.74#ibcon#wrote, iclass 21, count 2 2006.259.07:45:40.74#ibcon#about to read 3, iclass 21, count 2 2006.259.07:45:40.77#ibcon#read 3, iclass 21, count 2 2006.259.07:45:40.77#ibcon#about to read 4, iclass 21, count 2 2006.259.07:45:40.77#ibcon#read 4, iclass 21, count 2 2006.259.07:45:40.77#ibcon#about to read 5, iclass 21, count 2 2006.259.07:45:40.77#ibcon#read 5, iclass 21, count 2 2006.259.07:45:40.77#ibcon#about to read 6, iclass 21, count 2 2006.259.07:45:40.77#ibcon#read 6, iclass 21, count 2 2006.259.07:45:40.77#ibcon#end of sib2, iclass 21, count 2 2006.259.07:45:40.77#ibcon#*after write, iclass 21, count 2 2006.259.07:45:40.77#ibcon#*before return 0, iclass 21, count 2 2006.259.07:45:40.77#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.259.07:45:40.77#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.259.07:45:40.77#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.259.07:45:40.77#ibcon#ireg 7 cls_cnt 0 2006.259.07:45:40.77#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.259.07:45:40.89#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.259.07:45:40.89#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.259.07:45:40.89#ibcon#enter wrdev, iclass 21, count 0 2006.259.07:45:40.89#ibcon#first serial, iclass 21, count 0 2006.259.07:45:40.89#ibcon#enter sib2, iclass 21, count 0 2006.259.07:45:40.89#ibcon#flushed, iclass 21, count 0 2006.259.07:45:40.89#ibcon#about to write, iclass 21, count 0 2006.259.07:45:40.89#ibcon#wrote, iclass 21, count 0 2006.259.07:45:40.89#ibcon#about to read 3, iclass 21, count 0 2006.259.07:45:40.91#ibcon#read 3, iclass 21, count 0 2006.259.07:45:40.91#ibcon#about to read 4, iclass 21, count 0 2006.259.07:45:40.91#ibcon#read 4, iclass 21, count 0 2006.259.07:45:40.91#ibcon#about to read 5, iclass 21, count 0 2006.259.07:45:40.91#ibcon#read 5, iclass 21, count 0 2006.259.07:45:40.91#ibcon#about to read 6, iclass 21, count 0 2006.259.07:45:40.91#ibcon#read 6, iclass 21, count 0 2006.259.07:45:40.91#ibcon#end of sib2, iclass 21, count 0 2006.259.07:45:40.91#ibcon#*mode == 0, iclass 21, count 0 2006.259.07:45:40.91#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.259.07:45:40.91#ibcon#[25=USB\r\n] 2006.259.07:45:40.91#ibcon#*before write, iclass 21, count 0 2006.259.07:45:40.91#ibcon#enter sib2, iclass 21, count 0 2006.259.07:45:40.91#ibcon#flushed, iclass 21, count 0 2006.259.07:45:40.91#ibcon#about to write, iclass 21, count 0 2006.259.07:45:40.91#ibcon#wrote, iclass 21, count 0 2006.259.07:45:40.91#ibcon#about to read 3, iclass 21, count 0 2006.259.07:45:40.94#ibcon#read 3, iclass 21, count 0 2006.259.07:45:40.94#ibcon#about to read 4, iclass 21, count 0 2006.259.07:45:40.94#ibcon#read 4, iclass 21, count 0 2006.259.07:45:40.94#ibcon#about to read 5, iclass 21, count 0 2006.259.07:45:40.94#ibcon#read 5, iclass 21, count 0 2006.259.07:45:40.94#ibcon#about to read 6, iclass 21, count 0 2006.259.07:45:40.94#ibcon#read 6, iclass 21, count 0 2006.259.07:45:40.94#ibcon#end of sib2, iclass 21, count 0 2006.259.07:45:40.94#ibcon#*after write, iclass 21, count 0 2006.259.07:45:40.94#ibcon#*before return 0, iclass 21, count 0 2006.259.07:45:40.94#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.259.07:45:40.94#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.259.07:45:40.94#ibcon#about to clear, iclass 21 cls_cnt 0 2006.259.07:45:40.94#ibcon#cleared, iclass 21 cls_cnt 0 2006.259.07:45:40.94$vc4f8/valo=7,832.99 2006.259.07:45:40.94#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.259.07:45:40.94#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.259.07:45:40.94#ibcon#ireg 17 cls_cnt 0 2006.259.07:45:40.94#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.259.07:45:40.94#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.259.07:45:40.94#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.259.07:45:40.94#ibcon#enter wrdev, iclass 23, count 0 2006.259.07:45:40.94#ibcon#first serial, iclass 23, count 0 2006.259.07:45:40.94#ibcon#enter sib2, iclass 23, count 0 2006.259.07:45:40.94#ibcon#flushed, iclass 23, count 0 2006.259.07:45:40.94#ibcon#about to write, iclass 23, count 0 2006.259.07:45:40.94#ibcon#wrote, iclass 23, count 0 2006.259.07:45:40.94#ibcon#about to read 3, iclass 23, count 0 2006.259.07:45:40.96#ibcon#read 3, iclass 23, count 0 2006.259.07:45:40.96#ibcon#about to read 4, iclass 23, count 0 2006.259.07:45:40.96#ibcon#read 4, iclass 23, count 0 2006.259.07:45:40.96#ibcon#about to read 5, iclass 23, count 0 2006.259.07:45:40.96#ibcon#read 5, iclass 23, count 0 2006.259.07:45:40.96#ibcon#about to read 6, iclass 23, count 0 2006.259.07:45:40.96#ibcon#read 6, iclass 23, count 0 2006.259.07:45:40.96#ibcon#end of sib2, iclass 23, count 0 2006.259.07:45:40.96#ibcon#*mode == 0, iclass 23, count 0 2006.259.07:45:40.96#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.259.07:45:40.96#ibcon#[26=FRQ=07,832.99\r\n] 2006.259.07:45:40.96#ibcon#*before write, iclass 23, count 0 2006.259.07:45:40.96#ibcon#enter sib2, iclass 23, count 0 2006.259.07:45:40.96#ibcon#flushed, iclass 23, count 0 2006.259.07:45:40.96#ibcon#about to write, iclass 23, count 0 2006.259.07:45:40.96#ibcon#wrote, iclass 23, count 0 2006.259.07:45:40.96#ibcon#about to read 3, iclass 23, count 0 2006.259.07:45:41.00#ibcon#read 3, iclass 23, count 0 2006.259.07:45:41.00#ibcon#about to read 4, iclass 23, count 0 2006.259.07:45:41.00#ibcon#read 4, iclass 23, count 0 2006.259.07:45:41.00#ibcon#about to read 5, iclass 23, count 0 2006.259.07:45:41.00#ibcon#read 5, iclass 23, count 0 2006.259.07:45:41.00#ibcon#about to read 6, iclass 23, count 0 2006.259.07:45:41.00#ibcon#read 6, iclass 23, count 0 2006.259.07:45:41.00#ibcon#end of sib2, iclass 23, count 0 2006.259.07:45:41.00#ibcon#*after write, iclass 23, count 0 2006.259.07:45:41.00#ibcon#*before return 0, iclass 23, count 0 2006.259.07:45:41.00#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.259.07:45:41.00#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.259.07:45:41.00#ibcon#about to clear, iclass 23 cls_cnt 0 2006.259.07:45:41.00#ibcon#cleared, iclass 23 cls_cnt 0 2006.259.07:45:41.00$vc4f8/va=7,6 2006.259.07:45:41.00#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.259.07:45:41.00#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.259.07:45:41.00#ibcon#ireg 11 cls_cnt 2 2006.259.07:45:41.00#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.259.07:45:41.06#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.259.07:45:41.06#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.259.07:45:41.06#ibcon#enter wrdev, iclass 25, count 2 2006.259.07:45:41.06#ibcon#first serial, iclass 25, count 2 2006.259.07:45:41.06#ibcon#enter sib2, iclass 25, count 2 2006.259.07:45:41.06#ibcon#flushed, iclass 25, count 2 2006.259.07:45:41.06#ibcon#about to write, iclass 25, count 2 2006.259.07:45:41.06#ibcon#wrote, iclass 25, count 2 2006.259.07:45:41.06#ibcon#about to read 3, iclass 25, count 2 2006.259.07:45:41.08#ibcon#read 3, iclass 25, count 2 2006.259.07:45:41.08#ibcon#about to read 4, iclass 25, count 2 2006.259.07:45:41.08#ibcon#read 4, iclass 25, count 2 2006.259.07:45:41.08#ibcon#about to read 5, iclass 25, count 2 2006.259.07:45:41.08#ibcon#read 5, iclass 25, count 2 2006.259.07:45:41.08#ibcon#about to read 6, iclass 25, count 2 2006.259.07:45:41.08#ibcon#read 6, iclass 25, count 2 2006.259.07:45:41.08#ibcon#end of sib2, iclass 25, count 2 2006.259.07:45:41.08#ibcon#*mode == 0, iclass 25, count 2 2006.259.07:45:41.08#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.259.07:45:41.08#ibcon#[25=AT07-06\r\n] 2006.259.07:45:41.08#ibcon#*before write, iclass 25, count 2 2006.259.07:45:41.08#ibcon#enter sib2, iclass 25, count 2 2006.259.07:45:41.08#ibcon#flushed, iclass 25, count 2 2006.259.07:45:41.08#ibcon#about to write, iclass 25, count 2 2006.259.07:45:41.08#ibcon#wrote, iclass 25, count 2 2006.259.07:45:41.08#ibcon#about to read 3, iclass 25, count 2 2006.259.07:45:41.11#ibcon#read 3, iclass 25, count 2 2006.259.07:45:41.11#ibcon#about to read 4, iclass 25, count 2 2006.259.07:45:41.11#ibcon#read 4, iclass 25, count 2 2006.259.07:45:41.11#ibcon#about to read 5, iclass 25, count 2 2006.259.07:45:41.11#ibcon#read 5, iclass 25, count 2 2006.259.07:45:41.11#ibcon#about to read 6, iclass 25, count 2 2006.259.07:45:41.11#ibcon#read 6, iclass 25, count 2 2006.259.07:45:41.11#ibcon#end of sib2, iclass 25, count 2 2006.259.07:45:41.11#ibcon#*after write, iclass 25, count 2 2006.259.07:45:41.11#ibcon#*before return 0, iclass 25, count 2 2006.259.07:45:41.11#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.259.07:45:41.11#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.259.07:45:41.11#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.259.07:45:41.11#ibcon#ireg 7 cls_cnt 0 2006.259.07:45:41.11#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.259.07:45:41.23#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.259.07:45:41.23#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.259.07:45:41.23#ibcon#enter wrdev, iclass 25, count 0 2006.259.07:45:41.23#ibcon#first serial, iclass 25, count 0 2006.259.07:45:41.23#ibcon#enter sib2, iclass 25, count 0 2006.259.07:45:41.23#ibcon#flushed, iclass 25, count 0 2006.259.07:45:41.23#ibcon#about to write, iclass 25, count 0 2006.259.07:45:41.23#ibcon#wrote, iclass 25, count 0 2006.259.07:45:41.23#ibcon#about to read 3, iclass 25, count 0 2006.259.07:45:41.25#ibcon#read 3, iclass 25, count 0 2006.259.07:45:41.25#ibcon#about to read 4, iclass 25, count 0 2006.259.07:45:41.25#ibcon#read 4, iclass 25, count 0 2006.259.07:45:41.25#ibcon#about to read 5, iclass 25, count 0 2006.259.07:45:41.25#ibcon#read 5, iclass 25, count 0 2006.259.07:45:41.25#ibcon#about to read 6, iclass 25, count 0 2006.259.07:45:41.25#ibcon#read 6, iclass 25, count 0 2006.259.07:45:41.25#ibcon#end of sib2, iclass 25, count 0 2006.259.07:45:41.25#ibcon#*mode == 0, iclass 25, count 0 2006.259.07:45:41.25#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.259.07:45:41.25#ibcon#[25=USB\r\n] 2006.259.07:45:41.25#ibcon#*before write, iclass 25, count 0 2006.259.07:45:41.25#ibcon#enter sib2, iclass 25, count 0 2006.259.07:45:41.25#ibcon#flushed, iclass 25, count 0 2006.259.07:45:41.25#ibcon#about to write, iclass 25, count 0 2006.259.07:45:41.25#ibcon#wrote, iclass 25, count 0 2006.259.07:45:41.25#ibcon#about to read 3, iclass 25, count 0 2006.259.07:45:41.28#ibcon#read 3, iclass 25, count 0 2006.259.07:45:41.28#ibcon#about to read 4, iclass 25, count 0 2006.259.07:45:41.28#ibcon#read 4, iclass 25, count 0 2006.259.07:45:41.28#ibcon#about to read 5, iclass 25, count 0 2006.259.07:45:41.28#ibcon#read 5, iclass 25, count 0 2006.259.07:45:41.28#ibcon#about to read 6, iclass 25, count 0 2006.259.07:45:41.28#ibcon#read 6, iclass 25, count 0 2006.259.07:45:41.28#ibcon#end of sib2, iclass 25, count 0 2006.259.07:45:41.28#ibcon#*after write, iclass 25, count 0 2006.259.07:45:41.28#ibcon#*before return 0, iclass 25, count 0 2006.259.07:45:41.28#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.259.07:45:41.28#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.259.07:45:41.28#ibcon#about to clear, iclass 25 cls_cnt 0 2006.259.07:45:41.28#ibcon#cleared, iclass 25 cls_cnt 0 2006.259.07:45:41.28$vc4f8/valo=8,852.99 2006.259.07:45:41.28#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.259.07:45:41.28#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.259.07:45:41.28#ibcon#ireg 17 cls_cnt 0 2006.259.07:45:41.28#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.259.07:45:41.28#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.259.07:45:41.28#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.259.07:45:41.28#ibcon#enter wrdev, iclass 27, count 0 2006.259.07:45:41.28#ibcon#first serial, iclass 27, count 0 2006.259.07:45:41.28#ibcon#enter sib2, iclass 27, count 0 2006.259.07:45:41.28#ibcon#flushed, iclass 27, count 0 2006.259.07:45:41.28#ibcon#about to write, iclass 27, count 0 2006.259.07:45:41.28#ibcon#wrote, iclass 27, count 0 2006.259.07:45:41.28#ibcon#about to read 3, iclass 27, count 0 2006.259.07:45:41.30#ibcon#read 3, iclass 27, count 0 2006.259.07:45:41.30#ibcon#about to read 4, iclass 27, count 0 2006.259.07:45:41.30#ibcon#read 4, iclass 27, count 0 2006.259.07:45:41.30#ibcon#about to read 5, iclass 27, count 0 2006.259.07:45:41.30#ibcon#read 5, iclass 27, count 0 2006.259.07:45:41.30#ibcon#about to read 6, iclass 27, count 0 2006.259.07:45:41.30#ibcon#read 6, iclass 27, count 0 2006.259.07:45:41.30#ibcon#end of sib2, iclass 27, count 0 2006.259.07:45:41.30#ibcon#*mode == 0, iclass 27, count 0 2006.259.07:45:41.30#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.259.07:45:41.30#ibcon#[26=FRQ=08,852.99\r\n] 2006.259.07:45:41.30#ibcon#*before write, iclass 27, count 0 2006.259.07:45:41.30#ibcon#enter sib2, iclass 27, count 0 2006.259.07:45:41.30#ibcon#flushed, iclass 27, count 0 2006.259.07:45:41.30#ibcon#about to write, iclass 27, count 0 2006.259.07:45:41.30#ibcon#wrote, iclass 27, count 0 2006.259.07:45:41.30#ibcon#about to read 3, iclass 27, count 0 2006.259.07:45:41.34#ibcon#read 3, iclass 27, count 0 2006.259.07:45:41.34#ibcon#about to read 4, iclass 27, count 0 2006.259.07:45:41.34#ibcon#read 4, iclass 27, count 0 2006.259.07:45:41.34#ibcon#about to read 5, iclass 27, count 0 2006.259.07:45:41.34#ibcon#read 5, iclass 27, count 0 2006.259.07:45:41.34#ibcon#about to read 6, iclass 27, count 0 2006.259.07:45:41.34#ibcon#read 6, iclass 27, count 0 2006.259.07:45:41.34#ibcon#end of sib2, iclass 27, count 0 2006.259.07:45:41.34#ibcon#*after write, iclass 27, count 0 2006.259.07:45:41.34#ibcon#*before return 0, iclass 27, count 0 2006.259.07:45:41.34#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.259.07:45:41.34#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.259.07:45:41.34#ibcon#about to clear, iclass 27 cls_cnt 0 2006.259.07:45:41.34#ibcon#cleared, iclass 27 cls_cnt 0 2006.259.07:45:41.34$vc4f8/va=8,6 2006.259.07:45:41.34#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.259.07:45:41.34#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.259.07:45:41.34#ibcon#ireg 11 cls_cnt 2 2006.259.07:45:41.34#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.259.07:45:41.40#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.259.07:45:41.40#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.259.07:45:41.40#ibcon#enter wrdev, iclass 29, count 2 2006.259.07:45:41.40#ibcon#first serial, iclass 29, count 2 2006.259.07:45:41.40#ibcon#enter sib2, iclass 29, count 2 2006.259.07:45:41.40#ibcon#flushed, iclass 29, count 2 2006.259.07:45:41.40#ibcon#about to write, iclass 29, count 2 2006.259.07:45:41.40#ibcon#wrote, iclass 29, count 2 2006.259.07:45:41.40#ibcon#about to read 3, iclass 29, count 2 2006.259.07:45:41.42#ibcon#read 3, iclass 29, count 2 2006.259.07:45:41.42#ibcon#about to read 4, iclass 29, count 2 2006.259.07:45:41.42#ibcon#read 4, iclass 29, count 2 2006.259.07:45:41.42#ibcon#about to read 5, iclass 29, count 2 2006.259.07:45:41.42#ibcon#read 5, iclass 29, count 2 2006.259.07:45:41.42#ibcon#about to read 6, iclass 29, count 2 2006.259.07:45:41.42#ibcon#read 6, iclass 29, count 2 2006.259.07:45:41.42#ibcon#end of sib2, iclass 29, count 2 2006.259.07:45:41.42#ibcon#*mode == 0, iclass 29, count 2 2006.259.07:45:41.42#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.259.07:45:41.42#ibcon#[25=AT08-06\r\n] 2006.259.07:45:41.42#ibcon#*before write, iclass 29, count 2 2006.259.07:45:41.42#ibcon#enter sib2, iclass 29, count 2 2006.259.07:45:41.42#ibcon#flushed, iclass 29, count 2 2006.259.07:45:41.42#ibcon#about to write, iclass 29, count 2 2006.259.07:45:41.42#ibcon#wrote, iclass 29, count 2 2006.259.07:45:41.42#ibcon#about to read 3, iclass 29, count 2 2006.259.07:45:41.45#ibcon#read 3, iclass 29, count 2 2006.259.07:45:41.45#ibcon#about to read 4, iclass 29, count 2 2006.259.07:45:41.45#ibcon#read 4, iclass 29, count 2 2006.259.07:45:41.45#ibcon#about to read 5, iclass 29, count 2 2006.259.07:45:41.45#ibcon#read 5, iclass 29, count 2 2006.259.07:45:41.45#ibcon#about to read 6, iclass 29, count 2 2006.259.07:45:41.45#ibcon#read 6, iclass 29, count 2 2006.259.07:45:41.45#ibcon#end of sib2, iclass 29, count 2 2006.259.07:45:41.45#ibcon#*after write, iclass 29, count 2 2006.259.07:45:41.45#ibcon#*before return 0, iclass 29, count 2 2006.259.07:45:41.45#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.259.07:45:41.45#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.259.07:45:41.45#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.259.07:45:41.45#ibcon#ireg 7 cls_cnt 0 2006.259.07:45:41.45#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.259.07:45:41.57#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.259.07:45:41.57#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.259.07:45:41.57#ibcon#enter wrdev, iclass 29, count 0 2006.259.07:45:41.57#ibcon#first serial, iclass 29, count 0 2006.259.07:45:41.57#ibcon#enter sib2, iclass 29, count 0 2006.259.07:45:41.57#ibcon#flushed, iclass 29, count 0 2006.259.07:45:41.57#ibcon#about to write, iclass 29, count 0 2006.259.07:45:41.57#ibcon#wrote, iclass 29, count 0 2006.259.07:45:41.57#ibcon#about to read 3, iclass 29, count 0 2006.259.07:45:41.59#ibcon#read 3, iclass 29, count 0 2006.259.07:45:41.59#ibcon#about to read 4, iclass 29, count 0 2006.259.07:45:41.59#ibcon#read 4, iclass 29, count 0 2006.259.07:45:41.59#ibcon#about to read 5, iclass 29, count 0 2006.259.07:45:41.59#ibcon#read 5, iclass 29, count 0 2006.259.07:45:41.59#ibcon#about to read 6, iclass 29, count 0 2006.259.07:45:41.59#ibcon#read 6, iclass 29, count 0 2006.259.07:45:41.59#ibcon#end of sib2, iclass 29, count 0 2006.259.07:45:41.59#ibcon#*mode == 0, iclass 29, count 0 2006.259.07:45:41.59#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.259.07:45:41.59#ibcon#[25=USB\r\n] 2006.259.07:45:41.59#ibcon#*before write, iclass 29, count 0 2006.259.07:45:41.59#ibcon#enter sib2, iclass 29, count 0 2006.259.07:45:41.59#ibcon#flushed, iclass 29, count 0 2006.259.07:45:41.59#ibcon#about to write, iclass 29, count 0 2006.259.07:45:41.59#ibcon#wrote, iclass 29, count 0 2006.259.07:45:41.59#ibcon#about to read 3, iclass 29, count 0 2006.259.07:45:41.62#ibcon#read 3, iclass 29, count 0 2006.259.07:45:41.62#ibcon#about to read 4, iclass 29, count 0 2006.259.07:45:41.62#ibcon#read 4, iclass 29, count 0 2006.259.07:45:41.62#ibcon#about to read 5, iclass 29, count 0 2006.259.07:45:41.62#ibcon#read 5, iclass 29, count 0 2006.259.07:45:41.62#ibcon#about to read 6, iclass 29, count 0 2006.259.07:45:41.62#ibcon#read 6, iclass 29, count 0 2006.259.07:45:41.62#ibcon#end of sib2, iclass 29, count 0 2006.259.07:45:41.62#ibcon#*after write, iclass 29, count 0 2006.259.07:45:41.62#ibcon#*before return 0, iclass 29, count 0 2006.259.07:45:41.62#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.259.07:45:41.62#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.259.07:45:41.62#ibcon#about to clear, iclass 29 cls_cnt 0 2006.259.07:45:41.62#ibcon#cleared, iclass 29 cls_cnt 0 2006.259.07:45:41.62$vc4f8/vblo=1,632.99 2006.259.07:45:41.62#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.259.07:45:41.62#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.259.07:45:41.62#ibcon#ireg 17 cls_cnt 0 2006.259.07:45:41.62#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.259.07:45:41.62#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.259.07:45:41.62#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.259.07:45:41.62#ibcon#enter wrdev, iclass 31, count 0 2006.259.07:45:41.62#ibcon#first serial, iclass 31, count 0 2006.259.07:45:41.62#ibcon#enter sib2, iclass 31, count 0 2006.259.07:45:41.62#ibcon#flushed, iclass 31, count 0 2006.259.07:45:41.62#ibcon#about to write, iclass 31, count 0 2006.259.07:45:41.62#ibcon#wrote, iclass 31, count 0 2006.259.07:45:41.62#ibcon#about to read 3, iclass 31, count 0 2006.259.07:45:41.64#ibcon#read 3, iclass 31, count 0 2006.259.07:45:41.64#ibcon#about to read 4, iclass 31, count 0 2006.259.07:45:41.64#ibcon#read 4, iclass 31, count 0 2006.259.07:45:41.64#ibcon#about to read 5, iclass 31, count 0 2006.259.07:45:41.64#ibcon#read 5, iclass 31, count 0 2006.259.07:45:41.64#ibcon#about to read 6, iclass 31, count 0 2006.259.07:45:41.64#ibcon#read 6, iclass 31, count 0 2006.259.07:45:41.64#ibcon#end of sib2, iclass 31, count 0 2006.259.07:45:41.64#ibcon#*mode == 0, iclass 31, count 0 2006.259.07:45:41.64#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.259.07:45:41.64#ibcon#[28=FRQ=01,632.99\r\n] 2006.259.07:45:41.64#ibcon#*before write, iclass 31, count 0 2006.259.07:45:41.64#ibcon#enter sib2, iclass 31, count 0 2006.259.07:45:41.64#ibcon#flushed, iclass 31, count 0 2006.259.07:45:41.64#ibcon#about to write, iclass 31, count 0 2006.259.07:45:41.64#ibcon#wrote, iclass 31, count 0 2006.259.07:45:41.64#ibcon#about to read 3, iclass 31, count 0 2006.259.07:45:41.68#ibcon#read 3, iclass 31, count 0 2006.259.07:45:41.68#ibcon#about to read 4, iclass 31, count 0 2006.259.07:45:41.68#ibcon#read 4, iclass 31, count 0 2006.259.07:45:41.68#ibcon#about to read 5, iclass 31, count 0 2006.259.07:45:41.68#ibcon#read 5, iclass 31, count 0 2006.259.07:45:41.68#ibcon#about to read 6, iclass 31, count 0 2006.259.07:45:41.68#ibcon#read 6, iclass 31, count 0 2006.259.07:45:41.68#ibcon#end of sib2, iclass 31, count 0 2006.259.07:45:41.68#ibcon#*after write, iclass 31, count 0 2006.259.07:45:41.68#ibcon#*before return 0, iclass 31, count 0 2006.259.07:45:41.68#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.259.07:45:41.68#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.259.07:45:41.68#ibcon#about to clear, iclass 31 cls_cnt 0 2006.259.07:45:41.68#ibcon#cleared, iclass 31 cls_cnt 0 2006.259.07:45:41.68$vc4f8/vb=1,4 2006.259.07:45:41.68#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.259.07:45:41.68#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.259.07:45:41.68#ibcon#ireg 11 cls_cnt 2 2006.259.07:45:41.68#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.259.07:45:41.68#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.259.07:45:41.68#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.259.07:45:41.68#ibcon#enter wrdev, iclass 33, count 2 2006.259.07:45:41.68#ibcon#first serial, iclass 33, count 2 2006.259.07:45:41.68#ibcon#enter sib2, iclass 33, count 2 2006.259.07:45:41.68#ibcon#flushed, iclass 33, count 2 2006.259.07:45:41.68#ibcon#about to write, iclass 33, count 2 2006.259.07:45:41.68#ibcon#wrote, iclass 33, count 2 2006.259.07:45:41.68#ibcon#about to read 3, iclass 33, count 2 2006.259.07:45:41.70#ibcon#read 3, iclass 33, count 2 2006.259.07:45:41.70#ibcon#about to read 4, iclass 33, count 2 2006.259.07:45:41.70#ibcon#read 4, iclass 33, count 2 2006.259.07:45:41.70#ibcon#about to read 5, iclass 33, count 2 2006.259.07:45:41.70#ibcon#read 5, iclass 33, count 2 2006.259.07:45:41.70#ibcon#about to read 6, iclass 33, count 2 2006.259.07:45:41.70#ibcon#read 6, iclass 33, count 2 2006.259.07:45:41.70#ibcon#end of sib2, iclass 33, count 2 2006.259.07:45:41.70#ibcon#*mode == 0, iclass 33, count 2 2006.259.07:45:41.70#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.259.07:45:41.70#ibcon#[27=AT01-04\r\n] 2006.259.07:45:41.70#ibcon#*before write, iclass 33, count 2 2006.259.07:45:41.70#ibcon#enter sib2, iclass 33, count 2 2006.259.07:45:41.70#ibcon#flushed, iclass 33, count 2 2006.259.07:45:41.70#ibcon#about to write, iclass 33, count 2 2006.259.07:45:41.70#ibcon#wrote, iclass 33, count 2 2006.259.07:45:41.70#ibcon#about to read 3, iclass 33, count 2 2006.259.07:45:41.73#ibcon#read 3, iclass 33, count 2 2006.259.07:45:41.73#ibcon#about to read 4, iclass 33, count 2 2006.259.07:45:41.73#ibcon#read 4, iclass 33, count 2 2006.259.07:45:41.73#ibcon#about to read 5, iclass 33, count 2 2006.259.07:45:41.73#ibcon#read 5, iclass 33, count 2 2006.259.07:45:41.73#ibcon#about to read 6, iclass 33, count 2 2006.259.07:45:41.73#ibcon#read 6, iclass 33, count 2 2006.259.07:45:41.73#ibcon#end of sib2, iclass 33, count 2 2006.259.07:45:41.73#ibcon#*after write, iclass 33, count 2 2006.259.07:45:41.73#ibcon#*before return 0, iclass 33, count 2 2006.259.07:45:41.73#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.259.07:45:41.73#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.259.07:45:41.73#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.259.07:45:41.73#ibcon#ireg 7 cls_cnt 0 2006.259.07:45:41.73#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.259.07:45:41.85#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.259.07:45:41.85#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.259.07:45:41.85#ibcon#enter wrdev, iclass 33, count 0 2006.259.07:45:41.85#ibcon#first serial, iclass 33, count 0 2006.259.07:45:41.85#ibcon#enter sib2, iclass 33, count 0 2006.259.07:45:41.85#ibcon#flushed, iclass 33, count 0 2006.259.07:45:41.85#ibcon#about to write, iclass 33, count 0 2006.259.07:45:41.85#ibcon#wrote, iclass 33, count 0 2006.259.07:45:41.85#ibcon#about to read 3, iclass 33, count 0 2006.259.07:45:41.87#ibcon#read 3, iclass 33, count 0 2006.259.07:45:41.87#ibcon#about to read 4, iclass 33, count 0 2006.259.07:45:41.87#ibcon#read 4, iclass 33, count 0 2006.259.07:45:41.87#ibcon#about to read 5, iclass 33, count 0 2006.259.07:45:41.87#ibcon#read 5, iclass 33, count 0 2006.259.07:45:41.87#ibcon#about to read 6, iclass 33, count 0 2006.259.07:45:41.87#ibcon#read 6, iclass 33, count 0 2006.259.07:45:41.87#ibcon#end of sib2, iclass 33, count 0 2006.259.07:45:41.87#ibcon#*mode == 0, iclass 33, count 0 2006.259.07:45:41.87#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.259.07:45:41.87#ibcon#[27=USB\r\n] 2006.259.07:45:41.87#ibcon#*before write, iclass 33, count 0 2006.259.07:45:41.87#ibcon#enter sib2, iclass 33, count 0 2006.259.07:45:41.87#ibcon#flushed, iclass 33, count 0 2006.259.07:45:41.87#ibcon#about to write, iclass 33, count 0 2006.259.07:45:41.87#ibcon#wrote, iclass 33, count 0 2006.259.07:45:41.87#ibcon#about to read 3, iclass 33, count 0 2006.259.07:45:41.90#ibcon#read 3, iclass 33, count 0 2006.259.07:45:41.90#ibcon#about to read 4, iclass 33, count 0 2006.259.07:45:41.90#ibcon#read 4, iclass 33, count 0 2006.259.07:45:41.90#ibcon#about to read 5, iclass 33, count 0 2006.259.07:45:41.90#ibcon#read 5, iclass 33, count 0 2006.259.07:45:41.90#ibcon#about to read 6, iclass 33, count 0 2006.259.07:45:41.90#ibcon#read 6, iclass 33, count 0 2006.259.07:45:41.90#ibcon#end of sib2, iclass 33, count 0 2006.259.07:45:41.90#ibcon#*after write, iclass 33, count 0 2006.259.07:45:41.90#ibcon#*before return 0, iclass 33, count 0 2006.259.07:45:41.90#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.259.07:45:41.90#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.259.07:45:41.90#ibcon#about to clear, iclass 33 cls_cnt 0 2006.259.07:45:41.90#ibcon#cleared, iclass 33 cls_cnt 0 2006.259.07:45:41.90$vc4f8/vblo=2,640.99 2006.259.07:45:41.90#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.259.07:45:41.90#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.259.07:45:41.90#ibcon#ireg 17 cls_cnt 0 2006.259.07:45:41.90#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.259.07:45:41.90#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.259.07:45:41.90#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.259.07:45:41.90#ibcon#enter wrdev, iclass 35, count 0 2006.259.07:45:41.90#ibcon#first serial, iclass 35, count 0 2006.259.07:45:41.90#ibcon#enter sib2, iclass 35, count 0 2006.259.07:45:41.90#ibcon#flushed, iclass 35, count 0 2006.259.07:45:41.90#ibcon#about to write, iclass 35, count 0 2006.259.07:45:41.90#ibcon#wrote, iclass 35, count 0 2006.259.07:45:41.90#ibcon#about to read 3, iclass 35, count 0 2006.259.07:45:41.92#ibcon#read 3, iclass 35, count 0 2006.259.07:45:41.92#ibcon#about to read 4, iclass 35, count 0 2006.259.07:45:41.92#ibcon#read 4, iclass 35, count 0 2006.259.07:45:41.92#ibcon#about to read 5, iclass 35, count 0 2006.259.07:45:41.92#ibcon#read 5, iclass 35, count 0 2006.259.07:45:41.92#ibcon#about to read 6, iclass 35, count 0 2006.259.07:45:41.92#ibcon#read 6, iclass 35, count 0 2006.259.07:45:41.92#ibcon#end of sib2, iclass 35, count 0 2006.259.07:45:41.92#ibcon#*mode == 0, iclass 35, count 0 2006.259.07:45:41.92#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.259.07:45:41.92#ibcon#[28=FRQ=02,640.99\r\n] 2006.259.07:45:41.92#ibcon#*before write, iclass 35, count 0 2006.259.07:45:41.92#ibcon#enter sib2, iclass 35, count 0 2006.259.07:45:41.92#ibcon#flushed, iclass 35, count 0 2006.259.07:45:41.92#ibcon#about to write, iclass 35, count 0 2006.259.07:45:41.92#ibcon#wrote, iclass 35, count 0 2006.259.07:45:41.92#ibcon#about to read 3, iclass 35, count 0 2006.259.07:45:41.96#ibcon#read 3, iclass 35, count 0 2006.259.07:45:41.96#ibcon#about to read 4, iclass 35, count 0 2006.259.07:45:41.96#ibcon#read 4, iclass 35, count 0 2006.259.07:45:41.96#ibcon#about to read 5, iclass 35, count 0 2006.259.07:45:41.96#ibcon#read 5, iclass 35, count 0 2006.259.07:45:41.96#ibcon#about to read 6, iclass 35, count 0 2006.259.07:45:41.96#ibcon#read 6, iclass 35, count 0 2006.259.07:45:41.96#ibcon#end of sib2, iclass 35, count 0 2006.259.07:45:41.96#ibcon#*after write, iclass 35, count 0 2006.259.07:45:41.96#ibcon#*before return 0, iclass 35, count 0 2006.259.07:45:41.96#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.259.07:45:41.96#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.259.07:45:41.96#ibcon#about to clear, iclass 35 cls_cnt 0 2006.259.07:45:41.96#ibcon#cleared, iclass 35 cls_cnt 0 2006.259.07:45:41.96$vc4f8/vb=2,5 2006.259.07:45:41.96#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.259.07:45:41.96#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.259.07:45:41.96#ibcon#ireg 11 cls_cnt 2 2006.259.07:45:41.96#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.259.07:45:42.02#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.259.07:45:42.02#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.259.07:45:42.02#ibcon#enter wrdev, iclass 37, count 2 2006.259.07:45:42.02#ibcon#first serial, iclass 37, count 2 2006.259.07:45:42.02#ibcon#enter sib2, iclass 37, count 2 2006.259.07:45:42.02#ibcon#flushed, iclass 37, count 2 2006.259.07:45:42.02#ibcon#about to write, iclass 37, count 2 2006.259.07:45:42.02#ibcon#wrote, iclass 37, count 2 2006.259.07:45:42.02#ibcon#about to read 3, iclass 37, count 2 2006.259.07:45:42.04#ibcon#read 3, iclass 37, count 2 2006.259.07:45:42.04#ibcon#about to read 4, iclass 37, count 2 2006.259.07:45:42.04#ibcon#read 4, iclass 37, count 2 2006.259.07:45:42.04#ibcon#about to read 5, iclass 37, count 2 2006.259.07:45:42.04#ibcon#read 5, iclass 37, count 2 2006.259.07:45:42.04#ibcon#about to read 6, iclass 37, count 2 2006.259.07:45:42.04#ibcon#read 6, iclass 37, count 2 2006.259.07:45:42.04#ibcon#end of sib2, iclass 37, count 2 2006.259.07:45:42.04#ibcon#*mode == 0, iclass 37, count 2 2006.259.07:45:42.04#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.259.07:45:42.04#ibcon#[27=AT02-05\r\n] 2006.259.07:45:42.04#ibcon#*before write, iclass 37, count 2 2006.259.07:45:42.04#ibcon#enter sib2, iclass 37, count 2 2006.259.07:45:42.04#ibcon#flushed, iclass 37, count 2 2006.259.07:45:42.04#ibcon#about to write, iclass 37, count 2 2006.259.07:45:42.04#ibcon#wrote, iclass 37, count 2 2006.259.07:45:42.04#ibcon#about to read 3, iclass 37, count 2 2006.259.07:45:42.07#ibcon#read 3, iclass 37, count 2 2006.259.07:45:42.07#ibcon#about to read 4, iclass 37, count 2 2006.259.07:45:42.07#ibcon#read 4, iclass 37, count 2 2006.259.07:45:42.07#ibcon#about to read 5, iclass 37, count 2 2006.259.07:45:42.07#ibcon#read 5, iclass 37, count 2 2006.259.07:45:42.07#ibcon#about to read 6, iclass 37, count 2 2006.259.07:45:42.07#ibcon#read 6, iclass 37, count 2 2006.259.07:45:42.07#ibcon#end of sib2, iclass 37, count 2 2006.259.07:45:42.07#ibcon#*after write, iclass 37, count 2 2006.259.07:45:42.07#ibcon#*before return 0, iclass 37, count 2 2006.259.07:45:42.07#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.259.07:45:42.07#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.259.07:45:42.07#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.259.07:45:42.07#ibcon#ireg 7 cls_cnt 0 2006.259.07:45:42.07#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.259.07:45:42.19#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.259.07:45:42.19#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.259.07:45:42.19#ibcon#enter wrdev, iclass 37, count 0 2006.259.07:45:42.19#ibcon#first serial, iclass 37, count 0 2006.259.07:45:42.19#ibcon#enter sib2, iclass 37, count 0 2006.259.07:45:42.19#ibcon#flushed, iclass 37, count 0 2006.259.07:45:42.19#ibcon#about to write, iclass 37, count 0 2006.259.07:45:42.19#ibcon#wrote, iclass 37, count 0 2006.259.07:45:42.19#ibcon#about to read 3, iclass 37, count 0 2006.259.07:45:42.21#ibcon#read 3, iclass 37, count 0 2006.259.07:45:42.21#ibcon#about to read 4, iclass 37, count 0 2006.259.07:45:42.21#ibcon#read 4, iclass 37, count 0 2006.259.07:45:42.21#ibcon#about to read 5, iclass 37, count 0 2006.259.07:45:42.21#ibcon#read 5, iclass 37, count 0 2006.259.07:45:42.21#ibcon#about to read 6, iclass 37, count 0 2006.259.07:45:42.21#ibcon#read 6, iclass 37, count 0 2006.259.07:45:42.21#ibcon#end of sib2, iclass 37, count 0 2006.259.07:45:42.21#ibcon#*mode == 0, iclass 37, count 0 2006.259.07:45:42.21#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.259.07:45:42.21#ibcon#[27=USB\r\n] 2006.259.07:45:42.21#ibcon#*before write, iclass 37, count 0 2006.259.07:45:42.21#ibcon#enter sib2, iclass 37, count 0 2006.259.07:45:42.21#ibcon#flushed, iclass 37, count 0 2006.259.07:45:42.21#ibcon#about to write, iclass 37, count 0 2006.259.07:45:42.21#ibcon#wrote, iclass 37, count 0 2006.259.07:45:42.21#ibcon#about to read 3, iclass 37, count 0 2006.259.07:45:42.24#ibcon#read 3, iclass 37, count 0 2006.259.07:45:42.24#ibcon#about to read 4, iclass 37, count 0 2006.259.07:45:42.24#ibcon#read 4, iclass 37, count 0 2006.259.07:45:42.24#ibcon#about to read 5, iclass 37, count 0 2006.259.07:45:42.24#ibcon#read 5, iclass 37, count 0 2006.259.07:45:42.24#ibcon#about to read 6, iclass 37, count 0 2006.259.07:45:42.24#ibcon#read 6, iclass 37, count 0 2006.259.07:45:42.24#ibcon#end of sib2, iclass 37, count 0 2006.259.07:45:42.24#ibcon#*after write, iclass 37, count 0 2006.259.07:45:42.24#ibcon#*before return 0, iclass 37, count 0 2006.259.07:45:42.24#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.259.07:45:42.24#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.259.07:45:42.24#ibcon#about to clear, iclass 37 cls_cnt 0 2006.259.07:45:42.24#ibcon#cleared, iclass 37 cls_cnt 0 2006.259.07:45:42.24$vc4f8/vblo=3,656.99 2006.259.07:45:42.24#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.259.07:45:42.24#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.259.07:45:42.24#ibcon#ireg 17 cls_cnt 0 2006.259.07:45:42.24#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.259.07:45:42.24#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.259.07:45:42.24#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.259.07:45:42.24#ibcon#enter wrdev, iclass 39, count 0 2006.259.07:45:42.24#ibcon#first serial, iclass 39, count 0 2006.259.07:45:42.24#ibcon#enter sib2, iclass 39, count 0 2006.259.07:45:42.24#ibcon#flushed, iclass 39, count 0 2006.259.07:45:42.24#ibcon#about to write, iclass 39, count 0 2006.259.07:45:42.24#ibcon#wrote, iclass 39, count 0 2006.259.07:45:42.24#ibcon#about to read 3, iclass 39, count 0 2006.259.07:45:42.26#ibcon#read 3, iclass 39, count 0 2006.259.07:45:42.26#ibcon#about to read 4, iclass 39, count 0 2006.259.07:45:42.26#ibcon#read 4, iclass 39, count 0 2006.259.07:45:42.26#ibcon#about to read 5, iclass 39, count 0 2006.259.07:45:42.26#ibcon#read 5, iclass 39, count 0 2006.259.07:45:42.26#ibcon#about to read 6, iclass 39, count 0 2006.259.07:45:42.26#ibcon#read 6, iclass 39, count 0 2006.259.07:45:42.26#ibcon#end of sib2, iclass 39, count 0 2006.259.07:45:42.26#ibcon#*mode == 0, iclass 39, count 0 2006.259.07:45:42.26#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.259.07:45:42.26#ibcon#[28=FRQ=03,656.99\r\n] 2006.259.07:45:42.26#ibcon#*before write, iclass 39, count 0 2006.259.07:45:42.26#ibcon#enter sib2, iclass 39, count 0 2006.259.07:45:42.26#ibcon#flushed, iclass 39, count 0 2006.259.07:45:42.26#ibcon#about to write, iclass 39, count 0 2006.259.07:45:42.26#ibcon#wrote, iclass 39, count 0 2006.259.07:45:42.26#ibcon#about to read 3, iclass 39, count 0 2006.259.07:45:42.30#ibcon#read 3, iclass 39, count 0 2006.259.07:45:42.30#ibcon#about to read 4, iclass 39, count 0 2006.259.07:45:42.30#ibcon#read 4, iclass 39, count 0 2006.259.07:45:42.30#ibcon#about to read 5, iclass 39, count 0 2006.259.07:45:42.30#ibcon#read 5, iclass 39, count 0 2006.259.07:45:42.30#ibcon#about to read 6, iclass 39, count 0 2006.259.07:45:42.30#ibcon#read 6, iclass 39, count 0 2006.259.07:45:42.30#ibcon#end of sib2, iclass 39, count 0 2006.259.07:45:42.30#ibcon#*after write, iclass 39, count 0 2006.259.07:45:42.30#ibcon#*before return 0, iclass 39, count 0 2006.259.07:45:42.30#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.259.07:45:42.30#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.259.07:45:42.30#ibcon#about to clear, iclass 39 cls_cnt 0 2006.259.07:45:42.30#ibcon#cleared, iclass 39 cls_cnt 0 2006.259.07:45:42.30$vc4f8/vb=3,4 2006.259.07:45:42.30#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.259.07:45:42.30#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.259.07:45:42.30#ibcon#ireg 11 cls_cnt 2 2006.259.07:45:42.30#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.259.07:45:42.36#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.259.07:45:42.36#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.259.07:45:42.36#ibcon#enter wrdev, iclass 3, count 2 2006.259.07:45:42.36#ibcon#first serial, iclass 3, count 2 2006.259.07:45:42.36#ibcon#enter sib2, iclass 3, count 2 2006.259.07:45:42.36#ibcon#flushed, iclass 3, count 2 2006.259.07:45:42.36#ibcon#about to write, iclass 3, count 2 2006.259.07:45:42.36#ibcon#wrote, iclass 3, count 2 2006.259.07:45:42.36#ibcon#about to read 3, iclass 3, count 2 2006.259.07:45:42.38#ibcon#read 3, iclass 3, count 2 2006.259.07:45:42.38#ibcon#about to read 4, iclass 3, count 2 2006.259.07:45:42.38#ibcon#read 4, iclass 3, count 2 2006.259.07:45:42.38#ibcon#about to read 5, iclass 3, count 2 2006.259.07:45:42.38#ibcon#read 5, iclass 3, count 2 2006.259.07:45:42.38#ibcon#about to read 6, iclass 3, count 2 2006.259.07:45:42.38#ibcon#read 6, iclass 3, count 2 2006.259.07:45:42.38#ibcon#end of sib2, iclass 3, count 2 2006.259.07:45:42.38#ibcon#*mode == 0, iclass 3, count 2 2006.259.07:45:42.38#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.259.07:45:42.38#ibcon#[27=AT03-04\r\n] 2006.259.07:45:42.38#ibcon#*before write, iclass 3, count 2 2006.259.07:45:42.38#ibcon#enter sib2, iclass 3, count 2 2006.259.07:45:42.38#ibcon#flushed, iclass 3, count 2 2006.259.07:45:42.38#ibcon#about to write, iclass 3, count 2 2006.259.07:45:42.38#ibcon#wrote, iclass 3, count 2 2006.259.07:45:42.38#ibcon#about to read 3, iclass 3, count 2 2006.259.07:45:42.41#ibcon#read 3, iclass 3, count 2 2006.259.07:45:42.41#ibcon#about to read 4, iclass 3, count 2 2006.259.07:45:42.41#ibcon#read 4, iclass 3, count 2 2006.259.07:45:42.41#ibcon#about to read 5, iclass 3, count 2 2006.259.07:45:42.41#ibcon#read 5, iclass 3, count 2 2006.259.07:45:42.41#ibcon#about to read 6, iclass 3, count 2 2006.259.07:45:42.41#ibcon#read 6, iclass 3, count 2 2006.259.07:45:42.41#ibcon#end of sib2, iclass 3, count 2 2006.259.07:45:42.41#ibcon#*after write, iclass 3, count 2 2006.259.07:45:42.41#ibcon#*before return 0, iclass 3, count 2 2006.259.07:45:42.41#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.259.07:45:42.41#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.259.07:45:42.41#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.259.07:45:42.41#ibcon#ireg 7 cls_cnt 0 2006.259.07:45:42.41#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.259.07:45:42.53#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.259.07:45:42.53#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.259.07:45:42.53#ibcon#enter wrdev, iclass 3, count 0 2006.259.07:45:42.53#ibcon#first serial, iclass 3, count 0 2006.259.07:45:42.53#ibcon#enter sib2, iclass 3, count 0 2006.259.07:45:42.53#ibcon#flushed, iclass 3, count 0 2006.259.07:45:42.53#ibcon#about to write, iclass 3, count 0 2006.259.07:45:42.53#ibcon#wrote, iclass 3, count 0 2006.259.07:45:42.53#ibcon#about to read 3, iclass 3, count 0 2006.259.07:45:42.55#ibcon#read 3, iclass 3, count 0 2006.259.07:45:42.55#ibcon#about to read 4, iclass 3, count 0 2006.259.07:45:42.55#ibcon#read 4, iclass 3, count 0 2006.259.07:45:42.55#ibcon#about to read 5, iclass 3, count 0 2006.259.07:45:42.55#ibcon#read 5, iclass 3, count 0 2006.259.07:45:42.55#ibcon#about to read 6, iclass 3, count 0 2006.259.07:45:42.55#ibcon#read 6, iclass 3, count 0 2006.259.07:45:42.55#ibcon#end of sib2, iclass 3, count 0 2006.259.07:45:42.55#ibcon#*mode == 0, iclass 3, count 0 2006.259.07:45:42.55#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.259.07:45:42.55#ibcon#[27=USB\r\n] 2006.259.07:45:42.55#ibcon#*before write, iclass 3, count 0 2006.259.07:45:42.55#ibcon#enter sib2, iclass 3, count 0 2006.259.07:45:42.55#ibcon#flushed, iclass 3, count 0 2006.259.07:45:42.55#ibcon#about to write, iclass 3, count 0 2006.259.07:45:42.55#ibcon#wrote, iclass 3, count 0 2006.259.07:45:42.55#ibcon#about to read 3, iclass 3, count 0 2006.259.07:45:42.58#ibcon#read 3, iclass 3, count 0 2006.259.07:45:42.58#ibcon#about to read 4, iclass 3, count 0 2006.259.07:45:42.58#ibcon#read 4, iclass 3, count 0 2006.259.07:45:42.58#ibcon#about to read 5, iclass 3, count 0 2006.259.07:45:42.58#ibcon#read 5, iclass 3, count 0 2006.259.07:45:42.58#ibcon#about to read 6, iclass 3, count 0 2006.259.07:45:42.58#ibcon#read 6, iclass 3, count 0 2006.259.07:45:42.58#ibcon#end of sib2, iclass 3, count 0 2006.259.07:45:42.58#ibcon#*after write, iclass 3, count 0 2006.259.07:45:42.58#ibcon#*before return 0, iclass 3, count 0 2006.259.07:45:42.58#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.259.07:45:42.58#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.259.07:45:42.58#ibcon#about to clear, iclass 3 cls_cnt 0 2006.259.07:45:42.58#ibcon#cleared, iclass 3 cls_cnt 0 2006.259.07:45:42.58$vc4f8/vblo=4,712.99 2006.259.07:45:42.58#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.259.07:45:42.58#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.259.07:45:42.58#ibcon#ireg 17 cls_cnt 0 2006.259.07:45:42.58#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.259.07:45:42.58#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.259.07:45:42.58#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.259.07:45:42.58#ibcon#enter wrdev, iclass 5, count 0 2006.259.07:45:42.58#ibcon#first serial, iclass 5, count 0 2006.259.07:45:42.58#ibcon#enter sib2, iclass 5, count 0 2006.259.07:45:42.58#ibcon#flushed, iclass 5, count 0 2006.259.07:45:42.58#ibcon#about to write, iclass 5, count 0 2006.259.07:45:42.58#ibcon#wrote, iclass 5, count 0 2006.259.07:45:42.58#ibcon#about to read 3, iclass 5, count 0 2006.259.07:45:42.60#ibcon#read 3, iclass 5, count 0 2006.259.07:45:42.60#ibcon#about to read 4, iclass 5, count 0 2006.259.07:45:42.60#ibcon#read 4, iclass 5, count 0 2006.259.07:45:42.60#ibcon#about to read 5, iclass 5, count 0 2006.259.07:45:42.60#ibcon#read 5, iclass 5, count 0 2006.259.07:45:42.60#ibcon#about to read 6, iclass 5, count 0 2006.259.07:45:42.60#ibcon#read 6, iclass 5, count 0 2006.259.07:45:42.60#ibcon#end of sib2, iclass 5, count 0 2006.259.07:45:42.60#ibcon#*mode == 0, iclass 5, count 0 2006.259.07:45:42.60#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.259.07:45:42.60#ibcon#[28=FRQ=04,712.99\r\n] 2006.259.07:45:42.60#ibcon#*before write, iclass 5, count 0 2006.259.07:45:42.60#ibcon#enter sib2, iclass 5, count 0 2006.259.07:45:42.60#ibcon#flushed, iclass 5, count 0 2006.259.07:45:42.60#ibcon#about to write, iclass 5, count 0 2006.259.07:45:42.60#ibcon#wrote, iclass 5, count 0 2006.259.07:45:42.60#ibcon#about to read 3, iclass 5, count 0 2006.259.07:45:42.64#ibcon#read 3, iclass 5, count 0 2006.259.07:45:42.64#ibcon#about to read 4, iclass 5, count 0 2006.259.07:45:42.64#ibcon#read 4, iclass 5, count 0 2006.259.07:45:42.64#ibcon#about to read 5, iclass 5, count 0 2006.259.07:45:42.64#ibcon#read 5, iclass 5, count 0 2006.259.07:45:42.64#ibcon#about to read 6, iclass 5, count 0 2006.259.07:45:42.64#ibcon#read 6, iclass 5, count 0 2006.259.07:45:42.64#ibcon#end of sib2, iclass 5, count 0 2006.259.07:45:42.64#ibcon#*after write, iclass 5, count 0 2006.259.07:45:42.64#ibcon#*before return 0, iclass 5, count 0 2006.259.07:45:42.64#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.259.07:45:42.64#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.259.07:45:42.64#ibcon#about to clear, iclass 5 cls_cnt 0 2006.259.07:45:42.64#ibcon#cleared, iclass 5 cls_cnt 0 2006.259.07:45:42.64$vc4f8/vb=4,5 2006.259.07:45:42.64#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.259.07:45:42.64#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.259.07:45:42.64#ibcon#ireg 11 cls_cnt 2 2006.259.07:45:42.64#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.259.07:45:42.70#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.259.07:45:42.70#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.259.07:45:42.70#ibcon#enter wrdev, iclass 7, count 2 2006.259.07:45:42.70#ibcon#first serial, iclass 7, count 2 2006.259.07:45:42.70#ibcon#enter sib2, iclass 7, count 2 2006.259.07:45:42.70#ibcon#flushed, iclass 7, count 2 2006.259.07:45:42.70#ibcon#about to write, iclass 7, count 2 2006.259.07:45:42.70#ibcon#wrote, iclass 7, count 2 2006.259.07:45:42.70#ibcon#about to read 3, iclass 7, count 2 2006.259.07:45:42.72#ibcon#read 3, iclass 7, count 2 2006.259.07:45:42.72#ibcon#about to read 4, iclass 7, count 2 2006.259.07:45:42.72#ibcon#read 4, iclass 7, count 2 2006.259.07:45:42.72#ibcon#about to read 5, iclass 7, count 2 2006.259.07:45:42.72#ibcon#read 5, iclass 7, count 2 2006.259.07:45:42.72#ibcon#about to read 6, iclass 7, count 2 2006.259.07:45:42.72#ibcon#read 6, iclass 7, count 2 2006.259.07:45:42.72#ibcon#end of sib2, iclass 7, count 2 2006.259.07:45:42.72#ibcon#*mode == 0, iclass 7, count 2 2006.259.07:45:42.72#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.259.07:45:42.72#ibcon#[27=AT04-05\r\n] 2006.259.07:45:42.72#ibcon#*before write, iclass 7, count 2 2006.259.07:45:42.72#ibcon#enter sib2, iclass 7, count 2 2006.259.07:45:42.72#ibcon#flushed, iclass 7, count 2 2006.259.07:45:42.72#ibcon#about to write, iclass 7, count 2 2006.259.07:45:42.72#ibcon#wrote, iclass 7, count 2 2006.259.07:45:42.72#ibcon#about to read 3, iclass 7, count 2 2006.259.07:45:42.75#ibcon#read 3, iclass 7, count 2 2006.259.07:45:42.75#ibcon#about to read 4, iclass 7, count 2 2006.259.07:45:42.75#ibcon#read 4, iclass 7, count 2 2006.259.07:45:42.75#ibcon#about to read 5, iclass 7, count 2 2006.259.07:45:42.75#ibcon#read 5, iclass 7, count 2 2006.259.07:45:42.75#ibcon#about to read 6, iclass 7, count 2 2006.259.07:45:42.75#ibcon#read 6, iclass 7, count 2 2006.259.07:45:42.75#ibcon#end of sib2, iclass 7, count 2 2006.259.07:45:42.75#ibcon#*after write, iclass 7, count 2 2006.259.07:45:42.75#ibcon#*before return 0, iclass 7, count 2 2006.259.07:45:42.75#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.259.07:45:42.75#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.259.07:45:42.75#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.259.07:45:42.75#ibcon#ireg 7 cls_cnt 0 2006.259.07:45:42.75#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.259.07:45:42.87#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.259.07:45:42.87#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.259.07:45:42.87#ibcon#enter wrdev, iclass 7, count 0 2006.259.07:45:42.87#ibcon#first serial, iclass 7, count 0 2006.259.07:45:42.87#ibcon#enter sib2, iclass 7, count 0 2006.259.07:45:42.87#ibcon#flushed, iclass 7, count 0 2006.259.07:45:42.87#ibcon#about to write, iclass 7, count 0 2006.259.07:45:42.87#ibcon#wrote, iclass 7, count 0 2006.259.07:45:42.87#ibcon#about to read 3, iclass 7, count 0 2006.259.07:45:42.89#ibcon#read 3, iclass 7, count 0 2006.259.07:45:42.89#ibcon#about to read 4, iclass 7, count 0 2006.259.07:45:42.89#ibcon#read 4, iclass 7, count 0 2006.259.07:45:42.89#ibcon#about to read 5, iclass 7, count 0 2006.259.07:45:42.89#ibcon#read 5, iclass 7, count 0 2006.259.07:45:42.89#ibcon#about to read 6, iclass 7, count 0 2006.259.07:45:42.89#ibcon#read 6, iclass 7, count 0 2006.259.07:45:42.89#ibcon#end of sib2, iclass 7, count 0 2006.259.07:45:42.89#ibcon#*mode == 0, iclass 7, count 0 2006.259.07:45:42.89#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.259.07:45:42.89#ibcon#[27=USB\r\n] 2006.259.07:45:42.89#ibcon#*before write, iclass 7, count 0 2006.259.07:45:42.89#ibcon#enter sib2, iclass 7, count 0 2006.259.07:45:42.89#ibcon#flushed, iclass 7, count 0 2006.259.07:45:42.89#ibcon#about to write, iclass 7, count 0 2006.259.07:45:42.89#ibcon#wrote, iclass 7, count 0 2006.259.07:45:42.89#ibcon#about to read 3, iclass 7, count 0 2006.259.07:45:42.92#ibcon#read 3, iclass 7, count 0 2006.259.07:45:42.92#ibcon#about to read 4, iclass 7, count 0 2006.259.07:45:42.92#ibcon#read 4, iclass 7, count 0 2006.259.07:45:42.92#ibcon#about to read 5, iclass 7, count 0 2006.259.07:45:42.92#ibcon#read 5, iclass 7, count 0 2006.259.07:45:42.92#ibcon#about to read 6, iclass 7, count 0 2006.259.07:45:42.92#ibcon#read 6, iclass 7, count 0 2006.259.07:45:42.92#ibcon#end of sib2, iclass 7, count 0 2006.259.07:45:42.92#ibcon#*after write, iclass 7, count 0 2006.259.07:45:42.92#ibcon#*before return 0, iclass 7, count 0 2006.259.07:45:42.92#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.259.07:45:42.92#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.259.07:45:42.92#ibcon#about to clear, iclass 7 cls_cnt 0 2006.259.07:45:42.92#ibcon#cleared, iclass 7 cls_cnt 0 2006.259.07:45:42.92$vc4f8/vblo=5,744.99 2006.259.07:45:42.92#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.259.07:45:42.92#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.259.07:45:42.92#ibcon#ireg 17 cls_cnt 0 2006.259.07:45:42.92#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.259.07:45:42.92#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.259.07:45:42.92#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.259.07:45:42.92#ibcon#enter wrdev, iclass 11, count 0 2006.259.07:45:42.92#ibcon#first serial, iclass 11, count 0 2006.259.07:45:42.92#ibcon#enter sib2, iclass 11, count 0 2006.259.07:45:42.92#ibcon#flushed, iclass 11, count 0 2006.259.07:45:42.92#ibcon#about to write, iclass 11, count 0 2006.259.07:45:42.92#ibcon#wrote, iclass 11, count 0 2006.259.07:45:42.92#ibcon#about to read 3, iclass 11, count 0 2006.259.07:45:42.94#ibcon#read 3, iclass 11, count 0 2006.259.07:45:42.94#ibcon#about to read 4, iclass 11, count 0 2006.259.07:45:42.94#ibcon#read 4, iclass 11, count 0 2006.259.07:45:42.94#ibcon#about to read 5, iclass 11, count 0 2006.259.07:45:42.94#ibcon#read 5, iclass 11, count 0 2006.259.07:45:42.94#ibcon#about to read 6, iclass 11, count 0 2006.259.07:45:42.94#ibcon#read 6, iclass 11, count 0 2006.259.07:45:42.94#ibcon#end of sib2, iclass 11, count 0 2006.259.07:45:42.94#ibcon#*mode == 0, iclass 11, count 0 2006.259.07:45:42.94#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.259.07:45:42.94#ibcon#[28=FRQ=05,744.99\r\n] 2006.259.07:45:42.94#ibcon#*before write, iclass 11, count 0 2006.259.07:45:42.94#ibcon#enter sib2, iclass 11, count 0 2006.259.07:45:42.94#ibcon#flushed, iclass 11, count 0 2006.259.07:45:42.94#ibcon#about to write, iclass 11, count 0 2006.259.07:45:42.94#ibcon#wrote, iclass 11, count 0 2006.259.07:45:42.94#ibcon#about to read 3, iclass 11, count 0 2006.259.07:45:42.98#ibcon#read 3, iclass 11, count 0 2006.259.07:45:42.98#ibcon#about to read 4, iclass 11, count 0 2006.259.07:45:42.98#ibcon#read 4, iclass 11, count 0 2006.259.07:45:42.98#ibcon#about to read 5, iclass 11, count 0 2006.259.07:45:42.98#ibcon#read 5, iclass 11, count 0 2006.259.07:45:42.98#ibcon#about to read 6, iclass 11, count 0 2006.259.07:45:42.98#ibcon#read 6, iclass 11, count 0 2006.259.07:45:42.98#ibcon#end of sib2, iclass 11, count 0 2006.259.07:45:42.98#ibcon#*after write, iclass 11, count 0 2006.259.07:45:42.98#ibcon#*before return 0, iclass 11, count 0 2006.259.07:45:42.98#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.259.07:45:42.98#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.259.07:45:42.98#ibcon#about to clear, iclass 11 cls_cnt 0 2006.259.07:45:42.98#ibcon#cleared, iclass 11 cls_cnt 0 2006.259.07:45:42.98$vc4f8/vb=5,4 2006.259.07:45:42.98#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.259.07:45:42.98#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.259.07:45:42.98#ibcon#ireg 11 cls_cnt 2 2006.259.07:45:42.98#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.259.07:45:43.04#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.259.07:45:43.04#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.259.07:45:43.04#ibcon#enter wrdev, iclass 13, count 2 2006.259.07:45:43.04#ibcon#first serial, iclass 13, count 2 2006.259.07:45:43.04#ibcon#enter sib2, iclass 13, count 2 2006.259.07:45:43.04#ibcon#flushed, iclass 13, count 2 2006.259.07:45:43.04#ibcon#about to write, iclass 13, count 2 2006.259.07:45:43.04#ibcon#wrote, iclass 13, count 2 2006.259.07:45:43.04#ibcon#about to read 3, iclass 13, count 2 2006.259.07:45:43.06#ibcon#read 3, iclass 13, count 2 2006.259.07:45:43.06#ibcon#about to read 4, iclass 13, count 2 2006.259.07:45:43.06#ibcon#read 4, iclass 13, count 2 2006.259.07:45:43.06#ibcon#about to read 5, iclass 13, count 2 2006.259.07:45:43.06#ibcon#read 5, iclass 13, count 2 2006.259.07:45:43.06#ibcon#about to read 6, iclass 13, count 2 2006.259.07:45:43.06#ibcon#read 6, iclass 13, count 2 2006.259.07:45:43.06#ibcon#end of sib2, iclass 13, count 2 2006.259.07:45:43.06#ibcon#*mode == 0, iclass 13, count 2 2006.259.07:45:43.06#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.259.07:45:43.06#ibcon#[27=AT05-04\r\n] 2006.259.07:45:43.06#ibcon#*before write, iclass 13, count 2 2006.259.07:45:43.06#ibcon#enter sib2, iclass 13, count 2 2006.259.07:45:43.06#ibcon#flushed, iclass 13, count 2 2006.259.07:45:43.06#ibcon#about to write, iclass 13, count 2 2006.259.07:45:43.06#ibcon#wrote, iclass 13, count 2 2006.259.07:45:43.06#ibcon#about to read 3, iclass 13, count 2 2006.259.07:45:43.09#ibcon#read 3, iclass 13, count 2 2006.259.07:45:43.09#ibcon#about to read 4, iclass 13, count 2 2006.259.07:45:43.09#ibcon#read 4, iclass 13, count 2 2006.259.07:45:43.09#ibcon#about to read 5, iclass 13, count 2 2006.259.07:45:43.09#ibcon#read 5, iclass 13, count 2 2006.259.07:45:43.09#ibcon#about to read 6, iclass 13, count 2 2006.259.07:45:43.09#ibcon#read 6, iclass 13, count 2 2006.259.07:45:43.09#ibcon#end of sib2, iclass 13, count 2 2006.259.07:45:43.09#ibcon#*after write, iclass 13, count 2 2006.259.07:45:43.09#ibcon#*before return 0, iclass 13, count 2 2006.259.07:45:43.09#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.259.07:45:43.09#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.259.07:45:43.09#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.259.07:45:43.09#ibcon#ireg 7 cls_cnt 0 2006.259.07:45:43.09#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.259.07:45:43.21#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.259.07:45:43.21#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.259.07:45:43.21#ibcon#enter wrdev, iclass 13, count 0 2006.259.07:45:43.21#ibcon#first serial, iclass 13, count 0 2006.259.07:45:43.21#ibcon#enter sib2, iclass 13, count 0 2006.259.07:45:43.21#ibcon#flushed, iclass 13, count 0 2006.259.07:45:43.21#ibcon#about to write, iclass 13, count 0 2006.259.07:45:43.21#ibcon#wrote, iclass 13, count 0 2006.259.07:45:43.21#ibcon#about to read 3, iclass 13, count 0 2006.259.07:45:43.23#ibcon#read 3, iclass 13, count 0 2006.259.07:45:43.23#ibcon#about to read 4, iclass 13, count 0 2006.259.07:45:43.23#ibcon#read 4, iclass 13, count 0 2006.259.07:45:43.23#ibcon#about to read 5, iclass 13, count 0 2006.259.07:45:43.23#ibcon#read 5, iclass 13, count 0 2006.259.07:45:43.23#ibcon#about to read 6, iclass 13, count 0 2006.259.07:45:43.23#ibcon#read 6, iclass 13, count 0 2006.259.07:45:43.23#ibcon#end of sib2, iclass 13, count 0 2006.259.07:45:43.23#ibcon#*mode == 0, iclass 13, count 0 2006.259.07:45:43.23#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.259.07:45:43.23#ibcon#[27=USB\r\n] 2006.259.07:45:43.23#ibcon#*before write, iclass 13, count 0 2006.259.07:45:43.23#ibcon#enter sib2, iclass 13, count 0 2006.259.07:45:43.23#ibcon#flushed, iclass 13, count 0 2006.259.07:45:43.23#ibcon#about to write, iclass 13, count 0 2006.259.07:45:43.23#ibcon#wrote, iclass 13, count 0 2006.259.07:45:43.23#ibcon#about to read 3, iclass 13, count 0 2006.259.07:45:43.26#ibcon#read 3, iclass 13, count 0 2006.259.07:45:43.26#ibcon#about to read 4, iclass 13, count 0 2006.259.07:45:43.26#ibcon#read 4, iclass 13, count 0 2006.259.07:45:43.26#ibcon#about to read 5, iclass 13, count 0 2006.259.07:45:43.26#ibcon#read 5, iclass 13, count 0 2006.259.07:45:43.26#ibcon#about to read 6, iclass 13, count 0 2006.259.07:45:43.26#ibcon#read 6, iclass 13, count 0 2006.259.07:45:43.26#ibcon#end of sib2, iclass 13, count 0 2006.259.07:45:43.26#ibcon#*after write, iclass 13, count 0 2006.259.07:45:43.26#ibcon#*before return 0, iclass 13, count 0 2006.259.07:45:43.26#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.259.07:45:43.26#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.259.07:45:43.26#ibcon#about to clear, iclass 13 cls_cnt 0 2006.259.07:45:43.26#ibcon#cleared, iclass 13 cls_cnt 0 2006.259.07:45:43.26$vc4f8/vblo=6,752.99 2006.259.07:45:43.26#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.259.07:45:43.26#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.259.07:45:43.26#ibcon#ireg 17 cls_cnt 0 2006.259.07:45:43.26#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.259.07:45:43.26#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.259.07:45:43.26#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.259.07:45:43.26#ibcon#enter wrdev, iclass 15, count 0 2006.259.07:45:43.26#ibcon#first serial, iclass 15, count 0 2006.259.07:45:43.26#ibcon#enter sib2, iclass 15, count 0 2006.259.07:45:43.26#ibcon#flushed, iclass 15, count 0 2006.259.07:45:43.26#ibcon#about to write, iclass 15, count 0 2006.259.07:45:43.26#ibcon#wrote, iclass 15, count 0 2006.259.07:45:43.26#ibcon#about to read 3, iclass 15, count 0 2006.259.07:45:43.28#ibcon#read 3, iclass 15, count 0 2006.259.07:45:43.28#ibcon#about to read 4, iclass 15, count 0 2006.259.07:45:43.28#ibcon#read 4, iclass 15, count 0 2006.259.07:45:43.28#ibcon#about to read 5, iclass 15, count 0 2006.259.07:45:43.28#ibcon#read 5, iclass 15, count 0 2006.259.07:45:43.28#ibcon#about to read 6, iclass 15, count 0 2006.259.07:45:43.28#ibcon#read 6, iclass 15, count 0 2006.259.07:45:43.28#ibcon#end of sib2, iclass 15, count 0 2006.259.07:45:43.28#ibcon#*mode == 0, iclass 15, count 0 2006.259.07:45:43.28#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.259.07:45:43.28#ibcon#[28=FRQ=06,752.99\r\n] 2006.259.07:45:43.28#ibcon#*before write, iclass 15, count 0 2006.259.07:45:43.28#ibcon#enter sib2, iclass 15, count 0 2006.259.07:45:43.28#ibcon#flushed, iclass 15, count 0 2006.259.07:45:43.28#ibcon#about to write, iclass 15, count 0 2006.259.07:45:43.28#ibcon#wrote, iclass 15, count 0 2006.259.07:45:43.28#ibcon#about to read 3, iclass 15, count 0 2006.259.07:45:43.31#abcon#<5=/04 2.2 4.4 22.24 851012.9\r\n> 2006.259.07:45:43.32#ibcon#read 3, iclass 15, count 0 2006.259.07:45:43.32#ibcon#about to read 4, iclass 15, count 0 2006.259.07:45:43.32#ibcon#read 4, iclass 15, count 0 2006.259.07:45:43.32#ibcon#about to read 5, iclass 15, count 0 2006.259.07:45:43.32#ibcon#read 5, iclass 15, count 0 2006.259.07:45:43.32#ibcon#about to read 6, iclass 15, count 0 2006.259.07:45:43.32#ibcon#read 6, iclass 15, count 0 2006.259.07:45:43.32#ibcon#end of sib2, iclass 15, count 0 2006.259.07:45:43.32#ibcon#*after write, iclass 15, count 0 2006.259.07:45:43.32#ibcon#*before return 0, iclass 15, count 0 2006.259.07:45:43.32#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.259.07:45:43.32#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.259.07:45:43.32#ibcon#about to clear, iclass 15 cls_cnt 0 2006.259.07:45:43.32#ibcon#cleared, iclass 15 cls_cnt 0 2006.259.07:45:43.32$vc4f8/vb=6,4 2006.259.07:45:43.32#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.259.07:45:43.32#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.259.07:45:43.32#ibcon#ireg 11 cls_cnt 2 2006.259.07:45:43.32#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.259.07:45:43.33#abcon#{5=INTERFACE CLEAR} 2006.259.07:45:43.38#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.259.07:45:43.38#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.259.07:45:43.38#ibcon#enter wrdev, iclass 20, count 2 2006.259.07:45:43.38#ibcon#first serial, iclass 20, count 2 2006.259.07:45:43.38#ibcon#enter sib2, iclass 20, count 2 2006.259.07:45:43.38#ibcon#flushed, iclass 20, count 2 2006.259.07:45:43.38#ibcon#about to write, iclass 20, count 2 2006.259.07:45:43.38#ibcon#wrote, iclass 20, count 2 2006.259.07:45:43.38#ibcon#about to read 3, iclass 20, count 2 2006.259.07:45:43.39#abcon#[5=S1D000X0/0*\r\n] 2006.259.07:45:43.40#ibcon#read 3, iclass 20, count 2 2006.259.07:45:43.40#ibcon#about to read 4, iclass 20, count 2 2006.259.07:45:43.40#ibcon#read 4, iclass 20, count 2 2006.259.07:45:43.40#ibcon#about to read 5, iclass 20, count 2 2006.259.07:45:43.40#ibcon#read 5, iclass 20, count 2 2006.259.07:45:43.40#ibcon#about to read 6, iclass 20, count 2 2006.259.07:45:43.40#ibcon#read 6, iclass 20, count 2 2006.259.07:45:43.40#ibcon#end of sib2, iclass 20, count 2 2006.259.07:45:43.40#ibcon#*mode == 0, iclass 20, count 2 2006.259.07:45:43.40#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.259.07:45:43.40#ibcon#[27=AT06-04\r\n] 2006.259.07:45:43.40#ibcon#*before write, iclass 20, count 2 2006.259.07:45:43.40#ibcon#enter sib2, iclass 20, count 2 2006.259.07:45:43.40#ibcon#flushed, iclass 20, count 2 2006.259.07:45:43.40#ibcon#about to write, iclass 20, count 2 2006.259.07:45:43.40#ibcon#wrote, iclass 20, count 2 2006.259.07:45:43.40#ibcon#about to read 3, iclass 20, count 2 2006.259.07:45:43.43#ibcon#read 3, iclass 20, count 2 2006.259.07:45:43.43#ibcon#about to read 4, iclass 20, count 2 2006.259.07:45:43.43#ibcon#read 4, iclass 20, count 2 2006.259.07:45:43.43#ibcon#about to read 5, iclass 20, count 2 2006.259.07:45:43.43#ibcon#read 5, iclass 20, count 2 2006.259.07:45:43.43#ibcon#about to read 6, iclass 20, count 2 2006.259.07:45:43.43#ibcon#read 6, iclass 20, count 2 2006.259.07:45:43.43#ibcon#end of sib2, iclass 20, count 2 2006.259.07:45:43.43#ibcon#*after write, iclass 20, count 2 2006.259.07:45:43.43#ibcon#*before return 0, iclass 20, count 2 2006.259.07:45:43.43#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.259.07:45:43.43#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.259.07:45:43.43#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.259.07:45:43.43#ibcon#ireg 7 cls_cnt 0 2006.259.07:45:43.43#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.259.07:45:43.55#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.259.07:45:43.55#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.259.07:45:43.55#ibcon#enter wrdev, iclass 20, count 0 2006.259.07:45:43.55#ibcon#first serial, iclass 20, count 0 2006.259.07:45:43.55#ibcon#enter sib2, iclass 20, count 0 2006.259.07:45:43.55#ibcon#flushed, iclass 20, count 0 2006.259.07:45:43.55#ibcon#about to write, iclass 20, count 0 2006.259.07:45:43.55#ibcon#wrote, iclass 20, count 0 2006.259.07:45:43.55#ibcon#about to read 3, iclass 20, count 0 2006.259.07:45:43.57#ibcon#read 3, iclass 20, count 0 2006.259.07:45:43.57#ibcon#about to read 4, iclass 20, count 0 2006.259.07:45:43.57#ibcon#read 4, iclass 20, count 0 2006.259.07:45:43.57#ibcon#about to read 5, iclass 20, count 0 2006.259.07:45:43.57#ibcon#read 5, iclass 20, count 0 2006.259.07:45:43.57#ibcon#about to read 6, iclass 20, count 0 2006.259.07:45:43.57#ibcon#read 6, iclass 20, count 0 2006.259.07:45:43.57#ibcon#end of sib2, iclass 20, count 0 2006.259.07:45:43.57#ibcon#*mode == 0, iclass 20, count 0 2006.259.07:45:43.57#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.259.07:45:43.57#ibcon#[27=USB\r\n] 2006.259.07:45:43.57#ibcon#*before write, iclass 20, count 0 2006.259.07:45:43.57#ibcon#enter sib2, iclass 20, count 0 2006.259.07:45:43.57#ibcon#flushed, iclass 20, count 0 2006.259.07:45:43.57#ibcon#about to write, iclass 20, count 0 2006.259.07:45:43.57#ibcon#wrote, iclass 20, count 0 2006.259.07:45:43.57#ibcon#about to read 3, iclass 20, count 0 2006.259.07:45:43.60#ibcon#read 3, iclass 20, count 0 2006.259.07:45:43.60#ibcon#about to read 4, iclass 20, count 0 2006.259.07:45:43.60#ibcon#read 4, iclass 20, count 0 2006.259.07:45:43.60#ibcon#about to read 5, iclass 20, count 0 2006.259.07:45:43.60#ibcon#read 5, iclass 20, count 0 2006.259.07:45:43.60#ibcon#about to read 6, iclass 20, count 0 2006.259.07:45:43.60#ibcon#read 6, iclass 20, count 0 2006.259.07:45:43.60#ibcon#end of sib2, iclass 20, count 0 2006.259.07:45:43.60#ibcon#*after write, iclass 20, count 0 2006.259.07:45:43.60#ibcon#*before return 0, iclass 20, count 0 2006.259.07:45:43.60#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.259.07:45:43.60#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.259.07:45:43.60#ibcon#about to clear, iclass 20 cls_cnt 0 2006.259.07:45:43.60#ibcon#cleared, iclass 20 cls_cnt 0 2006.259.07:45:43.60$vc4f8/vabw=wide 2006.259.07:45:43.60#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.259.07:45:43.60#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.259.07:45:43.60#ibcon#ireg 8 cls_cnt 0 2006.259.07:45:43.60#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.259.07:45:43.60#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.259.07:45:43.60#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.259.07:45:43.60#ibcon#enter wrdev, iclass 23, count 0 2006.259.07:45:43.60#ibcon#first serial, iclass 23, count 0 2006.259.07:45:43.60#ibcon#enter sib2, iclass 23, count 0 2006.259.07:45:43.60#ibcon#flushed, iclass 23, count 0 2006.259.07:45:43.60#ibcon#about to write, iclass 23, count 0 2006.259.07:45:43.60#ibcon#wrote, iclass 23, count 0 2006.259.07:45:43.60#ibcon#about to read 3, iclass 23, count 0 2006.259.07:45:43.62#ibcon#read 3, iclass 23, count 0 2006.259.07:45:43.62#ibcon#about to read 4, iclass 23, count 0 2006.259.07:45:43.62#ibcon#read 4, iclass 23, count 0 2006.259.07:45:43.62#ibcon#about to read 5, iclass 23, count 0 2006.259.07:45:43.62#ibcon#read 5, iclass 23, count 0 2006.259.07:45:43.62#ibcon#about to read 6, iclass 23, count 0 2006.259.07:45:43.62#ibcon#read 6, iclass 23, count 0 2006.259.07:45:43.62#ibcon#end of sib2, iclass 23, count 0 2006.259.07:45:43.62#ibcon#*mode == 0, iclass 23, count 0 2006.259.07:45:43.62#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.259.07:45:43.62#ibcon#[25=BW32\r\n] 2006.259.07:45:43.62#ibcon#*before write, iclass 23, count 0 2006.259.07:45:43.62#ibcon#enter sib2, iclass 23, count 0 2006.259.07:45:43.62#ibcon#flushed, iclass 23, count 0 2006.259.07:45:43.62#ibcon#about to write, iclass 23, count 0 2006.259.07:45:43.62#ibcon#wrote, iclass 23, count 0 2006.259.07:45:43.62#ibcon#about to read 3, iclass 23, count 0 2006.259.07:45:43.65#ibcon#read 3, iclass 23, count 0 2006.259.07:45:43.65#ibcon#about to read 4, iclass 23, count 0 2006.259.07:45:43.65#ibcon#read 4, iclass 23, count 0 2006.259.07:45:43.65#ibcon#about to read 5, iclass 23, count 0 2006.259.07:45:43.65#ibcon#read 5, iclass 23, count 0 2006.259.07:45:43.65#ibcon#about to read 6, iclass 23, count 0 2006.259.07:45:43.65#ibcon#read 6, iclass 23, count 0 2006.259.07:45:43.65#ibcon#end of sib2, iclass 23, count 0 2006.259.07:45:43.65#ibcon#*after write, iclass 23, count 0 2006.259.07:45:43.65#ibcon#*before return 0, iclass 23, count 0 2006.259.07:45:43.65#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.259.07:45:43.65#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.259.07:45:43.65#ibcon#about to clear, iclass 23 cls_cnt 0 2006.259.07:45:43.65#ibcon#cleared, iclass 23 cls_cnt 0 2006.259.07:45:43.65$vc4f8/vbbw=wide 2006.259.07:45:43.65#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.259.07:45:43.65#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.259.07:45:43.65#ibcon#ireg 8 cls_cnt 0 2006.259.07:45:43.65#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.259.07:45:43.72#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.259.07:45:43.72#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.259.07:45:43.72#ibcon#enter wrdev, iclass 25, count 0 2006.259.07:45:43.72#ibcon#first serial, iclass 25, count 0 2006.259.07:45:43.72#ibcon#enter sib2, iclass 25, count 0 2006.259.07:45:43.72#ibcon#flushed, iclass 25, count 0 2006.259.07:45:43.72#ibcon#about to write, iclass 25, count 0 2006.259.07:45:43.72#ibcon#wrote, iclass 25, count 0 2006.259.07:45:43.72#ibcon#about to read 3, iclass 25, count 0 2006.259.07:45:43.74#ibcon#read 3, iclass 25, count 0 2006.259.07:45:43.74#ibcon#about to read 4, iclass 25, count 0 2006.259.07:45:43.74#ibcon#read 4, iclass 25, count 0 2006.259.07:45:43.74#ibcon#about to read 5, iclass 25, count 0 2006.259.07:45:43.74#ibcon#read 5, iclass 25, count 0 2006.259.07:45:43.74#ibcon#about to read 6, iclass 25, count 0 2006.259.07:45:43.74#ibcon#read 6, iclass 25, count 0 2006.259.07:45:43.74#ibcon#end of sib2, iclass 25, count 0 2006.259.07:45:43.74#ibcon#*mode == 0, iclass 25, count 0 2006.259.07:45:43.74#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.259.07:45:43.74#ibcon#[27=BW32\r\n] 2006.259.07:45:43.74#ibcon#*before write, iclass 25, count 0 2006.259.07:45:43.74#ibcon#enter sib2, iclass 25, count 0 2006.259.07:45:43.74#ibcon#flushed, iclass 25, count 0 2006.259.07:45:43.74#ibcon#about to write, iclass 25, count 0 2006.259.07:45:43.74#ibcon#wrote, iclass 25, count 0 2006.259.07:45:43.74#ibcon#about to read 3, iclass 25, count 0 2006.259.07:45:43.77#ibcon#read 3, iclass 25, count 0 2006.259.07:45:43.77#ibcon#about to read 4, iclass 25, count 0 2006.259.07:45:43.77#ibcon#read 4, iclass 25, count 0 2006.259.07:45:43.77#ibcon#about to read 5, iclass 25, count 0 2006.259.07:45:43.77#ibcon#read 5, iclass 25, count 0 2006.259.07:45:43.77#ibcon#about to read 6, iclass 25, count 0 2006.259.07:45:43.77#ibcon#read 6, iclass 25, count 0 2006.259.07:45:43.77#ibcon#end of sib2, iclass 25, count 0 2006.259.07:45:43.77#ibcon#*after write, iclass 25, count 0 2006.259.07:45:43.77#ibcon#*before return 0, iclass 25, count 0 2006.259.07:45:43.77#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.259.07:45:43.77#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.259.07:45:43.77#ibcon#about to clear, iclass 25 cls_cnt 0 2006.259.07:45:43.77#ibcon#cleared, iclass 25 cls_cnt 0 2006.259.07:45:43.77$4f8m12a/ifd4f 2006.259.07:45:43.77$ifd4f/lo= 2006.259.07:45:43.77$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.259.07:45:43.77$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.259.07:45:43.77$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.259.07:45:43.77$ifd4f/patch= 2006.259.07:45:43.77$ifd4f/patch=lo1,a1,a2,a3,a4 2006.259.07:45:43.77$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.259.07:45:43.77$ifd4f/patch=lo3,a5,a6,a7,a8 2006.259.07:45:43.77$4f8m12a/"form=m,16.000,1:2 2006.259.07:45:43.77$4f8m12a/"tpicd 2006.259.07:45:43.77$4f8m12a/echo=off 2006.259.07:45:43.77$4f8m12a/xlog=off 2006.259.07:45:43.77:!2006.259.07:46:10 2006.259.07:45:56.14#trakl#Source acquired 2006.259.07:45:58.14#flagr#flagr/antenna,acquired 2006.259.07:46:10.00:preob 2006.259.07:46:11.14/onsource/TRACKING 2006.259.07:46:11.14:!2006.259.07:46:20 2006.259.07:46:20.00:data_valid=on 2006.259.07:46:20.00:midob 2006.259.07:46:20.14/onsource/TRACKING 2006.259.07:46:20.14/wx/22.23,1012.9,85 2006.259.07:46:20.21/cable/+6.4588E-03 2006.259.07:46:21.30/va/01,08,usb,yes,31,32 2006.259.07:46:21.30/va/02,07,usb,yes,30,32 2006.259.07:46:21.30/va/03,08,usb,yes,23,23 2006.259.07:46:21.30/va/04,07,usb,yes,32,34 2006.259.07:46:21.30/va/05,07,usb,yes,35,37 2006.259.07:46:21.30/va/06,06,usb,yes,34,34 2006.259.07:46:21.30/va/07,06,usb,yes,35,35 2006.259.07:46:21.30/va/08,06,usb,yes,37,37 2006.259.07:46:21.53/valo/01,532.99,yes,locked 2006.259.07:46:21.53/valo/02,572.99,yes,locked 2006.259.07:46:21.53/valo/03,672.99,yes,locked 2006.259.07:46:21.53/valo/04,832.99,yes,locked 2006.259.07:46:21.53/valo/05,652.99,yes,locked 2006.259.07:46:21.53/valo/06,772.99,yes,locked 2006.259.07:46:21.53/valo/07,832.99,yes,locked 2006.259.07:46:21.53/valo/08,852.99,yes,locked 2006.259.07:46:22.62/vb/01,04,usb,yes,30,29 2006.259.07:46:22.62/vb/02,05,usb,yes,28,29 2006.259.07:46:22.62/vb/03,04,usb,yes,28,32 2006.259.07:46:22.62/vb/04,05,usb,yes,26,26 2006.259.07:46:22.62/vb/05,04,usb,yes,27,31 2006.259.07:46:22.62/vb/06,04,usb,yes,28,31 2006.259.07:46:22.62/vb/07,04,usb,yes,31,31 2006.259.07:46:22.62/vb/08,04,usb,yes,28,32 2006.259.07:46:22.86/vblo/01,632.99,yes,locked 2006.259.07:46:22.86/vblo/02,640.99,yes,locked 2006.259.07:46:22.86/vblo/03,656.99,yes,locked 2006.259.07:46:22.86/vblo/04,712.99,yes,locked 2006.259.07:46:22.86/vblo/05,744.99,yes,locked 2006.259.07:46:22.86/vblo/06,752.99,yes,locked 2006.259.07:46:22.86/vblo/07,734.99,yes,locked 2006.259.07:46:22.86/vblo/08,744.99,yes,locked 2006.259.07:46:23.01/vabw/8 2006.259.07:46:23.16/vbbw/8 2006.259.07:46:23.25/xfe/off,on,15.0 2006.259.07:46:23.62/ifatt/23,28,28,28 2006.259.07:46:24.08/fmout-gps/S +4.49E-07 2006.259.07:46:24.12:!2006.259.07:47:20 2006.259.07:47:20.00:data_valid=off 2006.259.07:47:20.00:postob 2006.259.07:47:20.11/cable/+6.4596E-03 2006.259.07:47:20.11/wx/22.23,1013.0,86 2006.259.07:47:21.08/fmout-gps/S +4.51E-07 2006.259.07:47:21.08:scan_name=259-0748,k06259,60 2006.259.07:47:21.08:source=4c39.25,092703.01,390220.9,2000.0,ccw 2006.259.07:47:21.16#flagr#flagr/antenna,new-source 2006.259.07:47:22.14:checkk5 2006.259.07:47:22.56/chk_autoobs//k5ts1/ autoobs is running! 2006.259.07:47:22.96/chk_autoobs//k5ts2/ autoobs is running! 2006.259.07:47:23.36/chk_autoobs//k5ts3/ autoobs is running! 2006.259.07:47:24.06/chk_autoobs//k5ts4/ autoobs is running! 2006.259.07:47:24.46/chk_obsdata//k5ts1/T2590746??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.259.07:47:25.12/chk_obsdata//k5ts2/T2590746??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.259.07:47:25.56/chk_obsdata//k5ts3/T2590746??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.259.07:47:25.95/chk_obsdata//k5ts4/T2590746??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.259.07:47:26.89/k5log//k5ts1_log_newline 2006.259.07:47:27.66/k5log//k5ts2_log_newline 2006.259.07:47:28.65/k5log//k5ts3_log_newline 2006.259.07:47:29.38/k5log//k5ts4_log_newline 2006.259.07:47:29.40/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.259.07:47:29.41:4f8m12a=1 2006.259.07:47:29.41$4f8m12a/echo=on 2006.259.07:47:29.41$4f8m12a/pcalon 2006.259.07:47:29.41$pcalon/"no phase cal control is implemented here 2006.259.07:47:29.41$4f8m12a/"tpicd=stop 2006.259.07:47:29.41$4f8m12a/vc4f8 2006.259.07:47:29.41$vc4f8/valo=1,532.99 2006.259.07:47:29.41#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.259.07:47:29.41#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.259.07:47:29.41#ibcon#ireg 17 cls_cnt 0 2006.259.07:47:29.41#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.259.07:47:29.41#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.259.07:47:29.41#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.259.07:47:29.41#ibcon#enter wrdev, iclass 32, count 0 2006.259.07:47:29.41#ibcon#first serial, iclass 32, count 0 2006.259.07:47:29.41#ibcon#enter sib2, iclass 32, count 0 2006.259.07:47:29.41#ibcon#flushed, iclass 32, count 0 2006.259.07:47:29.41#ibcon#about to write, iclass 32, count 0 2006.259.07:47:29.41#ibcon#wrote, iclass 32, count 0 2006.259.07:47:29.41#ibcon#about to read 3, iclass 32, count 0 2006.259.07:47:29.45#ibcon#read 3, iclass 32, count 0 2006.259.07:47:29.45#ibcon#about to read 4, iclass 32, count 0 2006.259.07:47:29.45#ibcon#read 4, iclass 32, count 0 2006.259.07:47:29.45#ibcon#about to read 5, iclass 32, count 0 2006.259.07:47:29.45#ibcon#read 5, iclass 32, count 0 2006.259.07:47:29.45#ibcon#about to read 6, iclass 32, count 0 2006.259.07:47:29.45#ibcon#read 6, iclass 32, count 0 2006.259.07:47:29.45#ibcon#end of sib2, iclass 32, count 0 2006.259.07:47:29.45#ibcon#*mode == 0, iclass 32, count 0 2006.259.07:47:29.45#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.259.07:47:29.45#ibcon#[26=FRQ=01,532.99\r\n] 2006.259.07:47:29.45#ibcon#*before write, iclass 32, count 0 2006.259.07:47:29.45#ibcon#enter sib2, iclass 32, count 0 2006.259.07:47:29.45#ibcon#flushed, iclass 32, count 0 2006.259.07:47:29.45#ibcon#about to write, iclass 32, count 0 2006.259.07:47:29.45#ibcon#wrote, iclass 32, count 0 2006.259.07:47:29.45#ibcon#about to read 3, iclass 32, count 0 2006.259.07:47:29.50#ibcon#read 3, iclass 32, count 0 2006.259.07:47:29.50#ibcon#about to read 4, iclass 32, count 0 2006.259.07:47:29.50#ibcon#read 4, iclass 32, count 0 2006.259.07:47:29.50#ibcon#about to read 5, iclass 32, count 0 2006.259.07:47:29.50#ibcon#read 5, iclass 32, count 0 2006.259.07:47:29.50#ibcon#about to read 6, iclass 32, count 0 2006.259.07:47:29.50#ibcon#read 6, iclass 32, count 0 2006.259.07:47:29.50#ibcon#end of sib2, iclass 32, count 0 2006.259.07:47:29.50#ibcon#*after write, iclass 32, count 0 2006.259.07:47:29.50#ibcon#*before return 0, iclass 32, count 0 2006.259.07:47:29.50#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.259.07:47:29.50#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.259.07:47:29.50#ibcon#about to clear, iclass 32 cls_cnt 0 2006.259.07:47:29.50#ibcon#cleared, iclass 32 cls_cnt 0 2006.259.07:47:29.50$vc4f8/va=1,8 2006.259.07:47:29.50#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.259.07:47:29.50#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.259.07:47:29.50#ibcon#ireg 11 cls_cnt 2 2006.259.07:47:29.50#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.259.07:47:29.50#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.259.07:47:29.50#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.259.07:47:29.50#ibcon#enter wrdev, iclass 34, count 2 2006.259.07:47:29.50#ibcon#first serial, iclass 34, count 2 2006.259.07:47:29.50#ibcon#enter sib2, iclass 34, count 2 2006.259.07:47:29.50#ibcon#flushed, iclass 34, count 2 2006.259.07:47:29.50#ibcon#about to write, iclass 34, count 2 2006.259.07:47:29.50#ibcon#wrote, iclass 34, count 2 2006.259.07:47:29.50#ibcon#about to read 3, iclass 34, count 2 2006.259.07:47:29.52#ibcon#read 3, iclass 34, count 2 2006.259.07:47:29.52#ibcon#about to read 4, iclass 34, count 2 2006.259.07:47:29.52#ibcon#read 4, iclass 34, count 2 2006.259.07:47:29.52#ibcon#about to read 5, iclass 34, count 2 2006.259.07:47:29.52#ibcon#read 5, iclass 34, count 2 2006.259.07:47:29.52#ibcon#about to read 6, iclass 34, count 2 2006.259.07:47:29.52#ibcon#read 6, iclass 34, count 2 2006.259.07:47:29.52#ibcon#end of sib2, iclass 34, count 2 2006.259.07:47:29.52#ibcon#*mode == 0, iclass 34, count 2 2006.259.07:47:29.52#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.259.07:47:29.52#ibcon#[25=AT01-08\r\n] 2006.259.07:47:29.52#ibcon#*before write, iclass 34, count 2 2006.259.07:47:29.52#ibcon#enter sib2, iclass 34, count 2 2006.259.07:47:29.52#ibcon#flushed, iclass 34, count 2 2006.259.07:47:29.52#ibcon#about to write, iclass 34, count 2 2006.259.07:47:29.52#ibcon#wrote, iclass 34, count 2 2006.259.07:47:29.52#ibcon#about to read 3, iclass 34, count 2 2006.259.07:47:29.55#ibcon#read 3, iclass 34, count 2 2006.259.07:47:29.55#ibcon#about to read 4, iclass 34, count 2 2006.259.07:47:29.55#ibcon#read 4, iclass 34, count 2 2006.259.07:47:29.55#ibcon#about to read 5, iclass 34, count 2 2006.259.07:47:29.55#ibcon#read 5, iclass 34, count 2 2006.259.07:47:29.55#ibcon#about to read 6, iclass 34, count 2 2006.259.07:47:29.55#ibcon#read 6, iclass 34, count 2 2006.259.07:47:29.55#ibcon#end of sib2, iclass 34, count 2 2006.259.07:47:29.55#ibcon#*after write, iclass 34, count 2 2006.259.07:47:29.55#ibcon#*before return 0, iclass 34, count 2 2006.259.07:47:29.55#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.259.07:47:29.55#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.259.07:47:29.55#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.259.07:47:29.55#ibcon#ireg 7 cls_cnt 0 2006.259.07:47:29.55#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.259.07:47:29.67#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.259.07:47:29.67#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.259.07:47:29.67#ibcon#enter wrdev, iclass 34, count 0 2006.259.07:47:29.67#ibcon#first serial, iclass 34, count 0 2006.259.07:47:29.67#ibcon#enter sib2, iclass 34, count 0 2006.259.07:47:29.67#ibcon#flushed, iclass 34, count 0 2006.259.07:47:29.67#ibcon#about to write, iclass 34, count 0 2006.259.07:47:29.67#ibcon#wrote, iclass 34, count 0 2006.259.07:47:29.67#ibcon#about to read 3, iclass 34, count 0 2006.259.07:47:29.69#ibcon#read 3, iclass 34, count 0 2006.259.07:47:29.69#ibcon#about to read 4, iclass 34, count 0 2006.259.07:47:29.69#ibcon#read 4, iclass 34, count 0 2006.259.07:47:29.69#ibcon#about to read 5, iclass 34, count 0 2006.259.07:47:29.69#ibcon#read 5, iclass 34, count 0 2006.259.07:47:29.69#ibcon#about to read 6, iclass 34, count 0 2006.259.07:47:29.69#ibcon#read 6, iclass 34, count 0 2006.259.07:47:29.69#ibcon#end of sib2, iclass 34, count 0 2006.259.07:47:29.69#ibcon#*mode == 0, iclass 34, count 0 2006.259.07:47:29.69#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.259.07:47:29.69#ibcon#[25=USB\r\n] 2006.259.07:47:29.69#ibcon#*before write, iclass 34, count 0 2006.259.07:47:29.69#ibcon#enter sib2, iclass 34, count 0 2006.259.07:47:29.69#ibcon#flushed, iclass 34, count 0 2006.259.07:47:29.69#ibcon#about to write, iclass 34, count 0 2006.259.07:47:29.69#ibcon#wrote, iclass 34, count 0 2006.259.07:47:29.69#ibcon#about to read 3, iclass 34, count 0 2006.259.07:47:29.72#ibcon#read 3, iclass 34, count 0 2006.259.07:47:29.72#ibcon#about to read 4, iclass 34, count 0 2006.259.07:47:29.72#ibcon#read 4, iclass 34, count 0 2006.259.07:47:29.72#ibcon#about to read 5, iclass 34, count 0 2006.259.07:47:29.72#ibcon#read 5, iclass 34, count 0 2006.259.07:47:29.72#ibcon#about to read 6, iclass 34, count 0 2006.259.07:47:29.72#ibcon#read 6, iclass 34, count 0 2006.259.07:47:29.72#ibcon#end of sib2, iclass 34, count 0 2006.259.07:47:29.72#ibcon#*after write, iclass 34, count 0 2006.259.07:47:29.72#ibcon#*before return 0, iclass 34, count 0 2006.259.07:47:29.72#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.259.07:47:29.72#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.259.07:47:29.72#ibcon#about to clear, iclass 34 cls_cnt 0 2006.259.07:47:29.72#ibcon#cleared, iclass 34 cls_cnt 0 2006.259.07:47:29.72$vc4f8/valo=2,572.99 2006.259.07:47:29.72#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.259.07:47:29.72#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.259.07:47:29.72#ibcon#ireg 17 cls_cnt 0 2006.259.07:47:29.72#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.259.07:47:29.72#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.259.07:47:29.72#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.259.07:47:29.72#ibcon#enter wrdev, iclass 36, count 0 2006.259.07:47:29.72#ibcon#first serial, iclass 36, count 0 2006.259.07:47:29.72#ibcon#enter sib2, iclass 36, count 0 2006.259.07:47:29.72#ibcon#flushed, iclass 36, count 0 2006.259.07:47:29.72#ibcon#about to write, iclass 36, count 0 2006.259.07:47:29.72#ibcon#wrote, iclass 36, count 0 2006.259.07:47:29.72#ibcon#about to read 3, iclass 36, count 0 2006.259.07:47:29.74#ibcon#read 3, iclass 36, count 0 2006.259.07:47:29.74#ibcon#about to read 4, iclass 36, count 0 2006.259.07:47:29.74#ibcon#read 4, iclass 36, count 0 2006.259.07:47:29.74#ibcon#about to read 5, iclass 36, count 0 2006.259.07:47:29.74#ibcon#read 5, iclass 36, count 0 2006.259.07:47:29.74#ibcon#about to read 6, iclass 36, count 0 2006.259.07:47:29.74#ibcon#read 6, iclass 36, count 0 2006.259.07:47:29.74#ibcon#end of sib2, iclass 36, count 0 2006.259.07:47:29.74#ibcon#*mode == 0, iclass 36, count 0 2006.259.07:47:29.74#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.259.07:47:29.74#ibcon#[26=FRQ=02,572.99\r\n] 2006.259.07:47:29.74#ibcon#*before write, iclass 36, count 0 2006.259.07:47:29.74#ibcon#enter sib2, iclass 36, count 0 2006.259.07:47:29.74#ibcon#flushed, iclass 36, count 0 2006.259.07:47:29.74#ibcon#about to write, iclass 36, count 0 2006.259.07:47:29.74#ibcon#wrote, iclass 36, count 0 2006.259.07:47:29.74#ibcon#about to read 3, iclass 36, count 0 2006.259.07:47:29.78#ibcon#read 3, iclass 36, count 0 2006.259.07:47:29.78#ibcon#about to read 4, iclass 36, count 0 2006.259.07:47:29.78#ibcon#read 4, iclass 36, count 0 2006.259.07:47:29.78#ibcon#about to read 5, iclass 36, count 0 2006.259.07:47:29.78#ibcon#read 5, iclass 36, count 0 2006.259.07:47:29.78#ibcon#about to read 6, iclass 36, count 0 2006.259.07:47:29.78#ibcon#read 6, iclass 36, count 0 2006.259.07:47:29.78#ibcon#end of sib2, iclass 36, count 0 2006.259.07:47:29.78#ibcon#*after write, iclass 36, count 0 2006.259.07:47:29.78#ibcon#*before return 0, iclass 36, count 0 2006.259.07:47:29.78#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.259.07:47:29.78#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.259.07:47:29.78#ibcon#about to clear, iclass 36 cls_cnt 0 2006.259.07:47:29.78#ibcon#cleared, iclass 36 cls_cnt 0 2006.259.07:47:29.78$vc4f8/va=2,7 2006.259.07:47:29.78#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.259.07:47:29.78#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.259.07:47:29.78#ibcon#ireg 11 cls_cnt 2 2006.259.07:47:29.78#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.259.07:47:29.84#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.259.07:47:29.84#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.259.07:47:29.84#ibcon#enter wrdev, iclass 38, count 2 2006.259.07:47:29.84#ibcon#first serial, iclass 38, count 2 2006.259.07:47:29.84#ibcon#enter sib2, iclass 38, count 2 2006.259.07:47:29.84#ibcon#flushed, iclass 38, count 2 2006.259.07:47:29.84#ibcon#about to write, iclass 38, count 2 2006.259.07:47:29.84#ibcon#wrote, iclass 38, count 2 2006.259.07:47:29.84#ibcon#about to read 3, iclass 38, count 2 2006.259.07:47:29.86#ibcon#read 3, iclass 38, count 2 2006.259.07:47:29.86#ibcon#about to read 4, iclass 38, count 2 2006.259.07:47:29.86#ibcon#read 4, iclass 38, count 2 2006.259.07:47:29.86#ibcon#about to read 5, iclass 38, count 2 2006.259.07:47:29.86#ibcon#read 5, iclass 38, count 2 2006.259.07:47:29.86#ibcon#about to read 6, iclass 38, count 2 2006.259.07:47:29.86#ibcon#read 6, iclass 38, count 2 2006.259.07:47:29.86#ibcon#end of sib2, iclass 38, count 2 2006.259.07:47:29.86#ibcon#*mode == 0, iclass 38, count 2 2006.259.07:47:29.86#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.259.07:47:29.86#ibcon#[25=AT02-07\r\n] 2006.259.07:47:29.86#ibcon#*before write, iclass 38, count 2 2006.259.07:47:29.86#ibcon#enter sib2, iclass 38, count 2 2006.259.07:47:29.86#ibcon#flushed, iclass 38, count 2 2006.259.07:47:29.86#ibcon#about to write, iclass 38, count 2 2006.259.07:47:29.86#ibcon#wrote, iclass 38, count 2 2006.259.07:47:29.86#ibcon#about to read 3, iclass 38, count 2 2006.259.07:47:29.90#ibcon#read 3, iclass 38, count 2 2006.259.07:47:29.90#ibcon#about to read 4, iclass 38, count 2 2006.259.07:47:29.90#ibcon#read 4, iclass 38, count 2 2006.259.07:47:29.90#ibcon#about to read 5, iclass 38, count 2 2006.259.07:47:29.90#ibcon#read 5, iclass 38, count 2 2006.259.07:47:29.90#ibcon#about to read 6, iclass 38, count 2 2006.259.07:47:29.90#ibcon#read 6, iclass 38, count 2 2006.259.07:47:29.90#ibcon#end of sib2, iclass 38, count 2 2006.259.07:47:29.90#ibcon#*after write, iclass 38, count 2 2006.259.07:47:29.90#ibcon#*before return 0, iclass 38, count 2 2006.259.07:47:29.90#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.259.07:47:29.90#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.259.07:47:29.90#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.259.07:47:29.90#ibcon#ireg 7 cls_cnt 0 2006.259.07:47:29.90#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.259.07:47:30.02#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.259.07:47:30.02#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.259.07:47:30.02#ibcon#enter wrdev, iclass 38, count 0 2006.259.07:47:30.02#ibcon#first serial, iclass 38, count 0 2006.259.07:47:30.02#ibcon#enter sib2, iclass 38, count 0 2006.259.07:47:30.02#ibcon#flushed, iclass 38, count 0 2006.259.07:47:30.02#ibcon#about to write, iclass 38, count 0 2006.259.07:47:30.02#ibcon#wrote, iclass 38, count 0 2006.259.07:47:30.02#ibcon#about to read 3, iclass 38, count 0 2006.259.07:47:30.04#ibcon#read 3, iclass 38, count 0 2006.259.07:47:30.04#ibcon#about to read 4, iclass 38, count 0 2006.259.07:47:30.04#ibcon#read 4, iclass 38, count 0 2006.259.07:47:30.04#ibcon#about to read 5, iclass 38, count 0 2006.259.07:47:30.04#ibcon#read 5, iclass 38, count 0 2006.259.07:47:30.04#ibcon#about to read 6, iclass 38, count 0 2006.259.07:47:30.04#ibcon#read 6, iclass 38, count 0 2006.259.07:47:30.04#ibcon#end of sib2, iclass 38, count 0 2006.259.07:47:30.04#ibcon#*mode == 0, iclass 38, count 0 2006.259.07:47:30.04#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.259.07:47:30.04#ibcon#[25=USB\r\n] 2006.259.07:47:30.04#ibcon#*before write, iclass 38, count 0 2006.259.07:47:30.04#ibcon#enter sib2, iclass 38, count 0 2006.259.07:47:30.04#ibcon#flushed, iclass 38, count 0 2006.259.07:47:30.04#ibcon#about to write, iclass 38, count 0 2006.259.07:47:30.04#ibcon#wrote, iclass 38, count 0 2006.259.07:47:30.04#ibcon#about to read 3, iclass 38, count 0 2006.259.07:47:30.07#ibcon#read 3, iclass 38, count 0 2006.259.07:47:30.07#ibcon#about to read 4, iclass 38, count 0 2006.259.07:47:30.07#ibcon#read 4, iclass 38, count 0 2006.259.07:47:30.07#ibcon#about to read 5, iclass 38, count 0 2006.259.07:47:30.07#ibcon#read 5, iclass 38, count 0 2006.259.07:47:30.07#ibcon#about to read 6, iclass 38, count 0 2006.259.07:47:30.07#ibcon#read 6, iclass 38, count 0 2006.259.07:47:30.07#ibcon#end of sib2, iclass 38, count 0 2006.259.07:47:30.07#ibcon#*after write, iclass 38, count 0 2006.259.07:47:30.07#ibcon#*before return 0, iclass 38, count 0 2006.259.07:47:30.07#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.259.07:47:30.07#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.259.07:47:30.07#ibcon#about to clear, iclass 38 cls_cnt 0 2006.259.07:47:30.07#ibcon#cleared, iclass 38 cls_cnt 0 2006.259.07:47:30.07$vc4f8/valo=3,672.99 2006.259.07:47:30.07#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.259.07:47:30.07#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.259.07:47:30.07#ibcon#ireg 17 cls_cnt 0 2006.259.07:47:30.07#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.259.07:47:30.07#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.259.07:47:30.07#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.259.07:47:30.07#ibcon#enter wrdev, iclass 40, count 0 2006.259.07:47:30.07#ibcon#first serial, iclass 40, count 0 2006.259.07:47:30.07#ibcon#enter sib2, iclass 40, count 0 2006.259.07:47:30.07#ibcon#flushed, iclass 40, count 0 2006.259.07:47:30.07#ibcon#about to write, iclass 40, count 0 2006.259.07:47:30.07#ibcon#wrote, iclass 40, count 0 2006.259.07:47:30.07#ibcon#about to read 3, iclass 40, count 0 2006.259.07:47:30.09#ibcon#read 3, iclass 40, count 0 2006.259.07:47:30.09#ibcon#about to read 4, iclass 40, count 0 2006.259.07:47:30.09#ibcon#read 4, iclass 40, count 0 2006.259.07:47:30.09#ibcon#about to read 5, iclass 40, count 0 2006.259.07:47:30.09#ibcon#read 5, iclass 40, count 0 2006.259.07:47:30.09#ibcon#about to read 6, iclass 40, count 0 2006.259.07:47:30.09#ibcon#read 6, iclass 40, count 0 2006.259.07:47:30.09#ibcon#end of sib2, iclass 40, count 0 2006.259.07:47:30.09#ibcon#*mode == 0, iclass 40, count 0 2006.259.07:47:30.09#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.259.07:47:30.09#ibcon#[26=FRQ=03,672.99\r\n] 2006.259.07:47:30.09#ibcon#*before write, iclass 40, count 0 2006.259.07:47:30.09#ibcon#enter sib2, iclass 40, count 0 2006.259.07:47:30.09#ibcon#flushed, iclass 40, count 0 2006.259.07:47:30.09#ibcon#about to write, iclass 40, count 0 2006.259.07:47:30.09#ibcon#wrote, iclass 40, count 0 2006.259.07:47:30.09#ibcon#about to read 3, iclass 40, count 0 2006.259.07:47:30.13#ibcon#read 3, iclass 40, count 0 2006.259.07:47:30.13#ibcon#about to read 4, iclass 40, count 0 2006.259.07:47:30.13#ibcon#read 4, iclass 40, count 0 2006.259.07:47:30.13#ibcon#about to read 5, iclass 40, count 0 2006.259.07:47:30.13#ibcon#read 5, iclass 40, count 0 2006.259.07:47:30.13#ibcon#about to read 6, iclass 40, count 0 2006.259.07:47:30.13#ibcon#read 6, iclass 40, count 0 2006.259.07:47:30.13#ibcon#end of sib2, iclass 40, count 0 2006.259.07:47:30.13#ibcon#*after write, iclass 40, count 0 2006.259.07:47:30.13#ibcon#*before return 0, iclass 40, count 0 2006.259.07:47:30.13#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.259.07:47:30.13#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.259.07:47:30.13#ibcon#about to clear, iclass 40 cls_cnt 0 2006.259.07:47:30.13#ibcon#cleared, iclass 40 cls_cnt 0 2006.259.07:47:30.13$vc4f8/va=3,8 2006.259.07:47:30.13#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.259.07:47:30.13#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.259.07:47:30.13#ibcon#ireg 11 cls_cnt 2 2006.259.07:47:30.13#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.259.07:47:30.19#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.259.07:47:30.19#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.259.07:47:30.19#ibcon#enter wrdev, iclass 4, count 2 2006.259.07:47:30.19#ibcon#first serial, iclass 4, count 2 2006.259.07:47:30.19#ibcon#enter sib2, iclass 4, count 2 2006.259.07:47:30.19#ibcon#flushed, iclass 4, count 2 2006.259.07:47:30.19#ibcon#about to write, iclass 4, count 2 2006.259.07:47:30.19#ibcon#wrote, iclass 4, count 2 2006.259.07:47:30.19#ibcon#about to read 3, iclass 4, count 2 2006.259.07:47:30.21#ibcon#read 3, iclass 4, count 2 2006.259.07:47:30.21#ibcon#about to read 4, iclass 4, count 2 2006.259.07:47:30.21#ibcon#read 4, iclass 4, count 2 2006.259.07:47:30.21#ibcon#about to read 5, iclass 4, count 2 2006.259.07:47:30.21#ibcon#read 5, iclass 4, count 2 2006.259.07:47:30.21#ibcon#about to read 6, iclass 4, count 2 2006.259.07:47:30.21#ibcon#read 6, iclass 4, count 2 2006.259.07:47:30.21#ibcon#end of sib2, iclass 4, count 2 2006.259.07:47:30.21#ibcon#*mode == 0, iclass 4, count 2 2006.259.07:47:30.21#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.259.07:47:30.21#ibcon#[25=AT03-08\r\n] 2006.259.07:47:30.21#ibcon#*before write, iclass 4, count 2 2006.259.07:47:30.21#ibcon#enter sib2, iclass 4, count 2 2006.259.07:47:30.21#ibcon#flushed, iclass 4, count 2 2006.259.07:47:30.21#ibcon#about to write, iclass 4, count 2 2006.259.07:47:30.21#ibcon#wrote, iclass 4, count 2 2006.259.07:47:30.21#ibcon#about to read 3, iclass 4, count 2 2006.259.07:47:30.24#ibcon#read 3, iclass 4, count 2 2006.259.07:47:30.24#ibcon#about to read 4, iclass 4, count 2 2006.259.07:47:30.24#ibcon#read 4, iclass 4, count 2 2006.259.07:47:30.24#ibcon#about to read 5, iclass 4, count 2 2006.259.07:47:30.24#ibcon#read 5, iclass 4, count 2 2006.259.07:47:30.24#ibcon#about to read 6, iclass 4, count 2 2006.259.07:47:30.24#ibcon#read 6, iclass 4, count 2 2006.259.07:47:30.24#ibcon#end of sib2, iclass 4, count 2 2006.259.07:47:30.24#ibcon#*after write, iclass 4, count 2 2006.259.07:47:30.24#ibcon#*before return 0, iclass 4, count 2 2006.259.07:47:30.24#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.259.07:47:30.24#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.259.07:47:30.24#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.259.07:47:30.24#ibcon#ireg 7 cls_cnt 0 2006.259.07:47:30.24#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.259.07:47:30.36#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.259.07:47:30.36#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.259.07:47:30.36#ibcon#enter wrdev, iclass 4, count 0 2006.259.07:47:30.36#ibcon#first serial, iclass 4, count 0 2006.259.07:47:30.36#ibcon#enter sib2, iclass 4, count 0 2006.259.07:47:30.36#ibcon#flushed, iclass 4, count 0 2006.259.07:47:30.36#ibcon#about to write, iclass 4, count 0 2006.259.07:47:30.36#ibcon#wrote, iclass 4, count 0 2006.259.07:47:30.36#ibcon#about to read 3, iclass 4, count 0 2006.259.07:47:30.38#ibcon#read 3, iclass 4, count 0 2006.259.07:47:30.38#ibcon#about to read 4, iclass 4, count 0 2006.259.07:47:30.38#ibcon#read 4, iclass 4, count 0 2006.259.07:47:30.38#ibcon#about to read 5, iclass 4, count 0 2006.259.07:47:30.38#ibcon#read 5, iclass 4, count 0 2006.259.07:47:30.38#ibcon#about to read 6, iclass 4, count 0 2006.259.07:47:30.38#ibcon#read 6, iclass 4, count 0 2006.259.07:47:30.38#ibcon#end of sib2, iclass 4, count 0 2006.259.07:47:30.38#ibcon#*mode == 0, iclass 4, count 0 2006.259.07:47:30.38#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.259.07:47:30.38#ibcon#[25=USB\r\n] 2006.259.07:47:30.38#ibcon#*before write, iclass 4, count 0 2006.259.07:47:30.38#ibcon#enter sib2, iclass 4, count 0 2006.259.07:47:30.38#ibcon#flushed, iclass 4, count 0 2006.259.07:47:30.38#ibcon#about to write, iclass 4, count 0 2006.259.07:47:30.38#ibcon#wrote, iclass 4, count 0 2006.259.07:47:30.38#ibcon#about to read 3, iclass 4, count 0 2006.259.07:47:30.41#ibcon#read 3, iclass 4, count 0 2006.259.07:47:30.41#ibcon#about to read 4, iclass 4, count 0 2006.259.07:47:30.41#ibcon#read 4, iclass 4, count 0 2006.259.07:47:30.41#ibcon#about to read 5, iclass 4, count 0 2006.259.07:47:30.41#ibcon#read 5, iclass 4, count 0 2006.259.07:47:30.41#ibcon#about to read 6, iclass 4, count 0 2006.259.07:47:30.41#ibcon#read 6, iclass 4, count 0 2006.259.07:47:30.41#ibcon#end of sib2, iclass 4, count 0 2006.259.07:47:30.41#ibcon#*after write, iclass 4, count 0 2006.259.07:47:30.41#ibcon#*before return 0, iclass 4, count 0 2006.259.07:47:30.41#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.259.07:47:30.41#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.259.07:47:30.41#ibcon#about to clear, iclass 4 cls_cnt 0 2006.259.07:47:30.41#ibcon#cleared, iclass 4 cls_cnt 0 2006.259.07:47:30.41$vc4f8/valo=4,832.99 2006.259.07:47:30.41#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.259.07:47:30.41#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.259.07:47:30.41#ibcon#ireg 17 cls_cnt 0 2006.259.07:47:30.41#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.259.07:47:30.41#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.259.07:47:30.41#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.259.07:47:30.41#ibcon#enter wrdev, iclass 6, count 0 2006.259.07:47:30.41#ibcon#first serial, iclass 6, count 0 2006.259.07:47:30.41#ibcon#enter sib2, iclass 6, count 0 2006.259.07:47:30.41#ibcon#flushed, iclass 6, count 0 2006.259.07:47:30.41#ibcon#about to write, iclass 6, count 0 2006.259.07:47:30.41#ibcon#wrote, iclass 6, count 0 2006.259.07:47:30.41#ibcon#about to read 3, iclass 6, count 0 2006.259.07:47:30.43#ibcon#read 3, iclass 6, count 0 2006.259.07:47:30.43#ibcon#about to read 4, iclass 6, count 0 2006.259.07:47:30.43#ibcon#read 4, iclass 6, count 0 2006.259.07:47:30.43#ibcon#about to read 5, iclass 6, count 0 2006.259.07:47:30.43#ibcon#read 5, iclass 6, count 0 2006.259.07:47:30.43#ibcon#about to read 6, iclass 6, count 0 2006.259.07:47:30.43#ibcon#read 6, iclass 6, count 0 2006.259.07:47:30.43#ibcon#end of sib2, iclass 6, count 0 2006.259.07:47:30.43#ibcon#*mode == 0, iclass 6, count 0 2006.259.07:47:30.43#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.259.07:47:30.43#ibcon#[26=FRQ=04,832.99\r\n] 2006.259.07:47:30.43#ibcon#*before write, iclass 6, count 0 2006.259.07:47:30.43#ibcon#enter sib2, iclass 6, count 0 2006.259.07:47:30.43#ibcon#flushed, iclass 6, count 0 2006.259.07:47:30.43#ibcon#about to write, iclass 6, count 0 2006.259.07:47:30.43#ibcon#wrote, iclass 6, count 0 2006.259.07:47:30.43#ibcon#about to read 3, iclass 6, count 0 2006.259.07:47:30.47#ibcon#read 3, iclass 6, count 0 2006.259.07:47:30.47#ibcon#about to read 4, iclass 6, count 0 2006.259.07:47:30.47#ibcon#read 4, iclass 6, count 0 2006.259.07:47:30.47#ibcon#about to read 5, iclass 6, count 0 2006.259.07:47:30.47#ibcon#read 5, iclass 6, count 0 2006.259.07:47:30.47#ibcon#about to read 6, iclass 6, count 0 2006.259.07:47:30.47#ibcon#read 6, iclass 6, count 0 2006.259.07:47:30.47#ibcon#end of sib2, iclass 6, count 0 2006.259.07:47:30.47#ibcon#*after write, iclass 6, count 0 2006.259.07:47:30.47#ibcon#*before return 0, iclass 6, count 0 2006.259.07:47:30.47#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.259.07:47:30.47#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.259.07:47:30.47#ibcon#about to clear, iclass 6 cls_cnt 0 2006.259.07:47:30.47#ibcon#cleared, iclass 6 cls_cnt 0 2006.259.07:47:30.47$vc4f8/va=4,7 2006.259.07:47:30.47#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.259.07:47:30.47#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.259.07:47:30.47#ibcon#ireg 11 cls_cnt 2 2006.259.07:47:30.47#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.259.07:47:30.53#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.259.07:47:30.53#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.259.07:47:30.53#ibcon#enter wrdev, iclass 10, count 2 2006.259.07:47:30.53#ibcon#first serial, iclass 10, count 2 2006.259.07:47:30.53#ibcon#enter sib2, iclass 10, count 2 2006.259.07:47:30.53#ibcon#flushed, iclass 10, count 2 2006.259.07:47:30.53#ibcon#about to write, iclass 10, count 2 2006.259.07:47:30.53#ibcon#wrote, iclass 10, count 2 2006.259.07:47:30.53#ibcon#about to read 3, iclass 10, count 2 2006.259.07:47:30.55#ibcon#read 3, iclass 10, count 2 2006.259.07:47:30.55#ibcon#about to read 4, iclass 10, count 2 2006.259.07:47:30.55#ibcon#read 4, iclass 10, count 2 2006.259.07:47:30.55#ibcon#about to read 5, iclass 10, count 2 2006.259.07:47:30.55#ibcon#read 5, iclass 10, count 2 2006.259.07:47:30.55#ibcon#about to read 6, iclass 10, count 2 2006.259.07:47:30.55#ibcon#read 6, iclass 10, count 2 2006.259.07:47:30.55#ibcon#end of sib2, iclass 10, count 2 2006.259.07:47:30.55#ibcon#*mode == 0, iclass 10, count 2 2006.259.07:47:30.55#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.259.07:47:30.55#ibcon#[25=AT04-07\r\n] 2006.259.07:47:30.55#ibcon#*before write, iclass 10, count 2 2006.259.07:47:30.55#ibcon#enter sib2, iclass 10, count 2 2006.259.07:47:30.55#ibcon#flushed, iclass 10, count 2 2006.259.07:47:30.55#ibcon#about to write, iclass 10, count 2 2006.259.07:47:30.55#ibcon#wrote, iclass 10, count 2 2006.259.07:47:30.55#ibcon#about to read 3, iclass 10, count 2 2006.259.07:47:30.58#ibcon#read 3, iclass 10, count 2 2006.259.07:47:30.58#ibcon#about to read 4, iclass 10, count 2 2006.259.07:47:30.58#ibcon#read 4, iclass 10, count 2 2006.259.07:47:30.58#ibcon#about to read 5, iclass 10, count 2 2006.259.07:47:30.58#ibcon#read 5, iclass 10, count 2 2006.259.07:47:30.58#ibcon#about to read 6, iclass 10, count 2 2006.259.07:47:30.58#ibcon#read 6, iclass 10, count 2 2006.259.07:47:30.58#ibcon#end of sib2, iclass 10, count 2 2006.259.07:47:30.58#ibcon#*after write, iclass 10, count 2 2006.259.07:47:30.58#ibcon#*before return 0, iclass 10, count 2 2006.259.07:47:30.58#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.259.07:47:30.58#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.259.07:47:30.58#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.259.07:47:30.58#ibcon#ireg 7 cls_cnt 0 2006.259.07:47:30.58#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.259.07:47:30.70#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.259.07:47:30.70#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.259.07:47:30.70#ibcon#enter wrdev, iclass 10, count 0 2006.259.07:47:30.70#ibcon#first serial, iclass 10, count 0 2006.259.07:47:30.70#ibcon#enter sib2, iclass 10, count 0 2006.259.07:47:30.70#ibcon#flushed, iclass 10, count 0 2006.259.07:47:30.70#ibcon#about to write, iclass 10, count 0 2006.259.07:47:30.70#ibcon#wrote, iclass 10, count 0 2006.259.07:47:30.70#ibcon#about to read 3, iclass 10, count 0 2006.259.07:47:30.72#ibcon#read 3, iclass 10, count 0 2006.259.07:47:30.72#ibcon#about to read 4, iclass 10, count 0 2006.259.07:47:30.72#ibcon#read 4, iclass 10, count 0 2006.259.07:47:30.72#ibcon#about to read 5, iclass 10, count 0 2006.259.07:47:30.72#ibcon#read 5, iclass 10, count 0 2006.259.07:47:30.72#ibcon#about to read 6, iclass 10, count 0 2006.259.07:47:30.72#ibcon#read 6, iclass 10, count 0 2006.259.07:47:30.72#ibcon#end of sib2, iclass 10, count 0 2006.259.07:47:30.72#ibcon#*mode == 0, iclass 10, count 0 2006.259.07:47:30.72#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.259.07:47:30.72#ibcon#[25=USB\r\n] 2006.259.07:47:30.72#ibcon#*before write, iclass 10, count 0 2006.259.07:47:30.72#ibcon#enter sib2, iclass 10, count 0 2006.259.07:47:30.72#ibcon#flushed, iclass 10, count 0 2006.259.07:47:30.72#ibcon#about to write, iclass 10, count 0 2006.259.07:47:30.72#ibcon#wrote, iclass 10, count 0 2006.259.07:47:30.72#ibcon#about to read 3, iclass 10, count 0 2006.259.07:47:30.75#ibcon#read 3, iclass 10, count 0 2006.259.07:47:30.75#ibcon#about to read 4, iclass 10, count 0 2006.259.07:47:30.75#ibcon#read 4, iclass 10, count 0 2006.259.07:47:30.75#ibcon#about to read 5, iclass 10, count 0 2006.259.07:47:30.75#ibcon#read 5, iclass 10, count 0 2006.259.07:47:30.75#ibcon#about to read 6, iclass 10, count 0 2006.259.07:47:30.75#ibcon#read 6, iclass 10, count 0 2006.259.07:47:30.75#ibcon#end of sib2, iclass 10, count 0 2006.259.07:47:30.75#ibcon#*after write, iclass 10, count 0 2006.259.07:47:30.75#ibcon#*before return 0, iclass 10, count 0 2006.259.07:47:30.75#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.259.07:47:30.75#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.259.07:47:30.75#ibcon#about to clear, iclass 10 cls_cnt 0 2006.259.07:47:30.75#ibcon#cleared, iclass 10 cls_cnt 0 2006.259.07:47:30.75$vc4f8/valo=5,652.99 2006.259.07:47:30.75#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.259.07:47:30.75#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.259.07:47:30.75#ibcon#ireg 17 cls_cnt 0 2006.259.07:47:30.75#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.259.07:47:30.75#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.259.07:47:30.75#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.259.07:47:30.75#ibcon#enter wrdev, iclass 12, count 0 2006.259.07:47:30.75#ibcon#first serial, iclass 12, count 0 2006.259.07:47:30.75#ibcon#enter sib2, iclass 12, count 0 2006.259.07:47:30.75#ibcon#flushed, iclass 12, count 0 2006.259.07:47:30.75#ibcon#about to write, iclass 12, count 0 2006.259.07:47:30.75#ibcon#wrote, iclass 12, count 0 2006.259.07:47:30.75#ibcon#about to read 3, iclass 12, count 0 2006.259.07:47:30.77#ibcon#read 3, iclass 12, count 0 2006.259.07:47:30.77#ibcon#about to read 4, iclass 12, count 0 2006.259.07:47:30.77#ibcon#read 4, iclass 12, count 0 2006.259.07:47:30.77#ibcon#about to read 5, iclass 12, count 0 2006.259.07:47:30.77#ibcon#read 5, iclass 12, count 0 2006.259.07:47:30.77#ibcon#about to read 6, iclass 12, count 0 2006.259.07:47:30.77#ibcon#read 6, iclass 12, count 0 2006.259.07:47:30.77#ibcon#end of sib2, iclass 12, count 0 2006.259.07:47:30.77#ibcon#*mode == 0, iclass 12, count 0 2006.259.07:47:30.77#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.259.07:47:30.77#ibcon#[26=FRQ=05,652.99\r\n] 2006.259.07:47:30.77#ibcon#*before write, iclass 12, count 0 2006.259.07:47:30.77#ibcon#enter sib2, iclass 12, count 0 2006.259.07:47:30.77#ibcon#flushed, iclass 12, count 0 2006.259.07:47:30.77#ibcon#about to write, iclass 12, count 0 2006.259.07:47:30.77#ibcon#wrote, iclass 12, count 0 2006.259.07:47:30.77#ibcon#about to read 3, iclass 12, count 0 2006.259.07:47:30.81#ibcon#read 3, iclass 12, count 0 2006.259.07:47:30.81#ibcon#about to read 4, iclass 12, count 0 2006.259.07:47:30.81#ibcon#read 4, iclass 12, count 0 2006.259.07:47:30.81#ibcon#about to read 5, iclass 12, count 0 2006.259.07:47:30.81#ibcon#read 5, iclass 12, count 0 2006.259.07:47:30.81#ibcon#about to read 6, iclass 12, count 0 2006.259.07:47:30.81#ibcon#read 6, iclass 12, count 0 2006.259.07:47:30.81#ibcon#end of sib2, iclass 12, count 0 2006.259.07:47:30.81#ibcon#*after write, iclass 12, count 0 2006.259.07:47:30.81#ibcon#*before return 0, iclass 12, count 0 2006.259.07:47:30.81#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.259.07:47:30.81#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.259.07:47:30.81#ibcon#about to clear, iclass 12 cls_cnt 0 2006.259.07:47:30.81#ibcon#cleared, iclass 12 cls_cnt 0 2006.259.07:47:30.81$vc4f8/va=5,7 2006.259.07:47:30.81#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.259.07:47:30.81#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.259.07:47:30.81#ibcon#ireg 11 cls_cnt 2 2006.259.07:47:30.81#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.259.07:47:30.87#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.259.07:47:30.87#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.259.07:47:30.87#ibcon#enter wrdev, iclass 14, count 2 2006.259.07:47:30.87#ibcon#first serial, iclass 14, count 2 2006.259.07:47:30.87#ibcon#enter sib2, iclass 14, count 2 2006.259.07:47:30.87#ibcon#flushed, iclass 14, count 2 2006.259.07:47:30.87#ibcon#about to write, iclass 14, count 2 2006.259.07:47:30.87#ibcon#wrote, iclass 14, count 2 2006.259.07:47:30.87#ibcon#about to read 3, iclass 14, count 2 2006.259.07:47:30.89#ibcon#read 3, iclass 14, count 2 2006.259.07:47:30.89#ibcon#about to read 4, iclass 14, count 2 2006.259.07:47:30.89#ibcon#read 4, iclass 14, count 2 2006.259.07:47:30.89#ibcon#about to read 5, iclass 14, count 2 2006.259.07:47:30.89#ibcon#read 5, iclass 14, count 2 2006.259.07:47:30.89#ibcon#about to read 6, iclass 14, count 2 2006.259.07:47:30.89#ibcon#read 6, iclass 14, count 2 2006.259.07:47:30.89#ibcon#end of sib2, iclass 14, count 2 2006.259.07:47:30.89#ibcon#*mode == 0, iclass 14, count 2 2006.259.07:47:30.89#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.259.07:47:30.89#ibcon#[25=AT05-07\r\n] 2006.259.07:47:30.89#ibcon#*before write, iclass 14, count 2 2006.259.07:47:30.89#ibcon#enter sib2, iclass 14, count 2 2006.259.07:47:30.89#ibcon#flushed, iclass 14, count 2 2006.259.07:47:30.89#ibcon#about to write, iclass 14, count 2 2006.259.07:47:30.89#ibcon#wrote, iclass 14, count 2 2006.259.07:47:30.89#ibcon#about to read 3, iclass 14, count 2 2006.259.07:47:30.92#ibcon#read 3, iclass 14, count 2 2006.259.07:47:30.92#ibcon#about to read 4, iclass 14, count 2 2006.259.07:47:30.92#ibcon#read 4, iclass 14, count 2 2006.259.07:47:30.92#ibcon#about to read 5, iclass 14, count 2 2006.259.07:47:30.92#ibcon#read 5, iclass 14, count 2 2006.259.07:47:30.92#ibcon#about to read 6, iclass 14, count 2 2006.259.07:47:30.92#ibcon#read 6, iclass 14, count 2 2006.259.07:47:30.92#ibcon#end of sib2, iclass 14, count 2 2006.259.07:47:30.92#ibcon#*after write, iclass 14, count 2 2006.259.07:47:30.92#ibcon#*before return 0, iclass 14, count 2 2006.259.07:47:30.92#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.259.07:47:30.92#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.259.07:47:30.92#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.259.07:47:30.92#ibcon#ireg 7 cls_cnt 0 2006.259.07:47:30.92#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.259.07:47:31.04#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.259.07:47:31.04#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.259.07:47:31.04#ibcon#enter wrdev, iclass 14, count 0 2006.259.07:47:31.04#ibcon#first serial, iclass 14, count 0 2006.259.07:47:31.04#ibcon#enter sib2, iclass 14, count 0 2006.259.07:47:31.04#ibcon#flushed, iclass 14, count 0 2006.259.07:47:31.04#ibcon#about to write, iclass 14, count 0 2006.259.07:47:31.04#ibcon#wrote, iclass 14, count 0 2006.259.07:47:31.04#ibcon#about to read 3, iclass 14, count 0 2006.259.07:47:31.06#ibcon#read 3, iclass 14, count 0 2006.259.07:47:31.06#ibcon#about to read 4, iclass 14, count 0 2006.259.07:47:31.06#ibcon#read 4, iclass 14, count 0 2006.259.07:47:31.06#ibcon#about to read 5, iclass 14, count 0 2006.259.07:47:31.06#ibcon#read 5, iclass 14, count 0 2006.259.07:47:31.06#ibcon#about to read 6, iclass 14, count 0 2006.259.07:47:31.06#ibcon#read 6, iclass 14, count 0 2006.259.07:47:31.06#ibcon#end of sib2, iclass 14, count 0 2006.259.07:47:31.06#ibcon#*mode == 0, iclass 14, count 0 2006.259.07:47:31.06#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.259.07:47:31.06#ibcon#[25=USB\r\n] 2006.259.07:47:31.06#ibcon#*before write, iclass 14, count 0 2006.259.07:47:31.06#ibcon#enter sib2, iclass 14, count 0 2006.259.07:47:31.06#ibcon#flushed, iclass 14, count 0 2006.259.07:47:31.06#ibcon#about to write, iclass 14, count 0 2006.259.07:47:31.06#ibcon#wrote, iclass 14, count 0 2006.259.07:47:31.06#ibcon#about to read 3, iclass 14, count 0 2006.259.07:47:31.09#ibcon#read 3, iclass 14, count 0 2006.259.07:47:31.09#ibcon#about to read 4, iclass 14, count 0 2006.259.07:47:31.09#ibcon#read 4, iclass 14, count 0 2006.259.07:47:31.09#ibcon#about to read 5, iclass 14, count 0 2006.259.07:47:31.09#ibcon#read 5, iclass 14, count 0 2006.259.07:47:31.09#ibcon#about to read 6, iclass 14, count 0 2006.259.07:47:31.09#ibcon#read 6, iclass 14, count 0 2006.259.07:47:31.09#ibcon#end of sib2, iclass 14, count 0 2006.259.07:47:31.09#ibcon#*after write, iclass 14, count 0 2006.259.07:47:31.09#ibcon#*before return 0, iclass 14, count 0 2006.259.07:47:31.09#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.259.07:47:31.09#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.259.07:47:31.09#ibcon#about to clear, iclass 14 cls_cnt 0 2006.259.07:47:31.09#ibcon#cleared, iclass 14 cls_cnt 0 2006.259.07:47:31.09$vc4f8/valo=6,772.99 2006.259.07:47:31.09#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.259.07:47:31.09#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.259.07:47:31.09#ibcon#ireg 17 cls_cnt 0 2006.259.07:47:31.09#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.259.07:47:31.09#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.259.07:47:31.09#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.259.07:47:31.09#ibcon#enter wrdev, iclass 16, count 0 2006.259.07:47:31.09#ibcon#first serial, iclass 16, count 0 2006.259.07:47:31.09#ibcon#enter sib2, iclass 16, count 0 2006.259.07:47:31.09#ibcon#flushed, iclass 16, count 0 2006.259.07:47:31.09#ibcon#about to write, iclass 16, count 0 2006.259.07:47:31.09#ibcon#wrote, iclass 16, count 0 2006.259.07:47:31.09#ibcon#about to read 3, iclass 16, count 0 2006.259.07:47:31.11#ibcon#read 3, iclass 16, count 0 2006.259.07:47:31.11#ibcon#about to read 4, iclass 16, count 0 2006.259.07:47:31.11#ibcon#read 4, iclass 16, count 0 2006.259.07:47:31.11#ibcon#about to read 5, iclass 16, count 0 2006.259.07:47:31.11#ibcon#read 5, iclass 16, count 0 2006.259.07:47:31.11#ibcon#about to read 6, iclass 16, count 0 2006.259.07:47:31.11#ibcon#read 6, iclass 16, count 0 2006.259.07:47:31.11#ibcon#end of sib2, iclass 16, count 0 2006.259.07:47:31.11#ibcon#*mode == 0, iclass 16, count 0 2006.259.07:47:31.11#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.259.07:47:31.11#ibcon#[26=FRQ=06,772.99\r\n] 2006.259.07:47:31.11#ibcon#*before write, iclass 16, count 0 2006.259.07:47:31.11#ibcon#enter sib2, iclass 16, count 0 2006.259.07:47:31.11#ibcon#flushed, iclass 16, count 0 2006.259.07:47:31.11#ibcon#about to write, iclass 16, count 0 2006.259.07:47:31.11#ibcon#wrote, iclass 16, count 0 2006.259.07:47:31.11#ibcon#about to read 3, iclass 16, count 0 2006.259.07:47:31.15#ibcon#read 3, iclass 16, count 0 2006.259.07:47:31.15#ibcon#about to read 4, iclass 16, count 0 2006.259.07:47:31.15#ibcon#read 4, iclass 16, count 0 2006.259.07:47:31.15#ibcon#about to read 5, iclass 16, count 0 2006.259.07:47:31.15#ibcon#read 5, iclass 16, count 0 2006.259.07:47:31.15#ibcon#about to read 6, iclass 16, count 0 2006.259.07:47:31.15#ibcon#read 6, iclass 16, count 0 2006.259.07:47:31.15#ibcon#end of sib2, iclass 16, count 0 2006.259.07:47:31.15#ibcon#*after write, iclass 16, count 0 2006.259.07:47:31.15#ibcon#*before return 0, iclass 16, count 0 2006.259.07:47:31.15#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.259.07:47:31.15#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.259.07:47:31.15#ibcon#about to clear, iclass 16 cls_cnt 0 2006.259.07:47:31.15#ibcon#cleared, iclass 16 cls_cnt 0 2006.259.07:47:31.15$vc4f8/va=6,6 2006.259.07:47:31.15#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.259.07:47:31.15#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.259.07:47:31.15#ibcon#ireg 11 cls_cnt 2 2006.259.07:47:31.15#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.259.07:47:31.21#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.259.07:47:31.21#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.259.07:47:31.21#ibcon#enter wrdev, iclass 18, count 2 2006.259.07:47:31.21#ibcon#first serial, iclass 18, count 2 2006.259.07:47:31.21#ibcon#enter sib2, iclass 18, count 2 2006.259.07:47:31.21#ibcon#flushed, iclass 18, count 2 2006.259.07:47:31.21#ibcon#about to write, iclass 18, count 2 2006.259.07:47:31.21#ibcon#wrote, iclass 18, count 2 2006.259.07:47:31.21#ibcon#about to read 3, iclass 18, count 2 2006.259.07:47:31.23#ibcon#read 3, iclass 18, count 2 2006.259.07:47:31.23#ibcon#about to read 4, iclass 18, count 2 2006.259.07:47:31.23#ibcon#read 4, iclass 18, count 2 2006.259.07:47:31.23#ibcon#about to read 5, iclass 18, count 2 2006.259.07:47:31.23#ibcon#read 5, iclass 18, count 2 2006.259.07:47:31.23#ibcon#about to read 6, iclass 18, count 2 2006.259.07:47:31.23#ibcon#read 6, iclass 18, count 2 2006.259.07:47:31.23#ibcon#end of sib2, iclass 18, count 2 2006.259.07:47:31.23#ibcon#*mode == 0, iclass 18, count 2 2006.259.07:47:31.23#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.259.07:47:31.23#ibcon#[25=AT06-06\r\n] 2006.259.07:47:31.23#ibcon#*before write, iclass 18, count 2 2006.259.07:47:31.23#ibcon#enter sib2, iclass 18, count 2 2006.259.07:47:31.23#ibcon#flushed, iclass 18, count 2 2006.259.07:47:31.23#ibcon#about to write, iclass 18, count 2 2006.259.07:47:31.23#ibcon#wrote, iclass 18, count 2 2006.259.07:47:31.23#ibcon#about to read 3, iclass 18, count 2 2006.259.07:47:31.26#ibcon#read 3, iclass 18, count 2 2006.259.07:47:31.26#ibcon#about to read 4, iclass 18, count 2 2006.259.07:47:31.26#ibcon#read 4, iclass 18, count 2 2006.259.07:47:31.26#ibcon#about to read 5, iclass 18, count 2 2006.259.07:47:31.26#ibcon#read 5, iclass 18, count 2 2006.259.07:47:31.26#ibcon#about to read 6, iclass 18, count 2 2006.259.07:47:31.26#ibcon#read 6, iclass 18, count 2 2006.259.07:47:31.26#ibcon#end of sib2, iclass 18, count 2 2006.259.07:47:31.26#ibcon#*after write, iclass 18, count 2 2006.259.07:47:31.26#ibcon#*before return 0, iclass 18, count 2 2006.259.07:47:31.26#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.259.07:47:31.26#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.259.07:47:31.26#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.259.07:47:31.26#ibcon#ireg 7 cls_cnt 0 2006.259.07:47:31.26#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.259.07:47:31.38#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.259.07:47:31.38#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.259.07:47:31.38#ibcon#enter wrdev, iclass 18, count 0 2006.259.07:47:31.38#ibcon#first serial, iclass 18, count 0 2006.259.07:47:31.38#ibcon#enter sib2, iclass 18, count 0 2006.259.07:47:31.38#ibcon#flushed, iclass 18, count 0 2006.259.07:47:31.38#ibcon#about to write, iclass 18, count 0 2006.259.07:47:31.38#ibcon#wrote, iclass 18, count 0 2006.259.07:47:31.38#ibcon#about to read 3, iclass 18, count 0 2006.259.07:47:31.40#ibcon#read 3, iclass 18, count 0 2006.259.07:47:31.40#ibcon#about to read 4, iclass 18, count 0 2006.259.07:47:31.40#ibcon#read 4, iclass 18, count 0 2006.259.07:47:31.40#ibcon#about to read 5, iclass 18, count 0 2006.259.07:47:31.40#ibcon#read 5, iclass 18, count 0 2006.259.07:47:31.40#ibcon#about to read 6, iclass 18, count 0 2006.259.07:47:31.40#ibcon#read 6, iclass 18, count 0 2006.259.07:47:31.40#ibcon#end of sib2, iclass 18, count 0 2006.259.07:47:31.40#ibcon#*mode == 0, iclass 18, count 0 2006.259.07:47:31.40#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.259.07:47:31.40#ibcon#[25=USB\r\n] 2006.259.07:47:31.40#ibcon#*before write, iclass 18, count 0 2006.259.07:47:31.40#ibcon#enter sib2, iclass 18, count 0 2006.259.07:47:31.40#ibcon#flushed, iclass 18, count 0 2006.259.07:47:31.40#ibcon#about to write, iclass 18, count 0 2006.259.07:47:31.40#ibcon#wrote, iclass 18, count 0 2006.259.07:47:31.40#ibcon#about to read 3, iclass 18, count 0 2006.259.07:47:31.43#ibcon#read 3, iclass 18, count 0 2006.259.07:47:31.43#ibcon#about to read 4, iclass 18, count 0 2006.259.07:47:31.43#ibcon#read 4, iclass 18, count 0 2006.259.07:47:31.43#ibcon#about to read 5, iclass 18, count 0 2006.259.07:47:31.43#ibcon#read 5, iclass 18, count 0 2006.259.07:47:31.43#ibcon#about to read 6, iclass 18, count 0 2006.259.07:47:31.43#ibcon#read 6, iclass 18, count 0 2006.259.07:47:31.43#ibcon#end of sib2, iclass 18, count 0 2006.259.07:47:31.43#ibcon#*after write, iclass 18, count 0 2006.259.07:47:31.43#ibcon#*before return 0, iclass 18, count 0 2006.259.07:47:31.43#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.259.07:47:31.43#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.259.07:47:31.43#ibcon#about to clear, iclass 18 cls_cnt 0 2006.259.07:47:31.43#ibcon#cleared, iclass 18 cls_cnt 0 2006.259.07:47:31.43$vc4f8/valo=7,832.99 2006.259.07:47:31.43#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.259.07:47:31.43#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.259.07:47:31.43#ibcon#ireg 17 cls_cnt 0 2006.259.07:47:31.43#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.259.07:47:31.43#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.259.07:47:31.43#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.259.07:47:31.43#ibcon#enter wrdev, iclass 20, count 0 2006.259.07:47:31.43#ibcon#first serial, iclass 20, count 0 2006.259.07:47:31.43#ibcon#enter sib2, iclass 20, count 0 2006.259.07:47:31.43#ibcon#flushed, iclass 20, count 0 2006.259.07:47:31.43#ibcon#about to write, iclass 20, count 0 2006.259.07:47:31.43#ibcon#wrote, iclass 20, count 0 2006.259.07:47:31.43#ibcon#about to read 3, iclass 20, count 0 2006.259.07:47:31.45#ibcon#read 3, iclass 20, count 0 2006.259.07:47:31.45#ibcon#about to read 4, iclass 20, count 0 2006.259.07:47:31.45#ibcon#read 4, iclass 20, count 0 2006.259.07:47:31.45#ibcon#about to read 5, iclass 20, count 0 2006.259.07:47:31.45#ibcon#read 5, iclass 20, count 0 2006.259.07:47:31.45#ibcon#about to read 6, iclass 20, count 0 2006.259.07:47:31.45#ibcon#read 6, iclass 20, count 0 2006.259.07:47:31.45#ibcon#end of sib2, iclass 20, count 0 2006.259.07:47:31.45#ibcon#*mode == 0, iclass 20, count 0 2006.259.07:47:31.45#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.259.07:47:31.45#ibcon#[26=FRQ=07,832.99\r\n] 2006.259.07:47:31.45#ibcon#*before write, iclass 20, count 0 2006.259.07:47:31.45#ibcon#enter sib2, iclass 20, count 0 2006.259.07:47:31.45#ibcon#flushed, iclass 20, count 0 2006.259.07:47:31.45#ibcon#about to write, iclass 20, count 0 2006.259.07:47:31.45#ibcon#wrote, iclass 20, count 0 2006.259.07:47:31.45#ibcon#about to read 3, iclass 20, count 0 2006.259.07:47:31.49#ibcon#read 3, iclass 20, count 0 2006.259.07:47:31.49#ibcon#about to read 4, iclass 20, count 0 2006.259.07:47:31.49#ibcon#read 4, iclass 20, count 0 2006.259.07:47:31.49#ibcon#about to read 5, iclass 20, count 0 2006.259.07:47:31.49#ibcon#read 5, iclass 20, count 0 2006.259.07:47:31.49#ibcon#about to read 6, iclass 20, count 0 2006.259.07:47:31.49#ibcon#read 6, iclass 20, count 0 2006.259.07:47:31.49#ibcon#end of sib2, iclass 20, count 0 2006.259.07:47:31.49#ibcon#*after write, iclass 20, count 0 2006.259.07:47:31.49#ibcon#*before return 0, iclass 20, count 0 2006.259.07:47:31.49#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.259.07:47:31.49#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.259.07:47:31.49#ibcon#about to clear, iclass 20 cls_cnt 0 2006.259.07:47:31.49#ibcon#cleared, iclass 20 cls_cnt 0 2006.259.07:47:31.49$vc4f8/va=7,6 2006.259.07:47:31.49#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.259.07:47:31.49#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.259.07:47:31.49#ibcon#ireg 11 cls_cnt 2 2006.259.07:47:31.49#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.259.07:47:31.55#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.259.07:47:31.55#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.259.07:47:31.55#ibcon#enter wrdev, iclass 22, count 2 2006.259.07:47:31.55#ibcon#first serial, iclass 22, count 2 2006.259.07:47:31.55#ibcon#enter sib2, iclass 22, count 2 2006.259.07:47:31.55#ibcon#flushed, iclass 22, count 2 2006.259.07:47:31.55#ibcon#about to write, iclass 22, count 2 2006.259.07:47:31.55#ibcon#wrote, iclass 22, count 2 2006.259.07:47:31.55#ibcon#about to read 3, iclass 22, count 2 2006.259.07:47:31.57#ibcon#read 3, iclass 22, count 2 2006.259.07:47:31.57#ibcon#about to read 4, iclass 22, count 2 2006.259.07:47:31.57#ibcon#read 4, iclass 22, count 2 2006.259.07:47:31.57#ibcon#about to read 5, iclass 22, count 2 2006.259.07:47:31.57#ibcon#read 5, iclass 22, count 2 2006.259.07:47:31.57#ibcon#about to read 6, iclass 22, count 2 2006.259.07:47:31.57#ibcon#read 6, iclass 22, count 2 2006.259.07:47:31.57#ibcon#end of sib2, iclass 22, count 2 2006.259.07:47:31.57#ibcon#*mode == 0, iclass 22, count 2 2006.259.07:47:31.57#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.259.07:47:31.57#ibcon#[25=AT07-06\r\n] 2006.259.07:47:31.57#ibcon#*before write, iclass 22, count 2 2006.259.07:47:31.57#ibcon#enter sib2, iclass 22, count 2 2006.259.07:47:31.57#ibcon#flushed, iclass 22, count 2 2006.259.07:47:31.57#ibcon#about to write, iclass 22, count 2 2006.259.07:47:31.57#ibcon#wrote, iclass 22, count 2 2006.259.07:47:31.57#ibcon#about to read 3, iclass 22, count 2 2006.259.07:47:31.60#ibcon#read 3, iclass 22, count 2 2006.259.07:47:31.60#ibcon#about to read 4, iclass 22, count 2 2006.259.07:47:31.60#ibcon#read 4, iclass 22, count 2 2006.259.07:47:31.60#ibcon#about to read 5, iclass 22, count 2 2006.259.07:47:31.60#ibcon#read 5, iclass 22, count 2 2006.259.07:47:31.60#ibcon#about to read 6, iclass 22, count 2 2006.259.07:47:31.60#ibcon#read 6, iclass 22, count 2 2006.259.07:47:31.60#ibcon#end of sib2, iclass 22, count 2 2006.259.07:47:31.60#ibcon#*after write, iclass 22, count 2 2006.259.07:47:31.60#ibcon#*before return 0, iclass 22, count 2 2006.259.07:47:31.60#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.259.07:47:31.60#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.259.07:47:31.60#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.259.07:47:31.60#ibcon#ireg 7 cls_cnt 0 2006.259.07:47:31.60#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.259.07:47:31.72#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.259.07:47:31.72#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.259.07:47:31.72#ibcon#enter wrdev, iclass 22, count 0 2006.259.07:47:31.72#ibcon#first serial, iclass 22, count 0 2006.259.07:47:31.72#ibcon#enter sib2, iclass 22, count 0 2006.259.07:47:31.72#ibcon#flushed, iclass 22, count 0 2006.259.07:47:31.72#ibcon#about to write, iclass 22, count 0 2006.259.07:47:31.72#ibcon#wrote, iclass 22, count 0 2006.259.07:47:31.72#ibcon#about to read 3, iclass 22, count 0 2006.259.07:47:31.74#ibcon#read 3, iclass 22, count 0 2006.259.07:47:31.74#ibcon#about to read 4, iclass 22, count 0 2006.259.07:47:31.74#ibcon#read 4, iclass 22, count 0 2006.259.07:47:31.74#ibcon#about to read 5, iclass 22, count 0 2006.259.07:47:31.74#ibcon#read 5, iclass 22, count 0 2006.259.07:47:31.74#ibcon#about to read 6, iclass 22, count 0 2006.259.07:47:31.74#ibcon#read 6, iclass 22, count 0 2006.259.07:47:31.74#ibcon#end of sib2, iclass 22, count 0 2006.259.07:47:31.74#ibcon#*mode == 0, iclass 22, count 0 2006.259.07:47:31.74#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.259.07:47:31.74#ibcon#[25=USB\r\n] 2006.259.07:47:31.74#ibcon#*before write, iclass 22, count 0 2006.259.07:47:31.74#ibcon#enter sib2, iclass 22, count 0 2006.259.07:47:31.74#ibcon#flushed, iclass 22, count 0 2006.259.07:47:31.74#ibcon#about to write, iclass 22, count 0 2006.259.07:47:31.74#ibcon#wrote, iclass 22, count 0 2006.259.07:47:31.74#ibcon#about to read 3, iclass 22, count 0 2006.259.07:47:31.77#ibcon#read 3, iclass 22, count 0 2006.259.07:47:31.77#ibcon#about to read 4, iclass 22, count 0 2006.259.07:47:31.77#ibcon#read 4, iclass 22, count 0 2006.259.07:47:31.77#ibcon#about to read 5, iclass 22, count 0 2006.259.07:47:31.77#ibcon#read 5, iclass 22, count 0 2006.259.07:47:31.77#ibcon#about to read 6, iclass 22, count 0 2006.259.07:47:31.77#ibcon#read 6, iclass 22, count 0 2006.259.07:47:31.77#ibcon#end of sib2, iclass 22, count 0 2006.259.07:47:31.77#ibcon#*after write, iclass 22, count 0 2006.259.07:47:31.77#ibcon#*before return 0, iclass 22, count 0 2006.259.07:47:31.77#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.259.07:47:31.77#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.259.07:47:31.77#ibcon#about to clear, iclass 22 cls_cnt 0 2006.259.07:47:31.77#ibcon#cleared, iclass 22 cls_cnt 0 2006.259.07:47:31.77$vc4f8/valo=8,852.99 2006.259.07:47:31.77#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.259.07:47:31.77#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.259.07:47:31.77#ibcon#ireg 17 cls_cnt 0 2006.259.07:47:31.77#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.259.07:47:31.77#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.259.07:47:31.77#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.259.07:47:31.77#ibcon#enter wrdev, iclass 24, count 0 2006.259.07:47:31.77#ibcon#first serial, iclass 24, count 0 2006.259.07:47:31.77#ibcon#enter sib2, iclass 24, count 0 2006.259.07:47:31.77#ibcon#flushed, iclass 24, count 0 2006.259.07:47:31.77#ibcon#about to write, iclass 24, count 0 2006.259.07:47:31.77#ibcon#wrote, iclass 24, count 0 2006.259.07:47:31.77#ibcon#about to read 3, iclass 24, count 0 2006.259.07:47:31.79#ibcon#read 3, iclass 24, count 0 2006.259.07:47:31.79#ibcon#about to read 4, iclass 24, count 0 2006.259.07:47:31.79#ibcon#read 4, iclass 24, count 0 2006.259.07:47:31.79#ibcon#about to read 5, iclass 24, count 0 2006.259.07:47:31.79#ibcon#read 5, iclass 24, count 0 2006.259.07:47:31.79#ibcon#about to read 6, iclass 24, count 0 2006.259.07:47:31.79#ibcon#read 6, iclass 24, count 0 2006.259.07:47:31.79#ibcon#end of sib2, iclass 24, count 0 2006.259.07:47:31.79#ibcon#*mode == 0, iclass 24, count 0 2006.259.07:47:31.79#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.259.07:47:31.79#ibcon#[26=FRQ=08,852.99\r\n] 2006.259.07:47:31.79#ibcon#*before write, iclass 24, count 0 2006.259.07:47:31.79#ibcon#enter sib2, iclass 24, count 0 2006.259.07:47:31.79#ibcon#flushed, iclass 24, count 0 2006.259.07:47:31.79#ibcon#about to write, iclass 24, count 0 2006.259.07:47:31.79#ibcon#wrote, iclass 24, count 0 2006.259.07:47:31.79#ibcon#about to read 3, iclass 24, count 0 2006.259.07:47:31.84#ibcon#read 3, iclass 24, count 0 2006.259.07:47:31.84#ibcon#about to read 4, iclass 24, count 0 2006.259.07:47:31.84#ibcon#read 4, iclass 24, count 0 2006.259.07:47:31.84#ibcon#about to read 5, iclass 24, count 0 2006.259.07:47:31.84#ibcon#read 5, iclass 24, count 0 2006.259.07:47:31.84#ibcon#about to read 6, iclass 24, count 0 2006.259.07:47:31.84#ibcon#read 6, iclass 24, count 0 2006.259.07:47:31.84#ibcon#end of sib2, iclass 24, count 0 2006.259.07:47:31.84#ibcon#*after write, iclass 24, count 0 2006.259.07:47:31.84#ibcon#*before return 0, iclass 24, count 0 2006.259.07:47:31.84#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.259.07:47:31.84#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.259.07:47:31.84#ibcon#about to clear, iclass 24 cls_cnt 0 2006.259.07:47:31.84#ibcon#cleared, iclass 24 cls_cnt 0 2006.259.07:47:31.84$vc4f8/va=8,6 2006.259.07:47:31.84#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.259.07:47:31.84#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.259.07:47:31.84#ibcon#ireg 11 cls_cnt 2 2006.259.07:47:31.84#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.259.07:47:31.89#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.259.07:47:31.89#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.259.07:47:31.89#ibcon#enter wrdev, iclass 26, count 2 2006.259.07:47:31.89#ibcon#first serial, iclass 26, count 2 2006.259.07:47:31.89#ibcon#enter sib2, iclass 26, count 2 2006.259.07:47:31.89#ibcon#flushed, iclass 26, count 2 2006.259.07:47:31.89#ibcon#about to write, iclass 26, count 2 2006.259.07:47:31.89#ibcon#wrote, iclass 26, count 2 2006.259.07:47:31.89#ibcon#about to read 3, iclass 26, count 2 2006.259.07:47:31.91#ibcon#read 3, iclass 26, count 2 2006.259.07:47:31.91#ibcon#about to read 4, iclass 26, count 2 2006.259.07:47:31.91#ibcon#read 4, iclass 26, count 2 2006.259.07:47:31.91#ibcon#about to read 5, iclass 26, count 2 2006.259.07:47:31.91#ibcon#read 5, iclass 26, count 2 2006.259.07:47:31.91#ibcon#about to read 6, iclass 26, count 2 2006.259.07:47:31.91#ibcon#read 6, iclass 26, count 2 2006.259.07:47:31.91#ibcon#end of sib2, iclass 26, count 2 2006.259.07:47:31.91#ibcon#*mode == 0, iclass 26, count 2 2006.259.07:47:31.91#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.259.07:47:31.91#ibcon#[25=AT08-06\r\n] 2006.259.07:47:31.91#ibcon#*before write, iclass 26, count 2 2006.259.07:47:31.91#ibcon#enter sib2, iclass 26, count 2 2006.259.07:47:31.91#ibcon#flushed, iclass 26, count 2 2006.259.07:47:31.91#ibcon#about to write, iclass 26, count 2 2006.259.07:47:31.91#ibcon#wrote, iclass 26, count 2 2006.259.07:47:31.91#ibcon#about to read 3, iclass 26, count 2 2006.259.07:47:31.94#ibcon#read 3, iclass 26, count 2 2006.259.07:47:31.94#ibcon#about to read 4, iclass 26, count 2 2006.259.07:47:31.94#ibcon#read 4, iclass 26, count 2 2006.259.07:47:31.94#ibcon#about to read 5, iclass 26, count 2 2006.259.07:47:31.94#ibcon#read 5, iclass 26, count 2 2006.259.07:47:31.94#ibcon#about to read 6, iclass 26, count 2 2006.259.07:47:31.94#ibcon#read 6, iclass 26, count 2 2006.259.07:47:31.94#ibcon#end of sib2, iclass 26, count 2 2006.259.07:47:31.94#ibcon#*after write, iclass 26, count 2 2006.259.07:47:31.94#ibcon#*before return 0, iclass 26, count 2 2006.259.07:47:31.94#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.259.07:47:31.94#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.259.07:47:31.94#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.259.07:47:31.94#ibcon#ireg 7 cls_cnt 0 2006.259.07:47:31.94#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.259.07:47:32.06#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.259.07:47:32.06#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.259.07:47:32.06#ibcon#enter wrdev, iclass 26, count 0 2006.259.07:47:32.06#ibcon#first serial, iclass 26, count 0 2006.259.07:47:32.06#ibcon#enter sib2, iclass 26, count 0 2006.259.07:47:32.06#ibcon#flushed, iclass 26, count 0 2006.259.07:47:32.06#ibcon#about to write, iclass 26, count 0 2006.259.07:47:32.06#ibcon#wrote, iclass 26, count 0 2006.259.07:47:32.06#ibcon#about to read 3, iclass 26, count 0 2006.259.07:47:32.08#ibcon#read 3, iclass 26, count 0 2006.259.07:47:32.08#ibcon#about to read 4, iclass 26, count 0 2006.259.07:47:32.08#ibcon#read 4, iclass 26, count 0 2006.259.07:47:32.08#ibcon#about to read 5, iclass 26, count 0 2006.259.07:47:32.08#ibcon#read 5, iclass 26, count 0 2006.259.07:47:32.08#ibcon#about to read 6, iclass 26, count 0 2006.259.07:47:32.08#ibcon#read 6, iclass 26, count 0 2006.259.07:47:32.08#ibcon#end of sib2, iclass 26, count 0 2006.259.07:47:32.08#ibcon#*mode == 0, iclass 26, count 0 2006.259.07:47:32.08#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.259.07:47:32.08#ibcon#[25=USB\r\n] 2006.259.07:47:32.08#ibcon#*before write, iclass 26, count 0 2006.259.07:47:32.08#ibcon#enter sib2, iclass 26, count 0 2006.259.07:47:32.08#ibcon#flushed, iclass 26, count 0 2006.259.07:47:32.08#ibcon#about to write, iclass 26, count 0 2006.259.07:47:32.08#ibcon#wrote, iclass 26, count 0 2006.259.07:47:32.08#ibcon#about to read 3, iclass 26, count 0 2006.259.07:47:32.11#ibcon#read 3, iclass 26, count 0 2006.259.07:47:32.11#ibcon#about to read 4, iclass 26, count 0 2006.259.07:47:32.11#ibcon#read 4, iclass 26, count 0 2006.259.07:47:32.11#ibcon#about to read 5, iclass 26, count 0 2006.259.07:47:32.11#ibcon#read 5, iclass 26, count 0 2006.259.07:47:32.11#ibcon#about to read 6, iclass 26, count 0 2006.259.07:47:32.11#ibcon#read 6, iclass 26, count 0 2006.259.07:47:32.11#ibcon#end of sib2, iclass 26, count 0 2006.259.07:47:32.11#ibcon#*after write, iclass 26, count 0 2006.259.07:47:32.11#ibcon#*before return 0, iclass 26, count 0 2006.259.07:47:32.11#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.259.07:47:32.11#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.259.07:47:32.11#ibcon#about to clear, iclass 26 cls_cnt 0 2006.259.07:47:32.11#ibcon#cleared, iclass 26 cls_cnt 0 2006.259.07:47:32.11$vc4f8/vblo=1,632.99 2006.259.07:47:32.11#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.259.07:47:32.11#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.259.07:47:32.11#ibcon#ireg 17 cls_cnt 0 2006.259.07:47:32.11#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.259.07:47:32.11#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.259.07:47:32.11#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.259.07:47:32.11#ibcon#enter wrdev, iclass 28, count 0 2006.259.07:47:32.11#ibcon#first serial, iclass 28, count 0 2006.259.07:47:32.11#ibcon#enter sib2, iclass 28, count 0 2006.259.07:47:32.11#ibcon#flushed, iclass 28, count 0 2006.259.07:47:32.11#ibcon#about to write, iclass 28, count 0 2006.259.07:47:32.11#ibcon#wrote, iclass 28, count 0 2006.259.07:47:32.11#ibcon#about to read 3, iclass 28, count 0 2006.259.07:47:32.13#ibcon#read 3, iclass 28, count 0 2006.259.07:47:32.13#ibcon#about to read 4, iclass 28, count 0 2006.259.07:47:32.13#ibcon#read 4, iclass 28, count 0 2006.259.07:47:32.13#ibcon#about to read 5, iclass 28, count 0 2006.259.07:47:32.13#ibcon#read 5, iclass 28, count 0 2006.259.07:47:32.13#ibcon#about to read 6, iclass 28, count 0 2006.259.07:47:32.13#ibcon#read 6, iclass 28, count 0 2006.259.07:47:32.13#ibcon#end of sib2, iclass 28, count 0 2006.259.07:47:32.13#ibcon#*mode == 0, iclass 28, count 0 2006.259.07:47:32.13#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.259.07:47:32.13#ibcon#[28=FRQ=01,632.99\r\n] 2006.259.07:47:32.13#ibcon#*before write, iclass 28, count 0 2006.259.07:47:32.13#ibcon#enter sib2, iclass 28, count 0 2006.259.07:47:32.13#ibcon#flushed, iclass 28, count 0 2006.259.07:47:32.13#ibcon#about to write, iclass 28, count 0 2006.259.07:47:32.13#ibcon#wrote, iclass 28, count 0 2006.259.07:47:32.13#ibcon#about to read 3, iclass 28, count 0 2006.259.07:47:32.17#ibcon#read 3, iclass 28, count 0 2006.259.07:47:32.17#ibcon#about to read 4, iclass 28, count 0 2006.259.07:47:32.17#ibcon#read 4, iclass 28, count 0 2006.259.07:47:32.17#ibcon#about to read 5, iclass 28, count 0 2006.259.07:47:32.17#ibcon#read 5, iclass 28, count 0 2006.259.07:47:32.17#ibcon#about to read 6, iclass 28, count 0 2006.259.07:47:32.17#ibcon#read 6, iclass 28, count 0 2006.259.07:47:32.17#ibcon#end of sib2, iclass 28, count 0 2006.259.07:47:32.17#ibcon#*after write, iclass 28, count 0 2006.259.07:47:32.17#ibcon#*before return 0, iclass 28, count 0 2006.259.07:47:32.17#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.259.07:47:32.17#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.259.07:47:32.17#ibcon#about to clear, iclass 28 cls_cnt 0 2006.259.07:47:32.17#ibcon#cleared, iclass 28 cls_cnt 0 2006.259.07:47:32.17$vc4f8/vb=1,4 2006.259.07:47:32.17#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.259.07:47:32.17#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.259.07:47:32.17#ibcon#ireg 11 cls_cnt 2 2006.259.07:47:32.17#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.259.07:47:32.17#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.259.07:47:32.17#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.259.07:47:32.17#ibcon#enter wrdev, iclass 30, count 2 2006.259.07:47:32.17#ibcon#first serial, iclass 30, count 2 2006.259.07:47:32.17#ibcon#enter sib2, iclass 30, count 2 2006.259.07:47:32.17#ibcon#flushed, iclass 30, count 2 2006.259.07:47:32.17#ibcon#about to write, iclass 30, count 2 2006.259.07:47:32.17#ibcon#wrote, iclass 30, count 2 2006.259.07:47:32.17#ibcon#about to read 3, iclass 30, count 2 2006.259.07:47:32.19#ibcon#read 3, iclass 30, count 2 2006.259.07:47:32.19#ibcon#about to read 4, iclass 30, count 2 2006.259.07:47:32.19#ibcon#read 4, iclass 30, count 2 2006.259.07:47:32.19#ibcon#about to read 5, iclass 30, count 2 2006.259.07:47:32.19#ibcon#read 5, iclass 30, count 2 2006.259.07:47:32.19#ibcon#about to read 6, iclass 30, count 2 2006.259.07:47:32.19#ibcon#read 6, iclass 30, count 2 2006.259.07:47:32.19#ibcon#end of sib2, iclass 30, count 2 2006.259.07:47:32.19#ibcon#*mode == 0, iclass 30, count 2 2006.259.07:47:32.19#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.259.07:47:32.19#ibcon#[27=AT01-04\r\n] 2006.259.07:47:32.19#ibcon#*before write, iclass 30, count 2 2006.259.07:47:32.19#ibcon#enter sib2, iclass 30, count 2 2006.259.07:47:32.19#ibcon#flushed, iclass 30, count 2 2006.259.07:47:32.19#ibcon#about to write, iclass 30, count 2 2006.259.07:47:32.19#ibcon#wrote, iclass 30, count 2 2006.259.07:47:32.19#ibcon#about to read 3, iclass 30, count 2 2006.259.07:47:32.22#ibcon#read 3, iclass 30, count 2 2006.259.07:47:32.22#ibcon#about to read 4, iclass 30, count 2 2006.259.07:47:32.22#ibcon#read 4, iclass 30, count 2 2006.259.07:47:32.22#ibcon#about to read 5, iclass 30, count 2 2006.259.07:47:32.22#ibcon#read 5, iclass 30, count 2 2006.259.07:47:32.22#ibcon#about to read 6, iclass 30, count 2 2006.259.07:47:32.22#ibcon#read 6, iclass 30, count 2 2006.259.07:47:32.22#ibcon#end of sib2, iclass 30, count 2 2006.259.07:47:32.22#ibcon#*after write, iclass 30, count 2 2006.259.07:47:32.22#ibcon#*before return 0, iclass 30, count 2 2006.259.07:47:32.22#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.259.07:47:32.22#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.259.07:47:32.22#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.259.07:47:32.22#ibcon#ireg 7 cls_cnt 0 2006.259.07:47:32.22#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.259.07:47:32.34#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.259.07:47:32.34#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.259.07:47:32.34#ibcon#enter wrdev, iclass 30, count 0 2006.259.07:47:32.34#ibcon#first serial, iclass 30, count 0 2006.259.07:47:32.34#ibcon#enter sib2, iclass 30, count 0 2006.259.07:47:32.34#ibcon#flushed, iclass 30, count 0 2006.259.07:47:32.34#ibcon#about to write, iclass 30, count 0 2006.259.07:47:32.34#ibcon#wrote, iclass 30, count 0 2006.259.07:47:32.34#ibcon#about to read 3, iclass 30, count 0 2006.259.07:47:32.36#ibcon#read 3, iclass 30, count 0 2006.259.07:47:32.36#ibcon#about to read 4, iclass 30, count 0 2006.259.07:47:32.36#ibcon#read 4, iclass 30, count 0 2006.259.07:47:32.36#ibcon#about to read 5, iclass 30, count 0 2006.259.07:47:32.36#ibcon#read 5, iclass 30, count 0 2006.259.07:47:32.36#ibcon#about to read 6, iclass 30, count 0 2006.259.07:47:32.36#ibcon#read 6, iclass 30, count 0 2006.259.07:47:32.36#ibcon#end of sib2, iclass 30, count 0 2006.259.07:47:32.36#ibcon#*mode == 0, iclass 30, count 0 2006.259.07:47:32.36#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.259.07:47:32.36#ibcon#[27=USB\r\n] 2006.259.07:47:32.36#ibcon#*before write, iclass 30, count 0 2006.259.07:47:32.36#ibcon#enter sib2, iclass 30, count 0 2006.259.07:47:32.36#ibcon#flushed, iclass 30, count 0 2006.259.07:47:32.36#ibcon#about to write, iclass 30, count 0 2006.259.07:47:32.36#ibcon#wrote, iclass 30, count 0 2006.259.07:47:32.36#ibcon#about to read 3, iclass 30, count 0 2006.259.07:47:32.39#ibcon#read 3, iclass 30, count 0 2006.259.07:47:32.39#ibcon#about to read 4, iclass 30, count 0 2006.259.07:47:32.39#ibcon#read 4, iclass 30, count 0 2006.259.07:47:32.39#ibcon#about to read 5, iclass 30, count 0 2006.259.07:47:32.39#ibcon#read 5, iclass 30, count 0 2006.259.07:47:32.39#ibcon#about to read 6, iclass 30, count 0 2006.259.07:47:32.39#ibcon#read 6, iclass 30, count 0 2006.259.07:47:32.39#ibcon#end of sib2, iclass 30, count 0 2006.259.07:47:32.39#ibcon#*after write, iclass 30, count 0 2006.259.07:47:32.39#ibcon#*before return 0, iclass 30, count 0 2006.259.07:47:32.39#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.259.07:47:32.39#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.259.07:47:32.39#ibcon#about to clear, iclass 30 cls_cnt 0 2006.259.07:47:32.39#ibcon#cleared, iclass 30 cls_cnt 0 2006.259.07:47:32.39$vc4f8/vblo=2,640.99 2006.259.07:47:32.39#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.259.07:47:32.39#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.259.07:47:32.39#ibcon#ireg 17 cls_cnt 0 2006.259.07:47:32.39#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.259.07:47:32.39#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.259.07:47:32.39#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.259.07:47:32.39#ibcon#enter wrdev, iclass 32, count 0 2006.259.07:47:32.39#ibcon#first serial, iclass 32, count 0 2006.259.07:47:32.39#ibcon#enter sib2, iclass 32, count 0 2006.259.07:47:32.39#ibcon#flushed, iclass 32, count 0 2006.259.07:47:32.39#ibcon#about to write, iclass 32, count 0 2006.259.07:47:32.39#ibcon#wrote, iclass 32, count 0 2006.259.07:47:32.39#ibcon#about to read 3, iclass 32, count 0 2006.259.07:47:32.41#ibcon#read 3, iclass 32, count 0 2006.259.07:47:32.41#ibcon#about to read 4, iclass 32, count 0 2006.259.07:47:32.41#ibcon#read 4, iclass 32, count 0 2006.259.07:47:32.41#ibcon#about to read 5, iclass 32, count 0 2006.259.07:47:32.41#ibcon#read 5, iclass 32, count 0 2006.259.07:47:32.41#ibcon#about to read 6, iclass 32, count 0 2006.259.07:47:32.41#ibcon#read 6, iclass 32, count 0 2006.259.07:47:32.41#ibcon#end of sib2, iclass 32, count 0 2006.259.07:47:32.41#ibcon#*mode == 0, iclass 32, count 0 2006.259.07:47:32.41#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.259.07:47:32.41#ibcon#[28=FRQ=02,640.99\r\n] 2006.259.07:47:32.41#ibcon#*before write, iclass 32, count 0 2006.259.07:47:32.41#ibcon#enter sib2, iclass 32, count 0 2006.259.07:47:32.41#ibcon#flushed, iclass 32, count 0 2006.259.07:47:32.41#ibcon#about to write, iclass 32, count 0 2006.259.07:47:32.41#ibcon#wrote, iclass 32, count 0 2006.259.07:47:32.41#ibcon#about to read 3, iclass 32, count 0 2006.259.07:47:32.45#ibcon#read 3, iclass 32, count 0 2006.259.07:47:32.45#ibcon#about to read 4, iclass 32, count 0 2006.259.07:47:32.45#ibcon#read 4, iclass 32, count 0 2006.259.07:47:32.45#ibcon#about to read 5, iclass 32, count 0 2006.259.07:47:32.45#ibcon#read 5, iclass 32, count 0 2006.259.07:47:32.45#ibcon#about to read 6, iclass 32, count 0 2006.259.07:47:32.45#ibcon#read 6, iclass 32, count 0 2006.259.07:47:32.45#ibcon#end of sib2, iclass 32, count 0 2006.259.07:47:32.45#ibcon#*after write, iclass 32, count 0 2006.259.07:47:32.45#ibcon#*before return 0, iclass 32, count 0 2006.259.07:47:32.45#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.259.07:47:32.45#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.259.07:47:32.45#ibcon#about to clear, iclass 32 cls_cnt 0 2006.259.07:47:32.45#ibcon#cleared, iclass 32 cls_cnt 0 2006.259.07:47:32.45$vc4f8/vb=2,5 2006.259.07:47:32.45#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.259.07:47:32.45#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.259.07:47:32.45#ibcon#ireg 11 cls_cnt 2 2006.259.07:47:32.45#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.259.07:47:32.51#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.259.07:47:32.51#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.259.07:47:32.51#ibcon#enter wrdev, iclass 34, count 2 2006.259.07:47:32.51#ibcon#first serial, iclass 34, count 2 2006.259.07:47:32.51#ibcon#enter sib2, iclass 34, count 2 2006.259.07:47:32.51#ibcon#flushed, iclass 34, count 2 2006.259.07:47:32.51#ibcon#about to write, iclass 34, count 2 2006.259.07:47:32.51#ibcon#wrote, iclass 34, count 2 2006.259.07:47:32.51#ibcon#about to read 3, iclass 34, count 2 2006.259.07:47:32.53#ibcon#read 3, iclass 34, count 2 2006.259.07:47:32.53#ibcon#about to read 4, iclass 34, count 2 2006.259.07:47:32.53#ibcon#read 4, iclass 34, count 2 2006.259.07:47:32.53#ibcon#about to read 5, iclass 34, count 2 2006.259.07:47:32.53#ibcon#read 5, iclass 34, count 2 2006.259.07:47:32.53#ibcon#about to read 6, iclass 34, count 2 2006.259.07:47:32.53#ibcon#read 6, iclass 34, count 2 2006.259.07:47:32.53#ibcon#end of sib2, iclass 34, count 2 2006.259.07:47:32.53#ibcon#*mode == 0, iclass 34, count 2 2006.259.07:47:32.53#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.259.07:47:32.53#ibcon#[27=AT02-05\r\n] 2006.259.07:47:32.53#ibcon#*before write, iclass 34, count 2 2006.259.07:47:32.53#ibcon#enter sib2, iclass 34, count 2 2006.259.07:47:32.53#ibcon#flushed, iclass 34, count 2 2006.259.07:47:32.53#ibcon#about to write, iclass 34, count 2 2006.259.07:47:32.53#ibcon#wrote, iclass 34, count 2 2006.259.07:47:32.53#ibcon#about to read 3, iclass 34, count 2 2006.259.07:47:32.56#ibcon#read 3, iclass 34, count 2 2006.259.07:47:32.56#ibcon#about to read 4, iclass 34, count 2 2006.259.07:47:32.56#ibcon#read 4, iclass 34, count 2 2006.259.07:47:32.56#ibcon#about to read 5, iclass 34, count 2 2006.259.07:47:32.56#ibcon#read 5, iclass 34, count 2 2006.259.07:47:32.56#ibcon#about to read 6, iclass 34, count 2 2006.259.07:47:32.56#ibcon#read 6, iclass 34, count 2 2006.259.07:47:32.56#ibcon#end of sib2, iclass 34, count 2 2006.259.07:47:32.56#ibcon#*after write, iclass 34, count 2 2006.259.07:47:32.56#ibcon#*before return 0, iclass 34, count 2 2006.259.07:47:32.56#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.259.07:47:32.56#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.259.07:47:32.56#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.259.07:47:32.56#ibcon#ireg 7 cls_cnt 0 2006.259.07:47:32.56#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.259.07:47:32.68#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.259.07:47:32.68#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.259.07:47:32.68#ibcon#enter wrdev, iclass 34, count 0 2006.259.07:47:32.68#ibcon#first serial, iclass 34, count 0 2006.259.07:47:32.68#ibcon#enter sib2, iclass 34, count 0 2006.259.07:47:32.68#ibcon#flushed, iclass 34, count 0 2006.259.07:47:32.68#ibcon#about to write, iclass 34, count 0 2006.259.07:47:32.68#ibcon#wrote, iclass 34, count 0 2006.259.07:47:32.68#ibcon#about to read 3, iclass 34, count 0 2006.259.07:47:32.70#ibcon#read 3, iclass 34, count 0 2006.259.07:47:32.70#ibcon#about to read 4, iclass 34, count 0 2006.259.07:47:32.70#ibcon#read 4, iclass 34, count 0 2006.259.07:47:32.70#ibcon#about to read 5, iclass 34, count 0 2006.259.07:47:32.70#ibcon#read 5, iclass 34, count 0 2006.259.07:47:32.70#ibcon#about to read 6, iclass 34, count 0 2006.259.07:47:32.70#ibcon#read 6, iclass 34, count 0 2006.259.07:47:32.70#ibcon#end of sib2, iclass 34, count 0 2006.259.07:47:32.70#ibcon#*mode == 0, iclass 34, count 0 2006.259.07:47:32.70#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.259.07:47:32.70#ibcon#[27=USB\r\n] 2006.259.07:47:32.70#ibcon#*before write, iclass 34, count 0 2006.259.07:47:32.70#ibcon#enter sib2, iclass 34, count 0 2006.259.07:47:32.70#ibcon#flushed, iclass 34, count 0 2006.259.07:47:32.70#ibcon#about to write, iclass 34, count 0 2006.259.07:47:32.70#ibcon#wrote, iclass 34, count 0 2006.259.07:47:32.70#ibcon#about to read 3, iclass 34, count 0 2006.259.07:47:32.73#ibcon#read 3, iclass 34, count 0 2006.259.07:47:32.73#ibcon#about to read 4, iclass 34, count 0 2006.259.07:47:32.73#ibcon#read 4, iclass 34, count 0 2006.259.07:47:32.73#ibcon#about to read 5, iclass 34, count 0 2006.259.07:47:32.73#ibcon#read 5, iclass 34, count 0 2006.259.07:47:32.73#ibcon#about to read 6, iclass 34, count 0 2006.259.07:47:32.73#ibcon#read 6, iclass 34, count 0 2006.259.07:47:32.73#ibcon#end of sib2, iclass 34, count 0 2006.259.07:47:32.73#ibcon#*after write, iclass 34, count 0 2006.259.07:47:32.73#ibcon#*before return 0, iclass 34, count 0 2006.259.07:47:32.73#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.259.07:47:32.73#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.259.07:47:32.73#ibcon#about to clear, iclass 34 cls_cnt 0 2006.259.07:47:32.73#ibcon#cleared, iclass 34 cls_cnt 0 2006.259.07:47:32.73$vc4f8/vblo=3,656.99 2006.259.07:47:32.73#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.259.07:47:32.73#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.259.07:47:32.73#ibcon#ireg 17 cls_cnt 0 2006.259.07:47:32.73#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.259.07:47:32.73#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.259.07:47:32.73#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.259.07:47:32.73#ibcon#enter wrdev, iclass 36, count 0 2006.259.07:47:32.73#ibcon#first serial, iclass 36, count 0 2006.259.07:47:32.73#ibcon#enter sib2, iclass 36, count 0 2006.259.07:47:32.73#ibcon#flushed, iclass 36, count 0 2006.259.07:47:32.73#ibcon#about to write, iclass 36, count 0 2006.259.07:47:32.73#ibcon#wrote, iclass 36, count 0 2006.259.07:47:32.73#ibcon#about to read 3, iclass 36, count 0 2006.259.07:47:32.75#ibcon#read 3, iclass 36, count 0 2006.259.07:47:32.75#ibcon#about to read 4, iclass 36, count 0 2006.259.07:47:32.75#ibcon#read 4, iclass 36, count 0 2006.259.07:47:32.75#ibcon#about to read 5, iclass 36, count 0 2006.259.07:47:32.75#ibcon#read 5, iclass 36, count 0 2006.259.07:47:32.75#ibcon#about to read 6, iclass 36, count 0 2006.259.07:47:32.75#ibcon#read 6, iclass 36, count 0 2006.259.07:47:32.75#ibcon#end of sib2, iclass 36, count 0 2006.259.07:47:32.75#ibcon#*mode == 0, iclass 36, count 0 2006.259.07:47:32.75#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.259.07:47:32.75#ibcon#[28=FRQ=03,656.99\r\n] 2006.259.07:47:32.75#ibcon#*before write, iclass 36, count 0 2006.259.07:47:32.75#ibcon#enter sib2, iclass 36, count 0 2006.259.07:47:32.75#ibcon#flushed, iclass 36, count 0 2006.259.07:47:32.75#ibcon#about to write, iclass 36, count 0 2006.259.07:47:32.75#ibcon#wrote, iclass 36, count 0 2006.259.07:47:32.75#ibcon#about to read 3, iclass 36, count 0 2006.259.07:47:32.79#ibcon#read 3, iclass 36, count 0 2006.259.07:47:32.79#ibcon#about to read 4, iclass 36, count 0 2006.259.07:47:32.79#ibcon#read 4, iclass 36, count 0 2006.259.07:47:32.79#ibcon#about to read 5, iclass 36, count 0 2006.259.07:47:32.79#ibcon#read 5, iclass 36, count 0 2006.259.07:47:32.79#ibcon#about to read 6, iclass 36, count 0 2006.259.07:47:32.79#ibcon#read 6, iclass 36, count 0 2006.259.07:47:32.79#ibcon#end of sib2, iclass 36, count 0 2006.259.07:47:32.79#ibcon#*after write, iclass 36, count 0 2006.259.07:47:32.79#ibcon#*before return 0, iclass 36, count 0 2006.259.07:47:32.79#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.259.07:47:32.79#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.259.07:47:32.79#ibcon#about to clear, iclass 36 cls_cnt 0 2006.259.07:47:32.79#ibcon#cleared, iclass 36 cls_cnt 0 2006.259.07:47:32.79$vc4f8/vb=3,4 2006.259.07:47:32.79#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.259.07:47:32.79#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.259.07:47:32.79#ibcon#ireg 11 cls_cnt 2 2006.259.07:47:32.79#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.259.07:47:32.85#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.259.07:47:32.85#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.259.07:47:32.85#ibcon#enter wrdev, iclass 38, count 2 2006.259.07:47:32.85#ibcon#first serial, iclass 38, count 2 2006.259.07:47:32.85#ibcon#enter sib2, iclass 38, count 2 2006.259.07:47:32.85#ibcon#flushed, iclass 38, count 2 2006.259.07:47:32.85#ibcon#about to write, iclass 38, count 2 2006.259.07:47:32.85#ibcon#wrote, iclass 38, count 2 2006.259.07:47:32.85#ibcon#about to read 3, iclass 38, count 2 2006.259.07:47:32.87#ibcon#read 3, iclass 38, count 2 2006.259.07:47:32.87#ibcon#about to read 4, iclass 38, count 2 2006.259.07:47:32.87#ibcon#read 4, iclass 38, count 2 2006.259.07:47:32.87#ibcon#about to read 5, iclass 38, count 2 2006.259.07:47:32.87#ibcon#read 5, iclass 38, count 2 2006.259.07:47:32.87#ibcon#about to read 6, iclass 38, count 2 2006.259.07:47:32.87#ibcon#read 6, iclass 38, count 2 2006.259.07:47:32.87#ibcon#end of sib2, iclass 38, count 2 2006.259.07:47:32.87#ibcon#*mode == 0, iclass 38, count 2 2006.259.07:47:32.87#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.259.07:47:32.87#ibcon#[27=AT03-04\r\n] 2006.259.07:47:32.87#ibcon#*before write, iclass 38, count 2 2006.259.07:47:32.87#ibcon#enter sib2, iclass 38, count 2 2006.259.07:47:32.87#ibcon#flushed, iclass 38, count 2 2006.259.07:47:32.87#ibcon#about to write, iclass 38, count 2 2006.259.07:47:32.87#ibcon#wrote, iclass 38, count 2 2006.259.07:47:32.87#ibcon#about to read 3, iclass 38, count 2 2006.259.07:47:32.90#ibcon#read 3, iclass 38, count 2 2006.259.07:47:32.90#ibcon#about to read 4, iclass 38, count 2 2006.259.07:47:32.90#ibcon#read 4, iclass 38, count 2 2006.259.07:47:32.90#ibcon#about to read 5, iclass 38, count 2 2006.259.07:47:32.90#ibcon#read 5, iclass 38, count 2 2006.259.07:47:32.90#ibcon#about to read 6, iclass 38, count 2 2006.259.07:47:32.90#ibcon#read 6, iclass 38, count 2 2006.259.07:47:32.90#ibcon#end of sib2, iclass 38, count 2 2006.259.07:47:32.90#ibcon#*after write, iclass 38, count 2 2006.259.07:47:32.90#ibcon#*before return 0, iclass 38, count 2 2006.259.07:47:32.90#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.259.07:47:32.90#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.259.07:47:32.90#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.259.07:47:32.90#ibcon#ireg 7 cls_cnt 0 2006.259.07:47:32.90#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.259.07:47:33.02#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.259.07:47:33.02#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.259.07:47:33.02#ibcon#enter wrdev, iclass 38, count 0 2006.259.07:47:33.02#ibcon#first serial, iclass 38, count 0 2006.259.07:47:33.02#ibcon#enter sib2, iclass 38, count 0 2006.259.07:47:33.02#ibcon#flushed, iclass 38, count 0 2006.259.07:47:33.02#ibcon#about to write, iclass 38, count 0 2006.259.07:47:33.02#ibcon#wrote, iclass 38, count 0 2006.259.07:47:33.02#ibcon#about to read 3, iclass 38, count 0 2006.259.07:47:33.04#ibcon#read 3, iclass 38, count 0 2006.259.07:47:33.04#ibcon#about to read 4, iclass 38, count 0 2006.259.07:47:33.04#ibcon#read 4, iclass 38, count 0 2006.259.07:47:33.04#ibcon#about to read 5, iclass 38, count 0 2006.259.07:47:33.04#ibcon#read 5, iclass 38, count 0 2006.259.07:47:33.04#ibcon#about to read 6, iclass 38, count 0 2006.259.07:47:33.04#ibcon#read 6, iclass 38, count 0 2006.259.07:47:33.04#ibcon#end of sib2, iclass 38, count 0 2006.259.07:47:33.04#ibcon#*mode == 0, iclass 38, count 0 2006.259.07:47:33.04#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.259.07:47:33.04#ibcon#[27=USB\r\n] 2006.259.07:47:33.04#ibcon#*before write, iclass 38, count 0 2006.259.07:47:33.04#ibcon#enter sib2, iclass 38, count 0 2006.259.07:47:33.04#ibcon#flushed, iclass 38, count 0 2006.259.07:47:33.04#ibcon#about to write, iclass 38, count 0 2006.259.07:47:33.04#ibcon#wrote, iclass 38, count 0 2006.259.07:47:33.04#ibcon#about to read 3, iclass 38, count 0 2006.259.07:47:33.07#ibcon#read 3, iclass 38, count 0 2006.259.07:47:33.07#ibcon#about to read 4, iclass 38, count 0 2006.259.07:47:33.07#ibcon#read 4, iclass 38, count 0 2006.259.07:47:33.07#ibcon#about to read 5, iclass 38, count 0 2006.259.07:47:33.07#ibcon#read 5, iclass 38, count 0 2006.259.07:47:33.07#ibcon#about to read 6, iclass 38, count 0 2006.259.07:47:33.07#ibcon#read 6, iclass 38, count 0 2006.259.07:47:33.07#ibcon#end of sib2, iclass 38, count 0 2006.259.07:47:33.07#ibcon#*after write, iclass 38, count 0 2006.259.07:47:33.07#ibcon#*before return 0, iclass 38, count 0 2006.259.07:47:33.07#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.259.07:47:33.07#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.259.07:47:33.07#ibcon#about to clear, iclass 38 cls_cnt 0 2006.259.07:47:33.07#ibcon#cleared, iclass 38 cls_cnt 0 2006.259.07:47:33.07$vc4f8/vblo=4,712.99 2006.259.07:47:33.07#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.259.07:47:33.07#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.259.07:47:33.07#ibcon#ireg 17 cls_cnt 0 2006.259.07:47:33.07#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.259.07:47:33.07#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.259.07:47:33.07#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.259.07:47:33.07#ibcon#enter wrdev, iclass 40, count 0 2006.259.07:47:33.07#ibcon#first serial, iclass 40, count 0 2006.259.07:47:33.07#ibcon#enter sib2, iclass 40, count 0 2006.259.07:47:33.07#ibcon#flushed, iclass 40, count 0 2006.259.07:47:33.07#ibcon#about to write, iclass 40, count 0 2006.259.07:47:33.07#ibcon#wrote, iclass 40, count 0 2006.259.07:47:33.07#ibcon#about to read 3, iclass 40, count 0 2006.259.07:47:33.09#ibcon#read 3, iclass 40, count 0 2006.259.07:47:33.09#ibcon#about to read 4, iclass 40, count 0 2006.259.07:47:33.09#ibcon#read 4, iclass 40, count 0 2006.259.07:47:33.09#ibcon#about to read 5, iclass 40, count 0 2006.259.07:47:33.09#ibcon#read 5, iclass 40, count 0 2006.259.07:47:33.09#ibcon#about to read 6, iclass 40, count 0 2006.259.07:47:33.09#ibcon#read 6, iclass 40, count 0 2006.259.07:47:33.09#ibcon#end of sib2, iclass 40, count 0 2006.259.07:47:33.09#ibcon#*mode == 0, iclass 40, count 0 2006.259.07:47:33.09#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.259.07:47:33.09#ibcon#[28=FRQ=04,712.99\r\n] 2006.259.07:47:33.09#ibcon#*before write, iclass 40, count 0 2006.259.07:47:33.09#ibcon#enter sib2, iclass 40, count 0 2006.259.07:47:33.09#ibcon#flushed, iclass 40, count 0 2006.259.07:47:33.09#ibcon#about to write, iclass 40, count 0 2006.259.07:47:33.09#ibcon#wrote, iclass 40, count 0 2006.259.07:47:33.09#ibcon#about to read 3, iclass 40, count 0 2006.259.07:47:33.13#ibcon#read 3, iclass 40, count 0 2006.259.07:47:33.13#ibcon#about to read 4, iclass 40, count 0 2006.259.07:47:33.13#ibcon#read 4, iclass 40, count 0 2006.259.07:47:33.13#ibcon#about to read 5, iclass 40, count 0 2006.259.07:47:33.13#ibcon#read 5, iclass 40, count 0 2006.259.07:47:33.13#ibcon#about to read 6, iclass 40, count 0 2006.259.07:47:33.13#ibcon#read 6, iclass 40, count 0 2006.259.07:47:33.13#ibcon#end of sib2, iclass 40, count 0 2006.259.07:47:33.13#ibcon#*after write, iclass 40, count 0 2006.259.07:47:33.13#ibcon#*before return 0, iclass 40, count 0 2006.259.07:47:33.13#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.259.07:47:33.13#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.259.07:47:33.13#ibcon#about to clear, iclass 40 cls_cnt 0 2006.259.07:47:33.13#ibcon#cleared, iclass 40 cls_cnt 0 2006.259.07:47:33.13$vc4f8/vb=4,5 2006.259.07:47:33.13#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.259.07:47:33.13#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.259.07:47:33.13#ibcon#ireg 11 cls_cnt 2 2006.259.07:47:33.13#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.259.07:47:33.19#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.259.07:47:33.19#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.259.07:47:33.19#ibcon#enter wrdev, iclass 4, count 2 2006.259.07:47:33.19#ibcon#first serial, iclass 4, count 2 2006.259.07:47:33.19#ibcon#enter sib2, iclass 4, count 2 2006.259.07:47:33.19#ibcon#flushed, iclass 4, count 2 2006.259.07:47:33.19#ibcon#about to write, iclass 4, count 2 2006.259.07:47:33.19#ibcon#wrote, iclass 4, count 2 2006.259.07:47:33.19#ibcon#about to read 3, iclass 4, count 2 2006.259.07:47:33.21#ibcon#read 3, iclass 4, count 2 2006.259.07:47:33.21#ibcon#about to read 4, iclass 4, count 2 2006.259.07:47:33.21#ibcon#read 4, iclass 4, count 2 2006.259.07:47:33.21#ibcon#about to read 5, iclass 4, count 2 2006.259.07:47:33.21#ibcon#read 5, iclass 4, count 2 2006.259.07:47:33.21#ibcon#about to read 6, iclass 4, count 2 2006.259.07:47:33.21#ibcon#read 6, iclass 4, count 2 2006.259.07:47:33.21#ibcon#end of sib2, iclass 4, count 2 2006.259.07:47:33.21#ibcon#*mode == 0, iclass 4, count 2 2006.259.07:47:33.21#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.259.07:47:33.21#ibcon#[27=AT04-05\r\n] 2006.259.07:47:33.21#ibcon#*before write, iclass 4, count 2 2006.259.07:47:33.21#ibcon#enter sib2, iclass 4, count 2 2006.259.07:47:33.21#ibcon#flushed, iclass 4, count 2 2006.259.07:47:33.21#ibcon#about to write, iclass 4, count 2 2006.259.07:47:33.21#ibcon#wrote, iclass 4, count 2 2006.259.07:47:33.21#ibcon#about to read 3, iclass 4, count 2 2006.259.07:47:33.24#ibcon#read 3, iclass 4, count 2 2006.259.07:47:33.24#ibcon#about to read 4, iclass 4, count 2 2006.259.07:47:33.24#ibcon#read 4, iclass 4, count 2 2006.259.07:47:33.24#ibcon#about to read 5, iclass 4, count 2 2006.259.07:47:33.24#ibcon#read 5, iclass 4, count 2 2006.259.07:47:33.24#ibcon#about to read 6, iclass 4, count 2 2006.259.07:47:33.24#ibcon#read 6, iclass 4, count 2 2006.259.07:47:33.24#ibcon#end of sib2, iclass 4, count 2 2006.259.07:47:33.24#ibcon#*after write, iclass 4, count 2 2006.259.07:47:33.24#ibcon#*before return 0, iclass 4, count 2 2006.259.07:47:33.24#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.259.07:47:33.24#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.259.07:47:33.24#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.259.07:47:33.24#ibcon#ireg 7 cls_cnt 0 2006.259.07:47:33.24#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.259.07:47:33.36#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.259.07:47:33.36#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.259.07:47:33.36#ibcon#enter wrdev, iclass 4, count 0 2006.259.07:47:33.36#ibcon#first serial, iclass 4, count 0 2006.259.07:47:33.36#ibcon#enter sib2, iclass 4, count 0 2006.259.07:47:33.36#ibcon#flushed, iclass 4, count 0 2006.259.07:47:33.36#ibcon#about to write, iclass 4, count 0 2006.259.07:47:33.36#ibcon#wrote, iclass 4, count 0 2006.259.07:47:33.36#ibcon#about to read 3, iclass 4, count 0 2006.259.07:47:33.38#ibcon#read 3, iclass 4, count 0 2006.259.07:47:33.38#ibcon#about to read 4, iclass 4, count 0 2006.259.07:47:33.38#ibcon#read 4, iclass 4, count 0 2006.259.07:47:33.38#ibcon#about to read 5, iclass 4, count 0 2006.259.07:47:33.38#ibcon#read 5, iclass 4, count 0 2006.259.07:47:33.38#ibcon#about to read 6, iclass 4, count 0 2006.259.07:47:33.38#ibcon#read 6, iclass 4, count 0 2006.259.07:47:33.38#ibcon#end of sib2, iclass 4, count 0 2006.259.07:47:33.38#ibcon#*mode == 0, iclass 4, count 0 2006.259.07:47:33.38#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.259.07:47:33.38#ibcon#[27=USB\r\n] 2006.259.07:47:33.38#ibcon#*before write, iclass 4, count 0 2006.259.07:47:33.38#ibcon#enter sib2, iclass 4, count 0 2006.259.07:47:33.38#ibcon#flushed, iclass 4, count 0 2006.259.07:47:33.38#ibcon#about to write, iclass 4, count 0 2006.259.07:47:33.38#ibcon#wrote, iclass 4, count 0 2006.259.07:47:33.38#ibcon#about to read 3, iclass 4, count 0 2006.259.07:47:33.41#ibcon#read 3, iclass 4, count 0 2006.259.07:47:33.41#ibcon#about to read 4, iclass 4, count 0 2006.259.07:47:33.41#ibcon#read 4, iclass 4, count 0 2006.259.07:47:33.41#ibcon#about to read 5, iclass 4, count 0 2006.259.07:47:33.41#ibcon#read 5, iclass 4, count 0 2006.259.07:47:33.41#ibcon#about to read 6, iclass 4, count 0 2006.259.07:47:33.41#ibcon#read 6, iclass 4, count 0 2006.259.07:47:33.41#ibcon#end of sib2, iclass 4, count 0 2006.259.07:47:33.41#ibcon#*after write, iclass 4, count 0 2006.259.07:47:33.41#ibcon#*before return 0, iclass 4, count 0 2006.259.07:47:33.41#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.259.07:47:33.41#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.259.07:47:33.41#ibcon#about to clear, iclass 4 cls_cnt 0 2006.259.07:47:33.41#ibcon#cleared, iclass 4 cls_cnt 0 2006.259.07:47:33.41$vc4f8/vblo=5,744.99 2006.259.07:47:33.41#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.259.07:47:33.41#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.259.07:47:33.41#ibcon#ireg 17 cls_cnt 0 2006.259.07:47:33.41#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.259.07:47:33.41#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.259.07:47:33.41#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.259.07:47:33.41#ibcon#enter wrdev, iclass 6, count 0 2006.259.07:47:33.41#ibcon#first serial, iclass 6, count 0 2006.259.07:47:33.41#ibcon#enter sib2, iclass 6, count 0 2006.259.07:47:33.41#ibcon#flushed, iclass 6, count 0 2006.259.07:47:33.41#ibcon#about to write, iclass 6, count 0 2006.259.07:47:33.41#ibcon#wrote, iclass 6, count 0 2006.259.07:47:33.41#ibcon#about to read 3, iclass 6, count 0 2006.259.07:47:33.43#ibcon#read 3, iclass 6, count 0 2006.259.07:47:33.43#ibcon#about to read 4, iclass 6, count 0 2006.259.07:47:33.43#ibcon#read 4, iclass 6, count 0 2006.259.07:47:33.43#ibcon#about to read 5, iclass 6, count 0 2006.259.07:47:33.43#ibcon#read 5, iclass 6, count 0 2006.259.07:47:33.43#ibcon#about to read 6, iclass 6, count 0 2006.259.07:47:33.43#ibcon#read 6, iclass 6, count 0 2006.259.07:47:33.43#ibcon#end of sib2, iclass 6, count 0 2006.259.07:47:33.43#ibcon#*mode == 0, iclass 6, count 0 2006.259.07:47:33.43#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.259.07:47:33.43#ibcon#[28=FRQ=05,744.99\r\n] 2006.259.07:47:33.43#ibcon#*before write, iclass 6, count 0 2006.259.07:47:33.43#ibcon#enter sib2, iclass 6, count 0 2006.259.07:47:33.43#ibcon#flushed, iclass 6, count 0 2006.259.07:47:33.43#ibcon#about to write, iclass 6, count 0 2006.259.07:47:33.43#ibcon#wrote, iclass 6, count 0 2006.259.07:47:33.43#ibcon#about to read 3, iclass 6, count 0 2006.259.07:47:33.48#ibcon#read 3, iclass 6, count 0 2006.259.07:47:33.48#ibcon#about to read 4, iclass 6, count 0 2006.259.07:47:33.48#ibcon#read 4, iclass 6, count 0 2006.259.07:47:33.48#ibcon#about to read 5, iclass 6, count 0 2006.259.07:47:33.48#ibcon#read 5, iclass 6, count 0 2006.259.07:47:33.48#ibcon#about to read 6, iclass 6, count 0 2006.259.07:47:33.48#ibcon#read 6, iclass 6, count 0 2006.259.07:47:33.48#ibcon#end of sib2, iclass 6, count 0 2006.259.07:47:33.48#ibcon#*after write, iclass 6, count 0 2006.259.07:47:33.48#ibcon#*before return 0, iclass 6, count 0 2006.259.07:47:33.48#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.259.07:47:33.48#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.259.07:47:33.48#ibcon#about to clear, iclass 6 cls_cnt 0 2006.259.07:47:33.48#ibcon#cleared, iclass 6 cls_cnt 0 2006.259.07:47:33.48$vc4f8/vb=5,4 2006.259.07:47:33.48#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.259.07:47:33.48#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.259.07:47:33.48#ibcon#ireg 11 cls_cnt 2 2006.259.07:47:33.48#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.259.07:47:33.53#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.259.07:47:33.53#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.259.07:47:33.53#ibcon#enter wrdev, iclass 10, count 2 2006.259.07:47:33.53#ibcon#first serial, iclass 10, count 2 2006.259.07:47:33.53#ibcon#enter sib2, iclass 10, count 2 2006.259.07:47:33.53#ibcon#flushed, iclass 10, count 2 2006.259.07:47:33.53#ibcon#about to write, iclass 10, count 2 2006.259.07:47:33.53#ibcon#wrote, iclass 10, count 2 2006.259.07:47:33.53#ibcon#about to read 3, iclass 10, count 2 2006.259.07:47:33.55#ibcon#read 3, iclass 10, count 2 2006.259.07:47:33.55#ibcon#about to read 4, iclass 10, count 2 2006.259.07:47:33.55#ibcon#read 4, iclass 10, count 2 2006.259.07:47:33.55#ibcon#about to read 5, iclass 10, count 2 2006.259.07:47:33.55#ibcon#read 5, iclass 10, count 2 2006.259.07:47:33.55#ibcon#about to read 6, iclass 10, count 2 2006.259.07:47:33.55#ibcon#read 6, iclass 10, count 2 2006.259.07:47:33.55#ibcon#end of sib2, iclass 10, count 2 2006.259.07:47:33.55#ibcon#*mode == 0, iclass 10, count 2 2006.259.07:47:33.55#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.259.07:47:33.55#ibcon#[27=AT05-04\r\n] 2006.259.07:47:33.55#ibcon#*before write, iclass 10, count 2 2006.259.07:47:33.55#ibcon#enter sib2, iclass 10, count 2 2006.259.07:47:33.55#ibcon#flushed, iclass 10, count 2 2006.259.07:47:33.55#ibcon#about to write, iclass 10, count 2 2006.259.07:47:33.55#ibcon#wrote, iclass 10, count 2 2006.259.07:47:33.55#ibcon#about to read 3, iclass 10, count 2 2006.259.07:47:33.58#ibcon#read 3, iclass 10, count 2 2006.259.07:47:33.58#ibcon#about to read 4, iclass 10, count 2 2006.259.07:47:33.58#ibcon#read 4, iclass 10, count 2 2006.259.07:47:33.58#ibcon#about to read 5, iclass 10, count 2 2006.259.07:47:33.58#ibcon#read 5, iclass 10, count 2 2006.259.07:47:33.58#ibcon#about to read 6, iclass 10, count 2 2006.259.07:47:33.58#ibcon#read 6, iclass 10, count 2 2006.259.07:47:33.58#ibcon#end of sib2, iclass 10, count 2 2006.259.07:47:33.58#ibcon#*after write, iclass 10, count 2 2006.259.07:47:33.58#ibcon#*before return 0, iclass 10, count 2 2006.259.07:47:33.58#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.259.07:47:33.58#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.259.07:47:33.58#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.259.07:47:33.58#ibcon#ireg 7 cls_cnt 0 2006.259.07:47:33.58#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.259.07:47:33.70#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.259.07:47:33.70#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.259.07:47:33.70#ibcon#enter wrdev, iclass 10, count 0 2006.259.07:47:33.70#ibcon#first serial, iclass 10, count 0 2006.259.07:47:33.70#ibcon#enter sib2, iclass 10, count 0 2006.259.07:47:33.70#ibcon#flushed, iclass 10, count 0 2006.259.07:47:33.70#ibcon#about to write, iclass 10, count 0 2006.259.07:47:33.70#ibcon#wrote, iclass 10, count 0 2006.259.07:47:33.70#ibcon#about to read 3, iclass 10, count 0 2006.259.07:47:33.72#ibcon#read 3, iclass 10, count 0 2006.259.07:47:33.72#ibcon#about to read 4, iclass 10, count 0 2006.259.07:47:33.72#ibcon#read 4, iclass 10, count 0 2006.259.07:47:33.72#ibcon#about to read 5, iclass 10, count 0 2006.259.07:47:33.72#ibcon#read 5, iclass 10, count 0 2006.259.07:47:33.72#ibcon#about to read 6, iclass 10, count 0 2006.259.07:47:33.72#ibcon#read 6, iclass 10, count 0 2006.259.07:47:33.72#ibcon#end of sib2, iclass 10, count 0 2006.259.07:47:33.72#ibcon#*mode == 0, iclass 10, count 0 2006.259.07:47:33.72#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.259.07:47:33.72#ibcon#[27=USB\r\n] 2006.259.07:47:33.72#ibcon#*before write, iclass 10, count 0 2006.259.07:47:33.72#ibcon#enter sib2, iclass 10, count 0 2006.259.07:47:33.72#ibcon#flushed, iclass 10, count 0 2006.259.07:47:33.72#ibcon#about to write, iclass 10, count 0 2006.259.07:47:33.72#ibcon#wrote, iclass 10, count 0 2006.259.07:47:33.72#ibcon#about to read 3, iclass 10, count 0 2006.259.07:47:33.75#ibcon#read 3, iclass 10, count 0 2006.259.07:47:33.75#ibcon#about to read 4, iclass 10, count 0 2006.259.07:47:33.75#ibcon#read 4, iclass 10, count 0 2006.259.07:47:33.75#ibcon#about to read 5, iclass 10, count 0 2006.259.07:47:33.75#ibcon#read 5, iclass 10, count 0 2006.259.07:47:33.75#ibcon#about to read 6, iclass 10, count 0 2006.259.07:47:33.75#ibcon#read 6, iclass 10, count 0 2006.259.07:47:33.75#ibcon#end of sib2, iclass 10, count 0 2006.259.07:47:33.75#ibcon#*after write, iclass 10, count 0 2006.259.07:47:33.75#ibcon#*before return 0, iclass 10, count 0 2006.259.07:47:33.75#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.259.07:47:33.75#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.259.07:47:33.75#ibcon#about to clear, iclass 10 cls_cnt 0 2006.259.07:47:33.75#ibcon#cleared, iclass 10 cls_cnt 0 2006.259.07:47:33.75$vc4f8/vblo=6,752.99 2006.259.07:47:33.75#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.259.07:47:33.75#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.259.07:47:33.75#ibcon#ireg 17 cls_cnt 0 2006.259.07:47:33.75#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.259.07:47:33.75#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.259.07:47:33.75#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.259.07:47:33.75#ibcon#enter wrdev, iclass 12, count 0 2006.259.07:47:33.75#ibcon#first serial, iclass 12, count 0 2006.259.07:47:33.75#ibcon#enter sib2, iclass 12, count 0 2006.259.07:47:33.75#ibcon#flushed, iclass 12, count 0 2006.259.07:47:33.75#ibcon#about to write, iclass 12, count 0 2006.259.07:47:33.75#ibcon#wrote, iclass 12, count 0 2006.259.07:47:33.75#ibcon#about to read 3, iclass 12, count 0 2006.259.07:47:33.77#ibcon#read 3, iclass 12, count 0 2006.259.07:47:33.77#ibcon#about to read 4, iclass 12, count 0 2006.259.07:47:33.77#ibcon#read 4, iclass 12, count 0 2006.259.07:47:33.77#ibcon#about to read 5, iclass 12, count 0 2006.259.07:47:33.77#ibcon#read 5, iclass 12, count 0 2006.259.07:47:33.77#ibcon#about to read 6, iclass 12, count 0 2006.259.07:47:33.77#ibcon#read 6, iclass 12, count 0 2006.259.07:47:33.77#ibcon#end of sib2, iclass 12, count 0 2006.259.07:47:33.77#ibcon#*mode == 0, iclass 12, count 0 2006.259.07:47:33.77#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.259.07:47:33.77#ibcon#[28=FRQ=06,752.99\r\n] 2006.259.07:47:33.77#ibcon#*before write, iclass 12, count 0 2006.259.07:47:33.77#ibcon#enter sib2, iclass 12, count 0 2006.259.07:47:33.77#ibcon#flushed, iclass 12, count 0 2006.259.07:47:33.77#ibcon#about to write, iclass 12, count 0 2006.259.07:47:33.77#ibcon#wrote, iclass 12, count 0 2006.259.07:47:33.77#ibcon#about to read 3, iclass 12, count 0 2006.259.07:47:33.81#ibcon#read 3, iclass 12, count 0 2006.259.07:47:33.81#ibcon#about to read 4, iclass 12, count 0 2006.259.07:47:33.81#ibcon#read 4, iclass 12, count 0 2006.259.07:47:33.81#ibcon#about to read 5, iclass 12, count 0 2006.259.07:47:33.81#ibcon#read 5, iclass 12, count 0 2006.259.07:47:33.81#ibcon#about to read 6, iclass 12, count 0 2006.259.07:47:33.81#ibcon#read 6, iclass 12, count 0 2006.259.07:47:33.81#ibcon#end of sib2, iclass 12, count 0 2006.259.07:47:33.81#ibcon#*after write, iclass 12, count 0 2006.259.07:47:33.81#ibcon#*before return 0, iclass 12, count 0 2006.259.07:47:33.81#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.259.07:47:33.81#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.259.07:47:33.81#ibcon#about to clear, iclass 12 cls_cnt 0 2006.259.07:47:33.81#ibcon#cleared, iclass 12 cls_cnt 0 2006.259.07:47:33.81$vc4f8/vb=6,4 2006.259.07:47:33.81#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.259.07:47:33.81#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.259.07:47:33.81#ibcon#ireg 11 cls_cnt 2 2006.259.07:47:33.81#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.259.07:47:33.87#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.259.07:47:33.87#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.259.07:47:33.87#ibcon#enter wrdev, iclass 14, count 2 2006.259.07:47:33.87#ibcon#first serial, iclass 14, count 2 2006.259.07:47:33.87#ibcon#enter sib2, iclass 14, count 2 2006.259.07:47:33.87#ibcon#flushed, iclass 14, count 2 2006.259.07:47:33.87#ibcon#about to write, iclass 14, count 2 2006.259.07:47:33.87#ibcon#wrote, iclass 14, count 2 2006.259.07:47:33.87#ibcon#about to read 3, iclass 14, count 2 2006.259.07:47:33.89#ibcon#read 3, iclass 14, count 2 2006.259.07:47:33.89#ibcon#about to read 4, iclass 14, count 2 2006.259.07:47:33.89#ibcon#read 4, iclass 14, count 2 2006.259.07:47:33.89#ibcon#about to read 5, iclass 14, count 2 2006.259.07:47:33.89#ibcon#read 5, iclass 14, count 2 2006.259.07:47:33.89#ibcon#about to read 6, iclass 14, count 2 2006.259.07:47:33.89#ibcon#read 6, iclass 14, count 2 2006.259.07:47:33.89#ibcon#end of sib2, iclass 14, count 2 2006.259.07:47:33.89#ibcon#*mode == 0, iclass 14, count 2 2006.259.07:47:33.89#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.259.07:47:33.89#ibcon#[27=AT06-04\r\n] 2006.259.07:47:33.89#ibcon#*before write, iclass 14, count 2 2006.259.07:47:33.89#ibcon#enter sib2, iclass 14, count 2 2006.259.07:47:33.89#ibcon#flushed, iclass 14, count 2 2006.259.07:47:33.89#ibcon#about to write, iclass 14, count 2 2006.259.07:47:33.89#ibcon#wrote, iclass 14, count 2 2006.259.07:47:33.89#ibcon#about to read 3, iclass 14, count 2 2006.259.07:47:33.92#ibcon#read 3, iclass 14, count 2 2006.259.07:47:33.92#ibcon#about to read 4, iclass 14, count 2 2006.259.07:47:33.92#ibcon#read 4, iclass 14, count 2 2006.259.07:47:33.92#ibcon#about to read 5, iclass 14, count 2 2006.259.07:47:33.92#ibcon#read 5, iclass 14, count 2 2006.259.07:47:33.92#ibcon#about to read 6, iclass 14, count 2 2006.259.07:47:33.92#ibcon#read 6, iclass 14, count 2 2006.259.07:47:33.92#ibcon#end of sib2, iclass 14, count 2 2006.259.07:47:33.92#ibcon#*after write, iclass 14, count 2 2006.259.07:47:33.92#ibcon#*before return 0, iclass 14, count 2 2006.259.07:47:33.92#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.259.07:47:33.92#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.259.07:47:33.92#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.259.07:47:33.92#ibcon#ireg 7 cls_cnt 0 2006.259.07:47:33.92#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.259.07:47:34.04#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.259.07:47:34.04#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.259.07:47:34.04#ibcon#enter wrdev, iclass 14, count 0 2006.259.07:47:34.04#ibcon#first serial, iclass 14, count 0 2006.259.07:47:34.04#ibcon#enter sib2, iclass 14, count 0 2006.259.07:47:34.04#ibcon#flushed, iclass 14, count 0 2006.259.07:47:34.04#ibcon#about to write, iclass 14, count 0 2006.259.07:47:34.04#ibcon#wrote, iclass 14, count 0 2006.259.07:47:34.04#ibcon#about to read 3, iclass 14, count 0 2006.259.07:47:34.06#ibcon#read 3, iclass 14, count 0 2006.259.07:47:34.06#ibcon#about to read 4, iclass 14, count 0 2006.259.07:47:34.06#ibcon#read 4, iclass 14, count 0 2006.259.07:47:34.06#ibcon#about to read 5, iclass 14, count 0 2006.259.07:47:34.06#ibcon#read 5, iclass 14, count 0 2006.259.07:47:34.06#ibcon#about to read 6, iclass 14, count 0 2006.259.07:47:34.06#ibcon#read 6, iclass 14, count 0 2006.259.07:47:34.06#ibcon#end of sib2, iclass 14, count 0 2006.259.07:47:34.06#ibcon#*mode == 0, iclass 14, count 0 2006.259.07:47:34.06#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.259.07:47:34.06#ibcon#[27=USB\r\n] 2006.259.07:47:34.06#ibcon#*before write, iclass 14, count 0 2006.259.07:47:34.06#ibcon#enter sib2, iclass 14, count 0 2006.259.07:47:34.06#ibcon#flushed, iclass 14, count 0 2006.259.07:47:34.06#ibcon#about to write, iclass 14, count 0 2006.259.07:47:34.06#ibcon#wrote, iclass 14, count 0 2006.259.07:47:34.06#ibcon#about to read 3, iclass 14, count 0 2006.259.07:47:34.09#ibcon#read 3, iclass 14, count 0 2006.259.07:47:34.09#ibcon#about to read 4, iclass 14, count 0 2006.259.07:47:34.09#ibcon#read 4, iclass 14, count 0 2006.259.07:47:34.09#ibcon#about to read 5, iclass 14, count 0 2006.259.07:47:34.09#ibcon#read 5, iclass 14, count 0 2006.259.07:47:34.09#ibcon#about to read 6, iclass 14, count 0 2006.259.07:47:34.09#ibcon#read 6, iclass 14, count 0 2006.259.07:47:34.09#ibcon#end of sib2, iclass 14, count 0 2006.259.07:47:34.09#ibcon#*after write, iclass 14, count 0 2006.259.07:47:34.09#ibcon#*before return 0, iclass 14, count 0 2006.259.07:47:34.09#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.259.07:47:34.09#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.259.07:47:34.09#ibcon#about to clear, iclass 14 cls_cnt 0 2006.259.07:47:34.09#ibcon#cleared, iclass 14 cls_cnt 0 2006.259.07:47:34.09$vc4f8/vabw=wide 2006.259.07:47:34.09#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.259.07:47:34.09#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.259.07:47:34.09#ibcon#ireg 8 cls_cnt 0 2006.259.07:47:34.09#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.259.07:47:34.09#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.259.07:47:34.09#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.259.07:47:34.09#ibcon#enter wrdev, iclass 16, count 0 2006.259.07:47:34.09#ibcon#first serial, iclass 16, count 0 2006.259.07:47:34.09#ibcon#enter sib2, iclass 16, count 0 2006.259.07:47:34.09#ibcon#flushed, iclass 16, count 0 2006.259.07:47:34.09#ibcon#about to write, iclass 16, count 0 2006.259.07:47:34.09#ibcon#wrote, iclass 16, count 0 2006.259.07:47:34.09#ibcon#about to read 3, iclass 16, count 0 2006.259.07:47:34.11#ibcon#read 3, iclass 16, count 0 2006.259.07:47:34.11#ibcon#about to read 4, iclass 16, count 0 2006.259.07:47:34.11#ibcon#read 4, iclass 16, count 0 2006.259.07:47:34.11#ibcon#about to read 5, iclass 16, count 0 2006.259.07:47:34.11#ibcon#read 5, iclass 16, count 0 2006.259.07:47:34.11#ibcon#about to read 6, iclass 16, count 0 2006.259.07:47:34.11#ibcon#read 6, iclass 16, count 0 2006.259.07:47:34.11#ibcon#end of sib2, iclass 16, count 0 2006.259.07:47:34.11#ibcon#*mode == 0, iclass 16, count 0 2006.259.07:47:34.11#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.259.07:47:34.11#ibcon#[25=BW32\r\n] 2006.259.07:47:34.11#ibcon#*before write, iclass 16, count 0 2006.259.07:47:34.11#ibcon#enter sib2, iclass 16, count 0 2006.259.07:47:34.11#ibcon#flushed, iclass 16, count 0 2006.259.07:47:34.11#ibcon#about to write, iclass 16, count 0 2006.259.07:47:34.11#ibcon#wrote, iclass 16, count 0 2006.259.07:47:34.11#ibcon#about to read 3, iclass 16, count 0 2006.259.07:47:34.14#ibcon#read 3, iclass 16, count 0 2006.259.07:47:34.14#ibcon#about to read 4, iclass 16, count 0 2006.259.07:47:34.14#ibcon#read 4, iclass 16, count 0 2006.259.07:47:34.14#ibcon#about to read 5, iclass 16, count 0 2006.259.07:47:34.14#ibcon#read 5, iclass 16, count 0 2006.259.07:47:34.14#ibcon#about to read 6, iclass 16, count 0 2006.259.07:47:34.14#ibcon#read 6, iclass 16, count 0 2006.259.07:47:34.14#ibcon#end of sib2, iclass 16, count 0 2006.259.07:47:34.14#ibcon#*after write, iclass 16, count 0 2006.259.07:47:34.14#ibcon#*before return 0, iclass 16, count 0 2006.259.07:47:34.14#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.259.07:47:34.14#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.259.07:47:34.14#ibcon#about to clear, iclass 16 cls_cnt 0 2006.259.07:47:34.14#ibcon#cleared, iclass 16 cls_cnt 0 2006.259.07:47:34.14$vc4f8/vbbw=wide 2006.259.07:47:34.14#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.259.07:47:34.14#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.259.07:47:34.14#ibcon#ireg 8 cls_cnt 0 2006.259.07:47:34.14#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.259.07:47:34.21#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.259.07:47:34.21#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.259.07:47:34.21#ibcon#enter wrdev, iclass 18, count 0 2006.259.07:47:34.21#ibcon#first serial, iclass 18, count 0 2006.259.07:47:34.21#ibcon#enter sib2, iclass 18, count 0 2006.259.07:47:34.21#ibcon#flushed, iclass 18, count 0 2006.259.07:47:34.21#ibcon#about to write, iclass 18, count 0 2006.259.07:47:34.21#ibcon#wrote, iclass 18, count 0 2006.259.07:47:34.21#ibcon#about to read 3, iclass 18, count 0 2006.259.07:47:34.23#ibcon#read 3, iclass 18, count 0 2006.259.07:47:34.23#ibcon#about to read 4, iclass 18, count 0 2006.259.07:47:34.23#ibcon#read 4, iclass 18, count 0 2006.259.07:47:34.23#ibcon#about to read 5, iclass 18, count 0 2006.259.07:47:34.23#ibcon#read 5, iclass 18, count 0 2006.259.07:47:34.23#ibcon#about to read 6, iclass 18, count 0 2006.259.07:47:34.23#ibcon#read 6, iclass 18, count 0 2006.259.07:47:34.23#ibcon#end of sib2, iclass 18, count 0 2006.259.07:47:34.23#ibcon#*mode == 0, iclass 18, count 0 2006.259.07:47:34.23#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.259.07:47:34.23#ibcon#[27=BW32\r\n] 2006.259.07:47:34.23#ibcon#*before write, iclass 18, count 0 2006.259.07:47:34.23#ibcon#enter sib2, iclass 18, count 0 2006.259.07:47:34.23#ibcon#flushed, iclass 18, count 0 2006.259.07:47:34.23#ibcon#about to write, iclass 18, count 0 2006.259.07:47:34.23#ibcon#wrote, iclass 18, count 0 2006.259.07:47:34.23#ibcon#about to read 3, iclass 18, count 0 2006.259.07:47:34.26#ibcon#read 3, iclass 18, count 0 2006.259.07:47:34.26#ibcon#about to read 4, iclass 18, count 0 2006.259.07:47:34.26#ibcon#read 4, iclass 18, count 0 2006.259.07:47:34.26#ibcon#about to read 5, iclass 18, count 0 2006.259.07:47:34.26#ibcon#read 5, iclass 18, count 0 2006.259.07:47:34.26#ibcon#about to read 6, iclass 18, count 0 2006.259.07:47:34.26#ibcon#read 6, iclass 18, count 0 2006.259.07:47:34.26#ibcon#end of sib2, iclass 18, count 0 2006.259.07:47:34.26#ibcon#*after write, iclass 18, count 0 2006.259.07:47:34.26#ibcon#*before return 0, iclass 18, count 0 2006.259.07:47:34.26#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.259.07:47:34.26#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.259.07:47:34.26#ibcon#about to clear, iclass 18 cls_cnt 0 2006.259.07:47:34.26#ibcon#cleared, iclass 18 cls_cnt 0 2006.259.07:47:34.26$4f8m12a/ifd4f 2006.259.07:47:34.26$ifd4f/lo= 2006.259.07:47:34.26$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.259.07:47:34.26$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.259.07:47:34.26$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.259.07:47:34.26$ifd4f/patch= 2006.259.07:47:34.26$ifd4f/patch=lo1,a1,a2,a3,a4 2006.259.07:47:34.26$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.259.07:47:34.26$ifd4f/patch=lo3,a5,a6,a7,a8 2006.259.07:47:34.26$4f8m12a/"form=m,16.000,1:2 2006.259.07:47:34.26$4f8m12a/"tpicd 2006.259.07:47:34.26$4f8m12a/echo=off 2006.259.07:47:34.26$4f8m12a/xlog=off 2006.259.07:47:34.26:!2006.259.07:48:00 2006.259.07:47:47.13#trakl#Source acquired 2006.259.07:47:48.13#flagr#flagr/antenna,acquired 2006.259.07:48:00.00:preob 2006.259.07:48:01.13/onsource/TRACKING 2006.259.07:48:01.13:!2006.259.07:48:10 2006.259.07:48:10.00:data_valid=on 2006.259.07:48:10.00:midob 2006.259.07:48:10.13/onsource/TRACKING 2006.259.07:48:10.13/wx/22.22,1013.0,86 2006.259.07:48:10.21/cable/+6.4577E-03 2006.259.07:48:11.30/va/01,08,usb,yes,46,49 2006.259.07:48:11.30/va/02,07,usb,yes,46,48 2006.259.07:48:11.30/va/03,08,usb,yes,36,36 2006.259.07:48:11.30/va/04,07,usb,yes,47,51 2006.259.07:48:11.30/va/05,07,usb,yes,53,56 2006.259.07:48:11.30/va/06,06,usb,yes,52,51 2006.259.07:48:11.30/va/07,06,usb,yes,53,52 2006.259.07:48:11.30/va/08,06,usb,yes,56,55 2006.259.07:48:11.53/valo/01,532.99,yes,locked 2006.259.07:48:11.53/valo/02,572.99,yes,locked 2006.259.07:48:11.53/valo/03,672.99,yes,locked 2006.259.07:48:11.53/valo/04,832.99,yes,locked 2006.259.07:48:11.53/valo/05,652.99,yes,locked 2006.259.07:48:11.53/valo/06,772.99,yes,locked 2006.259.07:48:11.53/valo/07,832.99,yes,locked 2006.259.07:48:11.53/valo/08,852.99,yes,locked 2006.259.07:48:12.62/vb/01,04,usb,yes,44,42 2006.259.07:48:12.62/vb/02,05,usb,yes,41,43 2006.259.07:48:12.62/vb/03,04,usb,yes,42,47 2006.259.07:48:12.62/vb/04,05,usb,yes,38,38 2006.259.07:48:12.62/vb/05,04,usb,yes,40,46 2006.259.07:48:12.62/vb/06,04,usb,yes,41,46 2006.259.07:48:12.62/vb/07,04,usb,yes,45,45 2006.259.07:48:12.62/vb/08,04,usb,yes,41,46 2006.259.07:48:12.86/vblo/01,632.99,yes,locked 2006.259.07:48:12.86/vblo/02,640.99,yes,locked 2006.259.07:48:12.86/vblo/03,656.99,yes,locked 2006.259.07:48:12.86/vblo/04,712.99,yes,locked 2006.259.07:48:12.86/vblo/05,744.99,yes,locked 2006.259.07:48:12.86/vblo/06,752.99,yes,locked 2006.259.07:48:12.86/vblo/07,734.99,yes,locked 2006.259.07:48:12.86/vblo/08,744.99,yes,locked 2006.259.07:48:13.01/vabw/8 2006.259.07:48:13.16/vbbw/8 2006.259.07:48:13.37/xfe/off,on,15.0 2006.259.07:48:13.75/ifatt/23,28,28,28 2006.259.07:48:14.08/fmout-gps/S +4.51E-07 2006.259.07:48:14.12:!2006.259.07:49:10 2006.259.07:49:10.00:data_valid=off 2006.259.07:49:10.00:postob 2006.259.07:49:10.13/cable/+6.4593E-03 2006.259.07:49:10.13/wx/22.22,1013.0,86 2006.259.07:49:11.08/fmout-gps/S +4.51E-07 2006.259.07:49:11.08:scan_name=259-0750,k06259,60 2006.259.07:49:11.08:source=1128+385,113053.28,381518.5,2000.0,ccw 2006.259.07:49:11.13#flagr#flagr/antenna,new-source 2006.259.07:49:12.13:checkk5 2006.259.07:49:12.57/chk_autoobs//k5ts1/ autoobs is running! 2006.259.07:49:13.05/chk_autoobs//k5ts2/ autoobs is running! 2006.259.07:49:13.68/chk_autoobs//k5ts3/ autoobs is running! 2006.259.07:49:14.06/chk_autoobs//k5ts4/ autoobs is running! 2006.259.07:49:14.45/chk_obsdata//k5ts1/T2590748??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.259.07:49:14.90/chk_obsdata//k5ts2/T2590748??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.259.07:49:15.33/chk_obsdata//k5ts3/T2590748??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.259.07:49:15.74/chk_obsdata//k5ts4/T2590748??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.259.07:49:16.55/k5log//k5ts1_log_newline 2006.259.07:49:17.33/k5log//k5ts2_log_newline 2006.259.07:49:18.16/k5log//k5ts3_log_newline 2006.259.07:49:18.94/k5log//k5ts4_log_newline 2006.259.07:49:18.97/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.259.07:49:18.97:4f8m12a=1 2006.259.07:49:18.97$4f8m12a/echo=on 2006.259.07:49:18.97$4f8m12a/pcalon 2006.259.07:49:18.97$pcalon/"no phase cal control is implemented here 2006.259.07:49:18.97$4f8m12a/"tpicd=stop 2006.259.07:49:18.97$4f8m12a/vc4f8 2006.259.07:49:18.97$vc4f8/valo=1,532.99 2006.259.07:49:18.97#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.259.07:49:18.97#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.259.07:49:18.97#ibcon#ireg 17 cls_cnt 0 2006.259.07:49:18.97#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.259.07:49:18.97#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.259.07:49:18.97#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.259.07:49:18.97#ibcon#enter wrdev, iclass 29, count 0 2006.259.07:49:18.97#ibcon#first serial, iclass 29, count 0 2006.259.07:49:18.97#ibcon#enter sib2, iclass 29, count 0 2006.259.07:49:18.97#ibcon#flushed, iclass 29, count 0 2006.259.07:49:18.97#ibcon#about to write, iclass 29, count 0 2006.259.07:49:18.97#ibcon#wrote, iclass 29, count 0 2006.259.07:49:18.97#ibcon#about to read 3, iclass 29, count 0 2006.259.07:49:19.02#ibcon#read 3, iclass 29, count 0 2006.259.07:49:19.02#ibcon#about to read 4, iclass 29, count 0 2006.259.07:49:19.02#ibcon#read 4, iclass 29, count 0 2006.259.07:49:19.02#ibcon#about to read 5, iclass 29, count 0 2006.259.07:49:19.02#ibcon#read 5, iclass 29, count 0 2006.259.07:49:19.02#ibcon#about to read 6, iclass 29, count 0 2006.259.07:49:19.02#ibcon#read 6, iclass 29, count 0 2006.259.07:49:19.02#ibcon#end of sib2, iclass 29, count 0 2006.259.07:49:19.02#ibcon#*mode == 0, iclass 29, count 0 2006.259.07:49:19.02#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.259.07:49:19.02#ibcon#[26=FRQ=01,532.99\r\n] 2006.259.07:49:19.02#ibcon#*before write, iclass 29, count 0 2006.259.07:49:19.02#ibcon#enter sib2, iclass 29, count 0 2006.259.07:49:19.02#ibcon#flushed, iclass 29, count 0 2006.259.07:49:19.02#ibcon#about to write, iclass 29, count 0 2006.259.07:49:19.02#ibcon#wrote, iclass 29, count 0 2006.259.07:49:19.02#ibcon#about to read 3, iclass 29, count 0 2006.259.07:49:19.07#ibcon#read 3, iclass 29, count 0 2006.259.07:49:19.07#ibcon#about to read 4, iclass 29, count 0 2006.259.07:49:19.07#ibcon#read 4, iclass 29, count 0 2006.259.07:49:19.07#ibcon#about to read 5, iclass 29, count 0 2006.259.07:49:19.07#ibcon#read 5, iclass 29, count 0 2006.259.07:49:19.07#ibcon#about to read 6, iclass 29, count 0 2006.259.07:49:19.07#ibcon#read 6, iclass 29, count 0 2006.259.07:49:19.07#ibcon#end of sib2, iclass 29, count 0 2006.259.07:49:19.07#ibcon#*after write, iclass 29, count 0 2006.259.07:49:19.07#ibcon#*before return 0, iclass 29, count 0 2006.259.07:49:19.07#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.259.07:49:19.07#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.259.07:49:19.07#ibcon#about to clear, iclass 29 cls_cnt 0 2006.259.07:49:19.07#ibcon#cleared, iclass 29 cls_cnt 0 2006.259.07:49:19.07$vc4f8/va=1,8 2006.259.07:49:19.07#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.259.07:49:19.07#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.259.07:49:19.07#ibcon#ireg 11 cls_cnt 2 2006.259.07:49:19.07#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.259.07:49:19.07#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.259.07:49:19.07#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.259.07:49:19.07#ibcon#enter wrdev, iclass 31, count 2 2006.259.07:49:19.07#ibcon#first serial, iclass 31, count 2 2006.259.07:49:19.07#ibcon#enter sib2, iclass 31, count 2 2006.259.07:49:19.07#ibcon#flushed, iclass 31, count 2 2006.259.07:49:19.07#ibcon#about to write, iclass 31, count 2 2006.259.07:49:19.07#ibcon#wrote, iclass 31, count 2 2006.259.07:49:19.07#ibcon#about to read 3, iclass 31, count 2 2006.259.07:49:19.09#ibcon#read 3, iclass 31, count 2 2006.259.07:49:19.09#ibcon#about to read 4, iclass 31, count 2 2006.259.07:49:19.09#ibcon#read 4, iclass 31, count 2 2006.259.07:49:19.09#ibcon#about to read 5, iclass 31, count 2 2006.259.07:49:19.09#ibcon#read 5, iclass 31, count 2 2006.259.07:49:19.09#ibcon#about to read 6, iclass 31, count 2 2006.259.07:49:19.09#ibcon#read 6, iclass 31, count 2 2006.259.07:49:19.09#ibcon#end of sib2, iclass 31, count 2 2006.259.07:49:19.09#ibcon#*mode == 0, iclass 31, count 2 2006.259.07:49:19.09#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.259.07:49:19.09#ibcon#[25=AT01-08\r\n] 2006.259.07:49:19.09#ibcon#*before write, iclass 31, count 2 2006.259.07:49:19.09#ibcon#enter sib2, iclass 31, count 2 2006.259.07:49:19.09#ibcon#flushed, iclass 31, count 2 2006.259.07:49:19.09#ibcon#about to write, iclass 31, count 2 2006.259.07:49:19.09#ibcon#wrote, iclass 31, count 2 2006.259.07:49:19.09#ibcon#about to read 3, iclass 31, count 2 2006.259.07:49:19.13#ibcon#read 3, iclass 31, count 2 2006.259.07:49:19.13#ibcon#about to read 4, iclass 31, count 2 2006.259.07:49:19.13#ibcon#read 4, iclass 31, count 2 2006.259.07:49:19.13#ibcon#about to read 5, iclass 31, count 2 2006.259.07:49:19.13#ibcon#read 5, iclass 31, count 2 2006.259.07:49:19.13#ibcon#about to read 6, iclass 31, count 2 2006.259.07:49:19.13#ibcon#read 6, iclass 31, count 2 2006.259.07:49:19.13#ibcon#end of sib2, iclass 31, count 2 2006.259.07:49:19.13#ibcon#*after write, iclass 31, count 2 2006.259.07:49:19.13#ibcon#*before return 0, iclass 31, count 2 2006.259.07:49:19.13#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.259.07:49:19.13#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.259.07:49:19.13#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.259.07:49:19.13#ibcon#ireg 7 cls_cnt 0 2006.259.07:49:19.13#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.259.07:49:19.25#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.259.07:49:19.25#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.259.07:49:19.25#ibcon#enter wrdev, iclass 31, count 0 2006.259.07:49:19.25#ibcon#first serial, iclass 31, count 0 2006.259.07:49:19.25#ibcon#enter sib2, iclass 31, count 0 2006.259.07:49:19.25#ibcon#flushed, iclass 31, count 0 2006.259.07:49:19.25#ibcon#about to write, iclass 31, count 0 2006.259.07:49:19.25#ibcon#wrote, iclass 31, count 0 2006.259.07:49:19.25#ibcon#about to read 3, iclass 31, count 0 2006.259.07:49:19.27#ibcon#read 3, iclass 31, count 0 2006.259.07:49:19.27#ibcon#about to read 4, iclass 31, count 0 2006.259.07:49:19.27#ibcon#read 4, iclass 31, count 0 2006.259.07:49:19.27#ibcon#about to read 5, iclass 31, count 0 2006.259.07:49:19.27#ibcon#read 5, iclass 31, count 0 2006.259.07:49:19.27#ibcon#about to read 6, iclass 31, count 0 2006.259.07:49:19.27#ibcon#read 6, iclass 31, count 0 2006.259.07:49:19.27#ibcon#end of sib2, iclass 31, count 0 2006.259.07:49:19.27#ibcon#*mode == 0, iclass 31, count 0 2006.259.07:49:19.27#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.259.07:49:19.27#ibcon#[25=USB\r\n] 2006.259.07:49:19.27#ibcon#*before write, iclass 31, count 0 2006.259.07:49:19.27#ibcon#enter sib2, iclass 31, count 0 2006.259.07:49:19.27#ibcon#flushed, iclass 31, count 0 2006.259.07:49:19.27#ibcon#about to write, iclass 31, count 0 2006.259.07:49:19.27#ibcon#wrote, iclass 31, count 0 2006.259.07:49:19.27#ibcon#about to read 3, iclass 31, count 0 2006.259.07:49:19.30#ibcon#read 3, iclass 31, count 0 2006.259.07:49:19.30#ibcon#about to read 4, iclass 31, count 0 2006.259.07:49:19.30#ibcon#read 4, iclass 31, count 0 2006.259.07:49:19.30#ibcon#about to read 5, iclass 31, count 0 2006.259.07:49:19.30#ibcon#read 5, iclass 31, count 0 2006.259.07:49:19.30#ibcon#about to read 6, iclass 31, count 0 2006.259.07:49:19.30#ibcon#read 6, iclass 31, count 0 2006.259.07:49:19.30#ibcon#end of sib2, iclass 31, count 0 2006.259.07:49:19.30#ibcon#*after write, iclass 31, count 0 2006.259.07:49:19.30#ibcon#*before return 0, iclass 31, count 0 2006.259.07:49:19.30#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.259.07:49:19.30#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.259.07:49:19.30#ibcon#about to clear, iclass 31 cls_cnt 0 2006.259.07:49:19.30#ibcon#cleared, iclass 31 cls_cnt 0 2006.259.07:49:19.30$vc4f8/valo=2,572.99 2006.259.07:49:19.30#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.259.07:49:19.30#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.259.07:49:19.30#ibcon#ireg 17 cls_cnt 0 2006.259.07:49:19.30#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.259.07:49:19.30#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.259.07:49:19.30#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.259.07:49:19.30#ibcon#enter wrdev, iclass 33, count 0 2006.259.07:49:19.30#ibcon#first serial, iclass 33, count 0 2006.259.07:49:19.30#ibcon#enter sib2, iclass 33, count 0 2006.259.07:49:19.30#ibcon#flushed, iclass 33, count 0 2006.259.07:49:19.30#ibcon#about to write, iclass 33, count 0 2006.259.07:49:19.30#ibcon#wrote, iclass 33, count 0 2006.259.07:49:19.30#ibcon#about to read 3, iclass 33, count 0 2006.259.07:49:19.32#ibcon#read 3, iclass 33, count 0 2006.259.07:49:19.32#ibcon#about to read 4, iclass 33, count 0 2006.259.07:49:19.32#ibcon#read 4, iclass 33, count 0 2006.259.07:49:19.32#ibcon#about to read 5, iclass 33, count 0 2006.259.07:49:19.32#ibcon#read 5, iclass 33, count 0 2006.259.07:49:19.32#ibcon#about to read 6, iclass 33, count 0 2006.259.07:49:19.32#ibcon#read 6, iclass 33, count 0 2006.259.07:49:19.32#ibcon#end of sib2, iclass 33, count 0 2006.259.07:49:19.32#ibcon#*mode == 0, iclass 33, count 0 2006.259.07:49:19.32#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.259.07:49:19.32#ibcon#[26=FRQ=02,572.99\r\n] 2006.259.07:49:19.32#ibcon#*before write, iclass 33, count 0 2006.259.07:49:19.32#ibcon#enter sib2, iclass 33, count 0 2006.259.07:49:19.32#ibcon#flushed, iclass 33, count 0 2006.259.07:49:19.32#ibcon#about to write, iclass 33, count 0 2006.259.07:49:19.32#ibcon#wrote, iclass 33, count 0 2006.259.07:49:19.32#ibcon#about to read 3, iclass 33, count 0 2006.259.07:49:19.36#ibcon#read 3, iclass 33, count 0 2006.259.07:49:19.36#ibcon#about to read 4, iclass 33, count 0 2006.259.07:49:19.36#ibcon#read 4, iclass 33, count 0 2006.259.07:49:19.36#ibcon#about to read 5, iclass 33, count 0 2006.259.07:49:19.36#ibcon#read 5, iclass 33, count 0 2006.259.07:49:19.36#ibcon#about to read 6, iclass 33, count 0 2006.259.07:49:19.36#ibcon#read 6, iclass 33, count 0 2006.259.07:49:19.36#ibcon#end of sib2, iclass 33, count 0 2006.259.07:49:19.36#ibcon#*after write, iclass 33, count 0 2006.259.07:49:19.36#ibcon#*before return 0, iclass 33, count 0 2006.259.07:49:19.36#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.259.07:49:19.36#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.259.07:49:19.36#ibcon#about to clear, iclass 33 cls_cnt 0 2006.259.07:49:19.36#ibcon#cleared, iclass 33 cls_cnt 0 2006.259.07:49:19.36$vc4f8/va=2,7 2006.259.07:49:19.36#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.259.07:49:19.36#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.259.07:49:19.36#ibcon#ireg 11 cls_cnt 2 2006.259.07:49:19.36#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.259.07:49:19.42#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.259.07:49:19.42#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.259.07:49:19.42#ibcon#enter wrdev, iclass 35, count 2 2006.259.07:49:19.42#ibcon#first serial, iclass 35, count 2 2006.259.07:49:19.42#ibcon#enter sib2, iclass 35, count 2 2006.259.07:49:19.42#ibcon#flushed, iclass 35, count 2 2006.259.07:49:19.42#ibcon#about to write, iclass 35, count 2 2006.259.07:49:19.42#ibcon#wrote, iclass 35, count 2 2006.259.07:49:19.42#ibcon#about to read 3, iclass 35, count 2 2006.259.07:49:19.44#ibcon#read 3, iclass 35, count 2 2006.259.07:49:19.44#ibcon#about to read 4, iclass 35, count 2 2006.259.07:49:19.44#ibcon#read 4, iclass 35, count 2 2006.259.07:49:19.44#ibcon#about to read 5, iclass 35, count 2 2006.259.07:49:19.44#ibcon#read 5, iclass 35, count 2 2006.259.07:49:19.44#ibcon#about to read 6, iclass 35, count 2 2006.259.07:49:19.44#ibcon#read 6, iclass 35, count 2 2006.259.07:49:19.44#ibcon#end of sib2, iclass 35, count 2 2006.259.07:49:19.44#ibcon#*mode == 0, iclass 35, count 2 2006.259.07:49:19.44#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.259.07:49:19.44#ibcon#[25=AT02-07\r\n] 2006.259.07:49:19.44#ibcon#*before write, iclass 35, count 2 2006.259.07:49:19.44#ibcon#enter sib2, iclass 35, count 2 2006.259.07:49:19.44#ibcon#flushed, iclass 35, count 2 2006.259.07:49:19.44#ibcon#about to write, iclass 35, count 2 2006.259.07:49:19.44#ibcon#wrote, iclass 35, count 2 2006.259.07:49:19.44#ibcon#about to read 3, iclass 35, count 2 2006.259.07:49:19.48#ibcon#read 3, iclass 35, count 2 2006.259.07:49:19.48#ibcon#about to read 4, iclass 35, count 2 2006.259.07:49:19.48#ibcon#read 4, iclass 35, count 2 2006.259.07:49:19.48#ibcon#about to read 5, iclass 35, count 2 2006.259.07:49:19.48#ibcon#read 5, iclass 35, count 2 2006.259.07:49:19.48#ibcon#about to read 6, iclass 35, count 2 2006.259.07:49:19.48#ibcon#read 6, iclass 35, count 2 2006.259.07:49:19.48#ibcon#end of sib2, iclass 35, count 2 2006.259.07:49:19.48#ibcon#*after write, iclass 35, count 2 2006.259.07:49:19.48#ibcon#*before return 0, iclass 35, count 2 2006.259.07:49:19.48#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.259.07:49:19.48#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.259.07:49:19.48#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.259.07:49:19.48#ibcon#ireg 7 cls_cnt 0 2006.259.07:49:19.48#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.259.07:49:19.60#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.259.07:49:19.60#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.259.07:49:19.60#ibcon#enter wrdev, iclass 35, count 0 2006.259.07:49:19.60#ibcon#first serial, iclass 35, count 0 2006.259.07:49:19.60#ibcon#enter sib2, iclass 35, count 0 2006.259.07:49:19.60#ibcon#flushed, iclass 35, count 0 2006.259.07:49:19.60#ibcon#about to write, iclass 35, count 0 2006.259.07:49:19.60#ibcon#wrote, iclass 35, count 0 2006.259.07:49:19.60#ibcon#about to read 3, iclass 35, count 0 2006.259.07:49:19.62#ibcon#read 3, iclass 35, count 0 2006.259.07:49:19.62#ibcon#about to read 4, iclass 35, count 0 2006.259.07:49:19.62#ibcon#read 4, iclass 35, count 0 2006.259.07:49:19.62#ibcon#about to read 5, iclass 35, count 0 2006.259.07:49:19.62#ibcon#read 5, iclass 35, count 0 2006.259.07:49:19.62#ibcon#about to read 6, iclass 35, count 0 2006.259.07:49:19.62#ibcon#read 6, iclass 35, count 0 2006.259.07:49:19.62#ibcon#end of sib2, iclass 35, count 0 2006.259.07:49:19.62#ibcon#*mode == 0, iclass 35, count 0 2006.259.07:49:19.62#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.259.07:49:19.62#ibcon#[25=USB\r\n] 2006.259.07:49:19.62#ibcon#*before write, iclass 35, count 0 2006.259.07:49:19.62#ibcon#enter sib2, iclass 35, count 0 2006.259.07:49:19.62#ibcon#flushed, iclass 35, count 0 2006.259.07:49:19.62#ibcon#about to write, iclass 35, count 0 2006.259.07:49:19.62#ibcon#wrote, iclass 35, count 0 2006.259.07:49:19.62#ibcon#about to read 3, iclass 35, count 0 2006.259.07:49:19.65#ibcon#read 3, iclass 35, count 0 2006.259.07:49:19.65#ibcon#about to read 4, iclass 35, count 0 2006.259.07:49:19.65#ibcon#read 4, iclass 35, count 0 2006.259.07:49:19.65#ibcon#about to read 5, iclass 35, count 0 2006.259.07:49:19.65#ibcon#read 5, iclass 35, count 0 2006.259.07:49:19.65#ibcon#about to read 6, iclass 35, count 0 2006.259.07:49:19.65#ibcon#read 6, iclass 35, count 0 2006.259.07:49:19.65#ibcon#end of sib2, iclass 35, count 0 2006.259.07:49:19.65#ibcon#*after write, iclass 35, count 0 2006.259.07:49:19.65#ibcon#*before return 0, iclass 35, count 0 2006.259.07:49:19.65#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.259.07:49:19.65#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.259.07:49:19.65#ibcon#about to clear, iclass 35 cls_cnt 0 2006.259.07:49:19.65#ibcon#cleared, iclass 35 cls_cnt 0 2006.259.07:49:19.65$vc4f8/valo=3,672.99 2006.259.07:49:19.65#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.259.07:49:19.65#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.259.07:49:19.65#ibcon#ireg 17 cls_cnt 0 2006.259.07:49:19.65#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.259.07:49:19.65#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.259.07:49:19.65#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.259.07:49:19.65#ibcon#enter wrdev, iclass 37, count 0 2006.259.07:49:19.65#ibcon#first serial, iclass 37, count 0 2006.259.07:49:19.65#ibcon#enter sib2, iclass 37, count 0 2006.259.07:49:19.65#ibcon#flushed, iclass 37, count 0 2006.259.07:49:19.65#ibcon#about to write, iclass 37, count 0 2006.259.07:49:19.65#ibcon#wrote, iclass 37, count 0 2006.259.07:49:19.65#ibcon#about to read 3, iclass 37, count 0 2006.259.07:49:19.67#ibcon#read 3, iclass 37, count 0 2006.259.07:49:19.67#ibcon#about to read 4, iclass 37, count 0 2006.259.07:49:19.67#ibcon#read 4, iclass 37, count 0 2006.259.07:49:19.67#ibcon#about to read 5, iclass 37, count 0 2006.259.07:49:19.67#ibcon#read 5, iclass 37, count 0 2006.259.07:49:19.67#ibcon#about to read 6, iclass 37, count 0 2006.259.07:49:19.67#ibcon#read 6, iclass 37, count 0 2006.259.07:49:19.67#ibcon#end of sib2, iclass 37, count 0 2006.259.07:49:19.67#ibcon#*mode == 0, iclass 37, count 0 2006.259.07:49:19.67#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.259.07:49:19.67#ibcon#[26=FRQ=03,672.99\r\n] 2006.259.07:49:19.67#ibcon#*before write, iclass 37, count 0 2006.259.07:49:19.67#ibcon#enter sib2, iclass 37, count 0 2006.259.07:49:19.67#ibcon#flushed, iclass 37, count 0 2006.259.07:49:19.67#ibcon#about to write, iclass 37, count 0 2006.259.07:49:19.67#ibcon#wrote, iclass 37, count 0 2006.259.07:49:19.67#ibcon#about to read 3, iclass 37, count 0 2006.259.07:49:19.71#ibcon#read 3, iclass 37, count 0 2006.259.07:49:19.71#ibcon#about to read 4, iclass 37, count 0 2006.259.07:49:19.71#ibcon#read 4, iclass 37, count 0 2006.259.07:49:19.71#ibcon#about to read 5, iclass 37, count 0 2006.259.07:49:19.71#ibcon#read 5, iclass 37, count 0 2006.259.07:49:19.71#ibcon#about to read 6, iclass 37, count 0 2006.259.07:49:19.71#ibcon#read 6, iclass 37, count 0 2006.259.07:49:19.71#ibcon#end of sib2, iclass 37, count 0 2006.259.07:49:19.71#ibcon#*after write, iclass 37, count 0 2006.259.07:49:19.71#ibcon#*before return 0, iclass 37, count 0 2006.259.07:49:19.71#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.259.07:49:19.71#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.259.07:49:19.71#ibcon#about to clear, iclass 37 cls_cnt 0 2006.259.07:49:19.71#ibcon#cleared, iclass 37 cls_cnt 0 2006.259.07:49:19.71$vc4f8/va=3,8 2006.259.07:49:19.71#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.259.07:49:19.71#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.259.07:49:19.71#ibcon#ireg 11 cls_cnt 2 2006.259.07:49:19.71#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.259.07:49:19.77#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.259.07:49:19.77#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.259.07:49:19.77#ibcon#enter wrdev, iclass 39, count 2 2006.259.07:49:19.77#ibcon#first serial, iclass 39, count 2 2006.259.07:49:19.77#ibcon#enter sib2, iclass 39, count 2 2006.259.07:49:19.77#ibcon#flushed, iclass 39, count 2 2006.259.07:49:19.77#ibcon#about to write, iclass 39, count 2 2006.259.07:49:19.77#ibcon#wrote, iclass 39, count 2 2006.259.07:49:19.77#ibcon#about to read 3, iclass 39, count 2 2006.259.07:49:19.79#ibcon#read 3, iclass 39, count 2 2006.259.07:49:19.79#ibcon#about to read 4, iclass 39, count 2 2006.259.07:49:19.79#ibcon#read 4, iclass 39, count 2 2006.259.07:49:19.79#ibcon#about to read 5, iclass 39, count 2 2006.259.07:49:19.79#ibcon#read 5, iclass 39, count 2 2006.259.07:49:19.79#ibcon#about to read 6, iclass 39, count 2 2006.259.07:49:19.79#ibcon#read 6, iclass 39, count 2 2006.259.07:49:19.79#ibcon#end of sib2, iclass 39, count 2 2006.259.07:49:19.79#ibcon#*mode == 0, iclass 39, count 2 2006.259.07:49:19.79#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.259.07:49:19.79#ibcon#[25=AT03-08\r\n] 2006.259.07:49:19.79#ibcon#*before write, iclass 39, count 2 2006.259.07:49:19.79#ibcon#enter sib2, iclass 39, count 2 2006.259.07:49:19.79#ibcon#flushed, iclass 39, count 2 2006.259.07:49:19.79#ibcon#about to write, iclass 39, count 2 2006.259.07:49:19.79#ibcon#wrote, iclass 39, count 2 2006.259.07:49:19.79#ibcon#about to read 3, iclass 39, count 2 2006.259.07:49:19.83#ibcon#read 3, iclass 39, count 2 2006.259.07:49:19.83#ibcon#about to read 4, iclass 39, count 2 2006.259.07:49:19.83#ibcon#read 4, iclass 39, count 2 2006.259.07:49:19.83#ibcon#about to read 5, iclass 39, count 2 2006.259.07:49:19.83#ibcon#read 5, iclass 39, count 2 2006.259.07:49:19.83#ibcon#about to read 6, iclass 39, count 2 2006.259.07:49:19.83#ibcon#read 6, iclass 39, count 2 2006.259.07:49:19.83#ibcon#end of sib2, iclass 39, count 2 2006.259.07:49:19.83#ibcon#*after write, iclass 39, count 2 2006.259.07:49:19.83#ibcon#*before return 0, iclass 39, count 2 2006.259.07:49:19.83#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.259.07:49:19.83#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.259.07:49:19.83#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.259.07:49:19.83#ibcon#ireg 7 cls_cnt 0 2006.259.07:49:19.83#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.259.07:49:19.95#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.259.07:49:19.95#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.259.07:49:19.95#ibcon#enter wrdev, iclass 39, count 0 2006.259.07:49:19.95#ibcon#first serial, iclass 39, count 0 2006.259.07:49:19.95#ibcon#enter sib2, iclass 39, count 0 2006.259.07:49:19.95#ibcon#flushed, iclass 39, count 0 2006.259.07:49:19.95#ibcon#about to write, iclass 39, count 0 2006.259.07:49:19.95#ibcon#wrote, iclass 39, count 0 2006.259.07:49:19.95#ibcon#about to read 3, iclass 39, count 0 2006.259.07:49:19.97#ibcon#read 3, iclass 39, count 0 2006.259.07:49:19.97#ibcon#about to read 4, iclass 39, count 0 2006.259.07:49:19.97#ibcon#read 4, iclass 39, count 0 2006.259.07:49:19.97#ibcon#about to read 5, iclass 39, count 0 2006.259.07:49:19.97#ibcon#read 5, iclass 39, count 0 2006.259.07:49:19.97#ibcon#about to read 6, iclass 39, count 0 2006.259.07:49:19.97#ibcon#read 6, iclass 39, count 0 2006.259.07:49:19.97#ibcon#end of sib2, iclass 39, count 0 2006.259.07:49:19.97#ibcon#*mode == 0, iclass 39, count 0 2006.259.07:49:19.97#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.259.07:49:19.97#ibcon#[25=USB\r\n] 2006.259.07:49:19.97#ibcon#*before write, iclass 39, count 0 2006.259.07:49:19.97#ibcon#enter sib2, iclass 39, count 0 2006.259.07:49:19.97#ibcon#flushed, iclass 39, count 0 2006.259.07:49:19.97#ibcon#about to write, iclass 39, count 0 2006.259.07:49:19.97#ibcon#wrote, iclass 39, count 0 2006.259.07:49:19.97#ibcon#about to read 3, iclass 39, count 0 2006.259.07:49:20.00#ibcon#read 3, iclass 39, count 0 2006.259.07:49:20.00#ibcon#about to read 4, iclass 39, count 0 2006.259.07:49:20.00#ibcon#read 4, iclass 39, count 0 2006.259.07:49:20.00#ibcon#about to read 5, iclass 39, count 0 2006.259.07:49:20.00#ibcon#read 5, iclass 39, count 0 2006.259.07:49:20.00#ibcon#about to read 6, iclass 39, count 0 2006.259.07:49:20.00#ibcon#read 6, iclass 39, count 0 2006.259.07:49:20.00#ibcon#end of sib2, iclass 39, count 0 2006.259.07:49:20.00#ibcon#*after write, iclass 39, count 0 2006.259.07:49:20.00#ibcon#*before return 0, iclass 39, count 0 2006.259.07:49:20.00#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.259.07:49:20.00#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.259.07:49:20.00#ibcon#about to clear, iclass 39 cls_cnt 0 2006.259.07:49:20.00#ibcon#cleared, iclass 39 cls_cnt 0 2006.259.07:49:20.00$vc4f8/valo=4,832.99 2006.259.07:49:20.00#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.259.07:49:20.00#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.259.07:49:20.00#ibcon#ireg 17 cls_cnt 0 2006.259.07:49:20.00#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.259.07:49:20.00#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.259.07:49:20.00#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.259.07:49:20.00#ibcon#enter wrdev, iclass 3, count 0 2006.259.07:49:20.00#ibcon#first serial, iclass 3, count 0 2006.259.07:49:20.00#ibcon#enter sib2, iclass 3, count 0 2006.259.07:49:20.00#ibcon#flushed, iclass 3, count 0 2006.259.07:49:20.00#ibcon#about to write, iclass 3, count 0 2006.259.07:49:20.00#ibcon#wrote, iclass 3, count 0 2006.259.07:49:20.00#ibcon#about to read 3, iclass 3, count 0 2006.259.07:49:20.02#ibcon#read 3, iclass 3, count 0 2006.259.07:49:20.02#ibcon#about to read 4, iclass 3, count 0 2006.259.07:49:20.02#ibcon#read 4, iclass 3, count 0 2006.259.07:49:20.02#ibcon#about to read 5, iclass 3, count 0 2006.259.07:49:20.02#ibcon#read 5, iclass 3, count 0 2006.259.07:49:20.02#ibcon#about to read 6, iclass 3, count 0 2006.259.07:49:20.02#ibcon#read 6, iclass 3, count 0 2006.259.07:49:20.02#ibcon#end of sib2, iclass 3, count 0 2006.259.07:49:20.02#ibcon#*mode == 0, iclass 3, count 0 2006.259.07:49:20.02#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.259.07:49:20.02#ibcon#[26=FRQ=04,832.99\r\n] 2006.259.07:49:20.02#ibcon#*before write, iclass 3, count 0 2006.259.07:49:20.02#ibcon#enter sib2, iclass 3, count 0 2006.259.07:49:20.02#ibcon#flushed, iclass 3, count 0 2006.259.07:49:20.02#ibcon#about to write, iclass 3, count 0 2006.259.07:49:20.02#ibcon#wrote, iclass 3, count 0 2006.259.07:49:20.02#ibcon#about to read 3, iclass 3, count 0 2006.259.07:49:20.06#ibcon#read 3, iclass 3, count 0 2006.259.07:49:20.06#ibcon#about to read 4, iclass 3, count 0 2006.259.07:49:20.06#ibcon#read 4, iclass 3, count 0 2006.259.07:49:20.06#ibcon#about to read 5, iclass 3, count 0 2006.259.07:49:20.06#ibcon#read 5, iclass 3, count 0 2006.259.07:49:20.06#ibcon#about to read 6, iclass 3, count 0 2006.259.07:49:20.06#ibcon#read 6, iclass 3, count 0 2006.259.07:49:20.06#ibcon#end of sib2, iclass 3, count 0 2006.259.07:49:20.06#ibcon#*after write, iclass 3, count 0 2006.259.07:49:20.06#ibcon#*before return 0, iclass 3, count 0 2006.259.07:49:20.06#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.259.07:49:20.06#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.259.07:49:20.06#ibcon#about to clear, iclass 3 cls_cnt 0 2006.259.07:49:20.06#ibcon#cleared, iclass 3 cls_cnt 0 2006.259.07:49:20.06$vc4f8/va=4,7 2006.259.07:49:20.06#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.259.07:49:20.06#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.259.07:49:20.06#ibcon#ireg 11 cls_cnt 2 2006.259.07:49:20.06#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.259.07:49:20.12#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.259.07:49:20.12#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.259.07:49:20.12#ibcon#enter wrdev, iclass 5, count 2 2006.259.07:49:20.12#ibcon#first serial, iclass 5, count 2 2006.259.07:49:20.12#ibcon#enter sib2, iclass 5, count 2 2006.259.07:49:20.12#ibcon#flushed, iclass 5, count 2 2006.259.07:49:20.12#ibcon#about to write, iclass 5, count 2 2006.259.07:49:20.12#ibcon#wrote, iclass 5, count 2 2006.259.07:49:20.12#ibcon#about to read 3, iclass 5, count 2 2006.259.07:49:20.14#ibcon#read 3, iclass 5, count 2 2006.259.07:49:20.14#ibcon#about to read 4, iclass 5, count 2 2006.259.07:49:20.14#ibcon#read 4, iclass 5, count 2 2006.259.07:49:20.14#ibcon#about to read 5, iclass 5, count 2 2006.259.07:49:20.14#ibcon#read 5, iclass 5, count 2 2006.259.07:49:20.14#ibcon#about to read 6, iclass 5, count 2 2006.259.07:49:20.14#ibcon#read 6, iclass 5, count 2 2006.259.07:49:20.14#ibcon#end of sib2, iclass 5, count 2 2006.259.07:49:20.14#ibcon#*mode == 0, iclass 5, count 2 2006.259.07:49:20.14#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.259.07:49:20.14#ibcon#[25=AT04-07\r\n] 2006.259.07:49:20.14#ibcon#*before write, iclass 5, count 2 2006.259.07:49:20.14#ibcon#enter sib2, iclass 5, count 2 2006.259.07:49:20.14#ibcon#flushed, iclass 5, count 2 2006.259.07:49:20.14#ibcon#about to write, iclass 5, count 2 2006.259.07:49:20.14#ibcon#wrote, iclass 5, count 2 2006.259.07:49:20.14#ibcon#about to read 3, iclass 5, count 2 2006.259.07:49:20.17#ibcon#read 3, iclass 5, count 2 2006.259.07:49:20.17#ibcon#about to read 4, iclass 5, count 2 2006.259.07:49:20.17#ibcon#read 4, iclass 5, count 2 2006.259.07:49:20.17#ibcon#about to read 5, iclass 5, count 2 2006.259.07:49:20.17#ibcon#read 5, iclass 5, count 2 2006.259.07:49:20.17#ibcon#about to read 6, iclass 5, count 2 2006.259.07:49:20.17#ibcon#read 6, iclass 5, count 2 2006.259.07:49:20.17#ibcon#end of sib2, iclass 5, count 2 2006.259.07:49:20.17#ibcon#*after write, iclass 5, count 2 2006.259.07:49:20.17#ibcon#*before return 0, iclass 5, count 2 2006.259.07:49:20.17#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.259.07:49:20.17#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.259.07:49:20.17#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.259.07:49:20.17#ibcon#ireg 7 cls_cnt 0 2006.259.07:49:20.17#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.259.07:49:20.29#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.259.07:49:20.29#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.259.07:49:20.29#ibcon#enter wrdev, iclass 5, count 0 2006.259.07:49:20.29#ibcon#first serial, iclass 5, count 0 2006.259.07:49:20.29#ibcon#enter sib2, iclass 5, count 0 2006.259.07:49:20.29#ibcon#flushed, iclass 5, count 0 2006.259.07:49:20.29#ibcon#about to write, iclass 5, count 0 2006.259.07:49:20.29#ibcon#wrote, iclass 5, count 0 2006.259.07:49:20.29#ibcon#about to read 3, iclass 5, count 0 2006.259.07:49:20.31#ibcon#read 3, iclass 5, count 0 2006.259.07:49:20.31#ibcon#about to read 4, iclass 5, count 0 2006.259.07:49:20.31#ibcon#read 4, iclass 5, count 0 2006.259.07:49:20.31#ibcon#about to read 5, iclass 5, count 0 2006.259.07:49:20.31#ibcon#read 5, iclass 5, count 0 2006.259.07:49:20.31#ibcon#about to read 6, iclass 5, count 0 2006.259.07:49:20.31#ibcon#read 6, iclass 5, count 0 2006.259.07:49:20.31#ibcon#end of sib2, iclass 5, count 0 2006.259.07:49:20.31#ibcon#*mode == 0, iclass 5, count 0 2006.259.07:49:20.31#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.259.07:49:20.31#ibcon#[25=USB\r\n] 2006.259.07:49:20.31#ibcon#*before write, iclass 5, count 0 2006.259.07:49:20.31#ibcon#enter sib2, iclass 5, count 0 2006.259.07:49:20.31#ibcon#flushed, iclass 5, count 0 2006.259.07:49:20.31#ibcon#about to write, iclass 5, count 0 2006.259.07:49:20.31#ibcon#wrote, iclass 5, count 0 2006.259.07:49:20.31#ibcon#about to read 3, iclass 5, count 0 2006.259.07:49:20.34#ibcon#read 3, iclass 5, count 0 2006.259.07:49:20.34#ibcon#about to read 4, iclass 5, count 0 2006.259.07:49:20.34#ibcon#read 4, iclass 5, count 0 2006.259.07:49:20.34#ibcon#about to read 5, iclass 5, count 0 2006.259.07:49:20.34#ibcon#read 5, iclass 5, count 0 2006.259.07:49:20.34#ibcon#about to read 6, iclass 5, count 0 2006.259.07:49:20.34#ibcon#read 6, iclass 5, count 0 2006.259.07:49:20.34#ibcon#end of sib2, iclass 5, count 0 2006.259.07:49:20.34#ibcon#*after write, iclass 5, count 0 2006.259.07:49:20.34#ibcon#*before return 0, iclass 5, count 0 2006.259.07:49:20.34#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.259.07:49:20.34#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.259.07:49:20.34#ibcon#about to clear, iclass 5 cls_cnt 0 2006.259.07:49:20.34#ibcon#cleared, iclass 5 cls_cnt 0 2006.259.07:49:20.34$vc4f8/valo=5,652.99 2006.259.07:49:20.34#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.259.07:49:20.34#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.259.07:49:20.34#ibcon#ireg 17 cls_cnt 0 2006.259.07:49:20.34#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.259.07:49:20.34#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.259.07:49:20.34#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.259.07:49:20.34#ibcon#enter wrdev, iclass 7, count 0 2006.259.07:49:20.34#ibcon#first serial, iclass 7, count 0 2006.259.07:49:20.34#ibcon#enter sib2, iclass 7, count 0 2006.259.07:49:20.34#ibcon#flushed, iclass 7, count 0 2006.259.07:49:20.34#ibcon#about to write, iclass 7, count 0 2006.259.07:49:20.34#ibcon#wrote, iclass 7, count 0 2006.259.07:49:20.34#ibcon#about to read 3, iclass 7, count 0 2006.259.07:49:20.36#ibcon#read 3, iclass 7, count 0 2006.259.07:49:20.36#ibcon#about to read 4, iclass 7, count 0 2006.259.07:49:20.36#ibcon#read 4, iclass 7, count 0 2006.259.07:49:20.36#ibcon#about to read 5, iclass 7, count 0 2006.259.07:49:20.36#ibcon#read 5, iclass 7, count 0 2006.259.07:49:20.36#ibcon#about to read 6, iclass 7, count 0 2006.259.07:49:20.36#ibcon#read 6, iclass 7, count 0 2006.259.07:49:20.36#ibcon#end of sib2, iclass 7, count 0 2006.259.07:49:20.36#ibcon#*mode == 0, iclass 7, count 0 2006.259.07:49:20.36#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.259.07:49:20.36#ibcon#[26=FRQ=05,652.99\r\n] 2006.259.07:49:20.36#ibcon#*before write, iclass 7, count 0 2006.259.07:49:20.36#ibcon#enter sib2, iclass 7, count 0 2006.259.07:49:20.36#ibcon#flushed, iclass 7, count 0 2006.259.07:49:20.36#ibcon#about to write, iclass 7, count 0 2006.259.07:49:20.36#ibcon#wrote, iclass 7, count 0 2006.259.07:49:20.36#ibcon#about to read 3, iclass 7, count 0 2006.259.07:49:20.40#ibcon#read 3, iclass 7, count 0 2006.259.07:49:20.40#ibcon#about to read 4, iclass 7, count 0 2006.259.07:49:20.40#ibcon#read 4, iclass 7, count 0 2006.259.07:49:20.40#ibcon#about to read 5, iclass 7, count 0 2006.259.07:49:20.40#ibcon#read 5, iclass 7, count 0 2006.259.07:49:20.40#ibcon#about to read 6, iclass 7, count 0 2006.259.07:49:20.40#ibcon#read 6, iclass 7, count 0 2006.259.07:49:20.40#ibcon#end of sib2, iclass 7, count 0 2006.259.07:49:20.40#ibcon#*after write, iclass 7, count 0 2006.259.07:49:20.40#ibcon#*before return 0, iclass 7, count 0 2006.259.07:49:20.40#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.259.07:49:20.40#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.259.07:49:20.40#ibcon#about to clear, iclass 7 cls_cnt 0 2006.259.07:49:20.40#ibcon#cleared, iclass 7 cls_cnt 0 2006.259.07:49:20.40$vc4f8/va=5,7 2006.259.07:49:20.40#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.259.07:49:20.40#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.259.07:49:20.40#ibcon#ireg 11 cls_cnt 2 2006.259.07:49:20.40#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.259.07:49:20.46#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.259.07:49:20.46#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.259.07:49:20.46#ibcon#enter wrdev, iclass 11, count 2 2006.259.07:49:20.46#ibcon#first serial, iclass 11, count 2 2006.259.07:49:20.46#ibcon#enter sib2, iclass 11, count 2 2006.259.07:49:20.46#ibcon#flushed, iclass 11, count 2 2006.259.07:49:20.46#ibcon#about to write, iclass 11, count 2 2006.259.07:49:20.46#ibcon#wrote, iclass 11, count 2 2006.259.07:49:20.46#ibcon#about to read 3, iclass 11, count 2 2006.259.07:49:20.48#ibcon#read 3, iclass 11, count 2 2006.259.07:49:20.48#ibcon#about to read 4, iclass 11, count 2 2006.259.07:49:20.48#ibcon#read 4, iclass 11, count 2 2006.259.07:49:20.48#ibcon#about to read 5, iclass 11, count 2 2006.259.07:49:20.48#ibcon#read 5, iclass 11, count 2 2006.259.07:49:20.48#ibcon#about to read 6, iclass 11, count 2 2006.259.07:49:20.48#ibcon#read 6, iclass 11, count 2 2006.259.07:49:20.48#ibcon#end of sib2, iclass 11, count 2 2006.259.07:49:20.48#ibcon#*mode == 0, iclass 11, count 2 2006.259.07:49:20.48#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.259.07:49:20.48#ibcon#[25=AT05-07\r\n] 2006.259.07:49:20.48#ibcon#*before write, iclass 11, count 2 2006.259.07:49:20.48#ibcon#enter sib2, iclass 11, count 2 2006.259.07:49:20.48#ibcon#flushed, iclass 11, count 2 2006.259.07:49:20.48#ibcon#about to write, iclass 11, count 2 2006.259.07:49:20.48#ibcon#wrote, iclass 11, count 2 2006.259.07:49:20.48#ibcon#about to read 3, iclass 11, count 2 2006.259.07:49:20.51#ibcon#read 3, iclass 11, count 2 2006.259.07:49:20.51#ibcon#about to read 4, iclass 11, count 2 2006.259.07:49:20.51#ibcon#read 4, iclass 11, count 2 2006.259.07:49:20.51#ibcon#about to read 5, iclass 11, count 2 2006.259.07:49:20.51#ibcon#read 5, iclass 11, count 2 2006.259.07:49:20.51#ibcon#about to read 6, iclass 11, count 2 2006.259.07:49:20.51#ibcon#read 6, iclass 11, count 2 2006.259.07:49:20.51#ibcon#end of sib2, iclass 11, count 2 2006.259.07:49:20.51#ibcon#*after write, iclass 11, count 2 2006.259.07:49:20.51#ibcon#*before return 0, iclass 11, count 2 2006.259.07:49:20.51#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.259.07:49:20.51#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.259.07:49:20.51#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.259.07:49:20.51#ibcon#ireg 7 cls_cnt 0 2006.259.07:49:20.51#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.259.07:49:20.63#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.259.07:49:20.63#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.259.07:49:20.63#ibcon#enter wrdev, iclass 11, count 0 2006.259.07:49:20.63#ibcon#first serial, iclass 11, count 0 2006.259.07:49:20.63#ibcon#enter sib2, iclass 11, count 0 2006.259.07:49:20.63#ibcon#flushed, iclass 11, count 0 2006.259.07:49:20.63#ibcon#about to write, iclass 11, count 0 2006.259.07:49:20.63#ibcon#wrote, iclass 11, count 0 2006.259.07:49:20.63#ibcon#about to read 3, iclass 11, count 0 2006.259.07:49:20.65#ibcon#read 3, iclass 11, count 0 2006.259.07:49:20.65#ibcon#about to read 4, iclass 11, count 0 2006.259.07:49:20.65#ibcon#read 4, iclass 11, count 0 2006.259.07:49:20.65#ibcon#about to read 5, iclass 11, count 0 2006.259.07:49:20.65#ibcon#read 5, iclass 11, count 0 2006.259.07:49:20.65#ibcon#about to read 6, iclass 11, count 0 2006.259.07:49:20.65#ibcon#read 6, iclass 11, count 0 2006.259.07:49:20.65#ibcon#end of sib2, iclass 11, count 0 2006.259.07:49:20.65#ibcon#*mode == 0, iclass 11, count 0 2006.259.07:49:20.65#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.259.07:49:20.65#ibcon#[25=USB\r\n] 2006.259.07:49:20.65#ibcon#*before write, iclass 11, count 0 2006.259.07:49:20.65#ibcon#enter sib2, iclass 11, count 0 2006.259.07:49:20.65#ibcon#flushed, iclass 11, count 0 2006.259.07:49:20.65#ibcon#about to write, iclass 11, count 0 2006.259.07:49:20.65#ibcon#wrote, iclass 11, count 0 2006.259.07:49:20.65#ibcon#about to read 3, iclass 11, count 0 2006.259.07:49:20.68#ibcon#read 3, iclass 11, count 0 2006.259.07:49:20.68#ibcon#about to read 4, iclass 11, count 0 2006.259.07:49:20.68#ibcon#read 4, iclass 11, count 0 2006.259.07:49:20.68#ibcon#about to read 5, iclass 11, count 0 2006.259.07:49:20.68#ibcon#read 5, iclass 11, count 0 2006.259.07:49:20.68#ibcon#about to read 6, iclass 11, count 0 2006.259.07:49:20.68#ibcon#read 6, iclass 11, count 0 2006.259.07:49:20.68#ibcon#end of sib2, iclass 11, count 0 2006.259.07:49:20.68#ibcon#*after write, iclass 11, count 0 2006.259.07:49:20.68#ibcon#*before return 0, iclass 11, count 0 2006.259.07:49:20.68#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.259.07:49:20.68#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.259.07:49:20.68#ibcon#about to clear, iclass 11 cls_cnt 0 2006.259.07:49:20.68#ibcon#cleared, iclass 11 cls_cnt 0 2006.259.07:49:20.68$vc4f8/valo=6,772.99 2006.259.07:49:20.68#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.259.07:49:20.68#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.259.07:49:20.68#ibcon#ireg 17 cls_cnt 0 2006.259.07:49:20.68#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.259.07:49:20.68#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.259.07:49:20.68#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.259.07:49:20.68#ibcon#enter wrdev, iclass 13, count 0 2006.259.07:49:20.68#ibcon#first serial, iclass 13, count 0 2006.259.07:49:20.68#ibcon#enter sib2, iclass 13, count 0 2006.259.07:49:20.68#ibcon#flushed, iclass 13, count 0 2006.259.07:49:20.68#ibcon#about to write, iclass 13, count 0 2006.259.07:49:20.68#ibcon#wrote, iclass 13, count 0 2006.259.07:49:20.68#ibcon#about to read 3, iclass 13, count 0 2006.259.07:49:20.70#ibcon#read 3, iclass 13, count 0 2006.259.07:49:20.70#ibcon#about to read 4, iclass 13, count 0 2006.259.07:49:20.70#ibcon#read 4, iclass 13, count 0 2006.259.07:49:20.70#ibcon#about to read 5, iclass 13, count 0 2006.259.07:49:20.70#ibcon#read 5, iclass 13, count 0 2006.259.07:49:20.70#ibcon#about to read 6, iclass 13, count 0 2006.259.07:49:20.70#ibcon#read 6, iclass 13, count 0 2006.259.07:49:20.70#ibcon#end of sib2, iclass 13, count 0 2006.259.07:49:20.70#ibcon#*mode == 0, iclass 13, count 0 2006.259.07:49:20.70#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.259.07:49:20.70#ibcon#[26=FRQ=06,772.99\r\n] 2006.259.07:49:20.70#ibcon#*before write, iclass 13, count 0 2006.259.07:49:20.70#ibcon#enter sib2, iclass 13, count 0 2006.259.07:49:20.70#ibcon#flushed, iclass 13, count 0 2006.259.07:49:20.70#ibcon#about to write, iclass 13, count 0 2006.259.07:49:20.70#ibcon#wrote, iclass 13, count 0 2006.259.07:49:20.70#ibcon#about to read 3, iclass 13, count 0 2006.259.07:49:20.74#ibcon#read 3, iclass 13, count 0 2006.259.07:49:20.74#ibcon#about to read 4, iclass 13, count 0 2006.259.07:49:20.74#ibcon#read 4, iclass 13, count 0 2006.259.07:49:20.74#ibcon#about to read 5, iclass 13, count 0 2006.259.07:49:20.74#ibcon#read 5, iclass 13, count 0 2006.259.07:49:20.74#ibcon#about to read 6, iclass 13, count 0 2006.259.07:49:20.74#ibcon#read 6, iclass 13, count 0 2006.259.07:49:20.74#ibcon#end of sib2, iclass 13, count 0 2006.259.07:49:20.74#ibcon#*after write, iclass 13, count 0 2006.259.07:49:20.74#ibcon#*before return 0, iclass 13, count 0 2006.259.07:49:20.74#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.259.07:49:20.74#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.259.07:49:20.74#ibcon#about to clear, iclass 13 cls_cnt 0 2006.259.07:49:20.74#ibcon#cleared, iclass 13 cls_cnt 0 2006.259.07:49:20.74$vc4f8/va=6,6 2006.259.07:49:20.74#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.259.07:49:20.74#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.259.07:49:20.74#ibcon#ireg 11 cls_cnt 2 2006.259.07:49:20.74#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.259.07:49:20.80#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.259.07:49:20.80#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.259.07:49:20.80#ibcon#enter wrdev, iclass 15, count 2 2006.259.07:49:20.80#ibcon#first serial, iclass 15, count 2 2006.259.07:49:20.80#ibcon#enter sib2, iclass 15, count 2 2006.259.07:49:20.80#ibcon#flushed, iclass 15, count 2 2006.259.07:49:20.80#ibcon#about to write, iclass 15, count 2 2006.259.07:49:20.80#ibcon#wrote, iclass 15, count 2 2006.259.07:49:20.80#ibcon#about to read 3, iclass 15, count 2 2006.259.07:49:20.82#ibcon#read 3, iclass 15, count 2 2006.259.07:49:20.82#ibcon#about to read 4, iclass 15, count 2 2006.259.07:49:20.82#ibcon#read 4, iclass 15, count 2 2006.259.07:49:20.82#ibcon#about to read 5, iclass 15, count 2 2006.259.07:49:20.82#ibcon#read 5, iclass 15, count 2 2006.259.07:49:20.82#ibcon#about to read 6, iclass 15, count 2 2006.259.07:49:20.82#ibcon#read 6, iclass 15, count 2 2006.259.07:49:20.82#ibcon#end of sib2, iclass 15, count 2 2006.259.07:49:20.82#ibcon#*mode == 0, iclass 15, count 2 2006.259.07:49:20.82#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.259.07:49:20.82#ibcon#[25=AT06-06\r\n] 2006.259.07:49:20.82#ibcon#*before write, iclass 15, count 2 2006.259.07:49:20.82#ibcon#enter sib2, iclass 15, count 2 2006.259.07:49:20.82#ibcon#flushed, iclass 15, count 2 2006.259.07:49:20.82#ibcon#about to write, iclass 15, count 2 2006.259.07:49:20.82#ibcon#wrote, iclass 15, count 2 2006.259.07:49:20.82#ibcon#about to read 3, iclass 15, count 2 2006.259.07:49:20.85#ibcon#read 3, iclass 15, count 2 2006.259.07:49:20.85#ibcon#about to read 4, iclass 15, count 2 2006.259.07:49:20.85#ibcon#read 4, iclass 15, count 2 2006.259.07:49:20.85#ibcon#about to read 5, iclass 15, count 2 2006.259.07:49:20.85#ibcon#read 5, iclass 15, count 2 2006.259.07:49:20.85#ibcon#about to read 6, iclass 15, count 2 2006.259.07:49:20.85#ibcon#read 6, iclass 15, count 2 2006.259.07:49:20.85#ibcon#end of sib2, iclass 15, count 2 2006.259.07:49:20.85#ibcon#*after write, iclass 15, count 2 2006.259.07:49:20.85#ibcon#*before return 0, iclass 15, count 2 2006.259.07:49:20.85#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.259.07:49:20.85#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.259.07:49:20.85#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.259.07:49:20.85#ibcon#ireg 7 cls_cnt 0 2006.259.07:49:20.85#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.259.07:49:20.97#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.259.07:49:20.97#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.259.07:49:20.97#ibcon#enter wrdev, iclass 15, count 0 2006.259.07:49:20.97#ibcon#first serial, iclass 15, count 0 2006.259.07:49:20.97#ibcon#enter sib2, iclass 15, count 0 2006.259.07:49:20.97#ibcon#flushed, iclass 15, count 0 2006.259.07:49:20.97#ibcon#about to write, iclass 15, count 0 2006.259.07:49:20.97#ibcon#wrote, iclass 15, count 0 2006.259.07:49:20.97#ibcon#about to read 3, iclass 15, count 0 2006.259.07:49:20.99#ibcon#read 3, iclass 15, count 0 2006.259.07:49:20.99#ibcon#about to read 4, iclass 15, count 0 2006.259.07:49:20.99#ibcon#read 4, iclass 15, count 0 2006.259.07:49:20.99#ibcon#about to read 5, iclass 15, count 0 2006.259.07:49:20.99#ibcon#read 5, iclass 15, count 0 2006.259.07:49:20.99#ibcon#about to read 6, iclass 15, count 0 2006.259.07:49:20.99#ibcon#read 6, iclass 15, count 0 2006.259.07:49:20.99#ibcon#end of sib2, iclass 15, count 0 2006.259.07:49:20.99#ibcon#*mode == 0, iclass 15, count 0 2006.259.07:49:20.99#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.259.07:49:20.99#ibcon#[25=USB\r\n] 2006.259.07:49:20.99#ibcon#*before write, iclass 15, count 0 2006.259.07:49:20.99#ibcon#enter sib2, iclass 15, count 0 2006.259.07:49:20.99#ibcon#flushed, iclass 15, count 0 2006.259.07:49:20.99#ibcon#about to write, iclass 15, count 0 2006.259.07:49:20.99#ibcon#wrote, iclass 15, count 0 2006.259.07:49:20.99#ibcon#about to read 3, iclass 15, count 0 2006.259.07:49:21.02#ibcon#read 3, iclass 15, count 0 2006.259.07:49:21.02#ibcon#about to read 4, iclass 15, count 0 2006.259.07:49:21.02#ibcon#read 4, iclass 15, count 0 2006.259.07:49:21.02#ibcon#about to read 5, iclass 15, count 0 2006.259.07:49:21.02#ibcon#read 5, iclass 15, count 0 2006.259.07:49:21.02#ibcon#about to read 6, iclass 15, count 0 2006.259.07:49:21.02#ibcon#read 6, iclass 15, count 0 2006.259.07:49:21.02#ibcon#end of sib2, iclass 15, count 0 2006.259.07:49:21.02#ibcon#*after write, iclass 15, count 0 2006.259.07:49:21.02#ibcon#*before return 0, iclass 15, count 0 2006.259.07:49:21.02#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.259.07:49:21.02#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.259.07:49:21.02#ibcon#about to clear, iclass 15 cls_cnt 0 2006.259.07:49:21.02#ibcon#cleared, iclass 15 cls_cnt 0 2006.259.07:49:21.02$vc4f8/valo=7,832.99 2006.259.07:49:21.02#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.259.07:49:21.02#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.259.07:49:21.02#ibcon#ireg 17 cls_cnt 0 2006.259.07:49:21.02#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.259.07:49:21.02#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.259.07:49:21.02#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.259.07:49:21.02#ibcon#enter wrdev, iclass 17, count 0 2006.259.07:49:21.02#ibcon#first serial, iclass 17, count 0 2006.259.07:49:21.02#ibcon#enter sib2, iclass 17, count 0 2006.259.07:49:21.02#ibcon#flushed, iclass 17, count 0 2006.259.07:49:21.02#ibcon#about to write, iclass 17, count 0 2006.259.07:49:21.02#ibcon#wrote, iclass 17, count 0 2006.259.07:49:21.02#ibcon#about to read 3, iclass 17, count 0 2006.259.07:49:21.04#ibcon#read 3, iclass 17, count 0 2006.259.07:49:21.04#ibcon#about to read 4, iclass 17, count 0 2006.259.07:49:21.04#ibcon#read 4, iclass 17, count 0 2006.259.07:49:21.04#ibcon#about to read 5, iclass 17, count 0 2006.259.07:49:21.04#ibcon#read 5, iclass 17, count 0 2006.259.07:49:21.04#ibcon#about to read 6, iclass 17, count 0 2006.259.07:49:21.04#ibcon#read 6, iclass 17, count 0 2006.259.07:49:21.04#ibcon#end of sib2, iclass 17, count 0 2006.259.07:49:21.04#ibcon#*mode == 0, iclass 17, count 0 2006.259.07:49:21.04#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.259.07:49:21.04#ibcon#[26=FRQ=07,832.99\r\n] 2006.259.07:49:21.04#ibcon#*before write, iclass 17, count 0 2006.259.07:49:21.04#ibcon#enter sib2, iclass 17, count 0 2006.259.07:49:21.04#ibcon#flushed, iclass 17, count 0 2006.259.07:49:21.04#ibcon#about to write, iclass 17, count 0 2006.259.07:49:21.04#ibcon#wrote, iclass 17, count 0 2006.259.07:49:21.04#ibcon#about to read 3, iclass 17, count 0 2006.259.07:49:21.08#ibcon#read 3, iclass 17, count 0 2006.259.07:49:21.08#ibcon#about to read 4, iclass 17, count 0 2006.259.07:49:21.08#ibcon#read 4, iclass 17, count 0 2006.259.07:49:21.08#ibcon#about to read 5, iclass 17, count 0 2006.259.07:49:21.08#ibcon#read 5, iclass 17, count 0 2006.259.07:49:21.08#ibcon#about to read 6, iclass 17, count 0 2006.259.07:49:21.08#ibcon#read 6, iclass 17, count 0 2006.259.07:49:21.08#ibcon#end of sib2, iclass 17, count 0 2006.259.07:49:21.08#ibcon#*after write, iclass 17, count 0 2006.259.07:49:21.08#ibcon#*before return 0, iclass 17, count 0 2006.259.07:49:21.08#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.259.07:49:21.08#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.259.07:49:21.08#ibcon#about to clear, iclass 17 cls_cnt 0 2006.259.07:49:21.08#ibcon#cleared, iclass 17 cls_cnt 0 2006.259.07:49:21.08$vc4f8/va=7,6 2006.259.07:49:21.08#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.259.07:49:21.08#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.259.07:49:21.08#ibcon#ireg 11 cls_cnt 2 2006.259.07:49:21.08#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.259.07:49:21.14#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.259.07:49:21.14#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.259.07:49:21.14#ibcon#enter wrdev, iclass 19, count 2 2006.259.07:49:21.14#ibcon#first serial, iclass 19, count 2 2006.259.07:49:21.14#ibcon#enter sib2, iclass 19, count 2 2006.259.07:49:21.14#ibcon#flushed, iclass 19, count 2 2006.259.07:49:21.14#ibcon#about to write, iclass 19, count 2 2006.259.07:49:21.14#ibcon#wrote, iclass 19, count 2 2006.259.07:49:21.14#ibcon#about to read 3, iclass 19, count 2 2006.259.07:49:21.16#ibcon#read 3, iclass 19, count 2 2006.259.07:49:21.16#ibcon#about to read 4, iclass 19, count 2 2006.259.07:49:21.16#ibcon#read 4, iclass 19, count 2 2006.259.07:49:21.16#ibcon#about to read 5, iclass 19, count 2 2006.259.07:49:21.16#ibcon#read 5, iclass 19, count 2 2006.259.07:49:21.16#ibcon#about to read 6, iclass 19, count 2 2006.259.07:49:21.16#ibcon#read 6, iclass 19, count 2 2006.259.07:49:21.16#ibcon#end of sib2, iclass 19, count 2 2006.259.07:49:21.16#ibcon#*mode == 0, iclass 19, count 2 2006.259.07:49:21.16#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.259.07:49:21.16#ibcon#[25=AT07-06\r\n] 2006.259.07:49:21.16#ibcon#*before write, iclass 19, count 2 2006.259.07:49:21.16#ibcon#enter sib2, iclass 19, count 2 2006.259.07:49:21.16#ibcon#flushed, iclass 19, count 2 2006.259.07:49:21.16#ibcon#about to write, iclass 19, count 2 2006.259.07:49:21.16#ibcon#wrote, iclass 19, count 2 2006.259.07:49:21.16#ibcon#about to read 3, iclass 19, count 2 2006.259.07:49:21.19#ibcon#read 3, iclass 19, count 2 2006.259.07:49:21.19#ibcon#about to read 4, iclass 19, count 2 2006.259.07:49:21.19#ibcon#read 4, iclass 19, count 2 2006.259.07:49:21.19#ibcon#about to read 5, iclass 19, count 2 2006.259.07:49:21.19#ibcon#read 5, iclass 19, count 2 2006.259.07:49:21.19#ibcon#about to read 6, iclass 19, count 2 2006.259.07:49:21.19#ibcon#read 6, iclass 19, count 2 2006.259.07:49:21.19#ibcon#end of sib2, iclass 19, count 2 2006.259.07:49:21.19#ibcon#*after write, iclass 19, count 2 2006.259.07:49:21.19#ibcon#*before return 0, iclass 19, count 2 2006.259.07:49:21.19#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.259.07:49:21.19#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.259.07:49:21.19#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.259.07:49:21.19#ibcon#ireg 7 cls_cnt 0 2006.259.07:49:21.19#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.259.07:49:21.31#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.259.07:49:21.31#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.259.07:49:21.31#ibcon#enter wrdev, iclass 19, count 0 2006.259.07:49:21.31#ibcon#first serial, iclass 19, count 0 2006.259.07:49:21.31#ibcon#enter sib2, iclass 19, count 0 2006.259.07:49:21.31#ibcon#flushed, iclass 19, count 0 2006.259.07:49:21.31#ibcon#about to write, iclass 19, count 0 2006.259.07:49:21.31#ibcon#wrote, iclass 19, count 0 2006.259.07:49:21.31#ibcon#about to read 3, iclass 19, count 0 2006.259.07:49:21.33#ibcon#read 3, iclass 19, count 0 2006.259.07:49:21.33#ibcon#about to read 4, iclass 19, count 0 2006.259.07:49:21.33#ibcon#read 4, iclass 19, count 0 2006.259.07:49:21.33#ibcon#about to read 5, iclass 19, count 0 2006.259.07:49:21.33#ibcon#read 5, iclass 19, count 0 2006.259.07:49:21.33#ibcon#about to read 6, iclass 19, count 0 2006.259.07:49:21.33#ibcon#read 6, iclass 19, count 0 2006.259.07:49:21.33#ibcon#end of sib2, iclass 19, count 0 2006.259.07:49:21.33#ibcon#*mode == 0, iclass 19, count 0 2006.259.07:49:21.33#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.259.07:49:21.33#ibcon#[25=USB\r\n] 2006.259.07:49:21.33#ibcon#*before write, iclass 19, count 0 2006.259.07:49:21.33#ibcon#enter sib2, iclass 19, count 0 2006.259.07:49:21.33#ibcon#flushed, iclass 19, count 0 2006.259.07:49:21.33#ibcon#about to write, iclass 19, count 0 2006.259.07:49:21.33#ibcon#wrote, iclass 19, count 0 2006.259.07:49:21.33#ibcon#about to read 3, iclass 19, count 0 2006.259.07:49:21.36#ibcon#read 3, iclass 19, count 0 2006.259.07:49:21.36#ibcon#about to read 4, iclass 19, count 0 2006.259.07:49:21.36#ibcon#read 4, iclass 19, count 0 2006.259.07:49:21.36#ibcon#about to read 5, iclass 19, count 0 2006.259.07:49:21.36#ibcon#read 5, iclass 19, count 0 2006.259.07:49:21.36#ibcon#about to read 6, iclass 19, count 0 2006.259.07:49:21.36#ibcon#read 6, iclass 19, count 0 2006.259.07:49:21.36#ibcon#end of sib2, iclass 19, count 0 2006.259.07:49:21.36#ibcon#*after write, iclass 19, count 0 2006.259.07:49:21.36#ibcon#*before return 0, iclass 19, count 0 2006.259.07:49:21.36#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.259.07:49:21.36#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.259.07:49:21.36#ibcon#about to clear, iclass 19 cls_cnt 0 2006.259.07:49:21.36#ibcon#cleared, iclass 19 cls_cnt 0 2006.259.07:49:21.36$vc4f8/valo=8,852.99 2006.259.07:49:21.36#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.259.07:49:21.36#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.259.07:49:21.36#ibcon#ireg 17 cls_cnt 0 2006.259.07:49:21.36#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.259.07:49:21.36#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.259.07:49:21.36#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.259.07:49:21.36#ibcon#enter wrdev, iclass 21, count 0 2006.259.07:49:21.36#ibcon#first serial, iclass 21, count 0 2006.259.07:49:21.36#ibcon#enter sib2, iclass 21, count 0 2006.259.07:49:21.36#ibcon#flushed, iclass 21, count 0 2006.259.07:49:21.36#ibcon#about to write, iclass 21, count 0 2006.259.07:49:21.36#ibcon#wrote, iclass 21, count 0 2006.259.07:49:21.36#ibcon#about to read 3, iclass 21, count 0 2006.259.07:49:21.38#ibcon#read 3, iclass 21, count 0 2006.259.07:49:21.38#ibcon#about to read 4, iclass 21, count 0 2006.259.07:49:21.38#ibcon#read 4, iclass 21, count 0 2006.259.07:49:21.38#ibcon#about to read 5, iclass 21, count 0 2006.259.07:49:21.38#ibcon#read 5, iclass 21, count 0 2006.259.07:49:21.38#ibcon#about to read 6, iclass 21, count 0 2006.259.07:49:21.38#ibcon#read 6, iclass 21, count 0 2006.259.07:49:21.38#ibcon#end of sib2, iclass 21, count 0 2006.259.07:49:21.38#ibcon#*mode == 0, iclass 21, count 0 2006.259.07:49:21.38#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.259.07:49:21.38#ibcon#[26=FRQ=08,852.99\r\n] 2006.259.07:49:21.38#ibcon#*before write, iclass 21, count 0 2006.259.07:49:21.38#ibcon#enter sib2, iclass 21, count 0 2006.259.07:49:21.38#ibcon#flushed, iclass 21, count 0 2006.259.07:49:21.38#ibcon#about to write, iclass 21, count 0 2006.259.07:49:21.38#ibcon#wrote, iclass 21, count 0 2006.259.07:49:21.38#ibcon#about to read 3, iclass 21, count 0 2006.259.07:49:21.42#ibcon#read 3, iclass 21, count 0 2006.259.07:49:21.42#ibcon#about to read 4, iclass 21, count 0 2006.259.07:49:21.42#ibcon#read 4, iclass 21, count 0 2006.259.07:49:21.42#ibcon#about to read 5, iclass 21, count 0 2006.259.07:49:21.42#ibcon#read 5, iclass 21, count 0 2006.259.07:49:21.42#ibcon#about to read 6, iclass 21, count 0 2006.259.07:49:21.42#ibcon#read 6, iclass 21, count 0 2006.259.07:49:21.42#ibcon#end of sib2, iclass 21, count 0 2006.259.07:49:21.42#ibcon#*after write, iclass 21, count 0 2006.259.07:49:21.42#ibcon#*before return 0, iclass 21, count 0 2006.259.07:49:21.42#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.259.07:49:21.42#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.259.07:49:21.42#ibcon#about to clear, iclass 21 cls_cnt 0 2006.259.07:49:21.42#ibcon#cleared, iclass 21 cls_cnt 0 2006.259.07:49:21.42$vc4f8/va=8,6 2006.259.07:49:21.42#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.259.07:49:21.42#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.259.07:49:21.42#ibcon#ireg 11 cls_cnt 2 2006.259.07:49:21.42#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.259.07:49:21.48#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.259.07:49:21.48#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.259.07:49:21.48#ibcon#enter wrdev, iclass 23, count 2 2006.259.07:49:21.48#ibcon#first serial, iclass 23, count 2 2006.259.07:49:21.48#ibcon#enter sib2, iclass 23, count 2 2006.259.07:49:21.48#ibcon#flushed, iclass 23, count 2 2006.259.07:49:21.48#ibcon#about to write, iclass 23, count 2 2006.259.07:49:21.48#ibcon#wrote, iclass 23, count 2 2006.259.07:49:21.48#ibcon#about to read 3, iclass 23, count 2 2006.259.07:49:21.50#ibcon#read 3, iclass 23, count 2 2006.259.07:49:21.50#ibcon#about to read 4, iclass 23, count 2 2006.259.07:49:21.50#ibcon#read 4, iclass 23, count 2 2006.259.07:49:21.50#ibcon#about to read 5, iclass 23, count 2 2006.259.07:49:21.50#ibcon#read 5, iclass 23, count 2 2006.259.07:49:21.50#ibcon#about to read 6, iclass 23, count 2 2006.259.07:49:21.50#ibcon#read 6, iclass 23, count 2 2006.259.07:49:21.50#ibcon#end of sib2, iclass 23, count 2 2006.259.07:49:21.50#ibcon#*mode == 0, iclass 23, count 2 2006.259.07:49:21.50#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.259.07:49:21.50#ibcon#[25=AT08-06\r\n] 2006.259.07:49:21.50#ibcon#*before write, iclass 23, count 2 2006.259.07:49:21.50#ibcon#enter sib2, iclass 23, count 2 2006.259.07:49:21.50#ibcon#flushed, iclass 23, count 2 2006.259.07:49:21.50#ibcon#about to write, iclass 23, count 2 2006.259.07:49:21.50#ibcon#wrote, iclass 23, count 2 2006.259.07:49:21.50#ibcon#about to read 3, iclass 23, count 2 2006.259.07:49:21.53#ibcon#read 3, iclass 23, count 2 2006.259.07:49:21.53#ibcon#about to read 4, iclass 23, count 2 2006.259.07:49:21.53#ibcon#read 4, iclass 23, count 2 2006.259.07:49:21.53#ibcon#about to read 5, iclass 23, count 2 2006.259.07:49:21.53#ibcon#read 5, iclass 23, count 2 2006.259.07:49:21.53#ibcon#about to read 6, iclass 23, count 2 2006.259.07:49:21.53#ibcon#read 6, iclass 23, count 2 2006.259.07:49:21.53#ibcon#end of sib2, iclass 23, count 2 2006.259.07:49:21.53#ibcon#*after write, iclass 23, count 2 2006.259.07:49:21.53#ibcon#*before return 0, iclass 23, count 2 2006.259.07:49:21.53#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.259.07:49:21.53#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.259.07:49:21.53#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.259.07:49:21.53#ibcon#ireg 7 cls_cnt 0 2006.259.07:49:21.53#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.259.07:49:21.65#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.259.07:49:21.65#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.259.07:49:21.65#ibcon#enter wrdev, iclass 23, count 0 2006.259.07:49:21.65#ibcon#first serial, iclass 23, count 0 2006.259.07:49:21.65#ibcon#enter sib2, iclass 23, count 0 2006.259.07:49:21.65#ibcon#flushed, iclass 23, count 0 2006.259.07:49:21.65#ibcon#about to write, iclass 23, count 0 2006.259.07:49:21.65#ibcon#wrote, iclass 23, count 0 2006.259.07:49:21.65#ibcon#about to read 3, iclass 23, count 0 2006.259.07:49:21.67#ibcon#read 3, iclass 23, count 0 2006.259.07:49:21.67#ibcon#about to read 4, iclass 23, count 0 2006.259.07:49:21.67#ibcon#read 4, iclass 23, count 0 2006.259.07:49:21.67#ibcon#about to read 5, iclass 23, count 0 2006.259.07:49:21.67#ibcon#read 5, iclass 23, count 0 2006.259.07:49:21.67#ibcon#about to read 6, iclass 23, count 0 2006.259.07:49:21.67#ibcon#read 6, iclass 23, count 0 2006.259.07:49:21.67#ibcon#end of sib2, iclass 23, count 0 2006.259.07:49:21.67#ibcon#*mode == 0, iclass 23, count 0 2006.259.07:49:21.67#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.259.07:49:21.67#ibcon#[25=USB\r\n] 2006.259.07:49:21.67#ibcon#*before write, iclass 23, count 0 2006.259.07:49:21.67#ibcon#enter sib2, iclass 23, count 0 2006.259.07:49:21.67#ibcon#flushed, iclass 23, count 0 2006.259.07:49:21.67#ibcon#about to write, iclass 23, count 0 2006.259.07:49:21.67#ibcon#wrote, iclass 23, count 0 2006.259.07:49:21.67#ibcon#about to read 3, iclass 23, count 0 2006.259.07:49:21.70#ibcon#read 3, iclass 23, count 0 2006.259.07:49:21.70#ibcon#about to read 4, iclass 23, count 0 2006.259.07:49:21.70#ibcon#read 4, iclass 23, count 0 2006.259.07:49:21.70#ibcon#about to read 5, iclass 23, count 0 2006.259.07:49:21.70#ibcon#read 5, iclass 23, count 0 2006.259.07:49:21.70#ibcon#about to read 6, iclass 23, count 0 2006.259.07:49:21.70#ibcon#read 6, iclass 23, count 0 2006.259.07:49:21.70#ibcon#end of sib2, iclass 23, count 0 2006.259.07:49:21.70#ibcon#*after write, iclass 23, count 0 2006.259.07:49:21.70#ibcon#*before return 0, iclass 23, count 0 2006.259.07:49:21.70#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.259.07:49:21.70#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.259.07:49:21.70#ibcon#about to clear, iclass 23 cls_cnt 0 2006.259.07:49:21.70#ibcon#cleared, iclass 23 cls_cnt 0 2006.259.07:49:21.70$vc4f8/vblo=1,632.99 2006.259.07:49:21.70#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.259.07:49:21.70#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.259.07:49:21.70#ibcon#ireg 17 cls_cnt 0 2006.259.07:49:21.70#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.259.07:49:21.70#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.259.07:49:21.70#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.259.07:49:21.70#ibcon#enter wrdev, iclass 25, count 0 2006.259.07:49:21.70#ibcon#first serial, iclass 25, count 0 2006.259.07:49:21.70#ibcon#enter sib2, iclass 25, count 0 2006.259.07:49:21.70#ibcon#flushed, iclass 25, count 0 2006.259.07:49:21.70#ibcon#about to write, iclass 25, count 0 2006.259.07:49:21.70#ibcon#wrote, iclass 25, count 0 2006.259.07:49:21.70#ibcon#about to read 3, iclass 25, count 0 2006.259.07:49:21.72#ibcon#read 3, iclass 25, count 0 2006.259.07:49:21.72#ibcon#about to read 4, iclass 25, count 0 2006.259.07:49:21.72#ibcon#read 4, iclass 25, count 0 2006.259.07:49:21.72#ibcon#about to read 5, iclass 25, count 0 2006.259.07:49:21.72#ibcon#read 5, iclass 25, count 0 2006.259.07:49:21.72#ibcon#about to read 6, iclass 25, count 0 2006.259.07:49:21.72#ibcon#read 6, iclass 25, count 0 2006.259.07:49:21.72#ibcon#end of sib2, iclass 25, count 0 2006.259.07:49:21.72#ibcon#*mode == 0, iclass 25, count 0 2006.259.07:49:21.72#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.259.07:49:21.72#ibcon#[28=FRQ=01,632.99\r\n] 2006.259.07:49:21.72#ibcon#*before write, iclass 25, count 0 2006.259.07:49:21.72#ibcon#enter sib2, iclass 25, count 0 2006.259.07:49:21.72#ibcon#flushed, iclass 25, count 0 2006.259.07:49:21.72#ibcon#about to write, iclass 25, count 0 2006.259.07:49:21.72#ibcon#wrote, iclass 25, count 0 2006.259.07:49:21.72#ibcon#about to read 3, iclass 25, count 0 2006.259.07:49:21.76#ibcon#read 3, iclass 25, count 0 2006.259.07:49:21.76#ibcon#about to read 4, iclass 25, count 0 2006.259.07:49:21.76#ibcon#read 4, iclass 25, count 0 2006.259.07:49:21.76#ibcon#about to read 5, iclass 25, count 0 2006.259.07:49:21.76#ibcon#read 5, iclass 25, count 0 2006.259.07:49:21.76#ibcon#about to read 6, iclass 25, count 0 2006.259.07:49:21.76#ibcon#read 6, iclass 25, count 0 2006.259.07:49:21.76#ibcon#end of sib2, iclass 25, count 0 2006.259.07:49:21.76#ibcon#*after write, iclass 25, count 0 2006.259.07:49:21.76#ibcon#*before return 0, iclass 25, count 0 2006.259.07:49:21.76#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.259.07:49:21.76#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.259.07:49:21.76#ibcon#about to clear, iclass 25 cls_cnt 0 2006.259.07:49:21.76#ibcon#cleared, iclass 25 cls_cnt 0 2006.259.07:49:21.76$vc4f8/vb=1,4 2006.259.07:49:21.76#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.259.07:49:21.76#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.259.07:49:21.76#ibcon#ireg 11 cls_cnt 2 2006.259.07:49:21.76#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.259.07:49:21.76#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.259.07:49:21.76#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.259.07:49:21.76#ibcon#enter wrdev, iclass 27, count 2 2006.259.07:49:21.76#ibcon#first serial, iclass 27, count 2 2006.259.07:49:21.76#ibcon#enter sib2, iclass 27, count 2 2006.259.07:49:21.76#ibcon#flushed, iclass 27, count 2 2006.259.07:49:21.76#ibcon#about to write, iclass 27, count 2 2006.259.07:49:21.76#ibcon#wrote, iclass 27, count 2 2006.259.07:49:21.76#ibcon#about to read 3, iclass 27, count 2 2006.259.07:49:21.78#ibcon#read 3, iclass 27, count 2 2006.259.07:49:21.78#ibcon#about to read 4, iclass 27, count 2 2006.259.07:49:21.78#ibcon#read 4, iclass 27, count 2 2006.259.07:49:21.78#ibcon#about to read 5, iclass 27, count 2 2006.259.07:49:21.78#ibcon#read 5, iclass 27, count 2 2006.259.07:49:21.78#ibcon#about to read 6, iclass 27, count 2 2006.259.07:49:21.78#ibcon#read 6, iclass 27, count 2 2006.259.07:49:21.78#ibcon#end of sib2, iclass 27, count 2 2006.259.07:49:21.78#ibcon#*mode == 0, iclass 27, count 2 2006.259.07:49:21.78#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.259.07:49:21.78#ibcon#[27=AT01-04\r\n] 2006.259.07:49:21.78#ibcon#*before write, iclass 27, count 2 2006.259.07:49:21.78#ibcon#enter sib2, iclass 27, count 2 2006.259.07:49:21.78#ibcon#flushed, iclass 27, count 2 2006.259.07:49:21.78#ibcon#about to write, iclass 27, count 2 2006.259.07:49:21.78#ibcon#wrote, iclass 27, count 2 2006.259.07:49:21.78#ibcon#about to read 3, iclass 27, count 2 2006.259.07:49:21.81#ibcon#read 3, iclass 27, count 2 2006.259.07:49:21.81#ibcon#about to read 4, iclass 27, count 2 2006.259.07:49:21.81#ibcon#read 4, iclass 27, count 2 2006.259.07:49:21.81#ibcon#about to read 5, iclass 27, count 2 2006.259.07:49:21.81#ibcon#read 5, iclass 27, count 2 2006.259.07:49:21.81#ibcon#about to read 6, iclass 27, count 2 2006.259.07:49:21.81#ibcon#read 6, iclass 27, count 2 2006.259.07:49:21.81#ibcon#end of sib2, iclass 27, count 2 2006.259.07:49:21.81#ibcon#*after write, iclass 27, count 2 2006.259.07:49:21.81#ibcon#*before return 0, iclass 27, count 2 2006.259.07:49:21.81#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.259.07:49:21.81#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.259.07:49:21.81#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.259.07:49:21.81#ibcon#ireg 7 cls_cnt 0 2006.259.07:49:21.81#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.259.07:49:21.93#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.259.07:49:21.93#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.259.07:49:21.93#ibcon#enter wrdev, iclass 27, count 0 2006.259.07:49:21.93#ibcon#first serial, iclass 27, count 0 2006.259.07:49:21.93#ibcon#enter sib2, iclass 27, count 0 2006.259.07:49:21.93#ibcon#flushed, iclass 27, count 0 2006.259.07:49:21.93#ibcon#about to write, iclass 27, count 0 2006.259.07:49:21.93#ibcon#wrote, iclass 27, count 0 2006.259.07:49:21.93#ibcon#about to read 3, iclass 27, count 0 2006.259.07:49:21.95#ibcon#read 3, iclass 27, count 0 2006.259.07:49:21.95#ibcon#about to read 4, iclass 27, count 0 2006.259.07:49:21.95#ibcon#read 4, iclass 27, count 0 2006.259.07:49:21.95#ibcon#about to read 5, iclass 27, count 0 2006.259.07:49:21.95#ibcon#read 5, iclass 27, count 0 2006.259.07:49:21.95#ibcon#about to read 6, iclass 27, count 0 2006.259.07:49:21.95#ibcon#read 6, iclass 27, count 0 2006.259.07:49:21.95#ibcon#end of sib2, iclass 27, count 0 2006.259.07:49:21.95#ibcon#*mode == 0, iclass 27, count 0 2006.259.07:49:21.95#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.259.07:49:21.95#ibcon#[27=USB\r\n] 2006.259.07:49:21.95#ibcon#*before write, iclass 27, count 0 2006.259.07:49:21.95#ibcon#enter sib2, iclass 27, count 0 2006.259.07:49:21.95#ibcon#flushed, iclass 27, count 0 2006.259.07:49:21.95#ibcon#about to write, iclass 27, count 0 2006.259.07:49:21.95#ibcon#wrote, iclass 27, count 0 2006.259.07:49:21.95#ibcon#about to read 3, iclass 27, count 0 2006.259.07:49:21.98#ibcon#read 3, iclass 27, count 0 2006.259.07:49:21.98#ibcon#about to read 4, iclass 27, count 0 2006.259.07:49:21.98#ibcon#read 4, iclass 27, count 0 2006.259.07:49:21.98#ibcon#about to read 5, iclass 27, count 0 2006.259.07:49:21.98#ibcon#read 5, iclass 27, count 0 2006.259.07:49:21.98#ibcon#about to read 6, iclass 27, count 0 2006.259.07:49:21.98#ibcon#read 6, iclass 27, count 0 2006.259.07:49:21.98#ibcon#end of sib2, iclass 27, count 0 2006.259.07:49:21.98#ibcon#*after write, iclass 27, count 0 2006.259.07:49:21.98#ibcon#*before return 0, iclass 27, count 0 2006.259.07:49:21.98#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.259.07:49:21.98#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.259.07:49:21.98#ibcon#about to clear, iclass 27 cls_cnt 0 2006.259.07:49:21.98#ibcon#cleared, iclass 27 cls_cnt 0 2006.259.07:49:21.98$vc4f8/vblo=2,640.99 2006.259.07:49:21.98#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.259.07:49:21.98#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.259.07:49:21.98#ibcon#ireg 17 cls_cnt 0 2006.259.07:49:21.98#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.259.07:49:21.98#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.259.07:49:21.98#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.259.07:49:21.98#ibcon#enter wrdev, iclass 29, count 0 2006.259.07:49:21.98#ibcon#first serial, iclass 29, count 0 2006.259.07:49:21.98#ibcon#enter sib2, iclass 29, count 0 2006.259.07:49:21.98#ibcon#flushed, iclass 29, count 0 2006.259.07:49:21.98#ibcon#about to write, iclass 29, count 0 2006.259.07:49:21.98#ibcon#wrote, iclass 29, count 0 2006.259.07:49:21.98#ibcon#about to read 3, iclass 29, count 0 2006.259.07:49:22.00#ibcon#read 3, iclass 29, count 0 2006.259.07:49:22.00#ibcon#about to read 4, iclass 29, count 0 2006.259.07:49:22.00#ibcon#read 4, iclass 29, count 0 2006.259.07:49:22.00#ibcon#about to read 5, iclass 29, count 0 2006.259.07:49:22.00#ibcon#read 5, iclass 29, count 0 2006.259.07:49:22.00#ibcon#about to read 6, iclass 29, count 0 2006.259.07:49:22.00#ibcon#read 6, iclass 29, count 0 2006.259.07:49:22.00#ibcon#end of sib2, iclass 29, count 0 2006.259.07:49:22.00#ibcon#*mode == 0, iclass 29, count 0 2006.259.07:49:22.00#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.259.07:49:22.00#ibcon#[28=FRQ=02,640.99\r\n] 2006.259.07:49:22.00#ibcon#*before write, iclass 29, count 0 2006.259.07:49:22.00#ibcon#enter sib2, iclass 29, count 0 2006.259.07:49:22.00#ibcon#flushed, iclass 29, count 0 2006.259.07:49:22.00#ibcon#about to write, iclass 29, count 0 2006.259.07:49:22.00#ibcon#wrote, iclass 29, count 0 2006.259.07:49:22.00#ibcon#about to read 3, iclass 29, count 0 2006.259.07:49:22.04#ibcon#read 3, iclass 29, count 0 2006.259.07:49:22.04#ibcon#about to read 4, iclass 29, count 0 2006.259.07:49:22.04#ibcon#read 4, iclass 29, count 0 2006.259.07:49:22.04#ibcon#about to read 5, iclass 29, count 0 2006.259.07:49:22.04#ibcon#read 5, iclass 29, count 0 2006.259.07:49:22.04#ibcon#about to read 6, iclass 29, count 0 2006.259.07:49:22.04#ibcon#read 6, iclass 29, count 0 2006.259.07:49:22.04#ibcon#end of sib2, iclass 29, count 0 2006.259.07:49:22.04#ibcon#*after write, iclass 29, count 0 2006.259.07:49:22.04#ibcon#*before return 0, iclass 29, count 0 2006.259.07:49:22.04#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.259.07:49:22.04#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.259.07:49:22.04#ibcon#about to clear, iclass 29 cls_cnt 0 2006.259.07:49:22.04#ibcon#cleared, iclass 29 cls_cnt 0 2006.259.07:49:22.04$vc4f8/vb=2,5 2006.259.07:49:22.04#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.259.07:49:22.04#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.259.07:49:22.04#ibcon#ireg 11 cls_cnt 2 2006.259.07:49:22.04#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.259.07:49:22.10#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.259.07:49:22.10#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.259.07:49:22.10#ibcon#enter wrdev, iclass 31, count 2 2006.259.07:49:22.10#ibcon#first serial, iclass 31, count 2 2006.259.07:49:22.10#ibcon#enter sib2, iclass 31, count 2 2006.259.07:49:22.10#ibcon#flushed, iclass 31, count 2 2006.259.07:49:22.10#ibcon#about to write, iclass 31, count 2 2006.259.07:49:22.10#ibcon#wrote, iclass 31, count 2 2006.259.07:49:22.10#ibcon#about to read 3, iclass 31, count 2 2006.259.07:49:22.12#ibcon#read 3, iclass 31, count 2 2006.259.07:49:22.12#ibcon#about to read 4, iclass 31, count 2 2006.259.07:49:22.12#ibcon#read 4, iclass 31, count 2 2006.259.07:49:22.12#ibcon#about to read 5, iclass 31, count 2 2006.259.07:49:22.12#ibcon#read 5, iclass 31, count 2 2006.259.07:49:22.12#ibcon#about to read 6, iclass 31, count 2 2006.259.07:49:22.12#ibcon#read 6, iclass 31, count 2 2006.259.07:49:22.12#ibcon#end of sib2, iclass 31, count 2 2006.259.07:49:22.12#ibcon#*mode == 0, iclass 31, count 2 2006.259.07:49:22.12#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.259.07:49:22.12#ibcon#[27=AT02-05\r\n] 2006.259.07:49:22.12#ibcon#*before write, iclass 31, count 2 2006.259.07:49:22.12#ibcon#enter sib2, iclass 31, count 2 2006.259.07:49:22.12#ibcon#flushed, iclass 31, count 2 2006.259.07:49:22.12#ibcon#about to write, iclass 31, count 2 2006.259.07:49:22.12#ibcon#wrote, iclass 31, count 2 2006.259.07:49:22.12#ibcon#about to read 3, iclass 31, count 2 2006.259.07:49:22.15#ibcon#read 3, iclass 31, count 2 2006.259.07:49:22.15#ibcon#about to read 4, iclass 31, count 2 2006.259.07:49:22.15#ibcon#read 4, iclass 31, count 2 2006.259.07:49:22.15#ibcon#about to read 5, iclass 31, count 2 2006.259.07:49:22.15#ibcon#read 5, iclass 31, count 2 2006.259.07:49:22.15#ibcon#about to read 6, iclass 31, count 2 2006.259.07:49:22.15#ibcon#read 6, iclass 31, count 2 2006.259.07:49:22.15#ibcon#end of sib2, iclass 31, count 2 2006.259.07:49:22.15#ibcon#*after write, iclass 31, count 2 2006.259.07:49:22.15#ibcon#*before return 0, iclass 31, count 2 2006.259.07:49:22.15#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.259.07:49:22.15#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.259.07:49:22.15#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.259.07:49:22.15#ibcon#ireg 7 cls_cnt 0 2006.259.07:49:22.15#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.259.07:49:22.27#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.259.07:49:22.27#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.259.07:49:22.27#ibcon#enter wrdev, iclass 31, count 0 2006.259.07:49:22.27#ibcon#first serial, iclass 31, count 0 2006.259.07:49:22.27#ibcon#enter sib2, iclass 31, count 0 2006.259.07:49:22.27#ibcon#flushed, iclass 31, count 0 2006.259.07:49:22.27#ibcon#about to write, iclass 31, count 0 2006.259.07:49:22.27#ibcon#wrote, iclass 31, count 0 2006.259.07:49:22.27#ibcon#about to read 3, iclass 31, count 0 2006.259.07:49:22.29#ibcon#read 3, iclass 31, count 0 2006.259.07:49:22.29#ibcon#about to read 4, iclass 31, count 0 2006.259.07:49:22.29#ibcon#read 4, iclass 31, count 0 2006.259.07:49:22.29#ibcon#about to read 5, iclass 31, count 0 2006.259.07:49:22.29#ibcon#read 5, iclass 31, count 0 2006.259.07:49:22.29#ibcon#about to read 6, iclass 31, count 0 2006.259.07:49:22.29#ibcon#read 6, iclass 31, count 0 2006.259.07:49:22.29#ibcon#end of sib2, iclass 31, count 0 2006.259.07:49:22.29#ibcon#*mode == 0, iclass 31, count 0 2006.259.07:49:22.29#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.259.07:49:22.29#ibcon#[27=USB\r\n] 2006.259.07:49:22.29#ibcon#*before write, iclass 31, count 0 2006.259.07:49:22.29#ibcon#enter sib2, iclass 31, count 0 2006.259.07:49:22.29#ibcon#flushed, iclass 31, count 0 2006.259.07:49:22.29#ibcon#about to write, iclass 31, count 0 2006.259.07:49:22.29#ibcon#wrote, iclass 31, count 0 2006.259.07:49:22.29#ibcon#about to read 3, iclass 31, count 0 2006.259.07:49:22.32#ibcon#read 3, iclass 31, count 0 2006.259.07:49:22.32#ibcon#about to read 4, iclass 31, count 0 2006.259.07:49:22.32#ibcon#read 4, iclass 31, count 0 2006.259.07:49:22.32#ibcon#about to read 5, iclass 31, count 0 2006.259.07:49:22.32#ibcon#read 5, iclass 31, count 0 2006.259.07:49:22.32#ibcon#about to read 6, iclass 31, count 0 2006.259.07:49:22.32#ibcon#read 6, iclass 31, count 0 2006.259.07:49:22.32#ibcon#end of sib2, iclass 31, count 0 2006.259.07:49:22.32#ibcon#*after write, iclass 31, count 0 2006.259.07:49:22.32#ibcon#*before return 0, iclass 31, count 0 2006.259.07:49:22.32#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.259.07:49:22.32#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.259.07:49:22.32#ibcon#about to clear, iclass 31 cls_cnt 0 2006.259.07:49:22.32#ibcon#cleared, iclass 31 cls_cnt 0 2006.259.07:49:22.32$vc4f8/vblo=3,656.99 2006.259.07:49:22.32#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.259.07:49:22.32#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.259.07:49:22.32#ibcon#ireg 17 cls_cnt 0 2006.259.07:49:22.32#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.259.07:49:22.32#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.259.07:49:22.32#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.259.07:49:22.32#ibcon#enter wrdev, iclass 33, count 0 2006.259.07:49:22.32#ibcon#first serial, iclass 33, count 0 2006.259.07:49:22.32#ibcon#enter sib2, iclass 33, count 0 2006.259.07:49:22.32#ibcon#flushed, iclass 33, count 0 2006.259.07:49:22.32#ibcon#about to write, iclass 33, count 0 2006.259.07:49:22.32#ibcon#wrote, iclass 33, count 0 2006.259.07:49:22.32#ibcon#about to read 3, iclass 33, count 0 2006.259.07:49:22.34#ibcon#read 3, iclass 33, count 0 2006.259.07:49:22.34#ibcon#about to read 4, iclass 33, count 0 2006.259.07:49:22.34#ibcon#read 4, iclass 33, count 0 2006.259.07:49:22.34#ibcon#about to read 5, iclass 33, count 0 2006.259.07:49:22.34#ibcon#read 5, iclass 33, count 0 2006.259.07:49:22.34#ibcon#about to read 6, iclass 33, count 0 2006.259.07:49:22.34#ibcon#read 6, iclass 33, count 0 2006.259.07:49:22.34#ibcon#end of sib2, iclass 33, count 0 2006.259.07:49:22.34#ibcon#*mode == 0, iclass 33, count 0 2006.259.07:49:22.34#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.259.07:49:22.34#ibcon#[28=FRQ=03,656.99\r\n] 2006.259.07:49:22.34#ibcon#*before write, iclass 33, count 0 2006.259.07:49:22.34#ibcon#enter sib2, iclass 33, count 0 2006.259.07:49:22.34#ibcon#flushed, iclass 33, count 0 2006.259.07:49:22.34#ibcon#about to write, iclass 33, count 0 2006.259.07:49:22.34#ibcon#wrote, iclass 33, count 0 2006.259.07:49:22.34#ibcon#about to read 3, iclass 33, count 0 2006.259.07:49:22.38#ibcon#read 3, iclass 33, count 0 2006.259.07:49:22.38#ibcon#about to read 4, iclass 33, count 0 2006.259.07:49:22.38#ibcon#read 4, iclass 33, count 0 2006.259.07:49:22.38#ibcon#about to read 5, iclass 33, count 0 2006.259.07:49:22.38#ibcon#read 5, iclass 33, count 0 2006.259.07:49:22.38#ibcon#about to read 6, iclass 33, count 0 2006.259.07:49:22.38#ibcon#read 6, iclass 33, count 0 2006.259.07:49:22.38#ibcon#end of sib2, iclass 33, count 0 2006.259.07:49:22.38#ibcon#*after write, iclass 33, count 0 2006.259.07:49:22.38#ibcon#*before return 0, iclass 33, count 0 2006.259.07:49:22.38#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.259.07:49:22.38#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.259.07:49:22.38#ibcon#about to clear, iclass 33 cls_cnt 0 2006.259.07:49:22.38#ibcon#cleared, iclass 33 cls_cnt 0 2006.259.07:49:22.38$vc4f8/vb=3,4 2006.259.07:49:22.38#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.259.07:49:22.38#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.259.07:49:22.38#ibcon#ireg 11 cls_cnt 2 2006.259.07:49:22.38#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.259.07:49:22.44#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.259.07:49:22.44#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.259.07:49:22.44#ibcon#enter wrdev, iclass 35, count 2 2006.259.07:49:22.44#ibcon#first serial, iclass 35, count 2 2006.259.07:49:22.44#ibcon#enter sib2, iclass 35, count 2 2006.259.07:49:22.44#ibcon#flushed, iclass 35, count 2 2006.259.07:49:22.44#ibcon#about to write, iclass 35, count 2 2006.259.07:49:22.44#ibcon#wrote, iclass 35, count 2 2006.259.07:49:22.44#ibcon#about to read 3, iclass 35, count 2 2006.259.07:49:22.46#ibcon#read 3, iclass 35, count 2 2006.259.07:49:22.46#ibcon#about to read 4, iclass 35, count 2 2006.259.07:49:22.46#ibcon#read 4, iclass 35, count 2 2006.259.07:49:22.46#ibcon#about to read 5, iclass 35, count 2 2006.259.07:49:22.46#ibcon#read 5, iclass 35, count 2 2006.259.07:49:22.46#ibcon#about to read 6, iclass 35, count 2 2006.259.07:49:22.46#ibcon#read 6, iclass 35, count 2 2006.259.07:49:22.46#ibcon#end of sib2, iclass 35, count 2 2006.259.07:49:22.46#ibcon#*mode == 0, iclass 35, count 2 2006.259.07:49:22.46#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.259.07:49:22.46#ibcon#[27=AT03-04\r\n] 2006.259.07:49:22.46#ibcon#*before write, iclass 35, count 2 2006.259.07:49:22.46#ibcon#enter sib2, iclass 35, count 2 2006.259.07:49:22.46#ibcon#flushed, iclass 35, count 2 2006.259.07:49:22.46#ibcon#about to write, iclass 35, count 2 2006.259.07:49:22.46#ibcon#wrote, iclass 35, count 2 2006.259.07:49:22.46#ibcon#about to read 3, iclass 35, count 2 2006.259.07:49:22.49#ibcon#read 3, iclass 35, count 2 2006.259.07:49:22.49#ibcon#about to read 4, iclass 35, count 2 2006.259.07:49:22.49#ibcon#read 4, iclass 35, count 2 2006.259.07:49:22.49#ibcon#about to read 5, iclass 35, count 2 2006.259.07:49:22.49#ibcon#read 5, iclass 35, count 2 2006.259.07:49:22.49#ibcon#about to read 6, iclass 35, count 2 2006.259.07:49:22.49#ibcon#read 6, iclass 35, count 2 2006.259.07:49:22.49#ibcon#end of sib2, iclass 35, count 2 2006.259.07:49:22.49#ibcon#*after write, iclass 35, count 2 2006.259.07:49:22.49#ibcon#*before return 0, iclass 35, count 2 2006.259.07:49:22.49#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.259.07:49:22.49#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.259.07:49:22.49#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.259.07:49:22.49#ibcon#ireg 7 cls_cnt 0 2006.259.07:49:22.49#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.259.07:49:22.61#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.259.07:49:22.61#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.259.07:49:22.61#ibcon#enter wrdev, iclass 35, count 0 2006.259.07:49:22.61#ibcon#first serial, iclass 35, count 0 2006.259.07:49:22.61#ibcon#enter sib2, iclass 35, count 0 2006.259.07:49:22.61#ibcon#flushed, iclass 35, count 0 2006.259.07:49:22.61#ibcon#about to write, iclass 35, count 0 2006.259.07:49:22.61#ibcon#wrote, iclass 35, count 0 2006.259.07:49:22.61#ibcon#about to read 3, iclass 35, count 0 2006.259.07:49:22.63#ibcon#read 3, iclass 35, count 0 2006.259.07:49:22.63#ibcon#about to read 4, iclass 35, count 0 2006.259.07:49:22.63#ibcon#read 4, iclass 35, count 0 2006.259.07:49:22.63#ibcon#about to read 5, iclass 35, count 0 2006.259.07:49:22.63#ibcon#read 5, iclass 35, count 0 2006.259.07:49:22.63#ibcon#about to read 6, iclass 35, count 0 2006.259.07:49:22.63#ibcon#read 6, iclass 35, count 0 2006.259.07:49:22.63#ibcon#end of sib2, iclass 35, count 0 2006.259.07:49:22.63#ibcon#*mode == 0, iclass 35, count 0 2006.259.07:49:22.63#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.259.07:49:22.63#ibcon#[27=USB\r\n] 2006.259.07:49:22.63#ibcon#*before write, iclass 35, count 0 2006.259.07:49:22.63#ibcon#enter sib2, iclass 35, count 0 2006.259.07:49:22.63#ibcon#flushed, iclass 35, count 0 2006.259.07:49:22.63#ibcon#about to write, iclass 35, count 0 2006.259.07:49:22.63#ibcon#wrote, iclass 35, count 0 2006.259.07:49:22.63#ibcon#about to read 3, iclass 35, count 0 2006.259.07:49:22.66#ibcon#read 3, iclass 35, count 0 2006.259.07:49:22.66#ibcon#about to read 4, iclass 35, count 0 2006.259.07:49:22.66#ibcon#read 4, iclass 35, count 0 2006.259.07:49:22.66#ibcon#about to read 5, iclass 35, count 0 2006.259.07:49:22.66#ibcon#read 5, iclass 35, count 0 2006.259.07:49:22.66#ibcon#about to read 6, iclass 35, count 0 2006.259.07:49:22.66#ibcon#read 6, iclass 35, count 0 2006.259.07:49:22.66#ibcon#end of sib2, iclass 35, count 0 2006.259.07:49:22.66#ibcon#*after write, iclass 35, count 0 2006.259.07:49:22.66#ibcon#*before return 0, iclass 35, count 0 2006.259.07:49:22.66#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.259.07:49:22.66#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.259.07:49:22.66#ibcon#about to clear, iclass 35 cls_cnt 0 2006.259.07:49:22.66#ibcon#cleared, iclass 35 cls_cnt 0 2006.259.07:49:22.66$vc4f8/vblo=4,712.99 2006.259.07:49:22.66#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.259.07:49:22.66#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.259.07:49:22.66#ibcon#ireg 17 cls_cnt 0 2006.259.07:49:22.66#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.259.07:49:22.66#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.259.07:49:22.66#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.259.07:49:22.66#ibcon#enter wrdev, iclass 37, count 0 2006.259.07:49:22.66#ibcon#first serial, iclass 37, count 0 2006.259.07:49:22.66#ibcon#enter sib2, iclass 37, count 0 2006.259.07:49:22.66#ibcon#flushed, iclass 37, count 0 2006.259.07:49:22.66#ibcon#about to write, iclass 37, count 0 2006.259.07:49:22.66#ibcon#wrote, iclass 37, count 0 2006.259.07:49:22.66#ibcon#about to read 3, iclass 37, count 0 2006.259.07:49:22.68#ibcon#read 3, iclass 37, count 0 2006.259.07:49:22.68#ibcon#about to read 4, iclass 37, count 0 2006.259.07:49:22.68#ibcon#read 4, iclass 37, count 0 2006.259.07:49:22.68#ibcon#about to read 5, iclass 37, count 0 2006.259.07:49:22.68#ibcon#read 5, iclass 37, count 0 2006.259.07:49:22.68#ibcon#about to read 6, iclass 37, count 0 2006.259.07:49:22.68#ibcon#read 6, iclass 37, count 0 2006.259.07:49:22.68#ibcon#end of sib2, iclass 37, count 0 2006.259.07:49:22.68#ibcon#*mode == 0, iclass 37, count 0 2006.259.07:49:22.68#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.259.07:49:22.68#ibcon#[28=FRQ=04,712.99\r\n] 2006.259.07:49:22.68#ibcon#*before write, iclass 37, count 0 2006.259.07:49:22.68#ibcon#enter sib2, iclass 37, count 0 2006.259.07:49:22.68#ibcon#flushed, iclass 37, count 0 2006.259.07:49:22.68#ibcon#about to write, iclass 37, count 0 2006.259.07:49:22.68#ibcon#wrote, iclass 37, count 0 2006.259.07:49:22.68#ibcon#about to read 3, iclass 37, count 0 2006.259.07:49:22.72#ibcon#read 3, iclass 37, count 0 2006.259.07:49:22.72#ibcon#about to read 4, iclass 37, count 0 2006.259.07:49:22.72#ibcon#read 4, iclass 37, count 0 2006.259.07:49:22.72#ibcon#about to read 5, iclass 37, count 0 2006.259.07:49:22.72#ibcon#read 5, iclass 37, count 0 2006.259.07:49:22.72#ibcon#about to read 6, iclass 37, count 0 2006.259.07:49:22.72#ibcon#read 6, iclass 37, count 0 2006.259.07:49:22.72#ibcon#end of sib2, iclass 37, count 0 2006.259.07:49:22.72#ibcon#*after write, iclass 37, count 0 2006.259.07:49:22.72#ibcon#*before return 0, iclass 37, count 0 2006.259.07:49:22.72#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.259.07:49:22.72#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.259.07:49:22.72#ibcon#about to clear, iclass 37 cls_cnt 0 2006.259.07:49:22.72#ibcon#cleared, iclass 37 cls_cnt 0 2006.259.07:49:22.72$vc4f8/vb=4,5 2006.259.07:49:22.72#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.259.07:49:22.72#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.259.07:49:22.72#ibcon#ireg 11 cls_cnt 2 2006.259.07:49:22.72#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.259.07:49:22.78#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.259.07:49:22.78#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.259.07:49:22.78#ibcon#enter wrdev, iclass 39, count 2 2006.259.07:49:22.78#ibcon#first serial, iclass 39, count 2 2006.259.07:49:22.78#ibcon#enter sib2, iclass 39, count 2 2006.259.07:49:22.78#ibcon#flushed, iclass 39, count 2 2006.259.07:49:22.78#ibcon#about to write, iclass 39, count 2 2006.259.07:49:22.78#ibcon#wrote, iclass 39, count 2 2006.259.07:49:22.78#ibcon#about to read 3, iclass 39, count 2 2006.259.07:49:22.80#ibcon#read 3, iclass 39, count 2 2006.259.07:49:22.80#ibcon#about to read 4, iclass 39, count 2 2006.259.07:49:22.80#ibcon#read 4, iclass 39, count 2 2006.259.07:49:22.80#ibcon#about to read 5, iclass 39, count 2 2006.259.07:49:22.80#ibcon#read 5, iclass 39, count 2 2006.259.07:49:22.80#ibcon#about to read 6, iclass 39, count 2 2006.259.07:49:22.80#ibcon#read 6, iclass 39, count 2 2006.259.07:49:22.80#ibcon#end of sib2, iclass 39, count 2 2006.259.07:49:22.80#ibcon#*mode == 0, iclass 39, count 2 2006.259.07:49:22.80#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.259.07:49:22.80#ibcon#[27=AT04-05\r\n] 2006.259.07:49:22.80#ibcon#*before write, iclass 39, count 2 2006.259.07:49:22.80#ibcon#enter sib2, iclass 39, count 2 2006.259.07:49:22.80#ibcon#flushed, iclass 39, count 2 2006.259.07:49:22.80#ibcon#about to write, iclass 39, count 2 2006.259.07:49:22.80#ibcon#wrote, iclass 39, count 2 2006.259.07:49:22.80#ibcon#about to read 3, iclass 39, count 2 2006.259.07:49:22.83#ibcon#read 3, iclass 39, count 2 2006.259.07:49:22.83#ibcon#about to read 4, iclass 39, count 2 2006.259.07:49:22.83#ibcon#read 4, iclass 39, count 2 2006.259.07:49:22.83#ibcon#about to read 5, iclass 39, count 2 2006.259.07:49:22.83#ibcon#read 5, iclass 39, count 2 2006.259.07:49:22.83#ibcon#about to read 6, iclass 39, count 2 2006.259.07:49:22.83#ibcon#read 6, iclass 39, count 2 2006.259.07:49:22.83#ibcon#end of sib2, iclass 39, count 2 2006.259.07:49:22.83#ibcon#*after write, iclass 39, count 2 2006.259.07:49:22.83#ibcon#*before return 0, iclass 39, count 2 2006.259.07:49:22.83#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.259.07:49:22.83#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.259.07:49:22.83#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.259.07:49:22.83#ibcon#ireg 7 cls_cnt 0 2006.259.07:49:22.83#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.259.07:49:22.95#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.259.07:49:22.95#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.259.07:49:22.95#ibcon#enter wrdev, iclass 39, count 0 2006.259.07:49:22.95#ibcon#first serial, iclass 39, count 0 2006.259.07:49:22.95#ibcon#enter sib2, iclass 39, count 0 2006.259.07:49:22.95#ibcon#flushed, iclass 39, count 0 2006.259.07:49:22.95#ibcon#about to write, iclass 39, count 0 2006.259.07:49:22.95#ibcon#wrote, iclass 39, count 0 2006.259.07:49:22.95#ibcon#about to read 3, iclass 39, count 0 2006.259.07:49:22.97#ibcon#read 3, iclass 39, count 0 2006.259.07:49:22.97#ibcon#about to read 4, iclass 39, count 0 2006.259.07:49:22.97#ibcon#read 4, iclass 39, count 0 2006.259.07:49:22.97#ibcon#about to read 5, iclass 39, count 0 2006.259.07:49:22.97#ibcon#read 5, iclass 39, count 0 2006.259.07:49:22.97#ibcon#about to read 6, iclass 39, count 0 2006.259.07:49:22.97#ibcon#read 6, iclass 39, count 0 2006.259.07:49:22.97#ibcon#end of sib2, iclass 39, count 0 2006.259.07:49:22.97#ibcon#*mode == 0, iclass 39, count 0 2006.259.07:49:22.97#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.259.07:49:22.97#ibcon#[27=USB\r\n] 2006.259.07:49:22.97#ibcon#*before write, iclass 39, count 0 2006.259.07:49:22.97#ibcon#enter sib2, iclass 39, count 0 2006.259.07:49:22.97#ibcon#flushed, iclass 39, count 0 2006.259.07:49:22.97#ibcon#about to write, iclass 39, count 0 2006.259.07:49:22.97#ibcon#wrote, iclass 39, count 0 2006.259.07:49:22.97#ibcon#about to read 3, iclass 39, count 0 2006.259.07:49:23.00#ibcon#read 3, iclass 39, count 0 2006.259.07:49:23.00#ibcon#about to read 4, iclass 39, count 0 2006.259.07:49:23.00#ibcon#read 4, iclass 39, count 0 2006.259.07:49:23.00#ibcon#about to read 5, iclass 39, count 0 2006.259.07:49:23.00#ibcon#read 5, iclass 39, count 0 2006.259.07:49:23.00#ibcon#about to read 6, iclass 39, count 0 2006.259.07:49:23.00#ibcon#read 6, iclass 39, count 0 2006.259.07:49:23.00#ibcon#end of sib2, iclass 39, count 0 2006.259.07:49:23.00#ibcon#*after write, iclass 39, count 0 2006.259.07:49:23.00#ibcon#*before return 0, iclass 39, count 0 2006.259.07:49:23.00#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.259.07:49:23.00#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.259.07:49:23.00#ibcon#about to clear, iclass 39 cls_cnt 0 2006.259.07:49:23.00#ibcon#cleared, iclass 39 cls_cnt 0 2006.259.07:49:23.00$vc4f8/vblo=5,744.99 2006.259.07:49:23.00#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.259.07:49:23.00#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.259.07:49:23.00#ibcon#ireg 17 cls_cnt 0 2006.259.07:49:23.00#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.259.07:49:23.00#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.259.07:49:23.00#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.259.07:49:23.00#ibcon#enter wrdev, iclass 3, count 0 2006.259.07:49:23.00#ibcon#first serial, iclass 3, count 0 2006.259.07:49:23.00#ibcon#enter sib2, iclass 3, count 0 2006.259.07:49:23.00#ibcon#flushed, iclass 3, count 0 2006.259.07:49:23.00#ibcon#about to write, iclass 3, count 0 2006.259.07:49:23.00#ibcon#wrote, iclass 3, count 0 2006.259.07:49:23.00#ibcon#about to read 3, iclass 3, count 0 2006.259.07:49:23.02#ibcon#read 3, iclass 3, count 0 2006.259.07:49:23.02#ibcon#about to read 4, iclass 3, count 0 2006.259.07:49:23.02#ibcon#read 4, iclass 3, count 0 2006.259.07:49:23.02#ibcon#about to read 5, iclass 3, count 0 2006.259.07:49:23.02#ibcon#read 5, iclass 3, count 0 2006.259.07:49:23.02#ibcon#about to read 6, iclass 3, count 0 2006.259.07:49:23.02#ibcon#read 6, iclass 3, count 0 2006.259.07:49:23.02#ibcon#end of sib2, iclass 3, count 0 2006.259.07:49:23.02#ibcon#*mode == 0, iclass 3, count 0 2006.259.07:49:23.02#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.259.07:49:23.02#ibcon#[28=FRQ=05,744.99\r\n] 2006.259.07:49:23.02#ibcon#*before write, iclass 3, count 0 2006.259.07:49:23.02#ibcon#enter sib2, iclass 3, count 0 2006.259.07:49:23.02#ibcon#flushed, iclass 3, count 0 2006.259.07:49:23.02#ibcon#about to write, iclass 3, count 0 2006.259.07:49:23.02#ibcon#wrote, iclass 3, count 0 2006.259.07:49:23.02#ibcon#about to read 3, iclass 3, count 0 2006.259.07:49:23.06#ibcon#read 3, iclass 3, count 0 2006.259.07:49:23.06#ibcon#about to read 4, iclass 3, count 0 2006.259.07:49:23.06#ibcon#read 4, iclass 3, count 0 2006.259.07:49:23.06#ibcon#about to read 5, iclass 3, count 0 2006.259.07:49:23.06#ibcon#read 5, iclass 3, count 0 2006.259.07:49:23.06#ibcon#about to read 6, iclass 3, count 0 2006.259.07:49:23.06#ibcon#read 6, iclass 3, count 0 2006.259.07:49:23.06#ibcon#end of sib2, iclass 3, count 0 2006.259.07:49:23.06#ibcon#*after write, iclass 3, count 0 2006.259.07:49:23.06#ibcon#*before return 0, iclass 3, count 0 2006.259.07:49:23.06#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.259.07:49:23.06#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.259.07:49:23.06#ibcon#about to clear, iclass 3 cls_cnt 0 2006.259.07:49:23.06#ibcon#cleared, iclass 3 cls_cnt 0 2006.259.07:49:23.06$vc4f8/vb=5,4 2006.259.07:49:23.06#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.259.07:49:23.06#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.259.07:49:23.06#ibcon#ireg 11 cls_cnt 2 2006.259.07:49:23.06#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.259.07:49:23.12#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.259.07:49:23.12#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.259.07:49:23.12#ibcon#enter wrdev, iclass 5, count 2 2006.259.07:49:23.12#ibcon#first serial, iclass 5, count 2 2006.259.07:49:23.12#ibcon#enter sib2, iclass 5, count 2 2006.259.07:49:23.12#ibcon#flushed, iclass 5, count 2 2006.259.07:49:23.12#ibcon#about to write, iclass 5, count 2 2006.259.07:49:23.12#ibcon#wrote, iclass 5, count 2 2006.259.07:49:23.12#ibcon#about to read 3, iclass 5, count 2 2006.259.07:49:23.14#ibcon#read 3, iclass 5, count 2 2006.259.07:49:23.14#ibcon#about to read 4, iclass 5, count 2 2006.259.07:49:23.14#ibcon#read 4, iclass 5, count 2 2006.259.07:49:23.14#ibcon#about to read 5, iclass 5, count 2 2006.259.07:49:23.14#ibcon#read 5, iclass 5, count 2 2006.259.07:49:23.14#ibcon#about to read 6, iclass 5, count 2 2006.259.07:49:23.14#ibcon#read 6, iclass 5, count 2 2006.259.07:49:23.14#ibcon#end of sib2, iclass 5, count 2 2006.259.07:49:23.14#ibcon#*mode == 0, iclass 5, count 2 2006.259.07:49:23.14#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.259.07:49:23.14#ibcon#[27=AT05-04\r\n] 2006.259.07:49:23.14#ibcon#*before write, iclass 5, count 2 2006.259.07:49:23.14#ibcon#enter sib2, iclass 5, count 2 2006.259.07:49:23.14#ibcon#flushed, iclass 5, count 2 2006.259.07:49:23.14#ibcon#about to write, iclass 5, count 2 2006.259.07:49:23.14#ibcon#wrote, iclass 5, count 2 2006.259.07:49:23.14#ibcon#about to read 3, iclass 5, count 2 2006.259.07:49:23.17#ibcon#read 3, iclass 5, count 2 2006.259.07:49:23.17#ibcon#about to read 4, iclass 5, count 2 2006.259.07:49:23.17#ibcon#read 4, iclass 5, count 2 2006.259.07:49:23.17#ibcon#about to read 5, iclass 5, count 2 2006.259.07:49:23.17#ibcon#read 5, iclass 5, count 2 2006.259.07:49:23.17#ibcon#about to read 6, iclass 5, count 2 2006.259.07:49:23.17#ibcon#read 6, iclass 5, count 2 2006.259.07:49:23.17#ibcon#end of sib2, iclass 5, count 2 2006.259.07:49:23.17#ibcon#*after write, iclass 5, count 2 2006.259.07:49:23.17#ibcon#*before return 0, iclass 5, count 2 2006.259.07:49:23.17#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.259.07:49:23.17#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.259.07:49:23.17#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.259.07:49:23.17#ibcon#ireg 7 cls_cnt 0 2006.259.07:49:23.17#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.259.07:49:23.29#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.259.07:49:23.29#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.259.07:49:23.29#ibcon#enter wrdev, iclass 5, count 0 2006.259.07:49:23.29#ibcon#first serial, iclass 5, count 0 2006.259.07:49:23.29#ibcon#enter sib2, iclass 5, count 0 2006.259.07:49:23.29#ibcon#flushed, iclass 5, count 0 2006.259.07:49:23.29#ibcon#about to write, iclass 5, count 0 2006.259.07:49:23.29#ibcon#wrote, iclass 5, count 0 2006.259.07:49:23.29#ibcon#about to read 3, iclass 5, count 0 2006.259.07:49:23.31#ibcon#read 3, iclass 5, count 0 2006.259.07:49:23.31#ibcon#about to read 4, iclass 5, count 0 2006.259.07:49:23.31#ibcon#read 4, iclass 5, count 0 2006.259.07:49:23.31#ibcon#about to read 5, iclass 5, count 0 2006.259.07:49:23.31#ibcon#read 5, iclass 5, count 0 2006.259.07:49:23.31#ibcon#about to read 6, iclass 5, count 0 2006.259.07:49:23.31#ibcon#read 6, iclass 5, count 0 2006.259.07:49:23.31#ibcon#end of sib2, iclass 5, count 0 2006.259.07:49:23.31#ibcon#*mode == 0, iclass 5, count 0 2006.259.07:49:23.31#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.259.07:49:23.31#ibcon#[27=USB\r\n] 2006.259.07:49:23.31#ibcon#*before write, iclass 5, count 0 2006.259.07:49:23.31#ibcon#enter sib2, iclass 5, count 0 2006.259.07:49:23.31#ibcon#flushed, iclass 5, count 0 2006.259.07:49:23.31#ibcon#about to write, iclass 5, count 0 2006.259.07:49:23.31#ibcon#wrote, iclass 5, count 0 2006.259.07:49:23.31#ibcon#about to read 3, iclass 5, count 0 2006.259.07:49:23.34#ibcon#read 3, iclass 5, count 0 2006.259.07:49:23.34#ibcon#about to read 4, iclass 5, count 0 2006.259.07:49:23.34#ibcon#read 4, iclass 5, count 0 2006.259.07:49:23.34#ibcon#about to read 5, iclass 5, count 0 2006.259.07:49:23.34#ibcon#read 5, iclass 5, count 0 2006.259.07:49:23.34#ibcon#about to read 6, iclass 5, count 0 2006.259.07:49:23.34#ibcon#read 6, iclass 5, count 0 2006.259.07:49:23.34#ibcon#end of sib2, iclass 5, count 0 2006.259.07:49:23.34#ibcon#*after write, iclass 5, count 0 2006.259.07:49:23.34#ibcon#*before return 0, iclass 5, count 0 2006.259.07:49:23.34#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.259.07:49:23.34#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.259.07:49:23.34#ibcon#about to clear, iclass 5 cls_cnt 0 2006.259.07:49:23.34#ibcon#cleared, iclass 5 cls_cnt 0 2006.259.07:49:23.34$vc4f8/vblo=6,752.99 2006.259.07:49:23.34#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.259.07:49:23.34#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.259.07:49:23.34#ibcon#ireg 17 cls_cnt 0 2006.259.07:49:23.34#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.259.07:49:23.34#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.259.07:49:23.34#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.259.07:49:23.34#ibcon#enter wrdev, iclass 7, count 0 2006.259.07:49:23.34#ibcon#first serial, iclass 7, count 0 2006.259.07:49:23.34#ibcon#enter sib2, iclass 7, count 0 2006.259.07:49:23.34#ibcon#flushed, iclass 7, count 0 2006.259.07:49:23.34#ibcon#about to write, iclass 7, count 0 2006.259.07:49:23.34#ibcon#wrote, iclass 7, count 0 2006.259.07:49:23.34#ibcon#about to read 3, iclass 7, count 0 2006.259.07:49:23.36#ibcon#read 3, iclass 7, count 0 2006.259.07:49:23.36#ibcon#about to read 4, iclass 7, count 0 2006.259.07:49:23.36#ibcon#read 4, iclass 7, count 0 2006.259.07:49:23.36#ibcon#about to read 5, iclass 7, count 0 2006.259.07:49:23.36#ibcon#read 5, iclass 7, count 0 2006.259.07:49:23.36#ibcon#about to read 6, iclass 7, count 0 2006.259.07:49:23.36#ibcon#read 6, iclass 7, count 0 2006.259.07:49:23.36#ibcon#end of sib2, iclass 7, count 0 2006.259.07:49:23.36#ibcon#*mode == 0, iclass 7, count 0 2006.259.07:49:23.36#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.259.07:49:23.36#ibcon#[28=FRQ=06,752.99\r\n] 2006.259.07:49:23.36#ibcon#*before write, iclass 7, count 0 2006.259.07:49:23.36#ibcon#enter sib2, iclass 7, count 0 2006.259.07:49:23.36#ibcon#flushed, iclass 7, count 0 2006.259.07:49:23.36#ibcon#about to write, iclass 7, count 0 2006.259.07:49:23.36#ibcon#wrote, iclass 7, count 0 2006.259.07:49:23.36#ibcon#about to read 3, iclass 7, count 0 2006.259.07:49:23.40#ibcon#read 3, iclass 7, count 0 2006.259.07:49:23.40#ibcon#about to read 4, iclass 7, count 0 2006.259.07:49:23.40#ibcon#read 4, iclass 7, count 0 2006.259.07:49:23.40#ibcon#about to read 5, iclass 7, count 0 2006.259.07:49:23.40#ibcon#read 5, iclass 7, count 0 2006.259.07:49:23.40#ibcon#about to read 6, iclass 7, count 0 2006.259.07:49:23.40#ibcon#read 6, iclass 7, count 0 2006.259.07:49:23.40#ibcon#end of sib2, iclass 7, count 0 2006.259.07:49:23.40#ibcon#*after write, iclass 7, count 0 2006.259.07:49:23.40#ibcon#*before return 0, iclass 7, count 0 2006.259.07:49:23.40#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.259.07:49:23.40#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.259.07:49:23.40#ibcon#about to clear, iclass 7 cls_cnt 0 2006.259.07:49:23.40#ibcon#cleared, iclass 7 cls_cnt 0 2006.259.07:49:23.40$vc4f8/vb=6,4 2006.259.07:49:23.40#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.259.07:49:23.40#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.259.07:49:23.40#ibcon#ireg 11 cls_cnt 2 2006.259.07:49:23.40#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.259.07:49:23.46#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.259.07:49:23.46#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.259.07:49:23.46#ibcon#enter wrdev, iclass 11, count 2 2006.259.07:49:23.46#ibcon#first serial, iclass 11, count 2 2006.259.07:49:23.46#ibcon#enter sib2, iclass 11, count 2 2006.259.07:49:23.46#ibcon#flushed, iclass 11, count 2 2006.259.07:49:23.46#ibcon#about to write, iclass 11, count 2 2006.259.07:49:23.46#ibcon#wrote, iclass 11, count 2 2006.259.07:49:23.46#ibcon#about to read 3, iclass 11, count 2 2006.259.07:49:23.48#ibcon#read 3, iclass 11, count 2 2006.259.07:49:23.48#ibcon#about to read 4, iclass 11, count 2 2006.259.07:49:23.48#ibcon#read 4, iclass 11, count 2 2006.259.07:49:23.48#ibcon#about to read 5, iclass 11, count 2 2006.259.07:49:23.48#ibcon#read 5, iclass 11, count 2 2006.259.07:49:23.48#ibcon#about to read 6, iclass 11, count 2 2006.259.07:49:23.48#ibcon#read 6, iclass 11, count 2 2006.259.07:49:23.48#ibcon#end of sib2, iclass 11, count 2 2006.259.07:49:23.48#ibcon#*mode == 0, iclass 11, count 2 2006.259.07:49:23.48#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.259.07:49:23.48#ibcon#[27=AT06-04\r\n] 2006.259.07:49:23.48#ibcon#*before write, iclass 11, count 2 2006.259.07:49:23.48#ibcon#enter sib2, iclass 11, count 2 2006.259.07:49:23.48#ibcon#flushed, iclass 11, count 2 2006.259.07:49:23.48#ibcon#about to write, iclass 11, count 2 2006.259.07:49:23.48#ibcon#wrote, iclass 11, count 2 2006.259.07:49:23.48#ibcon#about to read 3, iclass 11, count 2 2006.259.07:49:23.51#ibcon#read 3, iclass 11, count 2 2006.259.07:49:23.51#ibcon#about to read 4, iclass 11, count 2 2006.259.07:49:23.51#ibcon#read 4, iclass 11, count 2 2006.259.07:49:23.51#ibcon#about to read 5, iclass 11, count 2 2006.259.07:49:23.51#ibcon#read 5, iclass 11, count 2 2006.259.07:49:23.51#ibcon#about to read 6, iclass 11, count 2 2006.259.07:49:23.51#ibcon#read 6, iclass 11, count 2 2006.259.07:49:23.51#ibcon#end of sib2, iclass 11, count 2 2006.259.07:49:23.51#ibcon#*after write, iclass 11, count 2 2006.259.07:49:23.51#ibcon#*before return 0, iclass 11, count 2 2006.259.07:49:23.51#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.259.07:49:23.51#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.259.07:49:23.51#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.259.07:49:23.51#ibcon#ireg 7 cls_cnt 0 2006.259.07:49:23.51#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.259.07:49:23.63#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.259.07:49:23.63#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.259.07:49:23.63#ibcon#enter wrdev, iclass 11, count 0 2006.259.07:49:23.63#ibcon#first serial, iclass 11, count 0 2006.259.07:49:23.63#ibcon#enter sib2, iclass 11, count 0 2006.259.07:49:23.63#ibcon#flushed, iclass 11, count 0 2006.259.07:49:23.63#ibcon#about to write, iclass 11, count 0 2006.259.07:49:23.63#ibcon#wrote, iclass 11, count 0 2006.259.07:49:23.63#ibcon#about to read 3, iclass 11, count 0 2006.259.07:49:23.65#ibcon#read 3, iclass 11, count 0 2006.259.07:49:23.65#ibcon#about to read 4, iclass 11, count 0 2006.259.07:49:23.65#ibcon#read 4, iclass 11, count 0 2006.259.07:49:23.65#ibcon#about to read 5, iclass 11, count 0 2006.259.07:49:23.65#ibcon#read 5, iclass 11, count 0 2006.259.07:49:23.65#ibcon#about to read 6, iclass 11, count 0 2006.259.07:49:23.65#ibcon#read 6, iclass 11, count 0 2006.259.07:49:23.65#ibcon#end of sib2, iclass 11, count 0 2006.259.07:49:23.65#ibcon#*mode == 0, iclass 11, count 0 2006.259.07:49:23.65#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.259.07:49:23.65#ibcon#[27=USB\r\n] 2006.259.07:49:23.65#ibcon#*before write, iclass 11, count 0 2006.259.07:49:23.65#ibcon#enter sib2, iclass 11, count 0 2006.259.07:49:23.65#ibcon#flushed, iclass 11, count 0 2006.259.07:49:23.65#ibcon#about to write, iclass 11, count 0 2006.259.07:49:23.65#ibcon#wrote, iclass 11, count 0 2006.259.07:49:23.65#ibcon#about to read 3, iclass 11, count 0 2006.259.07:49:23.68#ibcon#read 3, iclass 11, count 0 2006.259.07:49:23.68#ibcon#about to read 4, iclass 11, count 0 2006.259.07:49:23.68#ibcon#read 4, iclass 11, count 0 2006.259.07:49:23.68#ibcon#about to read 5, iclass 11, count 0 2006.259.07:49:23.68#ibcon#read 5, iclass 11, count 0 2006.259.07:49:23.68#ibcon#about to read 6, iclass 11, count 0 2006.259.07:49:23.68#ibcon#read 6, iclass 11, count 0 2006.259.07:49:23.68#ibcon#end of sib2, iclass 11, count 0 2006.259.07:49:23.68#ibcon#*after write, iclass 11, count 0 2006.259.07:49:23.68#ibcon#*before return 0, iclass 11, count 0 2006.259.07:49:23.68#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.259.07:49:23.68#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.259.07:49:23.68#ibcon#about to clear, iclass 11 cls_cnt 0 2006.259.07:49:23.68#ibcon#cleared, iclass 11 cls_cnt 0 2006.259.07:49:23.68$vc4f8/vabw=wide 2006.259.07:49:23.68#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.259.07:49:23.68#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.259.07:49:23.68#ibcon#ireg 8 cls_cnt 0 2006.259.07:49:23.68#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.259.07:49:23.68#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.259.07:49:23.68#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.259.07:49:23.68#ibcon#enter wrdev, iclass 13, count 0 2006.259.07:49:23.68#ibcon#first serial, iclass 13, count 0 2006.259.07:49:23.68#ibcon#enter sib2, iclass 13, count 0 2006.259.07:49:23.68#ibcon#flushed, iclass 13, count 0 2006.259.07:49:23.68#ibcon#about to write, iclass 13, count 0 2006.259.07:49:23.68#ibcon#wrote, iclass 13, count 0 2006.259.07:49:23.68#ibcon#about to read 3, iclass 13, count 0 2006.259.07:49:23.70#ibcon#read 3, iclass 13, count 0 2006.259.07:49:23.70#ibcon#about to read 4, iclass 13, count 0 2006.259.07:49:23.70#ibcon#read 4, iclass 13, count 0 2006.259.07:49:23.70#ibcon#about to read 5, iclass 13, count 0 2006.259.07:49:23.70#ibcon#read 5, iclass 13, count 0 2006.259.07:49:23.70#ibcon#about to read 6, iclass 13, count 0 2006.259.07:49:23.70#ibcon#read 6, iclass 13, count 0 2006.259.07:49:23.70#ibcon#end of sib2, iclass 13, count 0 2006.259.07:49:23.70#ibcon#*mode == 0, iclass 13, count 0 2006.259.07:49:23.70#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.259.07:49:23.70#ibcon#[25=BW32\r\n] 2006.259.07:49:23.70#ibcon#*before write, iclass 13, count 0 2006.259.07:49:23.70#ibcon#enter sib2, iclass 13, count 0 2006.259.07:49:23.70#ibcon#flushed, iclass 13, count 0 2006.259.07:49:23.70#ibcon#about to write, iclass 13, count 0 2006.259.07:49:23.70#ibcon#wrote, iclass 13, count 0 2006.259.07:49:23.70#ibcon#about to read 3, iclass 13, count 0 2006.259.07:49:23.73#ibcon#read 3, iclass 13, count 0 2006.259.07:49:23.73#ibcon#about to read 4, iclass 13, count 0 2006.259.07:49:23.73#ibcon#read 4, iclass 13, count 0 2006.259.07:49:23.73#ibcon#about to read 5, iclass 13, count 0 2006.259.07:49:23.73#ibcon#read 5, iclass 13, count 0 2006.259.07:49:23.73#ibcon#about to read 6, iclass 13, count 0 2006.259.07:49:23.73#ibcon#read 6, iclass 13, count 0 2006.259.07:49:23.73#ibcon#end of sib2, iclass 13, count 0 2006.259.07:49:23.73#ibcon#*after write, iclass 13, count 0 2006.259.07:49:23.73#ibcon#*before return 0, iclass 13, count 0 2006.259.07:49:23.73#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.259.07:49:23.73#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.259.07:49:23.73#ibcon#about to clear, iclass 13 cls_cnt 0 2006.259.07:49:23.73#ibcon#cleared, iclass 13 cls_cnt 0 2006.259.07:49:23.73$vc4f8/vbbw=wide 2006.259.07:49:23.73#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.259.07:49:23.73#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.259.07:49:23.73#ibcon#ireg 8 cls_cnt 0 2006.259.07:49:23.73#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.259.07:49:23.80#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.259.07:49:23.80#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.259.07:49:23.80#ibcon#enter wrdev, iclass 15, count 0 2006.259.07:49:23.80#ibcon#first serial, iclass 15, count 0 2006.259.07:49:23.80#ibcon#enter sib2, iclass 15, count 0 2006.259.07:49:23.80#ibcon#flushed, iclass 15, count 0 2006.259.07:49:23.80#ibcon#about to write, iclass 15, count 0 2006.259.07:49:23.80#ibcon#wrote, iclass 15, count 0 2006.259.07:49:23.80#ibcon#about to read 3, iclass 15, count 0 2006.259.07:49:23.82#ibcon#read 3, iclass 15, count 0 2006.259.07:49:23.82#ibcon#about to read 4, iclass 15, count 0 2006.259.07:49:23.82#ibcon#read 4, iclass 15, count 0 2006.259.07:49:23.82#ibcon#about to read 5, iclass 15, count 0 2006.259.07:49:23.82#ibcon#read 5, iclass 15, count 0 2006.259.07:49:23.82#ibcon#about to read 6, iclass 15, count 0 2006.259.07:49:23.82#ibcon#read 6, iclass 15, count 0 2006.259.07:49:23.82#ibcon#end of sib2, iclass 15, count 0 2006.259.07:49:23.82#ibcon#*mode == 0, iclass 15, count 0 2006.259.07:49:23.82#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.259.07:49:23.82#ibcon#[27=BW32\r\n] 2006.259.07:49:23.82#ibcon#*before write, iclass 15, count 0 2006.259.07:49:23.82#ibcon#enter sib2, iclass 15, count 0 2006.259.07:49:23.82#ibcon#flushed, iclass 15, count 0 2006.259.07:49:23.82#ibcon#about to write, iclass 15, count 0 2006.259.07:49:23.82#ibcon#wrote, iclass 15, count 0 2006.259.07:49:23.82#ibcon#about to read 3, iclass 15, count 0 2006.259.07:49:23.85#ibcon#read 3, iclass 15, count 0 2006.259.07:49:23.85#ibcon#about to read 4, iclass 15, count 0 2006.259.07:49:23.85#ibcon#read 4, iclass 15, count 0 2006.259.07:49:23.85#ibcon#about to read 5, iclass 15, count 0 2006.259.07:49:23.85#ibcon#read 5, iclass 15, count 0 2006.259.07:49:23.85#ibcon#about to read 6, iclass 15, count 0 2006.259.07:49:23.85#ibcon#read 6, iclass 15, count 0 2006.259.07:49:23.85#ibcon#end of sib2, iclass 15, count 0 2006.259.07:49:23.85#ibcon#*after write, iclass 15, count 0 2006.259.07:49:23.85#ibcon#*before return 0, iclass 15, count 0 2006.259.07:49:23.85#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.259.07:49:23.85#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.259.07:49:23.85#ibcon#about to clear, iclass 15 cls_cnt 0 2006.259.07:49:23.85#ibcon#cleared, iclass 15 cls_cnt 0 2006.259.07:49:23.85$4f8m12a/ifd4f 2006.259.07:49:23.85$ifd4f/lo= 2006.259.07:49:23.85$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.259.07:49:23.85$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.259.07:49:23.85$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.259.07:49:23.85$ifd4f/patch= 2006.259.07:49:23.85$ifd4f/patch=lo1,a1,a2,a3,a4 2006.259.07:49:23.85$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.259.07:49:23.85$ifd4f/patch=lo3,a5,a6,a7,a8 2006.259.07:49:23.85$4f8m12a/"form=m,16.000,1:2 2006.259.07:49:23.85$4f8m12a/"tpicd 2006.259.07:49:23.85$4f8m12a/echo=off 2006.259.07:49:23.85$4f8m12a/xlog=off 2006.259.07:49:23.85:!2006.259.07:49:50 2006.259.07:49:29.13#trakl#Source acquired 2006.259.07:49:29.13#flagr#flagr/antenna,acquired 2006.259.07:49:50.00:preob 2006.259.07:49:51.14/onsource/TRACKING 2006.259.07:49:51.14:!2006.259.07:50:00 2006.259.07:50:00.00:data_valid=on 2006.259.07:50:00.00:midob 2006.259.07:50:00.14/onsource/TRACKING 2006.259.07:50:00.14/wx/22.22,1013.0,86 2006.259.07:50:00.31/cable/+6.4593E-03 2006.259.07:50:01.40/va/01,08,usb,yes,32,33 2006.259.07:50:01.40/va/02,07,usb,yes,31,33 2006.259.07:50:01.40/va/03,08,usb,yes,24,24 2006.259.07:50:01.40/va/04,07,usb,yes,33,35 2006.259.07:50:01.40/va/05,07,usb,yes,36,38 2006.259.07:50:01.40/va/06,06,usb,yes,35,35 2006.259.07:50:01.40/va/07,06,usb,yes,36,36 2006.259.07:50:01.40/va/08,06,usb,yes,38,38 2006.259.07:50:01.63/valo/01,532.99,yes,locked 2006.259.07:50:01.63/valo/02,572.99,yes,locked 2006.259.07:50:01.63/valo/03,672.99,yes,locked 2006.259.07:50:01.63/valo/04,832.99,yes,locked 2006.259.07:50:01.63/valo/05,652.99,yes,locked 2006.259.07:50:01.63/valo/06,772.99,yes,locked 2006.259.07:50:01.63/valo/07,832.99,yes,locked 2006.259.07:50:01.63/valo/08,852.99,yes,locked 2006.259.07:50:02.72/vb/01,04,usb,yes,31,30 2006.259.07:50:02.72/vb/02,05,usb,yes,29,30 2006.259.07:50:02.72/vb/03,04,usb,yes,29,33 2006.259.07:50:02.72/vb/04,05,usb,yes,26,26 2006.259.07:50:02.72/vb/05,04,usb,yes,28,32 2006.259.07:50:02.72/vb/06,04,usb,yes,29,32 2006.259.07:50:02.72/vb/07,04,usb,yes,31,31 2006.259.07:50:02.72/vb/08,04,usb,yes,29,32 2006.259.07:50:02.96/vblo/01,632.99,yes,locked 2006.259.07:50:02.96/vblo/02,640.99,yes,locked 2006.259.07:50:02.96/vblo/03,656.99,yes,locked 2006.259.07:50:02.96/vblo/04,712.99,yes,locked 2006.259.07:50:02.96/vblo/05,744.99,yes,locked 2006.259.07:50:02.96/vblo/06,752.99,yes,locked 2006.259.07:50:02.96/vblo/07,734.99,yes,locked 2006.259.07:50:02.96/vblo/08,744.99,yes,locked 2006.259.07:50:03.11/vabw/8 2006.259.07:50:03.26/vbbw/8 2006.259.07:50:03.35/xfe/off,on,15.0 2006.259.07:50:03.72/ifatt/23,28,28,28 2006.259.07:50:04.07/fmout-gps/S +4.51E-07 2006.259.07:50:04.11:!2006.259.07:51:00 2006.259.07:51:00.00:data_valid=off 2006.259.07:51:00.00:postob 2006.259.07:51:00.08/cable/+6.4598E-03 2006.259.07:51:00.08/wx/22.21,1013.0,86 2006.259.07:51:01.08/fmout-gps/S +4.51E-07 2006.259.07:51:01.08:scan_name=259-0751,k06259,60 2006.259.07:51:01.08:source=1418+546,141946.60,542314.8,2000.0,ccw 2006.259.07:51:01.14#flagr#flagr/antenna,new-source 2006.259.07:51:02.14:checkk5 2006.259.07:51:02.56/chk_autoobs//k5ts1/ autoobs is running! 2006.259.07:51:02.98/chk_autoobs//k5ts2/ autoobs is running! 2006.259.07:51:03.39/chk_autoobs//k5ts3/ autoobs is running! 2006.259.07:51:04.05/chk_autoobs//k5ts4/ autoobs is running! 2006.259.07:51:04.46/chk_obsdata//k5ts1/T2590750??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.259.07:51:04.88/chk_obsdata//k5ts2/T2590750??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.259.07:51:05.27/chk_obsdata//k5ts3/T2590750??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.259.07:51:05.67/chk_obsdata//k5ts4/T2590750??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.259.07:51:06.62/k5log//k5ts1_log_newline 2006.259.07:51:07.41/k5log//k5ts2_log_newline 2006.259.07:51:08.19/k5log//k5ts3_log_newline 2006.259.07:51:09.17/k5log//k5ts4_log_newline 2006.259.07:51:09.23/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.259.07:51:09.23:4f8m12a=1 2006.259.07:51:09.23$4f8m12a/echo=on 2006.259.07:51:09.24$4f8m12a/pcalon 2006.259.07:51:09.24$pcalon/"no phase cal control is implemented here 2006.259.07:51:09.24$4f8m12a/"tpicd=stop 2006.259.07:51:09.24$4f8m12a/vc4f8 2006.259.07:51:09.24$vc4f8/valo=1,532.99 2006.259.07:51:09.24#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.259.07:51:09.24#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.259.07:51:09.24#ibcon#ireg 17 cls_cnt 0 2006.259.07:51:09.24#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.259.07:51:09.24#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.259.07:51:09.24#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.259.07:51:09.24#ibcon#enter wrdev, iclass 26, count 0 2006.259.07:51:09.24#ibcon#first serial, iclass 26, count 0 2006.259.07:51:09.24#ibcon#enter sib2, iclass 26, count 0 2006.259.07:51:09.24#ibcon#flushed, iclass 26, count 0 2006.259.07:51:09.24#ibcon#about to write, iclass 26, count 0 2006.259.07:51:09.24#ibcon#wrote, iclass 26, count 0 2006.259.07:51:09.24#ibcon#about to read 3, iclass 26, count 0 2006.259.07:51:09.26#ibcon#read 3, iclass 26, count 0 2006.259.07:51:09.26#ibcon#about to read 4, iclass 26, count 0 2006.259.07:51:09.26#ibcon#read 4, iclass 26, count 0 2006.259.07:51:09.26#ibcon#about to read 5, iclass 26, count 0 2006.259.07:51:09.26#ibcon#read 5, iclass 26, count 0 2006.259.07:51:09.26#ibcon#about to read 6, iclass 26, count 0 2006.259.07:51:09.26#ibcon#read 6, iclass 26, count 0 2006.259.07:51:09.26#ibcon#end of sib2, iclass 26, count 0 2006.259.07:51:09.26#ibcon#*mode == 0, iclass 26, count 0 2006.259.07:51:09.26#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.259.07:51:09.26#ibcon#[26=FRQ=01,532.99\r\n] 2006.259.07:51:09.26#ibcon#*before write, iclass 26, count 0 2006.259.07:51:09.26#ibcon#enter sib2, iclass 26, count 0 2006.259.07:51:09.26#ibcon#flushed, iclass 26, count 0 2006.259.07:51:09.26#ibcon#about to write, iclass 26, count 0 2006.259.07:51:09.26#ibcon#wrote, iclass 26, count 0 2006.259.07:51:09.26#ibcon#about to read 3, iclass 26, count 0 2006.259.07:51:09.31#ibcon#read 3, iclass 26, count 0 2006.259.07:51:09.31#ibcon#about to read 4, iclass 26, count 0 2006.259.07:51:09.31#ibcon#read 4, iclass 26, count 0 2006.259.07:51:09.31#ibcon#about to read 5, iclass 26, count 0 2006.259.07:51:09.31#ibcon#read 5, iclass 26, count 0 2006.259.07:51:09.31#ibcon#about to read 6, iclass 26, count 0 2006.259.07:51:09.31#ibcon#read 6, iclass 26, count 0 2006.259.07:51:09.31#ibcon#end of sib2, iclass 26, count 0 2006.259.07:51:09.31#ibcon#*after write, iclass 26, count 0 2006.259.07:51:09.31#ibcon#*before return 0, iclass 26, count 0 2006.259.07:51:09.31#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.259.07:51:09.31#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.259.07:51:09.31#ibcon#about to clear, iclass 26 cls_cnt 0 2006.259.07:51:09.31#ibcon#cleared, iclass 26 cls_cnt 0 2006.259.07:51:09.31$vc4f8/va=1,8 2006.259.07:51:09.31#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.259.07:51:09.31#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.259.07:51:09.31#ibcon#ireg 11 cls_cnt 2 2006.259.07:51:09.31#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.259.07:51:09.31#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.259.07:51:09.31#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.259.07:51:09.31#ibcon#enter wrdev, iclass 28, count 2 2006.259.07:51:09.31#ibcon#first serial, iclass 28, count 2 2006.259.07:51:09.31#ibcon#enter sib2, iclass 28, count 2 2006.259.07:51:09.31#ibcon#flushed, iclass 28, count 2 2006.259.07:51:09.31#ibcon#about to write, iclass 28, count 2 2006.259.07:51:09.31#ibcon#wrote, iclass 28, count 2 2006.259.07:51:09.31#ibcon#about to read 3, iclass 28, count 2 2006.259.07:51:09.33#ibcon#read 3, iclass 28, count 2 2006.259.07:51:09.33#ibcon#about to read 4, iclass 28, count 2 2006.259.07:51:09.33#ibcon#read 4, iclass 28, count 2 2006.259.07:51:09.33#ibcon#about to read 5, iclass 28, count 2 2006.259.07:51:09.33#ibcon#read 5, iclass 28, count 2 2006.259.07:51:09.33#ibcon#about to read 6, iclass 28, count 2 2006.259.07:51:09.33#ibcon#read 6, iclass 28, count 2 2006.259.07:51:09.33#ibcon#end of sib2, iclass 28, count 2 2006.259.07:51:09.33#ibcon#*mode == 0, iclass 28, count 2 2006.259.07:51:09.33#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.259.07:51:09.33#ibcon#[25=AT01-08\r\n] 2006.259.07:51:09.33#ibcon#*before write, iclass 28, count 2 2006.259.07:51:09.33#ibcon#enter sib2, iclass 28, count 2 2006.259.07:51:09.33#ibcon#flushed, iclass 28, count 2 2006.259.07:51:09.33#ibcon#about to write, iclass 28, count 2 2006.259.07:51:09.33#ibcon#wrote, iclass 28, count 2 2006.259.07:51:09.33#ibcon#about to read 3, iclass 28, count 2 2006.259.07:51:09.36#ibcon#read 3, iclass 28, count 2 2006.259.07:51:09.36#ibcon#about to read 4, iclass 28, count 2 2006.259.07:51:09.36#ibcon#read 4, iclass 28, count 2 2006.259.07:51:09.36#ibcon#about to read 5, iclass 28, count 2 2006.259.07:51:09.36#ibcon#read 5, iclass 28, count 2 2006.259.07:51:09.36#ibcon#about to read 6, iclass 28, count 2 2006.259.07:51:09.36#ibcon#read 6, iclass 28, count 2 2006.259.07:51:09.36#ibcon#end of sib2, iclass 28, count 2 2006.259.07:51:09.36#ibcon#*after write, iclass 28, count 2 2006.259.07:51:09.36#ibcon#*before return 0, iclass 28, count 2 2006.259.07:51:09.36#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.259.07:51:09.36#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.259.07:51:09.36#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.259.07:51:09.36#ibcon#ireg 7 cls_cnt 0 2006.259.07:51:09.36#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.259.07:51:09.48#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.259.07:51:09.48#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.259.07:51:09.48#ibcon#enter wrdev, iclass 28, count 0 2006.259.07:51:09.48#ibcon#first serial, iclass 28, count 0 2006.259.07:51:09.48#ibcon#enter sib2, iclass 28, count 0 2006.259.07:51:09.48#ibcon#flushed, iclass 28, count 0 2006.259.07:51:09.48#ibcon#about to write, iclass 28, count 0 2006.259.07:51:09.48#ibcon#wrote, iclass 28, count 0 2006.259.07:51:09.48#ibcon#about to read 3, iclass 28, count 0 2006.259.07:51:09.50#ibcon#read 3, iclass 28, count 0 2006.259.07:51:09.50#ibcon#about to read 4, iclass 28, count 0 2006.259.07:51:09.50#ibcon#read 4, iclass 28, count 0 2006.259.07:51:09.50#ibcon#about to read 5, iclass 28, count 0 2006.259.07:51:09.50#ibcon#read 5, iclass 28, count 0 2006.259.07:51:09.50#ibcon#about to read 6, iclass 28, count 0 2006.259.07:51:09.50#ibcon#read 6, iclass 28, count 0 2006.259.07:51:09.50#ibcon#end of sib2, iclass 28, count 0 2006.259.07:51:09.50#ibcon#*mode == 0, iclass 28, count 0 2006.259.07:51:09.50#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.259.07:51:09.50#ibcon#[25=USB\r\n] 2006.259.07:51:09.50#ibcon#*before write, iclass 28, count 0 2006.259.07:51:09.50#ibcon#enter sib2, iclass 28, count 0 2006.259.07:51:09.50#ibcon#flushed, iclass 28, count 0 2006.259.07:51:09.50#ibcon#about to write, iclass 28, count 0 2006.259.07:51:09.50#ibcon#wrote, iclass 28, count 0 2006.259.07:51:09.50#ibcon#about to read 3, iclass 28, count 0 2006.259.07:51:09.53#ibcon#read 3, iclass 28, count 0 2006.259.07:51:09.53#ibcon#about to read 4, iclass 28, count 0 2006.259.07:51:09.53#ibcon#read 4, iclass 28, count 0 2006.259.07:51:09.53#ibcon#about to read 5, iclass 28, count 0 2006.259.07:51:09.53#ibcon#read 5, iclass 28, count 0 2006.259.07:51:09.53#ibcon#about to read 6, iclass 28, count 0 2006.259.07:51:09.53#ibcon#read 6, iclass 28, count 0 2006.259.07:51:09.53#ibcon#end of sib2, iclass 28, count 0 2006.259.07:51:09.53#ibcon#*after write, iclass 28, count 0 2006.259.07:51:09.53#ibcon#*before return 0, iclass 28, count 0 2006.259.07:51:09.53#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.259.07:51:09.53#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.259.07:51:09.53#ibcon#about to clear, iclass 28 cls_cnt 0 2006.259.07:51:09.53#ibcon#cleared, iclass 28 cls_cnt 0 2006.259.07:51:09.53$vc4f8/valo=2,572.99 2006.259.07:51:09.53#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.259.07:51:09.53#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.259.07:51:09.53#ibcon#ireg 17 cls_cnt 0 2006.259.07:51:09.53#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.259.07:51:09.53#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.259.07:51:09.53#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.259.07:51:09.53#ibcon#enter wrdev, iclass 30, count 0 2006.259.07:51:09.53#ibcon#first serial, iclass 30, count 0 2006.259.07:51:09.53#ibcon#enter sib2, iclass 30, count 0 2006.259.07:51:09.53#ibcon#flushed, iclass 30, count 0 2006.259.07:51:09.53#ibcon#about to write, iclass 30, count 0 2006.259.07:51:09.53#ibcon#wrote, iclass 30, count 0 2006.259.07:51:09.53#ibcon#about to read 3, iclass 30, count 0 2006.259.07:51:09.55#ibcon#read 3, iclass 30, count 0 2006.259.07:51:09.55#ibcon#about to read 4, iclass 30, count 0 2006.259.07:51:09.55#ibcon#read 4, iclass 30, count 0 2006.259.07:51:09.55#ibcon#about to read 5, iclass 30, count 0 2006.259.07:51:09.55#ibcon#read 5, iclass 30, count 0 2006.259.07:51:09.55#ibcon#about to read 6, iclass 30, count 0 2006.259.07:51:09.55#ibcon#read 6, iclass 30, count 0 2006.259.07:51:09.55#ibcon#end of sib2, iclass 30, count 0 2006.259.07:51:09.55#ibcon#*mode == 0, iclass 30, count 0 2006.259.07:51:09.55#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.259.07:51:09.55#ibcon#[26=FRQ=02,572.99\r\n] 2006.259.07:51:09.55#ibcon#*before write, iclass 30, count 0 2006.259.07:51:09.55#ibcon#enter sib2, iclass 30, count 0 2006.259.07:51:09.55#ibcon#flushed, iclass 30, count 0 2006.259.07:51:09.55#ibcon#about to write, iclass 30, count 0 2006.259.07:51:09.55#ibcon#wrote, iclass 30, count 0 2006.259.07:51:09.55#ibcon#about to read 3, iclass 30, count 0 2006.259.07:51:09.59#ibcon#read 3, iclass 30, count 0 2006.259.07:51:09.59#ibcon#about to read 4, iclass 30, count 0 2006.259.07:51:09.59#ibcon#read 4, iclass 30, count 0 2006.259.07:51:09.59#ibcon#about to read 5, iclass 30, count 0 2006.259.07:51:09.59#ibcon#read 5, iclass 30, count 0 2006.259.07:51:09.59#ibcon#about to read 6, iclass 30, count 0 2006.259.07:51:09.59#ibcon#read 6, iclass 30, count 0 2006.259.07:51:09.59#ibcon#end of sib2, iclass 30, count 0 2006.259.07:51:09.59#ibcon#*after write, iclass 30, count 0 2006.259.07:51:09.59#ibcon#*before return 0, iclass 30, count 0 2006.259.07:51:09.59#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.259.07:51:09.59#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.259.07:51:09.59#ibcon#about to clear, iclass 30 cls_cnt 0 2006.259.07:51:09.59#ibcon#cleared, iclass 30 cls_cnt 0 2006.259.07:51:09.59$vc4f8/va=2,7 2006.259.07:51:09.59#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.259.07:51:09.59#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.259.07:51:09.59#ibcon#ireg 11 cls_cnt 2 2006.259.07:51:09.59#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.259.07:51:09.65#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.259.07:51:09.65#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.259.07:51:09.65#ibcon#enter wrdev, iclass 32, count 2 2006.259.07:51:09.65#ibcon#first serial, iclass 32, count 2 2006.259.07:51:09.65#ibcon#enter sib2, iclass 32, count 2 2006.259.07:51:09.65#ibcon#flushed, iclass 32, count 2 2006.259.07:51:09.65#ibcon#about to write, iclass 32, count 2 2006.259.07:51:09.65#ibcon#wrote, iclass 32, count 2 2006.259.07:51:09.65#ibcon#about to read 3, iclass 32, count 2 2006.259.07:51:09.67#ibcon#read 3, iclass 32, count 2 2006.259.07:51:09.67#ibcon#about to read 4, iclass 32, count 2 2006.259.07:51:09.67#ibcon#read 4, iclass 32, count 2 2006.259.07:51:09.67#ibcon#about to read 5, iclass 32, count 2 2006.259.07:51:09.67#ibcon#read 5, iclass 32, count 2 2006.259.07:51:09.67#ibcon#about to read 6, iclass 32, count 2 2006.259.07:51:09.67#ibcon#read 6, iclass 32, count 2 2006.259.07:51:09.67#ibcon#end of sib2, iclass 32, count 2 2006.259.07:51:09.67#ibcon#*mode == 0, iclass 32, count 2 2006.259.07:51:09.67#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.259.07:51:09.67#ibcon#[25=AT02-07\r\n] 2006.259.07:51:09.67#ibcon#*before write, iclass 32, count 2 2006.259.07:51:09.67#ibcon#enter sib2, iclass 32, count 2 2006.259.07:51:09.67#ibcon#flushed, iclass 32, count 2 2006.259.07:51:09.67#ibcon#about to write, iclass 32, count 2 2006.259.07:51:09.67#ibcon#wrote, iclass 32, count 2 2006.259.07:51:09.67#ibcon#about to read 3, iclass 32, count 2 2006.259.07:51:09.71#ibcon#read 3, iclass 32, count 2 2006.259.07:51:09.71#ibcon#about to read 4, iclass 32, count 2 2006.259.07:51:09.71#ibcon#read 4, iclass 32, count 2 2006.259.07:51:09.71#ibcon#about to read 5, iclass 32, count 2 2006.259.07:51:09.71#ibcon#read 5, iclass 32, count 2 2006.259.07:51:09.71#ibcon#about to read 6, iclass 32, count 2 2006.259.07:51:09.71#ibcon#read 6, iclass 32, count 2 2006.259.07:51:09.71#ibcon#end of sib2, iclass 32, count 2 2006.259.07:51:09.71#ibcon#*after write, iclass 32, count 2 2006.259.07:51:09.71#ibcon#*before return 0, iclass 32, count 2 2006.259.07:51:09.71#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.259.07:51:09.71#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.259.07:51:09.71#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.259.07:51:09.71#ibcon#ireg 7 cls_cnt 0 2006.259.07:51:09.71#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.259.07:51:09.83#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.259.07:51:09.83#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.259.07:51:09.83#ibcon#enter wrdev, iclass 32, count 0 2006.259.07:51:09.83#ibcon#first serial, iclass 32, count 0 2006.259.07:51:09.83#ibcon#enter sib2, iclass 32, count 0 2006.259.07:51:09.83#ibcon#flushed, iclass 32, count 0 2006.259.07:51:09.83#ibcon#about to write, iclass 32, count 0 2006.259.07:51:09.83#ibcon#wrote, iclass 32, count 0 2006.259.07:51:09.83#ibcon#about to read 3, iclass 32, count 0 2006.259.07:51:09.85#ibcon#read 3, iclass 32, count 0 2006.259.07:51:09.85#ibcon#about to read 4, iclass 32, count 0 2006.259.07:51:09.85#ibcon#read 4, iclass 32, count 0 2006.259.07:51:09.85#ibcon#about to read 5, iclass 32, count 0 2006.259.07:51:09.85#ibcon#read 5, iclass 32, count 0 2006.259.07:51:09.85#ibcon#about to read 6, iclass 32, count 0 2006.259.07:51:09.85#ibcon#read 6, iclass 32, count 0 2006.259.07:51:09.85#ibcon#end of sib2, iclass 32, count 0 2006.259.07:51:09.85#ibcon#*mode == 0, iclass 32, count 0 2006.259.07:51:09.85#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.259.07:51:09.85#ibcon#[25=USB\r\n] 2006.259.07:51:09.85#ibcon#*before write, iclass 32, count 0 2006.259.07:51:09.85#ibcon#enter sib2, iclass 32, count 0 2006.259.07:51:09.85#ibcon#flushed, iclass 32, count 0 2006.259.07:51:09.85#ibcon#about to write, iclass 32, count 0 2006.259.07:51:09.85#ibcon#wrote, iclass 32, count 0 2006.259.07:51:09.85#ibcon#about to read 3, iclass 32, count 0 2006.259.07:51:09.88#ibcon#read 3, iclass 32, count 0 2006.259.07:51:09.88#ibcon#about to read 4, iclass 32, count 0 2006.259.07:51:09.88#ibcon#read 4, iclass 32, count 0 2006.259.07:51:09.88#ibcon#about to read 5, iclass 32, count 0 2006.259.07:51:09.88#ibcon#read 5, iclass 32, count 0 2006.259.07:51:09.88#ibcon#about to read 6, iclass 32, count 0 2006.259.07:51:09.88#ibcon#read 6, iclass 32, count 0 2006.259.07:51:09.88#ibcon#end of sib2, iclass 32, count 0 2006.259.07:51:09.88#ibcon#*after write, iclass 32, count 0 2006.259.07:51:09.88#ibcon#*before return 0, iclass 32, count 0 2006.259.07:51:09.88#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.259.07:51:09.88#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.259.07:51:09.88#ibcon#about to clear, iclass 32 cls_cnt 0 2006.259.07:51:09.88#ibcon#cleared, iclass 32 cls_cnt 0 2006.259.07:51:09.88$vc4f8/valo=3,672.99 2006.259.07:51:09.88#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.259.07:51:09.88#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.259.07:51:09.88#ibcon#ireg 17 cls_cnt 0 2006.259.07:51:09.88#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.259.07:51:09.88#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.259.07:51:09.88#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.259.07:51:09.88#ibcon#enter wrdev, iclass 34, count 0 2006.259.07:51:09.88#ibcon#first serial, iclass 34, count 0 2006.259.07:51:09.88#ibcon#enter sib2, iclass 34, count 0 2006.259.07:51:09.88#ibcon#flushed, iclass 34, count 0 2006.259.07:51:09.88#ibcon#about to write, iclass 34, count 0 2006.259.07:51:09.88#ibcon#wrote, iclass 34, count 0 2006.259.07:51:09.88#ibcon#about to read 3, iclass 34, count 0 2006.259.07:51:09.90#ibcon#read 3, iclass 34, count 0 2006.259.07:51:09.90#ibcon#about to read 4, iclass 34, count 0 2006.259.07:51:09.90#ibcon#read 4, iclass 34, count 0 2006.259.07:51:09.90#ibcon#about to read 5, iclass 34, count 0 2006.259.07:51:09.90#ibcon#read 5, iclass 34, count 0 2006.259.07:51:09.90#ibcon#about to read 6, iclass 34, count 0 2006.259.07:51:09.90#ibcon#read 6, iclass 34, count 0 2006.259.07:51:09.90#ibcon#end of sib2, iclass 34, count 0 2006.259.07:51:09.90#ibcon#*mode == 0, iclass 34, count 0 2006.259.07:51:09.90#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.259.07:51:09.90#ibcon#[26=FRQ=03,672.99\r\n] 2006.259.07:51:09.90#ibcon#*before write, iclass 34, count 0 2006.259.07:51:09.90#ibcon#enter sib2, iclass 34, count 0 2006.259.07:51:09.90#ibcon#flushed, iclass 34, count 0 2006.259.07:51:09.90#ibcon#about to write, iclass 34, count 0 2006.259.07:51:09.90#ibcon#wrote, iclass 34, count 0 2006.259.07:51:09.90#ibcon#about to read 3, iclass 34, count 0 2006.259.07:51:09.94#ibcon#read 3, iclass 34, count 0 2006.259.07:51:09.94#ibcon#about to read 4, iclass 34, count 0 2006.259.07:51:09.94#ibcon#read 4, iclass 34, count 0 2006.259.07:51:09.94#ibcon#about to read 5, iclass 34, count 0 2006.259.07:51:09.94#ibcon#read 5, iclass 34, count 0 2006.259.07:51:09.94#ibcon#about to read 6, iclass 34, count 0 2006.259.07:51:09.94#ibcon#read 6, iclass 34, count 0 2006.259.07:51:09.94#ibcon#end of sib2, iclass 34, count 0 2006.259.07:51:09.94#ibcon#*after write, iclass 34, count 0 2006.259.07:51:09.94#ibcon#*before return 0, iclass 34, count 0 2006.259.07:51:09.94#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.259.07:51:09.94#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.259.07:51:09.94#ibcon#about to clear, iclass 34 cls_cnt 0 2006.259.07:51:09.94#ibcon#cleared, iclass 34 cls_cnt 0 2006.259.07:51:09.94$vc4f8/va=3,8 2006.259.07:51:09.94#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.259.07:51:09.94#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.259.07:51:09.94#ibcon#ireg 11 cls_cnt 2 2006.259.07:51:09.94#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.259.07:51:10.00#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.259.07:51:10.00#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.259.07:51:10.00#ibcon#enter wrdev, iclass 36, count 2 2006.259.07:51:10.00#ibcon#first serial, iclass 36, count 2 2006.259.07:51:10.00#ibcon#enter sib2, iclass 36, count 2 2006.259.07:51:10.00#ibcon#flushed, iclass 36, count 2 2006.259.07:51:10.00#ibcon#about to write, iclass 36, count 2 2006.259.07:51:10.00#ibcon#wrote, iclass 36, count 2 2006.259.07:51:10.00#ibcon#about to read 3, iclass 36, count 2 2006.259.07:51:10.02#ibcon#read 3, iclass 36, count 2 2006.259.07:51:10.02#ibcon#about to read 4, iclass 36, count 2 2006.259.07:51:10.02#ibcon#read 4, iclass 36, count 2 2006.259.07:51:10.02#ibcon#about to read 5, iclass 36, count 2 2006.259.07:51:10.02#ibcon#read 5, iclass 36, count 2 2006.259.07:51:10.02#ibcon#about to read 6, iclass 36, count 2 2006.259.07:51:10.02#ibcon#read 6, iclass 36, count 2 2006.259.07:51:10.02#ibcon#end of sib2, iclass 36, count 2 2006.259.07:51:10.02#ibcon#*mode == 0, iclass 36, count 2 2006.259.07:51:10.02#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.259.07:51:10.02#ibcon#[25=AT03-08\r\n] 2006.259.07:51:10.02#ibcon#*before write, iclass 36, count 2 2006.259.07:51:10.02#ibcon#enter sib2, iclass 36, count 2 2006.259.07:51:10.02#ibcon#flushed, iclass 36, count 2 2006.259.07:51:10.02#ibcon#about to write, iclass 36, count 2 2006.259.07:51:10.02#ibcon#wrote, iclass 36, count 2 2006.259.07:51:10.02#ibcon#about to read 3, iclass 36, count 2 2006.259.07:51:10.05#ibcon#read 3, iclass 36, count 2 2006.259.07:51:10.05#ibcon#about to read 4, iclass 36, count 2 2006.259.07:51:10.05#ibcon#read 4, iclass 36, count 2 2006.259.07:51:10.05#ibcon#about to read 5, iclass 36, count 2 2006.259.07:51:10.05#ibcon#read 5, iclass 36, count 2 2006.259.07:51:10.05#ibcon#about to read 6, iclass 36, count 2 2006.259.07:51:10.05#ibcon#read 6, iclass 36, count 2 2006.259.07:51:10.05#ibcon#end of sib2, iclass 36, count 2 2006.259.07:51:10.05#ibcon#*after write, iclass 36, count 2 2006.259.07:51:10.05#ibcon#*before return 0, iclass 36, count 2 2006.259.07:51:10.05#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.259.07:51:10.05#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.259.07:51:10.05#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.259.07:51:10.05#ibcon#ireg 7 cls_cnt 0 2006.259.07:51:10.05#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.259.07:51:10.17#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.259.07:51:10.17#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.259.07:51:10.17#ibcon#enter wrdev, iclass 36, count 0 2006.259.07:51:10.17#ibcon#first serial, iclass 36, count 0 2006.259.07:51:10.17#ibcon#enter sib2, iclass 36, count 0 2006.259.07:51:10.17#ibcon#flushed, iclass 36, count 0 2006.259.07:51:10.17#ibcon#about to write, iclass 36, count 0 2006.259.07:51:10.17#ibcon#wrote, iclass 36, count 0 2006.259.07:51:10.17#ibcon#about to read 3, iclass 36, count 0 2006.259.07:51:10.19#ibcon#read 3, iclass 36, count 0 2006.259.07:51:10.19#ibcon#about to read 4, iclass 36, count 0 2006.259.07:51:10.19#ibcon#read 4, iclass 36, count 0 2006.259.07:51:10.19#ibcon#about to read 5, iclass 36, count 0 2006.259.07:51:10.19#ibcon#read 5, iclass 36, count 0 2006.259.07:51:10.19#ibcon#about to read 6, iclass 36, count 0 2006.259.07:51:10.19#ibcon#read 6, iclass 36, count 0 2006.259.07:51:10.19#ibcon#end of sib2, iclass 36, count 0 2006.259.07:51:10.19#ibcon#*mode == 0, iclass 36, count 0 2006.259.07:51:10.19#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.259.07:51:10.19#ibcon#[25=USB\r\n] 2006.259.07:51:10.19#ibcon#*before write, iclass 36, count 0 2006.259.07:51:10.19#ibcon#enter sib2, iclass 36, count 0 2006.259.07:51:10.19#ibcon#flushed, iclass 36, count 0 2006.259.07:51:10.19#ibcon#about to write, iclass 36, count 0 2006.259.07:51:10.19#ibcon#wrote, iclass 36, count 0 2006.259.07:51:10.19#ibcon#about to read 3, iclass 36, count 0 2006.259.07:51:10.22#ibcon#read 3, iclass 36, count 0 2006.259.07:51:10.22#ibcon#about to read 4, iclass 36, count 0 2006.259.07:51:10.22#ibcon#read 4, iclass 36, count 0 2006.259.07:51:10.22#ibcon#about to read 5, iclass 36, count 0 2006.259.07:51:10.22#ibcon#read 5, iclass 36, count 0 2006.259.07:51:10.22#ibcon#about to read 6, iclass 36, count 0 2006.259.07:51:10.22#ibcon#read 6, iclass 36, count 0 2006.259.07:51:10.22#ibcon#end of sib2, iclass 36, count 0 2006.259.07:51:10.22#ibcon#*after write, iclass 36, count 0 2006.259.07:51:10.22#ibcon#*before return 0, iclass 36, count 0 2006.259.07:51:10.22#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.259.07:51:10.22#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.259.07:51:10.22#ibcon#about to clear, iclass 36 cls_cnt 0 2006.259.07:51:10.22#ibcon#cleared, iclass 36 cls_cnt 0 2006.259.07:51:10.22$vc4f8/valo=4,832.99 2006.259.07:51:10.22#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.259.07:51:10.22#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.259.07:51:10.22#ibcon#ireg 17 cls_cnt 0 2006.259.07:51:10.22#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.259.07:51:10.22#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.259.07:51:10.22#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.259.07:51:10.22#ibcon#enter wrdev, iclass 38, count 0 2006.259.07:51:10.22#ibcon#first serial, iclass 38, count 0 2006.259.07:51:10.22#ibcon#enter sib2, iclass 38, count 0 2006.259.07:51:10.22#ibcon#flushed, iclass 38, count 0 2006.259.07:51:10.22#ibcon#about to write, iclass 38, count 0 2006.259.07:51:10.22#ibcon#wrote, iclass 38, count 0 2006.259.07:51:10.22#ibcon#about to read 3, iclass 38, count 0 2006.259.07:51:10.24#ibcon#read 3, iclass 38, count 0 2006.259.07:51:10.24#ibcon#about to read 4, iclass 38, count 0 2006.259.07:51:10.24#ibcon#read 4, iclass 38, count 0 2006.259.07:51:10.24#ibcon#about to read 5, iclass 38, count 0 2006.259.07:51:10.24#ibcon#read 5, iclass 38, count 0 2006.259.07:51:10.24#ibcon#about to read 6, iclass 38, count 0 2006.259.07:51:10.24#ibcon#read 6, iclass 38, count 0 2006.259.07:51:10.24#ibcon#end of sib2, iclass 38, count 0 2006.259.07:51:10.24#ibcon#*mode == 0, iclass 38, count 0 2006.259.07:51:10.24#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.259.07:51:10.24#ibcon#[26=FRQ=04,832.99\r\n] 2006.259.07:51:10.24#ibcon#*before write, iclass 38, count 0 2006.259.07:51:10.24#ibcon#enter sib2, iclass 38, count 0 2006.259.07:51:10.24#ibcon#flushed, iclass 38, count 0 2006.259.07:51:10.24#ibcon#about to write, iclass 38, count 0 2006.259.07:51:10.24#ibcon#wrote, iclass 38, count 0 2006.259.07:51:10.24#ibcon#about to read 3, iclass 38, count 0 2006.259.07:51:10.28#ibcon#read 3, iclass 38, count 0 2006.259.07:51:10.28#ibcon#about to read 4, iclass 38, count 0 2006.259.07:51:10.28#ibcon#read 4, iclass 38, count 0 2006.259.07:51:10.28#ibcon#about to read 5, iclass 38, count 0 2006.259.07:51:10.28#ibcon#read 5, iclass 38, count 0 2006.259.07:51:10.28#ibcon#about to read 6, iclass 38, count 0 2006.259.07:51:10.28#ibcon#read 6, iclass 38, count 0 2006.259.07:51:10.28#ibcon#end of sib2, iclass 38, count 0 2006.259.07:51:10.28#ibcon#*after write, iclass 38, count 0 2006.259.07:51:10.28#ibcon#*before return 0, iclass 38, count 0 2006.259.07:51:10.28#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.259.07:51:10.28#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.259.07:51:10.28#ibcon#about to clear, iclass 38 cls_cnt 0 2006.259.07:51:10.28#ibcon#cleared, iclass 38 cls_cnt 0 2006.259.07:51:10.28$vc4f8/va=4,7 2006.259.07:51:10.28#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.259.07:51:10.28#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.259.07:51:10.28#ibcon#ireg 11 cls_cnt 2 2006.259.07:51:10.28#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.259.07:51:10.34#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.259.07:51:10.34#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.259.07:51:10.34#ibcon#enter wrdev, iclass 40, count 2 2006.259.07:51:10.34#ibcon#first serial, iclass 40, count 2 2006.259.07:51:10.34#ibcon#enter sib2, iclass 40, count 2 2006.259.07:51:10.34#ibcon#flushed, iclass 40, count 2 2006.259.07:51:10.34#ibcon#about to write, iclass 40, count 2 2006.259.07:51:10.34#ibcon#wrote, iclass 40, count 2 2006.259.07:51:10.34#ibcon#about to read 3, iclass 40, count 2 2006.259.07:51:10.36#ibcon#read 3, iclass 40, count 2 2006.259.07:51:10.36#ibcon#about to read 4, iclass 40, count 2 2006.259.07:51:10.36#ibcon#read 4, iclass 40, count 2 2006.259.07:51:10.36#ibcon#about to read 5, iclass 40, count 2 2006.259.07:51:10.36#ibcon#read 5, iclass 40, count 2 2006.259.07:51:10.36#ibcon#about to read 6, iclass 40, count 2 2006.259.07:51:10.36#ibcon#read 6, iclass 40, count 2 2006.259.07:51:10.36#ibcon#end of sib2, iclass 40, count 2 2006.259.07:51:10.36#ibcon#*mode == 0, iclass 40, count 2 2006.259.07:51:10.36#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.259.07:51:10.36#ibcon#[25=AT04-07\r\n] 2006.259.07:51:10.36#ibcon#*before write, iclass 40, count 2 2006.259.07:51:10.36#ibcon#enter sib2, iclass 40, count 2 2006.259.07:51:10.36#ibcon#flushed, iclass 40, count 2 2006.259.07:51:10.36#ibcon#about to write, iclass 40, count 2 2006.259.07:51:10.36#ibcon#wrote, iclass 40, count 2 2006.259.07:51:10.36#ibcon#about to read 3, iclass 40, count 2 2006.259.07:51:10.39#ibcon#read 3, iclass 40, count 2 2006.259.07:51:10.39#ibcon#about to read 4, iclass 40, count 2 2006.259.07:51:10.39#ibcon#read 4, iclass 40, count 2 2006.259.07:51:10.39#ibcon#about to read 5, iclass 40, count 2 2006.259.07:51:10.39#ibcon#read 5, iclass 40, count 2 2006.259.07:51:10.39#ibcon#about to read 6, iclass 40, count 2 2006.259.07:51:10.39#ibcon#read 6, iclass 40, count 2 2006.259.07:51:10.39#ibcon#end of sib2, iclass 40, count 2 2006.259.07:51:10.39#ibcon#*after write, iclass 40, count 2 2006.259.07:51:10.39#ibcon#*before return 0, iclass 40, count 2 2006.259.07:51:10.39#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.259.07:51:10.39#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.259.07:51:10.39#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.259.07:51:10.39#ibcon#ireg 7 cls_cnt 0 2006.259.07:51:10.39#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.259.07:51:10.51#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.259.07:51:10.51#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.259.07:51:10.51#ibcon#enter wrdev, iclass 40, count 0 2006.259.07:51:10.51#ibcon#first serial, iclass 40, count 0 2006.259.07:51:10.51#ibcon#enter sib2, iclass 40, count 0 2006.259.07:51:10.51#ibcon#flushed, iclass 40, count 0 2006.259.07:51:10.51#ibcon#about to write, iclass 40, count 0 2006.259.07:51:10.51#ibcon#wrote, iclass 40, count 0 2006.259.07:51:10.51#ibcon#about to read 3, iclass 40, count 0 2006.259.07:51:10.53#ibcon#read 3, iclass 40, count 0 2006.259.07:51:10.53#ibcon#about to read 4, iclass 40, count 0 2006.259.07:51:10.53#ibcon#read 4, iclass 40, count 0 2006.259.07:51:10.53#ibcon#about to read 5, iclass 40, count 0 2006.259.07:51:10.53#ibcon#read 5, iclass 40, count 0 2006.259.07:51:10.53#ibcon#about to read 6, iclass 40, count 0 2006.259.07:51:10.53#ibcon#read 6, iclass 40, count 0 2006.259.07:51:10.53#ibcon#end of sib2, iclass 40, count 0 2006.259.07:51:10.53#ibcon#*mode == 0, iclass 40, count 0 2006.259.07:51:10.53#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.259.07:51:10.53#ibcon#[25=USB\r\n] 2006.259.07:51:10.53#ibcon#*before write, iclass 40, count 0 2006.259.07:51:10.53#ibcon#enter sib2, iclass 40, count 0 2006.259.07:51:10.53#ibcon#flushed, iclass 40, count 0 2006.259.07:51:10.53#ibcon#about to write, iclass 40, count 0 2006.259.07:51:10.53#ibcon#wrote, iclass 40, count 0 2006.259.07:51:10.53#ibcon#about to read 3, iclass 40, count 0 2006.259.07:51:10.56#ibcon#read 3, iclass 40, count 0 2006.259.07:51:10.56#ibcon#about to read 4, iclass 40, count 0 2006.259.07:51:10.56#ibcon#read 4, iclass 40, count 0 2006.259.07:51:10.56#ibcon#about to read 5, iclass 40, count 0 2006.259.07:51:10.56#ibcon#read 5, iclass 40, count 0 2006.259.07:51:10.56#ibcon#about to read 6, iclass 40, count 0 2006.259.07:51:10.56#ibcon#read 6, iclass 40, count 0 2006.259.07:51:10.56#ibcon#end of sib2, iclass 40, count 0 2006.259.07:51:10.56#ibcon#*after write, iclass 40, count 0 2006.259.07:51:10.56#ibcon#*before return 0, iclass 40, count 0 2006.259.07:51:10.56#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.259.07:51:10.56#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.259.07:51:10.56#ibcon#about to clear, iclass 40 cls_cnt 0 2006.259.07:51:10.56#ibcon#cleared, iclass 40 cls_cnt 0 2006.259.07:51:10.56$vc4f8/valo=5,652.99 2006.259.07:51:10.56#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.259.07:51:10.56#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.259.07:51:10.56#ibcon#ireg 17 cls_cnt 0 2006.259.07:51:10.56#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.259.07:51:10.56#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.259.07:51:10.56#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.259.07:51:10.56#ibcon#enter wrdev, iclass 4, count 0 2006.259.07:51:10.56#ibcon#first serial, iclass 4, count 0 2006.259.07:51:10.56#ibcon#enter sib2, iclass 4, count 0 2006.259.07:51:10.56#ibcon#flushed, iclass 4, count 0 2006.259.07:51:10.56#ibcon#about to write, iclass 4, count 0 2006.259.07:51:10.56#ibcon#wrote, iclass 4, count 0 2006.259.07:51:10.56#ibcon#about to read 3, iclass 4, count 0 2006.259.07:51:10.58#ibcon#read 3, iclass 4, count 0 2006.259.07:51:10.58#ibcon#about to read 4, iclass 4, count 0 2006.259.07:51:10.58#ibcon#read 4, iclass 4, count 0 2006.259.07:51:10.58#ibcon#about to read 5, iclass 4, count 0 2006.259.07:51:10.58#ibcon#read 5, iclass 4, count 0 2006.259.07:51:10.58#ibcon#about to read 6, iclass 4, count 0 2006.259.07:51:10.58#ibcon#read 6, iclass 4, count 0 2006.259.07:51:10.58#ibcon#end of sib2, iclass 4, count 0 2006.259.07:51:10.58#ibcon#*mode == 0, iclass 4, count 0 2006.259.07:51:10.58#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.259.07:51:10.58#ibcon#[26=FRQ=05,652.99\r\n] 2006.259.07:51:10.58#ibcon#*before write, iclass 4, count 0 2006.259.07:51:10.58#ibcon#enter sib2, iclass 4, count 0 2006.259.07:51:10.58#ibcon#flushed, iclass 4, count 0 2006.259.07:51:10.58#ibcon#about to write, iclass 4, count 0 2006.259.07:51:10.58#ibcon#wrote, iclass 4, count 0 2006.259.07:51:10.58#ibcon#about to read 3, iclass 4, count 0 2006.259.07:51:10.62#ibcon#read 3, iclass 4, count 0 2006.259.07:51:10.62#ibcon#about to read 4, iclass 4, count 0 2006.259.07:51:10.62#ibcon#read 4, iclass 4, count 0 2006.259.07:51:10.62#ibcon#about to read 5, iclass 4, count 0 2006.259.07:51:10.62#ibcon#read 5, iclass 4, count 0 2006.259.07:51:10.62#ibcon#about to read 6, iclass 4, count 0 2006.259.07:51:10.62#ibcon#read 6, iclass 4, count 0 2006.259.07:51:10.62#ibcon#end of sib2, iclass 4, count 0 2006.259.07:51:10.62#ibcon#*after write, iclass 4, count 0 2006.259.07:51:10.62#ibcon#*before return 0, iclass 4, count 0 2006.259.07:51:10.62#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.259.07:51:10.62#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.259.07:51:10.62#ibcon#about to clear, iclass 4 cls_cnt 0 2006.259.07:51:10.62#ibcon#cleared, iclass 4 cls_cnt 0 2006.259.07:51:10.62$vc4f8/va=5,7 2006.259.07:51:10.62#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.259.07:51:10.62#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.259.07:51:10.62#ibcon#ireg 11 cls_cnt 2 2006.259.07:51:10.62#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.259.07:51:10.68#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.259.07:51:10.68#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.259.07:51:10.68#ibcon#enter wrdev, iclass 6, count 2 2006.259.07:51:10.68#ibcon#first serial, iclass 6, count 2 2006.259.07:51:10.68#ibcon#enter sib2, iclass 6, count 2 2006.259.07:51:10.68#ibcon#flushed, iclass 6, count 2 2006.259.07:51:10.68#ibcon#about to write, iclass 6, count 2 2006.259.07:51:10.68#ibcon#wrote, iclass 6, count 2 2006.259.07:51:10.68#ibcon#about to read 3, iclass 6, count 2 2006.259.07:51:10.70#ibcon#read 3, iclass 6, count 2 2006.259.07:51:10.70#ibcon#about to read 4, iclass 6, count 2 2006.259.07:51:10.70#ibcon#read 4, iclass 6, count 2 2006.259.07:51:10.70#ibcon#about to read 5, iclass 6, count 2 2006.259.07:51:10.70#ibcon#read 5, iclass 6, count 2 2006.259.07:51:10.70#ibcon#about to read 6, iclass 6, count 2 2006.259.07:51:10.70#ibcon#read 6, iclass 6, count 2 2006.259.07:51:10.70#ibcon#end of sib2, iclass 6, count 2 2006.259.07:51:10.70#ibcon#*mode == 0, iclass 6, count 2 2006.259.07:51:10.70#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.259.07:51:10.70#ibcon#[25=AT05-07\r\n] 2006.259.07:51:10.70#ibcon#*before write, iclass 6, count 2 2006.259.07:51:10.70#ibcon#enter sib2, iclass 6, count 2 2006.259.07:51:10.70#ibcon#flushed, iclass 6, count 2 2006.259.07:51:10.70#ibcon#about to write, iclass 6, count 2 2006.259.07:51:10.70#ibcon#wrote, iclass 6, count 2 2006.259.07:51:10.70#ibcon#about to read 3, iclass 6, count 2 2006.259.07:51:10.73#ibcon#read 3, iclass 6, count 2 2006.259.07:51:10.73#ibcon#about to read 4, iclass 6, count 2 2006.259.07:51:10.73#ibcon#read 4, iclass 6, count 2 2006.259.07:51:10.73#ibcon#about to read 5, iclass 6, count 2 2006.259.07:51:10.73#ibcon#read 5, iclass 6, count 2 2006.259.07:51:10.73#ibcon#about to read 6, iclass 6, count 2 2006.259.07:51:10.73#ibcon#read 6, iclass 6, count 2 2006.259.07:51:10.73#ibcon#end of sib2, iclass 6, count 2 2006.259.07:51:10.73#ibcon#*after write, iclass 6, count 2 2006.259.07:51:10.73#ibcon#*before return 0, iclass 6, count 2 2006.259.07:51:10.73#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.259.07:51:10.73#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.259.07:51:10.73#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.259.07:51:10.73#ibcon#ireg 7 cls_cnt 0 2006.259.07:51:10.73#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.259.07:51:10.85#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.259.07:51:10.85#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.259.07:51:10.85#ibcon#enter wrdev, iclass 6, count 0 2006.259.07:51:10.85#ibcon#first serial, iclass 6, count 0 2006.259.07:51:10.85#ibcon#enter sib2, iclass 6, count 0 2006.259.07:51:10.85#ibcon#flushed, iclass 6, count 0 2006.259.07:51:10.85#ibcon#about to write, iclass 6, count 0 2006.259.07:51:10.85#ibcon#wrote, iclass 6, count 0 2006.259.07:51:10.85#ibcon#about to read 3, iclass 6, count 0 2006.259.07:51:10.87#ibcon#read 3, iclass 6, count 0 2006.259.07:51:10.87#ibcon#about to read 4, iclass 6, count 0 2006.259.07:51:10.87#ibcon#read 4, iclass 6, count 0 2006.259.07:51:10.87#ibcon#about to read 5, iclass 6, count 0 2006.259.07:51:10.87#ibcon#read 5, iclass 6, count 0 2006.259.07:51:10.87#ibcon#about to read 6, iclass 6, count 0 2006.259.07:51:10.87#ibcon#read 6, iclass 6, count 0 2006.259.07:51:10.87#ibcon#end of sib2, iclass 6, count 0 2006.259.07:51:10.87#ibcon#*mode == 0, iclass 6, count 0 2006.259.07:51:10.87#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.259.07:51:10.87#ibcon#[25=USB\r\n] 2006.259.07:51:10.87#ibcon#*before write, iclass 6, count 0 2006.259.07:51:10.87#ibcon#enter sib2, iclass 6, count 0 2006.259.07:51:10.87#ibcon#flushed, iclass 6, count 0 2006.259.07:51:10.87#ibcon#about to write, iclass 6, count 0 2006.259.07:51:10.87#ibcon#wrote, iclass 6, count 0 2006.259.07:51:10.87#ibcon#about to read 3, iclass 6, count 0 2006.259.07:51:10.90#ibcon#read 3, iclass 6, count 0 2006.259.07:51:10.90#ibcon#about to read 4, iclass 6, count 0 2006.259.07:51:10.90#ibcon#read 4, iclass 6, count 0 2006.259.07:51:10.90#ibcon#about to read 5, iclass 6, count 0 2006.259.07:51:10.90#ibcon#read 5, iclass 6, count 0 2006.259.07:51:10.90#ibcon#about to read 6, iclass 6, count 0 2006.259.07:51:10.90#ibcon#read 6, iclass 6, count 0 2006.259.07:51:10.90#ibcon#end of sib2, iclass 6, count 0 2006.259.07:51:10.90#ibcon#*after write, iclass 6, count 0 2006.259.07:51:10.90#ibcon#*before return 0, iclass 6, count 0 2006.259.07:51:10.90#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.259.07:51:10.90#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.259.07:51:10.90#ibcon#about to clear, iclass 6 cls_cnt 0 2006.259.07:51:10.90#ibcon#cleared, iclass 6 cls_cnt 0 2006.259.07:51:10.90$vc4f8/valo=6,772.99 2006.259.07:51:10.90#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.259.07:51:10.90#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.259.07:51:10.90#ibcon#ireg 17 cls_cnt 0 2006.259.07:51:10.90#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.259.07:51:10.90#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.259.07:51:10.90#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.259.07:51:10.90#ibcon#enter wrdev, iclass 10, count 0 2006.259.07:51:10.90#ibcon#first serial, iclass 10, count 0 2006.259.07:51:10.90#ibcon#enter sib2, iclass 10, count 0 2006.259.07:51:10.90#ibcon#flushed, iclass 10, count 0 2006.259.07:51:10.90#ibcon#about to write, iclass 10, count 0 2006.259.07:51:10.90#ibcon#wrote, iclass 10, count 0 2006.259.07:51:10.90#ibcon#about to read 3, iclass 10, count 0 2006.259.07:51:10.92#ibcon#read 3, iclass 10, count 0 2006.259.07:51:10.92#ibcon#about to read 4, iclass 10, count 0 2006.259.07:51:10.92#ibcon#read 4, iclass 10, count 0 2006.259.07:51:10.92#ibcon#about to read 5, iclass 10, count 0 2006.259.07:51:10.92#ibcon#read 5, iclass 10, count 0 2006.259.07:51:10.92#ibcon#about to read 6, iclass 10, count 0 2006.259.07:51:10.92#ibcon#read 6, iclass 10, count 0 2006.259.07:51:10.92#ibcon#end of sib2, iclass 10, count 0 2006.259.07:51:10.92#ibcon#*mode == 0, iclass 10, count 0 2006.259.07:51:10.92#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.259.07:51:10.92#ibcon#[26=FRQ=06,772.99\r\n] 2006.259.07:51:10.92#ibcon#*before write, iclass 10, count 0 2006.259.07:51:10.92#ibcon#enter sib2, iclass 10, count 0 2006.259.07:51:10.92#ibcon#flushed, iclass 10, count 0 2006.259.07:51:10.92#ibcon#about to write, iclass 10, count 0 2006.259.07:51:10.92#ibcon#wrote, iclass 10, count 0 2006.259.07:51:10.92#ibcon#about to read 3, iclass 10, count 0 2006.259.07:51:10.96#ibcon#read 3, iclass 10, count 0 2006.259.07:51:10.96#ibcon#about to read 4, iclass 10, count 0 2006.259.07:51:10.96#ibcon#read 4, iclass 10, count 0 2006.259.07:51:10.96#ibcon#about to read 5, iclass 10, count 0 2006.259.07:51:10.96#ibcon#read 5, iclass 10, count 0 2006.259.07:51:10.96#ibcon#about to read 6, iclass 10, count 0 2006.259.07:51:10.96#ibcon#read 6, iclass 10, count 0 2006.259.07:51:10.96#ibcon#end of sib2, iclass 10, count 0 2006.259.07:51:10.96#ibcon#*after write, iclass 10, count 0 2006.259.07:51:10.96#ibcon#*before return 0, iclass 10, count 0 2006.259.07:51:10.96#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.259.07:51:10.96#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.259.07:51:10.96#ibcon#about to clear, iclass 10 cls_cnt 0 2006.259.07:51:10.96#ibcon#cleared, iclass 10 cls_cnt 0 2006.259.07:51:10.96$vc4f8/va=6,6 2006.259.07:51:10.96#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.259.07:51:10.96#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.259.07:51:10.96#ibcon#ireg 11 cls_cnt 2 2006.259.07:51:10.96#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.259.07:51:11.02#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.259.07:51:11.02#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.259.07:51:11.02#ibcon#enter wrdev, iclass 12, count 2 2006.259.07:51:11.02#ibcon#first serial, iclass 12, count 2 2006.259.07:51:11.02#ibcon#enter sib2, iclass 12, count 2 2006.259.07:51:11.02#ibcon#flushed, iclass 12, count 2 2006.259.07:51:11.02#ibcon#about to write, iclass 12, count 2 2006.259.07:51:11.02#ibcon#wrote, iclass 12, count 2 2006.259.07:51:11.02#ibcon#about to read 3, iclass 12, count 2 2006.259.07:51:11.04#ibcon#read 3, iclass 12, count 2 2006.259.07:51:11.04#ibcon#about to read 4, iclass 12, count 2 2006.259.07:51:11.04#ibcon#read 4, iclass 12, count 2 2006.259.07:51:11.04#ibcon#about to read 5, iclass 12, count 2 2006.259.07:51:11.04#ibcon#read 5, iclass 12, count 2 2006.259.07:51:11.04#ibcon#about to read 6, iclass 12, count 2 2006.259.07:51:11.04#ibcon#read 6, iclass 12, count 2 2006.259.07:51:11.04#ibcon#end of sib2, iclass 12, count 2 2006.259.07:51:11.04#ibcon#*mode == 0, iclass 12, count 2 2006.259.07:51:11.04#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.259.07:51:11.04#ibcon#[25=AT06-06\r\n] 2006.259.07:51:11.04#ibcon#*before write, iclass 12, count 2 2006.259.07:51:11.04#ibcon#enter sib2, iclass 12, count 2 2006.259.07:51:11.04#ibcon#flushed, iclass 12, count 2 2006.259.07:51:11.04#ibcon#about to write, iclass 12, count 2 2006.259.07:51:11.04#ibcon#wrote, iclass 12, count 2 2006.259.07:51:11.04#ibcon#about to read 3, iclass 12, count 2 2006.259.07:51:11.07#ibcon#read 3, iclass 12, count 2 2006.259.07:51:11.07#ibcon#about to read 4, iclass 12, count 2 2006.259.07:51:11.07#ibcon#read 4, iclass 12, count 2 2006.259.07:51:11.07#ibcon#about to read 5, iclass 12, count 2 2006.259.07:51:11.07#ibcon#read 5, iclass 12, count 2 2006.259.07:51:11.07#ibcon#about to read 6, iclass 12, count 2 2006.259.07:51:11.07#ibcon#read 6, iclass 12, count 2 2006.259.07:51:11.07#ibcon#end of sib2, iclass 12, count 2 2006.259.07:51:11.07#ibcon#*after write, iclass 12, count 2 2006.259.07:51:11.07#ibcon#*before return 0, iclass 12, count 2 2006.259.07:51:11.07#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.259.07:51:11.07#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.259.07:51:11.07#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.259.07:51:11.07#ibcon#ireg 7 cls_cnt 0 2006.259.07:51:11.07#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.259.07:51:11.19#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.259.07:51:11.19#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.259.07:51:11.19#ibcon#enter wrdev, iclass 12, count 0 2006.259.07:51:11.19#ibcon#first serial, iclass 12, count 0 2006.259.07:51:11.19#ibcon#enter sib2, iclass 12, count 0 2006.259.07:51:11.19#ibcon#flushed, iclass 12, count 0 2006.259.07:51:11.19#ibcon#about to write, iclass 12, count 0 2006.259.07:51:11.19#ibcon#wrote, iclass 12, count 0 2006.259.07:51:11.19#ibcon#about to read 3, iclass 12, count 0 2006.259.07:51:11.21#ibcon#read 3, iclass 12, count 0 2006.259.07:51:11.21#ibcon#about to read 4, iclass 12, count 0 2006.259.07:51:11.21#ibcon#read 4, iclass 12, count 0 2006.259.07:51:11.21#ibcon#about to read 5, iclass 12, count 0 2006.259.07:51:11.21#ibcon#read 5, iclass 12, count 0 2006.259.07:51:11.21#ibcon#about to read 6, iclass 12, count 0 2006.259.07:51:11.21#ibcon#read 6, iclass 12, count 0 2006.259.07:51:11.21#ibcon#end of sib2, iclass 12, count 0 2006.259.07:51:11.21#ibcon#*mode == 0, iclass 12, count 0 2006.259.07:51:11.21#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.259.07:51:11.21#ibcon#[25=USB\r\n] 2006.259.07:51:11.21#ibcon#*before write, iclass 12, count 0 2006.259.07:51:11.21#ibcon#enter sib2, iclass 12, count 0 2006.259.07:51:11.21#ibcon#flushed, iclass 12, count 0 2006.259.07:51:11.21#ibcon#about to write, iclass 12, count 0 2006.259.07:51:11.21#ibcon#wrote, iclass 12, count 0 2006.259.07:51:11.21#ibcon#about to read 3, iclass 12, count 0 2006.259.07:51:11.24#ibcon#read 3, iclass 12, count 0 2006.259.07:51:11.24#ibcon#about to read 4, iclass 12, count 0 2006.259.07:51:11.24#ibcon#read 4, iclass 12, count 0 2006.259.07:51:11.24#ibcon#about to read 5, iclass 12, count 0 2006.259.07:51:11.24#ibcon#read 5, iclass 12, count 0 2006.259.07:51:11.24#ibcon#about to read 6, iclass 12, count 0 2006.259.07:51:11.24#ibcon#read 6, iclass 12, count 0 2006.259.07:51:11.24#ibcon#end of sib2, iclass 12, count 0 2006.259.07:51:11.24#ibcon#*after write, iclass 12, count 0 2006.259.07:51:11.24#ibcon#*before return 0, iclass 12, count 0 2006.259.07:51:11.24#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.259.07:51:11.24#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.259.07:51:11.24#ibcon#about to clear, iclass 12 cls_cnt 0 2006.259.07:51:11.24#ibcon#cleared, iclass 12 cls_cnt 0 2006.259.07:51:11.24$vc4f8/valo=7,832.99 2006.259.07:51:11.24#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.259.07:51:11.24#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.259.07:51:11.24#ibcon#ireg 17 cls_cnt 0 2006.259.07:51:11.24#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.259.07:51:11.24#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.259.07:51:11.24#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.259.07:51:11.24#ibcon#enter wrdev, iclass 14, count 0 2006.259.07:51:11.24#ibcon#first serial, iclass 14, count 0 2006.259.07:51:11.24#ibcon#enter sib2, iclass 14, count 0 2006.259.07:51:11.24#ibcon#flushed, iclass 14, count 0 2006.259.07:51:11.24#ibcon#about to write, iclass 14, count 0 2006.259.07:51:11.24#ibcon#wrote, iclass 14, count 0 2006.259.07:51:11.24#ibcon#about to read 3, iclass 14, count 0 2006.259.07:51:11.26#ibcon#read 3, iclass 14, count 0 2006.259.07:51:11.26#ibcon#about to read 4, iclass 14, count 0 2006.259.07:51:11.26#ibcon#read 4, iclass 14, count 0 2006.259.07:51:11.26#ibcon#about to read 5, iclass 14, count 0 2006.259.07:51:11.26#ibcon#read 5, iclass 14, count 0 2006.259.07:51:11.26#ibcon#about to read 6, iclass 14, count 0 2006.259.07:51:11.26#ibcon#read 6, iclass 14, count 0 2006.259.07:51:11.26#ibcon#end of sib2, iclass 14, count 0 2006.259.07:51:11.26#ibcon#*mode == 0, iclass 14, count 0 2006.259.07:51:11.26#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.259.07:51:11.26#ibcon#[26=FRQ=07,832.99\r\n] 2006.259.07:51:11.26#ibcon#*before write, iclass 14, count 0 2006.259.07:51:11.26#ibcon#enter sib2, iclass 14, count 0 2006.259.07:51:11.26#ibcon#flushed, iclass 14, count 0 2006.259.07:51:11.26#ibcon#about to write, iclass 14, count 0 2006.259.07:51:11.26#ibcon#wrote, iclass 14, count 0 2006.259.07:51:11.26#ibcon#about to read 3, iclass 14, count 0 2006.259.07:51:11.30#ibcon#read 3, iclass 14, count 0 2006.259.07:51:11.30#ibcon#about to read 4, iclass 14, count 0 2006.259.07:51:11.30#ibcon#read 4, iclass 14, count 0 2006.259.07:51:11.30#ibcon#about to read 5, iclass 14, count 0 2006.259.07:51:11.30#ibcon#read 5, iclass 14, count 0 2006.259.07:51:11.30#ibcon#about to read 6, iclass 14, count 0 2006.259.07:51:11.30#ibcon#read 6, iclass 14, count 0 2006.259.07:51:11.30#ibcon#end of sib2, iclass 14, count 0 2006.259.07:51:11.30#ibcon#*after write, iclass 14, count 0 2006.259.07:51:11.30#ibcon#*before return 0, iclass 14, count 0 2006.259.07:51:11.30#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.259.07:51:11.30#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.259.07:51:11.30#ibcon#about to clear, iclass 14 cls_cnt 0 2006.259.07:51:11.30#ibcon#cleared, iclass 14 cls_cnt 0 2006.259.07:51:11.30$vc4f8/va=7,6 2006.259.07:51:11.30#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.259.07:51:11.30#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.259.07:51:11.30#ibcon#ireg 11 cls_cnt 2 2006.259.07:51:11.30#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.259.07:51:11.36#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.259.07:51:11.36#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.259.07:51:11.36#ibcon#enter wrdev, iclass 16, count 2 2006.259.07:51:11.36#ibcon#first serial, iclass 16, count 2 2006.259.07:51:11.36#ibcon#enter sib2, iclass 16, count 2 2006.259.07:51:11.36#ibcon#flushed, iclass 16, count 2 2006.259.07:51:11.36#ibcon#about to write, iclass 16, count 2 2006.259.07:51:11.36#ibcon#wrote, iclass 16, count 2 2006.259.07:51:11.36#ibcon#about to read 3, iclass 16, count 2 2006.259.07:51:11.38#ibcon#read 3, iclass 16, count 2 2006.259.07:51:11.38#ibcon#about to read 4, iclass 16, count 2 2006.259.07:51:11.38#ibcon#read 4, iclass 16, count 2 2006.259.07:51:11.38#ibcon#about to read 5, iclass 16, count 2 2006.259.07:51:11.38#ibcon#read 5, iclass 16, count 2 2006.259.07:51:11.38#ibcon#about to read 6, iclass 16, count 2 2006.259.07:51:11.38#ibcon#read 6, iclass 16, count 2 2006.259.07:51:11.38#ibcon#end of sib2, iclass 16, count 2 2006.259.07:51:11.38#ibcon#*mode == 0, iclass 16, count 2 2006.259.07:51:11.38#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.259.07:51:11.38#ibcon#[25=AT07-06\r\n] 2006.259.07:51:11.38#ibcon#*before write, iclass 16, count 2 2006.259.07:51:11.38#ibcon#enter sib2, iclass 16, count 2 2006.259.07:51:11.38#ibcon#flushed, iclass 16, count 2 2006.259.07:51:11.38#ibcon#about to write, iclass 16, count 2 2006.259.07:51:11.38#ibcon#wrote, iclass 16, count 2 2006.259.07:51:11.38#ibcon#about to read 3, iclass 16, count 2 2006.259.07:51:11.41#ibcon#read 3, iclass 16, count 2 2006.259.07:51:11.41#ibcon#about to read 4, iclass 16, count 2 2006.259.07:51:11.41#ibcon#read 4, iclass 16, count 2 2006.259.07:51:11.41#ibcon#about to read 5, iclass 16, count 2 2006.259.07:51:11.41#ibcon#read 5, iclass 16, count 2 2006.259.07:51:11.41#ibcon#about to read 6, iclass 16, count 2 2006.259.07:51:11.41#ibcon#read 6, iclass 16, count 2 2006.259.07:51:11.41#ibcon#end of sib2, iclass 16, count 2 2006.259.07:51:11.41#ibcon#*after write, iclass 16, count 2 2006.259.07:51:11.41#ibcon#*before return 0, iclass 16, count 2 2006.259.07:51:11.41#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.259.07:51:11.41#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.259.07:51:11.41#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.259.07:51:11.41#ibcon#ireg 7 cls_cnt 0 2006.259.07:51:11.41#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.259.07:51:11.53#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.259.07:51:11.53#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.259.07:51:11.53#ibcon#enter wrdev, iclass 16, count 0 2006.259.07:51:11.53#ibcon#first serial, iclass 16, count 0 2006.259.07:51:11.53#ibcon#enter sib2, iclass 16, count 0 2006.259.07:51:11.53#ibcon#flushed, iclass 16, count 0 2006.259.07:51:11.53#ibcon#about to write, iclass 16, count 0 2006.259.07:51:11.53#ibcon#wrote, iclass 16, count 0 2006.259.07:51:11.53#ibcon#about to read 3, iclass 16, count 0 2006.259.07:51:11.55#ibcon#read 3, iclass 16, count 0 2006.259.07:51:11.55#ibcon#about to read 4, iclass 16, count 0 2006.259.07:51:11.55#ibcon#read 4, iclass 16, count 0 2006.259.07:51:11.55#ibcon#about to read 5, iclass 16, count 0 2006.259.07:51:11.55#ibcon#read 5, iclass 16, count 0 2006.259.07:51:11.55#ibcon#about to read 6, iclass 16, count 0 2006.259.07:51:11.55#ibcon#read 6, iclass 16, count 0 2006.259.07:51:11.55#ibcon#end of sib2, iclass 16, count 0 2006.259.07:51:11.55#ibcon#*mode == 0, iclass 16, count 0 2006.259.07:51:11.55#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.259.07:51:11.55#ibcon#[25=USB\r\n] 2006.259.07:51:11.55#ibcon#*before write, iclass 16, count 0 2006.259.07:51:11.55#ibcon#enter sib2, iclass 16, count 0 2006.259.07:51:11.55#ibcon#flushed, iclass 16, count 0 2006.259.07:51:11.55#ibcon#about to write, iclass 16, count 0 2006.259.07:51:11.55#ibcon#wrote, iclass 16, count 0 2006.259.07:51:11.55#ibcon#about to read 3, iclass 16, count 0 2006.259.07:51:11.58#ibcon#read 3, iclass 16, count 0 2006.259.07:51:11.58#ibcon#about to read 4, iclass 16, count 0 2006.259.07:51:11.58#ibcon#read 4, iclass 16, count 0 2006.259.07:51:11.58#ibcon#about to read 5, iclass 16, count 0 2006.259.07:51:11.58#ibcon#read 5, iclass 16, count 0 2006.259.07:51:11.58#ibcon#about to read 6, iclass 16, count 0 2006.259.07:51:11.58#ibcon#read 6, iclass 16, count 0 2006.259.07:51:11.58#ibcon#end of sib2, iclass 16, count 0 2006.259.07:51:11.58#ibcon#*after write, iclass 16, count 0 2006.259.07:51:11.58#ibcon#*before return 0, iclass 16, count 0 2006.259.07:51:11.58#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.259.07:51:11.58#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.259.07:51:11.58#ibcon#about to clear, iclass 16 cls_cnt 0 2006.259.07:51:11.58#ibcon#cleared, iclass 16 cls_cnt 0 2006.259.07:51:11.58$vc4f8/valo=8,852.99 2006.259.07:51:11.58#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.259.07:51:11.58#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.259.07:51:11.58#ibcon#ireg 17 cls_cnt 0 2006.259.07:51:11.58#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.259.07:51:11.58#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.259.07:51:11.58#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.259.07:51:11.58#ibcon#enter wrdev, iclass 18, count 0 2006.259.07:51:11.58#ibcon#first serial, iclass 18, count 0 2006.259.07:51:11.58#ibcon#enter sib2, iclass 18, count 0 2006.259.07:51:11.58#ibcon#flushed, iclass 18, count 0 2006.259.07:51:11.58#ibcon#about to write, iclass 18, count 0 2006.259.07:51:11.58#ibcon#wrote, iclass 18, count 0 2006.259.07:51:11.58#ibcon#about to read 3, iclass 18, count 0 2006.259.07:51:11.60#ibcon#read 3, iclass 18, count 0 2006.259.07:51:11.60#ibcon#about to read 4, iclass 18, count 0 2006.259.07:51:11.60#ibcon#read 4, iclass 18, count 0 2006.259.07:51:11.60#ibcon#about to read 5, iclass 18, count 0 2006.259.07:51:11.60#ibcon#read 5, iclass 18, count 0 2006.259.07:51:11.60#ibcon#about to read 6, iclass 18, count 0 2006.259.07:51:11.60#ibcon#read 6, iclass 18, count 0 2006.259.07:51:11.60#ibcon#end of sib2, iclass 18, count 0 2006.259.07:51:11.60#ibcon#*mode == 0, iclass 18, count 0 2006.259.07:51:11.60#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.259.07:51:11.60#ibcon#[26=FRQ=08,852.99\r\n] 2006.259.07:51:11.60#ibcon#*before write, iclass 18, count 0 2006.259.07:51:11.60#ibcon#enter sib2, iclass 18, count 0 2006.259.07:51:11.60#ibcon#flushed, iclass 18, count 0 2006.259.07:51:11.60#ibcon#about to write, iclass 18, count 0 2006.259.07:51:11.60#ibcon#wrote, iclass 18, count 0 2006.259.07:51:11.60#ibcon#about to read 3, iclass 18, count 0 2006.259.07:51:11.64#ibcon#read 3, iclass 18, count 0 2006.259.07:51:11.64#ibcon#about to read 4, iclass 18, count 0 2006.259.07:51:11.64#ibcon#read 4, iclass 18, count 0 2006.259.07:51:11.64#ibcon#about to read 5, iclass 18, count 0 2006.259.07:51:11.64#ibcon#read 5, iclass 18, count 0 2006.259.07:51:11.64#ibcon#about to read 6, iclass 18, count 0 2006.259.07:51:11.64#ibcon#read 6, iclass 18, count 0 2006.259.07:51:11.64#ibcon#end of sib2, iclass 18, count 0 2006.259.07:51:11.64#ibcon#*after write, iclass 18, count 0 2006.259.07:51:11.64#ibcon#*before return 0, iclass 18, count 0 2006.259.07:51:11.64#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.259.07:51:11.64#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.259.07:51:11.64#ibcon#about to clear, iclass 18 cls_cnt 0 2006.259.07:51:11.64#ibcon#cleared, iclass 18 cls_cnt 0 2006.259.07:51:11.64$vc4f8/va=8,6 2006.259.07:51:11.64#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.259.07:51:11.64#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.259.07:51:11.64#ibcon#ireg 11 cls_cnt 2 2006.259.07:51:11.64#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.259.07:51:11.70#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.259.07:51:11.70#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.259.07:51:11.70#ibcon#enter wrdev, iclass 20, count 2 2006.259.07:51:11.70#ibcon#first serial, iclass 20, count 2 2006.259.07:51:11.70#ibcon#enter sib2, iclass 20, count 2 2006.259.07:51:11.70#ibcon#flushed, iclass 20, count 2 2006.259.07:51:11.70#ibcon#about to write, iclass 20, count 2 2006.259.07:51:11.70#ibcon#wrote, iclass 20, count 2 2006.259.07:51:11.70#ibcon#about to read 3, iclass 20, count 2 2006.259.07:51:11.72#ibcon#read 3, iclass 20, count 2 2006.259.07:51:11.72#ibcon#about to read 4, iclass 20, count 2 2006.259.07:51:11.72#ibcon#read 4, iclass 20, count 2 2006.259.07:51:11.72#ibcon#about to read 5, iclass 20, count 2 2006.259.07:51:11.72#ibcon#read 5, iclass 20, count 2 2006.259.07:51:11.72#ibcon#about to read 6, iclass 20, count 2 2006.259.07:51:11.72#ibcon#read 6, iclass 20, count 2 2006.259.07:51:11.72#ibcon#end of sib2, iclass 20, count 2 2006.259.07:51:11.72#ibcon#*mode == 0, iclass 20, count 2 2006.259.07:51:11.72#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.259.07:51:11.72#ibcon#[25=AT08-06\r\n] 2006.259.07:51:11.72#ibcon#*before write, iclass 20, count 2 2006.259.07:51:11.72#ibcon#enter sib2, iclass 20, count 2 2006.259.07:51:11.72#ibcon#flushed, iclass 20, count 2 2006.259.07:51:11.72#ibcon#about to write, iclass 20, count 2 2006.259.07:51:11.72#ibcon#wrote, iclass 20, count 2 2006.259.07:51:11.72#ibcon#about to read 3, iclass 20, count 2 2006.259.07:51:11.75#ibcon#read 3, iclass 20, count 2 2006.259.07:51:11.75#ibcon#about to read 4, iclass 20, count 2 2006.259.07:51:11.75#ibcon#read 4, iclass 20, count 2 2006.259.07:51:11.75#ibcon#about to read 5, iclass 20, count 2 2006.259.07:51:11.75#ibcon#read 5, iclass 20, count 2 2006.259.07:51:11.75#ibcon#about to read 6, iclass 20, count 2 2006.259.07:51:11.75#ibcon#read 6, iclass 20, count 2 2006.259.07:51:11.75#ibcon#end of sib2, iclass 20, count 2 2006.259.07:51:11.75#ibcon#*after write, iclass 20, count 2 2006.259.07:51:11.75#ibcon#*before return 0, iclass 20, count 2 2006.259.07:51:11.75#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.259.07:51:11.75#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.259.07:51:11.75#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.259.07:51:11.75#ibcon#ireg 7 cls_cnt 0 2006.259.07:51:11.75#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.259.07:51:11.87#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.259.07:51:11.87#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.259.07:51:11.87#ibcon#enter wrdev, iclass 20, count 0 2006.259.07:51:11.87#ibcon#first serial, iclass 20, count 0 2006.259.07:51:11.87#ibcon#enter sib2, iclass 20, count 0 2006.259.07:51:11.87#ibcon#flushed, iclass 20, count 0 2006.259.07:51:11.87#ibcon#about to write, iclass 20, count 0 2006.259.07:51:11.87#ibcon#wrote, iclass 20, count 0 2006.259.07:51:11.87#ibcon#about to read 3, iclass 20, count 0 2006.259.07:51:11.89#ibcon#read 3, iclass 20, count 0 2006.259.07:51:11.89#ibcon#about to read 4, iclass 20, count 0 2006.259.07:51:11.89#ibcon#read 4, iclass 20, count 0 2006.259.07:51:11.89#ibcon#about to read 5, iclass 20, count 0 2006.259.07:51:11.89#ibcon#read 5, iclass 20, count 0 2006.259.07:51:11.89#ibcon#about to read 6, iclass 20, count 0 2006.259.07:51:11.89#ibcon#read 6, iclass 20, count 0 2006.259.07:51:11.89#ibcon#end of sib2, iclass 20, count 0 2006.259.07:51:11.89#ibcon#*mode == 0, iclass 20, count 0 2006.259.07:51:11.89#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.259.07:51:11.89#ibcon#[25=USB\r\n] 2006.259.07:51:11.89#ibcon#*before write, iclass 20, count 0 2006.259.07:51:11.89#ibcon#enter sib2, iclass 20, count 0 2006.259.07:51:11.89#ibcon#flushed, iclass 20, count 0 2006.259.07:51:11.89#ibcon#about to write, iclass 20, count 0 2006.259.07:51:11.89#ibcon#wrote, iclass 20, count 0 2006.259.07:51:11.89#ibcon#about to read 3, iclass 20, count 0 2006.259.07:51:11.92#ibcon#read 3, iclass 20, count 0 2006.259.07:51:11.92#ibcon#about to read 4, iclass 20, count 0 2006.259.07:51:11.92#ibcon#read 4, iclass 20, count 0 2006.259.07:51:11.92#ibcon#about to read 5, iclass 20, count 0 2006.259.07:51:11.92#ibcon#read 5, iclass 20, count 0 2006.259.07:51:11.92#ibcon#about to read 6, iclass 20, count 0 2006.259.07:51:11.92#ibcon#read 6, iclass 20, count 0 2006.259.07:51:11.92#ibcon#end of sib2, iclass 20, count 0 2006.259.07:51:11.92#ibcon#*after write, iclass 20, count 0 2006.259.07:51:11.92#ibcon#*before return 0, iclass 20, count 0 2006.259.07:51:11.92#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.259.07:51:11.92#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.259.07:51:11.92#ibcon#about to clear, iclass 20 cls_cnt 0 2006.259.07:51:11.92#ibcon#cleared, iclass 20 cls_cnt 0 2006.259.07:51:11.92$vc4f8/vblo=1,632.99 2006.259.07:51:11.92#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.259.07:51:11.92#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.259.07:51:11.92#ibcon#ireg 17 cls_cnt 0 2006.259.07:51:11.92#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.259.07:51:11.92#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.259.07:51:11.92#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.259.07:51:11.92#ibcon#enter wrdev, iclass 22, count 0 2006.259.07:51:11.92#ibcon#first serial, iclass 22, count 0 2006.259.07:51:11.92#ibcon#enter sib2, iclass 22, count 0 2006.259.07:51:11.92#ibcon#flushed, iclass 22, count 0 2006.259.07:51:11.92#ibcon#about to write, iclass 22, count 0 2006.259.07:51:11.92#ibcon#wrote, iclass 22, count 0 2006.259.07:51:11.92#ibcon#about to read 3, iclass 22, count 0 2006.259.07:51:11.94#ibcon#read 3, iclass 22, count 0 2006.259.07:51:11.94#ibcon#about to read 4, iclass 22, count 0 2006.259.07:51:11.94#ibcon#read 4, iclass 22, count 0 2006.259.07:51:11.94#ibcon#about to read 5, iclass 22, count 0 2006.259.07:51:11.94#ibcon#read 5, iclass 22, count 0 2006.259.07:51:11.94#ibcon#about to read 6, iclass 22, count 0 2006.259.07:51:11.94#ibcon#read 6, iclass 22, count 0 2006.259.07:51:11.94#ibcon#end of sib2, iclass 22, count 0 2006.259.07:51:11.94#ibcon#*mode == 0, iclass 22, count 0 2006.259.07:51:11.94#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.259.07:51:11.94#ibcon#[28=FRQ=01,632.99\r\n] 2006.259.07:51:11.94#ibcon#*before write, iclass 22, count 0 2006.259.07:51:11.94#ibcon#enter sib2, iclass 22, count 0 2006.259.07:51:11.94#ibcon#flushed, iclass 22, count 0 2006.259.07:51:11.94#ibcon#about to write, iclass 22, count 0 2006.259.07:51:11.94#ibcon#wrote, iclass 22, count 0 2006.259.07:51:11.94#ibcon#about to read 3, iclass 22, count 0 2006.259.07:51:11.98#ibcon#read 3, iclass 22, count 0 2006.259.07:51:11.98#ibcon#about to read 4, iclass 22, count 0 2006.259.07:51:11.98#ibcon#read 4, iclass 22, count 0 2006.259.07:51:11.98#ibcon#about to read 5, iclass 22, count 0 2006.259.07:51:11.98#ibcon#read 5, iclass 22, count 0 2006.259.07:51:11.98#ibcon#about to read 6, iclass 22, count 0 2006.259.07:51:11.98#ibcon#read 6, iclass 22, count 0 2006.259.07:51:11.98#ibcon#end of sib2, iclass 22, count 0 2006.259.07:51:11.98#ibcon#*after write, iclass 22, count 0 2006.259.07:51:11.98#ibcon#*before return 0, iclass 22, count 0 2006.259.07:51:11.98#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.259.07:51:11.98#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.259.07:51:11.98#ibcon#about to clear, iclass 22 cls_cnt 0 2006.259.07:51:11.98#ibcon#cleared, iclass 22 cls_cnt 0 2006.259.07:51:11.98$vc4f8/vb=1,4 2006.259.07:51:11.98#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.259.07:51:11.98#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.259.07:51:11.98#ibcon#ireg 11 cls_cnt 2 2006.259.07:51:11.98#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.259.07:51:11.98#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.259.07:51:11.98#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.259.07:51:11.98#ibcon#enter wrdev, iclass 24, count 2 2006.259.07:51:11.98#ibcon#first serial, iclass 24, count 2 2006.259.07:51:11.98#ibcon#enter sib2, iclass 24, count 2 2006.259.07:51:11.98#ibcon#flushed, iclass 24, count 2 2006.259.07:51:11.98#ibcon#about to write, iclass 24, count 2 2006.259.07:51:11.98#ibcon#wrote, iclass 24, count 2 2006.259.07:51:11.98#ibcon#about to read 3, iclass 24, count 2 2006.259.07:51:12.00#ibcon#read 3, iclass 24, count 2 2006.259.07:51:12.00#ibcon#about to read 4, iclass 24, count 2 2006.259.07:51:12.00#ibcon#read 4, iclass 24, count 2 2006.259.07:51:12.00#ibcon#about to read 5, iclass 24, count 2 2006.259.07:51:12.00#ibcon#read 5, iclass 24, count 2 2006.259.07:51:12.00#ibcon#about to read 6, iclass 24, count 2 2006.259.07:51:12.00#ibcon#read 6, iclass 24, count 2 2006.259.07:51:12.00#ibcon#end of sib2, iclass 24, count 2 2006.259.07:51:12.00#ibcon#*mode == 0, iclass 24, count 2 2006.259.07:51:12.00#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.259.07:51:12.00#ibcon#[27=AT01-04\r\n] 2006.259.07:51:12.00#ibcon#*before write, iclass 24, count 2 2006.259.07:51:12.00#ibcon#enter sib2, iclass 24, count 2 2006.259.07:51:12.00#ibcon#flushed, iclass 24, count 2 2006.259.07:51:12.00#ibcon#about to write, iclass 24, count 2 2006.259.07:51:12.00#ibcon#wrote, iclass 24, count 2 2006.259.07:51:12.00#ibcon#about to read 3, iclass 24, count 2 2006.259.07:51:12.03#ibcon#read 3, iclass 24, count 2 2006.259.07:51:12.03#ibcon#about to read 4, iclass 24, count 2 2006.259.07:51:12.03#ibcon#read 4, iclass 24, count 2 2006.259.07:51:12.03#ibcon#about to read 5, iclass 24, count 2 2006.259.07:51:12.03#ibcon#read 5, iclass 24, count 2 2006.259.07:51:12.03#ibcon#about to read 6, iclass 24, count 2 2006.259.07:51:12.03#ibcon#read 6, iclass 24, count 2 2006.259.07:51:12.03#ibcon#end of sib2, iclass 24, count 2 2006.259.07:51:12.03#ibcon#*after write, iclass 24, count 2 2006.259.07:51:12.03#ibcon#*before return 0, iclass 24, count 2 2006.259.07:51:12.03#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.259.07:51:12.03#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.259.07:51:12.03#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.259.07:51:12.03#ibcon#ireg 7 cls_cnt 0 2006.259.07:51:12.03#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.259.07:51:12.15#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.259.07:51:12.15#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.259.07:51:12.15#ibcon#enter wrdev, iclass 24, count 0 2006.259.07:51:12.15#ibcon#first serial, iclass 24, count 0 2006.259.07:51:12.15#ibcon#enter sib2, iclass 24, count 0 2006.259.07:51:12.15#ibcon#flushed, iclass 24, count 0 2006.259.07:51:12.15#ibcon#about to write, iclass 24, count 0 2006.259.07:51:12.15#ibcon#wrote, iclass 24, count 0 2006.259.07:51:12.15#ibcon#about to read 3, iclass 24, count 0 2006.259.07:51:12.17#ibcon#read 3, iclass 24, count 0 2006.259.07:51:12.17#ibcon#about to read 4, iclass 24, count 0 2006.259.07:51:12.17#ibcon#read 4, iclass 24, count 0 2006.259.07:51:12.17#ibcon#about to read 5, iclass 24, count 0 2006.259.07:51:12.17#ibcon#read 5, iclass 24, count 0 2006.259.07:51:12.17#ibcon#about to read 6, iclass 24, count 0 2006.259.07:51:12.17#ibcon#read 6, iclass 24, count 0 2006.259.07:51:12.17#ibcon#end of sib2, iclass 24, count 0 2006.259.07:51:12.17#ibcon#*mode == 0, iclass 24, count 0 2006.259.07:51:12.17#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.259.07:51:12.17#ibcon#[27=USB\r\n] 2006.259.07:51:12.17#ibcon#*before write, iclass 24, count 0 2006.259.07:51:12.17#ibcon#enter sib2, iclass 24, count 0 2006.259.07:51:12.17#ibcon#flushed, iclass 24, count 0 2006.259.07:51:12.17#ibcon#about to write, iclass 24, count 0 2006.259.07:51:12.17#ibcon#wrote, iclass 24, count 0 2006.259.07:51:12.17#ibcon#about to read 3, iclass 24, count 0 2006.259.07:51:12.20#ibcon#read 3, iclass 24, count 0 2006.259.07:51:12.20#ibcon#about to read 4, iclass 24, count 0 2006.259.07:51:12.20#ibcon#read 4, iclass 24, count 0 2006.259.07:51:12.20#ibcon#about to read 5, iclass 24, count 0 2006.259.07:51:12.20#ibcon#read 5, iclass 24, count 0 2006.259.07:51:12.20#ibcon#about to read 6, iclass 24, count 0 2006.259.07:51:12.20#ibcon#read 6, iclass 24, count 0 2006.259.07:51:12.20#ibcon#end of sib2, iclass 24, count 0 2006.259.07:51:12.20#ibcon#*after write, iclass 24, count 0 2006.259.07:51:12.20#ibcon#*before return 0, iclass 24, count 0 2006.259.07:51:12.20#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.259.07:51:12.20#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.259.07:51:12.20#ibcon#about to clear, iclass 24 cls_cnt 0 2006.259.07:51:12.20#ibcon#cleared, iclass 24 cls_cnt 0 2006.259.07:51:12.20$vc4f8/vblo=2,640.99 2006.259.07:51:12.20#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.259.07:51:12.20#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.259.07:51:12.20#ibcon#ireg 17 cls_cnt 0 2006.259.07:51:12.20#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.259.07:51:12.20#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.259.07:51:12.20#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.259.07:51:12.20#ibcon#enter wrdev, iclass 26, count 0 2006.259.07:51:12.20#ibcon#first serial, iclass 26, count 0 2006.259.07:51:12.20#ibcon#enter sib2, iclass 26, count 0 2006.259.07:51:12.20#ibcon#flushed, iclass 26, count 0 2006.259.07:51:12.20#ibcon#about to write, iclass 26, count 0 2006.259.07:51:12.20#ibcon#wrote, iclass 26, count 0 2006.259.07:51:12.20#ibcon#about to read 3, iclass 26, count 0 2006.259.07:51:12.22#ibcon#read 3, iclass 26, count 0 2006.259.07:51:12.22#ibcon#about to read 4, iclass 26, count 0 2006.259.07:51:12.22#ibcon#read 4, iclass 26, count 0 2006.259.07:51:12.22#ibcon#about to read 5, iclass 26, count 0 2006.259.07:51:12.22#ibcon#read 5, iclass 26, count 0 2006.259.07:51:12.22#ibcon#about to read 6, iclass 26, count 0 2006.259.07:51:12.22#ibcon#read 6, iclass 26, count 0 2006.259.07:51:12.22#ibcon#end of sib2, iclass 26, count 0 2006.259.07:51:12.22#ibcon#*mode == 0, iclass 26, count 0 2006.259.07:51:12.22#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.259.07:51:12.22#ibcon#[28=FRQ=02,640.99\r\n] 2006.259.07:51:12.22#ibcon#*before write, iclass 26, count 0 2006.259.07:51:12.22#ibcon#enter sib2, iclass 26, count 0 2006.259.07:51:12.22#ibcon#flushed, iclass 26, count 0 2006.259.07:51:12.22#ibcon#about to write, iclass 26, count 0 2006.259.07:51:12.22#ibcon#wrote, iclass 26, count 0 2006.259.07:51:12.22#ibcon#about to read 3, iclass 26, count 0 2006.259.07:51:12.26#ibcon#read 3, iclass 26, count 0 2006.259.07:51:12.26#ibcon#about to read 4, iclass 26, count 0 2006.259.07:51:12.26#ibcon#read 4, iclass 26, count 0 2006.259.07:51:12.26#ibcon#about to read 5, iclass 26, count 0 2006.259.07:51:12.26#ibcon#read 5, iclass 26, count 0 2006.259.07:51:12.26#ibcon#about to read 6, iclass 26, count 0 2006.259.07:51:12.26#ibcon#read 6, iclass 26, count 0 2006.259.07:51:12.26#ibcon#end of sib2, iclass 26, count 0 2006.259.07:51:12.26#ibcon#*after write, iclass 26, count 0 2006.259.07:51:12.26#ibcon#*before return 0, iclass 26, count 0 2006.259.07:51:12.26#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.259.07:51:12.26#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.259.07:51:12.26#ibcon#about to clear, iclass 26 cls_cnt 0 2006.259.07:51:12.26#ibcon#cleared, iclass 26 cls_cnt 0 2006.259.07:51:12.26$vc4f8/vb=2,5 2006.259.07:51:12.26#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.259.07:51:12.26#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.259.07:51:12.26#ibcon#ireg 11 cls_cnt 2 2006.259.07:51:12.26#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.259.07:51:12.31#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.259.07:51:12.32#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.259.07:51:12.32#ibcon#enter wrdev, iclass 28, count 2 2006.259.07:51:12.32#ibcon#first serial, iclass 28, count 2 2006.259.07:51:12.32#ibcon#enter sib2, iclass 28, count 2 2006.259.07:51:12.32#ibcon#flushed, iclass 28, count 2 2006.259.07:51:12.32#ibcon#about to write, iclass 28, count 2 2006.259.07:51:12.32#ibcon#wrote, iclass 28, count 2 2006.259.07:51:12.32#ibcon#about to read 3, iclass 28, count 2 2006.259.07:51:12.34#ibcon#read 3, iclass 28, count 2 2006.259.07:51:12.34#ibcon#about to read 4, iclass 28, count 2 2006.259.07:51:12.34#ibcon#read 4, iclass 28, count 2 2006.259.07:51:12.34#ibcon#about to read 5, iclass 28, count 2 2006.259.07:51:12.34#ibcon#read 5, iclass 28, count 2 2006.259.07:51:12.34#ibcon#about to read 6, iclass 28, count 2 2006.259.07:51:12.34#ibcon#read 6, iclass 28, count 2 2006.259.07:51:12.34#ibcon#end of sib2, iclass 28, count 2 2006.259.07:51:12.34#ibcon#*mode == 0, iclass 28, count 2 2006.259.07:51:12.34#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.259.07:51:12.34#ibcon#[27=AT02-05\r\n] 2006.259.07:51:12.34#ibcon#*before write, iclass 28, count 2 2006.259.07:51:12.34#ibcon#enter sib2, iclass 28, count 2 2006.259.07:51:12.34#ibcon#flushed, iclass 28, count 2 2006.259.07:51:12.34#ibcon#about to write, iclass 28, count 2 2006.259.07:51:12.34#ibcon#wrote, iclass 28, count 2 2006.259.07:51:12.34#ibcon#about to read 3, iclass 28, count 2 2006.259.07:51:12.37#ibcon#read 3, iclass 28, count 2 2006.259.07:51:12.37#ibcon#about to read 4, iclass 28, count 2 2006.259.07:51:12.37#ibcon#read 4, iclass 28, count 2 2006.259.07:51:12.37#ibcon#about to read 5, iclass 28, count 2 2006.259.07:51:12.37#ibcon#read 5, iclass 28, count 2 2006.259.07:51:12.37#ibcon#about to read 6, iclass 28, count 2 2006.259.07:51:12.37#ibcon#read 6, iclass 28, count 2 2006.259.07:51:12.37#ibcon#end of sib2, iclass 28, count 2 2006.259.07:51:12.37#ibcon#*after write, iclass 28, count 2 2006.259.07:51:12.37#ibcon#*before return 0, iclass 28, count 2 2006.259.07:51:12.37#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.259.07:51:12.37#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.259.07:51:12.37#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.259.07:51:12.37#ibcon#ireg 7 cls_cnt 0 2006.259.07:51:12.37#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.259.07:51:12.49#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.259.07:51:12.49#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.259.07:51:12.49#ibcon#enter wrdev, iclass 28, count 0 2006.259.07:51:12.49#ibcon#first serial, iclass 28, count 0 2006.259.07:51:12.49#ibcon#enter sib2, iclass 28, count 0 2006.259.07:51:12.49#ibcon#flushed, iclass 28, count 0 2006.259.07:51:12.49#ibcon#about to write, iclass 28, count 0 2006.259.07:51:12.49#ibcon#wrote, iclass 28, count 0 2006.259.07:51:12.49#ibcon#about to read 3, iclass 28, count 0 2006.259.07:51:12.51#ibcon#read 3, iclass 28, count 0 2006.259.07:51:12.51#ibcon#about to read 4, iclass 28, count 0 2006.259.07:51:12.51#ibcon#read 4, iclass 28, count 0 2006.259.07:51:12.51#ibcon#about to read 5, iclass 28, count 0 2006.259.07:51:12.51#ibcon#read 5, iclass 28, count 0 2006.259.07:51:12.51#ibcon#about to read 6, iclass 28, count 0 2006.259.07:51:12.51#ibcon#read 6, iclass 28, count 0 2006.259.07:51:12.51#ibcon#end of sib2, iclass 28, count 0 2006.259.07:51:12.51#ibcon#*mode == 0, iclass 28, count 0 2006.259.07:51:12.51#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.259.07:51:12.51#ibcon#[27=USB\r\n] 2006.259.07:51:12.51#ibcon#*before write, iclass 28, count 0 2006.259.07:51:12.51#ibcon#enter sib2, iclass 28, count 0 2006.259.07:51:12.51#ibcon#flushed, iclass 28, count 0 2006.259.07:51:12.51#ibcon#about to write, iclass 28, count 0 2006.259.07:51:12.51#ibcon#wrote, iclass 28, count 0 2006.259.07:51:12.51#ibcon#about to read 3, iclass 28, count 0 2006.259.07:51:12.54#ibcon#read 3, iclass 28, count 0 2006.259.07:51:12.54#ibcon#about to read 4, iclass 28, count 0 2006.259.07:51:12.54#ibcon#read 4, iclass 28, count 0 2006.259.07:51:12.54#ibcon#about to read 5, iclass 28, count 0 2006.259.07:51:12.54#ibcon#read 5, iclass 28, count 0 2006.259.07:51:12.54#ibcon#about to read 6, iclass 28, count 0 2006.259.07:51:12.54#ibcon#read 6, iclass 28, count 0 2006.259.07:51:12.54#ibcon#end of sib2, iclass 28, count 0 2006.259.07:51:12.54#ibcon#*after write, iclass 28, count 0 2006.259.07:51:12.54#ibcon#*before return 0, iclass 28, count 0 2006.259.07:51:12.54#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.259.07:51:12.54#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.259.07:51:12.54#ibcon#about to clear, iclass 28 cls_cnt 0 2006.259.07:51:12.54#ibcon#cleared, iclass 28 cls_cnt 0 2006.259.07:51:12.54$vc4f8/vblo=3,656.99 2006.259.07:51:12.54#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.259.07:51:12.54#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.259.07:51:12.54#ibcon#ireg 17 cls_cnt 0 2006.259.07:51:12.54#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.259.07:51:12.54#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.259.07:51:12.54#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.259.07:51:12.54#ibcon#enter wrdev, iclass 30, count 0 2006.259.07:51:12.54#ibcon#first serial, iclass 30, count 0 2006.259.07:51:12.54#ibcon#enter sib2, iclass 30, count 0 2006.259.07:51:12.54#ibcon#flushed, iclass 30, count 0 2006.259.07:51:12.54#ibcon#about to write, iclass 30, count 0 2006.259.07:51:12.54#ibcon#wrote, iclass 30, count 0 2006.259.07:51:12.54#ibcon#about to read 3, iclass 30, count 0 2006.259.07:51:12.56#ibcon#read 3, iclass 30, count 0 2006.259.07:51:12.56#ibcon#about to read 4, iclass 30, count 0 2006.259.07:51:12.56#ibcon#read 4, iclass 30, count 0 2006.259.07:51:12.56#ibcon#about to read 5, iclass 30, count 0 2006.259.07:51:12.56#ibcon#read 5, iclass 30, count 0 2006.259.07:51:12.56#ibcon#about to read 6, iclass 30, count 0 2006.259.07:51:12.56#ibcon#read 6, iclass 30, count 0 2006.259.07:51:12.56#ibcon#end of sib2, iclass 30, count 0 2006.259.07:51:12.56#ibcon#*mode == 0, iclass 30, count 0 2006.259.07:51:12.56#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.259.07:51:12.56#ibcon#[28=FRQ=03,656.99\r\n] 2006.259.07:51:12.56#ibcon#*before write, iclass 30, count 0 2006.259.07:51:12.56#ibcon#enter sib2, iclass 30, count 0 2006.259.07:51:12.56#ibcon#flushed, iclass 30, count 0 2006.259.07:51:12.56#ibcon#about to write, iclass 30, count 0 2006.259.07:51:12.56#ibcon#wrote, iclass 30, count 0 2006.259.07:51:12.56#ibcon#about to read 3, iclass 30, count 0 2006.259.07:51:12.60#ibcon#read 3, iclass 30, count 0 2006.259.07:51:12.60#ibcon#about to read 4, iclass 30, count 0 2006.259.07:51:12.60#ibcon#read 4, iclass 30, count 0 2006.259.07:51:12.60#ibcon#about to read 5, iclass 30, count 0 2006.259.07:51:12.60#ibcon#read 5, iclass 30, count 0 2006.259.07:51:12.60#ibcon#about to read 6, iclass 30, count 0 2006.259.07:51:12.60#ibcon#read 6, iclass 30, count 0 2006.259.07:51:12.60#ibcon#end of sib2, iclass 30, count 0 2006.259.07:51:12.60#ibcon#*after write, iclass 30, count 0 2006.259.07:51:12.60#ibcon#*before return 0, iclass 30, count 0 2006.259.07:51:12.60#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.259.07:51:12.60#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.259.07:51:12.60#ibcon#about to clear, iclass 30 cls_cnt 0 2006.259.07:51:12.60#ibcon#cleared, iclass 30 cls_cnt 0 2006.259.07:51:12.60$vc4f8/vb=3,4 2006.259.07:51:12.60#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.259.07:51:12.60#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.259.07:51:12.60#ibcon#ireg 11 cls_cnt 2 2006.259.07:51:12.60#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.259.07:51:12.65#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.259.07:51:12.66#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.259.07:51:12.66#ibcon#enter wrdev, iclass 32, count 2 2006.259.07:51:12.66#ibcon#first serial, iclass 32, count 2 2006.259.07:51:12.66#ibcon#enter sib2, iclass 32, count 2 2006.259.07:51:12.66#ibcon#flushed, iclass 32, count 2 2006.259.07:51:12.66#ibcon#about to write, iclass 32, count 2 2006.259.07:51:12.66#ibcon#wrote, iclass 32, count 2 2006.259.07:51:12.66#ibcon#about to read 3, iclass 32, count 2 2006.259.07:51:12.68#ibcon#read 3, iclass 32, count 2 2006.259.07:51:12.68#ibcon#about to read 4, iclass 32, count 2 2006.259.07:51:12.68#ibcon#read 4, iclass 32, count 2 2006.259.07:51:12.68#ibcon#about to read 5, iclass 32, count 2 2006.259.07:51:12.68#ibcon#read 5, iclass 32, count 2 2006.259.07:51:12.68#ibcon#about to read 6, iclass 32, count 2 2006.259.07:51:12.68#ibcon#read 6, iclass 32, count 2 2006.259.07:51:12.68#ibcon#end of sib2, iclass 32, count 2 2006.259.07:51:12.68#ibcon#*mode == 0, iclass 32, count 2 2006.259.07:51:12.68#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.259.07:51:12.68#ibcon#[27=AT03-04\r\n] 2006.259.07:51:12.68#ibcon#*before write, iclass 32, count 2 2006.259.07:51:12.68#ibcon#enter sib2, iclass 32, count 2 2006.259.07:51:12.68#ibcon#flushed, iclass 32, count 2 2006.259.07:51:12.68#ibcon#about to write, iclass 32, count 2 2006.259.07:51:12.68#ibcon#wrote, iclass 32, count 2 2006.259.07:51:12.68#ibcon#about to read 3, iclass 32, count 2 2006.259.07:51:12.71#ibcon#read 3, iclass 32, count 2 2006.259.07:51:12.71#ibcon#about to read 4, iclass 32, count 2 2006.259.07:51:12.71#ibcon#read 4, iclass 32, count 2 2006.259.07:51:12.71#ibcon#about to read 5, iclass 32, count 2 2006.259.07:51:12.71#ibcon#read 5, iclass 32, count 2 2006.259.07:51:12.71#ibcon#about to read 6, iclass 32, count 2 2006.259.07:51:12.71#ibcon#read 6, iclass 32, count 2 2006.259.07:51:12.71#ibcon#end of sib2, iclass 32, count 2 2006.259.07:51:12.71#ibcon#*after write, iclass 32, count 2 2006.259.07:51:12.71#ibcon#*before return 0, iclass 32, count 2 2006.259.07:51:12.71#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.259.07:51:12.71#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.259.07:51:12.71#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.259.07:51:12.71#ibcon#ireg 7 cls_cnt 0 2006.259.07:51:12.71#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.259.07:51:12.82#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.259.07:51:12.83#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.259.07:51:12.83#ibcon#enter wrdev, iclass 32, count 0 2006.259.07:51:12.83#ibcon#first serial, iclass 32, count 0 2006.259.07:51:12.83#ibcon#enter sib2, iclass 32, count 0 2006.259.07:51:12.83#ibcon#flushed, iclass 32, count 0 2006.259.07:51:12.83#ibcon#about to write, iclass 32, count 0 2006.259.07:51:12.83#ibcon#wrote, iclass 32, count 0 2006.259.07:51:12.83#ibcon#about to read 3, iclass 32, count 0 2006.259.07:51:12.85#ibcon#read 3, iclass 32, count 0 2006.259.07:51:12.85#ibcon#about to read 4, iclass 32, count 0 2006.259.07:51:12.85#ibcon#read 4, iclass 32, count 0 2006.259.07:51:12.85#ibcon#about to read 5, iclass 32, count 0 2006.259.07:51:12.85#ibcon#read 5, iclass 32, count 0 2006.259.07:51:12.85#ibcon#about to read 6, iclass 32, count 0 2006.259.07:51:12.85#ibcon#read 6, iclass 32, count 0 2006.259.07:51:12.85#ibcon#end of sib2, iclass 32, count 0 2006.259.07:51:12.85#ibcon#*mode == 0, iclass 32, count 0 2006.259.07:51:12.85#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.259.07:51:12.85#ibcon#[27=USB\r\n] 2006.259.07:51:12.85#ibcon#*before write, iclass 32, count 0 2006.259.07:51:12.85#ibcon#enter sib2, iclass 32, count 0 2006.259.07:51:12.85#ibcon#flushed, iclass 32, count 0 2006.259.07:51:12.85#ibcon#about to write, iclass 32, count 0 2006.259.07:51:12.85#ibcon#wrote, iclass 32, count 0 2006.259.07:51:12.85#ibcon#about to read 3, iclass 32, count 0 2006.259.07:51:12.88#ibcon#read 3, iclass 32, count 0 2006.259.07:51:12.88#ibcon#about to read 4, iclass 32, count 0 2006.259.07:51:12.88#ibcon#read 4, iclass 32, count 0 2006.259.07:51:12.88#ibcon#about to read 5, iclass 32, count 0 2006.259.07:51:12.88#ibcon#read 5, iclass 32, count 0 2006.259.07:51:12.88#ibcon#about to read 6, iclass 32, count 0 2006.259.07:51:12.88#ibcon#read 6, iclass 32, count 0 2006.259.07:51:12.88#ibcon#end of sib2, iclass 32, count 0 2006.259.07:51:12.88#ibcon#*after write, iclass 32, count 0 2006.259.07:51:12.88#ibcon#*before return 0, iclass 32, count 0 2006.259.07:51:12.88#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.259.07:51:12.88#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.259.07:51:12.88#ibcon#about to clear, iclass 32 cls_cnt 0 2006.259.07:51:12.88#ibcon#cleared, iclass 32 cls_cnt 0 2006.259.07:51:12.88$vc4f8/vblo=4,712.99 2006.259.07:51:12.88#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.259.07:51:12.88#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.259.07:51:12.88#ibcon#ireg 17 cls_cnt 0 2006.259.07:51:12.88#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.259.07:51:12.88#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.259.07:51:12.88#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.259.07:51:12.88#ibcon#enter wrdev, iclass 34, count 0 2006.259.07:51:12.88#ibcon#first serial, iclass 34, count 0 2006.259.07:51:12.88#ibcon#enter sib2, iclass 34, count 0 2006.259.07:51:12.88#ibcon#flushed, iclass 34, count 0 2006.259.07:51:12.88#ibcon#about to write, iclass 34, count 0 2006.259.07:51:12.88#ibcon#wrote, iclass 34, count 0 2006.259.07:51:12.88#ibcon#about to read 3, iclass 34, count 0 2006.259.07:51:12.90#ibcon#read 3, iclass 34, count 0 2006.259.07:51:12.90#ibcon#about to read 4, iclass 34, count 0 2006.259.07:51:12.90#ibcon#read 4, iclass 34, count 0 2006.259.07:51:12.90#ibcon#about to read 5, iclass 34, count 0 2006.259.07:51:12.90#ibcon#read 5, iclass 34, count 0 2006.259.07:51:12.90#ibcon#about to read 6, iclass 34, count 0 2006.259.07:51:12.90#ibcon#read 6, iclass 34, count 0 2006.259.07:51:12.90#ibcon#end of sib2, iclass 34, count 0 2006.259.07:51:12.90#ibcon#*mode == 0, iclass 34, count 0 2006.259.07:51:12.90#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.259.07:51:12.90#ibcon#[28=FRQ=04,712.99\r\n] 2006.259.07:51:12.90#ibcon#*before write, iclass 34, count 0 2006.259.07:51:12.90#ibcon#enter sib2, iclass 34, count 0 2006.259.07:51:12.90#ibcon#flushed, iclass 34, count 0 2006.259.07:51:12.90#ibcon#about to write, iclass 34, count 0 2006.259.07:51:12.90#ibcon#wrote, iclass 34, count 0 2006.259.07:51:12.90#ibcon#about to read 3, iclass 34, count 0 2006.259.07:51:12.94#ibcon#read 3, iclass 34, count 0 2006.259.07:51:12.94#ibcon#about to read 4, iclass 34, count 0 2006.259.07:51:12.94#ibcon#read 4, iclass 34, count 0 2006.259.07:51:12.94#ibcon#about to read 5, iclass 34, count 0 2006.259.07:51:12.94#ibcon#read 5, iclass 34, count 0 2006.259.07:51:12.94#ibcon#about to read 6, iclass 34, count 0 2006.259.07:51:12.94#ibcon#read 6, iclass 34, count 0 2006.259.07:51:12.94#ibcon#end of sib2, iclass 34, count 0 2006.259.07:51:12.94#ibcon#*after write, iclass 34, count 0 2006.259.07:51:12.94#ibcon#*before return 0, iclass 34, count 0 2006.259.07:51:12.94#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.259.07:51:12.94#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.259.07:51:12.94#ibcon#about to clear, iclass 34 cls_cnt 0 2006.259.07:51:12.94#ibcon#cleared, iclass 34 cls_cnt 0 2006.259.07:51:12.94$vc4f8/vb=4,5 2006.259.07:51:12.94#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.259.07:51:12.94#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.259.07:51:12.94#ibcon#ireg 11 cls_cnt 2 2006.259.07:51:12.94#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.259.07:51:13.00#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.259.07:51:13.00#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.259.07:51:13.00#ibcon#enter wrdev, iclass 36, count 2 2006.259.07:51:13.00#ibcon#first serial, iclass 36, count 2 2006.259.07:51:13.00#ibcon#enter sib2, iclass 36, count 2 2006.259.07:51:13.00#ibcon#flushed, iclass 36, count 2 2006.259.07:51:13.00#ibcon#about to write, iclass 36, count 2 2006.259.07:51:13.00#ibcon#wrote, iclass 36, count 2 2006.259.07:51:13.00#ibcon#about to read 3, iclass 36, count 2 2006.259.07:51:13.02#ibcon#read 3, iclass 36, count 2 2006.259.07:51:13.02#ibcon#about to read 4, iclass 36, count 2 2006.259.07:51:13.02#ibcon#read 4, iclass 36, count 2 2006.259.07:51:13.02#ibcon#about to read 5, iclass 36, count 2 2006.259.07:51:13.02#ibcon#read 5, iclass 36, count 2 2006.259.07:51:13.02#ibcon#about to read 6, iclass 36, count 2 2006.259.07:51:13.02#ibcon#read 6, iclass 36, count 2 2006.259.07:51:13.02#ibcon#end of sib2, iclass 36, count 2 2006.259.07:51:13.02#ibcon#*mode == 0, iclass 36, count 2 2006.259.07:51:13.02#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.259.07:51:13.02#ibcon#[27=AT04-05\r\n] 2006.259.07:51:13.02#ibcon#*before write, iclass 36, count 2 2006.259.07:51:13.02#ibcon#enter sib2, iclass 36, count 2 2006.259.07:51:13.02#ibcon#flushed, iclass 36, count 2 2006.259.07:51:13.02#ibcon#about to write, iclass 36, count 2 2006.259.07:51:13.02#ibcon#wrote, iclass 36, count 2 2006.259.07:51:13.02#ibcon#about to read 3, iclass 36, count 2 2006.259.07:51:13.05#ibcon#read 3, iclass 36, count 2 2006.259.07:51:13.05#ibcon#about to read 4, iclass 36, count 2 2006.259.07:51:13.05#ibcon#read 4, iclass 36, count 2 2006.259.07:51:13.05#ibcon#about to read 5, iclass 36, count 2 2006.259.07:51:13.05#ibcon#read 5, iclass 36, count 2 2006.259.07:51:13.05#ibcon#about to read 6, iclass 36, count 2 2006.259.07:51:13.05#ibcon#read 6, iclass 36, count 2 2006.259.07:51:13.05#ibcon#end of sib2, iclass 36, count 2 2006.259.07:51:13.05#ibcon#*after write, iclass 36, count 2 2006.259.07:51:13.05#ibcon#*before return 0, iclass 36, count 2 2006.259.07:51:13.05#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.259.07:51:13.05#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.259.07:51:13.05#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.259.07:51:13.05#ibcon#ireg 7 cls_cnt 0 2006.259.07:51:13.05#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.259.07:51:13.16#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.259.07:51:13.17#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.259.07:51:13.17#ibcon#enter wrdev, iclass 36, count 0 2006.259.07:51:13.17#ibcon#first serial, iclass 36, count 0 2006.259.07:51:13.17#ibcon#enter sib2, iclass 36, count 0 2006.259.07:51:13.17#ibcon#flushed, iclass 36, count 0 2006.259.07:51:13.17#ibcon#about to write, iclass 36, count 0 2006.259.07:51:13.17#ibcon#wrote, iclass 36, count 0 2006.259.07:51:13.17#ibcon#about to read 3, iclass 36, count 0 2006.259.07:51:13.19#ibcon#read 3, iclass 36, count 0 2006.259.07:51:13.19#ibcon#about to read 4, iclass 36, count 0 2006.259.07:51:13.19#ibcon#read 4, iclass 36, count 0 2006.259.07:51:13.19#ibcon#about to read 5, iclass 36, count 0 2006.259.07:51:13.19#ibcon#read 5, iclass 36, count 0 2006.259.07:51:13.19#ibcon#about to read 6, iclass 36, count 0 2006.259.07:51:13.19#ibcon#read 6, iclass 36, count 0 2006.259.07:51:13.19#ibcon#end of sib2, iclass 36, count 0 2006.259.07:51:13.19#ibcon#*mode == 0, iclass 36, count 0 2006.259.07:51:13.19#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.259.07:51:13.19#ibcon#[27=USB\r\n] 2006.259.07:51:13.19#ibcon#*before write, iclass 36, count 0 2006.259.07:51:13.19#ibcon#enter sib2, iclass 36, count 0 2006.259.07:51:13.19#ibcon#flushed, iclass 36, count 0 2006.259.07:51:13.19#ibcon#about to write, iclass 36, count 0 2006.259.07:51:13.19#ibcon#wrote, iclass 36, count 0 2006.259.07:51:13.19#ibcon#about to read 3, iclass 36, count 0 2006.259.07:51:13.22#ibcon#read 3, iclass 36, count 0 2006.259.07:51:13.22#ibcon#about to read 4, iclass 36, count 0 2006.259.07:51:13.22#ibcon#read 4, iclass 36, count 0 2006.259.07:51:13.22#ibcon#about to read 5, iclass 36, count 0 2006.259.07:51:13.22#ibcon#read 5, iclass 36, count 0 2006.259.07:51:13.22#ibcon#about to read 6, iclass 36, count 0 2006.259.07:51:13.22#ibcon#read 6, iclass 36, count 0 2006.259.07:51:13.22#ibcon#end of sib2, iclass 36, count 0 2006.259.07:51:13.22#ibcon#*after write, iclass 36, count 0 2006.259.07:51:13.22#ibcon#*before return 0, iclass 36, count 0 2006.259.07:51:13.22#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.259.07:51:13.22#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.259.07:51:13.22#ibcon#about to clear, iclass 36 cls_cnt 0 2006.259.07:51:13.22#ibcon#cleared, iclass 36 cls_cnt 0 2006.259.07:51:13.22$vc4f8/vblo=5,744.99 2006.259.07:51:13.22#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.259.07:51:13.22#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.259.07:51:13.22#ibcon#ireg 17 cls_cnt 0 2006.259.07:51:13.22#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.259.07:51:13.22#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.259.07:51:13.22#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.259.07:51:13.22#ibcon#enter wrdev, iclass 38, count 0 2006.259.07:51:13.22#ibcon#first serial, iclass 38, count 0 2006.259.07:51:13.22#ibcon#enter sib2, iclass 38, count 0 2006.259.07:51:13.22#ibcon#flushed, iclass 38, count 0 2006.259.07:51:13.22#ibcon#about to write, iclass 38, count 0 2006.259.07:51:13.22#ibcon#wrote, iclass 38, count 0 2006.259.07:51:13.22#ibcon#about to read 3, iclass 38, count 0 2006.259.07:51:13.24#ibcon#read 3, iclass 38, count 0 2006.259.07:51:13.24#ibcon#about to read 4, iclass 38, count 0 2006.259.07:51:13.24#ibcon#read 4, iclass 38, count 0 2006.259.07:51:13.24#ibcon#about to read 5, iclass 38, count 0 2006.259.07:51:13.24#ibcon#read 5, iclass 38, count 0 2006.259.07:51:13.24#ibcon#about to read 6, iclass 38, count 0 2006.259.07:51:13.24#ibcon#read 6, iclass 38, count 0 2006.259.07:51:13.24#ibcon#end of sib2, iclass 38, count 0 2006.259.07:51:13.24#ibcon#*mode == 0, iclass 38, count 0 2006.259.07:51:13.24#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.259.07:51:13.24#ibcon#[28=FRQ=05,744.99\r\n] 2006.259.07:51:13.24#ibcon#*before write, iclass 38, count 0 2006.259.07:51:13.24#ibcon#enter sib2, iclass 38, count 0 2006.259.07:51:13.24#ibcon#flushed, iclass 38, count 0 2006.259.07:51:13.24#ibcon#about to write, iclass 38, count 0 2006.259.07:51:13.24#ibcon#wrote, iclass 38, count 0 2006.259.07:51:13.24#ibcon#about to read 3, iclass 38, count 0 2006.259.07:51:13.28#ibcon#read 3, iclass 38, count 0 2006.259.07:51:13.28#ibcon#about to read 4, iclass 38, count 0 2006.259.07:51:13.28#ibcon#read 4, iclass 38, count 0 2006.259.07:51:13.28#ibcon#about to read 5, iclass 38, count 0 2006.259.07:51:13.28#ibcon#read 5, iclass 38, count 0 2006.259.07:51:13.28#ibcon#about to read 6, iclass 38, count 0 2006.259.07:51:13.28#ibcon#read 6, iclass 38, count 0 2006.259.07:51:13.28#ibcon#end of sib2, iclass 38, count 0 2006.259.07:51:13.28#ibcon#*after write, iclass 38, count 0 2006.259.07:51:13.28#ibcon#*before return 0, iclass 38, count 0 2006.259.07:51:13.28#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.259.07:51:13.28#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.259.07:51:13.28#ibcon#about to clear, iclass 38 cls_cnt 0 2006.259.07:51:13.28#ibcon#cleared, iclass 38 cls_cnt 0 2006.259.07:51:13.28$vc4f8/vb=5,4 2006.259.07:51:13.28#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.259.07:51:13.28#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.259.07:51:13.28#ibcon#ireg 11 cls_cnt 2 2006.259.07:51:13.28#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.259.07:51:13.34#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.259.07:51:13.34#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.259.07:51:13.34#ibcon#enter wrdev, iclass 40, count 2 2006.259.07:51:13.34#ibcon#first serial, iclass 40, count 2 2006.259.07:51:13.34#ibcon#enter sib2, iclass 40, count 2 2006.259.07:51:13.34#ibcon#flushed, iclass 40, count 2 2006.259.07:51:13.34#ibcon#about to write, iclass 40, count 2 2006.259.07:51:13.34#ibcon#wrote, iclass 40, count 2 2006.259.07:51:13.34#ibcon#about to read 3, iclass 40, count 2 2006.259.07:51:13.36#ibcon#read 3, iclass 40, count 2 2006.259.07:51:13.36#ibcon#about to read 4, iclass 40, count 2 2006.259.07:51:13.36#ibcon#read 4, iclass 40, count 2 2006.259.07:51:13.36#ibcon#about to read 5, iclass 40, count 2 2006.259.07:51:13.36#ibcon#read 5, iclass 40, count 2 2006.259.07:51:13.36#ibcon#about to read 6, iclass 40, count 2 2006.259.07:51:13.36#ibcon#read 6, iclass 40, count 2 2006.259.07:51:13.36#ibcon#end of sib2, iclass 40, count 2 2006.259.07:51:13.36#ibcon#*mode == 0, iclass 40, count 2 2006.259.07:51:13.36#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.259.07:51:13.36#ibcon#[27=AT05-04\r\n] 2006.259.07:51:13.36#ibcon#*before write, iclass 40, count 2 2006.259.07:51:13.36#ibcon#enter sib2, iclass 40, count 2 2006.259.07:51:13.36#ibcon#flushed, iclass 40, count 2 2006.259.07:51:13.36#ibcon#about to write, iclass 40, count 2 2006.259.07:51:13.36#ibcon#wrote, iclass 40, count 2 2006.259.07:51:13.36#ibcon#about to read 3, iclass 40, count 2 2006.259.07:51:13.39#ibcon#read 3, iclass 40, count 2 2006.259.07:51:13.39#ibcon#about to read 4, iclass 40, count 2 2006.259.07:51:13.39#ibcon#read 4, iclass 40, count 2 2006.259.07:51:13.39#ibcon#about to read 5, iclass 40, count 2 2006.259.07:51:13.39#ibcon#read 5, iclass 40, count 2 2006.259.07:51:13.39#ibcon#about to read 6, iclass 40, count 2 2006.259.07:51:13.39#ibcon#read 6, iclass 40, count 2 2006.259.07:51:13.39#ibcon#end of sib2, iclass 40, count 2 2006.259.07:51:13.39#ibcon#*after write, iclass 40, count 2 2006.259.07:51:13.39#ibcon#*before return 0, iclass 40, count 2 2006.259.07:51:13.39#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.259.07:51:13.39#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.259.07:51:13.39#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.259.07:51:13.39#ibcon#ireg 7 cls_cnt 0 2006.259.07:51:13.39#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.259.07:51:13.50#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.259.07:51:13.51#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.259.07:51:13.51#ibcon#enter wrdev, iclass 40, count 0 2006.259.07:51:13.51#ibcon#first serial, iclass 40, count 0 2006.259.07:51:13.51#ibcon#enter sib2, iclass 40, count 0 2006.259.07:51:13.51#ibcon#flushed, iclass 40, count 0 2006.259.07:51:13.51#ibcon#about to write, iclass 40, count 0 2006.259.07:51:13.51#ibcon#wrote, iclass 40, count 0 2006.259.07:51:13.51#ibcon#about to read 3, iclass 40, count 0 2006.259.07:51:13.53#ibcon#read 3, iclass 40, count 0 2006.259.07:51:13.53#ibcon#about to read 4, iclass 40, count 0 2006.259.07:51:13.53#ibcon#read 4, iclass 40, count 0 2006.259.07:51:13.53#ibcon#about to read 5, iclass 40, count 0 2006.259.07:51:13.53#ibcon#read 5, iclass 40, count 0 2006.259.07:51:13.53#ibcon#about to read 6, iclass 40, count 0 2006.259.07:51:13.53#ibcon#read 6, iclass 40, count 0 2006.259.07:51:13.53#ibcon#end of sib2, iclass 40, count 0 2006.259.07:51:13.53#ibcon#*mode == 0, iclass 40, count 0 2006.259.07:51:13.53#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.259.07:51:13.53#ibcon#[27=USB\r\n] 2006.259.07:51:13.53#ibcon#*before write, iclass 40, count 0 2006.259.07:51:13.53#ibcon#enter sib2, iclass 40, count 0 2006.259.07:51:13.53#ibcon#flushed, iclass 40, count 0 2006.259.07:51:13.53#ibcon#about to write, iclass 40, count 0 2006.259.07:51:13.53#ibcon#wrote, iclass 40, count 0 2006.259.07:51:13.53#ibcon#about to read 3, iclass 40, count 0 2006.259.07:51:13.56#ibcon#read 3, iclass 40, count 0 2006.259.07:51:13.56#ibcon#about to read 4, iclass 40, count 0 2006.259.07:51:13.56#ibcon#read 4, iclass 40, count 0 2006.259.07:51:13.56#ibcon#about to read 5, iclass 40, count 0 2006.259.07:51:13.56#ibcon#read 5, iclass 40, count 0 2006.259.07:51:13.56#ibcon#about to read 6, iclass 40, count 0 2006.259.07:51:13.56#ibcon#read 6, iclass 40, count 0 2006.259.07:51:13.56#ibcon#end of sib2, iclass 40, count 0 2006.259.07:51:13.56#ibcon#*after write, iclass 40, count 0 2006.259.07:51:13.56#ibcon#*before return 0, iclass 40, count 0 2006.259.07:51:13.56#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.259.07:51:13.56#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.259.07:51:13.56#ibcon#about to clear, iclass 40 cls_cnt 0 2006.259.07:51:13.56#ibcon#cleared, iclass 40 cls_cnt 0 2006.259.07:51:13.56$vc4f8/vblo=6,752.99 2006.259.07:51:13.56#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.259.07:51:13.56#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.259.07:51:13.56#ibcon#ireg 17 cls_cnt 0 2006.259.07:51:13.56#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.259.07:51:13.56#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.259.07:51:13.56#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.259.07:51:13.56#ibcon#enter wrdev, iclass 4, count 0 2006.259.07:51:13.56#ibcon#first serial, iclass 4, count 0 2006.259.07:51:13.56#ibcon#enter sib2, iclass 4, count 0 2006.259.07:51:13.56#ibcon#flushed, iclass 4, count 0 2006.259.07:51:13.56#ibcon#about to write, iclass 4, count 0 2006.259.07:51:13.56#ibcon#wrote, iclass 4, count 0 2006.259.07:51:13.56#ibcon#about to read 3, iclass 4, count 0 2006.259.07:51:13.58#ibcon#read 3, iclass 4, count 0 2006.259.07:51:13.58#ibcon#about to read 4, iclass 4, count 0 2006.259.07:51:13.58#ibcon#read 4, iclass 4, count 0 2006.259.07:51:13.58#ibcon#about to read 5, iclass 4, count 0 2006.259.07:51:13.58#ibcon#read 5, iclass 4, count 0 2006.259.07:51:13.58#ibcon#about to read 6, iclass 4, count 0 2006.259.07:51:13.58#ibcon#read 6, iclass 4, count 0 2006.259.07:51:13.58#ibcon#end of sib2, iclass 4, count 0 2006.259.07:51:13.58#ibcon#*mode == 0, iclass 4, count 0 2006.259.07:51:13.58#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.259.07:51:13.58#ibcon#[28=FRQ=06,752.99\r\n] 2006.259.07:51:13.58#ibcon#*before write, iclass 4, count 0 2006.259.07:51:13.58#ibcon#enter sib2, iclass 4, count 0 2006.259.07:51:13.58#ibcon#flushed, iclass 4, count 0 2006.259.07:51:13.58#ibcon#about to write, iclass 4, count 0 2006.259.07:51:13.58#ibcon#wrote, iclass 4, count 0 2006.259.07:51:13.58#ibcon#about to read 3, iclass 4, count 0 2006.259.07:51:13.62#ibcon#read 3, iclass 4, count 0 2006.259.07:51:13.62#ibcon#about to read 4, iclass 4, count 0 2006.259.07:51:13.62#ibcon#read 4, iclass 4, count 0 2006.259.07:51:13.62#ibcon#about to read 5, iclass 4, count 0 2006.259.07:51:13.62#ibcon#read 5, iclass 4, count 0 2006.259.07:51:13.62#ibcon#about to read 6, iclass 4, count 0 2006.259.07:51:13.62#ibcon#read 6, iclass 4, count 0 2006.259.07:51:13.62#ibcon#end of sib2, iclass 4, count 0 2006.259.07:51:13.62#ibcon#*after write, iclass 4, count 0 2006.259.07:51:13.62#ibcon#*before return 0, iclass 4, count 0 2006.259.07:51:13.62#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.259.07:51:13.62#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.259.07:51:13.62#ibcon#about to clear, iclass 4 cls_cnt 0 2006.259.07:51:13.62#ibcon#cleared, iclass 4 cls_cnt 0 2006.259.07:51:13.62$vc4f8/vb=6,4 2006.259.07:51:13.62#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.259.07:51:13.62#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.259.07:51:13.62#ibcon#ireg 11 cls_cnt 2 2006.259.07:51:13.62#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.259.07:51:13.67#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.259.07:51:13.68#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.259.07:51:13.68#ibcon#enter wrdev, iclass 6, count 2 2006.259.07:51:13.68#ibcon#first serial, iclass 6, count 2 2006.259.07:51:13.68#ibcon#enter sib2, iclass 6, count 2 2006.259.07:51:13.68#ibcon#flushed, iclass 6, count 2 2006.259.07:51:13.68#ibcon#about to write, iclass 6, count 2 2006.259.07:51:13.68#ibcon#wrote, iclass 6, count 2 2006.259.07:51:13.68#ibcon#about to read 3, iclass 6, count 2 2006.259.07:51:13.70#ibcon#read 3, iclass 6, count 2 2006.259.07:51:13.70#ibcon#about to read 4, iclass 6, count 2 2006.259.07:51:13.70#ibcon#read 4, iclass 6, count 2 2006.259.07:51:13.70#ibcon#about to read 5, iclass 6, count 2 2006.259.07:51:13.70#ibcon#read 5, iclass 6, count 2 2006.259.07:51:13.70#ibcon#about to read 6, iclass 6, count 2 2006.259.07:51:13.70#ibcon#read 6, iclass 6, count 2 2006.259.07:51:13.70#ibcon#end of sib2, iclass 6, count 2 2006.259.07:51:13.70#ibcon#*mode == 0, iclass 6, count 2 2006.259.07:51:13.70#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.259.07:51:13.70#ibcon#[27=AT06-04\r\n] 2006.259.07:51:13.70#ibcon#*before write, iclass 6, count 2 2006.259.07:51:13.70#ibcon#enter sib2, iclass 6, count 2 2006.259.07:51:13.70#ibcon#flushed, iclass 6, count 2 2006.259.07:51:13.70#ibcon#about to write, iclass 6, count 2 2006.259.07:51:13.70#ibcon#wrote, iclass 6, count 2 2006.259.07:51:13.70#ibcon#about to read 3, iclass 6, count 2 2006.259.07:51:13.73#ibcon#read 3, iclass 6, count 2 2006.259.07:51:13.73#ibcon#about to read 4, iclass 6, count 2 2006.259.07:51:13.73#ibcon#read 4, iclass 6, count 2 2006.259.07:51:13.73#ibcon#about to read 5, iclass 6, count 2 2006.259.07:51:13.73#ibcon#read 5, iclass 6, count 2 2006.259.07:51:13.73#ibcon#about to read 6, iclass 6, count 2 2006.259.07:51:13.73#ibcon#read 6, iclass 6, count 2 2006.259.07:51:13.73#ibcon#end of sib2, iclass 6, count 2 2006.259.07:51:13.73#ibcon#*after write, iclass 6, count 2 2006.259.07:51:13.73#ibcon#*before return 0, iclass 6, count 2 2006.259.07:51:13.73#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.259.07:51:13.73#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.259.07:51:13.73#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.259.07:51:13.73#ibcon#ireg 7 cls_cnt 0 2006.259.07:51:13.73#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.259.07:51:13.84#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.259.07:51:13.85#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.259.07:51:13.85#ibcon#enter wrdev, iclass 6, count 0 2006.259.07:51:13.85#ibcon#first serial, iclass 6, count 0 2006.259.07:51:13.85#ibcon#enter sib2, iclass 6, count 0 2006.259.07:51:13.85#ibcon#flushed, iclass 6, count 0 2006.259.07:51:13.85#ibcon#about to write, iclass 6, count 0 2006.259.07:51:13.85#ibcon#wrote, iclass 6, count 0 2006.259.07:51:13.85#ibcon#about to read 3, iclass 6, count 0 2006.259.07:51:13.87#ibcon#read 3, iclass 6, count 0 2006.259.07:51:13.87#ibcon#about to read 4, iclass 6, count 0 2006.259.07:51:13.87#ibcon#read 4, iclass 6, count 0 2006.259.07:51:13.87#ibcon#about to read 5, iclass 6, count 0 2006.259.07:51:13.87#ibcon#read 5, iclass 6, count 0 2006.259.07:51:13.87#ibcon#about to read 6, iclass 6, count 0 2006.259.07:51:13.87#ibcon#read 6, iclass 6, count 0 2006.259.07:51:13.87#ibcon#end of sib2, iclass 6, count 0 2006.259.07:51:13.87#ibcon#*mode == 0, iclass 6, count 0 2006.259.07:51:13.87#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.259.07:51:13.87#ibcon#[27=USB\r\n] 2006.259.07:51:13.87#ibcon#*before write, iclass 6, count 0 2006.259.07:51:13.87#ibcon#enter sib2, iclass 6, count 0 2006.259.07:51:13.87#ibcon#flushed, iclass 6, count 0 2006.259.07:51:13.87#ibcon#about to write, iclass 6, count 0 2006.259.07:51:13.87#ibcon#wrote, iclass 6, count 0 2006.259.07:51:13.87#ibcon#about to read 3, iclass 6, count 0 2006.259.07:51:13.90#ibcon#read 3, iclass 6, count 0 2006.259.07:51:13.90#ibcon#about to read 4, iclass 6, count 0 2006.259.07:51:13.90#ibcon#read 4, iclass 6, count 0 2006.259.07:51:13.90#ibcon#about to read 5, iclass 6, count 0 2006.259.07:51:13.90#ibcon#read 5, iclass 6, count 0 2006.259.07:51:13.90#ibcon#about to read 6, iclass 6, count 0 2006.259.07:51:13.90#ibcon#read 6, iclass 6, count 0 2006.259.07:51:13.90#ibcon#end of sib2, iclass 6, count 0 2006.259.07:51:13.90#ibcon#*after write, iclass 6, count 0 2006.259.07:51:13.90#ibcon#*before return 0, iclass 6, count 0 2006.259.07:51:13.90#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.259.07:51:13.90#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.259.07:51:13.90#ibcon#about to clear, iclass 6 cls_cnt 0 2006.259.07:51:13.90#ibcon#cleared, iclass 6 cls_cnt 0 2006.259.07:51:13.90$vc4f8/vabw=wide 2006.259.07:51:13.90#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.259.07:51:13.90#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.259.07:51:13.90#ibcon#ireg 8 cls_cnt 0 2006.259.07:51:13.90#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.259.07:51:13.90#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.259.07:51:13.90#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.259.07:51:13.90#ibcon#enter wrdev, iclass 10, count 0 2006.259.07:51:13.90#ibcon#first serial, iclass 10, count 0 2006.259.07:51:13.90#ibcon#enter sib2, iclass 10, count 0 2006.259.07:51:13.90#ibcon#flushed, iclass 10, count 0 2006.259.07:51:13.90#ibcon#about to write, iclass 10, count 0 2006.259.07:51:13.90#ibcon#wrote, iclass 10, count 0 2006.259.07:51:13.90#ibcon#about to read 3, iclass 10, count 0 2006.259.07:51:13.92#ibcon#read 3, iclass 10, count 0 2006.259.07:51:13.92#ibcon#about to read 4, iclass 10, count 0 2006.259.07:51:13.92#ibcon#read 4, iclass 10, count 0 2006.259.07:51:13.92#ibcon#about to read 5, iclass 10, count 0 2006.259.07:51:13.92#ibcon#read 5, iclass 10, count 0 2006.259.07:51:13.92#ibcon#about to read 6, iclass 10, count 0 2006.259.07:51:13.92#ibcon#read 6, iclass 10, count 0 2006.259.07:51:13.92#ibcon#end of sib2, iclass 10, count 0 2006.259.07:51:13.92#ibcon#*mode == 0, iclass 10, count 0 2006.259.07:51:13.92#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.259.07:51:13.92#ibcon#[25=BW32\r\n] 2006.259.07:51:13.92#ibcon#*before write, iclass 10, count 0 2006.259.07:51:13.92#ibcon#enter sib2, iclass 10, count 0 2006.259.07:51:13.92#ibcon#flushed, iclass 10, count 0 2006.259.07:51:13.92#ibcon#about to write, iclass 10, count 0 2006.259.07:51:13.92#ibcon#wrote, iclass 10, count 0 2006.259.07:51:13.92#ibcon#about to read 3, iclass 10, count 0 2006.259.07:51:13.95#ibcon#read 3, iclass 10, count 0 2006.259.07:51:13.95#ibcon#about to read 4, iclass 10, count 0 2006.259.07:51:13.95#ibcon#read 4, iclass 10, count 0 2006.259.07:51:13.95#ibcon#about to read 5, iclass 10, count 0 2006.259.07:51:13.95#ibcon#read 5, iclass 10, count 0 2006.259.07:51:13.95#ibcon#about to read 6, iclass 10, count 0 2006.259.07:51:13.95#ibcon#read 6, iclass 10, count 0 2006.259.07:51:13.95#ibcon#end of sib2, iclass 10, count 0 2006.259.07:51:13.95#ibcon#*after write, iclass 10, count 0 2006.259.07:51:13.95#ibcon#*before return 0, iclass 10, count 0 2006.259.07:51:13.95#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.259.07:51:13.95#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.259.07:51:13.95#ibcon#about to clear, iclass 10 cls_cnt 0 2006.259.07:51:13.95#ibcon#cleared, iclass 10 cls_cnt 0 2006.259.07:51:13.95$vc4f8/vbbw=wide 2006.259.07:51:13.95#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.259.07:51:13.95#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.259.07:51:13.95#ibcon#ireg 8 cls_cnt 0 2006.259.07:51:13.95#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.259.07:51:14.01#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.259.07:51:14.02#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.259.07:51:14.02#ibcon#enter wrdev, iclass 12, count 0 2006.259.07:51:14.02#ibcon#first serial, iclass 12, count 0 2006.259.07:51:14.02#ibcon#enter sib2, iclass 12, count 0 2006.259.07:51:14.02#ibcon#flushed, iclass 12, count 0 2006.259.07:51:14.02#ibcon#about to write, iclass 12, count 0 2006.259.07:51:14.02#ibcon#wrote, iclass 12, count 0 2006.259.07:51:14.02#ibcon#about to read 3, iclass 12, count 0 2006.259.07:51:14.04#ibcon#read 3, iclass 12, count 0 2006.259.07:51:14.04#ibcon#about to read 4, iclass 12, count 0 2006.259.07:51:14.04#ibcon#read 4, iclass 12, count 0 2006.259.07:51:14.04#ibcon#about to read 5, iclass 12, count 0 2006.259.07:51:14.04#ibcon#read 5, iclass 12, count 0 2006.259.07:51:14.04#ibcon#about to read 6, iclass 12, count 0 2006.259.07:51:14.04#ibcon#read 6, iclass 12, count 0 2006.259.07:51:14.04#ibcon#end of sib2, iclass 12, count 0 2006.259.07:51:14.04#ibcon#*mode == 0, iclass 12, count 0 2006.259.07:51:14.04#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.259.07:51:14.04#ibcon#[27=BW32\r\n] 2006.259.07:51:14.04#ibcon#*before write, iclass 12, count 0 2006.259.07:51:14.04#ibcon#enter sib2, iclass 12, count 0 2006.259.07:51:14.04#ibcon#flushed, iclass 12, count 0 2006.259.07:51:14.04#ibcon#about to write, iclass 12, count 0 2006.259.07:51:14.04#ibcon#wrote, iclass 12, count 0 2006.259.07:51:14.04#ibcon#about to read 3, iclass 12, count 0 2006.259.07:51:14.07#ibcon#read 3, iclass 12, count 0 2006.259.07:51:14.07#ibcon#about to read 4, iclass 12, count 0 2006.259.07:51:14.07#ibcon#read 4, iclass 12, count 0 2006.259.07:51:14.07#ibcon#about to read 5, iclass 12, count 0 2006.259.07:51:14.07#ibcon#read 5, iclass 12, count 0 2006.259.07:51:14.07#ibcon#about to read 6, iclass 12, count 0 2006.259.07:51:14.07#ibcon#read 6, iclass 12, count 0 2006.259.07:51:14.07#ibcon#end of sib2, iclass 12, count 0 2006.259.07:51:14.07#ibcon#*after write, iclass 12, count 0 2006.259.07:51:14.07#ibcon#*before return 0, iclass 12, count 0 2006.259.07:51:14.07#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.259.07:51:14.07#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.259.07:51:14.07#ibcon#about to clear, iclass 12 cls_cnt 0 2006.259.07:51:14.07#ibcon#cleared, iclass 12 cls_cnt 0 2006.259.07:51:14.07$4f8m12a/ifd4f 2006.259.07:51:14.07$ifd4f/lo= 2006.259.07:51:14.07$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.259.07:51:14.07$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.259.07:51:14.07$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.259.07:51:14.07$ifd4f/patch= 2006.259.07:51:14.07$ifd4f/patch=lo1,a1,a2,a3,a4 2006.259.07:51:14.07$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.259.07:51:14.07$ifd4f/patch=lo3,a5,a6,a7,a8 2006.259.07:51:14.07$4f8m12a/"form=m,16.000,1:2 2006.259.07:51:14.07$4f8m12a/"tpicd 2006.259.07:51:14.07$4f8m12a/echo=off 2006.259.07:51:14.07$4f8m12a/xlog=off 2006.259.07:51:14.07:!2006.259.07:51:40 2006.259.07:51:23.13#trakl#Source acquired 2006.259.07:51:25.14#flagr#flagr/antenna,acquired 2006.259.07:51:40.02:preob 2006.259.07:51:41.14/onsource/TRACKING 2006.259.07:51:41.14:!2006.259.07:51:50 2006.259.07:51:50.02:data_valid=on 2006.259.07:51:50.02:midob 2006.259.07:51:51.15/onsource/TRACKING 2006.259.07:51:51.15/wx/22.21,1013.0,86 2006.259.07:51:51.31/cable/+6.4580E-03 2006.259.07:51:52.40/va/01,08,usb,yes,30,32 2006.259.07:51:52.40/va/02,07,usb,yes,30,32 2006.259.07:51:52.40/va/03,08,usb,yes,23,23 2006.259.07:51:52.40/va/04,07,usb,yes,31,34 2006.259.07:51:52.40/va/05,07,usb,yes,35,37 2006.259.07:51:52.40/va/06,06,usb,yes,34,34 2006.259.07:51:52.40/va/07,06,usb,yes,35,35 2006.259.07:51:52.40/va/08,06,usb,yes,37,36 2006.259.07:51:52.63/valo/01,532.99,yes,locked 2006.259.07:51:52.63/valo/02,572.99,yes,locked 2006.259.07:51:52.63/valo/03,672.99,yes,locked 2006.259.07:51:52.63/valo/04,832.99,yes,locked 2006.259.07:51:52.63/valo/05,652.99,yes,locked 2006.259.07:51:52.63/valo/06,772.99,yes,locked 2006.259.07:51:52.63/valo/07,832.99,yes,locked 2006.259.07:51:52.63/valo/08,852.99,yes,locked 2006.259.07:51:53.72/vb/01,04,usb,yes,30,29 2006.259.07:51:53.72/vb/02,05,usb,yes,28,29 2006.259.07:51:53.72/vb/03,04,usb,yes,28,32 2006.259.07:51:53.72/vb/04,05,usb,yes,26,26 2006.259.07:51:53.72/vb/05,04,usb,yes,27,31 2006.259.07:51:53.72/vb/06,04,usb,yes,28,31 2006.259.07:51:53.72/vb/07,04,usb,yes,30,30 2006.259.07:51:53.72/vb/08,04,usb,yes,28,31 2006.259.07:51:53.95/vblo/01,632.99,yes,locked 2006.259.07:51:53.95/vblo/02,640.99,yes,locked 2006.259.07:51:53.95/vblo/03,656.99,yes,locked 2006.259.07:51:53.95/vblo/04,712.99,yes,locked 2006.259.07:51:53.95/vblo/05,744.99,yes,locked 2006.259.07:51:53.95/vblo/06,752.99,yes,locked 2006.259.07:51:53.95/vblo/07,734.99,yes,locked 2006.259.07:51:53.95/vblo/08,744.99,yes,locked 2006.259.07:51:54.09/vabw/8 2006.259.07:51:54.24/vbbw/8 2006.259.07:51:54.34/xfe/off,on,15.0 2006.259.07:51:54.71/ifatt/23,28,28,28 2006.259.07:51:55.08/fmout-gps/S +4.52E-07 2006.259.07:51:55.12:!2006.259.07:52:50 2006.259.07:52:50.02:data_valid=off 2006.259.07:52:50.02:postob 2006.259.07:52:50.11/cable/+6.4583E-03 2006.259.07:52:50.12/wx/22.20,1013.0,86 2006.259.07:52:51.07/fmout-gps/S +4.53E-07 2006.259.07:52:51.08:scan_name=259-0754,k06259,60 2006.259.07:52:51.08:source=0059+581,010245.76,582411.1,2000.0,cw 2006.259.07:52:52.14#flagr#flagr/antenna,new-source 2006.259.07:52:52.14:checkk5 2006.259.07:52:52.58/chk_autoobs//k5ts1/ autoobs is running! 2006.259.07:52:52.99/chk_autoobs//k5ts2/ autoobs is running! 2006.259.07:52:53.40/chk_autoobs//k5ts3/ autoobs is running! 2006.259.07:52:53.79/chk_autoobs//k5ts4/ autoobs is running! 2006.259.07:52:54.40/chk_obsdata//k5ts1/T2590751??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.259.07:52:54.82/chk_obsdata//k5ts2/T2590751??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.259.07:52:55.24/chk_obsdata//k5ts3/T2590751??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.259.07:52:55.68/chk_obsdata//k5ts4/T2590751??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.259.07:52:56.49/k5log//k5ts1_log_newline 2006.259.07:52:57.29/k5log//k5ts2_log_newline 2006.259.07:52:58.07/k5log//k5ts3_log_newline 2006.259.07:52:58.84/k5log//k5ts4_log_newline 2006.259.07:52:58.86/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.259.07:52:58.86:4f8m12a=2 2006.259.07:52:58.86$4f8m12a/echo=on 2006.259.07:52:58.86$4f8m12a/pcalon 2006.259.07:52:58.86$pcalon/"no phase cal control is implemented here 2006.259.07:52:58.86$4f8m12a/"tpicd=stop 2006.259.07:52:58.87$4f8m12a/vc4f8 2006.259.07:52:58.87$vc4f8/valo=1,532.99 2006.259.07:52:58.87#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.259.07:52:58.87#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.259.07:52:58.87#ibcon#ireg 17 cls_cnt 0 2006.259.07:52:58.87#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.259.07:52:58.87#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.259.07:52:58.87#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.259.07:52:58.87#ibcon#enter wrdev, iclass 19, count 0 2006.259.07:52:58.87#ibcon#first serial, iclass 19, count 0 2006.259.07:52:58.87#ibcon#enter sib2, iclass 19, count 0 2006.259.07:52:58.87#ibcon#flushed, iclass 19, count 0 2006.259.07:52:58.87#ibcon#about to write, iclass 19, count 0 2006.259.07:52:58.87#ibcon#wrote, iclass 19, count 0 2006.259.07:52:58.87#ibcon#about to read 3, iclass 19, count 0 2006.259.07:52:58.91#ibcon#read 3, iclass 19, count 0 2006.259.07:52:58.91#ibcon#about to read 4, iclass 19, count 0 2006.259.07:52:58.91#ibcon#read 4, iclass 19, count 0 2006.259.07:52:58.91#ibcon#about to read 5, iclass 19, count 0 2006.259.07:52:58.91#ibcon#read 5, iclass 19, count 0 2006.259.07:52:58.91#ibcon#about to read 6, iclass 19, count 0 2006.259.07:52:58.91#ibcon#read 6, iclass 19, count 0 2006.259.07:52:58.91#ibcon#end of sib2, iclass 19, count 0 2006.259.07:52:58.91#ibcon#*mode == 0, iclass 19, count 0 2006.259.07:52:58.91#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.259.07:52:58.91#ibcon#[26=FRQ=01,532.99\r\n] 2006.259.07:52:58.91#ibcon#*before write, iclass 19, count 0 2006.259.07:52:58.91#ibcon#enter sib2, iclass 19, count 0 2006.259.07:52:58.91#ibcon#flushed, iclass 19, count 0 2006.259.07:52:58.91#ibcon#about to write, iclass 19, count 0 2006.259.07:52:58.91#ibcon#wrote, iclass 19, count 0 2006.259.07:52:58.91#ibcon#about to read 3, iclass 19, count 0 2006.259.07:52:58.95#ibcon#read 3, iclass 19, count 0 2006.259.07:52:58.95#ibcon#about to read 4, iclass 19, count 0 2006.259.07:52:58.95#ibcon#read 4, iclass 19, count 0 2006.259.07:52:58.95#ibcon#about to read 5, iclass 19, count 0 2006.259.07:52:58.95#ibcon#read 5, iclass 19, count 0 2006.259.07:52:58.95#ibcon#about to read 6, iclass 19, count 0 2006.259.07:52:58.95#ibcon#read 6, iclass 19, count 0 2006.259.07:52:58.95#ibcon#end of sib2, iclass 19, count 0 2006.259.07:52:58.95#ibcon#*after write, iclass 19, count 0 2006.259.07:52:58.95#ibcon#*before return 0, iclass 19, count 0 2006.259.07:52:58.95#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.259.07:52:58.95#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.259.07:52:58.95#ibcon#about to clear, iclass 19 cls_cnt 0 2006.259.07:52:58.95#ibcon#cleared, iclass 19 cls_cnt 0 2006.259.07:52:58.96$vc4f8/va=1,8 2006.259.07:52:58.96#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.259.07:52:58.96#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.259.07:52:58.96#ibcon#ireg 11 cls_cnt 2 2006.259.07:52:58.96#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.259.07:52:58.96#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.259.07:52:58.96#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.259.07:52:58.96#ibcon#enter wrdev, iclass 21, count 2 2006.259.07:52:58.96#ibcon#first serial, iclass 21, count 2 2006.259.07:52:58.96#ibcon#enter sib2, iclass 21, count 2 2006.259.07:52:58.96#ibcon#flushed, iclass 21, count 2 2006.259.07:52:58.96#ibcon#about to write, iclass 21, count 2 2006.259.07:52:58.96#ibcon#wrote, iclass 21, count 2 2006.259.07:52:58.96#ibcon#about to read 3, iclass 21, count 2 2006.259.07:52:58.98#ibcon#read 3, iclass 21, count 2 2006.259.07:52:58.98#ibcon#about to read 4, iclass 21, count 2 2006.259.07:52:58.98#ibcon#read 4, iclass 21, count 2 2006.259.07:52:58.98#ibcon#about to read 5, iclass 21, count 2 2006.259.07:52:58.98#ibcon#read 5, iclass 21, count 2 2006.259.07:52:58.98#ibcon#about to read 6, iclass 21, count 2 2006.259.07:52:58.98#ibcon#read 6, iclass 21, count 2 2006.259.07:52:58.98#ibcon#end of sib2, iclass 21, count 2 2006.259.07:52:58.98#ibcon#*mode == 0, iclass 21, count 2 2006.259.07:52:58.98#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.259.07:52:58.98#ibcon#[25=AT01-08\r\n] 2006.259.07:52:58.98#ibcon#*before write, iclass 21, count 2 2006.259.07:52:58.98#ibcon#enter sib2, iclass 21, count 2 2006.259.07:52:58.98#ibcon#flushed, iclass 21, count 2 2006.259.07:52:58.98#ibcon#about to write, iclass 21, count 2 2006.259.07:52:58.98#ibcon#wrote, iclass 21, count 2 2006.259.07:52:58.98#ibcon#about to read 3, iclass 21, count 2 2006.259.07:52:59.01#ibcon#read 3, iclass 21, count 2 2006.259.07:52:59.01#ibcon#about to read 4, iclass 21, count 2 2006.259.07:52:59.01#ibcon#read 4, iclass 21, count 2 2006.259.07:52:59.01#ibcon#about to read 5, iclass 21, count 2 2006.259.07:52:59.01#ibcon#read 5, iclass 21, count 2 2006.259.07:52:59.01#ibcon#about to read 6, iclass 21, count 2 2006.259.07:52:59.01#ibcon#read 6, iclass 21, count 2 2006.259.07:52:59.01#ibcon#end of sib2, iclass 21, count 2 2006.259.07:52:59.01#ibcon#*after write, iclass 21, count 2 2006.259.07:52:59.01#ibcon#*before return 0, iclass 21, count 2 2006.259.07:52:59.01#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.259.07:52:59.01#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.259.07:52:59.01#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.259.07:52:59.01#ibcon#ireg 7 cls_cnt 0 2006.259.07:52:59.01#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.259.07:52:59.13#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.259.07:52:59.13#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.259.07:52:59.13#ibcon#enter wrdev, iclass 21, count 0 2006.259.07:52:59.13#ibcon#first serial, iclass 21, count 0 2006.259.07:52:59.13#ibcon#enter sib2, iclass 21, count 0 2006.259.07:52:59.13#ibcon#flushed, iclass 21, count 0 2006.259.07:52:59.13#ibcon#about to write, iclass 21, count 0 2006.259.07:52:59.13#ibcon#wrote, iclass 21, count 0 2006.259.07:52:59.13#ibcon#about to read 3, iclass 21, count 0 2006.259.07:52:59.14#ibcon#read 3, iclass 21, count 0 2006.259.07:52:59.14#ibcon#about to read 4, iclass 21, count 0 2006.259.07:52:59.14#ibcon#read 4, iclass 21, count 0 2006.259.07:52:59.14#ibcon#about to read 5, iclass 21, count 0 2006.259.07:52:59.14#ibcon#read 5, iclass 21, count 0 2006.259.07:52:59.14#ibcon#about to read 6, iclass 21, count 0 2006.259.07:52:59.14#ibcon#read 6, iclass 21, count 0 2006.259.07:52:59.14#ibcon#end of sib2, iclass 21, count 0 2006.259.07:52:59.14#ibcon#*mode == 0, iclass 21, count 0 2006.259.07:52:59.14#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.259.07:52:59.14#ibcon#[25=USB\r\n] 2006.259.07:52:59.14#ibcon#*before write, iclass 21, count 0 2006.259.07:52:59.14#ibcon#enter sib2, iclass 21, count 0 2006.259.07:52:59.14#ibcon#flushed, iclass 21, count 0 2006.259.07:52:59.14#ibcon#about to write, iclass 21, count 0 2006.259.07:52:59.14#ibcon#wrote, iclass 21, count 0 2006.259.07:52:59.14#ibcon#about to read 3, iclass 21, count 0 2006.259.07:52:59.17#ibcon#read 3, iclass 21, count 0 2006.259.07:52:59.17#ibcon#about to read 4, iclass 21, count 0 2006.259.07:52:59.17#ibcon#read 4, iclass 21, count 0 2006.259.07:52:59.17#ibcon#about to read 5, iclass 21, count 0 2006.259.07:52:59.17#ibcon#read 5, iclass 21, count 0 2006.259.07:52:59.17#ibcon#about to read 6, iclass 21, count 0 2006.259.07:52:59.17#ibcon#read 6, iclass 21, count 0 2006.259.07:52:59.17#ibcon#end of sib2, iclass 21, count 0 2006.259.07:52:59.17#ibcon#*after write, iclass 21, count 0 2006.259.07:52:59.17#ibcon#*before return 0, iclass 21, count 0 2006.259.07:52:59.17#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.259.07:52:59.17#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.259.07:52:59.17#ibcon#about to clear, iclass 21 cls_cnt 0 2006.259.07:52:59.17#ibcon#cleared, iclass 21 cls_cnt 0 2006.259.07:52:59.18$vc4f8/valo=2,572.99 2006.259.07:52:59.18#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.259.07:52:59.18#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.259.07:52:59.18#ibcon#ireg 17 cls_cnt 0 2006.259.07:52:59.18#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.259.07:52:59.18#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.259.07:52:59.18#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.259.07:52:59.18#ibcon#enter wrdev, iclass 23, count 0 2006.259.07:52:59.18#ibcon#first serial, iclass 23, count 0 2006.259.07:52:59.18#ibcon#enter sib2, iclass 23, count 0 2006.259.07:52:59.18#ibcon#flushed, iclass 23, count 0 2006.259.07:52:59.18#ibcon#about to write, iclass 23, count 0 2006.259.07:52:59.18#ibcon#wrote, iclass 23, count 0 2006.259.07:52:59.18#ibcon#about to read 3, iclass 23, count 0 2006.259.07:52:59.20#ibcon#read 3, iclass 23, count 0 2006.259.07:52:59.20#ibcon#about to read 4, iclass 23, count 0 2006.259.07:52:59.20#ibcon#read 4, iclass 23, count 0 2006.259.07:52:59.20#ibcon#about to read 5, iclass 23, count 0 2006.259.07:52:59.20#ibcon#read 5, iclass 23, count 0 2006.259.07:52:59.20#ibcon#about to read 6, iclass 23, count 0 2006.259.07:52:59.20#ibcon#read 6, iclass 23, count 0 2006.259.07:52:59.20#ibcon#end of sib2, iclass 23, count 0 2006.259.07:52:59.20#ibcon#*mode == 0, iclass 23, count 0 2006.259.07:52:59.20#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.259.07:52:59.20#ibcon#[26=FRQ=02,572.99\r\n] 2006.259.07:52:59.20#ibcon#*before write, iclass 23, count 0 2006.259.07:52:59.20#ibcon#enter sib2, iclass 23, count 0 2006.259.07:52:59.20#ibcon#flushed, iclass 23, count 0 2006.259.07:52:59.20#ibcon#about to write, iclass 23, count 0 2006.259.07:52:59.20#ibcon#wrote, iclass 23, count 0 2006.259.07:52:59.20#ibcon#about to read 3, iclass 23, count 0 2006.259.07:52:59.24#ibcon#read 3, iclass 23, count 0 2006.259.07:52:59.24#ibcon#about to read 4, iclass 23, count 0 2006.259.07:52:59.24#ibcon#read 4, iclass 23, count 0 2006.259.07:52:59.24#ibcon#about to read 5, iclass 23, count 0 2006.259.07:52:59.24#ibcon#read 5, iclass 23, count 0 2006.259.07:52:59.24#ibcon#about to read 6, iclass 23, count 0 2006.259.07:52:59.24#ibcon#read 6, iclass 23, count 0 2006.259.07:52:59.24#ibcon#end of sib2, iclass 23, count 0 2006.259.07:52:59.24#ibcon#*after write, iclass 23, count 0 2006.259.07:52:59.24#ibcon#*before return 0, iclass 23, count 0 2006.259.07:52:59.24#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.259.07:52:59.24#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.259.07:52:59.24#ibcon#about to clear, iclass 23 cls_cnt 0 2006.259.07:52:59.24#ibcon#cleared, iclass 23 cls_cnt 0 2006.259.07:52:59.25$vc4f8/va=2,7 2006.259.07:52:59.25#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.259.07:52:59.25#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.259.07:52:59.25#ibcon#ireg 11 cls_cnt 2 2006.259.07:52:59.25#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.259.07:52:59.28#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.259.07:52:59.28#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.259.07:52:59.28#ibcon#enter wrdev, iclass 25, count 2 2006.259.07:52:59.28#ibcon#first serial, iclass 25, count 2 2006.259.07:52:59.28#ibcon#enter sib2, iclass 25, count 2 2006.259.07:52:59.28#ibcon#flushed, iclass 25, count 2 2006.259.07:52:59.28#ibcon#about to write, iclass 25, count 2 2006.259.07:52:59.28#ibcon#wrote, iclass 25, count 2 2006.259.07:52:59.28#ibcon#about to read 3, iclass 25, count 2 2006.259.07:52:59.31#ibcon#read 3, iclass 25, count 2 2006.259.07:52:59.31#ibcon#about to read 4, iclass 25, count 2 2006.259.07:52:59.31#ibcon#read 4, iclass 25, count 2 2006.259.07:52:59.31#ibcon#about to read 5, iclass 25, count 2 2006.259.07:52:59.31#ibcon#read 5, iclass 25, count 2 2006.259.07:52:59.31#ibcon#about to read 6, iclass 25, count 2 2006.259.07:52:59.31#ibcon#read 6, iclass 25, count 2 2006.259.07:52:59.31#ibcon#end of sib2, iclass 25, count 2 2006.259.07:52:59.31#ibcon#*mode == 0, iclass 25, count 2 2006.259.07:52:59.31#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.259.07:52:59.31#ibcon#[25=AT02-07\r\n] 2006.259.07:52:59.31#ibcon#*before write, iclass 25, count 2 2006.259.07:52:59.31#ibcon#enter sib2, iclass 25, count 2 2006.259.07:52:59.31#ibcon#flushed, iclass 25, count 2 2006.259.07:52:59.31#ibcon#about to write, iclass 25, count 2 2006.259.07:52:59.31#ibcon#wrote, iclass 25, count 2 2006.259.07:52:59.31#ibcon#about to read 3, iclass 25, count 2 2006.259.07:52:59.34#ibcon#read 3, iclass 25, count 2 2006.259.07:52:59.34#ibcon#about to read 4, iclass 25, count 2 2006.259.07:52:59.34#ibcon#read 4, iclass 25, count 2 2006.259.07:52:59.34#ibcon#about to read 5, iclass 25, count 2 2006.259.07:52:59.34#ibcon#read 5, iclass 25, count 2 2006.259.07:52:59.34#ibcon#about to read 6, iclass 25, count 2 2006.259.07:52:59.34#ibcon#read 6, iclass 25, count 2 2006.259.07:52:59.34#ibcon#end of sib2, iclass 25, count 2 2006.259.07:52:59.34#ibcon#*after write, iclass 25, count 2 2006.259.07:52:59.34#ibcon#*before return 0, iclass 25, count 2 2006.259.07:52:59.34#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.259.07:52:59.34#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.259.07:52:59.34#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.259.07:52:59.34#ibcon#ireg 7 cls_cnt 0 2006.259.07:52:59.34#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.259.07:52:59.46#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.259.07:52:59.46#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.259.07:52:59.46#ibcon#enter wrdev, iclass 25, count 0 2006.259.07:52:59.46#ibcon#first serial, iclass 25, count 0 2006.259.07:52:59.46#ibcon#enter sib2, iclass 25, count 0 2006.259.07:52:59.46#ibcon#flushed, iclass 25, count 0 2006.259.07:52:59.46#ibcon#about to write, iclass 25, count 0 2006.259.07:52:59.46#ibcon#wrote, iclass 25, count 0 2006.259.07:52:59.46#ibcon#about to read 3, iclass 25, count 0 2006.259.07:52:59.48#ibcon#read 3, iclass 25, count 0 2006.259.07:52:59.48#ibcon#about to read 4, iclass 25, count 0 2006.259.07:52:59.48#ibcon#read 4, iclass 25, count 0 2006.259.07:52:59.48#ibcon#about to read 5, iclass 25, count 0 2006.259.07:52:59.48#ibcon#read 5, iclass 25, count 0 2006.259.07:52:59.48#ibcon#about to read 6, iclass 25, count 0 2006.259.07:52:59.48#ibcon#read 6, iclass 25, count 0 2006.259.07:52:59.48#ibcon#end of sib2, iclass 25, count 0 2006.259.07:52:59.48#ibcon#*mode == 0, iclass 25, count 0 2006.259.07:52:59.48#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.259.07:52:59.48#ibcon#[25=USB\r\n] 2006.259.07:52:59.48#ibcon#*before write, iclass 25, count 0 2006.259.07:52:59.48#ibcon#enter sib2, iclass 25, count 0 2006.259.07:52:59.48#ibcon#flushed, iclass 25, count 0 2006.259.07:52:59.48#ibcon#about to write, iclass 25, count 0 2006.259.07:52:59.48#ibcon#wrote, iclass 25, count 0 2006.259.07:52:59.48#ibcon#about to read 3, iclass 25, count 0 2006.259.07:52:59.51#ibcon#read 3, iclass 25, count 0 2006.259.07:52:59.51#ibcon#about to read 4, iclass 25, count 0 2006.259.07:52:59.51#ibcon#read 4, iclass 25, count 0 2006.259.07:52:59.51#ibcon#about to read 5, iclass 25, count 0 2006.259.07:52:59.51#ibcon#read 5, iclass 25, count 0 2006.259.07:52:59.51#ibcon#about to read 6, iclass 25, count 0 2006.259.07:52:59.51#ibcon#read 6, iclass 25, count 0 2006.259.07:52:59.51#ibcon#end of sib2, iclass 25, count 0 2006.259.07:52:59.51#ibcon#*after write, iclass 25, count 0 2006.259.07:52:59.51#ibcon#*before return 0, iclass 25, count 0 2006.259.07:52:59.51#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.259.07:52:59.51#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.259.07:52:59.51#ibcon#about to clear, iclass 25 cls_cnt 0 2006.259.07:52:59.51#ibcon#cleared, iclass 25 cls_cnt 0 2006.259.07:52:59.52$vc4f8/valo=3,672.99 2006.259.07:52:59.52#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.259.07:52:59.52#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.259.07:52:59.52#ibcon#ireg 17 cls_cnt 0 2006.259.07:52:59.52#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.259.07:52:59.52#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.259.07:52:59.52#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.259.07:52:59.52#ibcon#enter wrdev, iclass 27, count 0 2006.259.07:52:59.52#ibcon#first serial, iclass 27, count 0 2006.259.07:52:59.52#ibcon#enter sib2, iclass 27, count 0 2006.259.07:52:59.52#ibcon#flushed, iclass 27, count 0 2006.259.07:52:59.52#ibcon#about to write, iclass 27, count 0 2006.259.07:52:59.52#ibcon#wrote, iclass 27, count 0 2006.259.07:52:59.52#ibcon#about to read 3, iclass 27, count 0 2006.259.07:52:59.53#ibcon#read 3, iclass 27, count 0 2006.259.07:52:59.53#ibcon#about to read 4, iclass 27, count 0 2006.259.07:52:59.53#ibcon#read 4, iclass 27, count 0 2006.259.07:52:59.53#ibcon#about to read 5, iclass 27, count 0 2006.259.07:52:59.53#ibcon#read 5, iclass 27, count 0 2006.259.07:52:59.53#ibcon#about to read 6, iclass 27, count 0 2006.259.07:52:59.53#ibcon#read 6, iclass 27, count 0 2006.259.07:52:59.53#ibcon#end of sib2, iclass 27, count 0 2006.259.07:52:59.53#ibcon#*mode == 0, iclass 27, count 0 2006.259.07:52:59.53#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.259.07:52:59.53#ibcon#[26=FRQ=03,672.99\r\n] 2006.259.07:52:59.53#ibcon#*before write, iclass 27, count 0 2006.259.07:52:59.53#ibcon#enter sib2, iclass 27, count 0 2006.259.07:52:59.53#ibcon#flushed, iclass 27, count 0 2006.259.07:52:59.54#ibcon#about to write, iclass 27, count 0 2006.259.07:52:59.54#ibcon#wrote, iclass 27, count 0 2006.259.07:52:59.54#ibcon#about to read 3, iclass 27, count 0 2006.259.07:52:59.58#ibcon#read 3, iclass 27, count 0 2006.259.07:52:59.58#ibcon#about to read 4, iclass 27, count 0 2006.259.07:52:59.58#ibcon#read 4, iclass 27, count 0 2006.259.07:52:59.58#ibcon#about to read 5, iclass 27, count 0 2006.259.07:52:59.58#ibcon#read 5, iclass 27, count 0 2006.259.07:52:59.58#ibcon#about to read 6, iclass 27, count 0 2006.259.07:52:59.58#ibcon#read 6, iclass 27, count 0 2006.259.07:52:59.58#ibcon#end of sib2, iclass 27, count 0 2006.259.07:52:59.58#ibcon#*after write, iclass 27, count 0 2006.259.07:52:59.58#ibcon#*before return 0, iclass 27, count 0 2006.259.07:52:59.58#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.259.07:52:59.58#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.259.07:52:59.58#ibcon#about to clear, iclass 27 cls_cnt 0 2006.259.07:52:59.58#ibcon#cleared, iclass 27 cls_cnt 0 2006.259.07:52:59.58$vc4f8/va=3,8 2006.259.07:52:59.58#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.259.07:52:59.58#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.259.07:52:59.58#ibcon#ireg 11 cls_cnt 2 2006.259.07:52:59.58#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.259.07:52:59.62#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.259.07:52:59.62#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.259.07:52:59.62#ibcon#enter wrdev, iclass 29, count 2 2006.259.07:52:59.62#ibcon#first serial, iclass 29, count 2 2006.259.07:52:59.62#ibcon#enter sib2, iclass 29, count 2 2006.259.07:52:59.62#ibcon#flushed, iclass 29, count 2 2006.259.07:52:59.62#ibcon#about to write, iclass 29, count 2 2006.259.07:52:59.62#ibcon#wrote, iclass 29, count 2 2006.259.07:52:59.62#ibcon#about to read 3, iclass 29, count 2 2006.259.07:52:59.65#ibcon#read 3, iclass 29, count 2 2006.259.07:52:59.65#ibcon#about to read 4, iclass 29, count 2 2006.259.07:52:59.65#ibcon#read 4, iclass 29, count 2 2006.259.07:52:59.65#ibcon#about to read 5, iclass 29, count 2 2006.259.07:52:59.65#ibcon#read 5, iclass 29, count 2 2006.259.07:52:59.65#ibcon#about to read 6, iclass 29, count 2 2006.259.07:52:59.65#ibcon#read 6, iclass 29, count 2 2006.259.07:52:59.65#ibcon#end of sib2, iclass 29, count 2 2006.259.07:52:59.65#ibcon#*mode == 0, iclass 29, count 2 2006.259.07:52:59.65#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.259.07:52:59.65#ibcon#[25=AT03-08\r\n] 2006.259.07:52:59.65#ibcon#*before write, iclass 29, count 2 2006.259.07:52:59.65#ibcon#enter sib2, iclass 29, count 2 2006.259.07:52:59.65#ibcon#flushed, iclass 29, count 2 2006.259.07:52:59.65#ibcon#about to write, iclass 29, count 2 2006.259.07:52:59.65#ibcon#wrote, iclass 29, count 2 2006.259.07:52:59.65#ibcon#about to read 3, iclass 29, count 2 2006.259.07:52:59.68#ibcon#read 3, iclass 29, count 2 2006.259.07:52:59.68#ibcon#about to read 4, iclass 29, count 2 2006.259.07:52:59.68#ibcon#read 4, iclass 29, count 2 2006.259.07:52:59.68#ibcon#about to read 5, iclass 29, count 2 2006.259.07:52:59.68#ibcon#read 5, iclass 29, count 2 2006.259.07:52:59.68#ibcon#about to read 6, iclass 29, count 2 2006.259.07:52:59.68#ibcon#read 6, iclass 29, count 2 2006.259.07:52:59.68#ibcon#end of sib2, iclass 29, count 2 2006.259.07:52:59.68#ibcon#*after write, iclass 29, count 2 2006.259.07:52:59.68#ibcon#*before return 0, iclass 29, count 2 2006.259.07:52:59.68#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.259.07:52:59.68#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.259.07:52:59.68#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.259.07:52:59.68#ibcon#ireg 7 cls_cnt 0 2006.259.07:52:59.68#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.259.07:52:59.80#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.259.07:52:59.80#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.259.07:52:59.80#ibcon#enter wrdev, iclass 29, count 0 2006.259.07:52:59.80#ibcon#first serial, iclass 29, count 0 2006.259.07:52:59.80#ibcon#enter sib2, iclass 29, count 0 2006.259.07:52:59.80#ibcon#flushed, iclass 29, count 0 2006.259.07:52:59.80#ibcon#about to write, iclass 29, count 0 2006.259.07:52:59.80#ibcon#wrote, iclass 29, count 0 2006.259.07:52:59.80#ibcon#about to read 3, iclass 29, count 0 2006.259.07:52:59.82#ibcon#read 3, iclass 29, count 0 2006.259.07:52:59.82#ibcon#about to read 4, iclass 29, count 0 2006.259.07:52:59.82#ibcon#read 4, iclass 29, count 0 2006.259.07:52:59.82#ibcon#about to read 5, iclass 29, count 0 2006.259.07:52:59.82#ibcon#read 5, iclass 29, count 0 2006.259.07:52:59.82#ibcon#about to read 6, iclass 29, count 0 2006.259.07:52:59.82#ibcon#read 6, iclass 29, count 0 2006.259.07:52:59.82#ibcon#end of sib2, iclass 29, count 0 2006.259.07:52:59.82#ibcon#*mode == 0, iclass 29, count 0 2006.259.07:52:59.82#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.259.07:52:59.82#ibcon#[25=USB\r\n] 2006.259.07:52:59.82#ibcon#*before write, iclass 29, count 0 2006.259.07:52:59.82#ibcon#enter sib2, iclass 29, count 0 2006.259.07:52:59.82#ibcon#flushed, iclass 29, count 0 2006.259.07:52:59.82#ibcon#about to write, iclass 29, count 0 2006.259.07:52:59.82#ibcon#wrote, iclass 29, count 0 2006.259.07:52:59.82#ibcon#about to read 3, iclass 29, count 0 2006.259.07:52:59.85#ibcon#read 3, iclass 29, count 0 2006.259.07:52:59.85#ibcon#about to read 4, iclass 29, count 0 2006.259.07:52:59.85#ibcon#read 4, iclass 29, count 0 2006.259.07:52:59.85#ibcon#about to read 5, iclass 29, count 0 2006.259.07:52:59.85#ibcon#read 5, iclass 29, count 0 2006.259.07:52:59.85#ibcon#about to read 6, iclass 29, count 0 2006.259.07:52:59.85#ibcon#read 6, iclass 29, count 0 2006.259.07:52:59.85#ibcon#end of sib2, iclass 29, count 0 2006.259.07:52:59.85#ibcon#*after write, iclass 29, count 0 2006.259.07:52:59.85#ibcon#*before return 0, iclass 29, count 0 2006.259.07:52:59.85#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.259.07:52:59.85#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.259.07:52:59.85#ibcon#about to clear, iclass 29 cls_cnt 0 2006.259.07:52:59.85#ibcon#cleared, iclass 29 cls_cnt 0 2006.259.07:52:59.86$vc4f8/valo=4,832.99 2006.259.07:52:59.86#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.259.07:52:59.86#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.259.07:52:59.86#ibcon#ireg 17 cls_cnt 0 2006.259.07:52:59.86#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.259.07:52:59.86#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.259.07:52:59.86#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.259.07:52:59.86#ibcon#enter wrdev, iclass 31, count 0 2006.259.07:52:59.86#ibcon#first serial, iclass 31, count 0 2006.259.07:52:59.86#ibcon#enter sib2, iclass 31, count 0 2006.259.07:52:59.86#ibcon#flushed, iclass 31, count 0 2006.259.07:52:59.86#ibcon#about to write, iclass 31, count 0 2006.259.07:52:59.86#ibcon#wrote, iclass 31, count 0 2006.259.07:52:59.86#ibcon#about to read 3, iclass 31, count 0 2006.259.07:52:59.87#ibcon#read 3, iclass 31, count 0 2006.259.07:52:59.87#ibcon#about to read 4, iclass 31, count 0 2006.259.07:52:59.87#ibcon#read 4, iclass 31, count 0 2006.259.07:52:59.87#ibcon#about to read 5, iclass 31, count 0 2006.259.07:52:59.87#ibcon#read 5, iclass 31, count 0 2006.259.07:52:59.87#ibcon#about to read 6, iclass 31, count 0 2006.259.07:52:59.87#ibcon#read 6, iclass 31, count 0 2006.259.07:52:59.87#ibcon#end of sib2, iclass 31, count 0 2006.259.07:52:59.87#ibcon#*mode == 0, iclass 31, count 0 2006.259.07:52:59.87#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.259.07:52:59.87#ibcon#[26=FRQ=04,832.99\r\n] 2006.259.07:52:59.87#ibcon#*before write, iclass 31, count 0 2006.259.07:52:59.87#ibcon#enter sib2, iclass 31, count 0 2006.259.07:52:59.87#ibcon#flushed, iclass 31, count 0 2006.259.07:52:59.87#ibcon#about to write, iclass 31, count 0 2006.259.07:52:59.87#ibcon#wrote, iclass 31, count 0 2006.259.07:52:59.87#ibcon#about to read 3, iclass 31, count 0 2006.259.07:52:59.91#ibcon#read 3, iclass 31, count 0 2006.259.07:52:59.91#ibcon#about to read 4, iclass 31, count 0 2006.259.07:52:59.91#ibcon#read 4, iclass 31, count 0 2006.259.07:52:59.91#ibcon#about to read 5, iclass 31, count 0 2006.259.07:52:59.91#ibcon#read 5, iclass 31, count 0 2006.259.07:52:59.91#ibcon#about to read 6, iclass 31, count 0 2006.259.07:52:59.91#ibcon#read 6, iclass 31, count 0 2006.259.07:52:59.91#ibcon#end of sib2, iclass 31, count 0 2006.259.07:52:59.91#ibcon#*after write, iclass 31, count 0 2006.259.07:52:59.91#ibcon#*before return 0, iclass 31, count 0 2006.259.07:52:59.91#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.259.07:52:59.91#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.259.07:52:59.91#ibcon#about to clear, iclass 31 cls_cnt 0 2006.259.07:52:59.91#ibcon#cleared, iclass 31 cls_cnt 0 2006.259.07:52:59.92$vc4f8/va=4,7 2006.259.07:52:59.92#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.259.07:52:59.92#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.259.07:52:59.92#ibcon#ireg 11 cls_cnt 2 2006.259.07:52:59.92#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.259.07:52:59.96#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.259.07:52:59.96#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.259.07:52:59.96#ibcon#enter wrdev, iclass 33, count 2 2006.259.07:52:59.96#ibcon#first serial, iclass 33, count 2 2006.259.07:52:59.96#ibcon#enter sib2, iclass 33, count 2 2006.259.07:52:59.96#ibcon#flushed, iclass 33, count 2 2006.259.07:52:59.96#ibcon#about to write, iclass 33, count 2 2006.259.07:52:59.96#ibcon#wrote, iclass 33, count 2 2006.259.07:52:59.96#ibcon#about to read 3, iclass 33, count 2 2006.259.07:52:59.98#ibcon#read 3, iclass 33, count 2 2006.259.07:52:59.98#ibcon#about to read 4, iclass 33, count 2 2006.259.07:52:59.98#ibcon#read 4, iclass 33, count 2 2006.259.07:52:59.98#ibcon#about to read 5, iclass 33, count 2 2006.259.07:52:59.98#ibcon#read 5, iclass 33, count 2 2006.259.07:52:59.98#ibcon#about to read 6, iclass 33, count 2 2006.259.07:52:59.98#ibcon#read 6, iclass 33, count 2 2006.259.07:52:59.98#ibcon#end of sib2, iclass 33, count 2 2006.259.07:52:59.98#ibcon#*mode == 0, iclass 33, count 2 2006.259.07:52:59.98#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.259.07:52:59.98#ibcon#[25=AT04-07\r\n] 2006.259.07:52:59.98#ibcon#*before write, iclass 33, count 2 2006.259.07:52:59.98#ibcon#enter sib2, iclass 33, count 2 2006.259.07:52:59.98#ibcon#flushed, iclass 33, count 2 2006.259.07:52:59.98#ibcon#about to write, iclass 33, count 2 2006.259.07:52:59.98#ibcon#wrote, iclass 33, count 2 2006.259.07:52:59.98#ibcon#about to read 3, iclass 33, count 2 2006.259.07:53:00.01#ibcon#read 3, iclass 33, count 2 2006.259.07:53:00.01#ibcon#about to read 4, iclass 33, count 2 2006.259.07:53:00.01#ibcon#read 4, iclass 33, count 2 2006.259.07:53:00.01#ibcon#about to read 5, iclass 33, count 2 2006.259.07:53:00.01#ibcon#read 5, iclass 33, count 2 2006.259.07:53:00.01#ibcon#about to read 6, iclass 33, count 2 2006.259.07:53:00.01#ibcon#read 6, iclass 33, count 2 2006.259.07:53:00.01#ibcon#end of sib2, iclass 33, count 2 2006.259.07:53:00.01#ibcon#*after write, iclass 33, count 2 2006.259.07:53:00.01#ibcon#*before return 0, iclass 33, count 2 2006.259.07:53:00.01#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.259.07:53:00.01#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.259.07:53:00.01#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.259.07:53:00.01#ibcon#ireg 7 cls_cnt 0 2006.259.07:53:00.01#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.259.07:53:00.14#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.259.07:53:00.14#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.259.07:53:00.14#ibcon#enter wrdev, iclass 33, count 0 2006.259.07:53:00.14#ibcon#first serial, iclass 33, count 0 2006.259.07:53:00.14#ibcon#enter sib2, iclass 33, count 0 2006.259.07:53:00.14#ibcon#flushed, iclass 33, count 0 2006.259.07:53:00.14#ibcon#about to write, iclass 33, count 0 2006.259.07:53:00.14#ibcon#wrote, iclass 33, count 0 2006.259.07:53:00.14#ibcon#about to read 3, iclass 33, count 0 2006.259.07:53:00.15#ibcon#read 3, iclass 33, count 0 2006.259.07:53:00.15#ibcon#about to read 4, iclass 33, count 0 2006.259.07:53:00.15#ibcon#read 4, iclass 33, count 0 2006.259.07:53:00.15#ibcon#about to read 5, iclass 33, count 0 2006.259.07:53:00.15#ibcon#read 5, iclass 33, count 0 2006.259.07:53:00.15#ibcon#about to read 6, iclass 33, count 0 2006.259.07:53:00.15#ibcon#read 6, iclass 33, count 0 2006.259.07:53:00.15#ibcon#end of sib2, iclass 33, count 0 2006.259.07:53:00.15#ibcon#*mode == 0, iclass 33, count 0 2006.259.07:53:00.15#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.259.07:53:00.15#ibcon#[25=USB\r\n] 2006.259.07:53:00.15#ibcon#*before write, iclass 33, count 0 2006.259.07:53:00.15#ibcon#enter sib2, iclass 33, count 0 2006.259.07:53:00.15#ibcon#flushed, iclass 33, count 0 2006.259.07:53:00.15#ibcon#about to write, iclass 33, count 0 2006.259.07:53:00.15#ibcon#wrote, iclass 33, count 0 2006.259.07:53:00.15#ibcon#about to read 3, iclass 33, count 0 2006.259.07:53:00.18#ibcon#read 3, iclass 33, count 0 2006.259.07:53:00.18#ibcon#about to read 4, iclass 33, count 0 2006.259.07:53:00.18#ibcon#read 4, iclass 33, count 0 2006.259.07:53:00.18#ibcon#about to read 5, iclass 33, count 0 2006.259.07:53:00.18#ibcon#read 5, iclass 33, count 0 2006.259.07:53:00.18#ibcon#about to read 6, iclass 33, count 0 2006.259.07:53:00.18#ibcon#read 6, iclass 33, count 0 2006.259.07:53:00.18#ibcon#end of sib2, iclass 33, count 0 2006.259.07:53:00.18#ibcon#*after write, iclass 33, count 0 2006.259.07:53:00.18#ibcon#*before return 0, iclass 33, count 0 2006.259.07:53:00.18#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.259.07:53:00.18#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.259.07:53:00.18#ibcon#about to clear, iclass 33 cls_cnt 0 2006.259.07:53:00.18#ibcon#cleared, iclass 33 cls_cnt 0 2006.259.07:53:00.19$vc4f8/valo=5,652.99 2006.259.07:53:00.19#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.259.07:53:00.19#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.259.07:53:00.19#ibcon#ireg 17 cls_cnt 0 2006.259.07:53:00.19#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.259.07:53:00.19#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.259.07:53:00.19#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.259.07:53:00.19#ibcon#enter wrdev, iclass 35, count 0 2006.259.07:53:00.19#ibcon#first serial, iclass 35, count 0 2006.259.07:53:00.19#ibcon#enter sib2, iclass 35, count 0 2006.259.07:53:00.19#ibcon#flushed, iclass 35, count 0 2006.259.07:53:00.19#ibcon#about to write, iclass 35, count 0 2006.259.07:53:00.19#ibcon#wrote, iclass 35, count 0 2006.259.07:53:00.19#ibcon#about to read 3, iclass 35, count 0 2006.259.07:53:00.20#ibcon#read 3, iclass 35, count 0 2006.259.07:53:00.20#ibcon#about to read 4, iclass 35, count 0 2006.259.07:53:00.20#ibcon#read 4, iclass 35, count 0 2006.259.07:53:00.20#ibcon#about to read 5, iclass 35, count 0 2006.259.07:53:00.20#ibcon#read 5, iclass 35, count 0 2006.259.07:53:00.20#ibcon#about to read 6, iclass 35, count 0 2006.259.07:53:00.20#ibcon#read 6, iclass 35, count 0 2006.259.07:53:00.20#ibcon#end of sib2, iclass 35, count 0 2006.259.07:53:00.20#ibcon#*mode == 0, iclass 35, count 0 2006.259.07:53:00.20#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.259.07:53:00.20#ibcon#[26=FRQ=05,652.99\r\n] 2006.259.07:53:00.20#ibcon#*before write, iclass 35, count 0 2006.259.07:53:00.20#ibcon#enter sib2, iclass 35, count 0 2006.259.07:53:00.20#ibcon#flushed, iclass 35, count 0 2006.259.07:53:00.20#ibcon#about to write, iclass 35, count 0 2006.259.07:53:00.20#ibcon#wrote, iclass 35, count 0 2006.259.07:53:00.20#ibcon#about to read 3, iclass 35, count 0 2006.259.07:53:00.24#ibcon#read 3, iclass 35, count 0 2006.259.07:53:00.24#ibcon#about to read 4, iclass 35, count 0 2006.259.07:53:00.24#ibcon#read 4, iclass 35, count 0 2006.259.07:53:00.24#ibcon#about to read 5, iclass 35, count 0 2006.259.07:53:00.24#ibcon#read 5, iclass 35, count 0 2006.259.07:53:00.24#ibcon#about to read 6, iclass 35, count 0 2006.259.07:53:00.24#ibcon#read 6, iclass 35, count 0 2006.259.07:53:00.24#ibcon#end of sib2, iclass 35, count 0 2006.259.07:53:00.24#ibcon#*after write, iclass 35, count 0 2006.259.07:53:00.24#ibcon#*before return 0, iclass 35, count 0 2006.259.07:53:00.24#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.259.07:53:00.24#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.259.07:53:00.24#ibcon#about to clear, iclass 35 cls_cnt 0 2006.259.07:53:00.24#ibcon#cleared, iclass 35 cls_cnt 0 2006.259.07:53:00.25$vc4f8/va=5,7 2006.259.07:53:00.25#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.259.07:53:00.25#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.259.07:53:00.25#ibcon#ireg 11 cls_cnt 2 2006.259.07:53:00.25#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.259.07:53:00.29#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.259.07:53:00.29#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.259.07:53:00.29#ibcon#enter wrdev, iclass 37, count 2 2006.259.07:53:00.29#ibcon#first serial, iclass 37, count 2 2006.259.07:53:00.29#ibcon#enter sib2, iclass 37, count 2 2006.259.07:53:00.29#ibcon#flushed, iclass 37, count 2 2006.259.07:53:00.29#ibcon#about to write, iclass 37, count 2 2006.259.07:53:00.29#ibcon#wrote, iclass 37, count 2 2006.259.07:53:00.29#ibcon#about to read 3, iclass 37, count 2 2006.259.07:53:00.31#ibcon#read 3, iclass 37, count 2 2006.259.07:53:00.31#ibcon#about to read 4, iclass 37, count 2 2006.259.07:53:00.31#ibcon#read 4, iclass 37, count 2 2006.259.07:53:00.31#ibcon#about to read 5, iclass 37, count 2 2006.259.07:53:00.31#ibcon#read 5, iclass 37, count 2 2006.259.07:53:00.31#ibcon#about to read 6, iclass 37, count 2 2006.259.07:53:00.31#ibcon#read 6, iclass 37, count 2 2006.259.07:53:00.31#ibcon#end of sib2, iclass 37, count 2 2006.259.07:53:00.31#ibcon#*mode == 0, iclass 37, count 2 2006.259.07:53:00.31#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.259.07:53:00.31#ibcon#[25=AT05-07\r\n] 2006.259.07:53:00.31#ibcon#*before write, iclass 37, count 2 2006.259.07:53:00.31#ibcon#enter sib2, iclass 37, count 2 2006.259.07:53:00.31#ibcon#flushed, iclass 37, count 2 2006.259.07:53:00.31#ibcon#about to write, iclass 37, count 2 2006.259.07:53:00.31#ibcon#wrote, iclass 37, count 2 2006.259.07:53:00.31#ibcon#about to read 3, iclass 37, count 2 2006.259.07:53:00.34#ibcon#read 3, iclass 37, count 2 2006.259.07:53:00.34#ibcon#about to read 4, iclass 37, count 2 2006.259.07:53:00.34#ibcon#read 4, iclass 37, count 2 2006.259.07:53:00.34#ibcon#about to read 5, iclass 37, count 2 2006.259.07:53:00.34#ibcon#read 5, iclass 37, count 2 2006.259.07:53:00.34#ibcon#about to read 6, iclass 37, count 2 2006.259.07:53:00.34#ibcon#read 6, iclass 37, count 2 2006.259.07:53:00.34#ibcon#end of sib2, iclass 37, count 2 2006.259.07:53:00.34#ibcon#*after write, iclass 37, count 2 2006.259.07:53:00.34#ibcon#*before return 0, iclass 37, count 2 2006.259.07:53:00.34#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.259.07:53:00.34#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.259.07:53:00.34#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.259.07:53:00.34#ibcon#ireg 7 cls_cnt 0 2006.259.07:53:00.34#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.259.07:53:00.46#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.259.07:53:00.46#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.259.07:53:00.46#ibcon#enter wrdev, iclass 37, count 0 2006.259.07:53:00.46#ibcon#first serial, iclass 37, count 0 2006.259.07:53:00.46#ibcon#enter sib2, iclass 37, count 0 2006.259.07:53:00.46#ibcon#flushed, iclass 37, count 0 2006.259.07:53:00.46#ibcon#about to write, iclass 37, count 0 2006.259.07:53:00.46#ibcon#wrote, iclass 37, count 0 2006.259.07:53:00.46#ibcon#about to read 3, iclass 37, count 0 2006.259.07:53:00.48#ibcon#read 3, iclass 37, count 0 2006.259.07:53:00.48#ibcon#about to read 4, iclass 37, count 0 2006.259.07:53:00.48#ibcon#read 4, iclass 37, count 0 2006.259.07:53:00.48#ibcon#about to read 5, iclass 37, count 0 2006.259.07:53:00.48#ibcon#read 5, iclass 37, count 0 2006.259.07:53:00.48#ibcon#about to read 6, iclass 37, count 0 2006.259.07:53:00.48#ibcon#read 6, iclass 37, count 0 2006.259.07:53:00.48#ibcon#end of sib2, iclass 37, count 0 2006.259.07:53:00.48#ibcon#*mode == 0, iclass 37, count 0 2006.259.07:53:00.48#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.259.07:53:00.48#ibcon#[25=USB\r\n] 2006.259.07:53:00.48#ibcon#*before write, iclass 37, count 0 2006.259.07:53:00.48#ibcon#enter sib2, iclass 37, count 0 2006.259.07:53:00.48#ibcon#flushed, iclass 37, count 0 2006.259.07:53:00.48#ibcon#about to write, iclass 37, count 0 2006.259.07:53:00.48#ibcon#wrote, iclass 37, count 0 2006.259.07:53:00.48#ibcon#about to read 3, iclass 37, count 0 2006.259.07:53:00.51#ibcon#read 3, iclass 37, count 0 2006.259.07:53:00.51#ibcon#about to read 4, iclass 37, count 0 2006.259.07:53:00.51#ibcon#read 4, iclass 37, count 0 2006.259.07:53:00.51#ibcon#about to read 5, iclass 37, count 0 2006.259.07:53:00.51#ibcon#read 5, iclass 37, count 0 2006.259.07:53:00.51#ibcon#about to read 6, iclass 37, count 0 2006.259.07:53:00.51#ibcon#read 6, iclass 37, count 0 2006.259.07:53:00.51#ibcon#end of sib2, iclass 37, count 0 2006.259.07:53:00.51#ibcon#*after write, iclass 37, count 0 2006.259.07:53:00.51#ibcon#*before return 0, iclass 37, count 0 2006.259.07:53:00.51#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.259.07:53:00.51#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.259.07:53:00.51#ibcon#about to clear, iclass 37 cls_cnt 0 2006.259.07:53:00.51#ibcon#cleared, iclass 37 cls_cnt 0 2006.259.07:53:00.52$vc4f8/valo=6,772.99 2006.259.07:53:00.52#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.259.07:53:00.52#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.259.07:53:00.52#ibcon#ireg 17 cls_cnt 0 2006.259.07:53:00.52#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.259.07:53:00.52#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.259.07:53:00.52#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.259.07:53:00.52#ibcon#enter wrdev, iclass 39, count 0 2006.259.07:53:00.52#ibcon#first serial, iclass 39, count 0 2006.259.07:53:00.52#ibcon#enter sib2, iclass 39, count 0 2006.259.07:53:00.52#ibcon#flushed, iclass 39, count 0 2006.259.07:53:00.52#ibcon#about to write, iclass 39, count 0 2006.259.07:53:00.52#ibcon#wrote, iclass 39, count 0 2006.259.07:53:00.52#ibcon#about to read 3, iclass 39, count 0 2006.259.07:53:00.53#ibcon#read 3, iclass 39, count 0 2006.259.07:53:00.53#ibcon#about to read 4, iclass 39, count 0 2006.259.07:53:00.53#ibcon#read 4, iclass 39, count 0 2006.259.07:53:00.53#ibcon#about to read 5, iclass 39, count 0 2006.259.07:53:00.53#ibcon#read 5, iclass 39, count 0 2006.259.07:53:00.53#ibcon#about to read 6, iclass 39, count 0 2006.259.07:53:00.53#ibcon#read 6, iclass 39, count 0 2006.259.07:53:00.53#ibcon#end of sib2, iclass 39, count 0 2006.259.07:53:00.53#ibcon#*mode == 0, iclass 39, count 0 2006.259.07:53:00.53#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.259.07:53:00.53#ibcon#[26=FRQ=06,772.99\r\n] 2006.259.07:53:00.53#ibcon#*before write, iclass 39, count 0 2006.259.07:53:00.53#ibcon#enter sib2, iclass 39, count 0 2006.259.07:53:00.53#ibcon#flushed, iclass 39, count 0 2006.259.07:53:00.53#ibcon#about to write, iclass 39, count 0 2006.259.07:53:00.54#ibcon#wrote, iclass 39, count 0 2006.259.07:53:00.54#ibcon#about to read 3, iclass 39, count 0 2006.259.07:53:00.57#ibcon#read 3, iclass 39, count 0 2006.259.07:53:00.57#ibcon#about to read 4, iclass 39, count 0 2006.259.07:53:00.57#ibcon#read 4, iclass 39, count 0 2006.259.07:53:00.57#ibcon#about to read 5, iclass 39, count 0 2006.259.07:53:00.57#ibcon#read 5, iclass 39, count 0 2006.259.07:53:00.57#ibcon#about to read 6, iclass 39, count 0 2006.259.07:53:00.57#ibcon#read 6, iclass 39, count 0 2006.259.07:53:00.57#ibcon#end of sib2, iclass 39, count 0 2006.259.07:53:00.57#ibcon#*after write, iclass 39, count 0 2006.259.07:53:00.57#ibcon#*before return 0, iclass 39, count 0 2006.259.07:53:00.57#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.259.07:53:00.57#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.259.07:53:00.57#ibcon#about to clear, iclass 39 cls_cnt 0 2006.259.07:53:00.57#ibcon#cleared, iclass 39 cls_cnt 0 2006.259.07:53:00.58$vc4f8/va=6,6 2006.259.07:53:00.58#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.259.07:53:00.58#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.259.07:53:00.58#ibcon#ireg 11 cls_cnt 2 2006.259.07:53:00.58#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.259.07:53:00.62#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.259.07:53:00.62#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.259.07:53:00.62#ibcon#enter wrdev, iclass 3, count 2 2006.259.07:53:00.62#ibcon#first serial, iclass 3, count 2 2006.259.07:53:00.62#ibcon#enter sib2, iclass 3, count 2 2006.259.07:53:00.62#ibcon#flushed, iclass 3, count 2 2006.259.07:53:00.62#ibcon#about to write, iclass 3, count 2 2006.259.07:53:00.62#ibcon#wrote, iclass 3, count 2 2006.259.07:53:00.62#ibcon#about to read 3, iclass 3, count 2 2006.259.07:53:00.64#ibcon#read 3, iclass 3, count 2 2006.259.07:53:00.64#ibcon#about to read 4, iclass 3, count 2 2006.259.07:53:00.64#ibcon#read 4, iclass 3, count 2 2006.259.07:53:00.64#ibcon#about to read 5, iclass 3, count 2 2006.259.07:53:00.64#ibcon#read 5, iclass 3, count 2 2006.259.07:53:00.64#ibcon#about to read 6, iclass 3, count 2 2006.259.07:53:00.64#ibcon#read 6, iclass 3, count 2 2006.259.07:53:00.64#ibcon#end of sib2, iclass 3, count 2 2006.259.07:53:00.64#ibcon#*mode == 0, iclass 3, count 2 2006.259.07:53:00.64#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.259.07:53:00.64#ibcon#[25=AT06-06\r\n] 2006.259.07:53:00.64#ibcon#*before write, iclass 3, count 2 2006.259.07:53:00.64#ibcon#enter sib2, iclass 3, count 2 2006.259.07:53:00.64#ibcon#flushed, iclass 3, count 2 2006.259.07:53:00.64#ibcon#about to write, iclass 3, count 2 2006.259.07:53:00.64#ibcon#wrote, iclass 3, count 2 2006.259.07:53:00.64#ibcon#about to read 3, iclass 3, count 2 2006.259.07:53:00.67#ibcon#read 3, iclass 3, count 2 2006.259.07:53:00.67#ibcon#about to read 4, iclass 3, count 2 2006.259.07:53:00.67#ibcon#read 4, iclass 3, count 2 2006.259.07:53:00.67#ibcon#about to read 5, iclass 3, count 2 2006.259.07:53:00.67#ibcon#read 5, iclass 3, count 2 2006.259.07:53:00.67#ibcon#about to read 6, iclass 3, count 2 2006.259.07:53:00.67#ibcon#read 6, iclass 3, count 2 2006.259.07:53:00.67#ibcon#end of sib2, iclass 3, count 2 2006.259.07:53:00.67#ibcon#*after write, iclass 3, count 2 2006.259.07:53:00.67#ibcon#*before return 0, iclass 3, count 2 2006.259.07:53:00.67#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.259.07:53:00.67#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.259.07:53:00.67#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.259.07:53:00.67#ibcon#ireg 7 cls_cnt 0 2006.259.07:53:00.67#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.259.07:53:00.79#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.259.07:53:00.79#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.259.07:53:00.79#ibcon#enter wrdev, iclass 3, count 0 2006.259.07:53:00.79#ibcon#first serial, iclass 3, count 0 2006.259.07:53:00.79#ibcon#enter sib2, iclass 3, count 0 2006.259.07:53:00.79#ibcon#flushed, iclass 3, count 0 2006.259.07:53:00.79#ibcon#about to write, iclass 3, count 0 2006.259.07:53:00.79#ibcon#wrote, iclass 3, count 0 2006.259.07:53:00.79#ibcon#about to read 3, iclass 3, count 0 2006.259.07:53:00.81#ibcon#read 3, iclass 3, count 0 2006.259.07:53:00.81#ibcon#about to read 4, iclass 3, count 0 2006.259.07:53:00.81#ibcon#read 4, iclass 3, count 0 2006.259.07:53:00.81#ibcon#about to read 5, iclass 3, count 0 2006.259.07:53:00.81#ibcon#read 5, iclass 3, count 0 2006.259.07:53:00.81#ibcon#about to read 6, iclass 3, count 0 2006.259.07:53:00.81#ibcon#read 6, iclass 3, count 0 2006.259.07:53:00.81#ibcon#end of sib2, iclass 3, count 0 2006.259.07:53:00.81#ibcon#*mode == 0, iclass 3, count 0 2006.259.07:53:00.81#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.259.07:53:00.81#ibcon#[25=USB\r\n] 2006.259.07:53:00.81#ibcon#*before write, iclass 3, count 0 2006.259.07:53:00.81#ibcon#enter sib2, iclass 3, count 0 2006.259.07:53:00.81#ibcon#flushed, iclass 3, count 0 2006.259.07:53:00.81#ibcon#about to write, iclass 3, count 0 2006.259.07:53:00.81#ibcon#wrote, iclass 3, count 0 2006.259.07:53:00.81#ibcon#about to read 3, iclass 3, count 0 2006.259.07:53:00.84#ibcon#read 3, iclass 3, count 0 2006.259.07:53:00.84#ibcon#about to read 4, iclass 3, count 0 2006.259.07:53:00.84#ibcon#read 4, iclass 3, count 0 2006.259.07:53:00.84#ibcon#about to read 5, iclass 3, count 0 2006.259.07:53:00.84#ibcon#read 5, iclass 3, count 0 2006.259.07:53:00.84#ibcon#about to read 6, iclass 3, count 0 2006.259.07:53:00.84#ibcon#read 6, iclass 3, count 0 2006.259.07:53:00.84#ibcon#end of sib2, iclass 3, count 0 2006.259.07:53:00.84#ibcon#*after write, iclass 3, count 0 2006.259.07:53:00.84#ibcon#*before return 0, iclass 3, count 0 2006.259.07:53:00.84#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.259.07:53:00.84#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.259.07:53:00.84#ibcon#about to clear, iclass 3 cls_cnt 0 2006.259.07:53:00.84#ibcon#cleared, iclass 3 cls_cnt 0 2006.259.07:53:00.85$vc4f8/valo=7,832.99 2006.259.07:53:00.85#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.259.07:53:00.85#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.259.07:53:00.85#ibcon#ireg 17 cls_cnt 0 2006.259.07:53:00.85#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.259.07:53:00.85#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.259.07:53:00.85#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.259.07:53:00.85#ibcon#enter wrdev, iclass 5, count 0 2006.259.07:53:00.85#ibcon#first serial, iclass 5, count 0 2006.259.07:53:00.85#ibcon#enter sib2, iclass 5, count 0 2006.259.07:53:00.85#ibcon#flushed, iclass 5, count 0 2006.259.07:53:00.85#ibcon#about to write, iclass 5, count 0 2006.259.07:53:00.85#ibcon#wrote, iclass 5, count 0 2006.259.07:53:00.85#ibcon#about to read 3, iclass 5, count 0 2006.259.07:53:00.86#ibcon#read 3, iclass 5, count 0 2006.259.07:53:00.86#ibcon#about to read 4, iclass 5, count 0 2006.259.07:53:00.86#ibcon#read 4, iclass 5, count 0 2006.259.07:53:00.86#ibcon#about to read 5, iclass 5, count 0 2006.259.07:53:00.86#ibcon#read 5, iclass 5, count 0 2006.259.07:53:00.86#ibcon#about to read 6, iclass 5, count 0 2006.259.07:53:00.86#ibcon#read 6, iclass 5, count 0 2006.259.07:53:00.86#ibcon#end of sib2, iclass 5, count 0 2006.259.07:53:00.86#ibcon#*mode == 0, iclass 5, count 0 2006.259.07:53:00.86#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.259.07:53:00.86#ibcon#[26=FRQ=07,832.99\r\n] 2006.259.07:53:00.86#ibcon#*before write, iclass 5, count 0 2006.259.07:53:00.86#ibcon#enter sib2, iclass 5, count 0 2006.259.07:53:00.86#ibcon#flushed, iclass 5, count 0 2006.259.07:53:00.86#ibcon#about to write, iclass 5, count 0 2006.259.07:53:00.86#ibcon#wrote, iclass 5, count 0 2006.259.07:53:00.86#ibcon#about to read 3, iclass 5, count 0 2006.259.07:53:00.90#ibcon#read 3, iclass 5, count 0 2006.259.07:53:00.90#ibcon#about to read 4, iclass 5, count 0 2006.259.07:53:00.90#ibcon#read 4, iclass 5, count 0 2006.259.07:53:00.90#ibcon#about to read 5, iclass 5, count 0 2006.259.07:53:00.90#ibcon#read 5, iclass 5, count 0 2006.259.07:53:00.90#ibcon#about to read 6, iclass 5, count 0 2006.259.07:53:00.90#ibcon#read 6, iclass 5, count 0 2006.259.07:53:00.90#ibcon#end of sib2, iclass 5, count 0 2006.259.07:53:00.90#ibcon#*after write, iclass 5, count 0 2006.259.07:53:00.90#ibcon#*before return 0, iclass 5, count 0 2006.259.07:53:00.90#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.259.07:53:00.90#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.259.07:53:00.90#ibcon#about to clear, iclass 5 cls_cnt 0 2006.259.07:53:00.90#ibcon#cleared, iclass 5 cls_cnt 0 2006.259.07:53:00.91$vc4f8/va=7,6 2006.259.07:53:00.91#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.259.07:53:00.91#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.259.07:53:00.91#ibcon#ireg 11 cls_cnt 2 2006.259.07:53:00.91#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.259.07:53:00.92#abcon#<5=/04 1.9 3.5 22.20 861013.0\r\n> 2006.259.07:53:00.94#abcon#{5=INTERFACE CLEAR} 2006.259.07:53:00.95#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.259.07:53:00.95#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.259.07:53:00.95#ibcon#enter wrdev, iclass 10, count 2 2006.259.07:53:00.95#ibcon#first serial, iclass 10, count 2 2006.259.07:53:00.95#ibcon#enter sib2, iclass 10, count 2 2006.259.07:53:00.95#ibcon#flushed, iclass 10, count 2 2006.259.07:53:00.95#ibcon#about to write, iclass 10, count 2 2006.259.07:53:00.95#ibcon#wrote, iclass 10, count 2 2006.259.07:53:00.95#ibcon#about to read 3, iclass 10, count 2 2006.259.07:53:00.97#ibcon#read 3, iclass 10, count 2 2006.259.07:53:00.97#ibcon#about to read 4, iclass 10, count 2 2006.259.07:53:00.97#ibcon#read 4, iclass 10, count 2 2006.259.07:53:00.97#ibcon#about to read 5, iclass 10, count 2 2006.259.07:53:00.97#ibcon#read 5, iclass 10, count 2 2006.259.07:53:00.97#ibcon#about to read 6, iclass 10, count 2 2006.259.07:53:00.97#ibcon#read 6, iclass 10, count 2 2006.259.07:53:00.97#ibcon#end of sib2, iclass 10, count 2 2006.259.07:53:00.97#ibcon#*mode == 0, iclass 10, count 2 2006.259.07:53:00.97#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.259.07:53:00.97#ibcon#[25=AT07-06\r\n] 2006.259.07:53:00.97#ibcon#*before write, iclass 10, count 2 2006.259.07:53:00.97#ibcon#enter sib2, iclass 10, count 2 2006.259.07:53:00.97#ibcon#flushed, iclass 10, count 2 2006.259.07:53:00.97#ibcon#about to write, iclass 10, count 2 2006.259.07:53:00.97#ibcon#wrote, iclass 10, count 2 2006.259.07:53:00.97#ibcon#about to read 3, iclass 10, count 2 2006.259.07:53:01.00#abcon#[5=S1D000X0/0*\r\n] 2006.259.07:53:01.00#ibcon#read 3, iclass 10, count 2 2006.259.07:53:01.00#ibcon#about to read 4, iclass 10, count 2 2006.259.07:53:01.00#ibcon#read 4, iclass 10, count 2 2006.259.07:53:01.00#ibcon#about to read 5, iclass 10, count 2 2006.259.07:53:01.00#ibcon#read 5, iclass 10, count 2 2006.259.07:53:01.00#ibcon#about to read 6, iclass 10, count 2 2006.259.07:53:01.00#ibcon#read 6, iclass 10, count 2 2006.259.07:53:01.00#ibcon#end of sib2, iclass 10, count 2 2006.259.07:53:01.00#ibcon#*after write, iclass 10, count 2 2006.259.07:53:01.00#ibcon#*before return 0, iclass 10, count 2 2006.259.07:53:01.01#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.259.07:53:01.01#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.259.07:53:01.01#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.259.07:53:01.01#ibcon#ireg 7 cls_cnt 0 2006.259.07:53:01.01#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.259.07:53:01.12#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.259.07:53:01.12#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.259.07:53:01.12#ibcon#enter wrdev, iclass 10, count 0 2006.259.07:53:01.12#ibcon#first serial, iclass 10, count 0 2006.259.07:53:01.12#ibcon#enter sib2, iclass 10, count 0 2006.259.07:53:01.12#ibcon#flushed, iclass 10, count 0 2006.259.07:53:01.12#ibcon#about to write, iclass 10, count 0 2006.259.07:53:01.12#ibcon#wrote, iclass 10, count 0 2006.259.07:53:01.12#ibcon#about to read 3, iclass 10, count 0 2006.259.07:53:01.14#ibcon#read 3, iclass 10, count 0 2006.259.07:53:01.14#ibcon#about to read 4, iclass 10, count 0 2006.259.07:53:01.14#ibcon#read 4, iclass 10, count 0 2006.259.07:53:01.14#ibcon#about to read 5, iclass 10, count 0 2006.259.07:53:01.14#ibcon#read 5, iclass 10, count 0 2006.259.07:53:01.14#ibcon#about to read 6, iclass 10, count 0 2006.259.07:53:01.14#ibcon#read 6, iclass 10, count 0 2006.259.07:53:01.14#ibcon#end of sib2, iclass 10, count 0 2006.259.07:53:01.14#ibcon#*mode == 0, iclass 10, count 0 2006.259.07:53:01.14#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.259.07:53:01.14#ibcon#[25=USB\r\n] 2006.259.07:53:01.14#ibcon#*before write, iclass 10, count 0 2006.259.07:53:01.14#ibcon#enter sib2, iclass 10, count 0 2006.259.07:53:01.14#ibcon#flushed, iclass 10, count 0 2006.259.07:53:01.14#ibcon#about to write, iclass 10, count 0 2006.259.07:53:01.14#ibcon#wrote, iclass 10, count 0 2006.259.07:53:01.14#ibcon#about to read 3, iclass 10, count 0 2006.259.07:53:01.17#ibcon#read 3, iclass 10, count 0 2006.259.07:53:01.17#ibcon#about to read 4, iclass 10, count 0 2006.259.07:53:01.17#ibcon#read 4, iclass 10, count 0 2006.259.07:53:01.17#ibcon#about to read 5, iclass 10, count 0 2006.259.07:53:01.17#ibcon#read 5, iclass 10, count 0 2006.259.07:53:01.17#ibcon#about to read 6, iclass 10, count 0 2006.259.07:53:01.17#ibcon#read 6, iclass 10, count 0 2006.259.07:53:01.17#ibcon#end of sib2, iclass 10, count 0 2006.259.07:53:01.17#ibcon#*after write, iclass 10, count 0 2006.259.07:53:01.17#ibcon#*before return 0, iclass 10, count 0 2006.259.07:53:01.17#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.259.07:53:01.17#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.259.07:53:01.17#ibcon#about to clear, iclass 10 cls_cnt 0 2006.259.07:53:01.17#ibcon#cleared, iclass 10 cls_cnt 0 2006.259.07:53:01.18$vc4f8/valo=8,852.99 2006.259.07:53:01.18#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.259.07:53:01.18#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.259.07:53:01.18#ibcon#ireg 17 cls_cnt 0 2006.259.07:53:01.18#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.259.07:53:01.18#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.259.07:53:01.18#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.259.07:53:01.18#ibcon#enter wrdev, iclass 15, count 0 2006.259.07:53:01.18#ibcon#first serial, iclass 15, count 0 2006.259.07:53:01.18#ibcon#enter sib2, iclass 15, count 0 2006.259.07:53:01.18#ibcon#flushed, iclass 15, count 0 2006.259.07:53:01.18#ibcon#about to write, iclass 15, count 0 2006.259.07:53:01.18#ibcon#wrote, iclass 15, count 0 2006.259.07:53:01.18#ibcon#about to read 3, iclass 15, count 0 2006.259.07:53:01.19#ibcon#read 3, iclass 15, count 0 2006.259.07:53:01.19#ibcon#about to read 4, iclass 15, count 0 2006.259.07:53:01.19#ibcon#read 4, iclass 15, count 0 2006.259.07:53:01.19#ibcon#about to read 5, iclass 15, count 0 2006.259.07:53:01.19#ibcon#read 5, iclass 15, count 0 2006.259.07:53:01.19#ibcon#about to read 6, iclass 15, count 0 2006.259.07:53:01.19#ibcon#read 6, iclass 15, count 0 2006.259.07:53:01.19#ibcon#end of sib2, iclass 15, count 0 2006.259.07:53:01.19#ibcon#*mode == 0, iclass 15, count 0 2006.259.07:53:01.19#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.259.07:53:01.19#ibcon#[26=FRQ=08,852.99\r\n] 2006.259.07:53:01.19#ibcon#*before write, iclass 15, count 0 2006.259.07:53:01.19#ibcon#enter sib2, iclass 15, count 0 2006.259.07:53:01.19#ibcon#flushed, iclass 15, count 0 2006.259.07:53:01.19#ibcon#about to write, iclass 15, count 0 2006.259.07:53:01.19#ibcon#wrote, iclass 15, count 0 2006.259.07:53:01.19#ibcon#about to read 3, iclass 15, count 0 2006.259.07:53:01.23#ibcon#read 3, iclass 15, count 0 2006.259.07:53:01.23#ibcon#about to read 4, iclass 15, count 0 2006.259.07:53:01.23#ibcon#read 4, iclass 15, count 0 2006.259.07:53:01.23#ibcon#about to read 5, iclass 15, count 0 2006.259.07:53:01.23#ibcon#read 5, iclass 15, count 0 2006.259.07:53:01.23#ibcon#about to read 6, iclass 15, count 0 2006.259.07:53:01.23#ibcon#read 6, iclass 15, count 0 2006.259.07:53:01.24#ibcon#end of sib2, iclass 15, count 0 2006.259.07:53:01.24#ibcon#*after write, iclass 15, count 0 2006.259.07:53:01.24#ibcon#*before return 0, iclass 15, count 0 2006.259.07:53:01.24#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.259.07:53:01.24#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.259.07:53:01.24#ibcon#about to clear, iclass 15 cls_cnt 0 2006.259.07:53:01.24#ibcon#cleared, iclass 15 cls_cnt 0 2006.259.07:53:01.24$vc4f8/va=8,6 2006.259.07:53:01.24#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.259.07:53:01.24#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.259.07:53:01.24#ibcon#ireg 11 cls_cnt 2 2006.259.07:53:01.24#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.259.07:53:01.28#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.259.07:53:01.28#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.259.07:53:01.28#ibcon#enter wrdev, iclass 17, count 2 2006.259.07:53:01.28#ibcon#first serial, iclass 17, count 2 2006.259.07:53:01.28#ibcon#enter sib2, iclass 17, count 2 2006.259.07:53:01.28#ibcon#flushed, iclass 17, count 2 2006.259.07:53:01.28#ibcon#about to write, iclass 17, count 2 2006.259.07:53:01.28#ibcon#wrote, iclass 17, count 2 2006.259.07:53:01.28#ibcon#about to read 3, iclass 17, count 2 2006.259.07:53:01.30#ibcon#read 3, iclass 17, count 2 2006.259.07:53:01.30#ibcon#about to read 4, iclass 17, count 2 2006.259.07:53:01.30#ibcon#read 4, iclass 17, count 2 2006.259.07:53:01.30#ibcon#about to read 5, iclass 17, count 2 2006.259.07:53:01.30#ibcon#read 5, iclass 17, count 2 2006.259.07:53:01.30#ibcon#about to read 6, iclass 17, count 2 2006.259.07:53:01.30#ibcon#read 6, iclass 17, count 2 2006.259.07:53:01.30#ibcon#end of sib2, iclass 17, count 2 2006.259.07:53:01.30#ibcon#*mode == 0, iclass 17, count 2 2006.259.07:53:01.30#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.259.07:53:01.30#ibcon#[25=AT08-06\r\n] 2006.259.07:53:01.30#ibcon#*before write, iclass 17, count 2 2006.259.07:53:01.30#ibcon#enter sib2, iclass 17, count 2 2006.259.07:53:01.30#ibcon#flushed, iclass 17, count 2 2006.259.07:53:01.30#ibcon#about to write, iclass 17, count 2 2006.259.07:53:01.30#ibcon#wrote, iclass 17, count 2 2006.259.07:53:01.30#ibcon#about to read 3, iclass 17, count 2 2006.259.07:53:01.33#ibcon#read 3, iclass 17, count 2 2006.259.07:53:01.33#ibcon#about to read 4, iclass 17, count 2 2006.259.07:53:01.33#ibcon#read 4, iclass 17, count 2 2006.259.07:53:01.33#ibcon#about to read 5, iclass 17, count 2 2006.259.07:53:01.33#ibcon#read 5, iclass 17, count 2 2006.259.07:53:01.33#ibcon#about to read 6, iclass 17, count 2 2006.259.07:53:01.33#ibcon#read 6, iclass 17, count 2 2006.259.07:53:01.33#ibcon#end of sib2, iclass 17, count 2 2006.259.07:53:01.33#ibcon#*after write, iclass 17, count 2 2006.259.07:53:01.33#ibcon#*before return 0, iclass 17, count 2 2006.259.07:53:01.33#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.259.07:53:01.33#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.259.07:53:01.33#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.259.07:53:01.33#ibcon#ireg 7 cls_cnt 0 2006.259.07:53:01.33#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.259.07:53:01.45#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.259.07:53:01.45#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.259.07:53:01.45#ibcon#enter wrdev, iclass 17, count 0 2006.259.07:53:01.45#ibcon#first serial, iclass 17, count 0 2006.259.07:53:01.45#ibcon#enter sib2, iclass 17, count 0 2006.259.07:53:01.45#ibcon#flushed, iclass 17, count 0 2006.259.07:53:01.45#ibcon#about to write, iclass 17, count 0 2006.259.07:53:01.45#ibcon#wrote, iclass 17, count 0 2006.259.07:53:01.45#ibcon#about to read 3, iclass 17, count 0 2006.259.07:53:01.48#ibcon#read 3, iclass 17, count 0 2006.259.07:53:01.48#ibcon#about to read 4, iclass 17, count 0 2006.259.07:53:01.48#ibcon#read 4, iclass 17, count 0 2006.259.07:53:01.48#ibcon#about to read 5, iclass 17, count 0 2006.259.07:53:01.48#ibcon#read 5, iclass 17, count 0 2006.259.07:53:01.48#ibcon#about to read 6, iclass 17, count 0 2006.259.07:53:01.48#ibcon#read 6, iclass 17, count 0 2006.259.07:53:01.48#ibcon#end of sib2, iclass 17, count 0 2006.259.07:53:01.48#ibcon#*mode == 0, iclass 17, count 0 2006.259.07:53:01.48#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.259.07:53:01.48#ibcon#[25=USB\r\n] 2006.259.07:53:01.48#ibcon#*before write, iclass 17, count 0 2006.259.07:53:01.48#ibcon#enter sib2, iclass 17, count 0 2006.259.07:53:01.48#ibcon#flushed, iclass 17, count 0 2006.259.07:53:01.48#ibcon#about to write, iclass 17, count 0 2006.259.07:53:01.48#ibcon#wrote, iclass 17, count 0 2006.259.07:53:01.48#ibcon#about to read 3, iclass 17, count 0 2006.259.07:53:01.51#ibcon#read 3, iclass 17, count 0 2006.259.07:53:01.51#ibcon#about to read 4, iclass 17, count 0 2006.259.07:53:01.51#ibcon#read 4, iclass 17, count 0 2006.259.07:53:01.51#ibcon#about to read 5, iclass 17, count 0 2006.259.07:53:01.51#ibcon#read 5, iclass 17, count 0 2006.259.07:53:01.51#ibcon#about to read 6, iclass 17, count 0 2006.259.07:53:01.51#ibcon#read 6, iclass 17, count 0 2006.259.07:53:01.51#ibcon#end of sib2, iclass 17, count 0 2006.259.07:53:01.51#ibcon#*after write, iclass 17, count 0 2006.259.07:53:01.51#ibcon#*before return 0, iclass 17, count 0 2006.259.07:53:01.51#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.259.07:53:01.51#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.259.07:53:01.51#ibcon#about to clear, iclass 17 cls_cnt 0 2006.259.07:53:01.51#ibcon#cleared, iclass 17 cls_cnt 0 2006.259.07:53:01.52$vc4f8/vblo=1,632.99 2006.259.07:53:01.52#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.259.07:53:01.52#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.259.07:53:01.52#ibcon#ireg 17 cls_cnt 0 2006.259.07:53:01.52#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.259.07:53:01.52#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.259.07:53:01.52#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.259.07:53:01.52#ibcon#enter wrdev, iclass 19, count 0 2006.259.07:53:01.52#ibcon#first serial, iclass 19, count 0 2006.259.07:53:01.52#ibcon#enter sib2, iclass 19, count 0 2006.259.07:53:01.52#ibcon#flushed, iclass 19, count 0 2006.259.07:53:01.52#ibcon#about to write, iclass 19, count 0 2006.259.07:53:01.52#ibcon#wrote, iclass 19, count 0 2006.259.07:53:01.52#ibcon#about to read 3, iclass 19, count 0 2006.259.07:53:01.53#ibcon#read 3, iclass 19, count 0 2006.259.07:53:01.53#ibcon#about to read 4, iclass 19, count 0 2006.259.07:53:01.53#ibcon#read 4, iclass 19, count 0 2006.259.07:53:01.53#ibcon#about to read 5, iclass 19, count 0 2006.259.07:53:01.53#ibcon#read 5, iclass 19, count 0 2006.259.07:53:01.53#ibcon#about to read 6, iclass 19, count 0 2006.259.07:53:01.53#ibcon#read 6, iclass 19, count 0 2006.259.07:53:01.53#ibcon#end of sib2, iclass 19, count 0 2006.259.07:53:01.53#ibcon#*mode == 0, iclass 19, count 0 2006.259.07:53:01.53#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.259.07:53:01.53#ibcon#[28=FRQ=01,632.99\r\n] 2006.259.07:53:01.53#ibcon#*before write, iclass 19, count 0 2006.259.07:53:01.53#ibcon#enter sib2, iclass 19, count 0 2006.259.07:53:01.53#ibcon#flushed, iclass 19, count 0 2006.259.07:53:01.53#ibcon#about to write, iclass 19, count 0 2006.259.07:53:01.53#ibcon#wrote, iclass 19, count 0 2006.259.07:53:01.53#ibcon#about to read 3, iclass 19, count 0 2006.259.07:53:01.57#ibcon#read 3, iclass 19, count 0 2006.259.07:53:01.57#ibcon#about to read 4, iclass 19, count 0 2006.259.07:53:01.57#ibcon#read 4, iclass 19, count 0 2006.259.07:53:01.57#ibcon#about to read 5, iclass 19, count 0 2006.259.07:53:01.57#ibcon#read 5, iclass 19, count 0 2006.259.07:53:01.57#ibcon#about to read 6, iclass 19, count 0 2006.259.07:53:01.57#ibcon#read 6, iclass 19, count 0 2006.259.07:53:01.57#ibcon#end of sib2, iclass 19, count 0 2006.259.07:53:01.57#ibcon#*after write, iclass 19, count 0 2006.259.07:53:01.57#ibcon#*before return 0, iclass 19, count 0 2006.259.07:53:01.57#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.259.07:53:01.57#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.259.07:53:01.57#ibcon#about to clear, iclass 19 cls_cnt 0 2006.259.07:53:01.57#ibcon#cleared, iclass 19 cls_cnt 0 2006.259.07:53:01.58$vc4f8/vb=1,4 2006.259.07:53:01.58#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.259.07:53:01.58#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.259.07:53:01.58#ibcon#ireg 11 cls_cnt 2 2006.259.07:53:01.58#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.259.07:53:01.58#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.259.07:53:01.58#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.259.07:53:01.58#ibcon#enter wrdev, iclass 21, count 2 2006.259.07:53:01.58#ibcon#first serial, iclass 21, count 2 2006.259.07:53:01.58#ibcon#enter sib2, iclass 21, count 2 2006.259.07:53:01.58#ibcon#flushed, iclass 21, count 2 2006.259.07:53:01.58#ibcon#about to write, iclass 21, count 2 2006.259.07:53:01.58#ibcon#wrote, iclass 21, count 2 2006.259.07:53:01.58#ibcon#about to read 3, iclass 21, count 2 2006.259.07:53:01.59#ibcon#read 3, iclass 21, count 2 2006.259.07:53:01.59#ibcon#about to read 4, iclass 21, count 2 2006.259.07:53:01.59#ibcon#read 4, iclass 21, count 2 2006.259.07:53:01.59#ibcon#about to read 5, iclass 21, count 2 2006.259.07:53:01.59#ibcon#read 5, iclass 21, count 2 2006.259.07:53:01.59#ibcon#about to read 6, iclass 21, count 2 2006.259.07:53:01.59#ibcon#read 6, iclass 21, count 2 2006.259.07:53:01.59#ibcon#end of sib2, iclass 21, count 2 2006.259.07:53:01.59#ibcon#*mode == 0, iclass 21, count 2 2006.259.07:53:01.59#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.259.07:53:01.59#ibcon#[27=AT01-04\r\n] 2006.259.07:53:01.59#ibcon#*before write, iclass 21, count 2 2006.259.07:53:01.59#ibcon#enter sib2, iclass 21, count 2 2006.259.07:53:01.59#ibcon#flushed, iclass 21, count 2 2006.259.07:53:01.59#ibcon#about to write, iclass 21, count 2 2006.259.07:53:01.59#ibcon#wrote, iclass 21, count 2 2006.259.07:53:01.59#ibcon#about to read 3, iclass 21, count 2 2006.259.07:53:01.62#ibcon#read 3, iclass 21, count 2 2006.259.07:53:01.62#ibcon#about to read 4, iclass 21, count 2 2006.259.07:53:01.62#ibcon#read 4, iclass 21, count 2 2006.259.07:53:01.62#ibcon#about to read 5, iclass 21, count 2 2006.259.07:53:01.62#ibcon#read 5, iclass 21, count 2 2006.259.07:53:01.62#ibcon#about to read 6, iclass 21, count 2 2006.259.07:53:01.62#ibcon#read 6, iclass 21, count 2 2006.259.07:53:01.62#ibcon#end of sib2, iclass 21, count 2 2006.259.07:53:01.62#ibcon#*after write, iclass 21, count 2 2006.259.07:53:01.62#ibcon#*before return 0, iclass 21, count 2 2006.259.07:53:01.62#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.259.07:53:01.62#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.259.07:53:01.62#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.259.07:53:01.62#ibcon#ireg 7 cls_cnt 0 2006.259.07:53:01.62#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.259.07:53:01.75#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.259.07:53:01.75#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.259.07:53:01.75#ibcon#enter wrdev, iclass 21, count 0 2006.259.07:53:01.75#ibcon#first serial, iclass 21, count 0 2006.259.07:53:01.75#ibcon#enter sib2, iclass 21, count 0 2006.259.07:53:01.75#ibcon#flushed, iclass 21, count 0 2006.259.07:53:01.75#ibcon#about to write, iclass 21, count 0 2006.259.07:53:01.75#ibcon#wrote, iclass 21, count 0 2006.259.07:53:01.75#ibcon#about to read 3, iclass 21, count 0 2006.259.07:53:01.76#ibcon#read 3, iclass 21, count 0 2006.259.07:53:01.76#ibcon#about to read 4, iclass 21, count 0 2006.259.07:53:01.76#ibcon#read 4, iclass 21, count 0 2006.259.07:53:01.76#ibcon#about to read 5, iclass 21, count 0 2006.259.07:53:01.76#ibcon#read 5, iclass 21, count 0 2006.259.07:53:01.76#ibcon#about to read 6, iclass 21, count 0 2006.259.07:53:01.76#ibcon#read 6, iclass 21, count 0 2006.259.07:53:01.76#ibcon#end of sib2, iclass 21, count 0 2006.259.07:53:01.76#ibcon#*mode == 0, iclass 21, count 0 2006.259.07:53:01.76#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.259.07:53:01.76#ibcon#[27=USB\r\n] 2006.259.07:53:01.76#ibcon#*before write, iclass 21, count 0 2006.259.07:53:01.76#ibcon#enter sib2, iclass 21, count 0 2006.259.07:53:01.76#ibcon#flushed, iclass 21, count 0 2006.259.07:53:01.76#ibcon#about to write, iclass 21, count 0 2006.259.07:53:01.76#ibcon#wrote, iclass 21, count 0 2006.259.07:53:01.76#ibcon#about to read 3, iclass 21, count 0 2006.259.07:53:01.79#ibcon#read 3, iclass 21, count 0 2006.259.07:53:01.79#ibcon#about to read 4, iclass 21, count 0 2006.259.07:53:01.79#ibcon#read 4, iclass 21, count 0 2006.259.07:53:01.79#ibcon#about to read 5, iclass 21, count 0 2006.259.07:53:01.79#ibcon#read 5, iclass 21, count 0 2006.259.07:53:01.79#ibcon#about to read 6, iclass 21, count 0 2006.259.07:53:01.79#ibcon#read 6, iclass 21, count 0 2006.259.07:53:01.79#ibcon#end of sib2, iclass 21, count 0 2006.259.07:53:01.79#ibcon#*after write, iclass 21, count 0 2006.259.07:53:01.79#ibcon#*before return 0, iclass 21, count 0 2006.259.07:53:01.79#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.259.07:53:01.79#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.259.07:53:01.79#ibcon#about to clear, iclass 21 cls_cnt 0 2006.259.07:53:01.79#ibcon#cleared, iclass 21 cls_cnt 0 2006.259.07:53:01.80$vc4f8/vblo=2,640.99 2006.259.07:53:01.80#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.259.07:53:01.80#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.259.07:53:01.80#ibcon#ireg 17 cls_cnt 0 2006.259.07:53:01.80#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.259.07:53:01.80#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.259.07:53:01.80#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.259.07:53:01.80#ibcon#enter wrdev, iclass 23, count 0 2006.259.07:53:01.80#ibcon#first serial, iclass 23, count 0 2006.259.07:53:01.80#ibcon#enter sib2, iclass 23, count 0 2006.259.07:53:01.80#ibcon#flushed, iclass 23, count 0 2006.259.07:53:01.80#ibcon#about to write, iclass 23, count 0 2006.259.07:53:01.80#ibcon#wrote, iclass 23, count 0 2006.259.07:53:01.80#ibcon#about to read 3, iclass 23, count 0 2006.259.07:53:01.81#ibcon#read 3, iclass 23, count 0 2006.259.07:53:01.81#ibcon#about to read 4, iclass 23, count 0 2006.259.07:53:01.81#ibcon#read 4, iclass 23, count 0 2006.259.07:53:01.81#ibcon#about to read 5, iclass 23, count 0 2006.259.07:53:01.81#ibcon#read 5, iclass 23, count 0 2006.259.07:53:01.81#ibcon#about to read 6, iclass 23, count 0 2006.259.07:53:01.81#ibcon#read 6, iclass 23, count 0 2006.259.07:53:01.81#ibcon#end of sib2, iclass 23, count 0 2006.259.07:53:01.81#ibcon#*mode == 0, iclass 23, count 0 2006.259.07:53:01.81#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.259.07:53:01.81#ibcon#[28=FRQ=02,640.99\r\n] 2006.259.07:53:01.81#ibcon#*before write, iclass 23, count 0 2006.259.07:53:01.81#ibcon#enter sib2, iclass 23, count 0 2006.259.07:53:01.81#ibcon#flushed, iclass 23, count 0 2006.259.07:53:01.81#ibcon#about to write, iclass 23, count 0 2006.259.07:53:01.81#ibcon#wrote, iclass 23, count 0 2006.259.07:53:01.81#ibcon#about to read 3, iclass 23, count 0 2006.259.07:53:01.85#ibcon#read 3, iclass 23, count 0 2006.259.07:53:01.85#ibcon#about to read 4, iclass 23, count 0 2006.259.07:53:01.85#ibcon#read 4, iclass 23, count 0 2006.259.07:53:01.85#ibcon#about to read 5, iclass 23, count 0 2006.259.07:53:01.85#ibcon#read 5, iclass 23, count 0 2006.259.07:53:01.85#ibcon#about to read 6, iclass 23, count 0 2006.259.07:53:01.85#ibcon#read 6, iclass 23, count 0 2006.259.07:53:01.85#ibcon#end of sib2, iclass 23, count 0 2006.259.07:53:01.85#ibcon#*after write, iclass 23, count 0 2006.259.07:53:01.85#ibcon#*before return 0, iclass 23, count 0 2006.259.07:53:01.85#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.259.07:53:01.85#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.259.07:53:01.85#ibcon#about to clear, iclass 23 cls_cnt 0 2006.259.07:53:01.85#ibcon#cleared, iclass 23 cls_cnt 0 2006.259.07:53:01.86$vc4f8/vb=2,5 2006.259.07:53:01.86#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.259.07:53:01.86#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.259.07:53:01.86#ibcon#ireg 11 cls_cnt 2 2006.259.07:53:01.86#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.259.07:53:01.90#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.259.07:53:01.90#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.259.07:53:01.90#ibcon#enter wrdev, iclass 25, count 2 2006.259.07:53:01.90#ibcon#first serial, iclass 25, count 2 2006.259.07:53:01.90#ibcon#enter sib2, iclass 25, count 2 2006.259.07:53:01.90#ibcon#flushed, iclass 25, count 2 2006.259.07:53:01.90#ibcon#about to write, iclass 25, count 2 2006.259.07:53:01.90#ibcon#wrote, iclass 25, count 2 2006.259.07:53:01.90#ibcon#about to read 3, iclass 25, count 2 2006.259.07:53:01.92#ibcon#read 3, iclass 25, count 2 2006.259.07:53:01.92#ibcon#about to read 4, iclass 25, count 2 2006.259.07:53:01.92#ibcon#read 4, iclass 25, count 2 2006.259.07:53:01.92#ibcon#about to read 5, iclass 25, count 2 2006.259.07:53:01.92#ibcon#read 5, iclass 25, count 2 2006.259.07:53:01.92#ibcon#about to read 6, iclass 25, count 2 2006.259.07:53:01.92#ibcon#read 6, iclass 25, count 2 2006.259.07:53:01.92#ibcon#end of sib2, iclass 25, count 2 2006.259.07:53:01.92#ibcon#*mode == 0, iclass 25, count 2 2006.259.07:53:01.92#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.259.07:53:01.92#ibcon#[27=AT02-05\r\n] 2006.259.07:53:01.92#ibcon#*before write, iclass 25, count 2 2006.259.07:53:01.92#ibcon#enter sib2, iclass 25, count 2 2006.259.07:53:01.92#ibcon#flushed, iclass 25, count 2 2006.259.07:53:01.92#ibcon#about to write, iclass 25, count 2 2006.259.07:53:01.92#ibcon#wrote, iclass 25, count 2 2006.259.07:53:01.92#ibcon#about to read 3, iclass 25, count 2 2006.259.07:53:01.95#ibcon#read 3, iclass 25, count 2 2006.259.07:53:01.95#ibcon#about to read 4, iclass 25, count 2 2006.259.07:53:01.95#ibcon#read 4, iclass 25, count 2 2006.259.07:53:01.95#ibcon#about to read 5, iclass 25, count 2 2006.259.07:53:01.95#ibcon#read 5, iclass 25, count 2 2006.259.07:53:01.95#ibcon#about to read 6, iclass 25, count 2 2006.259.07:53:01.95#ibcon#read 6, iclass 25, count 2 2006.259.07:53:01.95#ibcon#end of sib2, iclass 25, count 2 2006.259.07:53:01.95#ibcon#*after write, iclass 25, count 2 2006.259.07:53:01.95#ibcon#*before return 0, iclass 25, count 2 2006.259.07:53:01.95#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.259.07:53:01.95#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.259.07:53:01.95#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.259.07:53:01.95#ibcon#ireg 7 cls_cnt 0 2006.259.07:53:01.95#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.259.07:53:02.07#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.259.07:53:02.07#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.259.07:53:02.07#ibcon#enter wrdev, iclass 25, count 0 2006.259.07:53:02.07#ibcon#first serial, iclass 25, count 0 2006.259.07:53:02.07#ibcon#enter sib2, iclass 25, count 0 2006.259.07:53:02.07#ibcon#flushed, iclass 25, count 0 2006.259.07:53:02.07#ibcon#about to write, iclass 25, count 0 2006.259.07:53:02.07#ibcon#wrote, iclass 25, count 0 2006.259.07:53:02.07#ibcon#about to read 3, iclass 25, count 0 2006.259.07:53:02.09#ibcon#read 3, iclass 25, count 0 2006.259.07:53:02.09#ibcon#about to read 4, iclass 25, count 0 2006.259.07:53:02.09#ibcon#read 4, iclass 25, count 0 2006.259.07:53:02.09#ibcon#about to read 5, iclass 25, count 0 2006.259.07:53:02.09#ibcon#read 5, iclass 25, count 0 2006.259.07:53:02.09#ibcon#about to read 6, iclass 25, count 0 2006.259.07:53:02.09#ibcon#read 6, iclass 25, count 0 2006.259.07:53:02.09#ibcon#end of sib2, iclass 25, count 0 2006.259.07:53:02.09#ibcon#*mode == 0, iclass 25, count 0 2006.259.07:53:02.09#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.259.07:53:02.09#ibcon#[27=USB\r\n] 2006.259.07:53:02.09#ibcon#*before write, iclass 25, count 0 2006.259.07:53:02.09#ibcon#enter sib2, iclass 25, count 0 2006.259.07:53:02.09#ibcon#flushed, iclass 25, count 0 2006.259.07:53:02.09#ibcon#about to write, iclass 25, count 0 2006.259.07:53:02.09#ibcon#wrote, iclass 25, count 0 2006.259.07:53:02.09#ibcon#about to read 3, iclass 25, count 0 2006.259.07:53:02.12#ibcon#read 3, iclass 25, count 0 2006.259.07:53:02.12#ibcon#about to read 4, iclass 25, count 0 2006.259.07:53:02.12#ibcon#read 4, iclass 25, count 0 2006.259.07:53:02.12#ibcon#about to read 5, iclass 25, count 0 2006.259.07:53:02.12#ibcon#read 5, iclass 25, count 0 2006.259.07:53:02.12#ibcon#about to read 6, iclass 25, count 0 2006.259.07:53:02.12#ibcon#read 6, iclass 25, count 0 2006.259.07:53:02.12#ibcon#end of sib2, iclass 25, count 0 2006.259.07:53:02.12#ibcon#*after write, iclass 25, count 0 2006.259.07:53:02.12#ibcon#*before return 0, iclass 25, count 0 2006.259.07:53:02.12#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.259.07:53:02.12#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.259.07:53:02.12#ibcon#about to clear, iclass 25 cls_cnt 0 2006.259.07:53:02.12#ibcon#cleared, iclass 25 cls_cnt 0 2006.259.07:53:02.13$vc4f8/vblo=3,656.99 2006.259.07:53:02.13#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.259.07:53:02.13#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.259.07:53:02.13#ibcon#ireg 17 cls_cnt 0 2006.259.07:53:02.13#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.259.07:53:02.13#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.259.07:53:02.13#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.259.07:53:02.13#ibcon#enter wrdev, iclass 27, count 0 2006.259.07:53:02.13#ibcon#first serial, iclass 27, count 0 2006.259.07:53:02.13#ibcon#enter sib2, iclass 27, count 0 2006.259.07:53:02.13#ibcon#flushed, iclass 27, count 0 2006.259.07:53:02.13#ibcon#about to write, iclass 27, count 0 2006.259.07:53:02.13#ibcon#wrote, iclass 27, count 0 2006.259.07:53:02.13#ibcon#about to read 3, iclass 27, count 0 2006.259.07:53:02.14#ibcon#read 3, iclass 27, count 0 2006.259.07:53:02.14#ibcon#about to read 4, iclass 27, count 0 2006.259.07:53:02.14#ibcon#read 4, iclass 27, count 0 2006.259.07:53:02.14#ibcon#about to read 5, iclass 27, count 0 2006.259.07:53:02.14#ibcon#read 5, iclass 27, count 0 2006.259.07:53:02.14#ibcon#about to read 6, iclass 27, count 0 2006.259.07:53:02.14#ibcon#read 6, iclass 27, count 0 2006.259.07:53:02.14#ibcon#end of sib2, iclass 27, count 0 2006.259.07:53:02.14#ibcon#*mode == 0, iclass 27, count 0 2006.259.07:53:02.14#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.259.07:53:02.14#ibcon#[28=FRQ=03,656.99\r\n] 2006.259.07:53:02.14#ibcon#*before write, iclass 27, count 0 2006.259.07:53:02.14#ibcon#enter sib2, iclass 27, count 0 2006.259.07:53:02.14#ibcon#flushed, iclass 27, count 0 2006.259.07:53:02.14#ibcon#about to write, iclass 27, count 0 2006.259.07:53:02.14#ibcon#wrote, iclass 27, count 0 2006.259.07:53:02.14#ibcon#about to read 3, iclass 27, count 0 2006.259.07:53:02.18#ibcon#read 3, iclass 27, count 0 2006.259.07:53:02.18#ibcon#about to read 4, iclass 27, count 0 2006.259.07:53:02.18#ibcon#read 4, iclass 27, count 0 2006.259.07:53:02.18#ibcon#about to read 5, iclass 27, count 0 2006.259.07:53:02.18#ibcon#read 5, iclass 27, count 0 2006.259.07:53:02.18#ibcon#about to read 6, iclass 27, count 0 2006.259.07:53:02.18#ibcon#read 6, iclass 27, count 0 2006.259.07:53:02.18#ibcon#end of sib2, iclass 27, count 0 2006.259.07:53:02.18#ibcon#*after write, iclass 27, count 0 2006.259.07:53:02.18#ibcon#*before return 0, iclass 27, count 0 2006.259.07:53:02.18#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.259.07:53:02.18#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.259.07:53:02.18#ibcon#about to clear, iclass 27 cls_cnt 0 2006.259.07:53:02.18#ibcon#cleared, iclass 27 cls_cnt 0 2006.259.07:53:02.19$vc4f8/vb=3,4 2006.259.07:53:02.19#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.259.07:53:02.19#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.259.07:53:02.19#ibcon#ireg 11 cls_cnt 2 2006.259.07:53:02.19#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.259.07:53:02.23#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.259.07:53:02.23#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.259.07:53:02.23#ibcon#enter wrdev, iclass 29, count 2 2006.259.07:53:02.23#ibcon#first serial, iclass 29, count 2 2006.259.07:53:02.23#ibcon#enter sib2, iclass 29, count 2 2006.259.07:53:02.23#ibcon#flushed, iclass 29, count 2 2006.259.07:53:02.23#ibcon#about to write, iclass 29, count 2 2006.259.07:53:02.23#ibcon#wrote, iclass 29, count 2 2006.259.07:53:02.23#ibcon#about to read 3, iclass 29, count 2 2006.259.07:53:02.25#ibcon#read 3, iclass 29, count 2 2006.259.07:53:02.25#ibcon#about to read 4, iclass 29, count 2 2006.259.07:53:02.25#ibcon#read 4, iclass 29, count 2 2006.259.07:53:02.25#ibcon#about to read 5, iclass 29, count 2 2006.259.07:53:02.25#ibcon#read 5, iclass 29, count 2 2006.259.07:53:02.25#ibcon#about to read 6, iclass 29, count 2 2006.259.07:53:02.25#ibcon#read 6, iclass 29, count 2 2006.259.07:53:02.25#ibcon#end of sib2, iclass 29, count 2 2006.259.07:53:02.25#ibcon#*mode == 0, iclass 29, count 2 2006.259.07:53:02.25#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.259.07:53:02.25#ibcon#[27=AT03-04\r\n] 2006.259.07:53:02.25#ibcon#*before write, iclass 29, count 2 2006.259.07:53:02.25#ibcon#enter sib2, iclass 29, count 2 2006.259.07:53:02.25#ibcon#flushed, iclass 29, count 2 2006.259.07:53:02.25#ibcon#about to write, iclass 29, count 2 2006.259.07:53:02.25#ibcon#wrote, iclass 29, count 2 2006.259.07:53:02.25#ibcon#about to read 3, iclass 29, count 2 2006.259.07:53:02.28#ibcon#read 3, iclass 29, count 2 2006.259.07:53:02.28#ibcon#about to read 4, iclass 29, count 2 2006.259.07:53:02.28#ibcon#read 4, iclass 29, count 2 2006.259.07:53:02.28#ibcon#about to read 5, iclass 29, count 2 2006.259.07:53:02.28#ibcon#read 5, iclass 29, count 2 2006.259.07:53:02.28#ibcon#about to read 6, iclass 29, count 2 2006.259.07:53:02.28#ibcon#read 6, iclass 29, count 2 2006.259.07:53:02.28#ibcon#end of sib2, iclass 29, count 2 2006.259.07:53:02.28#ibcon#*after write, iclass 29, count 2 2006.259.07:53:02.28#ibcon#*before return 0, iclass 29, count 2 2006.259.07:53:02.28#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.259.07:53:02.28#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.259.07:53:02.28#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.259.07:53:02.28#ibcon#ireg 7 cls_cnt 0 2006.259.07:53:02.28#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.259.07:53:02.40#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.259.07:53:02.40#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.259.07:53:02.40#ibcon#enter wrdev, iclass 29, count 0 2006.259.07:53:02.40#ibcon#first serial, iclass 29, count 0 2006.259.07:53:02.40#ibcon#enter sib2, iclass 29, count 0 2006.259.07:53:02.40#ibcon#flushed, iclass 29, count 0 2006.259.07:53:02.40#ibcon#about to write, iclass 29, count 0 2006.259.07:53:02.40#ibcon#wrote, iclass 29, count 0 2006.259.07:53:02.40#ibcon#about to read 3, iclass 29, count 0 2006.259.07:53:02.42#ibcon#read 3, iclass 29, count 0 2006.259.07:53:02.42#ibcon#about to read 4, iclass 29, count 0 2006.259.07:53:02.42#ibcon#read 4, iclass 29, count 0 2006.259.07:53:02.42#ibcon#about to read 5, iclass 29, count 0 2006.259.07:53:02.42#ibcon#read 5, iclass 29, count 0 2006.259.07:53:02.42#ibcon#about to read 6, iclass 29, count 0 2006.259.07:53:02.42#ibcon#read 6, iclass 29, count 0 2006.259.07:53:02.42#ibcon#end of sib2, iclass 29, count 0 2006.259.07:53:02.42#ibcon#*mode == 0, iclass 29, count 0 2006.259.07:53:02.42#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.259.07:53:02.42#ibcon#[27=USB\r\n] 2006.259.07:53:02.42#ibcon#*before write, iclass 29, count 0 2006.259.07:53:02.42#ibcon#enter sib2, iclass 29, count 0 2006.259.07:53:02.42#ibcon#flushed, iclass 29, count 0 2006.259.07:53:02.42#ibcon#about to write, iclass 29, count 0 2006.259.07:53:02.42#ibcon#wrote, iclass 29, count 0 2006.259.07:53:02.42#ibcon#about to read 3, iclass 29, count 0 2006.259.07:53:02.45#ibcon#read 3, iclass 29, count 0 2006.259.07:53:02.45#ibcon#about to read 4, iclass 29, count 0 2006.259.07:53:02.45#ibcon#read 4, iclass 29, count 0 2006.259.07:53:02.45#ibcon#about to read 5, iclass 29, count 0 2006.259.07:53:02.45#ibcon#read 5, iclass 29, count 0 2006.259.07:53:02.45#ibcon#about to read 6, iclass 29, count 0 2006.259.07:53:02.45#ibcon#read 6, iclass 29, count 0 2006.259.07:53:02.45#ibcon#end of sib2, iclass 29, count 0 2006.259.07:53:02.45#ibcon#*after write, iclass 29, count 0 2006.259.07:53:02.45#ibcon#*before return 0, iclass 29, count 0 2006.259.07:53:02.45#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.259.07:53:02.45#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.259.07:53:02.45#ibcon#about to clear, iclass 29 cls_cnt 0 2006.259.07:53:02.45#ibcon#cleared, iclass 29 cls_cnt 0 2006.259.07:53:02.46$vc4f8/vblo=4,712.99 2006.259.07:53:02.46#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.259.07:53:02.46#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.259.07:53:02.46#ibcon#ireg 17 cls_cnt 0 2006.259.07:53:02.46#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.259.07:53:02.46#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.259.07:53:02.46#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.259.07:53:02.46#ibcon#enter wrdev, iclass 31, count 0 2006.259.07:53:02.46#ibcon#first serial, iclass 31, count 0 2006.259.07:53:02.46#ibcon#enter sib2, iclass 31, count 0 2006.259.07:53:02.46#ibcon#flushed, iclass 31, count 0 2006.259.07:53:02.46#ibcon#about to write, iclass 31, count 0 2006.259.07:53:02.46#ibcon#wrote, iclass 31, count 0 2006.259.07:53:02.46#ibcon#about to read 3, iclass 31, count 0 2006.259.07:53:02.47#ibcon#read 3, iclass 31, count 0 2006.259.07:53:02.47#ibcon#about to read 4, iclass 31, count 0 2006.259.07:53:02.47#ibcon#read 4, iclass 31, count 0 2006.259.07:53:02.47#ibcon#about to read 5, iclass 31, count 0 2006.259.07:53:02.47#ibcon#read 5, iclass 31, count 0 2006.259.07:53:02.47#ibcon#about to read 6, iclass 31, count 0 2006.259.07:53:02.47#ibcon#read 6, iclass 31, count 0 2006.259.07:53:02.47#ibcon#end of sib2, iclass 31, count 0 2006.259.07:53:02.47#ibcon#*mode == 0, iclass 31, count 0 2006.259.07:53:02.47#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.259.07:53:02.47#ibcon#[28=FRQ=04,712.99\r\n] 2006.259.07:53:02.47#ibcon#*before write, iclass 31, count 0 2006.259.07:53:02.47#ibcon#enter sib2, iclass 31, count 0 2006.259.07:53:02.47#ibcon#flushed, iclass 31, count 0 2006.259.07:53:02.47#ibcon#about to write, iclass 31, count 0 2006.259.07:53:02.47#ibcon#wrote, iclass 31, count 0 2006.259.07:53:02.47#ibcon#about to read 3, iclass 31, count 0 2006.259.07:53:02.51#ibcon#read 3, iclass 31, count 0 2006.259.07:53:02.51#ibcon#about to read 4, iclass 31, count 0 2006.259.07:53:02.51#ibcon#read 4, iclass 31, count 0 2006.259.07:53:02.51#ibcon#about to read 5, iclass 31, count 0 2006.259.07:53:02.51#ibcon#read 5, iclass 31, count 0 2006.259.07:53:02.51#ibcon#about to read 6, iclass 31, count 0 2006.259.07:53:02.51#ibcon#read 6, iclass 31, count 0 2006.259.07:53:02.51#ibcon#end of sib2, iclass 31, count 0 2006.259.07:53:02.51#ibcon#*after write, iclass 31, count 0 2006.259.07:53:02.51#ibcon#*before return 0, iclass 31, count 0 2006.259.07:53:02.51#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.259.07:53:02.51#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.259.07:53:02.51#ibcon#about to clear, iclass 31 cls_cnt 0 2006.259.07:53:02.51#ibcon#cleared, iclass 31 cls_cnt 0 2006.259.07:53:02.52$vc4f8/vb=4,5 2006.259.07:53:02.52#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.259.07:53:02.52#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.259.07:53:02.52#ibcon#ireg 11 cls_cnt 2 2006.259.07:53:02.52#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.259.07:53:02.56#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.259.07:53:02.56#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.259.07:53:02.56#ibcon#enter wrdev, iclass 33, count 2 2006.259.07:53:02.56#ibcon#first serial, iclass 33, count 2 2006.259.07:53:02.56#ibcon#enter sib2, iclass 33, count 2 2006.259.07:53:02.56#ibcon#flushed, iclass 33, count 2 2006.259.07:53:02.56#ibcon#about to write, iclass 33, count 2 2006.259.07:53:02.56#ibcon#wrote, iclass 33, count 2 2006.259.07:53:02.56#ibcon#about to read 3, iclass 33, count 2 2006.259.07:53:02.58#ibcon#read 3, iclass 33, count 2 2006.259.07:53:02.58#ibcon#about to read 4, iclass 33, count 2 2006.259.07:53:02.58#ibcon#read 4, iclass 33, count 2 2006.259.07:53:02.58#ibcon#about to read 5, iclass 33, count 2 2006.259.07:53:02.58#ibcon#read 5, iclass 33, count 2 2006.259.07:53:02.58#ibcon#about to read 6, iclass 33, count 2 2006.259.07:53:02.58#ibcon#read 6, iclass 33, count 2 2006.259.07:53:02.58#ibcon#end of sib2, iclass 33, count 2 2006.259.07:53:02.58#ibcon#*mode == 0, iclass 33, count 2 2006.259.07:53:02.58#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.259.07:53:02.58#ibcon#[27=AT04-05\r\n] 2006.259.07:53:02.58#ibcon#*before write, iclass 33, count 2 2006.259.07:53:02.58#ibcon#enter sib2, iclass 33, count 2 2006.259.07:53:02.58#ibcon#flushed, iclass 33, count 2 2006.259.07:53:02.58#ibcon#about to write, iclass 33, count 2 2006.259.07:53:02.58#ibcon#wrote, iclass 33, count 2 2006.259.07:53:02.58#ibcon#about to read 3, iclass 33, count 2 2006.259.07:53:02.62#ibcon#read 3, iclass 33, count 2 2006.259.07:53:02.62#ibcon#about to read 4, iclass 33, count 2 2006.259.07:53:02.62#ibcon#read 4, iclass 33, count 2 2006.259.07:53:02.62#ibcon#about to read 5, iclass 33, count 2 2006.259.07:53:02.62#ibcon#read 5, iclass 33, count 2 2006.259.07:53:02.62#ibcon#about to read 6, iclass 33, count 2 2006.259.07:53:02.62#ibcon#read 6, iclass 33, count 2 2006.259.07:53:02.62#ibcon#end of sib2, iclass 33, count 2 2006.259.07:53:02.62#ibcon#*after write, iclass 33, count 2 2006.259.07:53:02.62#ibcon#*before return 0, iclass 33, count 2 2006.259.07:53:02.62#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.259.07:53:02.62#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.259.07:53:02.62#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.259.07:53:02.62#ibcon#ireg 7 cls_cnt 0 2006.259.07:53:02.62#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.259.07:53:02.73#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.259.07:53:02.73#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.259.07:53:02.73#ibcon#enter wrdev, iclass 33, count 0 2006.259.07:53:02.73#ibcon#first serial, iclass 33, count 0 2006.259.07:53:02.73#ibcon#enter sib2, iclass 33, count 0 2006.259.07:53:02.73#ibcon#flushed, iclass 33, count 0 2006.259.07:53:02.73#ibcon#about to write, iclass 33, count 0 2006.259.07:53:02.73#ibcon#wrote, iclass 33, count 0 2006.259.07:53:02.73#ibcon#about to read 3, iclass 33, count 0 2006.259.07:53:02.75#ibcon#read 3, iclass 33, count 0 2006.259.07:53:02.75#ibcon#about to read 4, iclass 33, count 0 2006.259.07:53:02.75#ibcon#read 4, iclass 33, count 0 2006.259.07:53:02.75#ibcon#about to read 5, iclass 33, count 0 2006.259.07:53:02.75#ibcon#read 5, iclass 33, count 0 2006.259.07:53:02.75#ibcon#about to read 6, iclass 33, count 0 2006.259.07:53:02.75#ibcon#read 6, iclass 33, count 0 2006.259.07:53:02.75#ibcon#end of sib2, iclass 33, count 0 2006.259.07:53:02.75#ibcon#*mode == 0, iclass 33, count 0 2006.259.07:53:02.75#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.259.07:53:02.75#ibcon#[27=USB\r\n] 2006.259.07:53:02.75#ibcon#*before write, iclass 33, count 0 2006.259.07:53:02.75#ibcon#enter sib2, iclass 33, count 0 2006.259.07:53:02.75#ibcon#flushed, iclass 33, count 0 2006.259.07:53:02.75#ibcon#about to write, iclass 33, count 0 2006.259.07:53:02.75#ibcon#wrote, iclass 33, count 0 2006.259.07:53:02.75#ibcon#about to read 3, iclass 33, count 0 2006.259.07:53:02.78#ibcon#read 3, iclass 33, count 0 2006.259.07:53:02.78#ibcon#about to read 4, iclass 33, count 0 2006.259.07:53:02.78#ibcon#read 4, iclass 33, count 0 2006.259.07:53:02.78#ibcon#about to read 5, iclass 33, count 0 2006.259.07:53:02.78#ibcon#read 5, iclass 33, count 0 2006.259.07:53:02.78#ibcon#about to read 6, iclass 33, count 0 2006.259.07:53:02.78#ibcon#read 6, iclass 33, count 0 2006.259.07:53:02.78#ibcon#end of sib2, iclass 33, count 0 2006.259.07:53:02.78#ibcon#*after write, iclass 33, count 0 2006.259.07:53:02.78#ibcon#*before return 0, iclass 33, count 0 2006.259.07:53:02.78#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.259.07:53:02.78#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.259.07:53:02.78#ibcon#about to clear, iclass 33 cls_cnt 0 2006.259.07:53:02.78#ibcon#cleared, iclass 33 cls_cnt 0 2006.259.07:53:02.79$vc4f8/vblo=5,744.99 2006.259.07:53:02.79#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.259.07:53:02.79#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.259.07:53:02.79#ibcon#ireg 17 cls_cnt 0 2006.259.07:53:02.79#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.259.07:53:02.79#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.259.07:53:02.79#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.259.07:53:02.79#ibcon#enter wrdev, iclass 35, count 0 2006.259.07:53:02.79#ibcon#first serial, iclass 35, count 0 2006.259.07:53:02.79#ibcon#enter sib2, iclass 35, count 0 2006.259.07:53:02.79#ibcon#flushed, iclass 35, count 0 2006.259.07:53:02.79#ibcon#about to write, iclass 35, count 0 2006.259.07:53:02.79#ibcon#wrote, iclass 35, count 0 2006.259.07:53:02.79#ibcon#about to read 3, iclass 35, count 0 2006.259.07:53:02.80#ibcon#read 3, iclass 35, count 0 2006.259.07:53:02.80#ibcon#about to read 4, iclass 35, count 0 2006.259.07:53:02.80#ibcon#read 4, iclass 35, count 0 2006.259.07:53:02.80#ibcon#about to read 5, iclass 35, count 0 2006.259.07:53:02.80#ibcon#read 5, iclass 35, count 0 2006.259.07:53:02.80#ibcon#about to read 6, iclass 35, count 0 2006.259.07:53:02.80#ibcon#read 6, iclass 35, count 0 2006.259.07:53:02.80#ibcon#end of sib2, iclass 35, count 0 2006.259.07:53:02.80#ibcon#*mode == 0, iclass 35, count 0 2006.259.07:53:02.80#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.259.07:53:02.80#ibcon#[28=FRQ=05,744.99\r\n] 2006.259.07:53:02.80#ibcon#*before write, iclass 35, count 0 2006.259.07:53:02.80#ibcon#enter sib2, iclass 35, count 0 2006.259.07:53:02.80#ibcon#flushed, iclass 35, count 0 2006.259.07:53:02.80#ibcon#about to write, iclass 35, count 0 2006.259.07:53:02.80#ibcon#wrote, iclass 35, count 0 2006.259.07:53:02.80#ibcon#about to read 3, iclass 35, count 0 2006.259.07:53:02.84#ibcon#read 3, iclass 35, count 0 2006.259.07:53:02.84#ibcon#about to read 4, iclass 35, count 0 2006.259.07:53:02.84#ibcon#read 4, iclass 35, count 0 2006.259.07:53:02.84#ibcon#about to read 5, iclass 35, count 0 2006.259.07:53:02.84#ibcon#read 5, iclass 35, count 0 2006.259.07:53:02.84#ibcon#about to read 6, iclass 35, count 0 2006.259.07:53:02.84#ibcon#read 6, iclass 35, count 0 2006.259.07:53:02.84#ibcon#end of sib2, iclass 35, count 0 2006.259.07:53:02.84#ibcon#*after write, iclass 35, count 0 2006.259.07:53:02.84#ibcon#*before return 0, iclass 35, count 0 2006.259.07:53:02.84#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.259.07:53:02.84#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.259.07:53:02.84#ibcon#about to clear, iclass 35 cls_cnt 0 2006.259.07:53:02.84#ibcon#cleared, iclass 35 cls_cnt 0 2006.259.07:53:02.85$vc4f8/vb=5,4 2006.259.07:53:02.85#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.259.07:53:02.85#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.259.07:53:02.85#ibcon#ireg 11 cls_cnt 2 2006.259.07:53:02.85#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.259.07:53:02.89#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.259.07:53:02.89#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.259.07:53:02.89#ibcon#enter wrdev, iclass 37, count 2 2006.259.07:53:02.89#ibcon#first serial, iclass 37, count 2 2006.259.07:53:02.89#ibcon#enter sib2, iclass 37, count 2 2006.259.07:53:02.89#ibcon#flushed, iclass 37, count 2 2006.259.07:53:02.89#ibcon#about to write, iclass 37, count 2 2006.259.07:53:02.89#ibcon#wrote, iclass 37, count 2 2006.259.07:53:02.89#ibcon#about to read 3, iclass 37, count 2 2006.259.07:53:02.91#ibcon#read 3, iclass 37, count 2 2006.259.07:53:02.91#ibcon#about to read 4, iclass 37, count 2 2006.259.07:53:02.91#ibcon#read 4, iclass 37, count 2 2006.259.07:53:02.91#ibcon#about to read 5, iclass 37, count 2 2006.259.07:53:02.91#ibcon#read 5, iclass 37, count 2 2006.259.07:53:02.91#ibcon#about to read 6, iclass 37, count 2 2006.259.07:53:02.91#ibcon#read 6, iclass 37, count 2 2006.259.07:53:02.91#ibcon#end of sib2, iclass 37, count 2 2006.259.07:53:02.91#ibcon#*mode == 0, iclass 37, count 2 2006.259.07:53:02.91#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.259.07:53:02.91#ibcon#[27=AT05-04\r\n] 2006.259.07:53:02.91#ibcon#*before write, iclass 37, count 2 2006.259.07:53:02.91#ibcon#enter sib2, iclass 37, count 2 2006.259.07:53:02.91#ibcon#flushed, iclass 37, count 2 2006.259.07:53:02.91#ibcon#about to write, iclass 37, count 2 2006.259.07:53:02.91#ibcon#wrote, iclass 37, count 2 2006.259.07:53:02.91#ibcon#about to read 3, iclass 37, count 2 2006.259.07:53:02.94#ibcon#read 3, iclass 37, count 2 2006.259.07:53:02.94#ibcon#about to read 4, iclass 37, count 2 2006.259.07:53:02.94#ibcon#read 4, iclass 37, count 2 2006.259.07:53:02.94#ibcon#about to read 5, iclass 37, count 2 2006.259.07:53:02.94#ibcon#read 5, iclass 37, count 2 2006.259.07:53:02.94#ibcon#about to read 6, iclass 37, count 2 2006.259.07:53:02.94#ibcon#read 6, iclass 37, count 2 2006.259.07:53:02.94#ibcon#end of sib2, iclass 37, count 2 2006.259.07:53:02.94#ibcon#*after write, iclass 37, count 2 2006.259.07:53:02.94#ibcon#*before return 0, iclass 37, count 2 2006.259.07:53:02.94#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.259.07:53:02.94#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.259.07:53:02.94#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.259.07:53:02.94#ibcon#ireg 7 cls_cnt 0 2006.259.07:53:02.94#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.259.07:53:03.06#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.259.07:53:03.06#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.259.07:53:03.06#ibcon#enter wrdev, iclass 37, count 0 2006.259.07:53:03.06#ibcon#first serial, iclass 37, count 0 2006.259.07:53:03.06#ibcon#enter sib2, iclass 37, count 0 2006.259.07:53:03.06#ibcon#flushed, iclass 37, count 0 2006.259.07:53:03.06#ibcon#about to write, iclass 37, count 0 2006.259.07:53:03.06#ibcon#wrote, iclass 37, count 0 2006.259.07:53:03.06#ibcon#about to read 3, iclass 37, count 0 2006.259.07:53:03.08#ibcon#read 3, iclass 37, count 0 2006.259.07:53:03.08#ibcon#about to read 4, iclass 37, count 0 2006.259.07:53:03.08#ibcon#read 4, iclass 37, count 0 2006.259.07:53:03.08#ibcon#about to read 5, iclass 37, count 0 2006.259.07:53:03.08#ibcon#read 5, iclass 37, count 0 2006.259.07:53:03.08#ibcon#about to read 6, iclass 37, count 0 2006.259.07:53:03.08#ibcon#read 6, iclass 37, count 0 2006.259.07:53:03.08#ibcon#end of sib2, iclass 37, count 0 2006.259.07:53:03.08#ibcon#*mode == 0, iclass 37, count 0 2006.259.07:53:03.08#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.259.07:53:03.08#ibcon#[27=USB\r\n] 2006.259.07:53:03.08#ibcon#*before write, iclass 37, count 0 2006.259.07:53:03.08#ibcon#enter sib2, iclass 37, count 0 2006.259.07:53:03.08#ibcon#flushed, iclass 37, count 0 2006.259.07:53:03.08#ibcon#about to write, iclass 37, count 0 2006.259.07:53:03.08#ibcon#wrote, iclass 37, count 0 2006.259.07:53:03.08#ibcon#about to read 3, iclass 37, count 0 2006.259.07:53:03.11#ibcon#read 3, iclass 37, count 0 2006.259.07:53:03.11#ibcon#about to read 4, iclass 37, count 0 2006.259.07:53:03.11#ibcon#read 4, iclass 37, count 0 2006.259.07:53:03.11#ibcon#about to read 5, iclass 37, count 0 2006.259.07:53:03.11#ibcon#read 5, iclass 37, count 0 2006.259.07:53:03.11#ibcon#about to read 6, iclass 37, count 0 2006.259.07:53:03.11#ibcon#read 6, iclass 37, count 0 2006.259.07:53:03.11#ibcon#end of sib2, iclass 37, count 0 2006.259.07:53:03.11#ibcon#*after write, iclass 37, count 0 2006.259.07:53:03.11#ibcon#*before return 0, iclass 37, count 0 2006.259.07:53:03.11#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.259.07:53:03.11#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.259.07:53:03.11#ibcon#about to clear, iclass 37 cls_cnt 0 2006.259.07:53:03.11#ibcon#cleared, iclass 37 cls_cnt 0 2006.259.07:53:03.12$vc4f8/vblo=6,752.99 2006.259.07:53:03.12#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.259.07:53:03.12#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.259.07:53:03.12#ibcon#ireg 17 cls_cnt 0 2006.259.07:53:03.12#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.259.07:53:03.12#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.259.07:53:03.12#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.259.07:53:03.12#ibcon#enter wrdev, iclass 39, count 0 2006.259.07:53:03.12#ibcon#first serial, iclass 39, count 0 2006.259.07:53:03.12#ibcon#enter sib2, iclass 39, count 0 2006.259.07:53:03.12#ibcon#flushed, iclass 39, count 0 2006.259.07:53:03.12#ibcon#about to write, iclass 39, count 0 2006.259.07:53:03.12#ibcon#wrote, iclass 39, count 0 2006.259.07:53:03.12#ibcon#about to read 3, iclass 39, count 0 2006.259.07:53:03.13#ibcon#read 3, iclass 39, count 0 2006.259.07:53:03.13#ibcon#about to read 4, iclass 39, count 0 2006.259.07:53:03.13#ibcon#read 4, iclass 39, count 0 2006.259.07:53:03.13#ibcon#about to read 5, iclass 39, count 0 2006.259.07:53:03.13#ibcon#read 5, iclass 39, count 0 2006.259.07:53:03.13#ibcon#about to read 6, iclass 39, count 0 2006.259.07:53:03.13#ibcon#read 6, iclass 39, count 0 2006.259.07:53:03.13#ibcon#end of sib2, iclass 39, count 0 2006.259.07:53:03.13#ibcon#*mode == 0, iclass 39, count 0 2006.259.07:53:03.13#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.259.07:53:03.13#ibcon#[28=FRQ=06,752.99\r\n] 2006.259.07:53:03.13#ibcon#*before write, iclass 39, count 0 2006.259.07:53:03.13#ibcon#enter sib2, iclass 39, count 0 2006.259.07:53:03.13#ibcon#flushed, iclass 39, count 0 2006.259.07:53:03.13#ibcon#about to write, iclass 39, count 0 2006.259.07:53:03.13#ibcon#wrote, iclass 39, count 0 2006.259.07:53:03.13#ibcon#about to read 3, iclass 39, count 0 2006.259.07:53:03.17#ibcon#read 3, iclass 39, count 0 2006.259.07:53:03.17#ibcon#about to read 4, iclass 39, count 0 2006.259.07:53:03.17#ibcon#read 4, iclass 39, count 0 2006.259.07:53:03.17#ibcon#about to read 5, iclass 39, count 0 2006.259.07:53:03.17#ibcon#read 5, iclass 39, count 0 2006.259.07:53:03.17#ibcon#about to read 6, iclass 39, count 0 2006.259.07:53:03.17#ibcon#read 6, iclass 39, count 0 2006.259.07:53:03.17#ibcon#end of sib2, iclass 39, count 0 2006.259.07:53:03.17#ibcon#*after write, iclass 39, count 0 2006.259.07:53:03.17#ibcon#*before return 0, iclass 39, count 0 2006.259.07:53:03.17#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.259.07:53:03.17#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.259.07:53:03.17#ibcon#about to clear, iclass 39 cls_cnt 0 2006.259.07:53:03.17#ibcon#cleared, iclass 39 cls_cnt 0 2006.259.07:53:03.18$vc4f8/vb=6,4 2006.259.07:53:03.18#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.259.07:53:03.18#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.259.07:53:03.18#ibcon#ireg 11 cls_cnt 2 2006.259.07:53:03.18#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.259.07:53:03.22#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.259.07:53:03.22#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.259.07:53:03.22#ibcon#enter wrdev, iclass 3, count 2 2006.259.07:53:03.22#ibcon#first serial, iclass 3, count 2 2006.259.07:53:03.22#ibcon#enter sib2, iclass 3, count 2 2006.259.07:53:03.22#ibcon#flushed, iclass 3, count 2 2006.259.07:53:03.22#ibcon#about to write, iclass 3, count 2 2006.259.07:53:03.22#ibcon#wrote, iclass 3, count 2 2006.259.07:53:03.22#ibcon#about to read 3, iclass 3, count 2 2006.259.07:53:03.24#ibcon#read 3, iclass 3, count 2 2006.259.07:53:03.24#ibcon#about to read 4, iclass 3, count 2 2006.259.07:53:03.24#ibcon#read 4, iclass 3, count 2 2006.259.07:53:03.24#ibcon#about to read 5, iclass 3, count 2 2006.259.07:53:03.24#ibcon#read 5, iclass 3, count 2 2006.259.07:53:03.24#ibcon#about to read 6, iclass 3, count 2 2006.259.07:53:03.24#ibcon#read 6, iclass 3, count 2 2006.259.07:53:03.24#ibcon#end of sib2, iclass 3, count 2 2006.259.07:53:03.24#ibcon#*mode == 0, iclass 3, count 2 2006.259.07:53:03.24#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.259.07:53:03.24#ibcon#[27=AT06-04\r\n] 2006.259.07:53:03.24#ibcon#*before write, iclass 3, count 2 2006.259.07:53:03.24#ibcon#enter sib2, iclass 3, count 2 2006.259.07:53:03.24#ibcon#flushed, iclass 3, count 2 2006.259.07:53:03.24#ibcon#about to write, iclass 3, count 2 2006.259.07:53:03.24#ibcon#wrote, iclass 3, count 2 2006.259.07:53:03.24#ibcon#about to read 3, iclass 3, count 2 2006.259.07:53:03.27#ibcon#read 3, iclass 3, count 2 2006.259.07:53:03.27#ibcon#about to read 4, iclass 3, count 2 2006.259.07:53:03.27#ibcon#read 4, iclass 3, count 2 2006.259.07:53:03.27#ibcon#about to read 5, iclass 3, count 2 2006.259.07:53:03.27#ibcon#read 5, iclass 3, count 2 2006.259.07:53:03.27#ibcon#about to read 6, iclass 3, count 2 2006.259.07:53:03.27#ibcon#read 6, iclass 3, count 2 2006.259.07:53:03.27#ibcon#end of sib2, iclass 3, count 2 2006.259.07:53:03.27#ibcon#*after write, iclass 3, count 2 2006.259.07:53:03.27#ibcon#*before return 0, iclass 3, count 2 2006.259.07:53:03.27#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.259.07:53:03.27#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.259.07:53:03.27#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.259.07:53:03.27#ibcon#ireg 7 cls_cnt 0 2006.259.07:53:03.27#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.259.07:53:03.39#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.259.07:53:03.39#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.259.07:53:03.39#ibcon#enter wrdev, iclass 3, count 0 2006.259.07:53:03.39#ibcon#first serial, iclass 3, count 0 2006.259.07:53:03.39#ibcon#enter sib2, iclass 3, count 0 2006.259.07:53:03.39#ibcon#flushed, iclass 3, count 0 2006.259.07:53:03.39#ibcon#about to write, iclass 3, count 0 2006.259.07:53:03.39#ibcon#wrote, iclass 3, count 0 2006.259.07:53:03.39#ibcon#about to read 3, iclass 3, count 0 2006.259.07:53:03.41#ibcon#read 3, iclass 3, count 0 2006.259.07:53:03.41#ibcon#about to read 4, iclass 3, count 0 2006.259.07:53:03.41#ibcon#read 4, iclass 3, count 0 2006.259.07:53:03.41#ibcon#about to read 5, iclass 3, count 0 2006.259.07:53:03.41#ibcon#read 5, iclass 3, count 0 2006.259.07:53:03.41#ibcon#about to read 6, iclass 3, count 0 2006.259.07:53:03.41#ibcon#read 6, iclass 3, count 0 2006.259.07:53:03.41#ibcon#end of sib2, iclass 3, count 0 2006.259.07:53:03.41#ibcon#*mode == 0, iclass 3, count 0 2006.259.07:53:03.41#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.259.07:53:03.41#ibcon#[27=USB\r\n] 2006.259.07:53:03.41#ibcon#*before write, iclass 3, count 0 2006.259.07:53:03.41#ibcon#enter sib2, iclass 3, count 0 2006.259.07:53:03.41#ibcon#flushed, iclass 3, count 0 2006.259.07:53:03.41#ibcon#about to write, iclass 3, count 0 2006.259.07:53:03.41#ibcon#wrote, iclass 3, count 0 2006.259.07:53:03.41#ibcon#about to read 3, iclass 3, count 0 2006.259.07:53:03.44#ibcon#read 3, iclass 3, count 0 2006.259.07:53:03.44#ibcon#about to read 4, iclass 3, count 0 2006.259.07:53:03.44#ibcon#read 4, iclass 3, count 0 2006.259.07:53:03.44#ibcon#about to read 5, iclass 3, count 0 2006.259.07:53:03.44#ibcon#read 5, iclass 3, count 0 2006.259.07:53:03.44#ibcon#about to read 6, iclass 3, count 0 2006.259.07:53:03.44#ibcon#read 6, iclass 3, count 0 2006.259.07:53:03.44#ibcon#end of sib2, iclass 3, count 0 2006.259.07:53:03.44#ibcon#*after write, iclass 3, count 0 2006.259.07:53:03.44#ibcon#*before return 0, iclass 3, count 0 2006.259.07:53:03.44#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.259.07:53:03.44#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.259.07:53:03.44#ibcon#about to clear, iclass 3 cls_cnt 0 2006.259.07:53:03.44#ibcon#cleared, iclass 3 cls_cnt 0 2006.259.07:53:03.45$vc4f8/vabw=wide 2006.259.07:53:03.45#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.259.07:53:03.45#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.259.07:53:03.45#ibcon#ireg 8 cls_cnt 0 2006.259.07:53:03.45#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.259.07:53:03.45#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.259.07:53:03.45#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.259.07:53:03.45#ibcon#enter wrdev, iclass 5, count 0 2006.259.07:53:03.45#ibcon#first serial, iclass 5, count 0 2006.259.07:53:03.45#ibcon#enter sib2, iclass 5, count 0 2006.259.07:53:03.45#ibcon#flushed, iclass 5, count 0 2006.259.07:53:03.45#ibcon#about to write, iclass 5, count 0 2006.259.07:53:03.45#ibcon#wrote, iclass 5, count 0 2006.259.07:53:03.45#ibcon#about to read 3, iclass 5, count 0 2006.259.07:53:03.46#ibcon#read 3, iclass 5, count 0 2006.259.07:53:03.46#ibcon#about to read 4, iclass 5, count 0 2006.259.07:53:03.46#ibcon#read 4, iclass 5, count 0 2006.259.07:53:03.46#ibcon#about to read 5, iclass 5, count 0 2006.259.07:53:03.46#ibcon#read 5, iclass 5, count 0 2006.259.07:53:03.46#ibcon#about to read 6, iclass 5, count 0 2006.259.07:53:03.46#ibcon#read 6, iclass 5, count 0 2006.259.07:53:03.46#ibcon#end of sib2, iclass 5, count 0 2006.259.07:53:03.46#ibcon#*mode == 0, iclass 5, count 0 2006.259.07:53:03.46#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.259.07:53:03.46#ibcon#[25=BW32\r\n] 2006.259.07:53:03.46#ibcon#*before write, iclass 5, count 0 2006.259.07:53:03.46#ibcon#enter sib2, iclass 5, count 0 2006.259.07:53:03.46#ibcon#flushed, iclass 5, count 0 2006.259.07:53:03.46#ibcon#about to write, iclass 5, count 0 2006.259.07:53:03.46#ibcon#wrote, iclass 5, count 0 2006.259.07:53:03.46#ibcon#about to read 3, iclass 5, count 0 2006.259.07:53:03.49#ibcon#read 3, iclass 5, count 0 2006.259.07:53:03.49#ibcon#about to read 4, iclass 5, count 0 2006.259.07:53:03.49#ibcon#read 4, iclass 5, count 0 2006.259.07:53:03.49#ibcon#about to read 5, iclass 5, count 0 2006.259.07:53:03.49#ibcon#read 5, iclass 5, count 0 2006.259.07:53:03.49#ibcon#about to read 6, iclass 5, count 0 2006.259.07:53:03.49#ibcon#read 6, iclass 5, count 0 2006.259.07:53:03.49#ibcon#end of sib2, iclass 5, count 0 2006.259.07:53:03.49#ibcon#*after write, iclass 5, count 0 2006.259.07:53:03.49#ibcon#*before return 0, iclass 5, count 0 2006.259.07:53:03.49#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.259.07:53:03.49#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.259.07:53:03.49#ibcon#about to clear, iclass 5 cls_cnt 0 2006.259.07:53:03.49#ibcon#cleared, iclass 5 cls_cnt 0 2006.259.07:53:03.50$vc4f8/vbbw=wide 2006.259.07:53:03.50#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.259.07:53:03.50#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.259.07:53:03.50#ibcon#ireg 8 cls_cnt 0 2006.259.07:53:03.50#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.259.07:53:03.55#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.259.07:53:03.55#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.259.07:53:03.55#ibcon#enter wrdev, iclass 7, count 0 2006.259.07:53:03.55#ibcon#first serial, iclass 7, count 0 2006.259.07:53:03.55#ibcon#enter sib2, iclass 7, count 0 2006.259.07:53:03.55#ibcon#flushed, iclass 7, count 0 2006.259.07:53:03.55#ibcon#about to write, iclass 7, count 0 2006.259.07:53:03.55#ibcon#wrote, iclass 7, count 0 2006.259.07:53:03.55#ibcon#about to read 3, iclass 7, count 0 2006.259.07:53:03.57#ibcon#read 3, iclass 7, count 0 2006.259.07:53:03.57#ibcon#about to read 4, iclass 7, count 0 2006.259.07:53:03.57#ibcon#read 4, iclass 7, count 0 2006.259.07:53:03.57#ibcon#about to read 5, iclass 7, count 0 2006.259.07:53:03.57#ibcon#read 5, iclass 7, count 0 2006.259.07:53:03.57#ibcon#about to read 6, iclass 7, count 0 2006.259.07:53:03.57#ibcon#read 6, iclass 7, count 0 2006.259.07:53:03.57#ibcon#end of sib2, iclass 7, count 0 2006.259.07:53:03.57#ibcon#*mode == 0, iclass 7, count 0 2006.259.07:53:03.57#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.259.07:53:03.57#ibcon#[27=BW32\r\n] 2006.259.07:53:03.57#ibcon#*before write, iclass 7, count 0 2006.259.07:53:03.57#ibcon#enter sib2, iclass 7, count 0 2006.259.07:53:03.58#ibcon#flushed, iclass 7, count 0 2006.259.07:53:03.58#ibcon#about to write, iclass 7, count 0 2006.259.07:53:03.58#ibcon#wrote, iclass 7, count 0 2006.259.07:53:03.58#ibcon#about to read 3, iclass 7, count 0 2006.259.07:53:03.60#ibcon#read 3, iclass 7, count 0 2006.259.07:53:03.60#ibcon#about to read 4, iclass 7, count 0 2006.259.07:53:03.60#ibcon#read 4, iclass 7, count 0 2006.259.07:53:03.60#ibcon#about to read 5, iclass 7, count 0 2006.259.07:53:03.60#ibcon#read 5, iclass 7, count 0 2006.259.07:53:03.60#ibcon#about to read 6, iclass 7, count 0 2006.259.07:53:03.60#ibcon#read 6, iclass 7, count 0 2006.259.07:53:03.60#ibcon#end of sib2, iclass 7, count 0 2006.259.07:53:03.60#ibcon#*after write, iclass 7, count 0 2006.259.07:53:03.60#ibcon#*before return 0, iclass 7, count 0 2006.259.07:53:03.60#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.259.07:53:03.60#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.259.07:53:03.60#ibcon#about to clear, iclass 7 cls_cnt 0 2006.259.07:53:03.60#ibcon#cleared, iclass 7 cls_cnt 0 2006.259.07:53:03.61$4f8m12a/ifd4f 2006.259.07:53:03.61$ifd4f/lo= 2006.259.07:53:03.61$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.259.07:53:03.61$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.259.07:53:03.61$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.259.07:53:03.61$ifd4f/patch= 2006.259.07:53:03.61$ifd4f/patch=lo1,a1,a2,a3,a4 2006.259.07:53:03.61$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.259.07:53:03.61$ifd4f/patch=lo3,a5,a6,a7,a8 2006.259.07:53:03.61$4f8m12a/"form=m,16.000,1:2 2006.259.07:53:03.61$4f8m12a/"tpicd 2006.259.07:53:03.61$4f8m12a/echo=off 2006.259.07:53:03.61$4f8m12a/xlog=off 2006.259.07:53:03.61:!2006.259.07:54:40 2006.259.07:53:24.14#trakl#Source acquired 2006.259.07:53:26.15#flagr#flagr/antenna,acquired 2006.259.07:54:40.01:preob 2006.259.07:54:41.14/onsource/TRACKING 2006.259.07:54:41.15:!2006.259.07:54:50 2006.259.07:54:50.01:data_valid=on 2006.259.07:54:50.02:midob 2006.259.07:54:51.14/onsource/TRACKING 2006.259.07:54:51.15/wx/22.19,1013.0,87 2006.259.07:54:51.24/cable/+6.4572E-03 2006.259.07:54:52.33/va/01,08,usb,yes,33,35 2006.259.07:54:52.33/va/02,07,usb,yes,33,35 2006.259.07:54:52.33/va/03,08,usb,yes,25,25 2006.259.07:54:52.33/va/04,07,usb,yes,34,37 2006.259.07:54:52.33/va/05,07,usb,yes,38,41 2006.259.07:54:52.33/va/06,06,usb,yes,37,37 2006.259.07:54:52.33/va/07,06,usb,yes,38,38 2006.259.07:54:52.33/va/08,06,usb,yes,41,40 2006.259.07:54:52.56/valo/01,532.99,yes,locked 2006.259.07:54:52.56/valo/02,572.99,yes,locked 2006.259.07:54:52.56/valo/03,672.99,yes,locked 2006.259.07:54:52.56/valo/04,832.99,yes,locked 2006.259.07:54:52.56/valo/05,652.99,yes,locked 2006.259.07:54:52.56/valo/06,772.99,yes,locked 2006.259.07:54:52.56/valo/07,832.99,yes,locked 2006.259.07:54:52.56/valo/08,852.99,yes,locked 2006.259.07:54:53.65/vb/01,04,usb,yes,32,31 2006.259.07:54:53.65/vb/02,05,usb,yes,30,31 2006.259.07:54:53.65/vb/03,04,usb,yes,30,34 2006.259.07:54:53.65/vb/04,05,usb,yes,28,28 2006.259.07:54:53.65/vb/05,04,usb,yes,30,34 2006.259.07:54:53.65/vb/06,04,usb,yes,31,34 2006.259.07:54:53.65/vb/07,04,usb,yes,33,33 2006.259.07:54:53.65/vb/08,04,usb,yes,30,34 2006.259.07:54:53.88/vblo/01,632.99,yes,locked 2006.259.07:54:53.88/vblo/02,640.99,yes,locked 2006.259.07:54:53.88/vblo/03,656.99,yes,locked 2006.259.07:54:53.88/vblo/04,712.99,yes,locked 2006.259.07:54:53.88/vblo/05,744.99,yes,locked 2006.259.07:54:53.88/vblo/06,752.99,yes,locked 2006.259.07:54:53.88/vblo/07,734.99,yes,locked 2006.259.07:54:53.88/vblo/08,744.99,yes,locked 2006.259.07:54:54.03/vabw/8 2006.259.07:54:54.18/vbbw/8 2006.259.07:54:54.27/xfe/off,on,15.0 2006.259.07:54:54.64/ifatt/23,28,28,28 2006.259.07:54:55.07/fmout-gps/S +4.54E-07 2006.259.07:54:55.12:!2006.259.07:55:50 2006.259.07:55:50.01:data_valid=off 2006.259.07:55:50.02:postob 2006.259.07:55:50.23/cable/+6.4584E-03 2006.259.07:55:50.24/wx/22.18,1013.0,86 2006.259.07:55:51.07/fmout-gps/S +4.54E-07 2006.259.07:55:51.08:scan_name=259-0758,k06259,60 2006.259.07:55:51.08:source=1611+343,161341.06,341247.9,2000.0,ccw 2006.259.07:55:52.14#flagr#flagr/antenna,new-source 2006.259.07:55:52.15:checkk5 2006.259.07:55:52.57/chk_autoobs//k5ts1/ autoobs is running! 2006.259.07:55:53.00/chk_autoobs//k5ts2/ autoobs is running! 2006.259.07:55:53.40/chk_autoobs//k5ts3/ autoobs is running! 2006.259.07:55:53.94/chk_autoobs//k5ts4/ autoobs is running! 2006.259.07:55:54.63/chk_obsdata//k5ts1/T2590754??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.259.07:55:55.06/chk_obsdata//k5ts2/T2590754??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.259.07:55:55.48/chk_obsdata//k5ts3/T2590754??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.259.07:55:55.87/chk_obsdata//k5ts4/T2590754??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.259.07:55:56.66/k5log//k5ts1_log_newline 2006.259.07:55:57.63/k5log//k5ts2_log_newline 2006.259.07:55:59.06/k5log//k5ts3_log_newline 2006.259.07:55:59.83/k5log//k5ts4_log_newline 2006.259.07:55:59.86/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.259.07:55:59.86:4f8m12a=2 2006.259.07:55:59.86$4f8m12a/echo=on 2006.259.07:55:59.86$4f8m12a/pcalon 2006.259.07:55:59.86$pcalon/"no phase cal control is implemented here 2006.259.07:55:59.86$4f8m12a/"tpicd=stop 2006.259.07:55:59.86$4f8m12a/vc4f8 2006.259.07:55:59.86$vc4f8/valo=1,532.99 2006.259.07:55:59.87#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.259.07:55:59.87#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.259.07:55:59.87#ibcon#ireg 17 cls_cnt 0 2006.259.07:55:59.87#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.259.07:55:59.87#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.259.07:55:59.87#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.259.07:55:59.87#ibcon#enter wrdev, iclass 6, count 0 2006.259.07:55:59.87#ibcon#first serial, iclass 6, count 0 2006.259.07:55:59.87#ibcon#enter sib2, iclass 6, count 0 2006.259.07:55:59.87#ibcon#flushed, iclass 6, count 0 2006.259.07:55:59.87#ibcon#about to write, iclass 6, count 0 2006.259.07:55:59.87#ibcon#wrote, iclass 6, count 0 2006.259.07:55:59.87#ibcon#about to read 3, iclass 6, count 0 2006.259.07:55:59.91#ibcon#read 3, iclass 6, count 0 2006.259.07:55:59.91#ibcon#about to read 4, iclass 6, count 0 2006.259.07:55:59.91#ibcon#read 4, iclass 6, count 0 2006.259.07:55:59.91#ibcon#about to read 5, iclass 6, count 0 2006.259.07:55:59.91#ibcon#read 5, iclass 6, count 0 2006.259.07:55:59.91#ibcon#about to read 6, iclass 6, count 0 2006.259.07:55:59.91#ibcon#read 6, iclass 6, count 0 2006.259.07:55:59.91#ibcon#end of sib2, iclass 6, count 0 2006.259.07:55:59.91#ibcon#*mode == 0, iclass 6, count 0 2006.259.07:55:59.91#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.259.07:55:59.91#ibcon#[26=FRQ=01,532.99\r\n] 2006.259.07:55:59.91#ibcon#*before write, iclass 6, count 0 2006.259.07:55:59.91#ibcon#enter sib2, iclass 6, count 0 2006.259.07:55:59.91#ibcon#flushed, iclass 6, count 0 2006.259.07:55:59.91#ibcon#about to write, iclass 6, count 0 2006.259.07:55:59.91#ibcon#wrote, iclass 6, count 0 2006.259.07:55:59.91#ibcon#about to read 3, iclass 6, count 0 2006.259.07:55:59.95#ibcon#read 3, iclass 6, count 0 2006.259.07:55:59.95#ibcon#about to read 4, iclass 6, count 0 2006.259.07:55:59.95#ibcon#read 4, iclass 6, count 0 2006.259.07:55:59.95#ibcon#about to read 5, iclass 6, count 0 2006.259.07:55:59.95#ibcon#read 5, iclass 6, count 0 2006.259.07:55:59.95#ibcon#about to read 6, iclass 6, count 0 2006.259.07:55:59.95#ibcon#read 6, iclass 6, count 0 2006.259.07:55:59.95#ibcon#end of sib2, iclass 6, count 0 2006.259.07:55:59.95#ibcon#*after write, iclass 6, count 0 2006.259.07:55:59.95#ibcon#*before return 0, iclass 6, count 0 2006.259.07:55:59.95#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.259.07:55:59.95#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.259.07:55:59.95#ibcon#about to clear, iclass 6 cls_cnt 0 2006.259.07:55:59.95#ibcon#cleared, iclass 6 cls_cnt 0 2006.259.07:55:59.95$vc4f8/va=1,8 2006.259.07:55:59.95#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.259.07:55:59.95#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.259.07:55:59.95#ibcon#ireg 11 cls_cnt 2 2006.259.07:55:59.95#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.259.07:55:59.95#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.259.07:55:59.95#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.259.07:55:59.95#ibcon#enter wrdev, iclass 10, count 2 2006.259.07:55:59.95#ibcon#first serial, iclass 10, count 2 2006.259.07:55:59.95#ibcon#enter sib2, iclass 10, count 2 2006.259.07:55:59.95#ibcon#flushed, iclass 10, count 2 2006.259.07:55:59.95#ibcon#about to write, iclass 10, count 2 2006.259.07:55:59.95#ibcon#wrote, iclass 10, count 2 2006.259.07:55:59.95#ibcon#about to read 3, iclass 10, count 2 2006.259.07:55:59.97#ibcon#read 3, iclass 10, count 2 2006.259.07:55:59.97#ibcon#about to read 4, iclass 10, count 2 2006.259.07:55:59.97#ibcon#read 4, iclass 10, count 2 2006.259.07:55:59.97#ibcon#about to read 5, iclass 10, count 2 2006.259.07:55:59.97#ibcon#read 5, iclass 10, count 2 2006.259.07:55:59.97#ibcon#about to read 6, iclass 10, count 2 2006.259.07:55:59.97#ibcon#read 6, iclass 10, count 2 2006.259.07:55:59.97#ibcon#end of sib2, iclass 10, count 2 2006.259.07:55:59.97#ibcon#*mode == 0, iclass 10, count 2 2006.259.07:55:59.97#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.259.07:55:59.97#ibcon#[25=AT01-08\r\n] 2006.259.07:55:59.97#ibcon#*before write, iclass 10, count 2 2006.259.07:55:59.97#ibcon#enter sib2, iclass 10, count 2 2006.259.07:55:59.97#ibcon#flushed, iclass 10, count 2 2006.259.07:55:59.97#ibcon#about to write, iclass 10, count 2 2006.259.07:55:59.97#ibcon#wrote, iclass 10, count 2 2006.259.07:55:59.97#ibcon#about to read 3, iclass 10, count 2 2006.259.07:56:00.00#ibcon#read 3, iclass 10, count 2 2006.259.07:56:00.00#ibcon#about to read 4, iclass 10, count 2 2006.259.07:56:00.00#ibcon#read 4, iclass 10, count 2 2006.259.07:56:00.00#ibcon#about to read 5, iclass 10, count 2 2006.259.07:56:00.00#ibcon#read 5, iclass 10, count 2 2006.259.07:56:00.00#ibcon#about to read 6, iclass 10, count 2 2006.259.07:56:00.00#ibcon#read 6, iclass 10, count 2 2006.259.07:56:00.00#ibcon#end of sib2, iclass 10, count 2 2006.259.07:56:00.00#ibcon#*after write, iclass 10, count 2 2006.259.07:56:00.00#ibcon#*before return 0, iclass 10, count 2 2006.259.07:56:00.00#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.259.07:56:00.00#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.259.07:56:00.00#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.259.07:56:00.00#ibcon#ireg 7 cls_cnt 0 2006.259.07:56:00.00#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.259.07:56:00.12#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.259.07:56:00.12#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.259.07:56:00.12#ibcon#enter wrdev, iclass 10, count 0 2006.259.07:56:00.12#ibcon#first serial, iclass 10, count 0 2006.259.07:56:00.12#ibcon#enter sib2, iclass 10, count 0 2006.259.07:56:00.12#ibcon#flushed, iclass 10, count 0 2006.259.07:56:00.12#ibcon#about to write, iclass 10, count 0 2006.259.07:56:00.12#ibcon#wrote, iclass 10, count 0 2006.259.07:56:00.12#ibcon#about to read 3, iclass 10, count 0 2006.259.07:56:00.14#ibcon#read 3, iclass 10, count 0 2006.259.07:56:00.14#ibcon#about to read 4, iclass 10, count 0 2006.259.07:56:00.14#ibcon#read 4, iclass 10, count 0 2006.259.07:56:00.14#ibcon#about to read 5, iclass 10, count 0 2006.259.07:56:00.14#ibcon#read 5, iclass 10, count 0 2006.259.07:56:00.14#ibcon#about to read 6, iclass 10, count 0 2006.259.07:56:00.14#ibcon#read 6, iclass 10, count 0 2006.259.07:56:00.14#ibcon#end of sib2, iclass 10, count 0 2006.259.07:56:00.14#ibcon#*mode == 0, iclass 10, count 0 2006.259.07:56:00.14#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.259.07:56:00.14#ibcon#[25=USB\r\n] 2006.259.07:56:00.14#ibcon#*before write, iclass 10, count 0 2006.259.07:56:00.14#ibcon#enter sib2, iclass 10, count 0 2006.259.07:56:00.14#ibcon#flushed, iclass 10, count 0 2006.259.07:56:00.14#ibcon#about to write, iclass 10, count 0 2006.259.07:56:00.14#ibcon#wrote, iclass 10, count 0 2006.259.07:56:00.14#ibcon#about to read 3, iclass 10, count 0 2006.259.07:56:00.17#ibcon#read 3, iclass 10, count 0 2006.259.07:56:00.17#ibcon#about to read 4, iclass 10, count 0 2006.259.07:56:00.17#ibcon#read 4, iclass 10, count 0 2006.259.07:56:00.17#ibcon#about to read 5, iclass 10, count 0 2006.259.07:56:00.17#ibcon#read 5, iclass 10, count 0 2006.259.07:56:00.17#ibcon#about to read 6, iclass 10, count 0 2006.259.07:56:00.17#ibcon#read 6, iclass 10, count 0 2006.259.07:56:00.17#ibcon#end of sib2, iclass 10, count 0 2006.259.07:56:00.17#ibcon#*after write, iclass 10, count 0 2006.259.07:56:00.17#ibcon#*before return 0, iclass 10, count 0 2006.259.07:56:00.17#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.259.07:56:00.17#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.259.07:56:00.17#ibcon#about to clear, iclass 10 cls_cnt 0 2006.259.07:56:00.17#ibcon#cleared, iclass 10 cls_cnt 0 2006.259.07:56:00.17$vc4f8/valo=2,572.99 2006.259.07:56:00.17#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.259.07:56:00.17#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.259.07:56:00.17#ibcon#ireg 17 cls_cnt 0 2006.259.07:56:00.17#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.259.07:56:00.17#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.259.07:56:00.17#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.259.07:56:00.17#ibcon#enter wrdev, iclass 12, count 0 2006.259.07:56:00.17#ibcon#first serial, iclass 12, count 0 2006.259.07:56:00.17#ibcon#enter sib2, iclass 12, count 0 2006.259.07:56:00.17#ibcon#flushed, iclass 12, count 0 2006.259.07:56:00.17#ibcon#about to write, iclass 12, count 0 2006.259.07:56:00.17#ibcon#wrote, iclass 12, count 0 2006.259.07:56:00.17#ibcon#about to read 3, iclass 12, count 0 2006.259.07:56:00.20#ibcon#read 3, iclass 12, count 0 2006.259.07:56:00.20#ibcon#about to read 4, iclass 12, count 0 2006.259.07:56:00.20#ibcon#read 4, iclass 12, count 0 2006.259.07:56:00.20#ibcon#about to read 5, iclass 12, count 0 2006.259.07:56:00.20#ibcon#read 5, iclass 12, count 0 2006.259.07:56:00.20#ibcon#about to read 6, iclass 12, count 0 2006.259.07:56:00.20#ibcon#read 6, iclass 12, count 0 2006.259.07:56:00.20#ibcon#end of sib2, iclass 12, count 0 2006.259.07:56:00.20#ibcon#*mode == 0, iclass 12, count 0 2006.259.07:56:00.20#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.259.07:56:00.20#ibcon#[26=FRQ=02,572.99\r\n] 2006.259.07:56:00.20#ibcon#*before write, iclass 12, count 0 2006.259.07:56:00.20#ibcon#enter sib2, iclass 12, count 0 2006.259.07:56:00.20#ibcon#flushed, iclass 12, count 0 2006.259.07:56:00.20#ibcon#about to write, iclass 12, count 0 2006.259.07:56:00.20#ibcon#wrote, iclass 12, count 0 2006.259.07:56:00.20#ibcon#about to read 3, iclass 12, count 0 2006.259.07:56:00.24#ibcon#read 3, iclass 12, count 0 2006.259.07:56:00.24#ibcon#about to read 4, iclass 12, count 0 2006.259.07:56:00.24#ibcon#read 4, iclass 12, count 0 2006.259.07:56:00.24#ibcon#about to read 5, iclass 12, count 0 2006.259.07:56:00.24#ibcon#read 5, iclass 12, count 0 2006.259.07:56:00.24#ibcon#about to read 6, iclass 12, count 0 2006.259.07:56:00.24#ibcon#read 6, iclass 12, count 0 2006.259.07:56:00.24#ibcon#end of sib2, iclass 12, count 0 2006.259.07:56:00.24#ibcon#*after write, iclass 12, count 0 2006.259.07:56:00.24#ibcon#*before return 0, iclass 12, count 0 2006.259.07:56:00.24#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.259.07:56:00.24#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.259.07:56:00.24#ibcon#about to clear, iclass 12 cls_cnt 0 2006.259.07:56:00.24#ibcon#cleared, iclass 12 cls_cnt 0 2006.259.07:56:00.24$vc4f8/va=2,7 2006.259.07:56:00.24#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.259.07:56:00.24#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.259.07:56:00.24#ibcon#ireg 11 cls_cnt 2 2006.259.07:56:00.24#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.259.07:56:00.29#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.259.07:56:00.29#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.259.07:56:00.29#ibcon#enter wrdev, iclass 14, count 2 2006.259.07:56:00.29#ibcon#first serial, iclass 14, count 2 2006.259.07:56:00.29#ibcon#enter sib2, iclass 14, count 2 2006.259.07:56:00.29#ibcon#flushed, iclass 14, count 2 2006.259.07:56:00.29#ibcon#about to write, iclass 14, count 2 2006.259.07:56:00.29#ibcon#wrote, iclass 14, count 2 2006.259.07:56:00.29#ibcon#about to read 3, iclass 14, count 2 2006.259.07:56:00.31#ibcon#read 3, iclass 14, count 2 2006.259.07:56:00.31#ibcon#about to read 4, iclass 14, count 2 2006.259.07:56:00.31#ibcon#read 4, iclass 14, count 2 2006.259.07:56:00.31#ibcon#about to read 5, iclass 14, count 2 2006.259.07:56:00.31#ibcon#read 5, iclass 14, count 2 2006.259.07:56:00.31#ibcon#about to read 6, iclass 14, count 2 2006.259.07:56:00.31#ibcon#read 6, iclass 14, count 2 2006.259.07:56:00.31#ibcon#end of sib2, iclass 14, count 2 2006.259.07:56:00.31#ibcon#*mode == 0, iclass 14, count 2 2006.259.07:56:00.31#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.259.07:56:00.31#ibcon#[25=AT02-07\r\n] 2006.259.07:56:00.31#ibcon#*before write, iclass 14, count 2 2006.259.07:56:00.31#ibcon#enter sib2, iclass 14, count 2 2006.259.07:56:00.31#ibcon#flushed, iclass 14, count 2 2006.259.07:56:00.31#ibcon#about to write, iclass 14, count 2 2006.259.07:56:00.31#ibcon#wrote, iclass 14, count 2 2006.259.07:56:00.31#ibcon#about to read 3, iclass 14, count 2 2006.259.07:56:00.34#ibcon#read 3, iclass 14, count 2 2006.259.07:56:00.34#ibcon#about to read 4, iclass 14, count 2 2006.259.07:56:00.34#ibcon#read 4, iclass 14, count 2 2006.259.07:56:00.34#ibcon#about to read 5, iclass 14, count 2 2006.259.07:56:00.34#ibcon#read 5, iclass 14, count 2 2006.259.07:56:00.34#ibcon#about to read 6, iclass 14, count 2 2006.259.07:56:00.34#ibcon#read 6, iclass 14, count 2 2006.259.07:56:00.34#ibcon#end of sib2, iclass 14, count 2 2006.259.07:56:00.34#ibcon#*after write, iclass 14, count 2 2006.259.07:56:00.34#ibcon#*before return 0, iclass 14, count 2 2006.259.07:56:00.34#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.259.07:56:00.34#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.259.07:56:00.34#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.259.07:56:00.34#ibcon#ireg 7 cls_cnt 0 2006.259.07:56:00.34#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.259.07:56:00.46#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.259.07:56:00.46#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.259.07:56:00.46#ibcon#enter wrdev, iclass 14, count 0 2006.259.07:56:00.46#ibcon#first serial, iclass 14, count 0 2006.259.07:56:00.46#ibcon#enter sib2, iclass 14, count 0 2006.259.07:56:00.46#ibcon#flushed, iclass 14, count 0 2006.259.07:56:00.46#ibcon#about to write, iclass 14, count 0 2006.259.07:56:00.46#ibcon#wrote, iclass 14, count 0 2006.259.07:56:00.46#ibcon#about to read 3, iclass 14, count 0 2006.259.07:56:00.48#ibcon#read 3, iclass 14, count 0 2006.259.07:56:00.48#ibcon#about to read 4, iclass 14, count 0 2006.259.07:56:00.48#ibcon#read 4, iclass 14, count 0 2006.259.07:56:00.48#ibcon#about to read 5, iclass 14, count 0 2006.259.07:56:00.48#ibcon#read 5, iclass 14, count 0 2006.259.07:56:00.48#ibcon#about to read 6, iclass 14, count 0 2006.259.07:56:00.48#ibcon#read 6, iclass 14, count 0 2006.259.07:56:00.48#ibcon#end of sib2, iclass 14, count 0 2006.259.07:56:00.48#ibcon#*mode == 0, iclass 14, count 0 2006.259.07:56:00.48#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.259.07:56:00.48#ibcon#[25=USB\r\n] 2006.259.07:56:00.48#ibcon#*before write, iclass 14, count 0 2006.259.07:56:00.48#ibcon#enter sib2, iclass 14, count 0 2006.259.07:56:00.48#ibcon#flushed, iclass 14, count 0 2006.259.07:56:00.48#ibcon#about to write, iclass 14, count 0 2006.259.07:56:00.48#ibcon#wrote, iclass 14, count 0 2006.259.07:56:00.48#ibcon#about to read 3, iclass 14, count 0 2006.259.07:56:00.51#ibcon#read 3, iclass 14, count 0 2006.259.07:56:00.51#ibcon#about to read 4, iclass 14, count 0 2006.259.07:56:00.51#ibcon#read 4, iclass 14, count 0 2006.259.07:56:00.51#ibcon#about to read 5, iclass 14, count 0 2006.259.07:56:00.51#ibcon#read 5, iclass 14, count 0 2006.259.07:56:00.51#ibcon#about to read 6, iclass 14, count 0 2006.259.07:56:00.51#ibcon#read 6, iclass 14, count 0 2006.259.07:56:00.51#ibcon#end of sib2, iclass 14, count 0 2006.259.07:56:00.51#ibcon#*after write, iclass 14, count 0 2006.259.07:56:00.51#ibcon#*before return 0, iclass 14, count 0 2006.259.07:56:00.51#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.259.07:56:00.51#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.259.07:56:00.51#ibcon#about to clear, iclass 14 cls_cnt 0 2006.259.07:56:00.51#ibcon#cleared, iclass 14 cls_cnt 0 2006.259.07:56:00.51$vc4f8/valo=3,672.99 2006.259.07:56:00.51#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.259.07:56:00.51#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.259.07:56:00.51#ibcon#ireg 17 cls_cnt 0 2006.259.07:56:00.51#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.259.07:56:00.51#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.259.07:56:00.51#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.259.07:56:00.51#ibcon#enter wrdev, iclass 16, count 0 2006.259.07:56:00.51#ibcon#first serial, iclass 16, count 0 2006.259.07:56:00.51#ibcon#enter sib2, iclass 16, count 0 2006.259.07:56:00.51#ibcon#flushed, iclass 16, count 0 2006.259.07:56:00.51#ibcon#about to write, iclass 16, count 0 2006.259.07:56:00.51#ibcon#wrote, iclass 16, count 0 2006.259.07:56:00.51#ibcon#about to read 3, iclass 16, count 0 2006.259.07:56:00.53#ibcon#read 3, iclass 16, count 0 2006.259.07:56:00.53#ibcon#about to read 4, iclass 16, count 0 2006.259.07:56:00.53#ibcon#read 4, iclass 16, count 0 2006.259.07:56:00.53#ibcon#about to read 5, iclass 16, count 0 2006.259.07:56:00.53#ibcon#read 5, iclass 16, count 0 2006.259.07:56:00.53#ibcon#about to read 6, iclass 16, count 0 2006.259.07:56:00.53#ibcon#read 6, iclass 16, count 0 2006.259.07:56:00.53#ibcon#end of sib2, iclass 16, count 0 2006.259.07:56:00.53#ibcon#*mode == 0, iclass 16, count 0 2006.259.07:56:00.53#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.259.07:56:00.53#ibcon#[26=FRQ=03,672.99\r\n] 2006.259.07:56:00.53#ibcon#*before write, iclass 16, count 0 2006.259.07:56:00.53#ibcon#enter sib2, iclass 16, count 0 2006.259.07:56:00.53#ibcon#flushed, iclass 16, count 0 2006.259.07:56:00.53#ibcon#about to write, iclass 16, count 0 2006.259.07:56:00.53#ibcon#wrote, iclass 16, count 0 2006.259.07:56:00.53#ibcon#about to read 3, iclass 16, count 0 2006.259.07:56:00.57#ibcon#read 3, iclass 16, count 0 2006.259.07:56:00.57#ibcon#about to read 4, iclass 16, count 0 2006.259.07:56:00.57#ibcon#read 4, iclass 16, count 0 2006.259.07:56:00.57#ibcon#about to read 5, iclass 16, count 0 2006.259.07:56:00.57#ibcon#read 5, iclass 16, count 0 2006.259.07:56:00.57#ibcon#about to read 6, iclass 16, count 0 2006.259.07:56:00.57#ibcon#read 6, iclass 16, count 0 2006.259.07:56:00.58#ibcon#end of sib2, iclass 16, count 0 2006.259.07:56:00.58#ibcon#*after write, iclass 16, count 0 2006.259.07:56:00.58#ibcon#*before return 0, iclass 16, count 0 2006.259.07:56:00.58#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.259.07:56:00.58#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.259.07:56:00.58#ibcon#about to clear, iclass 16 cls_cnt 0 2006.259.07:56:00.58#ibcon#cleared, iclass 16 cls_cnt 0 2006.259.07:56:00.58$vc4f8/va=3,8 2006.259.07:56:00.58#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.259.07:56:00.58#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.259.07:56:00.58#ibcon#ireg 11 cls_cnt 2 2006.259.07:56:00.58#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.259.07:56:00.62#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.259.07:56:00.62#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.259.07:56:00.62#ibcon#enter wrdev, iclass 18, count 2 2006.259.07:56:00.62#ibcon#first serial, iclass 18, count 2 2006.259.07:56:00.62#ibcon#enter sib2, iclass 18, count 2 2006.259.07:56:00.62#ibcon#flushed, iclass 18, count 2 2006.259.07:56:00.62#ibcon#about to write, iclass 18, count 2 2006.259.07:56:00.62#ibcon#wrote, iclass 18, count 2 2006.259.07:56:00.62#ibcon#about to read 3, iclass 18, count 2 2006.259.07:56:00.65#ibcon#read 3, iclass 18, count 2 2006.259.07:56:00.65#ibcon#about to read 4, iclass 18, count 2 2006.259.07:56:00.65#ibcon#read 4, iclass 18, count 2 2006.259.07:56:00.65#ibcon#about to read 5, iclass 18, count 2 2006.259.07:56:00.65#ibcon#read 5, iclass 18, count 2 2006.259.07:56:00.65#ibcon#about to read 6, iclass 18, count 2 2006.259.07:56:00.65#ibcon#read 6, iclass 18, count 2 2006.259.07:56:00.65#ibcon#end of sib2, iclass 18, count 2 2006.259.07:56:00.65#ibcon#*mode == 0, iclass 18, count 2 2006.259.07:56:00.65#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.259.07:56:00.65#ibcon#[25=AT03-08\r\n] 2006.259.07:56:00.65#ibcon#*before write, iclass 18, count 2 2006.259.07:56:00.65#ibcon#enter sib2, iclass 18, count 2 2006.259.07:56:00.65#ibcon#flushed, iclass 18, count 2 2006.259.07:56:00.65#ibcon#about to write, iclass 18, count 2 2006.259.07:56:00.65#ibcon#wrote, iclass 18, count 2 2006.259.07:56:00.65#ibcon#about to read 3, iclass 18, count 2 2006.259.07:56:00.68#ibcon#read 3, iclass 18, count 2 2006.259.07:56:00.68#ibcon#about to read 4, iclass 18, count 2 2006.259.07:56:00.68#ibcon#read 4, iclass 18, count 2 2006.259.07:56:00.68#ibcon#about to read 5, iclass 18, count 2 2006.259.07:56:00.68#ibcon#read 5, iclass 18, count 2 2006.259.07:56:00.68#ibcon#about to read 6, iclass 18, count 2 2006.259.07:56:00.68#ibcon#read 6, iclass 18, count 2 2006.259.07:56:00.68#ibcon#end of sib2, iclass 18, count 2 2006.259.07:56:00.68#ibcon#*after write, iclass 18, count 2 2006.259.07:56:00.68#ibcon#*before return 0, iclass 18, count 2 2006.259.07:56:00.68#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.259.07:56:00.68#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.259.07:56:00.68#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.259.07:56:00.68#ibcon#ireg 7 cls_cnt 0 2006.259.07:56:00.68#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.259.07:56:00.80#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.259.07:56:00.80#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.259.07:56:00.80#ibcon#enter wrdev, iclass 18, count 0 2006.259.07:56:00.80#ibcon#first serial, iclass 18, count 0 2006.259.07:56:00.80#ibcon#enter sib2, iclass 18, count 0 2006.259.07:56:00.80#ibcon#flushed, iclass 18, count 0 2006.259.07:56:00.80#ibcon#about to write, iclass 18, count 0 2006.259.07:56:00.80#ibcon#wrote, iclass 18, count 0 2006.259.07:56:00.80#ibcon#about to read 3, iclass 18, count 0 2006.259.07:56:00.82#ibcon#read 3, iclass 18, count 0 2006.259.07:56:00.82#ibcon#about to read 4, iclass 18, count 0 2006.259.07:56:00.82#ibcon#read 4, iclass 18, count 0 2006.259.07:56:00.82#ibcon#about to read 5, iclass 18, count 0 2006.259.07:56:00.82#ibcon#read 5, iclass 18, count 0 2006.259.07:56:00.82#ibcon#about to read 6, iclass 18, count 0 2006.259.07:56:00.82#ibcon#read 6, iclass 18, count 0 2006.259.07:56:00.82#ibcon#end of sib2, iclass 18, count 0 2006.259.07:56:00.82#ibcon#*mode == 0, iclass 18, count 0 2006.259.07:56:00.82#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.259.07:56:00.82#ibcon#[25=USB\r\n] 2006.259.07:56:00.82#ibcon#*before write, iclass 18, count 0 2006.259.07:56:00.82#ibcon#enter sib2, iclass 18, count 0 2006.259.07:56:00.82#ibcon#flushed, iclass 18, count 0 2006.259.07:56:00.82#ibcon#about to write, iclass 18, count 0 2006.259.07:56:00.82#ibcon#wrote, iclass 18, count 0 2006.259.07:56:00.82#ibcon#about to read 3, iclass 18, count 0 2006.259.07:56:00.85#ibcon#read 3, iclass 18, count 0 2006.259.07:56:00.85#ibcon#about to read 4, iclass 18, count 0 2006.259.07:56:00.85#ibcon#read 4, iclass 18, count 0 2006.259.07:56:00.85#ibcon#about to read 5, iclass 18, count 0 2006.259.07:56:00.85#ibcon#read 5, iclass 18, count 0 2006.259.07:56:00.85#ibcon#about to read 6, iclass 18, count 0 2006.259.07:56:00.85#ibcon#read 6, iclass 18, count 0 2006.259.07:56:00.85#ibcon#end of sib2, iclass 18, count 0 2006.259.07:56:00.85#ibcon#*after write, iclass 18, count 0 2006.259.07:56:00.85#ibcon#*before return 0, iclass 18, count 0 2006.259.07:56:00.85#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.259.07:56:00.85#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.259.07:56:00.85#ibcon#about to clear, iclass 18 cls_cnt 0 2006.259.07:56:00.85#ibcon#cleared, iclass 18 cls_cnt 0 2006.259.07:56:00.85$vc4f8/valo=4,832.99 2006.259.07:56:00.85#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.259.07:56:00.85#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.259.07:56:00.85#ibcon#ireg 17 cls_cnt 0 2006.259.07:56:00.85#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.259.07:56:00.85#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.259.07:56:00.85#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.259.07:56:00.85#ibcon#enter wrdev, iclass 20, count 0 2006.259.07:56:00.85#ibcon#first serial, iclass 20, count 0 2006.259.07:56:00.85#ibcon#enter sib2, iclass 20, count 0 2006.259.07:56:00.85#ibcon#flushed, iclass 20, count 0 2006.259.07:56:00.85#ibcon#about to write, iclass 20, count 0 2006.259.07:56:00.85#ibcon#wrote, iclass 20, count 0 2006.259.07:56:00.85#ibcon#about to read 3, iclass 20, count 0 2006.259.07:56:00.87#ibcon#read 3, iclass 20, count 0 2006.259.07:56:00.87#ibcon#about to read 4, iclass 20, count 0 2006.259.07:56:00.87#ibcon#read 4, iclass 20, count 0 2006.259.07:56:00.87#ibcon#about to read 5, iclass 20, count 0 2006.259.07:56:00.87#ibcon#read 5, iclass 20, count 0 2006.259.07:56:00.87#ibcon#about to read 6, iclass 20, count 0 2006.259.07:56:00.87#ibcon#read 6, iclass 20, count 0 2006.259.07:56:00.87#ibcon#end of sib2, iclass 20, count 0 2006.259.07:56:00.87#ibcon#*mode == 0, iclass 20, count 0 2006.259.07:56:00.87#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.259.07:56:00.87#ibcon#[26=FRQ=04,832.99\r\n] 2006.259.07:56:00.87#ibcon#*before write, iclass 20, count 0 2006.259.07:56:00.87#ibcon#enter sib2, iclass 20, count 0 2006.259.07:56:00.87#ibcon#flushed, iclass 20, count 0 2006.259.07:56:00.87#ibcon#about to write, iclass 20, count 0 2006.259.07:56:00.87#ibcon#wrote, iclass 20, count 0 2006.259.07:56:00.87#ibcon#about to read 3, iclass 20, count 0 2006.259.07:56:00.91#ibcon#read 3, iclass 20, count 0 2006.259.07:56:00.91#ibcon#about to read 4, iclass 20, count 0 2006.259.07:56:00.91#ibcon#read 4, iclass 20, count 0 2006.259.07:56:00.91#ibcon#about to read 5, iclass 20, count 0 2006.259.07:56:00.91#ibcon#read 5, iclass 20, count 0 2006.259.07:56:00.91#ibcon#about to read 6, iclass 20, count 0 2006.259.07:56:00.91#ibcon#read 6, iclass 20, count 0 2006.259.07:56:00.91#ibcon#end of sib2, iclass 20, count 0 2006.259.07:56:00.91#ibcon#*after write, iclass 20, count 0 2006.259.07:56:00.91#ibcon#*before return 0, iclass 20, count 0 2006.259.07:56:00.91#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.259.07:56:00.91#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.259.07:56:00.91#ibcon#about to clear, iclass 20 cls_cnt 0 2006.259.07:56:00.91#ibcon#cleared, iclass 20 cls_cnt 0 2006.259.07:56:00.91$vc4f8/va=4,7 2006.259.07:56:00.91#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.259.07:56:00.91#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.259.07:56:00.91#ibcon#ireg 11 cls_cnt 2 2006.259.07:56:00.91#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.259.07:56:00.97#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.259.07:56:00.97#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.259.07:56:00.97#ibcon#enter wrdev, iclass 22, count 2 2006.259.07:56:00.97#ibcon#first serial, iclass 22, count 2 2006.259.07:56:00.97#ibcon#enter sib2, iclass 22, count 2 2006.259.07:56:00.97#ibcon#flushed, iclass 22, count 2 2006.259.07:56:00.97#ibcon#about to write, iclass 22, count 2 2006.259.07:56:00.97#ibcon#wrote, iclass 22, count 2 2006.259.07:56:00.97#ibcon#about to read 3, iclass 22, count 2 2006.259.07:56:00.99#ibcon#read 3, iclass 22, count 2 2006.259.07:56:00.99#ibcon#about to read 4, iclass 22, count 2 2006.259.07:56:00.99#ibcon#read 4, iclass 22, count 2 2006.259.07:56:00.99#ibcon#about to read 5, iclass 22, count 2 2006.259.07:56:00.99#ibcon#read 5, iclass 22, count 2 2006.259.07:56:00.99#ibcon#about to read 6, iclass 22, count 2 2006.259.07:56:00.99#ibcon#read 6, iclass 22, count 2 2006.259.07:56:00.99#ibcon#end of sib2, iclass 22, count 2 2006.259.07:56:00.99#ibcon#*mode == 0, iclass 22, count 2 2006.259.07:56:00.99#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.259.07:56:00.99#ibcon#[25=AT04-07\r\n] 2006.259.07:56:00.99#ibcon#*before write, iclass 22, count 2 2006.259.07:56:00.99#ibcon#enter sib2, iclass 22, count 2 2006.259.07:56:00.99#ibcon#flushed, iclass 22, count 2 2006.259.07:56:00.99#ibcon#about to write, iclass 22, count 2 2006.259.07:56:00.99#ibcon#wrote, iclass 22, count 2 2006.259.07:56:00.99#ibcon#about to read 3, iclass 22, count 2 2006.259.07:56:01.02#ibcon#read 3, iclass 22, count 2 2006.259.07:56:01.02#ibcon#about to read 4, iclass 22, count 2 2006.259.07:56:01.02#ibcon#read 4, iclass 22, count 2 2006.259.07:56:01.02#ibcon#about to read 5, iclass 22, count 2 2006.259.07:56:01.02#ibcon#read 5, iclass 22, count 2 2006.259.07:56:01.02#ibcon#about to read 6, iclass 22, count 2 2006.259.07:56:01.02#ibcon#read 6, iclass 22, count 2 2006.259.07:56:01.02#ibcon#end of sib2, iclass 22, count 2 2006.259.07:56:01.02#ibcon#*after write, iclass 22, count 2 2006.259.07:56:01.02#ibcon#*before return 0, iclass 22, count 2 2006.259.07:56:01.02#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.259.07:56:01.02#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.259.07:56:01.02#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.259.07:56:01.02#ibcon#ireg 7 cls_cnt 0 2006.259.07:56:01.02#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.259.07:56:01.14#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.259.07:56:01.14#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.259.07:56:01.14#ibcon#enter wrdev, iclass 22, count 0 2006.259.07:56:01.14#ibcon#first serial, iclass 22, count 0 2006.259.07:56:01.14#ibcon#enter sib2, iclass 22, count 0 2006.259.07:56:01.14#ibcon#flushed, iclass 22, count 0 2006.259.07:56:01.14#ibcon#about to write, iclass 22, count 0 2006.259.07:56:01.14#ibcon#wrote, iclass 22, count 0 2006.259.07:56:01.14#ibcon#about to read 3, iclass 22, count 0 2006.259.07:56:01.16#ibcon#read 3, iclass 22, count 0 2006.259.07:56:01.16#ibcon#about to read 4, iclass 22, count 0 2006.259.07:56:01.16#ibcon#read 4, iclass 22, count 0 2006.259.07:56:01.16#ibcon#about to read 5, iclass 22, count 0 2006.259.07:56:01.16#ibcon#read 5, iclass 22, count 0 2006.259.07:56:01.16#ibcon#about to read 6, iclass 22, count 0 2006.259.07:56:01.16#ibcon#read 6, iclass 22, count 0 2006.259.07:56:01.16#ibcon#end of sib2, iclass 22, count 0 2006.259.07:56:01.16#ibcon#*mode == 0, iclass 22, count 0 2006.259.07:56:01.16#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.259.07:56:01.16#ibcon#[25=USB\r\n] 2006.259.07:56:01.16#ibcon#*before write, iclass 22, count 0 2006.259.07:56:01.16#ibcon#enter sib2, iclass 22, count 0 2006.259.07:56:01.16#ibcon#flushed, iclass 22, count 0 2006.259.07:56:01.16#ibcon#about to write, iclass 22, count 0 2006.259.07:56:01.16#ibcon#wrote, iclass 22, count 0 2006.259.07:56:01.16#ibcon#about to read 3, iclass 22, count 0 2006.259.07:56:01.19#ibcon#read 3, iclass 22, count 0 2006.259.07:56:01.19#ibcon#about to read 4, iclass 22, count 0 2006.259.07:56:01.19#ibcon#read 4, iclass 22, count 0 2006.259.07:56:01.19#ibcon#about to read 5, iclass 22, count 0 2006.259.07:56:01.19#ibcon#read 5, iclass 22, count 0 2006.259.07:56:01.19#ibcon#about to read 6, iclass 22, count 0 2006.259.07:56:01.19#ibcon#read 6, iclass 22, count 0 2006.259.07:56:01.19#ibcon#end of sib2, iclass 22, count 0 2006.259.07:56:01.19#ibcon#*after write, iclass 22, count 0 2006.259.07:56:01.19#ibcon#*before return 0, iclass 22, count 0 2006.259.07:56:01.19#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.259.07:56:01.19#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.259.07:56:01.19#ibcon#about to clear, iclass 22 cls_cnt 0 2006.259.07:56:01.19#ibcon#cleared, iclass 22 cls_cnt 0 2006.259.07:56:01.19$vc4f8/valo=5,652.99 2006.259.07:56:01.19#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.259.07:56:01.19#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.259.07:56:01.19#ibcon#ireg 17 cls_cnt 0 2006.259.07:56:01.19#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.259.07:56:01.19#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.259.07:56:01.19#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.259.07:56:01.19#ibcon#enter wrdev, iclass 24, count 0 2006.259.07:56:01.19#ibcon#first serial, iclass 24, count 0 2006.259.07:56:01.19#ibcon#enter sib2, iclass 24, count 0 2006.259.07:56:01.19#ibcon#flushed, iclass 24, count 0 2006.259.07:56:01.19#ibcon#about to write, iclass 24, count 0 2006.259.07:56:01.19#ibcon#wrote, iclass 24, count 0 2006.259.07:56:01.19#ibcon#about to read 3, iclass 24, count 0 2006.259.07:56:01.21#ibcon#read 3, iclass 24, count 0 2006.259.07:56:01.21#ibcon#about to read 4, iclass 24, count 0 2006.259.07:56:01.21#ibcon#read 4, iclass 24, count 0 2006.259.07:56:01.21#ibcon#about to read 5, iclass 24, count 0 2006.259.07:56:01.21#ibcon#read 5, iclass 24, count 0 2006.259.07:56:01.21#ibcon#about to read 6, iclass 24, count 0 2006.259.07:56:01.21#ibcon#read 6, iclass 24, count 0 2006.259.07:56:01.21#ibcon#end of sib2, iclass 24, count 0 2006.259.07:56:01.21#ibcon#*mode == 0, iclass 24, count 0 2006.259.07:56:01.21#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.259.07:56:01.21#ibcon#[26=FRQ=05,652.99\r\n] 2006.259.07:56:01.21#ibcon#*before write, iclass 24, count 0 2006.259.07:56:01.21#ibcon#enter sib2, iclass 24, count 0 2006.259.07:56:01.21#ibcon#flushed, iclass 24, count 0 2006.259.07:56:01.21#ibcon#about to write, iclass 24, count 0 2006.259.07:56:01.21#ibcon#wrote, iclass 24, count 0 2006.259.07:56:01.21#ibcon#about to read 3, iclass 24, count 0 2006.259.07:56:01.25#ibcon#read 3, iclass 24, count 0 2006.259.07:56:01.25#ibcon#about to read 4, iclass 24, count 0 2006.259.07:56:01.25#ibcon#read 4, iclass 24, count 0 2006.259.07:56:01.25#ibcon#about to read 5, iclass 24, count 0 2006.259.07:56:01.25#ibcon#read 5, iclass 24, count 0 2006.259.07:56:01.25#ibcon#about to read 6, iclass 24, count 0 2006.259.07:56:01.25#ibcon#read 6, iclass 24, count 0 2006.259.07:56:01.25#ibcon#end of sib2, iclass 24, count 0 2006.259.07:56:01.25#ibcon#*after write, iclass 24, count 0 2006.259.07:56:01.25#ibcon#*before return 0, iclass 24, count 0 2006.259.07:56:01.25#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.259.07:56:01.25#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.259.07:56:01.25#ibcon#about to clear, iclass 24 cls_cnt 0 2006.259.07:56:01.25#ibcon#cleared, iclass 24 cls_cnt 0 2006.259.07:56:01.25$vc4f8/va=5,7 2006.259.07:56:01.25#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.259.07:56:01.25#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.259.07:56:01.25#ibcon#ireg 11 cls_cnt 2 2006.259.07:56:01.25#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.259.07:56:01.31#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.259.07:56:01.31#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.259.07:56:01.31#ibcon#enter wrdev, iclass 26, count 2 2006.259.07:56:01.31#ibcon#first serial, iclass 26, count 2 2006.259.07:56:01.31#ibcon#enter sib2, iclass 26, count 2 2006.259.07:56:01.31#ibcon#flushed, iclass 26, count 2 2006.259.07:56:01.31#ibcon#about to write, iclass 26, count 2 2006.259.07:56:01.31#ibcon#wrote, iclass 26, count 2 2006.259.07:56:01.31#ibcon#about to read 3, iclass 26, count 2 2006.259.07:56:01.33#ibcon#read 3, iclass 26, count 2 2006.259.07:56:01.33#ibcon#about to read 4, iclass 26, count 2 2006.259.07:56:01.33#ibcon#read 4, iclass 26, count 2 2006.259.07:56:01.33#ibcon#about to read 5, iclass 26, count 2 2006.259.07:56:01.33#ibcon#read 5, iclass 26, count 2 2006.259.07:56:01.33#ibcon#about to read 6, iclass 26, count 2 2006.259.07:56:01.33#ibcon#read 6, iclass 26, count 2 2006.259.07:56:01.33#ibcon#end of sib2, iclass 26, count 2 2006.259.07:56:01.33#ibcon#*mode == 0, iclass 26, count 2 2006.259.07:56:01.33#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.259.07:56:01.33#ibcon#[25=AT05-07\r\n] 2006.259.07:56:01.33#ibcon#*before write, iclass 26, count 2 2006.259.07:56:01.33#ibcon#enter sib2, iclass 26, count 2 2006.259.07:56:01.33#ibcon#flushed, iclass 26, count 2 2006.259.07:56:01.33#ibcon#about to write, iclass 26, count 2 2006.259.07:56:01.33#ibcon#wrote, iclass 26, count 2 2006.259.07:56:01.33#ibcon#about to read 3, iclass 26, count 2 2006.259.07:56:01.36#ibcon#read 3, iclass 26, count 2 2006.259.07:56:01.36#ibcon#about to read 4, iclass 26, count 2 2006.259.07:56:01.36#ibcon#read 4, iclass 26, count 2 2006.259.07:56:01.36#ibcon#about to read 5, iclass 26, count 2 2006.259.07:56:01.36#ibcon#read 5, iclass 26, count 2 2006.259.07:56:01.36#ibcon#about to read 6, iclass 26, count 2 2006.259.07:56:01.36#ibcon#read 6, iclass 26, count 2 2006.259.07:56:01.36#ibcon#end of sib2, iclass 26, count 2 2006.259.07:56:01.36#ibcon#*after write, iclass 26, count 2 2006.259.07:56:01.36#ibcon#*before return 0, iclass 26, count 2 2006.259.07:56:01.36#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.259.07:56:01.36#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.259.07:56:01.36#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.259.07:56:01.36#ibcon#ireg 7 cls_cnt 0 2006.259.07:56:01.36#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.259.07:56:01.48#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.259.07:56:01.48#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.259.07:56:01.48#ibcon#enter wrdev, iclass 26, count 0 2006.259.07:56:01.48#ibcon#first serial, iclass 26, count 0 2006.259.07:56:01.48#ibcon#enter sib2, iclass 26, count 0 2006.259.07:56:01.48#ibcon#flushed, iclass 26, count 0 2006.259.07:56:01.48#ibcon#about to write, iclass 26, count 0 2006.259.07:56:01.48#ibcon#wrote, iclass 26, count 0 2006.259.07:56:01.48#ibcon#about to read 3, iclass 26, count 0 2006.259.07:56:01.50#ibcon#read 3, iclass 26, count 0 2006.259.07:56:01.50#ibcon#about to read 4, iclass 26, count 0 2006.259.07:56:01.50#ibcon#read 4, iclass 26, count 0 2006.259.07:56:01.50#ibcon#about to read 5, iclass 26, count 0 2006.259.07:56:01.50#ibcon#read 5, iclass 26, count 0 2006.259.07:56:01.50#ibcon#about to read 6, iclass 26, count 0 2006.259.07:56:01.50#ibcon#read 6, iclass 26, count 0 2006.259.07:56:01.50#ibcon#end of sib2, iclass 26, count 0 2006.259.07:56:01.50#ibcon#*mode == 0, iclass 26, count 0 2006.259.07:56:01.50#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.259.07:56:01.50#ibcon#[25=USB\r\n] 2006.259.07:56:01.50#ibcon#*before write, iclass 26, count 0 2006.259.07:56:01.50#ibcon#enter sib2, iclass 26, count 0 2006.259.07:56:01.50#ibcon#flushed, iclass 26, count 0 2006.259.07:56:01.50#ibcon#about to write, iclass 26, count 0 2006.259.07:56:01.50#ibcon#wrote, iclass 26, count 0 2006.259.07:56:01.50#ibcon#about to read 3, iclass 26, count 0 2006.259.07:56:01.53#ibcon#read 3, iclass 26, count 0 2006.259.07:56:01.53#ibcon#about to read 4, iclass 26, count 0 2006.259.07:56:01.53#ibcon#read 4, iclass 26, count 0 2006.259.07:56:01.53#ibcon#about to read 5, iclass 26, count 0 2006.259.07:56:01.53#ibcon#read 5, iclass 26, count 0 2006.259.07:56:01.53#ibcon#about to read 6, iclass 26, count 0 2006.259.07:56:01.53#ibcon#read 6, iclass 26, count 0 2006.259.07:56:01.53#ibcon#end of sib2, iclass 26, count 0 2006.259.07:56:01.53#ibcon#*after write, iclass 26, count 0 2006.259.07:56:01.53#ibcon#*before return 0, iclass 26, count 0 2006.259.07:56:01.53#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.259.07:56:01.53#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.259.07:56:01.53#ibcon#about to clear, iclass 26 cls_cnt 0 2006.259.07:56:01.53#ibcon#cleared, iclass 26 cls_cnt 0 2006.259.07:56:01.53$vc4f8/valo=6,772.99 2006.259.07:56:01.53#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.259.07:56:01.53#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.259.07:56:01.53#ibcon#ireg 17 cls_cnt 0 2006.259.07:56:01.53#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.259.07:56:01.53#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.259.07:56:01.53#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.259.07:56:01.53#ibcon#enter wrdev, iclass 28, count 0 2006.259.07:56:01.53#ibcon#first serial, iclass 28, count 0 2006.259.07:56:01.53#ibcon#enter sib2, iclass 28, count 0 2006.259.07:56:01.53#ibcon#flushed, iclass 28, count 0 2006.259.07:56:01.53#ibcon#about to write, iclass 28, count 0 2006.259.07:56:01.53#ibcon#wrote, iclass 28, count 0 2006.259.07:56:01.53#ibcon#about to read 3, iclass 28, count 0 2006.259.07:56:01.55#ibcon#read 3, iclass 28, count 0 2006.259.07:56:01.55#ibcon#about to read 4, iclass 28, count 0 2006.259.07:56:01.55#ibcon#read 4, iclass 28, count 0 2006.259.07:56:01.55#ibcon#about to read 5, iclass 28, count 0 2006.259.07:56:01.55#ibcon#read 5, iclass 28, count 0 2006.259.07:56:01.55#ibcon#about to read 6, iclass 28, count 0 2006.259.07:56:01.55#ibcon#read 6, iclass 28, count 0 2006.259.07:56:01.55#ibcon#end of sib2, iclass 28, count 0 2006.259.07:56:01.55#ibcon#*mode == 0, iclass 28, count 0 2006.259.07:56:01.55#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.259.07:56:01.55#ibcon#[26=FRQ=06,772.99\r\n] 2006.259.07:56:01.55#ibcon#*before write, iclass 28, count 0 2006.259.07:56:01.55#ibcon#enter sib2, iclass 28, count 0 2006.259.07:56:01.55#ibcon#flushed, iclass 28, count 0 2006.259.07:56:01.55#ibcon#about to write, iclass 28, count 0 2006.259.07:56:01.55#ibcon#wrote, iclass 28, count 0 2006.259.07:56:01.55#ibcon#about to read 3, iclass 28, count 0 2006.259.07:56:01.59#ibcon#read 3, iclass 28, count 0 2006.259.07:56:01.59#ibcon#about to read 4, iclass 28, count 0 2006.259.07:56:01.59#ibcon#read 4, iclass 28, count 0 2006.259.07:56:01.59#ibcon#about to read 5, iclass 28, count 0 2006.259.07:56:01.59#ibcon#read 5, iclass 28, count 0 2006.259.07:56:01.59#ibcon#about to read 6, iclass 28, count 0 2006.259.07:56:01.59#ibcon#read 6, iclass 28, count 0 2006.259.07:56:01.59#ibcon#end of sib2, iclass 28, count 0 2006.259.07:56:01.59#ibcon#*after write, iclass 28, count 0 2006.259.07:56:01.59#ibcon#*before return 0, iclass 28, count 0 2006.259.07:56:01.59#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.259.07:56:01.59#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.259.07:56:01.59#ibcon#about to clear, iclass 28 cls_cnt 0 2006.259.07:56:01.59#ibcon#cleared, iclass 28 cls_cnt 0 2006.259.07:56:01.59$vc4f8/va=6,6 2006.259.07:56:01.59#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.259.07:56:01.59#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.259.07:56:01.59#ibcon#ireg 11 cls_cnt 2 2006.259.07:56:01.59#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.259.07:56:01.65#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.259.07:56:01.65#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.259.07:56:01.65#ibcon#enter wrdev, iclass 30, count 2 2006.259.07:56:01.65#ibcon#first serial, iclass 30, count 2 2006.259.07:56:01.65#ibcon#enter sib2, iclass 30, count 2 2006.259.07:56:01.65#ibcon#flushed, iclass 30, count 2 2006.259.07:56:01.65#ibcon#about to write, iclass 30, count 2 2006.259.07:56:01.65#ibcon#wrote, iclass 30, count 2 2006.259.07:56:01.65#ibcon#about to read 3, iclass 30, count 2 2006.259.07:56:01.67#ibcon#read 3, iclass 30, count 2 2006.259.07:56:01.67#ibcon#about to read 4, iclass 30, count 2 2006.259.07:56:01.67#ibcon#read 4, iclass 30, count 2 2006.259.07:56:01.67#ibcon#about to read 5, iclass 30, count 2 2006.259.07:56:01.67#ibcon#read 5, iclass 30, count 2 2006.259.07:56:01.67#ibcon#about to read 6, iclass 30, count 2 2006.259.07:56:01.67#ibcon#read 6, iclass 30, count 2 2006.259.07:56:01.67#ibcon#end of sib2, iclass 30, count 2 2006.259.07:56:01.67#ibcon#*mode == 0, iclass 30, count 2 2006.259.07:56:01.67#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.259.07:56:01.67#ibcon#[25=AT06-06\r\n] 2006.259.07:56:01.67#ibcon#*before write, iclass 30, count 2 2006.259.07:56:01.67#ibcon#enter sib2, iclass 30, count 2 2006.259.07:56:01.67#ibcon#flushed, iclass 30, count 2 2006.259.07:56:01.67#ibcon#about to write, iclass 30, count 2 2006.259.07:56:01.67#ibcon#wrote, iclass 30, count 2 2006.259.07:56:01.67#ibcon#about to read 3, iclass 30, count 2 2006.259.07:56:01.70#ibcon#read 3, iclass 30, count 2 2006.259.07:56:01.70#ibcon#about to read 4, iclass 30, count 2 2006.259.07:56:01.70#ibcon#read 4, iclass 30, count 2 2006.259.07:56:01.70#ibcon#about to read 5, iclass 30, count 2 2006.259.07:56:01.70#ibcon#read 5, iclass 30, count 2 2006.259.07:56:01.70#ibcon#about to read 6, iclass 30, count 2 2006.259.07:56:01.70#ibcon#read 6, iclass 30, count 2 2006.259.07:56:01.70#ibcon#end of sib2, iclass 30, count 2 2006.259.07:56:01.70#ibcon#*after write, iclass 30, count 2 2006.259.07:56:01.70#ibcon#*before return 0, iclass 30, count 2 2006.259.07:56:01.70#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.259.07:56:01.70#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.259.07:56:01.70#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.259.07:56:01.70#ibcon#ireg 7 cls_cnt 0 2006.259.07:56:01.70#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.259.07:56:01.82#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.259.07:56:01.82#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.259.07:56:01.82#ibcon#enter wrdev, iclass 30, count 0 2006.259.07:56:01.82#ibcon#first serial, iclass 30, count 0 2006.259.07:56:01.82#ibcon#enter sib2, iclass 30, count 0 2006.259.07:56:01.82#ibcon#flushed, iclass 30, count 0 2006.259.07:56:01.82#ibcon#about to write, iclass 30, count 0 2006.259.07:56:01.82#ibcon#wrote, iclass 30, count 0 2006.259.07:56:01.82#ibcon#about to read 3, iclass 30, count 0 2006.259.07:56:01.84#ibcon#read 3, iclass 30, count 0 2006.259.07:56:01.84#ibcon#about to read 4, iclass 30, count 0 2006.259.07:56:01.84#ibcon#read 4, iclass 30, count 0 2006.259.07:56:01.84#ibcon#about to read 5, iclass 30, count 0 2006.259.07:56:01.84#ibcon#read 5, iclass 30, count 0 2006.259.07:56:01.84#ibcon#about to read 6, iclass 30, count 0 2006.259.07:56:01.84#ibcon#read 6, iclass 30, count 0 2006.259.07:56:01.84#ibcon#end of sib2, iclass 30, count 0 2006.259.07:56:01.84#ibcon#*mode == 0, iclass 30, count 0 2006.259.07:56:01.84#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.259.07:56:01.84#ibcon#[25=USB\r\n] 2006.259.07:56:01.84#ibcon#*before write, iclass 30, count 0 2006.259.07:56:01.84#ibcon#enter sib2, iclass 30, count 0 2006.259.07:56:01.84#ibcon#flushed, iclass 30, count 0 2006.259.07:56:01.84#ibcon#about to write, iclass 30, count 0 2006.259.07:56:01.84#ibcon#wrote, iclass 30, count 0 2006.259.07:56:01.84#ibcon#about to read 3, iclass 30, count 0 2006.259.07:56:01.87#ibcon#read 3, iclass 30, count 0 2006.259.07:56:01.87#ibcon#about to read 4, iclass 30, count 0 2006.259.07:56:01.87#ibcon#read 4, iclass 30, count 0 2006.259.07:56:01.87#ibcon#about to read 5, iclass 30, count 0 2006.259.07:56:01.87#ibcon#read 5, iclass 30, count 0 2006.259.07:56:01.87#ibcon#about to read 6, iclass 30, count 0 2006.259.07:56:01.87#ibcon#read 6, iclass 30, count 0 2006.259.07:56:01.87#ibcon#end of sib2, iclass 30, count 0 2006.259.07:56:01.87#ibcon#*after write, iclass 30, count 0 2006.259.07:56:01.87#ibcon#*before return 0, iclass 30, count 0 2006.259.07:56:01.87#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.259.07:56:01.87#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.259.07:56:01.87#ibcon#about to clear, iclass 30 cls_cnt 0 2006.259.07:56:01.87#ibcon#cleared, iclass 30 cls_cnt 0 2006.259.07:56:01.87$vc4f8/valo=7,832.99 2006.259.07:56:01.87#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.259.07:56:01.87#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.259.07:56:01.87#ibcon#ireg 17 cls_cnt 0 2006.259.07:56:01.87#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.259.07:56:01.87#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.259.07:56:01.87#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.259.07:56:01.87#ibcon#enter wrdev, iclass 32, count 0 2006.259.07:56:01.87#ibcon#first serial, iclass 32, count 0 2006.259.07:56:01.87#ibcon#enter sib2, iclass 32, count 0 2006.259.07:56:01.87#ibcon#flushed, iclass 32, count 0 2006.259.07:56:01.87#ibcon#about to write, iclass 32, count 0 2006.259.07:56:01.87#ibcon#wrote, iclass 32, count 0 2006.259.07:56:01.87#ibcon#about to read 3, iclass 32, count 0 2006.259.07:56:01.89#ibcon#read 3, iclass 32, count 0 2006.259.07:56:01.89#ibcon#about to read 4, iclass 32, count 0 2006.259.07:56:01.89#ibcon#read 4, iclass 32, count 0 2006.259.07:56:01.89#ibcon#about to read 5, iclass 32, count 0 2006.259.07:56:01.89#ibcon#read 5, iclass 32, count 0 2006.259.07:56:01.89#ibcon#about to read 6, iclass 32, count 0 2006.259.07:56:01.89#ibcon#read 6, iclass 32, count 0 2006.259.07:56:01.89#ibcon#end of sib2, iclass 32, count 0 2006.259.07:56:01.89#ibcon#*mode == 0, iclass 32, count 0 2006.259.07:56:01.89#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.259.07:56:01.89#ibcon#[26=FRQ=07,832.99\r\n] 2006.259.07:56:01.89#ibcon#*before write, iclass 32, count 0 2006.259.07:56:01.89#ibcon#enter sib2, iclass 32, count 0 2006.259.07:56:01.89#ibcon#flushed, iclass 32, count 0 2006.259.07:56:01.89#ibcon#about to write, iclass 32, count 0 2006.259.07:56:01.89#ibcon#wrote, iclass 32, count 0 2006.259.07:56:01.89#ibcon#about to read 3, iclass 32, count 0 2006.259.07:56:01.93#ibcon#read 3, iclass 32, count 0 2006.259.07:56:01.93#ibcon#about to read 4, iclass 32, count 0 2006.259.07:56:01.93#ibcon#read 4, iclass 32, count 0 2006.259.07:56:01.93#ibcon#about to read 5, iclass 32, count 0 2006.259.07:56:01.93#ibcon#read 5, iclass 32, count 0 2006.259.07:56:01.93#ibcon#about to read 6, iclass 32, count 0 2006.259.07:56:01.93#ibcon#read 6, iclass 32, count 0 2006.259.07:56:01.93#ibcon#end of sib2, iclass 32, count 0 2006.259.07:56:01.93#ibcon#*after write, iclass 32, count 0 2006.259.07:56:01.93#ibcon#*before return 0, iclass 32, count 0 2006.259.07:56:01.93#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.259.07:56:01.93#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.259.07:56:01.93#ibcon#about to clear, iclass 32 cls_cnt 0 2006.259.07:56:01.93#ibcon#cleared, iclass 32 cls_cnt 0 2006.259.07:56:01.93$vc4f8/va=7,6 2006.259.07:56:01.93#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.259.07:56:01.93#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.259.07:56:01.93#ibcon#ireg 11 cls_cnt 2 2006.259.07:56:01.93#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.259.07:56:01.99#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.259.07:56:01.99#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.259.07:56:01.99#ibcon#enter wrdev, iclass 34, count 2 2006.259.07:56:01.99#ibcon#first serial, iclass 34, count 2 2006.259.07:56:01.99#ibcon#enter sib2, iclass 34, count 2 2006.259.07:56:01.99#ibcon#flushed, iclass 34, count 2 2006.259.07:56:01.99#ibcon#about to write, iclass 34, count 2 2006.259.07:56:01.99#ibcon#wrote, iclass 34, count 2 2006.259.07:56:01.99#ibcon#about to read 3, iclass 34, count 2 2006.259.07:56:02.01#ibcon#read 3, iclass 34, count 2 2006.259.07:56:02.01#ibcon#about to read 4, iclass 34, count 2 2006.259.07:56:02.01#ibcon#read 4, iclass 34, count 2 2006.259.07:56:02.01#ibcon#about to read 5, iclass 34, count 2 2006.259.07:56:02.01#ibcon#read 5, iclass 34, count 2 2006.259.07:56:02.01#ibcon#about to read 6, iclass 34, count 2 2006.259.07:56:02.01#ibcon#read 6, iclass 34, count 2 2006.259.07:56:02.01#ibcon#end of sib2, iclass 34, count 2 2006.259.07:56:02.01#ibcon#*mode == 0, iclass 34, count 2 2006.259.07:56:02.01#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.259.07:56:02.01#ibcon#[25=AT07-06\r\n] 2006.259.07:56:02.01#ibcon#*before write, iclass 34, count 2 2006.259.07:56:02.01#ibcon#enter sib2, iclass 34, count 2 2006.259.07:56:02.01#ibcon#flushed, iclass 34, count 2 2006.259.07:56:02.01#ibcon#about to write, iclass 34, count 2 2006.259.07:56:02.01#ibcon#wrote, iclass 34, count 2 2006.259.07:56:02.01#ibcon#about to read 3, iclass 34, count 2 2006.259.07:56:02.04#ibcon#read 3, iclass 34, count 2 2006.259.07:56:02.04#ibcon#about to read 4, iclass 34, count 2 2006.259.07:56:02.04#ibcon#read 4, iclass 34, count 2 2006.259.07:56:02.04#ibcon#about to read 5, iclass 34, count 2 2006.259.07:56:02.04#ibcon#read 5, iclass 34, count 2 2006.259.07:56:02.04#ibcon#about to read 6, iclass 34, count 2 2006.259.07:56:02.04#ibcon#read 6, iclass 34, count 2 2006.259.07:56:02.04#ibcon#end of sib2, iclass 34, count 2 2006.259.07:56:02.04#ibcon#*after write, iclass 34, count 2 2006.259.07:56:02.04#ibcon#*before return 0, iclass 34, count 2 2006.259.07:56:02.04#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.259.07:56:02.04#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.259.07:56:02.04#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.259.07:56:02.04#ibcon#ireg 7 cls_cnt 0 2006.259.07:56:02.04#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.259.07:56:02.16#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.259.07:56:02.16#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.259.07:56:02.16#ibcon#enter wrdev, iclass 34, count 0 2006.259.07:56:02.16#ibcon#first serial, iclass 34, count 0 2006.259.07:56:02.16#ibcon#enter sib2, iclass 34, count 0 2006.259.07:56:02.16#ibcon#flushed, iclass 34, count 0 2006.259.07:56:02.16#ibcon#about to write, iclass 34, count 0 2006.259.07:56:02.16#ibcon#wrote, iclass 34, count 0 2006.259.07:56:02.16#ibcon#about to read 3, iclass 34, count 0 2006.259.07:56:02.18#ibcon#read 3, iclass 34, count 0 2006.259.07:56:02.18#ibcon#about to read 4, iclass 34, count 0 2006.259.07:56:02.18#ibcon#read 4, iclass 34, count 0 2006.259.07:56:02.18#ibcon#about to read 5, iclass 34, count 0 2006.259.07:56:02.18#ibcon#read 5, iclass 34, count 0 2006.259.07:56:02.18#ibcon#about to read 6, iclass 34, count 0 2006.259.07:56:02.18#ibcon#read 6, iclass 34, count 0 2006.259.07:56:02.18#ibcon#end of sib2, iclass 34, count 0 2006.259.07:56:02.18#ibcon#*mode == 0, iclass 34, count 0 2006.259.07:56:02.18#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.259.07:56:02.18#ibcon#[25=USB\r\n] 2006.259.07:56:02.18#ibcon#*before write, iclass 34, count 0 2006.259.07:56:02.18#ibcon#enter sib2, iclass 34, count 0 2006.259.07:56:02.18#ibcon#flushed, iclass 34, count 0 2006.259.07:56:02.18#ibcon#about to write, iclass 34, count 0 2006.259.07:56:02.18#ibcon#wrote, iclass 34, count 0 2006.259.07:56:02.18#ibcon#about to read 3, iclass 34, count 0 2006.259.07:56:02.21#ibcon#read 3, iclass 34, count 0 2006.259.07:56:02.21#ibcon#about to read 4, iclass 34, count 0 2006.259.07:56:02.21#ibcon#read 4, iclass 34, count 0 2006.259.07:56:02.21#ibcon#about to read 5, iclass 34, count 0 2006.259.07:56:02.21#ibcon#read 5, iclass 34, count 0 2006.259.07:56:02.21#ibcon#about to read 6, iclass 34, count 0 2006.259.07:56:02.21#ibcon#read 6, iclass 34, count 0 2006.259.07:56:02.21#ibcon#end of sib2, iclass 34, count 0 2006.259.07:56:02.21#ibcon#*after write, iclass 34, count 0 2006.259.07:56:02.21#ibcon#*before return 0, iclass 34, count 0 2006.259.07:56:02.21#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.259.07:56:02.21#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.259.07:56:02.21#ibcon#about to clear, iclass 34 cls_cnt 0 2006.259.07:56:02.21#ibcon#cleared, iclass 34 cls_cnt 0 2006.259.07:56:02.21$vc4f8/valo=8,852.99 2006.259.07:56:02.21#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.259.07:56:02.21#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.259.07:56:02.21#ibcon#ireg 17 cls_cnt 0 2006.259.07:56:02.21#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.259.07:56:02.21#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.259.07:56:02.21#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.259.07:56:02.21#ibcon#enter wrdev, iclass 36, count 0 2006.259.07:56:02.21#ibcon#first serial, iclass 36, count 0 2006.259.07:56:02.21#ibcon#enter sib2, iclass 36, count 0 2006.259.07:56:02.21#ibcon#flushed, iclass 36, count 0 2006.259.07:56:02.21#ibcon#about to write, iclass 36, count 0 2006.259.07:56:02.21#ibcon#wrote, iclass 36, count 0 2006.259.07:56:02.21#ibcon#about to read 3, iclass 36, count 0 2006.259.07:56:02.23#ibcon#read 3, iclass 36, count 0 2006.259.07:56:02.23#ibcon#about to read 4, iclass 36, count 0 2006.259.07:56:02.23#ibcon#read 4, iclass 36, count 0 2006.259.07:56:02.23#ibcon#about to read 5, iclass 36, count 0 2006.259.07:56:02.23#ibcon#read 5, iclass 36, count 0 2006.259.07:56:02.23#ibcon#about to read 6, iclass 36, count 0 2006.259.07:56:02.23#ibcon#read 6, iclass 36, count 0 2006.259.07:56:02.23#ibcon#end of sib2, iclass 36, count 0 2006.259.07:56:02.23#ibcon#*mode == 0, iclass 36, count 0 2006.259.07:56:02.23#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.259.07:56:02.23#ibcon#[26=FRQ=08,852.99\r\n] 2006.259.07:56:02.23#ibcon#*before write, iclass 36, count 0 2006.259.07:56:02.23#ibcon#enter sib2, iclass 36, count 0 2006.259.07:56:02.23#ibcon#flushed, iclass 36, count 0 2006.259.07:56:02.23#ibcon#about to write, iclass 36, count 0 2006.259.07:56:02.23#ibcon#wrote, iclass 36, count 0 2006.259.07:56:02.23#ibcon#about to read 3, iclass 36, count 0 2006.259.07:56:02.27#ibcon#read 3, iclass 36, count 0 2006.259.07:56:02.27#ibcon#about to read 4, iclass 36, count 0 2006.259.07:56:02.27#ibcon#read 4, iclass 36, count 0 2006.259.07:56:02.27#ibcon#about to read 5, iclass 36, count 0 2006.259.07:56:02.27#ibcon#read 5, iclass 36, count 0 2006.259.07:56:02.27#ibcon#about to read 6, iclass 36, count 0 2006.259.07:56:02.27#ibcon#read 6, iclass 36, count 0 2006.259.07:56:02.27#ibcon#end of sib2, iclass 36, count 0 2006.259.07:56:02.27#ibcon#*after write, iclass 36, count 0 2006.259.07:56:02.27#ibcon#*before return 0, iclass 36, count 0 2006.259.07:56:02.27#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.259.07:56:02.27#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.259.07:56:02.27#ibcon#about to clear, iclass 36 cls_cnt 0 2006.259.07:56:02.27#ibcon#cleared, iclass 36 cls_cnt 0 2006.259.07:56:02.27$vc4f8/va=8,6 2006.259.07:56:02.27#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.259.07:56:02.27#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.259.07:56:02.27#ibcon#ireg 11 cls_cnt 2 2006.259.07:56:02.27#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.259.07:56:02.33#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.259.07:56:02.33#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.259.07:56:02.33#ibcon#enter wrdev, iclass 38, count 2 2006.259.07:56:02.33#ibcon#first serial, iclass 38, count 2 2006.259.07:56:02.33#ibcon#enter sib2, iclass 38, count 2 2006.259.07:56:02.33#ibcon#flushed, iclass 38, count 2 2006.259.07:56:02.33#ibcon#about to write, iclass 38, count 2 2006.259.07:56:02.33#ibcon#wrote, iclass 38, count 2 2006.259.07:56:02.33#ibcon#about to read 3, iclass 38, count 2 2006.259.07:56:02.35#ibcon#read 3, iclass 38, count 2 2006.259.07:56:02.35#ibcon#about to read 4, iclass 38, count 2 2006.259.07:56:02.35#ibcon#read 4, iclass 38, count 2 2006.259.07:56:02.35#ibcon#about to read 5, iclass 38, count 2 2006.259.07:56:02.35#ibcon#read 5, iclass 38, count 2 2006.259.07:56:02.35#ibcon#about to read 6, iclass 38, count 2 2006.259.07:56:02.35#ibcon#read 6, iclass 38, count 2 2006.259.07:56:02.35#ibcon#end of sib2, iclass 38, count 2 2006.259.07:56:02.35#ibcon#*mode == 0, iclass 38, count 2 2006.259.07:56:02.35#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.259.07:56:02.35#ibcon#[25=AT08-06\r\n] 2006.259.07:56:02.35#ibcon#*before write, iclass 38, count 2 2006.259.07:56:02.35#ibcon#enter sib2, iclass 38, count 2 2006.259.07:56:02.35#ibcon#flushed, iclass 38, count 2 2006.259.07:56:02.35#ibcon#about to write, iclass 38, count 2 2006.259.07:56:02.35#ibcon#wrote, iclass 38, count 2 2006.259.07:56:02.35#ibcon#about to read 3, iclass 38, count 2 2006.259.07:56:02.38#ibcon#read 3, iclass 38, count 2 2006.259.07:56:02.38#ibcon#about to read 4, iclass 38, count 2 2006.259.07:56:02.38#ibcon#read 4, iclass 38, count 2 2006.259.07:56:02.38#ibcon#about to read 5, iclass 38, count 2 2006.259.07:56:02.38#ibcon#read 5, iclass 38, count 2 2006.259.07:56:02.38#ibcon#about to read 6, iclass 38, count 2 2006.259.07:56:02.38#ibcon#read 6, iclass 38, count 2 2006.259.07:56:02.38#ibcon#end of sib2, iclass 38, count 2 2006.259.07:56:02.38#ibcon#*after write, iclass 38, count 2 2006.259.07:56:02.38#ibcon#*before return 0, iclass 38, count 2 2006.259.07:56:02.38#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.259.07:56:02.38#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.259.07:56:02.38#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.259.07:56:02.38#ibcon#ireg 7 cls_cnt 0 2006.259.07:56:02.38#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.259.07:56:02.50#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.259.07:56:02.50#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.259.07:56:02.50#ibcon#enter wrdev, iclass 38, count 0 2006.259.07:56:02.50#ibcon#first serial, iclass 38, count 0 2006.259.07:56:02.50#ibcon#enter sib2, iclass 38, count 0 2006.259.07:56:02.50#ibcon#flushed, iclass 38, count 0 2006.259.07:56:02.50#ibcon#about to write, iclass 38, count 0 2006.259.07:56:02.50#ibcon#wrote, iclass 38, count 0 2006.259.07:56:02.50#ibcon#about to read 3, iclass 38, count 0 2006.259.07:56:02.52#ibcon#read 3, iclass 38, count 0 2006.259.07:56:02.52#ibcon#about to read 4, iclass 38, count 0 2006.259.07:56:02.52#ibcon#read 4, iclass 38, count 0 2006.259.07:56:02.52#ibcon#about to read 5, iclass 38, count 0 2006.259.07:56:02.52#ibcon#read 5, iclass 38, count 0 2006.259.07:56:02.52#ibcon#about to read 6, iclass 38, count 0 2006.259.07:56:02.52#ibcon#read 6, iclass 38, count 0 2006.259.07:56:02.52#ibcon#end of sib2, iclass 38, count 0 2006.259.07:56:02.52#ibcon#*mode == 0, iclass 38, count 0 2006.259.07:56:02.52#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.259.07:56:02.52#ibcon#[25=USB\r\n] 2006.259.07:56:02.52#ibcon#*before write, iclass 38, count 0 2006.259.07:56:02.52#ibcon#enter sib2, iclass 38, count 0 2006.259.07:56:02.52#ibcon#flushed, iclass 38, count 0 2006.259.07:56:02.52#ibcon#about to write, iclass 38, count 0 2006.259.07:56:02.52#ibcon#wrote, iclass 38, count 0 2006.259.07:56:02.52#ibcon#about to read 3, iclass 38, count 0 2006.259.07:56:02.55#ibcon#read 3, iclass 38, count 0 2006.259.07:56:02.55#ibcon#about to read 4, iclass 38, count 0 2006.259.07:56:02.55#ibcon#read 4, iclass 38, count 0 2006.259.07:56:02.55#ibcon#about to read 5, iclass 38, count 0 2006.259.07:56:02.55#ibcon#read 5, iclass 38, count 0 2006.259.07:56:02.55#ibcon#about to read 6, iclass 38, count 0 2006.259.07:56:02.55#ibcon#read 6, iclass 38, count 0 2006.259.07:56:02.55#ibcon#end of sib2, iclass 38, count 0 2006.259.07:56:02.55#ibcon#*after write, iclass 38, count 0 2006.259.07:56:02.55#ibcon#*before return 0, iclass 38, count 0 2006.259.07:56:02.55#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.259.07:56:02.55#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.259.07:56:02.55#ibcon#about to clear, iclass 38 cls_cnt 0 2006.259.07:56:02.55#ibcon#cleared, iclass 38 cls_cnt 0 2006.259.07:56:02.55$vc4f8/vblo=1,632.99 2006.259.07:56:02.55#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.259.07:56:02.55#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.259.07:56:02.55#ibcon#ireg 17 cls_cnt 0 2006.259.07:56:02.55#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.259.07:56:02.55#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.259.07:56:02.55#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.259.07:56:02.55#ibcon#enter wrdev, iclass 40, count 0 2006.259.07:56:02.55#ibcon#first serial, iclass 40, count 0 2006.259.07:56:02.55#ibcon#enter sib2, iclass 40, count 0 2006.259.07:56:02.55#ibcon#flushed, iclass 40, count 0 2006.259.07:56:02.55#ibcon#about to write, iclass 40, count 0 2006.259.07:56:02.55#ibcon#wrote, iclass 40, count 0 2006.259.07:56:02.55#ibcon#about to read 3, iclass 40, count 0 2006.259.07:56:02.57#ibcon#read 3, iclass 40, count 0 2006.259.07:56:02.57#ibcon#about to read 4, iclass 40, count 0 2006.259.07:56:02.57#ibcon#read 4, iclass 40, count 0 2006.259.07:56:02.57#ibcon#about to read 5, iclass 40, count 0 2006.259.07:56:02.57#ibcon#read 5, iclass 40, count 0 2006.259.07:56:02.57#ibcon#about to read 6, iclass 40, count 0 2006.259.07:56:02.57#ibcon#read 6, iclass 40, count 0 2006.259.07:56:02.57#ibcon#end of sib2, iclass 40, count 0 2006.259.07:56:02.57#ibcon#*mode == 0, iclass 40, count 0 2006.259.07:56:02.57#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.259.07:56:02.57#ibcon#[28=FRQ=01,632.99\r\n] 2006.259.07:56:02.57#ibcon#*before write, iclass 40, count 0 2006.259.07:56:02.57#ibcon#enter sib2, iclass 40, count 0 2006.259.07:56:02.57#ibcon#flushed, iclass 40, count 0 2006.259.07:56:02.57#ibcon#about to write, iclass 40, count 0 2006.259.07:56:02.57#ibcon#wrote, iclass 40, count 0 2006.259.07:56:02.57#ibcon#about to read 3, iclass 40, count 0 2006.259.07:56:02.61#ibcon#read 3, iclass 40, count 0 2006.259.07:56:02.61#ibcon#about to read 4, iclass 40, count 0 2006.259.07:56:02.61#ibcon#read 4, iclass 40, count 0 2006.259.07:56:02.61#ibcon#about to read 5, iclass 40, count 0 2006.259.07:56:02.61#ibcon#read 5, iclass 40, count 0 2006.259.07:56:02.61#ibcon#about to read 6, iclass 40, count 0 2006.259.07:56:02.61#ibcon#read 6, iclass 40, count 0 2006.259.07:56:02.61#ibcon#end of sib2, iclass 40, count 0 2006.259.07:56:02.61#ibcon#*after write, iclass 40, count 0 2006.259.07:56:02.61#ibcon#*before return 0, iclass 40, count 0 2006.259.07:56:02.61#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.259.07:56:02.61#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.259.07:56:02.61#ibcon#about to clear, iclass 40 cls_cnt 0 2006.259.07:56:02.61#ibcon#cleared, iclass 40 cls_cnt 0 2006.259.07:56:02.61$vc4f8/vb=1,4 2006.259.07:56:02.61#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.259.07:56:02.61#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.259.07:56:02.61#ibcon#ireg 11 cls_cnt 2 2006.259.07:56:02.61#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.259.07:56:02.61#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.259.07:56:02.61#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.259.07:56:02.61#ibcon#enter wrdev, iclass 4, count 2 2006.259.07:56:02.61#ibcon#first serial, iclass 4, count 2 2006.259.07:56:02.61#ibcon#enter sib2, iclass 4, count 2 2006.259.07:56:02.61#ibcon#flushed, iclass 4, count 2 2006.259.07:56:02.61#ibcon#about to write, iclass 4, count 2 2006.259.07:56:02.61#ibcon#wrote, iclass 4, count 2 2006.259.07:56:02.61#ibcon#about to read 3, iclass 4, count 2 2006.259.07:56:02.63#ibcon#read 3, iclass 4, count 2 2006.259.07:56:02.63#ibcon#about to read 4, iclass 4, count 2 2006.259.07:56:02.63#ibcon#read 4, iclass 4, count 2 2006.259.07:56:02.63#ibcon#about to read 5, iclass 4, count 2 2006.259.07:56:02.63#ibcon#read 5, iclass 4, count 2 2006.259.07:56:02.63#ibcon#about to read 6, iclass 4, count 2 2006.259.07:56:02.63#ibcon#read 6, iclass 4, count 2 2006.259.07:56:02.63#ibcon#end of sib2, iclass 4, count 2 2006.259.07:56:02.63#ibcon#*mode == 0, iclass 4, count 2 2006.259.07:56:02.63#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.259.07:56:02.63#ibcon#[27=AT01-04\r\n] 2006.259.07:56:02.63#ibcon#*before write, iclass 4, count 2 2006.259.07:56:02.63#ibcon#enter sib2, iclass 4, count 2 2006.259.07:56:02.63#ibcon#flushed, iclass 4, count 2 2006.259.07:56:02.63#ibcon#about to write, iclass 4, count 2 2006.259.07:56:02.63#ibcon#wrote, iclass 4, count 2 2006.259.07:56:02.63#ibcon#about to read 3, iclass 4, count 2 2006.259.07:56:02.66#ibcon#read 3, iclass 4, count 2 2006.259.07:56:02.66#ibcon#about to read 4, iclass 4, count 2 2006.259.07:56:02.66#ibcon#read 4, iclass 4, count 2 2006.259.07:56:02.66#ibcon#about to read 5, iclass 4, count 2 2006.259.07:56:02.66#ibcon#read 5, iclass 4, count 2 2006.259.07:56:02.66#ibcon#about to read 6, iclass 4, count 2 2006.259.07:56:02.66#ibcon#read 6, iclass 4, count 2 2006.259.07:56:02.66#ibcon#end of sib2, iclass 4, count 2 2006.259.07:56:02.66#ibcon#*after write, iclass 4, count 2 2006.259.07:56:02.66#ibcon#*before return 0, iclass 4, count 2 2006.259.07:56:02.66#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.259.07:56:02.66#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.259.07:56:02.66#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.259.07:56:02.66#ibcon#ireg 7 cls_cnt 0 2006.259.07:56:02.66#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.259.07:56:02.78#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.259.07:56:02.78#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.259.07:56:02.78#ibcon#enter wrdev, iclass 4, count 0 2006.259.07:56:02.78#ibcon#first serial, iclass 4, count 0 2006.259.07:56:02.78#ibcon#enter sib2, iclass 4, count 0 2006.259.07:56:02.78#ibcon#flushed, iclass 4, count 0 2006.259.07:56:02.78#ibcon#about to write, iclass 4, count 0 2006.259.07:56:02.78#ibcon#wrote, iclass 4, count 0 2006.259.07:56:02.78#ibcon#about to read 3, iclass 4, count 0 2006.259.07:56:02.80#ibcon#read 3, iclass 4, count 0 2006.259.07:56:02.80#ibcon#about to read 4, iclass 4, count 0 2006.259.07:56:02.80#ibcon#read 4, iclass 4, count 0 2006.259.07:56:02.80#ibcon#about to read 5, iclass 4, count 0 2006.259.07:56:02.80#ibcon#read 5, iclass 4, count 0 2006.259.07:56:02.80#ibcon#about to read 6, iclass 4, count 0 2006.259.07:56:02.80#ibcon#read 6, iclass 4, count 0 2006.259.07:56:02.80#ibcon#end of sib2, iclass 4, count 0 2006.259.07:56:02.80#ibcon#*mode == 0, iclass 4, count 0 2006.259.07:56:02.80#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.259.07:56:02.80#ibcon#[27=USB\r\n] 2006.259.07:56:02.80#ibcon#*before write, iclass 4, count 0 2006.259.07:56:02.80#ibcon#enter sib2, iclass 4, count 0 2006.259.07:56:02.80#ibcon#flushed, iclass 4, count 0 2006.259.07:56:02.80#ibcon#about to write, iclass 4, count 0 2006.259.07:56:02.80#ibcon#wrote, iclass 4, count 0 2006.259.07:56:02.80#ibcon#about to read 3, iclass 4, count 0 2006.259.07:56:02.83#ibcon#read 3, iclass 4, count 0 2006.259.07:56:02.83#ibcon#about to read 4, iclass 4, count 0 2006.259.07:56:02.83#ibcon#read 4, iclass 4, count 0 2006.259.07:56:02.83#ibcon#about to read 5, iclass 4, count 0 2006.259.07:56:02.83#ibcon#read 5, iclass 4, count 0 2006.259.07:56:02.83#ibcon#about to read 6, iclass 4, count 0 2006.259.07:56:02.83#ibcon#read 6, iclass 4, count 0 2006.259.07:56:02.83#ibcon#end of sib2, iclass 4, count 0 2006.259.07:56:02.83#ibcon#*after write, iclass 4, count 0 2006.259.07:56:02.83#ibcon#*before return 0, iclass 4, count 0 2006.259.07:56:02.83#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.259.07:56:02.83#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.259.07:56:02.83#ibcon#about to clear, iclass 4 cls_cnt 0 2006.259.07:56:02.83#ibcon#cleared, iclass 4 cls_cnt 0 2006.259.07:56:02.83$vc4f8/vblo=2,640.99 2006.259.07:56:02.83#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.259.07:56:02.83#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.259.07:56:02.83#ibcon#ireg 17 cls_cnt 0 2006.259.07:56:02.83#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.259.07:56:02.83#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.259.07:56:02.83#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.259.07:56:02.83#ibcon#enter wrdev, iclass 6, count 0 2006.259.07:56:02.83#ibcon#first serial, iclass 6, count 0 2006.259.07:56:02.83#ibcon#enter sib2, iclass 6, count 0 2006.259.07:56:02.83#ibcon#flushed, iclass 6, count 0 2006.259.07:56:02.83#ibcon#about to write, iclass 6, count 0 2006.259.07:56:02.83#ibcon#wrote, iclass 6, count 0 2006.259.07:56:02.83#ibcon#about to read 3, iclass 6, count 0 2006.259.07:56:02.85#ibcon#read 3, iclass 6, count 0 2006.259.07:56:02.85#ibcon#about to read 4, iclass 6, count 0 2006.259.07:56:02.85#ibcon#read 4, iclass 6, count 0 2006.259.07:56:02.85#ibcon#about to read 5, iclass 6, count 0 2006.259.07:56:02.85#ibcon#read 5, iclass 6, count 0 2006.259.07:56:02.85#ibcon#about to read 6, iclass 6, count 0 2006.259.07:56:02.85#ibcon#read 6, iclass 6, count 0 2006.259.07:56:02.85#ibcon#end of sib2, iclass 6, count 0 2006.259.07:56:02.85#ibcon#*mode == 0, iclass 6, count 0 2006.259.07:56:02.85#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.259.07:56:02.85#ibcon#[28=FRQ=02,640.99\r\n] 2006.259.07:56:02.85#ibcon#*before write, iclass 6, count 0 2006.259.07:56:02.85#ibcon#enter sib2, iclass 6, count 0 2006.259.07:56:02.85#ibcon#flushed, iclass 6, count 0 2006.259.07:56:02.85#ibcon#about to write, iclass 6, count 0 2006.259.07:56:02.85#ibcon#wrote, iclass 6, count 0 2006.259.07:56:02.85#ibcon#about to read 3, iclass 6, count 0 2006.259.07:56:02.89#ibcon#read 3, iclass 6, count 0 2006.259.07:56:02.89#ibcon#about to read 4, iclass 6, count 0 2006.259.07:56:02.89#ibcon#read 4, iclass 6, count 0 2006.259.07:56:02.89#ibcon#about to read 5, iclass 6, count 0 2006.259.07:56:02.89#ibcon#read 5, iclass 6, count 0 2006.259.07:56:02.89#ibcon#about to read 6, iclass 6, count 0 2006.259.07:56:02.89#ibcon#read 6, iclass 6, count 0 2006.259.07:56:02.89#ibcon#end of sib2, iclass 6, count 0 2006.259.07:56:02.89#ibcon#*after write, iclass 6, count 0 2006.259.07:56:02.89#ibcon#*before return 0, iclass 6, count 0 2006.259.07:56:02.89#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.259.07:56:02.89#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.259.07:56:02.89#ibcon#about to clear, iclass 6 cls_cnt 0 2006.259.07:56:02.89#ibcon#cleared, iclass 6 cls_cnt 0 2006.259.07:56:02.89$vc4f8/vb=2,5 2006.259.07:56:02.89#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.259.07:56:02.89#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.259.07:56:02.89#ibcon#ireg 11 cls_cnt 2 2006.259.07:56:02.89#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.259.07:56:02.95#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.259.07:56:02.95#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.259.07:56:02.95#ibcon#enter wrdev, iclass 10, count 2 2006.259.07:56:02.95#ibcon#first serial, iclass 10, count 2 2006.259.07:56:02.95#ibcon#enter sib2, iclass 10, count 2 2006.259.07:56:02.95#ibcon#flushed, iclass 10, count 2 2006.259.07:56:02.95#ibcon#about to write, iclass 10, count 2 2006.259.07:56:02.95#ibcon#wrote, iclass 10, count 2 2006.259.07:56:02.95#ibcon#about to read 3, iclass 10, count 2 2006.259.07:56:02.97#ibcon#read 3, iclass 10, count 2 2006.259.07:56:02.97#ibcon#about to read 4, iclass 10, count 2 2006.259.07:56:02.97#ibcon#read 4, iclass 10, count 2 2006.259.07:56:02.97#ibcon#about to read 5, iclass 10, count 2 2006.259.07:56:02.97#ibcon#read 5, iclass 10, count 2 2006.259.07:56:02.97#ibcon#about to read 6, iclass 10, count 2 2006.259.07:56:02.97#ibcon#read 6, iclass 10, count 2 2006.259.07:56:02.97#ibcon#end of sib2, iclass 10, count 2 2006.259.07:56:02.97#ibcon#*mode == 0, iclass 10, count 2 2006.259.07:56:02.97#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.259.07:56:02.97#ibcon#[27=AT02-05\r\n] 2006.259.07:56:02.97#ibcon#*before write, iclass 10, count 2 2006.259.07:56:02.97#ibcon#enter sib2, iclass 10, count 2 2006.259.07:56:02.97#ibcon#flushed, iclass 10, count 2 2006.259.07:56:02.97#ibcon#about to write, iclass 10, count 2 2006.259.07:56:02.97#ibcon#wrote, iclass 10, count 2 2006.259.07:56:02.97#ibcon#about to read 3, iclass 10, count 2 2006.259.07:56:03.00#ibcon#read 3, iclass 10, count 2 2006.259.07:56:03.00#ibcon#about to read 4, iclass 10, count 2 2006.259.07:56:03.00#ibcon#read 4, iclass 10, count 2 2006.259.07:56:03.00#ibcon#about to read 5, iclass 10, count 2 2006.259.07:56:03.00#ibcon#read 5, iclass 10, count 2 2006.259.07:56:03.00#ibcon#about to read 6, iclass 10, count 2 2006.259.07:56:03.00#ibcon#read 6, iclass 10, count 2 2006.259.07:56:03.00#ibcon#end of sib2, iclass 10, count 2 2006.259.07:56:03.00#ibcon#*after write, iclass 10, count 2 2006.259.07:56:03.00#ibcon#*before return 0, iclass 10, count 2 2006.259.07:56:03.00#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.259.07:56:03.00#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.259.07:56:03.00#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.259.07:56:03.00#ibcon#ireg 7 cls_cnt 0 2006.259.07:56:03.00#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.259.07:56:03.12#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.259.07:56:03.12#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.259.07:56:03.12#ibcon#enter wrdev, iclass 10, count 0 2006.259.07:56:03.12#ibcon#first serial, iclass 10, count 0 2006.259.07:56:03.12#ibcon#enter sib2, iclass 10, count 0 2006.259.07:56:03.12#ibcon#flushed, iclass 10, count 0 2006.259.07:56:03.12#ibcon#about to write, iclass 10, count 0 2006.259.07:56:03.12#ibcon#wrote, iclass 10, count 0 2006.259.07:56:03.12#ibcon#about to read 3, iclass 10, count 0 2006.259.07:56:03.14#ibcon#read 3, iclass 10, count 0 2006.259.07:56:03.14#ibcon#about to read 4, iclass 10, count 0 2006.259.07:56:03.14#ibcon#read 4, iclass 10, count 0 2006.259.07:56:03.14#ibcon#about to read 5, iclass 10, count 0 2006.259.07:56:03.14#ibcon#read 5, iclass 10, count 0 2006.259.07:56:03.14#ibcon#about to read 6, iclass 10, count 0 2006.259.07:56:03.14#ibcon#read 6, iclass 10, count 0 2006.259.07:56:03.14#ibcon#end of sib2, iclass 10, count 0 2006.259.07:56:03.14#ibcon#*mode == 0, iclass 10, count 0 2006.259.07:56:03.14#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.259.07:56:03.14#ibcon#[27=USB\r\n] 2006.259.07:56:03.14#ibcon#*before write, iclass 10, count 0 2006.259.07:56:03.14#ibcon#enter sib2, iclass 10, count 0 2006.259.07:56:03.14#ibcon#flushed, iclass 10, count 0 2006.259.07:56:03.14#ibcon#about to write, iclass 10, count 0 2006.259.07:56:03.14#ibcon#wrote, iclass 10, count 0 2006.259.07:56:03.14#ibcon#about to read 3, iclass 10, count 0 2006.259.07:56:03.17#ibcon#read 3, iclass 10, count 0 2006.259.07:56:03.17#ibcon#about to read 4, iclass 10, count 0 2006.259.07:56:03.17#ibcon#read 4, iclass 10, count 0 2006.259.07:56:03.17#ibcon#about to read 5, iclass 10, count 0 2006.259.07:56:03.17#ibcon#read 5, iclass 10, count 0 2006.259.07:56:03.17#ibcon#about to read 6, iclass 10, count 0 2006.259.07:56:03.17#ibcon#read 6, iclass 10, count 0 2006.259.07:56:03.17#ibcon#end of sib2, iclass 10, count 0 2006.259.07:56:03.17#ibcon#*after write, iclass 10, count 0 2006.259.07:56:03.17#ibcon#*before return 0, iclass 10, count 0 2006.259.07:56:03.17#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.259.07:56:03.17#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.259.07:56:03.17#ibcon#about to clear, iclass 10 cls_cnt 0 2006.259.07:56:03.17#ibcon#cleared, iclass 10 cls_cnt 0 2006.259.07:56:03.17$vc4f8/vblo=3,656.99 2006.259.07:56:03.17#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.259.07:56:03.17#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.259.07:56:03.17#ibcon#ireg 17 cls_cnt 0 2006.259.07:56:03.17#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.259.07:56:03.17#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.259.07:56:03.17#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.259.07:56:03.17#ibcon#enter wrdev, iclass 12, count 0 2006.259.07:56:03.17#ibcon#first serial, iclass 12, count 0 2006.259.07:56:03.17#ibcon#enter sib2, iclass 12, count 0 2006.259.07:56:03.17#ibcon#flushed, iclass 12, count 0 2006.259.07:56:03.17#ibcon#about to write, iclass 12, count 0 2006.259.07:56:03.17#ibcon#wrote, iclass 12, count 0 2006.259.07:56:03.17#ibcon#about to read 3, iclass 12, count 0 2006.259.07:56:03.20#ibcon#read 3, iclass 12, count 0 2006.259.07:56:03.20#ibcon#about to read 4, iclass 12, count 0 2006.259.07:56:03.20#ibcon#read 4, iclass 12, count 0 2006.259.07:56:03.20#ibcon#about to read 5, iclass 12, count 0 2006.259.07:56:03.20#ibcon#read 5, iclass 12, count 0 2006.259.07:56:03.20#ibcon#about to read 6, iclass 12, count 0 2006.259.07:56:03.20#ibcon#read 6, iclass 12, count 0 2006.259.07:56:03.20#ibcon#end of sib2, iclass 12, count 0 2006.259.07:56:03.20#ibcon#*mode == 0, iclass 12, count 0 2006.259.07:56:03.20#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.259.07:56:03.20#ibcon#[28=FRQ=03,656.99\r\n] 2006.259.07:56:03.20#ibcon#*before write, iclass 12, count 0 2006.259.07:56:03.20#ibcon#enter sib2, iclass 12, count 0 2006.259.07:56:03.20#ibcon#flushed, iclass 12, count 0 2006.259.07:56:03.20#ibcon#about to write, iclass 12, count 0 2006.259.07:56:03.20#ibcon#wrote, iclass 12, count 0 2006.259.07:56:03.20#ibcon#about to read 3, iclass 12, count 0 2006.259.07:56:03.24#ibcon#read 3, iclass 12, count 0 2006.259.07:56:03.24#ibcon#about to read 4, iclass 12, count 0 2006.259.07:56:03.24#ibcon#read 4, iclass 12, count 0 2006.259.07:56:03.24#ibcon#about to read 5, iclass 12, count 0 2006.259.07:56:03.24#ibcon#read 5, iclass 12, count 0 2006.259.07:56:03.24#ibcon#about to read 6, iclass 12, count 0 2006.259.07:56:03.24#ibcon#read 6, iclass 12, count 0 2006.259.07:56:03.24#ibcon#end of sib2, iclass 12, count 0 2006.259.07:56:03.24#ibcon#*after write, iclass 12, count 0 2006.259.07:56:03.24#ibcon#*before return 0, iclass 12, count 0 2006.259.07:56:03.24#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.259.07:56:03.24#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.259.07:56:03.24#ibcon#about to clear, iclass 12 cls_cnt 0 2006.259.07:56:03.24#ibcon#cleared, iclass 12 cls_cnt 0 2006.259.07:56:03.24$vc4f8/vb=3,4 2006.259.07:56:03.24#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.259.07:56:03.24#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.259.07:56:03.24#ibcon#ireg 11 cls_cnt 2 2006.259.07:56:03.24#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.259.07:56:03.29#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.259.07:56:03.29#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.259.07:56:03.29#ibcon#enter wrdev, iclass 14, count 2 2006.259.07:56:03.29#ibcon#first serial, iclass 14, count 2 2006.259.07:56:03.29#ibcon#enter sib2, iclass 14, count 2 2006.259.07:56:03.29#ibcon#flushed, iclass 14, count 2 2006.259.07:56:03.29#ibcon#about to write, iclass 14, count 2 2006.259.07:56:03.29#ibcon#wrote, iclass 14, count 2 2006.259.07:56:03.29#ibcon#about to read 3, iclass 14, count 2 2006.259.07:56:03.31#ibcon#read 3, iclass 14, count 2 2006.259.07:56:03.31#ibcon#about to read 4, iclass 14, count 2 2006.259.07:56:03.31#ibcon#read 4, iclass 14, count 2 2006.259.07:56:03.31#ibcon#about to read 5, iclass 14, count 2 2006.259.07:56:03.31#ibcon#read 5, iclass 14, count 2 2006.259.07:56:03.31#ibcon#about to read 6, iclass 14, count 2 2006.259.07:56:03.31#ibcon#read 6, iclass 14, count 2 2006.259.07:56:03.31#ibcon#end of sib2, iclass 14, count 2 2006.259.07:56:03.31#ibcon#*mode == 0, iclass 14, count 2 2006.259.07:56:03.31#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.259.07:56:03.31#ibcon#[27=AT03-04\r\n] 2006.259.07:56:03.31#ibcon#*before write, iclass 14, count 2 2006.259.07:56:03.31#ibcon#enter sib2, iclass 14, count 2 2006.259.07:56:03.31#ibcon#flushed, iclass 14, count 2 2006.259.07:56:03.31#ibcon#about to write, iclass 14, count 2 2006.259.07:56:03.31#ibcon#wrote, iclass 14, count 2 2006.259.07:56:03.31#ibcon#about to read 3, iclass 14, count 2 2006.259.07:56:03.34#ibcon#read 3, iclass 14, count 2 2006.259.07:56:03.34#ibcon#about to read 4, iclass 14, count 2 2006.259.07:56:03.34#ibcon#read 4, iclass 14, count 2 2006.259.07:56:03.34#ibcon#about to read 5, iclass 14, count 2 2006.259.07:56:03.34#ibcon#read 5, iclass 14, count 2 2006.259.07:56:03.34#ibcon#about to read 6, iclass 14, count 2 2006.259.07:56:03.34#ibcon#read 6, iclass 14, count 2 2006.259.07:56:03.34#ibcon#end of sib2, iclass 14, count 2 2006.259.07:56:03.34#ibcon#*after write, iclass 14, count 2 2006.259.07:56:03.34#ibcon#*before return 0, iclass 14, count 2 2006.259.07:56:03.34#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.259.07:56:03.34#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.259.07:56:03.34#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.259.07:56:03.34#ibcon#ireg 7 cls_cnt 0 2006.259.07:56:03.34#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.259.07:56:03.46#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.259.07:56:03.46#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.259.07:56:03.46#ibcon#enter wrdev, iclass 14, count 0 2006.259.07:56:03.46#ibcon#first serial, iclass 14, count 0 2006.259.07:56:03.46#ibcon#enter sib2, iclass 14, count 0 2006.259.07:56:03.46#ibcon#flushed, iclass 14, count 0 2006.259.07:56:03.46#ibcon#about to write, iclass 14, count 0 2006.259.07:56:03.46#ibcon#wrote, iclass 14, count 0 2006.259.07:56:03.46#ibcon#about to read 3, iclass 14, count 0 2006.259.07:56:03.48#ibcon#read 3, iclass 14, count 0 2006.259.07:56:03.48#ibcon#about to read 4, iclass 14, count 0 2006.259.07:56:03.48#ibcon#read 4, iclass 14, count 0 2006.259.07:56:03.48#ibcon#about to read 5, iclass 14, count 0 2006.259.07:56:03.48#ibcon#read 5, iclass 14, count 0 2006.259.07:56:03.48#ibcon#about to read 6, iclass 14, count 0 2006.259.07:56:03.48#ibcon#read 6, iclass 14, count 0 2006.259.07:56:03.48#ibcon#end of sib2, iclass 14, count 0 2006.259.07:56:03.48#ibcon#*mode == 0, iclass 14, count 0 2006.259.07:56:03.48#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.259.07:56:03.48#ibcon#[27=USB\r\n] 2006.259.07:56:03.48#ibcon#*before write, iclass 14, count 0 2006.259.07:56:03.48#ibcon#enter sib2, iclass 14, count 0 2006.259.07:56:03.48#ibcon#flushed, iclass 14, count 0 2006.259.07:56:03.48#ibcon#about to write, iclass 14, count 0 2006.259.07:56:03.48#ibcon#wrote, iclass 14, count 0 2006.259.07:56:03.48#ibcon#about to read 3, iclass 14, count 0 2006.259.07:56:03.51#ibcon#read 3, iclass 14, count 0 2006.259.07:56:03.51#ibcon#about to read 4, iclass 14, count 0 2006.259.07:56:03.51#ibcon#read 4, iclass 14, count 0 2006.259.07:56:03.51#ibcon#about to read 5, iclass 14, count 0 2006.259.07:56:03.51#ibcon#read 5, iclass 14, count 0 2006.259.07:56:03.51#ibcon#about to read 6, iclass 14, count 0 2006.259.07:56:03.51#ibcon#read 6, iclass 14, count 0 2006.259.07:56:03.51#ibcon#end of sib2, iclass 14, count 0 2006.259.07:56:03.51#ibcon#*after write, iclass 14, count 0 2006.259.07:56:03.51#ibcon#*before return 0, iclass 14, count 0 2006.259.07:56:03.51#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.259.07:56:03.51#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.259.07:56:03.51#ibcon#about to clear, iclass 14 cls_cnt 0 2006.259.07:56:03.51#ibcon#cleared, iclass 14 cls_cnt 0 2006.259.07:56:03.51$vc4f8/vblo=4,712.99 2006.259.07:56:03.51#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.259.07:56:03.51#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.259.07:56:03.51#ibcon#ireg 17 cls_cnt 0 2006.259.07:56:03.51#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.259.07:56:03.51#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.259.07:56:03.51#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.259.07:56:03.51#ibcon#enter wrdev, iclass 16, count 0 2006.259.07:56:03.51#ibcon#first serial, iclass 16, count 0 2006.259.07:56:03.51#ibcon#enter sib2, iclass 16, count 0 2006.259.07:56:03.51#ibcon#flushed, iclass 16, count 0 2006.259.07:56:03.51#ibcon#about to write, iclass 16, count 0 2006.259.07:56:03.51#ibcon#wrote, iclass 16, count 0 2006.259.07:56:03.51#ibcon#about to read 3, iclass 16, count 0 2006.259.07:56:03.53#ibcon#read 3, iclass 16, count 0 2006.259.07:56:03.53#ibcon#about to read 4, iclass 16, count 0 2006.259.07:56:03.53#ibcon#read 4, iclass 16, count 0 2006.259.07:56:03.53#ibcon#about to read 5, iclass 16, count 0 2006.259.07:56:03.53#ibcon#read 5, iclass 16, count 0 2006.259.07:56:03.53#ibcon#about to read 6, iclass 16, count 0 2006.259.07:56:03.53#ibcon#read 6, iclass 16, count 0 2006.259.07:56:03.53#ibcon#end of sib2, iclass 16, count 0 2006.259.07:56:03.53#ibcon#*mode == 0, iclass 16, count 0 2006.259.07:56:03.53#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.259.07:56:03.53#ibcon#[28=FRQ=04,712.99\r\n] 2006.259.07:56:03.53#ibcon#*before write, iclass 16, count 0 2006.259.07:56:03.53#ibcon#enter sib2, iclass 16, count 0 2006.259.07:56:03.53#ibcon#flushed, iclass 16, count 0 2006.259.07:56:03.53#ibcon#about to write, iclass 16, count 0 2006.259.07:56:03.53#ibcon#wrote, iclass 16, count 0 2006.259.07:56:03.53#ibcon#about to read 3, iclass 16, count 0 2006.259.07:56:03.57#ibcon#read 3, iclass 16, count 0 2006.259.07:56:03.57#ibcon#about to read 4, iclass 16, count 0 2006.259.07:56:03.57#ibcon#read 4, iclass 16, count 0 2006.259.07:56:03.57#ibcon#about to read 5, iclass 16, count 0 2006.259.07:56:03.57#ibcon#read 5, iclass 16, count 0 2006.259.07:56:03.57#ibcon#about to read 6, iclass 16, count 0 2006.259.07:56:03.57#ibcon#read 6, iclass 16, count 0 2006.259.07:56:03.57#ibcon#end of sib2, iclass 16, count 0 2006.259.07:56:03.57#ibcon#*after write, iclass 16, count 0 2006.259.07:56:03.57#ibcon#*before return 0, iclass 16, count 0 2006.259.07:56:03.57#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.259.07:56:03.57#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.259.07:56:03.57#ibcon#about to clear, iclass 16 cls_cnt 0 2006.259.07:56:03.57#ibcon#cleared, iclass 16 cls_cnt 0 2006.259.07:56:03.57$vc4f8/vb=4,5 2006.259.07:56:03.57#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.259.07:56:03.57#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.259.07:56:03.57#ibcon#ireg 11 cls_cnt 2 2006.259.07:56:03.57#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.259.07:56:03.63#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.259.07:56:03.63#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.259.07:56:03.63#ibcon#enter wrdev, iclass 18, count 2 2006.259.07:56:03.63#ibcon#first serial, iclass 18, count 2 2006.259.07:56:03.63#ibcon#enter sib2, iclass 18, count 2 2006.259.07:56:03.63#ibcon#flushed, iclass 18, count 2 2006.259.07:56:03.63#ibcon#about to write, iclass 18, count 2 2006.259.07:56:03.63#ibcon#wrote, iclass 18, count 2 2006.259.07:56:03.63#ibcon#about to read 3, iclass 18, count 2 2006.259.07:56:03.65#ibcon#read 3, iclass 18, count 2 2006.259.07:56:03.65#ibcon#about to read 4, iclass 18, count 2 2006.259.07:56:03.65#ibcon#read 4, iclass 18, count 2 2006.259.07:56:03.65#ibcon#about to read 5, iclass 18, count 2 2006.259.07:56:03.65#ibcon#read 5, iclass 18, count 2 2006.259.07:56:03.65#ibcon#about to read 6, iclass 18, count 2 2006.259.07:56:03.65#ibcon#read 6, iclass 18, count 2 2006.259.07:56:03.65#ibcon#end of sib2, iclass 18, count 2 2006.259.07:56:03.65#ibcon#*mode == 0, iclass 18, count 2 2006.259.07:56:03.65#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.259.07:56:03.65#ibcon#[27=AT04-05\r\n] 2006.259.07:56:03.65#ibcon#*before write, iclass 18, count 2 2006.259.07:56:03.65#ibcon#enter sib2, iclass 18, count 2 2006.259.07:56:03.65#ibcon#flushed, iclass 18, count 2 2006.259.07:56:03.65#ibcon#about to write, iclass 18, count 2 2006.259.07:56:03.65#ibcon#wrote, iclass 18, count 2 2006.259.07:56:03.65#ibcon#about to read 3, iclass 18, count 2 2006.259.07:56:03.68#ibcon#read 3, iclass 18, count 2 2006.259.07:56:03.68#ibcon#about to read 4, iclass 18, count 2 2006.259.07:56:03.68#ibcon#read 4, iclass 18, count 2 2006.259.07:56:03.68#ibcon#about to read 5, iclass 18, count 2 2006.259.07:56:03.68#ibcon#read 5, iclass 18, count 2 2006.259.07:56:03.68#ibcon#about to read 6, iclass 18, count 2 2006.259.07:56:03.68#ibcon#read 6, iclass 18, count 2 2006.259.07:56:03.68#ibcon#end of sib2, iclass 18, count 2 2006.259.07:56:03.68#ibcon#*after write, iclass 18, count 2 2006.259.07:56:03.68#ibcon#*before return 0, iclass 18, count 2 2006.259.07:56:03.68#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.259.07:56:03.68#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.259.07:56:03.68#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.259.07:56:03.68#ibcon#ireg 7 cls_cnt 0 2006.259.07:56:03.68#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.259.07:56:03.80#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.259.07:56:03.80#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.259.07:56:03.80#ibcon#enter wrdev, iclass 18, count 0 2006.259.07:56:03.80#ibcon#first serial, iclass 18, count 0 2006.259.07:56:03.80#ibcon#enter sib2, iclass 18, count 0 2006.259.07:56:03.80#ibcon#flushed, iclass 18, count 0 2006.259.07:56:03.80#ibcon#about to write, iclass 18, count 0 2006.259.07:56:03.80#ibcon#wrote, iclass 18, count 0 2006.259.07:56:03.80#ibcon#about to read 3, iclass 18, count 0 2006.259.07:56:03.82#ibcon#read 3, iclass 18, count 0 2006.259.07:56:03.82#ibcon#about to read 4, iclass 18, count 0 2006.259.07:56:03.82#ibcon#read 4, iclass 18, count 0 2006.259.07:56:03.82#ibcon#about to read 5, iclass 18, count 0 2006.259.07:56:03.82#ibcon#read 5, iclass 18, count 0 2006.259.07:56:03.82#ibcon#about to read 6, iclass 18, count 0 2006.259.07:56:03.82#ibcon#read 6, iclass 18, count 0 2006.259.07:56:03.82#ibcon#end of sib2, iclass 18, count 0 2006.259.07:56:03.82#ibcon#*mode == 0, iclass 18, count 0 2006.259.07:56:03.82#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.259.07:56:03.82#ibcon#[27=USB\r\n] 2006.259.07:56:03.82#ibcon#*before write, iclass 18, count 0 2006.259.07:56:03.82#ibcon#enter sib2, iclass 18, count 0 2006.259.07:56:03.82#ibcon#flushed, iclass 18, count 0 2006.259.07:56:03.82#ibcon#about to write, iclass 18, count 0 2006.259.07:56:03.82#ibcon#wrote, iclass 18, count 0 2006.259.07:56:03.82#ibcon#about to read 3, iclass 18, count 0 2006.259.07:56:03.85#ibcon#read 3, iclass 18, count 0 2006.259.07:56:03.85#ibcon#about to read 4, iclass 18, count 0 2006.259.07:56:03.85#ibcon#read 4, iclass 18, count 0 2006.259.07:56:03.85#ibcon#about to read 5, iclass 18, count 0 2006.259.07:56:03.85#ibcon#read 5, iclass 18, count 0 2006.259.07:56:03.85#ibcon#about to read 6, iclass 18, count 0 2006.259.07:56:03.85#ibcon#read 6, iclass 18, count 0 2006.259.07:56:03.85#ibcon#end of sib2, iclass 18, count 0 2006.259.07:56:03.85#ibcon#*after write, iclass 18, count 0 2006.259.07:56:03.85#ibcon#*before return 0, iclass 18, count 0 2006.259.07:56:03.85#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.259.07:56:03.85#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.259.07:56:03.85#ibcon#about to clear, iclass 18 cls_cnt 0 2006.259.07:56:03.85#ibcon#cleared, iclass 18 cls_cnt 0 2006.259.07:56:03.85$vc4f8/vblo=5,744.99 2006.259.07:56:03.85#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.259.07:56:03.85#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.259.07:56:03.85#ibcon#ireg 17 cls_cnt 0 2006.259.07:56:03.85#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.259.07:56:03.85#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.259.07:56:03.85#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.259.07:56:03.85#ibcon#enter wrdev, iclass 20, count 0 2006.259.07:56:03.85#ibcon#first serial, iclass 20, count 0 2006.259.07:56:03.85#ibcon#enter sib2, iclass 20, count 0 2006.259.07:56:03.85#ibcon#flushed, iclass 20, count 0 2006.259.07:56:03.85#ibcon#about to write, iclass 20, count 0 2006.259.07:56:03.85#ibcon#wrote, iclass 20, count 0 2006.259.07:56:03.85#ibcon#about to read 3, iclass 20, count 0 2006.259.07:56:03.87#ibcon#read 3, iclass 20, count 0 2006.259.07:56:03.87#ibcon#about to read 4, iclass 20, count 0 2006.259.07:56:03.87#ibcon#read 4, iclass 20, count 0 2006.259.07:56:03.87#ibcon#about to read 5, iclass 20, count 0 2006.259.07:56:03.87#ibcon#read 5, iclass 20, count 0 2006.259.07:56:03.87#ibcon#about to read 6, iclass 20, count 0 2006.259.07:56:03.87#ibcon#read 6, iclass 20, count 0 2006.259.07:56:03.87#ibcon#end of sib2, iclass 20, count 0 2006.259.07:56:03.87#ibcon#*mode == 0, iclass 20, count 0 2006.259.07:56:03.87#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.259.07:56:03.87#ibcon#[28=FRQ=05,744.99\r\n] 2006.259.07:56:03.87#ibcon#*before write, iclass 20, count 0 2006.259.07:56:03.87#ibcon#enter sib2, iclass 20, count 0 2006.259.07:56:03.87#ibcon#flushed, iclass 20, count 0 2006.259.07:56:03.87#ibcon#about to write, iclass 20, count 0 2006.259.07:56:03.87#ibcon#wrote, iclass 20, count 0 2006.259.07:56:03.87#ibcon#about to read 3, iclass 20, count 0 2006.259.07:56:03.91#ibcon#read 3, iclass 20, count 0 2006.259.07:56:03.91#ibcon#about to read 4, iclass 20, count 0 2006.259.07:56:03.91#ibcon#read 4, iclass 20, count 0 2006.259.07:56:03.91#ibcon#about to read 5, iclass 20, count 0 2006.259.07:56:03.91#ibcon#read 5, iclass 20, count 0 2006.259.07:56:03.91#ibcon#about to read 6, iclass 20, count 0 2006.259.07:56:03.91#ibcon#read 6, iclass 20, count 0 2006.259.07:56:03.91#ibcon#end of sib2, iclass 20, count 0 2006.259.07:56:03.91#ibcon#*after write, iclass 20, count 0 2006.259.07:56:03.91#ibcon#*before return 0, iclass 20, count 0 2006.259.07:56:03.91#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.259.07:56:03.91#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.259.07:56:03.91#ibcon#about to clear, iclass 20 cls_cnt 0 2006.259.07:56:03.91#ibcon#cleared, iclass 20 cls_cnt 0 2006.259.07:56:03.91$vc4f8/vb=5,4 2006.259.07:56:03.91#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.259.07:56:03.91#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.259.07:56:03.91#ibcon#ireg 11 cls_cnt 2 2006.259.07:56:03.91#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.259.07:56:03.97#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.259.07:56:03.97#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.259.07:56:03.97#ibcon#enter wrdev, iclass 22, count 2 2006.259.07:56:03.97#ibcon#first serial, iclass 22, count 2 2006.259.07:56:03.97#ibcon#enter sib2, iclass 22, count 2 2006.259.07:56:03.97#ibcon#flushed, iclass 22, count 2 2006.259.07:56:03.97#ibcon#about to write, iclass 22, count 2 2006.259.07:56:03.97#ibcon#wrote, iclass 22, count 2 2006.259.07:56:03.97#ibcon#about to read 3, iclass 22, count 2 2006.259.07:56:03.99#ibcon#read 3, iclass 22, count 2 2006.259.07:56:03.99#ibcon#about to read 4, iclass 22, count 2 2006.259.07:56:03.99#ibcon#read 4, iclass 22, count 2 2006.259.07:56:03.99#ibcon#about to read 5, iclass 22, count 2 2006.259.07:56:03.99#ibcon#read 5, iclass 22, count 2 2006.259.07:56:03.99#ibcon#about to read 6, iclass 22, count 2 2006.259.07:56:03.99#ibcon#read 6, iclass 22, count 2 2006.259.07:56:03.99#ibcon#end of sib2, iclass 22, count 2 2006.259.07:56:03.99#ibcon#*mode == 0, iclass 22, count 2 2006.259.07:56:03.99#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.259.07:56:03.99#ibcon#[27=AT05-04\r\n] 2006.259.07:56:03.99#ibcon#*before write, iclass 22, count 2 2006.259.07:56:03.99#ibcon#enter sib2, iclass 22, count 2 2006.259.07:56:03.99#ibcon#flushed, iclass 22, count 2 2006.259.07:56:03.99#ibcon#about to write, iclass 22, count 2 2006.259.07:56:03.99#ibcon#wrote, iclass 22, count 2 2006.259.07:56:03.99#ibcon#about to read 3, iclass 22, count 2 2006.259.07:56:04.02#ibcon#read 3, iclass 22, count 2 2006.259.07:56:04.02#ibcon#about to read 4, iclass 22, count 2 2006.259.07:56:04.02#ibcon#read 4, iclass 22, count 2 2006.259.07:56:04.02#ibcon#about to read 5, iclass 22, count 2 2006.259.07:56:04.02#ibcon#read 5, iclass 22, count 2 2006.259.07:56:04.02#ibcon#about to read 6, iclass 22, count 2 2006.259.07:56:04.02#ibcon#read 6, iclass 22, count 2 2006.259.07:56:04.02#ibcon#end of sib2, iclass 22, count 2 2006.259.07:56:04.02#ibcon#*after write, iclass 22, count 2 2006.259.07:56:04.02#ibcon#*before return 0, iclass 22, count 2 2006.259.07:56:04.02#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.259.07:56:04.02#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.259.07:56:04.02#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.259.07:56:04.02#ibcon#ireg 7 cls_cnt 0 2006.259.07:56:04.02#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.259.07:56:04.12#abcon#<5=/04 2.1 3.4 22.18 861013.0\r\n> 2006.259.07:56:04.14#abcon#{5=INTERFACE CLEAR} 2006.259.07:56:04.14#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.259.07:56:04.14#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.259.07:56:04.15#ibcon#enter wrdev, iclass 22, count 0 2006.259.07:56:04.15#ibcon#first serial, iclass 22, count 0 2006.259.07:56:04.15#ibcon#enter sib2, iclass 22, count 0 2006.259.07:56:04.15#ibcon#flushed, iclass 22, count 0 2006.259.07:56:04.15#ibcon#about to write, iclass 22, count 0 2006.259.07:56:04.15#ibcon#wrote, iclass 22, count 0 2006.259.07:56:04.15#ibcon#about to read 3, iclass 22, count 0 2006.259.07:56:04.16#ibcon#read 3, iclass 22, count 0 2006.259.07:56:04.16#ibcon#about to read 4, iclass 22, count 0 2006.259.07:56:04.16#ibcon#read 4, iclass 22, count 0 2006.259.07:56:04.16#ibcon#about to read 5, iclass 22, count 0 2006.259.07:56:04.16#ibcon#read 5, iclass 22, count 0 2006.259.07:56:04.16#ibcon#about to read 6, iclass 22, count 0 2006.259.07:56:04.16#ibcon#read 6, iclass 22, count 0 2006.259.07:56:04.16#ibcon#end of sib2, iclass 22, count 0 2006.259.07:56:04.16#ibcon#*mode == 0, iclass 22, count 0 2006.259.07:56:04.16#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.259.07:56:04.16#ibcon#[27=USB\r\n] 2006.259.07:56:04.16#ibcon#*before write, iclass 22, count 0 2006.259.07:56:04.16#ibcon#enter sib2, iclass 22, count 0 2006.259.07:56:04.16#ibcon#flushed, iclass 22, count 0 2006.259.07:56:04.16#ibcon#about to write, iclass 22, count 0 2006.259.07:56:04.16#ibcon#wrote, iclass 22, count 0 2006.259.07:56:04.16#ibcon#about to read 3, iclass 22, count 0 2006.259.07:56:04.19#ibcon#read 3, iclass 22, count 0 2006.259.07:56:04.19#ibcon#about to read 4, iclass 22, count 0 2006.259.07:56:04.19#ibcon#read 4, iclass 22, count 0 2006.259.07:56:04.19#ibcon#about to read 5, iclass 22, count 0 2006.259.07:56:04.19#ibcon#read 5, iclass 22, count 0 2006.259.07:56:04.19#ibcon#about to read 6, iclass 22, count 0 2006.259.07:56:04.19#ibcon#read 6, iclass 22, count 0 2006.259.07:56:04.19#ibcon#end of sib2, iclass 22, count 0 2006.259.07:56:04.19#ibcon#*after write, iclass 22, count 0 2006.259.07:56:04.19#ibcon#*before return 0, iclass 22, count 0 2006.259.07:56:04.19#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.259.07:56:04.19#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.259.07:56:04.19#ibcon#about to clear, iclass 22 cls_cnt 0 2006.259.07:56:04.19#ibcon#cleared, iclass 22 cls_cnt 0 2006.259.07:56:04.19$vc4f8/vblo=6,752.99 2006.259.07:56:04.19#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.259.07:56:04.19#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.259.07:56:04.19#ibcon#ireg 17 cls_cnt 0 2006.259.07:56:04.19#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.259.07:56:04.19#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.259.07:56:04.19#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.259.07:56:04.19#ibcon#enter wrdev, iclass 28, count 0 2006.259.07:56:04.19#ibcon#first serial, iclass 28, count 0 2006.259.07:56:04.19#ibcon#enter sib2, iclass 28, count 0 2006.259.07:56:04.19#ibcon#flushed, iclass 28, count 0 2006.259.07:56:04.19#ibcon#about to write, iclass 28, count 0 2006.259.07:56:04.19#ibcon#wrote, iclass 28, count 0 2006.259.07:56:04.19#ibcon#about to read 3, iclass 28, count 0 2006.259.07:56:04.20#abcon#[5=S1D000X0/0*\r\n] 2006.259.07:56:04.21#ibcon#read 3, iclass 28, count 0 2006.259.07:56:04.21#ibcon#about to read 4, iclass 28, count 0 2006.259.07:56:04.21#ibcon#read 4, iclass 28, count 0 2006.259.07:56:04.21#ibcon#about to read 5, iclass 28, count 0 2006.259.07:56:04.21#ibcon#read 5, iclass 28, count 0 2006.259.07:56:04.21#ibcon#about to read 6, iclass 28, count 0 2006.259.07:56:04.21#ibcon#read 6, iclass 28, count 0 2006.259.07:56:04.21#ibcon#end of sib2, iclass 28, count 0 2006.259.07:56:04.21#ibcon#*mode == 0, iclass 28, count 0 2006.259.07:56:04.21#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.259.07:56:04.21#ibcon#[28=FRQ=06,752.99\r\n] 2006.259.07:56:04.21#ibcon#*before write, iclass 28, count 0 2006.259.07:56:04.21#ibcon#enter sib2, iclass 28, count 0 2006.259.07:56:04.21#ibcon#flushed, iclass 28, count 0 2006.259.07:56:04.21#ibcon#about to write, iclass 28, count 0 2006.259.07:56:04.21#ibcon#wrote, iclass 28, count 0 2006.259.07:56:04.21#ibcon#about to read 3, iclass 28, count 0 2006.259.07:56:04.25#ibcon#read 3, iclass 28, count 0 2006.259.07:56:04.25#ibcon#about to read 4, iclass 28, count 0 2006.259.07:56:04.25#ibcon#read 4, iclass 28, count 0 2006.259.07:56:04.25#ibcon#about to read 5, iclass 28, count 0 2006.259.07:56:04.25#ibcon#read 5, iclass 28, count 0 2006.259.07:56:04.25#ibcon#about to read 6, iclass 28, count 0 2006.259.07:56:04.25#ibcon#read 6, iclass 28, count 0 2006.259.07:56:04.25#ibcon#end of sib2, iclass 28, count 0 2006.259.07:56:04.25#ibcon#*after write, iclass 28, count 0 2006.259.07:56:04.25#ibcon#*before return 0, iclass 28, count 0 2006.259.07:56:04.25#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.259.07:56:04.25#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.259.07:56:04.25#ibcon#about to clear, iclass 28 cls_cnt 0 2006.259.07:56:04.25#ibcon#cleared, iclass 28 cls_cnt 0 2006.259.07:56:04.25$vc4f8/vb=6,4 2006.259.07:56:04.25#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.259.07:56:04.25#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.259.07:56:04.25#ibcon#ireg 11 cls_cnt 2 2006.259.07:56:04.25#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.259.07:56:04.31#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.259.07:56:04.31#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.259.07:56:04.31#ibcon#enter wrdev, iclass 30, count 2 2006.259.07:56:04.31#ibcon#first serial, iclass 30, count 2 2006.259.07:56:04.31#ibcon#enter sib2, iclass 30, count 2 2006.259.07:56:04.31#ibcon#flushed, iclass 30, count 2 2006.259.07:56:04.31#ibcon#about to write, iclass 30, count 2 2006.259.07:56:04.31#ibcon#wrote, iclass 30, count 2 2006.259.07:56:04.31#ibcon#about to read 3, iclass 30, count 2 2006.259.07:56:04.33#ibcon#read 3, iclass 30, count 2 2006.259.07:56:04.33#ibcon#about to read 4, iclass 30, count 2 2006.259.07:56:04.33#ibcon#read 4, iclass 30, count 2 2006.259.07:56:04.33#ibcon#about to read 5, iclass 30, count 2 2006.259.07:56:04.33#ibcon#read 5, iclass 30, count 2 2006.259.07:56:04.33#ibcon#about to read 6, iclass 30, count 2 2006.259.07:56:04.33#ibcon#read 6, iclass 30, count 2 2006.259.07:56:04.33#ibcon#end of sib2, iclass 30, count 2 2006.259.07:56:04.33#ibcon#*mode == 0, iclass 30, count 2 2006.259.07:56:04.33#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.259.07:56:04.33#ibcon#[27=AT06-04\r\n] 2006.259.07:56:04.33#ibcon#*before write, iclass 30, count 2 2006.259.07:56:04.33#ibcon#enter sib2, iclass 30, count 2 2006.259.07:56:04.33#ibcon#flushed, iclass 30, count 2 2006.259.07:56:04.33#ibcon#about to write, iclass 30, count 2 2006.259.07:56:04.33#ibcon#wrote, iclass 30, count 2 2006.259.07:56:04.33#ibcon#about to read 3, iclass 30, count 2 2006.259.07:56:04.36#ibcon#read 3, iclass 30, count 2 2006.259.07:56:04.36#ibcon#about to read 4, iclass 30, count 2 2006.259.07:56:04.36#ibcon#read 4, iclass 30, count 2 2006.259.07:56:04.36#ibcon#about to read 5, iclass 30, count 2 2006.259.07:56:04.36#ibcon#read 5, iclass 30, count 2 2006.259.07:56:04.36#ibcon#about to read 6, iclass 30, count 2 2006.259.07:56:04.36#ibcon#read 6, iclass 30, count 2 2006.259.07:56:04.36#ibcon#end of sib2, iclass 30, count 2 2006.259.07:56:04.36#ibcon#*after write, iclass 30, count 2 2006.259.07:56:04.36#ibcon#*before return 0, iclass 30, count 2 2006.259.07:56:04.36#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.259.07:56:04.36#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.259.07:56:04.36#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.259.07:56:04.36#ibcon#ireg 7 cls_cnt 0 2006.259.07:56:04.36#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.259.07:56:04.48#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.259.07:56:04.48#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.259.07:56:04.48#ibcon#enter wrdev, iclass 30, count 0 2006.259.07:56:04.48#ibcon#first serial, iclass 30, count 0 2006.259.07:56:04.48#ibcon#enter sib2, iclass 30, count 0 2006.259.07:56:04.48#ibcon#flushed, iclass 30, count 0 2006.259.07:56:04.48#ibcon#about to write, iclass 30, count 0 2006.259.07:56:04.48#ibcon#wrote, iclass 30, count 0 2006.259.07:56:04.48#ibcon#about to read 3, iclass 30, count 0 2006.259.07:56:04.50#ibcon#read 3, iclass 30, count 0 2006.259.07:56:04.50#ibcon#about to read 4, iclass 30, count 0 2006.259.07:56:04.50#ibcon#read 4, iclass 30, count 0 2006.259.07:56:04.50#ibcon#about to read 5, iclass 30, count 0 2006.259.07:56:04.50#ibcon#read 5, iclass 30, count 0 2006.259.07:56:04.50#ibcon#about to read 6, iclass 30, count 0 2006.259.07:56:04.50#ibcon#read 6, iclass 30, count 0 2006.259.07:56:04.50#ibcon#end of sib2, iclass 30, count 0 2006.259.07:56:04.50#ibcon#*mode == 0, iclass 30, count 0 2006.259.07:56:04.50#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.259.07:56:04.50#ibcon#[27=USB\r\n] 2006.259.07:56:04.50#ibcon#*before write, iclass 30, count 0 2006.259.07:56:04.50#ibcon#enter sib2, iclass 30, count 0 2006.259.07:56:04.50#ibcon#flushed, iclass 30, count 0 2006.259.07:56:04.50#ibcon#about to write, iclass 30, count 0 2006.259.07:56:04.50#ibcon#wrote, iclass 30, count 0 2006.259.07:56:04.50#ibcon#about to read 3, iclass 30, count 0 2006.259.07:56:04.53#ibcon#read 3, iclass 30, count 0 2006.259.07:56:04.53#ibcon#about to read 4, iclass 30, count 0 2006.259.07:56:04.53#ibcon#read 4, iclass 30, count 0 2006.259.07:56:04.53#ibcon#about to read 5, iclass 30, count 0 2006.259.07:56:04.53#ibcon#read 5, iclass 30, count 0 2006.259.07:56:04.53#ibcon#about to read 6, iclass 30, count 0 2006.259.07:56:04.53#ibcon#read 6, iclass 30, count 0 2006.259.07:56:04.53#ibcon#end of sib2, iclass 30, count 0 2006.259.07:56:04.53#ibcon#*after write, iclass 30, count 0 2006.259.07:56:04.53#ibcon#*before return 0, iclass 30, count 0 2006.259.07:56:04.53#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.259.07:56:04.53#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.259.07:56:04.53#ibcon#about to clear, iclass 30 cls_cnt 0 2006.259.07:56:04.53#ibcon#cleared, iclass 30 cls_cnt 0 2006.259.07:56:04.53$vc4f8/vabw=wide 2006.259.07:56:04.53#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.259.07:56:04.53#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.259.07:56:04.53#ibcon#ireg 8 cls_cnt 0 2006.259.07:56:04.53#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.259.07:56:04.53#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.259.07:56:04.53#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.259.07:56:04.53#ibcon#enter wrdev, iclass 32, count 0 2006.259.07:56:04.53#ibcon#first serial, iclass 32, count 0 2006.259.07:56:04.53#ibcon#enter sib2, iclass 32, count 0 2006.259.07:56:04.53#ibcon#flushed, iclass 32, count 0 2006.259.07:56:04.53#ibcon#about to write, iclass 32, count 0 2006.259.07:56:04.53#ibcon#wrote, iclass 32, count 0 2006.259.07:56:04.53#ibcon#about to read 3, iclass 32, count 0 2006.259.07:56:04.55#ibcon#read 3, iclass 32, count 0 2006.259.07:56:04.55#ibcon#about to read 4, iclass 32, count 0 2006.259.07:56:04.55#ibcon#read 4, iclass 32, count 0 2006.259.07:56:04.55#ibcon#about to read 5, iclass 32, count 0 2006.259.07:56:04.55#ibcon#read 5, iclass 32, count 0 2006.259.07:56:04.55#ibcon#about to read 6, iclass 32, count 0 2006.259.07:56:04.55#ibcon#read 6, iclass 32, count 0 2006.259.07:56:04.55#ibcon#end of sib2, iclass 32, count 0 2006.259.07:56:04.55#ibcon#*mode == 0, iclass 32, count 0 2006.259.07:56:04.55#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.259.07:56:04.55#ibcon#[25=BW32\r\n] 2006.259.07:56:04.55#ibcon#*before write, iclass 32, count 0 2006.259.07:56:04.55#ibcon#enter sib2, iclass 32, count 0 2006.259.07:56:04.55#ibcon#flushed, iclass 32, count 0 2006.259.07:56:04.55#ibcon#about to write, iclass 32, count 0 2006.259.07:56:04.55#ibcon#wrote, iclass 32, count 0 2006.259.07:56:04.55#ibcon#about to read 3, iclass 32, count 0 2006.259.07:56:04.58#ibcon#read 3, iclass 32, count 0 2006.259.07:56:04.58#ibcon#about to read 4, iclass 32, count 0 2006.259.07:56:04.58#ibcon#read 4, iclass 32, count 0 2006.259.07:56:04.58#ibcon#about to read 5, iclass 32, count 0 2006.259.07:56:04.58#ibcon#read 5, iclass 32, count 0 2006.259.07:56:04.58#ibcon#about to read 6, iclass 32, count 0 2006.259.07:56:04.58#ibcon#read 6, iclass 32, count 0 2006.259.07:56:04.58#ibcon#end of sib2, iclass 32, count 0 2006.259.07:56:04.58#ibcon#*after write, iclass 32, count 0 2006.259.07:56:04.58#ibcon#*before return 0, iclass 32, count 0 2006.259.07:56:04.58#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.259.07:56:04.58#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.259.07:56:04.58#ibcon#about to clear, iclass 32 cls_cnt 0 2006.259.07:56:04.58#ibcon#cleared, iclass 32 cls_cnt 0 2006.259.07:56:04.58$vc4f8/vbbw=wide 2006.259.07:56:04.58#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.259.07:56:04.58#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.259.07:56:04.58#ibcon#ireg 8 cls_cnt 0 2006.259.07:56:04.58#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.259.07:56:04.65#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.259.07:56:04.65#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.259.07:56:04.65#ibcon#enter wrdev, iclass 34, count 0 2006.259.07:56:04.65#ibcon#first serial, iclass 34, count 0 2006.259.07:56:04.65#ibcon#enter sib2, iclass 34, count 0 2006.259.07:56:04.65#ibcon#flushed, iclass 34, count 0 2006.259.07:56:04.65#ibcon#about to write, iclass 34, count 0 2006.259.07:56:04.65#ibcon#wrote, iclass 34, count 0 2006.259.07:56:04.65#ibcon#about to read 3, iclass 34, count 0 2006.259.07:56:04.67#ibcon#read 3, iclass 34, count 0 2006.259.07:56:04.67#ibcon#about to read 4, iclass 34, count 0 2006.259.07:56:04.67#ibcon#read 4, iclass 34, count 0 2006.259.07:56:04.67#ibcon#about to read 5, iclass 34, count 0 2006.259.07:56:04.67#ibcon#read 5, iclass 34, count 0 2006.259.07:56:04.67#ibcon#about to read 6, iclass 34, count 0 2006.259.07:56:04.67#ibcon#read 6, iclass 34, count 0 2006.259.07:56:04.67#ibcon#end of sib2, iclass 34, count 0 2006.259.07:56:04.67#ibcon#*mode == 0, iclass 34, count 0 2006.259.07:56:04.67#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.259.07:56:04.67#ibcon#[27=BW32\r\n] 2006.259.07:56:04.67#ibcon#*before write, iclass 34, count 0 2006.259.07:56:04.67#ibcon#enter sib2, iclass 34, count 0 2006.259.07:56:04.67#ibcon#flushed, iclass 34, count 0 2006.259.07:56:04.67#ibcon#about to write, iclass 34, count 0 2006.259.07:56:04.67#ibcon#wrote, iclass 34, count 0 2006.259.07:56:04.67#ibcon#about to read 3, iclass 34, count 0 2006.259.07:56:04.70#ibcon#read 3, iclass 34, count 0 2006.259.07:56:04.70#ibcon#about to read 4, iclass 34, count 0 2006.259.07:56:04.70#ibcon#read 4, iclass 34, count 0 2006.259.07:56:04.70#ibcon#about to read 5, iclass 34, count 0 2006.259.07:56:04.70#ibcon#read 5, iclass 34, count 0 2006.259.07:56:04.70#ibcon#about to read 6, iclass 34, count 0 2006.259.07:56:04.70#ibcon#read 6, iclass 34, count 0 2006.259.07:56:04.70#ibcon#end of sib2, iclass 34, count 0 2006.259.07:56:04.70#ibcon#*after write, iclass 34, count 0 2006.259.07:56:04.70#ibcon#*before return 0, iclass 34, count 0 2006.259.07:56:04.70#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.259.07:56:04.70#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.259.07:56:04.70#ibcon#about to clear, iclass 34 cls_cnt 0 2006.259.07:56:04.70#ibcon#cleared, iclass 34 cls_cnt 0 2006.259.07:56:04.70$4f8m12a/ifd4f 2006.259.07:56:04.70$ifd4f/lo= 2006.259.07:56:04.70$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.259.07:56:04.70$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.259.07:56:04.71$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.259.07:56:04.71$ifd4f/patch= 2006.259.07:56:04.71$ifd4f/patch=lo1,a1,a2,a3,a4 2006.259.07:56:04.71$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.259.07:56:04.71$ifd4f/patch=lo3,a5,a6,a7,a8 2006.259.07:56:04.71$4f8m12a/"form=m,16.000,1:2 2006.259.07:56:04.71$4f8m12a/"tpicd 2006.259.07:56:04.71$4f8m12a/echo=off 2006.259.07:56:04.71$4f8m12a/xlog=off 2006.259.07:56:04.71:!2006.259.07:58:10 2006.259.07:56:40.13#trakl#Source acquired 2006.259.07:56:42.13#flagr#flagr/antenna,acquired 2006.259.07:58:10.01:preob 2006.259.07:58:11.13/onsource/TRACKING 2006.259.07:58:11.13:!2006.259.07:58:20 2006.259.07:58:20.00:data_valid=on 2006.259.07:58:20.00:midob 2006.259.07:58:20.14/onsource/TRACKING 2006.259.07:58:20.14/wx/22.15,1013.0,86 2006.259.07:58:20.31/cable/+6.4587E-03 2006.259.07:58:21.40/va/01,08,usb,yes,30,32 2006.259.07:58:21.40/va/02,07,usb,yes,30,32 2006.259.07:58:21.40/va/03,08,usb,yes,23,23 2006.259.07:58:21.40/va/04,07,usb,yes,31,34 2006.259.07:58:21.40/va/05,07,usb,yes,35,37 2006.259.07:58:21.40/va/06,06,usb,yes,34,34 2006.259.07:58:21.40/va/07,06,usb,yes,34,34 2006.259.07:58:21.40/va/08,06,usb,yes,37,36 2006.259.07:58:21.63/valo/01,532.99,yes,locked 2006.259.07:58:21.63/valo/02,572.99,yes,locked 2006.259.07:58:21.63/valo/03,672.99,yes,locked 2006.259.07:58:21.63/valo/04,832.99,yes,locked 2006.259.07:58:21.63/valo/05,652.99,yes,locked 2006.259.07:58:21.63/valo/06,772.99,yes,locked 2006.259.07:58:21.63/valo/07,832.99,yes,locked 2006.259.07:58:21.63/valo/08,852.99,yes,locked 2006.259.07:58:22.72/vb/01,04,usb,yes,30,29 2006.259.07:58:22.72/vb/02,05,usb,yes,28,30 2006.259.07:58:22.72/vb/03,04,usb,yes,28,32 2006.259.07:58:22.72/vb/04,05,usb,yes,26,26 2006.259.07:58:22.72/vb/05,04,usb,yes,28,32 2006.259.07:58:22.72/vb/06,04,usb,yes,29,31 2006.259.07:58:22.72/vb/07,04,usb,yes,31,31 2006.259.07:58:22.72/vb/08,04,usb,yes,28,32 2006.259.07:58:22.96/vblo/01,632.99,yes,locked 2006.259.07:58:22.96/vblo/02,640.99,yes,locked 2006.259.07:58:22.96/vblo/03,656.99,yes,locked 2006.259.07:58:22.96/vblo/04,712.99,yes,locked 2006.259.07:58:22.96/vblo/05,744.99,yes,locked 2006.259.07:58:22.96/vblo/06,752.99,yes,locked 2006.259.07:58:22.96/vblo/07,734.99,yes,locked 2006.259.07:58:22.96/vblo/08,744.99,yes,locked 2006.259.07:58:23.11/vabw/8 2006.259.07:58:23.26/vbbw/8 2006.259.07:58:23.35/xfe/off,on,15.2 2006.259.07:58:23.72/ifatt/23,28,28,28 2006.259.07:58:24.07/fmout-gps/S +4.57E-07 2006.259.07:58:24.11:!2006.259.07:59:20 2006.259.07:59:20.01:data_valid=off 2006.259.07:59:20.02:postob 2006.259.07:59:20.12/cable/+6.4576E-03 2006.259.07:59:20.13/wx/22.14,1013.0,86 2006.259.07:59:21.07/fmout-gps/S +4.57E-07 2006.259.07:59:21.08:scan_name=259-0800,k06259,60 2006.259.07:59:21.08:source=1417+385,141946.61,382148.5,2000.0,ccw 2006.259.07:59:22.14#flagr#flagr/antenna,new-source 2006.259.07:59:22.15:checkk5 2006.259.07:59:22.58/chk_autoobs//k5ts1/ autoobs is running! 2006.259.07:59:22.99/chk_autoobs//k5ts2/ autoobs is running! 2006.259.07:59:23.36/chk_autoobs//k5ts3/ autoobs is running! 2006.259.07:59:23.78/chk_autoobs//k5ts4/ autoobs is running! 2006.259.07:59:24.16/chk_obsdata//k5ts1/T2590758??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.259.07:59:24.86/chk_obsdata//k5ts2/T2590758??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.259.07:59:25.28/chk_obsdata//k5ts3/T2590758??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.259.07:59:25.67/chk_obsdata//k5ts4/T2590758??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.259.07:59:26.44/k5log//k5ts1_log_newline 2006.259.07:59:27.20/k5log//k5ts2_log_newline 2006.259.07:59:27.99/k5log//k5ts3_log_newline 2006.259.07:59:28.78/k5log//k5ts4_log_newline 2006.259.07:59:28.81/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.259.07:59:28.81:4f8m12a=2 2006.259.07:59:28.81$4f8m12a/echo=on 2006.259.07:59:28.81$4f8m12a/pcalon 2006.259.07:59:28.81$pcalon/"no phase cal control is implemented here 2006.259.07:59:28.81$4f8m12a/"tpicd=stop 2006.259.07:59:28.81$4f8m12a/vc4f8 2006.259.07:59:28.81$vc4f8/valo=1,532.99 2006.259.07:59:28.82#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.259.07:59:28.82#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.259.07:59:28.82#ibcon#ireg 17 cls_cnt 0 2006.259.07:59:28.82#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.259.07:59:28.82#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.259.07:59:28.82#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.259.07:59:28.82#ibcon#enter wrdev, iclass 7, count 0 2006.259.07:59:28.82#ibcon#first serial, iclass 7, count 0 2006.259.07:59:28.82#ibcon#enter sib2, iclass 7, count 0 2006.259.07:59:28.82#ibcon#flushed, iclass 7, count 0 2006.259.07:59:28.82#ibcon#about to write, iclass 7, count 0 2006.259.07:59:28.82#ibcon#wrote, iclass 7, count 0 2006.259.07:59:28.82#ibcon#about to read 3, iclass 7, count 0 2006.259.07:59:28.85#ibcon#read 3, iclass 7, count 0 2006.259.07:59:28.85#ibcon#about to read 4, iclass 7, count 0 2006.259.07:59:28.85#ibcon#read 4, iclass 7, count 0 2006.259.07:59:28.85#ibcon#about to read 5, iclass 7, count 0 2006.259.07:59:28.85#ibcon#read 5, iclass 7, count 0 2006.259.07:59:28.85#ibcon#about to read 6, iclass 7, count 0 2006.259.07:59:28.85#ibcon#read 6, iclass 7, count 0 2006.259.07:59:28.85#ibcon#end of sib2, iclass 7, count 0 2006.259.07:59:28.85#ibcon#*mode == 0, iclass 7, count 0 2006.259.07:59:28.85#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.259.07:59:28.85#ibcon#[26=FRQ=01,532.99\r\n] 2006.259.07:59:28.85#ibcon#*before write, iclass 7, count 0 2006.259.07:59:28.85#ibcon#enter sib2, iclass 7, count 0 2006.259.07:59:28.85#ibcon#flushed, iclass 7, count 0 2006.259.07:59:28.85#ibcon#about to write, iclass 7, count 0 2006.259.07:59:28.85#ibcon#wrote, iclass 7, count 0 2006.259.07:59:28.85#ibcon#about to read 3, iclass 7, count 0 2006.259.07:59:28.90#ibcon#read 3, iclass 7, count 0 2006.259.07:59:28.90#ibcon#about to read 4, iclass 7, count 0 2006.259.07:59:28.90#ibcon#read 4, iclass 7, count 0 2006.259.07:59:28.90#ibcon#about to read 5, iclass 7, count 0 2006.259.07:59:28.90#ibcon#read 5, iclass 7, count 0 2006.259.07:59:28.90#ibcon#about to read 6, iclass 7, count 0 2006.259.07:59:28.90#ibcon#read 6, iclass 7, count 0 2006.259.07:59:28.90#ibcon#end of sib2, iclass 7, count 0 2006.259.07:59:28.90#ibcon#*after write, iclass 7, count 0 2006.259.07:59:28.90#ibcon#*before return 0, iclass 7, count 0 2006.259.07:59:28.90#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.259.07:59:28.90#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.259.07:59:28.90#ibcon#about to clear, iclass 7 cls_cnt 0 2006.259.07:59:28.90#ibcon#cleared, iclass 7 cls_cnt 0 2006.259.07:59:28.90$vc4f8/va=1,8 2006.259.07:59:28.90#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.259.07:59:28.90#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.259.07:59:28.90#ibcon#ireg 11 cls_cnt 2 2006.259.07:59:28.90#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.259.07:59:28.90#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.259.07:59:28.90#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.259.07:59:28.90#ibcon#enter wrdev, iclass 11, count 2 2006.259.07:59:28.90#ibcon#first serial, iclass 11, count 2 2006.259.07:59:28.90#ibcon#enter sib2, iclass 11, count 2 2006.259.07:59:28.90#ibcon#flushed, iclass 11, count 2 2006.259.07:59:28.90#ibcon#about to write, iclass 11, count 2 2006.259.07:59:28.90#ibcon#wrote, iclass 11, count 2 2006.259.07:59:28.90#ibcon#about to read 3, iclass 11, count 2 2006.259.07:59:28.93#ibcon#read 3, iclass 11, count 2 2006.259.07:59:28.93#ibcon#about to read 4, iclass 11, count 2 2006.259.07:59:28.93#ibcon#read 4, iclass 11, count 2 2006.259.07:59:28.93#ibcon#about to read 5, iclass 11, count 2 2006.259.07:59:28.93#ibcon#read 5, iclass 11, count 2 2006.259.07:59:28.93#ibcon#about to read 6, iclass 11, count 2 2006.259.07:59:28.93#ibcon#read 6, iclass 11, count 2 2006.259.07:59:28.93#ibcon#end of sib2, iclass 11, count 2 2006.259.07:59:28.93#ibcon#*mode == 0, iclass 11, count 2 2006.259.07:59:28.93#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.259.07:59:28.93#ibcon#[25=AT01-08\r\n] 2006.259.07:59:28.93#ibcon#*before write, iclass 11, count 2 2006.259.07:59:28.93#ibcon#enter sib2, iclass 11, count 2 2006.259.07:59:28.93#ibcon#flushed, iclass 11, count 2 2006.259.07:59:28.93#ibcon#about to write, iclass 11, count 2 2006.259.07:59:28.93#ibcon#wrote, iclass 11, count 2 2006.259.07:59:28.93#ibcon#about to read 3, iclass 11, count 2 2006.259.07:59:28.96#ibcon#read 3, iclass 11, count 2 2006.259.07:59:28.96#ibcon#about to read 4, iclass 11, count 2 2006.259.07:59:28.96#ibcon#read 4, iclass 11, count 2 2006.259.07:59:28.96#ibcon#about to read 5, iclass 11, count 2 2006.259.07:59:28.96#ibcon#read 5, iclass 11, count 2 2006.259.07:59:28.96#ibcon#about to read 6, iclass 11, count 2 2006.259.07:59:28.96#ibcon#read 6, iclass 11, count 2 2006.259.07:59:28.96#ibcon#end of sib2, iclass 11, count 2 2006.259.07:59:28.96#ibcon#*after write, iclass 11, count 2 2006.259.07:59:28.96#ibcon#*before return 0, iclass 11, count 2 2006.259.07:59:28.96#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.259.07:59:28.96#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.259.07:59:28.96#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.259.07:59:28.96#ibcon#ireg 7 cls_cnt 0 2006.259.07:59:28.96#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.259.07:59:29.08#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.259.07:59:29.08#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.259.07:59:29.08#ibcon#enter wrdev, iclass 11, count 0 2006.259.07:59:29.08#ibcon#first serial, iclass 11, count 0 2006.259.07:59:29.08#ibcon#enter sib2, iclass 11, count 0 2006.259.07:59:29.08#ibcon#flushed, iclass 11, count 0 2006.259.07:59:29.08#ibcon#about to write, iclass 11, count 0 2006.259.07:59:29.08#ibcon#wrote, iclass 11, count 0 2006.259.07:59:29.08#ibcon#about to read 3, iclass 11, count 0 2006.259.07:59:29.10#ibcon#read 3, iclass 11, count 0 2006.259.07:59:29.10#ibcon#about to read 4, iclass 11, count 0 2006.259.07:59:29.10#ibcon#read 4, iclass 11, count 0 2006.259.07:59:29.10#ibcon#about to read 5, iclass 11, count 0 2006.259.07:59:29.10#ibcon#read 5, iclass 11, count 0 2006.259.07:59:29.10#ibcon#about to read 6, iclass 11, count 0 2006.259.07:59:29.10#ibcon#read 6, iclass 11, count 0 2006.259.07:59:29.10#ibcon#end of sib2, iclass 11, count 0 2006.259.07:59:29.10#ibcon#*mode == 0, iclass 11, count 0 2006.259.07:59:29.10#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.259.07:59:29.10#ibcon#[25=USB\r\n] 2006.259.07:59:29.10#ibcon#*before write, iclass 11, count 0 2006.259.07:59:29.10#ibcon#enter sib2, iclass 11, count 0 2006.259.07:59:29.10#ibcon#flushed, iclass 11, count 0 2006.259.07:59:29.10#ibcon#about to write, iclass 11, count 0 2006.259.07:59:29.10#ibcon#wrote, iclass 11, count 0 2006.259.07:59:29.10#ibcon#about to read 3, iclass 11, count 0 2006.259.07:59:29.13#ibcon#read 3, iclass 11, count 0 2006.259.07:59:29.13#ibcon#about to read 4, iclass 11, count 0 2006.259.07:59:29.13#ibcon#read 4, iclass 11, count 0 2006.259.07:59:29.13#ibcon#about to read 5, iclass 11, count 0 2006.259.07:59:29.13#ibcon#read 5, iclass 11, count 0 2006.259.07:59:29.13#ibcon#about to read 6, iclass 11, count 0 2006.259.07:59:29.13#ibcon#read 6, iclass 11, count 0 2006.259.07:59:29.13#ibcon#end of sib2, iclass 11, count 0 2006.259.07:59:29.13#ibcon#*after write, iclass 11, count 0 2006.259.07:59:29.13#ibcon#*before return 0, iclass 11, count 0 2006.259.07:59:29.13#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.259.07:59:29.13#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.259.07:59:29.13#ibcon#about to clear, iclass 11 cls_cnt 0 2006.259.07:59:29.13#ibcon#cleared, iclass 11 cls_cnt 0 2006.259.07:59:29.13$vc4f8/valo=2,572.99 2006.259.07:59:29.13#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.259.07:59:29.13#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.259.07:59:29.13#ibcon#ireg 17 cls_cnt 0 2006.259.07:59:29.13#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.259.07:59:29.13#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.259.07:59:29.13#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.259.07:59:29.13#ibcon#enter wrdev, iclass 13, count 0 2006.259.07:59:29.13#ibcon#first serial, iclass 13, count 0 2006.259.07:59:29.13#ibcon#enter sib2, iclass 13, count 0 2006.259.07:59:29.13#ibcon#flushed, iclass 13, count 0 2006.259.07:59:29.13#ibcon#about to write, iclass 13, count 0 2006.259.07:59:29.13#ibcon#wrote, iclass 13, count 0 2006.259.07:59:29.13#ibcon#about to read 3, iclass 13, count 0 2006.259.07:59:29.15#ibcon#read 3, iclass 13, count 0 2006.259.07:59:29.15#ibcon#about to read 4, iclass 13, count 0 2006.259.07:59:29.15#ibcon#read 4, iclass 13, count 0 2006.259.07:59:29.15#ibcon#about to read 5, iclass 13, count 0 2006.259.07:59:29.15#ibcon#read 5, iclass 13, count 0 2006.259.07:59:29.15#ibcon#about to read 6, iclass 13, count 0 2006.259.07:59:29.15#ibcon#read 6, iclass 13, count 0 2006.259.07:59:29.15#ibcon#end of sib2, iclass 13, count 0 2006.259.07:59:29.15#ibcon#*mode == 0, iclass 13, count 0 2006.259.07:59:29.15#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.259.07:59:29.15#ibcon#[26=FRQ=02,572.99\r\n] 2006.259.07:59:29.15#ibcon#*before write, iclass 13, count 0 2006.259.07:59:29.15#ibcon#enter sib2, iclass 13, count 0 2006.259.07:59:29.15#ibcon#flushed, iclass 13, count 0 2006.259.07:59:29.15#ibcon#about to write, iclass 13, count 0 2006.259.07:59:29.15#ibcon#wrote, iclass 13, count 0 2006.259.07:59:29.15#ibcon#about to read 3, iclass 13, count 0 2006.259.07:59:29.19#ibcon#read 3, iclass 13, count 0 2006.259.07:59:29.19#ibcon#about to read 4, iclass 13, count 0 2006.259.07:59:29.19#ibcon#read 4, iclass 13, count 0 2006.259.07:59:29.19#ibcon#about to read 5, iclass 13, count 0 2006.259.07:59:29.19#ibcon#read 5, iclass 13, count 0 2006.259.07:59:29.19#ibcon#about to read 6, iclass 13, count 0 2006.259.07:59:29.19#ibcon#read 6, iclass 13, count 0 2006.259.07:59:29.19#ibcon#end of sib2, iclass 13, count 0 2006.259.07:59:29.19#ibcon#*after write, iclass 13, count 0 2006.259.07:59:29.19#ibcon#*before return 0, iclass 13, count 0 2006.259.07:59:29.19#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.259.07:59:29.19#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.259.07:59:29.19#ibcon#about to clear, iclass 13 cls_cnt 0 2006.259.07:59:29.19#ibcon#cleared, iclass 13 cls_cnt 0 2006.259.07:59:29.19$vc4f8/va=2,7 2006.259.07:59:29.19#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.259.07:59:29.19#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.259.07:59:29.19#ibcon#ireg 11 cls_cnt 2 2006.259.07:59:29.19#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.259.07:59:29.25#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.259.07:59:29.25#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.259.07:59:29.25#ibcon#enter wrdev, iclass 15, count 2 2006.259.07:59:29.25#ibcon#first serial, iclass 15, count 2 2006.259.07:59:29.25#ibcon#enter sib2, iclass 15, count 2 2006.259.07:59:29.25#ibcon#flushed, iclass 15, count 2 2006.259.07:59:29.25#ibcon#about to write, iclass 15, count 2 2006.259.07:59:29.25#ibcon#wrote, iclass 15, count 2 2006.259.07:59:29.25#ibcon#about to read 3, iclass 15, count 2 2006.259.07:59:29.27#ibcon#read 3, iclass 15, count 2 2006.259.07:59:29.27#ibcon#about to read 4, iclass 15, count 2 2006.259.07:59:29.27#ibcon#read 4, iclass 15, count 2 2006.259.07:59:29.27#ibcon#about to read 5, iclass 15, count 2 2006.259.07:59:29.27#ibcon#read 5, iclass 15, count 2 2006.259.07:59:29.27#ibcon#about to read 6, iclass 15, count 2 2006.259.07:59:29.27#ibcon#read 6, iclass 15, count 2 2006.259.07:59:29.27#ibcon#end of sib2, iclass 15, count 2 2006.259.07:59:29.27#ibcon#*mode == 0, iclass 15, count 2 2006.259.07:59:29.27#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.259.07:59:29.27#ibcon#[25=AT02-07\r\n] 2006.259.07:59:29.27#ibcon#*before write, iclass 15, count 2 2006.259.07:59:29.27#ibcon#enter sib2, iclass 15, count 2 2006.259.07:59:29.27#ibcon#flushed, iclass 15, count 2 2006.259.07:59:29.27#ibcon#about to write, iclass 15, count 2 2006.259.07:59:29.27#ibcon#wrote, iclass 15, count 2 2006.259.07:59:29.27#ibcon#about to read 3, iclass 15, count 2 2006.259.07:59:29.30#ibcon#read 3, iclass 15, count 2 2006.259.07:59:29.30#ibcon#about to read 4, iclass 15, count 2 2006.259.07:59:29.30#ibcon#read 4, iclass 15, count 2 2006.259.07:59:29.30#ibcon#about to read 5, iclass 15, count 2 2006.259.07:59:29.30#ibcon#read 5, iclass 15, count 2 2006.259.07:59:29.30#ibcon#about to read 6, iclass 15, count 2 2006.259.07:59:29.30#ibcon#read 6, iclass 15, count 2 2006.259.07:59:29.30#ibcon#end of sib2, iclass 15, count 2 2006.259.07:59:29.30#ibcon#*after write, iclass 15, count 2 2006.259.07:59:29.30#ibcon#*before return 0, iclass 15, count 2 2006.259.07:59:29.30#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.259.07:59:29.30#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.259.07:59:29.30#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.259.07:59:29.30#ibcon#ireg 7 cls_cnt 0 2006.259.07:59:29.30#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.259.07:59:29.42#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.259.07:59:29.42#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.259.07:59:29.42#ibcon#enter wrdev, iclass 15, count 0 2006.259.07:59:29.42#ibcon#first serial, iclass 15, count 0 2006.259.07:59:29.42#ibcon#enter sib2, iclass 15, count 0 2006.259.07:59:29.42#ibcon#flushed, iclass 15, count 0 2006.259.07:59:29.42#ibcon#about to write, iclass 15, count 0 2006.259.07:59:29.42#ibcon#wrote, iclass 15, count 0 2006.259.07:59:29.42#ibcon#about to read 3, iclass 15, count 0 2006.259.07:59:29.44#ibcon#read 3, iclass 15, count 0 2006.259.07:59:29.44#ibcon#about to read 4, iclass 15, count 0 2006.259.07:59:29.44#ibcon#read 4, iclass 15, count 0 2006.259.07:59:29.44#ibcon#about to read 5, iclass 15, count 0 2006.259.07:59:29.44#ibcon#read 5, iclass 15, count 0 2006.259.07:59:29.44#ibcon#about to read 6, iclass 15, count 0 2006.259.07:59:29.44#ibcon#read 6, iclass 15, count 0 2006.259.07:59:29.44#ibcon#end of sib2, iclass 15, count 0 2006.259.07:59:29.44#ibcon#*mode == 0, iclass 15, count 0 2006.259.07:59:29.44#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.259.07:59:29.44#ibcon#[25=USB\r\n] 2006.259.07:59:29.44#ibcon#*before write, iclass 15, count 0 2006.259.07:59:29.44#ibcon#enter sib2, iclass 15, count 0 2006.259.07:59:29.44#ibcon#flushed, iclass 15, count 0 2006.259.07:59:29.44#ibcon#about to write, iclass 15, count 0 2006.259.07:59:29.44#ibcon#wrote, iclass 15, count 0 2006.259.07:59:29.44#ibcon#about to read 3, iclass 15, count 0 2006.259.07:59:29.47#ibcon#read 3, iclass 15, count 0 2006.259.07:59:29.47#ibcon#about to read 4, iclass 15, count 0 2006.259.07:59:29.47#ibcon#read 4, iclass 15, count 0 2006.259.07:59:29.47#ibcon#about to read 5, iclass 15, count 0 2006.259.07:59:29.47#ibcon#read 5, iclass 15, count 0 2006.259.07:59:29.47#ibcon#about to read 6, iclass 15, count 0 2006.259.07:59:29.47#ibcon#read 6, iclass 15, count 0 2006.259.07:59:29.47#ibcon#end of sib2, iclass 15, count 0 2006.259.07:59:29.47#ibcon#*after write, iclass 15, count 0 2006.259.07:59:29.47#ibcon#*before return 0, iclass 15, count 0 2006.259.07:59:29.47#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.259.07:59:29.47#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.259.07:59:29.47#ibcon#about to clear, iclass 15 cls_cnt 0 2006.259.07:59:29.47#ibcon#cleared, iclass 15 cls_cnt 0 2006.259.07:59:29.47$vc4f8/valo=3,672.99 2006.259.07:59:29.47#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.259.07:59:29.47#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.259.07:59:29.47#ibcon#ireg 17 cls_cnt 0 2006.259.07:59:29.47#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.259.07:59:29.47#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.259.07:59:29.47#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.259.07:59:29.47#ibcon#enter wrdev, iclass 17, count 0 2006.259.07:59:29.47#ibcon#first serial, iclass 17, count 0 2006.259.07:59:29.47#ibcon#enter sib2, iclass 17, count 0 2006.259.07:59:29.47#ibcon#flushed, iclass 17, count 0 2006.259.07:59:29.47#ibcon#about to write, iclass 17, count 0 2006.259.07:59:29.47#ibcon#wrote, iclass 17, count 0 2006.259.07:59:29.47#ibcon#about to read 3, iclass 17, count 0 2006.259.07:59:29.50#ibcon#read 3, iclass 17, count 0 2006.259.07:59:29.50#ibcon#about to read 4, iclass 17, count 0 2006.259.07:59:29.50#ibcon#read 4, iclass 17, count 0 2006.259.07:59:29.50#ibcon#about to read 5, iclass 17, count 0 2006.259.07:59:29.50#ibcon#read 5, iclass 17, count 0 2006.259.07:59:29.50#ibcon#about to read 6, iclass 17, count 0 2006.259.07:59:29.50#ibcon#read 6, iclass 17, count 0 2006.259.07:59:29.50#ibcon#end of sib2, iclass 17, count 0 2006.259.07:59:29.50#ibcon#*mode == 0, iclass 17, count 0 2006.259.07:59:29.50#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.259.07:59:29.50#ibcon#[26=FRQ=03,672.99\r\n] 2006.259.07:59:29.50#ibcon#*before write, iclass 17, count 0 2006.259.07:59:29.50#ibcon#enter sib2, iclass 17, count 0 2006.259.07:59:29.50#ibcon#flushed, iclass 17, count 0 2006.259.07:59:29.50#ibcon#about to write, iclass 17, count 0 2006.259.07:59:29.50#ibcon#wrote, iclass 17, count 0 2006.259.07:59:29.50#ibcon#about to read 3, iclass 17, count 0 2006.259.07:59:29.54#ibcon#read 3, iclass 17, count 0 2006.259.07:59:29.54#ibcon#about to read 4, iclass 17, count 0 2006.259.07:59:29.54#ibcon#read 4, iclass 17, count 0 2006.259.07:59:29.54#ibcon#about to read 5, iclass 17, count 0 2006.259.07:59:29.54#ibcon#read 5, iclass 17, count 0 2006.259.07:59:29.54#ibcon#about to read 6, iclass 17, count 0 2006.259.07:59:29.54#ibcon#read 6, iclass 17, count 0 2006.259.07:59:29.54#ibcon#end of sib2, iclass 17, count 0 2006.259.07:59:29.54#ibcon#*after write, iclass 17, count 0 2006.259.07:59:29.54#ibcon#*before return 0, iclass 17, count 0 2006.259.07:59:29.54#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.259.07:59:29.54#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.259.07:59:29.54#ibcon#about to clear, iclass 17 cls_cnt 0 2006.259.07:59:29.54#ibcon#cleared, iclass 17 cls_cnt 0 2006.259.07:59:29.54$vc4f8/va=3,8 2006.259.07:59:29.54#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.259.07:59:29.54#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.259.07:59:29.54#ibcon#ireg 11 cls_cnt 2 2006.259.07:59:29.54#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.259.07:59:29.59#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.259.07:59:29.59#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.259.07:59:29.59#ibcon#enter wrdev, iclass 19, count 2 2006.259.07:59:29.59#ibcon#first serial, iclass 19, count 2 2006.259.07:59:29.59#ibcon#enter sib2, iclass 19, count 2 2006.259.07:59:29.59#ibcon#flushed, iclass 19, count 2 2006.259.07:59:29.59#ibcon#about to write, iclass 19, count 2 2006.259.07:59:29.59#ibcon#wrote, iclass 19, count 2 2006.259.07:59:29.59#ibcon#about to read 3, iclass 19, count 2 2006.259.07:59:29.62#ibcon#read 3, iclass 19, count 2 2006.259.07:59:29.62#ibcon#about to read 4, iclass 19, count 2 2006.259.07:59:29.62#ibcon#read 4, iclass 19, count 2 2006.259.07:59:29.62#ibcon#about to read 5, iclass 19, count 2 2006.259.07:59:29.62#ibcon#read 5, iclass 19, count 2 2006.259.07:59:29.62#ibcon#about to read 6, iclass 19, count 2 2006.259.07:59:29.62#ibcon#read 6, iclass 19, count 2 2006.259.07:59:29.62#ibcon#end of sib2, iclass 19, count 2 2006.259.07:59:29.62#ibcon#*mode == 0, iclass 19, count 2 2006.259.07:59:29.62#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.259.07:59:29.62#ibcon#[25=AT03-08\r\n] 2006.259.07:59:29.62#ibcon#*before write, iclass 19, count 2 2006.259.07:59:29.62#ibcon#enter sib2, iclass 19, count 2 2006.259.07:59:29.62#ibcon#flushed, iclass 19, count 2 2006.259.07:59:29.62#ibcon#about to write, iclass 19, count 2 2006.259.07:59:29.62#ibcon#wrote, iclass 19, count 2 2006.259.07:59:29.62#ibcon#about to read 3, iclass 19, count 2 2006.259.07:59:29.65#ibcon#read 3, iclass 19, count 2 2006.259.07:59:29.65#ibcon#about to read 4, iclass 19, count 2 2006.259.07:59:29.65#ibcon#read 4, iclass 19, count 2 2006.259.07:59:29.65#ibcon#about to read 5, iclass 19, count 2 2006.259.07:59:29.65#ibcon#read 5, iclass 19, count 2 2006.259.07:59:29.65#ibcon#about to read 6, iclass 19, count 2 2006.259.07:59:29.65#ibcon#read 6, iclass 19, count 2 2006.259.07:59:29.65#ibcon#end of sib2, iclass 19, count 2 2006.259.07:59:29.65#ibcon#*after write, iclass 19, count 2 2006.259.07:59:29.65#ibcon#*before return 0, iclass 19, count 2 2006.259.07:59:29.65#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.259.07:59:29.65#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.259.07:59:29.65#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.259.07:59:29.65#ibcon#ireg 7 cls_cnt 0 2006.259.07:59:29.65#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.259.07:59:29.77#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.259.07:59:29.77#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.259.07:59:29.77#ibcon#enter wrdev, iclass 19, count 0 2006.259.07:59:29.77#ibcon#first serial, iclass 19, count 0 2006.259.07:59:29.77#ibcon#enter sib2, iclass 19, count 0 2006.259.07:59:29.77#ibcon#flushed, iclass 19, count 0 2006.259.07:59:29.77#ibcon#about to write, iclass 19, count 0 2006.259.07:59:29.77#ibcon#wrote, iclass 19, count 0 2006.259.07:59:29.77#ibcon#about to read 3, iclass 19, count 0 2006.259.07:59:29.79#ibcon#read 3, iclass 19, count 0 2006.259.07:59:29.79#ibcon#about to read 4, iclass 19, count 0 2006.259.07:59:29.79#ibcon#read 4, iclass 19, count 0 2006.259.07:59:29.79#ibcon#about to read 5, iclass 19, count 0 2006.259.07:59:29.79#ibcon#read 5, iclass 19, count 0 2006.259.07:59:29.79#ibcon#about to read 6, iclass 19, count 0 2006.259.07:59:29.79#ibcon#read 6, iclass 19, count 0 2006.259.07:59:29.79#ibcon#end of sib2, iclass 19, count 0 2006.259.07:59:29.79#ibcon#*mode == 0, iclass 19, count 0 2006.259.07:59:29.79#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.259.07:59:29.79#ibcon#[25=USB\r\n] 2006.259.07:59:29.79#ibcon#*before write, iclass 19, count 0 2006.259.07:59:29.79#ibcon#enter sib2, iclass 19, count 0 2006.259.07:59:29.79#ibcon#flushed, iclass 19, count 0 2006.259.07:59:29.79#ibcon#about to write, iclass 19, count 0 2006.259.07:59:29.79#ibcon#wrote, iclass 19, count 0 2006.259.07:59:29.79#ibcon#about to read 3, iclass 19, count 0 2006.259.07:59:29.82#ibcon#read 3, iclass 19, count 0 2006.259.07:59:29.82#ibcon#about to read 4, iclass 19, count 0 2006.259.07:59:29.82#ibcon#read 4, iclass 19, count 0 2006.259.07:59:29.82#ibcon#about to read 5, iclass 19, count 0 2006.259.07:59:29.82#ibcon#read 5, iclass 19, count 0 2006.259.07:59:29.82#ibcon#about to read 6, iclass 19, count 0 2006.259.07:59:29.82#ibcon#read 6, iclass 19, count 0 2006.259.07:59:29.82#ibcon#end of sib2, iclass 19, count 0 2006.259.07:59:29.82#ibcon#*after write, iclass 19, count 0 2006.259.07:59:29.82#ibcon#*before return 0, iclass 19, count 0 2006.259.07:59:29.82#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.259.07:59:29.82#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.259.07:59:29.82#ibcon#about to clear, iclass 19 cls_cnt 0 2006.259.07:59:29.82#ibcon#cleared, iclass 19 cls_cnt 0 2006.259.07:59:29.82$vc4f8/valo=4,832.99 2006.259.07:59:29.82#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.259.07:59:29.82#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.259.07:59:29.82#ibcon#ireg 17 cls_cnt 0 2006.259.07:59:29.82#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.259.07:59:29.82#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.259.07:59:29.82#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.259.07:59:29.82#ibcon#enter wrdev, iclass 21, count 0 2006.259.07:59:29.82#ibcon#first serial, iclass 21, count 0 2006.259.07:59:29.82#ibcon#enter sib2, iclass 21, count 0 2006.259.07:59:29.82#ibcon#flushed, iclass 21, count 0 2006.259.07:59:29.82#ibcon#about to write, iclass 21, count 0 2006.259.07:59:29.82#ibcon#wrote, iclass 21, count 0 2006.259.07:59:29.82#ibcon#about to read 3, iclass 21, count 0 2006.259.07:59:29.84#ibcon#read 3, iclass 21, count 0 2006.259.07:59:29.84#ibcon#about to read 4, iclass 21, count 0 2006.259.07:59:29.84#ibcon#read 4, iclass 21, count 0 2006.259.07:59:29.84#ibcon#about to read 5, iclass 21, count 0 2006.259.07:59:29.84#ibcon#read 5, iclass 21, count 0 2006.259.07:59:29.84#ibcon#about to read 6, iclass 21, count 0 2006.259.07:59:29.84#ibcon#read 6, iclass 21, count 0 2006.259.07:59:29.84#ibcon#end of sib2, iclass 21, count 0 2006.259.07:59:29.84#ibcon#*mode == 0, iclass 21, count 0 2006.259.07:59:29.84#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.259.07:59:29.84#ibcon#[26=FRQ=04,832.99\r\n] 2006.259.07:59:29.84#ibcon#*before write, iclass 21, count 0 2006.259.07:59:29.84#ibcon#enter sib2, iclass 21, count 0 2006.259.07:59:29.84#ibcon#flushed, iclass 21, count 0 2006.259.07:59:29.84#ibcon#about to write, iclass 21, count 0 2006.259.07:59:29.84#ibcon#wrote, iclass 21, count 0 2006.259.07:59:29.84#ibcon#about to read 3, iclass 21, count 0 2006.259.07:59:29.88#ibcon#read 3, iclass 21, count 0 2006.259.07:59:29.88#ibcon#about to read 4, iclass 21, count 0 2006.259.07:59:29.88#ibcon#read 4, iclass 21, count 0 2006.259.07:59:29.88#ibcon#about to read 5, iclass 21, count 0 2006.259.07:59:29.88#ibcon#read 5, iclass 21, count 0 2006.259.07:59:29.88#ibcon#about to read 6, iclass 21, count 0 2006.259.07:59:29.88#ibcon#read 6, iclass 21, count 0 2006.259.07:59:29.88#ibcon#end of sib2, iclass 21, count 0 2006.259.07:59:29.88#ibcon#*after write, iclass 21, count 0 2006.259.07:59:29.88#ibcon#*before return 0, iclass 21, count 0 2006.259.07:59:29.88#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.259.07:59:29.88#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.259.07:59:29.88#ibcon#about to clear, iclass 21 cls_cnt 0 2006.259.07:59:29.88#ibcon#cleared, iclass 21 cls_cnt 0 2006.259.07:59:29.88$vc4f8/va=4,7 2006.259.07:59:29.88#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.259.07:59:29.88#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.259.07:59:29.88#ibcon#ireg 11 cls_cnt 2 2006.259.07:59:29.88#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.259.07:59:29.94#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.259.07:59:29.94#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.259.07:59:29.94#ibcon#enter wrdev, iclass 23, count 2 2006.259.07:59:29.94#ibcon#first serial, iclass 23, count 2 2006.259.07:59:29.94#ibcon#enter sib2, iclass 23, count 2 2006.259.07:59:29.94#ibcon#flushed, iclass 23, count 2 2006.259.07:59:29.94#ibcon#about to write, iclass 23, count 2 2006.259.07:59:29.94#ibcon#wrote, iclass 23, count 2 2006.259.07:59:29.94#ibcon#about to read 3, iclass 23, count 2 2006.259.07:59:29.96#ibcon#read 3, iclass 23, count 2 2006.259.07:59:29.96#ibcon#about to read 4, iclass 23, count 2 2006.259.07:59:29.96#ibcon#read 4, iclass 23, count 2 2006.259.07:59:29.96#ibcon#about to read 5, iclass 23, count 2 2006.259.07:59:29.96#ibcon#read 5, iclass 23, count 2 2006.259.07:59:29.96#ibcon#about to read 6, iclass 23, count 2 2006.259.07:59:29.96#ibcon#read 6, iclass 23, count 2 2006.259.07:59:29.96#ibcon#end of sib2, iclass 23, count 2 2006.259.07:59:29.96#ibcon#*mode == 0, iclass 23, count 2 2006.259.07:59:29.96#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.259.07:59:29.96#ibcon#[25=AT04-07\r\n] 2006.259.07:59:29.96#ibcon#*before write, iclass 23, count 2 2006.259.07:59:29.96#ibcon#enter sib2, iclass 23, count 2 2006.259.07:59:29.96#ibcon#flushed, iclass 23, count 2 2006.259.07:59:29.96#ibcon#about to write, iclass 23, count 2 2006.259.07:59:29.96#ibcon#wrote, iclass 23, count 2 2006.259.07:59:29.96#ibcon#about to read 3, iclass 23, count 2 2006.259.07:59:29.99#ibcon#read 3, iclass 23, count 2 2006.259.07:59:29.99#ibcon#about to read 4, iclass 23, count 2 2006.259.07:59:29.99#ibcon#read 4, iclass 23, count 2 2006.259.07:59:29.99#ibcon#about to read 5, iclass 23, count 2 2006.259.07:59:29.99#ibcon#read 5, iclass 23, count 2 2006.259.07:59:29.99#ibcon#about to read 6, iclass 23, count 2 2006.259.07:59:29.99#ibcon#read 6, iclass 23, count 2 2006.259.07:59:29.99#ibcon#end of sib2, iclass 23, count 2 2006.259.07:59:29.99#ibcon#*after write, iclass 23, count 2 2006.259.07:59:29.99#ibcon#*before return 0, iclass 23, count 2 2006.259.07:59:29.99#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.259.07:59:29.99#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.259.07:59:29.99#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.259.07:59:29.99#ibcon#ireg 7 cls_cnt 0 2006.259.07:59:29.99#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.259.07:59:30.11#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.259.07:59:30.11#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.259.07:59:30.11#ibcon#enter wrdev, iclass 23, count 0 2006.259.07:59:30.11#ibcon#first serial, iclass 23, count 0 2006.259.07:59:30.11#ibcon#enter sib2, iclass 23, count 0 2006.259.07:59:30.11#ibcon#flushed, iclass 23, count 0 2006.259.07:59:30.11#ibcon#about to write, iclass 23, count 0 2006.259.07:59:30.11#ibcon#wrote, iclass 23, count 0 2006.259.07:59:30.11#ibcon#about to read 3, iclass 23, count 0 2006.259.07:59:30.13#ibcon#read 3, iclass 23, count 0 2006.259.07:59:30.13#ibcon#about to read 4, iclass 23, count 0 2006.259.07:59:30.13#ibcon#read 4, iclass 23, count 0 2006.259.07:59:30.13#ibcon#about to read 5, iclass 23, count 0 2006.259.07:59:30.13#ibcon#read 5, iclass 23, count 0 2006.259.07:59:30.13#ibcon#about to read 6, iclass 23, count 0 2006.259.07:59:30.13#ibcon#read 6, iclass 23, count 0 2006.259.07:59:30.13#ibcon#end of sib2, iclass 23, count 0 2006.259.07:59:30.13#ibcon#*mode == 0, iclass 23, count 0 2006.259.07:59:30.13#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.259.07:59:30.13#ibcon#[25=USB\r\n] 2006.259.07:59:30.13#ibcon#*before write, iclass 23, count 0 2006.259.07:59:30.13#ibcon#enter sib2, iclass 23, count 0 2006.259.07:59:30.13#ibcon#flushed, iclass 23, count 0 2006.259.07:59:30.13#ibcon#about to write, iclass 23, count 0 2006.259.07:59:30.13#ibcon#wrote, iclass 23, count 0 2006.259.07:59:30.13#ibcon#about to read 3, iclass 23, count 0 2006.259.07:59:30.16#ibcon#read 3, iclass 23, count 0 2006.259.07:59:30.16#ibcon#about to read 4, iclass 23, count 0 2006.259.07:59:30.16#ibcon#read 4, iclass 23, count 0 2006.259.07:59:30.16#ibcon#about to read 5, iclass 23, count 0 2006.259.07:59:30.16#ibcon#read 5, iclass 23, count 0 2006.259.07:59:30.16#ibcon#about to read 6, iclass 23, count 0 2006.259.07:59:30.16#ibcon#read 6, iclass 23, count 0 2006.259.07:59:30.16#ibcon#end of sib2, iclass 23, count 0 2006.259.07:59:30.16#ibcon#*after write, iclass 23, count 0 2006.259.07:59:30.16#ibcon#*before return 0, iclass 23, count 0 2006.259.07:59:30.16#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.259.07:59:30.16#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.259.07:59:30.16#ibcon#about to clear, iclass 23 cls_cnt 0 2006.259.07:59:30.16#ibcon#cleared, iclass 23 cls_cnt 0 2006.259.07:59:30.16$vc4f8/valo=5,652.99 2006.259.07:59:30.16#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.259.07:59:30.16#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.259.07:59:30.16#ibcon#ireg 17 cls_cnt 0 2006.259.07:59:30.16#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.259.07:59:30.16#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.259.07:59:30.16#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.259.07:59:30.16#ibcon#enter wrdev, iclass 25, count 0 2006.259.07:59:30.16#ibcon#first serial, iclass 25, count 0 2006.259.07:59:30.16#ibcon#enter sib2, iclass 25, count 0 2006.259.07:59:30.16#ibcon#flushed, iclass 25, count 0 2006.259.07:59:30.16#ibcon#about to write, iclass 25, count 0 2006.259.07:59:30.16#ibcon#wrote, iclass 25, count 0 2006.259.07:59:30.16#ibcon#about to read 3, iclass 25, count 0 2006.259.07:59:30.18#ibcon#read 3, iclass 25, count 0 2006.259.07:59:30.18#ibcon#about to read 4, iclass 25, count 0 2006.259.07:59:30.18#ibcon#read 4, iclass 25, count 0 2006.259.07:59:30.18#ibcon#about to read 5, iclass 25, count 0 2006.259.07:59:30.18#ibcon#read 5, iclass 25, count 0 2006.259.07:59:30.18#ibcon#about to read 6, iclass 25, count 0 2006.259.07:59:30.18#ibcon#read 6, iclass 25, count 0 2006.259.07:59:30.18#ibcon#end of sib2, iclass 25, count 0 2006.259.07:59:30.18#ibcon#*mode == 0, iclass 25, count 0 2006.259.07:59:30.18#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.259.07:59:30.18#ibcon#[26=FRQ=05,652.99\r\n] 2006.259.07:59:30.18#ibcon#*before write, iclass 25, count 0 2006.259.07:59:30.18#ibcon#enter sib2, iclass 25, count 0 2006.259.07:59:30.18#ibcon#flushed, iclass 25, count 0 2006.259.07:59:30.18#ibcon#about to write, iclass 25, count 0 2006.259.07:59:30.18#ibcon#wrote, iclass 25, count 0 2006.259.07:59:30.18#ibcon#about to read 3, iclass 25, count 0 2006.259.07:59:30.22#ibcon#read 3, iclass 25, count 0 2006.259.07:59:30.22#ibcon#about to read 4, iclass 25, count 0 2006.259.07:59:30.22#ibcon#read 4, iclass 25, count 0 2006.259.07:59:30.22#ibcon#about to read 5, iclass 25, count 0 2006.259.07:59:30.22#ibcon#read 5, iclass 25, count 0 2006.259.07:59:30.22#ibcon#about to read 6, iclass 25, count 0 2006.259.07:59:30.22#ibcon#read 6, iclass 25, count 0 2006.259.07:59:30.22#ibcon#end of sib2, iclass 25, count 0 2006.259.07:59:30.22#ibcon#*after write, iclass 25, count 0 2006.259.07:59:30.22#ibcon#*before return 0, iclass 25, count 0 2006.259.07:59:30.22#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.259.07:59:30.22#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.259.07:59:30.22#ibcon#about to clear, iclass 25 cls_cnt 0 2006.259.07:59:30.22#ibcon#cleared, iclass 25 cls_cnt 0 2006.259.07:59:30.22$vc4f8/va=5,7 2006.259.07:59:30.22#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.259.07:59:30.22#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.259.07:59:30.22#ibcon#ireg 11 cls_cnt 2 2006.259.07:59:30.22#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.259.07:59:30.28#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.259.07:59:30.28#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.259.07:59:30.28#ibcon#enter wrdev, iclass 27, count 2 2006.259.07:59:30.28#ibcon#first serial, iclass 27, count 2 2006.259.07:59:30.28#ibcon#enter sib2, iclass 27, count 2 2006.259.07:59:30.28#ibcon#flushed, iclass 27, count 2 2006.259.07:59:30.28#ibcon#about to write, iclass 27, count 2 2006.259.07:59:30.28#ibcon#wrote, iclass 27, count 2 2006.259.07:59:30.28#ibcon#about to read 3, iclass 27, count 2 2006.259.07:59:30.30#ibcon#read 3, iclass 27, count 2 2006.259.07:59:30.30#ibcon#about to read 4, iclass 27, count 2 2006.259.07:59:30.30#ibcon#read 4, iclass 27, count 2 2006.259.07:59:30.30#ibcon#about to read 5, iclass 27, count 2 2006.259.07:59:30.30#ibcon#read 5, iclass 27, count 2 2006.259.07:59:30.30#ibcon#about to read 6, iclass 27, count 2 2006.259.07:59:30.30#ibcon#read 6, iclass 27, count 2 2006.259.07:59:30.30#ibcon#end of sib2, iclass 27, count 2 2006.259.07:59:30.30#ibcon#*mode == 0, iclass 27, count 2 2006.259.07:59:30.30#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.259.07:59:30.30#ibcon#[25=AT05-07\r\n] 2006.259.07:59:30.30#ibcon#*before write, iclass 27, count 2 2006.259.07:59:30.30#ibcon#enter sib2, iclass 27, count 2 2006.259.07:59:30.30#ibcon#flushed, iclass 27, count 2 2006.259.07:59:30.30#ibcon#about to write, iclass 27, count 2 2006.259.07:59:30.30#ibcon#wrote, iclass 27, count 2 2006.259.07:59:30.30#ibcon#about to read 3, iclass 27, count 2 2006.259.07:59:30.33#ibcon#read 3, iclass 27, count 2 2006.259.07:59:30.33#ibcon#about to read 4, iclass 27, count 2 2006.259.07:59:30.33#ibcon#read 4, iclass 27, count 2 2006.259.07:59:30.33#ibcon#about to read 5, iclass 27, count 2 2006.259.07:59:30.33#ibcon#read 5, iclass 27, count 2 2006.259.07:59:30.33#ibcon#about to read 6, iclass 27, count 2 2006.259.07:59:30.33#ibcon#read 6, iclass 27, count 2 2006.259.07:59:30.33#ibcon#end of sib2, iclass 27, count 2 2006.259.07:59:30.33#ibcon#*after write, iclass 27, count 2 2006.259.07:59:30.33#ibcon#*before return 0, iclass 27, count 2 2006.259.07:59:30.33#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.259.07:59:30.33#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.259.07:59:30.33#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.259.07:59:30.33#ibcon#ireg 7 cls_cnt 0 2006.259.07:59:30.33#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.259.07:59:30.45#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.259.07:59:30.45#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.259.07:59:30.45#ibcon#enter wrdev, iclass 27, count 0 2006.259.07:59:30.45#ibcon#first serial, iclass 27, count 0 2006.259.07:59:30.45#ibcon#enter sib2, iclass 27, count 0 2006.259.07:59:30.45#ibcon#flushed, iclass 27, count 0 2006.259.07:59:30.45#ibcon#about to write, iclass 27, count 0 2006.259.07:59:30.45#ibcon#wrote, iclass 27, count 0 2006.259.07:59:30.45#ibcon#about to read 3, iclass 27, count 0 2006.259.07:59:30.47#ibcon#read 3, iclass 27, count 0 2006.259.07:59:30.47#ibcon#about to read 4, iclass 27, count 0 2006.259.07:59:30.47#ibcon#read 4, iclass 27, count 0 2006.259.07:59:30.47#ibcon#about to read 5, iclass 27, count 0 2006.259.07:59:30.47#ibcon#read 5, iclass 27, count 0 2006.259.07:59:30.47#ibcon#about to read 6, iclass 27, count 0 2006.259.07:59:30.47#ibcon#read 6, iclass 27, count 0 2006.259.07:59:30.47#ibcon#end of sib2, iclass 27, count 0 2006.259.07:59:30.47#ibcon#*mode == 0, iclass 27, count 0 2006.259.07:59:30.47#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.259.07:59:30.47#ibcon#[25=USB\r\n] 2006.259.07:59:30.47#ibcon#*before write, iclass 27, count 0 2006.259.07:59:30.47#ibcon#enter sib2, iclass 27, count 0 2006.259.07:59:30.47#ibcon#flushed, iclass 27, count 0 2006.259.07:59:30.47#ibcon#about to write, iclass 27, count 0 2006.259.07:59:30.47#ibcon#wrote, iclass 27, count 0 2006.259.07:59:30.47#ibcon#about to read 3, iclass 27, count 0 2006.259.07:59:30.50#ibcon#read 3, iclass 27, count 0 2006.259.07:59:30.50#ibcon#about to read 4, iclass 27, count 0 2006.259.07:59:30.50#ibcon#read 4, iclass 27, count 0 2006.259.07:59:30.50#ibcon#about to read 5, iclass 27, count 0 2006.259.07:59:30.50#ibcon#read 5, iclass 27, count 0 2006.259.07:59:30.50#ibcon#about to read 6, iclass 27, count 0 2006.259.07:59:30.50#ibcon#read 6, iclass 27, count 0 2006.259.07:59:30.50#ibcon#end of sib2, iclass 27, count 0 2006.259.07:59:30.50#ibcon#*after write, iclass 27, count 0 2006.259.07:59:30.50#ibcon#*before return 0, iclass 27, count 0 2006.259.07:59:30.50#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.259.07:59:30.50#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.259.07:59:30.50#ibcon#about to clear, iclass 27 cls_cnt 0 2006.259.07:59:30.50#ibcon#cleared, iclass 27 cls_cnt 0 2006.259.07:59:30.50$vc4f8/valo=6,772.99 2006.259.07:59:30.50#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.259.07:59:30.50#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.259.07:59:30.50#ibcon#ireg 17 cls_cnt 0 2006.259.07:59:30.50#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.259.07:59:30.50#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.259.07:59:30.50#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.259.07:59:30.50#ibcon#enter wrdev, iclass 29, count 0 2006.259.07:59:30.50#ibcon#first serial, iclass 29, count 0 2006.259.07:59:30.50#ibcon#enter sib2, iclass 29, count 0 2006.259.07:59:30.50#ibcon#flushed, iclass 29, count 0 2006.259.07:59:30.50#ibcon#about to write, iclass 29, count 0 2006.259.07:59:30.50#ibcon#wrote, iclass 29, count 0 2006.259.07:59:30.50#ibcon#about to read 3, iclass 29, count 0 2006.259.07:59:30.52#ibcon#read 3, iclass 29, count 0 2006.259.07:59:30.52#ibcon#about to read 4, iclass 29, count 0 2006.259.07:59:30.52#ibcon#read 4, iclass 29, count 0 2006.259.07:59:30.52#ibcon#about to read 5, iclass 29, count 0 2006.259.07:59:30.52#ibcon#read 5, iclass 29, count 0 2006.259.07:59:30.52#ibcon#about to read 6, iclass 29, count 0 2006.259.07:59:30.52#ibcon#read 6, iclass 29, count 0 2006.259.07:59:30.52#ibcon#end of sib2, iclass 29, count 0 2006.259.07:59:30.52#ibcon#*mode == 0, iclass 29, count 0 2006.259.07:59:30.52#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.259.07:59:30.52#ibcon#[26=FRQ=06,772.99\r\n] 2006.259.07:59:30.52#ibcon#*before write, iclass 29, count 0 2006.259.07:59:30.52#ibcon#enter sib2, iclass 29, count 0 2006.259.07:59:30.52#ibcon#flushed, iclass 29, count 0 2006.259.07:59:30.52#ibcon#about to write, iclass 29, count 0 2006.259.07:59:30.52#ibcon#wrote, iclass 29, count 0 2006.259.07:59:30.52#ibcon#about to read 3, iclass 29, count 0 2006.259.07:59:30.56#ibcon#read 3, iclass 29, count 0 2006.259.07:59:30.56#ibcon#about to read 4, iclass 29, count 0 2006.259.07:59:30.56#ibcon#read 4, iclass 29, count 0 2006.259.07:59:30.56#ibcon#about to read 5, iclass 29, count 0 2006.259.07:59:30.56#ibcon#read 5, iclass 29, count 0 2006.259.07:59:30.56#ibcon#about to read 6, iclass 29, count 0 2006.259.07:59:30.56#ibcon#read 6, iclass 29, count 0 2006.259.07:59:30.56#ibcon#end of sib2, iclass 29, count 0 2006.259.07:59:30.56#ibcon#*after write, iclass 29, count 0 2006.259.07:59:30.56#ibcon#*before return 0, iclass 29, count 0 2006.259.07:59:30.56#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.259.07:59:30.56#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.259.07:59:30.56#ibcon#about to clear, iclass 29 cls_cnt 0 2006.259.07:59:30.56#ibcon#cleared, iclass 29 cls_cnt 0 2006.259.07:59:30.56$vc4f8/va=6,6 2006.259.07:59:30.56#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.259.07:59:30.56#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.259.07:59:30.56#ibcon#ireg 11 cls_cnt 2 2006.259.07:59:30.56#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.259.07:59:30.62#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.259.07:59:30.62#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.259.07:59:30.62#ibcon#enter wrdev, iclass 31, count 2 2006.259.07:59:30.62#ibcon#first serial, iclass 31, count 2 2006.259.07:59:30.62#ibcon#enter sib2, iclass 31, count 2 2006.259.07:59:30.62#ibcon#flushed, iclass 31, count 2 2006.259.07:59:30.62#ibcon#about to write, iclass 31, count 2 2006.259.07:59:30.62#ibcon#wrote, iclass 31, count 2 2006.259.07:59:30.62#ibcon#about to read 3, iclass 31, count 2 2006.259.07:59:30.65#ibcon#read 3, iclass 31, count 2 2006.259.07:59:30.65#ibcon#about to read 4, iclass 31, count 2 2006.259.07:59:30.65#ibcon#read 4, iclass 31, count 2 2006.259.07:59:30.65#ibcon#about to read 5, iclass 31, count 2 2006.259.07:59:30.65#ibcon#read 5, iclass 31, count 2 2006.259.07:59:30.65#ibcon#about to read 6, iclass 31, count 2 2006.259.07:59:30.65#ibcon#read 6, iclass 31, count 2 2006.259.07:59:30.65#ibcon#end of sib2, iclass 31, count 2 2006.259.07:59:30.65#ibcon#*mode == 0, iclass 31, count 2 2006.259.07:59:30.65#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.259.07:59:30.65#ibcon#[25=AT06-06\r\n] 2006.259.07:59:30.65#ibcon#*before write, iclass 31, count 2 2006.259.07:59:30.65#ibcon#enter sib2, iclass 31, count 2 2006.259.07:59:30.65#ibcon#flushed, iclass 31, count 2 2006.259.07:59:30.65#ibcon#about to write, iclass 31, count 2 2006.259.07:59:30.65#ibcon#wrote, iclass 31, count 2 2006.259.07:59:30.65#ibcon#about to read 3, iclass 31, count 2 2006.259.07:59:30.68#ibcon#read 3, iclass 31, count 2 2006.259.07:59:30.68#ibcon#about to read 4, iclass 31, count 2 2006.259.07:59:30.68#ibcon#read 4, iclass 31, count 2 2006.259.07:59:30.68#ibcon#about to read 5, iclass 31, count 2 2006.259.07:59:30.68#ibcon#read 5, iclass 31, count 2 2006.259.07:59:30.68#ibcon#about to read 6, iclass 31, count 2 2006.259.07:59:30.68#ibcon#read 6, iclass 31, count 2 2006.259.07:59:30.68#ibcon#end of sib2, iclass 31, count 2 2006.259.07:59:30.68#ibcon#*after write, iclass 31, count 2 2006.259.07:59:30.68#ibcon#*before return 0, iclass 31, count 2 2006.259.07:59:30.68#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.259.07:59:30.68#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.259.07:59:30.68#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.259.07:59:30.68#ibcon#ireg 7 cls_cnt 0 2006.259.07:59:30.68#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.259.07:59:30.80#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.259.07:59:30.80#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.259.07:59:30.80#ibcon#enter wrdev, iclass 31, count 0 2006.259.07:59:30.80#ibcon#first serial, iclass 31, count 0 2006.259.07:59:30.80#ibcon#enter sib2, iclass 31, count 0 2006.259.07:59:30.80#ibcon#flushed, iclass 31, count 0 2006.259.07:59:30.80#ibcon#about to write, iclass 31, count 0 2006.259.07:59:30.80#ibcon#wrote, iclass 31, count 0 2006.259.07:59:30.80#ibcon#about to read 3, iclass 31, count 0 2006.259.07:59:30.82#ibcon#read 3, iclass 31, count 0 2006.259.07:59:30.82#ibcon#about to read 4, iclass 31, count 0 2006.259.07:59:30.82#ibcon#read 4, iclass 31, count 0 2006.259.07:59:30.82#ibcon#about to read 5, iclass 31, count 0 2006.259.07:59:30.82#ibcon#read 5, iclass 31, count 0 2006.259.07:59:30.82#ibcon#about to read 6, iclass 31, count 0 2006.259.07:59:30.82#ibcon#read 6, iclass 31, count 0 2006.259.07:59:30.82#ibcon#end of sib2, iclass 31, count 0 2006.259.07:59:30.82#ibcon#*mode == 0, iclass 31, count 0 2006.259.07:59:30.82#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.259.07:59:30.82#ibcon#[25=USB\r\n] 2006.259.07:59:30.82#ibcon#*before write, iclass 31, count 0 2006.259.07:59:30.82#ibcon#enter sib2, iclass 31, count 0 2006.259.07:59:30.82#ibcon#flushed, iclass 31, count 0 2006.259.07:59:30.82#ibcon#about to write, iclass 31, count 0 2006.259.07:59:30.82#ibcon#wrote, iclass 31, count 0 2006.259.07:59:30.82#ibcon#about to read 3, iclass 31, count 0 2006.259.07:59:30.85#ibcon#read 3, iclass 31, count 0 2006.259.07:59:30.85#ibcon#about to read 4, iclass 31, count 0 2006.259.07:59:30.85#ibcon#read 4, iclass 31, count 0 2006.259.07:59:30.85#ibcon#about to read 5, iclass 31, count 0 2006.259.07:59:30.85#ibcon#read 5, iclass 31, count 0 2006.259.07:59:30.85#ibcon#about to read 6, iclass 31, count 0 2006.259.07:59:30.85#ibcon#read 6, iclass 31, count 0 2006.259.07:59:30.85#ibcon#end of sib2, iclass 31, count 0 2006.259.07:59:30.85#ibcon#*after write, iclass 31, count 0 2006.259.07:59:30.85#ibcon#*before return 0, iclass 31, count 0 2006.259.07:59:30.85#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.259.07:59:30.85#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.259.07:59:30.85#ibcon#about to clear, iclass 31 cls_cnt 0 2006.259.07:59:30.85#ibcon#cleared, iclass 31 cls_cnt 0 2006.259.07:59:30.85$vc4f8/valo=7,832.99 2006.259.07:59:30.85#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.259.07:59:30.85#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.259.07:59:30.85#ibcon#ireg 17 cls_cnt 0 2006.259.07:59:30.85#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.259.07:59:30.85#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.259.07:59:30.85#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.259.07:59:30.85#ibcon#enter wrdev, iclass 33, count 0 2006.259.07:59:30.85#ibcon#first serial, iclass 33, count 0 2006.259.07:59:30.85#ibcon#enter sib2, iclass 33, count 0 2006.259.07:59:30.85#ibcon#flushed, iclass 33, count 0 2006.259.07:59:30.85#ibcon#about to write, iclass 33, count 0 2006.259.07:59:30.85#ibcon#wrote, iclass 33, count 0 2006.259.07:59:30.85#ibcon#about to read 3, iclass 33, count 0 2006.259.07:59:30.87#ibcon#read 3, iclass 33, count 0 2006.259.07:59:30.87#ibcon#about to read 4, iclass 33, count 0 2006.259.07:59:30.87#ibcon#read 4, iclass 33, count 0 2006.259.07:59:30.87#ibcon#about to read 5, iclass 33, count 0 2006.259.07:59:30.87#ibcon#read 5, iclass 33, count 0 2006.259.07:59:30.87#ibcon#about to read 6, iclass 33, count 0 2006.259.07:59:30.87#ibcon#read 6, iclass 33, count 0 2006.259.07:59:30.87#ibcon#end of sib2, iclass 33, count 0 2006.259.07:59:30.87#ibcon#*mode == 0, iclass 33, count 0 2006.259.07:59:30.87#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.259.07:59:30.87#ibcon#[26=FRQ=07,832.99\r\n] 2006.259.07:59:30.87#ibcon#*before write, iclass 33, count 0 2006.259.07:59:30.87#ibcon#enter sib2, iclass 33, count 0 2006.259.07:59:30.87#ibcon#flushed, iclass 33, count 0 2006.259.07:59:30.87#ibcon#about to write, iclass 33, count 0 2006.259.07:59:30.87#ibcon#wrote, iclass 33, count 0 2006.259.07:59:30.87#ibcon#about to read 3, iclass 33, count 0 2006.259.07:59:30.91#ibcon#read 3, iclass 33, count 0 2006.259.07:59:30.91#ibcon#about to read 4, iclass 33, count 0 2006.259.07:59:30.91#ibcon#read 4, iclass 33, count 0 2006.259.07:59:30.91#ibcon#about to read 5, iclass 33, count 0 2006.259.07:59:30.91#ibcon#read 5, iclass 33, count 0 2006.259.07:59:30.91#ibcon#about to read 6, iclass 33, count 0 2006.259.07:59:30.91#ibcon#read 6, iclass 33, count 0 2006.259.07:59:30.91#ibcon#end of sib2, iclass 33, count 0 2006.259.07:59:30.91#ibcon#*after write, iclass 33, count 0 2006.259.07:59:30.91#ibcon#*before return 0, iclass 33, count 0 2006.259.07:59:30.91#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.259.07:59:30.91#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.259.07:59:30.91#ibcon#about to clear, iclass 33 cls_cnt 0 2006.259.07:59:30.91#ibcon#cleared, iclass 33 cls_cnt 0 2006.259.07:59:30.91$vc4f8/va=7,6 2006.259.07:59:30.91#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.259.07:59:30.91#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.259.07:59:30.91#ibcon#ireg 11 cls_cnt 2 2006.259.07:59:30.91#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.259.07:59:30.97#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.259.07:59:30.97#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.259.07:59:30.97#ibcon#enter wrdev, iclass 35, count 2 2006.259.07:59:30.97#ibcon#first serial, iclass 35, count 2 2006.259.07:59:30.97#ibcon#enter sib2, iclass 35, count 2 2006.259.07:59:30.97#ibcon#flushed, iclass 35, count 2 2006.259.07:59:30.97#ibcon#about to write, iclass 35, count 2 2006.259.07:59:30.97#ibcon#wrote, iclass 35, count 2 2006.259.07:59:30.97#ibcon#about to read 3, iclass 35, count 2 2006.259.07:59:30.99#ibcon#read 3, iclass 35, count 2 2006.259.07:59:30.99#ibcon#about to read 4, iclass 35, count 2 2006.259.07:59:30.99#ibcon#read 4, iclass 35, count 2 2006.259.07:59:30.99#ibcon#about to read 5, iclass 35, count 2 2006.259.07:59:30.99#ibcon#read 5, iclass 35, count 2 2006.259.07:59:30.99#ibcon#about to read 6, iclass 35, count 2 2006.259.07:59:30.99#ibcon#read 6, iclass 35, count 2 2006.259.07:59:30.99#ibcon#end of sib2, iclass 35, count 2 2006.259.07:59:30.99#ibcon#*mode == 0, iclass 35, count 2 2006.259.07:59:30.99#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.259.07:59:30.99#ibcon#[25=AT07-06\r\n] 2006.259.07:59:30.99#ibcon#*before write, iclass 35, count 2 2006.259.07:59:30.99#ibcon#enter sib2, iclass 35, count 2 2006.259.07:59:30.99#ibcon#flushed, iclass 35, count 2 2006.259.07:59:30.99#ibcon#about to write, iclass 35, count 2 2006.259.07:59:30.99#ibcon#wrote, iclass 35, count 2 2006.259.07:59:30.99#ibcon#about to read 3, iclass 35, count 2 2006.259.07:59:31.02#ibcon#read 3, iclass 35, count 2 2006.259.07:59:31.02#ibcon#about to read 4, iclass 35, count 2 2006.259.07:59:31.02#ibcon#read 4, iclass 35, count 2 2006.259.07:59:31.02#ibcon#about to read 5, iclass 35, count 2 2006.259.07:59:31.02#ibcon#read 5, iclass 35, count 2 2006.259.07:59:31.02#ibcon#about to read 6, iclass 35, count 2 2006.259.07:59:31.02#ibcon#read 6, iclass 35, count 2 2006.259.07:59:31.02#ibcon#end of sib2, iclass 35, count 2 2006.259.07:59:31.02#ibcon#*after write, iclass 35, count 2 2006.259.07:59:31.02#ibcon#*before return 0, iclass 35, count 2 2006.259.07:59:31.02#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.259.07:59:31.02#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.259.07:59:31.02#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.259.07:59:31.02#ibcon#ireg 7 cls_cnt 0 2006.259.07:59:31.02#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.259.07:59:31.14#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.259.07:59:31.14#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.259.07:59:31.14#ibcon#enter wrdev, iclass 35, count 0 2006.259.07:59:31.14#ibcon#first serial, iclass 35, count 0 2006.259.07:59:31.14#ibcon#enter sib2, iclass 35, count 0 2006.259.07:59:31.14#ibcon#flushed, iclass 35, count 0 2006.259.07:59:31.14#ibcon#about to write, iclass 35, count 0 2006.259.07:59:31.14#ibcon#wrote, iclass 35, count 0 2006.259.07:59:31.14#ibcon#about to read 3, iclass 35, count 0 2006.259.07:59:31.16#ibcon#read 3, iclass 35, count 0 2006.259.07:59:31.16#ibcon#about to read 4, iclass 35, count 0 2006.259.07:59:31.16#ibcon#read 4, iclass 35, count 0 2006.259.07:59:31.16#ibcon#about to read 5, iclass 35, count 0 2006.259.07:59:31.16#ibcon#read 5, iclass 35, count 0 2006.259.07:59:31.16#ibcon#about to read 6, iclass 35, count 0 2006.259.07:59:31.16#ibcon#read 6, iclass 35, count 0 2006.259.07:59:31.16#ibcon#end of sib2, iclass 35, count 0 2006.259.07:59:31.16#ibcon#*mode == 0, iclass 35, count 0 2006.259.07:59:31.16#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.259.07:59:31.16#ibcon#[25=USB\r\n] 2006.259.07:59:31.16#ibcon#*before write, iclass 35, count 0 2006.259.07:59:31.16#ibcon#enter sib2, iclass 35, count 0 2006.259.07:59:31.16#ibcon#flushed, iclass 35, count 0 2006.259.07:59:31.16#ibcon#about to write, iclass 35, count 0 2006.259.07:59:31.16#ibcon#wrote, iclass 35, count 0 2006.259.07:59:31.16#ibcon#about to read 3, iclass 35, count 0 2006.259.07:59:31.19#ibcon#read 3, iclass 35, count 0 2006.259.07:59:31.19#ibcon#about to read 4, iclass 35, count 0 2006.259.07:59:31.19#ibcon#read 4, iclass 35, count 0 2006.259.07:59:31.19#ibcon#about to read 5, iclass 35, count 0 2006.259.07:59:31.19#ibcon#read 5, iclass 35, count 0 2006.259.07:59:31.19#ibcon#about to read 6, iclass 35, count 0 2006.259.07:59:31.19#ibcon#read 6, iclass 35, count 0 2006.259.07:59:31.19#ibcon#end of sib2, iclass 35, count 0 2006.259.07:59:31.19#ibcon#*after write, iclass 35, count 0 2006.259.07:59:31.19#ibcon#*before return 0, iclass 35, count 0 2006.259.07:59:31.19#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.259.07:59:31.19#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.259.07:59:31.19#ibcon#about to clear, iclass 35 cls_cnt 0 2006.259.07:59:31.19#ibcon#cleared, iclass 35 cls_cnt 0 2006.259.07:59:31.19$vc4f8/valo=8,852.99 2006.259.07:59:31.19#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.259.07:59:31.19#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.259.07:59:31.19#ibcon#ireg 17 cls_cnt 0 2006.259.07:59:31.19#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.259.07:59:31.19#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.259.07:59:31.19#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.259.07:59:31.19#ibcon#enter wrdev, iclass 37, count 0 2006.259.07:59:31.19#ibcon#first serial, iclass 37, count 0 2006.259.07:59:31.19#ibcon#enter sib2, iclass 37, count 0 2006.259.07:59:31.19#ibcon#flushed, iclass 37, count 0 2006.259.07:59:31.19#ibcon#about to write, iclass 37, count 0 2006.259.07:59:31.19#ibcon#wrote, iclass 37, count 0 2006.259.07:59:31.19#ibcon#about to read 3, iclass 37, count 0 2006.259.07:59:31.21#ibcon#read 3, iclass 37, count 0 2006.259.07:59:31.21#ibcon#about to read 4, iclass 37, count 0 2006.259.07:59:31.21#ibcon#read 4, iclass 37, count 0 2006.259.07:59:31.21#ibcon#about to read 5, iclass 37, count 0 2006.259.07:59:31.21#ibcon#read 5, iclass 37, count 0 2006.259.07:59:31.21#ibcon#about to read 6, iclass 37, count 0 2006.259.07:59:31.21#ibcon#read 6, iclass 37, count 0 2006.259.07:59:31.21#ibcon#end of sib2, iclass 37, count 0 2006.259.07:59:31.21#ibcon#*mode == 0, iclass 37, count 0 2006.259.07:59:31.21#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.259.07:59:31.21#ibcon#[26=FRQ=08,852.99\r\n] 2006.259.07:59:31.21#ibcon#*before write, iclass 37, count 0 2006.259.07:59:31.21#ibcon#enter sib2, iclass 37, count 0 2006.259.07:59:31.21#ibcon#flushed, iclass 37, count 0 2006.259.07:59:31.21#ibcon#about to write, iclass 37, count 0 2006.259.07:59:31.21#ibcon#wrote, iclass 37, count 0 2006.259.07:59:31.21#ibcon#about to read 3, iclass 37, count 0 2006.259.07:59:31.25#ibcon#read 3, iclass 37, count 0 2006.259.07:59:31.25#ibcon#about to read 4, iclass 37, count 0 2006.259.07:59:31.25#ibcon#read 4, iclass 37, count 0 2006.259.07:59:31.25#ibcon#about to read 5, iclass 37, count 0 2006.259.07:59:31.25#ibcon#read 5, iclass 37, count 0 2006.259.07:59:31.25#ibcon#about to read 6, iclass 37, count 0 2006.259.07:59:31.25#ibcon#read 6, iclass 37, count 0 2006.259.07:59:31.25#ibcon#end of sib2, iclass 37, count 0 2006.259.07:59:31.25#ibcon#*after write, iclass 37, count 0 2006.259.07:59:31.25#ibcon#*before return 0, iclass 37, count 0 2006.259.07:59:31.25#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.259.07:59:31.25#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.259.07:59:31.25#ibcon#about to clear, iclass 37 cls_cnt 0 2006.259.07:59:31.25#ibcon#cleared, iclass 37 cls_cnt 0 2006.259.07:59:31.25$vc4f8/va=8,6 2006.259.07:59:31.25#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.259.07:59:31.25#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.259.07:59:31.25#ibcon#ireg 11 cls_cnt 2 2006.259.07:59:31.25#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.259.07:59:31.31#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.259.07:59:31.31#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.259.07:59:31.31#ibcon#enter wrdev, iclass 39, count 2 2006.259.07:59:31.31#ibcon#first serial, iclass 39, count 2 2006.259.07:59:31.31#ibcon#enter sib2, iclass 39, count 2 2006.259.07:59:31.31#ibcon#flushed, iclass 39, count 2 2006.259.07:59:31.31#ibcon#about to write, iclass 39, count 2 2006.259.07:59:31.31#ibcon#wrote, iclass 39, count 2 2006.259.07:59:31.31#ibcon#about to read 3, iclass 39, count 2 2006.259.07:59:31.33#ibcon#read 3, iclass 39, count 2 2006.259.07:59:31.33#ibcon#about to read 4, iclass 39, count 2 2006.259.07:59:31.33#ibcon#read 4, iclass 39, count 2 2006.259.07:59:31.33#ibcon#about to read 5, iclass 39, count 2 2006.259.07:59:31.33#ibcon#read 5, iclass 39, count 2 2006.259.07:59:31.33#ibcon#about to read 6, iclass 39, count 2 2006.259.07:59:31.33#ibcon#read 6, iclass 39, count 2 2006.259.07:59:31.33#ibcon#end of sib2, iclass 39, count 2 2006.259.07:59:31.33#ibcon#*mode == 0, iclass 39, count 2 2006.259.07:59:31.33#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.259.07:59:31.33#ibcon#[25=AT08-06\r\n] 2006.259.07:59:31.33#ibcon#*before write, iclass 39, count 2 2006.259.07:59:31.33#ibcon#enter sib2, iclass 39, count 2 2006.259.07:59:31.33#ibcon#flushed, iclass 39, count 2 2006.259.07:59:31.33#ibcon#about to write, iclass 39, count 2 2006.259.07:59:31.33#ibcon#wrote, iclass 39, count 2 2006.259.07:59:31.33#ibcon#about to read 3, iclass 39, count 2 2006.259.07:59:31.36#ibcon#read 3, iclass 39, count 2 2006.259.07:59:31.36#ibcon#about to read 4, iclass 39, count 2 2006.259.07:59:31.36#ibcon#read 4, iclass 39, count 2 2006.259.07:59:31.36#ibcon#about to read 5, iclass 39, count 2 2006.259.07:59:31.36#ibcon#read 5, iclass 39, count 2 2006.259.07:59:31.36#ibcon#about to read 6, iclass 39, count 2 2006.259.07:59:31.36#ibcon#read 6, iclass 39, count 2 2006.259.07:59:31.36#ibcon#end of sib2, iclass 39, count 2 2006.259.07:59:31.36#ibcon#*after write, iclass 39, count 2 2006.259.07:59:31.36#ibcon#*before return 0, iclass 39, count 2 2006.259.07:59:31.36#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.259.07:59:31.36#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.259.07:59:31.36#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.259.07:59:31.36#ibcon#ireg 7 cls_cnt 0 2006.259.07:59:31.36#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.259.07:59:31.48#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.259.07:59:31.48#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.259.07:59:31.48#ibcon#enter wrdev, iclass 39, count 0 2006.259.07:59:31.48#ibcon#first serial, iclass 39, count 0 2006.259.07:59:31.48#ibcon#enter sib2, iclass 39, count 0 2006.259.07:59:31.48#ibcon#flushed, iclass 39, count 0 2006.259.07:59:31.48#ibcon#about to write, iclass 39, count 0 2006.259.07:59:31.48#ibcon#wrote, iclass 39, count 0 2006.259.07:59:31.48#ibcon#about to read 3, iclass 39, count 0 2006.259.07:59:31.50#ibcon#read 3, iclass 39, count 0 2006.259.07:59:31.50#ibcon#about to read 4, iclass 39, count 0 2006.259.07:59:31.50#ibcon#read 4, iclass 39, count 0 2006.259.07:59:31.50#ibcon#about to read 5, iclass 39, count 0 2006.259.07:59:31.50#ibcon#read 5, iclass 39, count 0 2006.259.07:59:31.50#ibcon#about to read 6, iclass 39, count 0 2006.259.07:59:31.50#ibcon#read 6, iclass 39, count 0 2006.259.07:59:31.50#ibcon#end of sib2, iclass 39, count 0 2006.259.07:59:31.50#ibcon#*mode == 0, iclass 39, count 0 2006.259.07:59:31.50#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.259.07:59:31.50#ibcon#[25=USB\r\n] 2006.259.07:59:31.50#ibcon#*before write, iclass 39, count 0 2006.259.07:59:31.50#ibcon#enter sib2, iclass 39, count 0 2006.259.07:59:31.50#ibcon#flushed, iclass 39, count 0 2006.259.07:59:31.50#ibcon#about to write, iclass 39, count 0 2006.259.07:59:31.50#ibcon#wrote, iclass 39, count 0 2006.259.07:59:31.50#ibcon#about to read 3, iclass 39, count 0 2006.259.07:59:31.53#ibcon#read 3, iclass 39, count 0 2006.259.07:59:31.53#ibcon#about to read 4, iclass 39, count 0 2006.259.07:59:31.53#ibcon#read 4, iclass 39, count 0 2006.259.07:59:31.53#ibcon#about to read 5, iclass 39, count 0 2006.259.07:59:31.53#ibcon#read 5, iclass 39, count 0 2006.259.07:59:31.53#ibcon#about to read 6, iclass 39, count 0 2006.259.07:59:31.53#ibcon#read 6, iclass 39, count 0 2006.259.07:59:31.53#ibcon#end of sib2, iclass 39, count 0 2006.259.07:59:31.53#ibcon#*after write, iclass 39, count 0 2006.259.07:59:31.53#ibcon#*before return 0, iclass 39, count 0 2006.259.07:59:31.53#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.259.07:59:31.53#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.259.07:59:31.53#ibcon#about to clear, iclass 39 cls_cnt 0 2006.259.07:59:31.53#ibcon#cleared, iclass 39 cls_cnt 0 2006.259.07:59:31.53$vc4f8/vblo=1,632.99 2006.259.07:59:31.53#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.259.07:59:31.53#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.259.07:59:31.53#ibcon#ireg 17 cls_cnt 0 2006.259.07:59:31.53#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.259.07:59:31.53#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.259.07:59:31.53#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.259.07:59:31.53#ibcon#enter wrdev, iclass 3, count 0 2006.259.07:59:31.53#ibcon#first serial, iclass 3, count 0 2006.259.07:59:31.53#ibcon#enter sib2, iclass 3, count 0 2006.259.07:59:31.53#ibcon#flushed, iclass 3, count 0 2006.259.07:59:31.53#ibcon#about to write, iclass 3, count 0 2006.259.07:59:31.53#ibcon#wrote, iclass 3, count 0 2006.259.07:59:31.53#ibcon#about to read 3, iclass 3, count 0 2006.259.07:59:31.55#ibcon#read 3, iclass 3, count 0 2006.259.07:59:31.55#ibcon#about to read 4, iclass 3, count 0 2006.259.07:59:31.55#ibcon#read 4, iclass 3, count 0 2006.259.07:59:31.55#ibcon#about to read 5, iclass 3, count 0 2006.259.07:59:31.55#ibcon#read 5, iclass 3, count 0 2006.259.07:59:31.55#ibcon#about to read 6, iclass 3, count 0 2006.259.07:59:31.55#ibcon#read 6, iclass 3, count 0 2006.259.07:59:31.55#ibcon#end of sib2, iclass 3, count 0 2006.259.07:59:31.55#ibcon#*mode == 0, iclass 3, count 0 2006.259.07:59:31.55#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.259.07:59:31.55#ibcon#[28=FRQ=01,632.99\r\n] 2006.259.07:59:31.55#ibcon#*before write, iclass 3, count 0 2006.259.07:59:31.55#ibcon#enter sib2, iclass 3, count 0 2006.259.07:59:31.55#ibcon#flushed, iclass 3, count 0 2006.259.07:59:31.55#ibcon#about to write, iclass 3, count 0 2006.259.07:59:31.55#ibcon#wrote, iclass 3, count 0 2006.259.07:59:31.55#ibcon#about to read 3, iclass 3, count 0 2006.259.07:59:31.59#ibcon#read 3, iclass 3, count 0 2006.259.07:59:31.59#ibcon#about to read 4, iclass 3, count 0 2006.259.07:59:31.59#ibcon#read 4, iclass 3, count 0 2006.259.07:59:31.59#ibcon#about to read 5, iclass 3, count 0 2006.259.07:59:31.59#ibcon#read 5, iclass 3, count 0 2006.259.07:59:31.59#ibcon#about to read 6, iclass 3, count 0 2006.259.07:59:31.59#ibcon#read 6, iclass 3, count 0 2006.259.07:59:31.59#ibcon#end of sib2, iclass 3, count 0 2006.259.07:59:31.59#ibcon#*after write, iclass 3, count 0 2006.259.07:59:31.59#ibcon#*before return 0, iclass 3, count 0 2006.259.07:59:31.59#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.259.07:59:31.59#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.259.07:59:31.59#ibcon#about to clear, iclass 3 cls_cnt 0 2006.259.07:59:31.59#ibcon#cleared, iclass 3 cls_cnt 0 2006.259.07:59:31.59$vc4f8/vb=1,4 2006.259.07:59:31.59#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.259.07:59:31.59#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.259.07:59:31.59#ibcon#ireg 11 cls_cnt 2 2006.259.07:59:31.59#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.259.07:59:31.59#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.259.07:59:31.59#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.259.07:59:31.59#ibcon#enter wrdev, iclass 5, count 2 2006.259.07:59:31.59#ibcon#first serial, iclass 5, count 2 2006.259.07:59:31.59#ibcon#enter sib2, iclass 5, count 2 2006.259.07:59:31.59#ibcon#flushed, iclass 5, count 2 2006.259.07:59:31.59#ibcon#about to write, iclass 5, count 2 2006.259.07:59:31.59#ibcon#wrote, iclass 5, count 2 2006.259.07:59:31.59#ibcon#about to read 3, iclass 5, count 2 2006.259.07:59:31.61#ibcon#read 3, iclass 5, count 2 2006.259.07:59:31.61#ibcon#about to read 4, iclass 5, count 2 2006.259.07:59:31.61#ibcon#read 4, iclass 5, count 2 2006.259.07:59:31.61#ibcon#about to read 5, iclass 5, count 2 2006.259.07:59:31.61#ibcon#read 5, iclass 5, count 2 2006.259.07:59:31.61#ibcon#about to read 6, iclass 5, count 2 2006.259.07:59:31.61#ibcon#read 6, iclass 5, count 2 2006.259.07:59:31.61#ibcon#end of sib2, iclass 5, count 2 2006.259.07:59:31.61#ibcon#*mode == 0, iclass 5, count 2 2006.259.07:59:31.61#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.259.07:59:31.61#ibcon#[27=AT01-04\r\n] 2006.259.07:59:31.61#ibcon#*before write, iclass 5, count 2 2006.259.07:59:31.61#ibcon#enter sib2, iclass 5, count 2 2006.259.07:59:31.61#ibcon#flushed, iclass 5, count 2 2006.259.07:59:31.61#ibcon#about to write, iclass 5, count 2 2006.259.07:59:31.61#ibcon#wrote, iclass 5, count 2 2006.259.07:59:31.61#ibcon#about to read 3, iclass 5, count 2 2006.259.07:59:31.64#ibcon#read 3, iclass 5, count 2 2006.259.07:59:31.64#ibcon#about to read 4, iclass 5, count 2 2006.259.07:59:31.64#ibcon#read 4, iclass 5, count 2 2006.259.07:59:31.64#ibcon#about to read 5, iclass 5, count 2 2006.259.07:59:31.64#ibcon#read 5, iclass 5, count 2 2006.259.07:59:31.64#ibcon#about to read 6, iclass 5, count 2 2006.259.07:59:31.64#ibcon#read 6, iclass 5, count 2 2006.259.07:59:31.64#ibcon#end of sib2, iclass 5, count 2 2006.259.07:59:31.64#ibcon#*after write, iclass 5, count 2 2006.259.07:59:31.64#ibcon#*before return 0, iclass 5, count 2 2006.259.07:59:31.64#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.259.07:59:31.64#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.259.07:59:31.64#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.259.07:59:31.64#ibcon#ireg 7 cls_cnt 0 2006.259.07:59:31.64#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.259.07:59:31.76#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.259.07:59:31.76#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.259.07:59:31.76#ibcon#enter wrdev, iclass 5, count 0 2006.259.07:59:31.76#ibcon#first serial, iclass 5, count 0 2006.259.07:59:31.76#ibcon#enter sib2, iclass 5, count 0 2006.259.07:59:31.76#ibcon#flushed, iclass 5, count 0 2006.259.07:59:31.76#ibcon#about to write, iclass 5, count 0 2006.259.07:59:31.76#ibcon#wrote, iclass 5, count 0 2006.259.07:59:31.76#ibcon#about to read 3, iclass 5, count 0 2006.259.07:59:31.78#ibcon#read 3, iclass 5, count 0 2006.259.07:59:31.78#ibcon#about to read 4, iclass 5, count 0 2006.259.07:59:31.78#ibcon#read 4, iclass 5, count 0 2006.259.07:59:31.78#ibcon#about to read 5, iclass 5, count 0 2006.259.07:59:31.78#ibcon#read 5, iclass 5, count 0 2006.259.07:59:31.78#ibcon#about to read 6, iclass 5, count 0 2006.259.07:59:31.78#ibcon#read 6, iclass 5, count 0 2006.259.07:59:31.78#ibcon#end of sib2, iclass 5, count 0 2006.259.07:59:31.78#ibcon#*mode == 0, iclass 5, count 0 2006.259.07:59:31.78#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.259.07:59:31.78#ibcon#[27=USB\r\n] 2006.259.07:59:31.78#ibcon#*before write, iclass 5, count 0 2006.259.07:59:31.78#ibcon#enter sib2, iclass 5, count 0 2006.259.07:59:31.78#ibcon#flushed, iclass 5, count 0 2006.259.07:59:31.78#ibcon#about to write, iclass 5, count 0 2006.259.07:59:31.78#ibcon#wrote, iclass 5, count 0 2006.259.07:59:31.78#ibcon#about to read 3, iclass 5, count 0 2006.259.07:59:31.81#ibcon#read 3, iclass 5, count 0 2006.259.07:59:31.81#ibcon#about to read 4, iclass 5, count 0 2006.259.07:59:31.81#ibcon#read 4, iclass 5, count 0 2006.259.07:59:31.81#ibcon#about to read 5, iclass 5, count 0 2006.259.07:59:31.81#ibcon#read 5, iclass 5, count 0 2006.259.07:59:31.81#ibcon#about to read 6, iclass 5, count 0 2006.259.07:59:31.81#ibcon#read 6, iclass 5, count 0 2006.259.07:59:31.81#ibcon#end of sib2, iclass 5, count 0 2006.259.07:59:31.81#ibcon#*after write, iclass 5, count 0 2006.259.07:59:31.81#ibcon#*before return 0, iclass 5, count 0 2006.259.07:59:31.81#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.259.07:59:31.81#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.259.07:59:31.81#ibcon#about to clear, iclass 5 cls_cnt 0 2006.259.07:59:31.81#ibcon#cleared, iclass 5 cls_cnt 0 2006.259.07:59:31.81$vc4f8/vblo=2,640.99 2006.259.07:59:31.81#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.259.07:59:31.81#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.259.07:59:31.81#ibcon#ireg 17 cls_cnt 0 2006.259.07:59:31.81#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.259.07:59:31.81#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.259.07:59:31.81#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.259.07:59:31.81#ibcon#enter wrdev, iclass 7, count 0 2006.259.07:59:31.81#ibcon#first serial, iclass 7, count 0 2006.259.07:59:31.81#ibcon#enter sib2, iclass 7, count 0 2006.259.07:59:31.81#ibcon#flushed, iclass 7, count 0 2006.259.07:59:31.81#ibcon#about to write, iclass 7, count 0 2006.259.07:59:31.81#ibcon#wrote, iclass 7, count 0 2006.259.07:59:31.81#ibcon#about to read 3, iclass 7, count 0 2006.259.07:59:31.83#ibcon#read 3, iclass 7, count 0 2006.259.07:59:31.83#ibcon#about to read 4, iclass 7, count 0 2006.259.07:59:31.83#ibcon#read 4, iclass 7, count 0 2006.259.07:59:31.83#ibcon#about to read 5, iclass 7, count 0 2006.259.07:59:31.83#ibcon#read 5, iclass 7, count 0 2006.259.07:59:31.83#ibcon#about to read 6, iclass 7, count 0 2006.259.07:59:31.83#ibcon#read 6, iclass 7, count 0 2006.259.07:59:31.83#ibcon#end of sib2, iclass 7, count 0 2006.259.07:59:31.83#ibcon#*mode == 0, iclass 7, count 0 2006.259.07:59:31.83#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.259.07:59:31.83#ibcon#[28=FRQ=02,640.99\r\n] 2006.259.07:59:31.83#ibcon#*before write, iclass 7, count 0 2006.259.07:59:31.83#ibcon#enter sib2, iclass 7, count 0 2006.259.07:59:31.83#ibcon#flushed, iclass 7, count 0 2006.259.07:59:31.83#ibcon#about to write, iclass 7, count 0 2006.259.07:59:31.83#ibcon#wrote, iclass 7, count 0 2006.259.07:59:31.83#ibcon#about to read 3, iclass 7, count 0 2006.259.07:59:31.87#ibcon#read 3, iclass 7, count 0 2006.259.07:59:31.87#ibcon#about to read 4, iclass 7, count 0 2006.259.07:59:31.87#ibcon#read 4, iclass 7, count 0 2006.259.07:59:31.87#ibcon#about to read 5, iclass 7, count 0 2006.259.07:59:31.87#ibcon#read 5, iclass 7, count 0 2006.259.07:59:31.87#ibcon#about to read 6, iclass 7, count 0 2006.259.07:59:31.87#ibcon#read 6, iclass 7, count 0 2006.259.07:59:31.87#ibcon#end of sib2, iclass 7, count 0 2006.259.07:59:31.87#ibcon#*after write, iclass 7, count 0 2006.259.07:59:31.87#ibcon#*before return 0, iclass 7, count 0 2006.259.07:59:31.87#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.259.07:59:31.87#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.259.07:59:31.87#ibcon#about to clear, iclass 7 cls_cnt 0 2006.259.07:59:31.87#ibcon#cleared, iclass 7 cls_cnt 0 2006.259.07:59:31.87$vc4f8/vb=2,5 2006.259.07:59:31.87#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.259.07:59:31.87#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.259.07:59:31.87#ibcon#ireg 11 cls_cnt 2 2006.259.07:59:31.87#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.259.07:59:31.93#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.259.07:59:31.93#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.259.07:59:31.93#ibcon#enter wrdev, iclass 11, count 2 2006.259.07:59:31.93#ibcon#first serial, iclass 11, count 2 2006.259.07:59:31.93#ibcon#enter sib2, iclass 11, count 2 2006.259.07:59:31.93#ibcon#flushed, iclass 11, count 2 2006.259.07:59:31.93#ibcon#about to write, iclass 11, count 2 2006.259.07:59:31.93#ibcon#wrote, iclass 11, count 2 2006.259.07:59:31.93#ibcon#about to read 3, iclass 11, count 2 2006.259.07:59:31.95#ibcon#read 3, iclass 11, count 2 2006.259.07:59:31.95#ibcon#about to read 4, iclass 11, count 2 2006.259.07:59:31.95#ibcon#read 4, iclass 11, count 2 2006.259.07:59:31.95#ibcon#about to read 5, iclass 11, count 2 2006.259.07:59:31.95#ibcon#read 5, iclass 11, count 2 2006.259.07:59:31.95#ibcon#about to read 6, iclass 11, count 2 2006.259.07:59:31.95#ibcon#read 6, iclass 11, count 2 2006.259.07:59:31.95#ibcon#end of sib2, iclass 11, count 2 2006.259.07:59:31.95#ibcon#*mode == 0, iclass 11, count 2 2006.259.07:59:31.95#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.259.07:59:31.95#ibcon#[27=AT02-05\r\n] 2006.259.07:59:31.95#ibcon#*before write, iclass 11, count 2 2006.259.07:59:31.95#ibcon#enter sib2, iclass 11, count 2 2006.259.07:59:31.95#ibcon#flushed, iclass 11, count 2 2006.259.07:59:31.95#ibcon#about to write, iclass 11, count 2 2006.259.07:59:31.95#ibcon#wrote, iclass 11, count 2 2006.259.07:59:31.95#ibcon#about to read 3, iclass 11, count 2 2006.259.07:59:31.98#ibcon#read 3, iclass 11, count 2 2006.259.07:59:31.98#ibcon#about to read 4, iclass 11, count 2 2006.259.07:59:31.98#ibcon#read 4, iclass 11, count 2 2006.259.07:59:31.98#ibcon#about to read 5, iclass 11, count 2 2006.259.07:59:31.98#ibcon#read 5, iclass 11, count 2 2006.259.07:59:31.98#ibcon#about to read 6, iclass 11, count 2 2006.259.07:59:31.98#ibcon#read 6, iclass 11, count 2 2006.259.07:59:31.98#ibcon#end of sib2, iclass 11, count 2 2006.259.07:59:31.98#ibcon#*after write, iclass 11, count 2 2006.259.07:59:31.98#ibcon#*before return 0, iclass 11, count 2 2006.259.07:59:31.98#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.259.07:59:31.98#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.259.07:59:31.98#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.259.07:59:31.98#ibcon#ireg 7 cls_cnt 0 2006.259.07:59:31.98#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.259.07:59:32.10#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.259.07:59:32.10#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.259.07:59:32.10#ibcon#enter wrdev, iclass 11, count 0 2006.259.07:59:32.10#ibcon#first serial, iclass 11, count 0 2006.259.07:59:32.10#ibcon#enter sib2, iclass 11, count 0 2006.259.07:59:32.10#ibcon#flushed, iclass 11, count 0 2006.259.07:59:32.10#ibcon#about to write, iclass 11, count 0 2006.259.07:59:32.10#ibcon#wrote, iclass 11, count 0 2006.259.07:59:32.10#ibcon#about to read 3, iclass 11, count 0 2006.259.07:59:32.12#ibcon#read 3, iclass 11, count 0 2006.259.07:59:32.12#ibcon#about to read 4, iclass 11, count 0 2006.259.07:59:32.12#ibcon#read 4, iclass 11, count 0 2006.259.07:59:32.12#ibcon#about to read 5, iclass 11, count 0 2006.259.07:59:32.12#ibcon#read 5, iclass 11, count 0 2006.259.07:59:32.12#ibcon#about to read 6, iclass 11, count 0 2006.259.07:59:32.12#ibcon#read 6, iclass 11, count 0 2006.259.07:59:32.12#ibcon#end of sib2, iclass 11, count 0 2006.259.07:59:32.12#ibcon#*mode == 0, iclass 11, count 0 2006.259.07:59:32.12#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.259.07:59:32.12#ibcon#[27=USB\r\n] 2006.259.07:59:32.12#ibcon#*before write, iclass 11, count 0 2006.259.07:59:32.12#ibcon#enter sib2, iclass 11, count 0 2006.259.07:59:32.12#ibcon#flushed, iclass 11, count 0 2006.259.07:59:32.12#ibcon#about to write, iclass 11, count 0 2006.259.07:59:32.12#ibcon#wrote, iclass 11, count 0 2006.259.07:59:32.12#ibcon#about to read 3, iclass 11, count 0 2006.259.07:59:32.15#ibcon#read 3, iclass 11, count 0 2006.259.07:59:32.15#ibcon#about to read 4, iclass 11, count 0 2006.259.07:59:32.15#ibcon#read 4, iclass 11, count 0 2006.259.07:59:32.15#ibcon#about to read 5, iclass 11, count 0 2006.259.07:59:32.15#ibcon#read 5, iclass 11, count 0 2006.259.07:59:32.15#ibcon#about to read 6, iclass 11, count 0 2006.259.07:59:32.15#ibcon#read 6, iclass 11, count 0 2006.259.07:59:32.15#ibcon#end of sib2, iclass 11, count 0 2006.259.07:59:32.15#ibcon#*after write, iclass 11, count 0 2006.259.07:59:32.15#ibcon#*before return 0, iclass 11, count 0 2006.259.07:59:32.15#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.259.07:59:32.15#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.259.07:59:32.15#ibcon#about to clear, iclass 11 cls_cnt 0 2006.259.07:59:32.15#ibcon#cleared, iclass 11 cls_cnt 0 2006.259.07:59:32.15$vc4f8/vblo=3,656.99 2006.259.07:59:32.15#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.259.07:59:32.15#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.259.07:59:32.15#ibcon#ireg 17 cls_cnt 0 2006.259.07:59:32.15#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.259.07:59:32.15#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.259.07:59:32.15#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.259.07:59:32.15#ibcon#enter wrdev, iclass 13, count 0 2006.259.07:59:32.15#ibcon#first serial, iclass 13, count 0 2006.259.07:59:32.15#ibcon#enter sib2, iclass 13, count 0 2006.259.07:59:32.15#ibcon#flushed, iclass 13, count 0 2006.259.07:59:32.15#ibcon#about to write, iclass 13, count 0 2006.259.07:59:32.15#ibcon#wrote, iclass 13, count 0 2006.259.07:59:32.15#ibcon#about to read 3, iclass 13, count 0 2006.259.07:59:32.17#ibcon#read 3, iclass 13, count 0 2006.259.07:59:32.17#ibcon#about to read 4, iclass 13, count 0 2006.259.07:59:32.17#ibcon#read 4, iclass 13, count 0 2006.259.07:59:32.17#ibcon#about to read 5, iclass 13, count 0 2006.259.07:59:32.17#ibcon#read 5, iclass 13, count 0 2006.259.07:59:32.17#ibcon#about to read 6, iclass 13, count 0 2006.259.07:59:32.17#ibcon#read 6, iclass 13, count 0 2006.259.07:59:32.17#ibcon#end of sib2, iclass 13, count 0 2006.259.07:59:32.17#ibcon#*mode == 0, iclass 13, count 0 2006.259.07:59:32.17#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.259.07:59:32.17#ibcon#[28=FRQ=03,656.99\r\n] 2006.259.07:59:32.17#ibcon#*before write, iclass 13, count 0 2006.259.07:59:32.17#ibcon#enter sib2, iclass 13, count 0 2006.259.07:59:32.17#ibcon#flushed, iclass 13, count 0 2006.259.07:59:32.17#ibcon#about to write, iclass 13, count 0 2006.259.07:59:32.17#ibcon#wrote, iclass 13, count 0 2006.259.07:59:32.17#ibcon#about to read 3, iclass 13, count 0 2006.259.07:59:32.21#ibcon#read 3, iclass 13, count 0 2006.259.07:59:32.21#ibcon#about to read 4, iclass 13, count 0 2006.259.07:59:32.21#ibcon#read 4, iclass 13, count 0 2006.259.07:59:32.21#ibcon#about to read 5, iclass 13, count 0 2006.259.07:59:32.21#ibcon#read 5, iclass 13, count 0 2006.259.07:59:32.21#ibcon#about to read 6, iclass 13, count 0 2006.259.07:59:32.21#ibcon#read 6, iclass 13, count 0 2006.259.07:59:32.21#ibcon#end of sib2, iclass 13, count 0 2006.259.07:59:32.21#ibcon#*after write, iclass 13, count 0 2006.259.07:59:32.21#ibcon#*before return 0, iclass 13, count 0 2006.259.07:59:32.21#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.259.07:59:32.21#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.259.07:59:32.21#ibcon#about to clear, iclass 13 cls_cnt 0 2006.259.07:59:32.21#ibcon#cleared, iclass 13 cls_cnt 0 2006.259.07:59:32.21$vc4f8/vb=3,4 2006.259.07:59:32.21#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.259.07:59:32.21#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.259.07:59:32.21#ibcon#ireg 11 cls_cnt 2 2006.259.07:59:32.21#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.259.07:59:32.27#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.259.07:59:32.27#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.259.07:59:32.27#ibcon#enter wrdev, iclass 15, count 2 2006.259.07:59:32.27#ibcon#first serial, iclass 15, count 2 2006.259.07:59:32.27#ibcon#enter sib2, iclass 15, count 2 2006.259.07:59:32.27#ibcon#flushed, iclass 15, count 2 2006.259.07:59:32.27#ibcon#about to write, iclass 15, count 2 2006.259.07:59:32.27#ibcon#wrote, iclass 15, count 2 2006.259.07:59:32.27#ibcon#about to read 3, iclass 15, count 2 2006.259.07:59:32.29#ibcon#read 3, iclass 15, count 2 2006.259.07:59:32.29#ibcon#about to read 4, iclass 15, count 2 2006.259.07:59:32.29#ibcon#read 4, iclass 15, count 2 2006.259.07:59:32.29#ibcon#about to read 5, iclass 15, count 2 2006.259.07:59:32.29#ibcon#read 5, iclass 15, count 2 2006.259.07:59:32.29#ibcon#about to read 6, iclass 15, count 2 2006.259.07:59:32.29#ibcon#read 6, iclass 15, count 2 2006.259.07:59:32.29#ibcon#end of sib2, iclass 15, count 2 2006.259.07:59:32.29#ibcon#*mode == 0, iclass 15, count 2 2006.259.07:59:32.29#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.259.07:59:32.29#ibcon#[27=AT03-04\r\n] 2006.259.07:59:32.29#ibcon#*before write, iclass 15, count 2 2006.259.07:59:32.29#ibcon#enter sib2, iclass 15, count 2 2006.259.07:59:32.29#ibcon#flushed, iclass 15, count 2 2006.259.07:59:32.29#ibcon#about to write, iclass 15, count 2 2006.259.07:59:32.29#ibcon#wrote, iclass 15, count 2 2006.259.07:59:32.29#ibcon#about to read 3, iclass 15, count 2 2006.259.07:59:32.32#ibcon#read 3, iclass 15, count 2 2006.259.07:59:32.32#ibcon#about to read 4, iclass 15, count 2 2006.259.07:59:32.32#ibcon#read 4, iclass 15, count 2 2006.259.07:59:32.32#ibcon#about to read 5, iclass 15, count 2 2006.259.07:59:32.32#ibcon#read 5, iclass 15, count 2 2006.259.07:59:32.32#ibcon#about to read 6, iclass 15, count 2 2006.259.07:59:32.32#ibcon#read 6, iclass 15, count 2 2006.259.07:59:32.32#ibcon#end of sib2, iclass 15, count 2 2006.259.07:59:32.32#ibcon#*after write, iclass 15, count 2 2006.259.07:59:32.32#ibcon#*before return 0, iclass 15, count 2 2006.259.07:59:32.32#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.259.07:59:32.32#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.259.07:59:32.32#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.259.07:59:32.32#ibcon#ireg 7 cls_cnt 0 2006.259.07:59:32.32#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.259.07:59:32.44#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.259.07:59:32.44#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.259.07:59:32.44#ibcon#enter wrdev, iclass 15, count 0 2006.259.07:59:32.44#ibcon#first serial, iclass 15, count 0 2006.259.07:59:32.44#ibcon#enter sib2, iclass 15, count 0 2006.259.07:59:32.44#ibcon#flushed, iclass 15, count 0 2006.259.07:59:32.44#ibcon#about to write, iclass 15, count 0 2006.259.07:59:32.44#ibcon#wrote, iclass 15, count 0 2006.259.07:59:32.44#ibcon#about to read 3, iclass 15, count 0 2006.259.07:59:32.46#ibcon#read 3, iclass 15, count 0 2006.259.07:59:32.46#ibcon#about to read 4, iclass 15, count 0 2006.259.07:59:32.46#ibcon#read 4, iclass 15, count 0 2006.259.07:59:32.46#ibcon#about to read 5, iclass 15, count 0 2006.259.07:59:32.46#ibcon#read 5, iclass 15, count 0 2006.259.07:59:32.46#ibcon#about to read 6, iclass 15, count 0 2006.259.07:59:32.46#ibcon#read 6, iclass 15, count 0 2006.259.07:59:32.46#ibcon#end of sib2, iclass 15, count 0 2006.259.07:59:32.46#ibcon#*mode == 0, iclass 15, count 0 2006.259.07:59:32.46#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.259.07:59:32.46#ibcon#[27=USB\r\n] 2006.259.07:59:32.46#ibcon#*before write, iclass 15, count 0 2006.259.07:59:32.46#ibcon#enter sib2, iclass 15, count 0 2006.259.07:59:32.46#ibcon#flushed, iclass 15, count 0 2006.259.07:59:32.46#ibcon#about to write, iclass 15, count 0 2006.259.07:59:32.46#ibcon#wrote, iclass 15, count 0 2006.259.07:59:32.46#ibcon#about to read 3, iclass 15, count 0 2006.259.07:59:32.49#ibcon#read 3, iclass 15, count 0 2006.259.07:59:32.49#ibcon#about to read 4, iclass 15, count 0 2006.259.07:59:32.49#ibcon#read 4, iclass 15, count 0 2006.259.07:59:32.49#ibcon#about to read 5, iclass 15, count 0 2006.259.07:59:32.49#ibcon#read 5, iclass 15, count 0 2006.259.07:59:32.49#ibcon#about to read 6, iclass 15, count 0 2006.259.07:59:32.49#ibcon#read 6, iclass 15, count 0 2006.259.07:59:32.49#ibcon#end of sib2, iclass 15, count 0 2006.259.07:59:32.49#ibcon#*after write, iclass 15, count 0 2006.259.07:59:32.49#ibcon#*before return 0, iclass 15, count 0 2006.259.07:59:32.49#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.259.07:59:32.49#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.259.07:59:32.49#ibcon#about to clear, iclass 15 cls_cnt 0 2006.259.07:59:32.49#ibcon#cleared, iclass 15 cls_cnt 0 2006.259.07:59:32.49$vc4f8/vblo=4,712.99 2006.259.07:59:32.49#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.259.07:59:32.49#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.259.07:59:32.49#ibcon#ireg 17 cls_cnt 0 2006.259.07:59:32.49#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.259.07:59:32.49#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.259.07:59:32.49#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.259.07:59:32.49#ibcon#enter wrdev, iclass 17, count 0 2006.259.07:59:32.49#ibcon#first serial, iclass 17, count 0 2006.259.07:59:32.49#ibcon#enter sib2, iclass 17, count 0 2006.259.07:59:32.49#ibcon#flushed, iclass 17, count 0 2006.259.07:59:32.49#ibcon#about to write, iclass 17, count 0 2006.259.07:59:32.49#ibcon#wrote, iclass 17, count 0 2006.259.07:59:32.49#ibcon#about to read 3, iclass 17, count 0 2006.259.07:59:32.51#ibcon#read 3, iclass 17, count 0 2006.259.07:59:32.51#ibcon#about to read 4, iclass 17, count 0 2006.259.07:59:32.51#ibcon#read 4, iclass 17, count 0 2006.259.07:59:32.51#ibcon#about to read 5, iclass 17, count 0 2006.259.07:59:32.51#ibcon#read 5, iclass 17, count 0 2006.259.07:59:32.51#ibcon#about to read 6, iclass 17, count 0 2006.259.07:59:32.51#ibcon#read 6, iclass 17, count 0 2006.259.07:59:32.51#ibcon#end of sib2, iclass 17, count 0 2006.259.07:59:32.51#ibcon#*mode == 0, iclass 17, count 0 2006.259.07:59:32.51#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.259.07:59:32.51#ibcon#[28=FRQ=04,712.99\r\n] 2006.259.07:59:32.51#ibcon#*before write, iclass 17, count 0 2006.259.07:59:32.51#ibcon#enter sib2, iclass 17, count 0 2006.259.07:59:32.51#ibcon#flushed, iclass 17, count 0 2006.259.07:59:32.51#ibcon#about to write, iclass 17, count 0 2006.259.07:59:32.51#ibcon#wrote, iclass 17, count 0 2006.259.07:59:32.51#ibcon#about to read 3, iclass 17, count 0 2006.259.07:59:32.55#ibcon#read 3, iclass 17, count 0 2006.259.07:59:32.55#ibcon#about to read 4, iclass 17, count 0 2006.259.07:59:32.55#ibcon#read 4, iclass 17, count 0 2006.259.07:59:32.55#ibcon#about to read 5, iclass 17, count 0 2006.259.07:59:32.55#ibcon#read 5, iclass 17, count 0 2006.259.07:59:32.55#ibcon#about to read 6, iclass 17, count 0 2006.259.07:59:32.55#ibcon#read 6, iclass 17, count 0 2006.259.07:59:32.55#ibcon#end of sib2, iclass 17, count 0 2006.259.07:59:32.55#ibcon#*after write, iclass 17, count 0 2006.259.07:59:32.55#ibcon#*before return 0, iclass 17, count 0 2006.259.07:59:32.55#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.259.07:59:32.55#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.259.07:59:32.55#ibcon#about to clear, iclass 17 cls_cnt 0 2006.259.07:59:32.55#ibcon#cleared, iclass 17 cls_cnt 0 2006.259.07:59:32.55$vc4f8/vb=4,5 2006.259.07:59:32.55#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.259.07:59:32.55#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.259.07:59:32.55#ibcon#ireg 11 cls_cnt 2 2006.259.07:59:32.55#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.259.07:59:32.61#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.259.07:59:32.61#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.259.07:59:32.61#ibcon#enter wrdev, iclass 19, count 2 2006.259.07:59:32.61#ibcon#first serial, iclass 19, count 2 2006.259.07:59:32.61#ibcon#enter sib2, iclass 19, count 2 2006.259.07:59:32.61#ibcon#flushed, iclass 19, count 2 2006.259.07:59:32.61#ibcon#about to write, iclass 19, count 2 2006.259.07:59:32.61#ibcon#wrote, iclass 19, count 2 2006.259.07:59:32.61#ibcon#about to read 3, iclass 19, count 2 2006.259.07:59:32.63#ibcon#read 3, iclass 19, count 2 2006.259.07:59:32.63#ibcon#about to read 4, iclass 19, count 2 2006.259.07:59:32.63#ibcon#read 4, iclass 19, count 2 2006.259.07:59:32.63#ibcon#about to read 5, iclass 19, count 2 2006.259.07:59:32.63#ibcon#read 5, iclass 19, count 2 2006.259.07:59:32.63#ibcon#about to read 6, iclass 19, count 2 2006.259.07:59:32.63#ibcon#read 6, iclass 19, count 2 2006.259.07:59:32.63#ibcon#end of sib2, iclass 19, count 2 2006.259.07:59:32.63#ibcon#*mode == 0, iclass 19, count 2 2006.259.07:59:32.63#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.259.07:59:32.63#ibcon#[27=AT04-05\r\n] 2006.259.07:59:32.63#ibcon#*before write, iclass 19, count 2 2006.259.07:59:32.63#ibcon#enter sib2, iclass 19, count 2 2006.259.07:59:32.63#ibcon#flushed, iclass 19, count 2 2006.259.07:59:32.63#ibcon#about to write, iclass 19, count 2 2006.259.07:59:32.63#ibcon#wrote, iclass 19, count 2 2006.259.07:59:32.63#ibcon#about to read 3, iclass 19, count 2 2006.259.07:59:32.66#ibcon#read 3, iclass 19, count 2 2006.259.07:59:32.66#ibcon#about to read 4, iclass 19, count 2 2006.259.07:59:32.66#ibcon#read 4, iclass 19, count 2 2006.259.07:59:32.66#ibcon#about to read 5, iclass 19, count 2 2006.259.07:59:32.66#ibcon#read 5, iclass 19, count 2 2006.259.07:59:32.66#ibcon#about to read 6, iclass 19, count 2 2006.259.07:59:32.66#ibcon#read 6, iclass 19, count 2 2006.259.07:59:32.66#ibcon#end of sib2, iclass 19, count 2 2006.259.07:59:32.66#ibcon#*after write, iclass 19, count 2 2006.259.07:59:32.66#ibcon#*before return 0, iclass 19, count 2 2006.259.07:59:32.66#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.259.07:59:32.66#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.259.07:59:32.66#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.259.07:59:32.66#ibcon#ireg 7 cls_cnt 0 2006.259.07:59:32.66#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.259.07:59:32.78#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.259.07:59:32.78#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.259.07:59:32.78#ibcon#enter wrdev, iclass 19, count 0 2006.259.07:59:32.78#ibcon#first serial, iclass 19, count 0 2006.259.07:59:32.78#ibcon#enter sib2, iclass 19, count 0 2006.259.07:59:32.78#ibcon#flushed, iclass 19, count 0 2006.259.07:59:32.78#ibcon#about to write, iclass 19, count 0 2006.259.07:59:32.78#ibcon#wrote, iclass 19, count 0 2006.259.07:59:32.78#ibcon#about to read 3, iclass 19, count 0 2006.259.07:59:32.80#ibcon#read 3, iclass 19, count 0 2006.259.07:59:32.80#ibcon#about to read 4, iclass 19, count 0 2006.259.07:59:32.80#ibcon#read 4, iclass 19, count 0 2006.259.07:59:32.80#ibcon#about to read 5, iclass 19, count 0 2006.259.07:59:32.80#ibcon#read 5, iclass 19, count 0 2006.259.07:59:32.80#ibcon#about to read 6, iclass 19, count 0 2006.259.07:59:32.80#ibcon#read 6, iclass 19, count 0 2006.259.07:59:32.80#ibcon#end of sib2, iclass 19, count 0 2006.259.07:59:32.80#ibcon#*mode == 0, iclass 19, count 0 2006.259.07:59:32.80#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.259.07:59:32.80#ibcon#[27=USB\r\n] 2006.259.07:59:32.80#ibcon#*before write, iclass 19, count 0 2006.259.07:59:32.80#ibcon#enter sib2, iclass 19, count 0 2006.259.07:59:32.80#ibcon#flushed, iclass 19, count 0 2006.259.07:59:32.80#ibcon#about to write, iclass 19, count 0 2006.259.07:59:32.80#ibcon#wrote, iclass 19, count 0 2006.259.07:59:32.80#ibcon#about to read 3, iclass 19, count 0 2006.259.07:59:32.83#ibcon#read 3, iclass 19, count 0 2006.259.07:59:32.83#ibcon#about to read 4, iclass 19, count 0 2006.259.07:59:32.83#ibcon#read 4, iclass 19, count 0 2006.259.07:59:32.83#ibcon#about to read 5, iclass 19, count 0 2006.259.07:59:32.83#ibcon#read 5, iclass 19, count 0 2006.259.07:59:32.83#ibcon#about to read 6, iclass 19, count 0 2006.259.07:59:32.83#ibcon#read 6, iclass 19, count 0 2006.259.07:59:32.83#ibcon#end of sib2, iclass 19, count 0 2006.259.07:59:32.83#ibcon#*after write, iclass 19, count 0 2006.259.07:59:32.83#ibcon#*before return 0, iclass 19, count 0 2006.259.07:59:32.83#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.259.07:59:32.83#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.259.07:59:32.83#ibcon#about to clear, iclass 19 cls_cnt 0 2006.259.07:59:32.83#ibcon#cleared, iclass 19 cls_cnt 0 2006.259.07:59:32.83$vc4f8/vblo=5,744.99 2006.259.07:59:32.83#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.259.07:59:32.83#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.259.07:59:32.83#ibcon#ireg 17 cls_cnt 0 2006.259.07:59:32.83#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.259.07:59:32.83#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.259.07:59:32.83#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.259.07:59:32.83#ibcon#enter wrdev, iclass 21, count 0 2006.259.07:59:32.83#ibcon#first serial, iclass 21, count 0 2006.259.07:59:32.83#ibcon#enter sib2, iclass 21, count 0 2006.259.07:59:32.83#ibcon#flushed, iclass 21, count 0 2006.259.07:59:32.83#ibcon#about to write, iclass 21, count 0 2006.259.07:59:32.83#ibcon#wrote, iclass 21, count 0 2006.259.07:59:32.83#ibcon#about to read 3, iclass 21, count 0 2006.259.07:59:32.85#ibcon#read 3, iclass 21, count 0 2006.259.07:59:32.85#ibcon#about to read 4, iclass 21, count 0 2006.259.07:59:32.85#ibcon#read 4, iclass 21, count 0 2006.259.07:59:32.85#ibcon#about to read 5, iclass 21, count 0 2006.259.07:59:32.85#ibcon#read 5, iclass 21, count 0 2006.259.07:59:32.85#ibcon#about to read 6, iclass 21, count 0 2006.259.07:59:32.85#ibcon#read 6, iclass 21, count 0 2006.259.07:59:32.85#ibcon#end of sib2, iclass 21, count 0 2006.259.07:59:32.85#ibcon#*mode == 0, iclass 21, count 0 2006.259.07:59:32.85#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.259.07:59:32.85#ibcon#[28=FRQ=05,744.99\r\n] 2006.259.07:59:32.85#ibcon#*before write, iclass 21, count 0 2006.259.07:59:32.85#ibcon#enter sib2, iclass 21, count 0 2006.259.07:59:32.85#ibcon#flushed, iclass 21, count 0 2006.259.07:59:32.85#ibcon#about to write, iclass 21, count 0 2006.259.07:59:32.85#ibcon#wrote, iclass 21, count 0 2006.259.07:59:32.85#ibcon#about to read 3, iclass 21, count 0 2006.259.07:59:32.89#ibcon#read 3, iclass 21, count 0 2006.259.07:59:32.89#ibcon#about to read 4, iclass 21, count 0 2006.259.07:59:32.89#ibcon#read 4, iclass 21, count 0 2006.259.07:59:32.89#ibcon#about to read 5, iclass 21, count 0 2006.259.07:59:32.89#ibcon#read 5, iclass 21, count 0 2006.259.07:59:32.89#ibcon#about to read 6, iclass 21, count 0 2006.259.07:59:32.89#ibcon#read 6, iclass 21, count 0 2006.259.07:59:32.89#ibcon#end of sib2, iclass 21, count 0 2006.259.07:59:32.89#ibcon#*after write, iclass 21, count 0 2006.259.07:59:32.89#ibcon#*before return 0, iclass 21, count 0 2006.259.07:59:32.89#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.259.07:59:32.89#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.259.07:59:32.89#ibcon#about to clear, iclass 21 cls_cnt 0 2006.259.07:59:32.89#ibcon#cleared, iclass 21 cls_cnt 0 2006.259.07:59:32.89$vc4f8/vb=5,4 2006.259.07:59:32.89#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.259.07:59:32.89#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.259.07:59:32.89#ibcon#ireg 11 cls_cnt 2 2006.259.07:59:32.89#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.259.07:59:32.95#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.259.07:59:32.95#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.259.07:59:32.95#ibcon#enter wrdev, iclass 23, count 2 2006.259.07:59:32.95#ibcon#first serial, iclass 23, count 2 2006.259.07:59:32.95#ibcon#enter sib2, iclass 23, count 2 2006.259.07:59:32.95#ibcon#flushed, iclass 23, count 2 2006.259.07:59:32.95#ibcon#about to write, iclass 23, count 2 2006.259.07:59:32.95#ibcon#wrote, iclass 23, count 2 2006.259.07:59:32.95#ibcon#about to read 3, iclass 23, count 2 2006.259.07:59:32.97#ibcon#read 3, iclass 23, count 2 2006.259.07:59:32.97#ibcon#about to read 4, iclass 23, count 2 2006.259.07:59:32.97#ibcon#read 4, iclass 23, count 2 2006.259.07:59:32.97#ibcon#about to read 5, iclass 23, count 2 2006.259.07:59:32.97#ibcon#read 5, iclass 23, count 2 2006.259.07:59:32.97#ibcon#about to read 6, iclass 23, count 2 2006.259.07:59:32.97#ibcon#read 6, iclass 23, count 2 2006.259.07:59:32.97#ibcon#end of sib2, iclass 23, count 2 2006.259.07:59:32.97#ibcon#*mode == 0, iclass 23, count 2 2006.259.07:59:32.97#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.259.07:59:32.97#ibcon#[27=AT05-04\r\n] 2006.259.07:59:32.97#ibcon#*before write, iclass 23, count 2 2006.259.07:59:32.97#ibcon#enter sib2, iclass 23, count 2 2006.259.07:59:32.97#ibcon#flushed, iclass 23, count 2 2006.259.07:59:32.97#ibcon#about to write, iclass 23, count 2 2006.259.07:59:32.97#ibcon#wrote, iclass 23, count 2 2006.259.07:59:32.97#ibcon#about to read 3, iclass 23, count 2 2006.259.07:59:33.00#ibcon#read 3, iclass 23, count 2 2006.259.07:59:33.00#ibcon#about to read 4, iclass 23, count 2 2006.259.07:59:33.00#ibcon#read 4, iclass 23, count 2 2006.259.07:59:33.00#ibcon#about to read 5, iclass 23, count 2 2006.259.07:59:33.00#ibcon#read 5, iclass 23, count 2 2006.259.07:59:33.00#ibcon#about to read 6, iclass 23, count 2 2006.259.07:59:33.00#ibcon#read 6, iclass 23, count 2 2006.259.07:59:33.00#ibcon#end of sib2, iclass 23, count 2 2006.259.07:59:33.00#ibcon#*after write, iclass 23, count 2 2006.259.07:59:33.00#ibcon#*before return 0, iclass 23, count 2 2006.259.07:59:33.00#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.259.07:59:33.00#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.259.07:59:33.00#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.259.07:59:33.00#ibcon#ireg 7 cls_cnt 0 2006.259.07:59:33.00#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.259.07:59:33.12#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.259.07:59:33.12#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.259.07:59:33.12#ibcon#enter wrdev, iclass 23, count 0 2006.259.07:59:33.12#ibcon#first serial, iclass 23, count 0 2006.259.07:59:33.12#ibcon#enter sib2, iclass 23, count 0 2006.259.07:59:33.12#ibcon#flushed, iclass 23, count 0 2006.259.07:59:33.12#ibcon#about to write, iclass 23, count 0 2006.259.07:59:33.12#ibcon#wrote, iclass 23, count 0 2006.259.07:59:33.12#ibcon#about to read 3, iclass 23, count 0 2006.259.07:59:33.14#ibcon#read 3, iclass 23, count 0 2006.259.07:59:33.14#ibcon#about to read 4, iclass 23, count 0 2006.259.07:59:33.14#ibcon#read 4, iclass 23, count 0 2006.259.07:59:33.14#ibcon#about to read 5, iclass 23, count 0 2006.259.07:59:33.14#ibcon#read 5, iclass 23, count 0 2006.259.07:59:33.14#ibcon#about to read 6, iclass 23, count 0 2006.259.07:59:33.14#ibcon#read 6, iclass 23, count 0 2006.259.07:59:33.14#ibcon#end of sib2, iclass 23, count 0 2006.259.07:59:33.14#ibcon#*mode == 0, iclass 23, count 0 2006.259.07:59:33.14#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.259.07:59:33.14#ibcon#[27=USB\r\n] 2006.259.07:59:33.14#ibcon#*before write, iclass 23, count 0 2006.259.07:59:33.14#ibcon#enter sib2, iclass 23, count 0 2006.259.07:59:33.14#ibcon#flushed, iclass 23, count 0 2006.259.07:59:33.14#ibcon#about to write, iclass 23, count 0 2006.259.07:59:33.14#ibcon#wrote, iclass 23, count 0 2006.259.07:59:33.14#ibcon#about to read 3, iclass 23, count 0 2006.259.07:59:33.17#ibcon#read 3, iclass 23, count 0 2006.259.07:59:33.17#ibcon#about to read 4, iclass 23, count 0 2006.259.07:59:33.17#ibcon#read 4, iclass 23, count 0 2006.259.07:59:33.17#ibcon#about to read 5, iclass 23, count 0 2006.259.07:59:33.17#ibcon#read 5, iclass 23, count 0 2006.259.07:59:33.17#ibcon#about to read 6, iclass 23, count 0 2006.259.07:59:33.17#ibcon#read 6, iclass 23, count 0 2006.259.07:59:33.17#ibcon#end of sib2, iclass 23, count 0 2006.259.07:59:33.17#ibcon#*after write, iclass 23, count 0 2006.259.07:59:33.17#ibcon#*before return 0, iclass 23, count 0 2006.259.07:59:33.17#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.259.07:59:33.17#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.259.07:59:33.17#ibcon#about to clear, iclass 23 cls_cnt 0 2006.259.07:59:33.17#ibcon#cleared, iclass 23 cls_cnt 0 2006.259.07:59:33.17$vc4f8/vblo=6,752.99 2006.259.07:59:33.17#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.259.07:59:33.17#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.259.07:59:33.17#ibcon#ireg 17 cls_cnt 0 2006.259.07:59:33.17#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.259.07:59:33.17#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.259.07:59:33.17#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.259.07:59:33.17#ibcon#enter wrdev, iclass 25, count 0 2006.259.07:59:33.17#ibcon#first serial, iclass 25, count 0 2006.259.07:59:33.17#ibcon#enter sib2, iclass 25, count 0 2006.259.07:59:33.17#ibcon#flushed, iclass 25, count 0 2006.259.07:59:33.17#ibcon#about to write, iclass 25, count 0 2006.259.07:59:33.17#ibcon#wrote, iclass 25, count 0 2006.259.07:59:33.17#ibcon#about to read 3, iclass 25, count 0 2006.259.07:59:33.19#ibcon#read 3, iclass 25, count 0 2006.259.07:59:33.19#ibcon#about to read 4, iclass 25, count 0 2006.259.07:59:33.19#ibcon#read 4, iclass 25, count 0 2006.259.07:59:33.19#ibcon#about to read 5, iclass 25, count 0 2006.259.07:59:33.19#ibcon#read 5, iclass 25, count 0 2006.259.07:59:33.19#ibcon#about to read 6, iclass 25, count 0 2006.259.07:59:33.19#ibcon#read 6, iclass 25, count 0 2006.259.07:59:33.19#ibcon#end of sib2, iclass 25, count 0 2006.259.07:59:33.19#ibcon#*mode == 0, iclass 25, count 0 2006.259.07:59:33.19#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.259.07:59:33.19#ibcon#[28=FRQ=06,752.99\r\n] 2006.259.07:59:33.19#ibcon#*before write, iclass 25, count 0 2006.259.07:59:33.19#ibcon#enter sib2, iclass 25, count 0 2006.259.07:59:33.19#ibcon#flushed, iclass 25, count 0 2006.259.07:59:33.19#ibcon#about to write, iclass 25, count 0 2006.259.07:59:33.19#ibcon#wrote, iclass 25, count 0 2006.259.07:59:33.19#ibcon#about to read 3, iclass 25, count 0 2006.259.07:59:33.23#ibcon#read 3, iclass 25, count 0 2006.259.07:59:33.23#ibcon#about to read 4, iclass 25, count 0 2006.259.07:59:33.23#ibcon#read 4, iclass 25, count 0 2006.259.07:59:33.23#ibcon#about to read 5, iclass 25, count 0 2006.259.07:59:33.23#ibcon#read 5, iclass 25, count 0 2006.259.07:59:33.23#ibcon#about to read 6, iclass 25, count 0 2006.259.07:59:33.23#ibcon#read 6, iclass 25, count 0 2006.259.07:59:33.23#ibcon#end of sib2, iclass 25, count 0 2006.259.07:59:33.23#ibcon#*after write, iclass 25, count 0 2006.259.07:59:33.23#ibcon#*before return 0, iclass 25, count 0 2006.259.07:59:33.23#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.259.07:59:33.23#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.259.07:59:33.23#ibcon#about to clear, iclass 25 cls_cnt 0 2006.259.07:59:33.23#ibcon#cleared, iclass 25 cls_cnt 0 2006.259.07:59:33.23$vc4f8/vb=6,4 2006.259.07:59:33.23#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.259.07:59:33.23#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.259.07:59:33.23#ibcon#ireg 11 cls_cnt 2 2006.259.07:59:33.23#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.259.07:59:33.29#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.259.07:59:33.29#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.259.07:59:33.29#ibcon#enter wrdev, iclass 27, count 2 2006.259.07:59:33.29#ibcon#first serial, iclass 27, count 2 2006.259.07:59:33.29#ibcon#enter sib2, iclass 27, count 2 2006.259.07:59:33.29#ibcon#flushed, iclass 27, count 2 2006.259.07:59:33.29#ibcon#about to write, iclass 27, count 2 2006.259.07:59:33.29#ibcon#wrote, iclass 27, count 2 2006.259.07:59:33.29#ibcon#about to read 3, iclass 27, count 2 2006.259.07:59:33.31#ibcon#read 3, iclass 27, count 2 2006.259.07:59:33.31#ibcon#about to read 4, iclass 27, count 2 2006.259.07:59:33.31#ibcon#read 4, iclass 27, count 2 2006.259.07:59:33.31#ibcon#about to read 5, iclass 27, count 2 2006.259.07:59:33.31#ibcon#read 5, iclass 27, count 2 2006.259.07:59:33.31#ibcon#about to read 6, iclass 27, count 2 2006.259.07:59:33.31#ibcon#read 6, iclass 27, count 2 2006.259.07:59:33.31#ibcon#end of sib2, iclass 27, count 2 2006.259.07:59:33.31#ibcon#*mode == 0, iclass 27, count 2 2006.259.07:59:33.31#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.259.07:59:33.31#ibcon#[27=AT06-04\r\n] 2006.259.07:59:33.31#ibcon#*before write, iclass 27, count 2 2006.259.07:59:33.31#ibcon#enter sib2, iclass 27, count 2 2006.259.07:59:33.31#ibcon#flushed, iclass 27, count 2 2006.259.07:59:33.31#ibcon#about to write, iclass 27, count 2 2006.259.07:59:33.31#ibcon#wrote, iclass 27, count 2 2006.259.07:59:33.31#ibcon#about to read 3, iclass 27, count 2 2006.259.07:59:33.34#ibcon#read 3, iclass 27, count 2 2006.259.07:59:33.34#ibcon#about to read 4, iclass 27, count 2 2006.259.07:59:33.34#ibcon#read 4, iclass 27, count 2 2006.259.07:59:33.34#ibcon#about to read 5, iclass 27, count 2 2006.259.07:59:33.34#ibcon#read 5, iclass 27, count 2 2006.259.07:59:33.34#ibcon#about to read 6, iclass 27, count 2 2006.259.07:59:33.34#ibcon#read 6, iclass 27, count 2 2006.259.07:59:33.34#ibcon#end of sib2, iclass 27, count 2 2006.259.07:59:33.34#ibcon#*after write, iclass 27, count 2 2006.259.07:59:33.34#ibcon#*before return 0, iclass 27, count 2 2006.259.07:59:33.34#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.259.07:59:33.34#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.259.07:59:33.34#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.259.07:59:33.34#ibcon#ireg 7 cls_cnt 0 2006.259.07:59:33.34#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.259.07:59:33.46#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.259.07:59:33.46#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.259.07:59:33.46#ibcon#enter wrdev, iclass 27, count 0 2006.259.07:59:33.46#ibcon#first serial, iclass 27, count 0 2006.259.07:59:33.46#ibcon#enter sib2, iclass 27, count 0 2006.259.07:59:33.46#ibcon#flushed, iclass 27, count 0 2006.259.07:59:33.46#ibcon#about to write, iclass 27, count 0 2006.259.07:59:33.46#ibcon#wrote, iclass 27, count 0 2006.259.07:59:33.46#ibcon#about to read 3, iclass 27, count 0 2006.259.07:59:33.48#ibcon#read 3, iclass 27, count 0 2006.259.07:59:33.48#ibcon#about to read 4, iclass 27, count 0 2006.259.07:59:33.48#ibcon#read 4, iclass 27, count 0 2006.259.07:59:33.48#ibcon#about to read 5, iclass 27, count 0 2006.259.07:59:33.48#ibcon#read 5, iclass 27, count 0 2006.259.07:59:33.48#ibcon#about to read 6, iclass 27, count 0 2006.259.07:59:33.48#ibcon#read 6, iclass 27, count 0 2006.259.07:59:33.48#ibcon#end of sib2, iclass 27, count 0 2006.259.07:59:33.48#ibcon#*mode == 0, iclass 27, count 0 2006.259.07:59:33.48#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.259.07:59:33.48#ibcon#[27=USB\r\n] 2006.259.07:59:33.48#ibcon#*before write, iclass 27, count 0 2006.259.07:59:33.48#ibcon#enter sib2, iclass 27, count 0 2006.259.07:59:33.48#ibcon#flushed, iclass 27, count 0 2006.259.07:59:33.48#ibcon#about to write, iclass 27, count 0 2006.259.07:59:33.48#ibcon#wrote, iclass 27, count 0 2006.259.07:59:33.48#ibcon#about to read 3, iclass 27, count 0 2006.259.07:59:33.51#ibcon#read 3, iclass 27, count 0 2006.259.07:59:33.51#ibcon#about to read 4, iclass 27, count 0 2006.259.07:59:33.51#ibcon#read 4, iclass 27, count 0 2006.259.07:59:33.51#ibcon#about to read 5, iclass 27, count 0 2006.259.07:59:33.51#ibcon#read 5, iclass 27, count 0 2006.259.07:59:33.51#ibcon#about to read 6, iclass 27, count 0 2006.259.07:59:33.51#ibcon#read 6, iclass 27, count 0 2006.259.07:59:33.51#ibcon#end of sib2, iclass 27, count 0 2006.259.07:59:33.51#ibcon#*after write, iclass 27, count 0 2006.259.07:59:33.51#ibcon#*before return 0, iclass 27, count 0 2006.259.07:59:33.51#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.259.07:59:33.51#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.259.07:59:33.51#ibcon#about to clear, iclass 27 cls_cnt 0 2006.259.07:59:33.51#ibcon#cleared, iclass 27 cls_cnt 0 2006.259.07:59:33.51$vc4f8/vabw=wide 2006.259.07:59:33.51#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.259.07:59:33.51#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.259.07:59:33.51#ibcon#ireg 8 cls_cnt 0 2006.259.07:59:33.51#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.259.07:59:33.51#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.259.07:59:33.51#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.259.07:59:33.51#ibcon#enter wrdev, iclass 29, count 0 2006.259.07:59:33.51#ibcon#first serial, iclass 29, count 0 2006.259.07:59:33.51#ibcon#enter sib2, iclass 29, count 0 2006.259.07:59:33.51#ibcon#flushed, iclass 29, count 0 2006.259.07:59:33.51#ibcon#about to write, iclass 29, count 0 2006.259.07:59:33.51#ibcon#wrote, iclass 29, count 0 2006.259.07:59:33.51#ibcon#about to read 3, iclass 29, count 0 2006.259.07:59:33.53#ibcon#read 3, iclass 29, count 0 2006.259.07:59:33.53#ibcon#about to read 4, iclass 29, count 0 2006.259.07:59:33.53#ibcon#read 4, iclass 29, count 0 2006.259.07:59:33.53#ibcon#about to read 5, iclass 29, count 0 2006.259.07:59:33.53#ibcon#read 5, iclass 29, count 0 2006.259.07:59:33.53#ibcon#about to read 6, iclass 29, count 0 2006.259.07:59:33.53#ibcon#read 6, iclass 29, count 0 2006.259.07:59:33.53#ibcon#end of sib2, iclass 29, count 0 2006.259.07:59:33.53#ibcon#*mode == 0, iclass 29, count 0 2006.259.07:59:33.53#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.259.07:59:33.53#ibcon#[25=BW32\r\n] 2006.259.07:59:33.53#ibcon#*before write, iclass 29, count 0 2006.259.07:59:33.53#ibcon#enter sib2, iclass 29, count 0 2006.259.07:59:33.53#ibcon#flushed, iclass 29, count 0 2006.259.07:59:33.53#ibcon#about to write, iclass 29, count 0 2006.259.07:59:33.53#ibcon#wrote, iclass 29, count 0 2006.259.07:59:33.53#ibcon#about to read 3, iclass 29, count 0 2006.259.07:59:33.56#ibcon#read 3, iclass 29, count 0 2006.259.07:59:33.56#ibcon#about to read 4, iclass 29, count 0 2006.259.07:59:33.56#ibcon#read 4, iclass 29, count 0 2006.259.07:59:33.56#ibcon#about to read 5, iclass 29, count 0 2006.259.07:59:33.56#ibcon#read 5, iclass 29, count 0 2006.259.07:59:33.56#ibcon#about to read 6, iclass 29, count 0 2006.259.07:59:33.56#ibcon#read 6, iclass 29, count 0 2006.259.07:59:33.56#ibcon#end of sib2, iclass 29, count 0 2006.259.07:59:33.56#ibcon#*after write, iclass 29, count 0 2006.259.07:59:33.56#ibcon#*before return 0, iclass 29, count 0 2006.259.07:59:33.56#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.259.07:59:33.56#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.259.07:59:33.56#ibcon#about to clear, iclass 29 cls_cnt 0 2006.259.07:59:33.56#ibcon#cleared, iclass 29 cls_cnt 0 2006.259.07:59:33.56$vc4f8/vbbw=wide 2006.259.07:59:33.56#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.259.07:59:33.56#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.259.07:59:33.56#ibcon#ireg 8 cls_cnt 0 2006.259.07:59:33.56#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.259.07:59:33.63#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.259.07:59:33.63#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.259.07:59:33.63#ibcon#enter wrdev, iclass 31, count 0 2006.259.07:59:33.63#ibcon#first serial, iclass 31, count 0 2006.259.07:59:33.63#ibcon#enter sib2, iclass 31, count 0 2006.259.07:59:33.63#ibcon#flushed, iclass 31, count 0 2006.259.07:59:33.63#ibcon#about to write, iclass 31, count 0 2006.259.07:59:33.63#ibcon#wrote, iclass 31, count 0 2006.259.07:59:33.63#ibcon#about to read 3, iclass 31, count 0 2006.259.07:59:33.65#ibcon#read 3, iclass 31, count 0 2006.259.07:59:33.65#ibcon#about to read 4, iclass 31, count 0 2006.259.07:59:33.65#ibcon#read 4, iclass 31, count 0 2006.259.07:59:33.65#ibcon#about to read 5, iclass 31, count 0 2006.259.07:59:33.65#ibcon#read 5, iclass 31, count 0 2006.259.07:59:33.65#ibcon#about to read 6, iclass 31, count 0 2006.259.07:59:33.65#ibcon#read 6, iclass 31, count 0 2006.259.07:59:33.65#ibcon#end of sib2, iclass 31, count 0 2006.259.07:59:33.65#ibcon#*mode == 0, iclass 31, count 0 2006.259.07:59:33.65#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.259.07:59:33.65#ibcon#[27=BW32\r\n] 2006.259.07:59:33.65#ibcon#*before write, iclass 31, count 0 2006.259.07:59:33.65#ibcon#enter sib2, iclass 31, count 0 2006.259.07:59:33.65#ibcon#flushed, iclass 31, count 0 2006.259.07:59:33.65#ibcon#about to write, iclass 31, count 0 2006.259.07:59:33.65#ibcon#wrote, iclass 31, count 0 2006.259.07:59:33.65#ibcon#about to read 3, iclass 31, count 0 2006.259.07:59:33.68#ibcon#read 3, iclass 31, count 0 2006.259.07:59:33.68#ibcon#about to read 4, iclass 31, count 0 2006.259.07:59:33.68#ibcon#read 4, iclass 31, count 0 2006.259.07:59:33.68#ibcon#about to read 5, iclass 31, count 0 2006.259.07:59:33.68#ibcon#read 5, iclass 31, count 0 2006.259.07:59:33.68#ibcon#about to read 6, iclass 31, count 0 2006.259.07:59:33.68#ibcon#read 6, iclass 31, count 0 2006.259.07:59:33.68#ibcon#end of sib2, iclass 31, count 0 2006.259.07:59:33.68#ibcon#*after write, iclass 31, count 0 2006.259.07:59:33.68#ibcon#*before return 0, iclass 31, count 0 2006.259.07:59:33.68#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.259.07:59:33.68#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.259.07:59:33.68#ibcon#about to clear, iclass 31 cls_cnt 0 2006.259.07:59:33.68#ibcon#cleared, iclass 31 cls_cnt 0 2006.259.07:59:33.68$4f8m12a/ifd4f 2006.259.07:59:33.68$ifd4f/lo= 2006.259.07:59:33.68$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.259.07:59:33.68$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.259.07:59:33.68$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.259.07:59:33.68$ifd4f/patch= 2006.259.07:59:33.68$ifd4f/patch=lo1,a1,a2,a3,a4 2006.259.07:59:33.68$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.259.07:59:33.68$ifd4f/patch=lo3,a5,a6,a7,a8 2006.259.07:59:33.69$4f8m12a/"form=m,16.000,1:2 2006.259.07:59:33.69$4f8m12a/"tpicd 2006.259.07:59:33.69$4f8m12a/echo=off 2006.259.07:59:33.69$4f8m12a/xlog=off 2006.259.07:59:33.69:!2006.259.08:00:00 2006.259.07:59:41.14#trakl#Source acquired 2006.259.07:59:41.14#flagr#flagr/antenna,acquired 2006.259.08:00:00.01:preob 2006.259.08:00:01.14/onsource/TRACKING 2006.259.08:00:01.14:!2006.259.08:00:10 2006.259.08:00:10.00:data_valid=on 2006.259.08:00:10.00:midob 2006.259.08:00:10.14/onsource/TRACKING 2006.259.08:00:10.14/wx/22.13,1013.0,86 2006.259.08:00:10.24/cable/+6.4599E-03 2006.259.08:00:11.33/va/01,08,usb,yes,30,32 2006.259.08:00:11.33/va/02,07,usb,yes,30,32 2006.259.08:00:11.33/va/03,08,usb,yes,23,23 2006.259.08:00:11.33/va/04,07,usb,yes,31,34 2006.259.08:00:11.33/va/05,07,usb,yes,35,37 2006.259.08:00:11.33/va/06,06,usb,yes,34,34 2006.259.08:00:11.33/va/07,06,usb,yes,35,35 2006.259.08:00:11.33/va/08,06,usb,yes,37,36 2006.259.08:00:11.56/valo/01,532.99,yes,locked 2006.259.08:00:11.56/valo/02,572.99,yes,locked 2006.259.08:00:11.56/valo/03,672.99,yes,locked 2006.259.08:00:11.56/valo/04,832.99,yes,locked 2006.259.08:00:11.56/valo/05,652.99,yes,locked 2006.259.08:00:11.56/valo/06,772.99,yes,locked 2006.259.08:00:11.56/valo/07,832.99,yes,locked 2006.259.08:00:11.56/valo/08,852.99,yes,locked 2006.259.08:00:12.65/vb/01,04,usb,yes,30,29 2006.259.08:00:12.65/vb/02,05,usb,yes,28,29 2006.259.08:00:12.65/vb/03,04,usb,yes,28,32 2006.259.08:00:12.65/vb/04,05,usb,yes,25,26 2006.259.08:00:12.65/vb/05,04,usb,yes,27,31 2006.259.08:00:12.65/vb/06,04,usb,yes,28,31 2006.259.08:00:12.65/vb/07,04,usb,yes,30,30 2006.259.08:00:12.65/vb/08,04,usb,yes,28,31 2006.259.08:00:12.89/vblo/01,632.99,yes,locked 2006.259.08:00:12.89/vblo/02,640.99,yes,locked 2006.259.08:00:12.89/vblo/03,656.99,yes,locked 2006.259.08:00:12.89/vblo/04,712.99,yes,locked 2006.259.08:00:12.89/vblo/05,744.99,yes,locked 2006.259.08:00:12.89/vblo/06,752.99,yes,locked 2006.259.08:00:12.89/vblo/07,734.99,yes,locked 2006.259.08:00:12.89/vblo/08,744.99,yes,locked 2006.259.08:00:13.04/vabw/8 2006.259.08:00:13.19/vbbw/8 2006.259.08:00:13.28/xfe/off,on,15.5 2006.259.08:00:13.66/ifatt/23,28,28,28 2006.259.08:00:14.07/fmout-gps/S +4.60E-07 2006.259.08:00:14.11:!2006.259.08:01:10 2006.259.08:01:10.01:data_valid=off 2006.259.08:01:10.02:postob 2006.259.08:01:10.23/cable/+6.4571E-03 2006.259.08:01:10.24/wx/22.11,1013.0,86 2006.259.08:01:11.07/fmout-gps/S +4.59E-07 2006.259.08:01:11.08:scan_name=259-0802,k06259,60 2006.259.08:01:11.08:source=0718+793,072611.74,791131.0,2000.0,neutral 2006.259.08:01:12.14#flagr#flagr/antenna,new-source 2006.259.08:01:12.15:checkk5 2006.259.08:01:12.78/chk_autoobs//k5ts1/ autoobs is running! 2006.259.08:01:13.24/chk_autoobs//k5ts2/ autoobs is running! 2006.259.08:01:13.84/chk_autoobs//k5ts3/ autoobs is running! 2006.259.08:01:14.24/chk_autoobs//k5ts4/ autoobs is running! 2006.259.08:01:14.62/chk_obsdata//k5ts1/T2590800??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.259.08:01:14.99/chk_obsdata//k5ts2/T2590800??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.259.08:01:15.37/chk_obsdata//k5ts3/T2590800??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.259.08:01:15.77/chk_obsdata//k5ts4/T2590800??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.259.08:01:16.61/k5log//k5ts1_log_newline 2006.259.08:01:17.41/k5log//k5ts2_log_newline 2006.259.08:01:18.34/k5log//k5ts3_log_newline 2006.259.08:01:19.09/k5log//k5ts4_log_newline 2006.259.08:01:19.12/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.259.08:01:19.12:4f8m12a=2 2006.259.08:01:19.12$4f8m12a/echo=on 2006.259.08:01:19.12$4f8m12a/pcalon 2006.259.08:01:19.12$pcalon/"no phase cal control is implemented here 2006.259.08:01:19.12$4f8m12a/"tpicd=stop 2006.259.08:01:19.12$4f8m12a/vc4f8 2006.259.08:01:19.12$vc4f8/valo=1,532.99 2006.259.08:01:19.12#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.259.08:01:19.12#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.259.08:01:19.12#ibcon#ireg 17 cls_cnt 0 2006.259.08:01:19.12#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.259.08:01:19.12#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.259.08:01:19.12#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.259.08:01:19.12#ibcon#enter wrdev, iclass 38, count 0 2006.259.08:01:19.12#ibcon#first serial, iclass 38, count 0 2006.259.08:01:19.12#ibcon#enter sib2, iclass 38, count 0 2006.259.08:01:19.12#ibcon#flushed, iclass 38, count 0 2006.259.08:01:19.12#ibcon#about to write, iclass 38, count 0 2006.259.08:01:19.12#ibcon#wrote, iclass 38, count 0 2006.259.08:01:19.12#ibcon#about to read 3, iclass 38, count 0 2006.259.08:01:19.17#ibcon#read 3, iclass 38, count 0 2006.259.08:01:19.17#ibcon#about to read 4, iclass 38, count 0 2006.259.08:01:19.17#ibcon#read 4, iclass 38, count 0 2006.259.08:01:19.17#ibcon#about to read 5, iclass 38, count 0 2006.259.08:01:19.17#ibcon#read 5, iclass 38, count 0 2006.259.08:01:19.17#ibcon#about to read 6, iclass 38, count 0 2006.259.08:01:19.17#ibcon#read 6, iclass 38, count 0 2006.259.08:01:19.17#ibcon#end of sib2, iclass 38, count 0 2006.259.08:01:19.17#ibcon#*mode == 0, iclass 38, count 0 2006.259.08:01:19.17#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.259.08:01:19.17#ibcon#[26=FRQ=01,532.99\r\n] 2006.259.08:01:19.17#ibcon#*before write, iclass 38, count 0 2006.259.08:01:19.17#ibcon#enter sib2, iclass 38, count 0 2006.259.08:01:19.17#ibcon#flushed, iclass 38, count 0 2006.259.08:01:19.17#ibcon#about to write, iclass 38, count 0 2006.259.08:01:19.17#ibcon#wrote, iclass 38, count 0 2006.259.08:01:19.17#ibcon#about to read 3, iclass 38, count 0 2006.259.08:01:19.21#ibcon#read 3, iclass 38, count 0 2006.259.08:01:19.21#ibcon#about to read 4, iclass 38, count 0 2006.259.08:01:19.21#ibcon#read 4, iclass 38, count 0 2006.259.08:01:19.21#ibcon#about to read 5, iclass 38, count 0 2006.259.08:01:19.21#ibcon#read 5, iclass 38, count 0 2006.259.08:01:19.21#ibcon#about to read 6, iclass 38, count 0 2006.259.08:01:19.21#ibcon#read 6, iclass 38, count 0 2006.259.08:01:19.21#ibcon#end of sib2, iclass 38, count 0 2006.259.08:01:19.21#ibcon#*after write, iclass 38, count 0 2006.259.08:01:19.21#ibcon#*before return 0, iclass 38, count 0 2006.259.08:01:19.21#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.259.08:01:19.21#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.259.08:01:19.21#ibcon#about to clear, iclass 38 cls_cnt 0 2006.259.08:01:19.21#ibcon#cleared, iclass 38 cls_cnt 0 2006.259.08:01:19.21$vc4f8/va=1,8 2006.259.08:01:19.21#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.259.08:01:19.21#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.259.08:01:19.21#ibcon#ireg 11 cls_cnt 2 2006.259.08:01:19.21#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.259.08:01:19.21#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.259.08:01:19.21#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.259.08:01:19.21#ibcon#enter wrdev, iclass 40, count 2 2006.259.08:01:19.21#ibcon#first serial, iclass 40, count 2 2006.259.08:01:19.21#ibcon#enter sib2, iclass 40, count 2 2006.259.08:01:19.21#ibcon#flushed, iclass 40, count 2 2006.259.08:01:19.21#ibcon#about to write, iclass 40, count 2 2006.259.08:01:19.21#ibcon#wrote, iclass 40, count 2 2006.259.08:01:19.21#ibcon#about to read 3, iclass 40, count 2 2006.259.08:01:19.23#ibcon#read 3, iclass 40, count 2 2006.259.08:01:19.23#ibcon#about to read 4, iclass 40, count 2 2006.259.08:01:19.23#ibcon#read 4, iclass 40, count 2 2006.259.08:01:19.23#ibcon#about to read 5, iclass 40, count 2 2006.259.08:01:19.23#ibcon#read 5, iclass 40, count 2 2006.259.08:01:19.23#ibcon#about to read 6, iclass 40, count 2 2006.259.08:01:19.23#ibcon#read 6, iclass 40, count 2 2006.259.08:01:19.23#ibcon#end of sib2, iclass 40, count 2 2006.259.08:01:19.23#ibcon#*mode == 0, iclass 40, count 2 2006.259.08:01:19.23#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.259.08:01:19.23#ibcon#[25=AT01-08\r\n] 2006.259.08:01:19.23#ibcon#*before write, iclass 40, count 2 2006.259.08:01:19.23#ibcon#enter sib2, iclass 40, count 2 2006.259.08:01:19.23#ibcon#flushed, iclass 40, count 2 2006.259.08:01:19.23#ibcon#about to write, iclass 40, count 2 2006.259.08:01:19.23#ibcon#wrote, iclass 40, count 2 2006.259.08:01:19.23#ibcon#about to read 3, iclass 40, count 2 2006.259.08:01:19.26#ibcon#read 3, iclass 40, count 2 2006.259.08:01:19.26#ibcon#about to read 4, iclass 40, count 2 2006.259.08:01:19.26#ibcon#read 4, iclass 40, count 2 2006.259.08:01:19.26#ibcon#about to read 5, iclass 40, count 2 2006.259.08:01:19.26#ibcon#read 5, iclass 40, count 2 2006.259.08:01:19.26#ibcon#about to read 6, iclass 40, count 2 2006.259.08:01:19.26#ibcon#read 6, iclass 40, count 2 2006.259.08:01:19.26#ibcon#end of sib2, iclass 40, count 2 2006.259.08:01:19.26#ibcon#*after write, iclass 40, count 2 2006.259.08:01:19.26#ibcon#*before return 0, iclass 40, count 2 2006.259.08:01:19.26#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.259.08:01:19.26#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.259.08:01:19.26#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.259.08:01:19.26#ibcon#ireg 7 cls_cnt 0 2006.259.08:01:19.26#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.259.08:01:19.38#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.259.08:01:19.38#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.259.08:01:19.38#ibcon#enter wrdev, iclass 40, count 0 2006.259.08:01:19.38#ibcon#first serial, iclass 40, count 0 2006.259.08:01:19.38#ibcon#enter sib2, iclass 40, count 0 2006.259.08:01:19.38#ibcon#flushed, iclass 40, count 0 2006.259.08:01:19.38#ibcon#about to write, iclass 40, count 0 2006.259.08:01:19.38#ibcon#wrote, iclass 40, count 0 2006.259.08:01:19.38#ibcon#about to read 3, iclass 40, count 0 2006.259.08:01:19.40#ibcon#read 3, iclass 40, count 0 2006.259.08:01:19.40#ibcon#about to read 4, iclass 40, count 0 2006.259.08:01:19.40#ibcon#read 4, iclass 40, count 0 2006.259.08:01:19.40#ibcon#about to read 5, iclass 40, count 0 2006.259.08:01:19.40#ibcon#read 5, iclass 40, count 0 2006.259.08:01:19.40#ibcon#about to read 6, iclass 40, count 0 2006.259.08:01:19.40#ibcon#read 6, iclass 40, count 0 2006.259.08:01:19.40#ibcon#end of sib2, iclass 40, count 0 2006.259.08:01:19.40#ibcon#*mode == 0, iclass 40, count 0 2006.259.08:01:19.40#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.259.08:01:19.40#ibcon#[25=USB\r\n] 2006.259.08:01:19.40#ibcon#*before write, iclass 40, count 0 2006.259.08:01:19.40#ibcon#enter sib2, iclass 40, count 0 2006.259.08:01:19.40#ibcon#flushed, iclass 40, count 0 2006.259.08:01:19.40#ibcon#about to write, iclass 40, count 0 2006.259.08:01:19.40#ibcon#wrote, iclass 40, count 0 2006.259.08:01:19.40#ibcon#about to read 3, iclass 40, count 0 2006.259.08:01:19.43#ibcon#read 3, iclass 40, count 0 2006.259.08:01:19.43#ibcon#about to read 4, iclass 40, count 0 2006.259.08:01:19.43#ibcon#read 4, iclass 40, count 0 2006.259.08:01:19.43#ibcon#about to read 5, iclass 40, count 0 2006.259.08:01:19.43#ibcon#read 5, iclass 40, count 0 2006.259.08:01:19.43#ibcon#about to read 6, iclass 40, count 0 2006.259.08:01:19.43#ibcon#read 6, iclass 40, count 0 2006.259.08:01:19.43#ibcon#end of sib2, iclass 40, count 0 2006.259.08:01:19.43#ibcon#*after write, iclass 40, count 0 2006.259.08:01:19.43#ibcon#*before return 0, iclass 40, count 0 2006.259.08:01:19.43#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.259.08:01:19.43#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.259.08:01:19.43#ibcon#about to clear, iclass 40 cls_cnt 0 2006.259.08:01:19.43#ibcon#cleared, iclass 40 cls_cnt 0 2006.259.08:01:19.43$vc4f8/valo=2,572.99 2006.259.08:01:19.43#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.259.08:01:19.43#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.259.08:01:19.43#ibcon#ireg 17 cls_cnt 0 2006.259.08:01:19.43#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.259.08:01:19.43#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.259.08:01:19.43#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.259.08:01:19.43#ibcon#enter wrdev, iclass 4, count 0 2006.259.08:01:19.43#ibcon#first serial, iclass 4, count 0 2006.259.08:01:19.43#ibcon#enter sib2, iclass 4, count 0 2006.259.08:01:19.43#ibcon#flushed, iclass 4, count 0 2006.259.08:01:19.43#ibcon#about to write, iclass 4, count 0 2006.259.08:01:19.43#ibcon#wrote, iclass 4, count 0 2006.259.08:01:19.43#ibcon#about to read 3, iclass 4, count 0 2006.259.08:01:19.45#ibcon#read 3, iclass 4, count 0 2006.259.08:01:19.45#ibcon#about to read 4, iclass 4, count 0 2006.259.08:01:19.45#ibcon#read 4, iclass 4, count 0 2006.259.08:01:19.45#ibcon#about to read 5, iclass 4, count 0 2006.259.08:01:19.45#ibcon#read 5, iclass 4, count 0 2006.259.08:01:19.45#ibcon#about to read 6, iclass 4, count 0 2006.259.08:01:19.45#ibcon#read 6, iclass 4, count 0 2006.259.08:01:19.45#ibcon#end of sib2, iclass 4, count 0 2006.259.08:01:19.45#ibcon#*mode == 0, iclass 4, count 0 2006.259.08:01:19.45#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.259.08:01:19.45#ibcon#[26=FRQ=02,572.99\r\n] 2006.259.08:01:19.45#ibcon#*before write, iclass 4, count 0 2006.259.08:01:19.45#ibcon#enter sib2, iclass 4, count 0 2006.259.08:01:19.45#ibcon#flushed, iclass 4, count 0 2006.259.08:01:19.45#ibcon#about to write, iclass 4, count 0 2006.259.08:01:19.45#ibcon#wrote, iclass 4, count 0 2006.259.08:01:19.45#ibcon#about to read 3, iclass 4, count 0 2006.259.08:01:19.49#ibcon#read 3, iclass 4, count 0 2006.259.08:01:19.49#ibcon#about to read 4, iclass 4, count 0 2006.259.08:01:19.49#ibcon#read 4, iclass 4, count 0 2006.259.08:01:19.49#ibcon#about to read 5, iclass 4, count 0 2006.259.08:01:19.49#ibcon#read 5, iclass 4, count 0 2006.259.08:01:19.49#ibcon#about to read 6, iclass 4, count 0 2006.259.08:01:19.49#ibcon#read 6, iclass 4, count 0 2006.259.08:01:19.49#ibcon#end of sib2, iclass 4, count 0 2006.259.08:01:19.49#ibcon#*after write, iclass 4, count 0 2006.259.08:01:19.49#ibcon#*before return 0, iclass 4, count 0 2006.259.08:01:19.49#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.259.08:01:19.49#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.259.08:01:19.49#ibcon#about to clear, iclass 4 cls_cnt 0 2006.259.08:01:19.49#ibcon#cleared, iclass 4 cls_cnt 0 2006.259.08:01:19.49$vc4f8/va=2,7 2006.259.08:01:19.49#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.259.08:01:19.49#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.259.08:01:19.49#ibcon#ireg 11 cls_cnt 2 2006.259.08:01:19.49#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.259.08:01:19.55#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.259.08:01:19.55#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.259.08:01:19.55#ibcon#enter wrdev, iclass 6, count 2 2006.259.08:01:19.55#ibcon#first serial, iclass 6, count 2 2006.259.08:01:19.55#ibcon#enter sib2, iclass 6, count 2 2006.259.08:01:19.55#ibcon#flushed, iclass 6, count 2 2006.259.08:01:19.55#ibcon#about to write, iclass 6, count 2 2006.259.08:01:19.55#ibcon#wrote, iclass 6, count 2 2006.259.08:01:19.55#ibcon#about to read 3, iclass 6, count 2 2006.259.08:01:19.58#ibcon#read 3, iclass 6, count 2 2006.259.08:01:19.58#ibcon#about to read 4, iclass 6, count 2 2006.259.08:01:19.58#ibcon#read 4, iclass 6, count 2 2006.259.08:01:19.58#ibcon#about to read 5, iclass 6, count 2 2006.259.08:01:19.58#ibcon#read 5, iclass 6, count 2 2006.259.08:01:19.58#ibcon#about to read 6, iclass 6, count 2 2006.259.08:01:19.58#ibcon#read 6, iclass 6, count 2 2006.259.08:01:19.58#ibcon#end of sib2, iclass 6, count 2 2006.259.08:01:19.58#ibcon#*mode == 0, iclass 6, count 2 2006.259.08:01:19.58#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.259.08:01:19.58#ibcon#[25=AT02-07\r\n] 2006.259.08:01:19.58#ibcon#*before write, iclass 6, count 2 2006.259.08:01:19.58#ibcon#enter sib2, iclass 6, count 2 2006.259.08:01:19.58#ibcon#flushed, iclass 6, count 2 2006.259.08:01:19.58#ibcon#about to write, iclass 6, count 2 2006.259.08:01:19.58#ibcon#wrote, iclass 6, count 2 2006.259.08:01:19.58#ibcon#about to read 3, iclass 6, count 2 2006.259.08:01:19.61#ibcon#read 3, iclass 6, count 2 2006.259.08:01:19.61#ibcon#about to read 4, iclass 6, count 2 2006.259.08:01:19.61#ibcon#read 4, iclass 6, count 2 2006.259.08:01:19.61#ibcon#about to read 5, iclass 6, count 2 2006.259.08:01:19.61#ibcon#read 5, iclass 6, count 2 2006.259.08:01:19.61#ibcon#about to read 6, iclass 6, count 2 2006.259.08:01:19.61#ibcon#read 6, iclass 6, count 2 2006.259.08:01:19.61#ibcon#end of sib2, iclass 6, count 2 2006.259.08:01:19.61#ibcon#*after write, iclass 6, count 2 2006.259.08:01:19.61#ibcon#*before return 0, iclass 6, count 2 2006.259.08:01:19.61#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.259.08:01:19.61#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.259.08:01:19.61#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.259.08:01:19.61#ibcon#ireg 7 cls_cnt 0 2006.259.08:01:19.61#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.259.08:01:19.64#abcon#<5=/04 2.7 4.4 22.11 861013.0\r\n> 2006.259.08:01:19.67#abcon#{5=INTERFACE CLEAR} 2006.259.08:01:19.72#abcon#[5=S1D000X0/0*\r\n] 2006.259.08:01:19.73#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.259.08:01:19.73#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.259.08:01:19.73#ibcon#enter wrdev, iclass 6, count 0 2006.259.08:01:19.73#ibcon#first serial, iclass 6, count 0 2006.259.08:01:19.73#ibcon#enter sib2, iclass 6, count 0 2006.259.08:01:19.73#ibcon#flushed, iclass 6, count 0 2006.259.08:01:19.73#ibcon#about to write, iclass 6, count 0 2006.259.08:01:19.73#ibcon#wrote, iclass 6, count 0 2006.259.08:01:19.73#ibcon#about to read 3, iclass 6, count 0 2006.259.08:01:19.77#ibcon#read 3, iclass 6, count 0 2006.259.08:01:19.77#ibcon#about to read 4, iclass 6, count 0 2006.259.08:01:19.77#ibcon#read 4, iclass 6, count 0 2006.259.08:01:19.77#ibcon#about to read 5, iclass 6, count 0 2006.259.08:01:19.77#ibcon#read 5, iclass 6, count 0 2006.259.08:01:19.77#ibcon#about to read 6, iclass 6, count 0 2006.259.08:01:19.77#ibcon#read 6, iclass 6, count 0 2006.259.08:01:19.77#ibcon#end of sib2, iclass 6, count 0 2006.259.08:01:19.77#ibcon#*mode == 0, iclass 6, count 0 2006.259.08:01:19.77#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.259.08:01:19.77#ibcon#[25=USB\r\n] 2006.259.08:01:19.77#ibcon#*before write, iclass 6, count 0 2006.259.08:01:19.77#ibcon#enter sib2, iclass 6, count 0 2006.259.08:01:19.77#ibcon#flushed, iclass 6, count 0 2006.259.08:01:19.77#ibcon#about to write, iclass 6, count 0 2006.259.08:01:19.77#ibcon#wrote, iclass 6, count 0 2006.259.08:01:19.77#ibcon#about to read 3, iclass 6, count 0 2006.259.08:01:19.80#ibcon#read 3, iclass 6, count 0 2006.259.08:01:19.80#ibcon#about to read 4, iclass 6, count 0 2006.259.08:01:19.80#ibcon#read 4, iclass 6, count 0 2006.259.08:01:19.80#ibcon#about to read 5, iclass 6, count 0 2006.259.08:01:19.80#ibcon#read 5, iclass 6, count 0 2006.259.08:01:19.80#ibcon#about to read 6, iclass 6, count 0 2006.259.08:01:19.80#ibcon#read 6, iclass 6, count 0 2006.259.08:01:19.80#ibcon#end of sib2, iclass 6, count 0 2006.259.08:01:19.80#ibcon#*after write, iclass 6, count 0 2006.259.08:01:19.80#ibcon#*before return 0, iclass 6, count 0 2006.259.08:01:19.80#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.259.08:01:19.80#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.259.08:01:19.80#ibcon#about to clear, iclass 6 cls_cnt 0 2006.259.08:01:19.80#ibcon#cleared, iclass 6 cls_cnt 0 2006.259.08:01:19.80$vc4f8/valo=3,672.99 2006.259.08:01:19.80#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.259.08:01:19.80#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.259.08:01:19.80#ibcon#ireg 17 cls_cnt 0 2006.259.08:01:19.80#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.259.08:01:19.80#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.259.08:01:19.80#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.259.08:01:19.80#ibcon#enter wrdev, iclass 14, count 0 2006.259.08:01:19.80#ibcon#first serial, iclass 14, count 0 2006.259.08:01:19.80#ibcon#enter sib2, iclass 14, count 0 2006.259.08:01:19.80#ibcon#flushed, iclass 14, count 0 2006.259.08:01:19.80#ibcon#about to write, iclass 14, count 0 2006.259.08:01:19.80#ibcon#wrote, iclass 14, count 0 2006.259.08:01:19.80#ibcon#about to read 3, iclass 14, count 0 2006.259.08:01:19.82#ibcon#read 3, iclass 14, count 0 2006.259.08:01:19.82#ibcon#about to read 4, iclass 14, count 0 2006.259.08:01:19.82#ibcon#read 4, iclass 14, count 0 2006.259.08:01:19.82#ibcon#about to read 5, iclass 14, count 0 2006.259.08:01:19.82#ibcon#read 5, iclass 14, count 0 2006.259.08:01:19.82#ibcon#about to read 6, iclass 14, count 0 2006.259.08:01:19.82#ibcon#read 6, iclass 14, count 0 2006.259.08:01:19.82#ibcon#end of sib2, iclass 14, count 0 2006.259.08:01:19.82#ibcon#*mode == 0, iclass 14, count 0 2006.259.08:01:19.82#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.259.08:01:19.82#ibcon#[26=FRQ=03,672.99\r\n] 2006.259.08:01:19.82#ibcon#*before write, iclass 14, count 0 2006.259.08:01:19.82#ibcon#enter sib2, iclass 14, count 0 2006.259.08:01:19.82#ibcon#flushed, iclass 14, count 0 2006.259.08:01:19.82#ibcon#about to write, iclass 14, count 0 2006.259.08:01:19.82#ibcon#wrote, iclass 14, count 0 2006.259.08:01:19.82#ibcon#about to read 3, iclass 14, count 0 2006.259.08:01:19.87#ibcon#read 3, iclass 14, count 0 2006.259.08:01:19.87#ibcon#about to read 4, iclass 14, count 0 2006.259.08:01:19.87#ibcon#read 4, iclass 14, count 0 2006.259.08:01:19.87#ibcon#about to read 5, iclass 14, count 0 2006.259.08:01:19.87#ibcon#read 5, iclass 14, count 0 2006.259.08:01:19.87#ibcon#about to read 6, iclass 14, count 0 2006.259.08:01:19.87#ibcon#read 6, iclass 14, count 0 2006.259.08:01:19.87#ibcon#end of sib2, iclass 14, count 0 2006.259.08:01:19.87#ibcon#*after write, iclass 14, count 0 2006.259.08:01:19.87#ibcon#*before return 0, iclass 14, count 0 2006.259.08:01:19.87#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.259.08:01:19.87#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.259.08:01:19.87#ibcon#about to clear, iclass 14 cls_cnt 0 2006.259.08:01:19.87#ibcon#cleared, iclass 14 cls_cnt 0 2006.259.08:01:19.87$vc4f8/va=3,8 2006.259.08:01:19.87#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.259.08:01:19.87#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.259.08:01:19.87#ibcon#ireg 11 cls_cnt 2 2006.259.08:01:19.87#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.259.08:01:19.91#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.259.08:01:19.91#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.259.08:01:19.91#ibcon#enter wrdev, iclass 16, count 2 2006.259.08:01:19.91#ibcon#first serial, iclass 16, count 2 2006.259.08:01:19.91#ibcon#enter sib2, iclass 16, count 2 2006.259.08:01:19.91#ibcon#flushed, iclass 16, count 2 2006.259.08:01:19.91#ibcon#about to write, iclass 16, count 2 2006.259.08:01:19.91#ibcon#wrote, iclass 16, count 2 2006.259.08:01:19.91#ibcon#about to read 3, iclass 16, count 2 2006.259.08:01:19.93#ibcon#read 3, iclass 16, count 2 2006.259.08:01:19.93#ibcon#about to read 4, iclass 16, count 2 2006.259.08:01:19.93#ibcon#read 4, iclass 16, count 2 2006.259.08:01:19.93#ibcon#about to read 5, iclass 16, count 2 2006.259.08:01:19.93#ibcon#read 5, iclass 16, count 2 2006.259.08:01:19.93#ibcon#about to read 6, iclass 16, count 2 2006.259.08:01:19.93#ibcon#read 6, iclass 16, count 2 2006.259.08:01:19.93#ibcon#end of sib2, iclass 16, count 2 2006.259.08:01:19.93#ibcon#*mode == 0, iclass 16, count 2 2006.259.08:01:19.93#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.259.08:01:19.93#ibcon#[25=AT03-08\r\n] 2006.259.08:01:19.93#ibcon#*before write, iclass 16, count 2 2006.259.08:01:19.93#ibcon#enter sib2, iclass 16, count 2 2006.259.08:01:19.93#ibcon#flushed, iclass 16, count 2 2006.259.08:01:19.93#ibcon#about to write, iclass 16, count 2 2006.259.08:01:19.93#ibcon#wrote, iclass 16, count 2 2006.259.08:01:19.93#ibcon#about to read 3, iclass 16, count 2 2006.259.08:01:19.96#ibcon#read 3, iclass 16, count 2 2006.259.08:01:19.96#ibcon#about to read 4, iclass 16, count 2 2006.259.08:01:19.96#ibcon#read 4, iclass 16, count 2 2006.259.08:01:19.96#ibcon#about to read 5, iclass 16, count 2 2006.259.08:01:19.96#ibcon#read 5, iclass 16, count 2 2006.259.08:01:19.96#ibcon#about to read 6, iclass 16, count 2 2006.259.08:01:19.96#ibcon#read 6, iclass 16, count 2 2006.259.08:01:19.96#ibcon#end of sib2, iclass 16, count 2 2006.259.08:01:19.96#ibcon#*after write, iclass 16, count 2 2006.259.08:01:19.96#ibcon#*before return 0, iclass 16, count 2 2006.259.08:01:19.96#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.259.08:01:19.96#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.259.08:01:19.96#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.259.08:01:19.96#ibcon#ireg 7 cls_cnt 0 2006.259.08:01:19.96#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.259.08:01:20.08#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.259.08:01:20.08#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.259.08:01:20.08#ibcon#enter wrdev, iclass 16, count 0 2006.259.08:01:20.08#ibcon#first serial, iclass 16, count 0 2006.259.08:01:20.08#ibcon#enter sib2, iclass 16, count 0 2006.259.08:01:20.08#ibcon#flushed, iclass 16, count 0 2006.259.08:01:20.08#ibcon#about to write, iclass 16, count 0 2006.259.08:01:20.08#ibcon#wrote, iclass 16, count 0 2006.259.08:01:20.08#ibcon#about to read 3, iclass 16, count 0 2006.259.08:01:20.10#ibcon#read 3, iclass 16, count 0 2006.259.08:01:20.10#ibcon#about to read 4, iclass 16, count 0 2006.259.08:01:20.10#ibcon#read 4, iclass 16, count 0 2006.259.08:01:20.10#ibcon#about to read 5, iclass 16, count 0 2006.259.08:01:20.10#ibcon#read 5, iclass 16, count 0 2006.259.08:01:20.10#ibcon#about to read 6, iclass 16, count 0 2006.259.08:01:20.10#ibcon#read 6, iclass 16, count 0 2006.259.08:01:20.10#ibcon#end of sib2, iclass 16, count 0 2006.259.08:01:20.10#ibcon#*mode == 0, iclass 16, count 0 2006.259.08:01:20.10#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.259.08:01:20.10#ibcon#[25=USB\r\n] 2006.259.08:01:20.10#ibcon#*before write, iclass 16, count 0 2006.259.08:01:20.10#ibcon#enter sib2, iclass 16, count 0 2006.259.08:01:20.10#ibcon#flushed, iclass 16, count 0 2006.259.08:01:20.10#ibcon#about to write, iclass 16, count 0 2006.259.08:01:20.10#ibcon#wrote, iclass 16, count 0 2006.259.08:01:20.10#ibcon#about to read 3, iclass 16, count 0 2006.259.08:01:20.13#ibcon#read 3, iclass 16, count 0 2006.259.08:01:20.13#ibcon#about to read 4, iclass 16, count 0 2006.259.08:01:20.13#ibcon#read 4, iclass 16, count 0 2006.259.08:01:20.13#ibcon#about to read 5, iclass 16, count 0 2006.259.08:01:20.13#ibcon#read 5, iclass 16, count 0 2006.259.08:01:20.13#ibcon#about to read 6, iclass 16, count 0 2006.259.08:01:20.13#ibcon#read 6, iclass 16, count 0 2006.259.08:01:20.13#ibcon#end of sib2, iclass 16, count 0 2006.259.08:01:20.13#ibcon#*after write, iclass 16, count 0 2006.259.08:01:20.13#ibcon#*before return 0, iclass 16, count 0 2006.259.08:01:20.13#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.259.08:01:20.13#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.259.08:01:20.13#ibcon#about to clear, iclass 16 cls_cnt 0 2006.259.08:01:20.13#ibcon#cleared, iclass 16 cls_cnt 0 2006.259.08:01:20.13$vc4f8/valo=4,832.99 2006.259.08:01:20.13#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.259.08:01:20.13#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.259.08:01:20.13#ibcon#ireg 17 cls_cnt 0 2006.259.08:01:20.13#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.259.08:01:20.13#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.259.08:01:20.13#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.259.08:01:20.13#ibcon#enter wrdev, iclass 18, count 0 2006.259.08:01:20.13#ibcon#first serial, iclass 18, count 0 2006.259.08:01:20.13#ibcon#enter sib2, iclass 18, count 0 2006.259.08:01:20.13#ibcon#flushed, iclass 18, count 0 2006.259.08:01:20.13#ibcon#about to write, iclass 18, count 0 2006.259.08:01:20.13#ibcon#wrote, iclass 18, count 0 2006.259.08:01:20.13#ibcon#about to read 3, iclass 18, count 0 2006.259.08:01:20.15#ibcon#read 3, iclass 18, count 0 2006.259.08:01:20.15#ibcon#about to read 4, iclass 18, count 0 2006.259.08:01:20.15#ibcon#read 4, iclass 18, count 0 2006.259.08:01:20.15#ibcon#about to read 5, iclass 18, count 0 2006.259.08:01:20.15#ibcon#read 5, iclass 18, count 0 2006.259.08:01:20.15#ibcon#about to read 6, iclass 18, count 0 2006.259.08:01:20.15#ibcon#read 6, iclass 18, count 0 2006.259.08:01:20.15#ibcon#end of sib2, iclass 18, count 0 2006.259.08:01:20.15#ibcon#*mode == 0, iclass 18, count 0 2006.259.08:01:20.15#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.259.08:01:20.15#ibcon#[26=FRQ=04,832.99\r\n] 2006.259.08:01:20.15#ibcon#*before write, iclass 18, count 0 2006.259.08:01:20.15#ibcon#enter sib2, iclass 18, count 0 2006.259.08:01:20.15#ibcon#flushed, iclass 18, count 0 2006.259.08:01:20.15#ibcon#about to write, iclass 18, count 0 2006.259.08:01:20.15#ibcon#wrote, iclass 18, count 0 2006.259.08:01:20.15#ibcon#about to read 3, iclass 18, count 0 2006.259.08:01:20.19#ibcon#read 3, iclass 18, count 0 2006.259.08:01:20.19#ibcon#about to read 4, iclass 18, count 0 2006.259.08:01:20.19#ibcon#read 4, iclass 18, count 0 2006.259.08:01:20.19#ibcon#about to read 5, iclass 18, count 0 2006.259.08:01:20.19#ibcon#read 5, iclass 18, count 0 2006.259.08:01:20.19#ibcon#about to read 6, iclass 18, count 0 2006.259.08:01:20.19#ibcon#read 6, iclass 18, count 0 2006.259.08:01:20.19#ibcon#end of sib2, iclass 18, count 0 2006.259.08:01:20.19#ibcon#*after write, iclass 18, count 0 2006.259.08:01:20.19#ibcon#*before return 0, iclass 18, count 0 2006.259.08:01:20.19#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.259.08:01:20.19#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.259.08:01:20.19#ibcon#about to clear, iclass 18 cls_cnt 0 2006.259.08:01:20.19#ibcon#cleared, iclass 18 cls_cnt 0 2006.259.08:01:20.19$vc4f8/va=4,7 2006.259.08:01:20.19#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.259.08:01:20.19#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.259.08:01:20.19#ibcon#ireg 11 cls_cnt 2 2006.259.08:01:20.19#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.259.08:01:20.25#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.259.08:01:20.25#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.259.08:01:20.25#ibcon#enter wrdev, iclass 20, count 2 2006.259.08:01:20.25#ibcon#first serial, iclass 20, count 2 2006.259.08:01:20.25#ibcon#enter sib2, iclass 20, count 2 2006.259.08:01:20.25#ibcon#flushed, iclass 20, count 2 2006.259.08:01:20.25#ibcon#about to write, iclass 20, count 2 2006.259.08:01:20.25#ibcon#wrote, iclass 20, count 2 2006.259.08:01:20.25#ibcon#about to read 3, iclass 20, count 2 2006.259.08:01:20.27#ibcon#read 3, iclass 20, count 2 2006.259.08:01:20.27#ibcon#about to read 4, iclass 20, count 2 2006.259.08:01:20.27#ibcon#read 4, iclass 20, count 2 2006.259.08:01:20.27#ibcon#about to read 5, iclass 20, count 2 2006.259.08:01:20.27#ibcon#read 5, iclass 20, count 2 2006.259.08:01:20.27#ibcon#about to read 6, iclass 20, count 2 2006.259.08:01:20.27#ibcon#read 6, iclass 20, count 2 2006.259.08:01:20.27#ibcon#end of sib2, iclass 20, count 2 2006.259.08:01:20.27#ibcon#*mode == 0, iclass 20, count 2 2006.259.08:01:20.27#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.259.08:01:20.27#ibcon#[25=AT04-07\r\n] 2006.259.08:01:20.27#ibcon#*before write, iclass 20, count 2 2006.259.08:01:20.27#ibcon#enter sib2, iclass 20, count 2 2006.259.08:01:20.27#ibcon#flushed, iclass 20, count 2 2006.259.08:01:20.27#ibcon#about to write, iclass 20, count 2 2006.259.08:01:20.27#ibcon#wrote, iclass 20, count 2 2006.259.08:01:20.27#ibcon#about to read 3, iclass 20, count 2 2006.259.08:01:20.30#ibcon#read 3, iclass 20, count 2 2006.259.08:01:20.30#ibcon#about to read 4, iclass 20, count 2 2006.259.08:01:20.30#ibcon#read 4, iclass 20, count 2 2006.259.08:01:20.30#ibcon#about to read 5, iclass 20, count 2 2006.259.08:01:20.30#ibcon#read 5, iclass 20, count 2 2006.259.08:01:20.30#ibcon#about to read 6, iclass 20, count 2 2006.259.08:01:20.30#ibcon#read 6, iclass 20, count 2 2006.259.08:01:20.30#ibcon#end of sib2, iclass 20, count 2 2006.259.08:01:20.30#ibcon#*after write, iclass 20, count 2 2006.259.08:01:20.30#ibcon#*before return 0, iclass 20, count 2 2006.259.08:01:20.30#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.259.08:01:20.30#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.259.08:01:20.30#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.259.08:01:20.30#ibcon#ireg 7 cls_cnt 0 2006.259.08:01:20.30#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.259.08:01:20.42#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.259.08:01:20.42#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.259.08:01:20.42#ibcon#enter wrdev, iclass 20, count 0 2006.259.08:01:20.42#ibcon#first serial, iclass 20, count 0 2006.259.08:01:20.42#ibcon#enter sib2, iclass 20, count 0 2006.259.08:01:20.42#ibcon#flushed, iclass 20, count 0 2006.259.08:01:20.42#ibcon#about to write, iclass 20, count 0 2006.259.08:01:20.42#ibcon#wrote, iclass 20, count 0 2006.259.08:01:20.42#ibcon#about to read 3, iclass 20, count 0 2006.259.08:01:20.44#ibcon#read 3, iclass 20, count 0 2006.259.08:01:20.44#ibcon#about to read 4, iclass 20, count 0 2006.259.08:01:20.44#ibcon#read 4, iclass 20, count 0 2006.259.08:01:20.44#ibcon#about to read 5, iclass 20, count 0 2006.259.08:01:20.44#ibcon#read 5, iclass 20, count 0 2006.259.08:01:20.44#ibcon#about to read 6, iclass 20, count 0 2006.259.08:01:20.44#ibcon#read 6, iclass 20, count 0 2006.259.08:01:20.44#ibcon#end of sib2, iclass 20, count 0 2006.259.08:01:20.44#ibcon#*mode == 0, iclass 20, count 0 2006.259.08:01:20.44#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.259.08:01:20.44#ibcon#[25=USB\r\n] 2006.259.08:01:20.44#ibcon#*before write, iclass 20, count 0 2006.259.08:01:20.44#ibcon#enter sib2, iclass 20, count 0 2006.259.08:01:20.44#ibcon#flushed, iclass 20, count 0 2006.259.08:01:20.44#ibcon#about to write, iclass 20, count 0 2006.259.08:01:20.44#ibcon#wrote, iclass 20, count 0 2006.259.08:01:20.44#ibcon#about to read 3, iclass 20, count 0 2006.259.08:01:20.47#ibcon#read 3, iclass 20, count 0 2006.259.08:01:20.47#ibcon#about to read 4, iclass 20, count 0 2006.259.08:01:20.47#ibcon#read 4, iclass 20, count 0 2006.259.08:01:20.47#ibcon#about to read 5, iclass 20, count 0 2006.259.08:01:20.47#ibcon#read 5, iclass 20, count 0 2006.259.08:01:20.47#ibcon#about to read 6, iclass 20, count 0 2006.259.08:01:20.47#ibcon#read 6, iclass 20, count 0 2006.259.08:01:20.47#ibcon#end of sib2, iclass 20, count 0 2006.259.08:01:20.47#ibcon#*after write, iclass 20, count 0 2006.259.08:01:20.47#ibcon#*before return 0, iclass 20, count 0 2006.259.08:01:20.47#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.259.08:01:20.47#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.259.08:01:20.47#ibcon#about to clear, iclass 20 cls_cnt 0 2006.259.08:01:20.47#ibcon#cleared, iclass 20 cls_cnt 0 2006.259.08:01:20.47$vc4f8/valo=5,652.99 2006.259.08:01:20.47#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.259.08:01:20.47#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.259.08:01:20.47#ibcon#ireg 17 cls_cnt 0 2006.259.08:01:20.47#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.259.08:01:20.47#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.259.08:01:20.47#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.259.08:01:20.47#ibcon#enter wrdev, iclass 22, count 0 2006.259.08:01:20.47#ibcon#first serial, iclass 22, count 0 2006.259.08:01:20.47#ibcon#enter sib2, iclass 22, count 0 2006.259.08:01:20.47#ibcon#flushed, iclass 22, count 0 2006.259.08:01:20.47#ibcon#about to write, iclass 22, count 0 2006.259.08:01:20.47#ibcon#wrote, iclass 22, count 0 2006.259.08:01:20.47#ibcon#about to read 3, iclass 22, count 0 2006.259.08:01:20.49#ibcon#read 3, iclass 22, count 0 2006.259.08:01:20.49#ibcon#about to read 4, iclass 22, count 0 2006.259.08:01:20.49#ibcon#read 4, iclass 22, count 0 2006.259.08:01:20.49#ibcon#about to read 5, iclass 22, count 0 2006.259.08:01:20.49#ibcon#read 5, iclass 22, count 0 2006.259.08:01:20.49#ibcon#about to read 6, iclass 22, count 0 2006.259.08:01:20.49#ibcon#read 6, iclass 22, count 0 2006.259.08:01:20.49#ibcon#end of sib2, iclass 22, count 0 2006.259.08:01:20.49#ibcon#*mode == 0, iclass 22, count 0 2006.259.08:01:20.49#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.259.08:01:20.49#ibcon#[26=FRQ=05,652.99\r\n] 2006.259.08:01:20.49#ibcon#*before write, iclass 22, count 0 2006.259.08:01:20.49#ibcon#enter sib2, iclass 22, count 0 2006.259.08:01:20.49#ibcon#flushed, iclass 22, count 0 2006.259.08:01:20.49#ibcon#about to write, iclass 22, count 0 2006.259.08:01:20.49#ibcon#wrote, iclass 22, count 0 2006.259.08:01:20.49#ibcon#about to read 3, iclass 22, count 0 2006.259.08:01:20.53#ibcon#read 3, iclass 22, count 0 2006.259.08:01:20.53#ibcon#about to read 4, iclass 22, count 0 2006.259.08:01:20.53#ibcon#read 4, iclass 22, count 0 2006.259.08:01:20.53#ibcon#about to read 5, iclass 22, count 0 2006.259.08:01:20.53#ibcon#read 5, iclass 22, count 0 2006.259.08:01:20.53#ibcon#about to read 6, iclass 22, count 0 2006.259.08:01:20.53#ibcon#read 6, iclass 22, count 0 2006.259.08:01:20.53#ibcon#end of sib2, iclass 22, count 0 2006.259.08:01:20.53#ibcon#*after write, iclass 22, count 0 2006.259.08:01:20.53#ibcon#*before return 0, iclass 22, count 0 2006.259.08:01:20.53#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.259.08:01:20.53#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.259.08:01:20.53#ibcon#about to clear, iclass 22 cls_cnt 0 2006.259.08:01:20.53#ibcon#cleared, iclass 22 cls_cnt 0 2006.259.08:01:20.53$vc4f8/va=5,7 2006.259.08:01:20.53#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.259.08:01:20.53#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.259.08:01:20.53#ibcon#ireg 11 cls_cnt 2 2006.259.08:01:20.53#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.259.08:01:20.59#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.259.08:01:20.59#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.259.08:01:20.59#ibcon#enter wrdev, iclass 24, count 2 2006.259.08:01:20.59#ibcon#first serial, iclass 24, count 2 2006.259.08:01:20.59#ibcon#enter sib2, iclass 24, count 2 2006.259.08:01:20.59#ibcon#flushed, iclass 24, count 2 2006.259.08:01:20.59#ibcon#about to write, iclass 24, count 2 2006.259.08:01:20.59#ibcon#wrote, iclass 24, count 2 2006.259.08:01:20.59#ibcon#about to read 3, iclass 24, count 2 2006.259.08:01:20.61#ibcon#read 3, iclass 24, count 2 2006.259.08:01:20.61#ibcon#about to read 4, iclass 24, count 2 2006.259.08:01:20.61#ibcon#read 4, iclass 24, count 2 2006.259.08:01:20.61#ibcon#about to read 5, iclass 24, count 2 2006.259.08:01:20.61#ibcon#read 5, iclass 24, count 2 2006.259.08:01:20.61#ibcon#about to read 6, iclass 24, count 2 2006.259.08:01:20.61#ibcon#read 6, iclass 24, count 2 2006.259.08:01:20.61#ibcon#end of sib2, iclass 24, count 2 2006.259.08:01:20.61#ibcon#*mode == 0, iclass 24, count 2 2006.259.08:01:20.61#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.259.08:01:20.61#ibcon#[25=AT05-07\r\n] 2006.259.08:01:20.61#ibcon#*before write, iclass 24, count 2 2006.259.08:01:20.61#ibcon#enter sib2, iclass 24, count 2 2006.259.08:01:20.61#ibcon#flushed, iclass 24, count 2 2006.259.08:01:20.61#ibcon#about to write, iclass 24, count 2 2006.259.08:01:20.61#ibcon#wrote, iclass 24, count 2 2006.259.08:01:20.61#ibcon#about to read 3, iclass 24, count 2 2006.259.08:01:20.64#ibcon#read 3, iclass 24, count 2 2006.259.08:01:20.64#ibcon#about to read 4, iclass 24, count 2 2006.259.08:01:20.64#ibcon#read 4, iclass 24, count 2 2006.259.08:01:20.64#ibcon#about to read 5, iclass 24, count 2 2006.259.08:01:20.64#ibcon#read 5, iclass 24, count 2 2006.259.08:01:20.64#ibcon#about to read 6, iclass 24, count 2 2006.259.08:01:20.64#ibcon#read 6, iclass 24, count 2 2006.259.08:01:20.64#ibcon#end of sib2, iclass 24, count 2 2006.259.08:01:20.64#ibcon#*after write, iclass 24, count 2 2006.259.08:01:20.64#ibcon#*before return 0, iclass 24, count 2 2006.259.08:01:20.64#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.259.08:01:20.64#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.259.08:01:20.64#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.259.08:01:20.64#ibcon#ireg 7 cls_cnt 0 2006.259.08:01:20.64#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.259.08:01:20.76#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.259.08:01:20.76#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.259.08:01:20.76#ibcon#enter wrdev, iclass 24, count 0 2006.259.08:01:20.76#ibcon#first serial, iclass 24, count 0 2006.259.08:01:20.76#ibcon#enter sib2, iclass 24, count 0 2006.259.08:01:20.76#ibcon#flushed, iclass 24, count 0 2006.259.08:01:20.76#ibcon#about to write, iclass 24, count 0 2006.259.08:01:20.76#ibcon#wrote, iclass 24, count 0 2006.259.08:01:20.76#ibcon#about to read 3, iclass 24, count 0 2006.259.08:01:20.78#ibcon#read 3, iclass 24, count 0 2006.259.08:01:20.78#ibcon#about to read 4, iclass 24, count 0 2006.259.08:01:20.78#ibcon#read 4, iclass 24, count 0 2006.259.08:01:20.78#ibcon#about to read 5, iclass 24, count 0 2006.259.08:01:20.78#ibcon#read 5, iclass 24, count 0 2006.259.08:01:20.78#ibcon#about to read 6, iclass 24, count 0 2006.259.08:01:20.78#ibcon#read 6, iclass 24, count 0 2006.259.08:01:20.78#ibcon#end of sib2, iclass 24, count 0 2006.259.08:01:20.78#ibcon#*mode == 0, iclass 24, count 0 2006.259.08:01:20.78#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.259.08:01:20.78#ibcon#[25=USB\r\n] 2006.259.08:01:20.78#ibcon#*before write, iclass 24, count 0 2006.259.08:01:20.78#ibcon#enter sib2, iclass 24, count 0 2006.259.08:01:20.78#ibcon#flushed, iclass 24, count 0 2006.259.08:01:20.78#ibcon#about to write, iclass 24, count 0 2006.259.08:01:20.78#ibcon#wrote, iclass 24, count 0 2006.259.08:01:20.78#ibcon#about to read 3, iclass 24, count 0 2006.259.08:01:20.81#ibcon#read 3, iclass 24, count 0 2006.259.08:01:20.81#ibcon#about to read 4, iclass 24, count 0 2006.259.08:01:20.81#ibcon#read 4, iclass 24, count 0 2006.259.08:01:20.81#ibcon#about to read 5, iclass 24, count 0 2006.259.08:01:20.81#ibcon#read 5, iclass 24, count 0 2006.259.08:01:20.81#ibcon#about to read 6, iclass 24, count 0 2006.259.08:01:20.81#ibcon#read 6, iclass 24, count 0 2006.259.08:01:20.81#ibcon#end of sib2, iclass 24, count 0 2006.259.08:01:20.81#ibcon#*after write, iclass 24, count 0 2006.259.08:01:20.81#ibcon#*before return 0, iclass 24, count 0 2006.259.08:01:20.81#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.259.08:01:20.81#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.259.08:01:20.81#ibcon#about to clear, iclass 24 cls_cnt 0 2006.259.08:01:20.81#ibcon#cleared, iclass 24 cls_cnt 0 2006.259.08:01:20.81$vc4f8/valo=6,772.99 2006.259.08:01:20.81#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.259.08:01:20.81#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.259.08:01:20.81#ibcon#ireg 17 cls_cnt 0 2006.259.08:01:20.81#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.259.08:01:20.81#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.259.08:01:20.81#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.259.08:01:20.81#ibcon#enter wrdev, iclass 26, count 0 2006.259.08:01:20.81#ibcon#first serial, iclass 26, count 0 2006.259.08:01:20.81#ibcon#enter sib2, iclass 26, count 0 2006.259.08:01:20.81#ibcon#flushed, iclass 26, count 0 2006.259.08:01:20.81#ibcon#about to write, iclass 26, count 0 2006.259.08:01:20.81#ibcon#wrote, iclass 26, count 0 2006.259.08:01:20.81#ibcon#about to read 3, iclass 26, count 0 2006.259.08:01:20.83#ibcon#read 3, iclass 26, count 0 2006.259.08:01:20.83#ibcon#about to read 4, iclass 26, count 0 2006.259.08:01:20.83#ibcon#read 4, iclass 26, count 0 2006.259.08:01:20.83#ibcon#about to read 5, iclass 26, count 0 2006.259.08:01:20.83#ibcon#read 5, iclass 26, count 0 2006.259.08:01:20.83#ibcon#about to read 6, iclass 26, count 0 2006.259.08:01:20.83#ibcon#read 6, iclass 26, count 0 2006.259.08:01:20.83#ibcon#end of sib2, iclass 26, count 0 2006.259.08:01:20.83#ibcon#*mode == 0, iclass 26, count 0 2006.259.08:01:20.83#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.259.08:01:20.83#ibcon#[26=FRQ=06,772.99\r\n] 2006.259.08:01:20.83#ibcon#*before write, iclass 26, count 0 2006.259.08:01:20.83#ibcon#enter sib2, iclass 26, count 0 2006.259.08:01:20.83#ibcon#flushed, iclass 26, count 0 2006.259.08:01:20.83#ibcon#about to write, iclass 26, count 0 2006.259.08:01:20.83#ibcon#wrote, iclass 26, count 0 2006.259.08:01:20.83#ibcon#about to read 3, iclass 26, count 0 2006.259.08:01:20.87#ibcon#read 3, iclass 26, count 0 2006.259.08:01:20.87#ibcon#about to read 4, iclass 26, count 0 2006.259.08:01:20.87#ibcon#read 4, iclass 26, count 0 2006.259.08:01:20.87#ibcon#about to read 5, iclass 26, count 0 2006.259.08:01:20.87#ibcon#read 5, iclass 26, count 0 2006.259.08:01:20.87#ibcon#about to read 6, iclass 26, count 0 2006.259.08:01:20.87#ibcon#read 6, iclass 26, count 0 2006.259.08:01:20.87#ibcon#end of sib2, iclass 26, count 0 2006.259.08:01:20.87#ibcon#*after write, iclass 26, count 0 2006.259.08:01:20.87#ibcon#*before return 0, iclass 26, count 0 2006.259.08:01:20.87#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.259.08:01:20.87#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.259.08:01:20.87#ibcon#about to clear, iclass 26 cls_cnt 0 2006.259.08:01:20.87#ibcon#cleared, iclass 26 cls_cnt 0 2006.259.08:01:20.87$vc4f8/va=6,6 2006.259.08:01:20.87#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.259.08:01:20.87#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.259.08:01:20.87#ibcon#ireg 11 cls_cnt 2 2006.259.08:01:20.87#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.259.08:01:20.93#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.259.08:01:20.93#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.259.08:01:20.93#ibcon#enter wrdev, iclass 28, count 2 2006.259.08:01:20.93#ibcon#first serial, iclass 28, count 2 2006.259.08:01:20.93#ibcon#enter sib2, iclass 28, count 2 2006.259.08:01:20.93#ibcon#flushed, iclass 28, count 2 2006.259.08:01:20.93#ibcon#about to write, iclass 28, count 2 2006.259.08:01:20.93#ibcon#wrote, iclass 28, count 2 2006.259.08:01:20.93#ibcon#about to read 3, iclass 28, count 2 2006.259.08:01:20.95#ibcon#read 3, iclass 28, count 2 2006.259.08:01:20.95#ibcon#about to read 4, iclass 28, count 2 2006.259.08:01:20.95#ibcon#read 4, iclass 28, count 2 2006.259.08:01:20.95#ibcon#about to read 5, iclass 28, count 2 2006.259.08:01:20.95#ibcon#read 5, iclass 28, count 2 2006.259.08:01:20.95#ibcon#about to read 6, iclass 28, count 2 2006.259.08:01:20.95#ibcon#read 6, iclass 28, count 2 2006.259.08:01:20.95#ibcon#end of sib2, iclass 28, count 2 2006.259.08:01:20.95#ibcon#*mode == 0, iclass 28, count 2 2006.259.08:01:20.95#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.259.08:01:20.95#ibcon#[25=AT06-06\r\n] 2006.259.08:01:20.95#ibcon#*before write, iclass 28, count 2 2006.259.08:01:20.95#ibcon#enter sib2, iclass 28, count 2 2006.259.08:01:20.95#ibcon#flushed, iclass 28, count 2 2006.259.08:01:20.95#ibcon#about to write, iclass 28, count 2 2006.259.08:01:20.95#ibcon#wrote, iclass 28, count 2 2006.259.08:01:20.95#ibcon#about to read 3, iclass 28, count 2 2006.259.08:01:20.98#ibcon#read 3, iclass 28, count 2 2006.259.08:01:20.98#ibcon#about to read 4, iclass 28, count 2 2006.259.08:01:20.98#ibcon#read 4, iclass 28, count 2 2006.259.08:01:20.98#ibcon#about to read 5, iclass 28, count 2 2006.259.08:01:20.98#ibcon#read 5, iclass 28, count 2 2006.259.08:01:20.98#ibcon#about to read 6, iclass 28, count 2 2006.259.08:01:20.98#ibcon#read 6, iclass 28, count 2 2006.259.08:01:20.98#ibcon#end of sib2, iclass 28, count 2 2006.259.08:01:20.98#ibcon#*after write, iclass 28, count 2 2006.259.08:01:20.98#ibcon#*before return 0, iclass 28, count 2 2006.259.08:01:20.98#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.259.08:01:20.98#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.259.08:01:20.98#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.259.08:01:20.98#ibcon#ireg 7 cls_cnt 0 2006.259.08:01:20.98#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.259.08:01:21.10#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.259.08:01:21.10#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.259.08:01:21.10#ibcon#enter wrdev, iclass 28, count 0 2006.259.08:01:21.10#ibcon#first serial, iclass 28, count 0 2006.259.08:01:21.10#ibcon#enter sib2, iclass 28, count 0 2006.259.08:01:21.10#ibcon#flushed, iclass 28, count 0 2006.259.08:01:21.10#ibcon#about to write, iclass 28, count 0 2006.259.08:01:21.10#ibcon#wrote, iclass 28, count 0 2006.259.08:01:21.10#ibcon#about to read 3, iclass 28, count 0 2006.259.08:01:21.12#ibcon#read 3, iclass 28, count 0 2006.259.08:01:21.12#ibcon#about to read 4, iclass 28, count 0 2006.259.08:01:21.12#ibcon#read 4, iclass 28, count 0 2006.259.08:01:21.12#ibcon#about to read 5, iclass 28, count 0 2006.259.08:01:21.12#ibcon#read 5, iclass 28, count 0 2006.259.08:01:21.12#ibcon#about to read 6, iclass 28, count 0 2006.259.08:01:21.12#ibcon#read 6, iclass 28, count 0 2006.259.08:01:21.12#ibcon#end of sib2, iclass 28, count 0 2006.259.08:01:21.12#ibcon#*mode == 0, iclass 28, count 0 2006.259.08:01:21.12#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.259.08:01:21.12#ibcon#[25=USB\r\n] 2006.259.08:01:21.12#ibcon#*before write, iclass 28, count 0 2006.259.08:01:21.12#ibcon#enter sib2, iclass 28, count 0 2006.259.08:01:21.12#ibcon#flushed, iclass 28, count 0 2006.259.08:01:21.12#ibcon#about to write, iclass 28, count 0 2006.259.08:01:21.12#ibcon#wrote, iclass 28, count 0 2006.259.08:01:21.12#ibcon#about to read 3, iclass 28, count 0 2006.259.08:01:21.15#ibcon#read 3, iclass 28, count 0 2006.259.08:01:21.15#ibcon#about to read 4, iclass 28, count 0 2006.259.08:01:21.15#ibcon#read 4, iclass 28, count 0 2006.259.08:01:21.15#ibcon#about to read 5, iclass 28, count 0 2006.259.08:01:21.15#ibcon#read 5, iclass 28, count 0 2006.259.08:01:21.15#ibcon#about to read 6, iclass 28, count 0 2006.259.08:01:21.15#ibcon#read 6, iclass 28, count 0 2006.259.08:01:21.15#ibcon#end of sib2, iclass 28, count 0 2006.259.08:01:21.15#ibcon#*after write, iclass 28, count 0 2006.259.08:01:21.15#ibcon#*before return 0, iclass 28, count 0 2006.259.08:01:21.15#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.259.08:01:21.15#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.259.08:01:21.15#ibcon#about to clear, iclass 28 cls_cnt 0 2006.259.08:01:21.15#ibcon#cleared, iclass 28 cls_cnt 0 2006.259.08:01:21.15$vc4f8/valo=7,832.99 2006.259.08:01:21.15#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.259.08:01:21.15#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.259.08:01:21.15#ibcon#ireg 17 cls_cnt 0 2006.259.08:01:21.15#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.259.08:01:21.15#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.259.08:01:21.15#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.259.08:01:21.15#ibcon#enter wrdev, iclass 30, count 0 2006.259.08:01:21.15#ibcon#first serial, iclass 30, count 0 2006.259.08:01:21.15#ibcon#enter sib2, iclass 30, count 0 2006.259.08:01:21.15#ibcon#flushed, iclass 30, count 0 2006.259.08:01:21.15#ibcon#about to write, iclass 30, count 0 2006.259.08:01:21.15#ibcon#wrote, iclass 30, count 0 2006.259.08:01:21.15#ibcon#about to read 3, iclass 30, count 0 2006.259.08:01:21.17#ibcon#read 3, iclass 30, count 0 2006.259.08:01:21.17#ibcon#about to read 4, iclass 30, count 0 2006.259.08:01:21.17#ibcon#read 4, iclass 30, count 0 2006.259.08:01:21.17#ibcon#about to read 5, iclass 30, count 0 2006.259.08:01:21.17#ibcon#read 5, iclass 30, count 0 2006.259.08:01:21.17#ibcon#about to read 6, iclass 30, count 0 2006.259.08:01:21.17#ibcon#read 6, iclass 30, count 0 2006.259.08:01:21.17#ibcon#end of sib2, iclass 30, count 0 2006.259.08:01:21.17#ibcon#*mode == 0, iclass 30, count 0 2006.259.08:01:21.17#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.259.08:01:21.17#ibcon#[26=FRQ=07,832.99\r\n] 2006.259.08:01:21.17#ibcon#*before write, iclass 30, count 0 2006.259.08:01:21.17#ibcon#enter sib2, iclass 30, count 0 2006.259.08:01:21.17#ibcon#flushed, iclass 30, count 0 2006.259.08:01:21.17#ibcon#about to write, iclass 30, count 0 2006.259.08:01:21.17#ibcon#wrote, iclass 30, count 0 2006.259.08:01:21.17#ibcon#about to read 3, iclass 30, count 0 2006.259.08:01:21.21#ibcon#read 3, iclass 30, count 0 2006.259.08:01:21.21#ibcon#about to read 4, iclass 30, count 0 2006.259.08:01:21.21#ibcon#read 4, iclass 30, count 0 2006.259.08:01:21.21#ibcon#about to read 5, iclass 30, count 0 2006.259.08:01:21.21#ibcon#read 5, iclass 30, count 0 2006.259.08:01:21.21#ibcon#about to read 6, iclass 30, count 0 2006.259.08:01:21.21#ibcon#read 6, iclass 30, count 0 2006.259.08:01:21.21#ibcon#end of sib2, iclass 30, count 0 2006.259.08:01:21.21#ibcon#*after write, iclass 30, count 0 2006.259.08:01:21.21#ibcon#*before return 0, iclass 30, count 0 2006.259.08:01:21.21#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.259.08:01:21.21#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.259.08:01:21.21#ibcon#about to clear, iclass 30 cls_cnt 0 2006.259.08:01:21.21#ibcon#cleared, iclass 30 cls_cnt 0 2006.259.08:01:21.21$vc4f8/va=7,6 2006.259.08:01:21.21#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.259.08:01:21.21#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.259.08:01:21.21#ibcon#ireg 11 cls_cnt 2 2006.259.08:01:21.21#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.259.08:01:21.27#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.259.08:01:21.27#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.259.08:01:21.27#ibcon#enter wrdev, iclass 32, count 2 2006.259.08:01:21.27#ibcon#first serial, iclass 32, count 2 2006.259.08:01:21.27#ibcon#enter sib2, iclass 32, count 2 2006.259.08:01:21.27#ibcon#flushed, iclass 32, count 2 2006.259.08:01:21.27#ibcon#about to write, iclass 32, count 2 2006.259.08:01:21.27#ibcon#wrote, iclass 32, count 2 2006.259.08:01:21.27#ibcon#about to read 3, iclass 32, count 2 2006.259.08:01:21.29#ibcon#read 3, iclass 32, count 2 2006.259.08:01:21.29#ibcon#about to read 4, iclass 32, count 2 2006.259.08:01:21.29#ibcon#read 4, iclass 32, count 2 2006.259.08:01:21.29#ibcon#about to read 5, iclass 32, count 2 2006.259.08:01:21.29#ibcon#read 5, iclass 32, count 2 2006.259.08:01:21.29#ibcon#about to read 6, iclass 32, count 2 2006.259.08:01:21.29#ibcon#read 6, iclass 32, count 2 2006.259.08:01:21.29#ibcon#end of sib2, iclass 32, count 2 2006.259.08:01:21.29#ibcon#*mode == 0, iclass 32, count 2 2006.259.08:01:21.29#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.259.08:01:21.29#ibcon#[25=AT07-06\r\n] 2006.259.08:01:21.29#ibcon#*before write, iclass 32, count 2 2006.259.08:01:21.29#ibcon#enter sib2, iclass 32, count 2 2006.259.08:01:21.29#ibcon#flushed, iclass 32, count 2 2006.259.08:01:21.29#ibcon#about to write, iclass 32, count 2 2006.259.08:01:21.29#ibcon#wrote, iclass 32, count 2 2006.259.08:01:21.29#ibcon#about to read 3, iclass 32, count 2 2006.259.08:01:21.32#ibcon#read 3, iclass 32, count 2 2006.259.08:01:21.32#ibcon#about to read 4, iclass 32, count 2 2006.259.08:01:21.32#ibcon#read 4, iclass 32, count 2 2006.259.08:01:21.32#ibcon#about to read 5, iclass 32, count 2 2006.259.08:01:21.32#ibcon#read 5, iclass 32, count 2 2006.259.08:01:21.32#ibcon#about to read 6, iclass 32, count 2 2006.259.08:01:21.32#ibcon#read 6, iclass 32, count 2 2006.259.08:01:21.32#ibcon#end of sib2, iclass 32, count 2 2006.259.08:01:21.32#ibcon#*after write, iclass 32, count 2 2006.259.08:01:21.32#ibcon#*before return 0, iclass 32, count 2 2006.259.08:01:21.32#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.259.08:01:21.32#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.259.08:01:21.32#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.259.08:01:21.32#ibcon#ireg 7 cls_cnt 0 2006.259.08:01:21.32#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.259.08:01:21.44#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.259.08:01:21.44#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.259.08:01:21.44#ibcon#enter wrdev, iclass 32, count 0 2006.259.08:01:21.44#ibcon#first serial, iclass 32, count 0 2006.259.08:01:21.44#ibcon#enter sib2, iclass 32, count 0 2006.259.08:01:21.44#ibcon#flushed, iclass 32, count 0 2006.259.08:01:21.44#ibcon#about to write, iclass 32, count 0 2006.259.08:01:21.44#ibcon#wrote, iclass 32, count 0 2006.259.08:01:21.44#ibcon#about to read 3, iclass 32, count 0 2006.259.08:01:21.46#ibcon#read 3, iclass 32, count 0 2006.259.08:01:21.46#ibcon#about to read 4, iclass 32, count 0 2006.259.08:01:21.46#ibcon#read 4, iclass 32, count 0 2006.259.08:01:21.46#ibcon#about to read 5, iclass 32, count 0 2006.259.08:01:21.46#ibcon#read 5, iclass 32, count 0 2006.259.08:01:21.46#ibcon#about to read 6, iclass 32, count 0 2006.259.08:01:21.46#ibcon#read 6, iclass 32, count 0 2006.259.08:01:21.46#ibcon#end of sib2, iclass 32, count 0 2006.259.08:01:21.46#ibcon#*mode == 0, iclass 32, count 0 2006.259.08:01:21.46#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.259.08:01:21.46#ibcon#[25=USB\r\n] 2006.259.08:01:21.46#ibcon#*before write, iclass 32, count 0 2006.259.08:01:21.46#ibcon#enter sib2, iclass 32, count 0 2006.259.08:01:21.46#ibcon#flushed, iclass 32, count 0 2006.259.08:01:21.46#ibcon#about to write, iclass 32, count 0 2006.259.08:01:21.46#ibcon#wrote, iclass 32, count 0 2006.259.08:01:21.46#ibcon#about to read 3, iclass 32, count 0 2006.259.08:01:21.49#ibcon#read 3, iclass 32, count 0 2006.259.08:01:21.49#ibcon#about to read 4, iclass 32, count 0 2006.259.08:01:21.49#ibcon#read 4, iclass 32, count 0 2006.259.08:01:21.49#ibcon#about to read 5, iclass 32, count 0 2006.259.08:01:21.49#ibcon#read 5, iclass 32, count 0 2006.259.08:01:21.49#ibcon#about to read 6, iclass 32, count 0 2006.259.08:01:21.49#ibcon#read 6, iclass 32, count 0 2006.259.08:01:21.49#ibcon#end of sib2, iclass 32, count 0 2006.259.08:01:21.49#ibcon#*after write, iclass 32, count 0 2006.259.08:01:21.49#ibcon#*before return 0, iclass 32, count 0 2006.259.08:01:21.49#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.259.08:01:21.49#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.259.08:01:21.49#ibcon#about to clear, iclass 32 cls_cnt 0 2006.259.08:01:21.49#ibcon#cleared, iclass 32 cls_cnt 0 2006.259.08:01:21.49$vc4f8/valo=8,852.99 2006.259.08:01:21.49#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.259.08:01:21.49#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.259.08:01:21.49#ibcon#ireg 17 cls_cnt 0 2006.259.08:01:21.49#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.259.08:01:21.49#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.259.08:01:21.49#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.259.08:01:21.49#ibcon#enter wrdev, iclass 34, count 0 2006.259.08:01:21.49#ibcon#first serial, iclass 34, count 0 2006.259.08:01:21.49#ibcon#enter sib2, iclass 34, count 0 2006.259.08:01:21.49#ibcon#flushed, iclass 34, count 0 2006.259.08:01:21.49#ibcon#about to write, iclass 34, count 0 2006.259.08:01:21.49#ibcon#wrote, iclass 34, count 0 2006.259.08:01:21.49#ibcon#about to read 3, iclass 34, count 0 2006.259.08:01:21.51#ibcon#read 3, iclass 34, count 0 2006.259.08:01:21.51#ibcon#about to read 4, iclass 34, count 0 2006.259.08:01:21.51#ibcon#read 4, iclass 34, count 0 2006.259.08:01:21.51#ibcon#about to read 5, iclass 34, count 0 2006.259.08:01:21.51#ibcon#read 5, iclass 34, count 0 2006.259.08:01:21.51#ibcon#about to read 6, iclass 34, count 0 2006.259.08:01:21.51#ibcon#read 6, iclass 34, count 0 2006.259.08:01:21.51#ibcon#end of sib2, iclass 34, count 0 2006.259.08:01:21.51#ibcon#*mode == 0, iclass 34, count 0 2006.259.08:01:21.51#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.259.08:01:21.51#ibcon#[26=FRQ=08,852.99\r\n] 2006.259.08:01:21.51#ibcon#*before write, iclass 34, count 0 2006.259.08:01:21.51#ibcon#enter sib2, iclass 34, count 0 2006.259.08:01:21.51#ibcon#flushed, iclass 34, count 0 2006.259.08:01:21.51#ibcon#about to write, iclass 34, count 0 2006.259.08:01:21.51#ibcon#wrote, iclass 34, count 0 2006.259.08:01:21.51#ibcon#about to read 3, iclass 34, count 0 2006.259.08:01:21.55#ibcon#read 3, iclass 34, count 0 2006.259.08:01:21.55#ibcon#about to read 4, iclass 34, count 0 2006.259.08:01:21.55#ibcon#read 4, iclass 34, count 0 2006.259.08:01:21.55#ibcon#about to read 5, iclass 34, count 0 2006.259.08:01:21.55#ibcon#read 5, iclass 34, count 0 2006.259.08:01:21.55#ibcon#about to read 6, iclass 34, count 0 2006.259.08:01:21.55#ibcon#read 6, iclass 34, count 0 2006.259.08:01:21.55#ibcon#end of sib2, iclass 34, count 0 2006.259.08:01:21.55#ibcon#*after write, iclass 34, count 0 2006.259.08:01:21.55#ibcon#*before return 0, iclass 34, count 0 2006.259.08:01:21.55#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.259.08:01:21.55#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.259.08:01:21.55#ibcon#about to clear, iclass 34 cls_cnt 0 2006.259.08:01:21.55#ibcon#cleared, iclass 34 cls_cnt 0 2006.259.08:01:21.55$vc4f8/va=8,6 2006.259.08:01:21.55#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.259.08:01:21.55#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.259.08:01:21.55#ibcon#ireg 11 cls_cnt 2 2006.259.08:01:21.55#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.259.08:01:21.61#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.259.08:01:21.61#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.259.08:01:21.61#ibcon#enter wrdev, iclass 36, count 2 2006.259.08:01:21.61#ibcon#first serial, iclass 36, count 2 2006.259.08:01:21.61#ibcon#enter sib2, iclass 36, count 2 2006.259.08:01:21.61#ibcon#flushed, iclass 36, count 2 2006.259.08:01:21.61#ibcon#about to write, iclass 36, count 2 2006.259.08:01:21.61#ibcon#wrote, iclass 36, count 2 2006.259.08:01:21.61#ibcon#about to read 3, iclass 36, count 2 2006.259.08:01:21.64#ibcon#read 3, iclass 36, count 2 2006.259.08:01:21.64#ibcon#about to read 4, iclass 36, count 2 2006.259.08:01:21.64#ibcon#read 4, iclass 36, count 2 2006.259.08:01:21.64#ibcon#about to read 5, iclass 36, count 2 2006.259.08:01:21.64#ibcon#read 5, iclass 36, count 2 2006.259.08:01:21.64#ibcon#about to read 6, iclass 36, count 2 2006.259.08:01:21.64#ibcon#read 6, iclass 36, count 2 2006.259.08:01:21.64#ibcon#end of sib2, iclass 36, count 2 2006.259.08:01:21.64#ibcon#*mode == 0, iclass 36, count 2 2006.259.08:01:21.64#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.259.08:01:21.64#ibcon#[25=AT08-06\r\n] 2006.259.08:01:21.64#ibcon#*before write, iclass 36, count 2 2006.259.08:01:21.64#ibcon#enter sib2, iclass 36, count 2 2006.259.08:01:21.64#ibcon#flushed, iclass 36, count 2 2006.259.08:01:21.64#ibcon#about to write, iclass 36, count 2 2006.259.08:01:21.64#ibcon#wrote, iclass 36, count 2 2006.259.08:01:21.64#ibcon#about to read 3, iclass 36, count 2 2006.259.08:01:21.67#ibcon#read 3, iclass 36, count 2 2006.259.08:01:21.67#ibcon#about to read 4, iclass 36, count 2 2006.259.08:01:21.67#ibcon#read 4, iclass 36, count 2 2006.259.08:01:21.67#ibcon#about to read 5, iclass 36, count 2 2006.259.08:01:21.67#ibcon#read 5, iclass 36, count 2 2006.259.08:01:21.67#ibcon#about to read 6, iclass 36, count 2 2006.259.08:01:21.67#ibcon#read 6, iclass 36, count 2 2006.259.08:01:21.67#ibcon#end of sib2, iclass 36, count 2 2006.259.08:01:21.67#ibcon#*after write, iclass 36, count 2 2006.259.08:01:21.67#ibcon#*before return 0, iclass 36, count 2 2006.259.08:01:21.67#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.259.08:01:21.67#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.259.08:01:21.67#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.259.08:01:21.67#ibcon#ireg 7 cls_cnt 0 2006.259.08:01:21.67#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.259.08:01:21.79#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.259.08:01:21.79#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.259.08:01:21.79#ibcon#enter wrdev, iclass 36, count 0 2006.259.08:01:21.79#ibcon#first serial, iclass 36, count 0 2006.259.08:01:21.79#ibcon#enter sib2, iclass 36, count 0 2006.259.08:01:21.79#ibcon#flushed, iclass 36, count 0 2006.259.08:01:21.79#ibcon#about to write, iclass 36, count 0 2006.259.08:01:21.79#ibcon#wrote, iclass 36, count 0 2006.259.08:01:21.79#ibcon#about to read 3, iclass 36, count 0 2006.259.08:01:21.81#ibcon#read 3, iclass 36, count 0 2006.259.08:01:21.81#ibcon#about to read 4, iclass 36, count 0 2006.259.08:01:21.81#ibcon#read 4, iclass 36, count 0 2006.259.08:01:21.81#ibcon#about to read 5, iclass 36, count 0 2006.259.08:01:21.81#ibcon#read 5, iclass 36, count 0 2006.259.08:01:21.81#ibcon#about to read 6, iclass 36, count 0 2006.259.08:01:21.81#ibcon#read 6, iclass 36, count 0 2006.259.08:01:21.81#ibcon#end of sib2, iclass 36, count 0 2006.259.08:01:21.81#ibcon#*mode == 0, iclass 36, count 0 2006.259.08:01:21.81#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.259.08:01:21.81#ibcon#[25=USB\r\n] 2006.259.08:01:21.81#ibcon#*before write, iclass 36, count 0 2006.259.08:01:21.81#ibcon#enter sib2, iclass 36, count 0 2006.259.08:01:21.81#ibcon#flushed, iclass 36, count 0 2006.259.08:01:21.81#ibcon#about to write, iclass 36, count 0 2006.259.08:01:21.81#ibcon#wrote, iclass 36, count 0 2006.259.08:01:21.81#ibcon#about to read 3, iclass 36, count 0 2006.259.08:01:21.84#ibcon#read 3, iclass 36, count 0 2006.259.08:01:21.84#ibcon#about to read 4, iclass 36, count 0 2006.259.08:01:21.84#ibcon#read 4, iclass 36, count 0 2006.259.08:01:21.84#ibcon#about to read 5, iclass 36, count 0 2006.259.08:01:21.84#ibcon#read 5, iclass 36, count 0 2006.259.08:01:21.84#ibcon#about to read 6, iclass 36, count 0 2006.259.08:01:21.84#ibcon#read 6, iclass 36, count 0 2006.259.08:01:21.84#ibcon#end of sib2, iclass 36, count 0 2006.259.08:01:21.84#ibcon#*after write, iclass 36, count 0 2006.259.08:01:21.84#ibcon#*before return 0, iclass 36, count 0 2006.259.08:01:21.84#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.259.08:01:21.84#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.259.08:01:21.84#ibcon#about to clear, iclass 36 cls_cnt 0 2006.259.08:01:21.84#ibcon#cleared, iclass 36 cls_cnt 0 2006.259.08:01:21.84$vc4f8/vblo=1,632.99 2006.259.08:01:21.84#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.259.08:01:21.84#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.259.08:01:21.84#ibcon#ireg 17 cls_cnt 0 2006.259.08:01:21.84#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.259.08:01:21.84#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.259.08:01:21.84#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.259.08:01:21.84#ibcon#enter wrdev, iclass 38, count 0 2006.259.08:01:21.84#ibcon#first serial, iclass 38, count 0 2006.259.08:01:21.84#ibcon#enter sib2, iclass 38, count 0 2006.259.08:01:21.84#ibcon#flushed, iclass 38, count 0 2006.259.08:01:21.84#ibcon#about to write, iclass 38, count 0 2006.259.08:01:21.84#ibcon#wrote, iclass 38, count 0 2006.259.08:01:21.84#ibcon#about to read 3, iclass 38, count 0 2006.259.08:01:21.86#ibcon#read 3, iclass 38, count 0 2006.259.08:01:21.86#ibcon#about to read 4, iclass 38, count 0 2006.259.08:01:21.86#ibcon#read 4, iclass 38, count 0 2006.259.08:01:21.86#ibcon#about to read 5, iclass 38, count 0 2006.259.08:01:21.86#ibcon#read 5, iclass 38, count 0 2006.259.08:01:21.86#ibcon#about to read 6, iclass 38, count 0 2006.259.08:01:21.86#ibcon#read 6, iclass 38, count 0 2006.259.08:01:21.86#ibcon#end of sib2, iclass 38, count 0 2006.259.08:01:21.86#ibcon#*mode == 0, iclass 38, count 0 2006.259.08:01:21.86#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.259.08:01:21.86#ibcon#[28=FRQ=01,632.99\r\n] 2006.259.08:01:21.86#ibcon#*before write, iclass 38, count 0 2006.259.08:01:21.86#ibcon#enter sib2, iclass 38, count 0 2006.259.08:01:21.86#ibcon#flushed, iclass 38, count 0 2006.259.08:01:21.86#ibcon#about to write, iclass 38, count 0 2006.259.08:01:21.86#ibcon#wrote, iclass 38, count 0 2006.259.08:01:21.86#ibcon#about to read 3, iclass 38, count 0 2006.259.08:01:21.90#ibcon#read 3, iclass 38, count 0 2006.259.08:01:21.90#ibcon#about to read 4, iclass 38, count 0 2006.259.08:01:21.90#ibcon#read 4, iclass 38, count 0 2006.259.08:01:21.90#ibcon#about to read 5, iclass 38, count 0 2006.259.08:01:21.90#ibcon#read 5, iclass 38, count 0 2006.259.08:01:21.90#ibcon#about to read 6, iclass 38, count 0 2006.259.08:01:21.90#ibcon#read 6, iclass 38, count 0 2006.259.08:01:21.90#ibcon#end of sib2, iclass 38, count 0 2006.259.08:01:21.90#ibcon#*after write, iclass 38, count 0 2006.259.08:01:21.90#ibcon#*before return 0, iclass 38, count 0 2006.259.08:01:21.90#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.259.08:01:21.90#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.259.08:01:21.90#ibcon#about to clear, iclass 38 cls_cnt 0 2006.259.08:01:21.90#ibcon#cleared, iclass 38 cls_cnt 0 2006.259.08:01:21.90$vc4f8/vb=1,4 2006.259.08:01:21.90#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.259.08:01:21.90#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.259.08:01:21.90#ibcon#ireg 11 cls_cnt 2 2006.259.08:01:21.90#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.259.08:01:21.90#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.259.08:01:21.90#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.259.08:01:21.90#ibcon#enter wrdev, iclass 40, count 2 2006.259.08:01:21.90#ibcon#first serial, iclass 40, count 2 2006.259.08:01:21.90#ibcon#enter sib2, iclass 40, count 2 2006.259.08:01:21.90#ibcon#flushed, iclass 40, count 2 2006.259.08:01:21.90#ibcon#about to write, iclass 40, count 2 2006.259.08:01:21.90#ibcon#wrote, iclass 40, count 2 2006.259.08:01:21.90#ibcon#about to read 3, iclass 40, count 2 2006.259.08:01:21.92#ibcon#read 3, iclass 40, count 2 2006.259.08:01:21.92#ibcon#about to read 4, iclass 40, count 2 2006.259.08:01:21.92#ibcon#read 4, iclass 40, count 2 2006.259.08:01:21.92#ibcon#about to read 5, iclass 40, count 2 2006.259.08:01:21.92#ibcon#read 5, iclass 40, count 2 2006.259.08:01:21.92#ibcon#about to read 6, iclass 40, count 2 2006.259.08:01:21.92#ibcon#read 6, iclass 40, count 2 2006.259.08:01:21.92#ibcon#end of sib2, iclass 40, count 2 2006.259.08:01:21.92#ibcon#*mode == 0, iclass 40, count 2 2006.259.08:01:21.92#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.259.08:01:21.92#ibcon#[27=AT01-04\r\n] 2006.259.08:01:21.92#ibcon#*before write, iclass 40, count 2 2006.259.08:01:21.92#ibcon#enter sib2, iclass 40, count 2 2006.259.08:01:21.92#ibcon#flushed, iclass 40, count 2 2006.259.08:01:21.92#ibcon#about to write, iclass 40, count 2 2006.259.08:01:21.92#ibcon#wrote, iclass 40, count 2 2006.259.08:01:21.92#ibcon#about to read 3, iclass 40, count 2 2006.259.08:01:21.95#ibcon#read 3, iclass 40, count 2 2006.259.08:01:21.95#ibcon#about to read 4, iclass 40, count 2 2006.259.08:01:21.95#ibcon#read 4, iclass 40, count 2 2006.259.08:01:21.95#ibcon#about to read 5, iclass 40, count 2 2006.259.08:01:21.95#ibcon#read 5, iclass 40, count 2 2006.259.08:01:21.95#ibcon#about to read 6, iclass 40, count 2 2006.259.08:01:21.95#ibcon#read 6, iclass 40, count 2 2006.259.08:01:21.95#ibcon#end of sib2, iclass 40, count 2 2006.259.08:01:21.95#ibcon#*after write, iclass 40, count 2 2006.259.08:01:21.95#ibcon#*before return 0, iclass 40, count 2 2006.259.08:01:21.95#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.259.08:01:21.95#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.259.08:01:21.95#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.259.08:01:21.95#ibcon#ireg 7 cls_cnt 0 2006.259.08:01:21.95#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.259.08:01:22.07#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.259.08:01:22.07#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.259.08:01:22.07#ibcon#enter wrdev, iclass 40, count 0 2006.259.08:01:22.07#ibcon#first serial, iclass 40, count 0 2006.259.08:01:22.07#ibcon#enter sib2, iclass 40, count 0 2006.259.08:01:22.07#ibcon#flushed, iclass 40, count 0 2006.259.08:01:22.07#ibcon#about to write, iclass 40, count 0 2006.259.08:01:22.07#ibcon#wrote, iclass 40, count 0 2006.259.08:01:22.07#ibcon#about to read 3, iclass 40, count 0 2006.259.08:01:22.09#ibcon#read 3, iclass 40, count 0 2006.259.08:01:22.09#ibcon#about to read 4, iclass 40, count 0 2006.259.08:01:22.09#ibcon#read 4, iclass 40, count 0 2006.259.08:01:22.09#ibcon#about to read 5, iclass 40, count 0 2006.259.08:01:22.09#ibcon#read 5, iclass 40, count 0 2006.259.08:01:22.09#ibcon#about to read 6, iclass 40, count 0 2006.259.08:01:22.09#ibcon#read 6, iclass 40, count 0 2006.259.08:01:22.09#ibcon#end of sib2, iclass 40, count 0 2006.259.08:01:22.09#ibcon#*mode == 0, iclass 40, count 0 2006.259.08:01:22.09#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.259.08:01:22.09#ibcon#[27=USB\r\n] 2006.259.08:01:22.09#ibcon#*before write, iclass 40, count 0 2006.259.08:01:22.09#ibcon#enter sib2, iclass 40, count 0 2006.259.08:01:22.09#ibcon#flushed, iclass 40, count 0 2006.259.08:01:22.09#ibcon#about to write, iclass 40, count 0 2006.259.08:01:22.09#ibcon#wrote, iclass 40, count 0 2006.259.08:01:22.09#ibcon#about to read 3, iclass 40, count 0 2006.259.08:01:22.12#ibcon#read 3, iclass 40, count 0 2006.259.08:01:22.12#ibcon#about to read 4, iclass 40, count 0 2006.259.08:01:22.12#ibcon#read 4, iclass 40, count 0 2006.259.08:01:22.12#ibcon#about to read 5, iclass 40, count 0 2006.259.08:01:22.12#ibcon#read 5, iclass 40, count 0 2006.259.08:01:22.12#ibcon#about to read 6, iclass 40, count 0 2006.259.08:01:22.12#ibcon#read 6, iclass 40, count 0 2006.259.08:01:22.12#ibcon#end of sib2, iclass 40, count 0 2006.259.08:01:22.12#ibcon#*after write, iclass 40, count 0 2006.259.08:01:22.12#ibcon#*before return 0, iclass 40, count 0 2006.259.08:01:22.12#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.259.08:01:22.12#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.259.08:01:22.12#ibcon#about to clear, iclass 40 cls_cnt 0 2006.259.08:01:22.12#ibcon#cleared, iclass 40 cls_cnt 0 2006.259.08:01:22.12$vc4f8/vblo=2,640.99 2006.259.08:01:22.12#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.259.08:01:22.12#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.259.08:01:22.12#ibcon#ireg 17 cls_cnt 0 2006.259.08:01:22.12#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.259.08:01:22.12#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.259.08:01:22.12#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.259.08:01:22.12#ibcon#enter wrdev, iclass 4, count 0 2006.259.08:01:22.12#ibcon#first serial, iclass 4, count 0 2006.259.08:01:22.12#ibcon#enter sib2, iclass 4, count 0 2006.259.08:01:22.12#ibcon#flushed, iclass 4, count 0 2006.259.08:01:22.12#ibcon#about to write, iclass 4, count 0 2006.259.08:01:22.12#ibcon#wrote, iclass 4, count 0 2006.259.08:01:22.12#ibcon#about to read 3, iclass 4, count 0 2006.259.08:01:22.14#ibcon#read 3, iclass 4, count 0 2006.259.08:01:22.14#ibcon#about to read 4, iclass 4, count 0 2006.259.08:01:22.14#ibcon#read 4, iclass 4, count 0 2006.259.08:01:22.14#ibcon#about to read 5, iclass 4, count 0 2006.259.08:01:22.14#ibcon#read 5, iclass 4, count 0 2006.259.08:01:22.14#ibcon#about to read 6, iclass 4, count 0 2006.259.08:01:22.14#ibcon#read 6, iclass 4, count 0 2006.259.08:01:22.14#ibcon#end of sib2, iclass 4, count 0 2006.259.08:01:22.14#ibcon#*mode == 0, iclass 4, count 0 2006.259.08:01:22.14#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.259.08:01:22.14#ibcon#[28=FRQ=02,640.99\r\n] 2006.259.08:01:22.14#ibcon#*before write, iclass 4, count 0 2006.259.08:01:22.14#ibcon#enter sib2, iclass 4, count 0 2006.259.08:01:22.14#ibcon#flushed, iclass 4, count 0 2006.259.08:01:22.14#ibcon#about to write, iclass 4, count 0 2006.259.08:01:22.14#ibcon#wrote, iclass 4, count 0 2006.259.08:01:22.14#ibcon#about to read 3, iclass 4, count 0 2006.259.08:01:22.18#ibcon#read 3, iclass 4, count 0 2006.259.08:01:22.18#ibcon#about to read 4, iclass 4, count 0 2006.259.08:01:22.18#ibcon#read 4, iclass 4, count 0 2006.259.08:01:22.18#ibcon#about to read 5, iclass 4, count 0 2006.259.08:01:22.18#ibcon#read 5, iclass 4, count 0 2006.259.08:01:22.18#ibcon#about to read 6, iclass 4, count 0 2006.259.08:01:22.18#ibcon#read 6, iclass 4, count 0 2006.259.08:01:22.18#ibcon#end of sib2, iclass 4, count 0 2006.259.08:01:22.18#ibcon#*after write, iclass 4, count 0 2006.259.08:01:22.18#ibcon#*before return 0, iclass 4, count 0 2006.259.08:01:22.18#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.259.08:01:22.18#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.259.08:01:22.18#ibcon#about to clear, iclass 4 cls_cnt 0 2006.259.08:01:22.18#ibcon#cleared, iclass 4 cls_cnt 0 2006.259.08:01:22.18$vc4f8/vb=2,5 2006.259.08:01:22.18#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.259.08:01:22.18#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.259.08:01:22.18#ibcon#ireg 11 cls_cnt 2 2006.259.08:01:22.18#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.259.08:01:22.24#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.259.08:01:22.24#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.259.08:01:22.24#ibcon#enter wrdev, iclass 6, count 2 2006.259.08:01:22.24#ibcon#first serial, iclass 6, count 2 2006.259.08:01:22.24#ibcon#enter sib2, iclass 6, count 2 2006.259.08:01:22.24#ibcon#flushed, iclass 6, count 2 2006.259.08:01:22.24#ibcon#about to write, iclass 6, count 2 2006.259.08:01:22.24#ibcon#wrote, iclass 6, count 2 2006.259.08:01:22.24#ibcon#about to read 3, iclass 6, count 2 2006.259.08:01:22.26#ibcon#read 3, iclass 6, count 2 2006.259.08:01:22.26#ibcon#about to read 4, iclass 6, count 2 2006.259.08:01:22.26#ibcon#read 4, iclass 6, count 2 2006.259.08:01:22.26#ibcon#about to read 5, iclass 6, count 2 2006.259.08:01:22.26#ibcon#read 5, iclass 6, count 2 2006.259.08:01:22.26#ibcon#about to read 6, iclass 6, count 2 2006.259.08:01:22.26#ibcon#read 6, iclass 6, count 2 2006.259.08:01:22.26#ibcon#end of sib2, iclass 6, count 2 2006.259.08:01:22.26#ibcon#*mode == 0, iclass 6, count 2 2006.259.08:01:22.26#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.259.08:01:22.26#ibcon#[27=AT02-05\r\n] 2006.259.08:01:22.26#ibcon#*before write, iclass 6, count 2 2006.259.08:01:22.26#ibcon#enter sib2, iclass 6, count 2 2006.259.08:01:22.26#ibcon#flushed, iclass 6, count 2 2006.259.08:01:22.26#ibcon#about to write, iclass 6, count 2 2006.259.08:01:22.26#ibcon#wrote, iclass 6, count 2 2006.259.08:01:22.26#ibcon#about to read 3, iclass 6, count 2 2006.259.08:01:22.29#ibcon#read 3, iclass 6, count 2 2006.259.08:01:22.29#ibcon#about to read 4, iclass 6, count 2 2006.259.08:01:22.29#ibcon#read 4, iclass 6, count 2 2006.259.08:01:22.29#ibcon#about to read 5, iclass 6, count 2 2006.259.08:01:22.29#ibcon#read 5, iclass 6, count 2 2006.259.08:01:22.29#ibcon#about to read 6, iclass 6, count 2 2006.259.08:01:22.29#ibcon#read 6, iclass 6, count 2 2006.259.08:01:22.29#ibcon#end of sib2, iclass 6, count 2 2006.259.08:01:22.29#ibcon#*after write, iclass 6, count 2 2006.259.08:01:22.29#ibcon#*before return 0, iclass 6, count 2 2006.259.08:01:22.29#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.259.08:01:22.29#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.259.08:01:22.29#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.259.08:01:22.29#ibcon#ireg 7 cls_cnt 0 2006.259.08:01:22.29#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.259.08:01:22.41#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.259.08:01:22.41#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.259.08:01:22.41#ibcon#enter wrdev, iclass 6, count 0 2006.259.08:01:22.41#ibcon#first serial, iclass 6, count 0 2006.259.08:01:22.41#ibcon#enter sib2, iclass 6, count 0 2006.259.08:01:22.41#ibcon#flushed, iclass 6, count 0 2006.259.08:01:22.41#ibcon#about to write, iclass 6, count 0 2006.259.08:01:22.41#ibcon#wrote, iclass 6, count 0 2006.259.08:01:22.41#ibcon#about to read 3, iclass 6, count 0 2006.259.08:01:22.43#ibcon#read 3, iclass 6, count 0 2006.259.08:01:22.43#ibcon#about to read 4, iclass 6, count 0 2006.259.08:01:22.43#ibcon#read 4, iclass 6, count 0 2006.259.08:01:22.43#ibcon#about to read 5, iclass 6, count 0 2006.259.08:01:22.43#ibcon#read 5, iclass 6, count 0 2006.259.08:01:22.43#ibcon#about to read 6, iclass 6, count 0 2006.259.08:01:22.43#ibcon#read 6, iclass 6, count 0 2006.259.08:01:22.43#ibcon#end of sib2, iclass 6, count 0 2006.259.08:01:22.43#ibcon#*mode == 0, iclass 6, count 0 2006.259.08:01:22.43#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.259.08:01:22.43#ibcon#[27=USB\r\n] 2006.259.08:01:22.43#ibcon#*before write, iclass 6, count 0 2006.259.08:01:22.43#ibcon#enter sib2, iclass 6, count 0 2006.259.08:01:22.43#ibcon#flushed, iclass 6, count 0 2006.259.08:01:22.43#ibcon#about to write, iclass 6, count 0 2006.259.08:01:22.43#ibcon#wrote, iclass 6, count 0 2006.259.08:01:22.43#ibcon#about to read 3, iclass 6, count 0 2006.259.08:01:22.46#ibcon#read 3, iclass 6, count 0 2006.259.08:01:22.46#ibcon#about to read 4, iclass 6, count 0 2006.259.08:01:22.46#ibcon#read 4, iclass 6, count 0 2006.259.08:01:22.46#ibcon#about to read 5, iclass 6, count 0 2006.259.08:01:22.46#ibcon#read 5, iclass 6, count 0 2006.259.08:01:22.46#ibcon#about to read 6, iclass 6, count 0 2006.259.08:01:22.46#ibcon#read 6, iclass 6, count 0 2006.259.08:01:22.46#ibcon#end of sib2, iclass 6, count 0 2006.259.08:01:22.46#ibcon#*after write, iclass 6, count 0 2006.259.08:01:22.46#ibcon#*before return 0, iclass 6, count 0 2006.259.08:01:22.46#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.259.08:01:22.46#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.259.08:01:22.46#ibcon#about to clear, iclass 6 cls_cnt 0 2006.259.08:01:22.46#ibcon#cleared, iclass 6 cls_cnt 0 2006.259.08:01:22.46$vc4f8/vblo=3,656.99 2006.259.08:01:22.46#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.259.08:01:22.46#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.259.08:01:22.46#ibcon#ireg 17 cls_cnt 0 2006.259.08:01:22.46#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.259.08:01:22.46#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.259.08:01:22.46#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.259.08:01:22.46#ibcon#enter wrdev, iclass 10, count 0 2006.259.08:01:22.46#ibcon#first serial, iclass 10, count 0 2006.259.08:01:22.46#ibcon#enter sib2, iclass 10, count 0 2006.259.08:01:22.46#ibcon#flushed, iclass 10, count 0 2006.259.08:01:22.46#ibcon#about to write, iclass 10, count 0 2006.259.08:01:22.46#ibcon#wrote, iclass 10, count 0 2006.259.08:01:22.46#ibcon#about to read 3, iclass 10, count 0 2006.259.08:01:22.48#ibcon#read 3, iclass 10, count 0 2006.259.08:01:22.48#ibcon#about to read 4, iclass 10, count 0 2006.259.08:01:22.48#ibcon#read 4, iclass 10, count 0 2006.259.08:01:22.48#ibcon#about to read 5, iclass 10, count 0 2006.259.08:01:22.48#ibcon#read 5, iclass 10, count 0 2006.259.08:01:22.48#ibcon#about to read 6, iclass 10, count 0 2006.259.08:01:22.48#ibcon#read 6, iclass 10, count 0 2006.259.08:01:22.48#ibcon#end of sib2, iclass 10, count 0 2006.259.08:01:22.48#ibcon#*mode == 0, iclass 10, count 0 2006.259.08:01:22.48#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.259.08:01:22.48#ibcon#[28=FRQ=03,656.99\r\n] 2006.259.08:01:22.48#ibcon#*before write, iclass 10, count 0 2006.259.08:01:22.48#ibcon#enter sib2, iclass 10, count 0 2006.259.08:01:22.48#ibcon#flushed, iclass 10, count 0 2006.259.08:01:22.48#ibcon#about to write, iclass 10, count 0 2006.259.08:01:22.48#ibcon#wrote, iclass 10, count 0 2006.259.08:01:22.48#ibcon#about to read 3, iclass 10, count 0 2006.259.08:01:22.52#ibcon#read 3, iclass 10, count 0 2006.259.08:01:22.52#ibcon#about to read 4, iclass 10, count 0 2006.259.08:01:22.52#ibcon#read 4, iclass 10, count 0 2006.259.08:01:22.52#ibcon#about to read 5, iclass 10, count 0 2006.259.08:01:22.52#ibcon#read 5, iclass 10, count 0 2006.259.08:01:22.52#ibcon#about to read 6, iclass 10, count 0 2006.259.08:01:22.52#ibcon#read 6, iclass 10, count 0 2006.259.08:01:22.52#ibcon#end of sib2, iclass 10, count 0 2006.259.08:01:22.52#ibcon#*after write, iclass 10, count 0 2006.259.08:01:22.52#ibcon#*before return 0, iclass 10, count 0 2006.259.08:01:22.52#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.259.08:01:22.52#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.259.08:01:22.52#ibcon#about to clear, iclass 10 cls_cnt 0 2006.259.08:01:22.52#ibcon#cleared, iclass 10 cls_cnt 0 2006.259.08:01:22.52$vc4f8/vb=3,4 2006.259.08:01:22.52#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.259.08:01:22.52#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.259.08:01:22.52#ibcon#ireg 11 cls_cnt 2 2006.259.08:01:22.52#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.259.08:01:22.58#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.259.08:01:22.58#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.259.08:01:22.58#ibcon#enter wrdev, iclass 12, count 2 2006.259.08:01:22.58#ibcon#first serial, iclass 12, count 2 2006.259.08:01:22.58#ibcon#enter sib2, iclass 12, count 2 2006.259.08:01:22.58#ibcon#flushed, iclass 12, count 2 2006.259.08:01:22.58#ibcon#about to write, iclass 12, count 2 2006.259.08:01:22.58#ibcon#wrote, iclass 12, count 2 2006.259.08:01:22.58#ibcon#about to read 3, iclass 12, count 2 2006.259.08:01:22.60#ibcon#read 3, iclass 12, count 2 2006.259.08:01:22.60#ibcon#about to read 4, iclass 12, count 2 2006.259.08:01:22.60#ibcon#read 4, iclass 12, count 2 2006.259.08:01:22.60#ibcon#about to read 5, iclass 12, count 2 2006.259.08:01:22.60#ibcon#read 5, iclass 12, count 2 2006.259.08:01:22.60#ibcon#about to read 6, iclass 12, count 2 2006.259.08:01:22.60#ibcon#read 6, iclass 12, count 2 2006.259.08:01:22.60#ibcon#end of sib2, iclass 12, count 2 2006.259.08:01:22.60#ibcon#*mode == 0, iclass 12, count 2 2006.259.08:01:22.60#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.259.08:01:22.60#ibcon#[27=AT03-04\r\n] 2006.259.08:01:22.60#ibcon#*before write, iclass 12, count 2 2006.259.08:01:22.60#ibcon#enter sib2, iclass 12, count 2 2006.259.08:01:22.60#ibcon#flushed, iclass 12, count 2 2006.259.08:01:22.60#ibcon#about to write, iclass 12, count 2 2006.259.08:01:22.60#ibcon#wrote, iclass 12, count 2 2006.259.08:01:22.60#ibcon#about to read 3, iclass 12, count 2 2006.259.08:01:22.63#ibcon#read 3, iclass 12, count 2 2006.259.08:01:22.63#ibcon#about to read 4, iclass 12, count 2 2006.259.08:01:22.63#ibcon#read 4, iclass 12, count 2 2006.259.08:01:22.63#ibcon#about to read 5, iclass 12, count 2 2006.259.08:01:22.63#ibcon#read 5, iclass 12, count 2 2006.259.08:01:22.63#ibcon#about to read 6, iclass 12, count 2 2006.259.08:01:22.63#ibcon#read 6, iclass 12, count 2 2006.259.08:01:22.63#ibcon#end of sib2, iclass 12, count 2 2006.259.08:01:22.63#ibcon#*after write, iclass 12, count 2 2006.259.08:01:22.63#ibcon#*before return 0, iclass 12, count 2 2006.259.08:01:22.63#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.259.08:01:22.63#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.259.08:01:22.63#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.259.08:01:22.63#ibcon#ireg 7 cls_cnt 0 2006.259.08:01:22.63#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.259.08:01:22.75#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.259.08:01:22.75#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.259.08:01:22.75#ibcon#enter wrdev, iclass 12, count 0 2006.259.08:01:22.75#ibcon#first serial, iclass 12, count 0 2006.259.08:01:22.75#ibcon#enter sib2, iclass 12, count 0 2006.259.08:01:22.75#ibcon#flushed, iclass 12, count 0 2006.259.08:01:22.75#ibcon#about to write, iclass 12, count 0 2006.259.08:01:22.75#ibcon#wrote, iclass 12, count 0 2006.259.08:01:22.75#ibcon#about to read 3, iclass 12, count 0 2006.259.08:01:22.77#ibcon#read 3, iclass 12, count 0 2006.259.08:01:22.77#ibcon#about to read 4, iclass 12, count 0 2006.259.08:01:22.77#ibcon#read 4, iclass 12, count 0 2006.259.08:01:22.77#ibcon#about to read 5, iclass 12, count 0 2006.259.08:01:22.77#ibcon#read 5, iclass 12, count 0 2006.259.08:01:22.77#ibcon#about to read 6, iclass 12, count 0 2006.259.08:01:22.77#ibcon#read 6, iclass 12, count 0 2006.259.08:01:22.77#ibcon#end of sib2, iclass 12, count 0 2006.259.08:01:22.77#ibcon#*mode == 0, iclass 12, count 0 2006.259.08:01:22.77#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.259.08:01:22.77#ibcon#[27=USB\r\n] 2006.259.08:01:22.77#ibcon#*before write, iclass 12, count 0 2006.259.08:01:22.77#ibcon#enter sib2, iclass 12, count 0 2006.259.08:01:22.77#ibcon#flushed, iclass 12, count 0 2006.259.08:01:22.77#ibcon#about to write, iclass 12, count 0 2006.259.08:01:22.77#ibcon#wrote, iclass 12, count 0 2006.259.08:01:22.77#ibcon#about to read 3, iclass 12, count 0 2006.259.08:01:22.80#ibcon#read 3, iclass 12, count 0 2006.259.08:01:22.80#ibcon#about to read 4, iclass 12, count 0 2006.259.08:01:22.80#ibcon#read 4, iclass 12, count 0 2006.259.08:01:22.80#ibcon#about to read 5, iclass 12, count 0 2006.259.08:01:22.80#ibcon#read 5, iclass 12, count 0 2006.259.08:01:22.80#ibcon#about to read 6, iclass 12, count 0 2006.259.08:01:22.80#ibcon#read 6, iclass 12, count 0 2006.259.08:01:22.80#ibcon#end of sib2, iclass 12, count 0 2006.259.08:01:22.80#ibcon#*after write, iclass 12, count 0 2006.259.08:01:22.80#ibcon#*before return 0, iclass 12, count 0 2006.259.08:01:22.80#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.259.08:01:22.80#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.259.08:01:22.80#ibcon#about to clear, iclass 12 cls_cnt 0 2006.259.08:01:22.80#ibcon#cleared, iclass 12 cls_cnt 0 2006.259.08:01:22.80$vc4f8/vblo=4,712.99 2006.259.08:01:22.80#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.259.08:01:22.80#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.259.08:01:22.80#ibcon#ireg 17 cls_cnt 0 2006.259.08:01:22.80#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.259.08:01:22.80#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.259.08:01:22.80#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.259.08:01:22.80#ibcon#enter wrdev, iclass 14, count 0 2006.259.08:01:22.80#ibcon#first serial, iclass 14, count 0 2006.259.08:01:22.80#ibcon#enter sib2, iclass 14, count 0 2006.259.08:01:22.80#ibcon#flushed, iclass 14, count 0 2006.259.08:01:22.80#ibcon#about to write, iclass 14, count 0 2006.259.08:01:22.80#ibcon#wrote, iclass 14, count 0 2006.259.08:01:22.80#ibcon#about to read 3, iclass 14, count 0 2006.259.08:01:22.82#ibcon#read 3, iclass 14, count 0 2006.259.08:01:22.82#ibcon#about to read 4, iclass 14, count 0 2006.259.08:01:22.82#ibcon#read 4, iclass 14, count 0 2006.259.08:01:22.82#ibcon#about to read 5, iclass 14, count 0 2006.259.08:01:22.82#ibcon#read 5, iclass 14, count 0 2006.259.08:01:22.82#ibcon#about to read 6, iclass 14, count 0 2006.259.08:01:22.82#ibcon#read 6, iclass 14, count 0 2006.259.08:01:22.82#ibcon#end of sib2, iclass 14, count 0 2006.259.08:01:22.82#ibcon#*mode == 0, iclass 14, count 0 2006.259.08:01:22.82#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.259.08:01:22.82#ibcon#[28=FRQ=04,712.99\r\n] 2006.259.08:01:22.82#ibcon#*before write, iclass 14, count 0 2006.259.08:01:22.82#ibcon#enter sib2, iclass 14, count 0 2006.259.08:01:22.82#ibcon#flushed, iclass 14, count 0 2006.259.08:01:22.82#ibcon#about to write, iclass 14, count 0 2006.259.08:01:22.82#ibcon#wrote, iclass 14, count 0 2006.259.08:01:22.82#ibcon#about to read 3, iclass 14, count 0 2006.259.08:01:22.86#ibcon#read 3, iclass 14, count 0 2006.259.08:01:22.86#ibcon#about to read 4, iclass 14, count 0 2006.259.08:01:22.86#ibcon#read 4, iclass 14, count 0 2006.259.08:01:22.86#ibcon#about to read 5, iclass 14, count 0 2006.259.08:01:22.86#ibcon#read 5, iclass 14, count 0 2006.259.08:01:22.86#ibcon#about to read 6, iclass 14, count 0 2006.259.08:01:22.86#ibcon#read 6, iclass 14, count 0 2006.259.08:01:22.86#ibcon#end of sib2, iclass 14, count 0 2006.259.08:01:22.86#ibcon#*after write, iclass 14, count 0 2006.259.08:01:22.86#ibcon#*before return 0, iclass 14, count 0 2006.259.08:01:22.86#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.259.08:01:22.86#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.259.08:01:22.86#ibcon#about to clear, iclass 14 cls_cnt 0 2006.259.08:01:22.86#ibcon#cleared, iclass 14 cls_cnt 0 2006.259.08:01:22.86$vc4f8/vb=4,5 2006.259.08:01:22.86#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.259.08:01:22.86#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.259.08:01:22.86#ibcon#ireg 11 cls_cnt 2 2006.259.08:01:22.86#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.259.08:01:22.92#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.259.08:01:22.92#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.259.08:01:22.92#ibcon#enter wrdev, iclass 16, count 2 2006.259.08:01:22.92#ibcon#first serial, iclass 16, count 2 2006.259.08:01:22.92#ibcon#enter sib2, iclass 16, count 2 2006.259.08:01:22.92#ibcon#flushed, iclass 16, count 2 2006.259.08:01:22.92#ibcon#about to write, iclass 16, count 2 2006.259.08:01:22.92#ibcon#wrote, iclass 16, count 2 2006.259.08:01:22.92#ibcon#about to read 3, iclass 16, count 2 2006.259.08:01:22.94#ibcon#read 3, iclass 16, count 2 2006.259.08:01:22.94#ibcon#about to read 4, iclass 16, count 2 2006.259.08:01:22.94#ibcon#read 4, iclass 16, count 2 2006.259.08:01:22.94#ibcon#about to read 5, iclass 16, count 2 2006.259.08:01:22.94#ibcon#read 5, iclass 16, count 2 2006.259.08:01:22.94#ibcon#about to read 6, iclass 16, count 2 2006.259.08:01:22.94#ibcon#read 6, iclass 16, count 2 2006.259.08:01:22.94#ibcon#end of sib2, iclass 16, count 2 2006.259.08:01:22.94#ibcon#*mode == 0, iclass 16, count 2 2006.259.08:01:22.94#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.259.08:01:22.94#ibcon#[27=AT04-05\r\n] 2006.259.08:01:22.94#ibcon#*before write, iclass 16, count 2 2006.259.08:01:22.94#ibcon#enter sib2, iclass 16, count 2 2006.259.08:01:22.94#ibcon#flushed, iclass 16, count 2 2006.259.08:01:22.94#ibcon#about to write, iclass 16, count 2 2006.259.08:01:22.94#ibcon#wrote, iclass 16, count 2 2006.259.08:01:22.94#ibcon#about to read 3, iclass 16, count 2 2006.259.08:01:22.97#ibcon#read 3, iclass 16, count 2 2006.259.08:01:22.97#ibcon#about to read 4, iclass 16, count 2 2006.259.08:01:22.97#ibcon#read 4, iclass 16, count 2 2006.259.08:01:22.97#ibcon#about to read 5, iclass 16, count 2 2006.259.08:01:22.97#ibcon#read 5, iclass 16, count 2 2006.259.08:01:22.97#ibcon#about to read 6, iclass 16, count 2 2006.259.08:01:22.97#ibcon#read 6, iclass 16, count 2 2006.259.08:01:22.97#ibcon#end of sib2, iclass 16, count 2 2006.259.08:01:22.97#ibcon#*after write, iclass 16, count 2 2006.259.08:01:22.97#ibcon#*before return 0, iclass 16, count 2 2006.259.08:01:22.97#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.259.08:01:22.97#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.259.08:01:22.97#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.259.08:01:22.97#ibcon#ireg 7 cls_cnt 0 2006.259.08:01:22.97#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.259.08:01:23.09#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.259.08:01:23.09#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.259.08:01:23.09#ibcon#enter wrdev, iclass 16, count 0 2006.259.08:01:23.09#ibcon#first serial, iclass 16, count 0 2006.259.08:01:23.09#ibcon#enter sib2, iclass 16, count 0 2006.259.08:01:23.09#ibcon#flushed, iclass 16, count 0 2006.259.08:01:23.09#ibcon#about to write, iclass 16, count 0 2006.259.08:01:23.09#ibcon#wrote, iclass 16, count 0 2006.259.08:01:23.09#ibcon#about to read 3, iclass 16, count 0 2006.259.08:01:23.11#ibcon#read 3, iclass 16, count 0 2006.259.08:01:23.11#ibcon#about to read 4, iclass 16, count 0 2006.259.08:01:23.11#ibcon#read 4, iclass 16, count 0 2006.259.08:01:23.11#ibcon#about to read 5, iclass 16, count 0 2006.259.08:01:23.11#ibcon#read 5, iclass 16, count 0 2006.259.08:01:23.11#ibcon#about to read 6, iclass 16, count 0 2006.259.08:01:23.11#ibcon#read 6, iclass 16, count 0 2006.259.08:01:23.11#ibcon#end of sib2, iclass 16, count 0 2006.259.08:01:23.11#ibcon#*mode == 0, iclass 16, count 0 2006.259.08:01:23.11#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.259.08:01:23.11#ibcon#[27=USB\r\n] 2006.259.08:01:23.11#ibcon#*before write, iclass 16, count 0 2006.259.08:01:23.11#ibcon#enter sib2, iclass 16, count 0 2006.259.08:01:23.11#ibcon#flushed, iclass 16, count 0 2006.259.08:01:23.11#ibcon#about to write, iclass 16, count 0 2006.259.08:01:23.11#ibcon#wrote, iclass 16, count 0 2006.259.08:01:23.11#ibcon#about to read 3, iclass 16, count 0 2006.259.08:01:23.14#ibcon#read 3, iclass 16, count 0 2006.259.08:01:23.14#ibcon#about to read 4, iclass 16, count 0 2006.259.08:01:23.14#ibcon#read 4, iclass 16, count 0 2006.259.08:01:23.14#ibcon#about to read 5, iclass 16, count 0 2006.259.08:01:23.14#ibcon#read 5, iclass 16, count 0 2006.259.08:01:23.14#ibcon#about to read 6, iclass 16, count 0 2006.259.08:01:23.14#ibcon#read 6, iclass 16, count 0 2006.259.08:01:23.14#ibcon#end of sib2, iclass 16, count 0 2006.259.08:01:23.14#ibcon#*after write, iclass 16, count 0 2006.259.08:01:23.14#ibcon#*before return 0, iclass 16, count 0 2006.259.08:01:23.14#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.259.08:01:23.14#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.259.08:01:23.14#ibcon#about to clear, iclass 16 cls_cnt 0 2006.259.08:01:23.14#ibcon#cleared, iclass 16 cls_cnt 0 2006.259.08:01:23.14$vc4f8/vblo=5,744.99 2006.259.08:01:23.14#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.259.08:01:23.14#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.259.08:01:23.14#ibcon#ireg 17 cls_cnt 0 2006.259.08:01:23.14#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.259.08:01:23.14#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.259.08:01:23.14#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.259.08:01:23.14#ibcon#enter wrdev, iclass 18, count 0 2006.259.08:01:23.14#ibcon#first serial, iclass 18, count 0 2006.259.08:01:23.14#ibcon#enter sib2, iclass 18, count 0 2006.259.08:01:23.14#ibcon#flushed, iclass 18, count 0 2006.259.08:01:23.14#ibcon#about to write, iclass 18, count 0 2006.259.08:01:23.14#ibcon#wrote, iclass 18, count 0 2006.259.08:01:23.14#ibcon#about to read 3, iclass 18, count 0 2006.259.08:01:23.16#ibcon#read 3, iclass 18, count 0 2006.259.08:01:23.16#ibcon#about to read 4, iclass 18, count 0 2006.259.08:01:23.16#ibcon#read 4, iclass 18, count 0 2006.259.08:01:23.16#ibcon#about to read 5, iclass 18, count 0 2006.259.08:01:23.16#ibcon#read 5, iclass 18, count 0 2006.259.08:01:23.16#ibcon#about to read 6, iclass 18, count 0 2006.259.08:01:23.16#ibcon#read 6, iclass 18, count 0 2006.259.08:01:23.16#ibcon#end of sib2, iclass 18, count 0 2006.259.08:01:23.16#ibcon#*mode == 0, iclass 18, count 0 2006.259.08:01:23.16#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.259.08:01:23.16#ibcon#[28=FRQ=05,744.99\r\n] 2006.259.08:01:23.16#ibcon#*before write, iclass 18, count 0 2006.259.08:01:23.16#ibcon#enter sib2, iclass 18, count 0 2006.259.08:01:23.16#ibcon#flushed, iclass 18, count 0 2006.259.08:01:23.16#ibcon#about to write, iclass 18, count 0 2006.259.08:01:23.16#ibcon#wrote, iclass 18, count 0 2006.259.08:01:23.16#ibcon#about to read 3, iclass 18, count 0 2006.259.08:01:23.20#ibcon#read 3, iclass 18, count 0 2006.259.08:01:23.20#ibcon#about to read 4, iclass 18, count 0 2006.259.08:01:23.20#ibcon#read 4, iclass 18, count 0 2006.259.08:01:23.20#ibcon#about to read 5, iclass 18, count 0 2006.259.08:01:23.20#ibcon#read 5, iclass 18, count 0 2006.259.08:01:23.20#ibcon#about to read 6, iclass 18, count 0 2006.259.08:01:23.20#ibcon#read 6, iclass 18, count 0 2006.259.08:01:23.20#ibcon#end of sib2, iclass 18, count 0 2006.259.08:01:23.20#ibcon#*after write, iclass 18, count 0 2006.259.08:01:23.20#ibcon#*before return 0, iclass 18, count 0 2006.259.08:01:23.20#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.259.08:01:23.20#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.259.08:01:23.20#ibcon#about to clear, iclass 18 cls_cnt 0 2006.259.08:01:23.20#ibcon#cleared, iclass 18 cls_cnt 0 2006.259.08:01:23.20$vc4f8/vb=5,4 2006.259.08:01:23.20#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.259.08:01:23.20#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.259.08:01:23.20#ibcon#ireg 11 cls_cnt 2 2006.259.08:01:23.20#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.259.08:01:23.26#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.259.08:01:23.26#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.259.08:01:23.26#ibcon#enter wrdev, iclass 20, count 2 2006.259.08:01:23.26#ibcon#first serial, iclass 20, count 2 2006.259.08:01:23.26#ibcon#enter sib2, iclass 20, count 2 2006.259.08:01:23.26#ibcon#flushed, iclass 20, count 2 2006.259.08:01:23.26#ibcon#about to write, iclass 20, count 2 2006.259.08:01:23.26#ibcon#wrote, iclass 20, count 2 2006.259.08:01:23.26#ibcon#about to read 3, iclass 20, count 2 2006.259.08:01:23.29#ibcon#read 3, iclass 20, count 2 2006.259.08:01:23.29#ibcon#about to read 4, iclass 20, count 2 2006.259.08:01:23.29#ibcon#read 4, iclass 20, count 2 2006.259.08:01:23.29#ibcon#about to read 5, iclass 20, count 2 2006.259.08:01:23.29#ibcon#read 5, iclass 20, count 2 2006.259.08:01:23.29#ibcon#about to read 6, iclass 20, count 2 2006.259.08:01:23.29#ibcon#read 6, iclass 20, count 2 2006.259.08:01:23.29#ibcon#end of sib2, iclass 20, count 2 2006.259.08:01:23.29#ibcon#*mode == 0, iclass 20, count 2 2006.259.08:01:23.29#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.259.08:01:23.29#ibcon#[27=AT05-04\r\n] 2006.259.08:01:23.29#ibcon#*before write, iclass 20, count 2 2006.259.08:01:23.29#ibcon#enter sib2, iclass 20, count 2 2006.259.08:01:23.29#ibcon#flushed, iclass 20, count 2 2006.259.08:01:23.29#ibcon#about to write, iclass 20, count 2 2006.259.08:01:23.29#ibcon#wrote, iclass 20, count 2 2006.259.08:01:23.29#ibcon#about to read 3, iclass 20, count 2 2006.259.08:01:23.32#ibcon#read 3, iclass 20, count 2 2006.259.08:01:23.32#ibcon#about to read 4, iclass 20, count 2 2006.259.08:01:23.32#ibcon#read 4, iclass 20, count 2 2006.259.08:01:23.32#ibcon#about to read 5, iclass 20, count 2 2006.259.08:01:23.32#ibcon#read 5, iclass 20, count 2 2006.259.08:01:23.32#ibcon#about to read 6, iclass 20, count 2 2006.259.08:01:23.32#ibcon#read 6, iclass 20, count 2 2006.259.08:01:23.32#ibcon#end of sib2, iclass 20, count 2 2006.259.08:01:23.32#ibcon#*after write, iclass 20, count 2 2006.259.08:01:23.32#ibcon#*before return 0, iclass 20, count 2 2006.259.08:01:23.32#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.259.08:01:23.32#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.259.08:01:23.32#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.259.08:01:23.32#ibcon#ireg 7 cls_cnt 0 2006.259.08:01:23.32#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.259.08:01:23.44#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.259.08:01:23.44#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.259.08:01:23.44#ibcon#enter wrdev, iclass 20, count 0 2006.259.08:01:23.44#ibcon#first serial, iclass 20, count 0 2006.259.08:01:23.44#ibcon#enter sib2, iclass 20, count 0 2006.259.08:01:23.44#ibcon#flushed, iclass 20, count 0 2006.259.08:01:23.44#ibcon#about to write, iclass 20, count 0 2006.259.08:01:23.44#ibcon#wrote, iclass 20, count 0 2006.259.08:01:23.44#ibcon#about to read 3, iclass 20, count 0 2006.259.08:01:23.46#ibcon#read 3, iclass 20, count 0 2006.259.08:01:23.46#ibcon#about to read 4, iclass 20, count 0 2006.259.08:01:23.46#ibcon#read 4, iclass 20, count 0 2006.259.08:01:23.46#ibcon#about to read 5, iclass 20, count 0 2006.259.08:01:23.46#ibcon#read 5, iclass 20, count 0 2006.259.08:01:23.46#ibcon#about to read 6, iclass 20, count 0 2006.259.08:01:23.46#ibcon#read 6, iclass 20, count 0 2006.259.08:01:23.46#ibcon#end of sib2, iclass 20, count 0 2006.259.08:01:23.46#ibcon#*mode == 0, iclass 20, count 0 2006.259.08:01:23.46#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.259.08:01:23.46#ibcon#[27=USB\r\n] 2006.259.08:01:23.46#ibcon#*before write, iclass 20, count 0 2006.259.08:01:23.46#ibcon#enter sib2, iclass 20, count 0 2006.259.08:01:23.46#ibcon#flushed, iclass 20, count 0 2006.259.08:01:23.46#ibcon#about to write, iclass 20, count 0 2006.259.08:01:23.46#ibcon#wrote, iclass 20, count 0 2006.259.08:01:23.46#ibcon#about to read 3, iclass 20, count 0 2006.259.08:01:23.49#ibcon#read 3, iclass 20, count 0 2006.259.08:01:23.49#ibcon#about to read 4, iclass 20, count 0 2006.259.08:01:23.49#ibcon#read 4, iclass 20, count 0 2006.259.08:01:23.49#ibcon#about to read 5, iclass 20, count 0 2006.259.08:01:23.49#ibcon#read 5, iclass 20, count 0 2006.259.08:01:23.49#ibcon#about to read 6, iclass 20, count 0 2006.259.08:01:23.49#ibcon#read 6, iclass 20, count 0 2006.259.08:01:23.49#ibcon#end of sib2, iclass 20, count 0 2006.259.08:01:23.49#ibcon#*after write, iclass 20, count 0 2006.259.08:01:23.49#ibcon#*before return 0, iclass 20, count 0 2006.259.08:01:23.49#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.259.08:01:23.49#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.259.08:01:23.49#ibcon#about to clear, iclass 20 cls_cnt 0 2006.259.08:01:23.49#ibcon#cleared, iclass 20 cls_cnt 0 2006.259.08:01:23.49$vc4f8/vblo=6,752.99 2006.259.08:01:23.49#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.259.08:01:23.49#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.259.08:01:23.49#ibcon#ireg 17 cls_cnt 0 2006.259.08:01:23.49#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.259.08:01:23.49#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.259.08:01:23.49#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.259.08:01:23.49#ibcon#enter wrdev, iclass 22, count 0 2006.259.08:01:23.49#ibcon#first serial, iclass 22, count 0 2006.259.08:01:23.49#ibcon#enter sib2, iclass 22, count 0 2006.259.08:01:23.49#ibcon#flushed, iclass 22, count 0 2006.259.08:01:23.49#ibcon#about to write, iclass 22, count 0 2006.259.08:01:23.49#ibcon#wrote, iclass 22, count 0 2006.259.08:01:23.49#ibcon#about to read 3, iclass 22, count 0 2006.259.08:01:23.51#ibcon#read 3, iclass 22, count 0 2006.259.08:01:23.51#ibcon#about to read 4, iclass 22, count 0 2006.259.08:01:23.51#ibcon#read 4, iclass 22, count 0 2006.259.08:01:23.51#ibcon#about to read 5, iclass 22, count 0 2006.259.08:01:23.51#ibcon#read 5, iclass 22, count 0 2006.259.08:01:23.51#ibcon#about to read 6, iclass 22, count 0 2006.259.08:01:23.51#ibcon#read 6, iclass 22, count 0 2006.259.08:01:23.51#ibcon#end of sib2, iclass 22, count 0 2006.259.08:01:23.51#ibcon#*mode == 0, iclass 22, count 0 2006.259.08:01:23.51#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.259.08:01:23.51#ibcon#[28=FRQ=06,752.99\r\n] 2006.259.08:01:23.51#ibcon#*before write, iclass 22, count 0 2006.259.08:01:23.51#ibcon#enter sib2, iclass 22, count 0 2006.259.08:01:23.51#ibcon#flushed, iclass 22, count 0 2006.259.08:01:23.51#ibcon#about to write, iclass 22, count 0 2006.259.08:01:23.51#ibcon#wrote, iclass 22, count 0 2006.259.08:01:23.51#ibcon#about to read 3, iclass 22, count 0 2006.259.08:01:23.55#ibcon#read 3, iclass 22, count 0 2006.259.08:01:23.55#ibcon#about to read 4, iclass 22, count 0 2006.259.08:01:23.55#ibcon#read 4, iclass 22, count 0 2006.259.08:01:23.55#ibcon#about to read 5, iclass 22, count 0 2006.259.08:01:23.55#ibcon#read 5, iclass 22, count 0 2006.259.08:01:23.55#ibcon#about to read 6, iclass 22, count 0 2006.259.08:01:23.55#ibcon#read 6, iclass 22, count 0 2006.259.08:01:23.55#ibcon#end of sib2, iclass 22, count 0 2006.259.08:01:23.55#ibcon#*after write, iclass 22, count 0 2006.259.08:01:23.55#ibcon#*before return 0, iclass 22, count 0 2006.259.08:01:23.55#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.259.08:01:23.55#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.259.08:01:23.55#ibcon#about to clear, iclass 22 cls_cnt 0 2006.259.08:01:23.55#ibcon#cleared, iclass 22 cls_cnt 0 2006.259.08:01:23.55$vc4f8/vb=6,4 2006.259.08:01:23.55#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.259.08:01:23.55#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.259.08:01:23.55#ibcon#ireg 11 cls_cnt 2 2006.259.08:01:23.55#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.259.08:01:23.61#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.259.08:01:23.61#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.259.08:01:23.61#ibcon#enter wrdev, iclass 24, count 2 2006.259.08:01:23.61#ibcon#first serial, iclass 24, count 2 2006.259.08:01:23.61#ibcon#enter sib2, iclass 24, count 2 2006.259.08:01:23.61#ibcon#flushed, iclass 24, count 2 2006.259.08:01:23.61#ibcon#about to write, iclass 24, count 2 2006.259.08:01:23.61#ibcon#wrote, iclass 24, count 2 2006.259.08:01:23.61#ibcon#about to read 3, iclass 24, count 2 2006.259.08:01:23.63#ibcon#read 3, iclass 24, count 2 2006.259.08:01:23.63#ibcon#about to read 4, iclass 24, count 2 2006.259.08:01:23.63#ibcon#read 4, iclass 24, count 2 2006.259.08:01:23.63#ibcon#about to read 5, iclass 24, count 2 2006.259.08:01:23.63#ibcon#read 5, iclass 24, count 2 2006.259.08:01:23.63#ibcon#about to read 6, iclass 24, count 2 2006.259.08:01:23.63#ibcon#read 6, iclass 24, count 2 2006.259.08:01:23.63#ibcon#end of sib2, iclass 24, count 2 2006.259.08:01:23.63#ibcon#*mode == 0, iclass 24, count 2 2006.259.08:01:23.63#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.259.08:01:23.63#ibcon#[27=AT06-04\r\n] 2006.259.08:01:23.63#ibcon#*before write, iclass 24, count 2 2006.259.08:01:23.63#ibcon#enter sib2, iclass 24, count 2 2006.259.08:01:23.63#ibcon#flushed, iclass 24, count 2 2006.259.08:01:23.63#ibcon#about to write, iclass 24, count 2 2006.259.08:01:23.63#ibcon#wrote, iclass 24, count 2 2006.259.08:01:23.63#ibcon#about to read 3, iclass 24, count 2 2006.259.08:01:23.66#ibcon#read 3, iclass 24, count 2 2006.259.08:01:23.66#ibcon#about to read 4, iclass 24, count 2 2006.259.08:01:23.66#ibcon#read 4, iclass 24, count 2 2006.259.08:01:23.66#ibcon#about to read 5, iclass 24, count 2 2006.259.08:01:23.66#ibcon#read 5, iclass 24, count 2 2006.259.08:01:23.66#ibcon#about to read 6, iclass 24, count 2 2006.259.08:01:23.66#ibcon#read 6, iclass 24, count 2 2006.259.08:01:23.66#ibcon#end of sib2, iclass 24, count 2 2006.259.08:01:23.66#ibcon#*after write, iclass 24, count 2 2006.259.08:01:23.66#ibcon#*before return 0, iclass 24, count 2 2006.259.08:01:23.66#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.259.08:01:23.66#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.259.08:01:23.66#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.259.08:01:23.66#ibcon#ireg 7 cls_cnt 0 2006.259.08:01:23.66#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.259.08:01:23.78#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.259.08:01:23.78#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.259.08:01:23.78#ibcon#enter wrdev, iclass 24, count 0 2006.259.08:01:23.78#ibcon#first serial, iclass 24, count 0 2006.259.08:01:23.78#ibcon#enter sib2, iclass 24, count 0 2006.259.08:01:23.78#ibcon#flushed, iclass 24, count 0 2006.259.08:01:23.78#ibcon#about to write, iclass 24, count 0 2006.259.08:01:23.78#ibcon#wrote, iclass 24, count 0 2006.259.08:01:23.78#ibcon#about to read 3, iclass 24, count 0 2006.259.08:01:23.80#ibcon#read 3, iclass 24, count 0 2006.259.08:01:23.80#ibcon#about to read 4, iclass 24, count 0 2006.259.08:01:23.80#ibcon#read 4, iclass 24, count 0 2006.259.08:01:23.80#ibcon#about to read 5, iclass 24, count 0 2006.259.08:01:23.80#ibcon#read 5, iclass 24, count 0 2006.259.08:01:23.80#ibcon#about to read 6, iclass 24, count 0 2006.259.08:01:23.80#ibcon#read 6, iclass 24, count 0 2006.259.08:01:23.80#ibcon#end of sib2, iclass 24, count 0 2006.259.08:01:23.80#ibcon#*mode == 0, iclass 24, count 0 2006.259.08:01:23.80#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.259.08:01:23.80#ibcon#[27=USB\r\n] 2006.259.08:01:23.80#ibcon#*before write, iclass 24, count 0 2006.259.08:01:23.80#ibcon#enter sib2, iclass 24, count 0 2006.259.08:01:23.80#ibcon#flushed, iclass 24, count 0 2006.259.08:01:23.80#ibcon#about to write, iclass 24, count 0 2006.259.08:01:23.80#ibcon#wrote, iclass 24, count 0 2006.259.08:01:23.80#ibcon#about to read 3, iclass 24, count 0 2006.259.08:01:23.83#ibcon#read 3, iclass 24, count 0 2006.259.08:01:23.83#ibcon#about to read 4, iclass 24, count 0 2006.259.08:01:23.83#ibcon#read 4, iclass 24, count 0 2006.259.08:01:23.83#ibcon#about to read 5, iclass 24, count 0 2006.259.08:01:23.83#ibcon#read 5, iclass 24, count 0 2006.259.08:01:23.83#ibcon#about to read 6, iclass 24, count 0 2006.259.08:01:23.83#ibcon#read 6, iclass 24, count 0 2006.259.08:01:23.83#ibcon#end of sib2, iclass 24, count 0 2006.259.08:01:23.83#ibcon#*after write, iclass 24, count 0 2006.259.08:01:23.83#ibcon#*before return 0, iclass 24, count 0 2006.259.08:01:23.83#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.259.08:01:23.83#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.259.08:01:23.83#ibcon#about to clear, iclass 24 cls_cnt 0 2006.259.08:01:23.83#ibcon#cleared, iclass 24 cls_cnt 0 2006.259.08:01:23.83$vc4f8/vabw=wide 2006.259.08:01:23.83#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.259.08:01:23.83#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.259.08:01:23.83#ibcon#ireg 8 cls_cnt 0 2006.259.08:01:23.83#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.259.08:01:23.83#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.259.08:01:23.83#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.259.08:01:23.83#ibcon#enter wrdev, iclass 26, count 0 2006.259.08:01:23.83#ibcon#first serial, iclass 26, count 0 2006.259.08:01:23.83#ibcon#enter sib2, iclass 26, count 0 2006.259.08:01:23.83#ibcon#flushed, iclass 26, count 0 2006.259.08:01:23.83#ibcon#about to write, iclass 26, count 0 2006.259.08:01:23.83#ibcon#wrote, iclass 26, count 0 2006.259.08:01:23.83#ibcon#about to read 3, iclass 26, count 0 2006.259.08:01:23.85#ibcon#read 3, iclass 26, count 0 2006.259.08:01:23.85#ibcon#about to read 4, iclass 26, count 0 2006.259.08:01:23.85#ibcon#read 4, iclass 26, count 0 2006.259.08:01:23.85#ibcon#about to read 5, iclass 26, count 0 2006.259.08:01:23.85#ibcon#read 5, iclass 26, count 0 2006.259.08:01:23.85#ibcon#about to read 6, iclass 26, count 0 2006.259.08:01:23.85#ibcon#read 6, iclass 26, count 0 2006.259.08:01:23.85#ibcon#end of sib2, iclass 26, count 0 2006.259.08:01:23.85#ibcon#*mode == 0, iclass 26, count 0 2006.259.08:01:23.85#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.259.08:01:23.85#ibcon#[25=BW32\r\n] 2006.259.08:01:23.85#ibcon#*before write, iclass 26, count 0 2006.259.08:01:23.85#ibcon#enter sib2, iclass 26, count 0 2006.259.08:01:23.85#ibcon#flushed, iclass 26, count 0 2006.259.08:01:23.85#ibcon#about to write, iclass 26, count 0 2006.259.08:01:23.85#ibcon#wrote, iclass 26, count 0 2006.259.08:01:23.85#ibcon#about to read 3, iclass 26, count 0 2006.259.08:01:23.88#ibcon#read 3, iclass 26, count 0 2006.259.08:01:23.88#ibcon#about to read 4, iclass 26, count 0 2006.259.08:01:23.88#ibcon#read 4, iclass 26, count 0 2006.259.08:01:23.88#ibcon#about to read 5, iclass 26, count 0 2006.259.08:01:23.88#ibcon#read 5, iclass 26, count 0 2006.259.08:01:23.88#ibcon#about to read 6, iclass 26, count 0 2006.259.08:01:23.88#ibcon#read 6, iclass 26, count 0 2006.259.08:01:23.88#ibcon#end of sib2, iclass 26, count 0 2006.259.08:01:23.88#ibcon#*after write, iclass 26, count 0 2006.259.08:01:23.88#ibcon#*before return 0, iclass 26, count 0 2006.259.08:01:23.88#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.259.08:01:23.88#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.259.08:01:23.88#ibcon#about to clear, iclass 26 cls_cnt 0 2006.259.08:01:23.88#ibcon#cleared, iclass 26 cls_cnt 0 2006.259.08:01:23.88$vc4f8/vbbw=wide 2006.259.08:01:23.88#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.259.08:01:23.88#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.259.08:01:23.88#ibcon#ireg 8 cls_cnt 0 2006.259.08:01:23.88#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.259.08:01:23.95#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.259.08:01:23.95#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.259.08:01:23.95#ibcon#enter wrdev, iclass 28, count 0 2006.259.08:01:23.95#ibcon#first serial, iclass 28, count 0 2006.259.08:01:23.95#ibcon#enter sib2, iclass 28, count 0 2006.259.08:01:23.95#ibcon#flushed, iclass 28, count 0 2006.259.08:01:23.95#ibcon#about to write, iclass 28, count 0 2006.259.08:01:23.95#ibcon#wrote, iclass 28, count 0 2006.259.08:01:23.95#ibcon#about to read 3, iclass 28, count 0 2006.259.08:01:23.97#ibcon#read 3, iclass 28, count 0 2006.259.08:01:23.97#ibcon#about to read 4, iclass 28, count 0 2006.259.08:01:23.97#ibcon#read 4, iclass 28, count 0 2006.259.08:01:23.97#ibcon#about to read 5, iclass 28, count 0 2006.259.08:01:23.97#ibcon#read 5, iclass 28, count 0 2006.259.08:01:23.97#ibcon#about to read 6, iclass 28, count 0 2006.259.08:01:23.97#ibcon#read 6, iclass 28, count 0 2006.259.08:01:23.97#ibcon#end of sib2, iclass 28, count 0 2006.259.08:01:23.97#ibcon#*mode == 0, iclass 28, count 0 2006.259.08:01:23.97#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.259.08:01:23.97#ibcon#[27=BW32\r\n] 2006.259.08:01:23.97#ibcon#*before write, iclass 28, count 0 2006.259.08:01:23.97#ibcon#enter sib2, iclass 28, count 0 2006.259.08:01:23.97#ibcon#flushed, iclass 28, count 0 2006.259.08:01:23.97#ibcon#about to write, iclass 28, count 0 2006.259.08:01:23.97#ibcon#wrote, iclass 28, count 0 2006.259.08:01:23.97#ibcon#about to read 3, iclass 28, count 0 2006.259.08:01:24.00#ibcon#read 3, iclass 28, count 0 2006.259.08:01:24.00#ibcon#about to read 4, iclass 28, count 0 2006.259.08:01:24.00#ibcon#read 4, iclass 28, count 0 2006.259.08:01:24.00#ibcon#about to read 5, iclass 28, count 0 2006.259.08:01:24.00#ibcon#read 5, iclass 28, count 0 2006.259.08:01:24.00#ibcon#about to read 6, iclass 28, count 0 2006.259.08:01:24.00#ibcon#read 6, iclass 28, count 0 2006.259.08:01:24.00#ibcon#end of sib2, iclass 28, count 0 2006.259.08:01:24.00#ibcon#*after write, iclass 28, count 0 2006.259.08:01:24.00#ibcon#*before return 0, iclass 28, count 0 2006.259.08:01:24.00#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.259.08:01:24.00#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.259.08:01:24.00#ibcon#about to clear, iclass 28 cls_cnt 0 2006.259.08:01:24.00#ibcon#cleared, iclass 28 cls_cnt 0 2006.259.08:01:24.00$4f8m12a/ifd4f 2006.259.08:01:24.00$ifd4f/lo= 2006.259.08:01:24.00$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.259.08:01:24.00$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.259.08:01:24.00$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.259.08:01:24.00$ifd4f/patch= 2006.259.08:01:24.00$ifd4f/patch=lo1,a1,a2,a3,a4 2006.259.08:01:24.00$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.259.08:01:24.00$ifd4f/patch=lo3,a5,a6,a7,a8 2006.259.08:01:24.00$4f8m12a/"form=m,16.000,1:2 2006.259.08:01:24.00$4f8m12a/"tpicd 2006.259.08:01:24.00$4f8m12a/echo=off 2006.259.08:01:24.00$4f8m12a/xlog=off 2006.259.08:01:24.01:!2006.259.08:02:00 2006.259.08:01:42.14#trakl#Source acquired 2006.259.08:01:43.14#flagr#flagr/antenna,acquired 2006.259.08:02:00.01:preob 2006.259.08:02:01.14/onsource/TRACKING 2006.259.08:02:01.14:!2006.259.08:02:10 2006.259.08:02:10.00:data_valid=on 2006.259.08:02:10.00:midob 2006.259.08:02:10.14/onsource/TRACKING 2006.259.08:02:10.14/wx/22.10,1013.0,86 2006.259.08:02:10.35/cable/+6.4611E-03 2006.259.08:02:11.44/va/01,08,usb,yes,32,33 2006.259.08:02:11.44/va/02,07,usb,yes,32,33 2006.259.08:02:11.44/va/03,08,usb,yes,24,24 2006.259.08:02:11.44/va/04,07,usb,yes,33,35 2006.259.08:02:11.44/va/05,07,usb,yes,36,38 2006.259.08:02:11.44/va/06,06,usb,yes,35,35 2006.259.08:02:11.44/va/07,06,usb,yes,36,36 2006.259.08:02:11.44/va/08,06,usb,yes,38,38 2006.259.08:02:11.67/valo/01,532.99,yes,locked 2006.259.08:02:11.67/valo/02,572.99,yes,locked 2006.259.08:02:11.67/valo/03,672.99,yes,locked 2006.259.08:02:11.67/valo/04,832.99,yes,locked 2006.259.08:02:11.67/valo/05,652.99,yes,locked 2006.259.08:02:11.67/valo/06,772.99,yes,locked 2006.259.08:02:11.67/valo/07,832.99,yes,locked 2006.259.08:02:11.67/valo/08,852.99,yes,locked 2006.259.08:02:12.76/vb/01,04,usb,yes,30,29 2006.259.08:02:12.76/vb/02,05,usb,yes,28,29 2006.259.08:02:12.76/vb/03,04,usb,yes,28,32 2006.259.08:02:12.76/vb/04,05,usb,yes,26,26 2006.259.08:02:12.76/vb/05,04,usb,yes,28,32 2006.259.08:02:12.76/vb/06,04,usb,yes,29,32 2006.259.08:02:12.76/vb/07,04,usb,yes,31,31 2006.259.08:02:12.76/vb/08,04,usb,yes,28,32 2006.259.08:02:13.00/vblo/01,632.99,yes,locked 2006.259.08:02:13.00/vblo/02,640.99,yes,locked 2006.259.08:02:13.00/vblo/03,656.99,yes,locked 2006.259.08:02:13.00/vblo/04,712.99,yes,locked 2006.259.08:02:13.00/vblo/05,744.99,yes,locked 2006.259.08:02:13.00/vblo/06,752.99,yes,locked 2006.259.08:02:13.00/vblo/07,734.99,yes,locked 2006.259.08:02:13.00/vblo/08,744.99,yes,locked 2006.259.08:02:13.15/vabw/8 2006.259.08:02:13.30/vbbw/8 2006.259.08:02:13.39/xfe/off,on,15.5 2006.259.08:02:13.76/ifatt/23,28,28,28 2006.259.08:02:14.07/fmout-gps/S +4.60E-07 2006.259.08:02:14.11:!2006.259.08:03:10 2006.259.08:03:10.01:data_valid=off 2006.259.08:03:10.02:postob 2006.259.08:03:10.19/cable/+6.4592E-03 2006.259.08:03:10.20/wx/22.08,1013.0,86 2006.259.08:03:11.07/fmout-gps/S +4.59E-07 2006.259.08:03:11.08:scan_name=259-0804,k06259,60 2006.259.08:03:11.08:source=1803+784,180045.68,782804.0,2000.0,neutral 2006.259.08:03:12.14#flagr#flagr/antenna,new-source 2006.259.08:03:12.15:checkk5 2006.259.08:03:12.53/chk_autoobs//k5ts1/ autoobs is running! 2006.259.08:03:12.94/chk_autoobs//k5ts2/ autoobs is running! 2006.259.08:03:13.38/chk_autoobs//k5ts3/ autoobs is running! 2006.259.08:03:13.79/chk_autoobs//k5ts4/ autoobs is running! 2006.259.08:03:14.27/chk_obsdata//k5ts1/T2590802??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.259.08:03:14.88/chk_obsdata//k5ts2/T2590802??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.259.08:03:15.44/chk_obsdata//k5ts3/T2590802??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.259.08:03:15.85/chk_obsdata//k5ts4/T2590802??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.259.08:03:16.64/k5log//k5ts1_log_newline 2006.259.08:03:17.60/k5log//k5ts2_log_newline 2006.259.08:03:18.37/k5log//k5ts3_log_newline 2006.259.08:03:19.16/k5log//k5ts4_log_newline 2006.259.08:03:19.18/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.259.08:03:19.18:4f8m12a=2 2006.259.08:03:19.18$4f8m12a/echo=on 2006.259.08:03:19.18$4f8m12a/pcalon 2006.259.08:03:19.18$pcalon/"no phase cal control is implemented here 2006.259.08:03:19.18$4f8m12a/"tpicd=stop 2006.259.08:03:19.18$4f8m12a/vc4f8 2006.259.08:03:19.18$vc4f8/valo=1,532.99 2006.259.08:03:19.22#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.259.08:03:19.22#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.259.08:03:19.22#ibcon#ireg 17 cls_cnt 0 2006.259.08:03:19.22#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.259.08:03:19.22#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.259.08:03:19.22#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.259.08:03:19.22#ibcon#enter wrdev, iclass 39, count 0 2006.259.08:03:19.22#ibcon#first serial, iclass 39, count 0 2006.259.08:03:19.22#ibcon#enter sib2, iclass 39, count 0 2006.259.08:03:19.22#ibcon#flushed, iclass 39, count 0 2006.259.08:03:19.22#ibcon#about to write, iclass 39, count 0 2006.259.08:03:19.22#ibcon#wrote, iclass 39, count 0 2006.259.08:03:19.22#ibcon#about to read 3, iclass 39, count 0 2006.259.08:03:19.24#ibcon#read 3, iclass 39, count 0 2006.259.08:03:19.24#ibcon#about to read 4, iclass 39, count 0 2006.259.08:03:19.24#ibcon#read 4, iclass 39, count 0 2006.259.08:03:19.24#ibcon#about to read 5, iclass 39, count 0 2006.259.08:03:19.24#ibcon#read 5, iclass 39, count 0 2006.259.08:03:19.24#ibcon#about to read 6, iclass 39, count 0 2006.259.08:03:19.24#ibcon#read 6, iclass 39, count 0 2006.259.08:03:19.24#ibcon#end of sib2, iclass 39, count 0 2006.259.08:03:19.24#ibcon#*mode == 0, iclass 39, count 0 2006.259.08:03:19.24#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.259.08:03:19.24#ibcon#[26=FRQ=01,532.99\r\n] 2006.259.08:03:19.24#ibcon#*before write, iclass 39, count 0 2006.259.08:03:19.24#ibcon#enter sib2, iclass 39, count 0 2006.259.08:03:19.24#ibcon#flushed, iclass 39, count 0 2006.259.08:03:19.24#ibcon#about to write, iclass 39, count 0 2006.259.08:03:19.24#ibcon#wrote, iclass 39, count 0 2006.259.08:03:19.24#ibcon#about to read 3, iclass 39, count 0 2006.259.08:03:19.29#ibcon#read 3, iclass 39, count 0 2006.259.08:03:19.29#ibcon#about to read 4, iclass 39, count 0 2006.259.08:03:19.29#ibcon#read 4, iclass 39, count 0 2006.259.08:03:19.29#ibcon#about to read 5, iclass 39, count 0 2006.259.08:03:19.29#ibcon#read 5, iclass 39, count 0 2006.259.08:03:19.29#ibcon#about to read 6, iclass 39, count 0 2006.259.08:03:19.29#ibcon#read 6, iclass 39, count 0 2006.259.08:03:19.29#ibcon#end of sib2, iclass 39, count 0 2006.259.08:03:19.29#ibcon#*after write, iclass 39, count 0 2006.259.08:03:19.29#ibcon#*before return 0, iclass 39, count 0 2006.259.08:03:19.29#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.259.08:03:19.29#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.259.08:03:19.29#ibcon#about to clear, iclass 39 cls_cnt 0 2006.259.08:03:19.29#ibcon#cleared, iclass 39 cls_cnt 0 2006.259.08:03:19.30$vc4f8/va=1,8 2006.259.08:03:19.30#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.259.08:03:19.30#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.259.08:03:19.30#ibcon#ireg 11 cls_cnt 2 2006.259.08:03:19.30#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.259.08:03:19.30#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.259.08:03:19.30#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.259.08:03:19.30#ibcon#enter wrdev, iclass 3, count 2 2006.259.08:03:19.30#ibcon#first serial, iclass 3, count 2 2006.259.08:03:19.30#ibcon#enter sib2, iclass 3, count 2 2006.259.08:03:19.30#ibcon#flushed, iclass 3, count 2 2006.259.08:03:19.30#ibcon#about to write, iclass 3, count 2 2006.259.08:03:19.30#ibcon#wrote, iclass 3, count 2 2006.259.08:03:19.30#ibcon#about to read 3, iclass 3, count 2 2006.259.08:03:19.32#ibcon#read 3, iclass 3, count 2 2006.259.08:03:19.32#ibcon#about to read 4, iclass 3, count 2 2006.259.08:03:19.32#ibcon#read 4, iclass 3, count 2 2006.259.08:03:19.32#ibcon#about to read 5, iclass 3, count 2 2006.259.08:03:19.32#ibcon#read 5, iclass 3, count 2 2006.259.08:03:19.32#ibcon#about to read 6, iclass 3, count 2 2006.259.08:03:19.32#ibcon#read 6, iclass 3, count 2 2006.259.08:03:19.32#ibcon#end of sib2, iclass 3, count 2 2006.259.08:03:19.32#ibcon#*mode == 0, iclass 3, count 2 2006.259.08:03:19.32#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.259.08:03:19.32#ibcon#[25=AT01-08\r\n] 2006.259.08:03:19.32#ibcon#*before write, iclass 3, count 2 2006.259.08:03:19.32#ibcon#enter sib2, iclass 3, count 2 2006.259.08:03:19.32#ibcon#flushed, iclass 3, count 2 2006.259.08:03:19.32#ibcon#about to write, iclass 3, count 2 2006.259.08:03:19.32#ibcon#wrote, iclass 3, count 2 2006.259.08:03:19.32#ibcon#about to read 3, iclass 3, count 2 2006.259.08:03:19.35#ibcon#read 3, iclass 3, count 2 2006.259.08:03:19.35#ibcon#about to read 4, iclass 3, count 2 2006.259.08:03:19.35#ibcon#read 4, iclass 3, count 2 2006.259.08:03:19.35#ibcon#about to read 5, iclass 3, count 2 2006.259.08:03:19.35#ibcon#read 5, iclass 3, count 2 2006.259.08:03:19.35#ibcon#about to read 6, iclass 3, count 2 2006.259.08:03:19.35#ibcon#read 6, iclass 3, count 2 2006.259.08:03:19.35#ibcon#end of sib2, iclass 3, count 2 2006.259.08:03:19.35#ibcon#*after write, iclass 3, count 2 2006.259.08:03:19.35#ibcon#*before return 0, iclass 3, count 2 2006.259.08:03:19.35#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.259.08:03:19.35#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.259.08:03:19.35#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.259.08:03:19.35#ibcon#ireg 7 cls_cnt 0 2006.259.08:03:19.35#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.259.08:03:19.48#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.259.08:03:19.48#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.259.08:03:19.48#ibcon#enter wrdev, iclass 3, count 0 2006.259.08:03:19.48#ibcon#first serial, iclass 3, count 0 2006.259.08:03:19.48#ibcon#enter sib2, iclass 3, count 0 2006.259.08:03:19.48#ibcon#flushed, iclass 3, count 0 2006.259.08:03:19.48#ibcon#about to write, iclass 3, count 0 2006.259.08:03:19.48#ibcon#wrote, iclass 3, count 0 2006.259.08:03:19.48#ibcon#about to read 3, iclass 3, count 0 2006.259.08:03:19.51#ibcon#read 3, iclass 3, count 0 2006.259.08:03:19.51#ibcon#about to read 4, iclass 3, count 0 2006.259.08:03:19.51#ibcon#read 4, iclass 3, count 0 2006.259.08:03:19.51#ibcon#about to read 5, iclass 3, count 0 2006.259.08:03:19.51#ibcon#read 5, iclass 3, count 0 2006.259.08:03:19.51#ibcon#about to read 6, iclass 3, count 0 2006.259.08:03:19.51#ibcon#read 6, iclass 3, count 0 2006.259.08:03:19.51#ibcon#end of sib2, iclass 3, count 0 2006.259.08:03:19.51#ibcon#*mode == 0, iclass 3, count 0 2006.259.08:03:19.51#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.259.08:03:19.51#ibcon#[25=USB\r\n] 2006.259.08:03:19.51#ibcon#*before write, iclass 3, count 0 2006.259.08:03:19.51#ibcon#enter sib2, iclass 3, count 0 2006.259.08:03:19.51#ibcon#flushed, iclass 3, count 0 2006.259.08:03:19.51#ibcon#about to write, iclass 3, count 0 2006.259.08:03:19.51#ibcon#wrote, iclass 3, count 0 2006.259.08:03:19.51#ibcon#about to read 3, iclass 3, count 0 2006.259.08:03:19.53#ibcon#read 3, iclass 3, count 0 2006.259.08:03:19.53#ibcon#about to read 4, iclass 3, count 0 2006.259.08:03:19.53#ibcon#read 4, iclass 3, count 0 2006.259.08:03:19.53#ibcon#about to read 5, iclass 3, count 0 2006.259.08:03:19.53#ibcon#read 5, iclass 3, count 0 2006.259.08:03:19.53#ibcon#about to read 6, iclass 3, count 0 2006.259.08:03:19.53#ibcon#read 6, iclass 3, count 0 2006.259.08:03:19.53#ibcon#end of sib2, iclass 3, count 0 2006.259.08:03:19.53#ibcon#*after write, iclass 3, count 0 2006.259.08:03:19.53#ibcon#*before return 0, iclass 3, count 0 2006.259.08:03:19.53#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.259.08:03:19.53#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.259.08:03:19.53#ibcon#about to clear, iclass 3 cls_cnt 0 2006.259.08:03:19.53#ibcon#cleared, iclass 3 cls_cnt 0 2006.259.08:03:19.53$vc4f8/valo=2,572.99 2006.259.08:03:19.53#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.259.08:03:19.53#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.259.08:03:19.53#ibcon#ireg 17 cls_cnt 0 2006.259.08:03:19.53#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.259.08:03:19.53#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.259.08:03:19.53#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.259.08:03:19.53#ibcon#enter wrdev, iclass 5, count 0 2006.259.08:03:19.53#ibcon#first serial, iclass 5, count 0 2006.259.08:03:19.53#ibcon#enter sib2, iclass 5, count 0 2006.259.08:03:19.53#ibcon#flushed, iclass 5, count 0 2006.259.08:03:19.53#ibcon#about to write, iclass 5, count 0 2006.259.08:03:19.53#ibcon#wrote, iclass 5, count 0 2006.259.08:03:19.53#ibcon#about to read 3, iclass 5, count 0 2006.259.08:03:19.55#ibcon#read 3, iclass 5, count 0 2006.259.08:03:19.55#ibcon#about to read 4, iclass 5, count 0 2006.259.08:03:19.55#ibcon#read 4, iclass 5, count 0 2006.259.08:03:19.55#ibcon#about to read 5, iclass 5, count 0 2006.259.08:03:19.55#ibcon#read 5, iclass 5, count 0 2006.259.08:03:19.55#ibcon#about to read 6, iclass 5, count 0 2006.259.08:03:19.55#ibcon#read 6, iclass 5, count 0 2006.259.08:03:19.55#ibcon#end of sib2, iclass 5, count 0 2006.259.08:03:19.55#ibcon#*mode == 0, iclass 5, count 0 2006.259.08:03:19.55#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.259.08:03:19.55#ibcon#[26=FRQ=02,572.99\r\n] 2006.259.08:03:19.55#ibcon#*before write, iclass 5, count 0 2006.259.08:03:19.55#ibcon#enter sib2, iclass 5, count 0 2006.259.08:03:19.55#ibcon#flushed, iclass 5, count 0 2006.259.08:03:19.55#ibcon#about to write, iclass 5, count 0 2006.259.08:03:19.55#ibcon#wrote, iclass 5, count 0 2006.259.08:03:19.55#ibcon#about to read 3, iclass 5, count 0 2006.259.08:03:19.59#ibcon#read 3, iclass 5, count 0 2006.259.08:03:19.59#ibcon#about to read 4, iclass 5, count 0 2006.259.08:03:19.59#ibcon#read 4, iclass 5, count 0 2006.259.08:03:19.59#ibcon#about to read 5, iclass 5, count 0 2006.259.08:03:19.59#ibcon#read 5, iclass 5, count 0 2006.259.08:03:19.59#ibcon#about to read 6, iclass 5, count 0 2006.259.08:03:19.59#ibcon#read 6, iclass 5, count 0 2006.259.08:03:19.59#ibcon#end of sib2, iclass 5, count 0 2006.259.08:03:19.59#ibcon#*after write, iclass 5, count 0 2006.259.08:03:19.59#ibcon#*before return 0, iclass 5, count 0 2006.259.08:03:19.59#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.259.08:03:19.59#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.259.08:03:19.59#ibcon#about to clear, iclass 5 cls_cnt 0 2006.259.08:03:19.59#ibcon#cleared, iclass 5 cls_cnt 0 2006.259.08:03:19.59$vc4f8/va=2,7 2006.259.08:03:19.59#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.259.08:03:19.59#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.259.08:03:19.59#ibcon#ireg 11 cls_cnt 2 2006.259.08:03:19.59#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.259.08:03:19.65#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.259.08:03:19.65#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.259.08:03:19.65#ibcon#enter wrdev, iclass 7, count 2 2006.259.08:03:19.65#ibcon#first serial, iclass 7, count 2 2006.259.08:03:19.65#ibcon#enter sib2, iclass 7, count 2 2006.259.08:03:19.65#ibcon#flushed, iclass 7, count 2 2006.259.08:03:19.65#ibcon#about to write, iclass 7, count 2 2006.259.08:03:19.65#ibcon#wrote, iclass 7, count 2 2006.259.08:03:19.65#ibcon#about to read 3, iclass 7, count 2 2006.259.08:03:19.68#ibcon#read 3, iclass 7, count 2 2006.259.08:03:19.68#ibcon#about to read 4, iclass 7, count 2 2006.259.08:03:19.68#ibcon#read 4, iclass 7, count 2 2006.259.08:03:19.68#ibcon#about to read 5, iclass 7, count 2 2006.259.08:03:19.68#ibcon#read 5, iclass 7, count 2 2006.259.08:03:19.68#ibcon#about to read 6, iclass 7, count 2 2006.259.08:03:19.68#ibcon#read 6, iclass 7, count 2 2006.259.08:03:19.68#ibcon#end of sib2, iclass 7, count 2 2006.259.08:03:19.68#ibcon#*mode == 0, iclass 7, count 2 2006.259.08:03:19.68#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.259.08:03:19.68#ibcon#[25=AT02-07\r\n] 2006.259.08:03:19.68#ibcon#*before write, iclass 7, count 2 2006.259.08:03:19.68#ibcon#enter sib2, iclass 7, count 2 2006.259.08:03:19.68#ibcon#flushed, iclass 7, count 2 2006.259.08:03:19.68#ibcon#about to write, iclass 7, count 2 2006.259.08:03:19.68#ibcon#wrote, iclass 7, count 2 2006.259.08:03:19.68#ibcon#about to read 3, iclass 7, count 2 2006.259.08:03:19.71#ibcon#read 3, iclass 7, count 2 2006.259.08:03:19.71#ibcon#about to read 4, iclass 7, count 2 2006.259.08:03:19.71#ibcon#read 4, iclass 7, count 2 2006.259.08:03:19.71#ibcon#about to read 5, iclass 7, count 2 2006.259.08:03:19.71#ibcon#read 5, iclass 7, count 2 2006.259.08:03:19.71#ibcon#about to read 6, iclass 7, count 2 2006.259.08:03:19.71#ibcon#read 6, iclass 7, count 2 2006.259.08:03:19.71#ibcon#end of sib2, iclass 7, count 2 2006.259.08:03:19.71#ibcon#*after write, iclass 7, count 2 2006.259.08:03:19.71#ibcon#*before return 0, iclass 7, count 2 2006.259.08:03:19.71#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.259.08:03:19.71#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.259.08:03:19.71#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.259.08:03:19.71#ibcon#ireg 7 cls_cnt 0 2006.259.08:03:19.71#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.259.08:03:19.83#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.259.08:03:19.83#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.259.08:03:19.83#ibcon#enter wrdev, iclass 7, count 0 2006.259.08:03:19.83#ibcon#first serial, iclass 7, count 0 2006.259.08:03:19.83#ibcon#enter sib2, iclass 7, count 0 2006.259.08:03:19.83#ibcon#flushed, iclass 7, count 0 2006.259.08:03:19.83#ibcon#about to write, iclass 7, count 0 2006.259.08:03:19.83#ibcon#wrote, iclass 7, count 0 2006.259.08:03:19.83#ibcon#about to read 3, iclass 7, count 0 2006.259.08:03:19.85#ibcon#read 3, iclass 7, count 0 2006.259.08:03:19.85#ibcon#about to read 4, iclass 7, count 0 2006.259.08:03:19.85#ibcon#read 4, iclass 7, count 0 2006.259.08:03:19.85#ibcon#about to read 5, iclass 7, count 0 2006.259.08:03:19.85#ibcon#read 5, iclass 7, count 0 2006.259.08:03:19.85#ibcon#about to read 6, iclass 7, count 0 2006.259.08:03:19.85#ibcon#read 6, iclass 7, count 0 2006.259.08:03:19.85#ibcon#end of sib2, iclass 7, count 0 2006.259.08:03:19.85#ibcon#*mode == 0, iclass 7, count 0 2006.259.08:03:19.85#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.259.08:03:19.85#ibcon#[25=USB\r\n] 2006.259.08:03:19.85#ibcon#*before write, iclass 7, count 0 2006.259.08:03:19.85#ibcon#enter sib2, iclass 7, count 0 2006.259.08:03:19.85#ibcon#flushed, iclass 7, count 0 2006.259.08:03:19.85#ibcon#about to write, iclass 7, count 0 2006.259.08:03:19.85#ibcon#wrote, iclass 7, count 0 2006.259.08:03:19.85#ibcon#about to read 3, iclass 7, count 0 2006.259.08:03:19.88#ibcon#read 3, iclass 7, count 0 2006.259.08:03:19.88#ibcon#about to read 4, iclass 7, count 0 2006.259.08:03:19.88#ibcon#read 4, iclass 7, count 0 2006.259.08:03:19.88#ibcon#about to read 5, iclass 7, count 0 2006.259.08:03:19.88#ibcon#read 5, iclass 7, count 0 2006.259.08:03:19.88#ibcon#about to read 6, iclass 7, count 0 2006.259.08:03:19.88#ibcon#read 6, iclass 7, count 0 2006.259.08:03:19.88#ibcon#end of sib2, iclass 7, count 0 2006.259.08:03:19.88#ibcon#*after write, iclass 7, count 0 2006.259.08:03:19.88#ibcon#*before return 0, iclass 7, count 0 2006.259.08:03:19.88#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.259.08:03:19.88#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.259.08:03:19.88#ibcon#about to clear, iclass 7 cls_cnt 0 2006.259.08:03:19.88#ibcon#cleared, iclass 7 cls_cnt 0 2006.259.08:03:19.88$vc4f8/valo=3,672.99 2006.259.08:03:19.88#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.259.08:03:19.88#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.259.08:03:19.88#ibcon#ireg 17 cls_cnt 0 2006.259.08:03:19.88#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.259.08:03:19.88#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.259.08:03:19.88#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.259.08:03:19.88#ibcon#enter wrdev, iclass 11, count 0 2006.259.08:03:19.88#ibcon#first serial, iclass 11, count 0 2006.259.08:03:19.88#ibcon#enter sib2, iclass 11, count 0 2006.259.08:03:19.88#ibcon#flushed, iclass 11, count 0 2006.259.08:03:19.88#ibcon#about to write, iclass 11, count 0 2006.259.08:03:19.88#ibcon#wrote, iclass 11, count 0 2006.259.08:03:19.88#ibcon#about to read 3, iclass 11, count 0 2006.259.08:03:19.90#ibcon#read 3, iclass 11, count 0 2006.259.08:03:19.90#ibcon#about to read 4, iclass 11, count 0 2006.259.08:03:19.90#ibcon#read 4, iclass 11, count 0 2006.259.08:03:19.90#ibcon#about to read 5, iclass 11, count 0 2006.259.08:03:19.90#ibcon#read 5, iclass 11, count 0 2006.259.08:03:19.90#ibcon#about to read 6, iclass 11, count 0 2006.259.08:03:19.90#ibcon#read 6, iclass 11, count 0 2006.259.08:03:19.90#ibcon#end of sib2, iclass 11, count 0 2006.259.08:03:19.90#ibcon#*mode == 0, iclass 11, count 0 2006.259.08:03:19.90#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.259.08:03:19.90#ibcon#[26=FRQ=03,672.99\r\n] 2006.259.08:03:19.90#ibcon#*before write, iclass 11, count 0 2006.259.08:03:19.90#ibcon#enter sib2, iclass 11, count 0 2006.259.08:03:19.90#ibcon#flushed, iclass 11, count 0 2006.259.08:03:19.90#ibcon#about to write, iclass 11, count 0 2006.259.08:03:19.90#ibcon#wrote, iclass 11, count 0 2006.259.08:03:19.90#ibcon#about to read 3, iclass 11, count 0 2006.259.08:03:19.94#ibcon#read 3, iclass 11, count 0 2006.259.08:03:19.94#ibcon#about to read 4, iclass 11, count 0 2006.259.08:03:19.94#ibcon#read 4, iclass 11, count 0 2006.259.08:03:19.94#ibcon#about to read 5, iclass 11, count 0 2006.259.08:03:19.94#ibcon#read 5, iclass 11, count 0 2006.259.08:03:19.94#ibcon#about to read 6, iclass 11, count 0 2006.259.08:03:19.94#ibcon#read 6, iclass 11, count 0 2006.259.08:03:19.94#ibcon#end of sib2, iclass 11, count 0 2006.259.08:03:19.94#ibcon#*after write, iclass 11, count 0 2006.259.08:03:19.94#ibcon#*before return 0, iclass 11, count 0 2006.259.08:03:19.94#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.259.08:03:19.94#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.259.08:03:19.94#ibcon#about to clear, iclass 11 cls_cnt 0 2006.259.08:03:19.94#ibcon#cleared, iclass 11 cls_cnt 0 2006.259.08:03:19.94$vc4f8/va=3,8 2006.259.08:03:19.94#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.259.08:03:19.94#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.259.08:03:19.94#ibcon#ireg 11 cls_cnt 2 2006.259.08:03:19.94#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.259.08:03:20.00#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.259.08:03:20.00#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.259.08:03:20.00#ibcon#enter wrdev, iclass 13, count 2 2006.259.08:03:20.00#ibcon#first serial, iclass 13, count 2 2006.259.08:03:20.00#ibcon#enter sib2, iclass 13, count 2 2006.259.08:03:20.00#ibcon#flushed, iclass 13, count 2 2006.259.08:03:20.00#ibcon#about to write, iclass 13, count 2 2006.259.08:03:20.00#ibcon#wrote, iclass 13, count 2 2006.259.08:03:20.00#ibcon#about to read 3, iclass 13, count 2 2006.259.08:03:20.02#ibcon#read 3, iclass 13, count 2 2006.259.08:03:20.02#ibcon#about to read 4, iclass 13, count 2 2006.259.08:03:20.02#ibcon#read 4, iclass 13, count 2 2006.259.08:03:20.02#ibcon#about to read 5, iclass 13, count 2 2006.259.08:03:20.02#ibcon#read 5, iclass 13, count 2 2006.259.08:03:20.02#ibcon#about to read 6, iclass 13, count 2 2006.259.08:03:20.02#ibcon#read 6, iclass 13, count 2 2006.259.08:03:20.02#ibcon#end of sib2, iclass 13, count 2 2006.259.08:03:20.02#ibcon#*mode == 0, iclass 13, count 2 2006.259.08:03:20.02#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.259.08:03:20.02#ibcon#[25=AT03-08\r\n] 2006.259.08:03:20.02#ibcon#*before write, iclass 13, count 2 2006.259.08:03:20.02#ibcon#enter sib2, iclass 13, count 2 2006.259.08:03:20.02#ibcon#flushed, iclass 13, count 2 2006.259.08:03:20.02#ibcon#about to write, iclass 13, count 2 2006.259.08:03:20.02#ibcon#wrote, iclass 13, count 2 2006.259.08:03:20.02#ibcon#about to read 3, iclass 13, count 2 2006.259.08:03:20.05#ibcon#read 3, iclass 13, count 2 2006.259.08:03:20.05#ibcon#about to read 4, iclass 13, count 2 2006.259.08:03:20.05#ibcon#read 4, iclass 13, count 2 2006.259.08:03:20.05#ibcon#about to read 5, iclass 13, count 2 2006.259.08:03:20.05#ibcon#read 5, iclass 13, count 2 2006.259.08:03:20.05#ibcon#about to read 6, iclass 13, count 2 2006.259.08:03:20.05#ibcon#read 6, iclass 13, count 2 2006.259.08:03:20.05#ibcon#end of sib2, iclass 13, count 2 2006.259.08:03:20.05#ibcon#*after write, iclass 13, count 2 2006.259.08:03:20.05#ibcon#*before return 0, iclass 13, count 2 2006.259.08:03:20.05#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.259.08:03:20.05#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.259.08:03:20.05#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.259.08:03:20.05#ibcon#ireg 7 cls_cnt 0 2006.259.08:03:20.05#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.259.08:03:20.17#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.259.08:03:20.17#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.259.08:03:20.17#ibcon#enter wrdev, iclass 13, count 0 2006.259.08:03:20.17#ibcon#first serial, iclass 13, count 0 2006.259.08:03:20.17#ibcon#enter sib2, iclass 13, count 0 2006.259.08:03:20.17#ibcon#flushed, iclass 13, count 0 2006.259.08:03:20.17#ibcon#about to write, iclass 13, count 0 2006.259.08:03:20.17#ibcon#wrote, iclass 13, count 0 2006.259.08:03:20.17#ibcon#about to read 3, iclass 13, count 0 2006.259.08:03:20.19#ibcon#read 3, iclass 13, count 0 2006.259.08:03:20.19#ibcon#about to read 4, iclass 13, count 0 2006.259.08:03:20.19#ibcon#read 4, iclass 13, count 0 2006.259.08:03:20.19#ibcon#about to read 5, iclass 13, count 0 2006.259.08:03:20.19#ibcon#read 5, iclass 13, count 0 2006.259.08:03:20.19#ibcon#about to read 6, iclass 13, count 0 2006.259.08:03:20.19#ibcon#read 6, iclass 13, count 0 2006.259.08:03:20.19#ibcon#end of sib2, iclass 13, count 0 2006.259.08:03:20.19#ibcon#*mode == 0, iclass 13, count 0 2006.259.08:03:20.19#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.259.08:03:20.19#ibcon#[25=USB\r\n] 2006.259.08:03:20.19#ibcon#*before write, iclass 13, count 0 2006.259.08:03:20.19#ibcon#enter sib2, iclass 13, count 0 2006.259.08:03:20.19#ibcon#flushed, iclass 13, count 0 2006.259.08:03:20.19#ibcon#about to write, iclass 13, count 0 2006.259.08:03:20.19#ibcon#wrote, iclass 13, count 0 2006.259.08:03:20.19#ibcon#about to read 3, iclass 13, count 0 2006.259.08:03:20.22#ibcon#read 3, iclass 13, count 0 2006.259.08:03:20.22#ibcon#about to read 4, iclass 13, count 0 2006.259.08:03:20.22#ibcon#read 4, iclass 13, count 0 2006.259.08:03:20.22#ibcon#about to read 5, iclass 13, count 0 2006.259.08:03:20.22#ibcon#read 5, iclass 13, count 0 2006.259.08:03:20.22#ibcon#about to read 6, iclass 13, count 0 2006.259.08:03:20.22#ibcon#read 6, iclass 13, count 0 2006.259.08:03:20.22#ibcon#end of sib2, iclass 13, count 0 2006.259.08:03:20.22#ibcon#*after write, iclass 13, count 0 2006.259.08:03:20.22#ibcon#*before return 0, iclass 13, count 0 2006.259.08:03:20.22#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.259.08:03:20.22#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.259.08:03:20.22#ibcon#about to clear, iclass 13 cls_cnt 0 2006.259.08:03:20.22#ibcon#cleared, iclass 13 cls_cnt 0 2006.259.08:03:20.22$vc4f8/valo=4,832.99 2006.259.08:03:20.22#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.259.08:03:20.22#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.259.08:03:20.22#ibcon#ireg 17 cls_cnt 0 2006.259.08:03:20.22#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.259.08:03:20.22#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.259.08:03:20.22#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.259.08:03:20.22#ibcon#enter wrdev, iclass 15, count 0 2006.259.08:03:20.22#ibcon#first serial, iclass 15, count 0 2006.259.08:03:20.22#ibcon#enter sib2, iclass 15, count 0 2006.259.08:03:20.22#ibcon#flushed, iclass 15, count 0 2006.259.08:03:20.22#ibcon#about to write, iclass 15, count 0 2006.259.08:03:20.22#ibcon#wrote, iclass 15, count 0 2006.259.08:03:20.22#ibcon#about to read 3, iclass 15, count 0 2006.259.08:03:20.24#ibcon#read 3, iclass 15, count 0 2006.259.08:03:20.24#ibcon#about to read 4, iclass 15, count 0 2006.259.08:03:20.24#ibcon#read 4, iclass 15, count 0 2006.259.08:03:20.24#ibcon#about to read 5, iclass 15, count 0 2006.259.08:03:20.24#ibcon#read 5, iclass 15, count 0 2006.259.08:03:20.24#ibcon#about to read 6, iclass 15, count 0 2006.259.08:03:20.24#ibcon#read 6, iclass 15, count 0 2006.259.08:03:20.24#ibcon#end of sib2, iclass 15, count 0 2006.259.08:03:20.24#ibcon#*mode == 0, iclass 15, count 0 2006.259.08:03:20.24#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.259.08:03:20.24#ibcon#[26=FRQ=04,832.99\r\n] 2006.259.08:03:20.24#ibcon#*before write, iclass 15, count 0 2006.259.08:03:20.24#ibcon#enter sib2, iclass 15, count 0 2006.259.08:03:20.24#ibcon#flushed, iclass 15, count 0 2006.259.08:03:20.24#ibcon#about to write, iclass 15, count 0 2006.259.08:03:20.24#ibcon#wrote, iclass 15, count 0 2006.259.08:03:20.24#ibcon#about to read 3, iclass 15, count 0 2006.259.08:03:20.28#ibcon#read 3, iclass 15, count 0 2006.259.08:03:20.28#ibcon#about to read 4, iclass 15, count 0 2006.259.08:03:20.28#ibcon#read 4, iclass 15, count 0 2006.259.08:03:20.28#ibcon#about to read 5, iclass 15, count 0 2006.259.08:03:20.28#ibcon#read 5, iclass 15, count 0 2006.259.08:03:20.28#ibcon#about to read 6, iclass 15, count 0 2006.259.08:03:20.28#ibcon#read 6, iclass 15, count 0 2006.259.08:03:20.28#ibcon#end of sib2, iclass 15, count 0 2006.259.08:03:20.28#ibcon#*after write, iclass 15, count 0 2006.259.08:03:20.28#ibcon#*before return 0, iclass 15, count 0 2006.259.08:03:20.28#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.259.08:03:20.28#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.259.08:03:20.28#ibcon#about to clear, iclass 15 cls_cnt 0 2006.259.08:03:20.28#ibcon#cleared, iclass 15 cls_cnt 0 2006.259.08:03:20.28$vc4f8/va=4,7 2006.259.08:03:20.28#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.259.08:03:20.28#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.259.08:03:20.28#ibcon#ireg 11 cls_cnt 2 2006.259.08:03:20.28#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.259.08:03:20.34#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.259.08:03:20.34#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.259.08:03:20.34#ibcon#enter wrdev, iclass 17, count 2 2006.259.08:03:20.34#ibcon#first serial, iclass 17, count 2 2006.259.08:03:20.34#ibcon#enter sib2, iclass 17, count 2 2006.259.08:03:20.34#ibcon#flushed, iclass 17, count 2 2006.259.08:03:20.34#ibcon#about to write, iclass 17, count 2 2006.259.08:03:20.34#ibcon#wrote, iclass 17, count 2 2006.259.08:03:20.34#ibcon#about to read 3, iclass 17, count 2 2006.259.08:03:20.36#ibcon#read 3, iclass 17, count 2 2006.259.08:03:20.36#ibcon#about to read 4, iclass 17, count 2 2006.259.08:03:20.36#ibcon#read 4, iclass 17, count 2 2006.259.08:03:20.36#ibcon#about to read 5, iclass 17, count 2 2006.259.08:03:20.36#ibcon#read 5, iclass 17, count 2 2006.259.08:03:20.36#ibcon#about to read 6, iclass 17, count 2 2006.259.08:03:20.36#ibcon#read 6, iclass 17, count 2 2006.259.08:03:20.36#ibcon#end of sib2, iclass 17, count 2 2006.259.08:03:20.36#ibcon#*mode == 0, iclass 17, count 2 2006.259.08:03:20.36#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.259.08:03:20.36#ibcon#[25=AT04-07\r\n] 2006.259.08:03:20.36#ibcon#*before write, iclass 17, count 2 2006.259.08:03:20.36#ibcon#enter sib2, iclass 17, count 2 2006.259.08:03:20.36#ibcon#flushed, iclass 17, count 2 2006.259.08:03:20.36#ibcon#about to write, iclass 17, count 2 2006.259.08:03:20.36#ibcon#wrote, iclass 17, count 2 2006.259.08:03:20.36#ibcon#about to read 3, iclass 17, count 2 2006.259.08:03:20.39#ibcon#read 3, iclass 17, count 2 2006.259.08:03:20.39#ibcon#about to read 4, iclass 17, count 2 2006.259.08:03:20.39#ibcon#read 4, iclass 17, count 2 2006.259.08:03:20.39#ibcon#about to read 5, iclass 17, count 2 2006.259.08:03:20.39#ibcon#read 5, iclass 17, count 2 2006.259.08:03:20.39#ibcon#about to read 6, iclass 17, count 2 2006.259.08:03:20.39#ibcon#read 6, iclass 17, count 2 2006.259.08:03:20.39#ibcon#end of sib2, iclass 17, count 2 2006.259.08:03:20.39#ibcon#*after write, iclass 17, count 2 2006.259.08:03:20.39#ibcon#*before return 0, iclass 17, count 2 2006.259.08:03:20.39#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.259.08:03:20.39#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.259.08:03:20.39#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.259.08:03:20.39#ibcon#ireg 7 cls_cnt 0 2006.259.08:03:20.39#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.259.08:03:20.51#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.259.08:03:20.51#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.259.08:03:20.51#ibcon#enter wrdev, iclass 17, count 0 2006.259.08:03:20.51#ibcon#first serial, iclass 17, count 0 2006.259.08:03:20.51#ibcon#enter sib2, iclass 17, count 0 2006.259.08:03:20.51#ibcon#flushed, iclass 17, count 0 2006.259.08:03:20.51#ibcon#about to write, iclass 17, count 0 2006.259.08:03:20.51#ibcon#wrote, iclass 17, count 0 2006.259.08:03:20.51#ibcon#about to read 3, iclass 17, count 0 2006.259.08:03:20.53#ibcon#read 3, iclass 17, count 0 2006.259.08:03:20.53#ibcon#about to read 4, iclass 17, count 0 2006.259.08:03:20.53#ibcon#read 4, iclass 17, count 0 2006.259.08:03:20.53#ibcon#about to read 5, iclass 17, count 0 2006.259.08:03:20.53#ibcon#read 5, iclass 17, count 0 2006.259.08:03:20.53#ibcon#about to read 6, iclass 17, count 0 2006.259.08:03:20.53#ibcon#read 6, iclass 17, count 0 2006.259.08:03:20.53#ibcon#end of sib2, iclass 17, count 0 2006.259.08:03:20.53#ibcon#*mode == 0, iclass 17, count 0 2006.259.08:03:20.53#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.259.08:03:20.53#ibcon#[25=USB\r\n] 2006.259.08:03:20.53#ibcon#*before write, iclass 17, count 0 2006.259.08:03:20.53#ibcon#enter sib2, iclass 17, count 0 2006.259.08:03:20.53#ibcon#flushed, iclass 17, count 0 2006.259.08:03:20.53#ibcon#about to write, iclass 17, count 0 2006.259.08:03:20.53#ibcon#wrote, iclass 17, count 0 2006.259.08:03:20.53#ibcon#about to read 3, iclass 17, count 0 2006.259.08:03:20.56#ibcon#read 3, iclass 17, count 0 2006.259.08:03:20.56#ibcon#about to read 4, iclass 17, count 0 2006.259.08:03:20.56#ibcon#read 4, iclass 17, count 0 2006.259.08:03:20.56#ibcon#about to read 5, iclass 17, count 0 2006.259.08:03:20.56#ibcon#read 5, iclass 17, count 0 2006.259.08:03:20.56#ibcon#about to read 6, iclass 17, count 0 2006.259.08:03:20.56#ibcon#read 6, iclass 17, count 0 2006.259.08:03:20.56#ibcon#end of sib2, iclass 17, count 0 2006.259.08:03:20.56#ibcon#*after write, iclass 17, count 0 2006.259.08:03:20.56#ibcon#*before return 0, iclass 17, count 0 2006.259.08:03:20.56#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.259.08:03:20.56#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.259.08:03:20.56#ibcon#about to clear, iclass 17 cls_cnt 0 2006.259.08:03:20.56#ibcon#cleared, iclass 17 cls_cnt 0 2006.259.08:03:20.56$vc4f8/valo=5,652.99 2006.259.08:03:20.56#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.259.08:03:20.56#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.259.08:03:20.56#ibcon#ireg 17 cls_cnt 0 2006.259.08:03:20.56#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.259.08:03:20.56#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.259.08:03:20.56#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.259.08:03:20.56#ibcon#enter wrdev, iclass 19, count 0 2006.259.08:03:20.56#ibcon#first serial, iclass 19, count 0 2006.259.08:03:20.56#ibcon#enter sib2, iclass 19, count 0 2006.259.08:03:20.56#ibcon#flushed, iclass 19, count 0 2006.259.08:03:20.56#ibcon#about to write, iclass 19, count 0 2006.259.08:03:20.56#ibcon#wrote, iclass 19, count 0 2006.259.08:03:20.56#ibcon#about to read 3, iclass 19, count 0 2006.259.08:03:20.58#ibcon#read 3, iclass 19, count 0 2006.259.08:03:20.58#ibcon#about to read 4, iclass 19, count 0 2006.259.08:03:20.58#ibcon#read 4, iclass 19, count 0 2006.259.08:03:20.58#ibcon#about to read 5, iclass 19, count 0 2006.259.08:03:20.58#ibcon#read 5, iclass 19, count 0 2006.259.08:03:20.58#ibcon#about to read 6, iclass 19, count 0 2006.259.08:03:20.58#ibcon#read 6, iclass 19, count 0 2006.259.08:03:20.58#ibcon#end of sib2, iclass 19, count 0 2006.259.08:03:20.58#ibcon#*mode == 0, iclass 19, count 0 2006.259.08:03:20.58#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.259.08:03:20.58#ibcon#[26=FRQ=05,652.99\r\n] 2006.259.08:03:20.58#ibcon#*before write, iclass 19, count 0 2006.259.08:03:20.58#ibcon#enter sib2, iclass 19, count 0 2006.259.08:03:20.58#ibcon#flushed, iclass 19, count 0 2006.259.08:03:20.58#ibcon#about to write, iclass 19, count 0 2006.259.08:03:20.58#ibcon#wrote, iclass 19, count 0 2006.259.08:03:20.58#ibcon#about to read 3, iclass 19, count 0 2006.259.08:03:20.62#ibcon#read 3, iclass 19, count 0 2006.259.08:03:20.62#ibcon#about to read 4, iclass 19, count 0 2006.259.08:03:20.62#ibcon#read 4, iclass 19, count 0 2006.259.08:03:20.62#ibcon#about to read 5, iclass 19, count 0 2006.259.08:03:20.62#ibcon#read 5, iclass 19, count 0 2006.259.08:03:20.62#ibcon#about to read 6, iclass 19, count 0 2006.259.08:03:20.62#ibcon#read 6, iclass 19, count 0 2006.259.08:03:20.62#ibcon#end of sib2, iclass 19, count 0 2006.259.08:03:20.62#ibcon#*after write, iclass 19, count 0 2006.259.08:03:20.62#ibcon#*before return 0, iclass 19, count 0 2006.259.08:03:20.62#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.259.08:03:20.62#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.259.08:03:20.62#ibcon#about to clear, iclass 19 cls_cnt 0 2006.259.08:03:20.62#ibcon#cleared, iclass 19 cls_cnt 0 2006.259.08:03:20.62$vc4f8/va=5,7 2006.259.08:03:20.62#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.259.08:03:20.62#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.259.08:03:20.62#ibcon#ireg 11 cls_cnt 2 2006.259.08:03:20.62#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.259.08:03:20.68#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.259.08:03:20.68#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.259.08:03:20.68#ibcon#enter wrdev, iclass 21, count 2 2006.259.08:03:20.68#ibcon#first serial, iclass 21, count 2 2006.259.08:03:20.68#ibcon#enter sib2, iclass 21, count 2 2006.259.08:03:20.68#ibcon#flushed, iclass 21, count 2 2006.259.08:03:20.68#ibcon#about to write, iclass 21, count 2 2006.259.08:03:20.68#ibcon#wrote, iclass 21, count 2 2006.259.08:03:20.68#ibcon#about to read 3, iclass 21, count 2 2006.259.08:03:20.70#ibcon#read 3, iclass 21, count 2 2006.259.08:03:20.70#ibcon#about to read 4, iclass 21, count 2 2006.259.08:03:20.70#ibcon#read 4, iclass 21, count 2 2006.259.08:03:20.70#ibcon#about to read 5, iclass 21, count 2 2006.259.08:03:20.70#ibcon#read 5, iclass 21, count 2 2006.259.08:03:20.70#ibcon#about to read 6, iclass 21, count 2 2006.259.08:03:20.70#ibcon#read 6, iclass 21, count 2 2006.259.08:03:20.70#ibcon#end of sib2, iclass 21, count 2 2006.259.08:03:20.70#ibcon#*mode == 0, iclass 21, count 2 2006.259.08:03:20.70#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.259.08:03:20.70#ibcon#[25=AT05-07\r\n] 2006.259.08:03:20.70#ibcon#*before write, iclass 21, count 2 2006.259.08:03:20.70#ibcon#enter sib2, iclass 21, count 2 2006.259.08:03:20.70#ibcon#flushed, iclass 21, count 2 2006.259.08:03:20.70#ibcon#about to write, iclass 21, count 2 2006.259.08:03:20.70#ibcon#wrote, iclass 21, count 2 2006.259.08:03:20.70#ibcon#about to read 3, iclass 21, count 2 2006.259.08:03:20.73#ibcon#read 3, iclass 21, count 2 2006.259.08:03:20.73#ibcon#about to read 4, iclass 21, count 2 2006.259.08:03:20.73#ibcon#read 4, iclass 21, count 2 2006.259.08:03:20.73#ibcon#about to read 5, iclass 21, count 2 2006.259.08:03:20.73#ibcon#read 5, iclass 21, count 2 2006.259.08:03:20.73#ibcon#about to read 6, iclass 21, count 2 2006.259.08:03:20.73#ibcon#read 6, iclass 21, count 2 2006.259.08:03:20.73#ibcon#end of sib2, iclass 21, count 2 2006.259.08:03:20.73#ibcon#*after write, iclass 21, count 2 2006.259.08:03:20.73#ibcon#*before return 0, iclass 21, count 2 2006.259.08:03:20.73#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.259.08:03:20.73#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.259.08:03:20.73#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.259.08:03:20.73#ibcon#ireg 7 cls_cnt 0 2006.259.08:03:20.73#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.259.08:03:20.85#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.259.08:03:20.85#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.259.08:03:20.85#ibcon#enter wrdev, iclass 21, count 0 2006.259.08:03:20.85#ibcon#first serial, iclass 21, count 0 2006.259.08:03:20.85#ibcon#enter sib2, iclass 21, count 0 2006.259.08:03:20.85#ibcon#flushed, iclass 21, count 0 2006.259.08:03:20.85#ibcon#about to write, iclass 21, count 0 2006.259.08:03:20.85#ibcon#wrote, iclass 21, count 0 2006.259.08:03:20.85#ibcon#about to read 3, iclass 21, count 0 2006.259.08:03:20.87#ibcon#read 3, iclass 21, count 0 2006.259.08:03:20.87#ibcon#about to read 4, iclass 21, count 0 2006.259.08:03:20.87#ibcon#read 4, iclass 21, count 0 2006.259.08:03:20.87#ibcon#about to read 5, iclass 21, count 0 2006.259.08:03:20.87#ibcon#read 5, iclass 21, count 0 2006.259.08:03:20.87#ibcon#about to read 6, iclass 21, count 0 2006.259.08:03:20.87#ibcon#read 6, iclass 21, count 0 2006.259.08:03:20.87#ibcon#end of sib2, iclass 21, count 0 2006.259.08:03:20.87#ibcon#*mode == 0, iclass 21, count 0 2006.259.08:03:20.87#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.259.08:03:20.87#ibcon#[25=USB\r\n] 2006.259.08:03:20.87#ibcon#*before write, iclass 21, count 0 2006.259.08:03:20.87#ibcon#enter sib2, iclass 21, count 0 2006.259.08:03:20.87#ibcon#flushed, iclass 21, count 0 2006.259.08:03:20.87#ibcon#about to write, iclass 21, count 0 2006.259.08:03:20.87#ibcon#wrote, iclass 21, count 0 2006.259.08:03:20.87#ibcon#about to read 3, iclass 21, count 0 2006.259.08:03:20.90#ibcon#read 3, iclass 21, count 0 2006.259.08:03:20.90#ibcon#about to read 4, iclass 21, count 0 2006.259.08:03:20.90#ibcon#read 4, iclass 21, count 0 2006.259.08:03:20.90#ibcon#about to read 5, iclass 21, count 0 2006.259.08:03:20.90#ibcon#read 5, iclass 21, count 0 2006.259.08:03:20.90#ibcon#about to read 6, iclass 21, count 0 2006.259.08:03:20.90#ibcon#read 6, iclass 21, count 0 2006.259.08:03:20.90#ibcon#end of sib2, iclass 21, count 0 2006.259.08:03:20.90#ibcon#*after write, iclass 21, count 0 2006.259.08:03:20.90#ibcon#*before return 0, iclass 21, count 0 2006.259.08:03:20.90#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.259.08:03:20.90#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.259.08:03:20.90#ibcon#about to clear, iclass 21 cls_cnt 0 2006.259.08:03:20.90#ibcon#cleared, iclass 21 cls_cnt 0 2006.259.08:03:20.90$vc4f8/valo=6,772.99 2006.259.08:03:20.90#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.259.08:03:20.90#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.259.08:03:20.90#ibcon#ireg 17 cls_cnt 0 2006.259.08:03:20.90#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.259.08:03:20.90#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.259.08:03:20.90#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.259.08:03:20.90#ibcon#enter wrdev, iclass 23, count 0 2006.259.08:03:20.90#ibcon#first serial, iclass 23, count 0 2006.259.08:03:20.90#ibcon#enter sib2, iclass 23, count 0 2006.259.08:03:20.90#ibcon#flushed, iclass 23, count 0 2006.259.08:03:20.90#ibcon#about to write, iclass 23, count 0 2006.259.08:03:20.90#ibcon#wrote, iclass 23, count 0 2006.259.08:03:20.90#ibcon#about to read 3, iclass 23, count 0 2006.259.08:03:20.92#ibcon#read 3, iclass 23, count 0 2006.259.08:03:20.92#ibcon#about to read 4, iclass 23, count 0 2006.259.08:03:20.92#ibcon#read 4, iclass 23, count 0 2006.259.08:03:20.92#ibcon#about to read 5, iclass 23, count 0 2006.259.08:03:20.92#ibcon#read 5, iclass 23, count 0 2006.259.08:03:20.92#ibcon#about to read 6, iclass 23, count 0 2006.259.08:03:20.92#ibcon#read 6, iclass 23, count 0 2006.259.08:03:20.92#ibcon#end of sib2, iclass 23, count 0 2006.259.08:03:20.92#ibcon#*mode == 0, iclass 23, count 0 2006.259.08:03:20.92#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.259.08:03:20.92#ibcon#[26=FRQ=06,772.99\r\n] 2006.259.08:03:20.92#ibcon#*before write, iclass 23, count 0 2006.259.08:03:20.92#ibcon#enter sib2, iclass 23, count 0 2006.259.08:03:20.92#ibcon#flushed, iclass 23, count 0 2006.259.08:03:20.92#ibcon#about to write, iclass 23, count 0 2006.259.08:03:20.92#ibcon#wrote, iclass 23, count 0 2006.259.08:03:20.92#ibcon#about to read 3, iclass 23, count 0 2006.259.08:03:20.96#ibcon#read 3, iclass 23, count 0 2006.259.08:03:20.96#ibcon#about to read 4, iclass 23, count 0 2006.259.08:03:20.96#ibcon#read 4, iclass 23, count 0 2006.259.08:03:20.96#ibcon#about to read 5, iclass 23, count 0 2006.259.08:03:20.96#ibcon#read 5, iclass 23, count 0 2006.259.08:03:20.96#ibcon#about to read 6, iclass 23, count 0 2006.259.08:03:20.96#ibcon#read 6, iclass 23, count 0 2006.259.08:03:20.96#ibcon#end of sib2, iclass 23, count 0 2006.259.08:03:20.96#ibcon#*after write, iclass 23, count 0 2006.259.08:03:20.96#ibcon#*before return 0, iclass 23, count 0 2006.259.08:03:20.96#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.259.08:03:20.96#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.259.08:03:20.96#ibcon#about to clear, iclass 23 cls_cnt 0 2006.259.08:03:20.96#ibcon#cleared, iclass 23 cls_cnt 0 2006.259.08:03:20.96$vc4f8/va=6,6 2006.259.08:03:20.96#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.259.08:03:20.96#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.259.08:03:20.96#ibcon#ireg 11 cls_cnt 2 2006.259.08:03:20.96#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.259.08:03:21.02#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.259.08:03:21.02#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.259.08:03:21.02#ibcon#enter wrdev, iclass 25, count 2 2006.259.08:03:21.02#ibcon#first serial, iclass 25, count 2 2006.259.08:03:21.02#ibcon#enter sib2, iclass 25, count 2 2006.259.08:03:21.02#ibcon#flushed, iclass 25, count 2 2006.259.08:03:21.02#ibcon#about to write, iclass 25, count 2 2006.259.08:03:21.02#ibcon#wrote, iclass 25, count 2 2006.259.08:03:21.02#ibcon#about to read 3, iclass 25, count 2 2006.259.08:03:21.04#ibcon#read 3, iclass 25, count 2 2006.259.08:03:21.04#ibcon#about to read 4, iclass 25, count 2 2006.259.08:03:21.04#ibcon#read 4, iclass 25, count 2 2006.259.08:03:21.04#ibcon#about to read 5, iclass 25, count 2 2006.259.08:03:21.04#ibcon#read 5, iclass 25, count 2 2006.259.08:03:21.04#ibcon#about to read 6, iclass 25, count 2 2006.259.08:03:21.04#ibcon#read 6, iclass 25, count 2 2006.259.08:03:21.04#ibcon#end of sib2, iclass 25, count 2 2006.259.08:03:21.04#ibcon#*mode == 0, iclass 25, count 2 2006.259.08:03:21.04#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.259.08:03:21.04#ibcon#[25=AT06-06\r\n] 2006.259.08:03:21.04#ibcon#*before write, iclass 25, count 2 2006.259.08:03:21.04#ibcon#enter sib2, iclass 25, count 2 2006.259.08:03:21.04#ibcon#flushed, iclass 25, count 2 2006.259.08:03:21.04#ibcon#about to write, iclass 25, count 2 2006.259.08:03:21.04#ibcon#wrote, iclass 25, count 2 2006.259.08:03:21.04#ibcon#about to read 3, iclass 25, count 2 2006.259.08:03:21.07#ibcon#read 3, iclass 25, count 2 2006.259.08:03:21.07#ibcon#about to read 4, iclass 25, count 2 2006.259.08:03:21.07#ibcon#read 4, iclass 25, count 2 2006.259.08:03:21.07#ibcon#about to read 5, iclass 25, count 2 2006.259.08:03:21.07#ibcon#read 5, iclass 25, count 2 2006.259.08:03:21.07#ibcon#about to read 6, iclass 25, count 2 2006.259.08:03:21.07#ibcon#read 6, iclass 25, count 2 2006.259.08:03:21.07#ibcon#end of sib2, iclass 25, count 2 2006.259.08:03:21.07#ibcon#*after write, iclass 25, count 2 2006.259.08:03:21.07#ibcon#*before return 0, iclass 25, count 2 2006.259.08:03:21.07#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.259.08:03:21.07#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.259.08:03:21.07#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.259.08:03:21.07#ibcon#ireg 7 cls_cnt 0 2006.259.08:03:21.07#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.259.08:03:21.19#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.259.08:03:21.19#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.259.08:03:21.19#ibcon#enter wrdev, iclass 25, count 0 2006.259.08:03:21.19#ibcon#first serial, iclass 25, count 0 2006.259.08:03:21.19#ibcon#enter sib2, iclass 25, count 0 2006.259.08:03:21.19#ibcon#flushed, iclass 25, count 0 2006.259.08:03:21.19#ibcon#about to write, iclass 25, count 0 2006.259.08:03:21.19#ibcon#wrote, iclass 25, count 0 2006.259.08:03:21.19#ibcon#about to read 3, iclass 25, count 0 2006.259.08:03:21.21#ibcon#read 3, iclass 25, count 0 2006.259.08:03:21.21#ibcon#about to read 4, iclass 25, count 0 2006.259.08:03:21.21#ibcon#read 4, iclass 25, count 0 2006.259.08:03:21.21#ibcon#about to read 5, iclass 25, count 0 2006.259.08:03:21.21#ibcon#read 5, iclass 25, count 0 2006.259.08:03:21.21#ibcon#about to read 6, iclass 25, count 0 2006.259.08:03:21.21#ibcon#read 6, iclass 25, count 0 2006.259.08:03:21.21#ibcon#end of sib2, iclass 25, count 0 2006.259.08:03:21.21#ibcon#*mode == 0, iclass 25, count 0 2006.259.08:03:21.21#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.259.08:03:21.21#ibcon#[25=USB\r\n] 2006.259.08:03:21.21#ibcon#*before write, iclass 25, count 0 2006.259.08:03:21.21#ibcon#enter sib2, iclass 25, count 0 2006.259.08:03:21.21#ibcon#flushed, iclass 25, count 0 2006.259.08:03:21.21#ibcon#about to write, iclass 25, count 0 2006.259.08:03:21.21#ibcon#wrote, iclass 25, count 0 2006.259.08:03:21.21#ibcon#about to read 3, iclass 25, count 0 2006.259.08:03:21.24#ibcon#read 3, iclass 25, count 0 2006.259.08:03:21.24#ibcon#about to read 4, iclass 25, count 0 2006.259.08:03:21.24#ibcon#read 4, iclass 25, count 0 2006.259.08:03:21.24#ibcon#about to read 5, iclass 25, count 0 2006.259.08:03:21.24#ibcon#read 5, iclass 25, count 0 2006.259.08:03:21.24#ibcon#about to read 6, iclass 25, count 0 2006.259.08:03:21.24#ibcon#read 6, iclass 25, count 0 2006.259.08:03:21.24#ibcon#end of sib2, iclass 25, count 0 2006.259.08:03:21.24#ibcon#*after write, iclass 25, count 0 2006.259.08:03:21.24#ibcon#*before return 0, iclass 25, count 0 2006.259.08:03:21.24#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.259.08:03:21.24#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.259.08:03:21.24#ibcon#about to clear, iclass 25 cls_cnt 0 2006.259.08:03:21.24#ibcon#cleared, iclass 25 cls_cnt 0 2006.259.08:03:21.24$vc4f8/valo=7,832.99 2006.259.08:03:21.24#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.259.08:03:21.24#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.259.08:03:21.24#ibcon#ireg 17 cls_cnt 0 2006.259.08:03:21.24#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.259.08:03:21.24#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.259.08:03:21.24#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.259.08:03:21.24#ibcon#enter wrdev, iclass 27, count 0 2006.259.08:03:21.24#ibcon#first serial, iclass 27, count 0 2006.259.08:03:21.24#ibcon#enter sib2, iclass 27, count 0 2006.259.08:03:21.24#ibcon#flushed, iclass 27, count 0 2006.259.08:03:21.24#ibcon#about to write, iclass 27, count 0 2006.259.08:03:21.24#ibcon#wrote, iclass 27, count 0 2006.259.08:03:21.24#ibcon#about to read 3, iclass 27, count 0 2006.259.08:03:21.26#ibcon#read 3, iclass 27, count 0 2006.259.08:03:21.26#ibcon#about to read 4, iclass 27, count 0 2006.259.08:03:21.26#ibcon#read 4, iclass 27, count 0 2006.259.08:03:21.26#ibcon#about to read 5, iclass 27, count 0 2006.259.08:03:21.26#ibcon#read 5, iclass 27, count 0 2006.259.08:03:21.26#ibcon#about to read 6, iclass 27, count 0 2006.259.08:03:21.26#ibcon#read 6, iclass 27, count 0 2006.259.08:03:21.26#ibcon#end of sib2, iclass 27, count 0 2006.259.08:03:21.26#ibcon#*mode == 0, iclass 27, count 0 2006.259.08:03:21.26#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.259.08:03:21.26#ibcon#[26=FRQ=07,832.99\r\n] 2006.259.08:03:21.26#ibcon#*before write, iclass 27, count 0 2006.259.08:03:21.26#ibcon#enter sib2, iclass 27, count 0 2006.259.08:03:21.26#ibcon#flushed, iclass 27, count 0 2006.259.08:03:21.26#ibcon#about to write, iclass 27, count 0 2006.259.08:03:21.26#ibcon#wrote, iclass 27, count 0 2006.259.08:03:21.26#ibcon#about to read 3, iclass 27, count 0 2006.259.08:03:21.30#ibcon#read 3, iclass 27, count 0 2006.259.08:03:21.30#ibcon#about to read 4, iclass 27, count 0 2006.259.08:03:21.30#ibcon#read 4, iclass 27, count 0 2006.259.08:03:21.30#ibcon#about to read 5, iclass 27, count 0 2006.259.08:03:21.30#ibcon#read 5, iclass 27, count 0 2006.259.08:03:21.30#ibcon#about to read 6, iclass 27, count 0 2006.259.08:03:21.30#ibcon#read 6, iclass 27, count 0 2006.259.08:03:21.30#ibcon#end of sib2, iclass 27, count 0 2006.259.08:03:21.30#ibcon#*after write, iclass 27, count 0 2006.259.08:03:21.30#ibcon#*before return 0, iclass 27, count 0 2006.259.08:03:21.30#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.259.08:03:21.30#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.259.08:03:21.30#ibcon#about to clear, iclass 27 cls_cnt 0 2006.259.08:03:21.30#ibcon#cleared, iclass 27 cls_cnt 0 2006.259.08:03:21.30$vc4f8/va=7,6 2006.259.08:03:21.30#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.259.08:03:21.30#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.259.08:03:21.30#ibcon#ireg 11 cls_cnt 2 2006.259.08:03:21.30#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.259.08:03:21.36#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.259.08:03:21.36#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.259.08:03:21.36#ibcon#enter wrdev, iclass 29, count 2 2006.259.08:03:21.36#ibcon#first serial, iclass 29, count 2 2006.259.08:03:21.36#ibcon#enter sib2, iclass 29, count 2 2006.259.08:03:21.36#ibcon#flushed, iclass 29, count 2 2006.259.08:03:21.36#ibcon#about to write, iclass 29, count 2 2006.259.08:03:21.36#ibcon#wrote, iclass 29, count 2 2006.259.08:03:21.36#ibcon#about to read 3, iclass 29, count 2 2006.259.08:03:21.38#ibcon#read 3, iclass 29, count 2 2006.259.08:03:21.38#ibcon#about to read 4, iclass 29, count 2 2006.259.08:03:21.38#ibcon#read 4, iclass 29, count 2 2006.259.08:03:21.38#ibcon#about to read 5, iclass 29, count 2 2006.259.08:03:21.38#ibcon#read 5, iclass 29, count 2 2006.259.08:03:21.38#ibcon#about to read 6, iclass 29, count 2 2006.259.08:03:21.38#ibcon#read 6, iclass 29, count 2 2006.259.08:03:21.38#ibcon#end of sib2, iclass 29, count 2 2006.259.08:03:21.38#ibcon#*mode == 0, iclass 29, count 2 2006.259.08:03:21.38#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.259.08:03:21.38#ibcon#[25=AT07-06\r\n] 2006.259.08:03:21.38#ibcon#*before write, iclass 29, count 2 2006.259.08:03:21.38#ibcon#enter sib2, iclass 29, count 2 2006.259.08:03:21.38#ibcon#flushed, iclass 29, count 2 2006.259.08:03:21.38#ibcon#about to write, iclass 29, count 2 2006.259.08:03:21.38#ibcon#wrote, iclass 29, count 2 2006.259.08:03:21.38#ibcon#about to read 3, iclass 29, count 2 2006.259.08:03:21.41#ibcon#read 3, iclass 29, count 2 2006.259.08:03:21.41#ibcon#about to read 4, iclass 29, count 2 2006.259.08:03:21.41#ibcon#read 4, iclass 29, count 2 2006.259.08:03:21.41#ibcon#about to read 5, iclass 29, count 2 2006.259.08:03:21.41#ibcon#read 5, iclass 29, count 2 2006.259.08:03:21.41#ibcon#about to read 6, iclass 29, count 2 2006.259.08:03:21.41#ibcon#read 6, iclass 29, count 2 2006.259.08:03:21.41#ibcon#end of sib2, iclass 29, count 2 2006.259.08:03:21.41#ibcon#*after write, iclass 29, count 2 2006.259.08:03:21.41#ibcon#*before return 0, iclass 29, count 2 2006.259.08:03:21.41#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.259.08:03:21.41#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.259.08:03:21.41#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.259.08:03:21.41#ibcon#ireg 7 cls_cnt 0 2006.259.08:03:21.41#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.259.08:03:21.53#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.259.08:03:21.53#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.259.08:03:21.53#ibcon#enter wrdev, iclass 29, count 0 2006.259.08:03:21.53#ibcon#first serial, iclass 29, count 0 2006.259.08:03:21.53#ibcon#enter sib2, iclass 29, count 0 2006.259.08:03:21.53#ibcon#flushed, iclass 29, count 0 2006.259.08:03:21.53#ibcon#about to write, iclass 29, count 0 2006.259.08:03:21.53#ibcon#wrote, iclass 29, count 0 2006.259.08:03:21.53#ibcon#about to read 3, iclass 29, count 0 2006.259.08:03:21.55#ibcon#read 3, iclass 29, count 0 2006.259.08:03:21.55#ibcon#about to read 4, iclass 29, count 0 2006.259.08:03:21.55#ibcon#read 4, iclass 29, count 0 2006.259.08:03:21.55#ibcon#about to read 5, iclass 29, count 0 2006.259.08:03:21.55#ibcon#read 5, iclass 29, count 0 2006.259.08:03:21.55#ibcon#about to read 6, iclass 29, count 0 2006.259.08:03:21.55#ibcon#read 6, iclass 29, count 0 2006.259.08:03:21.55#ibcon#end of sib2, iclass 29, count 0 2006.259.08:03:21.55#ibcon#*mode == 0, iclass 29, count 0 2006.259.08:03:21.55#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.259.08:03:21.55#ibcon#[25=USB\r\n] 2006.259.08:03:21.55#ibcon#*before write, iclass 29, count 0 2006.259.08:03:21.55#ibcon#enter sib2, iclass 29, count 0 2006.259.08:03:21.55#ibcon#flushed, iclass 29, count 0 2006.259.08:03:21.55#ibcon#about to write, iclass 29, count 0 2006.259.08:03:21.55#ibcon#wrote, iclass 29, count 0 2006.259.08:03:21.55#ibcon#about to read 3, iclass 29, count 0 2006.259.08:03:21.58#ibcon#read 3, iclass 29, count 0 2006.259.08:03:21.58#ibcon#about to read 4, iclass 29, count 0 2006.259.08:03:21.58#ibcon#read 4, iclass 29, count 0 2006.259.08:03:21.58#ibcon#about to read 5, iclass 29, count 0 2006.259.08:03:21.58#ibcon#read 5, iclass 29, count 0 2006.259.08:03:21.58#ibcon#about to read 6, iclass 29, count 0 2006.259.08:03:21.58#ibcon#read 6, iclass 29, count 0 2006.259.08:03:21.58#ibcon#end of sib2, iclass 29, count 0 2006.259.08:03:21.58#ibcon#*after write, iclass 29, count 0 2006.259.08:03:21.58#ibcon#*before return 0, iclass 29, count 0 2006.259.08:03:21.58#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.259.08:03:21.58#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.259.08:03:21.58#ibcon#about to clear, iclass 29 cls_cnt 0 2006.259.08:03:21.58#ibcon#cleared, iclass 29 cls_cnt 0 2006.259.08:03:21.58$vc4f8/valo=8,852.99 2006.259.08:03:21.58#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.259.08:03:21.58#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.259.08:03:21.58#ibcon#ireg 17 cls_cnt 0 2006.259.08:03:21.58#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.259.08:03:21.58#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.259.08:03:21.58#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.259.08:03:21.58#ibcon#enter wrdev, iclass 31, count 0 2006.259.08:03:21.58#ibcon#first serial, iclass 31, count 0 2006.259.08:03:21.58#ibcon#enter sib2, iclass 31, count 0 2006.259.08:03:21.58#ibcon#flushed, iclass 31, count 0 2006.259.08:03:21.58#ibcon#about to write, iclass 31, count 0 2006.259.08:03:21.58#ibcon#wrote, iclass 31, count 0 2006.259.08:03:21.58#ibcon#about to read 3, iclass 31, count 0 2006.259.08:03:21.60#ibcon#read 3, iclass 31, count 0 2006.259.08:03:21.60#ibcon#about to read 4, iclass 31, count 0 2006.259.08:03:21.60#ibcon#read 4, iclass 31, count 0 2006.259.08:03:21.60#ibcon#about to read 5, iclass 31, count 0 2006.259.08:03:21.60#ibcon#read 5, iclass 31, count 0 2006.259.08:03:21.60#ibcon#about to read 6, iclass 31, count 0 2006.259.08:03:21.60#ibcon#read 6, iclass 31, count 0 2006.259.08:03:21.60#ibcon#end of sib2, iclass 31, count 0 2006.259.08:03:21.60#ibcon#*mode == 0, iclass 31, count 0 2006.259.08:03:21.60#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.259.08:03:21.60#ibcon#[26=FRQ=08,852.99\r\n] 2006.259.08:03:21.60#ibcon#*before write, iclass 31, count 0 2006.259.08:03:21.60#ibcon#enter sib2, iclass 31, count 0 2006.259.08:03:21.60#ibcon#flushed, iclass 31, count 0 2006.259.08:03:21.60#ibcon#about to write, iclass 31, count 0 2006.259.08:03:21.60#ibcon#wrote, iclass 31, count 0 2006.259.08:03:21.60#ibcon#about to read 3, iclass 31, count 0 2006.259.08:03:21.64#ibcon#read 3, iclass 31, count 0 2006.259.08:03:21.64#ibcon#about to read 4, iclass 31, count 0 2006.259.08:03:21.64#ibcon#read 4, iclass 31, count 0 2006.259.08:03:21.64#ibcon#about to read 5, iclass 31, count 0 2006.259.08:03:21.64#ibcon#read 5, iclass 31, count 0 2006.259.08:03:21.64#ibcon#about to read 6, iclass 31, count 0 2006.259.08:03:21.64#ibcon#read 6, iclass 31, count 0 2006.259.08:03:21.64#ibcon#end of sib2, iclass 31, count 0 2006.259.08:03:21.64#ibcon#*after write, iclass 31, count 0 2006.259.08:03:21.64#ibcon#*before return 0, iclass 31, count 0 2006.259.08:03:21.64#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.259.08:03:21.64#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.259.08:03:21.64#ibcon#about to clear, iclass 31 cls_cnt 0 2006.259.08:03:21.64#ibcon#cleared, iclass 31 cls_cnt 0 2006.259.08:03:21.64$vc4f8/va=8,6 2006.259.08:03:21.64#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.259.08:03:21.64#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.259.08:03:21.64#ibcon#ireg 11 cls_cnt 2 2006.259.08:03:21.64#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.259.08:03:21.68#abcon#<5=/04 2.9 4.5 22.07 861013.0\r\n> 2006.259.08:03:21.70#abcon#{5=INTERFACE CLEAR} 2006.259.08:03:21.70#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.259.08:03:21.70#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.259.08:03:21.70#ibcon#enter wrdev, iclass 34, count 2 2006.259.08:03:21.70#ibcon#first serial, iclass 34, count 2 2006.259.08:03:21.70#ibcon#enter sib2, iclass 34, count 2 2006.259.08:03:21.70#ibcon#flushed, iclass 34, count 2 2006.259.08:03:21.70#ibcon#about to write, iclass 34, count 2 2006.259.08:03:21.70#ibcon#wrote, iclass 34, count 2 2006.259.08:03:21.70#ibcon#about to read 3, iclass 34, count 2 2006.259.08:03:21.72#ibcon#read 3, iclass 34, count 2 2006.259.08:03:21.72#ibcon#about to read 4, iclass 34, count 2 2006.259.08:03:21.72#ibcon#read 4, iclass 34, count 2 2006.259.08:03:21.72#ibcon#about to read 5, iclass 34, count 2 2006.259.08:03:21.72#ibcon#read 5, iclass 34, count 2 2006.259.08:03:21.72#ibcon#about to read 6, iclass 34, count 2 2006.259.08:03:21.72#ibcon#read 6, iclass 34, count 2 2006.259.08:03:21.72#ibcon#end of sib2, iclass 34, count 2 2006.259.08:03:21.72#ibcon#*mode == 0, iclass 34, count 2 2006.259.08:03:21.72#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.259.08:03:21.72#ibcon#[25=AT08-06\r\n] 2006.259.08:03:21.72#ibcon#*before write, iclass 34, count 2 2006.259.08:03:21.72#ibcon#enter sib2, iclass 34, count 2 2006.259.08:03:21.72#ibcon#flushed, iclass 34, count 2 2006.259.08:03:21.72#ibcon#about to write, iclass 34, count 2 2006.259.08:03:21.72#ibcon#wrote, iclass 34, count 2 2006.259.08:03:21.72#ibcon#about to read 3, iclass 34, count 2 2006.259.08:03:21.75#ibcon#read 3, iclass 34, count 2 2006.259.08:03:21.75#ibcon#about to read 4, iclass 34, count 2 2006.259.08:03:21.75#ibcon#read 4, iclass 34, count 2 2006.259.08:03:21.75#ibcon#about to read 5, iclass 34, count 2 2006.259.08:03:21.75#ibcon#read 5, iclass 34, count 2 2006.259.08:03:21.75#ibcon#about to read 6, iclass 34, count 2 2006.259.08:03:21.75#ibcon#read 6, iclass 34, count 2 2006.259.08:03:21.75#ibcon#end of sib2, iclass 34, count 2 2006.259.08:03:21.75#ibcon#*after write, iclass 34, count 2 2006.259.08:03:21.75#ibcon#*before return 0, iclass 34, count 2 2006.259.08:03:21.75#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.259.08:03:21.75#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.259.08:03:21.75#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.259.08:03:21.75#ibcon#ireg 7 cls_cnt 0 2006.259.08:03:21.75#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.259.08:03:21.76#abcon#[5=S1D000X0/0*\r\n] 2006.259.08:03:21.87#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.259.08:03:21.87#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.259.08:03:21.87#ibcon#enter wrdev, iclass 34, count 0 2006.259.08:03:21.87#ibcon#first serial, iclass 34, count 0 2006.259.08:03:21.87#ibcon#enter sib2, iclass 34, count 0 2006.259.08:03:21.87#ibcon#flushed, iclass 34, count 0 2006.259.08:03:21.87#ibcon#about to write, iclass 34, count 0 2006.259.08:03:21.87#ibcon#wrote, iclass 34, count 0 2006.259.08:03:21.87#ibcon#about to read 3, iclass 34, count 0 2006.259.08:03:21.89#ibcon#read 3, iclass 34, count 0 2006.259.08:03:21.89#ibcon#about to read 4, iclass 34, count 0 2006.259.08:03:21.89#ibcon#read 4, iclass 34, count 0 2006.259.08:03:21.89#ibcon#about to read 5, iclass 34, count 0 2006.259.08:03:21.89#ibcon#read 5, iclass 34, count 0 2006.259.08:03:21.89#ibcon#about to read 6, iclass 34, count 0 2006.259.08:03:21.89#ibcon#read 6, iclass 34, count 0 2006.259.08:03:21.89#ibcon#end of sib2, iclass 34, count 0 2006.259.08:03:21.89#ibcon#*mode == 0, iclass 34, count 0 2006.259.08:03:21.89#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.259.08:03:21.89#ibcon#[25=USB\r\n] 2006.259.08:03:21.89#ibcon#*before write, iclass 34, count 0 2006.259.08:03:21.89#ibcon#enter sib2, iclass 34, count 0 2006.259.08:03:21.89#ibcon#flushed, iclass 34, count 0 2006.259.08:03:21.89#ibcon#about to write, iclass 34, count 0 2006.259.08:03:21.89#ibcon#wrote, iclass 34, count 0 2006.259.08:03:21.89#ibcon#about to read 3, iclass 34, count 0 2006.259.08:03:21.92#ibcon#read 3, iclass 34, count 0 2006.259.08:03:21.92#ibcon#about to read 4, iclass 34, count 0 2006.259.08:03:21.92#ibcon#read 4, iclass 34, count 0 2006.259.08:03:21.92#ibcon#about to read 5, iclass 34, count 0 2006.259.08:03:21.92#ibcon#read 5, iclass 34, count 0 2006.259.08:03:21.92#ibcon#about to read 6, iclass 34, count 0 2006.259.08:03:21.92#ibcon#read 6, iclass 34, count 0 2006.259.08:03:21.92#ibcon#end of sib2, iclass 34, count 0 2006.259.08:03:21.92#ibcon#*after write, iclass 34, count 0 2006.259.08:03:21.92#ibcon#*before return 0, iclass 34, count 0 2006.259.08:03:21.92#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.259.08:03:21.92#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.259.08:03:21.92#ibcon#about to clear, iclass 34 cls_cnt 0 2006.259.08:03:21.92#ibcon#cleared, iclass 34 cls_cnt 0 2006.259.08:03:21.92$vc4f8/vblo=1,632.99 2006.259.08:03:21.92#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.259.08:03:21.92#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.259.08:03:21.92#ibcon#ireg 17 cls_cnt 0 2006.259.08:03:21.92#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.259.08:03:21.92#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.259.08:03:21.92#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.259.08:03:21.92#ibcon#enter wrdev, iclass 39, count 0 2006.259.08:03:21.92#ibcon#first serial, iclass 39, count 0 2006.259.08:03:21.92#ibcon#enter sib2, iclass 39, count 0 2006.259.08:03:21.92#ibcon#flushed, iclass 39, count 0 2006.259.08:03:21.92#ibcon#about to write, iclass 39, count 0 2006.259.08:03:21.92#ibcon#wrote, iclass 39, count 0 2006.259.08:03:21.92#ibcon#about to read 3, iclass 39, count 0 2006.259.08:03:21.94#ibcon#read 3, iclass 39, count 0 2006.259.08:03:21.94#ibcon#about to read 4, iclass 39, count 0 2006.259.08:03:21.94#ibcon#read 4, iclass 39, count 0 2006.259.08:03:21.94#ibcon#about to read 5, iclass 39, count 0 2006.259.08:03:21.94#ibcon#read 5, iclass 39, count 0 2006.259.08:03:21.94#ibcon#about to read 6, iclass 39, count 0 2006.259.08:03:21.94#ibcon#read 6, iclass 39, count 0 2006.259.08:03:21.94#ibcon#end of sib2, iclass 39, count 0 2006.259.08:03:21.94#ibcon#*mode == 0, iclass 39, count 0 2006.259.08:03:21.94#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.259.08:03:21.94#ibcon#[28=FRQ=01,632.99\r\n] 2006.259.08:03:21.94#ibcon#*before write, iclass 39, count 0 2006.259.08:03:21.94#ibcon#enter sib2, iclass 39, count 0 2006.259.08:03:21.94#ibcon#flushed, iclass 39, count 0 2006.259.08:03:21.94#ibcon#about to write, iclass 39, count 0 2006.259.08:03:21.94#ibcon#wrote, iclass 39, count 0 2006.259.08:03:21.94#ibcon#about to read 3, iclass 39, count 0 2006.259.08:03:21.98#ibcon#read 3, iclass 39, count 0 2006.259.08:03:21.98#ibcon#about to read 4, iclass 39, count 0 2006.259.08:03:21.98#ibcon#read 4, iclass 39, count 0 2006.259.08:03:21.98#ibcon#about to read 5, iclass 39, count 0 2006.259.08:03:21.98#ibcon#read 5, iclass 39, count 0 2006.259.08:03:21.98#ibcon#about to read 6, iclass 39, count 0 2006.259.08:03:21.98#ibcon#read 6, iclass 39, count 0 2006.259.08:03:21.98#ibcon#end of sib2, iclass 39, count 0 2006.259.08:03:21.98#ibcon#*after write, iclass 39, count 0 2006.259.08:03:21.98#ibcon#*before return 0, iclass 39, count 0 2006.259.08:03:21.98#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.259.08:03:21.98#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.259.08:03:21.98#ibcon#about to clear, iclass 39 cls_cnt 0 2006.259.08:03:21.98#ibcon#cleared, iclass 39 cls_cnt 0 2006.259.08:03:21.98$vc4f8/vb=1,4 2006.259.08:03:21.98#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.259.08:03:21.98#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.259.08:03:21.98#ibcon#ireg 11 cls_cnt 2 2006.259.08:03:21.98#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.259.08:03:21.98#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.259.08:03:21.98#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.259.08:03:21.98#ibcon#enter wrdev, iclass 3, count 2 2006.259.08:03:21.98#ibcon#first serial, iclass 3, count 2 2006.259.08:03:21.98#ibcon#enter sib2, iclass 3, count 2 2006.259.08:03:21.98#ibcon#flushed, iclass 3, count 2 2006.259.08:03:21.98#ibcon#about to write, iclass 3, count 2 2006.259.08:03:21.98#ibcon#wrote, iclass 3, count 2 2006.259.08:03:21.98#ibcon#about to read 3, iclass 3, count 2 2006.259.08:03:22.00#ibcon#read 3, iclass 3, count 2 2006.259.08:03:22.00#ibcon#about to read 4, iclass 3, count 2 2006.259.08:03:22.00#ibcon#read 4, iclass 3, count 2 2006.259.08:03:22.00#ibcon#about to read 5, iclass 3, count 2 2006.259.08:03:22.00#ibcon#read 5, iclass 3, count 2 2006.259.08:03:22.00#ibcon#about to read 6, iclass 3, count 2 2006.259.08:03:22.00#ibcon#read 6, iclass 3, count 2 2006.259.08:03:22.00#ibcon#end of sib2, iclass 3, count 2 2006.259.08:03:22.00#ibcon#*mode == 0, iclass 3, count 2 2006.259.08:03:22.00#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.259.08:03:22.00#ibcon#[27=AT01-04\r\n] 2006.259.08:03:22.00#ibcon#*before write, iclass 3, count 2 2006.259.08:03:22.00#ibcon#enter sib2, iclass 3, count 2 2006.259.08:03:22.00#ibcon#flushed, iclass 3, count 2 2006.259.08:03:22.00#ibcon#about to write, iclass 3, count 2 2006.259.08:03:22.00#ibcon#wrote, iclass 3, count 2 2006.259.08:03:22.00#ibcon#about to read 3, iclass 3, count 2 2006.259.08:03:22.03#ibcon#read 3, iclass 3, count 2 2006.259.08:03:22.03#ibcon#about to read 4, iclass 3, count 2 2006.259.08:03:22.03#ibcon#read 4, iclass 3, count 2 2006.259.08:03:22.03#ibcon#about to read 5, iclass 3, count 2 2006.259.08:03:22.03#ibcon#read 5, iclass 3, count 2 2006.259.08:03:22.03#ibcon#about to read 6, iclass 3, count 2 2006.259.08:03:22.03#ibcon#read 6, iclass 3, count 2 2006.259.08:03:22.03#ibcon#end of sib2, iclass 3, count 2 2006.259.08:03:22.03#ibcon#*after write, iclass 3, count 2 2006.259.08:03:22.03#ibcon#*before return 0, iclass 3, count 2 2006.259.08:03:22.03#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.259.08:03:22.03#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.259.08:03:22.03#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.259.08:03:22.03#ibcon#ireg 7 cls_cnt 0 2006.259.08:03:22.03#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.259.08:03:22.15#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.259.08:03:22.15#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.259.08:03:22.15#ibcon#enter wrdev, iclass 3, count 0 2006.259.08:03:22.15#ibcon#first serial, iclass 3, count 0 2006.259.08:03:22.15#ibcon#enter sib2, iclass 3, count 0 2006.259.08:03:22.15#ibcon#flushed, iclass 3, count 0 2006.259.08:03:22.15#ibcon#about to write, iclass 3, count 0 2006.259.08:03:22.15#ibcon#wrote, iclass 3, count 0 2006.259.08:03:22.15#ibcon#about to read 3, iclass 3, count 0 2006.259.08:03:22.17#ibcon#read 3, iclass 3, count 0 2006.259.08:03:22.17#ibcon#about to read 4, iclass 3, count 0 2006.259.08:03:22.17#ibcon#read 4, iclass 3, count 0 2006.259.08:03:22.17#ibcon#about to read 5, iclass 3, count 0 2006.259.08:03:22.17#ibcon#read 5, iclass 3, count 0 2006.259.08:03:22.17#ibcon#about to read 6, iclass 3, count 0 2006.259.08:03:22.17#ibcon#read 6, iclass 3, count 0 2006.259.08:03:22.17#ibcon#end of sib2, iclass 3, count 0 2006.259.08:03:22.17#ibcon#*mode == 0, iclass 3, count 0 2006.259.08:03:22.17#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.259.08:03:22.17#ibcon#[27=USB\r\n] 2006.259.08:03:22.17#ibcon#*before write, iclass 3, count 0 2006.259.08:03:22.17#ibcon#enter sib2, iclass 3, count 0 2006.259.08:03:22.17#ibcon#flushed, iclass 3, count 0 2006.259.08:03:22.17#ibcon#about to write, iclass 3, count 0 2006.259.08:03:22.17#ibcon#wrote, iclass 3, count 0 2006.259.08:03:22.17#ibcon#about to read 3, iclass 3, count 0 2006.259.08:03:22.20#ibcon#read 3, iclass 3, count 0 2006.259.08:03:22.20#ibcon#about to read 4, iclass 3, count 0 2006.259.08:03:22.20#ibcon#read 4, iclass 3, count 0 2006.259.08:03:22.20#ibcon#about to read 5, iclass 3, count 0 2006.259.08:03:22.20#ibcon#read 5, iclass 3, count 0 2006.259.08:03:22.20#ibcon#about to read 6, iclass 3, count 0 2006.259.08:03:22.20#ibcon#read 6, iclass 3, count 0 2006.259.08:03:22.20#ibcon#end of sib2, iclass 3, count 0 2006.259.08:03:22.20#ibcon#*after write, iclass 3, count 0 2006.259.08:03:22.20#ibcon#*before return 0, iclass 3, count 0 2006.259.08:03:22.20#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.259.08:03:22.20#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.259.08:03:22.20#ibcon#about to clear, iclass 3 cls_cnt 0 2006.259.08:03:22.20#ibcon#cleared, iclass 3 cls_cnt 0 2006.259.08:03:22.20$vc4f8/vblo=2,640.99 2006.259.08:03:22.20#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.259.08:03:22.20#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.259.08:03:22.20#ibcon#ireg 17 cls_cnt 0 2006.259.08:03:22.20#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.259.08:03:22.20#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.259.08:03:22.20#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.259.08:03:22.20#ibcon#enter wrdev, iclass 5, count 0 2006.259.08:03:22.20#ibcon#first serial, iclass 5, count 0 2006.259.08:03:22.20#ibcon#enter sib2, iclass 5, count 0 2006.259.08:03:22.20#ibcon#flushed, iclass 5, count 0 2006.259.08:03:22.20#ibcon#about to write, iclass 5, count 0 2006.259.08:03:22.20#ibcon#wrote, iclass 5, count 0 2006.259.08:03:22.20#ibcon#about to read 3, iclass 5, count 0 2006.259.08:03:22.22#ibcon#read 3, iclass 5, count 0 2006.259.08:03:22.22#ibcon#about to read 4, iclass 5, count 0 2006.259.08:03:22.22#ibcon#read 4, iclass 5, count 0 2006.259.08:03:22.22#ibcon#about to read 5, iclass 5, count 0 2006.259.08:03:22.22#ibcon#read 5, iclass 5, count 0 2006.259.08:03:22.22#ibcon#about to read 6, iclass 5, count 0 2006.259.08:03:22.22#ibcon#read 6, iclass 5, count 0 2006.259.08:03:22.22#ibcon#end of sib2, iclass 5, count 0 2006.259.08:03:22.22#ibcon#*mode == 0, iclass 5, count 0 2006.259.08:03:22.22#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.259.08:03:22.22#ibcon#[28=FRQ=02,640.99\r\n] 2006.259.08:03:22.22#ibcon#*before write, iclass 5, count 0 2006.259.08:03:22.22#ibcon#enter sib2, iclass 5, count 0 2006.259.08:03:22.22#ibcon#flushed, iclass 5, count 0 2006.259.08:03:22.22#ibcon#about to write, iclass 5, count 0 2006.259.08:03:22.22#ibcon#wrote, iclass 5, count 0 2006.259.08:03:22.22#ibcon#about to read 3, iclass 5, count 0 2006.259.08:03:22.26#ibcon#read 3, iclass 5, count 0 2006.259.08:03:22.26#ibcon#about to read 4, iclass 5, count 0 2006.259.08:03:22.26#ibcon#read 4, iclass 5, count 0 2006.259.08:03:22.26#ibcon#about to read 5, iclass 5, count 0 2006.259.08:03:22.26#ibcon#read 5, iclass 5, count 0 2006.259.08:03:22.26#ibcon#about to read 6, iclass 5, count 0 2006.259.08:03:22.26#ibcon#read 6, iclass 5, count 0 2006.259.08:03:22.26#ibcon#end of sib2, iclass 5, count 0 2006.259.08:03:22.26#ibcon#*after write, iclass 5, count 0 2006.259.08:03:22.26#ibcon#*before return 0, iclass 5, count 0 2006.259.08:03:22.26#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.259.08:03:22.26#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.259.08:03:22.26#ibcon#about to clear, iclass 5 cls_cnt 0 2006.259.08:03:22.26#ibcon#cleared, iclass 5 cls_cnt 0 2006.259.08:03:22.26$vc4f8/vb=2,5 2006.259.08:03:22.26#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.259.08:03:22.26#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.259.08:03:22.26#ibcon#ireg 11 cls_cnt 2 2006.259.08:03:22.26#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.259.08:03:22.32#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.259.08:03:22.32#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.259.08:03:22.32#ibcon#enter wrdev, iclass 7, count 2 2006.259.08:03:22.32#ibcon#first serial, iclass 7, count 2 2006.259.08:03:22.32#ibcon#enter sib2, iclass 7, count 2 2006.259.08:03:22.32#ibcon#flushed, iclass 7, count 2 2006.259.08:03:22.32#ibcon#about to write, iclass 7, count 2 2006.259.08:03:22.32#ibcon#wrote, iclass 7, count 2 2006.259.08:03:22.32#ibcon#about to read 3, iclass 7, count 2 2006.259.08:03:22.34#ibcon#read 3, iclass 7, count 2 2006.259.08:03:22.34#ibcon#about to read 4, iclass 7, count 2 2006.259.08:03:22.34#ibcon#read 4, iclass 7, count 2 2006.259.08:03:22.34#ibcon#about to read 5, iclass 7, count 2 2006.259.08:03:22.34#ibcon#read 5, iclass 7, count 2 2006.259.08:03:22.34#ibcon#about to read 6, iclass 7, count 2 2006.259.08:03:22.34#ibcon#read 6, iclass 7, count 2 2006.259.08:03:22.34#ibcon#end of sib2, iclass 7, count 2 2006.259.08:03:22.34#ibcon#*mode == 0, iclass 7, count 2 2006.259.08:03:22.34#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.259.08:03:22.34#ibcon#[27=AT02-05\r\n] 2006.259.08:03:22.34#ibcon#*before write, iclass 7, count 2 2006.259.08:03:22.34#ibcon#enter sib2, iclass 7, count 2 2006.259.08:03:22.34#ibcon#flushed, iclass 7, count 2 2006.259.08:03:22.34#ibcon#about to write, iclass 7, count 2 2006.259.08:03:22.34#ibcon#wrote, iclass 7, count 2 2006.259.08:03:22.34#ibcon#about to read 3, iclass 7, count 2 2006.259.08:03:22.37#ibcon#read 3, iclass 7, count 2 2006.259.08:03:22.37#ibcon#about to read 4, iclass 7, count 2 2006.259.08:03:22.37#ibcon#read 4, iclass 7, count 2 2006.259.08:03:22.37#ibcon#about to read 5, iclass 7, count 2 2006.259.08:03:22.37#ibcon#read 5, iclass 7, count 2 2006.259.08:03:22.37#ibcon#about to read 6, iclass 7, count 2 2006.259.08:03:22.37#ibcon#read 6, iclass 7, count 2 2006.259.08:03:22.37#ibcon#end of sib2, iclass 7, count 2 2006.259.08:03:22.37#ibcon#*after write, iclass 7, count 2 2006.259.08:03:22.37#ibcon#*before return 0, iclass 7, count 2 2006.259.08:03:22.37#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.259.08:03:22.37#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.259.08:03:22.37#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.259.08:03:22.37#ibcon#ireg 7 cls_cnt 0 2006.259.08:03:22.37#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.259.08:03:22.49#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.259.08:03:22.49#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.259.08:03:22.49#ibcon#enter wrdev, iclass 7, count 0 2006.259.08:03:22.49#ibcon#first serial, iclass 7, count 0 2006.259.08:03:22.49#ibcon#enter sib2, iclass 7, count 0 2006.259.08:03:22.49#ibcon#flushed, iclass 7, count 0 2006.259.08:03:22.49#ibcon#about to write, iclass 7, count 0 2006.259.08:03:22.49#ibcon#wrote, iclass 7, count 0 2006.259.08:03:22.49#ibcon#about to read 3, iclass 7, count 0 2006.259.08:03:22.51#ibcon#read 3, iclass 7, count 0 2006.259.08:03:22.51#ibcon#about to read 4, iclass 7, count 0 2006.259.08:03:22.51#ibcon#read 4, iclass 7, count 0 2006.259.08:03:22.51#ibcon#about to read 5, iclass 7, count 0 2006.259.08:03:22.51#ibcon#read 5, iclass 7, count 0 2006.259.08:03:22.51#ibcon#about to read 6, iclass 7, count 0 2006.259.08:03:22.51#ibcon#read 6, iclass 7, count 0 2006.259.08:03:22.51#ibcon#end of sib2, iclass 7, count 0 2006.259.08:03:22.51#ibcon#*mode == 0, iclass 7, count 0 2006.259.08:03:22.51#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.259.08:03:22.51#ibcon#[27=USB\r\n] 2006.259.08:03:22.51#ibcon#*before write, iclass 7, count 0 2006.259.08:03:22.51#ibcon#enter sib2, iclass 7, count 0 2006.259.08:03:22.51#ibcon#flushed, iclass 7, count 0 2006.259.08:03:22.51#ibcon#about to write, iclass 7, count 0 2006.259.08:03:22.51#ibcon#wrote, iclass 7, count 0 2006.259.08:03:22.51#ibcon#about to read 3, iclass 7, count 0 2006.259.08:03:22.54#ibcon#read 3, iclass 7, count 0 2006.259.08:03:22.54#ibcon#about to read 4, iclass 7, count 0 2006.259.08:03:22.54#ibcon#read 4, iclass 7, count 0 2006.259.08:03:22.54#ibcon#about to read 5, iclass 7, count 0 2006.259.08:03:22.54#ibcon#read 5, iclass 7, count 0 2006.259.08:03:22.54#ibcon#about to read 6, iclass 7, count 0 2006.259.08:03:22.54#ibcon#read 6, iclass 7, count 0 2006.259.08:03:22.54#ibcon#end of sib2, iclass 7, count 0 2006.259.08:03:22.54#ibcon#*after write, iclass 7, count 0 2006.259.08:03:22.54#ibcon#*before return 0, iclass 7, count 0 2006.259.08:03:22.54#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.259.08:03:22.54#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.259.08:03:22.54#ibcon#about to clear, iclass 7 cls_cnt 0 2006.259.08:03:22.54#ibcon#cleared, iclass 7 cls_cnt 0 2006.259.08:03:22.54$vc4f8/vblo=3,656.99 2006.259.08:03:22.54#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.259.08:03:22.54#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.259.08:03:22.54#ibcon#ireg 17 cls_cnt 0 2006.259.08:03:22.54#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.259.08:03:22.54#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.259.08:03:22.54#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.259.08:03:22.54#ibcon#enter wrdev, iclass 11, count 0 2006.259.08:03:22.54#ibcon#first serial, iclass 11, count 0 2006.259.08:03:22.54#ibcon#enter sib2, iclass 11, count 0 2006.259.08:03:22.54#ibcon#flushed, iclass 11, count 0 2006.259.08:03:22.54#ibcon#about to write, iclass 11, count 0 2006.259.08:03:22.54#ibcon#wrote, iclass 11, count 0 2006.259.08:03:22.54#ibcon#about to read 3, iclass 11, count 0 2006.259.08:03:22.56#ibcon#read 3, iclass 11, count 0 2006.259.08:03:22.56#ibcon#about to read 4, iclass 11, count 0 2006.259.08:03:22.56#ibcon#read 4, iclass 11, count 0 2006.259.08:03:22.56#ibcon#about to read 5, iclass 11, count 0 2006.259.08:03:22.56#ibcon#read 5, iclass 11, count 0 2006.259.08:03:22.56#ibcon#about to read 6, iclass 11, count 0 2006.259.08:03:22.56#ibcon#read 6, iclass 11, count 0 2006.259.08:03:22.56#ibcon#end of sib2, iclass 11, count 0 2006.259.08:03:22.56#ibcon#*mode == 0, iclass 11, count 0 2006.259.08:03:22.56#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.259.08:03:22.56#ibcon#[28=FRQ=03,656.99\r\n] 2006.259.08:03:22.56#ibcon#*before write, iclass 11, count 0 2006.259.08:03:22.56#ibcon#enter sib2, iclass 11, count 0 2006.259.08:03:22.56#ibcon#flushed, iclass 11, count 0 2006.259.08:03:22.56#ibcon#about to write, iclass 11, count 0 2006.259.08:03:22.56#ibcon#wrote, iclass 11, count 0 2006.259.08:03:22.56#ibcon#about to read 3, iclass 11, count 0 2006.259.08:03:22.60#ibcon#read 3, iclass 11, count 0 2006.259.08:03:22.60#ibcon#about to read 4, iclass 11, count 0 2006.259.08:03:22.60#ibcon#read 4, iclass 11, count 0 2006.259.08:03:22.60#ibcon#about to read 5, iclass 11, count 0 2006.259.08:03:22.60#ibcon#read 5, iclass 11, count 0 2006.259.08:03:22.60#ibcon#about to read 6, iclass 11, count 0 2006.259.08:03:22.60#ibcon#read 6, iclass 11, count 0 2006.259.08:03:22.60#ibcon#end of sib2, iclass 11, count 0 2006.259.08:03:22.60#ibcon#*after write, iclass 11, count 0 2006.259.08:03:22.60#ibcon#*before return 0, iclass 11, count 0 2006.259.08:03:22.60#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.259.08:03:22.60#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.259.08:03:22.60#ibcon#about to clear, iclass 11 cls_cnt 0 2006.259.08:03:22.60#ibcon#cleared, iclass 11 cls_cnt 0 2006.259.08:03:22.60$vc4f8/vb=3,4 2006.259.08:03:22.60#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.259.08:03:22.60#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.259.08:03:22.60#ibcon#ireg 11 cls_cnt 2 2006.259.08:03:22.60#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.259.08:03:22.66#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.259.08:03:22.66#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.259.08:03:22.66#ibcon#enter wrdev, iclass 13, count 2 2006.259.08:03:22.66#ibcon#first serial, iclass 13, count 2 2006.259.08:03:22.66#ibcon#enter sib2, iclass 13, count 2 2006.259.08:03:22.66#ibcon#flushed, iclass 13, count 2 2006.259.08:03:22.66#ibcon#about to write, iclass 13, count 2 2006.259.08:03:22.66#ibcon#wrote, iclass 13, count 2 2006.259.08:03:22.66#ibcon#about to read 3, iclass 13, count 2 2006.259.08:03:22.68#ibcon#read 3, iclass 13, count 2 2006.259.08:03:22.68#ibcon#about to read 4, iclass 13, count 2 2006.259.08:03:22.68#ibcon#read 4, iclass 13, count 2 2006.259.08:03:22.68#ibcon#about to read 5, iclass 13, count 2 2006.259.08:03:22.68#ibcon#read 5, iclass 13, count 2 2006.259.08:03:22.68#ibcon#about to read 6, iclass 13, count 2 2006.259.08:03:22.68#ibcon#read 6, iclass 13, count 2 2006.259.08:03:22.68#ibcon#end of sib2, iclass 13, count 2 2006.259.08:03:22.68#ibcon#*mode == 0, iclass 13, count 2 2006.259.08:03:22.68#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.259.08:03:22.68#ibcon#[27=AT03-04\r\n] 2006.259.08:03:22.68#ibcon#*before write, iclass 13, count 2 2006.259.08:03:22.68#ibcon#enter sib2, iclass 13, count 2 2006.259.08:03:22.68#ibcon#flushed, iclass 13, count 2 2006.259.08:03:22.68#ibcon#about to write, iclass 13, count 2 2006.259.08:03:22.68#ibcon#wrote, iclass 13, count 2 2006.259.08:03:22.68#ibcon#about to read 3, iclass 13, count 2 2006.259.08:03:22.71#ibcon#read 3, iclass 13, count 2 2006.259.08:03:22.71#ibcon#about to read 4, iclass 13, count 2 2006.259.08:03:22.71#ibcon#read 4, iclass 13, count 2 2006.259.08:03:22.71#ibcon#about to read 5, iclass 13, count 2 2006.259.08:03:22.71#ibcon#read 5, iclass 13, count 2 2006.259.08:03:22.71#ibcon#about to read 6, iclass 13, count 2 2006.259.08:03:22.71#ibcon#read 6, iclass 13, count 2 2006.259.08:03:22.71#ibcon#end of sib2, iclass 13, count 2 2006.259.08:03:22.71#ibcon#*after write, iclass 13, count 2 2006.259.08:03:22.71#ibcon#*before return 0, iclass 13, count 2 2006.259.08:03:22.71#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.259.08:03:22.71#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.259.08:03:22.71#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.259.08:03:22.71#ibcon#ireg 7 cls_cnt 0 2006.259.08:03:22.71#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.259.08:03:22.83#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.259.08:03:22.83#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.259.08:03:22.83#ibcon#enter wrdev, iclass 13, count 0 2006.259.08:03:22.83#ibcon#first serial, iclass 13, count 0 2006.259.08:03:22.83#ibcon#enter sib2, iclass 13, count 0 2006.259.08:03:22.83#ibcon#flushed, iclass 13, count 0 2006.259.08:03:22.83#ibcon#about to write, iclass 13, count 0 2006.259.08:03:22.83#ibcon#wrote, iclass 13, count 0 2006.259.08:03:22.83#ibcon#about to read 3, iclass 13, count 0 2006.259.08:03:22.85#ibcon#read 3, iclass 13, count 0 2006.259.08:03:22.85#ibcon#about to read 4, iclass 13, count 0 2006.259.08:03:22.85#ibcon#read 4, iclass 13, count 0 2006.259.08:03:22.85#ibcon#about to read 5, iclass 13, count 0 2006.259.08:03:22.85#ibcon#read 5, iclass 13, count 0 2006.259.08:03:22.85#ibcon#about to read 6, iclass 13, count 0 2006.259.08:03:22.85#ibcon#read 6, iclass 13, count 0 2006.259.08:03:22.85#ibcon#end of sib2, iclass 13, count 0 2006.259.08:03:22.85#ibcon#*mode == 0, iclass 13, count 0 2006.259.08:03:22.85#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.259.08:03:22.85#ibcon#[27=USB\r\n] 2006.259.08:03:22.85#ibcon#*before write, iclass 13, count 0 2006.259.08:03:22.85#ibcon#enter sib2, iclass 13, count 0 2006.259.08:03:22.85#ibcon#flushed, iclass 13, count 0 2006.259.08:03:22.85#ibcon#about to write, iclass 13, count 0 2006.259.08:03:22.85#ibcon#wrote, iclass 13, count 0 2006.259.08:03:22.85#ibcon#about to read 3, iclass 13, count 0 2006.259.08:03:22.88#ibcon#read 3, iclass 13, count 0 2006.259.08:03:22.88#ibcon#about to read 4, iclass 13, count 0 2006.259.08:03:22.88#ibcon#read 4, iclass 13, count 0 2006.259.08:03:22.88#ibcon#about to read 5, iclass 13, count 0 2006.259.08:03:22.88#ibcon#read 5, iclass 13, count 0 2006.259.08:03:22.88#ibcon#about to read 6, iclass 13, count 0 2006.259.08:03:22.88#ibcon#read 6, iclass 13, count 0 2006.259.08:03:22.88#ibcon#end of sib2, iclass 13, count 0 2006.259.08:03:22.88#ibcon#*after write, iclass 13, count 0 2006.259.08:03:22.88#ibcon#*before return 0, iclass 13, count 0 2006.259.08:03:22.88#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.259.08:03:22.88#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.259.08:03:22.88#ibcon#about to clear, iclass 13 cls_cnt 0 2006.259.08:03:22.88#ibcon#cleared, iclass 13 cls_cnt 0 2006.259.08:03:22.88$vc4f8/vblo=4,712.99 2006.259.08:03:22.88#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.259.08:03:22.88#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.259.08:03:22.88#ibcon#ireg 17 cls_cnt 0 2006.259.08:03:22.88#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.259.08:03:22.88#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.259.08:03:22.88#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.259.08:03:22.88#ibcon#enter wrdev, iclass 15, count 0 2006.259.08:03:22.88#ibcon#first serial, iclass 15, count 0 2006.259.08:03:22.88#ibcon#enter sib2, iclass 15, count 0 2006.259.08:03:22.88#ibcon#flushed, iclass 15, count 0 2006.259.08:03:22.88#ibcon#about to write, iclass 15, count 0 2006.259.08:03:22.88#ibcon#wrote, iclass 15, count 0 2006.259.08:03:22.88#ibcon#about to read 3, iclass 15, count 0 2006.259.08:03:22.90#ibcon#read 3, iclass 15, count 0 2006.259.08:03:22.90#ibcon#about to read 4, iclass 15, count 0 2006.259.08:03:22.90#ibcon#read 4, iclass 15, count 0 2006.259.08:03:22.90#ibcon#about to read 5, iclass 15, count 0 2006.259.08:03:22.90#ibcon#read 5, iclass 15, count 0 2006.259.08:03:22.90#ibcon#about to read 6, iclass 15, count 0 2006.259.08:03:22.90#ibcon#read 6, iclass 15, count 0 2006.259.08:03:22.90#ibcon#end of sib2, iclass 15, count 0 2006.259.08:03:22.90#ibcon#*mode == 0, iclass 15, count 0 2006.259.08:03:22.90#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.259.08:03:22.90#ibcon#[28=FRQ=04,712.99\r\n] 2006.259.08:03:22.90#ibcon#*before write, iclass 15, count 0 2006.259.08:03:22.90#ibcon#enter sib2, iclass 15, count 0 2006.259.08:03:22.90#ibcon#flushed, iclass 15, count 0 2006.259.08:03:22.90#ibcon#about to write, iclass 15, count 0 2006.259.08:03:22.90#ibcon#wrote, iclass 15, count 0 2006.259.08:03:22.90#ibcon#about to read 3, iclass 15, count 0 2006.259.08:03:22.94#ibcon#read 3, iclass 15, count 0 2006.259.08:03:22.94#ibcon#about to read 4, iclass 15, count 0 2006.259.08:03:22.94#ibcon#read 4, iclass 15, count 0 2006.259.08:03:22.94#ibcon#about to read 5, iclass 15, count 0 2006.259.08:03:22.94#ibcon#read 5, iclass 15, count 0 2006.259.08:03:22.94#ibcon#about to read 6, iclass 15, count 0 2006.259.08:03:22.94#ibcon#read 6, iclass 15, count 0 2006.259.08:03:22.94#ibcon#end of sib2, iclass 15, count 0 2006.259.08:03:22.94#ibcon#*after write, iclass 15, count 0 2006.259.08:03:22.94#ibcon#*before return 0, iclass 15, count 0 2006.259.08:03:22.94#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.259.08:03:22.94#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.259.08:03:22.94#ibcon#about to clear, iclass 15 cls_cnt 0 2006.259.08:03:22.94#ibcon#cleared, iclass 15 cls_cnt 0 2006.259.08:03:22.94$vc4f8/vb=4,5 2006.259.08:03:22.94#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.259.08:03:22.94#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.259.08:03:22.94#ibcon#ireg 11 cls_cnt 2 2006.259.08:03:22.94#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.259.08:03:23.00#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.259.08:03:23.00#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.259.08:03:23.00#ibcon#enter wrdev, iclass 17, count 2 2006.259.08:03:23.00#ibcon#first serial, iclass 17, count 2 2006.259.08:03:23.00#ibcon#enter sib2, iclass 17, count 2 2006.259.08:03:23.00#ibcon#flushed, iclass 17, count 2 2006.259.08:03:23.00#ibcon#about to write, iclass 17, count 2 2006.259.08:03:23.00#ibcon#wrote, iclass 17, count 2 2006.259.08:03:23.00#ibcon#about to read 3, iclass 17, count 2 2006.259.08:03:23.02#ibcon#read 3, iclass 17, count 2 2006.259.08:03:23.02#ibcon#about to read 4, iclass 17, count 2 2006.259.08:03:23.02#ibcon#read 4, iclass 17, count 2 2006.259.08:03:23.02#ibcon#about to read 5, iclass 17, count 2 2006.259.08:03:23.02#ibcon#read 5, iclass 17, count 2 2006.259.08:03:23.02#ibcon#about to read 6, iclass 17, count 2 2006.259.08:03:23.02#ibcon#read 6, iclass 17, count 2 2006.259.08:03:23.02#ibcon#end of sib2, iclass 17, count 2 2006.259.08:03:23.02#ibcon#*mode == 0, iclass 17, count 2 2006.259.08:03:23.02#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.259.08:03:23.02#ibcon#[27=AT04-05\r\n] 2006.259.08:03:23.02#ibcon#*before write, iclass 17, count 2 2006.259.08:03:23.02#ibcon#enter sib2, iclass 17, count 2 2006.259.08:03:23.02#ibcon#flushed, iclass 17, count 2 2006.259.08:03:23.02#ibcon#about to write, iclass 17, count 2 2006.259.08:03:23.02#ibcon#wrote, iclass 17, count 2 2006.259.08:03:23.02#ibcon#about to read 3, iclass 17, count 2 2006.259.08:03:23.05#ibcon#read 3, iclass 17, count 2 2006.259.08:03:23.05#ibcon#about to read 4, iclass 17, count 2 2006.259.08:03:23.05#ibcon#read 4, iclass 17, count 2 2006.259.08:03:23.05#ibcon#about to read 5, iclass 17, count 2 2006.259.08:03:23.05#ibcon#read 5, iclass 17, count 2 2006.259.08:03:23.05#ibcon#about to read 6, iclass 17, count 2 2006.259.08:03:23.05#ibcon#read 6, iclass 17, count 2 2006.259.08:03:23.05#ibcon#end of sib2, iclass 17, count 2 2006.259.08:03:23.05#ibcon#*after write, iclass 17, count 2 2006.259.08:03:23.05#ibcon#*before return 0, iclass 17, count 2 2006.259.08:03:23.05#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.259.08:03:23.05#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.259.08:03:23.05#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.259.08:03:23.05#ibcon#ireg 7 cls_cnt 0 2006.259.08:03:23.05#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.259.08:03:23.17#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.259.08:03:23.17#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.259.08:03:23.17#ibcon#enter wrdev, iclass 17, count 0 2006.259.08:03:23.17#ibcon#first serial, iclass 17, count 0 2006.259.08:03:23.17#ibcon#enter sib2, iclass 17, count 0 2006.259.08:03:23.17#ibcon#flushed, iclass 17, count 0 2006.259.08:03:23.17#ibcon#about to write, iclass 17, count 0 2006.259.08:03:23.17#ibcon#wrote, iclass 17, count 0 2006.259.08:03:23.17#ibcon#about to read 3, iclass 17, count 0 2006.259.08:03:23.19#ibcon#read 3, iclass 17, count 0 2006.259.08:03:23.19#ibcon#about to read 4, iclass 17, count 0 2006.259.08:03:23.19#ibcon#read 4, iclass 17, count 0 2006.259.08:03:23.19#ibcon#about to read 5, iclass 17, count 0 2006.259.08:03:23.19#ibcon#read 5, iclass 17, count 0 2006.259.08:03:23.19#ibcon#about to read 6, iclass 17, count 0 2006.259.08:03:23.19#ibcon#read 6, iclass 17, count 0 2006.259.08:03:23.19#ibcon#end of sib2, iclass 17, count 0 2006.259.08:03:23.19#ibcon#*mode == 0, iclass 17, count 0 2006.259.08:03:23.19#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.259.08:03:23.19#ibcon#[27=USB\r\n] 2006.259.08:03:23.19#ibcon#*before write, iclass 17, count 0 2006.259.08:03:23.19#ibcon#enter sib2, iclass 17, count 0 2006.259.08:03:23.19#ibcon#flushed, iclass 17, count 0 2006.259.08:03:23.19#ibcon#about to write, iclass 17, count 0 2006.259.08:03:23.19#ibcon#wrote, iclass 17, count 0 2006.259.08:03:23.19#ibcon#about to read 3, iclass 17, count 0 2006.259.08:03:23.22#ibcon#read 3, iclass 17, count 0 2006.259.08:03:23.22#ibcon#about to read 4, iclass 17, count 0 2006.259.08:03:23.22#ibcon#read 4, iclass 17, count 0 2006.259.08:03:23.22#ibcon#about to read 5, iclass 17, count 0 2006.259.08:03:23.22#ibcon#read 5, iclass 17, count 0 2006.259.08:03:23.22#ibcon#about to read 6, iclass 17, count 0 2006.259.08:03:23.22#ibcon#read 6, iclass 17, count 0 2006.259.08:03:23.22#ibcon#end of sib2, iclass 17, count 0 2006.259.08:03:23.22#ibcon#*after write, iclass 17, count 0 2006.259.08:03:23.22#ibcon#*before return 0, iclass 17, count 0 2006.259.08:03:23.22#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.259.08:03:23.22#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.259.08:03:23.22#ibcon#about to clear, iclass 17 cls_cnt 0 2006.259.08:03:23.22#ibcon#cleared, iclass 17 cls_cnt 0 2006.259.08:03:23.22$vc4f8/vblo=5,744.99 2006.259.08:03:23.22#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.259.08:03:23.22#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.259.08:03:23.22#ibcon#ireg 17 cls_cnt 0 2006.259.08:03:23.22#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.259.08:03:23.22#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.259.08:03:23.22#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.259.08:03:23.22#ibcon#enter wrdev, iclass 19, count 0 2006.259.08:03:23.22#ibcon#first serial, iclass 19, count 0 2006.259.08:03:23.22#ibcon#enter sib2, iclass 19, count 0 2006.259.08:03:23.22#ibcon#flushed, iclass 19, count 0 2006.259.08:03:23.22#ibcon#about to write, iclass 19, count 0 2006.259.08:03:23.22#ibcon#wrote, iclass 19, count 0 2006.259.08:03:23.22#ibcon#about to read 3, iclass 19, count 0 2006.259.08:03:23.24#ibcon#read 3, iclass 19, count 0 2006.259.08:03:23.24#ibcon#about to read 4, iclass 19, count 0 2006.259.08:03:23.24#ibcon#read 4, iclass 19, count 0 2006.259.08:03:23.24#ibcon#about to read 5, iclass 19, count 0 2006.259.08:03:23.24#ibcon#read 5, iclass 19, count 0 2006.259.08:03:23.24#ibcon#about to read 6, iclass 19, count 0 2006.259.08:03:23.24#ibcon#read 6, iclass 19, count 0 2006.259.08:03:23.24#ibcon#end of sib2, iclass 19, count 0 2006.259.08:03:23.24#ibcon#*mode == 0, iclass 19, count 0 2006.259.08:03:23.24#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.259.08:03:23.24#ibcon#[28=FRQ=05,744.99\r\n] 2006.259.08:03:23.24#ibcon#*before write, iclass 19, count 0 2006.259.08:03:23.24#ibcon#enter sib2, iclass 19, count 0 2006.259.08:03:23.24#ibcon#flushed, iclass 19, count 0 2006.259.08:03:23.24#ibcon#about to write, iclass 19, count 0 2006.259.08:03:23.24#ibcon#wrote, iclass 19, count 0 2006.259.08:03:23.24#ibcon#about to read 3, iclass 19, count 0 2006.259.08:03:23.28#ibcon#read 3, iclass 19, count 0 2006.259.08:03:23.28#ibcon#about to read 4, iclass 19, count 0 2006.259.08:03:23.28#ibcon#read 4, iclass 19, count 0 2006.259.08:03:23.28#ibcon#about to read 5, iclass 19, count 0 2006.259.08:03:23.28#ibcon#read 5, iclass 19, count 0 2006.259.08:03:23.28#ibcon#about to read 6, iclass 19, count 0 2006.259.08:03:23.28#ibcon#read 6, iclass 19, count 0 2006.259.08:03:23.28#ibcon#end of sib2, iclass 19, count 0 2006.259.08:03:23.28#ibcon#*after write, iclass 19, count 0 2006.259.08:03:23.28#ibcon#*before return 0, iclass 19, count 0 2006.259.08:03:23.28#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.259.08:03:23.28#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.259.08:03:23.28#ibcon#about to clear, iclass 19 cls_cnt 0 2006.259.08:03:23.28#ibcon#cleared, iclass 19 cls_cnt 0 2006.259.08:03:23.28$vc4f8/vb=5,4 2006.259.08:03:23.28#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.259.08:03:23.28#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.259.08:03:23.28#ibcon#ireg 11 cls_cnt 2 2006.259.08:03:23.28#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.259.08:03:23.34#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.259.08:03:23.34#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.259.08:03:23.34#ibcon#enter wrdev, iclass 21, count 2 2006.259.08:03:23.34#ibcon#first serial, iclass 21, count 2 2006.259.08:03:23.34#ibcon#enter sib2, iclass 21, count 2 2006.259.08:03:23.34#ibcon#flushed, iclass 21, count 2 2006.259.08:03:23.34#ibcon#about to write, iclass 21, count 2 2006.259.08:03:23.34#ibcon#wrote, iclass 21, count 2 2006.259.08:03:23.34#ibcon#about to read 3, iclass 21, count 2 2006.259.08:03:23.36#ibcon#read 3, iclass 21, count 2 2006.259.08:03:23.36#ibcon#about to read 4, iclass 21, count 2 2006.259.08:03:23.36#ibcon#read 4, iclass 21, count 2 2006.259.08:03:23.36#ibcon#about to read 5, iclass 21, count 2 2006.259.08:03:23.36#ibcon#read 5, iclass 21, count 2 2006.259.08:03:23.36#ibcon#about to read 6, iclass 21, count 2 2006.259.08:03:23.36#ibcon#read 6, iclass 21, count 2 2006.259.08:03:23.36#ibcon#end of sib2, iclass 21, count 2 2006.259.08:03:23.36#ibcon#*mode == 0, iclass 21, count 2 2006.259.08:03:23.36#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.259.08:03:23.36#ibcon#[27=AT05-04\r\n] 2006.259.08:03:23.36#ibcon#*before write, iclass 21, count 2 2006.259.08:03:23.36#ibcon#enter sib2, iclass 21, count 2 2006.259.08:03:23.36#ibcon#flushed, iclass 21, count 2 2006.259.08:03:23.36#ibcon#about to write, iclass 21, count 2 2006.259.08:03:23.36#ibcon#wrote, iclass 21, count 2 2006.259.08:03:23.36#ibcon#about to read 3, iclass 21, count 2 2006.259.08:03:23.39#ibcon#read 3, iclass 21, count 2 2006.259.08:03:23.39#ibcon#about to read 4, iclass 21, count 2 2006.259.08:03:23.39#ibcon#read 4, iclass 21, count 2 2006.259.08:03:23.39#ibcon#about to read 5, iclass 21, count 2 2006.259.08:03:23.39#ibcon#read 5, iclass 21, count 2 2006.259.08:03:23.39#ibcon#about to read 6, iclass 21, count 2 2006.259.08:03:23.39#ibcon#read 6, iclass 21, count 2 2006.259.08:03:23.39#ibcon#end of sib2, iclass 21, count 2 2006.259.08:03:23.39#ibcon#*after write, iclass 21, count 2 2006.259.08:03:23.39#ibcon#*before return 0, iclass 21, count 2 2006.259.08:03:23.39#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.259.08:03:23.39#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.259.08:03:23.39#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.259.08:03:23.39#ibcon#ireg 7 cls_cnt 0 2006.259.08:03:23.39#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.259.08:03:23.51#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.259.08:03:23.51#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.259.08:03:23.51#ibcon#enter wrdev, iclass 21, count 0 2006.259.08:03:23.51#ibcon#first serial, iclass 21, count 0 2006.259.08:03:23.51#ibcon#enter sib2, iclass 21, count 0 2006.259.08:03:23.51#ibcon#flushed, iclass 21, count 0 2006.259.08:03:23.51#ibcon#about to write, iclass 21, count 0 2006.259.08:03:23.51#ibcon#wrote, iclass 21, count 0 2006.259.08:03:23.51#ibcon#about to read 3, iclass 21, count 0 2006.259.08:03:23.53#ibcon#read 3, iclass 21, count 0 2006.259.08:03:23.53#ibcon#about to read 4, iclass 21, count 0 2006.259.08:03:23.53#ibcon#read 4, iclass 21, count 0 2006.259.08:03:23.53#ibcon#about to read 5, iclass 21, count 0 2006.259.08:03:23.53#ibcon#read 5, iclass 21, count 0 2006.259.08:03:23.53#ibcon#about to read 6, iclass 21, count 0 2006.259.08:03:23.53#ibcon#read 6, iclass 21, count 0 2006.259.08:03:23.53#ibcon#end of sib2, iclass 21, count 0 2006.259.08:03:23.53#ibcon#*mode == 0, iclass 21, count 0 2006.259.08:03:23.53#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.259.08:03:23.53#ibcon#[27=USB\r\n] 2006.259.08:03:23.53#ibcon#*before write, iclass 21, count 0 2006.259.08:03:23.53#ibcon#enter sib2, iclass 21, count 0 2006.259.08:03:23.53#ibcon#flushed, iclass 21, count 0 2006.259.08:03:23.53#ibcon#about to write, iclass 21, count 0 2006.259.08:03:23.53#ibcon#wrote, iclass 21, count 0 2006.259.08:03:23.53#ibcon#about to read 3, iclass 21, count 0 2006.259.08:03:23.56#ibcon#read 3, iclass 21, count 0 2006.259.08:03:23.56#ibcon#about to read 4, iclass 21, count 0 2006.259.08:03:23.56#ibcon#read 4, iclass 21, count 0 2006.259.08:03:23.56#ibcon#about to read 5, iclass 21, count 0 2006.259.08:03:23.56#ibcon#read 5, iclass 21, count 0 2006.259.08:03:23.56#ibcon#about to read 6, iclass 21, count 0 2006.259.08:03:23.56#ibcon#read 6, iclass 21, count 0 2006.259.08:03:23.56#ibcon#end of sib2, iclass 21, count 0 2006.259.08:03:23.56#ibcon#*after write, iclass 21, count 0 2006.259.08:03:23.56#ibcon#*before return 0, iclass 21, count 0 2006.259.08:03:23.56#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.259.08:03:23.56#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.259.08:03:23.56#ibcon#about to clear, iclass 21 cls_cnt 0 2006.259.08:03:23.56#ibcon#cleared, iclass 21 cls_cnt 0 2006.259.08:03:23.56$vc4f8/vblo=6,752.99 2006.259.08:03:23.56#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.259.08:03:23.56#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.259.08:03:23.56#ibcon#ireg 17 cls_cnt 0 2006.259.08:03:23.56#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.259.08:03:23.56#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.259.08:03:23.56#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.259.08:03:23.56#ibcon#enter wrdev, iclass 23, count 0 2006.259.08:03:23.56#ibcon#first serial, iclass 23, count 0 2006.259.08:03:23.56#ibcon#enter sib2, iclass 23, count 0 2006.259.08:03:23.56#ibcon#flushed, iclass 23, count 0 2006.259.08:03:23.56#ibcon#about to write, iclass 23, count 0 2006.259.08:03:23.56#ibcon#wrote, iclass 23, count 0 2006.259.08:03:23.56#ibcon#about to read 3, iclass 23, count 0 2006.259.08:03:23.58#ibcon#read 3, iclass 23, count 0 2006.259.08:03:23.58#ibcon#about to read 4, iclass 23, count 0 2006.259.08:03:23.58#ibcon#read 4, iclass 23, count 0 2006.259.08:03:23.58#ibcon#about to read 5, iclass 23, count 0 2006.259.08:03:23.58#ibcon#read 5, iclass 23, count 0 2006.259.08:03:23.58#ibcon#about to read 6, iclass 23, count 0 2006.259.08:03:23.58#ibcon#read 6, iclass 23, count 0 2006.259.08:03:23.58#ibcon#end of sib2, iclass 23, count 0 2006.259.08:03:23.58#ibcon#*mode == 0, iclass 23, count 0 2006.259.08:03:23.58#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.259.08:03:23.58#ibcon#[28=FRQ=06,752.99\r\n] 2006.259.08:03:23.58#ibcon#*before write, iclass 23, count 0 2006.259.08:03:23.58#ibcon#enter sib2, iclass 23, count 0 2006.259.08:03:23.58#ibcon#flushed, iclass 23, count 0 2006.259.08:03:23.58#ibcon#about to write, iclass 23, count 0 2006.259.08:03:23.58#ibcon#wrote, iclass 23, count 0 2006.259.08:03:23.58#ibcon#about to read 3, iclass 23, count 0 2006.259.08:03:23.62#ibcon#read 3, iclass 23, count 0 2006.259.08:03:23.62#ibcon#about to read 4, iclass 23, count 0 2006.259.08:03:23.62#ibcon#read 4, iclass 23, count 0 2006.259.08:03:23.62#ibcon#about to read 5, iclass 23, count 0 2006.259.08:03:23.62#ibcon#read 5, iclass 23, count 0 2006.259.08:03:23.62#ibcon#about to read 6, iclass 23, count 0 2006.259.08:03:23.62#ibcon#read 6, iclass 23, count 0 2006.259.08:03:23.62#ibcon#end of sib2, iclass 23, count 0 2006.259.08:03:23.62#ibcon#*after write, iclass 23, count 0 2006.259.08:03:23.62#ibcon#*before return 0, iclass 23, count 0 2006.259.08:03:23.62#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.259.08:03:23.62#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.259.08:03:23.62#ibcon#about to clear, iclass 23 cls_cnt 0 2006.259.08:03:23.62#ibcon#cleared, iclass 23 cls_cnt 0 2006.259.08:03:23.62$vc4f8/vb=6,4 2006.259.08:03:23.62#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.259.08:03:23.62#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.259.08:03:23.62#ibcon#ireg 11 cls_cnt 2 2006.259.08:03:23.62#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.259.08:03:23.68#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.259.08:03:23.68#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.259.08:03:23.68#ibcon#enter wrdev, iclass 25, count 2 2006.259.08:03:23.68#ibcon#first serial, iclass 25, count 2 2006.259.08:03:23.68#ibcon#enter sib2, iclass 25, count 2 2006.259.08:03:23.68#ibcon#flushed, iclass 25, count 2 2006.259.08:03:23.68#ibcon#about to write, iclass 25, count 2 2006.259.08:03:23.68#ibcon#wrote, iclass 25, count 2 2006.259.08:03:23.68#ibcon#about to read 3, iclass 25, count 2 2006.259.08:03:23.70#ibcon#read 3, iclass 25, count 2 2006.259.08:03:23.70#ibcon#about to read 4, iclass 25, count 2 2006.259.08:03:23.70#ibcon#read 4, iclass 25, count 2 2006.259.08:03:23.70#ibcon#about to read 5, iclass 25, count 2 2006.259.08:03:23.70#ibcon#read 5, iclass 25, count 2 2006.259.08:03:23.70#ibcon#about to read 6, iclass 25, count 2 2006.259.08:03:23.70#ibcon#read 6, iclass 25, count 2 2006.259.08:03:23.70#ibcon#end of sib2, iclass 25, count 2 2006.259.08:03:23.70#ibcon#*mode == 0, iclass 25, count 2 2006.259.08:03:23.70#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.259.08:03:23.70#ibcon#[27=AT06-04\r\n] 2006.259.08:03:23.70#ibcon#*before write, iclass 25, count 2 2006.259.08:03:23.70#ibcon#enter sib2, iclass 25, count 2 2006.259.08:03:23.70#ibcon#flushed, iclass 25, count 2 2006.259.08:03:23.70#ibcon#about to write, iclass 25, count 2 2006.259.08:03:23.70#ibcon#wrote, iclass 25, count 2 2006.259.08:03:23.70#ibcon#about to read 3, iclass 25, count 2 2006.259.08:03:23.73#ibcon#read 3, iclass 25, count 2 2006.259.08:03:23.73#ibcon#about to read 4, iclass 25, count 2 2006.259.08:03:23.73#ibcon#read 4, iclass 25, count 2 2006.259.08:03:23.73#ibcon#about to read 5, iclass 25, count 2 2006.259.08:03:23.73#ibcon#read 5, iclass 25, count 2 2006.259.08:03:23.73#ibcon#about to read 6, iclass 25, count 2 2006.259.08:03:23.73#ibcon#read 6, iclass 25, count 2 2006.259.08:03:23.73#ibcon#end of sib2, iclass 25, count 2 2006.259.08:03:23.73#ibcon#*after write, iclass 25, count 2 2006.259.08:03:23.73#ibcon#*before return 0, iclass 25, count 2 2006.259.08:03:23.73#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.259.08:03:23.73#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.259.08:03:23.73#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.259.08:03:23.73#ibcon#ireg 7 cls_cnt 0 2006.259.08:03:23.73#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.259.08:03:23.85#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.259.08:03:23.85#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.259.08:03:23.85#ibcon#enter wrdev, iclass 25, count 0 2006.259.08:03:23.85#ibcon#first serial, iclass 25, count 0 2006.259.08:03:23.85#ibcon#enter sib2, iclass 25, count 0 2006.259.08:03:23.85#ibcon#flushed, iclass 25, count 0 2006.259.08:03:23.85#ibcon#about to write, iclass 25, count 0 2006.259.08:03:23.85#ibcon#wrote, iclass 25, count 0 2006.259.08:03:23.85#ibcon#about to read 3, iclass 25, count 0 2006.259.08:03:23.87#ibcon#read 3, iclass 25, count 0 2006.259.08:03:23.87#ibcon#about to read 4, iclass 25, count 0 2006.259.08:03:23.87#ibcon#read 4, iclass 25, count 0 2006.259.08:03:23.87#ibcon#about to read 5, iclass 25, count 0 2006.259.08:03:23.87#ibcon#read 5, iclass 25, count 0 2006.259.08:03:23.87#ibcon#about to read 6, iclass 25, count 0 2006.259.08:03:23.87#ibcon#read 6, iclass 25, count 0 2006.259.08:03:23.87#ibcon#end of sib2, iclass 25, count 0 2006.259.08:03:23.87#ibcon#*mode == 0, iclass 25, count 0 2006.259.08:03:23.87#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.259.08:03:23.87#ibcon#[27=USB\r\n] 2006.259.08:03:23.87#ibcon#*before write, iclass 25, count 0 2006.259.08:03:23.87#ibcon#enter sib2, iclass 25, count 0 2006.259.08:03:23.87#ibcon#flushed, iclass 25, count 0 2006.259.08:03:23.87#ibcon#about to write, iclass 25, count 0 2006.259.08:03:23.87#ibcon#wrote, iclass 25, count 0 2006.259.08:03:23.87#ibcon#about to read 3, iclass 25, count 0 2006.259.08:03:23.90#ibcon#read 3, iclass 25, count 0 2006.259.08:03:23.90#ibcon#about to read 4, iclass 25, count 0 2006.259.08:03:23.90#ibcon#read 4, iclass 25, count 0 2006.259.08:03:23.90#ibcon#about to read 5, iclass 25, count 0 2006.259.08:03:23.90#ibcon#read 5, iclass 25, count 0 2006.259.08:03:23.90#ibcon#about to read 6, iclass 25, count 0 2006.259.08:03:23.90#ibcon#read 6, iclass 25, count 0 2006.259.08:03:23.90#ibcon#end of sib2, iclass 25, count 0 2006.259.08:03:23.90#ibcon#*after write, iclass 25, count 0 2006.259.08:03:23.90#ibcon#*before return 0, iclass 25, count 0 2006.259.08:03:23.90#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.259.08:03:23.90#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.259.08:03:23.90#ibcon#about to clear, iclass 25 cls_cnt 0 2006.259.08:03:23.90#ibcon#cleared, iclass 25 cls_cnt 0 2006.259.08:03:23.90$vc4f8/vabw=wide 2006.259.08:03:23.90#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.259.08:03:23.90#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.259.08:03:23.90#ibcon#ireg 8 cls_cnt 0 2006.259.08:03:23.90#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.259.08:03:23.90#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.259.08:03:23.90#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.259.08:03:23.90#ibcon#enter wrdev, iclass 27, count 0 2006.259.08:03:23.90#ibcon#first serial, iclass 27, count 0 2006.259.08:03:23.90#ibcon#enter sib2, iclass 27, count 0 2006.259.08:03:23.90#ibcon#flushed, iclass 27, count 0 2006.259.08:03:23.90#ibcon#about to write, iclass 27, count 0 2006.259.08:03:23.90#ibcon#wrote, iclass 27, count 0 2006.259.08:03:23.90#ibcon#about to read 3, iclass 27, count 0 2006.259.08:03:23.92#ibcon#read 3, iclass 27, count 0 2006.259.08:03:23.92#ibcon#about to read 4, iclass 27, count 0 2006.259.08:03:23.92#ibcon#read 4, iclass 27, count 0 2006.259.08:03:23.92#ibcon#about to read 5, iclass 27, count 0 2006.259.08:03:23.92#ibcon#read 5, iclass 27, count 0 2006.259.08:03:23.92#ibcon#about to read 6, iclass 27, count 0 2006.259.08:03:23.92#ibcon#read 6, iclass 27, count 0 2006.259.08:03:23.92#ibcon#end of sib2, iclass 27, count 0 2006.259.08:03:23.92#ibcon#*mode == 0, iclass 27, count 0 2006.259.08:03:23.92#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.259.08:03:23.92#ibcon#[25=BW32\r\n] 2006.259.08:03:23.92#ibcon#*before write, iclass 27, count 0 2006.259.08:03:23.92#ibcon#enter sib2, iclass 27, count 0 2006.259.08:03:23.92#ibcon#flushed, iclass 27, count 0 2006.259.08:03:23.92#ibcon#about to write, iclass 27, count 0 2006.259.08:03:23.92#ibcon#wrote, iclass 27, count 0 2006.259.08:03:23.92#ibcon#about to read 3, iclass 27, count 0 2006.259.08:03:23.95#ibcon#read 3, iclass 27, count 0 2006.259.08:03:23.95#ibcon#about to read 4, iclass 27, count 0 2006.259.08:03:23.95#ibcon#read 4, iclass 27, count 0 2006.259.08:03:23.95#ibcon#about to read 5, iclass 27, count 0 2006.259.08:03:23.95#ibcon#read 5, iclass 27, count 0 2006.259.08:03:23.95#ibcon#about to read 6, iclass 27, count 0 2006.259.08:03:23.95#ibcon#read 6, iclass 27, count 0 2006.259.08:03:23.95#ibcon#end of sib2, iclass 27, count 0 2006.259.08:03:23.95#ibcon#*after write, iclass 27, count 0 2006.259.08:03:23.95#ibcon#*before return 0, iclass 27, count 0 2006.259.08:03:23.95#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.259.08:03:23.95#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.259.08:03:23.95#ibcon#about to clear, iclass 27 cls_cnt 0 2006.259.08:03:23.95#ibcon#cleared, iclass 27 cls_cnt 0 2006.259.08:03:23.95$vc4f8/vbbw=wide 2006.259.08:03:23.95#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.259.08:03:23.95#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.259.08:03:23.95#ibcon#ireg 8 cls_cnt 0 2006.259.08:03:23.95#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.259.08:03:24.02#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.259.08:03:24.02#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.259.08:03:24.02#ibcon#enter wrdev, iclass 29, count 0 2006.259.08:03:24.02#ibcon#first serial, iclass 29, count 0 2006.259.08:03:24.02#ibcon#enter sib2, iclass 29, count 0 2006.259.08:03:24.02#ibcon#flushed, iclass 29, count 0 2006.259.08:03:24.02#ibcon#about to write, iclass 29, count 0 2006.259.08:03:24.02#ibcon#wrote, iclass 29, count 0 2006.259.08:03:24.02#ibcon#about to read 3, iclass 29, count 0 2006.259.08:03:24.04#ibcon#read 3, iclass 29, count 0 2006.259.08:03:24.04#ibcon#about to read 4, iclass 29, count 0 2006.259.08:03:24.04#ibcon#read 4, iclass 29, count 0 2006.259.08:03:24.04#ibcon#about to read 5, iclass 29, count 0 2006.259.08:03:24.04#ibcon#read 5, iclass 29, count 0 2006.259.08:03:24.04#ibcon#about to read 6, iclass 29, count 0 2006.259.08:03:24.04#ibcon#read 6, iclass 29, count 0 2006.259.08:03:24.04#ibcon#end of sib2, iclass 29, count 0 2006.259.08:03:24.04#ibcon#*mode == 0, iclass 29, count 0 2006.259.08:03:24.04#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.259.08:03:24.04#ibcon#[27=BW32\r\n] 2006.259.08:03:24.04#ibcon#*before write, iclass 29, count 0 2006.259.08:03:24.04#ibcon#enter sib2, iclass 29, count 0 2006.259.08:03:24.04#ibcon#flushed, iclass 29, count 0 2006.259.08:03:24.04#ibcon#about to write, iclass 29, count 0 2006.259.08:03:24.04#ibcon#wrote, iclass 29, count 0 2006.259.08:03:24.04#ibcon#about to read 3, iclass 29, count 0 2006.259.08:03:24.07#ibcon#read 3, iclass 29, count 0 2006.259.08:03:24.07#ibcon#about to read 4, iclass 29, count 0 2006.259.08:03:24.07#ibcon#read 4, iclass 29, count 0 2006.259.08:03:24.07#ibcon#about to read 5, iclass 29, count 0 2006.259.08:03:24.07#ibcon#read 5, iclass 29, count 0 2006.259.08:03:24.07#ibcon#about to read 6, iclass 29, count 0 2006.259.08:03:24.07#ibcon#read 6, iclass 29, count 0 2006.259.08:03:24.07#ibcon#end of sib2, iclass 29, count 0 2006.259.08:03:24.07#ibcon#*after write, iclass 29, count 0 2006.259.08:03:24.07#ibcon#*before return 0, iclass 29, count 0 2006.259.08:03:24.07#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.259.08:03:24.07#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.259.08:03:24.07#ibcon#about to clear, iclass 29 cls_cnt 0 2006.259.08:03:24.07#ibcon#cleared, iclass 29 cls_cnt 0 2006.259.08:03:24.07$4f8m12a/ifd4f 2006.259.08:03:24.07$ifd4f/lo= 2006.259.08:03:24.07$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.259.08:03:24.07$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.259.08:03:24.07$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.259.08:03:24.07$ifd4f/patch= 2006.259.08:03:24.07$ifd4f/patch=lo1,a1,a2,a3,a4 2006.259.08:03:24.07$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.259.08:03:24.07$ifd4f/patch=lo3,a5,a6,a7,a8 2006.259.08:03:24.07$4f8m12a/"form=m,16.000,1:2 2006.259.08:03:24.07$4f8m12a/"tpicd 2006.259.08:03:24.07$4f8m12a/echo=off 2006.259.08:03:24.07$4f8m12a/xlog=off 2006.259.08:03:24.07:!2006.259.08:03:50 2006.259.08:03:29.14#trakl#Source acquired 2006.259.08:03:31.14#flagr#flagr/antenna,acquired 2006.259.08:03:50.00:preob 2006.259.08:03:50.14/onsource/TRACKING 2006.259.08:03:50.14:!2006.259.08:04:00 2006.259.08:04:00.00:data_valid=on 2006.259.08:04:00.00:midob 2006.259.08:04:01.14/onsource/TRACKING 2006.259.08:04:01.14/wx/22.07,1013.0,86 2006.259.08:04:01.27/cable/+6.4584E-03 2006.259.08:04:02.36/va/01,08,usb,yes,31,32 2006.259.08:04:02.36/va/02,07,usb,yes,31,32 2006.259.08:04:02.36/va/03,08,usb,yes,23,23 2006.259.08:04:02.36/va/04,07,usb,yes,32,34 2006.259.08:04:02.36/va/05,07,usb,yes,35,37 2006.259.08:04:02.36/va/06,06,usb,yes,34,34 2006.259.08:04:02.36/va/07,06,usb,yes,35,35 2006.259.08:04:02.36/va/08,06,usb,yes,37,37 2006.259.08:04:02.59/valo/01,532.99,yes,locked 2006.259.08:04:02.59/valo/02,572.99,yes,locked 2006.259.08:04:02.59/valo/03,672.99,yes,locked 2006.259.08:04:02.59/valo/04,832.99,yes,locked 2006.259.08:04:02.59/valo/05,652.99,yes,locked 2006.259.08:04:02.59/valo/06,772.99,yes,locked 2006.259.08:04:02.59/valo/07,832.99,yes,locked 2006.259.08:04:02.59/valo/08,852.99,yes,locked 2006.259.08:04:03.68/vb/01,04,usb,yes,30,29 2006.259.08:04:03.68/vb/02,05,usb,yes,28,29 2006.259.08:04:03.68/vb/03,04,usb,yes,28,32 2006.259.08:04:03.68/vb/04,05,usb,yes,25,26 2006.259.08:04:03.68/vb/05,04,usb,yes,27,31 2006.259.08:04:03.68/vb/06,04,usb,yes,28,31 2006.259.08:04:03.68/vb/07,04,usb,yes,30,30 2006.259.08:04:03.68/vb/08,04,usb,yes,28,31 2006.259.08:04:03.92/vblo/01,632.99,yes,locked 2006.259.08:04:03.92/vblo/02,640.99,yes,locked 2006.259.08:04:03.92/vblo/03,656.99,yes,locked 2006.259.08:04:03.92/vblo/04,712.99,yes,locked 2006.259.08:04:03.92/vblo/05,744.99,yes,locked 2006.259.08:04:03.92/vblo/06,752.99,yes,locked 2006.259.08:04:03.92/vblo/07,734.99,yes,locked 2006.259.08:04:03.92/vblo/08,744.99,yes,locked 2006.259.08:04:04.07/vabw/8 2006.259.08:04:04.22/vbbw/8 2006.259.08:04:04.31/xfe/off,on,16.0 2006.259.08:04:04.68/ifatt/23,28,28,28 2006.259.08:04:05.07/fmout-gps/S +4.59E-07 2006.259.08:04:05.11:!2006.259.08:05:00 2006.259.08:05:00.01:data_valid=off 2006.259.08:05:00.02:postob 2006.259.08:05:00.19/cable/+6.4587E-03 2006.259.08:05:00.20/wx/22.05,1013.0,86 2006.259.08:05:01.07/fmout-gps/S +4.59E-07 2006.259.08:05:01.08:scan_name=259-0805,k06259,60 2006.259.08:05:01.08:source=1044+719,104827.62,714335.9,2000.0,ccw 2006.259.08:05:01.13#flagr#flagr/antenna,new-source 2006.259.08:05:02.13:checkk5 2006.259.08:05:02.53/chk_autoobs//k5ts1/ autoobs is running! 2006.259.08:05:02.96/chk_autoobs//k5ts2/ autoobs is running! 2006.259.08:05:03.36/chk_autoobs//k5ts3/ autoobs is running! 2006.259.08:05:03.75/chk_autoobs//k5ts4/ autoobs is running! 2006.259.08:05:04.15/chk_obsdata//k5ts1/T2590804??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.259.08:05:04.53/chk_obsdata//k5ts2/T2590804??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.259.08:05:04.95/chk_obsdata//k5ts3/T2590804??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.259.08:05:05.36/chk_obsdata//k5ts4/T2590804??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.259.08:05:06.07/k5log//k5ts1_log_newline 2006.259.08:05:07.04/k5log//k5ts2_log_newline 2006.259.08:05:07.80/k5log//k5ts3_log_newline 2006.259.08:05:08.56/k5log//k5ts4_log_newline 2006.259.08:05:08.59/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.259.08:05:08.59:4f8m12a=2 2006.259.08:05:08.59$4f8m12a/echo=on 2006.259.08:05:08.59$4f8m12a/pcalon 2006.259.08:05:08.59$pcalon/"no phase cal control is implemented here 2006.259.08:05:08.59$4f8m12a/"tpicd=stop 2006.259.08:05:08.59$4f8m12a/vc4f8 2006.259.08:05:08.59$vc4f8/valo=1,532.99 2006.259.08:05:08.59#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.259.08:05:08.59#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.259.08:05:08.59#ibcon#ireg 17 cls_cnt 0 2006.259.08:05:08.59#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.259.08:05:08.59#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.259.08:05:08.59#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.259.08:05:08.59#ibcon#enter wrdev, iclass 36, count 0 2006.259.08:05:08.59#ibcon#first serial, iclass 36, count 0 2006.259.08:05:08.59#ibcon#enter sib2, iclass 36, count 0 2006.259.08:05:08.59#ibcon#flushed, iclass 36, count 0 2006.259.08:05:08.59#ibcon#about to write, iclass 36, count 0 2006.259.08:05:08.59#ibcon#wrote, iclass 36, count 0 2006.259.08:05:08.59#ibcon#about to read 3, iclass 36, count 0 2006.259.08:05:08.63#ibcon#read 3, iclass 36, count 0 2006.259.08:05:08.63#ibcon#about to read 4, iclass 36, count 0 2006.259.08:05:08.63#ibcon#read 4, iclass 36, count 0 2006.259.08:05:08.63#ibcon#about to read 5, iclass 36, count 0 2006.259.08:05:08.63#ibcon#read 5, iclass 36, count 0 2006.259.08:05:08.63#ibcon#about to read 6, iclass 36, count 0 2006.259.08:05:08.63#ibcon#read 6, iclass 36, count 0 2006.259.08:05:08.63#ibcon#end of sib2, iclass 36, count 0 2006.259.08:05:08.63#ibcon#*mode == 0, iclass 36, count 0 2006.259.08:05:08.63#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.259.08:05:08.63#ibcon#[26=FRQ=01,532.99\r\n] 2006.259.08:05:08.63#ibcon#*before write, iclass 36, count 0 2006.259.08:05:08.63#ibcon#enter sib2, iclass 36, count 0 2006.259.08:05:08.63#ibcon#flushed, iclass 36, count 0 2006.259.08:05:08.63#ibcon#about to write, iclass 36, count 0 2006.259.08:05:08.63#ibcon#wrote, iclass 36, count 0 2006.259.08:05:08.63#ibcon#about to read 3, iclass 36, count 0 2006.259.08:05:08.68#ibcon#read 3, iclass 36, count 0 2006.259.08:05:08.68#ibcon#about to read 4, iclass 36, count 0 2006.259.08:05:08.68#ibcon#read 4, iclass 36, count 0 2006.259.08:05:08.68#ibcon#about to read 5, iclass 36, count 0 2006.259.08:05:08.68#ibcon#read 5, iclass 36, count 0 2006.259.08:05:08.68#ibcon#about to read 6, iclass 36, count 0 2006.259.08:05:08.68#ibcon#read 6, iclass 36, count 0 2006.259.08:05:08.68#ibcon#end of sib2, iclass 36, count 0 2006.259.08:05:08.68#ibcon#*after write, iclass 36, count 0 2006.259.08:05:08.68#ibcon#*before return 0, iclass 36, count 0 2006.259.08:05:08.68#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.259.08:05:08.68#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.259.08:05:08.68#ibcon#about to clear, iclass 36 cls_cnt 0 2006.259.08:05:08.68#ibcon#cleared, iclass 36 cls_cnt 0 2006.259.08:05:08.68$vc4f8/va=1,8 2006.259.08:05:08.68#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.259.08:05:08.68#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.259.08:05:08.68#ibcon#ireg 11 cls_cnt 2 2006.259.08:05:08.68#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.259.08:05:08.68#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.259.08:05:08.68#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.259.08:05:08.68#ibcon#enter wrdev, iclass 38, count 2 2006.259.08:05:08.68#ibcon#first serial, iclass 38, count 2 2006.259.08:05:08.68#ibcon#enter sib2, iclass 38, count 2 2006.259.08:05:08.68#ibcon#flushed, iclass 38, count 2 2006.259.08:05:08.68#ibcon#about to write, iclass 38, count 2 2006.259.08:05:08.68#ibcon#wrote, iclass 38, count 2 2006.259.08:05:08.68#ibcon#about to read 3, iclass 38, count 2 2006.259.08:05:08.70#ibcon#read 3, iclass 38, count 2 2006.259.08:05:08.70#ibcon#about to read 4, iclass 38, count 2 2006.259.08:05:08.70#ibcon#read 4, iclass 38, count 2 2006.259.08:05:08.70#ibcon#about to read 5, iclass 38, count 2 2006.259.08:05:08.70#ibcon#read 5, iclass 38, count 2 2006.259.08:05:08.70#ibcon#about to read 6, iclass 38, count 2 2006.259.08:05:08.70#ibcon#read 6, iclass 38, count 2 2006.259.08:05:08.70#ibcon#end of sib2, iclass 38, count 2 2006.259.08:05:08.70#ibcon#*mode == 0, iclass 38, count 2 2006.259.08:05:08.70#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.259.08:05:08.70#ibcon#[25=AT01-08\r\n] 2006.259.08:05:08.70#ibcon#*before write, iclass 38, count 2 2006.259.08:05:08.70#ibcon#enter sib2, iclass 38, count 2 2006.259.08:05:08.70#ibcon#flushed, iclass 38, count 2 2006.259.08:05:08.70#ibcon#about to write, iclass 38, count 2 2006.259.08:05:08.70#ibcon#wrote, iclass 38, count 2 2006.259.08:05:08.70#ibcon#about to read 3, iclass 38, count 2 2006.259.08:05:08.73#ibcon#read 3, iclass 38, count 2 2006.259.08:05:08.73#ibcon#about to read 4, iclass 38, count 2 2006.259.08:05:08.73#ibcon#read 4, iclass 38, count 2 2006.259.08:05:08.73#ibcon#about to read 5, iclass 38, count 2 2006.259.08:05:08.73#ibcon#read 5, iclass 38, count 2 2006.259.08:05:08.73#ibcon#about to read 6, iclass 38, count 2 2006.259.08:05:08.73#ibcon#read 6, iclass 38, count 2 2006.259.08:05:08.73#ibcon#end of sib2, iclass 38, count 2 2006.259.08:05:08.73#ibcon#*after write, iclass 38, count 2 2006.259.08:05:08.73#ibcon#*before return 0, iclass 38, count 2 2006.259.08:05:08.73#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.259.08:05:08.73#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.259.08:05:08.73#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.259.08:05:08.73#ibcon#ireg 7 cls_cnt 0 2006.259.08:05:08.73#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.259.08:05:08.85#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.259.08:05:08.85#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.259.08:05:08.85#ibcon#enter wrdev, iclass 38, count 0 2006.259.08:05:08.85#ibcon#first serial, iclass 38, count 0 2006.259.08:05:08.85#ibcon#enter sib2, iclass 38, count 0 2006.259.08:05:08.85#ibcon#flushed, iclass 38, count 0 2006.259.08:05:08.85#ibcon#about to write, iclass 38, count 0 2006.259.08:05:08.85#ibcon#wrote, iclass 38, count 0 2006.259.08:05:08.85#ibcon#about to read 3, iclass 38, count 0 2006.259.08:05:08.87#ibcon#read 3, iclass 38, count 0 2006.259.08:05:08.87#ibcon#about to read 4, iclass 38, count 0 2006.259.08:05:08.87#ibcon#read 4, iclass 38, count 0 2006.259.08:05:08.87#ibcon#about to read 5, iclass 38, count 0 2006.259.08:05:08.87#ibcon#read 5, iclass 38, count 0 2006.259.08:05:08.87#ibcon#about to read 6, iclass 38, count 0 2006.259.08:05:08.87#ibcon#read 6, iclass 38, count 0 2006.259.08:05:08.87#ibcon#end of sib2, iclass 38, count 0 2006.259.08:05:08.87#ibcon#*mode == 0, iclass 38, count 0 2006.259.08:05:08.87#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.259.08:05:08.87#ibcon#[25=USB\r\n] 2006.259.08:05:08.87#ibcon#*before write, iclass 38, count 0 2006.259.08:05:08.87#ibcon#enter sib2, iclass 38, count 0 2006.259.08:05:08.87#ibcon#flushed, iclass 38, count 0 2006.259.08:05:08.87#ibcon#about to write, iclass 38, count 0 2006.259.08:05:08.87#ibcon#wrote, iclass 38, count 0 2006.259.08:05:08.87#ibcon#about to read 3, iclass 38, count 0 2006.259.08:05:08.90#ibcon#read 3, iclass 38, count 0 2006.259.08:05:08.90#ibcon#about to read 4, iclass 38, count 0 2006.259.08:05:08.90#ibcon#read 4, iclass 38, count 0 2006.259.08:05:08.90#ibcon#about to read 5, iclass 38, count 0 2006.259.08:05:08.90#ibcon#read 5, iclass 38, count 0 2006.259.08:05:08.90#ibcon#about to read 6, iclass 38, count 0 2006.259.08:05:08.90#ibcon#read 6, iclass 38, count 0 2006.259.08:05:08.90#ibcon#end of sib2, iclass 38, count 0 2006.259.08:05:08.90#ibcon#*after write, iclass 38, count 0 2006.259.08:05:08.90#ibcon#*before return 0, iclass 38, count 0 2006.259.08:05:08.90#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.259.08:05:08.90#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.259.08:05:08.90#ibcon#about to clear, iclass 38 cls_cnt 0 2006.259.08:05:08.90#ibcon#cleared, iclass 38 cls_cnt 0 2006.259.08:05:08.90$vc4f8/valo=2,572.99 2006.259.08:05:08.90#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.259.08:05:08.90#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.259.08:05:08.90#ibcon#ireg 17 cls_cnt 0 2006.259.08:05:08.90#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.259.08:05:08.90#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.259.08:05:08.90#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.259.08:05:08.90#ibcon#enter wrdev, iclass 40, count 0 2006.259.08:05:08.90#ibcon#first serial, iclass 40, count 0 2006.259.08:05:08.90#ibcon#enter sib2, iclass 40, count 0 2006.259.08:05:08.90#ibcon#flushed, iclass 40, count 0 2006.259.08:05:08.90#ibcon#about to write, iclass 40, count 0 2006.259.08:05:08.90#ibcon#wrote, iclass 40, count 0 2006.259.08:05:08.90#ibcon#about to read 3, iclass 40, count 0 2006.259.08:05:08.92#ibcon#read 3, iclass 40, count 0 2006.259.08:05:08.92#ibcon#about to read 4, iclass 40, count 0 2006.259.08:05:08.92#ibcon#read 4, iclass 40, count 0 2006.259.08:05:08.92#ibcon#about to read 5, iclass 40, count 0 2006.259.08:05:08.92#ibcon#read 5, iclass 40, count 0 2006.259.08:05:08.92#ibcon#about to read 6, iclass 40, count 0 2006.259.08:05:08.92#ibcon#read 6, iclass 40, count 0 2006.259.08:05:08.92#ibcon#end of sib2, iclass 40, count 0 2006.259.08:05:08.92#ibcon#*mode == 0, iclass 40, count 0 2006.259.08:05:08.92#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.259.08:05:08.92#ibcon#[26=FRQ=02,572.99\r\n] 2006.259.08:05:08.92#ibcon#*before write, iclass 40, count 0 2006.259.08:05:08.92#ibcon#enter sib2, iclass 40, count 0 2006.259.08:05:08.92#ibcon#flushed, iclass 40, count 0 2006.259.08:05:08.92#ibcon#about to write, iclass 40, count 0 2006.259.08:05:08.92#ibcon#wrote, iclass 40, count 0 2006.259.08:05:08.92#ibcon#about to read 3, iclass 40, count 0 2006.259.08:05:08.96#ibcon#read 3, iclass 40, count 0 2006.259.08:05:08.96#ibcon#about to read 4, iclass 40, count 0 2006.259.08:05:08.96#ibcon#read 4, iclass 40, count 0 2006.259.08:05:08.96#ibcon#about to read 5, iclass 40, count 0 2006.259.08:05:08.96#ibcon#read 5, iclass 40, count 0 2006.259.08:05:08.96#ibcon#about to read 6, iclass 40, count 0 2006.259.08:05:08.96#ibcon#read 6, iclass 40, count 0 2006.259.08:05:08.96#ibcon#end of sib2, iclass 40, count 0 2006.259.08:05:08.96#ibcon#*after write, iclass 40, count 0 2006.259.08:05:08.96#ibcon#*before return 0, iclass 40, count 0 2006.259.08:05:08.96#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.259.08:05:08.96#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.259.08:05:08.96#ibcon#about to clear, iclass 40 cls_cnt 0 2006.259.08:05:08.96#ibcon#cleared, iclass 40 cls_cnt 0 2006.259.08:05:08.96$vc4f8/va=2,7 2006.259.08:05:08.96#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.259.08:05:08.96#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.259.08:05:08.96#ibcon#ireg 11 cls_cnt 2 2006.259.08:05:08.96#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.259.08:05:09.02#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.259.08:05:09.02#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.259.08:05:09.02#ibcon#enter wrdev, iclass 4, count 2 2006.259.08:05:09.02#ibcon#first serial, iclass 4, count 2 2006.259.08:05:09.02#ibcon#enter sib2, iclass 4, count 2 2006.259.08:05:09.02#ibcon#flushed, iclass 4, count 2 2006.259.08:05:09.02#ibcon#about to write, iclass 4, count 2 2006.259.08:05:09.02#ibcon#wrote, iclass 4, count 2 2006.259.08:05:09.02#ibcon#about to read 3, iclass 4, count 2 2006.259.08:05:09.04#ibcon#read 3, iclass 4, count 2 2006.259.08:05:09.04#ibcon#about to read 4, iclass 4, count 2 2006.259.08:05:09.04#ibcon#read 4, iclass 4, count 2 2006.259.08:05:09.04#ibcon#about to read 5, iclass 4, count 2 2006.259.08:05:09.04#ibcon#read 5, iclass 4, count 2 2006.259.08:05:09.04#ibcon#about to read 6, iclass 4, count 2 2006.259.08:05:09.04#ibcon#read 6, iclass 4, count 2 2006.259.08:05:09.04#ibcon#end of sib2, iclass 4, count 2 2006.259.08:05:09.04#ibcon#*mode == 0, iclass 4, count 2 2006.259.08:05:09.04#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.259.08:05:09.04#ibcon#[25=AT02-07\r\n] 2006.259.08:05:09.04#ibcon#*before write, iclass 4, count 2 2006.259.08:05:09.04#ibcon#enter sib2, iclass 4, count 2 2006.259.08:05:09.04#ibcon#flushed, iclass 4, count 2 2006.259.08:05:09.04#ibcon#about to write, iclass 4, count 2 2006.259.08:05:09.04#ibcon#wrote, iclass 4, count 2 2006.259.08:05:09.04#ibcon#about to read 3, iclass 4, count 2 2006.259.08:05:09.07#ibcon#read 3, iclass 4, count 2 2006.259.08:05:09.07#ibcon#about to read 4, iclass 4, count 2 2006.259.08:05:09.07#ibcon#read 4, iclass 4, count 2 2006.259.08:05:09.07#ibcon#about to read 5, iclass 4, count 2 2006.259.08:05:09.07#ibcon#read 5, iclass 4, count 2 2006.259.08:05:09.07#ibcon#about to read 6, iclass 4, count 2 2006.259.08:05:09.07#ibcon#read 6, iclass 4, count 2 2006.259.08:05:09.07#ibcon#end of sib2, iclass 4, count 2 2006.259.08:05:09.07#ibcon#*after write, iclass 4, count 2 2006.259.08:05:09.07#ibcon#*before return 0, iclass 4, count 2 2006.259.08:05:09.07#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.259.08:05:09.07#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.259.08:05:09.07#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.259.08:05:09.07#ibcon#ireg 7 cls_cnt 0 2006.259.08:05:09.07#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.259.08:05:09.19#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.259.08:05:09.19#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.259.08:05:09.19#ibcon#enter wrdev, iclass 4, count 0 2006.259.08:05:09.19#ibcon#first serial, iclass 4, count 0 2006.259.08:05:09.19#ibcon#enter sib2, iclass 4, count 0 2006.259.08:05:09.19#ibcon#flushed, iclass 4, count 0 2006.259.08:05:09.19#ibcon#about to write, iclass 4, count 0 2006.259.08:05:09.19#ibcon#wrote, iclass 4, count 0 2006.259.08:05:09.19#ibcon#about to read 3, iclass 4, count 0 2006.259.08:05:09.21#ibcon#read 3, iclass 4, count 0 2006.259.08:05:09.21#ibcon#about to read 4, iclass 4, count 0 2006.259.08:05:09.21#ibcon#read 4, iclass 4, count 0 2006.259.08:05:09.21#ibcon#about to read 5, iclass 4, count 0 2006.259.08:05:09.21#ibcon#read 5, iclass 4, count 0 2006.259.08:05:09.21#ibcon#about to read 6, iclass 4, count 0 2006.259.08:05:09.21#ibcon#read 6, iclass 4, count 0 2006.259.08:05:09.21#ibcon#end of sib2, iclass 4, count 0 2006.259.08:05:09.21#ibcon#*mode == 0, iclass 4, count 0 2006.259.08:05:09.21#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.259.08:05:09.21#ibcon#[25=USB\r\n] 2006.259.08:05:09.21#ibcon#*before write, iclass 4, count 0 2006.259.08:05:09.21#ibcon#enter sib2, iclass 4, count 0 2006.259.08:05:09.21#ibcon#flushed, iclass 4, count 0 2006.259.08:05:09.21#ibcon#about to write, iclass 4, count 0 2006.259.08:05:09.21#ibcon#wrote, iclass 4, count 0 2006.259.08:05:09.21#ibcon#about to read 3, iclass 4, count 0 2006.259.08:05:09.24#ibcon#read 3, iclass 4, count 0 2006.259.08:05:09.24#ibcon#about to read 4, iclass 4, count 0 2006.259.08:05:09.24#ibcon#read 4, iclass 4, count 0 2006.259.08:05:09.24#ibcon#about to read 5, iclass 4, count 0 2006.259.08:05:09.24#ibcon#read 5, iclass 4, count 0 2006.259.08:05:09.24#ibcon#about to read 6, iclass 4, count 0 2006.259.08:05:09.24#ibcon#read 6, iclass 4, count 0 2006.259.08:05:09.24#ibcon#end of sib2, iclass 4, count 0 2006.259.08:05:09.24#ibcon#*after write, iclass 4, count 0 2006.259.08:05:09.24#ibcon#*before return 0, iclass 4, count 0 2006.259.08:05:09.24#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.259.08:05:09.24#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.259.08:05:09.24#ibcon#about to clear, iclass 4 cls_cnt 0 2006.259.08:05:09.24#ibcon#cleared, iclass 4 cls_cnt 0 2006.259.08:05:09.24$vc4f8/valo=3,672.99 2006.259.08:05:09.24#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.259.08:05:09.24#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.259.08:05:09.24#ibcon#ireg 17 cls_cnt 0 2006.259.08:05:09.24#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.259.08:05:09.24#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.259.08:05:09.24#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.259.08:05:09.24#ibcon#enter wrdev, iclass 6, count 0 2006.259.08:05:09.24#ibcon#first serial, iclass 6, count 0 2006.259.08:05:09.24#ibcon#enter sib2, iclass 6, count 0 2006.259.08:05:09.24#ibcon#flushed, iclass 6, count 0 2006.259.08:05:09.24#ibcon#about to write, iclass 6, count 0 2006.259.08:05:09.24#ibcon#wrote, iclass 6, count 0 2006.259.08:05:09.24#ibcon#about to read 3, iclass 6, count 0 2006.259.08:05:09.26#ibcon#read 3, iclass 6, count 0 2006.259.08:05:09.26#ibcon#about to read 4, iclass 6, count 0 2006.259.08:05:09.26#ibcon#read 4, iclass 6, count 0 2006.259.08:05:09.26#ibcon#about to read 5, iclass 6, count 0 2006.259.08:05:09.26#ibcon#read 5, iclass 6, count 0 2006.259.08:05:09.26#ibcon#about to read 6, iclass 6, count 0 2006.259.08:05:09.26#ibcon#read 6, iclass 6, count 0 2006.259.08:05:09.26#ibcon#end of sib2, iclass 6, count 0 2006.259.08:05:09.26#ibcon#*mode == 0, iclass 6, count 0 2006.259.08:05:09.26#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.259.08:05:09.26#ibcon#[26=FRQ=03,672.99\r\n] 2006.259.08:05:09.26#ibcon#*before write, iclass 6, count 0 2006.259.08:05:09.26#ibcon#enter sib2, iclass 6, count 0 2006.259.08:05:09.26#ibcon#flushed, iclass 6, count 0 2006.259.08:05:09.26#ibcon#about to write, iclass 6, count 0 2006.259.08:05:09.26#ibcon#wrote, iclass 6, count 0 2006.259.08:05:09.26#ibcon#about to read 3, iclass 6, count 0 2006.259.08:05:09.30#ibcon#read 3, iclass 6, count 0 2006.259.08:05:09.30#ibcon#about to read 4, iclass 6, count 0 2006.259.08:05:09.30#ibcon#read 4, iclass 6, count 0 2006.259.08:05:09.30#ibcon#about to read 5, iclass 6, count 0 2006.259.08:05:09.30#ibcon#read 5, iclass 6, count 0 2006.259.08:05:09.30#ibcon#about to read 6, iclass 6, count 0 2006.259.08:05:09.30#ibcon#read 6, iclass 6, count 0 2006.259.08:05:09.30#ibcon#end of sib2, iclass 6, count 0 2006.259.08:05:09.30#ibcon#*after write, iclass 6, count 0 2006.259.08:05:09.30#ibcon#*before return 0, iclass 6, count 0 2006.259.08:05:09.30#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.259.08:05:09.30#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.259.08:05:09.30#ibcon#about to clear, iclass 6 cls_cnt 0 2006.259.08:05:09.30#ibcon#cleared, iclass 6 cls_cnt 0 2006.259.08:05:09.30$vc4f8/va=3,8 2006.259.08:05:09.30#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.259.08:05:09.30#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.259.08:05:09.30#ibcon#ireg 11 cls_cnt 2 2006.259.08:05:09.30#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.259.08:05:09.36#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.259.08:05:09.36#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.259.08:05:09.36#ibcon#enter wrdev, iclass 10, count 2 2006.259.08:05:09.36#ibcon#first serial, iclass 10, count 2 2006.259.08:05:09.36#ibcon#enter sib2, iclass 10, count 2 2006.259.08:05:09.36#ibcon#flushed, iclass 10, count 2 2006.259.08:05:09.36#ibcon#about to write, iclass 10, count 2 2006.259.08:05:09.36#ibcon#wrote, iclass 10, count 2 2006.259.08:05:09.36#ibcon#about to read 3, iclass 10, count 2 2006.259.08:05:09.38#ibcon#read 3, iclass 10, count 2 2006.259.08:05:09.38#ibcon#about to read 4, iclass 10, count 2 2006.259.08:05:09.38#ibcon#read 4, iclass 10, count 2 2006.259.08:05:09.38#ibcon#about to read 5, iclass 10, count 2 2006.259.08:05:09.38#ibcon#read 5, iclass 10, count 2 2006.259.08:05:09.38#ibcon#about to read 6, iclass 10, count 2 2006.259.08:05:09.38#ibcon#read 6, iclass 10, count 2 2006.259.08:05:09.38#ibcon#end of sib2, iclass 10, count 2 2006.259.08:05:09.38#ibcon#*mode == 0, iclass 10, count 2 2006.259.08:05:09.38#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.259.08:05:09.38#ibcon#[25=AT03-08\r\n] 2006.259.08:05:09.38#ibcon#*before write, iclass 10, count 2 2006.259.08:05:09.38#ibcon#enter sib2, iclass 10, count 2 2006.259.08:05:09.38#ibcon#flushed, iclass 10, count 2 2006.259.08:05:09.38#ibcon#about to write, iclass 10, count 2 2006.259.08:05:09.38#ibcon#wrote, iclass 10, count 2 2006.259.08:05:09.38#ibcon#about to read 3, iclass 10, count 2 2006.259.08:05:09.41#ibcon#read 3, iclass 10, count 2 2006.259.08:05:09.41#ibcon#about to read 4, iclass 10, count 2 2006.259.08:05:09.41#ibcon#read 4, iclass 10, count 2 2006.259.08:05:09.41#ibcon#about to read 5, iclass 10, count 2 2006.259.08:05:09.41#ibcon#read 5, iclass 10, count 2 2006.259.08:05:09.41#ibcon#about to read 6, iclass 10, count 2 2006.259.08:05:09.41#ibcon#read 6, iclass 10, count 2 2006.259.08:05:09.41#ibcon#end of sib2, iclass 10, count 2 2006.259.08:05:09.41#ibcon#*after write, iclass 10, count 2 2006.259.08:05:09.41#ibcon#*before return 0, iclass 10, count 2 2006.259.08:05:09.41#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.259.08:05:09.41#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.259.08:05:09.41#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.259.08:05:09.41#ibcon#ireg 7 cls_cnt 0 2006.259.08:05:09.41#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.259.08:05:09.53#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.259.08:05:09.53#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.259.08:05:09.53#ibcon#enter wrdev, iclass 10, count 0 2006.259.08:05:09.53#ibcon#first serial, iclass 10, count 0 2006.259.08:05:09.53#ibcon#enter sib2, iclass 10, count 0 2006.259.08:05:09.53#ibcon#flushed, iclass 10, count 0 2006.259.08:05:09.53#ibcon#about to write, iclass 10, count 0 2006.259.08:05:09.53#ibcon#wrote, iclass 10, count 0 2006.259.08:05:09.53#ibcon#about to read 3, iclass 10, count 0 2006.259.08:05:09.55#ibcon#read 3, iclass 10, count 0 2006.259.08:05:09.55#ibcon#about to read 4, iclass 10, count 0 2006.259.08:05:09.55#ibcon#read 4, iclass 10, count 0 2006.259.08:05:09.55#ibcon#about to read 5, iclass 10, count 0 2006.259.08:05:09.55#ibcon#read 5, iclass 10, count 0 2006.259.08:05:09.55#ibcon#about to read 6, iclass 10, count 0 2006.259.08:05:09.55#ibcon#read 6, iclass 10, count 0 2006.259.08:05:09.55#ibcon#end of sib2, iclass 10, count 0 2006.259.08:05:09.55#ibcon#*mode == 0, iclass 10, count 0 2006.259.08:05:09.55#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.259.08:05:09.55#ibcon#[25=USB\r\n] 2006.259.08:05:09.55#ibcon#*before write, iclass 10, count 0 2006.259.08:05:09.55#ibcon#enter sib2, iclass 10, count 0 2006.259.08:05:09.55#ibcon#flushed, iclass 10, count 0 2006.259.08:05:09.55#ibcon#about to write, iclass 10, count 0 2006.259.08:05:09.55#ibcon#wrote, iclass 10, count 0 2006.259.08:05:09.55#ibcon#about to read 3, iclass 10, count 0 2006.259.08:05:09.58#ibcon#read 3, iclass 10, count 0 2006.259.08:05:09.58#ibcon#about to read 4, iclass 10, count 0 2006.259.08:05:09.58#ibcon#read 4, iclass 10, count 0 2006.259.08:05:09.58#ibcon#about to read 5, iclass 10, count 0 2006.259.08:05:09.58#ibcon#read 5, iclass 10, count 0 2006.259.08:05:09.58#ibcon#about to read 6, iclass 10, count 0 2006.259.08:05:09.58#ibcon#read 6, iclass 10, count 0 2006.259.08:05:09.58#ibcon#end of sib2, iclass 10, count 0 2006.259.08:05:09.58#ibcon#*after write, iclass 10, count 0 2006.259.08:05:09.58#ibcon#*before return 0, iclass 10, count 0 2006.259.08:05:09.58#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.259.08:05:09.58#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.259.08:05:09.58#ibcon#about to clear, iclass 10 cls_cnt 0 2006.259.08:05:09.58#ibcon#cleared, iclass 10 cls_cnt 0 2006.259.08:05:09.58$vc4f8/valo=4,832.99 2006.259.08:05:09.58#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.259.08:05:09.58#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.259.08:05:09.58#ibcon#ireg 17 cls_cnt 0 2006.259.08:05:09.58#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.259.08:05:09.58#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.259.08:05:09.58#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.259.08:05:09.58#ibcon#enter wrdev, iclass 12, count 0 2006.259.08:05:09.58#ibcon#first serial, iclass 12, count 0 2006.259.08:05:09.58#ibcon#enter sib2, iclass 12, count 0 2006.259.08:05:09.58#ibcon#flushed, iclass 12, count 0 2006.259.08:05:09.58#ibcon#about to write, iclass 12, count 0 2006.259.08:05:09.58#ibcon#wrote, iclass 12, count 0 2006.259.08:05:09.58#ibcon#about to read 3, iclass 12, count 0 2006.259.08:05:09.60#ibcon#read 3, iclass 12, count 0 2006.259.08:05:09.60#ibcon#about to read 4, iclass 12, count 0 2006.259.08:05:09.60#ibcon#read 4, iclass 12, count 0 2006.259.08:05:09.60#ibcon#about to read 5, iclass 12, count 0 2006.259.08:05:09.60#ibcon#read 5, iclass 12, count 0 2006.259.08:05:09.60#ibcon#about to read 6, iclass 12, count 0 2006.259.08:05:09.60#ibcon#read 6, iclass 12, count 0 2006.259.08:05:09.60#ibcon#end of sib2, iclass 12, count 0 2006.259.08:05:09.60#ibcon#*mode == 0, iclass 12, count 0 2006.259.08:05:09.60#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.259.08:05:09.60#ibcon#[26=FRQ=04,832.99\r\n] 2006.259.08:05:09.60#ibcon#*before write, iclass 12, count 0 2006.259.08:05:09.60#ibcon#enter sib2, iclass 12, count 0 2006.259.08:05:09.60#ibcon#flushed, iclass 12, count 0 2006.259.08:05:09.60#ibcon#about to write, iclass 12, count 0 2006.259.08:05:09.60#ibcon#wrote, iclass 12, count 0 2006.259.08:05:09.60#ibcon#about to read 3, iclass 12, count 0 2006.259.08:05:09.64#ibcon#read 3, iclass 12, count 0 2006.259.08:05:09.64#ibcon#about to read 4, iclass 12, count 0 2006.259.08:05:09.64#ibcon#read 4, iclass 12, count 0 2006.259.08:05:09.64#ibcon#about to read 5, iclass 12, count 0 2006.259.08:05:09.64#ibcon#read 5, iclass 12, count 0 2006.259.08:05:09.64#ibcon#about to read 6, iclass 12, count 0 2006.259.08:05:09.64#ibcon#read 6, iclass 12, count 0 2006.259.08:05:09.64#ibcon#end of sib2, iclass 12, count 0 2006.259.08:05:09.64#ibcon#*after write, iclass 12, count 0 2006.259.08:05:09.64#ibcon#*before return 0, iclass 12, count 0 2006.259.08:05:09.64#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.259.08:05:09.64#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.259.08:05:09.64#ibcon#about to clear, iclass 12 cls_cnt 0 2006.259.08:05:09.64#ibcon#cleared, iclass 12 cls_cnt 0 2006.259.08:05:09.64$vc4f8/va=4,7 2006.259.08:05:09.64#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.259.08:05:09.64#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.259.08:05:09.64#ibcon#ireg 11 cls_cnt 2 2006.259.08:05:09.64#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.259.08:05:09.70#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.259.08:05:09.70#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.259.08:05:09.70#ibcon#enter wrdev, iclass 14, count 2 2006.259.08:05:09.70#ibcon#first serial, iclass 14, count 2 2006.259.08:05:09.70#ibcon#enter sib2, iclass 14, count 2 2006.259.08:05:09.70#ibcon#flushed, iclass 14, count 2 2006.259.08:05:09.70#ibcon#about to write, iclass 14, count 2 2006.259.08:05:09.70#ibcon#wrote, iclass 14, count 2 2006.259.08:05:09.70#ibcon#about to read 3, iclass 14, count 2 2006.259.08:05:09.72#ibcon#read 3, iclass 14, count 2 2006.259.08:05:09.72#ibcon#about to read 4, iclass 14, count 2 2006.259.08:05:09.72#ibcon#read 4, iclass 14, count 2 2006.259.08:05:09.72#ibcon#about to read 5, iclass 14, count 2 2006.259.08:05:09.72#ibcon#read 5, iclass 14, count 2 2006.259.08:05:09.72#ibcon#about to read 6, iclass 14, count 2 2006.259.08:05:09.72#ibcon#read 6, iclass 14, count 2 2006.259.08:05:09.72#ibcon#end of sib2, iclass 14, count 2 2006.259.08:05:09.72#ibcon#*mode == 0, iclass 14, count 2 2006.259.08:05:09.72#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.259.08:05:09.72#ibcon#[25=AT04-07\r\n] 2006.259.08:05:09.72#ibcon#*before write, iclass 14, count 2 2006.259.08:05:09.72#ibcon#enter sib2, iclass 14, count 2 2006.259.08:05:09.72#ibcon#flushed, iclass 14, count 2 2006.259.08:05:09.72#ibcon#about to write, iclass 14, count 2 2006.259.08:05:09.72#ibcon#wrote, iclass 14, count 2 2006.259.08:05:09.72#ibcon#about to read 3, iclass 14, count 2 2006.259.08:05:09.75#ibcon#read 3, iclass 14, count 2 2006.259.08:05:09.75#ibcon#about to read 4, iclass 14, count 2 2006.259.08:05:09.75#ibcon#read 4, iclass 14, count 2 2006.259.08:05:09.75#ibcon#about to read 5, iclass 14, count 2 2006.259.08:05:09.75#ibcon#read 5, iclass 14, count 2 2006.259.08:05:09.75#ibcon#about to read 6, iclass 14, count 2 2006.259.08:05:09.75#ibcon#read 6, iclass 14, count 2 2006.259.08:05:09.75#ibcon#end of sib2, iclass 14, count 2 2006.259.08:05:09.75#ibcon#*after write, iclass 14, count 2 2006.259.08:05:09.75#ibcon#*before return 0, iclass 14, count 2 2006.259.08:05:09.75#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.259.08:05:09.75#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.259.08:05:09.75#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.259.08:05:09.75#ibcon#ireg 7 cls_cnt 0 2006.259.08:05:09.75#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.259.08:05:09.87#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.259.08:05:09.87#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.259.08:05:09.87#ibcon#enter wrdev, iclass 14, count 0 2006.259.08:05:09.87#ibcon#first serial, iclass 14, count 0 2006.259.08:05:09.87#ibcon#enter sib2, iclass 14, count 0 2006.259.08:05:09.87#ibcon#flushed, iclass 14, count 0 2006.259.08:05:09.87#ibcon#about to write, iclass 14, count 0 2006.259.08:05:09.87#ibcon#wrote, iclass 14, count 0 2006.259.08:05:09.87#ibcon#about to read 3, iclass 14, count 0 2006.259.08:05:09.89#ibcon#read 3, iclass 14, count 0 2006.259.08:05:09.89#ibcon#about to read 4, iclass 14, count 0 2006.259.08:05:09.89#ibcon#read 4, iclass 14, count 0 2006.259.08:05:09.89#ibcon#about to read 5, iclass 14, count 0 2006.259.08:05:09.89#ibcon#read 5, iclass 14, count 0 2006.259.08:05:09.89#ibcon#about to read 6, iclass 14, count 0 2006.259.08:05:09.89#ibcon#read 6, iclass 14, count 0 2006.259.08:05:09.89#ibcon#end of sib2, iclass 14, count 0 2006.259.08:05:09.89#ibcon#*mode == 0, iclass 14, count 0 2006.259.08:05:09.89#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.259.08:05:09.89#ibcon#[25=USB\r\n] 2006.259.08:05:09.89#ibcon#*before write, iclass 14, count 0 2006.259.08:05:09.89#ibcon#enter sib2, iclass 14, count 0 2006.259.08:05:09.89#ibcon#flushed, iclass 14, count 0 2006.259.08:05:09.89#ibcon#about to write, iclass 14, count 0 2006.259.08:05:09.89#ibcon#wrote, iclass 14, count 0 2006.259.08:05:09.89#ibcon#about to read 3, iclass 14, count 0 2006.259.08:05:09.92#ibcon#read 3, iclass 14, count 0 2006.259.08:05:09.92#ibcon#about to read 4, iclass 14, count 0 2006.259.08:05:09.92#ibcon#read 4, iclass 14, count 0 2006.259.08:05:09.92#ibcon#about to read 5, iclass 14, count 0 2006.259.08:05:09.92#ibcon#read 5, iclass 14, count 0 2006.259.08:05:09.92#ibcon#about to read 6, iclass 14, count 0 2006.259.08:05:09.92#ibcon#read 6, iclass 14, count 0 2006.259.08:05:09.92#ibcon#end of sib2, iclass 14, count 0 2006.259.08:05:09.92#ibcon#*after write, iclass 14, count 0 2006.259.08:05:09.92#ibcon#*before return 0, iclass 14, count 0 2006.259.08:05:09.92#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.259.08:05:09.92#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.259.08:05:09.92#ibcon#about to clear, iclass 14 cls_cnt 0 2006.259.08:05:09.92#ibcon#cleared, iclass 14 cls_cnt 0 2006.259.08:05:09.92$vc4f8/valo=5,652.99 2006.259.08:05:09.92#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.259.08:05:09.92#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.259.08:05:09.92#ibcon#ireg 17 cls_cnt 0 2006.259.08:05:09.92#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.259.08:05:09.92#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.259.08:05:09.92#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.259.08:05:09.92#ibcon#enter wrdev, iclass 16, count 0 2006.259.08:05:09.92#ibcon#first serial, iclass 16, count 0 2006.259.08:05:09.92#ibcon#enter sib2, iclass 16, count 0 2006.259.08:05:09.92#ibcon#flushed, iclass 16, count 0 2006.259.08:05:09.92#ibcon#about to write, iclass 16, count 0 2006.259.08:05:09.92#ibcon#wrote, iclass 16, count 0 2006.259.08:05:09.92#ibcon#about to read 3, iclass 16, count 0 2006.259.08:05:09.94#ibcon#read 3, iclass 16, count 0 2006.259.08:05:09.94#ibcon#about to read 4, iclass 16, count 0 2006.259.08:05:09.94#ibcon#read 4, iclass 16, count 0 2006.259.08:05:09.94#ibcon#about to read 5, iclass 16, count 0 2006.259.08:05:09.94#ibcon#read 5, iclass 16, count 0 2006.259.08:05:09.94#ibcon#about to read 6, iclass 16, count 0 2006.259.08:05:09.94#ibcon#read 6, iclass 16, count 0 2006.259.08:05:09.94#ibcon#end of sib2, iclass 16, count 0 2006.259.08:05:09.94#ibcon#*mode == 0, iclass 16, count 0 2006.259.08:05:09.94#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.259.08:05:09.94#ibcon#[26=FRQ=05,652.99\r\n] 2006.259.08:05:09.94#ibcon#*before write, iclass 16, count 0 2006.259.08:05:09.94#ibcon#enter sib2, iclass 16, count 0 2006.259.08:05:09.94#ibcon#flushed, iclass 16, count 0 2006.259.08:05:09.94#ibcon#about to write, iclass 16, count 0 2006.259.08:05:09.94#ibcon#wrote, iclass 16, count 0 2006.259.08:05:09.94#ibcon#about to read 3, iclass 16, count 0 2006.259.08:05:09.98#ibcon#read 3, iclass 16, count 0 2006.259.08:05:09.98#ibcon#about to read 4, iclass 16, count 0 2006.259.08:05:09.98#ibcon#read 4, iclass 16, count 0 2006.259.08:05:09.98#ibcon#about to read 5, iclass 16, count 0 2006.259.08:05:09.98#ibcon#read 5, iclass 16, count 0 2006.259.08:05:09.98#ibcon#about to read 6, iclass 16, count 0 2006.259.08:05:09.98#ibcon#read 6, iclass 16, count 0 2006.259.08:05:09.98#ibcon#end of sib2, iclass 16, count 0 2006.259.08:05:09.98#ibcon#*after write, iclass 16, count 0 2006.259.08:05:09.98#ibcon#*before return 0, iclass 16, count 0 2006.259.08:05:09.98#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.259.08:05:09.98#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.259.08:05:09.98#ibcon#about to clear, iclass 16 cls_cnt 0 2006.259.08:05:09.98#ibcon#cleared, iclass 16 cls_cnt 0 2006.259.08:05:09.98$vc4f8/va=5,7 2006.259.08:05:09.98#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.259.08:05:09.98#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.259.08:05:09.98#ibcon#ireg 11 cls_cnt 2 2006.259.08:05:09.98#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.259.08:05:10.04#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.259.08:05:10.04#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.259.08:05:10.04#ibcon#enter wrdev, iclass 18, count 2 2006.259.08:05:10.04#ibcon#first serial, iclass 18, count 2 2006.259.08:05:10.04#ibcon#enter sib2, iclass 18, count 2 2006.259.08:05:10.04#ibcon#flushed, iclass 18, count 2 2006.259.08:05:10.04#ibcon#about to write, iclass 18, count 2 2006.259.08:05:10.04#ibcon#wrote, iclass 18, count 2 2006.259.08:05:10.04#ibcon#about to read 3, iclass 18, count 2 2006.259.08:05:10.06#ibcon#read 3, iclass 18, count 2 2006.259.08:05:10.06#ibcon#about to read 4, iclass 18, count 2 2006.259.08:05:10.06#ibcon#read 4, iclass 18, count 2 2006.259.08:05:10.06#ibcon#about to read 5, iclass 18, count 2 2006.259.08:05:10.06#ibcon#read 5, iclass 18, count 2 2006.259.08:05:10.06#ibcon#about to read 6, iclass 18, count 2 2006.259.08:05:10.06#ibcon#read 6, iclass 18, count 2 2006.259.08:05:10.06#ibcon#end of sib2, iclass 18, count 2 2006.259.08:05:10.06#ibcon#*mode == 0, iclass 18, count 2 2006.259.08:05:10.06#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.259.08:05:10.06#ibcon#[25=AT05-07\r\n] 2006.259.08:05:10.06#ibcon#*before write, iclass 18, count 2 2006.259.08:05:10.06#ibcon#enter sib2, iclass 18, count 2 2006.259.08:05:10.06#ibcon#flushed, iclass 18, count 2 2006.259.08:05:10.06#ibcon#about to write, iclass 18, count 2 2006.259.08:05:10.06#ibcon#wrote, iclass 18, count 2 2006.259.08:05:10.06#ibcon#about to read 3, iclass 18, count 2 2006.259.08:05:10.09#ibcon#read 3, iclass 18, count 2 2006.259.08:05:10.09#ibcon#about to read 4, iclass 18, count 2 2006.259.08:05:10.09#ibcon#read 4, iclass 18, count 2 2006.259.08:05:10.09#ibcon#about to read 5, iclass 18, count 2 2006.259.08:05:10.09#ibcon#read 5, iclass 18, count 2 2006.259.08:05:10.09#ibcon#about to read 6, iclass 18, count 2 2006.259.08:05:10.09#ibcon#read 6, iclass 18, count 2 2006.259.08:05:10.09#ibcon#end of sib2, iclass 18, count 2 2006.259.08:05:10.09#ibcon#*after write, iclass 18, count 2 2006.259.08:05:10.09#ibcon#*before return 0, iclass 18, count 2 2006.259.08:05:10.09#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.259.08:05:10.09#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.259.08:05:10.09#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.259.08:05:10.09#ibcon#ireg 7 cls_cnt 0 2006.259.08:05:10.09#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.259.08:05:10.21#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.259.08:05:10.21#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.259.08:05:10.21#ibcon#enter wrdev, iclass 18, count 0 2006.259.08:05:10.21#ibcon#first serial, iclass 18, count 0 2006.259.08:05:10.21#ibcon#enter sib2, iclass 18, count 0 2006.259.08:05:10.21#ibcon#flushed, iclass 18, count 0 2006.259.08:05:10.21#ibcon#about to write, iclass 18, count 0 2006.259.08:05:10.21#ibcon#wrote, iclass 18, count 0 2006.259.08:05:10.21#ibcon#about to read 3, iclass 18, count 0 2006.259.08:05:10.23#ibcon#read 3, iclass 18, count 0 2006.259.08:05:10.23#ibcon#about to read 4, iclass 18, count 0 2006.259.08:05:10.23#ibcon#read 4, iclass 18, count 0 2006.259.08:05:10.23#ibcon#about to read 5, iclass 18, count 0 2006.259.08:05:10.23#ibcon#read 5, iclass 18, count 0 2006.259.08:05:10.23#ibcon#about to read 6, iclass 18, count 0 2006.259.08:05:10.23#ibcon#read 6, iclass 18, count 0 2006.259.08:05:10.23#ibcon#end of sib2, iclass 18, count 0 2006.259.08:05:10.23#ibcon#*mode == 0, iclass 18, count 0 2006.259.08:05:10.23#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.259.08:05:10.23#ibcon#[25=USB\r\n] 2006.259.08:05:10.23#ibcon#*before write, iclass 18, count 0 2006.259.08:05:10.23#ibcon#enter sib2, iclass 18, count 0 2006.259.08:05:10.23#ibcon#flushed, iclass 18, count 0 2006.259.08:05:10.23#ibcon#about to write, iclass 18, count 0 2006.259.08:05:10.23#ibcon#wrote, iclass 18, count 0 2006.259.08:05:10.23#ibcon#about to read 3, iclass 18, count 0 2006.259.08:05:10.26#ibcon#read 3, iclass 18, count 0 2006.259.08:05:10.26#ibcon#about to read 4, iclass 18, count 0 2006.259.08:05:10.26#ibcon#read 4, iclass 18, count 0 2006.259.08:05:10.26#ibcon#about to read 5, iclass 18, count 0 2006.259.08:05:10.26#ibcon#read 5, iclass 18, count 0 2006.259.08:05:10.26#ibcon#about to read 6, iclass 18, count 0 2006.259.08:05:10.26#ibcon#read 6, iclass 18, count 0 2006.259.08:05:10.26#ibcon#end of sib2, iclass 18, count 0 2006.259.08:05:10.26#ibcon#*after write, iclass 18, count 0 2006.259.08:05:10.26#ibcon#*before return 0, iclass 18, count 0 2006.259.08:05:10.26#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.259.08:05:10.26#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.259.08:05:10.26#ibcon#about to clear, iclass 18 cls_cnt 0 2006.259.08:05:10.26#ibcon#cleared, iclass 18 cls_cnt 0 2006.259.08:05:10.26$vc4f8/valo=6,772.99 2006.259.08:05:10.26#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.259.08:05:10.26#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.259.08:05:10.26#ibcon#ireg 17 cls_cnt 0 2006.259.08:05:10.26#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.259.08:05:10.26#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.259.08:05:10.26#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.259.08:05:10.26#ibcon#enter wrdev, iclass 20, count 0 2006.259.08:05:10.26#ibcon#first serial, iclass 20, count 0 2006.259.08:05:10.26#ibcon#enter sib2, iclass 20, count 0 2006.259.08:05:10.26#ibcon#flushed, iclass 20, count 0 2006.259.08:05:10.26#ibcon#about to write, iclass 20, count 0 2006.259.08:05:10.26#ibcon#wrote, iclass 20, count 0 2006.259.08:05:10.26#ibcon#about to read 3, iclass 20, count 0 2006.259.08:05:10.28#ibcon#read 3, iclass 20, count 0 2006.259.08:05:10.28#ibcon#about to read 4, iclass 20, count 0 2006.259.08:05:10.28#ibcon#read 4, iclass 20, count 0 2006.259.08:05:10.28#ibcon#about to read 5, iclass 20, count 0 2006.259.08:05:10.28#ibcon#read 5, iclass 20, count 0 2006.259.08:05:10.28#ibcon#about to read 6, iclass 20, count 0 2006.259.08:05:10.28#ibcon#read 6, iclass 20, count 0 2006.259.08:05:10.28#ibcon#end of sib2, iclass 20, count 0 2006.259.08:05:10.28#ibcon#*mode == 0, iclass 20, count 0 2006.259.08:05:10.28#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.259.08:05:10.28#ibcon#[26=FRQ=06,772.99\r\n] 2006.259.08:05:10.28#ibcon#*before write, iclass 20, count 0 2006.259.08:05:10.28#ibcon#enter sib2, iclass 20, count 0 2006.259.08:05:10.28#ibcon#flushed, iclass 20, count 0 2006.259.08:05:10.28#ibcon#about to write, iclass 20, count 0 2006.259.08:05:10.28#ibcon#wrote, iclass 20, count 0 2006.259.08:05:10.28#ibcon#about to read 3, iclass 20, count 0 2006.259.08:05:10.32#ibcon#read 3, iclass 20, count 0 2006.259.08:05:10.32#ibcon#about to read 4, iclass 20, count 0 2006.259.08:05:10.32#ibcon#read 4, iclass 20, count 0 2006.259.08:05:10.32#ibcon#about to read 5, iclass 20, count 0 2006.259.08:05:10.32#ibcon#read 5, iclass 20, count 0 2006.259.08:05:10.32#ibcon#about to read 6, iclass 20, count 0 2006.259.08:05:10.32#ibcon#read 6, iclass 20, count 0 2006.259.08:05:10.32#ibcon#end of sib2, iclass 20, count 0 2006.259.08:05:10.32#ibcon#*after write, iclass 20, count 0 2006.259.08:05:10.32#ibcon#*before return 0, iclass 20, count 0 2006.259.08:05:10.32#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.259.08:05:10.32#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.259.08:05:10.32#ibcon#about to clear, iclass 20 cls_cnt 0 2006.259.08:05:10.32#ibcon#cleared, iclass 20 cls_cnt 0 2006.259.08:05:10.32$vc4f8/va=6,6 2006.259.08:05:10.32#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.259.08:05:10.32#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.259.08:05:10.32#ibcon#ireg 11 cls_cnt 2 2006.259.08:05:10.32#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.259.08:05:10.38#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.259.08:05:10.38#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.259.08:05:10.38#ibcon#enter wrdev, iclass 22, count 2 2006.259.08:05:10.38#ibcon#first serial, iclass 22, count 2 2006.259.08:05:10.38#ibcon#enter sib2, iclass 22, count 2 2006.259.08:05:10.38#ibcon#flushed, iclass 22, count 2 2006.259.08:05:10.38#ibcon#about to write, iclass 22, count 2 2006.259.08:05:10.38#ibcon#wrote, iclass 22, count 2 2006.259.08:05:10.38#ibcon#about to read 3, iclass 22, count 2 2006.259.08:05:10.40#ibcon#read 3, iclass 22, count 2 2006.259.08:05:10.40#ibcon#about to read 4, iclass 22, count 2 2006.259.08:05:10.40#ibcon#read 4, iclass 22, count 2 2006.259.08:05:10.40#ibcon#about to read 5, iclass 22, count 2 2006.259.08:05:10.40#ibcon#read 5, iclass 22, count 2 2006.259.08:05:10.40#ibcon#about to read 6, iclass 22, count 2 2006.259.08:05:10.40#ibcon#read 6, iclass 22, count 2 2006.259.08:05:10.40#ibcon#end of sib2, iclass 22, count 2 2006.259.08:05:10.40#ibcon#*mode == 0, iclass 22, count 2 2006.259.08:05:10.40#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.259.08:05:10.40#ibcon#[25=AT06-06\r\n] 2006.259.08:05:10.40#ibcon#*before write, iclass 22, count 2 2006.259.08:05:10.40#ibcon#enter sib2, iclass 22, count 2 2006.259.08:05:10.40#ibcon#flushed, iclass 22, count 2 2006.259.08:05:10.40#ibcon#about to write, iclass 22, count 2 2006.259.08:05:10.40#ibcon#wrote, iclass 22, count 2 2006.259.08:05:10.40#ibcon#about to read 3, iclass 22, count 2 2006.259.08:05:10.43#ibcon#read 3, iclass 22, count 2 2006.259.08:05:10.43#ibcon#about to read 4, iclass 22, count 2 2006.259.08:05:10.43#ibcon#read 4, iclass 22, count 2 2006.259.08:05:10.43#ibcon#about to read 5, iclass 22, count 2 2006.259.08:05:10.43#ibcon#read 5, iclass 22, count 2 2006.259.08:05:10.43#ibcon#about to read 6, iclass 22, count 2 2006.259.08:05:10.43#ibcon#read 6, iclass 22, count 2 2006.259.08:05:10.43#ibcon#end of sib2, iclass 22, count 2 2006.259.08:05:10.43#ibcon#*after write, iclass 22, count 2 2006.259.08:05:10.43#ibcon#*before return 0, iclass 22, count 2 2006.259.08:05:10.43#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.259.08:05:10.43#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.259.08:05:10.43#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.259.08:05:10.43#ibcon#ireg 7 cls_cnt 0 2006.259.08:05:10.43#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.259.08:05:10.55#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.259.08:05:10.55#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.259.08:05:10.55#ibcon#enter wrdev, iclass 22, count 0 2006.259.08:05:10.55#ibcon#first serial, iclass 22, count 0 2006.259.08:05:10.55#ibcon#enter sib2, iclass 22, count 0 2006.259.08:05:10.55#ibcon#flushed, iclass 22, count 0 2006.259.08:05:10.55#ibcon#about to write, iclass 22, count 0 2006.259.08:05:10.55#ibcon#wrote, iclass 22, count 0 2006.259.08:05:10.55#ibcon#about to read 3, iclass 22, count 0 2006.259.08:05:10.57#ibcon#read 3, iclass 22, count 0 2006.259.08:05:10.57#ibcon#about to read 4, iclass 22, count 0 2006.259.08:05:10.57#ibcon#read 4, iclass 22, count 0 2006.259.08:05:10.57#ibcon#about to read 5, iclass 22, count 0 2006.259.08:05:10.57#ibcon#read 5, iclass 22, count 0 2006.259.08:05:10.57#ibcon#about to read 6, iclass 22, count 0 2006.259.08:05:10.57#ibcon#read 6, iclass 22, count 0 2006.259.08:05:10.57#ibcon#end of sib2, iclass 22, count 0 2006.259.08:05:10.57#ibcon#*mode == 0, iclass 22, count 0 2006.259.08:05:10.57#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.259.08:05:10.57#ibcon#[25=USB\r\n] 2006.259.08:05:10.57#ibcon#*before write, iclass 22, count 0 2006.259.08:05:10.57#ibcon#enter sib2, iclass 22, count 0 2006.259.08:05:10.57#ibcon#flushed, iclass 22, count 0 2006.259.08:05:10.57#ibcon#about to write, iclass 22, count 0 2006.259.08:05:10.57#ibcon#wrote, iclass 22, count 0 2006.259.08:05:10.57#ibcon#about to read 3, iclass 22, count 0 2006.259.08:05:10.60#ibcon#read 3, iclass 22, count 0 2006.259.08:05:10.60#ibcon#about to read 4, iclass 22, count 0 2006.259.08:05:10.60#ibcon#read 4, iclass 22, count 0 2006.259.08:05:10.60#ibcon#about to read 5, iclass 22, count 0 2006.259.08:05:10.60#ibcon#read 5, iclass 22, count 0 2006.259.08:05:10.60#ibcon#about to read 6, iclass 22, count 0 2006.259.08:05:10.60#ibcon#read 6, iclass 22, count 0 2006.259.08:05:10.60#ibcon#end of sib2, iclass 22, count 0 2006.259.08:05:10.60#ibcon#*after write, iclass 22, count 0 2006.259.08:05:10.60#ibcon#*before return 0, iclass 22, count 0 2006.259.08:05:10.60#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.259.08:05:10.60#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.259.08:05:10.60#ibcon#about to clear, iclass 22 cls_cnt 0 2006.259.08:05:10.60#ibcon#cleared, iclass 22 cls_cnt 0 2006.259.08:05:10.60$vc4f8/valo=7,832.99 2006.259.08:05:10.60#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.259.08:05:10.60#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.259.08:05:10.60#ibcon#ireg 17 cls_cnt 0 2006.259.08:05:10.60#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.259.08:05:10.60#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.259.08:05:10.60#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.259.08:05:10.60#ibcon#enter wrdev, iclass 24, count 0 2006.259.08:05:10.60#ibcon#first serial, iclass 24, count 0 2006.259.08:05:10.60#ibcon#enter sib2, iclass 24, count 0 2006.259.08:05:10.60#ibcon#flushed, iclass 24, count 0 2006.259.08:05:10.60#ibcon#about to write, iclass 24, count 0 2006.259.08:05:10.60#ibcon#wrote, iclass 24, count 0 2006.259.08:05:10.60#ibcon#about to read 3, iclass 24, count 0 2006.259.08:05:10.62#ibcon#read 3, iclass 24, count 0 2006.259.08:05:10.62#ibcon#about to read 4, iclass 24, count 0 2006.259.08:05:10.62#ibcon#read 4, iclass 24, count 0 2006.259.08:05:10.62#ibcon#about to read 5, iclass 24, count 0 2006.259.08:05:10.62#ibcon#read 5, iclass 24, count 0 2006.259.08:05:10.62#ibcon#about to read 6, iclass 24, count 0 2006.259.08:05:10.62#ibcon#read 6, iclass 24, count 0 2006.259.08:05:10.62#ibcon#end of sib2, iclass 24, count 0 2006.259.08:05:10.62#ibcon#*mode == 0, iclass 24, count 0 2006.259.08:05:10.62#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.259.08:05:10.62#ibcon#[26=FRQ=07,832.99\r\n] 2006.259.08:05:10.62#ibcon#*before write, iclass 24, count 0 2006.259.08:05:10.62#ibcon#enter sib2, iclass 24, count 0 2006.259.08:05:10.62#ibcon#flushed, iclass 24, count 0 2006.259.08:05:10.62#ibcon#about to write, iclass 24, count 0 2006.259.08:05:10.62#ibcon#wrote, iclass 24, count 0 2006.259.08:05:10.62#ibcon#about to read 3, iclass 24, count 0 2006.259.08:05:10.66#ibcon#read 3, iclass 24, count 0 2006.259.08:05:10.66#ibcon#about to read 4, iclass 24, count 0 2006.259.08:05:10.66#ibcon#read 4, iclass 24, count 0 2006.259.08:05:10.66#ibcon#about to read 5, iclass 24, count 0 2006.259.08:05:10.66#ibcon#read 5, iclass 24, count 0 2006.259.08:05:10.66#ibcon#about to read 6, iclass 24, count 0 2006.259.08:05:10.66#ibcon#read 6, iclass 24, count 0 2006.259.08:05:10.66#ibcon#end of sib2, iclass 24, count 0 2006.259.08:05:10.66#ibcon#*after write, iclass 24, count 0 2006.259.08:05:10.66#ibcon#*before return 0, iclass 24, count 0 2006.259.08:05:10.66#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.259.08:05:10.66#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.259.08:05:10.66#ibcon#about to clear, iclass 24 cls_cnt 0 2006.259.08:05:10.66#ibcon#cleared, iclass 24 cls_cnt 0 2006.259.08:05:10.66$vc4f8/va=7,6 2006.259.08:05:10.66#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.259.08:05:10.66#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.259.08:05:10.66#ibcon#ireg 11 cls_cnt 2 2006.259.08:05:10.66#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.259.08:05:10.72#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.259.08:05:10.72#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.259.08:05:10.72#ibcon#enter wrdev, iclass 26, count 2 2006.259.08:05:10.72#ibcon#first serial, iclass 26, count 2 2006.259.08:05:10.72#ibcon#enter sib2, iclass 26, count 2 2006.259.08:05:10.72#ibcon#flushed, iclass 26, count 2 2006.259.08:05:10.72#ibcon#about to write, iclass 26, count 2 2006.259.08:05:10.72#ibcon#wrote, iclass 26, count 2 2006.259.08:05:10.72#ibcon#about to read 3, iclass 26, count 2 2006.259.08:05:10.74#ibcon#read 3, iclass 26, count 2 2006.259.08:05:10.74#ibcon#about to read 4, iclass 26, count 2 2006.259.08:05:10.74#ibcon#read 4, iclass 26, count 2 2006.259.08:05:10.74#ibcon#about to read 5, iclass 26, count 2 2006.259.08:05:10.74#ibcon#read 5, iclass 26, count 2 2006.259.08:05:10.74#ibcon#about to read 6, iclass 26, count 2 2006.259.08:05:10.74#ibcon#read 6, iclass 26, count 2 2006.259.08:05:10.74#ibcon#end of sib2, iclass 26, count 2 2006.259.08:05:10.74#ibcon#*mode == 0, iclass 26, count 2 2006.259.08:05:10.74#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.259.08:05:10.74#ibcon#[25=AT07-06\r\n] 2006.259.08:05:10.74#ibcon#*before write, iclass 26, count 2 2006.259.08:05:10.74#ibcon#enter sib2, iclass 26, count 2 2006.259.08:05:10.74#ibcon#flushed, iclass 26, count 2 2006.259.08:05:10.74#ibcon#about to write, iclass 26, count 2 2006.259.08:05:10.74#ibcon#wrote, iclass 26, count 2 2006.259.08:05:10.74#ibcon#about to read 3, iclass 26, count 2 2006.259.08:05:10.77#ibcon#read 3, iclass 26, count 2 2006.259.08:05:10.77#ibcon#about to read 4, iclass 26, count 2 2006.259.08:05:10.77#ibcon#read 4, iclass 26, count 2 2006.259.08:05:10.77#ibcon#about to read 5, iclass 26, count 2 2006.259.08:05:10.77#ibcon#read 5, iclass 26, count 2 2006.259.08:05:10.77#ibcon#about to read 6, iclass 26, count 2 2006.259.08:05:10.77#ibcon#read 6, iclass 26, count 2 2006.259.08:05:10.77#ibcon#end of sib2, iclass 26, count 2 2006.259.08:05:10.77#ibcon#*after write, iclass 26, count 2 2006.259.08:05:10.77#ibcon#*before return 0, iclass 26, count 2 2006.259.08:05:10.77#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.259.08:05:10.77#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.259.08:05:10.77#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.259.08:05:10.77#ibcon#ireg 7 cls_cnt 0 2006.259.08:05:10.77#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.259.08:05:10.89#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.259.08:05:10.89#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.259.08:05:10.89#ibcon#enter wrdev, iclass 26, count 0 2006.259.08:05:10.89#ibcon#first serial, iclass 26, count 0 2006.259.08:05:10.89#ibcon#enter sib2, iclass 26, count 0 2006.259.08:05:10.89#ibcon#flushed, iclass 26, count 0 2006.259.08:05:10.89#ibcon#about to write, iclass 26, count 0 2006.259.08:05:10.89#ibcon#wrote, iclass 26, count 0 2006.259.08:05:10.89#ibcon#about to read 3, iclass 26, count 0 2006.259.08:05:10.91#ibcon#read 3, iclass 26, count 0 2006.259.08:05:10.91#ibcon#about to read 4, iclass 26, count 0 2006.259.08:05:10.91#ibcon#read 4, iclass 26, count 0 2006.259.08:05:10.91#ibcon#about to read 5, iclass 26, count 0 2006.259.08:05:10.91#ibcon#read 5, iclass 26, count 0 2006.259.08:05:10.91#ibcon#about to read 6, iclass 26, count 0 2006.259.08:05:10.91#ibcon#read 6, iclass 26, count 0 2006.259.08:05:10.91#ibcon#end of sib2, iclass 26, count 0 2006.259.08:05:10.91#ibcon#*mode == 0, iclass 26, count 0 2006.259.08:05:10.91#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.259.08:05:10.91#ibcon#[25=USB\r\n] 2006.259.08:05:10.91#ibcon#*before write, iclass 26, count 0 2006.259.08:05:10.91#ibcon#enter sib2, iclass 26, count 0 2006.259.08:05:10.91#ibcon#flushed, iclass 26, count 0 2006.259.08:05:10.91#ibcon#about to write, iclass 26, count 0 2006.259.08:05:10.91#ibcon#wrote, iclass 26, count 0 2006.259.08:05:10.91#ibcon#about to read 3, iclass 26, count 0 2006.259.08:05:10.94#ibcon#read 3, iclass 26, count 0 2006.259.08:05:10.94#ibcon#about to read 4, iclass 26, count 0 2006.259.08:05:10.94#ibcon#read 4, iclass 26, count 0 2006.259.08:05:10.94#ibcon#about to read 5, iclass 26, count 0 2006.259.08:05:10.94#ibcon#read 5, iclass 26, count 0 2006.259.08:05:10.94#ibcon#about to read 6, iclass 26, count 0 2006.259.08:05:10.94#ibcon#read 6, iclass 26, count 0 2006.259.08:05:10.94#ibcon#end of sib2, iclass 26, count 0 2006.259.08:05:10.94#ibcon#*after write, iclass 26, count 0 2006.259.08:05:10.94#ibcon#*before return 0, iclass 26, count 0 2006.259.08:05:10.94#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.259.08:05:10.94#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.259.08:05:10.94#ibcon#about to clear, iclass 26 cls_cnt 0 2006.259.08:05:10.94#ibcon#cleared, iclass 26 cls_cnt 0 2006.259.08:05:10.94$vc4f8/valo=8,852.99 2006.259.08:05:10.94#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.259.08:05:10.94#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.259.08:05:10.94#ibcon#ireg 17 cls_cnt 0 2006.259.08:05:10.94#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.259.08:05:10.94#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.259.08:05:10.94#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.259.08:05:10.94#ibcon#enter wrdev, iclass 28, count 0 2006.259.08:05:10.94#ibcon#first serial, iclass 28, count 0 2006.259.08:05:10.94#ibcon#enter sib2, iclass 28, count 0 2006.259.08:05:10.94#ibcon#flushed, iclass 28, count 0 2006.259.08:05:10.94#ibcon#about to write, iclass 28, count 0 2006.259.08:05:10.94#ibcon#wrote, iclass 28, count 0 2006.259.08:05:10.94#ibcon#about to read 3, iclass 28, count 0 2006.259.08:05:10.96#ibcon#read 3, iclass 28, count 0 2006.259.08:05:10.96#ibcon#about to read 4, iclass 28, count 0 2006.259.08:05:10.96#ibcon#read 4, iclass 28, count 0 2006.259.08:05:10.96#ibcon#about to read 5, iclass 28, count 0 2006.259.08:05:10.96#ibcon#read 5, iclass 28, count 0 2006.259.08:05:10.96#ibcon#about to read 6, iclass 28, count 0 2006.259.08:05:10.96#ibcon#read 6, iclass 28, count 0 2006.259.08:05:10.96#ibcon#end of sib2, iclass 28, count 0 2006.259.08:05:10.96#ibcon#*mode == 0, iclass 28, count 0 2006.259.08:05:10.96#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.259.08:05:10.96#ibcon#[26=FRQ=08,852.99\r\n] 2006.259.08:05:10.96#ibcon#*before write, iclass 28, count 0 2006.259.08:05:10.96#ibcon#enter sib2, iclass 28, count 0 2006.259.08:05:10.96#ibcon#flushed, iclass 28, count 0 2006.259.08:05:10.96#ibcon#about to write, iclass 28, count 0 2006.259.08:05:10.96#ibcon#wrote, iclass 28, count 0 2006.259.08:05:10.96#ibcon#about to read 3, iclass 28, count 0 2006.259.08:05:11.00#ibcon#read 3, iclass 28, count 0 2006.259.08:05:11.00#ibcon#about to read 4, iclass 28, count 0 2006.259.08:05:11.00#ibcon#read 4, iclass 28, count 0 2006.259.08:05:11.00#ibcon#about to read 5, iclass 28, count 0 2006.259.08:05:11.00#ibcon#read 5, iclass 28, count 0 2006.259.08:05:11.00#ibcon#about to read 6, iclass 28, count 0 2006.259.08:05:11.00#ibcon#read 6, iclass 28, count 0 2006.259.08:05:11.00#ibcon#end of sib2, iclass 28, count 0 2006.259.08:05:11.00#ibcon#*after write, iclass 28, count 0 2006.259.08:05:11.00#ibcon#*before return 0, iclass 28, count 0 2006.259.08:05:11.00#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.259.08:05:11.00#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.259.08:05:11.00#ibcon#about to clear, iclass 28 cls_cnt 0 2006.259.08:05:11.00#ibcon#cleared, iclass 28 cls_cnt 0 2006.259.08:05:11.00$vc4f8/va=8,6 2006.259.08:05:11.00#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.259.08:05:11.00#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.259.08:05:11.00#ibcon#ireg 11 cls_cnt 2 2006.259.08:05:11.00#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.259.08:05:11.06#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.259.08:05:11.06#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.259.08:05:11.06#ibcon#enter wrdev, iclass 30, count 2 2006.259.08:05:11.06#ibcon#first serial, iclass 30, count 2 2006.259.08:05:11.06#ibcon#enter sib2, iclass 30, count 2 2006.259.08:05:11.06#ibcon#flushed, iclass 30, count 2 2006.259.08:05:11.06#ibcon#about to write, iclass 30, count 2 2006.259.08:05:11.06#ibcon#wrote, iclass 30, count 2 2006.259.08:05:11.06#ibcon#about to read 3, iclass 30, count 2 2006.259.08:05:11.08#ibcon#read 3, iclass 30, count 2 2006.259.08:05:11.08#ibcon#about to read 4, iclass 30, count 2 2006.259.08:05:11.08#ibcon#read 4, iclass 30, count 2 2006.259.08:05:11.08#ibcon#about to read 5, iclass 30, count 2 2006.259.08:05:11.08#ibcon#read 5, iclass 30, count 2 2006.259.08:05:11.08#ibcon#about to read 6, iclass 30, count 2 2006.259.08:05:11.08#ibcon#read 6, iclass 30, count 2 2006.259.08:05:11.08#ibcon#end of sib2, iclass 30, count 2 2006.259.08:05:11.08#ibcon#*mode == 0, iclass 30, count 2 2006.259.08:05:11.08#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.259.08:05:11.08#ibcon#[25=AT08-06\r\n] 2006.259.08:05:11.08#ibcon#*before write, iclass 30, count 2 2006.259.08:05:11.08#ibcon#enter sib2, iclass 30, count 2 2006.259.08:05:11.08#ibcon#flushed, iclass 30, count 2 2006.259.08:05:11.08#ibcon#about to write, iclass 30, count 2 2006.259.08:05:11.08#ibcon#wrote, iclass 30, count 2 2006.259.08:05:11.08#ibcon#about to read 3, iclass 30, count 2 2006.259.08:05:11.11#ibcon#read 3, iclass 30, count 2 2006.259.08:05:11.11#ibcon#about to read 4, iclass 30, count 2 2006.259.08:05:11.11#ibcon#read 4, iclass 30, count 2 2006.259.08:05:11.11#ibcon#about to read 5, iclass 30, count 2 2006.259.08:05:11.11#ibcon#read 5, iclass 30, count 2 2006.259.08:05:11.11#ibcon#about to read 6, iclass 30, count 2 2006.259.08:05:11.11#ibcon#read 6, iclass 30, count 2 2006.259.08:05:11.11#ibcon#end of sib2, iclass 30, count 2 2006.259.08:05:11.11#ibcon#*after write, iclass 30, count 2 2006.259.08:05:11.11#ibcon#*before return 0, iclass 30, count 2 2006.259.08:05:11.11#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.259.08:05:11.11#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.259.08:05:11.11#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.259.08:05:11.11#ibcon#ireg 7 cls_cnt 0 2006.259.08:05:11.11#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.259.08:05:11.23#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.259.08:05:11.23#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.259.08:05:11.23#ibcon#enter wrdev, iclass 30, count 0 2006.259.08:05:11.23#ibcon#first serial, iclass 30, count 0 2006.259.08:05:11.23#ibcon#enter sib2, iclass 30, count 0 2006.259.08:05:11.23#ibcon#flushed, iclass 30, count 0 2006.259.08:05:11.23#ibcon#about to write, iclass 30, count 0 2006.259.08:05:11.23#ibcon#wrote, iclass 30, count 0 2006.259.08:05:11.23#ibcon#about to read 3, iclass 30, count 0 2006.259.08:05:11.25#ibcon#read 3, iclass 30, count 0 2006.259.08:05:11.25#ibcon#about to read 4, iclass 30, count 0 2006.259.08:05:11.25#ibcon#read 4, iclass 30, count 0 2006.259.08:05:11.25#ibcon#about to read 5, iclass 30, count 0 2006.259.08:05:11.25#ibcon#read 5, iclass 30, count 0 2006.259.08:05:11.25#ibcon#about to read 6, iclass 30, count 0 2006.259.08:05:11.25#ibcon#read 6, iclass 30, count 0 2006.259.08:05:11.25#ibcon#end of sib2, iclass 30, count 0 2006.259.08:05:11.25#ibcon#*mode == 0, iclass 30, count 0 2006.259.08:05:11.25#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.259.08:05:11.25#ibcon#[25=USB\r\n] 2006.259.08:05:11.25#ibcon#*before write, iclass 30, count 0 2006.259.08:05:11.25#ibcon#enter sib2, iclass 30, count 0 2006.259.08:05:11.25#ibcon#flushed, iclass 30, count 0 2006.259.08:05:11.25#ibcon#about to write, iclass 30, count 0 2006.259.08:05:11.25#ibcon#wrote, iclass 30, count 0 2006.259.08:05:11.25#ibcon#about to read 3, iclass 30, count 0 2006.259.08:05:11.28#ibcon#read 3, iclass 30, count 0 2006.259.08:05:11.28#ibcon#about to read 4, iclass 30, count 0 2006.259.08:05:11.28#ibcon#read 4, iclass 30, count 0 2006.259.08:05:11.28#ibcon#about to read 5, iclass 30, count 0 2006.259.08:05:11.28#ibcon#read 5, iclass 30, count 0 2006.259.08:05:11.28#ibcon#about to read 6, iclass 30, count 0 2006.259.08:05:11.28#ibcon#read 6, iclass 30, count 0 2006.259.08:05:11.28#ibcon#end of sib2, iclass 30, count 0 2006.259.08:05:11.28#ibcon#*after write, iclass 30, count 0 2006.259.08:05:11.28#ibcon#*before return 0, iclass 30, count 0 2006.259.08:05:11.28#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.259.08:05:11.28#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.259.08:05:11.28#ibcon#about to clear, iclass 30 cls_cnt 0 2006.259.08:05:11.28#ibcon#cleared, iclass 30 cls_cnt 0 2006.259.08:05:11.28$vc4f8/vblo=1,632.99 2006.259.08:05:11.28#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.259.08:05:11.28#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.259.08:05:11.28#ibcon#ireg 17 cls_cnt 0 2006.259.08:05:11.28#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.259.08:05:11.28#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.259.08:05:11.28#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.259.08:05:11.28#ibcon#enter wrdev, iclass 32, count 0 2006.259.08:05:11.28#ibcon#first serial, iclass 32, count 0 2006.259.08:05:11.28#ibcon#enter sib2, iclass 32, count 0 2006.259.08:05:11.28#ibcon#flushed, iclass 32, count 0 2006.259.08:05:11.28#ibcon#about to write, iclass 32, count 0 2006.259.08:05:11.28#ibcon#wrote, iclass 32, count 0 2006.259.08:05:11.28#ibcon#about to read 3, iclass 32, count 0 2006.259.08:05:11.30#ibcon#read 3, iclass 32, count 0 2006.259.08:05:11.30#ibcon#about to read 4, iclass 32, count 0 2006.259.08:05:11.30#ibcon#read 4, iclass 32, count 0 2006.259.08:05:11.30#ibcon#about to read 5, iclass 32, count 0 2006.259.08:05:11.30#ibcon#read 5, iclass 32, count 0 2006.259.08:05:11.30#ibcon#about to read 6, iclass 32, count 0 2006.259.08:05:11.30#ibcon#read 6, iclass 32, count 0 2006.259.08:05:11.30#ibcon#end of sib2, iclass 32, count 0 2006.259.08:05:11.30#ibcon#*mode == 0, iclass 32, count 0 2006.259.08:05:11.30#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.259.08:05:11.30#ibcon#[28=FRQ=01,632.99\r\n] 2006.259.08:05:11.30#ibcon#*before write, iclass 32, count 0 2006.259.08:05:11.30#ibcon#enter sib2, iclass 32, count 0 2006.259.08:05:11.30#ibcon#flushed, iclass 32, count 0 2006.259.08:05:11.30#ibcon#about to write, iclass 32, count 0 2006.259.08:05:11.30#ibcon#wrote, iclass 32, count 0 2006.259.08:05:11.30#ibcon#about to read 3, iclass 32, count 0 2006.259.08:05:11.34#ibcon#read 3, iclass 32, count 0 2006.259.08:05:11.34#ibcon#about to read 4, iclass 32, count 0 2006.259.08:05:11.34#ibcon#read 4, iclass 32, count 0 2006.259.08:05:11.34#ibcon#about to read 5, iclass 32, count 0 2006.259.08:05:11.34#ibcon#read 5, iclass 32, count 0 2006.259.08:05:11.34#ibcon#about to read 6, iclass 32, count 0 2006.259.08:05:11.34#ibcon#read 6, iclass 32, count 0 2006.259.08:05:11.34#ibcon#end of sib2, iclass 32, count 0 2006.259.08:05:11.34#ibcon#*after write, iclass 32, count 0 2006.259.08:05:11.34#ibcon#*before return 0, iclass 32, count 0 2006.259.08:05:11.34#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.259.08:05:11.34#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.259.08:05:11.34#ibcon#about to clear, iclass 32 cls_cnt 0 2006.259.08:05:11.34#ibcon#cleared, iclass 32 cls_cnt 0 2006.259.08:05:11.34$vc4f8/vb=1,4 2006.259.08:05:11.34#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.259.08:05:11.34#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.259.08:05:11.34#ibcon#ireg 11 cls_cnt 2 2006.259.08:05:11.34#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.259.08:05:11.34#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.259.08:05:11.34#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.259.08:05:11.34#ibcon#enter wrdev, iclass 34, count 2 2006.259.08:05:11.34#ibcon#first serial, iclass 34, count 2 2006.259.08:05:11.34#ibcon#enter sib2, iclass 34, count 2 2006.259.08:05:11.34#ibcon#flushed, iclass 34, count 2 2006.259.08:05:11.34#ibcon#about to write, iclass 34, count 2 2006.259.08:05:11.34#ibcon#wrote, iclass 34, count 2 2006.259.08:05:11.34#ibcon#about to read 3, iclass 34, count 2 2006.259.08:05:11.36#ibcon#read 3, iclass 34, count 2 2006.259.08:05:11.36#ibcon#about to read 4, iclass 34, count 2 2006.259.08:05:11.36#ibcon#read 4, iclass 34, count 2 2006.259.08:05:11.36#ibcon#about to read 5, iclass 34, count 2 2006.259.08:05:11.36#ibcon#read 5, iclass 34, count 2 2006.259.08:05:11.36#ibcon#about to read 6, iclass 34, count 2 2006.259.08:05:11.36#ibcon#read 6, iclass 34, count 2 2006.259.08:05:11.36#ibcon#end of sib2, iclass 34, count 2 2006.259.08:05:11.36#ibcon#*mode == 0, iclass 34, count 2 2006.259.08:05:11.36#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.259.08:05:11.36#ibcon#[27=AT01-04\r\n] 2006.259.08:05:11.36#ibcon#*before write, iclass 34, count 2 2006.259.08:05:11.36#ibcon#enter sib2, iclass 34, count 2 2006.259.08:05:11.36#ibcon#flushed, iclass 34, count 2 2006.259.08:05:11.36#ibcon#about to write, iclass 34, count 2 2006.259.08:05:11.36#ibcon#wrote, iclass 34, count 2 2006.259.08:05:11.36#ibcon#about to read 3, iclass 34, count 2 2006.259.08:05:11.39#ibcon#read 3, iclass 34, count 2 2006.259.08:05:11.39#ibcon#about to read 4, iclass 34, count 2 2006.259.08:05:11.39#ibcon#read 4, iclass 34, count 2 2006.259.08:05:11.39#ibcon#about to read 5, iclass 34, count 2 2006.259.08:05:11.39#ibcon#read 5, iclass 34, count 2 2006.259.08:05:11.39#ibcon#about to read 6, iclass 34, count 2 2006.259.08:05:11.39#ibcon#read 6, iclass 34, count 2 2006.259.08:05:11.39#ibcon#end of sib2, iclass 34, count 2 2006.259.08:05:11.39#ibcon#*after write, iclass 34, count 2 2006.259.08:05:11.39#ibcon#*before return 0, iclass 34, count 2 2006.259.08:05:11.39#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.259.08:05:11.39#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.259.08:05:11.39#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.259.08:05:11.39#ibcon#ireg 7 cls_cnt 0 2006.259.08:05:11.39#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.259.08:05:11.51#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.259.08:05:11.51#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.259.08:05:11.51#ibcon#enter wrdev, iclass 34, count 0 2006.259.08:05:11.51#ibcon#first serial, iclass 34, count 0 2006.259.08:05:11.51#ibcon#enter sib2, iclass 34, count 0 2006.259.08:05:11.51#ibcon#flushed, iclass 34, count 0 2006.259.08:05:11.51#ibcon#about to write, iclass 34, count 0 2006.259.08:05:11.51#ibcon#wrote, iclass 34, count 0 2006.259.08:05:11.51#ibcon#about to read 3, iclass 34, count 0 2006.259.08:05:11.53#ibcon#read 3, iclass 34, count 0 2006.259.08:05:11.53#ibcon#about to read 4, iclass 34, count 0 2006.259.08:05:11.53#ibcon#read 4, iclass 34, count 0 2006.259.08:05:11.53#ibcon#about to read 5, iclass 34, count 0 2006.259.08:05:11.53#ibcon#read 5, iclass 34, count 0 2006.259.08:05:11.53#ibcon#about to read 6, iclass 34, count 0 2006.259.08:05:11.53#ibcon#read 6, iclass 34, count 0 2006.259.08:05:11.53#ibcon#end of sib2, iclass 34, count 0 2006.259.08:05:11.53#ibcon#*mode == 0, iclass 34, count 0 2006.259.08:05:11.53#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.259.08:05:11.53#ibcon#[27=USB\r\n] 2006.259.08:05:11.53#ibcon#*before write, iclass 34, count 0 2006.259.08:05:11.53#ibcon#enter sib2, iclass 34, count 0 2006.259.08:05:11.53#ibcon#flushed, iclass 34, count 0 2006.259.08:05:11.53#ibcon#about to write, iclass 34, count 0 2006.259.08:05:11.53#ibcon#wrote, iclass 34, count 0 2006.259.08:05:11.53#ibcon#about to read 3, iclass 34, count 0 2006.259.08:05:11.56#ibcon#read 3, iclass 34, count 0 2006.259.08:05:11.56#ibcon#about to read 4, iclass 34, count 0 2006.259.08:05:11.56#ibcon#read 4, iclass 34, count 0 2006.259.08:05:11.56#ibcon#about to read 5, iclass 34, count 0 2006.259.08:05:11.56#ibcon#read 5, iclass 34, count 0 2006.259.08:05:11.56#ibcon#about to read 6, iclass 34, count 0 2006.259.08:05:11.56#ibcon#read 6, iclass 34, count 0 2006.259.08:05:11.56#ibcon#end of sib2, iclass 34, count 0 2006.259.08:05:11.56#ibcon#*after write, iclass 34, count 0 2006.259.08:05:11.56#ibcon#*before return 0, iclass 34, count 0 2006.259.08:05:11.56#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.259.08:05:11.56#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.259.08:05:11.56#ibcon#about to clear, iclass 34 cls_cnt 0 2006.259.08:05:11.56#ibcon#cleared, iclass 34 cls_cnt 0 2006.259.08:05:11.56$vc4f8/vblo=2,640.99 2006.259.08:05:11.56#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.259.08:05:11.56#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.259.08:05:11.56#ibcon#ireg 17 cls_cnt 0 2006.259.08:05:11.56#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.259.08:05:11.56#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.259.08:05:11.56#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.259.08:05:11.56#ibcon#enter wrdev, iclass 36, count 0 2006.259.08:05:11.56#ibcon#first serial, iclass 36, count 0 2006.259.08:05:11.56#ibcon#enter sib2, iclass 36, count 0 2006.259.08:05:11.56#ibcon#flushed, iclass 36, count 0 2006.259.08:05:11.56#ibcon#about to write, iclass 36, count 0 2006.259.08:05:11.56#ibcon#wrote, iclass 36, count 0 2006.259.08:05:11.56#ibcon#about to read 3, iclass 36, count 0 2006.259.08:05:11.58#ibcon#read 3, iclass 36, count 0 2006.259.08:05:11.58#ibcon#about to read 4, iclass 36, count 0 2006.259.08:05:11.58#ibcon#read 4, iclass 36, count 0 2006.259.08:05:11.58#ibcon#about to read 5, iclass 36, count 0 2006.259.08:05:11.58#ibcon#read 5, iclass 36, count 0 2006.259.08:05:11.58#ibcon#about to read 6, iclass 36, count 0 2006.259.08:05:11.58#ibcon#read 6, iclass 36, count 0 2006.259.08:05:11.58#ibcon#end of sib2, iclass 36, count 0 2006.259.08:05:11.58#ibcon#*mode == 0, iclass 36, count 0 2006.259.08:05:11.58#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.259.08:05:11.58#ibcon#[28=FRQ=02,640.99\r\n] 2006.259.08:05:11.58#ibcon#*before write, iclass 36, count 0 2006.259.08:05:11.58#ibcon#enter sib2, iclass 36, count 0 2006.259.08:05:11.58#ibcon#flushed, iclass 36, count 0 2006.259.08:05:11.58#ibcon#about to write, iclass 36, count 0 2006.259.08:05:11.58#ibcon#wrote, iclass 36, count 0 2006.259.08:05:11.58#ibcon#about to read 3, iclass 36, count 0 2006.259.08:05:11.62#ibcon#read 3, iclass 36, count 0 2006.259.08:05:11.62#ibcon#about to read 4, iclass 36, count 0 2006.259.08:05:11.62#ibcon#read 4, iclass 36, count 0 2006.259.08:05:11.62#ibcon#about to read 5, iclass 36, count 0 2006.259.08:05:11.62#ibcon#read 5, iclass 36, count 0 2006.259.08:05:11.62#ibcon#about to read 6, iclass 36, count 0 2006.259.08:05:11.62#ibcon#read 6, iclass 36, count 0 2006.259.08:05:11.62#ibcon#end of sib2, iclass 36, count 0 2006.259.08:05:11.62#ibcon#*after write, iclass 36, count 0 2006.259.08:05:11.62#ibcon#*before return 0, iclass 36, count 0 2006.259.08:05:11.62#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.259.08:05:11.62#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.259.08:05:11.62#ibcon#about to clear, iclass 36 cls_cnt 0 2006.259.08:05:11.62#ibcon#cleared, iclass 36 cls_cnt 0 2006.259.08:05:11.62$vc4f8/vb=2,5 2006.259.08:05:11.62#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.259.08:05:11.62#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.259.08:05:11.62#ibcon#ireg 11 cls_cnt 2 2006.259.08:05:11.62#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.259.08:05:11.68#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.259.08:05:11.68#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.259.08:05:11.68#ibcon#enter wrdev, iclass 38, count 2 2006.259.08:05:11.68#ibcon#first serial, iclass 38, count 2 2006.259.08:05:11.68#ibcon#enter sib2, iclass 38, count 2 2006.259.08:05:11.68#ibcon#flushed, iclass 38, count 2 2006.259.08:05:11.68#ibcon#about to write, iclass 38, count 2 2006.259.08:05:11.68#ibcon#wrote, iclass 38, count 2 2006.259.08:05:11.68#ibcon#about to read 3, iclass 38, count 2 2006.259.08:05:11.70#ibcon#read 3, iclass 38, count 2 2006.259.08:05:11.70#ibcon#about to read 4, iclass 38, count 2 2006.259.08:05:11.70#ibcon#read 4, iclass 38, count 2 2006.259.08:05:11.70#ibcon#about to read 5, iclass 38, count 2 2006.259.08:05:11.70#ibcon#read 5, iclass 38, count 2 2006.259.08:05:11.70#ibcon#about to read 6, iclass 38, count 2 2006.259.08:05:11.70#ibcon#read 6, iclass 38, count 2 2006.259.08:05:11.70#ibcon#end of sib2, iclass 38, count 2 2006.259.08:05:11.70#ibcon#*mode == 0, iclass 38, count 2 2006.259.08:05:11.70#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.259.08:05:11.70#ibcon#[27=AT02-05\r\n] 2006.259.08:05:11.70#ibcon#*before write, iclass 38, count 2 2006.259.08:05:11.70#ibcon#enter sib2, iclass 38, count 2 2006.259.08:05:11.70#ibcon#flushed, iclass 38, count 2 2006.259.08:05:11.70#ibcon#about to write, iclass 38, count 2 2006.259.08:05:11.70#ibcon#wrote, iclass 38, count 2 2006.259.08:05:11.70#ibcon#about to read 3, iclass 38, count 2 2006.259.08:05:11.73#ibcon#read 3, iclass 38, count 2 2006.259.08:05:11.73#ibcon#about to read 4, iclass 38, count 2 2006.259.08:05:11.73#ibcon#read 4, iclass 38, count 2 2006.259.08:05:11.73#ibcon#about to read 5, iclass 38, count 2 2006.259.08:05:11.73#ibcon#read 5, iclass 38, count 2 2006.259.08:05:11.73#ibcon#about to read 6, iclass 38, count 2 2006.259.08:05:11.73#ibcon#read 6, iclass 38, count 2 2006.259.08:05:11.73#ibcon#end of sib2, iclass 38, count 2 2006.259.08:05:11.73#ibcon#*after write, iclass 38, count 2 2006.259.08:05:11.73#ibcon#*before return 0, iclass 38, count 2 2006.259.08:05:11.73#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.259.08:05:11.73#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.259.08:05:11.73#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.259.08:05:11.73#ibcon#ireg 7 cls_cnt 0 2006.259.08:05:11.73#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.259.08:05:11.85#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.259.08:05:11.85#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.259.08:05:11.85#ibcon#enter wrdev, iclass 38, count 0 2006.259.08:05:11.85#ibcon#first serial, iclass 38, count 0 2006.259.08:05:11.85#ibcon#enter sib2, iclass 38, count 0 2006.259.08:05:11.85#ibcon#flushed, iclass 38, count 0 2006.259.08:05:11.85#ibcon#about to write, iclass 38, count 0 2006.259.08:05:11.85#ibcon#wrote, iclass 38, count 0 2006.259.08:05:11.85#ibcon#about to read 3, iclass 38, count 0 2006.259.08:05:11.87#ibcon#read 3, iclass 38, count 0 2006.259.08:05:11.87#ibcon#about to read 4, iclass 38, count 0 2006.259.08:05:11.87#ibcon#read 4, iclass 38, count 0 2006.259.08:05:11.87#ibcon#about to read 5, iclass 38, count 0 2006.259.08:05:11.87#ibcon#read 5, iclass 38, count 0 2006.259.08:05:11.87#ibcon#about to read 6, iclass 38, count 0 2006.259.08:05:11.87#ibcon#read 6, iclass 38, count 0 2006.259.08:05:11.87#ibcon#end of sib2, iclass 38, count 0 2006.259.08:05:11.87#ibcon#*mode == 0, iclass 38, count 0 2006.259.08:05:11.87#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.259.08:05:11.87#ibcon#[27=USB\r\n] 2006.259.08:05:11.87#ibcon#*before write, iclass 38, count 0 2006.259.08:05:11.87#ibcon#enter sib2, iclass 38, count 0 2006.259.08:05:11.87#ibcon#flushed, iclass 38, count 0 2006.259.08:05:11.87#ibcon#about to write, iclass 38, count 0 2006.259.08:05:11.87#ibcon#wrote, iclass 38, count 0 2006.259.08:05:11.87#ibcon#about to read 3, iclass 38, count 0 2006.259.08:05:11.90#ibcon#read 3, iclass 38, count 0 2006.259.08:05:11.90#ibcon#about to read 4, iclass 38, count 0 2006.259.08:05:11.90#ibcon#read 4, iclass 38, count 0 2006.259.08:05:11.90#ibcon#about to read 5, iclass 38, count 0 2006.259.08:05:11.90#ibcon#read 5, iclass 38, count 0 2006.259.08:05:11.90#ibcon#about to read 6, iclass 38, count 0 2006.259.08:05:11.90#ibcon#read 6, iclass 38, count 0 2006.259.08:05:11.90#ibcon#end of sib2, iclass 38, count 0 2006.259.08:05:11.90#ibcon#*after write, iclass 38, count 0 2006.259.08:05:11.90#ibcon#*before return 0, iclass 38, count 0 2006.259.08:05:11.90#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.259.08:05:11.90#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.259.08:05:11.90#ibcon#about to clear, iclass 38 cls_cnt 0 2006.259.08:05:11.90#ibcon#cleared, iclass 38 cls_cnt 0 2006.259.08:05:11.90$vc4f8/vblo=3,656.99 2006.259.08:05:11.90#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.259.08:05:11.90#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.259.08:05:11.90#ibcon#ireg 17 cls_cnt 0 2006.259.08:05:11.90#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.259.08:05:11.90#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.259.08:05:11.90#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.259.08:05:11.90#ibcon#enter wrdev, iclass 40, count 0 2006.259.08:05:11.90#ibcon#first serial, iclass 40, count 0 2006.259.08:05:11.90#ibcon#enter sib2, iclass 40, count 0 2006.259.08:05:11.90#ibcon#flushed, iclass 40, count 0 2006.259.08:05:11.90#ibcon#about to write, iclass 40, count 0 2006.259.08:05:11.90#ibcon#wrote, iclass 40, count 0 2006.259.08:05:11.90#ibcon#about to read 3, iclass 40, count 0 2006.259.08:05:11.93#ibcon#read 3, iclass 40, count 0 2006.259.08:05:11.93#ibcon#about to read 4, iclass 40, count 0 2006.259.08:05:11.93#ibcon#read 4, iclass 40, count 0 2006.259.08:05:11.93#ibcon#about to read 5, iclass 40, count 0 2006.259.08:05:11.93#ibcon#read 5, iclass 40, count 0 2006.259.08:05:11.93#ibcon#about to read 6, iclass 40, count 0 2006.259.08:05:11.93#ibcon#read 6, iclass 40, count 0 2006.259.08:05:11.93#ibcon#end of sib2, iclass 40, count 0 2006.259.08:05:11.93#ibcon#*mode == 0, iclass 40, count 0 2006.259.08:05:11.93#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.259.08:05:11.93#ibcon#[28=FRQ=03,656.99\r\n] 2006.259.08:05:11.93#ibcon#*before write, iclass 40, count 0 2006.259.08:05:11.93#ibcon#enter sib2, iclass 40, count 0 2006.259.08:05:11.93#ibcon#flushed, iclass 40, count 0 2006.259.08:05:11.93#ibcon#about to write, iclass 40, count 0 2006.259.08:05:11.93#ibcon#wrote, iclass 40, count 0 2006.259.08:05:11.93#ibcon#about to read 3, iclass 40, count 0 2006.259.08:05:11.97#ibcon#read 3, iclass 40, count 0 2006.259.08:05:11.97#ibcon#about to read 4, iclass 40, count 0 2006.259.08:05:11.97#ibcon#read 4, iclass 40, count 0 2006.259.08:05:11.97#ibcon#about to read 5, iclass 40, count 0 2006.259.08:05:11.97#ibcon#read 5, iclass 40, count 0 2006.259.08:05:11.97#ibcon#about to read 6, iclass 40, count 0 2006.259.08:05:11.97#ibcon#read 6, iclass 40, count 0 2006.259.08:05:11.97#ibcon#end of sib2, iclass 40, count 0 2006.259.08:05:11.97#ibcon#*after write, iclass 40, count 0 2006.259.08:05:11.97#ibcon#*before return 0, iclass 40, count 0 2006.259.08:05:11.97#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.259.08:05:11.97#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.259.08:05:11.97#ibcon#about to clear, iclass 40 cls_cnt 0 2006.259.08:05:11.97#ibcon#cleared, iclass 40 cls_cnt 0 2006.259.08:05:11.97$vc4f8/vb=3,4 2006.259.08:05:11.97#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.259.08:05:11.97#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.259.08:05:11.97#ibcon#ireg 11 cls_cnt 2 2006.259.08:05:11.97#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.259.08:05:12.02#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.259.08:05:12.02#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.259.08:05:12.02#ibcon#enter wrdev, iclass 4, count 2 2006.259.08:05:12.02#ibcon#first serial, iclass 4, count 2 2006.259.08:05:12.02#ibcon#enter sib2, iclass 4, count 2 2006.259.08:05:12.02#ibcon#flushed, iclass 4, count 2 2006.259.08:05:12.02#ibcon#about to write, iclass 4, count 2 2006.259.08:05:12.02#ibcon#wrote, iclass 4, count 2 2006.259.08:05:12.02#ibcon#about to read 3, iclass 4, count 2 2006.259.08:05:12.04#ibcon#read 3, iclass 4, count 2 2006.259.08:05:12.04#ibcon#about to read 4, iclass 4, count 2 2006.259.08:05:12.04#ibcon#read 4, iclass 4, count 2 2006.259.08:05:12.04#ibcon#about to read 5, iclass 4, count 2 2006.259.08:05:12.04#ibcon#read 5, iclass 4, count 2 2006.259.08:05:12.04#ibcon#about to read 6, iclass 4, count 2 2006.259.08:05:12.04#ibcon#read 6, iclass 4, count 2 2006.259.08:05:12.04#ibcon#end of sib2, iclass 4, count 2 2006.259.08:05:12.04#ibcon#*mode == 0, iclass 4, count 2 2006.259.08:05:12.04#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.259.08:05:12.04#ibcon#[27=AT03-04\r\n] 2006.259.08:05:12.04#ibcon#*before write, iclass 4, count 2 2006.259.08:05:12.04#ibcon#enter sib2, iclass 4, count 2 2006.259.08:05:12.04#ibcon#flushed, iclass 4, count 2 2006.259.08:05:12.04#ibcon#about to write, iclass 4, count 2 2006.259.08:05:12.04#ibcon#wrote, iclass 4, count 2 2006.259.08:05:12.04#ibcon#about to read 3, iclass 4, count 2 2006.259.08:05:12.07#ibcon#read 3, iclass 4, count 2 2006.259.08:05:12.07#ibcon#about to read 4, iclass 4, count 2 2006.259.08:05:12.07#ibcon#read 4, iclass 4, count 2 2006.259.08:05:12.07#ibcon#about to read 5, iclass 4, count 2 2006.259.08:05:12.07#ibcon#read 5, iclass 4, count 2 2006.259.08:05:12.07#ibcon#about to read 6, iclass 4, count 2 2006.259.08:05:12.07#ibcon#read 6, iclass 4, count 2 2006.259.08:05:12.07#ibcon#end of sib2, iclass 4, count 2 2006.259.08:05:12.07#ibcon#*after write, iclass 4, count 2 2006.259.08:05:12.07#ibcon#*before return 0, iclass 4, count 2 2006.259.08:05:12.07#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.259.08:05:12.07#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.259.08:05:12.07#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.259.08:05:12.07#ibcon#ireg 7 cls_cnt 0 2006.259.08:05:12.07#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.259.08:05:12.19#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.259.08:05:12.19#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.259.08:05:12.19#ibcon#enter wrdev, iclass 4, count 0 2006.259.08:05:12.19#ibcon#first serial, iclass 4, count 0 2006.259.08:05:12.19#ibcon#enter sib2, iclass 4, count 0 2006.259.08:05:12.19#ibcon#flushed, iclass 4, count 0 2006.259.08:05:12.19#ibcon#about to write, iclass 4, count 0 2006.259.08:05:12.19#ibcon#wrote, iclass 4, count 0 2006.259.08:05:12.19#ibcon#about to read 3, iclass 4, count 0 2006.259.08:05:12.21#ibcon#read 3, iclass 4, count 0 2006.259.08:05:12.21#ibcon#about to read 4, iclass 4, count 0 2006.259.08:05:12.21#ibcon#read 4, iclass 4, count 0 2006.259.08:05:12.21#ibcon#about to read 5, iclass 4, count 0 2006.259.08:05:12.21#ibcon#read 5, iclass 4, count 0 2006.259.08:05:12.21#ibcon#about to read 6, iclass 4, count 0 2006.259.08:05:12.21#ibcon#read 6, iclass 4, count 0 2006.259.08:05:12.21#ibcon#end of sib2, iclass 4, count 0 2006.259.08:05:12.21#ibcon#*mode == 0, iclass 4, count 0 2006.259.08:05:12.21#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.259.08:05:12.21#ibcon#[27=USB\r\n] 2006.259.08:05:12.21#ibcon#*before write, iclass 4, count 0 2006.259.08:05:12.21#ibcon#enter sib2, iclass 4, count 0 2006.259.08:05:12.21#ibcon#flushed, iclass 4, count 0 2006.259.08:05:12.21#ibcon#about to write, iclass 4, count 0 2006.259.08:05:12.21#ibcon#wrote, iclass 4, count 0 2006.259.08:05:12.21#ibcon#about to read 3, iclass 4, count 0 2006.259.08:05:12.24#ibcon#read 3, iclass 4, count 0 2006.259.08:05:12.24#ibcon#about to read 4, iclass 4, count 0 2006.259.08:05:12.24#ibcon#read 4, iclass 4, count 0 2006.259.08:05:12.24#ibcon#about to read 5, iclass 4, count 0 2006.259.08:05:12.24#ibcon#read 5, iclass 4, count 0 2006.259.08:05:12.24#ibcon#about to read 6, iclass 4, count 0 2006.259.08:05:12.24#ibcon#read 6, iclass 4, count 0 2006.259.08:05:12.24#ibcon#end of sib2, iclass 4, count 0 2006.259.08:05:12.24#ibcon#*after write, iclass 4, count 0 2006.259.08:05:12.24#ibcon#*before return 0, iclass 4, count 0 2006.259.08:05:12.24#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.259.08:05:12.24#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.259.08:05:12.24#ibcon#about to clear, iclass 4 cls_cnt 0 2006.259.08:05:12.24#ibcon#cleared, iclass 4 cls_cnt 0 2006.259.08:05:12.24$vc4f8/vblo=4,712.99 2006.259.08:05:12.24#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.259.08:05:12.24#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.259.08:05:12.24#ibcon#ireg 17 cls_cnt 0 2006.259.08:05:12.24#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.259.08:05:12.24#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.259.08:05:12.24#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.259.08:05:12.24#ibcon#enter wrdev, iclass 6, count 0 2006.259.08:05:12.24#ibcon#first serial, iclass 6, count 0 2006.259.08:05:12.24#ibcon#enter sib2, iclass 6, count 0 2006.259.08:05:12.24#ibcon#flushed, iclass 6, count 0 2006.259.08:05:12.24#ibcon#about to write, iclass 6, count 0 2006.259.08:05:12.24#ibcon#wrote, iclass 6, count 0 2006.259.08:05:12.24#ibcon#about to read 3, iclass 6, count 0 2006.259.08:05:12.26#ibcon#read 3, iclass 6, count 0 2006.259.08:05:12.26#ibcon#about to read 4, iclass 6, count 0 2006.259.08:05:12.26#ibcon#read 4, iclass 6, count 0 2006.259.08:05:12.26#ibcon#about to read 5, iclass 6, count 0 2006.259.08:05:12.26#ibcon#read 5, iclass 6, count 0 2006.259.08:05:12.26#ibcon#about to read 6, iclass 6, count 0 2006.259.08:05:12.26#ibcon#read 6, iclass 6, count 0 2006.259.08:05:12.26#ibcon#end of sib2, iclass 6, count 0 2006.259.08:05:12.26#ibcon#*mode == 0, iclass 6, count 0 2006.259.08:05:12.26#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.259.08:05:12.26#ibcon#[28=FRQ=04,712.99\r\n] 2006.259.08:05:12.26#ibcon#*before write, iclass 6, count 0 2006.259.08:05:12.26#ibcon#enter sib2, iclass 6, count 0 2006.259.08:05:12.26#ibcon#flushed, iclass 6, count 0 2006.259.08:05:12.26#ibcon#about to write, iclass 6, count 0 2006.259.08:05:12.26#ibcon#wrote, iclass 6, count 0 2006.259.08:05:12.26#ibcon#about to read 3, iclass 6, count 0 2006.259.08:05:12.30#ibcon#read 3, iclass 6, count 0 2006.259.08:05:12.30#ibcon#about to read 4, iclass 6, count 0 2006.259.08:05:12.30#ibcon#read 4, iclass 6, count 0 2006.259.08:05:12.30#ibcon#about to read 5, iclass 6, count 0 2006.259.08:05:12.30#ibcon#read 5, iclass 6, count 0 2006.259.08:05:12.30#ibcon#about to read 6, iclass 6, count 0 2006.259.08:05:12.30#ibcon#read 6, iclass 6, count 0 2006.259.08:05:12.30#ibcon#end of sib2, iclass 6, count 0 2006.259.08:05:12.30#ibcon#*after write, iclass 6, count 0 2006.259.08:05:12.30#ibcon#*before return 0, iclass 6, count 0 2006.259.08:05:12.30#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.259.08:05:12.30#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.259.08:05:12.30#ibcon#about to clear, iclass 6 cls_cnt 0 2006.259.08:05:12.30#ibcon#cleared, iclass 6 cls_cnt 0 2006.259.08:05:12.30$vc4f8/vb=4,5 2006.259.08:05:12.30#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.259.08:05:12.30#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.259.08:05:12.30#ibcon#ireg 11 cls_cnt 2 2006.259.08:05:12.30#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.259.08:05:12.36#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.259.08:05:12.36#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.259.08:05:12.36#ibcon#enter wrdev, iclass 10, count 2 2006.259.08:05:12.36#ibcon#first serial, iclass 10, count 2 2006.259.08:05:12.36#ibcon#enter sib2, iclass 10, count 2 2006.259.08:05:12.36#ibcon#flushed, iclass 10, count 2 2006.259.08:05:12.36#ibcon#about to write, iclass 10, count 2 2006.259.08:05:12.36#ibcon#wrote, iclass 10, count 2 2006.259.08:05:12.36#ibcon#about to read 3, iclass 10, count 2 2006.259.08:05:12.38#ibcon#read 3, iclass 10, count 2 2006.259.08:05:12.38#ibcon#about to read 4, iclass 10, count 2 2006.259.08:05:12.38#ibcon#read 4, iclass 10, count 2 2006.259.08:05:12.38#ibcon#about to read 5, iclass 10, count 2 2006.259.08:05:12.38#ibcon#read 5, iclass 10, count 2 2006.259.08:05:12.38#ibcon#about to read 6, iclass 10, count 2 2006.259.08:05:12.38#ibcon#read 6, iclass 10, count 2 2006.259.08:05:12.38#ibcon#end of sib2, iclass 10, count 2 2006.259.08:05:12.38#ibcon#*mode == 0, iclass 10, count 2 2006.259.08:05:12.38#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.259.08:05:12.38#ibcon#[27=AT04-05\r\n] 2006.259.08:05:12.38#ibcon#*before write, iclass 10, count 2 2006.259.08:05:12.38#ibcon#enter sib2, iclass 10, count 2 2006.259.08:05:12.38#ibcon#flushed, iclass 10, count 2 2006.259.08:05:12.38#ibcon#about to write, iclass 10, count 2 2006.259.08:05:12.38#ibcon#wrote, iclass 10, count 2 2006.259.08:05:12.38#ibcon#about to read 3, iclass 10, count 2 2006.259.08:05:12.41#ibcon#read 3, iclass 10, count 2 2006.259.08:05:12.41#ibcon#about to read 4, iclass 10, count 2 2006.259.08:05:12.41#ibcon#read 4, iclass 10, count 2 2006.259.08:05:12.41#ibcon#about to read 5, iclass 10, count 2 2006.259.08:05:12.41#ibcon#read 5, iclass 10, count 2 2006.259.08:05:12.41#ibcon#about to read 6, iclass 10, count 2 2006.259.08:05:12.41#ibcon#read 6, iclass 10, count 2 2006.259.08:05:12.41#ibcon#end of sib2, iclass 10, count 2 2006.259.08:05:12.41#ibcon#*after write, iclass 10, count 2 2006.259.08:05:12.41#ibcon#*before return 0, iclass 10, count 2 2006.259.08:05:12.41#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.259.08:05:12.41#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.259.08:05:12.41#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.259.08:05:12.41#ibcon#ireg 7 cls_cnt 0 2006.259.08:05:12.41#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.259.08:05:12.53#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.259.08:05:12.53#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.259.08:05:12.53#ibcon#enter wrdev, iclass 10, count 0 2006.259.08:05:12.53#ibcon#first serial, iclass 10, count 0 2006.259.08:05:12.53#ibcon#enter sib2, iclass 10, count 0 2006.259.08:05:12.53#ibcon#flushed, iclass 10, count 0 2006.259.08:05:12.53#ibcon#about to write, iclass 10, count 0 2006.259.08:05:12.53#ibcon#wrote, iclass 10, count 0 2006.259.08:05:12.53#ibcon#about to read 3, iclass 10, count 0 2006.259.08:05:12.55#ibcon#read 3, iclass 10, count 0 2006.259.08:05:12.55#ibcon#about to read 4, iclass 10, count 0 2006.259.08:05:12.55#ibcon#read 4, iclass 10, count 0 2006.259.08:05:12.55#ibcon#about to read 5, iclass 10, count 0 2006.259.08:05:12.55#ibcon#read 5, iclass 10, count 0 2006.259.08:05:12.55#ibcon#about to read 6, iclass 10, count 0 2006.259.08:05:12.55#ibcon#read 6, iclass 10, count 0 2006.259.08:05:12.55#ibcon#end of sib2, iclass 10, count 0 2006.259.08:05:12.55#ibcon#*mode == 0, iclass 10, count 0 2006.259.08:05:12.55#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.259.08:05:12.55#ibcon#[27=USB\r\n] 2006.259.08:05:12.55#ibcon#*before write, iclass 10, count 0 2006.259.08:05:12.55#ibcon#enter sib2, iclass 10, count 0 2006.259.08:05:12.55#ibcon#flushed, iclass 10, count 0 2006.259.08:05:12.55#ibcon#about to write, iclass 10, count 0 2006.259.08:05:12.55#ibcon#wrote, iclass 10, count 0 2006.259.08:05:12.55#ibcon#about to read 3, iclass 10, count 0 2006.259.08:05:12.58#ibcon#read 3, iclass 10, count 0 2006.259.08:05:12.58#ibcon#about to read 4, iclass 10, count 0 2006.259.08:05:12.58#ibcon#read 4, iclass 10, count 0 2006.259.08:05:12.58#ibcon#about to read 5, iclass 10, count 0 2006.259.08:05:12.58#ibcon#read 5, iclass 10, count 0 2006.259.08:05:12.58#ibcon#about to read 6, iclass 10, count 0 2006.259.08:05:12.58#ibcon#read 6, iclass 10, count 0 2006.259.08:05:12.58#ibcon#end of sib2, iclass 10, count 0 2006.259.08:05:12.58#ibcon#*after write, iclass 10, count 0 2006.259.08:05:12.58#ibcon#*before return 0, iclass 10, count 0 2006.259.08:05:12.58#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.259.08:05:12.58#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.259.08:05:12.58#ibcon#about to clear, iclass 10 cls_cnt 0 2006.259.08:05:12.58#ibcon#cleared, iclass 10 cls_cnt 0 2006.259.08:05:12.58$vc4f8/vblo=5,744.99 2006.259.08:05:12.58#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.259.08:05:12.58#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.259.08:05:12.58#ibcon#ireg 17 cls_cnt 0 2006.259.08:05:12.58#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.259.08:05:12.58#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.259.08:05:12.58#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.259.08:05:12.58#ibcon#enter wrdev, iclass 12, count 0 2006.259.08:05:12.58#ibcon#first serial, iclass 12, count 0 2006.259.08:05:12.58#ibcon#enter sib2, iclass 12, count 0 2006.259.08:05:12.58#ibcon#flushed, iclass 12, count 0 2006.259.08:05:12.58#ibcon#about to write, iclass 12, count 0 2006.259.08:05:12.58#ibcon#wrote, iclass 12, count 0 2006.259.08:05:12.58#ibcon#about to read 3, iclass 12, count 0 2006.259.08:05:12.60#ibcon#read 3, iclass 12, count 0 2006.259.08:05:12.60#ibcon#about to read 4, iclass 12, count 0 2006.259.08:05:12.60#ibcon#read 4, iclass 12, count 0 2006.259.08:05:12.60#ibcon#about to read 5, iclass 12, count 0 2006.259.08:05:12.60#ibcon#read 5, iclass 12, count 0 2006.259.08:05:12.60#ibcon#about to read 6, iclass 12, count 0 2006.259.08:05:12.60#ibcon#read 6, iclass 12, count 0 2006.259.08:05:12.60#ibcon#end of sib2, iclass 12, count 0 2006.259.08:05:12.60#ibcon#*mode == 0, iclass 12, count 0 2006.259.08:05:12.60#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.259.08:05:12.60#ibcon#[28=FRQ=05,744.99\r\n] 2006.259.08:05:12.60#ibcon#*before write, iclass 12, count 0 2006.259.08:05:12.60#ibcon#enter sib2, iclass 12, count 0 2006.259.08:05:12.60#ibcon#flushed, iclass 12, count 0 2006.259.08:05:12.60#ibcon#about to write, iclass 12, count 0 2006.259.08:05:12.60#ibcon#wrote, iclass 12, count 0 2006.259.08:05:12.60#ibcon#about to read 3, iclass 12, count 0 2006.259.08:05:12.64#ibcon#read 3, iclass 12, count 0 2006.259.08:05:12.64#ibcon#about to read 4, iclass 12, count 0 2006.259.08:05:12.64#ibcon#read 4, iclass 12, count 0 2006.259.08:05:12.64#ibcon#about to read 5, iclass 12, count 0 2006.259.08:05:12.64#ibcon#read 5, iclass 12, count 0 2006.259.08:05:12.64#ibcon#about to read 6, iclass 12, count 0 2006.259.08:05:12.64#ibcon#read 6, iclass 12, count 0 2006.259.08:05:12.64#ibcon#end of sib2, iclass 12, count 0 2006.259.08:05:12.64#ibcon#*after write, iclass 12, count 0 2006.259.08:05:12.64#ibcon#*before return 0, iclass 12, count 0 2006.259.08:05:12.64#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.259.08:05:12.64#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.259.08:05:12.64#ibcon#about to clear, iclass 12 cls_cnt 0 2006.259.08:05:12.64#ibcon#cleared, iclass 12 cls_cnt 0 2006.259.08:05:12.64$vc4f8/vb=5,4 2006.259.08:05:12.64#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.259.08:05:12.64#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.259.08:05:12.64#ibcon#ireg 11 cls_cnt 2 2006.259.08:05:12.64#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.259.08:05:12.70#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.259.08:05:12.70#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.259.08:05:12.70#ibcon#enter wrdev, iclass 14, count 2 2006.259.08:05:12.70#ibcon#first serial, iclass 14, count 2 2006.259.08:05:12.70#ibcon#enter sib2, iclass 14, count 2 2006.259.08:05:12.70#ibcon#flushed, iclass 14, count 2 2006.259.08:05:12.70#ibcon#about to write, iclass 14, count 2 2006.259.08:05:12.70#ibcon#wrote, iclass 14, count 2 2006.259.08:05:12.70#ibcon#about to read 3, iclass 14, count 2 2006.259.08:05:12.72#ibcon#read 3, iclass 14, count 2 2006.259.08:05:12.72#ibcon#about to read 4, iclass 14, count 2 2006.259.08:05:12.72#ibcon#read 4, iclass 14, count 2 2006.259.08:05:12.72#ibcon#about to read 5, iclass 14, count 2 2006.259.08:05:12.72#ibcon#read 5, iclass 14, count 2 2006.259.08:05:12.72#ibcon#about to read 6, iclass 14, count 2 2006.259.08:05:12.72#ibcon#read 6, iclass 14, count 2 2006.259.08:05:12.72#ibcon#end of sib2, iclass 14, count 2 2006.259.08:05:12.72#ibcon#*mode == 0, iclass 14, count 2 2006.259.08:05:12.72#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.259.08:05:12.72#ibcon#[27=AT05-04\r\n] 2006.259.08:05:12.72#ibcon#*before write, iclass 14, count 2 2006.259.08:05:12.72#ibcon#enter sib2, iclass 14, count 2 2006.259.08:05:12.72#ibcon#flushed, iclass 14, count 2 2006.259.08:05:12.72#ibcon#about to write, iclass 14, count 2 2006.259.08:05:12.72#ibcon#wrote, iclass 14, count 2 2006.259.08:05:12.72#ibcon#about to read 3, iclass 14, count 2 2006.259.08:05:12.75#ibcon#read 3, iclass 14, count 2 2006.259.08:05:12.75#ibcon#about to read 4, iclass 14, count 2 2006.259.08:05:12.75#ibcon#read 4, iclass 14, count 2 2006.259.08:05:12.75#ibcon#about to read 5, iclass 14, count 2 2006.259.08:05:12.75#ibcon#read 5, iclass 14, count 2 2006.259.08:05:12.75#ibcon#about to read 6, iclass 14, count 2 2006.259.08:05:12.75#ibcon#read 6, iclass 14, count 2 2006.259.08:05:12.75#ibcon#end of sib2, iclass 14, count 2 2006.259.08:05:12.75#ibcon#*after write, iclass 14, count 2 2006.259.08:05:12.75#ibcon#*before return 0, iclass 14, count 2 2006.259.08:05:12.75#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.259.08:05:12.75#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.259.08:05:12.75#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.259.08:05:12.75#ibcon#ireg 7 cls_cnt 0 2006.259.08:05:12.75#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.259.08:05:12.87#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.259.08:05:12.87#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.259.08:05:12.87#ibcon#enter wrdev, iclass 14, count 0 2006.259.08:05:12.87#ibcon#first serial, iclass 14, count 0 2006.259.08:05:12.87#ibcon#enter sib2, iclass 14, count 0 2006.259.08:05:12.87#ibcon#flushed, iclass 14, count 0 2006.259.08:05:12.87#ibcon#about to write, iclass 14, count 0 2006.259.08:05:12.87#ibcon#wrote, iclass 14, count 0 2006.259.08:05:12.87#ibcon#about to read 3, iclass 14, count 0 2006.259.08:05:12.89#ibcon#read 3, iclass 14, count 0 2006.259.08:05:12.89#ibcon#about to read 4, iclass 14, count 0 2006.259.08:05:12.89#ibcon#read 4, iclass 14, count 0 2006.259.08:05:12.89#ibcon#about to read 5, iclass 14, count 0 2006.259.08:05:12.89#ibcon#read 5, iclass 14, count 0 2006.259.08:05:12.89#ibcon#about to read 6, iclass 14, count 0 2006.259.08:05:12.89#ibcon#read 6, iclass 14, count 0 2006.259.08:05:12.89#ibcon#end of sib2, iclass 14, count 0 2006.259.08:05:12.89#ibcon#*mode == 0, iclass 14, count 0 2006.259.08:05:12.89#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.259.08:05:12.89#ibcon#[27=USB\r\n] 2006.259.08:05:12.89#ibcon#*before write, iclass 14, count 0 2006.259.08:05:12.89#ibcon#enter sib2, iclass 14, count 0 2006.259.08:05:12.89#ibcon#flushed, iclass 14, count 0 2006.259.08:05:12.89#ibcon#about to write, iclass 14, count 0 2006.259.08:05:12.89#ibcon#wrote, iclass 14, count 0 2006.259.08:05:12.89#ibcon#about to read 3, iclass 14, count 0 2006.259.08:05:12.92#ibcon#read 3, iclass 14, count 0 2006.259.08:05:12.92#ibcon#about to read 4, iclass 14, count 0 2006.259.08:05:12.92#ibcon#read 4, iclass 14, count 0 2006.259.08:05:12.92#ibcon#about to read 5, iclass 14, count 0 2006.259.08:05:12.92#ibcon#read 5, iclass 14, count 0 2006.259.08:05:12.92#ibcon#about to read 6, iclass 14, count 0 2006.259.08:05:12.92#ibcon#read 6, iclass 14, count 0 2006.259.08:05:12.92#ibcon#end of sib2, iclass 14, count 0 2006.259.08:05:12.92#ibcon#*after write, iclass 14, count 0 2006.259.08:05:12.92#ibcon#*before return 0, iclass 14, count 0 2006.259.08:05:12.92#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.259.08:05:12.92#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.259.08:05:12.92#ibcon#about to clear, iclass 14 cls_cnt 0 2006.259.08:05:12.92#ibcon#cleared, iclass 14 cls_cnt 0 2006.259.08:05:12.92$vc4f8/vblo=6,752.99 2006.259.08:05:12.92#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.259.08:05:12.92#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.259.08:05:12.92#ibcon#ireg 17 cls_cnt 0 2006.259.08:05:12.92#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.259.08:05:12.92#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.259.08:05:12.92#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.259.08:05:12.92#ibcon#enter wrdev, iclass 16, count 0 2006.259.08:05:12.92#ibcon#first serial, iclass 16, count 0 2006.259.08:05:12.92#ibcon#enter sib2, iclass 16, count 0 2006.259.08:05:12.92#ibcon#flushed, iclass 16, count 0 2006.259.08:05:12.92#ibcon#about to write, iclass 16, count 0 2006.259.08:05:12.92#ibcon#wrote, iclass 16, count 0 2006.259.08:05:12.92#ibcon#about to read 3, iclass 16, count 0 2006.259.08:05:12.94#ibcon#read 3, iclass 16, count 0 2006.259.08:05:12.94#ibcon#about to read 4, iclass 16, count 0 2006.259.08:05:12.94#ibcon#read 4, iclass 16, count 0 2006.259.08:05:12.94#ibcon#about to read 5, iclass 16, count 0 2006.259.08:05:12.94#ibcon#read 5, iclass 16, count 0 2006.259.08:05:12.94#ibcon#about to read 6, iclass 16, count 0 2006.259.08:05:12.94#ibcon#read 6, iclass 16, count 0 2006.259.08:05:12.94#ibcon#end of sib2, iclass 16, count 0 2006.259.08:05:12.94#ibcon#*mode == 0, iclass 16, count 0 2006.259.08:05:12.94#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.259.08:05:12.94#ibcon#[28=FRQ=06,752.99\r\n] 2006.259.08:05:12.94#ibcon#*before write, iclass 16, count 0 2006.259.08:05:12.94#ibcon#enter sib2, iclass 16, count 0 2006.259.08:05:12.94#ibcon#flushed, iclass 16, count 0 2006.259.08:05:12.94#ibcon#about to write, iclass 16, count 0 2006.259.08:05:12.94#ibcon#wrote, iclass 16, count 0 2006.259.08:05:12.94#ibcon#about to read 3, iclass 16, count 0 2006.259.08:05:12.98#ibcon#read 3, iclass 16, count 0 2006.259.08:05:12.98#ibcon#about to read 4, iclass 16, count 0 2006.259.08:05:12.98#ibcon#read 4, iclass 16, count 0 2006.259.08:05:12.98#ibcon#about to read 5, iclass 16, count 0 2006.259.08:05:12.98#ibcon#read 5, iclass 16, count 0 2006.259.08:05:12.98#ibcon#about to read 6, iclass 16, count 0 2006.259.08:05:12.98#ibcon#read 6, iclass 16, count 0 2006.259.08:05:12.98#ibcon#end of sib2, iclass 16, count 0 2006.259.08:05:12.98#ibcon#*after write, iclass 16, count 0 2006.259.08:05:12.98#ibcon#*before return 0, iclass 16, count 0 2006.259.08:05:12.98#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.259.08:05:12.98#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.259.08:05:12.98#ibcon#about to clear, iclass 16 cls_cnt 0 2006.259.08:05:12.98#ibcon#cleared, iclass 16 cls_cnt 0 2006.259.08:05:12.98$vc4f8/vb=6,4 2006.259.08:05:12.98#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.259.08:05:12.98#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.259.08:05:12.98#ibcon#ireg 11 cls_cnt 2 2006.259.08:05:12.98#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.259.08:05:13.04#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.259.08:05:13.04#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.259.08:05:13.04#ibcon#enter wrdev, iclass 18, count 2 2006.259.08:05:13.04#ibcon#first serial, iclass 18, count 2 2006.259.08:05:13.04#ibcon#enter sib2, iclass 18, count 2 2006.259.08:05:13.04#ibcon#flushed, iclass 18, count 2 2006.259.08:05:13.04#ibcon#about to write, iclass 18, count 2 2006.259.08:05:13.04#ibcon#wrote, iclass 18, count 2 2006.259.08:05:13.04#ibcon#about to read 3, iclass 18, count 2 2006.259.08:05:13.06#ibcon#read 3, iclass 18, count 2 2006.259.08:05:13.06#ibcon#about to read 4, iclass 18, count 2 2006.259.08:05:13.06#ibcon#read 4, iclass 18, count 2 2006.259.08:05:13.06#ibcon#about to read 5, iclass 18, count 2 2006.259.08:05:13.06#ibcon#read 5, iclass 18, count 2 2006.259.08:05:13.06#ibcon#about to read 6, iclass 18, count 2 2006.259.08:05:13.06#ibcon#read 6, iclass 18, count 2 2006.259.08:05:13.06#ibcon#end of sib2, iclass 18, count 2 2006.259.08:05:13.06#ibcon#*mode == 0, iclass 18, count 2 2006.259.08:05:13.06#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.259.08:05:13.06#ibcon#[27=AT06-04\r\n] 2006.259.08:05:13.06#ibcon#*before write, iclass 18, count 2 2006.259.08:05:13.06#ibcon#enter sib2, iclass 18, count 2 2006.259.08:05:13.06#ibcon#flushed, iclass 18, count 2 2006.259.08:05:13.06#ibcon#about to write, iclass 18, count 2 2006.259.08:05:13.06#ibcon#wrote, iclass 18, count 2 2006.259.08:05:13.06#ibcon#about to read 3, iclass 18, count 2 2006.259.08:05:13.09#ibcon#read 3, iclass 18, count 2 2006.259.08:05:13.09#ibcon#about to read 4, iclass 18, count 2 2006.259.08:05:13.09#ibcon#read 4, iclass 18, count 2 2006.259.08:05:13.09#ibcon#about to read 5, iclass 18, count 2 2006.259.08:05:13.09#ibcon#read 5, iclass 18, count 2 2006.259.08:05:13.09#ibcon#about to read 6, iclass 18, count 2 2006.259.08:05:13.09#ibcon#read 6, iclass 18, count 2 2006.259.08:05:13.09#ibcon#end of sib2, iclass 18, count 2 2006.259.08:05:13.09#ibcon#*after write, iclass 18, count 2 2006.259.08:05:13.09#ibcon#*before return 0, iclass 18, count 2 2006.259.08:05:13.09#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.259.08:05:13.09#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.259.08:05:13.09#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.259.08:05:13.09#ibcon#ireg 7 cls_cnt 0 2006.259.08:05:13.09#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.259.08:05:13.21#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.259.08:05:13.21#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.259.08:05:13.21#ibcon#enter wrdev, iclass 18, count 0 2006.259.08:05:13.21#ibcon#first serial, iclass 18, count 0 2006.259.08:05:13.21#ibcon#enter sib2, iclass 18, count 0 2006.259.08:05:13.21#ibcon#flushed, iclass 18, count 0 2006.259.08:05:13.21#ibcon#about to write, iclass 18, count 0 2006.259.08:05:13.21#ibcon#wrote, iclass 18, count 0 2006.259.08:05:13.21#ibcon#about to read 3, iclass 18, count 0 2006.259.08:05:13.23#ibcon#read 3, iclass 18, count 0 2006.259.08:05:13.23#ibcon#about to read 4, iclass 18, count 0 2006.259.08:05:13.23#ibcon#read 4, iclass 18, count 0 2006.259.08:05:13.23#ibcon#about to read 5, iclass 18, count 0 2006.259.08:05:13.23#ibcon#read 5, iclass 18, count 0 2006.259.08:05:13.23#ibcon#about to read 6, iclass 18, count 0 2006.259.08:05:13.23#ibcon#read 6, iclass 18, count 0 2006.259.08:05:13.23#ibcon#end of sib2, iclass 18, count 0 2006.259.08:05:13.23#ibcon#*mode == 0, iclass 18, count 0 2006.259.08:05:13.23#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.259.08:05:13.23#ibcon#[27=USB\r\n] 2006.259.08:05:13.23#ibcon#*before write, iclass 18, count 0 2006.259.08:05:13.23#ibcon#enter sib2, iclass 18, count 0 2006.259.08:05:13.23#ibcon#flushed, iclass 18, count 0 2006.259.08:05:13.23#ibcon#about to write, iclass 18, count 0 2006.259.08:05:13.23#ibcon#wrote, iclass 18, count 0 2006.259.08:05:13.23#ibcon#about to read 3, iclass 18, count 0 2006.259.08:05:13.26#ibcon#read 3, iclass 18, count 0 2006.259.08:05:13.26#ibcon#about to read 4, iclass 18, count 0 2006.259.08:05:13.26#ibcon#read 4, iclass 18, count 0 2006.259.08:05:13.26#ibcon#about to read 5, iclass 18, count 0 2006.259.08:05:13.26#ibcon#read 5, iclass 18, count 0 2006.259.08:05:13.26#ibcon#about to read 6, iclass 18, count 0 2006.259.08:05:13.26#ibcon#read 6, iclass 18, count 0 2006.259.08:05:13.26#ibcon#end of sib2, iclass 18, count 0 2006.259.08:05:13.26#ibcon#*after write, iclass 18, count 0 2006.259.08:05:13.26#ibcon#*before return 0, iclass 18, count 0 2006.259.08:05:13.26#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.259.08:05:13.26#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.259.08:05:13.26#ibcon#about to clear, iclass 18 cls_cnt 0 2006.259.08:05:13.26#ibcon#cleared, iclass 18 cls_cnt 0 2006.259.08:05:13.26$vc4f8/vabw=wide 2006.259.08:05:13.26#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.259.08:05:13.26#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.259.08:05:13.26#ibcon#ireg 8 cls_cnt 0 2006.259.08:05:13.26#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.259.08:05:13.26#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.259.08:05:13.26#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.259.08:05:13.26#ibcon#enter wrdev, iclass 20, count 0 2006.259.08:05:13.26#ibcon#first serial, iclass 20, count 0 2006.259.08:05:13.26#ibcon#enter sib2, iclass 20, count 0 2006.259.08:05:13.26#ibcon#flushed, iclass 20, count 0 2006.259.08:05:13.26#ibcon#about to write, iclass 20, count 0 2006.259.08:05:13.26#ibcon#wrote, iclass 20, count 0 2006.259.08:05:13.26#ibcon#about to read 3, iclass 20, count 0 2006.259.08:05:13.28#ibcon#read 3, iclass 20, count 0 2006.259.08:05:13.28#ibcon#about to read 4, iclass 20, count 0 2006.259.08:05:13.28#ibcon#read 4, iclass 20, count 0 2006.259.08:05:13.28#ibcon#about to read 5, iclass 20, count 0 2006.259.08:05:13.28#ibcon#read 5, iclass 20, count 0 2006.259.08:05:13.28#ibcon#about to read 6, iclass 20, count 0 2006.259.08:05:13.28#ibcon#read 6, iclass 20, count 0 2006.259.08:05:13.28#ibcon#end of sib2, iclass 20, count 0 2006.259.08:05:13.28#ibcon#*mode == 0, iclass 20, count 0 2006.259.08:05:13.28#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.259.08:05:13.28#ibcon#[25=BW32\r\n] 2006.259.08:05:13.28#ibcon#*before write, iclass 20, count 0 2006.259.08:05:13.28#ibcon#enter sib2, iclass 20, count 0 2006.259.08:05:13.28#ibcon#flushed, iclass 20, count 0 2006.259.08:05:13.28#ibcon#about to write, iclass 20, count 0 2006.259.08:05:13.28#ibcon#wrote, iclass 20, count 0 2006.259.08:05:13.28#ibcon#about to read 3, iclass 20, count 0 2006.259.08:05:13.31#ibcon#read 3, iclass 20, count 0 2006.259.08:05:13.31#ibcon#about to read 4, iclass 20, count 0 2006.259.08:05:13.31#ibcon#read 4, iclass 20, count 0 2006.259.08:05:13.31#ibcon#about to read 5, iclass 20, count 0 2006.259.08:05:13.31#ibcon#read 5, iclass 20, count 0 2006.259.08:05:13.31#ibcon#about to read 6, iclass 20, count 0 2006.259.08:05:13.31#ibcon#read 6, iclass 20, count 0 2006.259.08:05:13.31#ibcon#end of sib2, iclass 20, count 0 2006.259.08:05:13.31#ibcon#*after write, iclass 20, count 0 2006.259.08:05:13.31#ibcon#*before return 0, iclass 20, count 0 2006.259.08:05:13.31#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.259.08:05:13.31#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.259.08:05:13.31#ibcon#about to clear, iclass 20 cls_cnt 0 2006.259.08:05:13.31#ibcon#cleared, iclass 20 cls_cnt 0 2006.259.08:05:13.31$vc4f8/vbbw=wide 2006.259.08:05:13.31#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.259.08:05:13.31#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.259.08:05:13.31#ibcon#ireg 8 cls_cnt 0 2006.259.08:05:13.31#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.259.08:05:13.38#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.259.08:05:13.38#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.259.08:05:13.38#ibcon#enter wrdev, iclass 22, count 0 2006.259.08:05:13.38#ibcon#first serial, iclass 22, count 0 2006.259.08:05:13.38#ibcon#enter sib2, iclass 22, count 0 2006.259.08:05:13.38#ibcon#flushed, iclass 22, count 0 2006.259.08:05:13.38#ibcon#about to write, iclass 22, count 0 2006.259.08:05:13.38#ibcon#wrote, iclass 22, count 0 2006.259.08:05:13.38#ibcon#about to read 3, iclass 22, count 0 2006.259.08:05:13.40#ibcon#read 3, iclass 22, count 0 2006.259.08:05:13.40#ibcon#about to read 4, iclass 22, count 0 2006.259.08:05:13.40#ibcon#read 4, iclass 22, count 0 2006.259.08:05:13.40#ibcon#about to read 5, iclass 22, count 0 2006.259.08:05:13.40#ibcon#read 5, iclass 22, count 0 2006.259.08:05:13.40#ibcon#about to read 6, iclass 22, count 0 2006.259.08:05:13.40#ibcon#read 6, iclass 22, count 0 2006.259.08:05:13.40#ibcon#end of sib2, iclass 22, count 0 2006.259.08:05:13.40#ibcon#*mode == 0, iclass 22, count 0 2006.259.08:05:13.40#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.259.08:05:13.40#ibcon#[27=BW32\r\n] 2006.259.08:05:13.40#ibcon#*before write, iclass 22, count 0 2006.259.08:05:13.40#ibcon#enter sib2, iclass 22, count 0 2006.259.08:05:13.40#ibcon#flushed, iclass 22, count 0 2006.259.08:05:13.40#ibcon#about to write, iclass 22, count 0 2006.259.08:05:13.40#ibcon#wrote, iclass 22, count 0 2006.259.08:05:13.40#ibcon#about to read 3, iclass 22, count 0 2006.259.08:05:13.43#ibcon#read 3, iclass 22, count 0 2006.259.08:05:13.43#ibcon#about to read 4, iclass 22, count 0 2006.259.08:05:13.43#ibcon#read 4, iclass 22, count 0 2006.259.08:05:13.43#ibcon#about to read 5, iclass 22, count 0 2006.259.08:05:13.43#ibcon#read 5, iclass 22, count 0 2006.259.08:05:13.43#ibcon#about to read 6, iclass 22, count 0 2006.259.08:05:13.43#ibcon#read 6, iclass 22, count 0 2006.259.08:05:13.43#ibcon#end of sib2, iclass 22, count 0 2006.259.08:05:13.43#ibcon#*after write, iclass 22, count 0 2006.259.08:05:13.43#ibcon#*before return 0, iclass 22, count 0 2006.259.08:05:13.43#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.259.08:05:13.43#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.259.08:05:13.43#ibcon#about to clear, iclass 22 cls_cnt 0 2006.259.08:05:13.43#ibcon#cleared, iclass 22 cls_cnt 0 2006.259.08:05:13.43$4f8m12a/ifd4f 2006.259.08:05:13.43$ifd4f/lo= 2006.259.08:05:13.43$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.259.08:05:13.43$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.259.08:05:13.43$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.259.08:05:13.43$ifd4f/patch= 2006.259.08:05:13.43$ifd4f/patch=lo1,a1,a2,a3,a4 2006.259.08:05:13.43$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.259.08:05:13.43$ifd4f/patch=lo3,a5,a6,a7,a8 2006.259.08:05:13.43$4f8m12a/"form=m,16.000,1:2 2006.259.08:05:13.43$4f8m12a/"tpicd 2006.259.08:05:13.43$4f8m12a/echo=off 2006.259.08:05:13.43$4f8m12a/xlog=off 2006.259.08:05:13.43:!2006.259.08:05:40 2006.259.08:05:22.13#trakl#Source acquired 2006.259.08:05:22.13#flagr#flagr/antenna,acquired 2006.259.08:05:40.00:preob 2006.259.08:05:41.13/onsource/TRACKING 2006.259.08:05:41.13:!2006.259.08:05:50 2006.259.08:05:50.00:data_valid=on 2006.259.08:05:50.00:midob 2006.259.08:05:50.13/onsource/TRACKING 2006.259.08:05:50.13/wx/22.04,1013.1,86 2006.259.08:05:50.31/cable/+6.4593E-03 2006.259.08:05:51.40/va/01,08,usb,yes,31,33 2006.259.08:05:51.40/va/02,07,usb,yes,31,33 2006.259.08:05:51.40/va/03,08,usb,yes,23,24 2006.259.08:05:51.40/va/04,07,usb,yes,32,35 2006.259.08:05:51.40/va/05,07,usb,yes,36,38 2006.259.08:05:51.40/va/06,06,usb,yes,35,35 2006.259.08:05:51.40/va/07,06,usb,yes,36,35 2006.259.08:05:51.40/va/08,06,usb,yes,38,37 2006.259.08:05:51.63/valo/01,532.99,yes,locked 2006.259.08:05:51.63/valo/02,572.99,yes,locked 2006.259.08:05:51.63/valo/03,672.99,yes,locked 2006.259.08:05:51.63/valo/04,832.99,yes,locked 2006.259.08:05:51.63/valo/05,652.99,yes,locked 2006.259.08:05:51.63/valo/06,772.99,yes,locked 2006.259.08:05:51.63/valo/07,832.99,yes,locked 2006.259.08:05:51.63/valo/08,852.99,yes,locked 2006.259.08:05:52.72/vb/01,04,usb,yes,30,29 2006.259.08:05:52.72/vb/02,05,usb,yes,28,30 2006.259.08:05:52.72/vb/03,04,usb,yes,29,32 2006.259.08:05:52.72/vb/04,05,usb,yes,26,26 2006.259.08:05:52.72/vb/05,04,usb,yes,28,32 2006.259.08:05:52.72/vb/06,04,usb,yes,29,32 2006.259.08:05:52.72/vb/07,04,usb,yes,31,31 2006.259.08:05:52.72/vb/08,04,usb,yes,29,32 2006.259.08:05:52.95/vblo/01,632.99,yes,locked 2006.259.08:05:52.95/vblo/02,640.99,yes,locked 2006.259.08:05:52.95/vblo/03,656.99,yes,locked 2006.259.08:05:52.95/vblo/04,712.99,yes,locked 2006.259.08:05:52.95/vblo/05,744.99,yes,locked 2006.259.08:05:52.95/vblo/06,752.99,yes,locked 2006.259.08:05:52.95/vblo/07,734.99,yes,locked 2006.259.08:05:52.95/vblo/08,744.99,yes,locked 2006.259.08:05:53.10/vabw/8 2006.259.08:05:53.25/vbbw/8 2006.259.08:05:53.36/xfe/off,on,16.0 2006.259.08:05:53.73/ifatt/23,28,28,28 2006.259.08:05:54.07/fmout-gps/S +4.59E-07 2006.259.08:05:54.11:!2006.259.08:06:50 2006.259.08:06:50.00:data_valid=off 2006.259.08:06:50.01:postob 2006.259.08:06:50.09/cable/+6.4604E-03 2006.259.08:06:50.09/wx/22.03,1013.1,86 2006.259.08:06:51.07/fmout-gps/S +4.58E-07 2006.259.08:06:51.07:scan_name=259-0808,k06259,70 2006.259.08:06:51.08:source=1252+119,125438.26,114105.9,2000.0,ccw 2006.259.08:06:51.14#flagr#flagr/antenna,new-source 2006.259.08:06:52.14:checkk5 2006.259.08:06:52.57/chk_autoobs//k5ts1/ autoobs is running! 2006.259.08:06:52.96/chk_autoobs//k5ts2/ autoobs is running! 2006.259.08:06:53.36/chk_autoobs//k5ts3/ autoobs is running! 2006.259.08:06:53.74/chk_autoobs//k5ts4/ autoobs is running! 2006.259.08:06:54.16/chk_obsdata//k5ts1/T2590805??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.259.08:06:54.57/chk_obsdata//k5ts2/T2590805??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.259.08:06:55.01/chk_obsdata//k5ts3/T2590805??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.259.08:06:55.63/chk_obsdata//k5ts4/T2590805??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.259.08:06:56.33/k5log//k5ts1_log_newline 2006.259.08:06:57.15/k5log//k5ts2_log_newline 2006.259.08:06:57.91/k5log//k5ts3_log_newline 2006.259.08:06:58.67/k5log//k5ts4_log_newline 2006.259.08:06:58.69/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.259.08:06:58.69:4f8m12a=2 2006.259.08:06:58.69$4f8m12a/echo=on 2006.259.08:06:58.69$4f8m12a/pcalon 2006.259.08:06:58.69$pcalon/"no phase cal control is implemented here 2006.259.08:06:58.69$4f8m12a/"tpicd=stop 2006.259.08:06:58.69$4f8m12a/vc4f8 2006.259.08:06:58.69$vc4f8/valo=1,532.99 2006.259.08:06:58.69#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.259.08:06:58.69#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.259.08:06:58.69#ibcon#ireg 17 cls_cnt 0 2006.259.08:06:58.69#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.259.08:06:58.69#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.259.08:06:58.69#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.259.08:06:58.69#ibcon#enter wrdev, iclass 33, count 0 2006.259.08:06:58.69#ibcon#first serial, iclass 33, count 0 2006.259.08:06:58.69#ibcon#enter sib2, iclass 33, count 0 2006.259.08:06:58.69#ibcon#flushed, iclass 33, count 0 2006.259.08:06:58.69#ibcon#about to write, iclass 33, count 0 2006.259.08:06:58.69#ibcon#wrote, iclass 33, count 0 2006.259.08:06:58.69#ibcon#about to read 3, iclass 33, count 0 2006.259.08:06:58.71#ibcon#read 3, iclass 33, count 0 2006.259.08:06:58.71#ibcon#about to read 4, iclass 33, count 0 2006.259.08:06:58.71#ibcon#read 4, iclass 33, count 0 2006.259.08:06:58.71#ibcon#about to read 5, iclass 33, count 0 2006.259.08:06:58.71#ibcon#read 5, iclass 33, count 0 2006.259.08:06:58.71#ibcon#about to read 6, iclass 33, count 0 2006.259.08:06:58.71#ibcon#read 6, iclass 33, count 0 2006.259.08:06:58.71#ibcon#end of sib2, iclass 33, count 0 2006.259.08:06:58.71#ibcon#*mode == 0, iclass 33, count 0 2006.259.08:06:58.71#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.259.08:06:58.71#ibcon#[26=FRQ=01,532.99\r\n] 2006.259.08:06:58.71#ibcon#*before write, iclass 33, count 0 2006.259.08:06:58.71#ibcon#enter sib2, iclass 33, count 0 2006.259.08:06:58.71#ibcon#flushed, iclass 33, count 0 2006.259.08:06:58.71#ibcon#about to write, iclass 33, count 0 2006.259.08:06:58.71#ibcon#wrote, iclass 33, count 0 2006.259.08:06:58.71#ibcon#about to read 3, iclass 33, count 0 2006.259.08:06:58.76#ibcon#read 3, iclass 33, count 0 2006.259.08:06:58.76#ibcon#about to read 4, iclass 33, count 0 2006.259.08:06:58.76#ibcon#read 4, iclass 33, count 0 2006.259.08:06:58.76#ibcon#about to read 5, iclass 33, count 0 2006.259.08:06:58.76#ibcon#read 5, iclass 33, count 0 2006.259.08:06:58.76#ibcon#about to read 6, iclass 33, count 0 2006.259.08:06:58.76#ibcon#read 6, iclass 33, count 0 2006.259.08:06:58.76#ibcon#end of sib2, iclass 33, count 0 2006.259.08:06:58.76#ibcon#*after write, iclass 33, count 0 2006.259.08:06:58.76#ibcon#*before return 0, iclass 33, count 0 2006.259.08:06:58.76#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.259.08:06:58.76#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.259.08:06:58.76#ibcon#about to clear, iclass 33 cls_cnt 0 2006.259.08:06:58.76#ibcon#cleared, iclass 33 cls_cnt 0 2006.259.08:06:58.76$vc4f8/va=1,8 2006.259.08:06:58.76#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.259.08:06:58.76#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.259.08:06:58.76#ibcon#ireg 11 cls_cnt 2 2006.259.08:06:58.76#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.259.08:06:58.76#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.259.08:06:58.76#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.259.08:06:58.76#ibcon#enter wrdev, iclass 35, count 2 2006.259.08:06:58.76#ibcon#first serial, iclass 35, count 2 2006.259.08:06:58.76#ibcon#enter sib2, iclass 35, count 2 2006.259.08:06:58.76#ibcon#flushed, iclass 35, count 2 2006.259.08:06:58.76#ibcon#about to write, iclass 35, count 2 2006.259.08:06:58.76#ibcon#wrote, iclass 35, count 2 2006.259.08:06:58.76#ibcon#about to read 3, iclass 35, count 2 2006.259.08:06:58.78#ibcon#read 3, iclass 35, count 2 2006.259.08:06:58.78#ibcon#about to read 4, iclass 35, count 2 2006.259.08:06:58.78#ibcon#read 4, iclass 35, count 2 2006.259.08:06:58.78#ibcon#about to read 5, iclass 35, count 2 2006.259.08:06:58.78#ibcon#read 5, iclass 35, count 2 2006.259.08:06:58.78#ibcon#about to read 6, iclass 35, count 2 2006.259.08:06:58.78#ibcon#read 6, iclass 35, count 2 2006.259.08:06:58.78#ibcon#end of sib2, iclass 35, count 2 2006.259.08:06:58.78#ibcon#*mode == 0, iclass 35, count 2 2006.259.08:06:58.78#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.259.08:06:58.78#ibcon#[25=AT01-08\r\n] 2006.259.08:06:58.78#ibcon#*before write, iclass 35, count 2 2006.259.08:06:58.78#ibcon#enter sib2, iclass 35, count 2 2006.259.08:06:58.78#ibcon#flushed, iclass 35, count 2 2006.259.08:06:58.78#ibcon#about to write, iclass 35, count 2 2006.259.08:06:58.78#ibcon#wrote, iclass 35, count 2 2006.259.08:06:58.78#ibcon#about to read 3, iclass 35, count 2 2006.259.08:06:58.81#ibcon#read 3, iclass 35, count 2 2006.259.08:06:58.81#ibcon#about to read 4, iclass 35, count 2 2006.259.08:06:58.81#ibcon#read 4, iclass 35, count 2 2006.259.08:06:58.81#ibcon#about to read 5, iclass 35, count 2 2006.259.08:06:58.81#ibcon#read 5, iclass 35, count 2 2006.259.08:06:58.81#ibcon#about to read 6, iclass 35, count 2 2006.259.08:06:58.81#ibcon#read 6, iclass 35, count 2 2006.259.08:06:58.81#ibcon#end of sib2, iclass 35, count 2 2006.259.08:06:58.81#ibcon#*after write, iclass 35, count 2 2006.259.08:06:58.81#ibcon#*before return 0, iclass 35, count 2 2006.259.08:06:58.81#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.259.08:06:58.81#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.259.08:06:58.81#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.259.08:06:58.81#ibcon#ireg 7 cls_cnt 0 2006.259.08:06:58.81#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.259.08:06:58.93#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.259.08:06:58.93#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.259.08:06:58.93#ibcon#enter wrdev, iclass 35, count 0 2006.259.08:06:58.93#ibcon#first serial, iclass 35, count 0 2006.259.08:06:58.93#ibcon#enter sib2, iclass 35, count 0 2006.259.08:06:58.93#ibcon#flushed, iclass 35, count 0 2006.259.08:06:58.93#ibcon#about to write, iclass 35, count 0 2006.259.08:06:58.94#ibcon#wrote, iclass 35, count 0 2006.259.08:06:58.94#ibcon#about to read 3, iclass 35, count 0 2006.259.08:06:58.95#ibcon#read 3, iclass 35, count 0 2006.259.08:06:58.95#ibcon#about to read 4, iclass 35, count 0 2006.259.08:06:58.95#ibcon#read 4, iclass 35, count 0 2006.259.08:06:58.95#ibcon#about to read 5, iclass 35, count 0 2006.259.08:06:58.95#ibcon#read 5, iclass 35, count 0 2006.259.08:06:58.95#ibcon#about to read 6, iclass 35, count 0 2006.259.08:06:58.95#ibcon#read 6, iclass 35, count 0 2006.259.08:06:58.95#ibcon#end of sib2, iclass 35, count 0 2006.259.08:06:58.95#ibcon#*mode == 0, iclass 35, count 0 2006.259.08:06:58.95#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.259.08:06:58.95#ibcon#[25=USB\r\n] 2006.259.08:06:58.95#ibcon#*before write, iclass 35, count 0 2006.259.08:06:58.95#ibcon#enter sib2, iclass 35, count 0 2006.259.08:06:58.95#ibcon#flushed, iclass 35, count 0 2006.259.08:06:58.95#ibcon#about to write, iclass 35, count 0 2006.259.08:06:58.95#ibcon#wrote, iclass 35, count 0 2006.259.08:06:58.95#ibcon#about to read 3, iclass 35, count 0 2006.259.08:06:58.98#ibcon#read 3, iclass 35, count 0 2006.259.08:06:58.98#ibcon#about to read 4, iclass 35, count 0 2006.259.08:06:58.98#ibcon#read 4, iclass 35, count 0 2006.259.08:06:58.98#ibcon#about to read 5, iclass 35, count 0 2006.259.08:06:58.98#ibcon#read 5, iclass 35, count 0 2006.259.08:06:58.98#ibcon#about to read 6, iclass 35, count 0 2006.259.08:06:58.98#ibcon#read 6, iclass 35, count 0 2006.259.08:06:58.98#ibcon#end of sib2, iclass 35, count 0 2006.259.08:06:58.98#ibcon#*after write, iclass 35, count 0 2006.259.08:06:58.98#ibcon#*before return 0, iclass 35, count 0 2006.259.08:06:58.98#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.259.08:06:58.98#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.259.08:06:58.98#ibcon#about to clear, iclass 35 cls_cnt 0 2006.259.08:06:58.98#ibcon#cleared, iclass 35 cls_cnt 0 2006.259.08:06:58.98$vc4f8/valo=2,572.99 2006.259.08:06:58.98#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.259.08:06:58.98#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.259.08:06:58.98#ibcon#ireg 17 cls_cnt 0 2006.259.08:06:58.98#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.259.08:06:58.98#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.259.08:06:58.98#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.259.08:06:58.98#ibcon#enter wrdev, iclass 37, count 0 2006.259.08:06:58.98#ibcon#first serial, iclass 37, count 0 2006.259.08:06:58.98#ibcon#enter sib2, iclass 37, count 0 2006.259.08:06:58.98#ibcon#flushed, iclass 37, count 0 2006.259.08:06:58.98#ibcon#about to write, iclass 37, count 0 2006.259.08:06:58.98#ibcon#wrote, iclass 37, count 0 2006.259.08:06:58.98#ibcon#about to read 3, iclass 37, count 0 2006.259.08:06:59.00#ibcon#read 3, iclass 37, count 0 2006.259.08:06:59.00#ibcon#about to read 4, iclass 37, count 0 2006.259.08:06:59.00#ibcon#read 4, iclass 37, count 0 2006.259.08:06:59.00#ibcon#about to read 5, iclass 37, count 0 2006.259.08:06:59.00#ibcon#read 5, iclass 37, count 0 2006.259.08:06:59.00#ibcon#about to read 6, iclass 37, count 0 2006.259.08:06:59.00#ibcon#read 6, iclass 37, count 0 2006.259.08:06:59.00#ibcon#end of sib2, iclass 37, count 0 2006.259.08:06:59.00#ibcon#*mode == 0, iclass 37, count 0 2006.259.08:06:59.00#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.259.08:06:59.00#ibcon#[26=FRQ=02,572.99\r\n] 2006.259.08:06:59.00#ibcon#*before write, iclass 37, count 0 2006.259.08:06:59.00#ibcon#enter sib2, iclass 37, count 0 2006.259.08:06:59.00#ibcon#flushed, iclass 37, count 0 2006.259.08:06:59.00#ibcon#about to write, iclass 37, count 0 2006.259.08:06:59.00#ibcon#wrote, iclass 37, count 0 2006.259.08:06:59.00#ibcon#about to read 3, iclass 37, count 0 2006.259.08:06:59.04#ibcon#read 3, iclass 37, count 0 2006.259.08:06:59.04#ibcon#about to read 4, iclass 37, count 0 2006.259.08:06:59.04#ibcon#read 4, iclass 37, count 0 2006.259.08:06:59.04#ibcon#about to read 5, iclass 37, count 0 2006.259.08:06:59.04#ibcon#read 5, iclass 37, count 0 2006.259.08:06:59.04#ibcon#about to read 6, iclass 37, count 0 2006.259.08:06:59.04#ibcon#read 6, iclass 37, count 0 2006.259.08:06:59.04#ibcon#end of sib2, iclass 37, count 0 2006.259.08:06:59.04#ibcon#*after write, iclass 37, count 0 2006.259.08:06:59.04#ibcon#*before return 0, iclass 37, count 0 2006.259.08:06:59.04#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.259.08:06:59.04#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.259.08:06:59.04#ibcon#about to clear, iclass 37 cls_cnt 0 2006.259.08:06:59.04#ibcon#cleared, iclass 37 cls_cnt 0 2006.259.08:06:59.04$vc4f8/va=2,7 2006.259.08:06:59.04#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.259.08:06:59.04#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.259.08:06:59.04#ibcon#ireg 11 cls_cnt 2 2006.259.08:06:59.04#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.259.08:06:59.10#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.259.08:06:59.10#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.259.08:06:59.10#ibcon#enter wrdev, iclass 39, count 2 2006.259.08:06:59.10#ibcon#first serial, iclass 39, count 2 2006.259.08:06:59.10#ibcon#enter sib2, iclass 39, count 2 2006.259.08:06:59.10#ibcon#flushed, iclass 39, count 2 2006.259.08:06:59.10#ibcon#about to write, iclass 39, count 2 2006.259.08:06:59.10#ibcon#wrote, iclass 39, count 2 2006.259.08:06:59.10#ibcon#about to read 3, iclass 39, count 2 2006.259.08:06:59.13#ibcon#read 3, iclass 39, count 2 2006.259.08:06:59.13#ibcon#about to read 4, iclass 39, count 2 2006.259.08:06:59.13#ibcon#read 4, iclass 39, count 2 2006.259.08:06:59.13#ibcon#about to read 5, iclass 39, count 2 2006.259.08:06:59.13#ibcon#read 5, iclass 39, count 2 2006.259.08:06:59.13#ibcon#about to read 6, iclass 39, count 2 2006.259.08:06:59.13#ibcon#read 6, iclass 39, count 2 2006.259.08:06:59.13#ibcon#end of sib2, iclass 39, count 2 2006.259.08:06:59.13#ibcon#*mode == 0, iclass 39, count 2 2006.259.08:06:59.13#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.259.08:06:59.13#ibcon#[25=AT02-07\r\n] 2006.259.08:06:59.13#ibcon#*before write, iclass 39, count 2 2006.259.08:06:59.13#ibcon#enter sib2, iclass 39, count 2 2006.259.08:06:59.13#ibcon#flushed, iclass 39, count 2 2006.259.08:06:59.13#ibcon#about to write, iclass 39, count 2 2006.259.08:06:59.13#ibcon#wrote, iclass 39, count 2 2006.259.08:06:59.13#ibcon#about to read 3, iclass 39, count 2 2006.259.08:06:59.16#ibcon#read 3, iclass 39, count 2 2006.259.08:06:59.16#ibcon#about to read 4, iclass 39, count 2 2006.259.08:06:59.16#ibcon#read 4, iclass 39, count 2 2006.259.08:06:59.16#ibcon#about to read 5, iclass 39, count 2 2006.259.08:06:59.16#ibcon#read 5, iclass 39, count 2 2006.259.08:06:59.16#ibcon#about to read 6, iclass 39, count 2 2006.259.08:06:59.16#ibcon#read 6, iclass 39, count 2 2006.259.08:06:59.16#ibcon#end of sib2, iclass 39, count 2 2006.259.08:06:59.16#ibcon#*after write, iclass 39, count 2 2006.259.08:06:59.16#ibcon#*before return 0, iclass 39, count 2 2006.259.08:06:59.16#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.259.08:06:59.16#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.259.08:06:59.16#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.259.08:06:59.16#ibcon#ireg 7 cls_cnt 0 2006.259.08:06:59.16#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.259.08:06:59.28#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.259.08:06:59.28#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.259.08:06:59.28#ibcon#enter wrdev, iclass 39, count 0 2006.259.08:06:59.28#ibcon#first serial, iclass 39, count 0 2006.259.08:06:59.28#ibcon#enter sib2, iclass 39, count 0 2006.259.08:06:59.28#ibcon#flushed, iclass 39, count 0 2006.259.08:06:59.28#ibcon#about to write, iclass 39, count 0 2006.259.08:06:59.28#ibcon#wrote, iclass 39, count 0 2006.259.08:06:59.28#ibcon#about to read 3, iclass 39, count 0 2006.259.08:06:59.30#ibcon#read 3, iclass 39, count 0 2006.259.08:06:59.30#ibcon#about to read 4, iclass 39, count 0 2006.259.08:06:59.30#ibcon#read 4, iclass 39, count 0 2006.259.08:06:59.30#ibcon#about to read 5, iclass 39, count 0 2006.259.08:06:59.30#ibcon#read 5, iclass 39, count 0 2006.259.08:06:59.30#ibcon#about to read 6, iclass 39, count 0 2006.259.08:06:59.30#ibcon#read 6, iclass 39, count 0 2006.259.08:06:59.30#ibcon#end of sib2, iclass 39, count 0 2006.259.08:06:59.30#ibcon#*mode == 0, iclass 39, count 0 2006.259.08:06:59.30#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.259.08:06:59.30#ibcon#[25=USB\r\n] 2006.259.08:06:59.30#ibcon#*before write, iclass 39, count 0 2006.259.08:06:59.30#ibcon#enter sib2, iclass 39, count 0 2006.259.08:06:59.30#ibcon#flushed, iclass 39, count 0 2006.259.08:06:59.30#ibcon#about to write, iclass 39, count 0 2006.259.08:06:59.30#ibcon#wrote, iclass 39, count 0 2006.259.08:06:59.30#ibcon#about to read 3, iclass 39, count 0 2006.259.08:06:59.33#ibcon#read 3, iclass 39, count 0 2006.259.08:06:59.33#ibcon#about to read 4, iclass 39, count 0 2006.259.08:06:59.33#ibcon#read 4, iclass 39, count 0 2006.259.08:06:59.33#ibcon#about to read 5, iclass 39, count 0 2006.259.08:06:59.33#ibcon#read 5, iclass 39, count 0 2006.259.08:06:59.33#ibcon#about to read 6, iclass 39, count 0 2006.259.08:06:59.33#ibcon#read 6, iclass 39, count 0 2006.259.08:06:59.33#ibcon#end of sib2, iclass 39, count 0 2006.259.08:06:59.33#ibcon#*after write, iclass 39, count 0 2006.259.08:06:59.33#ibcon#*before return 0, iclass 39, count 0 2006.259.08:06:59.33#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.259.08:06:59.33#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.259.08:06:59.33#ibcon#about to clear, iclass 39 cls_cnt 0 2006.259.08:06:59.33#ibcon#cleared, iclass 39 cls_cnt 0 2006.259.08:06:59.33$vc4f8/valo=3,672.99 2006.259.08:06:59.33#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.259.08:06:59.33#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.259.08:06:59.33#ibcon#ireg 17 cls_cnt 0 2006.259.08:06:59.33#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.259.08:06:59.33#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.259.08:06:59.33#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.259.08:06:59.33#ibcon#enter wrdev, iclass 3, count 0 2006.259.08:06:59.33#ibcon#first serial, iclass 3, count 0 2006.259.08:06:59.33#ibcon#enter sib2, iclass 3, count 0 2006.259.08:06:59.33#ibcon#flushed, iclass 3, count 0 2006.259.08:06:59.33#ibcon#about to write, iclass 3, count 0 2006.259.08:06:59.33#ibcon#wrote, iclass 3, count 0 2006.259.08:06:59.33#ibcon#about to read 3, iclass 3, count 0 2006.259.08:06:59.35#ibcon#read 3, iclass 3, count 0 2006.259.08:06:59.35#ibcon#about to read 4, iclass 3, count 0 2006.259.08:06:59.35#ibcon#read 4, iclass 3, count 0 2006.259.08:06:59.35#ibcon#about to read 5, iclass 3, count 0 2006.259.08:06:59.35#ibcon#read 5, iclass 3, count 0 2006.259.08:06:59.35#ibcon#about to read 6, iclass 3, count 0 2006.259.08:06:59.35#ibcon#read 6, iclass 3, count 0 2006.259.08:06:59.35#ibcon#end of sib2, iclass 3, count 0 2006.259.08:06:59.35#ibcon#*mode == 0, iclass 3, count 0 2006.259.08:06:59.35#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.259.08:06:59.35#ibcon#[26=FRQ=03,672.99\r\n] 2006.259.08:06:59.35#ibcon#*before write, iclass 3, count 0 2006.259.08:06:59.35#ibcon#enter sib2, iclass 3, count 0 2006.259.08:06:59.35#ibcon#flushed, iclass 3, count 0 2006.259.08:06:59.35#ibcon#about to write, iclass 3, count 0 2006.259.08:06:59.35#ibcon#wrote, iclass 3, count 0 2006.259.08:06:59.35#ibcon#about to read 3, iclass 3, count 0 2006.259.08:06:59.39#ibcon#read 3, iclass 3, count 0 2006.259.08:06:59.39#ibcon#about to read 4, iclass 3, count 0 2006.259.08:06:59.39#ibcon#read 4, iclass 3, count 0 2006.259.08:06:59.39#ibcon#about to read 5, iclass 3, count 0 2006.259.08:06:59.39#ibcon#read 5, iclass 3, count 0 2006.259.08:06:59.39#ibcon#about to read 6, iclass 3, count 0 2006.259.08:06:59.39#ibcon#read 6, iclass 3, count 0 2006.259.08:06:59.39#ibcon#end of sib2, iclass 3, count 0 2006.259.08:06:59.39#ibcon#*after write, iclass 3, count 0 2006.259.08:06:59.39#ibcon#*before return 0, iclass 3, count 0 2006.259.08:06:59.39#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.259.08:06:59.39#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.259.08:06:59.39#ibcon#about to clear, iclass 3 cls_cnt 0 2006.259.08:06:59.39#ibcon#cleared, iclass 3 cls_cnt 0 2006.259.08:06:59.39$vc4f8/va=3,8 2006.259.08:06:59.39#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.259.08:06:59.39#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.259.08:06:59.39#ibcon#ireg 11 cls_cnt 2 2006.259.08:06:59.39#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.259.08:06:59.45#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.259.08:06:59.45#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.259.08:06:59.45#ibcon#enter wrdev, iclass 5, count 2 2006.259.08:06:59.45#ibcon#first serial, iclass 5, count 2 2006.259.08:06:59.45#ibcon#enter sib2, iclass 5, count 2 2006.259.08:06:59.45#ibcon#flushed, iclass 5, count 2 2006.259.08:06:59.45#ibcon#about to write, iclass 5, count 2 2006.259.08:06:59.45#ibcon#wrote, iclass 5, count 2 2006.259.08:06:59.45#ibcon#about to read 3, iclass 5, count 2 2006.259.08:06:59.48#ibcon#read 3, iclass 5, count 2 2006.259.08:06:59.48#ibcon#about to read 4, iclass 5, count 2 2006.259.08:06:59.48#ibcon#read 4, iclass 5, count 2 2006.259.08:06:59.48#ibcon#about to read 5, iclass 5, count 2 2006.259.08:06:59.48#ibcon#read 5, iclass 5, count 2 2006.259.08:06:59.48#ibcon#about to read 6, iclass 5, count 2 2006.259.08:06:59.48#ibcon#read 6, iclass 5, count 2 2006.259.08:06:59.48#ibcon#end of sib2, iclass 5, count 2 2006.259.08:06:59.48#ibcon#*mode == 0, iclass 5, count 2 2006.259.08:06:59.48#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.259.08:06:59.48#ibcon#[25=AT03-08\r\n] 2006.259.08:06:59.48#ibcon#*before write, iclass 5, count 2 2006.259.08:06:59.48#ibcon#enter sib2, iclass 5, count 2 2006.259.08:06:59.48#ibcon#flushed, iclass 5, count 2 2006.259.08:06:59.48#ibcon#about to write, iclass 5, count 2 2006.259.08:06:59.48#ibcon#wrote, iclass 5, count 2 2006.259.08:06:59.48#ibcon#about to read 3, iclass 5, count 2 2006.259.08:06:59.51#ibcon#read 3, iclass 5, count 2 2006.259.08:06:59.51#ibcon#about to read 4, iclass 5, count 2 2006.259.08:06:59.51#ibcon#read 4, iclass 5, count 2 2006.259.08:06:59.51#ibcon#about to read 5, iclass 5, count 2 2006.259.08:06:59.51#ibcon#read 5, iclass 5, count 2 2006.259.08:06:59.51#ibcon#about to read 6, iclass 5, count 2 2006.259.08:06:59.51#ibcon#read 6, iclass 5, count 2 2006.259.08:06:59.51#ibcon#end of sib2, iclass 5, count 2 2006.259.08:06:59.51#ibcon#*after write, iclass 5, count 2 2006.259.08:06:59.51#ibcon#*before return 0, iclass 5, count 2 2006.259.08:06:59.51#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.259.08:06:59.51#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.259.08:06:59.51#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.259.08:06:59.51#ibcon#ireg 7 cls_cnt 0 2006.259.08:06:59.51#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.259.08:06:59.63#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.259.08:06:59.63#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.259.08:06:59.63#ibcon#enter wrdev, iclass 5, count 0 2006.259.08:06:59.63#ibcon#first serial, iclass 5, count 0 2006.259.08:06:59.63#ibcon#enter sib2, iclass 5, count 0 2006.259.08:06:59.63#ibcon#flushed, iclass 5, count 0 2006.259.08:06:59.63#ibcon#about to write, iclass 5, count 0 2006.259.08:06:59.63#ibcon#wrote, iclass 5, count 0 2006.259.08:06:59.63#ibcon#about to read 3, iclass 5, count 0 2006.259.08:06:59.65#ibcon#read 3, iclass 5, count 0 2006.259.08:06:59.65#ibcon#about to read 4, iclass 5, count 0 2006.259.08:06:59.65#ibcon#read 4, iclass 5, count 0 2006.259.08:06:59.65#ibcon#about to read 5, iclass 5, count 0 2006.259.08:06:59.65#ibcon#read 5, iclass 5, count 0 2006.259.08:06:59.65#ibcon#about to read 6, iclass 5, count 0 2006.259.08:06:59.65#ibcon#read 6, iclass 5, count 0 2006.259.08:06:59.65#ibcon#end of sib2, iclass 5, count 0 2006.259.08:06:59.65#ibcon#*mode == 0, iclass 5, count 0 2006.259.08:06:59.65#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.259.08:06:59.65#ibcon#[25=USB\r\n] 2006.259.08:06:59.65#ibcon#*before write, iclass 5, count 0 2006.259.08:06:59.65#ibcon#enter sib2, iclass 5, count 0 2006.259.08:06:59.65#ibcon#flushed, iclass 5, count 0 2006.259.08:06:59.65#ibcon#about to write, iclass 5, count 0 2006.259.08:06:59.65#ibcon#wrote, iclass 5, count 0 2006.259.08:06:59.65#ibcon#about to read 3, iclass 5, count 0 2006.259.08:06:59.68#ibcon#read 3, iclass 5, count 0 2006.259.08:06:59.68#ibcon#about to read 4, iclass 5, count 0 2006.259.08:06:59.68#ibcon#read 4, iclass 5, count 0 2006.259.08:06:59.68#ibcon#about to read 5, iclass 5, count 0 2006.259.08:06:59.68#ibcon#read 5, iclass 5, count 0 2006.259.08:06:59.68#ibcon#about to read 6, iclass 5, count 0 2006.259.08:06:59.68#ibcon#read 6, iclass 5, count 0 2006.259.08:06:59.68#ibcon#end of sib2, iclass 5, count 0 2006.259.08:06:59.68#ibcon#*after write, iclass 5, count 0 2006.259.08:06:59.68#ibcon#*before return 0, iclass 5, count 0 2006.259.08:06:59.68#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.259.08:06:59.68#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.259.08:06:59.68#ibcon#about to clear, iclass 5 cls_cnt 0 2006.259.08:06:59.68#ibcon#cleared, iclass 5 cls_cnt 0 2006.259.08:06:59.68$vc4f8/valo=4,832.99 2006.259.08:06:59.68#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.259.08:06:59.68#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.259.08:06:59.68#ibcon#ireg 17 cls_cnt 0 2006.259.08:06:59.68#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.259.08:06:59.68#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.259.08:06:59.68#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.259.08:06:59.68#ibcon#enter wrdev, iclass 7, count 0 2006.259.08:06:59.68#ibcon#first serial, iclass 7, count 0 2006.259.08:06:59.68#ibcon#enter sib2, iclass 7, count 0 2006.259.08:06:59.68#ibcon#flushed, iclass 7, count 0 2006.259.08:06:59.68#ibcon#about to write, iclass 7, count 0 2006.259.08:06:59.68#ibcon#wrote, iclass 7, count 0 2006.259.08:06:59.68#ibcon#about to read 3, iclass 7, count 0 2006.259.08:06:59.70#ibcon#read 3, iclass 7, count 0 2006.259.08:06:59.70#ibcon#about to read 4, iclass 7, count 0 2006.259.08:06:59.70#ibcon#read 4, iclass 7, count 0 2006.259.08:06:59.70#ibcon#about to read 5, iclass 7, count 0 2006.259.08:06:59.70#ibcon#read 5, iclass 7, count 0 2006.259.08:06:59.70#ibcon#about to read 6, iclass 7, count 0 2006.259.08:06:59.70#ibcon#read 6, iclass 7, count 0 2006.259.08:06:59.70#ibcon#end of sib2, iclass 7, count 0 2006.259.08:06:59.70#ibcon#*mode == 0, iclass 7, count 0 2006.259.08:06:59.70#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.259.08:06:59.70#ibcon#[26=FRQ=04,832.99\r\n] 2006.259.08:06:59.70#ibcon#*before write, iclass 7, count 0 2006.259.08:06:59.70#ibcon#enter sib2, iclass 7, count 0 2006.259.08:06:59.70#ibcon#flushed, iclass 7, count 0 2006.259.08:06:59.70#ibcon#about to write, iclass 7, count 0 2006.259.08:06:59.70#ibcon#wrote, iclass 7, count 0 2006.259.08:06:59.70#ibcon#about to read 3, iclass 7, count 0 2006.259.08:06:59.74#ibcon#read 3, iclass 7, count 0 2006.259.08:06:59.74#ibcon#about to read 4, iclass 7, count 0 2006.259.08:06:59.74#ibcon#read 4, iclass 7, count 0 2006.259.08:06:59.74#ibcon#about to read 5, iclass 7, count 0 2006.259.08:06:59.74#ibcon#read 5, iclass 7, count 0 2006.259.08:06:59.74#ibcon#about to read 6, iclass 7, count 0 2006.259.08:06:59.74#ibcon#read 6, iclass 7, count 0 2006.259.08:06:59.74#ibcon#end of sib2, iclass 7, count 0 2006.259.08:06:59.74#ibcon#*after write, iclass 7, count 0 2006.259.08:06:59.74#ibcon#*before return 0, iclass 7, count 0 2006.259.08:06:59.74#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.259.08:06:59.74#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.259.08:06:59.74#ibcon#about to clear, iclass 7 cls_cnt 0 2006.259.08:06:59.74#ibcon#cleared, iclass 7 cls_cnt 0 2006.259.08:06:59.74$vc4f8/va=4,7 2006.259.08:06:59.74#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.259.08:06:59.74#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.259.08:06:59.74#ibcon#ireg 11 cls_cnt 2 2006.259.08:06:59.74#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.259.08:06:59.80#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.259.08:06:59.80#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.259.08:06:59.80#ibcon#enter wrdev, iclass 11, count 2 2006.259.08:06:59.80#ibcon#first serial, iclass 11, count 2 2006.259.08:06:59.80#ibcon#enter sib2, iclass 11, count 2 2006.259.08:06:59.80#ibcon#flushed, iclass 11, count 2 2006.259.08:06:59.80#ibcon#about to write, iclass 11, count 2 2006.259.08:06:59.80#ibcon#wrote, iclass 11, count 2 2006.259.08:06:59.80#ibcon#about to read 3, iclass 11, count 2 2006.259.08:06:59.82#ibcon#read 3, iclass 11, count 2 2006.259.08:06:59.82#ibcon#about to read 4, iclass 11, count 2 2006.259.08:06:59.82#ibcon#read 4, iclass 11, count 2 2006.259.08:06:59.82#ibcon#about to read 5, iclass 11, count 2 2006.259.08:06:59.82#ibcon#read 5, iclass 11, count 2 2006.259.08:06:59.82#ibcon#about to read 6, iclass 11, count 2 2006.259.08:06:59.82#ibcon#read 6, iclass 11, count 2 2006.259.08:06:59.82#ibcon#end of sib2, iclass 11, count 2 2006.259.08:06:59.82#ibcon#*mode == 0, iclass 11, count 2 2006.259.08:06:59.82#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.259.08:06:59.82#ibcon#[25=AT04-07\r\n] 2006.259.08:06:59.82#ibcon#*before write, iclass 11, count 2 2006.259.08:06:59.82#ibcon#enter sib2, iclass 11, count 2 2006.259.08:06:59.82#ibcon#flushed, iclass 11, count 2 2006.259.08:06:59.82#ibcon#about to write, iclass 11, count 2 2006.259.08:06:59.82#ibcon#wrote, iclass 11, count 2 2006.259.08:06:59.82#ibcon#about to read 3, iclass 11, count 2 2006.259.08:06:59.85#ibcon#read 3, iclass 11, count 2 2006.259.08:06:59.85#ibcon#about to read 4, iclass 11, count 2 2006.259.08:06:59.85#ibcon#read 4, iclass 11, count 2 2006.259.08:06:59.85#ibcon#about to read 5, iclass 11, count 2 2006.259.08:06:59.85#ibcon#read 5, iclass 11, count 2 2006.259.08:06:59.85#ibcon#about to read 6, iclass 11, count 2 2006.259.08:06:59.85#ibcon#read 6, iclass 11, count 2 2006.259.08:06:59.85#ibcon#end of sib2, iclass 11, count 2 2006.259.08:06:59.85#ibcon#*after write, iclass 11, count 2 2006.259.08:06:59.85#ibcon#*before return 0, iclass 11, count 2 2006.259.08:06:59.85#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.259.08:06:59.85#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.259.08:06:59.85#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.259.08:06:59.85#ibcon#ireg 7 cls_cnt 0 2006.259.08:06:59.85#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.259.08:06:59.97#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.259.08:06:59.97#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.259.08:06:59.97#ibcon#enter wrdev, iclass 11, count 0 2006.259.08:06:59.97#ibcon#first serial, iclass 11, count 0 2006.259.08:06:59.97#ibcon#enter sib2, iclass 11, count 0 2006.259.08:06:59.97#ibcon#flushed, iclass 11, count 0 2006.259.08:06:59.97#ibcon#about to write, iclass 11, count 0 2006.259.08:06:59.97#ibcon#wrote, iclass 11, count 0 2006.259.08:06:59.97#ibcon#about to read 3, iclass 11, count 0 2006.259.08:06:59.99#ibcon#read 3, iclass 11, count 0 2006.259.08:06:59.99#ibcon#about to read 4, iclass 11, count 0 2006.259.08:06:59.99#ibcon#read 4, iclass 11, count 0 2006.259.08:06:59.99#ibcon#about to read 5, iclass 11, count 0 2006.259.08:06:59.99#ibcon#read 5, iclass 11, count 0 2006.259.08:06:59.99#ibcon#about to read 6, iclass 11, count 0 2006.259.08:06:59.99#ibcon#read 6, iclass 11, count 0 2006.259.08:06:59.99#ibcon#end of sib2, iclass 11, count 0 2006.259.08:06:59.99#ibcon#*mode == 0, iclass 11, count 0 2006.259.08:06:59.99#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.259.08:06:59.99#ibcon#[25=USB\r\n] 2006.259.08:06:59.99#ibcon#*before write, iclass 11, count 0 2006.259.08:06:59.99#ibcon#enter sib2, iclass 11, count 0 2006.259.08:06:59.99#ibcon#flushed, iclass 11, count 0 2006.259.08:06:59.99#ibcon#about to write, iclass 11, count 0 2006.259.08:06:59.99#ibcon#wrote, iclass 11, count 0 2006.259.08:06:59.99#ibcon#about to read 3, iclass 11, count 0 2006.259.08:07:00.02#ibcon#read 3, iclass 11, count 0 2006.259.08:07:00.02#ibcon#about to read 4, iclass 11, count 0 2006.259.08:07:00.02#ibcon#read 4, iclass 11, count 0 2006.259.08:07:00.02#ibcon#about to read 5, iclass 11, count 0 2006.259.08:07:00.02#ibcon#read 5, iclass 11, count 0 2006.259.08:07:00.02#ibcon#about to read 6, iclass 11, count 0 2006.259.08:07:00.02#ibcon#read 6, iclass 11, count 0 2006.259.08:07:00.02#ibcon#end of sib2, iclass 11, count 0 2006.259.08:07:00.02#ibcon#*after write, iclass 11, count 0 2006.259.08:07:00.02#ibcon#*before return 0, iclass 11, count 0 2006.259.08:07:00.02#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.259.08:07:00.02#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.259.08:07:00.02#ibcon#about to clear, iclass 11 cls_cnt 0 2006.259.08:07:00.02#ibcon#cleared, iclass 11 cls_cnt 0 2006.259.08:07:00.02$vc4f8/valo=5,652.99 2006.259.08:07:00.02#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.259.08:07:00.02#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.259.08:07:00.02#ibcon#ireg 17 cls_cnt 0 2006.259.08:07:00.02#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.259.08:07:00.02#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.259.08:07:00.02#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.259.08:07:00.02#ibcon#enter wrdev, iclass 13, count 0 2006.259.08:07:00.02#ibcon#first serial, iclass 13, count 0 2006.259.08:07:00.02#ibcon#enter sib2, iclass 13, count 0 2006.259.08:07:00.02#ibcon#flushed, iclass 13, count 0 2006.259.08:07:00.02#ibcon#about to write, iclass 13, count 0 2006.259.08:07:00.02#ibcon#wrote, iclass 13, count 0 2006.259.08:07:00.02#ibcon#about to read 3, iclass 13, count 0 2006.259.08:07:00.04#ibcon#read 3, iclass 13, count 0 2006.259.08:07:00.04#ibcon#about to read 4, iclass 13, count 0 2006.259.08:07:00.04#ibcon#read 4, iclass 13, count 0 2006.259.08:07:00.04#ibcon#about to read 5, iclass 13, count 0 2006.259.08:07:00.04#ibcon#read 5, iclass 13, count 0 2006.259.08:07:00.04#ibcon#about to read 6, iclass 13, count 0 2006.259.08:07:00.04#ibcon#read 6, iclass 13, count 0 2006.259.08:07:00.04#ibcon#end of sib2, iclass 13, count 0 2006.259.08:07:00.04#ibcon#*mode == 0, iclass 13, count 0 2006.259.08:07:00.04#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.259.08:07:00.04#ibcon#[26=FRQ=05,652.99\r\n] 2006.259.08:07:00.04#ibcon#*before write, iclass 13, count 0 2006.259.08:07:00.04#ibcon#enter sib2, iclass 13, count 0 2006.259.08:07:00.04#ibcon#flushed, iclass 13, count 0 2006.259.08:07:00.04#ibcon#about to write, iclass 13, count 0 2006.259.08:07:00.04#ibcon#wrote, iclass 13, count 0 2006.259.08:07:00.04#ibcon#about to read 3, iclass 13, count 0 2006.259.08:07:00.08#ibcon#read 3, iclass 13, count 0 2006.259.08:07:00.08#ibcon#about to read 4, iclass 13, count 0 2006.259.08:07:00.08#ibcon#read 4, iclass 13, count 0 2006.259.08:07:00.08#ibcon#about to read 5, iclass 13, count 0 2006.259.08:07:00.08#ibcon#read 5, iclass 13, count 0 2006.259.08:07:00.08#ibcon#about to read 6, iclass 13, count 0 2006.259.08:07:00.08#ibcon#read 6, iclass 13, count 0 2006.259.08:07:00.08#ibcon#end of sib2, iclass 13, count 0 2006.259.08:07:00.08#ibcon#*after write, iclass 13, count 0 2006.259.08:07:00.08#ibcon#*before return 0, iclass 13, count 0 2006.259.08:07:00.08#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.259.08:07:00.08#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.259.08:07:00.08#ibcon#about to clear, iclass 13 cls_cnt 0 2006.259.08:07:00.08#ibcon#cleared, iclass 13 cls_cnt 0 2006.259.08:07:00.08$vc4f8/va=5,7 2006.259.08:07:00.08#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.259.08:07:00.08#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.259.08:07:00.08#ibcon#ireg 11 cls_cnt 2 2006.259.08:07:00.08#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.259.08:07:00.14#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.259.08:07:00.14#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.259.08:07:00.14#ibcon#enter wrdev, iclass 15, count 2 2006.259.08:07:00.14#ibcon#first serial, iclass 15, count 2 2006.259.08:07:00.14#ibcon#enter sib2, iclass 15, count 2 2006.259.08:07:00.14#ibcon#flushed, iclass 15, count 2 2006.259.08:07:00.14#ibcon#about to write, iclass 15, count 2 2006.259.08:07:00.14#ibcon#wrote, iclass 15, count 2 2006.259.08:07:00.14#ibcon#about to read 3, iclass 15, count 2 2006.259.08:07:00.16#ibcon#read 3, iclass 15, count 2 2006.259.08:07:00.16#ibcon#about to read 4, iclass 15, count 2 2006.259.08:07:00.16#ibcon#read 4, iclass 15, count 2 2006.259.08:07:00.16#ibcon#about to read 5, iclass 15, count 2 2006.259.08:07:00.16#ibcon#read 5, iclass 15, count 2 2006.259.08:07:00.16#ibcon#about to read 6, iclass 15, count 2 2006.259.08:07:00.16#ibcon#read 6, iclass 15, count 2 2006.259.08:07:00.16#ibcon#end of sib2, iclass 15, count 2 2006.259.08:07:00.16#ibcon#*mode == 0, iclass 15, count 2 2006.259.08:07:00.16#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.259.08:07:00.16#ibcon#[25=AT05-07\r\n] 2006.259.08:07:00.16#ibcon#*before write, iclass 15, count 2 2006.259.08:07:00.16#ibcon#enter sib2, iclass 15, count 2 2006.259.08:07:00.16#ibcon#flushed, iclass 15, count 2 2006.259.08:07:00.16#ibcon#about to write, iclass 15, count 2 2006.259.08:07:00.16#ibcon#wrote, iclass 15, count 2 2006.259.08:07:00.16#ibcon#about to read 3, iclass 15, count 2 2006.259.08:07:00.19#ibcon#read 3, iclass 15, count 2 2006.259.08:07:00.19#ibcon#about to read 4, iclass 15, count 2 2006.259.08:07:00.19#ibcon#read 4, iclass 15, count 2 2006.259.08:07:00.19#ibcon#about to read 5, iclass 15, count 2 2006.259.08:07:00.19#ibcon#read 5, iclass 15, count 2 2006.259.08:07:00.19#ibcon#about to read 6, iclass 15, count 2 2006.259.08:07:00.19#ibcon#read 6, iclass 15, count 2 2006.259.08:07:00.19#ibcon#end of sib2, iclass 15, count 2 2006.259.08:07:00.19#ibcon#*after write, iclass 15, count 2 2006.259.08:07:00.19#ibcon#*before return 0, iclass 15, count 2 2006.259.08:07:00.19#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.259.08:07:00.19#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.259.08:07:00.19#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.259.08:07:00.19#ibcon#ireg 7 cls_cnt 0 2006.259.08:07:00.19#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.259.08:07:00.31#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.259.08:07:00.31#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.259.08:07:00.31#ibcon#enter wrdev, iclass 15, count 0 2006.259.08:07:00.31#ibcon#first serial, iclass 15, count 0 2006.259.08:07:00.31#ibcon#enter sib2, iclass 15, count 0 2006.259.08:07:00.31#ibcon#flushed, iclass 15, count 0 2006.259.08:07:00.31#ibcon#about to write, iclass 15, count 0 2006.259.08:07:00.31#ibcon#wrote, iclass 15, count 0 2006.259.08:07:00.31#ibcon#about to read 3, iclass 15, count 0 2006.259.08:07:00.33#ibcon#read 3, iclass 15, count 0 2006.259.08:07:00.33#ibcon#about to read 4, iclass 15, count 0 2006.259.08:07:00.33#ibcon#read 4, iclass 15, count 0 2006.259.08:07:00.33#ibcon#about to read 5, iclass 15, count 0 2006.259.08:07:00.33#ibcon#read 5, iclass 15, count 0 2006.259.08:07:00.33#ibcon#about to read 6, iclass 15, count 0 2006.259.08:07:00.33#ibcon#read 6, iclass 15, count 0 2006.259.08:07:00.33#ibcon#end of sib2, iclass 15, count 0 2006.259.08:07:00.33#ibcon#*mode == 0, iclass 15, count 0 2006.259.08:07:00.33#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.259.08:07:00.33#ibcon#[25=USB\r\n] 2006.259.08:07:00.33#ibcon#*before write, iclass 15, count 0 2006.259.08:07:00.33#ibcon#enter sib2, iclass 15, count 0 2006.259.08:07:00.33#ibcon#flushed, iclass 15, count 0 2006.259.08:07:00.33#ibcon#about to write, iclass 15, count 0 2006.259.08:07:00.33#ibcon#wrote, iclass 15, count 0 2006.259.08:07:00.33#ibcon#about to read 3, iclass 15, count 0 2006.259.08:07:00.36#ibcon#read 3, iclass 15, count 0 2006.259.08:07:00.36#ibcon#about to read 4, iclass 15, count 0 2006.259.08:07:00.36#ibcon#read 4, iclass 15, count 0 2006.259.08:07:00.36#ibcon#about to read 5, iclass 15, count 0 2006.259.08:07:00.36#ibcon#read 5, iclass 15, count 0 2006.259.08:07:00.36#ibcon#about to read 6, iclass 15, count 0 2006.259.08:07:00.36#ibcon#read 6, iclass 15, count 0 2006.259.08:07:00.36#ibcon#end of sib2, iclass 15, count 0 2006.259.08:07:00.36#ibcon#*after write, iclass 15, count 0 2006.259.08:07:00.36#ibcon#*before return 0, iclass 15, count 0 2006.259.08:07:00.36#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.259.08:07:00.36#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.259.08:07:00.36#ibcon#about to clear, iclass 15 cls_cnt 0 2006.259.08:07:00.36#ibcon#cleared, iclass 15 cls_cnt 0 2006.259.08:07:00.36$vc4f8/valo=6,772.99 2006.259.08:07:00.36#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.259.08:07:00.36#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.259.08:07:00.36#ibcon#ireg 17 cls_cnt 0 2006.259.08:07:00.36#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.259.08:07:00.36#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.259.08:07:00.36#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.259.08:07:00.36#ibcon#enter wrdev, iclass 17, count 0 2006.259.08:07:00.36#ibcon#first serial, iclass 17, count 0 2006.259.08:07:00.36#ibcon#enter sib2, iclass 17, count 0 2006.259.08:07:00.36#ibcon#flushed, iclass 17, count 0 2006.259.08:07:00.36#ibcon#about to write, iclass 17, count 0 2006.259.08:07:00.36#ibcon#wrote, iclass 17, count 0 2006.259.08:07:00.36#ibcon#about to read 3, iclass 17, count 0 2006.259.08:07:00.38#ibcon#read 3, iclass 17, count 0 2006.259.08:07:00.38#ibcon#about to read 4, iclass 17, count 0 2006.259.08:07:00.38#ibcon#read 4, iclass 17, count 0 2006.259.08:07:00.38#ibcon#about to read 5, iclass 17, count 0 2006.259.08:07:00.38#ibcon#read 5, iclass 17, count 0 2006.259.08:07:00.38#ibcon#about to read 6, iclass 17, count 0 2006.259.08:07:00.38#ibcon#read 6, iclass 17, count 0 2006.259.08:07:00.38#ibcon#end of sib2, iclass 17, count 0 2006.259.08:07:00.38#ibcon#*mode == 0, iclass 17, count 0 2006.259.08:07:00.38#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.259.08:07:00.38#ibcon#[26=FRQ=06,772.99\r\n] 2006.259.08:07:00.38#ibcon#*before write, iclass 17, count 0 2006.259.08:07:00.38#ibcon#enter sib2, iclass 17, count 0 2006.259.08:07:00.38#ibcon#flushed, iclass 17, count 0 2006.259.08:07:00.38#ibcon#about to write, iclass 17, count 0 2006.259.08:07:00.38#ibcon#wrote, iclass 17, count 0 2006.259.08:07:00.38#ibcon#about to read 3, iclass 17, count 0 2006.259.08:07:00.42#ibcon#read 3, iclass 17, count 0 2006.259.08:07:00.42#ibcon#about to read 4, iclass 17, count 0 2006.259.08:07:00.42#ibcon#read 4, iclass 17, count 0 2006.259.08:07:00.42#ibcon#about to read 5, iclass 17, count 0 2006.259.08:07:00.42#ibcon#read 5, iclass 17, count 0 2006.259.08:07:00.42#ibcon#about to read 6, iclass 17, count 0 2006.259.08:07:00.42#ibcon#read 6, iclass 17, count 0 2006.259.08:07:00.42#ibcon#end of sib2, iclass 17, count 0 2006.259.08:07:00.42#ibcon#*after write, iclass 17, count 0 2006.259.08:07:00.42#ibcon#*before return 0, iclass 17, count 0 2006.259.08:07:00.42#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.259.08:07:00.42#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.259.08:07:00.42#ibcon#about to clear, iclass 17 cls_cnt 0 2006.259.08:07:00.42#ibcon#cleared, iclass 17 cls_cnt 0 2006.259.08:07:00.42$vc4f8/va=6,6 2006.259.08:07:00.42#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.259.08:07:00.42#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.259.08:07:00.42#ibcon#ireg 11 cls_cnt 2 2006.259.08:07:00.42#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.259.08:07:00.48#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.259.08:07:00.48#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.259.08:07:00.48#ibcon#enter wrdev, iclass 19, count 2 2006.259.08:07:00.48#ibcon#first serial, iclass 19, count 2 2006.259.08:07:00.48#ibcon#enter sib2, iclass 19, count 2 2006.259.08:07:00.48#ibcon#flushed, iclass 19, count 2 2006.259.08:07:00.48#ibcon#about to write, iclass 19, count 2 2006.259.08:07:00.48#ibcon#wrote, iclass 19, count 2 2006.259.08:07:00.48#ibcon#about to read 3, iclass 19, count 2 2006.259.08:07:00.50#ibcon#read 3, iclass 19, count 2 2006.259.08:07:00.50#ibcon#about to read 4, iclass 19, count 2 2006.259.08:07:00.50#ibcon#read 4, iclass 19, count 2 2006.259.08:07:00.50#ibcon#about to read 5, iclass 19, count 2 2006.259.08:07:00.50#ibcon#read 5, iclass 19, count 2 2006.259.08:07:00.50#ibcon#about to read 6, iclass 19, count 2 2006.259.08:07:00.50#ibcon#read 6, iclass 19, count 2 2006.259.08:07:00.50#ibcon#end of sib2, iclass 19, count 2 2006.259.08:07:00.50#ibcon#*mode == 0, iclass 19, count 2 2006.259.08:07:00.50#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.259.08:07:00.50#ibcon#[25=AT06-06\r\n] 2006.259.08:07:00.50#ibcon#*before write, iclass 19, count 2 2006.259.08:07:00.50#ibcon#enter sib2, iclass 19, count 2 2006.259.08:07:00.50#ibcon#flushed, iclass 19, count 2 2006.259.08:07:00.50#ibcon#about to write, iclass 19, count 2 2006.259.08:07:00.50#ibcon#wrote, iclass 19, count 2 2006.259.08:07:00.50#ibcon#about to read 3, iclass 19, count 2 2006.259.08:07:00.53#ibcon#read 3, iclass 19, count 2 2006.259.08:07:00.53#ibcon#about to read 4, iclass 19, count 2 2006.259.08:07:00.53#ibcon#read 4, iclass 19, count 2 2006.259.08:07:00.53#ibcon#about to read 5, iclass 19, count 2 2006.259.08:07:00.53#ibcon#read 5, iclass 19, count 2 2006.259.08:07:00.53#ibcon#about to read 6, iclass 19, count 2 2006.259.08:07:00.53#ibcon#read 6, iclass 19, count 2 2006.259.08:07:00.53#ibcon#end of sib2, iclass 19, count 2 2006.259.08:07:00.53#ibcon#*after write, iclass 19, count 2 2006.259.08:07:00.53#ibcon#*before return 0, iclass 19, count 2 2006.259.08:07:00.53#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.259.08:07:00.53#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.259.08:07:00.53#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.259.08:07:00.53#ibcon#ireg 7 cls_cnt 0 2006.259.08:07:00.53#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.259.08:07:00.65#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.259.08:07:00.65#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.259.08:07:00.65#ibcon#enter wrdev, iclass 19, count 0 2006.259.08:07:00.65#ibcon#first serial, iclass 19, count 0 2006.259.08:07:00.65#ibcon#enter sib2, iclass 19, count 0 2006.259.08:07:00.65#ibcon#flushed, iclass 19, count 0 2006.259.08:07:00.65#ibcon#about to write, iclass 19, count 0 2006.259.08:07:00.65#ibcon#wrote, iclass 19, count 0 2006.259.08:07:00.65#ibcon#about to read 3, iclass 19, count 0 2006.259.08:07:00.67#ibcon#read 3, iclass 19, count 0 2006.259.08:07:00.67#ibcon#about to read 4, iclass 19, count 0 2006.259.08:07:00.67#ibcon#read 4, iclass 19, count 0 2006.259.08:07:00.67#ibcon#about to read 5, iclass 19, count 0 2006.259.08:07:00.67#ibcon#read 5, iclass 19, count 0 2006.259.08:07:00.67#ibcon#about to read 6, iclass 19, count 0 2006.259.08:07:00.67#ibcon#read 6, iclass 19, count 0 2006.259.08:07:00.67#ibcon#end of sib2, iclass 19, count 0 2006.259.08:07:00.67#ibcon#*mode == 0, iclass 19, count 0 2006.259.08:07:00.67#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.259.08:07:00.67#ibcon#[25=USB\r\n] 2006.259.08:07:00.67#ibcon#*before write, iclass 19, count 0 2006.259.08:07:00.67#ibcon#enter sib2, iclass 19, count 0 2006.259.08:07:00.67#ibcon#flushed, iclass 19, count 0 2006.259.08:07:00.67#ibcon#about to write, iclass 19, count 0 2006.259.08:07:00.67#ibcon#wrote, iclass 19, count 0 2006.259.08:07:00.67#ibcon#about to read 3, iclass 19, count 0 2006.259.08:07:00.70#ibcon#read 3, iclass 19, count 0 2006.259.08:07:00.70#ibcon#about to read 4, iclass 19, count 0 2006.259.08:07:00.70#ibcon#read 4, iclass 19, count 0 2006.259.08:07:00.70#ibcon#about to read 5, iclass 19, count 0 2006.259.08:07:00.70#ibcon#read 5, iclass 19, count 0 2006.259.08:07:00.70#ibcon#about to read 6, iclass 19, count 0 2006.259.08:07:00.70#ibcon#read 6, iclass 19, count 0 2006.259.08:07:00.70#ibcon#end of sib2, iclass 19, count 0 2006.259.08:07:00.70#ibcon#*after write, iclass 19, count 0 2006.259.08:07:00.70#ibcon#*before return 0, iclass 19, count 0 2006.259.08:07:00.70#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.259.08:07:00.70#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.259.08:07:00.70#ibcon#about to clear, iclass 19 cls_cnt 0 2006.259.08:07:00.70#ibcon#cleared, iclass 19 cls_cnt 0 2006.259.08:07:00.70$vc4f8/valo=7,832.99 2006.259.08:07:00.70#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.259.08:07:00.70#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.259.08:07:00.70#ibcon#ireg 17 cls_cnt 0 2006.259.08:07:00.70#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.259.08:07:00.70#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.259.08:07:00.70#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.259.08:07:00.70#ibcon#enter wrdev, iclass 21, count 0 2006.259.08:07:00.70#ibcon#first serial, iclass 21, count 0 2006.259.08:07:00.70#ibcon#enter sib2, iclass 21, count 0 2006.259.08:07:00.70#ibcon#flushed, iclass 21, count 0 2006.259.08:07:00.70#ibcon#about to write, iclass 21, count 0 2006.259.08:07:00.70#ibcon#wrote, iclass 21, count 0 2006.259.08:07:00.70#ibcon#about to read 3, iclass 21, count 0 2006.259.08:07:00.72#ibcon#read 3, iclass 21, count 0 2006.259.08:07:00.72#ibcon#about to read 4, iclass 21, count 0 2006.259.08:07:00.72#ibcon#read 4, iclass 21, count 0 2006.259.08:07:00.72#ibcon#about to read 5, iclass 21, count 0 2006.259.08:07:00.72#ibcon#read 5, iclass 21, count 0 2006.259.08:07:00.72#ibcon#about to read 6, iclass 21, count 0 2006.259.08:07:00.72#ibcon#read 6, iclass 21, count 0 2006.259.08:07:00.72#ibcon#end of sib2, iclass 21, count 0 2006.259.08:07:00.72#ibcon#*mode == 0, iclass 21, count 0 2006.259.08:07:00.72#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.259.08:07:00.72#ibcon#[26=FRQ=07,832.99\r\n] 2006.259.08:07:00.72#ibcon#*before write, iclass 21, count 0 2006.259.08:07:00.72#ibcon#enter sib2, iclass 21, count 0 2006.259.08:07:00.72#ibcon#flushed, iclass 21, count 0 2006.259.08:07:00.72#ibcon#about to write, iclass 21, count 0 2006.259.08:07:00.72#ibcon#wrote, iclass 21, count 0 2006.259.08:07:00.72#ibcon#about to read 3, iclass 21, count 0 2006.259.08:07:00.76#ibcon#read 3, iclass 21, count 0 2006.259.08:07:00.76#ibcon#about to read 4, iclass 21, count 0 2006.259.08:07:00.76#ibcon#read 4, iclass 21, count 0 2006.259.08:07:00.76#ibcon#about to read 5, iclass 21, count 0 2006.259.08:07:00.76#ibcon#read 5, iclass 21, count 0 2006.259.08:07:00.76#ibcon#about to read 6, iclass 21, count 0 2006.259.08:07:00.76#ibcon#read 6, iclass 21, count 0 2006.259.08:07:00.76#ibcon#end of sib2, iclass 21, count 0 2006.259.08:07:00.76#ibcon#*after write, iclass 21, count 0 2006.259.08:07:00.76#ibcon#*before return 0, iclass 21, count 0 2006.259.08:07:00.76#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.259.08:07:00.76#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.259.08:07:00.76#ibcon#about to clear, iclass 21 cls_cnt 0 2006.259.08:07:00.76#ibcon#cleared, iclass 21 cls_cnt 0 2006.259.08:07:00.76$vc4f8/va=7,6 2006.259.08:07:00.76#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.259.08:07:00.76#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.259.08:07:00.76#ibcon#ireg 11 cls_cnt 2 2006.259.08:07:00.76#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.259.08:07:00.82#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.259.08:07:00.82#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.259.08:07:00.82#ibcon#enter wrdev, iclass 23, count 2 2006.259.08:07:00.82#ibcon#first serial, iclass 23, count 2 2006.259.08:07:00.82#ibcon#enter sib2, iclass 23, count 2 2006.259.08:07:00.82#ibcon#flushed, iclass 23, count 2 2006.259.08:07:00.82#ibcon#about to write, iclass 23, count 2 2006.259.08:07:00.82#ibcon#wrote, iclass 23, count 2 2006.259.08:07:00.82#ibcon#about to read 3, iclass 23, count 2 2006.259.08:07:00.84#ibcon#read 3, iclass 23, count 2 2006.259.08:07:00.84#ibcon#about to read 4, iclass 23, count 2 2006.259.08:07:00.84#ibcon#read 4, iclass 23, count 2 2006.259.08:07:00.84#ibcon#about to read 5, iclass 23, count 2 2006.259.08:07:00.84#ibcon#read 5, iclass 23, count 2 2006.259.08:07:00.84#ibcon#about to read 6, iclass 23, count 2 2006.259.08:07:00.84#ibcon#read 6, iclass 23, count 2 2006.259.08:07:00.84#ibcon#end of sib2, iclass 23, count 2 2006.259.08:07:00.84#ibcon#*mode == 0, iclass 23, count 2 2006.259.08:07:00.84#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.259.08:07:00.84#ibcon#[25=AT07-06\r\n] 2006.259.08:07:00.84#ibcon#*before write, iclass 23, count 2 2006.259.08:07:00.84#ibcon#enter sib2, iclass 23, count 2 2006.259.08:07:00.84#ibcon#flushed, iclass 23, count 2 2006.259.08:07:00.84#ibcon#about to write, iclass 23, count 2 2006.259.08:07:00.84#ibcon#wrote, iclass 23, count 2 2006.259.08:07:00.84#ibcon#about to read 3, iclass 23, count 2 2006.259.08:07:00.87#ibcon#read 3, iclass 23, count 2 2006.259.08:07:00.87#ibcon#about to read 4, iclass 23, count 2 2006.259.08:07:00.87#ibcon#read 4, iclass 23, count 2 2006.259.08:07:00.87#ibcon#about to read 5, iclass 23, count 2 2006.259.08:07:00.87#ibcon#read 5, iclass 23, count 2 2006.259.08:07:00.87#ibcon#about to read 6, iclass 23, count 2 2006.259.08:07:00.87#ibcon#read 6, iclass 23, count 2 2006.259.08:07:00.87#ibcon#end of sib2, iclass 23, count 2 2006.259.08:07:00.87#ibcon#*after write, iclass 23, count 2 2006.259.08:07:00.87#ibcon#*before return 0, iclass 23, count 2 2006.259.08:07:00.87#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.259.08:07:00.87#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.259.08:07:00.87#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.259.08:07:00.87#ibcon#ireg 7 cls_cnt 0 2006.259.08:07:00.87#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.259.08:07:00.99#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.259.08:07:00.99#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.259.08:07:00.99#ibcon#enter wrdev, iclass 23, count 0 2006.259.08:07:00.99#ibcon#first serial, iclass 23, count 0 2006.259.08:07:00.99#ibcon#enter sib2, iclass 23, count 0 2006.259.08:07:00.99#ibcon#flushed, iclass 23, count 0 2006.259.08:07:00.99#ibcon#about to write, iclass 23, count 0 2006.259.08:07:00.99#ibcon#wrote, iclass 23, count 0 2006.259.08:07:00.99#ibcon#about to read 3, iclass 23, count 0 2006.259.08:07:01.01#ibcon#read 3, iclass 23, count 0 2006.259.08:07:01.01#ibcon#about to read 4, iclass 23, count 0 2006.259.08:07:01.01#ibcon#read 4, iclass 23, count 0 2006.259.08:07:01.01#ibcon#about to read 5, iclass 23, count 0 2006.259.08:07:01.01#ibcon#read 5, iclass 23, count 0 2006.259.08:07:01.01#ibcon#about to read 6, iclass 23, count 0 2006.259.08:07:01.01#ibcon#read 6, iclass 23, count 0 2006.259.08:07:01.01#ibcon#end of sib2, iclass 23, count 0 2006.259.08:07:01.01#ibcon#*mode == 0, iclass 23, count 0 2006.259.08:07:01.01#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.259.08:07:01.01#ibcon#[25=USB\r\n] 2006.259.08:07:01.01#ibcon#*before write, iclass 23, count 0 2006.259.08:07:01.01#ibcon#enter sib2, iclass 23, count 0 2006.259.08:07:01.01#ibcon#flushed, iclass 23, count 0 2006.259.08:07:01.01#ibcon#about to write, iclass 23, count 0 2006.259.08:07:01.01#ibcon#wrote, iclass 23, count 0 2006.259.08:07:01.01#ibcon#about to read 3, iclass 23, count 0 2006.259.08:07:01.04#ibcon#read 3, iclass 23, count 0 2006.259.08:07:01.04#ibcon#about to read 4, iclass 23, count 0 2006.259.08:07:01.04#ibcon#read 4, iclass 23, count 0 2006.259.08:07:01.04#ibcon#about to read 5, iclass 23, count 0 2006.259.08:07:01.04#ibcon#read 5, iclass 23, count 0 2006.259.08:07:01.04#ibcon#about to read 6, iclass 23, count 0 2006.259.08:07:01.04#ibcon#read 6, iclass 23, count 0 2006.259.08:07:01.04#ibcon#end of sib2, iclass 23, count 0 2006.259.08:07:01.04#ibcon#*after write, iclass 23, count 0 2006.259.08:07:01.04#ibcon#*before return 0, iclass 23, count 0 2006.259.08:07:01.04#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.259.08:07:01.04#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.259.08:07:01.04#ibcon#about to clear, iclass 23 cls_cnt 0 2006.259.08:07:01.04#ibcon#cleared, iclass 23 cls_cnt 0 2006.259.08:07:01.04$vc4f8/valo=8,852.99 2006.259.08:07:01.04#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.259.08:07:01.04#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.259.08:07:01.04#ibcon#ireg 17 cls_cnt 0 2006.259.08:07:01.04#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.259.08:07:01.04#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.259.08:07:01.04#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.259.08:07:01.04#ibcon#enter wrdev, iclass 25, count 0 2006.259.08:07:01.04#ibcon#first serial, iclass 25, count 0 2006.259.08:07:01.04#ibcon#enter sib2, iclass 25, count 0 2006.259.08:07:01.04#ibcon#flushed, iclass 25, count 0 2006.259.08:07:01.04#ibcon#about to write, iclass 25, count 0 2006.259.08:07:01.04#ibcon#wrote, iclass 25, count 0 2006.259.08:07:01.04#ibcon#about to read 3, iclass 25, count 0 2006.259.08:07:01.06#ibcon#read 3, iclass 25, count 0 2006.259.08:07:01.06#ibcon#about to read 4, iclass 25, count 0 2006.259.08:07:01.06#ibcon#read 4, iclass 25, count 0 2006.259.08:07:01.06#ibcon#about to read 5, iclass 25, count 0 2006.259.08:07:01.06#ibcon#read 5, iclass 25, count 0 2006.259.08:07:01.06#ibcon#about to read 6, iclass 25, count 0 2006.259.08:07:01.06#ibcon#read 6, iclass 25, count 0 2006.259.08:07:01.06#ibcon#end of sib2, iclass 25, count 0 2006.259.08:07:01.06#ibcon#*mode == 0, iclass 25, count 0 2006.259.08:07:01.06#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.259.08:07:01.06#ibcon#[26=FRQ=08,852.99\r\n] 2006.259.08:07:01.06#ibcon#*before write, iclass 25, count 0 2006.259.08:07:01.06#ibcon#enter sib2, iclass 25, count 0 2006.259.08:07:01.06#ibcon#flushed, iclass 25, count 0 2006.259.08:07:01.06#ibcon#about to write, iclass 25, count 0 2006.259.08:07:01.06#ibcon#wrote, iclass 25, count 0 2006.259.08:07:01.06#ibcon#about to read 3, iclass 25, count 0 2006.259.08:07:01.10#ibcon#read 3, iclass 25, count 0 2006.259.08:07:01.10#ibcon#about to read 4, iclass 25, count 0 2006.259.08:07:01.10#ibcon#read 4, iclass 25, count 0 2006.259.08:07:01.10#ibcon#about to read 5, iclass 25, count 0 2006.259.08:07:01.10#ibcon#read 5, iclass 25, count 0 2006.259.08:07:01.10#ibcon#about to read 6, iclass 25, count 0 2006.259.08:07:01.10#ibcon#read 6, iclass 25, count 0 2006.259.08:07:01.10#ibcon#end of sib2, iclass 25, count 0 2006.259.08:07:01.10#ibcon#*after write, iclass 25, count 0 2006.259.08:07:01.10#ibcon#*before return 0, iclass 25, count 0 2006.259.08:07:01.10#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.259.08:07:01.10#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.259.08:07:01.10#ibcon#about to clear, iclass 25 cls_cnt 0 2006.259.08:07:01.10#ibcon#cleared, iclass 25 cls_cnt 0 2006.259.08:07:01.10$vc4f8/va=8,6 2006.259.08:07:01.10#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.259.08:07:01.10#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.259.08:07:01.10#ibcon#ireg 11 cls_cnt 2 2006.259.08:07:01.10#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.259.08:07:01.16#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.259.08:07:01.16#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.259.08:07:01.16#ibcon#enter wrdev, iclass 27, count 2 2006.259.08:07:01.16#ibcon#first serial, iclass 27, count 2 2006.259.08:07:01.16#ibcon#enter sib2, iclass 27, count 2 2006.259.08:07:01.16#ibcon#flushed, iclass 27, count 2 2006.259.08:07:01.16#ibcon#about to write, iclass 27, count 2 2006.259.08:07:01.16#ibcon#wrote, iclass 27, count 2 2006.259.08:07:01.16#ibcon#about to read 3, iclass 27, count 2 2006.259.08:07:01.18#ibcon#read 3, iclass 27, count 2 2006.259.08:07:01.18#ibcon#about to read 4, iclass 27, count 2 2006.259.08:07:01.18#ibcon#read 4, iclass 27, count 2 2006.259.08:07:01.18#ibcon#about to read 5, iclass 27, count 2 2006.259.08:07:01.18#ibcon#read 5, iclass 27, count 2 2006.259.08:07:01.18#ibcon#about to read 6, iclass 27, count 2 2006.259.08:07:01.18#ibcon#read 6, iclass 27, count 2 2006.259.08:07:01.18#ibcon#end of sib2, iclass 27, count 2 2006.259.08:07:01.18#ibcon#*mode == 0, iclass 27, count 2 2006.259.08:07:01.18#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.259.08:07:01.18#ibcon#[25=AT08-06\r\n] 2006.259.08:07:01.18#ibcon#*before write, iclass 27, count 2 2006.259.08:07:01.18#ibcon#enter sib2, iclass 27, count 2 2006.259.08:07:01.18#ibcon#flushed, iclass 27, count 2 2006.259.08:07:01.18#ibcon#about to write, iclass 27, count 2 2006.259.08:07:01.18#ibcon#wrote, iclass 27, count 2 2006.259.08:07:01.18#ibcon#about to read 3, iclass 27, count 2 2006.259.08:07:01.21#ibcon#read 3, iclass 27, count 2 2006.259.08:07:01.21#ibcon#about to read 4, iclass 27, count 2 2006.259.08:07:01.21#ibcon#read 4, iclass 27, count 2 2006.259.08:07:01.21#ibcon#about to read 5, iclass 27, count 2 2006.259.08:07:01.21#ibcon#read 5, iclass 27, count 2 2006.259.08:07:01.21#ibcon#about to read 6, iclass 27, count 2 2006.259.08:07:01.21#ibcon#read 6, iclass 27, count 2 2006.259.08:07:01.21#ibcon#end of sib2, iclass 27, count 2 2006.259.08:07:01.21#ibcon#*after write, iclass 27, count 2 2006.259.08:07:01.21#ibcon#*before return 0, iclass 27, count 2 2006.259.08:07:01.21#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.259.08:07:01.21#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.259.08:07:01.21#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.259.08:07:01.21#ibcon#ireg 7 cls_cnt 0 2006.259.08:07:01.21#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.259.08:07:01.33#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.259.08:07:01.33#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.259.08:07:01.33#ibcon#enter wrdev, iclass 27, count 0 2006.259.08:07:01.33#ibcon#first serial, iclass 27, count 0 2006.259.08:07:01.33#ibcon#enter sib2, iclass 27, count 0 2006.259.08:07:01.33#ibcon#flushed, iclass 27, count 0 2006.259.08:07:01.33#ibcon#about to write, iclass 27, count 0 2006.259.08:07:01.33#ibcon#wrote, iclass 27, count 0 2006.259.08:07:01.33#ibcon#about to read 3, iclass 27, count 0 2006.259.08:07:01.35#ibcon#read 3, iclass 27, count 0 2006.259.08:07:01.35#ibcon#about to read 4, iclass 27, count 0 2006.259.08:07:01.35#ibcon#read 4, iclass 27, count 0 2006.259.08:07:01.35#ibcon#about to read 5, iclass 27, count 0 2006.259.08:07:01.35#ibcon#read 5, iclass 27, count 0 2006.259.08:07:01.35#ibcon#about to read 6, iclass 27, count 0 2006.259.08:07:01.35#ibcon#read 6, iclass 27, count 0 2006.259.08:07:01.35#ibcon#end of sib2, iclass 27, count 0 2006.259.08:07:01.35#ibcon#*mode == 0, iclass 27, count 0 2006.259.08:07:01.35#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.259.08:07:01.35#ibcon#[25=USB\r\n] 2006.259.08:07:01.35#ibcon#*before write, iclass 27, count 0 2006.259.08:07:01.35#ibcon#enter sib2, iclass 27, count 0 2006.259.08:07:01.35#ibcon#flushed, iclass 27, count 0 2006.259.08:07:01.35#ibcon#about to write, iclass 27, count 0 2006.259.08:07:01.35#ibcon#wrote, iclass 27, count 0 2006.259.08:07:01.35#ibcon#about to read 3, iclass 27, count 0 2006.259.08:07:01.38#ibcon#read 3, iclass 27, count 0 2006.259.08:07:01.38#ibcon#about to read 4, iclass 27, count 0 2006.259.08:07:01.38#ibcon#read 4, iclass 27, count 0 2006.259.08:07:01.38#ibcon#about to read 5, iclass 27, count 0 2006.259.08:07:01.38#ibcon#read 5, iclass 27, count 0 2006.259.08:07:01.38#ibcon#about to read 6, iclass 27, count 0 2006.259.08:07:01.38#ibcon#read 6, iclass 27, count 0 2006.259.08:07:01.38#ibcon#end of sib2, iclass 27, count 0 2006.259.08:07:01.38#ibcon#*after write, iclass 27, count 0 2006.259.08:07:01.38#ibcon#*before return 0, iclass 27, count 0 2006.259.08:07:01.38#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.259.08:07:01.38#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.259.08:07:01.38#ibcon#about to clear, iclass 27 cls_cnt 0 2006.259.08:07:01.38#ibcon#cleared, iclass 27 cls_cnt 0 2006.259.08:07:01.38$vc4f8/vblo=1,632.99 2006.259.08:07:01.38#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.259.08:07:01.38#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.259.08:07:01.38#ibcon#ireg 17 cls_cnt 0 2006.259.08:07:01.38#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.259.08:07:01.38#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.259.08:07:01.38#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.259.08:07:01.38#ibcon#enter wrdev, iclass 29, count 0 2006.259.08:07:01.38#ibcon#first serial, iclass 29, count 0 2006.259.08:07:01.38#ibcon#enter sib2, iclass 29, count 0 2006.259.08:07:01.38#ibcon#flushed, iclass 29, count 0 2006.259.08:07:01.38#ibcon#about to write, iclass 29, count 0 2006.259.08:07:01.38#ibcon#wrote, iclass 29, count 0 2006.259.08:07:01.38#ibcon#about to read 3, iclass 29, count 0 2006.259.08:07:01.40#ibcon#read 3, iclass 29, count 0 2006.259.08:07:01.40#ibcon#about to read 4, iclass 29, count 0 2006.259.08:07:01.40#ibcon#read 4, iclass 29, count 0 2006.259.08:07:01.40#ibcon#about to read 5, iclass 29, count 0 2006.259.08:07:01.40#ibcon#read 5, iclass 29, count 0 2006.259.08:07:01.40#ibcon#about to read 6, iclass 29, count 0 2006.259.08:07:01.40#ibcon#read 6, iclass 29, count 0 2006.259.08:07:01.40#ibcon#end of sib2, iclass 29, count 0 2006.259.08:07:01.40#ibcon#*mode == 0, iclass 29, count 0 2006.259.08:07:01.40#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.259.08:07:01.40#ibcon#[28=FRQ=01,632.99\r\n] 2006.259.08:07:01.40#ibcon#*before write, iclass 29, count 0 2006.259.08:07:01.40#ibcon#enter sib2, iclass 29, count 0 2006.259.08:07:01.40#ibcon#flushed, iclass 29, count 0 2006.259.08:07:01.40#ibcon#about to write, iclass 29, count 0 2006.259.08:07:01.40#ibcon#wrote, iclass 29, count 0 2006.259.08:07:01.40#ibcon#about to read 3, iclass 29, count 0 2006.259.08:07:01.44#ibcon#read 3, iclass 29, count 0 2006.259.08:07:01.44#ibcon#about to read 4, iclass 29, count 0 2006.259.08:07:01.44#ibcon#read 4, iclass 29, count 0 2006.259.08:07:01.44#ibcon#about to read 5, iclass 29, count 0 2006.259.08:07:01.44#ibcon#read 5, iclass 29, count 0 2006.259.08:07:01.44#ibcon#about to read 6, iclass 29, count 0 2006.259.08:07:01.44#ibcon#read 6, iclass 29, count 0 2006.259.08:07:01.44#ibcon#end of sib2, iclass 29, count 0 2006.259.08:07:01.44#ibcon#*after write, iclass 29, count 0 2006.259.08:07:01.44#ibcon#*before return 0, iclass 29, count 0 2006.259.08:07:01.44#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.259.08:07:01.44#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.259.08:07:01.44#ibcon#about to clear, iclass 29 cls_cnt 0 2006.259.08:07:01.44#ibcon#cleared, iclass 29 cls_cnt 0 2006.259.08:07:01.44$vc4f8/vb=1,4 2006.259.08:07:01.44#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.259.08:07:01.44#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.259.08:07:01.44#ibcon#ireg 11 cls_cnt 2 2006.259.08:07:01.44#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.259.08:07:01.44#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.259.08:07:01.44#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.259.08:07:01.44#ibcon#enter wrdev, iclass 31, count 2 2006.259.08:07:01.44#ibcon#first serial, iclass 31, count 2 2006.259.08:07:01.44#ibcon#enter sib2, iclass 31, count 2 2006.259.08:07:01.44#ibcon#flushed, iclass 31, count 2 2006.259.08:07:01.44#ibcon#about to write, iclass 31, count 2 2006.259.08:07:01.44#ibcon#wrote, iclass 31, count 2 2006.259.08:07:01.44#ibcon#about to read 3, iclass 31, count 2 2006.259.08:07:01.46#ibcon#read 3, iclass 31, count 2 2006.259.08:07:01.46#ibcon#about to read 4, iclass 31, count 2 2006.259.08:07:01.46#ibcon#read 4, iclass 31, count 2 2006.259.08:07:01.46#ibcon#about to read 5, iclass 31, count 2 2006.259.08:07:01.46#ibcon#read 5, iclass 31, count 2 2006.259.08:07:01.46#ibcon#about to read 6, iclass 31, count 2 2006.259.08:07:01.46#ibcon#read 6, iclass 31, count 2 2006.259.08:07:01.46#ibcon#end of sib2, iclass 31, count 2 2006.259.08:07:01.46#ibcon#*mode == 0, iclass 31, count 2 2006.259.08:07:01.46#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.259.08:07:01.46#ibcon#[27=AT01-04\r\n] 2006.259.08:07:01.46#ibcon#*before write, iclass 31, count 2 2006.259.08:07:01.46#ibcon#enter sib2, iclass 31, count 2 2006.259.08:07:01.46#ibcon#flushed, iclass 31, count 2 2006.259.08:07:01.46#ibcon#about to write, iclass 31, count 2 2006.259.08:07:01.46#ibcon#wrote, iclass 31, count 2 2006.259.08:07:01.46#ibcon#about to read 3, iclass 31, count 2 2006.259.08:07:01.49#ibcon#read 3, iclass 31, count 2 2006.259.08:07:01.49#ibcon#about to read 4, iclass 31, count 2 2006.259.08:07:01.49#ibcon#read 4, iclass 31, count 2 2006.259.08:07:01.49#ibcon#about to read 5, iclass 31, count 2 2006.259.08:07:01.49#ibcon#read 5, iclass 31, count 2 2006.259.08:07:01.49#ibcon#about to read 6, iclass 31, count 2 2006.259.08:07:01.49#ibcon#read 6, iclass 31, count 2 2006.259.08:07:01.49#ibcon#end of sib2, iclass 31, count 2 2006.259.08:07:01.49#ibcon#*after write, iclass 31, count 2 2006.259.08:07:01.49#ibcon#*before return 0, iclass 31, count 2 2006.259.08:07:01.49#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.259.08:07:01.49#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.259.08:07:01.49#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.259.08:07:01.49#ibcon#ireg 7 cls_cnt 0 2006.259.08:07:01.49#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.259.08:07:01.61#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.259.08:07:01.61#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.259.08:07:01.61#ibcon#enter wrdev, iclass 31, count 0 2006.259.08:07:01.61#ibcon#first serial, iclass 31, count 0 2006.259.08:07:01.61#ibcon#enter sib2, iclass 31, count 0 2006.259.08:07:01.61#ibcon#flushed, iclass 31, count 0 2006.259.08:07:01.61#ibcon#about to write, iclass 31, count 0 2006.259.08:07:01.61#ibcon#wrote, iclass 31, count 0 2006.259.08:07:01.61#ibcon#about to read 3, iclass 31, count 0 2006.259.08:07:01.63#ibcon#read 3, iclass 31, count 0 2006.259.08:07:01.63#ibcon#about to read 4, iclass 31, count 0 2006.259.08:07:01.63#ibcon#read 4, iclass 31, count 0 2006.259.08:07:01.63#ibcon#about to read 5, iclass 31, count 0 2006.259.08:07:01.63#ibcon#read 5, iclass 31, count 0 2006.259.08:07:01.63#ibcon#about to read 6, iclass 31, count 0 2006.259.08:07:01.63#ibcon#read 6, iclass 31, count 0 2006.259.08:07:01.63#ibcon#end of sib2, iclass 31, count 0 2006.259.08:07:01.63#ibcon#*mode == 0, iclass 31, count 0 2006.259.08:07:01.63#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.259.08:07:01.63#ibcon#[27=USB\r\n] 2006.259.08:07:01.63#ibcon#*before write, iclass 31, count 0 2006.259.08:07:01.63#ibcon#enter sib2, iclass 31, count 0 2006.259.08:07:01.63#ibcon#flushed, iclass 31, count 0 2006.259.08:07:01.63#ibcon#about to write, iclass 31, count 0 2006.259.08:07:01.63#ibcon#wrote, iclass 31, count 0 2006.259.08:07:01.63#ibcon#about to read 3, iclass 31, count 0 2006.259.08:07:01.66#ibcon#read 3, iclass 31, count 0 2006.259.08:07:01.66#ibcon#about to read 4, iclass 31, count 0 2006.259.08:07:01.66#ibcon#read 4, iclass 31, count 0 2006.259.08:07:01.66#ibcon#about to read 5, iclass 31, count 0 2006.259.08:07:01.66#ibcon#read 5, iclass 31, count 0 2006.259.08:07:01.66#ibcon#about to read 6, iclass 31, count 0 2006.259.08:07:01.66#ibcon#read 6, iclass 31, count 0 2006.259.08:07:01.66#ibcon#end of sib2, iclass 31, count 0 2006.259.08:07:01.66#ibcon#*after write, iclass 31, count 0 2006.259.08:07:01.66#ibcon#*before return 0, iclass 31, count 0 2006.259.08:07:01.66#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.259.08:07:01.66#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.259.08:07:01.66#ibcon#about to clear, iclass 31 cls_cnt 0 2006.259.08:07:01.66#ibcon#cleared, iclass 31 cls_cnt 0 2006.259.08:07:01.66$vc4f8/vblo=2,640.99 2006.259.08:07:01.66#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.259.08:07:01.66#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.259.08:07:01.66#ibcon#ireg 17 cls_cnt 0 2006.259.08:07:01.66#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.259.08:07:01.66#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.259.08:07:01.66#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.259.08:07:01.66#ibcon#enter wrdev, iclass 33, count 0 2006.259.08:07:01.66#ibcon#first serial, iclass 33, count 0 2006.259.08:07:01.66#ibcon#enter sib2, iclass 33, count 0 2006.259.08:07:01.66#ibcon#flushed, iclass 33, count 0 2006.259.08:07:01.66#ibcon#about to write, iclass 33, count 0 2006.259.08:07:01.66#ibcon#wrote, iclass 33, count 0 2006.259.08:07:01.66#ibcon#about to read 3, iclass 33, count 0 2006.259.08:07:01.68#ibcon#read 3, iclass 33, count 0 2006.259.08:07:01.68#ibcon#about to read 4, iclass 33, count 0 2006.259.08:07:01.68#ibcon#read 4, iclass 33, count 0 2006.259.08:07:01.68#ibcon#about to read 5, iclass 33, count 0 2006.259.08:07:01.68#ibcon#read 5, iclass 33, count 0 2006.259.08:07:01.68#ibcon#about to read 6, iclass 33, count 0 2006.259.08:07:01.68#ibcon#read 6, iclass 33, count 0 2006.259.08:07:01.68#ibcon#end of sib2, iclass 33, count 0 2006.259.08:07:01.68#ibcon#*mode == 0, iclass 33, count 0 2006.259.08:07:01.68#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.259.08:07:01.68#ibcon#[28=FRQ=02,640.99\r\n] 2006.259.08:07:01.68#ibcon#*before write, iclass 33, count 0 2006.259.08:07:01.68#ibcon#enter sib2, iclass 33, count 0 2006.259.08:07:01.68#ibcon#flushed, iclass 33, count 0 2006.259.08:07:01.68#ibcon#about to write, iclass 33, count 0 2006.259.08:07:01.68#ibcon#wrote, iclass 33, count 0 2006.259.08:07:01.68#ibcon#about to read 3, iclass 33, count 0 2006.259.08:07:01.72#ibcon#read 3, iclass 33, count 0 2006.259.08:07:01.72#ibcon#about to read 4, iclass 33, count 0 2006.259.08:07:01.72#ibcon#read 4, iclass 33, count 0 2006.259.08:07:01.72#ibcon#about to read 5, iclass 33, count 0 2006.259.08:07:01.72#ibcon#read 5, iclass 33, count 0 2006.259.08:07:01.72#ibcon#about to read 6, iclass 33, count 0 2006.259.08:07:01.72#ibcon#read 6, iclass 33, count 0 2006.259.08:07:01.72#ibcon#end of sib2, iclass 33, count 0 2006.259.08:07:01.72#ibcon#*after write, iclass 33, count 0 2006.259.08:07:01.72#ibcon#*before return 0, iclass 33, count 0 2006.259.08:07:01.72#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.259.08:07:01.72#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.259.08:07:01.72#ibcon#about to clear, iclass 33 cls_cnt 0 2006.259.08:07:01.72#ibcon#cleared, iclass 33 cls_cnt 0 2006.259.08:07:01.72$vc4f8/vb=2,5 2006.259.08:07:01.72#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.259.08:07:01.72#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.259.08:07:01.72#ibcon#ireg 11 cls_cnt 2 2006.259.08:07:01.72#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.259.08:07:01.78#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.259.08:07:01.78#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.259.08:07:01.78#ibcon#enter wrdev, iclass 35, count 2 2006.259.08:07:01.78#ibcon#first serial, iclass 35, count 2 2006.259.08:07:01.78#ibcon#enter sib2, iclass 35, count 2 2006.259.08:07:01.78#ibcon#flushed, iclass 35, count 2 2006.259.08:07:01.78#ibcon#about to write, iclass 35, count 2 2006.259.08:07:01.78#ibcon#wrote, iclass 35, count 2 2006.259.08:07:01.78#ibcon#about to read 3, iclass 35, count 2 2006.259.08:07:01.80#ibcon#read 3, iclass 35, count 2 2006.259.08:07:01.80#ibcon#about to read 4, iclass 35, count 2 2006.259.08:07:01.80#ibcon#read 4, iclass 35, count 2 2006.259.08:07:01.80#ibcon#about to read 5, iclass 35, count 2 2006.259.08:07:01.80#ibcon#read 5, iclass 35, count 2 2006.259.08:07:01.80#ibcon#about to read 6, iclass 35, count 2 2006.259.08:07:01.80#ibcon#read 6, iclass 35, count 2 2006.259.08:07:01.80#ibcon#end of sib2, iclass 35, count 2 2006.259.08:07:01.80#ibcon#*mode == 0, iclass 35, count 2 2006.259.08:07:01.80#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.259.08:07:01.80#ibcon#[27=AT02-05\r\n] 2006.259.08:07:01.80#ibcon#*before write, iclass 35, count 2 2006.259.08:07:01.80#ibcon#enter sib2, iclass 35, count 2 2006.259.08:07:01.80#ibcon#flushed, iclass 35, count 2 2006.259.08:07:01.80#ibcon#about to write, iclass 35, count 2 2006.259.08:07:01.80#ibcon#wrote, iclass 35, count 2 2006.259.08:07:01.80#ibcon#about to read 3, iclass 35, count 2 2006.259.08:07:01.83#ibcon#read 3, iclass 35, count 2 2006.259.08:07:01.83#ibcon#about to read 4, iclass 35, count 2 2006.259.08:07:01.83#ibcon#read 4, iclass 35, count 2 2006.259.08:07:01.83#ibcon#about to read 5, iclass 35, count 2 2006.259.08:07:01.83#ibcon#read 5, iclass 35, count 2 2006.259.08:07:01.83#ibcon#about to read 6, iclass 35, count 2 2006.259.08:07:01.83#ibcon#read 6, iclass 35, count 2 2006.259.08:07:01.83#ibcon#end of sib2, iclass 35, count 2 2006.259.08:07:01.83#ibcon#*after write, iclass 35, count 2 2006.259.08:07:01.83#ibcon#*before return 0, iclass 35, count 2 2006.259.08:07:01.83#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.259.08:07:01.83#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.259.08:07:01.83#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.259.08:07:01.83#ibcon#ireg 7 cls_cnt 0 2006.259.08:07:01.83#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.259.08:07:01.95#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.259.08:07:01.95#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.259.08:07:01.95#ibcon#enter wrdev, iclass 35, count 0 2006.259.08:07:01.95#ibcon#first serial, iclass 35, count 0 2006.259.08:07:01.95#ibcon#enter sib2, iclass 35, count 0 2006.259.08:07:01.95#ibcon#flushed, iclass 35, count 0 2006.259.08:07:01.95#ibcon#about to write, iclass 35, count 0 2006.259.08:07:01.95#ibcon#wrote, iclass 35, count 0 2006.259.08:07:01.95#ibcon#about to read 3, iclass 35, count 0 2006.259.08:07:01.97#ibcon#read 3, iclass 35, count 0 2006.259.08:07:01.97#ibcon#about to read 4, iclass 35, count 0 2006.259.08:07:01.97#ibcon#read 4, iclass 35, count 0 2006.259.08:07:01.97#ibcon#about to read 5, iclass 35, count 0 2006.259.08:07:01.97#ibcon#read 5, iclass 35, count 0 2006.259.08:07:01.97#ibcon#about to read 6, iclass 35, count 0 2006.259.08:07:01.97#ibcon#read 6, iclass 35, count 0 2006.259.08:07:01.97#ibcon#end of sib2, iclass 35, count 0 2006.259.08:07:01.97#ibcon#*mode == 0, iclass 35, count 0 2006.259.08:07:01.97#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.259.08:07:01.97#ibcon#[27=USB\r\n] 2006.259.08:07:01.97#ibcon#*before write, iclass 35, count 0 2006.259.08:07:01.97#ibcon#enter sib2, iclass 35, count 0 2006.259.08:07:01.97#ibcon#flushed, iclass 35, count 0 2006.259.08:07:01.97#ibcon#about to write, iclass 35, count 0 2006.259.08:07:01.97#ibcon#wrote, iclass 35, count 0 2006.259.08:07:01.97#ibcon#about to read 3, iclass 35, count 0 2006.259.08:07:02.00#ibcon#read 3, iclass 35, count 0 2006.259.08:07:02.00#ibcon#about to read 4, iclass 35, count 0 2006.259.08:07:02.00#ibcon#read 4, iclass 35, count 0 2006.259.08:07:02.00#ibcon#about to read 5, iclass 35, count 0 2006.259.08:07:02.00#ibcon#read 5, iclass 35, count 0 2006.259.08:07:02.00#ibcon#about to read 6, iclass 35, count 0 2006.259.08:07:02.00#ibcon#read 6, iclass 35, count 0 2006.259.08:07:02.00#ibcon#end of sib2, iclass 35, count 0 2006.259.08:07:02.00#ibcon#*after write, iclass 35, count 0 2006.259.08:07:02.00#ibcon#*before return 0, iclass 35, count 0 2006.259.08:07:02.00#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.259.08:07:02.00#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.259.08:07:02.00#ibcon#about to clear, iclass 35 cls_cnt 0 2006.259.08:07:02.00#ibcon#cleared, iclass 35 cls_cnt 0 2006.259.08:07:02.00$vc4f8/vblo=3,656.99 2006.259.08:07:02.00#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.259.08:07:02.00#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.259.08:07:02.00#ibcon#ireg 17 cls_cnt 0 2006.259.08:07:02.00#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.259.08:07:02.00#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.259.08:07:02.00#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.259.08:07:02.00#ibcon#enter wrdev, iclass 37, count 0 2006.259.08:07:02.00#ibcon#first serial, iclass 37, count 0 2006.259.08:07:02.00#ibcon#enter sib2, iclass 37, count 0 2006.259.08:07:02.00#ibcon#flushed, iclass 37, count 0 2006.259.08:07:02.00#ibcon#about to write, iclass 37, count 0 2006.259.08:07:02.00#ibcon#wrote, iclass 37, count 0 2006.259.08:07:02.00#ibcon#about to read 3, iclass 37, count 0 2006.259.08:07:02.02#ibcon#read 3, iclass 37, count 0 2006.259.08:07:02.02#ibcon#about to read 4, iclass 37, count 0 2006.259.08:07:02.02#ibcon#read 4, iclass 37, count 0 2006.259.08:07:02.02#ibcon#about to read 5, iclass 37, count 0 2006.259.08:07:02.02#ibcon#read 5, iclass 37, count 0 2006.259.08:07:02.02#ibcon#about to read 6, iclass 37, count 0 2006.259.08:07:02.02#ibcon#read 6, iclass 37, count 0 2006.259.08:07:02.02#ibcon#end of sib2, iclass 37, count 0 2006.259.08:07:02.02#ibcon#*mode == 0, iclass 37, count 0 2006.259.08:07:02.02#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.259.08:07:02.02#ibcon#[28=FRQ=03,656.99\r\n] 2006.259.08:07:02.02#ibcon#*before write, iclass 37, count 0 2006.259.08:07:02.02#ibcon#enter sib2, iclass 37, count 0 2006.259.08:07:02.02#ibcon#flushed, iclass 37, count 0 2006.259.08:07:02.02#ibcon#about to write, iclass 37, count 0 2006.259.08:07:02.02#ibcon#wrote, iclass 37, count 0 2006.259.08:07:02.02#ibcon#about to read 3, iclass 37, count 0 2006.259.08:07:02.06#ibcon#read 3, iclass 37, count 0 2006.259.08:07:02.06#ibcon#about to read 4, iclass 37, count 0 2006.259.08:07:02.06#ibcon#read 4, iclass 37, count 0 2006.259.08:07:02.06#ibcon#about to read 5, iclass 37, count 0 2006.259.08:07:02.06#ibcon#read 5, iclass 37, count 0 2006.259.08:07:02.06#ibcon#about to read 6, iclass 37, count 0 2006.259.08:07:02.06#ibcon#read 6, iclass 37, count 0 2006.259.08:07:02.06#ibcon#end of sib2, iclass 37, count 0 2006.259.08:07:02.06#ibcon#*after write, iclass 37, count 0 2006.259.08:07:02.06#ibcon#*before return 0, iclass 37, count 0 2006.259.08:07:02.06#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.259.08:07:02.06#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.259.08:07:02.06#ibcon#about to clear, iclass 37 cls_cnt 0 2006.259.08:07:02.06#ibcon#cleared, iclass 37 cls_cnt 0 2006.259.08:07:02.06$vc4f8/vb=3,4 2006.259.08:07:02.06#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.259.08:07:02.06#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.259.08:07:02.06#ibcon#ireg 11 cls_cnt 2 2006.259.08:07:02.06#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.259.08:07:02.12#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.259.08:07:02.12#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.259.08:07:02.12#ibcon#enter wrdev, iclass 39, count 2 2006.259.08:07:02.12#ibcon#first serial, iclass 39, count 2 2006.259.08:07:02.12#ibcon#enter sib2, iclass 39, count 2 2006.259.08:07:02.12#ibcon#flushed, iclass 39, count 2 2006.259.08:07:02.12#ibcon#about to write, iclass 39, count 2 2006.259.08:07:02.12#ibcon#wrote, iclass 39, count 2 2006.259.08:07:02.12#ibcon#about to read 3, iclass 39, count 2 2006.259.08:07:02.14#ibcon#read 3, iclass 39, count 2 2006.259.08:07:02.14#ibcon#about to read 4, iclass 39, count 2 2006.259.08:07:02.14#ibcon#read 4, iclass 39, count 2 2006.259.08:07:02.14#ibcon#about to read 5, iclass 39, count 2 2006.259.08:07:02.14#ibcon#read 5, iclass 39, count 2 2006.259.08:07:02.14#ibcon#about to read 6, iclass 39, count 2 2006.259.08:07:02.14#ibcon#read 6, iclass 39, count 2 2006.259.08:07:02.14#ibcon#end of sib2, iclass 39, count 2 2006.259.08:07:02.14#ibcon#*mode == 0, iclass 39, count 2 2006.259.08:07:02.14#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.259.08:07:02.14#ibcon#[27=AT03-04\r\n] 2006.259.08:07:02.14#ibcon#*before write, iclass 39, count 2 2006.259.08:07:02.14#ibcon#enter sib2, iclass 39, count 2 2006.259.08:07:02.14#ibcon#flushed, iclass 39, count 2 2006.259.08:07:02.14#ibcon#about to write, iclass 39, count 2 2006.259.08:07:02.14#ibcon#wrote, iclass 39, count 2 2006.259.08:07:02.14#ibcon#about to read 3, iclass 39, count 2 2006.259.08:07:02.17#ibcon#read 3, iclass 39, count 2 2006.259.08:07:02.17#ibcon#about to read 4, iclass 39, count 2 2006.259.08:07:02.17#ibcon#read 4, iclass 39, count 2 2006.259.08:07:02.17#ibcon#about to read 5, iclass 39, count 2 2006.259.08:07:02.17#ibcon#read 5, iclass 39, count 2 2006.259.08:07:02.17#ibcon#about to read 6, iclass 39, count 2 2006.259.08:07:02.17#ibcon#read 6, iclass 39, count 2 2006.259.08:07:02.17#ibcon#end of sib2, iclass 39, count 2 2006.259.08:07:02.17#ibcon#*after write, iclass 39, count 2 2006.259.08:07:02.17#ibcon#*before return 0, iclass 39, count 2 2006.259.08:07:02.17#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.259.08:07:02.17#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.259.08:07:02.17#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.259.08:07:02.17#ibcon#ireg 7 cls_cnt 0 2006.259.08:07:02.17#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.259.08:07:02.29#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.259.08:07:02.29#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.259.08:07:02.29#ibcon#enter wrdev, iclass 39, count 0 2006.259.08:07:02.29#ibcon#first serial, iclass 39, count 0 2006.259.08:07:02.29#ibcon#enter sib2, iclass 39, count 0 2006.259.08:07:02.29#ibcon#flushed, iclass 39, count 0 2006.259.08:07:02.29#ibcon#about to write, iclass 39, count 0 2006.259.08:07:02.29#ibcon#wrote, iclass 39, count 0 2006.259.08:07:02.29#ibcon#about to read 3, iclass 39, count 0 2006.259.08:07:02.31#ibcon#read 3, iclass 39, count 0 2006.259.08:07:02.31#ibcon#about to read 4, iclass 39, count 0 2006.259.08:07:02.31#ibcon#read 4, iclass 39, count 0 2006.259.08:07:02.31#ibcon#about to read 5, iclass 39, count 0 2006.259.08:07:02.31#ibcon#read 5, iclass 39, count 0 2006.259.08:07:02.31#ibcon#about to read 6, iclass 39, count 0 2006.259.08:07:02.31#ibcon#read 6, iclass 39, count 0 2006.259.08:07:02.31#ibcon#end of sib2, iclass 39, count 0 2006.259.08:07:02.31#ibcon#*mode == 0, iclass 39, count 0 2006.259.08:07:02.31#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.259.08:07:02.31#ibcon#[27=USB\r\n] 2006.259.08:07:02.31#ibcon#*before write, iclass 39, count 0 2006.259.08:07:02.31#ibcon#enter sib2, iclass 39, count 0 2006.259.08:07:02.31#ibcon#flushed, iclass 39, count 0 2006.259.08:07:02.31#ibcon#about to write, iclass 39, count 0 2006.259.08:07:02.31#ibcon#wrote, iclass 39, count 0 2006.259.08:07:02.31#ibcon#about to read 3, iclass 39, count 0 2006.259.08:07:02.34#ibcon#read 3, iclass 39, count 0 2006.259.08:07:02.34#ibcon#about to read 4, iclass 39, count 0 2006.259.08:07:02.34#ibcon#read 4, iclass 39, count 0 2006.259.08:07:02.34#ibcon#about to read 5, iclass 39, count 0 2006.259.08:07:02.34#ibcon#read 5, iclass 39, count 0 2006.259.08:07:02.34#ibcon#about to read 6, iclass 39, count 0 2006.259.08:07:02.34#ibcon#read 6, iclass 39, count 0 2006.259.08:07:02.34#ibcon#end of sib2, iclass 39, count 0 2006.259.08:07:02.34#ibcon#*after write, iclass 39, count 0 2006.259.08:07:02.34#ibcon#*before return 0, iclass 39, count 0 2006.259.08:07:02.34#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.259.08:07:02.34#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.259.08:07:02.34#ibcon#about to clear, iclass 39 cls_cnt 0 2006.259.08:07:02.34#ibcon#cleared, iclass 39 cls_cnt 0 2006.259.08:07:02.34$vc4f8/vblo=4,712.99 2006.259.08:07:02.34#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.259.08:07:02.34#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.259.08:07:02.34#ibcon#ireg 17 cls_cnt 0 2006.259.08:07:02.34#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.259.08:07:02.34#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.259.08:07:02.34#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.259.08:07:02.34#ibcon#enter wrdev, iclass 3, count 0 2006.259.08:07:02.34#ibcon#first serial, iclass 3, count 0 2006.259.08:07:02.34#ibcon#enter sib2, iclass 3, count 0 2006.259.08:07:02.34#ibcon#flushed, iclass 3, count 0 2006.259.08:07:02.34#ibcon#about to write, iclass 3, count 0 2006.259.08:07:02.34#ibcon#wrote, iclass 3, count 0 2006.259.08:07:02.34#ibcon#about to read 3, iclass 3, count 0 2006.259.08:07:02.36#ibcon#read 3, iclass 3, count 0 2006.259.08:07:02.36#ibcon#about to read 4, iclass 3, count 0 2006.259.08:07:02.36#ibcon#read 4, iclass 3, count 0 2006.259.08:07:02.36#ibcon#about to read 5, iclass 3, count 0 2006.259.08:07:02.36#ibcon#read 5, iclass 3, count 0 2006.259.08:07:02.36#ibcon#about to read 6, iclass 3, count 0 2006.259.08:07:02.36#ibcon#read 6, iclass 3, count 0 2006.259.08:07:02.36#ibcon#end of sib2, iclass 3, count 0 2006.259.08:07:02.36#ibcon#*mode == 0, iclass 3, count 0 2006.259.08:07:02.36#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.259.08:07:02.36#ibcon#[28=FRQ=04,712.99\r\n] 2006.259.08:07:02.36#ibcon#*before write, iclass 3, count 0 2006.259.08:07:02.36#ibcon#enter sib2, iclass 3, count 0 2006.259.08:07:02.36#ibcon#flushed, iclass 3, count 0 2006.259.08:07:02.36#ibcon#about to write, iclass 3, count 0 2006.259.08:07:02.36#ibcon#wrote, iclass 3, count 0 2006.259.08:07:02.36#ibcon#about to read 3, iclass 3, count 0 2006.259.08:07:02.40#ibcon#read 3, iclass 3, count 0 2006.259.08:07:02.40#ibcon#about to read 4, iclass 3, count 0 2006.259.08:07:02.40#ibcon#read 4, iclass 3, count 0 2006.259.08:07:02.40#ibcon#about to read 5, iclass 3, count 0 2006.259.08:07:02.40#ibcon#read 5, iclass 3, count 0 2006.259.08:07:02.40#ibcon#about to read 6, iclass 3, count 0 2006.259.08:07:02.40#ibcon#read 6, iclass 3, count 0 2006.259.08:07:02.40#ibcon#end of sib2, iclass 3, count 0 2006.259.08:07:02.40#ibcon#*after write, iclass 3, count 0 2006.259.08:07:02.40#ibcon#*before return 0, iclass 3, count 0 2006.259.08:07:02.40#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.259.08:07:02.40#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.259.08:07:02.40#ibcon#about to clear, iclass 3 cls_cnt 0 2006.259.08:07:02.40#ibcon#cleared, iclass 3 cls_cnt 0 2006.259.08:07:02.40$vc4f8/vb=4,5 2006.259.08:07:02.40#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.259.08:07:02.40#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.259.08:07:02.40#ibcon#ireg 11 cls_cnt 2 2006.259.08:07:02.40#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.259.08:07:02.46#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.259.08:07:02.46#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.259.08:07:02.46#ibcon#enter wrdev, iclass 5, count 2 2006.259.08:07:02.46#ibcon#first serial, iclass 5, count 2 2006.259.08:07:02.46#ibcon#enter sib2, iclass 5, count 2 2006.259.08:07:02.46#ibcon#flushed, iclass 5, count 2 2006.259.08:07:02.46#ibcon#about to write, iclass 5, count 2 2006.259.08:07:02.46#ibcon#wrote, iclass 5, count 2 2006.259.08:07:02.46#ibcon#about to read 3, iclass 5, count 2 2006.259.08:07:02.48#ibcon#read 3, iclass 5, count 2 2006.259.08:07:02.48#ibcon#about to read 4, iclass 5, count 2 2006.259.08:07:02.48#ibcon#read 4, iclass 5, count 2 2006.259.08:07:02.48#ibcon#about to read 5, iclass 5, count 2 2006.259.08:07:02.48#ibcon#read 5, iclass 5, count 2 2006.259.08:07:02.48#ibcon#about to read 6, iclass 5, count 2 2006.259.08:07:02.48#ibcon#read 6, iclass 5, count 2 2006.259.08:07:02.48#ibcon#end of sib2, iclass 5, count 2 2006.259.08:07:02.48#ibcon#*mode == 0, iclass 5, count 2 2006.259.08:07:02.48#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.259.08:07:02.48#ibcon#[27=AT04-05\r\n] 2006.259.08:07:02.48#ibcon#*before write, iclass 5, count 2 2006.259.08:07:02.48#ibcon#enter sib2, iclass 5, count 2 2006.259.08:07:02.48#ibcon#flushed, iclass 5, count 2 2006.259.08:07:02.48#ibcon#about to write, iclass 5, count 2 2006.259.08:07:02.48#ibcon#wrote, iclass 5, count 2 2006.259.08:07:02.48#ibcon#about to read 3, iclass 5, count 2 2006.259.08:07:02.51#ibcon#read 3, iclass 5, count 2 2006.259.08:07:02.51#ibcon#about to read 4, iclass 5, count 2 2006.259.08:07:02.51#ibcon#read 4, iclass 5, count 2 2006.259.08:07:02.51#ibcon#about to read 5, iclass 5, count 2 2006.259.08:07:02.51#ibcon#read 5, iclass 5, count 2 2006.259.08:07:02.51#ibcon#about to read 6, iclass 5, count 2 2006.259.08:07:02.51#ibcon#read 6, iclass 5, count 2 2006.259.08:07:02.51#ibcon#end of sib2, iclass 5, count 2 2006.259.08:07:02.51#ibcon#*after write, iclass 5, count 2 2006.259.08:07:02.51#ibcon#*before return 0, iclass 5, count 2 2006.259.08:07:02.51#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.259.08:07:02.51#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.259.08:07:02.51#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.259.08:07:02.51#ibcon#ireg 7 cls_cnt 0 2006.259.08:07:02.51#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.259.08:07:02.63#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.259.08:07:02.63#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.259.08:07:02.63#ibcon#enter wrdev, iclass 5, count 0 2006.259.08:07:02.63#ibcon#first serial, iclass 5, count 0 2006.259.08:07:02.63#ibcon#enter sib2, iclass 5, count 0 2006.259.08:07:02.63#ibcon#flushed, iclass 5, count 0 2006.259.08:07:02.63#ibcon#about to write, iclass 5, count 0 2006.259.08:07:02.63#ibcon#wrote, iclass 5, count 0 2006.259.08:07:02.63#ibcon#about to read 3, iclass 5, count 0 2006.259.08:07:02.65#ibcon#read 3, iclass 5, count 0 2006.259.08:07:02.65#ibcon#about to read 4, iclass 5, count 0 2006.259.08:07:02.65#ibcon#read 4, iclass 5, count 0 2006.259.08:07:02.65#ibcon#about to read 5, iclass 5, count 0 2006.259.08:07:02.65#ibcon#read 5, iclass 5, count 0 2006.259.08:07:02.65#ibcon#about to read 6, iclass 5, count 0 2006.259.08:07:02.65#ibcon#read 6, iclass 5, count 0 2006.259.08:07:02.65#ibcon#end of sib2, iclass 5, count 0 2006.259.08:07:02.65#ibcon#*mode == 0, iclass 5, count 0 2006.259.08:07:02.65#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.259.08:07:02.65#ibcon#[27=USB\r\n] 2006.259.08:07:02.65#ibcon#*before write, iclass 5, count 0 2006.259.08:07:02.65#ibcon#enter sib2, iclass 5, count 0 2006.259.08:07:02.65#ibcon#flushed, iclass 5, count 0 2006.259.08:07:02.65#ibcon#about to write, iclass 5, count 0 2006.259.08:07:02.65#ibcon#wrote, iclass 5, count 0 2006.259.08:07:02.65#ibcon#about to read 3, iclass 5, count 0 2006.259.08:07:02.68#ibcon#read 3, iclass 5, count 0 2006.259.08:07:02.68#ibcon#about to read 4, iclass 5, count 0 2006.259.08:07:02.68#ibcon#read 4, iclass 5, count 0 2006.259.08:07:02.68#ibcon#about to read 5, iclass 5, count 0 2006.259.08:07:02.68#ibcon#read 5, iclass 5, count 0 2006.259.08:07:02.68#ibcon#about to read 6, iclass 5, count 0 2006.259.08:07:02.68#ibcon#read 6, iclass 5, count 0 2006.259.08:07:02.68#ibcon#end of sib2, iclass 5, count 0 2006.259.08:07:02.68#ibcon#*after write, iclass 5, count 0 2006.259.08:07:02.68#ibcon#*before return 0, iclass 5, count 0 2006.259.08:07:02.68#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.259.08:07:02.68#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.259.08:07:02.68#ibcon#about to clear, iclass 5 cls_cnt 0 2006.259.08:07:02.68#ibcon#cleared, iclass 5 cls_cnt 0 2006.259.08:07:02.68$vc4f8/vblo=5,744.99 2006.259.08:07:02.68#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.259.08:07:02.68#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.259.08:07:02.68#ibcon#ireg 17 cls_cnt 0 2006.259.08:07:02.68#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.259.08:07:02.68#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.259.08:07:02.68#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.259.08:07:02.68#ibcon#enter wrdev, iclass 7, count 0 2006.259.08:07:02.68#ibcon#first serial, iclass 7, count 0 2006.259.08:07:02.68#ibcon#enter sib2, iclass 7, count 0 2006.259.08:07:02.68#ibcon#flushed, iclass 7, count 0 2006.259.08:07:02.68#ibcon#about to write, iclass 7, count 0 2006.259.08:07:02.68#ibcon#wrote, iclass 7, count 0 2006.259.08:07:02.68#ibcon#about to read 3, iclass 7, count 0 2006.259.08:07:02.70#ibcon#read 3, iclass 7, count 0 2006.259.08:07:02.70#ibcon#about to read 4, iclass 7, count 0 2006.259.08:07:02.70#ibcon#read 4, iclass 7, count 0 2006.259.08:07:02.70#ibcon#about to read 5, iclass 7, count 0 2006.259.08:07:02.70#ibcon#read 5, iclass 7, count 0 2006.259.08:07:02.70#ibcon#about to read 6, iclass 7, count 0 2006.259.08:07:02.70#ibcon#read 6, iclass 7, count 0 2006.259.08:07:02.70#ibcon#end of sib2, iclass 7, count 0 2006.259.08:07:02.70#ibcon#*mode == 0, iclass 7, count 0 2006.259.08:07:02.70#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.259.08:07:02.70#ibcon#[28=FRQ=05,744.99\r\n] 2006.259.08:07:02.70#ibcon#*before write, iclass 7, count 0 2006.259.08:07:02.70#ibcon#enter sib2, iclass 7, count 0 2006.259.08:07:02.70#ibcon#flushed, iclass 7, count 0 2006.259.08:07:02.70#ibcon#about to write, iclass 7, count 0 2006.259.08:07:02.70#ibcon#wrote, iclass 7, count 0 2006.259.08:07:02.70#ibcon#about to read 3, iclass 7, count 0 2006.259.08:07:02.74#ibcon#read 3, iclass 7, count 0 2006.259.08:07:02.74#ibcon#about to read 4, iclass 7, count 0 2006.259.08:07:02.74#ibcon#read 4, iclass 7, count 0 2006.259.08:07:02.74#ibcon#about to read 5, iclass 7, count 0 2006.259.08:07:02.74#ibcon#read 5, iclass 7, count 0 2006.259.08:07:02.74#ibcon#about to read 6, iclass 7, count 0 2006.259.08:07:02.74#ibcon#read 6, iclass 7, count 0 2006.259.08:07:02.74#ibcon#end of sib2, iclass 7, count 0 2006.259.08:07:02.74#ibcon#*after write, iclass 7, count 0 2006.259.08:07:02.74#ibcon#*before return 0, iclass 7, count 0 2006.259.08:07:02.74#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.259.08:07:02.74#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.259.08:07:02.74#ibcon#about to clear, iclass 7 cls_cnt 0 2006.259.08:07:02.74#ibcon#cleared, iclass 7 cls_cnt 0 2006.259.08:07:02.74$vc4f8/vb=5,4 2006.259.08:07:02.74#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.259.08:07:02.74#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.259.08:07:02.74#ibcon#ireg 11 cls_cnt 2 2006.259.08:07:02.74#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.259.08:07:02.80#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.259.08:07:02.80#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.259.08:07:02.80#ibcon#enter wrdev, iclass 11, count 2 2006.259.08:07:02.80#ibcon#first serial, iclass 11, count 2 2006.259.08:07:02.80#ibcon#enter sib2, iclass 11, count 2 2006.259.08:07:02.80#ibcon#flushed, iclass 11, count 2 2006.259.08:07:02.80#ibcon#about to write, iclass 11, count 2 2006.259.08:07:02.80#ibcon#wrote, iclass 11, count 2 2006.259.08:07:02.80#ibcon#about to read 3, iclass 11, count 2 2006.259.08:07:02.82#ibcon#read 3, iclass 11, count 2 2006.259.08:07:02.82#ibcon#about to read 4, iclass 11, count 2 2006.259.08:07:02.82#ibcon#read 4, iclass 11, count 2 2006.259.08:07:02.82#ibcon#about to read 5, iclass 11, count 2 2006.259.08:07:02.82#ibcon#read 5, iclass 11, count 2 2006.259.08:07:02.82#ibcon#about to read 6, iclass 11, count 2 2006.259.08:07:02.82#ibcon#read 6, iclass 11, count 2 2006.259.08:07:02.82#ibcon#end of sib2, iclass 11, count 2 2006.259.08:07:02.82#ibcon#*mode == 0, iclass 11, count 2 2006.259.08:07:02.82#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.259.08:07:02.82#ibcon#[27=AT05-04\r\n] 2006.259.08:07:02.82#ibcon#*before write, iclass 11, count 2 2006.259.08:07:02.82#ibcon#enter sib2, iclass 11, count 2 2006.259.08:07:02.82#ibcon#flushed, iclass 11, count 2 2006.259.08:07:02.82#ibcon#about to write, iclass 11, count 2 2006.259.08:07:02.82#ibcon#wrote, iclass 11, count 2 2006.259.08:07:02.82#ibcon#about to read 3, iclass 11, count 2 2006.259.08:07:02.85#ibcon#read 3, iclass 11, count 2 2006.259.08:07:02.85#ibcon#about to read 4, iclass 11, count 2 2006.259.08:07:02.85#ibcon#read 4, iclass 11, count 2 2006.259.08:07:02.85#ibcon#about to read 5, iclass 11, count 2 2006.259.08:07:02.85#ibcon#read 5, iclass 11, count 2 2006.259.08:07:02.85#ibcon#about to read 6, iclass 11, count 2 2006.259.08:07:02.85#ibcon#read 6, iclass 11, count 2 2006.259.08:07:02.85#ibcon#end of sib2, iclass 11, count 2 2006.259.08:07:02.85#ibcon#*after write, iclass 11, count 2 2006.259.08:07:02.85#ibcon#*before return 0, iclass 11, count 2 2006.259.08:07:02.85#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.259.08:07:02.85#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.259.08:07:02.85#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.259.08:07:02.85#ibcon#ireg 7 cls_cnt 0 2006.259.08:07:02.85#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.259.08:07:02.97#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.259.08:07:02.97#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.259.08:07:02.97#ibcon#enter wrdev, iclass 11, count 0 2006.259.08:07:02.97#ibcon#first serial, iclass 11, count 0 2006.259.08:07:02.97#ibcon#enter sib2, iclass 11, count 0 2006.259.08:07:02.97#ibcon#flushed, iclass 11, count 0 2006.259.08:07:02.97#ibcon#about to write, iclass 11, count 0 2006.259.08:07:02.97#ibcon#wrote, iclass 11, count 0 2006.259.08:07:02.97#ibcon#about to read 3, iclass 11, count 0 2006.259.08:07:02.99#ibcon#read 3, iclass 11, count 0 2006.259.08:07:02.99#ibcon#about to read 4, iclass 11, count 0 2006.259.08:07:02.99#ibcon#read 4, iclass 11, count 0 2006.259.08:07:02.99#ibcon#about to read 5, iclass 11, count 0 2006.259.08:07:02.99#ibcon#read 5, iclass 11, count 0 2006.259.08:07:02.99#ibcon#about to read 6, iclass 11, count 0 2006.259.08:07:02.99#ibcon#read 6, iclass 11, count 0 2006.259.08:07:02.99#ibcon#end of sib2, iclass 11, count 0 2006.259.08:07:02.99#ibcon#*mode == 0, iclass 11, count 0 2006.259.08:07:02.99#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.259.08:07:02.99#ibcon#[27=USB\r\n] 2006.259.08:07:02.99#ibcon#*before write, iclass 11, count 0 2006.259.08:07:02.99#ibcon#enter sib2, iclass 11, count 0 2006.259.08:07:02.99#ibcon#flushed, iclass 11, count 0 2006.259.08:07:02.99#ibcon#about to write, iclass 11, count 0 2006.259.08:07:02.99#ibcon#wrote, iclass 11, count 0 2006.259.08:07:02.99#ibcon#about to read 3, iclass 11, count 0 2006.259.08:07:03.02#ibcon#read 3, iclass 11, count 0 2006.259.08:07:03.02#ibcon#about to read 4, iclass 11, count 0 2006.259.08:07:03.02#ibcon#read 4, iclass 11, count 0 2006.259.08:07:03.02#ibcon#about to read 5, iclass 11, count 0 2006.259.08:07:03.02#ibcon#read 5, iclass 11, count 0 2006.259.08:07:03.02#ibcon#about to read 6, iclass 11, count 0 2006.259.08:07:03.02#ibcon#read 6, iclass 11, count 0 2006.259.08:07:03.02#ibcon#end of sib2, iclass 11, count 0 2006.259.08:07:03.02#ibcon#*after write, iclass 11, count 0 2006.259.08:07:03.02#ibcon#*before return 0, iclass 11, count 0 2006.259.08:07:03.02#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.259.08:07:03.02#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.259.08:07:03.02#ibcon#about to clear, iclass 11 cls_cnt 0 2006.259.08:07:03.02#ibcon#cleared, iclass 11 cls_cnt 0 2006.259.08:07:03.02$vc4f8/vblo=6,752.99 2006.259.08:07:03.02#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.259.08:07:03.02#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.259.08:07:03.02#ibcon#ireg 17 cls_cnt 0 2006.259.08:07:03.02#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.259.08:07:03.02#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.259.08:07:03.02#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.259.08:07:03.02#ibcon#enter wrdev, iclass 13, count 0 2006.259.08:07:03.02#ibcon#first serial, iclass 13, count 0 2006.259.08:07:03.02#ibcon#enter sib2, iclass 13, count 0 2006.259.08:07:03.02#ibcon#flushed, iclass 13, count 0 2006.259.08:07:03.02#ibcon#about to write, iclass 13, count 0 2006.259.08:07:03.02#ibcon#wrote, iclass 13, count 0 2006.259.08:07:03.02#ibcon#about to read 3, iclass 13, count 0 2006.259.08:07:03.04#ibcon#read 3, iclass 13, count 0 2006.259.08:07:03.04#ibcon#about to read 4, iclass 13, count 0 2006.259.08:07:03.04#ibcon#read 4, iclass 13, count 0 2006.259.08:07:03.04#ibcon#about to read 5, iclass 13, count 0 2006.259.08:07:03.04#ibcon#read 5, iclass 13, count 0 2006.259.08:07:03.04#ibcon#about to read 6, iclass 13, count 0 2006.259.08:07:03.04#ibcon#read 6, iclass 13, count 0 2006.259.08:07:03.04#ibcon#end of sib2, iclass 13, count 0 2006.259.08:07:03.04#ibcon#*mode == 0, iclass 13, count 0 2006.259.08:07:03.04#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.259.08:07:03.04#ibcon#[28=FRQ=06,752.99\r\n] 2006.259.08:07:03.04#ibcon#*before write, iclass 13, count 0 2006.259.08:07:03.04#ibcon#enter sib2, iclass 13, count 0 2006.259.08:07:03.04#ibcon#flushed, iclass 13, count 0 2006.259.08:07:03.04#ibcon#about to write, iclass 13, count 0 2006.259.08:07:03.04#ibcon#wrote, iclass 13, count 0 2006.259.08:07:03.04#ibcon#about to read 3, iclass 13, count 0 2006.259.08:07:03.08#ibcon#read 3, iclass 13, count 0 2006.259.08:07:03.08#ibcon#about to read 4, iclass 13, count 0 2006.259.08:07:03.08#ibcon#read 4, iclass 13, count 0 2006.259.08:07:03.08#ibcon#about to read 5, iclass 13, count 0 2006.259.08:07:03.08#ibcon#read 5, iclass 13, count 0 2006.259.08:07:03.08#ibcon#about to read 6, iclass 13, count 0 2006.259.08:07:03.08#ibcon#read 6, iclass 13, count 0 2006.259.08:07:03.08#ibcon#end of sib2, iclass 13, count 0 2006.259.08:07:03.08#ibcon#*after write, iclass 13, count 0 2006.259.08:07:03.08#ibcon#*before return 0, iclass 13, count 0 2006.259.08:07:03.08#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.259.08:07:03.08#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.259.08:07:03.08#ibcon#about to clear, iclass 13 cls_cnt 0 2006.259.08:07:03.08#ibcon#cleared, iclass 13 cls_cnt 0 2006.259.08:07:03.08$vc4f8/vb=6,4 2006.259.08:07:03.08#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.259.08:07:03.08#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.259.08:07:03.08#ibcon#ireg 11 cls_cnt 2 2006.259.08:07:03.08#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.259.08:07:03.14#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.259.08:07:03.14#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.259.08:07:03.14#ibcon#enter wrdev, iclass 15, count 2 2006.259.08:07:03.14#ibcon#first serial, iclass 15, count 2 2006.259.08:07:03.14#ibcon#enter sib2, iclass 15, count 2 2006.259.08:07:03.14#ibcon#flushed, iclass 15, count 2 2006.259.08:07:03.14#ibcon#about to write, iclass 15, count 2 2006.259.08:07:03.14#ibcon#wrote, iclass 15, count 2 2006.259.08:07:03.14#ibcon#about to read 3, iclass 15, count 2 2006.259.08:07:03.16#ibcon#read 3, iclass 15, count 2 2006.259.08:07:03.16#ibcon#about to read 4, iclass 15, count 2 2006.259.08:07:03.16#ibcon#read 4, iclass 15, count 2 2006.259.08:07:03.16#ibcon#about to read 5, iclass 15, count 2 2006.259.08:07:03.16#ibcon#read 5, iclass 15, count 2 2006.259.08:07:03.16#ibcon#about to read 6, iclass 15, count 2 2006.259.08:07:03.16#ibcon#read 6, iclass 15, count 2 2006.259.08:07:03.16#ibcon#end of sib2, iclass 15, count 2 2006.259.08:07:03.16#ibcon#*mode == 0, iclass 15, count 2 2006.259.08:07:03.16#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.259.08:07:03.16#ibcon#[27=AT06-04\r\n] 2006.259.08:07:03.16#ibcon#*before write, iclass 15, count 2 2006.259.08:07:03.16#ibcon#enter sib2, iclass 15, count 2 2006.259.08:07:03.16#ibcon#flushed, iclass 15, count 2 2006.259.08:07:03.16#ibcon#about to write, iclass 15, count 2 2006.259.08:07:03.16#ibcon#wrote, iclass 15, count 2 2006.259.08:07:03.16#ibcon#about to read 3, iclass 15, count 2 2006.259.08:07:03.19#ibcon#read 3, iclass 15, count 2 2006.259.08:07:03.19#ibcon#about to read 4, iclass 15, count 2 2006.259.08:07:03.19#ibcon#read 4, iclass 15, count 2 2006.259.08:07:03.19#ibcon#about to read 5, iclass 15, count 2 2006.259.08:07:03.19#ibcon#read 5, iclass 15, count 2 2006.259.08:07:03.19#ibcon#about to read 6, iclass 15, count 2 2006.259.08:07:03.19#ibcon#read 6, iclass 15, count 2 2006.259.08:07:03.19#ibcon#end of sib2, iclass 15, count 2 2006.259.08:07:03.19#ibcon#*after write, iclass 15, count 2 2006.259.08:07:03.19#ibcon#*before return 0, iclass 15, count 2 2006.259.08:07:03.19#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.259.08:07:03.19#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.259.08:07:03.19#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.259.08:07:03.19#ibcon#ireg 7 cls_cnt 0 2006.259.08:07:03.19#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.259.08:07:03.31#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.259.08:07:03.31#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.259.08:07:03.31#ibcon#enter wrdev, iclass 15, count 0 2006.259.08:07:03.31#ibcon#first serial, iclass 15, count 0 2006.259.08:07:03.31#ibcon#enter sib2, iclass 15, count 0 2006.259.08:07:03.31#ibcon#flushed, iclass 15, count 0 2006.259.08:07:03.31#ibcon#about to write, iclass 15, count 0 2006.259.08:07:03.31#ibcon#wrote, iclass 15, count 0 2006.259.08:07:03.31#ibcon#about to read 3, iclass 15, count 0 2006.259.08:07:03.33#ibcon#read 3, iclass 15, count 0 2006.259.08:07:03.33#ibcon#about to read 4, iclass 15, count 0 2006.259.08:07:03.33#ibcon#read 4, iclass 15, count 0 2006.259.08:07:03.33#ibcon#about to read 5, iclass 15, count 0 2006.259.08:07:03.33#ibcon#read 5, iclass 15, count 0 2006.259.08:07:03.33#ibcon#about to read 6, iclass 15, count 0 2006.259.08:07:03.33#ibcon#read 6, iclass 15, count 0 2006.259.08:07:03.33#ibcon#end of sib2, iclass 15, count 0 2006.259.08:07:03.33#ibcon#*mode == 0, iclass 15, count 0 2006.259.08:07:03.33#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.259.08:07:03.33#ibcon#[27=USB\r\n] 2006.259.08:07:03.33#ibcon#*before write, iclass 15, count 0 2006.259.08:07:03.33#ibcon#enter sib2, iclass 15, count 0 2006.259.08:07:03.33#ibcon#flushed, iclass 15, count 0 2006.259.08:07:03.33#ibcon#about to write, iclass 15, count 0 2006.259.08:07:03.33#ibcon#wrote, iclass 15, count 0 2006.259.08:07:03.33#ibcon#about to read 3, iclass 15, count 0 2006.259.08:07:03.36#ibcon#read 3, iclass 15, count 0 2006.259.08:07:03.36#ibcon#about to read 4, iclass 15, count 0 2006.259.08:07:03.36#ibcon#read 4, iclass 15, count 0 2006.259.08:07:03.36#ibcon#about to read 5, iclass 15, count 0 2006.259.08:07:03.36#ibcon#read 5, iclass 15, count 0 2006.259.08:07:03.36#ibcon#about to read 6, iclass 15, count 0 2006.259.08:07:03.36#ibcon#read 6, iclass 15, count 0 2006.259.08:07:03.36#ibcon#end of sib2, iclass 15, count 0 2006.259.08:07:03.36#ibcon#*after write, iclass 15, count 0 2006.259.08:07:03.36#ibcon#*before return 0, iclass 15, count 0 2006.259.08:07:03.36#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.259.08:07:03.36#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.259.08:07:03.36#ibcon#about to clear, iclass 15 cls_cnt 0 2006.259.08:07:03.36#ibcon#cleared, iclass 15 cls_cnt 0 2006.259.08:07:03.36$vc4f8/vabw=wide 2006.259.08:07:03.36#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.259.08:07:03.36#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.259.08:07:03.36#ibcon#ireg 8 cls_cnt 0 2006.259.08:07:03.36#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.259.08:07:03.36#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.259.08:07:03.36#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.259.08:07:03.36#ibcon#enter wrdev, iclass 17, count 0 2006.259.08:07:03.36#ibcon#first serial, iclass 17, count 0 2006.259.08:07:03.36#ibcon#enter sib2, iclass 17, count 0 2006.259.08:07:03.36#ibcon#flushed, iclass 17, count 0 2006.259.08:07:03.36#ibcon#about to write, iclass 17, count 0 2006.259.08:07:03.36#ibcon#wrote, iclass 17, count 0 2006.259.08:07:03.36#ibcon#about to read 3, iclass 17, count 0 2006.259.08:07:03.38#ibcon#read 3, iclass 17, count 0 2006.259.08:07:03.38#ibcon#about to read 4, iclass 17, count 0 2006.259.08:07:03.38#ibcon#read 4, iclass 17, count 0 2006.259.08:07:03.38#ibcon#about to read 5, iclass 17, count 0 2006.259.08:07:03.38#ibcon#read 5, iclass 17, count 0 2006.259.08:07:03.38#ibcon#about to read 6, iclass 17, count 0 2006.259.08:07:03.38#ibcon#read 6, iclass 17, count 0 2006.259.08:07:03.38#ibcon#end of sib2, iclass 17, count 0 2006.259.08:07:03.38#ibcon#*mode == 0, iclass 17, count 0 2006.259.08:07:03.38#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.259.08:07:03.38#ibcon#[25=BW32\r\n] 2006.259.08:07:03.38#ibcon#*before write, iclass 17, count 0 2006.259.08:07:03.38#ibcon#enter sib2, iclass 17, count 0 2006.259.08:07:03.38#ibcon#flushed, iclass 17, count 0 2006.259.08:07:03.38#ibcon#about to write, iclass 17, count 0 2006.259.08:07:03.38#ibcon#wrote, iclass 17, count 0 2006.259.08:07:03.38#ibcon#about to read 3, iclass 17, count 0 2006.259.08:07:03.41#ibcon#read 3, iclass 17, count 0 2006.259.08:07:03.41#ibcon#about to read 4, iclass 17, count 0 2006.259.08:07:03.41#ibcon#read 4, iclass 17, count 0 2006.259.08:07:03.41#ibcon#about to read 5, iclass 17, count 0 2006.259.08:07:03.41#ibcon#read 5, iclass 17, count 0 2006.259.08:07:03.41#ibcon#about to read 6, iclass 17, count 0 2006.259.08:07:03.41#ibcon#read 6, iclass 17, count 0 2006.259.08:07:03.41#ibcon#end of sib2, iclass 17, count 0 2006.259.08:07:03.41#ibcon#*after write, iclass 17, count 0 2006.259.08:07:03.41#ibcon#*before return 0, iclass 17, count 0 2006.259.08:07:03.41#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.259.08:07:03.41#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.259.08:07:03.41#ibcon#about to clear, iclass 17 cls_cnt 0 2006.259.08:07:03.41#ibcon#cleared, iclass 17 cls_cnt 0 2006.259.08:07:03.41$vc4f8/vbbw=wide 2006.259.08:07:03.41#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.259.08:07:03.41#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.259.08:07:03.41#ibcon#ireg 8 cls_cnt 0 2006.259.08:07:03.41#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.259.08:07:03.48#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.259.08:07:03.48#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.259.08:07:03.48#ibcon#enter wrdev, iclass 19, count 0 2006.259.08:07:03.48#ibcon#first serial, iclass 19, count 0 2006.259.08:07:03.48#ibcon#enter sib2, iclass 19, count 0 2006.259.08:07:03.48#ibcon#flushed, iclass 19, count 0 2006.259.08:07:03.48#ibcon#about to write, iclass 19, count 0 2006.259.08:07:03.48#ibcon#wrote, iclass 19, count 0 2006.259.08:07:03.48#ibcon#about to read 3, iclass 19, count 0 2006.259.08:07:03.50#ibcon#read 3, iclass 19, count 0 2006.259.08:07:03.50#ibcon#about to read 4, iclass 19, count 0 2006.259.08:07:03.50#ibcon#read 4, iclass 19, count 0 2006.259.08:07:03.50#ibcon#about to read 5, iclass 19, count 0 2006.259.08:07:03.50#ibcon#read 5, iclass 19, count 0 2006.259.08:07:03.50#ibcon#about to read 6, iclass 19, count 0 2006.259.08:07:03.50#ibcon#read 6, iclass 19, count 0 2006.259.08:07:03.50#ibcon#end of sib2, iclass 19, count 0 2006.259.08:07:03.50#ibcon#*mode == 0, iclass 19, count 0 2006.259.08:07:03.50#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.259.08:07:03.50#ibcon#[27=BW32\r\n] 2006.259.08:07:03.50#ibcon#*before write, iclass 19, count 0 2006.259.08:07:03.50#ibcon#enter sib2, iclass 19, count 0 2006.259.08:07:03.50#ibcon#flushed, iclass 19, count 0 2006.259.08:07:03.50#ibcon#about to write, iclass 19, count 0 2006.259.08:07:03.50#ibcon#wrote, iclass 19, count 0 2006.259.08:07:03.50#ibcon#about to read 3, iclass 19, count 0 2006.259.08:07:03.53#ibcon#read 3, iclass 19, count 0 2006.259.08:07:03.53#ibcon#about to read 4, iclass 19, count 0 2006.259.08:07:03.53#ibcon#read 4, iclass 19, count 0 2006.259.08:07:03.53#ibcon#about to read 5, iclass 19, count 0 2006.259.08:07:03.53#ibcon#read 5, iclass 19, count 0 2006.259.08:07:03.53#ibcon#about to read 6, iclass 19, count 0 2006.259.08:07:03.53#ibcon#read 6, iclass 19, count 0 2006.259.08:07:03.53#ibcon#end of sib2, iclass 19, count 0 2006.259.08:07:03.53#ibcon#*after write, iclass 19, count 0 2006.259.08:07:03.53#ibcon#*before return 0, iclass 19, count 0 2006.259.08:07:03.53#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.259.08:07:03.53#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.259.08:07:03.53#ibcon#about to clear, iclass 19 cls_cnt 0 2006.259.08:07:03.53#ibcon#cleared, iclass 19 cls_cnt 0 2006.259.08:07:03.53$4f8m12a/ifd4f 2006.259.08:07:03.53$ifd4f/lo= 2006.259.08:07:03.53$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.259.08:07:03.53$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.259.08:07:03.53$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.259.08:07:03.53$ifd4f/patch= 2006.259.08:07:03.53$ifd4f/patch=lo1,a1,a2,a3,a4 2006.259.08:07:03.53$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.259.08:07:03.53$ifd4f/patch=lo3,a5,a6,a7,a8 2006.259.08:07:03.53$4f8m12a/"form=m,16.000,1:2 2006.259.08:07:03.53$4f8m12a/"tpicd 2006.259.08:07:03.53$4f8m12a/echo=off 2006.259.08:07:03.53$4f8m12a/xlog=off 2006.259.08:07:03.53:!2006.259.08:07:50 2006.259.08:07:25.14#trakl#Source acquired 2006.259.08:07:27.14#flagr#flagr/antenna,acquired 2006.259.08:07:50.00:preob 2006.259.08:07:50.14/onsource/TRACKING 2006.259.08:07:50.14:!2006.259.08:08:00 2006.259.08:08:00.00:data_valid=on 2006.259.08:08:00.00:midob 2006.259.08:08:00.14/onsource/TRACKING 2006.259.08:08:00.14/wx/22.01,1013.0,87 2006.259.08:08:00.28/cable/+6.4592E-03 2006.259.08:08:01.37/va/01,08,usb,yes,31,33 2006.259.08:08:01.37/va/02,07,usb,yes,31,33 2006.259.08:08:01.37/va/03,08,usb,yes,24,24 2006.259.08:08:01.37/va/04,07,usb,yes,32,35 2006.259.08:08:01.37/va/05,07,usb,yes,36,38 2006.259.08:08:01.37/va/06,06,usb,yes,35,35 2006.259.08:08:01.37/va/07,06,usb,yes,36,35 2006.259.08:08:01.37/va/08,06,usb,yes,38,37 2006.259.08:08:01.60/valo/01,532.99,yes,locked 2006.259.08:08:01.60/valo/02,572.99,yes,locked 2006.259.08:08:01.60/valo/03,672.99,yes,locked 2006.259.08:08:01.60/valo/04,832.99,yes,locked 2006.259.08:08:01.60/valo/05,652.99,yes,locked 2006.259.08:08:01.60/valo/06,772.99,yes,locked 2006.259.08:08:01.60/valo/07,832.99,yes,locked 2006.259.08:08:01.60/valo/08,852.99,yes,locked 2006.259.08:08:02.69/vb/01,04,usb,yes,31,29 2006.259.08:08:02.69/vb/02,05,usb,yes,29,30 2006.259.08:08:02.69/vb/03,04,usb,yes,29,33 2006.259.08:08:02.69/vb/04,05,usb,yes,26,26 2006.259.08:08:02.69/vb/05,04,usb,yes,28,32 2006.259.08:08:02.69/vb/06,04,usb,yes,29,32 2006.259.08:08:02.69/vb/07,04,usb,yes,31,31 2006.259.08:08:02.69/vb/08,04,usb,yes,29,32 2006.259.08:08:02.93/vblo/01,632.99,yes,locked 2006.259.08:08:02.93/vblo/02,640.99,yes,locked 2006.259.08:08:02.93/vblo/03,656.99,yes,locked 2006.259.08:08:02.93/vblo/04,712.99,yes,locked 2006.259.08:08:02.93/vblo/05,744.99,yes,locked 2006.259.08:08:02.93/vblo/06,752.99,yes,locked 2006.259.08:08:02.93/vblo/07,734.99,yes,locked 2006.259.08:08:02.93/vblo/08,744.99,yes,locked 2006.259.08:08:03.08/vabw/8 2006.259.08:08:03.23/vbbw/8 2006.259.08:08:03.38/xfe/off,on,15.5 2006.259.08:08:03.75/ifatt/23,28,28,28 2006.259.08:08:04.08/fmout-gps/S +4.59E-07 2006.259.08:08:04.12:!2006.259.08:09:10 2006.259.08:09:10.00:data_valid=off 2006.259.08:09:10.00:postob 2006.259.08:09:10.19/cable/+6.4596E-03 2006.259.08:09:10.19/wx/22.01,1013.0,86 2006.259.08:09:11.08/fmout-gps/S +4.60E-07 2006.259.08:09:11.08:scan_name=259-0810,k06259,60 2006.259.08:09:11.09:source=0955+476,095819.67,472507.8,2000.0,ccw 2006.259.08:09:12.14#flagr#flagr/antenna,new-source 2006.259.08:09:12.15:checkk5 2006.259.08:09:12.73/chk_autoobs//k5ts1/ autoobs is running! 2006.259.08:09:13.19/chk_autoobs//k5ts2/ autoobs is running! 2006.259.08:09:13.59/chk_autoobs//k5ts3/ autoobs is running! 2006.259.08:09:14.00/chk_autoobs//k5ts4/ autoobs is running! 2006.259.08:09:14.41/chk_obsdata//k5ts1/T2590808??a.dat file size is correct (nominal:560MB, actual:552MB). 2006.259.08:09:14.80/chk_obsdata//k5ts2/T2590808??b.dat file size is correct (nominal:560MB, actual:552MB). 2006.259.08:09:15.22/chk_obsdata//k5ts3/T2590808??c.dat file size is correct (nominal:560MB, actual:552MB). 2006.259.08:09:15.61/chk_obsdata//k5ts4/T2590808??d.dat file size is correct (nominal:560MB, actual:552MB). 2006.259.08:09:16.47/k5log//k5ts1_log_newline 2006.259.08:09:17.47/k5log//k5ts2_log_newline 2006.259.08:09:18.31/k5log//k5ts3_log_newline 2006.259.08:09:19.05/k5log//k5ts4_log_newline 2006.259.08:09:19.11/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.259.08:09:19.11:4f8m12a=2 2006.259.08:09:19.11$4f8m12a/echo=on 2006.259.08:09:19.11$4f8m12a/pcalon 2006.259.08:09:19.11$pcalon/"no phase cal control is implemented here 2006.259.08:09:19.11$4f8m12a/"tpicd=stop 2006.259.08:09:19.11$4f8m12a/vc4f8 2006.259.08:09:19.11$vc4f8/valo=1,532.99 2006.259.08:09:19.11#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.259.08:09:19.11#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.259.08:09:19.11#ibcon#ireg 17 cls_cnt 0 2006.259.08:09:19.11#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.259.08:09:19.11#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.259.08:09:19.11#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.259.08:09:19.11#ibcon#enter wrdev, iclass 4, count 0 2006.259.08:09:19.11#ibcon#first serial, iclass 4, count 0 2006.259.08:09:19.11#ibcon#enter sib2, iclass 4, count 0 2006.259.08:09:19.11#ibcon#flushed, iclass 4, count 0 2006.259.08:09:19.11#ibcon#about to write, iclass 4, count 0 2006.259.08:09:19.11#ibcon#wrote, iclass 4, count 0 2006.259.08:09:19.11#ibcon#about to read 3, iclass 4, count 0 2006.259.08:09:19.13#ibcon#read 3, iclass 4, count 0 2006.259.08:09:19.13#ibcon#about to read 4, iclass 4, count 0 2006.259.08:09:19.13#ibcon#read 4, iclass 4, count 0 2006.259.08:09:19.13#ibcon#about to read 5, iclass 4, count 0 2006.259.08:09:19.13#ibcon#read 5, iclass 4, count 0 2006.259.08:09:19.13#ibcon#about to read 6, iclass 4, count 0 2006.259.08:09:19.13#ibcon#read 6, iclass 4, count 0 2006.259.08:09:19.13#ibcon#end of sib2, iclass 4, count 0 2006.259.08:09:19.13#ibcon#*mode == 0, iclass 4, count 0 2006.259.08:09:19.13#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.259.08:09:19.13#ibcon#[26=FRQ=01,532.99\r\n] 2006.259.08:09:19.13#ibcon#*before write, iclass 4, count 0 2006.259.08:09:19.13#ibcon#enter sib2, iclass 4, count 0 2006.259.08:09:19.13#ibcon#flushed, iclass 4, count 0 2006.259.08:09:19.13#ibcon#about to write, iclass 4, count 0 2006.259.08:09:19.13#ibcon#wrote, iclass 4, count 0 2006.259.08:09:19.13#ibcon#about to read 3, iclass 4, count 0 2006.259.08:09:19.18#ibcon#read 3, iclass 4, count 0 2006.259.08:09:19.18#ibcon#about to read 4, iclass 4, count 0 2006.259.08:09:19.18#ibcon#read 4, iclass 4, count 0 2006.259.08:09:19.18#ibcon#about to read 5, iclass 4, count 0 2006.259.08:09:19.18#ibcon#read 5, iclass 4, count 0 2006.259.08:09:19.18#ibcon#about to read 6, iclass 4, count 0 2006.259.08:09:19.18#ibcon#read 6, iclass 4, count 0 2006.259.08:09:19.18#ibcon#end of sib2, iclass 4, count 0 2006.259.08:09:19.18#ibcon#*after write, iclass 4, count 0 2006.259.08:09:19.18#ibcon#*before return 0, iclass 4, count 0 2006.259.08:09:19.18#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.259.08:09:19.18#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.259.08:09:19.18#ibcon#about to clear, iclass 4 cls_cnt 0 2006.259.08:09:19.18#ibcon#cleared, iclass 4 cls_cnt 0 2006.259.08:09:19.18$vc4f8/va=1,8 2006.259.08:09:19.18#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.259.08:09:19.18#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.259.08:09:19.18#ibcon#ireg 11 cls_cnt 2 2006.259.08:09:19.18#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.259.08:09:19.18#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.259.08:09:19.18#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.259.08:09:19.18#ibcon#enter wrdev, iclass 6, count 2 2006.259.08:09:19.18#ibcon#first serial, iclass 6, count 2 2006.259.08:09:19.18#ibcon#enter sib2, iclass 6, count 2 2006.259.08:09:19.18#ibcon#flushed, iclass 6, count 2 2006.259.08:09:19.18#ibcon#about to write, iclass 6, count 2 2006.259.08:09:19.18#ibcon#wrote, iclass 6, count 2 2006.259.08:09:19.18#ibcon#about to read 3, iclass 6, count 2 2006.259.08:09:19.20#ibcon#read 3, iclass 6, count 2 2006.259.08:09:19.20#ibcon#about to read 4, iclass 6, count 2 2006.259.08:09:19.20#ibcon#read 4, iclass 6, count 2 2006.259.08:09:19.20#ibcon#about to read 5, iclass 6, count 2 2006.259.08:09:19.20#ibcon#read 5, iclass 6, count 2 2006.259.08:09:19.20#ibcon#about to read 6, iclass 6, count 2 2006.259.08:09:19.20#ibcon#read 6, iclass 6, count 2 2006.259.08:09:19.20#ibcon#end of sib2, iclass 6, count 2 2006.259.08:09:19.20#ibcon#*mode == 0, iclass 6, count 2 2006.259.08:09:19.20#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.259.08:09:19.20#ibcon#[25=AT01-08\r\n] 2006.259.08:09:19.20#ibcon#*before write, iclass 6, count 2 2006.259.08:09:19.20#ibcon#enter sib2, iclass 6, count 2 2006.259.08:09:19.20#ibcon#flushed, iclass 6, count 2 2006.259.08:09:19.20#ibcon#about to write, iclass 6, count 2 2006.259.08:09:19.20#ibcon#wrote, iclass 6, count 2 2006.259.08:09:19.20#ibcon#about to read 3, iclass 6, count 2 2006.259.08:09:19.23#ibcon#read 3, iclass 6, count 2 2006.259.08:09:19.23#ibcon#about to read 4, iclass 6, count 2 2006.259.08:09:19.23#ibcon#read 4, iclass 6, count 2 2006.259.08:09:19.23#ibcon#about to read 5, iclass 6, count 2 2006.259.08:09:19.23#ibcon#read 5, iclass 6, count 2 2006.259.08:09:19.23#ibcon#about to read 6, iclass 6, count 2 2006.259.08:09:19.23#ibcon#read 6, iclass 6, count 2 2006.259.08:09:19.23#ibcon#end of sib2, iclass 6, count 2 2006.259.08:09:19.23#ibcon#*after write, iclass 6, count 2 2006.259.08:09:19.23#ibcon#*before return 0, iclass 6, count 2 2006.259.08:09:19.23#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.259.08:09:19.23#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.259.08:09:19.23#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.259.08:09:19.23#ibcon#ireg 7 cls_cnt 0 2006.259.08:09:19.23#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.259.08:09:19.35#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.259.08:09:19.35#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.259.08:09:19.35#ibcon#enter wrdev, iclass 6, count 0 2006.259.08:09:19.35#ibcon#first serial, iclass 6, count 0 2006.259.08:09:19.35#ibcon#enter sib2, iclass 6, count 0 2006.259.08:09:19.35#ibcon#flushed, iclass 6, count 0 2006.259.08:09:19.35#ibcon#about to write, iclass 6, count 0 2006.259.08:09:19.35#ibcon#wrote, iclass 6, count 0 2006.259.08:09:19.35#ibcon#about to read 3, iclass 6, count 0 2006.259.08:09:19.37#ibcon#read 3, iclass 6, count 0 2006.259.08:09:19.37#ibcon#about to read 4, iclass 6, count 0 2006.259.08:09:19.37#ibcon#read 4, iclass 6, count 0 2006.259.08:09:19.37#ibcon#about to read 5, iclass 6, count 0 2006.259.08:09:19.37#ibcon#read 5, iclass 6, count 0 2006.259.08:09:19.37#ibcon#about to read 6, iclass 6, count 0 2006.259.08:09:19.37#ibcon#read 6, iclass 6, count 0 2006.259.08:09:19.37#ibcon#end of sib2, iclass 6, count 0 2006.259.08:09:19.37#ibcon#*mode == 0, iclass 6, count 0 2006.259.08:09:19.37#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.259.08:09:19.37#ibcon#[25=USB\r\n] 2006.259.08:09:19.37#ibcon#*before write, iclass 6, count 0 2006.259.08:09:19.37#ibcon#enter sib2, iclass 6, count 0 2006.259.08:09:19.37#ibcon#flushed, iclass 6, count 0 2006.259.08:09:19.37#ibcon#about to write, iclass 6, count 0 2006.259.08:09:19.37#ibcon#wrote, iclass 6, count 0 2006.259.08:09:19.37#ibcon#about to read 3, iclass 6, count 0 2006.259.08:09:19.40#ibcon#read 3, iclass 6, count 0 2006.259.08:09:19.40#ibcon#about to read 4, iclass 6, count 0 2006.259.08:09:19.40#ibcon#read 4, iclass 6, count 0 2006.259.08:09:19.40#ibcon#about to read 5, iclass 6, count 0 2006.259.08:09:19.40#ibcon#read 5, iclass 6, count 0 2006.259.08:09:19.40#ibcon#about to read 6, iclass 6, count 0 2006.259.08:09:19.40#ibcon#read 6, iclass 6, count 0 2006.259.08:09:19.40#ibcon#end of sib2, iclass 6, count 0 2006.259.08:09:19.40#ibcon#*after write, iclass 6, count 0 2006.259.08:09:19.40#ibcon#*before return 0, iclass 6, count 0 2006.259.08:09:19.40#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.259.08:09:19.40#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.259.08:09:19.40#ibcon#about to clear, iclass 6 cls_cnt 0 2006.259.08:09:19.40#ibcon#cleared, iclass 6 cls_cnt 0 2006.259.08:09:19.40$vc4f8/valo=2,572.99 2006.259.08:09:19.40#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.259.08:09:19.40#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.259.08:09:19.40#ibcon#ireg 17 cls_cnt 0 2006.259.08:09:19.40#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.259.08:09:19.40#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.259.08:09:19.40#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.259.08:09:19.40#ibcon#enter wrdev, iclass 10, count 0 2006.259.08:09:19.40#ibcon#first serial, iclass 10, count 0 2006.259.08:09:19.40#ibcon#enter sib2, iclass 10, count 0 2006.259.08:09:19.40#ibcon#flushed, iclass 10, count 0 2006.259.08:09:19.40#ibcon#about to write, iclass 10, count 0 2006.259.08:09:19.40#ibcon#wrote, iclass 10, count 0 2006.259.08:09:19.40#ibcon#about to read 3, iclass 10, count 0 2006.259.08:09:19.42#ibcon#read 3, iclass 10, count 0 2006.259.08:09:19.42#ibcon#about to read 4, iclass 10, count 0 2006.259.08:09:19.42#ibcon#read 4, iclass 10, count 0 2006.259.08:09:19.42#ibcon#about to read 5, iclass 10, count 0 2006.259.08:09:19.42#ibcon#read 5, iclass 10, count 0 2006.259.08:09:19.42#ibcon#about to read 6, iclass 10, count 0 2006.259.08:09:19.42#ibcon#read 6, iclass 10, count 0 2006.259.08:09:19.42#ibcon#end of sib2, iclass 10, count 0 2006.259.08:09:19.42#ibcon#*mode == 0, iclass 10, count 0 2006.259.08:09:19.42#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.259.08:09:19.42#ibcon#[26=FRQ=02,572.99\r\n] 2006.259.08:09:19.42#ibcon#*before write, iclass 10, count 0 2006.259.08:09:19.42#ibcon#enter sib2, iclass 10, count 0 2006.259.08:09:19.42#ibcon#flushed, iclass 10, count 0 2006.259.08:09:19.42#ibcon#about to write, iclass 10, count 0 2006.259.08:09:19.42#ibcon#wrote, iclass 10, count 0 2006.259.08:09:19.42#ibcon#about to read 3, iclass 10, count 0 2006.259.08:09:19.46#ibcon#read 3, iclass 10, count 0 2006.259.08:09:19.46#ibcon#about to read 4, iclass 10, count 0 2006.259.08:09:19.46#ibcon#read 4, iclass 10, count 0 2006.259.08:09:19.46#ibcon#about to read 5, iclass 10, count 0 2006.259.08:09:19.46#ibcon#read 5, iclass 10, count 0 2006.259.08:09:19.46#ibcon#about to read 6, iclass 10, count 0 2006.259.08:09:19.46#ibcon#read 6, iclass 10, count 0 2006.259.08:09:19.46#ibcon#end of sib2, iclass 10, count 0 2006.259.08:09:19.46#ibcon#*after write, iclass 10, count 0 2006.259.08:09:19.46#ibcon#*before return 0, iclass 10, count 0 2006.259.08:09:19.46#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.259.08:09:19.46#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.259.08:09:19.46#ibcon#about to clear, iclass 10 cls_cnt 0 2006.259.08:09:19.46#ibcon#cleared, iclass 10 cls_cnt 0 2006.259.08:09:19.46$vc4f8/va=2,7 2006.259.08:09:19.46#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.259.08:09:19.46#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.259.08:09:19.46#ibcon#ireg 11 cls_cnt 2 2006.259.08:09:19.46#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.259.08:09:19.53#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.259.08:09:19.53#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.259.08:09:19.53#ibcon#enter wrdev, iclass 12, count 2 2006.259.08:09:19.53#ibcon#first serial, iclass 12, count 2 2006.259.08:09:19.53#ibcon#enter sib2, iclass 12, count 2 2006.259.08:09:19.53#ibcon#flushed, iclass 12, count 2 2006.259.08:09:19.53#ibcon#about to write, iclass 12, count 2 2006.259.08:09:19.53#ibcon#wrote, iclass 12, count 2 2006.259.08:09:19.53#ibcon#about to read 3, iclass 12, count 2 2006.259.08:09:19.54#ibcon#read 3, iclass 12, count 2 2006.259.08:09:19.54#ibcon#about to read 4, iclass 12, count 2 2006.259.08:09:19.54#ibcon#read 4, iclass 12, count 2 2006.259.08:09:19.54#ibcon#about to read 5, iclass 12, count 2 2006.259.08:09:19.54#ibcon#read 5, iclass 12, count 2 2006.259.08:09:19.54#ibcon#about to read 6, iclass 12, count 2 2006.259.08:09:19.54#ibcon#read 6, iclass 12, count 2 2006.259.08:09:19.54#ibcon#end of sib2, iclass 12, count 2 2006.259.08:09:19.54#ibcon#*mode == 0, iclass 12, count 2 2006.259.08:09:19.54#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.259.08:09:19.54#ibcon#[25=AT02-07\r\n] 2006.259.08:09:19.54#ibcon#*before write, iclass 12, count 2 2006.259.08:09:19.54#ibcon#enter sib2, iclass 12, count 2 2006.259.08:09:19.54#ibcon#flushed, iclass 12, count 2 2006.259.08:09:19.54#ibcon#about to write, iclass 12, count 2 2006.259.08:09:19.54#ibcon#wrote, iclass 12, count 2 2006.259.08:09:19.54#ibcon#about to read 3, iclass 12, count 2 2006.259.08:09:19.57#ibcon#read 3, iclass 12, count 2 2006.259.08:09:19.57#ibcon#about to read 4, iclass 12, count 2 2006.259.08:09:19.57#ibcon#read 4, iclass 12, count 2 2006.259.08:09:19.57#ibcon#about to read 5, iclass 12, count 2 2006.259.08:09:19.57#ibcon#read 5, iclass 12, count 2 2006.259.08:09:19.57#ibcon#about to read 6, iclass 12, count 2 2006.259.08:09:19.57#ibcon#read 6, iclass 12, count 2 2006.259.08:09:19.57#ibcon#end of sib2, iclass 12, count 2 2006.259.08:09:19.57#ibcon#*after write, iclass 12, count 2 2006.259.08:09:19.57#ibcon#*before return 0, iclass 12, count 2 2006.259.08:09:19.57#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.259.08:09:19.57#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.259.08:09:19.57#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.259.08:09:19.57#ibcon#ireg 7 cls_cnt 0 2006.259.08:09:19.57#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.259.08:09:19.69#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.259.08:09:19.69#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.259.08:09:19.69#ibcon#enter wrdev, iclass 12, count 0 2006.259.08:09:19.69#ibcon#first serial, iclass 12, count 0 2006.259.08:09:19.69#ibcon#enter sib2, iclass 12, count 0 2006.259.08:09:19.69#ibcon#flushed, iclass 12, count 0 2006.259.08:09:19.69#ibcon#about to write, iclass 12, count 0 2006.259.08:09:19.69#ibcon#wrote, iclass 12, count 0 2006.259.08:09:19.69#ibcon#about to read 3, iclass 12, count 0 2006.259.08:09:19.71#ibcon#read 3, iclass 12, count 0 2006.259.08:09:19.71#ibcon#about to read 4, iclass 12, count 0 2006.259.08:09:19.71#ibcon#read 4, iclass 12, count 0 2006.259.08:09:19.71#ibcon#about to read 5, iclass 12, count 0 2006.259.08:09:19.71#ibcon#read 5, iclass 12, count 0 2006.259.08:09:19.71#ibcon#about to read 6, iclass 12, count 0 2006.259.08:09:19.71#ibcon#read 6, iclass 12, count 0 2006.259.08:09:19.71#ibcon#end of sib2, iclass 12, count 0 2006.259.08:09:19.71#ibcon#*mode == 0, iclass 12, count 0 2006.259.08:09:19.71#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.259.08:09:19.71#ibcon#[25=USB\r\n] 2006.259.08:09:19.71#ibcon#*before write, iclass 12, count 0 2006.259.08:09:19.71#ibcon#enter sib2, iclass 12, count 0 2006.259.08:09:19.71#ibcon#flushed, iclass 12, count 0 2006.259.08:09:19.71#ibcon#about to write, iclass 12, count 0 2006.259.08:09:19.71#ibcon#wrote, iclass 12, count 0 2006.259.08:09:19.71#ibcon#about to read 3, iclass 12, count 0 2006.259.08:09:19.74#ibcon#read 3, iclass 12, count 0 2006.259.08:09:19.74#ibcon#about to read 4, iclass 12, count 0 2006.259.08:09:19.74#ibcon#read 4, iclass 12, count 0 2006.259.08:09:19.74#ibcon#about to read 5, iclass 12, count 0 2006.259.08:09:19.74#ibcon#read 5, iclass 12, count 0 2006.259.08:09:19.74#ibcon#about to read 6, iclass 12, count 0 2006.259.08:09:19.74#ibcon#read 6, iclass 12, count 0 2006.259.08:09:19.74#ibcon#end of sib2, iclass 12, count 0 2006.259.08:09:19.74#ibcon#*after write, iclass 12, count 0 2006.259.08:09:19.74#ibcon#*before return 0, iclass 12, count 0 2006.259.08:09:19.74#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.259.08:09:19.74#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.259.08:09:19.74#ibcon#about to clear, iclass 12 cls_cnt 0 2006.259.08:09:19.74#ibcon#cleared, iclass 12 cls_cnt 0 2006.259.08:09:19.74$vc4f8/valo=3,672.99 2006.259.08:09:19.74#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.259.08:09:19.74#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.259.08:09:19.74#ibcon#ireg 17 cls_cnt 0 2006.259.08:09:19.74#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.259.08:09:19.74#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.259.08:09:19.74#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.259.08:09:19.74#ibcon#enter wrdev, iclass 14, count 0 2006.259.08:09:19.74#ibcon#first serial, iclass 14, count 0 2006.259.08:09:19.74#ibcon#enter sib2, iclass 14, count 0 2006.259.08:09:19.74#ibcon#flushed, iclass 14, count 0 2006.259.08:09:19.74#ibcon#about to write, iclass 14, count 0 2006.259.08:09:19.74#ibcon#wrote, iclass 14, count 0 2006.259.08:09:19.74#ibcon#about to read 3, iclass 14, count 0 2006.259.08:09:19.76#ibcon#read 3, iclass 14, count 0 2006.259.08:09:19.76#ibcon#about to read 4, iclass 14, count 0 2006.259.08:09:19.76#ibcon#read 4, iclass 14, count 0 2006.259.08:09:19.76#ibcon#about to read 5, iclass 14, count 0 2006.259.08:09:19.76#ibcon#read 5, iclass 14, count 0 2006.259.08:09:19.76#ibcon#about to read 6, iclass 14, count 0 2006.259.08:09:19.76#ibcon#read 6, iclass 14, count 0 2006.259.08:09:19.76#ibcon#end of sib2, iclass 14, count 0 2006.259.08:09:19.76#ibcon#*mode == 0, iclass 14, count 0 2006.259.08:09:19.76#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.259.08:09:19.76#ibcon#[26=FRQ=03,672.99\r\n] 2006.259.08:09:19.76#ibcon#*before write, iclass 14, count 0 2006.259.08:09:19.76#ibcon#enter sib2, iclass 14, count 0 2006.259.08:09:19.76#ibcon#flushed, iclass 14, count 0 2006.259.08:09:19.76#ibcon#about to write, iclass 14, count 0 2006.259.08:09:19.76#ibcon#wrote, iclass 14, count 0 2006.259.08:09:19.76#ibcon#about to read 3, iclass 14, count 0 2006.259.08:09:19.80#ibcon#read 3, iclass 14, count 0 2006.259.08:09:19.80#ibcon#about to read 4, iclass 14, count 0 2006.259.08:09:19.80#ibcon#read 4, iclass 14, count 0 2006.259.08:09:19.80#ibcon#about to read 5, iclass 14, count 0 2006.259.08:09:19.80#ibcon#read 5, iclass 14, count 0 2006.259.08:09:19.80#ibcon#about to read 6, iclass 14, count 0 2006.259.08:09:19.80#ibcon#read 6, iclass 14, count 0 2006.259.08:09:19.80#ibcon#end of sib2, iclass 14, count 0 2006.259.08:09:19.80#ibcon#*after write, iclass 14, count 0 2006.259.08:09:19.80#ibcon#*before return 0, iclass 14, count 0 2006.259.08:09:19.80#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.259.08:09:19.80#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.259.08:09:19.80#ibcon#about to clear, iclass 14 cls_cnt 0 2006.259.08:09:19.80#ibcon#cleared, iclass 14 cls_cnt 0 2006.259.08:09:19.80$vc4f8/va=3,8 2006.259.08:09:19.80#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.259.08:09:19.80#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.259.08:09:19.80#ibcon#ireg 11 cls_cnt 2 2006.259.08:09:19.80#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.259.08:09:19.87#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.259.08:09:19.87#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.259.08:09:19.87#ibcon#enter wrdev, iclass 16, count 2 2006.259.08:09:19.87#ibcon#first serial, iclass 16, count 2 2006.259.08:09:19.87#ibcon#enter sib2, iclass 16, count 2 2006.259.08:09:19.87#ibcon#flushed, iclass 16, count 2 2006.259.08:09:19.87#ibcon#about to write, iclass 16, count 2 2006.259.08:09:19.87#ibcon#wrote, iclass 16, count 2 2006.259.08:09:19.87#ibcon#about to read 3, iclass 16, count 2 2006.259.08:09:19.88#ibcon#read 3, iclass 16, count 2 2006.259.08:09:19.88#ibcon#about to read 4, iclass 16, count 2 2006.259.08:09:19.88#ibcon#read 4, iclass 16, count 2 2006.259.08:09:19.88#ibcon#about to read 5, iclass 16, count 2 2006.259.08:09:19.88#ibcon#read 5, iclass 16, count 2 2006.259.08:09:19.88#ibcon#about to read 6, iclass 16, count 2 2006.259.08:09:19.88#ibcon#read 6, iclass 16, count 2 2006.259.08:09:19.88#ibcon#end of sib2, iclass 16, count 2 2006.259.08:09:19.88#ibcon#*mode == 0, iclass 16, count 2 2006.259.08:09:19.88#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.259.08:09:19.88#ibcon#[25=AT03-08\r\n] 2006.259.08:09:19.88#ibcon#*before write, iclass 16, count 2 2006.259.08:09:19.88#ibcon#enter sib2, iclass 16, count 2 2006.259.08:09:19.88#ibcon#flushed, iclass 16, count 2 2006.259.08:09:19.88#ibcon#about to write, iclass 16, count 2 2006.259.08:09:19.88#ibcon#wrote, iclass 16, count 2 2006.259.08:09:19.88#ibcon#about to read 3, iclass 16, count 2 2006.259.08:09:19.91#ibcon#read 3, iclass 16, count 2 2006.259.08:09:19.91#ibcon#about to read 4, iclass 16, count 2 2006.259.08:09:19.91#ibcon#read 4, iclass 16, count 2 2006.259.08:09:19.91#ibcon#about to read 5, iclass 16, count 2 2006.259.08:09:19.91#ibcon#read 5, iclass 16, count 2 2006.259.08:09:19.91#ibcon#about to read 6, iclass 16, count 2 2006.259.08:09:19.91#ibcon#read 6, iclass 16, count 2 2006.259.08:09:19.91#ibcon#end of sib2, iclass 16, count 2 2006.259.08:09:19.91#ibcon#*after write, iclass 16, count 2 2006.259.08:09:19.91#ibcon#*before return 0, iclass 16, count 2 2006.259.08:09:19.91#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.259.08:09:19.91#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.259.08:09:19.91#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.259.08:09:19.91#ibcon#ireg 7 cls_cnt 0 2006.259.08:09:19.91#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.259.08:09:20.03#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.259.08:09:20.03#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.259.08:09:20.03#ibcon#enter wrdev, iclass 16, count 0 2006.259.08:09:20.03#ibcon#first serial, iclass 16, count 0 2006.259.08:09:20.03#ibcon#enter sib2, iclass 16, count 0 2006.259.08:09:20.03#ibcon#flushed, iclass 16, count 0 2006.259.08:09:20.03#ibcon#about to write, iclass 16, count 0 2006.259.08:09:20.03#ibcon#wrote, iclass 16, count 0 2006.259.08:09:20.03#ibcon#about to read 3, iclass 16, count 0 2006.259.08:09:20.05#ibcon#read 3, iclass 16, count 0 2006.259.08:09:20.05#ibcon#about to read 4, iclass 16, count 0 2006.259.08:09:20.05#ibcon#read 4, iclass 16, count 0 2006.259.08:09:20.05#ibcon#about to read 5, iclass 16, count 0 2006.259.08:09:20.05#ibcon#read 5, iclass 16, count 0 2006.259.08:09:20.05#ibcon#about to read 6, iclass 16, count 0 2006.259.08:09:20.05#ibcon#read 6, iclass 16, count 0 2006.259.08:09:20.05#ibcon#end of sib2, iclass 16, count 0 2006.259.08:09:20.05#ibcon#*mode == 0, iclass 16, count 0 2006.259.08:09:20.05#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.259.08:09:20.05#ibcon#[25=USB\r\n] 2006.259.08:09:20.05#ibcon#*before write, iclass 16, count 0 2006.259.08:09:20.05#ibcon#enter sib2, iclass 16, count 0 2006.259.08:09:20.05#ibcon#flushed, iclass 16, count 0 2006.259.08:09:20.05#ibcon#about to write, iclass 16, count 0 2006.259.08:09:20.05#ibcon#wrote, iclass 16, count 0 2006.259.08:09:20.05#ibcon#about to read 3, iclass 16, count 0 2006.259.08:09:20.08#ibcon#read 3, iclass 16, count 0 2006.259.08:09:20.08#ibcon#about to read 4, iclass 16, count 0 2006.259.08:09:20.08#ibcon#read 4, iclass 16, count 0 2006.259.08:09:20.08#ibcon#about to read 5, iclass 16, count 0 2006.259.08:09:20.08#ibcon#read 5, iclass 16, count 0 2006.259.08:09:20.08#ibcon#about to read 6, iclass 16, count 0 2006.259.08:09:20.08#ibcon#read 6, iclass 16, count 0 2006.259.08:09:20.08#ibcon#end of sib2, iclass 16, count 0 2006.259.08:09:20.08#ibcon#*after write, iclass 16, count 0 2006.259.08:09:20.08#ibcon#*before return 0, iclass 16, count 0 2006.259.08:09:20.08#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.259.08:09:20.08#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.259.08:09:20.08#ibcon#about to clear, iclass 16 cls_cnt 0 2006.259.08:09:20.08#ibcon#cleared, iclass 16 cls_cnt 0 2006.259.08:09:20.08$vc4f8/valo=4,832.99 2006.259.08:09:20.08#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.259.08:09:20.08#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.259.08:09:20.08#ibcon#ireg 17 cls_cnt 0 2006.259.08:09:20.08#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.259.08:09:20.08#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.259.08:09:20.08#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.259.08:09:20.08#ibcon#enter wrdev, iclass 18, count 0 2006.259.08:09:20.08#ibcon#first serial, iclass 18, count 0 2006.259.08:09:20.08#ibcon#enter sib2, iclass 18, count 0 2006.259.08:09:20.08#ibcon#flushed, iclass 18, count 0 2006.259.08:09:20.08#ibcon#about to write, iclass 18, count 0 2006.259.08:09:20.08#ibcon#wrote, iclass 18, count 0 2006.259.08:09:20.08#ibcon#about to read 3, iclass 18, count 0 2006.259.08:09:20.10#ibcon#read 3, iclass 18, count 0 2006.259.08:09:20.10#ibcon#about to read 4, iclass 18, count 0 2006.259.08:09:20.10#ibcon#read 4, iclass 18, count 0 2006.259.08:09:20.10#ibcon#about to read 5, iclass 18, count 0 2006.259.08:09:20.10#ibcon#read 5, iclass 18, count 0 2006.259.08:09:20.10#ibcon#about to read 6, iclass 18, count 0 2006.259.08:09:20.10#ibcon#read 6, iclass 18, count 0 2006.259.08:09:20.10#ibcon#end of sib2, iclass 18, count 0 2006.259.08:09:20.10#ibcon#*mode == 0, iclass 18, count 0 2006.259.08:09:20.10#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.259.08:09:20.10#ibcon#[26=FRQ=04,832.99\r\n] 2006.259.08:09:20.10#ibcon#*before write, iclass 18, count 0 2006.259.08:09:20.10#ibcon#enter sib2, iclass 18, count 0 2006.259.08:09:20.10#ibcon#flushed, iclass 18, count 0 2006.259.08:09:20.10#ibcon#about to write, iclass 18, count 0 2006.259.08:09:20.10#ibcon#wrote, iclass 18, count 0 2006.259.08:09:20.10#ibcon#about to read 3, iclass 18, count 0 2006.259.08:09:20.14#ibcon#read 3, iclass 18, count 0 2006.259.08:09:20.14#ibcon#about to read 4, iclass 18, count 0 2006.259.08:09:20.14#ibcon#read 4, iclass 18, count 0 2006.259.08:09:20.14#ibcon#about to read 5, iclass 18, count 0 2006.259.08:09:20.14#ibcon#read 5, iclass 18, count 0 2006.259.08:09:20.14#ibcon#about to read 6, iclass 18, count 0 2006.259.08:09:20.14#ibcon#read 6, iclass 18, count 0 2006.259.08:09:20.14#ibcon#end of sib2, iclass 18, count 0 2006.259.08:09:20.14#ibcon#*after write, iclass 18, count 0 2006.259.08:09:20.14#ibcon#*before return 0, iclass 18, count 0 2006.259.08:09:20.14#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.259.08:09:20.14#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.259.08:09:20.14#ibcon#about to clear, iclass 18 cls_cnt 0 2006.259.08:09:20.14#ibcon#cleared, iclass 18 cls_cnt 0 2006.259.08:09:20.14$vc4f8/va=4,7 2006.259.08:09:20.14#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.259.08:09:20.14#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.259.08:09:20.14#ibcon#ireg 11 cls_cnt 2 2006.259.08:09:20.14#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.259.08:09:20.20#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.259.08:09:20.20#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.259.08:09:20.20#ibcon#enter wrdev, iclass 20, count 2 2006.259.08:09:20.20#ibcon#first serial, iclass 20, count 2 2006.259.08:09:20.20#ibcon#enter sib2, iclass 20, count 2 2006.259.08:09:20.20#ibcon#flushed, iclass 20, count 2 2006.259.08:09:20.20#ibcon#about to write, iclass 20, count 2 2006.259.08:09:20.20#ibcon#wrote, iclass 20, count 2 2006.259.08:09:20.20#ibcon#about to read 3, iclass 20, count 2 2006.259.08:09:20.22#ibcon#read 3, iclass 20, count 2 2006.259.08:09:20.22#ibcon#about to read 4, iclass 20, count 2 2006.259.08:09:20.22#ibcon#read 4, iclass 20, count 2 2006.259.08:09:20.22#ibcon#about to read 5, iclass 20, count 2 2006.259.08:09:20.22#ibcon#read 5, iclass 20, count 2 2006.259.08:09:20.22#ibcon#about to read 6, iclass 20, count 2 2006.259.08:09:20.22#ibcon#read 6, iclass 20, count 2 2006.259.08:09:20.22#ibcon#end of sib2, iclass 20, count 2 2006.259.08:09:20.22#ibcon#*mode == 0, iclass 20, count 2 2006.259.08:09:20.22#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.259.08:09:20.22#ibcon#[25=AT04-07\r\n] 2006.259.08:09:20.22#ibcon#*before write, iclass 20, count 2 2006.259.08:09:20.22#ibcon#enter sib2, iclass 20, count 2 2006.259.08:09:20.22#ibcon#flushed, iclass 20, count 2 2006.259.08:09:20.22#ibcon#about to write, iclass 20, count 2 2006.259.08:09:20.22#ibcon#wrote, iclass 20, count 2 2006.259.08:09:20.22#ibcon#about to read 3, iclass 20, count 2 2006.259.08:09:20.25#ibcon#read 3, iclass 20, count 2 2006.259.08:09:20.25#ibcon#about to read 4, iclass 20, count 2 2006.259.08:09:20.25#ibcon#read 4, iclass 20, count 2 2006.259.08:09:20.25#ibcon#about to read 5, iclass 20, count 2 2006.259.08:09:20.25#ibcon#read 5, iclass 20, count 2 2006.259.08:09:20.25#ibcon#about to read 6, iclass 20, count 2 2006.259.08:09:20.25#ibcon#read 6, iclass 20, count 2 2006.259.08:09:20.25#ibcon#end of sib2, iclass 20, count 2 2006.259.08:09:20.25#ibcon#*after write, iclass 20, count 2 2006.259.08:09:20.25#ibcon#*before return 0, iclass 20, count 2 2006.259.08:09:20.25#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.259.08:09:20.25#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.259.08:09:20.25#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.259.08:09:20.25#ibcon#ireg 7 cls_cnt 0 2006.259.08:09:20.25#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.259.08:09:20.37#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.259.08:09:20.37#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.259.08:09:20.37#ibcon#enter wrdev, iclass 20, count 0 2006.259.08:09:20.37#ibcon#first serial, iclass 20, count 0 2006.259.08:09:20.37#ibcon#enter sib2, iclass 20, count 0 2006.259.08:09:20.37#ibcon#flushed, iclass 20, count 0 2006.259.08:09:20.37#ibcon#about to write, iclass 20, count 0 2006.259.08:09:20.37#ibcon#wrote, iclass 20, count 0 2006.259.08:09:20.37#ibcon#about to read 3, iclass 20, count 0 2006.259.08:09:20.39#ibcon#read 3, iclass 20, count 0 2006.259.08:09:20.39#ibcon#about to read 4, iclass 20, count 0 2006.259.08:09:20.39#ibcon#read 4, iclass 20, count 0 2006.259.08:09:20.39#ibcon#about to read 5, iclass 20, count 0 2006.259.08:09:20.39#ibcon#read 5, iclass 20, count 0 2006.259.08:09:20.39#ibcon#about to read 6, iclass 20, count 0 2006.259.08:09:20.39#ibcon#read 6, iclass 20, count 0 2006.259.08:09:20.39#ibcon#end of sib2, iclass 20, count 0 2006.259.08:09:20.39#ibcon#*mode == 0, iclass 20, count 0 2006.259.08:09:20.39#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.259.08:09:20.39#ibcon#[25=USB\r\n] 2006.259.08:09:20.39#ibcon#*before write, iclass 20, count 0 2006.259.08:09:20.39#ibcon#enter sib2, iclass 20, count 0 2006.259.08:09:20.39#ibcon#flushed, iclass 20, count 0 2006.259.08:09:20.39#ibcon#about to write, iclass 20, count 0 2006.259.08:09:20.39#ibcon#wrote, iclass 20, count 0 2006.259.08:09:20.39#ibcon#about to read 3, iclass 20, count 0 2006.259.08:09:20.42#ibcon#read 3, iclass 20, count 0 2006.259.08:09:20.42#ibcon#about to read 4, iclass 20, count 0 2006.259.08:09:20.42#ibcon#read 4, iclass 20, count 0 2006.259.08:09:20.42#ibcon#about to read 5, iclass 20, count 0 2006.259.08:09:20.42#ibcon#read 5, iclass 20, count 0 2006.259.08:09:20.42#ibcon#about to read 6, iclass 20, count 0 2006.259.08:09:20.42#ibcon#read 6, iclass 20, count 0 2006.259.08:09:20.42#ibcon#end of sib2, iclass 20, count 0 2006.259.08:09:20.42#ibcon#*after write, iclass 20, count 0 2006.259.08:09:20.42#ibcon#*before return 0, iclass 20, count 0 2006.259.08:09:20.42#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.259.08:09:20.42#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.259.08:09:20.42#ibcon#about to clear, iclass 20 cls_cnt 0 2006.259.08:09:20.42#ibcon#cleared, iclass 20 cls_cnt 0 2006.259.08:09:20.42$vc4f8/valo=5,652.99 2006.259.08:09:20.42#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.259.08:09:20.42#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.259.08:09:20.42#ibcon#ireg 17 cls_cnt 0 2006.259.08:09:20.42#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.259.08:09:20.42#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.259.08:09:20.42#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.259.08:09:20.42#ibcon#enter wrdev, iclass 22, count 0 2006.259.08:09:20.42#ibcon#first serial, iclass 22, count 0 2006.259.08:09:20.42#ibcon#enter sib2, iclass 22, count 0 2006.259.08:09:20.42#ibcon#flushed, iclass 22, count 0 2006.259.08:09:20.42#ibcon#about to write, iclass 22, count 0 2006.259.08:09:20.42#ibcon#wrote, iclass 22, count 0 2006.259.08:09:20.42#ibcon#about to read 3, iclass 22, count 0 2006.259.08:09:20.44#ibcon#read 3, iclass 22, count 0 2006.259.08:09:20.44#ibcon#about to read 4, iclass 22, count 0 2006.259.08:09:20.44#ibcon#read 4, iclass 22, count 0 2006.259.08:09:20.44#ibcon#about to read 5, iclass 22, count 0 2006.259.08:09:20.44#ibcon#read 5, iclass 22, count 0 2006.259.08:09:20.44#ibcon#about to read 6, iclass 22, count 0 2006.259.08:09:20.44#ibcon#read 6, iclass 22, count 0 2006.259.08:09:20.44#ibcon#end of sib2, iclass 22, count 0 2006.259.08:09:20.44#ibcon#*mode == 0, iclass 22, count 0 2006.259.08:09:20.44#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.259.08:09:20.44#ibcon#[26=FRQ=05,652.99\r\n] 2006.259.08:09:20.44#ibcon#*before write, iclass 22, count 0 2006.259.08:09:20.44#ibcon#enter sib2, iclass 22, count 0 2006.259.08:09:20.44#ibcon#flushed, iclass 22, count 0 2006.259.08:09:20.44#ibcon#about to write, iclass 22, count 0 2006.259.08:09:20.44#ibcon#wrote, iclass 22, count 0 2006.259.08:09:20.44#ibcon#about to read 3, iclass 22, count 0 2006.259.08:09:20.48#ibcon#read 3, iclass 22, count 0 2006.259.08:09:20.48#ibcon#about to read 4, iclass 22, count 0 2006.259.08:09:20.48#ibcon#read 4, iclass 22, count 0 2006.259.08:09:20.48#ibcon#about to read 5, iclass 22, count 0 2006.259.08:09:20.48#ibcon#read 5, iclass 22, count 0 2006.259.08:09:20.48#ibcon#about to read 6, iclass 22, count 0 2006.259.08:09:20.48#ibcon#read 6, iclass 22, count 0 2006.259.08:09:20.48#ibcon#end of sib2, iclass 22, count 0 2006.259.08:09:20.48#ibcon#*after write, iclass 22, count 0 2006.259.08:09:20.48#ibcon#*before return 0, iclass 22, count 0 2006.259.08:09:20.48#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.259.08:09:20.48#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.259.08:09:20.48#ibcon#about to clear, iclass 22 cls_cnt 0 2006.259.08:09:20.48#ibcon#cleared, iclass 22 cls_cnt 0 2006.259.08:09:20.48$vc4f8/va=5,7 2006.259.08:09:20.48#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.259.08:09:20.48#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.259.08:09:20.48#ibcon#ireg 11 cls_cnt 2 2006.259.08:09:20.48#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.259.08:09:20.54#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.259.08:09:20.54#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.259.08:09:20.54#ibcon#enter wrdev, iclass 24, count 2 2006.259.08:09:20.54#ibcon#first serial, iclass 24, count 2 2006.259.08:09:20.54#ibcon#enter sib2, iclass 24, count 2 2006.259.08:09:20.54#ibcon#flushed, iclass 24, count 2 2006.259.08:09:20.54#ibcon#about to write, iclass 24, count 2 2006.259.08:09:20.54#ibcon#wrote, iclass 24, count 2 2006.259.08:09:20.54#ibcon#about to read 3, iclass 24, count 2 2006.259.08:09:20.56#ibcon#read 3, iclass 24, count 2 2006.259.08:09:20.56#ibcon#about to read 4, iclass 24, count 2 2006.259.08:09:20.56#ibcon#read 4, iclass 24, count 2 2006.259.08:09:20.56#ibcon#about to read 5, iclass 24, count 2 2006.259.08:09:20.56#ibcon#read 5, iclass 24, count 2 2006.259.08:09:20.56#ibcon#about to read 6, iclass 24, count 2 2006.259.08:09:20.56#ibcon#read 6, iclass 24, count 2 2006.259.08:09:20.56#ibcon#end of sib2, iclass 24, count 2 2006.259.08:09:20.56#ibcon#*mode == 0, iclass 24, count 2 2006.259.08:09:20.56#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.259.08:09:20.56#ibcon#[25=AT05-07\r\n] 2006.259.08:09:20.56#ibcon#*before write, iclass 24, count 2 2006.259.08:09:20.56#ibcon#enter sib2, iclass 24, count 2 2006.259.08:09:20.56#ibcon#flushed, iclass 24, count 2 2006.259.08:09:20.56#ibcon#about to write, iclass 24, count 2 2006.259.08:09:20.56#ibcon#wrote, iclass 24, count 2 2006.259.08:09:20.56#ibcon#about to read 3, iclass 24, count 2 2006.259.08:09:20.59#ibcon#read 3, iclass 24, count 2 2006.259.08:09:20.59#ibcon#about to read 4, iclass 24, count 2 2006.259.08:09:20.59#ibcon#read 4, iclass 24, count 2 2006.259.08:09:20.59#ibcon#about to read 5, iclass 24, count 2 2006.259.08:09:20.59#ibcon#read 5, iclass 24, count 2 2006.259.08:09:20.59#ibcon#about to read 6, iclass 24, count 2 2006.259.08:09:20.59#ibcon#read 6, iclass 24, count 2 2006.259.08:09:20.59#ibcon#end of sib2, iclass 24, count 2 2006.259.08:09:20.59#ibcon#*after write, iclass 24, count 2 2006.259.08:09:20.59#ibcon#*before return 0, iclass 24, count 2 2006.259.08:09:20.59#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.259.08:09:20.59#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.259.08:09:20.59#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.259.08:09:20.59#ibcon#ireg 7 cls_cnt 0 2006.259.08:09:20.59#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.259.08:09:20.71#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.259.08:09:20.71#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.259.08:09:20.71#ibcon#enter wrdev, iclass 24, count 0 2006.259.08:09:20.71#ibcon#first serial, iclass 24, count 0 2006.259.08:09:20.71#ibcon#enter sib2, iclass 24, count 0 2006.259.08:09:20.71#ibcon#flushed, iclass 24, count 0 2006.259.08:09:20.71#ibcon#about to write, iclass 24, count 0 2006.259.08:09:20.71#ibcon#wrote, iclass 24, count 0 2006.259.08:09:20.71#ibcon#about to read 3, iclass 24, count 0 2006.259.08:09:20.73#ibcon#read 3, iclass 24, count 0 2006.259.08:09:20.73#ibcon#about to read 4, iclass 24, count 0 2006.259.08:09:20.73#ibcon#read 4, iclass 24, count 0 2006.259.08:09:20.73#ibcon#about to read 5, iclass 24, count 0 2006.259.08:09:20.73#ibcon#read 5, iclass 24, count 0 2006.259.08:09:20.73#ibcon#about to read 6, iclass 24, count 0 2006.259.08:09:20.73#ibcon#read 6, iclass 24, count 0 2006.259.08:09:20.73#ibcon#end of sib2, iclass 24, count 0 2006.259.08:09:20.73#ibcon#*mode == 0, iclass 24, count 0 2006.259.08:09:20.73#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.259.08:09:20.73#ibcon#[25=USB\r\n] 2006.259.08:09:20.73#ibcon#*before write, iclass 24, count 0 2006.259.08:09:20.73#ibcon#enter sib2, iclass 24, count 0 2006.259.08:09:20.73#ibcon#flushed, iclass 24, count 0 2006.259.08:09:20.73#ibcon#about to write, iclass 24, count 0 2006.259.08:09:20.73#ibcon#wrote, iclass 24, count 0 2006.259.08:09:20.73#ibcon#about to read 3, iclass 24, count 0 2006.259.08:09:20.76#ibcon#read 3, iclass 24, count 0 2006.259.08:09:20.76#ibcon#about to read 4, iclass 24, count 0 2006.259.08:09:20.76#ibcon#read 4, iclass 24, count 0 2006.259.08:09:20.76#ibcon#about to read 5, iclass 24, count 0 2006.259.08:09:20.76#ibcon#read 5, iclass 24, count 0 2006.259.08:09:20.76#ibcon#about to read 6, iclass 24, count 0 2006.259.08:09:20.76#ibcon#read 6, iclass 24, count 0 2006.259.08:09:20.76#ibcon#end of sib2, iclass 24, count 0 2006.259.08:09:20.76#ibcon#*after write, iclass 24, count 0 2006.259.08:09:20.76#ibcon#*before return 0, iclass 24, count 0 2006.259.08:09:20.76#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.259.08:09:20.76#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.259.08:09:20.76#ibcon#about to clear, iclass 24 cls_cnt 0 2006.259.08:09:20.76#ibcon#cleared, iclass 24 cls_cnt 0 2006.259.08:09:20.76$vc4f8/valo=6,772.99 2006.259.08:09:20.76#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.259.08:09:20.76#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.259.08:09:20.76#ibcon#ireg 17 cls_cnt 0 2006.259.08:09:20.76#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.259.08:09:20.76#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.259.08:09:20.76#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.259.08:09:20.76#ibcon#enter wrdev, iclass 26, count 0 2006.259.08:09:20.76#ibcon#first serial, iclass 26, count 0 2006.259.08:09:20.76#ibcon#enter sib2, iclass 26, count 0 2006.259.08:09:20.76#ibcon#flushed, iclass 26, count 0 2006.259.08:09:20.76#ibcon#about to write, iclass 26, count 0 2006.259.08:09:20.76#ibcon#wrote, iclass 26, count 0 2006.259.08:09:20.76#ibcon#about to read 3, iclass 26, count 0 2006.259.08:09:20.78#ibcon#read 3, iclass 26, count 0 2006.259.08:09:20.78#ibcon#about to read 4, iclass 26, count 0 2006.259.08:09:20.78#ibcon#read 4, iclass 26, count 0 2006.259.08:09:20.78#ibcon#about to read 5, iclass 26, count 0 2006.259.08:09:20.78#ibcon#read 5, iclass 26, count 0 2006.259.08:09:20.78#ibcon#about to read 6, iclass 26, count 0 2006.259.08:09:20.78#ibcon#read 6, iclass 26, count 0 2006.259.08:09:20.78#ibcon#end of sib2, iclass 26, count 0 2006.259.08:09:20.78#ibcon#*mode == 0, iclass 26, count 0 2006.259.08:09:20.78#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.259.08:09:20.78#ibcon#[26=FRQ=06,772.99\r\n] 2006.259.08:09:20.78#ibcon#*before write, iclass 26, count 0 2006.259.08:09:20.78#ibcon#enter sib2, iclass 26, count 0 2006.259.08:09:20.78#ibcon#flushed, iclass 26, count 0 2006.259.08:09:20.78#ibcon#about to write, iclass 26, count 0 2006.259.08:09:20.78#ibcon#wrote, iclass 26, count 0 2006.259.08:09:20.78#ibcon#about to read 3, iclass 26, count 0 2006.259.08:09:20.82#ibcon#read 3, iclass 26, count 0 2006.259.08:09:20.82#ibcon#about to read 4, iclass 26, count 0 2006.259.08:09:20.82#ibcon#read 4, iclass 26, count 0 2006.259.08:09:20.82#ibcon#about to read 5, iclass 26, count 0 2006.259.08:09:20.82#ibcon#read 5, iclass 26, count 0 2006.259.08:09:20.82#ibcon#about to read 6, iclass 26, count 0 2006.259.08:09:20.82#ibcon#read 6, iclass 26, count 0 2006.259.08:09:20.82#ibcon#end of sib2, iclass 26, count 0 2006.259.08:09:20.82#ibcon#*after write, iclass 26, count 0 2006.259.08:09:20.82#ibcon#*before return 0, iclass 26, count 0 2006.259.08:09:20.82#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.259.08:09:20.82#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.259.08:09:20.82#ibcon#about to clear, iclass 26 cls_cnt 0 2006.259.08:09:20.82#ibcon#cleared, iclass 26 cls_cnt 0 2006.259.08:09:20.82$vc4f8/va=6,6 2006.259.08:09:20.82#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.259.08:09:20.82#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.259.08:09:20.82#ibcon#ireg 11 cls_cnt 2 2006.259.08:09:20.82#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.259.08:09:20.88#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.259.08:09:20.88#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.259.08:09:20.88#ibcon#enter wrdev, iclass 28, count 2 2006.259.08:09:20.88#ibcon#first serial, iclass 28, count 2 2006.259.08:09:20.88#ibcon#enter sib2, iclass 28, count 2 2006.259.08:09:20.88#ibcon#flushed, iclass 28, count 2 2006.259.08:09:20.88#ibcon#about to write, iclass 28, count 2 2006.259.08:09:20.88#ibcon#wrote, iclass 28, count 2 2006.259.08:09:20.88#ibcon#about to read 3, iclass 28, count 2 2006.259.08:09:20.90#ibcon#read 3, iclass 28, count 2 2006.259.08:09:20.90#ibcon#about to read 4, iclass 28, count 2 2006.259.08:09:20.90#ibcon#read 4, iclass 28, count 2 2006.259.08:09:20.90#ibcon#about to read 5, iclass 28, count 2 2006.259.08:09:20.90#ibcon#read 5, iclass 28, count 2 2006.259.08:09:20.90#ibcon#about to read 6, iclass 28, count 2 2006.259.08:09:20.90#ibcon#read 6, iclass 28, count 2 2006.259.08:09:20.90#ibcon#end of sib2, iclass 28, count 2 2006.259.08:09:20.90#ibcon#*mode == 0, iclass 28, count 2 2006.259.08:09:20.90#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.259.08:09:20.90#ibcon#[25=AT06-06\r\n] 2006.259.08:09:20.90#ibcon#*before write, iclass 28, count 2 2006.259.08:09:20.90#ibcon#enter sib2, iclass 28, count 2 2006.259.08:09:20.90#ibcon#flushed, iclass 28, count 2 2006.259.08:09:20.90#ibcon#about to write, iclass 28, count 2 2006.259.08:09:20.90#ibcon#wrote, iclass 28, count 2 2006.259.08:09:20.90#ibcon#about to read 3, iclass 28, count 2 2006.259.08:09:20.93#ibcon#read 3, iclass 28, count 2 2006.259.08:09:20.93#ibcon#about to read 4, iclass 28, count 2 2006.259.08:09:20.93#ibcon#read 4, iclass 28, count 2 2006.259.08:09:20.93#ibcon#about to read 5, iclass 28, count 2 2006.259.08:09:20.93#ibcon#read 5, iclass 28, count 2 2006.259.08:09:20.93#ibcon#about to read 6, iclass 28, count 2 2006.259.08:09:20.93#ibcon#read 6, iclass 28, count 2 2006.259.08:09:20.93#ibcon#end of sib2, iclass 28, count 2 2006.259.08:09:20.93#ibcon#*after write, iclass 28, count 2 2006.259.08:09:20.93#ibcon#*before return 0, iclass 28, count 2 2006.259.08:09:20.93#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.259.08:09:20.93#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.259.08:09:20.93#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.259.08:09:20.93#ibcon#ireg 7 cls_cnt 0 2006.259.08:09:20.93#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.259.08:09:21.05#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.259.08:09:21.05#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.259.08:09:21.05#ibcon#enter wrdev, iclass 28, count 0 2006.259.08:09:21.05#ibcon#first serial, iclass 28, count 0 2006.259.08:09:21.05#ibcon#enter sib2, iclass 28, count 0 2006.259.08:09:21.05#ibcon#flushed, iclass 28, count 0 2006.259.08:09:21.05#ibcon#about to write, iclass 28, count 0 2006.259.08:09:21.05#ibcon#wrote, iclass 28, count 0 2006.259.08:09:21.05#ibcon#about to read 3, iclass 28, count 0 2006.259.08:09:21.07#ibcon#read 3, iclass 28, count 0 2006.259.08:09:21.07#ibcon#about to read 4, iclass 28, count 0 2006.259.08:09:21.07#ibcon#read 4, iclass 28, count 0 2006.259.08:09:21.07#ibcon#about to read 5, iclass 28, count 0 2006.259.08:09:21.07#ibcon#read 5, iclass 28, count 0 2006.259.08:09:21.07#ibcon#about to read 6, iclass 28, count 0 2006.259.08:09:21.07#ibcon#read 6, iclass 28, count 0 2006.259.08:09:21.07#ibcon#end of sib2, iclass 28, count 0 2006.259.08:09:21.07#ibcon#*mode == 0, iclass 28, count 0 2006.259.08:09:21.07#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.259.08:09:21.07#ibcon#[25=USB\r\n] 2006.259.08:09:21.07#ibcon#*before write, iclass 28, count 0 2006.259.08:09:21.07#ibcon#enter sib2, iclass 28, count 0 2006.259.08:09:21.07#ibcon#flushed, iclass 28, count 0 2006.259.08:09:21.07#ibcon#about to write, iclass 28, count 0 2006.259.08:09:21.07#ibcon#wrote, iclass 28, count 0 2006.259.08:09:21.07#ibcon#about to read 3, iclass 28, count 0 2006.259.08:09:21.10#ibcon#read 3, iclass 28, count 0 2006.259.08:09:21.10#ibcon#about to read 4, iclass 28, count 0 2006.259.08:09:21.10#ibcon#read 4, iclass 28, count 0 2006.259.08:09:21.10#ibcon#about to read 5, iclass 28, count 0 2006.259.08:09:21.10#ibcon#read 5, iclass 28, count 0 2006.259.08:09:21.10#ibcon#about to read 6, iclass 28, count 0 2006.259.08:09:21.10#ibcon#read 6, iclass 28, count 0 2006.259.08:09:21.10#ibcon#end of sib2, iclass 28, count 0 2006.259.08:09:21.10#ibcon#*after write, iclass 28, count 0 2006.259.08:09:21.10#ibcon#*before return 0, iclass 28, count 0 2006.259.08:09:21.10#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.259.08:09:21.10#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.259.08:09:21.10#ibcon#about to clear, iclass 28 cls_cnt 0 2006.259.08:09:21.10#ibcon#cleared, iclass 28 cls_cnt 0 2006.259.08:09:21.10$vc4f8/valo=7,832.99 2006.259.08:09:21.10#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.259.08:09:21.10#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.259.08:09:21.10#ibcon#ireg 17 cls_cnt 0 2006.259.08:09:21.10#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.259.08:09:21.10#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.259.08:09:21.10#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.259.08:09:21.10#ibcon#enter wrdev, iclass 30, count 0 2006.259.08:09:21.10#ibcon#first serial, iclass 30, count 0 2006.259.08:09:21.10#ibcon#enter sib2, iclass 30, count 0 2006.259.08:09:21.10#ibcon#flushed, iclass 30, count 0 2006.259.08:09:21.10#ibcon#about to write, iclass 30, count 0 2006.259.08:09:21.10#ibcon#wrote, iclass 30, count 0 2006.259.08:09:21.10#ibcon#about to read 3, iclass 30, count 0 2006.259.08:09:21.12#ibcon#read 3, iclass 30, count 0 2006.259.08:09:21.12#ibcon#about to read 4, iclass 30, count 0 2006.259.08:09:21.12#ibcon#read 4, iclass 30, count 0 2006.259.08:09:21.12#ibcon#about to read 5, iclass 30, count 0 2006.259.08:09:21.12#ibcon#read 5, iclass 30, count 0 2006.259.08:09:21.12#ibcon#about to read 6, iclass 30, count 0 2006.259.08:09:21.12#ibcon#read 6, iclass 30, count 0 2006.259.08:09:21.12#ibcon#end of sib2, iclass 30, count 0 2006.259.08:09:21.12#ibcon#*mode == 0, iclass 30, count 0 2006.259.08:09:21.12#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.259.08:09:21.12#ibcon#[26=FRQ=07,832.99\r\n] 2006.259.08:09:21.12#ibcon#*before write, iclass 30, count 0 2006.259.08:09:21.12#ibcon#enter sib2, iclass 30, count 0 2006.259.08:09:21.12#ibcon#flushed, iclass 30, count 0 2006.259.08:09:21.12#ibcon#about to write, iclass 30, count 0 2006.259.08:09:21.12#ibcon#wrote, iclass 30, count 0 2006.259.08:09:21.12#ibcon#about to read 3, iclass 30, count 0 2006.259.08:09:21.16#ibcon#read 3, iclass 30, count 0 2006.259.08:09:21.16#ibcon#about to read 4, iclass 30, count 0 2006.259.08:09:21.16#ibcon#read 4, iclass 30, count 0 2006.259.08:09:21.16#ibcon#about to read 5, iclass 30, count 0 2006.259.08:09:21.16#ibcon#read 5, iclass 30, count 0 2006.259.08:09:21.16#ibcon#about to read 6, iclass 30, count 0 2006.259.08:09:21.16#ibcon#read 6, iclass 30, count 0 2006.259.08:09:21.16#ibcon#end of sib2, iclass 30, count 0 2006.259.08:09:21.16#ibcon#*after write, iclass 30, count 0 2006.259.08:09:21.16#ibcon#*before return 0, iclass 30, count 0 2006.259.08:09:21.16#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.259.08:09:21.16#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.259.08:09:21.16#ibcon#about to clear, iclass 30 cls_cnt 0 2006.259.08:09:21.16#ibcon#cleared, iclass 30 cls_cnt 0 2006.259.08:09:21.16$vc4f8/va=7,6 2006.259.08:09:21.16#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.259.08:09:21.16#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.259.08:09:21.16#ibcon#ireg 11 cls_cnt 2 2006.259.08:09:21.16#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.259.08:09:21.22#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.259.08:09:21.22#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.259.08:09:21.22#ibcon#enter wrdev, iclass 32, count 2 2006.259.08:09:21.22#ibcon#first serial, iclass 32, count 2 2006.259.08:09:21.22#ibcon#enter sib2, iclass 32, count 2 2006.259.08:09:21.22#ibcon#flushed, iclass 32, count 2 2006.259.08:09:21.22#ibcon#about to write, iclass 32, count 2 2006.259.08:09:21.22#ibcon#wrote, iclass 32, count 2 2006.259.08:09:21.22#ibcon#about to read 3, iclass 32, count 2 2006.259.08:09:21.24#ibcon#read 3, iclass 32, count 2 2006.259.08:09:21.24#ibcon#about to read 4, iclass 32, count 2 2006.259.08:09:21.24#ibcon#read 4, iclass 32, count 2 2006.259.08:09:21.24#ibcon#about to read 5, iclass 32, count 2 2006.259.08:09:21.24#ibcon#read 5, iclass 32, count 2 2006.259.08:09:21.24#ibcon#about to read 6, iclass 32, count 2 2006.259.08:09:21.24#ibcon#read 6, iclass 32, count 2 2006.259.08:09:21.24#ibcon#end of sib2, iclass 32, count 2 2006.259.08:09:21.24#ibcon#*mode == 0, iclass 32, count 2 2006.259.08:09:21.24#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.259.08:09:21.24#ibcon#[25=AT07-06\r\n] 2006.259.08:09:21.24#ibcon#*before write, iclass 32, count 2 2006.259.08:09:21.24#ibcon#enter sib2, iclass 32, count 2 2006.259.08:09:21.24#ibcon#flushed, iclass 32, count 2 2006.259.08:09:21.24#ibcon#about to write, iclass 32, count 2 2006.259.08:09:21.24#ibcon#wrote, iclass 32, count 2 2006.259.08:09:21.24#ibcon#about to read 3, iclass 32, count 2 2006.259.08:09:21.27#ibcon#read 3, iclass 32, count 2 2006.259.08:09:21.27#ibcon#about to read 4, iclass 32, count 2 2006.259.08:09:21.27#ibcon#read 4, iclass 32, count 2 2006.259.08:09:21.27#ibcon#about to read 5, iclass 32, count 2 2006.259.08:09:21.27#ibcon#read 5, iclass 32, count 2 2006.259.08:09:21.27#ibcon#about to read 6, iclass 32, count 2 2006.259.08:09:21.27#ibcon#read 6, iclass 32, count 2 2006.259.08:09:21.27#ibcon#end of sib2, iclass 32, count 2 2006.259.08:09:21.27#ibcon#*after write, iclass 32, count 2 2006.259.08:09:21.27#ibcon#*before return 0, iclass 32, count 2 2006.259.08:09:21.27#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.259.08:09:21.27#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.259.08:09:21.27#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.259.08:09:21.27#ibcon#ireg 7 cls_cnt 0 2006.259.08:09:21.27#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.259.08:09:21.39#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.259.08:09:21.39#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.259.08:09:21.39#ibcon#enter wrdev, iclass 32, count 0 2006.259.08:09:21.39#ibcon#first serial, iclass 32, count 0 2006.259.08:09:21.39#ibcon#enter sib2, iclass 32, count 0 2006.259.08:09:21.39#ibcon#flushed, iclass 32, count 0 2006.259.08:09:21.39#ibcon#about to write, iclass 32, count 0 2006.259.08:09:21.39#ibcon#wrote, iclass 32, count 0 2006.259.08:09:21.39#ibcon#about to read 3, iclass 32, count 0 2006.259.08:09:21.41#ibcon#read 3, iclass 32, count 0 2006.259.08:09:21.41#ibcon#about to read 4, iclass 32, count 0 2006.259.08:09:21.41#ibcon#read 4, iclass 32, count 0 2006.259.08:09:21.41#ibcon#about to read 5, iclass 32, count 0 2006.259.08:09:21.41#ibcon#read 5, iclass 32, count 0 2006.259.08:09:21.41#ibcon#about to read 6, iclass 32, count 0 2006.259.08:09:21.41#ibcon#read 6, iclass 32, count 0 2006.259.08:09:21.41#ibcon#end of sib2, iclass 32, count 0 2006.259.08:09:21.41#ibcon#*mode == 0, iclass 32, count 0 2006.259.08:09:21.41#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.259.08:09:21.41#ibcon#[25=USB\r\n] 2006.259.08:09:21.41#ibcon#*before write, iclass 32, count 0 2006.259.08:09:21.41#ibcon#enter sib2, iclass 32, count 0 2006.259.08:09:21.41#ibcon#flushed, iclass 32, count 0 2006.259.08:09:21.41#ibcon#about to write, iclass 32, count 0 2006.259.08:09:21.41#ibcon#wrote, iclass 32, count 0 2006.259.08:09:21.41#ibcon#about to read 3, iclass 32, count 0 2006.259.08:09:21.44#ibcon#read 3, iclass 32, count 0 2006.259.08:09:21.44#ibcon#about to read 4, iclass 32, count 0 2006.259.08:09:21.44#ibcon#read 4, iclass 32, count 0 2006.259.08:09:21.44#ibcon#about to read 5, iclass 32, count 0 2006.259.08:09:21.44#ibcon#read 5, iclass 32, count 0 2006.259.08:09:21.44#ibcon#about to read 6, iclass 32, count 0 2006.259.08:09:21.44#ibcon#read 6, iclass 32, count 0 2006.259.08:09:21.44#ibcon#end of sib2, iclass 32, count 0 2006.259.08:09:21.44#ibcon#*after write, iclass 32, count 0 2006.259.08:09:21.44#ibcon#*before return 0, iclass 32, count 0 2006.259.08:09:21.44#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.259.08:09:21.44#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.259.08:09:21.44#ibcon#about to clear, iclass 32 cls_cnt 0 2006.259.08:09:21.44#ibcon#cleared, iclass 32 cls_cnt 0 2006.259.08:09:21.44$vc4f8/valo=8,852.99 2006.259.08:09:21.44#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.259.08:09:21.44#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.259.08:09:21.44#ibcon#ireg 17 cls_cnt 0 2006.259.08:09:21.44#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.259.08:09:21.44#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.259.08:09:21.44#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.259.08:09:21.44#ibcon#enter wrdev, iclass 34, count 0 2006.259.08:09:21.44#ibcon#first serial, iclass 34, count 0 2006.259.08:09:21.44#ibcon#enter sib2, iclass 34, count 0 2006.259.08:09:21.44#ibcon#flushed, iclass 34, count 0 2006.259.08:09:21.44#ibcon#about to write, iclass 34, count 0 2006.259.08:09:21.44#ibcon#wrote, iclass 34, count 0 2006.259.08:09:21.44#ibcon#about to read 3, iclass 34, count 0 2006.259.08:09:21.46#ibcon#read 3, iclass 34, count 0 2006.259.08:09:21.46#ibcon#about to read 4, iclass 34, count 0 2006.259.08:09:21.46#ibcon#read 4, iclass 34, count 0 2006.259.08:09:21.46#ibcon#about to read 5, iclass 34, count 0 2006.259.08:09:21.46#ibcon#read 5, iclass 34, count 0 2006.259.08:09:21.46#ibcon#about to read 6, iclass 34, count 0 2006.259.08:09:21.46#ibcon#read 6, iclass 34, count 0 2006.259.08:09:21.46#ibcon#end of sib2, iclass 34, count 0 2006.259.08:09:21.46#ibcon#*mode == 0, iclass 34, count 0 2006.259.08:09:21.46#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.259.08:09:21.46#ibcon#[26=FRQ=08,852.99\r\n] 2006.259.08:09:21.46#ibcon#*before write, iclass 34, count 0 2006.259.08:09:21.46#ibcon#enter sib2, iclass 34, count 0 2006.259.08:09:21.46#ibcon#flushed, iclass 34, count 0 2006.259.08:09:21.46#ibcon#about to write, iclass 34, count 0 2006.259.08:09:21.46#ibcon#wrote, iclass 34, count 0 2006.259.08:09:21.46#ibcon#about to read 3, iclass 34, count 0 2006.259.08:09:21.51#ibcon#read 3, iclass 34, count 0 2006.259.08:09:21.51#ibcon#about to read 4, iclass 34, count 0 2006.259.08:09:21.51#ibcon#read 4, iclass 34, count 0 2006.259.08:09:21.51#ibcon#about to read 5, iclass 34, count 0 2006.259.08:09:21.51#ibcon#read 5, iclass 34, count 0 2006.259.08:09:21.51#ibcon#about to read 6, iclass 34, count 0 2006.259.08:09:21.51#ibcon#read 6, iclass 34, count 0 2006.259.08:09:21.51#ibcon#end of sib2, iclass 34, count 0 2006.259.08:09:21.51#ibcon#*after write, iclass 34, count 0 2006.259.08:09:21.51#ibcon#*before return 0, iclass 34, count 0 2006.259.08:09:21.51#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.259.08:09:21.51#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.259.08:09:21.51#ibcon#about to clear, iclass 34 cls_cnt 0 2006.259.08:09:21.51#ibcon#cleared, iclass 34 cls_cnt 0 2006.259.08:09:21.51$vc4f8/va=8,6 2006.259.08:09:21.51#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.259.08:09:21.51#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.259.08:09:21.51#ibcon#ireg 11 cls_cnt 2 2006.259.08:09:21.51#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.259.08:09:21.55#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.259.08:09:21.55#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.259.08:09:21.55#ibcon#enter wrdev, iclass 36, count 2 2006.259.08:09:21.55#ibcon#first serial, iclass 36, count 2 2006.259.08:09:21.55#ibcon#enter sib2, iclass 36, count 2 2006.259.08:09:21.55#ibcon#flushed, iclass 36, count 2 2006.259.08:09:21.55#ibcon#about to write, iclass 36, count 2 2006.259.08:09:21.55#ibcon#wrote, iclass 36, count 2 2006.259.08:09:21.55#ibcon#about to read 3, iclass 36, count 2 2006.259.08:09:21.57#ibcon#read 3, iclass 36, count 2 2006.259.08:09:21.57#ibcon#about to read 4, iclass 36, count 2 2006.259.08:09:21.57#ibcon#read 4, iclass 36, count 2 2006.259.08:09:21.57#ibcon#about to read 5, iclass 36, count 2 2006.259.08:09:21.57#ibcon#read 5, iclass 36, count 2 2006.259.08:09:21.57#ibcon#about to read 6, iclass 36, count 2 2006.259.08:09:21.57#ibcon#read 6, iclass 36, count 2 2006.259.08:09:21.57#ibcon#end of sib2, iclass 36, count 2 2006.259.08:09:21.57#ibcon#*mode == 0, iclass 36, count 2 2006.259.08:09:21.57#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.259.08:09:21.57#ibcon#[25=AT08-06\r\n] 2006.259.08:09:21.57#ibcon#*before write, iclass 36, count 2 2006.259.08:09:21.57#ibcon#enter sib2, iclass 36, count 2 2006.259.08:09:21.57#ibcon#flushed, iclass 36, count 2 2006.259.08:09:21.57#ibcon#about to write, iclass 36, count 2 2006.259.08:09:21.57#ibcon#wrote, iclass 36, count 2 2006.259.08:09:21.57#ibcon#about to read 3, iclass 36, count 2 2006.259.08:09:21.60#ibcon#read 3, iclass 36, count 2 2006.259.08:09:21.60#ibcon#about to read 4, iclass 36, count 2 2006.259.08:09:21.60#ibcon#read 4, iclass 36, count 2 2006.259.08:09:21.60#ibcon#about to read 5, iclass 36, count 2 2006.259.08:09:21.60#ibcon#read 5, iclass 36, count 2 2006.259.08:09:21.60#ibcon#about to read 6, iclass 36, count 2 2006.259.08:09:21.60#ibcon#read 6, iclass 36, count 2 2006.259.08:09:21.60#ibcon#end of sib2, iclass 36, count 2 2006.259.08:09:21.60#ibcon#*after write, iclass 36, count 2 2006.259.08:09:21.60#ibcon#*before return 0, iclass 36, count 2 2006.259.08:09:21.60#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.259.08:09:21.60#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.259.08:09:21.60#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.259.08:09:21.60#ibcon#ireg 7 cls_cnt 0 2006.259.08:09:21.60#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.259.08:09:21.72#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.259.08:09:21.72#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.259.08:09:21.72#ibcon#enter wrdev, iclass 36, count 0 2006.259.08:09:21.72#ibcon#first serial, iclass 36, count 0 2006.259.08:09:21.72#ibcon#enter sib2, iclass 36, count 0 2006.259.08:09:21.72#ibcon#flushed, iclass 36, count 0 2006.259.08:09:21.72#ibcon#about to write, iclass 36, count 0 2006.259.08:09:21.72#ibcon#wrote, iclass 36, count 0 2006.259.08:09:21.72#ibcon#about to read 3, iclass 36, count 0 2006.259.08:09:21.74#ibcon#read 3, iclass 36, count 0 2006.259.08:09:21.74#ibcon#about to read 4, iclass 36, count 0 2006.259.08:09:21.74#ibcon#read 4, iclass 36, count 0 2006.259.08:09:21.74#ibcon#about to read 5, iclass 36, count 0 2006.259.08:09:21.74#ibcon#read 5, iclass 36, count 0 2006.259.08:09:21.74#ibcon#about to read 6, iclass 36, count 0 2006.259.08:09:21.74#ibcon#read 6, iclass 36, count 0 2006.259.08:09:21.74#ibcon#end of sib2, iclass 36, count 0 2006.259.08:09:21.74#ibcon#*mode == 0, iclass 36, count 0 2006.259.08:09:21.74#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.259.08:09:21.74#ibcon#[25=USB\r\n] 2006.259.08:09:21.74#ibcon#*before write, iclass 36, count 0 2006.259.08:09:21.74#ibcon#enter sib2, iclass 36, count 0 2006.259.08:09:21.74#ibcon#flushed, iclass 36, count 0 2006.259.08:09:21.74#ibcon#about to write, iclass 36, count 0 2006.259.08:09:21.74#ibcon#wrote, iclass 36, count 0 2006.259.08:09:21.74#ibcon#about to read 3, iclass 36, count 0 2006.259.08:09:21.77#ibcon#read 3, iclass 36, count 0 2006.259.08:09:21.77#ibcon#about to read 4, iclass 36, count 0 2006.259.08:09:21.77#ibcon#read 4, iclass 36, count 0 2006.259.08:09:21.77#ibcon#about to read 5, iclass 36, count 0 2006.259.08:09:21.77#ibcon#read 5, iclass 36, count 0 2006.259.08:09:21.77#ibcon#about to read 6, iclass 36, count 0 2006.259.08:09:21.77#ibcon#read 6, iclass 36, count 0 2006.259.08:09:21.77#ibcon#end of sib2, iclass 36, count 0 2006.259.08:09:21.77#ibcon#*after write, iclass 36, count 0 2006.259.08:09:21.77#ibcon#*before return 0, iclass 36, count 0 2006.259.08:09:21.77#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.259.08:09:21.77#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.259.08:09:21.77#ibcon#about to clear, iclass 36 cls_cnt 0 2006.259.08:09:21.77#ibcon#cleared, iclass 36 cls_cnt 0 2006.259.08:09:21.77$vc4f8/vblo=1,632.99 2006.259.08:09:21.77#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.259.08:09:21.77#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.259.08:09:21.77#ibcon#ireg 17 cls_cnt 0 2006.259.08:09:21.77#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.259.08:09:21.77#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.259.08:09:21.77#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.259.08:09:21.77#ibcon#enter wrdev, iclass 38, count 0 2006.259.08:09:21.77#ibcon#first serial, iclass 38, count 0 2006.259.08:09:21.77#ibcon#enter sib2, iclass 38, count 0 2006.259.08:09:21.77#ibcon#flushed, iclass 38, count 0 2006.259.08:09:21.77#ibcon#about to write, iclass 38, count 0 2006.259.08:09:21.77#ibcon#wrote, iclass 38, count 0 2006.259.08:09:21.77#ibcon#about to read 3, iclass 38, count 0 2006.259.08:09:21.79#ibcon#read 3, iclass 38, count 0 2006.259.08:09:21.79#ibcon#about to read 4, iclass 38, count 0 2006.259.08:09:21.79#ibcon#read 4, iclass 38, count 0 2006.259.08:09:21.79#ibcon#about to read 5, iclass 38, count 0 2006.259.08:09:21.79#ibcon#read 5, iclass 38, count 0 2006.259.08:09:21.79#ibcon#about to read 6, iclass 38, count 0 2006.259.08:09:21.79#ibcon#read 6, iclass 38, count 0 2006.259.08:09:21.79#ibcon#end of sib2, iclass 38, count 0 2006.259.08:09:21.79#ibcon#*mode == 0, iclass 38, count 0 2006.259.08:09:21.79#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.259.08:09:21.79#ibcon#[28=FRQ=01,632.99\r\n] 2006.259.08:09:21.79#ibcon#*before write, iclass 38, count 0 2006.259.08:09:21.79#ibcon#enter sib2, iclass 38, count 0 2006.259.08:09:21.79#ibcon#flushed, iclass 38, count 0 2006.259.08:09:21.79#ibcon#about to write, iclass 38, count 0 2006.259.08:09:21.79#ibcon#wrote, iclass 38, count 0 2006.259.08:09:21.79#ibcon#about to read 3, iclass 38, count 0 2006.259.08:09:21.83#ibcon#read 3, iclass 38, count 0 2006.259.08:09:21.83#ibcon#about to read 4, iclass 38, count 0 2006.259.08:09:21.83#ibcon#read 4, iclass 38, count 0 2006.259.08:09:21.83#ibcon#about to read 5, iclass 38, count 0 2006.259.08:09:21.83#ibcon#read 5, iclass 38, count 0 2006.259.08:09:21.83#ibcon#about to read 6, iclass 38, count 0 2006.259.08:09:21.83#ibcon#read 6, iclass 38, count 0 2006.259.08:09:21.83#ibcon#end of sib2, iclass 38, count 0 2006.259.08:09:21.83#ibcon#*after write, iclass 38, count 0 2006.259.08:09:21.83#ibcon#*before return 0, iclass 38, count 0 2006.259.08:09:21.83#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.259.08:09:21.83#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.259.08:09:21.83#ibcon#about to clear, iclass 38 cls_cnt 0 2006.259.08:09:21.83#ibcon#cleared, iclass 38 cls_cnt 0 2006.259.08:09:21.83$vc4f8/vb=1,4 2006.259.08:09:21.83#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.259.08:09:21.83#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.259.08:09:21.83#ibcon#ireg 11 cls_cnt 2 2006.259.08:09:21.83#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.259.08:09:21.83#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.259.08:09:21.83#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.259.08:09:21.83#ibcon#enter wrdev, iclass 40, count 2 2006.259.08:09:21.83#ibcon#first serial, iclass 40, count 2 2006.259.08:09:21.83#ibcon#enter sib2, iclass 40, count 2 2006.259.08:09:21.83#ibcon#flushed, iclass 40, count 2 2006.259.08:09:21.83#ibcon#about to write, iclass 40, count 2 2006.259.08:09:21.83#ibcon#wrote, iclass 40, count 2 2006.259.08:09:21.83#ibcon#about to read 3, iclass 40, count 2 2006.259.08:09:21.85#ibcon#read 3, iclass 40, count 2 2006.259.08:09:21.85#ibcon#about to read 4, iclass 40, count 2 2006.259.08:09:21.85#ibcon#read 4, iclass 40, count 2 2006.259.08:09:21.85#ibcon#about to read 5, iclass 40, count 2 2006.259.08:09:21.85#ibcon#read 5, iclass 40, count 2 2006.259.08:09:21.85#ibcon#about to read 6, iclass 40, count 2 2006.259.08:09:21.85#ibcon#read 6, iclass 40, count 2 2006.259.08:09:21.85#ibcon#end of sib2, iclass 40, count 2 2006.259.08:09:21.85#ibcon#*mode == 0, iclass 40, count 2 2006.259.08:09:21.85#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.259.08:09:21.85#ibcon#[27=AT01-04\r\n] 2006.259.08:09:21.85#ibcon#*before write, iclass 40, count 2 2006.259.08:09:21.85#ibcon#enter sib2, iclass 40, count 2 2006.259.08:09:21.85#ibcon#flushed, iclass 40, count 2 2006.259.08:09:21.85#ibcon#about to write, iclass 40, count 2 2006.259.08:09:21.85#ibcon#wrote, iclass 40, count 2 2006.259.08:09:21.85#ibcon#about to read 3, iclass 40, count 2 2006.259.08:09:21.88#ibcon#read 3, iclass 40, count 2 2006.259.08:09:21.88#ibcon#about to read 4, iclass 40, count 2 2006.259.08:09:21.88#ibcon#read 4, iclass 40, count 2 2006.259.08:09:21.88#ibcon#about to read 5, iclass 40, count 2 2006.259.08:09:21.88#ibcon#read 5, iclass 40, count 2 2006.259.08:09:21.88#ibcon#about to read 6, iclass 40, count 2 2006.259.08:09:21.88#ibcon#read 6, iclass 40, count 2 2006.259.08:09:21.88#ibcon#end of sib2, iclass 40, count 2 2006.259.08:09:21.88#ibcon#*after write, iclass 40, count 2 2006.259.08:09:21.88#ibcon#*before return 0, iclass 40, count 2 2006.259.08:09:21.88#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.259.08:09:21.88#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.259.08:09:21.88#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.259.08:09:21.88#ibcon#ireg 7 cls_cnt 0 2006.259.08:09:21.88#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.259.08:09:22.00#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.259.08:09:22.00#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.259.08:09:22.00#ibcon#enter wrdev, iclass 40, count 0 2006.259.08:09:22.00#ibcon#first serial, iclass 40, count 0 2006.259.08:09:22.00#ibcon#enter sib2, iclass 40, count 0 2006.259.08:09:22.00#ibcon#flushed, iclass 40, count 0 2006.259.08:09:22.00#ibcon#about to write, iclass 40, count 0 2006.259.08:09:22.00#ibcon#wrote, iclass 40, count 0 2006.259.08:09:22.00#ibcon#about to read 3, iclass 40, count 0 2006.259.08:09:22.02#ibcon#read 3, iclass 40, count 0 2006.259.08:09:22.02#ibcon#about to read 4, iclass 40, count 0 2006.259.08:09:22.02#ibcon#read 4, iclass 40, count 0 2006.259.08:09:22.02#ibcon#about to read 5, iclass 40, count 0 2006.259.08:09:22.02#ibcon#read 5, iclass 40, count 0 2006.259.08:09:22.02#ibcon#about to read 6, iclass 40, count 0 2006.259.08:09:22.02#ibcon#read 6, iclass 40, count 0 2006.259.08:09:22.02#ibcon#end of sib2, iclass 40, count 0 2006.259.08:09:22.02#ibcon#*mode == 0, iclass 40, count 0 2006.259.08:09:22.02#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.259.08:09:22.02#ibcon#[27=USB\r\n] 2006.259.08:09:22.02#ibcon#*before write, iclass 40, count 0 2006.259.08:09:22.02#ibcon#enter sib2, iclass 40, count 0 2006.259.08:09:22.02#ibcon#flushed, iclass 40, count 0 2006.259.08:09:22.02#ibcon#about to write, iclass 40, count 0 2006.259.08:09:22.02#ibcon#wrote, iclass 40, count 0 2006.259.08:09:22.02#ibcon#about to read 3, iclass 40, count 0 2006.259.08:09:22.05#ibcon#read 3, iclass 40, count 0 2006.259.08:09:22.05#ibcon#about to read 4, iclass 40, count 0 2006.259.08:09:22.05#ibcon#read 4, iclass 40, count 0 2006.259.08:09:22.05#ibcon#about to read 5, iclass 40, count 0 2006.259.08:09:22.05#ibcon#read 5, iclass 40, count 0 2006.259.08:09:22.05#ibcon#about to read 6, iclass 40, count 0 2006.259.08:09:22.05#ibcon#read 6, iclass 40, count 0 2006.259.08:09:22.05#ibcon#end of sib2, iclass 40, count 0 2006.259.08:09:22.05#ibcon#*after write, iclass 40, count 0 2006.259.08:09:22.05#ibcon#*before return 0, iclass 40, count 0 2006.259.08:09:22.05#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.259.08:09:22.05#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.259.08:09:22.05#ibcon#about to clear, iclass 40 cls_cnt 0 2006.259.08:09:22.05#ibcon#cleared, iclass 40 cls_cnt 0 2006.259.08:09:22.05$vc4f8/vblo=2,640.99 2006.259.08:09:22.05#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.259.08:09:22.05#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.259.08:09:22.05#ibcon#ireg 17 cls_cnt 0 2006.259.08:09:22.05#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.259.08:09:22.05#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.259.08:09:22.05#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.259.08:09:22.05#ibcon#enter wrdev, iclass 4, count 0 2006.259.08:09:22.05#ibcon#first serial, iclass 4, count 0 2006.259.08:09:22.05#ibcon#enter sib2, iclass 4, count 0 2006.259.08:09:22.05#ibcon#flushed, iclass 4, count 0 2006.259.08:09:22.05#ibcon#about to write, iclass 4, count 0 2006.259.08:09:22.05#ibcon#wrote, iclass 4, count 0 2006.259.08:09:22.05#ibcon#about to read 3, iclass 4, count 0 2006.259.08:09:22.07#ibcon#read 3, iclass 4, count 0 2006.259.08:09:22.07#ibcon#about to read 4, iclass 4, count 0 2006.259.08:09:22.07#ibcon#read 4, iclass 4, count 0 2006.259.08:09:22.07#ibcon#about to read 5, iclass 4, count 0 2006.259.08:09:22.07#ibcon#read 5, iclass 4, count 0 2006.259.08:09:22.07#ibcon#about to read 6, iclass 4, count 0 2006.259.08:09:22.07#ibcon#read 6, iclass 4, count 0 2006.259.08:09:22.07#ibcon#end of sib2, iclass 4, count 0 2006.259.08:09:22.07#ibcon#*mode == 0, iclass 4, count 0 2006.259.08:09:22.07#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.259.08:09:22.07#ibcon#[28=FRQ=02,640.99\r\n] 2006.259.08:09:22.07#ibcon#*before write, iclass 4, count 0 2006.259.08:09:22.07#ibcon#enter sib2, iclass 4, count 0 2006.259.08:09:22.07#ibcon#flushed, iclass 4, count 0 2006.259.08:09:22.07#ibcon#about to write, iclass 4, count 0 2006.259.08:09:22.07#ibcon#wrote, iclass 4, count 0 2006.259.08:09:22.07#ibcon#about to read 3, iclass 4, count 0 2006.259.08:09:22.11#ibcon#read 3, iclass 4, count 0 2006.259.08:09:22.11#ibcon#about to read 4, iclass 4, count 0 2006.259.08:09:22.11#ibcon#read 4, iclass 4, count 0 2006.259.08:09:22.11#ibcon#about to read 5, iclass 4, count 0 2006.259.08:09:22.11#ibcon#read 5, iclass 4, count 0 2006.259.08:09:22.11#ibcon#about to read 6, iclass 4, count 0 2006.259.08:09:22.11#ibcon#read 6, iclass 4, count 0 2006.259.08:09:22.11#ibcon#end of sib2, iclass 4, count 0 2006.259.08:09:22.11#ibcon#*after write, iclass 4, count 0 2006.259.08:09:22.11#ibcon#*before return 0, iclass 4, count 0 2006.259.08:09:22.11#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.259.08:09:22.11#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.259.08:09:22.11#ibcon#about to clear, iclass 4 cls_cnt 0 2006.259.08:09:22.11#ibcon#cleared, iclass 4 cls_cnt 0 2006.259.08:09:22.11$vc4f8/vb=2,5 2006.259.08:09:22.11#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.259.08:09:22.11#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.259.08:09:22.11#ibcon#ireg 11 cls_cnt 2 2006.259.08:09:22.11#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.259.08:09:22.17#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.259.08:09:22.17#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.259.08:09:22.17#ibcon#enter wrdev, iclass 6, count 2 2006.259.08:09:22.17#ibcon#first serial, iclass 6, count 2 2006.259.08:09:22.17#ibcon#enter sib2, iclass 6, count 2 2006.259.08:09:22.17#ibcon#flushed, iclass 6, count 2 2006.259.08:09:22.17#ibcon#about to write, iclass 6, count 2 2006.259.08:09:22.17#ibcon#wrote, iclass 6, count 2 2006.259.08:09:22.17#ibcon#about to read 3, iclass 6, count 2 2006.259.08:09:22.19#ibcon#read 3, iclass 6, count 2 2006.259.08:09:22.19#ibcon#about to read 4, iclass 6, count 2 2006.259.08:09:22.19#ibcon#read 4, iclass 6, count 2 2006.259.08:09:22.19#ibcon#about to read 5, iclass 6, count 2 2006.259.08:09:22.19#ibcon#read 5, iclass 6, count 2 2006.259.08:09:22.19#ibcon#about to read 6, iclass 6, count 2 2006.259.08:09:22.19#ibcon#read 6, iclass 6, count 2 2006.259.08:09:22.19#ibcon#end of sib2, iclass 6, count 2 2006.259.08:09:22.19#ibcon#*mode == 0, iclass 6, count 2 2006.259.08:09:22.19#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.259.08:09:22.19#ibcon#[27=AT02-05\r\n] 2006.259.08:09:22.19#ibcon#*before write, iclass 6, count 2 2006.259.08:09:22.19#ibcon#enter sib2, iclass 6, count 2 2006.259.08:09:22.19#ibcon#flushed, iclass 6, count 2 2006.259.08:09:22.19#ibcon#about to write, iclass 6, count 2 2006.259.08:09:22.19#ibcon#wrote, iclass 6, count 2 2006.259.08:09:22.19#ibcon#about to read 3, iclass 6, count 2 2006.259.08:09:22.22#ibcon#read 3, iclass 6, count 2 2006.259.08:09:22.22#ibcon#about to read 4, iclass 6, count 2 2006.259.08:09:22.22#ibcon#read 4, iclass 6, count 2 2006.259.08:09:22.22#ibcon#about to read 5, iclass 6, count 2 2006.259.08:09:22.22#ibcon#read 5, iclass 6, count 2 2006.259.08:09:22.22#ibcon#about to read 6, iclass 6, count 2 2006.259.08:09:22.22#ibcon#read 6, iclass 6, count 2 2006.259.08:09:22.22#ibcon#end of sib2, iclass 6, count 2 2006.259.08:09:22.22#ibcon#*after write, iclass 6, count 2 2006.259.08:09:22.22#ibcon#*before return 0, iclass 6, count 2 2006.259.08:09:22.22#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.259.08:09:22.22#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.259.08:09:22.22#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.259.08:09:22.22#ibcon#ireg 7 cls_cnt 0 2006.259.08:09:22.22#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.259.08:09:22.34#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.259.08:09:22.34#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.259.08:09:22.34#ibcon#enter wrdev, iclass 6, count 0 2006.259.08:09:22.34#ibcon#first serial, iclass 6, count 0 2006.259.08:09:22.34#ibcon#enter sib2, iclass 6, count 0 2006.259.08:09:22.34#ibcon#flushed, iclass 6, count 0 2006.259.08:09:22.34#ibcon#about to write, iclass 6, count 0 2006.259.08:09:22.34#ibcon#wrote, iclass 6, count 0 2006.259.08:09:22.34#ibcon#about to read 3, iclass 6, count 0 2006.259.08:09:22.36#ibcon#read 3, iclass 6, count 0 2006.259.08:09:22.36#ibcon#about to read 4, iclass 6, count 0 2006.259.08:09:22.36#ibcon#read 4, iclass 6, count 0 2006.259.08:09:22.36#ibcon#about to read 5, iclass 6, count 0 2006.259.08:09:22.36#ibcon#read 5, iclass 6, count 0 2006.259.08:09:22.36#ibcon#about to read 6, iclass 6, count 0 2006.259.08:09:22.36#ibcon#read 6, iclass 6, count 0 2006.259.08:09:22.36#ibcon#end of sib2, iclass 6, count 0 2006.259.08:09:22.36#ibcon#*mode == 0, iclass 6, count 0 2006.259.08:09:22.36#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.259.08:09:22.36#ibcon#[27=USB\r\n] 2006.259.08:09:22.36#ibcon#*before write, iclass 6, count 0 2006.259.08:09:22.36#ibcon#enter sib2, iclass 6, count 0 2006.259.08:09:22.36#ibcon#flushed, iclass 6, count 0 2006.259.08:09:22.36#ibcon#about to write, iclass 6, count 0 2006.259.08:09:22.36#ibcon#wrote, iclass 6, count 0 2006.259.08:09:22.36#ibcon#about to read 3, iclass 6, count 0 2006.259.08:09:22.39#ibcon#read 3, iclass 6, count 0 2006.259.08:09:22.39#ibcon#about to read 4, iclass 6, count 0 2006.259.08:09:22.39#ibcon#read 4, iclass 6, count 0 2006.259.08:09:22.39#ibcon#about to read 5, iclass 6, count 0 2006.259.08:09:22.39#ibcon#read 5, iclass 6, count 0 2006.259.08:09:22.39#ibcon#about to read 6, iclass 6, count 0 2006.259.08:09:22.39#ibcon#read 6, iclass 6, count 0 2006.259.08:09:22.39#ibcon#end of sib2, iclass 6, count 0 2006.259.08:09:22.39#ibcon#*after write, iclass 6, count 0 2006.259.08:09:22.39#ibcon#*before return 0, iclass 6, count 0 2006.259.08:09:22.39#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.259.08:09:22.39#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.259.08:09:22.39#ibcon#about to clear, iclass 6 cls_cnt 0 2006.259.08:09:22.39#ibcon#cleared, iclass 6 cls_cnt 0 2006.259.08:09:22.39$vc4f8/vblo=3,656.99 2006.259.08:09:22.39#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.259.08:09:22.39#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.259.08:09:22.39#ibcon#ireg 17 cls_cnt 0 2006.259.08:09:22.39#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.259.08:09:22.39#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.259.08:09:22.39#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.259.08:09:22.39#ibcon#enter wrdev, iclass 10, count 0 2006.259.08:09:22.39#ibcon#first serial, iclass 10, count 0 2006.259.08:09:22.39#ibcon#enter sib2, iclass 10, count 0 2006.259.08:09:22.39#ibcon#flushed, iclass 10, count 0 2006.259.08:09:22.39#ibcon#about to write, iclass 10, count 0 2006.259.08:09:22.39#ibcon#wrote, iclass 10, count 0 2006.259.08:09:22.39#ibcon#about to read 3, iclass 10, count 0 2006.259.08:09:22.41#ibcon#read 3, iclass 10, count 0 2006.259.08:09:22.41#ibcon#about to read 4, iclass 10, count 0 2006.259.08:09:22.41#ibcon#read 4, iclass 10, count 0 2006.259.08:09:22.41#ibcon#about to read 5, iclass 10, count 0 2006.259.08:09:22.41#ibcon#read 5, iclass 10, count 0 2006.259.08:09:22.41#ibcon#about to read 6, iclass 10, count 0 2006.259.08:09:22.41#ibcon#read 6, iclass 10, count 0 2006.259.08:09:22.41#ibcon#end of sib2, iclass 10, count 0 2006.259.08:09:22.41#ibcon#*mode == 0, iclass 10, count 0 2006.259.08:09:22.41#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.259.08:09:22.41#ibcon#[28=FRQ=03,656.99\r\n] 2006.259.08:09:22.41#ibcon#*before write, iclass 10, count 0 2006.259.08:09:22.41#ibcon#enter sib2, iclass 10, count 0 2006.259.08:09:22.41#ibcon#flushed, iclass 10, count 0 2006.259.08:09:22.41#ibcon#about to write, iclass 10, count 0 2006.259.08:09:22.41#ibcon#wrote, iclass 10, count 0 2006.259.08:09:22.41#ibcon#about to read 3, iclass 10, count 0 2006.259.08:09:22.45#ibcon#read 3, iclass 10, count 0 2006.259.08:09:22.45#ibcon#about to read 4, iclass 10, count 0 2006.259.08:09:22.45#ibcon#read 4, iclass 10, count 0 2006.259.08:09:22.45#ibcon#about to read 5, iclass 10, count 0 2006.259.08:09:22.45#ibcon#read 5, iclass 10, count 0 2006.259.08:09:22.45#ibcon#about to read 6, iclass 10, count 0 2006.259.08:09:22.45#ibcon#read 6, iclass 10, count 0 2006.259.08:09:22.45#ibcon#end of sib2, iclass 10, count 0 2006.259.08:09:22.45#ibcon#*after write, iclass 10, count 0 2006.259.08:09:22.45#ibcon#*before return 0, iclass 10, count 0 2006.259.08:09:22.45#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.259.08:09:22.45#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.259.08:09:22.45#ibcon#about to clear, iclass 10 cls_cnt 0 2006.259.08:09:22.45#ibcon#cleared, iclass 10 cls_cnt 0 2006.259.08:09:22.45$vc4f8/vb=3,4 2006.259.08:09:22.45#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.259.08:09:22.45#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.259.08:09:22.45#ibcon#ireg 11 cls_cnt 2 2006.259.08:09:22.45#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.259.08:09:22.51#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.259.08:09:22.51#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.259.08:09:22.51#ibcon#enter wrdev, iclass 12, count 2 2006.259.08:09:22.51#ibcon#first serial, iclass 12, count 2 2006.259.08:09:22.51#ibcon#enter sib2, iclass 12, count 2 2006.259.08:09:22.51#ibcon#flushed, iclass 12, count 2 2006.259.08:09:22.51#ibcon#about to write, iclass 12, count 2 2006.259.08:09:22.51#ibcon#wrote, iclass 12, count 2 2006.259.08:09:22.51#ibcon#about to read 3, iclass 12, count 2 2006.259.08:09:22.53#ibcon#read 3, iclass 12, count 2 2006.259.08:09:22.53#ibcon#about to read 4, iclass 12, count 2 2006.259.08:09:22.53#ibcon#read 4, iclass 12, count 2 2006.259.08:09:22.53#ibcon#about to read 5, iclass 12, count 2 2006.259.08:09:22.53#ibcon#read 5, iclass 12, count 2 2006.259.08:09:22.53#ibcon#about to read 6, iclass 12, count 2 2006.259.08:09:22.53#ibcon#read 6, iclass 12, count 2 2006.259.08:09:22.53#ibcon#end of sib2, iclass 12, count 2 2006.259.08:09:22.53#ibcon#*mode == 0, iclass 12, count 2 2006.259.08:09:22.53#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.259.08:09:22.53#ibcon#[27=AT03-04\r\n] 2006.259.08:09:22.53#ibcon#*before write, iclass 12, count 2 2006.259.08:09:22.53#ibcon#enter sib2, iclass 12, count 2 2006.259.08:09:22.53#ibcon#flushed, iclass 12, count 2 2006.259.08:09:22.53#ibcon#about to write, iclass 12, count 2 2006.259.08:09:22.53#ibcon#wrote, iclass 12, count 2 2006.259.08:09:22.53#ibcon#about to read 3, iclass 12, count 2 2006.259.08:09:22.56#ibcon#read 3, iclass 12, count 2 2006.259.08:09:22.56#ibcon#about to read 4, iclass 12, count 2 2006.259.08:09:22.56#ibcon#read 4, iclass 12, count 2 2006.259.08:09:22.56#ibcon#about to read 5, iclass 12, count 2 2006.259.08:09:22.56#ibcon#read 5, iclass 12, count 2 2006.259.08:09:22.56#ibcon#about to read 6, iclass 12, count 2 2006.259.08:09:22.56#ibcon#read 6, iclass 12, count 2 2006.259.08:09:22.56#ibcon#end of sib2, iclass 12, count 2 2006.259.08:09:22.56#ibcon#*after write, iclass 12, count 2 2006.259.08:09:22.56#ibcon#*before return 0, iclass 12, count 2 2006.259.08:09:22.56#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.259.08:09:22.56#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.259.08:09:22.56#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.259.08:09:22.56#ibcon#ireg 7 cls_cnt 0 2006.259.08:09:22.56#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.259.08:09:22.68#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.259.08:09:22.68#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.259.08:09:22.68#ibcon#enter wrdev, iclass 12, count 0 2006.259.08:09:22.68#ibcon#first serial, iclass 12, count 0 2006.259.08:09:22.68#ibcon#enter sib2, iclass 12, count 0 2006.259.08:09:22.68#ibcon#flushed, iclass 12, count 0 2006.259.08:09:22.68#ibcon#about to write, iclass 12, count 0 2006.259.08:09:22.68#ibcon#wrote, iclass 12, count 0 2006.259.08:09:22.68#ibcon#about to read 3, iclass 12, count 0 2006.259.08:09:22.70#ibcon#read 3, iclass 12, count 0 2006.259.08:09:22.70#ibcon#about to read 4, iclass 12, count 0 2006.259.08:09:22.70#ibcon#read 4, iclass 12, count 0 2006.259.08:09:22.70#ibcon#about to read 5, iclass 12, count 0 2006.259.08:09:22.70#ibcon#read 5, iclass 12, count 0 2006.259.08:09:22.70#ibcon#about to read 6, iclass 12, count 0 2006.259.08:09:22.70#ibcon#read 6, iclass 12, count 0 2006.259.08:09:22.70#ibcon#end of sib2, iclass 12, count 0 2006.259.08:09:22.70#ibcon#*mode == 0, iclass 12, count 0 2006.259.08:09:22.70#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.259.08:09:22.70#ibcon#[27=USB\r\n] 2006.259.08:09:22.70#ibcon#*before write, iclass 12, count 0 2006.259.08:09:22.70#ibcon#enter sib2, iclass 12, count 0 2006.259.08:09:22.70#ibcon#flushed, iclass 12, count 0 2006.259.08:09:22.70#ibcon#about to write, iclass 12, count 0 2006.259.08:09:22.70#ibcon#wrote, iclass 12, count 0 2006.259.08:09:22.70#ibcon#about to read 3, iclass 12, count 0 2006.259.08:09:22.73#ibcon#read 3, iclass 12, count 0 2006.259.08:09:22.73#ibcon#about to read 4, iclass 12, count 0 2006.259.08:09:22.73#ibcon#read 4, iclass 12, count 0 2006.259.08:09:22.73#ibcon#about to read 5, iclass 12, count 0 2006.259.08:09:22.73#ibcon#read 5, iclass 12, count 0 2006.259.08:09:22.73#ibcon#about to read 6, iclass 12, count 0 2006.259.08:09:22.73#ibcon#read 6, iclass 12, count 0 2006.259.08:09:22.73#ibcon#end of sib2, iclass 12, count 0 2006.259.08:09:22.73#ibcon#*after write, iclass 12, count 0 2006.259.08:09:22.73#ibcon#*before return 0, iclass 12, count 0 2006.259.08:09:22.73#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.259.08:09:22.73#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.259.08:09:22.73#ibcon#about to clear, iclass 12 cls_cnt 0 2006.259.08:09:22.73#ibcon#cleared, iclass 12 cls_cnt 0 2006.259.08:09:22.73$vc4f8/vblo=4,712.99 2006.259.08:09:22.73#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.259.08:09:22.73#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.259.08:09:22.73#ibcon#ireg 17 cls_cnt 0 2006.259.08:09:22.73#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.259.08:09:22.73#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.259.08:09:22.73#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.259.08:09:22.73#ibcon#enter wrdev, iclass 14, count 0 2006.259.08:09:22.73#ibcon#first serial, iclass 14, count 0 2006.259.08:09:22.73#ibcon#enter sib2, iclass 14, count 0 2006.259.08:09:22.73#ibcon#flushed, iclass 14, count 0 2006.259.08:09:22.73#ibcon#about to write, iclass 14, count 0 2006.259.08:09:22.73#ibcon#wrote, iclass 14, count 0 2006.259.08:09:22.73#ibcon#about to read 3, iclass 14, count 0 2006.259.08:09:22.75#ibcon#read 3, iclass 14, count 0 2006.259.08:09:22.75#ibcon#about to read 4, iclass 14, count 0 2006.259.08:09:22.75#ibcon#read 4, iclass 14, count 0 2006.259.08:09:22.75#ibcon#about to read 5, iclass 14, count 0 2006.259.08:09:22.75#ibcon#read 5, iclass 14, count 0 2006.259.08:09:22.75#ibcon#about to read 6, iclass 14, count 0 2006.259.08:09:22.75#ibcon#read 6, iclass 14, count 0 2006.259.08:09:22.75#ibcon#end of sib2, iclass 14, count 0 2006.259.08:09:22.75#ibcon#*mode == 0, iclass 14, count 0 2006.259.08:09:22.75#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.259.08:09:22.75#ibcon#[28=FRQ=04,712.99\r\n] 2006.259.08:09:22.75#ibcon#*before write, iclass 14, count 0 2006.259.08:09:22.75#ibcon#enter sib2, iclass 14, count 0 2006.259.08:09:22.75#ibcon#flushed, iclass 14, count 0 2006.259.08:09:22.75#ibcon#about to write, iclass 14, count 0 2006.259.08:09:22.75#ibcon#wrote, iclass 14, count 0 2006.259.08:09:22.75#ibcon#about to read 3, iclass 14, count 0 2006.259.08:09:22.79#ibcon#read 3, iclass 14, count 0 2006.259.08:09:22.79#ibcon#about to read 4, iclass 14, count 0 2006.259.08:09:22.79#ibcon#read 4, iclass 14, count 0 2006.259.08:09:22.79#ibcon#about to read 5, iclass 14, count 0 2006.259.08:09:22.79#ibcon#read 5, iclass 14, count 0 2006.259.08:09:22.79#ibcon#about to read 6, iclass 14, count 0 2006.259.08:09:22.79#ibcon#read 6, iclass 14, count 0 2006.259.08:09:22.79#ibcon#end of sib2, iclass 14, count 0 2006.259.08:09:22.79#ibcon#*after write, iclass 14, count 0 2006.259.08:09:22.79#ibcon#*before return 0, iclass 14, count 0 2006.259.08:09:22.79#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.259.08:09:22.79#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.259.08:09:22.79#ibcon#about to clear, iclass 14 cls_cnt 0 2006.259.08:09:22.79#ibcon#cleared, iclass 14 cls_cnt 0 2006.259.08:09:22.79$vc4f8/vb=4,5 2006.259.08:09:22.79#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.259.08:09:22.79#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.259.08:09:22.79#ibcon#ireg 11 cls_cnt 2 2006.259.08:09:22.79#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.259.08:09:22.85#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.259.08:09:22.85#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.259.08:09:22.85#ibcon#enter wrdev, iclass 16, count 2 2006.259.08:09:22.85#ibcon#first serial, iclass 16, count 2 2006.259.08:09:22.85#ibcon#enter sib2, iclass 16, count 2 2006.259.08:09:22.85#ibcon#flushed, iclass 16, count 2 2006.259.08:09:22.85#ibcon#about to write, iclass 16, count 2 2006.259.08:09:22.85#ibcon#wrote, iclass 16, count 2 2006.259.08:09:22.85#ibcon#about to read 3, iclass 16, count 2 2006.259.08:09:22.87#ibcon#read 3, iclass 16, count 2 2006.259.08:09:22.87#ibcon#about to read 4, iclass 16, count 2 2006.259.08:09:22.87#ibcon#read 4, iclass 16, count 2 2006.259.08:09:22.87#ibcon#about to read 5, iclass 16, count 2 2006.259.08:09:22.87#ibcon#read 5, iclass 16, count 2 2006.259.08:09:22.87#ibcon#about to read 6, iclass 16, count 2 2006.259.08:09:22.87#ibcon#read 6, iclass 16, count 2 2006.259.08:09:22.87#ibcon#end of sib2, iclass 16, count 2 2006.259.08:09:22.87#ibcon#*mode == 0, iclass 16, count 2 2006.259.08:09:22.87#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.259.08:09:22.87#ibcon#[27=AT04-05\r\n] 2006.259.08:09:22.87#ibcon#*before write, iclass 16, count 2 2006.259.08:09:22.87#ibcon#enter sib2, iclass 16, count 2 2006.259.08:09:22.87#ibcon#flushed, iclass 16, count 2 2006.259.08:09:22.87#ibcon#about to write, iclass 16, count 2 2006.259.08:09:22.87#ibcon#wrote, iclass 16, count 2 2006.259.08:09:22.87#ibcon#about to read 3, iclass 16, count 2 2006.259.08:09:22.90#ibcon#read 3, iclass 16, count 2 2006.259.08:09:22.90#ibcon#about to read 4, iclass 16, count 2 2006.259.08:09:22.90#ibcon#read 4, iclass 16, count 2 2006.259.08:09:22.90#ibcon#about to read 5, iclass 16, count 2 2006.259.08:09:22.90#ibcon#read 5, iclass 16, count 2 2006.259.08:09:22.90#ibcon#about to read 6, iclass 16, count 2 2006.259.08:09:22.90#ibcon#read 6, iclass 16, count 2 2006.259.08:09:22.90#ibcon#end of sib2, iclass 16, count 2 2006.259.08:09:22.90#ibcon#*after write, iclass 16, count 2 2006.259.08:09:22.90#ibcon#*before return 0, iclass 16, count 2 2006.259.08:09:22.90#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.259.08:09:22.90#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.259.08:09:22.90#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.259.08:09:22.90#ibcon#ireg 7 cls_cnt 0 2006.259.08:09:22.90#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.259.08:09:23.02#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.259.08:09:23.02#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.259.08:09:23.02#ibcon#enter wrdev, iclass 16, count 0 2006.259.08:09:23.02#ibcon#first serial, iclass 16, count 0 2006.259.08:09:23.02#ibcon#enter sib2, iclass 16, count 0 2006.259.08:09:23.02#ibcon#flushed, iclass 16, count 0 2006.259.08:09:23.02#ibcon#about to write, iclass 16, count 0 2006.259.08:09:23.02#ibcon#wrote, iclass 16, count 0 2006.259.08:09:23.02#ibcon#about to read 3, iclass 16, count 0 2006.259.08:09:23.04#ibcon#read 3, iclass 16, count 0 2006.259.08:09:23.04#ibcon#about to read 4, iclass 16, count 0 2006.259.08:09:23.04#ibcon#read 4, iclass 16, count 0 2006.259.08:09:23.04#ibcon#about to read 5, iclass 16, count 0 2006.259.08:09:23.04#ibcon#read 5, iclass 16, count 0 2006.259.08:09:23.04#ibcon#about to read 6, iclass 16, count 0 2006.259.08:09:23.04#ibcon#read 6, iclass 16, count 0 2006.259.08:09:23.04#ibcon#end of sib2, iclass 16, count 0 2006.259.08:09:23.04#ibcon#*mode == 0, iclass 16, count 0 2006.259.08:09:23.04#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.259.08:09:23.04#ibcon#[27=USB\r\n] 2006.259.08:09:23.04#ibcon#*before write, iclass 16, count 0 2006.259.08:09:23.04#ibcon#enter sib2, iclass 16, count 0 2006.259.08:09:23.04#ibcon#flushed, iclass 16, count 0 2006.259.08:09:23.04#ibcon#about to write, iclass 16, count 0 2006.259.08:09:23.04#ibcon#wrote, iclass 16, count 0 2006.259.08:09:23.04#ibcon#about to read 3, iclass 16, count 0 2006.259.08:09:23.07#ibcon#read 3, iclass 16, count 0 2006.259.08:09:23.07#ibcon#about to read 4, iclass 16, count 0 2006.259.08:09:23.07#ibcon#read 4, iclass 16, count 0 2006.259.08:09:23.07#ibcon#about to read 5, iclass 16, count 0 2006.259.08:09:23.07#ibcon#read 5, iclass 16, count 0 2006.259.08:09:23.07#ibcon#about to read 6, iclass 16, count 0 2006.259.08:09:23.07#ibcon#read 6, iclass 16, count 0 2006.259.08:09:23.07#ibcon#end of sib2, iclass 16, count 0 2006.259.08:09:23.07#ibcon#*after write, iclass 16, count 0 2006.259.08:09:23.07#ibcon#*before return 0, iclass 16, count 0 2006.259.08:09:23.07#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.259.08:09:23.07#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.259.08:09:23.07#ibcon#about to clear, iclass 16 cls_cnt 0 2006.259.08:09:23.07#ibcon#cleared, iclass 16 cls_cnt 0 2006.259.08:09:23.07$vc4f8/vblo=5,744.99 2006.259.08:09:23.07#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.259.08:09:23.07#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.259.08:09:23.07#ibcon#ireg 17 cls_cnt 0 2006.259.08:09:23.07#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.259.08:09:23.07#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.259.08:09:23.07#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.259.08:09:23.07#ibcon#enter wrdev, iclass 18, count 0 2006.259.08:09:23.07#ibcon#first serial, iclass 18, count 0 2006.259.08:09:23.07#ibcon#enter sib2, iclass 18, count 0 2006.259.08:09:23.07#ibcon#flushed, iclass 18, count 0 2006.259.08:09:23.07#ibcon#about to write, iclass 18, count 0 2006.259.08:09:23.07#ibcon#wrote, iclass 18, count 0 2006.259.08:09:23.07#ibcon#about to read 3, iclass 18, count 0 2006.259.08:09:23.09#ibcon#read 3, iclass 18, count 0 2006.259.08:09:23.09#ibcon#about to read 4, iclass 18, count 0 2006.259.08:09:23.09#ibcon#read 4, iclass 18, count 0 2006.259.08:09:23.09#ibcon#about to read 5, iclass 18, count 0 2006.259.08:09:23.09#ibcon#read 5, iclass 18, count 0 2006.259.08:09:23.09#ibcon#about to read 6, iclass 18, count 0 2006.259.08:09:23.09#ibcon#read 6, iclass 18, count 0 2006.259.08:09:23.09#ibcon#end of sib2, iclass 18, count 0 2006.259.08:09:23.09#ibcon#*mode == 0, iclass 18, count 0 2006.259.08:09:23.09#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.259.08:09:23.09#ibcon#[28=FRQ=05,744.99\r\n] 2006.259.08:09:23.09#ibcon#*before write, iclass 18, count 0 2006.259.08:09:23.09#ibcon#enter sib2, iclass 18, count 0 2006.259.08:09:23.09#ibcon#flushed, iclass 18, count 0 2006.259.08:09:23.09#ibcon#about to write, iclass 18, count 0 2006.259.08:09:23.09#ibcon#wrote, iclass 18, count 0 2006.259.08:09:23.09#ibcon#about to read 3, iclass 18, count 0 2006.259.08:09:23.13#ibcon#read 3, iclass 18, count 0 2006.259.08:09:23.13#ibcon#about to read 4, iclass 18, count 0 2006.259.08:09:23.13#ibcon#read 4, iclass 18, count 0 2006.259.08:09:23.13#ibcon#about to read 5, iclass 18, count 0 2006.259.08:09:23.13#ibcon#read 5, iclass 18, count 0 2006.259.08:09:23.13#ibcon#about to read 6, iclass 18, count 0 2006.259.08:09:23.13#ibcon#read 6, iclass 18, count 0 2006.259.08:09:23.13#ibcon#end of sib2, iclass 18, count 0 2006.259.08:09:23.13#ibcon#*after write, iclass 18, count 0 2006.259.08:09:23.13#ibcon#*before return 0, iclass 18, count 0 2006.259.08:09:23.13#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.259.08:09:23.13#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.259.08:09:23.13#ibcon#about to clear, iclass 18 cls_cnt 0 2006.259.08:09:23.13#ibcon#cleared, iclass 18 cls_cnt 0 2006.259.08:09:23.13$vc4f8/vb=5,4 2006.259.08:09:23.13#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.259.08:09:23.13#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.259.08:09:23.13#ibcon#ireg 11 cls_cnt 2 2006.259.08:09:23.13#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.259.08:09:23.19#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.259.08:09:23.19#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.259.08:09:23.19#ibcon#enter wrdev, iclass 20, count 2 2006.259.08:09:23.19#ibcon#first serial, iclass 20, count 2 2006.259.08:09:23.19#ibcon#enter sib2, iclass 20, count 2 2006.259.08:09:23.19#ibcon#flushed, iclass 20, count 2 2006.259.08:09:23.19#ibcon#about to write, iclass 20, count 2 2006.259.08:09:23.19#ibcon#wrote, iclass 20, count 2 2006.259.08:09:23.19#ibcon#about to read 3, iclass 20, count 2 2006.259.08:09:23.21#ibcon#read 3, iclass 20, count 2 2006.259.08:09:23.21#ibcon#about to read 4, iclass 20, count 2 2006.259.08:09:23.21#ibcon#read 4, iclass 20, count 2 2006.259.08:09:23.21#ibcon#about to read 5, iclass 20, count 2 2006.259.08:09:23.21#ibcon#read 5, iclass 20, count 2 2006.259.08:09:23.21#ibcon#about to read 6, iclass 20, count 2 2006.259.08:09:23.21#ibcon#read 6, iclass 20, count 2 2006.259.08:09:23.21#ibcon#end of sib2, iclass 20, count 2 2006.259.08:09:23.21#ibcon#*mode == 0, iclass 20, count 2 2006.259.08:09:23.21#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.259.08:09:23.21#ibcon#[27=AT05-04\r\n] 2006.259.08:09:23.21#ibcon#*before write, iclass 20, count 2 2006.259.08:09:23.21#ibcon#enter sib2, iclass 20, count 2 2006.259.08:09:23.21#ibcon#flushed, iclass 20, count 2 2006.259.08:09:23.21#ibcon#about to write, iclass 20, count 2 2006.259.08:09:23.21#ibcon#wrote, iclass 20, count 2 2006.259.08:09:23.21#ibcon#about to read 3, iclass 20, count 2 2006.259.08:09:23.24#ibcon#read 3, iclass 20, count 2 2006.259.08:09:23.24#ibcon#about to read 4, iclass 20, count 2 2006.259.08:09:23.24#ibcon#read 4, iclass 20, count 2 2006.259.08:09:23.24#ibcon#about to read 5, iclass 20, count 2 2006.259.08:09:23.24#ibcon#read 5, iclass 20, count 2 2006.259.08:09:23.24#ibcon#about to read 6, iclass 20, count 2 2006.259.08:09:23.24#ibcon#read 6, iclass 20, count 2 2006.259.08:09:23.24#ibcon#end of sib2, iclass 20, count 2 2006.259.08:09:23.24#ibcon#*after write, iclass 20, count 2 2006.259.08:09:23.24#ibcon#*before return 0, iclass 20, count 2 2006.259.08:09:23.24#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.259.08:09:23.24#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.259.08:09:23.24#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.259.08:09:23.24#ibcon#ireg 7 cls_cnt 0 2006.259.08:09:23.24#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.259.08:09:23.36#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.259.08:09:23.36#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.259.08:09:23.36#ibcon#enter wrdev, iclass 20, count 0 2006.259.08:09:23.36#ibcon#first serial, iclass 20, count 0 2006.259.08:09:23.36#ibcon#enter sib2, iclass 20, count 0 2006.259.08:09:23.36#ibcon#flushed, iclass 20, count 0 2006.259.08:09:23.36#ibcon#about to write, iclass 20, count 0 2006.259.08:09:23.36#ibcon#wrote, iclass 20, count 0 2006.259.08:09:23.36#ibcon#about to read 3, iclass 20, count 0 2006.259.08:09:23.38#ibcon#read 3, iclass 20, count 0 2006.259.08:09:23.38#ibcon#about to read 4, iclass 20, count 0 2006.259.08:09:23.38#ibcon#read 4, iclass 20, count 0 2006.259.08:09:23.38#ibcon#about to read 5, iclass 20, count 0 2006.259.08:09:23.38#ibcon#read 5, iclass 20, count 0 2006.259.08:09:23.38#ibcon#about to read 6, iclass 20, count 0 2006.259.08:09:23.38#ibcon#read 6, iclass 20, count 0 2006.259.08:09:23.38#ibcon#end of sib2, iclass 20, count 0 2006.259.08:09:23.38#ibcon#*mode == 0, iclass 20, count 0 2006.259.08:09:23.38#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.259.08:09:23.38#ibcon#[27=USB\r\n] 2006.259.08:09:23.38#ibcon#*before write, iclass 20, count 0 2006.259.08:09:23.38#ibcon#enter sib2, iclass 20, count 0 2006.259.08:09:23.38#ibcon#flushed, iclass 20, count 0 2006.259.08:09:23.38#ibcon#about to write, iclass 20, count 0 2006.259.08:09:23.38#ibcon#wrote, iclass 20, count 0 2006.259.08:09:23.38#ibcon#about to read 3, iclass 20, count 0 2006.259.08:09:23.41#ibcon#read 3, iclass 20, count 0 2006.259.08:09:23.41#ibcon#about to read 4, iclass 20, count 0 2006.259.08:09:23.41#ibcon#read 4, iclass 20, count 0 2006.259.08:09:23.41#ibcon#about to read 5, iclass 20, count 0 2006.259.08:09:23.41#ibcon#read 5, iclass 20, count 0 2006.259.08:09:23.41#ibcon#about to read 6, iclass 20, count 0 2006.259.08:09:23.41#ibcon#read 6, iclass 20, count 0 2006.259.08:09:23.41#ibcon#end of sib2, iclass 20, count 0 2006.259.08:09:23.41#ibcon#*after write, iclass 20, count 0 2006.259.08:09:23.41#ibcon#*before return 0, iclass 20, count 0 2006.259.08:09:23.41#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.259.08:09:23.41#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.259.08:09:23.41#ibcon#about to clear, iclass 20 cls_cnt 0 2006.259.08:09:23.41#ibcon#cleared, iclass 20 cls_cnt 0 2006.259.08:09:23.41$vc4f8/vblo=6,752.99 2006.259.08:09:23.41#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.259.08:09:23.41#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.259.08:09:23.41#ibcon#ireg 17 cls_cnt 0 2006.259.08:09:23.41#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.259.08:09:23.41#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.259.08:09:23.41#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.259.08:09:23.41#ibcon#enter wrdev, iclass 22, count 0 2006.259.08:09:23.41#ibcon#first serial, iclass 22, count 0 2006.259.08:09:23.41#ibcon#enter sib2, iclass 22, count 0 2006.259.08:09:23.41#ibcon#flushed, iclass 22, count 0 2006.259.08:09:23.41#ibcon#about to write, iclass 22, count 0 2006.259.08:09:23.41#ibcon#wrote, iclass 22, count 0 2006.259.08:09:23.41#ibcon#about to read 3, iclass 22, count 0 2006.259.08:09:23.43#ibcon#read 3, iclass 22, count 0 2006.259.08:09:23.43#ibcon#about to read 4, iclass 22, count 0 2006.259.08:09:23.43#ibcon#read 4, iclass 22, count 0 2006.259.08:09:23.43#ibcon#about to read 5, iclass 22, count 0 2006.259.08:09:23.43#ibcon#read 5, iclass 22, count 0 2006.259.08:09:23.43#ibcon#about to read 6, iclass 22, count 0 2006.259.08:09:23.43#ibcon#read 6, iclass 22, count 0 2006.259.08:09:23.43#ibcon#end of sib2, iclass 22, count 0 2006.259.08:09:23.43#ibcon#*mode == 0, iclass 22, count 0 2006.259.08:09:23.43#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.259.08:09:23.43#ibcon#[28=FRQ=06,752.99\r\n] 2006.259.08:09:23.43#ibcon#*before write, iclass 22, count 0 2006.259.08:09:23.43#ibcon#enter sib2, iclass 22, count 0 2006.259.08:09:23.43#ibcon#flushed, iclass 22, count 0 2006.259.08:09:23.43#ibcon#about to write, iclass 22, count 0 2006.259.08:09:23.43#ibcon#wrote, iclass 22, count 0 2006.259.08:09:23.43#ibcon#about to read 3, iclass 22, count 0 2006.259.08:09:23.47#ibcon#read 3, iclass 22, count 0 2006.259.08:09:23.47#ibcon#about to read 4, iclass 22, count 0 2006.259.08:09:23.47#ibcon#read 4, iclass 22, count 0 2006.259.08:09:23.47#ibcon#about to read 5, iclass 22, count 0 2006.259.08:09:23.47#ibcon#read 5, iclass 22, count 0 2006.259.08:09:23.47#ibcon#about to read 6, iclass 22, count 0 2006.259.08:09:23.47#ibcon#read 6, iclass 22, count 0 2006.259.08:09:23.47#ibcon#end of sib2, iclass 22, count 0 2006.259.08:09:23.47#ibcon#*after write, iclass 22, count 0 2006.259.08:09:23.47#ibcon#*before return 0, iclass 22, count 0 2006.259.08:09:23.47#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.259.08:09:23.47#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.259.08:09:23.47#ibcon#about to clear, iclass 22 cls_cnt 0 2006.259.08:09:23.47#ibcon#cleared, iclass 22 cls_cnt 0 2006.259.08:09:23.47$vc4f8/vb=6,4 2006.259.08:09:23.47#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.259.08:09:23.47#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.259.08:09:23.47#ibcon#ireg 11 cls_cnt 2 2006.259.08:09:23.47#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.259.08:09:23.53#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.259.08:09:23.53#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.259.08:09:23.53#ibcon#enter wrdev, iclass 24, count 2 2006.259.08:09:23.53#ibcon#first serial, iclass 24, count 2 2006.259.08:09:23.53#ibcon#enter sib2, iclass 24, count 2 2006.259.08:09:23.53#ibcon#flushed, iclass 24, count 2 2006.259.08:09:23.53#ibcon#about to write, iclass 24, count 2 2006.259.08:09:23.53#ibcon#wrote, iclass 24, count 2 2006.259.08:09:23.53#ibcon#about to read 3, iclass 24, count 2 2006.259.08:09:23.55#ibcon#read 3, iclass 24, count 2 2006.259.08:09:23.55#ibcon#about to read 4, iclass 24, count 2 2006.259.08:09:23.55#ibcon#read 4, iclass 24, count 2 2006.259.08:09:23.55#ibcon#about to read 5, iclass 24, count 2 2006.259.08:09:23.55#ibcon#read 5, iclass 24, count 2 2006.259.08:09:23.55#ibcon#about to read 6, iclass 24, count 2 2006.259.08:09:23.55#ibcon#read 6, iclass 24, count 2 2006.259.08:09:23.55#ibcon#end of sib2, iclass 24, count 2 2006.259.08:09:23.55#ibcon#*mode == 0, iclass 24, count 2 2006.259.08:09:23.55#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.259.08:09:23.55#ibcon#[27=AT06-04\r\n] 2006.259.08:09:23.55#ibcon#*before write, iclass 24, count 2 2006.259.08:09:23.55#ibcon#enter sib2, iclass 24, count 2 2006.259.08:09:23.55#ibcon#flushed, iclass 24, count 2 2006.259.08:09:23.55#ibcon#about to write, iclass 24, count 2 2006.259.08:09:23.55#ibcon#wrote, iclass 24, count 2 2006.259.08:09:23.55#ibcon#about to read 3, iclass 24, count 2 2006.259.08:09:23.58#ibcon#read 3, iclass 24, count 2 2006.259.08:09:23.58#ibcon#about to read 4, iclass 24, count 2 2006.259.08:09:23.58#ibcon#read 4, iclass 24, count 2 2006.259.08:09:23.58#ibcon#about to read 5, iclass 24, count 2 2006.259.08:09:23.58#ibcon#read 5, iclass 24, count 2 2006.259.08:09:23.58#ibcon#about to read 6, iclass 24, count 2 2006.259.08:09:23.58#ibcon#read 6, iclass 24, count 2 2006.259.08:09:23.58#ibcon#end of sib2, iclass 24, count 2 2006.259.08:09:23.58#ibcon#*after write, iclass 24, count 2 2006.259.08:09:23.58#ibcon#*before return 0, iclass 24, count 2 2006.259.08:09:23.58#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.259.08:09:23.58#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.259.08:09:23.58#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.259.08:09:23.58#ibcon#ireg 7 cls_cnt 0 2006.259.08:09:23.58#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.259.08:09:23.70#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.259.08:09:23.70#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.259.08:09:23.70#ibcon#enter wrdev, iclass 24, count 0 2006.259.08:09:23.70#ibcon#first serial, iclass 24, count 0 2006.259.08:09:23.70#ibcon#enter sib2, iclass 24, count 0 2006.259.08:09:23.70#ibcon#flushed, iclass 24, count 0 2006.259.08:09:23.70#ibcon#about to write, iclass 24, count 0 2006.259.08:09:23.70#ibcon#wrote, iclass 24, count 0 2006.259.08:09:23.70#ibcon#about to read 3, iclass 24, count 0 2006.259.08:09:23.72#ibcon#read 3, iclass 24, count 0 2006.259.08:09:23.72#ibcon#about to read 4, iclass 24, count 0 2006.259.08:09:23.72#ibcon#read 4, iclass 24, count 0 2006.259.08:09:23.72#ibcon#about to read 5, iclass 24, count 0 2006.259.08:09:23.72#ibcon#read 5, iclass 24, count 0 2006.259.08:09:23.72#ibcon#about to read 6, iclass 24, count 0 2006.259.08:09:23.72#ibcon#read 6, iclass 24, count 0 2006.259.08:09:23.72#ibcon#end of sib2, iclass 24, count 0 2006.259.08:09:23.72#ibcon#*mode == 0, iclass 24, count 0 2006.259.08:09:23.72#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.259.08:09:23.72#ibcon#[27=USB\r\n] 2006.259.08:09:23.72#ibcon#*before write, iclass 24, count 0 2006.259.08:09:23.72#ibcon#enter sib2, iclass 24, count 0 2006.259.08:09:23.72#ibcon#flushed, iclass 24, count 0 2006.259.08:09:23.72#ibcon#about to write, iclass 24, count 0 2006.259.08:09:23.72#ibcon#wrote, iclass 24, count 0 2006.259.08:09:23.72#ibcon#about to read 3, iclass 24, count 0 2006.259.08:09:23.75#ibcon#read 3, iclass 24, count 0 2006.259.08:09:23.75#ibcon#about to read 4, iclass 24, count 0 2006.259.08:09:23.75#ibcon#read 4, iclass 24, count 0 2006.259.08:09:23.75#ibcon#about to read 5, iclass 24, count 0 2006.259.08:09:23.75#ibcon#read 5, iclass 24, count 0 2006.259.08:09:23.75#ibcon#about to read 6, iclass 24, count 0 2006.259.08:09:23.75#ibcon#read 6, iclass 24, count 0 2006.259.08:09:23.75#ibcon#end of sib2, iclass 24, count 0 2006.259.08:09:23.75#ibcon#*after write, iclass 24, count 0 2006.259.08:09:23.75#ibcon#*before return 0, iclass 24, count 0 2006.259.08:09:23.75#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.259.08:09:23.75#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.259.08:09:23.75#ibcon#about to clear, iclass 24 cls_cnt 0 2006.259.08:09:23.75#ibcon#cleared, iclass 24 cls_cnt 0 2006.259.08:09:23.75$vc4f8/vabw=wide 2006.259.08:09:23.75#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.259.08:09:23.75#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.259.08:09:23.75#ibcon#ireg 8 cls_cnt 0 2006.259.08:09:23.75#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.259.08:09:23.75#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.259.08:09:23.75#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.259.08:09:23.75#ibcon#enter wrdev, iclass 26, count 0 2006.259.08:09:23.75#ibcon#first serial, iclass 26, count 0 2006.259.08:09:23.75#ibcon#enter sib2, iclass 26, count 0 2006.259.08:09:23.75#ibcon#flushed, iclass 26, count 0 2006.259.08:09:23.75#ibcon#about to write, iclass 26, count 0 2006.259.08:09:23.75#ibcon#wrote, iclass 26, count 0 2006.259.08:09:23.75#ibcon#about to read 3, iclass 26, count 0 2006.259.08:09:23.77#ibcon#read 3, iclass 26, count 0 2006.259.08:09:23.77#ibcon#about to read 4, iclass 26, count 0 2006.259.08:09:23.77#ibcon#read 4, iclass 26, count 0 2006.259.08:09:23.77#ibcon#about to read 5, iclass 26, count 0 2006.259.08:09:23.77#ibcon#read 5, iclass 26, count 0 2006.259.08:09:23.77#ibcon#about to read 6, iclass 26, count 0 2006.259.08:09:23.77#ibcon#read 6, iclass 26, count 0 2006.259.08:09:23.77#ibcon#end of sib2, iclass 26, count 0 2006.259.08:09:23.77#ibcon#*mode == 0, iclass 26, count 0 2006.259.08:09:23.77#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.259.08:09:23.77#ibcon#[25=BW32\r\n] 2006.259.08:09:23.77#ibcon#*before write, iclass 26, count 0 2006.259.08:09:23.77#ibcon#enter sib2, iclass 26, count 0 2006.259.08:09:23.77#ibcon#flushed, iclass 26, count 0 2006.259.08:09:23.77#ibcon#about to write, iclass 26, count 0 2006.259.08:09:23.77#ibcon#wrote, iclass 26, count 0 2006.259.08:09:23.77#ibcon#about to read 3, iclass 26, count 0 2006.259.08:09:23.80#ibcon#read 3, iclass 26, count 0 2006.259.08:09:23.80#ibcon#about to read 4, iclass 26, count 0 2006.259.08:09:23.80#ibcon#read 4, iclass 26, count 0 2006.259.08:09:23.80#ibcon#about to read 5, iclass 26, count 0 2006.259.08:09:23.80#ibcon#read 5, iclass 26, count 0 2006.259.08:09:23.80#ibcon#about to read 6, iclass 26, count 0 2006.259.08:09:23.80#ibcon#read 6, iclass 26, count 0 2006.259.08:09:23.80#ibcon#end of sib2, iclass 26, count 0 2006.259.08:09:23.80#ibcon#*after write, iclass 26, count 0 2006.259.08:09:23.80#ibcon#*before return 0, iclass 26, count 0 2006.259.08:09:23.80#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.259.08:09:23.80#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.259.08:09:23.80#ibcon#about to clear, iclass 26 cls_cnt 0 2006.259.08:09:23.80#ibcon#cleared, iclass 26 cls_cnt 0 2006.259.08:09:23.80$vc4f8/vbbw=wide 2006.259.08:09:23.80#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.259.08:09:23.80#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.259.08:09:23.80#ibcon#ireg 8 cls_cnt 0 2006.259.08:09:23.80#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.259.08:09:23.87#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.259.08:09:23.87#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.259.08:09:23.87#ibcon#enter wrdev, iclass 28, count 0 2006.259.08:09:23.87#ibcon#first serial, iclass 28, count 0 2006.259.08:09:23.87#ibcon#enter sib2, iclass 28, count 0 2006.259.08:09:23.87#ibcon#flushed, iclass 28, count 0 2006.259.08:09:23.87#ibcon#about to write, iclass 28, count 0 2006.259.08:09:23.87#ibcon#wrote, iclass 28, count 0 2006.259.08:09:23.87#ibcon#about to read 3, iclass 28, count 0 2006.259.08:09:23.89#ibcon#read 3, iclass 28, count 0 2006.259.08:09:23.89#ibcon#about to read 4, iclass 28, count 0 2006.259.08:09:23.89#ibcon#read 4, iclass 28, count 0 2006.259.08:09:23.89#ibcon#about to read 5, iclass 28, count 0 2006.259.08:09:23.89#ibcon#read 5, iclass 28, count 0 2006.259.08:09:23.89#ibcon#about to read 6, iclass 28, count 0 2006.259.08:09:23.89#ibcon#read 6, iclass 28, count 0 2006.259.08:09:23.89#ibcon#end of sib2, iclass 28, count 0 2006.259.08:09:23.89#ibcon#*mode == 0, iclass 28, count 0 2006.259.08:09:23.89#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.259.08:09:23.89#ibcon#[27=BW32\r\n] 2006.259.08:09:23.89#ibcon#*before write, iclass 28, count 0 2006.259.08:09:23.89#ibcon#enter sib2, iclass 28, count 0 2006.259.08:09:23.89#ibcon#flushed, iclass 28, count 0 2006.259.08:09:23.89#ibcon#about to write, iclass 28, count 0 2006.259.08:09:23.89#ibcon#wrote, iclass 28, count 0 2006.259.08:09:23.89#ibcon#about to read 3, iclass 28, count 0 2006.259.08:09:23.92#ibcon#read 3, iclass 28, count 0 2006.259.08:09:23.92#ibcon#about to read 4, iclass 28, count 0 2006.259.08:09:23.92#ibcon#read 4, iclass 28, count 0 2006.259.08:09:23.92#ibcon#about to read 5, iclass 28, count 0 2006.259.08:09:23.92#ibcon#read 5, iclass 28, count 0 2006.259.08:09:23.92#ibcon#about to read 6, iclass 28, count 0 2006.259.08:09:23.92#ibcon#read 6, iclass 28, count 0 2006.259.08:09:23.92#ibcon#end of sib2, iclass 28, count 0 2006.259.08:09:23.92#ibcon#*after write, iclass 28, count 0 2006.259.08:09:23.92#ibcon#*before return 0, iclass 28, count 0 2006.259.08:09:23.92#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.259.08:09:23.92#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.259.08:09:23.92#ibcon#about to clear, iclass 28 cls_cnt 0 2006.259.08:09:23.92#ibcon#cleared, iclass 28 cls_cnt 0 2006.259.08:09:23.92$4f8m12a/ifd4f 2006.259.08:09:23.92$ifd4f/lo= 2006.259.08:09:23.92$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.259.08:09:23.92$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.259.08:09:23.92$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.259.08:09:23.92$ifd4f/patch= 2006.259.08:09:23.92$ifd4f/patch=lo1,a1,a2,a3,a4 2006.259.08:09:23.92$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.259.08:09:23.92$ifd4f/patch=lo3,a5,a6,a7,a8 2006.259.08:09:23.92$4f8m12a/"form=m,16.000,1:2 2006.259.08:09:23.92$4f8m12a/"tpicd 2006.259.08:09:23.92$4f8m12a/echo=off 2006.259.08:09:23.92$4f8m12a/xlog=off 2006.259.08:09:23.92:!2006.259.08:10:00 2006.259.08:09:38.14#trakl#Source acquired 2006.259.08:09:40.14#flagr#flagr/antenna,acquired 2006.259.08:10:00.00:preob 2006.259.08:10:00.14/onsource/TRACKING 2006.259.08:10:00.14:!2006.259.08:10:10 2006.259.08:10:10.00:data_valid=on 2006.259.08:10:10.00:midob 2006.259.08:10:10.14/onsource/TRACKING 2006.259.08:10:10.14/wx/21.99,1013.0,87 2006.259.08:10:10.32/cable/+6.4606E-03 2006.259.08:10:11.41/va/01,08,usb,yes,34,36 2006.259.08:10:11.41/va/02,07,usb,yes,34,36 2006.259.08:10:11.41/va/03,08,usb,yes,26,26 2006.259.08:10:11.41/va/04,07,usb,yes,35,38 2006.259.08:10:11.41/va/05,07,usb,yes,39,42 2006.259.08:10:11.41/va/06,06,usb,yes,39,38 2006.259.08:10:11.41/va/07,06,usb,yes,39,39 2006.259.08:10:11.41/va/08,06,usb,yes,42,41 2006.259.08:10:11.64/valo/01,532.99,yes,locked 2006.259.08:10:11.64/valo/02,572.99,yes,locked 2006.259.08:10:11.64/valo/03,672.99,yes,locked 2006.259.08:10:11.64/valo/04,832.99,yes,locked 2006.259.08:10:11.64/valo/05,652.99,yes,locked 2006.259.08:10:11.64/valo/06,772.99,yes,locked 2006.259.08:10:11.64/valo/07,832.99,yes,locked 2006.259.08:10:11.64/valo/08,852.99,yes,locked 2006.259.08:10:12.73/vb/01,04,usb,yes,32,31 2006.259.08:10:12.73/vb/02,05,usb,yes,30,31 2006.259.08:10:12.73/vb/03,04,usb,yes,30,34 2006.259.08:10:12.73/vb/04,05,usb,yes,28,28 2006.259.08:10:12.73/vb/05,04,usb,yes,30,34 2006.259.08:10:12.73/vb/06,04,usb,yes,31,34 2006.259.08:10:12.73/vb/07,04,usb,yes,33,33 2006.259.08:10:12.73/vb/08,04,usb,yes,30,34 2006.259.08:10:12.96/vblo/01,632.99,yes,locked 2006.259.08:10:12.96/vblo/02,640.99,yes,locked 2006.259.08:10:12.96/vblo/03,656.99,yes,locked 2006.259.08:10:12.96/vblo/04,712.99,yes,locked 2006.259.08:10:12.96/vblo/05,744.99,yes,locked 2006.259.08:10:12.96/vblo/06,752.99,yes,locked 2006.259.08:10:12.96/vblo/07,734.99,yes,locked 2006.259.08:10:12.96/vblo/08,744.99,yes,locked 2006.259.08:10:13.11/vabw/8 2006.259.08:10:13.26/vbbw/8 2006.259.08:10:13.35/xfe/off,on,15.5 2006.259.08:10:13.72/ifatt/23,28,28,28 2006.259.08:10:14.07/fmout-gps/S +4.60E-07 2006.259.08:10:14.11:!2006.259.08:11:10 2006.259.08:11:10.00:data_valid=off 2006.259.08:11:10.00:postob 2006.259.08:11:10.08/cable/+6.4601E-03 2006.259.08:11:10.08/wx/21.98,1013.0,87 2006.259.08:11:11.08/fmout-gps/S +4.60E-07 2006.259.08:11:11.08:scan_name=259-0812,k06259,60 2006.259.08:11:11.09:source=1357+769,135755.37,764321.1,2000.0,ccw 2006.259.08:11:11.14#flagr#flagr/antenna,new-source 2006.259.08:11:12.14:checkk5 2006.259.08:11:12.53/chk_autoobs//k5ts1/ autoobs is running! 2006.259.08:11:12.93/chk_autoobs//k5ts2/ autoobs is running! 2006.259.08:11:13.33/chk_autoobs//k5ts3/ autoobs is running! 2006.259.08:11:13.73/chk_autoobs//k5ts4/ autoobs is running! 2006.259.08:11:14.12/chk_obsdata//k5ts1/T2590810??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.259.08:11:14.53/chk_obsdata//k5ts2/T2590810??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.259.08:11:14.93/chk_obsdata//k5ts3/T2590810??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.259.08:11:15.32/chk_obsdata//k5ts4/T2590810??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.259.08:11:16.31/k5log//k5ts1_log_newline 2006.259.08:11:17.04/k5log//k5ts2_log_newline 2006.259.08:11:17.80/k5log//k5ts3_log_newline 2006.259.08:11:18.54/k5log//k5ts4_log_newline 2006.259.08:11:18.56/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.259.08:11:18.56:4f8m12a=2 2006.259.08:11:18.56$4f8m12a/echo=on 2006.259.08:11:18.56$4f8m12a/pcalon 2006.259.08:11:18.56$pcalon/"no phase cal control is implemented here 2006.259.08:11:18.56$4f8m12a/"tpicd=stop 2006.259.08:11:18.56$4f8m12a/vc4f8 2006.259.08:11:18.56$vc4f8/valo=1,532.99 2006.259.08:11:18.57#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.259.08:11:18.57#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.259.08:11:18.57#ibcon#ireg 17 cls_cnt 0 2006.259.08:11:18.57#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.259.08:11:18.57#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.259.08:11:18.57#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.259.08:11:18.57#ibcon#enter wrdev, iclass 39, count 0 2006.259.08:11:18.57#ibcon#first serial, iclass 39, count 0 2006.259.08:11:18.57#ibcon#enter sib2, iclass 39, count 0 2006.259.08:11:18.57#ibcon#flushed, iclass 39, count 0 2006.259.08:11:18.57#ibcon#about to write, iclass 39, count 0 2006.259.08:11:18.57#ibcon#wrote, iclass 39, count 0 2006.259.08:11:18.57#ibcon#about to read 3, iclass 39, count 0 2006.259.08:11:18.61#ibcon#read 3, iclass 39, count 0 2006.259.08:11:18.61#ibcon#about to read 4, iclass 39, count 0 2006.259.08:11:18.61#ibcon#read 4, iclass 39, count 0 2006.259.08:11:18.61#ibcon#about to read 5, iclass 39, count 0 2006.259.08:11:18.61#ibcon#read 5, iclass 39, count 0 2006.259.08:11:18.61#ibcon#about to read 6, iclass 39, count 0 2006.259.08:11:18.61#ibcon#read 6, iclass 39, count 0 2006.259.08:11:18.61#ibcon#end of sib2, iclass 39, count 0 2006.259.08:11:18.61#ibcon#*mode == 0, iclass 39, count 0 2006.259.08:11:18.61#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.259.08:11:18.61#ibcon#[26=FRQ=01,532.99\r\n] 2006.259.08:11:18.61#ibcon#*before write, iclass 39, count 0 2006.259.08:11:18.61#ibcon#enter sib2, iclass 39, count 0 2006.259.08:11:18.61#ibcon#flushed, iclass 39, count 0 2006.259.08:11:18.61#ibcon#about to write, iclass 39, count 0 2006.259.08:11:18.61#ibcon#wrote, iclass 39, count 0 2006.259.08:11:18.61#ibcon#about to read 3, iclass 39, count 0 2006.259.08:11:18.66#ibcon#read 3, iclass 39, count 0 2006.259.08:11:18.66#ibcon#about to read 4, iclass 39, count 0 2006.259.08:11:18.66#ibcon#read 4, iclass 39, count 0 2006.259.08:11:18.66#ibcon#about to read 5, iclass 39, count 0 2006.259.08:11:18.66#ibcon#read 5, iclass 39, count 0 2006.259.08:11:18.66#ibcon#about to read 6, iclass 39, count 0 2006.259.08:11:18.66#ibcon#read 6, iclass 39, count 0 2006.259.08:11:18.66#ibcon#end of sib2, iclass 39, count 0 2006.259.08:11:18.66#ibcon#*after write, iclass 39, count 0 2006.259.08:11:18.66#ibcon#*before return 0, iclass 39, count 0 2006.259.08:11:18.66#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.259.08:11:18.66#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.259.08:11:18.66#ibcon#about to clear, iclass 39 cls_cnt 0 2006.259.08:11:18.66#ibcon#cleared, iclass 39 cls_cnt 0 2006.259.08:11:18.66$vc4f8/va=1,8 2006.259.08:11:18.66#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.259.08:11:18.66#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.259.08:11:18.66#ibcon#ireg 11 cls_cnt 2 2006.259.08:11:18.66#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.259.08:11:18.66#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.259.08:11:18.66#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.259.08:11:18.66#ibcon#enter wrdev, iclass 3, count 2 2006.259.08:11:18.66#ibcon#first serial, iclass 3, count 2 2006.259.08:11:18.66#ibcon#enter sib2, iclass 3, count 2 2006.259.08:11:18.66#ibcon#flushed, iclass 3, count 2 2006.259.08:11:18.66#ibcon#about to write, iclass 3, count 2 2006.259.08:11:18.66#ibcon#wrote, iclass 3, count 2 2006.259.08:11:18.66#ibcon#about to read 3, iclass 3, count 2 2006.259.08:11:18.68#ibcon#read 3, iclass 3, count 2 2006.259.08:11:18.68#ibcon#about to read 4, iclass 3, count 2 2006.259.08:11:18.68#ibcon#read 4, iclass 3, count 2 2006.259.08:11:18.68#ibcon#about to read 5, iclass 3, count 2 2006.259.08:11:18.68#ibcon#read 5, iclass 3, count 2 2006.259.08:11:18.68#ibcon#about to read 6, iclass 3, count 2 2006.259.08:11:18.68#ibcon#read 6, iclass 3, count 2 2006.259.08:11:18.68#ibcon#end of sib2, iclass 3, count 2 2006.259.08:11:18.68#ibcon#*mode == 0, iclass 3, count 2 2006.259.08:11:18.68#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.259.08:11:18.68#ibcon#[25=AT01-08\r\n] 2006.259.08:11:18.68#ibcon#*before write, iclass 3, count 2 2006.259.08:11:18.68#ibcon#enter sib2, iclass 3, count 2 2006.259.08:11:18.68#ibcon#flushed, iclass 3, count 2 2006.259.08:11:18.68#ibcon#about to write, iclass 3, count 2 2006.259.08:11:18.68#ibcon#wrote, iclass 3, count 2 2006.259.08:11:18.68#ibcon#about to read 3, iclass 3, count 2 2006.259.08:11:18.71#ibcon#read 3, iclass 3, count 2 2006.259.08:11:18.71#ibcon#about to read 4, iclass 3, count 2 2006.259.08:11:18.71#ibcon#read 4, iclass 3, count 2 2006.259.08:11:18.71#ibcon#about to read 5, iclass 3, count 2 2006.259.08:11:18.71#ibcon#read 5, iclass 3, count 2 2006.259.08:11:18.71#ibcon#about to read 6, iclass 3, count 2 2006.259.08:11:18.71#ibcon#read 6, iclass 3, count 2 2006.259.08:11:18.71#ibcon#end of sib2, iclass 3, count 2 2006.259.08:11:18.71#ibcon#*after write, iclass 3, count 2 2006.259.08:11:18.71#ibcon#*before return 0, iclass 3, count 2 2006.259.08:11:18.71#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.259.08:11:18.71#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.259.08:11:18.71#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.259.08:11:18.71#ibcon#ireg 7 cls_cnt 0 2006.259.08:11:18.71#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.259.08:11:18.83#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.259.08:11:18.83#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.259.08:11:18.83#ibcon#enter wrdev, iclass 3, count 0 2006.259.08:11:18.83#ibcon#first serial, iclass 3, count 0 2006.259.08:11:18.83#ibcon#enter sib2, iclass 3, count 0 2006.259.08:11:18.83#ibcon#flushed, iclass 3, count 0 2006.259.08:11:18.83#ibcon#about to write, iclass 3, count 0 2006.259.08:11:18.83#ibcon#wrote, iclass 3, count 0 2006.259.08:11:18.83#ibcon#about to read 3, iclass 3, count 0 2006.259.08:11:18.85#ibcon#read 3, iclass 3, count 0 2006.259.08:11:18.85#ibcon#about to read 4, iclass 3, count 0 2006.259.08:11:18.85#ibcon#read 4, iclass 3, count 0 2006.259.08:11:18.85#ibcon#about to read 5, iclass 3, count 0 2006.259.08:11:18.85#ibcon#read 5, iclass 3, count 0 2006.259.08:11:18.85#ibcon#about to read 6, iclass 3, count 0 2006.259.08:11:18.85#ibcon#read 6, iclass 3, count 0 2006.259.08:11:18.85#ibcon#end of sib2, iclass 3, count 0 2006.259.08:11:18.85#ibcon#*mode == 0, iclass 3, count 0 2006.259.08:11:18.85#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.259.08:11:18.85#ibcon#[25=USB\r\n] 2006.259.08:11:18.85#ibcon#*before write, iclass 3, count 0 2006.259.08:11:18.85#ibcon#enter sib2, iclass 3, count 0 2006.259.08:11:18.85#ibcon#flushed, iclass 3, count 0 2006.259.08:11:18.85#ibcon#about to write, iclass 3, count 0 2006.259.08:11:18.85#ibcon#wrote, iclass 3, count 0 2006.259.08:11:18.85#ibcon#about to read 3, iclass 3, count 0 2006.259.08:11:18.88#ibcon#read 3, iclass 3, count 0 2006.259.08:11:18.88#ibcon#about to read 4, iclass 3, count 0 2006.259.08:11:18.88#ibcon#read 4, iclass 3, count 0 2006.259.08:11:18.88#ibcon#about to read 5, iclass 3, count 0 2006.259.08:11:18.88#ibcon#read 5, iclass 3, count 0 2006.259.08:11:18.88#ibcon#about to read 6, iclass 3, count 0 2006.259.08:11:18.88#ibcon#read 6, iclass 3, count 0 2006.259.08:11:18.88#ibcon#end of sib2, iclass 3, count 0 2006.259.08:11:18.88#ibcon#*after write, iclass 3, count 0 2006.259.08:11:18.88#ibcon#*before return 0, iclass 3, count 0 2006.259.08:11:18.88#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.259.08:11:18.88#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.259.08:11:18.88#ibcon#about to clear, iclass 3 cls_cnt 0 2006.259.08:11:18.88#ibcon#cleared, iclass 3 cls_cnt 0 2006.259.08:11:18.88$vc4f8/valo=2,572.99 2006.259.08:11:18.88#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.259.08:11:18.88#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.259.08:11:18.88#ibcon#ireg 17 cls_cnt 0 2006.259.08:11:18.88#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.259.08:11:18.88#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.259.08:11:18.88#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.259.08:11:18.88#ibcon#enter wrdev, iclass 5, count 0 2006.259.08:11:18.88#ibcon#first serial, iclass 5, count 0 2006.259.08:11:18.88#ibcon#enter sib2, iclass 5, count 0 2006.259.08:11:18.88#ibcon#flushed, iclass 5, count 0 2006.259.08:11:18.88#ibcon#about to write, iclass 5, count 0 2006.259.08:11:18.88#ibcon#wrote, iclass 5, count 0 2006.259.08:11:18.88#ibcon#about to read 3, iclass 5, count 0 2006.259.08:11:18.90#ibcon#read 3, iclass 5, count 0 2006.259.08:11:18.90#ibcon#about to read 4, iclass 5, count 0 2006.259.08:11:18.90#ibcon#read 4, iclass 5, count 0 2006.259.08:11:18.90#ibcon#about to read 5, iclass 5, count 0 2006.259.08:11:18.90#ibcon#read 5, iclass 5, count 0 2006.259.08:11:18.90#ibcon#about to read 6, iclass 5, count 0 2006.259.08:11:18.90#ibcon#read 6, iclass 5, count 0 2006.259.08:11:18.90#ibcon#end of sib2, iclass 5, count 0 2006.259.08:11:18.90#ibcon#*mode == 0, iclass 5, count 0 2006.259.08:11:18.90#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.259.08:11:18.90#ibcon#[26=FRQ=02,572.99\r\n] 2006.259.08:11:18.90#ibcon#*before write, iclass 5, count 0 2006.259.08:11:18.90#ibcon#enter sib2, iclass 5, count 0 2006.259.08:11:18.90#ibcon#flushed, iclass 5, count 0 2006.259.08:11:18.90#ibcon#about to write, iclass 5, count 0 2006.259.08:11:18.90#ibcon#wrote, iclass 5, count 0 2006.259.08:11:18.90#ibcon#about to read 3, iclass 5, count 0 2006.259.08:11:18.94#ibcon#read 3, iclass 5, count 0 2006.259.08:11:18.94#ibcon#about to read 4, iclass 5, count 0 2006.259.08:11:18.94#ibcon#read 4, iclass 5, count 0 2006.259.08:11:18.94#ibcon#about to read 5, iclass 5, count 0 2006.259.08:11:18.94#ibcon#read 5, iclass 5, count 0 2006.259.08:11:18.94#ibcon#about to read 6, iclass 5, count 0 2006.259.08:11:18.94#ibcon#read 6, iclass 5, count 0 2006.259.08:11:18.94#ibcon#end of sib2, iclass 5, count 0 2006.259.08:11:18.94#ibcon#*after write, iclass 5, count 0 2006.259.08:11:18.94#ibcon#*before return 0, iclass 5, count 0 2006.259.08:11:18.94#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.259.08:11:18.94#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.259.08:11:18.94#ibcon#about to clear, iclass 5 cls_cnt 0 2006.259.08:11:18.94#ibcon#cleared, iclass 5 cls_cnt 0 2006.259.08:11:18.94$vc4f8/va=2,7 2006.259.08:11:18.94#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.259.08:11:18.94#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.259.08:11:18.94#ibcon#ireg 11 cls_cnt 2 2006.259.08:11:18.94#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.259.08:11:19.00#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.259.08:11:19.00#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.259.08:11:19.00#ibcon#enter wrdev, iclass 7, count 2 2006.259.08:11:19.00#ibcon#first serial, iclass 7, count 2 2006.259.08:11:19.00#ibcon#enter sib2, iclass 7, count 2 2006.259.08:11:19.00#ibcon#flushed, iclass 7, count 2 2006.259.08:11:19.00#ibcon#about to write, iclass 7, count 2 2006.259.08:11:19.00#ibcon#wrote, iclass 7, count 2 2006.259.08:11:19.00#ibcon#about to read 3, iclass 7, count 2 2006.259.08:11:19.02#ibcon#read 3, iclass 7, count 2 2006.259.08:11:19.02#ibcon#about to read 4, iclass 7, count 2 2006.259.08:11:19.02#ibcon#read 4, iclass 7, count 2 2006.259.08:11:19.02#ibcon#about to read 5, iclass 7, count 2 2006.259.08:11:19.02#ibcon#read 5, iclass 7, count 2 2006.259.08:11:19.02#ibcon#about to read 6, iclass 7, count 2 2006.259.08:11:19.02#ibcon#read 6, iclass 7, count 2 2006.259.08:11:19.02#ibcon#end of sib2, iclass 7, count 2 2006.259.08:11:19.02#ibcon#*mode == 0, iclass 7, count 2 2006.259.08:11:19.02#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.259.08:11:19.02#ibcon#[25=AT02-07\r\n] 2006.259.08:11:19.02#ibcon#*before write, iclass 7, count 2 2006.259.08:11:19.02#ibcon#enter sib2, iclass 7, count 2 2006.259.08:11:19.02#ibcon#flushed, iclass 7, count 2 2006.259.08:11:19.02#ibcon#about to write, iclass 7, count 2 2006.259.08:11:19.02#ibcon#wrote, iclass 7, count 2 2006.259.08:11:19.02#ibcon#about to read 3, iclass 7, count 2 2006.259.08:11:19.05#ibcon#read 3, iclass 7, count 2 2006.259.08:11:19.05#ibcon#about to read 4, iclass 7, count 2 2006.259.08:11:19.05#ibcon#read 4, iclass 7, count 2 2006.259.08:11:19.05#ibcon#about to read 5, iclass 7, count 2 2006.259.08:11:19.05#ibcon#read 5, iclass 7, count 2 2006.259.08:11:19.05#ibcon#about to read 6, iclass 7, count 2 2006.259.08:11:19.05#ibcon#read 6, iclass 7, count 2 2006.259.08:11:19.05#ibcon#end of sib2, iclass 7, count 2 2006.259.08:11:19.05#ibcon#*after write, iclass 7, count 2 2006.259.08:11:19.05#ibcon#*before return 0, iclass 7, count 2 2006.259.08:11:19.05#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.259.08:11:19.05#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.259.08:11:19.05#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.259.08:11:19.05#ibcon#ireg 7 cls_cnt 0 2006.259.08:11:19.05#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.259.08:11:19.17#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.259.08:11:19.17#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.259.08:11:19.17#ibcon#enter wrdev, iclass 7, count 0 2006.259.08:11:19.17#ibcon#first serial, iclass 7, count 0 2006.259.08:11:19.17#ibcon#enter sib2, iclass 7, count 0 2006.259.08:11:19.17#ibcon#flushed, iclass 7, count 0 2006.259.08:11:19.17#ibcon#about to write, iclass 7, count 0 2006.259.08:11:19.17#ibcon#wrote, iclass 7, count 0 2006.259.08:11:19.17#ibcon#about to read 3, iclass 7, count 0 2006.259.08:11:19.19#ibcon#read 3, iclass 7, count 0 2006.259.08:11:19.19#ibcon#about to read 4, iclass 7, count 0 2006.259.08:11:19.19#ibcon#read 4, iclass 7, count 0 2006.259.08:11:19.19#ibcon#about to read 5, iclass 7, count 0 2006.259.08:11:19.19#ibcon#read 5, iclass 7, count 0 2006.259.08:11:19.19#ibcon#about to read 6, iclass 7, count 0 2006.259.08:11:19.19#ibcon#read 6, iclass 7, count 0 2006.259.08:11:19.19#ibcon#end of sib2, iclass 7, count 0 2006.259.08:11:19.19#ibcon#*mode == 0, iclass 7, count 0 2006.259.08:11:19.19#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.259.08:11:19.19#ibcon#[25=USB\r\n] 2006.259.08:11:19.19#ibcon#*before write, iclass 7, count 0 2006.259.08:11:19.19#ibcon#enter sib2, iclass 7, count 0 2006.259.08:11:19.19#ibcon#flushed, iclass 7, count 0 2006.259.08:11:19.19#ibcon#about to write, iclass 7, count 0 2006.259.08:11:19.19#ibcon#wrote, iclass 7, count 0 2006.259.08:11:19.19#ibcon#about to read 3, iclass 7, count 0 2006.259.08:11:19.22#ibcon#read 3, iclass 7, count 0 2006.259.08:11:19.22#ibcon#about to read 4, iclass 7, count 0 2006.259.08:11:19.22#ibcon#read 4, iclass 7, count 0 2006.259.08:11:19.22#ibcon#about to read 5, iclass 7, count 0 2006.259.08:11:19.22#ibcon#read 5, iclass 7, count 0 2006.259.08:11:19.22#ibcon#about to read 6, iclass 7, count 0 2006.259.08:11:19.22#ibcon#read 6, iclass 7, count 0 2006.259.08:11:19.22#ibcon#end of sib2, iclass 7, count 0 2006.259.08:11:19.22#ibcon#*after write, iclass 7, count 0 2006.259.08:11:19.22#ibcon#*before return 0, iclass 7, count 0 2006.259.08:11:19.22#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.259.08:11:19.22#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.259.08:11:19.22#ibcon#about to clear, iclass 7 cls_cnt 0 2006.259.08:11:19.22#ibcon#cleared, iclass 7 cls_cnt 0 2006.259.08:11:19.22$vc4f8/valo=3,672.99 2006.259.08:11:19.22#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.259.08:11:19.22#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.259.08:11:19.22#ibcon#ireg 17 cls_cnt 0 2006.259.08:11:19.22#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.259.08:11:19.22#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.259.08:11:19.22#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.259.08:11:19.22#ibcon#enter wrdev, iclass 11, count 0 2006.259.08:11:19.22#ibcon#first serial, iclass 11, count 0 2006.259.08:11:19.22#ibcon#enter sib2, iclass 11, count 0 2006.259.08:11:19.22#ibcon#flushed, iclass 11, count 0 2006.259.08:11:19.22#ibcon#about to write, iclass 11, count 0 2006.259.08:11:19.22#ibcon#wrote, iclass 11, count 0 2006.259.08:11:19.22#ibcon#about to read 3, iclass 11, count 0 2006.259.08:11:19.24#ibcon#read 3, iclass 11, count 0 2006.259.08:11:19.24#ibcon#about to read 4, iclass 11, count 0 2006.259.08:11:19.24#ibcon#read 4, iclass 11, count 0 2006.259.08:11:19.24#ibcon#about to read 5, iclass 11, count 0 2006.259.08:11:19.24#ibcon#read 5, iclass 11, count 0 2006.259.08:11:19.24#ibcon#about to read 6, iclass 11, count 0 2006.259.08:11:19.24#ibcon#read 6, iclass 11, count 0 2006.259.08:11:19.24#ibcon#end of sib2, iclass 11, count 0 2006.259.08:11:19.24#ibcon#*mode == 0, iclass 11, count 0 2006.259.08:11:19.24#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.259.08:11:19.24#ibcon#[26=FRQ=03,672.99\r\n] 2006.259.08:11:19.24#ibcon#*before write, iclass 11, count 0 2006.259.08:11:19.24#ibcon#enter sib2, iclass 11, count 0 2006.259.08:11:19.24#ibcon#flushed, iclass 11, count 0 2006.259.08:11:19.24#ibcon#about to write, iclass 11, count 0 2006.259.08:11:19.24#ibcon#wrote, iclass 11, count 0 2006.259.08:11:19.24#ibcon#about to read 3, iclass 11, count 0 2006.259.08:11:19.28#ibcon#read 3, iclass 11, count 0 2006.259.08:11:19.28#ibcon#about to read 4, iclass 11, count 0 2006.259.08:11:19.28#ibcon#read 4, iclass 11, count 0 2006.259.08:11:19.28#ibcon#about to read 5, iclass 11, count 0 2006.259.08:11:19.28#ibcon#read 5, iclass 11, count 0 2006.259.08:11:19.28#ibcon#about to read 6, iclass 11, count 0 2006.259.08:11:19.28#ibcon#read 6, iclass 11, count 0 2006.259.08:11:19.28#ibcon#end of sib2, iclass 11, count 0 2006.259.08:11:19.28#ibcon#*after write, iclass 11, count 0 2006.259.08:11:19.28#ibcon#*before return 0, iclass 11, count 0 2006.259.08:11:19.28#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.259.08:11:19.28#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.259.08:11:19.28#ibcon#about to clear, iclass 11 cls_cnt 0 2006.259.08:11:19.28#ibcon#cleared, iclass 11 cls_cnt 0 2006.259.08:11:19.28$vc4f8/va=3,8 2006.259.08:11:19.28#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.259.08:11:19.28#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.259.08:11:19.28#ibcon#ireg 11 cls_cnt 2 2006.259.08:11:19.28#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.259.08:11:19.34#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.259.08:11:19.34#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.259.08:11:19.34#ibcon#enter wrdev, iclass 13, count 2 2006.259.08:11:19.34#ibcon#first serial, iclass 13, count 2 2006.259.08:11:19.34#ibcon#enter sib2, iclass 13, count 2 2006.259.08:11:19.34#ibcon#flushed, iclass 13, count 2 2006.259.08:11:19.34#ibcon#about to write, iclass 13, count 2 2006.259.08:11:19.34#ibcon#wrote, iclass 13, count 2 2006.259.08:11:19.34#ibcon#about to read 3, iclass 13, count 2 2006.259.08:11:19.36#ibcon#read 3, iclass 13, count 2 2006.259.08:11:19.36#ibcon#about to read 4, iclass 13, count 2 2006.259.08:11:19.36#ibcon#read 4, iclass 13, count 2 2006.259.08:11:19.36#ibcon#about to read 5, iclass 13, count 2 2006.259.08:11:19.36#ibcon#read 5, iclass 13, count 2 2006.259.08:11:19.36#ibcon#about to read 6, iclass 13, count 2 2006.259.08:11:19.36#ibcon#read 6, iclass 13, count 2 2006.259.08:11:19.36#ibcon#end of sib2, iclass 13, count 2 2006.259.08:11:19.36#ibcon#*mode == 0, iclass 13, count 2 2006.259.08:11:19.36#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.259.08:11:19.36#ibcon#[25=AT03-08\r\n] 2006.259.08:11:19.36#ibcon#*before write, iclass 13, count 2 2006.259.08:11:19.36#ibcon#enter sib2, iclass 13, count 2 2006.259.08:11:19.36#ibcon#flushed, iclass 13, count 2 2006.259.08:11:19.36#ibcon#about to write, iclass 13, count 2 2006.259.08:11:19.36#ibcon#wrote, iclass 13, count 2 2006.259.08:11:19.36#ibcon#about to read 3, iclass 13, count 2 2006.259.08:11:19.39#ibcon#read 3, iclass 13, count 2 2006.259.08:11:19.39#ibcon#about to read 4, iclass 13, count 2 2006.259.08:11:19.39#ibcon#read 4, iclass 13, count 2 2006.259.08:11:19.39#ibcon#about to read 5, iclass 13, count 2 2006.259.08:11:19.39#ibcon#read 5, iclass 13, count 2 2006.259.08:11:19.39#ibcon#about to read 6, iclass 13, count 2 2006.259.08:11:19.39#ibcon#read 6, iclass 13, count 2 2006.259.08:11:19.39#ibcon#end of sib2, iclass 13, count 2 2006.259.08:11:19.39#ibcon#*after write, iclass 13, count 2 2006.259.08:11:19.39#ibcon#*before return 0, iclass 13, count 2 2006.259.08:11:19.39#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.259.08:11:19.39#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.259.08:11:19.39#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.259.08:11:19.39#ibcon#ireg 7 cls_cnt 0 2006.259.08:11:19.39#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.259.08:11:19.51#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.259.08:11:19.51#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.259.08:11:19.51#ibcon#enter wrdev, iclass 13, count 0 2006.259.08:11:19.51#ibcon#first serial, iclass 13, count 0 2006.259.08:11:19.51#ibcon#enter sib2, iclass 13, count 0 2006.259.08:11:19.51#ibcon#flushed, iclass 13, count 0 2006.259.08:11:19.51#ibcon#about to write, iclass 13, count 0 2006.259.08:11:19.51#ibcon#wrote, iclass 13, count 0 2006.259.08:11:19.51#ibcon#about to read 3, iclass 13, count 0 2006.259.08:11:19.53#ibcon#read 3, iclass 13, count 0 2006.259.08:11:19.53#ibcon#about to read 4, iclass 13, count 0 2006.259.08:11:19.53#ibcon#read 4, iclass 13, count 0 2006.259.08:11:19.53#ibcon#about to read 5, iclass 13, count 0 2006.259.08:11:19.53#ibcon#read 5, iclass 13, count 0 2006.259.08:11:19.53#ibcon#about to read 6, iclass 13, count 0 2006.259.08:11:19.53#ibcon#read 6, iclass 13, count 0 2006.259.08:11:19.53#ibcon#end of sib2, iclass 13, count 0 2006.259.08:11:19.53#ibcon#*mode == 0, iclass 13, count 0 2006.259.08:11:19.53#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.259.08:11:19.53#ibcon#[25=USB\r\n] 2006.259.08:11:19.53#ibcon#*before write, iclass 13, count 0 2006.259.08:11:19.53#ibcon#enter sib2, iclass 13, count 0 2006.259.08:11:19.53#ibcon#flushed, iclass 13, count 0 2006.259.08:11:19.53#ibcon#about to write, iclass 13, count 0 2006.259.08:11:19.53#ibcon#wrote, iclass 13, count 0 2006.259.08:11:19.53#ibcon#about to read 3, iclass 13, count 0 2006.259.08:11:19.56#ibcon#read 3, iclass 13, count 0 2006.259.08:11:19.56#ibcon#about to read 4, iclass 13, count 0 2006.259.08:11:19.56#ibcon#read 4, iclass 13, count 0 2006.259.08:11:19.56#ibcon#about to read 5, iclass 13, count 0 2006.259.08:11:19.56#ibcon#read 5, iclass 13, count 0 2006.259.08:11:19.56#ibcon#about to read 6, iclass 13, count 0 2006.259.08:11:19.56#ibcon#read 6, iclass 13, count 0 2006.259.08:11:19.56#ibcon#end of sib2, iclass 13, count 0 2006.259.08:11:19.56#ibcon#*after write, iclass 13, count 0 2006.259.08:11:19.56#ibcon#*before return 0, iclass 13, count 0 2006.259.08:11:19.56#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.259.08:11:19.56#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.259.08:11:19.56#ibcon#about to clear, iclass 13 cls_cnt 0 2006.259.08:11:19.56#ibcon#cleared, iclass 13 cls_cnt 0 2006.259.08:11:19.56$vc4f8/valo=4,832.99 2006.259.08:11:19.56#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.259.08:11:19.56#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.259.08:11:19.56#ibcon#ireg 17 cls_cnt 0 2006.259.08:11:19.56#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.259.08:11:19.56#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.259.08:11:19.56#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.259.08:11:19.56#ibcon#enter wrdev, iclass 15, count 0 2006.259.08:11:19.56#ibcon#first serial, iclass 15, count 0 2006.259.08:11:19.56#ibcon#enter sib2, iclass 15, count 0 2006.259.08:11:19.56#ibcon#flushed, iclass 15, count 0 2006.259.08:11:19.56#ibcon#about to write, iclass 15, count 0 2006.259.08:11:19.56#ibcon#wrote, iclass 15, count 0 2006.259.08:11:19.56#ibcon#about to read 3, iclass 15, count 0 2006.259.08:11:19.58#ibcon#read 3, iclass 15, count 0 2006.259.08:11:19.58#ibcon#about to read 4, iclass 15, count 0 2006.259.08:11:19.58#ibcon#read 4, iclass 15, count 0 2006.259.08:11:19.58#ibcon#about to read 5, iclass 15, count 0 2006.259.08:11:19.58#ibcon#read 5, iclass 15, count 0 2006.259.08:11:19.58#ibcon#about to read 6, iclass 15, count 0 2006.259.08:11:19.58#ibcon#read 6, iclass 15, count 0 2006.259.08:11:19.58#ibcon#end of sib2, iclass 15, count 0 2006.259.08:11:19.58#ibcon#*mode == 0, iclass 15, count 0 2006.259.08:11:19.58#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.259.08:11:19.58#ibcon#[26=FRQ=04,832.99\r\n] 2006.259.08:11:19.58#ibcon#*before write, iclass 15, count 0 2006.259.08:11:19.58#ibcon#enter sib2, iclass 15, count 0 2006.259.08:11:19.58#ibcon#flushed, iclass 15, count 0 2006.259.08:11:19.58#ibcon#about to write, iclass 15, count 0 2006.259.08:11:19.58#ibcon#wrote, iclass 15, count 0 2006.259.08:11:19.58#ibcon#about to read 3, iclass 15, count 0 2006.259.08:11:19.62#ibcon#read 3, iclass 15, count 0 2006.259.08:11:19.62#ibcon#about to read 4, iclass 15, count 0 2006.259.08:11:19.62#ibcon#read 4, iclass 15, count 0 2006.259.08:11:19.62#ibcon#about to read 5, iclass 15, count 0 2006.259.08:11:19.62#ibcon#read 5, iclass 15, count 0 2006.259.08:11:19.62#ibcon#about to read 6, iclass 15, count 0 2006.259.08:11:19.62#ibcon#read 6, iclass 15, count 0 2006.259.08:11:19.62#ibcon#end of sib2, iclass 15, count 0 2006.259.08:11:19.62#ibcon#*after write, iclass 15, count 0 2006.259.08:11:19.62#ibcon#*before return 0, iclass 15, count 0 2006.259.08:11:19.62#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.259.08:11:19.62#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.259.08:11:19.62#ibcon#about to clear, iclass 15 cls_cnt 0 2006.259.08:11:19.62#ibcon#cleared, iclass 15 cls_cnt 0 2006.259.08:11:19.62$vc4f8/va=4,7 2006.259.08:11:19.62#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.259.08:11:19.62#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.259.08:11:19.62#ibcon#ireg 11 cls_cnt 2 2006.259.08:11:19.62#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.259.08:11:19.68#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.259.08:11:19.68#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.259.08:11:19.68#ibcon#enter wrdev, iclass 17, count 2 2006.259.08:11:19.68#ibcon#first serial, iclass 17, count 2 2006.259.08:11:19.68#ibcon#enter sib2, iclass 17, count 2 2006.259.08:11:19.68#ibcon#flushed, iclass 17, count 2 2006.259.08:11:19.68#ibcon#about to write, iclass 17, count 2 2006.259.08:11:19.68#ibcon#wrote, iclass 17, count 2 2006.259.08:11:19.68#ibcon#about to read 3, iclass 17, count 2 2006.259.08:11:19.70#ibcon#read 3, iclass 17, count 2 2006.259.08:11:19.70#ibcon#about to read 4, iclass 17, count 2 2006.259.08:11:19.70#ibcon#read 4, iclass 17, count 2 2006.259.08:11:19.70#ibcon#about to read 5, iclass 17, count 2 2006.259.08:11:19.70#ibcon#read 5, iclass 17, count 2 2006.259.08:11:19.70#ibcon#about to read 6, iclass 17, count 2 2006.259.08:11:19.70#ibcon#read 6, iclass 17, count 2 2006.259.08:11:19.70#ibcon#end of sib2, iclass 17, count 2 2006.259.08:11:19.70#ibcon#*mode == 0, iclass 17, count 2 2006.259.08:11:19.70#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.259.08:11:19.70#ibcon#[25=AT04-07\r\n] 2006.259.08:11:19.70#ibcon#*before write, iclass 17, count 2 2006.259.08:11:19.70#ibcon#enter sib2, iclass 17, count 2 2006.259.08:11:19.70#ibcon#flushed, iclass 17, count 2 2006.259.08:11:19.70#ibcon#about to write, iclass 17, count 2 2006.259.08:11:19.70#ibcon#wrote, iclass 17, count 2 2006.259.08:11:19.70#ibcon#about to read 3, iclass 17, count 2 2006.259.08:11:19.73#ibcon#read 3, iclass 17, count 2 2006.259.08:11:19.73#ibcon#about to read 4, iclass 17, count 2 2006.259.08:11:19.73#ibcon#read 4, iclass 17, count 2 2006.259.08:11:19.73#ibcon#about to read 5, iclass 17, count 2 2006.259.08:11:19.73#ibcon#read 5, iclass 17, count 2 2006.259.08:11:19.73#ibcon#about to read 6, iclass 17, count 2 2006.259.08:11:19.73#ibcon#read 6, iclass 17, count 2 2006.259.08:11:19.73#ibcon#end of sib2, iclass 17, count 2 2006.259.08:11:19.73#ibcon#*after write, iclass 17, count 2 2006.259.08:11:19.73#ibcon#*before return 0, iclass 17, count 2 2006.259.08:11:19.73#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.259.08:11:19.73#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.259.08:11:19.73#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.259.08:11:19.73#ibcon#ireg 7 cls_cnt 0 2006.259.08:11:19.73#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.259.08:11:19.82#abcon#<5=/04 2.6 5.8 21.98 871013.0\r\n> 2006.259.08:11:19.84#abcon#{5=INTERFACE CLEAR} 2006.259.08:11:19.85#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.259.08:11:19.85#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.259.08:11:19.85#ibcon#enter wrdev, iclass 17, count 0 2006.259.08:11:19.85#ibcon#first serial, iclass 17, count 0 2006.259.08:11:19.85#ibcon#enter sib2, iclass 17, count 0 2006.259.08:11:19.85#ibcon#flushed, iclass 17, count 0 2006.259.08:11:19.85#ibcon#about to write, iclass 17, count 0 2006.259.08:11:19.85#ibcon#wrote, iclass 17, count 0 2006.259.08:11:19.85#ibcon#about to read 3, iclass 17, count 0 2006.259.08:11:19.87#ibcon#read 3, iclass 17, count 0 2006.259.08:11:19.87#ibcon#about to read 4, iclass 17, count 0 2006.259.08:11:19.87#ibcon#read 4, iclass 17, count 0 2006.259.08:11:19.87#ibcon#about to read 5, iclass 17, count 0 2006.259.08:11:19.87#ibcon#read 5, iclass 17, count 0 2006.259.08:11:19.87#ibcon#about to read 6, iclass 17, count 0 2006.259.08:11:19.87#ibcon#read 6, iclass 17, count 0 2006.259.08:11:19.87#ibcon#end of sib2, iclass 17, count 0 2006.259.08:11:19.87#ibcon#*mode == 0, iclass 17, count 0 2006.259.08:11:19.87#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.259.08:11:19.87#ibcon#[25=USB\r\n] 2006.259.08:11:19.87#ibcon#*before write, iclass 17, count 0 2006.259.08:11:19.87#ibcon#enter sib2, iclass 17, count 0 2006.259.08:11:19.87#ibcon#flushed, iclass 17, count 0 2006.259.08:11:19.87#ibcon#about to write, iclass 17, count 0 2006.259.08:11:19.87#ibcon#wrote, iclass 17, count 0 2006.259.08:11:19.87#ibcon#about to read 3, iclass 17, count 0 2006.259.08:11:19.90#abcon#[5=S1D000X0/0*\r\n] 2006.259.08:11:19.90#ibcon#read 3, iclass 17, count 0 2006.259.08:11:19.90#ibcon#about to read 4, iclass 17, count 0 2006.259.08:11:19.90#ibcon#read 4, iclass 17, count 0 2006.259.08:11:19.90#ibcon#about to read 5, iclass 17, count 0 2006.259.08:11:19.90#ibcon#read 5, iclass 17, count 0 2006.259.08:11:19.90#ibcon#about to read 6, iclass 17, count 0 2006.259.08:11:19.90#ibcon#read 6, iclass 17, count 0 2006.259.08:11:19.90#ibcon#end of sib2, iclass 17, count 0 2006.259.08:11:19.90#ibcon#*after write, iclass 17, count 0 2006.259.08:11:19.90#ibcon#*before return 0, iclass 17, count 0 2006.259.08:11:19.90#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.259.08:11:19.90#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.259.08:11:19.90#ibcon#about to clear, iclass 17 cls_cnt 0 2006.259.08:11:19.90#ibcon#cleared, iclass 17 cls_cnt 0 2006.259.08:11:19.90$vc4f8/valo=5,652.99 2006.259.08:11:19.90#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.259.08:11:19.90#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.259.08:11:19.90#ibcon#ireg 17 cls_cnt 0 2006.259.08:11:19.90#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.259.08:11:19.90#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.259.08:11:19.90#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.259.08:11:19.90#ibcon#enter wrdev, iclass 23, count 0 2006.259.08:11:19.90#ibcon#first serial, iclass 23, count 0 2006.259.08:11:19.90#ibcon#enter sib2, iclass 23, count 0 2006.259.08:11:19.90#ibcon#flushed, iclass 23, count 0 2006.259.08:11:19.90#ibcon#about to write, iclass 23, count 0 2006.259.08:11:19.90#ibcon#wrote, iclass 23, count 0 2006.259.08:11:19.90#ibcon#about to read 3, iclass 23, count 0 2006.259.08:11:19.92#ibcon#read 3, iclass 23, count 0 2006.259.08:11:19.92#ibcon#about to read 4, iclass 23, count 0 2006.259.08:11:19.92#ibcon#read 4, iclass 23, count 0 2006.259.08:11:19.92#ibcon#about to read 5, iclass 23, count 0 2006.259.08:11:19.92#ibcon#read 5, iclass 23, count 0 2006.259.08:11:19.92#ibcon#about to read 6, iclass 23, count 0 2006.259.08:11:19.92#ibcon#read 6, iclass 23, count 0 2006.259.08:11:19.92#ibcon#end of sib2, iclass 23, count 0 2006.259.08:11:19.92#ibcon#*mode == 0, iclass 23, count 0 2006.259.08:11:19.92#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.259.08:11:19.92#ibcon#[26=FRQ=05,652.99\r\n] 2006.259.08:11:19.92#ibcon#*before write, iclass 23, count 0 2006.259.08:11:19.92#ibcon#enter sib2, iclass 23, count 0 2006.259.08:11:19.92#ibcon#flushed, iclass 23, count 0 2006.259.08:11:19.92#ibcon#about to write, iclass 23, count 0 2006.259.08:11:19.92#ibcon#wrote, iclass 23, count 0 2006.259.08:11:19.92#ibcon#about to read 3, iclass 23, count 0 2006.259.08:11:19.96#ibcon#read 3, iclass 23, count 0 2006.259.08:11:19.96#ibcon#about to read 4, iclass 23, count 0 2006.259.08:11:19.96#ibcon#read 4, iclass 23, count 0 2006.259.08:11:19.96#ibcon#about to read 5, iclass 23, count 0 2006.259.08:11:19.96#ibcon#read 5, iclass 23, count 0 2006.259.08:11:19.96#ibcon#about to read 6, iclass 23, count 0 2006.259.08:11:19.96#ibcon#read 6, iclass 23, count 0 2006.259.08:11:19.96#ibcon#end of sib2, iclass 23, count 0 2006.259.08:11:19.96#ibcon#*after write, iclass 23, count 0 2006.259.08:11:19.96#ibcon#*before return 0, iclass 23, count 0 2006.259.08:11:19.96#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.259.08:11:19.96#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.259.08:11:19.96#ibcon#about to clear, iclass 23 cls_cnt 0 2006.259.08:11:19.96#ibcon#cleared, iclass 23 cls_cnt 0 2006.259.08:11:19.96$vc4f8/va=5,7 2006.259.08:11:19.96#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.259.08:11:19.96#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.259.08:11:19.96#ibcon#ireg 11 cls_cnt 2 2006.259.08:11:19.96#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.259.08:11:20.02#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.259.08:11:20.02#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.259.08:11:20.02#ibcon#enter wrdev, iclass 25, count 2 2006.259.08:11:20.02#ibcon#first serial, iclass 25, count 2 2006.259.08:11:20.02#ibcon#enter sib2, iclass 25, count 2 2006.259.08:11:20.02#ibcon#flushed, iclass 25, count 2 2006.259.08:11:20.02#ibcon#about to write, iclass 25, count 2 2006.259.08:11:20.02#ibcon#wrote, iclass 25, count 2 2006.259.08:11:20.02#ibcon#about to read 3, iclass 25, count 2 2006.259.08:11:20.04#ibcon#read 3, iclass 25, count 2 2006.259.08:11:20.04#ibcon#about to read 4, iclass 25, count 2 2006.259.08:11:20.04#ibcon#read 4, iclass 25, count 2 2006.259.08:11:20.04#ibcon#about to read 5, iclass 25, count 2 2006.259.08:11:20.04#ibcon#read 5, iclass 25, count 2 2006.259.08:11:20.04#ibcon#about to read 6, iclass 25, count 2 2006.259.08:11:20.04#ibcon#read 6, iclass 25, count 2 2006.259.08:11:20.04#ibcon#end of sib2, iclass 25, count 2 2006.259.08:11:20.04#ibcon#*mode == 0, iclass 25, count 2 2006.259.08:11:20.04#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.259.08:11:20.04#ibcon#[25=AT05-07\r\n] 2006.259.08:11:20.04#ibcon#*before write, iclass 25, count 2 2006.259.08:11:20.04#ibcon#enter sib2, iclass 25, count 2 2006.259.08:11:20.04#ibcon#flushed, iclass 25, count 2 2006.259.08:11:20.04#ibcon#about to write, iclass 25, count 2 2006.259.08:11:20.04#ibcon#wrote, iclass 25, count 2 2006.259.08:11:20.04#ibcon#about to read 3, iclass 25, count 2 2006.259.08:11:20.07#ibcon#read 3, iclass 25, count 2 2006.259.08:11:20.07#ibcon#about to read 4, iclass 25, count 2 2006.259.08:11:20.07#ibcon#read 4, iclass 25, count 2 2006.259.08:11:20.07#ibcon#about to read 5, iclass 25, count 2 2006.259.08:11:20.07#ibcon#read 5, iclass 25, count 2 2006.259.08:11:20.07#ibcon#about to read 6, iclass 25, count 2 2006.259.08:11:20.07#ibcon#read 6, iclass 25, count 2 2006.259.08:11:20.07#ibcon#end of sib2, iclass 25, count 2 2006.259.08:11:20.07#ibcon#*after write, iclass 25, count 2 2006.259.08:11:20.07#ibcon#*before return 0, iclass 25, count 2 2006.259.08:11:20.07#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.259.08:11:20.07#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.259.08:11:20.07#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.259.08:11:20.07#ibcon#ireg 7 cls_cnt 0 2006.259.08:11:20.07#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.259.08:11:20.19#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.259.08:11:20.19#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.259.08:11:20.19#ibcon#enter wrdev, iclass 25, count 0 2006.259.08:11:20.19#ibcon#first serial, iclass 25, count 0 2006.259.08:11:20.19#ibcon#enter sib2, iclass 25, count 0 2006.259.08:11:20.19#ibcon#flushed, iclass 25, count 0 2006.259.08:11:20.19#ibcon#about to write, iclass 25, count 0 2006.259.08:11:20.19#ibcon#wrote, iclass 25, count 0 2006.259.08:11:20.19#ibcon#about to read 3, iclass 25, count 0 2006.259.08:11:20.21#ibcon#read 3, iclass 25, count 0 2006.259.08:11:20.21#ibcon#about to read 4, iclass 25, count 0 2006.259.08:11:20.21#ibcon#read 4, iclass 25, count 0 2006.259.08:11:20.21#ibcon#about to read 5, iclass 25, count 0 2006.259.08:11:20.21#ibcon#read 5, iclass 25, count 0 2006.259.08:11:20.21#ibcon#about to read 6, iclass 25, count 0 2006.259.08:11:20.21#ibcon#read 6, iclass 25, count 0 2006.259.08:11:20.21#ibcon#end of sib2, iclass 25, count 0 2006.259.08:11:20.21#ibcon#*mode == 0, iclass 25, count 0 2006.259.08:11:20.21#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.259.08:11:20.21#ibcon#[25=USB\r\n] 2006.259.08:11:20.21#ibcon#*before write, iclass 25, count 0 2006.259.08:11:20.21#ibcon#enter sib2, iclass 25, count 0 2006.259.08:11:20.21#ibcon#flushed, iclass 25, count 0 2006.259.08:11:20.21#ibcon#about to write, iclass 25, count 0 2006.259.08:11:20.21#ibcon#wrote, iclass 25, count 0 2006.259.08:11:20.21#ibcon#about to read 3, iclass 25, count 0 2006.259.08:11:20.24#ibcon#read 3, iclass 25, count 0 2006.259.08:11:20.24#ibcon#about to read 4, iclass 25, count 0 2006.259.08:11:20.24#ibcon#read 4, iclass 25, count 0 2006.259.08:11:20.24#ibcon#about to read 5, iclass 25, count 0 2006.259.08:11:20.24#ibcon#read 5, iclass 25, count 0 2006.259.08:11:20.24#ibcon#about to read 6, iclass 25, count 0 2006.259.08:11:20.24#ibcon#read 6, iclass 25, count 0 2006.259.08:11:20.24#ibcon#end of sib2, iclass 25, count 0 2006.259.08:11:20.24#ibcon#*after write, iclass 25, count 0 2006.259.08:11:20.24#ibcon#*before return 0, iclass 25, count 0 2006.259.08:11:20.24#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.259.08:11:20.24#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.259.08:11:20.24#ibcon#about to clear, iclass 25 cls_cnt 0 2006.259.08:11:20.24#ibcon#cleared, iclass 25 cls_cnt 0 2006.259.08:11:20.24$vc4f8/valo=6,772.99 2006.259.08:11:20.24#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.259.08:11:20.24#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.259.08:11:20.24#ibcon#ireg 17 cls_cnt 0 2006.259.08:11:20.24#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.259.08:11:20.24#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.259.08:11:20.24#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.259.08:11:20.24#ibcon#enter wrdev, iclass 27, count 0 2006.259.08:11:20.24#ibcon#first serial, iclass 27, count 0 2006.259.08:11:20.24#ibcon#enter sib2, iclass 27, count 0 2006.259.08:11:20.24#ibcon#flushed, iclass 27, count 0 2006.259.08:11:20.24#ibcon#about to write, iclass 27, count 0 2006.259.08:11:20.24#ibcon#wrote, iclass 27, count 0 2006.259.08:11:20.24#ibcon#about to read 3, iclass 27, count 0 2006.259.08:11:20.26#ibcon#read 3, iclass 27, count 0 2006.259.08:11:20.26#ibcon#about to read 4, iclass 27, count 0 2006.259.08:11:20.26#ibcon#read 4, iclass 27, count 0 2006.259.08:11:20.26#ibcon#about to read 5, iclass 27, count 0 2006.259.08:11:20.26#ibcon#read 5, iclass 27, count 0 2006.259.08:11:20.26#ibcon#about to read 6, iclass 27, count 0 2006.259.08:11:20.26#ibcon#read 6, iclass 27, count 0 2006.259.08:11:20.26#ibcon#end of sib2, iclass 27, count 0 2006.259.08:11:20.26#ibcon#*mode == 0, iclass 27, count 0 2006.259.08:11:20.26#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.259.08:11:20.26#ibcon#[26=FRQ=06,772.99\r\n] 2006.259.08:11:20.26#ibcon#*before write, iclass 27, count 0 2006.259.08:11:20.26#ibcon#enter sib2, iclass 27, count 0 2006.259.08:11:20.26#ibcon#flushed, iclass 27, count 0 2006.259.08:11:20.26#ibcon#about to write, iclass 27, count 0 2006.259.08:11:20.26#ibcon#wrote, iclass 27, count 0 2006.259.08:11:20.26#ibcon#about to read 3, iclass 27, count 0 2006.259.08:11:20.30#ibcon#read 3, iclass 27, count 0 2006.259.08:11:20.30#ibcon#about to read 4, iclass 27, count 0 2006.259.08:11:20.30#ibcon#read 4, iclass 27, count 0 2006.259.08:11:20.30#ibcon#about to read 5, iclass 27, count 0 2006.259.08:11:20.30#ibcon#read 5, iclass 27, count 0 2006.259.08:11:20.30#ibcon#about to read 6, iclass 27, count 0 2006.259.08:11:20.30#ibcon#read 6, iclass 27, count 0 2006.259.08:11:20.30#ibcon#end of sib2, iclass 27, count 0 2006.259.08:11:20.30#ibcon#*after write, iclass 27, count 0 2006.259.08:11:20.30#ibcon#*before return 0, iclass 27, count 0 2006.259.08:11:20.30#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.259.08:11:20.30#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.259.08:11:20.30#ibcon#about to clear, iclass 27 cls_cnt 0 2006.259.08:11:20.30#ibcon#cleared, iclass 27 cls_cnt 0 2006.259.08:11:20.30$vc4f8/va=6,6 2006.259.08:11:20.30#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.259.08:11:20.30#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.259.08:11:20.30#ibcon#ireg 11 cls_cnt 2 2006.259.08:11:20.30#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.259.08:11:20.36#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.259.08:11:20.36#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.259.08:11:20.36#ibcon#enter wrdev, iclass 29, count 2 2006.259.08:11:20.36#ibcon#first serial, iclass 29, count 2 2006.259.08:11:20.36#ibcon#enter sib2, iclass 29, count 2 2006.259.08:11:20.36#ibcon#flushed, iclass 29, count 2 2006.259.08:11:20.36#ibcon#about to write, iclass 29, count 2 2006.259.08:11:20.36#ibcon#wrote, iclass 29, count 2 2006.259.08:11:20.36#ibcon#about to read 3, iclass 29, count 2 2006.259.08:11:20.38#ibcon#read 3, iclass 29, count 2 2006.259.08:11:20.38#ibcon#about to read 4, iclass 29, count 2 2006.259.08:11:20.38#ibcon#read 4, iclass 29, count 2 2006.259.08:11:20.38#ibcon#about to read 5, iclass 29, count 2 2006.259.08:11:20.38#ibcon#read 5, iclass 29, count 2 2006.259.08:11:20.38#ibcon#about to read 6, iclass 29, count 2 2006.259.08:11:20.38#ibcon#read 6, iclass 29, count 2 2006.259.08:11:20.38#ibcon#end of sib2, iclass 29, count 2 2006.259.08:11:20.38#ibcon#*mode == 0, iclass 29, count 2 2006.259.08:11:20.38#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.259.08:11:20.38#ibcon#[25=AT06-06\r\n] 2006.259.08:11:20.38#ibcon#*before write, iclass 29, count 2 2006.259.08:11:20.38#ibcon#enter sib2, iclass 29, count 2 2006.259.08:11:20.38#ibcon#flushed, iclass 29, count 2 2006.259.08:11:20.38#ibcon#about to write, iclass 29, count 2 2006.259.08:11:20.38#ibcon#wrote, iclass 29, count 2 2006.259.08:11:20.38#ibcon#about to read 3, iclass 29, count 2 2006.259.08:11:20.41#ibcon#read 3, iclass 29, count 2 2006.259.08:11:20.41#ibcon#about to read 4, iclass 29, count 2 2006.259.08:11:20.41#ibcon#read 4, iclass 29, count 2 2006.259.08:11:20.41#ibcon#about to read 5, iclass 29, count 2 2006.259.08:11:20.41#ibcon#read 5, iclass 29, count 2 2006.259.08:11:20.41#ibcon#about to read 6, iclass 29, count 2 2006.259.08:11:20.41#ibcon#read 6, iclass 29, count 2 2006.259.08:11:20.41#ibcon#end of sib2, iclass 29, count 2 2006.259.08:11:20.41#ibcon#*after write, iclass 29, count 2 2006.259.08:11:20.41#ibcon#*before return 0, iclass 29, count 2 2006.259.08:11:20.41#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.259.08:11:20.41#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.259.08:11:20.41#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.259.08:11:20.41#ibcon#ireg 7 cls_cnt 0 2006.259.08:11:20.41#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.259.08:11:20.53#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.259.08:11:20.53#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.259.08:11:20.53#ibcon#enter wrdev, iclass 29, count 0 2006.259.08:11:20.53#ibcon#first serial, iclass 29, count 0 2006.259.08:11:20.53#ibcon#enter sib2, iclass 29, count 0 2006.259.08:11:20.53#ibcon#flushed, iclass 29, count 0 2006.259.08:11:20.53#ibcon#about to write, iclass 29, count 0 2006.259.08:11:20.53#ibcon#wrote, iclass 29, count 0 2006.259.08:11:20.53#ibcon#about to read 3, iclass 29, count 0 2006.259.08:11:20.55#ibcon#read 3, iclass 29, count 0 2006.259.08:11:20.55#ibcon#about to read 4, iclass 29, count 0 2006.259.08:11:20.55#ibcon#read 4, iclass 29, count 0 2006.259.08:11:20.55#ibcon#about to read 5, iclass 29, count 0 2006.259.08:11:20.55#ibcon#read 5, iclass 29, count 0 2006.259.08:11:20.55#ibcon#about to read 6, iclass 29, count 0 2006.259.08:11:20.55#ibcon#read 6, iclass 29, count 0 2006.259.08:11:20.55#ibcon#end of sib2, iclass 29, count 0 2006.259.08:11:20.55#ibcon#*mode == 0, iclass 29, count 0 2006.259.08:11:20.55#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.259.08:11:20.55#ibcon#[25=USB\r\n] 2006.259.08:11:20.55#ibcon#*before write, iclass 29, count 0 2006.259.08:11:20.55#ibcon#enter sib2, iclass 29, count 0 2006.259.08:11:20.55#ibcon#flushed, iclass 29, count 0 2006.259.08:11:20.55#ibcon#about to write, iclass 29, count 0 2006.259.08:11:20.55#ibcon#wrote, iclass 29, count 0 2006.259.08:11:20.55#ibcon#about to read 3, iclass 29, count 0 2006.259.08:11:20.58#ibcon#read 3, iclass 29, count 0 2006.259.08:11:20.58#ibcon#about to read 4, iclass 29, count 0 2006.259.08:11:20.58#ibcon#read 4, iclass 29, count 0 2006.259.08:11:20.58#ibcon#about to read 5, iclass 29, count 0 2006.259.08:11:20.58#ibcon#read 5, iclass 29, count 0 2006.259.08:11:20.58#ibcon#about to read 6, iclass 29, count 0 2006.259.08:11:20.58#ibcon#read 6, iclass 29, count 0 2006.259.08:11:20.58#ibcon#end of sib2, iclass 29, count 0 2006.259.08:11:20.58#ibcon#*after write, iclass 29, count 0 2006.259.08:11:20.58#ibcon#*before return 0, iclass 29, count 0 2006.259.08:11:20.58#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.259.08:11:20.58#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.259.08:11:20.58#ibcon#about to clear, iclass 29 cls_cnt 0 2006.259.08:11:20.58#ibcon#cleared, iclass 29 cls_cnt 0 2006.259.08:11:20.58$vc4f8/valo=7,832.99 2006.259.08:11:20.58#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.259.08:11:20.58#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.259.08:11:20.58#ibcon#ireg 17 cls_cnt 0 2006.259.08:11:20.58#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.259.08:11:20.58#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.259.08:11:20.58#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.259.08:11:20.58#ibcon#enter wrdev, iclass 31, count 0 2006.259.08:11:20.58#ibcon#first serial, iclass 31, count 0 2006.259.08:11:20.58#ibcon#enter sib2, iclass 31, count 0 2006.259.08:11:20.58#ibcon#flushed, iclass 31, count 0 2006.259.08:11:20.58#ibcon#about to write, iclass 31, count 0 2006.259.08:11:20.58#ibcon#wrote, iclass 31, count 0 2006.259.08:11:20.58#ibcon#about to read 3, iclass 31, count 0 2006.259.08:11:20.60#ibcon#read 3, iclass 31, count 0 2006.259.08:11:20.60#ibcon#about to read 4, iclass 31, count 0 2006.259.08:11:20.60#ibcon#read 4, iclass 31, count 0 2006.259.08:11:20.60#ibcon#about to read 5, iclass 31, count 0 2006.259.08:11:20.60#ibcon#read 5, iclass 31, count 0 2006.259.08:11:20.60#ibcon#about to read 6, iclass 31, count 0 2006.259.08:11:20.60#ibcon#read 6, iclass 31, count 0 2006.259.08:11:20.60#ibcon#end of sib2, iclass 31, count 0 2006.259.08:11:20.60#ibcon#*mode == 0, iclass 31, count 0 2006.259.08:11:20.60#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.259.08:11:20.60#ibcon#[26=FRQ=07,832.99\r\n] 2006.259.08:11:20.60#ibcon#*before write, iclass 31, count 0 2006.259.08:11:20.60#ibcon#enter sib2, iclass 31, count 0 2006.259.08:11:20.60#ibcon#flushed, iclass 31, count 0 2006.259.08:11:20.60#ibcon#about to write, iclass 31, count 0 2006.259.08:11:20.60#ibcon#wrote, iclass 31, count 0 2006.259.08:11:20.60#ibcon#about to read 3, iclass 31, count 0 2006.259.08:11:20.64#ibcon#read 3, iclass 31, count 0 2006.259.08:11:20.64#ibcon#about to read 4, iclass 31, count 0 2006.259.08:11:20.64#ibcon#read 4, iclass 31, count 0 2006.259.08:11:20.64#ibcon#about to read 5, iclass 31, count 0 2006.259.08:11:20.64#ibcon#read 5, iclass 31, count 0 2006.259.08:11:20.64#ibcon#about to read 6, iclass 31, count 0 2006.259.08:11:20.64#ibcon#read 6, iclass 31, count 0 2006.259.08:11:20.64#ibcon#end of sib2, iclass 31, count 0 2006.259.08:11:20.64#ibcon#*after write, iclass 31, count 0 2006.259.08:11:20.64#ibcon#*before return 0, iclass 31, count 0 2006.259.08:11:20.64#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.259.08:11:20.64#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.259.08:11:20.64#ibcon#about to clear, iclass 31 cls_cnt 0 2006.259.08:11:20.64#ibcon#cleared, iclass 31 cls_cnt 0 2006.259.08:11:20.64$vc4f8/va=7,6 2006.259.08:11:20.64#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.259.08:11:20.64#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.259.08:11:20.64#ibcon#ireg 11 cls_cnt 2 2006.259.08:11:20.64#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.259.08:11:20.70#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.259.08:11:20.70#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.259.08:11:20.70#ibcon#enter wrdev, iclass 33, count 2 2006.259.08:11:20.70#ibcon#first serial, iclass 33, count 2 2006.259.08:11:20.70#ibcon#enter sib2, iclass 33, count 2 2006.259.08:11:20.70#ibcon#flushed, iclass 33, count 2 2006.259.08:11:20.70#ibcon#about to write, iclass 33, count 2 2006.259.08:11:20.70#ibcon#wrote, iclass 33, count 2 2006.259.08:11:20.70#ibcon#about to read 3, iclass 33, count 2 2006.259.08:11:20.72#ibcon#read 3, iclass 33, count 2 2006.259.08:11:20.72#ibcon#about to read 4, iclass 33, count 2 2006.259.08:11:20.72#ibcon#read 4, iclass 33, count 2 2006.259.08:11:20.72#ibcon#about to read 5, iclass 33, count 2 2006.259.08:11:20.72#ibcon#read 5, iclass 33, count 2 2006.259.08:11:20.72#ibcon#about to read 6, iclass 33, count 2 2006.259.08:11:20.72#ibcon#read 6, iclass 33, count 2 2006.259.08:11:20.72#ibcon#end of sib2, iclass 33, count 2 2006.259.08:11:20.72#ibcon#*mode == 0, iclass 33, count 2 2006.259.08:11:20.72#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.259.08:11:20.72#ibcon#[25=AT07-06\r\n] 2006.259.08:11:20.72#ibcon#*before write, iclass 33, count 2 2006.259.08:11:20.72#ibcon#enter sib2, iclass 33, count 2 2006.259.08:11:20.72#ibcon#flushed, iclass 33, count 2 2006.259.08:11:20.72#ibcon#about to write, iclass 33, count 2 2006.259.08:11:20.72#ibcon#wrote, iclass 33, count 2 2006.259.08:11:20.72#ibcon#about to read 3, iclass 33, count 2 2006.259.08:11:20.75#ibcon#read 3, iclass 33, count 2 2006.259.08:11:20.75#ibcon#about to read 4, iclass 33, count 2 2006.259.08:11:20.75#ibcon#read 4, iclass 33, count 2 2006.259.08:11:20.75#ibcon#about to read 5, iclass 33, count 2 2006.259.08:11:20.75#ibcon#read 5, iclass 33, count 2 2006.259.08:11:20.75#ibcon#about to read 6, iclass 33, count 2 2006.259.08:11:20.75#ibcon#read 6, iclass 33, count 2 2006.259.08:11:20.75#ibcon#end of sib2, iclass 33, count 2 2006.259.08:11:20.75#ibcon#*after write, iclass 33, count 2 2006.259.08:11:20.75#ibcon#*before return 0, iclass 33, count 2 2006.259.08:11:20.75#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.259.08:11:20.75#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.259.08:11:20.75#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.259.08:11:20.75#ibcon#ireg 7 cls_cnt 0 2006.259.08:11:20.75#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.259.08:11:20.87#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.259.08:11:20.87#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.259.08:11:20.87#ibcon#enter wrdev, iclass 33, count 0 2006.259.08:11:20.87#ibcon#first serial, iclass 33, count 0 2006.259.08:11:20.87#ibcon#enter sib2, iclass 33, count 0 2006.259.08:11:20.87#ibcon#flushed, iclass 33, count 0 2006.259.08:11:20.87#ibcon#about to write, iclass 33, count 0 2006.259.08:11:20.87#ibcon#wrote, iclass 33, count 0 2006.259.08:11:20.87#ibcon#about to read 3, iclass 33, count 0 2006.259.08:11:20.89#ibcon#read 3, iclass 33, count 0 2006.259.08:11:20.89#ibcon#about to read 4, iclass 33, count 0 2006.259.08:11:20.89#ibcon#read 4, iclass 33, count 0 2006.259.08:11:20.89#ibcon#about to read 5, iclass 33, count 0 2006.259.08:11:20.89#ibcon#read 5, iclass 33, count 0 2006.259.08:11:20.89#ibcon#about to read 6, iclass 33, count 0 2006.259.08:11:20.89#ibcon#read 6, iclass 33, count 0 2006.259.08:11:20.89#ibcon#end of sib2, iclass 33, count 0 2006.259.08:11:20.89#ibcon#*mode == 0, iclass 33, count 0 2006.259.08:11:20.89#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.259.08:11:20.89#ibcon#[25=USB\r\n] 2006.259.08:11:20.89#ibcon#*before write, iclass 33, count 0 2006.259.08:11:20.89#ibcon#enter sib2, iclass 33, count 0 2006.259.08:11:20.89#ibcon#flushed, iclass 33, count 0 2006.259.08:11:20.89#ibcon#about to write, iclass 33, count 0 2006.259.08:11:20.89#ibcon#wrote, iclass 33, count 0 2006.259.08:11:20.89#ibcon#about to read 3, iclass 33, count 0 2006.259.08:11:20.92#ibcon#read 3, iclass 33, count 0 2006.259.08:11:20.92#ibcon#about to read 4, iclass 33, count 0 2006.259.08:11:20.92#ibcon#read 4, iclass 33, count 0 2006.259.08:11:20.92#ibcon#about to read 5, iclass 33, count 0 2006.259.08:11:20.92#ibcon#read 5, iclass 33, count 0 2006.259.08:11:20.92#ibcon#about to read 6, iclass 33, count 0 2006.259.08:11:20.92#ibcon#read 6, iclass 33, count 0 2006.259.08:11:20.92#ibcon#end of sib2, iclass 33, count 0 2006.259.08:11:20.92#ibcon#*after write, iclass 33, count 0 2006.259.08:11:20.92#ibcon#*before return 0, iclass 33, count 0 2006.259.08:11:20.92#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.259.08:11:20.92#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.259.08:11:20.92#ibcon#about to clear, iclass 33 cls_cnt 0 2006.259.08:11:20.92#ibcon#cleared, iclass 33 cls_cnt 0 2006.259.08:11:20.92$vc4f8/valo=8,852.99 2006.259.08:11:20.92#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.259.08:11:20.92#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.259.08:11:20.92#ibcon#ireg 17 cls_cnt 0 2006.259.08:11:20.92#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.259.08:11:20.92#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.259.08:11:20.92#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.259.08:11:20.92#ibcon#enter wrdev, iclass 35, count 0 2006.259.08:11:20.92#ibcon#first serial, iclass 35, count 0 2006.259.08:11:20.92#ibcon#enter sib2, iclass 35, count 0 2006.259.08:11:20.92#ibcon#flushed, iclass 35, count 0 2006.259.08:11:20.92#ibcon#about to write, iclass 35, count 0 2006.259.08:11:20.92#ibcon#wrote, iclass 35, count 0 2006.259.08:11:20.92#ibcon#about to read 3, iclass 35, count 0 2006.259.08:11:20.94#ibcon#read 3, iclass 35, count 0 2006.259.08:11:20.94#ibcon#about to read 4, iclass 35, count 0 2006.259.08:11:20.94#ibcon#read 4, iclass 35, count 0 2006.259.08:11:20.94#ibcon#about to read 5, iclass 35, count 0 2006.259.08:11:20.94#ibcon#read 5, iclass 35, count 0 2006.259.08:11:20.94#ibcon#about to read 6, iclass 35, count 0 2006.259.08:11:20.94#ibcon#read 6, iclass 35, count 0 2006.259.08:11:20.94#ibcon#end of sib2, iclass 35, count 0 2006.259.08:11:20.94#ibcon#*mode == 0, iclass 35, count 0 2006.259.08:11:20.94#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.259.08:11:20.94#ibcon#[26=FRQ=08,852.99\r\n] 2006.259.08:11:20.94#ibcon#*before write, iclass 35, count 0 2006.259.08:11:20.94#ibcon#enter sib2, iclass 35, count 0 2006.259.08:11:20.94#ibcon#flushed, iclass 35, count 0 2006.259.08:11:20.94#ibcon#about to write, iclass 35, count 0 2006.259.08:11:20.94#ibcon#wrote, iclass 35, count 0 2006.259.08:11:20.94#ibcon#about to read 3, iclass 35, count 0 2006.259.08:11:20.98#ibcon#read 3, iclass 35, count 0 2006.259.08:11:20.98#ibcon#about to read 4, iclass 35, count 0 2006.259.08:11:20.98#ibcon#read 4, iclass 35, count 0 2006.259.08:11:20.98#ibcon#about to read 5, iclass 35, count 0 2006.259.08:11:20.98#ibcon#read 5, iclass 35, count 0 2006.259.08:11:20.98#ibcon#about to read 6, iclass 35, count 0 2006.259.08:11:20.98#ibcon#read 6, iclass 35, count 0 2006.259.08:11:20.98#ibcon#end of sib2, iclass 35, count 0 2006.259.08:11:20.98#ibcon#*after write, iclass 35, count 0 2006.259.08:11:20.98#ibcon#*before return 0, iclass 35, count 0 2006.259.08:11:20.98#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.259.08:11:20.98#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.259.08:11:20.98#ibcon#about to clear, iclass 35 cls_cnt 0 2006.259.08:11:20.98#ibcon#cleared, iclass 35 cls_cnt 0 2006.259.08:11:20.98$vc4f8/va=8,6 2006.259.08:11:20.98#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.259.08:11:20.98#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.259.08:11:20.98#ibcon#ireg 11 cls_cnt 2 2006.259.08:11:20.98#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.259.08:11:21.04#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.259.08:11:21.04#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.259.08:11:21.04#ibcon#enter wrdev, iclass 37, count 2 2006.259.08:11:21.04#ibcon#first serial, iclass 37, count 2 2006.259.08:11:21.04#ibcon#enter sib2, iclass 37, count 2 2006.259.08:11:21.04#ibcon#flushed, iclass 37, count 2 2006.259.08:11:21.04#ibcon#about to write, iclass 37, count 2 2006.259.08:11:21.04#ibcon#wrote, iclass 37, count 2 2006.259.08:11:21.04#ibcon#about to read 3, iclass 37, count 2 2006.259.08:11:21.06#ibcon#read 3, iclass 37, count 2 2006.259.08:11:21.06#ibcon#about to read 4, iclass 37, count 2 2006.259.08:11:21.06#ibcon#read 4, iclass 37, count 2 2006.259.08:11:21.06#ibcon#about to read 5, iclass 37, count 2 2006.259.08:11:21.06#ibcon#read 5, iclass 37, count 2 2006.259.08:11:21.06#ibcon#about to read 6, iclass 37, count 2 2006.259.08:11:21.06#ibcon#read 6, iclass 37, count 2 2006.259.08:11:21.06#ibcon#end of sib2, iclass 37, count 2 2006.259.08:11:21.06#ibcon#*mode == 0, iclass 37, count 2 2006.259.08:11:21.06#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.259.08:11:21.06#ibcon#[25=AT08-06\r\n] 2006.259.08:11:21.06#ibcon#*before write, iclass 37, count 2 2006.259.08:11:21.06#ibcon#enter sib2, iclass 37, count 2 2006.259.08:11:21.06#ibcon#flushed, iclass 37, count 2 2006.259.08:11:21.06#ibcon#about to write, iclass 37, count 2 2006.259.08:11:21.06#ibcon#wrote, iclass 37, count 2 2006.259.08:11:21.06#ibcon#about to read 3, iclass 37, count 2 2006.259.08:11:21.09#ibcon#read 3, iclass 37, count 2 2006.259.08:11:21.09#ibcon#about to read 4, iclass 37, count 2 2006.259.08:11:21.09#ibcon#read 4, iclass 37, count 2 2006.259.08:11:21.09#ibcon#about to read 5, iclass 37, count 2 2006.259.08:11:21.09#ibcon#read 5, iclass 37, count 2 2006.259.08:11:21.09#ibcon#about to read 6, iclass 37, count 2 2006.259.08:11:21.09#ibcon#read 6, iclass 37, count 2 2006.259.08:11:21.09#ibcon#end of sib2, iclass 37, count 2 2006.259.08:11:21.09#ibcon#*after write, iclass 37, count 2 2006.259.08:11:21.09#ibcon#*before return 0, iclass 37, count 2 2006.259.08:11:21.09#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.259.08:11:21.09#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.259.08:11:21.09#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.259.08:11:21.09#ibcon#ireg 7 cls_cnt 0 2006.259.08:11:21.09#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.259.08:11:21.21#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.259.08:11:21.21#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.259.08:11:21.21#ibcon#enter wrdev, iclass 37, count 0 2006.259.08:11:21.21#ibcon#first serial, iclass 37, count 0 2006.259.08:11:21.21#ibcon#enter sib2, iclass 37, count 0 2006.259.08:11:21.21#ibcon#flushed, iclass 37, count 0 2006.259.08:11:21.21#ibcon#about to write, iclass 37, count 0 2006.259.08:11:21.21#ibcon#wrote, iclass 37, count 0 2006.259.08:11:21.21#ibcon#about to read 3, iclass 37, count 0 2006.259.08:11:21.23#ibcon#read 3, iclass 37, count 0 2006.259.08:11:21.23#ibcon#about to read 4, iclass 37, count 0 2006.259.08:11:21.23#ibcon#read 4, iclass 37, count 0 2006.259.08:11:21.23#ibcon#about to read 5, iclass 37, count 0 2006.259.08:11:21.23#ibcon#read 5, iclass 37, count 0 2006.259.08:11:21.23#ibcon#about to read 6, iclass 37, count 0 2006.259.08:11:21.23#ibcon#read 6, iclass 37, count 0 2006.259.08:11:21.23#ibcon#end of sib2, iclass 37, count 0 2006.259.08:11:21.23#ibcon#*mode == 0, iclass 37, count 0 2006.259.08:11:21.23#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.259.08:11:21.23#ibcon#[25=USB\r\n] 2006.259.08:11:21.23#ibcon#*before write, iclass 37, count 0 2006.259.08:11:21.23#ibcon#enter sib2, iclass 37, count 0 2006.259.08:11:21.23#ibcon#flushed, iclass 37, count 0 2006.259.08:11:21.23#ibcon#about to write, iclass 37, count 0 2006.259.08:11:21.23#ibcon#wrote, iclass 37, count 0 2006.259.08:11:21.23#ibcon#about to read 3, iclass 37, count 0 2006.259.08:11:21.26#ibcon#read 3, iclass 37, count 0 2006.259.08:11:21.26#ibcon#about to read 4, iclass 37, count 0 2006.259.08:11:21.26#ibcon#read 4, iclass 37, count 0 2006.259.08:11:21.26#ibcon#about to read 5, iclass 37, count 0 2006.259.08:11:21.26#ibcon#read 5, iclass 37, count 0 2006.259.08:11:21.26#ibcon#about to read 6, iclass 37, count 0 2006.259.08:11:21.26#ibcon#read 6, iclass 37, count 0 2006.259.08:11:21.26#ibcon#end of sib2, iclass 37, count 0 2006.259.08:11:21.26#ibcon#*after write, iclass 37, count 0 2006.259.08:11:21.26#ibcon#*before return 0, iclass 37, count 0 2006.259.08:11:21.26#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.259.08:11:21.26#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.259.08:11:21.26#ibcon#about to clear, iclass 37 cls_cnt 0 2006.259.08:11:21.26#ibcon#cleared, iclass 37 cls_cnt 0 2006.259.08:11:21.26$vc4f8/vblo=1,632.99 2006.259.08:11:21.26#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.259.08:11:21.26#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.259.08:11:21.26#ibcon#ireg 17 cls_cnt 0 2006.259.08:11:21.26#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.259.08:11:21.26#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.259.08:11:21.26#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.259.08:11:21.26#ibcon#enter wrdev, iclass 39, count 0 2006.259.08:11:21.26#ibcon#first serial, iclass 39, count 0 2006.259.08:11:21.26#ibcon#enter sib2, iclass 39, count 0 2006.259.08:11:21.26#ibcon#flushed, iclass 39, count 0 2006.259.08:11:21.26#ibcon#about to write, iclass 39, count 0 2006.259.08:11:21.26#ibcon#wrote, iclass 39, count 0 2006.259.08:11:21.26#ibcon#about to read 3, iclass 39, count 0 2006.259.08:11:21.28#ibcon#read 3, iclass 39, count 0 2006.259.08:11:21.28#ibcon#about to read 4, iclass 39, count 0 2006.259.08:11:21.28#ibcon#read 4, iclass 39, count 0 2006.259.08:11:21.28#ibcon#about to read 5, iclass 39, count 0 2006.259.08:11:21.28#ibcon#read 5, iclass 39, count 0 2006.259.08:11:21.28#ibcon#about to read 6, iclass 39, count 0 2006.259.08:11:21.28#ibcon#read 6, iclass 39, count 0 2006.259.08:11:21.28#ibcon#end of sib2, iclass 39, count 0 2006.259.08:11:21.28#ibcon#*mode == 0, iclass 39, count 0 2006.259.08:11:21.28#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.259.08:11:21.28#ibcon#[28=FRQ=01,632.99\r\n] 2006.259.08:11:21.28#ibcon#*before write, iclass 39, count 0 2006.259.08:11:21.28#ibcon#enter sib2, iclass 39, count 0 2006.259.08:11:21.28#ibcon#flushed, iclass 39, count 0 2006.259.08:11:21.28#ibcon#about to write, iclass 39, count 0 2006.259.08:11:21.28#ibcon#wrote, iclass 39, count 0 2006.259.08:11:21.28#ibcon#about to read 3, iclass 39, count 0 2006.259.08:11:21.32#ibcon#read 3, iclass 39, count 0 2006.259.08:11:21.32#ibcon#about to read 4, iclass 39, count 0 2006.259.08:11:21.32#ibcon#read 4, iclass 39, count 0 2006.259.08:11:21.32#ibcon#about to read 5, iclass 39, count 0 2006.259.08:11:21.32#ibcon#read 5, iclass 39, count 0 2006.259.08:11:21.32#ibcon#about to read 6, iclass 39, count 0 2006.259.08:11:21.32#ibcon#read 6, iclass 39, count 0 2006.259.08:11:21.32#ibcon#end of sib2, iclass 39, count 0 2006.259.08:11:21.32#ibcon#*after write, iclass 39, count 0 2006.259.08:11:21.32#ibcon#*before return 0, iclass 39, count 0 2006.259.08:11:21.32#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.259.08:11:21.32#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.259.08:11:21.32#ibcon#about to clear, iclass 39 cls_cnt 0 2006.259.08:11:21.32#ibcon#cleared, iclass 39 cls_cnt 0 2006.259.08:11:21.32$vc4f8/vb=1,4 2006.259.08:11:21.32#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.259.08:11:21.32#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.259.08:11:21.32#ibcon#ireg 11 cls_cnt 2 2006.259.08:11:21.32#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.259.08:11:21.32#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.259.08:11:21.32#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.259.08:11:21.32#ibcon#enter wrdev, iclass 3, count 2 2006.259.08:11:21.32#ibcon#first serial, iclass 3, count 2 2006.259.08:11:21.32#ibcon#enter sib2, iclass 3, count 2 2006.259.08:11:21.32#ibcon#flushed, iclass 3, count 2 2006.259.08:11:21.32#ibcon#about to write, iclass 3, count 2 2006.259.08:11:21.32#ibcon#wrote, iclass 3, count 2 2006.259.08:11:21.32#ibcon#about to read 3, iclass 3, count 2 2006.259.08:11:21.34#ibcon#read 3, iclass 3, count 2 2006.259.08:11:21.34#ibcon#about to read 4, iclass 3, count 2 2006.259.08:11:21.34#ibcon#read 4, iclass 3, count 2 2006.259.08:11:21.34#ibcon#about to read 5, iclass 3, count 2 2006.259.08:11:21.34#ibcon#read 5, iclass 3, count 2 2006.259.08:11:21.34#ibcon#about to read 6, iclass 3, count 2 2006.259.08:11:21.34#ibcon#read 6, iclass 3, count 2 2006.259.08:11:21.34#ibcon#end of sib2, iclass 3, count 2 2006.259.08:11:21.34#ibcon#*mode == 0, iclass 3, count 2 2006.259.08:11:21.34#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.259.08:11:21.34#ibcon#[27=AT01-04\r\n] 2006.259.08:11:21.34#ibcon#*before write, iclass 3, count 2 2006.259.08:11:21.34#ibcon#enter sib2, iclass 3, count 2 2006.259.08:11:21.34#ibcon#flushed, iclass 3, count 2 2006.259.08:11:21.34#ibcon#about to write, iclass 3, count 2 2006.259.08:11:21.34#ibcon#wrote, iclass 3, count 2 2006.259.08:11:21.34#ibcon#about to read 3, iclass 3, count 2 2006.259.08:11:21.37#ibcon#read 3, iclass 3, count 2 2006.259.08:11:21.37#ibcon#about to read 4, iclass 3, count 2 2006.259.08:11:21.37#ibcon#read 4, iclass 3, count 2 2006.259.08:11:21.37#ibcon#about to read 5, iclass 3, count 2 2006.259.08:11:21.37#ibcon#read 5, iclass 3, count 2 2006.259.08:11:21.37#ibcon#about to read 6, iclass 3, count 2 2006.259.08:11:21.37#ibcon#read 6, iclass 3, count 2 2006.259.08:11:21.37#ibcon#end of sib2, iclass 3, count 2 2006.259.08:11:21.37#ibcon#*after write, iclass 3, count 2 2006.259.08:11:21.37#ibcon#*before return 0, iclass 3, count 2 2006.259.08:11:21.37#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.259.08:11:21.37#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.259.08:11:21.37#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.259.08:11:21.37#ibcon#ireg 7 cls_cnt 0 2006.259.08:11:21.37#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.259.08:11:21.49#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.259.08:11:21.49#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.259.08:11:21.49#ibcon#enter wrdev, iclass 3, count 0 2006.259.08:11:21.49#ibcon#first serial, iclass 3, count 0 2006.259.08:11:21.49#ibcon#enter sib2, iclass 3, count 0 2006.259.08:11:21.49#ibcon#flushed, iclass 3, count 0 2006.259.08:11:21.49#ibcon#about to write, iclass 3, count 0 2006.259.08:11:21.49#ibcon#wrote, iclass 3, count 0 2006.259.08:11:21.49#ibcon#about to read 3, iclass 3, count 0 2006.259.08:11:21.51#ibcon#read 3, iclass 3, count 0 2006.259.08:11:21.51#ibcon#about to read 4, iclass 3, count 0 2006.259.08:11:21.51#ibcon#read 4, iclass 3, count 0 2006.259.08:11:21.51#ibcon#about to read 5, iclass 3, count 0 2006.259.08:11:21.51#ibcon#read 5, iclass 3, count 0 2006.259.08:11:21.51#ibcon#about to read 6, iclass 3, count 0 2006.259.08:11:21.51#ibcon#read 6, iclass 3, count 0 2006.259.08:11:21.51#ibcon#end of sib2, iclass 3, count 0 2006.259.08:11:21.51#ibcon#*mode == 0, iclass 3, count 0 2006.259.08:11:21.51#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.259.08:11:21.51#ibcon#[27=USB\r\n] 2006.259.08:11:21.51#ibcon#*before write, iclass 3, count 0 2006.259.08:11:21.51#ibcon#enter sib2, iclass 3, count 0 2006.259.08:11:21.51#ibcon#flushed, iclass 3, count 0 2006.259.08:11:21.51#ibcon#about to write, iclass 3, count 0 2006.259.08:11:21.51#ibcon#wrote, iclass 3, count 0 2006.259.08:11:21.51#ibcon#about to read 3, iclass 3, count 0 2006.259.08:11:21.54#ibcon#read 3, iclass 3, count 0 2006.259.08:11:21.54#ibcon#about to read 4, iclass 3, count 0 2006.259.08:11:21.54#ibcon#read 4, iclass 3, count 0 2006.259.08:11:21.54#ibcon#about to read 5, iclass 3, count 0 2006.259.08:11:21.54#ibcon#read 5, iclass 3, count 0 2006.259.08:11:21.54#ibcon#about to read 6, iclass 3, count 0 2006.259.08:11:21.54#ibcon#read 6, iclass 3, count 0 2006.259.08:11:21.54#ibcon#end of sib2, iclass 3, count 0 2006.259.08:11:21.54#ibcon#*after write, iclass 3, count 0 2006.259.08:11:21.54#ibcon#*before return 0, iclass 3, count 0 2006.259.08:11:21.54#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.259.08:11:21.54#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.259.08:11:21.54#ibcon#about to clear, iclass 3 cls_cnt 0 2006.259.08:11:21.54#ibcon#cleared, iclass 3 cls_cnt 0 2006.259.08:11:21.54$vc4f8/vblo=2,640.99 2006.259.08:11:21.54#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.259.08:11:21.54#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.259.08:11:21.54#ibcon#ireg 17 cls_cnt 0 2006.259.08:11:21.54#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.259.08:11:21.54#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.259.08:11:21.54#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.259.08:11:21.54#ibcon#enter wrdev, iclass 5, count 0 2006.259.08:11:21.54#ibcon#first serial, iclass 5, count 0 2006.259.08:11:21.54#ibcon#enter sib2, iclass 5, count 0 2006.259.08:11:21.54#ibcon#flushed, iclass 5, count 0 2006.259.08:11:21.54#ibcon#about to write, iclass 5, count 0 2006.259.08:11:21.54#ibcon#wrote, iclass 5, count 0 2006.259.08:11:21.54#ibcon#about to read 3, iclass 5, count 0 2006.259.08:11:21.56#ibcon#read 3, iclass 5, count 0 2006.259.08:11:21.56#ibcon#about to read 4, iclass 5, count 0 2006.259.08:11:21.56#ibcon#read 4, iclass 5, count 0 2006.259.08:11:21.56#ibcon#about to read 5, iclass 5, count 0 2006.259.08:11:21.56#ibcon#read 5, iclass 5, count 0 2006.259.08:11:21.56#ibcon#about to read 6, iclass 5, count 0 2006.259.08:11:21.56#ibcon#read 6, iclass 5, count 0 2006.259.08:11:21.56#ibcon#end of sib2, iclass 5, count 0 2006.259.08:11:21.56#ibcon#*mode == 0, iclass 5, count 0 2006.259.08:11:21.56#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.259.08:11:21.56#ibcon#[28=FRQ=02,640.99\r\n] 2006.259.08:11:21.56#ibcon#*before write, iclass 5, count 0 2006.259.08:11:21.56#ibcon#enter sib2, iclass 5, count 0 2006.259.08:11:21.56#ibcon#flushed, iclass 5, count 0 2006.259.08:11:21.56#ibcon#about to write, iclass 5, count 0 2006.259.08:11:21.56#ibcon#wrote, iclass 5, count 0 2006.259.08:11:21.56#ibcon#about to read 3, iclass 5, count 0 2006.259.08:11:21.60#ibcon#read 3, iclass 5, count 0 2006.259.08:11:21.60#ibcon#about to read 4, iclass 5, count 0 2006.259.08:11:21.60#ibcon#read 4, iclass 5, count 0 2006.259.08:11:21.60#ibcon#about to read 5, iclass 5, count 0 2006.259.08:11:21.60#ibcon#read 5, iclass 5, count 0 2006.259.08:11:21.60#ibcon#about to read 6, iclass 5, count 0 2006.259.08:11:21.60#ibcon#read 6, iclass 5, count 0 2006.259.08:11:21.60#ibcon#end of sib2, iclass 5, count 0 2006.259.08:11:21.60#ibcon#*after write, iclass 5, count 0 2006.259.08:11:21.60#ibcon#*before return 0, iclass 5, count 0 2006.259.08:11:21.60#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.259.08:11:21.60#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.259.08:11:21.60#ibcon#about to clear, iclass 5 cls_cnt 0 2006.259.08:11:21.60#ibcon#cleared, iclass 5 cls_cnt 0 2006.259.08:11:21.60$vc4f8/vb=2,5 2006.259.08:11:21.60#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.259.08:11:21.60#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.259.08:11:21.60#ibcon#ireg 11 cls_cnt 2 2006.259.08:11:21.60#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.259.08:11:21.66#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.259.08:11:21.66#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.259.08:11:21.66#ibcon#enter wrdev, iclass 7, count 2 2006.259.08:11:21.66#ibcon#first serial, iclass 7, count 2 2006.259.08:11:21.66#ibcon#enter sib2, iclass 7, count 2 2006.259.08:11:21.66#ibcon#flushed, iclass 7, count 2 2006.259.08:11:21.66#ibcon#about to write, iclass 7, count 2 2006.259.08:11:21.66#ibcon#wrote, iclass 7, count 2 2006.259.08:11:21.66#ibcon#about to read 3, iclass 7, count 2 2006.259.08:11:21.69#ibcon#read 3, iclass 7, count 2 2006.259.08:11:21.69#ibcon#about to read 4, iclass 7, count 2 2006.259.08:11:21.69#ibcon#read 4, iclass 7, count 2 2006.259.08:11:21.69#ibcon#about to read 5, iclass 7, count 2 2006.259.08:11:21.69#ibcon#read 5, iclass 7, count 2 2006.259.08:11:21.69#ibcon#about to read 6, iclass 7, count 2 2006.259.08:11:21.69#ibcon#read 6, iclass 7, count 2 2006.259.08:11:21.69#ibcon#end of sib2, iclass 7, count 2 2006.259.08:11:21.69#ibcon#*mode == 0, iclass 7, count 2 2006.259.08:11:21.69#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.259.08:11:21.69#ibcon#[27=AT02-05\r\n] 2006.259.08:11:21.69#ibcon#*before write, iclass 7, count 2 2006.259.08:11:21.69#ibcon#enter sib2, iclass 7, count 2 2006.259.08:11:21.69#ibcon#flushed, iclass 7, count 2 2006.259.08:11:21.69#ibcon#about to write, iclass 7, count 2 2006.259.08:11:21.69#ibcon#wrote, iclass 7, count 2 2006.259.08:11:21.69#ibcon#about to read 3, iclass 7, count 2 2006.259.08:11:21.72#ibcon#read 3, iclass 7, count 2 2006.259.08:11:21.72#ibcon#about to read 4, iclass 7, count 2 2006.259.08:11:21.72#ibcon#read 4, iclass 7, count 2 2006.259.08:11:21.72#ibcon#about to read 5, iclass 7, count 2 2006.259.08:11:21.72#ibcon#read 5, iclass 7, count 2 2006.259.08:11:21.72#ibcon#about to read 6, iclass 7, count 2 2006.259.08:11:21.72#ibcon#read 6, iclass 7, count 2 2006.259.08:11:21.72#ibcon#end of sib2, iclass 7, count 2 2006.259.08:11:21.72#ibcon#*after write, iclass 7, count 2 2006.259.08:11:21.72#ibcon#*before return 0, iclass 7, count 2 2006.259.08:11:21.72#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.259.08:11:21.72#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.259.08:11:21.72#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.259.08:11:21.72#ibcon#ireg 7 cls_cnt 0 2006.259.08:11:21.72#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.259.08:11:21.84#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.259.08:11:21.84#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.259.08:11:21.84#ibcon#enter wrdev, iclass 7, count 0 2006.259.08:11:21.84#ibcon#first serial, iclass 7, count 0 2006.259.08:11:21.84#ibcon#enter sib2, iclass 7, count 0 2006.259.08:11:21.84#ibcon#flushed, iclass 7, count 0 2006.259.08:11:21.84#ibcon#about to write, iclass 7, count 0 2006.259.08:11:21.84#ibcon#wrote, iclass 7, count 0 2006.259.08:11:21.84#ibcon#about to read 3, iclass 7, count 0 2006.259.08:11:21.86#ibcon#read 3, iclass 7, count 0 2006.259.08:11:21.86#ibcon#about to read 4, iclass 7, count 0 2006.259.08:11:21.86#ibcon#read 4, iclass 7, count 0 2006.259.08:11:21.86#ibcon#about to read 5, iclass 7, count 0 2006.259.08:11:21.86#ibcon#read 5, iclass 7, count 0 2006.259.08:11:21.86#ibcon#about to read 6, iclass 7, count 0 2006.259.08:11:21.86#ibcon#read 6, iclass 7, count 0 2006.259.08:11:21.86#ibcon#end of sib2, iclass 7, count 0 2006.259.08:11:21.86#ibcon#*mode == 0, iclass 7, count 0 2006.259.08:11:21.86#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.259.08:11:21.86#ibcon#[27=USB\r\n] 2006.259.08:11:21.86#ibcon#*before write, iclass 7, count 0 2006.259.08:11:21.86#ibcon#enter sib2, iclass 7, count 0 2006.259.08:11:21.86#ibcon#flushed, iclass 7, count 0 2006.259.08:11:21.86#ibcon#about to write, iclass 7, count 0 2006.259.08:11:21.86#ibcon#wrote, iclass 7, count 0 2006.259.08:11:21.86#ibcon#about to read 3, iclass 7, count 0 2006.259.08:11:21.89#ibcon#read 3, iclass 7, count 0 2006.259.08:11:21.89#ibcon#about to read 4, iclass 7, count 0 2006.259.08:11:21.89#ibcon#read 4, iclass 7, count 0 2006.259.08:11:21.89#ibcon#about to read 5, iclass 7, count 0 2006.259.08:11:21.89#ibcon#read 5, iclass 7, count 0 2006.259.08:11:21.89#ibcon#about to read 6, iclass 7, count 0 2006.259.08:11:21.89#ibcon#read 6, iclass 7, count 0 2006.259.08:11:21.89#ibcon#end of sib2, iclass 7, count 0 2006.259.08:11:21.89#ibcon#*after write, iclass 7, count 0 2006.259.08:11:21.89#ibcon#*before return 0, iclass 7, count 0 2006.259.08:11:21.89#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.259.08:11:21.89#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.259.08:11:21.89#ibcon#about to clear, iclass 7 cls_cnt 0 2006.259.08:11:21.89#ibcon#cleared, iclass 7 cls_cnt 0 2006.259.08:11:21.89$vc4f8/vblo=3,656.99 2006.259.08:11:21.89#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.259.08:11:21.89#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.259.08:11:21.89#ibcon#ireg 17 cls_cnt 0 2006.259.08:11:21.89#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.259.08:11:21.89#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.259.08:11:21.89#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.259.08:11:21.89#ibcon#enter wrdev, iclass 11, count 0 2006.259.08:11:21.89#ibcon#first serial, iclass 11, count 0 2006.259.08:11:21.89#ibcon#enter sib2, iclass 11, count 0 2006.259.08:11:21.89#ibcon#flushed, iclass 11, count 0 2006.259.08:11:21.89#ibcon#about to write, iclass 11, count 0 2006.259.08:11:21.89#ibcon#wrote, iclass 11, count 0 2006.259.08:11:21.89#ibcon#about to read 3, iclass 11, count 0 2006.259.08:11:21.91#ibcon#read 3, iclass 11, count 0 2006.259.08:11:21.91#ibcon#about to read 4, iclass 11, count 0 2006.259.08:11:21.91#ibcon#read 4, iclass 11, count 0 2006.259.08:11:21.91#ibcon#about to read 5, iclass 11, count 0 2006.259.08:11:21.91#ibcon#read 5, iclass 11, count 0 2006.259.08:11:21.91#ibcon#about to read 6, iclass 11, count 0 2006.259.08:11:21.91#ibcon#read 6, iclass 11, count 0 2006.259.08:11:21.91#ibcon#end of sib2, iclass 11, count 0 2006.259.08:11:21.91#ibcon#*mode == 0, iclass 11, count 0 2006.259.08:11:21.91#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.259.08:11:21.91#ibcon#[28=FRQ=03,656.99\r\n] 2006.259.08:11:21.91#ibcon#*before write, iclass 11, count 0 2006.259.08:11:21.91#ibcon#enter sib2, iclass 11, count 0 2006.259.08:11:21.91#ibcon#flushed, iclass 11, count 0 2006.259.08:11:21.91#ibcon#about to write, iclass 11, count 0 2006.259.08:11:21.91#ibcon#wrote, iclass 11, count 0 2006.259.08:11:21.91#ibcon#about to read 3, iclass 11, count 0 2006.259.08:11:21.95#ibcon#read 3, iclass 11, count 0 2006.259.08:11:21.95#ibcon#about to read 4, iclass 11, count 0 2006.259.08:11:21.95#ibcon#read 4, iclass 11, count 0 2006.259.08:11:21.95#ibcon#about to read 5, iclass 11, count 0 2006.259.08:11:21.95#ibcon#read 5, iclass 11, count 0 2006.259.08:11:21.95#ibcon#about to read 6, iclass 11, count 0 2006.259.08:11:21.95#ibcon#read 6, iclass 11, count 0 2006.259.08:11:21.95#ibcon#end of sib2, iclass 11, count 0 2006.259.08:11:21.95#ibcon#*after write, iclass 11, count 0 2006.259.08:11:21.95#ibcon#*before return 0, iclass 11, count 0 2006.259.08:11:21.95#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.259.08:11:21.95#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.259.08:11:21.95#ibcon#about to clear, iclass 11 cls_cnt 0 2006.259.08:11:21.95#ibcon#cleared, iclass 11 cls_cnt 0 2006.259.08:11:21.95$vc4f8/vb=3,4 2006.259.08:11:21.95#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.259.08:11:21.95#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.259.08:11:21.95#ibcon#ireg 11 cls_cnt 2 2006.259.08:11:21.95#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.259.08:11:22.01#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.259.08:11:22.01#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.259.08:11:22.01#ibcon#enter wrdev, iclass 13, count 2 2006.259.08:11:22.01#ibcon#first serial, iclass 13, count 2 2006.259.08:11:22.01#ibcon#enter sib2, iclass 13, count 2 2006.259.08:11:22.01#ibcon#flushed, iclass 13, count 2 2006.259.08:11:22.01#ibcon#about to write, iclass 13, count 2 2006.259.08:11:22.01#ibcon#wrote, iclass 13, count 2 2006.259.08:11:22.01#ibcon#about to read 3, iclass 13, count 2 2006.259.08:11:22.03#ibcon#read 3, iclass 13, count 2 2006.259.08:11:22.03#ibcon#about to read 4, iclass 13, count 2 2006.259.08:11:22.03#ibcon#read 4, iclass 13, count 2 2006.259.08:11:22.03#ibcon#about to read 5, iclass 13, count 2 2006.259.08:11:22.03#ibcon#read 5, iclass 13, count 2 2006.259.08:11:22.03#ibcon#about to read 6, iclass 13, count 2 2006.259.08:11:22.03#ibcon#read 6, iclass 13, count 2 2006.259.08:11:22.03#ibcon#end of sib2, iclass 13, count 2 2006.259.08:11:22.03#ibcon#*mode == 0, iclass 13, count 2 2006.259.08:11:22.03#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.259.08:11:22.03#ibcon#[27=AT03-04\r\n] 2006.259.08:11:22.03#ibcon#*before write, iclass 13, count 2 2006.259.08:11:22.03#ibcon#enter sib2, iclass 13, count 2 2006.259.08:11:22.03#ibcon#flushed, iclass 13, count 2 2006.259.08:11:22.03#ibcon#about to write, iclass 13, count 2 2006.259.08:11:22.03#ibcon#wrote, iclass 13, count 2 2006.259.08:11:22.03#ibcon#about to read 3, iclass 13, count 2 2006.259.08:11:22.06#ibcon#read 3, iclass 13, count 2 2006.259.08:11:22.06#ibcon#about to read 4, iclass 13, count 2 2006.259.08:11:22.06#ibcon#read 4, iclass 13, count 2 2006.259.08:11:22.06#ibcon#about to read 5, iclass 13, count 2 2006.259.08:11:22.06#ibcon#read 5, iclass 13, count 2 2006.259.08:11:22.06#ibcon#about to read 6, iclass 13, count 2 2006.259.08:11:22.06#ibcon#read 6, iclass 13, count 2 2006.259.08:11:22.06#ibcon#end of sib2, iclass 13, count 2 2006.259.08:11:22.06#ibcon#*after write, iclass 13, count 2 2006.259.08:11:22.06#ibcon#*before return 0, iclass 13, count 2 2006.259.08:11:22.06#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.259.08:11:22.06#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.259.08:11:22.06#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.259.08:11:22.06#ibcon#ireg 7 cls_cnt 0 2006.259.08:11:22.06#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.259.08:11:22.18#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.259.08:11:22.18#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.259.08:11:22.18#ibcon#enter wrdev, iclass 13, count 0 2006.259.08:11:22.18#ibcon#first serial, iclass 13, count 0 2006.259.08:11:22.18#ibcon#enter sib2, iclass 13, count 0 2006.259.08:11:22.18#ibcon#flushed, iclass 13, count 0 2006.259.08:11:22.18#ibcon#about to write, iclass 13, count 0 2006.259.08:11:22.18#ibcon#wrote, iclass 13, count 0 2006.259.08:11:22.18#ibcon#about to read 3, iclass 13, count 0 2006.259.08:11:22.20#ibcon#read 3, iclass 13, count 0 2006.259.08:11:22.20#ibcon#about to read 4, iclass 13, count 0 2006.259.08:11:22.20#ibcon#read 4, iclass 13, count 0 2006.259.08:11:22.20#ibcon#about to read 5, iclass 13, count 0 2006.259.08:11:22.20#ibcon#read 5, iclass 13, count 0 2006.259.08:11:22.20#ibcon#about to read 6, iclass 13, count 0 2006.259.08:11:22.20#ibcon#read 6, iclass 13, count 0 2006.259.08:11:22.20#ibcon#end of sib2, iclass 13, count 0 2006.259.08:11:22.20#ibcon#*mode == 0, iclass 13, count 0 2006.259.08:11:22.20#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.259.08:11:22.20#ibcon#[27=USB\r\n] 2006.259.08:11:22.20#ibcon#*before write, iclass 13, count 0 2006.259.08:11:22.20#ibcon#enter sib2, iclass 13, count 0 2006.259.08:11:22.20#ibcon#flushed, iclass 13, count 0 2006.259.08:11:22.20#ibcon#about to write, iclass 13, count 0 2006.259.08:11:22.20#ibcon#wrote, iclass 13, count 0 2006.259.08:11:22.20#ibcon#about to read 3, iclass 13, count 0 2006.259.08:11:22.23#ibcon#read 3, iclass 13, count 0 2006.259.08:11:22.23#ibcon#about to read 4, iclass 13, count 0 2006.259.08:11:22.23#ibcon#read 4, iclass 13, count 0 2006.259.08:11:22.23#ibcon#about to read 5, iclass 13, count 0 2006.259.08:11:22.23#ibcon#read 5, iclass 13, count 0 2006.259.08:11:22.23#ibcon#about to read 6, iclass 13, count 0 2006.259.08:11:22.23#ibcon#read 6, iclass 13, count 0 2006.259.08:11:22.23#ibcon#end of sib2, iclass 13, count 0 2006.259.08:11:22.23#ibcon#*after write, iclass 13, count 0 2006.259.08:11:22.23#ibcon#*before return 0, iclass 13, count 0 2006.259.08:11:22.23#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.259.08:11:22.23#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.259.08:11:22.23#ibcon#about to clear, iclass 13 cls_cnt 0 2006.259.08:11:22.23#ibcon#cleared, iclass 13 cls_cnt 0 2006.259.08:11:22.23$vc4f8/vblo=4,712.99 2006.259.08:11:22.23#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.259.08:11:22.23#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.259.08:11:22.23#ibcon#ireg 17 cls_cnt 0 2006.259.08:11:22.23#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.259.08:11:22.23#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.259.08:11:22.23#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.259.08:11:22.23#ibcon#enter wrdev, iclass 15, count 0 2006.259.08:11:22.23#ibcon#first serial, iclass 15, count 0 2006.259.08:11:22.23#ibcon#enter sib2, iclass 15, count 0 2006.259.08:11:22.23#ibcon#flushed, iclass 15, count 0 2006.259.08:11:22.23#ibcon#about to write, iclass 15, count 0 2006.259.08:11:22.23#ibcon#wrote, iclass 15, count 0 2006.259.08:11:22.23#ibcon#about to read 3, iclass 15, count 0 2006.259.08:11:22.25#ibcon#read 3, iclass 15, count 0 2006.259.08:11:22.25#ibcon#about to read 4, iclass 15, count 0 2006.259.08:11:22.25#ibcon#read 4, iclass 15, count 0 2006.259.08:11:22.25#ibcon#about to read 5, iclass 15, count 0 2006.259.08:11:22.25#ibcon#read 5, iclass 15, count 0 2006.259.08:11:22.25#ibcon#about to read 6, iclass 15, count 0 2006.259.08:11:22.25#ibcon#read 6, iclass 15, count 0 2006.259.08:11:22.25#ibcon#end of sib2, iclass 15, count 0 2006.259.08:11:22.25#ibcon#*mode == 0, iclass 15, count 0 2006.259.08:11:22.25#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.259.08:11:22.25#ibcon#[28=FRQ=04,712.99\r\n] 2006.259.08:11:22.25#ibcon#*before write, iclass 15, count 0 2006.259.08:11:22.25#ibcon#enter sib2, iclass 15, count 0 2006.259.08:11:22.25#ibcon#flushed, iclass 15, count 0 2006.259.08:11:22.25#ibcon#about to write, iclass 15, count 0 2006.259.08:11:22.25#ibcon#wrote, iclass 15, count 0 2006.259.08:11:22.25#ibcon#about to read 3, iclass 15, count 0 2006.259.08:11:22.29#ibcon#read 3, iclass 15, count 0 2006.259.08:11:22.29#ibcon#about to read 4, iclass 15, count 0 2006.259.08:11:22.29#ibcon#read 4, iclass 15, count 0 2006.259.08:11:22.29#ibcon#about to read 5, iclass 15, count 0 2006.259.08:11:22.29#ibcon#read 5, iclass 15, count 0 2006.259.08:11:22.29#ibcon#about to read 6, iclass 15, count 0 2006.259.08:11:22.29#ibcon#read 6, iclass 15, count 0 2006.259.08:11:22.29#ibcon#end of sib2, iclass 15, count 0 2006.259.08:11:22.29#ibcon#*after write, iclass 15, count 0 2006.259.08:11:22.29#ibcon#*before return 0, iclass 15, count 0 2006.259.08:11:22.29#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.259.08:11:22.29#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.259.08:11:22.29#ibcon#about to clear, iclass 15 cls_cnt 0 2006.259.08:11:22.29#ibcon#cleared, iclass 15 cls_cnt 0 2006.259.08:11:22.29$vc4f8/vb=4,5 2006.259.08:11:22.29#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.259.08:11:22.29#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.259.08:11:22.29#ibcon#ireg 11 cls_cnt 2 2006.259.08:11:22.29#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.259.08:11:22.35#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.259.08:11:22.35#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.259.08:11:22.35#ibcon#enter wrdev, iclass 17, count 2 2006.259.08:11:22.35#ibcon#first serial, iclass 17, count 2 2006.259.08:11:22.35#ibcon#enter sib2, iclass 17, count 2 2006.259.08:11:22.35#ibcon#flushed, iclass 17, count 2 2006.259.08:11:22.35#ibcon#about to write, iclass 17, count 2 2006.259.08:11:22.35#ibcon#wrote, iclass 17, count 2 2006.259.08:11:22.35#ibcon#about to read 3, iclass 17, count 2 2006.259.08:11:22.37#ibcon#read 3, iclass 17, count 2 2006.259.08:11:22.37#ibcon#about to read 4, iclass 17, count 2 2006.259.08:11:22.37#ibcon#read 4, iclass 17, count 2 2006.259.08:11:22.37#ibcon#about to read 5, iclass 17, count 2 2006.259.08:11:22.37#ibcon#read 5, iclass 17, count 2 2006.259.08:11:22.37#ibcon#about to read 6, iclass 17, count 2 2006.259.08:11:22.37#ibcon#read 6, iclass 17, count 2 2006.259.08:11:22.37#ibcon#end of sib2, iclass 17, count 2 2006.259.08:11:22.37#ibcon#*mode == 0, iclass 17, count 2 2006.259.08:11:22.37#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.259.08:11:22.37#ibcon#[27=AT04-05\r\n] 2006.259.08:11:22.37#ibcon#*before write, iclass 17, count 2 2006.259.08:11:22.37#ibcon#enter sib2, iclass 17, count 2 2006.259.08:11:22.37#ibcon#flushed, iclass 17, count 2 2006.259.08:11:22.37#ibcon#about to write, iclass 17, count 2 2006.259.08:11:22.37#ibcon#wrote, iclass 17, count 2 2006.259.08:11:22.37#ibcon#about to read 3, iclass 17, count 2 2006.259.08:11:22.40#ibcon#read 3, iclass 17, count 2 2006.259.08:11:22.40#ibcon#about to read 4, iclass 17, count 2 2006.259.08:11:22.40#ibcon#read 4, iclass 17, count 2 2006.259.08:11:22.40#ibcon#about to read 5, iclass 17, count 2 2006.259.08:11:22.40#ibcon#read 5, iclass 17, count 2 2006.259.08:11:22.40#ibcon#about to read 6, iclass 17, count 2 2006.259.08:11:22.40#ibcon#read 6, iclass 17, count 2 2006.259.08:11:22.40#ibcon#end of sib2, iclass 17, count 2 2006.259.08:11:22.40#ibcon#*after write, iclass 17, count 2 2006.259.08:11:22.40#ibcon#*before return 0, iclass 17, count 2 2006.259.08:11:22.40#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.259.08:11:22.40#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.259.08:11:22.40#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.259.08:11:22.40#ibcon#ireg 7 cls_cnt 0 2006.259.08:11:22.40#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.259.08:11:22.52#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.259.08:11:22.52#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.259.08:11:22.52#ibcon#enter wrdev, iclass 17, count 0 2006.259.08:11:22.52#ibcon#first serial, iclass 17, count 0 2006.259.08:11:22.52#ibcon#enter sib2, iclass 17, count 0 2006.259.08:11:22.52#ibcon#flushed, iclass 17, count 0 2006.259.08:11:22.52#ibcon#about to write, iclass 17, count 0 2006.259.08:11:22.52#ibcon#wrote, iclass 17, count 0 2006.259.08:11:22.52#ibcon#about to read 3, iclass 17, count 0 2006.259.08:11:22.54#ibcon#read 3, iclass 17, count 0 2006.259.08:11:22.54#ibcon#about to read 4, iclass 17, count 0 2006.259.08:11:22.54#ibcon#read 4, iclass 17, count 0 2006.259.08:11:22.54#ibcon#about to read 5, iclass 17, count 0 2006.259.08:11:22.54#ibcon#read 5, iclass 17, count 0 2006.259.08:11:22.54#ibcon#about to read 6, iclass 17, count 0 2006.259.08:11:22.54#ibcon#read 6, iclass 17, count 0 2006.259.08:11:22.54#ibcon#end of sib2, iclass 17, count 0 2006.259.08:11:22.54#ibcon#*mode == 0, iclass 17, count 0 2006.259.08:11:22.54#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.259.08:11:22.54#ibcon#[27=USB\r\n] 2006.259.08:11:22.54#ibcon#*before write, iclass 17, count 0 2006.259.08:11:22.54#ibcon#enter sib2, iclass 17, count 0 2006.259.08:11:22.54#ibcon#flushed, iclass 17, count 0 2006.259.08:11:22.54#ibcon#about to write, iclass 17, count 0 2006.259.08:11:22.54#ibcon#wrote, iclass 17, count 0 2006.259.08:11:22.54#ibcon#about to read 3, iclass 17, count 0 2006.259.08:11:22.57#ibcon#read 3, iclass 17, count 0 2006.259.08:11:22.57#ibcon#about to read 4, iclass 17, count 0 2006.259.08:11:22.57#ibcon#read 4, iclass 17, count 0 2006.259.08:11:22.57#ibcon#about to read 5, iclass 17, count 0 2006.259.08:11:22.57#ibcon#read 5, iclass 17, count 0 2006.259.08:11:22.57#ibcon#about to read 6, iclass 17, count 0 2006.259.08:11:22.57#ibcon#read 6, iclass 17, count 0 2006.259.08:11:22.57#ibcon#end of sib2, iclass 17, count 0 2006.259.08:11:22.57#ibcon#*after write, iclass 17, count 0 2006.259.08:11:22.57#ibcon#*before return 0, iclass 17, count 0 2006.259.08:11:22.57#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.259.08:11:22.57#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.259.08:11:22.57#ibcon#about to clear, iclass 17 cls_cnt 0 2006.259.08:11:22.57#ibcon#cleared, iclass 17 cls_cnt 0 2006.259.08:11:22.57$vc4f8/vblo=5,744.99 2006.259.08:11:22.57#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.259.08:11:22.57#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.259.08:11:22.57#ibcon#ireg 17 cls_cnt 0 2006.259.08:11:22.57#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.259.08:11:22.57#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.259.08:11:22.57#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.259.08:11:22.57#ibcon#enter wrdev, iclass 19, count 0 2006.259.08:11:22.57#ibcon#first serial, iclass 19, count 0 2006.259.08:11:22.57#ibcon#enter sib2, iclass 19, count 0 2006.259.08:11:22.57#ibcon#flushed, iclass 19, count 0 2006.259.08:11:22.57#ibcon#about to write, iclass 19, count 0 2006.259.08:11:22.57#ibcon#wrote, iclass 19, count 0 2006.259.08:11:22.57#ibcon#about to read 3, iclass 19, count 0 2006.259.08:11:22.59#ibcon#read 3, iclass 19, count 0 2006.259.08:11:22.59#ibcon#about to read 4, iclass 19, count 0 2006.259.08:11:22.59#ibcon#read 4, iclass 19, count 0 2006.259.08:11:22.59#ibcon#about to read 5, iclass 19, count 0 2006.259.08:11:22.59#ibcon#read 5, iclass 19, count 0 2006.259.08:11:22.59#ibcon#about to read 6, iclass 19, count 0 2006.259.08:11:22.59#ibcon#read 6, iclass 19, count 0 2006.259.08:11:22.59#ibcon#end of sib2, iclass 19, count 0 2006.259.08:11:22.59#ibcon#*mode == 0, iclass 19, count 0 2006.259.08:11:22.59#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.259.08:11:22.59#ibcon#[28=FRQ=05,744.99\r\n] 2006.259.08:11:22.59#ibcon#*before write, iclass 19, count 0 2006.259.08:11:22.59#ibcon#enter sib2, iclass 19, count 0 2006.259.08:11:22.59#ibcon#flushed, iclass 19, count 0 2006.259.08:11:22.59#ibcon#about to write, iclass 19, count 0 2006.259.08:11:22.59#ibcon#wrote, iclass 19, count 0 2006.259.08:11:22.59#ibcon#about to read 3, iclass 19, count 0 2006.259.08:11:22.63#ibcon#read 3, iclass 19, count 0 2006.259.08:11:22.63#ibcon#about to read 4, iclass 19, count 0 2006.259.08:11:22.63#ibcon#read 4, iclass 19, count 0 2006.259.08:11:22.63#ibcon#about to read 5, iclass 19, count 0 2006.259.08:11:22.63#ibcon#read 5, iclass 19, count 0 2006.259.08:11:22.63#ibcon#about to read 6, iclass 19, count 0 2006.259.08:11:22.63#ibcon#read 6, iclass 19, count 0 2006.259.08:11:22.63#ibcon#end of sib2, iclass 19, count 0 2006.259.08:11:22.63#ibcon#*after write, iclass 19, count 0 2006.259.08:11:22.63#ibcon#*before return 0, iclass 19, count 0 2006.259.08:11:22.63#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.259.08:11:22.63#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.259.08:11:22.63#ibcon#about to clear, iclass 19 cls_cnt 0 2006.259.08:11:22.63#ibcon#cleared, iclass 19 cls_cnt 0 2006.259.08:11:22.63$vc4f8/vb=5,4 2006.259.08:11:22.63#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.259.08:11:22.63#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.259.08:11:22.63#ibcon#ireg 11 cls_cnt 2 2006.259.08:11:22.63#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.259.08:11:22.69#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.259.08:11:22.69#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.259.08:11:22.69#ibcon#enter wrdev, iclass 21, count 2 2006.259.08:11:22.69#ibcon#first serial, iclass 21, count 2 2006.259.08:11:22.69#ibcon#enter sib2, iclass 21, count 2 2006.259.08:11:22.69#ibcon#flushed, iclass 21, count 2 2006.259.08:11:22.69#ibcon#about to write, iclass 21, count 2 2006.259.08:11:22.69#ibcon#wrote, iclass 21, count 2 2006.259.08:11:22.69#ibcon#about to read 3, iclass 21, count 2 2006.259.08:11:22.71#ibcon#read 3, iclass 21, count 2 2006.259.08:11:22.71#ibcon#about to read 4, iclass 21, count 2 2006.259.08:11:22.71#ibcon#read 4, iclass 21, count 2 2006.259.08:11:22.71#ibcon#about to read 5, iclass 21, count 2 2006.259.08:11:22.71#ibcon#read 5, iclass 21, count 2 2006.259.08:11:22.71#ibcon#about to read 6, iclass 21, count 2 2006.259.08:11:22.71#ibcon#read 6, iclass 21, count 2 2006.259.08:11:22.71#ibcon#end of sib2, iclass 21, count 2 2006.259.08:11:22.71#ibcon#*mode == 0, iclass 21, count 2 2006.259.08:11:22.71#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.259.08:11:22.71#ibcon#[27=AT05-04\r\n] 2006.259.08:11:22.71#ibcon#*before write, iclass 21, count 2 2006.259.08:11:22.71#ibcon#enter sib2, iclass 21, count 2 2006.259.08:11:22.71#ibcon#flushed, iclass 21, count 2 2006.259.08:11:22.71#ibcon#about to write, iclass 21, count 2 2006.259.08:11:22.71#ibcon#wrote, iclass 21, count 2 2006.259.08:11:22.71#ibcon#about to read 3, iclass 21, count 2 2006.259.08:11:22.74#ibcon#read 3, iclass 21, count 2 2006.259.08:11:22.74#ibcon#about to read 4, iclass 21, count 2 2006.259.08:11:22.74#ibcon#read 4, iclass 21, count 2 2006.259.08:11:22.74#ibcon#about to read 5, iclass 21, count 2 2006.259.08:11:22.74#ibcon#read 5, iclass 21, count 2 2006.259.08:11:22.74#ibcon#about to read 6, iclass 21, count 2 2006.259.08:11:22.74#ibcon#read 6, iclass 21, count 2 2006.259.08:11:22.74#ibcon#end of sib2, iclass 21, count 2 2006.259.08:11:22.74#ibcon#*after write, iclass 21, count 2 2006.259.08:11:22.74#ibcon#*before return 0, iclass 21, count 2 2006.259.08:11:22.74#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.259.08:11:22.74#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.259.08:11:22.74#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.259.08:11:22.74#ibcon#ireg 7 cls_cnt 0 2006.259.08:11:22.74#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.259.08:11:22.86#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.259.08:11:22.86#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.259.08:11:22.86#ibcon#enter wrdev, iclass 21, count 0 2006.259.08:11:22.86#ibcon#first serial, iclass 21, count 0 2006.259.08:11:22.86#ibcon#enter sib2, iclass 21, count 0 2006.259.08:11:22.86#ibcon#flushed, iclass 21, count 0 2006.259.08:11:22.86#ibcon#about to write, iclass 21, count 0 2006.259.08:11:22.86#ibcon#wrote, iclass 21, count 0 2006.259.08:11:22.86#ibcon#about to read 3, iclass 21, count 0 2006.259.08:11:22.88#ibcon#read 3, iclass 21, count 0 2006.259.08:11:22.88#ibcon#about to read 4, iclass 21, count 0 2006.259.08:11:22.88#ibcon#read 4, iclass 21, count 0 2006.259.08:11:22.88#ibcon#about to read 5, iclass 21, count 0 2006.259.08:11:22.88#ibcon#read 5, iclass 21, count 0 2006.259.08:11:22.88#ibcon#about to read 6, iclass 21, count 0 2006.259.08:11:22.88#ibcon#read 6, iclass 21, count 0 2006.259.08:11:22.88#ibcon#end of sib2, iclass 21, count 0 2006.259.08:11:22.88#ibcon#*mode == 0, iclass 21, count 0 2006.259.08:11:22.88#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.259.08:11:22.88#ibcon#[27=USB\r\n] 2006.259.08:11:22.88#ibcon#*before write, iclass 21, count 0 2006.259.08:11:22.88#ibcon#enter sib2, iclass 21, count 0 2006.259.08:11:22.88#ibcon#flushed, iclass 21, count 0 2006.259.08:11:22.88#ibcon#about to write, iclass 21, count 0 2006.259.08:11:22.88#ibcon#wrote, iclass 21, count 0 2006.259.08:11:22.88#ibcon#about to read 3, iclass 21, count 0 2006.259.08:11:22.91#ibcon#read 3, iclass 21, count 0 2006.259.08:11:22.91#ibcon#about to read 4, iclass 21, count 0 2006.259.08:11:22.91#ibcon#read 4, iclass 21, count 0 2006.259.08:11:22.91#ibcon#about to read 5, iclass 21, count 0 2006.259.08:11:22.91#ibcon#read 5, iclass 21, count 0 2006.259.08:11:22.91#ibcon#about to read 6, iclass 21, count 0 2006.259.08:11:22.91#ibcon#read 6, iclass 21, count 0 2006.259.08:11:22.91#ibcon#end of sib2, iclass 21, count 0 2006.259.08:11:22.91#ibcon#*after write, iclass 21, count 0 2006.259.08:11:22.91#ibcon#*before return 0, iclass 21, count 0 2006.259.08:11:22.91#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.259.08:11:22.91#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.259.08:11:22.91#ibcon#about to clear, iclass 21 cls_cnt 0 2006.259.08:11:22.91#ibcon#cleared, iclass 21 cls_cnt 0 2006.259.08:11:22.91$vc4f8/vblo=6,752.99 2006.259.08:11:22.91#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.259.08:11:22.91#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.259.08:11:22.91#ibcon#ireg 17 cls_cnt 0 2006.259.08:11:22.91#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.259.08:11:22.91#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.259.08:11:22.91#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.259.08:11:22.91#ibcon#enter wrdev, iclass 23, count 0 2006.259.08:11:22.91#ibcon#first serial, iclass 23, count 0 2006.259.08:11:22.91#ibcon#enter sib2, iclass 23, count 0 2006.259.08:11:22.91#ibcon#flushed, iclass 23, count 0 2006.259.08:11:22.91#ibcon#about to write, iclass 23, count 0 2006.259.08:11:22.91#ibcon#wrote, iclass 23, count 0 2006.259.08:11:22.91#ibcon#about to read 3, iclass 23, count 0 2006.259.08:11:22.93#ibcon#read 3, iclass 23, count 0 2006.259.08:11:22.93#ibcon#about to read 4, iclass 23, count 0 2006.259.08:11:22.93#ibcon#read 4, iclass 23, count 0 2006.259.08:11:22.93#ibcon#about to read 5, iclass 23, count 0 2006.259.08:11:22.93#ibcon#read 5, iclass 23, count 0 2006.259.08:11:22.93#ibcon#about to read 6, iclass 23, count 0 2006.259.08:11:22.93#ibcon#read 6, iclass 23, count 0 2006.259.08:11:22.93#ibcon#end of sib2, iclass 23, count 0 2006.259.08:11:22.93#ibcon#*mode == 0, iclass 23, count 0 2006.259.08:11:22.93#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.259.08:11:22.93#ibcon#[28=FRQ=06,752.99\r\n] 2006.259.08:11:22.93#ibcon#*before write, iclass 23, count 0 2006.259.08:11:22.93#ibcon#enter sib2, iclass 23, count 0 2006.259.08:11:22.93#ibcon#flushed, iclass 23, count 0 2006.259.08:11:22.93#ibcon#about to write, iclass 23, count 0 2006.259.08:11:22.93#ibcon#wrote, iclass 23, count 0 2006.259.08:11:22.93#ibcon#about to read 3, iclass 23, count 0 2006.259.08:11:22.97#ibcon#read 3, iclass 23, count 0 2006.259.08:11:22.97#ibcon#about to read 4, iclass 23, count 0 2006.259.08:11:22.97#ibcon#read 4, iclass 23, count 0 2006.259.08:11:22.97#ibcon#about to read 5, iclass 23, count 0 2006.259.08:11:22.97#ibcon#read 5, iclass 23, count 0 2006.259.08:11:22.97#ibcon#about to read 6, iclass 23, count 0 2006.259.08:11:22.97#ibcon#read 6, iclass 23, count 0 2006.259.08:11:22.97#ibcon#end of sib2, iclass 23, count 0 2006.259.08:11:22.97#ibcon#*after write, iclass 23, count 0 2006.259.08:11:22.97#ibcon#*before return 0, iclass 23, count 0 2006.259.08:11:22.97#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.259.08:11:22.97#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.259.08:11:22.97#ibcon#about to clear, iclass 23 cls_cnt 0 2006.259.08:11:22.97#ibcon#cleared, iclass 23 cls_cnt 0 2006.259.08:11:22.97$vc4f8/vb=6,4 2006.259.08:11:22.97#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.259.08:11:22.97#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.259.08:11:22.97#ibcon#ireg 11 cls_cnt 2 2006.259.08:11:22.97#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.259.08:11:23.03#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.259.08:11:23.03#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.259.08:11:23.03#ibcon#enter wrdev, iclass 25, count 2 2006.259.08:11:23.03#ibcon#first serial, iclass 25, count 2 2006.259.08:11:23.03#ibcon#enter sib2, iclass 25, count 2 2006.259.08:11:23.03#ibcon#flushed, iclass 25, count 2 2006.259.08:11:23.03#ibcon#about to write, iclass 25, count 2 2006.259.08:11:23.03#ibcon#wrote, iclass 25, count 2 2006.259.08:11:23.03#ibcon#about to read 3, iclass 25, count 2 2006.259.08:11:23.05#ibcon#read 3, iclass 25, count 2 2006.259.08:11:23.05#ibcon#about to read 4, iclass 25, count 2 2006.259.08:11:23.05#ibcon#read 4, iclass 25, count 2 2006.259.08:11:23.05#ibcon#about to read 5, iclass 25, count 2 2006.259.08:11:23.05#ibcon#read 5, iclass 25, count 2 2006.259.08:11:23.05#ibcon#about to read 6, iclass 25, count 2 2006.259.08:11:23.05#ibcon#read 6, iclass 25, count 2 2006.259.08:11:23.05#ibcon#end of sib2, iclass 25, count 2 2006.259.08:11:23.05#ibcon#*mode == 0, iclass 25, count 2 2006.259.08:11:23.05#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.259.08:11:23.05#ibcon#[27=AT06-04\r\n] 2006.259.08:11:23.05#ibcon#*before write, iclass 25, count 2 2006.259.08:11:23.05#ibcon#enter sib2, iclass 25, count 2 2006.259.08:11:23.05#ibcon#flushed, iclass 25, count 2 2006.259.08:11:23.05#ibcon#about to write, iclass 25, count 2 2006.259.08:11:23.05#ibcon#wrote, iclass 25, count 2 2006.259.08:11:23.05#ibcon#about to read 3, iclass 25, count 2 2006.259.08:11:23.08#ibcon#read 3, iclass 25, count 2 2006.259.08:11:23.08#ibcon#about to read 4, iclass 25, count 2 2006.259.08:11:23.08#ibcon#read 4, iclass 25, count 2 2006.259.08:11:23.08#ibcon#about to read 5, iclass 25, count 2 2006.259.08:11:23.08#ibcon#read 5, iclass 25, count 2 2006.259.08:11:23.08#ibcon#about to read 6, iclass 25, count 2 2006.259.08:11:23.08#ibcon#read 6, iclass 25, count 2 2006.259.08:11:23.08#ibcon#end of sib2, iclass 25, count 2 2006.259.08:11:23.08#ibcon#*after write, iclass 25, count 2 2006.259.08:11:23.08#ibcon#*before return 0, iclass 25, count 2 2006.259.08:11:23.08#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.259.08:11:23.08#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.259.08:11:23.08#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.259.08:11:23.08#ibcon#ireg 7 cls_cnt 0 2006.259.08:11:23.08#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.259.08:11:23.20#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.259.08:11:23.20#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.259.08:11:23.20#ibcon#enter wrdev, iclass 25, count 0 2006.259.08:11:23.20#ibcon#first serial, iclass 25, count 0 2006.259.08:11:23.20#ibcon#enter sib2, iclass 25, count 0 2006.259.08:11:23.20#ibcon#flushed, iclass 25, count 0 2006.259.08:11:23.20#ibcon#about to write, iclass 25, count 0 2006.259.08:11:23.20#ibcon#wrote, iclass 25, count 0 2006.259.08:11:23.20#ibcon#about to read 3, iclass 25, count 0 2006.259.08:11:23.22#ibcon#read 3, iclass 25, count 0 2006.259.08:11:23.22#ibcon#about to read 4, iclass 25, count 0 2006.259.08:11:23.22#ibcon#read 4, iclass 25, count 0 2006.259.08:11:23.22#ibcon#about to read 5, iclass 25, count 0 2006.259.08:11:23.22#ibcon#read 5, iclass 25, count 0 2006.259.08:11:23.22#ibcon#about to read 6, iclass 25, count 0 2006.259.08:11:23.22#ibcon#read 6, iclass 25, count 0 2006.259.08:11:23.22#ibcon#end of sib2, iclass 25, count 0 2006.259.08:11:23.22#ibcon#*mode == 0, iclass 25, count 0 2006.259.08:11:23.22#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.259.08:11:23.22#ibcon#[27=USB\r\n] 2006.259.08:11:23.22#ibcon#*before write, iclass 25, count 0 2006.259.08:11:23.22#ibcon#enter sib2, iclass 25, count 0 2006.259.08:11:23.22#ibcon#flushed, iclass 25, count 0 2006.259.08:11:23.22#ibcon#about to write, iclass 25, count 0 2006.259.08:11:23.22#ibcon#wrote, iclass 25, count 0 2006.259.08:11:23.22#ibcon#about to read 3, iclass 25, count 0 2006.259.08:11:23.25#ibcon#read 3, iclass 25, count 0 2006.259.08:11:23.25#ibcon#about to read 4, iclass 25, count 0 2006.259.08:11:23.25#ibcon#read 4, iclass 25, count 0 2006.259.08:11:23.25#ibcon#about to read 5, iclass 25, count 0 2006.259.08:11:23.25#ibcon#read 5, iclass 25, count 0 2006.259.08:11:23.25#ibcon#about to read 6, iclass 25, count 0 2006.259.08:11:23.25#ibcon#read 6, iclass 25, count 0 2006.259.08:11:23.25#ibcon#end of sib2, iclass 25, count 0 2006.259.08:11:23.25#ibcon#*after write, iclass 25, count 0 2006.259.08:11:23.25#ibcon#*before return 0, iclass 25, count 0 2006.259.08:11:23.25#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.259.08:11:23.25#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.259.08:11:23.25#ibcon#about to clear, iclass 25 cls_cnt 0 2006.259.08:11:23.25#ibcon#cleared, iclass 25 cls_cnt 0 2006.259.08:11:23.25$vc4f8/vabw=wide 2006.259.08:11:23.25#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.259.08:11:23.25#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.259.08:11:23.25#ibcon#ireg 8 cls_cnt 0 2006.259.08:11:23.25#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.259.08:11:23.25#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.259.08:11:23.25#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.259.08:11:23.25#ibcon#enter wrdev, iclass 27, count 0 2006.259.08:11:23.25#ibcon#first serial, iclass 27, count 0 2006.259.08:11:23.25#ibcon#enter sib2, iclass 27, count 0 2006.259.08:11:23.25#ibcon#flushed, iclass 27, count 0 2006.259.08:11:23.25#ibcon#about to write, iclass 27, count 0 2006.259.08:11:23.25#ibcon#wrote, iclass 27, count 0 2006.259.08:11:23.25#ibcon#about to read 3, iclass 27, count 0 2006.259.08:11:23.27#ibcon#read 3, iclass 27, count 0 2006.259.08:11:23.27#ibcon#about to read 4, iclass 27, count 0 2006.259.08:11:23.27#ibcon#read 4, iclass 27, count 0 2006.259.08:11:23.27#ibcon#about to read 5, iclass 27, count 0 2006.259.08:11:23.27#ibcon#read 5, iclass 27, count 0 2006.259.08:11:23.27#ibcon#about to read 6, iclass 27, count 0 2006.259.08:11:23.27#ibcon#read 6, iclass 27, count 0 2006.259.08:11:23.27#ibcon#end of sib2, iclass 27, count 0 2006.259.08:11:23.27#ibcon#*mode == 0, iclass 27, count 0 2006.259.08:11:23.27#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.259.08:11:23.27#ibcon#[25=BW32\r\n] 2006.259.08:11:23.27#ibcon#*before write, iclass 27, count 0 2006.259.08:11:23.27#ibcon#enter sib2, iclass 27, count 0 2006.259.08:11:23.27#ibcon#flushed, iclass 27, count 0 2006.259.08:11:23.27#ibcon#about to write, iclass 27, count 0 2006.259.08:11:23.27#ibcon#wrote, iclass 27, count 0 2006.259.08:11:23.27#ibcon#about to read 3, iclass 27, count 0 2006.259.08:11:23.30#ibcon#read 3, iclass 27, count 0 2006.259.08:11:23.30#ibcon#about to read 4, iclass 27, count 0 2006.259.08:11:23.30#ibcon#read 4, iclass 27, count 0 2006.259.08:11:23.30#ibcon#about to read 5, iclass 27, count 0 2006.259.08:11:23.30#ibcon#read 5, iclass 27, count 0 2006.259.08:11:23.30#ibcon#about to read 6, iclass 27, count 0 2006.259.08:11:23.30#ibcon#read 6, iclass 27, count 0 2006.259.08:11:23.30#ibcon#end of sib2, iclass 27, count 0 2006.259.08:11:23.30#ibcon#*after write, iclass 27, count 0 2006.259.08:11:23.30#ibcon#*before return 0, iclass 27, count 0 2006.259.08:11:23.30#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.259.08:11:23.30#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.259.08:11:23.30#ibcon#about to clear, iclass 27 cls_cnt 0 2006.259.08:11:23.30#ibcon#cleared, iclass 27 cls_cnt 0 2006.259.08:11:23.30$vc4f8/vbbw=wide 2006.259.08:11:23.30#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.259.08:11:23.30#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.259.08:11:23.30#ibcon#ireg 8 cls_cnt 0 2006.259.08:11:23.30#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.259.08:11:23.37#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.259.08:11:23.37#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.259.08:11:23.37#ibcon#enter wrdev, iclass 29, count 0 2006.259.08:11:23.37#ibcon#first serial, iclass 29, count 0 2006.259.08:11:23.37#ibcon#enter sib2, iclass 29, count 0 2006.259.08:11:23.37#ibcon#flushed, iclass 29, count 0 2006.259.08:11:23.37#ibcon#about to write, iclass 29, count 0 2006.259.08:11:23.37#ibcon#wrote, iclass 29, count 0 2006.259.08:11:23.37#ibcon#about to read 3, iclass 29, count 0 2006.259.08:11:23.39#ibcon#read 3, iclass 29, count 0 2006.259.08:11:23.39#ibcon#about to read 4, iclass 29, count 0 2006.259.08:11:23.39#ibcon#read 4, iclass 29, count 0 2006.259.08:11:23.39#ibcon#about to read 5, iclass 29, count 0 2006.259.08:11:23.39#ibcon#read 5, iclass 29, count 0 2006.259.08:11:23.39#ibcon#about to read 6, iclass 29, count 0 2006.259.08:11:23.39#ibcon#read 6, iclass 29, count 0 2006.259.08:11:23.39#ibcon#end of sib2, iclass 29, count 0 2006.259.08:11:23.39#ibcon#*mode == 0, iclass 29, count 0 2006.259.08:11:23.39#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.259.08:11:23.39#ibcon#[27=BW32\r\n] 2006.259.08:11:23.39#ibcon#*before write, iclass 29, count 0 2006.259.08:11:23.39#ibcon#enter sib2, iclass 29, count 0 2006.259.08:11:23.39#ibcon#flushed, iclass 29, count 0 2006.259.08:11:23.39#ibcon#about to write, iclass 29, count 0 2006.259.08:11:23.39#ibcon#wrote, iclass 29, count 0 2006.259.08:11:23.39#ibcon#about to read 3, iclass 29, count 0 2006.259.08:11:23.42#ibcon#read 3, iclass 29, count 0 2006.259.08:11:23.42#ibcon#about to read 4, iclass 29, count 0 2006.259.08:11:23.42#ibcon#read 4, iclass 29, count 0 2006.259.08:11:23.42#ibcon#about to read 5, iclass 29, count 0 2006.259.08:11:23.42#ibcon#read 5, iclass 29, count 0 2006.259.08:11:23.42#ibcon#about to read 6, iclass 29, count 0 2006.259.08:11:23.42#ibcon#read 6, iclass 29, count 0 2006.259.08:11:23.42#ibcon#end of sib2, iclass 29, count 0 2006.259.08:11:23.42#ibcon#*after write, iclass 29, count 0 2006.259.08:11:23.42#ibcon#*before return 0, iclass 29, count 0 2006.259.08:11:23.42#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.259.08:11:23.42#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.259.08:11:23.42#ibcon#about to clear, iclass 29 cls_cnt 0 2006.259.08:11:23.42#ibcon#cleared, iclass 29 cls_cnt 0 2006.259.08:11:23.42$4f8m12a/ifd4f 2006.259.08:11:23.42$ifd4f/lo= 2006.259.08:11:23.42$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.259.08:11:23.42$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.259.08:11:23.42$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.259.08:11:23.42$ifd4f/patch= 2006.259.08:11:23.42$ifd4f/patch=lo1,a1,a2,a3,a4 2006.259.08:11:23.42$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.259.08:11:23.42$ifd4f/patch=lo3,a5,a6,a7,a8 2006.259.08:11:23.42$4f8m12a/"form=m,16.000,1:2 2006.259.08:11:23.42$4f8m12a/"tpicd 2006.259.08:11:23.42$4f8m12a/echo=off 2006.259.08:11:23.42$4f8m12a/xlog=off 2006.259.08:11:23.42:!2006.259.08:11:50 2006.259.08:11:35.14#trakl#Source acquired 2006.259.08:11:35.14#flagr#flagr/antenna,acquired 2006.259.08:11:50.00:preob 2006.259.08:11:51.14/onsource/TRACKING 2006.259.08:11:51.14:!2006.259.08:12:00 2006.259.08:12:00.00:data_valid=on 2006.259.08:12:00.00:midob 2006.259.08:12:00.14/onsource/TRACKING 2006.259.08:12:00.14/wx/21.97,1013.0,87 2006.259.08:12:00.20/cable/+6.4595E-03 2006.259.08:12:01.29/va/01,08,usb,yes,31,32 2006.259.08:12:01.29/va/02,07,usb,yes,30,32 2006.259.08:12:01.29/va/03,08,usb,yes,23,23 2006.259.08:12:01.29/va/04,07,usb,yes,32,34 2006.259.08:12:01.29/va/05,07,usb,yes,35,37 2006.259.08:12:01.29/va/06,06,usb,yes,34,34 2006.259.08:12:01.29/va/07,06,usb,yes,35,35 2006.259.08:12:01.29/va/08,06,usb,yes,37,37 2006.259.08:12:01.52/valo/01,532.99,yes,locked 2006.259.08:12:01.52/valo/02,572.99,yes,locked 2006.259.08:12:01.52/valo/03,672.99,yes,locked 2006.259.08:12:01.52/valo/04,832.99,yes,locked 2006.259.08:12:01.52/valo/05,652.99,yes,locked 2006.259.08:12:01.52/valo/06,772.99,yes,locked 2006.259.08:12:01.52/valo/07,832.99,yes,locked 2006.259.08:12:01.52/valo/08,852.99,yes,locked 2006.259.08:12:02.61/vb/01,04,usb,yes,30,28 2006.259.08:12:02.61/vb/02,05,usb,yes,28,29 2006.259.08:12:02.61/vb/03,04,usb,yes,28,32 2006.259.08:12:02.61/vb/04,05,usb,yes,25,25 2006.259.08:12:02.61/vb/05,04,usb,yes,27,31 2006.259.08:12:02.61/vb/06,04,usb,yes,28,31 2006.259.08:12:02.61/vb/07,04,usb,yes,30,30 2006.259.08:12:02.61/vb/08,04,usb,yes,28,31 2006.259.08:12:02.85/vblo/01,632.99,yes,locked 2006.259.08:12:02.85/vblo/02,640.99,yes,locked 2006.259.08:12:02.85/vblo/03,656.99,yes,locked 2006.259.08:12:02.85/vblo/04,712.99,yes,locked 2006.259.08:12:02.85/vblo/05,744.99,yes,locked 2006.259.08:12:02.85/vblo/06,752.99,yes,locked 2006.259.08:12:02.85/vblo/07,734.99,yes,locked 2006.259.08:12:02.85/vblo/08,744.99,yes,locked 2006.259.08:12:03.00/vabw/8 2006.259.08:12:03.15/vbbw/8 2006.259.08:12:03.24/xfe/off,on,15.5 2006.259.08:12:03.63/ifatt/23,28,28,28 2006.259.08:12:04.08/fmout-gps/S +4.59E-07 2006.259.08:12:04.12:!2006.259.08:13:00 2006.259.08:13:00.01:data_valid=off 2006.259.08:13:00.01:postob 2006.259.08:13:00.20/cable/+6.4597E-03 2006.259.08:13:00.20/wx/21.96,1013.0,86 2006.259.08:13:01.08/fmout-gps/S +4.61E-07 2006.259.08:13:01.08:scan_name=259-0813,k06259,60 2006.259.08:13:01.09:source=3c371,180650.68,694928.1,2000.0,neutral 2006.259.08:13:01.14#flagr#flagr/antenna,new-source 2006.259.08:13:02.14:checkk5 2006.259.08:13:02.53/chk_autoobs//k5ts1/ autoobs is running! 2006.259.08:13:02.92/chk_autoobs//k5ts2/ autoobs is running! 2006.259.08:13:03.32/chk_autoobs//k5ts3/ autoobs is running! 2006.259.08:13:03.74/chk_autoobs//k5ts4/ autoobs is running! 2006.259.08:13:04.11/chk_obsdata//k5ts1/T2590812??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.259.08:13:04.53/chk_obsdata//k5ts2/T2590812??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.259.08:13:04.94/chk_obsdata//k5ts3/T2590812??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.259.08:13:05.33/chk_obsdata//k5ts4/T2590812??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.259.08:13:06.34/k5log//k5ts1_log_newline 2006.259.08:13:07.12/k5log//k5ts2_log_newline 2006.259.08:13:07.92/k5log//k5ts3_log_newline 2006.259.08:13:08.72/k5log//k5ts4_log_newline 2006.259.08:13:08.75/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.259.08:13:08.75:4f8m12a=2 2006.259.08:13:08.75$4f8m12a/echo=on 2006.259.08:13:08.75$4f8m12a/pcalon 2006.259.08:13:08.75$pcalon/"no phase cal control is implemented here 2006.259.08:13:08.75$4f8m12a/"tpicd=stop 2006.259.08:13:08.75$4f8m12a/vc4f8 2006.259.08:13:08.75$vc4f8/valo=1,532.99 2006.259.08:13:08.76#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.259.08:13:08.76#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.259.08:13:08.76#ibcon#ireg 17 cls_cnt 0 2006.259.08:13:08.76#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.259.08:13:08.76#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.259.08:13:08.76#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.259.08:13:08.76#ibcon#enter wrdev, iclass 36, count 0 2006.259.08:13:08.76#ibcon#first serial, iclass 36, count 0 2006.259.08:13:08.76#ibcon#enter sib2, iclass 36, count 0 2006.259.08:13:08.76#ibcon#flushed, iclass 36, count 0 2006.259.08:13:08.76#ibcon#about to write, iclass 36, count 0 2006.259.08:13:08.76#ibcon#wrote, iclass 36, count 0 2006.259.08:13:08.76#ibcon#about to read 3, iclass 36, count 0 2006.259.08:13:08.80#ibcon#read 3, iclass 36, count 0 2006.259.08:13:08.80#ibcon#about to read 4, iclass 36, count 0 2006.259.08:13:08.80#ibcon#read 4, iclass 36, count 0 2006.259.08:13:08.80#ibcon#about to read 5, iclass 36, count 0 2006.259.08:13:08.80#ibcon#read 5, iclass 36, count 0 2006.259.08:13:08.80#ibcon#about to read 6, iclass 36, count 0 2006.259.08:13:08.80#ibcon#read 6, iclass 36, count 0 2006.259.08:13:08.80#ibcon#end of sib2, iclass 36, count 0 2006.259.08:13:08.80#ibcon#*mode == 0, iclass 36, count 0 2006.259.08:13:08.80#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.259.08:13:08.80#ibcon#[26=FRQ=01,532.99\r\n] 2006.259.08:13:08.80#ibcon#*before write, iclass 36, count 0 2006.259.08:13:08.80#ibcon#enter sib2, iclass 36, count 0 2006.259.08:13:08.80#ibcon#flushed, iclass 36, count 0 2006.259.08:13:08.80#ibcon#about to write, iclass 36, count 0 2006.259.08:13:08.80#ibcon#wrote, iclass 36, count 0 2006.259.08:13:08.80#ibcon#about to read 3, iclass 36, count 0 2006.259.08:13:08.84#ibcon#read 3, iclass 36, count 0 2006.259.08:13:08.84#ibcon#about to read 4, iclass 36, count 0 2006.259.08:13:08.84#ibcon#read 4, iclass 36, count 0 2006.259.08:13:08.84#ibcon#about to read 5, iclass 36, count 0 2006.259.08:13:08.84#ibcon#read 5, iclass 36, count 0 2006.259.08:13:08.84#ibcon#about to read 6, iclass 36, count 0 2006.259.08:13:08.84#ibcon#read 6, iclass 36, count 0 2006.259.08:13:08.84#ibcon#end of sib2, iclass 36, count 0 2006.259.08:13:08.84#ibcon#*after write, iclass 36, count 0 2006.259.08:13:08.84#ibcon#*before return 0, iclass 36, count 0 2006.259.08:13:08.84#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.259.08:13:08.84#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.259.08:13:08.84#ibcon#about to clear, iclass 36 cls_cnt 0 2006.259.08:13:08.84#ibcon#cleared, iclass 36 cls_cnt 0 2006.259.08:13:08.84$vc4f8/va=1,8 2006.259.08:13:08.84#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.259.08:13:08.84#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.259.08:13:08.84#ibcon#ireg 11 cls_cnt 2 2006.259.08:13:08.84#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.259.08:13:08.84#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.259.08:13:08.84#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.259.08:13:08.84#ibcon#enter wrdev, iclass 38, count 2 2006.259.08:13:08.84#ibcon#first serial, iclass 38, count 2 2006.259.08:13:08.84#ibcon#enter sib2, iclass 38, count 2 2006.259.08:13:08.84#ibcon#flushed, iclass 38, count 2 2006.259.08:13:08.84#ibcon#about to write, iclass 38, count 2 2006.259.08:13:08.84#ibcon#wrote, iclass 38, count 2 2006.259.08:13:08.84#ibcon#about to read 3, iclass 38, count 2 2006.259.08:13:08.86#ibcon#read 3, iclass 38, count 2 2006.259.08:13:08.86#ibcon#about to read 4, iclass 38, count 2 2006.259.08:13:08.86#ibcon#read 4, iclass 38, count 2 2006.259.08:13:08.86#ibcon#about to read 5, iclass 38, count 2 2006.259.08:13:08.86#ibcon#read 5, iclass 38, count 2 2006.259.08:13:08.86#ibcon#about to read 6, iclass 38, count 2 2006.259.08:13:08.86#ibcon#read 6, iclass 38, count 2 2006.259.08:13:08.86#ibcon#end of sib2, iclass 38, count 2 2006.259.08:13:08.86#ibcon#*mode == 0, iclass 38, count 2 2006.259.08:13:08.86#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.259.08:13:08.86#ibcon#[25=AT01-08\r\n] 2006.259.08:13:08.86#ibcon#*before write, iclass 38, count 2 2006.259.08:13:08.86#ibcon#enter sib2, iclass 38, count 2 2006.259.08:13:08.86#ibcon#flushed, iclass 38, count 2 2006.259.08:13:08.86#ibcon#about to write, iclass 38, count 2 2006.259.08:13:08.86#ibcon#wrote, iclass 38, count 2 2006.259.08:13:08.86#ibcon#about to read 3, iclass 38, count 2 2006.259.08:13:08.89#ibcon#read 3, iclass 38, count 2 2006.259.08:13:08.89#ibcon#about to read 4, iclass 38, count 2 2006.259.08:13:08.89#ibcon#read 4, iclass 38, count 2 2006.259.08:13:08.89#ibcon#about to read 5, iclass 38, count 2 2006.259.08:13:08.89#ibcon#read 5, iclass 38, count 2 2006.259.08:13:08.89#ibcon#about to read 6, iclass 38, count 2 2006.259.08:13:08.89#ibcon#read 6, iclass 38, count 2 2006.259.08:13:08.89#ibcon#end of sib2, iclass 38, count 2 2006.259.08:13:08.89#ibcon#*after write, iclass 38, count 2 2006.259.08:13:08.89#ibcon#*before return 0, iclass 38, count 2 2006.259.08:13:08.89#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.259.08:13:08.89#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.259.08:13:08.89#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.259.08:13:08.89#ibcon#ireg 7 cls_cnt 0 2006.259.08:13:08.89#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.259.08:13:09.01#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.259.08:13:09.01#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.259.08:13:09.01#ibcon#enter wrdev, iclass 38, count 0 2006.259.08:13:09.01#ibcon#first serial, iclass 38, count 0 2006.259.08:13:09.01#ibcon#enter sib2, iclass 38, count 0 2006.259.08:13:09.01#ibcon#flushed, iclass 38, count 0 2006.259.08:13:09.01#ibcon#about to write, iclass 38, count 0 2006.259.08:13:09.01#ibcon#wrote, iclass 38, count 0 2006.259.08:13:09.01#ibcon#about to read 3, iclass 38, count 0 2006.259.08:13:09.03#ibcon#read 3, iclass 38, count 0 2006.259.08:13:09.03#ibcon#about to read 4, iclass 38, count 0 2006.259.08:13:09.03#ibcon#read 4, iclass 38, count 0 2006.259.08:13:09.03#ibcon#about to read 5, iclass 38, count 0 2006.259.08:13:09.03#ibcon#read 5, iclass 38, count 0 2006.259.08:13:09.03#ibcon#about to read 6, iclass 38, count 0 2006.259.08:13:09.03#ibcon#read 6, iclass 38, count 0 2006.259.08:13:09.03#ibcon#end of sib2, iclass 38, count 0 2006.259.08:13:09.03#ibcon#*mode == 0, iclass 38, count 0 2006.259.08:13:09.03#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.259.08:13:09.03#ibcon#[25=USB\r\n] 2006.259.08:13:09.03#ibcon#*before write, iclass 38, count 0 2006.259.08:13:09.03#ibcon#enter sib2, iclass 38, count 0 2006.259.08:13:09.03#ibcon#flushed, iclass 38, count 0 2006.259.08:13:09.03#ibcon#about to write, iclass 38, count 0 2006.259.08:13:09.03#ibcon#wrote, iclass 38, count 0 2006.259.08:13:09.03#ibcon#about to read 3, iclass 38, count 0 2006.259.08:13:09.06#ibcon#read 3, iclass 38, count 0 2006.259.08:13:09.06#ibcon#about to read 4, iclass 38, count 0 2006.259.08:13:09.06#ibcon#read 4, iclass 38, count 0 2006.259.08:13:09.06#ibcon#about to read 5, iclass 38, count 0 2006.259.08:13:09.06#ibcon#read 5, iclass 38, count 0 2006.259.08:13:09.06#ibcon#about to read 6, iclass 38, count 0 2006.259.08:13:09.06#ibcon#read 6, iclass 38, count 0 2006.259.08:13:09.06#ibcon#end of sib2, iclass 38, count 0 2006.259.08:13:09.06#ibcon#*after write, iclass 38, count 0 2006.259.08:13:09.06#ibcon#*before return 0, iclass 38, count 0 2006.259.08:13:09.06#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.259.08:13:09.06#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.259.08:13:09.06#ibcon#about to clear, iclass 38 cls_cnt 0 2006.259.08:13:09.06#ibcon#cleared, iclass 38 cls_cnt 0 2006.259.08:13:09.06$vc4f8/valo=2,572.99 2006.259.08:13:09.06#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.259.08:13:09.06#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.259.08:13:09.06#ibcon#ireg 17 cls_cnt 0 2006.259.08:13:09.06#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.259.08:13:09.06#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.259.08:13:09.06#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.259.08:13:09.06#ibcon#enter wrdev, iclass 40, count 0 2006.259.08:13:09.06#ibcon#first serial, iclass 40, count 0 2006.259.08:13:09.06#ibcon#enter sib2, iclass 40, count 0 2006.259.08:13:09.06#ibcon#flushed, iclass 40, count 0 2006.259.08:13:09.06#ibcon#about to write, iclass 40, count 0 2006.259.08:13:09.06#ibcon#wrote, iclass 40, count 0 2006.259.08:13:09.06#ibcon#about to read 3, iclass 40, count 0 2006.259.08:13:09.08#ibcon#read 3, iclass 40, count 0 2006.259.08:13:09.08#ibcon#about to read 4, iclass 40, count 0 2006.259.08:13:09.08#ibcon#read 4, iclass 40, count 0 2006.259.08:13:09.08#ibcon#about to read 5, iclass 40, count 0 2006.259.08:13:09.08#ibcon#read 5, iclass 40, count 0 2006.259.08:13:09.08#ibcon#about to read 6, iclass 40, count 0 2006.259.08:13:09.08#ibcon#read 6, iclass 40, count 0 2006.259.08:13:09.08#ibcon#end of sib2, iclass 40, count 0 2006.259.08:13:09.08#ibcon#*mode == 0, iclass 40, count 0 2006.259.08:13:09.08#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.259.08:13:09.08#ibcon#[26=FRQ=02,572.99\r\n] 2006.259.08:13:09.08#ibcon#*before write, iclass 40, count 0 2006.259.08:13:09.08#ibcon#enter sib2, iclass 40, count 0 2006.259.08:13:09.08#ibcon#flushed, iclass 40, count 0 2006.259.08:13:09.08#ibcon#about to write, iclass 40, count 0 2006.259.08:13:09.08#ibcon#wrote, iclass 40, count 0 2006.259.08:13:09.08#ibcon#about to read 3, iclass 40, count 0 2006.259.08:13:09.12#ibcon#read 3, iclass 40, count 0 2006.259.08:13:09.12#ibcon#about to read 4, iclass 40, count 0 2006.259.08:13:09.12#ibcon#read 4, iclass 40, count 0 2006.259.08:13:09.12#ibcon#about to read 5, iclass 40, count 0 2006.259.08:13:09.12#ibcon#read 5, iclass 40, count 0 2006.259.08:13:09.12#ibcon#about to read 6, iclass 40, count 0 2006.259.08:13:09.12#ibcon#read 6, iclass 40, count 0 2006.259.08:13:09.12#ibcon#end of sib2, iclass 40, count 0 2006.259.08:13:09.12#ibcon#*after write, iclass 40, count 0 2006.259.08:13:09.12#ibcon#*before return 0, iclass 40, count 0 2006.259.08:13:09.12#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.259.08:13:09.12#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.259.08:13:09.12#ibcon#about to clear, iclass 40 cls_cnt 0 2006.259.08:13:09.12#ibcon#cleared, iclass 40 cls_cnt 0 2006.259.08:13:09.12$vc4f8/va=2,7 2006.259.08:13:09.12#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.259.08:13:09.12#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.259.08:13:09.12#ibcon#ireg 11 cls_cnt 2 2006.259.08:13:09.12#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.259.08:13:09.18#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.259.08:13:09.18#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.259.08:13:09.18#ibcon#enter wrdev, iclass 4, count 2 2006.259.08:13:09.18#ibcon#first serial, iclass 4, count 2 2006.259.08:13:09.18#ibcon#enter sib2, iclass 4, count 2 2006.259.08:13:09.18#ibcon#flushed, iclass 4, count 2 2006.259.08:13:09.18#ibcon#about to write, iclass 4, count 2 2006.259.08:13:09.18#ibcon#wrote, iclass 4, count 2 2006.259.08:13:09.18#ibcon#about to read 3, iclass 4, count 2 2006.259.08:13:09.20#ibcon#read 3, iclass 4, count 2 2006.259.08:13:09.20#ibcon#about to read 4, iclass 4, count 2 2006.259.08:13:09.20#ibcon#read 4, iclass 4, count 2 2006.259.08:13:09.20#ibcon#about to read 5, iclass 4, count 2 2006.259.08:13:09.20#ibcon#read 5, iclass 4, count 2 2006.259.08:13:09.20#ibcon#about to read 6, iclass 4, count 2 2006.259.08:13:09.20#ibcon#read 6, iclass 4, count 2 2006.259.08:13:09.20#ibcon#end of sib2, iclass 4, count 2 2006.259.08:13:09.20#ibcon#*mode == 0, iclass 4, count 2 2006.259.08:13:09.20#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.259.08:13:09.20#ibcon#[25=AT02-07\r\n] 2006.259.08:13:09.20#ibcon#*before write, iclass 4, count 2 2006.259.08:13:09.20#ibcon#enter sib2, iclass 4, count 2 2006.259.08:13:09.20#ibcon#flushed, iclass 4, count 2 2006.259.08:13:09.20#ibcon#about to write, iclass 4, count 2 2006.259.08:13:09.20#ibcon#wrote, iclass 4, count 2 2006.259.08:13:09.20#ibcon#about to read 3, iclass 4, count 2 2006.259.08:13:09.23#ibcon#read 3, iclass 4, count 2 2006.259.08:13:09.23#ibcon#about to read 4, iclass 4, count 2 2006.259.08:13:09.23#ibcon#read 4, iclass 4, count 2 2006.259.08:13:09.23#ibcon#about to read 5, iclass 4, count 2 2006.259.08:13:09.23#ibcon#read 5, iclass 4, count 2 2006.259.08:13:09.23#ibcon#about to read 6, iclass 4, count 2 2006.259.08:13:09.23#ibcon#read 6, iclass 4, count 2 2006.259.08:13:09.23#ibcon#end of sib2, iclass 4, count 2 2006.259.08:13:09.23#ibcon#*after write, iclass 4, count 2 2006.259.08:13:09.23#ibcon#*before return 0, iclass 4, count 2 2006.259.08:13:09.23#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.259.08:13:09.23#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.259.08:13:09.23#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.259.08:13:09.23#ibcon#ireg 7 cls_cnt 0 2006.259.08:13:09.23#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.259.08:13:09.35#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.259.08:13:09.35#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.259.08:13:09.35#ibcon#enter wrdev, iclass 4, count 0 2006.259.08:13:09.35#ibcon#first serial, iclass 4, count 0 2006.259.08:13:09.35#ibcon#enter sib2, iclass 4, count 0 2006.259.08:13:09.35#ibcon#flushed, iclass 4, count 0 2006.259.08:13:09.35#ibcon#about to write, iclass 4, count 0 2006.259.08:13:09.35#ibcon#wrote, iclass 4, count 0 2006.259.08:13:09.35#ibcon#about to read 3, iclass 4, count 0 2006.259.08:13:09.37#ibcon#read 3, iclass 4, count 0 2006.259.08:13:09.37#ibcon#about to read 4, iclass 4, count 0 2006.259.08:13:09.37#ibcon#read 4, iclass 4, count 0 2006.259.08:13:09.37#ibcon#about to read 5, iclass 4, count 0 2006.259.08:13:09.37#ibcon#read 5, iclass 4, count 0 2006.259.08:13:09.37#ibcon#about to read 6, iclass 4, count 0 2006.259.08:13:09.37#ibcon#read 6, iclass 4, count 0 2006.259.08:13:09.37#ibcon#end of sib2, iclass 4, count 0 2006.259.08:13:09.37#ibcon#*mode == 0, iclass 4, count 0 2006.259.08:13:09.37#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.259.08:13:09.37#ibcon#[25=USB\r\n] 2006.259.08:13:09.37#ibcon#*before write, iclass 4, count 0 2006.259.08:13:09.37#ibcon#enter sib2, iclass 4, count 0 2006.259.08:13:09.37#ibcon#flushed, iclass 4, count 0 2006.259.08:13:09.37#ibcon#about to write, iclass 4, count 0 2006.259.08:13:09.37#ibcon#wrote, iclass 4, count 0 2006.259.08:13:09.37#ibcon#about to read 3, iclass 4, count 0 2006.259.08:13:09.40#ibcon#read 3, iclass 4, count 0 2006.259.08:13:09.40#ibcon#about to read 4, iclass 4, count 0 2006.259.08:13:09.40#ibcon#read 4, iclass 4, count 0 2006.259.08:13:09.40#ibcon#about to read 5, iclass 4, count 0 2006.259.08:13:09.40#ibcon#read 5, iclass 4, count 0 2006.259.08:13:09.40#ibcon#about to read 6, iclass 4, count 0 2006.259.08:13:09.40#ibcon#read 6, iclass 4, count 0 2006.259.08:13:09.40#ibcon#end of sib2, iclass 4, count 0 2006.259.08:13:09.40#ibcon#*after write, iclass 4, count 0 2006.259.08:13:09.40#ibcon#*before return 0, iclass 4, count 0 2006.259.08:13:09.40#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.259.08:13:09.40#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.259.08:13:09.40#ibcon#about to clear, iclass 4 cls_cnt 0 2006.259.08:13:09.40#ibcon#cleared, iclass 4 cls_cnt 0 2006.259.08:13:09.40$vc4f8/valo=3,672.99 2006.259.08:13:09.40#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.259.08:13:09.40#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.259.08:13:09.40#ibcon#ireg 17 cls_cnt 0 2006.259.08:13:09.40#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.259.08:13:09.40#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.259.08:13:09.40#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.259.08:13:09.40#ibcon#enter wrdev, iclass 6, count 0 2006.259.08:13:09.40#ibcon#first serial, iclass 6, count 0 2006.259.08:13:09.40#ibcon#enter sib2, iclass 6, count 0 2006.259.08:13:09.40#ibcon#flushed, iclass 6, count 0 2006.259.08:13:09.40#ibcon#about to write, iclass 6, count 0 2006.259.08:13:09.40#ibcon#wrote, iclass 6, count 0 2006.259.08:13:09.40#ibcon#about to read 3, iclass 6, count 0 2006.259.08:13:09.42#ibcon#read 3, iclass 6, count 0 2006.259.08:13:09.42#ibcon#about to read 4, iclass 6, count 0 2006.259.08:13:09.42#ibcon#read 4, iclass 6, count 0 2006.259.08:13:09.42#ibcon#about to read 5, iclass 6, count 0 2006.259.08:13:09.42#ibcon#read 5, iclass 6, count 0 2006.259.08:13:09.42#ibcon#about to read 6, iclass 6, count 0 2006.259.08:13:09.42#ibcon#read 6, iclass 6, count 0 2006.259.08:13:09.42#ibcon#end of sib2, iclass 6, count 0 2006.259.08:13:09.42#ibcon#*mode == 0, iclass 6, count 0 2006.259.08:13:09.42#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.259.08:13:09.42#ibcon#[26=FRQ=03,672.99\r\n] 2006.259.08:13:09.42#ibcon#*before write, iclass 6, count 0 2006.259.08:13:09.42#ibcon#enter sib2, iclass 6, count 0 2006.259.08:13:09.42#ibcon#flushed, iclass 6, count 0 2006.259.08:13:09.42#ibcon#about to write, iclass 6, count 0 2006.259.08:13:09.42#ibcon#wrote, iclass 6, count 0 2006.259.08:13:09.42#ibcon#about to read 3, iclass 6, count 0 2006.259.08:13:09.46#ibcon#read 3, iclass 6, count 0 2006.259.08:13:09.46#ibcon#about to read 4, iclass 6, count 0 2006.259.08:13:09.46#ibcon#read 4, iclass 6, count 0 2006.259.08:13:09.46#ibcon#about to read 5, iclass 6, count 0 2006.259.08:13:09.46#ibcon#read 5, iclass 6, count 0 2006.259.08:13:09.46#ibcon#about to read 6, iclass 6, count 0 2006.259.08:13:09.46#ibcon#read 6, iclass 6, count 0 2006.259.08:13:09.46#ibcon#end of sib2, iclass 6, count 0 2006.259.08:13:09.46#ibcon#*after write, iclass 6, count 0 2006.259.08:13:09.46#ibcon#*before return 0, iclass 6, count 0 2006.259.08:13:09.46#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.259.08:13:09.46#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.259.08:13:09.46#ibcon#about to clear, iclass 6 cls_cnt 0 2006.259.08:13:09.46#ibcon#cleared, iclass 6 cls_cnt 0 2006.259.08:13:09.46$vc4f8/va=3,8 2006.259.08:13:09.46#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.259.08:13:09.46#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.259.08:13:09.46#ibcon#ireg 11 cls_cnt 2 2006.259.08:13:09.46#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.259.08:13:09.53#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.259.08:13:09.53#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.259.08:13:09.53#ibcon#enter wrdev, iclass 10, count 2 2006.259.08:13:09.53#ibcon#first serial, iclass 10, count 2 2006.259.08:13:09.53#ibcon#enter sib2, iclass 10, count 2 2006.259.08:13:09.53#ibcon#flushed, iclass 10, count 2 2006.259.08:13:09.53#ibcon#about to write, iclass 10, count 2 2006.259.08:13:09.53#ibcon#wrote, iclass 10, count 2 2006.259.08:13:09.53#ibcon#about to read 3, iclass 10, count 2 2006.259.08:13:09.54#ibcon#read 3, iclass 10, count 2 2006.259.08:13:09.54#ibcon#about to read 4, iclass 10, count 2 2006.259.08:13:09.54#ibcon#read 4, iclass 10, count 2 2006.259.08:13:09.54#ibcon#about to read 5, iclass 10, count 2 2006.259.08:13:09.54#ibcon#read 5, iclass 10, count 2 2006.259.08:13:09.54#ibcon#about to read 6, iclass 10, count 2 2006.259.08:13:09.54#ibcon#read 6, iclass 10, count 2 2006.259.08:13:09.54#ibcon#end of sib2, iclass 10, count 2 2006.259.08:13:09.54#ibcon#*mode == 0, iclass 10, count 2 2006.259.08:13:09.54#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.259.08:13:09.54#ibcon#[25=AT03-08\r\n] 2006.259.08:13:09.54#ibcon#*before write, iclass 10, count 2 2006.259.08:13:09.54#ibcon#enter sib2, iclass 10, count 2 2006.259.08:13:09.54#ibcon#flushed, iclass 10, count 2 2006.259.08:13:09.54#ibcon#about to write, iclass 10, count 2 2006.259.08:13:09.54#ibcon#wrote, iclass 10, count 2 2006.259.08:13:09.54#ibcon#about to read 3, iclass 10, count 2 2006.259.08:13:09.57#ibcon#read 3, iclass 10, count 2 2006.259.08:13:09.57#ibcon#about to read 4, iclass 10, count 2 2006.259.08:13:09.57#ibcon#read 4, iclass 10, count 2 2006.259.08:13:09.57#ibcon#about to read 5, iclass 10, count 2 2006.259.08:13:09.57#ibcon#read 5, iclass 10, count 2 2006.259.08:13:09.57#ibcon#about to read 6, iclass 10, count 2 2006.259.08:13:09.57#ibcon#read 6, iclass 10, count 2 2006.259.08:13:09.57#ibcon#end of sib2, iclass 10, count 2 2006.259.08:13:09.57#ibcon#*after write, iclass 10, count 2 2006.259.08:13:09.57#ibcon#*before return 0, iclass 10, count 2 2006.259.08:13:09.57#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.259.08:13:09.57#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.259.08:13:09.57#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.259.08:13:09.57#ibcon#ireg 7 cls_cnt 0 2006.259.08:13:09.57#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.259.08:13:09.69#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.259.08:13:09.69#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.259.08:13:09.69#ibcon#enter wrdev, iclass 10, count 0 2006.259.08:13:09.69#ibcon#first serial, iclass 10, count 0 2006.259.08:13:09.69#ibcon#enter sib2, iclass 10, count 0 2006.259.08:13:09.69#ibcon#flushed, iclass 10, count 0 2006.259.08:13:09.69#ibcon#about to write, iclass 10, count 0 2006.259.08:13:09.69#ibcon#wrote, iclass 10, count 0 2006.259.08:13:09.69#ibcon#about to read 3, iclass 10, count 0 2006.259.08:13:09.71#ibcon#read 3, iclass 10, count 0 2006.259.08:13:09.71#ibcon#about to read 4, iclass 10, count 0 2006.259.08:13:09.71#ibcon#read 4, iclass 10, count 0 2006.259.08:13:09.71#ibcon#about to read 5, iclass 10, count 0 2006.259.08:13:09.71#ibcon#read 5, iclass 10, count 0 2006.259.08:13:09.71#ibcon#about to read 6, iclass 10, count 0 2006.259.08:13:09.71#ibcon#read 6, iclass 10, count 0 2006.259.08:13:09.71#ibcon#end of sib2, iclass 10, count 0 2006.259.08:13:09.71#ibcon#*mode == 0, iclass 10, count 0 2006.259.08:13:09.71#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.259.08:13:09.71#ibcon#[25=USB\r\n] 2006.259.08:13:09.71#ibcon#*before write, iclass 10, count 0 2006.259.08:13:09.71#ibcon#enter sib2, iclass 10, count 0 2006.259.08:13:09.71#ibcon#flushed, iclass 10, count 0 2006.259.08:13:09.71#ibcon#about to write, iclass 10, count 0 2006.259.08:13:09.71#ibcon#wrote, iclass 10, count 0 2006.259.08:13:09.71#ibcon#about to read 3, iclass 10, count 0 2006.259.08:13:09.74#ibcon#read 3, iclass 10, count 0 2006.259.08:13:09.74#ibcon#about to read 4, iclass 10, count 0 2006.259.08:13:09.74#ibcon#read 4, iclass 10, count 0 2006.259.08:13:09.74#ibcon#about to read 5, iclass 10, count 0 2006.259.08:13:09.74#ibcon#read 5, iclass 10, count 0 2006.259.08:13:09.74#ibcon#about to read 6, iclass 10, count 0 2006.259.08:13:09.74#ibcon#read 6, iclass 10, count 0 2006.259.08:13:09.74#ibcon#end of sib2, iclass 10, count 0 2006.259.08:13:09.74#ibcon#*after write, iclass 10, count 0 2006.259.08:13:09.74#ibcon#*before return 0, iclass 10, count 0 2006.259.08:13:09.74#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.259.08:13:09.74#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.259.08:13:09.74#ibcon#about to clear, iclass 10 cls_cnt 0 2006.259.08:13:09.74#ibcon#cleared, iclass 10 cls_cnt 0 2006.259.08:13:09.74$vc4f8/valo=4,832.99 2006.259.08:13:09.74#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.259.08:13:09.74#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.259.08:13:09.74#ibcon#ireg 17 cls_cnt 0 2006.259.08:13:09.74#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.259.08:13:09.74#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.259.08:13:09.74#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.259.08:13:09.74#ibcon#enter wrdev, iclass 12, count 0 2006.259.08:13:09.74#ibcon#first serial, iclass 12, count 0 2006.259.08:13:09.74#ibcon#enter sib2, iclass 12, count 0 2006.259.08:13:09.74#ibcon#flushed, iclass 12, count 0 2006.259.08:13:09.74#ibcon#about to write, iclass 12, count 0 2006.259.08:13:09.74#ibcon#wrote, iclass 12, count 0 2006.259.08:13:09.74#ibcon#about to read 3, iclass 12, count 0 2006.259.08:13:09.76#ibcon#read 3, iclass 12, count 0 2006.259.08:13:09.76#ibcon#about to read 4, iclass 12, count 0 2006.259.08:13:09.76#ibcon#read 4, iclass 12, count 0 2006.259.08:13:09.76#ibcon#about to read 5, iclass 12, count 0 2006.259.08:13:09.76#ibcon#read 5, iclass 12, count 0 2006.259.08:13:09.76#ibcon#about to read 6, iclass 12, count 0 2006.259.08:13:09.76#ibcon#read 6, iclass 12, count 0 2006.259.08:13:09.76#ibcon#end of sib2, iclass 12, count 0 2006.259.08:13:09.76#ibcon#*mode == 0, iclass 12, count 0 2006.259.08:13:09.76#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.259.08:13:09.76#ibcon#[26=FRQ=04,832.99\r\n] 2006.259.08:13:09.76#ibcon#*before write, iclass 12, count 0 2006.259.08:13:09.76#ibcon#enter sib2, iclass 12, count 0 2006.259.08:13:09.76#ibcon#flushed, iclass 12, count 0 2006.259.08:13:09.76#ibcon#about to write, iclass 12, count 0 2006.259.08:13:09.76#ibcon#wrote, iclass 12, count 0 2006.259.08:13:09.76#ibcon#about to read 3, iclass 12, count 0 2006.259.08:13:09.80#ibcon#read 3, iclass 12, count 0 2006.259.08:13:09.80#ibcon#about to read 4, iclass 12, count 0 2006.259.08:13:09.80#ibcon#read 4, iclass 12, count 0 2006.259.08:13:09.80#ibcon#about to read 5, iclass 12, count 0 2006.259.08:13:09.80#ibcon#read 5, iclass 12, count 0 2006.259.08:13:09.80#ibcon#about to read 6, iclass 12, count 0 2006.259.08:13:09.80#ibcon#read 6, iclass 12, count 0 2006.259.08:13:09.80#ibcon#end of sib2, iclass 12, count 0 2006.259.08:13:09.80#ibcon#*after write, iclass 12, count 0 2006.259.08:13:09.80#ibcon#*before return 0, iclass 12, count 0 2006.259.08:13:09.80#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.259.08:13:09.80#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.259.08:13:09.80#ibcon#about to clear, iclass 12 cls_cnt 0 2006.259.08:13:09.80#ibcon#cleared, iclass 12 cls_cnt 0 2006.259.08:13:09.80$vc4f8/va=4,7 2006.259.08:13:09.80#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.259.08:13:09.80#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.259.08:13:09.80#ibcon#ireg 11 cls_cnt 2 2006.259.08:13:09.80#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.259.08:13:09.86#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.259.08:13:09.86#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.259.08:13:09.86#ibcon#enter wrdev, iclass 14, count 2 2006.259.08:13:09.86#ibcon#first serial, iclass 14, count 2 2006.259.08:13:09.86#ibcon#enter sib2, iclass 14, count 2 2006.259.08:13:09.86#ibcon#flushed, iclass 14, count 2 2006.259.08:13:09.86#ibcon#about to write, iclass 14, count 2 2006.259.08:13:09.86#ibcon#wrote, iclass 14, count 2 2006.259.08:13:09.86#ibcon#about to read 3, iclass 14, count 2 2006.259.08:13:09.88#ibcon#read 3, iclass 14, count 2 2006.259.08:13:09.88#ibcon#about to read 4, iclass 14, count 2 2006.259.08:13:09.88#ibcon#read 4, iclass 14, count 2 2006.259.08:13:09.88#ibcon#about to read 5, iclass 14, count 2 2006.259.08:13:09.88#ibcon#read 5, iclass 14, count 2 2006.259.08:13:09.88#ibcon#about to read 6, iclass 14, count 2 2006.259.08:13:09.88#ibcon#read 6, iclass 14, count 2 2006.259.08:13:09.88#ibcon#end of sib2, iclass 14, count 2 2006.259.08:13:09.88#ibcon#*mode == 0, iclass 14, count 2 2006.259.08:13:09.88#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.259.08:13:09.88#ibcon#[25=AT04-07\r\n] 2006.259.08:13:09.88#ibcon#*before write, iclass 14, count 2 2006.259.08:13:09.88#ibcon#enter sib2, iclass 14, count 2 2006.259.08:13:09.88#ibcon#flushed, iclass 14, count 2 2006.259.08:13:09.88#ibcon#about to write, iclass 14, count 2 2006.259.08:13:09.88#ibcon#wrote, iclass 14, count 2 2006.259.08:13:09.88#ibcon#about to read 3, iclass 14, count 2 2006.259.08:13:09.91#ibcon#read 3, iclass 14, count 2 2006.259.08:13:09.91#ibcon#about to read 4, iclass 14, count 2 2006.259.08:13:09.91#ibcon#read 4, iclass 14, count 2 2006.259.08:13:09.91#ibcon#about to read 5, iclass 14, count 2 2006.259.08:13:09.91#ibcon#read 5, iclass 14, count 2 2006.259.08:13:09.91#ibcon#about to read 6, iclass 14, count 2 2006.259.08:13:09.91#ibcon#read 6, iclass 14, count 2 2006.259.08:13:09.91#ibcon#end of sib2, iclass 14, count 2 2006.259.08:13:09.91#ibcon#*after write, iclass 14, count 2 2006.259.08:13:09.91#ibcon#*before return 0, iclass 14, count 2 2006.259.08:13:09.91#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.259.08:13:09.91#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.259.08:13:09.91#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.259.08:13:09.91#ibcon#ireg 7 cls_cnt 0 2006.259.08:13:09.91#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.259.08:13:10.03#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.259.08:13:10.03#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.259.08:13:10.03#ibcon#enter wrdev, iclass 14, count 0 2006.259.08:13:10.03#ibcon#first serial, iclass 14, count 0 2006.259.08:13:10.03#ibcon#enter sib2, iclass 14, count 0 2006.259.08:13:10.03#ibcon#flushed, iclass 14, count 0 2006.259.08:13:10.03#ibcon#about to write, iclass 14, count 0 2006.259.08:13:10.03#ibcon#wrote, iclass 14, count 0 2006.259.08:13:10.03#ibcon#about to read 3, iclass 14, count 0 2006.259.08:13:10.05#ibcon#read 3, iclass 14, count 0 2006.259.08:13:10.05#ibcon#about to read 4, iclass 14, count 0 2006.259.08:13:10.05#ibcon#read 4, iclass 14, count 0 2006.259.08:13:10.05#ibcon#about to read 5, iclass 14, count 0 2006.259.08:13:10.05#ibcon#read 5, iclass 14, count 0 2006.259.08:13:10.05#ibcon#about to read 6, iclass 14, count 0 2006.259.08:13:10.05#ibcon#read 6, iclass 14, count 0 2006.259.08:13:10.05#ibcon#end of sib2, iclass 14, count 0 2006.259.08:13:10.05#ibcon#*mode == 0, iclass 14, count 0 2006.259.08:13:10.05#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.259.08:13:10.05#ibcon#[25=USB\r\n] 2006.259.08:13:10.05#ibcon#*before write, iclass 14, count 0 2006.259.08:13:10.05#ibcon#enter sib2, iclass 14, count 0 2006.259.08:13:10.05#ibcon#flushed, iclass 14, count 0 2006.259.08:13:10.05#ibcon#about to write, iclass 14, count 0 2006.259.08:13:10.05#ibcon#wrote, iclass 14, count 0 2006.259.08:13:10.05#ibcon#about to read 3, iclass 14, count 0 2006.259.08:13:10.08#ibcon#read 3, iclass 14, count 0 2006.259.08:13:10.08#ibcon#about to read 4, iclass 14, count 0 2006.259.08:13:10.08#ibcon#read 4, iclass 14, count 0 2006.259.08:13:10.08#ibcon#about to read 5, iclass 14, count 0 2006.259.08:13:10.08#ibcon#read 5, iclass 14, count 0 2006.259.08:13:10.08#ibcon#about to read 6, iclass 14, count 0 2006.259.08:13:10.08#ibcon#read 6, iclass 14, count 0 2006.259.08:13:10.08#ibcon#end of sib2, iclass 14, count 0 2006.259.08:13:10.08#ibcon#*after write, iclass 14, count 0 2006.259.08:13:10.08#ibcon#*before return 0, iclass 14, count 0 2006.259.08:13:10.08#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.259.08:13:10.08#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.259.08:13:10.08#ibcon#about to clear, iclass 14 cls_cnt 0 2006.259.08:13:10.08#ibcon#cleared, iclass 14 cls_cnt 0 2006.259.08:13:10.08$vc4f8/valo=5,652.99 2006.259.08:13:10.08#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.259.08:13:10.08#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.259.08:13:10.08#ibcon#ireg 17 cls_cnt 0 2006.259.08:13:10.08#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.259.08:13:10.08#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.259.08:13:10.08#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.259.08:13:10.08#ibcon#enter wrdev, iclass 16, count 0 2006.259.08:13:10.08#ibcon#first serial, iclass 16, count 0 2006.259.08:13:10.08#ibcon#enter sib2, iclass 16, count 0 2006.259.08:13:10.08#ibcon#flushed, iclass 16, count 0 2006.259.08:13:10.08#ibcon#about to write, iclass 16, count 0 2006.259.08:13:10.08#ibcon#wrote, iclass 16, count 0 2006.259.08:13:10.08#ibcon#about to read 3, iclass 16, count 0 2006.259.08:13:10.10#ibcon#read 3, iclass 16, count 0 2006.259.08:13:10.10#ibcon#about to read 4, iclass 16, count 0 2006.259.08:13:10.10#ibcon#read 4, iclass 16, count 0 2006.259.08:13:10.10#ibcon#about to read 5, iclass 16, count 0 2006.259.08:13:10.10#ibcon#read 5, iclass 16, count 0 2006.259.08:13:10.10#ibcon#about to read 6, iclass 16, count 0 2006.259.08:13:10.10#ibcon#read 6, iclass 16, count 0 2006.259.08:13:10.10#ibcon#end of sib2, iclass 16, count 0 2006.259.08:13:10.10#ibcon#*mode == 0, iclass 16, count 0 2006.259.08:13:10.10#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.259.08:13:10.10#ibcon#[26=FRQ=05,652.99\r\n] 2006.259.08:13:10.10#ibcon#*before write, iclass 16, count 0 2006.259.08:13:10.10#ibcon#enter sib2, iclass 16, count 0 2006.259.08:13:10.10#ibcon#flushed, iclass 16, count 0 2006.259.08:13:10.10#ibcon#about to write, iclass 16, count 0 2006.259.08:13:10.10#ibcon#wrote, iclass 16, count 0 2006.259.08:13:10.10#ibcon#about to read 3, iclass 16, count 0 2006.259.08:13:10.14#ibcon#read 3, iclass 16, count 0 2006.259.08:13:10.14#ibcon#about to read 4, iclass 16, count 0 2006.259.08:13:10.14#ibcon#read 4, iclass 16, count 0 2006.259.08:13:10.14#ibcon#about to read 5, iclass 16, count 0 2006.259.08:13:10.14#ibcon#read 5, iclass 16, count 0 2006.259.08:13:10.14#ibcon#about to read 6, iclass 16, count 0 2006.259.08:13:10.14#ibcon#read 6, iclass 16, count 0 2006.259.08:13:10.14#ibcon#end of sib2, iclass 16, count 0 2006.259.08:13:10.14#ibcon#*after write, iclass 16, count 0 2006.259.08:13:10.14#ibcon#*before return 0, iclass 16, count 0 2006.259.08:13:10.14#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.259.08:13:10.14#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.259.08:13:10.14#ibcon#about to clear, iclass 16 cls_cnt 0 2006.259.08:13:10.14#ibcon#cleared, iclass 16 cls_cnt 0 2006.259.08:13:10.14$vc4f8/va=5,7 2006.259.08:13:10.14#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.259.08:13:10.14#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.259.08:13:10.14#ibcon#ireg 11 cls_cnt 2 2006.259.08:13:10.14#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.259.08:13:10.20#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.259.08:13:10.20#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.259.08:13:10.20#ibcon#enter wrdev, iclass 18, count 2 2006.259.08:13:10.20#ibcon#first serial, iclass 18, count 2 2006.259.08:13:10.20#ibcon#enter sib2, iclass 18, count 2 2006.259.08:13:10.20#ibcon#flushed, iclass 18, count 2 2006.259.08:13:10.20#ibcon#about to write, iclass 18, count 2 2006.259.08:13:10.20#ibcon#wrote, iclass 18, count 2 2006.259.08:13:10.20#ibcon#about to read 3, iclass 18, count 2 2006.259.08:13:10.22#ibcon#read 3, iclass 18, count 2 2006.259.08:13:10.22#ibcon#about to read 4, iclass 18, count 2 2006.259.08:13:10.22#ibcon#read 4, iclass 18, count 2 2006.259.08:13:10.22#ibcon#about to read 5, iclass 18, count 2 2006.259.08:13:10.22#ibcon#read 5, iclass 18, count 2 2006.259.08:13:10.22#ibcon#about to read 6, iclass 18, count 2 2006.259.08:13:10.22#ibcon#read 6, iclass 18, count 2 2006.259.08:13:10.22#ibcon#end of sib2, iclass 18, count 2 2006.259.08:13:10.22#ibcon#*mode == 0, iclass 18, count 2 2006.259.08:13:10.22#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.259.08:13:10.22#ibcon#[25=AT05-07\r\n] 2006.259.08:13:10.22#ibcon#*before write, iclass 18, count 2 2006.259.08:13:10.22#ibcon#enter sib2, iclass 18, count 2 2006.259.08:13:10.22#ibcon#flushed, iclass 18, count 2 2006.259.08:13:10.22#ibcon#about to write, iclass 18, count 2 2006.259.08:13:10.22#ibcon#wrote, iclass 18, count 2 2006.259.08:13:10.22#ibcon#about to read 3, iclass 18, count 2 2006.259.08:13:10.25#ibcon#read 3, iclass 18, count 2 2006.259.08:13:10.25#ibcon#about to read 4, iclass 18, count 2 2006.259.08:13:10.25#ibcon#read 4, iclass 18, count 2 2006.259.08:13:10.25#ibcon#about to read 5, iclass 18, count 2 2006.259.08:13:10.25#ibcon#read 5, iclass 18, count 2 2006.259.08:13:10.25#ibcon#about to read 6, iclass 18, count 2 2006.259.08:13:10.25#ibcon#read 6, iclass 18, count 2 2006.259.08:13:10.25#ibcon#end of sib2, iclass 18, count 2 2006.259.08:13:10.25#ibcon#*after write, iclass 18, count 2 2006.259.08:13:10.25#ibcon#*before return 0, iclass 18, count 2 2006.259.08:13:10.25#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.259.08:13:10.25#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.259.08:13:10.25#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.259.08:13:10.25#ibcon#ireg 7 cls_cnt 0 2006.259.08:13:10.25#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.259.08:13:10.38#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.259.08:13:10.38#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.259.08:13:10.38#ibcon#enter wrdev, iclass 18, count 0 2006.259.08:13:10.38#ibcon#first serial, iclass 18, count 0 2006.259.08:13:10.38#ibcon#enter sib2, iclass 18, count 0 2006.259.08:13:10.38#ibcon#flushed, iclass 18, count 0 2006.259.08:13:10.38#ibcon#about to write, iclass 18, count 0 2006.259.08:13:10.38#ibcon#wrote, iclass 18, count 0 2006.259.08:13:10.38#ibcon#about to read 3, iclass 18, count 0 2006.259.08:13:10.40#ibcon#read 3, iclass 18, count 0 2006.259.08:13:10.40#ibcon#about to read 4, iclass 18, count 0 2006.259.08:13:10.40#ibcon#read 4, iclass 18, count 0 2006.259.08:13:10.40#ibcon#about to read 5, iclass 18, count 0 2006.259.08:13:10.40#ibcon#read 5, iclass 18, count 0 2006.259.08:13:10.40#ibcon#about to read 6, iclass 18, count 0 2006.259.08:13:10.40#ibcon#read 6, iclass 18, count 0 2006.259.08:13:10.40#ibcon#end of sib2, iclass 18, count 0 2006.259.08:13:10.40#ibcon#*mode == 0, iclass 18, count 0 2006.259.08:13:10.40#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.259.08:13:10.40#ibcon#[25=USB\r\n] 2006.259.08:13:10.40#ibcon#*before write, iclass 18, count 0 2006.259.08:13:10.40#ibcon#enter sib2, iclass 18, count 0 2006.259.08:13:10.40#ibcon#flushed, iclass 18, count 0 2006.259.08:13:10.40#ibcon#about to write, iclass 18, count 0 2006.259.08:13:10.40#ibcon#wrote, iclass 18, count 0 2006.259.08:13:10.40#ibcon#about to read 3, iclass 18, count 0 2006.259.08:13:10.43#ibcon#read 3, iclass 18, count 0 2006.259.08:13:10.43#ibcon#about to read 4, iclass 18, count 0 2006.259.08:13:10.43#ibcon#read 4, iclass 18, count 0 2006.259.08:13:10.43#ibcon#about to read 5, iclass 18, count 0 2006.259.08:13:10.43#ibcon#read 5, iclass 18, count 0 2006.259.08:13:10.43#ibcon#about to read 6, iclass 18, count 0 2006.259.08:13:10.43#ibcon#read 6, iclass 18, count 0 2006.259.08:13:10.43#ibcon#end of sib2, iclass 18, count 0 2006.259.08:13:10.43#ibcon#*after write, iclass 18, count 0 2006.259.08:13:10.43#ibcon#*before return 0, iclass 18, count 0 2006.259.08:13:10.43#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.259.08:13:10.43#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.259.08:13:10.43#ibcon#about to clear, iclass 18 cls_cnt 0 2006.259.08:13:10.43#ibcon#cleared, iclass 18 cls_cnt 0 2006.259.08:13:10.43$vc4f8/valo=6,772.99 2006.259.08:13:10.43#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.259.08:13:10.43#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.259.08:13:10.43#ibcon#ireg 17 cls_cnt 0 2006.259.08:13:10.43#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.259.08:13:10.43#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.259.08:13:10.43#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.259.08:13:10.43#ibcon#enter wrdev, iclass 20, count 0 2006.259.08:13:10.43#ibcon#first serial, iclass 20, count 0 2006.259.08:13:10.43#ibcon#enter sib2, iclass 20, count 0 2006.259.08:13:10.43#ibcon#flushed, iclass 20, count 0 2006.259.08:13:10.43#ibcon#about to write, iclass 20, count 0 2006.259.08:13:10.43#ibcon#wrote, iclass 20, count 0 2006.259.08:13:10.43#ibcon#about to read 3, iclass 20, count 0 2006.259.08:13:10.45#ibcon#read 3, iclass 20, count 0 2006.259.08:13:10.45#ibcon#about to read 4, iclass 20, count 0 2006.259.08:13:10.45#ibcon#read 4, iclass 20, count 0 2006.259.08:13:10.45#ibcon#about to read 5, iclass 20, count 0 2006.259.08:13:10.45#ibcon#read 5, iclass 20, count 0 2006.259.08:13:10.45#ibcon#about to read 6, iclass 20, count 0 2006.259.08:13:10.45#ibcon#read 6, iclass 20, count 0 2006.259.08:13:10.45#ibcon#end of sib2, iclass 20, count 0 2006.259.08:13:10.45#ibcon#*mode == 0, iclass 20, count 0 2006.259.08:13:10.45#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.259.08:13:10.45#ibcon#[26=FRQ=06,772.99\r\n] 2006.259.08:13:10.45#ibcon#*before write, iclass 20, count 0 2006.259.08:13:10.45#ibcon#enter sib2, iclass 20, count 0 2006.259.08:13:10.45#ibcon#flushed, iclass 20, count 0 2006.259.08:13:10.45#ibcon#about to write, iclass 20, count 0 2006.259.08:13:10.45#ibcon#wrote, iclass 20, count 0 2006.259.08:13:10.45#ibcon#about to read 3, iclass 20, count 0 2006.259.08:13:10.49#ibcon#read 3, iclass 20, count 0 2006.259.08:13:10.49#ibcon#about to read 4, iclass 20, count 0 2006.259.08:13:10.49#ibcon#read 4, iclass 20, count 0 2006.259.08:13:10.49#ibcon#about to read 5, iclass 20, count 0 2006.259.08:13:10.49#ibcon#read 5, iclass 20, count 0 2006.259.08:13:10.49#ibcon#about to read 6, iclass 20, count 0 2006.259.08:13:10.49#ibcon#read 6, iclass 20, count 0 2006.259.08:13:10.49#ibcon#end of sib2, iclass 20, count 0 2006.259.08:13:10.49#ibcon#*after write, iclass 20, count 0 2006.259.08:13:10.49#ibcon#*before return 0, iclass 20, count 0 2006.259.08:13:10.49#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.259.08:13:10.49#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.259.08:13:10.49#ibcon#about to clear, iclass 20 cls_cnt 0 2006.259.08:13:10.49#ibcon#cleared, iclass 20 cls_cnt 0 2006.259.08:13:10.49$vc4f8/va=6,6 2006.259.08:13:10.49#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.259.08:13:10.49#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.259.08:13:10.49#ibcon#ireg 11 cls_cnt 2 2006.259.08:13:10.49#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.259.08:13:10.55#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.259.08:13:10.55#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.259.08:13:10.55#ibcon#enter wrdev, iclass 22, count 2 2006.259.08:13:10.55#ibcon#first serial, iclass 22, count 2 2006.259.08:13:10.55#ibcon#enter sib2, iclass 22, count 2 2006.259.08:13:10.55#ibcon#flushed, iclass 22, count 2 2006.259.08:13:10.55#ibcon#about to write, iclass 22, count 2 2006.259.08:13:10.55#ibcon#wrote, iclass 22, count 2 2006.259.08:13:10.55#ibcon#about to read 3, iclass 22, count 2 2006.259.08:13:10.57#ibcon#read 3, iclass 22, count 2 2006.259.08:13:10.57#ibcon#about to read 4, iclass 22, count 2 2006.259.08:13:10.57#ibcon#read 4, iclass 22, count 2 2006.259.08:13:10.57#ibcon#about to read 5, iclass 22, count 2 2006.259.08:13:10.57#ibcon#read 5, iclass 22, count 2 2006.259.08:13:10.57#ibcon#about to read 6, iclass 22, count 2 2006.259.08:13:10.57#ibcon#read 6, iclass 22, count 2 2006.259.08:13:10.57#ibcon#end of sib2, iclass 22, count 2 2006.259.08:13:10.57#ibcon#*mode == 0, iclass 22, count 2 2006.259.08:13:10.57#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.259.08:13:10.57#ibcon#[25=AT06-06\r\n] 2006.259.08:13:10.57#ibcon#*before write, iclass 22, count 2 2006.259.08:13:10.57#ibcon#enter sib2, iclass 22, count 2 2006.259.08:13:10.57#ibcon#flushed, iclass 22, count 2 2006.259.08:13:10.57#ibcon#about to write, iclass 22, count 2 2006.259.08:13:10.57#ibcon#wrote, iclass 22, count 2 2006.259.08:13:10.57#ibcon#about to read 3, iclass 22, count 2 2006.259.08:13:10.60#ibcon#read 3, iclass 22, count 2 2006.259.08:13:10.60#ibcon#about to read 4, iclass 22, count 2 2006.259.08:13:10.60#ibcon#read 4, iclass 22, count 2 2006.259.08:13:10.60#ibcon#about to read 5, iclass 22, count 2 2006.259.08:13:10.60#ibcon#read 5, iclass 22, count 2 2006.259.08:13:10.60#ibcon#about to read 6, iclass 22, count 2 2006.259.08:13:10.60#ibcon#read 6, iclass 22, count 2 2006.259.08:13:10.60#ibcon#end of sib2, iclass 22, count 2 2006.259.08:13:10.60#ibcon#*after write, iclass 22, count 2 2006.259.08:13:10.60#ibcon#*before return 0, iclass 22, count 2 2006.259.08:13:10.60#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.259.08:13:10.60#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.259.08:13:10.60#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.259.08:13:10.60#ibcon#ireg 7 cls_cnt 0 2006.259.08:13:10.60#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.259.08:13:10.72#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.259.08:13:10.72#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.259.08:13:10.72#ibcon#enter wrdev, iclass 22, count 0 2006.259.08:13:10.72#ibcon#first serial, iclass 22, count 0 2006.259.08:13:10.72#ibcon#enter sib2, iclass 22, count 0 2006.259.08:13:10.72#ibcon#flushed, iclass 22, count 0 2006.259.08:13:10.72#ibcon#about to write, iclass 22, count 0 2006.259.08:13:10.72#ibcon#wrote, iclass 22, count 0 2006.259.08:13:10.72#ibcon#about to read 3, iclass 22, count 0 2006.259.08:13:10.74#ibcon#read 3, iclass 22, count 0 2006.259.08:13:10.74#ibcon#about to read 4, iclass 22, count 0 2006.259.08:13:10.74#ibcon#read 4, iclass 22, count 0 2006.259.08:13:10.74#ibcon#about to read 5, iclass 22, count 0 2006.259.08:13:10.74#ibcon#read 5, iclass 22, count 0 2006.259.08:13:10.74#ibcon#about to read 6, iclass 22, count 0 2006.259.08:13:10.74#ibcon#read 6, iclass 22, count 0 2006.259.08:13:10.74#ibcon#end of sib2, iclass 22, count 0 2006.259.08:13:10.74#ibcon#*mode == 0, iclass 22, count 0 2006.259.08:13:10.74#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.259.08:13:10.74#ibcon#[25=USB\r\n] 2006.259.08:13:10.74#ibcon#*before write, iclass 22, count 0 2006.259.08:13:10.74#ibcon#enter sib2, iclass 22, count 0 2006.259.08:13:10.74#ibcon#flushed, iclass 22, count 0 2006.259.08:13:10.74#ibcon#about to write, iclass 22, count 0 2006.259.08:13:10.74#ibcon#wrote, iclass 22, count 0 2006.259.08:13:10.74#ibcon#about to read 3, iclass 22, count 0 2006.259.08:13:10.77#ibcon#read 3, iclass 22, count 0 2006.259.08:13:10.77#ibcon#about to read 4, iclass 22, count 0 2006.259.08:13:10.77#ibcon#read 4, iclass 22, count 0 2006.259.08:13:10.77#ibcon#about to read 5, iclass 22, count 0 2006.259.08:13:10.77#ibcon#read 5, iclass 22, count 0 2006.259.08:13:10.77#ibcon#about to read 6, iclass 22, count 0 2006.259.08:13:10.77#ibcon#read 6, iclass 22, count 0 2006.259.08:13:10.77#ibcon#end of sib2, iclass 22, count 0 2006.259.08:13:10.77#ibcon#*after write, iclass 22, count 0 2006.259.08:13:10.77#ibcon#*before return 0, iclass 22, count 0 2006.259.08:13:10.77#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.259.08:13:10.77#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.259.08:13:10.77#ibcon#about to clear, iclass 22 cls_cnt 0 2006.259.08:13:10.77#ibcon#cleared, iclass 22 cls_cnt 0 2006.259.08:13:10.77$vc4f8/valo=7,832.99 2006.259.08:13:10.77#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.259.08:13:10.77#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.259.08:13:10.77#ibcon#ireg 17 cls_cnt 0 2006.259.08:13:10.77#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.259.08:13:10.77#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.259.08:13:10.77#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.259.08:13:10.77#ibcon#enter wrdev, iclass 24, count 0 2006.259.08:13:10.77#ibcon#first serial, iclass 24, count 0 2006.259.08:13:10.77#ibcon#enter sib2, iclass 24, count 0 2006.259.08:13:10.77#ibcon#flushed, iclass 24, count 0 2006.259.08:13:10.77#ibcon#about to write, iclass 24, count 0 2006.259.08:13:10.77#ibcon#wrote, iclass 24, count 0 2006.259.08:13:10.77#ibcon#about to read 3, iclass 24, count 0 2006.259.08:13:10.79#ibcon#read 3, iclass 24, count 0 2006.259.08:13:10.79#ibcon#about to read 4, iclass 24, count 0 2006.259.08:13:10.79#ibcon#read 4, iclass 24, count 0 2006.259.08:13:10.79#ibcon#about to read 5, iclass 24, count 0 2006.259.08:13:10.79#ibcon#read 5, iclass 24, count 0 2006.259.08:13:10.79#ibcon#about to read 6, iclass 24, count 0 2006.259.08:13:10.79#ibcon#read 6, iclass 24, count 0 2006.259.08:13:10.79#ibcon#end of sib2, iclass 24, count 0 2006.259.08:13:10.79#ibcon#*mode == 0, iclass 24, count 0 2006.259.08:13:10.79#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.259.08:13:10.79#ibcon#[26=FRQ=07,832.99\r\n] 2006.259.08:13:10.79#ibcon#*before write, iclass 24, count 0 2006.259.08:13:10.79#ibcon#enter sib2, iclass 24, count 0 2006.259.08:13:10.79#ibcon#flushed, iclass 24, count 0 2006.259.08:13:10.79#ibcon#about to write, iclass 24, count 0 2006.259.08:13:10.79#ibcon#wrote, iclass 24, count 0 2006.259.08:13:10.79#ibcon#about to read 3, iclass 24, count 0 2006.259.08:13:10.83#ibcon#read 3, iclass 24, count 0 2006.259.08:13:10.83#ibcon#about to read 4, iclass 24, count 0 2006.259.08:13:10.83#ibcon#read 4, iclass 24, count 0 2006.259.08:13:10.83#ibcon#about to read 5, iclass 24, count 0 2006.259.08:13:10.83#ibcon#read 5, iclass 24, count 0 2006.259.08:13:10.83#ibcon#about to read 6, iclass 24, count 0 2006.259.08:13:10.83#ibcon#read 6, iclass 24, count 0 2006.259.08:13:10.83#ibcon#end of sib2, iclass 24, count 0 2006.259.08:13:10.83#ibcon#*after write, iclass 24, count 0 2006.259.08:13:10.83#ibcon#*before return 0, iclass 24, count 0 2006.259.08:13:10.83#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.259.08:13:10.83#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.259.08:13:10.83#ibcon#about to clear, iclass 24 cls_cnt 0 2006.259.08:13:10.83#ibcon#cleared, iclass 24 cls_cnt 0 2006.259.08:13:10.83$vc4f8/va=7,6 2006.259.08:13:10.83#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.259.08:13:10.83#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.259.08:13:10.83#ibcon#ireg 11 cls_cnt 2 2006.259.08:13:10.83#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.259.08:13:10.89#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.259.08:13:10.89#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.259.08:13:10.89#ibcon#enter wrdev, iclass 26, count 2 2006.259.08:13:10.89#ibcon#first serial, iclass 26, count 2 2006.259.08:13:10.89#ibcon#enter sib2, iclass 26, count 2 2006.259.08:13:10.89#ibcon#flushed, iclass 26, count 2 2006.259.08:13:10.89#ibcon#about to write, iclass 26, count 2 2006.259.08:13:10.89#ibcon#wrote, iclass 26, count 2 2006.259.08:13:10.89#ibcon#about to read 3, iclass 26, count 2 2006.259.08:13:10.91#ibcon#read 3, iclass 26, count 2 2006.259.08:13:10.91#ibcon#about to read 4, iclass 26, count 2 2006.259.08:13:10.91#ibcon#read 4, iclass 26, count 2 2006.259.08:13:10.91#ibcon#about to read 5, iclass 26, count 2 2006.259.08:13:10.91#ibcon#read 5, iclass 26, count 2 2006.259.08:13:10.91#ibcon#about to read 6, iclass 26, count 2 2006.259.08:13:10.91#ibcon#read 6, iclass 26, count 2 2006.259.08:13:10.91#ibcon#end of sib2, iclass 26, count 2 2006.259.08:13:10.91#ibcon#*mode == 0, iclass 26, count 2 2006.259.08:13:10.91#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.259.08:13:10.91#ibcon#[25=AT07-06\r\n] 2006.259.08:13:10.91#ibcon#*before write, iclass 26, count 2 2006.259.08:13:10.91#ibcon#enter sib2, iclass 26, count 2 2006.259.08:13:10.91#ibcon#flushed, iclass 26, count 2 2006.259.08:13:10.91#ibcon#about to write, iclass 26, count 2 2006.259.08:13:10.91#ibcon#wrote, iclass 26, count 2 2006.259.08:13:10.91#ibcon#about to read 3, iclass 26, count 2 2006.259.08:13:10.94#ibcon#read 3, iclass 26, count 2 2006.259.08:13:10.94#ibcon#about to read 4, iclass 26, count 2 2006.259.08:13:10.94#ibcon#read 4, iclass 26, count 2 2006.259.08:13:10.94#ibcon#about to read 5, iclass 26, count 2 2006.259.08:13:10.94#ibcon#read 5, iclass 26, count 2 2006.259.08:13:10.94#ibcon#about to read 6, iclass 26, count 2 2006.259.08:13:10.94#ibcon#read 6, iclass 26, count 2 2006.259.08:13:10.94#ibcon#end of sib2, iclass 26, count 2 2006.259.08:13:10.94#ibcon#*after write, iclass 26, count 2 2006.259.08:13:10.94#ibcon#*before return 0, iclass 26, count 2 2006.259.08:13:10.94#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.259.08:13:10.94#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.259.08:13:10.94#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.259.08:13:10.94#ibcon#ireg 7 cls_cnt 0 2006.259.08:13:10.94#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.259.08:13:11.06#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.259.08:13:11.06#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.259.08:13:11.06#ibcon#enter wrdev, iclass 26, count 0 2006.259.08:13:11.06#ibcon#first serial, iclass 26, count 0 2006.259.08:13:11.06#ibcon#enter sib2, iclass 26, count 0 2006.259.08:13:11.06#ibcon#flushed, iclass 26, count 0 2006.259.08:13:11.06#ibcon#about to write, iclass 26, count 0 2006.259.08:13:11.06#ibcon#wrote, iclass 26, count 0 2006.259.08:13:11.06#ibcon#about to read 3, iclass 26, count 0 2006.259.08:13:11.10#ibcon#read 3, iclass 26, count 0 2006.259.08:13:11.10#ibcon#about to read 4, iclass 26, count 0 2006.259.08:13:11.10#ibcon#read 4, iclass 26, count 0 2006.259.08:13:11.10#ibcon#about to read 5, iclass 26, count 0 2006.259.08:13:11.10#ibcon#read 5, iclass 26, count 0 2006.259.08:13:11.10#ibcon#about to read 6, iclass 26, count 0 2006.259.08:13:11.10#ibcon#read 6, iclass 26, count 0 2006.259.08:13:11.10#ibcon#end of sib2, iclass 26, count 0 2006.259.08:13:11.10#ibcon#*mode == 0, iclass 26, count 0 2006.259.08:13:11.10#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.259.08:13:11.10#ibcon#[25=USB\r\n] 2006.259.08:13:11.10#ibcon#*before write, iclass 26, count 0 2006.259.08:13:11.10#ibcon#enter sib2, iclass 26, count 0 2006.259.08:13:11.10#ibcon#flushed, iclass 26, count 0 2006.259.08:13:11.10#ibcon#about to write, iclass 26, count 0 2006.259.08:13:11.10#ibcon#wrote, iclass 26, count 0 2006.259.08:13:11.10#ibcon#about to read 3, iclass 26, count 0 2006.259.08:13:11.13#ibcon#read 3, iclass 26, count 0 2006.259.08:13:11.13#ibcon#about to read 4, iclass 26, count 0 2006.259.08:13:11.13#ibcon#read 4, iclass 26, count 0 2006.259.08:13:11.13#ibcon#about to read 5, iclass 26, count 0 2006.259.08:13:11.13#ibcon#read 5, iclass 26, count 0 2006.259.08:13:11.13#ibcon#about to read 6, iclass 26, count 0 2006.259.08:13:11.13#ibcon#read 6, iclass 26, count 0 2006.259.08:13:11.13#ibcon#end of sib2, iclass 26, count 0 2006.259.08:13:11.13#ibcon#*after write, iclass 26, count 0 2006.259.08:13:11.13#ibcon#*before return 0, iclass 26, count 0 2006.259.08:13:11.13#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.259.08:13:11.13#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.259.08:13:11.13#ibcon#about to clear, iclass 26 cls_cnt 0 2006.259.08:13:11.13#ibcon#cleared, iclass 26 cls_cnt 0 2006.259.08:13:11.13$vc4f8/valo=8,852.99 2006.259.08:13:11.13#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.259.08:13:11.13#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.259.08:13:11.13#ibcon#ireg 17 cls_cnt 0 2006.259.08:13:11.13#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.259.08:13:11.13#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.259.08:13:11.13#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.259.08:13:11.13#ibcon#enter wrdev, iclass 28, count 0 2006.259.08:13:11.13#ibcon#first serial, iclass 28, count 0 2006.259.08:13:11.13#ibcon#enter sib2, iclass 28, count 0 2006.259.08:13:11.13#ibcon#flushed, iclass 28, count 0 2006.259.08:13:11.13#ibcon#about to write, iclass 28, count 0 2006.259.08:13:11.13#ibcon#wrote, iclass 28, count 0 2006.259.08:13:11.13#ibcon#about to read 3, iclass 28, count 0 2006.259.08:13:11.15#ibcon#read 3, iclass 28, count 0 2006.259.08:13:11.15#ibcon#about to read 4, iclass 28, count 0 2006.259.08:13:11.15#ibcon#read 4, iclass 28, count 0 2006.259.08:13:11.15#ibcon#about to read 5, iclass 28, count 0 2006.259.08:13:11.15#ibcon#read 5, iclass 28, count 0 2006.259.08:13:11.15#ibcon#about to read 6, iclass 28, count 0 2006.259.08:13:11.15#ibcon#read 6, iclass 28, count 0 2006.259.08:13:11.15#ibcon#end of sib2, iclass 28, count 0 2006.259.08:13:11.15#ibcon#*mode == 0, iclass 28, count 0 2006.259.08:13:11.15#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.259.08:13:11.15#ibcon#[26=FRQ=08,852.99\r\n] 2006.259.08:13:11.15#ibcon#*before write, iclass 28, count 0 2006.259.08:13:11.15#ibcon#enter sib2, iclass 28, count 0 2006.259.08:13:11.15#ibcon#flushed, iclass 28, count 0 2006.259.08:13:11.15#ibcon#about to write, iclass 28, count 0 2006.259.08:13:11.15#ibcon#wrote, iclass 28, count 0 2006.259.08:13:11.15#ibcon#about to read 3, iclass 28, count 0 2006.259.08:13:11.19#ibcon#read 3, iclass 28, count 0 2006.259.08:13:11.19#ibcon#about to read 4, iclass 28, count 0 2006.259.08:13:11.19#ibcon#read 4, iclass 28, count 0 2006.259.08:13:11.19#ibcon#about to read 5, iclass 28, count 0 2006.259.08:13:11.19#ibcon#read 5, iclass 28, count 0 2006.259.08:13:11.19#ibcon#about to read 6, iclass 28, count 0 2006.259.08:13:11.19#ibcon#read 6, iclass 28, count 0 2006.259.08:13:11.19#ibcon#end of sib2, iclass 28, count 0 2006.259.08:13:11.19#ibcon#*after write, iclass 28, count 0 2006.259.08:13:11.19#ibcon#*before return 0, iclass 28, count 0 2006.259.08:13:11.19#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.259.08:13:11.19#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.259.08:13:11.19#ibcon#about to clear, iclass 28 cls_cnt 0 2006.259.08:13:11.19#ibcon#cleared, iclass 28 cls_cnt 0 2006.259.08:13:11.19$vc4f8/va=8,6 2006.259.08:13:11.19#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.259.08:13:11.19#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.259.08:13:11.19#ibcon#ireg 11 cls_cnt 2 2006.259.08:13:11.19#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.259.08:13:11.25#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.259.08:13:11.25#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.259.08:13:11.25#ibcon#enter wrdev, iclass 30, count 2 2006.259.08:13:11.25#ibcon#first serial, iclass 30, count 2 2006.259.08:13:11.25#ibcon#enter sib2, iclass 30, count 2 2006.259.08:13:11.25#ibcon#flushed, iclass 30, count 2 2006.259.08:13:11.25#ibcon#about to write, iclass 30, count 2 2006.259.08:13:11.25#ibcon#wrote, iclass 30, count 2 2006.259.08:13:11.25#ibcon#about to read 3, iclass 30, count 2 2006.259.08:13:11.27#ibcon#read 3, iclass 30, count 2 2006.259.08:13:11.27#ibcon#about to read 4, iclass 30, count 2 2006.259.08:13:11.27#ibcon#read 4, iclass 30, count 2 2006.259.08:13:11.27#ibcon#about to read 5, iclass 30, count 2 2006.259.08:13:11.27#ibcon#read 5, iclass 30, count 2 2006.259.08:13:11.27#ibcon#about to read 6, iclass 30, count 2 2006.259.08:13:11.27#ibcon#read 6, iclass 30, count 2 2006.259.08:13:11.27#ibcon#end of sib2, iclass 30, count 2 2006.259.08:13:11.27#ibcon#*mode == 0, iclass 30, count 2 2006.259.08:13:11.27#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.259.08:13:11.27#ibcon#[25=AT08-06\r\n] 2006.259.08:13:11.27#ibcon#*before write, iclass 30, count 2 2006.259.08:13:11.27#ibcon#enter sib2, iclass 30, count 2 2006.259.08:13:11.27#ibcon#flushed, iclass 30, count 2 2006.259.08:13:11.27#ibcon#about to write, iclass 30, count 2 2006.259.08:13:11.27#ibcon#wrote, iclass 30, count 2 2006.259.08:13:11.27#ibcon#about to read 3, iclass 30, count 2 2006.259.08:13:11.30#ibcon#read 3, iclass 30, count 2 2006.259.08:13:11.30#ibcon#about to read 4, iclass 30, count 2 2006.259.08:13:11.30#ibcon#read 4, iclass 30, count 2 2006.259.08:13:11.30#ibcon#about to read 5, iclass 30, count 2 2006.259.08:13:11.30#ibcon#read 5, iclass 30, count 2 2006.259.08:13:11.30#ibcon#about to read 6, iclass 30, count 2 2006.259.08:13:11.30#ibcon#read 6, iclass 30, count 2 2006.259.08:13:11.30#ibcon#end of sib2, iclass 30, count 2 2006.259.08:13:11.30#ibcon#*after write, iclass 30, count 2 2006.259.08:13:11.30#ibcon#*before return 0, iclass 30, count 2 2006.259.08:13:11.30#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.259.08:13:11.30#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.259.08:13:11.30#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.259.08:13:11.30#ibcon#ireg 7 cls_cnt 0 2006.259.08:13:11.30#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.259.08:13:11.42#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.259.08:13:11.42#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.259.08:13:11.42#ibcon#enter wrdev, iclass 30, count 0 2006.259.08:13:11.42#ibcon#first serial, iclass 30, count 0 2006.259.08:13:11.42#ibcon#enter sib2, iclass 30, count 0 2006.259.08:13:11.42#ibcon#flushed, iclass 30, count 0 2006.259.08:13:11.42#ibcon#about to write, iclass 30, count 0 2006.259.08:13:11.42#ibcon#wrote, iclass 30, count 0 2006.259.08:13:11.42#ibcon#about to read 3, iclass 30, count 0 2006.259.08:13:11.44#ibcon#read 3, iclass 30, count 0 2006.259.08:13:11.44#ibcon#about to read 4, iclass 30, count 0 2006.259.08:13:11.44#ibcon#read 4, iclass 30, count 0 2006.259.08:13:11.44#ibcon#about to read 5, iclass 30, count 0 2006.259.08:13:11.44#ibcon#read 5, iclass 30, count 0 2006.259.08:13:11.44#ibcon#about to read 6, iclass 30, count 0 2006.259.08:13:11.44#ibcon#read 6, iclass 30, count 0 2006.259.08:13:11.44#ibcon#end of sib2, iclass 30, count 0 2006.259.08:13:11.44#ibcon#*mode == 0, iclass 30, count 0 2006.259.08:13:11.44#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.259.08:13:11.44#ibcon#[25=USB\r\n] 2006.259.08:13:11.44#ibcon#*before write, iclass 30, count 0 2006.259.08:13:11.44#ibcon#enter sib2, iclass 30, count 0 2006.259.08:13:11.44#ibcon#flushed, iclass 30, count 0 2006.259.08:13:11.44#ibcon#about to write, iclass 30, count 0 2006.259.08:13:11.44#ibcon#wrote, iclass 30, count 0 2006.259.08:13:11.44#ibcon#about to read 3, iclass 30, count 0 2006.259.08:13:11.47#ibcon#read 3, iclass 30, count 0 2006.259.08:13:11.47#ibcon#about to read 4, iclass 30, count 0 2006.259.08:13:11.47#ibcon#read 4, iclass 30, count 0 2006.259.08:13:11.47#ibcon#about to read 5, iclass 30, count 0 2006.259.08:13:11.47#ibcon#read 5, iclass 30, count 0 2006.259.08:13:11.47#ibcon#about to read 6, iclass 30, count 0 2006.259.08:13:11.47#ibcon#read 6, iclass 30, count 0 2006.259.08:13:11.47#ibcon#end of sib2, iclass 30, count 0 2006.259.08:13:11.47#ibcon#*after write, iclass 30, count 0 2006.259.08:13:11.47#ibcon#*before return 0, iclass 30, count 0 2006.259.08:13:11.47#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.259.08:13:11.47#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.259.08:13:11.47#ibcon#about to clear, iclass 30 cls_cnt 0 2006.259.08:13:11.47#ibcon#cleared, iclass 30 cls_cnt 0 2006.259.08:13:11.47$vc4f8/vblo=1,632.99 2006.259.08:13:11.47#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.259.08:13:11.47#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.259.08:13:11.47#ibcon#ireg 17 cls_cnt 0 2006.259.08:13:11.47#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.259.08:13:11.47#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.259.08:13:11.47#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.259.08:13:11.47#ibcon#enter wrdev, iclass 32, count 0 2006.259.08:13:11.47#ibcon#first serial, iclass 32, count 0 2006.259.08:13:11.47#ibcon#enter sib2, iclass 32, count 0 2006.259.08:13:11.47#ibcon#flushed, iclass 32, count 0 2006.259.08:13:11.47#ibcon#about to write, iclass 32, count 0 2006.259.08:13:11.47#ibcon#wrote, iclass 32, count 0 2006.259.08:13:11.47#ibcon#about to read 3, iclass 32, count 0 2006.259.08:13:11.49#ibcon#read 3, iclass 32, count 0 2006.259.08:13:11.49#ibcon#about to read 4, iclass 32, count 0 2006.259.08:13:11.49#ibcon#read 4, iclass 32, count 0 2006.259.08:13:11.49#ibcon#about to read 5, iclass 32, count 0 2006.259.08:13:11.49#ibcon#read 5, iclass 32, count 0 2006.259.08:13:11.49#ibcon#about to read 6, iclass 32, count 0 2006.259.08:13:11.49#ibcon#read 6, iclass 32, count 0 2006.259.08:13:11.49#ibcon#end of sib2, iclass 32, count 0 2006.259.08:13:11.49#ibcon#*mode == 0, iclass 32, count 0 2006.259.08:13:11.49#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.259.08:13:11.49#ibcon#[28=FRQ=01,632.99\r\n] 2006.259.08:13:11.49#ibcon#*before write, iclass 32, count 0 2006.259.08:13:11.49#ibcon#enter sib2, iclass 32, count 0 2006.259.08:13:11.49#ibcon#flushed, iclass 32, count 0 2006.259.08:13:11.49#ibcon#about to write, iclass 32, count 0 2006.259.08:13:11.49#ibcon#wrote, iclass 32, count 0 2006.259.08:13:11.49#ibcon#about to read 3, iclass 32, count 0 2006.259.08:13:11.53#ibcon#read 3, iclass 32, count 0 2006.259.08:13:11.53#ibcon#about to read 4, iclass 32, count 0 2006.259.08:13:11.53#ibcon#read 4, iclass 32, count 0 2006.259.08:13:11.53#ibcon#about to read 5, iclass 32, count 0 2006.259.08:13:11.53#ibcon#read 5, iclass 32, count 0 2006.259.08:13:11.53#ibcon#about to read 6, iclass 32, count 0 2006.259.08:13:11.53#ibcon#read 6, iclass 32, count 0 2006.259.08:13:11.53#ibcon#end of sib2, iclass 32, count 0 2006.259.08:13:11.53#ibcon#*after write, iclass 32, count 0 2006.259.08:13:11.53#ibcon#*before return 0, iclass 32, count 0 2006.259.08:13:11.53#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.259.08:13:11.53#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.259.08:13:11.53#ibcon#about to clear, iclass 32 cls_cnt 0 2006.259.08:13:11.53#ibcon#cleared, iclass 32 cls_cnt 0 2006.259.08:13:11.53$vc4f8/vb=1,4 2006.259.08:13:11.53#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.259.08:13:11.53#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.259.08:13:11.53#ibcon#ireg 11 cls_cnt 2 2006.259.08:13:11.53#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.259.08:13:11.53#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.259.08:13:11.53#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.259.08:13:11.53#ibcon#enter wrdev, iclass 34, count 2 2006.259.08:13:11.53#ibcon#first serial, iclass 34, count 2 2006.259.08:13:11.53#ibcon#enter sib2, iclass 34, count 2 2006.259.08:13:11.53#ibcon#flushed, iclass 34, count 2 2006.259.08:13:11.53#ibcon#about to write, iclass 34, count 2 2006.259.08:13:11.53#ibcon#wrote, iclass 34, count 2 2006.259.08:13:11.53#ibcon#about to read 3, iclass 34, count 2 2006.259.08:13:11.55#ibcon#read 3, iclass 34, count 2 2006.259.08:13:11.55#ibcon#about to read 4, iclass 34, count 2 2006.259.08:13:11.55#ibcon#read 4, iclass 34, count 2 2006.259.08:13:11.55#ibcon#about to read 5, iclass 34, count 2 2006.259.08:13:11.55#ibcon#read 5, iclass 34, count 2 2006.259.08:13:11.55#ibcon#about to read 6, iclass 34, count 2 2006.259.08:13:11.55#ibcon#read 6, iclass 34, count 2 2006.259.08:13:11.55#ibcon#end of sib2, iclass 34, count 2 2006.259.08:13:11.55#ibcon#*mode == 0, iclass 34, count 2 2006.259.08:13:11.55#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.259.08:13:11.55#ibcon#[27=AT01-04\r\n] 2006.259.08:13:11.55#ibcon#*before write, iclass 34, count 2 2006.259.08:13:11.55#ibcon#enter sib2, iclass 34, count 2 2006.259.08:13:11.55#ibcon#flushed, iclass 34, count 2 2006.259.08:13:11.55#ibcon#about to write, iclass 34, count 2 2006.259.08:13:11.55#ibcon#wrote, iclass 34, count 2 2006.259.08:13:11.55#ibcon#about to read 3, iclass 34, count 2 2006.259.08:13:11.58#ibcon#read 3, iclass 34, count 2 2006.259.08:13:11.58#ibcon#about to read 4, iclass 34, count 2 2006.259.08:13:11.58#ibcon#read 4, iclass 34, count 2 2006.259.08:13:11.58#ibcon#about to read 5, iclass 34, count 2 2006.259.08:13:11.58#ibcon#read 5, iclass 34, count 2 2006.259.08:13:11.58#ibcon#about to read 6, iclass 34, count 2 2006.259.08:13:11.58#ibcon#read 6, iclass 34, count 2 2006.259.08:13:11.58#ibcon#end of sib2, iclass 34, count 2 2006.259.08:13:11.58#ibcon#*after write, iclass 34, count 2 2006.259.08:13:11.58#ibcon#*before return 0, iclass 34, count 2 2006.259.08:13:11.58#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.259.08:13:11.58#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.259.08:13:11.58#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.259.08:13:11.58#ibcon#ireg 7 cls_cnt 0 2006.259.08:13:11.58#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.259.08:13:11.69#abcon#<5=/04 2.5 4.9 21.95 861013.1\r\n> 2006.259.08:13:11.70#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.259.08:13:11.70#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.259.08:13:11.70#ibcon#enter wrdev, iclass 34, count 0 2006.259.08:13:11.70#ibcon#first serial, iclass 34, count 0 2006.259.08:13:11.70#ibcon#enter sib2, iclass 34, count 0 2006.259.08:13:11.70#ibcon#flushed, iclass 34, count 0 2006.259.08:13:11.70#ibcon#about to write, iclass 34, count 0 2006.259.08:13:11.70#ibcon#wrote, iclass 34, count 0 2006.259.08:13:11.70#ibcon#about to read 3, iclass 34, count 0 2006.259.08:13:11.71#abcon#{5=INTERFACE CLEAR} 2006.259.08:13:11.72#ibcon#read 3, iclass 34, count 0 2006.259.08:13:11.72#ibcon#about to read 4, iclass 34, count 0 2006.259.08:13:11.72#ibcon#read 4, iclass 34, count 0 2006.259.08:13:11.72#ibcon#about to read 5, iclass 34, count 0 2006.259.08:13:11.72#ibcon#read 5, iclass 34, count 0 2006.259.08:13:11.72#ibcon#about to read 6, iclass 34, count 0 2006.259.08:13:11.72#ibcon#read 6, iclass 34, count 0 2006.259.08:13:11.72#ibcon#end of sib2, iclass 34, count 0 2006.259.08:13:11.72#ibcon#*mode == 0, iclass 34, count 0 2006.259.08:13:11.72#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.259.08:13:11.72#ibcon#[27=USB\r\n] 2006.259.08:13:11.72#ibcon#*before write, iclass 34, count 0 2006.259.08:13:11.72#ibcon#enter sib2, iclass 34, count 0 2006.259.08:13:11.72#ibcon#flushed, iclass 34, count 0 2006.259.08:13:11.72#ibcon#about to write, iclass 34, count 0 2006.259.08:13:11.72#ibcon#wrote, iclass 34, count 0 2006.259.08:13:11.72#ibcon#about to read 3, iclass 34, count 0 2006.259.08:13:11.75#ibcon#read 3, iclass 34, count 0 2006.259.08:13:11.75#ibcon#about to read 4, iclass 34, count 0 2006.259.08:13:11.75#ibcon#read 4, iclass 34, count 0 2006.259.08:13:11.75#ibcon#about to read 5, iclass 34, count 0 2006.259.08:13:11.75#ibcon#read 5, iclass 34, count 0 2006.259.08:13:11.75#ibcon#about to read 6, iclass 34, count 0 2006.259.08:13:11.75#ibcon#read 6, iclass 34, count 0 2006.259.08:13:11.75#ibcon#end of sib2, iclass 34, count 0 2006.259.08:13:11.75#ibcon#*after write, iclass 34, count 0 2006.259.08:13:11.75#ibcon#*before return 0, iclass 34, count 0 2006.259.08:13:11.75#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.259.08:13:11.75#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.259.08:13:11.75#ibcon#about to clear, iclass 34 cls_cnt 0 2006.259.08:13:11.75#ibcon#cleared, iclass 34 cls_cnt 0 2006.259.08:13:11.75$vc4f8/vblo=2,640.99 2006.259.08:13:11.75#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.259.08:13:11.75#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.259.08:13:11.75#ibcon#ireg 17 cls_cnt 0 2006.259.08:13:11.75#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.259.08:13:11.75#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.259.08:13:11.75#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.259.08:13:11.75#ibcon#enter wrdev, iclass 39, count 0 2006.259.08:13:11.75#ibcon#first serial, iclass 39, count 0 2006.259.08:13:11.75#ibcon#enter sib2, iclass 39, count 0 2006.259.08:13:11.75#ibcon#flushed, iclass 39, count 0 2006.259.08:13:11.75#ibcon#about to write, iclass 39, count 0 2006.259.08:13:11.75#ibcon#wrote, iclass 39, count 0 2006.259.08:13:11.75#ibcon#about to read 3, iclass 39, count 0 2006.259.08:13:11.77#ibcon#read 3, iclass 39, count 0 2006.259.08:13:11.77#ibcon#about to read 4, iclass 39, count 0 2006.259.08:13:11.77#ibcon#read 4, iclass 39, count 0 2006.259.08:13:11.77#ibcon#about to read 5, iclass 39, count 0 2006.259.08:13:11.77#ibcon#read 5, iclass 39, count 0 2006.259.08:13:11.77#ibcon#about to read 6, iclass 39, count 0 2006.259.08:13:11.77#ibcon#read 6, iclass 39, count 0 2006.259.08:13:11.77#ibcon#end of sib2, iclass 39, count 0 2006.259.08:13:11.77#ibcon#*mode == 0, iclass 39, count 0 2006.259.08:13:11.77#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.259.08:13:11.77#ibcon#[28=FRQ=02,640.99\r\n] 2006.259.08:13:11.77#ibcon#*before write, iclass 39, count 0 2006.259.08:13:11.77#ibcon#enter sib2, iclass 39, count 0 2006.259.08:13:11.77#ibcon#flushed, iclass 39, count 0 2006.259.08:13:11.77#ibcon#about to write, iclass 39, count 0 2006.259.08:13:11.77#ibcon#wrote, iclass 39, count 0 2006.259.08:13:11.77#ibcon#about to read 3, iclass 39, count 0 2006.259.08:13:11.77#abcon#[5=S1D000X0/0*\r\n] 2006.259.08:13:11.81#ibcon#read 3, iclass 39, count 0 2006.259.08:13:11.81#ibcon#about to read 4, iclass 39, count 0 2006.259.08:13:11.81#ibcon#read 4, iclass 39, count 0 2006.259.08:13:11.81#ibcon#about to read 5, iclass 39, count 0 2006.259.08:13:11.81#ibcon#read 5, iclass 39, count 0 2006.259.08:13:11.81#ibcon#about to read 6, iclass 39, count 0 2006.259.08:13:11.81#ibcon#read 6, iclass 39, count 0 2006.259.08:13:11.81#ibcon#end of sib2, iclass 39, count 0 2006.259.08:13:11.81#ibcon#*after write, iclass 39, count 0 2006.259.08:13:11.81#ibcon#*before return 0, iclass 39, count 0 2006.259.08:13:11.81#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.259.08:13:11.81#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.259.08:13:11.81#ibcon#about to clear, iclass 39 cls_cnt 0 2006.259.08:13:11.81#ibcon#cleared, iclass 39 cls_cnt 0 2006.259.08:13:11.81$vc4f8/vb=2,5 2006.259.08:13:11.81#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.259.08:13:11.81#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.259.08:13:11.81#ibcon#ireg 11 cls_cnt 2 2006.259.08:13:11.81#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.259.08:13:11.87#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.259.08:13:11.87#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.259.08:13:11.87#ibcon#enter wrdev, iclass 4, count 2 2006.259.08:13:11.87#ibcon#first serial, iclass 4, count 2 2006.259.08:13:11.87#ibcon#enter sib2, iclass 4, count 2 2006.259.08:13:11.87#ibcon#flushed, iclass 4, count 2 2006.259.08:13:11.87#ibcon#about to write, iclass 4, count 2 2006.259.08:13:11.87#ibcon#wrote, iclass 4, count 2 2006.259.08:13:11.87#ibcon#about to read 3, iclass 4, count 2 2006.259.08:13:11.90#ibcon#read 3, iclass 4, count 2 2006.259.08:13:11.90#ibcon#about to read 4, iclass 4, count 2 2006.259.08:13:11.90#ibcon#read 4, iclass 4, count 2 2006.259.08:13:11.90#ibcon#about to read 5, iclass 4, count 2 2006.259.08:13:11.90#ibcon#read 5, iclass 4, count 2 2006.259.08:13:11.90#ibcon#about to read 6, iclass 4, count 2 2006.259.08:13:11.90#ibcon#read 6, iclass 4, count 2 2006.259.08:13:11.90#ibcon#end of sib2, iclass 4, count 2 2006.259.08:13:11.90#ibcon#*mode == 0, iclass 4, count 2 2006.259.08:13:11.90#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.259.08:13:11.90#ibcon#[27=AT02-05\r\n] 2006.259.08:13:11.90#ibcon#*before write, iclass 4, count 2 2006.259.08:13:11.90#ibcon#enter sib2, iclass 4, count 2 2006.259.08:13:11.90#ibcon#flushed, iclass 4, count 2 2006.259.08:13:11.90#ibcon#about to write, iclass 4, count 2 2006.259.08:13:11.90#ibcon#wrote, iclass 4, count 2 2006.259.08:13:11.90#ibcon#about to read 3, iclass 4, count 2 2006.259.08:13:11.93#ibcon#read 3, iclass 4, count 2 2006.259.08:13:11.93#ibcon#about to read 4, iclass 4, count 2 2006.259.08:13:11.93#ibcon#read 4, iclass 4, count 2 2006.259.08:13:11.93#ibcon#about to read 5, iclass 4, count 2 2006.259.08:13:11.93#ibcon#read 5, iclass 4, count 2 2006.259.08:13:11.93#ibcon#about to read 6, iclass 4, count 2 2006.259.08:13:11.93#ibcon#read 6, iclass 4, count 2 2006.259.08:13:11.93#ibcon#end of sib2, iclass 4, count 2 2006.259.08:13:11.93#ibcon#*after write, iclass 4, count 2 2006.259.08:13:11.93#ibcon#*before return 0, iclass 4, count 2 2006.259.08:13:11.93#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.259.08:13:11.93#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.259.08:13:11.93#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.259.08:13:11.93#ibcon#ireg 7 cls_cnt 0 2006.259.08:13:11.93#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.259.08:13:12.05#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.259.08:13:12.05#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.259.08:13:12.05#ibcon#enter wrdev, iclass 4, count 0 2006.259.08:13:12.05#ibcon#first serial, iclass 4, count 0 2006.259.08:13:12.05#ibcon#enter sib2, iclass 4, count 0 2006.259.08:13:12.05#ibcon#flushed, iclass 4, count 0 2006.259.08:13:12.05#ibcon#about to write, iclass 4, count 0 2006.259.08:13:12.05#ibcon#wrote, iclass 4, count 0 2006.259.08:13:12.05#ibcon#about to read 3, iclass 4, count 0 2006.259.08:13:12.07#ibcon#read 3, iclass 4, count 0 2006.259.08:13:12.07#ibcon#about to read 4, iclass 4, count 0 2006.259.08:13:12.07#ibcon#read 4, iclass 4, count 0 2006.259.08:13:12.07#ibcon#about to read 5, iclass 4, count 0 2006.259.08:13:12.07#ibcon#read 5, iclass 4, count 0 2006.259.08:13:12.07#ibcon#about to read 6, iclass 4, count 0 2006.259.08:13:12.07#ibcon#read 6, iclass 4, count 0 2006.259.08:13:12.07#ibcon#end of sib2, iclass 4, count 0 2006.259.08:13:12.07#ibcon#*mode == 0, iclass 4, count 0 2006.259.08:13:12.07#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.259.08:13:12.07#ibcon#[27=USB\r\n] 2006.259.08:13:12.07#ibcon#*before write, iclass 4, count 0 2006.259.08:13:12.07#ibcon#enter sib2, iclass 4, count 0 2006.259.08:13:12.07#ibcon#flushed, iclass 4, count 0 2006.259.08:13:12.07#ibcon#about to write, iclass 4, count 0 2006.259.08:13:12.07#ibcon#wrote, iclass 4, count 0 2006.259.08:13:12.07#ibcon#about to read 3, iclass 4, count 0 2006.259.08:13:12.10#ibcon#read 3, iclass 4, count 0 2006.259.08:13:12.10#ibcon#about to read 4, iclass 4, count 0 2006.259.08:13:12.10#ibcon#read 4, iclass 4, count 0 2006.259.08:13:12.10#ibcon#about to read 5, iclass 4, count 0 2006.259.08:13:12.10#ibcon#read 5, iclass 4, count 0 2006.259.08:13:12.10#ibcon#about to read 6, iclass 4, count 0 2006.259.08:13:12.10#ibcon#read 6, iclass 4, count 0 2006.259.08:13:12.10#ibcon#end of sib2, iclass 4, count 0 2006.259.08:13:12.10#ibcon#*after write, iclass 4, count 0 2006.259.08:13:12.10#ibcon#*before return 0, iclass 4, count 0 2006.259.08:13:12.10#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.259.08:13:12.10#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.259.08:13:12.10#ibcon#about to clear, iclass 4 cls_cnt 0 2006.259.08:13:12.10#ibcon#cleared, iclass 4 cls_cnt 0 2006.259.08:13:12.10$vc4f8/vblo=3,656.99 2006.259.08:13:12.10#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.259.08:13:12.10#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.259.08:13:12.10#ibcon#ireg 17 cls_cnt 0 2006.259.08:13:12.10#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.259.08:13:12.10#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.259.08:13:12.10#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.259.08:13:12.10#ibcon#enter wrdev, iclass 6, count 0 2006.259.08:13:12.10#ibcon#first serial, iclass 6, count 0 2006.259.08:13:12.10#ibcon#enter sib2, iclass 6, count 0 2006.259.08:13:12.10#ibcon#flushed, iclass 6, count 0 2006.259.08:13:12.10#ibcon#about to write, iclass 6, count 0 2006.259.08:13:12.10#ibcon#wrote, iclass 6, count 0 2006.259.08:13:12.10#ibcon#about to read 3, iclass 6, count 0 2006.259.08:13:12.12#ibcon#read 3, iclass 6, count 0 2006.259.08:13:12.12#ibcon#about to read 4, iclass 6, count 0 2006.259.08:13:12.12#ibcon#read 4, iclass 6, count 0 2006.259.08:13:12.12#ibcon#about to read 5, iclass 6, count 0 2006.259.08:13:12.12#ibcon#read 5, iclass 6, count 0 2006.259.08:13:12.12#ibcon#about to read 6, iclass 6, count 0 2006.259.08:13:12.12#ibcon#read 6, iclass 6, count 0 2006.259.08:13:12.12#ibcon#end of sib2, iclass 6, count 0 2006.259.08:13:12.12#ibcon#*mode == 0, iclass 6, count 0 2006.259.08:13:12.12#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.259.08:13:12.12#ibcon#[28=FRQ=03,656.99\r\n] 2006.259.08:13:12.12#ibcon#*before write, iclass 6, count 0 2006.259.08:13:12.12#ibcon#enter sib2, iclass 6, count 0 2006.259.08:13:12.12#ibcon#flushed, iclass 6, count 0 2006.259.08:13:12.12#ibcon#about to write, iclass 6, count 0 2006.259.08:13:12.12#ibcon#wrote, iclass 6, count 0 2006.259.08:13:12.12#ibcon#about to read 3, iclass 6, count 0 2006.259.08:13:12.16#ibcon#read 3, iclass 6, count 0 2006.259.08:13:12.16#ibcon#about to read 4, iclass 6, count 0 2006.259.08:13:12.16#ibcon#read 4, iclass 6, count 0 2006.259.08:13:12.16#ibcon#about to read 5, iclass 6, count 0 2006.259.08:13:12.16#ibcon#read 5, iclass 6, count 0 2006.259.08:13:12.16#ibcon#about to read 6, iclass 6, count 0 2006.259.08:13:12.16#ibcon#read 6, iclass 6, count 0 2006.259.08:13:12.16#ibcon#end of sib2, iclass 6, count 0 2006.259.08:13:12.16#ibcon#*after write, iclass 6, count 0 2006.259.08:13:12.16#ibcon#*before return 0, iclass 6, count 0 2006.259.08:13:12.16#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.259.08:13:12.16#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.259.08:13:12.16#ibcon#about to clear, iclass 6 cls_cnt 0 2006.259.08:13:12.16#ibcon#cleared, iclass 6 cls_cnt 0 2006.259.08:13:12.16$vc4f8/vb=3,4 2006.259.08:13:12.16#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.259.08:13:12.16#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.259.08:13:12.16#ibcon#ireg 11 cls_cnt 2 2006.259.08:13:12.16#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.259.08:13:12.22#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.259.08:13:12.22#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.259.08:13:12.22#ibcon#enter wrdev, iclass 10, count 2 2006.259.08:13:12.22#ibcon#first serial, iclass 10, count 2 2006.259.08:13:12.22#ibcon#enter sib2, iclass 10, count 2 2006.259.08:13:12.22#ibcon#flushed, iclass 10, count 2 2006.259.08:13:12.22#ibcon#about to write, iclass 10, count 2 2006.259.08:13:12.22#ibcon#wrote, iclass 10, count 2 2006.259.08:13:12.22#ibcon#about to read 3, iclass 10, count 2 2006.259.08:13:12.24#ibcon#read 3, iclass 10, count 2 2006.259.08:13:12.24#ibcon#about to read 4, iclass 10, count 2 2006.259.08:13:12.24#ibcon#read 4, iclass 10, count 2 2006.259.08:13:12.24#ibcon#about to read 5, iclass 10, count 2 2006.259.08:13:12.24#ibcon#read 5, iclass 10, count 2 2006.259.08:13:12.24#ibcon#about to read 6, iclass 10, count 2 2006.259.08:13:12.24#ibcon#read 6, iclass 10, count 2 2006.259.08:13:12.24#ibcon#end of sib2, iclass 10, count 2 2006.259.08:13:12.24#ibcon#*mode == 0, iclass 10, count 2 2006.259.08:13:12.24#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.259.08:13:12.24#ibcon#[27=AT03-04\r\n] 2006.259.08:13:12.24#ibcon#*before write, iclass 10, count 2 2006.259.08:13:12.24#ibcon#enter sib2, iclass 10, count 2 2006.259.08:13:12.24#ibcon#flushed, iclass 10, count 2 2006.259.08:13:12.24#ibcon#about to write, iclass 10, count 2 2006.259.08:13:12.24#ibcon#wrote, iclass 10, count 2 2006.259.08:13:12.24#ibcon#about to read 3, iclass 10, count 2 2006.259.08:13:12.27#ibcon#read 3, iclass 10, count 2 2006.259.08:13:12.27#ibcon#about to read 4, iclass 10, count 2 2006.259.08:13:12.27#ibcon#read 4, iclass 10, count 2 2006.259.08:13:12.27#ibcon#about to read 5, iclass 10, count 2 2006.259.08:13:12.27#ibcon#read 5, iclass 10, count 2 2006.259.08:13:12.27#ibcon#about to read 6, iclass 10, count 2 2006.259.08:13:12.27#ibcon#read 6, iclass 10, count 2 2006.259.08:13:12.27#ibcon#end of sib2, iclass 10, count 2 2006.259.08:13:12.27#ibcon#*after write, iclass 10, count 2 2006.259.08:13:12.27#ibcon#*before return 0, iclass 10, count 2 2006.259.08:13:12.27#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.259.08:13:12.27#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.259.08:13:12.27#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.259.08:13:12.27#ibcon#ireg 7 cls_cnt 0 2006.259.08:13:12.27#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.259.08:13:12.39#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.259.08:13:12.39#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.259.08:13:12.39#ibcon#enter wrdev, iclass 10, count 0 2006.259.08:13:12.39#ibcon#first serial, iclass 10, count 0 2006.259.08:13:12.39#ibcon#enter sib2, iclass 10, count 0 2006.259.08:13:12.39#ibcon#flushed, iclass 10, count 0 2006.259.08:13:12.39#ibcon#about to write, iclass 10, count 0 2006.259.08:13:12.39#ibcon#wrote, iclass 10, count 0 2006.259.08:13:12.39#ibcon#about to read 3, iclass 10, count 0 2006.259.08:13:12.41#ibcon#read 3, iclass 10, count 0 2006.259.08:13:12.41#ibcon#about to read 4, iclass 10, count 0 2006.259.08:13:12.41#ibcon#read 4, iclass 10, count 0 2006.259.08:13:12.41#ibcon#about to read 5, iclass 10, count 0 2006.259.08:13:12.41#ibcon#read 5, iclass 10, count 0 2006.259.08:13:12.41#ibcon#about to read 6, iclass 10, count 0 2006.259.08:13:12.41#ibcon#read 6, iclass 10, count 0 2006.259.08:13:12.41#ibcon#end of sib2, iclass 10, count 0 2006.259.08:13:12.41#ibcon#*mode == 0, iclass 10, count 0 2006.259.08:13:12.41#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.259.08:13:12.41#ibcon#[27=USB\r\n] 2006.259.08:13:12.41#ibcon#*before write, iclass 10, count 0 2006.259.08:13:12.41#ibcon#enter sib2, iclass 10, count 0 2006.259.08:13:12.41#ibcon#flushed, iclass 10, count 0 2006.259.08:13:12.41#ibcon#about to write, iclass 10, count 0 2006.259.08:13:12.41#ibcon#wrote, iclass 10, count 0 2006.259.08:13:12.41#ibcon#about to read 3, iclass 10, count 0 2006.259.08:13:12.44#ibcon#read 3, iclass 10, count 0 2006.259.08:13:12.44#ibcon#about to read 4, iclass 10, count 0 2006.259.08:13:12.44#ibcon#read 4, iclass 10, count 0 2006.259.08:13:12.44#ibcon#about to read 5, iclass 10, count 0 2006.259.08:13:12.44#ibcon#read 5, iclass 10, count 0 2006.259.08:13:12.44#ibcon#about to read 6, iclass 10, count 0 2006.259.08:13:12.44#ibcon#read 6, iclass 10, count 0 2006.259.08:13:12.44#ibcon#end of sib2, iclass 10, count 0 2006.259.08:13:12.44#ibcon#*after write, iclass 10, count 0 2006.259.08:13:12.44#ibcon#*before return 0, iclass 10, count 0 2006.259.08:13:12.44#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.259.08:13:12.44#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.259.08:13:12.44#ibcon#about to clear, iclass 10 cls_cnt 0 2006.259.08:13:12.44#ibcon#cleared, iclass 10 cls_cnt 0 2006.259.08:13:12.44$vc4f8/vblo=4,712.99 2006.259.08:13:12.44#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.259.08:13:12.44#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.259.08:13:12.44#ibcon#ireg 17 cls_cnt 0 2006.259.08:13:12.44#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.259.08:13:12.44#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.259.08:13:12.44#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.259.08:13:12.44#ibcon#enter wrdev, iclass 12, count 0 2006.259.08:13:12.44#ibcon#first serial, iclass 12, count 0 2006.259.08:13:12.44#ibcon#enter sib2, iclass 12, count 0 2006.259.08:13:12.44#ibcon#flushed, iclass 12, count 0 2006.259.08:13:12.44#ibcon#about to write, iclass 12, count 0 2006.259.08:13:12.44#ibcon#wrote, iclass 12, count 0 2006.259.08:13:12.44#ibcon#about to read 3, iclass 12, count 0 2006.259.08:13:12.46#ibcon#read 3, iclass 12, count 0 2006.259.08:13:12.46#ibcon#about to read 4, iclass 12, count 0 2006.259.08:13:12.46#ibcon#read 4, iclass 12, count 0 2006.259.08:13:12.46#ibcon#about to read 5, iclass 12, count 0 2006.259.08:13:12.46#ibcon#read 5, iclass 12, count 0 2006.259.08:13:12.46#ibcon#about to read 6, iclass 12, count 0 2006.259.08:13:12.46#ibcon#read 6, iclass 12, count 0 2006.259.08:13:12.46#ibcon#end of sib2, iclass 12, count 0 2006.259.08:13:12.46#ibcon#*mode == 0, iclass 12, count 0 2006.259.08:13:12.46#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.259.08:13:12.46#ibcon#[28=FRQ=04,712.99\r\n] 2006.259.08:13:12.46#ibcon#*before write, iclass 12, count 0 2006.259.08:13:12.46#ibcon#enter sib2, iclass 12, count 0 2006.259.08:13:12.46#ibcon#flushed, iclass 12, count 0 2006.259.08:13:12.46#ibcon#about to write, iclass 12, count 0 2006.259.08:13:12.46#ibcon#wrote, iclass 12, count 0 2006.259.08:13:12.46#ibcon#about to read 3, iclass 12, count 0 2006.259.08:13:12.50#ibcon#read 3, iclass 12, count 0 2006.259.08:13:12.50#ibcon#about to read 4, iclass 12, count 0 2006.259.08:13:12.50#ibcon#read 4, iclass 12, count 0 2006.259.08:13:12.50#ibcon#about to read 5, iclass 12, count 0 2006.259.08:13:12.50#ibcon#read 5, iclass 12, count 0 2006.259.08:13:12.50#ibcon#about to read 6, iclass 12, count 0 2006.259.08:13:12.50#ibcon#read 6, iclass 12, count 0 2006.259.08:13:12.50#ibcon#end of sib2, iclass 12, count 0 2006.259.08:13:12.50#ibcon#*after write, iclass 12, count 0 2006.259.08:13:12.50#ibcon#*before return 0, iclass 12, count 0 2006.259.08:13:12.50#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.259.08:13:12.50#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.259.08:13:12.50#ibcon#about to clear, iclass 12 cls_cnt 0 2006.259.08:13:12.50#ibcon#cleared, iclass 12 cls_cnt 0 2006.259.08:13:12.50$vc4f8/vb=4,5 2006.259.08:13:12.50#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.259.08:13:12.50#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.259.08:13:12.50#ibcon#ireg 11 cls_cnt 2 2006.259.08:13:12.50#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.259.08:13:12.56#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.259.08:13:12.56#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.259.08:13:12.56#ibcon#enter wrdev, iclass 14, count 2 2006.259.08:13:12.56#ibcon#first serial, iclass 14, count 2 2006.259.08:13:12.56#ibcon#enter sib2, iclass 14, count 2 2006.259.08:13:12.56#ibcon#flushed, iclass 14, count 2 2006.259.08:13:12.56#ibcon#about to write, iclass 14, count 2 2006.259.08:13:12.56#ibcon#wrote, iclass 14, count 2 2006.259.08:13:12.56#ibcon#about to read 3, iclass 14, count 2 2006.259.08:13:12.58#ibcon#read 3, iclass 14, count 2 2006.259.08:13:12.58#ibcon#about to read 4, iclass 14, count 2 2006.259.08:13:12.58#ibcon#read 4, iclass 14, count 2 2006.259.08:13:12.58#ibcon#about to read 5, iclass 14, count 2 2006.259.08:13:12.58#ibcon#read 5, iclass 14, count 2 2006.259.08:13:12.58#ibcon#about to read 6, iclass 14, count 2 2006.259.08:13:12.58#ibcon#read 6, iclass 14, count 2 2006.259.08:13:12.58#ibcon#end of sib2, iclass 14, count 2 2006.259.08:13:12.58#ibcon#*mode == 0, iclass 14, count 2 2006.259.08:13:12.58#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.259.08:13:12.58#ibcon#[27=AT04-05\r\n] 2006.259.08:13:12.58#ibcon#*before write, iclass 14, count 2 2006.259.08:13:12.58#ibcon#enter sib2, iclass 14, count 2 2006.259.08:13:12.58#ibcon#flushed, iclass 14, count 2 2006.259.08:13:12.58#ibcon#about to write, iclass 14, count 2 2006.259.08:13:12.58#ibcon#wrote, iclass 14, count 2 2006.259.08:13:12.58#ibcon#about to read 3, iclass 14, count 2 2006.259.08:13:12.61#ibcon#read 3, iclass 14, count 2 2006.259.08:13:12.61#ibcon#about to read 4, iclass 14, count 2 2006.259.08:13:12.61#ibcon#read 4, iclass 14, count 2 2006.259.08:13:12.61#ibcon#about to read 5, iclass 14, count 2 2006.259.08:13:12.61#ibcon#read 5, iclass 14, count 2 2006.259.08:13:12.61#ibcon#about to read 6, iclass 14, count 2 2006.259.08:13:12.61#ibcon#read 6, iclass 14, count 2 2006.259.08:13:12.61#ibcon#end of sib2, iclass 14, count 2 2006.259.08:13:12.61#ibcon#*after write, iclass 14, count 2 2006.259.08:13:12.61#ibcon#*before return 0, iclass 14, count 2 2006.259.08:13:12.61#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.259.08:13:12.61#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.259.08:13:12.61#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.259.08:13:12.61#ibcon#ireg 7 cls_cnt 0 2006.259.08:13:12.61#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.259.08:13:12.73#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.259.08:13:12.73#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.259.08:13:12.73#ibcon#enter wrdev, iclass 14, count 0 2006.259.08:13:12.73#ibcon#first serial, iclass 14, count 0 2006.259.08:13:12.73#ibcon#enter sib2, iclass 14, count 0 2006.259.08:13:12.73#ibcon#flushed, iclass 14, count 0 2006.259.08:13:12.73#ibcon#about to write, iclass 14, count 0 2006.259.08:13:12.73#ibcon#wrote, iclass 14, count 0 2006.259.08:13:12.73#ibcon#about to read 3, iclass 14, count 0 2006.259.08:13:12.75#ibcon#read 3, iclass 14, count 0 2006.259.08:13:12.75#ibcon#about to read 4, iclass 14, count 0 2006.259.08:13:12.75#ibcon#read 4, iclass 14, count 0 2006.259.08:13:12.75#ibcon#about to read 5, iclass 14, count 0 2006.259.08:13:12.75#ibcon#read 5, iclass 14, count 0 2006.259.08:13:12.75#ibcon#about to read 6, iclass 14, count 0 2006.259.08:13:12.75#ibcon#read 6, iclass 14, count 0 2006.259.08:13:12.75#ibcon#end of sib2, iclass 14, count 0 2006.259.08:13:12.75#ibcon#*mode == 0, iclass 14, count 0 2006.259.08:13:12.75#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.259.08:13:12.75#ibcon#[27=USB\r\n] 2006.259.08:13:12.75#ibcon#*before write, iclass 14, count 0 2006.259.08:13:12.75#ibcon#enter sib2, iclass 14, count 0 2006.259.08:13:12.75#ibcon#flushed, iclass 14, count 0 2006.259.08:13:12.75#ibcon#about to write, iclass 14, count 0 2006.259.08:13:12.75#ibcon#wrote, iclass 14, count 0 2006.259.08:13:12.75#ibcon#about to read 3, iclass 14, count 0 2006.259.08:13:12.78#ibcon#read 3, iclass 14, count 0 2006.259.08:13:12.78#ibcon#about to read 4, iclass 14, count 0 2006.259.08:13:12.78#ibcon#read 4, iclass 14, count 0 2006.259.08:13:12.78#ibcon#about to read 5, iclass 14, count 0 2006.259.08:13:12.78#ibcon#read 5, iclass 14, count 0 2006.259.08:13:12.78#ibcon#about to read 6, iclass 14, count 0 2006.259.08:13:12.78#ibcon#read 6, iclass 14, count 0 2006.259.08:13:12.78#ibcon#end of sib2, iclass 14, count 0 2006.259.08:13:12.78#ibcon#*after write, iclass 14, count 0 2006.259.08:13:12.78#ibcon#*before return 0, iclass 14, count 0 2006.259.08:13:12.78#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.259.08:13:12.78#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.259.08:13:12.78#ibcon#about to clear, iclass 14 cls_cnt 0 2006.259.08:13:12.78#ibcon#cleared, iclass 14 cls_cnt 0 2006.259.08:13:12.78$vc4f8/vblo=5,744.99 2006.259.08:13:12.78#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.259.08:13:12.78#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.259.08:13:12.78#ibcon#ireg 17 cls_cnt 0 2006.259.08:13:12.78#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.259.08:13:12.78#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.259.08:13:12.78#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.259.08:13:12.78#ibcon#enter wrdev, iclass 16, count 0 2006.259.08:13:12.78#ibcon#first serial, iclass 16, count 0 2006.259.08:13:12.78#ibcon#enter sib2, iclass 16, count 0 2006.259.08:13:12.78#ibcon#flushed, iclass 16, count 0 2006.259.08:13:12.78#ibcon#about to write, iclass 16, count 0 2006.259.08:13:12.78#ibcon#wrote, iclass 16, count 0 2006.259.08:13:12.78#ibcon#about to read 3, iclass 16, count 0 2006.259.08:13:12.80#ibcon#read 3, iclass 16, count 0 2006.259.08:13:12.80#ibcon#about to read 4, iclass 16, count 0 2006.259.08:13:12.80#ibcon#read 4, iclass 16, count 0 2006.259.08:13:12.80#ibcon#about to read 5, iclass 16, count 0 2006.259.08:13:12.80#ibcon#read 5, iclass 16, count 0 2006.259.08:13:12.80#ibcon#about to read 6, iclass 16, count 0 2006.259.08:13:12.80#ibcon#read 6, iclass 16, count 0 2006.259.08:13:12.80#ibcon#end of sib2, iclass 16, count 0 2006.259.08:13:12.80#ibcon#*mode == 0, iclass 16, count 0 2006.259.08:13:12.80#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.259.08:13:12.80#ibcon#[28=FRQ=05,744.99\r\n] 2006.259.08:13:12.80#ibcon#*before write, iclass 16, count 0 2006.259.08:13:12.80#ibcon#enter sib2, iclass 16, count 0 2006.259.08:13:12.80#ibcon#flushed, iclass 16, count 0 2006.259.08:13:12.80#ibcon#about to write, iclass 16, count 0 2006.259.08:13:12.80#ibcon#wrote, iclass 16, count 0 2006.259.08:13:12.80#ibcon#about to read 3, iclass 16, count 0 2006.259.08:13:12.84#ibcon#read 3, iclass 16, count 0 2006.259.08:13:12.84#ibcon#about to read 4, iclass 16, count 0 2006.259.08:13:12.84#ibcon#read 4, iclass 16, count 0 2006.259.08:13:12.84#ibcon#about to read 5, iclass 16, count 0 2006.259.08:13:12.84#ibcon#read 5, iclass 16, count 0 2006.259.08:13:12.84#ibcon#about to read 6, iclass 16, count 0 2006.259.08:13:12.84#ibcon#read 6, iclass 16, count 0 2006.259.08:13:12.84#ibcon#end of sib2, iclass 16, count 0 2006.259.08:13:12.84#ibcon#*after write, iclass 16, count 0 2006.259.08:13:12.84#ibcon#*before return 0, iclass 16, count 0 2006.259.08:13:12.84#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.259.08:13:12.84#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.259.08:13:12.84#ibcon#about to clear, iclass 16 cls_cnt 0 2006.259.08:13:12.84#ibcon#cleared, iclass 16 cls_cnt 0 2006.259.08:13:12.84$vc4f8/vb=5,4 2006.259.08:13:12.84#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.259.08:13:12.84#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.259.08:13:12.84#ibcon#ireg 11 cls_cnt 2 2006.259.08:13:12.84#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.259.08:13:12.90#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.259.08:13:12.90#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.259.08:13:12.90#ibcon#enter wrdev, iclass 18, count 2 2006.259.08:13:12.90#ibcon#first serial, iclass 18, count 2 2006.259.08:13:12.90#ibcon#enter sib2, iclass 18, count 2 2006.259.08:13:12.90#ibcon#flushed, iclass 18, count 2 2006.259.08:13:12.90#ibcon#about to write, iclass 18, count 2 2006.259.08:13:12.90#ibcon#wrote, iclass 18, count 2 2006.259.08:13:12.90#ibcon#about to read 3, iclass 18, count 2 2006.259.08:13:12.92#ibcon#read 3, iclass 18, count 2 2006.259.08:13:12.92#ibcon#about to read 4, iclass 18, count 2 2006.259.08:13:12.92#ibcon#read 4, iclass 18, count 2 2006.259.08:13:12.92#ibcon#about to read 5, iclass 18, count 2 2006.259.08:13:12.92#ibcon#read 5, iclass 18, count 2 2006.259.08:13:12.92#ibcon#about to read 6, iclass 18, count 2 2006.259.08:13:12.92#ibcon#read 6, iclass 18, count 2 2006.259.08:13:12.92#ibcon#end of sib2, iclass 18, count 2 2006.259.08:13:12.92#ibcon#*mode == 0, iclass 18, count 2 2006.259.08:13:12.92#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.259.08:13:12.92#ibcon#[27=AT05-04\r\n] 2006.259.08:13:12.92#ibcon#*before write, iclass 18, count 2 2006.259.08:13:12.92#ibcon#enter sib2, iclass 18, count 2 2006.259.08:13:12.92#ibcon#flushed, iclass 18, count 2 2006.259.08:13:12.92#ibcon#about to write, iclass 18, count 2 2006.259.08:13:12.92#ibcon#wrote, iclass 18, count 2 2006.259.08:13:12.92#ibcon#about to read 3, iclass 18, count 2 2006.259.08:13:12.95#ibcon#read 3, iclass 18, count 2 2006.259.08:13:12.95#ibcon#about to read 4, iclass 18, count 2 2006.259.08:13:12.95#ibcon#read 4, iclass 18, count 2 2006.259.08:13:12.95#ibcon#about to read 5, iclass 18, count 2 2006.259.08:13:12.95#ibcon#read 5, iclass 18, count 2 2006.259.08:13:12.95#ibcon#about to read 6, iclass 18, count 2 2006.259.08:13:12.95#ibcon#read 6, iclass 18, count 2 2006.259.08:13:12.95#ibcon#end of sib2, iclass 18, count 2 2006.259.08:13:12.95#ibcon#*after write, iclass 18, count 2 2006.259.08:13:12.95#ibcon#*before return 0, iclass 18, count 2 2006.259.08:13:12.95#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.259.08:13:12.95#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.259.08:13:12.95#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.259.08:13:12.95#ibcon#ireg 7 cls_cnt 0 2006.259.08:13:12.95#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.259.08:13:13.07#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.259.08:13:13.07#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.259.08:13:13.07#ibcon#enter wrdev, iclass 18, count 0 2006.259.08:13:13.07#ibcon#first serial, iclass 18, count 0 2006.259.08:13:13.07#ibcon#enter sib2, iclass 18, count 0 2006.259.08:13:13.07#ibcon#flushed, iclass 18, count 0 2006.259.08:13:13.07#ibcon#about to write, iclass 18, count 0 2006.259.08:13:13.07#ibcon#wrote, iclass 18, count 0 2006.259.08:13:13.07#ibcon#about to read 3, iclass 18, count 0 2006.259.08:13:13.09#ibcon#read 3, iclass 18, count 0 2006.259.08:13:13.09#ibcon#about to read 4, iclass 18, count 0 2006.259.08:13:13.09#ibcon#read 4, iclass 18, count 0 2006.259.08:13:13.09#ibcon#about to read 5, iclass 18, count 0 2006.259.08:13:13.09#ibcon#read 5, iclass 18, count 0 2006.259.08:13:13.09#ibcon#about to read 6, iclass 18, count 0 2006.259.08:13:13.09#ibcon#read 6, iclass 18, count 0 2006.259.08:13:13.09#ibcon#end of sib2, iclass 18, count 0 2006.259.08:13:13.09#ibcon#*mode == 0, iclass 18, count 0 2006.259.08:13:13.09#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.259.08:13:13.09#ibcon#[27=USB\r\n] 2006.259.08:13:13.09#ibcon#*before write, iclass 18, count 0 2006.259.08:13:13.09#ibcon#enter sib2, iclass 18, count 0 2006.259.08:13:13.09#ibcon#flushed, iclass 18, count 0 2006.259.08:13:13.09#ibcon#about to write, iclass 18, count 0 2006.259.08:13:13.09#ibcon#wrote, iclass 18, count 0 2006.259.08:13:13.09#ibcon#about to read 3, iclass 18, count 0 2006.259.08:13:13.12#ibcon#read 3, iclass 18, count 0 2006.259.08:13:13.12#ibcon#about to read 4, iclass 18, count 0 2006.259.08:13:13.12#ibcon#read 4, iclass 18, count 0 2006.259.08:13:13.12#ibcon#about to read 5, iclass 18, count 0 2006.259.08:13:13.12#ibcon#read 5, iclass 18, count 0 2006.259.08:13:13.12#ibcon#about to read 6, iclass 18, count 0 2006.259.08:13:13.12#ibcon#read 6, iclass 18, count 0 2006.259.08:13:13.12#ibcon#end of sib2, iclass 18, count 0 2006.259.08:13:13.12#ibcon#*after write, iclass 18, count 0 2006.259.08:13:13.12#ibcon#*before return 0, iclass 18, count 0 2006.259.08:13:13.12#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.259.08:13:13.12#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.259.08:13:13.12#ibcon#about to clear, iclass 18 cls_cnt 0 2006.259.08:13:13.12#ibcon#cleared, iclass 18 cls_cnt 0 2006.259.08:13:13.12$vc4f8/vblo=6,752.99 2006.259.08:13:13.12#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.259.08:13:13.12#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.259.08:13:13.12#ibcon#ireg 17 cls_cnt 0 2006.259.08:13:13.12#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.259.08:13:13.12#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.259.08:13:13.12#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.259.08:13:13.12#ibcon#enter wrdev, iclass 20, count 0 2006.259.08:13:13.12#ibcon#first serial, iclass 20, count 0 2006.259.08:13:13.12#ibcon#enter sib2, iclass 20, count 0 2006.259.08:13:13.12#ibcon#flushed, iclass 20, count 0 2006.259.08:13:13.12#ibcon#about to write, iclass 20, count 0 2006.259.08:13:13.12#ibcon#wrote, iclass 20, count 0 2006.259.08:13:13.12#ibcon#about to read 3, iclass 20, count 0 2006.259.08:13:13.14#ibcon#read 3, iclass 20, count 0 2006.259.08:13:13.14#ibcon#about to read 4, iclass 20, count 0 2006.259.08:13:13.14#ibcon#read 4, iclass 20, count 0 2006.259.08:13:13.14#ibcon#about to read 5, iclass 20, count 0 2006.259.08:13:13.14#ibcon#read 5, iclass 20, count 0 2006.259.08:13:13.14#ibcon#about to read 6, iclass 20, count 0 2006.259.08:13:13.14#ibcon#read 6, iclass 20, count 0 2006.259.08:13:13.14#ibcon#end of sib2, iclass 20, count 0 2006.259.08:13:13.14#ibcon#*mode == 0, iclass 20, count 0 2006.259.08:13:13.14#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.259.08:13:13.14#ibcon#[28=FRQ=06,752.99\r\n] 2006.259.08:13:13.14#ibcon#*before write, iclass 20, count 0 2006.259.08:13:13.14#ibcon#enter sib2, iclass 20, count 0 2006.259.08:13:13.14#ibcon#flushed, iclass 20, count 0 2006.259.08:13:13.14#ibcon#about to write, iclass 20, count 0 2006.259.08:13:13.14#ibcon#wrote, iclass 20, count 0 2006.259.08:13:13.14#ibcon#about to read 3, iclass 20, count 0 2006.259.08:13:13.18#ibcon#read 3, iclass 20, count 0 2006.259.08:13:13.18#ibcon#about to read 4, iclass 20, count 0 2006.259.08:13:13.18#ibcon#read 4, iclass 20, count 0 2006.259.08:13:13.18#ibcon#about to read 5, iclass 20, count 0 2006.259.08:13:13.18#ibcon#read 5, iclass 20, count 0 2006.259.08:13:13.18#ibcon#about to read 6, iclass 20, count 0 2006.259.08:13:13.18#ibcon#read 6, iclass 20, count 0 2006.259.08:13:13.18#ibcon#end of sib2, iclass 20, count 0 2006.259.08:13:13.18#ibcon#*after write, iclass 20, count 0 2006.259.08:13:13.18#ibcon#*before return 0, iclass 20, count 0 2006.259.08:13:13.18#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.259.08:13:13.18#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.259.08:13:13.18#ibcon#about to clear, iclass 20 cls_cnt 0 2006.259.08:13:13.18#ibcon#cleared, iclass 20 cls_cnt 0 2006.259.08:13:13.18$vc4f8/vb=6,4 2006.259.08:13:13.18#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.259.08:13:13.18#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.259.08:13:13.18#ibcon#ireg 11 cls_cnt 2 2006.259.08:13:13.18#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.259.08:13:13.24#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.259.08:13:13.24#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.259.08:13:13.24#ibcon#enter wrdev, iclass 22, count 2 2006.259.08:13:13.24#ibcon#first serial, iclass 22, count 2 2006.259.08:13:13.24#ibcon#enter sib2, iclass 22, count 2 2006.259.08:13:13.24#ibcon#flushed, iclass 22, count 2 2006.259.08:13:13.24#ibcon#about to write, iclass 22, count 2 2006.259.08:13:13.24#ibcon#wrote, iclass 22, count 2 2006.259.08:13:13.24#ibcon#about to read 3, iclass 22, count 2 2006.259.08:13:13.26#ibcon#read 3, iclass 22, count 2 2006.259.08:13:13.26#ibcon#about to read 4, iclass 22, count 2 2006.259.08:13:13.26#ibcon#read 4, iclass 22, count 2 2006.259.08:13:13.26#ibcon#about to read 5, iclass 22, count 2 2006.259.08:13:13.26#ibcon#read 5, iclass 22, count 2 2006.259.08:13:13.26#ibcon#about to read 6, iclass 22, count 2 2006.259.08:13:13.26#ibcon#read 6, iclass 22, count 2 2006.259.08:13:13.26#ibcon#end of sib2, iclass 22, count 2 2006.259.08:13:13.26#ibcon#*mode == 0, iclass 22, count 2 2006.259.08:13:13.26#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.259.08:13:13.26#ibcon#[27=AT06-04\r\n] 2006.259.08:13:13.26#ibcon#*before write, iclass 22, count 2 2006.259.08:13:13.26#ibcon#enter sib2, iclass 22, count 2 2006.259.08:13:13.26#ibcon#flushed, iclass 22, count 2 2006.259.08:13:13.26#ibcon#about to write, iclass 22, count 2 2006.259.08:13:13.26#ibcon#wrote, iclass 22, count 2 2006.259.08:13:13.26#ibcon#about to read 3, iclass 22, count 2 2006.259.08:13:13.29#ibcon#read 3, iclass 22, count 2 2006.259.08:13:13.29#ibcon#about to read 4, iclass 22, count 2 2006.259.08:13:13.29#ibcon#read 4, iclass 22, count 2 2006.259.08:13:13.29#ibcon#about to read 5, iclass 22, count 2 2006.259.08:13:13.29#ibcon#read 5, iclass 22, count 2 2006.259.08:13:13.29#ibcon#about to read 6, iclass 22, count 2 2006.259.08:13:13.29#ibcon#read 6, iclass 22, count 2 2006.259.08:13:13.29#ibcon#end of sib2, iclass 22, count 2 2006.259.08:13:13.29#ibcon#*after write, iclass 22, count 2 2006.259.08:13:13.29#ibcon#*before return 0, iclass 22, count 2 2006.259.08:13:13.29#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.259.08:13:13.29#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.259.08:13:13.29#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.259.08:13:13.29#ibcon#ireg 7 cls_cnt 0 2006.259.08:13:13.29#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.259.08:13:13.41#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.259.08:13:13.41#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.259.08:13:13.41#ibcon#enter wrdev, iclass 22, count 0 2006.259.08:13:13.41#ibcon#first serial, iclass 22, count 0 2006.259.08:13:13.41#ibcon#enter sib2, iclass 22, count 0 2006.259.08:13:13.41#ibcon#flushed, iclass 22, count 0 2006.259.08:13:13.41#ibcon#about to write, iclass 22, count 0 2006.259.08:13:13.41#ibcon#wrote, iclass 22, count 0 2006.259.08:13:13.41#ibcon#about to read 3, iclass 22, count 0 2006.259.08:13:13.44#ibcon#read 3, iclass 22, count 0 2006.259.08:13:13.44#ibcon#about to read 4, iclass 22, count 0 2006.259.08:13:13.44#ibcon#read 4, iclass 22, count 0 2006.259.08:13:13.44#ibcon#about to read 5, iclass 22, count 0 2006.259.08:13:13.44#ibcon#read 5, iclass 22, count 0 2006.259.08:13:13.44#ibcon#about to read 6, iclass 22, count 0 2006.259.08:13:13.44#ibcon#read 6, iclass 22, count 0 2006.259.08:13:13.44#ibcon#end of sib2, iclass 22, count 0 2006.259.08:13:13.44#ibcon#*mode == 0, iclass 22, count 0 2006.259.08:13:13.44#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.259.08:13:13.44#ibcon#[27=USB\r\n] 2006.259.08:13:13.44#ibcon#*before write, iclass 22, count 0 2006.259.08:13:13.44#ibcon#enter sib2, iclass 22, count 0 2006.259.08:13:13.44#ibcon#flushed, iclass 22, count 0 2006.259.08:13:13.44#ibcon#about to write, iclass 22, count 0 2006.259.08:13:13.44#ibcon#wrote, iclass 22, count 0 2006.259.08:13:13.44#ibcon#about to read 3, iclass 22, count 0 2006.259.08:13:13.47#ibcon#read 3, iclass 22, count 0 2006.259.08:13:13.47#ibcon#about to read 4, iclass 22, count 0 2006.259.08:13:13.47#ibcon#read 4, iclass 22, count 0 2006.259.08:13:13.47#ibcon#about to read 5, iclass 22, count 0 2006.259.08:13:13.47#ibcon#read 5, iclass 22, count 0 2006.259.08:13:13.47#ibcon#about to read 6, iclass 22, count 0 2006.259.08:13:13.47#ibcon#read 6, iclass 22, count 0 2006.259.08:13:13.47#ibcon#end of sib2, iclass 22, count 0 2006.259.08:13:13.47#ibcon#*after write, iclass 22, count 0 2006.259.08:13:13.47#ibcon#*before return 0, iclass 22, count 0 2006.259.08:13:13.47#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.259.08:13:13.47#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.259.08:13:13.47#ibcon#about to clear, iclass 22 cls_cnt 0 2006.259.08:13:13.47#ibcon#cleared, iclass 22 cls_cnt 0 2006.259.08:13:13.47$vc4f8/vabw=wide 2006.259.08:13:13.47#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.259.08:13:13.47#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.259.08:13:13.47#ibcon#ireg 8 cls_cnt 0 2006.259.08:13:13.47#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.259.08:13:13.47#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.259.08:13:13.47#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.259.08:13:13.47#ibcon#enter wrdev, iclass 24, count 0 2006.259.08:13:13.47#ibcon#first serial, iclass 24, count 0 2006.259.08:13:13.47#ibcon#enter sib2, iclass 24, count 0 2006.259.08:13:13.47#ibcon#flushed, iclass 24, count 0 2006.259.08:13:13.47#ibcon#about to write, iclass 24, count 0 2006.259.08:13:13.47#ibcon#wrote, iclass 24, count 0 2006.259.08:13:13.47#ibcon#about to read 3, iclass 24, count 0 2006.259.08:13:13.49#ibcon#read 3, iclass 24, count 0 2006.259.08:13:13.49#ibcon#about to read 4, iclass 24, count 0 2006.259.08:13:13.49#ibcon#read 4, iclass 24, count 0 2006.259.08:13:13.49#ibcon#about to read 5, iclass 24, count 0 2006.259.08:13:13.49#ibcon#read 5, iclass 24, count 0 2006.259.08:13:13.49#ibcon#about to read 6, iclass 24, count 0 2006.259.08:13:13.49#ibcon#read 6, iclass 24, count 0 2006.259.08:13:13.49#ibcon#end of sib2, iclass 24, count 0 2006.259.08:13:13.49#ibcon#*mode == 0, iclass 24, count 0 2006.259.08:13:13.49#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.259.08:13:13.49#ibcon#[25=BW32\r\n] 2006.259.08:13:13.49#ibcon#*before write, iclass 24, count 0 2006.259.08:13:13.49#ibcon#enter sib2, iclass 24, count 0 2006.259.08:13:13.49#ibcon#flushed, iclass 24, count 0 2006.259.08:13:13.49#ibcon#about to write, iclass 24, count 0 2006.259.08:13:13.49#ibcon#wrote, iclass 24, count 0 2006.259.08:13:13.49#ibcon#about to read 3, iclass 24, count 0 2006.259.08:13:13.52#ibcon#read 3, iclass 24, count 0 2006.259.08:13:13.52#ibcon#about to read 4, iclass 24, count 0 2006.259.08:13:13.52#ibcon#read 4, iclass 24, count 0 2006.259.08:13:13.52#ibcon#about to read 5, iclass 24, count 0 2006.259.08:13:13.52#ibcon#read 5, iclass 24, count 0 2006.259.08:13:13.52#ibcon#about to read 6, iclass 24, count 0 2006.259.08:13:13.52#ibcon#read 6, iclass 24, count 0 2006.259.08:13:13.52#ibcon#end of sib2, iclass 24, count 0 2006.259.08:13:13.52#ibcon#*after write, iclass 24, count 0 2006.259.08:13:13.52#ibcon#*before return 0, iclass 24, count 0 2006.259.08:13:13.52#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.259.08:13:13.52#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.259.08:13:13.52#ibcon#about to clear, iclass 24 cls_cnt 0 2006.259.08:13:13.52#ibcon#cleared, iclass 24 cls_cnt 0 2006.259.08:13:13.52$vc4f8/vbbw=wide 2006.259.08:13:13.52#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.259.08:13:13.52#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.259.08:13:13.52#ibcon#ireg 8 cls_cnt 0 2006.259.08:13:13.52#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.259.08:13:13.59#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.259.08:13:13.59#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.259.08:13:13.59#ibcon#enter wrdev, iclass 26, count 0 2006.259.08:13:13.59#ibcon#first serial, iclass 26, count 0 2006.259.08:13:13.59#ibcon#enter sib2, iclass 26, count 0 2006.259.08:13:13.59#ibcon#flushed, iclass 26, count 0 2006.259.08:13:13.59#ibcon#about to write, iclass 26, count 0 2006.259.08:13:13.59#ibcon#wrote, iclass 26, count 0 2006.259.08:13:13.59#ibcon#about to read 3, iclass 26, count 0 2006.259.08:13:13.61#ibcon#read 3, iclass 26, count 0 2006.259.08:13:13.61#ibcon#about to read 4, iclass 26, count 0 2006.259.08:13:13.61#ibcon#read 4, iclass 26, count 0 2006.259.08:13:13.61#ibcon#about to read 5, iclass 26, count 0 2006.259.08:13:13.61#ibcon#read 5, iclass 26, count 0 2006.259.08:13:13.61#ibcon#about to read 6, iclass 26, count 0 2006.259.08:13:13.61#ibcon#read 6, iclass 26, count 0 2006.259.08:13:13.61#ibcon#end of sib2, iclass 26, count 0 2006.259.08:13:13.61#ibcon#*mode == 0, iclass 26, count 0 2006.259.08:13:13.61#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.259.08:13:13.61#ibcon#[27=BW32\r\n] 2006.259.08:13:13.61#ibcon#*before write, iclass 26, count 0 2006.259.08:13:13.61#ibcon#enter sib2, iclass 26, count 0 2006.259.08:13:13.61#ibcon#flushed, iclass 26, count 0 2006.259.08:13:13.61#ibcon#about to write, iclass 26, count 0 2006.259.08:13:13.61#ibcon#wrote, iclass 26, count 0 2006.259.08:13:13.61#ibcon#about to read 3, iclass 26, count 0 2006.259.08:13:13.64#ibcon#read 3, iclass 26, count 0 2006.259.08:13:13.64#ibcon#about to read 4, iclass 26, count 0 2006.259.08:13:13.64#ibcon#read 4, iclass 26, count 0 2006.259.08:13:13.64#ibcon#about to read 5, iclass 26, count 0 2006.259.08:13:13.64#ibcon#read 5, iclass 26, count 0 2006.259.08:13:13.64#ibcon#about to read 6, iclass 26, count 0 2006.259.08:13:13.64#ibcon#read 6, iclass 26, count 0 2006.259.08:13:13.64#ibcon#end of sib2, iclass 26, count 0 2006.259.08:13:13.64#ibcon#*after write, iclass 26, count 0 2006.259.08:13:13.64#ibcon#*before return 0, iclass 26, count 0 2006.259.08:13:13.64#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.259.08:13:13.64#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.259.08:13:13.64#ibcon#about to clear, iclass 26 cls_cnt 0 2006.259.08:13:13.64#ibcon#cleared, iclass 26 cls_cnt 0 2006.259.08:13:13.64$4f8m12a/ifd4f 2006.259.08:13:13.64$ifd4f/lo= 2006.259.08:13:13.64$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.259.08:13:13.64$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.259.08:13:13.64$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.259.08:13:13.64$ifd4f/patch= 2006.259.08:13:13.64$ifd4f/patch=lo1,a1,a2,a3,a4 2006.259.08:13:13.64$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.259.08:13:13.64$ifd4f/patch=lo3,a5,a6,a7,a8 2006.259.08:13:13.64$4f8m12a/"form=m,16.000,1:2 2006.259.08:13:13.64$4f8m12a/"tpicd 2006.259.08:13:13.64$4f8m12a/echo=off 2006.259.08:13:13.64$4f8m12a/xlog=off 2006.259.08:13:13.64:!2006.259.08:13:40 2006.259.08:13:18.13#trakl#Source acquired 2006.259.08:13:19.13#flagr#flagr/antenna,acquired 2006.259.08:13:40.00:preob 2006.259.08:13:41.13/onsource/TRACKING 2006.259.08:13:41.13:!2006.259.08:13:50 2006.259.08:13:50.00:data_valid=on 2006.259.08:13:50.00:midob 2006.259.08:13:50.13/onsource/TRACKING 2006.259.08:13:50.13/wx/21.94,1013.1,86 2006.259.08:13:50.19/cable/+6.4590E-03 2006.259.08:13:51.29/va/01,08,usb,yes,30,32 2006.259.08:13:51.29/va/02,07,usb,yes,30,32 2006.259.08:13:51.29/va/03,08,usb,yes,23,23 2006.259.08:13:51.29/va/04,07,usb,yes,31,34 2006.259.08:13:51.29/va/05,07,usb,yes,35,37 2006.259.08:13:51.29/va/06,06,usb,yes,34,34 2006.259.08:13:51.29/va/07,06,usb,yes,34,34 2006.259.08:13:51.29/va/08,06,usb,yes,37,36 2006.259.08:13:51.52/valo/01,532.99,yes,locked 2006.259.08:13:51.52/valo/02,572.99,yes,locked 2006.259.08:13:51.52/valo/03,672.99,yes,locked 2006.259.08:13:51.52/valo/04,832.99,yes,locked 2006.259.08:13:51.52/valo/05,652.99,yes,locked 2006.259.08:13:51.52/valo/06,772.99,yes,locked 2006.259.08:13:51.52/valo/07,832.99,yes,locked 2006.259.08:13:51.52/valo/08,852.99,yes,locked 2006.259.08:13:52.61/vb/01,04,usb,yes,29,28 2006.259.08:13:52.61/vb/02,05,usb,yes,27,29 2006.259.08:13:52.61/vb/03,04,usb,yes,28,31 2006.259.08:13:52.61/vb/04,05,usb,yes,25,25 2006.259.08:13:52.61/vb/05,04,usb,yes,27,31 2006.259.08:13:52.61/vb/06,04,usb,yes,28,31 2006.259.08:13:52.61/vb/07,04,usb,yes,30,30 2006.259.08:13:52.61/vb/08,04,usb,yes,27,31 2006.259.08:13:52.84/vblo/01,632.99,yes,locked 2006.259.08:13:52.84/vblo/02,640.99,yes,locked 2006.259.08:13:52.84/vblo/03,656.99,yes,locked 2006.259.08:13:52.84/vblo/04,712.99,yes,locked 2006.259.08:13:52.84/vblo/05,744.99,yes,locked 2006.259.08:13:52.84/vblo/06,752.99,yes,locked 2006.259.08:13:52.84/vblo/07,734.99,yes,locked 2006.259.08:13:52.84/vblo/08,744.99,yes,locked 2006.259.08:13:52.99/vabw/8 2006.259.08:13:53.14/vbbw/8 2006.259.08:13:53.23/xfe/off,on,15.5 2006.259.08:13:53.61/ifatt/23,28,28,28 2006.259.08:13:54.07/fmout-gps/S +4.61E-07 2006.259.08:13:54.11:!2006.259.08:14:50 2006.259.08:14:50.00:data_valid=off 2006.259.08:14:50.00:postob 2006.259.08:14:50.20/cable/+6.4588E-03 2006.259.08:14:50.20/wx/21.92,1013.1,86 2006.259.08:14:51.08/fmout-gps/S +4.62E-07 2006.259.08:14:51.08:scan_name=259-0815,k06259,60 2006.259.08:14:51.09:source=0059+581,010245.76,582411.1,2000.0,cw 2006.259.08:14:51.13#flagr#flagr/antenna,new-source 2006.259.08:14:52.13:checkk5 2006.259.08:14:52.56/chk_autoobs//k5ts1/ autoobs is running! 2006.259.08:14:52.95/chk_autoobs//k5ts2/ autoobs is running! 2006.259.08:14:53.35/chk_autoobs//k5ts3/ autoobs is running! 2006.259.08:14:53.74/chk_autoobs//k5ts4/ autoobs is running! 2006.259.08:14:54.20/chk_obsdata//k5ts1/T2590813??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.259.08:14:54.61/chk_obsdata//k5ts2/T2590813??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.259.08:14:55.03/chk_obsdata//k5ts3/T2590813??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.259.08:14:55.43/chk_obsdata//k5ts4/T2590813??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.259.08:14:56.24/k5log//k5ts1_log_newline 2006.259.08:14:57.02/k5log//k5ts2_log_newline 2006.259.08:14:57.82/k5log//k5ts3_log_newline 2006.259.08:14:58.56/k5log//k5ts4_log_newline 2006.259.08:14:58.59/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.259.08:14:58.59:4f8m12a=2 2006.259.08:14:58.59$4f8m12a/echo=on 2006.259.08:14:58.59$4f8m12a/pcalon 2006.259.08:14:58.59$pcalon/"no phase cal control is implemented here 2006.259.08:14:58.59$4f8m12a/"tpicd=stop 2006.259.08:14:58.59$4f8m12a/vc4f8 2006.259.08:14:58.59$vc4f8/valo=1,532.99 2006.259.08:14:58.59#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.259.08:14:58.59#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.259.08:14:58.59#ibcon#ireg 17 cls_cnt 0 2006.259.08:14:58.59#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.259.08:14:58.59#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.259.08:14:58.59#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.259.08:14:58.59#ibcon#enter wrdev, iclass 33, count 0 2006.259.08:14:58.59#ibcon#first serial, iclass 33, count 0 2006.259.08:14:58.59#ibcon#enter sib2, iclass 33, count 0 2006.259.08:14:58.59#ibcon#flushed, iclass 33, count 0 2006.259.08:14:58.59#ibcon#about to write, iclass 33, count 0 2006.259.08:14:58.59#ibcon#wrote, iclass 33, count 0 2006.259.08:14:58.59#ibcon#about to read 3, iclass 33, count 0 2006.259.08:14:58.63#ibcon#read 3, iclass 33, count 0 2006.259.08:14:58.63#ibcon#about to read 4, iclass 33, count 0 2006.259.08:14:58.63#ibcon#read 4, iclass 33, count 0 2006.259.08:14:58.63#ibcon#about to read 5, iclass 33, count 0 2006.259.08:14:58.63#ibcon#read 5, iclass 33, count 0 2006.259.08:14:58.63#ibcon#about to read 6, iclass 33, count 0 2006.259.08:14:58.63#ibcon#read 6, iclass 33, count 0 2006.259.08:14:58.63#ibcon#end of sib2, iclass 33, count 0 2006.259.08:14:58.63#ibcon#*mode == 0, iclass 33, count 0 2006.259.08:14:58.63#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.259.08:14:58.63#ibcon#[26=FRQ=01,532.99\r\n] 2006.259.08:14:58.63#ibcon#*before write, iclass 33, count 0 2006.259.08:14:58.63#ibcon#enter sib2, iclass 33, count 0 2006.259.08:14:58.63#ibcon#flushed, iclass 33, count 0 2006.259.08:14:58.63#ibcon#about to write, iclass 33, count 0 2006.259.08:14:58.63#ibcon#wrote, iclass 33, count 0 2006.259.08:14:58.63#ibcon#about to read 3, iclass 33, count 0 2006.259.08:14:58.68#ibcon#read 3, iclass 33, count 0 2006.259.08:14:58.68#ibcon#about to read 4, iclass 33, count 0 2006.259.08:14:58.68#ibcon#read 4, iclass 33, count 0 2006.259.08:14:58.68#ibcon#about to read 5, iclass 33, count 0 2006.259.08:14:58.68#ibcon#read 5, iclass 33, count 0 2006.259.08:14:58.68#ibcon#about to read 6, iclass 33, count 0 2006.259.08:14:58.68#ibcon#read 6, iclass 33, count 0 2006.259.08:14:58.68#ibcon#end of sib2, iclass 33, count 0 2006.259.08:14:58.68#ibcon#*after write, iclass 33, count 0 2006.259.08:14:58.68#ibcon#*before return 0, iclass 33, count 0 2006.259.08:14:58.68#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.259.08:14:58.68#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.259.08:14:58.68#ibcon#about to clear, iclass 33 cls_cnt 0 2006.259.08:14:58.68#ibcon#cleared, iclass 33 cls_cnt 0 2006.259.08:14:58.68$vc4f8/va=1,8 2006.259.08:14:58.68#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.259.08:14:58.68#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.259.08:14:58.68#ibcon#ireg 11 cls_cnt 2 2006.259.08:14:58.68#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.259.08:14:58.68#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.259.08:14:58.68#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.259.08:14:58.68#ibcon#enter wrdev, iclass 35, count 2 2006.259.08:14:58.68#ibcon#first serial, iclass 35, count 2 2006.259.08:14:58.68#ibcon#enter sib2, iclass 35, count 2 2006.259.08:14:58.68#ibcon#flushed, iclass 35, count 2 2006.259.08:14:58.68#ibcon#about to write, iclass 35, count 2 2006.259.08:14:58.68#ibcon#wrote, iclass 35, count 2 2006.259.08:14:58.68#ibcon#about to read 3, iclass 35, count 2 2006.259.08:14:58.70#ibcon#read 3, iclass 35, count 2 2006.259.08:14:58.70#ibcon#about to read 4, iclass 35, count 2 2006.259.08:14:58.70#ibcon#read 4, iclass 35, count 2 2006.259.08:14:58.70#ibcon#about to read 5, iclass 35, count 2 2006.259.08:14:58.70#ibcon#read 5, iclass 35, count 2 2006.259.08:14:58.70#ibcon#about to read 6, iclass 35, count 2 2006.259.08:14:58.70#ibcon#read 6, iclass 35, count 2 2006.259.08:14:58.70#ibcon#end of sib2, iclass 35, count 2 2006.259.08:14:58.70#ibcon#*mode == 0, iclass 35, count 2 2006.259.08:14:58.70#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.259.08:14:58.70#ibcon#[25=AT01-08\r\n] 2006.259.08:14:58.70#ibcon#*before write, iclass 35, count 2 2006.259.08:14:58.70#ibcon#enter sib2, iclass 35, count 2 2006.259.08:14:58.70#ibcon#flushed, iclass 35, count 2 2006.259.08:14:58.70#ibcon#about to write, iclass 35, count 2 2006.259.08:14:58.70#ibcon#wrote, iclass 35, count 2 2006.259.08:14:58.70#ibcon#about to read 3, iclass 35, count 2 2006.259.08:14:58.73#ibcon#read 3, iclass 35, count 2 2006.259.08:14:58.73#ibcon#about to read 4, iclass 35, count 2 2006.259.08:14:58.73#ibcon#read 4, iclass 35, count 2 2006.259.08:14:58.73#ibcon#about to read 5, iclass 35, count 2 2006.259.08:14:58.73#ibcon#read 5, iclass 35, count 2 2006.259.08:14:58.73#ibcon#about to read 6, iclass 35, count 2 2006.259.08:14:58.73#ibcon#read 6, iclass 35, count 2 2006.259.08:14:58.73#ibcon#end of sib2, iclass 35, count 2 2006.259.08:14:58.73#ibcon#*after write, iclass 35, count 2 2006.259.08:14:58.73#ibcon#*before return 0, iclass 35, count 2 2006.259.08:14:58.73#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.259.08:14:58.73#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.259.08:14:58.73#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.259.08:14:58.73#ibcon#ireg 7 cls_cnt 0 2006.259.08:14:58.73#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.259.08:14:58.85#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.259.08:14:58.85#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.259.08:14:58.85#ibcon#enter wrdev, iclass 35, count 0 2006.259.08:14:58.85#ibcon#first serial, iclass 35, count 0 2006.259.08:14:58.85#ibcon#enter sib2, iclass 35, count 0 2006.259.08:14:58.85#ibcon#flushed, iclass 35, count 0 2006.259.08:14:58.85#ibcon#about to write, iclass 35, count 0 2006.259.08:14:58.85#ibcon#wrote, iclass 35, count 0 2006.259.08:14:58.85#ibcon#about to read 3, iclass 35, count 0 2006.259.08:14:58.87#ibcon#read 3, iclass 35, count 0 2006.259.08:14:58.87#ibcon#about to read 4, iclass 35, count 0 2006.259.08:14:58.87#ibcon#read 4, iclass 35, count 0 2006.259.08:14:58.87#ibcon#about to read 5, iclass 35, count 0 2006.259.08:14:58.87#ibcon#read 5, iclass 35, count 0 2006.259.08:14:58.87#ibcon#about to read 6, iclass 35, count 0 2006.259.08:14:58.87#ibcon#read 6, iclass 35, count 0 2006.259.08:14:58.87#ibcon#end of sib2, iclass 35, count 0 2006.259.08:14:58.87#ibcon#*mode == 0, iclass 35, count 0 2006.259.08:14:58.87#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.259.08:14:58.87#ibcon#[25=USB\r\n] 2006.259.08:14:58.87#ibcon#*before write, iclass 35, count 0 2006.259.08:14:58.87#ibcon#enter sib2, iclass 35, count 0 2006.259.08:14:58.87#ibcon#flushed, iclass 35, count 0 2006.259.08:14:58.87#ibcon#about to write, iclass 35, count 0 2006.259.08:14:58.87#ibcon#wrote, iclass 35, count 0 2006.259.08:14:58.87#ibcon#about to read 3, iclass 35, count 0 2006.259.08:14:58.90#ibcon#read 3, iclass 35, count 0 2006.259.08:14:58.90#ibcon#about to read 4, iclass 35, count 0 2006.259.08:14:58.90#ibcon#read 4, iclass 35, count 0 2006.259.08:14:58.90#ibcon#about to read 5, iclass 35, count 0 2006.259.08:14:58.90#ibcon#read 5, iclass 35, count 0 2006.259.08:14:58.90#ibcon#about to read 6, iclass 35, count 0 2006.259.08:14:58.90#ibcon#read 6, iclass 35, count 0 2006.259.08:14:58.90#ibcon#end of sib2, iclass 35, count 0 2006.259.08:14:58.90#ibcon#*after write, iclass 35, count 0 2006.259.08:14:58.90#ibcon#*before return 0, iclass 35, count 0 2006.259.08:14:58.90#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.259.08:14:58.90#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.259.08:14:58.90#ibcon#about to clear, iclass 35 cls_cnt 0 2006.259.08:14:58.90#ibcon#cleared, iclass 35 cls_cnt 0 2006.259.08:14:58.90$vc4f8/valo=2,572.99 2006.259.08:14:58.90#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.259.08:14:58.90#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.259.08:14:58.90#ibcon#ireg 17 cls_cnt 0 2006.259.08:14:58.90#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.259.08:14:58.90#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.259.08:14:58.90#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.259.08:14:58.90#ibcon#enter wrdev, iclass 37, count 0 2006.259.08:14:58.90#ibcon#first serial, iclass 37, count 0 2006.259.08:14:58.90#ibcon#enter sib2, iclass 37, count 0 2006.259.08:14:58.90#ibcon#flushed, iclass 37, count 0 2006.259.08:14:58.90#ibcon#about to write, iclass 37, count 0 2006.259.08:14:58.90#ibcon#wrote, iclass 37, count 0 2006.259.08:14:58.90#ibcon#about to read 3, iclass 37, count 0 2006.259.08:14:58.92#ibcon#read 3, iclass 37, count 0 2006.259.08:14:58.92#ibcon#about to read 4, iclass 37, count 0 2006.259.08:14:58.92#ibcon#read 4, iclass 37, count 0 2006.259.08:14:58.92#ibcon#about to read 5, iclass 37, count 0 2006.259.08:14:58.92#ibcon#read 5, iclass 37, count 0 2006.259.08:14:58.92#ibcon#about to read 6, iclass 37, count 0 2006.259.08:14:58.92#ibcon#read 6, iclass 37, count 0 2006.259.08:14:58.92#ibcon#end of sib2, iclass 37, count 0 2006.259.08:14:58.92#ibcon#*mode == 0, iclass 37, count 0 2006.259.08:14:58.92#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.259.08:14:58.92#ibcon#[26=FRQ=02,572.99\r\n] 2006.259.08:14:58.92#ibcon#*before write, iclass 37, count 0 2006.259.08:14:58.92#ibcon#enter sib2, iclass 37, count 0 2006.259.08:14:58.92#ibcon#flushed, iclass 37, count 0 2006.259.08:14:58.92#ibcon#about to write, iclass 37, count 0 2006.259.08:14:58.92#ibcon#wrote, iclass 37, count 0 2006.259.08:14:58.92#ibcon#about to read 3, iclass 37, count 0 2006.259.08:14:58.96#ibcon#read 3, iclass 37, count 0 2006.259.08:14:58.96#ibcon#about to read 4, iclass 37, count 0 2006.259.08:14:58.96#ibcon#read 4, iclass 37, count 0 2006.259.08:14:58.96#ibcon#about to read 5, iclass 37, count 0 2006.259.08:14:58.96#ibcon#read 5, iclass 37, count 0 2006.259.08:14:58.96#ibcon#about to read 6, iclass 37, count 0 2006.259.08:14:58.96#ibcon#read 6, iclass 37, count 0 2006.259.08:14:58.96#ibcon#end of sib2, iclass 37, count 0 2006.259.08:14:58.96#ibcon#*after write, iclass 37, count 0 2006.259.08:14:58.96#ibcon#*before return 0, iclass 37, count 0 2006.259.08:14:58.96#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.259.08:14:58.96#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.259.08:14:58.96#ibcon#about to clear, iclass 37 cls_cnt 0 2006.259.08:14:58.96#ibcon#cleared, iclass 37 cls_cnt 0 2006.259.08:14:58.96$vc4f8/va=2,7 2006.259.08:14:58.96#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.259.08:14:58.96#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.259.08:14:58.96#ibcon#ireg 11 cls_cnt 2 2006.259.08:14:58.96#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.259.08:14:59.02#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.259.08:14:59.02#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.259.08:14:59.02#ibcon#enter wrdev, iclass 39, count 2 2006.259.08:14:59.02#ibcon#first serial, iclass 39, count 2 2006.259.08:14:59.02#ibcon#enter sib2, iclass 39, count 2 2006.259.08:14:59.02#ibcon#flushed, iclass 39, count 2 2006.259.08:14:59.02#ibcon#about to write, iclass 39, count 2 2006.259.08:14:59.02#ibcon#wrote, iclass 39, count 2 2006.259.08:14:59.02#ibcon#about to read 3, iclass 39, count 2 2006.259.08:14:59.04#ibcon#read 3, iclass 39, count 2 2006.259.08:14:59.04#ibcon#about to read 4, iclass 39, count 2 2006.259.08:14:59.04#ibcon#read 4, iclass 39, count 2 2006.259.08:14:59.04#ibcon#about to read 5, iclass 39, count 2 2006.259.08:14:59.04#ibcon#read 5, iclass 39, count 2 2006.259.08:14:59.04#ibcon#about to read 6, iclass 39, count 2 2006.259.08:14:59.04#ibcon#read 6, iclass 39, count 2 2006.259.08:14:59.04#ibcon#end of sib2, iclass 39, count 2 2006.259.08:14:59.04#ibcon#*mode == 0, iclass 39, count 2 2006.259.08:14:59.04#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.259.08:14:59.04#ibcon#[25=AT02-07\r\n] 2006.259.08:14:59.04#ibcon#*before write, iclass 39, count 2 2006.259.08:14:59.04#ibcon#enter sib2, iclass 39, count 2 2006.259.08:14:59.04#ibcon#flushed, iclass 39, count 2 2006.259.08:14:59.04#ibcon#about to write, iclass 39, count 2 2006.259.08:14:59.04#ibcon#wrote, iclass 39, count 2 2006.259.08:14:59.04#ibcon#about to read 3, iclass 39, count 2 2006.259.08:14:59.07#ibcon#read 3, iclass 39, count 2 2006.259.08:14:59.07#ibcon#about to read 4, iclass 39, count 2 2006.259.08:14:59.07#ibcon#read 4, iclass 39, count 2 2006.259.08:14:59.07#ibcon#about to read 5, iclass 39, count 2 2006.259.08:14:59.07#ibcon#read 5, iclass 39, count 2 2006.259.08:14:59.07#ibcon#about to read 6, iclass 39, count 2 2006.259.08:14:59.07#ibcon#read 6, iclass 39, count 2 2006.259.08:14:59.07#ibcon#end of sib2, iclass 39, count 2 2006.259.08:14:59.07#ibcon#*after write, iclass 39, count 2 2006.259.08:14:59.07#ibcon#*before return 0, iclass 39, count 2 2006.259.08:14:59.07#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.259.08:14:59.07#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.259.08:14:59.07#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.259.08:14:59.07#ibcon#ireg 7 cls_cnt 0 2006.259.08:14:59.07#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.259.08:14:59.19#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.259.08:14:59.19#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.259.08:14:59.19#ibcon#enter wrdev, iclass 39, count 0 2006.259.08:14:59.19#ibcon#first serial, iclass 39, count 0 2006.259.08:14:59.19#ibcon#enter sib2, iclass 39, count 0 2006.259.08:14:59.19#ibcon#flushed, iclass 39, count 0 2006.259.08:14:59.19#ibcon#about to write, iclass 39, count 0 2006.259.08:14:59.19#ibcon#wrote, iclass 39, count 0 2006.259.08:14:59.19#ibcon#about to read 3, iclass 39, count 0 2006.259.08:14:59.21#ibcon#read 3, iclass 39, count 0 2006.259.08:14:59.21#ibcon#about to read 4, iclass 39, count 0 2006.259.08:14:59.21#ibcon#read 4, iclass 39, count 0 2006.259.08:14:59.21#ibcon#about to read 5, iclass 39, count 0 2006.259.08:14:59.21#ibcon#read 5, iclass 39, count 0 2006.259.08:14:59.21#ibcon#about to read 6, iclass 39, count 0 2006.259.08:14:59.21#ibcon#read 6, iclass 39, count 0 2006.259.08:14:59.21#ibcon#end of sib2, iclass 39, count 0 2006.259.08:14:59.21#ibcon#*mode == 0, iclass 39, count 0 2006.259.08:14:59.21#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.259.08:14:59.21#ibcon#[25=USB\r\n] 2006.259.08:14:59.21#ibcon#*before write, iclass 39, count 0 2006.259.08:14:59.21#ibcon#enter sib2, iclass 39, count 0 2006.259.08:14:59.21#ibcon#flushed, iclass 39, count 0 2006.259.08:14:59.21#ibcon#about to write, iclass 39, count 0 2006.259.08:14:59.21#ibcon#wrote, iclass 39, count 0 2006.259.08:14:59.21#ibcon#about to read 3, iclass 39, count 0 2006.259.08:14:59.24#ibcon#read 3, iclass 39, count 0 2006.259.08:14:59.24#ibcon#about to read 4, iclass 39, count 0 2006.259.08:14:59.24#ibcon#read 4, iclass 39, count 0 2006.259.08:14:59.24#ibcon#about to read 5, iclass 39, count 0 2006.259.08:14:59.24#ibcon#read 5, iclass 39, count 0 2006.259.08:14:59.24#ibcon#about to read 6, iclass 39, count 0 2006.259.08:14:59.24#ibcon#read 6, iclass 39, count 0 2006.259.08:14:59.24#ibcon#end of sib2, iclass 39, count 0 2006.259.08:14:59.24#ibcon#*after write, iclass 39, count 0 2006.259.08:14:59.24#ibcon#*before return 0, iclass 39, count 0 2006.259.08:14:59.24#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.259.08:14:59.24#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.259.08:14:59.24#ibcon#about to clear, iclass 39 cls_cnt 0 2006.259.08:14:59.24#ibcon#cleared, iclass 39 cls_cnt 0 2006.259.08:14:59.24$vc4f8/valo=3,672.99 2006.259.08:14:59.24#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.259.08:14:59.24#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.259.08:14:59.24#ibcon#ireg 17 cls_cnt 0 2006.259.08:14:59.24#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.259.08:14:59.24#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.259.08:14:59.24#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.259.08:14:59.24#ibcon#enter wrdev, iclass 3, count 0 2006.259.08:14:59.24#ibcon#first serial, iclass 3, count 0 2006.259.08:14:59.24#ibcon#enter sib2, iclass 3, count 0 2006.259.08:14:59.24#ibcon#flushed, iclass 3, count 0 2006.259.08:14:59.24#ibcon#about to write, iclass 3, count 0 2006.259.08:14:59.24#ibcon#wrote, iclass 3, count 0 2006.259.08:14:59.24#ibcon#about to read 3, iclass 3, count 0 2006.259.08:14:59.26#ibcon#read 3, iclass 3, count 0 2006.259.08:14:59.26#ibcon#about to read 4, iclass 3, count 0 2006.259.08:14:59.26#ibcon#read 4, iclass 3, count 0 2006.259.08:14:59.26#ibcon#about to read 5, iclass 3, count 0 2006.259.08:14:59.26#ibcon#read 5, iclass 3, count 0 2006.259.08:14:59.26#ibcon#about to read 6, iclass 3, count 0 2006.259.08:14:59.26#ibcon#read 6, iclass 3, count 0 2006.259.08:14:59.26#ibcon#end of sib2, iclass 3, count 0 2006.259.08:14:59.26#ibcon#*mode == 0, iclass 3, count 0 2006.259.08:14:59.26#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.259.08:14:59.26#ibcon#[26=FRQ=03,672.99\r\n] 2006.259.08:14:59.26#ibcon#*before write, iclass 3, count 0 2006.259.08:14:59.26#ibcon#enter sib2, iclass 3, count 0 2006.259.08:14:59.26#ibcon#flushed, iclass 3, count 0 2006.259.08:14:59.26#ibcon#about to write, iclass 3, count 0 2006.259.08:14:59.26#ibcon#wrote, iclass 3, count 0 2006.259.08:14:59.26#ibcon#about to read 3, iclass 3, count 0 2006.259.08:14:59.30#ibcon#read 3, iclass 3, count 0 2006.259.08:14:59.30#ibcon#about to read 4, iclass 3, count 0 2006.259.08:14:59.30#ibcon#read 4, iclass 3, count 0 2006.259.08:14:59.30#ibcon#about to read 5, iclass 3, count 0 2006.259.08:14:59.30#ibcon#read 5, iclass 3, count 0 2006.259.08:14:59.30#ibcon#about to read 6, iclass 3, count 0 2006.259.08:14:59.30#ibcon#read 6, iclass 3, count 0 2006.259.08:14:59.30#ibcon#end of sib2, iclass 3, count 0 2006.259.08:14:59.30#ibcon#*after write, iclass 3, count 0 2006.259.08:14:59.30#ibcon#*before return 0, iclass 3, count 0 2006.259.08:14:59.30#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.259.08:14:59.30#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.259.08:14:59.30#ibcon#about to clear, iclass 3 cls_cnt 0 2006.259.08:14:59.30#ibcon#cleared, iclass 3 cls_cnt 0 2006.259.08:14:59.30$vc4f8/va=3,8 2006.259.08:14:59.30#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.259.08:14:59.30#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.259.08:14:59.30#ibcon#ireg 11 cls_cnt 2 2006.259.08:14:59.30#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.259.08:14:59.36#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.259.08:14:59.36#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.259.08:14:59.36#ibcon#enter wrdev, iclass 5, count 2 2006.259.08:14:59.36#ibcon#first serial, iclass 5, count 2 2006.259.08:14:59.36#ibcon#enter sib2, iclass 5, count 2 2006.259.08:14:59.36#ibcon#flushed, iclass 5, count 2 2006.259.08:14:59.36#ibcon#about to write, iclass 5, count 2 2006.259.08:14:59.36#ibcon#wrote, iclass 5, count 2 2006.259.08:14:59.36#ibcon#about to read 3, iclass 5, count 2 2006.259.08:14:59.38#ibcon#read 3, iclass 5, count 2 2006.259.08:14:59.38#ibcon#about to read 4, iclass 5, count 2 2006.259.08:14:59.38#ibcon#read 4, iclass 5, count 2 2006.259.08:14:59.38#ibcon#about to read 5, iclass 5, count 2 2006.259.08:14:59.38#ibcon#read 5, iclass 5, count 2 2006.259.08:14:59.38#ibcon#about to read 6, iclass 5, count 2 2006.259.08:14:59.38#ibcon#read 6, iclass 5, count 2 2006.259.08:14:59.38#ibcon#end of sib2, iclass 5, count 2 2006.259.08:14:59.38#ibcon#*mode == 0, iclass 5, count 2 2006.259.08:14:59.38#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.259.08:14:59.38#ibcon#[25=AT03-08\r\n] 2006.259.08:14:59.38#ibcon#*before write, iclass 5, count 2 2006.259.08:14:59.38#ibcon#enter sib2, iclass 5, count 2 2006.259.08:14:59.38#ibcon#flushed, iclass 5, count 2 2006.259.08:14:59.38#ibcon#about to write, iclass 5, count 2 2006.259.08:14:59.38#ibcon#wrote, iclass 5, count 2 2006.259.08:14:59.38#ibcon#about to read 3, iclass 5, count 2 2006.259.08:14:59.41#ibcon#read 3, iclass 5, count 2 2006.259.08:14:59.41#ibcon#about to read 4, iclass 5, count 2 2006.259.08:14:59.41#ibcon#read 4, iclass 5, count 2 2006.259.08:14:59.41#ibcon#about to read 5, iclass 5, count 2 2006.259.08:14:59.41#ibcon#read 5, iclass 5, count 2 2006.259.08:14:59.41#ibcon#about to read 6, iclass 5, count 2 2006.259.08:14:59.41#ibcon#read 6, iclass 5, count 2 2006.259.08:14:59.41#ibcon#end of sib2, iclass 5, count 2 2006.259.08:14:59.41#ibcon#*after write, iclass 5, count 2 2006.259.08:14:59.41#ibcon#*before return 0, iclass 5, count 2 2006.259.08:14:59.41#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.259.08:14:59.41#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.259.08:14:59.41#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.259.08:14:59.41#ibcon#ireg 7 cls_cnt 0 2006.259.08:14:59.41#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.259.08:14:59.53#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.259.08:14:59.53#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.259.08:14:59.53#ibcon#enter wrdev, iclass 5, count 0 2006.259.08:14:59.53#ibcon#first serial, iclass 5, count 0 2006.259.08:14:59.53#ibcon#enter sib2, iclass 5, count 0 2006.259.08:14:59.53#ibcon#flushed, iclass 5, count 0 2006.259.08:14:59.53#ibcon#about to write, iclass 5, count 0 2006.259.08:14:59.53#ibcon#wrote, iclass 5, count 0 2006.259.08:14:59.53#ibcon#about to read 3, iclass 5, count 0 2006.259.08:14:59.55#ibcon#read 3, iclass 5, count 0 2006.259.08:14:59.55#ibcon#about to read 4, iclass 5, count 0 2006.259.08:14:59.55#ibcon#read 4, iclass 5, count 0 2006.259.08:14:59.55#ibcon#about to read 5, iclass 5, count 0 2006.259.08:14:59.55#ibcon#read 5, iclass 5, count 0 2006.259.08:14:59.55#ibcon#about to read 6, iclass 5, count 0 2006.259.08:14:59.55#ibcon#read 6, iclass 5, count 0 2006.259.08:14:59.55#ibcon#end of sib2, iclass 5, count 0 2006.259.08:14:59.55#ibcon#*mode == 0, iclass 5, count 0 2006.259.08:14:59.55#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.259.08:14:59.55#ibcon#[25=USB\r\n] 2006.259.08:14:59.55#ibcon#*before write, iclass 5, count 0 2006.259.08:14:59.55#ibcon#enter sib2, iclass 5, count 0 2006.259.08:14:59.55#ibcon#flushed, iclass 5, count 0 2006.259.08:14:59.55#ibcon#about to write, iclass 5, count 0 2006.259.08:14:59.55#ibcon#wrote, iclass 5, count 0 2006.259.08:14:59.55#ibcon#about to read 3, iclass 5, count 0 2006.259.08:14:59.58#ibcon#read 3, iclass 5, count 0 2006.259.08:14:59.58#ibcon#about to read 4, iclass 5, count 0 2006.259.08:14:59.58#ibcon#read 4, iclass 5, count 0 2006.259.08:14:59.58#ibcon#about to read 5, iclass 5, count 0 2006.259.08:14:59.58#ibcon#read 5, iclass 5, count 0 2006.259.08:14:59.58#ibcon#about to read 6, iclass 5, count 0 2006.259.08:14:59.58#ibcon#read 6, iclass 5, count 0 2006.259.08:14:59.58#ibcon#end of sib2, iclass 5, count 0 2006.259.08:14:59.58#ibcon#*after write, iclass 5, count 0 2006.259.08:14:59.58#ibcon#*before return 0, iclass 5, count 0 2006.259.08:14:59.58#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.259.08:14:59.58#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.259.08:14:59.58#ibcon#about to clear, iclass 5 cls_cnt 0 2006.259.08:14:59.58#ibcon#cleared, iclass 5 cls_cnt 0 2006.259.08:14:59.58$vc4f8/valo=4,832.99 2006.259.08:14:59.58#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.259.08:14:59.58#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.259.08:14:59.58#ibcon#ireg 17 cls_cnt 0 2006.259.08:14:59.58#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.259.08:14:59.58#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.259.08:14:59.58#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.259.08:14:59.58#ibcon#enter wrdev, iclass 7, count 0 2006.259.08:14:59.58#ibcon#first serial, iclass 7, count 0 2006.259.08:14:59.58#ibcon#enter sib2, iclass 7, count 0 2006.259.08:14:59.58#ibcon#flushed, iclass 7, count 0 2006.259.08:14:59.58#ibcon#about to write, iclass 7, count 0 2006.259.08:14:59.58#ibcon#wrote, iclass 7, count 0 2006.259.08:14:59.58#ibcon#about to read 3, iclass 7, count 0 2006.259.08:14:59.60#ibcon#read 3, iclass 7, count 0 2006.259.08:14:59.60#ibcon#about to read 4, iclass 7, count 0 2006.259.08:14:59.60#ibcon#read 4, iclass 7, count 0 2006.259.08:14:59.60#ibcon#about to read 5, iclass 7, count 0 2006.259.08:14:59.60#ibcon#read 5, iclass 7, count 0 2006.259.08:14:59.60#ibcon#about to read 6, iclass 7, count 0 2006.259.08:14:59.60#ibcon#read 6, iclass 7, count 0 2006.259.08:14:59.60#ibcon#end of sib2, iclass 7, count 0 2006.259.08:14:59.60#ibcon#*mode == 0, iclass 7, count 0 2006.259.08:14:59.60#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.259.08:14:59.60#ibcon#[26=FRQ=04,832.99\r\n] 2006.259.08:14:59.60#ibcon#*before write, iclass 7, count 0 2006.259.08:14:59.60#ibcon#enter sib2, iclass 7, count 0 2006.259.08:14:59.60#ibcon#flushed, iclass 7, count 0 2006.259.08:14:59.60#ibcon#about to write, iclass 7, count 0 2006.259.08:14:59.60#ibcon#wrote, iclass 7, count 0 2006.259.08:14:59.60#ibcon#about to read 3, iclass 7, count 0 2006.259.08:14:59.64#ibcon#read 3, iclass 7, count 0 2006.259.08:14:59.64#ibcon#about to read 4, iclass 7, count 0 2006.259.08:14:59.64#ibcon#read 4, iclass 7, count 0 2006.259.08:14:59.64#ibcon#about to read 5, iclass 7, count 0 2006.259.08:14:59.64#ibcon#read 5, iclass 7, count 0 2006.259.08:14:59.64#ibcon#about to read 6, iclass 7, count 0 2006.259.08:14:59.64#ibcon#read 6, iclass 7, count 0 2006.259.08:14:59.64#ibcon#end of sib2, iclass 7, count 0 2006.259.08:14:59.64#ibcon#*after write, iclass 7, count 0 2006.259.08:14:59.64#ibcon#*before return 0, iclass 7, count 0 2006.259.08:14:59.64#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.259.08:14:59.64#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.259.08:14:59.64#ibcon#about to clear, iclass 7 cls_cnt 0 2006.259.08:14:59.64#ibcon#cleared, iclass 7 cls_cnt 0 2006.259.08:14:59.64$vc4f8/va=4,7 2006.259.08:14:59.64#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.259.08:14:59.64#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.259.08:14:59.64#ibcon#ireg 11 cls_cnt 2 2006.259.08:14:59.64#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.259.08:14:59.70#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.259.08:14:59.70#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.259.08:14:59.70#ibcon#enter wrdev, iclass 11, count 2 2006.259.08:14:59.70#ibcon#first serial, iclass 11, count 2 2006.259.08:14:59.70#ibcon#enter sib2, iclass 11, count 2 2006.259.08:14:59.70#ibcon#flushed, iclass 11, count 2 2006.259.08:14:59.70#ibcon#about to write, iclass 11, count 2 2006.259.08:14:59.70#ibcon#wrote, iclass 11, count 2 2006.259.08:14:59.70#ibcon#about to read 3, iclass 11, count 2 2006.259.08:14:59.72#ibcon#read 3, iclass 11, count 2 2006.259.08:14:59.72#ibcon#about to read 4, iclass 11, count 2 2006.259.08:14:59.72#ibcon#read 4, iclass 11, count 2 2006.259.08:14:59.72#ibcon#about to read 5, iclass 11, count 2 2006.259.08:14:59.72#ibcon#read 5, iclass 11, count 2 2006.259.08:14:59.72#ibcon#about to read 6, iclass 11, count 2 2006.259.08:14:59.72#ibcon#read 6, iclass 11, count 2 2006.259.08:14:59.72#ibcon#end of sib2, iclass 11, count 2 2006.259.08:14:59.72#ibcon#*mode == 0, iclass 11, count 2 2006.259.08:14:59.72#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.259.08:14:59.72#ibcon#[25=AT04-07\r\n] 2006.259.08:14:59.72#ibcon#*before write, iclass 11, count 2 2006.259.08:14:59.72#ibcon#enter sib2, iclass 11, count 2 2006.259.08:14:59.72#ibcon#flushed, iclass 11, count 2 2006.259.08:14:59.72#ibcon#about to write, iclass 11, count 2 2006.259.08:14:59.72#ibcon#wrote, iclass 11, count 2 2006.259.08:14:59.72#ibcon#about to read 3, iclass 11, count 2 2006.259.08:14:59.75#ibcon#read 3, iclass 11, count 2 2006.259.08:14:59.75#ibcon#about to read 4, iclass 11, count 2 2006.259.08:14:59.75#ibcon#read 4, iclass 11, count 2 2006.259.08:14:59.75#ibcon#about to read 5, iclass 11, count 2 2006.259.08:14:59.75#ibcon#read 5, iclass 11, count 2 2006.259.08:14:59.75#ibcon#about to read 6, iclass 11, count 2 2006.259.08:14:59.75#ibcon#read 6, iclass 11, count 2 2006.259.08:14:59.75#ibcon#end of sib2, iclass 11, count 2 2006.259.08:14:59.75#ibcon#*after write, iclass 11, count 2 2006.259.08:14:59.75#ibcon#*before return 0, iclass 11, count 2 2006.259.08:14:59.75#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.259.08:14:59.75#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.259.08:14:59.75#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.259.08:14:59.75#ibcon#ireg 7 cls_cnt 0 2006.259.08:14:59.75#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.259.08:14:59.87#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.259.08:14:59.87#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.259.08:14:59.87#ibcon#enter wrdev, iclass 11, count 0 2006.259.08:14:59.87#ibcon#first serial, iclass 11, count 0 2006.259.08:14:59.87#ibcon#enter sib2, iclass 11, count 0 2006.259.08:14:59.87#ibcon#flushed, iclass 11, count 0 2006.259.08:14:59.87#ibcon#about to write, iclass 11, count 0 2006.259.08:14:59.87#ibcon#wrote, iclass 11, count 0 2006.259.08:14:59.87#ibcon#about to read 3, iclass 11, count 0 2006.259.08:14:59.89#ibcon#read 3, iclass 11, count 0 2006.259.08:14:59.89#ibcon#about to read 4, iclass 11, count 0 2006.259.08:14:59.89#ibcon#read 4, iclass 11, count 0 2006.259.08:14:59.89#ibcon#about to read 5, iclass 11, count 0 2006.259.08:14:59.89#ibcon#read 5, iclass 11, count 0 2006.259.08:14:59.89#ibcon#about to read 6, iclass 11, count 0 2006.259.08:14:59.89#ibcon#read 6, iclass 11, count 0 2006.259.08:14:59.89#ibcon#end of sib2, iclass 11, count 0 2006.259.08:14:59.89#ibcon#*mode == 0, iclass 11, count 0 2006.259.08:14:59.89#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.259.08:14:59.89#ibcon#[25=USB\r\n] 2006.259.08:14:59.89#ibcon#*before write, iclass 11, count 0 2006.259.08:14:59.89#ibcon#enter sib2, iclass 11, count 0 2006.259.08:14:59.89#ibcon#flushed, iclass 11, count 0 2006.259.08:14:59.89#ibcon#about to write, iclass 11, count 0 2006.259.08:14:59.89#ibcon#wrote, iclass 11, count 0 2006.259.08:14:59.89#ibcon#about to read 3, iclass 11, count 0 2006.259.08:14:59.92#ibcon#read 3, iclass 11, count 0 2006.259.08:14:59.92#ibcon#about to read 4, iclass 11, count 0 2006.259.08:14:59.92#ibcon#read 4, iclass 11, count 0 2006.259.08:14:59.92#ibcon#about to read 5, iclass 11, count 0 2006.259.08:14:59.92#ibcon#read 5, iclass 11, count 0 2006.259.08:14:59.92#ibcon#about to read 6, iclass 11, count 0 2006.259.08:14:59.92#ibcon#read 6, iclass 11, count 0 2006.259.08:14:59.92#ibcon#end of sib2, iclass 11, count 0 2006.259.08:14:59.92#ibcon#*after write, iclass 11, count 0 2006.259.08:14:59.92#ibcon#*before return 0, iclass 11, count 0 2006.259.08:14:59.92#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.259.08:14:59.92#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.259.08:14:59.92#ibcon#about to clear, iclass 11 cls_cnt 0 2006.259.08:14:59.92#ibcon#cleared, iclass 11 cls_cnt 0 2006.259.08:14:59.92$vc4f8/valo=5,652.99 2006.259.08:14:59.92#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.259.08:14:59.92#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.259.08:14:59.92#ibcon#ireg 17 cls_cnt 0 2006.259.08:14:59.92#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.259.08:14:59.92#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.259.08:14:59.92#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.259.08:14:59.92#ibcon#enter wrdev, iclass 13, count 0 2006.259.08:14:59.92#ibcon#first serial, iclass 13, count 0 2006.259.08:14:59.92#ibcon#enter sib2, iclass 13, count 0 2006.259.08:14:59.92#ibcon#flushed, iclass 13, count 0 2006.259.08:14:59.92#ibcon#about to write, iclass 13, count 0 2006.259.08:14:59.92#ibcon#wrote, iclass 13, count 0 2006.259.08:14:59.92#ibcon#about to read 3, iclass 13, count 0 2006.259.08:14:59.94#ibcon#read 3, iclass 13, count 0 2006.259.08:14:59.94#ibcon#about to read 4, iclass 13, count 0 2006.259.08:14:59.94#ibcon#read 4, iclass 13, count 0 2006.259.08:14:59.94#ibcon#about to read 5, iclass 13, count 0 2006.259.08:14:59.94#ibcon#read 5, iclass 13, count 0 2006.259.08:14:59.94#ibcon#about to read 6, iclass 13, count 0 2006.259.08:14:59.94#ibcon#read 6, iclass 13, count 0 2006.259.08:14:59.94#ibcon#end of sib2, iclass 13, count 0 2006.259.08:14:59.94#ibcon#*mode == 0, iclass 13, count 0 2006.259.08:14:59.94#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.259.08:14:59.94#ibcon#[26=FRQ=05,652.99\r\n] 2006.259.08:14:59.94#ibcon#*before write, iclass 13, count 0 2006.259.08:14:59.94#ibcon#enter sib2, iclass 13, count 0 2006.259.08:14:59.94#ibcon#flushed, iclass 13, count 0 2006.259.08:14:59.94#ibcon#about to write, iclass 13, count 0 2006.259.08:14:59.94#ibcon#wrote, iclass 13, count 0 2006.259.08:14:59.94#ibcon#about to read 3, iclass 13, count 0 2006.259.08:14:59.98#ibcon#read 3, iclass 13, count 0 2006.259.08:14:59.98#ibcon#about to read 4, iclass 13, count 0 2006.259.08:14:59.98#ibcon#read 4, iclass 13, count 0 2006.259.08:14:59.98#ibcon#about to read 5, iclass 13, count 0 2006.259.08:14:59.98#ibcon#read 5, iclass 13, count 0 2006.259.08:14:59.98#ibcon#about to read 6, iclass 13, count 0 2006.259.08:14:59.98#ibcon#read 6, iclass 13, count 0 2006.259.08:14:59.98#ibcon#end of sib2, iclass 13, count 0 2006.259.08:14:59.98#ibcon#*after write, iclass 13, count 0 2006.259.08:14:59.98#ibcon#*before return 0, iclass 13, count 0 2006.259.08:14:59.98#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.259.08:14:59.98#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.259.08:14:59.98#ibcon#about to clear, iclass 13 cls_cnt 0 2006.259.08:14:59.98#ibcon#cleared, iclass 13 cls_cnt 0 2006.259.08:14:59.98$vc4f8/va=5,7 2006.259.08:14:59.98#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.259.08:14:59.98#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.259.08:14:59.98#ibcon#ireg 11 cls_cnt 2 2006.259.08:14:59.98#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.259.08:15:00.04#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.259.08:15:00.04#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.259.08:15:00.04#ibcon#enter wrdev, iclass 15, count 2 2006.259.08:15:00.04#ibcon#first serial, iclass 15, count 2 2006.259.08:15:00.04#ibcon#enter sib2, iclass 15, count 2 2006.259.08:15:00.04#ibcon#flushed, iclass 15, count 2 2006.259.08:15:00.04#ibcon#about to write, iclass 15, count 2 2006.259.08:15:00.04#ibcon#wrote, iclass 15, count 2 2006.259.08:15:00.04#ibcon#about to read 3, iclass 15, count 2 2006.259.08:15:00.06#ibcon#read 3, iclass 15, count 2 2006.259.08:15:00.06#ibcon#about to read 4, iclass 15, count 2 2006.259.08:15:00.06#ibcon#read 4, iclass 15, count 2 2006.259.08:15:00.06#ibcon#about to read 5, iclass 15, count 2 2006.259.08:15:00.06#ibcon#read 5, iclass 15, count 2 2006.259.08:15:00.06#ibcon#about to read 6, iclass 15, count 2 2006.259.08:15:00.06#ibcon#read 6, iclass 15, count 2 2006.259.08:15:00.06#ibcon#end of sib2, iclass 15, count 2 2006.259.08:15:00.06#ibcon#*mode == 0, iclass 15, count 2 2006.259.08:15:00.06#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.259.08:15:00.06#ibcon#[25=AT05-07\r\n] 2006.259.08:15:00.06#ibcon#*before write, iclass 15, count 2 2006.259.08:15:00.06#ibcon#enter sib2, iclass 15, count 2 2006.259.08:15:00.06#ibcon#flushed, iclass 15, count 2 2006.259.08:15:00.06#ibcon#about to write, iclass 15, count 2 2006.259.08:15:00.06#ibcon#wrote, iclass 15, count 2 2006.259.08:15:00.06#ibcon#about to read 3, iclass 15, count 2 2006.259.08:15:00.09#ibcon#read 3, iclass 15, count 2 2006.259.08:15:00.09#ibcon#about to read 4, iclass 15, count 2 2006.259.08:15:00.09#ibcon#read 4, iclass 15, count 2 2006.259.08:15:00.09#ibcon#about to read 5, iclass 15, count 2 2006.259.08:15:00.09#ibcon#read 5, iclass 15, count 2 2006.259.08:15:00.09#ibcon#about to read 6, iclass 15, count 2 2006.259.08:15:00.09#ibcon#read 6, iclass 15, count 2 2006.259.08:15:00.09#ibcon#end of sib2, iclass 15, count 2 2006.259.08:15:00.09#ibcon#*after write, iclass 15, count 2 2006.259.08:15:00.09#ibcon#*before return 0, iclass 15, count 2 2006.259.08:15:00.09#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.259.08:15:00.09#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.259.08:15:00.09#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.259.08:15:00.09#ibcon#ireg 7 cls_cnt 0 2006.259.08:15:00.09#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.259.08:15:00.21#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.259.08:15:00.21#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.259.08:15:00.21#ibcon#enter wrdev, iclass 15, count 0 2006.259.08:15:00.21#ibcon#first serial, iclass 15, count 0 2006.259.08:15:00.21#ibcon#enter sib2, iclass 15, count 0 2006.259.08:15:00.21#ibcon#flushed, iclass 15, count 0 2006.259.08:15:00.21#ibcon#about to write, iclass 15, count 0 2006.259.08:15:00.21#ibcon#wrote, iclass 15, count 0 2006.259.08:15:00.21#ibcon#about to read 3, iclass 15, count 0 2006.259.08:15:00.23#ibcon#read 3, iclass 15, count 0 2006.259.08:15:00.23#ibcon#about to read 4, iclass 15, count 0 2006.259.08:15:00.23#ibcon#read 4, iclass 15, count 0 2006.259.08:15:00.23#ibcon#about to read 5, iclass 15, count 0 2006.259.08:15:00.23#ibcon#read 5, iclass 15, count 0 2006.259.08:15:00.23#ibcon#about to read 6, iclass 15, count 0 2006.259.08:15:00.23#ibcon#read 6, iclass 15, count 0 2006.259.08:15:00.23#ibcon#end of sib2, iclass 15, count 0 2006.259.08:15:00.23#ibcon#*mode == 0, iclass 15, count 0 2006.259.08:15:00.23#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.259.08:15:00.23#ibcon#[25=USB\r\n] 2006.259.08:15:00.23#ibcon#*before write, iclass 15, count 0 2006.259.08:15:00.23#ibcon#enter sib2, iclass 15, count 0 2006.259.08:15:00.23#ibcon#flushed, iclass 15, count 0 2006.259.08:15:00.23#ibcon#about to write, iclass 15, count 0 2006.259.08:15:00.23#ibcon#wrote, iclass 15, count 0 2006.259.08:15:00.23#ibcon#about to read 3, iclass 15, count 0 2006.259.08:15:00.26#ibcon#read 3, iclass 15, count 0 2006.259.08:15:00.26#ibcon#about to read 4, iclass 15, count 0 2006.259.08:15:00.26#ibcon#read 4, iclass 15, count 0 2006.259.08:15:00.26#ibcon#about to read 5, iclass 15, count 0 2006.259.08:15:00.26#ibcon#read 5, iclass 15, count 0 2006.259.08:15:00.26#ibcon#about to read 6, iclass 15, count 0 2006.259.08:15:00.26#ibcon#read 6, iclass 15, count 0 2006.259.08:15:00.26#ibcon#end of sib2, iclass 15, count 0 2006.259.08:15:00.26#ibcon#*after write, iclass 15, count 0 2006.259.08:15:00.26#ibcon#*before return 0, iclass 15, count 0 2006.259.08:15:00.26#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.259.08:15:00.26#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.259.08:15:00.26#ibcon#about to clear, iclass 15 cls_cnt 0 2006.259.08:15:00.26#ibcon#cleared, iclass 15 cls_cnt 0 2006.259.08:15:00.26$vc4f8/valo=6,772.99 2006.259.08:15:00.26#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.259.08:15:00.26#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.259.08:15:00.26#ibcon#ireg 17 cls_cnt 0 2006.259.08:15:00.26#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.259.08:15:00.26#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.259.08:15:00.26#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.259.08:15:00.26#ibcon#enter wrdev, iclass 17, count 0 2006.259.08:15:00.26#ibcon#first serial, iclass 17, count 0 2006.259.08:15:00.26#ibcon#enter sib2, iclass 17, count 0 2006.259.08:15:00.26#ibcon#flushed, iclass 17, count 0 2006.259.08:15:00.26#ibcon#about to write, iclass 17, count 0 2006.259.08:15:00.26#ibcon#wrote, iclass 17, count 0 2006.259.08:15:00.26#ibcon#about to read 3, iclass 17, count 0 2006.259.08:15:00.28#ibcon#read 3, iclass 17, count 0 2006.259.08:15:00.28#ibcon#about to read 4, iclass 17, count 0 2006.259.08:15:00.28#ibcon#read 4, iclass 17, count 0 2006.259.08:15:00.28#ibcon#about to read 5, iclass 17, count 0 2006.259.08:15:00.28#ibcon#read 5, iclass 17, count 0 2006.259.08:15:00.28#ibcon#about to read 6, iclass 17, count 0 2006.259.08:15:00.28#ibcon#read 6, iclass 17, count 0 2006.259.08:15:00.28#ibcon#end of sib2, iclass 17, count 0 2006.259.08:15:00.28#ibcon#*mode == 0, iclass 17, count 0 2006.259.08:15:00.28#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.259.08:15:00.28#ibcon#[26=FRQ=06,772.99\r\n] 2006.259.08:15:00.28#ibcon#*before write, iclass 17, count 0 2006.259.08:15:00.28#ibcon#enter sib2, iclass 17, count 0 2006.259.08:15:00.28#ibcon#flushed, iclass 17, count 0 2006.259.08:15:00.28#ibcon#about to write, iclass 17, count 0 2006.259.08:15:00.28#ibcon#wrote, iclass 17, count 0 2006.259.08:15:00.28#ibcon#about to read 3, iclass 17, count 0 2006.259.08:15:00.32#ibcon#read 3, iclass 17, count 0 2006.259.08:15:00.32#ibcon#about to read 4, iclass 17, count 0 2006.259.08:15:00.32#ibcon#read 4, iclass 17, count 0 2006.259.08:15:00.32#ibcon#about to read 5, iclass 17, count 0 2006.259.08:15:00.32#ibcon#read 5, iclass 17, count 0 2006.259.08:15:00.32#ibcon#about to read 6, iclass 17, count 0 2006.259.08:15:00.32#ibcon#read 6, iclass 17, count 0 2006.259.08:15:00.32#ibcon#end of sib2, iclass 17, count 0 2006.259.08:15:00.32#ibcon#*after write, iclass 17, count 0 2006.259.08:15:00.32#ibcon#*before return 0, iclass 17, count 0 2006.259.08:15:00.32#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.259.08:15:00.32#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.259.08:15:00.32#ibcon#about to clear, iclass 17 cls_cnt 0 2006.259.08:15:00.32#ibcon#cleared, iclass 17 cls_cnt 0 2006.259.08:15:00.32$vc4f8/va=6,6 2006.259.08:15:00.32#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.259.08:15:00.32#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.259.08:15:00.32#ibcon#ireg 11 cls_cnt 2 2006.259.08:15:00.32#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.259.08:15:00.38#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.259.08:15:00.38#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.259.08:15:00.38#ibcon#enter wrdev, iclass 19, count 2 2006.259.08:15:00.38#ibcon#first serial, iclass 19, count 2 2006.259.08:15:00.38#ibcon#enter sib2, iclass 19, count 2 2006.259.08:15:00.38#ibcon#flushed, iclass 19, count 2 2006.259.08:15:00.38#ibcon#about to write, iclass 19, count 2 2006.259.08:15:00.38#ibcon#wrote, iclass 19, count 2 2006.259.08:15:00.38#ibcon#about to read 3, iclass 19, count 2 2006.259.08:15:00.40#ibcon#read 3, iclass 19, count 2 2006.259.08:15:00.40#ibcon#about to read 4, iclass 19, count 2 2006.259.08:15:00.40#ibcon#read 4, iclass 19, count 2 2006.259.08:15:00.40#ibcon#about to read 5, iclass 19, count 2 2006.259.08:15:00.40#ibcon#read 5, iclass 19, count 2 2006.259.08:15:00.40#ibcon#about to read 6, iclass 19, count 2 2006.259.08:15:00.40#ibcon#read 6, iclass 19, count 2 2006.259.08:15:00.40#ibcon#end of sib2, iclass 19, count 2 2006.259.08:15:00.40#ibcon#*mode == 0, iclass 19, count 2 2006.259.08:15:00.40#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.259.08:15:00.40#ibcon#[25=AT06-06\r\n] 2006.259.08:15:00.40#ibcon#*before write, iclass 19, count 2 2006.259.08:15:00.40#ibcon#enter sib2, iclass 19, count 2 2006.259.08:15:00.40#ibcon#flushed, iclass 19, count 2 2006.259.08:15:00.40#ibcon#about to write, iclass 19, count 2 2006.259.08:15:00.40#ibcon#wrote, iclass 19, count 2 2006.259.08:15:00.40#ibcon#about to read 3, iclass 19, count 2 2006.259.08:15:00.43#ibcon#read 3, iclass 19, count 2 2006.259.08:15:00.43#ibcon#about to read 4, iclass 19, count 2 2006.259.08:15:00.43#ibcon#read 4, iclass 19, count 2 2006.259.08:15:00.43#ibcon#about to read 5, iclass 19, count 2 2006.259.08:15:00.43#ibcon#read 5, iclass 19, count 2 2006.259.08:15:00.43#ibcon#about to read 6, iclass 19, count 2 2006.259.08:15:00.43#ibcon#read 6, iclass 19, count 2 2006.259.08:15:00.43#ibcon#end of sib2, iclass 19, count 2 2006.259.08:15:00.43#ibcon#*after write, iclass 19, count 2 2006.259.08:15:00.43#ibcon#*before return 0, iclass 19, count 2 2006.259.08:15:00.43#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.259.08:15:00.43#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.259.08:15:00.43#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.259.08:15:00.43#ibcon#ireg 7 cls_cnt 0 2006.259.08:15:00.43#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.259.08:15:00.55#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.259.08:15:00.55#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.259.08:15:00.55#ibcon#enter wrdev, iclass 19, count 0 2006.259.08:15:00.55#ibcon#first serial, iclass 19, count 0 2006.259.08:15:00.55#ibcon#enter sib2, iclass 19, count 0 2006.259.08:15:00.55#ibcon#flushed, iclass 19, count 0 2006.259.08:15:00.55#ibcon#about to write, iclass 19, count 0 2006.259.08:15:00.55#ibcon#wrote, iclass 19, count 0 2006.259.08:15:00.55#ibcon#about to read 3, iclass 19, count 0 2006.259.08:15:00.57#ibcon#read 3, iclass 19, count 0 2006.259.08:15:00.57#ibcon#about to read 4, iclass 19, count 0 2006.259.08:15:00.57#ibcon#read 4, iclass 19, count 0 2006.259.08:15:00.57#ibcon#about to read 5, iclass 19, count 0 2006.259.08:15:00.57#ibcon#read 5, iclass 19, count 0 2006.259.08:15:00.57#ibcon#about to read 6, iclass 19, count 0 2006.259.08:15:00.57#ibcon#read 6, iclass 19, count 0 2006.259.08:15:00.57#ibcon#end of sib2, iclass 19, count 0 2006.259.08:15:00.57#ibcon#*mode == 0, iclass 19, count 0 2006.259.08:15:00.57#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.259.08:15:00.57#ibcon#[25=USB\r\n] 2006.259.08:15:00.57#ibcon#*before write, iclass 19, count 0 2006.259.08:15:00.57#ibcon#enter sib2, iclass 19, count 0 2006.259.08:15:00.57#ibcon#flushed, iclass 19, count 0 2006.259.08:15:00.57#ibcon#about to write, iclass 19, count 0 2006.259.08:15:00.57#ibcon#wrote, iclass 19, count 0 2006.259.08:15:00.57#ibcon#about to read 3, iclass 19, count 0 2006.259.08:15:00.60#ibcon#read 3, iclass 19, count 0 2006.259.08:15:00.60#ibcon#about to read 4, iclass 19, count 0 2006.259.08:15:00.60#ibcon#read 4, iclass 19, count 0 2006.259.08:15:00.60#ibcon#about to read 5, iclass 19, count 0 2006.259.08:15:00.60#ibcon#read 5, iclass 19, count 0 2006.259.08:15:00.60#ibcon#about to read 6, iclass 19, count 0 2006.259.08:15:00.60#ibcon#read 6, iclass 19, count 0 2006.259.08:15:00.60#ibcon#end of sib2, iclass 19, count 0 2006.259.08:15:00.60#ibcon#*after write, iclass 19, count 0 2006.259.08:15:00.60#ibcon#*before return 0, iclass 19, count 0 2006.259.08:15:00.60#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.259.08:15:00.60#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.259.08:15:00.60#ibcon#about to clear, iclass 19 cls_cnt 0 2006.259.08:15:00.60#ibcon#cleared, iclass 19 cls_cnt 0 2006.259.08:15:00.60$vc4f8/valo=7,832.99 2006.259.08:15:00.60#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.259.08:15:00.60#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.259.08:15:00.60#ibcon#ireg 17 cls_cnt 0 2006.259.08:15:00.60#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.259.08:15:00.60#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.259.08:15:00.60#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.259.08:15:00.60#ibcon#enter wrdev, iclass 21, count 0 2006.259.08:15:00.60#ibcon#first serial, iclass 21, count 0 2006.259.08:15:00.60#ibcon#enter sib2, iclass 21, count 0 2006.259.08:15:00.60#ibcon#flushed, iclass 21, count 0 2006.259.08:15:00.60#ibcon#about to write, iclass 21, count 0 2006.259.08:15:00.60#ibcon#wrote, iclass 21, count 0 2006.259.08:15:00.60#ibcon#about to read 3, iclass 21, count 0 2006.259.08:15:00.62#ibcon#read 3, iclass 21, count 0 2006.259.08:15:00.62#ibcon#about to read 4, iclass 21, count 0 2006.259.08:15:00.62#ibcon#read 4, iclass 21, count 0 2006.259.08:15:00.62#ibcon#about to read 5, iclass 21, count 0 2006.259.08:15:00.62#ibcon#read 5, iclass 21, count 0 2006.259.08:15:00.62#ibcon#about to read 6, iclass 21, count 0 2006.259.08:15:00.62#ibcon#read 6, iclass 21, count 0 2006.259.08:15:00.62#ibcon#end of sib2, iclass 21, count 0 2006.259.08:15:00.62#ibcon#*mode == 0, iclass 21, count 0 2006.259.08:15:00.62#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.259.08:15:00.62#ibcon#[26=FRQ=07,832.99\r\n] 2006.259.08:15:00.62#ibcon#*before write, iclass 21, count 0 2006.259.08:15:00.62#ibcon#enter sib2, iclass 21, count 0 2006.259.08:15:00.62#ibcon#flushed, iclass 21, count 0 2006.259.08:15:00.62#ibcon#about to write, iclass 21, count 0 2006.259.08:15:00.62#ibcon#wrote, iclass 21, count 0 2006.259.08:15:00.62#ibcon#about to read 3, iclass 21, count 0 2006.259.08:15:00.66#ibcon#read 3, iclass 21, count 0 2006.259.08:15:00.66#ibcon#about to read 4, iclass 21, count 0 2006.259.08:15:00.66#ibcon#read 4, iclass 21, count 0 2006.259.08:15:00.66#ibcon#about to read 5, iclass 21, count 0 2006.259.08:15:00.66#ibcon#read 5, iclass 21, count 0 2006.259.08:15:00.66#ibcon#about to read 6, iclass 21, count 0 2006.259.08:15:00.66#ibcon#read 6, iclass 21, count 0 2006.259.08:15:00.66#ibcon#end of sib2, iclass 21, count 0 2006.259.08:15:00.66#ibcon#*after write, iclass 21, count 0 2006.259.08:15:00.66#ibcon#*before return 0, iclass 21, count 0 2006.259.08:15:00.66#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.259.08:15:00.66#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.259.08:15:00.66#ibcon#about to clear, iclass 21 cls_cnt 0 2006.259.08:15:00.66#ibcon#cleared, iclass 21 cls_cnt 0 2006.259.08:15:00.66$vc4f8/va=7,6 2006.259.08:15:00.66#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.259.08:15:00.66#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.259.08:15:00.66#ibcon#ireg 11 cls_cnt 2 2006.259.08:15:00.66#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.259.08:15:00.72#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.259.08:15:00.72#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.259.08:15:00.72#ibcon#enter wrdev, iclass 23, count 2 2006.259.08:15:00.72#ibcon#first serial, iclass 23, count 2 2006.259.08:15:00.72#ibcon#enter sib2, iclass 23, count 2 2006.259.08:15:00.72#ibcon#flushed, iclass 23, count 2 2006.259.08:15:00.72#ibcon#about to write, iclass 23, count 2 2006.259.08:15:00.72#ibcon#wrote, iclass 23, count 2 2006.259.08:15:00.72#ibcon#about to read 3, iclass 23, count 2 2006.259.08:15:00.74#ibcon#read 3, iclass 23, count 2 2006.259.08:15:00.74#ibcon#about to read 4, iclass 23, count 2 2006.259.08:15:00.74#ibcon#read 4, iclass 23, count 2 2006.259.08:15:00.74#ibcon#about to read 5, iclass 23, count 2 2006.259.08:15:00.74#ibcon#read 5, iclass 23, count 2 2006.259.08:15:00.74#ibcon#about to read 6, iclass 23, count 2 2006.259.08:15:00.74#ibcon#read 6, iclass 23, count 2 2006.259.08:15:00.74#ibcon#end of sib2, iclass 23, count 2 2006.259.08:15:00.74#ibcon#*mode == 0, iclass 23, count 2 2006.259.08:15:00.74#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.259.08:15:00.74#ibcon#[25=AT07-06\r\n] 2006.259.08:15:00.74#ibcon#*before write, iclass 23, count 2 2006.259.08:15:00.74#ibcon#enter sib2, iclass 23, count 2 2006.259.08:15:00.74#ibcon#flushed, iclass 23, count 2 2006.259.08:15:00.74#ibcon#about to write, iclass 23, count 2 2006.259.08:15:00.74#ibcon#wrote, iclass 23, count 2 2006.259.08:15:00.74#ibcon#about to read 3, iclass 23, count 2 2006.259.08:15:00.77#ibcon#read 3, iclass 23, count 2 2006.259.08:15:00.77#ibcon#about to read 4, iclass 23, count 2 2006.259.08:15:00.77#ibcon#read 4, iclass 23, count 2 2006.259.08:15:00.77#ibcon#about to read 5, iclass 23, count 2 2006.259.08:15:00.77#ibcon#read 5, iclass 23, count 2 2006.259.08:15:00.77#ibcon#about to read 6, iclass 23, count 2 2006.259.08:15:00.77#ibcon#read 6, iclass 23, count 2 2006.259.08:15:00.77#ibcon#end of sib2, iclass 23, count 2 2006.259.08:15:00.77#ibcon#*after write, iclass 23, count 2 2006.259.08:15:00.77#ibcon#*before return 0, iclass 23, count 2 2006.259.08:15:00.77#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.259.08:15:00.77#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.259.08:15:00.77#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.259.08:15:00.77#ibcon#ireg 7 cls_cnt 0 2006.259.08:15:00.77#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.259.08:15:00.89#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.259.08:15:00.89#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.259.08:15:00.89#ibcon#enter wrdev, iclass 23, count 0 2006.259.08:15:00.89#ibcon#first serial, iclass 23, count 0 2006.259.08:15:00.89#ibcon#enter sib2, iclass 23, count 0 2006.259.08:15:00.89#ibcon#flushed, iclass 23, count 0 2006.259.08:15:00.89#ibcon#about to write, iclass 23, count 0 2006.259.08:15:00.89#ibcon#wrote, iclass 23, count 0 2006.259.08:15:00.89#ibcon#about to read 3, iclass 23, count 0 2006.259.08:15:00.91#ibcon#read 3, iclass 23, count 0 2006.259.08:15:00.91#ibcon#about to read 4, iclass 23, count 0 2006.259.08:15:00.91#ibcon#read 4, iclass 23, count 0 2006.259.08:15:00.91#ibcon#about to read 5, iclass 23, count 0 2006.259.08:15:00.91#ibcon#read 5, iclass 23, count 0 2006.259.08:15:00.91#ibcon#about to read 6, iclass 23, count 0 2006.259.08:15:00.91#ibcon#read 6, iclass 23, count 0 2006.259.08:15:00.91#ibcon#end of sib2, iclass 23, count 0 2006.259.08:15:00.91#ibcon#*mode == 0, iclass 23, count 0 2006.259.08:15:00.91#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.259.08:15:00.91#ibcon#[25=USB\r\n] 2006.259.08:15:00.91#ibcon#*before write, iclass 23, count 0 2006.259.08:15:00.91#ibcon#enter sib2, iclass 23, count 0 2006.259.08:15:00.91#ibcon#flushed, iclass 23, count 0 2006.259.08:15:00.91#ibcon#about to write, iclass 23, count 0 2006.259.08:15:00.91#ibcon#wrote, iclass 23, count 0 2006.259.08:15:00.91#ibcon#about to read 3, iclass 23, count 0 2006.259.08:15:00.94#ibcon#read 3, iclass 23, count 0 2006.259.08:15:00.94#ibcon#about to read 4, iclass 23, count 0 2006.259.08:15:00.94#ibcon#read 4, iclass 23, count 0 2006.259.08:15:00.94#ibcon#about to read 5, iclass 23, count 0 2006.259.08:15:00.94#ibcon#read 5, iclass 23, count 0 2006.259.08:15:00.94#ibcon#about to read 6, iclass 23, count 0 2006.259.08:15:00.94#ibcon#read 6, iclass 23, count 0 2006.259.08:15:00.94#ibcon#end of sib2, iclass 23, count 0 2006.259.08:15:00.94#ibcon#*after write, iclass 23, count 0 2006.259.08:15:00.94#ibcon#*before return 0, iclass 23, count 0 2006.259.08:15:00.94#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.259.08:15:00.94#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.259.08:15:00.94#ibcon#about to clear, iclass 23 cls_cnt 0 2006.259.08:15:00.94#ibcon#cleared, iclass 23 cls_cnt 0 2006.259.08:15:00.94$vc4f8/valo=8,852.99 2006.259.08:15:00.94#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.259.08:15:00.94#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.259.08:15:00.94#ibcon#ireg 17 cls_cnt 0 2006.259.08:15:00.94#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.259.08:15:00.94#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.259.08:15:00.94#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.259.08:15:00.94#ibcon#enter wrdev, iclass 25, count 0 2006.259.08:15:00.94#ibcon#first serial, iclass 25, count 0 2006.259.08:15:00.94#ibcon#enter sib2, iclass 25, count 0 2006.259.08:15:00.94#ibcon#flushed, iclass 25, count 0 2006.259.08:15:00.94#ibcon#about to write, iclass 25, count 0 2006.259.08:15:00.94#ibcon#wrote, iclass 25, count 0 2006.259.08:15:00.94#ibcon#about to read 3, iclass 25, count 0 2006.259.08:15:00.96#ibcon#read 3, iclass 25, count 0 2006.259.08:15:00.96#ibcon#about to read 4, iclass 25, count 0 2006.259.08:15:00.96#ibcon#read 4, iclass 25, count 0 2006.259.08:15:00.96#ibcon#about to read 5, iclass 25, count 0 2006.259.08:15:00.96#ibcon#read 5, iclass 25, count 0 2006.259.08:15:00.96#ibcon#about to read 6, iclass 25, count 0 2006.259.08:15:00.96#ibcon#read 6, iclass 25, count 0 2006.259.08:15:00.96#ibcon#end of sib2, iclass 25, count 0 2006.259.08:15:00.96#ibcon#*mode == 0, iclass 25, count 0 2006.259.08:15:00.96#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.259.08:15:00.96#ibcon#[26=FRQ=08,852.99\r\n] 2006.259.08:15:00.96#ibcon#*before write, iclass 25, count 0 2006.259.08:15:00.96#ibcon#enter sib2, iclass 25, count 0 2006.259.08:15:00.96#ibcon#flushed, iclass 25, count 0 2006.259.08:15:00.96#ibcon#about to write, iclass 25, count 0 2006.259.08:15:00.96#ibcon#wrote, iclass 25, count 0 2006.259.08:15:00.96#ibcon#about to read 3, iclass 25, count 0 2006.259.08:15:01.00#ibcon#read 3, iclass 25, count 0 2006.259.08:15:01.00#ibcon#about to read 4, iclass 25, count 0 2006.259.08:15:01.00#ibcon#read 4, iclass 25, count 0 2006.259.08:15:01.00#ibcon#about to read 5, iclass 25, count 0 2006.259.08:15:01.00#ibcon#read 5, iclass 25, count 0 2006.259.08:15:01.00#ibcon#about to read 6, iclass 25, count 0 2006.259.08:15:01.00#ibcon#read 6, iclass 25, count 0 2006.259.08:15:01.00#ibcon#end of sib2, iclass 25, count 0 2006.259.08:15:01.00#ibcon#*after write, iclass 25, count 0 2006.259.08:15:01.00#ibcon#*before return 0, iclass 25, count 0 2006.259.08:15:01.00#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.259.08:15:01.00#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.259.08:15:01.00#ibcon#about to clear, iclass 25 cls_cnt 0 2006.259.08:15:01.00#ibcon#cleared, iclass 25 cls_cnt 0 2006.259.08:15:01.00$vc4f8/va=8,6 2006.259.08:15:01.00#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.259.08:15:01.00#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.259.08:15:01.00#ibcon#ireg 11 cls_cnt 2 2006.259.08:15:01.00#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.259.08:15:01.06#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.259.08:15:01.06#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.259.08:15:01.06#ibcon#enter wrdev, iclass 27, count 2 2006.259.08:15:01.06#ibcon#first serial, iclass 27, count 2 2006.259.08:15:01.06#ibcon#enter sib2, iclass 27, count 2 2006.259.08:15:01.06#ibcon#flushed, iclass 27, count 2 2006.259.08:15:01.06#ibcon#about to write, iclass 27, count 2 2006.259.08:15:01.06#ibcon#wrote, iclass 27, count 2 2006.259.08:15:01.06#ibcon#about to read 3, iclass 27, count 2 2006.259.08:15:01.08#ibcon#read 3, iclass 27, count 2 2006.259.08:15:01.08#ibcon#about to read 4, iclass 27, count 2 2006.259.08:15:01.08#ibcon#read 4, iclass 27, count 2 2006.259.08:15:01.08#ibcon#about to read 5, iclass 27, count 2 2006.259.08:15:01.08#ibcon#read 5, iclass 27, count 2 2006.259.08:15:01.08#ibcon#about to read 6, iclass 27, count 2 2006.259.08:15:01.08#ibcon#read 6, iclass 27, count 2 2006.259.08:15:01.08#ibcon#end of sib2, iclass 27, count 2 2006.259.08:15:01.08#ibcon#*mode == 0, iclass 27, count 2 2006.259.08:15:01.08#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.259.08:15:01.08#ibcon#[25=AT08-06\r\n] 2006.259.08:15:01.08#ibcon#*before write, iclass 27, count 2 2006.259.08:15:01.08#ibcon#enter sib2, iclass 27, count 2 2006.259.08:15:01.08#ibcon#flushed, iclass 27, count 2 2006.259.08:15:01.08#ibcon#about to write, iclass 27, count 2 2006.259.08:15:01.08#ibcon#wrote, iclass 27, count 2 2006.259.08:15:01.08#ibcon#about to read 3, iclass 27, count 2 2006.259.08:15:01.11#ibcon#read 3, iclass 27, count 2 2006.259.08:15:01.11#ibcon#about to read 4, iclass 27, count 2 2006.259.08:15:01.11#ibcon#read 4, iclass 27, count 2 2006.259.08:15:01.11#ibcon#about to read 5, iclass 27, count 2 2006.259.08:15:01.11#ibcon#read 5, iclass 27, count 2 2006.259.08:15:01.11#ibcon#about to read 6, iclass 27, count 2 2006.259.08:15:01.11#ibcon#read 6, iclass 27, count 2 2006.259.08:15:01.11#ibcon#end of sib2, iclass 27, count 2 2006.259.08:15:01.11#ibcon#*after write, iclass 27, count 2 2006.259.08:15:01.11#ibcon#*before return 0, iclass 27, count 2 2006.259.08:15:01.11#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.259.08:15:01.11#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.259.08:15:01.11#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.259.08:15:01.11#ibcon#ireg 7 cls_cnt 0 2006.259.08:15:01.11#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.259.08:15:01.23#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.259.08:15:01.23#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.259.08:15:01.23#ibcon#enter wrdev, iclass 27, count 0 2006.259.08:15:01.23#ibcon#first serial, iclass 27, count 0 2006.259.08:15:01.23#ibcon#enter sib2, iclass 27, count 0 2006.259.08:15:01.23#ibcon#flushed, iclass 27, count 0 2006.259.08:15:01.23#ibcon#about to write, iclass 27, count 0 2006.259.08:15:01.23#ibcon#wrote, iclass 27, count 0 2006.259.08:15:01.23#ibcon#about to read 3, iclass 27, count 0 2006.259.08:15:01.25#ibcon#read 3, iclass 27, count 0 2006.259.08:15:01.25#ibcon#about to read 4, iclass 27, count 0 2006.259.08:15:01.25#ibcon#read 4, iclass 27, count 0 2006.259.08:15:01.25#ibcon#about to read 5, iclass 27, count 0 2006.259.08:15:01.25#ibcon#read 5, iclass 27, count 0 2006.259.08:15:01.25#ibcon#about to read 6, iclass 27, count 0 2006.259.08:15:01.25#ibcon#read 6, iclass 27, count 0 2006.259.08:15:01.25#ibcon#end of sib2, iclass 27, count 0 2006.259.08:15:01.25#ibcon#*mode == 0, iclass 27, count 0 2006.259.08:15:01.25#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.259.08:15:01.25#ibcon#[25=USB\r\n] 2006.259.08:15:01.25#ibcon#*before write, iclass 27, count 0 2006.259.08:15:01.25#ibcon#enter sib2, iclass 27, count 0 2006.259.08:15:01.25#ibcon#flushed, iclass 27, count 0 2006.259.08:15:01.25#ibcon#about to write, iclass 27, count 0 2006.259.08:15:01.25#ibcon#wrote, iclass 27, count 0 2006.259.08:15:01.25#ibcon#about to read 3, iclass 27, count 0 2006.259.08:15:01.28#ibcon#read 3, iclass 27, count 0 2006.259.08:15:01.28#ibcon#about to read 4, iclass 27, count 0 2006.259.08:15:01.28#ibcon#read 4, iclass 27, count 0 2006.259.08:15:01.28#ibcon#about to read 5, iclass 27, count 0 2006.259.08:15:01.28#ibcon#read 5, iclass 27, count 0 2006.259.08:15:01.28#ibcon#about to read 6, iclass 27, count 0 2006.259.08:15:01.28#ibcon#read 6, iclass 27, count 0 2006.259.08:15:01.28#ibcon#end of sib2, iclass 27, count 0 2006.259.08:15:01.28#ibcon#*after write, iclass 27, count 0 2006.259.08:15:01.28#ibcon#*before return 0, iclass 27, count 0 2006.259.08:15:01.28#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.259.08:15:01.28#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.259.08:15:01.28#ibcon#about to clear, iclass 27 cls_cnt 0 2006.259.08:15:01.28#ibcon#cleared, iclass 27 cls_cnt 0 2006.259.08:15:01.28$vc4f8/vblo=1,632.99 2006.259.08:15:01.28#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.259.08:15:01.28#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.259.08:15:01.28#ibcon#ireg 17 cls_cnt 0 2006.259.08:15:01.28#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.259.08:15:01.28#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.259.08:15:01.28#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.259.08:15:01.28#ibcon#enter wrdev, iclass 29, count 0 2006.259.08:15:01.28#ibcon#first serial, iclass 29, count 0 2006.259.08:15:01.28#ibcon#enter sib2, iclass 29, count 0 2006.259.08:15:01.28#ibcon#flushed, iclass 29, count 0 2006.259.08:15:01.28#ibcon#about to write, iclass 29, count 0 2006.259.08:15:01.28#ibcon#wrote, iclass 29, count 0 2006.259.08:15:01.28#ibcon#about to read 3, iclass 29, count 0 2006.259.08:15:01.30#ibcon#read 3, iclass 29, count 0 2006.259.08:15:01.30#ibcon#about to read 4, iclass 29, count 0 2006.259.08:15:01.30#ibcon#read 4, iclass 29, count 0 2006.259.08:15:01.30#ibcon#about to read 5, iclass 29, count 0 2006.259.08:15:01.30#ibcon#read 5, iclass 29, count 0 2006.259.08:15:01.30#ibcon#about to read 6, iclass 29, count 0 2006.259.08:15:01.30#ibcon#read 6, iclass 29, count 0 2006.259.08:15:01.30#ibcon#end of sib2, iclass 29, count 0 2006.259.08:15:01.30#ibcon#*mode == 0, iclass 29, count 0 2006.259.08:15:01.30#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.259.08:15:01.30#ibcon#[28=FRQ=01,632.99\r\n] 2006.259.08:15:01.30#ibcon#*before write, iclass 29, count 0 2006.259.08:15:01.30#ibcon#enter sib2, iclass 29, count 0 2006.259.08:15:01.30#ibcon#flushed, iclass 29, count 0 2006.259.08:15:01.30#ibcon#about to write, iclass 29, count 0 2006.259.08:15:01.30#ibcon#wrote, iclass 29, count 0 2006.259.08:15:01.30#ibcon#about to read 3, iclass 29, count 0 2006.259.08:15:01.34#ibcon#read 3, iclass 29, count 0 2006.259.08:15:01.34#ibcon#about to read 4, iclass 29, count 0 2006.259.08:15:01.34#ibcon#read 4, iclass 29, count 0 2006.259.08:15:01.34#ibcon#about to read 5, iclass 29, count 0 2006.259.08:15:01.34#ibcon#read 5, iclass 29, count 0 2006.259.08:15:01.34#ibcon#about to read 6, iclass 29, count 0 2006.259.08:15:01.34#ibcon#read 6, iclass 29, count 0 2006.259.08:15:01.34#ibcon#end of sib2, iclass 29, count 0 2006.259.08:15:01.34#ibcon#*after write, iclass 29, count 0 2006.259.08:15:01.34#ibcon#*before return 0, iclass 29, count 0 2006.259.08:15:01.34#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.259.08:15:01.34#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.259.08:15:01.34#ibcon#about to clear, iclass 29 cls_cnt 0 2006.259.08:15:01.34#ibcon#cleared, iclass 29 cls_cnt 0 2006.259.08:15:01.34$vc4f8/vb=1,4 2006.259.08:15:01.34#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.259.08:15:01.34#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.259.08:15:01.34#ibcon#ireg 11 cls_cnt 2 2006.259.08:15:01.34#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.259.08:15:01.34#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.259.08:15:01.34#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.259.08:15:01.34#ibcon#enter wrdev, iclass 31, count 2 2006.259.08:15:01.34#ibcon#first serial, iclass 31, count 2 2006.259.08:15:01.34#ibcon#enter sib2, iclass 31, count 2 2006.259.08:15:01.34#ibcon#flushed, iclass 31, count 2 2006.259.08:15:01.34#ibcon#about to write, iclass 31, count 2 2006.259.08:15:01.34#ibcon#wrote, iclass 31, count 2 2006.259.08:15:01.34#ibcon#about to read 3, iclass 31, count 2 2006.259.08:15:01.36#ibcon#read 3, iclass 31, count 2 2006.259.08:15:01.36#ibcon#about to read 4, iclass 31, count 2 2006.259.08:15:01.36#ibcon#read 4, iclass 31, count 2 2006.259.08:15:01.36#ibcon#about to read 5, iclass 31, count 2 2006.259.08:15:01.36#ibcon#read 5, iclass 31, count 2 2006.259.08:15:01.36#ibcon#about to read 6, iclass 31, count 2 2006.259.08:15:01.36#ibcon#read 6, iclass 31, count 2 2006.259.08:15:01.36#ibcon#end of sib2, iclass 31, count 2 2006.259.08:15:01.36#ibcon#*mode == 0, iclass 31, count 2 2006.259.08:15:01.36#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.259.08:15:01.36#ibcon#[27=AT01-04\r\n] 2006.259.08:15:01.36#ibcon#*before write, iclass 31, count 2 2006.259.08:15:01.36#ibcon#enter sib2, iclass 31, count 2 2006.259.08:15:01.36#ibcon#flushed, iclass 31, count 2 2006.259.08:15:01.36#ibcon#about to write, iclass 31, count 2 2006.259.08:15:01.36#ibcon#wrote, iclass 31, count 2 2006.259.08:15:01.36#ibcon#about to read 3, iclass 31, count 2 2006.259.08:15:01.39#ibcon#read 3, iclass 31, count 2 2006.259.08:15:01.39#ibcon#about to read 4, iclass 31, count 2 2006.259.08:15:01.39#ibcon#read 4, iclass 31, count 2 2006.259.08:15:01.39#ibcon#about to read 5, iclass 31, count 2 2006.259.08:15:01.39#ibcon#read 5, iclass 31, count 2 2006.259.08:15:01.39#ibcon#about to read 6, iclass 31, count 2 2006.259.08:15:01.39#ibcon#read 6, iclass 31, count 2 2006.259.08:15:01.39#ibcon#end of sib2, iclass 31, count 2 2006.259.08:15:01.39#ibcon#*after write, iclass 31, count 2 2006.259.08:15:01.39#ibcon#*before return 0, iclass 31, count 2 2006.259.08:15:01.39#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.259.08:15:01.39#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.259.08:15:01.39#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.259.08:15:01.39#ibcon#ireg 7 cls_cnt 0 2006.259.08:15:01.39#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.259.08:15:01.51#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.259.08:15:01.51#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.259.08:15:01.51#ibcon#enter wrdev, iclass 31, count 0 2006.259.08:15:01.51#ibcon#first serial, iclass 31, count 0 2006.259.08:15:01.51#ibcon#enter sib2, iclass 31, count 0 2006.259.08:15:01.51#ibcon#flushed, iclass 31, count 0 2006.259.08:15:01.51#ibcon#about to write, iclass 31, count 0 2006.259.08:15:01.51#ibcon#wrote, iclass 31, count 0 2006.259.08:15:01.51#ibcon#about to read 3, iclass 31, count 0 2006.259.08:15:01.53#ibcon#read 3, iclass 31, count 0 2006.259.08:15:01.53#ibcon#about to read 4, iclass 31, count 0 2006.259.08:15:01.53#ibcon#read 4, iclass 31, count 0 2006.259.08:15:01.53#ibcon#about to read 5, iclass 31, count 0 2006.259.08:15:01.53#ibcon#read 5, iclass 31, count 0 2006.259.08:15:01.53#ibcon#about to read 6, iclass 31, count 0 2006.259.08:15:01.53#ibcon#read 6, iclass 31, count 0 2006.259.08:15:01.53#ibcon#end of sib2, iclass 31, count 0 2006.259.08:15:01.53#ibcon#*mode == 0, iclass 31, count 0 2006.259.08:15:01.53#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.259.08:15:01.53#ibcon#[27=USB\r\n] 2006.259.08:15:01.53#ibcon#*before write, iclass 31, count 0 2006.259.08:15:01.53#ibcon#enter sib2, iclass 31, count 0 2006.259.08:15:01.53#ibcon#flushed, iclass 31, count 0 2006.259.08:15:01.53#ibcon#about to write, iclass 31, count 0 2006.259.08:15:01.53#ibcon#wrote, iclass 31, count 0 2006.259.08:15:01.53#ibcon#about to read 3, iclass 31, count 0 2006.259.08:15:01.56#ibcon#read 3, iclass 31, count 0 2006.259.08:15:01.56#ibcon#about to read 4, iclass 31, count 0 2006.259.08:15:01.56#ibcon#read 4, iclass 31, count 0 2006.259.08:15:01.56#ibcon#about to read 5, iclass 31, count 0 2006.259.08:15:01.56#ibcon#read 5, iclass 31, count 0 2006.259.08:15:01.56#ibcon#about to read 6, iclass 31, count 0 2006.259.08:15:01.56#ibcon#read 6, iclass 31, count 0 2006.259.08:15:01.56#ibcon#end of sib2, iclass 31, count 0 2006.259.08:15:01.56#ibcon#*after write, iclass 31, count 0 2006.259.08:15:01.56#ibcon#*before return 0, iclass 31, count 0 2006.259.08:15:01.56#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.259.08:15:01.56#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.259.08:15:01.56#ibcon#about to clear, iclass 31 cls_cnt 0 2006.259.08:15:01.56#ibcon#cleared, iclass 31 cls_cnt 0 2006.259.08:15:01.56$vc4f8/vblo=2,640.99 2006.259.08:15:01.56#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.259.08:15:01.56#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.259.08:15:01.56#ibcon#ireg 17 cls_cnt 0 2006.259.08:15:01.56#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.259.08:15:01.56#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.259.08:15:01.56#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.259.08:15:01.56#ibcon#enter wrdev, iclass 33, count 0 2006.259.08:15:01.56#ibcon#first serial, iclass 33, count 0 2006.259.08:15:01.56#ibcon#enter sib2, iclass 33, count 0 2006.259.08:15:01.56#ibcon#flushed, iclass 33, count 0 2006.259.08:15:01.56#ibcon#about to write, iclass 33, count 0 2006.259.08:15:01.56#ibcon#wrote, iclass 33, count 0 2006.259.08:15:01.56#ibcon#about to read 3, iclass 33, count 0 2006.259.08:15:01.58#ibcon#read 3, iclass 33, count 0 2006.259.08:15:01.58#ibcon#about to read 4, iclass 33, count 0 2006.259.08:15:01.58#ibcon#read 4, iclass 33, count 0 2006.259.08:15:01.58#ibcon#about to read 5, iclass 33, count 0 2006.259.08:15:01.58#ibcon#read 5, iclass 33, count 0 2006.259.08:15:01.58#ibcon#about to read 6, iclass 33, count 0 2006.259.08:15:01.58#ibcon#read 6, iclass 33, count 0 2006.259.08:15:01.58#ibcon#end of sib2, iclass 33, count 0 2006.259.08:15:01.58#ibcon#*mode == 0, iclass 33, count 0 2006.259.08:15:01.58#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.259.08:15:01.58#ibcon#[28=FRQ=02,640.99\r\n] 2006.259.08:15:01.58#ibcon#*before write, iclass 33, count 0 2006.259.08:15:01.58#ibcon#enter sib2, iclass 33, count 0 2006.259.08:15:01.58#ibcon#flushed, iclass 33, count 0 2006.259.08:15:01.58#ibcon#about to write, iclass 33, count 0 2006.259.08:15:01.58#ibcon#wrote, iclass 33, count 0 2006.259.08:15:01.58#ibcon#about to read 3, iclass 33, count 0 2006.259.08:15:01.62#ibcon#read 3, iclass 33, count 0 2006.259.08:15:01.62#ibcon#about to read 4, iclass 33, count 0 2006.259.08:15:01.62#ibcon#read 4, iclass 33, count 0 2006.259.08:15:01.62#ibcon#about to read 5, iclass 33, count 0 2006.259.08:15:01.62#ibcon#read 5, iclass 33, count 0 2006.259.08:15:01.62#ibcon#about to read 6, iclass 33, count 0 2006.259.08:15:01.62#ibcon#read 6, iclass 33, count 0 2006.259.08:15:01.62#ibcon#end of sib2, iclass 33, count 0 2006.259.08:15:01.62#ibcon#*after write, iclass 33, count 0 2006.259.08:15:01.62#ibcon#*before return 0, iclass 33, count 0 2006.259.08:15:01.62#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.259.08:15:01.62#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.259.08:15:01.62#ibcon#about to clear, iclass 33 cls_cnt 0 2006.259.08:15:01.62#ibcon#cleared, iclass 33 cls_cnt 0 2006.259.08:15:01.62$vc4f8/vb=2,5 2006.259.08:15:01.62#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.259.08:15:01.62#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.259.08:15:01.62#ibcon#ireg 11 cls_cnt 2 2006.259.08:15:01.62#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.259.08:15:01.68#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.259.08:15:01.68#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.259.08:15:01.68#ibcon#enter wrdev, iclass 35, count 2 2006.259.08:15:01.68#ibcon#first serial, iclass 35, count 2 2006.259.08:15:01.68#ibcon#enter sib2, iclass 35, count 2 2006.259.08:15:01.68#ibcon#flushed, iclass 35, count 2 2006.259.08:15:01.68#ibcon#about to write, iclass 35, count 2 2006.259.08:15:01.68#ibcon#wrote, iclass 35, count 2 2006.259.08:15:01.68#ibcon#about to read 3, iclass 35, count 2 2006.259.08:15:01.70#ibcon#read 3, iclass 35, count 2 2006.259.08:15:01.70#ibcon#about to read 4, iclass 35, count 2 2006.259.08:15:01.70#ibcon#read 4, iclass 35, count 2 2006.259.08:15:01.70#ibcon#about to read 5, iclass 35, count 2 2006.259.08:15:01.70#ibcon#read 5, iclass 35, count 2 2006.259.08:15:01.70#ibcon#about to read 6, iclass 35, count 2 2006.259.08:15:01.70#ibcon#read 6, iclass 35, count 2 2006.259.08:15:01.70#ibcon#end of sib2, iclass 35, count 2 2006.259.08:15:01.70#ibcon#*mode == 0, iclass 35, count 2 2006.259.08:15:01.70#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.259.08:15:01.70#ibcon#[27=AT02-05\r\n] 2006.259.08:15:01.70#ibcon#*before write, iclass 35, count 2 2006.259.08:15:01.70#ibcon#enter sib2, iclass 35, count 2 2006.259.08:15:01.70#ibcon#flushed, iclass 35, count 2 2006.259.08:15:01.70#ibcon#about to write, iclass 35, count 2 2006.259.08:15:01.70#ibcon#wrote, iclass 35, count 2 2006.259.08:15:01.70#ibcon#about to read 3, iclass 35, count 2 2006.259.08:15:01.73#ibcon#read 3, iclass 35, count 2 2006.259.08:15:01.73#ibcon#about to read 4, iclass 35, count 2 2006.259.08:15:01.73#ibcon#read 4, iclass 35, count 2 2006.259.08:15:01.73#ibcon#about to read 5, iclass 35, count 2 2006.259.08:15:01.73#ibcon#read 5, iclass 35, count 2 2006.259.08:15:01.73#ibcon#about to read 6, iclass 35, count 2 2006.259.08:15:01.73#ibcon#read 6, iclass 35, count 2 2006.259.08:15:01.73#ibcon#end of sib2, iclass 35, count 2 2006.259.08:15:01.73#ibcon#*after write, iclass 35, count 2 2006.259.08:15:01.73#ibcon#*before return 0, iclass 35, count 2 2006.259.08:15:01.73#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.259.08:15:01.73#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.259.08:15:01.73#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.259.08:15:01.73#ibcon#ireg 7 cls_cnt 0 2006.259.08:15:01.73#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.259.08:15:01.85#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.259.08:15:01.85#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.259.08:15:01.85#ibcon#enter wrdev, iclass 35, count 0 2006.259.08:15:01.85#ibcon#first serial, iclass 35, count 0 2006.259.08:15:01.85#ibcon#enter sib2, iclass 35, count 0 2006.259.08:15:01.85#ibcon#flushed, iclass 35, count 0 2006.259.08:15:01.85#ibcon#about to write, iclass 35, count 0 2006.259.08:15:01.85#ibcon#wrote, iclass 35, count 0 2006.259.08:15:01.85#ibcon#about to read 3, iclass 35, count 0 2006.259.08:15:01.87#ibcon#read 3, iclass 35, count 0 2006.259.08:15:01.87#ibcon#about to read 4, iclass 35, count 0 2006.259.08:15:01.87#ibcon#read 4, iclass 35, count 0 2006.259.08:15:01.87#ibcon#about to read 5, iclass 35, count 0 2006.259.08:15:01.87#ibcon#read 5, iclass 35, count 0 2006.259.08:15:01.87#ibcon#about to read 6, iclass 35, count 0 2006.259.08:15:01.87#ibcon#read 6, iclass 35, count 0 2006.259.08:15:01.87#ibcon#end of sib2, iclass 35, count 0 2006.259.08:15:01.87#ibcon#*mode == 0, iclass 35, count 0 2006.259.08:15:01.87#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.259.08:15:01.87#ibcon#[27=USB\r\n] 2006.259.08:15:01.87#ibcon#*before write, iclass 35, count 0 2006.259.08:15:01.87#ibcon#enter sib2, iclass 35, count 0 2006.259.08:15:01.87#ibcon#flushed, iclass 35, count 0 2006.259.08:15:01.87#ibcon#about to write, iclass 35, count 0 2006.259.08:15:01.87#ibcon#wrote, iclass 35, count 0 2006.259.08:15:01.87#ibcon#about to read 3, iclass 35, count 0 2006.259.08:15:01.90#ibcon#read 3, iclass 35, count 0 2006.259.08:15:01.90#ibcon#about to read 4, iclass 35, count 0 2006.259.08:15:01.90#ibcon#read 4, iclass 35, count 0 2006.259.08:15:01.90#ibcon#about to read 5, iclass 35, count 0 2006.259.08:15:01.90#ibcon#read 5, iclass 35, count 0 2006.259.08:15:01.90#ibcon#about to read 6, iclass 35, count 0 2006.259.08:15:01.90#ibcon#read 6, iclass 35, count 0 2006.259.08:15:01.90#ibcon#end of sib2, iclass 35, count 0 2006.259.08:15:01.90#ibcon#*after write, iclass 35, count 0 2006.259.08:15:01.90#ibcon#*before return 0, iclass 35, count 0 2006.259.08:15:01.90#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.259.08:15:01.90#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.259.08:15:01.90#ibcon#about to clear, iclass 35 cls_cnt 0 2006.259.08:15:01.90#ibcon#cleared, iclass 35 cls_cnt 0 2006.259.08:15:01.90$vc4f8/vblo=3,656.99 2006.259.08:15:01.90#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.259.08:15:01.90#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.259.08:15:01.90#ibcon#ireg 17 cls_cnt 0 2006.259.08:15:01.90#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.259.08:15:01.90#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.259.08:15:01.90#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.259.08:15:01.90#ibcon#enter wrdev, iclass 37, count 0 2006.259.08:15:01.90#ibcon#first serial, iclass 37, count 0 2006.259.08:15:01.90#ibcon#enter sib2, iclass 37, count 0 2006.259.08:15:01.90#ibcon#flushed, iclass 37, count 0 2006.259.08:15:01.90#ibcon#about to write, iclass 37, count 0 2006.259.08:15:01.90#ibcon#wrote, iclass 37, count 0 2006.259.08:15:01.90#ibcon#about to read 3, iclass 37, count 0 2006.259.08:15:01.92#ibcon#read 3, iclass 37, count 0 2006.259.08:15:01.92#ibcon#about to read 4, iclass 37, count 0 2006.259.08:15:01.92#ibcon#read 4, iclass 37, count 0 2006.259.08:15:01.92#ibcon#about to read 5, iclass 37, count 0 2006.259.08:15:01.92#ibcon#read 5, iclass 37, count 0 2006.259.08:15:01.92#ibcon#about to read 6, iclass 37, count 0 2006.259.08:15:01.92#ibcon#read 6, iclass 37, count 0 2006.259.08:15:01.92#ibcon#end of sib2, iclass 37, count 0 2006.259.08:15:01.92#ibcon#*mode == 0, iclass 37, count 0 2006.259.08:15:01.92#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.259.08:15:01.92#ibcon#[28=FRQ=03,656.99\r\n] 2006.259.08:15:01.92#ibcon#*before write, iclass 37, count 0 2006.259.08:15:01.92#ibcon#enter sib2, iclass 37, count 0 2006.259.08:15:01.92#ibcon#flushed, iclass 37, count 0 2006.259.08:15:01.92#ibcon#about to write, iclass 37, count 0 2006.259.08:15:01.92#ibcon#wrote, iclass 37, count 0 2006.259.08:15:01.92#ibcon#about to read 3, iclass 37, count 0 2006.259.08:15:01.96#ibcon#read 3, iclass 37, count 0 2006.259.08:15:01.96#ibcon#about to read 4, iclass 37, count 0 2006.259.08:15:01.96#ibcon#read 4, iclass 37, count 0 2006.259.08:15:01.96#ibcon#about to read 5, iclass 37, count 0 2006.259.08:15:01.96#ibcon#read 5, iclass 37, count 0 2006.259.08:15:01.96#ibcon#about to read 6, iclass 37, count 0 2006.259.08:15:01.96#ibcon#read 6, iclass 37, count 0 2006.259.08:15:01.96#ibcon#end of sib2, iclass 37, count 0 2006.259.08:15:01.96#ibcon#*after write, iclass 37, count 0 2006.259.08:15:01.96#ibcon#*before return 0, iclass 37, count 0 2006.259.08:15:01.96#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.259.08:15:01.96#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.259.08:15:01.96#ibcon#about to clear, iclass 37 cls_cnt 0 2006.259.08:15:01.96#ibcon#cleared, iclass 37 cls_cnt 0 2006.259.08:15:01.96$vc4f8/vb=3,4 2006.259.08:15:01.96#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.259.08:15:01.96#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.259.08:15:01.96#ibcon#ireg 11 cls_cnt 2 2006.259.08:15:01.96#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.259.08:15:02.02#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.259.08:15:02.02#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.259.08:15:02.02#ibcon#enter wrdev, iclass 39, count 2 2006.259.08:15:02.02#ibcon#first serial, iclass 39, count 2 2006.259.08:15:02.02#ibcon#enter sib2, iclass 39, count 2 2006.259.08:15:02.02#ibcon#flushed, iclass 39, count 2 2006.259.08:15:02.02#ibcon#about to write, iclass 39, count 2 2006.259.08:15:02.02#ibcon#wrote, iclass 39, count 2 2006.259.08:15:02.02#ibcon#about to read 3, iclass 39, count 2 2006.259.08:15:02.04#ibcon#read 3, iclass 39, count 2 2006.259.08:15:02.04#ibcon#about to read 4, iclass 39, count 2 2006.259.08:15:02.04#ibcon#read 4, iclass 39, count 2 2006.259.08:15:02.04#ibcon#about to read 5, iclass 39, count 2 2006.259.08:15:02.04#ibcon#read 5, iclass 39, count 2 2006.259.08:15:02.04#ibcon#about to read 6, iclass 39, count 2 2006.259.08:15:02.04#ibcon#read 6, iclass 39, count 2 2006.259.08:15:02.04#ibcon#end of sib2, iclass 39, count 2 2006.259.08:15:02.04#ibcon#*mode == 0, iclass 39, count 2 2006.259.08:15:02.04#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.259.08:15:02.04#ibcon#[27=AT03-04\r\n] 2006.259.08:15:02.04#ibcon#*before write, iclass 39, count 2 2006.259.08:15:02.04#ibcon#enter sib2, iclass 39, count 2 2006.259.08:15:02.04#ibcon#flushed, iclass 39, count 2 2006.259.08:15:02.04#ibcon#about to write, iclass 39, count 2 2006.259.08:15:02.04#ibcon#wrote, iclass 39, count 2 2006.259.08:15:02.04#ibcon#about to read 3, iclass 39, count 2 2006.259.08:15:02.07#ibcon#read 3, iclass 39, count 2 2006.259.08:15:02.07#ibcon#about to read 4, iclass 39, count 2 2006.259.08:15:02.07#ibcon#read 4, iclass 39, count 2 2006.259.08:15:02.07#ibcon#about to read 5, iclass 39, count 2 2006.259.08:15:02.07#ibcon#read 5, iclass 39, count 2 2006.259.08:15:02.07#ibcon#about to read 6, iclass 39, count 2 2006.259.08:15:02.07#ibcon#read 6, iclass 39, count 2 2006.259.08:15:02.07#ibcon#end of sib2, iclass 39, count 2 2006.259.08:15:02.07#ibcon#*after write, iclass 39, count 2 2006.259.08:15:02.07#ibcon#*before return 0, iclass 39, count 2 2006.259.08:15:02.07#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.259.08:15:02.07#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.259.08:15:02.07#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.259.08:15:02.07#ibcon#ireg 7 cls_cnt 0 2006.259.08:15:02.07#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.259.08:15:02.19#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.259.08:15:02.19#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.259.08:15:02.19#ibcon#enter wrdev, iclass 39, count 0 2006.259.08:15:02.19#ibcon#first serial, iclass 39, count 0 2006.259.08:15:02.19#ibcon#enter sib2, iclass 39, count 0 2006.259.08:15:02.19#ibcon#flushed, iclass 39, count 0 2006.259.08:15:02.19#ibcon#about to write, iclass 39, count 0 2006.259.08:15:02.19#ibcon#wrote, iclass 39, count 0 2006.259.08:15:02.19#ibcon#about to read 3, iclass 39, count 0 2006.259.08:15:02.21#ibcon#read 3, iclass 39, count 0 2006.259.08:15:02.21#ibcon#about to read 4, iclass 39, count 0 2006.259.08:15:02.21#ibcon#read 4, iclass 39, count 0 2006.259.08:15:02.21#ibcon#about to read 5, iclass 39, count 0 2006.259.08:15:02.21#ibcon#read 5, iclass 39, count 0 2006.259.08:15:02.21#ibcon#about to read 6, iclass 39, count 0 2006.259.08:15:02.21#ibcon#read 6, iclass 39, count 0 2006.259.08:15:02.21#ibcon#end of sib2, iclass 39, count 0 2006.259.08:15:02.21#ibcon#*mode == 0, iclass 39, count 0 2006.259.08:15:02.21#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.259.08:15:02.21#ibcon#[27=USB\r\n] 2006.259.08:15:02.21#ibcon#*before write, iclass 39, count 0 2006.259.08:15:02.21#ibcon#enter sib2, iclass 39, count 0 2006.259.08:15:02.21#ibcon#flushed, iclass 39, count 0 2006.259.08:15:02.21#ibcon#about to write, iclass 39, count 0 2006.259.08:15:02.21#ibcon#wrote, iclass 39, count 0 2006.259.08:15:02.21#ibcon#about to read 3, iclass 39, count 0 2006.259.08:15:02.24#ibcon#read 3, iclass 39, count 0 2006.259.08:15:02.24#ibcon#about to read 4, iclass 39, count 0 2006.259.08:15:02.24#ibcon#read 4, iclass 39, count 0 2006.259.08:15:02.24#ibcon#about to read 5, iclass 39, count 0 2006.259.08:15:02.24#ibcon#read 5, iclass 39, count 0 2006.259.08:15:02.24#ibcon#about to read 6, iclass 39, count 0 2006.259.08:15:02.24#ibcon#read 6, iclass 39, count 0 2006.259.08:15:02.24#ibcon#end of sib2, iclass 39, count 0 2006.259.08:15:02.24#ibcon#*after write, iclass 39, count 0 2006.259.08:15:02.24#ibcon#*before return 0, iclass 39, count 0 2006.259.08:15:02.24#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.259.08:15:02.24#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.259.08:15:02.24#ibcon#about to clear, iclass 39 cls_cnt 0 2006.259.08:15:02.24#ibcon#cleared, iclass 39 cls_cnt 0 2006.259.08:15:02.24$vc4f8/vblo=4,712.99 2006.259.08:15:02.24#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.259.08:15:02.24#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.259.08:15:02.24#ibcon#ireg 17 cls_cnt 0 2006.259.08:15:02.24#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.259.08:15:02.24#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.259.08:15:02.24#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.259.08:15:02.24#ibcon#enter wrdev, iclass 3, count 0 2006.259.08:15:02.24#ibcon#first serial, iclass 3, count 0 2006.259.08:15:02.24#ibcon#enter sib2, iclass 3, count 0 2006.259.08:15:02.24#ibcon#flushed, iclass 3, count 0 2006.259.08:15:02.24#ibcon#about to write, iclass 3, count 0 2006.259.08:15:02.24#ibcon#wrote, iclass 3, count 0 2006.259.08:15:02.24#ibcon#about to read 3, iclass 3, count 0 2006.259.08:15:02.26#ibcon#read 3, iclass 3, count 0 2006.259.08:15:02.26#ibcon#about to read 4, iclass 3, count 0 2006.259.08:15:02.26#ibcon#read 4, iclass 3, count 0 2006.259.08:15:02.26#ibcon#about to read 5, iclass 3, count 0 2006.259.08:15:02.26#ibcon#read 5, iclass 3, count 0 2006.259.08:15:02.26#ibcon#about to read 6, iclass 3, count 0 2006.259.08:15:02.26#ibcon#read 6, iclass 3, count 0 2006.259.08:15:02.26#ibcon#end of sib2, iclass 3, count 0 2006.259.08:15:02.26#ibcon#*mode == 0, iclass 3, count 0 2006.259.08:15:02.26#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.259.08:15:02.26#ibcon#[28=FRQ=04,712.99\r\n] 2006.259.08:15:02.26#ibcon#*before write, iclass 3, count 0 2006.259.08:15:02.26#ibcon#enter sib2, iclass 3, count 0 2006.259.08:15:02.26#ibcon#flushed, iclass 3, count 0 2006.259.08:15:02.26#ibcon#about to write, iclass 3, count 0 2006.259.08:15:02.26#ibcon#wrote, iclass 3, count 0 2006.259.08:15:02.26#ibcon#about to read 3, iclass 3, count 0 2006.259.08:15:02.30#ibcon#read 3, iclass 3, count 0 2006.259.08:15:02.30#ibcon#about to read 4, iclass 3, count 0 2006.259.08:15:02.30#ibcon#read 4, iclass 3, count 0 2006.259.08:15:02.30#ibcon#about to read 5, iclass 3, count 0 2006.259.08:15:02.30#ibcon#read 5, iclass 3, count 0 2006.259.08:15:02.30#ibcon#about to read 6, iclass 3, count 0 2006.259.08:15:02.30#ibcon#read 6, iclass 3, count 0 2006.259.08:15:02.30#ibcon#end of sib2, iclass 3, count 0 2006.259.08:15:02.30#ibcon#*after write, iclass 3, count 0 2006.259.08:15:02.30#ibcon#*before return 0, iclass 3, count 0 2006.259.08:15:02.30#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.259.08:15:02.30#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.259.08:15:02.30#ibcon#about to clear, iclass 3 cls_cnt 0 2006.259.08:15:02.30#ibcon#cleared, iclass 3 cls_cnt 0 2006.259.08:15:02.30$vc4f8/vb=4,5 2006.259.08:15:02.30#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.259.08:15:02.30#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.259.08:15:02.30#ibcon#ireg 11 cls_cnt 2 2006.259.08:15:02.30#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.259.08:15:02.36#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.259.08:15:02.36#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.259.08:15:02.36#ibcon#enter wrdev, iclass 5, count 2 2006.259.08:15:02.36#ibcon#first serial, iclass 5, count 2 2006.259.08:15:02.36#ibcon#enter sib2, iclass 5, count 2 2006.259.08:15:02.36#ibcon#flushed, iclass 5, count 2 2006.259.08:15:02.36#ibcon#about to write, iclass 5, count 2 2006.259.08:15:02.36#ibcon#wrote, iclass 5, count 2 2006.259.08:15:02.36#ibcon#about to read 3, iclass 5, count 2 2006.259.08:15:02.38#ibcon#read 3, iclass 5, count 2 2006.259.08:15:02.38#ibcon#about to read 4, iclass 5, count 2 2006.259.08:15:02.38#ibcon#read 4, iclass 5, count 2 2006.259.08:15:02.38#ibcon#about to read 5, iclass 5, count 2 2006.259.08:15:02.38#ibcon#read 5, iclass 5, count 2 2006.259.08:15:02.38#ibcon#about to read 6, iclass 5, count 2 2006.259.08:15:02.38#ibcon#read 6, iclass 5, count 2 2006.259.08:15:02.38#ibcon#end of sib2, iclass 5, count 2 2006.259.08:15:02.38#ibcon#*mode == 0, iclass 5, count 2 2006.259.08:15:02.38#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.259.08:15:02.38#ibcon#[27=AT04-05\r\n] 2006.259.08:15:02.38#ibcon#*before write, iclass 5, count 2 2006.259.08:15:02.38#ibcon#enter sib2, iclass 5, count 2 2006.259.08:15:02.38#ibcon#flushed, iclass 5, count 2 2006.259.08:15:02.38#ibcon#about to write, iclass 5, count 2 2006.259.08:15:02.38#ibcon#wrote, iclass 5, count 2 2006.259.08:15:02.38#ibcon#about to read 3, iclass 5, count 2 2006.259.08:15:02.41#ibcon#read 3, iclass 5, count 2 2006.259.08:15:02.41#ibcon#about to read 4, iclass 5, count 2 2006.259.08:15:02.41#ibcon#read 4, iclass 5, count 2 2006.259.08:15:02.41#ibcon#about to read 5, iclass 5, count 2 2006.259.08:15:02.41#ibcon#read 5, iclass 5, count 2 2006.259.08:15:02.41#ibcon#about to read 6, iclass 5, count 2 2006.259.08:15:02.41#ibcon#read 6, iclass 5, count 2 2006.259.08:15:02.41#ibcon#end of sib2, iclass 5, count 2 2006.259.08:15:02.41#ibcon#*after write, iclass 5, count 2 2006.259.08:15:02.41#ibcon#*before return 0, iclass 5, count 2 2006.259.08:15:02.41#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.259.08:15:02.41#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.259.08:15:02.41#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.259.08:15:02.41#ibcon#ireg 7 cls_cnt 0 2006.259.08:15:02.41#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.259.08:15:02.53#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.259.08:15:02.53#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.259.08:15:02.53#ibcon#enter wrdev, iclass 5, count 0 2006.259.08:15:02.53#ibcon#first serial, iclass 5, count 0 2006.259.08:15:02.53#ibcon#enter sib2, iclass 5, count 0 2006.259.08:15:02.53#ibcon#flushed, iclass 5, count 0 2006.259.08:15:02.53#ibcon#about to write, iclass 5, count 0 2006.259.08:15:02.53#ibcon#wrote, iclass 5, count 0 2006.259.08:15:02.53#ibcon#about to read 3, iclass 5, count 0 2006.259.08:15:02.55#ibcon#read 3, iclass 5, count 0 2006.259.08:15:02.55#ibcon#about to read 4, iclass 5, count 0 2006.259.08:15:02.55#ibcon#read 4, iclass 5, count 0 2006.259.08:15:02.55#ibcon#about to read 5, iclass 5, count 0 2006.259.08:15:02.55#ibcon#read 5, iclass 5, count 0 2006.259.08:15:02.55#ibcon#about to read 6, iclass 5, count 0 2006.259.08:15:02.55#ibcon#read 6, iclass 5, count 0 2006.259.08:15:02.55#ibcon#end of sib2, iclass 5, count 0 2006.259.08:15:02.55#ibcon#*mode == 0, iclass 5, count 0 2006.259.08:15:02.55#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.259.08:15:02.55#ibcon#[27=USB\r\n] 2006.259.08:15:02.55#ibcon#*before write, iclass 5, count 0 2006.259.08:15:02.55#ibcon#enter sib2, iclass 5, count 0 2006.259.08:15:02.55#ibcon#flushed, iclass 5, count 0 2006.259.08:15:02.55#ibcon#about to write, iclass 5, count 0 2006.259.08:15:02.55#ibcon#wrote, iclass 5, count 0 2006.259.08:15:02.55#ibcon#about to read 3, iclass 5, count 0 2006.259.08:15:02.58#ibcon#read 3, iclass 5, count 0 2006.259.08:15:02.58#ibcon#about to read 4, iclass 5, count 0 2006.259.08:15:02.58#ibcon#read 4, iclass 5, count 0 2006.259.08:15:02.58#ibcon#about to read 5, iclass 5, count 0 2006.259.08:15:02.58#ibcon#read 5, iclass 5, count 0 2006.259.08:15:02.58#ibcon#about to read 6, iclass 5, count 0 2006.259.08:15:02.58#ibcon#read 6, iclass 5, count 0 2006.259.08:15:02.58#ibcon#end of sib2, iclass 5, count 0 2006.259.08:15:02.58#ibcon#*after write, iclass 5, count 0 2006.259.08:15:02.58#ibcon#*before return 0, iclass 5, count 0 2006.259.08:15:02.58#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.259.08:15:02.58#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.259.08:15:02.58#ibcon#about to clear, iclass 5 cls_cnt 0 2006.259.08:15:02.58#ibcon#cleared, iclass 5 cls_cnt 0 2006.259.08:15:02.58$vc4f8/vblo=5,744.99 2006.259.08:15:02.58#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.259.08:15:02.58#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.259.08:15:02.58#ibcon#ireg 17 cls_cnt 0 2006.259.08:15:02.58#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.259.08:15:02.58#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.259.08:15:02.58#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.259.08:15:02.58#ibcon#enter wrdev, iclass 7, count 0 2006.259.08:15:02.58#ibcon#first serial, iclass 7, count 0 2006.259.08:15:02.58#ibcon#enter sib2, iclass 7, count 0 2006.259.08:15:02.58#ibcon#flushed, iclass 7, count 0 2006.259.08:15:02.58#ibcon#about to write, iclass 7, count 0 2006.259.08:15:02.58#ibcon#wrote, iclass 7, count 0 2006.259.08:15:02.58#ibcon#about to read 3, iclass 7, count 0 2006.259.08:15:02.60#ibcon#read 3, iclass 7, count 0 2006.259.08:15:02.60#ibcon#about to read 4, iclass 7, count 0 2006.259.08:15:02.60#ibcon#read 4, iclass 7, count 0 2006.259.08:15:02.60#ibcon#about to read 5, iclass 7, count 0 2006.259.08:15:02.60#ibcon#read 5, iclass 7, count 0 2006.259.08:15:02.60#ibcon#about to read 6, iclass 7, count 0 2006.259.08:15:02.60#ibcon#read 6, iclass 7, count 0 2006.259.08:15:02.60#ibcon#end of sib2, iclass 7, count 0 2006.259.08:15:02.60#ibcon#*mode == 0, iclass 7, count 0 2006.259.08:15:02.60#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.259.08:15:02.60#ibcon#[28=FRQ=05,744.99\r\n] 2006.259.08:15:02.60#ibcon#*before write, iclass 7, count 0 2006.259.08:15:02.60#ibcon#enter sib2, iclass 7, count 0 2006.259.08:15:02.60#ibcon#flushed, iclass 7, count 0 2006.259.08:15:02.60#ibcon#about to write, iclass 7, count 0 2006.259.08:15:02.60#ibcon#wrote, iclass 7, count 0 2006.259.08:15:02.60#ibcon#about to read 3, iclass 7, count 0 2006.259.08:15:02.64#ibcon#read 3, iclass 7, count 0 2006.259.08:15:02.64#ibcon#about to read 4, iclass 7, count 0 2006.259.08:15:02.64#ibcon#read 4, iclass 7, count 0 2006.259.08:15:02.64#ibcon#about to read 5, iclass 7, count 0 2006.259.08:15:02.64#ibcon#read 5, iclass 7, count 0 2006.259.08:15:02.64#ibcon#about to read 6, iclass 7, count 0 2006.259.08:15:02.64#ibcon#read 6, iclass 7, count 0 2006.259.08:15:02.64#ibcon#end of sib2, iclass 7, count 0 2006.259.08:15:02.64#ibcon#*after write, iclass 7, count 0 2006.259.08:15:02.64#ibcon#*before return 0, iclass 7, count 0 2006.259.08:15:02.64#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.259.08:15:02.64#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.259.08:15:02.64#ibcon#about to clear, iclass 7 cls_cnt 0 2006.259.08:15:02.64#ibcon#cleared, iclass 7 cls_cnt 0 2006.259.08:15:02.64$vc4f8/vb=5,4 2006.259.08:15:02.64#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.259.08:15:02.64#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.259.08:15:02.64#ibcon#ireg 11 cls_cnt 2 2006.259.08:15:02.64#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.259.08:15:02.70#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.259.08:15:02.70#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.259.08:15:02.70#ibcon#enter wrdev, iclass 11, count 2 2006.259.08:15:02.70#ibcon#first serial, iclass 11, count 2 2006.259.08:15:02.70#ibcon#enter sib2, iclass 11, count 2 2006.259.08:15:02.70#ibcon#flushed, iclass 11, count 2 2006.259.08:15:02.70#ibcon#about to write, iclass 11, count 2 2006.259.08:15:02.70#ibcon#wrote, iclass 11, count 2 2006.259.08:15:02.70#ibcon#about to read 3, iclass 11, count 2 2006.259.08:15:02.72#ibcon#read 3, iclass 11, count 2 2006.259.08:15:02.72#ibcon#about to read 4, iclass 11, count 2 2006.259.08:15:02.72#ibcon#read 4, iclass 11, count 2 2006.259.08:15:02.72#ibcon#about to read 5, iclass 11, count 2 2006.259.08:15:02.72#ibcon#read 5, iclass 11, count 2 2006.259.08:15:02.72#ibcon#about to read 6, iclass 11, count 2 2006.259.08:15:02.72#ibcon#read 6, iclass 11, count 2 2006.259.08:15:02.72#ibcon#end of sib2, iclass 11, count 2 2006.259.08:15:02.72#ibcon#*mode == 0, iclass 11, count 2 2006.259.08:15:02.72#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.259.08:15:02.72#ibcon#[27=AT05-04\r\n] 2006.259.08:15:02.72#ibcon#*before write, iclass 11, count 2 2006.259.08:15:02.72#ibcon#enter sib2, iclass 11, count 2 2006.259.08:15:02.72#ibcon#flushed, iclass 11, count 2 2006.259.08:15:02.72#ibcon#about to write, iclass 11, count 2 2006.259.08:15:02.72#ibcon#wrote, iclass 11, count 2 2006.259.08:15:02.72#ibcon#about to read 3, iclass 11, count 2 2006.259.08:15:02.75#ibcon#read 3, iclass 11, count 2 2006.259.08:15:02.75#ibcon#about to read 4, iclass 11, count 2 2006.259.08:15:02.75#ibcon#read 4, iclass 11, count 2 2006.259.08:15:02.75#ibcon#about to read 5, iclass 11, count 2 2006.259.08:15:02.75#ibcon#read 5, iclass 11, count 2 2006.259.08:15:02.75#ibcon#about to read 6, iclass 11, count 2 2006.259.08:15:02.75#ibcon#read 6, iclass 11, count 2 2006.259.08:15:02.75#ibcon#end of sib2, iclass 11, count 2 2006.259.08:15:02.75#ibcon#*after write, iclass 11, count 2 2006.259.08:15:02.75#ibcon#*before return 0, iclass 11, count 2 2006.259.08:15:02.75#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.259.08:15:02.75#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.259.08:15:02.75#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.259.08:15:02.75#ibcon#ireg 7 cls_cnt 0 2006.259.08:15:02.75#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.259.08:15:02.87#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.259.08:15:02.87#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.259.08:15:02.87#ibcon#enter wrdev, iclass 11, count 0 2006.259.08:15:02.87#ibcon#first serial, iclass 11, count 0 2006.259.08:15:02.87#ibcon#enter sib2, iclass 11, count 0 2006.259.08:15:02.87#ibcon#flushed, iclass 11, count 0 2006.259.08:15:02.87#ibcon#about to write, iclass 11, count 0 2006.259.08:15:02.87#ibcon#wrote, iclass 11, count 0 2006.259.08:15:02.87#ibcon#about to read 3, iclass 11, count 0 2006.259.08:15:02.89#ibcon#read 3, iclass 11, count 0 2006.259.08:15:02.89#ibcon#about to read 4, iclass 11, count 0 2006.259.08:15:02.89#ibcon#read 4, iclass 11, count 0 2006.259.08:15:02.89#ibcon#about to read 5, iclass 11, count 0 2006.259.08:15:02.89#ibcon#read 5, iclass 11, count 0 2006.259.08:15:02.89#ibcon#about to read 6, iclass 11, count 0 2006.259.08:15:02.89#ibcon#read 6, iclass 11, count 0 2006.259.08:15:02.89#ibcon#end of sib2, iclass 11, count 0 2006.259.08:15:02.89#ibcon#*mode == 0, iclass 11, count 0 2006.259.08:15:02.89#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.259.08:15:02.89#ibcon#[27=USB\r\n] 2006.259.08:15:02.89#ibcon#*before write, iclass 11, count 0 2006.259.08:15:02.89#ibcon#enter sib2, iclass 11, count 0 2006.259.08:15:02.89#ibcon#flushed, iclass 11, count 0 2006.259.08:15:02.89#ibcon#about to write, iclass 11, count 0 2006.259.08:15:02.89#ibcon#wrote, iclass 11, count 0 2006.259.08:15:02.89#ibcon#about to read 3, iclass 11, count 0 2006.259.08:15:02.92#ibcon#read 3, iclass 11, count 0 2006.259.08:15:02.92#ibcon#about to read 4, iclass 11, count 0 2006.259.08:15:02.92#ibcon#read 4, iclass 11, count 0 2006.259.08:15:02.92#ibcon#about to read 5, iclass 11, count 0 2006.259.08:15:02.92#ibcon#read 5, iclass 11, count 0 2006.259.08:15:02.92#ibcon#about to read 6, iclass 11, count 0 2006.259.08:15:02.92#ibcon#read 6, iclass 11, count 0 2006.259.08:15:02.92#ibcon#end of sib2, iclass 11, count 0 2006.259.08:15:02.92#ibcon#*after write, iclass 11, count 0 2006.259.08:15:02.92#ibcon#*before return 0, iclass 11, count 0 2006.259.08:15:02.92#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.259.08:15:02.92#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.259.08:15:02.92#ibcon#about to clear, iclass 11 cls_cnt 0 2006.259.08:15:02.92#ibcon#cleared, iclass 11 cls_cnt 0 2006.259.08:15:02.92$vc4f8/vblo=6,752.99 2006.259.08:15:02.92#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.259.08:15:02.92#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.259.08:15:02.92#ibcon#ireg 17 cls_cnt 0 2006.259.08:15:02.92#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.259.08:15:02.92#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.259.08:15:02.92#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.259.08:15:02.92#ibcon#enter wrdev, iclass 13, count 0 2006.259.08:15:02.92#ibcon#first serial, iclass 13, count 0 2006.259.08:15:02.92#ibcon#enter sib2, iclass 13, count 0 2006.259.08:15:02.92#ibcon#flushed, iclass 13, count 0 2006.259.08:15:02.92#ibcon#about to write, iclass 13, count 0 2006.259.08:15:02.92#ibcon#wrote, iclass 13, count 0 2006.259.08:15:02.92#ibcon#about to read 3, iclass 13, count 0 2006.259.08:15:02.94#ibcon#read 3, iclass 13, count 0 2006.259.08:15:02.94#ibcon#about to read 4, iclass 13, count 0 2006.259.08:15:02.94#ibcon#read 4, iclass 13, count 0 2006.259.08:15:02.94#ibcon#about to read 5, iclass 13, count 0 2006.259.08:15:02.94#ibcon#read 5, iclass 13, count 0 2006.259.08:15:02.94#ibcon#about to read 6, iclass 13, count 0 2006.259.08:15:02.94#ibcon#read 6, iclass 13, count 0 2006.259.08:15:02.94#ibcon#end of sib2, iclass 13, count 0 2006.259.08:15:02.94#ibcon#*mode == 0, iclass 13, count 0 2006.259.08:15:02.94#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.259.08:15:02.94#ibcon#[28=FRQ=06,752.99\r\n] 2006.259.08:15:02.94#ibcon#*before write, iclass 13, count 0 2006.259.08:15:02.94#ibcon#enter sib2, iclass 13, count 0 2006.259.08:15:02.94#ibcon#flushed, iclass 13, count 0 2006.259.08:15:02.94#ibcon#about to write, iclass 13, count 0 2006.259.08:15:02.94#ibcon#wrote, iclass 13, count 0 2006.259.08:15:02.94#ibcon#about to read 3, iclass 13, count 0 2006.259.08:15:02.98#ibcon#read 3, iclass 13, count 0 2006.259.08:15:02.98#ibcon#about to read 4, iclass 13, count 0 2006.259.08:15:02.98#ibcon#read 4, iclass 13, count 0 2006.259.08:15:02.98#ibcon#about to read 5, iclass 13, count 0 2006.259.08:15:02.98#ibcon#read 5, iclass 13, count 0 2006.259.08:15:02.98#ibcon#about to read 6, iclass 13, count 0 2006.259.08:15:02.98#ibcon#read 6, iclass 13, count 0 2006.259.08:15:02.98#ibcon#end of sib2, iclass 13, count 0 2006.259.08:15:02.98#ibcon#*after write, iclass 13, count 0 2006.259.08:15:02.98#ibcon#*before return 0, iclass 13, count 0 2006.259.08:15:02.98#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.259.08:15:02.98#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.259.08:15:02.98#ibcon#about to clear, iclass 13 cls_cnt 0 2006.259.08:15:02.98#ibcon#cleared, iclass 13 cls_cnt 0 2006.259.08:15:02.98$vc4f8/vb=6,4 2006.259.08:15:02.98#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.259.08:15:02.98#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.259.08:15:02.98#ibcon#ireg 11 cls_cnt 2 2006.259.08:15:02.98#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.259.08:15:03.04#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.259.08:15:03.04#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.259.08:15:03.04#ibcon#enter wrdev, iclass 15, count 2 2006.259.08:15:03.04#ibcon#first serial, iclass 15, count 2 2006.259.08:15:03.04#ibcon#enter sib2, iclass 15, count 2 2006.259.08:15:03.04#ibcon#flushed, iclass 15, count 2 2006.259.08:15:03.04#ibcon#about to write, iclass 15, count 2 2006.259.08:15:03.04#ibcon#wrote, iclass 15, count 2 2006.259.08:15:03.04#ibcon#about to read 3, iclass 15, count 2 2006.259.08:15:03.06#ibcon#read 3, iclass 15, count 2 2006.259.08:15:03.06#ibcon#about to read 4, iclass 15, count 2 2006.259.08:15:03.06#ibcon#read 4, iclass 15, count 2 2006.259.08:15:03.06#ibcon#about to read 5, iclass 15, count 2 2006.259.08:15:03.06#ibcon#read 5, iclass 15, count 2 2006.259.08:15:03.06#ibcon#about to read 6, iclass 15, count 2 2006.259.08:15:03.06#ibcon#read 6, iclass 15, count 2 2006.259.08:15:03.06#ibcon#end of sib2, iclass 15, count 2 2006.259.08:15:03.06#ibcon#*mode == 0, iclass 15, count 2 2006.259.08:15:03.06#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.259.08:15:03.06#ibcon#[27=AT06-04\r\n] 2006.259.08:15:03.06#ibcon#*before write, iclass 15, count 2 2006.259.08:15:03.06#ibcon#enter sib2, iclass 15, count 2 2006.259.08:15:03.06#ibcon#flushed, iclass 15, count 2 2006.259.08:15:03.06#ibcon#about to write, iclass 15, count 2 2006.259.08:15:03.06#ibcon#wrote, iclass 15, count 2 2006.259.08:15:03.06#ibcon#about to read 3, iclass 15, count 2 2006.259.08:15:03.09#ibcon#read 3, iclass 15, count 2 2006.259.08:15:03.09#ibcon#about to read 4, iclass 15, count 2 2006.259.08:15:03.09#ibcon#read 4, iclass 15, count 2 2006.259.08:15:03.09#ibcon#about to read 5, iclass 15, count 2 2006.259.08:15:03.09#ibcon#read 5, iclass 15, count 2 2006.259.08:15:03.09#ibcon#about to read 6, iclass 15, count 2 2006.259.08:15:03.09#ibcon#read 6, iclass 15, count 2 2006.259.08:15:03.09#ibcon#end of sib2, iclass 15, count 2 2006.259.08:15:03.09#ibcon#*after write, iclass 15, count 2 2006.259.08:15:03.09#ibcon#*before return 0, iclass 15, count 2 2006.259.08:15:03.09#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.259.08:15:03.09#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.259.08:15:03.09#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.259.08:15:03.09#ibcon#ireg 7 cls_cnt 0 2006.259.08:15:03.09#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.259.08:15:03.21#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.259.08:15:03.21#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.259.08:15:03.21#ibcon#enter wrdev, iclass 15, count 0 2006.259.08:15:03.21#ibcon#first serial, iclass 15, count 0 2006.259.08:15:03.21#ibcon#enter sib2, iclass 15, count 0 2006.259.08:15:03.21#ibcon#flushed, iclass 15, count 0 2006.259.08:15:03.21#ibcon#about to write, iclass 15, count 0 2006.259.08:15:03.21#ibcon#wrote, iclass 15, count 0 2006.259.08:15:03.21#ibcon#about to read 3, iclass 15, count 0 2006.259.08:15:03.23#ibcon#read 3, iclass 15, count 0 2006.259.08:15:03.23#ibcon#about to read 4, iclass 15, count 0 2006.259.08:15:03.23#ibcon#read 4, iclass 15, count 0 2006.259.08:15:03.23#ibcon#about to read 5, iclass 15, count 0 2006.259.08:15:03.23#ibcon#read 5, iclass 15, count 0 2006.259.08:15:03.23#ibcon#about to read 6, iclass 15, count 0 2006.259.08:15:03.23#ibcon#read 6, iclass 15, count 0 2006.259.08:15:03.23#ibcon#end of sib2, iclass 15, count 0 2006.259.08:15:03.23#ibcon#*mode == 0, iclass 15, count 0 2006.259.08:15:03.23#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.259.08:15:03.23#ibcon#[27=USB\r\n] 2006.259.08:15:03.23#ibcon#*before write, iclass 15, count 0 2006.259.08:15:03.23#ibcon#enter sib2, iclass 15, count 0 2006.259.08:15:03.23#ibcon#flushed, iclass 15, count 0 2006.259.08:15:03.23#ibcon#about to write, iclass 15, count 0 2006.259.08:15:03.23#ibcon#wrote, iclass 15, count 0 2006.259.08:15:03.23#ibcon#about to read 3, iclass 15, count 0 2006.259.08:15:03.26#ibcon#read 3, iclass 15, count 0 2006.259.08:15:03.26#ibcon#about to read 4, iclass 15, count 0 2006.259.08:15:03.26#ibcon#read 4, iclass 15, count 0 2006.259.08:15:03.26#ibcon#about to read 5, iclass 15, count 0 2006.259.08:15:03.26#ibcon#read 5, iclass 15, count 0 2006.259.08:15:03.26#ibcon#about to read 6, iclass 15, count 0 2006.259.08:15:03.26#ibcon#read 6, iclass 15, count 0 2006.259.08:15:03.26#ibcon#end of sib2, iclass 15, count 0 2006.259.08:15:03.26#ibcon#*after write, iclass 15, count 0 2006.259.08:15:03.26#ibcon#*before return 0, iclass 15, count 0 2006.259.08:15:03.26#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.259.08:15:03.26#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.259.08:15:03.26#ibcon#about to clear, iclass 15 cls_cnt 0 2006.259.08:15:03.26#ibcon#cleared, iclass 15 cls_cnt 0 2006.259.08:15:03.26$vc4f8/vabw=wide 2006.259.08:15:03.26#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.259.08:15:03.26#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.259.08:15:03.26#ibcon#ireg 8 cls_cnt 0 2006.259.08:15:03.26#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.259.08:15:03.26#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.259.08:15:03.26#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.259.08:15:03.26#ibcon#enter wrdev, iclass 17, count 0 2006.259.08:15:03.26#ibcon#first serial, iclass 17, count 0 2006.259.08:15:03.26#ibcon#enter sib2, iclass 17, count 0 2006.259.08:15:03.26#ibcon#flushed, iclass 17, count 0 2006.259.08:15:03.26#ibcon#about to write, iclass 17, count 0 2006.259.08:15:03.26#ibcon#wrote, iclass 17, count 0 2006.259.08:15:03.26#ibcon#about to read 3, iclass 17, count 0 2006.259.08:15:03.28#ibcon#read 3, iclass 17, count 0 2006.259.08:15:03.28#ibcon#about to read 4, iclass 17, count 0 2006.259.08:15:03.28#ibcon#read 4, iclass 17, count 0 2006.259.08:15:03.28#ibcon#about to read 5, iclass 17, count 0 2006.259.08:15:03.28#ibcon#read 5, iclass 17, count 0 2006.259.08:15:03.28#ibcon#about to read 6, iclass 17, count 0 2006.259.08:15:03.28#ibcon#read 6, iclass 17, count 0 2006.259.08:15:03.28#ibcon#end of sib2, iclass 17, count 0 2006.259.08:15:03.28#ibcon#*mode == 0, iclass 17, count 0 2006.259.08:15:03.28#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.259.08:15:03.28#ibcon#[25=BW32\r\n] 2006.259.08:15:03.28#ibcon#*before write, iclass 17, count 0 2006.259.08:15:03.28#ibcon#enter sib2, iclass 17, count 0 2006.259.08:15:03.28#ibcon#flushed, iclass 17, count 0 2006.259.08:15:03.28#ibcon#about to write, iclass 17, count 0 2006.259.08:15:03.28#ibcon#wrote, iclass 17, count 0 2006.259.08:15:03.28#ibcon#about to read 3, iclass 17, count 0 2006.259.08:15:03.31#ibcon#read 3, iclass 17, count 0 2006.259.08:15:03.31#ibcon#about to read 4, iclass 17, count 0 2006.259.08:15:03.31#ibcon#read 4, iclass 17, count 0 2006.259.08:15:03.31#ibcon#about to read 5, iclass 17, count 0 2006.259.08:15:03.31#ibcon#read 5, iclass 17, count 0 2006.259.08:15:03.31#ibcon#about to read 6, iclass 17, count 0 2006.259.08:15:03.31#ibcon#read 6, iclass 17, count 0 2006.259.08:15:03.31#ibcon#end of sib2, iclass 17, count 0 2006.259.08:15:03.31#ibcon#*after write, iclass 17, count 0 2006.259.08:15:03.31#ibcon#*before return 0, iclass 17, count 0 2006.259.08:15:03.31#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.259.08:15:03.31#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.259.08:15:03.31#ibcon#about to clear, iclass 17 cls_cnt 0 2006.259.08:15:03.31#ibcon#cleared, iclass 17 cls_cnt 0 2006.259.08:15:03.31$vc4f8/vbbw=wide 2006.259.08:15:03.31#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.259.08:15:03.31#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.259.08:15:03.31#ibcon#ireg 8 cls_cnt 0 2006.259.08:15:03.31#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.259.08:15:03.38#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.259.08:15:03.38#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.259.08:15:03.38#ibcon#enter wrdev, iclass 19, count 0 2006.259.08:15:03.38#ibcon#first serial, iclass 19, count 0 2006.259.08:15:03.38#ibcon#enter sib2, iclass 19, count 0 2006.259.08:15:03.38#ibcon#flushed, iclass 19, count 0 2006.259.08:15:03.38#ibcon#about to write, iclass 19, count 0 2006.259.08:15:03.38#ibcon#wrote, iclass 19, count 0 2006.259.08:15:03.38#ibcon#about to read 3, iclass 19, count 0 2006.259.08:15:03.40#ibcon#read 3, iclass 19, count 0 2006.259.08:15:03.40#ibcon#about to read 4, iclass 19, count 0 2006.259.08:15:03.40#ibcon#read 4, iclass 19, count 0 2006.259.08:15:03.40#ibcon#about to read 5, iclass 19, count 0 2006.259.08:15:03.40#ibcon#read 5, iclass 19, count 0 2006.259.08:15:03.40#ibcon#about to read 6, iclass 19, count 0 2006.259.08:15:03.40#ibcon#read 6, iclass 19, count 0 2006.259.08:15:03.40#ibcon#end of sib2, iclass 19, count 0 2006.259.08:15:03.40#ibcon#*mode == 0, iclass 19, count 0 2006.259.08:15:03.40#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.259.08:15:03.40#ibcon#[27=BW32\r\n] 2006.259.08:15:03.40#ibcon#*before write, iclass 19, count 0 2006.259.08:15:03.40#ibcon#enter sib2, iclass 19, count 0 2006.259.08:15:03.40#ibcon#flushed, iclass 19, count 0 2006.259.08:15:03.40#ibcon#about to write, iclass 19, count 0 2006.259.08:15:03.40#ibcon#wrote, iclass 19, count 0 2006.259.08:15:03.40#ibcon#about to read 3, iclass 19, count 0 2006.259.08:15:03.43#ibcon#read 3, iclass 19, count 0 2006.259.08:15:03.43#ibcon#about to read 4, iclass 19, count 0 2006.259.08:15:03.43#ibcon#read 4, iclass 19, count 0 2006.259.08:15:03.43#ibcon#about to read 5, iclass 19, count 0 2006.259.08:15:03.43#ibcon#read 5, iclass 19, count 0 2006.259.08:15:03.43#ibcon#about to read 6, iclass 19, count 0 2006.259.08:15:03.43#ibcon#read 6, iclass 19, count 0 2006.259.08:15:03.43#ibcon#end of sib2, iclass 19, count 0 2006.259.08:15:03.43#ibcon#*after write, iclass 19, count 0 2006.259.08:15:03.43#ibcon#*before return 0, iclass 19, count 0 2006.259.08:15:03.43#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.259.08:15:03.43#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.259.08:15:03.43#ibcon#about to clear, iclass 19 cls_cnt 0 2006.259.08:15:03.43#ibcon#cleared, iclass 19 cls_cnt 0 2006.259.08:15:03.43$4f8m12a/ifd4f 2006.259.08:15:03.43$ifd4f/lo= 2006.259.08:15:03.43$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.259.08:15:03.43$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.259.08:15:03.43$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.259.08:15:03.43$ifd4f/patch= 2006.259.08:15:03.43$ifd4f/patch=lo1,a1,a2,a3,a4 2006.259.08:15:03.43$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.259.08:15:03.43$ifd4f/patch=lo3,a5,a6,a7,a8 2006.259.08:15:03.43$4f8m12a/"form=m,16.000,1:2 2006.259.08:15:03.43$4f8m12a/"tpicd 2006.259.08:15:03.43$4f8m12a/echo=off 2006.259.08:15:03.43$4f8m12a/xlog=off 2006.259.08:15:03.43:!2006.259.08:15:30 2006.259.08:15:16.14#trakl#Source acquired 2006.259.08:15:18.14#flagr#flagr/antenna,acquired 2006.259.08:15:30.00:preob 2006.259.08:15:31.14/onsource/TRACKING 2006.259.08:15:31.14:!2006.259.08:15:40 2006.259.08:15:40.00:data_valid=on 2006.259.08:15:40.00:midob 2006.259.08:15:40.14/onsource/TRACKING 2006.259.08:15:40.14/wx/21.91,1013.1,86 2006.259.08:15:40.24/cable/+6.4587E-03 2006.259.08:15:41.33/va/01,08,usb,yes,33,34 2006.259.08:15:41.33/va/02,07,usb,yes,33,34 2006.259.08:15:41.33/va/03,08,usb,yes,25,25 2006.259.08:15:41.33/va/04,07,usb,yes,34,37 2006.259.08:15:41.33/va/05,07,usb,yes,38,40 2006.259.08:15:41.33/va/06,06,usb,yes,37,37 2006.259.08:15:41.33/va/07,06,usb,yes,38,37 2006.259.08:15:41.33/va/08,06,usb,yes,40,39 2006.259.08:15:41.56/valo/01,532.99,yes,locked 2006.259.08:15:41.56/valo/02,572.99,yes,locked 2006.259.08:15:41.56/valo/03,672.99,yes,locked 2006.259.08:15:41.56/valo/04,832.99,yes,locked 2006.259.08:15:41.56/valo/05,652.99,yes,locked 2006.259.08:15:41.56/valo/06,772.99,yes,locked 2006.259.08:15:41.56/valo/07,832.99,yes,locked 2006.259.08:15:41.56/valo/08,852.99,yes,locked 2006.259.08:15:42.65/vb/01,04,usb,yes,32,30 2006.259.08:15:42.65/vb/02,05,usb,yes,29,31 2006.259.08:15:42.65/vb/03,04,usb,yes,30,34 2006.259.08:15:42.65/vb/04,05,usb,yes,27,27 2006.259.08:15:42.65/vb/05,04,usb,yes,29,33 2006.259.08:15:42.65/vb/06,04,usb,yes,30,33 2006.259.08:15:42.65/vb/07,04,usb,yes,32,32 2006.259.08:15:42.65/vb/08,04,usb,yes,30,33 2006.259.08:15:42.88/vblo/01,632.99,yes,locked 2006.259.08:15:42.88/vblo/02,640.99,yes,locked 2006.259.08:15:42.88/vblo/03,656.99,yes,locked 2006.259.08:15:42.88/vblo/04,712.99,yes,locked 2006.259.08:15:42.88/vblo/05,744.99,yes,locked 2006.259.08:15:42.88/vblo/06,752.99,yes,locked 2006.259.08:15:42.88/vblo/07,734.99,yes,locked 2006.259.08:15:42.88/vblo/08,744.99,yes,locked 2006.259.08:15:43.03/vabw/8 2006.259.08:15:43.18/vbbw/8 2006.259.08:15:43.27/xfe/off,on,15.5 2006.259.08:15:43.66/ifatt/23,28,28,28 2006.259.08:15:44.08/fmout-gps/S +4.61E-07 2006.259.08:15:44.12:!2006.259.08:16:40 2006.259.08:16:40.00:data_valid=off 2006.259.08:16:40.00:postob 2006.259.08:16:40.11/cable/+6.4580E-03 2006.259.08:16:40.11/wx/21.89,1013.1,86 2006.259.08:16:41.08/fmout-gps/S +4.60E-07 2006.259.08:16:41.08:scan_name=259-0817,k06259,60 2006.259.08:16:41.09:source=1300+580,130252.47,574837.6,2000.0,ccw 2006.259.08:16:41.14#flagr#flagr/antenna,new-source 2006.259.08:16:42.14:checkk5 2006.259.08:16:42.57/chk_autoobs//k5ts1/ autoobs is running! 2006.259.08:16:42.97/chk_autoobs//k5ts2/ autoobs is running! 2006.259.08:16:43.44/chk_autoobs//k5ts3/ autoobs is running! 2006.259.08:16:43.86/chk_autoobs//k5ts4/ autoobs is running! 2006.259.08:16:44.26/chk_obsdata//k5ts1/T2590815??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.259.08:16:44.66/chk_obsdata//k5ts2/T2590815??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.259.08:16:45.27/chk_obsdata//k5ts3/T2590815??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.259.08:16:45.65/chk_obsdata//k5ts4/T2590815??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.259.08:16:46.45/k5log//k5ts1_log_newline 2006.259.08:16:47.23/k5log//k5ts2_log_newline 2006.259.08:16:48.01/k5log//k5ts3_log_newline 2006.259.08:16:53.76/k5log//k5ts4_log_newline 2006.259.08:16:53.78/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.259.08:16:53.78:4f8m12a=2 2006.259.08:16:53.78$4f8m12a/echo=on 2006.259.08:16:53.78$4f8m12a/pcalon 2006.259.08:16:53.78$pcalon/"no phase cal control is implemented here 2006.259.08:16:53.78$4f8m12a/"tpicd=stop 2006.259.08:16:53.78$4f8m12a/vc4f8 2006.259.08:16:53.78$vc4f8/valo=1,532.99 2006.259.08:16:53.79#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.259.08:16:53.79#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.259.08:16:53.79#ibcon#ireg 17 cls_cnt 0 2006.259.08:16:53.79#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.259.08:16:53.79#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.259.08:16:53.79#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.259.08:16:53.79#ibcon#enter wrdev, iclass 30, count 0 2006.259.08:16:53.79#ibcon#first serial, iclass 30, count 0 2006.259.08:16:53.79#ibcon#enter sib2, iclass 30, count 0 2006.259.08:16:53.79#ibcon#flushed, iclass 30, count 0 2006.259.08:16:53.79#ibcon#about to write, iclass 30, count 0 2006.259.08:16:53.79#ibcon#wrote, iclass 30, count 0 2006.259.08:16:53.79#ibcon#about to read 3, iclass 30, count 0 2006.259.08:16:53.83#ibcon#read 3, iclass 30, count 0 2006.259.08:16:53.83#ibcon#about to read 4, iclass 30, count 0 2006.259.08:16:53.83#ibcon#read 4, iclass 30, count 0 2006.259.08:16:53.83#ibcon#about to read 5, iclass 30, count 0 2006.259.08:16:53.83#ibcon#read 5, iclass 30, count 0 2006.259.08:16:53.83#ibcon#about to read 6, iclass 30, count 0 2006.259.08:16:53.83#ibcon#read 6, iclass 30, count 0 2006.259.08:16:53.83#ibcon#end of sib2, iclass 30, count 0 2006.259.08:16:53.83#ibcon#*mode == 0, iclass 30, count 0 2006.259.08:16:53.83#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.259.08:16:53.83#ibcon#[26=FRQ=01,532.99\r\n] 2006.259.08:16:53.83#ibcon#*before write, iclass 30, count 0 2006.259.08:16:53.83#ibcon#enter sib2, iclass 30, count 0 2006.259.08:16:53.83#ibcon#flushed, iclass 30, count 0 2006.259.08:16:53.83#ibcon#about to write, iclass 30, count 0 2006.259.08:16:53.83#ibcon#wrote, iclass 30, count 0 2006.259.08:16:53.83#ibcon#about to read 3, iclass 30, count 0 2006.259.08:16:53.88#ibcon#read 3, iclass 30, count 0 2006.259.08:16:53.88#ibcon#about to read 4, iclass 30, count 0 2006.259.08:16:53.88#ibcon#read 4, iclass 30, count 0 2006.259.08:16:53.88#ibcon#about to read 5, iclass 30, count 0 2006.259.08:16:53.88#ibcon#read 5, iclass 30, count 0 2006.259.08:16:53.88#ibcon#about to read 6, iclass 30, count 0 2006.259.08:16:53.88#ibcon#read 6, iclass 30, count 0 2006.259.08:16:53.88#ibcon#end of sib2, iclass 30, count 0 2006.259.08:16:53.88#ibcon#*after write, iclass 30, count 0 2006.259.08:16:53.88#ibcon#*before return 0, iclass 30, count 0 2006.259.08:16:53.88#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.259.08:16:53.88#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.259.08:16:53.88#ibcon#about to clear, iclass 30 cls_cnt 0 2006.259.08:16:53.88#ibcon#cleared, iclass 30 cls_cnt 0 2006.259.08:16:53.88$vc4f8/va=1,8 2006.259.08:16:53.88#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.259.08:16:53.88#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.259.08:16:53.88#ibcon#ireg 11 cls_cnt 2 2006.259.08:16:53.88#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.259.08:16:53.88#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.259.08:16:53.88#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.259.08:16:53.88#ibcon#enter wrdev, iclass 32, count 2 2006.259.08:16:53.88#ibcon#first serial, iclass 32, count 2 2006.259.08:16:53.88#ibcon#enter sib2, iclass 32, count 2 2006.259.08:16:53.88#ibcon#flushed, iclass 32, count 2 2006.259.08:16:53.88#ibcon#about to write, iclass 32, count 2 2006.259.08:16:53.88#ibcon#wrote, iclass 32, count 2 2006.259.08:16:53.88#ibcon#about to read 3, iclass 32, count 2 2006.259.08:16:53.90#ibcon#read 3, iclass 32, count 2 2006.259.08:16:53.90#ibcon#about to read 4, iclass 32, count 2 2006.259.08:16:53.90#ibcon#read 4, iclass 32, count 2 2006.259.08:16:53.90#ibcon#about to read 5, iclass 32, count 2 2006.259.08:16:53.90#ibcon#read 5, iclass 32, count 2 2006.259.08:16:53.90#ibcon#about to read 6, iclass 32, count 2 2006.259.08:16:53.90#ibcon#read 6, iclass 32, count 2 2006.259.08:16:53.90#ibcon#end of sib2, iclass 32, count 2 2006.259.08:16:53.90#ibcon#*mode == 0, iclass 32, count 2 2006.259.08:16:53.90#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.259.08:16:53.90#ibcon#[25=AT01-08\r\n] 2006.259.08:16:53.90#ibcon#*before write, iclass 32, count 2 2006.259.08:16:53.90#ibcon#enter sib2, iclass 32, count 2 2006.259.08:16:53.90#ibcon#flushed, iclass 32, count 2 2006.259.08:16:53.90#ibcon#about to write, iclass 32, count 2 2006.259.08:16:53.90#ibcon#wrote, iclass 32, count 2 2006.259.08:16:53.90#ibcon#about to read 3, iclass 32, count 2 2006.259.08:16:53.93#ibcon#read 3, iclass 32, count 2 2006.259.08:16:53.93#ibcon#about to read 4, iclass 32, count 2 2006.259.08:16:53.93#ibcon#read 4, iclass 32, count 2 2006.259.08:16:53.93#ibcon#about to read 5, iclass 32, count 2 2006.259.08:16:53.93#ibcon#read 5, iclass 32, count 2 2006.259.08:16:53.93#ibcon#about to read 6, iclass 32, count 2 2006.259.08:16:53.93#ibcon#read 6, iclass 32, count 2 2006.259.08:16:53.93#ibcon#end of sib2, iclass 32, count 2 2006.259.08:16:53.93#ibcon#*after write, iclass 32, count 2 2006.259.08:16:53.93#ibcon#*before return 0, iclass 32, count 2 2006.259.08:16:53.93#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.259.08:16:53.93#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.259.08:16:53.93#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.259.08:16:53.93#ibcon#ireg 7 cls_cnt 0 2006.259.08:16:53.93#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.259.08:16:54.05#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.259.08:16:54.05#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.259.08:16:54.05#ibcon#enter wrdev, iclass 32, count 0 2006.259.08:16:54.05#ibcon#first serial, iclass 32, count 0 2006.259.08:16:54.05#ibcon#enter sib2, iclass 32, count 0 2006.259.08:16:54.05#ibcon#flushed, iclass 32, count 0 2006.259.08:16:54.05#ibcon#about to write, iclass 32, count 0 2006.259.08:16:54.05#ibcon#wrote, iclass 32, count 0 2006.259.08:16:54.05#ibcon#about to read 3, iclass 32, count 0 2006.259.08:16:54.07#ibcon#read 3, iclass 32, count 0 2006.259.08:16:54.07#ibcon#about to read 4, iclass 32, count 0 2006.259.08:16:54.07#ibcon#read 4, iclass 32, count 0 2006.259.08:16:54.07#ibcon#about to read 5, iclass 32, count 0 2006.259.08:16:54.07#ibcon#read 5, iclass 32, count 0 2006.259.08:16:54.07#ibcon#about to read 6, iclass 32, count 0 2006.259.08:16:54.07#ibcon#read 6, iclass 32, count 0 2006.259.08:16:54.07#ibcon#end of sib2, iclass 32, count 0 2006.259.08:16:54.07#ibcon#*mode == 0, iclass 32, count 0 2006.259.08:16:54.07#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.259.08:16:54.07#ibcon#[25=USB\r\n] 2006.259.08:16:54.07#ibcon#*before write, iclass 32, count 0 2006.259.08:16:54.07#ibcon#enter sib2, iclass 32, count 0 2006.259.08:16:54.07#ibcon#flushed, iclass 32, count 0 2006.259.08:16:54.07#ibcon#about to write, iclass 32, count 0 2006.259.08:16:54.07#ibcon#wrote, iclass 32, count 0 2006.259.08:16:54.07#ibcon#about to read 3, iclass 32, count 0 2006.259.08:16:54.10#ibcon#read 3, iclass 32, count 0 2006.259.08:16:54.10#ibcon#about to read 4, iclass 32, count 0 2006.259.08:16:54.10#ibcon#read 4, iclass 32, count 0 2006.259.08:16:54.10#ibcon#about to read 5, iclass 32, count 0 2006.259.08:16:54.10#ibcon#read 5, iclass 32, count 0 2006.259.08:16:54.10#ibcon#about to read 6, iclass 32, count 0 2006.259.08:16:54.10#ibcon#read 6, iclass 32, count 0 2006.259.08:16:54.10#ibcon#end of sib2, iclass 32, count 0 2006.259.08:16:54.10#ibcon#*after write, iclass 32, count 0 2006.259.08:16:54.10#ibcon#*before return 0, iclass 32, count 0 2006.259.08:16:54.10#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.259.08:16:54.10#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.259.08:16:54.10#ibcon#about to clear, iclass 32 cls_cnt 0 2006.259.08:16:54.10#ibcon#cleared, iclass 32 cls_cnt 0 2006.259.08:16:54.10$vc4f8/valo=2,572.99 2006.259.08:16:54.10#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.259.08:16:54.10#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.259.08:16:54.10#ibcon#ireg 17 cls_cnt 0 2006.259.08:16:54.10#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.259.08:16:54.10#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.259.08:16:54.10#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.259.08:16:54.10#ibcon#enter wrdev, iclass 34, count 0 2006.259.08:16:54.10#ibcon#first serial, iclass 34, count 0 2006.259.08:16:54.10#ibcon#enter sib2, iclass 34, count 0 2006.259.08:16:54.10#ibcon#flushed, iclass 34, count 0 2006.259.08:16:54.10#ibcon#about to write, iclass 34, count 0 2006.259.08:16:54.10#ibcon#wrote, iclass 34, count 0 2006.259.08:16:54.10#ibcon#about to read 3, iclass 34, count 0 2006.259.08:16:54.12#ibcon#read 3, iclass 34, count 0 2006.259.08:16:54.12#ibcon#about to read 4, iclass 34, count 0 2006.259.08:16:54.12#ibcon#read 4, iclass 34, count 0 2006.259.08:16:54.12#ibcon#about to read 5, iclass 34, count 0 2006.259.08:16:54.12#ibcon#read 5, iclass 34, count 0 2006.259.08:16:54.12#ibcon#about to read 6, iclass 34, count 0 2006.259.08:16:54.12#ibcon#read 6, iclass 34, count 0 2006.259.08:16:54.12#ibcon#end of sib2, iclass 34, count 0 2006.259.08:16:54.12#ibcon#*mode == 0, iclass 34, count 0 2006.259.08:16:54.12#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.259.08:16:54.12#ibcon#[26=FRQ=02,572.99\r\n] 2006.259.08:16:54.12#ibcon#*before write, iclass 34, count 0 2006.259.08:16:54.12#ibcon#enter sib2, iclass 34, count 0 2006.259.08:16:54.12#ibcon#flushed, iclass 34, count 0 2006.259.08:16:54.12#ibcon#about to write, iclass 34, count 0 2006.259.08:16:54.12#ibcon#wrote, iclass 34, count 0 2006.259.08:16:54.12#ibcon#about to read 3, iclass 34, count 0 2006.259.08:16:54.16#ibcon#read 3, iclass 34, count 0 2006.259.08:16:54.16#ibcon#about to read 4, iclass 34, count 0 2006.259.08:16:54.16#ibcon#read 4, iclass 34, count 0 2006.259.08:16:54.16#ibcon#about to read 5, iclass 34, count 0 2006.259.08:16:54.16#ibcon#read 5, iclass 34, count 0 2006.259.08:16:54.16#ibcon#about to read 6, iclass 34, count 0 2006.259.08:16:54.16#ibcon#read 6, iclass 34, count 0 2006.259.08:16:54.16#ibcon#end of sib2, iclass 34, count 0 2006.259.08:16:54.16#ibcon#*after write, iclass 34, count 0 2006.259.08:16:54.16#ibcon#*before return 0, iclass 34, count 0 2006.259.08:16:54.16#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.259.08:16:54.16#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.259.08:16:54.16#ibcon#about to clear, iclass 34 cls_cnt 0 2006.259.08:16:54.16#ibcon#cleared, iclass 34 cls_cnt 0 2006.259.08:16:54.16$vc4f8/va=2,7 2006.259.08:16:54.16#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.259.08:16:54.16#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.259.08:16:54.16#ibcon#ireg 11 cls_cnt 2 2006.259.08:16:54.16#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.259.08:16:54.22#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.259.08:16:54.22#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.259.08:16:54.22#ibcon#enter wrdev, iclass 36, count 2 2006.259.08:16:54.22#ibcon#first serial, iclass 36, count 2 2006.259.08:16:54.22#ibcon#enter sib2, iclass 36, count 2 2006.259.08:16:54.22#ibcon#flushed, iclass 36, count 2 2006.259.08:16:54.22#ibcon#about to write, iclass 36, count 2 2006.259.08:16:54.22#ibcon#wrote, iclass 36, count 2 2006.259.08:16:54.22#ibcon#about to read 3, iclass 36, count 2 2006.259.08:16:54.24#ibcon#read 3, iclass 36, count 2 2006.259.08:16:54.24#ibcon#about to read 4, iclass 36, count 2 2006.259.08:16:54.24#ibcon#read 4, iclass 36, count 2 2006.259.08:16:54.24#ibcon#about to read 5, iclass 36, count 2 2006.259.08:16:54.24#ibcon#read 5, iclass 36, count 2 2006.259.08:16:54.24#ibcon#about to read 6, iclass 36, count 2 2006.259.08:16:54.24#ibcon#read 6, iclass 36, count 2 2006.259.08:16:54.24#ibcon#end of sib2, iclass 36, count 2 2006.259.08:16:54.24#ibcon#*mode == 0, iclass 36, count 2 2006.259.08:16:54.24#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.259.08:16:54.24#ibcon#[25=AT02-07\r\n] 2006.259.08:16:54.24#ibcon#*before write, iclass 36, count 2 2006.259.08:16:54.24#ibcon#enter sib2, iclass 36, count 2 2006.259.08:16:54.24#ibcon#flushed, iclass 36, count 2 2006.259.08:16:54.24#ibcon#about to write, iclass 36, count 2 2006.259.08:16:54.24#ibcon#wrote, iclass 36, count 2 2006.259.08:16:54.24#ibcon#about to read 3, iclass 36, count 2 2006.259.08:16:54.27#ibcon#read 3, iclass 36, count 2 2006.259.08:16:54.27#ibcon#about to read 4, iclass 36, count 2 2006.259.08:16:54.27#ibcon#read 4, iclass 36, count 2 2006.259.08:16:54.27#ibcon#about to read 5, iclass 36, count 2 2006.259.08:16:54.27#ibcon#read 5, iclass 36, count 2 2006.259.08:16:54.27#ibcon#about to read 6, iclass 36, count 2 2006.259.08:16:54.27#ibcon#read 6, iclass 36, count 2 2006.259.08:16:54.27#ibcon#end of sib2, iclass 36, count 2 2006.259.08:16:54.27#ibcon#*after write, iclass 36, count 2 2006.259.08:16:54.27#ibcon#*before return 0, iclass 36, count 2 2006.259.08:16:54.27#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.259.08:16:54.27#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.259.08:16:54.27#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.259.08:16:54.27#ibcon#ireg 7 cls_cnt 0 2006.259.08:16:54.27#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.259.08:16:54.39#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.259.08:16:54.39#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.259.08:16:54.39#ibcon#enter wrdev, iclass 36, count 0 2006.259.08:16:54.39#ibcon#first serial, iclass 36, count 0 2006.259.08:16:54.39#ibcon#enter sib2, iclass 36, count 0 2006.259.08:16:54.39#ibcon#flushed, iclass 36, count 0 2006.259.08:16:54.39#ibcon#about to write, iclass 36, count 0 2006.259.08:16:54.39#ibcon#wrote, iclass 36, count 0 2006.259.08:16:54.39#ibcon#about to read 3, iclass 36, count 0 2006.259.08:16:54.41#ibcon#read 3, iclass 36, count 0 2006.259.08:16:54.41#ibcon#about to read 4, iclass 36, count 0 2006.259.08:16:54.41#ibcon#read 4, iclass 36, count 0 2006.259.08:16:54.41#ibcon#about to read 5, iclass 36, count 0 2006.259.08:16:54.41#ibcon#read 5, iclass 36, count 0 2006.259.08:16:54.41#ibcon#about to read 6, iclass 36, count 0 2006.259.08:16:54.41#ibcon#read 6, iclass 36, count 0 2006.259.08:16:54.41#ibcon#end of sib2, iclass 36, count 0 2006.259.08:16:54.41#ibcon#*mode == 0, iclass 36, count 0 2006.259.08:16:54.41#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.259.08:16:54.41#ibcon#[25=USB\r\n] 2006.259.08:16:54.41#ibcon#*before write, iclass 36, count 0 2006.259.08:16:54.41#ibcon#enter sib2, iclass 36, count 0 2006.259.08:16:54.41#ibcon#flushed, iclass 36, count 0 2006.259.08:16:54.41#ibcon#about to write, iclass 36, count 0 2006.259.08:16:54.41#ibcon#wrote, iclass 36, count 0 2006.259.08:16:54.41#ibcon#about to read 3, iclass 36, count 0 2006.259.08:16:54.44#ibcon#read 3, iclass 36, count 0 2006.259.08:16:54.44#ibcon#about to read 4, iclass 36, count 0 2006.259.08:16:54.44#ibcon#read 4, iclass 36, count 0 2006.259.08:16:54.44#ibcon#about to read 5, iclass 36, count 0 2006.259.08:16:54.44#ibcon#read 5, iclass 36, count 0 2006.259.08:16:54.44#ibcon#about to read 6, iclass 36, count 0 2006.259.08:16:54.44#ibcon#read 6, iclass 36, count 0 2006.259.08:16:54.44#ibcon#end of sib2, iclass 36, count 0 2006.259.08:16:54.44#ibcon#*after write, iclass 36, count 0 2006.259.08:16:54.44#ibcon#*before return 0, iclass 36, count 0 2006.259.08:16:54.44#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.259.08:16:54.44#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.259.08:16:54.44#ibcon#about to clear, iclass 36 cls_cnt 0 2006.259.08:16:54.44#ibcon#cleared, iclass 36 cls_cnt 0 2006.259.08:16:54.44$vc4f8/valo=3,672.99 2006.259.08:16:54.44#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.259.08:16:54.44#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.259.08:16:54.44#ibcon#ireg 17 cls_cnt 0 2006.259.08:16:54.44#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.259.08:16:54.44#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.259.08:16:54.44#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.259.08:16:54.44#ibcon#enter wrdev, iclass 38, count 0 2006.259.08:16:54.44#ibcon#first serial, iclass 38, count 0 2006.259.08:16:54.44#ibcon#enter sib2, iclass 38, count 0 2006.259.08:16:54.44#ibcon#flushed, iclass 38, count 0 2006.259.08:16:54.44#ibcon#about to write, iclass 38, count 0 2006.259.08:16:54.44#ibcon#wrote, iclass 38, count 0 2006.259.08:16:54.44#ibcon#about to read 3, iclass 38, count 0 2006.259.08:16:54.47#ibcon#read 3, iclass 38, count 0 2006.259.08:16:54.47#ibcon#about to read 4, iclass 38, count 0 2006.259.08:16:54.47#ibcon#read 4, iclass 38, count 0 2006.259.08:16:54.47#ibcon#about to read 5, iclass 38, count 0 2006.259.08:16:54.47#ibcon#read 5, iclass 38, count 0 2006.259.08:16:54.47#ibcon#about to read 6, iclass 38, count 0 2006.259.08:16:54.47#ibcon#read 6, iclass 38, count 0 2006.259.08:16:54.47#ibcon#end of sib2, iclass 38, count 0 2006.259.08:16:54.47#ibcon#*mode == 0, iclass 38, count 0 2006.259.08:16:54.47#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.259.08:16:54.47#ibcon#[26=FRQ=03,672.99\r\n] 2006.259.08:16:54.47#ibcon#*before write, iclass 38, count 0 2006.259.08:16:54.47#ibcon#enter sib2, iclass 38, count 0 2006.259.08:16:54.47#ibcon#flushed, iclass 38, count 0 2006.259.08:16:54.47#ibcon#about to write, iclass 38, count 0 2006.259.08:16:54.47#ibcon#wrote, iclass 38, count 0 2006.259.08:16:54.47#ibcon#about to read 3, iclass 38, count 0 2006.259.08:16:54.51#ibcon#read 3, iclass 38, count 0 2006.259.08:16:54.51#ibcon#about to read 4, iclass 38, count 0 2006.259.08:16:54.51#ibcon#read 4, iclass 38, count 0 2006.259.08:16:54.51#ibcon#about to read 5, iclass 38, count 0 2006.259.08:16:54.51#ibcon#read 5, iclass 38, count 0 2006.259.08:16:54.51#ibcon#about to read 6, iclass 38, count 0 2006.259.08:16:54.51#ibcon#read 6, iclass 38, count 0 2006.259.08:16:54.51#ibcon#end of sib2, iclass 38, count 0 2006.259.08:16:54.51#ibcon#*after write, iclass 38, count 0 2006.259.08:16:54.51#ibcon#*before return 0, iclass 38, count 0 2006.259.08:16:54.51#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.259.08:16:54.51#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.259.08:16:54.51#ibcon#about to clear, iclass 38 cls_cnt 0 2006.259.08:16:54.51#ibcon#cleared, iclass 38 cls_cnt 0 2006.259.08:16:54.51$vc4f8/va=3,8 2006.259.08:16:54.51#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.259.08:16:54.51#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.259.08:16:54.51#ibcon#ireg 11 cls_cnt 2 2006.259.08:16:54.51#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.259.08:16:54.56#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.259.08:16:54.56#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.259.08:16:54.56#ibcon#enter wrdev, iclass 40, count 2 2006.259.08:16:54.56#ibcon#first serial, iclass 40, count 2 2006.259.08:16:54.56#ibcon#enter sib2, iclass 40, count 2 2006.259.08:16:54.56#ibcon#flushed, iclass 40, count 2 2006.259.08:16:54.56#ibcon#about to write, iclass 40, count 2 2006.259.08:16:54.56#ibcon#wrote, iclass 40, count 2 2006.259.08:16:54.56#ibcon#about to read 3, iclass 40, count 2 2006.259.08:16:54.59#ibcon#read 3, iclass 40, count 2 2006.259.08:16:54.59#ibcon#about to read 4, iclass 40, count 2 2006.259.08:16:54.59#ibcon#read 4, iclass 40, count 2 2006.259.08:16:54.59#ibcon#about to read 5, iclass 40, count 2 2006.259.08:16:54.59#ibcon#read 5, iclass 40, count 2 2006.259.08:16:54.59#ibcon#about to read 6, iclass 40, count 2 2006.259.08:16:54.59#ibcon#read 6, iclass 40, count 2 2006.259.08:16:54.59#ibcon#end of sib2, iclass 40, count 2 2006.259.08:16:54.59#ibcon#*mode == 0, iclass 40, count 2 2006.259.08:16:54.59#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.259.08:16:54.59#ibcon#[25=AT03-08\r\n] 2006.259.08:16:54.59#ibcon#*before write, iclass 40, count 2 2006.259.08:16:54.59#ibcon#enter sib2, iclass 40, count 2 2006.259.08:16:54.59#ibcon#flushed, iclass 40, count 2 2006.259.08:16:54.59#ibcon#about to write, iclass 40, count 2 2006.259.08:16:54.59#ibcon#wrote, iclass 40, count 2 2006.259.08:16:54.59#ibcon#about to read 3, iclass 40, count 2 2006.259.08:16:54.62#ibcon#read 3, iclass 40, count 2 2006.259.08:16:54.62#ibcon#about to read 4, iclass 40, count 2 2006.259.08:16:54.62#ibcon#read 4, iclass 40, count 2 2006.259.08:16:54.62#ibcon#about to read 5, iclass 40, count 2 2006.259.08:16:54.62#ibcon#read 5, iclass 40, count 2 2006.259.08:16:54.62#ibcon#about to read 6, iclass 40, count 2 2006.259.08:16:54.62#ibcon#read 6, iclass 40, count 2 2006.259.08:16:54.62#ibcon#end of sib2, iclass 40, count 2 2006.259.08:16:54.62#ibcon#*after write, iclass 40, count 2 2006.259.08:16:54.62#ibcon#*before return 0, iclass 40, count 2 2006.259.08:16:54.62#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.259.08:16:54.62#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.259.08:16:54.62#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.259.08:16:54.62#ibcon#ireg 7 cls_cnt 0 2006.259.08:16:54.62#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.259.08:16:54.74#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.259.08:16:54.74#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.259.08:16:54.74#ibcon#enter wrdev, iclass 40, count 0 2006.259.08:16:54.74#ibcon#first serial, iclass 40, count 0 2006.259.08:16:54.74#ibcon#enter sib2, iclass 40, count 0 2006.259.08:16:54.74#ibcon#flushed, iclass 40, count 0 2006.259.08:16:54.74#ibcon#about to write, iclass 40, count 0 2006.259.08:16:54.74#ibcon#wrote, iclass 40, count 0 2006.259.08:16:54.74#ibcon#about to read 3, iclass 40, count 0 2006.259.08:16:54.76#ibcon#read 3, iclass 40, count 0 2006.259.08:16:54.76#ibcon#about to read 4, iclass 40, count 0 2006.259.08:16:54.76#ibcon#read 4, iclass 40, count 0 2006.259.08:16:54.76#ibcon#about to read 5, iclass 40, count 0 2006.259.08:16:54.76#ibcon#read 5, iclass 40, count 0 2006.259.08:16:54.76#ibcon#about to read 6, iclass 40, count 0 2006.259.08:16:54.76#ibcon#read 6, iclass 40, count 0 2006.259.08:16:54.76#ibcon#end of sib2, iclass 40, count 0 2006.259.08:16:54.76#ibcon#*mode == 0, iclass 40, count 0 2006.259.08:16:54.76#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.259.08:16:54.76#ibcon#[25=USB\r\n] 2006.259.08:16:54.76#ibcon#*before write, iclass 40, count 0 2006.259.08:16:54.76#ibcon#enter sib2, iclass 40, count 0 2006.259.08:16:54.76#ibcon#flushed, iclass 40, count 0 2006.259.08:16:54.76#ibcon#about to write, iclass 40, count 0 2006.259.08:16:54.76#ibcon#wrote, iclass 40, count 0 2006.259.08:16:54.76#ibcon#about to read 3, iclass 40, count 0 2006.259.08:16:54.79#ibcon#read 3, iclass 40, count 0 2006.259.08:16:54.79#ibcon#about to read 4, iclass 40, count 0 2006.259.08:16:54.79#ibcon#read 4, iclass 40, count 0 2006.259.08:16:54.79#ibcon#about to read 5, iclass 40, count 0 2006.259.08:16:54.79#ibcon#read 5, iclass 40, count 0 2006.259.08:16:54.79#ibcon#about to read 6, iclass 40, count 0 2006.259.08:16:54.79#ibcon#read 6, iclass 40, count 0 2006.259.08:16:54.79#ibcon#end of sib2, iclass 40, count 0 2006.259.08:16:54.79#ibcon#*after write, iclass 40, count 0 2006.259.08:16:54.79#ibcon#*before return 0, iclass 40, count 0 2006.259.08:16:54.79#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.259.08:16:54.79#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.259.08:16:54.79#ibcon#about to clear, iclass 40 cls_cnt 0 2006.259.08:16:54.79#ibcon#cleared, iclass 40 cls_cnt 0 2006.259.08:16:54.79$vc4f8/valo=4,832.99 2006.259.08:16:54.79#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.259.08:16:54.79#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.259.08:16:54.79#ibcon#ireg 17 cls_cnt 0 2006.259.08:16:54.79#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.259.08:16:54.79#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.259.08:16:54.79#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.259.08:16:54.79#ibcon#enter wrdev, iclass 4, count 0 2006.259.08:16:54.79#ibcon#first serial, iclass 4, count 0 2006.259.08:16:54.79#ibcon#enter sib2, iclass 4, count 0 2006.259.08:16:54.79#ibcon#flushed, iclass 4, count 0 2006.259.08:16:54.79#ibcon#about to write, iclass 4, count 0 2006.259.08:16:54.79#ibcon#wrote, iclass 4, count 0 2006.259.08:16:54.79#ibcon#about to read 3, iclass 4, count 0 2006.259.08:16:54.81#ibcon#read 3, iclass 4, count 0 2006.259.08:16:54.81#ibcon#about to read 4, iclass 4, count 0 2006.259.08:16:54.81#ibcon#read 4, iclass 4, count 0 2006.259.08:16:54.81#ibcon#about to read 5, iclass 4, count 0 2006.259.08:16:54.81#ibcon#read 5, iclass 4, count 0 2006.259.08:16:54.81#ibcon#about to read 6, iclass 4, count 0 2006.259.08:16:54.81#ibcon#read 6, iclass 4, count 0 2006.259.08:16:54.81#ibcon#end of sib2, iclass 4, count 0 2006.259.08:16:54.81#ibcon#*mode == 0, iclass 4, count 0 2006.259.08:16:54.81#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.259.08:16:54.81#ibcon#[26=FRQ=04,832.99\r\n] 2006.259.08:16:54.81#ibcon#*before write, iclass 4, count 0 2006.259.08:16:54.81#ibcon#enter sib2, iclass 4, count 0 2006.259.08:16:54.81#ibcon#flushed, iclass 4, count 0 2006.259.08:16:54.81#ibcon#about to write, iclass 4, count 0 2006.259.08:16:54.81#ibcon#wrote, iclass 4, count 0 2006.259.08:16:54.81#ibcon#about to read 3, iclass 4, count 0 2006.259.08:16:54.85#ibcon#read 3, iclass 4, count 0 2006.259.08:16:54.85#ibcon#about to read 4, iclass 4, count 0 2006.259.08:16:54.85#ibcon#read 4, iclass 4, count 0 2006.259.08:16:54.85#ibcon#about to read 5, iclass 4, count 0 2006.259.08:16:54.85#ibcon#read 5, iclass 4, count 0 2006.259.08:16:54.85#ibcon#about to read 6, iclass 4, count 0 2006.259.08:16:54.85#ibcon#read 6, iclass 4, count 0 2006.259.08:16:54.85#ibcon#end of sib2, iclass 4, count 0 2006.259.08:16:54.85#ibcon#*after write, iclass 4, count 0 2006.259.08:16:54.85#ibcon#*before return 0, iclass 4, count 0 2006.259.08:16:54.85#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.259.08:16:54.85#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.259.08:16:54.85#ibcon#about to clear, iclass 4 cls_cnt 0 2006.259.08:16:54.85#ibcon#cleared, iclass 4 cls_cnt 0 2006.259.08:16:54.85$vc4f8/va=4,7 2006.259.08:16:54.85#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.259.08:16:54.85#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.259.08:16:54.85#ibcon#ireg 11 cls_cnt 2 2006.259.08:16:54.85#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.259.08:16:54.91#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.259.08:16:54.91#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.259.08:16:54.91#ibcon#enter wrdev, iclass 6, count 2 2006.259.08:16:54.91#ibcon#first serial, iclass 6, count 2 2006.259.08:16:54.91#ibcon#enter sib2, iclass 6, count 2 2006.259.08:16:54.91#ibcon#flushed, iclass 6, count 2 2006.259.08:16:54.91#ibcon#about to write, iclass 6, count 2 2006.259.08:16:54.91#ibcon#wrote, iclass 6, count 2 2006.259.08:16:54.91#ibcon#about to read 3, iclass 6, count 2 2006.259.08:16:54.93#ibcon#read 3, iclass 6, count 2 2006.259.08:16:54.93#ibcon#about to read 4, iclass 6, count 2 2006.259.08:16:54.93#ibcon#read 4, iclass 6, count 2 2006.259.08:16:54.93#ibcon#about to read 5, iclass 6, count 2 2006.259.08:16:54.93#ibcon#read 5, iclass 6, count 2 2006.259.08:16:54.93#ibcon#about to read 6, iclass 6, count 2 2006.259.08:16:54.93#ibcon#read 6, iclass 6, count 2 2006.259.08:16:54.93#ibcon#end of sib2, iclass 6, count 2 2006.259.08:16:54.93#ibcon#*mode == 0, iclass 6, count 2 2006.259.08:16:54.93#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.259.08:16:54.93#ibcon#[25=AT04-07\r\n] 2006.259.08:16:54.93#ibcon#*before write, iclass 6, count 2 2006.259.08:16:54.93#ibcon#enter sib2, iclass 6, count 2 2006.259.08:16:54.93#ibcon#flushed, iclass 6, count 2 2006.259.08:16:54.93#ibcon#about to write, iclass 6, count 2 2006.259.08:16:54.93#ibcon#wrote, iclass 6, count 2 2006.259.08:16:54.93#ibcon#about to read 3, iclass 6, count 2 2006.259.08:16:54.96#ibcon#read 3, iclass 6, count 2 2006.259.08:16:54.96#ibcon#about to read 4, iclass 6, count 2 2006.259.08:16:54.96#ibcon#read 4, iclass 6, count 2 2006.259.08:16:54.96#ibcon#about to read 5, iclass 6, count 2 2006.259.08:16:54.96#ibcon#read 5, iclass 6, count 2 2006.259.08:16:54.96#ibcon#about to read 6, iclass 6, count 2 2006.259.08:16:54.96#ibcon#read 6, iclass 6, count 2 2006.259.08:16:54.96#ibcon#end of sib2, iclass 6, count 2 2006.259.08:16:54.96#ibcon#*after write, iclass 6, count 2 2006.259.08:16:54.96#ibcon#*before return 0, iclass 6, count 2 2006.259.08:16:54.96#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.259.08:16:54.96#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.259.08:16:54.96#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.259.08:16:54.96#ibcon#ireg 7 cls_cnt 0 2006.259.08:16:54.96#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.259.08:16:55.08#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.259.08:16:55.08#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.259.08:16:55.08#ibcon#enter wrdev, iclass 6, count 0 2006.259.08:16:55.08#ibcon#first serial, iclass 6, count 0 2006.259.08:16:55.08#ibcon#enter sib2, iclass 6, count 0 2006.259.08:16:55.08#ibcon#flushed, iclass 6, count 0 2006.259.08:16:55.08#ibcon#about to write, iclass 6, count 0 2006.259.08:16:55.08#ibcon#wrote, iclass 6, count 0 2006.259.08:16:55.08#ibcon#about to read 3, iclass 6, count 0 2006.259.08:16:55.10#ibcon#read 3, iclass 6, count 0 2006.259.08:16:55.10#ibcon#about to read 4, iclass 6, count 0 2006.259.08:16:55.10#ibcon#read 4, iclass 6, count 0 2006.259.08:16:55.10#ibcon#about to read 5, iclass 6, count 0 2006.259.08:16:55.10#ibcon#read 5, iclass 6, count 0 2006.259.08:16:55.10#ibcon#about to read 6, iclass 6, count 0 2006.259.08:16:55.10#ibcon#read 6, iclass 6, count 0 2006.259.08:16:55.10#ibcon#end of sib2, iclass 6, count 0 2006.259.08:16:55.10#ibcon#*mode == 0, iclass 6, count 0 2006.259.08:16:55.10#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.259.08:16:55.10#ibcon#[25=USB\r\n] 2006.259.08:16:55.10#ibcon#*before write, iclass 6, count 0 2006.259.08:16:55.10#ibcon#enter sib2, iclass 6, count 0 2006.259.08:16:55.10#ibcon#flushed, iclass 6, count 0 2006.259.08:16:55.10#ibcon#about to write, iclass 6, count 0 2006.259.08:16:55.10#ibcon#wrote, iclass 6, count 0 2006.259.08:16:55.10#ibcon#about to read 3, iclass 6, count 0 2006.259.08:16:55.13#ibcon#read 3, iclass 6, count 0 2006.259.08:16:55.13#ibcon#about to read 4, iclass 6, count 0 2006.259.08:16:55.13#ibcon#read 4, iclass 6, count 0 2006.259.08:16:55.13#ibcon#about to read 5, iclass 6, count 0 2006.259.08:16:55.13#ibcon#read 5, iclass 6, count 0 2006.259.08:16:55.13#ibcon#about to read 6, iclass 6, count 0 2006.259.08:16:55.13#ibcon#read 6, iclass 6, count 0 2006.259.08:16:55.13#ibcon#end of sib2, iclass 6, count 0 2006.259.08:16:55.13#ibcon#*after write, iclass 6, count 0 2006.259.08:16:55.13#ibcon#*before return 0, iclass 6, count 0 2006.259.08:16:55.13#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.259.08:16:55.13#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.259.08:16:55.13#ibcon#about to clear, iclass 6 cls_cnt 0 2006.259.08:16:55.13#ibcon#cleared, iclass 6 cls_cnt 0 2006.259.08:16:55.13$vc4f8/valo=5,652.99 2006.259.08:16:55.13#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.259.08:16:55.13#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.259.08:16:55.13#ibcon#ireg 17 cls_cnt 0 2006.259.08:16:55.13#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.259.08:16:55.13#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.259.08:16:55.13#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.259.08:16:55.13#ibcon#enter wrdev, iclass 10, count 0 2006.259.08:16:55.13#ibcon#first serial, iclass 10, count 0 2006.259.08:16:55.13#ibcon#enter sib2, iclass 10, count 0 2006.259.08:16:55.13#ibcon#flushed, iclass 10, count 0 2006.259.08:16:55.13#ibcon#about to write, iclass 10, count 0 2006.259.08:16:55.13#ibcon#wrote, iclass 10, count 0 2006.259.08:16:55.13#ibcon#about to read 3, iclass 10, count 0 2006.259.08:16:55.15#ibcon#read 3, iclass 10, count 0 2006.259.08:16:55.15#ibcon#about to read 4, iclass 10, count 0 2006.259.08:16:55.15#ibcon#read 4, iclass 10, count 0 2006.259.08:16:55.15#ibcon#about to read 5, iclass 10, count 0 2006.259.08:16:55.15#ibcon#read 5, iclass 10, count 0 2006.259.08:16:55.15#ibcon#about to read 6, iclass 10, count 0 2006.259.08:16:55.15#ibcon#read 6, iclass 10, count 0 2006.259.08:16:55.15#ibcon#end of sib2, iclass 10, count 0 2006.259.08:16:55.15#ibcon#*mode == 0, iclass 10, count 0 2006.259.08:16:55.15#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.259.08:16:55.15#ibcon#[26=FRQ=05,652.99\r\n] 2006.259.08:16:55.15#ibcon#*before write, iclass 10, count 0 2006.259.08:16:55.15#ibcon#enter sib2, iclass 10, count 0 2006.259.08:16:55.15#ibcon#flushed, iclass 10, count 0 2006.259.08:16:55.15#ibcon#about to write, iclass 10, count 0 2006.259.08:16:55.15#ibcon#wrote, iclass 10, count 0 2006.259.08:16:55.15#ibcon#about to read 3, iclass 10, count 0 2006.259.08:16:55.19#ibcon#read 3, iclass 10, count 0 2006.259.08:16:55.19#ibcon#about to read 4, iclass 10, count 0 2006.259.08:16:55.19#ibcon#read 4, iclass 10, count 0 2006.259.08:16:55.19#ibcon#about to read 5, iclass 10, count 0 2006.259.08:16:55.19#ibcon#read 5, iclass 10, count 0 2006.259.08:16:55.19#ibcon#about to read 6, iclass 10, count 0 2006.259.08:16:55.19#ibcon#read 6, iclass 10, count 0 2006.259.08:16:55.19#ibcon#end of sib2, iclass 10, count 0 2006.259.08:16:55.19#ibcon#*after write, iclass 10, count 0 2006.259.08:16:55.19#ibcon#*before return 0, iclass 10, count 0 2006.259.08:16:55.19#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.259.08:16:55.19#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.259.08:16:55.19#ibcon#about to clear, iclass 10 cls_cnt 0 2006.259.08:16:55.19#ibcon#cleared, iclass 10 cls_cnt 0 2006.259.08:16:55.19$vc4f8/va=5,7 2006.259.08:16:55.19#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.259.08:16:55.19#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.259.08:16:55.19#ibcon#ireg 11 cls_cnt 2 2006.259.08:16:55.19#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.259.08:16:55.25#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.259.08:16:55.25#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.259.08:16:55.25#ibcon#enter wrdev, iclass 12, count 2 2006.259.08:16:55.25#ibcon#first serial, iclass 12, count 2 2006.259.08:16:55.25#ibcon#enter sib2, iclass 12, count 2 2006.259.08:16:55.25#ibcon#flushed, iclass 12, count 2 2006.259.08:16:55.25#ibcon#about to write, iclass 12, count 2 2006.259.08:16:55.25#ibcon#wrote, iclass 12, count 2 2006.259.08:16:55.25#ibcon#about to read 3, iclass 12, count 2 2006.259.08:16:55.27#ibcon#read 3, iclass 12, count 2 2006.259.08:16:55.27#ibcon#about to read 4, iclass 12, count 2 2006.259.08:16:55.27#ibcon#read 4, iclass 12, count 2 2006.259.08:16:55.27#ibcon#about to read 5, iclass 12, count 2 2006.259.08:16:55.27#ibcon#read 5, iclass 12, count 2 2006.259.08:16:55.27#ibcon#about to read 6, iclass 12, count 2 2006.259.08:16:55.27#ibcon#read 6, iclass 12, count 2 2006.259.08:16:55.27#ibcon#end of sib2, iclass 12, count 2 2006.259.08:16:55.27#ibcon#*mode == 0, iclass 12, count 2 2006.259.08:16:55.27#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.259.08:16:55.27#ibcon#[25=AT05-07\r\n] 2006.259.08:16:55.27#ibcon#*before write, iclass 12, count 2 2006.259.08:16:55.27#ibcon#enter sib2, iclass 12, count 2 2006.259.08:16:55.27#ibcon#flushed, iclass 12, count 2 2006.259.08:16:55.27#ibcon#about to write, iclass 12, count 2 2006.259.08:16:55.27#ibcon#wrote, iclass 12, count 2 2006.259.08:16:55.27#ibcon#about to read 3, iclass 12, count 2 2006.259.08:16:55.30#ibcon#read 3, iclass 12, count 2 2006.259.08:16:55.30#ibcon#about to read 4, iclass 12, count 2 2006.259.08:16:55.30#ibcon#read 4, iclass 12, count 2 2006.259.08:16:55.30#ibcon#about to read 5, iclass 12, count 2 2006.259.08:16:55.30#ibcon#read 5, iclass 12, count 2 2006.259.08:16:55.30#ibcon#about to read 6, iclass 12, count 2 2006.259.08:16:55.30#ibcon#read 6, iclass 12, count 2 2006.259.08:16:55.30#ibcon#end of sib2, iclass 12, count 2 2006.259.08:16:55.30#ibcon#*after write, iclass 12, count 2 2006.259.08:16:55.30#ibcon#*before return 0, iclass 12, count 2 2006.259.08:16:55.30#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.259.08:16:55.30#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.259.08:16:55.30#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.259.08:16:55.30#ibcon#ireg 7 cls_cnt 0 2006.259.08:16:55.30#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.259.08:16:55.43#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.259.08:16:55.43#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.259.08:16:55.43#ibcon#enter wrdev, iclass 12, count 0 2006.259.08:16:55.43#ibcon#first serial, iclass 12, count 0 2006.259.08:16:55.43#ibcon#enter sib2, iclass 12, count 0 2006.259.08:16:55.43#ibcon#flushed, iclass 12, count 0 2006.259.08:16:55.43#ibcon#about to write, iclass 12, count 0 2006.259.08:16:55.43#ibcon#wrote, iclass 12, count 0 2006.259.08:16:55.43#ibcon#about to read 3, iclass 12, count 0 2006.259.08:16:55.45#ibcon#read 3, iclass 12, count 0 2006.259.08:16:55.45#ibcon#about to read 4, iclass 12, count 0 2006.259.08:16:55.45#ibcon#read 4, iclass 12, count 0 2006.259.08:16:55.45#ibcon#about to read 5, iclass 12, count 0 2006.259.08:16:55.45#ibcon#read 5, iclass 12, count 0 2006.259.08:16:55.45#ibcon#about to read 6, iclass 12, count 0 2006.259.08:16:55.45#ibcon#read 6, iclass 12, count 0 2006.259.08:16:55.45#ibcon#end of sib2, iclass 12, count 0 2006.259.08:16:55.45#ibcon#*mode == 0, iclass 12, count 0 2006.259.08:16:55.45#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.259.08:16:55.45#ibcon#[25=USB\r\n] 2006.259.08:16:55.45#ibcon#*before write, iclass 12, count 0 2006.259.08:16:55.45#ibcon#enter sib2, iclass 12, count 0 2006.259.08:16:55.45#ibcon#flushed, iclass 12, count 0 2006.259.08:16:55.45#ibcon#about to write, iclass 12, count 0 2006.259.08:16:55.45#ibcon#wrote, iclass 12, count 0 2006.259.08:16:55.45#ibcon#about to read 3, iclass 12, count 0 2006.259.08:16:55.48#ibcon#read 3, iclass 12, count 0 2006.259.08:16:55.48#ibcon#about to read 4, iclass 12, count 0 2006.259.08:16:55.48#ibcon#read 4, iclass 12, count 0 2006.259.08:16:55.48#ibcon#about to read 5, iclass 12, count 0 2006.259.08:16:55.48#ibcon#read 5, iclass 12, count 0 2006.259.08:16:55.48#ibcon#about to read 6, iclass 12, count 0 2006.259.08:16:55.48#ibcon#read 6, iclass 12, count 0 2006.259.08:16:55.48#ibcon#end of sib2, iclass 12, count 0 2006.259.08:16:55.48#ibcon#*after write, iclass 12, count 0 2006.259.08:16:55.48#ibcon#*before return 0, iclass 12, count 0 2006.259.08:16:55.48#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.259.08:16:55.48#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.259.08:16:55.48#ibcon#about to clear, iclass 12 cls_cnt 0 2006.259.08:16:55.48#ibcon#cleared, iclass 12 cls_cnt 0 2006.259.08:16:55.48$vc4f8/valo=6,772.99 2006.259.08:16:55.48#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.259.08:16:55.48#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.259.08:16:55.48#ibcon#ireg 17 cls_cnt 0 2006.259.08:16:55.48#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.259.08:16:55.48#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.259.08:16:55.48#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.259.08:16:55.48#ibcon#enter wrdev, iclass 15, count 0 2006.259.08:16:55.48#ibcon#first serial, iclass 15, count 0 2006.259.08:16:55.48#ibcon#enter sib2, iclass 15, count 0 2006.259.08:16:55.48#ibcon#flushed, iclass 15, count 0 2006.259.08:16:55.48#ibcon#about to write, iclass 15, count 0 2006.259.08:16:55.48#ibcon#wrote, iclass 15, count 0 2006.259.08:16:55.48#ibcon#about to read 3, iclass 15, count 0 2006.259.08:16:55.50#ibcon#read 3, iclass 15, count 0 2006.259.08:16:55.50#ibcon#about to read 4, iclass 15, count 0 2006.259.08:16:55.50#ibcon#read 4, iclass 15, count 0 2006.259.08:16:55.50#ibcon#about to read 5, iclass 15, count 0 2006.259.08:16:55.50#ibcon#read 5, iclass 15, count 0 2006.259.08:16:55.50#ibcon#about to read 6, iclass 15, count 0 2006.259.08:16:55.50#ibcon#read 6, iclass 15, count 0 2006.259.08:16:55.50#ibcon#end of sib2, iclass 15, count 0 2006.259.08:16:55.50#ibcon#*mode == 0, iclass 15, count 0 2006.259.08:16:55.50#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.259.08:16:55.50#ibcon#[26=FRQ=06,772.99\r\n] 2006.259.08:16:55.50#ibcon#*before write, iclass 15, count 0 2006.259.08:16:55.50#ibcon#enter sib2, iclass 15, count 0 2006.259.08:16:55.50#ibcon#flushed, iclass 15, count 0 2006.259.08:16:55.50#ibcon#about to write, iclass 15, count 0 2006.259.08:16:55.50#ibcon#wrote, iclass 15, count 0 2006.259.08:16:55.50#ibcon#about to read 3, iclass 15, count 0 2006.259.08:16:55.50#abcon#<5=/04 2.7 4.9 21.88 861013.1\r\n> 2006.259.08:16:55.52#abcon#{5=INTERFACE CLEAR} 2006.259.08:16:55.54#ibcon#read 3, iclass 15, count 0 2006.259.08:16:55.54#ibcon#about to read 4, iclass 15, count 0 2006.259.08:16:55.54#ibcon#read 4, iclass 15, count 0 2006.259.08:16:55.54#ibcon#about to read 5, iclass 15, count 0 2006.259.08:16:55.54#ibcon#read 5, iclass 15, count 0 2006.259.08:16:55.54#ibcon#about to read 6, iclass 15, count 0 2006.259.08:16:55.54#ibcon#read 6, iclass 15, count 0 2006.259.08:16:55.54#ibcon#end of sib2, iclass 15, count 0 2006.259.08:16:55.54#ibcon#*after write, iclass 15, count 0 2006.259.08:16:55.54#ibcon#*before return 0, iclass 15, count 0 2006.259.08:16:55.54#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.259.08:16:55.54#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.259.08:16:55.54#ibcon#about to clear, iclass 15 cls_cnt 0 2006.259.08:16:55.54#ibcon#cleared, iclass 15 cls_cnt 0 2006.259.08:16:55.54$vc4f8/va=6,6 2006.259.08:16:55.54#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.259.08:16:55.54#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.259.08:16:55.54#ibcon#ireg 11 cls_cnt 2 2006.259.08:16:55.54#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.259.08:16:55.58#abcon#[5=S1D000X0/0*\r\n] 2006.259.08:16:55.60#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.259.08:16:55.60#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.259.08:16:55.60#ibcon#enter wrdev, iclass 19, count 2 2006.259.08:16:55.60#ibcon#first serial, iclass 19, count 2 2006.259.08:16:55.60#ibcon#enter sib2, iclass 19, count 2 2006.259.08:16:55.60#ibcon#flushed, iclass 19, count 2 2006.259.08:16:55.60#ibcon#about to write, iclass 19, count 2 2006.259.08:16:55.60#ibcon#wrote, iclass 19, count 2 2006.259.08:16:55.60#ibcon#about to read 3, iclass 19, count 2 2006.259.08:16:55.62#ibcon#read 3, iclass 19, count 2 2006.259.08:16:55.62#ibcon#about to read 4, iclass 19, count 2 2006.259.08:16:55.62#ibcon#read 4, iclass 19, count 2 2006.259.08:16:55.62#ibcon#about to read 5, iclass 19, count 2 2006.259.08:16:55.62#ibcon#read 5, iclass 19, count 2 2006.259.08:16:55.62#ibcon#about to read 6, iclass 19, count 2 2006.259.08:16:55.62#ibcon#read 6, iclass 19, count 2 2006.259.08:16:55.62#ibcon#end of sib2, iclass 19, count 2 2006.259.08:16:55.62#ibcon#*mode == 0, iclass 19, count 2 2006.259.08:16:55.62#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.259.08:16:55.62#ibcon#[25=AT06-06\r\n] 2006.259.08:16:55.62#ibcon#*before write, iclass 19, count 2 2006.259.08:16:55.62#ibcon#enter sib2, iclass 19, count 2 2006.259.08:16:55.62#ibcon#flushed, iclass 19, count 2 2006.259.08:16:55.62#ibcon#about to write, iclass 19, count 2 2006.259.08:16:55.62#ibcon#wrote, iclass 19, count 2 2006.259.08:16:55.62#ibcon#about to read 3, iclass 19, count 2 2006.259.08:16:55.65#ibcon#read 3, iclass 19, count 2 2006.259.08:16:55.65#ibcon#about to read 4, iclass 19, count 2 2006.259.08:16:55.65#ibcon#read 4, iclass 19, count 2 2006.259.08:16:55.65#ibcon#about to read 5, iclass 19, count 2 2006.259.08:16:55.65#ibcon#read 5, iclass 19, count 2 2006.259.08:16:55.65#ibcon#about to read 6, iclass 19, count 2 2006.259.08:16:55.65#ibcon#read 6, iclass 19, count 2 2006.259.08:16:55.65#ibcon#end of sib2, iclass 19, count 2 2006.259.08:16:55.65#ibcon#*after write, iclass 19, count 2 2006.259.08:16:55.65#ibcon#*before return 0, iclass 19, count 2 2006.259.08:16:55.65#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.259.08:16:55.65#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.259.08:16:55.65#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.259.08:16:55.65#ibcon#ireg 7 cls_cnt 0 2006.259.08:16:55.65#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.259.08:16:55.77#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.259.08:16:55.77#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.259.08:16:55.77#ibcon#enter wrdev, iclass 19, count 0 2006.259.08:16:55.77#ibcon#first serial, iclass 19, count 0 2006.259.08:16:55.77#ibcon#enter sib2, iclass 19, count 0 2006.259.08:16:55.77#ibcon#flushed, iclass 19, count 0 2006.259.08:16:55.77#ibcon#about to write, iclass 19, count 0 2006.259.08:16:55.77#ibcon#wrote, iclass 19, count 0 2006.259.08:16:55.77#ibcon#about to read 3, iclass 19, count 0 2006.259.08:16:55.79#ibcon#read 3, iclass 19, count 0 2006.259.08:16:55.79#ibcon#about to read 4, iclass 19, count 0 2006.259.08:16:55.79#ibcon#read 4, iclass 19, count 0 2006.259.08:16:55.79#ibcon#about to read 5, iclass 19, count 0 2006.259.08:16:55.79#ibcon#read 5, iclass 19, count 0 2006.259.08:16:55.79#ibcon#about to read 6, iclass 19, count 0 2006.259.08:16:55.79#ibcon#read 6, iclass 19, count 0 2006.259.08:16:55.79#ibcon#end of sib2, iclass 19, count 0 2006.259.08:16:55.79#ibcon#*mode == 0, iclass 19, count 0 2006.259.08:16:55.79#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.259.08:16:55.79#ibcon#[25=USB\r\n] 2006.259.08:16:55.79#ibcon#*before write, iclass 19, count 0 2006.259.08:16:55.79#ibcon#enter sib2, iclass 19, count 0 2006.259.08:16:55.79#ibcon#flushed, iclass 19, count 0 2006.259.08:16:55.79#ibcon#about to write, iclass 19, count 0 2006.259.08:16:55.79#ibcon#wrote, iclass 19, count 0 2006.259.08:16:55.79#ibcon#about to read 3, iclass 19, count 0 2006.259.08:16:55.82#ibcon#read 3, iclass 19, count 0 2006.259.08:16:55.82#ibcon#about to read 4, iclass 19, count 0 2006.259.08:16:55.82#ibcon#read 4, iclass 19, count 0 2006.259.08:16:55.82#ibcon#about to read 5, iclass 19, count 0 2006.259.08:16:55.82#ibcon#read 5, iclass 19, count 0 2006.259.08:16:55.82#ibcon#about to read 6, iclass 19, count 0 2006.259.08:16:55.82#ibcon#read 6, iclass 19, count 0 2006.259.08:16:55.82#ibcon#end of sib2, iclass 19, count 0 2006.259.08:16:55.82#ibcon#*after write, iclass 19, count 0 2006.259.08:16:55.82#ibcon#*before return 0, iclass 19, count 0 2006.259.08:16:55.82#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.259.08:16:55.82#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.259.08:16:55.82#ibcon#about to clear, iclass 19 cls_cnt 0 2006.259.08:16:55.82#ibcon#cleared, iclass 19 cls_cnt 0 2006.259.08:16:55.82$vc4f8/valo=7,832.99 2006.259.08:16:55.82#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.259.08:16:55.82#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.259.08:16:55.82#ibcon#ireg 17 cls_cnt 0 2006.259.08:16:55.82#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.259.08:16:55.82#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.259.08:16:55.82#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.259.08:16:55.82#ibcon#enter wrdev, iclass 22, count 0 2006.259.08:16:55.82#ibcon#first serial, iclass 22, count 0 2006.259.08:16:55.82#ibcon#enter sib2, iclass 22, count 0 2006.259.08:16:55.82#ibcon#flushed, iclass 22, count 0 2006.259.08:16:55.82#ibcon#about to write, iclass 22, count 0 2006.259.08:16:55.82#ibcon#wrote, iclass 22, count 0 2006.259.08:16:55.82#ibcon#about to read 3, iclass 22, count 0 2006.259.08:16:55.84#ibcon#read 3, iclass 22, count 0 2006.259.08:16:55.84#ibcon#about to read 4, iclass 22, count 0 2006.259.08:16:55.84#ibcon#read 4, iclass 22, count 0 2006.259.08:16:55.84#ibcon#about to read 5, iclass 22, count 0 2006.259.08:16:55.84#ibcon#read 5, iclass 22, count 0 2006.259.08:16:55.84#ibcon#about to read 6, iclass 22, count 0 2006.259.08:16:55.84#ibcon#read 6, iclass 22, count 0 2006.259.08:16:55.84#ibcon#end of sib2, iclass 22, count 0 2006.259.08:16:55.84#ibcon#*mode == 0, iclass 22, count 0 2006.259.08:16:55.84#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.259.08:16:55.84#ibcon#[26=FRQ=07,832.99\r\n] 2006.259.08:16:55.84#ibcon#*before write, iclass 22, count 0 2006.259.08:16:55.84#ibcon#enter sib2, iclass 22, count 0 2006.259.08:16:55.84#ibcon#flushed, iclass 22, count 0 2006.259.08:16:55.84#ibcon#about to write, iclass 22, count 0 2006.259.08:16:55.84#ibcon#wrote, iclass 22, count 0 2006.259.08:16:55.84#ibcon#about to read 3, iclass 22, count 0 2006.259.08:16:55.88#ibcon#read 3, iclass 22, count 0 2006.259.08:16:55.88#ibcon#about to read 4, iclass 22, count 0 2006.259.08:16:55.88#ibcon#read 4, iclass 22, count 0 2006.259.08:16:55.88#ibcon#about to read 5, iclass 22, count 0 2006.259.08:16:55.88#ibcon#read 5, iclass 22, count 0 2006.259.08:16:55.88#ibcon#about to read 6, iclass 22, count 0 2006.259.08:16:55.88#ibcon#read 6, iclass 22, count 0 2006.259.08:16:55.88#ibcon#end of sib2, iclass 22, count 0 2006.259.08:16:55.88#ibcon#*after write, iclass 22, count 0 2006.259.08:16:55.88#ibcon#*before return 0, iclass 22, count 0 2006.259.08:16:55.88#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.259.08:16:55.88#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.259.08:16:55.88#ibcon#about to clear, iclass 22 cls_cnt 0 2006.259.08:16:55.88#ibcon#cleared, iclass 22 cls_cnt 0 2006.259.08:16:55.88$vc4f8/va=7,6 2006.259.08:16:55.88#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.259.08:16:55.88#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.259.08:16:55.88#ibcon#ireg 11 cls_cnt 2 2006.259.08:16:55.88#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.259.08:16:55.94#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.259.08:16:55.94#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.259.08:16:55.94#ibcon#enter wrdev, iclass 24, count 2 2006.259.08:16:55.94#ibcon#first serial, iclass 24, count 2 2006.259.08:16:55.94#ibcon#enter sib2, iclass 24, count 2 2006.259.08:16:55.94#ibcon#flushed, iclass 24, count 2 2006.259.08:16:55.94#ibcon#about to write, iclass 24, count 2 2006.259.08:16:55.94#ibcon#wrote, iclass 24, count 2 2006.259.08:16:55.94#ibcon#about to read 3, iclass 24, count 2 2006.259.08:16:55.96#ibcon#read 3, iclass 24, count 2 2006.259.08:16:55.96#ibcon#about to read 4, iclass 24, count 2 2006.259.08:16:55.96#ibcon#read 4, iclass 24, count 2 2006.259.08:16:55.96#ibcon#about to read 5, iclass 24, count 2 2006.259.08:16:55.96#ibcon#read 5, iclass 24, count 2 2006.259.08:16:55.96#ibcon#about to read 6, iclass 24, count 2 2006.259.08:16:55.96#ibcon#read 6, iclass 24, count 2 2006.259.08:16:55.96#ibcon#end of sib2, iclass 24, count 2 2006.259.08:16:55.96#ibcon#*mode == 0, iclass 24, count 2 2006.259.08:16:55.96#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.259.08:16:55.96#ibcon#[25=AT07-06\r\n] 2006.259.08:16:55.96#ibcon#*before write, iclass 24, count 2 2006.259.08:16:55.96#ibcon#enter sib2, iclass 24, count 2 2006.259.08:16:55.96#ibcon#flushed, iclass 24, count 2 2006.259.08:16:55.96#ibcon#about to write, iclass 24, count 2 2006.259.08:16:55.96#ibcon#wrote, iclass 24, count 2 2006.259.08:16:55.96#ibcon#about to read 3, iclass 24, count 2 2006.259.08:16:55.99#ibcon#read 3, iclass 24, count 2 2006.259.08:16:55.99#ibcon#about to read 4, iclass 24, count 2 2006.259.08:16:55.99#ibcon#read 4, iclass 24, count 2 2006.259.08:16:55.99#ibcon#about to read 5, iclass 24, count 2 2006.259.08:16:55.99#ibcon#read 5, iclass 24, count 2 2006.259.08:16:55.99#ibcon#about to read 6, iclass 24, count 2 2006.259.08:16:55.99#ibcon#read 6, iclass 24, count 2 2006.259.08:16:55.99#ibcon#end of sib2, iclass 24, count 2 2006.259.08:16:55.99#ibcon#*after write, iclass 24, count 2 2006.259.08:16:55.99#ibcon#*before return 0, iclass 24, count 2 2006.259.08:16:55.99#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.259.08:16:55.99#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.259.08:16:55.99#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.259.08:16:55.99#ibcon#ireg 7 cls_cnt 0 2006.259.08:16:55.99#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.259.08:16:56.11#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.259.08:16:56.11#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.259.08:16:56.11#ibcon#enter wrdev, iclass 24, count 0 2006.259.08:16:56.11#ibcon#first serial, iclass 24, count 0 2006.259.08:16:56.11#ibcon#enter sib2, iclass 24, count 0 2006.259.08:16:56.11#ibcon#flushed, iclass 24, count 0 2006.259.08:16:56.11#ibcon#about to write, iclass 24, count 0 2006.259.08:16:56.11#ibcon#wrote, iclass 24, count 0 2006.259.08:16:56.11#ibcon#about to read 3, iclass 24, count 0 2006.259.08:16:56.13#ibcon#read 3, iclass 24, count 0 2006.259.08:16:56.13#ibcon#about to read 4, iclass 24, count 0 2006.259.08:16:56.13#ibcon#read 4, iclass 24, count 0 2006.259.08:16:56.13#ibcon#about to read 5, iclass 24, count 0 2006.259.08:16:56.13#ibcon#read 5, iclass 24, count 0 2006.259.08:16:56.13#ibcon#about to read 6, iclass 24, count 0 2006.259.08:16:56.13#ibcon#read 6, iclass 24, count 0 2006.259.08:16:56.13#ibcon#end of sib2, iclass 24, count 0 2006.259.08:16:56.13#ibcon#*mode == 0, iclass 24, count 0 2006.259.08:16:56.13#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.259.08:16:56.13#ibcon#[25=USB\r\n] 2006.259.08:16:56.13#ibcon#*before write, iclass 24, count 0 2006.259.08:16:56.13#ibcon#enter sib2, iclass 24, count 0 2006.259.08:16:56.13#ibcon#flushed, iclass 24, count 0 2006.259.08:16:56.13#ibcon#about to write, iclass 24, count 0 2006.259.08:16:56.13#ibcon#wrote, iclass 24, count 0 2006.259.08:16:56.13#ibcon#about to read 3, iclass 24, count 0 2006.259.08:16:56.16#ibcon#read 3, iclass 24, count 0 2006.259.08:16:56.16#ibcon#about to read 4, iclass 24, count 0 2006.259.08:16:56.16#ibcon#read 4, iclass 24, count 0 2006.259.08:16:56.16#ibcon#about to read 5, iclass 24, count 0 2006.259.08:16:56.16#ibcon#read 5, iclass 24, count 0 2006.259.08:16:56.16#ibcon#about to read 6, iclass 24, count 0 2006.259.08:16:56.16#ibcon#read 6, iclass 24, count 0 2006.259.08:16:56.16#ibcon#end of sib2, iclass 24, count 0 2006.259.08:16:56.16#ibcon#*after write, iclass 24, count 0 2006.259.08:16:56.16#ibcon#*before return 0, iclass 24, count 0 2006.259.08:16:56.16#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.259.08:16:56.16#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.259.08:16:56.16#ibcon#about to clear, iclass 24 cls_cnt 0 2006.259.08:16:56.16#ibcon#cleared, iclass 24 cls_cnt 0 2006.259.08:16:56.16$vc4f8/valo=8,852.99 2006.259.08:16:56.16#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.259.08:16:56.16#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.259.08:16:56.16#ibcon#ireg 17 cls_cnt 0 2006.259.08:16:56.16#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.259.08:16:56.16#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.259.08:16:56.16#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.259.08:16:56.16#ibcon#enter wrdev, iclass 26, count 0 2006.259.08:16:56.16#ibcon#first serial, iclass 26, count 0 2006.259.08:16:56.16#ibcon#enter sib2, iclass 26, count 0 2006.259.08:16:56.16#ibcon#flushed, iclass 26, count 0 2006.259.08:16:56.16#ibcon#about to write, iclass 26, count 0 2006.259.08:16:56.16#ibcon#wrote, iclass 26, count 0 2006.259.08:16:56.16#ibcon#about to read 3, iclass 26, count 0 2006.259.08:16:56.18#ibcon#read 3, iclass 26, count 0 2006.259.08:16:56.18#ibcon#about to read 4, iclass 26, count 0 2006.259.08:16:56.18#ibcon#read 4, iclass 26, count 0 2006.259.08:16:56.18#ibcon#about to read 5, iclass 26, count 0 2006.259.08:16:56.18#ibcon#read 5, iclass 26, count 0 2006.259.08:16:56.18#ibcon#about to read 6, iclass 26, count 0 2006.259.08:16:56.18#ibcon#read 6, iclass 26, count 0 2006.259.08:16:56.18#ibcon#end of sib2, iclass 26, count 0 2006.259.08:16:56.18#ibcon#*mode == 0, iclass 26, count 0 2006.259.08:16:56.18#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.259.08:16:56.18#ibcon#[26=FRQ=08,852.99\r\n] 2006.259.08:16:56.18#ibcon#*before write, iclass 26, count 0 2006.259.08:16:56.18#ibcon#enter sib2, iclass 26, count 0 2006.259.08:16:56.18#ibcon#flushed, iclass 26, count 0 2006.259.08:16:56.18#ibcon#about to write, iclass 26, count 0 2006.259.08:16:56.18#ibcon#wrote, iclass 26, count 0 2006.259.08:16:56.18#ibcon#about to read 3, iclass 26, count 0 2006.259.08:16:56.22#ibcon#read 3, iclass 26, count 0 2006.259.08:16:56.22#ibcon#about to read 4, iclass 26, count 0 2006.259.08:16:56.22#ibcon#read 4, iclass 26, count 0 2006.259.08:16:56.22#ibcon#about to read 5, iclass 26, count 0 2006.259.08:16:56.22#ibcon#read 5, iclass 26, count 0 2006.259.08:16:56.22#ibcon#about to read 6, iclass 26, count 0 2006.259.08:16:56.22#ibcon#read 6, iclass 26, count 0 2006.259.08:16:56.22#ibcon#end of sib2, iclass 26, count 0 2006.259.08:16:56.22#ibcon#*after write, iclass 26, count 0 2006.259.08:16:56.22#ibcon#*before return 0, iclass 26, count 0 2006.259.08:16:56.22#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.259.08:16:56.22#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.259.08:16:56.22#ibcon#about to clear, iclass 26 cls_cnt 0 2006.259.08:16:56.22#ibcon#cleared, iclass 26 cls_cnt 0 2006.259.08:16:56.22$vc4f8/va=8,6 2006.259.08:16:56.22#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.259.08:16:56.22#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.259.08:16:56.22#ibcon#ireg 11 cls_cnt 2 2006.259.08:16:56.22#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.259.08:16:56.28#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.259.08:16:56.28#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.259.08:16:56.28#ibcon#enter wrdev, iclass 28, count 2 2006.259.08:16:56.28#ibcon#first serial, iclass 28, count 2 2006.259.08:16:56.28#ibcon#enter sib2, iclass 28, count 2 2006.259.08:16:56.28#ibcon#flushed, iclass 28, count 2 2006.259.08:16:56.28#ibcon#about to write, iclass 28, count 2 2006.259.08:16:56.28#ibcon#wrote, iclass 28, count 2 2006.259.08:16:56.28#ibcon#about to read 3, iclass 28, count 2 2006.259.08:16:56.30#ibcon#read 3, iclass 28, count 2 2006.259.08:16:56.30#ibcon#about to read 4, iclass 28, count 2 2006.259.08:16:56.30#ibcon#read 4, iclass 28, count 2 2006.259.08:16:56.30#ibcon#about to read 5, iclass 28, count 2 2006.259.08:16:56.30#ibcon#read 5, iclass 28, count 2 2006.259.08:16:56.30#ibcon#about to read 6, iclass 28, count 2 2006.259.08:16:56.30#ibcon#read 6, iclass 28, count 2 2006.259.08:16:56.30#ibcon#end of sib2, iclass 28, count 2 2006.259.08:16:56.30#ibcon#*mode == 0, iclass 28, count 2 2006.259.08:16:56.30#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.259.08:16:56.30#ibcon#[25=AT08-06\r\n] 2006.259.08:16:56.30#ibcon#*before write, iclass 28, count 2 2006.259.08:16:56.30#ibcon#enter sib2, iclass 28, count 2 2006.259.08:16:56.30#ibcon#flushed, iclass 28, count 2 2006.259.08:16:56.30#ibcon#about to write, iclass 28, count 2 2006.259.08:16:56.30#ibcon#wrote, iclass 28, count 2 2006.259.08:16:56.30#ibcon#about to read 3, iclass 28, count 2 2006.259.08:16:56.33#ibcon#read 3, iclass 28, count 2 2006.259.08:16:56.33#ibcon#about to read 4, iclass 28, count 2 2006.259.08:16:56.33#ibcon#read 4, iclass 28, count 2 2006.259.08:16:56.33#ibcon#about to read 5, iclass 28, count 2 2006.259.08:16:56.33#ibcon#read 5, iclass 28, count 2 2006.259.08:16:56.33#ibcon#about to read 6, iclass 28, count 2 2006.259.08:16:56.33#ibcon#read 6, iclass 28, count 2 2006.259.08:16:56.33#ibcon#end of sib2, iclass 28, count 2 2006.259.08:16:56.33#ibcon#*after write, iclass 28, count 2 2006.259.08:16:56.33#ibcon#*before return 0, iclass 28, count 2 2006.259.08:16:56.33#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.259.08:16:56.33#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.259.08:16:56.33#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.259.08:16:56.33#ibcon#ireg 7 cls_cnt 0 2006.259.08:16:56.33#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.259.08:16:56.45#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.259.08:16:56.45#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.259.08:16:56.45#ibcon#enter wrdev, iclass 28, count 0 2006.259.08:16:56.45#ibcon#first serial, iclass 28, count 0 2006.259.08:16:56.45#ibcon#enter sib2, iclass 28, count 0 2006.259.08:16:56.45#ibcon#flushed, iclass 28, count 0 2006.259.08:16:56.45#ibcon#about to write, iclass 28, count 0 2006.259.08:16:56.45#ibcon#wrote, iclass 28, count 0 2006.259.08:16:56.45#ibcon#about to read 3, iclass 28, count 0 2006.259.08:16:56.47#ibcon#read 3, iclass 28, count 0 2006.259.08:16:56.47#ibcon#about to read 4, iclass 28, count 0 2006.259.08:16:56.47#ibcon#read 4, iclass 28, count 0 2006.259.08:16:56.47#ibcon#about to read 5, iclass 28, count 0 2006.259.08:16:56.47#ibcon#read 5, iclass 28, count 0 2006.259.08:16:56.47#ibcon#about to read 6, iclass 28, count 0 2006.259.08:16:56.47#ibcon#read 6, iclass 28, count 0 2006.259.08:16:56.47#ibcon#end of sib2, iclass 28, count 0 2006.259.08:16:56.47#ibcon#*mode == 0, iclass 28, count 0 2006.259.08:16:56.47#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.259.08:16:56.47#ibcon#[25=USB\r\n] 2006.259.08:16:56.47#ibcon#*before write, iclass 28, count 0 2006.259.08:16:56.47#ibcon#enter sib2, iclass 28, count 0 2006.259.08:16:56.47#ibcon#flushed, iclass 28, count 0 2006.259.08:16:56.47#ibcon#about to write, iclass 28, count 0 2006.259.08:16:56.47#ibcon#wrote, iclass 28, count 0 2006.259.08:16:56.47#ibcon#about to read 3, iclass 28, count 0 2006.259.08:16:56.50#ibcon#read 3, iclass 28, count 0 2006.259.08:16:56.50#ibcon#about to read 4, iclass 28, count 0 2006.259.08:16:56.50#ibcon#read 4, iclass 28, count 0 2006.259.08:16:56.50#ibcon#about to read 5, iclass 28, count 0 2006.259.08:16:56.50#ibcon#read 5, iclass 28, count 0 2006.259.08:16:56.50#ibcon#about to read 6, iclass 28, count 0 2006.259.08:16:56.50#ibcon#read 6, iclass 28, count 0 2006.259.08:16:56.50#ibcon#end of sib2, iclass 28, count 0 2006.259.08:16:56.50#ibcon#*after write, iclass 28, count 0 2006.259.08:16:56.50#ibcon#*before return 0, iclass 28, count 0 2006.259.08:16:56.50#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.259.08:16:56.50#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.259.08:16:56.50#ibcon#about to clear, iclass 28 cls_cnt 0 2006.259.08:16:56.50#ibcon#cleared, iclass 28 cls_cnt 0 2006.259.08:16:56.50$vc4f8/vblo=1,632.99 2006.259.08:16:56.50#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.259.08:16:56.50#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.259.08:16:56.50#ibcon#ireg 17 cls_cnt 0 2006.259.08:16:56.50#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.259.08:16:56.50#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.259.08:16:56.50#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.259.08:16:56.50#ibcon#enter wrdev, iclass 30, count 0 2006.259.08:16:56.50#ibcon#first serial, iclass 30, count 0 2006.259.08:16:56.50#ibcon#enter sib2, iclass 30, count 0 2006.259.08:16:56.50#ibcon#flushed, iclass 30, count 0 2006.259.08:16:56.50#ibcon#about to write, iclass 30, count 0 2006.259.08:16:56.50#ibcon#wrote, iclass 30, count 0 2006.259.08:16:56.50#ibcon#about to read 3, iclass 30, count 0 2006.259.08:16:56.52#ibcon#read 3, iclass 30, count 0 2006.259.08:16:56.52#ibcon#about to read 4, iclass 30, count 0 2006.259.08:16:56.52#ibcon#read 4, iclass 30, count 0 2006.259.08:16:56.52#ibcon#about to read 5, iclass 30, count 0 2006.259.08:16:56.52#ibcon#read 5, iclass 30, count 0 2006.259.08:16:56.52#ibcon#about to read 6, iclass 30, count 0 2006.259.08:16:56.52#ibcon#read 6, iclass 30, count 0 2006.259.08:16:56.52#ibcon#end of sib2, iclass 30, count 0 2006.259.08:16:56.52#ibcon#*mode == 0, iclass 30, count 0 2006.259.08:16:56.52#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.259.08:16:56.52#ibcon#[28=FRQ=01,632.99\r\n] 2006.259.08:16:56.52#ibcon#*before write, iclass 30, count 0 2006.259.08:16:56.52#ibcon#enter sib2, iclass 30, count 0 2006.259.08:16:56.52#ibcon#flushed, iclass 30, count 0 2006.259.08:16:56.52#ibcon#about to write, iclass 30, count 0 2006.259.08:16:56.52#ibcon#wrote, iclass 30, count 0 2006.259.08:16:56.52#ibcon#about to read 3, iclass 30, count 0 2006.259.08:16:56.56#ibcon#read 3, iclass 30, count 0 2006.259.08:16:56.56#ibcon#about to read 4, iclass 30, count 0 2006.259.08:16:56.56#ibcon#read 4, iclass 30, count 0 2006.259.08:16:56.56#ibcon#about to read 5, iclass 30, count 0 2006.259.08:16:56.56#ibcon#read 5, iclass 30, count 0 2006.259.08:16:56.56#ibcon#about to read 6, iclass 30, count 0 2006.259.08:16:56.56#ibcon#read 6, iclass 30, count 0 2006.259.08:16:56.56#ibcon#end of sib2, iclass 30, count 0 2006.259.08:16:56.56#ibcon#*after write, iclass 30, count 0 2006.259.08:16:56.56#ibcon#*before return 0, iclass 30, count 0 2006.259.08:16:56.56#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.259.08:16:56.56#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.259.08:16:56.56#ibcon#about to clear, iclass 30 cls_cnt 0 2006.259.08:16:56.56#ibcon#cleared, iclass 30 cls_cnt 0 2006.259.08:16:56.56$vc4f8/vb=1,4 2006.259.08:16:56.56#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.259.08:16:56.56#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.259.08:16:56.56#ibcon#ireg 11 cls_cnt 2 2006.259.08:16:56.56#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.259.08:16:56.56#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.259.08:16:56.56#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.259.08:16:56.56#ibcon#enter wrdev, iclass 32, count 2 2006.259.08:16:56.56#ibcon#first serial, iclass 32, count 2 2006.259.08:16:56.56#ibcon#enter sib2, iclass 32, count 2 2006.259.08:16:56.56#ibcon#flushed, iclass 32, count 2 2006.259.08:16:56.56#ibcon#about to write, iclass 32, count 2 2006.259.08:16:56.56#ibcon#wrote, iclass 32, count 2 2006.259.08:16:56.56#ibcon#about to read 3, iclass 32, count 2 2006.259.08:16:56.58#ibcon#read 3, iclass 32, count 2 2006.259.08:16:56.58#ibcon#about to read 4, iclass 32, count 2 2006.259.08:16:56.58#ibcon#read 4, iclass 32, count 2 2006.259.08:16:56.58#ibcon#about to read 5, iclass 32, count 2 2006.259.08:16:56.58#ibcon#read 5, iclass 32, count 2 2006.259.08:16:56.58#ibcon#about to read 6, iclass 32, count 2 2006.259.08:16:56.58#ibcon#read 6, iclass 32, count 2 2006.259.08:16:56.58#ibcon#end of sib2, iclass 32, count 2 2006.259.08:16:56.58#ibcon#*mode == 0, iclass 32, count 2 2006.259.08:16:56.58#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.259.08:16:56.58#ibcon#[27=AT01-04\r\n] 2006.259.08:16:56.58#ibcon#*before write, iclass 32, count 2 2006.259.08:16:56.58#ibcon#enter sib2, iclass 32, count 2 2006.259.08:16:56.58#ibcon#flushed, iclass 32, count 2 2006.259.08:16:56.58#ibcon#about to write, iclass 32, count 2 2006.259.08:16:56.58#ibcon#wrote, iclass 32, count 2 2006.259.08:16:56.58#ibcon#about to read 3, iclass 32, count 2 2006.259.08:16:56.61#ibcon#read 3, iclass 32, count 2 2006.259.08:16:56.61#ibcon#about to read 4, iclass 32, count 2 2006.259.08:16:56.61#ibcon#read 4, iclass 32, count 2 2006.259.08:16:56.61#ibcon#about to read 5, iclass 32, count 2 2006.259.08:16:56.61#ibcon#read 5, iclass 32, count 2 2006.259.08:16:56.61#ibcon#about to read 6, iclass 32, count 2 2006.259.08:16:56.61#ibcon#read 6, iclass 32, count 2 2006.259.08:16:56.61#ibcon#end of sib2, iclass 32, count 2 2006.259.08:16:56.61#ibcon#*after write, iclass 32, count 2 2006.259.08:16:56.61#ibcon#*before return 0, iclass 32, count 2 2006.259.08:16:56.61#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.259.08:16:56.61#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.259.08:16:56.61#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.259.08:16:56.61#ibcon#ireg 7 cls_cnt 0 2006.259.08:16:56.61#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.259.08:16:56.73#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.259.08:16:56.73#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.259.08:16:56.73#ibcon#enter wrdev, iclass 32, count 0 2006.259.08:16:56.73#ibcon#first serial, iclass 32, count 0 2006.259.08:16:56.73#ibcon#enter sib2, iclass 32, count 0 2006.259.08:16:56.73#ibcon#flushed, iclass 32, count 0 2006.259.08:16:56.73#ibcon#about to write, iclass 32, count 0 2006.259.08:16:56.73#ibcon#wrote, iclass 32, count 0 2006.259.08:16:56.73#ibcon#about to read 3, iclass 32, count 0 2006.259.08:16:56.75#ibcon#read 3, iclass 32, count 0 2006.259.08:16:56.75#ibcon#about to read 4, iclass 32, count 0 2006.259.08:16:56.75#ibcon#read 4, iclass 32, count 0 2006.259.08:16:56.75#ibcon#about to read 5, iclass 32, count 0 2006.259.08:16:56.75#ibcon#read 5, iclass 32, count 0 2006.259.08:16:56.75#ibcon#about to read 6, iclass 32, count 0 2006.259.08:16:56.75#ibcon#read 6, iclass 32, count 0 2006.259.08:16:56.75#ibcon#end of sib2, iclass 32, count 0 2006.259.08:16:56.75#ibcon#*mode == 0, iclass 32, count 0 2006.259.08:16:56.75#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.259.08:16:56.75#ibcon#[27=USB\r\n] 2006.259.08:16:56.75#ibcon#*before write, iclass 32, count 0 2006.259.08:16:56.75#ibcon#enter sib2, iclass 32, count 0 2006.259.08:16:56.75#ibcon#flushed, iclass 32, count 0 2006.259.08:16:56.75#ibcon#about to write, iclass 32, count 0 2006.259.08:16:56.75#ibcon#wrote, iclass 32, count 0 2006.259.08:16:56.75#ibcon#about to read 3, iclass 32, count 0 2006.259.08:16:56.78#ibcon#read 3, iclass 32, count 0 2006.259.08:16:56.78#ibcon#about to read 4, iclass 32, count 0 2006.259.08:16:56.78#ibcon#read 4, iclass 32, count 0 2006.259.08:16:56.78#ibcon#about to read 5, iclass 32, count 0 2006.259.08:16:56.78#ibcon#read 5, iclass 32, count 0 2006.259.08:16:56.78#ibcon#about to read 6, iclass 32, count 0 2006.259.08:16:56.78#ibcon#read 6, iclass 32, count 0 2006.259.08:16:56.78#ibcon#end of sib2, iclass 32, count 0 2006.259.08:16:56.78#ibcon#*after write, iclass 32, count 0 2006.259.08:16:56.78#ibcon#*before return 0, iclass 32, count 0 2006.259.08:16:56.78#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.259.08:16:56.78#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.259.08:16:56.78#ibcon#about to clear, iclass 32 cls_cnt 0 2006.259.08:16:56.78#ibcon#cleared, iclass 32 cls_cnt 0 2006.259.08:16:56.78$vc4f8/vblo=2,640.99 2006.259.08:16:56.78#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.259.08:16:56.78#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.259.08:16:56.78#ibcon#ireg 17 cls_cnt 0 2006.259.08:16:56.78#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.259.08:16:56.78#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.259.08:16:56.78#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.259.08:16:56.78#ibcon#enter wrdev, iclass 34, count 0 2006.259.08:16:56.78#ibcon#first serial, iclass 34, count 0 2006.259.08:16:56.78#ibcon#enter sib2, iclass 34, count 0 2006.259.08:16:56.78#ibcon#flushed, iclass 34, count 0 2006.259.08:16:56.78#ibcon#about to write, iclass 34, count 0 2006.259.08:16:56.78#ibcon#wrote, iclass 34, count 0 2006.259.08:16:56.78#ibcon#about to read 3, iclass 34, count 0 2006.259.08:16:56.80#ibcon#read 3, iclass 34, count 0 2006.259.08:16:56.80#ibcon#about to read 4, iclass 34, count 0 2006.259.08:16:56.80#ibcon#read 4, iclass 34, count 0 2006.259.08:16:56.80#ibcon#about to read 5, iclass 34, count 0 2006.259.08:16:56.80#ibcon#read 5, iclass 34, count 0 2006.259.08:16:56.80#ibcon#about to read 6, iclass 34, count 0 2006.259.08:16:56.80#ibcon#read 6, iclass 34, count 0 2006.259.08:16:56.80#ibcon#end of sib2, iclass 34, count 0 2006.259.08:16:56.80#ibcon#*mode == 0, iclass 34, count 0 2006.259.08:16:56.80#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.259.08:16:56.80#ibcon#[28=FRQ=02,640.99\r\n] 2006.259.08:16:56.80#ibcon#*before write, iclass 34, count 0 2006.259.08:16:56.80#ibcon#enter sib2, iclass 34, count 0 2006.259.08:16:56.80#ibcon#flushed, iclass 34, count 0 2006.259.08:16:56.80#ibcon#about to write, iclass 34, count 0 2006.259.08:16:56.80#ibcon#wrote, iclass 34, count 0 2006.259.08:16:56.80#ibcon#about to read 3, iclass 34, count 0 2006.259.08:16:56.84#ibcon#read 3, iclass 34, count 0 2006.259.08:16:56.84#ibcon#about to read 4, iclass 34, count 0 2006.259.08:16:56.84#ibcon#read 4, iclass 34, count 0 2006.259.08:16:56.84#ibcon#about to read 5, iclass 34, count 0 2006.259.08:16:56.84#ibcon#read 5, iclass 34, count 0 2006.259.08:16:56.84#ibcon#about to read 6, iclass 34, count 0 2006.259.08:16:56.84#ibcon#read 6, iclass 34, count 0 2006.259.08:16:56.84#ibcon#end of sib2, iclass 34, count 0 2006.259.08:16:56.84#ibcon#*after write, iclass 34, count 0 2006.259.08:16:56.84#ibcon#*before return 0, iclass 34, count 0 2006.259.08:16:56.84#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.259.08:16:56.84#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.259.08:16:56.84#ibcon#about to clear, iclass 34 cls_cnt 0 2006.259.08:16:56.84#ibcon#cleared, iclass 34 cls_cnt 0 2006.259.08:16:56.84$vc4f8/vb=2,5 2006.259.08:16:56.84#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.259.08:16:56.84#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.259.08:16:56.84#ibcon#ireg 11 cls_cnt 2 2006.259.08:16:56.84#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.259.08:16:56.90#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.259.08:16:56.90#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.259.08:16:56.90#ibcon#enter wrdev, iclass 36, count 2 2006.259.08:16:56.90#ibcon#first serial, iclass 36, count 2 2006.259.08:16:56.90#ibcon#enter sib2, iclass 36, count 2 2006.259.08:16:56.90#ibcon#flushed, iclass 36, count 2 2006.259.08:16:56.90#ibcon#about to write, iclass 36, count 2 2006.259.08:16:56.90#ibcon#wrote, iclass 36, count 2 2006.259.08:16:56.90#ibcon#about to read 3, iclass 36, count 2 2006.259.08:16:56.92#ibcon#read 3, iclass 36, count 2 2006.259.08:16:56.92#ibcon#about to read 4, iclass 36, count 2 2006.259.08:16:56.92#ibcon#read 4, iclass 36, count 2 2006.259.08:16:56.92#ibcon#about to read 5, iclass 36, count 2 2006.259.08:16:56.92#ibcon#read 5, iclass 36, count 2 2006.259.08:16:56.92#ibcon#about to read 6, iclass 36, count 2 2006.259.08:16:56.92#ibcon#read 6, iclass 36, count 2 2006.259.08:16:56.92#ibcon#end of sib2, iclass 36, count 2 2006.259.08:16:56.92#ibcon#*mode == 0, iclass 36, count 2 2006.259.08:16:56.92#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.259.08:16:56.92#ibcon#[27=AT02-05\r\n] 2006.259.08:16:56.92#ibcon#*before write, iclass 36, count 2 2006.259.08:16:56.92#ibcon#enter sib2, iclass 36, count 2 2006.259.08:16:56.92#ibcon#flushed, iclass 36, count 2 2006.259.08:16:56.92#ibcon#about to write, iclass 36, count 2 2006.259.08:16:56.92#ibcon#wrote, iclass 36, count 2 2006.259.08:16:56.92#ibcon#about to read 3, iclass 36, count 2 2006.259.08:16:56.95#ibcon#read 3, iclass 36, count 2 2006.259.08:16:56.95#ibcon#about to read 4, iclass 36, count 2 2006.259.08:16:56.95#ibcon#read 4, iclass 36, count 2 2006.259.08:16:56.95#ibcon#about to read 5, iclass 36, count 2 2006.259.08:16:56.95#ibcon#read 5, iclass 36, count 2 2006.259.08:16:56.95#ibcon#about to read 6, iclass 36, count 2 2006.259.08:16:56.95#ibcon#read 6, iclass 36, count 2 2006.259.08:16:56.95#ibcon#end of sib2, iclass 36, count 2 2006.259.08:16:56.95#ibcon#*after write, iclass 36, count 2 2006.259.08:16:56.95#ibcon#*before return 0, iclass 36, count 2 2006.259.08:16:56.95#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.259.08:16:56.95#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.259.08:16:56.95#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.259.08:16:56.95#ibcon#ireg 7 cls_cnt 0 2006.259.08:16:56.95#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.259.08:16:57.07#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.259.08:16:57.07#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.259.08:16:57.07#ibcon#enter wrdev, iclass 36, count 0 2006.259.08:16:57.07#ibcon#first serial, iclass 36, count 0 2006.259.08:16:57.07#ibcon#enter sib2, iclass 36, count 0 2006.259.08:16:57.07#ibcon#flushed, iclass 36, count 0 2006.259.08:16:57.07#ibcon#about to write, iclass 36, count 0 2006.259.08:16:57.07#ibcon#wrote, iclass 36, count 0 2006.259.08:16:57.07#ibcon#about to read 3, iclass 36, count 0 2006.259.08:16:57.09#ibcon#read 3, iclass 36, count 0 2006.259.08:16:57.09#ibcon#about to read 4, iclass 36, count 0 2006.259.08:16:57.09#ibcon#read 4, iclass 36, count 0 2006.259.08:16:57.09#ibcon#about to read 5, iclass 36, count 0 2006.259.08:16:57.09#ibcon#read 5, iclass 36, count 0 2006.259.08:16:57.09#ibcon#about to read 6, iclass 36, count 0 2006.259.08:16:57.09#ibcon#read 6, iclass 36, count 0 2006.259.08:16:57.09#ibcon#end of sib2, iclass 36, count 0 2006.259.08:16:57.09#ibcon#*mode == 0, iclass 36, count 0 2006.259.08:16:57.09#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.259.08:16:57.09#ibcon#[27=USB\r\n] 2006.259.08:16:57.09#ibcon#*before write, iclass 36, count 0 2006.259.08:16:57.09#ibcon#enter sib2, iclass 36, count 0 2006.259.08:16:57.09#ibcon#flushed, iclass 36, count 0 2006.259.08:16:57.09#ibcon#about to write, iclass 36, count 0 2006.259.08:16:57.09#ibcon#wrote, iclass 36, count 0 2006.259.08:16:57.09#ibcon#about to read 3, iclass 36, count 0 2006.259.08:16:57.12#ibcon#read 3, iclass 36, count 0 2006.259.08:16:57.12#ibcon#about to read 4, iclass 36, count 0 2006.259.08:16:57.12#ibcon#read 4, iclass 36, count 0 2006.259.08:16:57.12#ibcon#about to read 5, iclass 36, count 0 2006.259.08:16:57.12#ibcon#read 5, iclass 36, count 0 2006.259.08:16:57.12#ibcon#about to read 6, iclass 36, count 0 2006.259.08:16:57.12#ibcon#read 6, iclass 36, count 0 2006.259.08:16:57.12#ibcon#end of sib2, iclass 36, count 0 2006.259.08:16:57.12#ibcon#*after write, iclass 36, count 0 2006.259.08:16:57.12#ibcon#*before return 0, iclass 36, count 0 2006.259.08:16:57.12#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.259.08:16:57.12#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.259.08:16:57.12#ibcon#about to clear, iclass 36 cls_cnt 0 2006.259.08:16:57.12#ibcon#cleared, iclass 36 cls_cnt 0 2006.259.08:16:57.12$vc4f8/vblo=3,656.99 2006.259.08:16:57.12#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.259.08:16:57.12#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.259.08:16:57.12#ibcon#ireg 17 cls_cnt 0 2006.259.08:16:57.12#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.259.08:16:57.12#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.259.08:16:57.12#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.259.08:16:57.12#ibcon#enter wrdev, iclass 38, count 0 2006.259.08:16:57.12#ibcon#first serial, iclass 38, count 0 2006.259.08:16:57.12#ibcon#enter sib2, iclass 38, count 0 2006.259.08:16:57.12#ibcon#flushed, iclass 38, count 0 2006.259.08:16:57.12#ibcon#about to write, iclass 38, count 0 2006.259.08:16:57.12#ibcon#wrote, iclass 38, count 0 2006.259.08:16:57.12#ibcon#about to read 3, iclass 38, count 0 2006.259.08:16:57.14#ibcon#read 3, iclass 38, count 0 2006.259.08:16:57.14#ibcon#about to read 4, iclass 38, count 0 2006.259.08:16:57.14#ibcon#read 4, iclass 38, count 0 2006.259.08:16:57.14#ibcon#about to read 5, iclass 38, count 0 2006.259.08:16:57.14#ibcon#read 5, iclass 38, count 0 2006.259.08:16:57.14#ibcon#about to read 6, iclass 38, count 0 2006.259.08:16:57.14#ibcon#read 6, iclass 38, count 0 2006.259.08:16:57.14#ibcon#end of sib2, iclass 38, count 0 2006.259.08:16:57.14#ibcon#*mode == 0, iclass 38, count 0 2006.259.08:16:57.14#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.259.08:16:57.14#ibcon#[28=FRQ=03,656.99\r\n] 2006.259.08:16:57.14#ibcon#*before write, iclass 38, count 0 2006.259.08:16:57.14#ibcon#enter sib2, iclass 38, count 0 2006.259.08:16:57.14#ibcon#flushed, iclass 38, count 0 2006.259.08:16:57.14#ibcon#about to write, iclass 38, count 0 2006.259.08:16:57.14#ibcon#wrote, iclass 38, count 0 2006.259.08:16:57.14#ibcon#about to read 3, iclass 38, count 0 2006.259.08:16:57.18#ibcon#read 3, iclass 38, count 0 2006.259.08:16:57.18#ibcon#about to read 4, iclass 38, count 0 2006.259.08:16:57.18#ibcon#read 4, iclass 38, count 0 2006.259.08:16:57.18#ibcon#about to read 5, iclass 38, count 0 2006.259.08:16:57.18#ibcon#read 5, iclass 38, count 0 2006.259.08:16:57.18#ibcon#about to read 6, iclass 38, count 0 2006.259.08:16:57.18#ibcon#read 6, iclass 38, count 0 2006.259.08:16:57.18#ibcon#end of sib2, iclass 38, count 0 2006.259.08:16:57.18#ibcon#*after write, iclass 38, count 0 2006.259.08:16:57.18#ibcon#*before return 0, iclass 38, count 0 2006.259.08:16:57.18#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.259.08:16:57.18#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.259.08:16:57.18#ibcon#about to clear, iclass 38 cls_cnt 0 2006.259.08:16:57.18#ibcon#cleared, iclass 38 cls_cnt 0 2006.259.08:16:57.18$vc4f8/vb=3,4 2006.259.08:16:57.18#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.259.08:16:57.18#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.259.08:16:57.18#ibcon#ireg 11 cls_cnt 2 2006.259.08:16:57.18#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.259.08:16:57.24#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.259.08:16:57.24#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.259.08:16:57.24#ibcon#enter wrdev, iclass 40, count 2 2006.259.08:16:57.24#ibcon#first serial, iclass 40, count 2 2006.259.08:16:57.24#ibcon#enter sib2, iclass 40, count 2 2006.259.08:16:57.24#ibcon#flushed, iclass 40, count 2 2006.259.08:16:57.24#ibcon#about to write, iclass 40, count 2 2006.259.08:16:57.24#ibcon#wrote, iclass 40, count 2 2006.259.08:16:57.24#ibcon#about to read 3, iclass 40, count 2 2006.259.08:16:57.26#ibcon#read 3, iclass 40, count 2 2006.259.08:16:57.26#ibcon#about to read 4, iclass 40, count 2 2006.259.08:16:57.26#ibcon#read 4, iclass 40, count 2 2006.259.08:16:57.26#ibcon#about to read 5, iclass 40, count 2 2006.259.08:16:57.26#ibcon#read 5, iclass 40, count 2 2006.259.08:16:57.26#ibcon#about to read 6, iclass 40, count 2 2006.259.08:16:57.26#ibcon#read 6, iclass 40, count 2 2006.259.08:16:57.26#ibcon#end of sib2, iclass 40, count 2 2006.259.08:16:57.26#ibcon#*mode == 0, iclass 40, count 2 2006.259.08:16:57.26#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.259.08:16:57.26#ibcon#[27=AT03-04\r\n] 2006.259.08:16:57.26#ibcon#*before write, iclass 40, count 2 2006.259.08:16:57.26#ibcon#enter sib2, iclass 40, count 2 2006.259.08:16:57.26#ibcon#flushed, iclass 40, count 2 2006.259.08:16:57.26#ibcon#about to write, iclass 40, count 2 2006.259.08:16:57.26#ibcon#wrote, iclass 40, count 2 2006.259.08:16:57.26#ibcon#about to read 3, iclass 40, count 2 2006.259.08:16:57.29#ibcon#read 3, iclass 40, count 2 2006.259.08:16:57.29#ibcon#about to read 4, iclass 40, count 2 2006.259.08:16:57.29#ibcon#read 4, iclass 40, count 2 2006.259.08:16:57.29#ibcon#about to read 5, iclass 40, count 2 2006.259.08:16:57.29#ibcon#read 5, iclass 40, count 2 2006.259.08:16:57.29#ibcon#about to read 6, iclass 40, count 2 2006.259.08:16:57.29#ibcon#read 6, iclass 40, count 2 2006.259.08:16:57.29#ibcon#end of sib2, iclass 40, count 2 2006.259.08:16:57.29#ibcon#*after write, iclass 40, count 2 2006.259.08:16:57.29#ibcon#*before return 0, iclass 40, count 2 2006.259.08:16:57.29#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.259.08:16:57.29#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.259.08:16:57.29#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.259.08:16:57.29#ibcon#ireg 7 cls_cnt 0 2006.259.08:16:57.29#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.259.08:16:57.41#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.259.08:16:57.41#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.259.08:16:57.41#ibcon#enter wrdev, iclass 40, count 0 2006.259.08:16:57.41#ibcon#first serial, iclass 40, count 0 2006.259.08:16:57.41#ibcon#enter sib2, iclass 40, count 0 2006.259.08:16:57.41#ibcon#flushed, iclass 40, count 0 2006.259.08:16:57.41#ibcon#about to write, iclass 40, count 0 2006.259.08:16:57.41#ibcon#wrote, iclass 40, count 0 2006.259.08:16:57.41#ibcon#about to read 3, iclass 40, count 0 2006.259.08:16:57.43#ibcon#read 3, iclass 40, count 0 2006.259.08:16:57.43#ibcon#about to read 4, iclass 40, count 0 2006.259.08:16:57.43#ibcon#read 4, iclass 40, count 0 2006.259.08:16:57.43#ibcon#about to read 5, iclass 40, count 0 2006.259.08:16:57.43#ibcon#read 5, iclass 40, count 0 2006.259.08:16:57.43#ibcon#about to read 6, iclass 40, count 0 2006.259.08:16:57.43#ibcon#read 6, iclass 40, count 0 2006.259.08:16:57.43#ibcon#end of sib2, iclass 40, count 0 2006.259.08:16:57.43#ibcon#*mode == 0, iclass 40, count 0 2006.259.08:16:57.43#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.259.08:16:57.43#ibcon#[27=USB\r\n] 2006.259.08:16:57.43#ibcon#*before write, iclass 40, count 0 2006.259.08:16:57.43#ibcon#enter sib2, iclass 40, count 0 2006.259.08:16:57.43#ibcon#flushed, iclass 40, count 0 2006.259.08:16:57.43#ibcon#about to write, iclass 40, count 0 2006.259.08:16:57.43#ibcon#wrote, iclass 40, count 0 2006.259.08:16:57.43#ibcon#about to read 3, iclass 40, count 0 2006.259.08:16:57.46#ibcon#read 3, iclass 40, count 0 2006.259.08:16:57.46#ibcon#about to read 4, iclass 40, count 0 2006.259.08:16:57.46#ibcon#read 4, iclass 40, count 0 2006.259.08:16:57.46#ibcon#about to read 5, iclass 40, count 0 2006.259.08:16:57.46#ibcon#read 5, iclass 40, count 0 2006.259.08:16:57.46#ibcon#about to read 6, iclass 40, count 0 2006.259.08:16:57.46#ibcon#read 6, iclass 40, count 0 2006.259.08:16:57.46#ibcon#end of sib2, iclass 40, count 0 2006.259.08:16:57.46#ibcon#*after write, iclass 40, count 0 2006.259.08:16:57.46#ibcon#*before return 0, iclass 40, count 0 2006.259.08:16:57.46#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.259.08:16:57.46#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.259.08:16:57.46#ibcon#about to clear, iclass 40 cls_cnt 0 2006.259.08:16:57.46#ibcon#cleared, iclass 40 cls_cnt 0 2006.259.08:16:57.46$vc4f8/vblo=4,712.99 2006.259.08:16:57.46#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.259.08:16:57.46#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.259.08:16:57.46#ibcon#ireg 17 cls_cnt 0 2006.259.08:16:57.46#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.259.08:16:57.46#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.259.08:16:57.46#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.259.08:16:57.46#ibcon#enter wrdev, iclass 4, count 0 2006.259.08:16:57.46#ibcon#first serial, iclass 4, count 0 2006.259.08:16:57.46#ibcon#enter sib2, iclass 4, count 0 2006.259.08:16:57.46#ibcon#flushed, iclass 4, count 0 2006.259.08:16:57.46#ibcon#about to write, iclass 4, count 0 2006.259.08:16:57.46#ibcon#wrote, iclass 4, count 0 2006.259.08:16:57.46#ibcon#about to read 3, iclass 4, count 0 2006.259.08:16:57.48#ibcon#read 3, iclass 4, count 0 2006.259.08:16:57.48#ibcon#about to read 4, iclass 4, count 0 2006.259.08:16:57.48#ibcon#read 4, iclass 4, count 0 2006.259.08:16:57.48#ibcon#about to read 5, iclass 4, count 0 2006.259.08:16:57.48#ibcon#read 5, iclass 4, count 0 2006.259.08:16:57.48#ibcon#about to read 6, iclass 4, count 0 2006.259.08:16:57.48#ibcon#read 6, iclass 4, count 0 2006.259.08:16:57.48#ibcon#end of sib2, iclass 4, count 0 2006.259.08:16:57.48#ibcon#*mode == 0, iclass 4, count 0 2006.259.08:16:57.48#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.259.08:16:57.48#ibcon#[28=FRQ=04,712.99\r\n] 2006.259.08:16:57.48#ibcon#*before write, iclass 4, count 0 2006.259.08:16:57.48#ibcon#enter sib2, iclass 4, count 0 2006.259.08:16:57.48#ibcon#flushed, iclass 4, count 0 2006.259.08:16:57.48#ibcon#about to write, iclass 4, count 0 2006.259.08:16:57.48#ibcon#wrote, iclass 4, count 0 2006.259.08:16:57.48#ibcon#about to read 3, iclass 4, count 0 2006.259.08:16:57.52#ibcon#read 3, iclass 4, count 0 2006.259.08:16:57.52#ibcon#about to read 4, iclass 4, count 0 2006.259.08:16:57.52#ibcon#read 4, iclass 4, count 0 2006.259.08:16:57.52#ibcon#about to read 5, iclass 4, count 0 2006.259.08:16:57.52#ibcon#read 5, iclass 4, count 0 2006.259.08:16:57.52#ibcon#about to read 6, iclass 4, count 0 2006.259.08:16:57.52#ibcon#read 6, iclass 4, count 0 2006.259.08:16:57.52#ibcon#end of sib2, iclass 4, count 0 2006.259.08:16:57.52#ibcon#*after write, iclass 4, count 0 2006.259.08:16:57.52#ibcon#*before return 0, iclass 4, count 0 2006.259.08:16:57.52#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.259.08:16:57.52#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.259.08:16:57.52#ibcon#about to clear, iclass 4 cls_cnt 0 2006.259.08:16:57.52#ibcon#cleared, iclass 4 cls_cnt 0 2006.259.08:16:57.52$vc4f8/vb=4,5 2006.259.08:16:57.52#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.259.08:16:57.52#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.259.08:16:57.52#ibcon#ireg 11 cls_cnt 2 2006.259.08:16:57.52#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.259.08:16:57.58#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.259.08:16:57.58#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.259.08:16:57.58#ibcon#enter wrdev, iclass 6, count 2 2006.259.08:16:57.58#ibcon#first serial, iclass 6, count 2 2006.259.08:16:57.58#ibcon#enter sib2, iclass 6, count 2 2006.259.08:16:57.58#ibcon#flushed, iclass 6, count 2 2006.259.08:16:57.58#ibcon#about to write, iclass 6, count 2 2006.259.08:16:57.58#ibcon#wrote, iclass 6, count 2 2006.259.08:16:57.58#ibcon#about to read 3, iclass 6, count 2 2006.259.08:16:57.60#ibcon#read 3, iclass 6, count 2 2006.259.08:16:57.60#ibcon#about to read 4, iclass 6, count 2 2006.259.08:16:57.60#ibcon#read 4, iclass 6, count 2 2006.259.08:16:57.60#ibcon#about to read 5, iclass 6, count 2 2006.259.08:16:57.60#ibcon#read 5, iclass 6, count 2 2006.259.08:16:57.60#ibcon#about to read 6, iclass 6, count 2 2006.259.08:16:57.60#ibcon#read 6, iclass 6, count 2 2006.259.08:16:57.60#ibcon#end of sib2, iclass 6, count 2 2006.259.08:16:57.60#ibcon#*mode == 0, iclass 6, count 2 2006.259.08:16:57.60#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.259.08:16:57.60#ibcon#[27=AT04-05\r\n] 2006.259.08:16:57.60#ibcon#*before write, iclass 6, count 2 2006.259.08:16:57.60#ibcon#enter sib2, iclass 6, count 2 2006.259.08:16:57.60#ibcon#flushed, iclass 6, count 2 2006.259.08:16:57.60#ibcon#about to write, iclass 6, count 2 2006.259.08:16:57.60#ibcon#wrote, iclass 6, count 2 2006.259.08:16:57.60#ibcon#about to read 3, iclass 6, count 2 2006.259.08:16:57.63#ibcon#read 3, iclass 6, count 2 2006.259.08:16:57.63#ibcon#about to read 4, iclass 6, count 2 2006.259.08:16:57.63#ibcon#read 4, iclass 6, count 2 2006.259.08:16:57.63#ibcon#about to read 5, iclass 6, count 2 2006.259.08:16:57.63#ibcon#read 5, iclass 6, count 2 2006.259.08:16:57.63#ibcon#about to read 6, iclass 6, count 2 2006.259.08:16:57.63#ibcon#read 6, iclass 6, count 2 2006.259.08:16:57.63#ibcon#end of sib2, iclass 6, count 2 2006.259.08:16:57.63#ibcon#*after write, iclass 6, count 2 2006.259.08:16:57.63#ibcon#*before return 0, iclass 6, count 2 2006.259.08:16:57.63#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.259.08:16:57.63#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.259.08:16:57.63#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.259.08:16:57.63#ibcon#ireg 7 cls_cnt 0 2006.259.08:16:57.63#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.259.08:16:57.75#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.259.08:16:57.75#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.259.08:16:57.75#ibcon#enter wrdev, iclass 6, count 0 2006.259.08:16:57.75#ibcon#first serial, iclass 6, count 0 2006.259.08:16:57.75#ibcon#enter sib2, iclass 6, count 0 2006.259.08:16:57.75#ibcon#flushed, iclass 6, count 0 2006.259.08:16:57.75#ibcon#about to write, iclass 6, count 0 2006.259.08:16:57.75#ibcon#wrote, iclass 6, count 0 2006.259.08:16:57.75#ibcon#about to read 3, iclass 6, count 0 2006.259.08:16:57.77#ibcon#read 3, iclass 6, count 0 2006.259.08:16:57.77#ibcon#about to read 4, iclass 6, count 0 2006.259.08:16:57.77#ibcon#read 4, iclass 6, count 0 2006.259.08:16:57.77#ibcon#about to read 5, iclass 6, count 0 2006.259.08:16:57.77#ibcon#read 5, iclass 6, count 0 2006.259.08:16:57.77#ibcon#about to read 6, iclass 6, count 0 2006.259.08:16:57.77#ibcon#read 6, iclass 6, count 0 2006.259.08:16:57.77#ibcon#end of sib2, iclass 6, count 0 2006.259.08:16:57.77#ibcon#*mode == 0, iclass 6, count 0 2006.259.08:16:57.77#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.259.08:16:57.77#ibcon#[27=USB\r\n] 2006.259.08:16:57.77#ibcon#*before write, iclass 6, count 0 2006.259.08:16:57.77#ibcon#enter sib2, iclass 6, count 0 2006.259.08:16:57.77#ibcon#flushed, iclass 6, count 0 2006.259.08:16:57.77#ibcon#about to write, iclass 6, count 0 2006.259.08:16:57.77#ibcon#wrote, iclass 6, count 0 2006.259.08:16:57.77#ibcon#about to read 3, iclass 6, count 0 2006.259.08:16:57.80#ibcon#read 3, iclass 6, count 0 2006.259.08:16:57.80#ibcon#about to read 4, iclass 6, count 0 2006.259.08:16:57.80#ibcon#read 4, iclass 6, count 0 2006.259.08:16:57.80#ibcon#about to read 5, iclass 6, count 0 2006.259.08:16:57.80#ibcon#read 5, iclass 6, count 0 2006.259.08:16:57.80#ibcon#about to read 6, iclass 6, count 0 2006.259.08:16:57.80#ibcon#read 6, iclass 6, count 0 2006.259.08:16:57.80#ibcon#end of sib2, iclass 6, count 0 2006.259.08:16:57.80#ibcon#*after write, iclass 6, count 0 2006.259.08:16:57.80#ibcon#*before return 0, iclass 6, count 0 2006.259.08:16:57.80#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.259.08:16:57.80#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.259.08:16:57.80#ibcon#about to clear, iclass 6 cls_cnt 0 2006.259.08:16:57.80#ibcon#cleared, iclass 6 cls_cnt 0 2006.259.08:16:57.80$vc4f8/vblo=5,744.99 2006.259.08:16:57.80#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.259.08:16:57.80#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.259.08:16:57.80#ibcon#ireg 17 cls_cnt 0 2006.259.08:16:57.80#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.259.08:16:57.80#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.259.08:16:57.80#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.259.08:16:57.80#ibcon#enter wrdev, iclass 10, count 0 2006.259.08:16:57.80#ibcon#first serial, iclass 10, count 0 2006.259.08:16:57.80#ibcon#enter sib2, iclass 10, count 0 2006.259.08:16:57.80#ibcon#flushed, iclass 10, count 0 2006.259.08:16:57.80#ibcon#about to write, iclass 10, count 0 2006.259.08:16:57.80#ibcon#wrote, iclass 10, count 0 2006.259.08:16:57.80#ibcon#about to read 3, iclass 10, count 0 2006.259.08:16:57.82#ibcon#read 3, iclass 10, count 0 2006.259.08:16:57.82#ibcon#about to read 4, iclass 10, count 0 2006.259.08:16:57.82#ibcon#read 4, iclass 10, count 0 2006.259.08:16:57.82#ibcon#about to read 5, iclass 10, count 0 2006.259.08:16:57.82#ibcon#read 5, iclass 10, count 0 2006.259.08:16:57.82#ibcon#about to read 6, iclass 10, count 0 2006.259.08:16:57.82#ibcon#read 6, iclass 10, count 0 2006.259.08:16:57.82#ibcon#end of sib2, iclass 10, count 0 2006.259.08:16:57.82#ibcon#*mode == 0, iclass 10, count 0 2006.259.08:16:57.82#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.259.08:16:57.82#ibcon#[28=FRQ=05,744.99\r\n] 2006.259.08:16:57.82#ibcon#*before write, iclass 10, count 0 2006.259.08:16:57.82#ibcon#enter sib2, iclass 10, count 0 2006.259.08:16:57.82#ibcon#flushed, iclass 10, count 0 2006.259.08:16:57.82#ibcon#about to write, iclass 10, count 0 2006.259.08:16:57.82#ibcon#wrote, iclass 10, count 0 2006.259.08:16:57.82#ibcon#about to read 3, iclass 10, count 0 2006.259.08:16:57.86#ibcon#read 3, iclass 10, count 0 2006.259.08:16:57.86#ibcon#about to read 4, iclass 10, count 0 2006.259.08:16:57.86#ibcon#read 4, iclass 10, count 0 2006.259.08:16:57.86#ibcon#about to read 5, iclass 10, count 0 2006.259.08:16:57.86#ibcon#read 5, iclass 10, count 0 2006.259.08:16:57.86#ibcon#about to read 6, iclass 10, count 0 2006.259.08:16:57.86#ibcon#read 6, iclass 10, count 0 2006.259.08:16:57.86#ibcon#end of sib2, iclass 10, count 0 2006.259.08:16:57.86#ibcon#*after write, iclass 10, count 0 2006.259.08:16:57.86#ibcon#*before return 0, iclass 10, count 0 2006.259.08:16:57.86#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.259.08:16:57.86#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.259.08:16:57.86#ibcon#about to clear, iclass 10 cls_cnt 0 2006.259.08:16:57.86#ibcon#cleared, iclass 10 cls_cnt 0 2006.259.08:16:57.86$vc4f8/vb=5,4 2006.259.08:16:57.86#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.259.08:16:57.86#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.259.08:16:57.86#ibcon#ireg 11 cls_cnt 2 2006.259.08:16:57.86#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.259.08:16:57.92#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.259.08:16:57.92#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.259.08:16:57.92#ibcon#enter wrdev, iclass 12, count 2 2006.259.08:16:57.92#ibcon#first serial, iclass 12, count 2 2006.259.08:16:57.92#ibcon#enter sib2, iclass 12, count 2 2006.259.08:16:57.92#ibcon#flushed, iclass 12, count 2 2006.259.08:16:57.92#ibcon#about to write, iclass 12, count 2 2006.259.08:16:57.92#ibcon#wrote, iclass 12, count 2 2006.259.08:16:57.92#ibcon#about to read 3, iclass 12, count 2 2006.259.08:16:57.94#ibcon#read 3, iclass 12, count 2 2006.259.08:16:57.94#ibcon#about to read 4, iclass 12, count 2 2006.259.08:16:57.94#ibcon#read 4, iclass 12, count 2 2006.259.08:16:57.94#ibcon#about to read 5, iclass 12, count 2 2006.259.08:16:57.94#ibcon#read 5, iclass 12, count 2 2006.259.08:16:57.94#ibcon#about to read 6, iclass 12, count 2 2006.259.08:16:57.94#ibcon#read 6, iclass 12, count 2 2006.259.08:16:57.94#ibcon#end of sib2, iclass 12, count 2 2006.259.08:16:57.94#ibcon#*mode == 0, iclass 12, count 2 2006.259.08:16:57.94#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.259.08:16:57.94#ibcon#[27=AT05-04\r\n] 2006.259.08:16:57.94#ibcon#*before write, iclass 12, count 2 2006.259.08:16:57.94#ibcon#enter sib2, iclass 12, count 2 2006.259.08:16:57.94#ibcon#flushed, iclass 12, count 2 2006.259.08:16:57.94#ibcon#about to write, iclass 12, count 2 2006.259.08:16:57.94#ibcon#wrote, iclass 12, count 2 2006.259.08:16:57.94#ibcon#about to read 3, iclass 12, count 2 2006.259.08:16:57.97#ibcon#read 3, iclass 12, count 2 2006.259.08:16:57.97#ibcon#about to read 4, iclass 12, count 2 2006.259.08:16:57.97#ibcon#read 4, iclass 12, count 2 2006.259.08:16:57.97#ibcon#about to read 5, iclass 12, count 2 2006.259.08:16:57.97#ibcon#read 5, iclass 12, count 2 2006.259.08:16:57.97#ibcon#about to read 6, iclass 12, count 2 2006.259.08:16:57.97#ibcon#read 6, iclass 12, count 2 2006.259.08:16:57.97#ibcon#end of sib2, iclass 12, count 2 2006.259.08:16:57.97#ibcon#*after write, iclass 12, count 2 2006.259.08:16:57.97#ibcon#*before return 0, iclass 12, count 2 2006.259.08:16:57.97#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.259.08:16:57.97#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.259.08:16:57.97#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.259.08:16:57.97#ibcon#ireg 7 cls_cnt 0 2006.259.08:16:57.97#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.259.08:16:58.09#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.259.08:16:58.09#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.259.08:16:58.09#ibcon#enter wrdev, iclass 12, count 0 2006.259.08:16:58.09#ibcon#first serial, iclass 12, count 0 2006.259.08:16:58.09#ibcon#enter sib2, iclass 12, count 0 2006.259.08:16:58.09#ibcon#flushed, iclass 12, count 0 2006.259.08:16:58.09#ibcon#about to write, iclass 12, count 0 2006.259.08:16:58.09#ibcon#wrote, iclass 12, count 0 2006.259.08:16:58.09#ibcon#about to read 3, iclass 12, count 0 2006.259.08:16:58.11#ibcon#read 3, iclass 12, count 0 2006.259.08:16:58.11#ibcon#about to read 4, iclass 12, count 0 2006.259.08:16:58.11#ibcon#read 4, iclass 12, count 0 2006.259.08:16:58.11#ibcon#about to read 5, iclass 12, count 0 2006.259.08:16:58.11#ibcon#read 5, iclass 12, count 0 2006.259.08:16:58.11#ibcon#about to read 6, iclass 12, count 0 2006.259.08:16:58.11#ibcon#read 6, iclass 12, count 0 2006.259.08:16:58.11#ibcon#end of sib2, iclass 12, count 0 2006.259.08:16:58.11#ibcon#*mode == 0, iclass 12, count 0 2006.259.08:16:58.11#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.259.08:16:58.11#ibcon#[27=USB\r\n] 2006.259.08:16:58.11#ibcon#*before write, iclass 12, count 0 2006.259.08:16:58.11#ibcon#enter sib2, iclass 12, count 0 2006.259.08:16:58.11#ibcon#flushed, iclass 12, count 0 2006.259.08:16:58.11#ibcon#about to write, iclass 12, count 0 2006.259.08:16:58.11#ibcon#wrote, iclass 12, count 0 2006.259.08:16:58.11#ibcon#about to read 3, iclass 12, count 0 2006.259.08:16:58.14#ibcon#read 3, iclass 12, count 0 2006.259.08:16:58.14#ibcon#about to read 4, iclass 12, count 0 2006.259.08:16:58.14#ibcon#read 4, iclass 12, count 0 2006.259.08:16:58.14#ibcon#about to read 5, iclass 12, count 0 2006.259.08:16:58.14#ibcon#read 5, iclass 12, count 0 2006.259.08:16:58.14#ibcon#about to read 6, iclass 12, count 0 2006.259.08:16:58.14#ibcon#read 6, iclass 12, count 0 2006.259.08:16:58.14#ibcon#end of sib2, iclass 12, count 0 2006.259.08:16:58.14#ibcon#*after write, iclass 12, count 0 2006.259.08:16:58.14#ibcon#*before return 0, iclass 12, count 0 2006.259.08:16:58.14#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.259.08:16:58.14#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.259.08:16:58.14#ibcon#about to clear, iclass 12 cls_cnt 0 2006.259.08:16:58.14#ibcon#cleared, iclass 12 cls_cnt 0 2006.259.08:16:58.14$vc4f8/vblo=6,752.99 2006.259.08:16:58.14#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.259.08:16:58.14#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.259.08:16:58.14#ibcon#ireg 17 cls_cnt 0 2006.259.08:16:58.14#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.259.08:16:58.14#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.259.08:16:58.14#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.259.08:16:58.14#ibcon#enter wrdev, iclass 14, count 0 2006.259.08:16:58.14#ibcon#first serial, iclass 14, count 0 2006.259.08:16:58.14#ibcon#enter sib2, iclass 14, count 0 2006.259.08:16:58.14#ibcon#flushed, iclass 14, count 0 2006.259.08:16:58.14#ibcon#about to write, iclass 14, count 0 2006.259.08:16:58.14#ibcon#wrote, iclass 14, count 0 2006.259.08:16:58.14#ibcon#about to read 3, iclass 14, count 0 2006.259.08:16:58.16#ibcon#read 3, iclass 14, count 0 2006.259.08:16:58.16#ibcon#about to read 4, iclass 14, count 0 2006.259.08:16:58.16#ibcon#read 4, iclass 14, count 0 2006.259.08:16:58.16#ibcon#about to read 5, iclass 14, count 0 2006.259.08:16:58.16#ibcon#read 5, iclass 14, count 0 2006.259.08:16:58.16#ibcon#about to read 6, iclass 14, count 0 2006.259.08:16:58.16#ibcon#read 6, iclass 14, count 0 2006.259.08:16:58.16#ibcon#end of sib2, iclass 14, count 0 2006.259.08:16:58.16#ibcon#*mode == 0, iclass 14, count 0 2006.259.08:16:58.16#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.259.08:16:58.16#ibcon#[28=FRQ=06,752.99\r\n] 2006.259.08:16:58.16#ibcon#*before write, iclass 14, count 0 2006.259.08:16:58.16#ibcon#enter sib2, iclass 14, count 0 2006.259.08:16:58.16#ibcon#flushed, iclass 14, count 0 2006.259.08:16:58.16#ibcon#about to write, iclass 14, count 0 2006.259.08:16:58.16#ibcon#wrote, iclass 14, count 0 2006.259.08:16:58.16#ibcon#about to read 3, iclass 14, count 0 2006.259.08:16:58.20#ibcon#read 3, iclass 14, count 0 2006.259.08:16:58.20#ibcon#about to read 4, iclass 14, count 0 2006.259.08:16:58.20#ibcon#read 4, iclass 14, count 0 2006.259.08:16:58.20#ibcon#about to read 5, iclass 14, count 0 2006.259.08:16:58.20#ibcon#read 5, iclass 14, count 0 2006.259.08:16:58.20#ibcon#about to read 6, iclass 14, count 0 2006.259.08:16:58.20#ibcon#read 6, iclass 14, count 0 2006.259.08:16:58.20#ibcon#end of sib2, iclass 14, count 0 2006.259.08:16:58.20#ibcon#*after write, iclass 14, count 0 2006.259.08:16:58.20#ibcon#*before return 0, iclass 14, count 0 2006.259.08:16:58.20#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.259.08:16:58.20#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.259.08:16:58.20#ibcon#about to clear, iclass 14 cls_cnt 0 2006.259.08:16:58.20#ibcon#cleared, iclass 14 cls_cnt 0 2006.259.08:16:58.20$vc4f8/vb=6,4 2006.259.08:16:58.20#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.259.08:16:58.20#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.259.08:16:58.20#ibcon#ireg 11 cls_cnt 2 2006.259.08:16:58.20#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.259.08:16:58.26#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.259.08:16:58.26#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.259.08:16:58.26#ibcon#enter wrdev, iclass 16, count 2 2006.259.08:16:58.26#ibcon#first serial, iclass 16, count 2 2006.259.08:16:58.26#ibcon#enter sib2, iclass 16, count 2 2006.259.08:16:58.26#ibcon#flushed, iclass 16, count 2 2006.259.08:16:58.26#ibcon#about to write, iclass 16, count 2 2006.259.08:16:58.26#ibcon#wrote, iclass 16, count 2 2006.259.08:16:58.26#ibcon#about to read 3, iclass 16, count 2 2006.259.08:16:58.28#ibcon#read 3, iclass 16, count 2 2006.259.08:16:58.28#ibcon#about to read 4, iclass 16, count 2 2006.259.08:16:58.28#ibcon#read 4, iclass 16, count 2 2006.259.08:16:58.28#ibcon#about to read 5, iclass 16, count 2 2006.259.08:16:58.28#ibcon#read 5, iclass 16, count 2 2006.259.08:16:58.28#ibcon#about to read 6, iclass 16, count 2 2006.259.08:16:58.28#ibcon#read 6, iclass 16, count 2 2006.259.08:16:58.28#ibcon#end of sib2, iclass 16, count 2 2006.259.08:16:58.28#ibcon#*mode == 0, iclass 16, count 2 2006.259.08:16:58.28#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.259.08:16:58.28#ibcon#[27=AT06-04\r\n] 2006.259.08:16:58.28#ibcon#*before write, iclass 16, count 2 2006.259.08:16:58.28#ibcon#enter sib2, iclass 16, count 2 2006.259.08:16:58.28#ibcon#flushed, iclass 16, count 2 2006.259.08:16:58.28#ibcon#about to write, iclass 16, count 2 2006.259.08:16:58.28#ibcon#wrote, iclass 16, count 2 2006.259.08:16:58.28#ibcon#about to read 3, iclass 16, count 2 2006.259.08:16:58.31#ibcon#read 3, iclass 16, count 2 2006.259.08:16:58.31#ibcon#about to read 4, iclass 16, count 2 2006.259.08:16:58.31#ibcon#read 4, iclass 16, count 2 2006.259.08:16:58.31#ibcon#about to read 5, iclass 16, count 2 2006.259.08:16:58.31#ibcon#read 5, iclass 16, count 2 2006.259.08:16:58.31#ibcon#about to read 6, iclass 16, count 2 2006.259.08:16:58.31#ibcon#read 6, iclass 16, count 2 2006.259.08:16:58.31#ibcon#end of sib2, iclass 16, count 2 2006.259.08:16:58.31#ibcon#*after write, iclass 16, count 2 2006.259.08:16:58.31#ibcon#*before return 0, iclass 16, count 2 2006.259.08:16:58.31#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.259.08:16:58.31#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.259.08:16:58.31#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.259.08:16:58.31#ibcon#ireg 7 cls_cnt 0 2006.259.08:16:58.31#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.259.08:16:58.43#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.259.08:16:58.43#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.259.08:16:58.43#ibcon#enter wrdev, iclass 16, count 0 2006.259.08:16:58.43#ibcon#first serial, iclass 16, count 0 2006.259.08:16:58.43#ibcon#enter sib2, iclass 16, count 0 2006.259.08:16:58.43#ibcon#flushed, iclass 16, count 0 2006.259.08:16:58.43#ibcon#about to write, iclass 16, count 0 2006.259.08:16:58.43#ibcon#wrote, iclass 16, count 0 2006.259.08:16:58.43#ibcon#about to read 3, iclass 16, count 0 2006.259.08:16:58.45#ibcon#read 3, iclass 16, count 0 2006.259.08:16:58.45#ibcon#about to read 4, iclass 16, count 0 2006.259.08:16:58.45#ibcon#read 4, iclass 16, count 0 2006.259.08:16:58.45#ibcon#about to read 5, iclass 16, count 0 2006.259.08:16:58.45#ibcon#read 5, iclass 16, count 0 2006.259.08:16:58.45#ibcon#about to read 6, iclass 16, count 0 2006.259.08:16:58.45#ibcon#read 6, iclass 16, count 0 2006.259.08:16:58.45#ibcon#end of sib2, iclass 16, count 0 2006.259.08:16:58.45#ibcon#*mode == 0, iclass 16, count 0 2006.259.08:16:58.45#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.259.08:16:58.45#ibcon#[27=USB\r\n] 2006.259.08:16:58.45#ibcon#*before write, iclass 16, count 0 2006.259.08:16:58.45#ibcon#enter sib2, iclass 16, count 0 2006.259.08:16:58.45#ibcon#flushed, iclass 16, count 0 2006.259.08:16:58.45#ibcon#about to write, iclass 16, count 0 2006.259.08:16:58.45#ibcon#wrote, iclass 16, count 0 2006.259.08:16:58.45#ibcon#about to read 3, iclass 16, count 0 2006.259.08:16:58.48#ibcon#read 3, iclass 16, count 0 2006.259.08:16:58.48#ibcon#about to read 4, iclass 16, count 0 2006.259.08:16:58.48#ibcon#read 4, iclass 16, count 0 2006.259.08:16:58.48#ibcon#about to read 5, iclass 16, count 0 2006.259.08:16:58.48#ibcon#read 5, iclass 16, count 0 2006.259.08:16:58.48#ibcon#about to read 6, iclass 16, count 0 2006.259.08:16:58.48#ibcon#read 6, iclass 16, count 0 2006.259.08:16:58.48#ibcon#end of sib2, iclass 16, count 0 2006.259.08:16:58.48#ibcon#*after write, iclass 16, count 0 2006.259.08:16:58.48#ibcon#*before return 0, iclass 16, count 0 2006.259.08:16:58.48#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.259.08:16:58.48#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.259.08:16:58.48#ibcon#about to clear, iclass 16 cls_cnt 0 2006.259.08:16:58.48#ibcon#cleared, iclass 16 cls_cnt 0 2006.259.08:16:58.48$vc4f8/vabw=wide 2006.259.08:16:58.48#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.259.08:16:58.48#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.259.08:16:58.48#ibcon#ireg 8 cls_cnt 0 2006.259.08:16:58.48#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.259.08:16:58.48#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.259.08:16:58.48#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.259.08:16:58.48#ibcon#enter wrdev, iclass 18, count 0 2006.259.08:16:58.48#ibcon#first serial, iclass 18, count 0 2006.259.08:16:58.48#ibcon#enter sib2, iclass 18, count 0 2006.259.08:16:58.48#ibcon#flushed, iclass 18, count 0 2006.259.08:16:58.48#ibcon#about to write, iclass 18, count 0 2006.259.08:16:58.48#ibcon#wrote, iclass 18, count 0 2006.259.08:16:58.48#ibcon#about to read 3, iclass 18, count 0 2006.259.08:16:58.50#ibcon#read 3, iclass 18, count 0 2006.259.08:16:58.50#ibcon#about to read 4, iclass 18, count 0 2006.259.08:16:58.50#ibcon#read 4, iclass 18, count 0 2006.259.08:16:58.50#ibcon#about to read 5, iclass 18, count 0 2006.259.08:16:58.50#ibcon#read 5, iclass 18, count 0 2006.259.08:16:58.50#ibcon#about to read 6, iclass 18, count 0 2006.259.08:16:58.50#ibcon#read 6, iclass 18, count 0 2006.259.08:16:58.50#ibcon#end of sib2, iclass 18, count 0 2006.259.08:16:58.50#ibcon#*mode == 0, iclass 18, count 0 2006.259.08:16:58.50#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.259.08:16:58.50#ibcon#[25=BW32\r\n] 2006.259.08:16:58.50#ibcon#*before write, iclass 18, count 0 2006.259.08:16:58.50#ibcon#enter sib2, iclass 18, count 0 2006.259.08:16:58.50#ibcon#flushed, iclass 18, count 0 2006.259.08:16:58.50#ibcon#about to write, iclass 18, count 0 2006.259.08:16:58.50#ibcon#wrote, iclass 18, count 0 2006.259.08:16:58.50#ibcon#about to read 3, iclass 18, count 0 2006.259.08:16:58.53#ibcon#read 3, iclass 18, count 0 2006.259.08:16:58.53#ibcon#about to read 4, iclass 18, count 0 2006.259.08:16:58.53#ibcon#read 4, iclass 18, count 0 2006.259.08:16:58.53#ibcon#about to read 5, iclass 18, count 0 2006.259.08:16:58.53#ibcon#read 5, iclass 18, count 0 2006.259.08:16:58.53#ibcon#about to read 6, iclass 18, count 0 2006.259.08:16:58.53#ibcon#read 6, iclass 18, count 0 2006.259.08:16:58.53#ibcon#end of sib2, iclass 18, count 0 2006.259.08:16:58.53#ibcon#*after write, iclass 18, count 0 2006.259.08:16:58.53#ibcon#*before return 0, iclass 18, count 0 2006.259.08:16:58.53#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.259.08:16:58.53#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.259.08:16:58.53#ibcon#about to clear, iclass 18 cls_cnt 0 2006.259.08:16:58.53#ibcon#cleared, iclass 18 cls_cnt 0 2006.259.08:16:58.53$vc4f8/vbbw=wide 2006.259.08:16:58.53#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.259.08:16:58.53#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.259.08:16:58.53#ibcon#ireg 8 cls_cnt 0 2006.259.08:16:58.53#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.259.08:16:58.60#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.259.08:16:58.60#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.259.08:16:58.60#ibcon#enter wrdev, iclass 20, count 0 2006.259.08:16:58.60#ibcon#first serial, iclass 20, count 0 2006.259.08:16:58.60#ibcon#enter sib2, iclass 20, count 0 2006.259.08:16:58.60#ibcon#flushed, iclass 20, count 0 2006.259.08:16:58.60#ibcon#about to write, iclass 20, count 0 2006.259.08:16:58.60#ibcon#wrote, iclass 20, count 0 2006.259.08:16:58.60#ibcon#about to read 3, iclass 20, count 0 2006.259.08:16:58.62#ibcon#read 3, iclass 20, count 0 2006.259.08:16:58.62#ibcon#about to read 4, iclass 20, count 0 2006.259.08:16:58.62#ibcon#read 4, iclass 20, count 0 2006.259.08:16:58.62#ibcon#about to read 5, iclass 20, count 0 2006.259.08:16:58.62#ibcon#read 5, iclass 20, count 0 2006.259.08:16:58.62#ibcon#about to read 6, iclass 20, count 0 2006.259.08:16:58.62#ibcon#read 6, iclass 20, count 0 2006.259.08:16:58.62#ibcon#end of sib2, iclass 20, count 0 2006.259.08:16:58.62#ibcon#*mode == 0, iclass 20, count 0 2006.259.08:16:58.62#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.259.08:16:58.62#ibcon#[27=BW32\r\n] 2006.259.08:16:58.62#ibcon#*before write, iclass 20, count 0 2006.259.08:16:58.62#ibcon#enter sib2, iclass 20, count 0 2006.259.08:16:58.62#ibcon#flushed, iclass 20, count 0 2006.259.08:16:58.62#ibcon#about to write, iclass 20, count 0 2006.259.08:16:58.62#ibcon#wrote, iclass 20, count 0 2006.259.08:16:58.62#ibcon#about to read 3, iclass 20, count 0 2006.259.08:16:58.65#ibcon#read 3, iclass 20, count 0 2006.259.08:16:58.65#ibcon#about to read 4, iclass 20, count 0 2006.259.08:16:58.65#ibcon#read 4, iclass 20, count 0 2006.259.08:16:58.65#ibcon#about to read 5, iclass 20, count 0 2006.259.08:16:58.65#ibcon#read 5, iclass 20, count 0 2006.259.08:16:58.65#ibcon#about to read 6, iclass 20, count 0 2006.259.08:16:58.65#ibcon#read 6, iclass 20, count 0 2006.259.08:16:58.65#ibcon#end of sib2, iclass 20, count 0 2006.259.08:16:58.65#ibcon#*after write, iclass 20, count 0 2006.259.08:16:58.65#ibcon#*before return 0, iclass 20, count 0 2006.259.08:16:58.65#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.259.08:16:58.65#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.259.08:16:58.65#ibcon#about to clear, iclass 20 cls_cnt 0 2006.259.08:16:58.65#ibcon#cleared, iclass 20 cls_cnt 0 2006.259.08:16:58.65$4f8m12a/ifd4f 2006.259.08:16:58.65$ifd4f/lo= 2006.259.08:16:58.65$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.259.08:16:58.65$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.259.08:16:58.65$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.259.08:16:58.65$ifd4f/patch= 2006.259.08:16:58.65$ifd4f/patch=lo1,a1,a2,a3,a4 2006.259.08:16:58.65$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.259.08:16:58.65$ifd4f/patch=lo3,a5,a6,a7,a8 2006.259.08:16:58.65$4f8m12a/"form=m,16.000,1:2 2006.259.08:16:58.65$4f8m12a/"tpicd 2006.259.08:16:58.65$4f8m12a/echo=off 2006.259.08:16:58.65$4f8m12a/xlog=off 2006.259.08:16:58.65:!2006.259.08:17:30 2006.259.08:17:14.14#trakl#Source acquired 2006.259.08:17:14.14#flagr#flagr/antenna,acquired 2006.259.08:17:30.00:preob 2006.259.08:17:30.14/onsource/TRACKING 2006.259.08:17:30.14:!2006.259.08:17:40 2006.259.08:17:40.00:data_valid=on 2006.259.08:17:40.00:midob 2006.259.08:17:41.14/onsource/TRACKING 2006.259.08:17:41.14/wx/21.87,1013.1,86 2006.259.08:17:41.29/cable/+6.4590E-03 2006.259.08:17:42.38/va/01,08,usb,yes,31,32 2006.259.08:17:42.38/va/02,07,usb,yes,30,32 2006.259.08:17:42.38/va/03,08,usb,yes,23,23 2006.259.08:17:42.38/va/04,07,usb,yes,32,34 2006.259.08:17:42.38/va/05,07,usb,yes,35,37 2006.259.08:17:42.38/va/06,06,usb,yes,34,34 2006.259.08:17:42.38/va/07,06,usb,yes,35,35 2006.259.08:17:42.38/va/08,06,usb,yes,37,37 2006.259.08:17:42.61/valo/01,532.99,yes,locked 2006.259.08:17:42.61/valo/02,572.99,yes,locked 2006.259.08:17:42.61/valo/03,672.99,yes,locked 2006.259.08:17:42.61/valo/04,832.99,yes,locked 2006.259.08:17:42.61/valo/05,652.99,yes,locked 2006.259.08:17:42.61/valo/06,772.99,yes,locked 2006.259.08:17:42.61/valo/07,832.99,yes,locked 2006.259.08:17:42.61/valo/08,852.99,yes,locked 2006.259.08:17:43.70/vb/01,04,usb,yes,30,29 2006.259.08:17:43.70/vb/02,05,usb,yes,28,29 2006.259.08:17:43.70/vb/03,04,usb,yes,28,32 2006.259.08:17:43.70/vb/04,05,usb,yes,26,26 2006.259.08:17:43.70/vb/05,04,usb,yes,27,32 2006.259.08:17:43.70/vb/06,04,usb,yes,28,31 2006.259.08:17:43.70/vb/07,04,usb,yes,31,31 2006.259.08:17:43.70/vb/08,04,usb,yes,28,32 2006.259.08:17:43.93/vblo/01,632.99,yes,locked 2006.259.08:17:43.93/vblo/02,640.99,yes,locked 2006.259.08:17:43.93/vblo/03,656.99,yes,locked 2006.259.08:17:43.93/vblo/04,712.99,yes,locked 2006.259.08:17:43.93/vblo/05,744.99,yes,locked 2006.259.08:17:43.93/vblo/06,752.99,yes,locked 2006.259.08:17:43.93/vblo/07,734.99,yes,locked 2006.259.08:17:43.93/vblo/08,744.99,yes,locked 2006.259.08:17:44.08/vabw/8 2006.259.08:17:44.23/vbbw/8 2006.259.08:17:44.34/xfe/off,on,15.2 2006.259.08:17:44.73/ifatt/23,28,28,28 2006.259.08:17:45.07/fmout-gps/S +4.61E-07 2006.259.08:17:45.11:!2006.259.08:18:40 2006.259.08:18:40.00:data_valid=off 2006.259.08:18:40.00:postob 2006.259.08:18:40.23/cable/+6.4615E-03 2006.259.08:18:40.23/wx/21.84,1013.2,85 2006.259.08:18:41.08/fmout-gps/S +4.60E-07 2006.259.08:18:41.08:scan_name=259-0820,k06259,80 2006.259.08:18:41.09:source=1307+121,130933.93,115424.6,2000.0,ccw 2006.259.08:18:41.14#flagr#flagr/antenna,new-source 2006.259.08:18:42.14:checkk5 2006.259.08:18:42.55/chk_autoobs//k5ts1/ autoobs is running! 2006.259.08:18:43.05/chk_autoobs//k5ts2/ autoobs is running! 2006.259.08:18:43.51/chk_autoobs//k5ts3/ autoobs is running! 2006.259.08:18:43.88/chk_autoobs//k5ts4/ autoobs is running! 2006.259.08:18:44.32/chk_obsdata//k5ts1/T2590817??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.259.08:18:44.75/chk_obsdata//k5ts2/T2590817??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.259.08:18:45.44/chk_obsdata//k5ts3/T2590817??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.259.08:18:45.91/chk_obsdata//k5ts4/T2590817??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.259.08:18:47.01/k5log//k5ts1_log_newline 2006.259.08:18:48.28/k5log//k5ts2_log_newline 2006.259.08:18:49.21/k5log//k5ts3_log_newline 2006.259.08:18:50.02/k5log//k5ts4_log_newline 2006.259.08:18:50.04/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.259.08:18:50.04:4f8m12a=3 2006.259.08:18:50.04$4f8m12a/echo=on 2006.259.08:18:50.04$4f8m12a/pcalon 2006.259.08:18:50.04$pcalon/"no phase cal control is implemented here 2006.259.08:18:50.04$4f8m12a/"tpicd=stop 2006.259.08:18:50.04$4f8m12a/vc4f8 2006.259.08:18:50.04$vc4f8/valo=1,532.99 2006.259.08:18:50.04#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.259.08:18:50.04#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.259.08:18:50.04#ibcon#ireg 17 cls_cnt 0 2006.259.08:18:50.04#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.259.08:18:50.04#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.259.08:18:50.04#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.259.08:18:50.04#ibcon#enter wrdev, iclass 31, count 0 2006.259.08:18:50.04#ibcon#first serial, iclass 31, count 0 2006.259.08:18:50.04#ibcon#enter sib2, iclass 31, count 0 2006.259.08:18:50.04#ibcon#flushed, iclass 31, count 0 2006.259.08:18:50.04#ibcon#about to write, iclass 31, count 0 2006.259.08:18:50.04#ibcon#wrote, iclass 31, count 0 2006.259.08:18:50.04#ibcon#about to read 3, iclass 31, count 0 2006.259.08:18:50.08#ibcon#read 3, iclass 31, count 0 2006.259.08:18:50.08#ibcon#about to read 4, iclass 31, count 0 2006.259.08:18:50.08#ibcon#read 4, iclass 31, count 0 2006.259.08:18:50.08#ibcon#about to read 5, iclass 31, count 0 2006.259.08:18:50.08#ibcon#read 5, iclass 31, count 0 2006.259.08:18:50.08#ibcon#about to read 6, iclass 31, count 0 2006.259.08:18:50.08#ibcon#read 6, iclass 31, count 0 2006.259.08:18:50.08#ibcon#end of sib2, iclass 31, count 0 2006.259.08:18:50.08#ibcon#*mode == 0, iclass 31, count 0 2006.259.08:18:50.08#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.259.08:18:50.08#ibcon#[26=FRQ=01,532.99\r\n] 2006.259.08:18:50.08#ibcon#*before write, iclass 31, count 0 2006.259.08:18:50.08#ibcon#enter sib2, iclass 31, count 0 2006.259.08:18:50.08#ibcon#flushed, iclass 31, count 0 2006.259.08:18:50.08#ibcon#about to write, iclass 31, count 0 2006.259.08:18:50.08#ibcon#wrote, iclass 31, count 0 2006.259.08:18:50.08#ibcon#about to read 3, iclass 31, count 0 2006.259.08:18:50.13#ibcon#read 3, iclass 31, count 0 2006.259.08:18:50.13#ibcon#about to read 4, iclass 31, count 0 2006.259.08:18:50.13#ibcon#read 4, iclass 31, count 0 2006.259.08:18:50.13#ibcon#about to read 5, iclass 31, count 0 2006.259.08:18:50.13#ibcon#read 5, iclass 31, count 0 2006.259.08:18:50.13#ibcon#about to read 6, iclass 31, count 0 2006.259.08:18:50.13#ibcon#read 6, iclass 31, count 0 2006.259.08:18:50.13#ibcon#end of sib2, iclass 31, count 0 2006.259.08:18:50.13#ibcon#*after write, iclass 31, count 0 2006.259.08:18:50.13#ibcon#*before return 0, iclass 31, count 0 2006.259.08:18:50.13#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.259.08:18:50.13#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.259.08:18:50.13#ibcon#about to clear, iclass 31 cls_cnt 0 2006.259.08:18:50.13#ibcon#cleared, iclass 31 cls_cnt 0 2006.259.08:18:50.13$vc4f8/va=1,8 2006.259.08:18:50.13#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.259.08:18:50.13#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.259.08:18:50.13#ibcon#ireg 11 cls_cnt 2 2006.259.08:18:50.13#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.259.08:18:50.13#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.259.08:18:50.13#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.259.08:18:50.13#ibcon#enter wrdev, iclass 33, count 2 2006.259.08:18:50.13#ibcon#first serial, iclass 33, count 2 2006.259.08:18:50.13#ibcon#enter sib2, iclass 33, count 2 2006.259.08:18:50.13#ibcon#flushed, iclass 33, count 2 2006.259.08:18:50.13#ibcon#about to write, iclass 33, count 2 2006.259.08:18:50.13#ibcon#wrote, iclass 33, count 2 2006.259.08:18:50.13#ibcon#about to read 3, iclass 33, count 2 2006.259.08:18:50.15#ibcon#read 3, iclass 33, count 2 2006.259.08:18:50.15#ibcon#about to read 4, iclass 33, count 2 2006.259.08:18:50.15#ibcon#read 4, iclass 33, count 2 2006.259.08:18:50.15#ibcon#about to read 5, iclass 33, count 2 2006.259.08:18:50.15#ibcon#read 5, iclass 33, count 2 2006.259.08:18:50.15#ibcon#about to read 6, iclass 33, count 2 2006.259.08:18:50.15#ibcon#read 6, iclass 33, count 2 2006.259.08:18:50.15#ibcon#end of sib2, iclass 33, count 2 2006.259.08:18:50.15#ibcon#*mode == 0, iclass 33, count 2 2006.259.08:18:50.15#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.259.08:18:50.15#ibcon#[25=AT01-08\r\n] 2006.259.08:18:50.15#ibcon#*before write, iclass 33, count 2 2006.259.08:18:50.15#ibcon#enter sib2, iclass 33, count 2 2006.259.08:18:50.15#ibcon#flushed, iclass 33, count 2 2006.259.08:18:50.15#ibcon#about to write, iclass 33, count 2 2006.259.08:18:50.15#ibcon#wrote, iclass 33, count 2 2006.259.08:18:50.15#ibcon#about to read 3, iclass 33, count 2 2006.259.08:18:50.19#ibcon#read 3, iclass 33, count 2 2006.259.08:18:50.19#ibcon#about to read 4, iclass 33, count 2 2006.259.08:18:50.19#ibcon#read 4, iclass 33, count 2 2006.259.08:18:50.19#ibcon#about to read 5, iclass 33, count 2 2006.259.08:18:50.19#ibcon#read 5, iclass 33, count 2 2006.259.08:18:50.19#ibcon#about to read 6, iclass 33, count 2 2006.259.08:18:50.19#ibcon#read 6, iclass 33, count 2 2006.259.08:18:50.19#ibcon#end of sib2, iclass 33, count 2 2006.259.08:18:50.19#ibcon#*after write, iclass 33, count 2 2006.259.08:18:50.19#ibcon#*before return 0, iclass 33, count 2 2006.259.08:18:50.19#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.259.08:18:50.19#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.259.08:18:50.19#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.259.08:18:50.19#ibcon#ireg 7 cls_cnt 0 2006.259.08:18:50.19#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.259.08:18:50.31#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.259.08:18:50.31#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.259.08:18:50.31#ibcon#enter wrdev, iclass 33, count 0 2006.259.08:18:50.31#ibcon#first serial, iclass 33, count 0 2006.259.08:18:50.31#ibcon#enter sib2, iclass 33, count 0 2006.259.08:18:50.31#ibcon#flushed, iclass 33, count 0 2006.259.08:18:50.31#ibcon#about to write, iclass 33, count 0 2006.259.08:18:50.31#ibcon#wrote, iclass 33, count 0 2006.259.08:18:50.31#ibcon#about to read 3, iclass 33, count 0 2006.259.08:18:50.33#ibcon#read 3, iclass 33, count 0 2006.259.08:18:50.33#ibcon#about to read 4, iclass 33, count 0 2006.259.08:18:50.33#ibcon#read 4, iclass 33, count 0 2006.259.08:18:50.33#ibcon#about to read 5, iclass 33, count 0 2006.259.08:18:50.33#ibcon#read 5, iclass 33, count 0 2006.259.08:18:50.33#ibcon#about to read 6, iclass 33, count 0 2006.259.08:18:50.33#ibcon#read 6, iclass 33, count 0 2006.259.08:18:50.33#ibcon#end of sib2, iclass 33, count 0 2006.259.08:18:50.33#ibcon#*mode == 0, iclass 33, count 0 2006.259.08:18:50.33#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.259.08:18:50.33#ibcon#[25=USB\r\n] 2006.259.08:18:50.33#ibcon#*before write, iclass 33, count 0 2006.259.08:18:50.33#ibcon#enter sib2, iclass 33, count 0 2006.259.08:18:50.33#ibcon#flushed, iclass 33, count 0 2006.259.08:18:50.33#ibcon#about to write, iclass 33, count 0 2006.259.08:18:50.33#ibcon#wrote, iclass 33, count 0 2006.259.08:18:50.33#ibcon#about to read 3, iclass 33, count 0 2006.259.08:18:50.36#ibcon#read 3, iclass 33, count 0 2006.259.08:18:50.36#ibcon#about to read 4, iclass 33, count 0 2006.259.08:18:50.36#ibcon#read 4, iclass 33, count 0 2006.259.08:18:50.36#ibcon#about to read 5, iclass 33, count 0 2006.259.08:18:50.36#ibcon#read 5, iclass 33, count 0 2006.259.08:18:50.36#ibcon#about to read 6, iclass 33, count 0 2006.259.08:18:50.36#ibcon#read 6, iclass 33, count 0 2006.259.08:18:50.36#ibcon#end of sib2, iclass 33, count 0 2006.259.08:18:50.36#ibcon#*after write, iclass 33, count 0 2006.259.08:18:50.36#ibcon#*before return 0, iclass 33, count 0 2006.259.08:18:50.36#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.259.08:18:50.36#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.259.08:18:50.36#ibcon#about to clear, iclass 33 cls_cnt 0 2006.259.08:18:50.36#ibcon#cleared, iclass 33 cls_cnt 0 2006.259.08:18:50.36$vc4f8/valo=2,572.99 2006.259.08:18:50.36#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.259.08:18:50.36#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.259.08:18:50.36#ibcon#ireg 17 cls_cnt 0 2006.259.08:18:50.36#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.259.08:18:50.36#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.259.08:18:50.36#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.259.08:18:50.36#ibcon#enter wrdev, iclass 35, count 0 2006.259.08:18:50.36#ibcon#first serial, iclass 35, count 0 2006.259.08:18:50.36#ibcon#enter sib2, iclass 35, count 0 2006.259.08:18:50.36#ibcon#flushed, iclass 35, count 0 2006.259.08:18:50.36#ibcon#about to write, iclass 35, count 0 2006.259.08:18:50.36#ibcon#wrote, iclass 35, count 0 2006.259.08:18:50.36#ibcon#about to read 3, iclass 35, count 0 2006.259.08:18:50.38#ibcon#read 3, iclass 35, count 0 2006.259.08:18:50.38#ibcon#about to read 4, iclass 35, count 0 2006.259.08:18:50.38#ibcon#read 4, iclass 35, count 0 2006.259.08:18:50.38#ibcon#about to read 5, iclass 35, count 0 2006.259.08:18:50.38#ibcon#read 5, iclass 35, count 0 2006.259.08:18:50.38#ibcon#about to read 6, iclass 35, count 0 2006.259.08:18:50.38#ibcon#read 6, iclass 35, count 0 2006.259.08:18:50.38#ibcon#end of sib2, iclass 35, count 0 2006.259.08:18:50.38#ibcon#*mode == 0, iclass 35, count 0 2006.259.08:18:50.38#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.259.08:18:50.38#ibcon#[26=FRQ=02,572.99\r\n] 2006.259.08:18:50.38#ibcon#*before write, iclass 35, count 0 2006.259.08:18:50.38#ibcon#enter sib2, iclass 35, count 0 2006.259.08:18:50.38#ibcon#flushed, iclass 35, count 0 2006.259.08:18:50.38#ibcon#about to write, iclass 35, count 0 2006.259.08:18:50.38#ibcon#wrote, iclass 35, count 0 2006.259.08:18:50.38#ibcon#about to read 3, iclass 35, count 0 2006.259.08:18:50.42#ibcon#read 3, iclass 35, count 0 2006.259.08:18:50.42#ibcon#about to read 4, iclass 35, count 0 2006.259.08:18:50.42#ibcon#read 4, iclass 35, count 0 2006.259.08:18:50.42#ibcon#about to read 5, iclass 35, count 0 2006.259.08:18:50.42#ibcon#read 5, iclass 35, count 0 2006.259.08:18:50.42#ibcon#about to read 6, iclass 35, count 0 2006.259.08:18:50.42#ibcon#read 6, iclass 35, count 0 2006.259.08:18:50.42#ibcon#end of sib2, iclass 35, count 0 2006.259.08:18:50.42#ibcon#*after write, iclass 35, count 0 2006.259.08:18:50.42#ibcon#*before return 0, iclass 35, count 0 2006.259.08:18:50.42#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.259.08:18:50.42#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.259.08:18:50.42#ibcon#about to clear, iclass 35 cls_cnt 0 2006.259.08:18:50.42#ibcon#cleared, iclass 35 cls_cnt 0 2006.259.08:18:50.42$vc4f8/va=2,7 2006.259.08:18:50.42#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.259.08:18:50.42#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.259.08:18:50.42#ibcon#ireg 11 cls_cnt 2 2006.259.08:18:50.42#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.259.08:18:50.48#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.259.08:18:50.48#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.259.08:18:50.48#ibcon#enter wrdev, iclass 37, count 2 2006.259.08:18:50.48#ibcon#first serial, iclass 37, count 2 2006.259.08:18:50.48#ibcon#enter sib2, iclass 37, count 2 2006.259.08:18:50.48#ibcon#flushed, iclass 37, count 2 2006.259.08:18:50.48#ibcon#about to write, iclass 37, count 2 2006.259.08:18:50.48#ibcon#wrote, iclass 37, count 2 2006.259.08:18:50.48#ibcon#about to read 3, iclass 37, count 2 2006.259.08:18:50.50#ibcon#read 3, iclass 37, count 2 2006.259.08:18:50.50#ibcon#about to read 4, iclass 37, count 2 2006.259.08:18:50.50#ibcon#read 4, iclass 37, count 2 2006.259.08:18:50.50#ibcon#about to read 5, iclass 37, count 2 2006.259.08:18:50.50#ibcon#read 5, iclass 37, count 2 2006.259.08:18:50.50#ibcon#about to read 6, iclass 37, count 2 2006.259.08:18:50.50#ibcon#read 6, iclass 37, count 2 2006.259.08:18:50.50#ibcon#end of sib2, iclass 37, count 2 2006.259.08:18:50.51#ibcon#*mode == 0, iclass 37, count 2 2006.259.08:18:50.51#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.259.08:18:50.51#ibcon#[25=AT02-07\r\n] 2006.259.08:18:50.51#ibcon#*before write, iclass 37, count 2 2006.259.08:18:50.51#ibcon#enter sib2, iclass 37, count 2 2006.259.08:18:50.51#ibcon#flushed, iclass 37, count 2 2006.259.08:18:50.51#ibcon#about to write, iclass 37, count 2 2006.259.08:18:50.51#ibcon#wrote, iclass 37, count 2 2006.259.08:18:50.51#ibcon#about to read 3, iclass 37, count 2 2006.259.08:18:50.54#ibcon#read 3, iclass 37, count 2 2006.259.08:18:50.54#ibcon#about to read 4, iclass 37, count 2 2006.259.08:18:50.54#ibcon#read 4, iclass 37, count 2 2006.259.08:18:50.54#ibcon#about to read 5, iclass 37, count 2 2006.259.08:18:50.54#ibcon#read 5, iclass 37, count 2 2006.259.08:18:50.54#ibcon#about to read 6, iclass 37, count 2 2006.259.08:18:50.54#ibcon#read 6, iclass 37, count 2 2006.259.08:18:50.54#ibcon#end of sib2, iclass 37, count 2 2006.259.08:18:50.54#ibcon#*after write, iclass 37, count 2 2006.259.08:18:50.54#ibcon#*before return 0, iclass 37, count 2 2006.259.08:18:50.54#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.259.08:18:50.54#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.259.08:18:50.54#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.259.08:18:50.54#ibcon#ireg 7 cls_cnt 0 2006.259.08:18:50.54#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.259.08:18:50.66#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.259.08:18:50.66#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.259.08:18:50.66#ibcon#enter wrdev, iclass 37, count 0 2006.259.08:18:50.66#ibcon#first serial, iclass 37, count 0 2006.259.08:18:50.66#ibcon#enter sib2, iclass 37, count 0 2006.259.08:18:50.66#ibcon#flushed, iclass 37, count 0 2006.259.08:18:50.66#ibcon#about to write, iclass 37, count 0 2006.259.08:18:50.66#ibcon#wrote, iclass 37, count 0 2006.259.08:18:50.66#ibcon#about to read 3, iclass 37, count 0 2006.259.08:18:50.68#ibcon#read 3, iclass 37, count 0 2006.259.08:18:50.68#ibcon#about to read 4, iclass 37, count 0 2006.259.08:18:50.68#ibcon#read 4, iclass 37, count 0 2006.259.08:18:50.68#ibcon#about to read 5, iclass 37, count 0 2006.259.08:18:50.68#ibcon#read 5, iclass 37, count 0 2006.259.08:18:50.68#ibcon#about to read 6, iclass 37, count 0 2006.259.08:18:50.68#ibcon#read 6, iclass 37, count 0 2006.259.08:18:50.68#ibcon#end of sib2, iclass 37, count 0 2006.259.08:18:50.68#ibcon#*mode == 0, iclass 37, count 0 2006.259.08:18:50.68#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.259.08:18:50.68#ibcon#[25=USB\r\n] 2006.259.08:18:50.68#ibcon#*before write, iclass 37, count 0 2006.259.08:18:50.68#ibcon#enter sib2, iclass 37, count 0 2006.259.08:18:50.68#ibcon#flushed, iclass 37, count 0 2006.259.08:18:50.68#ibcon#about to write, iclass 37, count 0 2006.259.08:18:50.68#ibcon#wrote, iclass 37, count 0 2006.259.08:18:50.68#ibcon#about to read 3, iclass 37, count 0 2006.259.08:18:50.71#ibcon#read 3, iclass 37, count 0 2006.259.08:18:50.71#ibcon#about to read 4, iclass 37, count 0 2006.259.08:18:50.71#ibcon#read 4, iclass 37, count 0 2006.259.08:18:50.71#ibcon#about to read 5, iclass 37, count 0 2006.259.08:18:50.71#ibcon#read 5, iclass 37, count 0 2006.259.08:18:50.71#ibcon#about to read 6, iclass 37, count 0 2006.259.08:18:50.71#ibcon#read 6, iclass 37, count 0 2006.259.08:18:50.71#ibcon#end of sib2, iclass 37, count 0 2006.259.08:18:50.71#ibcon#*after write, iclass 37, count 0 2006.259.08:18:50.71#ibcon#*before return 0, iclass 37, count 0 2006.259.08:18:50.71#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.259.08:18:50.71#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.259.08:18:50.71#ibcon#about to clear, iclass 37 cls_cnt 0 2006.259.08:18:50.71#ibcon#cleared, iclass 37 cls_cnt 0 2006.259.08:18:50.71$vc4f8/valo=3,672.99 2006.259.08:18:50.71#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.259.08:18:50.71#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.259.08:18:50.71#ibcon#ireg 17 cls_cnt 0 2006.259.08:18:50.71#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.259.08:18:50.71#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.259.08:18:50.71#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.259.08:18:50.71#ibcon#enter wrdev, iclass 39, count 0 2006.259.08:18:50.71#ibcon#first serial, iclass 39, count 0 2006.259.08:18:50.71#ibcon#enter sib2, iclass 39, count 0 2006.259.08:18:50.71#ibcon#flushed, iclass 39, count 0 2006.259.08:18:50.71#ibcon#about to write, iclass 39, count 0 2006.259.08:18:50.71#ibcon#wrote, iclass 39, count 0 2006.259.08:18:50.71#ibcon#about to read 3, iclass 39, count 0 2006.259.08:18:50.73#ibcon#read 3, iclass 39, count 0 2006.259.08:18:50.73#ibcon#about to read 4, iclass 39, count 0 2006.259.08:18:50.73#ibcon#read 4, iclass 39, count 0 2006.259.08:18:50.73#ibcon#about to read 5, iclass 39, count 0 2006.259.08:18:50.73#ibcon#read 5, iclass 39, count 0 2006.259.08:18:50.73#ibcon#about to read 6, iclass 39, count 0 2006.259.08:18:50.73#ibcon#read 6, iclass 39, count 0 2006.259.08:18:50.73#ibcon#end of sib2, iclass 39, count 0 2006.259.08:18:50.73#ibcon#*mode == 0, iclass 39, count 0 2006.259.08:18:50.73#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.259.08:18:50.73#ibcon#[26=FRQ=03,672.99\r\n] 2006.259.08:18:50.73#ibcon#*before write, iclass 39, count 0 2006.259.08:18:50.73#ibcon#enter sib2, iclass 39, count 0 2006.259.08:18:50.73#ibcon#flushed, iclass 39, count 0 2006.259.08:18:50.73#ibcon#about to write, iclass 39, count 0 2006.259.08:18:50.73#ibcon#wrote, iclass 39, count 0 2006.259.08:18:50.73#ibcon#about to read 3, iclass 39, count 0 2006.259.08:18:50.77#ibcon#read 3, iclass 39, count 0 2006.259.08:18:50.77#ibcon#about to read 4, iclass 39, count 0 2006.259.08:18:50.77#ibcon#read 4, iclass 39, count 0 2006.259.08:18:50.77#ibcon#about to read 5, iclass 39, count 0 2006.259.08:18:50.77#ibcon#read 5, iclass 39, count 0 2006.259.08:18:50.77#ibcon#about to read 6, iclass 39, count 0 2006.259.08:18:50.77#ibcon#read 6, iclass 39, count 0 2006.259.08:18:50.77#ibcon#end of sib2, iclass 39, count 0 2006.259.08:18:50.77#ibcon#*after write, iclass 39, count 0 2006.259.08:18:50.77#ibcon#*before return 0, iclass 39, count 0 2006.259.08:18:50.77#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.259.08:18:50.77#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.259.08:18:50.77#ibcon#about to clear, iclass 39 cls_cnt 0 2006.259.08:18:50.77#ibcon#cleared, iclass 39 cls_cnt 0 2006.259.08:18:50.77$vc4f8/va=3,8 2006.259.08:18:50.77#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.259.08:18:50.77#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.259.08:18:50.77#ibcon#ireg 11 cls_cnt 2 2006.259.08:18:50.77#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.259.08:18:50.83#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.259.08:18:50.83#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.259.08:18:50.83#ibcon#enter wrdev, iclass 3, count 2 2006.259.08:18:50.83#ibcon#first serial, iclass 3, count 2 2006.259.08:18:50.83#ibcon#enter sib2, iclass 3, count 2 2006.259.08:18:50.83#ibcon#flushed, iclass 3, count 2 2006.259.08:18:50.83#ibcon#about to write, iclass 3, count 2 2006.259.08:18:50.83#ibcon#wrote, iclass 3, count 2 2006.259.08:18:50.83#ibcon#about to read 3, iclass 3, count 2 2006.259.08:18:50.85#ibcon#read 3, iclass 3, count 2 2006.259.08:18:50.85#ibcon#about to read 4, iclass 3, count 2 2006.259.08:18:50.85#ibcon#read 4, iclass 3, count 2 2006.259.08:18:50.85#ibcon#about to read 5, iclass 3, count 2 2006.259.08:18:50.86#ibcon#read 5, iclass 3, count 2 2006.259.08:18:50.86#ibcon#about to read 6, iclass 3, count 2 2006.259.08:18:50.86#ibcon#read 6, iclass 3, count 2 2006.259.08:18:50.86#ibcon#end of sib2, iclass 3, count 2 2006.259.08:18:50.86#ibcon#*mode == 0, iclass 3, count 2 2006.259.08:18:50.86#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.259.08:18:50.86#ibcon#[25=AT03-08\r\n] 2006.259.08:18:50.86#ibcon#*before write, iclass 3, count 2 2006.259.08:18:50.86#ibcon#enter sib2, iclass 3, count 2 2006.259.08:18:50.86#ibcon#flushed, iclass 3, count 2 2006.259.08:18:50.86#ibcon#about to write, iclass 3, count 2 2006.259.08:18:50.86#ibcon#wrote, iclass 3, count 2 2006.259.08:18:50.86#ibcon#about to read 3, iclass 3, count 2 2006.259.08:18:50.89#ibcon#read 3, iclass 3, count 2 2006.259.08:18:50.89#ibcon#about to read 4, iclass 3, count 2 2006.259.08:18:50.89#ibcon#read 4, iclass 3, count 2 2006.259.08:18:50.89#ibcon#about to read 5, iclass 3, count 2 2006.259.08:18:50.89#ibcon#read 5, iclass 3, count 2 2006.259.08:18:50.89#ibcon#about to read 6, iclass 3, count 2 2006.259.08:18:50.89#ibcon#read 6, iclass 3, count 2 2006.259.08:18:50.89#ibcon#end of sib2, iclass 3, count 2 2006.259.08:18:50.89#ibcon#*after write, iclass 3, count 2 2006.259.08:18:50.89#ibcon#*before return 0, iclass 3, count 2 2006.259.08:18:50.89#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.259.08:18:50.89#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.259.08:18:50.89#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.259.08:18:50.89#ibcon#ireg 7 cls_cnt 0 2006.259.08:18:50.89#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.259.08:18:51.01#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.259.08:18:51.01#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.259.08:18:51.01#ibcon#enter wrdev, iclass 3, count 0 2006.259.08:18:51.01#ibcon#first serial, iclass 3, count 0 2006.259.08:18:51.01#ibcon#enter sib2, iclass 3, count 0 2006.259.08:18:51.01#ibcon#flushed, iclass 3, count 0 2006.259.08:18:51.01#ibcon#about to write, iclass 3, count 0 2006.259.08:18:51.01#ibcon#wrote, iclass 3, count 0 2006.259.08:18:51.01#ibcon#about to read 3, iclass 3, count 0 2006.259.08:18:51.03#ibcon#read 3, iclass 3, count 0 2006.259.08:18:51.03#ibcon#about to read 4, iclass 3, count 0 2006.259.08:18:51.03#ibcon#read 4, iclass 3, count 0 2006.259.08:18:51.03#ibcon#about to read 5, iclass 3, count 0 2006.259.08:18:51.03#ibcon#read 5, iclass 3, count 0 2006.259.08:18:51.03#ibcon#about to read 6, iclass 3, count 0 2006.259.08:18:51.03#ibcon#read 6, iclass 3, count 0 2006.259.08:18:51.03#ibcon#end of sib2, iclass 3, count 0 2006.259.08:18:51.03#ibcon#*mode == 0, iclass 3, count 0 2006.259.08:18:51.03#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.259.08:18:51.03#ibcon#[25=USB\r\n] 2006.259.08:18:51.03#ibcon#*before write, iclass 3, count 0 2006.259.08:18:51.03#ibcon#enter sib2, iclass 3, count 0 2006.259.08:18:51.03#ibcon#flushed, iclass 3, count 0 2006.259.08:18:51.03#ibcon#about to write, iclass 3, count 0 2006.259.08:18:51.03#ibcon#wrote, iclass 3, count 0 2006.259.08:18:51.03#ibcon#about to read 3, iclass 3, count 0 2006.259.08:18:51.06#ibcon#read 3, iclass 3, count 0 2006.259.08:18:51.06#ibcon#about to read 4, iclass 3, count 0 2006.259.08:18:51.06#ibcon#read 4, iclass 3, count 0 2006.259.08:18:51.06#ibcon#about to read 5, iclass 3, count 0 2006.259.08:18:51.06#ibcon#read 5, iclass 3, count 0 2006.259.08:18:51.06#ibcon#about to read 6, iclass 3, count 0 2006.259.08:18:51.06#ibcon#read 6, iclass 3, count 0 2006.259.08:18:51.06#ibcon#end of sib2, iclass 3, count 0 2006.259.08:18:51.06#ibcon#*after write, iclass 3, count 0 2006.259.08:18:51.06#ibcon#*before return 0, iclass 3, count 0 2006.259.08:18:51.06#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.259.08:18:51.06#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.259.08:18:51.06#ibcon#about to clear, iclass 3 cls_cnt 0 2006.259.08:18:51.06#ibcon#cleared, iclass 3 cls_cnt 0 2006.259.08:18:51.06$vc4f8/valo=4,832.99 2006.259.08:18:51.06#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.259.08:18:51.06#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.259.08:18:51.06#ibcon#ireg 17 cls_cnt 0 2006.259.08:18:51.06#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.259.08:18:51.06#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.259.08:18:51.06#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.259.08:18:51.06#ibcon#enter wrdev, iclass 5, count 0 2006.259.08:18:51.06#ibcon#first serial, iclass 5, count 0 2006.259.08:18:51.06#ibcon#enter sib2, iclass 5, count 0 2006.259.08:18:51.06#ibcon#flushed, iclass 5, count 0 2006.259.08:18:51.06#ibcon#about to write, iclass 5, count 0 2006.259.08:18:51.06#ibcon#wrote, iclass 5, count 0 2006.259.08:18:51.06#ibcon#about to read 3, iclass 5, count 0 2006.259.08:18:51.08#ibcon#read 3, iclass 5, count 0 2006.259.08:18:51.08#ibcon#about to read 4, iclass 5, count 0 2006.259.08:18:51.08#ibcon#read 4, iclass 5, count 0 2006.259.08:18:51.08#ibcon#about to read 5, iclass 5, count 0 2006.259.08:18:51.08#ibcon#read 5, iclass 5, count 0 2006.259.08:18:51.08#ibcon#about to read 6, iclass 5, count 0 2006.259.08:18:51.08#ibcon#read 6, iclass 5, count 0 2006.259.08:18:51.08#ibcon#end of sib2, iclass 5, count 0 2006.259.08:18:51.08#ibcon#*mode == 0, iclass 5, count 0 2006.259.08:18:51.08#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.259.08:18:51.08#ibcon#[26=FRQ=04,832.99\r\n] 2006.259.08:18:51.08#ibcon#*before write, iclass 5, count 0 2006.259.08:18:51.08#ibcon#enter sib2, iclass 5, count 0 2006.259.08:18:51.08#ibcon#flushed, iclass 5, count 0 2006.259.08:18:51.08#ibcon#about to write, iclass 5, count 0 2006.259.08:18:51.08#ibcon#wrote, iclass 5, count 0 2006.259.08:18:51.08#ibcon#about to read 3, iclass 5, count 0 2006.259.08:18:51.12#ibcon#read 3, iclass 5, count 0 2006.259.08:18:51.12#ibcon#about to read 4, iclass 5, count 0 2006.259.08:18:51.12#ibcon#read 4, iclass 5, count 0 2006.259.08:18:51.12#ibcon#about to read 5, iclass 5, count 0 2006.259.08:18:51.12#ibcon#read 5, iclass 5, count 0 2006.259.08:18:51.12#ibcon#about to read 6, iclass 5, count 0 2006.259.08:18:51.12#ibcon#read 6, iclass 5, count 0 2006.259.08:18:51.12#ibcon#end of sib2, iclass 5, count 0 2006.259.08:18:51.12#ibcon#*after write, iclass 5, count 0 2006.259.08:18:51.12#ibcon#*before return 0, iclass 5, count 0 2006.259.08:18:51.12#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.259.08:18:51.12#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.259.08:18:51.12#ibcon#about to clear, iclass 5 cls_cnt 0 2006.259.08:18:51.12#ibcon#cleared, iclass 5 cls_cnt 0 2006.259.08:18:51.12$vc4f8/va=4,7 2006.259.08:18:51.12#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.259.08:18:51.12#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.259.08:18:51.12#ibcon#ireg 11 cls_cnt 2 2006.259.08:18:51.12#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.259.08:18:51.18#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.259.08:18:51.18#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.259.08:18:51.18#ibcon#enter wrdev, iclass 7, count 2 2006.259.08:18:51.18#ibcon#first serial, iclass 7, count 2 2006.259.08:18:51.18#ibcon#enter sib2, iclass 7, count 2 2006.259.08:18:51.18#ibcon#flushed, iclass 7, count 2 2006.259.08:18:51.18#ibcon#about to write, iclass 7, count 2 2006.259.08:18:51.18#ibcon#wrote, iclass 7, count 2 2006.259.08:18:51.18#ibcon#about to read 3, iclass 7, count 2 2006.259.08:18:51.20#ibcon#read 3, iclass 7, count 2 2006.259.08:18:51.20#ibcon#about to read 4, iclass 7, count 2 2006.259.08:18:51.20#ibcon#read 4, iclass 7, count 2 2006.259.08:18:51.20#ibcon#about to read 5, iclass 7, count 2 2006.259.08:18:51.20#ibcon#read 5, iclass 7, count 2 2006.259.08:18:51.20#ibcon#about to read 6, iclass 7, count 2 2006.259.08:18:51.20#ibcon#read 6, iclass 7, count 2 2006.259.08:18:51.20#ibcon#end of sib2, iclass 7, count 2 2006.259.08:18:51.20#ibcon#*mode == 0, iclass 7, count 2 2006.259.08:18:51.20#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.259.08:18:51.20#ibcon#[25=AT04-07\r\n] 2006.259.08:18:51.20#ibcon#*before write, iclass 7, count 2 2006.259.08:18:51.20#ibcon#enter sib2, iclass 7, count 2 2006.259.08:18:51.20#ibcon#flushed, iclass 7, count 2 2006.259.08:18:51.20#ibcon#about to write, iclass 7, count 2 2006.259.08:18:51.20#ibcon#wrote, iclass 7, count 2 2006.259.08:18:51.20#ibcon#about to read 3, iclass 7, count 2 2006.259.08:18:51.23#ibcon#read 3, iclass 7, count 2 2006.259.08:18:51.23#ibcon#about to read 4, iclass 7, count 2 2006.259.08:18:51.23#ibcon#read 4, iclass 7, count 2 2006.259.08:18:51.23#ibcon#about to read 5, iclass 7, count 2 2006.259.08:18:51.23#ibcon#read 5, iclass 7, count 2 2006.259.08:18:51.23#ibcon#about to read 6, iclass 7, count 2 2006.259.08:18:51.23#ibcon#read 6, iclass 7, count 2 2006.259.08:18:51.23#ibcon#end of sib2, iclass 7, count 2 2006.259.08:18:51.23#ibcon#*after write, iclass 7, count 2 2006.259.08:18:51.23#ibcon#*before return 0, iclass 7, count 2 2006.259.08:18:51.23#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.259.08:18:51.23#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.259.08:18:51.23#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.259.08:18:51.23#ibcon#ireg 7 cls_cnt 0 2006.259.08:18:51.23#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.259.08:18:51.35#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.259.08:18:51.35#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.259.08:18:51.35#ibcon#enter wrdev, iclass 7, count 0 2006.259.08:18:51.35#ibcon#first serial, iclass 7, count 0 2006.259.08:18:51.35#ibcon#enter sib2, iclass 7, count 0 2006.259.08:18:51.35#ibcon#flushed, iclass 7, count 0 2006.259.08:18:51.35#ibcon#about to write, iclass 7, count 0 2006.259.08:18:51.35#ibcon#wrote, iclass 7, count 0 2006.259.08:18:51.35#ibcon#about to read 3, iclass 7, count 0 2006.259.08:18:51.37#ibcon#read 3, iclass 7, count 0 2006.259.08:18:51.37#ibcon#about to read 4, iclass 7, count 0 2006.259.08:18:51.37#ibcon#read 4, iclass 7, count 0 2006.259.08:18:51.37#ibcon#about to read 5, iclass 7, count 0 2006.259.08:18:51.37#ibcon#read 5, iclass 7, count 0 2006.259.08:18:51.37#ibcon#about to read 6, iclass 7, count 0 2006.259.08:18:51.37#ibcon#read 6, iclass 7, count 0 2006.259.08:18:51.37#ibcon#end of sib2, iclass 7, count 0 2006.259.08:18:51.37#ibcon#*mode == 0, iclass 7, count 0 2006.259.08:18:51.37#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.259.08:18:51.37#ibcon#[25=USB\r\n] 2006.259.08:18:51.37#ibcon#*before write, iclass 7, count 0 2006.259.08:18:51.37#ibcon#enter sib2, iclass 7, count 0 2006.259.08:18:51.37#ibcon#flushed, iclass 7, count 0 2006.259.08:18:51.37#ibcon#about to write, iclass 7, count 0 2006.259.08:18:51.37#ibcon#wrote, iclass 7, count 0 2006.259.08:18:51.37#ibcon#about to read 3, iclass 7, count 0 2006.259.08:18:51.40#ibcon#read 3, iclass 7, count 0 2006.259.08:18:51.40#ibcon#about to read 4, iclass 7, count 0 2006.259.08:18:51.40#ibcon#read 4, iclass 7, count 0 2006.259.08:18:51.40#ibcon#about to read 5, iclass 7, count 0 2006.259.08:18:51.40#ibcon#read 5, iclass 7, count 0 2006.259.08:18:51.40#ibcon#about to read 6, iclass 7, count 0 2006.259.08:18:51.40#ibcon#read 6, iclass 7, count 0 2006.259.08:18:51.40#ibcon#end of sib2, iclass 7, count 0 2006.259.08:18:51.40#ibcon#*after write, iclass 7, count 0 2006.259.08:18:51.40#ibcon#*before return 0, iclass 7, count 0 2006.259.08:18:51.40#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.259.08:18:51.40#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.259.08:18:51.40#ibcon#about to clear, iclass 7 cls_cnt 0 2006.259.08:18:51.40#ibcon#cleared, iclass 7 cls_cnt 0 2006.259.08:18:51.40$vc4f8/valo=5,652.99 2006.259.08:18:51.40#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.259.08:18:51.40#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.259.08:18:51.40#ibcon#ireg 17 cls_cnt 0 2006.259.08:18:51.40#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.259.08:18:51.40#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.259.08:18:51.40#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.259.08:18:51.40#ibcon#enter wrdev, iclass 11, count 0 2006.259.08:18:51.40#ibcon#first serial, iclass 11, count 0 2006.259.08:18:51.40#ibcon#enter sib2, iclass 11, count 0 2006.259.08:18:51.40#ibcon#flushed, iclass 11, count 0 2006.259.08:18:51.40#ibcon#about to write, iclass 11, count 0 2006.259.08:18:51.40#ibcon#wrote, iclass 11, count 0 2006.259.08:18:51.40#ibcon#about to read 3, iclass 11, count 0 2006.259.08:18:51.42#ibcon#read 3, iclass 11, count 0 2006.259.08:18:51.42#ibcon#about to read 4, iclass 11, count 0 2006.259.08:18:51.42#ibcon#read 4, iclass 11, count 0 2006.259.08:18:51.42#ibcon#about to read 5, iclass 11, count 0 2006.259.08:18:51.42#ibcon#read 5, iclass 11, count 0 2006.259.08:18:51.42#ibcon#about to read 6, iclass 11, count 0 2006.259.08:18:51.42#ibcon#read 6, iclass 11, count 0 2006.259.08:18:51.42#ibcon#end of sib2, iclass 11, count 0 2006.259.08:18:51.42#ibcon#*mode == 0, iclass 11, count 0 2006.259.08:18:51.42#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.259.08:18:51.42#ibcon#[26=FRQ=05,652.99\r\n] 2006.259.08:18:51.42#ibcon#*before write, iclass 11, count 0 2006.259.08:18:51.42#ibcon#enter sib2, iclass 11, count 0 2006.259.08:18:51.42#ibcon#flushed, iclass 11, count 0 2006.259.08:18:51.42#ibcon#about to write, iclass 11, count 0 2006.259.08:18:51.42#ibcon#wrote, iclass 11, count 0 2006.259.08:18:51.42#ibcon#about to read 3, iclass 11, count 0 2006.259.08:18:51.46#ibcon#read 3, iclass 11, count 0 2006.259.08:18:51.46#ibcon#about to read 4, iclass 11, count 0 2006.259.08:18:51.46#ibcon#read 4, iclass 11, count 0 2006.259.08:18:51.46#ibcon#about to read 5, iclass 11, count 0 2006.259.08:18:51.46#ibcon#read 5, iclass 11, count 0 2006.259.08:18:51.46#ibcon#about to read 6, iclass 11, count 0 2006.259.08:18:51.46#ibcon#read 6, iclass 11, count 0 2006.259.08:18:51.46#ibcon#end of sib2, iclass 11, count 0 2006.259.08:18:51.46#ibcon#*after write, iclass 11, count 0 2006.259.08:18:51.46#ibcon#*before return 0, iclass 11, count 0 2006.259.08:18:51.46#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.259.08:18:51.46#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.259.08:18:51.46#ibcon#about to clear, iclass 11 cls_cnt 0 2006.259.08:18:51.46#ibcon#cleared, iclass 11 cls_cnt 0 2006.259.08:18:51.46$vc4f8/va=5,7 2006.259.08:18:51.46#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.259.08:18:51.46#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.259.08:18:51.46#ibcon#ireg 11 cls_cnt 2 2006.259.08:18:51.46#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.259.08:18:51.52#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.259.08:18:51.52#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.259.08:18:51.52#ibcon#enter wrdev, iclass 13, count 2 2006.259.08:18:51.52#ibcon#first serial, iclass 13, count 2 2006.259.08:18:51.52#ibcon#enter sib2, iclass 13, count 2 2006.259.08:18:51.52#ibcon#flushed, iclass 13, count 2 2006.259.08:18:51.52#ibcon#about to write, iclass 13, count 2 2006.259.08:18:51.52#ibcon#wrote, iclass 13, count 2 2006.259.08:18:51.52#ibcon#about to read 3, iclass 13, count 2 2006.259.08:18:51.54#ibcon#read 3, iclass 13, count 2 2006.259.08:18:51.54#ibcon#about to read 4, iclass 13, count 2 2006.259.08:18:51.54#ibcon#read 4, iclass 13, count 2 2006.259.08:18:51.54#ibcon#about to read 5, iclass 13, count 2 2006.259.08:18:51.54#ibcon#read 5, iclass 13, count 2 2006.259.08:18:51.54#ibcon#about to read 6, iclass 13, count 2 2006.259.08:18:51.54#ibcon#read 6, iclass 13, count 2 2006.259.08:18:51.54#ibcon#end of sib2, iclass 13, count 2 2006.259.08:18:51.54#ibcon#*mode == 0, iclass 13, count 2 2006.259.08:18:51.54#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.259.08:18:51.54#ibcon#[25=AT05-07\r\n] 2006.259.08:18:51.54#ibcon#*before write, iclass 13, count 2 2006.259.08:18:51.54#ibcon#enter sib2, iclass 13, count 2 2006.259.08:18:51.54#ibcon#flushed, iclass 13, count 2 2006.259.08:18:51.54#ibcon#about to write, iclass 13, count 2 2006.259.08:18:51.54#ibcon#wrote, iclass 13, count 2 2006.259.08:18:51.54#ibcon#about to read 3, iclass 13, count 2 2006.259.08:18:51.57#ibcon#read 3, iclass 13, count 2 2006.259.08:18:51.57#ibcon#about to read 4, iclass 13, count 2 2006.259.08:18:51.57#ibcon#read 4, iclass 13, count 2 2006.259.08:18:51.57#ibcon#about to read 5, iclass 13, count 2 2006.259.08:18:51.57#ibcon#read 5, iclass 13, count 2 2006.259.08:18:51.57#ibcon#about to read 6, iclass 13, count 2 2006.259.08:18:51.57#ibcon#read 6, iclass 13, count 2 2006.259.08:18:51.57#ibcon#end of sib2, iclass 13, count 2 2006.259.08:18:51.57#ibcon#*after write, iclass 13, count 2 2006.259.08:18:51.57#ibcon#*before return 0, iclass 13, count 2 2006.259.08:18:51.57#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.259.08:18:51.57#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.259.08:18:51.57#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.259.08:18:51.57#ibcon#ireg 7 cls_cnt 0 2006.259.08:18:51.57#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.259.08:18:51.69#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.259.08:18:51.69#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.259.08:18:51.69#ibcon#enter wrdev, iclass 13, count 0 2006.259.08:18:51.69#ibcon#first serial, iclass 13, count 0 2006.259.08:18:51.69#ibcon#enter sib2, iclass 13, count 0 2006.259.08:18:51.69#ibcon#flushed, iclass 13, count 0 2006.259.08:18:51.69#ibcon#about to write, iclass 13, count 0 2006.259.08:18:51.69#ibcon#wrote, iclass 13, count 0 2006.259.08:18:51.69#ibcon#about to read 3, iclass 13, count 0 2006.259.08:18:51.71#ibcon#read 3, iclass 13, count 0 2006.259.08:18:51.71#ibcon#about to read 4, iclass 13, count 0 2006.259.08:18:51.71#ibcon#read 4, iclass 13, count 0 2006.259.08:18:51.71#ibcon#about to read 5, iclass 13, count 0 2006.259.08:18:51.71#ibcon#read 5, iclass 13, count 0 2006.259.08:18:51.71#ibcon#about to read 6, iclass 13, count 0 2006.259.08:18:51.71#ibcon#read 6, iclass 13, count 0 2006.259.08:18:51.71#ibcon#end of sib2, iclass 13, count 0 2006.259.08:18:51.71#ibcon#*mode == 0, iclass 13, count 0 2006.259.08:18:51.71#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.259.08:18:51.71#ibcon#[25=USB\r\n] 2006.259.08:18:51.71#ibcon#*before write, iclass 13, count 0 2006.259.08:18:51.71#ibcon#enter sib2, iclass 13, count 0 2006.259.08:18:51.71#ibcon#flushed, iclass 13, count 0 2006.259.08:18:51.71#ibcon#about to write, iclass 13, count 0 2006.259.08:18:51.71#ibcon#wrote, iclass 13, count 0 2006.259.08:18:51.71#ibcon#about to read 3, iclass 13, count 0 2006.259.08:18:51.74#ibcon#read 3, iclass 13, count 0 2006.259.08:18:51.74#ibcon#about to read 4, iclass 13, count 0 2006.259.08:18:51.74#ibcon#read 4, iclass 13, count 0 2006.259.08:18:51.74#ibcon#about to read 5, iclass 13, count 0 2006.259.08:18:51.74#ibcon#read 5, iclass 13, count 0 2006.259.08:18:51.74#ibcon#about to read 6, iclass 13, count 0 2006.259.08:18:51.74#ibcon#read 6, iclass 13, count 0 2006.259.08:18:51.74#ibcon#end of sib2, iclass 13, count 0 2006.259.08:18:51.74#ibcon#*after write, iclass 13, count 0 2006.259.08:18:51.74#ibcon#*before return 0, iclass 13, count 0 2006.259.08:18:51.74#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.259.08:18:51.74#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.259.08:18:51.74#ibcon#about to clear, iclass 13 cls_cnt 0 2006.259.08:18:51.74#ibcon#cleared, iclass 13 cls_cnt 0 2006.259.08:18:51.74$vc4f8/valo=6,772.99 2006.259.08:18:51.74#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.259.08:18:51.74#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.259.08:18:51.74#ibcon#ireg 17 cls_cnt 0 2006.259.08:18:51.74#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.259.08:18:51.74#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.259.08:18:51.74#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.259.08:18:51.74#ibcon#enter wrdev, iclass 15, count 0 2006.259.08:18:51.74#ibcon#first serial, iclass 15, count 0 2006.259.08:18:51.74#ibcon#enter sib2, iclass 15, count 0 2006.259.08:18:51.74#ibcon#flushed, iclass 15, count 0 2006.259.08:18:51.74#ibcon#about to write, iclass 15, count 0 2006.259.08:18:51.74#ibcon#wrote, iclass 15, count 0 2006.259.08:18:51.74#ibcon#about to read 3, iclass 15, count 0 2006.259.08:18:51.76#ibcon#read 3, iclass 15, count 0 2006.259.08:18:51.76#ibcon#about to read 4, iclass 15, count 0 2006.259.08:18:51.76#ibcon#read 4, iclass 15, count 0 2006.259.08:18:51.76#ibcon#about to read 5, iclass 15, count 0 2006.259.08:18:51.76#ibcon#read 5, iclass 15, count 0 2006.259.08:18:51.76#ibcon#about to read 6, iclass 15, count 0 2006.259.08:18:51.76#ibcon#read 6, iclass 15, count 0 2006.259.08:18:51.76#ibcon#end of sib2, iclass 15, count 0 2006.259.08:18:51.76#ibcon#*mode == 0, iclass 15, count 0 2006.259.08:18:51.76#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.259.08:18:51.76#ibcon#[26=FRQ=06,772.99\r\n] 2006.259.08:18:51.76#ibcon#*before write, iclass 15, count 0 2006.259.08:18:51.76#ibcon#enter sib2, iclass 15, count 0 2006.259.08:18:51.76#ibcon#flushed, iclass 15, count 0 2006.259.08:18:51.76#ibcon#about to write, iclass 15, count 0 2006.259.08:18:51.76#ibcon#wrote, iclass 15, count 0 2006.259.08:18:51.76#ibcon#about to read 3, iclass 15, count 0 2006.259.08:18:51.80#ibcon#read 3, iclass 15, count 0 2006.259.08:18:51.80#ibcon#about to read 4, iclass 15, count 0 2006.259.08:18:51.80#ibcon#read 4, iclass 15, count 0 2006.259.08:18:51.80#ibcon#about to read 5, iclass 15, count 0 2006.259.08:18:51.80#ibcon#read 5, iclass 15, count 0 2006.259.08:18:51.80#ibcon#about to read 6, iclass 15, count 0 2006.259.08:18:51.80#ibcon#read 6, iclass 15, count 0 2006.259.08:18:51.80#ibcon#end of sib2, iclass 15, count 0 2006.259.08:18:51.80#ibcon#*after write, iclass 15, count 0 2006.259.08:18:51.80#ibcon#*before return 0, iclass 15, count 0 2006.259.08:18:51.80#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.259.08:18:51.80#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.259.08:18:51.80#ibcon#about to clear, iclass 15 cls_cnt 0 2006.259.08:18:51.80#ibcon#cleared, iclass 15 cls_cnt 0 2006.259.08:18:51.80$vc4f8/va=6,6 2006.259.08:18:51.80#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.259.08:18:51.80#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.259.08:18:51.80#ibcon#ireg 11 cls_cnt 2 2006.259.08:18:51.80#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.259.08:18:51.86#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.259.08:18:51.86#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.259.08:18:51.86#ibcon#enter wrdev, iclass 17, count 2 2006.259.08:18:51.86#ibcon#first serial, iclass 17, count 2 2006.259.08:18:51.86#ibcon#enter sib2, iclass 17, count 2 2006.259.08:18:51.86#ibcon#flushed, iclass 17, count 2 2006.259.08:18:51.86#ibcon#about to write, iclass 17, count 2 2006.259.08:18:51.86#ibcon#wrote, iclass 17, count 2 2006.259.08:18:51.86#ibcon#about to read 3, iclass 17, count 2 2006.259.08:18:51.88#ibcon#read 3, iclass 17, count 2 2006.259.08:18:51.88#ibcon#about to read 4, iclass 17, count 2 2006.259.08:18:51.88#ibcon#read 4, iclass 17, count 2 2006.259.08:18:51.88#ibcon#about to read 5, iclass 17, count 2 2006.259.08:18:51.88#ibcon#read 5, iclass 17, count 2 2006.259.08:18:51.88#ibcon#about to read 6, iclass 17, count 2 2006.259.08:18:51.88#ibcon#read 6, iclass 17, count 2 2006.259.08:18:51.88#ibcon#end of sib2, iclass 17, count 2 2006.259.08:18:51.88#ibcon#*mode == 0, iclass 17, count 2 2006.259.08:18:51.88#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.259.08:18:51.88#ibcon#[25=AT06-06\r\n] 2006.259.08:18:51.88#ibcon#*before write, iclass 17, count 2 2006.259.08:18:51.88#ibcon#enter sib2, iclass 17, count 2 2006.259.08:18:51.88#ibcon#flushed, iclass 17, count 2 2006.259.08:18:51.88#ibcon#about to write, iclass 17, count 2 2006.259.08:18:51.88#ibcon#wrote, iclass 17, count 2 2006.259.08:18:51.88#ibcon#about to read 3, iclass 17, count 2 2006.259.08:18:51.91#ibcon#read 3, iclass 17, count 2 2006.259.08:18:51.91#ibcon#about to read 4, iclass 17, count 2 2006.259.08:18:51.91#ibcon#read 4, iclass 17, count 2 2006.259.08:18:51.91#ibcon#about to read 5, iclass 17, count 2 2006.259.08:18:51.91#ibcon#read 5, iclass 17, count 2 2006.259.08:18:51.91#ibcon#about to read 6, iclass 17, count 2 2006.259.08:18:51.91#ibcon#read 6, iclass 17, count 2 2006.259.08:18:51.91#ibcon#end of sib2, iclass 17, count 2 2006.259.08:18:51.91#ibcon#*after write, iclass 17, count 2 2006.259.08:18:51.91#ibcon#*before return 0, iclass 17, count 2 2006.259.08:18:51.91#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.259.08:18:51.91#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.259.08:18:51.91#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.259.08:18:51.91#ibcon#ireg 7 cls_cnt 0 2006.259.08:18:51.91#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.259.08:18:52.03#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.259.08:18:52.03#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.259.08:18:52.03#ibcon#enter wrdev, iclass 17, count 0 2006.259.08:18:52.03#ibcon#first serial, iclass 17, count 0 2006.259.08:18:52.03#ibcon#enter sib2, iclass 17, count 0 2006.259.08:18:52.03#ibcon#flushed, iclass 17, count 0 2006.259.08:18:52.03#ibcon#about to write, iclass 17, count 0 2006.259.08:18:52.03#ibcon#wrote, iclass 17, count 0 2006.259.08:18:52.03#ibcon#about to read 3, iclass 17, count 0 2006.259.08:18:52.05#ibcon#read 3, iclass 17, count 0 2006.259.08:18:52.05#ibcon#about to read 4, iclass 17, count 0 2006.259.08:18:52.05#ibcon#read 4, iclass 17, count 0 2006.259.08:18:52.05#ibcon#about to read 5, iclass 17, count 0 2006.259.08:18:52.05#ibcon#read 5, iclass 17, count 0 2006.259.08:18:52.05#ibcon#about to read 6, iclass 17, count 0 2006.259.08:18:52.05#ibcon#read 6, iclass 17, count 0 2006.259.08:18:52.05#ibcon#end of sib2, iclass 17, count 0 2006.259.08:18:52.05#ibcon#*mode == 0, iclass 17, count 0 2006.259.08:18:52.05#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.259.08:18:52.05#ibcon#[25=USB\r\n] 2006.259.08:18:52.05#ibcon#*before write, iclass 17, count 0 2006.259.08:18:52.05#ibcon#enter sib2, iclass 17, count 0 2006.259.08:18:52.05#ibcon#flushed, iclass 17, count 0 2006.259.08:18:52.05#ibcon#about to write, iclass 17, count 0 2006.259.08:18:52.05#ibcon#wrote, iclass 17, count 0 2006.259.08:18:52.05#ibcon#about to read 3, iclass 17, count 0 2006.259.08:18:52.08#ibcon#read 3, iclass 17, count 0 2006.259.08:18:52.08#ibcon#about to read 4, iclass 17, count 0 2006.259.08:18:52.08#ibcon#read 4, iclass 17, count 0 2006.259.08:18:52.08#ibcon#about to read 5, iclass 17, count 0 2006.259.08:18:52.08#ibcon#read 5, iclass 17, count 0 2006.259.08:18:52.08#ibcon#about to read 6, iclass 17, count 0 2006.259.08:18:52.08#ibcon#read 6, iclass 17, count 0 2006.259.08:18:52.08#ibcon#end of sib2, iclass 17, count 0 2006.259.08:18:52.08#ibcon#*after write, iclass 17, count 0 2006.259.08:18:52.08#ibcon#*before return 0, iclass 17, count 0 2006.259.08:18:52.08#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.259.08:18:52.08#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.259.08:18:52.08#ibcon#about to clear, iclass 17 cls_cnt 0 2006.259.08:18:52.08#ibcon#cleared, iclass 17 cls_cnt 0 2006.259.08:18:52.08$vc4f8/valo=7,832.99 2006.259.08:18:52.08#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.259.08:18:52.08#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.259.08:18:52.08#ibcon#ireg 17 cls_cnt 0 2006.259.08:18:52.08#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.259.08:18:52.08#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.259.08:18:52.08#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.259.08:18:52.08#ibcon#enter wrdev, iclass 19, count 0 2006.259.08:18:52.08#ibcon#first serial, iclass 19, count 0 2006.259.08:18:52.08#ibcon#enter sib2, iclass 19, count 0 2006.259.08:18:52.08#ibcon#flushed, iclass 19, count 0 2006.259.08:18:52.08#ibcon#about to write, iclass 19, count 0 2006.259.08:18:52.08#ibcon#wrote, iclass 19, count 0 2006.259.08:18:52.08#ibcon#about to read 3, iclass 19, count 0 2006.259.08:18:52.10#ibcon#read 3, iclass 19, count 0 2006.259.08:18:52.10#ibcon#about to read 4, iclass 19, count 0 2006.259.08:18:52.10#ibcon#read 4, iclass 19, count 0 2006.259.08:18:52.10#ibcon#about to read 5, iclass 19, count 0 2006.259.08:18:52.10#ibcon#read 5, iclass 19, count 0 2006.259.08:18:52.10#ibcon#about to read 6, iclass 19, count 0 2006.259.08:18:52.10#ibcon#read 6, iclass 19, count 0 2006.259.08:18:52.10#ibcon#end of sib2, iclass 19, count 0 2006.259.08:18:52.10#ibcon#*mode == 0, iclass 19, count 0 2006.259.08:18:52.10#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.259.08:18:52.10#ibcon#[26=FRQ=07,832.99\r\n] 2006.259.08:18:52.10#ibcon#*before write, iclass 19, count 0 2006.259.08:18:52.10#ibcon#enter sib2, iclass 19, count 0 2006.259.08:18:52.10#ibcon#flushed, iclass 19, count 0 2006.259.08:18:52.10#ibcon#about to write, iclass 19, count 0 2006.259.08:18:52.10#ibcon#wrote, iclass 19, count 0 2006.259.08:18:52.10#ibcon#about to read 3, iclass 19, count 0 2006.259.08:18:52.14#ibcon#read 3, iclass 19, count 0 2006.259.08:18:52.14#ibcon#about to read 4, iclass 19, count 0 2006.259.08:18:52.14#ibcon#read 4, iclass 19, count 0 2006.259.08:18:52.14#ibcon#about to read 5, iclass 19, count 0 2006.259.08:18:52.14#ibcon#read 5, iclass 19, count 0 2006.259.08:18:52.14#ibcon#about to read 6, iclass 19, count 0 2006.259.08:18:52.14#ibcon#read 6, iclass 19, count 0 2006.259.08:18:52.14#ibcon#end of sib2, iclass 19, count 0 2006.259.08:18:52.14#ibcon#*after write, iclass 19, count 0 2006.259.08:18:52.14#ibcon#*before return 0, iclass 19, count 0 2006.259.08:18:52.14#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.259.08:18:52.14#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.259.08:18:52.14#ibcon#about to clear, iclass 19 cls_cnt 0 2006.259.08:18:52.14#ibcon#cleared, iclass 19 cls_cnt 0 2006.259.08:18:52.14$vc4f8/va=7,6 2006.259.08:18:52.14#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.259.08:18:52.14#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.259.08:18:52.14#ibcon#ireg 11 cls_cnt 2 2006.259.08:18:52.14#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.259.08:18:52.20#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.259.08:18:52.20#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.259.08:18:52.20#ibcon#enter wrdev, iclass 21, count 2 2006.259.08:18:52.20#ibcon#first serial, iclass 21, count 2 2006.259.08:18:52.20#ibcon#enter sib2, iclass 21, count 2 2006.259.08:18:52.20#ibcon#flushed, iclass 21, count 2 2006.259.08:18:52.20#ibcon#about to write, iclass 21, count 2 2006.259.08:18:52.20#ibcon#wrote, iclass 21, count 2 2006.259.08:18:52.20#ibcon#about to read 3, iclass 21, count 2 2006.259.08:18:52.22#ibcon#read 3, iclass 21, count 2 2006.259.08:18:52.22#ibcon#about to read 4, iclass 21, count 2 2006.259.08:18:52.22#ibcon#read 4, iclass 21, count 2 2006.259.08:18:52.22#ibcon#about to read 5, iclass 21, count 2 2006.259.08:18:52.22#ibcon#read 5, iclass 21, count 2 2006.259.08:18:52.22#ibcon#about to read 6, iclass 21, count 2 2006.259.08:18:52.22#ibcon#read 6, iclass 21, count 2 2006.259.08:18:52.22#ibcon#end of sib2, iclass 21, count 2 2006.259.08:18:52.22#ibcon#*mode == 0, iclass 21, count 2 2006.259.08:18:52.22#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.259.08:18:52.22#ibcon#[25=AT07-06\r\n] 2006.259.08:18:52.22#ibcon#*before write, iclass 21, count 2 2006.259.08:18:52.22#ibcon#enter sib2, iclass 21, count 2 2006.259.08:18:52.22#ibcon#flushed, iclass 21, count 2 2006.259.08:18:52.22#ibcon#about to write, iclass 21, count 2 2006.259.08:18:52.22#ibcon#wrote, iclass 21, count 2 2006.259.08:18:52.22#ibcon#about to read 3, iclass 21, count 2 2006.259.08:18:52.25#ibcon#read 3, iclass 21, count 2 2006.259.08:18:52.25#ibcon#about to read 4, iclass 21, count 2 2006.259.08:18:52.25#ibcon#read 4, iclass 21, count 2 2006.259.08:18:52.25#ibcon#about to read 5, iclass 21, count 2 2006.259.08:18:52.25#ibcon#read 5, iclass 21, count 2 2006.259.08:18:52.25#ibcon#about to read 6, iclass 21, count 2 2006.259.08:18:52.25#ibcon#read 6, iclass 21, count 2 2006.259.08:18:52.25#ibcon#end of sib2, iclass 21, count 2 2006.259.08:18:52.25#ibcon#*after write, iclass 21, count 2 2006.259.08:18:52.25#ibcon#*before return 0, iclass 21, count 2 2006.259.08:18:52.25#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.259.08:18:52.25#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.259.08:18:52.25#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.259.08:18:52.25#ibcon#ireg 7 cls_cnt 0 2006.259.08:18:52.25#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.259.08:18:52.37#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.259.08:18:52.37#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.259.08:18:52.37#ibcon#enter wrdev, iclass 21, count 0 2006.259.08:18:52.37#ibcon#first serial, iclass 21, count 0 2006.259.08:18:52.37#ibcon#enter sib2, iclass 21, count 0 2006.259.08:18:52.37#ibcon#flushed, iclass 21, count 0 2006.259.08:18:52.37#ibcon#about to write, iclass 21, count 0 2006.259.08:18:52.37#ibcon#wrote, iclass 21, count 0 2006.259.08:18:52.37#ibcon#about to read 3, iclass 21, count 0 2006.259.08:18:52.39#ibcon#read 3, iclass 21, count 0 2006.259.08:18:52.39#ibcon#about to read 4, iclass 21, count 0 2006.259.08:18:52.39#ibcon#read 4, iclass 21, count 0 2006.259.08:18:52.39#ibcon#about to read 5, iclass 21, count 0 2006.259.08:18:52.39#ibcon#read 5, iclass 21, count 0 2006.259.08:18:52.39#ibcon#about to read 6, iclass 21, count 0 2006.259.08:18:52.39#ibcon#read 6, iclass 21, count 0 2006.259.08:18:52.39#ibcon#end of sib2, iclass 21, count 0 2006.259.08:18:52.39#ibcon#*mode == 0, iclass 21, count 0 2006.259.08:18:52.39#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.259.08:18:52.39#ibcon#[25=USB\r\n] 2006.259.08:18:52.39#ibcon#*before write, iclass 21, count 0 2006.259.08:18:52.39#ibcon#enter sib2, iclass 21, count 0 2006.259.08:18:52.39#ibcon#flushed, iclass 21, count 0 2006.259.08:18:52.39#ibcon#about to write, iclass 21, count 0 2006.259.08:18:52.39#ibcon#wrote, iclass 21, count 0 2006.259.08:18:52.39#ibcon#about to read 3, iclass 21, count 0 2006.259.08:18:52.42#ibcon#read 3, iclass 21, count 0 2006.259.08:18:52.42#ibcon#about to read 4, iclass 21, count 0 2006.259.08:18:52.42#ibcon#read 4, iclass 21, count 0 2006.259.08:18:52.42#ibcon#about to read 5, iclass 21, count 0 2006.259.08:18:52.42#ibcon#read 5, iclass 21, count 0 2006.259.08:18:52.42#ibcon#about to read 6, iclass 21, count 0 2006.259.08:18:52.42#ibcon#read 6, iclass 21, count 0 2006.259.08:18:52.42#ibcon#end of sib2, iclass 21, count 0 2006.259.08:18:52.42#ibcon#*after write, iclass 21, count 0 2006.259.08:18:52.42#ibcon#*before return 0, iclass 21, count 0 2006.259.08:18:52.42#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.259.08:18:52.42#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.259.08:18:52.42#ibcon#about to clear, iclass 21 cls_cnt 0 2006.259.08:18:52.42#ibcon#cleared, iclass 21 cls_cnt 0 2006.259.08:18:52.42$vc4f8/valo=8,852.99 2006.259.08:18:52.42#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.259.08:18:52.42#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.259.08:18:52.42#ibcon#ireg 17 cls_cnt 0 2006.259.08:18:52.42#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.259.08:18:52.42#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.259.08:18:52.42#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.259.08:18:52.42#ibcon#enter wrdev, iclass 23, count 0 2006.259.08:18:52.42#ibcon#first serial, iclass 23, count 0 2006.259.08:18:52.42#ibcon#enter sib2, iclass 23, count 0 2006.259.08:18:52.42#ibcon#flushed, iclass 23, count 0 2006.259.08:18:52.42#ibcon#about to write, iclass 23, count 0 2006.259.08:18:52.42#ibcon#wrote, iclass 23, count 0 2006.259.08:18:52.42#ibcon#about to read 3, iclass 23, count 0 2006.259.08:18:52.44#ibcon#read 3, iclass 23, count 0 2006.259.08:18:52.44#ibcon#about to read 4, iclass 23, count 0 2006.259.08:18:52.44#ibcon#read 4, iclass 23, count 0 2006.259.08:18:52.44#ibcon#about to read 5, iclass 23, count 0 2006.259.08:18:52.44#ibcon#read 5, iclass 23, count 0 2006.259.08:18:52.44#ibcon#about to read 6, iclass 23, count 0 2006.259.08:18:52.44#ibcon#read 6, iclass 23, count 0 2006.259.08:18:52.44#ibcon#end of sib2, iclass 23, count 0 2006.259.08:18:52.44#ibcon#*mode == 0, iclass 23, count 0 2006.259.08:18:52.44#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.259.08:18:52.44#ibcon#[26=FRQ=08,852.99\r\n] 2006.259.08:18:52.44#ibcon#*before write, iclass 23, count 0 2006.259.08:18:52.44#ibcon#enter sib2, iclass 23, count 0 2006.259.08:18:52.44#ibcon#flushed, iclass 23, count 0 2006.259.08:18:52.44#ibcon#about to write, iclass 23, count 0 2006.259.08:18:52.44#ibcon#wrote, iclass 23, count 0 2006.259.08:18:52.44#ibcon#about to read 3, iclass 23, count 0 2006.259.08:18:52.48#ibcon#read 3, iclass 23, count 0 2006.259.08:18:52.48#ibcon#about to read 4, iclass 23, count 0 2006.259.08:18:52.48#ibcon#read 4, iclass 23, count 0 2006.259.08:18:52.48#ibcon#about to read 5, iclass 23, count 0 2006.259.08:18:52.48#ibcon#read 5, iclass 23, count 0 2006.259.08:18:52.48#ibcon#about to read 6, iclass 23, count 0 2006.259.08:18:52.48#ibcon#read 6, iclass 23, count 0 2006.259.08:18:52.48#ibcon#end of sib2, iclass 23, count 0 2006.259.08:18:52.48#ibcon#*after write, iclass 23, count 0 2006.259.08:18:52.48#ibcon#*before return 0, iclass 23, count 0 2006.259.08:18:52.48#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.259.08:18:52.48#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.259.08:18:52.48#ibcon#about to clear, iclass 23 cls_cnt 0 2006.259.08:18:52.48#ibcon#cleared, iclass 23 cls_cnt 0 2006.259.08:18:52.48$vc4f8/va=8,6 2006.259.08:18:52.48#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.259.08:18:52.48#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.259.08:18:52.48#ibcon#ireg 11 cls_cnt 2 2006.259.08:18:52.48#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.259.08:18:52.54#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.259.08:18:52.54#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.259.08:18:52.54#ibcon#enter wrdev, iclass 25, count 2 2006.259.08:18:52.54#ibcon#first serial, iclass 25, count 2 2006.259.08:18:52.54#ibcon#enter sib2, iclass 25, count 2 2006.259.08:18:52.54#ibcon#flushed, iclass 25, count 2 2006.259.08:18:52.54#ibcon#about to write, iclass 25, count 2 2006.259.08:18:52.54#ibcon#wrote, iclass 25, count 2 2006.259.08:18:52.54#ibcon#about to read 3, iclass 25, count 2 2006.259.08:18:52.56#ibcon#read 3, iclass 25, count 2 2006.259.08:18:52.56#ibcon#about to read 4, iclass 25, count 2 2006.259.08:18:52.56#ibcon#read 4, iclass 25, count 2 2006.259.08:18:52.56#ibcon#about to read 5, iclass 25, count 2 2006.259.08:18:52.56#ibcon#read 5, iclass 25, count 2 2006.259.08:18:52.56#ibcon#about to read 6, iclass 25, count 2 2006.259.08:18:52.56#ibcon#read 6, iclass 25, count 2 2006.259.08:18:52.56#ibcon#end of sib2, iclass 25, count 2 2006.259.08:18:52.56#ibcon#*mode == 0, iclass 25, count 2 2006.259.08:18:52.56#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.259.08:18:52.56#ibcon#[25=AT08-06\r\n] 2006.259.08:18:52.56#ibcon#*before write, iclass 25, count 2 2006.259.08:18:52.56#ibcon#enter sib2, iclass 25, count 2 2006.259.08:18:52.56#ibcon#flushed, iclass 25, count 2 2006.259.08:18:52.56#ibcon#about to write, iclass 25, count 2 2006.259.08:18:52.56#ibcon#wrote, iclass 25, count 2 2006.259.08:18:52.56#ibcon#about to read 3, iclass 25, count 2 2006.259.08:18:52.59#ibcon#read 3, iclass 25, count 2 2006.259.08:18:52.59#ibcon#about to read 4, iclass 25, count 2 2006.259.08:18:52.59#ibcon#read 4, iclass 25, count 2 2006.259.08:18:52.59#ibcon#about to read 5, iclass 25, count 2 2006.259.08:18:52.59#ibcon#read 5, iclass 25, count 2 2006.259.08:18:52.59#ibcon#about to read 6, iclass 25, count 2 2006.259.08:18:52.59#ibcon#read 6, iclass 25, count 2 2006.259.08:18:52.59#ibcon#end of sib2, iclass 25, count 2 2006.259.08:18:52.59#ibcon#*after write, iclass 25, count 2 2006.259.08:18:52.59#ibcon#*before return 0, iclass 25, count 2 2006.259.08:18:52.59#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.259.08:18:52.59#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.259.08:18:52.59#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.259.08:18:52.59#ibcon#ireg 7 cls_cnt 0 2006.259.08:18:52.59#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.259.08:18:52.71#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.259.08:18:52.71#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.259.08:18:52.71#ibcon#enter wrdev, iclass 25, count 0 2006.259.08:18:52.71#ibcon#first serial, iclass 25, count 0 2006.259.08:18:52.71#ibcon#enter sib2, iclass 25, count 0 2006.259.08:18:52.71#ibcon#flushed, iclass 25, count 0 2006.259.08:18:52.71#ibcon#about to write, iclass 25, count 0 2006.259.08:18:52.71#ibcon#wrote, iclass 25, count 0 2006.259.08:18:52.71#ibcon#about to read 3, iclass 25, count 0 2006.259.08:18:52.73#ibcon#read 3, iclass 25, count 0 2006.259.08:18:52.73#ibcon#about to read 4, iclass 25, count 0 2006.259.08:18:52.73#ibcon#read 4, iclass 25, count 0 2006.259.08:18:52.73#ibcon#about to read 5, iclass 25, count 0 2006.259.08:18:52.73#ibcon#read 5, iclass 25, count 0 2006.259.08:18:52.73#ibcon#about to read 6, iclass 25, count 0 2006.259.08:18:52.73#ibcon#read 6, iclass 25, count 0 2006.259.08:18:52.73#ibcon#end of sib2, iclass 25, count 0 2006.259.08:18:52.73#ibcon#*mode == 0, iclass 25, count 0 2006.259.08:18:52.73#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.259.08:18:52.73#ibcon#[25=USB\r\n] 2006.259.08:18:52.73#ibcon#*before write, iclass 25, count 0 2006.259.08:18:52.73#ibcon#enter sib2, iclass 25, count 0 2006.259.08:18:52.73#ibcon#flushed, iclass 25, count 0 2006.259.08:18:52.73#ibcon#about to write, iclass 25, count 0 2006.259.08:18:52.73#ibcon#wrote, iclass 25, count 0 2006.259.08:18:52.73#ibcon#about to read 3, iclass 25, count 0 2006.259.08:18:52.76#ibcon#read 3, iclass 25, count 0 2006.259.08:18:52.76#ibcon#about to read 4, iclass 25, count 0 2006.259.08:18:52.76#ibcon#read 4, iclass 25, count 0 2006.259.08:18:52.76#ibcon#about to read 5, iclass 25, count 0 2006.259.08:18:52.76#ibcon#read 5, iclass 25, count 0 2006.259.08:18:52.76#ibcon#about to read 6, iclass 25, count 0 2006.259.08:18:52.76#ibcon#read 6, iclass 25, count 0 2006.259.08:18:52.76#ibcon#end of sib2, iclass 25, count 0 2006.259.08:18:52.76#ibcon#*after write, iclass 25, count 0 2006.259.08:18:52.76#ibcon#*before return 0, iclass 25, count 0 2006.259.08:18:52.76#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.259.08:18:52.76#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.259.08:18:52.76#ibcon#about to clear, iclass 25 cls_cnt 0 2006.259.08:18:52.76#ibcon#cleared, iclass 25 cls_cnt 0 2006.259.08:18:52.76$vc4f8/vblo=1,632.99 2006.259.08:18:52.76#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.259.08:18:52.76#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.259.08:18:52.76#ibcon#ireg 17 cls_cnt 0 2006.259.08:18:52.76#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.259.08:18:52.76#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.259.08:18:52.76#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.259.08:18:52.76#ibcon#enter wrdev, iclass 27, count 0 2006.259.08:18:52.76#ibcon#first serial, iclass 27, count 0 2006.259.08:18:52.76#ibcon#enter sib2, iclass 27, count 0 2006.259.08:18:52.76#ibcon#flushed, iclass 27, count 0 2006.259.08:18:52.76#ibcon#about to write, iclass 27, count 0 2006.259.08:18:52.76#ibcon#wrote, iclass 27, count 0 2006.259.08:18:52.76#ibcon#about to read 3, iclass 27, count 0 2006.259.08:18:52.78#ibcon#read 3, iclass 27, count 0 2006.259.08:18:52.78#ibcon#about to read 4, iclass 27, count 0 2006.259.08:18:52.78#ibcon#read 4, iclass 27, count 0 2006.259.08:18:52.78#ibcon#about to read 5, iclass 27, count 0 2006.259.08:18:52.78#ibcon#read 5, iclass 27, count 0 2006.259.08:18:52.78#ibcon#about to read 6, iclass 27, count 0 2006.259.08:18:52.78#ibcon#read 6, iclass 27, count 0 2006.259.08:18:52.78#ibcon#end of sib2, iclass 27, count 0 2006.259.08:18:52.78#ibcon#*mode == 0, iclass 27, count 0 2006.259.08:18:52.78#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.259.08:18:52.78#ibcon#[28=FRQ=01,632.99\r\n] 2006.259.08:18:52.78#ibcon#*before write, iclass 27, count 0 2006.259.08:18:52.78#ibcon#enter sib2, iclass 27, count 0 2006.259.08:18:52.78#ibcon#flushed, iclass 27, count 0 2006.259.08:18:52.78#ibcon#about to write, iclass 27, count 0 2006.259.08:18:52.78#ibcon#wrote, iclass 27, count 0 2006.259.08:18:52.78#ibcon#about to read 3, iclass 27, count 0 2006.259.08:18:52.82#ibcon#read 3, iclass 27, count 0 2006.259.08:18:52.82#ibcon#about to read 4, iclass 27, count 0 2006.259.08:18:52.82#ibcon#read 4, iclass 27, count 0 2006.259.08:18:52.82#ibcon#about to read 5, iclass 27, count 0 2006.259.08:18:52.82#ibcon#read 5, iclass 27, count 0 2006.259.08:18:52.82#ibcon#about to read 6, iclass 27, count 0 2006.259.08:18:52.82#ibcon#read 6, iclass 27, count 0 2006.259.08:18:52.82#ibcon#end of sib2, iclass 27, count 0 2006.259.08:18:52.82#ibcon#*after write, iclass 27, count 0 2006.259.08:18:52.82#ibcon#*before return 0, iclass 27, count 0 2006.259.08:18:52.82#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.259.08:18:52.82#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.259.08:18:52.82#ibcon#about to clear, iclass 27 cls_cnt 0 2006.259.08:18:52.82#ibcon#cleared, iclass 27 cls_cnt 0 2006.259.08:18:52.82$vc4f8/vb=1,4 2006.259.08:18:52.82#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.259.08:18:52.82#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.259.08:18:52.82#ibcon#ireg 11 cls_cnt 2 2006.259.08:18:52.82#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.259.08:18:52.82#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.259.08:18:52.82#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.259.08:18:52.82#ibcon#enter wrdev, iclass 29, count 2 2006.259.08:18:52.82#ibcon#first serial, iclass 29, count 2 2006.259.08:18:52.82#ibcon#enter sib2, iclass 29, count 2 2006.259.08:18:52.82#ibcon#flushed, iclass 29, count 2 2006.259.08:18:52.82#ibcon#about to write, iclass 29, count 2 2006.259.08:18:52.82#ibcon#wrote, iclass 29, count 2 2006.259.08:18:52.82#ibcon#about to read 3, iclass 29, count 2 2006.259.08:18:52.84#ibcon#read 3, iclass 29, count 2 2006.259.08:18:52.84#ibcon#about to read 4, iclass 29, count 2 2006.259.08:18:52.84#ibcon#read 4, iclass 29, count 2 2006.259.08:18:52.84#ibcon#about to read 5, iclass 29, count 2 2006.259.08:18:52.84#ibcon#read 5, iclass 29, count 2 2006.259.08:18:52.84#ibcon#about to read 6, iclass 29, count 2 2006.259.08:18:52.84#ibcon#read 6, iclass 29, count 2 2006.259.08:18:52.84#ibcon#end of sib2, iclass 29, count 2 2006.259.08:18:52.84#ibcon#*mode == 0, iclass 29, count 2 2006.259.08:18:52.84#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.259.08:18:52.84#ibcon#[27=AT01-04\r\n] 2006.259.08:18:52.84#ibcon#*before write, iclass 29, count 2 2006.259.08:18:52.84#ibcon#enter sib2, iclass 29, count 2 2006.259.08:18:52.84#ibcon#flushed, iclass 29, count 2 2006.259.08:18:52.84#ibcon#about to write, iclass 29, count 2 2006.259.08:18:52.84#ibcon#wrote, iclass 29, count 2 2006.259.08:18:52.84#ibcon#about to read 3, iclass 29, count 2 2006.259.08:18:52.87#ibcon#read 3, iclass 29, count 2 2006.259.08:18:52.87#ibcon#about to read 4, iclass 29, count 2 2006.259.08:18:52.87#ibcon#read 4, iclass 29, count 2 2006.259.08:18:52.87#ibcon#about to read 5, iclass 29, count 2 2006.259.08:18:52.87#ibcon#read 5, iclass 29, count 2 2006.259.08:18:52.87#ibcon#about to read 6, iclass 29, count 2 2006.259.08:18:52.87#ibcon#read 6, iclass 29, count 2 2006.259.08:18:52.87#ibcon#end of sib2, iclass 29, count 2 2006.259.08:18:52.87#ibcon#*after write, iclass 29, count 2 2006.259.08:18:52.87#ibcon#*before return 0, iclass 29, count 2 2006.259.08:18:52.87#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.259.08:18:52.87#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.259.08:18:52.87#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.259.08:18:52.87#ibcon#ireg 7 cls_cnt 0 2006.259.08:18:52.87#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.259.08:18:52.99#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.259.08:18:52.99#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.259.08:18:52.99#ibcon#enter wrdev, iclass 29, count 0 2006.259.08:18:52.99#ibcon#first serial, iclass 29, count 0 2006.259.08:18:52.99#ibcon#enter sib2, iclass 29, count 0 2006.259.08:18:52.99#ibcon#flushed, iclass 29, count 0 2006.259.08:18:52.99#ibcon#about to write, iclass 29, count 0 2006.259.08:18:52.99#ibcon#wrote, iclass 29, count 0 2006.259.08:18:52.99#ibcon#about to read 3, iclass 29, count 0 2006.259.08:18:53.01#ibcon#read 3, iclass 29, count 0 2006.259.08:18:53.01#ibcon#about to read 4, iclass 29, count 0 2006.259.08:18:53.01#ibcon#read 4, iclass 29, count 0 2006.259.08:18:53.01#ibcon#about to read 5, iclass 29, count 0 2006.259.08:18:53.01#ibcon#read 5, iclass 29, count 0 2006.259.08:18:53.01#ibcon#about to read 6, iclass 29, count 0 2006.259.08:18:53.01#ibcon#read 6, iclass 29, count 0 2006.259.08:18:53.01#ibcon#end of sib2, iclass 29, count 0 2006.259.08:18:53.01#ibcon#*mode == 0, iclass 29, count 0 2006.259.08:18:53.01#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.259.08:18:53.01#ibcon#[27=USB\r\n] 2006.259.08:18:53.01#ibcon#*before write, iclass 29, count 0 2006.259.08:18:53.01#ibcon#enter sib2, iclass 29, count 0 2006.259.08:18:53.01#ibcon#flushed, iclass 29, count 0 2006.259.08:18:53.01#ibcon#about to write, iclass 29, count 0 2006.259.08:18:53.01#ibcon#wrote, iclass 29, count 0 2006.259.08:18:53.01#ibcon#about to read 3, iclass 29, count 0 2006.259.08:18:53.04#ibcon#read 3, iclass 29, count 0 2006.259.08:18:53.04#ibcon#about to read 4, iclass 29, count 0 2006.259.08:18:53.04#ibcon#read 4, iclass 29, count 0 2006.259.08:18:53.04#ibcon#about to read 5, iclass 29, count 0 2006.259.08:18:53.04#ibcon#read 5, iclass 29, count 0 2006.259.08:18:53.04#ibcon#about to read 6, iclass 29, count 0 2006.259.08:18:53.04#ibcon#read 6, iclass 29, count 0 2006.259.08:18:53.04#ibcon#end of sib2, iclass 29, count 0 2006.259.08:18:53.04#ibcon#*after write, iclass 29, count 0 2006.259.08:18:53.04#ibcon#*before return 0, iclass 29, count 0 2006.259.08:18:53.04#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.259.08:18:53.04#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.259.08:18:53.04#ibcon#about to clear, iclass 29 cls_cnt 0 2006.259.08:18:53.04#ibcon#cleared, iclass 29 cls_cnt 0 2006.259.08:18:53.04$vc4f8/vblo=2,640.99 2006.259.08:18:53.04#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.259.08:18:53.04#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.259.08:18:53.04#ibcon#ireg 17 cls_cnt 0 2006.259.08:18:53.04#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.259.08:18:53.04#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.259.08:18:53.04#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.259.08:18:53.04#ibcon#enter wrdev, iclass 31, count 0 2006.259.08:18:53.04#ibcon#first serial, iclass 31, count 0 2006.259.08:18:53.04#ibcon#enter sib2, iclass 31, count 0 2006.259.08:18:53.04#ibcon#flushed, iclass 31, count 0 2006.259.08:18:53.04#ibcon#about to write, iclass 31, count 0 2006.259.08:18:53.04#ibcon#wrote, iclass 31, count 0 2006.259.08:18:53.04#ibcon#about to read 3, iclass 31, count 0 2006.259.08:18:53.06#ibcon#read 3, iclass 31, count 0 2006.259.08:18:53.06#ibcon#about to read 4, iclass 31, count 0 2006.259.08:18:53.06#ibcon#read 4, iclass 31, count 0 2006.259.08:18:53.06#ibcon#about to read 5, iclass 31, count 0 2006.259.08:18:53.06#ibcon#read 5, iclass 31, count 0 2006.259.08:18:53.06#ibcon#about to read 6, iclass 31, count 0 2006.259.08:18:53.06#ibcon#read 6, iclass 31, count 0 2006.259.08:18:53.06#ibcon#end of sib2, iclass 31, count 0 2006.259.08:18:53.06#ibcon#*mode == 0, iclass 31, count 0 2006.259.08:18:53.06#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.259.08:18:53.06#ibcon#[28=FRQ=02,640.99\r\n] 2006.259.08:18:53.06#ibcon#*before write, iclass 31, count 0 2006.259.08:18:53.06#ibcon#enter sib2, iclass 31, count 0 2006.259.08:18:53.06#ibcon#flushed, iclass 31, count 0 2006.259.08:18:53.06#ibcon#about to write, iclass 31, count 0 2006.259.08:18:53.06#ibcon#wrote, iclass 31, count 0 2006.259.08:18:53.06#ibcon#about to read 3, iclass 31, count 0 2006.259.08:18:53.10#ibcon#read 3, iclass 31, count 0 2006.259.08:18:53.10#ibcon#about to read 4, iclass 31, count 0 2006.259.08:18:53.10#ibcon#read 4, iclass 31, count 0 2006.259.08:18:53.10#ibcon#about to read 5, iclass 31, count 0 2006.259.08:18:53.10#ibcon#read 5, iclass 31, count 0 2006.259.08:18:53.10#ibcon#about to read 6, iclass 31, count 0 2006.259.08:18:53.10#ibcon#read 6, iclass 31, count 0 2006.259.08:18:53.10#ibcon#end of sib2, iclass 31, count 0 2006.259.08:18:53.10#ibcon#*after write, iclass 31, count 0 2006.259.08:18:53.10#ibcon#*before return 0, iclass 31, count 0 2006.259.08:18:53.10#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.259.08:18:53.10#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.259.08:18:53.10#ibcon#about to clear, iclass 31 cls_cnt 0 2006.259.08:18:53.10#ibcon#cleared, iclass 31 cls_cnt 0 2006.259.08:18:53.10$vc4f8/vb=2,5 2006.259.08:18:53.10#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.259.08:18:53.10#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.259.08:18:53.10#ibcon#ireg 11 cls_cnt 2 2006.259.08:18:53.10#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.259.08:18:53.16#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.259.08:18:53.16#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.259.08:18:53.16#ibcon#enter wrdev, iclass 33, count 2 2006.259.08:18:53.16#ibcon#first serial, iclass 33, count 2 2006.259.08:18:53.16#ibcon#enter sib2, iclass 33, count 2 2006.259.08:18:53.16#ibcon#flushed, iclass 33, count 2 2006.259.08:18:53.16#ibcon#about to write, iclass 33, count 2 2006.259.08:18:53.16#ibcon#wrote, iclass 33, count 2 2006.259.08:18:53.16#ibcon#about to read 3, iclass 33, count 2 2006.259.08:18:53.18#ibcon#read 3, iclass 33, count 2 2006.259.08:18:53.18#ibcon#about to read 4, iclass 33, count 2 2006.259.08:18:53.18#ibcon#read 4, iclass 33, count 2 2006.259.08:18:53.18#ibcon#about to read 5, iclass 33, count 2 2006.259.08:18:53.18#ibcon#read 5, iclass 33, count 2 2006.259.08:18:53.18#ibcon#about to read 6, iclass 33, count 2 2006.259.08:18:53.18#ibcon#read 6, iclass 33, count 2 2006.259.08:18:53.18#ibcon#end of sib2, iclass 33, count 2 2006.259.08:18:53.18#ibcon#*mode == 0, iclass 33, count 2 2006.259.08:18:53.18#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.259.08:18:53.18#ibcon#[27=AT02-05\r\n] 2006.259.08:18:53.18#ibcon#*before write, iclass 33, count 2 2006.259.08:18:53.18#ibcon#enter sib2, iclass 33, count 2 2006.259.08:18:53.18#ibcon#flushed, iclass 33, count 2 2006.259.08:18:53.18#ibcon#about to write, iclass 33, count 2 2006.259.08:18:53.18#ibcon#wrote, iclass 33, count 2 2006.259.08:18:53.18#ibcon#about to read 3, iclass 33, count 2 2006.259.08:18:53.21#ibcon#read 3, iclass 33, count 2 2006.259.08:18:53.21#ibcon#about to read 4, iclass 33, count 2 2006.259.08:18:53.21#ibcon#read 4, iclass 33, count 2 2006.259.08:18:53.21#ibcon#about to read 5, iclass 33, count 2 2006.259.08:18:53.21#ibcon#read 5, iclass 33, count 2 2006.259.08:18:53.21#ibcon#about to read 6, iclass 33, count 2 2006.259.08:18:53.21#ibcon#read 6, iclass 33, count 2 2006.259.08:18:53.21#ibcon#end of sib2, iclass 33, count 2 2006.259.08:18:53.21#ibcon#*after write, iclass 33, count 2 2006.259.08:18:53.21#ibcon#*before return 0, iclass 33, count 2 2006.259.08:18:53.21#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.259.08:18:53.21#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.259.08:18:53.21#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.259.08:18:53.21#ibcon#ireg 7 cls_cnt 0 2006.259.08:18:53.21#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.259.08:18:53.33#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.259.08:18:53.33#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.259.08:18:53.33#ibcon#enter wrdev, iclass 33, count 0 2006.259.08:18:53.33#ibcon#first serial, iclass 33, count 0 2006.259.08:18:53.33#ibcon#enter sib2, iclass 33, count 0 2006.259.08:18:53.33#ibcon#flushed, iclass 33, count 0 2006.259.08:18:53.33#ibcon#about to write, iclass 33, count 0 2006.259.08:18:53.33#ibcon#wrote, iclass 33, count 0 2006.259.08:18:53.33#ibcon#about to read 3, iclass 33, count 0 2006.259.08:18:53.35#ibcon#read 3, iclass 33, count 0 2006.259.08:18:53.35#ibcon#about to read 4, iclass 33, count 0 2006.259.08:18:53.35#ibcon#read 4, iclass 33, count 0 2006.259.08:18:53.35#ibcon#about to read 5, iclass 33, count 0 2006.259.08:18:53.35#ibcon#read 5, iclass 33, count 0 2006.259.08:18:53.35#ibcon#about to read 6, iclass 33, count 0 2006.259.08:18:53.35#ibcon#read 6, iclass 33, count 0 2006.259.08:18:53.35#ibcon#end of sib2, iclass 33, count 0 2006.259.08:18:53.35#ibcon#*mode == 0, iclass 33, count 0 2006.259.08:18:53.35#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.259.08:18:53.35#ibcon#[27=USB\r\n] 2006.259.08:18:53.35#ibcon#*before write, iclass 33, count 0 2006.259.08:18:53.35#ibcon#enter sib2, iclass 33, count 0 2006.259.08:18:53.35#ibcon#flushed, iclass 33, count 0 2006.259.08:18:53.35#ibcon#about to write, iclass 33, count 0 2006.259.08:18:53.35#ibcon#wrote, iclass 33, count 0 2006.259.08:18:53.35#ibcon#about to read 3, iclass 33, count 0 2006.259.08:18:53.38#ibcon#read 3, iclass 33, count 0 2006.259.08:18:53.38#ibcon#about to read 4, iclass 33, count 0 2006.259.08:18:53.38#ibcon#read 4, iclass 33, count 0 2006.259.08:18:53.38#ibcon#about to read 5, iclass 33, count 0 2006.259.08:18:53.38#ibcon#read 5, iclass 33, count 0 2006.259.08:18:53.38#ibcon#about to read 6, iclass 33, count 0 2006.259.08:18:53.38#ibcon#read 6, iclass 33, count 0 2006.259.08:18:53.38#ibcon#end of sib2, iclass 33, count 0 2006.259.08:18:53.38#ibcon#*after write, iclass 33, count 0 2006.259.08:18:53.38#ibcon#*before return 0, iclass 33, count 0 2006.259.08:18:53.38#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.259.08:18:53.38#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.259.08:18:53.38#ibcon#about to clear, iclass 33 cls_cnt 0 2006.259.08:18:53.38#ibcon#cleared, iclass 33 cls_cnt 0 2006.259.08:18:53.38$vc4f8/vblo=3,656.99 2006.259.08:18:53.38#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.259.08:18:53.38#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.259.08:18:53.38#ibcon#ireg 17 cls_cnt 0 2006.259.08:18:53.38#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.259.08:18:53.38#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.259.08:18:53.38#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.259.08:18:53.38#ibcon#enter wrdev, iclass 35, count 0 2006.259.08:18:53.38#ibcon#first serial, iclass 35, count 0 2006.259.08:18:53.38#ibcon#enter sib2, iclass 35, count 0 2006.259.08:18:53.38#ibcon#flushed, iclass 35, count 0 2006.259.08:18:53.38#ibcon#about to write, iclass 35, count 0 2006.259.08:18:53.38#ibcon#wrote, iclass 35, count 0 2006.259.08:18:53.38#ibcon#about to read 3, iclass 35, count 0 2006.259.08:18:53.40#ibcon#read 3, iclass 35, count 0 2006.259.08:18:53.40#ibcon#about to read 4, iclass 35, count 0 2006.259.08:18:53.40#ibcon#read 4, iclass 35, count 0 2006.259.08:18:53.40#ibcon#about to read 5, iclass 35, count 0 2006.259.08:18:53.40#ibcon#read 5, iclass 35, count 0 2006.259.08:18:53.40#ibcon#about to read 6, iclass 35, count 0 2006.259.08:18:53.40#ibcon#read 6, iclass 35, count 0 2006.259.08:18:53.40#ibcon#end of sib2, iclass 35, count 0 2006.259.08:18:53.40#ibcon#*mode == 0, iclass 35, count 0 2006.259.08:18:53.40#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.259.08:18:53.40#ibcon#[28=FRQ=03,656.99\r\n] 2006.259.08:18:53.40#ibcon#*before write, iclass 35, count 0 2006.259.08:18:53.40#ibcon#enter sib2, iclass 35, count 0 2006.259.08:18:53.40#ibcon#flushed, iclass 35, count 0 2006.259.08:18:53.40#ibcon#about to write, iclass 35, count 0 2006.259.08:18:53.40#ibcon#wrote, iclass 35, count 0 2006.259.08:18:53.40#ibcon#about to read 3, iclass 35, count 0 2006.259.08:18:53.44#ibcon#read 3, iclass 35, count 0 2006.259.08:18:53.44#ibcon#about to read 4, iclass 35, count 0 2006.259.08:18:53.44#ibcon#read 4, iclass 35, count 0 2006.259.08:18:53.44#ibcon#about to read 5, iclass 35, count 0 2006.259.08:18:53.44#ibcon#read 5, iclass 35, count 0 2006.259.08:18:53.44#ibcon#about to read 6, iclass 35, count 0 2006.259.08:18:53.44#ibcon#read 6, iclass 35, count 0 2006.259.08:18:53.44#ibcon#end of sib2, iclass 35, count 0 2006.259.08:18:53.44#ibcon#*after write, iclass 35, count 0 2006.259.08:18:53.44#ibcon#*before return 0, iclass 35, count 0 2006.259.08:18:53.44#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.259.08:18:53.44#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.259.08:18:53.44#ibcon#about to clear, iclass 35 cls_cnt 0 2006.259.08:18:53.44#ibcon#cleared, iclass 35 cls_cnt 0 2006.259.08:18:53.44$vc4f8/vb=3,4 2006.259.08:18:53.44#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.259.08:18:53.44#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.259.08:18:53.44#ibcon#ireg 11 cls_cnt 2 2006.259.08:18:53.44#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.259.08:18:53.50#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.259.08:18:53.50#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.259.08:18:53.50#ibcon#enter wrdev, iclass 37, count 2 2006.259.08:18:53.50#ibcon#first serial, iclass 37, count 2 2006.259.08:18:53.50#ibcon#enter sib2, iclass 37, count 2 2006.259.08:18:53.50#ibcon#flushed, iclass 37, count 2 2006.259.08:18:53.50#ibcon#about to write, iclass 37, count 2 2006.259.08:18:53.50#ibcon#wrote, iclass 37, count 2 2006.259.08:18:53.50#ibcon#about to read 3, iclass 37, count 2 2006.259.08:18:53.52#ibcon#read 3, iclass 37, count 2 2006.259.08:18:53.52#ibcon#about to read 4, iclass 37, count 2 2006.259.08:18:53.52#ibcon#read 4, iclass 37, count 2 2006.259.08:18:53.52#ibcon#about to read 5, iclass 37, count 2 2006.259.08:18:53.52#ibcon#read 5, iclass 37, count 2 2006.259.08:18:53.52#ibcon#about to read 6, iclass 37, count 2 2006.259.08:18:53.52#ibcon#read 6, iclass 37, count 2 2006.259.08:18:53.52#ibcon#end of sib2, iclass 37, count 2 2006.259.08:18:53.52#ibcon#*mode == 0, iclass 37, count 2 2006.259.08:18:53.52#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.259.08:18:53.52#ibcon#[27=AT03-04\r\n] 2006.259.08:18:53.52#ibcon#*before write, iclass 37, count 2 2006.259.08:18:53.52#ibcon#enter sib2, iclass 37, count 2 2006.259.08:18:53.52#ibcon#flushed, iclass 37, count 2 2006.259.08:18:53.52#ibcon#about to write, iclass 37, count 2 2006.259.08:18:53.52#ibcon#wrote, iclass 37, count 2 2006.259.08:18:53.52#ibcon#about to read 3, iclass 37, count 2 2006.259.08:18:53.55#ibcon#read 3, iclass 37, count 2 2006.259.08:18:53.55#ibcon#about to read 4, iclass 37, count 2 2006.259.08:18:53.55#ibcon#read 4, iclass 37, count 2 2006.259.08:18:53.55#ibcon#about to read 5, iclass 37, count 2 2006.259.08:18:53.55#ibcon#read 5, iclass 37, count 2 2006.259.08:18:53.55#ibcon#about to read 6, iclass 37, count 2 2006.259.08:18:53.55#ibcon#read 6, iclass 37, count 2 2006.259.08:18:53.55#ibcon#end of sib2, iclass 37, count 2 2006.259.08:18:53.55#ibcon#*after write, iclass 37, count 2 2006.259.08:18:53.55#ibcon#*before return 0, iclass 37, count 2 2006.259.08:18:53.55#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.259.08:18:53.55#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.259.08:18:53.55#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.259.08:18:53.55#ibcon#ireg 7 cls_cnt 0 2006.259.08:18:53.55#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.259.08:18:53.67#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.259.08:18:53.67#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.259.08:18:53.67#ibcon#enter wrdev, iclass 37, count 0 2006.259.08:18:53.67#ibcon#first serial, iclass 37, count 0 2006.259.08:18:53.67#ibcon#enter sib2, iclass 37, count 0 2006.259.08:18:53.67#ibcon#flushed, iclass 37, count 0 2006.259.08:18:53.67#ibcon#about to write, iclass 37, count 0 2006.259.08:18:53.67#ibcon#wrote, iclass 37, count 0 2006.259.08:18:53.67#ibcon#about to read 3, iclass 37, count 0 2006.259.08:18:53.69#ibcon#read 3, iclass 37, count 0 2006.259.08:18:53.69#ibcon#about to read 4, iclass 37, count 0 2006.259.08:18:53.69#ibcon#read 4, iclass 37, count 0 2006.259.08:18:53.69#ibcon#about to read 5, iclass 37, count 0 2006.259.08:18:53.69#ibcon#read 5, iclass 37, count 0 2006.259.08:18:53.69#ibcon#about to read 6, iclass 37, count 0 2006.259.08:18:53.69#ibcon#read 6, iclass 37, count 0 2006.259.08:18:53.69#ibcon#end of sib2, iclass 37, count 0 2006.259.08:18:53.69#ibcon#*mode == 0, iclass 37, count 0 2006.259.08:18:53.69#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.259.08:18:53.69#ibcon#[27=USB\r\n] 2006.259.08:18:53.69#ibcon#*before write, iclass 37, count 0 2006.259.08:18:53.69#ibcon#enter sib2, iclass 37, count 0 2006.259.08:18:53.69#ibcon#flushed, iclass 37, count 0 2006.259.08:18:53.69#ibcon#about to write, iclass 37, count 0 2006.259.08:18:53.69#ibcon#wrote, iclass 37, count 0 2006.259.08:18:53.69#ibcon#about to read 3, iclass 37, count 0 2006.259.08:18:53.72#ibcon#read 3, iclass 37, count 0 2006.259.08:18:53.72#ibcon#about to read 4, iclass 37, count 0 2006.259.08:18:53.72#ibcon#read 4, iclass 37, count 0 2006.259.08:18:53.72#ibcon#about to read 5, iclass 37, count 0 2006.259.08:18:53.72#ibcon#read 5, iclass 37, count 0 2006.259.08:18:53.72#ibcon#about to read 6, iclass 37, count 0 2006.259.08:18:53.72#ibcon#read 6, iclass 37, count 0 2006.259.08:18:53.72#ibcon#end of sib2, iclass 37, count 0 2006.259.08:18:53.72#ibcon#*after write, iclass 37, count 0 2006.259.08:18:53.72#ibcon#*before return 0, iclass 37, count 0 2006.259.08:18:53.72#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.259.08:18:53.72#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.259.08:18:53.72#ibcon#about to clear, iclass 37 cls_cnt 0 2006.259.08:18:53.72#ibcon#cleared, iclass 37 cls_cnt 0 2006.259.08:18:53.72$vc4f8/vblo=4,712.99 2006.259.08:18:53.72#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.259.08:18:53.72#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.259.08:18:53.72#ibcon#ireg 17 cls_cnt 0 2006.259.08:18:53.72#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.259.08:18:53.72#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.259.08:18:53.72#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.259.08:18:53.72#ibcon#enter wrdev, iclass 39, count 0 2006.259.08:18:53.72#ibcon#first serial, iclass 39, count 0 2006.259.08:18:53.72#ibcon#enter sib2, iclass 39, count 0 2006.259.08:18:53.72#ibcon#flushed, iclass 39, count 0 2006.259.08:18:53.72#ibcon#about to write, iclass 39, count 0 2006.259.08:18:53.72#ibcon#wrote, iclass 39, count 0 2006.259.08:18:53.72#ibcon#about to read 3, iclass 39, count 0 2006.259.08:18:53.74#ibcon#read 3, iclass 39, count 0 2006.259.08:18:53.74#ibcon#about to read 4, iclass 39, count 0 2006.259.08:18:53.74#ibcon#read 4, iclass 39, count 0 2006.259.08:18:53.74#ibcon#about to read 5, iclass 39, count 0 2006.259.08:18:53.74#ibcon#read 5, iclass 39, count 0 2006.259.08:18:53.74#ibcon#about to read 6, iclass 39, count 0 2006.259.08:18:53.74#ibcon#read 6, iclass 39, count 0 2006.259.08:18:53.74#ibcon#end of sib2, iclass 39, count 0 2006.259.08:18:53.74#ibcon#*mode == 0, iclass 39, count 0 2006.259.08:18:53.74#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.259.08:18:53.74#ibcon#[28=FRQ=04,712.99\r\n] 2006.259.08:18:53.74#ibcon#*before write, iclass 39, count 0 2006.259.08:18:53.74#ibcon#enter sib2, iclass 39, count 0 2006.259.08:18:53.74#ibcon#flushed, iclass 39, count 0 2006.259.08:18:53.74#ibcon#about to write, iclass 39, count 0 2006.259.08:18:53.74#ibcon#wrote, iclass 39, count 0 2006.259.08:18:53.74#ibcon#about to read 3, iclass 39, count 0 2006.259.08:18:53.78#ibcon#read 3, iclass 39, count 0 2006.259.08:18:53.78#ibcon#about to read 4, iclass 39, count 0 2006.259.08:18:53.78#ibcon#read 4, iclass 39, count 0 2006.259.08:18:53.78#ibcon#about to read 5, iclass 39, count 0 2006.259.08:18:53.78#ibcon#read 5, iclass 39, count 0 2006.259.08:18:53.78#ibcon#about to read 6, iclass 39, count 0 2006.259.08:18:53.78#ibcon#read 6, iclass 39, count 0 2006.259.08:18:53.78#ibcon#end of sib2, iclass 39, count 0 2006.259.08:18:53.78#ibcon#*after write, iclass 39, count 0 2006.259.08:18:53.78#ibcon#*before return 0, iclass 39, count 0 2006.259.08:18:53.78#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.259.08:18:53.78#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.259.08:18:53.78#ibcon#about to clear, iclass 39 cls_cnt 0 2006.259.08:18:53.78#ibcon#cleared, iclass 39 cls_cnt 0 2006.259.08:18:53.78$vc4f8/vb=4,5 2006.259.08:18:53.78#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.259.08:18:53.78#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.259.08:18:53.78#ibcon#ireg 11 cls_cnt 2 2006.259.08:18:53.78#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.259.08:18:53.84#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.259.08:18:53.84#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.259.08:18:53.84#ibcon#enter wrdev, iclass 3, count 2 2006.259.08:18:53.84#ibcon#first serial, iclass 3, count 2 2006.259.08:18:53.84#ibcon#enter sib2, iclass 3, count 2 2006.259.08:18:53.84#ibcon#flushed, iclass 3, count 2 2006.259.08:18:53.84#ibcon#about to write, iclass 3, count 2 2006.259.08:18:53.84#ibcon#wrote, iclass 3, count 2 2006.259.08:18:53.84#ibcon#about to read 3, iclass 3, count 2 2006.259.08:18:53.86#ibcon#read 3, iclass 3, count 2 2006.259.08:18:53.86#ibcon#about to read 4, iclass 3, count 2 2006.259.08:18:53.86#ibcon#read 4, iclass 3, count 2 2006.259.08:18:53.86#ibcon#about to read 5, iclass 3, count 2 2006.259.08:18:53.86#ibcon#read 5, iclass 3, count 2 2006.259.08:18:53.86#ibcon#about to read 6, iclass 3, count 2 2006.259.08:18:53.86#ibcon#read 6, iclass 3, count 2 2006.259.08:18:53.86#ibcon#end of sib2, iclass 3, count 2 2006.259.08:18:53.86#ibcon#*mode == 0, iclass 3, count 2 2006.259.08:18:53.86#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.259.08:18:53.86#ibcon#[27=AT04-05\r\n] 2006.259.08:18:53.86#ibcon#*before write, iclass 3, count 2 2006.259.08:18:53.86#ibcon#enter sib2, iclass 3, count 2 2006.259.08:18:53.86#ibcon#flushed, iclass 3, count 2 2006.259.08:18:53.86#ibcon#about to write, iclass 3, count 2 2006.259.08:18:53.86#ibcon#wrote, iclass 3, count 2 2006.259.08:18:53.86#ibcon#about to read 3, iclass 3, count 2 2006.259.08:18:53.89#ibcon#read 3, iclass 3, count 2 2006.259.08:18:53.89#ibcon#about to read 4, iclass 3, count 2 2006.259.08:18:53.89#ibcon#read 4, iclass 3, count 2 2006.259.08:18:53.89#ibcon#about to read 5, iclass 3, count 2 2006.259.08:18:53.89#ibcon#read 5, iclass 3, count 2 2006.259.08:18:53.89#ibcon#about to read 6, iclass 3, count 2 2006.259.08:18:53.89#ibcon#read 6, iclass 3, count 2 2006.259.08:18:53.89#ibcon#end of sib2, iclass 3, count 2 2006.259.08:18:53.89#ibcon#*after write, iclass 3, count 2 2006.259.08:18:53.89#ibcon#*before return 0, iclass 3, count 2 2006.259.08:18:53.89#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.259.08:18:53.89#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.259.08:18:53.89#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.259.08:18:53.89#ibcon#ireg 7 cls_cnt 0 2006.259.08:18:53.89#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.259.08:18:54.01#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.259.08:18:54.01#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.259.08:18:54.01#ibcon#enter wrdev, iclass 3, count 0 2006.259.08:18:54.01#ibcon#first serial, iclass 3, count 0 2006.259.08:18:54.01#ibcon#enter sib2, iclass 3, count 0 2006.259.08:18:54.01#ibcon#flushed, iclass 3, count 0 2006.259.08:18:54.01#ibcon#about to write, iclass 3, count 0 2006.259.08:18:54.01#ibcon#wrote, iclass 3, count 0 2006.259.08:18:54.01#ibcon#about to read 3, iclass 3, count 0 2006.259.08:18:54.03#ibcon#read 3, iclass 3, count 0 2006.259.08:18:54.03#ibcon#about to read 4, iclass 3, count 0 2006.259.08:18:54.03#ibcon#read 4, iclass 3, count 0 2006.259.08:18:54.03#ibcon#about to read 5, iclass 3, count 0 2006.259.08:18:54.03#ibcon#read 5, iclass 3, count 0 2006.259.08:18:54.03#ibcon#about to read 6, iclass 3, count 0 2006.259.08:18:54.03#ibcon#read 6, iclass 3, count 0 2006.259.08:18:54.03#ibcon#end of sib2, iclass 3, count 0 2006.259.08:18:54.03#ibcon#*mode == 0, iclass 3, count 0 2006.259.08:18:54.03#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.259.08:18:54.03#ibcon#[27=USB\r\n] 2006.259.08:18:54.03#ibcon#*before write, iclass 3, count 0 2006.259.08:18:54.03#ibcon#enter sib2, iclass 3, count 0 2006.259.08:18:54.03#ibcon#flushed, iclass 3, count 0 2006.259.08:18:54.03#ibcon#about to write, iclass 3, count 0 2006.259.08:18:54.03#ibcon#wrote, iclass 3, count 0 2006.259.08:18:54.03#ibcon#about to read 3, iclass 3, count 0 2006.259.08:18:54.06#ibcon#read 3, iclass 3, count 0 2006.259.08:18:54.06#ibcon#about to read 4, iclass 3, count 0 2006.259.08:18:54.06#ibcon#read 4, iclass 3, count 0 2006.259.08:18:54.06#ibcon#about to read 5, iclass 3, count 0 2006.259.08:18:54.06#ibcon#read 5, iclass 3, count 0 2006.259.08:18:54.06#ibcon#about to read 6, iclass 3, count 0 2006.259.08:18:54.06#ibcon#read 6, iclass 3, count 0 2006.259.08:18:54.06#ibcon#end of sib2, iclass 3, count 0 2006.259.08:18:54.06#ibcon#*after write, iclass 3, count 0 2006.259.08:18:54.06#ibcon#*before return 0, iclass 3, count 0 2006.259.08:18:54.06#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.259.08:18:54.06#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.259.08:18:54.06#ibcon#about to clear, iclass 3 cls_cnt 0 2006.259.08:18:54.06#ibcon#cleared, iclass 3 cls_cnt 0 2006.259.08:18:54.06$vc4f8/vblo=5,744.99 2006.259.08:18:54.06#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.259.08:18:54.06#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.259.08:18:54.06#ibcon#ireg 17 cls_cnt 0 2006.259.08:18:54.06#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.259.08:18:54.06#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.259.08:18:54.06#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.259.08:18:54.06#ibcon#enter wrdev, iclass 5, count 0 2006.259.08:18:54.06#ibcon#first serial, iclass 5, count 0 2006.259.08:18:54.06#ibcon#enter sib2, iclass 5, count 0 2006.259.08:18:54.06#ibcon#flushed, iclass 5, count 0 2006.259.08:18:54.06#ibcon#about to write, iclass 5, count 0 2006.259.08:18:54.06#ibcon#wrote, iclass 5, count 0 2006.259.08:18:54.06#ibcon#about to read 3, iclass 5, count 0 2006.259.08:18:54.08#ibcon#read 3, iclass 5, count 0 2006.259.08:18:54.08#ibcon#about to read 4, iclass 5, count 0 2006.259.08:18:54.08#ibcon#read 4, iclass 5, count 0 2006.259.08:18:54.08#ibcon#about to read 5, iclass 5, count 0 2006.259.08:18:54.08#ibcon#read 5, iclass 5, count 0 2006.259.08:18:54.08#ibcon#about to read 6, iclass 5, count 0 2006.259.08:18:54.08#ibcon#read 6, iclass 5, count 0 2006.259.08:18:54.08#ibcon#end of sib2, iclass 5, count 0 2006.259.08:18:54.08#ibcon#*mode == 0, iclass 5, count 0 2006.259.08:18:54.08#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.259.08:18:54.08#ibcon#[28=FRQ=05,744.99\r\n] 2006.259.08:18:54.08#ibcon#*before write, iclass 5, count 0 2006.259.08:18:54.08#ibcon#enter sib2, iclass 5, count 0 2006.259.08:18:54.08#ibcon#flushed, iclass 5, count 0 2006.259.08:18:54.08#ibcon#about to write, iclass 5, count 0 2006.259.08:18:54.08#ibcon#wrote, iclass 5, count 0 2006.259.08:18:54.08#ibcon#about to read 3, iclass 5, count 0 2006.259.08:18:54.12#ibcon#read 3, iclass 5, count 0 2006.259.08:18:54.12#ibcon#about to read 4, iclass 5, count 0 2006.259.08:18:54.12#ibcon#read 4, iclass 5, count 0 2006.259.08:18:54.12#ibcon#about to read 5, iclass 5, count 0 2006.259.08:18:54.12#ibcon#read 5, iclass 5, count 0 2006.259.08:18:54.12#ibcon#about to read 6, iclass 5, count 0 2006.259.08:18:54.12#ibcon#read 6, iclass 5, count 0 2006.259.08:18:54.12#ibcon#end of sib2, iclass 5, count 0 2006.259.08:18:54.12#ibcon#*after write, iclass 5, count 0 2006.259.08:18:54.12#ibcon#*before return 0, iclass 5, count 0 2006.259.08:18:54.12#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.259.08:18:54.12#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.259.08:18:54.12#ibcon#about to clear, iclass 5 cls_cnt 0 2006.259.08:18:54.12#ibcon#cleared, iclass 5 cls_cnt 0 2006.259.08:18:54.12$vc4f8/vb=5,4 2006.259.08:18:54.12#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.259.08:18:54.12#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.259.08:18:54.12#ibcon#ireg 11 cls_cnt 2 2006.259.08:18:54.12#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.259.08:18:54.18#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.259.08:18:54.18#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.259.08:18:54.18#ibcon#enter wrdev, iclass 7, count 2 2006.259.08:18:54.18#ibcon#first serial, iclass 7, count 2 2006.259.08:18:54.18#ibcon#enter sib2, iclass 7, count 2 2006.259.08:18:54.18#ibcon#flushed, iclass 7, count 2 2006.259.08:18:54.18#ibcon#about to write, iclass 7, count 2 2006.259.08:18:54.18#ibcon#wrote, iclass 7, count 2 2006.259.08:18:54.18#ibcon#about to read 3, iclass 7, count 2 2006.259.08:18:54.20#ibcon#read 3, iclass 7, count 2 2006.259.08:18:54.20#ibcon#about to read 4, iclass 7, count 2 2006.259.08:18:54.20#ibcon#read 4, iclass 7, count 2 2006.259.08:18:54.20#ibcon#about to read 5, iclass 7, count 2 2006.259.08:18:54.20#ibcon#read 5, iclass 7, count 2 2006.259.08:18:54.20#ibcon#about to read 6, iclass 7, count 2 2006.259.08:18:54.20#ibcon#read 6, iclass 7, count 2 2006.259.08:18:54.20#ibcon#end of sib2, iclass 7, count 2 2006.259.08:18:54.20#ibcon#*mode == 0, iclass 7, count 2 2006.259.08:18:54.20#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.259.08:18:54.20#ibcon#[27=AT05-04\r\n] 2006.259.08:18:54.20#ibcon#*before write, iclass 7, count 2 2006.259.08:18:54.20#ibcon#enter sib2, iclass 7, count 2 2006.259.08:18:54.20#ibcon#flushed, iclass 7, count 2 2006.259.08:18:54.20#ibcon#about to write, iclass 7, count 2 2006.259.08:18:54.20#ibcon#wrote, iclass 7, count 2 2006.259.08:18:54.20#ibcon#about to read 3, iclass 7, count 2 2006.259.08:18:54.23#ibcon#read 3, iclass 7, count 2 2006.259.08:18:54.23#ibcon#about to read 4, iclass 7, count 2 2006.259.08:18:54.23#ibcon#read 4, iclass 7, count 2 2006.259.08:18:54.23#ibcon#about to read 5, iclass 7, count 2 2006.259.08:18:54.23#ibcon#read 5, iclass 7, count 2 2006.259.08:18:54.23#ibcon#about to read 6, iclass 7, count 2 2006.259.08:18:54.23#ibcon#read 6, iclass 7, count 2 2006.259.08:18:54.23#ibcon#end of sib2, iclass 7, count 2 2006.259.08:18:54.23#ibcon#*after write, iclass 7, count 2 2006.259.08:18:54.23#ibcon#*before return 0, iclass 7, count 2 2006.259.08:18:54.23#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.259.08:18:54.23#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.259.08:18:54.23#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.259.08:18:54.23#ibcon#ireg 7 cls_cnt 0 2006.259.08:18:54.23#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.259.08:18:54.35#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.259.08:18:54.35#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.259.08:18:54.35#ibcon#enter wrdev, iclass 7, count 0 2006.259.08:18:54.35#ibcon#first serial, iclass 7, count 0 2006.259.08:18:54.35#ibcon#enter sib2, iclass 7, count 0 2006.259.08:18:54.35#ibcon#flushed, iclass 7, count 0 2006.259.08:18:54.35#ibcon#about to write, iclass 7, count 0 2006.259.08:18:54.35#ibcon#wrote, iclass 7, count 0 2006.259.08:18:54.35#ibcon#about to read 3, iclass 7, count 0 2006.259.08:18:54.37#ibcon#read 3, iclass 7, count 0 2006.259.08:18:54.37#ibcon#about to read 4, iclass 7, count 0 2006.259.08:18:54.37#ibcon#read 4, iclass 7, count 0 2006.259.08:18:54.37#ibcon#about to read 5, iclass 7, count 0 2006.259.08:18:54.37#ibcon#read 5, iclass 7, count 0 2006.259.08:18:54.37#ibcon#about to read 6, iclass 7, count 0 2006.259.08:18:54.37#ibcon#read 6, iclass 7, count 0 2006.259.08:18:54.37#ibcon#end of sib2, iclass 7, count 0 2006.259.08:18:54.37#ibcon#*mode == 0, iclass 7, count 0 2006.259.08:18:54.37#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.259.08:18:54.37#ibcon#[27=USB\r\n] 2006.259.08:18:54.37#ibcon#*before write, iclass 7, count 0 2006.259.08:18:54.37#ibcon#enter sib2, iclass 7, count 0 2006.259.08:18:54.37#ibcon#flushed, iclass 7, count 0 2006.259.08:18:54.37#ibcon#about to write, iclass 7, count 0 2006.259.08:18:54.37#ibcon#wrote, iclass 7, count 0 2006.259.08:18:54.37#ibcon#about to read 3, iclass 7, count 0 2006.259.08:18:54.40#ibcon#read 3, iclass 7, count 0 2006.259.08:18:54.40#ibcon#about to read 4, iclass 7, count 0 2006.259.08:18:54.40#ibcon#read 4, iclass 7, count 0 2006.259.08:18:54.40#ibcon#about to read 5, iclass 7, count 0 2006.259.08:18:54.40#ibcon#read 5, iclass 7, count 0 2006.259.08:18:54.40#ibcon#about to read 6, iclass 7, count 0 2006.259.08:18:54.40#ibcon#read 6, iclass 7, count 0 2006.259.08:18:54.40#ibcon#end of sib2, iclass 7, count 0 2006.259.08:18:54.40#ibcon#*after write, iclass 7, count 0 2006.259.08:18:54.40#ibcon#*before return 0, iclass 7, count 0 2006.259.08:18:54.40#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.259.08:18:54.40#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.259.08:18:54.40#ibcon#about to clear, iclass 7 cls_cnt 0 2006.259.08:18:54.40#ibcon#cleared, iclass 7 cls_cnt 0 2006.259.08:18:54.40$vc4f8/vblo=6,752.99 2006.259.08:18:54.40#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.259.08:18:54.40#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.259.08:18:54.40#ibcon#ireg 17 cls_cnt 0 2006.259.08:18:54.40#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.259.08:18:54.40#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.259.08:18:54.40#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.259.08:18:54.40#ibcon#enter wrdev, iclass 11, count 0 2006.259.08:18:54.40#ibcon#first serial, iclass 11, count 0 2006.259.08:18:54.40#ibcon#enter sib2, iclass 11, count 0 2006.259.08:18:54.40#ibcon#flushed, iclass 11, count 0 2006.259.08:18:54.40#ibcon#about to write, iclass 11, count 0 2006.259.08:18:54.40#ibcon#wrote, iclass 11, count 0 2006.259.08:18:54.40#ibcon#about to read 3, iclass 11, count 0 2006.259.08:18:54.42#ibcon#read 3, iclass 11, count 0 2006.259.08:18:54.42#ibcon#about to read 4, iclass 11, count 0 2006.259.08:18:54.42#ibcon#read 4, iclass 11, count 0 2006.259.08:18:54.42#ibcon#about to read 5, iclass 11, count 0 2006.259.08:18:54.42#ibcon#read 5, iclass 11, count 0 2006.259.08:18:54.42#ibcon#about to read 6, iclass 11, count 0 2006.259.08:18:54.42#ibcon#read 6, iclass 11, count 0 2006.259.08:18:54.42#ibcon#end of sib2, iclass 11, count 0 2006.259.08:18:54.42#ibcon#*mode == 0, iclass 11, count 0 2006.259.08:18:54.42#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.259.08:18:54.42#ibcon#[28=FRQ=06,752.99\r\n] 2006.259.08:18:54.42#ibcon#*before write, iclass 11, count 0 2006.259.08:18:54.42#ibcon#enter sib2, iclass 11, count 0 2006.259.08:18:54.42#ibcon#flushed, iclass 11, count 0 2006.259.08:18:54.42#ibcon#about to write, iclass 11, count 0 2006.259.08:18:54.42#ibcon#wrote, iclass 11, count 0 2006.259.08:18:54.42#ibcon#about to read 3, iclass 11, count 0 2006.259.08:18:54.46#ibcon#read 3, iclass 11, count 0 2006.259.08:18:54.46#ibcon#about to read 4, iclass 11, count 0 2006.259.08:18:54.46#ibcon#read 4, iclass 11, count 0 2006.259.08:18:54.46#ibcon#about to read 5, iclass 11, count 0 2006.259.08:18:54.46#ibcon#read 5, iclass 11, count 0 2006.259.08:18:54.46#ibcon#about to read 6, iclass 11, count 0 2006.259.08:18:54.46#ibcon#read 6, iclass 11, count 0 2006.259.08:18:54.46#ibcon#end of sib2, iclass 11, count 0 2006.259.08:18:54.46#ibcon#*after write, iclass 11, count 0 2006.259.08:18:54.46#ibcon#*before return 0, iclass 11, count 0 2006.259.08:18:54.46#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.259.08:18:54.46#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.259.08:18:54.46#ibcon#about to clear, iclass 11 cls_cnt 0 2006.259.08:18:54.46#ibcon#cleared, iclass 11 cls_cnt 0 2006.259.08:18:54.46$vc4f8/vb=6,4 2006.259.08:18:54.46#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.259.08:18:54.46#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.259.08:18:54.46#ibcon#ireg 11 cls_cnt 2 2006.259.08:18:54.46#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.259.08:18:54.52#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.259.08:18:54.52#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.259.08:18:54.52#ibcon#enter wrdev, iclass 13, count 2 2006.259.08:18:54.52#ibcon#first serial, iclass 13, count 2 2006.259.08:18:54.52#ibcon#enter sib2, iclass 13, count 2 2006.259.08:18:54.52#ibcon#flushed, iclass 13, count 2 2006.259.08:18:54.52#ibcon#about to write, iclass 13, count 2 2006.259.08:18:54.52#ibcon#wrote, iclass 13, count 2 2006.259.08:18:54.52#ibcon#about to read 3, iclass 13, count 2 2006.259.08:18:54.54#ibcon#read 3, iclass 13, count 2 2006.259.08:18:54.54#ibcon#about to read 4, iclass 13, count 2 2006.259.08:18:54.54#ibcon#read 4, iclass 13, count 2 2006.259.08:18:54.54#ibcon#about to read 5, iclass 13, count 2 2006.259.08:18:54.54#ibcon#read 5, iclass 13, count 2 2006.259.08:18:54.54#ibcon#about to read 6, iclass 13, count 2 2006.259.08:18:54.54#ibcon#read 6, iclass 13, count 2 2006.259.08:18:54.54#ibcon#end of sib2, iclass 13, count 2 2006.259.08:18:54.54#ibcon#*mode == 0, iclass 13, count 2 2006.259.08:18:54.54#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.259.08:18:54.54#ibcon#[27=AT06-04\r\n] 2006.259.08:18:54.54#ibcon#*before write, iclass 13, count 2 2006.259.08:18:54.54#ibcon#enter sib2, iclass 13, count 2 2006.259.08:18:54.54#ibcon#flushed, iclass 13, count 2 2006.259.08:18:54.54#ibcon#about to write, iclass 13, count 2 2006.259.08:18:54.54#ibcon#wrote, iclass 13, count 2 2006.259.08:18:54.54#ibcon#about to read 3, iclass 13, count 2 2006.259.08:18:54.57#ibcon#read 3, iclass 13, count 2 2006.259.08:18:54.57#ibcon#about to read 4, iclass 13, count 2 2006.259.08:18:54.57#ibcon#read 4, iclass 13, count 2 2006.259.08:18:54.57#ibcon#about to read 5, iclass 13, count 2 2006.259.08:18:54.57#ibcon#read 5, iclass 13, count 2 2006.259.08:18:54.57#ibcon#about to read 6, iclass 13, count 2 2006.259.08:18:54.57#ibcon#read 6, iclass 13, count 2 2006.259.08:18:54.57#ibcon#end of sib2, iclass 13, count 2 2006.259.08:18:54.57#ibcon#*after write, iclass 13, count 2 2006.259.08:18:54.57#ibcon#*before return 0, iclass 13, count 2 2006.259.08:18:54.57#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.259.08:18:54.57#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.259.08:18:54.57#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.259.08:18:54.57#ibcon#ireg 7 cls_cnt 0 2006.259.08:18:54.57#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.259.08:18:54.69#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.259.08:18:54.69#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.259.08:18:54.69#ibcon#enter wrdev, iclass 13, count 0 2006.259.08:18:54.69#ibcon#first serial, iclass 13, count 0 2006.259.08:18:54.69#ibcon#enter sib2, iclass 13, count 0 2006.259.08:18:54.69#ibcon#flushed, iclass 13, count 0 2006.259.08:18:54.69#ibcon#about to write, iclass 13, count 0 2006.259.08:18:54.69#ibcon#wrote, iclass 13, count 0 2006.259.08:18:54.69#ibcon#about to read 3, iclass 13, count 0 2006.259.08:18:54.71#ibcon#read 3, iclass 13, count 0 2006.259.08:18:54.71#ibcon#about to read 4, iclass 13, count 0 2006.259.08:18:54.71#ibcon#read 4, iclass 13, count 0 2006.259.08:18:54.71#ibcon#about to read 5, iclass 13, count 0 2006.259.08:18:54.71#ibcon#read 5, iclass 13, count 0 2006.259.08:18:54.71#ibcon#about to read 6, iclass 13, count 0 2006.259.08:18:54.71#ibcon#read 6, iclass 13, count 0 2006.259.08:18:54.71#ibcon#end of sib2, iclass 13, count 0 2006.259.08:18:54.71#ibcon#*mode == 0, iclass 13, count 0 2006.259.08:18:54.71#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.259.08:18:54.71#ibcon#[27=USB\r\n] 2006.259.08:18:54.71#ibcon#*before write, iclass 13, count 0 2006.259.08:18:54.71#ibcon#enter sib2, iclass 13, count 0 2006.259.08:18:54.71#ibcon#flushed, iclass 13, count 0 2006.259.08:18:54.71#ibcon#about to write, iclass 13, count 0 2006.259.08:18:54.71#ibcon#wrote, iclass 13, count 0 2006.259.08:18:54.71#ibcon#about to read 3, iclass 13, count 0 2006.259.08:18:54.74#ibcon#read 3, iclass 13, count 0 2006.259.08:18:54.74#ibcon#about to read 4, iclass 13, count 0 2006.259.08:18:54.74#ibcon#read 4, iclass 13, count 0 2006.259.08:18:54.74#ibcon#about to read 5, iclass 13, count 0 2006.259.08:18:54.74#ibcon#read 5, iclass 13, count 0 2006.259.08:18:54.74#ibcon#about to read 6, iclass 13, count 0 2006.259.08:18:54.74#ibcon#read 6, iclass 13, count 0 2006.259.08:18:54.74#ibcon#end of sib2, iclass 13, count 0 2006.259.08:18:54.74#ibcon#*after write, iclass 13, count 0 2006.259.08:18:54.74#ibcon#*before return 0, iclass 13, count 0 2006.259.08:18:54.74#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.259.08:18:54.74#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.259.08:18:54.74#ibcon#about to clear, iclass 13 cls_cnt 0 2006.259.08:18:54.74#ibcon#cleared, iclass 13 cls_cnt 0 2006.259.08:18:54.74$vc4f8/vabw=wide 2006.259.08:18:54.74#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.259.08:18:54.74#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.259.08:18:54.74#ibcon#ireg 8 cls_cnt 0 2006.259.08:18:54.74#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.259.08:18:54.74#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.259.08:18:54.74#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.259.08:18:54.74#ibcon#enter wrdev, iclass 15, count 0 2006.259.08:18:54.74#ibcon#first serial, iclass 15, count 0 2006.259.08:18:54.74#ibcon#enter sib2, iclass 15, count 0 2006.259.08:18:54.74#ibcon#flushed, iclass 15, count 0 2006.259.08:18:54.74#ibcon#about to write, iclass 15, count 0 2006.259.08:18:54.74#ibcon#wrote, iclass 15, count 0 2006.259.08:18:54.74#ibcon#about to read 3, iclass 15, count 0 2006.259.08:18:54.76#ibcon#read 3, iclass 15, count 0 2006.259.08:18:54.76#ibcon#about to read 4, iclass 15, count 0 2006.259.08:18:54.76#ibcon#read 4, iclass 15, count 0 2006.259.08:18:54.76#ibcon#about to read 5, iclass 15, count 0 2006.259.08:18:54.76#ibcon#read 5, iclass 15, count 0 2006.259.08:18:54.76#ibcon#about to read 6, iclass 15, count 0 2006.259.08:18:54.76#ibcon#read 6, iclass 15, count 0 2006.259.08:18:54.76#ibcon#end of sib2, iclass 15, count 0 2006.259.08:18:54.76#ibcon#*mode == 0, iclass 15, count 0 2006.259.08:18:54.76#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.259.08:18:54.76#ibcon#[25=BW32\r\n] 2006.259.08:18:54.76#ibcon#*before write, iclass 15, count 0 2006.259.08:18:54.76#ibcon#enter sib2, iclass 15, count 0 2006.259.08:18:54.76#ibcon#flushed, iclass 15, count 0 2006.259.08:18:54.76#ibcon#about to write, iclass 15, count 0 2006.259.08:18:54.76#ibcon#wrote, iclass 15, count 0 2006.259.08:18:54.76#ibcon#about to read 3, iclass 15, count 0 2006.259.08:18:54.79#ibcon#read 3, iclass 15, count 0 2006.259.08:18:54.79#ibcon#about to read 4, iclass 15, count 0 2006.259.08:18:54.79#ibcon#read 4, iclass 15, count 0 2006.259.08:18:54.79#ibcon#about to read 5, iclass 15, count 0 2006.259.08:18:54.79#ibcon#read 5, iclass 15, count 0 2006.259.08:18:54.79#ibcon#about to read 6, iclass 15, count 0 2006.259.08:18:54.79#ibcon#read 6, iclass 15, count 0 2006.259.08:18:54.79#ibcon#end of sib2, iclass 15, count 0 2006.259.08:18:54.79#ibcon#*after write, iclass 15, count 0 2006.259.08:18:54.79#ibcon#*before return 0, iclass 15, count 0 2006.259.08:18:54.79#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.259.08:18:54.79#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.259.08:18:54.79#ibcon#about to clear, iclass 15 cls_cnt 0 2006.259.08:18:54.79#ibcon#cleared, iclass 15 cls_cnt 0 2006.259.08:18:54.79$vc4f8/vbbw=wide 2006.259.08:18:54.79#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.259.08:18:54.79#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.259.08:18:54.79#ibcon#ireg 8 cls_cnt 0 2006.259.08:18:54.79#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.259.08:18:54.86#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.259.08:18:54.86#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.259.08:18:54.86#ibcon#enter wrdev, iclass 17, count 0 2006.259.08:18:54.86#ibcon#first serial, iclass 17, count 0 2006.259.08:18:54.86#ibcon#enter sib2, iclass 17, count 0 2006.259.08:18:54.86#ibcon#flushed, iclass 17, count 0 2006.259.08:18:54.86#ibcon#about to write, iclass 17, count 0 2006.259.08:18:54.86#ibcon#wrote, iclass 17, count 0 2006.259.08:18:54.86#ibcon#about to read 3, iclass 17, count 0 2006.259.08:18:54.88#ibcon#read 3, iclass 17, count 0 2006.259.08:18:54.88#ibcon#about to read 4, iclass 17, count 0 2006.259.08:18:54.88#ibcon#read 4, iclass 17, count 0 2006.259.08:18:54.88#ibcon#about to read 5, iclass 17, count 0 2006.259.08:18:54.88#ibcon#read 5, iclass 17, count 0 2006.259.08:18:54.88#ibcon#about to read 6, iclass 17, count 0 2006.259.08:18:54.88#ibcon#read 6, iclass 17, count 0 2006.259.08:18:54.88#ibcon#end of sib2, iclass 17, count 0 2006.259.08:18:54.88#ibcon#*mode == 0, iclass 17, count 0 2006.259.08:18:54.88#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.259.08:18:54.88#ibcon#[27=BW32\r\n] 2006.259.08:18:54.88#ibcon#*before write, iclass 17, count 0 2006.259.08:18:54.88#ibcon#enter sib2, iclass 17, count 0 2006.259.08:18:54.88#ibcon#flushed, iclass 17, count 0 2006.259.08:18:54.88#ibcon#about to write, iclass 17, count 0 2006.259.08:18:54.88#ibcon#wrote, iclass 17, count 0 2006.259.08:18:54.88#ibcon#about to read 3, iclass 17, count 0 2006.259.08:18:54.91#ibcon#read 3, iclass 17, count 0 2006.259.08:18:54.91#ibcon#about to read 4, iclass 17, count 0 2006.259.08:18:54.91#ibcon#read 4, iclass 17, count 0 2006.259.08:18:54.91#ibcon#about to read 5, iclass 17, count 0 2006.259.08:18:54.91#ibcon#read 5, iclass 17, count 0 2006.259.08:18:54.91#ibcon#about to read 6, iclass 17, count 0 2006.259.08:18:54.91#ibcon#read 6, iclass 17, count 0 2006.259.08:18:54.91#ibcon#end of sib2, iclass 17, count 0 2006.259.08:18:54.91#ibcon#*after write, iclass 17, count 0 2006.259.08:18:54.91#ibcon#*before return 0, iclass 17, count 0 2006.259.08:18:54.91#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.259.08:18:54.91#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.259.08:18:54.91#ibcon#about to clear, iclass 17 cls_cnt 0 2006.259.08:18:54.91#ibcon#cleared, iclass 17 cls_cnt 0 2006.259.08:18:54.91$4f8m12a/ifd4f 2006.259.08:18:54.91$ifd4f/lo= 2006.259.08:18:54.91$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.259.08:18:54.91$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.259.08:18:54.91$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.259.08:18:54.91$ifd4f/patch= 2006.259.08:18:54.91$ifd4f/patch=lo1,a1,a2,a3,a4 2006.259.08:18:54.91$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.259.08:18:54.91$ifd4f/patch=lo3,a5,a6,a7,a8 2006.259.08:18:54.91$4f8m12a/"form=m,16.000,1:2 2006.259.08:18:54.91$4f8m12a/"tpicd 2006.259.08:18:54.91$4f8m12a/echo=off 2006.259.08:18:54.91$4f8m12a/xlog=off 2006.259.08:18:54.91:!2006.259.08:20:20 2006.259.08:19:11.14#trakl#Source acquired 2006.259.08:19:11.14#flagr#flagr/antenna,acquired 2006.259.08:20:20.00:preob 2006.259.08:20:21.14/onsource/TRACKING 2006.259.08:20:21.14:!2006.259.08:20:30 2006.259.08:20:30.00:data_valid=on 2006.259.08:20:30.00:midob 2006.259.08:20:30.14/onsource/TRACKING 2006.259.08:20:30.14/wx/21.79,1013.2,85 2006.259.08:20:30.24/cable/+6.4597E-03 2006.259.08:20:31.33/va/01,08,usb,yes,31,33 2006.259.08:20:31.33/va/02,07,usb,yes,31,33 2006.259.08:20:31.33/va/03,08,usb,yes,24,24 2006.259.08:20:31.33/va/04,07,usb,yes,32,35 2006.259.08:20:31.33/va/05,07,usb,yes,36,38 2006.259.08:20:31.33/va/06,06,usb,yes,35,35 2006.259.08:20:31.33/va/07,06,usb,yes,35,35 2006.259.08:20:31.33/va/08,06,usb,yes,38,37 2006.259.08:20:31.56/valo/01,532.99,yes,locked 2006.259.08:20:31.56/valo/02,572.99,yes,locked 2006.259.08:20:31.56/valo/03,672.99,yes,locked 2006.259.08:20:31.56/valo/04,832.99,yes,locked 2006.259.08:20:31.56/valo/05,652.99,yes,locked 2006.259.08:20:31.56/valo/06,772.99,yes,locked 2006.259.08:20:31.56/valo/07,832.99,yes,locked 2006.259.08:20:31.56/valo/08,852.99,yes,locked 2006.259.08:20:32.65/vb/01,04,usb,yes,31,29 2006.259.08:20:32.65/vb/02,05,usb,yes,29,30 2006.259.08:20:32.65/vb/03,04,usb,yes,29,33 2006.259.08:20:32.65/vb/04,05,usb,yes,26,26 2006.259.08:20:32.65/vb/05,04,usb,yes,28,32 2006.259.08:20:32.65/vb/06,04,usb,yes,29,32 2006.259.08:20:32.65/vb/07,04,usb,yes,31,31 2006.259.08:20:32.65/vb/08,04,usb,yes,29,32 2006.259.08:20:32.88/vblo/01,632.99,yes,locked 2006.259.08:20:32.88/vblo/02,640.99,yes,locked 2006.259.08:20:32.88/vblo/03,656.99,yes,locked 2006.259.08:20:32.88/vblo/04,712.99,yes,locked 2006.259.08:20:32.88/vblo/05,744.99,yes,locked 2006.259.08:20:32.88/vblo/06,752.99,yes,locked 2006.259.08:20:32.88/vblo/07,734.99,yes,locked 2006.259.08:20:32.88/vblo/08,744.99,yes,locked 2006.259.08:20:33.03/vabw/8 2006.259.08:20:33.18/vbbw/8 2006.259.08:20:33.27/xfe/off,on,15.5 2006.259.08:20:33.65/ifatt/23,28,28,28 2006.259.08:20:34.08/fmout-gps/S +4.58E-07 2006.259.08:20:34.12:!2006.259.08:21:50 2006.259.08:21:50.00:data_valid=off 2006.259.08:21:50.00:postob 2006.259.08:21:50.08/cable/+6.4598E-03 2006.259.08:21:50.08/wx/21.76,1013.2,85 2006.259.08:21:51.08/fmout-gps/S +4.57E-07 2006.259.08:21:51.08:scan_name=259-0824,k06259,60 2006.259.08:21:51.08:source=1128+385,113053.28,381518.5,2000.0,ccw 2006.259.08:21:52.14#flagr#flagr/antenna,new-source 2006.259.08:21:52.14:checkk5 2006.259.08:21:52.54/chk_autoobs//k5ts1/ autoobs is running! 2006.259.08:21:52.97/chk_autoobs//k5ts2/ autoobs is running! 2006.259.08:21:53.46/chk_autoobs//k5ts3/ autoobs is running! 2006.259.08:21:53.88/chk_autoobs//k5ts4/ autoobs is running! 2006.259.08:21:54.25/chk_obsdata//k5ts1/T2590820??a.dat file size is correct (nominal:640MB, actual:640MB). 2006.259.08:21:54.65/chk_obsdata//k5ts2/T2590820??b.dat file size is correct (nominal:640MB, actual:640MB). 2006.259.08:21:55.07/chk_obsdata//k5ts3/T2590820??c.dat file size is correct (nominal:640MB, actual:640MB). 2006.259.08:21:55.47/chk_obsdata//k5ts4/T2590820??d.dat file size is correct (nominal:640MB, actual:640MB). 2006.259.08:21:56.51/k5log//k5ts1_log_newline 2006.259.08:21:57.56/k5log//k5ts2_log_newline 2006.259.08:21:58.32/k5log//k5ts3_log_newline 2006.259.08:21:59.11/k5log//k5ts4_log_newline 2006.259.08:21:59.13/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.259.08:21:59.14:4f8m12a=3 2006.259.08:21:59.14$4f8m12a/echo=on 2006.259.08:21:59.14$4f8m12a/pcalon 2006.259.08:21:59.14$pcalon/"no phase cal control is implemented here 2006.259.08:21:59.14$4f8m12a/"tpicd=stop 2006.259.08:21:59.14$4f8m12a/vc4f8 2006.259.08:21:59.14$vc4f8/valo=1,532.99 2006.259.08:21:59.14#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.259.08:21:59.14#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.259.08:21:59.14#ibcon#ireg 17 cls_cnt 0 2006.259.08:21:59.14#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.259.08:21:59.14#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.259.08:21:59.14#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.259.08:21:59.14#ibcon#enter wrdev, iclass 15, count 0 2006.259.08:21:59.14#ibcon#first serial, iclass 15, count 0 2006.259.08:21:59.14#ibcon#enter sib2, iclass 15, count 0 2006.259.08:21:59.14#ibcon#flushed, iclass 15, count 0 2006.259.08:21:59.14#ibcon#about to write, iclass 15, count 0 2006.259.08:21:59.14#ibcon#wrote, iclass 15, count 0 2006.259.08:21:59.14#ibcon#about to read 3, iclass 15, count 0 2006.259.08:21:59.18#ibcon#read 3, iclass 15, count 0 2006.259.08:21:59.18#ibcon#about to read 4, iclass 15, count 0 2006.259.08:21:59.18#ibcon#read 4, iclass 15, count 0 2006.259.08:21:59.18#ibcon#about to read 5, iclass 15, count 0 2006.259.08:21:59.18#ibcon#read 5, iclass 15, count 0 2006.259.08:21:59.18#ibcon#about to read 6, iclass 15, count 0 2006.259.08:21:59.18#ibcon#read 6, iclass 15, count 0 2006.259.08:21:59.18#ibcon#end of sib2, iclass 15, count 0 2006.259.08:21:59.18#ibcon#*mode == 0, iclass 15, count 0 2006.259.08:21:59.18#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.259.08:21:59.18#ibcon#[26=FRQ=01,532.99\r\n] 2006.259.08:21:59.18#ibcon#*before write, iclass 15, count 0 2006.259.08:21:59.18#ibcon#enter sib2, iclass 15, count 0 2006.259.08:21:59.18#ibcon#flushed, iclass 15, count 0 2006.259.08:21:59.18#ibcon#about to write, iclass 15, count 0 2006.259.08:21:59.18#ibcon#wrote, iclass 15, count 0 2006.259.08:21:59.18#ibcon#about to read 3, iclass 15, count 0 2006.259.08:21:59.23#ibcon#read 3, iclass 15, count 0 2006.259.08:21:59.23#ibcon#about to read 4, iclass 15, count 0 2006.259.08:21:59.23#ibcon#read 4, iclass 15, count 0 2006.259.08:21:59.23#ibcon#about to read 5, iclass 15, count 0 2006.259.08:21:59.23#ibcon#read 5, iclass 15, count 0 2006.259.08:21:59.23#ibcon#about to read 6, iclass 15, count 0 2006.259.08:21:59.23#ibcon#read 6, iclass 15, count 0 2006.259.08:21:59.23#ibcon#end of sib2, iclass 15, count 0 2006.259.08:21:59.23#ibcon#*after write, iclass 15, count 0 2006.259.08:21:59.23#ibcon#*before return 0, iclass 15, count 0 2006.259.08:21:59.23#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.259.08:21:59.23#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.259.08:21:59.23#ibcon#about to clear, iclass 15 cls_cnt 0 2006.259.08:21:59.23#ibcon#cleared, iclass 15 cls_cnt 0 2006.259.08:21:59.23$vc4f8/va=1,8 2006.259.08:21:59.23#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.259.08:21:59.23#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.259.08:21:59.23#ibcon#ireg 11 cls_cnt 2 2006.259.08:21:59.23#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.259.08:21:59.23#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.259.08:21:59.23#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.259.08:21:59.23#ibcon#enter wrdev, iclass 17, count 2 2006.259.08:21:59.23#ibcon#first serial, iclass 17, count 2 2006.259.08:21:59.23#ibcon#enter sib2, iclass 17, count 2 2006.259.08:21:59.23#ibcon#flushed, iclass 17, count 2 2006.259.08:21:59.23#ibcon#about to write, iclass 17, count 2 2006.259.08:21:59.23#ibcon#wrote, iclass 17, count 2 2006.259.08:21:59.23#ibcon#about to read 3, iclass 17, count 2 2006.259.08:21:59.25#ibcon#read 3, iclass 17, count 2 2006.259.08:21:59.25#ibcon#about to read 4, iclass 17, count 2 2006.259.08:21:59.25#ibcon#read 4, iclass 17, count 2 2006.259.08:21:59.25#ibcon#about to read 5, iclass 17, count 2 2006.259.08:21:59.25#ibcon#read 5, iclass 17, count 2 2006.259.08:21:59.25#ibcon#about to read 6, iclass 17, count 2 2006.259.08:21:59.25#ibcon#read 6, iclass 17, count 2 2006.259.08:21:59.25#ibcon#end of sib2, iclass 17, count 2 2006.259.08:21:59.25#ibcon#*mode == 0, iclass 17, count 2 2006.259.08:21:59.25#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.259.08:21:59.25#ibcon#[25=AT01-08\r\n] 2006.259.08:21:59.25#ibcon#*before write, iclass 17, count 2 2006.259.08:21:59.25#ibcon#enter sib2, iclass 17, count 2 2006.259.08:21:59.25#ibcon#flushed, iclass 17, count 2 2006.259.08:21:59.25#ibcon#about to write, iclass 17, count 2 2006.259.08:21:59.25#ibcon#wrote, iclass 17, count 2 2006.259.08:21:59.25#ibcon#about to read 3, iclass 17, count 2 2006.259.08:21:59.28#ibcon#read 3, iclass 17, count 2 2006.259.08:21:59.28#ibcon#about to read 4, iclass 17, count 2 2006.259.08:21:59.28#ibcon#read 4, iclass 17, count 2 2006.259.08:21:59.28#ibcon#about to read 5, iclass 17, count 2 2006.259.08:21:59.28#ibcon#read 5, iclass 17, count 2 2006.259.08:21:59.28#ibcon#about to read 6, iclass 17, count 2 2006.259.08:21:59.28#ibcon#read 6, iclass 17, count 2 2006.259.08:21:59.28#ibcon#end of sib2, iclass 17, count 2 2006.259.08:21:59.28#ibcon#*after write, iclass 17, count 2 2006.259.08:21:59.28#ibcon#*before return 0, iclass 17, count 2 2006.259.08:21:59.28#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.259.08:21:59.28#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.259.08:21:59.28#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.259.08:21:59.28#ibcon#ireg 7 cls_cnt 0 2006.259.08:21:59.28#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.259.08:21:59.40#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.259.08:21:59.40#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.259.08:21:59.40#ibcon#enter wrdev, iclass 17, count 0 2006.259.08:21:59.40#ibcon#first serial, iclass 17, count 0 2006.259.08:21:59.40#ibcon#enter sib2, iclass 17, count 0 2006.259.08:21:59.40#ibcon#flushed, iclass 17, count 0 2006.259.08:21:59.40#ibcon#about to write, iclass 17, count 0 2006.259.08:21:59.40#ibcon#wrote, iclass 17, count 0 2006.259.08:21:59.40#ibcon#about to read 3, iclass 17, count 0 2006.259.08:21:59.42#ibcon#read 3, iclass 17, count 0 2006.259.08:21:59.42#ibcon#about to read 4, iclass 17, count 0 2006.259.08:21:59.42#ibcon#read 4, iclass 17, count 0 2006.259.08:21:59.42#ibcon#about to read 5, iclass 17, count 0 2006.259.08:21:59.42#ibcon#read 5, iclass 17, count 0 2006.259.08:21:59.42#ibcon#about to read 6, iclass 17, count 0 2006.259.08:21:59.42#ibcon#read 6, iclass 17, count 0 2006.259.08:21:59.42#ibcon#end of sib2, iclass 17, count 0 2006.259.08:21:59.42#ibcon#*mode == 0, iclass 17, count 0 2006.259.08:21:59.42#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.259.08:21:59.42#ibcon#[25=USB\r\n] 2006.259.08:21:59.42#ibcon#*before write, iclass 17, count 0 2006.259.08:21:59.42#ibcon#enter sib2, iclass 17, count 0 2006.259.08:21:59.42#ibcon#flushed, iclass 17, count 0 2006.259.08:21:59.42#ibcon#about to write, iclass 17, count 0 2006.259.08:21:59.42#ibcon#wrote, iclass 17, count 0 2006.259.08:21:59.42#ibcon#about to read 3, iclass 17, count 0 2006.259.08:21:59.45#ibcon#read 3, iclass 17, count 0 2006.259.08:21:59.45#ibcon#about to read 4, iclass 17, count 0 2006.259.08:21:59.45#ibcon#read 4, iclass 17, count 0 2006.259.08:21:59.45#ibcon#about to read 5, iclass 17, count 0 2006.259.08:21:59.45#ibcon#read 5, iclass 17, count 0 2006.259.08:21:59.45#ibcon#about to read 6, iclass 17, count 0 2006.259.08:21:59.45#ibcon#read 6, iclass 17, count 0 2006.259.08:21:59.45#ibcon#end of sib2, iclass 17, count 0 2006.259.08:21:59.45#ibcon#*after write, iclass 17, count 0 2006.259.08:21:59.45#ibcon#*before return 0, iclass 17, count 0 2006.259.08:21:59.45#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.259.08:21:59.45#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.259.08:21:59.45#ibcon#about to clear, iclass 17 cls_cnt 0 2006.259.08:21:59.45#ibcon#cleared, iclass 17 cls_cnt 0 2006.259.08:21:59.45$vc4f8/valo=2,572.99 2006.259.08:21:59.45#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.259.08:21:59.45#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.259.08:21:59.45#ibcon#ireg 17 cls_cnt 0 2006.259.08:21:59.45#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.259.08:21:59.45#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.259.08:21:59.45#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.259.08:21:59.45#ibcon#enter wrdev, iclass 19, count 0 2006.259.08:21:59.45#ibcon#first serial, iclass 19, count 0 2006.259.08:21:59.45#ibcon#enter sib2, iclass 19, count 0 2006.259.08:21:59.45#ibcon#flushed, iclass 19, count 0 2006.259.08:21:59.45#ibcon#about to write, iclass 19, count 0 2006.259.08:21:59.45#ibcon#wrote, iclass 19, count 0 2006.259.08:21:59.45#ibcon#about to read 3, iclass 19, count 0 2006.259.08:21:59.47#ibcon#read 3, iclass 19, count 0 2006.259.08:21:59.47#ibcon#about to read 4, iclass 19, count 0 2006.259.08:21:59.47#ibcon#read 4, iclass 19, count 0 2006.259.08:21:59.47#ibcon#about to read 5, iclass 19, count 0 2006.259.08:21:59.47#ibcon#read 5, iclass 19, count 0 2006.259.08:21:59.47#ibcon#about to read 6, iclass 19, count 0 2006.259.08:21:59.47#ibcon#read 6, iclass 19, count 0 2006.259.08:21:59.47#ibcon#end of sib2, iclass 19, count 0 2006.259.08:21:59.47#ibcon#*mode == 0, iclass 19, count 0 2006.259.08:21:59.47#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.259.08:21:59.47#ibcon#[26=FRQ=02,572.99\r\n] 2006.259.08:21:59.47#ibcon#*before write, iclass 19, count 0 2006.259.08:21:59.47#ibcon#enter sib2, iclass 19, count 0 2006.259.08:21:59.47#ibcon#flushed, iclass 19, count 0 2006.259.08:21:59.47#ibcon#about to write, iclass 19, count 0 2006.259.08:21:59.47#ibcon#wrote, iclass 19, count 0 2006.259.08:21:59.47#ibcon#about to read 3, iclass 19, count 0 2006.259.08:21:59.51#ibcon#read 3, iclass 19, count 0 2006.259.08:21:59.51#ibcon#about to read 4, iclass 19, count 0 2006.259.08:21:59.51#ibcon#read 4, iclass 19, count 0 2006.259.08:21:59.51#ibcon#about to read 5, iclass 19, count 0 2006.259.08:21:59.51#ibcon#read 5, iclass 19, count 0 2006.259.08:21:59.51#ibcon#about to read 6, iclass 19, count 0 2006.259.08:21:59.51#ibcon#read 6, iclass 19, count 0 2006.259.08:21:59.51#ibcon#end of sib2, iclass 19, count 0 2006.259.08:21:59.51#ibcon#*after write, iclass 19, count 0 2006.259.08:21:59.51#ibcon#*before return 0, iclass 19, count 0 2006.259.08:21:59.51#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.259.08:21:59.51#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.259.08:21:59.51#ibcon#about to clear, iclass 19 cls_cnt 0 2006.259.08:21:59.51#ibcon#cleared, iclass 19 cls_cnt 0 2006.259.08:21:59.51$vc4f8/va=2,7 2006.259.08:21:59.51#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.259.08:21:59.51#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.259.08:21:59.51#ibcon#ireg 11 cls_cnt 2 2006.259.08:21:59.51#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.259.08:21:59.57#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.259.08:21:59.57#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.259.08:21:59.57#ibcon#enter wrdev, iclass 21, count 2 2006.259.08:21:59.57#ibcon#first serial, iclass 21, count 2 2006.259.08:21:59.57#ibcon#enter sib2, iclass 21, count 2 2006.259.08:21:59.57#ibcon#flushed, iclass 21, count 2 2006.259.08:21:59.57#ibcon#about to write, iclass 21, count 2 2006.259.08:21:59.57#ibcon#wrote, iclass 21, count 2 2006.259.08:21:59.57#ibcon#about to read 3, iclass 21, count 2 2006.259.08:21:59.59#ibcon#read 3, iclass 21, count 2 2006.259.08:21:59.59#ibcon#about to read 4, iclass 21, count 2 2006.259.08:21:59.59#ibcon#read 4, iclass 21, count 2 2006.259.08:21:59.59#ibcon#about to read 5, iclass 21, count 2 2006.259.08:21:59.59#ibcon#read 5, iclass 21, count 2 2006.259.08:21:59.59#ibcon#about to read 6, iclass 21, count 2 2006.259.08:21:59.59#ibcon#read 6, iclass 21, count 2 2006.259.08:21:59.59#ibcon#end of sib2, iclass 21, count 2 2006.259.08:21:59.59#ibcon#*mode == 0, iclass 21, count 2 2006.259.08:21:59.59#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.259.08:21:59.59#ibcon#[25=AT02-07\r\n] 2006.259.08:21:59.59#ibcon#*before write, iclass 21, count 2 2006.259.08:21:59.59#ibcon#enter sib2, iclass 21, count 2 2006.259.08:21:59.59#ibcon#flushed, iclass 21, count 2 2006.259.08:21:59.59#ibcon#about to write, iclass 21, count 2 2006.259.08:21:59.59#ibcon#wrote, iclass 21, count 2 2006.259.08:21:59.59#ibcon#about to read 3, iclass 21, count 2 2006.259.08:21:59.63#ibcon#read 3, iclass 21, count 2 2006.259.08:21:59.63#ibcon#about to read 4, iclass 21, count 2 2006.259.08:21:59.63#ibcon#read 4, iclass 21, count 2 2006.259.08:21:59.63#ibcon#about to read 5, iclass 21, count 2 2006.259.08:21:59.63#ibcon#read 5, iclass 21, count 2 2006.259.08:21:59.63#ibcon#about to read 6, iclass 21, count 2 2006.259.08:21:59.63#ibcon#read 6, iclass 21, count 2 2006.259.08:21:59.63#ibcon#end of sib2, iclass 21, count 2 2006.259.08:21:59.63#ibcon#*after write, iclass 21, count 2 2006.259.08:21:59.63#ibcon#*before return 0, iclass 21, count 2 2006.259.08:21:59.63#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.259.08:21:59.63#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.259.08:21:59.63#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.259.08:21:59.63#ibcon#ireg 7 cls_cnt 0 2006.259.08:21:59.63#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.259.08:21:59.75#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.259.08:21:59.75#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.259.08:21:59.75#ibcon#enter wrdev, iclass 21, count 0 2006.259.08:21:59.75#ibcon#first serial, iclass 21, count 0 2006.259.08:21:59.75#ibcon#enter sib2, iclass 21, count 0 2006.259.08:21:59.75#ibcon#flushed, iclass 21, count 0 2006.259.08:21:59.75#ibcon#about to write, iclass 21, count 0 2006.259.08:21:59.75#ibcon#wrote, iclass 21, count 0 2006.259.08:21:59.75#ibcon#about to read 3, iclass 21, count 0 2006.259.08:21:59.77#ibcon#read 3, iclass 21, count 0 2006.259.08:21:59.77#ibcon#about to read 4, iclass 21, count 0 2006.259.08:21:59.77#ibcon#read 4, iclass 21, count 0 2006.259.08:21:59.77#ibcon#about to read 5, iclass 21, count 0 2006.259.08:21:59.77#ibcon#read 5, iclass 21, count 0 2006.259.08:21:59.77#ibcon#about to read 6, iclass 21, count 0 2006.259.08:21:59.77#ibcon#read 6, iclass 21, count 0 2006.259.08:21:59.77#ibcon#end of sib2, iclass 21, count 0 2006.259.08:21:59.77#ibcon#*mode == 0, iclass 21, count 0 2006.259.08:21:59.77#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.259.08:21:59.77#ibcon#[25=USB\r\n] 2006.259.08:21:59.77#ibcon#*before write, iclass 21, count 0 2006.259.08:21:59.77#ibcon#enter sib2, iclass 21, count 0 2006.259.08:21:59.77#ibcon#flushed, iclass 21, count 0 2006.259.08:21:59.77#ibcon#about to write, iclass 21, count 0 2006.259.08:21:59.77#ibcon#wrote, iclass 21, count 0 2006.259.08:21:59.77#ibcon#about to read 3, iclass 21, count 0 2006.259.08:21:59.80#ibcon#read 3, iclass 21, count 0 2006.259.08:21:59.80#ibcon#about to read 4, iclass 21, count 0 2006.259.08:21:59.80#ibcon#read 4, iclass 21, count 0 2006.259.08:21:59.80#ibcon#about to read 5, iclass 21, count 0 2006.259.08:21:59.80#ibcon#read 5, iclass 21, count 0 2006.259.08:21:59.80#ibcon#about to read 6, iclass 21, count 0 2006.259.08:21:59.80#ibcon#read 6, iclass 21, count 0 2006.259.08:21:59.80#ibcon#end of sib2, iclass 21, count 0 2006.259.08:21:59.80#ibcon#*after write, iclass 21, count 0 2006.259.08:21:59.80#ibcon#*before return 0, iclass 21, count 0 2006.259.08:21:59.80#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.259.08:21:59.80#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.259.08:21:59.80#ibcon#about to clear, iclass 21 cls_cnt 0 2006.259.08:21:59.80#ibcon#cleared, iclass 21 cls_cnt 0 2006.259.08:21:59.80$vc4f8/valo=3,672.99 2006.259.08:21:59.80#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.259.08:21:59.80#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.259.08:21:59.80#ibcon#ireg 17 cls_cnt 0 2006.259.08:21:59.80#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.259.08:21:59.80#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.259.08:21:59.80#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.259.08:21:59.80#ibcon#enter wrdev, iclass 23, count 0 2006.259.08:21:59.80#ibcon#first serial, iclass 23, count 0 2006.259.08:21:59.80#ibcon#enter sib2, iclass 23, count 0 2006.259.08:21:59.80#ibcon#flushed, iclass 23, count 0 2006.259.08:21:59.80#ibcon#about to write, iclass 23, count 0 2006.259.08:21:59.80#ibcon#wrote, iclass 23, count 0 2006.259.08:21:59.80#ibcon#about to read 3, iclass 23, count 0 2006.259.08:21:59.82#ibcon#read 3, iclass 23, count 0 2006.259.08:21:59.82#ibcon#about to read 4, iclass 23, count 0 2006.259.08:21:59.82#ibcon#read 4, iclass 23, count 0 2006.259.08:21:59.82#ibcon#about to read 5, iclass 23, count 0 2006.259.08:21:59.82#ibcon#read 5, iclass 23, count 0 2006.259.08:21:59.82#ibcon#about to read 6, iclass 23, count 0 2006.259.08:21:59.82#ibcon#read 6, iclass 23, count 0 2006.259.08:21:59.82#ibcon#end of sib2, iclass 23, count 0 2006.259.08:21:59.82#ibcon#*mode == 0, iclass 23, count 0 2006.259.08:21:59.82#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.259.08:21:59.82#ibcon#[26=FRQ=03,672.99\r\n] 2006.259.08:21:59.82#ibcon#*before write, iclass 23, count 0 2006.259.08:21:59.82#ibcon#enter sib2, iclass 23, count 0 2006.259.08:21:59.82#ibcon#flushed, iclass 23, count 0 2006.259.08:21:59.82#ibcon#about to write, iclass 23, count 0 2006.259.08:21:59.82#ibcon#wrote, iclass 23, count 0 2006.259.08:21:59.82#ibcon#about to read 3, iclass 23, count 0 2006.259.08:21:59.86#ibcon#read 3, iclass 23, count 0 2006.259.08:21:59.86#ibcon#about to read 4, iclass 23, count 0 2006.259.08:21:59.86#ibcon#read 4, iclass 23, count 0 2006.259.08:21:59.86#ibcon#about to read 5, iclass 23, count 0 2006.259.08:21:59.86#ibcon#read 5, iclass 23, count 0 2006.259.08:21:59.86#ibcon#about to read 6, iclass 23, count 0 2006.259.08:21:59.86#ibcon#read 6, iclass 23, count 0 2006.259.08:21:59.86#ibcon#end of sib2, iclass 23, count 0 2006.259.08:21:59.86#ibcon#*after write, iclass 23, count 0 2006.259.08:21:59.86#ibcon#*before return 0, iclass 23, count 0 2006.259.08:21:59.86#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.259.08:21:59.86#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.259.08:21:59.86#ibcon#about to clear, iclass 23 cls_cnt 0 2006.259.08:21:59.86#ibcon#cleared, iclass 23 cls_cnt 0 2006.259.08:21:59.86$vc4f8/va=3,8 2006.259.08:21:59.86#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.259.08:21:59.86#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.259.08:21:59.86#ibcon#ireg 11 cls_cnt 2 2006.259.08:21:59.86#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.259.08:21:59.92#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.259.08:21:59.92#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.259.08:21:59.92#ibcon#enter wrdev, iclass 25, count 2 2006.259.08:21:59.92#ibcon#first serial, iclass 25, count 2 2006.259.08:21:59.92#ibcon#enter sib2, iclass 25, count 2 2006.259.08:21:59.92#ibcon#flushed, iclass 25, count 2 2006.259.08:21:59.92#ibcon#about to write, iclass 25, count 2 2006.259.08:21:59.92#ibcon#wrote, iclass 25, count 2 2006.259.08:21:59.92#ibcon#about to read 3, iclass 25, count 2 2006.259.08:21:59.94#ibcon#read 3, iclass 25, count 2 2006.259.08:21:59.94#ibcon#about to read 4, iclass 25, count 2 2006.259.08:21:59.94#ibcon#read 4, iclass 25, count 2 2006.259.08:21:59.94#ibcon#about to read 5, iclass 25, count 2 2006.259.08:21:59.94#ibcon#read 5, iclass 25, count 2 2006.259.08:21:59.94#ibcon#about to read 6, iclass 25, count 2 2006.259.08:21:59.94#ibcon#read 6, iclass 25, count 2 2006.259.08:21:59.94#ibcon#end of sib2, iclass 25, count 2 2006.259.08:21:59.94#ibcon#*mode == 0, iclass 25, count 2 2006.259.08:21:59.94#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.259.08:21:59.94#ibcon#[25=AT03-08\r\n] 2006.259.08:21:59.94#ibcon#*before write, iclass 25, count 2 2006.259.08:21:59.94#ibcon#enter sib2, iclass 25, count 2 2006.259.08:21:59.94#ibcon#flushed, iclass 25, count 2 2006.259.08:21:59.94#ibcon#about to write, iclass 25, count 2 2006.259.08:21:59.94#ibcon#wrote, iclass 25, count 2 2006.259.08:21:59.94#ibcon#about to read 3, iclass 25, count 2 2006.259.08:21:59.98#ibcon#read 3, iclass 25, count 2 2006.259.08:21:59.98#ibcon#about to read 4, iclass 25, count 2 2006.259.08:21:59.98#ibcon#read 4, iclass 25, count 2 2006.259.08:21:59.98#ibcon#about to read 5, iclass 25, count 2 2006.259.08:21:59.98#ibcon#read 5, iclass 25, count 2 2006.259.08:21:59.98#ibcon#about to read 6, iclass 25, count 2 2006.259.08:21:59.98#ibcon#read 6, iclass 25, count 2 2006.259.08:21:59.98#ibcon#end of sib2, iclass 25, count 2 2006.259.08:21:59.98#ibcon#*after write, iclass 25, count 2 2006.259.08:21:59.98#ibcon#*before return 0, iclass 25, count 2 2006.259.08:21:59.98#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.259.08:21:59.98#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.259.08:21:59.98#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.259.08:21:59.98#ibcon#ireg 7 cls_cnt 0 2006.259.08:21:59.98#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.259.08:22:00.10#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.259.08:22:00.10#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.259.08:22:00.10#ibcon#enter wrdev, iclass 25, count 0 2006.259.08:22:00.10#ibcon#first serial, iclass 25, count 0 2006.259.08:22:00.10#ibcon#enter sib2, iclass 25, count 0 2006.259.08:22:00.10#ibcon#flushed, iclass 25, count 0 2006.259.08:22:00.10#ibcon#about to write, iclass 25, count 0 2006.259.08:22:00.10#ibcon#wrote, iclass 25, count 0 2006.259.08:22:00.10#ibcon#about to read 3, iclass 25, count 0 2006.259.08:22:00.12#ibcon#read 3, iclass 25, count 0 2006.259.08:22:00.12#ibcon#about to read 4, iclass 25, count 0 2006.259.08:22:00.12#ibcon#read 4, iclass 25, count 0 2006.259.08:22:00.12#ibcon#about to read 5, iclass 25, count 0 2006.259.08:22:00.12#ibcon#read 5, iclass 25, count 0 2006.259.08:22:00.12#ibcon#about to read 6, iclass 25, count 0 2006.259.08:22:00.12#ibcon#read 6, iclass 25, count 0 2006.259.08:22:00.12#ibcon#end of sib2, iclass 25, count 0 2006.259.08:22:00.12#ibcon#*mode == 0, iclass 25, count 0 2006.259.08:22:00.12#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.259.08:22:00.12#ibcon#[25=USB\r\n] 2006.259.08:22:00.12#ibcon#*before write, iclass 25, count 0 2006.259.08:22:00.12#ibcon#enter sib2, iclass 25, count 0 2006.259.08:22:00.12#ibcon#flushed, iclass 25, count 0 2006.259.08:22:00.12#ibcon#about to write, iclass 25, count 0 2006.259.08:22:00.12#ibcon#wrote, iclass 25, count 0 2006.259.08:22:00.12#ibcon#about to read 3, iclass 25, count 0 2006.259.08:22:00.15#ibcon#read 3, iclass 25, count 0 2006.259.08:22:00.15#ibcon#about to read 4, iclass 25, count 0 2006.259.08:22:00.15#ibcon#read 4, iclass 25, count 0 2006.259.08:22:00.15#ibcon#about to read 5, iclass 25, count 0 2006.259.08:22:00.15#ibcon#read 5, iclass 25, count 0 2006.259.08:22:00.15#ibcon#about to read 6, iclass 25, count 0 2006.259.08:22:00.15#ibcon#read 6, iclass 25, count 0 2006.259.08:22:00.15#ibcon#end of sib2, iclass 25, count 0 2006.259.08:22:00.15#ibcon#*after write, iclass 25, count 0 2006.259.08:22:00.15#ibcon#*before return 0, iclass 25, count 0 2006.259.08:22:00.15#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.259.08:22:00.15#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.259.08:22:00.15#ibcon#about to clear, iclass 25 cls_cnt 0 2006.259.08:22:00.15#ibcon#cleared, iclass 25 cls_cnt 0 2006.259.08:22:00.15$vc4f8/valo=4,832.99 2006.259.08:22:00.15#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.259.08:22:00.15#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.259.08:22:00.15#ibcon#ireg 17 cls_cnt 0 2006.259.08:22:00.15#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.259.08:22:00.15#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.259.08:22:00.15#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.259.08:22:00.15#ibcon#enter wrdev, iclass 27, count 0 2006.259.08:22:00.15#ibcon#first serial, iclass 27, count 0 2006.259.08:22:00.15#ibcon#enter sib2, iclass 27, count 0 2006.259.08:22:00.15#ibcon#flushed, iclass 27, count 0 2006.259.08:22:00.15#ibcon#about to write, iclass 27, count 0 2006.259.08:22:00.15#ibcon#wrote, iclass 27, count 0 2006.259.08:22:00.15#ibcon#about to read 3, iclass 27, count 0 2006.259.08:22:00.17#ibcon#read 3, iclass 27, count 0 2006.259.08:22:00.17#ibcon#about to read 4, iclass 27, count 0 2006.259.08:22:00.17#ibcon#read 4, iclass 27, count 0 2006.259.08:22:00.17#ibcon#about to read 5, iclass 27, count 0 2006.259.08:22:00.17#ibcon#read 5, iclass 27, count 0 2006.259.08:22:00.17#ibcon#about to read 6, iclass 27, count 0 2006.259.08:22:00.17#ibcon#read 6, iclass 27, count 0 2006.259.08:22:00.17#ibcon#end of sib2, iclass 27, count 0 2006.259.08:22:00.17#ibcon#*mode == 0, iclass 27, count 0 2006.259.08:22:00.17#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.259.08:22:00.17#ibcon#[26=FRQ=04,832.99\r\n] 2006.259.08:22:00.17#ibcon#*before write, iclass 27, count 0 2006.259.08:22:00.17#ibcon#enter sib2, iclass 27, count 0 2006.259.08:22:00.17#ibcon#flushed, iclass 27, count 0 2006.259.08:22:00.17#ibcon#about to write, iclass 27, count 0 2006.259.08:22:00.17#ibcon#wrote, iclass 27, count 0 2006.259.08:22:00.17#ibcon#about to read 3, iclass 27, count 0 2006.259.08:22:00.21#ibcon#read 3, iclass 27, count 0 2006.259.08:22:00.21#ibcon#about to read 4, iclass 27, count 0 2006.259.08:22:00.21#ibcon#read 4, iclass 27, count 0 2006.259.08:22:00.21#ibcon#about to read 5, iclass 27, count 0 2006.259.08:22:00.21#ibcon#read 5, iclass 27, count 0 2006.259.08:22:00.21#ibcon#about to read 6, iclass 27, count 0 2006.259.08:22:00.21#ibcon#read 6, iclass 27, count 0 2006.259.08:22:00.21#ibcon#end of sib2, iclass 27, count 0 2006.259.08:22:00.21#ibcon#*after write, iclass 27, count 0 2006.259.08:22:00.21#ibcon#*before return 0, iclass 27, count 0 2006.259.08:22:00.21#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.259.08:22:00.21#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.259.08:22:00.21#ibcon#about to clear, iclass 27 cls_cnt 0 2006.259.08:22:00.21#ibcon#cleared, iclass 27 cls_cnt 0 2006.259.08:22:00.21$vc4f8/va=4,7 2006.259.08:22:00.21#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.259.08:22:00.21#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.259.08:22:00.21#ibcon#ireg 11 cls_cnt 2 2006.259.08:22:00.21#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.259.08:22:00.27#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.259.08:22:00.27#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.259.08:22:00.27#ibcon#enter wrdev, iclass 29, count 2 2006.259.08:22:00.27#ibcon#first serial, iclass 29, count 2 2006.259.08:22:00.27#ibcon#enter sib2, iclass 29, count 2 2006.259.08:22:00.27#ibcon#flushed, iclass 29, count 2 2006.259.08:22:00.27#ibcon#about to write, iclass 29, count 2 2006.259.08:22:00.27#ibcon#wrote, iclass 29, count 2 2006.259.08:22:00.27#ibcon#about to read 3, iclass 29, count 2 2006.259.08:22:00.29#ibcon#read 3, iclass 29, count 2 2006.259.08:22:00.29#ibcon#about to read 4, iclass 29, count 2 2006.259.08:22:00.29#ibcon#read 4, iclass 29, count 2 2006.259.08:22:00.29#ibcon#about to read 5, iclass 29, count 2 2006.259.08:22:00.29#ibcon#read 5, iclass 29, count 2 2006.259.08:22:00.29#ibcon#about to read 6, iclass 29, count 2 2006.259.08:22:00.29#ibcon#read 6, iclass 29, count 2 2006.259.08:22:00.29#ibcon#end of sib2, iclass 29, count 2 2006.259.08:22:00.29#ibcon#*mode == 0, iclass 29, count 2 2006.259.08:22:00.29#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.259.08:22:00.29#ibcon#[25=AT04-07\r\n] 2006.259.08:22:00.29#ibcon#*before write, iclass 29, count 2 2006.259.08:22:00.29#ibcon#enter sib2, iclass 29, count 2 2006.259.08:22:00.29#ibcon#flushed, iclass 29, count 2 2006.259.08:22:00.29#ibcon#about to write, iclass 29, count 2 2006.259.08:22:00.29#ibcon#wrote, iclass 29, count 2 2006.259.08:22:00.29#ibcon#about to read 3, iclass 29, count 2 2006.259.08:22:00.32#ibcon#read 3, iclass 29, count 2 2006.259.08:22:00.32#ibcon#about to read 4, iclass 29, count 2 2006.259.08:22:00.32#ibcon#read 4, iclass 29, count 2 2006.259.08:22:00.32#ibcon#about to read 5, iclass 29, count 2 2006.259.08:22:00.32#ibcon#read 5, iclass 29, count 2 2006.259.08:22:00.32#ibcon#about to read 6, iclass 29, count 2 2006.259.08:22:00.32#ibcon#read 6, iclass 29, count 2 2006.259.08:22:00.32#ibcon#end of sib2, iclass 29, count 2 2006.259.08:22:00.32#ibcon#*after write, iclass 29, count 2 2006.259.08:22:00.32#ibcon#*before return 0, iclass 29, count 2 2006.259.08:22:00.32#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.259.08:22:00.32#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.259.08:22:00.32#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.259.08:22:00.32#ibcon#ireg 7 cls_cnt 0 2006.259.08:22:00.32#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.259.08:22:00.44#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.259.08:22:00.44#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.259.08:22:00.44#ibcon#enter wrdev, iclass 29, count 0 2006.259.08:22:00.44#ibcon#first serial, iclass 29, count 0 2006.259.08:22:00.44#ibcon#enter sib2, iclass 29, count 0 2006.259.08:22:00.44#ibcon#flushed, iclass 29, count 0 2006.259.08:22:00.44#ibcon#about to write, iclass 29, count 0 2006.259.08:22:00.44#ibcon#wrote, iclass 29, count 0 2006.259.08:22:00.44#ibcon#about to read 3, iclass 29, count 0 2006.259.08:22:00.46#ibcon#read 3, iclass 29, count 0 2006.259.08:22:00.46#ibcon#about to read 4, iclass 29, count 0 2006.259.08:22:00.46#ibcon#read 4, iclass 29, count 0 2006.259.08:22:00.46#ibcon#about to read 5, iclass 29, count 0 2006.259.08:22:00.46#ibcon#read 5, iclass 29, count 0 2006.259.08:22:00.46#ibcon#about to read 6, iclass 29, count 0 2006.259.08:22:00.46#ibcon#read 6, iclass 29, count 0 2006.259.08:22:00.46#ibcon#end of sib2, iclass 29, count 0 2006.259.08:22:00.46#ibcon#*mode == 0, iclass 29, count 0 2006.259.08:22:00.46#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.259.08:22:00.46#ibcon#[25=USB\r\n] 2006.259.08:22:00.46#ibcon#*before write, iclass 29, count 0 2006.259.08:22:00.46#ibcon#enter sib2, iclass 29, count 0 2006.259.08:22:00.46#ibcon#flushed, iclass 29, count 0 2006.259.08:22:00.46#ibcon#about to write, iclass 29, count 0 2006.259.08:22:00.46#ibcon#wrote, iclass 29, count 0 2006.259.08:22:00.46#ibcon#about to read 3, iclass 29, count 0 2006.259.08:22:00.49#ibcon#read 3, iclass 29, count 0 2006.259.08:22:00.49#ibcon#about to read 4, iclass 29, count 0 2006.259.08:22:00.49#ibcon#read 4, iclass 29, count 0 2006.259.08:22:00.49#ibcon#about to read 5, iclass 29, count 0 2006.259.08:22:00.49#ibcon#read 5, iclass 29, count 0 2006.259.08:22:00.49#ibcon#about to read 6, iclass 29, count 0 2006.259.08:22:00.49#ibcon#read 6, iclass 29, count 0 2006.259.08:22:00.49#ibcon#end of sib2, iclass 29, count 0 2006.259.08:22:00.49#ibcon#*after write, iclass 29, count 0 2006.259.08:22:00.49#ibcon#*before return 0, iclass 29, count 0 2006.259.08:22:00.49#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.259.08:22:00.49#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.259.08:22:00.49#ibcon#about to clear, iclass 29 cls_cnt 0 2006.259.08:22:00.49#ibcon#cleared, iclass 29 cls_cnt 0 2006.259.08:22:00.49$vc4f8/valo=5,652.99 2006.259.08:22:00.49#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.259.08:22:00.49#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.259.08:22:00.49#ibcon#ireg 17 cls_cnt 0 2006.259.08:22:00.49#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.259.08:22:00.49#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.259.08:22:00.49#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.259.08:22:00.49#ibcon#enter wrdev, iclass 31, count 0 2006.259.08:22:00.49#ibcon#first serial, iclass 31, count 0 2006.259.08:22:00.49#ibcon#enter sib2, iclass 31, count 0 2006.259.08:22:00.49#ibcon#flushed, iclass 31, count 0 2006.259.08:22:00.49#ibcon#about to write, iclass 31, count 0 2006.259.08:22:00.49#ibcon#wrote, iclass 31, count 0 2006.259.08:22:00.49#ibcon#about to read 3, iclass 31, count 0 2006.259.08:22:00.51#ibcon#read 3, iclass 31, count 0 2006.259.08:22:00.51#ibcon#about to read 4, iclass 31, count 0 2006.259.08:22:00.51#ibcon#read 4, iclass 31, count 0 2006.259.08:22:00.51#ibcon#about to read 5, iclass 31, count 0 2006.259.08:22:00.51#ibcon#read 5, iclass 31, count 0 2006.259.08:22:00.51#ibcon#about to read 6, iclass 31, count 0 2006.259.08:22:00.51#ibcon#read 6, iclass 31, count 0 2006.259.08:22:00.51#ibcon#end of sib2, iclass 31, count 0 2006.259.08:22:00.51#ibcon#*mode == 0, iclass 31, count 0 2006.259.08:22:00.51#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.259.08:22:00.51#ibcon#[26=FRQ=05,652.99\r\n] 2006.259.08:22:00.51#ibcon#*before write, iclass 31, count 0 2006.259.08:22:00.51#ibcon#enter sib2, iclass 31, count 0 2006.259.08:22:00.51#ibcon#flushed, iclass 31, count 0 2006.259.08:22:00.51#ibcon#about to write, iclass 31, count 0 2006.259.08:22:00.51#ibcon#wrote, iclass 31, count 0 2006.259.08:22:00.51#ibcon#about to read 3, iclass 31, count 0 2006.259.08:22:00.55#ibcon#read 3, iclass 31, count 0 2006.259.08:22:00.55#ibcon#about to read 4, iclass 31, count 0 2006.259.08:22:00.55#ibcon#read 4, iclass 31, count 0 2006.259.08:22:00.55#ibcon#about to read 5, iclass 31, count 0 2006.259.08:22:00.55#ibcon#read 5, iclass 31, count 0 2006.259.08:22:00.55#ibcon#about to read 6, iclass 31, count 0 2006.259.08:22:00.55#ibcon#read 6, iclass 31, count 0 2006.259.08:22:00.55#ibcon#end of sib2, iclass 31, count 0 2006.259.08:22:00.55#ibcon#*after write, iclass 31, count 0 2006.259.08:22:00.55#ibcon#*before return 0, iclass 31, count 0 2006.259.08:22:00.55#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.259.08:22:00.55#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.259.08:22:00.55#ibcon#about to clear, iclass 31 cls_cnt 0 2006.259.08:22:00.55#ibcon#cleared, iclass 31 cls_cnt 0 2006.259.08:22:00.55$vc4f8/va=5,7 2006.259.08:22:00.55#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.259.08:22:00.55#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.259.08:22:00.55#ibcon#ireg 11 cls_cnt 2 2006.259.08:22:00.55#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.259.08:22:00.61#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.259.08:22:00.61#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.259.08:22:00.61#ibcon#enter wrdev, iclass 33, count 2 2006.259.08:22:00.61#ibcon#first serial, iclass 33, count 2 2006.259.08:22:00.61#ibcon#enter sib2, iclass 33, count 2 2006.259.08:22:00.61#ibcon#flushed, iclass 33, count 2 2006.259.08:22:00.61#ibcon#about to write, iclass 33, count 2 2006.259.08:22:00.61#ibcon#wrote, iclass 33, count 2 2006.259.08:22:00.61#ibcon#about to read 3, iclass 33, count 2 2006.259.08:22:00.63#ibcon#read 3, iclass 33, count 2 2006.259.08:22:00.63#ibcon#about to read 4, iclass 33, count 2 2006.259.08:22:00.63#ibcon#read 4, iclass 33, count 2 2006.259.08:22:00.63#ibcon#about to read 5, iclass 33, count 2 2006.259.08:22:00.63#ibcon#read 5, iclass 33, count 2 2006.259.08:22:00.63#ibcon#about to read 6, iclass 33, count 2 2006.259.08:22:00.63#ibcon#read 6, iclass 33, count 2 2006.259.08:22:00.63#ibcon#end of sib2, iclass 33, count 2 2006.259.08:22:00.63#ibcon#*mode == 0, iclass 33, count 2 2006.259.08:22:00.63#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.259.08:22:00.63#ibcon#[25=AT05-07\r\n] 2006.259.08:22:00.63#ibcon#*before write, iclass 33, count 2 2006.259.08:22:00.63#ibcon#enter sib2, iclass 33, count 2 2006.259.08:22:00.63#ibcon#flushed, iclass 33, count 2 2006.259.08:22:00.63#ibcon#about to write, iclass 33, count 2 2006.259.08:22:00.63#ibcon#wrote, iclass 33, count 2 2006.259.08:22:00.63#ibcon#about to read 3, iclass 33, count 2 2006.259.08:22:00.67#ibcon#read 3, iclass 33, count 2 2006.259.08:22:00.67#ibcon#about to read 4, iclass 33, count 2 2006.259.08:22:00.67#ibcon#read 4, iclass 33, count 2 2006.259.08:22:00.67#ibcon#about to read 5, iclass 33, count 2 2006.259.08:22:00.67#ibcon#read 5, iclass 33, count 2 2006.259.08:22:00.67#ibcon#about to read 6, iclass 33, count 2 2006.259.08:22:00.67#ibcon#read 6, iclass 33, count 2 2006.259.08:22:00.67#ibcon#end of sib2, iclass 33, count 2 2006.259.08:22:00.67#ibcon#*after write, iclass 33, count 2 2006.259.08:22:00.67#ibcon#*before return 0, iclass 33, count 2 2006.259.08:22:00.67#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.259.08:22:00.67#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.259.08:22:00.67#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.259.08:22:00.67#ibcon#ireg 7 cls_cnt 0 2006.259.08:22:00.67#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.259.08:22:00.79#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.259.08:22:00.79#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.259.08:22:00.79#ibcon#enter wrdev, iclass 33, count 0 2006.259.08:22:00.79#ibcon#first serial, iclass 33, count 0 2006.259.08:22:00.79#ibcon#enter sib2, iclass 33, count 0 2006.259.08:22:00.79#ibcon#flushed, iclass 33, count 0 2006.259.08:22:00.79#ibcon#about to write, iclass 33, count 0 2006.259.08:22:00.79#ibcon#wrote, iclass 33, count 0 2006.259.08:22:00.79#ibcon#about to read 3, iclass 33, count 0 2006.259.08:22:00.81#ibcon#read 3, iclass 33, count 0 2006.259.08:22:00.81#ibcon#about to read 4, iclass 33, count 0 2006.259.08:22:00.81#ibcon#read 4, iclass 33, count 0 2006.259.08:22:00.81#ibcon#about to read 5, iclass 33, count 0 2006.259.08:22:00.81#ibcon#read 5, iclass 33, count 0 2006.259.08:22:00.81#ibcon#about to read 6, iclass 33, count 0 2006.259.08:22:00.81#ibcon#read 6, iclass 33, count 0 2006.259.08:22:00.81#ibcon#end of sib2, iclass 33, count 0 2006.259.08:22:00.81#ibcon#*mode == 0, iclass 33, count 0 2006.259.08:22:00.81#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.259.08:22:00.81#ibcon#[25=USB\r\n] 2006.259.08:22:00.81#ibcon#*before write, iclass 33, count 0 2006.259.08:22:00.81#ibcon#enter sib2, iclass 33, count 0 2006.259.08:22:00.81#ibcon#flushed, iclass 33, count 0 2006.259.08:22:00.81#ibcon#about to write, iclass 33, count 0 2006.259.08:22:00.81#ibcon#wrote, iclass 33, count 0 2006.259.08:22:00.81#ibcon#about to read 3, iclass 33, count 0 2006.259.08:22:00.84#ibcon#read 3, iclass 33, count 0 2006.259.08:22:00.84#ibcon#about to read 4, iclass 33, count 0 2006.259.08:22:00.84#ibcon#read 4, iclass 33, count 0 2006.259.08:22:00.84#ibcon#about to read 5, iclass 33, count 0 2006.259.08:22:00.84#ibcon#read 5, iclass 33, count 0 2006.259.08:22:00.84#ibcon#about to read 6, iclass 33, count 0 2006.259.08:22:00.84#ibcon#read 6, iclass 33, count 0 2006.259.08:22:00.84#ibcon#end of sib2, iclass 33, count 0 2006.259.08:22:00.84#ibcon#*after write, iclass 33, count 0 2006.259.08:22:00.84#ibcon#*before return 0, iclass 33, count 0 2006.259.08:22:00.84#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.259.08:22:00.84#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.259.08:22:00.84#ibcon#about to clear, iclass 33 cls_cnt 0 2006.259.08:22:00.84#ibcon#cleared, iclass 33 cls_cnt 0 2006.259.08:22:00.84$vc4f8/valo=6,772.99 2006.259.08:22:00.84#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.259.08:22:00.84#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.259.08:22:00.84#ibcon#ireg 17 cls_cnt 0 2006.259.08:22:00.84#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.259.08:22:00.84#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.259.08:22:00.84#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.259.08:22:00.84#ibcon#enter wrdev, iclass 35, count 0 2006.259.08:22:00.84#ibcon#first serial, iclass 35, count 0 2006.259.08:22:00.84#ibcon#enter sib2, iclass 35, count 0 2006.259.08:22:00.84#ibcon#flushed, iclass 35, count 0 2006.259.08:22:00.84#ibcon#about to write, iclass 35, count 0 2006.259.08:22:00.84#ibcon#wrote, iclass 35, count 0 2006.259.08:22:00.84#ibcon#about to read 3, iclass 35, count 0 2006.259.08:22:00.86#ibcon#read 3, iclass 35, count 0 2006.259.08:22:00.86#ibcon#about to read 4, iclass 35, count 0 2006.259.08:22:00.86#ibcon#read 4, iclass 35, count 0 2006.259.08:22:00.86#ibcon#about to read 5, iclass 35, count 0 2006.259.08:22:00.86#ibcon#read 5, iclass 35, count 0 2006.259.08:22:00.86#ibcon#about to read 6, iclass 35, count 0 2006.259.08:22:00.86#ibcon#read 6, iclass 35, count 0 2006.259.08:22:00.86#ibcon#end of sib2, iclass 35, count 0 2006.259.08:22:00.86#ibcon#*mode == 0, iclass 35, count 0 2006.259.08:22:00.86#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.259.08:22:00.86#ibcon#[26=FRQ=06,772.99\r\n] 2006.259.08:22:00.86#ibcon#*before write, iclass 35, count 0 2006.259.08:22:00.86#ibcon#enter sib2, iclass 35, count 0 2006.259.08:22:00.86#ibcon#flushed, iclass 35, count 0 2006.259.08:22:00.86#ibcon#about to write, iclass 35, count 0 2006.259.08:22:00.86#ibcon#wrote, iclass 35, count 0 2006.259.08:22:00.86#ibcon#about to read 3, iclass 35, count 0 2006.259.08:22:00.90#ibcon#read 3, iclass 35, count 0 2006.259.08:22:00.90#ibcon#about to read 4, iclass 35, count 0 2006.259.08:22:00.90#ibcon#read 4, iclass 35, count 0 2006.259.08:22:00.90#ibcon#about to read 5, iclass 35, count 0 2006.259.08:22:00.90#ibcon#read 5, iclass 35, count 0 2006.259.08:22:00.90#ibcon#about to read 6, iclass 35, count 0 2006.259.08:22:00.90#ibcon#read 6, iclass 35, count 0 2006.259.08:22:00.90#ibcon#end of sib2, iclass 35, count 0 2006.259.08:22:00.90#ibcon#*after write, iclass 35, count 0 2006.259.08:22:00.90#ibcon#*before return 0, iclass 35, count 0 2006.259.08:22:00.90#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.259.08:22:00.90#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.259.08:22:00.90#ibcon#about to clear, iclass 35 cls_cnt 0 2006.259.08:22:00.90#ibcon#cleared, iclass 35 cls_cnt 0 2006.259.08:22:00.90$vc4f8/va=6,6 2006.259.08:22:00.90#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.259.08:22:00.90#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.259.08:22:00.90#ibcon#ireg 11 cls_cnt 2 2006.259.08:22:00.90#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.259.08:22:00.96#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.259.08:22:00.96#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.259.08:22:00.96#ibcon#enter wrdev, iclass 37, count 2 2006.259.08:22:00.96#ibcon#first serial, iclass 37, count 2 2006.259.08:22:00.96#ibcon#enter sib2, iclass 37, count 2 2006.259.08:22:00.96#ibcon#flushed, iclass 37, count 2 2006.259.08:22:00.96#ibcon#about to write, iclass 37, count 2 2006.259.08:22:00.96#ibcon#wrote, iclass 37, count 2 2006.259.08:22:00.96#ibcon#about to read 3, iclass 37, count 2 2006.259.08:22:00.98#ibcon#read 3, iclass 37, count 2 2006.259.08:22:00.98#ibcon#about to read 4, iclass 37, count 2 2006.259.08:22:00.98#ibcon#read 4, iclass 37, count 2 2006.259.08:22:00.98#ibcon#about to read 5, iclass 37, count 2 2006.259.08:22:00.98#ibcon#read 5, iclass 37, count 2 2006.259.08:22:00.98#ibcon#about to read 6, iclass 37, count 2 2006.259.08:22:00.98#ibcon#read 6, iclass 37, count 2 2006.259.08:22:00.98#ibcon#end of sib2, iclass 37, count 2 2006.259.08:22:00.98#ibcon#*mode == 0, iclass 37, count 2 2006.259.08:22:00.98#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.259.08:22:00.98#ibcon#[25=AT06-06\r\n] 2006.259.08:22:00.98#ibcon#*before write, iclass 37, count 2 2006.259.08:22:00.98#ibcon#enter sib2, iclass 37, count 2 2006.259.08:22:00.98#ibcon#flushed, iclass 37, count 2 2006.259.08:22:00.98#ibcon#about to write, iclass 37, count 2 2006.259.08:22:00.98#ibcon#wrote, iclass 37, count 2 2006.259.08:22:00.98#ibcon#about to read 3, iclass 37, count 2 2006.259.08:22:01.01#ibcon#read 3, iclass 37, count 2 2006.259.08:22:01.01#ibcon#about to read 4, iclass 37, count 2 2006.259.08:22:01.01#ibcon#read 4, iclass 37, count 2 2006.259.08:22:01.01#ibcon#about to read 5, iclass 37, count 2 2006.259.08:22:01.01#ibcon#read 5, iclass 37, count 2 2006.259.08:22:01.01#ibcon#about to read 6, iclass 37, count 2 2006.259.08:22:01.01#ibcon#read 6, iclass 37, count 2 2006.259.08:22:01.01#ibcon#end of sib2, iclass 37, count 2 2006.259.08:22:01.01#ibcon#*after write, iclass 37, count 2 2006.259.08:22:01.01#ibcon#*before return 0, iclass 37, count 2 2006.259.08:22:01.01#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.259.08:22:01.01#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.259.08:22:01.01#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.259.08:22:01.01#ibcon#ireg 7 cls_cnt 0 2006.259.08:22:01.01#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.259.08:22:01.13#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.259.08:22:01.13#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.259.08:22:01.13#ibcon#enter wrdev, iclass 37, count 0 2006.259.08:22:01.13#ibcon#first serial, iclass 37, count 0 2006.259.08:22:01.13#ibcon#enter sib2, iclass 37, count 0 2006.259.08:22:01.13#ibcon#flushed, iclass 37, count 0 2006.259.08:22:01.13#ibcon#about to write, iclass 37, count 0 2006.259.08:22:01.13#ibcon#wrote, iclass 37, count 0 2006.259.08:22:01.13#ibcon#about to read 3, iclass 37, count 0 2006.259.08:22:01.15#ibcon#read 3, iclass 37, count 0 2006.259.08:22:01.15#ibcon#about to read 4, iclass 37, count 0 2006.259.08:22:01.15#ibcon#read 4, iclass 37, count 0 2006.259.08:22:01.15#ibcon#about to read 5, iclass 37, count 0 2006.259.08:22:01.15#ibcon#read 5, iclass 37, count 0 2006.259.08:22:01.15#ibcon#about to read 6, iclass 37, count 0 2006.259.08:22:01.15#ibcon#read 6, iclass 37, count 0 2006.259.08:22:01.15#ibcon#end of sib2, iclass 37, count 0 2006.259.08:22:01.15#ibcon#*mode == 0, iclass 37, count 0 2006.259.08:22:01.15#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.259.08:22:01.15#ibcon#[25=USB\r\n] 2006.259.08:22:01.15#ibcon#*before write, iclass 37, count 0 2006.259.08:22:01.15#ibcon#enter sib2, iclass 37, count 0 2006.259.08:22:01.15#ibcon#flushed, iclass 37, count 0 2006.259.08:22:01.15#ibcon#about to write, iclass 37, count 0 2006.259.08:22:01.15#ibcon#wrote, iclass 37, count 0 2006.259.08:22:01.15#ibcon#about to read 3, iclass 37, count 0 2006.259.08:22:01.18#ibcon#read 3, iclass 37, count 0 2006.259.08:22:01.18#ibcon#about to read 4, iclass 37, count 0 2006.259.08:22:01.18#ibcon#read 4, iclass 37, count 0 2006.259.08:22:01.18#ibcon#about to read 5, iclass 37, count 0 2006.259.08:22:01.18#ibcon#read 5, iclass 37, count 0 2006.259.08:22:01.18#ibcon#about to read 6, iclass 37, count 0 2006.259.08:22:01.18#ibcon#read 6, iclass 37, count 0 2006.259.08:22:01.18#ibcon#end of sib2, iclass 37, count 0 2006.259.08:22:01.18#ibcon#*after write, iclass 37, count 0 2006.259.08:22:01.18#ibcon#*before return 0, iclass 37, count 0 2006.259.08:22:01.18#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.259.08:22:01.18#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.259.08:22:01.18#ibcon#about to clear, iclass 37 cls_cnt 0 2006.259.08:22:01.18#ibcon#cleared, iclass 37 cls_cnt 0 2006.259.08:22:01.18$vc4f8/valo=7,832.99 2006.259.08:22:01.18#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.259.08:22:01.18#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.259.08:22:01.18#ibcon#ireg 17 cls_cnt 0 2006.259.08:22:01.18#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.259.08:22:01.18#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.259.08:22:01.18#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.259.08:22:01.18#ibcon#enter wrdev, iclass 39, count 0 2006.259.08:22:01.18#ibcon#first serial, iclass 39, count 0 2006.259.08:22:01.18#ibcon#enter sib2, iclass 39, count 0 2006.259.08:22:01.18#ibcon#flushed, iclass 39, count 0 2006.259.08:22:01.18#ibcon#about to write, iclass 39, count 0 2006.259.08:22:01.18#ibcon#wrote, iclass 39, count 0 2006.259.08:22:01.18#ibcon#about to read 3, iclass 39, count 0 2006.259.08:22:01.20#ibcon#read 3, iclass 39, count 0 2006.259.08:22:01.20#ibcon#about to read 4, iclass 39, count 0 2006.259.08:22:01.20#ibcon#read 4, iclass 39, count 0 2006.259.08:22:01.20#ibcon#about to read 5, iclass 39, count 0 2006.259.08:22:01.20#ibcon#read 5, iclass 39, count 0 2006.259.08:22:01.20#ibcon#about to read 6, iclass 39, count 0 2006.259.08:22:01.20#ibcon#read 6, iclass 39, count 0 2006.259.08:22:01.20#ibcon#end of sib2, iclass 39, count 0 2006.259.08:22:01.20#ibcon#*mode == 0, iclass 39, count 0 2006.259.08:22:01.20#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.259.08:22:01.20#ibcon#[26=FRQ=07,832.99\r\n] 2006.259.08:22:01.20#ibcon#*before write, iclass 39, count 0 2006.259.08:22:01.20#ibcon#enter sib2, iclass 39, count 0 2006.259.08:22:01.20#ibcon#flushed, iclass 39, count 0 2006.259.08:22:01.20#ibcon#about to write, iclass 39, count 0 2006.259.08:22:01.20#ibcon#wrote, iclass 39, count 0 2006.259.08:22:01.20#ibcon#about to read 3, iclass 39, count 0 2006.259.08:22:01.24#ibcon#read 3, iclass 39, count 0 2006.259.08:22:01.24#ibcon#about to read 4, iclass 39, count 0 2006.259.08:22:01.24#ibcon#read 4, iclass 39, count 0 2006.259.08:22:01.24#ibcon#about to read 5, iclass 39, count 0 2006.259.08:22:01.24#ibcon#read 5, iclass 39, count 0 2006.259.08:22:01.24#ibcon#about to read 6, iclass 39, count 0 2006.259.08:22:01.24#ibcon#read 6, iclass 39, count 0 2006.259.08:22:01.24#ibcon#end of sib2, iclass 39, count 0 2006.259.08:22:01.24#ibcon#*after write, iclass 39, count 0 2006.259.08:22:01.24#ibcon#*before return 0, iclass 39, count 0 2006.259.08:22:01.24#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.259.08:22:01.24#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.259.08:22:01.24#ibcon#about to clear, iclass 39 cls_cnt 0 2006.259.08:22:01.24#ibcon#cleared, iclass 39 cls_cnt 0 2006.259.08:22:01.24$vc4f8/va=7,6 2006.259.08:22:01.24#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.259.08:22:01.24#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.259.08:22:01.24#ibcon#ireg 11 cls_cnt 2 2006.259.08:22:01.24#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.259.08:22:01.30#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.259.08:22:01.30#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.259.08:22:01.30#ibcon#enter wrdev, iclass 3, count 2 2006.259.08:22:01.30#ibcon#first serial, iclass 3, count 2 2006.259.08:22:01.30#ibcon#enter sib2, iclass 3, count 2 2006.259.08:22:01.30#ibcon#flushed, iclass 3, count 2 2006.259.08:22:01.30#ibcon#about to write, iclass 3, count 2 2006.259.08:22:01.30#ibcon#wrote, iclass 3, count 2 2006.259.08:22:01.30#ibcon#about to read 3, iclass 3, count 2 2006.259.08:22:01.32#ibcon#read 3, iclass 3, count 2 2006.259.08:22:01.32#ibcon#about to read 4, iclass 3, count 2 2006.259.08:22:01.32#ibcon#read 4, iclass 3, count 2 2006.259.08:22:01.32#ibcon#about to read 5, iclass 3, count 2 2006.259.08:22:01.32#ibcon#read 5, iclass 3, count 2 2006.259.08:22:01.32#ibcon#about to read 6, iclass 3, count 2 2006.259.08:22:01.32#ibcon#read 6, iclass 3, count 2 2006.259.08:22:01.32#ibcon#end of sib2, iclass 3, count 2 2006.259.08:22:01.32#ibcon#*mode == 0, iclass 3, count 2 2006.259.08:22:01.32#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.259.08:22:01.32#ibcon#[25=AT07-06\r\n] 2006.259.08:22:01.32#ibcon#*before write, iclass 3, count 2 2006.259.08:22:01.32#ibcon#enter sib2, iclass 3, count 2 2006.259.08:22:01.32#ibcon#flushed, iclass 3, count 2 2006.259.08:22:01.32#ibcon#about to write, iclass 3, count 2 2006.259.08:22:01.32#ibcon#wrote, iclass 3, count 2 2006.259.08:22:01.32#ibcon#about to read 3, iclass 3, count 2 2006.259.08:22:01.35#ibcon#read 3, iclass 3, count 2 2006.259.08:22:01.35#ibcon#about to read 4, iclass 3, count 2 2006.259.08:22:01.35#ibcon#read 4, iclass 3, count 2 2006.259.08:22:01.35#ibcon#about to read 5, iclass 3, count 2 2006.259.08:22:01.35#ibcon#read 5, iclass 3, count 2 2006.259.08:22:01.35#ibcon#about to read 6, iclass 3, count 2 2006.259.08:22:01.35#ibcon#read 6, iclass 3, count 2 2006.259.08:22:01.35#ibcon#end of sib2, iclass 3, count 2 2006.259.08:22:01.35#ibcon#*after write, iclass 3, count 2 2006.259.08:22:01.35#ibcon#*before return 0, iclass 3, count 2 2006.259.08:22:01.35#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.259.08:22:01.35#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.259.08:22:01.35#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.259.08:22:01.35#ibcon#ireg 7 cls_cnt 0 2006.259.08:22:01.35#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.259.08:22:01.47#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.259.08:22:01.47#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.259.08:22:01.47#ibcon#enter wrdev, iclass 3, count 0 2006.259.08:22:01.47#ibcon#first serial, iclass 3, count 0 2006.259.08:22:01.47#ibcon#enter sib2, iclass 3, count 0 2006.259.08:22:01.47#ibcon#flushed, iclass 3, count 0 2006.259.08:22:01.47#ibcon#about to write, iclass 3, count 0 2006.259.08:22:01.47#ibcon#wrote, iclass 3, count 0 2006.259.08:22:01.47#ibcon#about to read 3, iclass 3, count 0 2006.259.08:22:01.49#ibcon#read 3, iclass 3, count 0 2006.259.08:22:01.49#ibcon#about to read 4, iclass 3, count 0 2006.259.08:22:01.49#ibcon#read 4, iclass 3, count 0 2006.259.08:22:01.49#ibcon#about to read 5, iclass 3, count 0 2006.259.08:22:01.49#ibcon#read 5, iclass 3, count 0 2006.259.08:22:01.49#ibcon#about to read 6, iclass 3, count 0 2006.259.08:22:01.49#ibcon#read 6, iclass 3, count 0 2006.259.08:22:01.49#ibcon#end of sib2, iclass 3, count 0 2006.259.08:22:01.49#ibcon#*mode == 0, iclass 3, count 0 2006.259.08:22:01.49#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.259.08:22:01.49#ibcon#[25=USB\r\n] 2006.259.08:22:01.49#ibcon#*before write, iclass 3, count 0 2006.259.08:22:01.49#ibcon#enter sib2, iclass 3, count 0 2006.259.08:22:01.49#ibcon#flushed, iclass 3, count 0 2006.259.08:22:01.49#ibcon#about to write, iclass 3, count 0 2006.259.08:22:01.49#ibcon#wrote, iclass 3, count 0 2006.259.08:22:01.49#ibcon#about to read 3, iclass 3, count 0 2006.259.08:22:01.52#ibcon#read 3, iclass 3, count 0 2006.259.08:22:01.52#ibcon#about to read 4, iclass 3, count 0 2006.259.08:22:01.52#ibcon#read 4, iclass 3, count 0 2006.259.08:22:01.52#ibcon#about to read 5, iclass 3, count 0 2006.259.08:22:01.52#ibcon#read 5, iclass 3, count 0 2006.259.08:22:01.52#ibcon#about to read 6, iclass 3, count 0 2006.259.08:22:01.52#ibcon#read 6, iclass 3, count 0 2006.259.08:22:01.52#ibcon#end of sib2, iclass 3, count 0 2006.259.08:22:01.52#ibcon#*after write, iclass 3, count 0 2006.259.08:22:01.52#ibcon#*before return 0, iclass 3, count 0 2006.259.08:22:01.52#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.259.08:22:01.52#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.259.08:22:01.52#ibcon#about to clear, iclass 3 cls_cnt 0 2006.259.08:22:01.52#ibcon#cleared, iclass 3 cls_cnt 0 2006.259.08:22:01.52$vc4f8/valo=8,852.99 2006.259.08:22:01.52#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.259.08:22:01.52#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.259.08:22:01.52#ibcon#ireg 17 cls_cnt 0 2006.259.08:22:01.52#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.259.08:22:01.52#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.259.08:22:01.52#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.259.08:22:01.52#ibcon#enter wrdev, iclass 5, count 0 2006.259.08:22:01.52#ibcon#first serial, iclass 5, count 0 2006.259.08:22:01.52#ibcon#enter sib2, iclass 5, count 0 2006.259.08:22:01.52#ibcon#flushed, iclass 5, count 0 2006.259.08:22:01.52#ibcon#about to write, iclass 5, count 0 2006.259.08:22:01.52#ibcon#wrote, iclass 5, count 0 2006.259.08:22:01.52#ibcon#about to read 3, iclass 5, count 0 2006.259.08:22:01.54#ibcon#read 3, iclass 5, count 0 2006.259.08:22:01.54#ibcon#about to read 4, iclass 5, count 0 2006.259.08:22:01.54#ibcon#read 4, iclass 5, count 0 2006.259.08:22:01.54#ibcon#about to read 5, iclass 5, count 0 2006.259.08:22:01.54#ibcon#read 5, iclass 5, count 0 2006.259.08:22:01.54#ibcon#about to read 6, iclass 5, count 0 2006.259.08:22:01.54#ibcon#read 6, iclass 5, count 0 2006.259.08:22:01.54#ibcon#end of sib2, iclass 5, count 0 2006.259.08:22:01.54#ibcon#*mode == 0, iclass 5, count 0 2006.259.08:22:01.54#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.259.08:22:01.54#ibcon#[26=FRQ=08,852.99\r\n] 2006.259.08:22:01.54#ibcon#*before write, iclass 5, count 0 2006.259.08:22:01.54#ibcon#enter sib2, iclass 5, count 0 2006.259.08:22:01.54#ibcon#flushed, iclass 5, count 0 2006.259.08:22:01.54#ibcon#about to write, iclass 5, count 0 2006.259.08:22:01.54#ibcon#wrote, iclass 5, count 0 2006.259.08:22:01.54#ibcon#about to read 3, iclass 5, count 0 2006.259.08:22:01.58#ibcon#read 3, iclass 5, count 0 2006.259.08:22:01.58#ibcon#about to read 4, iclass 5, count 0 2006.259.08:22:01.58#ibcon#read 4, iclass 5, count 0 2006.259.08:22:01.58#ibcon#about to read 5, iclass 5, count 0 2006.259.08:22:01.58#ibcon#read 5, iclass 5, count 0 2006.259.08:22:01.58#ibcon#about to read 6, iclass 5, count 0 2006.259.08:22:01.58#ibcon#read 6, iclass 5, count 0 2006.259.08:22:01.58#ibcon#end of sib2, iclass 5, count 0 2006.259.08:22:01.58#ibcon#*after write, iclass 5, count 0 2006.259.08:22:01.58#ibcon#*before return 0, iclass 5, count 0 2006.259.08:22:01.58#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.259.08:22:01.58#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.259.08:22:01.58#ibcon#about to clear, iclass 5 cls_cnt 0 2006.259.08:22:01.58#ibcon#cleared, iclass 5 cls_cnt 0 2006.259.08:22:01.58$vc4f8/va=8,6 2006.259.08:22:01.58#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.259.08:22:01.58#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.259.08:22:01.58#ibcon#ireg 11 cls_cnt 2 2006.259.08:22:01.58#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.259.08:22:01.64#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.259.08:22:01.64#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.259.08:22:01.64#ibcon#enter wrdev, iclass 7, count 2 2006.259.08:22:01.64#ibcon#first serial, iclass 7, count 2 2006.259.08:22:01.64#ibcon#enter sib2, iclass 7, count 2 2006.259.08:22:01.64#ibcon#flushed, iclass 7, count 2 2006.259.08:22:01.64#ibcon#about to write, iclass 7, count 2 2006.259.08:22:01.64#ibcon#wrote, iclass 7, count 2 2006.259.08:22:01.64#ibcon#about to read 3, iclass 7, count 2 2006.259.08:22:01.66#ibcon#read 3, iclass 7, count 2 2006.259.08:22:01.66#ibcon#about to read 4, iclass 7, count 2 2006.259.08:22:01.66#ibcon#read 4, iclass 7, count 2 2006.259.08:22:01.66#ibcon#about to read 5, iclass 7, count 2 2006.259.08:22:01.66#ibcon#read 5, iclass 7, count 2 2006.259.08:22:01.66#ibcon#about to read 6, iclass 7, count 2 2006.259.08:22:01.66#ibcon#read 6, iclass 7, count 2 2006.259.08:22:01.66#ibcon#end of sib2, iclass 7, count 2 2006.259.08:22:01.66#ibcon#*mode == 0, iclass 7, count 2 2006.259.08:22:01.66#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.259.08:22:01.66#ibcon#[25=AT08-06\r\n] 2006.259.08:22:01.66#ibcon#*before write, iclass 7, count 2 2006.259.08:22:01.66#ibcon#enter sib2, iclass 7, count 2 2006.259.08:22:01.66#ibcon#flushed, iclass 7, count 2 2006.259.08:22:01.66#ibcon#about to write, iclass 7, count 2 2006.259.08:22:01.66#ibcon#wrote, iclass 7, count 2 2006.259.08:22:01.66#ibcon#about to read 3, iclass 7, count 2 2006.259.08:22:01.69#ibcon#read 3, iclass 7, count 2 2006.259.08:22:01.69#ibcon#about to read 4, iclass 7, count 2 2006.259.08:22:01.69#ibcon#read 4, iclass 7, count 2 2006.259.08:22:01.69#ibcon#about to read 5, iclass 7, count 2 2006.259.08:22:01.69#ibcon#read 5, iclass 7, count 2 2006.259.08:22:01.69#ibcon#about to read 6, iclass 7, count 2 2006.259.08:22:01.69#ibcon#read 6, iclass 7, count 2 2006.259.08:22:01.69#ibcon#end of sib2, iclass 7, count 2 2006.259.08:22:01.69#ibcon#*after write, iclass 7, count 2 2006.259.08:22:01.69#ibcon#*before return 0, iclass 7, count 2 2006.259.08:22:01.69#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.259.08:22:01.69#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.259.08:22:01.69#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.259.08:22:01.69#ibcon#ireg 7 cls_cnt 0 2006.259.08:22:01.69#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.259.08:22:01.81#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.259.08:22:01.81#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.259.08:22:01.81#ibcon#enter wrdev, iclass 7, count 0 2006.259.08:22:01.81#ibcon#first serial, iclass 7, count 0 2006.259.08:22:01.81#ibcon#enter sib2, iclass 7, count 0 2006.259.08:22:01.81#ibcon#flushed, iclass 7, count 0 2006.259.08:22:01.81#ibcon#about to write, iclass 7, count 0 2006.259.08:22:01.81#ibcon#wrote, iclass 7, count 0 2006.259.08:22:01.81#ibcon#about to read 3, iclass 7, count 0 2006.259.08:22:01.83#ibcon#read 3, iclass 7, count 0 2006.259.08:22:01.83#ibcon#about to read 4, iclass 7, count 0 2006.259.08:22:01.83#ibcon#read 4, iclass 7, count 0 2006.259.08:22:01.83#ibcon#about to read 5, iclass 7, count 0 2006.259.08:22:01.83#ibcon#read 5, iclass 7, count 0 2006.259.08:22:01.83#ibcon#about to read 6, iclass 7, count 0 2006.259.08:22:01.83#ibcon#read 6, iclass 7, count 0 2006.259.08:22:01.83#ibcon#end of sib2, iclass 7, count 0 2006.259.08:22:01.83#ibcon#*mode == 0, iclass 7, count 0 2006.259.08:22:01.83#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.259.08:22:01.83#ibcon#[25=USB\r\n] 2006.259.08:22:01.83#ibcon#*before write, iclass 7, count 0 2006.259.08:22:01.83#ibcon#enter sib2, iclass 7, count 0 2006.259.08:22:01.83#ibcon#flushed, iclass 7, count 0 2006.259.08:22:01.83#ibcon#about to write, iclass 7, count 0 2006.259.08:22:01.83#ibcon#wrote, iclass 7, count 0 2006.259.08:22:01.83#ibcon#about to read 3, iclass 7, count 0 2006.259.08:22:01.86#ibcon#read 3, iclass 7, count 0 2006.259.08:22:01.86#ibcon#about to read 4, iclass 7, count 0 2006.259.08:22:01.86#ibcon#read 4, iclass 7, count 0 2006.259.08:22:01.86#ibcon#about to read 5, iclass 7, count 0 2006.259.08:22:01.86#ibcon#read 5, iclass 7, count 0 2006.259.08:22:01.86#ibcon#about to read 6, iclass 7, count 0 2006.259.08:22:01.86#ibcon#read 6, iclass 7, count 0 2006.259.08:22:01.86#ibcon#end of sib2, iclass 7, count 0 2006.259.08:22:01.86#ibcon#*after write, iclass 7, count 0 2006.259.08:22:01.86#ibcon#*before return 0, iclass 7, count 0 2006.259.08:22:01.86#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.259.08:22:01.86#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.259.08:22:01.86#ibcon#about to clear, iclass 7 cls_cnt 0 2006.259.08:22:01.86#ibcon#cleared, iclass 7 cls_cnt 0 2006.259.08:22:01.86$vc4f8/vblo=1,632.99 2006.259.08:22:01.86#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.259.08:22:01.86#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.259.08:22:01.86#ibcon#ireg 17 cls_cnt 0 2006.259.08:22:01.86#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.259.08:22:01.86#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.259.08:22:01.86#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.259.08:22:01.86#ibcon#enter wrdev, iclass 11, count 0 2006.259.08:22:01.86#ibcon#first serial, iclass 11, count 0 2006.259.08:22:01.86#ibcon#enter sib2, iclass 11, count 0 2006.259.08:22:01.86#ibcon#flushed, iclass 11, count 0 2006.259.08:22:01.86#ibcon#about to write, iclass 11, count 0 2006.259.08:22:01.86#ibcon#wrote, iclass 11, count 0 2006.259.08:22:01.86#ibcon#about to read 3, iclass 11, count 0 2006.259.08:22:01.88#ibcon#read 3, iclass 11, count 0 2006.259.08:22:01.88#ibcon#about to read 4, iclass 11, count 0 2006.259.08:22:01.88#ibcon#read 4, iclass 11, count 0 2006.259.08:22:01.88#ibcon#about to read 5, iclass 11, count 0 2006.259.08:22:01.88#ibcon#read 5, iclass 11, count 0 2006.259.08:22:01.88#ibcon#about to read 6, iclass 11, count 0 2006.259.08:22:01.88#ibcon#read 6, iclass 11, count 0 2006.259.08:22:01.88#ibcon#end of sib2, iclass 11, count 0 2006.259.08:22:01.88#ibcon#*mode == 0, iclass 11, count 0 2006.259.08:22:01.88#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.259.08:22:01.88#ibcon#[28=FRQ=01,632.99\r\n] 2006.259.08:22:01.88#ibcon#*before write, iclass 11, count 0 2006.259.08:22:01.88#ibcon#enter sib2, iclass 11, count 0 2006.259.08:22:01.88#ibcon#flushed, iclass 11, count 0 2006.259.08:22:01.88#ibcon#about to write, iclass 11, count 0 2006.259.08:22:01.88#ibcon#wrote, iclass 11, count 0 2006.259.08:22:01.88#ibcon#about to read 3, iclass 11, count 0 2006.259.08:22:01.92#ibcon#read 3, iclass 11, count 0 2006.259.08:22:01.92#ibcon#about to read 4, iclass 11, count 0 2006.259.08:22:01.92#ibcon#read 4, iclass 11, count 0 2006.259.08:22:01.92#ibcon#about to read 5, iclass 11, count 0 2006.259.08:22:01.92#ibcon#read 5, iclass 11, count 0 2006.259.08:22:01.92#ibcon#about to read 6, iclass 11, count 0 2006.259.08:22:01.92#ibcon#read 6, iclass 11, count 0 2006.259.08:22:01.92#ibcon#end of sib2, iclass 11, count 0 2006.259.08:22:01.92#ibcon#*after write, iclass 11, count 0 2006.259.08:22:01.92#ibcon#*before return 0, iclass 11, count 0 2006.259.08:22:01.92#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.259.08:22:01.92#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.259.08:22:01.92#ibcon#about to clear, iclass 11 cls_cnt 0 2006.259.08:22:01.92#ibcon#cleared, iclass 11 cls_cnt 0 2006.259.08:22:01.92$vc4f8/vb=1,4 2006.259.08:22:01.92#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.259.08:22:01.92#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.259.08:22:01.92#ibcon#ireg 11 cls_cnt 2 2006.259.08:22:01.92#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.259.08:22:01.92#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.259.08:22:01.92#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.259.08:22:01.92#ibcon#enter wrdev, iclass 13, count 2 2006.259.08:22:01.92#ibcon#first serial, iclass 13, count 2 2006.259.08:22:01.92#ibcon#enter sib2, iclass 13, count 2 2006.259.08:22:01.92#ibcon#flushed, iclass 13, count 2 2006.259.08:22:01.92#ibcon#about to write, iclass 13, count 2 2006.259.08:22:01.92#ibcon#wrote, iclass 13, count 2 2006.259.08:22:01.92#ibcon#about to read 3, iclass 13, count 2 2006.259.08:22:01.94#ibcon#read 3, iclass 13, count 2 2006.259.08:22:01.94#ibcon#about to read 4, iclass 13, count 2 2006.259.08:22:01.94#ibcon#read 4, iclass 13, count 2 2006.259.08:22:01.94#ibcon#about to read 5, iclass 13, count 2 2006.259.08:22:01.94#ibcon#read 5, iclass 13, count 2 2006.259.08:22:01.94#ibcon#about to read 6, iclass 13, count 2 2006.259.08:22:01.94#ibcon#read 6, iclass 13, count 2 2006.259.08:22:01.94#ibcon#end of sib2, iclass 13, count 2 2006.259.08:22:01.94#ibcon#*mode == 0, iclass 13, count 2 2006.259.08:22:01.94#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.259.08:22:01.94#ibcon#[27=AT01-04\r\n] 2006.259.08:22:01.94#ibcon#*before write, iclass 13, count 2 2006.259.08:22:01.94#ibcon#enter sib2, iclass 13, count 2 2006.259.08:22:01.94#ibcon#flushed, iclass 13, count 2 2006.259.08:22:01.94#ibcon#about to write, iclass 13, count 2 2006.259.08:22:01.94#ibcon#wrote, iclass 13, count 2 2006.259.08:22:01.94#ibcon#about to read 3, iclass 13, count 2 2006.259.08:22:01.97#ibcon#read 3, iclass 13, count 2 2006.259.08:22:01.97#ibcon#about to read 4, iclass 13, count 2 2006.259.08:22:01.97#ibcon#read 4, iclass 13, count 2 2006.259.08:22:01.97#ibcon#about to read 5, iclass 13, count 2 2006.259.08:22:01.97#ibcon#read 5, iclass 13, count 2 2006.259.08:22:01.97#ibcon#about to read 6, iclass 13, count 2 2006.259.08:22:01.97#ibcon#read 6, iclass 13, count 2 2006.259.08:22:01.97#ibcon#end of sib2, iclass 13, count 2 2006.259.08:22:01.97#ibcon#*after write, iclass 13, count 2 2006.259.08:22:01.97#ibcon#*before return 0, iclass 13, count 2 2006.259.08:22:01.97#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.259.08:22:01.97#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.259.08:22:01.97#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.259.08:22:01.97#ibcon#ireg 7 cls_cnt 0 2006.259.08:22:01.97#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.259.08:22:02.09#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.259.08:22:02.09#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.259.08:22:02.09#ibcon#enter wrdev, iclass 13, count 0 2006.259.08:22:02.09#ibcon#first serial, iclass 13, count 0 2006.259.08:22:02.09#ibcon#enter sib2, iclass 13, count 0 2006.259.08:22:02.09#ibcon#flushed, iclass 13, count 0 2006.259.08:22:02.09#ibcon#about to write, iclass 13, count 0 2006.259.08:22:02.09#ibcon#wrote, iclass 13, count 0 2006.259.08:22:02.09#ibcon#about to read 3, iclass 13, count 0 2006.259.08:22:02.11#ibcon#read 3, iclass 13, count 0 2006.259.08:22:02.11#ibcon#about to read 4, iclass 13, count 0 2006.259.08:22:02.11#ibcon#read 4, iclass 13, count 0 2006.259.08:22:02.11#ibcon#about to read 5, iclass 13, count 0 2006.259.08:22:02.11#ibcon#read 5, iclass 13, count 0 2006.259.08:22:02.11#ibcon#about to read 6, iclass 13, count 0 2006.259.08:22:02.11#ibcon#read 6, iclass 13, count 0 2006.259.08:22:02.11#ibcon#end of sib2, iclass 13, count 0 2006.259.08:22:02.11#ibcon#*mode == 0, iclass 13, count 0 2006.259.08:22:02.11#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.259.08:22:02.11#ibcon#[27=USB\r\n] 2006.259.08:22:02.11#ibcon#*before write, iclass 13, count 0 2006.259.08:22:02.11#ibcon#enter sib2, iclass 13, count 0 2006.259.08:22:02.11#ibcon#flushed, iclass 13, count 0 2006.259.08:22:02.11#ibcon#about to write, iclass 13, count 0 2006.259.08:22:02.11#ibcon#wrote, iclass 13, count 0 2006.259.08:22:02.11#ibcon#about to read 3, iclass 13, count 0 2006.259.08:22:02.14#ibcon#read 3, iclass 13, count 0 2006.259.08:22:02.14#ibcon#about to read 4, iclass 13, count 0 2006.259.08:22:02.14#ibcon#read 4, iclass 13, count 0 2006.259.08:22:02.14#ibcon#about to read 5, iclass 13, count 0 2006.259.08:22:02.14#ibcon#read 5, iclass 13, count 0 2006.259.08:22:02.14#ibcon#about to read 6, iclass 13, count 0 2006.259.08:22:02.14#ibcon#read 6, iclass 13, count 0 2006.259.08:22:02.14#ibcon#end of sib2, iclass 13, count 0 2006.259.08:22:02.14#ibcon#*after write, iclass 13, count 0 2006.259.08:22:02.14#ibcon#*before return 0, iclass 13, count 0 2006.259.08:22:02.14#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.259.08:22:02.14#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.259.08:22:02.14#ibcon#about to clear, iclass 13 cls_cnt 0 2006.259.08:22:02.14#ibcon#cleared, iclass 13 cls_cnt 0 2006.259.08:22:02.14$vc4f8/vblo=2,640.99 2006.259.08:22:02.14#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.259.08:22:02.14#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.259.08:22:02.14#ibcon#ireg 17 cls_cnt 0 2006.259.08:22:02.14#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.259.08:22:02.14#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.259.08:22:02.14#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.259.08:22:02.14#ibcon#enter wrdev, iclass 15, count 0 2006.259.08:22:02.14#ibcon#first serial, iclass 15, count 0 2006.259.08:22:02.14#ibcon#enter sib2, iclass 15, count 0 2006.259.08:22:02.14#ibcon#flushed, iclass 15, count 0 2006.259.08:22:02.14#ibcon#about to write, iclass 15, count 0 2006.259.08:22:02.14#ibcon#wrote, iclass 15, count 0 2006.259.08:22:02.14#ibcon#about to read 3, iclass 15, count 0 2006.259.08:22:02.16#ibcon#read 3, iclass 15, count 0 2006.259.08:22:02.16#ibcon#about to read 4, iclass 15, count 0 2006.259.08:22:02.16#ibcon#read 4, iclass 15, count 0 2006.259.08:22:02.16#ibcon#about to read 5, iclass 15, count 0 2006.259.08:22:02.16#ibcon#read 5, iclass 15, count 0 2006.259.08:22:02.16#ibcon#about to read 6, iclass 15, count 0 2006.259.08:22:02.16#ibcon#read 6, iclass 15, count 0 2006.259.08:22:02.16#ibcon#end of sib2, iclass 15, count 0 2006.259.08:22:02.16#ibcon#*mode == 0, iclass 15, count 0 2006.259.08:22:02.16#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.259.08:22:02.16#ibcon#[28=FRQ=02,640.99\r\n] 2006.259.08:22:02.16#ibcon#*before write, iclass 15, count 0 2006.259.08:22:02.16#ibcon#enter sib2, iclass 15, count 0 2006.259.08:22:02.16#ibcon#flushed, iclass 15, count 0 2006.259.08:22:02.16#ibcon#about to write, iclass 15, count 0 2006.259.08:22:02.16#ibcon#wrote, iclass 15, count 0 2006.259.08:22:02.16#ibcon#about to read 3, iclass 15, count 0 2006.259.08:22:02.20#ibcon#read 3, iclass 15, count 0 2006.259.08:22:02.20#ibcon#about to read 4, iclass 15, count 0 2006.259.08:22:02.20#ibcon#read 4, iclass 15, count 0 2006.259.08:22:02.20#ibcon#about to read 5, iclass 15, count 0 2006.259.08:22:02.20#ibcon#read 5, iclass 15, count 0 2006.259.08:22:02.20#ibcon#about to read 6, iclass 15, count 0 2006.259.08:22:02.20#ibcon#read 6, iclass 15, count 0 2006.259.08:22:02.20#ibcon#end of sib2, iclass 15, count 0 2006.259.08:22:02.20#ibcon#*after write, iclass 15, count 0 2006.259.08:22:02.20#ibcon#*before return 0, iclass 15, count 0 2006.259.08:22:02.20#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.259.08:22:02.20#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.259.08:22:02.20#ibcon#about to clear, iclass 15 cls_cnt 0 2006.259.08:22:02.20#ibcon#cleared, iclass 15 cls_cnt 0 2006.259.08:22:02.20$vc4f8/vb=2,5 2006.259.08:22:02.20#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.259.08:22:02.20#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.259.08:22:02.20#ibcon#ireg 11 cls_cnt 2 2006.259.08:22:02.20#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.259.08:22:02.26#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.259.08:22:02.26#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.259.08:22:02.26#ibcon#enter wrdev, iclass 17, count 2 2006.259.08:22:02.26#ibcon#first serial, iclass 17, count 2 2006.259.08:22:02.26#ibcon#enter sib2, iclass 17, count 2 2006.259.08:22:02.26#ibcon#flushed, iclass 17, count 2 2006.259.08:22:02.26#ibcon#about to write, iclass 17, count 2 2006.259.08:22:02.26#ibcon#wrote, iclass 17, count 2 2006.259.08:22:02.26#ibcon#about to read 3, iclass 17, count 2 2006.259.08:22:02.28#ibcon#read 3, iclass 17, count 2 2006.259.08:22:02.28#ibcon#about to read 4, iclass 17, count 2 2006.259.08:22:02.28#ibcon#read 4, iclass 17, count 2 2006.259.08:22:02.28#ibcon#about to read 5, iclass 17, count 2 2006.259.08:22:02.28#ibcon#read 5, iclass 17, count 2 2006.259.08:22:02.28#ibcon#about to read 6, iclass 17, count 2 2006.259.08:22:02.28#ibcon#read 6, iclass 17, count 2 2006.259.08:22:02.28#ibcon#end of sib2, iclass 17, count 2 2006.259.08:22:02.28#ibcon#*mode == 0, iclass 17, count 2 2006.259.08:22:02.28#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.259.08:22:02.28#ibcon#[27=AT02-05\r\n] 2006.259.08:22:02.28#ibcon#*before write, iclass 17, count 2 2006.259.08:22:02.28#ibcon#enter sib2, iclass 17, count 2 2006.259.08:22:02.28#ibcon#flushed, iclass 17, count 2 2006.259.08:22:02.28#ibcon#about to write, iclass 17, count 2 2006.259.08:22:02.28#ibcon#wrote, iclass 17, count 2 2006.259.08:22:02.28#ibcon#about to read 3, iclass 17, count 2 2006.259.08:22:02.31#ibcon#read 3, iclass 17, count 2 2006.259.08:22:02.31#ibcon#about to read 4, iclass 17, count 2 2006.259.08:22:02.31#ibcon#read 4, iclass 17, count 2 2006.259.08:22:02.31#ibcon#about to read 5, iclass 17, count 2 2006.259.08:22:02.31#ibcon#read 5, iclass 17, count 2 2006.259.08:22:02.31#ibcon#about to read 6, iclass 17, count 2 2006.259.08:22:02.31#ibcon#read 6, iclass 17, count 2 2006.259.08:22:02.31#ibcon#end of sib2, iclass 17, count 2 2006.259.08:22:02.31#ibcon#*after write, iclass 17, count 2 2006.259.08:22:02.31#ibcon#*before return 0, iclass 17, count 2 2006.259.08:22:02.31#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.259.08:22:02.31#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.259.08:22:02.31#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.259.08:22:02.31#ibcon#ireg 7 cls_cnt 0 2006.259.08:22:02.31#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.259.08:22:02.43#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.259.08:22:02.43#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.259.08:22:02.43#ibcon#enter wrdev, iclass 17, count 0 2006.259.08:22:02.43#ibcon#first serial, iclass 17, count 0 2006.259.08:22:02.43#ibcon#enter sib2, iclass 17, count 0 2006.259.08:22:02.43#ibcon#flushed, iclass 17, count 0 2006.259.08:22:02.43#ibcon#about to write, iclass 17, count 0 2006.259.08:22:02.43#ibcon#wrote, iclass 17, count 0 2006.259.08:22:02.43#ibcon#about to read 3, iclass 17, count 0 2006.259.08:22:02.45#ibcon#read 3, iclass 17, count 0 2006.259.08:22:02.45#ibcon#about to read 4, iclass 17, count 0 2006.259.08:22:02.45#ibcon#read 4, iclass 17, count 0 2006.259.08:22:02.45#ibcon#about to read 5, iclass 17, count 0 2006.259.08:22:02.45#ibcon#read 5, iclass 17, count 0 2006.259.08:22:02.45#ibcon#about to read 6, iclass 17, count 0 2006.259.08:22:02.45#ibcon#read 6, iclass 17, count 0 2006.259.08:22:02.45#ibcon#end of sib2, iclass 17, count 0 2006.259.08:22:02.45#ibcon#*mode == 0, iclass 17, count 0 2006.259.08:22:02.45#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.259.08:22:02.45#ibcon#[27=USB\r\n] 2006.259.08:22:02.45#ibcon#*before write, iclass 17, count 0 2006.259.08:22:02.45#ibcon#enter sib2, iclass 17, count 0 2006.259.08:22:02.45#ibcon#flushed, iclass 17, count 0 2006.259.08:22:02.45#ibcon#about to write, iclass 17, count 0 2006.259.08:22:02.45#ibcon#wrote, iclass 17, count 0 2006.259.08:22:02.45#ibcon#about to read 3, iclass 17, count 0 2006.259.08:22:02.48#ibcon#read 3, iclass 17, count 0 2006.259.08:22:02.48#ibcon#about to read 4, iclass 17, count 0 2006.259.08:22:02.48#ibcon#read 4, iclass 17, count 0 2006.259.08:22:02.48#ibcon#about to read 5, iclass 17, count 0 2006.259.08:22:02.48#ibcon#read 5, iclass 17, count 0 2006.259.08:22:02.48#ibcon#about to read 6, iclass 17, count 0 2006.259.08:22:02.48#ibcon#read 6, iclass 17, count 0 2006.259.08:22:02.48#ibcon#end of sib2, iclass 17, count 0 2006.259.08:22:02.48#ibcon#*after write, iclass 17, count 0 2006.259.08:22:02.48#ibcon#*before return 0, iclass 17, count 0 2006.259.08:22:02.48#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.259.08:22:02.48#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.259.08:22:02.48#ibcon#about to clear, iclass 17 cls_cnt 0 2006.259.08:22:02.48#ibcon#cleared, iclass 17 cls_cnt 0 2006.259.08:22:02.48$vc4f8/vblo=3,656.99 2006.259.08:22:02.48#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.259.08:22:02.48#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.259.08:22:02.48#ibcon#ireg 17 cls_cnt 0 2006.259.08:22:02.48#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.259.08:22:02.48#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.259.08:22:02.48#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.259.08:22:02.48#ibcon#enter wrdev, iclass 19, count 0 2006.259.08:22:02.48#ibcon#first serial, iclass 19, count 0 2006.259.08:22:02.48#ibcon#enter sib2, iclass 19, count 0 2006.259.08:22:02.48#ibcon#flushed, iclass 19, count 0 2006.259.08:22:02.48#ibcon#about to write, iclass 19, count 0 2006.259.08:22:02.48#ibcon#wrote, iclass 19, count 0 2006.259.08:22:02.48#ibcon#about to read 3, iclass 19, count 0 2006.259.08:22:02.50#ibcon#read 3, iclass 19, count 0 2006.259.08:22:02.50#ibcon#about to read 4, iclass 19, count 0 2006.259.08:22:02.50#ibcon#read 4, iclass 19, count 0 2006.259.08:22:02.50#ibcon#about to read 5, iclass 19, count 0 2006.259.08:22:02.50#ibcon#read 5, iclass 19, count 0 2006.259.08:22:02.50#ibcon#about to read 6, iclass 19, count 0 2006.259.08:22:02.50#ibcon#read 6, iclass 19, count 0 2006.259.08:22:02.50#ibcon#end of sib2, iclass 19, count 0 2006.259.08:22:02.50#ibcon#*mode == 0, iclass 19, count 0 2006.259.08:22:02.50#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.259.08:22:02.50#ibcon#[28=FRQ=03,656.99\r\n] 2006.259.08:22:02.50#ibcon#*before write, iclass 19, count 0 2006.259.08:22:02.50#ibcon#enter sib2, iclass 19, count 0 2006.259.08:22:02.50#ibcon#flushed, iclass 19, count 0 2006.259.08:22:02.50#ibcon#about to write, iclass 19, count 0 2006.259.08:22:02.50#ibcon#wrote, iclass 19, count 0 2006.259.08:22:02.50#ibcon#about to read 3, iclass 19, count 0 2006.259.08:22:02.54#ibcon#read 3, iclass 19, count 0 2006.259.08:22:02.54#ibcon#about to read 4, iclass 19, count 0 2006.259.08:22:02.54#ibcon#read 4, iclass 19, count 0 2006.259.08:22:02.54#ibcon#about to read 5, iclass 19, count 0 2006.259.08:22:02.54#ibcon#read 5, iclass 19, count 0 2006.259.08:22:02.54#ibcon#about to read 6, iclass 19, count 0 2006.259.08:22:02.54#ibcon#read 6, iclass 19, count 0 2006.259.08:22:02.54#ibcon#end of sib2, iclass 19, count 0 2006.259.08:22:02.54#ibcon#*after write, iclass 19, count 0 2006.259.08:22:02.54#ibcon#*before return 0, iclass 19, count 0 2006.259.08:22:02.54#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.259.08:22:02.54#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.259.08:22:02.54#ibcon#about to clear, iclass 19 cls_cnt 0 2006.259.08:22:02.54#ibcon#cleared, iclass 19 cls_cnt 0 2006.259.08:22:02.54$vc4f8/vb=3,4 2006.259.08:22:02.54#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.259.08:22:02.54#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.259.08:22:02.54#ibcon#ireg 11 cls_cnt 2 2006.259.08:22:02.54#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.259.08:22:02.60#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.259.08:22:02.60#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.259.08:22:02.60#ibcon#enter wrdev, iclass 21, count 2 2006.259.08:22:02.60#ibcon#first serial, iclass 21, count 2 2006.259.08:22:02.60#ibcon#enter sib2, iclass 21, count 2 2006.259.08:22:02.60#ibcon#flushed, iclass 21, count 2 2006.259.08:22:02.60#ibcon#about to write, iclass 21, count 2 2006.259.08:22:02.60#ibcon#wrote, iclass 21, count 2 2006.259.08:22:02.60#ibcon#about to read 3, iclass 21, count 2 2006.259.08:22:02.62#ibcon#read 3, iclass 21, count 2 2006.259.08:22:02.62#ibcon#about to read 4, iclass 21, count 2 2006.259.08:22:02.62#ibcon#read 4, iclass 21, count 2 2006.259.08:22:02.62#ibcon#about to read 5, iclass 21, count 2 2006.259.08:22:02.62#ibcon#read 5, iclass 21, count 2 2006.259.08:22:02.62#ibcon#about to read 6, iclass 21, count 2 2006.259.08:22:02.62#ibcon#read 6, iclass 21, count 2 2006.259.08:22:02.62#ibcon#end of sib2, iclass 21, count 2 2006.259.08:22:02.62#ibcon#*mode == 0, iclass 21, count 2 2006.259.08:22:02.62#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.259.08:22:02.62#ibcon#[27=AT03-04\r\n] 2006.259.08:22:02.62#ibcon#*before write, iclass 21, count 2 2006.259.08:22:02.62#ibcon#enter sib2, iclass 21, count 2 2006.259.08:22:02.62#ibcon#flushed, iclass 21, count 2 2006.259.08:22:02.62#ibcon#about to write, iclass 21, count 2 2006.259.08:22:02.62#ibcon#wrote, iclass 21, count 2 2006.259.08:22:02.62#ibcon#about to read 3, iclass 21, count 2 2006.259.08:22:02.65#ibcon#read 3, iclass 21, count 2 2006.259.08:22:02.65#ibcon#about to read 4, iclass 21, count 2 2006.259.08:22:02.65#ibcon#read 4, iclass 21, count 2 2006.259.08:22:02.65#ibcon#about to read 5, iclass 21, count 2 2006.259.08:22:02.65#ibcon#read 5, iclass 21, count 2 2006.259.08:22:02.65#ibcon#about to read 6, iclass 21, count 2 2006.259.08:22:02.65#ibcon#read 6, iclass 21, count 2 2006.259.08:22:02.65#ibcon#end of sib2, iclass 21, count 2 2006.259.08:22:02.65#ibcon#*after write, iclass 21, count 2 2006.259.08:22:02.65#ibcon#*before return 0, iclass 21, count 2 2006.259.08:22:02.65#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.259.08:22:02.65#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.259.08:22:02.65#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.259.08:22:02.65#ibcon#ireg 7 cls_cnt 0 2006.259.08:22:02.65#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.259.08:22:02.77#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.259.08:22:02.77#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.259.08:22:02.77#ibcon#enter wrdev, iclass 21, count 0 2006.259.08:22:02.77#ibcon#first serial, iclass 21, count 0 2006.259.08:22:02.77#ibcon#enter sib2, iclass 21, count 0 2006.259.08:22:02.77#ibcon#flushed, iclass 21, count 0 2006.259.08:22:02.77#ibcon#about to write, iclass 21, count 0 2006.259.08:22:02.77#ibcon#wrote, iclass 21, count 0 2006.259.08:22:02.77#ibcon#about to read 3, iclass 21, count 0 2006.259.08:22:02.79#ibcon#read 3, iclass 21, count 0 2006.259.08:22:02.79#ibcon#about to read 4, iclass 21, count 0 2006.259.08:22:02.79#ibcon#read 4, iclass 21, count 0 2006.259.08:22:02.79#ibcon#about to read 5, iclass 21, count 0 2006.259.08:22:02.79#ibcon#read 5, iclass 21, count 0 2006.259.08:22:02.79#ibcon#about to read 6, iclass 21, count 0 2006.259.08:22:02.79#ibcon#read 6, iclass 21, count 0 2006.259.08:22:02.79#ibcon#end of sib2, iclass 21, count 0 2006.259.08:22:02.79#ibcon#*mode == 0, iclass 21, count 0 2006.259.08:22:02.79#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.259.08:22:02.79#ibcon#[27=USB\r\n] 2006.259.08:22:02.79#ibcon#*before write, iclass 21, count 0 2006.259.08:22:02.79#ibcon#enter sib2, iclass 21, count 0 2006.259.08:22:02.79#ibcon#flushed, iclass 21, count 0 2006.259.08:22:02.79#ibcon#about to write, iclass 21, count 0 2006.259.08:22:02.79#ibcon#wrote, iclass 21, count 0 2006.259.08:22:02.79#ibcon#about to read 3, iclass 21, count 0 2006.259.08:22:02.82#ibcon#read 3, iclass 21, count 0 2006.259.08:22:02.82#ibcon#about to read 4, iclass 21, count 0 2006.259.08:22:02.82#ibcon#read 4, iclass 21, count 0 2006.259.08:22:02.82#ibcon#about to read 5, iclass 21, count 0 2006.259.08:22:02.82#ibcon#read 5, iclass 21, count 0 2006.259.08:22:02.82#ibcon#about to read 6, iclass 21, count 0 2006.259.08:22:02.82#ibcon#read 6, iclass 21, count 0 2006.259.08:22:02.82#ibcon#end of sib2, iclass 21, count 0 2006.259.08:22:02.82#ibcon#*after write, iclass 21, count 0 2006.259.08:22:02.82#ibcon#*before return 0, iclass 21, count 0 2006.259.08:22:02.82#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.259.08:22:02.82#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.259.08:22:02.82#ibcon#about to clear, iclass 21 cls_cnt 0 2006.259.08:22:02.82#ibcon#cleared, iclass 21 cls_cnt 0 2006.259.08:22:02.82$vc4f8/vblo=4,712.99 2006.259.08:22:02.82#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.259.08:22:02.82#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.259.08:22:02.82#ibcon#ireg 17 cls_cnt 0 2006.259.08:22:02.82#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.259.08:22:02.82#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.259.08:22:02.82#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.259.08:22:02.82#ibcon#enter wrdev, iclass 23, count 0 2006.259.08:22:02.82#ibcon#first serial, iclass 23, count 0 2006.259.08:22:02.82#ibcon#enter sib2, iclass 23, count 0 2006.259.08:22:02.82#ibcon#flushed, iclass 23, count 0 2006.259.08:22:02.82#ibcon#about to write, iclass 23, count 0 2006.259.08:22:02.82#ibcon#wrote, iclass 23, count 0 2006.259.08:22:02.82#ibcon#about to read 3, iclass 23, count 0 2006.259.08:22:02.84#ibcon#read 3, iclass 23, count 0 2006.259.08:22:02.84#ibcon#about to read 4, iclass 23, count 0 2006.259.08:22:02.84#ibcon#read 4, iclass 23, count 0 2006.259.08:22:02.84#ibcon#about to read 5, iclass 23, count 0 2006.259.08:22:02.84#ibcon#read 5, iclass 23, count 0 2006.259.08:22:02.84#ibcon#about to read 6, iclass 23, count 0 2006.259.08:22:02.84#ibcon#read 6, iclass 23, count 0 2006.259.08:22:02.84#ibcon#end of sib2, iclass 23, count 0 2006.259.08:22:02.84#ibcon#*mode == 0, iclass 23, count 0 2006.259.08:22:02.84#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.259.08:22:02.84#ibcon#[28=FRQ=04,712.99\r\n] 2006.259.08:22:02.84#ibcon#*before write, iclass 23, count 0 2006.259.08:22:02.84#ibcon#enter sib2, iclass 23, count 0 2006.259.08:22:02.84#ibcon#flushed, iclass 23, count 0 2006.259.08:22:02.84#ibcon#about to write, iclass 23, count 0 2006.259.08:22:02.84#ibcon#wrote, iclass 23, count 0 2006.259.08:22:02.84#ibcon#about to read 3, iclass 23, count 0 2006.259.08:22:02.88#ibcon#read 3, iclass 23, count 0 2006.259.08:22:02.88#ibcon#about to read 4, iclass 23, count 0 2006.259.08:22:02.88#ibcon#read 4, iclass 23, count 0 2006.259.08:22:02.88#ibcon#about to read 5, iclass 23, count 0 2006.259.08:22:02.88#ibcon#read 5, iclass 23, count 0 2006.259.08:22:02.88#ibcon#about to read 6, iclass 23, count 0 2006.259.08:22:02.88#ibcon#read 6, iclass 23, count 0 2006.259.08:22:02.88#ibcon#end of sib2, iclass 23, count 0 2006.259.08:22:02.88#ibcon#*after write, iclass 23, count 0 2006.259.08:22:02.88#ibcon#*before return 0, iclass 23, count 0 2006.259.08:22:02.88#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.259.08:22:02.88#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.259.08:22:02.88#ibcon#about to clear, iclass 23 cls_cnt 0 2006.259.08:22:02.88#ibcon#cleared, iclass 23 cls_cnt 0 2006.259.08:22:02.88$vc4f8/vb=4,5 2006.259.08:22:02.88#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.259.08:22:02.88#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.259.08:22:02.88#ibcon#ireg 11 cls_cnt 2 2006.259.08:22:02.88#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.259.08:22:02.94#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.259.08:22:02.94#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.259.08:22:02.94#ibcon#enter wrdev, iclass 25, count 2 2006.259.08:22:02.94#ibcon#first serial, iclass 25, count 2 2006.259.08:22:02.94#ibcon#enter sib2, iclass 25, count 2 2006.259.08:22:02.94#ibcon#flushed, iclass 25, count 2 2006.259.08:22:02.94#ibcon#about to write, iclass 25, count 2 2006.259.08:22:02.94#ibcon#wrote, iclass 25, count 2 2006.259.08:22:02.94#ibcon#about to read 3, iclass 25, count 2 2006.259.08:22:02.96#ibcon#read 3, iclass 25, count 2 2006.259.08:22:02.96#ibcon#about to read 4, iclass 25, count 2 2006.259.08:22:02.96#ibcon#read 4, iclass 25, count 2 2006.259.08:22:02.96#ibcon#about to read 5, iclass 25, count 2 2006.259.08:22:02.96#ibcon#read 5, iclass 25, count 2 2006.259.08:22:02.96#ibcon#about to read 6, iclass 25, count 2 2006.259.08:22:02.96#ibcon#read 6, iclass 25, count 2 2006.259.08:22:02.96#ibcon#end of sib2, iclass 25, count 2 2006.259.08:22:02.96#ibcon#*mode == 0, iclass 25, count 2 2006.259.08:22:02.96#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.259.08:22:02.96#ibcon#[27=AT04-05\r\n] 2006.259.08:22:02.96#ibcon#*before write, iclass 25, count 2 2006.259.08:22:02.96#ibcon#enter sib2, iclass 25, count 2 2006.259.08:22:02.96#ibcon#flushed, iclass 25, count 2 2006.259.08:22:02.96#ibcon#about to write, iclass 25, count 2 2006.259.08:22:02.96#ibcon#wrote, iclass 25, count 2 2006.259.08:22:02.96#ibcon#about to read 3, iclass 25, count 2 2006.259.08:22:02.99#ibcon#read 3, iclass 25, count 2 2006.259.08:22:02.99#ibcon#about to read 4, iclass 25, count 2 2006.259.08:22:02.99#ibcon#read 4, iclass 25, count 2 2006.259.08:22:02.99#ibcon#about to read 5, iclass 25, count 2 2006.259.08:22:02.99#ibcon#read 5, iclass 25, count 2 2006.259.08:22:02.99#ibcon#about to read 6, iclass 25, count 2 2006.259.08:22:02.99#ibcon#read 6, iclass 25, count 2 2006.259.08:22:02.99#ibcon#end of sib2, iclass 25, count 2 2006.259.08:22:02.99#ibcon#*after write, iclass 25, count 2 2006.259.08:22:02.99#ibcon#*before return 0, iclass 25, count 2 2006.259.08:22:02.99#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.259.08:22:02.99#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.259.08:22:02.99#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.259.08:22:02.99#ibcon#ireg 7 cls_cnt 0 2006.259.08:22:02.99#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.259.08:22:03.11#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.259.08:22:03.11#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.259.08:22:03.11#ibcon#enter wrdev, iclass 25, count 0 2006.259.08:22:03.11#ibcon#first serial, iclass 25, count 0 2006.259.08:22:03.11#ibcon#enter sib2, iclass 25, count 0 2006.259.08:22:03.11#ibcon#flushed, iclass 25, count 0 2006.259.08:22:03.11#ibcon#about to write, iclass 25, count 0 2006.259.08:22:03.11#ibcon#wrote, iclass 25, count 0 2006.259.08:22:03.11#ibcon#about to read 3, iclass 25, count 0 2006.259.08:22:03.13#ibcon#read 3, iclass 25, count 0 2006.259.08:22:03.13#ibcon#about to read 4, iclass 25, count 0 2006.259.08:22:03.13#ibcon#read 4, iclass 25, count 0 2006.259.08:22:03.13#ibcon#about to read 5, iclass 25, count 0 2006.259.08:22:03.13#ibcon#read 5, iclass 25, count 0 2006.259.08:22:03.13#ibcon#about to read 6, iclass 25, count 0 2006.259.08:22:03.13#ibcon#read 6, iclass 25, count 0 2006.259.08:22:03.13#ibcon#end of sib2, iclass 25, count 0 2006.259.08:22:03.13#ibcon#*mode == 0, iclass 25, count 0 2006.259.08:22:03.13#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.259.08:22:03.13#ibcon#[27=USB\r\n] 2006.259.08:22:03.13#ibcon#*before write, iclass 25, count 0 2006.259.08:22:03.13#ibcon#enter sib2, iclass 25, count 0 2006.259.08:22:03.13#ibcon#flushed, iclass 25, count 0 2006.259.08:22:03.13#ibcon#about to write, iclass 25, count 0 2006.259.08:22:03.13#ibcon#wrote, iclass 25, count 0 2006.259.08:22:03.13#ibcon#about to read 3, iclass 25, count 0 2006.259.08:22:03.16#ibcon#read 3, iclass 25, count 0 2006.259.08:22:03.16#ibcon#about to read 4, iclass 25, count 0 2006.259.08:22:03.16#ibcon#read 4, iclass 25, count 0 2006.259.08:22:03.16#ibcon#about to read 5, iclass 25, count 0 2006.259.08:22:03.16#ibcon#read 5, iclass 25, count 0 2006.259.08:22:03.16#ibcon#about to read 6, iclass 25, count 0 2006.259.08:22:03.16#ibcon#read 6, iclass 25, count 0 2006.259.08:22:03.16#ibcon#end of sib2, iclass 25, count 0 2006.259.08:22:03.16#ibcon#*after write, iclass 25, count 0 2006.259.08:22:03.16#ibcon#*before return 0, iclass 25, count 0 2006.259.08:22:03.16#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.259.08:22:03.16#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.259.08:22:03.16#ibcon#about to clear, iclass 25 cls_cnt 0 2006.259.08:22:03.16#ibcon#cleared, iclass 25 cls_cnt 0 2006.259.08:22:03.16$vc4f8/vblo=5,744.99 2006.259.08:22:03.16#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.259.08:22:03.16#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.259.08:22:03.16#ibcon#ireg 17 cls_cnt 0 2006.259.08:22:03.16#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.259.08:22:03.16#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.259.08:22:03.16#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.259.08:22:03.16#ibcon#enter wrdev, iclass 27, count 0 2006.259.08:22:03.16#ibcon#first serial, iclass 27, count 0 2006.259.08:22:03.16#ibcon#enter sib2, iclass 27, count 0 2006.259.08:22:03.16#ibcon#flushed, iclass 27, count 0 2006.259.08:22:03.16#ibcon#about to write, iclass 27, count 0 2006.259.08:22:03.16#ibcon#wrote, iclass 27, count 0 2006.259.08:22:03.16#ibcon#about to read 3, iclass 27, count 0 2006.259.08:22:03.18#ibcon#read 3, iclass 27, count 0 2006.259.08:22:03.18#ibcon#about to read 4, iclass 27, count 0 2006.259.08:22:03.18#ibcon#read 4, iclass 27, count 0 2006.259.08:22:03.18#ibcon#about to read 5, iclass 27, count 0 2006.259.08:22:03.18#ibcon#read 5, iclass 27, count 0 2006.259.08:22:03.18#ibcon#about to read 6, iclass 27, count 0 2006.259.08:22:03.18#ibcon#read 6, iclass 27, count 0 2006.259.08:22:03.18#ibcon#end of sib2, iclass 27, count 0 2006.259.08:22:03.18#ibcon#*mode == 0, iclass 27, count 0 2006.259.08:22:03.18#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.259.08:22:03.18#ibcon#[28=FRQ=05,744.99\r\n] 2006.259.08:22:03.18#ibcon#*before write, iclass 27, count 0 2006.259.08:22:03.18#ibcon#enter sib2, iclass 27, count 0 2006.259.08:22:03.18#ibcon#flushed, iclass 27, count 0 2006.259.08:22:03.18#ibcon#about to write, iclass 27, count 0 2006.259.08:22:03.18#ibcon#wrote, iclass 27, count 0 2006.259.08:22:03.18#ibcon#about to read 3, iclass 27, count 0 2006.259.08:22:03.23#ibcon#read 3, iclass 27, count 0 2006.259.08:22:03.23#ibcon#about to read 4, iclass 27, count 0 2006.259.08:22:03.23#ibcon#read 4, iclass 27, count 0 2006.259.08:22:03.23#ibcon#about to read 5, iclass 27, count 0 2006.259.08:22:03.23#ibcon#read 5, iclass 27, count 0 2006.259.08:22:03.23#ibcon#about to read 6, iclass 27, count 0 2006.259.08:22:03.23#ibcon#read 6, iclass 27, count 0 2006.259.08:22:03.23#ibcon#end of sib2, iclass 27, count 0 2006.259.08:22:03.23#ibcon#*after write, iclass 27, count 0 2006.259.08:22:03.23#ibcon#*before return 0, iclass 27, count 0 2006.259.08:22:03.23#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.259.08:22:03.23#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.259.08:22:03.23#ibcon#about to clear, iclass 27 cls_cnt 0 2006.259.08:22:03.23#ibcon#cleared, iclass 27 cls_cnt 0 2006.259.08:22:03.23$vc4f8/vb=5,4 2006.259.08:22:03.23#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.259.08:22:03.23#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.259.08:22:03.23#ibcon#ireg 11 cls_cnt 2 2006.259.08:22:03.23#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.259.08:22:03.28#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.259.08:22:03.28#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.259.08:22:03.28#ibcon#enter wrdev, iclass 29, count 2 2006.259.08:22:03.28#ibcon#first serial, iclass 29, count 2 2006.259.08:22:03.28#ibcon#enter sib2, iclass 29, count 2 2006.259.08:22:03.28#ibcon#flushed, iclass 29, count 2 2006.259.08:22:03.28#ibcon#about to write, iclass 29, count 2 2006.259.08:22:03.28#ibcon#wrote, iclass 29, count 2 2006.259.08:22:03.28#ibcon#about to read 3, iclass 29, count 2 2006.259.08:22:03.30#ibcon#read 3, iclass 29, count 2 2006.259.08:22:03.30#ibcon#about to read 4, iclass 29, count 2 2006.259.08:22:03.30#ibcon#read 4, iclass 29, count 2 2006.259.08:22:03.30#ibcon#about to read 5, iclass 29, count 2 2006.259.08:22:03.30#ibcon#read 5, iclass 29, count 2 2006.259.08:22:03.30#ibcon#about to read 6, iclass 29, count 2 2006.259.08:22:03.30#ibcon#read 6, iclass 29, count 2 2006.259.08:22:03.30#ibcon#end of sib2, iclass 29, count 2 2006.259.08:22:03.30#ibcon#*mode == 0, iclass 29, count 2 2006.259.08:22:03.30#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.259.08:22:03.30#ibcon#[27=AT05-04\r\n] 2006.259.08:22:03.30#ibcon#*before write, iclass 29, count 2 2006.259.08:22:03.30#ibcon#enter sib2, iclass 29, count 2 2006.259.08:22:03.30#ibcon#flushed, iclass 29, count 2 2006.259.08:22:03.30#ibcon#about to write, iclass 29, count 2 2006.259.08:22:03.30#ibcon#wrote, iclass 29, count 2 2006.259.08:22:03.30#ibcon#about to read 3, iclass 29, count 2 2006.259.08:22:03.33#ibcon#read 3, iclass 29, count 2 2006.259.08:22:03.33#ibcon#about to read 4, iclass 29, count 2 2006.259.08:22:03.33#ibcon#read 4, iclass 29, count 2 2006.259.08:22:03.33#ibcon#about to read 5, iclass 29, count 2 2006.259.08:22:03.33#ibcon#read 5, iclass 29, count 2 2006.259.08:22:03.33#ibcon#about to read 6, iclass 29, count 2 2006.259.08:22:03.33#ibcon#read 6, iclass 29, count 2 2006.259.08:22:03.33#ibcon#end of sib2, iclass 29, count 2 2006.259.08:22:03.33#ibcon#*after write, iclass 29, count 2 2006.259.08:22:03.33#ibcon#*before return 0, iclass 29, count 2 2006.259.08:22:03.33#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.259.08:22:03.33#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.259.08:22:03.33#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.259.08:22:03.33#ibcon#ireg 7 cls_cnt 0 2006.259.08:22:03.33#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.259.08:22:03.44#abcon#<5=/04 2.6 4.8 21.76 851013.2\r\n> 2006.259.08:22:03.45#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.259.08:22:03.45#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.259.08:22:03.45#ibcon#enter wrdev, iclass 29, count 0 2006.259.08:22:03.45#ibcon#first serial, iclass 29, count 0 2006.259.08:22:03.45#ibcon#enter sib2, iclass 29, count 0 2006.259.08:22:03.45#ibcon#flushed, iclass 29, count 0 2006.259.08:22:03.45#ibcon#about to write, iclass 29, count 0 2006.259.08:22:03.45#ibcon#wrote, iclass 29, count 0 2006.259.08:22:03.45#ibcon#about to read 3, iclass 29, count 0 2006.259.08:22:03.46#abcon#{5=INTERFACE CLEAR} 2006.259.08:22:03.47#ibcon#read 3, iclass 29, count 0 2006.259.08:22:03.47#ibcon#about to read 4, iclass 29, count 0 2006.259.08:22:03.47#ibcon#read 4, iclass 29, count 0 2006.259.08:22:03.47#ibcon#about to read 5, iclass 29, count 0 2006.259.08:22:03.47#ibcon#read 5, iclass 29, count 0 2006.259.08:22:03.47#ibcon#about to read 6, iclass 29, count 0 2006.259.08:22:03.47#ibcon#read 6, iclass 29, count 0 2006.259.08:22:03.47#ibcon#end of sib2, iclass 29, count 0 2006.259.08:22:03.47#ibcon#*mode == 0, iclass 29, count 0 2006.259.08:22:03.47#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.259.08:22:03.47#ibcon#[27=USB\r\n] 2006.259.08:22:03.47#ibcon#*before write, iclass 29, count 0 2006.259.08:22:03.47#ibcon#enter sib2, iclass 29, count 0 2006.259.08:22:03.47#ibcon#flushed, iclass 29, count 0 2006.259.08:22:03.47#ibcon#about to write, iclass 29, count 0 2006.259.08:22:03.47#ibcon#wrote, iclass 29, count 0 2006.259.08:22:03.47#ibcon#about to read 3, iclass 29, count 0 2006.259.08:22:03.50#ibcon#read 3, iclass 29, count 0 2006.259.08:22:03.50#ibcon#about to read 4, iclass 29, count 0 2006.259.08:22:03.50#ibcon#read 4, iclass 29, count 0 2006.259.08:22:03.50#ibcon#about to read 5, iclass 29, count 0 2006.259.08:22:03.50#ibcon#read 5, iclass 29, count 0 2006.259.08:22:03.50#ibcon#about to read 6, iclass 29, count 0 2006.259.08:22:03.50#ibcon#read 6, iclass 29, count 0 2006.259.08:22:03.50#ibcon#end of sib2, iclass 29, count 0 2006.259.08:22:03.50#ibcon#*after write, iclass 29, count 0 2006.259.08:22:03.50#ibcon#*before return 0, iclass 29, count 0 2006.259.08:22:03.50#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.259.08:22:03.50#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.259.08:22:03.50#ibcon#about to clear, iclass 29 cls_cnt 0 2006.259.08:22:03.50#ibcon#cleared, iclass 29 cls_cnt 0 2006.259.08:22:03.50$vc4f8/vblo=6,752.99 2006.259.08:22:03.50#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.259.08:22:03.50#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.259.08:22:03.50#ibcon#ireg 17 cls_cnt 0 2006.259.08:22:03.50#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.259.08:22:03.50#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.259.08:22:03.50#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.259.08:22:03.50#ibcon#enter wrdev, iclass 34, count 0 2006.259.08:22:03.50#ibcon#first serial, iclass 34, count 0 2006.259.08:22:03.50#ibcon#enter sib2, iclass 34, count 0 2006.259.08:22:03.50#ibcon#flushed, iclass 34, count 0 2006.259.08:22:03.50#ibcon#about to write, iclass 34, count 0 2006.259.08:22:03.50#ibcon#wrote, iclass 34, count 0 2006.259.08:22:03.50#ibcon#about to read 3, iclass 34, count 0 2006.259.08:22:03.52#ibcon#read 3, iclass 34, count 0 2006.259.08:22:03.52#ibcon#about to read 4, iclass 34, count 0 2006.259.08:22:03.52#ibcon#read 4, iclass 34, count 0 2006.259.08:22:03.52#ibcon#about to read 5, iclass 34, count 0 2006.259.08:22:03.52#ibcon#read 5, iclass 34, count 0 2006.259.08:22:03.52#ibcon#about to read 6, iclass 34, count 0 2006.259.08:22:03.52#ibcon#read 6, iclass 34, count 0 2006.259.08:22:03.52#ibcon#end of sib2, iclass 34, count 0 2006.259.08:22:03.52#ibcon#*mode == 0, iclass 34, count 0 2006.259.08:22:03.52#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.259.08:22:03.52#ibcon#[28=FRQ=06,752.99\r\n] 2006.259.08:22:03.52#ibcon#*before write, iclass 34, count 0 2006.259.08:22:03.52#ibcon#enter sib2, iclass 34, count 0 2006.259.08:22:03.52#ibcon#flushed, iclass 34, count 0 2006.259.08:22:03.52#ibcon#about to write, iclass 34, count 0 2006.259.08:22:03.52#ibcon#wrote, iclass 34, count 0 2006.259.08:22:03.52#ibcon#about to read 3, iclass 34, count 0 2006.259.08:22:03.52#abcon#[5=S1D000X0/0*\r\n] 2006.259.08:22:03.56#ibcon#read 3, iclass 34, count 0 2006.259.08:22:03.56#ibcon#about to read 4, iclass 34, count 0 2006.259.08:22:03.56#ibcon#read 4, iclass 34, count 0 2006.259.08:22:03.56#ibcon#about to read 5, iclass 34, count 0 2006.259.08:22:03.56#ibcon#read 5, iclass 34, count 0 2006.259.08:22:03.56#ibcon#about to read 6, iclass 34, count 0 2006.259.08:22:03.56#ibcon#read 6, iclass 34, count 0 2006.259.08:22:03.56#ibcon#end of sib2, iclass 34, count 0 2006.259.08:22:03.56#ibcon#*after write, iclass 34, count 0 2006.259.08:22:03.56#ibcon#*before return 0, iclass 34, count 0 2006.259.08:22:03.56#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.259.08:22:03.56#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.259.08:22:03.56#ibcon#about to clear, iclass 34 cls_cnt 0 2006.259.08:22:03.56#ibcon#cleared, iclass 34 cls_cnt 0 2006.259.08:22:03.56$vc4f8/vb=6,4 2006.259.08:22:03.56#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.259.08:22:03.56#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.259.08:22:03.56#ibcon#ireg 11 cls_cnt 2 2006.259.08:22:03.56#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.259.08:22:03.62#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.259.08:22:03.62#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.259.08:22:03.62#ibcon#enter wrdev, iclass 37, count 2 2006.259.08:22:03.62#ibcon#first serial, iclass 37, count 2 2006.259.08:22:03.62#ibcon#enter sib2, iclass 37, count 2 2006.259.08:22:03.62#ibcon#flushed, iclass 37, count 2 2006.259.08:22:03.62#ibcon#about to write, iclass 37, count 2 2006.259.08:22:03.62#ibcon#wrote, iclass 37, count 2 2006.259.08:22:03.62#ibcon#about to read 3, iclass 37, count 2 2006.259.08:22:03.64#ibcon#read 3, iclass 37, count 2 2006.259.08:22:03.64#ibcon#about to read 4, iclass 37, count 2 2006.259.08:22:03.64#ibcon#read 4, iclass 37, count 2 2006.259.08:22:03.64#ibcon#about to read 5, iclass 37, count 2 2006.259.08:22:03.64#ibcon#read 5, iclass 37, count 2 2006.259.08:22:03.64#ibcon#about to read 6, iclass 37, count 2 2006.259.08:22:03.64#ibcon#read 6, iclass 37, count 2 2006.259.08:22:03.64#ibcon#end of sib2, iclass 37, count 2 2006.259.08:22:03.64#ibcon#*mode == 0, iclass 37, count 2 2006.259.08:22:03.64#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.259.08:22:03.64#ibcon#[27=AT06-04\r\n] 2006.259.08:22:03.64#ibcon#*before write, iclass 37, count 2 2006.259.08:22:03.64#ibcon#enter sib2, iclass 37, count 2 2006.259.08:22:03.64#ibcon#flushed, iclass 37, count 2 2006.259.08:22:03.64#ibcon#about to write, iclass 37, count 2 2006.259.08:22:03.64#ibcon#wrote, iclass 37, count 2 2006.259.08:22:03.64#ibcon#about to read 3, iclass 37, count 2 2006.259.08:22:03.67#ibcon#read 3, iclass 37, count 2 2006.259.08:22:03.67#ibcon#about to read 4, iclass 37, count 2 2006.259.08:22:03.67#ibcon#read 4, iclass 37, count 2 2006.259.08:22:03.67#ibcon#about to read 5, iclass 37, count 2 2006.259.08:22:03.67#ibcon#read 5, iclass 37, count 2 2006.259.08:22:03.67#ibcon#about to read 6, iclass 37, count 2 2006.259.08:22:03.67#ibcon#read 6, iclass 37, count 2 2006.259.08:22:03.67#ibcon#end of sib2, iclass 37, count 2 2006.259.08:22:03.67#ibcon#*after write, iclass 37, count 2 2006.259.08:22:03.67#ibcon#*before return 0, iclass 37, count 2 2006.259.08:22:03.67#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.259.08:22:03.67#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.259.08:22:03.67#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.259.08:22:03.67#ibcon#ireg 7 cls_cnt 0 2006.259.08:22:03.67#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.259.08:22:03.79#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.259.08:22:03.79#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.259.08:22:03.79#ibcon#enter wrdev, iclass 37, count 0 2006.259.08:22:03.79#ibcon#first serial, iclass 37, count 0 2006.259.08:22:03.79#ibcon#enter sib2, iclass 37, count 0 2006.259.08:22:03.79#ibcon#flushed, iclass 37, count 0 2006.259.08:22:03.79#ibcon#about to write, iclass 37, count 0 2006.259.08:22:03.79#ibcon#wrote, iclass 37, count 0 2006.259.08:22:03.79#ibcon#about to read 3, iclass 37, count 0 2006.259.08:22:03.81#ibcon#read 3, iclass 37, count 0 2006.259.08:22:03.81#ibcon#about to read 4, iclass 37, count 0 2006.259.08:22:03.81#ibcon#read 4, iclass 37, count 0 2006.259.08:22:03.81#ibcon#about to read 5, iclass 37, count 0 2006.259.08:22:03.81#ibcon#read 5, iclass 37, count 0 2006.259.08:22:03.81#ibcon#about to read 6, iclass 37, count 0 2006.259.08:22:03.81#ibcon#read 6, iclass 37, count 0 2006.259.08:22:03.81#ibcon#end of sib2, iclass 37, count 0 2006.259.08:22:03.81#ibcon#*mode == 0, iclass 37, count 0 2006.259.08:22:03.81#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.259.08:22:03.81#ibcon#[27=USB\r\n] 2006.259.08:22:03.81#ibcon#*before write, iclass 37, count 0 2006.259.08:22:03.81#ibcon#enter sib2, iclass 37, count 0 2006.259.08:22:03.81#ibcon#flushed, iclass 37, count 0 2006.259.08:22:03.81#ibcon#about to write, iclass 37, count 0 2006.259.08:22:03.81#ibcon#wrote, iclass 37, count 0 2006.259.08:22:03.81#ibcon#about to read 3, iclass 37, count 0 2006.259.08:22:03.84#ibcon#read 3, iclass 37, count 0 2006.259.08:22:03.84#ibcon#about to read 4, iclass 37, count 0 2006.259.08:22:03.84#ibcon#read 4, iclass 37, count 0 2006.259.08:22:03.84#ibcon#about to read 5, iclass 37, count 0 2006.259.08:22:03.84#ibcon#read 5, iclass 37, count 0 2006.259.08:22:03.84#ibcon#about to read 6, iclass 37, count 0 2006.259.08:22:03.84#ibcon#read 6, iclass 37, count 0 2006.259.08:22:03.84#ibcon#end of sib2, iclass 37, count 0 2006.259.08:22:03.84#ibcon#*after write, iclass 37, count 0 2006.259.08:22:03.84#ibcon#*before return 0, iclass 37, count 0 2006.259.08:22:03.84#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.259.08:22:03.84#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.259.08:22:03.84#ibcon#about to clear, iclass 37 cls_cnt 0 2006.259.08:22:03.84#ibcon#cleared, iclass 37 cls_cnt 0 2006.259.08:22:03.84$vc4f8/vabw=wide 2006.259.08:22:03.84#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.259.08:22:03.84#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.259.08:22:03.84#ibcon#ireg 8 cls_cnt 0 2006.259.08:22:03.84#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.259.08:22:03.84#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.259.08:22:03.84#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.259.08:22:03.84#ibcon#enter wrdev, iclass 39, count 0 2006.259.08:22:03.84#ibcon#first serial, iclass 39, count 0 2006.259.08:22:03.84#ibcon#enter sib2, iclass 39, count 0 2006.259.08:22:03.84#ibcon#flushed, iclass 39, count 0 2006.259.08:22:03.84#ibcon#about to write, iclass 39, count 0 2006.259.08:22:03.84#ibcon#wrote, iclass 39, count 0 2006.259.08:22:03.84#ibcon#about to read 3, iclass 39, count 0 2006.259.08:22:03.86#ibcon#read 3, iclass 39, count 0 2006.259.08:22:03.86#ibcon#about to read 4, iclass 39, count 0 2006.259.08:22:03.86#ibcon#read 4, iclass 39, count 0 2006.259.08:22:03.86#ibcon#about to read 5, iclass 39, count 0 2006.259.08:22:03.86#ibcon#read 5, iclass 39, count 0 2006.259.08:22:03.86#ibcon#about to read 6, iclass 39, count 0 2006.259.08:22:03.86#ibcon#read 6, iclass 39, count 0 2006.259.08:22:03.86#ibcon#end of sib2, iclass 39, count 0 2006.259.08:22:03.86#ibcon#*mode == 0, iclass 39, count 0 2006.259.08:22:03.86#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.259.08:22:03.86#ibcon#[25=BW32\r\n] 2006.259.08:22:03.86#ibcon#*before write, iclass 39, count 0 2006.259.08:22:03.86#ibcon#enter sib2, iclass 39, count 0 2006.259.08:22:03.86#ibcon#flushed, iclass 39, count 0 2006.259.08:22:03.86#ibcon#about to write, iclass 39, count 0 2006.259.08:22:03.86#ibcon#wrote, iclass 39, count 0 2006.259.08:22:03.86#ibcon#about to read 3, iclass 39, count 0 2006.259.08:22:03.89#ibcon#read 3, iclass 39, count 0 2006.259.08:22:03.89#ibcon#about to read 4, iclass 39, count 0 2006.259.08:22:03.89#ibcon#read 4, iclass 39, count 0 2006.259.08:22:03.89#ibcon#about to read 5, iclass 39, count 0 2006.259.08:22:03.89#ibcon#read 5, iclass 39, count 0 2006.259.08:22:03.89#ibcon#about to read 6, iclass 39, count 0 2006.259.08:22:03.89#ibcon#read 6, iclass 39, count 0 2006.259.08:22:03.89#ibcon#end of sib2, iclass 39, count 0 2006.259.08:22:03.89#ibcon#*after write, iclass 39, count 0 2006.259.08:22:03.89#ibcon#*before return 0, iclass 39, count 0 2006.259.08:22:03.89#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.259.08:22:03.89#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.259.08:22:03.89#ibcon#about to clear, iclass 39 cls_cnt 0 2006.259.08:22:03.89#ibcon#cleared, iclass 39 cls_cnt 0 2006.259.08:22:03.89$vc4f8/vbbw=wide 2006.259.08:22:03.89#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.259.08:22:03.89#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.259.08:22:03.89#ibcon#ireg 8 cls_cnt 0 2006.259.08:22:03.89#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.259.08:22:03.96#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.259.08:22:03.96#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.259.08:22:03.96#ibcon#enter wrdev, iclass 3, count 0 2006.259.08:22:03.96#ibcon#first serial, iclass 3, count 0 2006.259.08:22:03.96#ibcon#enter sib2, iclass 3, count 0 2006.259.08:22:03.96#ibcon#flushed, iclass 3, count 0 2006.259.08:22:03.96#ibcon#about to write, iclass 3, count 0 2006.259.08:22:03.96#ibcon#wrote, iclass 3, count 0 2006.259.08:22:03.96#ibcon#about to read 3, iclass 3, count 0 2006.259.08:22:03.98#ibcon#read 3, iclass 3, count 0 2006.259.08:22:03.98#ibcon#about to read 4, iclass 3, count 0 2006.259.08:22:03.98#ibcon#read 4, iclass 3, count 0 2006.259.08:22:03.98#ibcon#about to read 5, iclass 3, count 0 2006.259.08:22:03.98#ibcon#read 5, iclass 3, count 0 2006.259.08:22:03.98#ibcon#about to read 6, iclass 3, count 0 2006.259.08:22:03.98#ibcon#read 6, iclass 3, count 0 2006.259.08:22:03.98#ibcon#end of sib2, iclass 3, count 0 2006.259.08:22:03.98#ibcon#*mode == 0, iclass 3, count 0 2006.259.08:22:03.98#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.259.08:22:03.98#ibcon#[27=BW32\r\n] 2006.259.08:22:03.98#ibcon#*before write, iclass 3, count 0 2006.259.08:22:03.98#ibcon#enter sib2, iclass 3, count 0 2006.259.08:22:03.98#ibcon#flushed, iclass 3, count 0 2006.259.08:22:03.98#ibcon#about to write, iclass 3, count 0 2006.259.08:22:03.98#ibcon#wrote, iclass 3, count 0 2006.259.08:22:03.98#ibcon#about to read 3, iclass 3, count 0 2006.259.08:22:04.01#ibcon#read 3, iclass 3, count 0 2006.259.08:22:04.01#ibcon#about to read 4, iclass 3, count 0 2006.259.08:22:04.01#ibcon#read 4, iclass 3, count 0 2006.259.08:22:04.01#ibcon#about to read 5, iclass 3, count 0 2006.259.08:22:04.01#ibcon#read 5, iclass 3, count 0 2006.259.08:22:04.01#ibcon#about to read 6, iclass 3, count 0 2006.259.08:22:04.01#ibcon#read 6, iclass 3, count 0 2006.259.08:22:04.01#ibcon#end of sib2, iclass 3, count 0 2006.259.08:22:04.01#ibcon#*after write, iclass 3, count 0 2006.259.08:22:04.01#ibcon#*before return 0, iclass 3, count 0 2006.259.08:22:04.01#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.259.08:22:04.01#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.259.08:22:04.01#ibcon#about to clear, iclass 3 cls_cnt 0 2006.259.08:22:04.01#ibcon#cleared, iclass 3 cls_cnt 0 2006.259.08:22:04.01$4f8m12a/ifd4f 2006.259.08:22:04.01$ifd4f/lo= 2006.259.08:22:04.01$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.259.08:22:04.01$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.259.08:22:04.01$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.259.08:22:04.01$ifd4f/patch= 2006.259.08:22:04.01$ifd4f/patch=lo1,a1,a2,a3,a4 2006.259.08:22:04.01$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.259.08:22:04.01$ifd4f/patch=lo3,a5,a6,a7,a8 2006.259.08:22:04.01$4f8m12a/"form=m,16.000,1:2 2006.259.08:22:04.01$4f8m12a/"tpicd 2006.259.08:22:04.01$4f8m12a/echo=off 2006.259.08:22:04.01$4f8m12a/xlog=off 2006.259.08:22:04.01:!2006.259.08:24:10 2006.259.08:22:13.13#trakl#Source acquired 2006.259.08:22:15.13#flagr#flagr/antenna,acquired 2006.259.08:24:10.00:preob 2006.259.08:24:10.14/onsource/TRACKING 2006.259.08:24:10.14:!2006.259.08:24:20 2006.259.08:24:20.00:data_valid=on 2006.259.08:24:20.00:midob 2006.259.08:24:21.14/onsource/TRACKING 2006.259.08:24:21.14/wx/21.70,1013.2,85 2006.259.08:24:21.32/cable/+6.4590E-03 2006.259.08:24:22.41/va/01,08,usb,yes,32,33 2006.259.08:24:22.41/va/02,07,usb,yes,32,33 2006.259.08:24:22.41/va/03,08,usb,yes,24,24 2006.259.08:24:22.41/va/04,07,usb,yes,33,36 2006.259.08:24:22.41/va/05,07,usb,yes,37,39 2006.259.08:24:22.41/va/06,06,usb,yes,36,36 2006.259.08:24:22.41/va/07,06,usb,yes,37,37 2006.259.08:24:22.41/va/08,06,usb,yes,39,39 2006.259.08:24:22.64/valo/01,532.99,yes,locked 2006.259.08:24:22.64/valo/02,572.99,yes,locked 2006.259.08:24:22.64/valo/03,672.99,yes,locked 2006.259.08:24:22.64/valo/04,832.99,yes,locked 2006.259.08:24:22.64/valo/05,652.99,yes,locked 2006.259.08:24:22.64/valo/06,772.99,yes,locked 2006.259.08:24:22.64/valo/07,832.99,yes,locked 2006.259.08:24:22.64/valo/08,852.99,yes,locked 2006.259.08:24:23.73/vb/01,04,usb,yes,31,30 2006.259.08:24:23.73/vb/02,05,usb,yes,29,30 2006.259.08:24:23.73/vb/03,04,usb,yes,29,33 2006.259.08:24:23.73/vb/04,05,usb,yes,27,27 2006.259.08:24:23.73/vb/05,04,usb,yes,29,33 2006.259.08:24:23.73/vb/06,04,usb,yes,30,32 2006.259.08:24:23.73/vb/07,04,usb,yes,32,32 2006.259.08:24:23.73/vb/08,04,usb,yes,29,33 2006.259.08:24:23.96/vblo/01,632.99,yes,locked 2006.259.08:24:23.96/vblo/02,640.99,yes,locked 2006.259.08:24:23.96/vblo/03,656.99,yes,locked 2006.259.08:24:23.96/vblo/04,712.99,yes,locked 2006.259.08:24:23.96/vblo/05,744.99,yes,locked 2006.259.08:24:23.96/vblo/06,752.99,yes,locked 2006.259.08:24:23.96/vblo/07,734.99,yes,locked 2006.259.08:24:23.96/vblo/08,744.99,yes,locked 2006.259.08:24:24.11/vabw/8 2006.259.08:24:24.26/vbbw/8 2006.259.08:24:24.35/xfe/off,on,15.2 2006.259.08:24:24.75/ifatt/23,28,28,28 2006.259.08:24:25.08/fmout-gps/S +4.53E-07 2006.259.08:24:25.12:!2006.259.08:25:20 2006.259.08:25:20.00:data_valid=off 2006.259.08:25:20.00:postob 2006.259.08:25:20.23/cable/+6.4611E-03 2006.259.08:25:20.23/wx/21.68,1013.2,85 2006.259.08:25:21.08/fmout-gps/S +4.54E-07 2006.259.08:25:21.08:scan_name=259-0826,k06259,60 2006.259.08:25:21.08:source=0955+476,095819.67,472507.8,2000.0,ccw 2006.259.08:25:21.14#flagr#flagr/antenna,new-source 2006.259.08:25:22.14:checkk5 2006.259.08:25:22.55/chk_autoobs//k5ts1/ autoobs is running! 2006.259.08:25:22.98/chk_autoobs//k5ts2/ autoobs is running! 2006.259.08:25:23.68/chk_autoobs//k5ts3/ autoobs is running! 2006.259.08:25:24.09/chk_autoobs//k5ts4/ autoobs is running! 2006.259.08:25:24.47/chk_obsdata//k5ts1/T2590824??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.259.08:25:24.88/chk_obsdata//k5ts2/T2590824??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.259.08:25:25.34/chk_obsdata//k5ts3/T2590824??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.259.08:25:25.73/chk_obsdata//k5ts4/T2590824??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.259.08:25:26.48/k5log//k5ts1_log_newline 2006.259.08:25:27.25/k5log//k5ts2_log_newline 2006.259.08:25:28.27/k5log//k5ts3_log_newline 2006.259.08:25:29.02/k5log//k5ts4_log_newline 2006.259.08:25:29.08/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.259.08:25:29.08:4f8m12a=3 2006.259.08:25:29.08$4f8m12a/echo=on 2006.259.08:25:29.08$4f8m12a/pcalon 2006.259.08:25:29.08$pcalon/"no phase cal control is implemented here 2006.259.08:25:29.08$4f8m12a/"tpicd=stop 2006.259.08:25:29.08$4f8m12a/vc4f8 2006.259.08:25:29.08$vc4f8/valo=1,532.99 2006.259.08:25:29.09#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.259.08:25:29.09#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.259.08:25:29.09#ibcon#ireg 17 cls_cnt 0 2006.259.08:25:29.09#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.259.08:25:29.09#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.259.08:25:29.09#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.259.08:25:29.09#ibcon#enter wrdev, iclass 16, count 0 2006.259.08:25:29.09#ibcon#first serial, iclass 16, count 0 2006.259.08:25:29.09#ibcon#enter sib2, iclass 16, count 0 2006.259.08:25:29.09#ibcon#flushed, iclass 16, count 0 2006.259.08:25:29.09#ibcon#about to write, iclass 16, count 0 2006.259.08:25:29.09#ibcon#wrote, iclass 16, count 0 2006.259.08:25:29.09#ibcon#about to read 3, iclass 16, count 0 2006.259.08:25:29.11#ibcon#read 3, iclass 16, count 0 2006.259.08:25:29.11#ibcon#about to read 4, iclass 16, count 0 2006.259.08:25:29.11#ibcon#read 4, iclass 16, count 0 2006.259.08:25:29.11#ibcon#about to read 5, iclass 16, count 0 2006.259.08:25:29.11#ibcon#read 5, iclass 16, count 0 2006.259.08:25:29.11#ibcon#about to read 6, iclass 16, count 0 2006.259.08:25:29.11#ibcon#read 6, iclass 16, count 0 2006.259.08:25:29.11#ibcon#end of sib2, iclass 16, count 0 2006.259.08:25:29.11#ibcon#*mode == 0, iclass 16, count 0 2006.259.08:25:29.11#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.259.08:25:29.11#ibcon#[26=FRQ=01,532.99\r\n] 2006.259.08:25:29.11#ibcon#*before write, iclass 16, count 0 2006.259.08:25:29.11#ibcon#enter sib2, iclass 16, count 0 2006.259.08:25:29.11#ibcon#flushed, iclass 16, count 0 2006.259.08:25:29.11#ibcon#about to write, iclass 16, count 0 2006.259.08:25:29.11#ibcon#wrote, iclass 16, count 0 2006.259.08:25:29.11#ibcon#about to read 3, iclass 16, count 0 2006.259.08:25:29.16#ibcon#read 3, iclass 16, count 0 2006.259.08:25:29.16#ibcon#about to read 4, iclass 16, count 0 2006.259.08:25:29.16#ibcon#read 4, iclass 16, count 0 2006.259.08:25:29.16#ibcon#about to read 5, iclass 16, count 0 2006.259.08:25:29.16#ibcon#read 5, iclass 16, count 0 2006.259.08:25:29.16#ibcon#about to read 6, iclass 16, count 0 2006.259.08:25:29.16#ibcon#read 6, iclass 16, count 0 2006.259.08:25:29.16#ibcon#end of sib2, iclass 16, count 0 2006.259.08:25:29.16#ibcon#*after write, iclass 16, count 0 2006.259.08:25:29.16#ibcon#*before return 0, iclass 16, count 0 2006.259.08:25:29.16#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.259.08:25:29.16#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.259.08:25:29.16#ibcon#about to clear, iclass 16 cls_cnt 0 2006.259.08:25:29.16#ibcon#cleared, iclass 16 cls_cnt 0 2006.259.08:25:29.16$vc4f8/va=1,8 2006.259.08:25:29.16#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.259.08:25:29.16#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.259.08:25:29.16#ibcon#ireg 11 cls_cnt 2 2006.259.08:25:29.16#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.259.08:25:29.16#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.259.08:25:29.16#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.259.08:25:29.16#ibcon#enter wrdev, iclass 18, count 2 2006.259.08:25:29.16#ibcon#first serial, iclass 18, count 2 2006.259.08:25:29.16#ibcon#enter sib2, iclass 18, count 2 2006.259.08:25:29.16#ibcon#flushed, iclass 18, count 2 2006.259.08:25:29.16#ibcon#about to write, iclass 18, count 2 2006.259.08:25:29.16#ibcon#wrote, iclass 18, count 2 2006.259.08:25:29.16#ibcon#about to read 3, iclass 18, count 2 2006.259.08:25:29.18#ibcon#read 3, iclass 18, count 2 2006.259.08:25:29.18#ibcon#about to read 4, iclass 18, count 2 2006.259.08:25:29.18#ibcon#read 4, iclass 18, count 2 2006.259.08:25:29.18#ibcon#about to read 5, iclass 18, count 2 2006.259.08:25:29.18#ibcon#read 5, iclass 18, count 2 2006.259.08:25:29.18#ibcon#about to read 6, iclass 18, count 2 2006.259.08:25:29.18#ibcon#read 6, iclass 18, count 2 2006.259.08:25:29.18#ibcon#end of sib2, iclass 18, count 2 2006.259.08:25:29.18#ibcon#*mode == 0, iclass 18, count 2 2006.259.08:25:29.18#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.259.08:25:29.18#ibcon#[25=AT01-08\r\n] 2006.259.08:25:29.18#ibcon#*before write, iclass 18, count 2 2006.259.08:25:29.18#ibcon#enter sib2, iclass 18, count 2 2006.259.08:25:29.18#ibcon#flushed, iclass 18, count 2 2006.259.08:25:29.18#ibcon#about to write, iclass 18, count 2 2006.259.08:25:29.18#ibcon#wrote, iclass 18, count 2 2006.259.08:25:29.18#ibcon#about to read 3, iclass 18, count 2 2006.259.08:25:29.21#ibcon#read 3, iclass 18, count 2 2006.259.08:25:29.21#ibcon#about to read 4, iclass 18, count 2 2006.259.08:25:29.21#ibcon#read 4, iclass 18, count 2 2006.259.08:25:29.21#ibcon#about to read 5, iclass 18, count 2 2006.259.08:25:29.21#ibcon#read 5, iclass 18, count 2 2006.259.08:25:29.21#ibcon#about to read 6, iclass 18, count 2 2006.259.08:25:29.21#ibcon#read 6, iclass 18, count 2 2006.259.08:25:29.21#ibcon#end of sib2, iclass 18, count 2 2006.259.08:25:29.21#ibcon#*after write, iclass 18, count 2 2006.259.08:25:29.21#ibcon#*before return 0, iclass 18, count 2 2006.259.08:25:29.21#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.259.08:25:29.21#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.259.08:25:29.21#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.259.08:25:29.21#ibcon#ireg 7 cls_cnt 0 2006.259.08:25:29.21#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.259.08:25:29.33#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.259.08:25:29.33#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.259.08:25:29.33#ibcon#enter wrdev, iclass 18, count 0 2006.259.08:25:29.33#ibcon#first serial, iclass 18, count 0 2006.259.08:25:29.33#ibcon#enter sib2, iclass 18, count 0 2006.259.08:25:29.33#ibcon#flushed, iclass 18, count 0 2006.259.08:25:29.33#ibcon#about to write, iclass 18, count 0 2006.259.08:25:29.33#ibcon#wrote, iclass 18, count 0 2006.259.08:25:29.33#ibcon#about to read 3, iclass 18, count 0 2006.259.08:25:29.35#ibcon#read 3, iclass 18, count 0 2006.259.08:25:29.35#ibcon#about to read 4, iclass 18, count 0 2006.259.08:25:29.35#ibcon#read 4, iclass 18, count 0 2006.259.08:25:29.35#ibcon#about to read 5, iclass 18, count 0 2006.259.08:25:29.35#ibcon#read 5, iclass 18, count 0 2006.259.08:25:29.35#ibcon#about to read 6, iclass 18, count 0 2006.259.08:25:29.35#ibcon#read 6, iclass 18, count 0 2006.259.08:25:29.35#ibcon#end of sib2, iclass 18, count 0 2006.259.08:25:29.35#ibcon#*mode == 0, iclass 18, count 0 2006.259.08:25:29.35#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.259.08:25:29.35#ibcon#[25=USB\r\n] 2006.259.08:25:29.35#ibcon#*before write, iclass 18, count 0 2006.259.08:25:29.35#ibcon#enter sib2, iclass 18, count 0 2006.259.08:25:29.35#ibcon#flushed, iclass 18, count 0 2006.259.08:25:29.35#ibcon#about to write, iclass 18, count 0 2006.259.08:25:29.35#ibcon#wrote, iclass 18, count 0 2006.259.08:25:29.35#ibcon#about to read 3, iclass 18, count 0 2006.259.08:25:29.38#ibcon#read 3, iclass 18, count 0 2006.259.08:25:29.38#ibcon#about to read 4, iclass 18, count 0 2006.259.08:25:29.38#ibcon#read 4, iclass 18, count 0 2006.259.08:25:29.38#ibcon#about to read 5, iclass 18, count 0 2006.259.08:25:29.38#ibcon#read 5, iclass 18, count 0 2006.259.08:25:29.38#ibcon#about to read 6, iclass 18, count 0 2006.259.08:25:29.38#ibcon#read 6, iclass 18, count 0 2006.259.08:25:29.38#ibcon#end of sib2, iclass 18, count 0 2006.259.08:25:29.38#ibcon#*after write, iclass 18, count 0 2006.259.08:25:29.38#ibcon#*before return 0, iclass 18, count 0 2006.259.08:25:29.38#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.259.08:25:29.38#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.259.08:25:29.38#ibcon#about to clear, iclass 18 cls_cnt 0 2006.259.08:25:29.38#ibcon#cleared, iclass 18 cls_cnt 0 2006.259.08:25:29.38$vc4f8/valo=2,572.99 2006.259.08:25:29.38#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.259.08:25:29.38#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.259.08:25:29.38#ibcon#ireg 17 cls_cnt 0 2006.259.08:25:29.38#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.259.08:25:29.38#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.259.08:25:29.38#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.259.08:25:29.38#ibcon#enter wrdev, iclass 20, count 0 2006.259.08:25:29.38#ibcon#first serial, iclass 20, count 0 2006.259.08:25:29.38#ibcon#enter sib2, iclass 20, count 0 2006.259.08:25:29.38#ibcon#flushed, iclass 20, count 0 2006.259.08:25:29.38#ibcon#about to write, iclass 20, count 0 2006.259.08:25:29.38#ibcon#wrote, iclass 20, count 0 2006.259.08:25:29.38#ibcon#about to read 3, iclass 20, count 0 2006.259.08:25:29.40#ibcon#read 3, iclass 20, count 0 2006.259.08:25:29.40#ibcon#about to read 4, iclass 20, count 0 2006.259.08:25:29.40#ibcon#read 4, iclass 20, count 0 2006.259.08:25:29.40#ibcon#about to read 5, iclass 20, count 0 2006.259.08:25:29.40#ibcon#read 5, iclass 20, count 0 2006.259.08:25:29.40#ibcon#about to read 6, iclass 20, count 0 2006.259.08:25:29.40#ibcon#read 6, iclass 20, count 0 2006.259.08:25:29.40#ibcon#end of sib2, iclass 20, count 0 2006.259.08:25:29.40#ibcon#*mode == 0, iclass 20, count 0 2006.259.08:25:29.40#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.259.08:25:29.40#ibcon#[26=FRQ=02,572.99\r\n] 2006.259.08:25:29.40#ibcon#*before write, iclass 20, count 0 2006.259.08:25:29.40#ibcon#enter sib2, iclass 20, count 0 2006.259.08:25:29.40#ibcon#flushed, iclass 20, count 0 2006.259.08:25:29.40#ibcon#about to write, iclass 20, count 0 2006.259.08:25:29.40#ibcon#wrote, iclass 20, count 0 2006.259.08:25:29.40#ibcon#about to read 3, iclass 20, count 0 2006.259.08:25:29.44#ibcon#read 3, iclass 20, count 0 2006.259.08:25:29.44#ibcon#about to read 4, iclass 20, count 0 2006.259.08:25:29.44#ibcon#read 4, iclass 20, count 0 2006.259.08:25:29.44#ibcon#about to read 5, iclass 20, count 0 2006.259.08:25:29.44#ibcon#read 5, iclass 20, count 0 2006.259.08:25:29.44#ibcon#about to read 6, iclass 20, count 0 2006.259.08:25:29.44#ibcon#read 6, iclass 20, count 0 2006.259.08:25:29.44#ibcon#end of sib2, iclass 20, count 0 2006.259.08:25:29.44#ibcon#*after write, iclass 20, count 0 2006.259.08:25:29.44#ibcon#*before return 0, iclass 20, count 0 2006.259.08:25:29.44#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.259.08:25:29.44#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.259.08:25:29.44#ibcon#about to clear, iclass 20 cls_cnt 0 2006.259.08:25:29.44#ibcon#cleared, iclass 20 cls_cnt 0 2006.259.08:25:29.44$vc4f8/va=2,7 2006.259.08:25:29.44#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.259.08:25:29.44#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.259.08:25:29.44#ibcon#ireg 11 cls_cnt 2 2006.259.08:25:29.44#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.259.08:25:29.50#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.259.08:25:29.50#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.259.08:25:29.50#ibcon#enter wrdev, iclass 22, count 2 2006.259.08:25:29.50#ibcon#first serial, iclass 22, count 2 2006.259.08:25:29.50#ibcon#enter sib2, iclass 22, count 2 2006.259.08:25:29.50#ibcon#flushed, iclass 22, count 2 2006.259.08:25:29.50#ibcon#about to write, iclass 22, count 2 2006.259.08:25:29.50#ibcon#wrote, iclass 22, count 2 2006.259.08:25:29.50#ibcon#about to read 3, iclass 22, count 2 2006.259.08:25:29.52#ibcon#read 3, iclass 22, count 2 2006.259.08:25:29.52#ibcon#about to read 4, iclass 22, count 2 2006.259.08:25:29.52#ibcon#read 4, iclass 22, count 2 2006.259.08:25:29.52#ibcon#about to read 5, iclass 22, count 2 2006.259.08:25:29.52#ibcon#read 5, iclass 22, count 2 2006.259.08:25:29.52#ibcon#about to read 6, iclass 22, count 2 2006.259.08:25:29.52#ibcon#read 6, iclass 22, count 2 2006.259.08:25:29.52#ibcon#end of sib2, iclass 22, count 2 2006.259.08:25:29.52#ibcon#*mode == 0, iclass 22, count 2 2006.259.08:25:29.52#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.259.08:25:29.52#ibcon#[25=AT02-07\r\n] 2006.259.08:25:29.52#ibcon#*before write, iclass 22, count 2 2006.259.08:25:29.52#ibcon#enter sib2, iclass 22, count 2 2006.259.08:25:29.52#ibcon#flushed, iclass 22, count 2 2006.259.08:25:29.52#ibcon#about to write, iclass 22, count 2 2006.259.08:25:29.52#ibcon#wrote, iclass 22, count 2 2006.259.08:25:29.52#ibcon#about to read 3, iclass 22, count 2 2006.259.08:25:29.56#ibcon#read 3, iclass 22, count 2 2006.259.08:25:29.56#ibcon#about to read 4, iclass 22, count 2 2006.259.08:25:29.56#ibcon#read 4, iclass 22, count 2 2006.259.08:25:29.56#ibcon#about to read 5, iclass 22, count 2 2006.259.08:25:29.56#ibcon#read 5, iclass 22, count 2 2006.259.08:25:29.56#ibcon#about to read 6, iclass 22, count 2 2006.259.08:25:29.56#ibcon#read 6, iclass 22, count 2 2006.259.08:25:29.56#ibcon#end of sib2, iclass 22, count 2 2006.259.08:25:29.56#ibcon#*after write, iclass 22, count 2 2006.259.08:25:29.56#ibcon#*before return 0, iclass 22, count 2 2006.259.08:25:29.56#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.259.08:25:29.56#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.259.08:25:29.56#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.259.08:25:29.56#ibcon#ireg 7 cls_cnt 0 2006.259.08:25:29.56#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.259.08:25:29.68#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.259.08:25:29.68#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.259.08:25:29.68#ibcon#enter wrdev, iclass 22, count 0 2006.259.08:25:29.68#ibcon#first serial, iclass 22, count 0 2006.259.08:25:29.68#ibcon#enter sib2, iclass 22, count 0 2006.259.08:25:29.68#ibcon#flushed, iclass 22, count 0 2006.259.08:25:29.68#ibcon#about to write, iclass 22, count 0 2006.259.08:25:29.68#ibcon#wrote, iclass 22, count 0 2006.259.08:25:29.68#ibcon#about to read 3, iclass 22, count 0 2006.259.08:25:29.70#ibcon#read 3, iclass 22, count 0 2006.259.08:25:29.70#ibcon#about to read 4, iclass 22, count 0 2006.259.08:25:29.70#ibcon#read 4, iclass 22, count 0 2006.259.08:25:29.70#ibcon#about to read 5, iclass 22, count 0 2006.259.08:25:29.70#ibcon#read 5, iclass 22, count 0 2006.259.08:25:29.70#ibcon#about to read 6, iclass 22, count 0 2006.259.08:25:29.70#ibcon#read 6, iclass 22, count 0 2006.259.08:25:29.70#ibcon#end of sib2, iclass 22, count 0 2006.259.08:25:29.70#ibcon#*mode == 0, iclass 22, count 0 2006.259.08:25:29.70#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.259.08:25:29.70#ibcon#[25=USB\r\n] 2006.259.08:25:29.70#ibcon#*before write, iclass 22, count 0 2006.259.08:25:29.70#ibcon#enter sib2, iclass 22, count 0 2006.259.08:25:29.70#ibcon#flushed, iclass 22, count 0 2006.259.08:25:29.70#ibcon#about to write, iclass 22, count 0 2006.259.08:25:29.70#ibcon#wrote, iclass 22, count 0 2006.259.08:25:29.70#ibcon#about to read 3, iclass 22, count 0 2006.259.08:25:29.73#ibcon#read 3, iclass 22, count 0 2006.259.08:25:29.73#ibcon#about to read 4, iclass 22, count 0 2006.259.08:25:29.73#ibcon#read 4, iclass 22, count 0 2006.259.08:25:29.73#ibcon#about to read 5, iclass 22, count 0 2006.259.08:25:29.73#ibcon#read 5, iclass 22, count 0 2006.259.08:25:29.73#ibcon#about to read 6, iclass 22, count 0 2006.259.08:25:29.73#ibcon#read 6, iclass 22, count 0 2006.259.08:25:29.73#ibcon#end of sib2, iclass 22, count 0 2006.259.08:25:29.73#ibcon#*after write, iclass 22, count 0 2006.259.08:25:29.73#ibcon#*before return 0, iclass 22, count 0 2006.259.08:25:29.73#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.259.08:25:29.73#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.259.08:25:29.73#ibcon#about to clear, iclass 22 cls_cnt 0 2006.259.08:25:29.73#ibcon#cleared, iclass 22 cls_cnt 0 2006.259.08:25:29.73$vc4f8/valo=3,672.99 2006.259.08:25:29.73#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.259.08:25:29.73#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.259.08:25:29.73#ibcon#ireg 17 cls_cnt 0 2006.259.08:25:29.73#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.259.08:25:29.73#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.259.08:25:29.73#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.259.08:25:29.73#ibcon#enter wrdev, iclass 24, count 0 2006.259.08:25:29.73#ibcon#first serial, iclass 24, count 0 2006.259.08:25:29.73#ibcon#enter sib2, iclass 24, count 0 2006.259.08:25:29.73#ibcon#flushed, iclass 24, count 0 2006.259.08:25:29.73#ibcon#about to write, iclass 24, count 0 2006.259.08:25:29.73#ibcon#wrote, iclass 24, count 0 2006.259.08:25:29.73#ibcon#about to read 3, iclass 24, count 0 2006.259.08:25:29.75#ibcon#read 3, iclass 24, count 0 2006.259.08:25:29.75#ibcon#about to read 4, iclass 24, count 0 2006.259.08:25:29.75#ibcon#read 4, iclass 24, count 0 2006.259.08:25:29.75#ibcon#about to read 5, iclass 24, count 0 2006.259.08:25:29.75#ibcon#read 5, iclass 24, count 0 2006.259.08:25:29.75#ibcon#about to read 6, iclass 24, count 0 2006.259.08:25:29.75#ibcon#read 6, iclass 24, count 0 2006.259.08:25:29.75#ibcon#end of sib2, iclass 24, count 0 2006.259.08:25:29.75#ibcon#*mode == 0, iclass 24, count 0 2006.259.08:25:29.75#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.259.08:25:29.75#ibcon#[26=FRQ=03,672.99\r\n] 2006.259.08:25:29.75#ibcon#*before write, iclass 24, count 0 2006.259.08:25:29.75#ibcon#enter sib2, iclass 24, count 0 2006.259.08:25:29.75#ibcon#flushed, iclass 24, count 0 2006.259.08:25:29.75#ibcon#about to write, iclass 24, count 0 2006.259.08:25:29.75#ibcon#wrote, iclass 24, count 0 2006.259.08:25:29.75#ibcon#about to read 3, iclass 24, count 0 2006.259.08:25:29.80#ibcon#read 3, iclass 24, count 0 2006.259.08:25:29.80#ibcon#about to read 4, iclass 24, count 0 2006.259.08:25:29.80#ibcon#read 4, iclass 24, count 0 2006.259.08:25:29.80#ibcon#about to read 5, iclass 24, count 0 2006.259.08:25:29.80#ibcon#read 5, iclass 24, count 0 2006.259.08:25:29.80#ibcon#about to read 6, iclass 24, count 0 2006.259.08:25:29.80#ibcon#read 6, iclass 24, count 0 2006.259.08:25:29.80#ibcon#end of sib2, iclass 24, count 0 2006.259.08:25:29.80#ibcon#*after write, iclass 24, count 0 2006.259.08:25:29.80#ibcon#*before return 0, iclass 24, count 0 2006.259.08:25:29.80#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.259.08:25:29.80#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.259.08:25:29.80#ibcon#about to clear, iclass 24 cls_cnt 0 2006.259.08:25:29.80#ibcon#cleared, iclass 24 cls_cnt 0 2006.259.08:25:29.80$vc4f8/va=3,8 2006.259.08:25:29.80#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.259.08:25:29.80#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.259.08:25:29.80#ibcon#ireg 11 cls_cnt 2 2006.259.08:25:29.80#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.259.08:25:29.85#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.259.08:25:29.85#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.259.08:25:29.85#ibcon#enter wrdev, iclass 26, count 2 2006.259.08:25:29.85#ibcon#first serial, iclass 26, count 2 2006.259.08:25:29.85#ibcon#enter sib2, iclass 26, count 2 2006.259.08:25:29.85#ibcon#flushed, iclass 26, count 2 2006.259.08:25:29.85#ibcon#about to write, iclass 26, count 2 2006.259.08:25:29.85#ibcon#wrote, iclass 26, count 2 2006.259.08:25:29.85#ibcon#about to read 3, iclass 26, count 2 2006.259.08:25:29.87#ibcon#read 3, iclass 26, count 2 2006.259.08:25:29.87#ibcon#about to read 4, iclass 26, count 2 2006.259.08:25:29.87#ibcon#read 4, iclass 26, count 2 2006.259.08:25:29.87#ibcon#about to read 5, iclass 26, count 2 2006.259.08:25:29.87#ibcon#read 5, iclass 26, count 2 2006.259.08:25:29.87#ibcon#about to read 6, iclass 26, count 2 2006.259.08:25:29.87#ibcon#read 6, iclass 26, count 2 2006.259.08:25:29.87#ibcon#end of sib2, iclass 26, count 2 2006.259.08:25:29.87#ibcon#*mode == 0, iclass 26, count 2 2006.259.08:25:29.87#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.259.08:25:29.87#ibcon#[25=AT03-08\r\n] 2006.259.08:25:29.87#ibcon#*before write, iclass 26, count 2 2006.259.08:25:29.87#ibcon#enter sib2, iclass 26, count 2 2006.259.08:25:29.87#ibcon#flushed, iclass 26, count 2 2006.259.08:25:29.87#ibcon#about to write, iclass 26, count 2 2006.259.08:25:29.87#ibcon#wrote, iclass 26, count 2 2006.259.08:25:29.87#ibcon#about to read 3, iclass 26, count 2 2006.259.08:25:29.91#ibcon#read 3, iclass 26, count 2 2006.259.08:25:29.91#ibcon#about to read 4, iclass 26, count 2 2006.259.08:25:29.91#ibcon#read 4, iclass 26, count 2 2006.259.08:25:29.91#ibcon#about to read 5, iclass 26, count 2 2006.259.08:25:29.91#ibcon#read 5, iclass 26, count 2 2006.259.08:25:29.91#ibcon#about to read 6, iclass 26, count 2 2006.259.08:25:29.91#ibcon#read 6, iclass 26, count 2 2006.259.08:25:29.91#ibcon#end of sib2, iclass 26, count 2 2006.259.08:25:29.91#ibcon#*after write, iclass 26, count 2 2006.259.08:25:29.91#ibcon#*before return 0, iclass 26, count 2 2006.259.08:25:29.91#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.259.08:25:29.91#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.259.08:25:29.91#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.259.08:25:29.91#ibcon#ireg 7 cls_cnt 0 2006.259.08:25:29.91#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.259.08:25:30.03#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.259.08:25:30.03#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.259.08:25:30.03#ibcon#enter wrdev, iclass 26, count 0 2006.259.08:25:30.03#ibcon#first serial, iclass 26, count 0 2006.259.08:25:30.03#ibcon#enter sib2, iclass 26, count 0 2006.259.08:25:30.03#ibcon#flushed, iclass 26, count 0 2006.259.08:25:30.03#ibcon#about to write, iclass 26, count 0 2006.259.08:25:30.03#ibcon#wrote, iclass 26, count 0 2006.259.08:25:30.03#ibcon#about to read 3, iclass 26, count 0 2006.259.08:25:30.05#ibcon#read 3, iclass 26, count 0 2006.259.08:25:30.05#ibcon#about to read 4, iclass 26, count 0 2006.259.08:25:30.05#ibcon#read 4, iclass 26, count 0 2006.259.08:25:30.05#ibcon#about to read 5, iclass 26, count 0 2006.259.08:25:30.05#ibcon#read 5, iclass 26, count 0 2006.259.08:25:30.05#ibcon#about to read 6, iclass 26, count 0 2006.259.08:25:30.05#ibcon#read 6, iclass 26, count 0 2006.259.08:25:30.05#ibcon#end of sib2, iclass 26, count 0 2006.259.08:25:30.05#ibcon#*mode == 0, iclass 26, count 0 2006.259.08:25:30.05#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.259.08:25:30.05#ibcon#[25=USB\r\n] 2006.259.08:25:30.05#ibcon#*before write, iclass 26, count 0 2006.259.08:25:30.05#ibcon#enter sib2, iclass 26, count 0 2006.259.08:25:30.05#ibcon#flushed, iclass 26, count 0 2006.259.08:25:30.05#ibcon#about to write, iclass 26, count 0 2006.259.08:25:30.05#ibcon#wrote, iclass 26, count 0 2006.259.08:25:30.05#ibcon#about to read 3, iclass 26, count 0 2006.259.08:25:30.08#ibcon#read 3, iclass 26, count 0 2006.259.08:25:30.08#ibcon#about to read 4, iclass 26, count 0 2006.259.08:25:30.08#ibcon#read 4, iclass 26, count 0 2006.259.08:25:30.08#ibcon#about to read 5, iclass 26, count 0 2006.259.08:25:30.08#ibcon#read 5, iclass 26, count 0 2006.259.08:25:30.08#ibcon#about to read 6, iclass 26, count 0 2006.259.08:25:30.08#ibcon#read 6, iclass 26, count 0 2006.259.08:25:30.08#ibcon#end of sib2, iclass 26, count 0 2006.259.08:25:30.08#ibcon#*after write, iclass 26, count 0 2006.259.08:25:30.08#ibcon#*before return 0, iclass 26, count 0 2006.259.08:25:30.08#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.259.08:25:30.08#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.259.08:25:30.08#ibcon#about to clear, iclass 26 cls_cnt 0 2006.259.08:25:30.08#ibcon#cleared, iclass 26 cls_cnt 0 2006.259.08:25:30.08$vc4f8/valo=4,832.99 2006.259.08:25:30.08#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.259.08:25:30.08#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.259.08:25:30.08#ibcon#ireg 17 cls_cnt 0 2006.259.08:25:30.08#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.259.08:25:30.08#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.259.08:25:30.08#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.259.08:25:30.08#ibcon#enter wrdev, iclass 28, count 0 2006.259.08:25:30.08#ibcon#first serial, iclass 28, count 0 2006.259.08:25:30.08#ibcon#enter sib2, iclass 28, count 0 2006.259.08:25:30.08#ibcon#flushed, iclass 28, count 0 2006.259.08:25:30.08#ibcon#about to write, iclass 28, count 0 2006.259.08:25:30.08#ibcon#wrote, iclass 28, count 0 2006.259.08:25:30.08#ibcon#about to read 3, iclass 28, count 0 2006.259.08:25:30.10#ibcon#read 3, iclass 28, count 0 2006.259.08:25:30.10#ibcon#about to read 4, iclass 28, count 0 2006.259.08:25:30.10#ibcon#read 4, iclass 28, count 0 2006.259.08:25:30.10#ibcon#about to read 5, iclass 28, count 0 2006.259.08:25:30.10#ibcon#read 5, iclass 28, count 0 2006.259.08:25:30.10#ibcon#about to read 6, iclass 28, count 0 2006.259.08:25:30.10#ibcon#read 6, iclass 28, count 0 2006.259.08:25:30.10#ibcon#end of sib2, iclass 28, count 0 2006.259.08:25:30.10#ibcon#*mode == 0, iclass 28, count 0 2006.259.08:25:30.10#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.259.08:25:30.10#ibcon#[26=FRQ=04,832.99\r\n] 2006.259.08:25:30.10#ibcon#*before write, iclass 28, count 0 2006.259.08:25:30.10#ibcon#enter sib2, iclass 28, count 0 2006.259.08:25:30.10#ibcon#flushed, iclass 28, count 0 2006.259.08:25:30.10#ibcon#about to write, iclass 28, count 0 2006.259.08:25:30.10#ibcon#wrote, iclass 28, count 0 2006.259.08:25:30.10#ibcon#about to read 3, iclass 28, count 0 2006.259.08:25:30.14#ibcon#read 3, iclass 28, count 0 2006.259.08:25:30.14#ibcon#about to read 4, iclass 28, count 0 2006.259.08:25:30.14#ibcon#read 4, iclass 28, count 0 2006.259.08:25:30.14#ibcon#about to read 5, iclass 28, count 0 2006.259.08:25:30.14#ibcon#read 5, iclass 28, count 0 2006.259.08:25:30.14#ibcon#about to read 6, iclass 28, count 0 2006.259.08:25:30.14#ibcon#read 6, iclass 28, count 0 2006.259.08:25:30.14#ibcon#end of sib2, iclass 28, count 0 2006.259.08:25:30.14#ibcon#*after write, iclass 28, count 0 2006.259.08:25:30.14#ibcon#*before return 0, iclass 28, count 0 2006.259.08:25:30.14#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.259.08:25:30.14#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.259.08:25:30.14#ibcon#about to clear, iclass 28 cls_cnt 0 2006.259.08:25:30.14#ibcon#cleared, iclass 28 cls_cnt 0 2006.259.08:25:30.14$vc4f8/va=4,7 2006.259.08:25:30.14#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.259.08:25:30.14#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.259.08:25:30.14#ibcon#ireg 11 cls_cnt 2 2006.259.08:25:30.14#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.259.08:25:30.20#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.259.08:25:30.20#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.259.08:25:30.20#ibcon#enter wrdev, iclass 30, count 2 2006.259.08:25:30.20#ibcon#first serial, iclass 30, count 2 2006.259.08:25:30.20#ibcon#enter sib2, iclass 30, count 2 2006.259.08:25:30.20#ibcon#flushed, iclass 30, count 2 2006.259.08:25:30.20#ibcon#about to write, iclass 30, count 2 2006.259.08:25:30.20#ibcon#wrote, iclass 30, count 2 2006.259.08:25:30.20#ibcon#about to read 3, iclass 30, count 2 2006.259.08:25:30.22#ibcon#read 3, iclass 30, count 2 2006.259.08:25:30.22#ibcon#about to read 4, iclass 30, count 2 2006.259.08:25:30.22#ibcon#read 4, iclass 30, count 2 2006.259.08:25:30.22#ibcon#about to read 5, iclass 30, count 2 2006.259.08:25:30.22#ibcon#read 5, iclass 30, count 2 2006.259.08:25:30.22#ibcon#about to read 6, iclass 30, count 2 2006.259.08:25:30.22#ibcon#read 6, iclass 30, count 2 2006.259.08:25:30.22#ibcon#end of sib2, iclass 30, count 2 2006.259.08:25:30.22#ibcon#*mode == 0, iclass 30, count 2 2006.259.08:25:30.22#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.259.08:25:30.22#ibcon#[25=AT04-07\r\n] 2006.259.08:25:30.22#ibcon#*before write, iclass 30, count 2 2006.259.08:25:30.22#ibcon#enter sib2, iclass 30, count 2 2006.259.08:25:30.22#ibcon#flushed, iclass 30, count 2 2006.259.08:25:30.22#ibcon#about to write, iclass 30, count 2 2006.259.08:25:30.22#ibcon#wrote, iclass 30, count 2 2006.259.08:25:30.22#ibcon#about to read 3, iclass 30, count 2 2006.259.08:25:30.25#ibcon#read 3, iclass 30, count 2 2006.259.08:25:30.25#ibcon#about to read 4, iclass 30, count 2 2006.259.08:25:30.25#ibcon#read 4, iclass 30, count 2 2006.259.08:25:30.25#ibcon#about to read 5, iclass 30, count 2 2006.259.08:25:30.25#ibcon#read 5, iclass 30, count 2 2006.259.08:25:30.25#ibcon#about to read 6, iclass 30, count 2 2006.259.08:25:30.25#ibcon#read 6, iclass 30, count 2 2006.259.08:25:30.25#ibcon#end of sib2, iclass 30, count 2 2006.259.08:25:30.25#ibcon#*after write, iclass 30, count 2 2006.259.08:25:30.25#ibcon#*before return 0, iclass 30, count 2 2006.259.08:25:30.25#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.259.08:25:30.25#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.259.08:25:30.25#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.259.08:25:30.25#ibcon#ireg 7 cls_cnt 0 2006.259.08:25:30.25#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.259.08:25:30.37#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.259.08:25:30.37#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.259.08:25:30.37#ibcon#enter wrdev, iclass 30, count 0 2006.259.08:25:30.37#ibcon#first serial, iclass 30, count 0 2006.259.08:25:30.37#ibcon#enter sib2, iclass 30, count 0 2006.259.08:25:30.37#ibcon#flushed, iclass 30, count 0 2006.259.08:25:30.37#ibcon#about to write, iclass 30, count 0 2006.259.08:25:30.37#ibcon#wrote, iclass 30, count 0 2006.259.08:25:30.37#ibcon#about to read 3, iclass 30, count 0 2006.259.08:25:30.39#ibcon#read 3, iclass 30, count 0 2006.259.08:25:30.39#ibcon#about to read 4, iclass 30, count 0 2006.259.08:25:30.39#ibcon#read 4, iclass 30, count 0 2006.259.08:25:30.39#ibcon#about to read 5, iclass 30, count 0 2006.259.08:25:30.39#ibcon#read 5, iclass 30, count 0 2006.259.08:25:30.39#ibcon#about to read 6, iclass 30, count 0 2006.259.08:25:30.39#ibcon#read 6, iclass 30, count 0 2006.259.08:25:30.39#ibcon#end of sib2, iclass 30, count 0 2006.259.08:25:30.39#ibcon#*mode == 0, iclass 30, count 0 2006.259.08:25:30.39#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.259.08:25:30.39#ibcon#[25=USB\r\n] 2006.259.08:25:30.39#ibcon#*before write, iclass 30, count 0 2006.259.08:25:30.39#ibcon#enter sib2, iclass 30, count 0 2006.259.08:25:30.39#ibcon#flushed, iclass 30, count 0 2006.259.08:25:30.39#ibcon#about to write, iclass 30, count 0 2006.259.08:25:30.39#ibcon#wrote, iclass 30, count 0 2006.259.08:25:30.39#ibcon#about to read 3, iclass 30, count 0 2006.259.08:25:30.42#ibcon#read 3, iclass 30, count 0 2006.259.08:25:30.42#ibcon#about to read 4, iclass 30, count 0 2006.259.08:25:30.42#ibcon#read 4, iclass 30, count 0 2006.259.08:25:30.42#ibcon#about to read 5, iclass 30, count 0 2006.259.08:25:30.42#ibcon#read 5, iclass 30, count 0 2006.259.08:25:30.42#ibcon#about to read 6, iclass 30, count 0 2006.259.08:25:30.42#ibcon#read 6, iclass 30, count 0 2006.259.08:25:30.42#ibcon#end of sib2, iclass 30, count 0 2006.259.08:25:30.42#ibcon#*after write, iclass 30, count 0 2006.259.08:25:30.42#ibcon#*before return 0, iclass 30, count 0 2006.259.08:25:30.42#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.259.08:25:30.42#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.259.08:25:30.42#ibcon#about to clear, iclass 30 cls_cnt 0 2006.259.08:25:30.42#ibcon#cleared, iclass 30 cls_cnt 0 2006.259.08:25:30.42$vc4f8/valo=5,652.99 2006.259.08:25:30.42#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.259.08:25:30.42#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.259.08:25:30.42#ibcon#ireg 17 cls_cnt 0 2006.259.08:25:30.42#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.259.08:25:30.42#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.259.08:25:30.42#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.259.08:25:30.42#ibcon#enter wrdev, iclass 32, count 0 2006.259.08:25:30.42#ibcon#first serial, iclass 32, count 0 2006.259.08:25:30.42#ibcon#enter sib2, iclass 32, count 0 2006.259.08:25:30.42#ibcon#flushed, iclass 32, count 0 2006.259.08:25:30.42#ibcon#about to write, iclass 32, count 0 2006.259.08:25:30.42#ibcon#wrote, iclass 32, count 0 2006.259.08:25:30.42#ibcon#about to read 3, iclass 32, count 0 2006.259.08:25:30.44#ibcon#read 3, iclass 32, count 0 2006.259.08:25:30.44#ibcon#about to read 4, iclass 32, count 0 2006.259.08:25:30.44#ibcon#read 4, iclass 32, count 0 2006.259.08:25:30.44#ibcon#about to read 5, iclass 32, count 0 2006.259.08:25:30.44#ibcon#read 5, iclass 32, count 0 2006.259.08:25:30.44#ibcon#about to read 6, iclass 32, count 0 2006.259.08:25:30.44#ibcon#read 6, iclass 32, count 0 2006.259.08:25:30.44#ibcon#end of sib2, iclass 32, count 0 2006.259.08:25:30.44#ibcon#*mode == 0, iclass 32, count 0 2006.259.08:25:30.44#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.259.08:25:30.44#ibcon#[26=FRQ=05,652.99\r\n] 2006.259.08:25:30.44#ibcon#*before write, iclass 32, count 0 2006.259.08:25:30.44#ibcon#enter sib2, iclass 32, count 0 2006.259.08:25:30.44#ibcon#flushed, iclass 32, count 0 2006.259.08:25:30.44#ibcon#about to write, iclass 32, count 0 2006.259.08:25:30.44#ibcon#wrote, iclass 32, count 0 2006.259.08:25:30.44#ibcon#about to read 3, iclass 32, count 0 2006.259.08:25:30.48#ibcon#read 3, iclass 32, count 0 2006.259.08:25:30.48#ibcon#about to read 4, iclass 32, count 0 2006.259.08:25:30.48#ibcon#read 4, iclass 32, count 0 2006.259.08:25:30.48#ibcon#about to read 5, iclass 32, count 0 2006.259.08:25:30.48#ibcon#read 5, iclass 32, count 0 2006.259.08:25:30.48#ibcon#about to read 6, iclass 32, count 0 2006.259.08:25:30.48#ibcon#read 6, iclass 32, count 0 2006.259.08:25:30.48#ibcon#end of sib2, iclass 32, count 0 2006.259.08:25:30.48#ibcon#*after write, iclass 32, count 0 2006.259.08:25:30.48#ibcon#*before return 0, iclass 32, count 0 2006.259.08:25:30.48#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.259.08:25:30.48#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.259.08:25:30.48#ibcon#about to clear, iclass 32 cls_cnt 0 2006.259.08:25:30.48#ibcon#cleared, iclass 32 cls_cnt 0 2006.259.08:25:30.48$vc4f8/va=5,7 2006.259.08:25:30.48#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.259.08:25:30.48#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.259.08:25:30.48#ibcon#ireg 11 cls_cnt 2 2006.259.08:25:30.48#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.259.08:25:30.54#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.259.08:25:30.54#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.259.08:25:30.54#ibcon#enter wrdev, iclass 34, count 2 2006.259.08:25:30.54#ibcon#first serial, iclass 34, count 2 2006.259.08:25:30.54#ibcon#enter sib2, iclass 34, count 2 2006.259.08:25:30.54#ibcon#flushed, iclass 34, count 2 2006.259.08:25:30.54#ibcon#about to write, iclass 34, count 2 2006.259.08:25:30.54#ibcon#wrote, iclass 34, count 2 2006.259.08:25:30.54#ibcon#about to read 3, iclass 34, count 2 2006.259.08:25:30.56#ibcon#read 3, iclass 34, count 2 2006.259.08:25:30.56#ibcon#about to read 4, iclass 34, count 2 2006.259.08:25:30.56#ibcon#read 4, iclass 34, count 2 2006.259.08:25:30.56#ibcon#about to read 5, iclass 34, count 2 2006.259.08:25:30.56#ibcon#read 5, iclass 34, count 2 2006.259.08:25:30.56#ibcon#about to read 6, iclass 34, count 2 2006.259.08:25:30.56#ibcon#read 6, iclass 34, count 2 2006.259.08:25:30.56#ibcon#end of sib2, iclass 34, count 2 2006.259.08:25:30.56#ibcon#*mode == 0, iclass 34, count 2 2006.259.08:25:30.56#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.259.08:25:30.56#ibcon#[25=AT05-07\r\n] 2006.259.08:25:30.56#ibcon#*before write, iclass 34, count 2 2006.259.08:25:30.56#ibcon#enter sib2, iclass 34, count 2 2006.259.08:25:30.56#ibcon#flushed, iclass 34, count 2 2006.259.08:25:30.56#ibcon#about to write, iclass 34, count 2 2006.259.08:25:30.56#ibcon#wrote, iclass 34, count 2 2006.259.08:25:30.56#ibcon#about to read 3, iclass 34, count 2 2006.259.08:25:30.59#ibcon#read 3, iclass 34, count 2 2006.259.08:25:30.59#ibcon#about to read 4, iclass 34, count 2 2006.259.08:25:30.59#ibcon#read 4, iclass 34, count 2 2006.259.08:25:30.59#ibcon#about to read 5, iclass 34, count 2 2006.259.08:25:30.59#ibcon#read 5, iclass 34, count 2 2006.259.08:25:30.59#ibcon#about to read 6, iclass 34, count 2 2006.259.08:25:30.59#ibcon#read 6, iclass 34, count 2 2006.259.08:25:30.59#ibcon#end of sib2, iclass 34, count 2 2006.259.08:25:30.59#ibcon#*after write, iclass 34, count 2 2006.259.08:25:30.59#ibcon#*before return 0, iclass 34, count 2 2006.259.08:25:30.59#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.259.08:25:30.59#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.259.08:25:30.59#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.259.08:25:30.59#ibcon#ireg 7 cls_cnt 0 2006.259.08:25:30.59#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.259.08:25:30.71#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.259.08:25:30.71#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.259.08:25:30.71#ibcon#enter wrdev, iclass 34, count 0 2006.259.08:25:30.71#ibcon#first serial, iclass 34, count 0 2006.259.08:25:30.71#ibcon#enter sib2, iclass 34, count 0 2006.259.08:25:30.71#ibcon#flushed, iclass 34, count 0 2006.259.08:25:30.71#ibcon#about to write, iclass 34, count 0 2006.259.08:25:30.71#ibcon#wrote, iclass 34, count 0 2006.259.08:25:30.71#ibcon#about to read 3, iclass 34, count 0 2006.259.08:25:30.73#ibcon#read 3, iclass 34, count 0 2006.259.08:25:30.73#ibcon#about to read 4, iclass 34, count 0 2006.259.08:25:30.73#ibcon#read 4, iclass 34, count 0 2006.259.08:25:30.73#ibcon#about to read 5, iclass 34, count 0 2006.259.08:25:30.73#ibcon#read 5, iclass 34, count 0 2006.259.08:25:30.73#ibcon#about to read 6, iclass 34, count 0 2006.259.08:25:30.73#ibcon#read 6, iclass 34, count 0 2006.259.08:25:30.73#ibcon#end of sib2, iclass 34, count 0 2006.259.08:25:30.73#ibcon#*mode == 0, iclass 34, count 0 2006.259.08:25:30.73#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.259.08:25:30.73#ibcon#[25=USB\r\n] 2006.259.08:25:30.73#ibcon#*before write, iclass 34, count 0 2006.259.08:25:30.73#ibcon#enter sib2, iclass 34, count 0 2006.259.08:25:30.73#ibcon#flushed, iclass 34, count 0 2006.259.08:25:30.73#ibcon#about to write, iclass 34, count 0 2006.259.08:25:30.73#ibcon#wrote, iclass 34, count 0 2006.259.08:25:30.73#ibcon#about to read 3, iclass 34, count 0 2006.259.08:25:30.76#ibcon#read 3, iclass 34, count 0 2006.259.08:25:30.76#ibcon#about to read 4, iclass 34, count 0 2006.259.08:25:30.76#ibcon#read 4, iclass 34, count 0 2006.259.08:25:30.76#ibcon#about to read 5, iclass 34, count 0 2006.259.08:25:30.76#ibcon#read 5, iclass 34, count 0 2006.259.08:25:30.76#ibcon#about to read 6, iclass 34, count 0 2006.259.08:25:30.76#ibcon#read 6, iclass 34, count 0 2006.259.08:25:30.76#ibcon#end of sib2, iclass 34, count 0 2006.259.08:25:30.76#ibcon#*after write, iclass 34, count 0 2006.259.08:25:30.76#ibcon#*before return 0, iclass 34, count 0 2006.259.08:25:30.76#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.259.08:25:30.76#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.259.08:25:30.76#ibcon#about to clear, iclass 34 cls_cnt 0 2006.259.08:25:30.76#ibcon#cleared, iclass 34 cls_cnt 0 2006.259.08:25:30.76$vc4f8/valo=6,772.99 2006.259.08:25:30.76#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.259.08:25:30.76#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.259.08:25:30.76#ibcon#ireg 17 cls_cnt 0 2006.259.08:25:30.76#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.259.08:25:30.76#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.259.08:25:30.76#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.259.08:25:30.76#ibcon#enter wrdev, iclass 36, count 0 2006.259.08:25:30.76#ibcon#first serial, iclass 36, count 0 2006.259.08:25:30.76#ibcon#enter sib2, iclass 36, count 0 2006.259.08:25:30.76#ibcon#flushed, iclass 36, count 0 2006.259.08:25:30.76#ibcon#about to write, iclass 36, count 0 2006.259.08:25:30.76#ibcon#wrote, iclass 36, count 0 2006.259.08:25:30.76#ibcon#about to read 3, iclass 36, count 0 2006.259.08:25:30.78#ibcon#read 3, iclass 36, count 0 2006.259.08:25:30.78#ibcon#about to read 4, iclass 36, count 0 2006.259.08:25:30.78#ibcon#read 4, iclass 36, count 0 2006.259.08:25:30.78#ibcon#about to read 5, iclass 36, count 0 2006.259.08:25:30.78#ibcon#read 5, iclass 36, count 0 2006.259.08:25:30.78#ibcon#about to read 6, iclass 36, count 0 2006.259.08:25:30.78#ibcon#read 6, iclass 36, count 0 2006.259.08:25:30.78#ibcon#end of sib2, iclass 36, count 0 2006.259.08:25:30.78#ibcon#*mode == 0, iclass 36, count 0 2006.259.08:25:30.78#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.259.08:25:30.78#ibcon#[26=FRQ=06,772.99\r\n] 2006.259.08:25:30.78#ibcon#*before write, iclass 36, count 0 2006.259.08:25:30.78#ibcon#enter sib2, iclass 36, count 0 2006.259.08:25:30.78#ibcon#flushed, iclass 36, count 0 2006.259.08:25:30.78#ibcon#about to write, iclass 36, count 0 2006.259.08:25:30.78#ibcon#wrote, iclass 36, count 0 2006.259.08:25:30.78#ibcon#about to read 3, iclass 36, count 0 2006.259.08:25:30.82#ibcon#read 3, iclass 36, count 0 2006.259.08:25:30.82#ibcon#about to read 4, iclass 36, count 0 2006.259.08:25:30.82#ibcon#read 4, iclass 36, count 0 2006.259.08:25:30.82#ibcon#about to read 5, iclass 36, count 0 2006.259.08:25:30.82#ibcon#read 5, iclass 36, count 0 2006.259.08:25:30.82#ibcon#about to read 6, iclass 36, count 0 2006.259.08:25:30.82#ibcon#read 6, iclass 36, count 0 2006.259.08:25:30.82#ibcon#end of sib2, iclass 36, count 0 2006.259.08:25:30.82#ibcon#*after write, iclass 36, count 0 2006.259.08:25:30.82#ibcon#*before return 0, iclass 36, count 0 2006.259.08:25:30.82#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.259.08:25:30.82#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.259.08:25:30.82#ibcon#about to clear, iclass 36 cls_cnt 0 2006.259.08:25:30.82#ibcon#cleared, iclass 36 cls_cnt 0 2006.259.08:25:30.82$vc4f8/va=6,6 2006.259.08:25:30.82#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.259.08:25:30.82#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.259.08:25:30.82#ibcon#ireg 11 cls_cnt 2 2006.259.08:25:30.82#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.259.08:25:30.88#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.259.08:25:30.88#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.259.08:25:30.88#ibcon#enter wrdev, iclass 38, count 2 2006.259.08:25:30.88#ibcon#first serial, iclass 38, count 2 2006.259.08:25:30.88#ibcon#enter sib2, iclass 38, count 2 2006.259.08:25:30.88#ibcon#flushed, iclass 38, count 2 2006.259.08:25:30.88#ibcon#about to write, iclass 38, count 2 2006.259.08:25:30.88#ibcon#wrote, iclass 38, count 2 2006.259.08:25:30.88#ibcon#about to read 3, iclass 38, count 2 2006.259.08:25:30.90#ibcon#read 3, iclass 38, count 2 2006.259.08:25:30.90#ibcon#about to read 4, iclass 38, count 2 2006.259.08:25:30.90#ibcon#read 4, iclass 38, count 2 2006.259.08:25:30.90#ibcon#about to read 5, iclass 38, count 2 2006.259.08:25:30.90#ibcon#read 5, iclass 38, count 2 2006.259.08:25:30.90#ibcon#about to read 6, iclass 38, count 2 2006.259.08:25:30.90#ibcon#read 6, iclass 38, count 2 2006.259.08:25:30.90#ibcon#end of sib2, iclass 38, count 2 2006.259.08:25:30.90#ibcon#*mode == 0, iclass 38, count 2 2006.259.08:25:30.90#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.259.08:25:30.90#ibcon#[25=AT06-06\r\n] 2006.259.08:25:30.90#ibcon#*before write, iclass 38, count 2 2006.259.08:25:30.90#ibcon#enter sib2, iclass 38, count 2 2006.259.08:25:30.90#ibcon#flushed, iclass 38, count 2 2006.259.08:25:30.90#ibcon#about to write, iclass 38, count 2 2006.259.08:25:30.90#ibcon#wrote, iclass 38, count 2 2006.259.08:25:30.90#ibcon#about to read 3, iclass 38, count 2 2006.259.08:25:30.93#ibcon#read 3, iclass 38, count 2 2006.259.08:25:30.93#ibcon#about to read 4, iclass 38, count 2 2006.259.08:25:30.93#ibcon#read 4, iclass 38, count 2 2006.259.08:25:30.93#ibcon#about to read 5, iclass 38, count 2 2006.259.08:25:30.93#ibcon#read 5, iclass 38, count 2 2006.259.08:25:30.93#ibcon#about to read 6, iclass 38, count 2 2006.259.08:25:30.93#ibcon#read 6, iclass 38, count 2 2006.259.08:25:30.93#ibcon#end of sib2, iclass 38, count 2 2006.259.08:25:30.93#ibcon#*after write, iclass 38, count 2 2006.259.08:25:30.93#ibcon#*before return 0, iclass 38, count 2 2006.259.08:25:30.93#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.259.08:25:30.93#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.259.08:25:30.93#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.259.08:25:30.93#ibcon#ireg 7 cls_cnt 0 2006.259.08:25:30.93#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.259.08:25:31.05#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.259.08:25:31.05#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.259.08:25:31.05#ibcon#enter wrdev, iclass 38, count 0 2006.259.08:25:31.05#ibcon#first serial, iclass 38, count 0 2006.259.08:25:31.05#ibcon#enter sib2, iclass 38, count 0 2006.259.08:25:31.05#ibcon#flushed, iclass 38, count 0 2006.259.08:25:31.05#ibcon#about to write, iclass 38, count 0 2006.259.08:25:31.05#ibcon#wrote, iclass 38, count 0 2006.259.08:25:31.05#ibcon#about to read 3, iclass 38, count 0 2006.259.08:25:31.07#ibcon#read 3, iclass 38, count 0 2006.259.08:25:31.07#ibcon#about to read 4, iclass 38, count 0 2006.259.08:25:31.07#ibcon#read 4, iclass 38, count 0 2006.259.08:25:31.07#ibcon#about to read 5, iclass 38, count 0 2006.259.08:25:31.07#ibcon#read 5, iclass 38, count 0 2006.259.08:25:31.07#ibcon#about to read 6, iclass 38, count 0 2006.259.08:25:31.07#ibcon#read 6, iclass 38, count 0 2006.259.08:25:31.07#ibcon#end of sib2, iclass 38, count 0 2006.259.08:25:31.07#ibcon#*mode == 0, iclass 38, count 0 2006.259.08:25:31.07#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.259.08:25:31.07#ibcon#[25=USB\r\n] 2006.259.08:25:31.07#ibcon#*before write, iclass 38, count 0 2006.259.08:25:31.07#ibcon#enter sib2, iclass 38, count 0 2006.259.08:25:31.07#ibcon#flushed, iclass 38, count 0 2006.259.08:25:31.07#ibcon#about to write, iclass 38, count 0 2006.259.08:25:31.07#ibcon#wrote, iclass 38, count 0 2006.259.08:25:31.07#ibcon#about to read 3, iclass 38, count 0 2006.259.08:25:31.10#ibcon#read 3, iclass 38, count 0 2006.259.08:25:31.10#ibcon#about to read 4, iclass 38, count 0 2006.259.08:25:31.10#ibcon#read 4, iclass 38, count 0 2006.259.08:25:31.10#ibcon#about to read 5, iclass 38, count 0 2006.259.08:25:31.10#ibcon#read 5, iclass 38, count 0 2006.259.08:25:31.10#ibcon#about to read 6, iclass 38, count 0 2006.259.08:25:31.10#ibcon#read 6, iclass 38, count 0 2006.259.08:25:31.10#ibcon#end of sib2, iclass 38, count 0 2006.259.08:25:31.10#ibcon#*after write, iclass 38, count 0 2006.259.08:25:31.10#ibcon#*before return 0, iclass 38, count 0 2006.259.08:25:31.10#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.259.08:25:31.10#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.259.08:25:31.10#ibcon#about to clear, iclass 38 cls_cnt 0 2006.259.08:25:31.10#ibcon#cleared, iclass 38 cls_cnt 0 2006.259.08:25:31.10$vc4f8/valo=7,832.99 2006.259.08:25:31.10#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.259.08:25:31.10#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.259.08:25:31.10#ibcon#ireg 17 cls_cnt 0 2006.259.08:25:31.10#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.259.08:25:31.10#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.259.08:25:31.10#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.259.08:25:31.10#ibcon#enter wrdev, iclass 40, count 0 2006.259.08:25:31.10#ibcon#first serial, iclass 40, count 0 2006.259.08:25:31.10#ibcon#enter sib2, iclass 40, count 0 2006.259.08:25:31.10#ibcon#flushed, iclass 40, count 0 2006.259.08:25:31.10#ibcon#about to write, iclass 40, count 0 2006.259.08:25:31.10#ibcon#wrote, iclass 40, count 0 2006.259.08:25:31.10#ibcon#about to read 3, iclass 40, count 0 2006.259.08:25:31.12#ibcon#read 3, iclass 40, count 0 2006.259.08:25:31.12#ibcon#about to read 4, iclass 40, count 0 2006.259.08:25:31.12#ibcon#read 4, iclass 40, count 0 2006.259.08:25:31.12#ibcon#about to read 5, iclass 40, count 0 2006.259.08:25:31.12#ibcon#read 5, iclass 40, count 0 2006.259.08:25:31.12#ibcon#about to read 6, iclass 40, count 0 2006.259.08:25:31.12#ibcon#read 6, iclass 40, count 0 2006.259.08:25:31.12#ibcon#end of sib2, iclass 40, count 0 2006.259.08:25:31.12#ibcon#*mode == 0, iclass 40, count 0 2006.259.08:25:31.12#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.259.08:25:31.12#ibcon#[26=FRQ=07,832.99\r\n] 2006.259.08:25:31.12#ibcon#*before write, iclass 40, count 0 2006.259.08:25:31.12#ibcon#enter sib2, iclass 40, count 0 2006.259.08:25:31.12#ibcon#flushed, iclass 40, count 0 2006.259.08:25:31.12#ibcon#about to write, iclass 40, count 0 2006.259.08:25:31.12#ibcon#wrote, iclass 40, count 0 2006.259.08:25:31.12#ibcon#about to read 3, iclass 40, count 0 2006.259.08:25:31.16#ibcon#read 3, iclass 40, count 0 2006.259.08:25:31.16#ibcon#about to read 4, iclass 40, count 0 2006.259.08:25:31.16#ibcon#read 4, iclass 40, count 0 2006.259.08:25:31.16#ibcon#about to read 5, iclass 40, count 0 2006.259.08:25:31.16#ibcon#read 5, iclass 40, count 0 2006.259.08:25:31.16#ibcon#about to read 6, iclass 40, count 0 2006.259.08:25:31.16#ibcon#read 6, iclass 40, count 0 2006.259.08:25:31.16#ibcon#end of sib2, iclass 40, count 0 2006.259.08:25:31.16#ibcon#*after write, iclass 40, count 0 2006.259.08:25:31.16#ibcon#*before return 0, iclass 40, count 0 2006.259.08:25:31.16#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.259.08:25:31.16#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.259.08:25:31.16#ibcon#about to clear, iclass 40 cls_cnt 0 2006.259.08:25:31.16#ibcon#cleared, iclass 40 cls_cnt 0 2006.259.08:25:31.16$vc4f8/va=7,6 2006.259.08:25:31.16#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.259.08:25:31.16#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.259.08:25:31.16#ibcon#ireg 11 cls_cnt 2 2006.259.08:25:31.16#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.259.08:25:31.22#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.259.08:25:31.22#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.259.08:25:31.22#ibcon#enter wrdev, iclass 4, count 2 2006.259.08:25:31.22#ibcon#first serial, iclass 4, count 2 2006.259.08:25:31.22#ibcon#enter sib2, iclass 4, count 2 2006.259.08:25:31.22#ibcon#flushed, iclass 4, count 2 2006.259.08:25:31.22#ibcon#about to write, iclass 4, count 2 2006.259.08:25:31.22#ibcon#wrote, iclass 4, count 2 2006.259.08:25:31.22#ibcon#about to read 3, iclass 4, count 2 2006.259.08:25:31.24#ibcon#read 3, iclass 4, count 2 2006.259.08:25:31.24#ibcon#about to read 4, iclass 4, count 2 2006.259.08:25:31.24#ibcon#read 4, iclass 4, count 2 2006.259.08:25:31.24#ibcon#about to read 5, iclass 4, count 2 2006.259.08:25:31.24#ibcon#read 5, iclass 4, count 2 2006.259.08:25:31.24#ibcon#about to read 6, iclass 4, count 2 2006.259.08:25:31.24#ibcon#read 6, iclass 4, count 2 2006.259.08:25:31.24#ibcon#end of sib2, iclass 4, count 2 2006.259.08:25:31.24#ibcon#*mode == 0, iclass 4, count 2 2006.259.08:25:31.24#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.259.08:25:31.24#ibcon#[25=AT07-06\r\n] 2006.259.08:25:31.24#ibcon#*before write, iclass 4, count 2 2006.259.08:25:31.24#ibcon#enter sib2, iclass 4, count 2 2006.259.08:25:31.24#ibcon#flushed, iclass 4, count 2 2006.259.08:25:31.24#ibcon#about to write, iclass 4, count 2 2006.259.08:25:31.24#ibcon#wrote, iclass 4, count 2 2006.259.08:25:31.24#ibcon#about to read 3, iclass 4, count 2 2006.259.08:25:31.27#ibcon#read 3, iclass 4, count 2 2006.259.08:25:31.27#ibcon#about to read 4, iclass 4, count 2 2006.259.08:25:31.27#ibcon#read 4, iclass 4, count 2 2006.259.08:25:31.27#ibcon#about to read 5, iclass 4, count 2 2006.259.08:25:31.27#ibcon#read 5, iclass 4, count 2 2006.259.08:25:31.27#ibcon#about to read 6, iclass 4, count 2 2006.259.08:25:31.27#ibcon#read 6, iclass 4, count 2 2006.259.08:25:31.27#ibcon#end of sib2, iclass 4, count 2 2006.259.08:25:31.27#ibcon#*after write, iclass 4, count 2 2006.259.08:25:31.27#ibcon#*before return 0, iclass 4, count 2 2006.259.08:25:31.27#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.259.08:25:31.27#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.259.08:25:31.27#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.259.08:25:31.27#ibcon#ireg 7 cls_cnt 0 2006.259.08:25:31.27#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.259.08:25:31.39#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.259.08:25:31.39#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.259.08:25:31.39#ibcon#enter wrdev, iclass 4, count 0 2006.259.08:25:31.39#ibcon#first serial, iclass 4, count 0 2006.259.08:25:31.39#ibcon#enter sib2, iclass 4, count 0 2006.259.08:25:31.39#ibcon#flushed, iclass 4, count 0 2006.259.08:25:31.39#ibcon#about to write, iclass 4, count 0 2006.259.08:25:31.39#ibcon#wrote, iclass 4, count 0 2006.259.08:25:31.39#ibcon#about to read 3, iclass 4, count 0 2006.259.08:25:31.41#ibcon#read 3, iclass 4, count 0 2006.259.08:25:31.41#ibcon#about to read 4, iclass 4, count 0 2006.259.08:25:31.41#ibcon#read 4, iclass 4, count 0 2006.259.08:25:31.41#ibcon#about to read 5, iclass 4, count 0 2006.259.08:25:31.41#ibcon#read 5, iclass 4, count 0 2006.259.08:25:31.41#ibcon#about to read 6, iclass 4, count 0 2006.259.08:25:31.41#ibcon#read 6, iclass 4, count 0 2006.259.08:25:31.41#ibcon#end of sib2, iclass 4, count 0 2006.259.08:25:31.41#ibcon#*mode == 0, iclass 4, count 0 2006.259.08:25:31.41#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.259.08:25:31.41#ibcon#[25=USB\r\n] 2006.259.08:25:31.41#ibcon#*before write, iclass 4, count 0 2006.259.08:25:31.41#ibcon#enter sib2, iclass 4, count 0 2006.259.08:25:31.41#ibcon#flushed, iclass 4, count 0 2006.259.08:25:31.41#ibcon#about to write, iclass 4, count 0 2006.259.08:25:31.41#ibcon#wrote, iclass 4, count 0 2006.259.08:25:31.41#ibcon#about to read 3, iclass 4, count 0 2006.259.08:25:31.44#ibcon#read 3, iclass 4, count 0 2006.259.08:25:31.44#ibcon#about to read 4, iclass 4, count 0 2006.259.08:25:31.44#ibcon#read 4, iclass 4, count 0 2006.259.08:25:31.44#ibcon#about to read 5, iclass 4, count 0 2006.259.08:25:31.44#ibcon#read 5, iclass 4, count 0 2006.259.08:25:31.44#ibcon#about to read 6, iclass 4, count 0 2006.259.08:25:31.44#ibcon#read 6, iclass 4, count 0 2006.259.08:25:31.44#ibcon#end of sib2, iclass 4, count 0 2006.259.08:25:31.44#ibcon#*after write, iclass 4, count 0 2006.259.08:25:31.44#ibcon#*before return 0, iclass 4, count 0 2006.259.08:25:31.44#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.259.08:25:31.44#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.259.08:25:31.44#ibcon#about to clear, iclass 4 cls_cnt 0 2006.259.08:25:31.44#ibcon#cleared, iclass 4 cls_cnt 0 2006.259.08:25:31.44$vc4f8/valo=8,852.99 2006.259.08:25:31.44#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.259.08:25:31.44#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.259.08:25:31.44#ibcon#ireg 17 cls_cnt 0 2006.259.08:25:31.44#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.259.08:25:31.44#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.259.08:25:31.44#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.259.08:25:31.44#ibcon#enter wrdev, iclass 6, count 0 2006.259.08:25:31.44#ibcon#first serial, iclass 6, count 0 2006.259.08:25:31.44#ibcon#enter sib2, iclass 6, count 0 2006.259.08:25:31.44#ibcon#flushed, iclass 6, count 0 2006.259.08:25:31.44#ibcon#about to write, iclass 6, count 0 2006.259.08:25:31.44#ibcon#wrote, iclass 6, count 0 2006.259.08:25:31.44#ibcon#about to read 3, iclass 6, count 0 2006.259.08:25:31.46#ibcon#read 3, iclass 6, count 0 2006.259.08:25:31.46#ibcon#about to read 4, iclass 6, count 0 2006.259.08:25:31.46#ibcon#read 4, iclass 6, count 0 2006.259.08:25:31.46#ibcon#about to read 5, iclass 6, count 0 2006.259.08:25:31.46#ibcon#read 5, iclass 6, count 0 2006.259.08:25:31.46#ibcon#about to read 6, iclass 6, count 0 2006.259.08:25:31.46#ibcon#read 6, iclass 6, count 0 2006.259.08:25:31.46#ibcon#end of sib2, iclass 6, count 0 2006.259.08:25:31.46#ibcon#*mode == 0, iclass 6, count 0 2006.259.08:25:31.46#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.259.08:25:31.46#ibcon#[26=FRQ=08,852.99\r\n] 2006.259.08:25:31.46#ibcon#*before write, iclass 6, count 0 2006.259.08:25:31.46#ibcon#enter sib2, iclass 6, count 0 2006.259.08:25:31.46#ibcon#flushed, iclass 6, count 0 2006.259.08:25:31.46#ibcon#about to write, iclass 6, count 0 2006.259.08:25:31.46#ibcon#wrote, iclass 6, count 0 2006.259.08:25:31.46#ibcon#about to read 3, iclass 6, count 0 2006.259.08:25:31.50#ibcon#read 3, iclass 6, count 0 2006.259.08:25:31.50#ibcon#about to read 4, iclass 6, count 0 2006.259.08:25:31.50#ibcon#read 4, iclass 6, count 0 2006.259.08:25:31.50#ibcon#about to read 5, iclass 6, count 0 2006.259.08:25:31.50#ibcon#read 5, iclass 6, count 0 2006.259.08:25:31.50#ibcon#about to read 6, iclass 6, count 0 2006.259.08:25:31.50#ibcon#read 6, iclass 6, count 0 2006.259.08:25:31.50#ibcon#end of sib2, iclass 6, count 0 2006.259.08:25:31.50#ibcon#*after write, iclass 6, count 0 2006.259.08:25:31.50#ibcon#*before return 0, iclass 6, count 0 2006.259.08:25:31.50#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.259.08:25:31.50#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.259.08:25:31.50#ibcon#about to clear, iclass 6 cls_cnt 0 2006.259.08:25:31.50#ibcon#cleared, iclass 6 cls_cnt 0 2006.259.08:25:31.50$vc4f8/va=8,6 2006.259.08:25:31.50#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.259.08:25:31.50#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.259.08:25:31.50#ibcon#ireg 11 cls_cnt 2 2006.259.08:25:31.50#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.259.08:25:31.56#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.259.08:25:31.56#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.259.08:25:31.56#ibcon#enter wrdev, iclass 10, count 2 2006.259.08:25:31.56#ibcon#first serial, iclass 10, count 2 2006.259.08:25:31.56#ibcon#enter sib2, iclass 10, count 2 2006.259.08:25:31.56#ibcon#flushed, iclass 10, count 2 2006.259.08:25:31.56#ibcon#about to write, iclass 10, count 2 2006.259.08:25:31.56#ibcon#wrote, iclass 10, count 2 2006.259.08:25:31.56#ibcon#about to read 3, iclass 10, count 2 2006.259.08:25:31.58#ibcon#read 3, iclass 10, count 2 2006.259.08:25:31.58#ibcon#about to read 4, iclass 10, count 2 2006.259.08:25:31.58#ibcon#read 4, iclass 10, count 2 2006.259.08:25:31.58#ibcon#about to read 5, iclass 10, count 2 2006.259.08:25:31.58#ibcon#read 5, iclass 10, count 2 2006.259.08:25:31.58#ibcon#about to read 6, iclass 10, count 2 2006.259.08:25:31.58#ibcon#read 6, iclass 10, count 2 2006.259.08:25:31.58#ibcon#end of sib2, iclass 10, count 2 2006.259.08:25:31.58#ibcon#*mode == 0, iclass 10, count 2 2006.259.08:25:31.58#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.259.08:25:31.58#ibcon#[25=AT08-06\r\n] 2006.259.08:25:31.58#ibcon#*before write, iclass 10, count 2 2006.259.08:25:31.58#ibcon#enter sib2, iclass 10, count 2 2006.259.08:25:31.58#ibcon#flushed, iclass 10, count 2 2006.259.08:25:31.58#ibcon#about to write, iclass 10, count 2 2006.259.08:25:31.58#ibcon#wrote, iclass 10, count 2 2006.259.08:25:31.58#ibcon#about to read 3, iclass 10, count 2 2006.259.08:25:31.61#ibcon#read 3, iclass 10, count 2 2006.259.08:25:31.61#ibcon#about to read 4, iclass 10, count 2 2006.259.08:25:31.61#ibcon#read 4, iclass 10, count 2 2006.259.08:25:31.61#ibcon#about to read 5, iclass 10, count 2 2006.259.08:25:31.61#ibcon#read 5, iclass 10, count 2 2006.259.08:25:31.61#ibcon#about to read 6, iclass 10, count 2 2006.259.08:25:31.61#ibcon#read 6, iclass 10, count 2 2006.259.08:25:31.61#ibcon#end of sib2, iclass 10, count 2 2006.259.08:25:31.61#ibcon#*after write, iclass 10, count 2 2006.259.08:25:31.61#ibcon#*before return 0, iclass 10, count 2 2006.259.08:25:31.61#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.259.08:25:31.61#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.259.08:25:31.61#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.259.08:25:31.61#ibcon#ireg 7 cls_cnt 0 2006.259.08:25:31.61#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.259.08:25:31.73#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.259.08:25:31.73#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.259.08:25:31.73#ibcon#enter wrdev, iclass 10, count 0 2006.259.08:25:31.73#ibcon#first serial, iclass 10, count 0 2006.259.08:25:31.73#ibcon#enter sib2, iclass 10, count 0 2006.259.08:25:31.73#ibcon#flushed, iclass 10, count 0 2006.259.08:25:31.73#ibcon#about to write, iclass 10, count 0 2006.259.08:25:31.73#ibcon#wrote, iclass 10, count 0 2006.259.08:25:31.73#ibcon#about to read 3, iclass 10, count 0 2006.259.08:25:31.75#ibcon#read 3, iclass 10, count 0 2006.259.08:25:31.75#ibcon#about to read 4, iclass 10, count 0 2006.259.08:25:31.75#ibcon#read 4, iclass 10, count 0 2006.259.08:25:31.75#ibcon#about to read 5, iclass 10, count 0 2006.259.08:25:31.75#ibcon#read 5, iclass 10, count 0 2006.259.08:25:31.75#ibcon#about to read 6, iclass 10, count 0 2006.259.08:25:31.75#ibcon#read 6, iclass 10, count 0 2006.259.08:25:31.75#ibcon#end of sib2, iclass 10, count 0 2006.259.08:25:31.75#ibcon#*mode == 0, iclass 10, count 0 2006.259.08:25:31.75#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.259.08:25:31.75#ibcon#[25=USB\r\n] 2006.259.08:25:31.75#ibcon#*before write, iclass 10, count 0 2006.259.08:25:31.75#ibcon#enter sib2, iclass 10, count 0 2006.259.08:25:31.75#ibcon#flushed, iclass 10, count 0 2006.259.08:25:31.75#ibcon#about to write, iclass 10, count 0 2006.259.08:25:31.75#ibcon#wrote, iclass 10, count 0 2006.259.08:25:31.75#ibcon#about to read 3, iclass 10, count 0 2006.259.08:25:31.78#ibcon#read 3, iclass 10, count 0 2006.259.08:25:31.78#ibcon#about to read 4, iclass 10, count 0 2006.259.08:25:31.78#ibcon#read 4, iclass 10, count 0 2006.259.08:25:31.78#ibcon#about to read 5, iclass 10, count 0 2006.259.08:25:31.78#ibcon#read 5, iclass 10, count 0 2006.259.08:25:31.78#ibcon#about to read 6, iclass 10, count 0 2006.259.08:25:31.78#ibcon#read 6, iclass 10, count 0 2006.259.08:25:31.78#ibcon#end of sib2, iclass 10, count 0 2006.259.08:25:31.78#ibcon#*after write, iclass 10, count 0 2006.259.08:25:31.78#ibcon#*before return 0, iclass 10, count 0 2006.259.08:25:31.78#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.259.08:25:31.78#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.259.08:25:31.78#ibcon#about to clear, iclass 10 cls_cnt 0 2006.259.08:25:31.78#ibcon#cleared, iclass 10 cls_cnt 0 2006.259.08:25:31.78$vc4f8/vblo=1,632.99 2006.259.08:25:31.78#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.259.08:25:31.78#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.259.08:25:31.78#ibcon#ireg 17 cls_cnt 0 2006.259.08:25:31.78#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.259.08:25:31.78#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.259.08:25:31.78#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.259.08:25:31.78#ibcon#enter wrdev, iclass 12, count 0 2006.259.08:25:31.78#ibcon#first serial, iclass 12, count 0 2006.259.08:25:31.78#ibcon#enter sib2, iclass 12, count 0 2006.259.08:25:31.78#ibcon#flushed, iclass 12, count 0 2006.259.08:25:31.78#ibcon#about to write, iclass 12, count 0 2006.259.08:25:31.78#ibcon#wrote, iclass 12, count 0 2006.259.08:25:31.78#ibcon#about to read 3, iclass 12, count 0 2006.259.08:25:31.80#ibcon#read 3, iclass 12, count 0 2006.259.08:25:31.80#ibcon#about to read 4, iclass 12, count 0 2006.259.08:25:31.80#ibcon#read 4, iclass 12, count 0 2006.259.08:25:31.80#ibcon#about to read 5, iclass 12, count 0 2006.259.08:25:31.80#ibcon#read 5, iclass 12, count 0 2006.259.08:25:31.80#ibcon#about to read 6, iclass 12, count 0 2006.259.08:25:31.80#ibcon#read 6, iclass 12, count 0 2006.259.08:25:31.80#ibcon#end of sib2, iclass 12, count 0 2006.259.08:25:31.80#ibcon#*mode == 0, iclass 12, count 0 2006.259.08:25:31.80#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.259.08:25:31.80#ibcon#[28=FRQ=01,632.99\r\n] 2006.259.08:25:31.80#ibcon#*before write, iclass 12, count 0 2006.259.08:25:31.80#ibcon#enter sib2, iclass 12, count 0 2006.259.08:25:31.80#ibcon#flushed, iclass 12, count 0 2006.259.08:25:31.80#ibcon#about to write, iclass 12, count 0 2006.259.08:25:31.80#ibcon#wrote, iclass 12, count 0 2006.259.08:25:31.80#ibcon#about to read 3, iclass 12, count 0 2006.259.08:25:31.84#ibcon#read 3, iclass 12, count 0 2006.259.08:25:31.84#ibcon#about to read 4, iclass 12, count 0 2006.259.08:25:31.84#ibcon#read 4, iclass 12, count 0 2006.259.08:25:31.84#ibcon#about to read 5, iclass 12, count 0 2006.259.08:25:31.84#ibcon#read 5, iclass 12, count 0 2006.259.08:25:31.84#ibcon#about to read 6, iclass 12, count 0 2006.259.08:25:31.84#ibcon#read 6, iclass 12, count 0 2006.259.08:25:31.84#ibcon#end of sib2, iclass 12, count 0 2006.259.08:25:31.84#ibcon#*after write, iclass 12, count 0 2006.259.08:25:31.84#ibcon#*before return 0, iclass 12, count 0 2006.259.08:25:31.84#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.259.08:25:31.84#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.259.08:25:31.84#ibcon#about to clear, iclass 12 cls_cnt 0 2006.259.08:25:31.84#ibcon#cleared, iclass 12 cls_cnt 0 2006.259.08:25:31.84$vc4f8/vb=1,4 2006.259.08:25:31.84#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.259.08:25:31.84#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.259.08:25:31.84#ibcon#ireg 11 cls_cnt 2 2006.259.08:25:31.84#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.259.08:25:31.84#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.259.08:25:31.84#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.259.08:25:31.84#ibcon#enter wrdev, iclass 14, count 2 2006.259.08:25:31.84#ibcon#first serial, iclass 14, count 2 2006.259.08:25:31.84#ibcon#enter sib2, iclass 14, count 2 2006.259.08:25:31.84#ibcon#flushed, iclass 14, count 2 2006.259.08:25:31.84#ibcon#about to write, iclass 14, count 2 2006.259.08:25:31.84#ibcon#wrote, iclass 14, count 2 2006.259.08:25:31.84#ibcon#about to read 3, iclass 14, count 2 2006.259.08:25:31.86#ibcon#read 3, iclass 14, count 2 2006.259.08:25:31.86#ibcon#about to read 4, iclass 14, count 2 2006.259.08:25:31.86#ibcon#read 4, iclass 14, count 2 2006.259.08:25:31.86#ibcon#about to read 5, iclass 14, count 2 2006.259.08:25:31.86#ibcon#read 5, iclass 14, count 2 2006.259.08:25:31.86#ibcon#about to read 6, iclass 14, count 2 2006.259.08:25:31.86#ibcon#read 6, iclass 14, count 2 2006.259.08:25:31.86#ibcon#end of sib2, iclass 14, count 2 2006.259.08:25:31.86#ibcon#*mode == 0, iclass 14, count 2 2006.259.08:25:31.86#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.259.08:25:31.86#ibcon#[27=AT01-04\r\n] 2006.259.08:25:31.86#ibcon#*before write, iclass 14, count 2 2006.259.08:25:31.86#ibcon#enter sib2, iclass 14, count 2 2006.259.08:25:31.86#ibcon#flushed, iclass 14, count 2 2006.259.08:25:31.86#ibcon#about to write, iclass 14, count 2 2006.259.08:25:31.86#ibcon#wrote, iclass 14, count 2 2006.259.08:25:31.86#ibcon#about to read 3, iclass 14, count 2 2006.259.08:25:31.89#ibcon#read 3, iclass 14, count 2 2006.259.08:25:31.89#ibcon#about to read 4, iclass 14, count 2 2006.259.08:25:31.89#ibcon#read 4, iclass 14, count 2 2006.259.08:25:31.89#ibcon#about to read 5, iclass 14, count 2 2006.259.08:25:31.89#ibcon#read 5, iclass 14, count 2 2006.259.08:25:31.89#ibcon#about to read 6, iclass 14, count 2 2006.259.08:25:31.89#ibcon#read 6, iclass 14, count 2 2006.259.08:25:31.89#ibcon#end of sib2, iclass 14, count 2 2006.259.08:25:31.89#ibcon#*after write, iclass 14, count 2 2006.259.08:25:31.89#ibcon#*before return 0, iclass 14, count 2 2006.259.08:25:31.89#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.259.08:25:31.89#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.259.08:25:31.89#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.259.08:25:31.89#ibcon#ireg 7 cls_cnt 0 2006.259.08:25:31.89#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.259.08:25:32.01#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.259.08:25:32.01#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.259.08:25:32.01#ibcon#enter wrdev, iclass 14, count 0 2006.259.08:25:32.01#ibcon#first serial, iclass 14, count 0 2006.259.08:25:32.01#ibcon#enter sib2, iclass 14, count 0 2006.259.08:25:32.01#ibcon#flushed, iclass 14, count 0 2006.259.08:25:32.01#ibcon#about to write, iclass 14, count 0 2006.259.08:25:32.01#ibcon#wrote, iclass 14, count 0 2006.259.08:25:32.01#ibcon#about to read 3, iclass 14, count 0 2006.259.08:25:32.03#ibcon#read 3, iclass 14, count 0 2006.259.08:25:32.03#ibcon#about to read 4, iclass 14, count 0 2006.259.08:25:32.03#ibcon#read 4, iclass 14, count 0 2006.259.08:25:32.03#ibcon#about to read 5, iclass 14, count 0 2006.259.08:25:32.03#ibcon#read 5, iclass 14, count 0 2006.259.08:25:32.03#ibcon#about to read 6, iclass 14, count 0 2006.259.08:25:32.03#ibcon#read 6, iclass 14, count 0 2006.259.08:25:32.03#ibcon#end of sib2, iclass 14, count 0 2006.259.08:25:32.03#ibcon#*mode == 0, iclass 14, count 0 2006.259.08:25:32.03#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.259.08:25:32.03#ibcon#[27=USB\r\n] 2006.259.08:25:32.03#ibcon#*before write, iclass 14, count 0 2006.259.08:25:32.03#ibcon#enter sib2, iclass 14, count 0 2006.259.08:25:32.03#ibcon#flushed, iclass 14, count 0 2006.259.08:25:32.03#ibcon#about to write, iclass 14, count 0 2006.259.08:25:32.03#ibcon#wrote, iclass 14, count 0 2006.259.08:25:32.03#ibcon#about to read 3, iclass 14, count 0 2006.259.08:25:32.06#ibcon#read 3, iclass 14, count 0 2006.259.08:25:32.06#ibcon#about to read 4, iclass 14, count 0 2006.259.08:25:32.06#ibcon#read 4, iclass 14, count 0 2006.259.08:25:32.06#ibcon#about to read 5, iclass 14, count 0 2006.259.08:25:32.06#ibcon#read 5, iclass 14, count 0 2006.259.08:25:32.06#ibcon#about to read 6, iclass 14, count 0 2006.259.08:25:32.06#ibcon#read 6, iclass 14, count 0 2006.259.08:25:32.06#ibcon#end of sib2, iclass 14, count 0 2006.259.08:25:32.06#ibcon#*after write, iclass 14, count 0 2006.259.08:25:32.06#ibcon#*before return 0, iclass 14, count 0 2006.259.08:25:32.06#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.259.08:25:32.06#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.259.08:25:32.06#ibcon#about to clear, iclass 14 cls_cnt 0 2006.259.08:25:32.06#ibcon#cleared, iclass 14 cls_cnt 0 2006.259.08:25:32.06$vc4f8/vblo=2,640.99 2006.259.08:25:32.06#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.259.08:25:32.06#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.259.08:25:32.06#ibcon#ireg 17 cls_cnt 0 2006.259.08:25:32.06#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.259.08:25:32.06#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.259.08:25:32.06#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.259.08:25:32.06#ibcon#enter wrdev, iclass 16, count 0 2006.259.08:25:32.06#ibcon#first serial, iclass 16, count 0 2006.259.08:25:32.06#ibcon#enter sib2, iclass 16, count 0 2006.259.08:25:32.06#ibcon#flushed, iclass 16, count 0 2006.259.08:25:32.06#ibcon#about to write, iclass 16, count 0 2006.259.08:25:32.06#ibcon#wrote, iclass 16, count 0 2006.259.08:25:32.06#ibcon#about to read 3, iclass 16, count 0 2006.259.08:25:32.08#ibcon#read 3, iclass 16, count 0 2006.259.08:25:32.08#ibcon#about to read 4, iclass 16, count 0 2006.259.08:25:32.08#ibcon#read 4, iclass 16, count 0 2006.259.08:25:32.08#ibcon#about to read 5, iclass 16, count 0 2006.259.08:25:32.08#ibcon#read 5, iclass 16, count 0 2006.259.08:25:32.08#ibcon#about to read 6, iclass 16, count 0 2006.259.08:25:32.08#ibcon#read 6, iclass 16, count 0 2006.259.08:25:32.08#ibcon#end of sib2, iclass 16, count 0 2006.259.08:25:32.08#ibcon#*mode == 0, iclass 16, count 0 2006.259.08:25:32.08#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.259.08:25:32.08#ibcon#[28=FRQ=02,640.99\r\n] 2006.259.08:25:32.08#ibcon#*before write, iclass 16, count 0 2006.259.08:25:32.08#ibcon#enter sib2, iclass 16, count 0 2006.259.08:25:32.08#ibcon#flushed, iclass 16, count 0 2006.259.08:25:32.08#ibcon#about to write, iclass 16, count 0 2006.259.08:25:32.08#ibcon#wrote, iclass 16, count 0 2006.259.08:25:32.08#ibcon#about to read 3, iclass 16, count 0 2006.259.08:25:32.12#ibcon#read 3, iclass 16, count 0 2006.259.08:25:32.12#ibcon#about to read 4, iclass 16, count 0 2006.259.08:25:32.12#ibcon#read 4, iclass 16, count 0 2006.259.08:25:32.12#ibcon#about to read 5, iclass 16, count 0 2006.259.08:25:32.12#ibcon#read 5, iclass 16, count 0 2006.259.08:25:32.12#ibcon#about to read 6, iclass 16, count 0 2006.259.08:25:32.12#ibcon#read 6, iclass 16, count 0 2006.259.08:25:32.12#ibcon#end of sib2, iclass 16, count 0 2006.259.08:25:32.12#ibcon#*after write, iclass 16, count 0 2006.259.08:25:32.12#ibcon#*before return 0, iclass 16, count 0 2006.259.08:25:32.12#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.259.08:25:32.12#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.259.08:25:32.12#ibcon#about to clear, iclass 16 cls_cnt 0 2006.259.08:25:32.12#ibcon#cleared, iclass 16 cls_cnt 0 2006.259.08:25:32.12$vc4f8/vb=2,5 2006.259.08:25:32.12#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.259.08:25:32.12#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.259.08:25:32.12#ibcon#ireg 11 cls_cnt 2 2006.259.08:25:32.12#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.259.08:25:32.18#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.259.08:25:32.18#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.259.08:25:32.18#ibcon#enter wrdev, iclass 18, count 2 2006.259.08:25:32.18#ibcon#first serial, iclass 18, count 2 2006.259.08:25:32.18#ibcon#enter sib2, iclass 18, count 2 2006.259.08:25:32.18#ibcon#flushed, iclass 18, count 2 2006.259.08:25:32.18#ibcon#about to write, iclass 18, count 2 2006.259.08:25:32.18#ibcon#wrote, iclass 18, count 2 2006.259.08:25:32.18#ibcon#about to read 3, iclass 18, count 2 2006.259.08:25:32.20#ibcon#read 3, iclass 18, count 2 2006.259.08:25:32.20#ibcon#about to read 4, iclass 18, count 2 2006.259.08:25:32.20#ibcon#read 4, iclass 18, count 2 2006.259.08:25:32.20#ibcon#about to read 5, iclass 18, count 2 2006.259.08:25:32.20#ibcon#read 5, iclass 18, count 2 2006.259.08:25:32.20#ibcon#about to read 6, iclass 18, count 2 2006.259.08:25:32.20#ibcon#read 6, iclass 18, count 2 2006.259.08:25:32.20#ibcon#end of sib2, iclass 18, count 2 2006.259.08:25:32.20#ibcon#*mode == 0, iclass 18, count 2 2006.259.08:25:32.20#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.259.08:25:32.20#ibcon#[27=AT02-05\r\n] 2006.259.08:25:32.20#ibcon#*before write, iclass 18, count 2 2006.259.08:25:32.20#ibcon#enter sib2, iclass 18, count 2 2006.259.08:25:32.20#ibcon#flushed, iclass 18, count 2 2006.259.08:25:32.20#ibcon#about to write, iclass 18, count 2 2006.259.08:25:32.20#ibcon#wrote, iclass 18, count 2 2006.259.08:25:32.20#ibcon#about to read 3, iclass 18, count 2 2006.259.08:25:32.23#ibcon#read 3, iclass 18, count 2 2006.259.08:25:32.23#ibcon#about to read 4, iclass 18, count 2 2006.259.08:25:32.23#ibcon#read 4, iclass 18, count 2 2006.259.08:25:32.23#ibcon#about to read 5, iclass 18, count 2 2006.259.08:25:32.23#ibcon#read 5, iclass 18, count 2 2006.259.08:25:32.23#ibcon#about to read 6, iclass 18, count 2 2006.259.08:25:32.23#ibcon#read 6, iclass 18, count 2 2006.259.08:25:32.23#ibcon#end of sib2, iclass 18, count 2 2006.259.08:25:32.23#ibcon#*after write, iclass 18, count 2 2006.259.08:25:32.23#ibcon#*before return 0, iclass 18, count 2 2006.259.08:25:32.23#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.259.08:25:32.23#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.259.08:25:32.23#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.259.08:25:32.23#ibcon#ireg 7 cls_cnt 0 2006.259.08:25:32.23#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.259.08:25:32.35#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.259.08:25:32.35#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.259.08:25:32.35#ibcon#enter wrdev, iclass 18, count 0 2006.259.08:25:32.35#ibcon#first serial, iclass 18, count 0 2006.259.08:25:32.35#ibcon#enter sib2, iclass 18, count 0 2006.259.08:25:32.35#ibcon#flushed, iclass 18, count 0 2006.259.08:25:32.35#ibcon#about to write, iclass 18, count 0 2006.259.08:25:32.35#ibcon#wrote, iclass 18, count 0 2006.259.08:25:32.35#ibcon#about to read 3, iclass 18, count 0 2006.259.08:25:32.37#ibcon#read 3, iclass 18, count 0 2006.259.08:25:32.37#ibcon#about to read 4, iclass 18, count 0 2006.259.08:25:32.37#ibcon#read 4, iclass 18, count 0 2006.259.08:25:32.37#ibcon#about to read 5, iclass 18, count 0 2006.259.08:25:32.37#ibcon#read 5, iclass 18, count 0 2006.259.08:25:32.37#ibcon#about to read 6, iclass 18, count 0 2006.259.08:25:32.37#ibcon#read 6, iclass 18, count 0 2006.259.08:25:32.37#ibcon#end of sib2, iclass 18, count 0 2006.259.08:25:32.37#ibcon#*mode == 0, iclass 18, count 0 2006.259.08:25:32.37#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.259.08:25:32.37#ibcon#[27=USB\r\n] 2006.259.08:25:32.37#ibcon#*before write, iclass 18, count 0 2006.259.08:25:32.37#ibcon#enter sib2, iclass 18, count 0 2006.259.08:25:32.37#ibcon#flushed, iclass 18, count 0 2006.259.08:25:32.37#ibcon#about to write, iclass 18, count 0 2006.259.08:25:32.37#ibcon#wrote, iclass 18, count 0 2006.259.08:25:32.37#ibcon#about to read 3, iclass 18, count 0 2006.259.08:25:32.40#ibcon#read 3, iclass 18, count 0 2006.259.08:25:32.40#ibcon#about to read 4, iclass 18, count 0 2006.259.08:25:32.40#ibcon#read 4, iclass 18, count 0 2006.259.08:25:32.40#ibcon#about to read 5, iclass 18, count 0 2006.259.08:25:32.40#ibcon#read 5, iclass 18, count 0 2006.259.08:25:32.40#ibcon#about to read 6, iclass 18, count 0 2006.259.08:25:32.40#ibcon#read 6, iclass 18, count 0 2006.259.08:25:32.40#ibcon#end of sib2, iclass 18, count 0 2006.259.08:25:32.40#ibcon#*after write, iclass 18, count 0 2006.259.08:25:32.40#ibcon#*before return 0, iclass 18, count 0 2006.259.08:25:32.40#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.259.08:25:32.40#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.259.08:25:32.40#ibcon#about to clear, iclass 18 cls_cnt 0 2006.259.08:25:32.40#ibcon#cleared, iclass 18 cls_cnt 0 2006.259.08:25:32.40$vc4f8/vblo=3,656.99 2006.259.08:25:32.40#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.259.08:25:32.40#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.259.08:25:32.40#ibcon#ireg 17 cls_cnt 0 2006.259.08:25:32.40#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.259.08:25:32.40#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.259.08:25:32.40#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.259.08:25:32.40#ibcon#enter wrdev, iclass 20, count 0 2006.259.08:25:32.40#ibcon#first serial, iclass 20, count 0 2006.259.08:25:32.40#ibcon#enter sib2, iclass 20, count 0 2006.259.08:25:32.40#ibcon#flushed, iclass 20, count 0 2006.259.08:25:32.40#ibcon#about to write, iclass 20, count 0 2006.259.08:25:32.40#ibcon#wrote, iclass 20, count 0 2006.259.08:25:32.40#ibcon#about to read 3, iclass 20, count 0 2006.259.08:25:32.42#ibcon#read 3, iclass 20, count 0 2006.259.08:25:32.42#ibcon#about to read 4, iclass 20, count 0 2006.259.08:25:32.42#ibcon#read 4, iclass 20, count 0 2006.259.08:25:32.42#ibcon#about to read 5, iclass 20, count 0 2006.259.08:25:32.42#ibcon#read 5, iclass 20, count 0 2006.259.08:25:32.42#ibcon#about to read 6, iclass 20, count 0 2006.259.08:25:32.42#ibcon#read 6, iclass 20, count 0 2006.259.08:25:32.42#ibcon#end of sib2, iclass 20, count 0 2006.259.08:25:32.42#ibcon#*mode == 0, iclass 20, count 0 2006.259.08:25:32.42#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.259.08:25:32.42#ibcon#[28=FRQ=03,656.99\r\n] 2006.259.08:25:32.42#ibcon#*before write, iclass 20, count 0 2006.259.08:25:32.42#ibcon#enter sib2, iclass 20, count 0 2006.259.08:25:32.42#ibcon#flushed, iclass 20, count 0 2006.259.08:25:32.42#ibcon#about to write, iclass 20, count 0 2006.259.08:25:32.42#ibcon#wrote, iclass 20, count 0 2006.259.08:25:32.42#ibcon#about to read 3, iclass 20, count 0 2006.259.08:25:32.46#ibcon#read 3, iclass 20, count 0 2006.259.08:25:32.46#ibcon#about to read 4, iclass 20, count 0 2006.259.08:25:32.46#ibcon#read 4, iclass 20, count 0 2006.259.08:25:32.46#ibcon#about to read 5, iclass 20, count 0 2006.259.08:25:32.46#ibcon#read 5, iclass 20, count 0 2006.259.08:25:32.46#ibcon#about to read 6, iclass 20, count 0 2006.259.08:25:32.46#ibcon#read 6, iclass 20, count 0 2006.259.08:25:32.46#ibcon#end of sib2, iclass 20, count 0 2006.259.08:25:32.46#ibcon#*after write, iclass 20, count 0 2006.259.08:25:32.46#ibcon#*before return 0, iclass 20, count 0 2006.259.08:25:32.46#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.259.08:25:32.46#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.259.08:25:32.46#ibcon#about to clear, iclass 20 cls_cnt 0 2006.259.08:25:32.46#ibcon#cleared, iclass 20 cls_cnt 0 2006.259.08:25:32.46$vc4f8/vb=3,4 2006.259.08:25:32.46#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.259.08:25:32.46#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.259.08:25:32.46#ibcon#ireg 11 cls_cnt 2 2006.259.08:25:32.46#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.259.08:25:32.52#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.259.08:25:32.52#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.259.08:25:32.52#ibcon#enter wrdev, iclass 22, count 2 2006.259.08:25:32.52#ibcon#first serial, iclass 22, count 2 2006.259.08:25:32.52#ibcon#enter sib2, iclass 22, count 2 2006.259.08:25:32.52#ibcon#flushed, iclass 22, count 2 2006.259.08:25:32.52#ibcon#about to write, iclass 22, count 2 2006.259.08:25:32.52#ibcon#wrote, iclass 22, count 2 2006.259.08:25:32.52#ibcon#about to read 3, iclass 22, count 2 2006.259.08:25:32.54#ibcon#read 3, iclass 22, count 2 2006.259.08:25:32.54#ibcon#about to read 4, iclass 22, count 2 2006.259.08:25:32.54#ibcon#read 4, iclass 22, count 2 2006.259.08:25:32.54#ibcon#about to read 5, iclass 22, count 2 2006.259.08:25:32.54#ibcon#read 5, iclass 22, count 2 2006.259.08:25:32.54#ibcon#about to read 6, iclass 22, count 2 2006.259.08:25:32.54#ibcon#read 6, iclass 22, count 2 2006.259.08:25:32.54#ibcon#end of sib2, iclass 22, count 2 2006.259.08:25:32.54#ibcon#*mode == 0, iclass 22, count 2 2006.259.08:25:32.54#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.259.08:25:32.54#ibcon#[27=AT03-04\r\n] 2006.259.08:25:32.54#ibcon#*before write, iclass 22, count 2 2006.259.08:25:32.54#ibcon#enter sib2, iclass 22, count 2 2006.259.08:25:32.54#ibcon#flushed, iclass 22, count 2 2006.259.08:25:32.54#ibcon#about to write, iclass 22, count 2 2006.259.08:25:32.54#ibcon#wrote, iclass 22, count 2 2006.259.08:25:32.54#ibcon#about to read 3, iclass 22, count 2 2006.259.08:25:32.57#ibcon#read 3, iclass 22, count 2 2006.259.08:25:32.57#ibcon#about to read 4, iclass 22, count 2 2006.259.08:25:32.57#ibcon#read 4, iclass 22, count 2 2006.259.08:25:32.57#ibcon#about to read 5, iclass 22, count 2 2006.259.08:25:32.57#ibcon#read 5, iclass 22, count 2 2006.259.08:25:32.57#ibcon#about to read 6, iclass 22, count 2 2006.259.08:25:32.57#ibcon#read 6, iclass 22, count 2 2006.259.08:25:32.57#ibcon#end of sib2, iclass 22, count 2 2006.259.08:25:32.57#ibcon#*after write, iclass 22, count 2 2006.259.08:25:32.57#ibcon#*before return 0, iclass 22, count 2 2006.259.08:25:32.57#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.259.08:25:32.57#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.259.08:25:32.57#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.259.08:25:32.57#ibcon#ireg 7 cls_cnt 0 2006.259.08:25:32.57#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.259.08:25:32.69#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.259.08:25:32.69#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.259.08:25:32.69#ibcon#enter wrdev, iclass 22, count 0 2006.259.08:25:32.69#ibcon#first serial, iclass 22, count 0 2006.259.08:25:32.69#ibcon#enter sib2, iclass 22, count 0 2006.259.08:25:32.69#ibcon#flushed, iclass 22, count 0 2006.259.08:25:32.69#ibcon#about to write, iclass 22, count 0 2006.259.08:25:32.69#ibcon#wrote, iclass 22, count 0 2006.259.08:25:32.69#ibcon#about to read 3, iclass 22, count 0 2006.259.08:25:32.71#ibcon#read 3, iclass 22, count 0 2006.259.08:25:32.71#ibcon#about to read 4, iclass 22, count 0 2006.259.08:25:32.71#ibcon#read 4, iclass 22, count 0 2006.259.08:25:32.71#ibcon#about to read 5, iclass 22, count 0 2006.259.08:25:32.71#ibcon#read 5, iclass 22, count 0 2006.259.08:25:32.71#ibcon#about to read 6, iclass 22, count 0 2006.259.08:25:32.71#ibcon#read 6, iclass 22, count 0 2006.259.08:25:32.71#ibcon#end of sib2, iclass 22, count 0 2006.259.08:25:32.71#ibcon#*mode == 0, iclass 22, count 0 2006.259.08:25:32.71#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.259.08:25:32.71#ibcon#[27=USB\r\n] 2006.259.08:25:32.71#ibcon#*before write, iclass 22, count 0 2006.259.08:25:32.71#ibcon#enter sib2, iclass 22, count 0 2006.259.08:25:32.71#ibcon#flushed, iclass 22, count 0 2006.259.08:25:32.71#ibcon#about to write, iclass 22, count 0 2006.259.08:25:32.71#ibcon#wrote, iclass 22, count 0 2006.259.08:25:32.71#ibcon#about to read 3, iclass 22, count 0 2006.259.08:25:32.74#ibcon#read 3, iclass 22, count 0 2006.259.08:25:32.74#ibcon#about to read 4, iclass 22, count 0 2006.259.08:25:32.74#ibcon#read 4, iclass 22, count 0 2006.259.08:25:32.74#ibcon#about to read 5, iclass 22, count 0 2006.259.08:25:32.74#ibcon#read 5, iclass 22, count 0 2006.259.08:25:32.74#ibcon#about to read 6, iclass 22, count 0 2006.259.08:25:32.74#ibcon#read 6, iclass 22, count 0 2006.259.08:25:32.74#ibcon#end of sib2, iclass 22, count 0 2006.259.08:25:32.74#ibcon#*after write, iclass 22, count 0 2006.259.08:25:32.74#ibcon#*before return 0, iclass 22, count 0 2006.259.08:25:32.74#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.259.08:25:32.74#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.259.08:25:32.74#ibcon#about to clear, iclass 22 cls_cnt 0 2006.259.08:25:32.74#ibcon#cleared, iclass 22 cls_cnt 0 2006.259.08:25:32.74$vc4f8/vblo=4,712.99 2006.259.08:25:32.74#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.259.08:25:32.74#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.259.08:25:32.74#ibcon#ireg 17 cls_cnt 0 2006.259.08:25:32.74#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.259.08:25:32.74#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.259.08:25:32.74#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.259.08:25:32.74#ibcon#enter wrdev, iclass 24, count 0 2006.259.08:25:32.74#ibcon#first serial, iclass 24, count 0 2006.259.08:25:32.74#ibcon#enter sib2, iclass 24, count 0 2006.259.08:25:32.74#ibcon#flushed, iclass 24, count 0 2006.259.08:25:32.74#ibcon#about to write, iclass 24, count 0 2006.259.08:25:32.74#ibcon#wrote, iclass 24, count 0 2006.259.08:25:32.74#ibcon#about to read 3, iclass 24, count 0 2006.259.08:25:32.76#ibcon#read 3, iclass 24, count 0 2006.259.08:25:32.76#ibcon#about to read 4, iclass 24, count 0 2006.259.08:25:32.76#ibcon#read 4, iclass 24, count 0 2006.259.08:25:32.76#ibcon#about to read 5, iclass 24, count 0 2006.259.08:25:32.76#ibcon#read 5, iclass 24, count 0 2006.259.08:25:32.76#ibcon#about to read 6, iclass 24, count 0 2006.259.08:25:32.76#ibcon#read 6, iclass 24, count 0 2006.259.08:25:32.76#ibcon#end of sib2, iclass 24, count 0 2006.259.08:25:32.76#ibcon#*mode == 0, iclass 24, count 0 2006.259.08:25:32.76#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.259.08:25:32.76#ibcon#[28=FRQ=04,712.99\r\n] 2006.259.08:25:32.76#ibcon#*before write, iclass 24, count 0 2006.259.08:25:32.76#ibcon#enter sib2, iclass 24, count 0 2006.259.08:25:32.76#ibcon#flushed, iclass 24, count 0 2006.259.08:25:32.76#ibcon#about to write, iclass 24, count 0 2006.259.08:25:32.76#ibcon#wrote, iclass 24, count 0 2006.259.08:25:32.76#ibcon#about to read 3, iclass 24, count 0 2006.259.08:25:32.80#ibcon#read 3, iclass 24, count 0 2006.259.08:25:32.80#ibcon#about to read 4, iclass 24, count 0 2006.259.08:25:32.80#ibcon#read 4, iclass 24, count 0 2006.259.08:25:32.80#ibcon#about to read 5, iclass 24, count 0 2006.259.08:25:32.80#ibcon#read 5, iclass 24, count 0 2006.259.08:25:32.80#ibcon#about to read 6, iclass 24, count 0 2006.259.08:25:32.80#ibcon#read 6, iclass 24, count 0 2006.259.08:25:32.80#ibcon#end of sib2, iclass 24, count 0 2006.259.08:25:32.80#ibcon#*after write, iclass 24, count 0 2006.259.08:25:32.80#ibcon#*before return 0, iclass 24, count 0 2006.259.08:25:32.80#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.259.08:25:32.80#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.259.08:25:32.80#ibcon#about to clear, iclass 24 cls_cnt 0 2006.259.08:25:32.80#ibcon#cleared, iclass 24 cls_cnt 0 2006.259.08:25:32.80$vc4f8/vb=4,5 2006.259.08:25:32.80#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.259.08:25:32.80#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.259.08:25:32.80#ibcon#ireg 11 cls_cnt 2 2006.259.08:25:32.80#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.259.08:25:32.86#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.259.08:25:32.86#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.259.08:25:32.86#ibcon#enter wrdev, iclass 26, count 2 2006.259.08:25:32.86#ibcon#first serial, iclass 26, count 2 2006.259.08:25:32.86#ibcon#enter sib2, iclass 26, count 2 2006.259.08:25:32.86#ibcon#flushed, iclass 26, count 2 2006.259.08:25:32.86#ibcon#about to write, iclass 26, count 2 2006.259.08:25:32.86#ibcon#wrote, iclass 26, count 2 2006.259.08:25:32.86#ibcon#about to read 3, iclass 26, count 2 2006.259.08:25:32.88#ibcon#read 3, iclass 26, count 2 2006.259.08:25:32.88#ibcon#about to read 4, iclass 26, count 2 2006.259.08:25:32.88#ibcon#read 4, iclass 26, count 2 2006.259.08:25:32.88#ibcon#about to read 5, iclass 26, count 2 2006.259.08:25:32.88#ibcon#read 5, iclass 26, count 2 2006.259.08:25:32.88#ibcon#about to read 6, iclass 26, count 2 2006.259.08:25:32.88#ibcon#read 6, iclass 26, count 2 2006.259.08:25:32.88#ibcon#end of sib2, iclass 26, count 2 2006.259.08:25:32.88#ibcon#*mode == 0, iclass 26, count 2 2006.259.08:25:32.88#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.259.08:25:32.88#ibcon#[27=AT04-05\r\n] 2006.259.08:25:32.88#ibcon#*before write, iclass 26, count 2 2006.259.08:25:32.88#ibcon#enter sib2, iclass 26, count 2 2006.259.08:25:32.88#ibcon#flushed, iclass 26, count 2 2006.259.08:25:32.88#ibcon#about to write, iclass 26, count 2 2006.259.08:25:32.88#ibcon#wrote, iclass 26, count 2 2006.259.08:25:32.88#ibcon#about to read 3, iclass 26, count 2 2006.259.08:25:32.91#ibcon#read 3, iclass 26, count 2 2006.259.08:25:32.91#ibcon#about to read 4, iclass 26, count 2 2006.259.08:25:32.91#ibcon#read 4, iclass 26, count 2 2006.259.08:25:32.91#ibcon#about to read 5, iclass 26, count 2 2006.259.08:25:32.91#ibcon#read 5, iclass 26, count 2 2006.259.08:25:32.91#ibcon#about to read 6, iclass 26, count 2 2006.259.08:25:32.91#ibcon#read 6, iclass 26, count 2 2006.259.08:25:32.91#ibcon#end of sib2, iclass 26, count 2 2006.259.08:25:32.91#ibcon#*after write, iclass 26, count 2 2006.259.08:25:32.91#ibcon#*before return 0, iclass 26, count 2 2006.259.08:25:32.91#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.259.08:25:32.91#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.259.08:25:32.91#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.259.08:25:32.91#ibcon#ireg 7 cls_cnt 0 2006.259.08:25:32.91#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.259.08:25:33.03#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.259.08:25:33.03#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.259.08:25:33.03#ibcon#enter wrdev, iclass 26, count 0 2006.259.08:25:33.03#ibcon#first serial, iclass 26, count 0 2006.259.08:25:33.03#ibcon#enter sib2, iclass 26, count 0 2006.259.08:25:33.03#ibcon#flushed, iclass 26, count 0 2006.259.08:25:33.03#ibcon#about to write, iclass 26, count 0 2006.259.08:25:33.03#ibcon#wrote, iclass 26, count 0 2006.259.08:25:33.03#ibcon#about to read 3, iclass 26, count 0 2006.259.08:25:33.05#ibcon#read 3, iclass 26, count 0 2006.259.08:25:33.05#ibcon#about to read 4, iclass 26, count 0 2006.259.08:25:33.05#ibcon#read 4, iclass 26, count 0 2006.259.08:25:33.05#ibcon#about to read 5, iclass 26, count 0 2006.259.08:25:33.05#ibcon#read 5, iclass 26, count 0 2006.259.08:25:33.05#ibcon#about to read 6, iclass 26, count 0 2006.259.08:25:33.05#ibcon#read 6, iclass 26, count 0 2006.259.08:25:33.05#ibcon#end of sib2, iclass 26, count 0 2006.259.08:25:33.05#ibcon#*mode == 0, iclass 26, count 0 2006.259.08:25:33.05#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.259.08:25:33.05#ibcon#[27=USB\r\n] 2006.259.08:25:33.05#ibcon#*before write, iclass 26, count 0 2006.259.08:25:33.05#ibcon#enter sib2, iclass 26, count 0 2006.259.08:25:33.05#ibcon#flushed, iclass 26, count 0 2006.259.08:25:33.05#ibcon#about to write, iclass 26, count 0 2006.259.08:25:33.05#ibcon#wrote, iclass 26, count 0 2006.259.08:25:33.05#ibcon#about to read 3, iclass 26, count 0 2006.259.08:25:33.08#ibcon#read 3, iclass 26, count 0 2006.259.08:25:33.08#ibcon#about to read 4, iclass 26, count 0 2006.259.08:25:33.08#ibcon#read 4, iclass 26, count 0 2006.259.08:25:33.08#ibcon#about to read 5, iclass 26, count 0 2006.259.08:25:33.08#ibcon#read 5, iclass 26, count 0 2006.259.08:25:33.08#ibcon#about to read 6, iclass 26, count 0 2006.259.08:25:33.08#ibcon#read 6, iclass 26, count 0 2006.259.08:25:33.08#ibcon#end of sib2, iclass 26, count 0 2006.259.08:25:33.08#ibcon#*after write, iclass 26, count 0 2006.259.08:25:33.08#ibcon#*before return 0, iclass 26, count 0 2006.259.08:25:33.08#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.259.08:25:33.08#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.259.08:25:33.08#ibcon#about to clear, iclass 26 cls_cnt 0 2006.259.08:25:33.08#ibcon#cleared, iclass 26 cls_cnt 0 2006.259.08:25:33.08$vc4f8/vblo=5,744.99 2006.259.08:25:33.08#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.259.08:25:33.08#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.259.08:25:33.08#ibcon#ireg 17 cls_cnt 0 2006.259.08:25:33.08#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.259.08:25:33.08#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.259.08:25:33.08#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.259.08:25:33.08#ibcon#enter wrdev, iclass 28, count 0 2006.259.08:25:33.08#ibcon#first serial, iclass 28, count 0 2006.259.08:25:33.08#ibcon#enter sib2, iclass 28, count 0 2006.259.08:25:33.08#ibcon#flushed, iclass 28, count 0 2006.259.08:25:33.08#ibcon#about to write, iclass 28, count 0 2006.259.08:25:33.08#ibcon#wrote, iclass 28, count 0 2006.259.08:25:33.08#ibcon#about to read 3, iclass 28, count 0 2006.259.08:25:33.10#ibcon#read 3, iclass 28, count 0 2006.259.08:25:33.10#ibcon#about to read 4, iclass 28, count 0 2006.259.08:25:33.10#ibcon#read 4, iclass 28, count 0 2006.259.08:25:33.10#ibcon#about to read 5, iclass 28, count 0 2006.259.08:25:33.10#ibcon#read 5, iclass 28, count 0 2006.259.08:25:33.10#ibcon#about to read 6, iclass 28, count 0 2006.259.08:25:33.10#ibcon#read 6, iclass 28, count 0 2006.259.08:25:33.10#ibcon#end of sib2, iclass 28, count 0 2006.259.08:25:33.10#ibcon#*mode == 0, iclass 28, count 0 2006.259.08:25:33.10#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.259.08:25:33.10#ibcon#[28=FRQ=05,744.99\r\n] 2006.259.08:25:33.10#ibcon#*before write, iclass 28, count 0 2006.259.08:25:33.10#ibcon#enter sib2, iclass 28, count 0 2006.259.08:25:33.10#ibcon#flushed, iclass 28, count 0 2006.259.08:25:33.10#ibcon#about to write, iclass 28, count 0 2006.259.08:25:33.10#ibcon#wrote, iclass 28, count 0 2006.259.08:25:33.10#ibcon#about to read 3, iclass 28, count 0 2006.259.08:25:33.15#ibcon#read 3, iclass 28, count 0 2006.259.08:25:33.15#ibcon#about to read 4, iclass 28, count 0 2006.259.08:25:33.15#ibcon#read 4, iclass 28, count 0 2006.259.08:25:33.15#ibcon#about to read 5, iclass 28, count 0 2006.259.08:25:33.15#ibcon#read 5, iclass 28, count 0 2006.259.08:25:33.15#ibcon#about to read 6, iclass 28, count 0 2006.259.08:25:33.15#ibcon#read 6, iclass 28, count 0 2006.259.08:25:33.15#ibcon#end of sib2, iclass 28, count 0 2006.259.08:25:33.15#ibcon#*after write, iclass 28, count 0 2006.259.08:25:33.15#ibcon#*before return 0, iclass 28, count 0 2006.259.08:25:33.15#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.259.08:25:33.15#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.259.08:25:33.15#ibcon#about to clear, iclass 28 cls_cnt 0 2006.259.08:25:33.15#ibcon#cleared, iclass 28 cls_cnt 0 2006.259.08:25:33.15$vc4f8/vb=5,4 2006.259.08:25:33.15#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.259.08:25:33.15#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.259.08:25:33.15#ibcon#ireg 11 cls_cnt 2 2006.259.08:25:33.15#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.259.08:25:33.20#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.259.08:25:33.20#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.259.08:25:33.20#ibcon#enter wrdev, iclass 30, count 2 2006.259.08:25:33.20#ibcon#first serial, iclass 30, count 2 2006.259.08:25:33.20#ibcon#enter sib2, iclass 30, count 2 2006.259.08:25:33.20#ibcon#flushed, iclass 30, count 2 2006.259.08:25:33.20#ibcon#about to write, iclass 30, count 2 2006.259.08:25:33.20#ibcon#wrote, iclass 30, count 2 2006.259.08:25:33.20#ibcon#about to read 3, iclass 30, count 2 2006.259.08:25:33.22#ibcon#read 3, iclass 30, count 2 2006.259.08:25:33.22#ibcon#about to read 4, iclass 30, count 2 2006.259.08:25:33.22#ibcon#read 4, iclass 30, count 2 2006.259.08:25:33.22#ibcon#about to read 5, iclass 30, count 2 2006.259.08:25:33.22#ibcon#read 5, iclass 30, count 2 2006.259.08:25:33.22#ibcon#about to read 6, iclass 30, count 2 2006.259.08:25:33.22#ibcon#read 6, iclass 30, count 2 2006.259.08:25:33.22#ibcon#end of sib2, iclass 30, count 2 2006.259.08:25:33.22#ibcon#*mode == 0, iclass 30, count 2 2006.259.08:25:33.22#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.259.08:25:33.22#ibcon#[27=AT05-04\r\n] 2006.259.08:25:33.22#ibcon#*before write, iclass 30, count 2 2006.259.08:25:33.22#ibcon#enter sib2, iclass 30, count 2 2006.259.08:25:33.22#ibcon#flushed, iclass 30, count 2 2006.259.08:25:33.22#ibcon#about to write, iclass 30, count 2 2006.259.08:25:33.22#ibcon#wrote, iclass 30, count 2 2006.259.08:25:33.22#ibcon#about to read 3, iclass 30, count 2 2006.259.08:25:33.25#ibcon#read 3, iclass 30, count 2 2006.259.08:25:33.25#ibcon#about to read 4, iclass 30, count 2 2006.259.08:25:33.25#ibcon#read 4, iclass 30, count 2 2006.259.08:25:33.25#ibcon#about to read 5, iclass 30, count 2 2006.259.08:25:33.25#ibcon#read 5, iclass 30, count 2 2006.259.08:25:33.25#ibcon#about to read 6, iclass 30, count 2 2006.259.08:25:33.25#ibcon#read 6, iclass 30, count 2 2006.259.08:25:33.25#ibcon#end of sib2, iclass 30, count 2 2006.259.08:25:33.25#ibcon#*after write, iclass 30, count 2 2006.259.08:25:33.25#ibcon#*before return 0, iclass 30, count 2 2006.259.08:25:33.25#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.259.08:25:33.25#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.259.08:25:33.25#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.259.08:25:33.25#ibcon#ireg 7 cls_cnt 0 2006.259.08:25:33.25#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.259.08:25:33.37#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.259.08:25:33.37#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.259.08:25:33.37#ibcon#enter wrdev, iclass 30, count 0 2006.259.08:25:33.37#ibcon#first serial, iclass 30, count 0 2006.259.08:25:33.37#ibcon#enter sib2, iclass 30, count 0 2006.259.08:25:33.37#ibcon#flushed, iclass 30, count 0 2006.259.08:25:33.37#ibcon#about to write, iclass 30, count 0 2006.259.08:25:33.37#ibcon#wrote, iclass 30, count 0 2006.259.08:25:33.37#ibcon#about to read 3, iclass 30, count 0 2006.259.08:25:33.39#ibcon#read 3, iclass 30, count 0 2006.259.08:25:33.39#ibcon#about to read 4, iclass 30, count 0 2006.259.08:25:33.39#ibcon#read 4, iclass 30, count 0 2006.259.08:25:33.39#ibcon#about to read 5, iclass 30, count 0 2006.259.08:25:33.39#ibcon#read 5, iclass 30, count 0 2006.259.08:25:33.39#ibcon#about to read 6, iclass 30, count 0 2006.259.08:25:33.39#ibcon#read 6, iclass 30, count 0 2006.259.08:25:33.39#ibcon#end of sib2, iclass 30, count 0 2006.259.08:25:33.39#ibcon#*mode == 0, iclass 30, count 0 2006.259.08:25:33.39#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.259.08:25:33.39#ibcon#[27=USB\r\n] 2006.259.08:25:33.39#ibcon#*before write, iclass 30, count 0 2006.259.08:25:33.39#ibcon#enter sib2, iclass 30, count 0 2006.259.08:25:33.39#ibcon#flushed, iclass 30, count 0 2006.259.08:25:33.39#ibcon#about to write, iclass 30, count 0 2006.259.08:25:33.39#ibcon#wrote, iclass 30, count 0 2006.259.08:25:33.39#ibcon#about to read 3, iclass 30, count 0 2006.259.08:25:33.42#ibcon#read 3, iclass 30, count 0 2006.259.08:25:33.42#ibcon#about to read 4, iclass 30, count 0 2006.259.08:25:33.42#ibcon#read 4, iclass 30, count 0 2006.259.08:25:33.42#ibcon#about to read 5, iclass 30, count 0 2006.259.08:25:33.42#ibcon#read 5, iclass 30, count 0 2006.259.08:25:33.42#ibcon#about to read 6, iclass 30, count 0 2006.259.08:25:33.42#ibcon#read 6, iclass 30, count 0 2006.259.08:25:33.42#ibcon#end of sib2, iclass 30, count 0 2006.259.08:25:33.42#ibcon#*after write, iclass 30, count 0 2006.259.08:25:33.42#ibcon#*before return 0, iclass 30, count 0 2006.259.08:25:33.42#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.259.08:25:33.42#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.259.08:25:33.42#ibcon#about to clear, iclass 30 cls_cnt 0 2006.259.08:25:33.42#ibcon#cleared, iclass 30 cls_cnt 0 2006.259.08:25:33.42$vc4f8/vblo=6,752.99 2006.259.08:25:33.42#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.259.08:25:33.42#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.259.08:25:33.42#ibcon#ireg 17 cls_cnt 0 2006.259.08:25:33.42#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.259.08:25:33.42#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.259.08:25:33.42#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.259.08:25:33.42#ibcon#enter wrdev, iclass 32, count 0 2006.259.08:25:33.42#ibcon#first serial, iclass 32, count 0 2006.259.08:25:33.42#ibcon#enter sib2, iclass 32, count 0 2006.259.08:25:33.42#ibcon#flushed, iclass 32, count 0 2006.259.08:25:33.42#ibcon#about to write, iclass 32, count 0 2006.259.08:25:33.42#ibcon#wrote, iclass 32, count 0 2006.259.08:25:33.42#ibcon#about to read 3, iclass 32, count 0 2006.259.08:25:33.44#ibcon#read 3, iclass 32, count 0 2006.259.08:25:33.44#ibcon#about to read 4, iclass 32, count 0 2006.259.08:25:33.44#ibcon#read 4, iclass 32, count 0 2006.259.08:25:33.44#ibcon#about to read 5, iclass 32, count 0 2006.259.08:25:33.44#ibcon#read 5, iclass 32, count 0 2006.259.08:25:33.44#ibcon#about to read 6, iclass 32, count 0 2006.259.08:25:33.44#ibcon#read 6, iclass 32, count 0 2006.259.08:25:33.44#ibcon#end of sib2, iclass 32, count 0 2006.259.08:25:33.44#ibcon#*mode == 0, iclass 32, count 0 2006.259.08:25:33.44#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.259.08:25:33.44#ibcon#[28=FRQ=06,752.99\r\n] 2006.259.08:25:33.44#ibcon#*before write, iclass 32, count 0 2006.259.08:25:33.44#ibcon#enter sib2, iclass 32, count 0 2006.259.08:25:33.44#ibcon#flushed, iclass 32, count 0 2006.259.08:25:33.44#ibcon#about to write, iclass 32, count 0 2006.259.08:25:33.44#ibcon#wrote, iclass 32, count 0 2006.259.08:25:33.44#ibcon#about to read 3, iclass 32, count 0 2006.259.08:25:33.48#ibcon#read 3, iclass 32, count 0 2006.259.08:25:33.48#ibcon#about to read 4, iclass 32, count 0 2006.259.08:25:33.48#ibcon#read 4, iclass 32, count 0 2006.259.08:25:33.48#ibcon#about to read 5, iclass 32, count 0 2006.259.08:25:33.48#ibcon#read 5, iclass 32, count 0 2006.259.08:25:33.48#ibcon#about to read 6, iclass 32, count 0 2006.259.08:25:33.48#ibcon#read 6, iclass 32, count 0 2006.259.08:25:33.48#ibcon#end of sib2, iclass 32, count 0 2006.259.08:25:33.48#ibcon#*after write, iclass 32, count 0 2006.259.08:25:33.48#ibcon#*before return 0, iclass 32, count 0 2006.259.08:25:33.48#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.259.08:25:33.48#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.259.08:25:33.48#ibcon#about to clear, iclass 32 cls_cnt 0 2006.259.08:25:33.48#ibcon#cleared, iclass 32 cls_cnt 0 2006.259.08:25:33.48$vc4f8/vb=6,4 2006.259.08:25:33.48#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.259.08:25:33.48#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.259.08:25:33.48#ibcon#ireg 11 cls_cnt 2 2006.259.08:25:33.48#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.259.08:25:33.54#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.259.08:25:33.54#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.259.08:25:33.54#ibcon#enter wrdev, iclass 34, count 2 2006.259.08:25:33.54#ibcon#first serial, iclass 34, count 2 2006.259.08:25:33.54#ibcon#enter sib2, iclass 34, count 2 2006.259.08:25:33.54#ibcon#flushed, iclass 34, count 2 2006.259.08:25:33.54#ibcon#about to write, iclass 34, count 2 2006.259.08:25:33.54#ibcon#wrote, iclass 34, count 2 2006.259.08:25:33.54#ibcon#about to read 3, iclass 34, count 2 2006.259.08:25:33.56#ibcon#read 3, iclass 34, count 2 2006.259.08:25:33.56#ibcon#about to read 4, iclass 34, count 2 2006.259.08:25:33.56#ibcon#read 4, iclass 34, count 2 2006.259.08:25:33.56#ibcon#about to read 5, iclass 34, count 2 2006.259.08:25:33.56#ibcon#read 5, iclass 34, count 2 2006.259.08:25:33.56#ibcon#about to read 6, iclass 34, count 2 2006.259.08:25:33.56#ibcon#read 6, iclass 34, count 2 2006.259.08:25:33.56#ibcon#end of sib2, iclass 34, count 2 2006.259.08:25:33.56#ibcon#*mode == 0, iclass 34, count 2 2006.259.08:25:33.56#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.259.08:25:33.56#ibcon#[27=AT06-04\r\n] 2006.259.08:25:33.56#ibcon#*before write, iclass 34, count 2 2006.259.08:25:33.56#ibcon#enter sib2, iclass 34, count 2 2006.259.08:25:33.56#ibcon#flushed, iclass 34, count 2 2006.259.08:25:33.56#ibcon#about to write, iclass 34, count 2 2006.259.08:25:33.56#ibcon#wrote, iclass 34, count 2 2006.259.08:25:33.56#ibcon#about to read 3, iclass 34, count 2 2006.259.08:25:33.59#ibcon#read 3, iclass 34, count 2 2006.259.08:25:33.59#ibcon#about to read 4, iclass 34, count 2 2006.259.08:25:33.59#ibcon#read 4, iclass 34, count 2 2006.259.08:25:33.59#ibcon#about to read 5, iclass 34, count 2 2006.259.08:25:33.59#ibcon#read 5, iclass 34, count 2 2006.259.08:25:33.59#ibcon#about to read 6, iclass 34, count 2 2006.259.08:25:33.59#ibcon#read 6, iclass 34, count 2 2006.259.08:25:33.59#ibcon#end of sib2, iclass 34, count 2 2006.259.08:25:33.59#ibcon#*after write, iclass 34, count 2 2006.259.08:25:33.59#ibcon#*before return 0, iclass 34, count 2 2006.259.08:25:33.59#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.259.08:25:33.59#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.259.08:25:33.59#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.259.08:25:33.59#ibcon#ireg 7 cls_cnt 0 2006.259.08:25:33.59#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.259.08:25:33.71#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.259.08:25:33.71#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.259.08:25:33.71#ibcon#enter wrdev, iclass 34, count 0 2006.259.08:25:33.71#ibcon#first serial, iclass 34, count 0 2006.259.08:25:33.71#ibcon#enter sib2, iclass 34, count 0 2006.259.08:25:33.71#ibcon#flushed, iclass 34, count 0 2006.259.08:25:33.71#ibcon#about to write, iclass 34, count 0 2006.259.08:25:33.71#ibcon#wrote, iclass 34, count 0 2006.259.08:25:33.71#ibcon#about to read 3, iclass 34, count 0 2006.259.08:25:33.73#ibcon#read 3, iclass 34, count 0 2006.259.08:25:33.73#ibcon#about to read 4, iclass 34, count 0 2006.259.08:25:33.73#ibcon#read 4, iclass 34, count 0 2006.259.08:25:33.73#ibcon#about to read 5, iclass 34, count 0 2006.259.08:25:33.73#ibcon#read 5, iclass 34, count 0 2006.259.08:25:33.73#ibcon#about to read 6, iclass 34, count 0 2006.259.08:25:33.73#ibcon#read 6, iclass 34, count 0 2006.259.08:25:33.73#ibcon#end of sib2, iclass 34, count 0 2006.259.08:25:33.73#ibcon#*mode == 0, iclass 34, count 0 2006.259.08:25:33.73#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.259.08:25:33.73#ibcon#[27=USB\r\n] 2006.259.08:25:33.73#ibcon#*before write, iclass 34, count 0 2006.259.08:25:33.73#ibcon#enter sib2, iclass 34, count 0 2006.259.08:25:33.73#ibcon#flushed, iclass 34, count 0 2006.259.08:25:33.73#ibcon#about to write, iclass 34, count 0 2006.259.08:25:33.73#ibcon#wrote, iclass 34, count 0 2006.259.08:25:33.73#ibcon#about to read 3, iclass 34, count 0 2006.259.08:25:33.76#ibcon#read 3, iclass 34, count 0 2006.259.08:25:33.76#ibcon#about to read 4, iclass 34, count 0 2006.259.08:25:33.76#ibcon#read 4, iclass 34, count 0 2006.259.08:25:33.76#ibcon#about to read 5, iclass 34, count 0 2006.259.08:25:33.76#ibcon#read 5, iclass 34, count 0 2006.259.08:25:33.76#ibcon#about to read 6, iclass 34, count 0 2006.259.08:25:33.76#ibcon#read 6, iclass 34, count 0 2006.259.08:25:33.76#ibcon#end of sib2, iclass 34, count 0 2006.259.08:25:33.76#ibcon#*after write, iclass 34, count 0 2006.259.08:25:33.76#ibcon#*before return 0, iclass 34, count 0 2006.259.08:25:33.76#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.259.08:25:33.76#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.259.08:25:33.76#ibcon#about to clear, iclass 34 cls_cnt 0 2006.259.08:25:33.76#ibcon#cleared, iclass 34 cls_cnt 0 2006.259.08:25:33.76$vc4f8/vabw=wide 2006.259.08:25:33.76#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.259.08:25:33.76#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.259.08:25:33.76#ibcon#ireg 8 cls_cnt 0 2006.259.08:25:33.76#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.259.08:25:33.76#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.259.08:25:33.76#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.259.08:25:33.76#ibcon#enter wrdev, iclass 36, count 0 2006.259.08:25:33.76#ibcon#first serial, iclass 36, count 0 2006.259.08:25:33.76#ibcon#enter sib2, iclass 36, count 0 2006.259.08:25:33.76#ibcon#flushed, iclass 36, count 0 2006.259.08:25:33.76#ibcon#about to write, iclass 36, count 0 2006.259.08:25:33.76#ibcon#wrote, iclass 36, count 0 2006.259.08:25:33.76#ibcon#about to read 3, iclass 36, count 0 2006.259.08:25:33.78#ibcon#read 3, iclass 36, count 0 2006.259.08:25:33.78#ibcon#about to read 4, iclass 36, count 0 2006.259.08:25:33.78#ibcon#read 4, iclass 36, count 0 2006.259.08:25:33.78#ibcon#about to read 5, iclass 36, count 0 2006.259.08:25:33.78#ibcon#read 5, iclass 36, count 0 2006.259.08:25:33.78#ibcon#about to read 6, iclass 36, count 0 2006.259.08:25:33.78#ibcon#read 6, iclass 36, count 0 2006.259.08:25:33.78#ibcon#end of sib2, iclass 36, count 0 2006.259.08:25:33.78#ibcon#*mode == 0, iclass 36, count 0 2006.259.08:25:33.78#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.259.08:25:33.78#ibcon#[25=BW32\r\n] 2006.259.08:25:33.78#ibcon#*before write, iclass 36, count 0 2006.259.08:25:33.78#ibcon#enter sib2, iclass 36, count 0 2006.259.08:25:33.78#ibcon#flushed, iclass 36, count 0 2006.259.08:25:33.78#ibcon#about to write, iclass 36, count 0 2006.259.08:25:33.78#ibcon#wrote, iclass 36, count 0 2006.259.08:25:33.78#ibcon#about to read 3, iclass 36, count 0 2006.259.08:25:33.81#ibcon#read 3, iclass 36, count 0 2006.259.08:25:33.81#ibcon#about to read 4, iclass 36, count 0 2006.259.08:25:33.81#ibcon#read 4, iclass 36, count 0 2006.259.08:25:33.81#ibcon#about to read 5, iclass 36, count 0 2006.259.08:25:33.81#ibcon#read 5, iclass 36, count 0 2006.259.08:25:33.81#ibcon#about to read 6, iclass 36, count 0 2006.259.08:25:33.81#ibcon#read 6, iclass 36, count 0 2006.259.08:25:33.81#ibcon#end of sib2, iclass 36, count 0 2006.259.08:25:33.81#ibcon#*after write, iclass 36, count 0 2006.259.08:25:33.81#ibcon#*before return 0, iclass 36, count 0 2006.259.08:25:33.81#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.259.08:25:33.81#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.259.08:25:33.81#ibcon#about to clear, iclass 36 cls_cnt 0 2006.259.08:25:33.81#ibcon#cleared, iclass 36 cls_cnt 0 2006.259.08:25:33.81$vc4f8/vbbw=wide 2006.259.08:25:33.81#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.259.08:25:33.81#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.259.08:25:33.81#ibcon#ireg 8 cls_cnt 0 2006.259.08:25:33.81#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.259.08:25:33.88#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.259.08:25:33.88#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.259.08:25:33.88#ibcon#enter wrdev, iclass 38, count 0 2006.259.08:25:33.88#ibcon#first serial, iclass 38, count 0 2006.259.08:25:33.88#ibcon#enter sib2, iclass 38, count 0 2006.259.08:25:33.88#ibcon#flushed, iclass 38, count 0 2006.259.08:25:33.88#ibcon#about to write, iclass 38, count 0 2006.259.08:25:33.88#ibcon#wrote, iclass 38, count 0 2006.259.08:25:33.88#ibcon#about to read 3, iclass 38, count 0 2006.259.08:25:33.90#ibcon#read 3, iclass 38, count 0 2006.259.08:25:33.90#ibcon#about to read 4, iclass 38, count 0 2006.259.08:25:33.90#ibcon#read 4, iclass 38, count 0 2006.259.08:25:33.90#ibcon#about to read 5, iclass 38, count 0 2006.259.08:25:33.90#ibcon#read 5, iclass 38, count 0 2006.259.08:25:33.90#ibcon#about to read 6, iclass 38, count 0 2006.259.08:25:33.90#ibcon#read 6, iclass 38, count 0 2006.259.08:25:33.90#ibcon#end of sib2, iclass 38, count 0 2006.259.08:25:33.90#ibcon#*mode == 0, iclass 38, count 0 2006.259.08:25:33.90#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.259.08:25:33.90#ibcon#[27=BW32\r\n] 2006.259.08:25:33.90#ibcon#*before write, iclass 38, count 0 2006.259.08:25:33.90#ibcon#enter sib2, iclass 38, count 0 2006.259.08:25:33.90#ibcon#flushed, iclass 38, count 0 2006.259.08:25:33.90#ibcon#about to write, iclass 38, count 0 2006.259.08:25:33.90#ibcon#wrote, iclass 38, count 0 2006.259.08:25:33.90#ibcon#about to read 3, iclass 38, count 0 2006.259.08:25:33.93#ibcon#read 3, iclass 38, count 0 2006.259.08:25:33.93#ibcon#about to read 4, iclass 38, count 0 2006.259.08:25:33.93#ibcon#read 4, iclass 38, count 0 2006.259.08:25:33.93#ibcon#about to read 5, iclass 38, count 0 2006.259.08:25:33.93#ibcon#read 5, iclass 38, count 0 2006.259.08:25:33.93#ibcon#about to read 6, iclass 38, count 0 2006.259.08:25:33.93#ibcon#read 6, iclass 38, count 0 2006.259.08:25:33.93#ibcon#end of sib2, iclass 38, count 0 2006.259.08:25:33.93#ibcon#*after write, iclass 38, count 0 2006.259.08:25:33.93#ibcon#*before return 0, iclass 38, count 0 2006.259.08:25:33.93#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.259.08:25:33.93#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.259.08:25:33.93#ibcon#about to clear, iclass 38 cls_cnt 0 2006.259.08:25:33.93#ibcon#cleared, iclass 38 cls_cnt 0 2006.259.08:25:33.93$4f8m12a/ifd4f 2006.259.08:25:33.93$ifd4f/lo= 2006.259.08:25:33.93$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.259.08:25:33.93$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.259.08:25:33.93$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.259.08:25:33.93$ifd4f/patch= 2006.259.08:25:33.93$ifd4f/patch=lo1,a1,a2,a3,a4 2006.259.08:25:33.93$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.259.08:25:33.93$ifd4f/patch=lo3,a5,a6,a7,a8 2006.259.08:25:33.93$4f8m12a/"form=m,16.000,1:2 2006.259.08:25:33.93$4f8m12a/"tpicd 2006.259.08:25:33.93$4f8m12a/echo=off 2006.259.08:25:33.93$4f8m12a/xlog=off 2006.259.08:25:33.93:!2006.259.08:26:00 2006.259.08:25:37.14#trakl#Source acquired 2006.259.08:25:39.14#flagr#flagr/antenna,acquired 2006.259.08:26:00.00:preob 2006.259.08:26:01.14/onsource/TRACKING 2006.259.08:26:01.14:!2006.259.08:26:10 2006.259.08:26:10.00:data_valid=on 2006.259.08:26:10.00:midob 2006.259.08:26:10.14/onsource/TRACKING 2006.259.08:26:10.14/wx/21.66,1013.2,85 2006.259.08:26:10.24/cable/+6.4594E-03 2006.259.08:26:11.33/va/01,08,usb,yes,35,36 2006.259.08:26:11.33/va/02,07,usb,yes,35,36 2006.259.08:26:11.33/va/03,08,usb,yes,26,27 2006.259.08:26:11.33/va/04,07,usb,yes,36,39 2006.259.08:26:11.33/va/05,07,usb,yes,40,43 2006.259.08:26:11.33/va/06,06,usb,yes,40,39 2006.259.08:26:11.33/va/07,06,usb,yes,40,40 2006.259.08:26:11.33/va/08,06,usb,yes,43,42 2006.259.08:26:11.56/valo/01,532.99,yes,locked 2006.259.08:26:11.56/valo/02,572.99,yes,locked 2006.259.08:26:11.56/valo/03,672.99,yes,locked 2006.259.08:26:11.56/valo/04,832.99,yes,locked 2006.259.08:26:11.56/valo/05,652.99,yes,locked 2006.259.08:26:11.56/valo/06,772.99,yes,locked 2006.259.08:26:11.56/valo/07,832.99,yes,locked 2006.259.08:26:11.56/valo/08,852.99,yes,locked 2006.259.08:26:12.65/vb/01,04,usb,yes,32,31 2006.259.08:26:12.65/vb/02,05,usb,yes,30,31 2006.259.08:26:12.65/vb/03,04,usb,yes,31,34 2006.259.08:26:12.65/vb/04,05,usb,yes,28,28 2006.259.08:26:12.65/vb/05,04,usb,yes,30,34 2006.259.08:26:12.65/vb/06,04,usb,yes,31,34 2006.259.08:26:12.65/vb/07,04,usb,yes,33,33 2006.259.08:26:12.65/vb/08,04,usb,yes,31,34 2006.259.08:26:12.89/vblo/01,632.99,yes,locked 2006.259.08:26:12.89/vblo/02,640.99,yes,locked 2006.259.08:26:12.89/vblo/03,656.99,yes,locked 2006.259.08:26:12.89/vblo/04,712.99,yes,locked 2006.259.08:26:12.89/vblo/05,744.99,yes,locked 2006.259.08:26:12.89/vblo/06,752.99,yes,locked 2006.259.08:26:12.89/vblo/07,734.99,yes,locked 2006.259.08:26:12.89/vblo/08,744.99,yes,locked 2006.259.08:26:13.04/vabw/8 2006.259.08:26:13.19/vbbw/8 2006.259.08:26:13.28/xfe/off,on,15.2 2006.259.08:26:13.66/ifatt/23,28,28,28 2006.259.08:26:14.08/fmout-gps/S +4.53E-07 2006.259.08:26:14.12:!2006.259.08:27:10 2006.259.08:27:10.00:data_valid=off 2006.259.08:27:10.00:postob 2006.259.08:27:10.24/cable/+6.4597E-03 2006.259.08:27:10.24/wx/21.64,1013.2,85 2006.259.08:27:11.08/fmout-gps/S +4.52E-07 2006.259.08:27:11.08:checkk5last 2006.259.08:27:11.08&checkk5last/chk_obsdata=1 2006.259.08:27:11.09&checkk5last/chk_obsdata=2 2006.259.08:27:11.09&checkk5last/chk_obsdata=3 2006.259.08:27:11.09&checkk5last/chk_obsdata=4 2006.259.08:27:11.10&checkk5last/k5log=1 2006.259.08:27:11.10&checkk5last/k5log=2 2006.259.08:27:11.10&checkk5last/k5log=3 2006.259.08:27:11.11&checkk5last/k5log=4 2006.259.08:27:11.11&checkk5last/obsinfo 2006.259.08:27:11.55/chk_obsdata//k5ts1/T2590826??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.259.08:27:11.97/chk_obsdata//k5ts2/T2590826??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.259.08:27:12.43/chk_obsdata//k5ts3/T2590826??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.259.08:27:12.81/chk_obsdata//k5ts4/T2590826??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.259.08:27:13.59/k5log//k5ts1_log_newline 2006.259.08:27:14.36/k5log//k5ts2_log_newline 2006.259.08:27:15.30/k5log//k5ts3_log_newline 2006.259.08:27:16.29/k5log//k5ts4_log_newline 2006.259.08:27:16.31/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.259.08:27:16.31:"sched_end 2006.259.08:27:16.31:source=idle 2006.259.08:27:17.14:stow 2006.259.08:27:17.14&stow/source=idle 2006.259.08:27:17.14&stow/"this is stow command. 2006.259.08:27:17.14&stow/antenna=m3 2006.259.08:27:17.14#flagr#flagr/antenna,new-source 2006.259.08:27:20.01:!+10m 2006.259.08:37:20.02:standby 2006.259.08:37:20.02&standby/"this is standby command. 2006.259.08:37:20.02&standby/antenna=m0 2006.259.08:37:21.01:checkk5hdd 2006.259.08:37:21.01&checkk5hdd/chk_hdd=1 2006.259.08:37:21.01&checkk5hdd/chk_hdd=2 2006.259.08:37:21.01&checkk5hdd/chk_hdd=3 2006.259.08:37:21.01&checkk5hdd/chk_hdd=4 2006.259.08:37:24.40/chk_hdd//k5ts1/GSI00275:T259073000a.dat~T259082610a.dat[13129351168Byte] 2006.259.08:37:27.84/chk_hdd//k5ts2/GSI00163:T259073000b.dat~T259082610b.dat[13129351168Byte] 2006.259.08:37:31.29/chk_hdd//k5ts3/GSI00278:T259073000c.dat~T259082610c.dat[13129351168Byte] 2006.259.08:37:35.01/chk_hdd//k5ts4/GSI00141:T259073000d.dat~T259082610d.dat[13129351168Byte] 2006.259.08:37:35.01:sy=cp /usr2/log/k06259ts.log /usr2/log_backup/ 2006.259.08:37:35.10:log=k06260ts