2006.252.08:37:41.39:Log Opened: Mark IV Field System Version 9.7.7 2006.252.08:37:41.39:location,TSUKUB32,-140.09,36.10,61.0 2006.252.08:37:41.39:horizon1,0.,5.,360. 2006.252.08:37:41.40:antenna,32.0,180.0,180.0,10.0,710.0,5.0,88.0,azel 2006.252.08:37:41.40:equip,k42c/mk4,vlbab,vlbab,mk4,500.10,3,a/d,101,60,20,none,41,1,in,8bit,cdp,3 2006.252.08:37:41.40:drivev11,330,270,no 2006.252.08:37:41.41:drivev12,mvme117,0,11.400,2548.000,152.780,-6.655,0.014,152,10.000,54500 2006.252.08:37:41.41:drivev13,15.000,268,10.000,10.000,10.000 2006.252.08:37:41.41:drivev21,330,270,no 2006.252.08:37:41.42:drivev22,mvme117,0,11.500,2821.000,127.500,-8.640,0.015,152,14.000,54500 2006.252.08:37:41.42:drivev23,15.000,268,10.000,10.000,10.000 2006.252.08:37:41.47:head10,all,all,all,odd,adaptive,no,5.0000,1 2006.252.08:37:41.47:head11,131.5,16.4,-291.0,131.5,16.4,0.8,168.30,168.30 2006.252.08:37:41.47:head12,122.8,13.9,-150.8,122.8,14.7,2.5,167.61,167.61 2006.252.08:37:41.48:head20,all,all,all,odd,adaptive,no,5.0000,1 2006.252.08:37:41.48:head21,145.3,16.1,-209.3,137.2,16.1,58.9,165.28,165.28 2006.252.08:37:41.48:head22,157.5,17.4,-203.7,149.2,16.6,56.5,169.73,169.73 2006.252.08:37:41.49:time,-0.364,101.533,rate 2006.252.08:37:41.49:flagr,200 2006.252.08:37:41.49:proc=k06253ts 2006.252.08:37:41.50:" k06253 2006 tsukub32 t ts 2006.252.08:37:41.50:" t tsukub32 azel .0000 180.0 14 10.0 710.0 180.0 14 5.0 88.0 32.0 ts 108 2006.252.08:37:41.51:" ts tsukub32 -3957408.75120 3310229.34660 3737494.83600 73452301 2006.252.08:37:41.55:" 108 tsukub32 14 17400 2006.252.08:37:41.56:" drudg version 050216 compiled under fs 9.7.07 2006.252.08:37:41.56:" rack=k4-2/m4 recorder 1=k5 recorder 2=none 2006.252.08:37:41.56:!2006.253.06:29:50 2006.253.06:29:50.00:sy=/usr2/oper/k5/bin/freeze_chk.pl & 2006.253.06:29:50.02:!2006.253.07:19:50 2006.253.07:19:50.00:unstow 2006.253.07:19:50.00&unstow/antenna=e 2006.253.07:19:50.00&unstow/!+10s 2006.253.07:19:50.00&unstow/antenna=m2 2006.253.07:20:02.01:scan_name=253-0730,k06253,60 2006.253.07:20:02.01:source=1128+385,113053.28,381518.5,2000.0,ccw 2006.253.07:20:02.01#antcn#PM 1 00019 2005 228 00 22 31 00 2006.253.07:20:02.01#antcn#PM 2 90.0000 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 2006.253.07:20:02.01#antcn#PM 2 -0.0279715 0.0000000 -0.0282214 -0.0241630 -0.0014011 2006.253.07:20:02.01#antcn#PM 3 -0.0059899 0.0042895 -0.0643783 0.0000000 0.0000000 2006.253.07:20:02.01#antcn#PM 4 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.253.07:20:02.01#antcn#PM 5 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.253.07:20:03.14:ready_k5 2006.253.07:20:03.14&ready_k5/obsinfo=st 2006.253.07:20:03.14&ready_k5/autoobs=1 2006.253.07:20:03.14&ready_k5/autoobs=2 2006.253.07:20:03.14&ready_k5/autoobs=3 2006.253.07:20:03.14&ready_k5/autoobs=4 2006.253.07:20:03.14&ready_k5/obsinfo 2006.253.07:20:03.14/obsinfo=st/error_log.tmp was not found (or not removed). 2006.253.07:20:03.14#flagr#flagr/antenna,new-source 2006.253.07:20:06.34/autoobs//k5ts1/ autoobs started! 2006.253.07:20:09.47/autoobs//k5ts2/ autoobs started! 2006.253.07:20:12.59/autoobs//k5ts3/ autoobs started! 2006.253.07:20:15.73/autoobs//k5ts4/ autoobs started! 2006.253.07:20:15.76/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.253.07:20:15.76:4f8m12a=1 2006.253.07:20:15.76&4f8m12a/xlog=on 2006.253.07:20:15.76&4f8m12a/echo=on 2006.253.07:20:15.76&4f8m12a/pcalon 2006.253.07:20:15.76&4f8m12a/"tpicd=stop 2006.253.07:20:15.76&4f8m12a/vc4f8 2006.253.07:20:15.76&4f8m12a/ifd4f 2006.253.07:20:15.76&4f8m12a/"form=m,16.000,1:2 2006.253.07:20:15.76&4f8m12a/"tpicd 2006.253.07:20:15.76&4f8m12a/echo=off 2006.253.07:20:15.76&4f8m12a/xlog=off 2006.253.07:20:15.76$4f8m12a/echo=on 2006.253.07:20:15.76$4f8m12a/pcalon 2006.253.07:20:15.76&pcalon/"no phase cal control is implemented here 2006.253.07:20:15.76$pcalon/"no phase cal control is implemented here 2006.253.07:20:15.76$4f8m12a/"tpicd=stop 2006.253.07:20:15.76$4f8m12a/vc4f8 2006.253.07:20:15.76&vc4f8/valo=1,532.99 2006.253.07:20:15.76&vc4f8/va=1,8 2006.253.07:20:15.76&vc4f8/valo=2,572.99 2006.253.07:20:15.76&vc4f8/va=2,7 2006.253.07:20:15.76&vc4f8/valo=3,672.99 2006.253.07:20:15.76&vc4f8/va=3,6 2006.253.07:20:15.76&vc4f8/valo=4,832.99 2006.253.07:20:15.76&vc4f8/va=4,7 2006.253.07:20:15.76&vc4f8/valo=5,652.99 2006.253.07:20:15.76&vc4f8/va=5,7 2006.253.07:20:15.76&vc4f8/valo=6,772.99 2006.253.07:20:15.76&vc4f8/va=6,7 2006.253.07:20:15.76&vc4f8/valo=7,832.99 2006.253.07:20:15.76&vc4f8/va=7,7 2006.253.07:20:15.76&vc4f8/valo=8,852.99 2006.253.07:20:15.76&vc4f8/va=8,7 2006.253.07:20:15.76&vc4f8/vblo=1,632.99 2006.253.07:20:15.76&vc4f8/vb=1,4 2006.253.07:20:15.76&vc4f8/vblo=2,640.99 2006.253.07:20:15.76&vc4f8/vb=2,5 2006.253.07:20:15.76&vc4f8/vblo=3,656.99 2006.253.07:20:15.76&vc4f8/vb=3,4 2006.253.07:20:15.76&vc4f8/vblo=4,712.99 2006.253.07:20:15.76&vc4f8/vb=4,4 2006.253.07:20:15.76&vc4f8/vblo=5,744.99 2006.253.07:20:15.76&vc4f8/vb=5,4 2006.253.07:20:15.76&vc4f8/vblo=6,752.99 2006.253.07:20:15.76&vc4f8/vb=6,4 2006.253.07:20:15.76&vc4f8/vabw=wide 2006.253.07:20:15.76&vc4f8/vbbw=wide 2006.253.07:20:15.76$vc4f8/valo=1,532.99 2006.253.07:20:15.76#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.253.07:20:15.76#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.253.07:20:15.76#ibcon#ireg 17 cls_cnt 0 2006.253.07:20:15.76#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.253.07:20:15.76#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.253.07:20:15.76#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.253.07:20:15.76#ibcon#enter wrdev, iclass 24, count 0 2006.253.07:20:15.76#ibcon#first serial, iclass 24, count 0 2006.253.07:20:15.76#ibcon#enter sib2, iclass 24, count 0 2006.253.07:20:15.76#ibcon#flushed, iclass 24, count 0 2006.253.07:20:15.76#ibcon#about to write, iclass 24, count 0 2006.253.07:20:15.76#ibcon#wrote, iclass 24, count 0 2006.253.07:20:15.76#ibcon#about to read 3, iclass 24, count 0 2006.253.07:20:15.80#ibcon#read 3, iclass 24, count 0 2006.253.07:20:15.80#ibcon#about to read 4, iclass 24, count 0 2006.253.07:20:15.80#ibcon#read 4, iclass 24, count 0 2006.253.07:20:15.80#ibcon#about to read 5, iclass 24, count 0 2006.253.07:20:15.80#ibcon#read 5, iclass 24, count 0 2006.253.07:20:15.80#ibcon#about to read 6, iclass 24, count 0 2006.253.07:20:15.80#ibcon#read 6, iclass 24, count 0 2006.253.07:20:15.80#ibcon#end of sib2, iclass 24, count 0 2006.253.07:20:15.80#ibcon#*mode == 0, iclass 24, count 0 2006.253.07:20:15.80#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.253.07:20:15.80#ibcon#[26=FRQ=01,532.99\r\n] 2006.253.07:20:15.80#ibcon#*before write, iclass 24, count 0 2006.253.07:20:15.80#ibcon#enter sib2, iclass 24, count 0 2006.253.07:20:15.80#ibcon#flushed, iclass 24, count 0 2006.253.07:20:15.80#ibcon#about to write, iclass 24, count 0 2006.253.07:20:15.80#ibcon#wrote, iclass 24, count 0 2006.253.07:20:15.80#ibcon#about to read 3, iclass 24, count 0 2006.253.07:20:15.84#ibcon#read 3, iclass 24, count 0 2006.253.07:20:15.84#ibcon#about to read 4, iclass 24, count 0 2006.253.07:20:15.84#ibcon#read 4, iclass 24, count 0 2006.253.07:20:15.84#ibcon#about to read 5, iclass 24, count 0 2006.253.07:20:15.84#ibcon#read 5, iclass 24, count 0 2006.253.07:20:15.84#ibcon#about to read 6, iclass 24, count 0 2006.253.07:20:15.84#ibcon#read 6, iclass 24, count 0 2006.253.07:20:15.84#ibcon#end of sib2, iclass 24, count 0 2006.253.07:20:15.84#ibcon#*after write, iclass 24, count 0 2006.253.07:20:15.84#ibcon#*before return 0, iclass 24, count 0 2006.253.07:20:15.84#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.253.07:20:15.84#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.253.07:20:15.84#ibcon#about to clear, iclass 24 cls_cnt 0 2006.253.07:20:15.84#ibcon#cleared, iclass 24 cls_cnt 0 2006.253.07:20:15.84$vc4f8/va=1,8 2006.253.07:20:15.84#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.253.07:20:15.84#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.253.07:20:15.84#ibcon#ireg 11 cls_cnt 2 2006.253.07:20:15.84#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.253.07:20:15.84#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.253.07:20:15.84#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.253.07:20:15.84#ibcon#enter wrdev, iclass 26, count 2 2006.253.07:20:15.84#ibcon#first serial, iclass 26, count 2 2006.253.07:20:15.84#ibcon#enter sib2, iclass 26, count 2 2006.253.07:20:15.84#ibcon#flushed, iclass 26, count 2 2006.253.07:20:15.84#ibcon#about to write, iclass 26, count 2 2006.253.07:20:15.84#ibcon#wrote, iclass 26, count 2 2006.253.07:20:15.84#ibcon#about to read 3, iclass 26, count 2 2006.253.07:20:15.86#ibcon#read 3, iclass 26, count 2 2006.253.07:20:15.86#ibcon#about to read 4, iclass 26, count 2 2006.253.07:20:15.86#ibcon#read 4, iclass 26, count 2 2006.253.07:20:15.86#ibcon#about to read 5, iclass 26, count 2 2006.253.07:20:15.86#ibcon#read 5, iclass 26, count 2 2006.253.07:20:15.86#ibcon#about to read 6, iclass 26, count 2 2006.253.07:20:15.86#ibcon#read 6, iclass 26, count 2 2006.253.07:20:15.86#ibcon#end of sib2, iclass 26, count 2 2006.253.07:20:15.86#ibcon#*mode == 0, iclass 26, count 2 2006.253.07:20:15.86#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.253.07:20:15.86#ibcon#[25=AT01-08\r\n] 2006.253.07:20:15.86#ibcon#*before write, iclass 26, count 2 2006.253.07:20:15.86#ibcon#enter sib2, iclass 26, count 2 2006.253.07:20:15.86#ibcon#flushed, iclass 26, count 2 2006.253.07:20:15.86#ibcon#about to write, iclass 26, count 2 2006.253.07:20:15.86#ibcon#wrote, iclass 26, count 2 2006.253.07:20:15.86#ibcon#about to read 3, iclass 26, count 2 2006.253.07:20:15.89#ibcon#read 3, iclass 26, count 2 2006.253.07:20:15.89#ibcon#about to read 4, iclass 26, count 2 2006.253.07:20:15.89#ibcon#read 4, iclass 26, count 2 2006.253.07:20:15.89#ibcon#about to read 5, iclass 26, count 2 2006.253.07:20:15.89#ibcon#read 5, iclass 26, count 2 2006.253.07:20:15.89#ibcon#about to read 6, iclass 26, count 2 2006.253.07:20:15.89#ibcon#read 6, iclass 26, count 2 2006.253.07:20:15.89#ibcon#end of sib2, iclass 26, count 2 2006.253.07:20:15.89#ibcon#*after write, iclass 26, count 2 2006.253.07:20:15.89#ibcon#*before return 0, iclass 26, count 2 2006.253.07:20:15.89#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.253.07:20:15.89#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.253.07:20:15.89#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.253.07:20:15.89#ibcon#ireg 7 cls_cnt 0 2006.253.07:20:15.89#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.253.07:20:16.01#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.253.07:20:16.01#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.253.07:20:16.01#ibcon#enter wrdev, iclass 26, count 0 2006.253.07:20:16.01#ibcon#first serial, iclass 26, count 0 2006.253.07:20:16.01#ibcon#enter sib2, iclass 26, count 0 2006.253.07:20:16.01#ibcon#flushed, iclass 26, count 0 2006.253.07:20:16.01#ibcon#about to write, iclass 26, count 0 2006.253.07:20:16.01#ibcon#wrote, iclass 26, count 0 2006.253.07:20:16.01#ibcon#about to read 3, iclass 26, count 0 2006.253.07:20:16.03#ibcon#read 3, iclass 26, count 0 2006.253.07:20:16.03#ibcon#about to read 4, iclass 26, count 0 2006.253.07:20:16.03#ibcon#read 4, iclass 26, count 0 2006.253.07:20:16.03#ibcon#about to read 5, iclass 26, count 0 2006.253.07:20:16.03#ibcon#read 5, iclass 26, count 0 2006.253.07:20:16.03#ibcon#about to read 6, iclass 26, count 0 2006.253.07:20:16.03#ibcon#read 6, iclass 26, count 0 2006.253.07:20:16.03#ibcon#end of sib2, iclass 26, count 0 2006.253.07:20:16.03#ibcon#*mode == 0, iclass 26, count 0 2006.253.07:20:16.03#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.253.07:20:16.03#ibcon#[25=USB\r\n] 2006.253.07:20:16.03#ibcon#*before write, iclass 26, count 0 2006.253.07:20:16.03#ibcon#enter sib2, iclass 26, count 0 2006.253.07:20:16.03#ibcon#flushed, iclass 26, count 0 2006.253.07:20:16.03#ibcon#about to write, iclass 26, count 0 2006.253.07:20:16.03#ibcon#wrote, iclass 26, count 0 2006.253.07:20:16.03#ibcon#about to read 3, iclass 26, count 0 2006.253.07:20:16.06#ibcon#read 3, iclass 26, count 0 2006.253.07:20:16.06#ibcon#about to read 4, iclass 26, count 0 2006.253.07:20:16.06#ibcon#read 4, iclass 26, count 0 2006.253.07:20:16.06#ibcon#about to read 5, iclass 26, count 0 2006.253.07:20:16.06#ibcon#read 5, iclass 26, count 0 2006.253.07:20:16.06#ibcon#about to read 6, iclass 26, count 0 2006.253.07:20:16.06#ibcon#read 6, iclass 26, count 0 2006.253.07:20:16.06#ibcon#end of sib2, iclass 26, count 0 2006.253.07:20:16.06#ibcon#*after write, iclass 26, count 0 2006.253.07:20:16.06#ibcon#*before return 0, iclass 26, count 0 2006.253.07:20:16.06#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.253.07:20:16.06#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.253.07:20:16.06#ibcon#about to clear, iclass 26 cls_cnt 0 2006.253.07:20:16.06#ibcon#cleared, iclass 26 cls_cnt 0 2006.253.07:20:16.06$vc4f8/valo=2,572.99 2006.253.07:20:16.06#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.253.07:20:16.06#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.253.07:20:16.06#ibcon#ireg 17 cls_cnt 0 2006.253.07:20:16.06#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.253.07:20:16.06#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.253.07:20:16.06#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.253.07:20:16.06#ibcon#enter wrdev, iclass 28, count 0 2006.253.07:20:16.06#ibcon#first serial, iclass 28, count 0 2006.253.07:20:16.06#ibcon#enter sib2, iclass 28, count 0 2006.253.07:20:16.06#ibcon#flushed, iclass 28, count 0 2006.253.07:20:16.06#ibcon#about to write, iclass 28, count 0 2006.253.07:20:16.06#ibcon#wrote, iclass 28, count 0 2006.253.07:20:16.06#ibcon#about to read 3, iclass 28, count 0 2006.253.07:20:16.09#ibcon#read 3, iclass 28, count 0 2006.253.07:20:16.09#ibcon#about to read 4, iclass 28, count 0 2006.253.07:20:16.09#ibcon#read 4, iclass 28, count 0 2006.253.07:20:16.09#ibcon#about to read 5, iclass 28, count 0 2006.253.07:20:16.09#ibcon#read 5, iclass 28, count 0 2006.253.07:20:16.09#ibcon#about to read 6, iclass 28, count 0 2006.253.07:20:16.09#ibcon#read 6, iclass 28, count 0 2006.253.07:20:16.09#ibcon#end of sib2, iclass 28, count 0 2006.253.07:20:16.09#ibcon#*mode == 0, iclass 28, count 0 2006.253.07:20:16.09#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.253.07:20:16.09#ibcon#[26=FRQ=02,572.99\r\n] 2006.253.07:20:16.09#ibcon#*before write, iclass 28, count 0 2006.253.07:20:16.09#ibcon#enter sib2, iclass 28, count 0 2006.253.07:20:16.09#ibcon#flushed, iclass 28, count 0 2006.253.07:20:16.09#ibcon#about to write, iclass 28, count 0 2006.253.07:20:16.09#ibcon#wrote, iclass 28, count 0 2006.253.07:20:16.09#ibcon#about to read 3, iclass 28, count 0 2006.253.07:20:16.13#ibcon#read 3, iclass 28, count 0 2006.253.07:20:16.13#ibcon#about to read 4, iclass 28, count 0 2006.253.07:20:16.13#ibcon#read 4, iclass 28, count 0 2006.253.07:20:16.13#ibcon#about to read 5, iclass 28, count 0 2006.253.07:20:16.13#ibcon#read 5, iclass 28, count 0 2006.253.07:20:16.13#ibcon#about to read 6, iclass 28, count 0 2006.253.07:20:16.13#ibcon#read 6, iclass 28, count 0 2006.253.07:20:16.13#ibcon#end of sib2, iclass 28, count 0 2006.253.07:20:16.13#ibcon#*after write, iclass 28, count 0 2006.253.07:20:16.13#ibcon#*before return 0, iclass 28, count 0 2006.253.07:20:16.13#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.253.07:20:16.13#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.253.07:20:16.13#ibcon#about to clear, iclass 28 cls_cnt 0 2006.253.07:20:16.13#ibcon#cleared, iclass 28 cls_cnt 0 2006.253.07:20:16.13$vc4f8/va=2,7 2006.253.07:20:16.13#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.253.07:20:16.13#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.253.07:20:16.13#ibcon#ireg 11 cls_cnt 2 2006.253.07:20:16.13#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.253.07:20:16.18#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.253.07:20:16.18#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.253.07:20:16.18#ibcon#enter wrdev, iclass 30, count 2 2006.253.07:20:16.18#ibcon#first serial, iclass 30, count 2 2006.253.07:20:16.18#ibcon#enter sib2, iclass 30, count 2 2006.253.07:20:16.18#ibcon#flushed, iclass 30, count 2 2006.253.07:20:16.18#ibcon#about to write, iclass 30, count 2 2006.253.07:20:16.18#ibcon#wrote, iclass 30, count 2 2006.253.07:20:16.18#ibcon#about to read 3, iclass 30, count 2 2006.253.07:20:16.20#ibcon#read 3, iclass 30, count 2 2006.253.07:20:16.20#ibcon#about to read 4, iclass 30, count 2 2006.253.07:20:16.20#ibcon#read 4, iclass 30, count 2 2006.253.07:20:16.20#ibcon#about to read 5, iclass 30, count 2 2006.253.07:20:16.20#ibcon#read 5, iclass 30, count 2 2006.253.07:20:16.20#ibcon#about to read 6, iclass 30, count 2 2006.253.07:20:16.20#ibcon#read 6, iclass 30, count 2 2006.253.07:20:16.20#ibcon#end of sib2, iclass 30, count 2 2006.253.07:20:16.20#ibcon#*mode == 0, iclass 30, count 2 2006.253.07:20:16.20#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.253.07:20:16.20#ibcon#[25=AT02-07\r\n] 2006.253.07:20:16.20#ibcon#*before write, iclass 30, count 2 2006.253.07:20:16.20#ibcon#enter sib2, iclass 30, count 2 2006.253.07:20:16.20#ibcon#flushed, iclass 30, count 2 2006.253.07:20:16.20#ibcon#about to write, iclass 30, count 2 2006.253.07:20:16.20#ibcon#wrote, iclass 30, count 2 2006.253.07:20:16.20#ibcon#about to read 3, iclass 30, count 2 2006.253.07:20:16.23#ibcon#read 3, iclass 30, count 2 2006.253.07:20:16.23#ibcon#about to read 4, iclass 30, count 2 2006.253.07:20:16.23#ibcon#read 4, iclass 30, count 2 2006.253.07:20:16.23#ibcon#about to read 5, iclass 30, count 2 2006.253.07:20:16.23#ibcon#read 5, iclass 30, count 2 2006.253.07:20:16.23#ibcon#about to read 6, iclass 30, count 2 2006.253.07:20:16.23#ibcon#read 6, iclass 30, count 2 2006.253.07:20:16.23#ibcon#end of sib2, iclass 30, count 2 2006.253.07:20:16.23#ibcon#*after write, iclass 30, count 2 2006.253.07:20:16.23#ibcon#*before return 0, iclass 30, count 2 2006.253.07:20:16.23#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.253.07:20:16.23#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.253.07:20:16.23#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.253.07:20:16.23#ibcon#ireg 7 cls_cnt 0 2006.253.07:20:16.23#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.253.07:20:16.35#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.253.07:20:16.35#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.253.07:20:16.35#ibcon#enter wrdev, iclass 30, count 0 2006.253.07:20:16.35#ibcon#first serial, iclass 30, count 0 2006.253.07:20:16.35#ibcon#enter sib2, iclass 30, count 0 2006.253.07:20:16.35#ibcon#flushed, iclass 30, count 0 2006.253.07:20:16.35#ibcon#about to write, iclass 30, count 0 2006.253.07:20:16.35#ibcon#wrote, iclass 30, count 0 2006.253.07:20:16.35#ibcon#about to read 3, iclass 30, count 0 2006.253.07:20:16.37#ibcon#read 3, iclass 30, count 0 2006.253.07:20:16.37#ibcon#about to read 4, iclass 30, count 0 2006.253.07:20:16.37#ibcon#read 4, iclass 30, count 0 2006.253.07:20:16.37#ibcon#about to read 5, iclass 30, count 0 2006.253.07:20:16.37#ibcon#read 5, iclass 30, count 0 2006.253.07:20:16.37#ibcon#about to read 6, iclass 30, count 0 2006.253.07:20:16.37#ibcon#read 6, iclass 30, count 0 2006.253.07:20:16.37#ibcon#end of sib2, iclass 30, count 0 2006.253.07:20:16.37#ibcon#*mode == 0, iclass 30, count 0 2006.253.07:20:16.37#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.253.07:20:16.37#ibcon#[25=USB\r\n] 2006.253.07:20:16.37#ibcon#*before write, iclass 30, count 0 2006.253.07:20:16.37#ibcon#enter sib2, iclass 30, count 0 2006.253.07:20:16.37#ibcon#flushed, iclass 30, count 0 2006.253.07:20:16.37#ibcon#about to write, iclass 30, count 0 2006.253.07:20:16.37#ibcon#wrote, iclass 30, count 0 2006.253.07:20:16.37#ibcon#about to read 3, iclass 30, count 0 2006.253.07:20:16.40#ibcon#read 3, iclass 30, count 0 2006.253.07:20:16.40#ibcon#about to read 4, iclass 30, count 0 2006.253.07:20:16.40#ibcon#read 4, iclass 30, count 0 2006.253.07:20:16.40#ibcon#about to read 5, iclass 30, count 0 2006.253.07:20:16.40#ibcon#read 5, iclass 30, count 0 2006.253.07:20:16.40#ibcon#about to read 6, iclass 30, count 0 2006.253.07:20:16.40#ibcon#read 6, iclass 30, count 0 2006.253.07:20:16.40#ibcon#end of sib2, iclass 30, count 0 2006.253.07:20:16.40#ibcon#*after write, iclass 30, count 0 2006.253.07:20:16.40#ibcon#*before return 0, iclass 30, count 0 2006.253.07:20:16.40#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.253.07:20:16.40#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.253.07:20:16.40#ibcon#about to clear, iclass 30 cls_cnt 0 2006.253.07:20:16.40#ibcon#cleared, iclass 30 cls_cnt 0 2006.253.07:20:16.40$vc4f8/valo=3,672.99 2006.253.07:20:16.40#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.253.07:20:16.40#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.253.07:20:16.40#ibcon#ireg 17 cls_cnt 0 2006.253.07:20:16.40#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.253.07:20:16.40#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.253.07:20:16.40#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.253.07:20:16.40#ibcon#enter wrdev, iclass 32, count 0 2006.253.07:20:16.40#ibcon#first serial, iclass 32, count 0 2006.253.07:20:16.40#ibcon#enter sib2, iclass 32, count 0 2006.253.07:20:16.40#ibcon#flushed, iclass 32, count 0 2006.253.07:20:16.40#ibcon#about to write, iclass 32, count 0 2006.253.07:20:16.40#ibcon#wrote, iclass 32, count 0 2006.253.07:20:16.40#ibcon#about to read 3, iclass 32, count 0 2006.253.07:20:16.43#ibcon#read 3, iclass 32, count 0 2006.253.07:20:16.43#ibcon#about to read 4, iclass 32, count 0 2006.253.07:20:16.43#ibcon#read 4, iclass 32, count 0 2006.253.07:20:16.43#ibcon#about to read 5, iclass 32, count 0 2006.253.07:20:16.43#ibcon#read 5, iclass 32, count 0 2006.253.07:20:16.43#ibcon#about to read 6, iclass 32, count 0 2006.253.07:20:16.43#ibcon#read 6, iclass 32, count 0 2006.253.07:20:16.43#ibcon#end of sib2, iclass 32, count 0 2006.253.07:20:16.43#ibcon#*mode == 0, iclass 32, count 0 2006.253.07:20:16.43#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.253.07:20:16.43#ibcon#[26=FRQ=03,672.99\r\n] 2006.253.07:20:16.43#ibcon#*before write, iclass 32, count 0 2006.253.07:20:16.43#ibcon#enter sib2, iclass 32, count 0 2006.253.07:20:16.43#ibcon#flushed, iclass 32, count 0 2006.253.07:20:16.43#ibcon#about to write, iclass 32, count 0 2006.253.07:20:16.43#ibcon#wrote, iclass 32, count 0 2006.253.07:20:16.43#ibcon#about to read 3, iclass 32, count 0 2006.253.07:20:16.47#ibcon#read 3, iclass 32, count 0 2006.253.07:20:16.47#ibcon#about to read 4, iclass 32, count 0 2006.253.07:20:16.47#ibcon#read 4, iclass 32, count 0 2006.253.07:20:16.47#ibcon#about to read 5, iclass 32, count 0 2006.253.07:20:16.47#ibcon#read 5, iclass 32, count 0 2006.253.07:20:16.47#ibcon#about to read 6, iclass 32, count 0 2006.253.07:20:16.47#ibcon#read 6, iclass 32, count 0 2006.253.07:20:16.47#ibcon#end of sib2, iclass 32, count 0 2006.253.07:20:16.47#ibcon#*after write, iclass 32, count 0 2006.253.07:20:16.47#ibcon#*before return 0, iclass 32, count 0 2006.253.07:20:16.47#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.253.07:20:16.47#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.253.07:20:16.47#ibcon#about to clear, iclass 32 cls_cnt 0 2006.253.07:20:16.47#ibcon#cleared, iclass 32 cls_cnt 0 2006.253.07:20:16.47$vc4f8/va=3,6 2006.253.07:20:16.47#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.253.07:20:16.47#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.253.07:20:16.47#ibcon#ireg 11 cls_cnt 2 2006.253.07:20:16.47#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.253.07:20:16.52#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.253.07:20:16.52#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.253.07:20:16.52#ibcon#enter wrdev, iclass 34, count 2 2006.253.07:20:16.52#ibcon#first serial, iclass 34, count 2 2006.253.07:20:16.52#ibcon#enter sib2, iclass 34, count 2 2006.253.07:20:16.52#ibcon#flushed, iclass 34, count 2 2006.253.07:20:16.52#ibcon#about to write, iclass 34, count 2 2006.253.07:20:16.52#ibcon#wrote, iclass 34, count 2 2006.253.07:20:16.52#ibcon#about to read 3, iclass 34, count 2 2006.253.07:20:16.54#ibcon#read 3, iclass 34, count 2 2006.253.07:20:16.54#ibcon#about to read 4, iclass 34, count 2 2006.253.07:20:16.54#ibcon#read 4, iclass 34, count 2 2006.253.07:20:16.54#ibcon#about to read 5, iclass 34, count 2 2006.253.07:20:16.54#ibcon#read 5, iclass 34, count 2 2006.253.07:20:16.54#ibcon#about to read 6, iclass 34, count 2 2006.253.07:20:16.54#ibcon#read 6, iclass 34, count 2 2006.253.07:20:16.54#ibcon#end of sib2, iclass 34, count 2 2006.253.07:20:16.54#ibcon#*mode == 0, iclass 34, count 2 2006.253.07:20:16.54#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.253.07:20:16.54#ibcon#[25=AT03-06\r\n] 2006.253.07:20:16.54#ibcon#*before write, iclass 34, count 2 2006.253.07:20:16.54#ibcon#enter sib2, iclass 34, count 2 2006.253.07:20:16.54#ibcon#flushed, iclass 34, count 2 2006.253.07:20:16.54#ibcon#about to write, iclass 34, count 2 2006.253.07:20:16.54#ibcon#wrote, iclass 34, count 2 2006.253.07:20:16.54#ibcon#about to read 3, iclass 34, count 2 2006.253.07:20:16.57#ibcon#read 3, iclass 34, count 2 2006.253.07:20:16.57#ibcon#about to read 4, iclass 34, count 2 2006.253.07:20:16.57#ibcon#read 4, iclass 34, count 2 2006.253.07:20:16.57#ibcon#about to read 5, iclass 34, count 2 2006.253.07:20:16.57#ibcon#read 5, iclass 34, count 2 2006.253.07:20:16.57#ibcon#about to read 6, iclass 34, count 2 2006.253.07:20:16.57#ibcon#read 6, iclass 34, count 2 2006.253.07:20:16.57#ibcon#end of sib2, iclass 34, count 2 2006.253.07:20:16.57#ibcon#*after write, iclass 34, count 2 2006.253.07:20:16.57#ibcon#*before return 0, iclass 34, count 2 2006.253.07:20:16.57#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.253.07:20:16.57#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.253.07:20:16.57#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.253.07:20:16.57#ibcon#ireg 7 cls_cnt 0 2006.253.07:20:16.57#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.253.07:20:16.69#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.253.07:20:16.69#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.253.07:20:16.69#ibcon#enter wrdev, iclass 34, count 0 2006.253.07:20:16.69#ibcon#first serial, iclass 34, count 0 2006.253.07:20:16.69#ibcon#enter sib2, iclass 34, count 0 2006.253.07:20:16.69#ibcon#flushed, iclass 34, count 0 2006.253.07:20:16.69#ibcon#about to write, iclass 34, count 0 2006.253.07:20:16.69#ibcon#wrote, iclass 34, count 0 2006.253.07:20:16.69#ibcon#about to read 3, iclass 34, count 0 2006.253.07:20:16.71#ibcon#read 3, iclass 34, count 0 2006.253.07:20:16.71#ibcon#about to read 4, iclass 34, count 0 2006.253.07:20:16.71#ibcon#read 4, iclass 34, count 0 2006.253.07:20:16.71#ibcon#about to read 5, iclass 34, count 0 2006.253.07:20:16.71#ibcon#read 5, iclass 34, count 0 2006.253.07:20:16.71#ibcon#about to read 6, iclass 34, count 0 2006.253.07:20:16.71#ibcon#read 6, iclass 34, count 0 2006.253.07:20:16.71#ibcon#end of sib2, iclass 34, count 0 2006.253.07:20:16.71#ibcon#*mode == 0, iclass 34, count 0 2006.253.07:20:16.71#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.253.07:20:16.71#ibcon#[25=USB\r\n] 2006.253.07:20:16.71#ibcon#*before write, iclass 34, count 0 2006.253.07:20:16.71#ibcon#enter sib2, iclass 34, count 0 2006.253.07:20:16.71#ibcon#flushed, iclass 34, count 0 2006.253.07:20:16.71#ibcon#about to write, iclass 34, count 0 2006.253.07:20:16.71#ibcon#wrote, iclass 34, count 0 2006.253.07:20:16.71#ibcon#about to read 3, iclass 34, count 0 2006.253.07:20:16.74#ibcon#read 3, iclass 34, count 0 2006.253.07:20:16.74#ibcon#about to read 4, iclass 34, count 0 2006.253.07:20:16.74#ibcon#read 4, iclass 34, count 0 2006.253.07:20:16.74#ibcon#about to read 5, iclass 34, count 0 2006.253.07:20:16.74#ibcon#read 5, iclass 34, count 0 2006.253.07:20:16.74#ibcon#about to read 6, iclass 34, count 0 2006.253.07:20:16.74#ibcon#read 6, iclass 34, count 0 2006.253.07:20:16.74#ibcon#end of sib2, iclass 34, count 0 2006.253.07:20:16.74#ibcon#*after write, iclass 34, count 0 2006.253.07:20:16.74#ibcon#*before return 0, iclass 34, count 0 2006.253.07:20:16.74#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.253.07:20:16.74#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.253.07:20:16.74#ibcon#about to clear, iclass 34 cls_cnt 0 2006.253.07:20:16.74#ibcon#cleared, iclass 34 cls_cnt 0 2006.253.07:20:16.74$vc4f8/valo=4,832.99 2006.253.07:20:16.74#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.253.07:20:16.74#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.253.07:20:16.74#ibcon#ireg 17 cls_cnt 0 2006.253.07:20:16.74#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.253.07:20:16.74#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.253.07:20:16.74#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.253.07:20:16.74#ibcon#enter wrdev, iclass 36, count 0 2006.253.07:20:16.74#ibcon#first serial, iclass 36, count 0 2006.253.07:20:16.74#ibcon#enter sib2, iclass 36, count 0 2006.253.07:20:16.74#ibcon#flushed, iclass 36, count 0 2006.253.07:20:16.74#ibcon#about to write, iclass 36, count 0 2006.253.07:20:16.74#ibcon#wrote, iclass 36, count 0 2006.253.07:20:16.74#ibcon#about to read 3, iclass 36, count 0 2006.253.07:20:16.77#ibcon#read 3, iclass 36, count 0 2006.253.07:20:16.77#ibcon#about to read 4, iclass 36, count 0 2006.253.07:20:16.77#ibcon#read 4, iclass 36, count 0 2006.253.07:20:16.77#ibcon#about to read 5, iclass 36, count 0 2006.253.07:20:16.77#ibcon#read 5, iclass 36, count 0 2006.253.07:20:16.77#ibcon#about to read 6, iclass 36, count 0 2006.253.07:20:16.77#ibcon#read 6, iclass 36, count 0 2006.253.07:20:16.77#ibcon#end of sib2, iclass 36, count 0 2006.253.07:20:16.77#ibcon#*mode == 0, iclass 36, count 0 2006.253.07:20:16.77#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.253.07:20:16.77#ibcon#[26=FRQ=04,832.99\r\n] 2006.253.07:20:16.77#ibcon#*before write, iclass 36, count 0 2006.253.07:20:16.77#ibcon#enter sib2, iclass 36, count 0 2006.253.07:20:16.77#ibcon#flushed, iclass 36, count 0 2006.253.07:20:16.77#ibcon#about to write, iclass 36, count 0 2006.253.07:20:16.77#ibcon#wrote, iclass 36, count 0 2006.253.07:20:16.77#ibcon#about to read 3, iclass 36, count 0 2006.253.07:20:16.81#ibcon#read 3, iclass 36, count 0 2006.253.07:20:16.81#ibcon#about to read 4, iclass 36, count 0 2006.253.07:20:16.81#ibcon#read 4, iclass 36, count 0 2006.253.07:20:16.81#ibcon#about to read 5, iclass 36, count 0 2006.253.07:20:16.81#ibcon#read 5, iclass 36, count 0 2006.253.07:20:16.81#ibcon#about to read 6, iclass 36, count 0 2006.253.07:20:16.81#ibcon#read 6, iclass 36, count 0 2006.253.07:20:16.81#ibcon#end of sib2, iclass 36, count 0 2006.253.07:20:16.81#ibcon#*after write, iclass 36, count 0 2006.253.07:20:16.81#ibcon#*before return 0, iclass 36, count 0 2006.253.07:20:16.81#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.253.07:20:16.81#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.253.07:20:16.81#ibcon#about to clear, iclass 36 cls_cnt 0 2006.253.07:20:16.81#ibcon#cleared, iclass 36 cls_cnt 0 2006.253.07:20:16.81$vc4f8/va=4,7 2006.253.07:20:16.81#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.253.07:20:16.81#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.253.07:20:16.81#ibcon#ireg 11 cls_cnt 2 2006.253.07:20:16.81#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.253.07:20:16.86#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.253.07:20:16.86#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.253.07:20:16.86#ibcon#enter wrdev, iclass 38, count 2 2006.253.07:20:16.86#ibcon#first serial, iclass 38, count 2 2006.253.07:20:16.86#ibcon#enter sib2, iclass 38, count 2 2006.253.07:20:16.86#ibcon#flushed, iclass 38, count 2 2006.253.07:20:16.86#ibcon#about to write, iclass 38, count 2 2006.253.07:20:16.86#ibcon#wrote, iclass 38, count 2 2006.253.07:20:16.86#ibcon#about to read 3, iclass 38, count 2 2006.253.07:20:16.88#ibcon#read 3, iclass 38, count 2 2006.253.07:20:16.88#ibcon#about to read 4, iclass 38, count 2 2006.253.07:20:16.88#ibcon#read 4, iclass 38, count 2 2006.253.07:20:16.88#ibcon#about to read 5, iclass 38, count 2 2006.253.07:20:16.88#ibcon#read 5, iclass 38, count 2 2006.253.07:20:16.88#ibcon#about to read 6, iclass 38, count 2 2006.253.07:20:16.88#ibcon#read 6, iclass 38, count 2 2006.253.07:20:16.88#ibcon#end of sib2, iclass 38, count 2 2006.253.07:20:16.88#ibcon#*mode == 0, iclass 38, count 2 2006.253.07:20:16.88#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.253.07:20:16.88#ibcon#[25=AT04-07\r\n] 2006.253.07:20:16.88#ibcon#*before write, iclass 38, count 2 2006.253.07:20:16.88#ibcon#enter sib2, iclass 38, count 2 2006.253.07:20:16.88#ibcon#flushed, iclass 38, count 2 2006.253.07:20:16.88#ibcon#about to write, iclass 38, count 2 2006.253.07:20:16.88#ibcon#wrote, iclass 38, count 2 2006.253.07:20:16.88#ibcon#about to read 3, iclass 38, count 2 2006.253.07:20:16.91#ibcon#read 3, iclass 38, count 2 2006.253.07:20:16.91#ibcon#about to read 4, iclass 38, count 2 2006.253.07:20:16.91#ibcon#read 4, iclass 38, count 2 2006.253.07:20:16.91#ibcon#about to read 5, iclass 38, count 2 2006.253.07:20:16.91#ibcon#read 5, iclass 38, count 2 2006.253.07:20:16.91#ibcon#about to read 6, iclass 38, count 2 2006.253.07:20:16.91#ibcon#read 6, iclass 38, count 2 2006.253.07:20:16.91#ibcon#end of sib2, iclass 38, count 2 2006.253.07:20:16.91#ibcon#*after write, iclass 38, count 2 2006.253.07:20:16.91#ibcon#*before return 0, iclass 38, count 2 2006.253.07:20:16.91#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.253.07:20:16.91#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.253.07:20:16.91#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.253.07:20:16.91#ibcon#ireg 7 cls_cnt 0 2006.253.07:20:16.91#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.253.07:20:17.03#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.253.07:20:17.03#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.253.07:20:17.03#ibcon#enter wrdev, iclass 38, count 0 2006.253.07:20:17.03#ibcon#first serial, iclass 38, count 0 2006.253.07:20:17.03#ibcon#enter sib2, iclass 38, count 0 2006.253.07:20:17.03#ibcon#flushed, iclass 38, count 0 2006.253.07:20:17.03#ibcon#about to write, iclass 38, count 0 2006.253.07:20:17.03#ibcon#wrote, iclass 38, count 0 2006.253.07:20:17.03#ibcon#about to read 3, iclass 38, count 0 2006.253.07:20:17.05#ibcon#read 3, iclass 38, count 0 2006.253.07:20:17.05#ibcon#about to read 4, iclass 38, count 0 2006.253.07:20:17.05#ibcon#read 4, iclass 38, count 0 2006.253.07:20:17.05#ibcon#about to read 5, iclass 38, count 0 2006.253.07:20:17.05#ibcon#read 5, iclass 38, count 0 2006.253.07:20:17.05#ibcon#about to read 6, iclass 38, count 0 2006.253.07:20:17.05#ibcon#read 6, iclass 38, count 0 2006.253.07:20:17.05#ibcon#end of sib2, iclass 38, count 0 2006.253.07:20:17.05#ibcon#*mode == 0, iclass 38, count 0 2006.253.07:20:17.05#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.253.07:20:17.05#ibcon#[25=USB\r\n] 2006.253.07:20:17.05#ibcon#*before write, iclass 38, count 0 2006.253.07:20:17.05#ibcon#enter sib2, iclass 38, count 0 2006.253.07:20:17.05#ibcon#flushed, iclass 38, count 0 2006.253.07:20:17.05#ibcon#about to write, iclass 38, count 0 2006.253.07:20:17.05#ibcon#wrote, iclass 38, count 0 2006.253.07:20:17.05#ibcon#about to read 3, iclass 38, count 0 2006.253.07:20:17.08#ibcon#read 3, iclass 38, count 0 2006.253.07:20:17.08#ibcon#about to read 4, iclass 38, count 0 2006.253.07:20:17.08#ibcon#read 4, iclass 38, count 0 2006.253.07:20:17.08#ibcon#about to read 5, iclass 38, count 0 2006.253.07:20:17.08#ibcon#read 5, iclass 38, count 0 2006.253.07:20:17.08#ibcon#about to read 6, iclass 38, count 0 2006.253.07:20:17.08#ibcon#read 6, iclass 38, count 0 2006.253.07:20:17.08#ibcon#end of sib2, iclass 38, count 0 2006.253.07:20:17.08#ibcon#*after write, iclass 38, count 0 2006.253.07:20:17.08#ibcon#*before return 0, iclass 38, count 0 2006.253.07:20:17.08#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.253.07:20:17.08#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.253.07:20:17.08#ibcon#about to clear, iclass 38 cls_cnt 0 2006.253.07:20:17.08#ibcon#cleared, iclass 38 cls_cnt 0 2006.253.07:20:17.08$vc4f8/valo=5,652.99 2006.253.07:20:17.08#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.253.07:20:17.08#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.253.07:20:17.08#ibcon#ireg 17 cls_cnt 0 2006.253.07:20:17.08#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.253.07:20:17.08#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.253.07:20:17.08#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.253.07:20:17.08#ibcon#enter wrdev, iclass 40, count 0 2006.253.07:20:17.08#ibcon#first serial, iclass 40, count 0 2006.253.07:20:17.08#ibcon#enter sib2, iclass 40, count 0 2006.253.07:20:17.08#ibcon#flushed, iclass 40, count 0 2006.253.07:20:17.08#ibcon#about to write, iclass 40, count 0 2006.253.07:20:17.08#ibcon#wrote, iclass 40, count 0 2006.253.07:20:17.08#ibcon#about to read 3, iclass 40, count 0 2006.253.07:20:17.10#ibcon#read 3, iclass 40, count 0 2006.253.07:20:17.10#ibcon#about to read 4, iclass 40, count 0 2006.253.07:20:17.10#ibcon#read 4, iclass 40, count 0 2006.253.07:20:17.10#ibcon#about to read 5, iclass 40, count 0 2006.253.07:20:17.10#ibcon#read 5, iclass 40, count 0 2006.253.07:20:17.10#ibcon#about to read 6, iclass 40, count 0 2006.253.07:20:17.10#ibcon#read 6, iclass 40, count 0 2006.253.07:20:17.10#ibcon#end of sib2, iclass 40, count 0 2006.253.07:20:17.10#ibcon#*mode == 0, iclass 40, count 0 2006.253.07:20:17.10#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.253.07:20:17.10#ibcon#[26=FRQ=05,652.99\r\n] 2006.253.07:20:17.10#ibcon#*before write, iclass 40, count 0 2006.253.07:20:17.10#ibcon#enter sib2, iclass 40, count 0 2006.253.07:20:17.10#ibcon#flushed, iclass 40, count 0 2006.253.07:20:17.10#ibcon#about to write, iclass 40, count 0 2006.253.07:20:17.10#ibcon#wrote, iclass 40, count 0 2006.253.07:20:17.10#ibcon#about to read 3, iclass 40, count 0 2006.253.07:20:17.14#ibcon#read 3, iclass 40, count 0 2006.253.07:20:17.14#ibcon#about to read 4, iclass 40, count 0 2006.253.07:20:17.14#ibcon#read 4, iclass 40, count 0 2006.253.07:20:17.14#ibcon#about to read 5, iclass 40, count 0 2006.253.07:20:17.14#ibcon#read 5, iclass 40, count 0 2006.253.07:20:17.14#ibcon#about to read 6, iclass 40, count 0 2006.253.07:20:17.14#ibcon#read 6, iclass 40, count 0 2006.253.07:20:17.14#ibcon#end of sib2, iclass 40, count 0 2006.253.07:20:17.14#ibcon#*after write, iclass 40, count 0 2006.253.07:20:17.14#ibcon#*before return 0, iclass 40, count 0 2006.253.07:20:17.14#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.253.07:20:17.14#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.253.07:20:17.14#ibcon#about to clear, iclass 40 cls_cnt 0 2006.253.07:20:17.14#ibcon#cleared, iclass 40 cls_cnt 0 2006.253.07:20:17.14$vc4f8/va=5,7 2006.253.07:20:17.14#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.253.07:20:17.14#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.253.07:20:17.14#ibcon#ireg 11 cls_cnt 2 2006.253.07:20:17.14#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.253.07:20:17.20#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.253.07:20:17.20#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.253.07:20:17.20#ibcon#enter wrdev, iclass 4, count 2 2006.253.07:20:17.20#ibcon#first serial, iclass 4, count 2 2006.253.07:20:17.20#ibcon#enter sib2, iclass 4, count 2 2006.253.07:20:17.20#ibcon#flushed, iclass 4, count 2 2006.253.07:20:17.20#ibcon#about to write, iclass 4, count 2 2006.253.07:20:17.20#ibcon#wrote, iclass 4, count 2 2006.253.07:20:17.20#ibcon#about to read 3, iclass 4, count 2 2006.253.07:20:17.22#ibcon#read 3, iclass 4, count 2 2006.253.07:20:17.22#ibcon#about to read 4, iclass 4, count 2 2006.253.07:20:17.22#ibcon#read 4, iclass 4, count 2 2006.253.07:20:17.22#ibcon#about to read 5, iclass 4, count 2 2006.253.07:20:17.22#ibcon#read 5, iclass 4, count 2 2006.253.07:20:17.22#ibcon#about to read 6, iclass 4, count 2 2006.253.07:20:17.22#ibcon#read 6, iclass 4, count 2 2006.253.07:20:17.22#ibcon#end of sib2, iclass 4, count 2 2006.253.07:20:17.22#ibcon#*mode == 0, iclass 4, count 2 2006.253.07:20:17.22#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.253.07:20:17.22#ibcon#[25=AT05-07\r\n] 2006.253.07:20:17.22#ibcon#*before write, iclass 4, count 2 2006.253.07:20:17.22#ibcon#enter sib2, iclass 4, count 2 2006.253.07:20:17.22#ibcon#flushed, iclass 4, count 2 2006.253.07:20:17.22#ibcon#about to write, iclass 4, count 2 2006.253.07:20:17.22#ibcon#wrote, iclass 4, count 2 2006.253.07:20:17.22#ibcon#about to read 3, iclass 4, count 2 2006.253.07:20:17.25#ibcon#read 3, iclass 4, count 2 2006.253.07:20:17.25#ibcon#about to read 4, iclass 4, count 2 2006.253.07:20:17.25#ibcon#read 4, iclass 4, count 2 2006.253.07:20:17.25#ibcon#about to read 5, iclass 4, count 2 2006.253.07:20:17.25#ibcon#read 5, iclass 4, count 2 2006.253.07:20:17.25#ibcon#about to read 6, iclass 4, count 2 2006.253.07:20:17.25#ibcon#read 6, iclass 4, count 2 2006.253.07:20:17.25#ibcon#end of sib2, iclass 4, count 2 2006.253.07:20:17.25#ibcon#*after write, iclass 4, count 2 2006.253.07:20:17.25#ibcon#*before return 0, iclass 4, count 2 2006.253.07:20:17.25#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.253.07:20:17.25#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.253.07:20:17.25#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.253.07:20:17.25#ibcon#ireg 7 cls_cnt 0 2006.253.07:20:17.25#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.253.07:20:17.37#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.253.07:20:17.37#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.253.07:20:17.37#ibcon#enter wrdev, iclass 4, count 0 2006.253.07:20:17.37#ibcon#first serial, iclass 4, count 0 2006.253.07:20:17.37#ibcon#enter sib2, iclass 4, count 0 2006.253.07:20:17.37#ibcon#flushed, iclass 4, count 0 2006.253.07:20:17.37#ibcon#about to write, iclass 4, count 0 2006.253.07:20:17.37#ibcon#wrote, iclass 4, count 0 2006.253.07:20:17.37#ibcon#about to read 3, iclass 4, count 0 2006.253.07:20:17.39#ibcon#read 3, iclass 4, count 0 2006.253.07:20:17.39#ibcon#about to read 4, iclass 4, count 0 2006.253.07:20:17.39#ibcon#read 4, iclass 4, count 0 2006.253.07:20:17.39#ibcon#about to read 5, iclass 4, count 0 2006.253.07:20:17.39#ibcon#read 5, iclass 4, count 0 2006.253.07:20:17.39#ibcon#about to read 6, iclass 4, count 0 2006.253.07:20:17.39#ibcon#read 6, iclass 4, count 0 2006.253.07:20:17.39#ibcon#end of sib2, iclass 4, count 0 2006.253.07:20:17.39#ibcon#*mode == 0, iclass 4, count 0 2006.253.07:20:17.39#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.253.07:20:17.39#ibcon#[25=USB\r\n] 2006.253.07:20:17.39#ibcon#*before write, iclass 4, count 0 2006.253.07:20:17.39#ibcon#enter sib2, iclass 4, count 0 2006.253.07:20:17.39#ibcon#flushed, iclass 4, count 0 2006.253.07:20:17.39#ibcon#about to write, iclass 4, count 0 2006.253.07:20:17.39#ibcon#wrote, iclass 4, count 0 2006.253.07:20:17.39#ibcon#about to read 3, iclass 4, count 0 2006.253.07:20:17.42#ibcon#read 3, iclass 4, count 0 2006.253.07:20:17.42#ibcon#about to read 4, iclass 4, count 0 2006.253.07:20:17.42#ibcon#read 4, iclass 4, count 0 2006.253.07:20:17.42#ibcon#about to read 5, iclass 4, count 0 2006.253.07:20:17.42#ibcon#read 5, iclass 4, count 0 2006.253.07:20:17.42#ibcon#about to read 6, iclass 4, count 0 2006.253.07:20:17.42#ibcon#read 6, iclass 4, count 0 2006.253.07:20:17.42#ibcon#end of sib2, iclass 4, count 0 2006.253.07:20:17.42#ibcon#*after write, iclass 4, count 0 2006.253.07:20:17.42#ibcon#*before return 0, iclass 4, count 0 2006.253.07:20:17.42#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.253.07:20:17.42#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.253.07:20:17.42#ibcon#about to clear, iclass 4 cls_cnt 0 2006.253.07:20:17.42#ibcon#cleared, iclass 4 cls_cnt 0 2006.253.07:20:17.42$vc4f8/valo=6,772.99 2006.253.07:20:17.42#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.253.07:20:17.42#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.253.07:20:17.42#ibcon#ireg 17 cls_cnt 0 2006.253.07:20:17.42#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.253.07:20:17.42#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.253.07:20:17.42#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.253.07:20:17.42#ibcon#enter wrdev, iclass 6, count 0 2006.253.07:20:17.42#ibcon#first serial, iclass 6, count 0 2006.253.07:20:17.42#ibcon#enter sib2, iclass 6, count 0 2006.253.07:20:17.42#ibcon#flushed, iclass 6, count 0 2006.253.07:20:17.42#ibcon#about to write, iclass 6, count 0 2006.253.07:20:17.42#ibcon#wrote, iclass 6, count 0 2006.253.07:20:17.42#ibcon#about to read 3, iclass 6, count 0 2006.253.07:20:17.44#ibcon#read 3, iclass 6, count 0 2006.253.07:20:17.44#ibcon#about to read 4, iclass 6, count 0 2006.253.07:20:17.44#ibcon#read 4, iclass 6, count 0 2006.253.07:20:17.44#ibcon#about to read 5, iclass 6, count 0 2006.253.07:20:17.44#ibcon#read 5, iclass 6, count 0 2006.253.07:20:17.44#ibcon#about to read 6, iclass 6, count 0 2006.253.07:20:17.44#ibcon#read 6, iclass 6, count 0 2006.253.07:20:17.44#ibcon#end of sib2, iclass 6, count 0 2006.253.07:20:17.44#ibcon#*mode == 0, iclass 6, count 0 2006.253.07:20:17.44#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.253.07:20:17.44#ibcon#[26=FRQ=06,772.99\r\n] 2006.253.07:20:17.44#ibcon#*before write, iclass 6, count 0 2006.253.07:20:17.44#ibcon#enter sib2, iclass 6, count 0 2006.253.07:20:17.44#ibcon#flushed, iclass 6, count 0 2006.253.07:20:17.44#ibcon#about to write, iclass 6, count 0 2006.253.07:20:17.44#ibcon#wrote, iclass 6, count 0 2006.253.07:20:17.44#ibcon#about to read 3, iclass 6, count 0 2006.253.07:20:17.48#ibcon#read 3, iclass 6, count 0 2006.253.07:20:17.48#ibcon#about to read 4, iclass 6, count 0 2006.253.07:20:17.48#ibcon#read 4, iclass 6, count 0 2006.253.07:20:17.48#ibcon#about to read 5, iclass 6, count 0 2006.253.07:20:17.48#ibcon#read 5, iclass 6, count 0 2006.253.07:20:17.48#ibcon#about to read 6, iclass 6, count 0 2006.253.07:20:17.48#ibcon#read 6, iclass 6, count 0 2006.253.07:20:17.48#ibcon#end of sib2, iclass 6, count 0 2006.253.07:20:17.48#ibcon#*after write, iclass 6, count 0 2006.253.07:20:17.48#ibcon#*before return 0, iclass 6, count 0 2006.253.07:20:17.48#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.253.07:20:17.48#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.253.07:20:17.48#ibcon#about to clear, iclass 6 cls_cnt 0 2006.253.07:20:17.48#ibcon#cleared, iclass 6 cls_cnt 0 2006.253.07:20:17.48$vc4f8/va=6,7 2006.253.07:20:17.48#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.253.07:20:17.48#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.253.07:20:17.48#ibcon#ireg 11 cls_cnt 2 2006.253.07:20:17.48#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.253.07:20:17.54#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.253.07:20:17.54#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.253.07:20:17.54#ibcon#enter wrdev, iclass 10, count 2 2006.253.07:20:17.54#ibcon#first serial, iclass 10, count 2 2006.253.07:20:17.54#ibcon#enter sib2, iclass 10, count 2 2006.253.07:20:17.54#ibcon#flushed, iclass 10, count 2 2006.253.07:20:17.54#ibcon#about to write, iclass 10, count 2 2006.253.07:20:17.54#ibcon#wrote, iclass 10, count 2 2006.253.07:20:17.54#ibcon#about to read 3, iclass 10, count 2 2006.253.07:20:17.56#ibcon#read 3, iclass 10, count 2 2006.253.07:20:17.56#ibcon#about to read 4, iclass 10, count 2 2006.253.07:20:17.56#ibcon#read 4, iclass 10, count 2 2006.253.07:20:17.56#ibcon#about to read 5, iclass 10, count 2 2006.253.07:20:17.56#ibcon#read 5, iclass 10, count 2 2006.253.07:20:17.56#ibcon#about to read 6, iclass 10, count 2 2006.253.07:20:17.56#ibcon#read 6, iclass 10, count 2 2006.253.07:20:17.56#ibcon#end of sib2, iclass 10, count 2 2006.253.07:20:17.56#ibcon#*mode == 0, iclass 10, count 2 2006.253.07:20:17.56#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.253.07:20:17.56#ibcon#[25=AT06-07\r\n] 2006.253.07:20:17.56#ibcon#*before write, iclass 10, count 2 2006.253.07:20:17.56#ibcon#enter sib2, iclass 10, count 2 2006.253.07:20:17.56#ibcon#flushed, iclass 10, count 2 2006.253.07:20:17.56#ibcon#about to write, iclass 10, count 2 2006.253.07:20:17.56#ibcon#wrote, iclass 10, count 2 2006.253.07:20:17.56#ibcon#about to read 3, iclass 10, count 2 2006.253.07:20:17.59#ibcon#read 3, iclass 10, count 2 2006.253.07:20:17.59#ibcon#about to read 4, iclass 10, count 2 2006.253.07:20:17.59#ibcon#read 4, iclass 10, count 2 2006.253.07:20:17.59#ibcon#about to read 5, iclass 10, count 2 2006.253.07:20:17.59#ibcon#read 5, iclass 10, count 2 2006.253.07:20:17.59#ibcon#about to read 6, iclass 10, count 2 2006.253.07:20:17.59#ibcon#read 6, iclass 10, count 2 2006.253.07:20:17.59#ibcon#end of sib2, iclass 10, count 2 2006.253.07:20:17.59#ibcon#*after write, iclass 10, count 2 2006.253.07:20:17.59#ibcon#*before return 0, iclass 10, count 2 2006.253.07:20:17.59#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.253.07:20:17.59#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.253.07:20:17.59#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.253.07:20:17.59#ibcon#ireg 7 cls_cnt 0 2006.253.07:20:17.59#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.253.07:20:17.71#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.253.07:20:17.71#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.253.07:20:17.71#ibcon#enter wrdev, iclass 10, count 0 2006.253.07:20:17.71#ibcon#first serial, iclass 10, count 0 2006.253.07:20:17.71#ibcon#enter sib2, iclass 10, count 0 2006.253.07:20:17.71#ibcon#flushed, iclass 10, count 0 2006.253.07:20:17.71#ibcon#about to write, iclass 10, count 0 2006.253.07:20:17.71#ibcon#wrote, iclass 10, count 0 2006.253.07:20:17.71#ibcon#about to read 3, iclass 10, count 0 2006.253.07:20:17.73#ibcon#read 3, iclass 10, count 0 2006.253.07:20:17.73#ibcon#about to read 4, iclass 10, count 0 2006.253.07:20:17.73#ibcon#read 4, iclass 10, count 0 2006.253.07:20:17.73#ibcon#about to read 5, iclass 10, count 0 2006.253.07:20:17.73#ibcon#read 5, iclass 10, count 0 2006.253.07:20:17.73#ibcon#about to read 6, iclass 10, count 0 2006.253.07:20:17.73#ibcon#read 6, iclass 10, count 0 2006.253.07:20:17.73#ibcon#end of sib2, iclass 10, count 0 2006.253.07:20:17.73#ibcon#*mode == 0, iclass 10, count 0 2006.253.07:20:17.73#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.253.07:20:17.73#ibcon#[25=USB\r\n] 2006.253.07:20:17.73#ibcon#*before write, iclass 10, count 0 2006.253.07:20:17.73#ibcon#enter sib2, iclass 10, count 0 2006.253.07:20:17.73#ibcon#flushed, iclass 10, count 0 2006.253.07:20:17.73#ibcon#about to write, iclass 10, count 0 2006.253.07:20:17.73#ibcon#wrote, iclass 10, count 0 2006.253.07:20:17.73#ibcon#about to read 3, iclass 10, count 0 2006.253.07:20:17.76#ibcon#read 3, iclass 10, count 0 2006.253.07:20:17.76#ibcon#about to read 4, iclass 10, count 0 2006.253.07:20:17.76#ibcon#read 4, iclass 10, count 0 2006.253.07:20:17.76#ibcon#about to read 5, iclass 10, count 0 2006.253.07:20:17.76#ibcon#read 5, iclass 10, count 0 2006.253.07:20:17.76#ibcon#about to read 6, iclass 10, count 0 2006.253.07:20:17.76#ibcon#read 6, iclass 10, count 0 2006.253.07:20:17.76#ibcon#end of sib2, iclass 10, count 0 2006.253.07:20:17.76#ibcon#*after write, iclass 10, count 0 2006.253.07:20:17.76#ibcon#*before return 0, iclass 10, count 0 2006.253.07:20:17.76#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.253.07:20:17.76#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.253.07:20:17.76#ibcon#about to clear, iclass 10 cls_cnt 0 2006.253.07:20:17.76#ibcon#cleared, iclass 10 cls_cnt 0 2006.253.07:20:17.76$vc4f8/valo=7,832.99 2006.253.07:20:17.76#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.253.07:20:17.76#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.253.07:20:17.76#ibcon#ireg 17 cls_cnt 0 2006.253.07:20:17.76#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.253.07:20:17.76#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.253.07:20:17.76#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.253.07:20:17.76#ibcon#enter wrdev, iclass 12, count 0 2006.253.07:20:17.76#ibcon#first serial, iclass 12, count 0 2006.253.07:20:17.76#ibcon#enter sib2, iclass 12, count 0 2006.253.07:20:17.76#ibcon#flushed, iclass 12, count 0 2006.253.07:20:17.76#ibcon#about to write, iclass 12, count 0 2006.253.07:20:17.76#ibcon#wrote, iclass 12, count 0 2006.253.07:20:17.76#ibcon#about to read 3, iclass 12, count 0 2006.253.07:20:17.78#ibcon#read 3, iclass 12, count 0 2006.253.07:20:17.78#ibcon#about to read 4, iclass 12, count 0 2006.253.07:20:17.78#ibcon#read 4, iclass 12, count 0 2006.253.07:20:17.78#ibcon#about to read 5, iclass 12, count 0 2006.253.07:20:17.78#ibcon#read 5, iclass 12, count 0 2006.253.07:20:17.78#ibcon#about to read 6, iclass 12, count 0 2006.253.07:20:17.78#ibcon#read 6, iclass 12, count 0 2006.253.07:20:17.78#ibcon#end of sib2, iclass 12, count 0 2006.253.07:20:17.78#ibcon#*mode == 0, iclass 12, count 0 2006.253.07:20:17.78#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.253.07:20:17.78#ibcon#[26=FRQ=07,832.99\r\n] 2006.253.07:20:17.78#ibcon#*before write, iclass 12, count 0 2006.253.07:20:17.78#ibcon#enter sib2, iclass 12, count 0 2006.253.07:20:17.78#ibcon#flushed, iclass 12, count 0 2006.253.07:20:17.78#ibcon#about to write, iclass 12, count 0 2006.253.07:20:17.78#ibcon#wrote, iclass 12, count 0 2006.253.07:20:17.78#ibcon#about to read 3, iclass 12, count 0 2006.253.07:20:17.82#ibcon#read 3, iclass 12, count 0 2006.253.07:20:17.82#ibcon#about to read 4, iclass 12, count 0 2006.253.07:20:17.82#ibcon#read 4, iclass 12, count 0 2006.253.07:20:17.82#ibcon#about to read 5, iclass 12, count 0 2006.253.07:20:17.82#ibcon#read 5, iclass 12, count 0 2006.253.07:20:17.82#ibcon#about to read 6, iclass 12, count 0 2006.253.07:20:17.82#ibcon#read 6, iclass 12, count 0 2006.253.07:20:17.82#ibcon#end of sib2, iclass 12, count 0 2006.253.07:20:17.82#ibcon#*after write, iclass 12, count 0 2006.253.07:20:17.82#ibcon#*before return 0, iclass 12, count 0 2006.253.07:20:17.82#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.253.07:20:17.82#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.253.07:20:17.82#ibcon#about to clear, iclass 12 cls_cnt 0 2006.253.07:20:17.82#ibcon#cleared, iclass 12 cls_cnt 0 2006.253.07:20:17.82$vc4f8/va=7,7 2006.253.07:20:17.82#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.253.07:20:17.82#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.253.07:20:17.82#ibcon#ireg 11 cls_cnt 2 2006.253.07:20:17.82#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.253.07:20:17.89#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.253.07:20:17.89#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.253.07:20:17.89#ibcon#enter wrdev, iclass 14, count 2 2006.253.07:20:17.89#ibcon#first serial, iclass 14, count 2 2006.253.07:20:17.89#ibcon#enter sib2, iclass 14, count 2 2006.253.07:20:17.89#ibcon#flushed, iclass 14, count 2 2006.253.07:20:17.89#ibcon#about to write, iclass 14, count 2 2006.253.07:20:17.89#ibcon#wrote, iclass 14, count 2 2006.253.07:20:17.89#ibcon#about to read 3, iclass 14, count 2 2006.253.07:20:17.90#ibcon#read 3, iclass 14, count 2 2006.253.07:20:17.90#ibcon#about to read 4, iclass 14, count 2 2006.253.07:20:17.90#ibcon#read 4, iclass 14, count 2 2006.253.07:20:17.90#ibcon#about to read 5, iclass 14, count 2 2006.253.07:20:17.90#ibcon#read 5, iclass 14, count 2 2006.253.07:20:17.90#ibcon#about to read 6, iclass 14, count 2 2006.253.07:20:17.90#ibcon#read 6, iclass 14, count 2 2006.253.07:20:17.90#ibcon#end of sib2, iclass 14, count 2 2006.253.07:20:17.90#ibcon#*mode == 0, iclass 14, count 2 2006.253.07:20:17.90#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.253.07:20:17.90#ibcon#[25=AT07-07\r\n] 2006.253.07:20:17.90#ibcon#*before write, iclass 14, count 2 2006.253.07:20:17.90#ibcon#enter sib2, iclass 14, count 2 2006.253.07:20:17.90#ibcon#flushed, iclass 14, count 2 2006.253.07:20:17.90#ibcon#about to write, iclass 14, count 2 2006.253.07:20:17.90#ibcon#wrote, iclass 14, count 2 2006.253.07:20:17.90#ibcon#about to read 3, iclass 14, count 2 2006.253.07:20:17.93#ibcon#read 3, iclass 14, count 2 2006.253.07:20:17.93#ibcon#about to read 4, iclass 14, count 2 2006.253.07:20:17.93#ibcon#read 4, iclass 14, count 2 2006.253.07:20:17.93#ibcon#about to read 5, iclass 14, count 2 2006.253.07:20:17.93#ibcon#read 5, iclass 14, count 2 2006.253.07:20:17.93#ibcon#about to read 6, iclass 14, count 2 2006.253.07:20:17.93#ibcon#read 6, iclass 14, count 2 2006.253.07:20:17.93#ibcon#end of sib2, iclass 14, count 2 2006.253.07:20:17.93#ibcon#*after write, iclass 14, count 2 2006.253.07:20:17.93#ibcon#*before return 0, iclass 14, count 2 2006.253.07:20:17.93#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.253.07:20:17.93#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.253.07:20:17.93#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.253.07:20:17.93#ibcon#ireg 7 cls_cnt 0 2006.253.07:20:17.93#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.253.07:20:18.05#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.253.07:20:18.05#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.253.07:20:18.05#ibcon#enter wrdev, iclass 14, count 0 2006.253.07:20:18.05#ibcon#first serial, iclass 14, count 0 2006.253.07:20:18.05#ibcon#enter sib2, iclass 14, count 0 2006.253.07:20:18.05#ibcon#flushed, iclass 14, count 0 2006.253.07:20:18.05#ibcon#about to write, iclass 14, count 0 2006.253.07:20:18.05#ibcon#wrote, iclass 14, count 0 2006.253.07:20:18.05#ibcon#about to read 3, iclass 14, count 0 2006.253.07:20:18.07#ibcon#read 3, iclass 14, count 0 2006.253.07:20:18.07#ibcon#about to read 4, iclass 14, count 0 2006.253.07:20:18.07#ibcon#read 4, iclass 14, count 0 2006.253.07:20:18.07#ibcon#about to read 5, iclass 14, count 0 2006.253.07:20:18.07#ibcon#read 5, iclass 14, count 0 2006.253.07:20:18.07#ibcon#about to read 6, iclass 14, count 0 2006.253.07:20:18.07#ibcon#read 6, iclass 14, count 0 2006.253.07:20:18.07#ibcon#end of sib2, iclass 14, count 0 2006.253.07:20:18.07#ibcon#*mode == 0, iclass 14, count 0 2006.253.07:20:18.07#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.253.07:20:18.07#ibcon#[25=USB\r\n] 2006.253.07:20:18.07#ibcon#*before write, iclass 14, count 0 2006.253.07:20:18.07#ibcon#enter sib2, iclass 14, count 0 2006.253.07:20:18.07#ibcon#flushed, iclass 14, count 0 2006.253.07:20:18.07#ibcon#about to write, iclass 14, count 0 2006.253.07:20:18.07#ibcon#wrote, iclass 14, count 0 2006.253.07:20:18.07#ibcon#about to read 3, iclass 14, count 0 2006.253.07:20:18.10#ibcon#read 3, iclass 14, count 0 2006.253.07:20:18.10#ibcon#about to read 4, iclass 14, count 0 2006.253.07:20:18.10#ibcon#read 4, iclass 14, count 0 2006.253.07:20:18.10#ibcon#about to read 5, iclass 14, count 0 2006.253.07:20:18.10#ibcon#read 5, iclass 14, count 0 2006.253.07:20:18.10#ibcon#about to read 6, iclass 14, count 0 2006.253.07:20:18.10#ibcon#read 6, iclass 14, count 0 2006.253.07:20:18.10#ibcon#end of sib2, iclass 14, count 0 2006.253.07:20:18.10#ibcon#*after write, iclass 14, count 0 2006.253.07:20:18.10#ibcon#*before return 0, iclass 14, count 0 2006.253.07:20:18.10#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.253.07:20:18.10#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.253.07:20:18.10#ibcon#about to clear, iclass 14 cls_cnt 0 2006.253.07:20:18.10#ibcon#cleared, iclass 14 cls_cnt 0 2006.253.07:20:18.10$vc4f8/valo=8,852.99 2006.253.07:20:18.10#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.253.07:20:18.10#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.253.07:20:18.10#ibcon#ireg 17 cls_cnt 0 2006.253.07:20:18.10#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.253.07:20:18.10#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.253.07:20:18.10#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.253.07:20:18.10#ibcon#enter wrdev, iclass 16, count 0 2006.253.07:20:18.10#ibcon#first serial, iclass 16, count 0 2006.253.07:20:18.10#ibcon#enter sib2, iclass 16, count 0 2006.253.07:20:18.10#ibcon#flushed, iclass 16, count 0 2006.253.07:20:18.10#ibcon#about to write, iclass 16, count 0 2006.253.07:20:18.10#ibcon#wrote, iclass 16, count 0 2006.253.07:20:18.10#ibcon#about to read 3, iclass 16, count 0 2006.253.07:20:18.12#ibcon#read 3, iclass 16, count 0 2006.253.07:20:18.12#ibcon#about to read 4, iclass 16, count 0 2006.253.07:20:18.12#ibcon#read 4, iclass 16, count 0 2006.253.07:20:18.12#ibcon#about to read 5, iclass 16, count 0 2006.253.07:20:18.12#ibcon#read 5, iclass 16, count 0 2006.253.07:20:18.12#ibcon#about to read 6, iclass 16, count 0 2006.253.07:20:18.12#ibcon#read 6, iclass 16, count 0 2006.253.07:20:18.12#ibcon#end of sib2, iclass 16, count 0 2006.253.07:20:18.12#ibcon#*mode == 0, iclass 16, count 0 2006.253.07:20:18.12#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.253.07:20:18.12#ibcon#[26=FRQ=08,852.99\r\n] 2006.253.07:20:18.12#ibcon#*before write, iclass 16, count 0 2006.253.07:20:18.12#ibcon#enter sib2, iclass 16, count 0 2006.253.07:20:18.12#ibcon#flushed, iclass 16, count 0 2006.253.07:20:18.12#ibcon#about to write, iclass 16, count 0 2006.253.07:20:18.12#ibcon#wrote, iclass 16, count 0 2006.253.07:20:18.12#ibcon#about to read 3, iclass 16, count 0 2006.253.07:20:18.16#ibcon#read 3, iclass 16, count 0 2006.253.07:20:18.16#ibcon#about to read 4, iclass 16, count 0 2006.253.07:20:18.16#ibcon#read 4, iclass 16, count 0 2006.253.07:20:18.16#ibcon#about to read 5, iclass 16, count 0 2006.253.07:20:18.16#ibcon#read 5, iclass 16, count 0 2006.253.07:20:18.16#ibcon#about to read 6, iclass 16, count 0 2006.253.07:20:18.16#ibcon#read 6, iclass 16, count 0 2006.253.07:20:18.16#ibcon#end of sib2, iclass 16, count 0 2006.253.07:20:18.16#ibcon#*after write, iclass 16, count 0 2006.253.07:20:18.16#ibcon#*before return 0, iclass 16, count 0 2006.253.07:20:18.16#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.253.07:20:18.16#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.253.07:20:18.16#ibcon#about to clear, iclass 16 cls_cnt 0 2006.253.07:20:18.16#ibcon#cleared, iclass 16 cls_cnt 0 2006.253.07:20:18.16$vc4f8/va=8,7 2006.253.07:20:18.16#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.253.07:20:18.16#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.253.07:20:18.16#ibcon#ireg 11 cls_cnt 2 2006.253.07:20:18.16#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.253.07:20:18.22#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.253.07:20:18.22#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.253.07:20:18.22#ibcon#enter wrdev, iclass 18, count 2 2006.253.07:20:18.22#ibcon#first serial, iclass 18, count 2 2006.253.07:20:18.22#ibcon#enter sib2, iclass 18, count 2 2006.253.07:20:18.22#ibcon#flushed, iclass 18, count 2 2006.253.07:20:18.22#ibcon#about to write, iclass 18, count 2 2006.253.07:20:18.22#ibcon#wrote, iclass 18, count 2 2006.253.07:20:18.22#ibcon#about to read 3, iclass 18, count 2 2006.253.07:20:18.24#ibcon#read 3, iclass 18, count 2 2006.253.07:20:18.24#ibcon#about to read 4, iclass 18, count 2 2006.253.07:20:18.24#ibcon#read 4, iclass 18, count 2 2006.253.07:20:18.24#ibcon#about to read 5, iclass 18, count 2 2006.253.07:20:18.24#ibcon#read 5, iclass 18, count 2 2006.253.07:20:18.24#ibcon#about to read 6, iclass 18, count 2 2006.253.07:20:18.24#ibcon#read 6, iclass 18, count 2 2006.253.07:20:18.24#ibcon#end of sib2, iclass 18, count 2 2006.253.07:20:18.24#ibcon#*mode == 0, iclass 18, count 2 2006.253.07:20:18.24#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.253.07:20:18.24#ibcon#[25=AT08-07\r\n] 2006.253.07:20:18.24#ibcon#*before write, iclass 18, count 2 2006.253.07:20:18.24#ibcon#enter sib2, iclass 18, count 2 2006.253.07:20:18.24#ibcon#flushed, iclass 18, count 2 2006.253.07:20:18.24#ibcon#about to write, iclass 18, count 2 2006.253.07:20:18.24#ibcon#wrote, iclass 18, count 2 2006.253.07:20:18.24#ibcon#about to read 3, iclass 18, count 2 2006.253.07:20:18.27#ibcon#read 3, iclass 18, count 2 2006.253.07:20:18.27#ibcon#about to read 4, iclass 18, count 2 2006.253.07:20:18.27#ibcon#read 4, iclass 18, count 2 2006.253.07:20:18.27#ibcon#about to read 5, iclass 18, count 2 2006.253.07:20:18.27#ibcon#read 5, iclass 18, count 2 2006.253.07:20:18.27#ibcon#about to read 6, iclass 18, count 2 2006.253.07:20:18.27#ibcon#read 6, iclass 18, count 2 2006.253.07:20:18.27#ibcon#end of sib2, iclass 18, count 2 2006.253.07:20:18.27#ibcon#*after write, iclass 18, count 2 2006.253.07:20:18.27#ibcon#*before return 0, iclass 18, count 2 2006.253.07:20:18.27#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.253.07:20:18.27#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.253.07:20:18.27#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.253.07:20:18.27#ibcon#ireg 7 cls_cnt 0 2006.253.07:20:18.27#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.253.07:20:18.39#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.253.07:20:18.39#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.253.07:20:18.39#ibcon#enter wrdev, iclass 18, count 0 2006.253.07:20:18.39#ibcon#first serial, iclass 18, count 0 2006.253.07:20:18.39#ibcon#enter sib2, iclass 18, count 0 2006.253.07:20:18.39#ibcon#flushed, iclass 18, count 0 2006.253.07:20:18.39#ibcon#about to write, iclass 18, count 0 2006.253.07:20:18.39#ibcon#wrote, iclass 18, count 0 2006.253.07:20:18.39#ibcon#about to read 3, iclass 18, count 0 2006.253.07:20:18.41#ibcon#read 3, iclass 18, count 0 2006.253.07:20:18.41#ibcon#about to read 4, iclass 18, count 0 2006.253.07:20:18.41#ibcon#read 4, iclass 18, count 0 2006.253.07:20:18.41#ibcon#about to read 5, iclass 18, count 0 2006.253.07:20:18.41#ibcon#read 5, iclass 18, count 0 2006.253.07:20:18.41#ibcon#about to read 6, iclass 18, count 0 2006.253.07:20:18.41#ibcon#read 6, iclass 18, count 0 2006.253.07:20:18.41#ibcon#end of sib2, iclass 18, count 0 2006.253.07:20:18.41#ibcon#*mode == 0, iclass 18, count 0 2006.253.07:20:18.41#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.253.07:20:18.41#ibcon#[25=USB\r\n] 2006.253.07:20:18.41#ibcon#*before write, iclass 18, count 0 2006.253.07:20:18.41#ibcon#enter sib2, iclass 18, count 0 2006.253.07:20:18.41#ibcon#flushed, iclass 18, count 0 2006.253.07:20:18.41#ibcon#about to write, iclass 18, count 0 2006.253.07:20:18.41#ibcon#wrote, iclass 18, count 0 2006.253.07:20:18.41#ibcon#about to read 3, iclass 18, count 0 2006.253.07:20:18.44#ibcon#read 3, iclass 18, count 0 2006.253.07:20:18.44#ibcon#about to read 4, iclass 18, count 0 2006.253.07:20:18.44#ibcon#read 4, iclass 18, count 0 2006.253.07:20:18.44#ibcon#about to read 5, iclass 18, count 0 2006.253.07:20:18.44#ibcon#read 5, iclass 18, count 0 2006.253.07:20:18.44#ibcon#about to read 6, iclass 18, count 0 2006.253.07:20:18.44#ibcon#read 6, iclass 18, count 0 2006.253.07:20:18.44#ibcon#end of sib2, iclass 18, count 0 2006.253.07:20:18.44#ibcon#*after write, iclass 18, count 0 2006.253.07:20:18.44#ibcon#*before return 0, iclass 18, count 0 2006.253.07:20:18.44#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.253.07:20:18.44#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.253.07:20:18.44#ibcon#about to clear, iclass 18 cls_cnt 0 2006.253.07:20:18.44#ibcon#cleared, iclass 18 cls_cnt 0 2006.253.07:20:18.44$vc4f8/vblo=1,632.99 2006.253.07:20:18.44#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.253.07:20:18.44#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.253.07:20:18.44#ibcon#ireg 17 cls_cnt 0 2006.253.07:20:18.44#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.253.07:20:18.44#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.253.07:20:18.44#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.253.07:20:18.44#ibcon#enter wrdev, iclass 20, count 0 2006.253.07:20:18.44#ibcon#first serial, iclass 20, count 0 2006.253.07:20:18.44#ibcon#enter sib2, iclass 20, count 0 2006.253.07:20:18.44#ibcon#flushed, iclass 20, count 0 2006.253.07:20:18.44#ibcon#about to write, iclass 20, count 0 2006.253.07:20:18.44#ibcon#wrote, iclass 20, count 0 2006.253.07:20:18.44#ibcon#about to read 3, iclass 20, count 0 2006.253.07:20:18.47#ibcon#read 3, iclass 20, count 0 2006.253.07:20:18.47#ibcon#about to read 4, iclass 20, count 0 2006.253.07:20:18.47#ibcon#read 4, iclass 20, count 0 2006.253.07:20:18.47#ibcon#about to read 5, iclass 20, count 0 2006.253.07:20:18.47#ibcon#read 5, iclass 20, count 0 2006.253.07:20:18.47#ibcon#about to read 6, iclass 20, count 0 2006.253.07:20:18.47#ibcon#read 6, iclass 20, count 0 2006.253.07:20:18.47#ibcon#end of sib2, iclass 20, count 0 2006.253.07:20:18.47#ibcon#*mode == 0, iclass 20, count 0 2006.253.07:20:18.47#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.253.07:20:18.47#ibcon#[28=FRQ=01,632.99\r\n] 2006.253.07:20:18.47#ibcon#*before write, iclass 20, count 0 2006.253.07:20:18.47#ibcon#enter sib2, iclass 20, count 0 2006.253.07:20:18.47#ibcon#flushed, iclass 20, count 0 2006.253.07:20:18.47#ibcon#about to write, iclass 20, count 0 2006.253.07:20:18.47#ibcon#wrote, iclass 20, count 0 2006.253.07:20:18.47#ibcon#about to read 3, iclass 20, count 0 2006.253.07:20:18.51#ibcon#read 3, iclass 20, count 0 2006.253.07:20:18.51#ibcon#about to read 4, iclass 20, count 0 2006.253.07:20:18.51#ibcon#read 4, iclass 20, count 0 2006.253.07:20:18.51#ibcon#about to read 5, iclass 20, count 0 2006.253.07:20:18.51#ibcon#read 5, iclass 20, count 0 2006.253.07:20:18.51#ibcon#about to read 6, iclass 20, count 0 2006.253.07:20:18.51#ibcon#read 6, iclass 20, count 0 2006.253.07:20:18.51#ibcon#end of sib2, iclass 20, count 0 2006.253.07:20:18.51#ibcon#*after write, iclass 20, count 0 2006.253.07:20:18.51#ibcon#*before return 0, iclass 20, count 0 2006.253.07:20:18.51#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.253.07:20:18.51#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.253.07:20:18.51#ibcon#about to clear, iclass 20 cls_cnt 0 2006.253.07:20:18.51#ibcon#cleared, iclass 20 cls_cnt 0 2006.253.07:20:18.51$vc4f8/vb=1,4 2006.253.07:20:18.51#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.253.07:20:18.51#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.253.07:20:18.51#ibcon#ireg 11 cls_cnt 2 2006.253.07:20:18.51#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.253.07:20:18.51#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.253.07:20:18.51#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.253.07:20:18.51#ibcon#enter wrdev, iclass 22, count 2 2006.253.07:20:18.51#ibcon#first serial, iclass 22, count 2 2006.253.07:20:18.51#ibcon#enter sib2, iclass 22, count 2 2006.253.07:20:18.51#ibcon#flushed, iclass 22, count 2 2006.253.07:20:18.51#ibcon#about to write, iclass 22, count 2 2006.253.07:20:18.51#ibcon#wrote, iclass 22, count 2 2006.253.07:20:18.51#ibcon#about to read 3, iclass 22, count 2 2006.253.07:20:18.53#ibcon#read 3, iclass 22, count 2 2006.253.07:20:18.53#ibcon#about to read 4, iclass 22, count 2 2006.253.07:20:18.53#ibcon#read 4, iclass 22, count 2 2006.253.07:20:18.53#ibcon#about to read 5, iclass 22, count 2 2006.253.07:20:18.53#ibcon#read 5, iclass 22, count 2 2006.253.07:20:18.53#ibcon#about to read 6, iclass 22, count 2 2006.253.07:20:18.53#ibcon#read 6, iclass 22, count 2 2006.253.07:20:18.53#ibcon#end of sib2, iclass 22, count 2 2006.253.07:20:18.53#ibcon#*mode == 0, iclass 22, count 2 2006.253.07:20:18.53#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.253.07:20:18.53#ibcon#[27=AT01-04\r\n] 2006.253.07:20:18.53#ibcon#*before write, iclass 22, count 2 2006.253.07:20:18.53#ibcon#enter sib2, iclass 22, count 2 2006.253.07:20:18.53#ibcon#flushed, iclass 22, count 2 2006.253.07:20:18.53#ibcon#about to write, iclass 22, count 2 2006.253.07:20:18.53#ibcon#wrote, iclass 22, count 2 2006.253.07:20:18.53#ibcon#about to read 3, iclass 22, count 2 2006.253.07:20:18.56#ibcon#read 3, iclass 22, count 2 2006.253.07:20:18.56#ibcon#about to read 4, iclass 22, count 2 2006.253.07:20:18.56#ibcon#read 4, iclass 22, count 2 2006.253.07:20:18.56#ibcon#about to read 5, iclass 22, count 2 2006.253.07:20:18.56#ibcon#read 5, iclass 22, count 2 2006.253.07:20:18.56#ibcon#about to read 6, iclass 22, count 2 2006.253.07:20:18.56#ibcon#read 6, iclass 22, count 2 2006.253.07:20:18.56#ibcon#end of sib2, iclass 22, count 2 2006.253.07:20:18.56#ibcon#*after write, iclass 22, count 2 2006.253.07:20:18.56#ibcon#*before return 0, iclass 22, count 2 2006.253.07:20:18.56#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.253.07:20:18.56#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.253.07:20:18.56#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.253.07:20:18.56#ibcon#ireg 7 cls_cnt 0 2006.253.07:20:18.56#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.253.07:20:18.68#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.253.07:20:18.68#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.253.07:20:18.68#ibcon#enter wrdev, iclass 22, count 0 2006.253.07:20:18.68#ibcon#first serial, iclass 22, count 0 2006.253.07:20:18.68#ibcon#enter sib2, iclass 22, count 0 2006.253.07:20:18.68#ibcon#flushed, iclass 22, count 0 2006.253.07:20:18.68#ibcon#about to write, iclass 22, count 0 2006.253.07:20:18.68#ibcon#wrote, iclass 22, count 0 2006.253.07:20:18.68#ibcon#about to read 3, iclass 22, count 0 2006.253.07:20:18.70#ibcon#read 3, iclass 22, count 0 2006.253.07:20:18.70#ibcon#about to read 4, iclass 22, count 0 2006.253.07:20:18.70#ibcon#read 4, iclass 22, count 0 2006.253.07:20:18.70#ibcon#about to read 5, iclass 22, count 0 2006.253.07:20:18.70#ibcon#read 5, iclass 22, count 0 2006.253.07:20:18.70#ibcon#about to read 6, iclass 22, count 0 2006.253.07:20:18.70#ibcon#read 6, iclass 22, count 0 2006.253.07:20:18.70#ibcon#end of sib2, iclass 22, count 0 2006.253.07:20:18.70#ibcon#*mode == 0, iclass 22, count 0 2006.253.07:20:18.70#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.253.07:20:18.70#ibcon#[27=USB\r\n] 2006.253.07:20:18.70#ibcon#*before write, iclass 22, count 0 2006.253.07:20:18.70#ibcon#enter sib2, iclass 22, count 0 2006.253.07:20:18.70#ibcon#flushed, iclass 22, count 0 2006.253.07:20:18.70#ibcon#about to write, iclass 22, count 0 2006.253.07:20:18.70#ibcon#wrote, iclass 22, count 0 2006.253.07:20:18.70#ibcon#about to read 3, iclass 22, count 0 2006.253.07:20:18.73#ibcon#read 3, iclass 22, count 0 2006.253.07:20:18.73#ibcon#about to read 4, iclass 22, count 0 2006.253.07:20:18.73#ibcon#read 4, iclass 22, count 0 2006.253.07:20:18.73#ibcon#about to read 5, iclass 22, count 0 2006.253.07:20:18.73#ibcon#read 5, iclass 22, count 0 2006.253.07:20:18.73#ibcon#about to read 6, iclass 22, count 0 2006.253.07:20:18.73#ibcon#read 6, iclass 22, count 0 2006.253.07:20:18.73#ibcon#end of sib2, iclass 22, count 0 2006.253.07:20:18.73#ibcon#*after write, iclass 22, count 0 2006.253.07:20:18.73#ibcon#*before return 0, iclass 22, count 0 2006.253.07:20:18.73#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.253.07:20:18.73#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.253.07:20:18.73#ibcon#about to clear, iclass 22 cls_cnt 0 2006.253.07:20:18.73#ibcon#cleared, iclass 22 cls_cnt 0 2006.253.07:20:18.73$vc4f8/vblo=2,640.99 2006.253.07:20:18.73#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.253.07:20:18.73#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.253.07:20:18.73#ibcon#ireg 17 cls_cnt 0 2006.253.07:20:18.73#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.253.07:20:18.73#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.253.07:20:18.73#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.253.07:20:18.73#ibcon#enter wrdev, iclass 24, count 0 2006.253.07:20:18.73#ibcon#first serial, iclass 24, count 0 2006.253.07:20:18.73#ibcon#enter sib2, iclass 24, count 0 2006.253.07:20:18.73#ibcon#flushed, iclass 24, count 0 2006.253.07:20:18.73#ibcon#about to write, iclass 24, count 0 2006.253.07:20:18.73#ibcon#wrote, iclass 24, count 0 2006.253.07:20:18.73#ibcon#about to read 3, iclass 24, count 0 2006.253.07:20:18.75#ibcon#read 3, iclass 24, count 0 2006.253.07:20:18.75#ibcon#about to read 4, iclass 24, count 0 2006.253.07:20:18.75#ibcon#read 4, iclass 24, count 0 2006.253.07:20:18.75#ibcon#about to read 5, iclass 24, count 0 2006.253.07:20:18.75#ibcon#read 5, iclass 24, count 0 2006.253.07:20:18.75#ibcon#about to read 6, iclass 24, count 0 2006.253.07:20:18.75#ibcon#read 6, iclass 24, count 0 2006.253.07:20:18.75#ibcon#end of sib2, iclass 24, count 0 2006.253.07:20:18.75#ibcon#*mode == 0, iclass 24, count 0 2006.253.07:20:18.75#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.253.07:20:18.75#ibcon#[28=FRQ=02,640.99\r\n] 2006.253.07:20:18.75#ibcon#*before write, iclass 24, count 0 2006.253.07:20:18.75#ibcon#enter sib2, iclass 24, count 0 2006.253.07:20:18.75#ibcon#flushed, iclass 24, count 0 2006.253.07:20:18.75#ibcon#about to write, iclass 24, count 0 2006.253.07:20:18.75#ibcon#wrote, iclass 24, count 0 2006.253.07:20:18.75#ibcon#about to read 3, iclass 24, count 0 2006.253.07:20:18.79#ibcon#read 3, iclass 24, count 0 2006.253.07:20:18.79#ibcon#about to read 4, iclass 24, count 0 2006.253.07:20:18.79#ibcon#read 4, iclass 24, count 0 2006.253.07:20:18.79#ibcon#about to read 5, iclass 24, count 0 2006.253.07:20:18.79#ibcon#read 5, iclass 24, count 0 2006.253.07:20:18.79#ibcon#about to read 6, iclass 24, count 0 2006.253.07:20:18.79#ibcon#read 6, iclass 24, count 0 2006.253.07:20:18.79#ibcon#end of sib2, iclass 24, count 0 2006.253.07:20:18.79#ibcon#*after write, iclass 24, count 0 2006.253.07:20:18.79#ibcon#*before return 0, iclass 24, count 0 2006.253.07:20:18.79#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.253.07:20:18.79#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.253.07:20:18.79#ibcon#about to clear, iclass 24 cls_cnt 0 2006.253.07:20:18.79#ibcon#cleared, iclass 24 cls_cnt 0 2006.253.07:20:18.79$vc4f8/vb=2,5 2006.253.07:20:18.79#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.253.07:20:18.79#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.253.07:20:18.79#ibcon#ireg 11 cls_cnt 2 2006.253.07:20:18.79#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.253.07:20:18.85#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.253.07:20:18.85#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.253.07:20:18.85#ibcon#enter wrdev, iclass 26, count 2 2006.253.07:20:18.85#ibcon#first serial, iclass 26, count 2 2006.253.07:20:18.85#ibcon#enter sib2, iclass 26, count 2 2006.253.07:20:18.85#ibcon#flushed, iclass 26, count 2 2006.253.07:20:18.85#ibcon#about to write, iclass 26, count 2 2006.253.07:20:18.85#ibcon#wrote, iclass 26, count 2 2006.253.07:20:18.85#ibcon#about to read 3, iclass 26, count 2 2006.253.07:20:18.87#ibcon#read 3, iclass 26, count 2 2006.253.07:20:18.87#ibcon#about to read 4, iclass 26, count 2 2006.253.07:20:18.87#ibcon#read 4, iclass 26, count 2 2006.253.07:20:18.87#ibcon#about to read 5, iclass 26, count 2 2006.253.07:20:18.87#ibcon#read 5, iclass 26, count 2 2006.253.07:20:18.87#ibcon#about to read 6, iclass 26, count 2 2006.253.07:20:18.87#ibcon#read 6, iclass 26, count 2 2006.253.07:20:18.87#ibcon#end of sib2, iclass 26, count 2 2006.253.07:20:18.87#ibcon#*mode == 0, iclass 26, count 2 2006.253.07:20:18.87#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.253.07:20:18.87#ibcon#[27=AT02-05\r\n] 2006.253.07:20:18.87#ibcon#*before write, iclass 26, count 2 2006.253.07:20:18.87#ibcon#enter sib2, iclass 26, count 2 2006.253.07:20:18.87#ibcon#flushed, iclass 26, count 2 2006.253.07:20:18.87#ibcon#about to write, iclass 26, count 2 2006.253.07:20:18.87#ibcon#wrote, iclass 26, count 2 2006.253.07:20:18.87#ibcon#about to read 3, iclass 26, count 2 2006.253.07:20:18.90#ibcon#read 3, iclass 26, count 2 2006.253.07:20:18.90#ibcon#about to read 4, iclass 26, count 2 2006.253.07:20:18.90#ibcon#read 4, iclass 26, count 2 2006.253.07:20:18.90#ibcon#about to read 5, iclass 26, count 2 2006.253.07:20:18.90#ibcon#read 5, iclass 26, count 2 2006.253.07:20:18.90#ibcon#about to read 6, iclass 26, count 2 2006.253.07:20:18.90#ibcon#read 6, iclass 26, count 2 2006.253.07:20:18.90#ibcon#end of sib2, iclass 26, count 2 2006.253.07:20:18.90#ibcon#*after write, iclass 26, count 2 2006.253.07:20:18.90#ibcon#*before return 0, iclass 26, count 2 2006.253.07:20:18.90#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.253.07:20:18.90#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.253.07:20:18.90#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.253.07:20:18.90#ibcon#ireg 7 cls_cnt 0 2006.253.07:20:18.90#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.253.07:20:19.02#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.253.07:20:19.02#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.253.07:20:19.02#ibcon#enter wrdev, iclass 26, count 0 2006.253.07:20:19.02#ibcon#first serial, iclass 26, count 0 2006.253.07:20:19.02#ibcon#enter sib2, iclass 26, count 0 2006.253.07:20:19.02#ibcon#flushed, iclass 26, count 0 2006.253.07:20:19.02#ibcon#about to write, iclass 26, count 0 2006.253.07:20:19.02#ibcon#wrote, iclass 26, count 0 2006.253.07:20:19.02#ibcon#about to read 3, iclass 26, count 0 2006.253.07:20:19.04#ibcon#read 3, iclass 26, count 0 2006.253.07:20:19.04#ibcon#about to read 4, iclass 26, count 0 2006.253.07:20:19.04#ibcon#read 4, iclass 26, count 0 2006.253.07:20:19.04#ibcon#about to read 5, iclass 26, count 0 2006.253.07:20:19.04#ibcon#read 5, iclass 26, count 0 2006.253.07:20:19.04#ibcon#about to read 6, iclass 26, count 0 2006.253.07:20:19.04#ibcon#read 6, iclass 26, count 0 2006.253.07:20:19.04#ibcon#end of sib2, iclass 26, count 0 2006.253.07:20:19.04#ibcon#*mode == 0, iclass 26, count 0 2006.253.07:20:19.04#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.253.07:20:19.04#ibcon#[27=USB\r\n] 2006.253.07:20:19.04#ibcon#*before write, iclass 26, count 0 2006.253.07:20:19.04#ibcon#enter sib2, iclass 26, count 0 2006.253.07:20:19.04#ibcon#flushed, iclass 26, count 0 2006.253.07:20:19.04#ibcon#about to write, iclass 26, count 0 2006.253.07:20:19.04#ibcon#wrote, iclass 26, count 0 2006.253.07:20:19.04#ibcon#about to read 3, iclass 26, count 0 2006.253.07:20:19.07#ibcon#read 3, iclass 26, count 0 2006.253.07:20:19.07#ibcon#about to read 4, iclass 26, count 0 2006.253.07:20:19.07#ibcon#read 4, iclass 26, count 0 2006.253.07:20:19.07#ibcon#about to read 5, iclass 26, count 0 2006.253.07:20:19.07#ibcon#read 5, iclass 26, count 0 2006.253.07:20:19.07#ibcon#about to read 6, iclass 26, count 0 2006.253.07:20:19.07#ibcon#read 6, iclass 26, count 0 2006.253.07:20:19.07#ibcon#end of sib2, iclass 26, count 0 2006.253.07:20:19.07#ibcon#*after write, iclass 26, count 0 2006.253.07:20:19.07#ibcon#*before return 0, iclass 26, count 0 2006.253.07:20:19.07#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.253.07:20:19.07#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.253.07:20:19.07#ibcon#about to clear, iclass 26 cls_cnt 0 2006.253.07:20:19.07#ibcon#cleared, iclass 26 cls_cnt 0 2006.253.07:20:19.07$vc4f8/vblo=3,656.99 2006.253.07:20:19.07#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.253.07:20:19.07#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.253.07:20:19.07#ibcon#ireg 17 cls_cnt 0 2006.253.07:20:19.07#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.253.07:20:19.07#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.253.07:20:19.07#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.253.07:20:19.07#ibcon#enter wrdev, iclass 28, count 0 2006.253.07:20:19.07#ibcon#first serial, iclass 28, count 0 2006.253.07:20:19.07#ibcon#enter sib2, iclass 28, count 0 2006.253.07:20:19.07#ibcon#flushed, iclass 28, count 0 2006.253.07:20:19.07#ibcon#about to write, iclass 28, count 0 2006.253.07:20:19.07#ibcon#wrote, iclass 28, count 0 2006.253.07:20:19.07#ibcon#about to read 3, iclass 28, count 0 2006.253.07:20:19.09#ibcon#read 3, iclass 28, count 0 2006.253.07:20:19.09#ibcon#about to read 4, iclass 28, count 0 2006.253.07:20:19.09#ibcon#read 4, iclass 28, count 0 2006.253.07:20:19.09#ibcon#about to read 5, iclass 28, count 0 2006.253.07:20:19.09#ibcon#read 5, iclass 28, count 0 2006.253.07:20:19.09#ibcon#about to read 6, iclass 28, count 0 2006.253.07:20:19.09#ibcon#read 6, iclass 28, count 0 2006.253.07:20:19.09#ibcon#end of sib2, iclass 28, count 0 2006.253.07:20:19.09#ibcon#*mode == 0, iclass 28, count 0 2006.253.07:20:19.09#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.253.07:20:19.09#ibcon#[28=FRQ=03,656.99\r\n] 2006.253.07:20:19.09#ibcon#*before write, iclass 28, count 0 2006.253.07:20:19.09#ibcon#enter sib2, iclass 28, count 0 2006.253.07:20:19.09#ibcon#flushed, iclass 28, count 0 2006.253.07:20:19.09#ibcon#about to write, iclass 28, count 0 2006.253.07:20:19.09#ibcon#wrote, iclass 28, count 0 2006.253.07:20:19.09#ibcon#about to read 3, iclass 28, count 0 2006.253.07:20:19.13#ibcon#read 3, iclass 28, count 0 2006.253.07:20:19.13#ibcon#about to read 4, iclass 28, count 0 2006.253.07:20:19.13#ibcon#read 4, iclass 28, count 0 2006.253.07:20:19.13#ibcon#about to read 5, iclass 28, count 0 2006.253.07:20:19.13#ibcon#read 5, iclass 28, count 0 2006.253.07:20:19.13#ibcon#about to read 6, iclass 28, count 0 2006.253.07:20:19.13#ibcon#read 6, iclass 28, count 0 2006.253.07:20:19.13#ibcon#end of sib2, iclass 28, count 0 2006.253.07:20:19.13#ibcon#*after write, iclass 28, count 0 2006.253.07:20:19.13#ibcon#*before return 0, iclass 28, count 0 2006.253.07:20:19.13#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.253.07:20:19.13#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.253.07:20:19.13#ibcon#about to clear, iclass 28 cls_cnt 0 2006.253.07:20:19.13#ibcon#cleared, iclass 28 cls_cnt 0 2006.253.07:20:19.13$vc4f8/vb=3,4 2006.253.07:20:19.13#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.253.07:20:19.13#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.253.07:20:19.13#ibcon#ireg 11 cls_cnt 2 2006.253.07:20:19.13#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.253.07:20:19.19#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.253.07:20:19.19#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.253.07:20:19.19#ibcon#enter wrdev, iclass 30, count 2 2006.253.07:20:19.19#ibcon#first serial, iclass 30, count 2 2006.253.07:20:19.19#ibcon#enter sib2, iclass 30, count 2 2006.253.07:20:19.19#ibcon#flushed, iclass 30, count 2 2006.253.07:20:19.19#ibcon#about to write, iclass 30, count 2 2006.253.07:20:19.19#ibcon#wrote, iclass 30, count 2 2006.253.07:20:19.19#ibcon#about to read 3, iclass 30, count 2 2006.253.07:20:19.21#ibcon#read 3, iclass 30, count 2 2006.253.07:20:19.21#ibcon#about to read 4, iclass 30, count 2 2006.253.07:20:19.21#ibcon#read 4, iclass 30, count 2 2006.253.07:20:19.21#ibcon#about to read 5, iclass 30, count 2 2006.253.07:20:19.21#ibcon#read 5, iclass 30, count 2 2006.253.07:20:19.21#ibcon#about to read 6, iclass 30, count 2 2006.253.07:20:19.21#ibcon#read 6, iclass 30, count 2 2006.253.07:20:19.21#ibcon#end of sib2, iclass 30, count 2 2006.253.07:20:19.21#ibcon#*mode == 0, iclass 30, count 2 2006.253.07:20:19.21#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.253.07:20:19.21#ibcon#[27=AT03-04\r\n] 2006.253.07:20:19.21#ibcon#*before write, iclass 30, count 2 2006.253.07:20:19.21#ibcon#enter sib2, iclass 30, count 2 2006.253.07:20:19.21#ibcon#flushed, iclass 30, count 2 2006.253.07:20:19.21#ibcon#about to write, iclass 30, count 2 2006.253.07:20:19.21#ibcon#wrote, iclass 30, count 2 2006.253.07:20:19.21#ibcon#about to read 3, iclass 30, count 2 2006.253.07:20:19.24#ibcon#read 3, iclass 30, count 2 2006.253.07:20:19.24#ibcon#about to read 4, iclass 30, count 2 2006.253.07:20:19.24#ibcon#read 4, iclass 30, count 2 2006.253.07:20:19.24#ibcon#about to read 5, iclass 30, count 2 2006.253.07:20:19.24#ibcon#read 5, iclass 30, count 2 2006.253.07:20:19.24#ibcon#about to read 6, iclass 30, count 2 2006.253.07:20:19.24#ibcon#read 6, iclass 30, count 2 2006.253.07:20:19.24#ibcon#end of sib2, iclass 30, count 2 2006.253.07:20:19.24#ibcon#*after write, iclass 30, count 2 2006.253.07:20:19.24#ibcon#*before return 0, iclass 30, count 2 2006.253.07:20:19.24#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.253.07:20:19.24#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.253.07:20:19.24#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.253.07:20:19.24#ibcon#ireg 7 cls_cnt 0 2006.253.07:20:19.24#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.253.07:20:19.34#abcon#<5=/08 1.3 3.2 31.75 721006.2\r\n> 2006.253.07:20:19.36#abcon#{5=INTERFACE CLEAR} 2006.253.07:20:19.36#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.253.07:20:19.36#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.253.07:20:19.36#ibcon#enter wrdev, iclass 30, count 0 2006.253.07:20:19.36#ibcon#first serial, iclass 30, count 0 2006.253.07:20:19.36#ibcon#enter sib2, iclass 30, count 0 2006.253.07:20:19.36#ibcon#flushed, iclass 30, count 0 2006.253.07:20:19.36#ibcon#about to write, iclass 30, count 0 2006.253.07:20:19.36#ibcon#wrote, iclass 30, count 0 2006.253.07:20:19.36#ibcon#about to read 3, iclass 30, count 0 2006.253.07:20:19.38#ibcon#read 3, iclass 30, count 0 2006.253.07:20:19.38#ibcon#about to read 4, iclass 30, count 0 2006.253.07:20:19.38#ibcon#read 4, iclass 30, count 0 2006.253.07:20:19.38#ibcon#about to read 5, iclass 30, count 0 2006.253.07:20:19.38#ibcon#read 5, iclass 30, count 0 2006.253.07:20:19.38#ibcon#about to read 6, iclass 30, count 0 2006.253.07:20:19.38#ibcon#read 6, iclass 30, count 0 2006.253.07:20:19.38#ibcon#end of sib2, iclass 30, count 0 2006.253.07:20:19.38#ibcon#*mode == 0, iclass 30, count 0 2006.253.07:20:19.38#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.253.07:20:19.38#ibcon#[27=USB\r\n] 2006.253.07:20:19.38#ibcon#*before write, iclass 30, count 0 2006.253.07:20:19.38#ibcon#enter sib2, iclass 30, count 0 2006.253.07:20:19.38#ibcon#flushed, iclass 30, count 0 2006.253.07:20:19.38#ibcon#about to write, iclass 30, count 0 2006.253.07:20:19.38#ibcon#wrote, iclass 30, count 0 2006.253.07:20:19.38#ibcon#about to read 3, iclass 30, count 0 2006.253.07:20:19.41#ibcon#read 3, iclass 30, count 0 2006.253.07:20:19.41#ibcon#about to read 4, iclass 30, count 0 2006.253.07:20:19.41#ibcon#read 4, iclass 30, count 0 2006.253.07:20:19.41#ibcon#about to read 5, iclass 30, count 0 2006.253.07:20:19.41#ibcon#read 5, iclass 30, count 0 2006.253.07:20:19.41#ibcon#about to read 6, iclass 30, count 0 2006.253.07:20:19.41#ibcon#read 6, iclass 30, count 0 2006.253.07:20:19.41#ibcon#end of sib2, iclass 30, count 0 2006.253.07:20:19.41#ibcon#*after write, iclass 30, count 0 2006.253.07:20:19.41#ibcon#*before return 0, iclass 30, count 0 2006.253.07:20:19.41#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.253.07:20:19.41#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.253.07:20:19.41#ibcon#about to clear, iclass 30 cls_cnt 0 2006.253.07:20:19.41#ibcon#cleared, iclass 30 cls_cnt 0 2006.253.07:20:19.41$vc4f8/vblo=4,712.99 2006.253.07:20:19.41#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.253.07:20:19.41#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.253.07:20:19.41#ibcon#ireg 17 cls_cnt 0 2006.253.07:20:19.41#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.253.07:20:19.41#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.253.07:20:19.41#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.253.07:20:19.41#ibcon#enter wrdev, iclass 36, count 0 2006.253.07:20:19.41#ibcon#first serial, iclass 36, count 0 2006.253.07:20:19.41#ibcon#enter sib2, iclass 36, count 0 2006.253.07:20:19.41#ibcon#flushed, iclass 36, count 0 2006.253.07:20:19.41#ibcon#about to write, iclass 36, count 0 2006.253.07:20:19.41#ibcon#wrote, iclass 36, count 0 2006.253.07:20:19.41#ibcon#about to read 3, iclass 36, count 0 2006.253.07:20:19.42#abcon#[5=S1D000X0/0*\r\n] 2006.253.07:20:19.43#ibcon#read 3, iclass 36, count 0 2006.253.07:20:19.43#ibcon#about to read 4, iclass 36, count 0 2006.253.07:20:19.43#ibcon#read 4, iclass 36, count 0 2006.253.07:20:19.43#ibcon#about to read 5, iclass 36, count 0 2006.253.07:20:19.43#ibcon#read 5, iclass 36, count 0 2006.253.07:20:19.43#ibcon#about to read 6, iclass 36, count 0 2006.253.07:20:19.43#ibcon#read 6, iclass 36, count 0 2006.253.07:20:19.43#ibcon#end of sib2, iclass 36, count 0 2006.253.07:20:19.43#ibcon#*mode == 0, iclass 36, count 0 2006.253.07:20:19.43#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.253.07:20:19.43#ibcon#[28=FRQ=04,712.99\r\n] 2006.253.07:20:19.43#ibcon#*before write, iclass 36, count 0 2006.253.07:20:19.43#ibcon#enter sib2, iclass 36, count 0 2006.253.07:20:19.43#ibcon#flushed, iclass 36, count 0 2006.253.07:20:19.43#ibcon#about to write, iclass 36, count 0 2006.253.07:20:19.43#ibcon#wrote, iclass 36, count 0 2006.253.07:20:19.43#ibcon#about to read 3, iclass 36, count 0 2006.253.07:20:19.47#ibcon#read 3, iclass 36, count 0 2006.253.07:20:19.47#ibcon#about to read 4, iclass 36, count 0 2006.253.07:20:19.47#ibcon#read 4, iclass 36, count 0 2006.253.07:20:19.47#ibcon#about to read 5, iclass 36, count 0 2006.253.07:20:19.47#ibcon#read 5, iclass 36, count 0 2006.253.07:20:19.47#ibcon#about to read 6, iclass 36, count 0 2006.253.07:20:19.47#ibcon#read 6, iclass 36, count 0 2006.253.07:20:19.47#ibcon#end of sib2, iclass 36, count 0 2006.253.07:20:19.47#ibcon#*after write, iclass 36, count 0 2006.253.07:20:19.47#ibcon#*before return 0, iclass 36, count 0 2006.253.07:20:19.47#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.253.07:20:19.47#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.253.07:20:19.47#ibcon#about to clear, iclass 36 cls_cnt 0 2006.253.07:20:19.47#ibcon#cleared, iclass 36 cls_cnt 0 2006.253.07:20:19.47$vc4f8/vb=4,4 2006.253.07:20:19.47#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.253.07:20:19.47#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.253.07:20:19.47#ibcon#ireg 11 cls_cnt 2 2006.253.07:20:19.47#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.253.07:20:19.53#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.253.07:20:19.53#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.253.07:20:19.53#ibcon#enter wrdev, iclass 38, count 2 2006.253.07:20:19.53#ibcon#first serial, iclass 38, count 2 2006.253.07:20:19.53#ibcon#enter sib2, iclass 38, count 2 2006.253.07:20:19.53#ibcon#flushed, iclass 38, count 2 2006.253.07:20:19.53#ibcon#about to write, iclass 38, count 2 2006.253.07:20:19.53#ibcon#wrote, iclass 38, count 2 2006.253.07:20:19.53#ibcon#about to read 3, iclass 38, count 2 2006.253.07:20:19.55#ibcon#read 3, iclass 38, count 2 2006.253.07:20:19.55#ibcon#about to read 4, iclass 38, count 2 2006.253.07:20:19.55#ibcon#read 4, iclass 38, count 2 2006.253.07:20:19.55#ibcon#about to read 5, iclass 38, count 2 2006.253.07:20:19.55#ibcon#read 5, iclass 38, count 2 2006.253.07:20:19.55#ibcon#about to read 6, iclass 38, count 2 2006.253.07:20:19.55#ibcon#read 6, iclass 38, count 2 2006.253.07:20:19.55#ibcon#end of sib2, iclass 38, count 2 2006.253.07:20:19.55#ibcon#*mode == 0, iclass 38, count 2 2006.253.07:20:19.55#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.253.07:20:19.55#ibcon#[27=AT04-04\r\n] 2006.253.07:20:19.55#ibcon#*before write, iclass 38, count 2 2006.253.07:20:19.55#ibcon#enter sib2, iclass 38, count 2 2006.253.07:20:19.55#ibcon#flushed, iclass 38, count 2 2006.253.07:20:19.55#ibcon#about to write, iclass 38, count 2 2006.253.07:20:19.55#ibcon#wrote, iclass 38, count 2 2006.253.07:20:19.55#ibcon#about to read 3, iclass 38, count 2 2006.253.07:20:19.58#ibcon#read 3, iclass 38, count 2 2006.253.07:20:19.58#ibcon#about to read 4, iclass 38, count 2 2006.253.07:20:19.58#ibcon#read 4, iclass 38, count 2 2006.253.07:20:19.58#ibcon#about to read 5, iclass 38, count 2 2006.253.07:20:19.58#ibcon#read 5, iclass 38, count 2 2006.253.07:20:19.58#ibcon#about to read 6, iclass 38, count 2 2006.253.07:20:19.58#ibcon#read 6, iclass 38, count 2 2006.253.07:20:19.58#ibcon#end of sib2, iclass 38, count 2 2006.253.07:20:19.58#ibcon#*after write, iclass 38, count 2 2006.253.07:20:19.58#ibcon#*before return 0, iclass 38, count 2 2006.253.07:20:19.58#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.253.07:20:19.58#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.253.07:20:19.58#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.253.07:20:19.58#ibcon#ireg 7 cls_cnt 0 2006.253.07:20:19.58#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.253.07:20:19.70#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.253.07:20:19.70#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.253.07:20:19.70#ibcon#enter wrdev, iclass 38, count 0 2006.253.07:20:19.70#ibcon#first serial, iclass 38, count 0 2006.253.07:20:19.70#ibcon#enter sib2, iclass 38, count 0 2006.253.07:20:19.70#ibcon#flushed, iclass 38, count 0 2006.253.07:20:19.70#ibcon#about to write, iclass 38, count 0 2006.253.07:20:19.70#ibcon#wrote, iclass 38, count 0 2006.253.07:20:19.70#ibcon#about to read 3, iclass 38, count 0 2006.253.07:20:19.72#ibcon#read 3, iclass 38, count 0 2006.253.07:20:19.72#ibcon#about to read 4, iclass 38, count 0 2006.253.07:20:19.72#ibcon#read 4, iclass 38, count 0 2006.253.07:20:19.72#ibcon#about to read 5, iclass 38, count 0 2006.253.07:20:19.72#ibcon#read 5, iclass 38, count 0 2006.253.07:20:19.72#ibcon#about to read 6, iclass 38, count 0 2006.253.07:20:19.72#ibcon#read 6, iclass 38, count 0 2006.253.07:20:19.72#ibcon#end of sib2, iclass 38, count 0 2006.253.07:20:19.72#ibcon#*mode == 0, iclass 38, count 0 2006.253.07:20:19.72#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.253.07:20:19.72#ibcon#[27=USB\r\n] 2006.253.07:20:19.72#ibcon#*before write, iclass 38, count 0 2006.253.07:20:19.72#ibcon#enter sib2, iclass 38, count 0 2006.253.07:20:19.72#ibcon#flushed, iclass 38, count 0 2006.253.07:20:19.72#ibcon#about to write, iclass 38, count 0 2006.253.07:20:19.72#ibcon#wrote, iclass 38, count 0 2006.253.07:20:19.72#ibcon#about to read 3, iclass 38, count 0 2006.253.07:20:19.75#ibcon#read 3, iclass 38, count 0 2006.253.07:20:19.75#ibcon#about to read 4, iclass 38, count 0 2006.253.07:20:19.75#ibcon#read 4, iclass 38, count 0 2006.253.07:20:19.75#ibcon#about to read 5, iclass 38, count 0 2006.253.07:20:19.75#ibcon#read 5, iclass 38, count 0 2006.253.07:20:19.75#ibcon#about to read 6, iclass 38, count 0 2006.253.07:20:19.75#ibcon#read 6, iclass 38, count 0 2006.253.07:20:19.75#ibcon#end of sib2, iclass 38, count 0 2006.253.07:20:19.75#ibcon#*after write, iclass 38, count 0 2006.253.07:20:19.75#ibcon#*before return 0, iclass 38, count 0 2006.253.07:20:19.75#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.253.07:20:19.75#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.253.07:20:19.75#ibcon#about to clear, iclass 38 cls_cnt 0 2006.253.07:20:19.75#ibcon#cleared, iclass 38 cls_cnt 0 2006.253.07:20:19.75$vc4f8/vblo=5,744.99 2006.253.07:20:19.75#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.253.07:20:19.75#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.253.07:20:19.75#ibcon#ireg 17 cls_cnt 0 2006.253.07:20:19.75#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.253.07:20:19.75#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.253.07:20:19.75#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.253.07:20:19.75#ibcon#enter wrdev, iclass 40, count 0 2006.253.07:20:19.75#ibcon#first serial, iclass 40, count 0 2006.253.07:20:19.75#ibcon#enter sib2, iclass 40, count 0 2006.253.07:20:19.75#ibcon#flushed, iclass 40, count 0 2006.253.07:20:19.75#ibcon#about to write, iclass 40, count 0 2006.253.07:20:19.75#ibcon#wrote, iclass 40, count 0 2006.253.07:20:19.75#ibcon#about to read 3, iclass 40, count 0 2006.253.07:20:19.77#ibcon#read 3, iclass 40, count 0 2006.253.07:20:19.77#ibcon#about to read 4, iclass 40, count 0 2006.253.07:20:19.77#ibcon#read 4, iclass 40, count 0 2006.253.07:20:19.77#ibcon#about to read 5, iclass 40, count 0 2006.253.07:20:19.77#ibcon#read 5, iclass 40, count 0 2006.253.07:20:19.77#ibcon#about to read 6, iclass 40, count 0 2006.253.07:20:19.77#ibcon#read 6, iclass 40, count 0 2006.253.07:20:19.77#ibcon#end of sib2, iclass 40, count 0 2006.253.07:20:19.77#ibcon#*mode == 0, iclass 40, count 0 2006.253.07:20:19.77#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.253.07:20:19.77#ibcon#[28=FRQ=05,744.99\r\n] 2006.253.07:20:19.77#ibcon#*before write, iclass 40, count 0 2006.253.07:20:19.77#ibcon#enter sib2, iclass 40, count 0 2006.253.07:20:19.77#ibcon#flushed, iclass 40, count 0 2006.253.07:20:19.77#ibcon#about to write, iclass 40, count 0 2006.253.07:20:19.77#ibcon#wrote, iclass 40, count 0 2006.253.07:20:19.77#ibcon#about to read 3, iclass 40, count 0 2006.253.07:20:19.81#ibcon#read 3, iclass 40, count 0 2006.253.07:20:19.81#ibcon#about to read 4, iclass 40, count 0 2006.253.07:20:19.81#ibcon#read 4, iclass 40, count 0 2006.253.07:20:19.81#ibcon#about to read 5, iclass 40, count 0 2006.253.07:20:19.81#ibcon#read 5, iclass 40, count 0 2006.253.07:20:19.81#ibcon#about to read 6, iclass 40, count 0 2006.253.07:20:19.81#ibcon#read 6, iclass 40, count 0 2006.253.07:20:19.81#ibcon#end of sib2, iclass 40, count 0 2006.253.07:20:19.81#ibcon#*after write, iclass 40, count 0 2006.253.07:20:19.81#ibcon#*before return 0, iclass 40, count 0 2006.253.07:20:19.81#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.253.07:20:19.81#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.253.07:20:19.81#ibcon#about to clear, iclass 40 cls_cnt 0 2006.253.07:20:19.81#ibcon#cleared, iclass 40 cls_cnt 0 2006.253.07:20:19.81$vc4f8/vb=5,4 2006.253.07:20:19.81#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.253.07:20:19.81#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.253.07:20:19.81#ibcon#ireg 11 cls_cnt 2 2006.253.07:20:19.81#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.253.07:20:19.87#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.253.07:20:19.87#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.253.07:20:19.87#ibcon#enter wrdev, iclass 4, count 2 2006.253.07:20:19.87#ibcon#first serial, iclass 4, count 2 2006.253.07:20:19.87#ibcon#enter sib2, iclass 4, count 2 2006.253.07:20:19.87#ibcon#flushed, iclass 4, count 2 2006.253.07:20:19.87#ibcon#about to write, iclass 4, count 2 2006.253.07:20:19.87#ibcon#wrote, iclass 4, count 2 2006.253.07:20:19.87#ibcon#about to read 3, iclass 4, count 2 2006.253.07:20:19.89#ibcon#read 3, iclass 4, count 2 2006.253.07:20:19.89#ibcon#about to read 4, iclass 4, count 2 2006.253.07:20:19.89#ibcon#read 4, iclass 4, count 2 2006.253.07:20:19.89#ibcon#about to read 5, iclass 4, count 2 2006.253.07:20:19.89#ibcon#read 5, iclass 4, count 2 2006.253.07:20:19.89#ibcon#about to read 6, iclass 4, count 2 2006.253.07:20:19.89#ibcon#read 6, iclass 4, count 2 2006.253.07:20:19.89#ibcon#end of sib2, iclass 4, count 2 2006.253.07:20:19.89#ibcon#*mode == 0, iclass 4, count 2 2006.253.07:20:19.89#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.253.07:20:19.89#ibcon#[27=AT05-04\r\n] 2006.253.07:20:19.89#ibcon#*before write, iclass 4, count 2 2006.253.07:20:19.89#ibcon#enter sib2, iclass 4, count 2 2006.253.07:20:19.89#ibcon#flushed, iclass 4, count 2 2006.253.07:20:19.89#ibcon#about to write, iclass 4, count 2 2006.253.07:20:19.89#ibcon#wrote, iclass 4, count 2 2006.253.07:20:19.89#ibcon#about to read 3, iclass 4, count 2 2006.253.07:20:19.92#ibcon#read 3, iclass 4, count 2 2006.253.07:20:19.92#ibcon#about to read 4, iclass 4, count 2 2006.253.07:20:19.92#ibcon#read 4, iclass 4, count 2 2006.253.07:20:19.92#ibcon#about to read 5, iclass 4, count 2 2006.253.07:20:19.92#ibcon#read 5, iclass 4, count 2 2006.253.07:20:19.92#ibcon#about to read 6, iclass 4, count 2 2006.253.07:20:19.92#ibcon#read 6, iclass 4, count 2 2006.253.07:20:19.92#ibcon#end of sib2, iclass 4, count 2 2006.253.07:20:19.92#ibcon#*after write, iclass 4, count 2 2006.253.07:20:19.92#ibcon#*before return 0, iclass 4, count 2 2006.253.07:20:19.92#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.253.07:20:19.92#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.253.07:20:19.92#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.253.07:20:19.92#ibcon#ireg 7 cls_cnt 0 2006.253.07:20:19.92#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.253.07:20:20.04#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.253.07:20:20.04#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.253.07:20:20.04#ibcon#enter wrdev, iclass 4, count 0 2006.253.07:20:20.04#ibcon#first serial, iclass 4, count 0 2006.253.07:20:20.04#ibcon#enter sib2, iclass 4, count 0 2006.253.07:20:20.04#ibcon#flushed, iclass 4, count 0 2006.253.07:20:20.04#ibcon#about to write, iclass 4, count 0 2006.253.07:20:20.04#ibcon#wrote, iclass 4, count 0 2006.253.07:20:20.04#ibcon#about to read 3, iclass 4, count 0 2006.253.07:20:20.06#ibcon#read 3, iclass 4, count 0 2006.253.07:20:20.06#ibcon#about to read 4, iclass 4, count 0 2006.253.07:20:20.06#ibcon#read 4, iclass 4, count 0 2006.253.07:20:20.06#ibcon#about to read 5, iclass 4, count 0 2006.253.07:20:20.06#ibcon#read 5, iclass 4, count 0 2006.253.07:20:20.06#ibcon#about to read 6, iclass 4, count 0 2006.253.07:20:20.06#ibcon#read 6, iclass 4, count 0 2006.253.07:20:20.06#ibcon#end of sib2, iclass 4, count 0 2006.253.07:20:20.06#ibcon#*mode == 0, iclass 4, count 0 2006.253.07:20:20.06#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.253.07:20:20.06#ibcon#[27=USB\r\n] 2006.253.07:20:20.06#ibcon#*before write, iclass 4, count 0 2006.253.07:20:20.06#ibcon#enter sib2, iclass 4, count 0 2006.253.07:20:20.06#ibcon#flushed, iclass 4, count 0 2006.253.07:20:20.06#ibcon#about to write, iclass 4, count 0 2006.253.07:20:20.06#ibcon#wrote, iclass 4, count 0 2006.253.07:20:20.06#ibcon#about to read 3, iclass 4, count 0 2006.253.07:20:20.09#ibcon#read 3, iclass 4, count 0 2006.253.07:20:20.09#ibcon#about to read 4, iclass 4, count 0 2006.253.07:20:20.09#ibcon#read 4, iclass 4, count 0 2006.253.07:20:20.09#ibcon#about to read 5, iclass 4, count 0 2006.253.07:20:20.09#ibcon#read 5, iclass 4, count 0 2006.253.07:20:20.09#ibcon#about to read 6, iclass 4, count 0 2006.253.07:20:20.09#ibcon#read 6, iclass 4, count 0 2006.253.07:20:20.09#ibcon#end of sib2, iclass 4, count 0 2006.253.07:20:20.09#ibcon#*after write, iclass 4, count 0 2006.253.07:20:20.09#ibcon#*before return 0, iclass 4, count 0 2006.253.07:20:20.09#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.253.07:20:20.09#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.253.07:20:20.09#ibcon#about to clear, iclass 4 cls_cnt 0 2006.253.07:20:20.09#ibcon#cleared, iclass 4 cls_cnt 0 2006.253.07:20:20.09$vc4f8/vblo=6,752.99 2006.253.07:20:20.09#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.253.07:20:20.09#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.253.07:20:20.09#ibcon#ireg 17 cls_cnt 0 2006.253.07:20:20.09#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.253.07:20:20.09#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.253.07:20:20.09#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.253.07:20:20.09#ibcon#enter wrdev, iclass 6, count 0 2006.253.07:20:20.09#ibcon#first serial, iclass 6, count 0 2006.253.07:20:20.09#ibcon#enter sib2, iclass 6, count 0 2006.253.07:20:20.09#ibcon#flushed, iclass 6, count 0 2006.253.07:20:20.09#ibcon#about to write, iclass 6, count 0 2006.253.07:20:20.09#ibcon#wrote, iclass 6, count 0 2006.253.07:20:20.09#ibcon#about to read 3, iclass 6, count 0 2006.253.07:20:20.11#ibcon#read 3, iclass 6, count 0 2006.253.07:20:20.11#ibcon#about to read 4, iclass 6, count 0 2006.253.07:20:20.11#ibcon#read 4, iclass 6, count 0 2006.253.07:20:20.11#ibcon#about to read 5, iclass 6, count 0 2006.253.07:20:20.11#ibcon#read 5, iclass 6, count 0 2006.253.07:20:20.11#ibcon#about to read 6, iclass 6, count 0 2006.253.07:20:20.11#ibcon#read 6, iclass 6, count 0 2006.253.07:20:20.11#ibcon#end of sib2, iclass 6, count 0 2006.253.07:20:20.11#ibcon#*mode == 0, iclass 6, count 0 2006.253.07:20:20.11#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.253.07:20:20.11#ibcon#[28=FRQ=06,752.99\r\n] 2006.253.07:20:20.11#ibcon#*before write, iclass 6, count 0 2006.253.07:20:20.11#ibcon#enter sib2, iclass 6, count 0 2006.253.07:20:20.11#ibcon#flushed, iclass 6, count 0 2006.253.07:20:20.11#ibcon#about to write, iclass 6, count 0 2006.253.07:20:20.11#ibcon#wrote, iclass 6, count 0 2006.253.07:20:20.11#ibcon#about to read 3, iclass 6, count 0 2006.253.07:20:20.15#ibcon#read 3, iclass 6, count 0 2006.253.07:20:20.15#ibcon#about to read 4, iclass 6, count 0 2006.253.07:20:20.15#ibcon#read 4, iclass 6, count 0 2006.253.07:20:20.15#ibcon#about to read 5, iclass 6, count 0 2006.253.07:20:20.15#ibcon#read 5, iclass 6, count 0 2006.253.07:20:20.15#ibcon#about to read 6, iclass 6, count 0 2006.253.07:20:20.15#ibcon#read 6, iclass 6, count 0 2006.253.07:20:20.15#ibcon#end of sib2, iclass 6, count 0 2006.253.07:20:20.15#ibcon#*after write, iclass 6, count 0 2006.253.07:20:20.15#ibcon#*before return 0, iclass 6, count 0 2006.253.07:20:20.15#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.253.07:20:20.15#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.253.07:20:20.15#ibcon#about to clear, iclass 6 cls_cnt 0 2006.253.07:20:20.15#ibcon#cleared, iclass 6 cls_cnt 0 2006.253.07:20:20.15$vc4f8/vb=6,4 2006.253.07:20:20.15#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.253.07:20:20.15#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.253.07:20:20.15#ibcon#ireg 11 cls_cnt 2 2006.253.07:20:20.15#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.253.07:20:20.21#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.253.07:20:20.21#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.253.07:20:20.21#ibcon#enter wrdev, iclass 10, count 2 2006.253.07:20:20.21#ibcon#first serial, iclass 10, count 2 2006.253.07:20:20.21#ibcon#enter sib2, iclass 10, count 2 2006.253.07:20:20.21#ibcon#flushed, iclass 10, count 2 2006.253.07:20:20.21#ibcon#about to write, iclass 10, count 2 2006.253.07:20:20.21#ibcon#wrote, iclass 10, count 2 2006.253.07:20:20.21#ibcon#about to read 3, iclass 10, count 2 2006.253.07:20:20.23#ibcon#read 3, iclass 10, count 2 2006.253.07:20:20.23#ibcon#about to read 4, iclass 10, count 2 2006.253.07:20:20.23#ibcon#read 4, iclass 10, count 2 2006.253.07:20:20.23#ibcon#about to read 5, iclass 10, count 2 2006.253.07:20:20.23#ibcon#read 5, iclass 10, count 2 2006.253.07:20:20.23#ibcon#about to read 6, iclass 10, count 2 2006.253.07:20:20.23#ibcon#read 6, iclass 10, count 2 2006.253.07:20:20.23#ibcon#end of sib2, iclass 10, count 2 2006.253.07:20:20.23#ibcon#*mode == 0, iclass 10, count 2 2006.253.07:20:20.23#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.253.07:20:20.23#ibcon#[27=AT06-04\r\n] 2006.253.07:20:20.23#ibcon#*before write, iclass 10, count 2 2006.253.07:20:20.23#ibcon#enter sib2, iclass 10, count 2 2006.253.07:20:20.23#ibcon#flushed, iclass 10, count 2 2006.253.07:20:20.23#ibcon#about to write, iclass 10, count 2 2006.253.07:20:20.23#ibcon#wrote, iclass 10, count 2 2006.253.07:20:20.23#ibcon#about to read 3, iclass 10, count 2 2006.253.07:20:20.26#ibcon#read 3, iclass 10, count 2 2006.253.07:20:20.26#ibcon#about to read 4, iclass 10, count 2 2006.253.07:20:20.26#ibcon#read 4, iclass 10, count 2 2006.253.07:20:20.26#ibcon#about to read 5, iclass 10, count 2 2006.253.07:20:20.26#ibcon#read 5, iclass 10, count 2 2006.253.07:20:20.26#ibcon#about to read 6, iclass 10, count 2 2006.253.07:20:20.26#ibcon#read 6, iclass 10, count 2 2006.253.07:20:20.26#ibcon#end of sib2, iclass 10, count 2 2006.253.07:20:20.26#ibcon#*after write, iclass 10, count 2 2006.253.07:20:20.26#ibcon#*before return 0, iclass 10, count 2 2006.253.07:20:20.26#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.253.07:20:20.26#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.253.07:20:20.26#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.253.07:20:20.26#ibcon#ireg 7 cls_cnt 0 2006.253.07:20:20.26#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.253.07:20:20.38#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.253.07:20:20.38#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.253.07:20:20.38#ibcon#enter wrdev, iclass 10, count 0 2006.253.07:20:20.38#ibcon#first serial, iclass 10, count 0 2006.253.07:20:20.38#ibcon#enter sib2, iclass 10, count 0 2006.253.07:20:20.38#ibcon#flushed, iclass 10, count 0 2006.253.07:20:20.38#ibcon#about to write, iclass 10, count 0 2006.253.07:20:20.38#ibcon#wrote, iclass 10, count 0 2006.253.07:20:20.38#ibcon#about to read 3, iclass 10, count 0 2006.253.07:20:20.40#ibcon#read 3, iclass 10, count 0 2006.253.07:20:20.40#ibcon#about to read 4, iclass 10, count 0 2006.253.07:20:20.40#ibcon#read 4, iclass 10, count 0 2006.253.07:20:20.40#ibcon#about to read 5, iclass 10, count 0 2006.253.07:20:20.40#ibcon#read 5, iclass 10, count 0 2006.253.07:20:20.40#ibcon#about to read 6, iclass 10, count 0 2006.253.07:20:20.40#ibcon#read 6, iclass 10, count 0 2006.253.07:20:20.40#ibcon#end of sib2, iclass 10, count 0 2006.253.07:20:20.40#ibcon#*mode == 0, iclass 10, count 0 2006.253.07:20:20.40#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.253.07:20:20.40#ibcon#[27=USB\r\n] 2006.253.07:20:20.40#ibcon#*before write, iclass 10, count 0 2006.253.07:20:20.40#ibcon#enter sib2, iclass 10, count 0 2006.253.07:20:20.40#ibcon#flushed, iclass 10, count 0 2006.253.07:20:20.40#ibcon#about to write, iclass 10, count 0 2006.253.07:20:20.40#ibcon#wrote, iclass 10, count 0 2006.253.07:20:20.40#ibcon#about to read 3, iclass 10, count 0 2006.253.07:20:20.43#ibcon#read 3, iclass 10, count 0 2006.253.07:20:20.43#ibcon#about to read 4, iclass 10, count 0 2006.253.07:20:20.43#ibcon#read 4, iclass 10, count 0 2006.253.07:20:20.43#ibcon#about to read 5, iclass 10, count 0 2006.253.07:20:20.43#ibcon#read 5, iclass 10, count 0 2006.253.07:20:20.43#ibcon#about to read 6, iclass 10, count 0 2006.253.07:20:20.43#ibcon#read 6, iclass 10, count 0 2006.253.07:20:20.43#ibcon#end of sib2, iclass 10, count 0 2006.253.07:20:20.43#ibcon#*after write, iclass 10, count 0 2006.253.07:20:20.43#ibcon#*before return 0, iclass 10, count 0 2006.253.07:20:20.43#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.253.07:20:20.43#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.253.07:20:20.43#ibcon#about to clear, iclass 10 cls_cnt 0 2006.253.07:20:20.43#ibcon#cleared, iclass 10 cls_cnt 0 2006.253.07:20:20.43$vc4f8/vabw=wide 2006.253.07:20:20.43#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.253.07:20:20.43#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.253.07:20:20.43#ibcon#ireg 8 cls_cnt 0 2006.253.07:20:20.43#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.253.07:20:20.43#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.253.07:20:20.43#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.253.07:20:20.43#ibcon#enter wrdev, iclass 12, count 0 2006.253.07:20:20.43#ibcon#first serial, iclass 12, count 0 2006.253.07:20:20.43#ibcon#enter sib2, iclass 12, count 0 2006.253.07:20:20.43#ibcon#flushed, iclass 12, count 0 2006.253.07:20:20.43#ibcon#about to write, iclass 12, count 0 2006.253.07:20:20.43#ibcon#wrote, iclass 12, count 0 2006.253.07:20:20.43#ibcon#about to read 3, iclass 12, count 0 2006.253.07:20:20.45#ibcon#read 3, iclass 12, count 0 2006.253.07:20:20.45#ibcon#about to read 4, iclass 12, count 0 2006.253.07:20:20.45#ibcon#read 4, iclass 12, count 0 2006.253.07:20:20.45#ibcon#about to read 5, iclass 12, count 0 2006.253.07:20:20.45#ibcon#read 5, iclass 12, count 0 2006.253.07:20:20.45#ibcon#about to read 6, iclass 12, count 0 2006.253.07:20:20.45#ibcon#read 6, iclass 12, count 0 2006.253.07:20:20.45#ibcon#end of sib2, iclass 12, count 0 2006.253.07:20:20.45#ibcon#*mode == 0, iclass 12, count 0 2006.253.07:20:20.45#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.253.07:20:20.45#ibcon#[25=BW32\r\n] 2006.253.07:20:20.45#ibcon#*before write, iclass 12, count 0 2006.253.07:20:20.45#ibcon#enter sib2, iclass 12, count 0 2006.253.07:20:20.45#ibcon#flushed, iclass 12, count 0 2006.253.07:20:20.45#ibcon#about to write, iclass 12, count 0 2006.253.07:20:20.45#ibcon#wrote, iclass 12, count 0 2006.253.07:20:20.45#ibcon#about to read 3, iclass 12, count 0 2006.253.07:20:20.48#ibcon#read 3, iclass 12, count 0 2006.253.07:20:20.48#ibcon#about to read 4, iclass 12, count 0 2006.253.07:20:20.48#ibcon#read 4, iclass 12, count 0 2006.253.07:20:20.48#ibcon#about to read 5, iclass 12, count 0 2006.253.07:20:20.48#ibcon#read 5, iclass 12, count 0 2006.253.07:20:20.48#ibcon#about to read 6, iclass 12, count 0 2006.253.07:20:20.48#ibcon#read 6, iclass 12, count 0 2006.253.07:20:20.48#ibcon#end of sib2, iclass 12, count 0 2006.253.07:20:20.48#ibcon#*after write, iclass 12, count 0 2006.253.07:20:20.48#ibcon#*before return 0, iclass 12, count 0 2006.253.07:20:20.48#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.253.07:20:20.48#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.253.07:20:20.48#ibcon#about to clear, iclass 12 cls_cnt 0 2006.253.07:20:20.48#ibcon#cleared, iclass 12 cls_cnt 0 2006.253.07:20:20.48$vc4f8/vbbw=wide 2006.253.07:20:20.48#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.253.07:20:20.48#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.253.07:20:20.48#ibcon#ireg 8 cls_cnt 0 2006.253.07:20:20.48#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.253.07:20:20.55#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.253.07:20:20.55#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.253.07:20:20.55#ibcon#enter wrdev, iclass 14, count 0 2006.253.07:20:20.55#ibcon#first serial, iclass 14, count 0 2006.253.07:20:20.55#ibcon#enter sib2, iclass 14, count 0 2006.253.07:20:20.55#ibcon#flushed, iclass 14, count 0 2006.253.07:20:20.55#ibcon#about to write, iclass 14, count 0 2006.253.07:20:20.55#ibcon#wrote, iclass 14, count 0 2006.253.07:20:20.55#ibcon#about to read 3, iclass 14, count 0 2006.253.07:20:20.57#ibcon#read 3, iclass 14, count 0 2006.253.07:20:20.57#ibcon#about to read 4, iclass 14, count 0 2006.253.07:20:20.57#ibcon#read 4, iclass 14, count 0 2006.253.07:20:20.57#ibcon#about to read 5, iclass 14, count 0 2006.253.07:20:20.57#ibcon#read 5, iclass 14, count 0 2006.253.07:20:20.57#ibcon#about to read 6, iclass 14, count 0 2006.253.07:20:20.57#ibcon#read 6, iclass 14, count 0 2006.253.07:20:20.57#ibcon#end of sib2, iclass 14, count 0 2006.253.07:20:20.57#ibcon#*mode == 0, iclass 14, count 0 2006.253.07:20:20.57#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.253.07:20:20.57#ibcon#[27=BW32\r\n] 2006.253.07:20:20.57#ibcon#*before write, iclass 14, count 0 2006.253.07:20:20.57#ibcon#enter sib2, iclass 14, count 0 2006.253.07:20:20.57#ibcon#flushed, iclass 14, count 0 2006.253.07:20:20.57#ibcon#about to write, iclass 14, count 0 2006.253.07:20:20.57#ibcon#wrote, iclass 14, count 0 2006.253.07:20:20.57#ibcon#about to read 3, iclass 14, count 0 2006.253.07:20:20.60#ibcon#read 3, iclass 14, count 0 2006.253.07:20:20.60#ibcon#about to read 4, iclass 14, count 0 2006.253.07:20:20.60#ibcon#read 4, iclass 14, count 0 2006.253.07:20:20.60#ibcon#about to read 5, iclass 14, count 0 2006.253.07:20:20.60#ibcon#read 5, iclass 14, count 0 2006.253.07:20:20.60#ibcon#about to read 6, iclass 14, count 0 2006.253.07:20:20.60#ibcon#read 6, iclass 14, count 0 2006.253.07:20:20.60#ibcon#end of sib2, iclass 14, count 0 2006.253.07:20:20.60#ibcon#*after write, iclass 14, count 0 2006.253.07:20:20.60#ibcon#*before return 0, iclass 14, count 0 2006.253.07:20:20.60#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.253.07:20:20.60#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.253.07:20:20.60#ibcon#about to clear, iclass 14 cls_cnt 0 2006.253.07:20:20.60#ibcon#cleared, iclass 14 cls_cnt 0 2006.253.07:20:20.60$4f8m12a/ifd4f 2006.253.07:20:20.60&ifd4f/lo= 2006.253.07:20:20.60&ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.253.07:20:20.60&ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.253.07:20:20.60&ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.253.07:20:20.60&ifd4f/patch= 2006.253.07:20:20.60&ifd4f/patch=lo1,a1,a2,a3,a4 2006.253.07:20:20.60&ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.253.07:20:20.60&ifd4f/patch=lo3,a5,a6,a7,a8 2006.253.07:20:20.60$ifd4f/lo= 2006.253.07:20:20.60$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.253.07:20:20.60$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.253.07:20:20.60$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.253.07:20:20.60$ifd4f/patch= 2006.253.07:20:20.60$ifd4f/patch=lo1,a1,a2,a3,a4 2006.253.07:20:20.60$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.253.07:20:20.60$ifd4f/patch=lo3,a5,a6,a7,a8 2006.253.07:20:20.60$4f8m12a/"form=m,16.000,1:2 2006.253.07:20:20.60$4f8m12a/"tpicd 2006.253.07:20:20.60$4f8m12a/echo=off 2006.253.07:20:20.60$4f8m12a/xlog=off 2006.253.07:20:20.60:!2006.253.07:29:50 2006.253.07:20:34.13#trakl#Source acquired 2006.253.07:20:35.13#flagr#flagr/antenna,acquired 2006.253.07:29:50.00:preob 2006.253.07:29:50.00&preob/onsource 2006.253.07:29:51.13/onsource/TRACKING 2006.253.07:29:51.13:!2006.253.07:30:00 2006.253.07:30:00.00:data_valid=on 2006.253.07:30:00.00:midob 2006.253.07:30:00.00&midob/onsource 2006.253.07:30:00.00&midob/wx 2006.253.07:30:00.00&midob/cable 2006.253.07:30:00.00&midob/va 2006.253.07:30:00.00&midob/valo 2006.253.07:30:00.00&midob/vb 2006.253.07:30:00.00&midob/vblo 2006.253.07:30:00.00&midob/vabw 2006.253.07:30:00.00&midob/vbbw 2006.253.07:30:00.00&midob/"form 2006.253.07:30:00.00&midob/xfe 2006.253.07:30:00.00&midob/ifatt 2006.253.07:30:00.00&midob/clockoff 2006.253.07:30:00.00&midob/sy=logmail 2006.253.07:30:00.00&midob/"sy=run setcl adapt & 2006.253.07:30:00.13/onsource/TRACKING 2006.253.07:30:00.13/wx/31.63,1006.3,71 2006.253.07:30:00.23/cable/+6.3689E-03 2006.253.07:30:01.32/va/01,08,usb,yes,32,33 2006.253.07:30:01.32/va/02,07,usb,yes,32,33 2006.253.07:30:01.32/va/03,06,usb,yes,34,34 2006.253.07:30:01.32/va/04,07,usb,yes,33,36 2006.253.07:30:01.32/va/05,07,usb,yes,34,36 2006.253.07:30:01.32/va/06,07,usb,yes,30,30 2006.253.07:30:01.32/va/07,07,usb,yes,30,29 2006.253.07:30:01.32/va/08,07,usb,yes,32,32 2006.253.07:30:01.55/valo/01,532.99,yes,locked 2006.253.07:30:01.55/valo/02,572.99,yes,locked 2006.253.07:30:01.55/valo/03,672.99,yes,locked 2006.253.07:30:01.55/valo/04,832.99,yes,locked 2006.253.07:30:01.55/valo/05,652.99,yes,locked 2006.253.07:30:01.55/valo/06,772.99,yes,locked 2006.253.07:30:01.55/valo/07,832.99,yes,locked 2006.253.07:30:01.55/valo/08,852.99,yes,locked 2006.253.07:30:02.64/vb/01,04,usb,yes,31,29 2006.253.07:30:02.64/vb/02,05,usb,yes,29,30 2006.253.07:30:02.64/vb/03,04,usb,yes,29,33 2006.253.07:30:02.64/vb/04,04,usb,yes,30,30 2006.253.07:30:02.64/vb/05,04,usb,yes,28,32 2006.253.07:30:02.64/vb/06,04,usb,yes,29,32 2006.253.07:30:02.64/vb/07,04,usb,yes,31,31 2006.253.07:30:02.64/vb/08,04,usb,yes,29,32 2006.253.07:30:02.88/vblo/01,632.99,yes,locked 2006.253.07:30:02.88/vblo/02,640.99,yes,locked 2006.253.07:30:02.88/vblo/03,656.99,yes,locked 2006.253.07:30:02.88/vblo/04,712.99,yes,locked 2006.253.07:30:02.88/vblo/05,744.99,yes,locked 2006.253.07:30:02.88/vblo/06,752.99,yes,locked 2006.253.07:30:02.88/vblo/07,734.99,yes,locked 2006.253.07:30:02.88/vblo/08,744.99,yes,locked 2006.253.07:30:03.03/vabw/8 2006.253.07:30:03.18/vbbw/8 2006.253.07:30:03.29/xfe/off,on,14.7 2006.253.07:30:03.66/ifatt/23,28,28,28 2006.253.07:30:03.66&clockoff/"gps-fmout=1p 2006.253.07:30:03.66&clockoff/fmout-gps=1p 2006.253.07:30:04.08/fmout-gps/S +4.79E-07 2006.253.07:30:04.16:!2006.253.07:31:00 2006.253.07:31:00.01:data_valid=off 2006.253.07:31:00.01:postob 2006.253.07:31:00.02&postob/cable 2006.253.07:31:00.02&postob/wx 2006.253.07:31:00.02&postob/clockoff 2006.253.07:31:00.24/cable/+6.3697E-03 2006.253.07:31:00.24/wx/31.62,1006.3,72 2006.253.07:31:01.08/fmout-gps/S +4.78E-07 2006.253.07:31:01.08:scan_name=253-0733,k06253,80 2006.253.07:31:01.09:source=1219+044,122222.55,041315.8,2000.0,ccw 2006.253.07:31:01.13#flagr#flagr/antenna,new-source 2006.253.07:31:02.14:checkk5 2006.253.07:31:02.14&checkk5/chk_autoobs=1 2006.253.07:31:02.15&checkk5/chk_autoobs=2 2006.253.07:31:02.15&checkk5/chk_autoobs=3 2006.253.07:31:02.15&checkk5/chk_autoobs=4 2006.253.07:31:02.16&checkk5/chk_obsdata=1 2006.253.07:31:02.16&checkk5/chk_obsdata=2 2006.253.07:31:02.16&checkk5/chk_obsdata=3 2006.253.07:31:02.17&checkk5/chk_obsdata=4 2006.253.07:31:02.17&checkk5/k5log=1 2006.253.07:31:02.17&checkk5/k5log=2 2006.253.07:31:02.18&checkk5/k5log=3 2006.253.07:31:02.18&checkk5/k5log=4 2006.253.07:31:02.18&checkk5/obsinfo 2006.253.07:31:02.57/chk_autoobs//k5ts1/ autoobs is running! 2006.253.07:31:02.95/chk_autoobs//k5ts2/ autoobs is running! 2006.253.07:31:03.33/chk_autoobs//k5ts3/ autoobs is running! 2006.253.07:31:03.71/chk_autoobs//k5ts4/ autoobs is running! 2006.253.07:31:04.08/chk_obsdata//k5ts1/T2530730??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.07:31:04.45/chk_obsdata//k5ts2/T2530730??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.07:31:04.82/chk_obsdata//k5ts3/T2530730??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.07:31:05.19/chk_obsdata//k5ts4/T2530730??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.07:31:05.89/k5log//k5ts1_log_newline 2006.253.07:31:06.58/k5log//k5ts2_log_newline 2006.253.07:31:07.26/k5log//k5ts3_log_newline 2006.253.07:31:07.95/k5log//k5ts4_log_newline 2006.253.07:31:07.98/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.253.07:31:07.98:4f8m12a=1 2006.253.07:31:07.98$4f8m12a/echo=on 2006.253.07:31:07.98$4f8m12a/pcalon 2006.253.07:31:07.98$pcalon/"no phase cal control is implemented here 2006.253.07:31:07.98$4f8m12a/"tpicd=stop 2006.253.07:31:07.98$4f8m12a/vc4f8 2006.253.07:31:07.98$vc4f8/valo=1,532.99 2006.253.07:31:07.98#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.253.07:31:07.98#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.253.07:31:07.98#ibcon#ireg 17 cls_cnt 0 2006.253.07:31:07.98#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.253.07:31:07.98#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.253.07:31:07.98#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.253.07:31:07.98#ibcon#enter wrdev, iclass 17, count 0 2006.253.07:31:07.98#ibcon#first serial, iclass 17, count 0 2006.253.07:31:07.98#ibcon#enter sib2, iclass 17, count 0 2006.253.07:31:07.98#ibcon#flushed, iclass 17, count 0 2006.253.07:31:07.98#ibcon#about to write, iclass 17, count 0 2006.253.07:31:07.98#ibcon#wrote, iclass 17, count 0 2006.253.07:31:07.98#ibcon#about to read 3, iclass 17, count 0 2006.253.07:31:08.02#ibcon#read 3, iclass 17, count 0 2006.253.07:31:08.02#ibcon#about to read 4, iclass 17, count 0 2006.253.07:31:08.02#ibcon#read 4, iclass 17, count 0 2006.253.07:31:08.02#ibcon#about to read 5, iclass 17, count 0 2006.253.07:31:08.02#ibcon#read 5, iclass 17, count 0 2006.253.07:31:08.02#ibcon#about to read 6, iclass 17, count 0 2006.253.07:31:08.02#ibcon#read 6, iclass 17, count 0 2006.253.07:31:08.02#ibcon#end of sib2, iclass 17, count 0 2006.253.07:31:08.02#ibcon#*mode == 0, iclass 17, count 0 2006.253.07:31:08.02#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.253.07:31:08.02#ibcon#[26=FRQ=01,532.99\r\n] 2006.253.07:31:08.02#ibcon#*before write, iclass 17, count 0 2006.253.07:31:08.02#ibcon#enter sib2, iclass 17, count 0 2006.253.07:31:08.02#ibcon#flushed, iclass 17, count 0 2006.253.07:31:08.02#ibcon#about to write, iclass 17, count 0 2006.253.07:31:08.02#ibcon#wrote, iclass 17, count 0 2006.253.07:31:08.02#ibcon#about to read 3, iclass 17, count 0 2006.253.07:31:08.07#ibcon#read 3, iclass 17, count 0 2006.253.07:31:08.07#ibcon#about to read 4, iclass 17, count 0 2006.253.07:31:08.07#ibcon#read 4, iclass 17, count 0 2006.253.07:31:08.07#ibcon#about to read 5, iclass 17, count 0 2006.253.07:31:08.07#ibcon#read 5, iclass 17, count 0 2006.253.07:31:08.07#ibcon#about to read 6, iclass 17, count 0 2006.253.07:31:08.07#ibcon#read 6, iclass 17, count 0 2006.253.07:31:08.07#ibcon#end of sib2, iclass 17, count 0 2006.253.07:31:08.07#ibcon#*after write, iclass 17, count 0 2006.253.07:31:08.07#ibcon#*before return 0, iclass 17, count 0 2006.253.07:31:08.07#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.253.07:31:08.07#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.253.07:31:08.07#ibcon#about to clear, iclass 17 cls_cnt 0 2006.253.07:31:08.07#ibcon#cleared, iclass 17 cls_cnt 0 2006.253.07:31:08.07$vc4f8/va=1,8 2006.253.07:31:08.07#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.253.07:31:08.07#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.253.07:31:08.07#ibcon#ireg 11 cls_cnt 2 2006.253.07:31:08.07#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.253.07:31:08.07#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.253.07:31:08.07#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.253.07:31:08.07#ibcon#enter wrdev, iclass 19, count 2 2006.253.07:31:08.07#ibcon#first serial, iclass 19, count 2 2006.253.07:31:08.07#ibcon#enter sib2, iclass 19, count 2 2006.253.07:31:08.07#ibcon#flushed, iclass 19, count 2 2006.253.07:31:08.07#ibcon#about to write, iclass 19, count 2 2006.253.07:31:08.07#ibcon#wrote, iclass 19, count 2 2006.253.07:31:08.07#ibcon#about to read 3, iclass 19, count 2 2006.253.07:31:08.09#ibcon#read 3, iclass 19, count 2 2006.253.07:31:08.09#ibcon#about to read 4, iclass 19, count 2 2006.253.07:31:08.09#ibcon#read 4, iclass 19, count 2 2006.253.07:31:08.09#ibcon#about to read 5, iclass 19, count 2 2006.253.07:31:08.09#ibcon#read 5, iclass 19, count 2 2006.253.07:31:08.09#ibcon#about to read 6, iclass 19, count 2 2006.253.07:31:08.09#ibcon#read 6, iclass 19, count 2 2006.253.07:31:08.09#ibcon#end of sib2, iclass 19, count 2 2006.253.07:31:08.09#ibcon#*mode == 0, iclass 19, count 2 2006.253.07:31:08.09#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.253.07:31:08.09#ibcon#[25=AT01-08\r\n] 2006.253.07:31:08.09#ibcon#*before write, iclass 19, count 2 2006.253.07:31:08.09#ibcon#enter sib2, iclass 19, count 2 2006.253.07:31:08.09#ibcon#flushed, iclass 19, count 2 2006.253.07:31:08.09#ibcon#about to write, iclass 19, count 2 2006.253.07:31:08.09#ibcon#wrote, iclass 19, count 2 2006.253.07:31:08.09#ibcon#about to read 3, iclass 19, count 2 2006.253.07:31:08.12#ibcon#read 3, iclass 19, count 2 2006.253.07:31:08.12#ibcon#about to read 4, iclass 19, count 2 2006.253.07:31:08.12#ibcon#read 4, iclass 19, count 2 2006.253.07:31:08.12#ibcon#about to read 5, iclass 19, count 2 2006.253.07:31:08.12#ibcon#read 5, iclass 19, count 2 2006.253.07:31:08.12#ibcon#about to read 6, iclass 19, count 2 2006.253.07:31:08.12#ibcon#read 6, iclass 19, count 2 2006.253.07:31:08.12#ibcon#end of sib2, iclass 19, count 2 2006.253.07:31:08.12#ibcon#*after write, iclass 19, count 2 2006.253.07:31:08.12#ibcon#*before return 0, iclass 19, count 2 2006.253.07:31:08.12#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.253.07:31:08.12#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.253.07:31:08.12#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.253.07:31:08.12#ibcon#ireg 7 cls_cnt 0 2006.253.07:31:08.12#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.253.07:31:08.24#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.253.07:31:08.24#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.253.07:31:08.24#ibcon#enter wrdev, iclass 19, count 0 2006.253.07:31:08.24#ibcon#first serial, iclass 19, count 0 2006.253.07:31:08.24#ibcon#enter sib2, iclass 19, count 0 2006.253.07:31:08.24#ibcon#flushed, iclass 19, count 0 2006.253.07:31:08.24#ibcon#about to write, iclass 19, count 0 2006.253.07:31:08.24#ibcon#wrote, iclass 19, count 0 2006.253.07:31:08.24#ibcon#about to read 3, iclass 19, count 0 2006.253.07:31:08.26#ibcon#read 3, iclass 19, count 0 2006.253.07:31:08.26#ibcon#about to read 4, iclass 19, count 0 2006.253.07:31:08.26#ibcon#read 4, iclass 19, count 0 2006.253.07:31:08.26#ibcon#about to read 5, iclass 19, count 0 2006.253.07:31:08.26#ibcon#read 5, iclass 19, count 0 2006.253.07:31:08.26#ibcon#about to read 6, iclass 19, count 0 2006.253.07:31:08.26#ibcon#read 6, iclass 19, count 0 2006.253.07:31:08.26#ibcon#end of sib2, iclass 19, count 0 2006.253.07:31:08.26#ibcon#*mode == 0, iclass 19, count 0 2006.253.07:31:08.26#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.253.07:31:08.26#ibcon#[25=USB\r\n] 2006.253.07:31:08.26#ibcon#*before write, iclass 19, count 0 2006.253.07:31:08.26#ibcon#enter sib2, iclass 19, count 0 2006.253.07:31:08.26#ibcon#flushed, iclass 19, count 0 2006.253.07:31:08.26#ibcon#about to write, iclass 19, count 0 2006.253.07:31:08.26#ibcon#wrote, iclass 19, count 0 2006.253.07:31:08.26#ibcon#about to read 3, iclass 19, count 0 2006.253.07:31:08.29#ibcon#read 3, iclass 19, count 0 2006.253.07:31:08.29#ibcon#about to read 4, iclass 19, count 0 2006.253.07:31:08.29#ibcon#read 4, iclass 19, count 0 2006.253.07:31:08.29#ibcon#about to read 5, iclass 19, count 0 2006.253.07:31:08.29#ibcon#read 5, iclass 19, count 0 2006.253.07:31:08.29#ibcon#about to read 6, iclass 19, count 0 2006.253.07:31:08.29#ibcon#read 6, iclass 19, count 0 2006.253.07:31:08.29#ibcon#end of sib2, iclass 19, count 0 2006.253.07:31:08.29#ibcon#*after write, iclass 19, count 0 2006.253.07:31:08.29#ibcon#*before return 0, iclass 19, count 0 2006.253.07:31:08.29#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.253.07:31:08.29#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.253.07:31:08.29#ibcon#about to clear, iclass 19 cls_cnt 0 2006.253.07:31:08.29#ibcon#cleared, iclass 19 cls_cnt 0 2006.253.07:31:08.29$vc4f8/valo=2,572.99 2006.253.07:31:08.29#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.253.07:31:08.29#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.253.07:31:08.29#ibcon#ireg 17 cls_cnt 0 2006.253.07:31:08.29#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.253.07:31:08.29#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.253.07:31:08.29#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.253.07:31:08.29#ibcon#enter wrdev, iclass 21, count 0 2006.253.07:31:08.29#ibcon#first serial, iclass 21, count 0 2006.253.07:31:08.29#ibcon#enter sib2, iclass 21, count 0 2006.253.07:31:08.29#ibcon#flushed, iclass 21, count 0 2006.253.07:31:08.29#ibcon#about to write, iclass 21, count 0 2006.253.07:31:08.29#ibcon#wrote, iclass 21, count 0 2006.253.07:31:08.29#ibcon#about to read 3, iclass 21, count 0 2006.253.07:31:08.32#ibcon#read 3, iclass 21, count 0 2006.253.07:31:08.32#ibcon#about to read 4, iclass 21, count 0 2006.253.07:31:08.32#ibcon#read 4, iclass 21, count 0 2006.253.07:31:08.32#ibcon#about to read 5, iclass 21, count 0 2006.253.07:31:08.32#ibcon#read 5, iclass 21, count 0 2006.253.07:31:08.32#ibcon#about to read 6, iclass 21, count 0 2006.253.07:31:08.32#ibcon#read 6, iclass 21, count 0 2006.253.07:31:08.32#ibcon#end of sib2, iclass 21, count 0 2006.253.07:31:08.32#ibcon#*mode == 0, iclass 21, count 0 2006.253.07:31:08.32#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.253.07:31:08.32#ibcon#[26=FRQ=02,572.99\r\n] 2006.253.07:31:08.32#ibcon#*before write, iclass 21, count 0 2006.253.07:31:08.32#ibcon#enter sib2, iclass 21, count 0 2006.253.07:31:08.32#ibcon#flushed, iclass 21, count 0 2006.253.07:31:08.32#ibcon#about to write, iclass 21, count 0 2006.253.07:31:08.32#ibcon#wrote, iclass 21, count 0 2006.253.07:31:08.32#ibcon#about to read 3, iclass 21, count 0 2006.253.07:31:08.36#ibcon#read 3, iclass 21, count 0 2006.253.07:31:08.36#ibcon#about to read 4, iclass 21, count 0 2006.253.07:31:08.36#ibcon#read 4, iclass 21, count 0 2006.253.07:31:08.36#ibcon#about to read 5, iclass 21, count 0 2006.253.07:31:08.36#ibcon#read 5, iclass 21, count 0 2006.253.07:31:08.36#ibcon#about to read 6, iclass 21, count 0 2006.253.07:31:08.36#ibcon#read 6, iclass 21, count 0 2006.253.07:31:08.36#ibcon#end of sib2, iclass 21, count 0 2006.253.07:31:08.36#ibcon#*after write, iclass 21, count 0 2006.253.07:31:08.36#ibcon#*before return 0, iclass 21, count 0 2006.253.07:31:08.36#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.253.07:31:08.36#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.253.07:31:08.36#ibcon#about to clear, iclass 21 cls_cnt 0 2006.253.07:31:08.36#ibcon#cleared, iclass 21 cls_cnt 0 2006.253.07:31:08.36$vc4f8/va=2,7 2006.253.07:31:08.36#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.253.07:31:08.36#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.253.07:31:08.36#ibcon#ireg 11 cls_cnt 2 2006.253.07:31:08.36#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.253.07:31:08.41#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.253.07:31:08.41#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.253.07:31:08.41#ibcon#enter wrdev, iclass 23, count 2 2006.253.07:31:08.41#ibcon#first serial, iclass 23, count 2 2006.253.07:31:08.41#ibcon#enter sib2, iclass 23, count 2 2006.253.07:31:08.41#ibcon#flushed, iclass 23, count 2 2006.253.07:31:08.41#ibcon#about to write, iclass 23, count 2 2006.253.07:31:08.41#ibcon#wrote, iclass 23, count 2 2006.253.07:31:08.41#ibcon#about to read 3, iclass 23, count 2 2006.253.07:31:08.43#ibcon#read 3, iclass 23, count 2 2006.253.07:31:08.43#ibcon#about to read 4, iclass 23, count 2 2006.253.07:31:08.43#ibcon#read 4, iclass 23, count 2 2006.253.07:31:08.43#ibcon#about to read 5, iclass 23, count 2 2006.253.07:31:08.43#ibcon#read 5, iclass 23, count 2 2006.253.07:31:08.43#ibcon#about to read 6, iclass 23, count 2 2006.253.07:31:08.43#ibcon#read 6, iclass 23, count 2 2006.253.07:31:08.43#ibcon#end of sib2, iclass 23, count 2 2006.253.07:31:08.43#ibcon#*mode == 0, iclass 23, count 2 2006.253.07:31:08.43#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.253.07:31:08.43#ibcon#[25=AT02-07\r\n] 2006.253.07:31:08.43#ibcon#*before write, iclass 23, count 2 2006.253.07:31:08.43#ibcon#enter sib2, iclass 23, count 2 2006.253.07:31:08.43#ibcon#flushed, iclass 23, count 2 2006.253.07:31:08.43#ibcon#about to write, iclass 23, count 2 2006.253.07:31:08.43#ibcon#wrote, iclass 23, count 2 2006.253.07:31:08.43#ibcon#about to read 3, iclass 23, count 2 2006.253.07:31:08.46#ibcon#read 3, iclass 23, count 2 2006.253.07:31:08.46#ibcon#about to read 4, iclass 23, count 2 2006.253.07:31:08.46#ibcon#read 4, iclass 23, count 2 2006.253.07:31:08.46#ibcon#about to read 5, iclass 23, count 2 2006.253.07:31:08.46#ibcon#read 5, iclass 23, count 2 2006.253.07:31:08.46#ibcon#about to read 6, iclass 23, count 2 2006.253.07:31:08.46#ibcon#read 6, iclass 23, count 2 2006.253.07:31:08.46#ibcon#end of sib2, iclass 23, count 2 2006.253.07:31:08.46#ibcon#*after write, iclass 23, count 2 2006.253.07:31:08.46#ibcon#*before return 0, iclass 23, count 2 2006.253.07:31:08.46#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.253.07:31:08.46#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.253.07:31:08.46#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.253.07:31:08.46#ibcon#ireg 7 cls_cnt 0 2006.253.07:31:08.46#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.253.07:31:08.58#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.253.07:31:08.58#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.253.07:31:08.58#ibcon#enter wrdev, iclass 23, count 0 2006.253.07:31:08.58#ibcon#first serial, iclass 23, count 0 2006.253.07:31:08.58#ibcon#enter sib2, iclass 23, count 0 2006.253.07:31:08.58#ibcon#flushed, iclass 23, count 0 2006.253.07:31:08.58#ibcon#about to write, iclass 23, count 0 2006.253.07:31:08.58#ibcon#wrote, iclass 23, count 0 2006.253.07:31:08.58#ibcon#about to read 3, iclass 23, count 0 2006.253.07:31:08.60#ibcon#read 3, iclass 23, count 0 2006.253.07:31:08.60#ibcon#about to read 4, iclass 23, count 0 2006.253.07:31:08.60#ibcon#read 4, iclass 23, count 0 2006.253.07:31:08.60#ibcon#about to read 5, iclass 23, count 0 2006.253.07:31:08.60#ibcon#read 5, iclass 23, count 0 2006.253.07:31:08.60#ibcon#about to read 6, iclass 23, count 0 2006.253.07:31:08.60#ibcon#read 6, iclass 23, count 0 2006.253.07:31:08.60#ibcon#end of sib2, iclass 23, count 0 2006.253.07:31:08.60#ibcon#*mode == 0, iclass 23, count 0 2006.253.07:31:08.60#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.253.07:31:08.60#ibcon#[25=USB\r\n] 2006.253.07:31:08.60#ibcon#*before write, iclass 23, count 0 2006.253.07:31:08.60#ibcon#enter sib2, iclass 23, count 0 2006.253.07:31:08.60#ibcon#flushed, iclass 23, count 0 2006.253.07:31:08.60#ibcon#about to write, iclass 23, count 0 2006.253.07:31:08.60#ibcon#wrote, iclass 23, count 0 2006.253.07:31:08.60#ibcon#about to read 3, iclass 23, count 0 2006.253.07:31:08.63#ibcon#read 3, iclass 23, count 0 2006.253.07:31:08.63#ibcon#about to read 4, iclass 23, count 0 2006.253.07:31:08.63#ibcon#read 4, iclass 23, count 0 2006.253.07:31:08.63#ibcon#about to read 5, iclass 23, count 0 2006.253.07:31:08.63#ibcon#read 5, iclass 23, count 0 2006.253.07:31:08.63#ibcon#about to read 6, iclass 23, count 0 2006.253.07:31:08.63#ibcon#read 6, iclass 23, count 0 2006.253.07:31:08.63#ibcon#end of sib2, iclass 23, count 0 2006.253.07:31:08.63#ibcon#*after write, iclass 23, count 0 2006.253.07:31:08.63#ibcon#*before return 0, iclass 23, count 0 2006.253.07:31:08.63#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.253.07:31:08.63#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.253.07:31:08.63#ibcon#about to clear, iclass 23 cls_cnt 0 2006.253.07:31:08.63#ibcon#cleared, iclass 23 cls_cnt 0 2006.253.07:31:08.63$vc4f8/valo=3,672.99 2006.253.07:31:08.63#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.253.07:31:08.63#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.253.07:31:08.63#ibcon#ireg 17 cls_cnt 0 2006.253.07:31:08.63#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.253.07:31:08.63#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.253.07:31:08.63#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.253.07:31:08.63#ibcon#enter wrdev, iclass 25, count 0 2006.253.07:31:08.63#ibcon#first serial, iclass 25, count 0 2006.253.07:31:08.63#ibcon#enter sib2, iclass 25, count 0 2006.253.07:31:08.63#ibcon#flushed, iclass 25, count 0 2006.253.07:31:08.63#ibcon#about to write, iclass 25, count 0 2006.253.07:31:08.63#ibcon#wrote, iclass 25, count 0 2006.253.07:31:08.63#ibcon#about to read 3, iclass 25, count 0 2006.253.07:31:08.66#ibcon#read 3, iclass 25, count 0 2006.253.07:31:08.66#ibcon#about to read 4, iclass 25, count 0 2006.253.07:31:08.66#ibcon#read 4, iclass 25, count 0 2006.253.07:31:08.66#ibcon#about to read 5, iclass 25, count 0 2006.253.07:31:08.66#ibcon#read 5, iclass 25, count 0 2006.253.07:31:08.66#ibcon#about to read 6, iclass 25, count 0 2006.253.07:31:08.66#ibcon#read 6, iclass 25, count 0 2006.253.07:31:08.66#ibcon#end of sib2, iclass 25, count 0 2006.253.07:31:08.66#ibcon#*mode == 0, iclass 25, count 0 2006.253.07:31:08.66#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.253.07:31:08.66#ibcon#[26=FRQ=03,672.99\r\n] 2006.253.07:31:08.66#ibcon#*before write, iclass 25, count 0 2006.253.07:31:08.66#ibcon#enter sib2, iclass 25, count 0 2006.253.07:31:08.66#ibcon#flushed, iclass 25, count 0 2006.253.07:31:08.66#ibcon#about to write, iclass 25, count 0 2006.253.07:31:08.66#ibcon#wrote, iclass 25, count 0 2006.253.07:31:08.66#ibcon#about to read 3, iclass 25, count 0 2006.253.07:31:08.70#ibcon#read 3, iclass 25, count 0 2006.253.07:31:08.70#ibcon#about to read 4, iclass 25, count 0 2006.253.07:31:08.70#ibcon#read 4, iclass 25, count 0 2006.253.07:31:08.70#ibcon#about to read 5, iclass 25, count 0 2006.253.07:31:08.70#ibcon#read 5, iclass 25, count 0 2006.253.07:31:08.70#ibcon#about to read 6, iclass 25, count 0 2006.253.07:31:08.70#ibcon#read 6, iclass 25, count 0 2006.253.07:31:08.70#ibcon#end of sib2, iclass 25, count 0 2006.253.07:31:08.70#ibcon#*after write, iclass 25, count 0 2006.253.07:31:08.70#ibcon#*before return 0, iclass 25, count 0 2006.253.07:31:08.70#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.253.07:31:08.70#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.253.07:31:08.70#ibcon#about to clear, iclass 25 cls_cnt 0 2006.253.07:31:08.70#ibcon#cleared, iclass 25 cls_cnt 0 2006.253.07:31:08.70$vc4f8/va=3,6 2006.253.07:31:08.70#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.253.07:31:08.70#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.253.07:31:08.70#ibcon#ireg 11 cls_cnt 2 2006.253.07:31:08.70#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.253.07:31:08.75#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.253.07:31:08.75#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.253.07:31:08.75#ibcon#enter wrdev, iclass 27, count 2 2006.253.07:31:08.75#ibcon#first serial, iclass 27, count 2 2006.253.07:31:08.75#ibcon#enter sib2, iclass 27, count 2 2006.253.07:31:08.75#ibcon#flushed, iclass 27, count 2 2006.253.07:31:08.75#ibcon#about to write, iclass 27, count 2 2006.253.07:31:08.75#ibcon#wrote, iclass 27, count 2 2006.253.07:31:08.75#ibcon#about to read 3, iclass 27, count 2 2006.253.07:31:08.77#ibcon#read 3, iclass 27, count 2 2006.253.07:31:08.77#ibcon#about to read 4, iclass 27, count 2 2006.253.07:31:08.77#ibcon#read 4, iclass 27, count 2 2006.253.07:31:08.77#ibcon#about to read 5, iclass 27, count 2 2006.253.07:31:08.77#ibcon#read 5, iclass 27, count 2 2006.253.07:31:08.77#ibcon#about to read 6, iclass 27, count 2 2006.253.07:31:08.77#ibcon#read 6, iclass 27, count 2 2006.253.07:31:08.77#ibcon#end of sib2, iclass 27, count 2 2006.253.07:31:08.77#ibcon#*mode == 0, iclass 27, count 2 2006.253.07:31:08.77#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.253.07:31:08.77#ibcon#[25=AT03-06\r\n] 2006.253.07:31:08.77#ibcon#*before write, iclass 27, count 2 2006.253.07:31:08.77#ibcon#enter sib2, iclass 27, count 2 2006.253.07:31:08.77#ibcon#flushed, iclass 27, count 2 2006.253.07:31:08.77#ibcon#about to write, iclass 27, count 2 2006.253.07:31:08.77#ibcon#wrote, iclass 27, count 2 2006.253.07:31:08.77#ibcon#about to read 3, iclass 27, count 2 2006.253.07:31:08.80#ibcon#read 3, iclass 27, count 2 2006.253.07:31:08.80#ibcon#about to read 4, iclass 27, count 2 2006.253.07:31:08.80#ibcon#read 4, iclass 27, count 2 2006.253.07:31:08.80#ibcon#about to read 5, iclass 27, count 2 2006.253.07:31:08.80#ibcon#read 5, iclass 27, count 2 2006.253.07:31:08.80#ibcon#about to read 6, iclass 27, count 2 2006.253.07:31:08.80#ibcon#read 6, iclass 27, count 2 2006.253.07:31:08.80#ibcon#end of sib2, iclass 27, count 2 2006.253.07:31:08.80#ibcon#*after write, iclass 27, count 2 2006.253.07:31:08.80#ibcon#*before return 0, iclass 27, count 2 2006.253.07:31:08.80#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.253.07:31:08.80#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.253.07:31:08.80#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.253.07:31:08.80#ibcon#ireg 7 cls_cnt 0 2006.253.07:31:08.80#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.253.07:31:08.92#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.253.07:31:08.92#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.253.07:31:08.92#ibcon#enter wrdev, iclass 27, count 0 2006.253.07:31:08.92#ibcon#first serial, iclass 27, count 0 2006.253.07:31:08.92#ibcon#enter sib2, iclass 27, count 0 2006.253.07:31:08.92#ibcon#flushed, iclass 27, count 0 2006.253.07:31:08.92#ibcon#about to write, iclass 27, count 0 2006.253.07:31:08.92#ibcon#wrote, iclass 27, count 0 2006.253.07:31:08.92#ibcon#about to read 3, iclass 27, count 0 2006.253.07:31:08.94#ibcon#read 3, iclass 27, count 0 2006.253.07:31:08.94#ibcon#about to read 4, iclass 27, count 0 2006.253.07:31:08.94#ibcon#read 4, iclass 27, count 0 2006.253.07:31:08.94#ibcon#about to read 5, iclass 27, count 0 2006.253.07:31:08.94#ibcon#read 5, iclass 27, count 0 2006.253.07:31:08.94#ibcon#about to read 6, iclass 27, count 0 2006.253.07:31:08.94#ibcon#read 6, iclass 27, count 0 2006.253.07:31:08.94#ibcon#end of sib2, iclass 27, count 0 2006.253.07:31:08.94#ibcon#*mode == 0, iclass 27, count 0 2006.253.07:31:08.94#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.253.07:31:08.94#ibcon#[25=USB\r\n] 2006.253.07:31:08.94#ibcon#*before write, iclass 27, count 0 2006.253.07:31:08.94#ibcon#enter sib2, iclass 27, count 0 2006.253.07:31:08.94#ibcon#flushed, iclass 27, count 0 2006.253.07:31:08.94#ibcon#about to write, iclass 27, count 0 2006.253.07:31:08.94#ibcon#wrote, iclass 27, count 0 2006.253.07:31:08.94#ibcon#about to read 3, iclass 27, count 0 2006.253.07:31:08.97#ibcon#read 3, iclass 27, count 0 2006.253.07:31:08.97#ibcon#about to read 4, iclass 27, count 0 2006.253.07:31:08.97#ibcon#read 4, iclass 27, count 0 2006.253.07:31:08.97#ibcon#about to read 5, iclass 27, count 0 2006.253.07:31:08.97#ibcon#read 5, iclass 27, count 0 2006.253.07:31:08.97#ibcon#about to read 6, iclass 27, count 0 2006.253.07:31:08.97#ibcon#read 6, iclass 27, count 0 2006.253.07:31:08.97#ibcon#end of sib2, iclass 27, count 0 2006.253.07:31:08.97#ibcon#*after write, iclass 27, count 0 2006.253.07:31:08.97#ibcon#*before return 0, iclass 27, count 0 2006.253.07:31:08.97#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.253.07:31:08.97#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.253.07:31:08.97#ibcon#about to clear, iclass 27 cls_cnt 0 2006.253.07:31:08.97#ibcon#cleared, iclass 27 cls_cnt 0 2006.253.07:31:08.97$vc4f8/valo=4,832.99 2006.253.07:31:08.97#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.253.07:31:08.97#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.253.07:31:08.97#ibcon#ireg 17 cls_cnt 0 2006.253.07:31:08.97#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.253.07:31:08.97#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.253.07:31:08.97#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.253.07:31:08.97#ibcon#enter wrdev, iclass 29, count 0 2006.253.07:31:08.97#ibcon#first serial, iclass 29, count 0 2006.253.07:31:08.97#ibcon#enter sib2, iclass 29, count 0 2006.253.07:31:08.97#ibcon#flushed, iclass 29, count 0 2006.253.07:31:08.97#ibcon#about to write, iclass 29, count 0 2006.253.07:31:08.97#ibcon#wrote, iclass 29, count 0 2006.253.07:31:08.97#ibcon#about to read 3, iclass 29, count 0 2006.253.07:31:09.00#ibcon#read 3, iclass 29, count 0 2006.253.07:31:09.00#ibcon#about to read 4, iclass 29, count 0 2006.253.07:31:09.00#ibcon#read 4, iclass 29, count 0 2006.253.07:31:09.00#ibcon#about to read 5, iclass 29, count 0 2006.253.07:31:09.00#ibcon#read 5, iclass 29, count 0 2006.253.07:31:09.00#ibcon#about to read 6, iclass 29, count 0 2006.253.07:31:09.00#ibcon#read 6, iclass 29, count 0 2006.253.07:31:09.00#ibcon#end of sib2, iclass 29, count 0 2006.253.07:31:09.00#ibcon#*mode == 0, iclass 29, count 0 2006.253.07:31:09.00#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.253.07:31:09.00#ibcon#[26=FRQ=04,832.99\r\n] 2006.253.07:31:09.00#ibcon#*before write, iclass 29, count 0 2006.253.07:31:09.00#ibcon#enter sib2, iclass 29, count 0 2006.253.07:31:09.00#ibcon#flushed, iclass 29, count 0 2006.253.07:31:09.00#ibcon#about to write, iclass 29, count 0 2006.253.07:31:09.00#ibcon#wrote, iclass 29, count 0 2006.253.07:31:09.00#ibcon#about to read 3, iclass 29, count 0 2006.253.07:31:09.04#ibcon#read 3, iclass 29, count 0 2006.253.07:31:09.04#ibcon#about to read 4, iclass 29, count 0 2006.253.07:31:09.04#ibcon#read 4, iclass 29, count 0 2006.253.07:31:09.04#ibcon#about to read 5, iclass 29, count 0 2006.253.07:31:09.04#ibcon#read 5, iclass 29, count 0 2006.253.07:31:09.04#ibcon#about to read 6, iclass 29, count 0 2006.253.07:31:09.04#ibcon#read 6, iclass 29, count 0 2006.253.07:31:09.04#ibcon#end of sib2, iclass 29, count 0 2006.253.07:31:09.04#ibcon#*after write, iclass 29, count 0 2006.253.07:31:09.04#ibcon#*before return 0, iclass 29, count 0 2006.253.07:31:09.04#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.253.07:31:09.04#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.253.07:31:09.04#ibcon#about to clear, iclass 29 cls_cnt 0 2006.253.07:31:09.04#ibcon#cleared, iclass 29 cls_cnt 0 2006.253.07:31:09.04$vc4f8/va=4,7 2006.253.07:31:09.04#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.253.07:31:09.04#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.253.07:31:09.04#ibcon#ireg 11 cls_cnt 2 2006.253.07:31:09.04#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.253.07:31:09.09#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.253.07:31:09.09#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.253.07:31:09.09#ibcon#enter wrdev, iclass 31, count 2 2006.253.07:31:09.09#ibcon#first serial, iclass 31, count 2 2006.253.07:31:09.09#ibcon#enter sib2, iclass 31, count 2 2006.253.07:31:09.09#ibcon#flushed, iclass 31, count 2 2006.253.07:31:09.09#ibcon#about to write, iclass 31, count 2 2006.253.07:31:09.09#ibcon#wrote, iclass 31, count 2 2006.253.07:31:09.09#ibcon#about to read 3, iclass 31, count 2 2006.253.07:31:09.11#ibcon#read 3, iclass 31, count 2 2006.253.07:31:09.11#ibcon#about to read 4, iclass 31, count 2 2006.253.07:31:09.11#ibcon#read 4, iclass 31, count 2 2006.253.07:31:09.11#ibcon#about to read 5, iclass 31, count 2 2006.253.07:31:09.11#ibcon#read 5, iclass 31, count 2 2006.253.07:31:09.11#ibcon#about to read 6, iclass 31, count 2 2006.253.07:31:09.11#ibcon#read 6, iclass 31, count 2 2006.253.07:31:09.11#ibcon#end of sib2, iclass 31, count 2 2006.253.07:31:09.11#ibcon#*mode == 0, iclass 31, count 2 2006.253.07:31:09.11#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.253.07:31:09.11#ibcon#[25=AT04-07\r\n] 2006.253.07:31:09.11#ibcon#*before write, iclass 31, count 2 2006.253.07:31:09.11#ibcon#enter sib2, iclass 31, count 2 2006.253.07:31:09.11#ibcon#flushed, iclass 31, count 2 2006.253.07:31:09.11#ibcon#about to write, iclass 31, count 2 2006.253.07:31:09.11#ibcon#wrote, iclass 31, count 2 2006.253.07:31:09.11#ibcon#about to read 3, iclass 31, count 2 2006.253.07:31:09.14#ibcon#read 3, iclass 31, count 2 2006.253.07:31:09.14#ibcon#about to read 4, iclass 31, count 2 2006.253.07:31:09.14#ibcon#read 4, iclass 31, count 2 2006.253.07:31:09.14#ibcon#about to read 5, iclass 31, count 2 2006.253.07:31:09.14#ibcon#read 5, iclass 31, count 2 2006.253.07:31:09.14#ibcon#about to read 6, iclass 31, count 2 2006.253.07:31:09.14#ibcon#read 6, iclass 31, count 2 2006.253.07:31:09.14#ibcon#end of sib2, iclass 31, count 2 2006.253.07:31:09.14#ibcon#*after write, iclass 31, count 2 2006.253.07:31:09.14#ibcon#*before return 0, iclass 31, count 2 2006.253.07:31:09.14#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.253.07:31:09.14#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.253.07:31:09.14#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.253.07:31:09.14#ibcon#ireg 7 cls_cnt 0 2006.253.07:31:09.14#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.253.07:31:09.26#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.253.07:31:09.26#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.253.07:31:09.26#ibcon#enter wrdev, iclass 31, count 0 2006.253.07:31:09.26#ibcon#first serial, iclass 31, count 0 2006.253.07:31:09.26#ibcon#enter sib2, iclass 31, count 0 2006.253.07:31:09.26#ibcon#flushed, iclass 31, count 0 2006.253.07:31:09.26#ibcon#about to write, iclass 31, count 0 2006.253.07:31:09.26#ibcon#wrote, iclass 31, count 0 2006.253.07:31:09.26#ibcon#about to read 3, iclass 31, count 0 2006.253.07:31:09.28#ibcon#read 3, iclass 31, count 0 2006.253.07:31:09.28#ibcon#about to read 4, iclass 31, count 0 2006.253.07:31:09.28#ibcon#read 4, iclass 31, count 0 2006.253.07:31:09.28#ibcon#about to read 5, iclass 31, count 0 2006.253.07:31:09.28#ibcon#read 5, iclass 31, count 0 2006.253.07:31:09.28#ibcon#about to read 6, iclass 31, count 0 2006.253.07:31:09.28#ibcon#read 6, iclass 31, count 0 2006.253.07:31:09.28#ibcon#end of sib2, iclass 31, count 0 2006.253.07:31:09.28#ibcon#*mode == 0, iclass 31, count 0 2006.253.07:31:09.28#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.253.07:31:09.28#ibcon#[25=USB\r\n] 2006.253.07:31:09.28#ibcon#*before write, iclass 31, count 0 2006.253.07:31:09.28#ibcon#enter sib2, iclass 31, count 0 2006.253.07:31:09.28#ibcon#flushed, iclass 31, count 0 2006.253.07:31:09.28#ibcon#about to write, iclass 31, count 0 2006.253.07:31:09.28#ibcon#wrote, iclass 31, count 0 2006.253.07:31:09.28#ibcon#about to read 3, iclass 31, count 0 2006.253.07:31:09.31#ibcon#read 3, iclass 31, count 0 2006.253.07:31:09.31#ibcon#about to read 4, iclass 31, count 0 2006.253.07:31:09.31#ibcon#read 4, iclass 31, count 0 2006.253.07:31:09.31#ibcon#about to read 5, iclass 31, count 0 2006.253.07:31:09.31#ibcon#read 5, iclass 31, count 0 2006.253.07:31:09.31#ibcon#about to read 6, iclass 31, count 0 2006.253.07:31:09.31#ibcon#read 6, iclass 31, count 0 2006.253.07:31:09.31#ibcon#end of sib2, iclass 31, count 0 2006.253.07:31:09.31#ibcon#*after write, iclass 31, count 0 2006.253.07:31:09.31#ibcon#*before return 0, iclass 31, count 0 2006.253.07:31:09.31#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.253.07:31:09.31#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.253.07:31:09.31#ibcon#about to clear, iclass 31 cls_cnt 0 2006.253.07:31:09.31#ibcon#cleared, iclass 31 cls_cnt 0 2006.253.07:31:09.31$vc4f8/valo=5,652.99 2006.253.07:31:09.31#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.253.07:31:09.31#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.253.07:31:09.31#ibcon#ireg 17 cls_cnt 0 2006.253.07:31:09.31#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.253.07:31:09.31#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.253.07:31:09.31#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.253.07:31:09.31#ibcon#enter wrdev, iclass 33, count 0 2006.253.07:31:09.31#ibcon#first serial, iclass 33, count 0 2006.253.07:31:09.31#ibcon#enter sib2, iclass 33, count 0 2006.253.07:31:09.31#ibcon#flushed, iclass 33, count 0 2006.253.07:31:09.31#ibcon#about to write, iclass 33, count 0 2006.253.07:31:09.31#ibcon#wrote, iclass 33, count 0 2006.253.07:31:09.31#ibcon#about to read 3, iclass 33, count 0 2006.253.07:31:09.34#ibcon#read 3, iclass 33, count 0 2006.253.07:31:09.34#ibcon#about to read 4, iclass 33, count 0 2006.253.07:31:09.34#ibcon#read 4, iclass 33, count 0 2006.253.07:31:09.34#ibcon#about to read 5, iclass 33, count 0 2006.253.07:31:09.34#ibcon#read 5, iclass 33, count 0 2006.253.07:31:09.34#ibcon#about to read 6, iclass 33, count 0 2006.253.07:31:09.34#ibcon#read 6, iclass 33, count 0 2006.253.07:31:09.34#ibcon#end of sib2, iclass 33, count 0 2006.253.07:31:09.34#ibcon#*mode == 0, iclass 33, count 0 2006.253.07:31:09.34#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.253.07:31:09.34#ibcon#[26=FRQ=05,652.99\r\n] 2006.253.07:31:09.34#ibcon#*before write, iclass 33, count 0 2006.253.07:31:09.34#ibcon#enter sib2, iclass 33, count 0 2006.253.07:31:09.34#ibcon#flushed, iclass 33, count 0 2006.253.07:31:09.34#ibcon#about to write, iclass 33, count 0 2006.253.07:31:09.34#ibcon#wrote, iclass 33, count 0 2006.253.07:31:09.34#ibcon#about to read 3, iclass 33, count 0 2006.253.07:31:09.38#ibcon#read 3, iclass 33, count 0 2006.253.07:31:09.38#ibcon#about to read 4, iclass 33, count 0 2006.253.07:31:09.38#ibcon#read 4, iclass 33, count 0 2006.253.07:31:09.38#ibcon#about to read 5, iclass 33, count 0 2006.253.07:31:09.38#ibcon#read 5, iclass 33, count 0 2006.253.07:31:09.38#ibcon#about to read 6, iclass 33, count 0 2006.253.07:31:09.38#ibcon#read 6, iclass 33, count 0 2006.253.07:31:09.38#ibcon#end of sib2, iclass 33, count 0 2006.253.07:31:09.38#ibcon#*after write, iclass 33, count 0 2006.253.07:31:09.38#ibcon#*before return 0, iclass 33, count 0 2006.253.07:31:09.38#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.253.07:31:09.38#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.253.07:31:09.38#ibcon#about to clear, iclass 33 cls_cnt 0 2006.253.07:31:09.38#ibcon#cleared, iclass 33 cls_cnt 0 2006.253.07:31:09.38$vc4f8/va=5,7 2006.253.07:31:09.38#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.253.07:31:09.38#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.253.07:31:09.38#ibcon#ireg 11 cls_cnt 2 2006.253.07:31:09.38#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.253.07:31:09.43#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.253.07:31:09.43#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.253.07:31:09.43#ibcon#enter wrdev, iclass 35, count 2 2006.253.07:31:09.43#ibcon#first serial, iclass 35, count 2 2006.253.07:31:09.43#ibcon#enter sib2, iclass 35, count 2 2006.253.07:31:09.43#ibcon#flushed, iclass 35, count 2 2006.253.07:31:09.43#ibcon#about to write, iclass 35, count 2 2006.253.07:31:09.43#ibcon#wrote, iclass 35, count 2 2006.253.07:31:09.43#ibcon#about to read 3, iclass 35, count 2 2006.253.07:31:09.45#ibcon#read 3, iclass 35, count 2 2006.253.07:31:09.45#ibcon#about to read 4, iclass 35, count 2 2006.253.07:31:09.45#ibcon#read 4, iclass 35, count 2 2006.253.07:31:09.45#ibcon#about to read 5, iclass 35, count 2 2006.253.07:31:09.45#ibcon#read 5, iclass 35, count 2 2006.253.07:31:09.45#ibcon#about to read 6, iclass 35, count 2 2006.253.07:31:09.45#ibcon#read 6, iclass 35, count 2 2006.253.07:31:09.45#ibcon#end of sib2, iclass 35, count 2 2006.253.07:31:09.45#ibcon#*mode == 0, iclass 35, count 2 2006.253.07:31:09.45#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.253.07:31:09.45#ibcon#[25=AT05-07\r\n] 2006.253.07:31:09.45#ibcon#*before write, iclass 35, count 2 2006.253.07:31:09.45#ibcon#enter sib2, iclass 35, count 2 2006.253.07:31:09.45#ibcon#flushed, iclass 35, count 2 2006.253.07:31:09.45#ibcon#about to write, iclass 35, count 2 2006.253.07:31:09.45#ibcon#wrote, iclass 35, count 2 2006.253.07:31:09.45#ibcon#about to read 3, iclass 35, count 2 2006.253.07:31:09.48#ibcon#read 3, iclass 35, count 2 2006.253.07:31:09.48#ibcon#about to read 4, iclass 35, count 2 2006.253.07:31:09.48#ibcon#read 4, iclass 35, count 2 2006.253.07:31:09.48#ibcon#about to read 5, iclass 35, count 2 2006.253.07:31:09.48#ibcon#read 5, iclass 35, count 2 2006.253.07:31:09.48#ibcon#about to read 6, iclass 35, count 2 2006.253.07:31:09.48#ibcon#read 6, iclass 35, count 2 2006.253.07:31:09.48#ibcon#end of sib2, iclass 35, count 2 2006.253.07:31:09.48#ibcon#*after write, iclass 35, count 2 2006.253.07:31:09.48#ibcon#*before return 0, iclass 35, count 2 2006.253.07:31:09.48#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.253.07:31:09.48#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.253.07:31:09.48#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.253.07:31:09.48#ibcon#ireg 7 cls_cnt 0 2006.253.07:31:09.48#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.253.07:31:09.60#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.253.07:31:09.60#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.253.07:31:09.60#ibcon#enter wrdev, iclass 35, count 0 2006.253.07:31:09.60#ibcon#first serial, iclass 35, count 0 2006.253.07:31:09.60#ibcon#enter sib2, iclass 35, count 0 2006.253.07:31:09.60#ibcon#flushed, iclass 35, count 0 2006.253.07:31:09.60#ibcon#about to write, iclass 35, count 0 2006.253.07:31:09.60#ibcon#wrote, iclass 35, count 0 2006.253.07:31:09.60#ibcon#about to read 3, iclass 35, count 0 2006.253.07:31:09.62#ibcon#read 3, iclass 35, count 0 2006.253.07:31:09.62#ibcon#about to read 4, iclass 35, count 0 2006.253.07:31:09.62#ibcon#read 4, iclass 35, count 0 2006.253.07:31:09.62#ibcon#about to read 5, iclass 35, count 0 2006.253.07:31:09.62#ibcon#read 5, iclass 35, count 0 2006.253.07:31:09.62#ibcon#about to read 6, iclass 35, count 0 2006.253.07:31:09.62#ibcon#read 6, iclass 35, count 0 2006.253.07:31:09.62#ibcon#end of sib2, iclass 35, count 0 2006.253.07:31:09.62#ibcon#*mode == 0, iclass 35, count 0 2006.253.07:31:09.62#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.253.07:31:09.62#ibcon#[25=USB\r\n] 2006.253.07:31:09.62#ibcon#*before write, iclass 35, count 0 2006.253.07:31:09.62#ibcon#enter sib2, iclass 35, count 0 2006.253.07:31:09.62#ibcon#flushed, iclass 35, count 0 2006.253.07:31:09.62#ibcon#about to write, iclass 35, count 0 2006.253.07:31:09.62#ibcon#wrote, iclass 35, count 0 2006.253.07:31:09.62#ibcon#about to read 3, iclass 35, count 0 2006.253.07:31:09.65#ibcon#read 3, iclass 35, count 0 2006.253.07:31:09.65#ibcon#about to read 4, iclass 35, count 0 2006.253.07:31:09.65#ibcon#read 4, iclass 35, count 0 2006.253.07:31:09.65#ibcon#about to read 5, iclass 35, count 0 2006.253.07:31:09.65#ibcon#read 5, iclass 35, count 0 2006.253.07:31:09.65#ibcon#about to read 6, iclass 35, count 0 2006.253.07:31:09.65#ibcon#read 6, iclass 35, count 0 2006.253.07:31:09.65#ibcon#end of sib2, iclass 35, count 0 2006.253.07:31:09.65#ibcon#*after write, iclass 35, count 0 2006.253.07:31:09.65#ibcon#*before return 0, iclass 35, count 0 2006.253.07:31:09.65#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.253.07:31:09.65#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.253.07:31:09.65#ibcon#about to clear, iclass 35 cls_cnt 0 2006.253.07:31:09.65#ibcon#cleared, iclass 35 cls_cnt 0 2006.253.07:31:09.65$vc4f8/valo=6,772.99 2006.253.07:31:09.65#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.253.07:31:09.65#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.253.07:31:09.65#ibcon#ireg 17 cls_cnt 0 2006.253.07:31:09.65#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.253.07:31:09.65#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.253.07:31:09.65#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.253.07:31:09.65#ibcon#enter wrdev, iclass 37, count 0 2006.253.07:31:09.65#ibcon#first serial, iclass 37, count 0 2006.253.07:31:09.65#ibcon#enter sib2, iclass 37, count 0 2006.253.07:31:09.65#ibcon#flushed, iclass 37, count 0 2006.253.07:31:09.65#ibcon#about to write, iclass 37, count 0 2006.253.07:31:09.65#ibcon#wrote, iclass 37, count 0 2006.253.07:31:09.65#ibcon#about to read 3, iclass 37, count 0 2006.253.07:31:09.68#ibcon#read 3, iclass 37, count 0 2006.253.07:31:09.68#ibcon#about to read 4, iclass 37, count 0 2006.253.07:31:09.68#ibcon#read 4, iclass 37, count 0 2006.253.07:31:09.68#ibcon#about to read 5, iclass 37, count 0 2006.253.07:31:09.68#ibcon#read 5, iclass 37, count 0 2006.253.07:31:09.68#ibcon#about to read 6, iclass 37, count 0 2006.253.07:31:09.68#ibcon#read 6, iclass 37, count 0 2006.253.07:31:09.68#ibcon#end of sib2, iclass 37, count 0 2006.253.07:31:09.68#ibcon#*mode == 0, iclass 37, count 0 2006.253.07:31:09.68#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.253.07:31:09.68#ibcon#[26=FRQ=06,772.99\r\n] 2006.253.07:31:09.68#ibcon#*before write, iclass 37, count 0 2006.253.07:31:09.68#ibcon#enter sib2, iclass 37, count 0 2006.253.07:31:09.68#ibcon#flushed, iclass 37, count 0 2006.253.07:31:09.68#ibcon#about to write, iclass 37, count 0 2006.253.07:31:09.68#ibcon#wrote, iclass 37, count 0 2006.253.07:31:09.68#ibcon#about to read 3, iclass 37, count 0 2006.253.07:31:09.72#ibcon#read 3, iclass 37, count 0 2006.253.07:31:09.72#ibcon#about to read 4, iclass 37, count 0 2006.253.07:31:09.72#ibcon#read 4, iclass 37, count 0 2006.253.07:31:09.72#ibcon#about to read 5, iclass 37, count 0 2006.253.07:31:09.72#ibcon#read 5, iclass 37, count 0 2006.253.07:31:09.72#ibcon#about to read 6, iclass 37, count 0 2006.253.07:31:09.72#ibcon#read 6, iclass 37, count 0 2006.253.07:31:09.72#ibcon#end of sib2, iclass 37, count 0 2006.253.07:31:09.72#ibcon#*after write, iclass 37, count 0 2006.253.07:31:09.72#ibcon#*before return 0, iclass 37, count 0 2006.253.07:31:09.72#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.253.07:31:09.72#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.253.07:31:09.72#ibcon#about to clear, iclass 37 cls_cnt 0 2006.253.07:31:09.72#ibcon#cleared, iclass 37 cls_cnt 0 2006.253.07:31:09.72$vc4f8/va=6,7 2006.253.07:31:09.72#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.253.07:31:09.72#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.253.07:31:09.72#ibcon#ireg 11 cls_cnt 2 2006.253.07:31:09.72#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.253.07:31:09.77#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.253.07:31:09.77#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.253.07:31:09.77#ibcon#enter wrdev, iclass 39, count 2 2006.253.07:31:09.77#ibcon#first serial, iclass 39, count 2 2006.253.07:31:09.77#ibcon#enter sib2, iclass 39, count 2 2006.253.07:31:09.77#ibcon#flushed, iclass 39, count 2 2006.253.07:31:09.77#ibcon#about to write, iclass 39, count 2 2006.253.07:31:09.77#ibcon#wrote, iclass 39, count 2 2006.253.07:31:09.77#ibcon#about to read 3, iclass 39, count 2 2006.253.07:31:09.79#ibcon#read 3, iclass 39, count 2 2006.253.07:31:09.79#ibcon#about to read 4, iclass 39, count 2 2006.253.07:31:09.79#ibcon#read 4, iclass 39, count 2 2006.253.07:31:09.79#ibcon#about to read 5, iclass 39, count 2 2006.253.07:31:09.79#ibcon#read 5, iclass 39, count 2 2006.253.07:31:09.79#ibcon#about to read 6, iclass 39, count 2 2006.253.07:31:09.79#ibcon#read 6, iclass 39, count 2 2006.253.07:31:09.79#ibcon#end of sib2, iclass 39, count 2 2006.253.07:31:09.79#ibcon#*mode == 0, iclass 39, count 2 2006.253.07:31:09.79#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.253.07:31:09.79#ibcon#[25=AT06-07\r\n] 2006.253.07:31:09.79#ibcon#*before write, iclass 39, count 2 2006.253.07:31:09.79#ibcon#enter sib2, iclass 39, count 2 2006.253.07:31:09.79#ibcon#flushed, iclass 39, count 2 2006.253.07:31:09.79#ibcon#about to write, iclass 39, count 2 2006.253.07:31:09.79#ibcon#wrote, iclass 39, count 2 2006.253.07:31:09.79#ibcon#about to read 3, iclass 39, count 2 2006.253.07:31:09.82#ibcon#read 3, iclass 39, count 2 2006.253.07:31:09.82#ibcon#about to read 4, iclass 39, count 2 2006.253.07:31:09.82#ibcon#read 4, iclass 39, count 2 2006.253.07:31:09.82#ibcon#about to read 5, iclass 39, count 2 2006.253.07:31:09.82#ibcon#read 5, iclass 39, count 2 2006.253.07:31:09.82#ibcon#about to read 6, iclass 39, count 2 2006.253.07:31:09.82#ibcon#read 6, iclass 39, count 2 2006.253.07:31:09.82#ibcon#end of sib2, iclass 39, count 2 2006.253.07:31:09.82#ibcon#*after write, iclass 39, count 2 2006.253.07:31:09.82#ibcon#*before return 0, iclass 39, count 2 2006.253.07:31:09.82#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.253.07:31:09.82#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.253.07:31:09.82#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.253.07:31:09.82#ibcon#ireg 7 cls_cnt 0 2006.253.07:31:09.82#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.253.07:31:09.94#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.253.07:31:09.94#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.253.07:31:09.94#ibcon#enter wrdev, iclass 39, count 0 2006.253.07:31:09.94#ibcon#first serial, iclass 39, count 0 2006.253.07:31:09.94#ibcon#enter sib2, iclass 39, count 0 2006.253.07:31:09.94#ibcon#flushed, iclass 39, count 0 2006.253.07:31:09.94#ibcon#about to write, iclass 39, count 0 2006.253.07:31:09.94#ibcon#wrote, iclass 39, count 0 2006.253.07:31:09.94#ibcon#about to read 3, iclass 39, count 0 2006.253.07:31:09.96#ibcon#read 3, iclass 39, count 0 2006.253.07:31:09.96#ibcon#about to read 4, iclass 39, count 0 2006.253.07:31:09.96#ibcon#read 4, iclass 39, count 0 2006.253.07:31:09.96#ibcon#about to read 5, iclass 39, count 0 2006.253.07:31:09.96#ibcon#read 5, iclass 39, count 0 2006.253.07:31:09.96#ibcon#about to read 6, iclass 39, count 0 2006.253.07:31:09.96#ibcon#read 6, iclass 39, count 0 2006.253.07:31:09.96#ibcon#end of sib2, iclass 39, count 0 2006.253.07:31:09.96#ibcon#*mode == 0, iclass 39, count 0 2006.253.07:31:09.96#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.253.07:31:09.96#ibcon#[25=USB\r\n] 2006.253.07:31:09.96#ibcon#*before write, iclass 39, count 0 2006.253.07:31:09.96#ibcon#enter sib2, iclass 39, count 0 2006.253.07:31:09.96#ibcon#flushed, iclass 39, count 0 2006.253.07:31:09.96#ibcon#about to write, iclass 39, count 0 2006.253.07:31:09.96#ibcon#wrote, iclass 39, count 0 2006.253.07:31:09.96#ibcon#about to read 3, iclass 39, count 0 2006.253.07:31:09.99#ibcon#read 3, iclass 39, count 0 2006.253.07:31:09.99#ibcon#about to read 4, iclass 39, count 0 2006.253.07:31:09.99#ibcon#read 4, iclass 39, count 0 2006.253.07:31:09.99#ibcon#about to read 5, iclass 39, count 0 2006.253.07:31:09.99#ibcon#read 5, iclass 39, count 0 2006.253.07:31:09.99#ibcon#about to read 6, iclass 39, count 0 2006.253.07:31:09.99#ibcon#read 6, iclass 39, count 0 2006.253.07:31:09.99#ibcon#end of sib2, iclass 39, count 0 2006.253.07:31:09.99#ibcon#*after write, iclass 39, count 0 2006.253.07:31:09.99#ibcon#*before return 0, iclass 39, count 0 2006.253.07:31:09.99#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.253.07:31:09.99#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.253.07:31:09.99#ibcon#about to clear, iclass 39 cls_cnt 0 2006.253.07:31:09.99#ibcon#cleared, iclass 39 cls_cnt 0 2006.253.07:31:09.99$vc4f8/valo=7,832.99 2006.253.07:31:09.99#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.253.07:31:09.99#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.253.07:31:09.99#ibcon#ireg 17 cls_cnt 0 2006.253.07:31:09.99#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.253.07:31:09.99#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.253.07:31:09.99#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.253.07:31:09.99#ibcon#enter wrdev, iclass 3, count 0 2006.253.07:31:09.99#ibcon#first serial, iclass 3, count 0 2006.253.07:31:09.99#ibcon#enter sib2, iclass 3, count 0 2006.253.07:31:09.99#ibcon#flushed, iclass 3, count 0 2006.253.07:31:09.99#ibcon#about to write, iclass 3, count 0 2006.253.07:31:09.99#ibcon#wrote, iclass 3, count 0 2006.253.07:31:09.99#ibcon#about to read 3, iclass 3, count 0 2006.253.07:31:10.01#ibcon#read 3, iclass 3, count 0 2006.253.07:31:10.01#ibcon#about to read 4, iclass 3, count 0 2006.253.07:31:10.01#ibcon#read 4, iclass 3, count 0 2006.253.07:31:10.01#ibcon#about to read 5, iclass 3, count 0 2006.253.07:31:10.01#ibcon#read 5, iclass 3, count 0 2006.253.07:31:10.01#ibcon#about to read 6, iclass 3, count 0 2006.253.07:31:10.01#ibcon#read 6, iclass 3, count 0 2006.253.07:31:10.01#ibcon#end of sib2, iclass 3, count 0 2006.253.07:31:10.01#ibcon#*mode == 0, iclass 3, count 0 2006.253.07:31:10.01#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.253.07:31:10.01#ibcon#[26=FRQ=07,832.99\r\n] 2006.253.07:31:10.01#ibcon#*before write, iclass 3, count 0 2006.253.07:31:10.01#ibcon#enter sib2, iclass 3, count 0 2006.253.07:31:10.01#ibcon#flushed, iclass 3, count 0 2006.253.07:31:10.01#ibcon#about to write, iclass 3, count 0 2006.253.07:31:10.01#ibcon#wrote, iclass 3, count 0 2006.253.07:31:10.01#ibcon#about to read 3, iclass 3, count 0 2006.253.07:31:10.05#ibcon#read 3, iclass 3, count 0 2006.253.07:31:10.05#ibcon#about to read 4, iclass 3, count 0 2006.253.07:31:10.05#ibcon#read 4, iclass 3, count 0 2006.253.07:31:10.05#ibcon#about to read 5, iclass 3, count 0 2006.253.07:31:10.05#ibcon#read 5, iclass 3, count 0 2006.253.07:31:10.05#ibcon#about to read 6, iclass 3, count 0 2006.253.07:31:10.05#ibcon#read 6, iclass 3, count 0 2006.253.07:31:10.05#ibcon#end of sib2, iclass 3, count 0 2006.253.07:31:10.05#ibcon#*after write, iclass 3, count 0 2006.253.07:31:10.05#ibcon#*before return 0, iclass 3, count 0 2006.253.07:31:10.05#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.253.07:31:10.05#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.253.07:31:10.05#ibcon#about to clear, iclass 3 cls_cnt 0 2006.253.07:31:10.05#ibcon#cleared, iclass 3 cls_cnt 0 2006.253.07:31:10.05$vc4f8/va=7,7 2006.253.07:31:10.05#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.253.07:31:10.05#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.253.07:31:10.05#ibcon#ireg 11 cls_cnt 2 2006.253.07:31:10.05#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.253.07:31:10.11#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.253.07:31:10.11#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.253.07:31:10.11#ibcon#enter wrdev, iclass 5, count 2 2006.253.07:31:10.11#ibcon#first serial, iclass 5, count 2 2006.253.07:31:10.11#ibcon#enter sib2, iclass 5, count 2 2006.253.07:31:10.11#ibcon#flushed, iclass 5, count 2 2006.253.07:31:10.11#ibcon#about to write, iclass 5, count 2 2006.253.07:31:10.11#ibcon#wrote, iclass 5, count 2 2006.253.07:31:10.11#ibcon#about to read 3, iclass 5, count 2 2006.253.07:31:10.13#ibcon#read 3, iclass 5, count 2 2006.253.07:31:10.13#ibcon#about to read 4, iclass 5, count 2 2006.253.07:31:10.13#ibcon#read 4, iclass 5, count 2 2006.253.07:31:10.13#ibcon#about to read 5, iclass 5, count 2 2006.253.07:31:10.13#ibcon#read 5, iclass 5, count 2 2006.253.07:31:10.13#ibcon#about to read 6, iclass 5, count 2 2006.253.07:31:10.13#ibcon#read 6, iclass 5, count 2 2006.253.07:31:10.13#ibcon#end of sib2, iclass 5, count 2 2006.253.07:31:10.13#ibcon#*mode == 0, iclass 5, count 2 2006.253.07:31:10.13#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.253.07:31:10.13#ibcon#[25=AT07-07\r\n] 2006.253.07:31:10.13#ibcon#*before write, iclass 5, count 2 2006.253.07:31:10.13#ibcon#enter sib2, iclass 5, count 2 2006.253.07:31:10.13#ibcon#flushed, iclass 5, count 2 2006.253.07:31:10.13#ibcon#about to write, iclass 5, count 2 2006.253.07:31:10.13#ibcon#wrote, iclass 5, count 2 2006.253.07:31:10.13#ibcon#about to read 3, iclass 5, count 2 2006.253.07:31:10.16#ibcon#read 3, iclass 5, count 2 2006.253.07:31:10.16#ibcon#about to read 4, iclass 5, count 2 2006.253.07:31:10.16#ibcon#read 4, iclass 5, count 2 2006.253.07:31:10.16#ibcon#about to read 5, iclass 5, count 2 2006.253.07:31:10.16#ibcon#read 5, iclass 5, count 2 2006.253.07:31:10.16#ibcon#about to read 6, iclass 5, count 2 2006.253.07:31:10.16#ibcon#read 6, iclass 5, count 2 2006.253.07:31:10.16#ibcon#end of sib2, iclass 5, count 2 2006.253.07:31:10.16#ibcon#*after write, iclass 5, count 2 2006.253.07:31:10.16#ibcon#*before return 0, iclass 5, count 2 2006.253.07:31:10.16#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.253.07:31:10.16#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.253.07:31:10.16#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.253.07:31:10.16#ibcon#ireg 7 cls_cnt 0 2006.253.07:31:10.16#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.253.07:31:10.28#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.253.07:31:10.28#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.253.07:31:10.28#ibcon#enter wrdev, iclass 5, count 0 2006.253.07:31:10.28#ibcon#first serial, iclass 5, count 0 2006.253.07:31:10.28#ibcon#enter sib2, iclass 5, count 0 2006.253.07:31:10.28#ibcon#flushed, iclass 5, count 0 2006.253.07:31:10.28#ibcon#about to write, iclass 5, count 0 2006.253.07:31:10.28#ibcon#wrote, iclass 5, count 0 2006.253.07:31:10.28#ibcon#about to read 3, iclass 5, count 0 2006.253.07:31:10.30#ibcon#read 3, iclass 5, count 0 2006.253.07:31:10.30#ibcon#about to read 4, iclass 5, count 0 2006.253.07:31:10.30#ibcon#read 4, iclass 5, count 0 2006.253.07:31:10.30#ibcon#about to read 5, iclass 5, count 0 2006.253.07:31:10.30#ibcon#read 5, iclass 5, count 0 2006.253.07:31:10.30#ibcon#about to read 6, iclass 5, count 0 2006.253.07:31:10.30#ibcon#read 6, iclass 5, count 0 2006.253.07:31:10.30#ibcon#end of sib2, iclass 5, count 0 2006.253.07:31:10.30#ibcon#*mode == 0, iclass 5, count 0 2006.253.07:31:10.30#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.253.07:31:10.30#ibcon#[25=USB\r\n] 2006.253.07:31:10.30#ibcon#*before write, iclass 5, count 0 2006.253.07:31:10.30#ibcon#enter sib2, iclass 5, count 0 2006.253.07:31:10.30#ibcon#flushed, iclass 5, count 0 2006.253.07:31:10.30#ibcon#about to write, iclass 5, count 0 2006.253.07:31:10.30#ibcon#wrote, iclass 5, count 0 2006.253.07:31:10.30#ibcon#about to read 3, iclass 5, count 0 2006.253.07:31:10.33#ibcon#read 3, iclass 5, count 0 2006.253.07:31:10.33#ibcon#about to read 4, iclass 5, count 0 2006.253.07:31:10.33#ibcon#read 4, iclass 5, count 0 2006.253.07:31:10.33#ibcon#about to read 5, iclass 5, count 0 2006.253.07:31:10.33#ibcon#read 5, iclass 5, count 0 2006.253.07:31:10.33#ibcon#about to read 6, iclass 5, count 0 2006.253.07:31:10.33#ibcon#read 6, iclass 5, count 0 2006.253.07:31:10.33#ibcon#end of sib2, iclass 5, count 0 2006.253.07:31:10.33#ibcon#*after write, iclass 5, count 0 2006.253.07:31:10.33#ibcon#*before return 0, iclass 5, count 0 2006.253.07:31:10.33#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.253.07:31:10.33#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.253.07:31:10.33#ibcon#about to clear, iclass 5 cls_cnt 0 2006.253.07:31:10.33#ibcon#cleared, iclass 5 cls_cnt 0 2006.253.07:31:10.33$vc4f8/valo=8,852.99 2006.253.07:31:10.33#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.253.07:31:10.33#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.253.07:31:10.33#ibcon#ireg 17 cls_cnt 0 2006.253.07:31:10.33#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.253.07:31:10.33#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.253.07:31:10.33#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.253.07:31:10.33#ibcon#enter wrdev, iclass 7, count 0 2006.253.07:31:10.33#ibcon#first serial, iclass 7, count 0 2006.253.07:31:10.33#ibcon#enter sib2, iclass 7, count 0 2006.253.07:31:10.33#ibcon#flushed, iclass 7, count 0 2006.253.07:31:10.33#ibcon#about to write, iclass 7, count 0 2006.253.07:31:10.33#ibcon#wrote, iclass 7, count 0 2006.253.07:31:10.33#ibcon#about to read 3, iclass 7, count 0 2006.253.07:31:10.36#ibcon#read 3, iclass 7, count 0 2006.253.07:31:10.36#ibcon#about to read 4, iclass 7, count 0 2006.253.07:31:10.36#ibcon#read 4, iclass 7, count 0 2006.253.07:31:10.36#ibcon#about to read 5, iclass 7, count 0 2006.253.07:31:10.36#ibcon#read 5, iclass 7, count 0 2006.253.07:31:10.36#ibcon#about to read 6, iclass 7, count 0 2006.253.07:31:10.36#ibcon#read 6, iclass 7, count 0 2006.253.07:31:10.36#ibcon#end of sib2, iclass 7, count 0 2006.253.07:31:10.36#ibcon#*mode == 0, iclass 7, count 0 2006.253.07:31:10.36#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.253.07:31:10.36#ibcon#[26=FRQ=08,852.99\r\n] 2006.253.07:31:10.36#ibcon#*before write, iclass 7, count 0 2006.253.07:31:10.36#ibcon#enter sib2, iclass 7, count 0 2006.253.07:31:10.36#ibcon#flushed, iclass 7, count 0 2006.253.07:31:10.36#ibcon#about to write, iclass 7, count 0 2006.253.07:31:10.36#ibcon#wrote, iclass 7, count 0 2006.253.07:31:10.36#ibcon#about to read 3, iclass 7, count 0 2006.253.07:31:10.40#ibcon#read 3, iclass 7, count 0 2006.253.07:31:10.40#ibcon#about to read 4, iclass 7, count 0 2006.253.07:31:10.40#ibcon#read 4, iclass 7, count 0 2006.253.07:31:10.40#ibcon#about to read 5, iclass 7, count 0 2006.253.07:31:10.40#ibcon#read 5, iclass 7, count 0 2006.253.07:31:10.40#ibcon#about to read 6, iclass 7, count 0 2006.253.07:31:10.40#ibcon#read 6, iclass 7, count 0 2006.253.07:31:10.40#ibcon#end of sib2, iclass 7, count 0 2006.253.07:31:10.40#ibcon#*after write, iclass 7, count 0 2006.253.07:31:10.40#ibcon#*before return 0, iclass 7, count 0 2006.253.07:31:10.40#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.253.07:31:10.40#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.253.07:31:10.40#ibcon#about to clear, iclass 7 cls_cnt 0 2006.253.07:31:10.40#ibcon#cleared, iclass 7 cls_cnt 0 2006.253.07:31:10.40$vc4f8/va=8,7 2006.253.07:31:10.40#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.253.07:31:10.40#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.253.07:31:10.40#ibcon#ireg 11 cls_cnt 2 2006.253.07:31:10.40#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.253.07:31:10.42#abcon#<5=/08 1.1 3.8 31.61 721006.3\r\n> 2006.253.07:31:10.44#abcon#{5=INTERFACE CLEAR} 2006.253.07:31:10.45#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.253.07:31:10.45#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.253.07:31:10.45#ibcon#enter wrdev, iclass 12, count 2 2006.253.07:31:10.45#ibcon#first serial, iclass 12, count 2 2006.253.07:31:10.45#ibcon#enter sib2, iclass 12, count 2 2006.253.07:31:10.45#ibcon#flushed, iclass 12, count 2 2006.253.07:31:10.45#ibcon#about to write, iclass 12, count 2 2006.253.07:31:10.45#ibcon#wrote, iclass 12, count 2 2006.253.07:31:10.45#ibcon#about to read 3, iclass 12, count 2 2006.253.07:31:10.47#ibcon#read 3, iclass 12, count 2 2006.253.07:31:10.47#ibcon#about to read 4, iclass 12, count 2 2006.253.07:31:10.47#ibcon#read 4, iclass 12, count 2 2006.253.07:31:10.47#ibcon#about to read 5, iclass 12, count 2 2006.253.07:31:10.47#ibcon#read 5, iclass 12, count 2 2006.253.07:31:10.47#ibcon#about to read 6, iclass 12, count 2 2006.253.07:31:10.47#ibcon#read 6, iclass 12, count 2 2006.253.07:31:10.47#ibcon#end of sib2, iclass 12, count 2 2006.253.07:31:10.47#ibcon#*mode == 0, iclass 12, count 2 2006.253.07:31:10.47#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.253.07:31:10.47#ibcon#[25=AT08-07\r\n] 2006.253.07:31:10.47#ibcon#*before write, iclass 12, count 2 2006.253.07:31:10.47#ibcon#enter sib2, iclass 12, count 2 2006.253.07:31:10.47#ibcon#flushed, iclass 12, count 2 2006.253.07:31:10.47#ibcon#about to write, iclass 12, count 2 2006.253.07:31:10.47#ibcon#wrote, iclass 12, count 2 2006.253.07:31:10.47#ibcon#about to read 3, iclass 12, count 2 2006.253.07:31:10.50#abcon#[5=S1D000X0/0*\r\n] 2006.253.07:31:10.50#ibcon#read 3, iclass 12, count 2 2006.253.07:31:10.50#ibcon#about to read 4, iclass 12, count 2 2006.253.07:31:10.50#ibcon#read 4, iclass 12, count 2 2006.253.07:31:10.50#ibcon#about to read 5, iclass 12, count 2 2006.253.07:31:10.50#ibcon#read 5, iclass 12, count 2 2006.253.07:31:10.50#ibcon#about to read 6, iclass 12, count 2 2006.253.07:31:10.50#ibcon#read 6, iclass 12, count 2 2006.253.07:31:10.50#ibcon#end of sib2, iclass 12, count 2 2006.253.07:31:10.50#ibcon#*after write, iclass 12, count 2 2006.253.07:31:10.50#ibcon#*before return 0, iclass 12, count 2 2006.253.07:31:10.50#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.253.07:31:10.50#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.253.07:31:10.50#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.253.07:31:10.50#ibcon#ireg 7 cls_cnt 0 2006.253.07:31:10.50#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.253.07:31:10.62#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.253.07:31:10.62#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.253.07:31:10.62#ibcon#enter wrdev, iclass 12, count 0 2006.253.07:31:10.62#ibcon#first serial, iclass 12, count 0 2006.253.07:31:10.62#ibcon#enter sib2, iclass 12, count 0 2006.253.07:31:10.62#ibcon#flushed, iclass 12, count 0 2006.253.07:31:10.62#ibcon#about to write, iclass 12, count 0 2006.253.07:31:10.62#ibcon#wrote, iclass 12, count 0 2006.253.07:31:10.62#ibcon#about to read 3, iclass 12, count 0 2006.253.07:31:10.64#ibcon#read 3, iclass 12, count 0 2006.253.07:31:10.64#ibcon#about to read 4, iclass 12, count 0 2006.253.07:31:10.64#ibcon#read 4, iclass 12, count 0 2006.253.07:31:10.64#ibcon#about to read 5, iclass 12, count 0 2006.253.07:31:10.64#ibcon#read 5, iclass 12, count 0 2006.253.07:31:10.64#ibcon#about to read 6, iclass 12, count 0 2006.253.07:31:10.64#ibcon#read 6, iclass 12, count 0 2006.253.07:31:10.64#ibcon#end of sib2, iclass 12, count 0 2006.253.07:31:10.64#ibcon#*mode == 0, iclass 12, count 0 2006.253.07:31:10.64#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.253.07:31:10.64#ibcon#[25=USB\r\n] 2006.253.07:31:10.64#ibcon#*before write, iclass 12, count 0 2006.253.07:31:10.64#ibcon#enter sib2, iclass 12, count 0 2006.253.07:31:10.64#ibcon#flushed, iclass 12, count 0 2006.253.07:31:10.64#ibcon#about to write, iclass 12, count 0 2006.253.07:31:10.64#ibcon#wrote, iclass 12, count 0 2006.253.07:31:10.64#ibcon#about to read 3, iclass 12, count 0 2006.253.07:31:10.67#ibcon#read 3, iclass 12, count 0 2006.253.07:31:10.67#ibcon#about to read 4, iclass 12, count 0 2006.253.07:31:10.67#ibcon#read 4, iclass 12, count 0 2006.253.07:31:10.67#ibcon#about to read 5, iclass 12, count 0 2006.253.07:31:10.67#ibcon#read 5, iclass 12, count 0 2006.253.07:31:10.67#ibcon#about to read 6, iclass 12, count 0 2006.253.07:31:10.67#ibcon#read 6, iclass 12, count 0 2006.253.07:31:10.67#ibcon#end of sib2, iclass 12, count 0 2006.253.07:31:10.67#ibcon#*after write, iclass 12, count 0 2006.253.07:31:10.67#ibcon#*before return 0, iclass 12, count 0 2006.253.07:31:10.67#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.253.07:31:10.67#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.253.07:31:10.67#ibcon#about to clear, iclass 12 cls_cnt 0 2006.253.07:31:10.67#ibcon#cleared, iclass 12 cls_cnt 0 2006.253.07:31:10.67$vc4f8/vblo=1,632.99 2006.253.07:31:10.67#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.253.07:31:10.67#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.253.07:31:10.67#ibcon#ireg 17 cls_cnt 0 2006.253.07:31:10.67#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.253.07:31:10.67#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.253.07:31:10.67#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.253.07:31:10.67#ibcon#enter wrdev, iclass 17, count 0 2006.253.07:31:10.67#ibcon#first serial, iclass 17, count 0 2006.253.07:31:10.67#ibcon#enter sib2, iclass 17, count 0 2006.253.07:31:10.67#ibcon#flushed, iclass 17, count 0 2006.253.07:31:10.67#ibcon#about to write, iclass 17, count 0 2006.253.07:31:10.67#ibcon#wrote, iclass 17, count 0 2006.253.07:31:10.67#ibcon#about to read 3, iclass 17, count 0 2006.253.07:31:10.69#ibcon#read 3, iclass 17, count 0 2006.253.07:31:10.69#ibcon#about to read 4, iclass 17, count 0 2006.253.07:31:10.69#ibcon#read 4, iclass 17, count 0 2006.253.07:31:10.69#ibcon#about to read 5, iclass 17, count 0 2006.253.07:31:10.69#ibcon#read 5, iclass 17, count 0 2006.253.07:31:10.69#ibcon#about to read 6, iclass 17, count 0 2006.253.07:31:10.69#ibcon#read 6, iclass 17, count 0 2006.253.07:31:10.69#ibcon#end of sib2, iclass 17, count 0 2006.253.07:31:10.69#ibcon#*mode == 0, iclass 17, count 0 2006.253.07:31:10.69#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.253.07:31:10.69#ibcon#[28=FRQ=01,632.99\r\n] 2006.253.07:31:10.69#ibcon#*before write, iclass 17, count 0 2006.253.07:31:10.69#ibcon#enter sib2, iclass 17, count 0 2006.253.07:31:10.69#ibcon#flushed, iclass 17, count 0 2006.253.07:31:10.69#ibcon#about to write, iclass 17, count 0 2006.253.07:31:10.69#ibcon#wrote, iclass 17, count 0 2006.253.07:31:10.69#ibcon#about to read 3, iclass 17, count 0 2006.253.07:31:10.73#ibcon#read 3, iclass 17, count 0 2006.253.07:31:10.73#ibcon#about to read 4, iclass 17, count 0 2006.253.07:31:10.73#ibcon#read 4, iclass 17, count 0 2006.253.07:31:10.73#ibcon#about to read 5, iclass 17, count 0 2006.253.07:31:10.73#ibcon#read 5, iclass 17, count 0 2006.253.07:31:10.73#ibcon#about to read 6, iclass 17, count 0 2006.253.07:31:10.73#ibcon#read 6, iclass 17, count 0 2006.253.07:31:10.73#ibcon#end of sib2, iclass 17, count 0 2006.253.07:31:10.73#ibcon#*after write, iclass 17, count 0 2006.253.07:31:10.73#ibcon#*before return 0, iclass 17, count 0 2006.253.07:31:10.73#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.253.07:31:10.73#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.253.07:31:10.73#ibcon#about to clear, iclass 17 cls_cnt 0 2006.253.07:31:10.73#ibcon#cleared, iclass 17 cls_cnt 0 2006.253.07:31:10.73$vc4f8/vb=1,4 2006.253.07:31:10.73#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.253.07:31:10.73#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.253.07:31:10.73#ibcon#ireg 11 cls_cnt 2 2006.253.07:31:10.73#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.253.07:31:10.73#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.253.07:31:10.73#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.253.07:31:10.73#ibcon#enter wrdev, iclass 19, count 2 2006.253.07:31:10.73#ibcon#first serial, iclass 19, count 2 2006.253.07:31:10.73#ibcon#enter sib2, iclass 19, count 2 2006.253.07:31:10.73#ibcon#flushed, iclass 19, count 2 2006.253.07:31:10.73#ibcon#about to write, iclass 19, count 2 2006.253.07:31:10.73#ibcon#wrote, iclass 19, count 2 2006.253.07:31:10.73#ibcon#about to read 3, iclass 19, count 2 2006.253.07:31:10.75#ibcon#read 3, iclass 19, count 2 2006.253.07:31:10.75#ibcon#about to read 4, iclass 19, count 2 2006.253.07:31:10.75#ibcon#read 4, iclass 19, count 2 2006.253.07:31:10.75#ibcon#about to read 5, iclass 19, count 2 2006.253.07:31:10.75#ibcon#read 5, iclass 19, count 2 2006.253.07:31:10.75#ibcon#about to read 6, iclass 19, count 2 2006.253.07:31:10.75#ibcon#read 6, iclass 19, count 2 2006.253.07:31:10.75#ibcon#end of sib2, iclass 19, count 2 2006.253.07:31:10.75#ibcon#*mode == 0, iclass 19, count 2 2006.253.07:31:10.75#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.253.07:31:10.75#ibcon#[27=AT01-04\r\n] 2006.253.07:31:10.75#ibcon#*before write, iclass 19, count 2 2006.253.07:31:10.75#ibcon#enter sib2, iclass 19, count 2 2006.253.07:31:10.75#ibcon#flushed, iclass 19, count 2 2006.253.07:31:10.75#ibcon#about to write, iclass 19, count 2 2006.253.07:31:10.75#ibcon#wrote, iclass 19, count 2 2006.253.07:31:10.75#ibcon#about to read 3, iclass 19, count 2 2006.253.07:31:10.78#ibcon#read 3, iclass 19, count 2 2006.253.07:31:10.78#ibcon#about to read 4, iclass 19, count 2 2006.253.07:31:10.78#ibcon#read 4, iclass 19, count 2 2006.253.07:31:10.78#ibcon#about to read 5, iclass 19, count 2 2006.253.07:31:10.78#ibcon#read 5, iclass 19, count 2 2006.253.07:31:10.78#ibcon#about to read 6, iclass 19, count 2 2006.253.07:31:10.78#ibcon#read 6, iclass 19, count 2 2006.253.07:31:10.78#ibcon#end of sib2, iclass 19, count 2 2006.253.07:31:10.78#ibcon#*after write, iclass 19, count 2 2006.253.07:31:10.78#ibcon#*before return 0, iclass 19, count 2 2006.253.07:31:10.78#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.253.07:31:10.78#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.253.07:31:10.78#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.253.07:31:10.78#ibcon#ireg 7 cls_cnt 0 2006.253.07:31:10.78#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.253.07:31:10.90#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.253.07:31:10.90#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.253.07:31:10.90#ibcon#enter wrdev, iclass 19, count 0 2006.253.07:31:10.90#ibcon#first serial, iclass 19, count 0 2006.253.07:31:10.90#ibcon#enter sib2, iclass 19, count 0 2006.253.07:31:10.90#ibcon#flushed, iclass 19, count 0 2006.253.07:31:10.90#ibcon#about to write, iclass 19, count 0 2006.253.07:31:10.90#ibcon#wrote, iclass 19, count 0 2006.253.07:31:10.90#ibcon#about to read 3, iclass 19, count 0 2006.253.07:31:10.92#ibcon#read 3, iclass 19, count 0 2006.253.07:31:10.92#ibcon#about to read 4, iclass 19, count 0 2006.253.07:31:10.92#ibcon#read 4, iclass 19, count 0 2006.253.07:31:10.92#ibcon#about to read 5, iclass 19, count 0 2006.253.07:31:10.92#ibcon#read 5, iclass 19, count 0 2006.253.07:31:10.92#ibcon#about to read 6, iclass 19, count 0 2006.253.07:31:10.92#ibcon#read 6, iclass 19, count 0 2006.253.07:31:10.92#ibcon#end of sib2, iclass 19, count 0 2006.253.07:31:10.92#ibcon#*mode == 0, iclass 19, count 0 2006.253.07:31:10.92#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.253.07:31:10.92#ibcon#[27=USB\r\n] 2006.253.07:31:10.92#ibcon#*before write, iclass 19, count 0 2006.253.07:31:10.92#ibcon#enter sib2, iclass 19, count 0 2006.253.07:31:10.92#ibcon#flushed, iclass 19, count 0 2006.253.07:31:10.92#ibcon#about to write, iclass 19, count 0 2006.253.07:31:10.92#ibcon#wrote, iclass 19, count 0 2006.253.07:31:10.92#ibcon#about to read 3, iclass 19, count 0 2006.253.07:31:10.95#ibcon#read 3, iclass 19, count 0 2006.253.07:31:10.95#ibcon#about to read 4, iclass 19, count 0 2006.253.07:31:10.95#ibcon#read 4, iclass 19, count 0 2006.253.07:31:10.95#ibcon#about to read 5, iclass 19, count 0 2006.253.07:31:10.95#ibcon#read 5, iclass 19, count 0 2006.253.07:31:10.95#ibcon#about to read 6, iclass 19, count 0 2006.253.07:31:10.95#ibcon#read 6, iclass 19, count 0 2006.253.07:31:10.95#ibcon#end of sib2, iclass 19, count 0 2006.253.07:31:10.95#ibcon#*after write, iclass 19, count 0 2006.253.07:31:10.95#ibcon#*before return 0, iclass 19, count 0 2006.253.07:31:10.95#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.253.07:31:10.95#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.253.07:31:10.95#ibcon#about to clear, iclass 19 cls_cnt 0 2006.253.07:31:10.95#ibcon#cleared, iclass 19 cls_cnt 0 2006.253.07:31:10.95$vc4f8/vblo=2,640.99 2006.253.07:31:10.95#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.253.07:31:10.95#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.253.07:31:10.95#ibcon#ireg 17 cls_cnt 0 2006.253.07:31:10.95#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.253.07:31:10.95#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.253.07:31:10.95#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.253.07:31:10.95#ibcon#enter wrdev, iclass 21, count 0 2006.253.07:31:10.95#ibcon#first serial, iclass 21, count 0 2006.253.07:31:10.95#ibcon#enter sib2, iclass 21, count 0 2006.253.07:31:10.95#ibcon#flushed, iclass 21, count 0 2006.253.07:31:10.95#ibcon#about to write, iclass 21, count 0 2006.253.07:31:10.95#ibcon#wrote, iclass 21, count 0 2006.253.07:31:10.95#ibcon#about to read 3, iclass 21, count 0 2006.253.07:31:10.98#ibcon#read 3, iclass 21, count 0 2006.253.07:31:10.98#ibcon#about to read 4, iclass 21, count 0 2006.253.07:31:10.98#ibcon#read 4, iclass 21, count 0 2006.253.07:31:10.98#ibcon#about to read 5, iclass 21, count 0 2006.253.07:31:10.98#ibcon#read 5, iclass 21, count 0 2006.253.07:31:10.98#ibcon#about to read 6, iclass 21, count 0 2006.253.07:31:10.98#ibcon#read 6, iclass 21, count 0 2006.253.07:31:10.98#ibcon#end of sib2, iclass 21, count 0 2006.253.07:31:10.98#ibcon#*mode == 0, iclass 21, count 0 2006.253.07:31:10.98#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.253.07:31:10.98#ibcon#[28=FRQ=02,640.99\r\n] 2006.253.07:31:10.98#ibcon#*before write, iclass 21, count 0 2006.253.07:31:10.98#ibcon#enter sib2, iclass 21, count 0 2006.253.07:31:10.98#ibcon#flushed, iclass 21, count 0 2006.253.07:31:10.98#ibcon#about to write, iclass 21, count 0 2006.253.07:31:10.98#ibcon#wrote, iclass 21, count 0 2006.253.07:31:10.98#ibcon#about to read 3, iclass 21, count 0 2006.253.07:31:11.02#ibcon#read 3, iclass 21, count 0 2006.253.07:31:11.02#ibcon#about to read 4, iclass 21, count 0 2006.253.07:31:11.02#ibcon#read 4, iclass 21, count 0 2006.253.07:31:11.02#ibcon#about to read 5, iclass 21, count 0 2006.253.07:31:11.02#ibcon#read 5, iclass 21, count 0 2006.253.07:31:11.02#ibcon#about to read 6, iclass 21, count 0 2006.253.07:31:11.02#ibcon#read 6, iclass 21, count 0 2006.253.07:31:11.02#ibcon#end of sib2, iclass 21, count 0 2006.253.07:31:11.02#ibcon#*after write, iclass 21, count 0 2006.253.07:31:11.02#ibcon#*before return 0, iclass 21, count 0 2006.253.07:31:11.02#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.253.07:31:11.02#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.253.07:31:11.02#ibcon#about to clear, iclass 21 cls_cnt 0 2006.253.07:31:11.02#ibcon#cleared, iclass 21 cls_cnt 0 2006.253.07:31:11.02$vc4f8/vb=2,5 2006.253.07:31:11.02#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.253.07:31:11.02#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.253.07:31:11.02#ibcon#ireg 11 cls_cnt 2 2006.253.07:31:11.02#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.253.07:31:11.07#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.253.07:31:11.07#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.253.07:31:11.07#ibcon#enter wrdev, iclass 23, count 2 2006.253.07:31:11.07#ibcon#first serial, iclass 23, count 2 2006.253.07:31:11.07#ibcon#enter sib2, iclass 23, count 2 2006.253.07:31:11.07#ibcon#flushed, iclass 23, count 2 2006.253.07:31:11.07#ibcon#about to write, iclass 23, count 2 2006.253.07:31:11.07#ibcon#wrote, iclass 23, count 2 2006.253.07:31:11.07#ibcon#about to read 3, iclass 23, count 2 2006.253.07:31:11.09#ibcon#read 3, iclass 23, count 2 2006.253.07:31:11.09#ibcon#about to read 4, iclass 23, count 2 2006.253.07:31:11.09#ibcon#read 4, iclass 23, count 2 2006.253.07:31:11.09#ibcon#about to read 5, iclass 23, count 2 2006.253.07:31:11.09#ibcon#read 5, iclass 23, count 2 2006.253.07:31:11.09#ibcon#about to read 6, iclass 23, count 2 2006.253.07:31:11.09#ibcon#read 6, iclass 23, count 2 2006.253.07:31:11.09#ibcon#end of sib2, iclass 23, count 2 2006.253.07:31:11.09#ibcon#*mode == 0, iclass 23, count 2 2006.253.07:31:11.09#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.253.07:31:11.09#ibcon#[27=AT02-05\r\n] 2006.253.07:31:11.09#ibcon#*before write, iclass 23, count 2 2006.253.07:31:11.09#ibcon#enter sib2, iclass 23, count 2 2006.253.07:31:11.09#ibcon#flushed, iclass 23, count 2 2006.253.07:31:11.09#ibcon#about to write, iclass 23, count 2 2006.253.07:31:11.09#ibcon#wrote, iclass 23, count 2 2006.253.07:31:11.09#ibcon#about to read 3, iclass 23, count 2 2006.253.07:31:11.12#ibcon#read 3, iclass 23, count 2 2006.253.07:31:11.12#ibcon#about to read 4, iclass 23, count 2 2006.253.07:31:11.12#ibcon#read 4, iclass 23, count 2 2006.253.07:31:11.12#ibcon#about to read 5, iclass 23, count 2 2006.253.07:31:11.12#ibcon#read 5, iclass 23, count 2 2006.253.07:31:11.12#ibcon#about to read 6, iclass 23, count 2 2006.253.07:31:11.12#ibcon#read 6, iclass 23, count 2 2006.253.07:31:11.12#ibcon#end of sib2, iclass 23, count 2 2006.253.07:31:11.12#ibcon#*after write, iclass 23, count 2 2006.253.07:31:11.12#ibcon#*before return 0, iclass 23, count 2 2006.253.07:31:11.12#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.253.07:31:11.12#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.253.07:31:11.12#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.253.07:31:11.12#ibcon#ireg 7 cls_cnt 0 2006.253.07:31:11.12#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.253.07:31:11.24#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.253.07:31:11.24#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.253.07:31:11.24#ibcon#enter wrdev, iclass 23, count 0 2006.253.07:31:11.24#ibcon#first serial, iclass 23, count 0 2006.253.07:31:11.24#ibcon#enter sib2, iclass 23, count 0 2006.253.07:31:11.24#ibcon#flushed, iclass 23, count 0 2006.253.07:31:11.24#ibcon#about to write, iclass 23, count 0 2006.253.07:31:11.24#ibcon#wrote, iclass 23, count 0 2006.253.07:31:11.24#ibcon#about to read 3, iclass 23, count 0 2006.253.07:31:11.26#ibcon#read 3, iclass 23, count 0 2006.253.07:31:11.26#ibcon#about to read 4, iclass 23, count 0 2006.253.07:31:11.26#ibcon#read 4, iclass 23, count 0 2006.253.07:31:11.26#ibcon#about to read 5, iclass 23, count 0 2006.253.07:31:11.26#ibcon#read 5, iclass 23, count 0 2006.253.07:31:11.26#ibcon#about to read 6, iclass 23, count 0 2006.253.07:31:11.26#ibcon#read 6, iclass 23, count 0 2006.253.07:31:11.26#ibcon#end of sib2, iclass 23, count 0 2006.253.07:31:11.26#ibcon#*mode == 0, iclass 23, count 0 2006.253.07:31:11.26#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.253.07:31:11.26#ibcon#[27=USB\r\n] 2006.253.07:31:11.26#ibcon#*before write, iclass 23, count 0 2006.253.07:31:11.26#ibcon#enter sib2, iclass 23, count 0 2006.253.07:31:11.26#ibcon#flushed, iclass 23, count 0 2006.253.07:31:11.26#ibcon#about to write, iclass 23, count 0 2006.253.07:31:11.26#ibcon#wrote, iclass 23, count 0 2006.253.07:31:11.26#ibcon#about to read 3, iclass 23, count 0 2006.253.07:31:11.29#ibcon#read 3, iclass 23, count 0 2006.253.07:31:11.29#ibcon#about to read 4, iclass 23, count 0 2006.253.07:31:11.29#ibcon#read 4, iclass 23, count 0 2006.253.07:31:11.29#ibcon#about to read 5, iclass 23, count 0 2006.253.07:31:11.29#ibcon#read 5, iclass 23, count 0 2006.253.07:31:11.29#ibcon#about to read 6, iclass 23, count 0 2006.253.07:31:11.29#ibcon#read 6, iclass 23, count 0 2006.253.07:31:11.29#ibcon#end of sib2, iclass 23, count 0 2006.253.07:31:11.29#ibcon#*after write, iclass 23, count 0 2006.253.07:31:11.29#ibcon#*before return 0, iclass 23, count 0 2006.253.07:31:11.29#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.253.07:31:11.29#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.253.07:31:11.29#ibcon#about to clear, iclass 23 cls_cnt 0 2006.253.07:31:11.29#ibcon#cleared, iclass 23 cls_cnt 0 2006.253.07:31:11.29$vc4f8/vblo=3,656.99 2006.253.07:31:11.29#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.253.07:31:11.29#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.253.07:31:11.29#ibcon#ireg 17 cls_cnt 0 2006.253.07:31:11.29#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.253.07:31:11.29#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.253.07:31:11.29#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.253.07:31:11.29#ibcon#enter wrdev, iclass 25, count 0 2006.253.07:31:11.29#ibcon#first serial, iclass 25, count 0 2006.253.07:31:11.29#ibcon#enter sib2, iclass 25, count 0 2006.253.07:31:11.29#ibcon#flushed, iclass 25, count 0 2006.253.07:31:11.29#ibcon#about to write, iclass 25, count 0 2006.253.07:31:11.29#ibcon#wrote, iclass 25, count 0 2006.253.07:31:11.29#ibcon#about to read 3, iclass 25, count 0 2006.253.07:31:11.31#ibcon#read 3, iclass 25, count 0 2006.253.07:31:11.31#ibcon#about to read 4, iclass 25, count 0 2006.253.07:31:11.31#ibcon#read 4, iclass 25, count 0 2006.253.07:31:11.31#ibcon#about to read 5, iclass 25, count 0 2006.253.07:31:11.31#ibcon#read 5, iclass 25, count 0 2006.253.07:31:11.31#ibcon#about to read 6, iclass 25, count 0 2006.253.07:31:11.31#ibcon#read 6, iclass 25, count 0 2006.253.07:31:11.31#ibcon#end of sib2, iclass 25, count 0 2006.253.07:31:11.31#ibcon#*mode == 0, iclass 25, count 0 2006.253.07:31:11.31#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.253.07:31:11.31#ibcon#[28=FRQ=03,656.99\r\n] 2006.253.07:31:11.31#ibcon#*before write, iclass 25, count 0 2006.253.07:31:11.31#ibcon#enter sib2, iclass 25, count 0 2006.253.07:31:11.31#ibcon#flushed, iclass 25, count 0 2006.253.07:31:11.31#ibcon#about to write, iclass 25, count 0 2006.253.07:31:11.31#ibcon#wrote, iclass 25, count 0 2006.253.07:31:11.31#ibcon#about to read 3, iclass 25, count 0 2006.253.07:31:11.35#ibcon#read 3, iclass 25, count 0 2006.253.07:31:11.35#ibcon#about to read 4, iclass 25, count 0 2006.253.07:31:11.35#ibcon#read 4, iclass 25, count 0 2006.253.07:31:11.35#ibcon#about to read 5, iclass 25, count 0 2006.253.07:31:11.35#ibcon#read 5, iclass 25, count 0 2006.253.07:31:11.35#ibcon#about to read 6, iclass 25, count 0 2006.253.07:31:11.35#ibcon#read 6, iclass 25, count 0 2006.253.07:31:11.35#ibcon#end of sib2, iclass 25, count 0 2006.253.07:31:11.35#ibcon#*after write, iclass 25, count 0 2006.253.07:31:11.35#ibcon#*before return 0, iclass 25, count 0 2006.253.07:31:11.35#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.253.07:31:11.35#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.253.07:31:11.35#ibcon#about to clear, iclass 25 cls_cnt 0 2006.253.07:31:11.35#ibcon#cleared, iclass 25 cls_cnt 0 2006.253.07:31:11.35$vc4f8/vb=3,4 2006.253.07:31:11.35#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.253.07:31:11.35#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.253.07:31:11.35#ibcon#ireg 11 cls_cnt 2 2006.253.07:31:11.35#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.253.07:31:11.41#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.253.07:31:11.41#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.253.07:31:11.41#ibcon#enter wrdev, iclass 27, count 2 2006.253.07:31:11.41#ibcon#first serial, iclass 27, count 2 2006.253.07:31:11.41#ibcon#enter sib2, iclass 27, count 2 2006.253.07:31:11.41#ibcon#flushed, iclass 27, count 2 2006.253.07:31:11.41#ibcon#about to write, iclass 27, count 2 2006.253.07:31:11.41#ibcon#wrote, iclass 27, count 2 2006.253.07:31:11.41#ibcon#about to read 3, iclass 27, count 2 2006.253.07:31:11.43#ibcon#read 3, iclass 27, count 2 2006.253.07:31:11.43#ibcon#about to read 4, iclass 27, count 2 2006.253.07:31:11.43#ibcon#read 4, iclass 27, count 2 2006.253.07:31:11.43#ibcon#about to read 5, iclass 27, count 2 2006.253.07:31:11.43#ibcon#read 5, iclass 27, count 2 2006.253.07:31:11.43#ibcon#about to read 6, iclass 27, count 2 2006.253.07:31:11.43#ibcon#read 6, iclass 27, count 2 2006.253.07:31:11.43#ibcon#end of sib2, iclass 27, count 2 2006.253.07:31:11.43#ibcon#*mode == 0, iclass 27, count 2 2006.253.07:31:11.43#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.253.07:31:11.43#ibcon#[27=AT03-04\r\n] 2006.253.07:31:11.43#ibcon#*before write, iclass 27, count 2 2006.253.07:31:11.43#ibcon#enter sib2, iclass 27, count 2 2006.253.07:31:11.43#ibcon#flushed, iclass 27, count 2 2006.253.07:31:11.43#ibcon#about to write, iclass 27, count 2 2006.253.07:31:11.43#ibcon#wrote, iclass 27, count 2 2006.253.07:31:11.43#ibcon#about to read 3, iclass 27, count 2 2006.253.07:31:11.46#ibcon#read 3, iclass 27, count 2 2006.253.07:31:11.46#ibcon#about to read 4, iclass 27, count 2 2006.253.07:31:11.46#ibcon#read 4, iclass 27, count 2 2006.253.07:31:11.46#ibcon#about to read 5, iclass 27, count 2 2006.253.07:31:11.46#ibcon#read 5, iclass 27, count 2 2006.253.07:31:11.46#ibcon#about to read 6, iclass 27, count 2 2006.253.07:31:11.46#ibcon#read 6, iclass 27, count 2 2006.253.07:31:11.46#ibcon#end of sib2, iclass 27, count 2 2006.253.07:31:11.46#ibcon#*after write, iclass 27, count 2 2006.253.07:31:11.46#ibcon#*before return 0, iclass 27, count 2 2006.253.07:31:11.46#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.253.07:31:11.46#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.253.07:31:11.46#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.253.07:31:11.46#ibcon#ireg 7 cls_cnt 0 2006.253.07:31:11.46#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.253.07:31:11.58#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.253.07:31:11.58#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.253.07:31:11.58#ibcon#enter wrdev, iclass 27, count 0 2006.253.07:31:11.58#ibcon#first serial, iclass 27, count 0 2006.253.07:31:11.58#ibcon#enter sib2, iclass 27, count 0 2006.253.07:31:11.58#ibcon#flushed, iclass 27, count 0 2006.253.07:31:11.58#ibcon#about to write, iclass 27, count 0 2006.253.07:31:11.58#ibcon#wrote, iclass 27, count 0 2006.253.07:31:11.58#ibcon#about to read 3, iclass 27, count 0 2006.253.07:31:11.60#ibcon#read 3, iclass 27, count 0 2006.253.07:31:11.60#ibcon#about to read 4, iclass 27, count 0 2006.253.07:31:11.60#ibcon#read 4, iclass 27, count 0 2006.253.07:31:11.60#ibcon#about to read 5, iclass 27, count 0 2006.253.07:31:11.60#ibcon#read 5, iclass 27, count 0 2006.253.07:31:11.60#ibcon#about to read 6, iclass 27, count 0 2006.253.07:31:11.60#ibcon#read 6, iclass 27, count 0 2006.253.07:31:11.60#ibcon#end of sib2, iclass 27, count 0 2006.253.07:31:11.60#ibcon#*mode == 0, iclass 27, count 0 2006.253.07:31:11.60#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.253.07:31:11.60#ibcon#[27=USB\r\n] 2006.253.07:31:11.60#ibcon#*before write, iclass 27, count 0 2006.253.07:31:11.60#ibcon#enter sib2, iclass 27, count 0 2006.253.07:31:11.60#ibcon#flushed, iclass 27, count 0 2006.253.07:31:11.60#ibcon#about to write, iclass 27, count 0 2006.253.07:31:11.60#ibcon#wrote, iclass 27, count 0 2006.253.07:31:11.60#ibcon#about to read 3, iclass 27, count 0 2006.253.07:31:11.63#ibcon#read 3, iclass 27, count 0 2006.253.07:31:11.63#ibcon#about to read 4, iclass 27, count 0 2006.253.07:31:11.63#ibcon#read 4, iclass 27, count 0 2006.253.07:31:11.63#ibcon#about to read 5, iclass 27, count 0 2006.253.07:31:11.63#ibcon#read 5, iclass 27, count 0 2006.253.07:31:11.63#ibcon#about to read 6, iclass 27, count 0 2006.253.07:31:11.63#ibcon#read 6, iclass 27, count 0 2006.253.07:31:11.63#ibcon#end of sib2, iclass 27, count 0 2006.253.07:31:11.63#ibcon#*after write, iclass 27, count 0 2006.253.07:31:11.63#ibcon#*before return 0, iclass 27, count 0 2006.253.07:31:11.63#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.253.07:31:11.63#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.253.07:31:11.63#ibcon#about to clear, iclass 27 cls_cnt 0 2006.253.07:31:11.63#ibcon#cleared, iclass 27 cls_cnt 0 2006.253.07:31:11.63$vc4f8/vblo=4,712.99 2006.253.07:31:11.63#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.253.07:31:11.63#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.253.07:31:11.63#ibcon#ireg 17 cls_cnt 0 2006.253.07:31:11.63#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.253.07:31:11.63#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.253.07:31:11.63#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.253.07:31:11.63#ibcon#enter wrdev, iclass 29, count 0 2006.253.07:31:11.63#ibcon#first serial, iclass 29, count 0 2006.253.07:31:11.63#ibcon#enter sib2, iclass 29, count 0 2006.253.07:31:11.63#ibcon#flushed, iclass 29, count 0 2006.253.07:31:11.63#ibcon#about to write, iclass 29, count 0 2006.253.07:31:11.63#ibcon#wrote, iclass 29, count 0 2006.253.07:31:11.63#ibcon#about to read 3, iclass 29, count 0 2006.253.07:31:11.66#ibcon#read 3, iclass 29, count 0 2006.253.07:31:11.66#ibcon#about to read 4, iclass 29, count 0 2006.253.07:31:11.66#ibcon#read 4, iclass 29, count 0 2006.253.07:31:11.66#ibcon#about to read 5, iclass 29, count 0 2006.253.07:31:11.66#ibcon#read 5, iclass 29, count 0 2006.253.07:31:11.66#ibcon#about to read 6, iclass 29, count 0 2006.253.07:31:11.66#ibcon#read 6, iclass 29, count 0 2006.253.07:31:11.66#ibcon#end of sib2, iclass 29, count 0 2006.253.07:31:11.66#ibcon#*mode == 0, iclass 29, count 0 2006.253.07:31:11.66#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.253.07:31:11.66#ibcon#[28=FRQ=04,712.99\r\n] 2006.253.07:31:11.66#ibcon#*before write, iclass 29, count 0 2006.253.07:31:11.66#ibcon#enter sib2, iclass 29, count 0 2006.253.07:31:11.66#ibcon#flushed, iclass 29, count 0 2006.253.07:31:11.66#ibcon#about to write, iclass 29, count 0 2006.253.07:31:11.66#ibcon#wrote, iclass 29, count 0 2006.253.07:31:11.66#ibcon#about to read 3, iclass 29, count 0 2006.253.07:31:11.70#ibcon#read 3, iclass 29, count 0 2006.253.07:31:11.70#ibcon#about to read 4, iclass 29, count 0 2006.253.07:31:11.70#ibcon#read 4, iclass 29, count 0 2006.253.07:31:11.70#ibcon#about to read 5, iclass 29, count 0 2006.253.07:31:11.70#ibcon#read 5, iclass 29, count 0 2006.253.07:31:11.70#ibcon#about to read 6, iclass 29, count 0 2006.253.07:31:11.70#ibcon#read 6, iclass 29, count 0 2006.253.07:31:11.70#ibcon#end of sib2, iclass 29, count 0 2006.253.07:31:11.70#ibcon#*after write, iclass 29, count 0 2006.253.07:31:11.70#ibcon#*before return 0, iclass 29, count 0 2006.253.07:31:11.70#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.253.07:31:11.70#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.253.07:31:11.70#ibcon#about to clear, iclass 29 cls_cnt 0 2006.253.07:31:11.70#ibcon#cleared, iclass 29 cls_cnt 0 2006.253.07:31:11.70$vc4f8/vb=4,4 2006.253.07:31:11.70#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.253.07:31:11.70#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.253.07:31:11.70#ibcon#ireg 11 cls_cnt 2 2006.253.07:31:11.70#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.253.07:31:11.75#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.253.07:31:11.75#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.253.07:31:11.75#ibcon#enter wrdev, iclass 31, count 2 2006.253.07:31:11.75#ibcon#first serial, iclass 31, count 2 2006.253.07:31:11.75#ibcon#enter sib2, iclass 31, count 2 2006.253.07:31:11.75#ibcon#flushed, iclass 31, count 2 2006.253.07:31:11.75#ibcon#about to write, iclass 31, count 2 2006.253.07:31:11.75#ibcon#wrote, iclass 31, count 2 2006.253.07:31:11.75#ibcon#about to read 3, iclass 31, count 2 2006.253.07:31:11.77#ibcon#read 3, iclass 31, count 2 2006.253.07:31:11.77#ibcon#about to read 4, iclass 31, count 2 2006.253.07:31:11.77#ibcon#read 4, iclass 31, count 2 2006.253.07:31:11.77#ibcon#about to read 5, iclass 31, count 2 2006.253.07:31:11.77#ibcon#read 5, iclass 31, count 2 2006.253.07:31:11.77#ibcon#about to read 6, iclass 31, count 2 2006.253.07:31:11.77#ibcon#read 6, iclass 31, count 2 2006.253.07:31:11.77#ibcon#end of sib2, iclass 31, count 2 2006.253.07:31:11.77#ibcon#*mode == 0, iclass 31, count 2 2006.253.07:31:11.77#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.253.07:31:11.77#ibcon#[27=AT04-04\r\n] 2006.253.07:31:11.77#ibcon#*before write, iclass 31, count 2 2006.253.07:31:11.77#ibcon#enter sib2, iclass 31, count 2 2006.253.07:31:11.77#ibcon#flushed, iclass 31, count 2 2006.253.07:31:11.77#ibcon#about to write, iclass 31, count 2 2006.253.07:31:11.77#ibcon#wrote, iclass 31, count 2 2006.253.07:31:11.77#ibcon#about to read 3, iclass 31, count 2 2006.253.07:31:11.80#ibcon#read 3, iclass 31, count 2 2006.253.07:31:11.80#ibcon#about to read 4, iclass 31, count 2 2006.253.07:31:11.80#ibcon#read 4, iclass 31, count 2 2006.253.07:31:11.80#ibcon#about to read 5, iclass 31, count 2 2006.253.07:31:11.80#ibcon#read 5, iclass 31, count 2 2006.253.07:31:11.80#ibcon#about to read 6, iclass 31, count 2 2006.253.07:31:11.80#ibcon#read 6, iclass 31, count 2 2006.253.07:31:11.80#ibcon#end of sib2, iclass 31, count 2 2006.253.07:31:11.80#ibcon#*after write, iclass 31, count 2 2006.253.07:31:11.80#ibcon#*before return 0, iclass 31, count 2 2006.253.07:31:11.80#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.253.07:31:11.80#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.253.07:31:11.80#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.253.07:31:11.80#ibcon#ireg 7 cls_cnt 0 2006.253.07:31:11.80#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.253.07:31:11.92#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.253.07:31:11.92#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.253.07:31:11.92#ibcon#enter wrdev, iclass 31, count 0 2006.253.07:31:11.92#ibcon#first serial, iclass 31, count 0 2006.253.07:31:11.92#ibcon#enter sib2, iclass 31, count 0 2006.253.07:31:11.92#ibcon#flushed, iclass 31, count 0 2006.253.07:31:11.92#ibcon#about to write, iclass 31, count 0 2006.253.07:31:11.92#ibcon#wrote, iclass 31, count 0 2006.253.07:31:11.92#ibcon#about to read 3, iclass 31, count 0 2006.253.07:31:11.94#ibcon#read 3, iclass 31, count 0 2006.253.07:31:11.94#ibcon#about to read 4, iclass 31, count 0 2006.253.07:31:11.94#ibcon#read 4, iclass 31, count 0 2006.253.07:31:11.94#ibcon#about to read 5, iclass 31, count 0 2006.253.07:31:11.94#ibcon#read 5, iclass 31, count 0 2006.253.07:31:11.94#ibcon#about to read 6, iclass 31, count 0 2006.253.07:31:11.94#ibcon#read 6, iclass 31, count 0 2006.253.07:31:11.94#ibcon#end of sib2, iclass 31, count 0 2006.253.07:31:11.94#ibcon#*mode == 0, iclass 31, count 0 2006.253.07:31:11.94#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.253.07:31:11.94#ibcon#[27=USB\r\n] 2006.253.07:31:11.94#ibcon#*before write, iclass 31, count 0 2006.253.07:31:11.94#ibcon#enter sib2, iclass 31, count 0 2006.253.07:31:11.94#ibcon#flushed, iclass 31, count 0 2006.253.07:31:11.94#ibcon#about to write, iclass 31, count 0 2006.253.07:31:11.94#ibcon#wrote, iclass 31, count 0 2006.253.07:31:11.94#ibcon#about to read 3, iclass 31, count 0 2006.253.07:31:11.97#ibcon#read 3, iclass 31, count 0 2006.253.07:31:11.97#ibcon#about to read 4, iclass 31, count 0 2006.253.07:31:11.97#ibcon#read 4, iclass 31, count 0 2006.253.07:31:11.97#ibcon#about to read 5, iclass 31, count 0 2006.253.07:31:11.97#ibcon#read 5, iclass 31, count 0 2006.253.07:31:11.97#ibcon#about to read 6, iclass 31, count 0 2006.253.07:31:11.97#ibcon#read 6, iclass 31, count 0 2006.253.07:31:11.97#ibcon#end of sib2, iclass 31, count 0 2006.253.07:31:11.97#ibcon#*after write, iclass 31, count 0 2006.253.07:31:11.97#ibcon#*before return 0, iclass 31, count 0 2006.253.07:31:11.97#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.253.07:31:11.97#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.253.07:31:11.97#ibcon#about to clear, iclass 31 cls_cnt 0 2006.253.07:31:11.97#ibcon#cleared, iclass 31 cls_cnt 0 2006.253.07:31:11.97$vc4f8/vblo=5,744.99 2006.253.07:31:11.97#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.253.07:31:11.97#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.253.07:31:11.97#ibcon#ireg 17 cls_cnt 0 2006.253.07:31:11.97#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.253.07:31:11.97#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.253.07:31:11.97#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.253.07:31:11.97#ibcon#enter wrdev, iclass 33, count 0 2006.253.07:31:11.97#ibcon#first serial, iclass 33, count 0 2006.253.07:31:11.97#ibcon#enter sib2, iclass 33, count 0 2006.253.07:31:11.97#ibcon#flushed, iclass 33, count 0 2006.253.07:31:11.97#ibcon#about to write, iclass 33, count 0 2006.253.07:31:11.97#ibcon#wrote, iclass 33, count 0 2006.253.07:31:11.97#ibcon#about to read 3, iclass 33, count 0 2006.253.07:31:12.00#ibcon#read 3, iclass 33, count 0 2006.253.07:31:12.00#ibcon#about to read 4, iclass 33, count 0 2006.253.07:31:12.00#ibcon#read 4, iclass 33, count 0 2006.253.07:31:12.00#ibcon#about to read 5, iclass 33, count 0 2006.253.07:31:12.00#ibcon#read 5, iclass 33, count 0 2006.253.07:31:12.00#ibcon#about to read 6, iclass 33, count 0 2006.253.07:31:12.00#ibcon#read 6, iclass 33, count 0 2006.253.07:31:12.00#ibcon#end of sib2, iclass 33, count 0 2006.253.07:31:12.00#ibcon#*mode == 0, iclass 33, count 0 2006.253.07:31:12.00#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.253.07:31:12.00#ibcon#[28=FRQ=05,744.99\r\n] 2006.253.07:31:12.00#ibcon#*before write, iclass 33, count 0 2006.253.07:31:12.00#ibcon#enter sib2, iclass 33, count 0 2006.253.07:31:12.00#ibcon#flushed, iclass 33, count 0 2006.253.07:31:12.00#ibcon#about to write, iclass 33, count 0 2006.253.07:31:12.00#ibcon#wrote, iclass 33, count 0 2006.253.07:31:12.00#ibcon#about to read 3, iclass 33, count 0 2006.253.07:31:12.04#ibcon#read 3, iclass 33, count 0 2006.253.07:31:12.04#ibcon#about to read 4, iclass 33, count 0 2006.253.07:31:12.04#ibcon#read 4, iclass 33, count 0 2006.253.07:31:12.04#ibcon#about to read 5, iclass 33, count 0 2006.253.07:31:12.04#ibcon#read 5, iclass 33, count 0 2006.253.07:31:12.04#ibcon#about to read 6, iclass 33, count 0 2006.253.07:31:12.04#ibcon#read 6, iclass 33, count 0 2006.253.07:31:12.04#ibcon#end of sib2, iclass 33, count 0 2006.253.07:31:12.04#ibcon#*after write, iclass 33, count 0 2006.253.07:31:12.04#ibcon#*before return 0, iclass 33, count 0 2006.253.07:31:12.04#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.253.07:31:12.04#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.253.07:31:12.04#ibcon#about to clear, iclass 33 cls_cnt 0 2006.253.07:31:12.04#ibcon#cleared, iclass 33 cls_cnt 0 2006.253.07:31:12.04$vc4f8/vb=5,4 2006.253.07:31:12.04#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.253.07:31:12.04#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.253.07:31:12.04#ibcon#ireg 11 cls_cnt 2 2006.253.07:31:12.04#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.253.07:31:12.09#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.253.07:31:12.09#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.253.07:31:12.09#ibcon#enter wrdev, iclass 35, count 2 2006.253.07:31:12.09#ibcon#first serial, iclass 35, count 2 2006.253.07:31:12.09#ibcon#enter sib2, iclass 35, count 2 2006.253.07:31:12.09#ibcon#flushed, iclass 35, count 2 2006.253.07:31:12.09#ibcon#about to write, iclass 35, count 2 2006.253.07:31:12.09#ibcon#wrote, iclass 35, count 2 2006.253.07:31:12.09#ibcon#about to read 3, iclass 35, count 2 2006.253.07:31:12.11#ibcon#read 3, iclass 35, count 2 2006.253.07:31:12.11#ibcon#about to read 4, iclass 35, count 2 2006.253.07:31:12.11#ibcon#read 4, iclass 35, count 2 2006.253.07:31:12.11#ibcon#about to read 5, iclass 35, count 2 2006.253.07:31:12.11#ibcon#read 5, iclass 35, count 2 2006.253.07:31:12.11#ibcon#about to read 6, iclass 35, count 2 2006.253.07:31:12.11#ibcon#read 6, iclass 35, count 2 2006.253.07:31:12.11#ibcon#end of sib2, iclass 35, count 2 2006.253.07:31:12.11#ibcon#*mode == 0, iclass 35, count 2 2006.253.07:31:12.11#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.253.07:31:12.11#ibcon#[27=AT05-04\r\n] 2006.253.07:31:12.11#ibcon#*before write, iclass 35, count 2 2006.253.07:31:12.11#ibcon#enter sib2, iclass 35, count 2 2006.253.07:31:12.11#ibcon#flushed, iclass 35, count 2 2006.253.07:31:12.11#ibcon#about to write, iclass 35, count 2 2006.253.07:31:12.11#ibcon#wrote, iclass 35, count 2 2006.253.07:31:12.11#ibcon#about to read 3, iclass 35, count 2 2006.253.07:31:12.14#ibcon#read 3, iclass 35, count 2 2006.253.07:31:12.14#ibcon#about to read 4, iclass 35, count 2 2006.253.07:31:12.14#ibcon#read 4, iclass 35, count 2 2006.253.07:31:12.14#ibcon#about to read 5, iclass 35, count 2 2006.253.07:31:12.14#ibcon#read 5, iclass 35, count 2 2006.253.07:31:12.14#ibcon#about to read 6, iclass 35, count 2 2006.253.07:31:12.14#ibcon#read 6, iclass 35, count 2 2006.253.07:31:12.14#ibcon#end of sib2, iclass 35, count 2 2006.253.07:31:12.14#ibcon#*after write, iclass 35, count 2 2006.253.07:31:12.14#ibcon#*before return 0, iclass 35, count 2 2006.253.07:31:12.14#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.253.07:31:12.14#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.253.07:31:12.14#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.253.07:31:12.14#ibcon#ireg 7 cls_cnt 0 2006.253.07:31:12.14#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.253.07:31:12.26#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.253.07:31:12.26#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.253.07:31:12.26#ibcon#enter wrdev, iclass 35, count 0 2006.253.07:31:12.26#ibcon#first serial, iclass 35, count 0 2006.253.07:31:12.26#ibcon#enter sib2, iclass 35, count 0 2006.253.07:31:12.26#ibcon#flushed, iclass 35, count 0 2006.253.07:31:12.26#ibcon#about to write, iclass 35, count 0 2006.253.07:31:12.26#ibcon#wrote, iclass 35, count 0 2006.253.07:31:12.26#ibcon#about to read 3, iclass 35, count 0 2006.253.07:31:12.28#ibcon#read 3, iclass 35, count 0 2006.253.07:31:12.28#ibcon#about to read 4, iclass 35, count 0 2006.253.07:31:12.28#ibcon#read 4, iclass 35, count 0 2006.253.07:31:12.28#ibcon#about to read 5, iclass 35, count 0 2006.253.07:31:12.28#ibcon#read 5, iclass 35, count 0 2006.253.07:31:12.28#ibcon#about to read 6, iclass 35, count 0 2006.253.07:31:12.28#ibcon#read 6, iclass 35, count 0 2006.253.07:31:12.28#ibcon#end of sib2, iclass 35, count 0 2006.253.07:31:12.28#ibcon#*mode == 0, iclass 35, count 0 2006.253.07:31:12.28#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.253.07:31:12.28#ibcon#[27=USB\r\n] 2006.253.07:31:12.28#ibcon#*before write, iclass 35, count 0 2006.253.07:31:12.28#ibcon#enter sib2, iclass 35, count 0 2006.253.07:31:12.28#ibcon#flushed, iclass 35, count 0 2006.253.07:31:12.28#ibcon#about to write, iclass 35, count 0 2006.253.07:31:12.28#ibcon#wrote, iclass 35, count 0 2006.253.07:31:12.28#ibcon#about to read 3, iclass 35, count 0 2006.253.07:31:12.31#ibcon#read 3, iclass 35, count 0 2006.253.07:31:12.31#ibcon#about to read 4, iclass 35, count 0 2006.253.07:31:12.31#ibcon#read 4, iclass 35, count 0 2006.253.07:31:12.31#ibcon#about to read 5, iclass 35, count 0 2006.253.07:31:12.31#ibcon#read 5, iclass 35, count 0 2006.253.07:31:12.31#ibcon#about to read 6, iclass 35, count 0 2006.253.07:31:12.31#ibcon#read 6, iclass 35, count 0 2006.253.07:31:12.31#ibcon#end of sib2, iclass 35, count 0 2006.253.07:31:12.31#ibcon#*after write, iclass 35, count 0 2006.253.07:31:12.31#ibcon#*before return 0, iclass 35, count 0 2006.253.07:31:12.31#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.253.07:31:12.31#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.253.07:31:12.31#ibcon#about to clear, iclass 35 cls_cnt 0 2006.253.07:31:12.31#ibcon#cleared, iclass 35 cls_cnt 0 2006.253.07:31:12.31$vc4f8/vblo=6,752.99 2006.253.07:31:12.31#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.253.07:31:12.31#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.253.07:31:12.31#ibcon#ireg 17 cls_cnt 0 2006.253.07:31:12.31#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.253.07:31:12.31#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.253.07:31:12.31#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.253.07:31:12.31#ibcon#enter wrdev, iclass 37, count 0 2006.253.07:31:12.31#ibcon#first serial, iclass 37, count 0 2006.253.07:31:12.31#ibcon#enter sib2, iclass 37, count 0 2006.253.07:31:12.31#ibcon#flushed, iclass 37, count 0 2006.253.07:31:12.31#ibcon#about to write, iclass 37, count 0 2006.253.07:31:12.31#ibcon#wrote, iclass 37, count 0 2006.253.07:31:12.31#ibcon#about to read 3, iclass 37, count 0 2006.253.07:31:12.34#ibcon#read 3, iclass 37, count 0 2006.253.07:31:12.34#ibcon#about to read 4, iclass 37, count 0 2006.253.07:31:12.34#ibcon#read 4, iclass 37, count 0 2006.253.07:31:12.34#ibcon#about to read 5, iclass 37, count 0 2006.253.07:31:12.34#ibcon#read 5, iclass 37, count 0 2006.253.07:31:12.34#ibcon#about to read 6, iclass 37, count 0 2006.253.07:31:12.34#ibcon#read 6, iclass 37, count 0 2006.253.07:31:12.34#ibcon#end of sib2, iclass 37, count 0 2006.253.07:31:12.34#ibcon#*mode == 0, iclass 37, count 0 2006.253.07:31:12.34#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.253.07:31:12.34#ibcon#[28=FRQ=06,752.99\r\n] 2006.253.07:31:12.34#ibcon#*before write, iclass 37, count 0 2006.253.07:31:12.34#ibcon#enter sib2, iclass 37, count 0 2006.253.07:31:12.34#ibcon#flushed, iclass 37, count 0 2006.253.07:31:12.34#ibcon#about to write, iclass 37, count 0 2006.253.07:31:12.34#ibcon#wrote, iclass 37, count 0 2006.253.07:31:12.34#ibcon#about to read 3, iclass 37, count 0 2006.253.07:31:12.38#ibcon#read 3, iclass 37, count 0 2006.253.07:31:12.38#ibcon#about to read 4, iclass 37, count 0 2006.253.07:31:12.38#ibcon#read 4, iclass 37, count 0 2006.253.07:31:12.38#ibcon#about to read 5, iclass 37, count 0 2006.253.07:31:12.38#ibcon#read 5, iclass 37, count 0 2006.253.07:31:12.38#ibcon#about to read 6, iclass 37, count 0 2006.253.07:31:12.38#ibcon#read 6, iclass 37, count 0 2006.253.07:31:12.38#ibcon#end of sib2, iclass 37, count 0 2006.253.07:31:12.38#ibcon#*after write, iclass 37, count 0 2006.253.07:31:12.38#ibcon#*before return 0, iclass 37, count 0 2006.253.07:31:12.38#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.253.07:31:12.38#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.253.07:31:12.38#ibcon#about to clear, iclass 37 cls_cnt 0 2006.253.07:31:12.38#ibcon#cleared, iclass 37 cls_cnt 0 2006.253.07:31:12.38$vc4f8/vb=6,4 2006.253.07:31:12.38#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.253.07:31:12.38#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.253.07:31:12.38#ibcon#ireg 11 cls_cnt 2 2006.253.07:31:12.38#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.253.07:31:12.43#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.253.07:31:12.43#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.253.07:31:12.43#ibcon#enter wrdev, iclass 39, count 2 2006.253.07:31:12.43#ibcon#first serial, iclass 39, count 2 2006.253.07:31:12.43#ibcon#enter sib2, iclass 39, count 2 2006.253.07:31:12.43#ibcon#flushed, iclass 39, count 2 2006.253.07:31:12.43#ibcon#about to write, iclass 39, count 2 2006.253.07:31:12.43#ibcon#wrote, iclass 39, count 2 2006.253.07:31:12.43#ibcon#about to read 3, iclass 39, count 2 2006.253.07:31:12.45#ibcon#read 3, iclass 39, count 2 2006.253.07:31:12.45#ibcon#about to read 4, iclass 39, count 2 2006.253.07:31:12.45#ibcon#read 4, iclass 39, count 2 2006.253.07:31:12.45#ibcon#about to read 5, iclass 39, count 2 2006.253.07:31:12.45#ibcon#read 5, iclass 39, count 2 2006.253.07:31:12.45#ibcon#about to read 6, iclass 39, count 2 2006.253.07:31:12.45#ibcon#read 6, iclass 39, count 2 2006.253.07:31:12.45#ibcon#end of sib2, iclass 39, count 2 2006.253.07:31:12.45#ibcon#*mode == 0, iclass 39, count 2 2006.253.07:31:12.45#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.253.07:31:12.45#ibcon#[27=AT06-04\r\n] 2006.253.07:31:12.45#ibcon#*before write, iclass 39, count 2 2006.253.07:31:12.45#ibcon#enter sib2, iclass 39, count 2 2006.253.07:31:12.45#ibcon#flushed, iclass 39, count 2 2006.253.07:31:12.45#ibcon#about to write, iclass 39, count 2 2006.253.07:31:12.45#ibcon#wrote, iclass 39, count 2 2006.253.07:31:12.45#ibcon#about to read 3, iclass 39, count 2 2006.253.07:31:12.48#ibcon#read 3, iclass 39, count 2 2006.253.07:31:12.48#ibcon#about to read 4, iclass 39, count 2 2006.253.07:31:12.48#ibcon#read 4, iclass 39, count 2 2006.253.07:31:12.48#ibcon#about to read 5, iclass 39, count 2 2006.253.07:31:12.48#ibcon#read 5, iclass 39, count 2 2006.253.07:31:12.48#ibcon#about to read 6, iclass 39, count 2 2006.253.07:31:12.48#ibcon#read 6, iclass 39, count 2 2006.253.07:31:12.48#ibcon#end of sib2, iclass 39, count 2 2006.253.07:31:12.48#ibcon#*after write, iclass 39, count 2 2006.253.07:31:12.48#ibcon#*before return 0, iclass 39, count 2 2006.253.07:31:12.48#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.253.07:31:12.48#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.253.07:31:12.48#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.253.07:31:12.48#ibcon#ireg 7 cls_cnt 0 2006.253.07:31:12.48#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.253.07:31:12.60#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.253.07:31:12.60#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.253.07:31:12.60#ibcon#enter wrdev, iclass 39, count 0 2006.253.07:31:12.60#ibcon#first serial, iclass 39, count 0 2006.253.07:31:12.60#ibcon#enter sib2, iclass 39, count 0 2006.253.07:31:12.60#ibcon#flushed, iclass 39, count 0 2006.253.07:31:12.60#ibcon#about to write, iclass 39, count 0 2006.253.07:31:12.60#ibcon#wrote, iclass 39, count 0 2006.253.07:31:12.60#ibcon#about to read 3, iclass 39, count 0 2006.253.07:31:12.62#ibcon#read 3, iclass 39, count 0 2006.253.07:31:12.62#ibcon#about to read 4, iclass 39, count 0 2006.253.07:31:12.62#ibcon#read 4, iclass 39, count 0 2006.253.07:31:12.62#ibcon#about to read 5, iclass 39, count 0 2006.253.07:31:12.62#ibcon#read 5, iclass 39, count 0 2006.253.07:31:12.62#ibcon#about to read 6, iclass 39, count 0 2006.253.07:31:12.62#ibcon#read 6, iclass 39, count 0 2006.253.07:31:12.62#ibcon#end of sib2, iclass 39, count 0 2006.253.07:31:12.62#ibcon#*mode == 0, iclass 39, count 0 2006.253.07:31:12.62#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.253.07:31:12.62#ibcon#[27=USB\r\n] 2006.253.07:31:12.62#ibcon#*before write, iclass 39, count 0 2006.253.07:31:12.62#ibcon#enter sib2, iclass 39, count 0 2006.253.07:31:12.62#ibcon#flushed, iclass 39, count 0 2006.253.07:31:12.62#ibcon#about to write, iclass 39, count 0 2006.253.07:31:12.62#ibcon#wrote, iclass 39, count 0 2006.253.07:31:12.62#ibcon#about to read 3, iclass 39, count 0 2006.253.07:31:12.65#ibcon#read 3, iclass 39, count 0 2006.253.07:31:12.65#ibcon#about to read 4, iclass 39, count 0 2006.253.07:31:12.65#ibcon#read 4, iclass 39, count 0 2006.253.07:31:12.65#ibcon#about to read 5, iclass 39, count 0 2006.253.07:31:12.65#ibcon#read 5, iclass 39, count 0 2006.253.07:31:12.65#ibcon#about to read 6, iclass 39, count 0 2006.253.07:31:12.65#ibcon#read 6, iclass 39, count 0 2006.253.07:31:12.65#ibcon#end of sib2, iclass 39, count 0 2006.253.07:31:12.65#ibcon#*after write, iclass 39, count 0 2006.253.07:31:12.65#ibcon#*before return 0, iclass 39, count 0 2006.253.07:31:12.65#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.253.07:31:12.65#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.253.07:31:12.65#ibcon#about to clear, iclass 39 cls_cnt 0 2006.253.07:31:12.65#ibcon#cleared, iclass 39 cls_cnt 0 2006.253.07:31:12.65$vc4f8/vabw=wide 2006.253.07:31:12.65#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.253.07:31:12.65#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.253.07:31:12.65#ibcon#ireg 8 cls_cnt 0 2006.253.07:31:12.65#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.253.07:31:12.65#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.253.07:31:12.65#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.253.07:31:12.65#ibcon#enter wrdev, iclass 3, count 0 2006.253.07:31:12.65#ibcon#first serial, iclass 3, count 0 2006.253.07:31:12.65#ibcon#enter sib2, iclass 3, count 0 2006.253.07:31:12.65#ibcon#flushed, iclass 3, count 0 2006.253.07:31:12.65#ibcon#about to write, iclass 3, count 0 2006.253.07:31:12.65#ibcon#wrote, iclass 3, count 0 2006.253.07:31:12.65#ibcon#about to read 3, iclass 3, count 0 2006.253.07:31:12.68#ibcon#read 3, iclass 3, count 0 2006.253.07:31:12.68#ibcon#about to read 4, iclass 3, count 0 2006.253.07:31:12.68#ibcon#read 4, iclass 3, count 0 2006.253.07:31:12.68#ibcon#about to read 5, iclass 3, count 0 2006.253.07:31:12.68#ibcon#read 5, iclass 3, count 0 2006.253.07:31:12.68#ibcon#about to read 6, iclass 3, count 0 2006.253.07:31:12.68#ibcon#read 6, iclass 3, count 0 2006.253.07:31:12.68#ibcon#end of sib2, iclass 3, count 0 2006.253.07:31:12.68#ibcon#*mode == 0, iclass 3, count 0 2006.253.07:31:12.68#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.253.07:31:12.68#ibcon#[25=BW32\r\n] 2006.253.07:31:12.68#ibcon#*before write, iclass 3, count 0 2006.253.07:31:12.68#ibcon#enter sib2, iclass 3, count 0 2006.253.07:31:12.68#ibcon#flushed, iclass 3, count 0 2006.253.07:31:12.68#ibcon#about to write, iclass 3, count 0 2006.253.07:31:12.68#ibcon#wrote, iclass 3, count 0 2006.253.07:31:12.68#ibcon#about to read 3, iclass 3, count 0 2006.253.07:31:12.71#ibcon#read 3, iclass 3, count 0 2006.253.07:31:12.71#ibcon#about to read 4, iclass 3, count 0 2006.253.07:31:12.71#ibcon#read 4, iclass 3, count 0 2006.253.07:31:12.71#ibcon#about to read 5, iclass 3, count 0 2006.253.07:31:12.71#ibcon#read 5, iclass 3, count 0 2006.253.07:31:12.71#ibcon#about to read 6, iclass 3, count 0 2006.253.07:31:12.71#ibcon#read 6, iclass 3, count 0 2006.253.07:31:12.71#ibcon#end of sib2, iclass 3, count 0 2006.253.07:31:12.71#ibcon#*after write, iclass 3, count 0 2006.253.07:31:12.71#ibcon#*before return 0, iclass 3, count 0 2006.253.07:31:12.71#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.253.07:31:12.71#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.253.07:31:12.71#ibcon#about to clear, iclass 3 cls_cnt 0 2006.253.07:31:12.71#ibcon#cleared, iclass 3 cls_cnt 0 2006.253.07:31:12.71$vc4f8/vbbw=wide 2006.253.07:31:12.71#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.253.07:31:12.71#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.253.07:31:12.71#ibcon#ireg 8 cls_cnt 0 2006.253.07:31:12.71#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.253.07:31:12.77#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.253.07:31:12.77#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.253.07:31:12.77#ibcon#enter wrdev, iclass 5, count 0 2006.253.07:31:12.77#ibcon#first serial, iclass 5, count 0 2006.253.07:31:12.77#ibcon#enter sib2, iclass 5, count 0 2006.253.07:31:12.77#ibcon#flushed, iclass 5, count 0 2006.253.07:31:12.77#ibcon#about to write, iclass 5, count 0 2006.253.07:31:12.77#ibcon#wrote, iclass 5, count 0 2006.253.07:31:12.77#ibcon#about to read 3, iclass 5, count 0 2006.253.07:31:12.79#ibcon#read 3, iclass 5, count 0 2006.253.07:31:12.79#ibcon#about to read 4, iclass 5, count 0 2006.253.07:31:12.79#ibcon#read 4, iclass 5, count 0 2006.253.07:31:12.79#ibcon#about to read 5, iclass 5, count 0 2006.253.07:31:12.79#ibcon#read 5, iclass 5, count 0 2006.253.07:31:12.79#ibcon#about to read 6, iclass 5, count 0 2006.253.07:31:12.79#ibcon#read 6, iclass 5, count 0 2006.253.07:31:12.79#ibcon#end of sib2, iclass 5, count 0 2006.253.07:31:12.79#ibcon#*mode == 0, iclass 5, count 0 2006.253.07:31:12.79#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.253.07:31:12.79#ibcon#[27=BW32\r\n] 2006.253.07:31:12.79#ibcon#*before write, iclass 5, count 0 2006.253.07:31:12.79#ibcon#enter sib2, iclass 5, count 0 2006.253.07:31:12.79#ibcon#flushed, iclass 5, count 0 2006.253.07:31:12.79#ibcon#about to write, iclass 5, count 0 2006.253.07:31:12.79#ibcon#wrote, iclass 5, count 0 2006.253.07:31:12.79#ibcon#about to read 3, iclass 5, count 0 2006.253.07:31:12.82#ibcon#read 3, iclass 5, count 0 2006.253.07:31:12.82#ibcon#about to read 4, iclass 5, count 0 2006.253.07:31:12.82#ibcon#read 4, iclass 5, count 0 2006.253.07:31:12.82#ibcon#about to read 5, iclass 5, count 0 2006.253.07:31:12.82#ibcon#read 5, iclass 5, count 0 2006.253.07:31:12.82#ibcon#about to read 6, iclass 5, count 0 2006.253.07:31:12.82#ibcon#read 6, iclass 5, count 0 2006.253.07:31:12.82#ibcon#end of sib2, iclass 5, count 0 2006.253.07:31:12.82#ibcon#*after write, iclass 5, count 0 2006.253.07:31:12.82#ibcon#*before return 0, iclass 5, count 0 2006.253.07:31:12.82#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.253.07:31:12.82#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.253.07:31:12.82#ibcon#about to clear, iclass 5 cls_cnt 0 2006.253.07:31:12.82#ibcon#cleared, iclass 5 cls_cnt 0 2006.253.07:31:12.82$4f8m12a/ifd4f 2006.253.07:31:12.82$ifd4f/lo= 2006.253.07:31:12.82$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.253.07:31:12.82$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.253.07:31:12.82$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.253.07:31:12.82$ifd4f/patch= 2006.253.07:31:12.82$ifd4f/patch=lo1,a1,a2,a3,a4 2006.253.07:31:12.82$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.253.07:31:12.82$ifd4f/patch=lo3,a5,a6,a7,a8 2006.253.07:31:12.82$4f8m12a/"form=m,16.000,1:2 2006.253.07:31:12.82$4f8m12a/"tpicd 2006.253.07:31:12.82$4f8m12a/echo=off 2006.253.07:31:12.82$4f8m12a/xlog=off 2006.253.07:31:12.82:!2006.253.07:33:20 2006.253.07:31:25.14#trakl#Source acquired 2006.253.07:31:25.14#flagr#flagr/antenna,acquired 2006.253.07:33:20.00:preob 2006.253.07:33:20.14/onsource/TRACKING 2006.253.07:33:20.14:!2006.253.07:33:30 2006.253.07:33:30.00:data_valid=on 2006.253.07:33:30.00:midob 2006.253.07:33:31.14/onsource/TRACKING 2006.253.07:33:31.14/wx/31.58,1006.3,72 2006.253.07:33:31.27/cable/+6.3696E-03 2006.253.07:33:32.36/va/01,08,usb,yes,32,34 2006.253.07:33:32.36/va/02,07,usb,yes,32,34 2006.253.07:33:32.36/va/03,06,usb,yes,34,35 2006.253.07:33:32.36/va/04,07,usb,yes,33,36 2006.253.07:33:32.36/va/05,07,usb,yes,35,36 2006.253.07:33:32.36/va/06,07,usb,yes,30,30 2006.253.07:33:32.36/va/07,07,usb,yes,30,30 2006.253.07:33:32.36/va/08,07,usb,yes,32,32 2006.253.07:33:32.59/valo/01,532.99,yes,locked 2006.253.07:33:32.59/valo/02,572.99,yes,locked 2006.253.07:33:32.59/valo/03,672.99,yes,locked 2006.253.07:33:32.59/valo/04,832.99,yes,locked 2006.253.07:33:32.59/valo/05,652.99,yes,locked 2006.253.07:33:32.59/valo/06,772.99,yes,locked 2006.253.07:33:32.59/valo/07,832.99,yes,locked 2006.253.07:33:32.59/valo/08,852.99,yes,locked 2006.253.07:33:33.68/vb/01,04,usb,yes,31,30 2006.253.07:33:33.68/vb/02,05,usb,yes,29,30 2006.253.07:33:33.68/vb/03,04,usb,yes,29,33 2006.253.07:33:33.68/vb/04,04,usb,yes,30,30 2006.253.07:33:33.68/vb/05,04,usb,yes,28,32 2006.253.07:33:33.68/vb/06,04,usb,yes,29,32 2006.253.07:33:33.68/vb/07,04,usb,yes,32,31 2006.253.07:33:33.68/vb/08,04,usb,yes,29,32 2006.253.07:33:33.92/vblo/01,632.99,yes,locked 2006.253.07:33:33.92/vblo/02,640.99,yes,locked 2006.253.07:33:33.92/vblo/03,656.99,yes,locked 2006.253.07:33:33.92/vblo/04,712.99,yes,locked 2006.253.07:33:33.92/vblo/05,744.99,yes,locked 2006.253.07:33:33.92/vblo/06,752.99,yes,locked 2006.253.07:33:33.92/vblo/07,734.99,yes,locked 2006.253.07:33:33.92/vblo/08,744.99,yes,locked 2006.253.07:33:34.07/vabw/8 2006.253.07:33:34.22/vbbw/8 2006.253.07:33:34.31/xfe/off,on,14.7 2006.253.07:33:34.69/ifatt/23,28,28,28 2006.253.07:33:35.08/fmout-gps/S +4.77E-07 2006.253.07:33:35.12:!2006.253.07:34:50 2006.253.07:34:50.00:data_valid=off 2006.253.07:34:50.00:postob 2006.253.07:34:50.09/cable/+6.3698E-03 2006.253.07:34:50.09/wx/31.56,1006.3,72 2006.253.07:34:51.08/fmout-gps/S +4.77E-07 2006.253.07:34:51.08:scan_name=253-0736,k06253,60 2006.253.07:34:51.08:source=1357+769,135755.37,764321.1,2000.0,ccw 2006.253.07:34:52.14#flagr#flagr/antenna,new-source 2006.253.07:34:52.14:checkk5 2006.253.07:34:52.52/chk_autoobs//k5ts1/ autoobs is running! 2006.253.07:34:52.89/chk_autoobs//k5ts2/ autoobs is running! 2006.253.07:34:53.27/chk_autoobs//k5ts3/ autoobs is running! 2006.253.07:34:53.64/chk_autoobs//k5ts4/ autoobs is running! 2006.253.07:34:54.01/chk_obsdata//k5ts1/T2530733??a.dat file size is correct (nominal:640MB, actual:632MB). 2006.253.07:34:54.38/chk_obsdata//k5ts2/T2530733??b.dat file size is correct (nominal:640MB, actual:632MB). 2006.253.07:34:54.75/chk_obsdata//k5ts3/T2530733??c.dat file size is correct (nominal:640MB, actual:632MB). 2006.253.07:34:55.12/chk_obsdata//k5ts4/T2530733??d.dat file size is correct (nominal:640MB, actual:632MB). 2006.253.07:34:55.82/k5log//k5ts1_log_newline 2006.253.07:34:56.52/k5log//k5ts2_log_newline 2006.253.07:34:57.20/k5log//k5ts3_log_newline 2006.253.07:34:57.89/k5log//k5ts4_log_newline 2006.253.07:34:57.92/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.253.07:34:57.92:4f8m12a=1 2006.253.07:34:57.92$4f8m12a/echo=on 2006.253.07:34:57.92$4f8m12a/pcalon 2006.253.07:34:57.92$pcalon/"no phase cal control is implemented here 2006.253.07:34:57.92$4f8m12a/"tpicd=stop 2006.253.07:34:57.92$4f8m12a/vc4f8 2006.253.07:34:57.92$vc4f8/valo=1,532.99 2006.253.07:34:57.93#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.253.07:34:57.93#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.253.07:34:57.93#ibcon#ireg 17 cls_cnt 0 2006.253.07:34:57.93#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.253.07:34:57.93#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.253.07:34:57.93#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.253.07:34:57.93#ibcon#enter wrdev, iclass 26, count 0 2006.253.07:34:57.93#ibcon#first serial, iclass 26, count 0 2006.253.07:34:57.93#ibcon#enter sib2, iclass 26, count 0 2006.253.07:34:57.93#ibcon#flushed, iclass 26, count 0 2006.253.07:34:57.93#ibcon#about to write, iclass 26, count 0 2006.253.07:34:57.93#ibcon#wrote, iclass 26, count 0 2006.253.07:34:57.93#ibcon#about to read 3, iclass 26, count 0 2006.253.07:34:57.96#ibcon#read 3, iclass 26, count 0 2006.253.07:34:57.96#ibcon#about to read 4, iclass 26, count 0 2006.253.07:34:57.96#ibcon#read 4, iclass 26, count 0 2006.253.07:34:57.96#ibcon#about to read 5, iclass 26, count 0 2006.253.07:34:57.96#ibcon#read 5, iclass 26, count 0 2006.253.07:34:57.96#ibcon#about to read 6, iclass 26, count 0 2006.253.07:34:57.96#ibcon#read 6, iclass 26, count 0 2006.253.07:34:57.96#ibcon#end of sib2, iclass 26, count 0 2006.253.07:34:57.96#ibcon#*mode == 0, iclass 26, count 0 2006.253.07:34:57.96#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.253.07:34:57.96#ibcon#[26=FRQ=01,532.99\r\n] 2006.253.07:34:57.96#ibcon#*before write, iclass 26, count 0 2006.253.07:34:57.96#ibcon#enter sib2, iclass 26, count 0 2006.253.07:34:57.97#ibcon#flushed, iclass 26, count 0 2006.253.07:34:57.97#ibcon#about to write, iclass 26, count 0 2006.253.07:34:57.97#ibcon#wrote, iclass 26, count 0 2006.253.07:34:57.97#ibcon#about to read 3, iclass 26, count 0 2006.253.07:34:58.01#ibcon#read 3, iclass 26, count 0 2006.253.07:34:58.01#ibcon#about to read 4, iclass 26, count 0 2006.253.07:34:58.01#ibcon#read 4, iclass 26, count 0 2006.253.07:34:58.01#ibcon#about to read 5, iclass 26, count 0 2006.253.07:34:58.01#ibcon#read 5, iclass 26, count 0 2006.253.07:34:58.01#ibcon#about to read 6, iclass 26, count 0 2006.253.07:34:58.01#ibcon#read 6, iclass 26, count 0 2006.253.07:34:58.01#ibcon#end of sib2, iclass 26, count 0 2006.253.07:34:58.01#ibcon#*after write, iclass 26, count 0 2006.253.07:34:58.01#ibcon#*before return 0, iclass 26, count 0 2006.253.07:34:58.01#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.253.07:34:58.01#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.253.07:34:58.01#ibcon#about to clear, iclass 26 cls_cnt 0 2006.253.07:34:58.01#ibcon#cleared, iclass 26 cls_cnt 0 2006.253.07:34:58.01$vc4f8/va=1,8 2006.253.07:34:58.01#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.253.07:34:58.01#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.253.07:34:58.01#ibcon#ireg 11 cls_cnt 2 2006.253.07:34:58.01#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.253.07:34:58.01#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.253.07:34:58.01#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.253.07:34:58.01#ibcon#enter wrdev, iclass 28, count 2 2006.253.07:34:58.01#ibcon#first serial, iclass 28, count 2 2006.253.07:34:58.01#ibcon#enter sib2, iclass 28, count 2 2006.253.07:34:58.01#ibcon#flushed, iclass 28, count 2 2006.253.07:34:58.01#ibcon#about to write, iclass 28, count 2 2006.253.07:34:58.01#ibcon#wrote, iclass 28, count 2 2006.253.07:34:58.01#ibcon#about to read 3, iclass 28, count 2 2006.253.07:34:58.03#ibcon#read 3, iclass 28, count 2 2006.253.07:34:58.03#ibcon#about to read 4, iclass 28, count 2 2006.253.07:34:58.03#ibcon#read 4, iclass 28, count 2 2006.253.07:34:58.03#ibcon#about to read 5, iclass 28, count 2 2006.253.07:34:58.03#ibcon#read 5, iclass 28, count 2 2006.253.07:34:58.03#ibcon#about to read 6, iclass 28, count 2 2006.253.07:34:58.03#ibcon#read 6, iclass 28, count 2 2006.253.07:34:58.03#ibcon#end of sib2, iclass 28, count 2 2006.253.07:34:58.03#ibcon#*mode == 0, iclass 28, count 2 2006.253.07:34:58.03#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.253.07:34:58.03#ibcon#[25=AT01-08\r\n] 2006.253.07:34:58.03#ibcon#*before write, iclass 28, count 2 2006.253.07:34:58.03#ibcon#enter sib2, iclass 28, count 2 2006.253.07:34:58.03#ibcon#flushed, iclass 28, count 2 2006.253.07:34:58.03#ibcon#about to write, iclass 28, count 2 2006.253.07:34:58.03#ibcon#wrote, iclass 28, count 2 2006.253.07:34:58.03#ibcon#about to read 3, iclass 28, count 2 2006.253.07:34:58.06#ibcon#read 3, iclass 28, count 2 2006.253.07:34:58.06#ibcon#about to read 4, iclass 28, count 2 2006.253.07:34:58.06#ibcon#read 4, iclass 28, count 2 2006.253.07:34:58.06#ibcon#about to read 5, iclass 28, count 2 2006.253.07:34:58.06#ibcon#read 5, iclass 28, count 2 2006.253.07:34:58.06#ibcon#about to read 6, iclass 28, count 2 2006.253.07:34:58.06#ibcon#read 6, iclass 28, count 2 2006.253.07:34:58.06#ibcon#end of sib2, iclass 28, count 2 2006.253.07:34:58.06#ibcon#*after write, iclass 28, count 2 2006.253.07:34:58.06#ibcon#*before return 0, iclass 28, count 2 2006.253.07:34:58.06#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.253.07:34:58.06#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.253.07:34:58.06#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.253.07:34:58.06#ibcon#ireg 7 cls_cnt 0 2006.253.07:34:58.06#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.253.07:34:58.18#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.253.07:34:58.18#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.253.07:34:58.18#ibcon#enter wrdev, iclass 28, count 0 2006.253.07:34:58.18#ibcon#first serial, iclass 28, count 0 2006.253.07:34:58.18#ibcon#enter sib2, iclass 28, count 0 2006.253.07:34:58.18#ibcon#flushed, iclass 28, count 0 2006.253.07:34:58.18#ibcon#about to write, iclass 28, count 0 2006.253.07:34:58.18#ibcon#wrote, iclass 28, count 0 2006.253.07:34:58.18#ibcon#about to read 3, iclass 28, count 0 2006.253.07:34:58.20#ibcon#read 3, iclass 28, count 0 2006.253.07:34:58.20#ibcon#about to read 4, iclass 28, count 0 2006.253.07:34:58.20#ibcon#read 4, iclass 28, count 0 2006.253.07:34:58.20#ibcon#about to read 5, iclass 28, count 0 2006.253.07:34:58.20#ibcon#read 5, iclass 28, count 0 2006.253.07:34:58.20#ibcon#about to read 6, iclass 28, count 0 2006.253.07:34:58.20#ibcon#read 6, iclass 28, count 0 2006.253.07:34:58.20#ibcon#end of sib2, iclass 28, count 0 2006.253.07:34:58.20#ibcon#*mode == 0, iclass 28, count 0 2006.253.07:34:58.20#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.253.07:34:58.20#ibcon#[25=USB\r\n] 2006.253.07:34:58.20#ibcon#*before write, iclass 28, count 0 2006.253.07:34:58.20#ibcon#enter sib2, iclass 28, count 0 2006.253.07:34:58.20#ibcon#flushed, iclass 28, count 0 2006.253.07:34:58.20#ibcon#about to write, iclass 28, count 0 2006.253.07:34:58.20#ibcon#wrote, iclass 28, count 0 2006.253.07:34:58.20#ibcon#about to read 3, iclass 28, count 0 2006.253.07:34:58.23#ibcon#read 3, iclass 28, count 0 2006.253.07:34:58.23#ibcon#about to read 4, iclass 28, count 0 2006.253.07:34:58.23#ibcon#read 4, iclass 28, count 0 2006.253.07:34:58.23#ibcon#about to read 5, iclass 28, count 0 2006.253.07:34:58.23#ibcon#read 5, iclass 28, count 0 2006.253.07:34:58.23#ibcon#about to read 6, iclass 28, count 0 2006.253.07:34:58.23#ibcon#read 6, iclass 28, count 0 2006.253.07:34:58.23#ibcon#end of sib2, iclass 28, count 0 2006.253.07:34:58.23#ibcon#*after write, iclass 28, count 0 2006.253.07:34:58.23#ibcon#*before return 0, iclass 28, count 0 2006.253.07:34:58.23#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.253.07:34:58.23#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.253.07:34:58.23#ibcon#about to clear, iclass 28 cls_cnt 0 2006.253.07:34:58.23#ibcon#cleared, iclass 28 cls_cnt 0 2006.253.07:34:58.23$vc4f8/valo=2,572.99 2006.253.07:34:58.23#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.253.07:34:58.23#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.253.07:34:58.23#ibcon#ireg 17 cls_cnt 0 2006.253.07:34:58.23#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.253.07:34:58.23#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.253.07:34:58.23#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.253.07:34:58.23#ibcon#enter wrdev, iclass 30, count 0 2006.253.07:34:58.23#ibcon#first serial, iclass 30, count 0 2006.253.07:34:58.23#ibcon#enter sib2, iclass 30, count 0 2006.253.07:34:58.23#ibcon#flushed, iclass 30, count 0 2006.253.07:34:58.23#ibcon#about to write, iclass 30, count 0 2006.253.07:34:58.23#ibcon#wrote, iclass 30, count 0 2006.253.07:34:58.23#ibcon#about to read 3, iclass 30, count 0 2006.253.07:34:58.25#ibcon#read 3, iclass 30, count 0 2006.253.07:34:58.25#ibcon#about to read 4, iclass 30, count 0 2006.253.07:34:58.25#ibcon#read 4, iclass 30, count 0 2006.253.07:34:58.25#ibcon#about to read 5, iclass 30, count 0 2006.253.07:34:58.25#ibcon#read 5, iclass 30, count 0 2006.253.07:34:58.25#ibcon#about to read 6, iclass 30, count 0 2006.253.07:34:58.25#ibcon#read 6, iclass 30, count 0 2006.253.07:34:58.25#ibcon#end of sib2, iclass 30, count 0 2006.253.07:34:58.25#ibcon#*mode == 0, iclass 30, count 0 2006.253.07:34:58.25#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.253.07:34:58.25#ibcon#[26=FRQ=02,572.99\r\n] 2006.253.07:34:58.25#ibcon#*before write, iclass 30, count 0 2006.253.07:34:58.25#ibcon#enter sib2, iclass 30, count 0 2006.253.07:34:58.25#ibcon#flushed, iclass 30, count 0 2006.253.07:34:58.25#ibcon#about to write, iclass 30, count 0 2006.253.07:34:58.25#ibcon#wrote, iclass 30, count 0 2006.253.07:34:58.25#ibcon#about to read 3, iclass 30, count 0 2006.253.07:34:58.29#ibcon#read 3, iclass 30, count 0 2006.253.07:34:58.29#ibcon#about to read 4, iclass 30, count 0 2006.253.07:34:58.29#ibcon#read 4, iclass 30, count 0 2006.253.07:34:58.29#ibcon#about to read 5, iclass 30, count 0 2006.253.07:34:58.29#ibcon#read 5, iclass 30, count 0 2006.253.07:34:58.29#ibcon#about to read 6, iclass 30, count 0 2006.253.07:34:58.29#ibcon#read 6, iclass 30, count 0 2006.253.07:34:58.29#ibcon#end of sib2, iclass 30, count 0 2006.253.07:34:58.29#ibcon#*after write, iclass 30, count 0 2006.253.07:34:58.29#ibcon#*before return 0, iclass 30, count 0 2006.253.07:34:58.29#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.253.07:34:58.29#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.253.07:34:58.29#ibcon#about to clear, iclass 30 cls_cnt 0 2006.253.07:34:58.29#ibcon#cleared, iclass 30 cls_cnt 0 2006.253.07:34:58.29$vc4f8/va=2,7 2006.253.07:34:58.29#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.253.07:34:58.29#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.253.07:34:58.29#ibcon#ireg 11 cls_cnt 2 2006.253.07:34:58.29#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.253.07:34:58.35#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.253.07:34:58.35#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.253.07:34:58.35#ibcon#enter wrdev, iclass 32, count 2 2006.253.07:34:58.35#ibcon#first serial, iclass 32, count 2 2006.253.07:34:58.35#ibcon#enter sib2, iclass 32, count 2 2006.253.07:34:58.35#ibcon#flushed, iclass 32, count 2 2006.253.07:34:58.35#ibcon#about to write, iclass 32, count 2 2006.253.07:34:58.35#ibcon#wrote, iclass 32, count 2 2006.253.07:34:58.35#ibcon#about to read 3, iclass 32, count 2 2006.253.07:34:58.37#ibcon#read 3, iclass 32, count 2 2006.253.07:34:58.37#ibcon#about to read 4, iclass 32, count 2 2006.253.07:34:58.37#ibcon#read 4, iclass 32, count 2 2006.253.07:34:58.37#ibcon#about to read 5, iclass 32, count 2 2006.253.07:34:58.37#ibcon#read 5, iclass 32, count 2 2006.253.07:34:58.37#ibcon#about to read 6, iclass 32, count 2 2006.253.07:34:58.37#ibcon#read 6, iclass 32, count 2 2006.253.07:34:58.37#ibcon#end of sib2, iclass 32, count 2 2006.253.07:34:58.37#ibcon#*mode == 0, iclass 32, count 2 2006.253.07:34:58.37#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.253.07:34:58.37#ibcon#[25=AT02-07\r\n] 2006.253.07:34:58.37#ibcon#*before write, iclass 32, count 2 2006.253.07:34:58.37#ibcon#enter sib2, iclass 32, count 2 2006.253.07:34:58.37#ibcon#flushed, iclass 32, count 2 2006.253.07:34:58.37#ibcon#about to write, iclass 32, count 2 2006.253.07:34:58.37#ibcon#wrote, iclass 32, count 2 2006.253.07:34:58.37#ibcon#about to read 3, iclass 32, count 2 2006.253.07:34:58.40#ibcon#read 3, iclass 32, count 2 2006.253.07:34:58.40#ibcon#about to read 4, iclass 32, count 2 2006.253.07:34:58.40#ibcon#read 4, iclass 32, count 2 2006.253.07:34:58.40#ibcon#about to read 5, iclass 32, count 2 2006.253.07:34:58.40#ibcon#read 5, iclass 32, count 2 2006.253.07:34:58.40#ibcon#about to read 6, iclass 32, count 2 2006.253.07:34:58.40#ibcon#read 6, iclass 32, count 2 2006.253.07:34:58.40#ibcon#end of sib2, iclass 32, count 2 2006.253.07:34:58.40#ibcon#*after write, iclass 32, count 2 2006.253.07:34:58.40#ibcon#*before return 0, iclass 32, count 2 2006.253.07:34:58.40#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.253.07:34:58.40#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.253.07:34:58.40#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.253.07:34:58.40#ibcon#ireg 7 cls_cnt 0 2006.253.07:34:58.40#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.253.07:34:58.52#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.253.07:34:58.52#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.253.07:34:58.52#ibcon#enter wrdev, iclass 32, count 0 2006.253.07:34:58.52#ibcon#first serial, iclass 32, count 0 2006.253.07:34:58.52#ibcon#enter sib2, iclass 32, count 0 2006.253.07:34:58.52#ibcon#flushed, iclass 32, count 0 2006.253.07:34:58.52#ibcon#about to write, iclass 32, count 0 2006.253.07:34:58.52#ibcon#wrote, iclass 32, count 0 2006.253.07:34:58.52#ibcon#about to read 3, iclass 32, count 0 2006.253.07:34:58.54#ibcon#read 3, iclass 32, count 0 2006.253.07:34:58.54#ibcon#about to read 4, iclass 32, count 0 2006.253.07:34:58.54#ibcon#read 4, iclass 32, count 0 2006.253.07:34:58.54#ibcon#about to read 5, iclass 32, count 0 2006.253.07:34:58.54#ibcon#read 5, iclass 32, count 0 2006.253.07:34:58.54#ibcon#about to read 6, iclass 32, count 0 2006.253.07:34:58.54#ibcon#read 6, iclass 32, count 0 2006.253.07:34:58.54#ibcon#end of sib2, iclass 32, count 0 2006.253.07:34:58.54#ibcon#*mode == 0, iclass 32, count 0 2006.253.07:34:58.54#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.253.07:34:58.54#ibcon#[25=USB\r\n] 2006.253.07:34:58.54#ibcon#*before write, iclass 32, count 0 2006.253.07:34:58.54#ibcon#enter sib2, iclass 32, count 0 2006.253.07:34:58.54#ibcon#flushed, iclass 32, count 0 2006.253.07:34:58.54#ibcon#about to write, iclass 32, count 0 2006.253.07:34:58.54#ibcon#wrote, iclass 32, count 0 2006.253.07:34:58.54#ibcon#about to read 3, iclass 32, count 0 2006.253.07:34:58.57#ibcon#read 3, iclass 32, count 0 2006.253.07:34:58.57#ibcon#about to read 4, iclass 32, count 0 2006.253.07:34:58.57#ibcon#read 4, iclass 32, count 0 2006.253.07:34:58.57#ibcon#about to read 5, iclass 32, count 0 2006.253.07:34:58.57#ibcon#read 5, iclass 32, count 0 2006.253.07:34:58.57#ibcon#about to read 6, iclass 32, count 0 2006.253.07:34:58.57#ibcon#read 6, iclass 32, count 0 2006.253.07:34:58.57#ibcon#end of sib2, iclass 32, count 0 2006.253.07:34:58.57#ibcon#*after write, iclass 32, count 0 2006.253.07:34:58.57#ibcon#*before return 0, iclass 32, count 0 2006.253.07:34:58.57#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.253.07:34:58.57#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.253.07:34:58.57#ibcon#about to clear, iclass 32 cls_cnt 0 2006.253.07:34:58.57#ibcon#cleared, iclass 32 cls_cnt 0 2006.253.07:34:58.57$vc4f8/valo=3,672.99 2006.253.07:34:58.57#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.253.07:34:58.57#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.253.07:34:58.57#ibcon#ireg 17 cls_cnt 0 2006.253.07:34:58.57#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.253.07:34:58.57#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.253.07:34:58.57#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.253.07:34:58.57#ibcon#enter wrdev, iclass 34, count 0 2006.253.07:34:58.57#ibcon#first serial, iclass 34, count 0 2006.253.07:34:58.57#ibcon#enter sib2, iclass 34, count 0 2006.253.07:34:58.57#ibcon#flushed, iclass 34, count 0 2006.253.07:34:58.57#ibcon#about to write, iclass 34, count 0 2006.253.07:34:58.57#ibcon#wrote, iclass 34, count 0 2006.253.07:34:58.57#ibcon#about to read 3, iclass 34, count 0 2006.253.07:34:58.59#ibcon#read 3, iclass 34, count 0 2006.253.07:34:58.59#ibcon#about to read 4, iclass 34, count 0 2006.253.07:34:58.59#ibcon#read 4, iclass 34, count 0 2006.253.07:34:58.59#ibcon#about to read 5, iclass 34, count 0 2006.253.07:34:58.59#ibcon#read 5, iclass 34, count 0 2006.253.07:34:58.59#ibcon#about to read 6, iclass 34, count 0 2006.253.07:34:58.59#ibcon#read 6, iclass 34, count 0 2006.253.07:34:58.59#ibcon#end of sib2, iclass 34, count 0 2006.253.07:34:58.59#ibcon#*mode == 0, iclass 34, count 0 2006.253.07:34:58.59#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.253.07:34:58.59#ibcon#[26=FRQ=03,672.99\r\n] 2006.253.07:34:58.59#ibcon#*before write, iclass 34, count 0 2006.253.07:34:58.59#ibcon#enter sib2, iclass 34, count 0 2006.253.07:34:58.59#ibcon#flushed, iclass 34, count 0 2006.253.07:34:58.59#ibcon#about to write, iclass 34, count 0 2006.253.07:34:58.59#ibcon#wrote, iclass 34, count 0 2006.253.07:34:58.59#ibcon#about to read 3, iclass 34, count 0 2006.253.07:34:58.64#ibcon#read 3, iclass 34, count 0 2006.253.07:34:58.64#ibcon#about to read 4, iclass 34, count 0 2006.253.07:34:58.64#ibcon#read 4, iclass 34, count 0 2006.253.07:34:58.64#ibcon#about to read 5, iclass 34, count 0 2006.253.07:34:58.64#ibcon#read 5, iclass 34, count 0 2006.253.07:34:58.64#ibcon#about to read 6, iclass 34, count 0 2006.253.07:34:58.64#ibcon#read 6, iclass 34, count 0 2006.253.07:34:58.64#ibcon#end of sib2, iclass 34, count 0 2006.253.07:34:58.64#ibcon#*after write, iclass 34, count 0 2006.253.07:34:58.64#ibcon#*before return 0, iclass 34, count 0 2006.253.07:34:58.64#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.253.07:34:58.64#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.253.07:34:58.64#ibcon#about to clear, iclass 34 cls_cnt 0 2006.253.07:34:58.64#ibcon#cleared, iclass 34 cls_cnt 0 2006.253.07:34:58.64$vc4f8/va=3,6 2006.253.07:34:58.64#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.253.07:34:58.64#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.253.07:34:58.64#ibcon#ireg 11 cls_cnt 2 2006.253.07:34:58.64#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.253.07:34:58.69#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.253.07:34:58.69#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.253.07:34:58.69#ibcon#enter wrdev, iclass 36, count 2 2006.253.07:34:58.69#ibcon#first serial, iclass 36, count 2 2006.253.07:34:58.69#ibcon#enter sib2, iclass 36, count 2 2006.253.07:34:58.69#ibcon#flushed, iclass 36, count 2 2006.253.07:34:58.69#ibcon#about to write, iclass 36, count 2 2006.253.07:34:58.69#ibcon#wrote, iclass 36, count 2 2006.253.07:34:58.69#ibcon#about to read 3, iclass 36, count 2 2006.253.07:34:58.71#ibcon#read 3, iclass 36, count 2 2006.253.07:34:58.71#ibcon#about to read 4, iclass 36, count 2 2006.253.07:34:58.71#ibcon#read 4, iclass 36, count 2 2006.253.07:34:58.71#ibcon#about to read 5, iclass 36, count 2 2006.253.07:34:58.71#ibcon#read 5, iclass 36, count 2 2006.253.07:34:58.71#ibcon#about to read 6, iclass 36, count 2 2006.253.07:34:58.71#ibcon#read 6, iclass 36, count 2 2006.253.07:34:58.71#ibcon#end of sib2, iclass 36, count 2 2006.253.07:34:58.71#ibcon#*mode == 0, iclass 36, count 2 2006.253.07:34:58.71#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.253.07:34:58.71#ibcon#[25=AT03-06\r\n] 2006.253.07:34:58.71#ibcon#*before write, iclass 36, count 2 2006.253.07:34:58.71#ibcon#enter sib2, iclass 36, count 2 2006.253.07:34:58.71#ibcon#flushed, iclass 36, count 2 2006.253.07:34:58.71#ibcon#about to write, iclass 36, count 2 2006.253.07:34:58.71#ibcon#wrote, iclass 36, count 2 2006.253.07:34:58.71#ibcon#about to read 3, iclass 36, count 2 2006.253.07:34:58.74#ibcon#read 3, iclass 36, count 2 2006.253.07:34:58.74#ibcon#about to read 4, iclass 36, count 2 2006.253.07:34:58.74#ibcon#read 4, iclass 36, count 2 2006.253.07:34:58.74#ibcon#about to read 5, iclass 36, count 2 2006.253.07:34:58.74#ibcon#read 5, iclass 36, count 2 2006.253.07:34:58.74#ibcon#about to read 6, iclass 36, count 2 2006.253.07:34:58.74#ibcon#read 6, iclass 36, count 2 2006.253.07:34:58.74#ibcon#end of sib2, iclass 36, count 2 2006.253.07:34:58.74#ibcon#*after write, iclass 36, count 2 2006.253.07:34:58.74#ibcon#*before return 0, iclass 36, count 2 2006.253.07:34:58.74#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.253.07:34:58.74#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.253.07:34:58.74#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.253.07:34:58.74#ibcon#ireg 7 cls_cnt 0 2006.253.07:34:58.74#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.253.07:34:58.86#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.253.07:34:58.86#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.253.07:34:58.86#ibcon#enter wrdev, iclass 36, count 0 2006.253.07:34:58.86#ibcon#first serial, iclass 36, count 0 2006.253.07:34:58.86#ibcon#enter sib2, iclass 36, count 0 2006.253.07:34:58.86#ibcon#flushed, iclass 36, count 0 2006.253.07:34:58.86#ibcon#about to write, iclass 36, count 0 2006.253.07:34:58.86#ibcon#wrote, iclass 36, count 0 2006.253.07:34:58.86#ibcon#about to read 3, iclass 36, count 0 2006.253.07:34:58.88#ibcon#read 3, iclass 36, count 0 2006.253.07:34:58.88#ibcon#about to read 4, iclass 36, count 0 2006.253.07:34:58.88#ibcon#read 4, iclass 36, count 0 2006.253.07:34:58.88#ibcon#about to read 5, iclass 36, count 0 2006.253.07:34:58.88#ibcon#read 5, iclass 36, count 0 2006.253.07:34:58.88#ibcon#about to read 6, iclass 36, count 0 2006.253.07:34:58.88#ibcon#read 6, iclass 36, count 0 2006.253.07:34:58.88#ibcon#end of sib2, iclass 36, count 0 2006.253.07:34:58.88#ibcon#*mode == 0, iclass 36, count 0 2006.253.07:34:58.88#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.253.07:34:58.88#ibcon#[25=USB\r\n] 2006.253.07:34:58.88#ibcon#*before write, iclass 36, count 0 2006.253.07:34:58.88#ibcon#enter sib2, iclass 36, count 0 2006.253.07:34:58.88#ibcon#flushed, iclass 36, count 0 2006.253.07:34:58.88#ibcon#about to write, iclass 36, count 0 2006.253.07:34:58.88#ibcon#wrote, iclass 36, count 0 2006.253.07:34:58.88#ibcon#about to read 3, iclass 36, count 0 2006.253.07:34:58.91#ibcon#read 3, iclass 36, count 0 2006.253.07:34:58.91#ibcon#about to read 4, iclass 36, count 0 2006.253.07:34:58.91#ibcon#read 4, iclass 36, count 0 2006.253.07:34:58.91#ibcon#about to read 5, iclass 36, count 0 2006.253.07:34:58.91#ibcon#read 5, iclass 36, count 0 2006.253.07:34:58.91#ibcon#about to read 6, iclass 36, count 0 2006.253.07:34:58.91#ibcon#read 6, iclass 36, count 0 2006.253.07:34:58.91#ibcon#end of sib2, iclass 36, count 0 2006.253.07:34:58.91#ibcon#*after write, iclass 36, count 0 2006.253.07:34:58.91#ibcon#*before return 0, iclass 36, count 0 2006.253.07:34:58.91#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.253.07:34:58.91#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.253.07:34:58.91#ibcon#about to clear, iclass 36 cls_cnt 0 2006.253.07:34:58.91#ibcon#cleared, iclass 36 cls_cnt 0 2006.253.07:34:58.91$vc4f8/valo=4,832.99 2006.253.07:34:58.91#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.253.07:34:58.91#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.253.07:34:58.91#ibcon#ireg 17 cls_cnt 0 2006.253.07:34:58.91#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.253.07:34:58.91#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.253.07:34:58.91#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.253.07:34:58.91#ibcon#enter wrdev, iclass 38, count 0 2006.253.07:34:58.91#ibcon#first serial, iclass 38, count 0 2006.253.07:34:58.91#ibcon#enter sib2, iclass 38, count 0 2006.253.07:34:58.91#ibcon#flushed, iclass 38, count 0 2006.253.07:34:58.91#ibcon#about to write, iclass 38, count 0 2006.253.07:34:58.91#ibcon#wrote, iclass 38, count 0 2006.253.07:34:58.91#ibcon#about to read 3, iclass 38, count 0 2006.253.07:34:58.93#ibcon#read 3, iclass 38, count 0 2006.253.07:34:58.93#ibcon#about to read 4, iclass 38, count 0 2006.253.07:34:58.93#ibcon#read 4, iclass 38, count 0 2006.253.07:34:58.93#ibcon#about to read 5, iclass 38, count 0 2006.253.07:34:58.93#ibcon#read 5, iclass 38, count 0 2006.253.07:34:58.93#ibcon#about to read 6, iclass 38, count 0 2006.253.07:34:58.93#ibcon#read 6, iclass 38, count 0 2006.253.07:34:58.93#ibcon#end of sib2, iclass 38, count 0 2006.253.07:34:58.93#ibcon#*mode == 0, iclass 38, count 0 2006.253.07:34:58.93#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.253.07:34:58.93#ibcon#[26=FRQ=04,832.99\r\n] 2006.253.07:34:58.93#ibcon#*before write, iclass 38, count 0 2006.253.07:34:58.93#ibcon#enter sib2, iclass 38, count 0 2006.253.07:34:58.93#ibcon#flushed, iclass 38, count 0 2006.253.07:34:58.93#ibcon#about to write, iclass 38, count 0 2006.253.07:34:58.93#ibcon#wrote, iclass 38, count 0 2006.253.07:34:58.93#ibcon#about to read 3, iclass 38, count 0 2006.253.07:34:58.98#ibcon#read 3, iclass 38, count 0 2006.253.07:34:58.98#ibcon#about to read 4, iclass 38, count 0 2006.253.07:34:58.98#ibcon#read 4, iclass 38, count 0 2006.253.07:34:58.98#ibcon#about to read 5, iclass 38, count 0 2006.253.07:34:58.98#ibcon#read 5, iclass 38, count 0 2006.253.07:34:58.98#ibcon#about to read 6, iclass 38, count 0 2006.253.07:34:58.98#ibcon#read 6, iclass 38, count 0 2006.253.07:34:58.98#ibcon#end of sib2, iclass 38, count 0 2006.253.07:34:58.98#ibcon#*after write, iclass 38, count 0 2006.253.07:34:58.98#ibcon#*before return 0, iclass 38, count 0 2006.253.07:34:58.98#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.253.07:34:58.98#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.253.07:34:58.98#ibcon#about to clear, iclass 38 cls_cnt 0 2006.253.07:34:58.98#ibcon#cleared, iclass 38 cls_cnt 0 2006.253.07:34:58.98$vc4f8/va=4,7 2006.253.07:34:58.98#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.253.07:34:58.98#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.253.07:34:58.98#ibcon#ireg 11 cls_cnt 2 2006.253.07:34:58.98#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.253.07:34:59.03#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.253.07:34:59.03#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.253.07:34:59.03#ibcon#enter wrdev, iclass 40, count 2 2006.253.07:34:59.03#ibcon#first serial, iclass 40, count 2 2006.253.07:34:59.03#ibcon#enter sib2, iclass 40, count 2 2006.253.07:34:59.03#ibcon#flushed, iclass 40, count 2 2006.253.07:34:59.03#ibcon#about to write, iclass 40, count 2 2006.253.07:34:59.03#ibcon#wrote, iclass 40, count 2 2006.253.07:34:59.03#ibcon#about to read 3, iclass 40, count 2 2006.253.07:34:59.05#ibcon#read 3, iclass 40, count 2 2006.253.07:34:59.05#ibcon#about to read 4, iclass 40, count 2 2006.253.07:34:59.05#ibcon#read 4, iclass 40, count 2 2006.253.07:34:59.05#ibcon#about to read 5, iclass 40, count 2 2006.253.07:34:59.05#ibcon#read 5, iclass 40, count 2 2006.253.07:34:59.05#ibcon#about to read 6, iclass 40, count 2 2006.253.07:34:59.05#ibcon#read 6, iclass 40, count 2 2006.253.07:34:59.05#ibcon#end of sib2, iclass 40, count 2 2006.253.07:34:59.05#ibcon#*mode == 0, iclass 40, count 2 2006.253.07:34:59.05#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.253.07:34:59.05#ibcon#[25=AT04-07\r\n] 2006.253.07:34:59.05#ibcon#*before write, iclass 40, count 2 2006.253.07:34:59.05#ibcon#enter sib2, iclass 40, count 2 2006.253.07:34:59.05#ibcon#flushed, iclass 40, count 2 2006.253.07:34:59.05#ibcon#about to write, iclass 40, count 2 2006.253.07:34:59.05#ibcon#wrote, iclass 40, count 2 2006.253.07:34:59.05#ibcon#about to read 3, iclass 40, count 2 2006.253.07:34:59.08#ibcon#read 3, iclass 40, count 2 2006.253.07:34:59.08#ibcon#about to read 4, iclass 40, count 2 2006.253.07:34:59.08#ibcon#read 4, iclass 40, count 2 2006.253.07:34:59.08#ibcon#about to read 5, iclass 40, count 2 2006.253.07:34:59.08#ibcon#read 5, iclass 40, count 2 2006.253.07:34:59.08#ibcon#about to read 6, iclass 40, count 2 2006.253.07:34:59.08#ibcon#read 6, iclass 40, count 2 2006.253.07:34:59.08#ibcon#end of sib2, iclass 40, count 2 2006.253.07:34:59.08#ibcon#*after write, iclass 40, count 2 2006.253.07:34:59.08#ibcon#*before return 0, iclass 40, count 2 2006.253.07:34:59.08#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.253.07:34:59.08#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.253.07:34:59.08#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.253.07:34:59.08#ibcon#ireg 7 cls_cnt 0 2006.253.07:34:59.08#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.253.07:34:59.20#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.253.07:34:59.20#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.253.07:34:59.20#ibcon#enter wrdev, iclass 40, count 0 2006.253.07:34:59.20#ibcon#first serial, iclass 40, count 0 2006.253.07:34:59.20#ibcon#enter sib2, iclass 40, count 0 2006.253.07:34:59.20#ibcon#flushed, iclass 40, count 0 2006.253.07:34:59.20#ibcon#about to write, iclass 40, count 0 2006.253.07:34:59.20#ibcon#wrote, iclass 40, count 0 2006.253.07:34:59.20#ibcon#about to read 3, iclass 40, count 0 2006.253.07:34:59.22#ibcon#read 3, iclass 40, count 0 2006.253.07:34:59.22#ibcon#about to read 4, iclass 40, count 0 2006.253.07:34:59.22#ibcon#read 4, iclass 40, count 0 2006.253.07:34:59.22#ibcon#about to read 5, iclass 40, count 0 2006.253.07:34:59.22#ibcon#read 5, iclass 40, count 0 2006.253.07:34:59.22#ibcon#about to read 6, iclass 40, count 0 2006.253.07:34:59.22#ibcon#read 6, iclass 40, count 0 2006.253.07:34:59.22#ibcon#end of sib2, iclass 40, count 0 2006.253.07:34:59.22#ibcon#*mode == 0, iclass 40, count 0 2006.253.07:34:59.22#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.253.07:34:59.22#ibcon#[25=USB\r\n] 2006.253.07:34:59.22#ibcon#*before write, iclass 40, count 0 2006.253.07:34:59.22#ibcon#enter sib2, iclass 40, count 0 2006.253.07:34:59.22#ibcon#flushed, iclass 40, count 0 2006.253.07:34:59.22#ibcon#about to write, iclass 40, count 0 2006.253.07:34:59.22#ibcon#wrote, iclass 40, count 0 2006.253.07:34:59.22#ibcon#about to read 3, iclass 40, count 0 2006.253.07:34:59.25#ibcon#read 3, iclass 40, count 0 2006.253.07:34:59.25#ibcon#about to read 4, iclass 40, count 0 2006.253.07:34:59.25#ibcon#read 4, iclass 40, count 0 2006.253.07:34:59.25#ibcon#about to read 5, iclass 40, count 0 2006.253.07:34:59.25#ibcon#read 5, iclass 40, count 0 2006.253.07:34:59.25#ibcon#about to read 6, iclass 40, count 0 2006.253.07:34:59.25#ibcon#read 6, iclass 40, count 0 2006.253.07:34:59.25#ibcon#end of sib2, iclass 40, count 0 2006.253.07:34:59.25#ibcon#*after write, iclass 40, count 0 2006.253.07:34:59.25#ibcon#*before return 0, iclass 40, count 0 2006.253.07:34:59.25#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.253.07:34:59.25#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.253.07:34:59.25#ibcon#about to clear, iclass 40 cls_cnt 0 2006.253.07:34:59.25#ibcon#cleared, iclass 40 cls_cnt 0 2006.253.07:34:59.25$vc4f8/valo=5,652.99 2006.253.07:34:59.25#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.253.07:34:59.25#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.253.07:34:59.25#ibcon#ireg 17 cls_cnt 0 2006.253.07:34:59.25#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.253.07:34:59.25#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.253.07:34:59.25#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.253.07:34:59.25#ibcon#enter wrdev, iclass 4, count 0 2006.253.07:34:59.25#ibcon#first serial, iclass 4, count 0 2006.253.07:34:59.25#ibcon#enter sib2, iclass 4, count 0 2006.253.07:34:59.25#ibcon#flushed, iclass 4, count 0 2006.253.07:34:59.25#ibcon#about to write, iclass 4, count 0 2006.253.07:34:59.25#ibcon#wrote, iclass 4, count 0 2006.253.07:34:59.25#ibcon#about to read 3, iclass 4, count 0 2006.253.07:34:59.27#ibcon#read 3, iclass 4, count 0 2006.253.07:34:59.27#ibcon#about to read 4, iclass 4, count 0 2006.253.07:34:59.27#ibcon#read 4, iclass 4, count 0 2006.253.07:34:59.27#ibcon#about to read 5, iclass 4, count 0 2006.253.07:34:59.27#ibcon#read 5, iclass 4, count 0 2006.253.07:34:59.27#ibcon#about to read 6, iclass 4, count 0 2006.253.07:34:59.27#ibcon#read 6, iclass 4, count 0 2006.253.07:34:59.27#ibcon#end of sib2, iclass 4, count 0 2006.253.07:34:59.27#ibcon#*mode == 0, iclass 4, count 0 2006.253.07:34:59.27#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.253.07:34:59.27#ibcon#[26=FRQ=05,652.99\r\n] 2006.253.07:34:59.27#ibcon#*before write, iclass 4, count 0 2006.253.07:34:59.27#ibcon#enter sib2, iclass 4, count 0 2006.253.07:34:59.27#ibcon#flushed, iclass 4, count 0 2006.253.07:34:59.27#ibcon#about to write, iclass 4, count 0 2006.253.07:34:59.27#ibcon#wrote, iclass 4, count 0 2006.253.07:34:59.27#ibcon#about to read 3, iclass 4, count 0 2006.253.07:34:59.31#ibcon#read 3, iclass 4, count 0 2006.253.07:34:59.31#ibcon#about to read 4, iclass 4, count 0 2006.253.07:34:59.31#ibcon#read 4, iclass 4, count 0 2006.253.07:34:59.31#ibcon#about to read 5, iclass 4, count 0 2006.253.07:34:59.31#ibcon#read 5, iclass 4, count 0 2006.253.07:34:59.31#ibcon#about to read 6, iclass 4, count 0 2006.253.07:34:59.31#ibcon#read 6, iclass 4, count 0 2006.253.07:34:59.31#ibcon#end of sib2, iclass 4, count 0 2006.253.07:34:59.31#ibcon#*after write, iclass 4, count 0 2006.253.07:34:59.31#ibcon#*before return 0, iclass 4, count 0 2006.253.07:34:59.31#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.253.07:34:59.31#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.253.07:34:59.31#ibcon#about to clear, iclass 4 cls_cnt 0 2006.253.07:34:59.31#ibcon#cleared, iclass 4 cls_cnt 0 2006.253.07:34:59.31$vc4f8/va=5,7 2006.253.07:34:59.31#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.253.07:34:59.31#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.253.07:34:59.31#ibcon#ireg 11 cls_cnt 2 2006.253.07:34:59.31#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.253.07:34:59.37#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.253.07:34:59.37#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.253.07:34:59.37#ibcon#enter wrdev, iclass 6, count 2 2006.253.07:34:59.37#ibcon#first serial, iclass 6, count 2 2006.253.07:34:59.37#ibcon#enter sib2, iclass 6, count 2 2006.253.07:34:59.37#ibcon#flushed, iclass 6, count 2 2006.253.07:34:59.37#ibcon#about to write, iclass 6, count 2 2006.253.07:34:59.37#ibcon#wrote, iclass 6, count 2 2006.253.07:34:59.37#ibcon#about to read 3, iclass 6, count 2 2006.253.07:34:59.39#ibcon#read 3, iclass 6, count 2 2006.253.07:34:59.39#ibcon#about to read 4, iclass 6, count 2 2006.253.07:34:59.39#ibcon#read 4, iclass 6, count 2 2006.253.07:34:59.39#ibcon#about to read 5, iclass 6, count 2 2006.253.07:34:59.39#ibcon#read 5, iclass 6, count 2 2006.253.07:34:59.39#ibcon#about to read 6, iclass 6, count 2 2006.253.07:34:59.39#ibcon#read 6, iclass 6, count 2 2006.253.07:34:59.39#ibcon#end of sib2, iclass 6, count 2 2006.253.07:34:59.39#ibcon#*mode == 0, iclass 6, count 2 2006.253.07:34:59.39#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.253.07:34:59.39#ibcon#[25=AT05-07\r\n] 2006.253.07:34:59.39#ibcon#*before write, iclass 6, count 2 2006.253.07:34:59.39#ibcon#enter sib2, iclass 6, count 2 2006.253.07:34:59.39#ibcon#flushed, iclass 6, count 2 2006.253.07:34:59.39#ibcon#about to write, iclass 6, count 2 2006.253.07:34:59.39#ibcon#wrote, iclass 6, count 2 2006.253.07:34:59.39#ibcon#about to read 3, iclass 6, count 2 2006.253.07:34:59.42#ibcon#read 3, iclass 6, count 2 2006.253.07:34:59.42#ibcon#about to read 4, iclass 6, count 2 2006.253.07:34:59.42#ibcon#read 4, iclass 6, count 2 2006.253.07:34:59.42#ibcon#about to read 5, iclass 6, count 2 2006.253.07:34:59.42#ibcon#read 5, iclass 6, count 2 2006.253.07:34:59.42#ibcon#about to read 6, iclass 6, count 2 2006.253.07:34:59.42#ibcon#read 6, iclass 6, count 2 2006.253.07:34:59.42#ibcon#end of sib2, iclass 6, count 2 2006.253.07:34:59.42#ibcon#*after write, iclass 6, count 2 2006.253.07:34:59.42#ibcon#*before return 0, iclass 6, count 2 2006.253.07:34:59.42#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.253.07:34:59.42#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.253.07:34:59.42#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.253.07:34:59.42#ibcon#ireg 7 cls_cnt 0 2006.253.07:34:59.42#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.253.07:34:59.54#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.253.07:34:59.54#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.253.07:34:59.54#ibcon#enter wrdev, iclass 6, count 0 2006.253.07:34:59.54#ibcon#first serial, iclass 6, count 0 2006.253.07:34:59.54#ibcon#enter sib2, iclass 6, count 0 2006.253.07:34:59.54#ibcon#flushed, iclass 6, count 0 2006.253.07:34:59.54#ibcon#about to write, iclass 6, count 0 2006.253.07:34:59.54#ibcon#wrote, iclass 6, count 0 2006.253.07:34:59.54#ibcon#about to read 3, iclass 6, count 0 2006.253.07:34:59.56#ibcon#read 3, iclass 6, count 0 2006.253.07:34:59.56#ibcon#about to read 4, iclass 6, count 0 2006.253.07:34:59.56#ibcon#read 4, iclass 6, count 0 2006.253.07:34:59.56#ibcon#about to read 5, iclass 6, count 0 2006.253.07:34:59.56#ibcon#read 5, iclass 6, count 0 2006.253.07:34:59.56#ibcon#about to read 6, iclass 6, count 0 2006.253.07:34:59.56#ibcon#read 6, iclass 6, count 0 2006.253.07:34:59.56#ibcon#end of sib2, iclass 6, count 0 2006.253.07:34:59.56#ibcon#*mode == 0, iclass 6, count 0 2006.253.07:34:59.56#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.253.07:34:59.56#ibcon#[25=USB\r\n] 2006.253.07:34:59.56#ibcon#*before write, iclass 6, count 0 2006.253.07:34:59.56#ibcon#enter sib2, iclass 6, count 0 2006.253.07:34:59.56#ibcon#flushed, iclass 6, count 0 2006.253.07:34:59.56#ibcon#about to write, iclass 6, count 0 2006.253.07:34:59.56#ibcon#wrote, iclass 6, count 0 2006.253.07:34:59.56#ibcon#about to read 3, iclass 6, count 0 2006.253.07:34:59.59#ibcon#read 3, iclass 6, count 0 2006.253.07:34:59.59#ibcon#about to read 4, iclass 6, count 0 2006.253.07:34:59.59#ibcon#read 4, iclass 6, count 0 2006.253.07:34:59.59#ibcon#about to read 5, iclass 6, count 0 2006.253.07:34:59.59#ibcon#read 5, iclass 6, count 0 2006.253.07:34:59.59#ibcon#about to read 6, iclass 6, count 0 2006.253.07:34:59.59#ibcon#read 6, iclass 6, count 0 2006.253.07:34:59.59#ibcon#end of sib2, iclass 6, count 0 2006.253.07:34:59.59#ibcon#*after write, iclass 6, count 0 2006.253.07:34:59.59#ibcon#*before return 0, iclass 6, count 0 2006.253.07:34:59.59#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.253.07:34:59.59#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.253.07:34:59.59#ibcon#about to clear, iclass 6 cls_cnt 0 2006.253.07:34:59.59#ibcon#cleared, iclass 6 cls_cnt 0 2006.253.07:34:59.59$vc4f8/valo=6,772.99 2006.253.07:34:59.59#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.253.07:34:59.59#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.253.07:34:59.59#ibcon#ireg 17 cls_cnt 0 2006.253.07:34:59.59#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.253.07:34:59.59#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.253.07:34:59.59#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.253.07:34:59.59#ibcon#enter wrdev, iclass 10, count 0 2006.253.07:34:59.59#ibcon#first serial, iclass 10, count 0 2006.253.07:34:59.59#ibcon#enter sib2, iclass 10, count 0 2006.253.07:34:59.59#ibcon#flushed, iclass 10, count 0 2006.253.07:34:59.59#ibcon#about to write, iclass 10, count 0 2006.253.07:34:59.59#ibcon#wrote, iclass 10, count 0 2006.253.07:34:59.59#ibcon#about to read 3, iclass 10, count 0 2006.253.07:34:59.61#ibcon#read 3, iclass 10, count 0 2006.253.07:34:59.61#ibcon#about to read 4, iclass 10, count 0 2006.253.07:34:59.61#ibcon#read 4, iclass 10, count 0 2006.253.07:34:59.61#ibcon#about to read 5, iclass 10, count 0 2006.253.07:34:59.61#ibcon#read 5, iclass 10, count 0 2006.253.07:34:59.61#ibcon#about to read 6, iclass 10, count 0 2006.253.07:34:59.61#ibcon#read 6, iclass 10, count 0 2006.253.07:34:59.61#ibcon#end of sib2, iclass 10, count 0 2006.253.07:34:59.61#ibcon#*mode == 0, iclass 10, count 0 2006.253.07:34:59.61#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.253.07:34:59.61#ibcon#[26=FRQ=06,772.99\r\n] 2006.253.07:34:59.61#ibcon#*before write, iclass 10, count 0 2006.253.07:34:59.61#ibcon#enter sib2, iclass 10, count 0 2006.253.07:34:59.61#ibcon#flushed, iclass 10, count 0 2006.253.07:34:59.61#ibcon#about to write, iclass 10, count 0 2006.253.07:34:59.61#ibcon#wrote, iclass 10, count 0 2006.253.07:34:59.61#ibcon#about to read 3, iclass 10, count 0 2006.253.07:34:59.66#ibcon#read 3, iclass 10, count 0 2006.253.07:34:59.66#ibcon#about to read 4, iclass 10, count 0 2006.253.07:34:59.66#ibcon#read 4, iclass 10, count 0 2006.253.07:34:59.66#ibcon#about to read 5, iclass 10, count 0 2006.253.07:34:59.66#ibcon#read 5, iclass 10, count 0 2006.253.07:34:59.66#ibcon#about to read 6, iclass 10, count 0 2006.253.07:34:59.66#ibcon#read 6, iclass 10, count 0 2006.253.07:34:59.66#ibcon#end of sib2, iclass 10, count 0 2006.253.07:34:59.66#ibcon#*after write, iclass 10, count 0 2006.253.07:34:59.66#ibcon#*before return 0, iclass 10, count 0 2006.253.07:34:59.66#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.253.07:34:59.66#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.253.07:34:59.66#ibcon#about to clear, iclass 10 cls_cnt 0 2006.253.07:34:59.66#ibcon#cleared, iclass 10 cls_cnt 0 2006.253.07:34:59.66$vc4f8/va=6,7 2006.253.07:34:59.66#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.253.07:34:59.66#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.253.07:34:59.66#ibcon#ireg 11 cls_cnt 2 2006.253.07:34:59.66#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.253.07:34:59.71#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.253.07:34:59.71#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.253.07:34:59.71#ibcon#enter wrdev, iclass 12, count 2 2006.253.07:34:59.71#ibcon#first serial, iclass 12, count 2 2006.253.07:34:59.71#ibcon#enter sib2, iclass 12, count 2 2006.253.07:34:59.71#ibcon#flushed, iclass 12, count 2 2006.253.07:34:59.71#ibcon#about to write, iclass 12, count 2 2006.253.07:34:59.71#ibcon#wrote, iclass 12, count 2 2006.253.07:34:59.71#ibcon#about to read 3, iclass 12, count 2 2006.253.07:34:59.73#ibcon#read 3, iclass 12, count 2 2006.253.07:34:59.73#ibcon#about to read 4, iclass 12, count 2 2006.253.07:34:59.73#ibcon#read 4, iclass 12, count 2 2006.253.07:34:59.73#ibcon#about to read 5, iclass 12, count 2 2006.253.07:34:59.73#ibcon#read 5, iclass 12, count 2 2006.253.07:34:59.73#ibcon#about to read 6, iclass 12, count 2 2006.253.07:34:59.73#ibcon#read 6, iclass 12, count 2 2006.253.07:34:59.73#ibcon#end of sib2, iclass 12, count 2 2006.253.07:34:59.73#ibcon#*mode == 0, iclass 12, count 2 2006.253.07:34:59.73#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.253.07:34:59.73#ibcon#[25=AT06-07\r\n] 2006.253.07:34:59.73#ibcon#*before write, iclass 12, count 2 2006.253.07:34:59.73#ibcon#enter sib2, iclass 12, count 2 2006.253.07:34:59.73#ibcon#flushed, iclass 12, count 2 2006.253.07:34:59.73#ibcon#about to write, iclass 12, count 2 2006.253.07:34:59.73#ibcon#wrote, iclass 12, count 2 2006.253.07:34:59.73#ibcon#about to read 3, iclass 12, count 2 2006.253.07:34:59.76#ibcon#read 3, iclass 12, count 2 2006.253.07:34:59.76#ibcon#about to read 4, iclass 12, count 2 2006.253.07:34:59.76#ibcon#read 4, iclass 12, count 2 2006.253.07:34:59.76#ibcon#about to read 5, iclass 12, count 2 2006.253.07:34:59.76#ibcon#read 5, iclass 12, count 2 2006.253.07:34:59.76#ibcon#about to read 6, iclass 12, count 2 2006.253.07:34:59.76#ibcon#read 6, iclass 12, count 2 2006.253.07:34:59.76#ibcon#end of sib2, iclass 12, count 2 2006.253.07:34:59.76#ibcon#*after write, iclass 12, count 2 2006.253.07:34:59.76#ibcon#*before return 0, iclass 12, count 2 2006.253.07:34:59.76#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.253.07:34:59.76#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.253.07:34:59.76#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.253.07:34:59.76#ibcon#ireg 7 cls_cnt 0 2006.253.07:34:59.76#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.253.07:34:59.88#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.253.07:34:59.88#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.253.07:34:59.88#ibcon#enter wrdev, iclass 12, count 0 2006.253.07:34:59.88#ibcon#first serial, iclass 12, count 0 2006.253.07:34:59.88#ibcon#enter sib2, iclass 12, count 0 2006.253.07:34:59.88#ibcon#flushed, iclass 12, count 0 2006.253.07:34:59.88#ibcon#about to write, iclass 12, count 0 2006.253.07:34:59.88#ibcon#wrote, iclass 12, count 0 2006.253.07:34:59.88#ibcon#about to read 3, iclass 12, count 0 2006.253.07:34:59.90#ibcon#read 3, iclass 12, count 0 2006.253.07:34:59.90#ibcon#about to read 4, iclass 12, count 0 2006.253.07:34:59.90#ibcon#read 4, iclass 12, count 0 2006.253.07:34:59.90#ibcon#about to read 5, iclass 12, count 0 2006.253.07:34:59.90#ibcon#read 5, iclass 12, count 0 2006.253.07:34:59.90#ibcon#about to read 6, iclass 12, count 0 2006.253.07:34:59.90#ibcon#read 6, iclass 12, count 0 2006.253.07:34:59.90#ibcon#end of sib2, iclass 12, count 0 2006.253.07:34:59.90#ibcon#*mode == 0, iclass 12, count 0 2006.253.07:34:59.90#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.253.07:34:59.90#ibcon#[25=USB\r\n] 2006.253.07:34:59.90#ibcon#*before write, iclass 12, count 0 2006.253.07:34:59.90#ibcon#enter sib2, iclass 12, count 0 2006.253.07:34:59.90#ibcon#flushed, iclass 12, count 0 2006.253.07:34:59.90#ibcon#about to write, iclass 12, count 0 2006.253.07:34:59.90#ibcon#wrote, iclass 12, count 0 2006.253.07:34:59.90#ibcon#about to read 3, iclass 12, count 0 2006.253.07:34:59.93#ibcon#read 3, iclass 12, count 0 2006.253.07:34:59.93#ibcon#about to read 4, iclass 12, count 0 2006.253.07:34:59.93#ibcon#read 4, iclass 12, count 0 2006.253.07:34:59.93#ibcon#about to read 5, iclass 12, count 0 2006.253.07:34:59.93#ibcon#read 5, iclass 12, count 0 2006.253.07:34:59.93#ibcon#about to read 6, iclass 12, count 0 2006.253.07:34:59.93#ibcon#read 6, iclass 12, count 0 2006.253.07:34:59.93#ibcon#end of sib2, iclass 12, count 0 2006.253.07:34:59.93#ibcon#*after write, iclass 12, count 0 2006.253.07:34:59.93#ibcon#*before return 0, iclass 12, count 0 2006.253.07:34:59.93#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.253.07:34:59.93#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.253.07:34:59.93#ibcon#about to clear, iclass 12 cls_cnt 0 2006.253.07:34:59.93#ibcon#cleared, iclass 12 cls_cnt 0 2006.253.07:34:59.93$vc4f8/valo=7,832.99 2006.253.07:34:59.93#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.253.07:34:59.93#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.253.07:34:59.93#ibcon#ireg 17 cls_cnt 0 2006.253.07:34:59.93#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.253.07:34:59.93#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.253.07:34:59.93#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.253.07:34:59.93#ibcon#enter wrdev, iclass 14, count 0 2006.253.07:34:59.93#ibcon#first serial, iclass 14, count 0 2006.253.07:34:59.93#ibcon#enter sib2, iclass 14, count 0 2006.253.07:34:59.93#ibcon#flushed, iclass 14, count 0 2006.253.07:34:59.93#ibcon#about to write, iclass 14, count 0 2006.253.07:34:59.93#ibcon#wrote, iclass 14, count 0 2006.253.07:34:59.93#ibcon#about to read 3, iclass 14, count 0 2006.253.07:34:59.95#ibcon#read 3, iclass 14, count 0 2006.253.07:34:59.95#ibcon#about to read 4, iclass 14, count 0 2006.253.07:34:59.95#ibcon#read 4, iclass 14, count 0 2006.253.07:34:59.95#ibcon#about to read 5, iclass 14, count 0 2006.253.07:34:59.95#ibcon#read 5, iclass 14, count 0 2006.253.07:34:59.95#ibcon#about to read 6, iclass 14, count 0 2006.253.07:34:59.95#ibcon#read 6, iclass 14, count 0 2006.253.07:34:59.95#ibcon#end of sib2, iclass 14, count 0 2006.253.07:34:59.95#ibcon#*mode == 0, iclass 14, count 0 2006.253.07:34:59.95#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.253.07:34:59.95#ibcon#[26=FRQ=07,832.99\r\n] 2006.253.07:34:59.95#ibcon#*before write, iclass 14, count 0 2006.253.07:34:59.95#ibcon#enter sib2, iclass 14, count 0 2006.253.07:34:59.95#ibcon#flushed, iclass 14, count 0 2006.253.07:34:59.95#ibcon#about to write, iclass 14, count 0 2006.253.07:34:59.95#ibcon#wrote, iclass 14, count 0 2006.253.07:34:59.95#ibcon#about to read 3, iclass 14, count 0 2006.253.07:34:59.99#ibcon#read 3, iclass 14, count 0 2006.253.07:34:59.99#ibcon#about to read 4, iclass 14, count 0 2006.253.07:34:59.99#ibcon#read 4, iclass 14, count 0 2006.253.07:34:59.99#ibcon#about to read 5, iclass 14, count 0 2006.253.07:34:59.99#ibcon#read 5, iclass 14, count 0 2006.253.07:34:59.99#ibcon#about to read 6, iclass 14, count 0 2006.253.07:34:59.99#ibcon#read 6, iclass 14, count 0 2006.253.07:34:59.99#ibcon#end of sib2, iclass 14, count 0 2006.253.07:34:59.99#ibcon#*after write, iclass 14, count 0 2006.253.07:34:59.99#ibcon#*before return 0, iclass 14, count 0 2006.253.07:34:59.99#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.253.07:34:59.99#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.253.07:34:59.99#ibcon#about to clear, iclass 14 cls_cnt 0 2006.253.07:34:59.99#ibcon#cleared, iclass 14 cls_cnt 0 2006.253.07:34:59.99$vc4f8/va=7,7 2006.253.07:34:59.99#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.253.07:34:59.99#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.253.07:34:59.99#ibcon#ireg 11 cls_cnt 2 2006.253.07:34:59.99#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.253.07:35:00.05#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.253.07:35:00.05#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.253.07:35:00.05#ibcon#enter wrdev, iclass 16, count 2 2006.253.07:35:00.05#ibcon#first serial, iclass 16, count 2 2006.253.07:35:00.05#ibcon#enter sib2, iclass 16, count 2 2006.253.07:35:00.05#ibcon#flushed, iclass 16, count 2 2006.253.07:35:00.05#ibcon#about to write, iclass 16, count 2 2006.253.07:35:00.05#ibcon#wrote, iclass 16, count 2 2006.253.07:35:00.05#ibcon#about to read 3, iclass 16, count 2 2006.253.07:35:00.07#ibcon#read 3, iclass 16, count 2 2006.253.07:35:00.07#ibcon#about to read 4, iclass 16, count 2 2006.253.07:35:00.07#ibcon#read 4, iclass 16, count 2 2006.253.07:35:00.07#ibcon#about to read 5, iclass 16, count 2 2006.253.07:35:00.07#ibcon#read 5, iclass 16, count 2 2006.253.07:35:00.07#ibcon#about to read 6, iclass 16, count 2 2006.253.07:35:00.07#ibcon#read 6, iclass 16, count 2 2006.253.07:35:00.07#ibcon#end of sib2, iclass 16, count 2 2006.253.07:35:00.07#ibcon#*mode == 0, iclass 16, count 2 2006.253.07:35:00.07#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.253.07:35:00.07#ibcon#[25=AT07-07\r\n] 2006.253.07:35:00.07#ibcon#*before write, iclass 16, count 2 2006.253.07:35:00.07#ibcon#enter sib2, iclass 16, count 2 2006.253.07:35:00.07#ibcon#flushed, iclass 16, count 2 2006.253.07:35:00.07#ibcon#about to write, iclass 16, count 2 2006.253.07:35:00.07#ibcon#wrote, iclass 16, count 2 2006.253.07:35:00.07#ibcon#about to read 3, iclass 16, count 2 2006.253.07:35:00.10#ibcon#read 3, iclass 16, count 2 2006.253.07:35:00.10#ibcon#about to read 4, iclass 16, count 2 2006.253.07:35:00.10#ibcon#read 4, iclass 16, count 2 2006.253.07:35:00.10#ibcon#about to read 5, iclass 16, count 2 2006.253.07:35:00.10#ibcon#read 5, iclass 16, count 2 2006.253.07:35:00.10#ibcon#about to read 6, iclass 16, count 2 2006.253.07:35:00.10#ibcon#read 6, iclass 16, count 2 2006.253.07:35:00.10#ibcon#end of sib2, iclass 16, count 2 2006.253.07:35:00.10#ibcon#*after write, iclass 16, count 2 2006.253.07:35:00.10#ibcon#*before return 0, iclass 16, count 2 2006.253.07:35:00.10#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.253.07:35:00.10#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.253.07:35:00.10#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.253.07:35:00.10#ibcon#ireg 7 cls_cnt 0 2006.253.07:35:00.10#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.253.07:35:00.22#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.253.07:35:00.22#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.253.07:35:00.22#ibcon#enter wrdev, iclass 16, count 0 2006.253.07:35:00.22#ibcon#first serial, iclass 16, count 0 2006.253.07:35:00.22#ibcon#enter sib2, iclass 16, count 0 2006.253.07:35:00.22#ibcon#flushed, iclass 16, count 0 2006.253.07:35:00.22#ibcon#about to write, iclass 16, count 0 2006.253.07:35:00.22#ibcon#wrote, iclass 16, count 0 2006.253.07:35:00.22#ibcon#about to read 3, iclass 16, count 0 2006.253.07:35:00.25#ibcon#read 3, iclass 16, count 0 2006.253.07:35:00.25#ibcon#about to read 4, iclass 16, count 0 2006.253.07:35:00.25#ibcon#read 4, iclass 16, count 0 2006.253.07:35:00.25#ibcon#about to read 5, iclass 16, count 0 2006.253.07:35:00.25#ibcon#read 5, iclass 16, count 0 2006.253.07:35:00.25#ibcon#about to read 6, iclass 16, count 0 2006.253.07:35:00.25#ibcon#read 6, iclass 16, count 0 2006.253.07:35:00.25#ibcon#end of sib2, iclass 16, count 0 2006.253.07:35:00.25#ibcon#*mode == 0, iclass 16, count 0 2006.253.07:35:00.25#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.253.07:35:00.25#ibcon#[25=USB\r\n] 2006.253.07:35:00.25#ibcon#*before write, iclass 16, count 0 2006.253.07:35:00.25#ibcon#enter sib2, iclass 16, count 0 2006.253.07:35:00.25#ibcon#flushed, iclass 16, count 0 2006.253.07:35:00.25#ibcon#about to write, iclass 16, count 0 2006.253.07:35:00.25#ibcon#wrote, iclass 16, count 0 2006.253.07:35:00.25#ibcon#about to read 3, iclass 16, count 0 2006.253.07:35:00.29#ibcon#read 3, iclass 16, count 0 2006.253.07:35:00.29#ibcon#about to read 4, iclass 16, count 0 2006.253.07:35:00.29#ibcon#read 4, iclass 16, count 0 2006.253.07:35:00.29#ibcon#about to read 5, iclass 16, count 0 2006.253.07:35:00.29#ibcon#read 5, iclass 16, count 0 2006.253.07:35:00.29#ibcon#about to read 6, iclass 16, count 0 2006.253.07:35:00.29#ibcon#read 6, iclass 16, count 0 2006.253.07:35:00.29#ibcon#end of sib2, iclass 16, count 0 2006.253.07:35:00.29#ibcon#*after write, iclass 16, count 0 2006.253.07:35:00.29#ibcon#*before return 0, iclass 16, count 0 2006.253.07:35:00.29#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.253.07:35:00.29#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.253.07:35:00.29#ibcon#about to clear, iclass 16 cls_cnt 0 2006.253.07:35:00.29#ibcon#cleared, iclass 16 cls_cnt 0 2006.253.07:35:00.29$vc4f8/valo=8,852.99 2006.253.07:35:00.29#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.253.07:35:00.29#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.253.07:35:00.29#ibcon#ireg 17 cls_cnt 0 2006.253.07:35:00.29#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.253.07:35:00.29#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.253.07:35:00.29#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.253.07:35:00.29#ibcon#enter wrdev, iclass 18, count 0 2006.253.07:35:00.29#ibcon#first serial, iclass 18, count 0 2006.253.07:35:00.29#ibcon#enter sib2, iclass 18, count 0 2006.253.07:35:00.29#ibcon#flushed, iclass 18, count 0 2006.253.07:35:00.29#ibcon#about to write, iclass 18, count 0 2006.253.07:35:00.29#ibcon#wrote, iclass 18, count 0 2006.253.07:35:00.29#ibcon#about to read 3, iclass 18, count 0 2006.253.07:35:00.31#ibcon#read 3, iclass 18, count 0 2006.253.07:35:00.31#ibcon#about to read 4, iclass 18, count 0 2006.253.07:35:00.31#ibcon#read 4, iclass 18, count 0 2006.253.07:35:00.31#ibcon#about to read 5, iclass 18, count 0 2006.253.07:35:00.31#ibcon#read 5, iclass 18, count 0 2006.253.07:35:00.31#ibcon#about to read 6, iclass 18, count 0 2006.253.07:35:00.31#ibcon#read 6, iclass 18, count 0 2006.253.07:35:00.31#ibcon#end of sib2, iclass 18, count 0 2006.253.07:35:00.31#ibcon#*mode == 0, iclass 18, count 0 2006.253.07:35:00.31#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.253.07:35:00.31#ibcon#[26=FRQ=08,852.99\r\n] 2006.253.07:35:00.31#ibcon#*before write, iclass 18, count 0 2006.253.07:35:00.31#ibcon#enter sib2, iclass 18, count 0 2006.253.07:35:00.31#ibcon#flushed, iclass 18, count 0 2006.253.07:35:00.31#ibcon#about to write, iclass 18, count 0 2006.253.07:35:00.31#ibcon#wrote, iclass 18, count 0 2006.253.07:35:00.31#ibcon#about to read 3, iclass 18, count 0 2006.253.07:35:00.35#ibcon#read 3, iclass 18, count 0 2006.253.07:35:00.35#ibcon#about to read 4, iclass 18, count 0 2006.253.07:35:00.35#ibcon#read 4, iclass 18, count 0 2006.253.07:35:00.35#ibcon#about to read 5, iclass 18, count 0 2006.253.07:35:00.35#ibcon#read 5, iclass 18, count 0 2006.253.07:35:00.35#ibcon#about to read 6, iclass 18, count 0 2006.253.07:35:00.35#ibcon#read 6, iclass 18, count 0 2006.253.07:35:00.35#ibcon#end of sib2, iclass 18, count 0 2006.253.07:35:00.35#ibcon#*after write, iclass 18, count 0 2006.253.07:35:00.35#ibcon#*before return 0, iclass 18, count 0 2006.253.07:35:00.35#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.253.07:35:00.35#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.253.07:35:00.35#ibcon#about to clear, iclass 18 cls_cnt 0 2006.253.07:35:00.35#ibcon#cleared, iclass 18 cls_cnt 0 2006.253.07:35:00.35$vc4f8/va=8,7 2006.253.07:35:00.35#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.253.07:35:00.35#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.253.07:35:00.35#ibcon#ireg 11 cls_cnt 2 2006.253.07:35:00.35#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.253.07:35:00.41#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.253.07:35:00.41#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.253.07:35:00.41#ibcon#enter wrdev, iclass 20, count 2 2006.253.07:35:00.41#ibcon#first serial, iclass 20, count 2 2006.253.07:35:00.41#ibcon#enter sib2, iclass 20, count 2 2006.253.07:35:00.41#ibcon#flushed, iclass 20, count 2 2006.253.07:35:00.41#ibcon#about to write, iclass 20, count 2 2006.253.07:35:00.41#ibcon#wrote, iclass 20, count 2 2006.253.07:35:00.41#ibcon#about to read 3, iclass 20, count 2 2006.253.07:35:00.43#ibcon#read 3, iclass 20, count 2 2006.253.07:35:00.43#ibcon#about to read 4, iclass 20, count 2 2006.253.07:35:00.43#ibcon#read 4, iclass 20, count 2 2006.253.07:35:00.43#ibcon#about to read 5, iclass 20, count 2 2006.253.07:35:00.43#ibcon#read 5, iclass 20, count 2 2006.253.07:35:00.43#ibcon#about to read 6, iclass 20, count 2 2006.253.07:35:00.43#ibcon#read 6, iclass 20, count 2 2006.253.07:35:00.43#ibcon#end of sib2, iclass 20, count 2 2006.253.07:35:00.43#ibcon#*mode == 0, iclass 20, count 2 2006.253.07:35:00.43#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.253.07:35:00.43#ibcon#[25=AT08-07\r\n] 2006.253.07:35:00.43#ibcon#*before write, iclass 20, count 2 2006.253.07:35:00.43#ibcon#enter sib2, iclass 20, count 2 2006.253.07:35:00.43#ibcon#flushed, iclass 20, count 2 2006.253.07:35:00.43#ibcon#about to write, iclass 20, count 2 2006.253.07:35:00.43#ibcon#wrote, iclass 20, count 2 2006.253.07:35:00.43#ibcon#about to read 3, iclass 20, count 2 2006.253.07:35:00.46#ibcon#read 3, iclass 20, count 2 2006.253.07:35:00.46#ibcon#about to read 4, iclass 20, count 2 2006.253.07:35:00.46#ibcon#read 4, iclass 20, count 2 2006.253.07:35:00.46#ibcon#about to read 5, iclass 20, count 2 2006.253.07:35:00.46#ibcon#read 5, iclass 20, count 2 2006.253.07:35:00.46#ibcon#about to read 6, iclass 20, count 2 2006.253.07:35:00.46#ibcon#read 6, iclass 20, count 2 2006.253.07:35:00.46#ibcon#end of sib2, iclass 20, count 2 2006.253.07:35:00.46#ibcon#*after write, iclass 20, count 2 2006.253.07:35:00.46#ibcon#*before return 0, iclass 20, count 2 2006.253.07:35:00.46#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.253.07:35:00.46#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.253.07:35:00.46#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.253.07:35:00.46#ibcon#ireg 7 cls_cnt 0 2006.253.07:35:00.46#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.253.07:35:00.58#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.253.07:35:00.58#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.253.07:35:00.58#ibcon#enter wrdev, iclass 20, count 0 2006.253.07:35:00.58#ibcon#first serial, iclass 20, count 0 2006.253.07:35:00.58#ibcon#enter sib2, iclass 20, count 0 2006.253.07:35:00.58#ibcon#flushed, iclass 20, count 0 2006.253.07:35:00.58#ibcon#about to write, iclass 20, count 0 2006.253.07:35:00.58#ibcon#wrote, iclass 20, count 0 2006.253.07:35:00.58#ibcon#about to read 3, iclass 20, count 0 2006.253.07:35:00.60#ibcon#read 3, iclass 20, count 0 2006.253.07:35:00.60#ibcon#about to read 4, iclass 20, count 0 2006.253.07:35:00.60#ibcon#read 4, iclass 20, count 0 2006.253.07:35:00.60#ibcon#about to read 5, iclass 20, count 0 2006.253.07:35:00.60#ibcon#read 5, iclass 20, count 0 2006.253.07:35:00.60#ibcon#about to read 6, iclass 20, count 0 2006.253.07:35:00.60#ibcon#read 6, iclass 20, count 0 2006.253.07:35:00.60#ibcon#end of sib2, iclass 20, count 0 2006.253.07:35:00.60#ibcon#*mode == 0, iclass 20, count 0 2006.253.07:35:00.60#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.253.07:35:00.60#ibcon#[25=USB\r\n] 2006.253.07:35:00.60#ibcon#*before write, iclass 20, count 0 2006.253.07:35:00.60#ibcon#enter sib2, iclass 20, count 0 2006.253.07:35:00.60#ibcon#flushed, iclass 20, count 0 2006.253.07:35:00.60#ibcon#about to write, iclass 20, count 0 2006.253.07:35:00.60#ibcon#wrote, iclass 20, count 0 2006.253.07:35:00.60#ibcon#about to read 3, iclass 20, count 0 2006.253.07:35:00.63#ibcon#read 3, iclass 20, count 0 2006.253.07:35:00.63#ibcon#about to read 4, iclass 20, count 0 2006.253.07:35:00.63#ibcon#read 4, iclass 20, count 0 2006.253.07:35:00.63#ibcon#about to read 5, iclass 20, count 0 2006.253.07:35:00.63#ibcon#read 5, iclass 20, count 0 2006.253.07:35:00.63#ibcon#about to read 6, iclass 20, count 0 2006.253.07:35:00.63#ibcon#read 6, iclass 20, count 0 2006.253.07:35:00.63#ibcon#end of sib2, iclass 20, count 0 2006.253.07:35:00.63#ibcon#*after write, iclass 20, count 0 2006.253.07:35:00.63#ibcon#*before return 0, iclass 20, count 0 2006.253.07:35:00.63#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.253.07:35:00.63#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.253.07:35:00.63#ibcon#about to clear, iclass 20 cls_cnt 0 2006.253.07:35:00.63#ibcon#cleared, iclass 20 cls_cnt 0 2006.253.07:35:00.63$vc4f8/vblo=1,632.99 2006.253.07:35:00.63#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.253.07:35:00.63#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.253.07:35:00.63#ibcon#ireg 17 cls_cnt 0 2006.253.07:35:00.63#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.253.07:35:00.63#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.253.07:35:00.63#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.253.07:35:00.63#ibcon#enter wrdev, iclass 22, count 0 2006.253.07:35:00.63#ibcon#first serial, iclass 22, count 0 2006.253.07:35:00.63#ibcon#enter sib2, iclass 22, count 0 2006.253.07:35:00.63#ibcon#flushed, iclass 22, count 0 2006.253.07:35:00.63#ibcon#about to write, iclass 22, count 0 2006.253.07:35:00.63#ibcon#wrote, iclass 22, count 0 2006.253.07:35:00.63#ibcon#about to read 3, iclass 22, count 0 2006.253.07:35:00.65#ibcon#read 3, iclass 22, count 0 2006.253.07:35:00.65#ibcon#about to read 4, iclass 22, count 0 2006.253.07:35:00.65#ibcon#read 4, iclass 22, count 0 2006.253.07:35:00.65#ibcon#about to read 5, iclass 22, count 0 2006.253.07:35:00.65#ibcon#read 5, iclass 22, count 0 2006.253.07:35:00.65#ibcon#about to read 6, iclass 22, count 0 2006.253.07:35:00.65#ibcon#read 6, iclass 22, count 0 2006.253.07:35:00.65#ibcon#end of sib2, iclass 22, count 0 2006.253.07:35:00.65#ibcon#*mode == 0, iclass 22, count 0 2006.253.07:35:00.65#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.253.07:35:00.65#ibcon#[28=FRQ=01,632.99\r\n] 2006.253.07:35:00.65#ibcon#*before write, iclass 22, count 0 2006.253.07:35:00.65#ibcon#enter sib2, iclass 22, count 0 2006.253.07:35:00.65#ibcon#flushed, iclass 22, count 0 2006.253.07:35:00.65#ibcon#about to write, iclass 22, count 0 2006.253.07:35:00.65#ibcon#wrote, iclass 22, count 0 2006.253.07:35:00.65#ibcon#about to read 3, iclass 22, count 0 2006.253.07:35:00.69#ibcon#read 3, iclass 22, count 0 2006.253.07:35:00.69#ibcon#about to read 4, iclass 22, count 0 2006.253.07:35:00.69#ibcon#read 4, iclass 22, count 0 2006.253.07:35:00.69#ibcon#about to read 5, iclass 22, count 0 2006.253.07:35:00.69#ibcon#read 5, iclass 22, count 0 2006.253.07:35:00.69#ibcon#about to read 6, iclass 22, count 0 2006.253.07:35:00.69#ibcon#read 6, iclass 22, count 0 2006.253.07:35:00.69#ibcon#end of sib2, iclass 22, count 0 2006.253.07:35:00.69#ibcon#*after write, iclass 22, count 0 2006.253.07:35:00.69#ibcon#*before return 0, iclass 22, count 0 2006.253.07:35:00.69#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.253.07:35:00.69#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.253.07:35:00.69#ibcon#about to clear, iclass 22 cls_cnt 0 2006.253.07:35:00.69#ibcon#cleared, iclass 22 cls_cnt 0 2006.253.07:35:00.69$vc4f8/vb=1,4 2006.253.07:35:00.69#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.253.07:35:00.69#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.253.07:35:00.69#ibcon#ireg 11 cls_cnt 2 2006.253.07:35:00.69#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.253.07:35:00.69#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.253.07:35:00.69#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.253.07:35:00.69#ibcon#enter wrdev, iclass 24, count 2 2006.253.07:35:00.69#ibcon#first serial, iclass 24, count 2 2006.253.07:35:00.69#ibcon#enter sib2, iclass 24, count 2 2006.253.07:35:00.69#ibcon#flushed, iclass 24, count 2 2006.253.07:35:00.69#ibcon#about to write, iclass 24, count 2 2006.253.07:35:00.69#ibcon#wrote, iclass 24, count 2 2006.253.07:35:00.69#ibcon#about to read 3, iclass 24, count 2 2006.253.07:35:00.71#ibcon#read 3, iclass 24, count 2 2006.253.07:35:00.71#ibcon#about to read 4, iclass 24, count 2 2006.253.07:35:00.71#ibcon#read 4, iclass 24, count 2 2006.253.07:35:00.71#ibcon#about to read 5, iclass 24, count 2 2006.253.07:35:00.71#ibcon#read 5, iclass 24, count 2 2006.253.07:35:00.71#ibcon#about to read 6, iclass 24, count 2 2006.253.07:35:00.71#ibcon#read 6, iclass 24, count 2 2006.253.07:35:00.71#ibcon#end of sib2, iclass 24, count 2 2006.253.07:35:00.71#ibcon#*mode == 0, iclass 24, count 2 2006.253.07:35:00.71#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.253.07:35:00.71#ibcon#[27=AT01-04\r\n] 2006.253.07:35:00.71#ibcon#*before write, iclass 24, count 2 2006.253.07:35:00.71#ibcon#enter sib2, iclass 24, count 2 2006.253.07:35:00.71#ibcon#flushed, iclass 24, count 2 2006.253.07:35:00.71#ibcon#about to write, iclass 24, count 2 2006.253.07:35:00.71#ibcon#wrote, iclass 24, count 2 2006.253.07:35:00.71#ibcon#about to read 3, iclass 24, count 2 2006.253.07:35:00.74#ibcon#read 3, iclass 24, count 2 2006.253.07:35:00.74#ibcon#about to read 4, iclass 24, count 2 2006.253.07:35:00.74#ibcon#read 4, iclass 24, count 2 2006.253.07:35:00.74#ibcon#about to read 5, iclass 24, count 2 2006.253.07:35:00.74#ibcon#read 5, iclass 24, count 2 2006.253.07:35:00.74#ibcon#about to read 6, iclass 24, count 2 2006.253.07:35:00.74#ibcon#read 6, iclass 24, count 2 2006.253.07:35:00.74#ibcon#end of sib2, iclass 24, count 2 2006.253.07:35:00.74#ibcon#*after write, iclass 24, count 2 2006.253.07:35:00.74#ibcon#*before return 0, iclass 24, count 2 2006.253.07:35:00.74#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.253.07:35:00.74#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.253.07:35:00.74#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.253.07:35:00.74#ibcon#ireg 7 cls_cnt 0 2006.253.07:35:00.74#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.253.07:35:00.86#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.253.07:35:00.86#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.253.07:35:00.86#ibcon#enter wrdev, iclass 24, count 0 2006.253.07:35:00.86#ibcon#first serial, iclass 24, count 0 2006.253.07:35:00.86#ibcon#enter sib2, iclass 24, count 0 2006.253.07:35:00.86#ibcon#flushed, iclass 24, count 0 2006.253.07:35:00.86#ibcon#about to write, iclass 24, count 0 2006.253.07:35:00.86#ibcon#wrote, iclass 24, count 0 2006.253.07:35:00.86#ibcon#about to read 3, iclass 24, count 0 2006.253.07:35:00.88#ibcon#read 3, iclass 24, count 0 2006.253.07:35:00.88#ibcon#about to read 4, iclass 24, count 0 2006.253.07:35:00.88#ibcon#read 4, iclass 24, count 0 2006.253.07:35:00.88#ibcon#about to read 5, iclass 24, count 0 2006.253.07:35:00.88#ibcon#read 5, iclass 24, count 0 2006.253.07:35:00.88#ibcon#about to read 6, iclass 24, count 0 2006.253.07:35:00.88#ibcon#read 6, iclass 24, count 0 2006.253.07:35:00.88#ibcon#end of sib2, iclass 24, count 0 2006.253.07:35:00.88#ibcon#*mode == 0, iclass 24, count 0 2006.253.07:35:00.88#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.253.07:35:00.88#ibcon#[27=USB\r\n] 2006.253.07:35:00.88#ibcon#*before write, iclass 24, count 0 2006.253.07:35:00.88#ibcon#enter sib2, iclass 24, count 0 2006.253.07:35:00.88#ibcon#flushed, iclass 24, count 0 2006.253.07:35:00.88#ibcon#about to write, iclass 24, count 0 2006.253.07:35:00.88#ibcon#wrote, iclass 24, count 0 2006.253.07:35:00.88#ibcon#about to read 3, iclass 24, count 0 2006.253.07:35:00.91#ibcon#read 3, iclass 24, count 0 2006.253.07:35:00.91#ibcon#about to read 4, iclass 24, count 0 2006.253.07:35:00.91#ibcon#read 4, iclass 24, count 0 2006.253.07:35:00.91#ibcon#about to read 5, iclass 24, count 0 2006.253.07:35:00.91#ibcon#read 5, iclass 24, count 0 2006.253.07:35:00.91#ibcon#about to read 6, iclass 24, count 0 2006.253.07:35:00.91#ibcon#read 6, iclass 24, count 0 2006.253.07:35:00.91#ibcon#end of sib2, iclass 24, count 0 2006.253.07:35:00.91#ibcon#*after write, iclass 24, count 0 2006.253.07:35:00.91#ibcon#*before return 0, iclass 24, count 0 2006.253.07:35:00.91#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.253.07:35:00.91#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.253.07:35:00.91#ibcon#about to clear, iclass 24 cls_cnt 0 2006.253.07:35:00.91#ibcon#cleared, iclass 24 cls_cnt 0 2006.253.07:35:00.91$vc4f8/vblo=2,640.99 2006.253.07:35:00.91#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.253.07:35:00.91#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.253.07:35:00.91#ibcon#ireg 17 cls_cnt 0 2006.253.07:35:00.91#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.253.07:35:00.91#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.253.07:35:00.91#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.253.07:35:00.91#ibcon#enter wrdev, iclass 26, count 0 2006.253.07:35:00.91#ibcon#first serial, iclass 26, count 0 2006.253.07:35:00.91#ibcon#enter sib2, iclass 26, count 0 2006.253.07:35:00.91#ibcon#flushed, iclass 26, count 0 2006.253.07:35:00.91#ibcon#about to write, iclass 26, count 0 2006.253.07:35:00.91#ibcon#wrote, iclass 26, count 0 2006.253.07:35:00.91#ibcon#about to read 3, iclass 26, count 0 2006.253.07:35:00.93#ibcon#read 3, iclass 26, count 0 2006.253.07:35:00.93#ibcon#about to read 4, iclass 26, count 0 2006.253.07:35:00.93#ibcon#read 4, iclass 26, count 0 2006.253.07:35:00.93#ibcon#about to read 5, iclass 26, count 0 2006.253.07:35:00.93#ibcon#read 5, iclass 26, count 0 2006.253.07:35:00.93#ibcon#about to read 6, iclass 26, count 0 2006.253.07:35:00.93#ibcon#read 6, iclass 26, count 0 2006.253.07:35:00.93#ibcon#end of sib2, iclass 26, count 0 2006.253.07:35:00.93#ibcon#*mode == 0, iclass 26, count 0 2006.253.07:35:00.93#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.253.07:35:00.93#ibcon#[28=FRQ=02,640.99\r\n] 2006.253.07:35:00.93#ibcon#*before write, iclass 26, count 0 2006.253.07:35:00.93#ibcon#enter sib2, iclass 26, count 0 2006.253.07:35:00.93#ibcon#flushed, iclass 26, count 0 2006.253.07:35:00.93#ibcon#about to write, iclass 26, count 0 2006.253.07:35:00.93#ibcon#wrote, iclass 26, count 0 2006.253.07:35:00.93#ibcon#about to read 3, iclass 26, count 0 2006.253.07:35:00.97#ibcon#read 3, iclass 26, count 0 2006.253.07:35:00.97#ibcon#about to read 4, iclass 26, count 0 2006.253.07:35:00.97#ibcon#read 4, iclass 26, count 0 2006.253.07:35:00.97#ibcon#about to read 5, iclass 26, count 0 2006.253.07:35:00.97#ibcon#read 5, iclass 26, count 0 2006.253.07:35:00.97#ibcon#about to read 6, iclass 26, count 0 2006.253.07:35:00.97#ibcon#read 6, iclass 26, count 0 2006.253.07:35:00.97#ibcon#end of sib2, iclass 26, count 0 2006.253.07:35:00.97#ibcon#*after write, iclass 26, count 0 2006.253.07:35:00.97#ibcon#*before return 0, iclass 26, count 0 2006.253.07:35:00.97#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.253.07:35:00.97#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.253.07:35:00.97#ibcon#about to clear, iclass 26 cls_cnt 0 2006.253.07:35:00.97#ibcon#cleared, iclass 26 cls_cnt 0 2006.253.07:35:00.97$vc4f8/vb=2,5 2006.253.07:35:00.97#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.253.07:35:00.97#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.253.07:35:00.97#ibcon#ireg 11 cls_cnt 2 2006.253.07:35:00.97#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.253.07:35:01.03#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.253.07:35:01.03#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.253.07:35:01.03#ibcon#enter wrdev, iclass 28, count 2 2006.253.07:35:01.03#ibcon#first serial, iclass 28, count 2 2006.253.07:35:01.03#ibcon#enter sib2, iclass 28, count 2 2006.253.07:35:01.03#ibcon#flushed, iclass 28, count 2 2006.253.07:35:01.03#ibcon#about to write, iclass 28, count 2 2006.253.07:35:01.03#ibcon#wrote, iclass 28, count 2 2006.253.07:35:01.03#ibcon#about to read 3, iclass 28, count 2 2006.253.07:35:01.05#ibcon#read 3, iclass 28, count 2 2006.253.07:35:01.05#ibcon#about to read 4, iclass 28, count 2 2006.253.07:35:01.05#ibcon#read 4, iclass 28, count 2 2006.253.07:35:01.05#ibcon#about to read 5, iclass 28, count 2 2006.253.07:35:01.05#ibcon#read 5, iclass 28, count 2 2006.253.07:35:01.05#ibcon#about to read 6, iclass 28, count 2 2006.253.07:35:01.05#ibcon#read 6, iclass 28, count 2 2006.253.07:35:01.05#ibcon#end of sib2, iclass 28, count 2 2006.253.07:35:01.05#ibcon#*mode == 0, iclass 28, count 2 2006.253.07:35:01.05#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.253.07:35:01.05#ibcon#[27=AT02-05\r\n] 2006.253.07:35:01.05#ibcon#*before write, iclass 28, count 2 2006.253.07:35:01.05#ibcon#enter sib2, iclass 28, count 2 2006.253.07:35:01.05#ibcon#flushed, iclass 28, count 2 2006.253.07:35:01.05#ibcon#about to write, iclass 28, count 2 2006.253.07:35:01.05#ibcon#wrote, iclass 28, count 2 2006.253.07:35:01.05#ibcon#about to read 3, iclass 28, count 2 2006.253.07:35:01.08#ibcon#read 3, iclass 28, count 2 2006.253.07:35:01.08#ibcon#about to read 4, iclass 28, count 2 2006.253.07:35:01.08#ibcon#read 4, iclass 28, count 2 2006.253.07:35:01.08#ibcon#about to read 5, iclass 28, count 2 2006.253.07:35:01.08#ibcon#read 5, iclass 28, count 2 2006.253.07:35:01.08#ibcon#about to read 6, iclass 28, count 2 2006.253.07:35:01.08#ibcon#read 6, iclass 28, count 2 2006.253.07:35:01.08#ibcon#end of sib2, iclass 28, count 2 2006.253.07:35:01.08#ibcon#*after write, iclass 28, count 2 2006.253.07:35:01.08#ibcon#*before return 0, iclass 28, count 2 2006.253.07:35:01.08#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.253.07:35:01.08#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.253.07:35:01.08#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.253.07:35:01.08#ibcon#ireg 7 cls_cnt 0 2006.253.07:35:01.08#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.253.07:35:01.20#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.253.07:35:01.20#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.253.07:35:01.20#ibcon#enter wrdev, iclass 28, count 0 2006.253.07:35:01.20#ibcon#first serial, iclass 28, count 0 2006.253.07:35:01.20#ibcon#enter sib2, iclass 28, count 0 2006.253.07:35:01.20#ibcon#flushed, iclass 28, count 0 2006.253.07:35:01.20#ibcon#about to write, iclass 28, count 0 2006.253.07:35:01.20#ibcon#wrote, iclass 28, count 0 2006.253.07:35:01.20#ibcon#about to read 3, iclass 28, count 0 2006.253.07:35:01.22#ibcon#read 3, iclass 28, count 0 2006.253.07:35:01.22#ibcon#about to read 4, iclass 28, count 0 2006.253.07:35:01.22#ibcon#read 4, iclass 28, count 0 2006.253.07:35:01.22#ibcon#about to read 5, iclass 28, count 0 2006.253.07:35:01.22#ibcon#read 5, iclass 28, count 0 2006.253.07:35:01.22#ibcon#about to read 6, iclass 28, count 0 2006.253.07:35:01.22#ibcon#read 6, iclass 28, count 0 2006.253.07:35:01.22#ibcon#end of sib2, iclass 28, count 0 2006.253.07:35:01.22#ibcon#*mode == 0, iclass 28, count 0 2006.253.07:35:01.22#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.253.07:35:01.22#ibcon#[27=USB\r\n] 2006.253.07:35:01.22#ibcon#*before write, iclass 28, count 0 2006.253.07:35:01.22#ibcon#enter sib2, iclass 28, count 0 2006.253.07:35:01.22#ibcon#flushed, iclass 28, count 0 2006.253.07:35:01.22#ibcon#about to write, iclass 28, count 0 2006.253.07:35:01.22#ibcon#wrote, iclass 28, count 0 2006.253.07:35:01.22#ibcon#about to read 3, iclass 28, count 0 2006.253.07:35:01.25#ibcon#read 3, iclass 28, count 0 2006.253.07:35:01.25#ibcon#about to read 4, iclass 28, count 0 2006.253.07:35:01.25#ibcon#read 4, iclass 28, count 0 2006.253.07:35:01.25#ibcon#about to read 5, iclass 28, count 0 2006.253.07:35:01.25#ibcon#read 5, iclass 28, count 0 2006.253.07:35:01.25#ibcon#about to read 6, iclass 28, count 0 2006.253.07:35:01.25#ibcon#read 6, iclass 28, count 0 2006.253.07:35:01.25#ibcon#end of sib2, iclass 28, count 0 2006.253.07:35:01.25#ibcon#*after write, iclass 28, count 0 2006.253.07:35:01.25#ibcon#*before return 0, iclass 28, count 0 2006.253.07:35:01.25#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.253.07:35:01.25#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.253.07:35:01.25#ibcon#about to clear, iclass 28 cls_cnt 0 2006.253.07:35:01.25#ibcon#cleared, iclass 28 cls_cnt 0 2006.253.07:35:01.25$vc4f8/vblo=3,656.99 2006.253.07:35:01.25#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.253.07:35:01.25#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.253.07:35:01.25#ibcon#ireg 17 cls_cnt 0 2006.253.07:35:01.25#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.253.07:35:01.25#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.253.07:35:01.25#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.253.07:35:01.25#ibcon#enter wrdev, iclass 30, count 0 2006.253.07:35:01.25#ibcon#first serial, iclass 30, count 0 2006.253.07:35:01.25#ibcon#enter sib2, iclass 30, count 0 2006.253.07:35:01.25#ibcon#flushed, iclass 30, count 0 2006.253.07:35:01.25#ibcon#about to write, iclass 30, count 0 2006.253.07:35:01.25#ibcon#wrote, iclass 30, count 0 2006.253.07:35:01.25#ibcon#about to read 3, iclass 30, count 0 2006.253.07:35:01.27#ibcon#read 3, iclass 30, count 0 2006.253.07:35:01.27#ibcon#about to read 4, iclass 30, count 0 2006.253.07:35:01.27#ibcon#read 4, iclass 30, count 0 2006.253.07:35:01.27#ibcon#about to read 5, iclass 30, count 0 2006.253.07:35:01.27#ibcon#read 5, iclass 30, count 0 2006.253.07:35:01.27#ibcon#about to read 6, iclass 30, count 0 2006.253.07:35:01.27#ibcon#read 6, iclass 30, count 0 2006.253.07:35:01.27#ibcon#end of sib2, iclass 30, count 0 2006.253.07:35:01.27#ibcon#*mode == 0, iclass 30, count 0 2006.253.07:35:01.27#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.253.07:35:01.27#ibcon#[28=FRQ=03,656.99\r\n] 2006.253.07:35:01.27#ibcon#*before write, iclass 30, count 0 2006.253.07:35:01.27#ibcon#enter sib2, iclass 30, count 0 2006.253.07:35:01.27#ibcon#flushed, iclass 30, count 0 2006.253.07:35:01.27#ibcon#about to write, iclass 30, count 0 2006.253.07:35:01.27#ibcon#wrote, iclass 30, count 0 2006.253.07:35:01.27#ibcon#about to read 3, iclass 30, count 0 2006.253.07:35:01.31#ibcon#read 3, iclass 30, count 0 2006.253.07:35:01.31#ibcon#about to read 4, iclass 30, count 0 2006.253.07:35:01.31#ibcon#read 4, iclass 30, count 0 2006.253.07:35:01.31#ibcon#about to read 5, iclass 30, count 0 2006.253.07:35:01.31#ibcon#read 5, iclass 30, count 0 2006.253.07:35:01.31#ibcon#about to read 6, iclass 30, count 0 2006.253.07:35:01.31#ibcon#read 6, iclass 30, count 0 2006.253.07:35:01.31#ibcon#end of sib2, iclass 30, count 0 2006.253.07:35:01.31#ibcon#*after write, iclass 30, count 0 2006.253.07:35:01.31#ibcon#*before return 0, iclass 30, count 0 2006.253.07:35:01.31#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.253.07:35:01.31#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.253.07:35:01.31#ibcon#about to clear, iclass 30 cls_cnt 0 2006.253.07:35:01.31#ibcon#cleared, iclass 30 cls_cnt 0 2006.253.07:35:01.31$vc4f8/vb=3,4 2006.253.07:35:01.31#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.253.07:35:01.31#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.253.07:35:01.31#ibcon#ireg 11 cls_cnt 2 2006.253.07:35:01.31#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.253.07:35:01.37#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.253.07:35:01.37#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.253.07:35:01.37#ibcon#enter wrdev, iclass 32, count 2 2006.253.07:35:01.37#ibcon#first serial, iclass 32, count 2 2006.253.07:35:01.37#ibcon#enter sib2, iclass 32, count 2 2006.253.07:35:01.37#ibcon#flushed, iclass 32, count 2 2006.253.07:35:01.37#ibcon#about to write, iclass 32, count 2 2006.253.07:35:01.37#ibcon#wrote, iclass 32, count 2 2006.253.07:35:01.37#ibcon#about to read 3, iclass 32, count 2 2006.253.07:35:01.39#ibcon#read 3, iclass 32, count 2 2006.253.07:35:01.39#ibcon#about to read 4, iclass 32, count 2 2006.253.07:35:01.39#ibcon#read 4, iclass 32, count 2 2006.253.07:35:01.39#ibcon#about to read 5, iclass 32, count 2 2006.253.07:35:01.39#ibcon#read 5, iclass 32, count 2 2006.253.07:35:01.39#ibcon#about to read 6, iclass 32, count 2 2006.253.07:35:01.39#ibcon#read 6, iclass 32, count 2 2006.253.07:35:01.39#ibcon#end of sib2, iclass 32, count 2 2006.253.07:35:01.39#ibcon#*mode == 0, iclass 32, count 2 2006.253.07:35:01.39#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.253.07:35:01.39#ibcon#[27=AT03-04\r\n] 2006.253.07:35:01.39#ibcon#*before write, iclass 32, count 2 2006.253.07:35:01.39#ibcon#enter sib2, iclass 32, count 2 2006.253.07:35:01.39#ibcon#flushed, iclass 32, count 2 2006.253.07:35:01.39#ibcon#about to write, iclass 32, count 2 2006.253.07:35:01.39#ibcon#wrote, iclass 32, count 2 2006.253.07:35:01.39#ibcon#about to read 3, iclass 32, count 2 2006.253.07:35:01.42#ibcon#read 3, iclass 32, count 2 2006.253.07:35:01.42#ibcon#about to read 4, iclass 32, count 2 2006.253.07:35:01.42#ibcon#read 4, iclass 32, count 2 2006.253.07:35:01.42#ibcon#about to read 5, iclass 32, count 2 2006.253.07:35:01.42#ibcon#read 5, iclass 32, count 2 2006.253.07:35:01.42#ibcon#about to read 6, iclass 32, count 2 2006.253.07:35:01.42#ibcon#read 6, iclass 32, count 2 2006.253.07:35:01.42#ibcon#end of sib2, iclass 32, count 2 2006.253.07:35:01.42#ibcon#*after write, iclass 32, count 2 2006.253.07:35:01.42#ibcon#*before return 0, iclass 32, count 2 2006.253.07:35:01.42#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.253.07:35:01.42#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.253.07:35:01.42#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.253.07:35:01.42#ibcon#ireg 7 cls_cnt 0 2006.253.07:35:01.42#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.253.07:35:01.54#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.253.07:35:01.54#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.253.07:35:01.54#ibcon#enter wrdev, iclass 32, count 0 2006.253.07:35:01.54#ibcon#first serial, iclass 32, count 0 2006.253.07:35:01.54#ibcon#enter sib2, iclass 32, count 0 2006.253.07:35:01.54#ibcon#flushed, iclass 32, count 0 2006.253.07:35:01.54#ibcon#about to write, iclass 32, count 0 2006.253.07:35:01.54#ibcon#wrote, iclass 32, count 0 2006.253.07:35:01.54#ibcon#about to read 3, iclass 32, count 0 2006.253.07:35:01.56#ibcon#read 3, iclass 32, count 0 2006.253.07:35:01.56#ibcon#about to read 4, iclass 32, count 0 2006.253.07:35:01.56#ibcon#read 4, iclass 32, count 0 2006.253.07:35:01.56#ibcon#about to read 5, iclass 32, count 0 2006.253.07:35:01.56#ibcon#read 5, iclass 32, count 0 2006.253.07:35:01.56#ibcon#about to read 6, iclass 32, count 0 2006.253.07:35:01.56#ibcon#read 6, iclass 32, count 0 2006.253.07:35:01.56#ibcon#end of sib2, iclass 32, count 0 2006.253.07:35:01.56#ibcon#*mode == 0, iclass 32, count 0 2006.253.07:35:01.56#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.253.07:35:01.56#ibcon#[27=USB\r\n] 2006.253.07:35:01.56#ibcon#*before write, iclass 32, count 0 2006.253.07:35:01.56#ibcon#enter sib2, iclass 32, count 0 2006.253.07:35:01.56#ibcon#flushed, iclass 32, count 0 2006.253.07:35:01.56#ibcon#about to write, iclass 32, count 0 2006.253.07:35:01.56#ibcon#wrote, iclass 32, count 0 2006.253.07:35:01.56#ibcon#about to read 3, iclass 32, count 0 2006.253.07:35:01.59#ibcon#read 3, iclass 32, count 0 2006.253.07:35:01.59#ibcon#about to read 4, iclass 32, count 0 2006.253.07:35:01.59#ibcon#read 4, iclass 32, count 0 2006.253.07:35:01.59#ibcon#about to read 5, iclass 32, count 0 2006.253.07:35:01.59#ibcon#read 5, iclass 32, count 0 2006.253.07:35:01.59#ibcon#about to read 6, iclass 32, count 0 2006.253.07:35:01.59#ibcon#read 6, iclass 32, count 0 2006.253.07:35:01.59#ibcon#end of sib2, iclass 32, count 0 2006.253.07:35:01.59#ibcon#*after write, iclass 32, count 0 2006.253.07:35:01.59#ibcon#*before return 0, iclass 32, count 0 2006.253.07:35:01.59#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.253.07:35:01.59#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.253.07:35:01.59#ibcon#about to clear, iclass 32 cls_cnt 0 2006.253.07:35:01.59#ibcon#cleared, iclass 32 cls_cnt 0 2006.253.07:35:01.59$vc4f8/vblo=4,712.99 2006.253.07:35:01.59#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.253.07:35:01.59#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.253.07:35:01.59#ibcon#ireg 17 cls_cnt 0 2006.253.07:35:01.59#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.253.07:35:01.59#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.253.07:35:01.59#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.253.07:35:01.59#ibcon#enter wrdev, iclass 34, count 0 2006.253.07:35:01.59#ibcon#first serial, iclass 34, count 0 2006.253.07:35:01.59#ibcon#enter sib2, iclass 34, count 0 2006.253.07:35:01.59#ibcon#flushed, iclass 34, count 0 2006.253.07:35:01.59#ibcon#about to write, iclass 34, count 0 2006.253.07:35:01.59#ibcon#wrote, iclass 34, count 0 2006.253.07:35:01.59#ibcon#about to read 3, iclass 34, count 0 2006.253.07:35:01.61#ibcon#read 3, iclass 34, count 0 2006.253.07:35:01.61#ibcon#about to read 4, iclass 34, count 0 2006.253.07:35:01.61#ibcon#read 4, iclass 34, count 0 2006.253.07:35:01.61#ibcon#about to read 5, iclass 34, count 0 2006.253.07:35:01.61#ibcon#read 5, iclass 34, count 0 2006.253.07:35:01.61#ibcon#about to read 6, iclass 34, count 0 2006.253.07:35:01.61#ibcon#read 6, iclass 34, count 0 2006.253.07:35:01.61#ibcon#end of sib2, iclass 34, count 0 2006.253.07:35:01.61#ibcon#*mode == 0, iclass 34, count 0 2006.253.07:35:01.61#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.253.07:35:01.61#ibcon#[28=FRQ=04,712.99\r\n] 2006.253.07:35:01.61#ibcon#*before write, iclass 34, count 0 2006.253.07:35:01.61#ibcon#enter sib2, iclass 34, count 0 2006.253.07:35:01.61#ibcon#flushed, iclass 34, count 0 2006.253.07:35:01.61#ibcon#about to write, iclass 34, count 0 2006.253.07:35:01.61#ibcon#wrote, iclass 34, count 0 2006.253.07:35:01.61#ibcon#about to read 3, iclass 34, count 0 2006.253.07:35:01.65#ibcon#read 3, iclass 34, count 0 2006.253.07:35:01.65#ibcon#about to read 4, iclass 34, count 0 2006.253.07:35:01.65#ibcon#read 4, iclass 34, count 0 2006.253.07:35:01.65#ibcon#about to read 5, iclass 34, count 0 2006.253.07:35:01.65#ibcon#read 5, iclass 34, count 0 2006.253.07:35:01.65#ibcon#about to read 6, iclass 34, count 0 2006.253.07:35:01.65#ibcon#read 6, iclass 34, count 0 2006.253.07:35:01.65#ibcon#end of sib2, iclass 34, count 0 2006.253.07:35:01.65#ibcon#*after write, iclass 34, count 0 2006.253.07:35:01.65#ibcon#*before return 0, iclass 34, count 0 2006.253.07:35:01.65#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.253.07:35:01.65#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.253.07:35:01.65#ibcon#about to clear, iclass 34 cls_cnt 0 2006.253.07:35:01.65#ibcon#cleared, iclass 34 cls_cnt 0 2006.253.07:35:01.65$vc4f8/vb=4,4 2006.253.07:35:01.65#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.253.07:35:01.65#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.253.07:35:01.65#ibcon#ireg 11 cls_cnt 2 2006.253.07:35:01.65#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.253.07:35:01.71#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.253.07:35:01.71#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.253.07:35:01.71#ibcon#enter wrdev, iclass 36, count 2 2006.253.07:35:01.71#ibcon#first serial, iclass 36, count 2 2006.253.07:35:01.71#ibcon#enter sib2, iclass 36, count 2 2006.253.07:35:01.71#ibcon#flushed, iclass 36, count 2 2006.253.07:35:01.71#ibcon#about to write, iclass 36, count 2 2006.253.07:35:01.71#ibcon#wrote, iclass 36, count 2 2006.253.07:35:01.71#ibcon#about to read 3, iclass 36, count 2 2006.253.07:35:01.73#ibcon#read 3, iclass 36, count 2 2006.253.07:35:01.73#ibcon#about to read 4, iclass 36, count 2 2006.253.07:35:01.73#ibcon#read 4, iclass 36, count 2 2006.253.07:35:01.73#ibcon#about to read 5, iclass 36, count 2 2006.253.07:35:01.73#ibcon#read 5, iclass 36, count 2 2006.253.07:35:01.73#ibcon#about to read 6, iclass 36, count 2 2006.253.07:35:01.73#ibcon#read 6, iclass 36, count 2 2006.253.07:35:01.73#ibcon#end of sib2, iclass 36, count 2 2006.253.07:35:01.73#ibcon#*mode == 0, iclass 36, count 2 2006.253.07:35:01.73#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.253.07:35:01.73#ibcon#[27=AT04-04\r\n] 2006.253.07:35:01.73#ibcon#*before write, iclass 36, count 2 2006.253.07:35:01.73#ibcon#enter sib2, iclass 36, count 2 2006.253.07:35:01.73#ibcon#flushed, iclass 36, count 2 2006.253.07:35:01.73#ibcon#about to write, iclass 36, count 2 2006.253.07:35:01.73#ibcon#wrote, iclass 36, count 2 2006.253.07:35:01.73#ibcon#about to read 3, iclass 36, count 2 2006.253.07:35:01.76#ibcon#read 3, iclass 36, count 2 2006.253.07:35:01.76#ibcon#about to read 4, iclass 36, count 2 2006.253.07:35:01.76#ibcon#read 4, iclass 36, count 2 2006.253.07:35:01.76#ibcon#about to read 5, iclass 36, count 2 2006.253.07:35:01.76#ibcon#read 5, iclass 36, count 2 2006.253.07:35:01.76#ibcon#about to read 6, iclass 36, count 2 2006.253.07:35:01.76#ibcon#read 6, iclass 36, count 2 2006.253.07:35:01.76#ibcon#end of sib2, iclass 36, count 2 2006.253.07:35:01.76#ibcon#*after write, iclass 36, count 2 2006.253.07:35:01.76#ibcon#*before return 0, iclass 36, count 2 2006.253.07:35:01.76#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.253.07:35:01.76#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.253.07:35:01.76#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.253.07:35:01.76#ibcon#ireg 7 cls_cnt 0 2006.253.07:35:01.76#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.253.07:35:01.88#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.253.07:35:01.88#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.253.07:35:01.88#ibcon#enter wrdev, iclass 36, count 0 2006.253.07:35:01.88#ibcon#first serial, iclass 36, count 0 2006.253.07:35:01.88#ibcon#enter sib2, iclass 36, count 0 2006.253.07:35:01.88#ibcon#flushed, iclass 36, count 0 2006.253.07:35:01.88#ibcon#about to write, iclass 36, count 0 2006.253.07:35:01.88#ibcon#wrote, iclass 36, count 0 2006.253.07:35:01.88#ibcon#about to read 3, iclass 36, count 0 2006.253.07:35:01.90#ibcon#read 3, iclass 36, count 0 2006.253.07:35:01.90#ibcon#about to read 4, iclass 36, count 0 2006.253.07:35:01.90#ibcon#read 4, iclass 36, count 0 2006.253.07:35:01.90#ibcon#about to read 5, iclass 36, count 0 2006.253.07:35:01.90#ibcon#read 5, iclass 36, count 0 2006.253.07:35:01.90#ibcon#about to read 6, iclass 36, count 0 2006.253.07:35:01.90#ibcon#read 6, iclass 36, count 0 2006.253.07:35:01.90#ibcon#end of sib2, iclass 36, count 0 2006.253.07:35:01.90#ibcon#*mode == 0, iclass 36, count 0 2006.253.07:35:01.90#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.253.07:35:01.90#ibcon#[27=USB\r\n] 2006.253.07:35:01.90#ibcon#*before write, iclass 36, count 0 2006.253.07:35:01.90#ibcon#enter sib2, iclass 36, count 0 2006.253.07:35:01.90#ibcon#flushed, iclass 36, count 0 2006.253.07:35:01.90#ibcon#about to write, iclass 36, count 0 2006.253.07:35:01.90#ibcon#wrote, iclass 36, count 0 2006.253.07:35:01.90#ibcon#about to read 3, iclass 36, count 0 2006.253.07:35:01.93#ibcon#read 3, iclass 36, count 0 2006.253.07:35:01.93#ibcon#about to read 4, iclass 36, count 0 2006.253.07:35:01.93#ibcon#read 4, iclass 36, count 0 2006.253.07:35:01.93#ibcon#about to read 5, iclass 36, count 0 2006.253.07:35:01.93#ibcon#read 5, iclass 36, count 0 2006.253.07:35:01.93#ibcon#about to read 6, iclass 36, count 0 2006.253.07:35:01.93#ibcon#read 6, iclass 36, count 0 2006.253.07:35:01.93#ibcon#end of sib2, iclass 36, count 0 2006.253.07:35:01.93#ibcon#*after write, iclass 36, count 0 2006.253.07:35:01.93#ibcon#*before return 0, iclass 36, count 0 2006.253.07:35:01.93#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.253.07:35:01.93#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.253.07:35:01.93#ibcon#about to clear, iclass 36 cls_cnt 0 2006.253.07:35:01.93#ibcon#cleared, iclass 36 cls_cnt 0 2006.253.07:35:01.93$vc4f8/vblo=5,744.99 2006.253.07:35:01.93#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.253.07:35:01.93#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.253.07:35:01.93#ibcon#ireg 17 cls_cnt 0 2006.253.07:35:01.93#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.253.07:35:01.93#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.253.07:35:01.93#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.253.07:35:01.93#ibcon#enter wrdev, iclass 38, count 0 2006.253.07:35:01.93#ibcon#first serial, iclass 38, count 0 2006.253.07:35:01.93#ibcon#enter sib2, iclass 38, count 0 2006.253.07:35:01.93#ibcon#flushed, iclass 38, count 0 2006.253.07:35:01.93#ibcon#about to write, iclass 38, count 0 2006.253.07:35:01.93#ibcon#wrote, iclass 38, count 0 2006.253.07:35:01.93#ibcon#about to read 3, iclass 38, count 0 2006.253.07:35:01.95#ibcon#read 3, iclass 38, count 0 2006.253.07:35:01.95#ibcon#about to read 4, iclass 38, count 0 2006.253.07:35:01.95#ibcon#read 4, iclass 38, count 0 2006.253.07:35:01.95#ibcon#about to read 5, iclass 38, count 0 2006.253.07:35:01.95#ibcon#read 5, iclass 38, count 0 2006.253.07:35:01.95#ibcon#about to read 6, iclass 38, count 0 2006.253.07:35:01.95#ibcon#read 6, iclass 38, count 0 2006.253.07:35:01.95#ibcon#end of sib2, iclass 38, count 0 2006.253.07:35:01.95#ibcon#*mode == 0, iclass 38, count 0 2006.253.07:35:01.95#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.253.07:35:01.95#ibcon#[28=FRQ=05,744.99\r\n] 2006.253.07:35:01.95#ibcon#*before write, iclass 38, count 0 2006.253.07:35:01.95#ibcon#enter sib2, iclass 38, count 0 2006.253.07:35:01.95#ibcon#flushed, iclass 38, count 0 2006.253.07:35:01.95#ibcon#about to write, iclass 38, count 0 2006.253.07:35:01.95#ibcon#wrote, iclass 38, count 0 2006.253.07:35:01.95#ibcon#about to read 3, iclass 38, count 0 2006.253.07:35:02.00#ibcon#read 3, iclass 38, count 0 2006.253.07:35:02.00#ibcon#about to read 4, iclass 38, count 0 2006.253.07:35:02.00#ibcon#read 4, iclass 38, count 0 2006.253.07:35:02.00#ibcon#about to read 5, iclass 38, count 0 2006.253.07:35:02.00#ibcon#read 5, iclass 38, count 0 2006.253.07:35:02.00#ibcon#about to read 6, iclass 38, count 0 2006.253.07:35:02.00#ibcon#read 6, iclass 38, count 0 2006.253.07:35:02.00#ibcon#end of sib2, iclass 38, count 0 2006.253.07:35:02.00#ibcon#*after write, iclass 38, count 0 2006.253.07:35:02.00#ibcon#*before return 0, iclass 38, count 0 2006.253.07:35:02.00#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.253.07:35:02.00#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.253.07:35:02.00#ibcon#about to clear, iclass 38 cls_cnt 0 2006.253.07:35:02.00#ibcon#cleared, iclass 38 cls_cnt 0 2006.253.07:35:02.00$vc4f8/vb=5,4 2006.253.07:35:02.00#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.253.07:35:02.00#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.253.07:35:02.00#ibcon#ireg 11 cls_cnt 2 2006.253.07:35:02.00#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.253.07:35:02.05#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.253.07:35:02.05#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.253.07:35:02.05#ibcon#enter wrdev, iclass 40, count 2 2006.253.07:35:02.05#ibcon#first serial, iclass 40, count 2 2006.253.07:35:02.05#ibcon#enter sib2, iclass 40, count 2 2006.253.07:35:02.05#ibcon#flushed, iclass 40, count 2 2006.253.07:35:02.05#ibcon#about to write, iclass 40, count 2 2006.253.07:35:02.05#ibcon#wrote, iclass 40, count 2 2006.253.07:35:02.05#ibcon#about to read 3, iclass 40, count 2 2006.253.07:35:02.07#ibcon#read 3, iclass 40, count 2 2006.253.07:35:02.07#ibcon#about to read 4, iclass 40, count 2 2006.253.07:35:02.07#ibcon#read 4, iclass 40, count 2 2006.253.07:35:02.07#ibcon#about to read 5, iclass 40, count 2 2006.253.07:35:02.07#ibcon#read 5, iclass 40, count 2 2006.253.07:35:02.07#ibcon#about to read 6, iclass 40, count 2 2006.253.07:35:02.07#ibcon#read 6, iclass 40, count 2 2006.253.07:35:02.07#ibcon#end of sib2, iclass 40, count 2 2006.253.07:35:02.07#ibcon#*mode == 0, iclass 40, count 2 2006.253.07:35:02.07#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.253.07:35:02.07#ibcon#[27=AT05-04\r\n] 2006.253.07:35:02.07#ibcon#*before write, iclass 40, count 2 2006.253.07:35:02.07#ibcon#enter sib2, iclass 40, count 2 2006.253.07:35:02.07#ibcon#flushed, iclass 40, count 2 2006.253.07:35:02.07#ibcon#about to write, iclass 40, count 2 2006.253.07:35:02.07#ibcon#wrote, iclass 40, count 2 2006.253.07:35:02.07#ibcon#about to read 3, iclass 40, count 2 2006.253.07:35:02.10#ibcon#read 3, iclass 40, count 2 2006.253.07:35:02.10#ibcon#about to read 4, iclass 40, count 2 2006.253.07:35:02.10#ibcon#read 4, iclass 40, count 2 2006.253.07:35:02.10#ibcon#about to read 5, iclass 40, count 2 2006.253.07:35:02.10#ibcon#read 5, iclass 40, count 2 2006.253.07:35:02.10#ibcon#about to read 6, iclass 40, count 2 2006.253.07:35:02.10#ibcon#read 6, iclass 40, count 2 2006.253.07:35:02.10#ibcon#end of sib2, iclass 40, count 2 2006.253.07:35:02.10#ibcon#*after write, iclass 40, count 2 2006.253.07:35:02.10#ibcon#*before return 0, iclass 40, count 2 2006.253.07:35:02.10#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.253.07:35:02.10#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.253.07:35:02.10#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.253.07:35:02.10#ibcon#ireg 7 cls_cnt 0 2006.253.07:35:02.10#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.253.07:35:02.22#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.253.07:35:02.22#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.253.07:35:02.22#ibcon#enter wrdev, iclass 40, count 0 2006.253.07:35:02.22#ibcon#first serial, iclass 40, count 0 2006.253.07:35:02.22#ibcon#enter sib2, iclass 40, count 0 2006.253.07:35:02.22#ibcon#flushed, iclass 40, count 0 2006.253.07:35:02.22#ibcon#about to write, iclass 40, count 0 2006.253.07:35:02.22#ibcon#wrote, iclass 40, count 0 2006.253.07:35:02.22#ibcon#about to read 3, iclass 40, count 0 2006.253.07:35:02.24#ibcon#read 3, iclass 40, count 0 2006.253.07:35:02.24#ibcon#about to read 4, iclass 40, count 0 2006.253.07:35:02.24#ibcon#read 4, iclass 40, count 0 2006.253.07:35:02.24#ibcon#about to read 5, iclass 40, count 0 2006.253.07:35:02.24#ibcon#read 5, iclass 40, count 0 2006.253.07:35:02.24#ibcon#about to read 6, iclass 40, count 0 2006.253.07:35:02.24#ibcon#read 6, iclass 40, count 0 2006.253.07:35:02.24#ibcon#end of sib2, iclass 40, count 0 2006.253.07:35:02.24#ibcon#*mode == 0, iclass 40, count 0 2006.253.07:35:02.24#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.253.07:35:02.24#ibcon#[27=USB\r\n] 2006.253.07:35:02.24#ibcon#*before write, iclass 40, count 0 2006.253.07:35:02.24#ibcon#enter sib2, iclass 40, count 0 2006.253.07:35:02.24#ibcon#flushed, iclass 40, count 0 2006.253.07:35:02.24#ibcon#about to write, iclass 40, count 0 2006.253.07:35:02.24#ibcon#wrote, iclass 40, count 0 2006.253.07:35:02.24#ibcon#about to read 3, iclass 40, count 0 2006.253.07:35:02.27#ibcon#read 3, iclass 40, count 0 2006.253.07:35:02.27#ibcon#about to read 4, iclass 40, count 0 2006.253.07:35:02.27#ibcon#read 4, iclass 40, count 0 2006.253.07:35:02.27#ibcon#about to read 5, iclass 40, count 0 2006.253.07:35:02.27#ibcon#read 5, iclass 40, count 0 2006.253.07:35:02.27#ibcon#about to read 6, iclass 40, count 0 2006.253.07:35:02.27#ibcon#read 6, iclass 40, count 0 2006.253.07:35:02.27#ibcon#end of sib2, iclass 40, count 0 2006.253.07:35:02.27#ibcon#*after write, iclass 40, count 0 2006.253.07:35:02.27#ibcon#*before return 0, iclass 40, count 0 2006.253.07:35:02.27#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.253.07:35:02.27#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.253.07:35:02.27#ibcon#about to clear, iclass 40 cls_cnt 0 2006.253.07:35:02.27#ibcon#cleared, iclass 40 cls_cnt 0 2006.253.07:35:02.27$vc4f8/vblo=6,752.99 2006.253.07:35:02.27#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.253.07:35:02.27#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.253.07:35:02.27#ibcon#ireg 17 cls_cnt 0 2006.253.07:35:02.27#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.253.07:35:02.27#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.253.07:35:02.27#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.253.07:35:02.27#ibcon#enter wrdev, iclass 4, count 0 2006.253.07:35:02.27#ibcon#first serial, iclass 4, count 0 2006.253.07:35:02.27#ibcon#enter sib2, iclass 4, count 0 2006.253.07:35:02.27#ibcon#flushed, iclass 4, count 0 2006.253.07:35:02.27#ibcon#about to write, iclass 4, count 0 2006.253.07:35:02.27#ibcon#wrote, iclass 4, count 0 2006.253.07:35:02.27#ibcon#about to read 3, iclass 4, count 0 2006.253.07:35:02.29#ibcon#read 3, iclass 4, count 0 2006.253.07:35:02.29#ibcon#about to read 4, iclass 4, count 0 2006.253.07:35:02.29#ibcon#read 4, iclass 4, count 0 2006.253.07:35:02.29#ibcon#about to read 5, iclass 4, count 0 2006.253.07:35:02.29#ibcon#read 5, iclass 4, count 0 2006.253.07:35:02.29#ibcon#about to read 6, iclass 4, count 0 2006.253.07:35:02.29#ibcon#read 6, iclass 4, count 0 2006.253.07:35:02.29#ibcon#end of sib2, iclass 4, count 0 2006.253.07:35:02.29#ibcon#*mode == 0, iclass 4, count 0 2006.253.07:35:02.29#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.253.07:35:02.29#ibcon#[28=FRQ=06,752.99\r\n] 2006.253.07:35:02.29#ibcon#*before write, iclass 4, count 0 2006.253.07:35:02.29#ibcon#enter sib2, iclass 4, count 0 2006.253.07:35:02.29#ibcon#flushed, iclass 4, count 0 2006.253.07:35:02.29#ibcon#about to write, iclass 4, count 0 2006.253.07:35:02.29#ibcon#wrote, iclass 4, count 0 2006.253.07:35:02.29#ibcon#about to read 3, iclass 4, count 0 2006.253.07:35:02.33#ibcon#read 3, iclass 4, count 0 2006.253.07:35:02.33#ibcon#about to read 4, iclass 4, count 0 2006.253.07:35:02.33#ibcon#read 4, iclass 4, count 0 2006.253.07:35:02.33#ibcon#about to read 5, iclass 4, count 0 2006.253.07:35:02.33#ibcon#read 5, iclass 4, count 0 2006.253.07:35:02.33#ibcon#about to read 6, iclass 4, count 0 2006.253.07:35:02.33#ibcon#read 6, iclass 4, count 0 2006.253.07:35:02.33#ibcon#end of sib2, iclass 4, count 0 2006.253.07:35:02.33#ibcon#*after write, iclass 4, count 0 2006.253.07:35:02.33#ibcon#*before return 0, iclass 4, count 0 2006.253.07:35:02.33#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.253.07:35:02.33#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.253.07:35:02.33#ibcon#about to clear, iclass 4 cls_cnt 0 2006.253.07:35:02.33#ibcon#cleared, iclass 4 cls_cnt 0 2006.253.07:35:02.33$vc4f8/vb=6,4 2006.253.07:35:02.33#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.253.07:35:02.33#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.253.07:35:02.33#ibcon#ireg 11 cls_cnt 2 2006.253.07:35:02.33#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.253.07:35:02.39#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.253.07:35:02.39#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.253.07:35:02.39#ibcon#enter wrdev, iclass 6, count 2 2006.253.07:35:02.39#ibcon#first serial, iclass 6, count 2 2006.253.07:35:02.39#ibcon#enter sib2, iclass 6, count 2 2006.253.07:35:02.39#ibcon#flushed, iclass 6, count 2 2006.253.07:35:02.39#ibcon#about to write, iclass 6, count 2 2006.253.07:35:02.39#ibcon#wrote, iclass 6, count 2 2006.253.07:35:02.39#ibcon#about to read 3, iclass 6, count 2 2006.253.07:35:02.41#ibcon#read 3, iclass 6, count 2 2006.253.07:35:02.41#ibcon#about to read 4, iclass 6, count 2 2006.253.07:35:02.41#ibcon#read 4, iclass 6, count 2 2006.253.07:35:02.41#ibcon#about to read 5, iclass 6, count 2 2006.253.07:35:02.41#ibcon#read 5, iclass 6, count 2 2006.253.07:35:02.41#ibcon#about to read 6, iclass 6, count 2 2006.253.07:35:02.41#ibcon#read 6, iclass 6, count 2 2006.253.07:35:02.41#ibcon#end of sib2, iclass 6, count 2 2006.253.07:35:02.41#ibcon#*mode == 0, iclass 6, count 2 2006.253.07:35:02.41#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.253.07:35:02.41#ibcon#[27=AT06-04\r\n] 2006.253.07:35:02.41#ibcon#*before write, iclass 6, count 2 2006.253.07:35:02.41#ibcon#enter sib2, iclass 6, count 2 2006.253.07:35:02.41#ibcon#flushed, iclass 6, count 2 2006.253.07:35:02.41#ibcon#about to write, iclass 6, count 2 2006.253.07:35:02.41#ibcon#wrote, iclass 6, count 2 2006.253.07:35:02.41#ibcon#about to read 3, iclass 6, count 2 2006.253.07:35:02.44#ibcon#read 3, iclass 6, count 2 2006.253.07:35:02.44#ibcon#about to read 4, iclass 6, count 2 2006.253.07:35:02.44#ibcon#read 4, iclass 6, count 2 2006.253.07:35:02.44#ibcon#about to read 5, iclass 6, count 2 2006.253.07:35:02.44#ibcon#read 5, iclass 6, count 2 2006.253.07:35:02.44#ibcon#about to read 6, iclass 6, count 2 2006.253.07:35:02.44#ibcon#read 6, iclass 6, count 2 2006.253.07:35:02.44#ibcon#end of sib2, iclass 6, count 2 2006.253.07:35:02.44#ibcon#*after write, iclass 6, count 2 2006.253.07:35:02.44#ibcon#*before return 0, iclass 6, count 2 2006.253.07:35:02.44#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.253.07:35:02.44#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.253.07:35:02.44#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.253.07:35:02.44#ibcon#ireg 7 cls_cnt 0 2006.253.07:35:02.44#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.253.07:35:02.56#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.253.07:35:02.56#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.253.07:35:02.56#ibcon#enter wrdev, iclass 6, count 0 2006.253.07:35:02.56#ibcon#first serial, iclass 6, count 0 2006.253.07:35:02.56#ibcon#enter sib2, iclass 6, count 0 2006.253.07:35:02.56#ibcon#flushed, iclass 6, count 0 2006.253.07:35:02.56#ibcon#about to write, iclass 6, count 0 2006.253.07:35:02.56#ibcon#wrote, iclass 6, count 0 2006.253.07:35:02.56#ibcon#about to read 3, iclass 6, count 0 2006.253.07:35:02.58#ibcon#read 3, iclass 6, count 0 2006.253.07:35:02.58#ibcon#about to read 4, iclass 6, count 0 2006.253.07:35:02.58#ibcon#read 4, iclass 6, count 0 2006.253.07:35:02.58#ibcon#about to read 5, iclass 6, count 0 2006.253.07:35:02.58#ibcon#read 5, iclass 6, count 0 2006.253.07:35:02.58#ibcon#about to read 6, iclass 6, count 0 2006.253.07:35:02.58#ibcon#read 6, iclass 6, count 0 2006.253.07:35:02.58#ibcon#end of sib2, iclass 6, count 0 2006.253.07:35:02.58#ibcon#*mode == 0, iclass 6, count 0 2006.253.07:35:02.58#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.253.07:35:02.58#ibcon#[27=USB\r\n] 2006.253.07:35:02.58#ibcon#*before write, iclass 6, count 0 2006.253.07:35:02.58#ibcon#enter sib2, iclass 6, count 0 2006.253.07:35:02.58#ibcon#flushed, iclass 6, count 0 2006.253.07:35:02.58#ibcon#about to write, iclass 6, count 0 2006.253.07:35:02.58#ibcon#wrote, iclass 6, count 0 2006.253.07:35:02.58#ibcon#about to read 3, iclass 6, count 0 2006.253.07:35:02.61#ibcon#read 3, iclass 6, count 0 2006.253.07:35:02.61#ibcon#about to read 4, iclass 6, count 0 2006.253.07:35:02.61#ibcon#read 4, iclass 6, count 0 2006.253.07:35:02.61#ibcon#about to read 5, iclass 6, count 0 2006.253.07:35:02.61#ibcon#read 5, iclass 6, count 0 2006.253.07:35:02.61#ibcon#about to read 6, iclass 6, count 0 2006.253.07:35:02.61#ibcon#read 6, iclass 6, count 0 2006.253.07:35:02.61#ibcon#end of sib2, iclass 6, count 0 2006.253.07:35:02.61#ibcon#*after write, iclass 6, count 0 2006.253.07:35:02.61#ibcon#*before return 0, iclass 6, count 0 2006.253.07:35:02.61#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.253.07:35:02.61#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.253.07:35:02.61#ibcon#about to clear, iclass 6 cls_cnt 0 2006.253.07:35:02.61#ibcon#cleared, iclass 6 cls_cnt 0 2006.253.07:35:02.61$vc4f8/vabw=wide 2006.253.07:35:02.61#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.253.07:35:02.61#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.253.07:35:02.61#ibcon#ireg 8 cls_cnt 0 2006.253.07:35:02.61#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.253.07:35:02.61#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.253.07:35:02.61#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.253.07:35:02.61#ibcon#enter wrdev, iclass 10, count 0 2006.253.07:35:02.61#ibcon#first serial, iclass 10, count 0 2006.253.07:35:02.61#ibcon#enter sib2, iclass 10, count 0 2006.253.07:35:02.61#ibcon#flushed, iclass 10, count 0 2006.253.07:35:02.61#ibcon#about to write, iclass 10, count 0 2006.253.07:35:02.61#ibcon#wrote, iclass 10, count 0 2006.253.07:35:02.61#ibcon#about to read 3, iclass 10, count 0 2006.253.07:35:02.63#ibcon#read 3, iclass 10, count 0 2006.253.07:35:02.63#ibcon#about to read 4, iclass 10, count 0 2006.253.07:35:02.63#ibcon#read 4, iclass 10, count 0 2006.253.07:35:02.63#ibcon#about to read 5, iclass 10, count 0 2006.253.07:35:02.63#ibcon#read 5, iclass 10, count 0 2006.253.07:35:02.63#ibcon#about to read 6, iclass 10, count 0 2006.253.07:35:02.63#ibcon#read 6, iclass 10, count 0 2006.253.07:35:02.63#ibcon#end of sib2, iclass 10, count 0 2006.253.07:35:02.63#ibcon#*mode == 0, iclass 10, count 0 2006.253.07:35:02.63#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.253.07:35:02.63#ibcon#[25=BW32\r\n] 2006.253.07:35:02.63#ibcon#*before write, iclass 10, count 0 2006.253.07:35:02.63#ibcon#enter sib2, iclass 10, count 0 2006.253.07:35:02.63#ibcon#flushed, iclass 10, count 0 2006.253.07:35:02.63#ibcon#about to write, iclass 10, count 0 2006.253.07:35:02.63#ibcon#wrote, iclass 10, count 0 2006.253.07:35:02.63#ibcon#about to read 3, iclass 10, count 0 2006.253.07:35:02.67#ibcon#read 3, iclass 10, count 0 2006.253.07:35:02.67#ibcon#about to read 4, iclass 10, count 0 2006.253.07:35:02.67#ibcon#read 4, iclass 10, count 0 2006.253.07:35:02.67#ibcon#about to read 5, iclass 10, count 0 2006.253.07:35:02.67#ibcon#read 5, iclass 10, count 0 2006.253.07:35:02.67#ibcon#about to read 6, iclass 10, count 0 2006.253.07:35:02.67#ibcon#read 6, iclass 10, count 0 2006.253.07:35:02.67#ibcon#end of sib2, iclass 10, count 0 2006.253.07:35:02.67#ibcon#*after write, iclass 10, count 0 2006.253.07:35:02.67#ibcon#*before return 0, iclass 10, count 0 2006.253.07:35:02.67#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.253.07:35:02.67#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.253.07:35:02.67#ibcon#about to clear, iclass 10 cls_cnt 0 2006.253.07:35:02.67#ibcon#cleared, iclass 10 cls_cnt 0 2006.253.07:35:02.67$vc4f8/vbbw=wide 2006.253.07:35:02.67#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.253.07:35:02.67#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.253.07:35:02.67#ibcon#ireg 8 cls_cnt 0 2006.253.07:35:02.67#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.253.07:35:02.73#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.253.07:35:02.73#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.253.07:35:02.73#ibcon#enter wrdev, iclass 12, count 0 2006.253.07:35:02.73#ibcon#first serial, iclass 12, count 0 2006.253.07:35:02.73#ibcon#enter sib2, iclass 12, count 0 2006.253.07:35:02.73#ibcon#flushed, iclass 12, count 0 2006.253.07:35:02.73#ibcon#about to write, iclass 12, count 0 2006.253.07:35:02.73#ibcon#wrote, iclass 12, count 0 2006.253.07:35:02.73#ibcon#about to read 3, iclass 12, count 0 2006.253.07:35:02.75#ibcon#read 3, iclass 12, count 0 2006.253.07:35:02.75#ibcon#about to read 4, iclass 12, count 0 2006.253.07:35:02.75#ibcon#read 4, iclass 12, count 0 2006.253.07:35:02.75#ibcon#about to read 5, iclass 12, count 0 2006.253.07:35:02.75#ibcon#read 5, iclass 12, count 0 2006.253.07:35:02.75#ibcon#about to read 6, iclass 12, count 0 2006.253.07:35:02.75#ibcon#read 6, iclass 12, count 0 2006.253.07:35:02.75#ibcon#end of sib2, iclass 12, count 0 2006.253.07:35:02.75#ibcon#*mode == 0, iclass 12, count 0 2006.253.07:35:02.75#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.253.07:35:02.75#ibcon#[27=BW32\r\n] 2006.253.07:35:02.75#ibcon#*before write, iclass 12, count 0 2006.253.07:35:02.75#ibcon#enter sib2, iclass 12, count 0 2006.253.07:35:02.75#ibcon#flushed, iclass 12, count 0 2006.253.07:35:02.75#ibcon#about to write, iclass 12, count 0 2006.253.07:35:02.75#ibcon#wrote, iclass 12, count 0 2006.253.07:35:02.75#ibcon#about to read 3, iclass 12, count 0 2006.253.07:35:02.78#ibcon#read 3, iclass 12, count 0 2006.253.07:35:02.78#ibcon#about to read 4, iclass 12, count 0 2006.253.07:35:02.78#ibcon#read 4, iclass 12, count 0 2006.253.07:35:02.78#ibcon#about to read 5, iclass 12, count 0 2006.253.07:35:02.78#ibcon#read 5, iclass 12, count 0 2006.253.07:35:02.78#ibcon#about to read 6, iclass 12, count 0 2006.253.07:35:02.78#ibcon#read 6, iclass 12, count 0 2006.253.07:35:02.78#ibcon#end of sib2, iclass 12, count 0 2006.253.07:35:02.78#ibcon#*after write, iclass 12, count 0 2006.253.07:35:02.78#ibcon#*before return 0, iclass 12, count 0 2006.253.07:35:02.78#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.253.07:35:02.78#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.253.07:35:02.78#ibcon#about to clear, iclass 12 cls_cnt 0 2006.253.07:35:02.78#ibcon#cleared, iclass 12 cls_cnt 0 2006.253.07:35:02.78$4f8m12a/ifd4f 2006.253.07:35:02.78$ifd4f/lo= 2006.253.07:35:02.78$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.253.07:35:02.78$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.253.07:35:02.78$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.253.07:35:02.78$ifd4f/patch= 2006.253.07:35:02.78$ifd4f/patch=lo1,a1,a2,a3,a4 2006.253.07:35:02.78$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.253.07:35:02.78$ifd4f/patch=lo3,a5,a6,a7,a8 2006.253.07:35:02.78$4f8m12a/"form=m,16.000,1:2 2006.253.07:35:02.78$4f8m12a/"tpicd 2006.253.07:35:02.78$4f8m12a/echo=off 2006.253.07:35:02.78$4f8m12a/xlog=off 2006.253.07:35:02.78:!2006.253.07:35:50 2006.253.07:35:31.14#trakl#Source acquired 2006.253.07:35:33.14#flagr#flagr/antenna,acquired 2006.253.07:35:50.00:preob 2006.253.07:35:50.14/onsource/TRACKING 2006.253.07:35:50.14:!2006.253.07:36:00 2006.253.07:36:00.00:data_valid=on 2006.253.07:36:00.00:midob 2006.253.07:36:00.14/onsource/TRACKING 2006.253.07:36:00.14/wx/31.54,1006.3,72 2006.253.07:36:00.20/cable/+6.3696E-03 2006.253.07:36:01.29/va/01,08,usb,yes,32,33 2006.253.07:36:01.29/va/02,07,usb,yes,31,33 2006.253.07:36:01.29/va/03,06,usb,yes,33,34 2006.253.07:36:01.29/va/04,07,usb,yes,32,35 2006.253.07:36:01.29/va/05,07,usb,yes,34,35 2006.253.07:36:01.29/va/06,07,usb,yes,29,29 2006.253.07:36:01.29/va/07,07,usb,yes,29,29 2006.253.07:36:01.29/va/08,07,usb,yes,32,31 2006.253.07:36:01.52/valo/01,532.99,yes,locked 2006.253.07:36:01.52/valo/02,572.99,yes,locked 2006.253.07:36:01.52/valo/03,672.99,yes,locked 2006.253.07:36:01.52/valo/04,832.99,yes,locked 2006.253.07:36:01.52/valo/05,652.99,yes,locked 2006.253.07:36:01.52/valo/06,772.99,yes,locked 2006.253.07:36:01.52/valo/07,832.99,yes,locked 2006.253.07:36:01.52/valo/08,852.99,yes,locked 2006.253.07:36:02.61/vb/01,04,usb,yes,30,29 2006.253.07:36:02.61/vb/02,05,usb,yes,28,29 2006.253.07:36:02.61/vb/03,04,usb,yes,28,32 2006.253.07:36:02.61/vb/04,04,usb,yes,29,29 2006.253.07:36:02.61/vb/05,04,usb,yes,28,32 2006.253.07:36:02.61/vb/06,04,usb,yes,29,32 2006.253.07:36:02.61/vb/07,04,usb,yes,31,31 2006.253.07:36:02.61/vb/08,04,usb,yes,28,32 2006.253.07:36:02.84/vblo/01,632.99,yes,locked 2006.253.07:36:02.84/vblo/02,640.99,yes,locked 2006.253.07:36:02.84/vblo/03,656.99,yes,locked 2006.253.07:36:02.84/vblo/04,712.99,yes,locked 2006.253.07:36:02.84/vblo/05,744.99,yes,locked 2006.253.07:36:02.84/vblo/06,752.99,yes,locked 2006.253.07:36:02.84/vblo/07,734.99,yes,locked 2006.253.07:36:02.84/vblo/08,744.99,yes,locked 2006.253.07:36:02.99/vabw/8 2006.253.07:36:03.14/vbbw/8 2006.253.07:36:03.23/xfe/off,on,14.5 2006.253.07:36:03.61/ifatt/23,28,28,28 2006.253.07:36:04.08/fmout-gps/S +4.75E-07 2006.253.07:36:04.12:!2006.253.07:37:00 2006.253.07:37:00.00:data_valid=off 2006.253.07:37:00.00:postob 2006.253.07:37:00.11/cable/+6.3701E-03 2006.253.07:37:00.11/wx/31.53,1006.3,73 2006.253.07:37:01.08/fmout-gps/S +4.75E-07 2006.253.07:37:01.08:scan_name=253-0737,k06253,60 2006.253.07:37:01.08:source=0804+499,080839.67,495036.5,2000.0,ccw 2006.253.07:37:01.16#flagr#flagr/antenna,new-source 2006.253.07:37:02.14:checkk5 2006.253.07:37:02.52/chk_autoobs//k5ts1/ autoobs is running! 2006.253.07:37:02.89/chk_autoobs//k5ts2/ autoobs is running! 2006.253.07:37:03.27/chk_autoobs//k5ts3/ autoobs is running! 2006.253.07:37:03.64/chk_autoobs//k5ts4/ autoobs is running! 2006.253.07:37:04.01/chk_obsdata//k5ts1/T2530736??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.07:37:04.38/chk_obsdata//k5ts2/T2530736??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.07:37:04.76/chk_obsdata//k5ts3/T2530736??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.07:37:05.13/chk_obsdata//k5ts4/T2530736??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.07:37:05.84/k5log//k5ts1_log_newline 2006.253.07:37:06.53/k5log//k5ts2_log_newline 2006.253.07:37:07.22/k5log//k5ts3_log_newline 2006.253.07:37:07.90/k5log//k5ts4_log_newline 2006.253.07:37:07.93/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.253.07:37:07.93:4f8m12a=1 2006.253.07:37:07.93$4f8m12a/echo=on 2006.253.07:37:07.93$4f8m12a/pcalon 2006.253.07:37:07.93$pcalon/"no phase cal control is implemented here 2006.253.07:37:07.93$4f8m12a/"tpicd=stop 2006.253.07:37:07.93$4f8m12a/vc4f8 2006.253.07:37:07.93$vc4f8/valo=1,532.99 2006.253.07:37:07.93#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.253.07:37:07.93#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.253.07:37:07.93#ibcon#ireg 17 cls_cnt 0 2006.253.07:37:07.93#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.253.07:37:07.93#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.253.07:37:07.93#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.253.07:37:07.93#ibcon#enter wrdev, iclass 31, count 0 2006.253.07:37:07.93#ibcon#first serial, iclass 31, count 0 2006.253.07:37:07.93#ibcon#enter sib2, iclass 31, count 0 2006.253.07:37:07.93#ibcon#flushed, iclass 31, count 0 2006.253.07:37:07.93#ibcon#about to write, iclass 31, count 0 2006.253.07:37:07.93#ibcon#wrote, iclass 31, count 0 2006.253.07:37:07.93#ibcon#about to read 3, iclass 31, count 0 2006.253.07:37:07.97#ibcon#read 3, iclass 31, count 0 2006.253.07:37:07.97#ibcon#about to read 4, iclass 31, count 0 2006.253.07:37:07.97#ibcon#read 4, iclass 31, count 0 2006.253.07:37:07.97#ibcon#about to read 5, iclass 31, count 0 2006.253.07:37:07.97#ibcon#read 5, iclass 31, count 0 2006.253.07:37:07.97#ibcon#about to read 6, iclass 31, count 0 2006.253.07:37:07.97#ibcon#read 6, iclass 31, count 0 2006.253.07:37:07.97#ibcon#end of sib2, iclass 31, count 0 2006.253.07:37:07.97#ibcon#*mode == 0, iclass 31, count 0 2006.253.07:37:07.97#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.253.07:37:07.97#ibcon#[26=FRQ=01,532.99\r\n] 2006.253.07:37:07.97#ibcon#*before write, iclass 31, count 0 2006.253.07:37:07.97#ibcon#enter sib2, iclass 31, count 0 2006.253.07:37:07.97#ibcon#flushed, iclass 31, count 0 2006.253.07:37:07.97#ibcon#about to write, iclass 31, count 0 2006.253.07:37:07.97#ibcon#wrote, iclass 31, count 0 2006.253.07:37:07.97#ibcon#about to read 3, iclass 31, count 0 2006.253.07:37:08.02#ibcon#read 3, iclass 31, count 0 2006.253.07:37:08.02#ibcon#about to read 4, iclass 31, count 0 2006.253.07:37:08.02#ibcon#read 4, iclass 31, count 0 2006.253.07:37:08.02#ibcon#about to read 5, iclass 31, count 0 2006.253.07:37:08.02#ibcon#read 5, iclass 31, count 0 2006.253.07:37:08.02#ibcon#about to read 6, iclass 31, count 0 2006.253.07:37:08.02#ibcon#read 6, iclass 31, count 0 2006.253.07:37:08.02#ibcon#end of sib2, iclass 31, count 0 2006.253.07:37:08.02#ibcon#*after write, iclass 31, count 0 2006.253.07:37:08.02#ibcon#*before return 0, iclass 31, count 0 2006.253.07:37:08.02#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.253.07:37:08.02#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.253.07:37:08.02#ibcon#about to clear, iclass 31 cls_cnt 0 2006.253.07:37:08.02#ibcon#cleared, iclass 31 cls_cnt 0 2006.253.07:37:08.02$vc4f8/va=1,8 2006.253.07:37:08.02#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.253.07:37:08.02#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.253.07:37:08.02#ibcon#ireg 11 cls_cnt 2 2006.253.07:37:08.02#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.253.07:37:08.02#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.253.07:37:08.02#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.253.07:37:08.02#ibcon#enter wrdev, iclass 33, count 2 2006.253.07:37:08.02#ibcon#first serial, iclass 33, count 2 2006.253.07:37:08.02#ibcon#enter sib2, iclass 33, count 2 2006.253.07:37:08.02#ibcon#flushed, iclass 33, count 2 2006.253.07:37:08.02#ibcon#about to write, iclass 33, count 2 2006.253.07:37:08.02#ibcon#wrote, iclass 33, count 2 2006.253.07:37:08.02#ibcon#about to read 3, iclass 33, count 2 2006.253.07:37:08.04#ibcon#read 3, iclass 33, count 2 2006.253.07:37:08.04#ibcon#about to read 4, iclass 33, count 2 2006.253.07:37:08.04#ibcon#read 4, iclass 33, count 2 2006.253.07:37:08.04#ibcon#about to read 5, iclass 33, count 2 2006.253.07:37:08.04#ibcon#read 5, iclass 33, count 2 2006.253.07:37:08.04#ibcon#about to read 6, iclass 33, count 2 2006.253.07:37:08.04#ibcon#read 6, iclass 33, count 2 2006.253.07:37:08.04#ibcon#end of sib2, iclass 33, count 2 2006.253.07:37:08.04#ibcon#*mode == 0, iclass 33, count 2 2006.253.07:37:08.04#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.253.07:37:08.04#ibcon#[25=AT01-08\r\n] 2006.253.07:37:08.04#ibcon#*before write, iclass 33, count 2 2006.253.07:37:08.04#ibcon#enter sib2, iclass 33, count 2 2006.253.07:37:08.04#ibcon#flushed, iclass 33, count 2 2006.253.07:37:08.04#ibcon#about to write, iclass 33, count 2 2006.253.07:37:08.04#ibcon#wrote, iclass 33, count 2 2006.253.07:37:08.04#ibcon#about to read 3, iclass 33, count 2 2006.253.07:37:08.07#ibcon#read 3, iclass 33, count 2 2006.253.07:37:08.07#ibcon#about to read 4, iclass 33, count 2 2006.253.07:37:08.07#ibcon#read 4, iclass 33, count 2 2006.253.07:37:08.07#ibcon#about to read 5, iclass 33, count 2 2006.253.07:37:08.07#ibcon#read 5, iclass 33, count 2 2006.253.07:37:08.07#ibcon#about to read 6, iclass 33, count 2 2006.253.07:37:08.07#ibcon#read 6, iclass 33, count 2 2006.253.07:37:08.07#ibcon#end of sib2, iclass 33, count 2 2006.253.07:37:08.07#ibcon#*after write, iclass 33, count 2 2006.253.07:37:08.07#ibcon#*before return 0, iclass 33, count 2 2006.253.07:37:08.07#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.253.07:37:08.07#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.253.07:37:08.07#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.253.07:37:08.07#ibcon#ireg 7 cls_cnt 0 2006.253.07:37:08.07#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.253.07:37:08.19#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.253.07:37:08.19#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.253.07:37:08.19#ibcon#enter wrdev, iclass 33, count 0 2006.253.07:37:08.19#ibcon#first serial, iclass 33, count 0 2006.253.07:37:08.19#ibcon#enter sib2, iclass 33, count 0 2006.253.07:37:08.19#ibcon#flushed, iclass 33, count 0 2006.253.07:37:08.19#ibcon#about to write, iclass 33, count 0 2006.253.07:37:08.19#ibcon#wrote, iclass 33, count 0 2006.253.07:37:08.19#ibcon#about to read 3, iclass 33, count 0 2006.253.07:37:08.21#ibcon#read 3, iclass 33, count 0 2006.253.07:37:08.21#ibcon#about to read 4, iclass 33, count 0 2006.253.07:37:08.21#ibcon#read 4, iclass 33, count 0 2006.253.07:37:08.21#ibcon#about to read 5, iclass 33, count 0 2006.253.07:37:08.21#ibcon#read 5, iclass 33, count 0 2006.253.07:37:08.21#ibcon#about to read 6, iclass 33, count 0 2006.253.07:37:08.21#ibcon#read 6, iclass 33, count 0 2006.253.07:37:08.21#ibcon#end of sib2, iclass 33, count 0 2006.253.07:37:08.21#ibcon#*mode == 0, iclass 33, count 0 2006.253.07:37:08.21#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.253.07:37:08.21#ibcon#[25=USB\r\n] 2006.253.07:37:08.21#ibcon#*before write, iclass 33, count 0 2006.253.07:37:08.21#ibcon#enter sib2, iclass 33, count 0 2006.253.07:37:08.21#ibcon#flushed, iclass 33, count 0 2006.253.07:37:08.21#ibcon#about to write, iclass 33, count 0 2006.253.07:37:08.21#ibcon#wrote, iclass 33, count 0 2006.253.07:37:08.21#ibcon#about to read 3, iclass 33, count 0 2006.253.07:37:08.24#ibcon#read 3, iclass 33, count 0 2006.253.07:37:08.24#ibcon#about to read 4, iclass 33, count 0 2006.253.07:37:08.24#ibcon#read 4, iclass 33, count 0 2006.253.07:37:08.24#ibcon#about to read 5, iclass 33, count 0 2006.253.07:37:08.24#ibcon#read 5, iclass 33, count 0 2006.253.07:37:08.24#ibcon#about to read 6, iclass 33, count 0 2006.253.07:37:08.24#ibcon#read 6, iclass 33, count 0 2006.253.07:37:08.24#ibcon#end of sib2, iclass 33, count 0 2006.253.07:37:08.24#ibcon#*after write, iclass 33, count 0 2006.253.07:37:08.24#ibcon#*before return 0, iclass 33, count 0 2006.253.07:37:08.24#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.253.07:37:08.24#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.253.07:37:08.24#ibcon#about to clear, iclass 33 cls_cnt 0 2006.253.07:37:08.24#ibcon#cleared, iclass 33 cls_cnt 0 2006.253.07:37:08.24$vc4f8/valo=2,572.99 2006.253.07:37:08.24#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.253.07:37:08.24#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.253.07:37:08.24#ibcon#ireg 17 cls_cnt 0 2006.253.07:37:08.24#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.253.07:37:08.24#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.253.07:37:08.24#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.253.07:37:08.24#ibcon#enter wrdev, iclass 35, count 0 2006.253.07:37:08.24#ibcon#first serial, iclass 35, count 0 2006.253.07:37:08.24#ibcon#enter sib2, iclass 35, count 0 2006.253.07:37:08.24#ibcon#flushed, iclass 35, count 0 2006.253.07:37:08.24#ibcon#about to write, iclass 35, count 0 2006.253.07:37:08.24#ibcon#wrote, iclass 35, count 0 2006.253.07:37:08.24#ibcon#about to read 3, iclass 35, count 0 2006.253.07:37:08.26#ibcon#read 3, iclass 35, count 0 2006.253.07:37:08.26#ibcon#about to read 4, iclass 35, count 0 2006.253.07:37:08.26#ibcon#read 4, iclass 35, count 0 2006.253.07:37:08.26#ibcon#about to read 5, iclass 35, count 0 2006.253.07:37:08.26#ibcon#read 5, iclass 35, count 0 2006.253.07:37:08.26#ibcon#about to read 6, iclass 35, count 0 2006.253.07:37:08.26#ibcon#read 6, iclass 35, count 0 2006.253.07:37:08.26#ibcon#end of sib2, iclass 35, count 0 2006.253.07:37:08.26#ibcon#*mode == 0, iclass 35, count 0 2006.253.07:37:08.26#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.253.07:37:08.26#ibcon#[26=FRQ=02,572.99\r\n] 2006.253.07:37:08.26#ibcon#*before write, iclass 35, count 0 2006.253.07:37:08.26#ibcon#enter sib2, iclass 35, count 0 2006.253.07:37:08.26#ibcon#flushed, iclass 35, count 0 2006.253.07:37:08.26#ibcon#about to write, iclass 35, count 0 2006.253.07:37:08.26#ibcon#wrote, iclass 35, count 0 2006.253.07:37:08.26#ibcon#about to read 3, iclass 35, count 0 2006.253.07:37:08.31#ibcon#read 3, iclass 35, count 0 2006.253.07:37:08.31#ibcon#about to read 4, iclass 35, count 0 2006.253.07:37:08.31#ibcon#read 4, iclass 35, count 0 2006.253.07:37:08.31#ibcon#about to read 5, iclass 35, count 0 2006.253.07:37:08.31#ibcon#read 5, iclass 35, count 0 2006.253.07:37:08.31#ibcon#about to read 6, iclass 35, count 0 2006.253.07:37:08.31#ibcon#read 6, iclass 35, count 0 2006.253.07:37:08.31#ibcon#end of sib2, iclass 35, count 0 2006.253.07:37:08.31#ibcon#*after write, iclass 35, count 0 2006.253.07:37:08.31#ibcon#*before return 0, iclass 35, count 0 2006.253.07:37:08.31#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.253.07:37:08.31#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.253.07:37:08.31#ibcon#about to clear, iclass 35 cls_cnt 0 2006.253.07:37:08.31#ibcon#cleared, iclass 35 cls_cnt 0 2006.253.07:37:08.31$vc4f8/va=2,7 2006.253.07:37:08.31#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.253.07:37:08.31#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.253.07:37:08.31#ibcon#ireg 11 cls_cnt 2 2006.253.07:37:08.31#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.253.07:37:08.36#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.253.07:37:08.36#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.253.07:37:08.36#ibcon#enter wrdev, iclass 37, count 2 2006.253.07:37:08.36#ibcon#first serial, iclass 37, count 2 2006.253.07:37:08.36#ibcon#enter sib2, iclass 37, count 2 2006.253.07:37:08.36#ibcon#flushed, iclass 37, count 2 2006.253.07:37:08.36#ibcon#about to write, iclass 37, count 2 2006.253.07:37:08.36#ibcon#wrote, iclass 37, count 2 2006.253.07:37:08.36#ibcon#about to read 3, iclass 37, count 2 2006.253.07:37:08.38#ibcon#read 3, iclass 37, count 2 2006.253.07:37:08.38#ibcon#about to read 4, iclass 37, count 2 2006.253.07:37:08.38#ibcon#read 4, iclass 37, count 2 2006.253.07:37:08.38#ibcon#about to read 5, iclass 37, count 2 2006.253.07:37:08.38#ibcon#read 5, iclass 37, count 2 2006.253.07:37:08.38#ibcon#about to read 6, iclass 37, count 2 2006.253.07:37:08.38#ibcon#read 6, iclass 37, count 2 2006.253.07:37:08.38#ibcon#end of sib2, iclass 37, count 2 2006.253.07:37:08.38#ibcon#*mode == 0, iclass 37, count 2 2006.253.07:37:08.38#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.253.07:37:08.38#ibcon#[25=AT02-07\r\n] 2006.253.07:37:08.38#ibcon#*before write, iclass 37, count 2 2006.253.07:37:08.38#ibcon#enter sib2, iclass 37, count 2 2006.253.07:37:08.38#ibcon#flushed, iclass 37, count 2 2006.253.07:37:08.38#ibcon#about to write, iclass 37, count 2 2006.253.07:37:08.38#ibcon#wrote, iclass 37, count 2 2006.253.07:37:08.38#ibcon#about to read 3, iclass 37, count 2 2006.253.07:37:08.41#ibcon#read 3, iclass 37, count 2 2006.253.07:37:08.41#ibcon#about to read 4, iclass 37, count 2 2006.253.07:37:08.41#ibcon#read 4, iclass 37, count 2 2006.253.07:37:08.41#ibcon#about to read 5, iclass 37, count 2 2006.253.07:37:08.41#ibcon#read 5, iclass 37, count 2 2006.253.07:37:08.41#ibcon#about to read 6, iclass 37, count 2 2006.253.07:37:08.41#ibcon#read 6, iclass 37, count 2 2006.253.07:37:08.41#ibcon#end of sib2, iclass 37, count 2 2006.253.07:37:08.41#ibcon#*after write, iclass 37, count 2 2006.253.07:37:08.41#ibcon#*before return 0, iclass 37, count 2 2006.253.07:37:08.41#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.253.07:37:08.41#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.253.07:37:08.41#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.253.07:37:08.41#ibcon#ireg 7 cls_cnt 0 2006.253.07:37:08.41#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.253.07:37:08.53#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.253.07:37:08.53#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.253.07:37:08.53#ibcon#enter wrdev, iclass 37, count 0 2006.253.07:37:08.53#ibcon#first serial, iclass 37, count 0 2006.253.07:37:08.53#ibcon#enter sib2, iclass 37, count 0 2006.253.07:37:08.53#ibcon#flushed, iclass 37, count 0 2006.253.07:37:08.53#ibcon#about to write, iclass 37, count 0 2006.253.07:37:08.53#ibcon#wrote, iclass 37, count 0 2006.253.07:37:08.53#ibcon#about to read 3, iclass 37, count 0 2006.253.07:37:08.55#ibcon#read 3, iclass 37, count 0 2006.253.07:37:08.55#ibcon#about to read 4, iclass 37, count 0 2006.253.07:37:08.55#ibcon#read 4, iclass 37, count 0 2006.253.07:37:08.55#ibcon#about to read 5, iclass 37, count 0 2006.253.07:37:08.55#ibcon#read 5, iclass 37, count 0 2006.253.07:37:08.55#ibcon#about to read 6, iclass 37, count 0 2006.253.07:37:08.55#ibcon#read 6, iclass 37, count 0 2006.253.07:37:08.55#ibcon#end of sib2, iclass 37, count 0 2006.253.07:37:08.55#ibcon#*mode == 0, iclass 37, count 0 2006.253.07:37:08.55#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.253.07:37:08.55#ibcon#[25=USB\r\n] 2006.253.07:37:08.55#ibcon#*before write, iclass 37, count 0 2006.253.07:37:08.55#ibcon#enter sib2, iclass 37, count 0 2006.253.07:37:08.55#ibcon#flushed, iclass 37, count 0 2006.253.07:37:08.55#ibcon#about to write, iclass 37, count 0 2006.253.07:37:08.55#ibcon#wrote, iclass 37, count 0 2006.253.07:37:08.55#ibcon#about to read 3, iclass 37, count 0 2006.253.07:37:08.58#ibcon#read 3, iclass 37, count 0 2006.253.07:37:08.58#ibcon#about to read 4, iclass 37, count 0 2006.253.07:37:08.58#ibcon#read 4, iclass 37, count 0 2006.253.07:37:08.58#ibcon#about to read 5, iclass 37, count 0 2006.253.07:37:08.58#ibcon#read 5, iclass 37, count 0 2006.253.07:37:08.58#ibcon#about to read 6, iclass 37, count 0 2006.253.07:37:08.58#ibcon#read 6, iclass 37, count 0 2006.253.07:37:08.58#ibcon#end of sib2, iclass 37, count 0 2006.253.07:37:08.58#ibcon#*after write, iclass 37, count 0 2006.253.07:37:08.58#ibcon#*before return 0, iclass 37, count 0 2006.253.07:37:08.58#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.253.07:37:08.58#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.253.07:37:08.58#ibcon#about to clear, iclass 37 cls_cnt 0 2006.253.07:37:08.58#ibcon#cleared, iclass 37 cls_cnt 0 2006.253.07:37:08.58$vc4f8/valo=3,672.99 2006.253.07:37:08.58#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.253.07:37:08.58#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.253.07:37:08.58#ibcon#ireg 17 cls_cnt 0 2006.253.07:37:08.58#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.253.07:37:08.58#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.253.07:37:08.58#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.253.07:37:08.58#ibcon#enter wrdev, iclass 39, count 0 2006.253.07:37:08.58#ibcon#first serial, iclass 39, count 0 2006.253.07:37:08.58#ibcon#enter sib2, iclass 39, count 0 2006.253.07:37:08.58#ibcon#flushed, iclass 39, count 0 2006.253.07:37:08.58#ibcon#about to write, iclass 39, count 0 2006.253.07:37:08.58#ibcon#wrote, iclass 39, count 0 2006.253.07:37:08.58#ibcon#about to read 3, iclass 39, count 0 2006.253.07:37:08.60#ibcon#read 3, iclass 39, count 0 2006.253.07:37:08.60#ibcon#about to read 4, iclass 39, count 0 2006.253.07:37:08.60#ibcon#read 4, iclass 39, count 0 2006.253.07:37:08.60#ibcon#about to read 5, iclass 39, count 0 2006.253.07:37:08.60#ibcon#read 5, iclass 39, count 0 2006.253.07:37:08.60#ibcon#about to read 6, iclass 39, count 0 2006.253.07:37:08.60#ibcon#read 6, iclass 39, count 0 2006.253.07:37:08.60#ibcon#end of sib2, iclass 39, count 0 2006.253.07:37:08.60#ibcon#*mode == 0, iclass 39, count 0 2006.253.07:37:08.60#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.253.07:37:08.60#ibcon#[26=FRQ=03,672.99\r\n] 2006.253.07:37:08.60#ibcon#*before write, iclass 39, count 0 2006.253.07:37:08.60#ibcon#enter sib2, iclass 39, count 0 2006.253.07:37:08.60#ibcon#flushed, iclass 39, count 0 2006.253.07:37:08.60#ibcon#about to write, iclass 39, count 0 2006.253.07:37:08.60#ibcon#wrote, iclass 39, count 0 2006.253.07:37:08.60#ibcon#about to read 3, iclass 39, count 0 2006.253.07:37:08.65#ibcon#read 3, iclass 39, count 0 2006.253.07:37:08.65#ibcon#about to read 4, iclass 39, count 0 2006.253.07:37:08.65#ibcon#read 4, iclass 39, count 0 2006.253.07:37:08.65#ibcon#about to read 5, iclass 39, count 0 2006.253.07:37:08.65#ibcon#read 5, iclass 39, count 0 2006.253.07:37:08.65#ibcon#about to read 6, iclass 39, count 0 2006.253.07:37:08.65#ibcon#read 6, iclass 39, count 0 2006.253.07:37:08.65#ibcon#end of sib2, iclass 39, count 0 2006.253.07:37:08.65#ibcon#*after write, iclass 39, count 0 2006.253.07:37:08.65#ibcon#*before return 0, iclass 39, count 0 2006.253.07:37:08.65#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.253.07:37:08.65#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.253.07:37:08.65#ibcon#about to clear, iclass 39 cls_cnt 0 2006.253.07:37:08.65#ibcon#cleared, iclass 39 cls_cnt 0 2006.253.07:37:08.65$vc4f8/va=3,6 2006.253.07:37:08.65#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.253.07:37:08.65#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.253.07:37:08.65#ibcon#ireg 11 cls_cnt 2 2006.253.07:37:08.65#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.253.07:37:08.70#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.253.07:37:08.70#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.253.07:37:08.70#ibcon#enter wrdev, iclass 3, count 2 2006.253.07:37:08.70#ibcon#first serial, iclass 3, count 2 2006.253.07:37:08.70#ibcon#enter sib2, iclass 3, count 2 2006.253.07:37:08.70#ibcon#flushed, iclass 3, count 2 2006.253.07:37:08.70#ibcon#about to write, iclass 3, count 2 2006.253.07:37:08.70#ibcon#wrote, iclass 3, count 2 2006.253.07:37:08.70#ibcon#about to read 3, iclass 3, count 2 2006.253.07:37:08.72#ibcon#read 3, iclass 3, count 2 2006.253.07:37:08.72#ibcon#about to read 4, iclass 3, count 2 2006.253.07:37:08.72#ibcon#read 4, iclass 3, count 2 2006.253.07:37:08.72#ibcon#about to read 5, iclass 3, count 2 2006.253.07:37:08.72#ibcon#read 5, iclass 3, count 2 2006.253.07:37:08.72#ibcon#about to read 6, iclass 3, count 2 2006.253.07:37:08.72#ibcon#read 6, iclass 3, count 2 2006.253.07:37:08.72#ibcon#end of sib2, iclass 3, count 2 2006.253.07:37:08.72#ibcon#*mode == 0, iclass 3, count 2 2006.253.07:37:08.72#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.253.07:37:08.72#ibcon#[25=AT03-06\r\n] 2006.253.07:37:08.72#ibcon#*before write, iclass 3, count 2 2006.253.07:37:08.72#ibcon#enter sib2, iclass 3, count 2 2006.253.07:37:08.72#ibcon#flushed, iclass 3, count 2 2006.253.07:37:08.72#ibcon#about to write, iclass 3, count 2 2006.253.07:37:08.72#ibcon#wrote, iclass 3, count 2 2006.253.07:37:08.72#ibcon#about to read 3, iclass 3, count 2 2006.253.07:37:08.75#ibcon#read 3, iclass 3, count 2 2006.253.07:37:08.75#ibcon#about to read 4, iclass 3, count 2 2006.253.07:37:08.75#ibcon#read 4, iclass 3, count 2 2006.253.07:37:08.75#ibcon#about to read 5, iclass 3, count 2 2006.253.07:37:08.75#ibcon#read 5, iclass 3, count 2 2006.253.07:37:08.75#ibcon#about to read 6, iclass 3, count 2 2006.253.07:37:08.75#ibcon#read 6, iclass 3, count 2 2006.253.07:37:08.75#ibcon#end of sib2, iclass 3, count 2 2006.253.07:37:08.75#ibcon#*after write, iclass 3, count 2 2006.253.07:37:08.75#ibcon#*before return 0, iclass 3, count 2 2006.253.07:37:08.75#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.253.07:37:08.75#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.253.07:37:08.75#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.253.07:37:08.75#ibcon#ireg 7 cls_cnt 0 2006.253.07:37:08.75#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.253.07:37:08.87#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.253.07:37:08.87#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.253.07:37:08.87#ibcon#enter wrdev, iclass 3, count 0 2006.253.07:37:08.87#ibcon#first serial, iclass 3, count 0 2006.253.07:37:08.87#ibcon#enter sib2, iclass 3, count 0 2006.253.07:37:08.87#ibcon#flushed, iclass 3, count 0 2006.253.07:37:08.87#ibcon#about to write, iclass 3, count 0 2006.253.07:37:08.87#ibcon#wrote, iclass 3, count 0 2006.253.07:37:08.87#ibcon#about to read 3, iclass 3, count 0 2006.253.07:37:08.89#ibcon#read 3, iclass 3, count 0 2006.253.07:37:08.89#ibcon#about to read 4, iclass 3, count 0 2006.253.07:37:08.89#ibcon#read 4, iclass 3, count 0 2006.253.07:37:08.89#ibcon#about to read 5, iclass 3, count 0 2006.253.07:37:08.89#ibcon#read 5, iclass 3, count 0 2006.253.07:37:08.89#ibcon#about to read 6, iclass 3, count 0 2006.253.07:37:08.89#ibcon#read 6, iclass 3, count 0 2006.253.07:37:08.89#ibcon#end of sib2, iclass 3, count 0 2006.253.07:37:08.89#ibcon#*mode == 0, iclass 3, count 0 2006.253.07:37:08.89#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.253.07:37:08.89#ibcon#[25=USB\r\n] 2006.253.07:37:08.89#ibcon#*before write, iclass 3, count 0 2006.253.07:37:08.89#ibcon#enter sib2, iclass 3, count 0 2006.253.07:37:08.89#ibcon#flushed, iclass 3, count 0 2006.253.07:37:08.89#ibcon#about to write, iclass 3, count 0 2006.253.07:37:08.89#ibcon#wrote, iclass 3, count 0 2006.253.07:37:08.89#ibcon#about to read 3, iclass 3, count 0 2006.253.07:37:08.92#ibcon#read 3, iclass 3, count 0 2006.253.07:37:08.92#ibcon#about to read 4, iclass 3, count 0 2006.253.07:37:08.92#ibcon#read 4, iclass 3, count 0 2006.253.07:37:08.92#ibcon#about to read 5, iclass 3, count 0 2006.253.07:37:08.92#ibcon#read 5, iclass 3, count 0 2006.253.07:37:08.92#ibcon#about to read 6, iclass 3, count 0 2006.253.07:37:08.92#ibcon#read 6, iclass 3, count 0 2006.253.07:37:08.92#ibcon#end of sib2, iclass 3, count 0 2006.253.07:37:08.92#ibcon#*after write, iclass 3, count 0 2006.253.07:37:08.92#ibcon#*before return 0, iclass 3, count 0 2006.253.07:37:08.92#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.253.07:37:08.92#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.253.07:37:08.92#ibcon#about to clear, iclass 3 cls_cnt 0 2006.253.07:37:08.92#ibcon#cleared, iclass 3 cls_cnt 0 2006.253.07:37:08.92$vc4f8/valo=4,832.99 2006.253.07:37:08.92#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.253.07:37:08.92#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.253.07:37:08.92#ibcon#ireg 17 cls_cnt 0 2006.253.07:37:08.92#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.253.07:37:08.92#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.253.07:37:08.92#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.253.07:37:08.92#ibcon#enter wrdev, iclass 5, count 0 2006.253.07:37:08.92#ibcon#first serial, iclass 5, count 0 2006.253.07:37:08.92#ibcon#enter sib2, iclass 5, count 0 2006.253.07:37:08.92#ibcon#flushed, iclass 5, count 0 2006.253.07:37:08.92#ibcon#about to write, iclass 5, count 0 2006.253.07:37:08.92#ibcon#wrote, iclass 5, count 0 2006.253.07:37:08.92#ibcon#about to read 3, iclass 5, count 0 2006.253.07:37:08.94#ibcon#read 3, iclass 5, count 0 2006.253.07:37:08.94#ibcon#about to read 4, iclass 5, count 0 2006.253.07:37:08.94#ibcon#read 4, iclass 5, count 0 2006.253.07:37:08.94#ibcon#about to read 5, iclass 5, count 0 2006.253.07:37:08.94#ibcon#read 5, iclass 5, count 0 2006.253.07:37:08.94#ibcon#about to read 6, iclass 5, count 0 2006.253.07:37:08.94#ibcon#read 6, iclass 5, count 0 2006.253.07:37:08.94#ibcon#end of sib2, iclass 5, count 0 2006.253.07:37:08.94#ibcon#*mode == 0, iclass 5, count 0 2006.253.07:37:08.94#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.253.07:37:08.94#ibcon#[26=FRQ=04,832.99\r\n] 2006.253.07:37:08.94#ibcon#*before write, iclass 5, count 0 2006.253.07:37:08.94#ibcon#enter sib2, iclass 5, count 0 2006.253.07:37:08.94#ibcon#flushed, iclass 5, count 0 2006.253.07:37:08.94#ibcon#about to write, iclass 5, count 0 2006.253.07:37:08.94#ibcon#wrote, iclass 5, count 0 2006.253.07:37:08.94#ibcon#about to read 3, iclass 5, count 0 2006.253.07:37:08.99#ibcon#read 3, iclass 5, count 0 2006.253.07:37:08.99#ibcon#about to read 4, iclass 5, count 0 2006.253.07:37:08.99#ibcon#read 4, iclass 5, count 0 2006.253.07:37:08.99#ibcon#about to read 5, iclass 5, count 0 2006.253.07:37:08.99#ibcon#read 5, iclass 5, count 0 2006.253.07:37:08.99#ibcon#about to read 6, iclass 5, count 0 2006.253.07:37:08.99#ibcon#read 6, iclass 5, count 0 2006.253.07:37:08.99#ibcon#end of sib2, iclass 5, count 0 2006.253.07:37:08.99#ibcon#*after write, iclass 5, count 0 2006.253.07:37:08.99#ibcon#*before return 0, iclass 5, count 0 2006.253.07:37:08.99#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.253.07:37:08.99#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.253.07:37:08.99#ibcon#about to clear, iclass 5 cls_cnt 0 2006.253.07:37:08.99#ibcon#cleared, iclass 5 cls_cnt 0 2006.253.07:37:08.99$vc4f8/va=4,7 2006.253.07:37:08.99#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.253.07:37:08.99#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.253.07:37:08.99#ibcon#ireg 11 cls_cnt 2 2006.253.07:37:08.99#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.253.07:37:09.04#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.253.07:37:09.04#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.253.07:37:09.04#ibcon#enter wrdev, iclass 7, count 2 2006.253.07:37:09.04#ibcon#first serial, iclass 7, count 2 2006.253.07:37:09.04#ibcon#enter sib2, iclass 7, count 2 2006.253.07:37:09.04#ibcon#flushed, iclass 7, count 2 2006.253.07:37:09.04#ibcon#about to write, iclass 7, count 2 2006.253.07:37:09.04#ibcon#wrote, iclass 7, count 2 2006.253.07:37:09.04#ibcon#about to read 3, iclass 7, count 2 2006.253.07:37:09.06#ibcon#read 3, iclass 7, count 2 2006.253.07:37:09.06#ibcon#about to read 4, iclass 7, count 2 2006.253.07:37:09.06#ibcon#read 4, iclass 7, count 2 2006.253.07:37:09.06#ibcon#about to read 5, iclass 7, count 2 2006.253.07:37:09.06#ibcon#read 5, iclass 7, count 2 2006.253.07:37:09.06#ibcon#about to read 6, iclass 7, count 2 2006.253.07:37:09.06#ibcon#read 6, iclass 7, count 2 2006.253.07:37:09.06#ibcon#end of sib2, iclass 7, count 2 2006.253.07:37:09.06#ibcon#*mode == 0, iclass 7, count 2 2006.253.07:37:09.06#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.253.07:37:09.06#ibcon#[25=AT04-07\r\n] 2006.253.07:37:09.06#ibcon#*before write, iclass 7, count 2 2006.253.07:37:09.06#ibcon#enter sib2, iclass 7, count 2 2006.253.07:37:09.06#ibcon#flushed, iclass 7, count 2 2006.253.07:37:09.06#ibcon#about to write, iclass 7, count 2 2006.253.07:37:09.06#ibcon#wrote, iclass 7, count 2 2006.253.07:37:09.06#ibcon#about to read 3, iclass 7, count 2 2006.253.07:37:09.09#ibcon#read 3, iclass 7, count 2 2006.253.07:37:09.09#ibcon#about to read 4, iclass 7, count 2 2006.253.07:37:09.09#ibcon#read 4, iclass 7, count 2 2006.253.07:37:09.09#ibcon#about to read 5, iclass 7, count 2 2006.253.07:37:09.09#ibcon#read 5, iclass 7, count 2 2006.253.07:37:09.09#ibcon#about to read 6, iclass 7, count 2 2006.253.07:37:09.09#ibcon#read 6, iclass 7, count 2 2006.253.07:37:09.09#ibcon#end of sib2, iclass 7, count 2 2006.253.07:37:09.09#ibcon#*after write, iclass 7, count 2 2006.253.07:37:09.09#ibcon#*before return 0, iclass 7, count 2 2006.253.07:37:09.09#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.253.07:37:09.09#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.253.07:37:09.09#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.253.07:37:09.09#ibcon#ireg 7 cls_cnt 0 2006.253.07:37:09.09#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.253.07:37:09.21#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.253.07:37:09.21#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.253.07:37:09.21#ibcon#enter wrdev, iclass 7, count 0 2006.253.07:37:09.21#ibcon#first serial, iclass 7, count 0 2006.253.07:37:09.21#ibcon#enter sib2, iclass 7, count 0 2006.253.07:37:09.21#ibcon#flushed, iclass 7, count 0 2006.253.07:37:09.21#ibcon#about to write, iclass 7, count 0 2006.253.07:37:09.21#ibcon#wrote, iclass 7, count 0 2006.253.07:37:09.21#ibcon#about to read 3, iclass 7, count 0 2006.253.07:37:09.23#ibcon#read 3, iclass 7, count 0 2006.253.07:37:09.23#ibcon#about to read 4, iclass 7, count 0 2006.253.07:37:09.23#ibcon#read 4, iclass 7, count 0 2006.253.07:37:09.23#ibcon#about to read 5, iclass 7, count 0 2006.253.07:37:09.23#ibcon#read 5, iclass 7, count 0 2006.253.07:37:09.23#ibcon#about to read 6, iclass 7, count 0 2006.253.07:37:09.23#ibcon#read 6, iclass 7, count 0 2006.253.07:37:09.23#ibcon#end of sib2, iclass 7, count 0 2006.253.07:37:09.23#ibcon#*mode == 0, iclass 7, count 0 2006.253.07:37:09.23#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.253.07:37:09.23#ibcon#[25=USB\r\n] 2006.253.07:37:09.23#ibcon#*before write, iclass 7, count 0 2006.253.07:37:09.23#ibcon#enter sib2, iclass 7, count 0 2006.253.07:37:09.23#ibcon#flushed, iclass 7, count 0 2006.253.07:37:09.23#ibcon#about to write, iclass 7, count 0 2006.253.07:37:09.23#ibcon#wrote, iclass 7, count 0 2006.253.07:37:09.23#ibcon#about to read 3, iclass 7, count 0 2006.253.07:37:09.26#ibcon#read 3, iclass 7, count 0 2006.253.07:37:09.26#ibcon#about to read 4, iclass 7, count 0 2006.253.07:37:09.26#ibcon#read 4, iclass 7, count 0 2006.253.07:37:09.26#ibcon#about to read 5, iclass 7, count 0 2006.253.07:37:09.26#ibcon#read 5, iclass 7, count 0 2006.253.07:37:09.26#ibcon#about to read 6, iclass 7, count 0 2006.253.07:37:09.26#ibcon#read 6, iclass 7, count 0 2006.253.07:37:09.26#ibcon#end of sib2, iclass 7, count 0 2006.253.07:37:09.26#ibcon#*after write, iclass 7, count 0 2006.253.07:37:09.26#ibcon#*before return 0, iclass 7, count 0 2006.253.07:37:09.26#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.253.07:37:09.26#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.253.07:37:09.26#ibcon#about to clear, iclass 7 cls_cnt 0 2006.253.07:37:09.26#ibcon#cleared, iclass 7 cls_cnt 0 2006.253.07:37:09.26$vc4f8/valo=5,652.99 2006.253.07:37:09.26#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.253.07:37:09.26#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.253.07:37:09.26#ibcon#ireg 17 cls_cnt 0 2006.253.07:37:09.26#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.253.07:37:09.26#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.253.07:37:09.26#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.253.07:37:09.26#ibcon#enter wrdev, iclass 11, count 0 2006.253.07:37:09.26#ibcon#first serial, iclass 11, count 0 2006.253.07:37:09.26#ibcon#enter sib2, iclass 11, count 0 2006.253.07:37:09.26#ibcon#flushed, iclass 11, count 0 2006.253.07:37:09.26#ibcon#about to write, iclass 11, count 0 2006.253.07:37:09.26#ibcon#wrote, iclass 11, count 0 2006.253.07:37:09.26#ibcon#about to read 3, iclass 11, count 0 2006.253.07:37:09.28#ibcon#read 3, iclass 11, count 0 2006.253.07:37:09.28#ibcon#about to read 4, iclass 11, count 0 2006.253.07:37:09.28#ibcon#read 4, iclass 11, count 0 2006.253.07:37:09.28#ibcon#about to read 5, iclass 11, count 0 2006.253.07:37:09.28#ibcon#read 5, iclass 11, count 0 2006.253.07:37:09.28#ibcon#about to read 6, iclass 11, count 0 2006.253.07:37:09.28#ibcon#read 6, iclass 11, count 0 2006.253.07:37:09.28#ibcon#end of sib2, iclass 11, count 0 2006.253.07:37:09.28#ibcon#*mode == 0, iclass 11, count 0 2006.253.07:37:09.28#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.253.07:37:09.28#ibcon#[26=FRQ=05,652.99\r\n] 2006.253.07:37:09.28#ibcon#*before write, iclass 11, count 0 2006.253.07:37:09.28#ibcon#enter sib2, iclass 11, count 0 2006.253.07:37:09.28#ibcon#flushed, iclass 11, count 0 2006.253.07:37:09.28#ibcon#about to write, iclass 11, count 0 2006.253.07:37:09.28#ibcon#wrote, iclass 11, count 0 2006.253.07:37:09.28#ibcon#about to read 3, iclass 11, count 0 2006.253.07:37:09.32#ibcon#read 3, iclass 11, count 0 2006.253.07:37:09.32#ibcon#about to read 4, iclass 11, count 0 2006.253.07:37:09.32#ibcon#read 4, iclass 11, count 0 2006.253.07:37:09.32#ibcon#about to read 5, iclass 11, count 0 2006.253.07:37:09.32#ibcon#read 5, iclass 11, count 0 2006.253.07:37:09.32#ibcon#about to read 6, iclass 11, count 0 2006.253.07:37:09.32#ibcon#read 6, iclass 11, count 0 2006.253.07:37:09.32#ibcon#end of sib2, iclass 11, count 0 2006.253.07:37:09.32#ibcon#*after write, iclass 11, count 0 2006.253.07:37:09.32#ibcon#*before return 0, iclass 11, count 0 2006.253.07:37:09.32#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.253.07:37:09.32#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.253.07:37:09.32#ibcon#about to clear, iclass 11 cls_cnt 0 2006.253.07:37:09.32#ibcon#cleared, iclass 11 cls_cnt 0 2006.253.07:37:09.32$vc4f8/va=5,7 2006.253.07:37:09.32#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.253.07:37:09.32#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.253.07:37:09.32#ibcon#ireg 11 cls_cnt 2 2006.253.07:37:09.32#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.253.07:37:09.38#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.253.07:37:09.38#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.253.07:37:09.38#ibcon#enter wrdev, iclass 13, count 2 2006.253.07:37:09.38#ibcon#first serial, iclass 13, count 2 2006.253.07:37:09.38#ibcon#enter sib2, iclass 13, count 2 2006.253.07:37:09.38#ibcon#flushed, iclass 13, count 2 2006.253.07:37:09.38#ibcon#about to write, iclass 13, count 2 2006.253.07:37:09.38#ibcon#wrote, iclass 13, count 2 2006.253.07:37:09.38#ibcon#about to read 3, iclass 13, count 2 2006.253.07:37:09.40#ibcon#read 3, iclass 13, count 2 2006.253.07:37:09.40#ibcon#about to read 4, iclass 13, count 2 2006.253.07:37:09.40#ibcon#read 4, iclass 13, count 2 2006.253.07:37:09.40#ibcon#about to read 5, iclass 13, count 2 2006.253.07:37:09.40#ibcon#read 5, iclass 13, count 2 2006.253.07:37:09.40#ibcon#about to read 6, iclass 13, count 2 2006.253.07:37:09.40#ibcon#read 6, iclass 13, count 2 2006.253.07:37:09.40#ibcon#end of sib2, iclass 13, count 2 2006.253.07:37:09.40#ibcon#*mode == 0, iclass 13, count 2 2006.253.07:37:09.40#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.253.07:37:09.40#ibcon#[25=AT05-07\r\n] 2006.253.07:37:09.40#ibcon#*before write, iclass 13, count 2 2006.253.07:37:09.40#ibcon#enter sib2, iclass 13, count 2 2006.253.07:37:09.40#ibcon#flushed, iclass 13, count 2 2006.253.07:37:09.40#ibcon#about to write, iclass 13, count 2 2006.253.07:37:09.40#ibcon#wrote, iclass 13, count 2 2006.253.07:37:09.40#ibcon#about to read 3, iclass 13, count 2 2006.253.07:37:09.43#ibcon#read 3, iclass 13, count 2 2006.253.07:37:09.43#ibcon#about to read 4, iclass 13, count 2 2006.253.07:37:09.43#ibcon#read 4, iclass 13, count 2 2006.253.07:37:09.43#ibcon#about to read 5, iclass 13, count 2 2006.253.07:37:09.43#ibcon#read 5, iclass 13, count 2 2006.253.07:37:09.43#ibcon#about to read 6, iclass 13, count 2 2006.253.07:37:09.43#ibcon#read 6, iclass 13, count 2 2006.253.07:37:09.43#ibcon#end of sib2, iclass 13, count 2 2006.253.07:37:09.43#ibcon#*after write, iclass 13, count 2 2006.253.07:37:09.43#ibcon#*before return 0, iclass 13, count 2 2006.253.07:37:09.43#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.253.07:37:09.43#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.253.07:37:09.43#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.253.07:37:09.43#ibcon#ireg 7 cls_cnt 0 2006.253.07:37:09.43#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.253.07:37:09.55#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.253.07:37:09.55#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.253.07:37:09.55#ibcon#enter wrdev, iclass 13, count 0 2006.253.07:37:09.55#ibcon#first serial, iclass 13, count 0 2006.253.07:37:09.55#ibcon#enter sib2, iclass 13, count 0 2006.253.07:37:09.55#ibcon#flushed, iclass 13, count 0 2006.253.07:37:09.55#ibcon#about to write, iclass 13, count 0 2006.253.07:37:09.55#ibcon#wrote, iclass 13, count 0 2006.253.07:37:09.55#ibcon#about to read 3, iclass 13, count 0 2006.253.07:37:09.57#ibcon#read 3, iclass 13, count 0 2006.253.07:37:09.57#ibcon#about to read 4, iclass 13, count 0 2006.253.07:37:09.57#ibcon#read 4, iclass 13, count 0 2006.253.07:37:09.57#ibcon#about to read 5, iclass 13, count 0 2006.253.07:37:09.57#ibcon#read 5, iclass 13, count 0 2006.253.07:37:09.57#ibcon#about to read 6, iclass 13, count 0 2006.253.07:37:09.57#ibcon#read 6, iclass 13, count 0 2006.253.07:37:09.57#ibcon#end of sib2, iclass 13, count 0 2006.253.07:37:09.57#ibcon#*mode == 0, iclass 13, count 0 2006.253.07:37:09.57#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.253.07:37:09.57#ibcon#[25=USB\r\n] 2006.253.07:37:09.57#ibcon#*before write, iclass 13, count 0 2006.253.07:37:09.57#ibcon#enter sib2, iclass 13, count 0 2006.253.07:37:09.57#ibcon#flushed, iclass 13, count 0 2006.253.07:37:09.57#ibcon#about to write, iclass 13, count 0 2006.253.07:37:09.57#ibcon#wrote, iclass 13, count 0 2006.253.07:37:09.57#ibcon#about to read 3, iclass 13, count 0 2006.253.07:37:09.60#ibcon#read 3, iclass 13, count 0 2006.253.07:37:09.60#ibcon#about to read 4, iclass 13, count 0 2006.253.07:37:09.60#ibcon#read 4, iclass 13, count 0 2006.253.07:37:09.60#ibcon#about to read 5, iclass 13, count 0 2006.253.07:37:09.60#ibcon#read 5, iclass 13, count 0 2006.253.07:37:09.60#ibcon#about to read 6, iclass 13, count 0 2006.253.07:37:09.60#ibcon#read 6, iclass 13, count 0 2006.253.07:37:09.60#ibcon#end of sib2, iclass 13, count 0 2006.253.07:37:09.60#ibcon#*after write, iclass 13, count 0 2006.253.07:37:09.60#ibcon#*before return 0, iclass 13, count 0 2006.253.07:37:09.60#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.253.07:37:09.60#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.253.07:37:09.60#ibcon#about to clear, iclass 13 cls_cnt 0 2006.253.07:37:09.60#ibcon#cleared, iclass 13 cls_cnt 0 2006.253.07:37:09.60$vc4f8/valo=6,772.99 2006.253.07:37:09.60#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.253.07:37:09.60#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.253.07:37:09.60#ibcon#ireg 17 cls_cnt 0 2006.253.07:37:09.60#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.253.07:37:09.60#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.253.07:37:09.60#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.253.07:37:09.60#ibcon#enter wrdev, iclass 15, count 0 2006.253.07:37:09.60#ibcon#first serial, iclass 15, count 0 2006.253.07:37:09.60#ibcon#enter sib2, iclass 15, count 0 2006.253.07:37:09.60#ibcon#flushed, iclass 15, count 0 2006.253.07:37:09.60#ibcon#about to write, iclass 15, count 0 2006.253.07:37:09.60#ibcon#wrote, iclass 15, count 0 2006.253.07:37:09.60#ibcon#about to read 3, iclass 15, count 0 2006.253.07:37:09.62#ibcon#read 3, iclass 15, count 0 2006.253.07:37:09.62#ibcon#about to read 4, iclass 15, count 0 2006.253.07:37:09.62#ibcon#read 4, iclass 15, count 0 2006.253.07:37:09.62#ibcon#about to read 5, iclass 15, count 0 2006.253.07:37:09.62#ibcon#read 5, iclass 15, count 0 2006.253.07:37:09.62#ibcon#about to read 6, iclass 15, count 0 2006.253.07:37:09.62#ibcon#read 6, iclass 15, count 0 2006.253.07:37:09.62#ibcon#end of sib2, iclass 15, count 0 2006.253.07:37:09.62#ibcon#*mode == 0, iclass 15, count 0 2006.253.07:37:09.62#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.253.07:37:09.62#ibcon#[26=FRQ=06,772.99\r\n] 2006.253.07:37:09.62#ibcon#*before write, iclass 15, count 0 2006.253.07:37:09.62#ibcon#enter sib2, iclass 15, count 0 2006.253.07:37:09.62#ibcon#flushed, iclass 15, count 0 2006.253.07:37:09.62#ibcon#about to write, iclass 15, count 0 2006.253.07:37:09.62#ibcon#wrote, iclass 15, count 0 2006.253.07:37:09.62#ibcon#about to read 3, iclass 15, count 0 2006.253.07:37:09.66#ibcon#read 3, iclass 15, count 0 2006.253.07:37:09.66#ibcon#about to read 4, iclass 15, count 0 2006.253.07:37:09.66#ibcon#read 4, iclass 15, count 0 2006.253.07:37:09.66#ibcon#about to read 5, iclass 15, count 0 2006.253.07:37:09.66#ibcon#read 5, iclass 15, count 0 2006.253.07:37:09.66#ibcon#about to read 6, iclass 15, count 0 2006.253.07:37:09.66#ibcon#read 6, iclass 15, count 0 2006.253.07:37:09.66#ibcon#end of sib2, iclass 15, count 0 2006.253.07:37:09.66#ibcon#*after write, iclass 15, count 0 2006.253.07:37:09.66#ibcon#*before return 0, iclass 15, count 0 2006.253.07:37:09.66#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.253.07:37:09.66#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.253.07:37:09.66#ibcon#about to clear, iclass 15 cls_cnt 0 2006.253.07:37:09.66#ibcon#cleared, iclass 15 cls_cnt 0 2006.253.07:37:09.66$vc4f8/va=6,7 2006.253.07:37:09.66#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.253.07:37:09.66#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.253.07:37:09.66#ibcon#ireg 11 cls_cnt 2 2006.253.07:37:09.66#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.253.07:37:09.72#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.253.07:37:09.72#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.253.07:37:09.72#ibcon#enter wrdev, iclass 17, count 2 2006.253.07:37:09.72#ibcon#first serial, iclass 17, count 2 2006.253.07:37:09.72#ibcon#enter sib2, iclass 17, count 2 2006.253.07:37:09.72#ibcon#flushed, iclass 17, count 2 2006.253.07:37:09.72#ibcon#about to write, iclass 17, count 2 2006.253.07:37:09.72#ibcon#wrote, iclass 17, count 2 2006.253.07:37:09.72#ibcon#about to read 3, iclass 17, count 2 2006.253.07:37:09.74#ibcon#read 3, iclass 17, count 2 2006.253.07:37:09.74#ibcon#about to read 4, iclass 17, count 2 2006.253.07:37:09.74#ibcon#read 4, iclass 17, count 2 2006.253.07:37:09.74#ibcon#about to read 5, iclass 17, count 2 2006.253.07:37:09.74#ibcon#read 5, iclass 17, count 2 2006.253.07:37:09.74#ibcon#about to read 6, iclass 17, count 2 2006.253.07:37:09.74#ibcon#read 6, iclass 17, count 2 2006.253.07:37:09.74#ibcon#end of sib2, iclass 17, count 2 2006.253.07:37:09.74#ibcon#*mode == 0, iclass 17, count 2 2006.253.07:37:09.74#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.253.07:37:09.74#ibcon#[25=AT06-07\r\n] 2006.253.07:37:09.74#ibcon#*before write, iclass 17, count 2 2006.253.07:37:09.74#ibcon#enter sib2, iclass 17, count 2 2006.253.07:37:09.74#ibcon#flushed, iclass 17, count 2 2006.253.07:37:09.74#ibcon#about to write, iclass 17, count 2 2006.253.07:37:09.74#ibcon#wrote, iclass 17, count 2 2006.253.07:37:09.74#ibcon#about to read 3, iclass 17, count 2 2006.253.07:37:09.77#ibcon#read 3, iclass 17, count 2 2006.253.07:37:09.77#ibcon#about to read 4, iclass 17, count 2 2006.253.07:37:09.77#ibcon#read 4, iclass 17, count 2 2006.253.07:37:09.77#ibcon#about to read 5, iclass 17, count 2 2006.253.07:37:09.77#ibcon#read 5, iclass 17, count 2 2006.253.07:37:09.77#ibcon#about to read 6, iclass 17, count 2 2006.253.07:37:09.77#ibcon#read 6, iclass 17, count 2 2006.253.07:37:09.77#ibcon#end of sib2, iclass 17, count 2 2006.253.07:37:09.77#ibcon#*after write, iclass 17, count 2 2006.253.07:37:09.77#ibcon#*before return 0, iclass 17, count 2 2006.253.07:37:09.77#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.253.07:37:09.77#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.253.07:37:09.77#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.253.07:37:09.77#ibcon#ireg 7 cls_cnt 0 2006.253.07:37:09.77#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.253.07:37:09.89#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.253.07:37:09.89#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.253.07:37:09.89#ibcon#enter wrdev, iclass 17, count 0 2006.253.07:37:09.89#ibcon#first serial, iclass 17, count 0 2006.253.07:37:09.89#ibcon#enter sib2, iclass 17, count 0 2006.253.07:37:09.89#ibcon#flushed, iclass 17, count 0 2006.253.07:37:09.89#ibcon#about to write, iclass 17, count 0 2006.253.07:37:09.89#ibcon#wrote, iclass 17, count 0 2006.253.07:37:09.89#ibcon#about to read 3, iclass 17, count 0 2006.253.07:37:09.91#ibcon#read 3, iclass 17, count 0 2006.253.07:37:09.91#ibcon#about to read 4, iclass 17, count 0 2006.253.07:37:09.91#ibcon#read 4, iclass 17, count 0 2006.253.07:37:09.91#ibcon#about to read 5, iclass 17, count 0 2006.253.07:37:09.91#ibcon#read 5, iclass 17, count 0 2006.253.07:37:09.91#ibcon#about to read 6, iclass 17, count 0 2006.253.07:37:09.91#ibcon#read 6, iclass 17, count 0 2006.253.07:37:09.91#ibcon#end of sib2, iclass 17, count 0 2006.253.07:37:09.91#ibcon#*mode == 0, iclass 17, count 0 2006.253.07:37:09.91#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.253.07:37:09.91#ibcon#[25=USB\r\n] 2006.253.07:37:09.91#ibcon#*before write, iclass 17, count 0 2006.253.07:37:09.91#ibcon#enter sib2, iclass 17, count 0 2006.253.07:37:09.91#ibcon#flushed, iclass 17, count 0 2006.253.07:37:09.91#ibcon#about to write, iclass 17, count 0 2006.253.07:37:09.91#ibcon#wrote, iclass 17, count 0 2006.253.07:37:09.91#ibcon#about to read 3, iclass 17, count 0 2006.253.07:37:09.94#ibcon#read 3, iclass 17, count 0 2006.253.07:37:09.94#ibcon#about to read 4, iclass 17, count 0 2006.253.07:37:09.94#ibcon#read 4, iclass 17, count 0 2006.253.07:37:09.94#ibcon#about to read 5, iclass 17, count 0 2006.253.07:37:09.94#ibcon#read 5, iclass 17, count 0 2006.253.07:37:09.94#ibcon#about to read 6, iclass 17, count 0 2006.253.07:37:09.94#ibcon#read 6, iclass 17, count 0 2006.253.07:37:09.94#ibcon#end of sib2, iclass 17, count 0 2006.253.07:37:09.94#ibcon#*after write, iclass 17, count 0 2006.253.07:37:09.94#ibcon#*before return 0, iclass 17, count 0 2006.253.07:37:09.94#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.253.07:37:09.94#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.253.07:37:09.94#ibcon#about to clear, iclass 17 cls_cnt 0 2006.253.07:37:09.94#ibcon#cleared, iclass 17 cls_cnt 0 2006.253.07:37:09.94$vc4f8/valo=7,832.99 2006.253.07:37:09.94#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.253.07:37:09.94#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.253.07:37:09.94#ibcon#ireg 17 cls_cnt 0 2006.253.07:37:09.94#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.253.07:37:09.94#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.253.07:37:09.94#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.253.07:37:09.94#ibcon#enter wrdev, iclass 19, count 0 2006.253.07:37:09.94#ibcon#first serial, iclass 19, count 0 2006.253.07:37:09.94#ibcon#enter sib2, iclass 19, count 0 2006.253.07:37:09.94#ibcon#flushed, iclass 19, count 0 2006.253.07:37:09.94#ibcon#about to write, iclass 19, count 0 2006.253.07:37:09.94#ibcon#wrote, iclass 19, count 0 2006.253.07:37:09.94#ibcon#about to read 3, iclass 19, count 0 2006.253.07:37:09.96#ibcon#read 3, iclass 19, count 0 2006.253.07:37:09.96#ibcon#about to read 4, iclass 19, count 0 2006.253.07:37:09.96#ibcon#read 4, iclass 19, count 0 2006.253.07:37:09.96#ibcon#about to read 5, iclass 19, count 0 2006.253.07:37:09.96#ibcon#read 5, iclass 19, count 0 2006.253.07:37:09.96#ibcon#about to read 6, iclass 19, count 0 2006.253.07:37:09.96#ibcon#read 6, iclass 19, count 0 2006.253.07:37:09.96#ibcon#end of sib2, iclass 19, count 0 2006.253.07:37:09.96#ibcon#*mode == 0, iclass 19, count 0 2006.253.07:37:09.96#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.253.07:37:09.96#ibcon#[26=FRQ=07,832.99\r\n] 2006.253.07:37:09.96#ibcon#*before write, iclass 19, count 0 2006.253.07:37:09.96#ibcon#enter sib2, iclass 19, count 0 2006.253.07:37:09.96#ibcon#flushed, iclass 19, count 0 2006.253.07:37:09.96#ibcon#about to write, iclass 19, count 0 2006.253.07:37:09.96#ibcon#wrote, iclass 19, count 0 2006.253.07:37:09.96#ibcon#about to read 3, iclass 19, count 0 2006.253.07:37:10.00#ibcon#read 3, iclass 19, count 0 2006.253.07:37:10.00#ibcon#about to read 4, iclass 19, count 0 2006.253.07:37:10.00#ibcon#read 4, iclass 19, count 0 2006.253.07:37:10.00#ibcon#about to read 5, iclass 19, count 0 2006.253.07:37:10.00#ibcon#read 5, iclass 19, count 0 2006.253.07:37:10.00#ibcon#about to read 6, iclass 19, count 0 2006.253.07:37:10.00#ibcon#read 6, iclass 19, count 0 2006.253.07:37:10.00#ibcon#end of sib2, iclass 19, count 0 2006.253.07:37:10.00#ibcon#*after write, iclass 19, count 0 2006.253.07:37:10.00#ibcon#*before return 0, iclass 19, count 0 2006.253.07:37:10.00#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.253.07:37:10.00#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.253.07:37:10.00#ibcon#about to clear, iclass 19 cls_cnt 0 2006.253.07:37:10.00#ibcon#cleared, iclass 19 cls_cnt 0 2006.253.07:37:10.00$vc4f8/va=7,7 2006.253.07:37:10.00#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.253.07:37:10.00#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.253.07:37:10.00#ibcon#ireg 11 cls_cnt 2 2006.253.07:37:10.00#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.253.07:37:10.06#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.253.07:37:10.06#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.253.07:37:10.06#ibcon#enter wrdev, iclass 21, count 2 2006.253.07:37:10.06#ibcon#first serial, iclass 21, count 2 2006.253.07:37:10.06#ibcon#enter sib2, iclass 21, count 2 2006.253.07:37:10.06#ibcon#flushed, iclass 21, count 2 2006.253.07:37:10.06#ibcon#about to write, iclass 21, count 2 2006.253.07:37:10.06#ibcon#wrote, iclass 21, count 2 2006.253.07:37:10.06#ibcon#about to read 3, iclass 21, count 2 2006.253.07:37:10.08#ibcon#read 3, iclass 21, count 2 2006.253.07:37:10.08#ibcon#about to read 4, iclass 21, count 2 2006.253.07:37:10.08#ibcon#read 4, iclass 21, count 2 2006.253.07:37:10.08#ibcon#about to read 5, iclass 21, count 2 2006.253.07:37:10.08#ibcon#read 5, iclass 21, count 2 2006.253.07:37:10.08#ibcon#about to read 6, iclass 21, count 2 2006.253.07:37:10.08#ibcon#read 6, iclass 21, count 2 2006.253.07:37:10.08#ibcon#end of sib2, iclass 21, count 2 2006.253.07:37:10.08#ibcon#*mode == 0, iclass 21, count 2 2006.253.07:37:10.08#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.253.07:37:10.08#ibcon#[25=AT07-07\r\n] 2006.253.07:37:10.08#ibcon#*before write, iclass 21, count 2 2006.253.07:37:10.08#ibcon#enter sib2, iclass 21, count 2 2006.253.07:37:10.08#ibcon#flushed, iclass 21, count 2 2006.253.07:37:10.08#ibcon#about to write, iclass 21, count 2 2006.253.07:37:10.08#ibcon#wrote, iclass 21, count 2 2006.253.07:37:10.08#ibcon#about to read 3, iclass 21, count 2 2006.253.07:37:10.11#ibcon#read 3, iclass 21, count 2 2006.253.07:37:10.11#ibcon#about to read 4, iclass 21, count 2 2006.253.07:37:10.11#ibcon#read 4, iclass 21, count 2 2006.253.07:37:10.11#ibcon#about to read 5, iclass 21, count 2 2006.253.07:37:10.11#ibcon#read 5, iclass 21, count 2 2006.253.07:37:10.11#ibcon#about to read 6, iclass 21, count 2 2006.253.07:37:10.11#ibcon#read 6, iclass 21, count 2 2006.253.07:37:10.11#ibcon#end of sib2, iclass 21, count 2 2006.253.07:37:10.11#ibcon#*after write, iclass 21, count 2 2006.253.07:37:10.11#ibcon#*before return 0, iclass 21, count 2 2006.253.07:37:10.11#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.253.07:37:10.11#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.253.07:37:10.11#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.253.07:37:10.11#ibcon#ireg 7 cls_cnt 0 2006.253.07:37:10.11#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.253.07:37:10.23#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.253.07:37:10.23#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.253.07:37:10.23#ibcon#enter wrdev, iclass 21, count 0 2006.253.07:37:10.23#ibcon#first serial, iclass 21, count 0 2006.253.07:37:10.23#ibcon#enter sib2, iclass 21, count 0 2006.253.07:37:10.23#ibcon#flushed, iclass 21, count 0 2006.253.07:37:10.23#ibcon#about to write, iclass 21, count 0 2006.253.07:37:10.23#ibcon#wrote, iclass 21, count 0 2006.253.07:37:10.23#ibcon#about to read 3, iclass 21, count 0 2006.253.07:37:10.25#ibcon#read 3, iclass 21, count 0 2006.253.07:37:10.25#ibcon#about to read 4, iclass 21, count 0 2006.253.07:37:10.25#ibcon#read 4, iclass 21, count 0 2006.253.07:37:10.25#ibcon#about to read 5, iclass 21, count 0 2006.253.07:37:10.25#ibcon#read 5, iclass 21, count 0 2006.253.07:37:10.25#ibcon#about to read 6, iclass 21, count 0 2006.253.07:37:10.25#ibcon#read 6, iclass 21, count 0 2006.253.07:37:10.25#ibcon#end of sib2, iclass 21, count 0 2006.253.07:37:10.25#ibcon#*mode == 0, iclass 21, count 0 2006.253.07:37:10.25#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.253.07:37:10.25#ibcon#[25=USB\r\n] 2006.253.07:37:10.25#ibcon#*before write, iclass 21, count 0 2006.253.07:37:10.25#ibcon#enter sib2, iclass 21, count 0 2006.253.07:37:10.25#ibcon#flushed, iclass 21, count 0 2006.253.07:37:10.25#ibcon#about to write, iclass 21, count 0 2006.253.07:37:10.25#ibcon#wrote, iclass 21, count 0 2006.253.07:37:10.25#ibcon#about to read 3, iclass 21, count 0 2006.253.07:37:10.28#ibcon#read 3, iclass 21, count 0 2006.253.07:37:10.28#ibcon#about to read 4, iclass 21, count 0 2006.253.07:37:10.28#ibcon#read 4, iclass 21, count 0 2006.253.07:37:10.28#ibcon#about to read 5, iclass 21, count 0 2006.253.07:37:10.28#ibcon#read 5, iclass 21, count 0 2006.253.07:37:10.28#ibcon#about to read 6, iclass 21, count 0 2006.253.07:37:10.28#ibcon#read 6, iclass 21, count 0 2006.253.07:37:10.28#ibcon#end of sib2, iclass 21, count 0 2006.253.07:37:10.28#ibcon#*after write, iclass 21, count 0 2006.253.07:37:10.28#ibcon#*before return 0, iclass 21, count 0 2006.253.07:37:10.28#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.253.07:37:10.28#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.253.07:37:10.28#ibcon#about to clear, iclass 21 cls_cnt 0 2006.253.07:37:10.28#ibcon#cleared, iclass 21 cls_cnt 0 2006.253.07:37:10.28$vc4f8/valo=8,852.99 2006.253.07:37:10.28#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.253.07:37:10.28#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.253.07:37:10.28#ibcon#ireg 17 cls_cnt 0 2006.253.07:37:10.28#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.253.07:37:10.28#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.253.07:37:10.28#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.253.07:37:10.28#ibcon#enter wrdev, iclass 23, count 0 2006.253.07:37:10.28#ibcon#first serial, iclass 23, count 0 2006.253.07:37:10.28#ibcon#enter sib2, iclass 23, count 0 2006.253.07:37:10.28#ibcon#flushed, iclass 23, count 0 2006.253.07:37:10.28#ibcon#about to write, iclass 23, count 0 2006.253.07:37:10.28#ibcon#wrote, iclass 23, count 0 2006.253.07:37:10.28#ibcon#about to read 3, iclass 23, count 0 2006.253.07:37:10.30#ibcon#read 3, iclass 23, count 0 2006.253.07:37:10.30#ibcon#about to read 4, iclass 23, count 0 2006.253.07:37:10.30#ibcon#read 4, iclass 23, count 0 2006.253.07:37:10.30#ibcon#about to read 5, iclass 23, count 0 2006.253.07:37:10.30#ibcon#read 5, iclass 23, count 0 2006.253.07:37:10.30#ibcon#about to read 6, iclass 23, count 0 2006.253.07:37:10.30#ibcon#read 6, iclass 23, count 0 2006.253.07:37:10.30#ibcon#end of sib2, iclass 23, count 0 2006.253.07:37:10.30#ibcon#*mode == 0, iclass 23, count 0 2006.253.07:37:10.30#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.253.07:37:10.30#ibcon#[26=FRQ=08,852.99\r\n] 2006.253.07:37:10.30#ibcon#*before write, iclass 23, count 0 2006.253.07:37:10.30#ibcon#enter sib2, iclass 23, count 0 2006.253.07:37:10.30#ibcon#flushed, iclass 23, count 0 2006.253.07:37:10.30#ibcon#about to write, iclass 23, count 0 2006.253.07:37:10.30#ibcon#wrote, iclass 23, count 0 2006.253.07:37:10.30#ibcon#about to read 3, iclass 23, count 0 2006.253.07:37:10.35#ibcon#read 3, iclass 23, count 0 2006.253.07:37:10.35#ibcon#about to read 4, iclass 23, count 0 2006.253.07:37:10.35#ibcon#read 4, iclass 23, count 0 2006.253.07:37:10.35#ibcon#about to read 5, iclass 23, count 0 2006.253.07:37:10.35#ibcon#read 5, iclass 23, count 0 2006.253.07:37:10.35#ibcon#about to read 6, iclass 23, count 0 2006.253.07:37:10.35#ibcon#read 6, iclass 23, count 0 2006.253.07:37:10.35#ibcon#end of sib2, iclass 23, count 0 2006.253.07:37:10.35#ibcon#*after write, iclass 23, count 0 2006.253.07:37:10.35#ibcon#*before return 0, iclass 23, count 0 2006.253.07:37:10.35#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.253.07:37:10.35#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.253.07:37:10.35#ibcon#about to clear, iclass 23 cls_cnt 0 2006.253.07:37:10.35#ibcon#cleared, iclass 23 cls_cnt 0 2006.253.07:37:10.35$vc4f8/va=8,7 2006.253.07:37:10.35#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.253.07:37:10.35#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.253.07:37:10.35#ibcon#ireg 11 cls_cnt 2 2006.253.07:37:10.35#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.253.07:37:10.40#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.253.07:37:10.40#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.253.07:37:10.40#ibcon#enter wrdev, iclass 25, count 2 2006.253.07:37:10.40#ibcon#first serial, iclass 25, count 2 2006.253.07:37:10.40#ibcon#enter sib2, iclass 25, count 2 2006.253.07:37:10.40#ibcon#flushed, iclass 25, count 2 2006.253.07:37:10.40#ibcon#about to write, iclass 25, count 2 2006.253.07:37:10.40#ibcon#wrote, iclass 25, count 2 2006.253.07:37:10.40#ibcon#about to read 3, iclass 25, count 2 2006.253.07:37:10.42#ibcon#read 3, iclass 25, count 2 2006.253.07:37:10.42#ibcon#about to read 4, iclass 25, count 2 2006.253.07:37:10.42#ibcon#read 4, iclass 25, count 2 2006.253.07:37:10.42#ibcon#about to read 5, iclass 25, count 2 2006.253.07:37:10.42#ibcon#read 5, iclass 25, count 2 2006.253.07:37:10.42#ibcon#about to read 6, iclass 25, count 2 2006.253.07:37:10.42#ibcon#read 6, iclass 25, count 2 2006.253.07:37:10.42#ibcon#end of sib2, iclass 25, count 2 2006.253.07:37:10.42#ibcon#*mode == 0, iclass 25, count 2 2006.253.07:37:10.42#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.253.07:37:10.42#ibcon#[25=AT08-07\r\n] 2006.253.07:37:10.42#ibcon#*before write, iclass 25, count 2 2006.253.07:37:10.42#ibcon#enter sib2, iclass 25, count 2 2006.253.07:37:10.42#ibcon#flushed, iclass 25, count 2 2006.253.07:37:10.42#ibcon#about to write, iclass 25, count 2 2006.253.07:37:10.42#ibcon#wrote, iclass 25, count 2 2006.253.07:37:10.42#ibcon#about to read 3, iclass 25, count 2 2006.253.07:37:10.45#ibcon#read 3, iclass 25, count 2 2006.253.07:37:10.45#ibcon#about to read 4, iclass 25, count 2 2006.253.07:37:10.45#ibcon#read 4, iclass 25, count 2 2006.253.07:37:10.45#ibcon#about to read 5, iclass 25, count 2 2006.253.07:37:10.45#ibcon#read 5, iclass 25, count 2 2006.253.07:37:10.45#ibcon#about to read 6, iclass 25, count 2 2006.253.07:37:10.45#ibcon#read 6, iclass 25, count 2 2006.253.07:37:10.45#ibcon#end of sib2, iclass 25, count 2 2006.253.07:37:10.45#ibcon#*after write, iclass 25, count 2 2006.253.07:37:10.45#ibcon#*before return 0, iclass 25, count 2 2006.253.07:37:10.45#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.253.07:37:10.45#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.253.07:37:10.45#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.253.07:37:10.45#ibcon#ireg 7 cls_cnt 0 2006.253.07:37:10.45#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.253.07:37:10.57#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.253.07:37:10.57#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.253.07:37:10.57#ibcon#enter wrdev, iclass 25, count 0 2006.253.07:37:10.57#ibcon#first serial, iclass 25, count 0 2006.253.07:37:10.57#ibcon#enter sib2, iclass 25, count 0 2006.253.07:37:10.57#ibcon#flushed, iclass 25, count 0 2006.253.07:37:10.57#ibcon#about to write, iclass 25, count 0 2006.253.07:37:10.57#ibcon#wrote, iclass 25, count 0 2006.253.07:37:10.57#ibcon#about to read 3, iclass 25, count 0 2006.253.07:37:10.59#ibcon#read 3, iclass 25, count 0 2006.253.07:37:10.59#ibcon#about to read 4, iclass 25, count 0 2006.253.07:37:10.59#ibcon#read 4, iclass 25, count 0 2006.253.07:37:10.59#ibcon#about to read 5, iclass 25, count 0 2006.253.07:37:10.59#ibcon#read 5, iclass 25, count 0 2006.253.07:37:10.59#ibcon#about to read 6, iclass 25, count 0 2006.253.07:37:10.59#ibcon#read 6, iclass 25, count 0 2006.253.07:37:10.59#ibcon#end of sib2, iclass 25, count 0 2006.253.07:37:10.59#ibcon#*mode == 0, iclass 25, count 0 2006.253.07:37:10.59#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.253.07:37:10.59#ibcon#[25=USB\r\n] 2006.253.07:37:10.59#ibcon#*before write, iclass 25, count 0 2006.253.07:37:10.59#ibcon#enter sib2, iclass 25, count 0 2006.253.07:37:10.59#ibcon#flushed, iclass 25, count 0 2006.253.07:37:10.59#ibcon#about to write, iclass 25, count 0 2006.253.07:37:10.59#ibcon#wrote, iclass 25, count 0 2006.253.07:37:10.59#ibcon#about to read 3, iclass 25, count 0 2006.253.07:37:10.62#ibcon#read 3, iclass 25, count 0 2006.253.07:37:10.62#ibcon#about to read 4, iclass 25, count 0 2006.253.07:37:10.62#ibcon#read 4, iclass 25, count 0 2006.253.07:37:10.62#ibcon#about to read 5, iclass 25, count 0 2006.253.07:37:10.62#ibcon#read 5, iclass 25, count 0 2006.253.07:37:10.62#ibcon#about to read 6, iclass 25, count 0 2006.253.07:37:10.62#ibcon#read 6, iclass 25, count 0 2006.253.07:37:10.62#ibcon#end of sib2, iclass 25, count 0 2006.253.07:37:10.62#ibcon#*after write, iclass 25, count 0 2006.253.07:37:10.62#ibcon#*before return 0, iclass 25, count 0 2006.253.07:37:10.62#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.253.07:37:10.62#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.253.07:37:10.62#ibcon#about to clear, iclass 25 cls_cnt 0 2006.253.07:37:10.62#ibcon#cleared, iclass 25 cls_cnt 0 2006.253.07:37:10.62$vc4f8/vblo=1,632.99 2006.253.07:37:10.62#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.253.07:37:10.62#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.253.07:37:10.62#ibcon#ireg 17 cls_cnt 0 2006.253.07:37:10.62#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.253.07:37:10.62#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.253.07:37:10.62#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.253.07:37:10.62#ibcon#enter wrdev, iclass 27, count 0 2006.253.07:37:10.62#ibcon#first serial, iclass 27, count 0 2006.253.07:37:10.62#ibcon#enter sib2, iclass 27, count 0 2006.253.07:37:10.62#ibcon#flushed, iclass 27, count 0 2006.253.07:37:10.62#ibcon#about to write, iclass 27, count 0 2006.253.07:37:10.62#ibcon#wrote, iclass 27, count 0 2006.253.07:37:10.62#ibcon#about to read 3, iclass 27, count 0 2006.253.07:37:10.64#ibcon#read 3, iclass 27, count 0 2006.253.07:37:10.64#ibcon#about to read 4, iclass 27, count 0 2006.253.07:37:10.64#ibcon#read 4, iclass 27, count 0 2006.253.07:37:10.64#ibcon#about to read 5, iclass 27, count 0 2006.253.07:37:10.64#ibcon#read 5, iclass 27, count 0 2006.253.07:37:10.64#ibcon#about to read 6, iclass 27, count 0 2006.253.07:37:10.64#ibcon#read 6, iclass 27, count 0 2006.253.07:37:10.64#ibcon#end of sib2, iclass 27, count 0 2006.253.07:37:10.64#ibcon#*mode == 0, iclass 27, count 0 2006.253.07:37:10.64#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.253.07:37:10.64#ibcon#[28=FRQ=01,632.99\r\n] 2006.253.07:37:10.64#ibcon#*before write, iclass 27, count 0 2006.253.07:37:10.64#ibcon#enter sib2, iclass 27, count 0 2006.253.07:37:10.64#ibcon#flushed, iclass 27, count 0 2006.253.07:37:10.64#ibcon#about to write, iclass 27, count 0 2006.253.07:37:10.64#ibcon#wrote, iclass 27, count 0 2006.253.07:37:10.64#ibcon#about to read 3, iclass 27, count 0 2006.253.07:37:10.68#ibcon#read 3, iclass 27, count 0 2006.253.07:37:10.68#ibcon#about to read 4, iclass 27, count 0 2006.253.07:37:10.68#ibcon#read 4, iclass 27, count 0 2006.253.07:37:10.68#ibcon#about to read 5, iclass 27, count 0 2006.253.07:37:10.68#ibcon#read 5, iclass 27, count 0 2006.253.07:37:10.68#ibcon#about to read 6, iclass 27, count 0 2006.253.07:37:10.68#ibcon#read 6, iclass 27, count 0 2006.253.07:37:10.68#ibcon#end of sib2, iclass 27, count 0 2006.253.07:37:10.68#ibcon#*after write, iclass 27, count 0 2006.253.07:37:10.68#ibcon#*before return 0, iclass 27, count 0 2006.253.07:37:10.68#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.253.07:37:10.68#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.253.07:37:10.68#ibcon#about to clear, iclass 27 cls_cnt 0 2006.253.07:37:10.68#ibcon#cleared, iclass 27 cls_cnt 0 2006.253.07:37:10.68$vc4f8/vb=1,4 2006.253.07:37:10.68#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.253.07:37:10.68#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.253.07:37:10.68#ibcon#ireg 11 cls_cnt 2 2006.253.07:37:10.68#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.253.07:37:10.68#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.253.07:37:10.68#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.253.07:37:10.68#ibcon#enter wrdev, iclass 29, count 2 2006.253.07:37:10.68#ibcon#first serial, iclass 29, count 2 2006.253.07:37:10.68#ibcon#enter sib2, iclass 29, count 2 2006.253.07:37:10.68#ibcon#flushed, iclass 29, count 2 2006.253.07:37:10.68#ibcon#about to write, iclass 29, count 2 2006.253.07:37:10.68#ibcon#wrote, iclass 29, count 2 2006.253.07:37:10.68#ibcon#about to read 3, iclass 29, count 2 2006.253.07:37:10.70#ibcon#read 3, iclass 29, count 2 2006.253.07:37:10.70#ibcon#about to read 4, iclass 29, count 2 2006.253.07:37:10.70#ibcon#read 4, iclass 29, count 2 2006.253.07:37:10.70#ibcon#about to read 5, iclass 29, count 2 2006.253.07:37:10.70#ibcon#read 5, iclass 29, count 2 2006.253.07:37:10.70#ibcon#about to read 6, iclass 29, count 2 2006.253.07:37:10.70#ibcon#read 6, iclass 29, count 2 2006.253.07:37:10.70#ibcon#end of sib2, iclass 29, count 2 2006.253.07:37:10.70#ibcon#*mode == 0, iclass 29, count 2 2006.253.07:37:10.70#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.253.07:37:10.70#ibcon#[27=AT01-04\r\n] 2006.253.07:37:10.70#ibcon#*before write, iclass 29, count 2 2006.253.07:37:10.70#ibcon#enter sib2, iclass 29, count 2 2006.253.07:37:10.70#ibcon#flushed, iclass 29, count 2 2006.253.07:37:10.70#ibcon#about to write, iclass 29, count 2 2006.253.07:37:10.70#ibcon#wrote, iclass 29, count 2 2006.253.07:37:10.70#ibcon#about to read 3, iclass 29, count 2 2006.253.07:37:10.73#ibcon#read 3, iclass 29, count 2 2006.253.07:37:10.73#ibcon#about to read 4, iclass 29, count 2 2006.253.07:37:10.73#ibcon#read 4, iclass 29, count 2 2006.253.07:37:10.73#ibcon#about to read 5, iclass 29, count 2 2006.253.07:37:10.73#ibcon#read 5, iclass 29, count 2 2006.253.07:37:10.73#ibcon#about to read 6, iclass 29, count 2 2006.253.07:37:10.73#ibcon#read 6, iclass 29, count 2 2006.253.07:37:10.73#ibcon#end of sib2, iclass 29, count 2 2006.253.07:37:10.73#ibcon#*after write, iclass 29, count 2 2006.253.07:37:10.73#ibcon#*before return 0, iclass 29, count 2 2006.253.07:37:10.73#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.253.07:37:10.73#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.253.07:37:10.73#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.253.07:37:10.73#ibcon#ireg 7 cls_cnt 0 2006.253.07:37:10.73#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.253.07:37:10.85#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.253.07:37:10.85#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.253.07:37:10.85#ibcon#enter wrdev, iclass 29, count 0 2006.253.07:37:10.85#ibcon#first serial, iclass 29, count 0 2006.253.07:37:10.85#ibcon#enter sib2, iclass 29, count 0 2006.253.07:37:10.85#ibcon#flushed, iclass 29, count 0 2006.253.07:37:10.85#ibcon#about to write, iclass 29, count 0 2006.253.07:37:10.85#ibcon#wrote, iclass 29, count 0 2006.253.07:37:10.85#ibcon#about to read 3, iclass 29, count 0 2006.253.07:37:10.87#ibcon#read 3, iclass 29, count 0 2006.253.07:37:10.87#ibcon#about to read 4, iclass 29, count 0 2006.253.07:37:10.87#ibcon#read 4, iclass 29, count 0 2006.253.07:37:10.87#ibcon#about to read 5, iclass 29, count 0 2006.253.07:37:10.87#ibcon#read 5, iclass 29, count 0 2006.253.07:37:10.87#ibcon#about to read 6, iclass 29, count 0 2006.253.07:37:10.87#ibcon#read 6, iclass 29, count 0 2006.253.07:37:10.87#ibcon#end of sib2, iclass 29, count 0 2006.253.07:37:10.87#ibcon#*mode == 0, iclass 29, count 0 2006.253.07:37:10.87#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.253.07:37:10.87#ibcon#[27=USB\r\n] 2006.253.07:37:10.87#ibcon#*before write, iclass 29, count 0 2006.253.07:37:10.87#ibcon#enter sib2, iclass 29, count 0 2006.253.07:37:10.87#ibcon#flushed, iclass 29, count 0 2006.253.07:37:10.87#ibcon#about to write, iclass 29, count 0 2006.253.07:37:10.87#ibcon#wrote, iclass 29, count 0 2006.253.07:37:10.87#ibcon#about to read 3, iclass 29, count 0 2006.253.07:37:10.90#ibcon#read 3, iclass 29, count 0 2006.253.07:37:10.90#ibcon#about to read 4, iclass 29, count 0 2006.253.07:37:10.90#ibcon#read 4, iclass 29, count 0 2006.253.07:37:10.90#ibcon#about to read 5, iclass 29, count 0 2006.253.07:37:10.90#ibcon#read 5, iclass 29, count 0 2006.253.07:37:10.90#ibcon#about to read 6, iclass 29, count 0 2006.253.07:37:10.90#ibcon#read 6, iclass 29, count 0 2006.253.07:37:10.90#ibcon#end of sib2, iclass 29, count 0 2006.253.07:37:10.90#ibcon#*after write, iclass 29, count 0 2006.253.07:37:10.90#ibcon#*before return 0, iclass 29, count 0 2006.253.07:37:10.90#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.253.07:37:10.90#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.253.07:37:10.90#ibcon#about to clear, iclass 29 cls_cnt 0 2006.253.07:37:10.90#ibcon#cleared, iclass 29 cls_cnt 0 2006.253.07:37:10.90$vc4f8/vblo=2,640.99 2006.253.07:37:10.90#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.253.07:37:10.90#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.253.07:37:10.90#ibcon#ireg 17 cls_cnt 0 2006.253.07:37:10.90#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.253.07:37:10.90#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.253.07:37:10.90#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.253.07:37:10.90#ibcon#enter wrdev, iclass 31, count 0 2006.253.07:37:10.90#ibcon#first serial, iclass 31, count 0 2006.253.07:37:10.90#ibcon#enter sib2, iclass 31, count 0 2006.253.07:37:10.90#ibcon#flushed, iclass 31, count 0 2006.253.07:37:10.90#ibcon#about to write, iclass 31, count 0 2006.253.07:37:10.90#ibcon#wrote, iclass 31, count 0 2006.253.07:37:10.90#ibcon#about to read 3, iclass 31, count 0 2006.253.07:37:10.92#ibcon#read 3, iclass 31, count 0 2006.253.07:37:10.92#ibcon#about to read 4, iclass 31, count 0 2006.253.07:37:10.92#ibcon#read 4, iclass 31, count 0 2006.253.07:37:10.92#ibcon#about to read 5, iclass 31, count 0 2006.253.07:37:10.92#ibcon#read 5, iclass 31, count 0 2006.253.07:37:10.92#ibcon#about to read 6, iclass 31, count 0 2006.253.07:37:10.92#ibcon#read 6, iclass 31, count 0 2006.253.07:37:10.92#ibcon#end of sib2, iclass 31, count 0 2006.253.07:37:10.92#ibcon#*mode == 0, iclass 31, count 0 2006.253.07:37:10.92#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.253.07:37:10.92#ibcon#[28=FRQ=02,640.99\r\n] 2006.253.07:37:10.92#ibcon#*before write, iclass 31, count 0 2006.253.07:37:10.92#ibcon#enter sib2, iclass 31, count 0 2006.253.07:37:10.92#ibcon#flushed, iclass 31, count 0 2006.253.07:37:10.92#ibcon#about to write, iclass 31, count 0 2006.253.07:37:10.92#ibcon#wrote, iclass 31, count 0 2006.253.07:37:10.92#ibcon#about to read 3, iclass 31, count 0 2006.253.07:37:10.97#ibcon#read 3, iclass 31, count 0 2006.253.07:37:10.97#ibcon#about to read 4, iclass 31, count 0 2006.253.07:37:10.97#ibcon#read 4, iclass 31, count 0 2006.253.07:37:10.97#ibcon#about to read 5, iclass 31, count 0 2006.253.07:37:10.97#ibcon#read 5, iclass 31, count 0 2006.253.07:37:10.97#ibcon#about to read 6, iclass 31, count 0 2006.253.07:37:10.97#ibcon#read 6, iclass 31, count 0 2006.253.07:37:10.97#ibcon#end of sib2, iclass 31, count 0 2006.253.07:37:10.97#ibcon#*after write, iclass 31, count 0 2006.253.07:37:10.97#ibcon#*before return 0, iclass 31, count 0 2006.253.07:37:10.97#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.253.07:37:10.97#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.253.07:37:10.97#ibcon#about to clear, iclass 31 cls_cnt 0 2006.253.07:37:10.97#ibcon#cleared, iclass 31 cls_cnt 0 2006.253.07:37:10.97$vc4f8/vb=2,5 2006.253.07:37:10.97#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.253.07:37:10.97#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.253.07:37:10.97#ibcon#ireg 11 cls_cnt 2 2006.253.07:37:10.97#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.253.07:37:11.02#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.253.07:37:11.02#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.253.07:37:11.02#ibcon#enter wrdev, iclass 33, count 2 2006.253.07:37:11.02#ibcon#first serial, iclass 33, count 2 2006.253.07:37:11.02#ibcon#enter sib2, iclass 33, count 2 2006.253.07:37:11.02#ibcon#flushed, iclass 33, count 2 2006.253.07:37:11.02#ibcon#about to write, iclass 33, count 2 2006.253.07:37:11.02#ibcon#wrote, iclass 33, count 2 2006.253.07:37:11.02#ibcon#about to read 3, iclass 33, count 2 2006.253.07:37:11.04#ibcon#read 3, iclass 33, count 2 2006.253.07:37:11.04#ibcon#about to read 4, iclass 33, count 2 2006.253.07:37:11.04#ibcon#read 4, iclass 33, count 2 2006.253.07:37:11.04#ibcon#about to read 5, iclass 33, count 2 2006.253.07:37:11.04#ibcon#read 5, iclass 33, count 2 2006.253.07:37:11.04#ibcon#about to read 6, iclass 33, count 2 2006.253.07:37:11.04#ibcon#read 6, iclass 33, count 2 2006.253.07:37:11.04#ibcon#end of sib2, iclass 33, count 2 2006.253.07:37:11.04#ibcon#*mode == 0, iclass 33, count 2 2006.253.07:37:11.04#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.253.07:37:11.04#ibcon#[27=AT02-05\r\n] 2006.253.07:37:11.04#ibcon#*before write, iclass 33, count 2 2006.253.07:37:11.04#ibcon#enter sib2, iclass 33, count 2 2006.253.07:37:11.04#ibcon#flushed, iclass 33, count 2 2006.253.07:37:11.04#ibcon#about to write, iclass 33, count 2 2006.253.07:37:11.04#ibcon#wrote, iclass 33, count 2 2006.253.07:37:11.04#ibcon#about to read 3, iclass 33, count 2 2006.253.07:37:11.07#ibcon#read 3, iclass 33, count 2 2006.253.07:37:11.07#ibcon#about to read 4, iclass 33, count 2 2006.253.07:37:11.07#ibcon#read 4, iclass 33, count 2 2006.253.07:37:11.07#ibcon#about to read 5, iclass 33, count 2 2006.253.07:37:11.07#ibcon#read 5, iclass 33, count 2 2006.253.07:37:11.07#ibcon#about to read 6, iclass 33, count 2 2006.253.07:37:11.07#ibcon#read 6, iclass 33, count 2 2006.253.07:37:11.07#ibcon#end of sib2, iclass 33, count 2 2006.253.07:37:11.07#ibcon#*after write, iclass 33, count 2 2006.253.07:37:11.07#ibcon#*before return 0, iclass 33, count 2 2006.253.07:37:11.07#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.253.07:37:11.07#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.253.07:37:11.07#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.253.07:37:11.07#ibcon#ireg 7 cls_cnt 0 2006.253.07:37:11.07#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.253.07:37:11.19#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.253.07:37:11.19#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.253.07:37:11.19#ibcon#enter wrdev, iclass 33, count 0 2006.253.07:37:11.19#ibcon#first serial, iclass 33, count 0 2006.253.07:37:11.19#ibcon#enter sib2, iclass 33, count 0 2006.253.07:37:11.19#ibcon#flushed, iclass 33, count 0 2006.253.07:37:11.19#ibcon#about to write, iclass 33, count 0 2006.253.07:37:11.19#ibcon#wrote, iclass 33, count 0 2006.253.07:37:11.19#ibcon#about to read 3, iclass 33, count 0 2006.253.07:37:11.21#ibcon#read 3, iclass 33, count 0 2006.253.07:37:11.21#ibcon#about to read 4, iclass 33, count 0 2006.253.07:37:11.21#ibcon#read 4, iclass 33, count 0 2006.253.07:37:11.21#ibcon#about to read 5, iclass 33, count 0 2006.253.07:37:11.21#ibcon#read 5, iclass 33, count 0 2006.253.07:37:11.21#ibcon#about to read 6, iclass 33, count 0 2006.253.07:37:11.21#ibcon#read 6, iclass 33, count 0 2006.253.07:37:11.21#ibcon#end of sib2, iclass 33, count 0 2006.253.07:37:11.21#ibcon#*mode == 0, iclass 33, count 0 2006.253.07:37:11.21#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.253.07:37:11.21#ibcon#[27=USB\r\n] 2006.253.07:37:11.21#ibcon#*before write, iclass 33, count 0 2006.253.07:37:11.21#ibcon#enter sib2, iclass 33, count 0 2006.253.07:37:11.21#ibcon#flushed, iclass 33, count 0 2006.253.07:37:11.21#ibcon#about to write, iclass 33, count 0 2006.253.07:37:11.21#ibcon#wrote, iclass 33, count 0 2006.253.07:37:11.21#ibcon#about to read 3, iclass 33, count 0 2006.253.07:37:11.24#ibcon#read 3, iclass 33, count 0 2006.253.07:37:11.24#ibcon#about to read 4, iclass 33, count 0 2006.253.07:37:11.24#ibcon#read 4, iclass 33, count 0 2006.253.07:37:11.24#ibcon#about to read 5, iclass 33, count 0 2006.253.07:37:11.24#ibcon#read 5, iclass 33, count 0 2006.253.07:37:11.24#ibcon#about to read 6, iclass 33, count 0 2006.253.07:37:11.24#ibcon#read 6, iclass 33, count 0 2006.253.07:37:11.24#ibcon#end of sib2, iclass 33, count 0 2006.253.07:37:11.24#ibcon#*after write, iclass 33, count 0 2006.253.07:37:11.24#ibcon#*before return 0, iclass 33, count 0 2006.253.07:37:11.24#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.253.07:37:11.24#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.253.07:37:11.24#ibcon#about to clear, iclass 33 cls_cnt 0 2006.253.07:37:11.24#ibcon#cleared, iclass 33 cls_cnt 0 2006.253.07:37:11.24$vc4f8/vblo=3,656.99 2006.253.07:37:11.24#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.253.07:37:11.24#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.253.07:37:11.24#ibcon#ireg 17 cls_cnt 0 2006.253.07:37:11.24#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.253.07:37:11.24#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.253.07:37:11.24#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.253.07:37:11.24#ibcon#enter wrdev, iclass 35, count 0 2006.253.07:37:11.24#ibcon#first serial, iclass 35, count 0 2006.253.07:37:11.24#ibcon#enter sib2, iclass 35, count 0 2006.253.07:37:11.24#ibcon#flushed, iclass 35, count 0 2006.253.07:37:11.24#ibcon#about to write, iclass 35, count 0 2006.253.07:37:11.24#ibcon#wrote, iclass 35, count 0 2006.253.07:37:11.24#ibcon#about to read 3, iclass 35, count 0 2006.253.07:37:11.26#ibcon#read 3, iclass 35, count 0 2006.253.07:37:11.26#ibcon#about to read 4, iclass 35, count 0 2006.253.07:37:11.26#ibcon#read 4, iclass 35, count 0 2006.253.07:37:11.26#ibcon#about to read 5, iclass 35, count 0 2006.253.07:37:11.26#ibcon#read 5, iclass 35, count 0 2006.253.07:37:11.26#ibcon#about to read 6, iclass 35, count 0 2006.253.07:37:11.26#ibcon#read 6, iclass 35, count 0 2006.253.07:37:11.26#ibcon#end of sib2, iclass 35, count 0 2006.253.07:37:11.26#ibcon#*mode == 0, iclass 35, count 0 2006.253.07:37:11.26#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.253.07:37:11.26#ibcon#[28=FRQ=03,656.99\r\n] 2006.253.07:37:11.26#ibcon#*before write, iclass 35, count 0 2006.253.07:37:11.26#ibcon#enter sib2, iclass 35, count 0 2006.253.07:37:11.26#ibcon#flushed, iclass 35, count 0 2006.253.07:37:11.26#ibcon#about to write, iclass 35, count 0 2006.253.07:37:11.26#ibcon#wrote, iclass 35, count 0 2006.253.07:37:11.26#ibcon#about to read 3, iclass 35, count 0 2006.253.07:37:11.30#ibcon#read 3, iclass 35, count 0 2006.253.07:37:11.30#ibcon#about to read 4, iclass 35, count 0 2006.253.07:37:11.30#ibcon#read 4, iclass 35, count 0 2006.253.07:37:11.30#ibcon#about to read 5, iclass 35, count 0 2006.253.07:37:11.30#ibcon#read 5, iclass 35, count 0 2006.253.07:37:11.30#ibcon#about to read 6, iclass 35, count 0 2006.253.07:37:11.30#ibcon#read 6, iclass 35, count 0 2006.253.07:37:11.30#ibcon#end of sib2, iclass 35, count 0 2006.253.07:37:11.30#ibcon#*after write, iclass 35, count 0 2006.253.07:37:11.30#ibcon#*before return 0, iclass 35, count 0 2006.253.07:37:11.30#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.253.07:37:11.30#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.253.07:37:11.30#ibcon#about to clear, iclass 35 cls_cnt 0 2006.253.07:37:11.30#ibcon#cleared, iclass 35 cls_cnt 0 2006.253.07:37:11.30$vc4f8/vb=3,4 2006.253.07:37:11.30#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.253.07:37:11.30#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.253.07:37:11.30#ibcon#ireg 11 cls_cnt 2 2006.253.07:37:11.30#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.253.07:37:11.36#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.253.07:37:11.36#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.253.07:37:11.36#ibcon#enter wrdev, iclass 37, count 2 2006.253.07:37:11.36#ibcon#first serial, iclass 37, count 2 2006.253.07:37:11.36#ibcon#enter sib2, iclass 37, count 2 2006.253.07:37:11.36#ibcon#flushed, iclass 37, count 2 2006.253.07:37:11.36#ibcon#about to write, iclass 37, count 2 2006.253.07:37:11.36#ibcon#wrote, iclass 37, count 2 2006.253.07:37:11.36#ibcon#about to read 3, iclass 37, count 2 2006.253.07:37:11.38#ibcon#read 3, iclass 37, count 2 2006.253.07:37:11.38#ibcon#about to read 4, iclass 37, count 2 2006.253.07:37:11.38#ibcon#read 4, iclass 37, count 2 2006.253.07:37:11.38#ibcon#about to read 5, iclass 37, count 2 2006.253.07:37:11.38#ibcon#read 5, iclass 37, count 2 2006.253.07:37:11.38#ibcon#about to read 6, iclass 37, count 2 2006.253.07:37:11.38#ibcon#read 6, iclass 37, count 2 2006.253.07:37:11.38#ibcon#end of sib2, iclass 37, count 2 2006.253.07:37:11.38#ibcon#*mode == 0, iclass 37, count 2 2006.253.07:37:11.38#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.253.07:37:11.38#ibcon#[27=AT03-04\r\n] 2006.253.07:37:11.38#ibcon#*before write, iclass 37, count 2 2006.253.07:37:11.38#ibcon#enter sib2, iclass 37, count 2 2006.253.07:37:11.38#ibcon#flushed, iclass 37, count 2 2006.253.07:37:11.38#ibcon#about to write, iclass 37, count 2 2006.253.07:37:11.38#ibcon#wrote, iclass 37, count 2 2006.253.07:37:11.38#ibcon#about to read 3, iclass 37, count 2 2006.253.07:37:11.41#ibcon#read 3, iclass 37, count 2 2006.253.07:37:11.41#ibcon#about to read 4, iclass 37, count 2 2006.253.07:37:11.41#ibcon#read 4, iclass 37, count 2 2006.253.07:37:11.41#ibcon#about to read 5, iclass 37, count 2 2006.253.07:37:11.41#ibcon#read 5, iclass 37, count 2 2006.253.07:37:11.41#ibcon#about to read 6, iclass 37, count 2 2006.253.07:37:11.41#ibcon#read 6, iclass 37, count 2 2006.253.07:37:11.41#ibcon#end of sib2, iclass 37, count 2 2006.253.07:37:11.41#ibcon#*after write, iclass 37, count 2 2006.253.07:37:11.41#ibcon#*before return 0, iclass 37, count 2 2006.253.07:37:11.41#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.253.07:37:11.41#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.253.07:37:11.41#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.253.07:37:11.41#ibcon#ireg 7 cls_cnt 0 2006.253.07:37:11.41#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.253.07:37:11.53#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.253.07:37:11.53#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.253.07:37:11.53#ibcon#enter wrdev, iclass 37, count 0 2006.253.07:37:11.53#ibcon#first serial, iclass 37, count 0 2006.253.07:37:11.53#ibcon#enter sib2, iclass 37, count 0 2006.253.07:37:11.53#ibcon#flushed, iclass 37, count 0 2006.253.07:37:11.53#ibcon#about to write, iclass 37, count 0 2006.253.07:37:11.53#ibcon#wrote, iclass 37, count 0 2006.253.07:37:11.53#ibcon#about to read 3, iclass 37, count 0 2006.253.07:37:11.55#ibcon#read 3, iclass 37, count 0 2006.253.07:37:11.55#ibcon#about to read 4, iclass 37, count 0 2006.253.07:37:11.55#ibcon#read 4, iclass 37, count 0 2006.253.07:37:11.55#ibcon#about to read 5, iclass 37, count 0 2006.253.07:37:11.55#ibcon#read 5, iclass 37, count 0 2006.253.07:37:11.55#ibcon#about to read 6, iclass 37, count 0 2006.253.07:37:11.55#ibcon#read 6, iclass 37, count 0 2006.253.07:37:11.55#ibcon#end of sib2, iclass 37, count 0 2006.253.07:37:11.55#ibcon#*mode == 0, iclass 37, count 0 2006.253.07:37:11.55#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.253.07:37:11.55#ibcon#[27=USB\r\n] 2006.253.07:37:11.55#ibcon#*before write, iclass 37, count 0 2006.253.07:37:11.55#ibcon#enter sib2, iclass 37, count 0 2006.253.07:37:11.55#ibcon#flushed, iclass 37, count 0 2006.253.07:37:11.55#ibcon#about to write, iclass 37, count 0 2006.253.07:37:11.55#ibcon#wrote, iclass 37, count 0 2006.253.07:37:11.55#ibcon#about to read 3, iclass 37, count 0 2006.253.07:37:11.58#ibcon#read 3, iclass 37, count 0 2006.253.07:37:11.58#ibcon#about to read 4, iclass 37, count 0 2006.253.07:37:11.58#ibcon#read 4, iclass 37, count 0 2006.253.07:37:11.58#ibcon#about to read 5, iclass 37, count 0 2006.253.07:37:11.58#ibcon#read 5, iclass 37, count 0 2006.253.07:37:11.58#ibcon#about to read 6, iclass 37, count 0 2006.253.07:37:11.58#ibcon#read 6, iclass 37, count 0 2006.253.07:37:11.58#ibcon#end of sib2, iclass 37, count 0 2006.253.07:37:11.58#ibcon#*after write, iclass 37, count 0 2006.253.07:37:11.58#ibcon#*before return 0, iclass 37, count 0 2006.253.07:37:11.58#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.253.07:37:11.58#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.253.07:37:11.58#ibcon#about to clear, iclass 37 cls_cnt 0 2006.253.07:37:11.58#ibcon#cleared, iclass 37 cls_cnt 0 2006.253.07:37:11.58$vc4f8/vblo=4,712.99 2006.253.07:37:11.58#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.253.07:37:11.58#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.253.07:37:11.58#ibcon#ireg 17 cls_cnt 0 2006.253.07:37:11.58#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.253.07:37:11.58#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.253.07:37:11.58#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.253.07:37:11.58#ibcon#enter wrdev, iclass 39, count 0 2006.253.07:37:11.58#ibcon#first serial, iclass 39, count 0 2006.253.07:37:11.58#ibcon#enter sib2, iclass 39, count 0 2006.253.07:37:11.58#ibcon#flushed, iclass 39, count 0 2006.253.07:37:11.58#ibcon#about to write, iclass 39, count 0 2006.253.07:37:11.58#ibcon#wrote, iclass 39, count 0 2006.253.07:37:11.58#ibcon#about to read 3, iclass 39, count 0 2006.253.07:37:11.60#ibcon#read 3, iclass 39, count 0 2006.253.07:37:11.60#ibcon#about to read 4, iclass 39, count 0 2006.253.07:37:11.60#ibcon#read 4, iclass 39, count 0 2006.253.07:37:11.60#ibcon#about to read 5, iclass 39, count 0 2006.253.07:37:11.60#ibcon#read 5, iclass 39, count 0 2006.253.07:37:11.60#ibcon#about to read 6, iclass 39, count 0 2006.253.07:37:11.60#ibcon#read 6, iclass 39, count 0 2006.253.07:37:11.60#ibcon#end of sib2, iclass 39, count 0 2006.253.07:37:11.60#ibcon#*mode == 0, iclass 39, count 0 2006.253.07:37:11.60#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.253.07:37:11.60#ibcon#[28=FRQ=04,712.99\r\n] 2006.253.07:37:11.60#ibcon#*before write, iclass 39, count 0 2006.253.07:37:11.60#ibcon#enter sib2, iclass 39, count 0 2006.253.07:37:11.60#ibcon#flushed, iclass 39, count 0 2006.253.07:37:11.60#ibcon#about to write, iclass 39, count 0 2006.253.07:37:11.60#ibcon#wrote, iclass 39, count 0 2006.253.07:37:11.60#ibcon#about to read 3, iclass 39, count 0 2006.253.07:37:11.64#ibcon#read 3, iclass 39, count 0 2006.253.07:37:11.64#ibcon#about to read 4, iclass 39, count 0 2006.253.07:37:11.64#ibcon#read 4, iclass 39, count 0 2006.253.07:37:11.64#ibcon#about to read 5, iclass 39, count 0 2006.253.07:37:11.64#ibcon#read 5, iclass 39, count 0 2006.253.07:37:11.64#ibcon#about to read 6, iclass 39, count 0 2006.253.07:37:11.64#ibcon#read 6, iclass 39, count 0 2006.253.07:37:11.64#ibcon#end of sib2, iclass 39, count 0 2006.253.07:37:11.64#ibcon#*after write, iclass 39, count 0 2006.253.07:37:11.64#ibcon#*before return 0, iclass 39, count 0 2006.253.07:37:11.64#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.253.07:37:11.64#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.253.07:37:11.64#ibcon#about to clear, iclass 39 cls_cnt 0 2006.253.07:37:11.64#ibcon#cleared, iclass 39 cls_cnt 0 2006.253.07:37:11.64$vc4f8/vb=4,4 2006.253.07:37:11.64#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.253.07:37:11.64#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.253.07:37:11.64#ibcon#ireg 11 cls_cnt 2 2006.253.07:37:11.64#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.253.07:37:11.70#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.253.07:37:11.70#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.253.07:37:11.70#ibcon#enter wrdev, iclass 3, count 2 2006.253.07:37:11.70#ibcon#first serial, iclass 3, count 2 2006.253.07:37:11.70#ibcon#enter sib2, iclass 3, count 2 2006.253.07:37:11.70#ibcon#flushed, iclass 3, count 2 2006.253.07:37:11.70#ibcon#about to write, iclass 3, count 2 2006.253.07:37:11.70#ibcon#wrote, iclass 3, count 2 2006.253.07:37:11.70#ibcon#about to read 3, iclass 3, count 2 2006.253.07:37:11.72#ibcon#read 3, iclass 3, count 2 2006.253.07:37:11.72#ibcon#about to read 4, iclass 3, count 2 2006.253.07:37:11.72#ibcon#read 4, iclass 3, count 2 2006.253.07:37:11.72#ibcon#about to read 5, iclass 3, count 2 2006.253.07:37:11.72#ibcon#read 5, iclass 3, count 2 2006.253.07:37:11.72#ibcon#about to read 6, iclass 3, count 2 2006.253.07:37:11.72#ibcon#read 6, iclass 3, count 2 2006.253.07:37:11.72#ibcon#end of sib2, iclass 3, count 2 2006.253.07:37:11.72#ibcon#*mode == 0, iclass 3, count 2 2006.253.07:37:11.72#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.253.07:37:11.72#ibcon#[27=AT04-04\r\n] 2006.253.07:37:11.72#ibcon#*before write, iclass 3, count 2 2006.253.07:37:11.72#ibcon#enter sib2, iclass 3, count 2 2006.253.07:37:11.72#ibcon#flushed, iclass 3, count 2 2006.253.07:37:11.72#ibcon#about to write, iclass 3, count 2 2006.253.07:37:11.72#ibcon#wrote, iclass 3, count 2 2006.253.07:37:11.72#ibcon#about to read 3, iclass 3, count 2 2006.253.07:37:11.75#ibcon#read 3, iclass 3, count 2 2006.253.07:37:11.75#ibcon#about to read 4, iclass 3, count 2 2006.253.07:37:11.75#ibcon#read 4, iclass 3, count 2 2006.253.07:37:11.75#ibcon#about to read 5, iclass 3, count 2 2006.253.07:37:11.75#ibcon#read 5, iclass 3, count 2 2006.253.07:37:11.75#ibcon#about to read 6, iclass 3, count 2 2006.253.07:37:11.75#ibcon#read 6, iclass 3, count 2 2006.253.07:37:11.75#ibcon#end of sib2, iclass 3, count 2 2006.253.07:37:11.75#ibcon#*after write, iclass 3, count 2 2006.253.07:37:11.75#ibcon#*before return 0, iclass 3, count 2 2006.253.07:37:11.75#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.253.07:37:11.75#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.253.07:37:11.75#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.253.07:37:11.75#ibcon#ireg 7 cls_cnt 0 2006.253.07:37:11.75#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.253.07:37:11.87#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.253.07:37:11.87#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.253.07:37:11.87#ibcon#enter wrdev, iclass 3, count 0 2006.253.07:37:11.87#ibcon#first serial, iclass 3, count 0 2006.253.07:37:11.87#ibcon#enter sib2, iclass 3, count 0 2006.253.07:37:11.87#ibcon#flushed, iclass 3, count 0 2006.253.07:37:11.87#ibcon#about to write, iclass 3, count 0 2006.253.07:37:11.87#ibcon#wrote, iclass 3, count 0 2006.253.07:37:11.87#ibcon#about to read 3, iclass 3, count 0 2006.253.07:37:11.89#ibcon#read 3, iclass 3, count 0 2006.253.07:37:11.89#ibcon#about to read 4, iclass 3, count 0 2006.253.07:37:11.89#ibcon#read 4, iclass 3, count 0 2006.253.07:37:11.89#ibcon#about to read 5, iclass 3, count 0 2006.253.07:37:11.89#ibcon#read 5, iclass 3, count 0 2006.253.07:37:11.89#ibcon#about to read 6, iclass 3, count 0 2006.253.07:37:11.89#ibcon#read 6, iclass 3, count 0 2006.253.07:37:11.89#ibcon#end of sib2, iclass 3, count 0 2006.253.07:37:11.89#ibcon#*mode == 0, iclass 3, count 0 2006.253.07:37:11.89#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.253.07:37:11.89#ibcon#[27=USB\r\n] 2006.253.07:37:11.89#ibcon#*before write, iclass 3, count 0 2006.253.07:37:11.89#ibcon#enter sib2, iclass 3, count 0 2006.253.07:37:11.89#ibcon#flushed, iclass 3, count 0 2006.253.07:37:11.89#ibcon#about to write, iclass 3, count 0 2006.253.07:37:11.89#ibcon#wrote, iclass 3, count 0 2006.253.07:37:11.89#ibcon#about to read 3, iclass 3, count 0 2006.253.07:37:11.92#ibcon#read 3, iclass 3, count 0 2006.253.07:37:11.92#ibcon#about to read 4, iclass 3, count 0 2006.253.07:37:11.92#ibcon#read 4, iclass 3, count 0 2006.253.07:37:11.92#ibcon#about to read 5, iclass 3, count 0 2006.253.07:37:11.92#ibcon#read 5, iclass 3, count 0 2006.253.07:37:11.92#ibcon#about to read 6, iclass 3, count 0 2006.253.07:37:11.92#ibcon#read 6, iclass 3, count 0 2006.253.07:37:11.92#ibcon#end of sib2, iclass 3, count 0 2006.253.07:37:11.92#ibcon#*after write, iclass 3, count 0 2006.253.07:37:11.92#ibcon#*before return 0, iclass 3, count 0 2006.253.07:37:11.92#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.253.07:37:11.92#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.253.07:37:11.92#ibcon#about to clear, iclass 3 cls_cnt 0 2006.253.07:37:11.92#ibcon#cleared, iclass 3 cls_cnt 0 2006.253.07:37:11.92$vc4f8/vblo=5,744.99 2006.253.07:37:11.92#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.253.07:37:11.92#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.253.07:37:11.92#ibcon#ireg 17 cls_cnt 0 2006.253.07:37:11.92#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.253.07:37:11.92#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.253.07:37:11.92#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.253.07:37:11.92#ibcon#enter wrdev, iclass 5, count 0 2006.253.07:37:11.92#ibcon#first serial, iclass 5, count 0 2006.253.07:37:11.92#ibcon#enter sib2, iclass 5, count 0 2006.253.07:37:11.92#ibcon#flushed, iclass 5, count 0 2006.253.07:37:11.92#ibcon#about to write, iclass 5, count 0 2006.253.07:37:11.92#ibcon#wrote, iclass 5, count 0 2006.253.07:37:11.92#ibcon#about to read 3, iclass 5, count 0 2006.253.07:37:11.94#ibcon#read 3, iclass 5, count 0 2006.253.07:37:11.94#ibcon#about to read 4, iclass 5, count 0 2006.253.07:37:11.94#ibcon#read 4, iclass 5, count 0 2006.253.07:37:11.94#ibcon#about to read 5, iclass 5, count 0 2006.253.07:37:11.94#ibcon#read 5, iclass 5, count 0 2006.253.07:37:11.94#ibcon#about to read 6, iclass 5, count 0 2006.253.07:37:11.94#ibcon#read 6, iclass 5, count 0 2006.253.07:37:11.94#ibcon#end of sib2, iclass 5, count 0 2006.253.07:37:11.94#ibcon#*mode == 0, iclass 5, count 0 2006.253.07:37:11.94#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.253.07:37:11.94#ibcon#[28=FRQ=05,744.99\r\n] 2006.253.07:37:11.94#ibcon#*before write, iclass 5, count 0 2006.253.07:37:11.94#ibcon#enter sib2, iclass 5, count 0 2006.253.07:37:11.94#ibcon#flushed, iclass 5, count 0 2006.253.07:37:11.94#ibcon#about to write, iclass 5, count 0 2006.253.07:37:11.94#ibcon#wrote, iclass 5, count 0 2006.253.07:37:11.94#ibcon#about to read 3, iclass 5, count 0 2006.253.07:37:11.98#ibcon#read 3, iclass 5, count 0 2006.253.07:37:11.98#ibcon#about to read 4, iclass 5, count 0 2006.253.07:37:11.98#ibcon#read 4, iclass 5, count 0 2006.253.07:37:11.98#ibcon#about to read 5, iclass 5, count 0 2006.253.07:37:11.98#ibcon#read 5, iclass 5, count 0 2006.253.07:37:11.98#ibcon#about to read 6, iclass 5, count 0 2006.253.07:37:11.98#ibcon#read 6, iclass 5, count 0 2006.253.07:37:11.98#ibcon#end of sib2, iclass 5, count 0 2006.253.07:37:11.98#ibcon#*after write, iclass 5, count 0 2006.253.07:37:11.98#ibcon#*before return 0, iclass 5, count 0 2006.253.07:37:11.98#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.253.07:37:11.98#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.253.07:37:11.98#ibcon#about to clear, iclass 5 cls_cnt 0 2006.253.07:37:11.98#ibcon#cleared, iclass 5 cls_cnt 0 2006.253.07:37:11.98$vc4f8/vb=5,4 2006.253.07:37:11.98#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.253.07:37:11.98#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.253.07:37:11.98#ibcon#ireg 11 cls_cnt 2 2006.253.07:37:11.98#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.253.07:37:12.04#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.253.07:37:12.04#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.253.07:37:12.04#ibcon#enter wrdev, iclass 7, count 2 2006.253.07:37:12.04#ibcon#first serial, iclass 7, count 2 2006.253.07:37:12.04#ibcon#enter sib2, iclass 7, count 2 2006.253.07:37:12.04#ibcon#flushed, iclass 7, count 2 2006.253.07:37:12.04#ibcon#about to write, iclass 7, count 2 2006.253.07:37:12.04#ibcon#wrote, iclass 7, count 2 2006.253.07:37:12.04#ibcon#about to read 3, iclass 7, count 2 2006.253.07:37:12.06#ibcon#read 3, iclass 7, count 2 2006.253.07:37:12.06#ibcon#about to read 4, iclass 7, count 2 2006.253.07:37:12.06#ibcon#read 4, iclass 7, count 2 2006.253.07:37:12.06#ibcon#about to read 5, iclass 7, count 2 2006.253.07:37:12.06#ibcon#read 5, iclass 7, count 2 2006.253.07:37:12.06#ibcon#about to read 6, iclass 7, count 2 2006.253.07:37:12.06#ibcon#read 6, iclass 7, count 2 2006.253.07:37:12.06#ibcon#end of sib2, iclass 7, count 2 2006.253.07:37:12.06#ibcon#*mode == 0, iclass 7, count 2 2006.253.07:37:12.06#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.253.07:37:12.06#ibcon#[27=AT05-04\r\n] 2006.253.07:37:12.06#ibcon#*before write, iclass 7, count 2 2006.253.07:37:12.06#ibcon#enter sib2, iclass 7, count 2 2006.253.07:37:12.06#ibcon#flushed, iclass 7, count 2 2006.253.07:37:12.06#ibcon#about to write, iclass 7, count 2 2006.253.07:37:12.06#ibcon#wrote, iclass 7, count 2 2006.253.07:37:12.06#ibcon#about to read 3, iclass 7, count 2 2006.253.07:37:12.09#ibcon#read 3, iclass 7, count 2 2006.253.07:37:12.09#ibcon#about to read 4, iclass 7, count 2 2006.253.07:37:12.09#ibcon#read 4, iclass 7, count 2 2006.253.07:37:12.09#ibcon#about to read 5, iclass 7, count 2 2006.253.07:37:12.09#ibcon#read 5, iclass 7, count 2 2006.253.07:37:12.09#ibcon#about to read 6, iclass 7, count 2 2006.253.07:37:12.09#ibcon#read 6, iclass 7, count 2 2006.253.07:37:12.09#ibcon#end of sib2, iclass 7, count 2 2006.253.07:37:12.09#ibcon#*after write, iclass 7, count 2 2006.253.07:37:12.09#ibcon#*before return 0, iclass 7, count 2 2006.253.07:37:12.09#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.253.07:37:12.09#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.253.07:37:12.09#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.253.07:37:12.09#ibcon#ireg 7 cls_cnt 0 2006.253.07:37:12.09#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.253.07:37:12.21#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.253.07:37:12.21#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.253.07:37:12.21#ibcon#enter wrdev, iclass 7, count 0 2006.253.07:37:12.21#ibcon#first serial, iclass 7, count 0 2006.253.07:37:12.21#ibcon#enter sib2, iclass 7, count 0 2006.253.07:37:12.21#ibcon#flushed, iclass 7, count 0 2006.253.07:37:12.21#ibcon#about to write, iclass 7, count 0 2006.253.07:37:12.21#ibcon#wrote, iclass 7, count 0 2006.253.07:37:12.21#ibcon#about to read 3, iclass 7, count 0 2006.253.07:37:12.23#ibcon#read 3, iclass 7, count 0 2006.253.07:37:12.23#ibcon#about to read 4, iclass 7, count 0 2006.253.07:37:12.23#ibcon#read 4, iclass 7, count 0 2006.253.07:37:12.23#ibcon#about to read 5, iclass 7, count 0 2006.253.07:37:12.23#ibcon#read 5, iclass 7, count 0 2006.253.07:37:12.23#ibcon#about to read 6, iclass 7, count 0 2006.253.07:37:12.23#ibcon#read 6, iclass 7, count 0 2006.253.07:37:12.23#ibcon#end of sib2, iclass 7, count 0 2006.253.07:37:12.23#ibcon#*mode == 0, iclass 7, count 0 2006.253.07:37:12.23#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.253.07:37:12.23#ibcon#[27=USB\r\n] 2006.253.07:37:12.23#ibcon#*before write, iclass 7, count 0 2006.253.07:37:12.23#ibcon#enter sib2, iclass 7, count 0 2006.253.07:37:12.23#ibcon#flushed, iclass 7, count 0 2006.253.07:37:12.23#ibcon#about to write, iclass 7, count 0 2006.253.07:37:12.23#ibcon#wrote, iclass 7, count 0 2006.253.07:37:12.23#ibcon#about to read 3, iclass 7, count 0 2006.253.07:37:12.26#ibcon#read 3, iclass 7, count 0 2006.253.07:37:12.26#ibcon#about to read 4, iclass 7, count 0 2006.253.07:37:12.26#ibcon#read 4, iclass 7, count 0 2006.253.07:37:12.26#ibcon#about to read 5, iclass 7, count 0 2006.253.07:37:12.26#ibcon#read 5, iclass 7, count 0 2006.253.07:37:12.26#ibcon#about to read 6, iclass 7, count 0 2006.253.07:37:12.26#ibcon#read 6, iclass 7, count 0 2006.253.07:37:12.26#ibcon#end of sib2, iclass 7, count 0 2006.253.07:37:12.26#ibcon#*after write, iclass 7, count 0 2006.253.07:37:12.26#ibcon#*before return 0, iclass 7, count 0 2006.253.07:37:12.26#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.253.07:37:12.26#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.253.07:37:12.26#ibcon#about to clear, iclass 7 cls_cnt 0 2006.253.07:37:12.26#ibcon#cleared, iclass 7 cls_cnt 0 2006.253.07:37:12.26$vc4f8/vblo=6,752.99 2006.253.07:37:12.26#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.253.07:37:12.26#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.253.07:37:12.26#ibcon#ireg 17 cls_cnt 0 2006.253.07:37:12.26#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.253.07:37:12.26#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.253.07:37:12.26#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.253.07:37:12.26#ibcon#enter wrdev, iclass 11, count 0 2006.253.07:37:12.26#ibcon#first serial, iclass 11, count 0 2006.253.07:37:12.26#ibcon#enter sib2, iclass 11, count 0 2006.253.07:37:12.26#ibcon#flushed, iclass 11, count 0 2006.253.07:37:12.26#ibcon#about to write, iclass 11, count 0 2006.253.07:37:12.26#ibcon#wrote, iclass 11, count 0 2006.253.07:37:12.26#ibcon#about to read 3, iclass 11, count 0 2006.253.07:37:12.28#ibcon#read 3, iclass 11, count 0 2006.253.07:37:12.28#ibcon#about to read 4, iclass 11, count 0 2006.253.07:37:12.28#ibcon#read 4, iclass 11, count 0 2006.253.07:37:12.28#ibcon#about to read 5, iclass 11, count 0 2006.253.07:37:12.28#ibcon#read 5, iclass 11, count 0 2006.253.07:37:12.28#ibcon#about to read 6, iclass 11, count 0 2006.253.07:37:12.28#ibcon#read 6, iclass 11, count 0 2006.253.07:37:12.28#ibcon#end of sib2, iclass 11, count 0 2006.253.07:37:12.28#ibcon#*mode == 0, iclass 11, count 0 2006.253.07:37:12.28#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.253.07:37:12.28#ibcon#[28=FRQ=06,752.99\r\n] 2006.253.07:37:12.28#ibcon#*before write, iclass 11, count 0 2006.253.07:37:12.28#ibcon#enter sib2, iclass 11, count 0 2006.253.07:37:12.28#ibcon#flushed, iclass 11, count 0 2006.253.07:37:12.28#ibcon#about to write, iclass 11, count 0 2006.253.07:37:12.28#ibcon#wrote, iclass 11, count 0 2006.253.07:37:12.28#ibcon#about to read 3, iclass 11, count 0 2006.253.07:37:12.32#ibcon#read 3, iclass 11, count 0 2006.253.07:37:12.32#ibcon#about to read 4, iclass 11, count 0 2006.253.07:37:12.32#ibcon#read 4, iclass 11, count 0 2006.253.07:37:12.32#ibcon#about to read 5, iclass 11, count 0 2006.253.07:37:12.32#ibcon#read 5, iclass 11, count 0 2006.253.07:37:12.32#ibcon#about to read 6, iclass 11, count 0 2006.253.07:37:12.32#ibcon#read 6, iclass 11, count 0 2006.253.07:37:12.32#ibcon#end of sib2, iclass 11, count 0 2006.253.07:37:12.32#ibcon#*after write, iclass 11, count 0 2006.253.07:37:12.32#ibcon#*before return 0, iclass 11, count 0 2006.253.07:37:12.32#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.253.07:37:12.32#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.253.07:37:12.32#ibcon#about to clear, iclass 11 cls_cnt 0 2006.253.07:37:12.32#ibcon#cleared, iclass 11 cls_cnt 0 2006.253.07:37:12.32$vc4f8/vb=6,4 2006.253.07:37:12.32#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.253.07:37:12.32#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.253.07:37:12.32#ibcon#ireg 11 cls_cnt 2 2006.253.07:37:12.32#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.253.07:37:12.38#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.253.07:37:12.38#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.253.07:37:12.38#ibcon#enter wrdev, iclass 13, count 2 2006.253.07:37:12.38#ibcon#first serial, iclass 13, count 2 2006.253.07:37:12.38#ibcon#enter sib2, iclass 13, count 2 2006.253.07:37:12.38#ibcon#flushed, iclass 13, count 2 2006.253.07:37:12.38#ibcon#about to write, iclass 13, count 2 2006.253.07:37:12.38#ibcon#wrote, iclass 13, count 2 2006.253.07:37:12.38#ibcon#about to read 3, iclass 13, count 2 2006.253.07:37:12.40#ibcon#read 3, iclass 13, count 2 2006.253.07:37:12.40#ibcon#about to read 4, iclass 13, count 2 2006.253.07:37:12.40#ibcon#read 4, iclass 13, count 2 2006.253.07:37:12.40#ibcon#about to read 5, iclass 13, count 2 2006.253.07:37:12.40#ibcon#read 5, iclass 13, count 2 2006.253.07:37:12.40#ibcon#about to read 6, iclass 13, count 2 2006.253.07:37:12.40#ibcon#read 6, iclass 13, count 2 2006.253.07:37:12.40#ibcon#end of sib2, iclass 13, count 2 2006.253.07:37:12.40#ibcon#*mode == 0, iclass 13, count 2 2006.253.07:37:12.40#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.253.07:37:12.40#ibcon#[27=AT06-04\r\n] 2006.253.07:37:12.40#ibcon#*before write, iclass 13, count 2 2006.253.07:37:12.40#ibcon#enter sib2, iclass 13, count 2 2006.253.07:37:12.40#ibcon#flushed, iclass 13, count 2 2006.253.07:37:12.40#ibcon#about to write, iclass 13, count 2 2006.253.07:37:12.40#ibcon#wrote, iclass 13, count 2 2006.253.07:37:12.40#ibcon#about to read 3, iclass 13, count 2 2006.253.07:37:12.43#ibcon#read 3, iclass 13, count 2 2006.253.07:37:12.43#ibcon#about to read 4, iclass 13, count 2 2006.253.07:37:12.43#ibcon#read 4, iclass 13, count 2 2006.253.07:37:12.43#ibcon#about to read 5, iclass 13, count 2 2006.253.07:37:12.43#ibcon#read 5, iclass 13, count 2 2006.253.07:37:12.43#ibcon#about to read 6, iclass 13, count 2 2006.253.07:37:12.43#ibcon#read 6, iclass 13, count 2 2006.253.07:37:12.43#ibcon#end of sib2, iclass 13, count 2 2006.253.07:37:12.43#ibcon#*after write, iclass 13, count 2 2006.253.07:37:12.43#ibcon#*before return 0, iclass 13, count 2 2006.253.07:37:12.43#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.253.07:37:12.43#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.253.07:37:12.43#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.253.07:37:12.43#ibcon#ireg 7 cls_cnt 0 2006.253.07:37:12.43#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.253.07:37:12.55#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.253.07:37:12.55#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.253.07:37:12.55#ibcon#enter wrdev, iclass 13, count 0 2006.253.07:37:12.55#ibcon#first serial, iclass 13, count 0 2006.253.07:37:12.55#ibcon#enter sib2, iclass 13, count 0 2006.253.07:37:12.55#ibcon#flushed, iclass 13, count 0 2006.253.07:37:12.55#ibcon#about to write, iclass 13, count 0 2006.253.07:37:12.55#ibcon#wrote, iclass 13, count 0 2006.253.07:37:12.55#ibcon#about to read 3, iclass 13, count 0 2006.253.07:37:12.57#ibcon#read 3, iclass 13, count 0 2006.253.07:37:12.57#ibcon#about to read 4, iclass 13, count 0 2006.253.07:37:12.57#ibcon#read 4, iclass 13, count 0 2006.253.07:37:12.57#ibcon#about to read 5, iclass 13, count 0 2006.253.07:37:12.57#ibcon#read 5, iclass 13, count 0 2006.253.07:37:12.57#ibcon#about to read 6, iclass 13, count 0 2006.253.07:37:12.57#ibcon#read 6, iclass 13, count 0 2006.253.07:37:12.57#ibcon#end of sib2, iclass 13, count 0 2006.253.07:37:12.57#ibcon#*mode == 0, iclass 13, count 0 2006.253.07:37:12.57#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.253.07:37:12.57#ibcon#[27=USB\r\n] 2006.253.07:37:12.57#ibcon#*before write, iclass 13, count 0 2006.253.07:37:12.57#ibcon#enter sib2, iclass 13, count 0 2006.253.07:37:12.57#ibcon#flushed, iclass 13, count 0 2006.253.07:37:12.57#ibcon#about to write, iclass 13, count 0 2006.253.07:37:12.57#ibcon#wrote, iclass 13, count 0 2006.253.07:37:12.57#ibcon#about to read 3, iclass 13, count 0 2006.253.07:37:12.60#ibcon#read 3, iclass 13, count 0 2006.253.07:37:12.60#ibcon#about to read 4, iclass 13, count 0 2006.253.07:37:12.60#ibcon#read 4, iclass 13, count 0 2006.253.07:37:12.60#ibcon#about to read 5, iclass 13, count 0 2006.253.07:37:12.60#ibcon#read 5, iclass 13, count 0 2006.253.07:37:12.60#ibcon#about to read 6, iclass 13, count 0 2006.253.07:37:12.60#ibcon#read 6, iclass 13, count 0 2006.253.07:37:12.60#ibcon#end of sib2, iclass 13, count 0 2006.253.07:37:12.60#ibcon#*after write, iclass 13, count 0 2006.253.07:37:12.60#ibcon#*before return 0, iclass 13, count 0 2006.253.07:37:12.60#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.253.07:37:12.60#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.253.07:37:12.60#ibcon#about to clear, iclass 13 cls_cnt 0 2006.253.07:37:12.60#ibcon#cleared, iclass 13 cls_cnt 0 2006.253.07:37:12.60$vc4f8/vabw=wide 2006.253.07:37:12.60#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.253.07:37:12.60#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.253.07:37:12.60#ibcon#ireg 8 cls_cnt 0 2006.253.07:37:12.60#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.253.07:37:12.60#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.253.07:37:12.60#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.253.07:37:12.60#ibcon#enter wrdev, iclass 15, count 0 2006.253.07:37:12.60#ibcon#first serial, iclass 15, count 0 2006.253.07:37:12.60#ibcon#enter sib2, iclass 15, count 0 2006.253.07:37:12.60#ibcon#flushed, iclass 15, count 0 2006.253.07:37:12.60#ibcon#about to write, iclass 15, count 0 2006.253.07:37:12.60#ibcon#wrote, iclass 15, count 0 2006.253.07:37:12.60#ibcon#about to read 3, iclass 15, count 0 2006.253.07:37:12.62#ibcon#read 3, iclass 15, count 0 2006.253.07:37:12.62#ibcon#about to read 4, iclass 15, count 0 2006.253.07:37:12.62#ibcon#read 4, iclass 15, count 0 2006.253.07:37:12.62#ibcon#about to read 5, iclass 15, count 0 2006.253.07:37:12.62#ibcon#read 5, iclass 15, count 0 2006.253.07:37:12.62#ibcon#about to read 6, iclass 15, count 0 2006.253.07:37:12.62#ibcon#read 6, iclass 15, count 0 2006.253.07:37:12.62#ibcon#end of sib2, iclass 15, count 0 2006.253.07:37:12.62#ibcon#*mode == 0, iclass 15, count 0 2006.253.07:37:12.62#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.253.07:37:12.62#ibcon#[25=BW32\r\n] 2006.253.07:37:12.62#ibcon#*before write, iclass 15, count 0 2006.253.07:37:12.62#ibcon#enter sib2, iclass 15, count 0 2006.253.07:37:12.62#ibcon#flushed, iclass 15, count 0 2006.253.07:37:12.62#ibcon#about to write, iclass 15, count 0 2006.253.07:37:12.62#ibcon#wrote, iclass 15, count 0 2006.253.07:37:12.62#ibcon#about to read 3, iclass 15, count 0 2006.253.07:37:12.66#ibcon#read 3, iclass 15, count 0 2006.253.07:37:12.66#ibcon#about to read 4, iclass 15, count 0 2006.253.07:37:12.66#ibcon#read 4, iclass 15, count 0 2006.253.07:37:12.66#ibcon#about to read 5, iclass 15, count 0 2006.253.07:37:12.66#ibcon#read 5, iclass 15, count 0 2006.253.07:37:12.66#ibcon#about to read 6, iclass 15, count 0 2006.253.07:37:12.66#ibcon#read 6, iclass 15, count 0 2006.253.07:37:12.66#ibcon#end of sib2, iclass 15, count 0 2006.253.07:37:12.66#ibcon#*after write, iclass 15, count 0 2006.253.07:37:12.66#ibcon#*before return 0, iclass 15, count 0 2006.253.07:37:12.66#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.253.07:37:12.66#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.253.07:37:12.66#ibcon#about to clear, iclass 15 cls_cnt 0 2006.253.07:37:12.66#ibcon#cleared, iclass 15 cls_cnt 0 2006.253.07:37:12.66$vc4f8/vbbw=wide 2006.253.07:37:12.66#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.253.07:37:12.66#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.253.07:37:12.66#ibcon#ireg 8 cls_cnt 0 2006.253.07:37:12.66#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.253.07:37:12.72#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.253.07:37:12.72#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.253.07:37:12.72#ibcon#enter wrdev, iclass 17, count 0 2006.253.07:37:12.72#ibcon#first serial, iclass 17, count 0 2006.253.07:37:12.72#ibcon#enter sib2, iclass 17, count 0 2006.253.07:37:12.72#ibcon#flushed, iclass 17, count 0 2006.253.07:37:12.72#ibcon#about to write, iclass 17, count 0 2006.253.07:37:12.72#ibcon#wrote, iclass 17, count 0 2006.253.07:37:12.72#ibcon#about to read 3, iclass 17, count 0 2006.253.07:37:12.74#ibcon#read 3, iclass 17, count 0 2006.253.07:37:12.74#ibcon#about to read 4, iclass 17, count 0 2006.253.07:37:12.74#ibcon#read 4, iclass 17, count 0 2006.253.07:37:12.74#ibcon#about to read 5, iclass 17, count 0 2006.253.07:37:12.74#ibcon#read 5, iclass 17, count 0 2006.253.07:37:12.74#ibcon#about to read 6, iclass 17, count 0 2006.253.07:37:12.74#ibcon#read 6, iclass 17, count 0 2006.253.07:37:12.74#ibcon#end of sib2, iclass 17, count 0 2006.253.07:37:12.74#ibcon#*mode == 0, iclass 17, count 0 2006.253.07:37:12.74#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.253.07:37:12.74#ibcon#[27=BW32\r\n] 2006.253.07:37:12.74#ibcon#*before write, iclass 17, count 0 2006.253.07:37:12.74#ibcon#enter sib2, iclass 17, count 0 2006.253.07:37:12.74#ibcon#flushed, iclass 17, count 0 2006.253.07:37:12.74#ibcon#about to write, iclass 17, count 0 2006.253.07:37:12.74#ibcon#wrote, iclass 17, count 0 2006.253.07:37:12.74#ibcon#about to read 3, iclass 17, count 0 2006.253.07:37:12.77#ibcon#read 3, iclass 17, count 0 2006.253.07:37:12.77#ibcon#about to read 4, iclass 17, count 0 2006.253.07:37:12.77#ibcon#read 4, iclass 17, count 0 2006.253.07:37:12.77#ibcon#about to read 5, iclass 17, count 0 2006.253.07:37:12.77#ibcon#read 5, iclass 17, count 0 2006.253.07:37:12.77#ibcon#about to read 6, iclass 17, count 0 2006.253.07:37:12.77#ibcon#read 6, iclass 17, count 0 2006.253.07:37:12.77#ibcon#end of sib2, iclass 17, count 0 2006.253.07:37:12.77#ibcon#*after write, iclass 17, count 0 2006.253.07:37:12.77#ibcon#*before return 0, iclass 17, count 0 2006.253.07:37:12.77#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.253.07:37:12.77#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.253.07:37:12.77#ibcon#about to clear, iclass 17 cls_cnt 0 2006.253.07:37:12.77#ibcon#cleared, iclass 17 cls_cnt 0 2006.253.07:37:12.77$4f8m12a/ifd4f 2006.253.07:37:12.77$ifd4f/lo= 2006.253.07:37:12.77$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.253.07:37:12.77$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.253.07:37:12.77$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.253.07:37:12.77$ifd4f/patch= 2006.253.07:37:12.77$ifd4f/patch=lo1,a1,a2,a3,a4 2006.253.07:37:12.77$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.253.07:37:12.77$ifd4f/patch=lo3,a5,a6,a7,a8 2006.253.07:37:12.77$4f8m12a/"form=m,16.000,1:2 2006.253.07:37:12.77$4f8m12a/"tpicd 2006.253.07:37:12.77$4f8m12a/echo=off 2006.253.07:37:12.77$4f8m12a/xlog=off 2006.253.07:37:12.77:!2006.253.07:37:40 2006.253.07:37:26.13#trakl#Source acquired 2006.253.07:37:28.13#flagr#flagr/antenna,acquired 2006.253.07:37:40.00:preob 2006.253.07:37:41.13/onsource/TRACKING 2006.253.07:37:41.13:!2006.253.07:37:50 2006.253.07:37:50.00:data_valid=on 2006.253.07:37:50.00:midob 2006.253.07:37:50.13/onsource/TRACKING 2006.253.07:37:50.13/wx/31.52,1006.3,73 2006.253.07:37:50.24/cable/+6.3686E-03 2006.253.07:37:51.33/va/01,08,usb,yes,36,38 2006.253.07:37:51.33/va/02,07,usb,yes,36,38 2006.253.07:37:51.33/va/03,06,usb,yes,38,39 2006.253.07:37:51.33/va/04,07,usb,yes,37,41 2006.253.07:37:51.33/va/05,07,usb,yes,39,41 2006.253.07:37:51.33/va/06,07,usb,yes,34,34 2006.253.07:37:51.33/va/07,07,usb,yes,34,34 2006.253.07:37:51.33/va/08,07,usb,yes,37,36 2006.253.07:37:51.56/valo/01,532.99,yes,locked 2006.253.07:37:51.56/valo/02,572.99,yes,locked 2006.253.07:37:51.56/valo/03,672.99,yes,locked 2006.253.07:37:51.56/valo/04,832.99,yes,locked 2006.253.07:37:51.56/valo/05,652.99,yes,locked 2006.253.07:37:51.56/valo/06,772.99,yes,locked 2006.253.07:37:51.56/valo/07,832.99,yes,locked 2006.253.07:37:51.56/valo/08,852.99,yes,locked 2006.253.07:37:52.65/vb/01,04,usb,yes,34,32 2006.253.07:37:52.65/vb/02,05,usb,yes,31,33 2006.253.07:37:52.65/vb/03,04,usb,yes,32,36 2006.253.07:37:52.65/vb/04,04,usb,yes,33,33 2006.253.07:37:52.65/vb/05,04,usb,yes,31,35 2006.253.07:37:52.65/vb/06,04,usb,yes,32,35 2006.253.07:37:52.65/vb/07,04,usb,yes,35,34 2006.253.07:37:52.65/vb/08,04,usb,yes,32,35 2006.253.07:37:52.89/vblo/01,632.99,yes,locked 2006.253.07:37:52.89/vblo/02,640.99,yes,locked 2006.253.07:37:52.89/vblo/03,656.99,yes,locked 2006.253.07:37:52.89/vblo/04,712.99,yes,locked 2006.253.07:37:52.89/vblo/05,744.99,yes,locked 2006.253.07:37:52.89/vblo/06,752.99,yes,locked 2006.253.07:37:52.89/vblo/07,734.99,yes,locked 2006.253.07:37:52.89/vblo/08,744.99,yes,locked 2006.253.07:37:53.04/vabw/8 2006.253.07:37:53.19/vbbw/8 2006.253.07:37:53.32/xfe/off,on,14.2 2006.253.07:37:53.69/ifatt/23,28,28,28 2006.253.07:37:54.08/fmout-gps/S +4.75E-07 2006.253.07:37:54.15:!2006.253.07:38:50 2006.253.07:38:50.00:data_valid=off 2006.253.07:38:50.00:postob 2006.253.07:38:50.16/cable/+6.3685E-03 2006.253.07:38:50.16/wx/31.51,1006.3,72 2006.253.07:38:51.08/fmout-gps/S +4.75E-07 2006.253.07:38:51.08:scan_name=253-0739,k06253,60 2006.253.07:38:51.08:source=1300+580,130252.47,574837.6,2000.0,ccw 2006.253.07:38:51.13#flagr#flagr/antenna,new-source 2006.253.07:38:52.13:checkk5 2006.253.07:38:52.50/chk_autoobs//k5ts1/ autoobs is running! 2006.253.07:38:52.88/chk_autoobs//k5ts2/ autoobs is running! 2006.253.07:38:53.26/chk_autoobs//k5ts3/ autoobs is running! 2006.253.07:38:53.63/chk_autoobs//k5ts4/ autoobs is running! 2006.253.07:38:54.00/chk_obsdata//k5ts1/T2530737??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.07:38:54.36/chk_obsdata//k5ts2/T2530737??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.07:38:54.74/chk_obsdata//k5ts3/T2530737??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.07:38:55.11/chk_obsdata//k5ts4/T2530737??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.07:38:55.81/k5log//k5ts1_log_newline 2006.253.07:38:56.50/k5log//k5ts2_log_newline 2006.253.07:38:57.19/k5log//k5ts3_log_newline 2006.253.07:38:57.87/k5log//k5ts4_log_newline 2006.253.07:38:57.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.253.07:38:57.90:4f8m12a=1 2006.253.07:38:57.90$4f8m12a/echo=on 2006.253.07:38:57.90$4f8m12a/pcalon 2006.253.07:38:57.90$pcalon/"no phase cal control is implemented here 2006.253.07:38:57.90$4f8m12a/"tpicd=stop 2006.253.07:38:57.90$4f8m12a/vc4f8 2006.253.07:38:57.90$vc4f8/valo=1,532.99 2006.253.07:38:57.90#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.253.07:38:57.90#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.253.07:38:57.90#ibcon#ireg 17 cls_cnt 0 2006.253.07:38:57.90#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.253.07:38:57.90#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.253.07:38:57.90#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.253.07:38:57.90#ibcon#enter wrdev, iclass 24, count 0 2006.253.07:38:57.90#ibcon#first serial, iclass 24, count 0 2006.253.07:38:57.90#ibcon#enter sib2, iclass 24, count 0 2006.253.07:38:57.90#ibcon#flushed, iclass 24, count 0 2006.253.07:38:57.90#ibcon#about to write, iclass 24, count 0 2006.253.07:38:57.90#ibcon#wrote, iclass 24, count 0 2006.253.07:38:57.90#ibcon#about to read 3, iclass 24, count 0 2006.253.07:38:57.94#ibcon#read 3, iclass 24, count 0 2006.253.07:38:57.94#ibcon#about to read 4, iclass 24, count 0 2006.253.07:38:57.94#ibcon#read 4, iclass 24, count 0 2006.253.07:38:57.94#ibcon#about to read 5, iclass 24, count 0 2006.253.07:38:57.94#ibcon#read 5, iclass 24, count 0 2006.253.07:38:57.94#ibcon#about to read 6, iclass 24, count 0 2006.253.07:38:57.94#ibcon#read 6, iclass 24, count 0 2006.253.07:38:57.94#ibcon#end of sib2, iclass 24, count 0 2006.253.07:38:57.94#ibcon#*mode == 0, iclass 24, count 0 2006.253.07:38:57.94#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.253.07:38:57.94#ibcon#[26=FRQ=01,532.99\r\n] 2006.253.07:38:57.94#ibcon#*before write, iclass 24, count 0 2006.253.07:38:57.94#ibcon#enter sib2, iclass 24, count 0 2006.253.07:38:57.94#ibcon#flushed, iclass 24, count 0 2006.253.07:38:57.94#ibcon#about to write, iclass 24, count 0 2006.253.07:38:57.94#ibcon#wrote, iclass 24, count 0 2006.253.07:38:57.94#ibcon#about to read 3, iclass 24, count 0 2006.253.07:38:57.99#ibcon#read 3, iclass 24, count 0 2006.253.07:38:57.99#ibcon#about to read 4, iclass 24, count 0 2006.253.07:38:57.99#ibcon#read 4, iclass 24, count 0 2006.253.07:38:57.99#ibcon#about to read 5, iclass 24, count 0 2006.253.07:38:57.99#ibcon#read 5, iclass 24, count 0 2006.253.07:38:57.99#ibcon#about to read 6, iclass 24, count 0 2006.253.07:38:57.99#ibcon#read 6, iclass 24, count 0 2006.253.07:38:57.99#ibcon#end of sib2, iclass 24, count 0 2006.253.07:38:57.99#ibcon#*after write, iclass 24, count 0 2006.253.07:38:57.99#ibcon#*before return 0, iclass 24, count 0 2006.253.07:38:57.99#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.253.07:38:57.99#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.253.07:38:57.99#ibcon#about to clear, iclass 24 cls_cnt 0 2006.253.07:38:57.99#ibcon#cleared, iclass 24 cls_cnt 0 2006.253.07:38:57.99$vc4f8/va=1,8 2006.253.07:38:57.99#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.253.07:38:57.99#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.253.07:38:57.99#ibcon#ireg 11 cls_cnt 2 2006.253.07:38:57.99#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.253.07:38:57.99#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.253.07:38:57.99#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.253.07:38:57.99#ibcon#enter wrdev, iclass 26, count 2 2006.253.07:38:57.99#ibcon#first serial, iclass 26, count 2 2006.253.07:38:57.99#ibcon#enter sib2, iclass 26, count 2 2006.253.07:38:57.99#ibcon#flushed, iclass 26, count 2 2006.253.07:38:57.99#ibcon#about to write, iclass 26, count 2 2006.253.07:38:57.99#ibcon#wrote, iclass 26, count 2 2006.253.07:38:57.99#ibcon#about to read 3, iclass 26, count 2 2006.253.07:38:58.01#ibcon#read 3, iclass 26, count 2 2006.253.07:38:58.01#ibcon#about to read 4, iclass 26, count 2 2006.253.07:38:58.01#ibcon#read 4, iclass 26, count 2 2006.253.07:38:58.01#ibcon#about to read 5, iclass 26, count 2 2006.253.07:38:58.01#ibcon#read 5, iclass 26, count 2 2006.253.07:38:58.01#ibcon#about to read 6, iclass 26, count 2 2006.253.07:38:58.01#ibcon#read 6, iclass 26, count 2 2006.253.07:38:58.01#ibcon#end of sib2, iclass 26, count 2 2006.253.07:38:58.01#ibcon#*mode == 0, iclass 26, count 2 2006.253.07:38:58.01#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.253.07:38:58.01#ibcon#[25=AT01-08\r\n] 2006.253.07:38:58.01#ibcon#*before write, iclass 26, count 2 2006.253.07:38:58.01#ibcon#enter sib2, iclass 26, count 2 2006.253.07:38:58.01#ibcon#flushed, iclass 26, count 2 2006.253.07:38:58.01#ibcon#about to write, iclass 26, count 2 2006.253.07:38:58.01#ibcon#wrote, iclass 26, count 2 2006.253.07:38:58.01#ibcon#about to read 3, iclass 26, count 2 2006.253.07:38:58.04#ibcon#read 3, iclass 26, count 2 2006.253.07:38:58.04#ibcon#about to read 4, iclass 26, count 2 2006.253.07:38:58.04#ibcon#read 4, iclass 26, count 2 2006.253.07:38:58.04#ibcon#about to read 5, iclass 26, count 2 2006.253.07:38:58.04#ibcon#read 5, iclass 26, count 2 2006.253.07:38:58.04#ibcon#about to read 6, iclass 26, count 2 2006.253.07:38:58.04#ibcon#read 6, iclass 26, count 2 2006.253.07:38:58.04#ibcon#end of sib2, iclass 26, count 2 2006.253.07:38:58.04#ibcon#*after write, iclass 26, count 2 2006.253.07:38:58.04#ibcon#*before return 0, iclass 26, count 2 2006.253.07:38:58.04#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.253.07:38:58.04#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.253.07:38:58.04#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.253.07:38:58.04#ibcon#ireg 7 cls_cnt 0 2006.253.07:38:58.04#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.253.07:38:58.16#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.253.07:38:58.16#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.253.07:38:58.16#ibcon#enter wrdev, iclass 26, count 0 2006.253.07:38:58.16#ibcon#first serial, iclass 26, count 0 2006.253.07:38:58.16#ibcon#enter sib2, iclass 26, count 0 2006.253.07:38:58.16#ibcon#flushed, iclass 26, count 0 2006.253.07:38:58.16#ibcon#about to write, iclass 26, count 0 2006.253.07:38:58.16#ibcon#wrote, iclass 26, count 0 2006.253.07:38:58.16#ibcon#about to read 3, iclass 26, count 0 2006.253.07:38:58.18#ibcon#read 3, iclass 26, count 0 2006.253.07:38:58.18#ibcon#about to read 4, iclass 26, count 0 2006.253.07:38:58.18#ibcon#read 4, iclass 26, count 0 2006.253.07:38:58.18#ibcon#about to read 5, iclass 26, count 0 2006.253.07:38:58.18#ibcon#read 5, iclass 26, count 0 2006.253.07:38:58.18#ibcon#about to read 6, iclass 26, count 0 2006.253.07:38:58.18#ibcon#read 6, iclass 26, count 0 2006.253.07:38:58.18#ibcon#end of sib2, iclass 26, count 0 2006.253.07:38:58.18#ibcon#*mode == 0, iclass 26, count 0 2006.253.07:38:58.18#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.253.07:38:58.18#ibcon#[25=USB\r\n] 2006.253.07:38:58.18#ibcon#*before write, iclass 26, count 0 2006.253.07:38:58.18#ibcon#enter sib2, iclass 26, count 0 2006.253.07:38:58.18#ibcon#flushed, iclass 26, count 0 2006.253.07:38:58.18#ibcon#about to write, iclass 26, count 0 2006.253.07:38:58.18#ibcon#wrote, iclass 26, count 0 2006.253.07:38:58.18#ibcon#about to read 3, iclass 26, count 0 2006.253.07:38:58.21#ibcon#read 3, iclass 26, count 0 2006.253.07:38:58.21#ibcon#about to read 4, iclass 26, count 0 2006.253.07:38:58.21#ibcon#read 4, iclass 26, count 0 2006.253.07:38:58.21#ibcon#about to read 5, iclass 26, count 0 2006.253.07:38:58.21#ibcon#read 5, iclass 26, count 0 2006.253.07:38:58.21#ibcon#about to read 6, iclass 26, count 0 2006.253.07:38:58.21#ibcon#read 6, iclass 26, count 0 2006.253.07:38:58.21#ibcon#end of sib2, iclass 26, count 0 2006.253.07:38:58.21#ibcon#*after write, iclass 26, count 0 2006.253.07:38:58.21#ibcon#*before return 0, iclass 26, count 0 2006.253.07:38:58.21#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.253.07:38:58.21#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.253.07:38:58.21#ibcon#about to clear, iclass 26 cls_cnt 0 2006.253.07:38:58.21#ibcon#cleared, iclass 26 cls_cnt 0 2006.253.07:38:58.21$vc4f8/valo=2,572.99 2006.253.07:38:58.21#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.253.07:38:58.21#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.253.07:38:58.21#ibcon#ireg 17 cls_cnt 0 2006.253.07:38:58.21#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.253.07:38:58.21#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.253.07:38:58.21#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.253.07:38:58.21#ibcon#enter wrdev, iclass 29, count 0 2006.253.07:38:58.21#ibcon#first serial, iclass 29, count 0 2006.253.07:38:58.21#ibcon#enter sib2, iclass 29, count 0 2006.253.07:38:58.21#ibcon#flushed, iclass 29, count 0 2006.253.07:38:58.21#ibcon#about to write, iclass 29, count 0 2006.253.07:38:58.21#ibcon#wrote, iclass 29, count 0 2006.253.07:38:58.21#ibcon#about to read 3, iclass 29, count 0 2006.253.07:38:58.23#ibcon#read 3, iclass 29, count 0 2006.253.07:38:58.23#ibcon#about to read 4, iclass 29, count 0 2006.253.07:38:58.23#ibcon#read 4, iclass 29, count 0 2006.253.07:38:58.23#ibcon#about to read 5, iclass 29, count 0 2006.253.07:38:58.23#ibcon#read 5, iclass 29, count 0 2006.253.07:38:58.23#ibcon#about to read 6, iclass 29, count 0 2006.253.07:38:58.23#ibcon#read 6, iclass 29, count 0 2006.253.07:38:58.23#ibcon#end of sib2, iclass 29, count 0 2006.253.07:38:58.23#ibcon#*mode == 0, iclass 29, count 0 2006.253.07:38:58.23#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.253.07:38:58.23#ibcon#[26=FRQ=02,572.99\r\n] 2006.253.07:38:58.23#ibcon#*before write, iclass 29, count 0 2006.253.07:38:58.23#ibcon#enter sib2, iclass 29, count 0 2006.253.07:38:58.23#ibcon#flushed, iclass 29, count 0 2006.253.07:38:58.23#ibcon#about to write, iclass 29, count 0 2006.253.07:38:58.23#ibcon#wrote, iclass 29, count 0 2006.253.07:38:58.23#ibcon#about to read 3, iclass 29, count 0 2006.253.07:38:58.25#abcon#<5=/08 1.1 4.1 31.50 721006.3\r\n> 2006.253.07:38:58.27#abcon#{5=INTERFACE CLEAR} 2006.253.07:38:58.27#ibcon#read 3, iclass 29, count 0 2006.253.07:38:58.27#ibcon#about to read 4, iclass 29, count 0 2006.253.07:38:58.27#ibcon#read 4, iclass 29, count 0 2006.253.07:38:58.27#ibcon#about to read 5, iclass 29, count 0 2006.253.07:38:58.27#ibcon#read 5, iclass 29, count 0 2006.253.07:38:58.27#ibcon#about to read 6, iclass 29, count 0 2006.253.07:38:58.27#ibcon#read 6, iclass 29, count 0 2006.253.07:38:58.27#ibcon#end of sib2, iclass 29, count 0 2006.253.07:38:58.27#ibcon#*after write, iclass 29, count 0 2006.253.07:38:58.27#ibcon#*before return 0, iclass 29, count 0 2006.253.07:38:58.27#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.253.07:38:58.27#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.253.07:38:58.27#ibcon#about to clear, iclass 29 cls_cnt 0 2006.253.07:38:58.27#ibcon#cleared, iclass 29 cls_cnt 0 2006.253.07:38:58.27$vc4f8/va=2,7 2006.253.07:38:58.27#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.253.07:38:58.27#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.253.07:38:58.27#ibcon#ireg 11 cls_cnt 2 2006.253.07:38:58.27#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.253.07:38:58.33#abcon#[5=S1D000X0/0*\r\n] 2006.253.07:38:58.33#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.253.07:38:58.33#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.253.07:38:58.33#ibcon#enter wrdev, iclass 33, count 2 2006.253.07:38:58.33#ibcon#first serial, iclass 33, count 2 2006.253.07:38:58.33#ibcon#enter sib2, iclass 33, count 2 2006.253.07:38:58.33#ibcon#flushed, iclass 33, count 2 2006.253.07:38:58.33#ibcon#about to write, iclass 33, count 2 2006.253.07:38:58.33#ibcon#wrote, iclass 33, count 2 2006.253.07:38:58.33#ibcon#about to read 3, iclass 33, count 2 2006.253.07:38:58.35#ibcon#read 3, iclass 33, count 2 2006.253.07:38:58.35#ibcon#about to read 4, iclass 33, count 2 2006.253.07:38:58.35#ibcon#read 4, iclass 33, count 2 2006.253.07:38:58.35#ibcon#about to read 5, iclass 33, count 2 2006.253.07:38:58.35#ibcon#read 5, iclass 33, count 2 2006.253.07:38:58.35#ibcon#about to read 6, iclass 33, count 2 2006.253.07:38:58.35#ibcon#read 6, iclass 33, count 2 2006.253.07:38:58.35#ibcon#end of sib2, iclass 33, count 2 2006.253.07:38:58.35#ibcon#*mode == 0, iclass 33, count 2 2006.253.07:38:58.35#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.253.07:38:58.35#ibcon#[25=AT02-07\r\n] 2006.253.07:38:58.35#ibcon#*before write, iclass 33, count 2 2006.253.07:38:58.35#ibcon#enter sib2, iclass 33, count 2 2006.253.07:38:58.35#ibcon#flushed, iclass 33, count 2 2006.253.07:38:58.35#ibcon#about to write, iclass 33, count 2 2006.253.07:38:58.35#ibcon#wrote, iclass 33, count 2 2006.253.07:38:58.35#ibcon#about to read 3, iclass 33, count 2 2006.253.07:38:58.38#ibcon#read 3, iclass 33, count 2 2006.253.07:38:58.38#ibcon#about to read 4, iclass 33, count 2 2006.253.07:38:58.38#ibcon#read 4, iclass 33, count 2 2006.253.07:38:58.38#ibcon#about to read 5, iclass 33, count 2 2006.253.07:38:58.38#ibcon#read 5, iclass 33, count 2 2006.253.07:38:58.38#ibcon#about to read 6, iclass 33, count 2 2006.253.07:38:58.38#ibcon#read 6, iclass 33, count 2 2006.253.07:38:58.38#ibcon#end of sib2, iclass 33, count 2 2006.253.07:38:58.38#ibcon#*after write, iclass 33, count 2 2006.253.07:38:58.38#ibcon#*before return 0, iclass 33, count 2 2006.253.07:38:58.38#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.253.07:38:58.38#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.253.07:38:58.38#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.253.07:38:58.38#ibcon#ireg 7 cls_cnt 0 2006.253.07:38:58.38#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.253.07:38:58.50#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.253.07:38:58.50#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.253.07:38:58.50#ibcon#enter wrdev, iclass 33, count 0 2006.253.07:38:58.50#ibcon#first serial, iclass 33, count 0 2006.253.07:38:58.50#ibcon#enter sib2, iclass 33, count 0 2006.253.07:38:58.50#ibcon#flushed, iclass 33, count 0 2006.253.07:38:58.50#ibcon#about to write, iclass 33, count 0 2006.253.07:38:58.50#ibcon#wrote, iclass 33, count 0 2006.253.07:38:58.50#ibcon#about to read 3, iclass 33, count 0 2006.253.07:38:58.52#ibcon#read 3, iclass 33, count 0 2006.253.07:38:58.52#ibcon#about to read 4, iclass 33, count 0 2006.253.07:38:58.52#ibcon#read 4, iclass 33, count 0 2006.253.07:38:58.52#ibcon#about to read 5, iclass 33, count 0 2006.253.07:38:58.52#ibcon#read 5, iclass 33, count 0 2006.253.07:38:58.52#ibcon#about to read 6, iclass 33, count 0 2006.253.07:38:58.52#ibcon#read 6, iclass 33, count 0 2006.253.07:38:58.52#ibcon#end of sib2, iclass 33, count 0 2006.253.07:38:58.52#ibcon#*mode == 0, iclass 33, count 0 2006.253.07:38:58.52#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.253.07:38:58.52#ibcon#[25=USB\r\n] 2006.253.07:38:58.52#ibcon#*before write, iclass 33, count 0 2006.253.07:38:58.52#ibcon#enter sib2, iclass 33, count 0 2006.253.07:38:58.52#ibcon#flushed, iclass 33, count 0 2006.253.07:38:58.52#ibcon#about to write, iclass 33, count 0 2006.253.07:38:58.52#ibcon#wrote, iclass 33, count 0 2006.253.07:38:58.52#ibcon#about to read 3, iclass 33, count 0 2006.253.07:38:58.55#ibcon#read 3, iclass 33, count 0 2006.253.07:38:58.55#ibcon#about to read 4, iclass 33, count 0 2006.253.07:38:58.55#ibcon#read 4, iclass 33, count 0 2006.253.07:38:58.55#ibcon#about to read 5, iclass 33, count 0 2006.253.07:38:58.55#ibcon#read 5, iclass 33, count 0 2006.253.07:38:58.55#ibcon#about to read 6, iclass 33, count 0 2006.253.07:38:58.55#ibcon#read 6, iclass 33, count 0 2006.253.07:38:58.55#ibcon#end of sib2, iclass 33, count 0 2006.253.07:38:58.55#ibcon#*after write, iclass 33, count 0 2006.253.07:38:58.55#ibcon#*before return 0, iclass 33, count 0 2006.253.07:38:58.55#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.253.07:38:58.55#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.253.07:38:58.55#ibcon#about to clear, iclass 33 cls_cnt 0 2006.253.07:38:58.55#ibcon#cleared, iclass 33 cls_cnt 0 2006.253.07:38:58.55$vc4f8/valo=3,672.99 2006.253.07:38:58.55#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.253.07:38:58.55#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.253.07:38:58.55#ibcon#ireg 17 cls_cnt 0 2006.253.07:38:58.55#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.253.07:38:58.55#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.253.07:38:58.55#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.253.07:38:58.55#ibcon#enter wrdev, iclass 36, count 0 2006.253.07:38:58.55#ibcon#first serial, iclass 36, count 0 2006.253.07:38:58.55#ibcon#enter sib2, iclass 36, count 0 2006.253.07:38:58.55#ibcon#flushed, iclass 36, count 0 2006.253.07:38:58.55#ibcon#about to write, iclass 36, count 0 2006.253.07:38:58.55#ibcon#wrote, iclass 36, count 0 2006.253.07:38:58.55#ibcon#about to read 3, iclass 36, count 0 2006.253.07:38:58.57#ibcon#read 3, iclass 36, count 0 2006.253.07:38:58.57#ibcon#about to read 4, iclass 36, count 0 2006.253.07:38:58.57#ibcon#read 4, iclass 36, count 0 2006.253.07:38:58.57#ibcon#about to read 5, iclass 36, count 0 2006.253.07:38:58.57#ibcon#read 5, iclass 36, count 0 2006.253.07:38:58.57#ibcon#about to read 6, iclass 36, count 0 2006.253.07:38:58.57#ibcon#read 6, iclass 36, count 0 2006.253.07:38:58.57#ibcon#end of sib2, iclass 36, count 0 2006.253.07:38:58.57#ibcon#*mode == 0, iclass 36, count 0 2006.253.07:38:58.57#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.253.07:38:58.57#ibcon#[26=FRQ=03,672.99\r\n] 2006.253.07:38:58.57#ibcon#*before write, iclass 36, count 0 2006.253.07:38:58.57#ibcon#enter sib2, iclass 36, count 0 2006.253.07:38:58.57#ibcon#flushed, iclass 36, count 0 2006.253.07:38:58.57#ibcon#about to write, iclass 36, count 0 2006.253.07:38:58.57#ibcon#wrote, iclass 36, count 0 2006.253.07:38:58.57#ibcon#about to read 3, iclass 36, count 0 2006.253.07:38:58.62#ibcon#read 3, iclass 36, count 0 2006.253.07:38:58.62#ibcon#about to read 4, iclass 36, count 0 2006.253.07:38:58.62#ibcon#read 4, iclass 36, count 0 2006.253.07:38:58.62#ibcon#about to read 5, iclass 36, count 0 2006.253.07:38:58.62#ibcon#read 5, iclass 36, count 0 2006.253.07:38:58.62#ibcon#about to read 6, iclass 36, count 0 2006.253.07:38:58.62#ibcon#read 6, iclass 36, count 0 2006.253.07:38:58.62#ibcon#end of sib2, iclass 36, count 0 2006.253.07:38:58.62#ibcon#*after write, iclass 36, count 0 2006.253.07:38:58.62#ibcon#*before return 0, iclass 36, count 0 2006.253.07:38:58.62#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.253.07:38:58.62#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.253.07:38:58.62#ibcon#about to clear, iclass 36 cls_cnt 0 2006.253.07:38:58.62#ibcon#cleared, iclass 36 cls_cnt 0 2006.253.07:38:58.62$vc4f8/va=3,6 2006.253.07:38:58.62#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.253.07:38:58.62#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.253.07:38:58.62#ibcon#ireg 11 cls_cnt 2 2006.253.07:38:58.62#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.253.07:38:58.67#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.253.07:38:58.67#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.253.07:38:58.67#ibcon#enter wrdev, iclass 38, count 2 2006.253.07:38:58.67#ibcon#first serial, iclass 38, count 2 2006.253.07:38:58.67#ibcon#enter sib2, iclass 38, count 2 2006.253.07:38:58.67#ibcon#flushed, iclass 38, count 2 2006.253.07:38:58.67#ibcon#about to write, iclass 38, count 2 2006.253.07:38:58.67#ibcon#wrote, iclass 38, count 2 2006.253.07:38:58.67#ibcon#about to read 3, iclass 38, count 2 2006.253.07:38:58.69#ibcon#read 3, iclass 38, count 2 2006.253.07:38:58.69#ibcon#about to read 4, iclass 38, count 2 2006.253.07:38:58.69#ibcon#read 4, iclass 38, count 2 2006.253.07:38:58.69#ibcon#about to read 5, iclass 38, count 2 2006.253.07:38:58.69#ibcon#read 5, iclass 38, count 2 2006.253.07:38:58.69#ibcon#about to read 6, iclass 38, count 2 2006.253.07:38:58.69#ibcon#read 6, iclass 38, count 2 2006.253.07:38:58.69#ibcon#end of sib2, iclass 38, count 2 2006.253.07:38:58.69#ibcon#*mode == 0, iclass 38, count 2 2006.253.07:38:58.69#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.253.07:38:58.69#ibcon#[25=AT03-06\r\n] 2006.253.07:38:58.69#ibcon#*before write, iclass 38, count 2 2006.253.07:38:58.69#ibcon#enter sib2, iclass 38, count 2 2006.253.07:38:58.69#ibcon#flushed, iclass 38, count 2 2006.253.07:38:58.69#ibcon#about to write, iclass 38, count 2 2006.253.07:38:58.69#ibcon#wrote, iclass 38, count 2 2006.253.07:38:58.69#ibcon#about to read 3, iclass 38, count 2 2006.253.07:38:58.72#ibcon#read 3, iclass 38, count 2 2006.253.07:38:58.72#ibcon#about to read 4, iclass 38, count 2 2006.253.07:38:58.72#ibcon#read 4, iclass 38, count 2 2006.253.07:38:58.72#ibcon#about to read 5, iclass 38, count 2 2006.253.07:38:58.72#ibcon#read 5, iclass 38, count 2 2006.253.07:38:58.72#ibcon#about to read 6, iclass 38, count 2 2006.253.07:38:58.72#ibcon#read 6, iclass 38, count 2 2006.253.07:38:58.72#ibcon#end of sib2, iclass 38, count 2 2006.253.07:38:58.72#ibcon#*after write, iclass 38, count 2 2006.253.07:38:58.72#ibcon#*before return 0, iclass 38, count 2 2006.253.07:38:58.72#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.253.07:38:58.72#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.253.07:38:58.72#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.253.07:38:58.72#ibcon#ireg 7 cls_cnt 0 2006.253.07:38:58.72#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.253.07:38:58.84#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.253.07:38:58.84#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.253.07:38:58.84#ibcon#enter wrdev, iclass 38, count 0 2006.253.07:38:58.84#ibcon#first serial, iclass 38, count 0 2006.253.07:38:58.84#ibcon#enter sib2, iclass 38, count 0 2006.253.07:38:58.84#ibcon#flushed, iclass 38, count 0 2006.253.07:38:58.84#ibcon#about to write, iclass 38, count 0 2006.253.07:38:58.84#ibcon#wrote, iclass 38, count 0 2006.253.07:38:58.84#ibcon#about to read 3, iclass 38, count 0 2006.253.07:38:58.86#ibcon#read 3, iclass 38, count 0 2006.253.07:38:58.86#ibcon#about to read 4, iclass 38, count 0 2006.253.07:38:58.86#ibcon#read 4, iclass 38, count 0 2006.253.07:38:58.86#ibcon#about to read 5, iclass 38, count 0 2006.253.07:38:58.86#ibcon#read 5, iclass 38, count 0 2006.253.07:38:58.86#ibcon#about to read 6, iclass 38, count 0 2006.253.07:38:58.86#ibcon#read 6, iclass 38, count 0 2006.253.07:38:58.86#ibcon#end of sib2, iclass 38, count 0 2006.253.07:38:58.86#ibcon#*mode == 0, iclass 38, count 0 2006.253.07:38:58.86#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.253.07:38:58.86#ibcon#[25=USB\r\n] 2006.253.07:38:58.86#ibcon#*before write, iclass 38, count 0 2006.253.07:38:58.86#ibcon#enter sib2, iclass 38, count 0 2006.253.07:38:58.86#ibcon#flushed, iclass 38, count 0 2006.253.07:38:58.86#ibcon#about to write, iclass 38, count 0 2006.253.07:38:58.86#ibcon#wrote, iclass 38, count 0 2006.253.07:38:58.86#ibcon#about to read 3, iclass 38, count 0 2006.253.07:38:58.89#ibcon#read 3, iclass 38, count 0 2006.253.07:38:58.89#ibcon#about to read 4, iclass 38, count 0 2006.253.07:38:58.89#ibcon#read 4, iclass 38, count 0 2006.253.07:38:58.89#ibcon#about to read 5, iclass 38, count 0 2006.253.07:38:58.89#ibcon#read 5, iclass 38, count 0 2006.253.07:38:58.89#ibcon#about to read 6, iclass 38, count 0 2006.253.07:38:58.89#ibcon#read 6, iclass 38, count 0 2006.253.07:38:58.89#ibcon#end of sib2, iclass 38, count 0 2006.253.07:38:58.89#ibcon#*after write, iclass 38, count 0 2006.253.07:38:58.89#ibcon#*before return 0, iclass 38, count 0 2006.253.07:38:58.89#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.253.07:38:58.89#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.253.07:38:58.89#ibcon#about to clear, iclass 38 cls_cnt 0 2006.253.07:38:58.89#ibcon#cleared, iclass 38 cls_cnt 0 2006.253.07:38:58.89$vc4f8/valo=4,832.99 2006.253.07:38:58.89#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.253.07:38:58.89#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.253.07:38:58.89#ibcon#ireg 17 cls_cnt 0 2006.253.07:38:58.89#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.253.07:38:58.89#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.253.07:38:58.89#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.253.07:38:58.89#ibcon#enter wrdev, iclass 40, count 0 2006.253.07:38:58.89#ibcon#first serial, iclass 40, count 0 2006.253.07:38:58.89#ibcon#enter sib2, iclass 40, count 0 2006.253.07:38:58.89#ibcon#flushed, iclass 40, count 0 2006.253.07:38:58.89#ibcon#about to write, iclass 40, count 0 2006.253.07:38:58.89#ibcon#wrote, iclass 40, count 0 2006.253.07:38:58.89#ibcon#about to read 3, iclass 40, count 0 2006.253.07:38:58.91#ibcon#read 3, iclass 40, count 0 2006.253.07:38:58.91#ibcon#about to read 4, iclass 40, count 0 2006.253.07:38:58.91#ibcon#read 4, iclass 40, count 0 2006.253.07:38:58.91#ibcon#about to read 5, iclass 40, count 0 2006.253.07:38:58.91#ibcon#read 5, iclass 40, count 0 2006.253.07:38:58.91#ibcon#about to read 6, iclass 40, count 0 2006.253.07:38:58.91#ibcon#read 6, iclass 40, count 0 2006.253.07:38:58.91#ibcon#end of sib2, iclass 40, count 0 2006.253.07:38:58.91#ibcon#*mode == 0, iclass 40, count 0 2006.253.07:38:58.91#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.253.07:38:58.91#ibcon#[26=FRQ=04,832.99\r\n] 2006.253.07:38:58.91#ibcon#*before write, iclass 40, count 0 2006.253.07:38:58.91#ibcon#enter sib2, iclass 40, count 0 2006.253.07:38:58.91#ibcon#flushed, iclass 40, count 0 2006.253.07:38:58.91#ibcon#about to write, iclass 40, count 0 2006.253.07:38:58.91#ibcon#wrote, iclass 40, count 0 2006.253.07:38:58.91#ibcon#about to read 3, iclass 40, count 0 2006.253.07:38:58.96#ibcon#read 3, iclass 40, count 0 2006.253.07:38:58.96#ibcon#about to read 4, iclass 40, count 0 2006.253.07:38:58.96#ibcon#read 4, iclass 40, count 0 2006.253.07:38:58.96#ibcon#about to read 5, iclass 40, count 0 2006.253.07:38:58.96#ibcon#read 5, iclass 40, count 0 2006.253.07:38:58.96#ibcon#about to read 6, iclass 40, count 0 2006.253.07:38:58.96#ibcon#read 6, iclass 40, count 0 2006.253.07:38:58.96#ibcon#end of sib2, iclass 40, count 0 2006.253.07:38:58.96#ibcon#*after write, iclass 40, count 0 2006.253.07:38:58.96#ibcon#*before return 0, iclass 40, count 0 2006.253.07:38:58.96#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.253.07:38:58.96#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.253.07:38:58.96#ibcon#about to clear, iclass 40 cls_cnt 0 2006.253.07:38:58.96#ibcon#cleared, iclass 40 cls_cnt 0 2006.253.07:38:58.96$vc4f8/va=4,7 2006.253.07:38:58.96#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.253.07:38:58.96#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.253.07:38:58.96#ibcon#ireg 11 cls_cnt 2 2006.253.07:38:58.96#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.253.07:38:59.01#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.253.07:38:59.01#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.253.07:38:59.01#ibcon#enter wrdev, iclass 4, count 2 2006.253.07:38:59.01#ibcon#first serial, iclass 4, count 2 2006.253.07:38:59.01#ibcon#enter sib2, iclass 4, count 2 2006.253.07:38:59.01#ibcon#flushed, iclass 4, count 2 2006.253.07:38:59.01#ibcon#about to write, iclass 4, count 2 2006.253.07:38:59.01#ibcon#wrote, iclass 4, count 2 2006.253.07:38:59.01#ibcon#about to read 3, iclass 4, count 2 2006.253.07:38:59.03#ibcon#read 3, iclass 4, count 2 2006.253.07:38:59.03#ibcon#about to read 4, iclass 4, count 2 2006.253.07:38:59.03#ibcon#read 4, iclass 4, count 2 2006.253.07:38:59.03#ibcon#about to read 5, iclass 4, count 2 2006.253.07:38:59.03#ibcon#read 5, iclass 4, count 2 2006.253.07:38:59.03#ibcon#about to read 6, iclass 4, count 2 2006.253.07:38:59.03#ibcon#read 6, iclass 4, count 2 2006.253.07:38:59.03#ibcon#end of sib2, iclass 4, count 2 2006.253.07:38:59.03#ibcon#*mode == 0, iclass 4, count 2 2006.253.07:38:59.03#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.253.07:38:59.03#ibcon#[25=AT04-07\r\n] 2006.253.07:38:59.03#ibcon#*before write, iclass 4, count 2 2006.253.07:38:59.03#ibcon#enter sib2, iclass 4, count 2 2006.253.07:38:59.03#ibcon#flushed, iclass 4, count 2 2006.253.07:38:59.03#ibcon#about to write, iclass 4, count 2 2006.253.07:38:59.03#ibcon#wrote, iclass 4, count 2 2006.253.07:38:59.03#ibcon#about to read 3, iclass 4, count 2 2006.253.07:38:59.06#ibcon#read 3, iclass 4, count 2 2006.253.07:38:59.06#ibcon#about to read 4, iclass 4, count 2 2006.253.07:38:59.06#ibcon#read 4, iclass 4, count 2 2006.253.07:38:59.06#ibcon#about to read 5, iclass 4, count 2 2006.253.07:38:59.06#ibcon#read 5, iclass 4, count 2 2006.253.07:38:59.06#ibcon#about to read 6, iclass 4, count 2 2006.253.07:38:59.06#ibcon#read 6, iclass 4, count 2 2006.253.07:38:59.06#ibcon#end of sib2, iclass 4, count 2 2006.253.07:38:59.06#ibcon#*after write, iclass 4, count 2 2006.253.07:38:59.06#ibcon#*before return 0, iclass 4, count 2 2006.253.07:38:59.06#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.253.07:38:59.06#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.253.07:38:59.06#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.253.07:38:59.06#ibcon#ireg 7 cls_cnt 0 2006.253.07:38:59.06#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.253.07:38:59.18#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.253.07:38:59.18#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.253.07:38:59.18#ibcon#enter wrdev, iclass 4, count 0 2006.253.07:38:59.18#ibcon#first serial, iclass 4, count 0 2006.253.07:38:59.18#ibcon#enter sib2, iclass 4, count 0 2006.253.07:38:59.18#ibcon#flushed, iclass 4, count 0 2006.253.07:38:59.18#ibcon#about to write, iclass 4, count 0 2006.253.07:38:59.18#ibcon#wrote, iclass 4, count 0 2006.253.07:38:59.18#ibcon#about to read 3, iclass 4, count 0 2006.253.07:38:59.20#ibcon#read 3, iclass 4, count 0 2006.253.07:38:59.20#ibcon#about to read 4, iclass 4, count 0 2006.253.07:38:59.20#ibcon#read 4, iclass 4, count 0 2006.253.07:38:59.20#ibcon#about to read 5, iclass 4, count 0 2006.253.07:38:59.20#ibcon#read 5, iclass 4, count 0 2006.253.07:38:59.20#ibcon#about to read 6, iclass 4, count 0 2006.253.07:38:59.20#ibcon#read 6, iclass 4, count 0 2006.253.07:38:59.20#ibcon#end of sib2, iclass 4, count 0 2006.253.07:38:59.20#ibcon#*mode == 0, iclass 4, count 0 2006.253.07:38:59.20#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.253.07:38:59.20#ibcon#[25=USB\r\n] 2006.253.07:38:59.20#ibcon#*before write, iclass 4, count 0 2006.253.07:38:59.20#ibcon#enter sib2, iclass 4, count 0 2006.253.07:38:59.20#ibcon#flushed, iclass 4, count 0 2006.253.07:38:59.20#ibcon#about to write, iclass 4, count 0 2006.253.07:38:59.20#ibcon#wrote, iclass 4, count 0 2006.253.07:38:59.20#ibcon#about to read 3, iclass 4, count 0 2006.253.07:38:59.23#ibcon#read 3, iclass 4, count 0 2006.253.07:38:59.23#ibcon#about to read 4, iclass 4, count 0 2006.253.07:38:59.23#ibcon#read 4, iclass 4, count 0 2006.253.07:38:59.23#ibcon#about to read 5, iclass 4, count 0 2006.253.07:38:59.23#ibcon#read 5, iclass 4, count 0 2006.253.07:38:59.23#ibcon#about to read 6, iclass 4, count 0 2006.253.07:38:59.23#ibcon#read 6, iclass 4, count 0 2006.253.07:38:59.23#ibcon#end of sib2, iclass 4, count 0 2006.253.07:38:59.23#ibcon#*after write, iclass 4, count 0 2006.253.07:38:59.23#ibcon#*before return 0, iclass 4, count 0 2006.253.07:38:59.23#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.253.07:38:59.23#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.253.07:38:59.23#ibcon#about to clear, iclass 4 cls_cnt 0 2006.253.07:38:59.23#ibcon#cleared, iclass 4 cls_cnt 0 2006.253.07:38:59.23$vc4f8/valo=5,652.99 2006.253.07:38:59.23#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.253.07:38:59.23#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.253.07:38:59.23#ibcon#ireg 17 cls_cnt 0 2006.253.07:38:59.23#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.253.07:38:59.23#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.253.07:38:59.23#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.253.07:38:59.23#ibcon#enter wrdev, iclass 6, count 0 2006.253.07:38:59.23#ibcon#first serial, iclass 6, count 0 2006.253.07:38:59.23#ibcon#enter sib2, iclass 6, count 0 2006.253.07:38:59.23#ibcon#flushed, iclass 6, count 0 2006.253.07:38:59.23#ibcon#about to write, iclass 6, count 0 2006.253.07:38:59.23#ibcon#wrote, iclass 6, count 0 2006.253.07:38:59.23#ibcon#about to read 3, iclass 6, count 0 2006.253.07:38:59.25#ibcon#read 3, iclass 6, count 0 2006.253.07:38:59.25#ibcon#about to read 4, iclass 6, count 0 2006.253.07:38:59.25#ibcon#read 4, iclass 6, count 0 2006.253.07:38:59.25#ibcon#about to read 5, iclass 6, count 0 2006.253.07:38:59.25#ibcon#read 5, iclass 6, count 0 2006.253.07:38:59.25#ibcon#about to read 6, iclass 6, count 0 2006.253.07:38:59.25#ibcon#read 6, iclass 6, count 0 2006.253.07:38:59.25#ibcon#end of sib2, iclass 6, count 0 2006.253.07:38:59.25#ibcon#*mode == 0, iclass 6, count 0 2006.253.07:38:59.25#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.253.07:38:59.25#ibcon#[26=FRQ=05,652.99\r\n] 2006.253.07:38:59.25#ibcon#*before write, iclass 6, count 0 2006.253.07:38:59.25#ibcon#enter sib2, iclass 6, count 0 2006.253.07:38:59.25#ibcon#flushed, iclass 6, count 0 2006.253.07:38:59.25#ibcon#about to write, iclass 6, count 0 2006.253.07:38:59.25#ibcon#wrote, iclass 6, count 0 2006.253.07:38:59.25#ibcon#about to read 3, iclass 6, count 0 2006.253.07:38:59.29#ibcon#read 3, iclass 6, count 0 2006.253.07:38:59.29#ibcon#about to read 4, iclass 6, count 0 2006.253.07:38:59.29#ibcon#read 4, iclass 6, count 0 2006.253.07:38:59.29#ibcon#about to read 5, iclass 6, count 0 2006.253.07:38:59.29#ibcon#read 5, iclass 6, count 0 2006.253.07:38:59.29#ibcon#about to read 6, iclass 6, count 0 2006.253.07:38:59.29#ibcon#read 6, iclass 6, count 0 2006.253.07:38:59.29#ibcon#end of sib2, iclass 6, count 0 2006.253.07:38:59.29#ibcon#*after write, iclass 6, count 0 2006.253.07:38:59.29#ibcon#*before return 0, iclass 6, count 0 2006.253.07:38:59.29#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.253.07:38:59.29#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.253.07:38:59.29#ibcon#about to clear, iclass 6 cls_cnt 0 2006.253.07:38:59.29#ibcon#cleared, iclass 6 cls_cnt 0 2006.253.07:38:59.29$vc4f8/va=5,7 2006.253.07:38:59.29#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.253.07:38:59.29#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.253.07:38:59.29#ibcon#ireg 11 cls_cnt 2 2006.253.07:38:59.29#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.253.07:38:59.35#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.253.07:38:59.35#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.253.07:38:59.35#ibcon#enter wrdev, iclass 10, count 2 2006.253.07:38:59.35#ibcon#first serial, iclass 10, count 2 2006.253.07:38:59.35#ibcon#enter sib2, iclass 10, count 2 2006.253.07:38:59.35#ibcon#flushed, iclass 10, count 2 2006.253.07:38:59.35#ibcon#about to write, iclass 10, count 2 2006.253.07:38:59.35#ibcon#wrote, iclass 10, count 2 2006.253.07:38:59.35#ibcon#about to read 3, iclass 10, count 2 2006.253.07:38:59.37#ibcon#read 3, iclass 10, count 2 2006.253.07:38:59.37#ibcon#about to read 4, iclass 10, count 2 2006.253.07:38:59.37#ibcon#read 4, iclass 10, count 2 2006.253.07:38:59.37#ibcon#about to read 5, iclass 10, count 2 2006.253.07:38:59.37#ibcon#read 5, iclass 10, count 2 2006.253.07:38:59.37#ibcon#about to read 6, iclass 10, count 2 2006.253.07:38:59.37#ibcon#read 6, iclass 10, count 2 2006.253.07:38:59.37#ibcon#end of sib2, iclass 10, count 2 2006.253.07:38:59.37#ibcon#*mode == 0, iclass 10, count 2 2006.253.07:38:59.37#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.253.07:38:59.37#ibcon#[25=AT05-07\r\n] 2006.253.07:38:59.37#ibcon#*before write, iclass 10, count 2 2006.253.07:38:59.37#ibcon#enter sib2, iclass 10, count 2 2006.253.07:38:59.37#ibcon#flushed, iclass 10, count 2 2006.253.07:38:59.37#ibcon#about to write, iclass 10, count 2 2006.253.07:38:59.37#ibcon#wrote, iclass 10, count 2 2006.253.07:38:59.37#ibcon#about to read 3, iclass 10, count 2 2006.253.07:38:59.40#ibcon#read 3, iclass 10, count 2 2006.253.07:38:59.40#ibcon#about to read 4, iclass 10, count 2 2006.253.07:38:59.40#ibcon#read 4, iclass 10, count 2 2006.253.07:38:59.40#ibcon#about to read 5, iclass 10, count 2 2006.253.07:38:59.40#ibcon#read 5, iclass 10, count 2 2006.253.07:38:59.40#ibcon#about to read 6, iclass 10, count 2 2006.253.07:38:59.40#ibcon#read 6, iclass 10, count 2 2006.253.07:38:59.40#ibcon#end of sib2, iclass 10, count 2 2006.253.07:38:59.40#ibcon#*after write, iclass 10, count 2 2006.253.07:38:59.40#ibcon#*before return 0, iclass 10, count 2 2006.253.07:38:59.40#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.253.07:38:59.40#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.253.07:38:59.40#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.253.07:38:59.40#ibcon#ireg 7 cls_cnt 0 2006.253.07:38:59.40#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.253.07:38:59.52#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.253.07:38:59.52#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.253.07:38:59.52#ibcon#enter wrdev, iclass 10, count 0 2006.253.07:38:59.52#ibcon#first serial, iclass 10, count 0 2006.253.07:38:59.52#ibcon#enter sib2, iclass 10, count 0 2006.253.07:38:59.52#ibcon#flushed, iclass 10, count 0 2006.253.07:38:59.52#ibcon#about to write, iclass 10, count 0 2006.253.07:38:59.52#ibcon#wrote, iclass 10, count 0 2006.253.07:38:59.52#ibcon#about to read 3, iclass 10, count 0 2006.253.07:38:59.54#ibcon#read 3, iclass 10, count 0 2006.253.07:38:59.54#ibcon#about to read 4, iclass 10, count 0 2006.253.07:38:59.54#ibcon#read 4, iclass 10, count 0 2006.253.07:38:59.54#ibcon#about to read 5, iclass 10, count 0 2006.253.07:38:59.54#ibcon#read 5, iclass 10, count 0 2006.253.07:38:59.54#ibcon#about to read 6, iclass 10, count 0 2006.253.07:38:59.54#ibcon#read 6, iclass 10, count 0 2006.253.07:38:59.54#ibcon#end of sib2, iclass 10, count 0 2006.253.07:38:59.54#ibcon#*mode == 0, iclass 10, count 0 2006.253.07:38:59.54#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.253.07:38:59.54#ibcon#[25=USB\r\n] 2006.253.07:38:59.54#ibcon#*before write, iclass 10, count 0 2006.253.07:38:59.54#ibcon#enter sib2, iclass 10, count 0 2006.253.07:38:59.54#ibcon#flushed, iclass 10, count 0 2006.253.07:38:59.54#ibcon#about to write, iclass 10, count 0 2006.253.07:38:59.54#ibcon#wrote, iclass 10, count 0 2006.253.07:38:59.54#ibcon#about to read 3, iclass 10, count 0 2006.253.07:38:59.57#ibcon#read 3, iclass 10, count 0 2006.253.07:38:59.57#ibcon#about to read 4, iclass 10, count 0 2006.253.07:38:59.57#ibcon#read 4, iclass 10, count 0 2006.253.07:38:59.57#ibcon#about to read 5, iclass 10, count 0 2006.253.07:38:59.57#ibcon#read 5, iclass 10, count 0 2006.253.07:38:59.57#ibcon#about to read 6, iclass 10, count 0 2006.253.07:38:59.57#ibcon#read 6, iclass 10, count 0 2006.253.07:38:59.57#ibcon#end of sib2, iclass 10, count 0 2006.253.07:38:59.57#ibcon#*after write, iclass 10, count 0 2006.253.07:38:59.57#ibcon#*before return 0, iclass 10, count 0 2006.253.07:38:59.57#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.253.07:38:59.57#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.253.07:38:59.57#ibcon#about to clear, iclass 10 cls_cnt 0 2006.253.07:38:59.57#ibcon#cleared, iclass 10 cls_cnt 0 2006.253.07:38:59.57$vc4f8/valo=6,772.99 2006.253.07:38:59.57#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.253.07:38:59.57#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.253.07:38:59.57#ibcon#ireg 17 cls_cnt 0 2006.253.07:38:59.57#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.253.07:38:59.57#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.253.07:38:59.57#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.253.07:38:59.57#ibcon#enter wrdev, iclass 12, count 0 2006.253.07:38:59.57#ibcon#first serial, iclass 12, count 0 2006.253.07:38:59.57#ibcon#enter sib2, iclass 12, count 0 2006.253.07:38:59.57#ibcon#flushed, iclass 12, count 0 2006.253.07:38:59.57#ibcon#about to write, iclass 12, count 0 2006.253.07:38:59.57#ibcon#wrote, iclass 12, count 0 2006.253.07:38:59.57#ibcon#about to read 3, iclass 12, count 0 2006.253.07:38:59.59#ibcon#read 3, iclass 12, count 0 2006.253.07:38:59.59#ibcon#about to read 4, iclass 12, count 0 2006.253.07:38:59.59#ibcon#read 4, iclass 12, count 0 2006.253.07:38:59.59#ibcon#about to read 5, iclass 12, count 0 2006.253.07:38:59.59#ibcon#read 5, iclass 12, count 0 2006.253.07:38:59.59#ibcon#about to read 6, iclass 12, count 0 2006.253.07:38:59.59#ibcon#read 6, iclass 12, count 0 2006.253.07:38:59.59#ibcon#end of sib2, iclass 12, count 0 2006.253.07:38:59.59#ibcon#*mode == 0, iclass 12, count 0 2006.253.07:38:59.59#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.253.07:38:59.59#ibcon#[26=FRQ=06,772.99\r\n] 2006.253.07:38:59.59#ibcon#*before write, iclass 12, count 0 2006.253.07:38:59.59#ibcon#enter sib2, iclass 12, count 0 2006.253.07:38:59.59#ibcon#flushed, iclass 12, count 0 2006.253.07:38:59.59#ibcon#about to write, iclass 12, count 0 2006.253.07:38:59.59#ibcon#wrote, iclass 12, count 0 2006.253.07:38:59.59#ibcon#about to read 3, iclass 12, count 0 2006.253.07:38:59.64#ibcon#read 3, iclass 12, count 0 2006.253.07:38:59.64#ibcon#about to read 4, iclass 12, count 0 2006.253.07:38:59.64#ibcon#read 4, iclass 12, count 0 2006.253.07:38:59.64#ibcon#about to read 5, iclass 12, count 0 2006.253.07:38:59.64#ibcon#read 5, iclass 12, count 0 2006.253.07:38:59.64#ibcon#about to read 6, iclass 12, count 0 2006.253.07:38:59.64#ibcon#read 6, iclass 12, count 0 2006.253.07:38:59.64#ibcon#end of sib2, iclass 12, count 0 2006.253.07:38:59.64#ibcon#*after write, iclass 12, count 0 2006.253.07:38:59.64#ibcon#*before return 0, iclass 12, count 0 2006.253.07:38:59.64#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.253.07:38:59.64#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.253.07:38:59.64#ibcon#about to clear, iclass 12 cls_cnt 0 2006.253.07:38:59.64#ibcon#cleared, iclass 12 cls_cnt 0 2006.253.07:38:59.64$vc4f8/va=6,7 2006.253.07:38:59.64#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.253.07:38:59.64#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.253.07:38:59.64#ibcon#ireg 11 cls_cnt 2 2006.253.07:38:59.64#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.253.07:38:59.69#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.253.07:38:59.69#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.253.07:38:59.69#ibcon#enter wrdev, iclass 14, count 2 2006.253.07:38:59.69#ibcon#first serial, iclass 14, count 2 2006.253.07:38:59.69#ibcon#enter sib2, iclass 14, count 2 2006.253.07:38:59.69#ibcon#flushed, iclass 14, count 2 2006.253.07:38:59.69#ibcon#about to write, iclass 14, count 2 2006.253.07:38:59.69#ibcon#wrote, iclass 14, count 2 2006.253.07:38:59.69#ibcon#about to read 3, iclass 14, count 2 2006.253.07:38:59.71#ibcon#read 3, iclass 14, count 2 2006.253.07:38:59.71#ibcon#about to read 4, iclass 14, count 2 2006.253.07:38:59.71#ibcon#read 4, iclass 14, count 2 2006.253.07:38:59.71#ibcon#about to read 5, iclass 14, count 2 2006.253.07:38:59.71#ibcon#read 5, iclass 14, count 2 2006.253.07:38:59.71#ibcon#about to read 6, iclass 14, count 2 2006.253.07:38:59.71#ibcon#read 6, iclass 14, count 2 2006.253.07:38:59.71#ibcon#end of sib2, iclass 14, count 2 2006.253.07:38:59.71#ibcon#*mode == 0, iclass 14, count 2 2006.253.07:38:59.71#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.253.07:38:59.71#ibcon#[25=AT06-07\r\n] 2006.253.07:38:59.71#ibcon#*before write, iclass 14, count 2 2006.253.07:38:59.71#ibcon#enter sib2, iclass 14, count 2 2006.253.07:38:59.71#ibcon#flushed, iclass 14, count 2 2006.253.07:38:59.71#ibcon#about to write, iclass 14, count 2 2006.253.07:38:59.71#ibcon#wrote, iclass 14, count 2 2006.253.07:38:59.71#ibcon#about to read 3, iclass 14, count 2 2006.253.07:38:59.74#ibcon#read 3, iclass 14, count 2 2006.253.07:38:59.74#ibcon#about to read 4, iclass 14, count 2 2006.253.07:38:59.74#ibcon#read 4, iclass 14, count 2 2006.253.07:38:59.74#ibcon#about to read 5, iclass 14, count 2 2006.253.07:38:59.74#ibcon#read 5, iclass 14, count 2 2006.253.07:38:59.74#ibcon#about to read 6, iclass 14, count 2 2006.253.07:38:59.74#ibcon#read 6, iclass 14, count 2 2006.253.07:38:59.74#ibcon#end of sib2, iclass 14, count 2 2006.253.07:38:59.74#ibcon#*after write, iclass 14, count 2 2006.253.07:38:59.74#ibcon#*before return 0, iclass 14, count 2 2006.253.07:38:59.74#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.253.07:38:59.74#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.253.07:38:59.74#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.253.07:38:59.74#ibcon#ireg 7 cls_cnt 0 2006.253.07:38:59.74#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.253.07:38:59.86#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.253.07:38:59.86#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.253.07:38:59.86#ibcon#enter wrdev, iclass 14, count 0 2006.253.07:38:59.86#ibcon#first serial, iclass 14, count 0 2006.253.07:38:59.86#ibcon#enter sib2, iclass 14, count 0 2006.253.07:38:59.86#ibcon#flushed, iclass 14, count 0 2006.253.07:38:59.86#ibcon#about to write, iclass 14, count 0 2006.253.07:38:59.86#ibcon#wrote, iclass 14, count 0 2006.253.07:38:59.86#ibcon#about to read 3, iclass 14, count 0 2006.253.07:38:59.88#ibcon#read 3, iclass 14, count 0 2006.253.07:38:59.88#ibcon#about to read 4, iclass 14, count 0 2006.253.07:38:59.88#ibcon#read 4, iclass 14, count 0 2006.253.07:38:59.88#ibcon#about to read 5, iclass 14, count 0 2006.253.07:38:59.88#ibcon#read 5, iclass 14, count 0 2006.253.07:38:59.88#ibcon#about to read 6, iclass 14, count 0 2006.253.07:38:59.88#ibcon#read 6, iclass 14, count 0 2006.253.07:38:59.88#ibcon#end of sib2, iclass 14, count 0 2006.253.07:38:59.88#ibcon#*mode == 0, iclass 14, count 0 2006.253.07:38:59.88#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.253.07:38:59.88#ibcon#[25=USB\r\n] 2006.253.07:38:59.88#ibcon#*before write, iclass 14, count 0 2006.253.07:38:59.88#ibcon#enter sib2, iclass 14, count 0 2006.253.07:38:59.88#ibcon#flushed, iclass 14, count 0 2006.253.07:38:59.88#ibcon#about to write, iclass 14, count 0 2006.253.07:38:59.88#ibcon#wrote, iclass 14, count 0 2006.253.07:38:59.88#ibcon#about to read 3, iclass 14, count 0 2006.253.07:38:59.91#ibcon#read 3, iclass 14, count 0 2006.253.07:38:59.91#ibcon#about to read 4, iclass 14, count 0 2006.253.07:38:59.91#ibcon#read 4, iclass 14, count 0 2006.253.07:38:59.91#ibcon#about to read 5, iclass 14, count 0 2006.253.07:38:59.91#ibcon#read 5, iclass 14, count 0 2006.253.07:38:59.91#ibcon#about to read 6, iclass 14, count 0 2006.253.07:38:59.91#ibcon#read 6, iclass 14, count 0 2006.253.07:38:59.91#ibcon#end of sib2, iclass 14, count 0 2006.253.07:38:59.91#ibcon#*after write, iclass 14, count 0 2006.253.07:38:59.91#ibcon#*before return 0, iclass 14, count 0 2006.253.07:38:59.91#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.253.07:38:59.91#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.253.07:38:59.91#ibcon#about to clear, iclass 14 cls_cnt 0 2006.253.07:38:59.91#ibcon#cleared, iclass 14 cls_cnt 0 2006.253.07:38:59.91$vc4f8/valo=7,832.99 2006.253.07:38:59.91#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.253.07:38:59.91#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.253.07:38:59.91#ibcon#ireg 17 cls_cnt 0 2006.253.07:38:59.91#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.253.07:38:59.91#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.253.07:38:59.91#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.253.07:38:59.91#ibcon#enter wrdev, iclass 16, count 0 2006.253.07:38:59.91#ibcon#first serial, iclass 16, count 0 2006.253.07:38:59.91#ibcon#enter sib2, iclass 16, count 0 2006.253.07:38:59.91#ibcon#flushed, iclass 16, count 0 2006.253.07:38:59.91#ibcon#about to write, iclass 16, count 0 2006.253.07:38:59.91#ibcon#wrote, iclass 16, count 0 2006.253.07:38:59.91#ibcon#about to read 3, iclass 16, count 0 2006.253.07:38:59.93#ibcon#read 3, iclass 16, count 0 2006.253.07:38:59.93#ibcon#about to read 4, iclass 16, count 0 2006.253.07:38:59.93#ibcon#read 4, iclass 16, count 0 2006.253.07:38:59.93#ibcon#about to read 5, iclass 16, count 0 2006.253.07:38:59.93#ibcon#read 5, iclass 16, count 0 2006.253.07:38:59.93#ibcon#about to read 6, iclass 16, count 0 2006.253.07:38:59.93#ibcon#read 6, iclass 16, count 0 2006.253.07:38:59.93#ibcon#end of sib2, iclass 16, count 0 2006.253.07:38:59.93#ibcon#*mode == 0, iclass 16, count 0 2006.253.07:38:59.93#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.253.07:38:59.93#ibcon#[26=FRQ=07,832.99\r\n] 2006.253.07:38:59.93#ibcon#*before write, iclass 16, count 0 2006.253.07:38:59.93#ibcon#enter sib2, iclass 16, count 0 2006.253.07:38:59.93#ibcon#flushed, iclass 16, count 0 2006.253.07:38:59.93#ibcon#about to write, iclass 16, count 0 2006.253.07:38:59.93#ibcon#wrote, iclass 16, count 0 2006.253.07:38:59.93#ibcon#about to read 3, iclass 16, count 0 2006.253.07:38:59.97#ibcon#read 3, iclass 16, count 0 2006.253.07:38:59.97#ibcon#about to read 4, iclass 16, count 0 2006.253.07:38:59.97#ibcon#read 4, iclass 16, count 0 2006.253.07:38:59.97#ibcon#about to read 5, iclass 16, count 0 2006.253.07:38:59.97#ibcon#read 5, iclass 16, count 0 2006.253.07:38:59.97#ibcon#about to read 6, iclass 16, count 0 2006.253.07:38:59.97#ibcon#read 6, iclass 16, count 0 2006.253.07:38:59.97#ibcon#end of sib2, iclass 16, count 0 2006.253.07:38:59.97#ibcon#*after write, iclass 16, count 0 2006.253.07:38:59.97#ibcon#*before return 0, iclass 16, count 0 2006.253.07:38:59.97#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.253.07:38:59.97#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.253.07:38:59.97#ibcon#about to clear, iclass 16 cls_cnt 0 2006.253.07:38:59.97#ibcon#cleared, iclass 16 cls_cnt 0 2006.253.07:38:59.97$vc4f8/va=7,7 2006.253.07:38:59.97#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.253.07:38:59.97#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.253.07:38:59.97#ibcon#ireg 11 cls_cnt 2 2006.253.07:38:59.97#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.253.07:39:00.03#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.253.07:39:00.03#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.253.07:39:00.03#ibcon#enter wrdev, iclass 18, count 2 2006.253.07:39:00.03#ibcon#first serial, iclass 18, count 2 2006.253.07:39:00.03#ibcon#enter sib2, iclass 18, count 2 2006.253.07:39:00.03#ibcon#flushed, iclass 18, count 2 2006.253.07:39:00.03#ibcon#about to write, iclass 18, count 2 2006.253.07:39:00.03#ibcon#wrote, iclass 18, count 2 2006.253.07:39:00.03#ibcon#about to read 3, iclass 18, count 2 2006.253.07:39:00.05#ibcon#read 3, iclass 18, count 2 2006.253.07:39:00.05#ibcon#about to read 4, iclass 18, count 2 2006.253.07:39:00.05#ibcon#read 4, iclass 18, count 2 2006.253.07:39:00.05#ibcon#about to read 5, iclass 18, count 2 2006.253.07:39:00.05#ibcon#read 5, iclass 18, count 2 2006.253.07:39:00.05#ibcon#about to read 6, iclass 18, count 2 2006.253.07:39:00.05#ibcon#read 6, iclass 18, count 2 2006.253.07:39:00.05#ibcon#end of sib2, iclass 18, count 2 2006.253.07:39:00.05#ibcon#*mode == 0, iclass 18, count 2 2006.253.07:39:00.05#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.253.07:39:00.05#ibcon#[25=AT07-07\r\n] 2006.253.07:39:00.05#ibcon#*before write, iclass 18, count 2 2006.253.07:39:00.05#ibcon#enter sib2, iclass 18, count 2 2006.253.07:39:00.05#ibcon#flushed, iclass 18, count 2 2006.253.07:39:00.05#ibcon#about to write, iclass 18, count 2 2006.253.07:39:00.05#ibcon#wrote, iclass 18, count 2 2006.253.07:39:00.05#ibcon#about to read 3, iclass 18, count 2 2006.253.07:39:00.08#ibcon#read 3, iclass 18, count 2 2006.253.07:39:00.08#ibcon#about to read 4, iclass 18, count 2 2006.253.07:39:00.08#ibcon#read 4, iclass 18, count 2 2006.253.07:39:00.08#ibcon#about to read 5, iclass 18, count 2 2006.253.07:39:00.08#ibcon#read 5, iclass 18, count 2 2006.253.07:39:00.08#ibcon#about to read 6, iclass 18, count 2 2006.253.07:39:00.08#ibcon#read 6, iclass 18, count 2 2006.253.07:39:00.08#ibcon#end of sib2, iclass 18, count 2 2006.253.07:39:00.08#ibcon#*after write, iclass 18, count 2 2006.253.07:39:00.08#ibcon#*before return 0, iclass 18, count 2 2006.253.07:39:00.08#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.253.07:39:00.08#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.253.07:39:00.08#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.253.07:39:00.08#ibcon#ireg 7 cls_cnt 0 2006.253.07:39:00.08#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.253.07:39:00.20#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.253.07:39:00.20#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.253.07:39:00.20#ibcon#enter wrdev, iclass 18, count 0 2006.253.07:39:00.20#ibcon#first serial, iclass 18, count 0 2006.253.07:39:00.20#ibcon#enter sib2, iclass 18, count 0 2006.253.07:39:00.20#ibcon#flushed, iclass 18, count 0 2006.253.07:39:00.20#ibcon#about to write, iclass 18, count 0 2006.253.07:39:00.20#ibcon#wrote, iclass 18, count 0 2006.253.07:39:00.20#ibcon#about to read 3, iclass 18, count 0 2006.253.07:39:00.22#ibcon#read 3, iclass 18, count 0 2006.253.07:39:00.22#ibcon#about to read 4, iclass 18, count 0 2006.253.07:39:00.22#ibcon#read 4, iclass 18, count 0 2006.253.07:39:00.22#ibcon#about to read 5, iclass 18, count 0 2006.253.07:39:00.22#ibcon#read 5, iclass 18, count 0 2006.253.07:39:00.22#ibcon#about to read 6, iclass 18, count 0 2006.253.07:39:00.22#ibcon#read 6, iclass 18, count 0 2006.253.07:39:00.22#ibcon#end of sib2, iclass 18, count 0 2006.253.07:39:00.22#ibcon#*mode == 0, iclass 18, count 0 2006.253.07:39:00.22#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.253.07:39:00.22#ibcon#[25=USB\r\n] 2006.253.07:39:00.22#ibcon#*before write, iclass 18, count 0 2006.253.07:39:00.22#ibcon#enter sib2, iclass 18, count 0 2006.253.07:39:00.22#ibcon#flushed, iclass 18, count 0 2006.253.07:39:00.22#ibcon#about to write, iclass 18, count 0 2006.253.07:39:00.22#ibcon#wrote, iclass 18, count 0 2006.253.07:39:00.22#ibcon#about to read 3, iclass 18, count 0 2006.253.07:39:00.25#ibcon#read 3, iclass 18, count 0 2006.253.07:39:00.25#ibcon#about to read 4, iclass 18, count 0 2006.253.07:39:00.25#ibcon#read 4, iclass 18, count 0 2006.253.07:39:00.25#ibcon#about to read 5, iclass 18, count 0 2006.253.07:39:00.25#ibcon#read 5, iclass 18, count 0 2006.253.07:39:00.25#ibcon#about to read 6, iclass 18, count 0 2006.253.07:39:00.25#ibcon#read 6, iclass 18, count 0 2006.253.07:39:00.25#ibcon#end of sib2, iclass 18, count 0 2006.253.07:39:00.25#ibcon#*after write, iclass 18, count 0 2006.253.07:39:00.25#ibcon#*before return 0, iclass 18, count 0 2006.253.07:39:00.25#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.253.07:39:00.25#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.253.07:39:00.25#ibcon#about to clear, iclass 18 cls_cnt 0 2006.253.07:39:00.25#ibcon#cleared, iclass 18 cls_cnt 0 2006.253.07:39:00.25$vc4f8/valo=8,852.99 2006.253.07:39:00.25#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.253.07:39:00.25#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.253.07:39:00.25#ibcon#ireg 17 cls_cnt 0 2006.253.07:39:00.25#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.253.07:39:00.25#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.253.07:39:00.25#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.253.07:39:00.25#ibcon#enter wrdev, iclass 20, count 0 2006.253.07:39:00.25#ibcon#first serial, iclass 20, count 0 2006.253.07:39:00.25#ibcon#enter sib2, iclass 20, count 0 2006.253.07:39:00.25#ibcon#flushed, iclass 20, count 0 2006.253.07:39:00.25#ibcon#about to write, iclass 20, count 0 2006.253.07:39:00.25#ibcon#wrote, iclass 20, count 0 2006.253.07:39:00.25#ibcon#about to read 3, iclass 20, count 0 2006.253.07:39:00.27#ibcon#read 3, iclass 20, count 0 2006.253.07:39:00.27#ibcon#about to read 4, iclass 20, count 0 2006.253.07:39:00.27#ibcon#read 4, iclass 20, count 0 2006.253.07:39:00.27#ibcon#about to read 5, iclass 20, count 0 2006.253.07:39:00.27#ibcon#read 5, iclass 20, count 0 2006.253.07:39:00.27#ibcon#about to read 6, iclass 20, count 0 2006.253.07:39:00.27#ibcon#read 6, iclass 20, count 0 2006.253.07:39:00.27#ibcon#end of sib2, iclass 20, count 0 2006.253.07:39:00.27#ibcon#*mode == 0, iclass 20, count 0 2006.253.07:39:00.27#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.253.07:39:00.27#ibcon#[26=FRQ=08,852.99\r\n] 2006.253.07:39:00.27#ibcon#*before write, iclass 20, count 0 2006.253.07:39:00.27#ibcon#enter sib2, iclass 20, count 0 2006.253.07:39:00.27#ibcon#flushed, iclass 20, count 0 2006.253.07:39:00.27#ibcon#about to write, iclass 20, count 0 2006.253.07:39:00.27#ibcon#wrote, iclass 20, count 0 2006.253.07:39:00.27#ibcon#about to read 3, iclass 20, count 0 2006.253.07:39:00.31#ibcon#read 3, iclass 20, count 0 2006.253.07:39:00.31#ibcon#about to read 4, iclass 20, count 0 2006.253.07:39:00.31#ibcon#read 4, iclass 20, count 0 2006.253.07:39:00.31#ibcon#about to read 5, iclass 20, count 0 2006.253.07:39:00.31#ibcon#read 5, iclass 20, count 0 2006.253.07:39:00.31#ibcon#about to read 6, iclass 20, count 0 2006.253.07:39:00.31#ibcon#read 6, iclass 20, count 0 2006.253.07:39:00.31#ibcon#end of sib2, iclass 20, count 0 2006.253.07:39:00.31#ibcon#*after write, iclass 20, count 0 2006.253.07:39:00.31#ibcon#*before return 0, iclass 20, count 0 2006.253.07:39:00.31#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.253.07:39:00.31#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.253.07:39:00.31#ibcon#about to clear, iclass 20 cls_cnt 0 2006.253.07:39:00.31#ibcon#cleared, iclass 20 cls_cnt 0 2006.253.07:39:00.31$vc4f8/va=8,7 2006.253.07:39:00.31#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.253.07:39:00.31#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.253.07:39:00.31#ibcon#ireg 11 cls_cnt 2 2006.253.07:39:00.31#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.253.07:39:00.37#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.253.07:39:00.37#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.253.07:39:00.37#ibcon#enter wrdev, iclass 22, count 2 2006.253.07:39:00.37#ibcon#first serial, iclass 22, count 2 2006.253.07:39:00.37#ibcon#enter sib2, iclass 22, count 2 2006.253.07:39:00.37#ibcon#flushed, iclass 22, count 2 2006.253.07:39:00.37#ibcon#about to write, iclass 22, count 2 2006.253.07:39:00.37#ibcon#wrote, iclass 22, count 2 2006.253.07:39:00.37#ibcon#about to read 3, iclass 22, count 2 2006.253.07:39:00.39#ibcon#read 3, iclass 22, count 2 2006.253.07:39:00.39#ibcon#about to read 4, iclass 22, count 2 2006.253.07:39:00.39#ibcon#read 4, iclass 22, count 2 2006.253.07:39:00.39#ibcon#about to read 5, iclass 22, count 2 2006.253.07:39:00.39#ibcon#read 5, iclass 22, count 2 2006.253.07:39:00.39#ibcon#about to read 6, iclass 22, count 2 2006.253.07:39:00.39#ibcon#read 6, iclass 22, count 2 2006.253.07:39:00.39#ibcon#end of sib2, iclass 22, count 2 2006.253.07:39:00.39#ibcon#*mode == 0, iclass 22, count 2 2006.253.07:39:00.39#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.253.07:39:00.39#ibcon#[25=AT08-07\r\n] 2006.253.07:39:00.39#ibcon#*before write, iclass 22, count 2 2006.253.07:39:00.39#ibcon#enter sib2, iclass 22, count 2 2006.253.07:39:00.39#ibcon#flushed, iclass 22, count 2 2006.253.07:39:00.39#ibcon#about to write, iclass 22, count 2 2006.253.07:39:00.39#ibcon#wrote, iclass 22, count 2 2006.253.07:39:00.39#ibcon#about to read 3, iclass 22, count 2 2006.253.07:39:00.42#ibcon#read 3, iclass 22, count 2 2006.253.07:39:00.42#ibcon#about to read 4, iclass 22, count 2 2006.253.07:39:00.42#ibcon#read 4, iclass 22, count 2 2006.253.07:39:00.42#ibcon#about to read 5, iclass 22, count 2 2006.253.07:39:00.42#ibcon#read 5, iclass 22, count 2 2006.253.07:39:00.42#ibcon#about to read 6, iclass 22, count 2 2006.253.07:39:00.42#ibcon#read 6, iclass 22, count 2 2006.253.07:39:00.42#ibcon#end of sib2, iclass 22, count 2 2006.253.07:39:00.42#ibcon#*after write, iclass 22, count 2 2006.253.07:39:00.42#ibcon#*before return 0, iclass 22, count 2 2006.253.07:39:00.42#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.253.07:39:00.42#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.253.07:39:00.42#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.253.07:39:00.42#ibcon#ireg 7 cls_cnt 0 2006.253.07:39:00.42#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.253.07:39:00.54#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.253.07:39:00.54#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.253.07:39:00.54#ibcon#enter wrdev, iclass 22, count 0 2006.253.07:39:00.54#ibcon#first serial, iclass 22, count 0 2006.253.07:39:00.54#ibcon#enter sib2, iclass 22, count 0 2006.253.07:39:00.54#ibcon#flushed, iclass 22, count 0 2006.253.07:39:00.54#ibcon#about to write, iclass 22, count 0 2006.253.07:39:00.54#ibcon#wrote, iclass 22, count 0 2006.253.07:39:00.54#ibcon#about to read 3, iclass 22, count 0 2006.253.07:39:00.56#ibcon#read 3, iclass 22, count 0 2006.253.07:39:00.56#ibcon#about to read 4, iclass 22, count 0 2006.253.07:39:00.56#ibcon#read 4, iclass 22, count 0 2006.253.07:39:00.56#ibcon#about to read 5, iclass 22, count 0 2006.253.07:39:00.56#ibcon#read 5, iclass 22, count 0 2006.253.07:39:00.56#ibcon#about to read 6, iclass 22, count 0 2006.253.07:39:00.56#ibcon#read 6, iclass 22, count 0 2006.253.07:39:00.56#ibcon#end of sib2, iclass 22, count 0 2006.253.07:39:00.56#ibcon#*mode == 0, iclass 22, count 0 2006.253.07:39:00.56#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.253.07:39:00.56#ibcon#[25=USB\r\n] 2006.253.07:39:00.56#ibcon#*before write, iclass 22, count 0 2006.253.07:39:00.56#ibcon#enter sib2, iclass 22, count 0 2006.253.07:39:00.56#ibcon#flushed, iclass 22, count 0 2006.253.07:39:00.56#ibcon#about to write, iclass 22, count 0 2006.253.07:39:00.56#ibcon#wrote, iclass 22, count 0 2006.253.07:39:00.56#ibcon#about to read 3, iclass 22, count 0 2006.253.07:39:00.59#ibcon#read 3, iclass 22, count 0 2006.253.07:39:00.59#ibcon#about to read 4, iclass 22, count 0 2006.253.07:39:00.59#ibcon#read 4, iclass 22, count 0 2006.253.07:39:00.59#ibcon#about to read 5, iclass 22, count 0 2006.253.07:39:00.59#ibcon#read 5, iclass 22, count 0 2006.253.07:39:00.59#ibcon#about to read 6, iclass 22, count 0 2006.253.07:39:00.59#ibcon#read 6, iclass 22, count 0 2006.253.07:39:00.59#ibcon#end of sib2, iclass 22, count 0 2006.253.07:39:00.59#ibcon#*after write, iclass 22, count 0 2006.253.07:39:00.59#ibcon#*before return 0, iclass 22, count 0 2006.253.07:39:00.59#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.253.07:39:00.59#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.253.07:39:00.59#ibcon#about to clear, iclass 22 cls_cnt 0 2006.253.07:39:00.59#ibcon#cleared, iclass 22 cls_cnt 0 2006.253.07:39:00.59$vc4f8/vblo=1,632.99 2006.253.07:39:00.59#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.253.07:39:00.59#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.253.07:39:00.59#ibcon#ireg 17 cls_cnt 0 2006.253.07:39:00.59#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.253.07:39:00.59#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.253.07:39:00.59#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.253.07:39:00.59#ibcon#enter wrdev, iclass 24, count 0 2006.253.07:39:00.59#ibcon#first serial, iclass 24, count 0 2006.253.07:39:00.59#ibcon#enter sib2, iclass 24, count 0 2006.253.07:39:00.59#ibcon#flushed, iclass 24, count 0 2006.253.07:39:00.59#ibcon#about to write, iclass 24, count 0 2006.253.07:39:00.59#ibcon#wrote, iclass 24, count 0 2006.253.07:39:00.59#ibcon#about to read 3, iclass 24, count 0 2006.253.07:39:00.61#ibcon#read 3, iclass 24, count 0 2006.253.07:39:00.61#ibcon#about to read 4, iclass 24, count 0 2006.253.07:39:00.61#ibcon#read 4, iclass 24, count 0 2006.253.07:39:00.61#ibcon#about to read 5, iclass 24, count 0 2006.253.07:39:00.61#ibcon#read 5, iclass 24, count 0 2006.253.07:39:00.61#ibcon#about to read 6, iclass 24, count 0 2006.253.07:39:00.61#ibcon#read 6, iclass 24, count 0 2006.253.07:39:00.61#ibcon#end of sib2, iclass 24, count 0 2006.253.07:39:00.61#ibcon#*mode == 0, iclass 24, count 0 2006.253.07:39:00.61#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.253.07:39:00.61#ibcon#[28=FRQ=01,632.99\r\n] 2006.253.07:39:00.61#ibcon#*before write, iclass 24, count 0 2006.253.07:39:00.61#ibcon#enter sib2, iclass 24, count 0 2006.253.07:39:00.61#ibcon#flushed, iclass 24, count 0 2006.253.07:39:00.61#ibcon#about to write, iclass 24, count 0 2006.253.07:39:00.61#ibcon#wrote, iclass 24, count 0 2006.253.07:39:00.61#ibcon#about to read 3, iclass 24, count 0 2006.253.07:39:00.65#ibcon#read 3, iclass 24, count 0 2006.253.07:39:00.65#ibcon#about to read 4, iclass 24, count 0 2006.253.07:39:00.65#ibcon#read 4, iclass 24, count 0 2006.253.07:39:00.65#ibcon#about to read 5, iclass 24, count 0 2006.253.07:39:00.65#ibcon#read 5, iclass 24, count 0 2006.253.07:39:00.65#ibcon#about to read 6, iclass 24, count 0 2006.253.07:39:00.65#ibcon#read 6, iclass 24, count 0 2006.253.07:39:00.65#ibcon#end of sib2, iclass 24, count 0 2006.253.07:39:00.65#ibcon#*after write, iclass 24, count 0 2006.253.07:39:00.65#ibcon#*before return 0, iclass 24, count 0 2006.253.07:39:00.65#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.253.07:39:00.65#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.253.07:39:00.65#ibcon#about to clear, iclass 24 cls_cnt 0 2006.253.07:39:00.65#ibcon#cleared, iclass 24 cls_cnt 0 2006.253.07:39:00.65$vc4f8/vb=1,4 2006.253.07:39:00.65#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.253.07:39:00.65#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.253.07:39:00.65#ibcon#ireg 11 cls_cnt 2 2006.253.07:39:00.65#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.253.07:39:00.65#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.253.07:39:00.65#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.253.07:39:00.65#ibcon#enter wrdev, iclass 26, count 2 2006.253.07:39:00.65#ibcon#first serial, iclass 26, count 2 2006.253.07:39:00.65#ibcon#enter sib2, iclass 26, count 2 2006.253.07:39:00.65#ibcon#flushed, iclass 26, count 2 2006.253.07:39:00.65#ibcon#about to write, iclass 26, count 2 2006.253.07:39:00.65#ibcon#wrote, iclass 26, count 2 2006.253.07:39:00.65#ibcon#about to read 3, iclass 26, count 2 2006.253.07:39:00.67#ibcon#read 3, iclass 26, count 2 2006.253.07:39:00.67#ibcon#about to read 4, iclass 26, count 2 2006.253.07:39:00.67#ibcon#read 4, iclass 26, count 2 2006.253.07:39:00.67#ibcon#about to read 5, iclass 26, count 2 2006.253.07:39:00.67#ibcon#read 5, iclass 26, count 2 2006.253.07:39:00.67#ibcon#about to read 6, iclass 26, count 2 2006.253.07:39:00.67#ibcon#read 6, iclass 26, count 2 2006.253.07:39:00.67#ibcon#end of sib2, iclass 26, count 2 2006.253.07:39:00.67#ibcon#*mode == 0, iclass 26, count 2 2006.253.07:39:00.67#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.253.07:39:00.67#ibcon#[27=AT01-04\r\n] 2006.253.07:39:00.67#ibcon#*before write, iclass 26, count 2 2006.253.07:39:00.67#ibcon#enter sib2, iclass 26, count 2 2006.253.07:39:00.67#ibcon#flushed, iclass 26, count 2 2006.253.07:39:00.67#ibcon#about to write, iclass 26, count 2 2006.253.07:39:00.67#ibcon#wrote, iclass 26, count 2 2006.253.07:39:00.67#ibcon#about to read 3, iclass 26, count 2 2006.253.07:39:00.70#ibcon#read 3, iclass 26, count 2 2006.253.07:39:00.70#ibcon#about to read 4, iclass 26, count 2 2006.253.07:39:00.70#ibcon#read 4, iclass 26, count 2 2006.253.07:39:00.70#ibcon#about to read 5, iclass 26, count 2 2006.253.07:39:00.70#ibcon#read 5, iclass 26, count 2 2006.253.07:39:00.70#ibcon#about to read 6, iclass 26, count 2 2006.253.07:39:00.70#ibcon#read 6, iclass 26, count 2 2006.253.07:39:00.70#ibcon#end of sib2, iclass 26, count 2 2006.253.07:39:00.70#ibcon#*after write, iclass 26, count 2 2006.253.07:39:00.70#ibcon#*before return 0, iclass 26, count 2 2006.253.07:39:00.70#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.253.07:39:00.70#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.253.07:39:00.70#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.253.07:39:00.70#ibcon#ireg 7 cls_cnt 0 2006.253.07:39:00.70#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.253.07:39:00.82#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.253.07:39:00.82#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.253.07:39:00.82#ibcon#enter wrdev, iclass 26, count 0 2006.253.07:39:00.82#ibcon#first serial, iclass 26, count 0 2006.253.07:39:00.82#ibcon#enter sib2, iclass 26, count 0 2006.253.07:39:00.82#ibcon#flushed, iclass 26, count 0 2006.253.07:39:00.82#ibcon#about to write, iclass 26, count 0 2006.253.07:39:00.82#ibcon#wrote, iclass 26, count 0 2006.253.07:39:00.82#ibcon#about to read 3, iclass 26, count 0 2006.253.07:39:00.84#ibcon#read 3, iclass 26, count 0 2006.253.07:39:00.84#ibcon#about to read 4, iclass 26, count 0 2006.253.07:39:00.84#ibcon#read 4, iclass 26, count 0 2006.253.07:39:00.84#ibcon#about to read 5, iclass 26, count 0 2006.253.07:39:00.84#ibcon#read 5, iclass 26, count 0 2006.253.07:39:00.84#ibcon#about to read 6, iclass 26, count 0 2006.253.07:39:00.84#ibcon#read 6, iclass 26, count 0 2006.253.07:39:00.84#ibcon#end of sib2, iclass 26, count 0 2006.253.07:39:00.84#ibcon#*mode == 0, iclass 26, count 0 2006.253.07:39:00.84#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.253.07:39:00.84#ibcon#[27=USB\r\n] 2006.253.07:39:00.84#ibcon#*before write, iclass 26, count 0 2006.253.07:39:00.84#ibcon#enter sib2, iclass 26, count 0 2006.253.07:39:00.84#ibcon#flushed, iclass 26, count 0 2006.253.07:39:00.84#ibcon#about to write, iclass 26, count 0 2006.253.07:39:00.84#ibcon#wrote, iclass 26, count 0 2006.253.07:39:00.84#ibcon#about to read 3, iclass 26, count 0 2006.253.07:39:00.87#ibcon#read 3, iclass 26, count 0 2006.253.07:39:00.87#ibcon#about to read 4, iclass 26, count 0 2006.253.07:39:00.87#ibcon#read 4, iclass 26, count 0 2006.253.07:39:00.87#ibcon#about to read 5, iclass 26, count 0 2006.253.07:39:00.87#ibcon#read 5, iclass 26, count 0 2006.253.07:39:00.87#ibcon#about to read 6, iclass 26, count 0 2006.253.07:39:00.87#ibcon#read 6, iclass 26, count 0 2006.253.07:39:00.87#ibcon#end of sib2, iclass 26, count 0 2006.253.07:39:00.87#ibcon#*after write, iclass 26, count 0 2006.253.07:39:00.87#ibcon#*before return 0, iclass 26, count 0 2006.253.07:39:00.87#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.253.07:39:00.87#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.253.07:39:00.87#ibcon#about to clear, iclass 26 cls_cnt 0 2006.253.07:39:00.87#ibcon#cleared, iclass 26 cls_cnt 0 2006.253.07:39:00.87$vc4f8/vblo=2,640.99 2006.253.07:39:00.87#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.253.07:39:00.87#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.253.07:39:00.87#ibcon#ireg 17 cls_cnt 0 2006.253.07:39:00.87#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.253.07:39:00.87#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.253.07:39:00.87#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.253.07:39:00.87#ibcon#enter wrdev, iclass 28, count 0 2006.253.07:39:00.87#ibcon#first serial, iclass 28, count 0 2006.253.07:39:00.87#ibcon#enter sib2, iclass 28, count 0 2006.253.07:39:00.87#ibcon#flushed, iclass 28, count 0 2006.253.07:39:00.87#ibcon#about to write, iclass 28, count 0 2006.253.07:39:00.87#ibcon#wrote, iclass 28, count 0 2006.253.07:39:00.87#ibcon#about to read 3, iclass 28, count 0 2006.253.07:39:00.89#ibcon#read 3, iclass 28, count 0 2006.253.07:39:00.89#ibcon#about to read 4, iclass 28, count 0 2006.253.07:39:00.89#ibcon#read 4, iclass 28, count 0 2006.253.07:39:00.89#ibcon#about to read 5, iclass 28, count 0 2006.253.07:39:00.89#ibcon#read 5, iclass 28, count 0 2006.253.07:39:00.89#ibcon#about to read 6, iclass 28, count 0 2006.253.07:39:00.89#ibcon#read 6, iclass 28, count 0 2006.253.07:39:00.89#ibcon#end of sib2, iclass 28, count 0 2006.253.07:39:00.89#ibcon#*mode == 0, iclass 28, count 0 2006.253.07:39:00.89#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.253.07:39:00.89#ibcon#[28=FRQ=02,640.99\r\n] 2006.253.07:39:00.89#ibcon#*before write, iclass 28, count 0 2006.253.07:39:00.89#ibcon#enter sib2, iclass 28, count 0 2006.253.07:39:00.89#ibcon#flushed, iclass 28, count 0 2006.253.07:39:00.89#ibcon#about to write, iclass 28, count 0 2006.253.07:39:00.89#ibcon#wrote, iclass 28, count 0 2006.253.07:39:00.89#ibcon#about to read 3, iclass 28, count 0 2006.253.07:39:00.93#ibcon#read 3, iclass 28, count 0 2006.253.07:39:00.93#ibcon#about to read 4, iclass 28, count 0 2006.253.07:39:00.93#ibcon#read 4, iclass 28, count 0 2006.253.07:39:00.93#ibcon#about to read 5, iclass 28, count 0 2006.253.07:39:00.93#ibcon#read 5, iclass 28, count 0 2006.253.07:39:00.93#ibcon#about to read 6, iclass 28, count 0 2006.253.07:39:00.93#ibcon#read 6, iclass 28, count 0 2006.253.07:39:00.93#ibcon#end of sib2, iclass 28, count 0 2006.253.07:39:00.93#ibcon#*after write, iclass 28, count 0 2006.253.07:39:00.93#ibcon#*before return 0, iclass 28, count 0 2006.253.07:39:00.93#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.253.07:39:00.93#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.253.07:39:00.93#ibcon#about to clear, iclass 28 cls_cnt 0 2006.253.07:39:00.93#ibcon#cleared, iclass 28 cls_cnt 0 2006.253.07:39:00.93$vc4f8/vb=2,5 2006.253.07:39:00.93#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.253.07:39:00.93#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.253.07:39:00.93#ibcon#ireg 11 cls_cnt 2 2006.253.07:39:00.93#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.253.07:39:00.99#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.253.07:39:00.99#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.253.07:39:00.99#ibcon#enter wrdev, iclass 30, count 2 2006.253.07:39:00.99#ibcon#first serial, iclass 30, count 2 2006.253.07:39:00.99#ibcon#enter sib2, iclass 30, count 2 2006.253.07:39:00.99#ibcon#flushed, iclass 30, count 2 2006.253.07:39:00.99#ibcon#about to write, iclass 30, count 2 2006.253.07:39:00.99#ibcon#wrote, iclass 30, count 2 2006.253.07:39:00.99#ibcon#about to read 3, iclass 30, count 2 2006.253.07:39:01.01#ibcon#read 3, iclass 30, count 2 2006.253.07:39:01.01#ibcon#about to read 4, iclass 30, count 2 2006.253.07:39:01.01#ibcon#read 4, iclass 30, count 2 2006.253.07:39:01.01#ibcon#about to read 5, iclass 30, count 2 2006.253.07:39:01.01#ibcon#read 5, iclass 30, count 2 2006.253.07:39:01.01#ibcon#about to read 6, iclass 30, count 2 2006.253.07:39:01.01#ibcon#read 6, iclass 30, count 2 2006.253.07:39:01.01#ibcon#end of sib2, iclass 30, count 2 2006.253.07:39:01.01#ibcon#*mode == 0, iclass 30, count 2 2006.253.07:39:01.01#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.253.07:39:01.01#ibcon#[27=AT02-05\r\n] 2006.253.07:39:01.01#ibcon#*before write, iclass 30, count 2 2006.253.07:39:01.01#ibcon#enter sib2, iclass 30, count 2 2006.253.07:39:01.01#ibcon#flushed, iclass 30, count 2 2006.253.07:39:01.01#ibcon#about to write, iclass 30, count 2 2006.253.07:39:01.01#ibcon#wrote, iclass 30, count 2 2006.253.07:39:01.01#ibcon#about to read 3, iclass 30, count 2 2006.253.07:39:01.04#ibcon#read 3, iclass 30, count 2 2006.253.07:39:01.04#ibcon#about to read 4, iclass 30, count 2 2006.253.07:39:01.04#ibcon#read 4, iclass 30, count 2 2006.253.07:39:01.04#ibcon#about to read 5, iclass 30, count 2 2006.253.07:39:01.04#ibcon#read 5, iclass 30, count 2 2006.253.07:39:01.04#ibcon#about to read 6, iclass 30, count 2 2006.253.07:39:01.04#ibcon#read 6, iclass 30, count 2 2006.253.07:39:01.04#ibcon#end of sib2, iclass 30, count 2 2006.253.07:39:01.04#ibcon#*after write, iclass 30, count 2 2006.253.07:39:01.04#ibcon#*before return 0, iclass 30, count 2 2006.253.07:39:01.04#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.253.07:39:01.04#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.253.07:39:01.04#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.253.07:39:01.04#ibcon#ireg 7 cls_cnt 0 2006.253.07:39:01.04#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.253.07:39:01.16#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.253.07:39:01.16#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.253.07:39:01.16#ibcon#enter wrdev, iclass 30, count 0 2006.253.07:39:01.16#ibcon#first serial, iclass 30, count 0 2006.253.07:39:01.16#ibcon#enter sib2, iclass 30, count 0 2006.253.07:39:01.16#ibcon#flushed, iclass 30, count 0 2006.253.07:39:01.16#ibcon#about to write, iclass 30, count 0 2006.253.07:39:01.16#ibcon#wrote, iclass 30, count 0 2006.253.07:39:01.16#ibcon#about to read 3, iclass 30, count 0 2006.253.07:39:01.18#ibcon#read 3, iclass 30, count 0 2006.253.07:39:01.18#ibcon#about to read 4, iclass 30, count 0 2006.253.07:39:01.18#ibcon#read 4, iclass 30, count 0 2006.253.07:39:01.18#ibcon#about to read 5, iclass 30, count 0 2006.253.07:39:01.18#ibcon#read 5, iclass 30, count 0 2006.253.07:39:01.18#ibcon#about to read 6, iclass 30, count 0 2006.253.07:39:01.18#ibcon#read 6, iclass 30, count 0 2006.253.07:39:01.18#ibcon#end of sib2, iclass 30, count 0 2006.253.07:39:01.18#ibcon#*mode == 0, iclass 30, count 0 2006.253.07:39:01.18#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.253.07:39:01.18#ibcon#[27=USB\r\n] 2006.253.07:39:01.18#ibcon#*before write, iclass 30, count 0 2006.253.07:39:01.18#ibcon#enter sib2, iclass 30, count 0 2006.253.07:39:01.18#ibcon#flushed, iclass 30, count 0 2006.253.07:39:01.18#ibcon#about to write, iclass 30, count 0 2006.253.07:39:01.18#ibcon#wrote, iclass 30, count 0 2006.253.07:39:01.18#ibcon#about to read 3, iclass 30, count 0 2006.253.07:39:01.21#ibcon#read 3, iclass 30, count 0 2006.253.07:39:01.21#ibcon#about to read 4, iclass 30, count 0 2006.253.07:39:01.21#ibcon#read 4, iclass 30, count 0 2006.253.07:39:01.21#ibcon#about to read 5, iclass 30, count 0 2006.253.07:39:01.21#ibcon#read 5, iclass 30, count 0 2006.253.07:39:01.21#ibcon#about to read 6, iclass 30, count 0 2006.253.07:39:01.21#ibcon#read 6, iclass 30, count 0 2006.253.07:39:01.21#ibcon#end of sib2, iclass 30, count 0 2006.253.07:39:01.21#ibcon#*after write, iclass 30, count 0 2006.253.07:39:01.21#ibcon#*before return 0, iclass 30, count 0 2006.253.07:39:01.21#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.253.07:39:01.21#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.253.07:39:01.21#ibcon#about to clear, iclass 30 cls_cnt 0 2006.253.07:39:01.21#ibcon#cleared, iclass 30 cls_cnt 0 2006.253.07:39:01.21$vc4f8/vblo=3,656.99 2006.253.07:39:01.21#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.253.07:39:01.21#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.253.07:39:01.21#ibcon#ireg 17 cls_cnt 0 2006.253.07:39:01.21#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.253.07:39:01.21#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.253.07:39:01.21#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.253.07:39:01.21#ibcon#enter wrdev, iclass 32, count 0 2006.253.07:39:01.21#ibcon#first serial, iclass 32, count 0 2006.253.07:39:01.21#ibcon#enter sib2, iclass 32, count 0 2006.253.07:39:01.21#ibcon#flushed, iclass 32, count 0 2006.253.07:39:01.21#ibcon#about to write, iclass 32, count 0 2006.253.07:39:01.21#ibcon#wrote, iclass 32, count 0 2006.253.07:39:01.21#ibcon#about to read 3, iclass 32, count 0 2006.253.07:39:01.23#ibcon#read 3, iclass 32, count 0 2006.253.07:39:01.23#ibcon#about to read 4, iclass 32, count 0 2006.253.07:39:01.23#ibcon#read 4, iclass 32, count 0 2006.253.07:39:01.23#ibcon#about to read 5, iclass 32, count 0 2006.253.07:39:01.23#ibcon#read 5, iclass 32, count 0 2006.253.07:39:01.23#ibcon#about to read 6, iclass 32, count 0 2006.253.07:39:01.23#ibcon#read 6, iclass 32, count 0 2006.253.07:39:01.23#ibcon#end of sib2, iclass 32, count 0 2006.253.07:39:01.23#ibcon#*mode == 0, iclass 32, count 0 2006.253.07:39:01.23#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.253.07:39:01.23#ibcon#[28=FRQ=03,656.99\r\n] 2006.253.07:39:01.23#ibcon#*before write, iclass 32, count 0 2006.253.07:39:01.23#ibcon#enter sib2, iclass 32, count 0 2006.253.07:39:01.23#ibcon#flushed, iclass 32, count 0 2006.253.07:39:01.23#ibcon#about to write, iclass 32, count 0 2006.253.07:39:01.23#ibcon#wrote, iclass 32, count 0 2006.253.07:39:01.23#ibcon#about to read 3, iclass 32, count 0 2006.253.07:39:01.27#ibcon#read 3, iclass 32, count 0 2006.253.07:39:01.27#ibcon#about to read 4, iclass 32, count 0 2006.253.07:39:01.27#ibcon#read 4, iclass 32, count 0 2006.253.07:39:01.27#ibcon#about to read 5, iclass 32, count 0 2006.253.07:39:01.27#ibcon#read 5, iclass 32, count 0 2006.253.07:39:01.27#ibcon#about to read 6, iclass 32, count 0 2006.253.07:39:01.27#ibcon#read 6, iclass 32, count 0 2006.253.07:39:01.27#ibcon#end of sib2, iclass 32, count 0 2006.253.07:39:01.27#ibcon#*after write, iclass 32, count 0 2006.253.07:39:01.27#ibcon#*before return 0, iclass 32, count 0 2006.253.07:39:01.27#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.253.07:39:01.27#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.253.07:39:01.27#ibcon#about to clear, iclass 32 cls_cnt 0 2006.253.07:39:01.27#ibcon#cleared, iclass 32 cls_cnt 0 2006.253.07:39:01.27$vc4f8/vb=3,4 2006.253.07:39:01.27#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.253.07:39:01.27#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.253.07:39:01.27#ibcon#ireg 11 cls_cnt 2 2006.253.07:39:01.27#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.253.07:39:01.33#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.253.07:39:01.33#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.253.07:39:01.33#ibcon#enter wrdev, iclass 34, count 2 2006.253.07:39:01.33#ibcon#first serial, iclass 34, count 2 2006.253.07:39:01.33#ibcon#enter sib2, iclass 34, count 2 2006.253.07:39:01.33#ibcon#flushed, iclass 34, count 2 2006.253.07:39:01.33#ibcon#about to write, iclass 34, count 2 2006.253.07:39:01.33#ibcon#wrote, iclass 34, count 2 2006.253.07:39:01.33#ibcon#about to read 3, iclass 34, count 2 2006.253.07:39:01.35#ibcon#read 3, iclass 34, count 2 2006.253.07:39:01.35#ibcon#about to read 4, iclass 34, count 2 2006.253.07:39:01.35#ibcon#read 4, iclass 34, count 2 2006.253.07:39:01.35#ibcon#about to read 5, iclass 34, count 2 2006.253.07:39:01.35#ibcon#read 5, iclass 34, count 2 2006.253.07:39:01.35#ibcon#about to read 6, iclass 34, count 2 2006.253.07:39:01.35#ibcon#read 6, iclass 34, count 2 2006.253.07:39:01.35#ibcon#end of sib2, iclass 34, count 2 2006.253.07:39:01.35#ibcon#*mode == 0, iclass 34, count 2 2006.253.07:39:01.35#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.253.07:39:01.35#ibcon#[27=AT03-04\r\n] 2006.253.07:39:01.35#ibcon#*before write, iclass 34, count 2 2006.253.07:39:01.35#ibcon#enter sib2, iclass 34, count 2 2006.253.07:39:01.35#ibcon#flushed, iclass 34, count 2 2006.253.07:39:01.35#ibcon#about to write, iclass 34, count 2 2006.253.07:39:01.35#ibcon#wrote, iclass 34, count 2 2006.253.07:39:01.35#ibcon#about to read 3, iclass 34, count 2 2006.253.07:39:01.38#ibcon#read 3, iclass 34, count 2 2006.253.07:39:01.38#ibcon#about to read 4, iclass 34, count 2 2006.253.07:39:01.38#ibcon#read 4, iclass 34, count 2 2006.253.07:39:01.38#ibcon#about to read 5, iclass 34, count 2 2006.253.07:39:01.38#ibcon#read 5, iclass 34, count 2 2006.253.07:39:01.38#ibcon#about to read 6, iclass 34, count 2 2006.253.07:39:01.38#ibcon#read 6, iclass 34, count 2 2006.253.07:39:01.38#ibcon#end of sib2, iclass 34, count 2 2006.253.07:39:01.38#ibcon#*after write, iclass 34, count 2 2006.253.07:39:01.38#ibcon#*before return 0, iclass 34, count 2 2006.253.07:39:01.38#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.253.07:39:01.38#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.253.07:39:01.38#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.253.07:39:01.38#ibcon#ireg 7 cls_cnt 0 2006.253.07:39:01.38#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.253.07:39:01.50#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.253.07:39:01.50#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.253.07:39:01.50#ibcon#enter wrdev, iclass 34, count 0 2006.253.07:39:01.50#ibcon#first serial, iclass 34, count 0 2006.253.07:39:01.50#ibcon#enter sib2, iclass 34, count 0 2006.253.07:39:01.50#ibcon#flushed, iclass 34, count 0 2006.253.07:39:01.50#ibcon#about to write, iclass 34, count 0 2006.253.07:39:01.50#ibcon#wrote, iclass 34, count 0 2006.253.07:39:01.50#ibcon#about to read 3, iclass 34, count 0 2006.253.07:39:01.52#ibcon#read 3, iclass 34, count 0 2006.253.07:39:01.52#ibcon#about to read 4, iclass 34, count 0 2006.253.07:39:01.52#ibcon#read 4, iclass 34, count 0 2006.253.07:39:01.52#ibcon#about to read 5, iclass 34, count 0 2006.253.07:39:01.52#ibcon#read 5, iclass 34, count 0 2006.253.07:39:01.52#ibcon#about to read 6, iclass 34, count 0 2006.253.07:39:01.52#ibcon#read 6, iclass 34, count 0 2006.253.07:39:01.52#ibcon#end of sib2, iclass 34, count 0 2006.253.07:39:01.52#ibcon#*mode == 0, iclass 34, count 0 2006.253.07:39:01.52#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.253.07:39:01.52#ibcon#[27=USB\r\n] 2006.253.07:39:01.52#ibcon#*before write, iclass 34, count 0 2006.253.07:39:01.52#ibcon#enter sib2, iclass 34, count 0 2006.253.07:39:01.52#ibcon#flushed, iclass 34, count 0 2006.253.07:39:01.52#ibcon#about to write, iclass 34, count 0 2006.253.07:39:01.52#ibcon#wrote, iclass 34, count 0 2006.253.07:39:01.52#ibcon#about to read 3, iclass 34, count 0 2006.253.07:39:01.55#ibcon#read 3, iclass 34, count 0 2006.253.07:39:01.55#ibcon#about to read 4, iclass 34, count 0 2006.253.07:39:01.55#ibcon#read 4, iclass 34, count 0 2006.253.07:39:01.55#ibcon#about to read 5, iclass 34, count 0 2006.253.07:39:01.55#ibcon#read 5, iclass 34, count 0 2006.253.07:39:01.55#ibcon#about to read 6, iclass 34, count 0 2006.253.07:39:01.55#ibcon#read 6, iclass 34, count 0 2006.253.07:39:01.55#ibcon#end of sib2, iclass 34, count 0 2006.253.07:39:01.55#ibcon#*after write, iclass 34, count 0 2006.253.07:39:01.55#ibcon#*before return 0, iclass 34, count 0 2006.253.07:39:01.55#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.253.07:39:01.55#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.253.07:39:01.55#ibcon#about to clear, iclass 34 cls_cnt 0 2006.253.07:39:01.55#ibcon#cleared, iclass 34 cls_cnt 0 2006.253.07:39:01.55$vc4f8/vblo=4,712.99 2006.253.07:39:01.55#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.253.07:39:01.55#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.253.07:39:01.55#ibcon#ireg 17 cls_cnt 0 2006.253.07:39:01.55#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.253.07:39:01.55#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.253.07:39:01.55#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.253.07:39:01.55#ibcon#enter wrdev, iclass 36, count 0 2006.253.07:39:01.55#ibcon#first serial, iclass 36, count 0 2006.253.07:39:01.55#ibcon#enter sib2, iclass 36, count 0 2006.253.07:39:01.55#ibcon#flushed, iclass 36, count 0 2006.253.07:39:01.55#ibcon#about to write, iclass 36, count 0 2006.253.07:39:01.55#ibcon#wrote, iclass 36, count 0 2006.253.07:39:01.55#ibcon#about to read 3, iclass 36, count 0 2006.253.07:39:01.57#ibcon#read 3, iclass 36, count 0 2006.253.07:39:01.57#ibcon#about to read 4, iclass 36, count 0 2006.253.07:39:01.57#ibcon#read 4, iclass 36, count 0 2006.253.07:39:01.57#ibcon#about to read 5, iclass 36, count 0 2006.253.07:39:01.57#ibcon#read 5, iclass 36, count 0 2006.253.07:39:01.57#ibcon#about to read 6, iclass 36, count 0 2006.253.07:39:01.57#ibcon#read 6, iclass 36, count 0 2006.253.07:39:01.57#ibcon#end of sib2, iclass 36, count 0 2006.253.07:39:01.57#ibcon#*mode == 0, iclass 36, count 0 2006.253.07:39:01.57#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.253.07:39:01.57#ibcon#[28=FRQ=04,712.99\r\n] 2006.253.07:39:01.57#ibcon#*before write, iclass 36, count 0 2006.253.07:39:01.57#ibcon#enter sib2, iclass 36, count 0 2006.253.07:39:01.57#ibcon#flushed, iclass 36, count 0 2006.253.07:39:01.57#ibcon#about to write, iclass 36, count 0 2006.253.07:39:01.57#ibcon#wrote, iclass 36, count 0 2006.253.07:39:01.57#ibcon#about to read 3, iclass 36, count 0 2006.253.07:39:01.61#ibcon#read 3, iclass 36, count 0 2006.253.07:39:01.61#ibcon#about to read 4, iclass 36, count 0 2006.253.07:39:01.61#ibcon#read 4, iclass 36, count 0 2006.253.07:39:01.61#ibcon#about to read 5, iclass 36, count 0 2006.253.07:39:01.61#ibcon#read 5, iclass 36, count 0 2006.253.07:39:01.61#ibcon#about to read 6, iclass 36, count 0 2006.253.07:39:01.61#ibcon#read 6, iclass 36, count 0 2006.253.07:39:01.61#ibcon#end of sib2, iclass 36, count 0 2006.253.07:39:01.61#ibcon#*after write, iclass 36, count 0 2006.253.07:39:01.61#ibcon#*before return 0, iclass 36, count 0 2006.253.07:39:01.61#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.253.07:39:01.61#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.253.07:39:01.61#ibcon#about to clear, iclass 36 cls_cnt 0 2006.253.07:39:01.61#ibcon#cleared, iclass 36 cls_cnt 0 2006.253.07:39:01.61$vc4f8/vb=4,4 2006.253.07:39:01.61#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.253.07:39:01.61#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.253.07:39:01.61#ibcon#ireg 11 cls_cnt 2 2006.253.07:39:01.61#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.253.07:39:01.67#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.253.07:39:01.67#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.253.07:39:01.67#ibcon#enter wrdev, iclass 38, count 2 2006.253.07:39:01.67#ibcon#first serial, iclass 38, count 2 2006.253.07:39:01.67#ibcon#enter sib2, iclass 38, count 2 2006.253.07:39:01.67#ibcon#flushed, iclass 38, count 2 2006.253.07:39:01.67#ibcon#about to write, iclass 38, count 2 2006.253.07:39:01.67#ibcon#wrote, iclass 38, count 2 2006.253.07:39:01.67#ibcon#about to read 3, iclass 38, count 2 2006.253.07:39:01.69#ibcon#read 3, iclass 38, count 2 2006.253.07:39:01.69#ibcon#about to read 4, iclass 38, count 2 2006.253.07:39:01.69#ibcon#read 4, iclass 38, count 2 2006.253.07:39:01.69#ibcon#about to read 5, iclass 38, count 2 2006.253.07:39:01.69#ibcon#read 5, iclass 38, count 2 2006.253.07:39:01.69#ibcon#about to read 6, iclass 38, count 2 2006.253.07:39:01.69#ibcon#read 6, iclass 38, count 2 2006.253.07:39:01.69#ibcon#end of sib2, iclass 38, count 2 2006.253.07:39:01.69#ibcon#*mode == 0, iclass 38, count 2 2006.253.07:39:01.69#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.253.07:39:01.69#ibcon#[27=AT04-04\r\n] 2006.253.07:39:01.69#ibcon#*before write, iclass 38, count 2 2006.253.07:39:01.69#ibcon#enter sib2, iclass 38, count 2 2006.253.07:39:01.69#ibcon#flushed, iclass 38, count 2 2006.253.07:39:01.69#ibcon#about to write, iclass 38, count 2 2006.253.07:39:01.69#ibcon#wrote, iclass 38, count 2 2006.253.07:39:01.69#ibcon#about to read 3, iclass 38, count 2 2006.253.07:39:01.72#ibcon#read 3, iclass 38, count 2 2006.253.07:39:01.72#ibcon#about to read 4, iclass 38, count 2 2006.253.07:39:01.72#ibcon#read 4, iclass 38, count 2 2006.253.07:39:01.72#ibcon#about to read 5, iclass 38, count 2 2006.253.07:39:01.72#ibcon#read 5, iclass 38, count 2 2006.253.07:39:01.72#ibcon#about to read 6, iclass 38, count 2 2006.253.07:39:01.72#ibcon#read 6, iclass 38, count 2 2006.253.07:39:01.72#ibcon#end of sib2, iclass 38, count 2 2006.253.07:39:01.72#ibcon#*after write, iclass 38, count 2 2006.253.07:39:01.72#ibcon#*before return 0, iclass 38, count 2 2006.253.07:39:01.72#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.253.07:39:01.72#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.253.07:39:01.72#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.253.07:39:01.72#ibcon#ireg 7 cls_cnt 0 2006.253.07:39:01.72#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.253.07:39:01.84#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.253.07:39:01.84#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.253.07:39:01.84#ibcon#enter wrdev, iclass 38, count 0 2006.253.07:39:01.84#ibcon#first serial, iclass 38, count 0 2006.253.07:39:01.84#ibcon#enter sib2, iclass 38, count 0 2006.253.07:39:01.84#ibcon#flushed, iclass 38, count 0 2006.253.07:39:01.84#ibcon#about to write, iclass 38, count 0 2006.253.07:39:01.84#ibcon#wrote, iclass 38, count 0 2006.253.07:39:01.84#ibcon#about to read 3, iclass 38, count 0 2006.253.07:39:01.86#ibcon#read 3, iclass 38, count 0 2006.253.07:39:01.86#ibcon#about to read 4, iclass 38, count 0 2006.253.07:39:01.86#ibcon#read 4, iclass 38, count 0 2006.253.07:39:01.86#ibcon#about to read 5, iclass 38, count 0 2006.253.07:39:01.86#ibcon#read 5, iclass 38, count 0 2006.253.07:39:01.86#ibcon#about to read 6, iclass 38, count 0 2006.253.07:39:01.86#ibcon#read 6, iclass 38, count 0 2006.253.07:39:01.86#ibcon#end of sib2, iclass 38, count 0 2006.253.07:39:01.86#ibcon#*mode == 0, iclass 38, count 0 2006.253.07:39:01.86#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.253.07:39:01.86#ibcon#[27=USB\r\n] 2006.253.07:39:01.86#ibcon#*before write, iclass 38, count 0 2006.253.07:39:01.86#ibcon#enter sib2, iclass 38, count 0 2006.253.07:39:01.86#ibcon#flushed, iclass 38, count 0 2006.253.07:39:01.86#ibcon#about to write, iclass 38, count 0 2006.253.07:39:01.86#ibcon#wrote, iclass 38, count 0 2006.253.07:39:01.86#ibcon#about to read 3, iclass 38, count 0 2006.253.07:39:01.89#ibcon#read 3, iclass 38, count 0 2006.253.07:39:01.89#ibcon#about to read 4, iclass 38, count 0 2006.253.07:39:01.89#ibcon#read 4, iclass 38, count 0 2006.253.07:39:01.89#ibcon#about to read 5, iclass 38, count 0 2006.253.07:39:01.89#ibcon#read 5, iclass 38, count 0 2006.253.07:39:01.89#ibcon#about to read 6, iclass 38, count 0 2006.253.07:39:01.89#ibcon#read 6, iclass 38, count 0 2006.253.07:39:01.89#ibcon#end of sib2, iclass 38, count 0 2006.253.07:39:01.89#ibcon#*after write, iclass 38, count 0 2006.253.07:39:01.89#ibcon#*before return 0, iclass 38, count 0 2006.253.07:39:01.89#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.253.07:39:01.89#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.253.07:39:01.89#ibcon#about to clear, iclass 38 cls_cnt 0 2006.253.07:39:01.89#ibcon#cleared, iclass 38 cls_cnt 0 2006.253.07:39:01.89$vc4f8/vblo=5,744.99 2006.253.07:39:01.89#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.253.07:39:01.89#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.253.07:39:01.89#ibcon#ireg 17 cls_cnt 0 2006.253.07:39:01.89#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.253.07:39:01.89#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.253.07:39:01.89#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.253.07:39:01.89#ibcon#enter wrdev, iclass 40, count 0 2006.253.07:39:01.89#ibcon#first serial, iclass 40, count 0 2006.253.07:39:01.89#ibcon#enter sib2, iclass 40, count 0 2006.253.07:39:01.89#ibcon#flushed, iclass 40, count 0 2006.253.07:39:01.89#ibcon#about to write, iclass 40, count 0 2006.253.07:39:01.89#ibcon#wrote, iclass 40, count 0 2006.253.07:39:01.89#ibcon#about to read 3, iclass 40, count 0 2006.253.07:39:01.91#ibcon#read 3, iclass 40, count 0 2006.253.07:39:01.91#ibcon#about to read 4, iclass 40, count 0 2006.253.07:39:01.91#ibcon#read 4, iclass 40, count 0 2006.253.07:39:01.91#ibcon#about to read 5, iclass 40, count 0 2006.253.07:39:01.91#ibcon#read 5, iclass 40, count 0 2006.253.07:39:01.91#ibcon#about to read 6, iclass 40, count 0 2006.253.07:39:01.91#ibcon#read 6, iclass 40, count 0 2006.253.07:39:01.91#ibcon#end of sib2, iclass 40, count 0 2006.253.07:39:01.91#ibcon#*mode == 0, iclass 40, count 0 2006.253.07:39:01.91#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.253.07:39:01.91#ibcon#[28=FRQ=05,744.99\r\n] 2006.253.07:39:01.91#ibcon#*before write, iclass 40, count 0 2006.253.07:39:01.91#ibcon#enter sib2, iclass 40, count 0 2006.253.07:39:01.91#ibcon#flushed, iclass 40, count 0 2006.253.07:39:01.91#ibcon#about to write, iclass 40, count 0 2006.253.07:39:01.91#ibcon#wrote, iclass 40, count 0 2006.253.07:39:01.91#ibcon#about to read 3, iclass 40, count 0 2006.253.07:39:01.96#ibcon#read 3, iclass 40, count 0 2006.253.07:39:01.96#ibcon#about to read 4, iclass 40, count 0 2006.253.07:39:01.96#ibcon#read 4, iclass 40, count 0 2006.253.07:39:01.96#ibcon#about to read 5, iclass 40, count 0 2006.253.07:39:01.96#ibcon#read 5, iclass 40, count 0 2006.253.07:39:01.96#ibcon#about to read 6, iclass 40, count 0 2006.253.07:39:01.96#ibcon#read 6, iclass 40, count 0 2006.253.07:39:01.96#ibcon#end of sib2, iclass 40, count 0 2006.253.07:39:01.96#ibcon#*after write, iclass 40, count 0 2006.253.07:39:01.96#ibcon#*before return 0, iclass 40, count 0 2006.253.07:39:01.96#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.253.07:39:01.96#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.253.07:39:01.96#ibcon#about to clear, iclass 40 cls_cnt 0 2006.253.07:39:01.96#ibcon#cleared, iclass 40 cls_cnt 0 2006.253.07:39:01.96$vc4f8/vb=5,4 2006.253.07:39:01.96#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.253.07:39:01.96#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.253.07:39:01.96#ibcon#ireg 11 cls_cnt 2 2006.253.07:39:01.96#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.253.07:39:02.01#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.253.07:39:02.01#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.253.07:39:02.01#ibcon#enter wrdev, iclass 4, count 2 2006.253.07:39:02.01#ibcon#first serial, iclass 4, count 2 2006.253.07:39:02.01#ibcon#enter sib2, iclass 4, count 2 2006.253.07:39:02.01#ibcon#flushed, iclass 4, count 2 2006.253.07:39:02.01#ibcon#about to write, iclass 4, count 2 2006.253.07:39:02.01#ibcon#wrote, iclass 4, count 2 2006.253.07:39:02.01#ibcon#about to read 3, iclass 4, count 2 2006.253.07:39:02.03#ibcon#read 3, iclass 4, count 2 2006.253.07:39:02.03#ibcon#about to read 4, iclass 4, count 2 2006.253.07:39:02.03#ibcon#read 4, iclass 4, count 2 2006.253.07:39:02.03#ibcon#about to read 5, iclass 4, count 2 2006.253.07:39:02.03#ibcon#read 5, iclass 4, count 2 2006.253.07:39:02.03#ibcon#about to read 6, iclass 4, count 2 2006.253.07:39:02.03#ibcon#read 6, iclass 4, count 2 2006.253.07:39:02.03#ibcon#end of sib2, iclass 4, count 2 2006.253.07:39:02.03#ibcon#*mode == 0, iclass 4, count 2 2006.253.07:39:02.03#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.253.07:39:02.03#ibcon#[27=AT05-04\r\n] 2006.253.07:39:02.03#ibcon#*before write, iclass 4, count 2 2006.253.07:39:02.03#ibcon#enter sib2, iclass 4, count 2 2006.253.07:39:02.03#ibcon#flushed, iclass 4, count 2 2006.253.07:39:02.03#ibcon#about to write, iclass 4, count 2 2006.253.07:39:02.03#ibcon#wrote, iclass 4, count 2 2006.253.07:39:02.03#ibcon#about to read 3, iclass 4, count 2 2006.253.07:39:02.06#ibcon#read 3, iclass 4, count 2 2006.253.07:39:02.06#ibcon#about to read 4, iclass 4, count 2 2006.253.07:39:02.06#ibcon#read 4, iclass 4, count 2 2006.253.07:39:02.06#ibcon#about to read 5, iclass 4, count 2 2006.253.07:39:02.06#ibcon#read 5, iclass 4, count 2 2006.253.07:39:02.06#ibcon#about to read 6, iclass 4, count 2 2006.253.07:39:02.06#ibcon#read 6, iclass 4, count 2 2006.253.07:39:02.06#ibcon#end of sib2, iclass 4, count 2 2006.253.07:39:02.06#ibcon#*after write, iclass 4, count 2 2006.253.07:39:02.06#ibcon#*before return 0, iclass 4, count 2 2006.253.07:39:02.06#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.253.07:39:02.06#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.253.07:39:02.06#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.253.07:39:02.06#ibcon#ireg 7 cls_cnt 0 2006.253.07:39:02.06#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.253.07:39:02.18#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.253.07:39:02.18#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.253.07:39:02.18#ibcon#enter wrdev, iclass 4, count 0 2006.253.07:39:02.18#ibcon#first serial, iclass 4, count 0 2006.253.07:39:02.18#ibcon#enter sib2, iclass 4, count 0 2006.253.07:39:02.18#ibcon#flushed, iclass 4, count 0 2006.253.07:39:02.18#ibcon#about to write, iclass 4, count 0 2006.253.07:39:02.18#ibcon#wrote, iclass 4, count 0 2006.253.07:39:02.18#ibcon#about to read 3, iclass 4, count 0 2006.253.07:39:02.20#ibcon#read 3, iclass 4, count 0 2006.253.07:39:02.20#ibcon#about to read 4, iclass 4, count 0 2006.253.07:39:02.20#ibcon#read 4, iclass 4, count 0 2006.253.07:39:02.20#ibcon#about to read 5, iclass 4, count 0 2006.253.07:39:02.20#ibcon#read 5, iclass 4, count 0 2006.253.07:39:02.20#ibcon#about to read 6, iclass 4, count 0 2006.253.07:39:02.20#ibcon#read 6, iclass 4, count 0 2006.253.07:39:02.20#ibcon#end of sib2, iclass 4, count 0 2006.253.07:39:02.20#ibcon#*mode == 0, iclass 4, count 0 2006.253.07:39:02.20#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.253.07:39:02.20#ibcon#[27=USB\r\n] 2006.253.07:39:02.20#ibcon#*before write, iclass 4, count 0 2006.253.07:39:02.20#ibcon#enter sib2, iclass 4, count 0 2006.253.07:39:02.20#ibcon#flushed, iclass 4, count 0 2006.253.07:39:02.20#ibcon#about to write, iclass 4, count 0 2006.253.07:39:02.20#ibcon#wrote, iclass 4, count 0 2006.253.07:39:02.20#ibcon#about to read 3, iclass 4, count 0 2006.253.07:39:02.23#ibcon#read 3, iclass 4, count 0 2006.253.07:39:02.23#ibcon#about to read 4, iclass 4, count 0 2006.253.07:39:02.23#ibcon#read 4, iclass 4, count 0 2006.253.07:39:02.23#ibcon#about to read 5, iclass 4, count 0 2006.253.07:39:02.23#ibcon#read 5, iclass 4, count 0 2006.253.07:39:02.23#ibcon#about to read 6, iclass 4, count 0 2006.253.07:39:02.23#ibcon#read 6, iclass 4, count 0 2006.253.07:39:02.23#ibcon#end of sib2, iclass 4, count 0 2006.253.07:39:02.23#ibcon#*after write, iclass 4, count 0 2006.253.07:39:02.23#ibcon#*before return 0, iclass 4, count 0 2006.253.07:39:02.23#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.253.07:39:02.23#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.253.07:39:02.23#ibcon#about to clear, iclass 4 cls_cnt 0 2006.253.07:39:02.23#ibcon#cleared, iclass 4 cls_cnt 0 2006.253.07:39:02.23$vc4f8/vblo=6,752.99 2006.253.07:39:02.23#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.253.07:39:02.23#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.253.07:39:02.23#ibcon#ireg 17 cls_cnt 0 2006.253.07:39:02.23#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.253.07:39:02.23#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.253.07:39:02.23#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.253.07:39:02.23#ibcon#enter wrdev, iclass 6, count 0 2006.253.07:39:02.23#ibcon#first serial, iclass 6, count 0 2006.253.07:39:02.23#ibcon#enter sib2, iclass 6, count 0 2006.253.07:39:02.23#ibcon#flushed, iclass 6, count 0 2006.253.07:39:02.23#ibcon#about to write, iclass 6, count 0 2006.253.07:39:02.23#ibcon#wrote, iclass 6, count 0 2006.253.07:39:02.23#ibcon#about to read 3, iclass 6, count 0 2006.253.07:39:02.25#ibcon#read 3, iclass 6, count 0 2006.253.07:39:02.25#ibcon#about to read 4, iclass 6, count 0 2006.253.07:39:02.25#ibcon#read 4, iclass 6, count 0 2006.253.07:39:02.25#ibcon#about to read 5, iclass 6, count 0 2006.253.07:39:02.25#ibcon#read 5, iclass 6, count 0 2006.253.07:39:02.25#ibcon#about to read 6, iclass 6, count 0 2006.253.07:39:02.25#ibcon#read 6, iclass 6, count 0 2006.253.07:39:02.25#ibcon#end of sib2, iclass 6, count 0 2006.253.07:39:02.25#ibcon#*mode == 0, iclass 6, count 0 2006.253.07:39:02.25#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.253.07:39:02.25#ibcon#[28=FRQ=06,752.99\r\n] 2006.253.07:39:02.25#ibcon#*before write, iclass 6, count 0 2006.253.07:39:02.25#ibcon#enter sib2, iclass 6, count 0 2006.253.07:39:02.25#ibcon#flushed, iclass 6, count 0 2006.253.07:39:02.25#ibcon#about to write, iclass 6, count 0 2006.253.07:39:02.25#ibcon#wrote, iclass 6, count 0 2006.253.07:39:02.25#ibcon#about to read 3, iclass 6, count 0 2006.253.07:39:02.29#ibcon#read 3, iclass 6, count 0 2006.253.07:39:02.29#ibcon#about to read 4, iclass 6, count 0 2006.253.07:39:02.29#ibcon#read 4, iclass 6, count 0 2006.253.07:39:02.29#ibcon#about to read 5, iclass 6, count 0 2006.253.07:39:02.29#ibcon#read 5, iclass 6, count 0 2006.253.07:39:02.29#ibcon#about to read 6, iclass 6, count 0 2006.253.07:39:02.29#ibcon#read 6, iclass 6, count 0 2006.253.07:39:02.29#ibcon#end of sib2, iclass 6, count 0 2006.253.07:39:02.29#ibcon#*after write, iclass 6, count 0 2006.253.07:39:02.29#ibcon#*before return 0, iclass 6, count 0 2006.253.07:39:02.29#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.253.07:39:02.29#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.253.07:39:02.29#ibcon#about to clear, iclass 6 cls_cnt 0 2006.253.07:39:02.29#ibcon#cleared, iclass 6 cls_cnt 0 2006.253.07:39:02.29$vc4f8/vb=6,4 2006.253.07:39:02.29#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.253.07:39:02.29#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.253.07:39:02.29#ibcon#ireg 11 cls_cnt 2 2006.253.07:39:02.29#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.253.07:39:02.35#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.253.07:39:02.35#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.253.07:39:02.35#ibcon#enter wrdev, iclass 10, count 2 2006.253.07:39:02.35#ibcon#first serial, iclass 10, count 2 2006.253.07:39:02.35#ibcon#enter sib2, iclass 10, count 2 2006.253.07:39:02.35#ibcon#flushed, iclass 10, count 2 2006.253.07:39:02.35#ibcon#about to write, iclass 10, count 2 2006.253.07:39:02.35#ibcon#wrote, iclass 10, count 2 2006.253.07:39:02.35#ibcon#about to read 3, iclass 10, count 2 2006.253.07:39:02.37#ibcon#read 3, iclass 10, count 2 2006.253.07:39:02.37#ibcon#about to read 4, iclass 10, count 2 2006.253.07:39:02.37#ibcon#read 4, iclass 10, count 2 2006.253.07:39:02.37#ibcon#about to read 5, iclass 10, count 2 2006.253.07:39:02.37#ibcon#read 5, iclass 10, count 2 2006.253.07:39:02.37#ibcon#about to read 6, iclass 10, count 2 2006.253.07:39:02.37#ibcon#read 6, iclass 10, count 2 2006.253.07:39:02.37#ibcon#end of sib2, iclass 10, count 2 2006.253.07:39:02.37#ibcon#*mode == 0, iclass 10, count 2 2006.253.07:39:02.37#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.253.07:39:02.37#ibcon#[27=AT06-04\r\n] 2006.253.07:39:02.37#ibcon#*before write, iclass 10, count 2 2006.253.07:39:02.37#ibcon#enter sib2, iclass 10, count 2 2006.253.07:39:02.37#ibcon#flushed, iclass 10, count 2 2006.253.07:39:02.37#ibcon#about to write, iclass 10, count 2 2006.253.07:39:02.37#ibcon#wrote, iclass 10, count 2 2006.253.07:39:02.37#ibcon#about to read 3, iclass 10, count 2 2006.253.07:39:02.40#ibcon#read 3, iclass 10, count 2 2006.253.07:39:02.40#ibcon#about to read 4, iclass 10, count 2 2006.253.07:39:02.40#ibcon#read 4, iclass 10, count 2 2006.253.07:39:02.40#ibcon#about to read 5, iclass 10, count 2 2006.253.07:39:02.40#ibcon#read 5, iclass 10, count 2 2006.253.07:39:02.40#ibcon#about to read 6, iclass 10, count 2 2006.253.07:39:02.40#ibcon#read 6, iclass 10, count 2 2006.253.07:39:02.40#ibcon#end of sib2, iclass 10, count 2 2006.253.07:39:02.40#ibcon#*after write, iclass 10, count 2 2006.253.07:39:02.40#ibcon#*before return 0, iclass 10, count 2 2006.253.07:39:02.40#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.253.07:39:02.40#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.253.07:39:02.40#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.253.07:39:02.40#ibcon#ireg 7 cls_cnt 0 2006.253.07:39:02.40#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.253.07:39:02.52#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.253.07:39:02.52#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.253.07:39:02.52#ibcon#enter wrdev, iclass 10, count 0 2006.253.07:39:02.52#ibcon#first serial, iclass 10, count 0 2006.253.07:39:02.52#ibcon#enter sib2, iclass 10, count 0 2006.253.07:39:02.52#ibcon#flushed, iclass 10, count 0 2006.253.07:39:02.52#ibcon#about to write, iclass 10, count 0 2006.253.07:39:02.52#ibcon#wrote, iclass 10, count 0 2006.253.07:39:02.52#ibcon#about to read 3, iclass 10, count 0 2006.253.07:39:02.54#ibcon#read 3, iclass 10, count 0 2006.253.07:39:02.54#ibcon#about to read 4, iclass 10, count 0 2006.253.07:39:02.54#ibcon#read 4, iclass 10, count 0 2006.253.07:39:02.54#ibcon#about to read 5, iclass 10, count 0 2006.253.07:39:02.54#ibcon#read 5, iclass 10, count 0 2006.253.07:39:02.54#ibcon#about to read 6, iclass 10, count 0 2006.253.07:39:02.54#ibcon#read 6, iclass 10, count 0 2006.253.07:39:02.54#ibcon#end of sib2, iclass 10, count 0 2006.253.07:39:02.54#ibcon#*mode == 0, iclass 10, count 0 2006.253.07:39:02.54#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.253.07:39:02.54#ibcon#[27=USB\r\n] 2006.253.07:39:02.54#ibcon#*before write, iclass 10, count 0 2006.253.07:39:02.54#ibcon#enter sib2, iclass 10, count 0 2006.253.07:39:02.54#ibcon#flushed, iclass 10, count 0 2006.253.07:39:02.54#ibcon#about to write, iclass 10, count 0 2006.253.07:39:02.54#ibcon#wrote, iclass 10, count 0 2006.253.07:39:02.54#ibcon#about to read 3, iclass 10, count 0 2006.253.07:39:02.57#ibcon#read 3, iclass 10, count 0 2006.253.07:39:02.57#ibcon#about to read 4, iclass 10, count 0 2006.253.07:39:02.57#ibcon#read 4, iclass 10, count 0 2006.253.07:39:02.57#ibcon#about to read 5, iclass 10, count 0 2006.253.07:39:02.57#ibcon#read 5, iclass 10, count 0 2006.253.07:39:02.57#ibcon#about to read 6, iclass 10, count 0 2006.253.07:39:02.57#ibcon#read 6, iclass 10, count 0 2006.253.07:39:02.57#ibcon#end of sib2, iclass 10, count 0 2006.253.07:39:02.57#ibcon#*after write, iclass 10, count 0 2006.253.07:39:02.57#ibcon#*before return 0, iclass 10, count 0 2006.253.07:39:02.57#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.253.07:39:02.57#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.253.07:39:02.57#ibcon#about to clear, iclass 10 cls_cnt 0 2006.253.07:39:02.57#ibcon#cleared, iclass 10 cls_cnt 0 2006.253.07:39:02.57$vc4f8/vabw=wide 2006.253.07:39:02.57#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.253.07:39:02.57#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.253.07:39:02.57#ibcon#ireg 8 cls_cnt 0 2006.253.07:39:02.57#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.253.07:39:02.57#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.253.07:39:02.57#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.253.07:39:02.57#ibcon#enter wrdev, iclass 12, count 0 2006.253.07:39:02.57#ibcon#first serial, iclass 12, count 0 2006.253.07:39:02.57#ibcon#enter sib2, iclass 12, count 0 2006.253.07:39:02.57#ibcon#flushed, iclass 12, count 0 2006.253.07:39:02.57#ibcon#about to write, iclass 12, count 0 2006.253.07:39:02.57#ibcon#wrote, iclass 12, count 0 2006.253.07:39:02.57#ibcon#about to read 3, iclass 12, count 0 2006.253.07:39:02.59#ibcon#read 3, iclass 12, count 0 2006.253.07:39:02.59#ibcon#about to read 4, iclass 12, count 0 2006.253.07:39:02.59#ibcon#read 4, iclass 12, count 0 2006.253.07:39:02.59#ibcon#about to read 5, iclass 12, count 0 2006.253.07:39:02.59#ibcon#read 5, iclass 12, count 0 2006.253.07:39:02.59#ibcon#about to read 6, iclass 12, count 0 2006.253.07:39:02.59#ibcon#read 6, iclass 12, count 0 2006.253.07:39:02.59#ibcon#end of sib2, iclass 12, count 0 2006.253.07:39:02.59#ibcon#*mode == 0, iclass 12, count 0 2006.253.07:39:02.59#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.253.07:39:02.59#ibcon#[25=BW32\r\n] 2006.253.07:39:02.59#ibcon#*before write, iclass 12, count 0 2006.253.07:39:02.59#ibcon#enter sib2, iclass 12, count 0 2006.253.07:39:02.59#ibcon#flushed, iclass 12, count 0 2006.253.07:39:02.59#ibcon#about to write, iclass 12, count 0 2006.253.07:39:02.59#ibcon#wrote, iclass 12, count 0 2006.253.07:39:02.59#ibcon#about to read 3, iclass 12, count 0 2006.253.07:39:02.63#ibcon#read 3, iclass 12, count 0 2006.253.07:39:02.63#ibcon#about to read 4, iclass 12, count 0 2006.253.07:39:02.63#ibcon#read 4, iclass 12, count 0 2006.253.07:39:02.63#ibcon#about to read 5, iclass 12, count 0 2006.253.07:39:02.63#ibcon#read 5, iclass 12, count 0 2006.253.07:39:02.63#ibcon#about to read 6, iclass 12, count 0 2006.253.07:39:02.63#ibcon#read 6, iclass 12, count 0 2006.253.07:39:02.63#ibcon#end of sib2, iclass 12, count 0 2006.253.07:39:02.63#ibcon#*after write, iclass 12, count 0 2006.253.07:39:02.63#ibcon#*before return 0, iclass 12, count 0 2006.253.07:39:02.63#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.253.07:39:02.63#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.253.07:39:02.63#ibcon#about to clear, iclass 12 cls_cnt 0 2006.253.07:39:02.63#ibcon#cleared, iclass 12 cls_cnt 0 2006.253.07:39:02.63$vc4f8/vbbw=wide 2006.253.07:39:02.63#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.253.07:39:02.63#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.253.07:39:02.63#ibcon#ireg 8 cls_cnt 0 2006.253.07:39:02.63#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.253.07:39:02.69#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.253.07:39:02.69#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.253.07:39:02.69#ibcon#enter wrdev, iclass 14, count 0 2006.253.07:39:02.69#ibcon#first serial, iclass 14, count 0 2006.253.07:39:02.69#ibcon#enter sib2, iclass 14, count 0 2006.253.07:39:02.69#ibcon#flushed, iclass 14, count 0 2006.253.07:39:02.69#ibcon#about to write, iclass 14, count 0 2006.253.07:39:02.69#ibcon#wrote, iclass 14, count 0 2006.253.07:39:02.69#ibcon#about to read 3, iclass 14, count 0 2006.253.07:39:02.71#ibcon#read 3, iclass 14, count 0 2006.253.07:39:02.71#ibcon#about to read 4, iclass 14, count 0 2006.253.07:39:02.71#ibcon#read 4, iclass 14, count 0 2006.253.07:39:02.71#ibcon#about to read 5, iclass 14, count 0 2006.253.07:39:02.71#ibcon#read 5, iclass 14, count 0 2006.253.07:39:02.71#ibcon#about to read 6, iclass 14, count 0 2006.253.07:39:02.71#ibcon#read 6, iclass 14, count 0 2006.253.07:39:02.71#ibcon#end of sib2, iclass 14, count 0 2006.253.07:39:02.71#ibcon#*mode == 0, iclass 14, count 0 2006.253.07:39:02.71#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.253.07:39:02.71#ibcon#[27=BW32\r\n] 2006.253.07:39:02.71#ibcon#*before write, iclass 14, count 0 2006.253.07:39:02.71#ibcon#enter sib2, iclass 14, count 0 2006.253.07:39:02.71#ibcon#flushed, iclass 14, count 0 2006.253.07:39:02.71#ibcon#about to write, iclass 14, count 0 2006.253.07:39:02.71#ibcon#wrote, iclass 14, count 0 2006.253.07:39:02.71#ibcon#about to read 3, iclass 14, count 0 2006.253.07:39:02.74#ibcon#read 3, iclass 14, count 0 2006.253.07:39:02.74#ibcon#about to read 4, iclass 14, count 0 2006.253.07:39:02.74#ibcon#read 4, iclass 14, count 0 2006.253.07:39:02.74#ibcon#about to read 5, iclass 14, count 0 2006.253.07:39:02.74#ibcon#read 5, iclass 14, count 0 2006.253.07:39:02.74#ibcon#about to read 6, iclass 14, count 0 2006.253.07:39:02.74#ibcon#read 6, iclass 14, count 0 2006.253.07:39:02.74#ibcon#end of sib2, iclass 14, count 0 2006.253.07:39:02.74#ibcon#*after write, iclass 14, count 0 2006.253.07:39:02.74#ibcon#*before return 0, iclass 14, count 0 2006.253.07:39:02.74#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.253.07:39:02.74#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.253.07:39:02.74#ibcon#about to clear, iclass 14 cls_cnt 0 2006.253.07:39:02.74#ibcon#cleared, iclass 14 cls_cnt 0 2006.253.07:39:02.74$4f8m12a/ifd4f 2006.253.07:39:02.74$ifd4f/lo= 2006.253.07:39:02.74$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.253.07:39:02.74$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.253.07:39:02.74$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.253.07:39:02.74$ifd4f/patch= 2006.253.07:39:02.74$ifd4f/patch=lo1,a1,a2,a3,a4 2006.253.07:39:02.74$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.253.07:39:02.74$ifd4f/patch=lo3,a5,a6,a7,a8 2006.253.07:39:02.74$4f8m12a/"form=m,16.000,1:2 2006.253.07:39:02.74$4f8m12a/"tpicd 2006.253.07:39:02.74$4f8m12a/echo=off 2006.253.07:39:02.74$4f8m12a/xlog=off 2006.253.07:39:02.74:!2006.253.07:39:30 2006.253.07:39:16.13#trakl#Source acquired 2006.253.07:39:18.13#flagr#flagr/antenna,acquired 2006.253.07:39:30.00:preob 2006.253.07:39:31.14/onsource/TRACKING 2006.253.07:39:31.14:!2006.253.07:39:40 2006.253.07:39:40.00:data_valid=on 2006.253.07:39:40.00:midob 2006.253.07:39:40.14/onsource/TRACKING 2006.253.07:39:40.14/wx/31.49,1006.3,72 2006.253.07:39:40.21/cable/+6.3689E-03 2006.253.07:39:41.30/va/01,08,usb,yes,31,33 2006.253.07:39:41.30/va/02,07,usb,yes,31,33 2006.253.07:39:41.30/va/03,06,usb,yes,33,33 2006.253.07:39:41.30/va/04,07,usb,yes,32,35 2006.253.07:39:41.30/va/05,07,usb,yes,33,35 2006.253.07:39:41.30/va/06,07,usb,yes,29,29 2006.253.07:39:41.30/va/07,07,usb,yes,29,29 2006.253.07:39:41.30/va/08,07,usb,yes,31,31 2006.253.07:39:41.53/valo/01,532.99,yes,locked 2006.253.07:39:41.53/valo/02,572.99,yes,locked 2006.253.07:39:41.53/valo/03,672.99,yes,locked 2006.253.07:39:41.53/valo/04,832.99,yes,locked 2006.253.07:39:41.53/valo/05,652.99,yes,locked 2006.253.07:39:41.53/valo/06,772.99,yes,locked 2006.253.07:39:41.53/valo/07,832.99,yes,locked 2006.253.07:39:41.53/valo/08,852.99,yes,locked 2006.253.07:39:42.62/vb/01,04,usb,yes,30,29 2006.253.07:39:42.62/vb/02,05,usb,yes,28,29 2006.253.07:39:42.62/vb/03,04,usb,yes,28,32 2006.253.07:39:42.62/vb/04,04,usb,yes,29,29 2006.253.07:39:42.62/vb/05,04,usb,yes,28,32 2006.253.07:39:42.62/vb/06,04,usb,yes,29,31 2006.253.07:39:42.62/vb/07,04,usb,yes,31,31 2006.253.07:39:42.62/vb/08,04,usb,yes,28,32 2006.253.07:39:42.85/vblo/01,632.99,yes,locked 2006.253.07:39:42.85/vblo/02,640.99,yes,locked 2006.253.07:39:42.85/vblo/03,656.99,yes,locked 2006.253.07:39:42.85/vblo/04,712.99,yes,locked 2006.253.07:39:42.85/vblo/05,744.99,yes,locked 2006.253.07:39:42.85/vblo/06,752.99,yes,locked 2006.253.07:39:42.85/vblo/07,734.99,yes,locked 2006.253.07:39:42.85/vblo/08,744.99,yes,locked 2006.253.07:39:43.00/vabw/8 2006.253.07:39:43.15/vbbw/8 2006.253.07:39:43.24/xfe/off,on,14.7 2006.253.07:39:43.61/ifatt/23,28,28,28 2006.253.07:39:44.08/fmout-gps/S +4.76E-07 2006.253.07:39:44.12:!2006.253.07:40:40 2006.253.07:40:40.00:data_valid=off 2006.253.07:40:40.00:postob 2006.253.07:40:40.21/cable/+6.3687E-03 2006.253.07:40:40.21/wx/31.47,1006.3,73 2006.253.07:40:41.08/fmout-gps/S +4.74E-07 2006.253.07:40:41.08:scan_name=253-0741,k06253,60 2006.253.07:40:41.08:source=1417+385,141946.61,382148.5,2000.0,ccw 2006.253.07:40:41.14#flagr#flagr/antenna,new-source 2006.253.07:40:42.14:checkk5 2006.253.07:40:42.51/chk_autoobs//k5ts1/ autoobs is running! 2006.253.07:40:42.89/chk_autoobs//k5ts2/ autoobs is running! 2006.253.07:40:43.27/chk_autoobs//k5ts3/ autoobs is running! 2006.253.07:40:43.64/chk_autoobs//k5ts4/ autoobs is running! 2006.253.07:40:44.01/chk_obsdata//k5ts1/T2530739??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.253.07:40:44.37/chk_obsdata//k5ts2/T2530739??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.253.07:40:44.76/chk_obsdata//k5ts3/T2530739??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.253.07:40:45.13/chk_obsdata//k5ts4/T2530739??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.253.07:40:45.82/k5log//k5ts1_log_newline 2006.253.07:40:46.52/k5log//k5ts2_log_newline 2006.253.07:40:47.21/k5log//k5ts3_log_newline 2006.253.07:40:47.89/k5log//k5ts4_log_newline 2006.253.07:40:47.92/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.253.07:40:47.92:4f8m12a=1 2006.253.07:40:47.92$4f8m12a/echo=on 2006.253.07:40:47.92$4f8m12a/pcalon 2006.253.07:40:47.92$pcalon/"no phase cal control is implemented here 2006.253.07:40:47.92$4f8m12a/"tpicd=stop 2006.253.07:40:47.92$4f8m12a/vc4f8 2006.253.07:40:47.92$vc4f8/valo=1,532.99 2006.253.07:40:47.92#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.253.07:40:47.92#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.253.07:40:47.92#ibcon#ireg 17 cls_cnt 0 2006.253.07:40:47.92#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.253.07:40:47.92#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.253.07:40:47.92#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.253.07:40:47.92#ibcon#enter wrdev, iclass 21, count 0 2006.253.07:40:47.92#ibcon#first serial, iclass 21, count 0 2006.253.07:40:47.92#ibcon#enter sib2, iclass 21, count 0 2006.253.07:40:47.92#ibcon#flushed, iclass 21, count 0 2006.253.07:40:47.92#ibcon#about to write, iclass 21, count 0 2006.253.07:40:47.92#ibcon#wrote, iclass 21, count 0 2006.253.07:40:47.92#ibcon#about to read 3, iclass 21, count 0 2006.253.07:40:47.94#ibcon#read 3, iclass 21, count 0 2006.253.07:40:47.94#ibcon#about to read 4, iclass 21, count 0 2006.253.07:40:47.94#ibcon#read 4, iclass 21, count 0 2006.253.07:40:47.94#ibcon#about to read 5, iclass 21, count 0 2006.253.07:40:47.94#ibcon#read 5, iclass 21, count 0 2006.253.07:40:47.94#ibcon#about to read 6, iclass 21, count 0 2006.253.07:40:47.94#ibcon#read 6, iclass 21, count 0 2006.253.07:40:47.94#ibcon#end of sib2, iclass 21, count 0 2006.253.07:40:47.94#ibcon#*mode == 0, iclass 21, count 0 2006.253.07:40:47.94#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.253.07:40:47.94#ibcon#[26=FRQ=01,532.99\r\n] 2006.253.07:40:47.94#ibcon#*before write, iclass 21, count 0 2006.253.07:40:47.94#ibcon#enter sib2, iclass 21, count 0 2006.253.07:40:47.94#ibcon#flushed, iclass 21, count 0 2006.253.07:40:47.94#ibcon#about to write, iclass 21, count 0 2006.253.07:40:47.94#ibcon#wrote, iclass 21, count 0 2006.253.07:40:47.94#ibcon#about to read 3, iclass 21, count 0 2006.253.07:40:47.99#ibcon#read 3, iclass 21, count 0 2006.253.07:40:47.99#ibcon#about to read 4, iclass 21, count 0 2006.253.07:40:47.99#ibcon#read 4, iclass 21, count 0 2006.253.07:40:47.99#ibcon#about to read 5, iclass 21, count 0 2006.253.07:40:47.99#ibcon#read 5, iclass 21, count 0 2006.253.07:40:47.99#ibcon#about to read 6, iclass 21, count 0 2006.253.07:40:47.99#ibcon#read 6, iclass 21, count 0 2006.253.07:40:47.99#ibcon#end of sib2, iclass 21, count 0 2006.253.07:40:47.99#ibcon#*after write, iclass 21, count 0 2006.253.07:40:47.99#ibcon#*before return 0, iclass 21, count 0 2006.253.07:40:47.99#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.253.07:40:47.99#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.253.07:40:47.99#ibcon#about to clear, iclass 21 cls_cnt 0 2006.253.07:40:47.99#ibcon#cleared, iclass 21 cls_cnt 0 2006.253.07:40:47.99$vc4f8/va=1,8 2006.253.07:40:47.99#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.253.07:40:47.99#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.253.07:40:47.99#ibcon#ireg 11 cls_cnt 2 2006.253.07:40:47.99#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.253.07:40:47.99#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.253.07:40:47.99#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.253.07:40:47.99#ibcon#enter wrdev, iclass 23, count 2 2006.253.07:40:47.99#ibcon#first serial, iclass 23, count 2 2006.253.07:40:47.99#ibcon#enter sib2, iclass 23, count 2 2006.253.07:40:47.99#ibcon#flushed, iclass 23, count 2 2006.253.07:40:47.99#ibcon#about to write, iclass 23, count 2 2006.253.07:40:47.99#ibcon#wrote, iclass 23, count 2 2006.253.07:40:47.99#ibcon#about to read 3, iclass 23, count 2 2006.253.07:40:48.01#ibcon#read 3, iclass 23, count 2 2006.253.07:40:48.01#ibcon#about to read 4, iclass 23, count 2 2006.253.07:40:48.01#ibcon#read 4, iclass 23, count 2 2006.253.07:40:48.01#ibcon#about to read 5, iclass 23, count 2 2006.253.07:40:48.01#ibcon#read 5, iclass 23, count 2 2006.253.07:40:48.01#ibcon#about to read 6, iclass 23, count 2 2006.253.07:40:48.01#ibcon#read 6, iclass 23, count 2 2006.253.07:40:48.01#ibcon#end of sib2, iclass 23, count 2 2006.253.07:40:48.01#ibcon#*mode == 0, iclass 23, count 2 2006.253.07:40:48.01#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.253.07:40:48.01#ibcon#[25=AT01-08\r\n] 2006.253.07:40:48.01#ibcon#*before write, iclass 23, count 2 2006.253.07:40:48.01#ibcon#enter sib2, iclass 23, count 2 2006.253.07:40:48.01#ibcon#flushed, iclass 23, count 2 2006.253.07:40:48.01#ibcon#about to write, iclass 23, count 2 2006.253.07:40:48.01#ibcon#wrote, iclass 23, count 2 2006.253.07:40:48.01#ibcon#about to read 3, iclass 23, count 2 2006.253.07:40:48.04#ibcon#read 3, iclass 23, count 2 2006.253.07:40:48.04#ibcon#about to read 4, iclass 23, count 2 2006.253.07:40:48.04#ibcon#read 4, iclass 23, count 2 2006.253.07:40:48.04#ibcon#about to read 5, iclass 23, count 2 2006.253.07:40:48.04#ibcon#read 5, iclass 23, count 2 2006.253.07:40:48.04#ibcon#about to read 6, iclass 23, count 2 2006.253.07:40:48.04#ibcon#read 6, iclass 23, count 2 2006.253.07:40:48.04#ibcon#end of sib2, iclass 23, count 2 2006.253.07:40:48.04#ibcon#*after write, iclass 23, count 2 2006.253.07:40:48.04#ibcon#*before return 0, iclass 23, count 2 2006.253.07:40:48.04#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.253.07:40:48.04#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.253.07:40:48.04#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.253.07:40:48.04#ibcon#ireg 7 cls_cnt 0 2006.253.07:40:48.04#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.253.07:40:48.16#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.253.07:40:48.16#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.253.07:40:48.16#ibcon#enter wrdev, iclass 23, count 0 2006.253.07:40:48.16#ibcon#first serial, iclass 23, count 0 2006.253.07:40:48.16#ibcon#enter sib2, iclass 23, count 0 2006.253.07:40:48.16#ibcon#flushed, iclass 23, count 0 2006.253.07:40:48.16#ibcon#about to write, iclass 23, count 0 2006.253.07:40:48.16#ibcon#wrote, iclass 23, count 0 2006.253.07:40:48.16#ibcon#about to read 3, iclass 23, count 0 2006.253.07:40:48.18#ibcon#read 3, iclass 23, count 0 2006.253.07:40:48.18#ibcon#about to read 4, iclass 23, count 0 2006.253.07:40:48.18#ibcon#read 4, iclass 23, count 0 2006.253.07:40:48.18#ibcon#about to read 5, iclass 23, count 0 2006.253.07:40:48.18#ibcon#read 5, iclass 23, count 0 2006.253.07:40:48.18#ibcon#about to read 6, iclass 23, count 0 2006.253.07:40:48.18#ibcon#read 6, iclass 23, count 0 2006.253.07:40:48.18#ibcon#end of sib2, iclass 23, count 0 2006.253.07:40:48.18#ibcon#*mode == 0, iclass 23, count 0 2006.253.07:40:48.18#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.253.07:40:48.18#ibcon#[25=USB\r\n] 2006.253.07:40:48.18#ibcon#*before write, iclass 23, count 0 2006.253.07:40:48.18#ibcon#enter sib2, iclass 23, count 0 2006.253.07:40:48.18#ibcon#flushed, iclass 23, count 0 2006.253.07:40:48.18#ibcon#about to write, iclass 23, count 0 2006.253.07:40:48.18#ibcon#wrote, iclass 23, count 0 2006.253.07:40:48.18#ibcon#about to read 3, iclass 23, count 0 2006.253.07:40:48.21#ibcon#read 3, iclass 23, count 0 2006.253.07:40:48.21#ibcon#about to read 4, iclass 23, count 0 2006.253.07:40:48.21#ibcon#read 4, iclass 23, count 0 2006.253.07:40:48.21#ibcon#about to read 5, iclass 23, count 0 2006.253.07:40:48.21#ibcon#read 5, iclass 23, count 0 2006.253.07:40:48.21#ibcon#about to read 6, iclass 23, count 0 2006.253.07:40:48.21#ibcon#read 6, iclass 23, count 0 2006.253.07:40:48.21#ibcon#end of sib2, iclass 23, count 0 2006.253.07:40:48.21#ibcon#*after write, iclass 23, count 0 2006.253.07:40:48.21#ibcon#*before return 0, iclass 23, count 0 2006.253.07:40:48.21#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.253.07:40:48.21#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.253.07:40:48.21#ibcon#about to clear, iclass 23 cls_cnt 0 2006.253.07:40:48.21#ibcon#cleared, iclass 23 cls_cnt 0 2006.253.07:40:48.21$vc4f8/valo=2,572.99 2006.253.07:40:48.21#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.253.07:40:48.21#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.253.07:40:48.21#ibcon#ireg 17 cls_cnt 0 2006.253.07:40:48.21#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.253.07:40:48.21#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.253.07:40:48.21#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.253.07:40:48.21#ibcon#enter wrdev, iclass 25, count 0 2006.253.07:40:48.21#ibcon#first serial, iclass 25, count 0 2006.253.07:40:48.21#ibcon#enter sib2, iclass 25, count 0 2006.253.07:40:48.21#ibcon#flushed, iclass 25, count 0 2006.253.07:40:48.21#ibcon#about to write, iclass 25, count 0 2006.253.07:40:48.21#ibcon#wrote, iclass 25, count 0 2006.253.07:40:48.21#ibcon#about to read 3, iclass 25, count 0 2006.253.07:40:48.23#ibcon#read 3, iclass 25, count 0 2006.253.07:40:48.23#ibcon#about to read 4, iclass 25, count 0 2006.253.07:40:48.23#ibcon#read 4, iclass 25, count 0 2006.253.07:40:48.23#ibcon#about to read 5, iclass 25, count 0 2006.253.07:40:48.23#ibcon#read 5, iclass 25, count 0 2006.253.07:40:48.23#ibcon#about to read 6, iclass 25, count 0 2006.253.07:40:48.23#ibcon#read 6, iclass 25, count 0 2006.253.07:40:48.23#ibcon#end of sib2, iclass 25, count 0 2006.253.07:40:48.23#ibcon#*mode == 0, iclass 25, count 0 2006.253.07:40:48.23#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.253.07:40:48.23#ibcon#[26=FRQ=02,572.99\r\n] 2006.253.07:40:48.23#ibcon#*before write, iclass 25, count 0 2006.253.07:40:48.23#ibcon#enter sib2, iclass 25, count 0 2006.253.07:40:48.23#ibcon#flushed, iclass 25, count 0 2006.253.07:40:48.23#ibcon#about to write, iclass 25, count 0 2006.253.07:40:48.23#ibcon#wrote, iclass 25, count 0 2006.253.07:40:48.23#ibcon#about to read 3, iclass 25, count 0 2006.253.07:40:48.28#ibcon#read 3, iclass 25, count 0 2006.253.07:40:48.28#ibcon#about to read 4, iclass 25, count 0 2006.253.07:40:48.28#ibcon#read 4, iclass 25, count 0 2006.253.07:40:48.28#ibcon#about to read 5, iclass 25, count 0 2006.253.07:40:48.28#ibcon#read 5, iclass 25, count 0 2006.253.07:40:48.28#ibcon#about to read 6, iclass 25, count 0 2006.253.07:40:48.28#ibcon#read 6, iclass 25, count 0 2006.253.07:40:48.28#ibcon#end of sib2, iclass 25, count 0 2006.253.07:40:48.28#ibcon#*after write, iclass 25, count 0 2006.253.07:40:48.28#ibcon#*before return 0, iclass 25, count 0 2006.253.07:40:48.28#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.253.07:40:48.28#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.253.07:40:48.28#ibcon#about to clear, iclass 25 cls_cnt 0 2006.253.07:40:48.28#ibcon#cleared, iclass 25 cls_cnt 0 2006.253.07:40:48.28$vc4f8/va=2,7 2006.253.07:40:48.28#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.253.07:40:48.28#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.253.07:40:48.28#ibcon#ireg 11 cls_cnt 2 2006.253.07:40:48.28#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.253.07:40:48.33#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.253.07:40:48.33#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.253.07:40:48.33#ibcon#enter wrdev, iclass 27, count 2 2006.253.07:40:48.33#ibcon#first serial, iclass 27, count 2 2006.253.07:40:48.33#ibcon#enter sib2, iclass 27, count 2 2006.253.07:40:48.33#ibcon#flushed, iclass 27, count 2 2006.253.07:40:48.33#ibcon#about to write, iclass 27, count 2 2006.253.07:40:48.33#ibcon#wrote, iclass 27, count 2 2006.253.07:40:48.33#ibcon#about to read 3, iclass 27, count 2 2006.253.07:40:48.35#ibcon#read 3, iclass 27, count 2 2006.253.07:40:48.35#ibcon#about to read 4, iclass 27, count 2 2006.253.07:40:48.35#ibcon#read 4, iclass 27, count 2 2006.253.07:40:48.35#ibcon#about to read 5, iclass 27, count 2 2006.253.07:40:48.35#ibcon#read 5, iclass 27, count 2 2006.253.07:40:48.35#ibcon#about to read 6, iclass 27, count 2 2006.253.07:40:48.35#ibcon#read 6, iclass 27, count 2 2006.253.07:40:48.35#ibcon#end of sib2, iclass 27, count 2 2006.253.07:40:48.35#ibcon#*mode == 0, iclass 27, count 2 2006.253.07:40:48.35#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.253.07:40:48.35#ibcon#[25=AT02-07\r\n] 2006.253.07:40:48.35#ibcon#*before write, iclass 27, count 2 2006.253.07:40:48.35#ibcon#enter sib2, iclass 27, count 2 2006.253.07:40:48.35#ibcon#flushed, iclass 27, count 2 2006.253.07:40:48.35#ibcon#about to write, iclass 27, count 2 2006.253.07:40:48.35#ibcon#wrote, iclass 27, count 2 2006.253.07:40:48.35#ibcon#about to read 3, iclass 27, count 2 2006.253.07:40:48.38#ibcon#read 3, iclass 27, count 2 2006.253.07:40:48.38#ibcon#about to read 4, iclass 27, count 2 2006.253.07:40:48.38#ibcon#read 4, iclass 27, count 2 2006.253.07:40:48.38#ibcon#about to read 5, iclass 27, count 2 2006.253.07:40:48.38#ibcon#read 5, iclass 27, count 2 2006.253.07:40:48.38#ibcon#about to read 6, iclass 27, count 2 2006.253.07:40:48.38#ibcon#read 6, iclass 27, count 2 2006.253.07:40:48.38#ibcon#end of sib2, iclass 27, count 2 2006.253.07:40:48.38#ibcon#*after write, iclass 27, count 2 2006.253.07:40:48.38#ibcon#*before return 0, iclass 27, count 2 2006.253.07:40:48.38#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.253.07:40:48.38#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.253.07:40:48.38#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.253.07:40:48.38#ibcon#ireg 7 cls_cnt 0 2006.253.07:40:48.38#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.253.07:40:48.50#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.253.07:40:48.50#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.253.07:40:48.50#ibcon#enter wrdev, iclass 27, count 0 2006.253.07:40:48.50#ibcon#first serial, iclass 27, count 0 2006.253.07:40:48.50#ibcon#enter sib2, iclass 27, count 0 2006.253.07:40:48.50#ibcon#flushed, iclass 27, count 0 2006.253.07:40:48.50#ibcon#about to write, iclass 27, count 0 2006.253.07:40:48.50#ibcon#wrote, iclass 27, count 0 2006.253.07:40:48.50#ibcon#about to read 3, iclass 27, count 0 2006.253.07:40:48.52#ibcon#read 3, iclass 27, count 0 2006.253.07:40:48.52#ibcon#about to read 4, iclass 27, count 0 2006.253.07:40:48.52#ibcon#read 4, iclass 27, count 0 2006.253.07:40:48.52#ibcon#about to read 5, iclass 27, count 0 2006.253.07:40:48.52#ibcon#read 5, iclass 27, count 0 2006.253.07:40:48.52#ibcon#about to read 6, iclass 27, count 0 2006.253.07:40:48.52#ibcon#read 6, iclass 27, count 0 2006.253.07:40:48.52#ibcon#end of sib2, iclass 27, count 0 2006.253.07:40:48.52#ibcon#*mode == 0, iclass 27, count 0 2006.253.07:40:48.52#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.253.07:40:48.52#ibcon#[25=USB\r\n] 2006.253.07:40:48.52#ibcon#*before write, iclass 27, count 0 2006.253.07:40:48.52#ibcon#enter sib2, iclass 27, count 0 2006.253.07:40:48.52#ibcon#flushed, iclass 27, count 0 2006.253.07:40:48.52#ibcon#about to write, iclass 27, count 0 2006.253.07:40:48.52#ibcon#wrote, iclass 27, count 0 2006.253.07:40:48.52#ibcon#about to read 3, iclass 27, count 0 2006.253.07:40:48.55#ibcon#read 3, iclass 27, count 0 2006.253.07:40:48.55#ibcon#about to read 4, iclass 27, count 0 2006.253.07:40:48.55#ibcon#read 4, iclass 27, count 0 2006.253.07:40:48.55#ibcon#about to read 5, iclass 27, count 0 2006.253.07:40:48.55#ibcon#read 5, iclass 27, count 0 2006.253.07:40:48.55#ibcon#about to read 6, iclass 27, count 0 2006.253.07:40:48.55#ibcon#read 6, iclass 27, count 0 2006.253.07:40:48.55#ibcon#end of sib2, iclass 27, count 0 2006.253.07:40:48.55#ibcon#*after write, iclass 27, count 0 2006.253.07:40:48.55#ibcon#*before return 0, iclass 27, count 0 2006.253.07:40:48.55#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.253.07:40:48.55#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.253.07:40:48.55#ibcon#about to clear, iclass 27 cls_cnt 0 2006.253.07:40:48.55#ibcon#cleared, iclass 27 cls_cnt 0 2006.253.07:40:48.55$vc4f8/valo=3,672.99 2006.253.07:40:48.55#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.253.07:40:48.55#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.253.07:40:48.55#ibcon#ireg 17 cls_cnt 0 2006.253.07:40:48.55#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.253.07:40:48.55#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.253.07:40:48.55#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.253.07:40:48.55#ibcon#enter wrdev, iclass 29, count 0 2006.253.07:40:48.55#ibcon#first serial, iclass 29, count 0 2006.253.07:40:48.55#ibcon#enter sib2, iclass 29, count 0 2006.253.07:40:48.55#ibcon#flushed, iclass 29, count 0 2006.253.07:40:48.55#ibcon#about to write, iclass 29, count 0 2006.253.07:40:48.55#ibcon#wrote, iclass 29, count 0 2006.253.07:40:48.55#ibcon#about to read 3, iclass 29, count 0 2006.253.07:40:48.57#ibcon#read 3, iclass 29, count 0 2006.253.07:40:48.57#ibcon#about to read 4, iclass 29, count 0 2006.253.07:40:48.57#ibcon#read 4, iclass 29, count 0 2006.253.07:40:48.57#ibcon#about to read 5, iclass 29, count 0 2006.253.07:40:48.57#ibcon#read 5, iclass 29, count 0 2006.253.07:40:48.57#ibcon#about to read 6, iclass 29, count 0 2006.253.07:40:48.57#ibcon#read 6, iclass 29, count 0 2006.253.07:40:48.57#ibcon#end of sib2, iclass 29, count 0 2006.253.07:40:48.57#ibcon#*mode == 0, iclass 29, count 0 2006.253.07:40:48.57#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.253.07:40:48.57#ibcon#[26=FRQ=03,672.99\r\n] 2006.253.07:40:48.57#ibcon#*before write, iclass 29, count 0 2006.253.07:40:48.57#ibcon#enter sib2, iclass 29, count 0 2006.253.07:40:48.57#ibcon#flushed, iclass 29, count 0 2006.253.07:40:48.57#ibcon#about to write, iclass 29, count 0 2006.253.07:40:48.57#ibcon#wrote, iclass 29, count 0 2006.253.07:40:48.57#ibcon#about to read 3, iclass 29, count 0 2006.253.07:40:48.62#ibcon#read 3, iclass 29, count 0 2006.253.07:40:48.62#ibcon#about to read 4, iclass 29, count 0 2006.253.07:40:48.62#ibcon#read 4, iclass 29, count 0 2006.253.07:40:48.62#ibcon#about to read 5, iclass 29, count 0 2006.253.07:40:48.62#ibcon#read 5, iclass 29, count 0 2006.253.07:40:48.62#ibcon#about to read 6, iclass 29, count 0 2006.253.07:40:48.62#ibcon#read 6, iclass 29, count 0 2006.253.07:40:48.62#ibcon#end of sib2, iclass 29, count 0 2006.253.07:40:48.62#ibcon#*after write, iclass 29, count 0 2006.253.07:40:48.62#ibcon#*before return 0, iclass 29, count 0 2006.253.07:40:48.62#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.253.07:40:48.62#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.253.07:40:48.62#ibcon#about to clear, iclass 29 cls_cnt 0 2006.253.07:40:48.62#ibcon#cleared, iclass 29 cls_cnt 0 2006.253.07:40:48.62$vc4f8/va=3,6 2006.253.07:40:48.62#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.253.07:40:48.62#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.253.07:40:48.62#ibcon#ireg 11 cls_cnt 2 2006.253.07:40:48.62#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.253.07:40:48.67#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.253.07:40:48.67#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.253.07:40:48.67#ibcon#enter wrdev, iclass 31, count 2 2006.253.07:40:48.67#ibcon#first serial, iclass 31, count 2 2006.253.07:40:48.67#ibcon#enter sib2, iclass 31, count 2 2006.253.07:40:48.67#ibcon#flushed, iclass 31, count 2 2006.253.07:40:48.67#ibcon#about to write, iclass 31, count 2 2006.253.07:40:48.67#ibcon#wrote, iclass 31, count 2 2006.253.07:40:48.67#ibcon#about to read 3, iclass 31, count 2 2006.253.07:40:48.69#ibcon#read 3, iclass 31, count 2 2006.253.07:40:48.69#ibcon#about to read 4, iclass 31, count 2 2006.253.07:40:48.69#ibcon#read 4, iclass 31, count 2 2006.253.07:40:48.69#ibcon#about to read 5, iclass 31, count 2 2006.253.07:40:48.69#ibcon#read 5, iclass 31, count 2 2006.253.07:40:48.69#ibcon#about to read 6, iclass 31, count 2 2006.253.07:40:48.69#ibcon#read 6, iclass 31, count 2 2006.253.07:40:48.69#ibcon#end of sib2, iclass 31, count 2 2006.253.07:40:48.69#ibcon#*mode == 0, iclass 31, count 2 2006.253.07:40:48.69#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.253.07:40:48.69#ibcon#[25=AT03-06\r\n] 2006.253.07:40:48.69#ibcon#*before write, iclass 31, count 2 2006.253.07:40:48.69#ibcon#enter sib2, iclass 31, count 2 2006.253.07:40:48.69#ibcon#flushed, iclass 31, count 2 2006.253.07:40:48.69#ibcon#about to write, iclass 31, count 2 2006.253.07:40:48.69#ibcon#wrote, iclass 31, count 2 2006.253.07:40:48.69#ibcon#about to read 3, iclass 31, count 2 2006.253.07:40:48.72#ibcon#read 3, iclass 31, count 2 2006.253.07:40:48.72#ibcon#about to read 4, iclass 31, count 2 2006.253.07:40:48.72#ibcon#read 4, iclass 31, count 2 2006.253.07:40:48.72#ibcon#about to read 5, iclass 31, count 2 2006.253.07:40:48.72#ibcon#read 5, iclass 31, count 2 2006.253.07:40:48.72#ibcon#about to read 6, iclass 31, count 2 2006.253.07:40:48.72#ibcon#read 6, iclass 31, count 2 2006.253.07:40:48.72#ibcon#end of sib2, iclass 31, count 2 2006.253.07:40:48.72#ibcon#*after write, iclass 31, count 2 2006.253.07:40:48.72#ibcon#*before return 0, iclass 31, count 2 2006.253.07:40:48.72#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.253.07:40:48.72#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.253.07:40:48.72#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.253.07:40:48.72#ibcon#ireg 7 cls_cnt 0 2006.253.07:40:48.72#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.253.07:40:48.84#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.253.07:40:48.84#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.253.07:40:48.84#ibcon#enter wrdev, iclass 31, count 0 2006.253.07:40:48.84#ibcon#first serial, iclass 31, count 0 2006.253.07:40:48.84#ibcon#enter sib2, iclass 31, count 0 2006.253.07:40:48.84#ibcon#flushed, iclass 31, count 0 2006.253.07:40:48.84#ibcon#about to write, iclass 31, count 0 2006.253.07:40:48.84#ibcon#wrote, iclass 31, count 0 2006.253.07:40:48.84#ibcon#about to read 3, iclass 31, count 0 2006.253.07:40:48.86#ibcon#read 3, iclass 31, count 0 2006.253.07:40:48.86#ibcon#about to read 4, iclass 31, count 0 2006.253.07:40:48.86#ibcon#read 4, iclass 31, count 0 2006.253.07:40:48.86#ibcon#about to read 5, iclass 31, count 0 2006.253.07:40:48.86#ibcon#read 5, iclass 31, count 0 2006.253.07:40:48.86#ibcon#about to read 6, iclass 31, count 0 2006.253.07:40:48.86#ibcon#read 6, iclass 31, count 0 2006.253.07:40:48.86#ibcon#end of sib2, iclass 31, count 0 2006.253.07:40:48.86#ibcon#*mode == 0, iclass 31, count 0 2006.253.07:40:48.86#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.253.07:40:48.86#ibcon#[25=USB\r\n] 2006.253.07:40:48.86#ibcon#*before write, iclass 31, count 0 2006.253.07:40:48.86#ibcon#enter sib2, iclass 31, count 0 2006.253.07:40:48.86#ibcon#flushed, iclass 31, count 0 2006.253.07:40:48.86#ibcon#about to write, iclass 31, count 0 2006.253.07:40:48.86#ibcon#wrote, iclass 31, count 0 2006.253.07:40:48.86#ibcon#about to read 3, iclass 31, count 0 2006.253.07:40:48.89#ibcon#read 3, iclass 31, count 0 2006.253.07:40:48.89#ibcon#about to read 4, iclass 31, count 0 2006.253.07:40:48.89#ibcon#read 4, iclass 31, count 0 2006.253.07:40:48.89#ibcon#about to read 5, iclass 31, count 0 2006.253.07:40:48.89#ibcon#read 5, iclass 31, count 0 2006.253.07:40:48.89#ibcon#about to read 6, iclass 31, count 0 2006.253.07:40:48.89#ibcon#read 6, iclass 31, count 0 2006.253.07:40:48.89#ibcon#end of sib2, iclass 31, count 0 2006.253.07:40:48.89#ibcon#*after write, iclass 31, count 0 2006.253.07:40:48.89#ibcon#*before return 0, iclass 31, count 0 2006.253.07:40:48.89#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.253.07:40:48.89#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.253.07:40:48.89#ibcon#about to clear, iclass 31 cls_cnt 0 2006.253.07:40:48.89#ibcon#cleared, iclass 31 cls_cnt 0 2006.253.07:40:48.89$vc4f8/valo=4,832.99 2006.253.07:40:48.89#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.253.07:40:48.89#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.253.07:40:48.89#ibcon#ireg 17 cls_cnt 0 2006.253.07:40:48.89#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.253.07:40:48.89#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.253.07:40:48.89#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.253.07:40:48.89#ibcon#enter wrdev, iclass 33, count 0 2006.253.07:40:48.89#ibcon#first serial, iclass 33, count 0 2006.253.07:40:48.89#ibcon#enter sib2, iclass 33, count 0 2006.253.07:40:48.89#ibcon#flushed, iclass 33, count 0 2006.253.07:40:48.89#ibcon#about to write, iclass 33, count 0 2006.253.07:40:48.89#ibcon#wrote, iclass 33, count 0 2006.253.07:40:48.89#ibcon#about to read 3, iclass 33, count 0 2006.253.07:40:48.91#ibcon#read 3, iclass 33, count 0 2006.253.07:40:48.91#ibcon#about to read 4, iclass 33, count 0 2006.253.07:40:48.91#ibcon#read 4, iclass 33, count 0 2006.253.07:40:48.91#ibcon#about to read 5, iclass 33, count 0 2006.253.07:40:48.91#ibcon#read 5, iclass 33, count 0 2006.253.07:40:48.91#ibcon#about to read 6, iclass 33, count 0 2006.253.07:40:48.91#ibcon#read 6, iclass 33, count 0 2006.253.07:40:48.91#ibcon#end of sib2, iclass 33, count 0 2006.253.07:40:48.91#ibcon#*mode == 0, iclass 33, count 0 2006.253.07:40:48.91#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.253.07:40:48.91#ibcon#[26=FRQ=04,832.99\r\n] 2006.253.07:40:48.91#ibcon#*before write, iclass 33, count 0 2006.253.07:40:48.91#ibcon#enter sib2, iclass 33, count 0 2006.253.07:40:48.91#ibcon#flushed, iclass 33, count 0 2006.253.07:40:48.91#ibcon#about to write, iclass 33, count 0 2006.253.07:40:48.91#ibcon#wrote, iclass 33, count 0 2006.253.07:40:48.91#ibcon#about to read 3, iclass 33, count 0 2006.253.07:40:48.95#ibcon#read 3, iclass 33, count 0 2006.253.07:40:48.95#ibcon#about to read 4, iclass 33, count 0 2006.253.07:40:48.95#ibcon#read 4, iclass 33, count 0 2006.253.07:40:48.95#ibcon#about to read 5, iclass 33, count 0 2006.253.07:40:48.95#ibcon#read 5, iclass 33, count 0 2006.253.07:40:48.95#ibcon#about to read 6, iclass 33, count 0 2006.253.07:40:48.95#ibcon#read 6, iclass 33, count 0 2006.253.07:40:48.95#ibcon#end of sib2, iclass 33, count 0 2006.253.07:40:48.95#ibcon#*after write, iclass 33, count 0 2006.253.07:40:48.95#ibcon#*before return 0, iclass 33, count 0 2006.253.07:40:48.95#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.253.07:40:48.95#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.253.07:40:48.95#ibcon#about to clear, iclass 33 cls_cnt 0 2006.253.07:40:48.95#ibcon#cleared, iclass 33 cls_cnt 0 2006.253.07:40:48.95$vc4f8/va=4,7 2006.253.07:40:48.95#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.253.07:40:48.95#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.253.07:40:48.95#ibcon#ireg 11 cls_cnt 2 2006.253.07:40:48.95#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.253.07:40:49.01#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.253.07:40:49.01#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.253.07:40:49.01#ibcon#enter wrdev, iclass 35, count 2 2006.253.07:40:49.01#ibcon#first serial, iclass 35, count 2 2006.253.07:40:49.01#ibcon#enter sib2, iclass 35, count 2 2006.253.07:40:49.01#ibcon#flushed, iclass 35, count 2 2006.253.07:40:49.01#ibcon#about to write, iclass 35, count 2 2006.253.07:40:49.01#ibcon#wrote, iclass 35, count 2 2006.253.07:40:49.01#ibcon#about to read 3, iclass 35, count 2 2006.253.07:40:49.03#ibcon#read 3, iclass 35, count 2 2006.253.07:40:49.03#ibcon#about to read 4, iclass 35, count 2 2006.253.07:40:49.03#ibcon#read 4, iclass 35, count 2 2006.253.07:40:49.03#ibcon#about to read 5, iclass 35, count 2 2006.253.07:40:49.03#ibcon#read 5, iclass 35, count 2 2006.253.07:40:49.03#ibcon#about to read 6, iclass 35, count 2 2006.253.07:40:49.03#ibcon#read 6, iclass 35, count 2 2006.253.07:40:49.03#ibcon#end of sib2, iclass 35, count 2 2006.253.07:40:49.03#ibcon#*mode == 0, iclass 35, count 2 2006.253.07:40:49.03#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.253.07:40:49.03#ibcon#[25=AT04-07\r\n] 2006.253.07:40:49.03#ibcon#*before write, iclass 35, count 2 2006.253.07:40:49.03#ibcon#enter sib2, iclass 35, count 2 2006.253.07:40:49.03#ibcon#flushed, iclass 35, count 2 2006.253.07:40:49.03#ibcon#about to write, iclass 35, count 2 2006.253.07:40:49.03#ibcon#wrote, iclass 35, count 2 2006.253.07:40:49.03#ibcon#about to read 3, iclass 35, count 2 2006.253.07:40:49.06#ibcon#read 3, iclass 35, count 2 2006.253.07:40:49.06#ibcon#about to read 4, iclass 35, count 2 2006.253.07:40:49.06#ibcon#read 4, iclass 35, count 2 2006.253.07:40:49.06#ibcon#about to read 5, iclass 35, count 2 2006.253.07:40:49.06#ibcon#read 5, iclass 35, count 2 2006.253.07:40:49.06#ibcon#about to read 6, iclass 35, count 2 2006.253.07:40:49.06#ibcon#read 6, iclass 35, count 2 2006.253.07:40:49.06#ibcon#end of sib2, iclass 35, count 2 2006.253.07:40:49.06#ibcon#*after write, iclass 35, count 2 2006.253.07:40:49.06#ibcon#*before return 0, iclass 35, count 2 2006.253.07:40:49.06#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.253.07:40:49.06#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.253.07:40:49.06#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.253.07:40:49.06#ibcon#ireg 7 cls_cnt 0 2006.253.07:40:49.06#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.253.07:40:49.18#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.253.07:40:49.18#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.253.07:40:49.18#ibcon#enter wrdev, iclass 35, count 0 2006.253.07:40:49.18#ibcon#first serial, iclass 35, count 0 2006.253.07:40:49.18#ibcon#enter sib2, iclass 35, count 0 2006.253.07:40:49.18#ibcon#flushed, iclass 35, count 0 2006.253.07:40:49.18#ibcon#about to write, iclass 35, count 0 2006.253.07:40:49.18#ibcon#wrote, iclass 35, count 0 2006.253.07:40:49.18#ibcon#about to read 3, iclass 35, count 0 2006.253.07:40:49.20#ibcon#read 3, iclass 35, count 0 2006.253.07:40:49.20#ibcon#about to read 4, iclass 35, count 0 2006.253.07:40:49.20#ibcon#read 4, iclass 35, count 0 2006.253.07:40:49.20#ibcon#about to read 5, iclass 35, count 0 2006.253.07:40:49.20#ibcon#read 5, iclass 35, count 0 2006.253.07:40:49.20#ibcon#about to read 6, iclass 35, count 0 2006.253.07:40:49.20#ibcon#read 6, iclass 35, count 0 2006.253.07:40:49.20#ibcon#end of sib2, iclass 35, count 0 2006.253.07:40:49.20#ibcon#*mode == 0, iclass 35, count 0 2006.253.07:40:49.20#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.253.07:40:49.20#ibcon#[25=USB\r\n] 2006.253.07:40:49.20#ibcon#*before write, iclass 35, count 0 2006.253.07:40:49.20#ibcon#enter sib2, iclass 35, count 0 2006.253.07:40:49.20#ibcon#flushed, iclass 35, count 0 2006.253.07:40:49.20#ibcon#about to write, iclass 35, count 0 2006.253.07:40:49.20#ibcon#wrote, iclass 35, count 0 2006.253.07:40:49.20#ibcon#about to read 3, iclass 35, count 0 2006.253.07:40:49.23#ibcon#read 3, iclass 35, count 0 2006.253.07:40:49.23#ibcon#about to read 4, iclass 35, count 0 2006.253.07:40:49.23#ibcon#read 4, iclass 35, count 0 2006.253.07:40:49.23#ibcon#about to read 5, iclass 35, count 0 2006.253.07:40:49.23#ibcon#read 5, iclass 35, count 0 2006.253.07:40:49.23#ibcon#about to read 6, iclass 35, count 0 2006.253.07:40:49.23#ibcon#read 6, iclass 35, count 0 2006.253.07:40:49.23#ibcon#end of sib2, iclass 35, count 0 2006.253.07:40:49.23#ibcon#*after write, iclass 35, count 0 2006.253.07:40:49.23#ibcon#*before return 0, iclass 35, count 0 2006.253.07:40:49.23#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.253.07:40:49.23#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.253.07:40:49.23#ibcon#about to clear, iclass 35 cls_cnt 0 2006.253.07:40:49.23#ibcon#cleared, iclass 35 cls_cnt 0 2006.253.07:40:49.23$vc4f8/valo=5,652.99 2006.253.07:40:49.23#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.253.07:40:49.23#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.253.07:40:49.23#ibcon#ireg 17 cls_cnt 0 2006.253.07:40:49.23#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.253.07:40:49.23#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.253.07:40:49.23#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.253.07:40:49.23#ibcon#enter wrdev, iclass 37, count 0 2006.253.07:40:49.23#ibcon#first serial, iclass 37, count 0 2006.253.07:40:49.23#ibcon#enter sib2, iclass 37, count 0 2006.253.07:40:49.23#ibcon#flushed, iclass 37, count 0 2006.253.07:40:49.23#ibcon#about to write, iclass 37, count 0 2006.253.07:40:49.23#ibcon#wrote, iclass 37, count 0 2006.253.07:40:49.23#ibcon#about to read 3, iclass 37, count 0 2006.253.07:40:49.25#ibcon#read 3, iclass 37, count 0 2006.253.07:40:49.25#ibcon#about to read 4, iclass 37, count 0 2006.253.07:40:49.25#ibcon#read 4, iclass 37, count 0 2006.253.07:40:49.25#ibcon#about to read 5, iclass 37, count 0 2006.253.07:40:49.25#ibcon#read 5, iclass 37, count 0 2006.253.07:40:49.25#ibcon#about to read 6, iclass 37, count 0 2006.253.07:40:49.25#ibcon#read 6, iclass 37, count 0 2006.253.07:40:49.25#ibcon#end of sib2, iclass 37, count 0 2006.253.07:40:49.25#ibcon#*mode == 0, iclass 37, count 0 2006.253.07:40:49.25#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.253.07:40:49.25#ibcon#[26=FRQ=05,652.99\r\n] 2006.253.07:40:49.25#ibcon#*before write, iclass 37, count 0 2006.253.07:40:49.25#ibcon#enter sib2, iclass 37, count 0 2006.253.07:40:49.25#ibcon#flushed, iclass 37, count 0 2006.253.07:40:49.25#ibcon#about to write, iclass 37, count 0 2006.253.07:40:49.25#ibcon#wrote, iclass 37, count 0 2006.253.07:40:49.25#ibcon#about to read 3, iclass 37, count 0 2006.253.07:40:49.29#ibcon#read 3, iclass 37, count 0 2006.253.07:40:49.29#ibcon#about to read 4, iclass 37, count 0 2006.253.07:40:49.29#ibcon#read 4, iclass 37, count 0 2006.253.07:40:49.29#ibcon#about to read 5, iclass 37, count 0 2006.253.07:40:49.29#ibcon#read 5, iclass 37, count 0 2006.253.07:40:49.29#ibcon#about to read 6, iclass 37, count 0 2006.253.07:40:49.29#ibcon#read 6, iclass 37, count 0 2006.253.07:40:49.29#ibcon#end of sib2, iclass 37, count 0 2006.253.07:40:49.29#ibcon#*after write, iclass 37, count 0 2006.253.07:40:49.29#ibcon#*before return 0, iclass 37, count 0 2006.253.07:40:49.29#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.253.07:40:49.29#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.253.07:40:49.29#ibcon#about to clear, iclass 37 cls_cnt 0 2006.253.07:40:49.29#ibcon#cleared, iclass 37 cls_cnt 0 2006.253.07:40:49.29$vc4f8/va=5,7 2006.253.07:40:49.29#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.253.07:40:49.29#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.253.07:40:49.29#ibcon#ireg 11 cls_cnt 2 2006.253.07:40:49.29#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.253.07:40:49.35#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.253.07:40:49.35#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.253.07:40:49.35#ibcon#enter wrdev, iclass 39, count 2 2006.253.07:40:49.35#ibcon#first serial, iclass 39, count 2 2006.253.07:40:49.35#ibcon#enter sib2, iclass 39, count 2 2006.253.07:40:49.35#ibcon#flushed, iclass 39, count 2 2006.253.07:40:49.35#ibcon#about to write, iclass 39, count 2 2006.253.07:40:49.35#ibcon#wrote, iclass 39, count 2 2006.253.07:40:49.35#ibcon#about to read 3, iclass 39, count 2 2006.253.07:40:49.37#ibcon#read 3, iclass 39, count 2 2006.253.07:40:49.37#ibcon#about to read 4, iclass 39, count 2 2006.253.07:40:49.37#ibcon#read 4, iclass 39, count 2 2006.253.07:40:49.37#ibcon#about to read 5, iclass 39, count 2 2006.253.07:40:49.37#ibcon#read 5, iclass 39, count 2 2006.253.07:40:49.37#ibcon#about to read 6, iclass 39, count 2 2006.253.07:40:49.37#ibcon#read 6, iclass 39, count 2 2006.253.07:40:49.37#ibcon#end of sib2, iclass 39, count 2 2006.253.07:40:49.37#ibcon#*mode == 0, iclass 39, count 2 2006.253.07:40:49.37#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.253.07:40:49.37#ibcon#[25=AT05-07\r\n] 2006.253.07:40:49.37#ibcon#*before write, iclass 39, count 2 2006.253.07:40:49.37#ibcon#enter sib2, iclass 39, count 2 2006.253.07:40:49.37#ibcon#flushed, iclass 39, count 2 2006.253.07:40:49.37#ibcon#about to write, iclass 39, count 2 2006.253.07:40:49.37#ibcon#wrote, iclass 39, count 2 2006.253.07:40:49.37#ibcon#about to read 3, iclass 39, count 2 2006.253.07:40:49.40#ibcon#read 3, iclass 39, count 2 2006.253.07:40:49.40#ibcon#about to read 4, iclass 39, count 2 2006.253.07:40:49.40#ibcon#read 4, iclass 39, count 2 2006.253.07:40:49.40#ibcon#about to read 5, iclass 39, count 2 2006.253.07:40:49.40#ibcon#read 5, iclass 39, count 2 2006.253.07:40:49.40#ibcon#about to read 6, iclass 39, count 2 2006.253.07:40:49.40#ibcon#read 6, iclass 39, count 2 2006.253.07:40:49.40#ibcon#end of sib2, iclass 39, count 2 2006.253.07:40:49.40#ibcon#*after write, iclass 39, count 2 2006.253.07:40:49.40#ibcon#*before return 0, iclass 39, count 2 2006.253.07:40:49.40#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.253.07:40:49.40#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.253.07:40:49.40#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.253.07:40:49.40#ibcon#ireg 7 cls_cnt 0 2006.253.07:40:49.40#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.253.07:40:49.52#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.253.07:40:49.52#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.253.07:40:49.52#ibcon#enter wrdev, iclass 39, count 0 2006.253.07:40:49.52#ibcon#first serial, iclass 39, count 0 2006.253.07:40:49.52#ibcon#enter sib2, iclass 39, count 0 2006.253.07:40:49.52#ibcon#flushed, iclass 39, count 0 2006.253.07:40:49.52#ibcon#about to write, iclass 39, count 0 2006.253.07:40:49.52#ibcon#wrote, iclass 39, count 0 2006.253.07:40:49.52#ibcon#about to read 3, iclass 39, count 0 2006.253.07:40:49.54#ibcon#read 3, iclass 39, count 0 2006.253.07:40:49.54#ibcon#about to read 4, iclass 39, count 0 2006.253.07:40:49.54#ibcon#read 4, iclass 39, count 0 2006.253.07:40:49.54#ibcon#about to read 5, iclass 39, count 0 2006.253.07:40:49.54#ibcon#read 5, iclass 39, count 0 2006.253.07:40:49.54#ibcon#about to read 6, iclass 39, count 0 2006.253.07:40:49.54#ibcon#read 6, iclass 39, count 0 2006.253.07:40:49.54#ibcon#end of sib2, iclass 39, count 0 2006.253.07:40:49.54#ibcon#*mode == 0, iclass 39, count 0 2006.253.07:40:49.54#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.253.07:40:49.54#ibcon#[25=USB\r\n] 2006.253.07:40:49.54#ibcon#*before write, iclass 39, count 0 2006.253.07:40:49.54#ibcon#enter sib2, iclass 39, count 0 2006.253.07:40:49.54#ibcon#flushed, iclass 39, count 0 2006.253.07:40:49.54#ibcon#about to write, iclass 39, count 0 2006.253.07:40:49.54#ibcon#wrote, iclass 39, count 0 2006.253.07:40:49.54#ibcon#about to read 3, iclass 39, count 0 2006.253.07:40:49.57#ibcon#read 3, iclass 39, count 0 2006.253.07:40:49.57#ibcon#about to read 4, iclass 39, count 0 2006.253.07:40:49.57#ibcon#read 4, iclass 39, count 0 2006.253.07:40:49.57#ibcon#about to read 5, iclass 39, count 0 2006.253.07:40:49.57#ibcon#read 5, iclass 39, count 0 2006.253.07:40:49.57#ibcon#about to read 6, iclass 39, count 0 2006.253.07:40:49.57#ibcon#read 6, iclass 39, count 0 2006.253.07:40:49.57#ibcon#end of sib2, iclass 39, count 0 2006.253.07:40:49.57#ibcon#*after write, iclass 39, count 0 2006.253.07:40:49.57#ibcon#*before return 0, iclass 39, count 0 2006.253.07:40:49.57#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.253.07:40:49.57#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.253.07:40:49.57#ibcon#about to clear, iclass 39 cls_cnt 0 2006.253.07:40:49.57#ibcon#cleared, iclass 39 cls_cnt 0 2006.253.07:40:49.57$vc4f8/valo=6,772.99 2006.253.07:40:49.57#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.253.07:40:49.57#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.253.07:40:49.57#ibcon#ireg 17 cls_cnt 0 2006.253.07:40:49.57#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.253.07:40:49.57#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.253.07:40:49.57#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.253.07:40:49.57#ibcon#enter wrdev, iclass 3, count 0 2006.253.07:40:49.57#ibcon#first serial, iclass 3, count 0 2006.253.07:40:49.57#ibcon#enter sib2, iclass 3, count 0 2006.253.07:40:49.57#ibcon#flushed, iclass 3, count 0 2006.253.07:40:49.57#ibcon#about to write, iclass 3, count 0 2006.253.07:40:49.57#ibcon#wrote, iclass 3, count 0 2006.253.07:40:49.57#ibcon#about to read 3, iclass 3, count 0 2006.253.07:40:49.59#ibcon#read 3, iclass 3, count 0 2006.253.07:40:49.59#ibcon#about to read 4, iclass 3, count 0 2006.253.07:40:49.59#ibcon#read 4, iclass 3, count 0 2006.253.07:40:49.59#ibcon#about to read 5, iclass 3, count 0 2006.253.07:40:49.59#ibcon#read 5, iclass 3, count 0 2006.253.07:40:49.59#ibcon#about to read 6, iclass 3, count 0 2006.253.07:40:49.59#ibcon#read 6, iclass 3, count 0 2006.253.07:40:49.59#ibcon#end of sib2, iclass 3, count 0 2006.253.07:40:49.59#ibcon#*mode == 0, iclass 3, count 0 2006.253.07:40:49.59#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.253.07:40:49.59#ibcon#[26=FRQ=06,772.99\r\n] 2006.253.07:40:49.59#ibcon#*before write, iclass 3, count 0 2006.253.07:40:49.59#ibcon#enter sib2, iclass 3, count 0 2006.253.07:40:49.59#ibcon#flushed, iclass 3, count 0 2006.253.07:40:49.59#ibcon#about to write, iclass 3, count 0 2006.253.07:40:49.59#ibcon#wrote, iclass 3, count 0 2006.253.07:40:49.59#ibcon#about to read 3, iclass 3, count 0 2006.253.07:40:49.64#ibcon#read 3, iclass 3, count 0 2006.253.07:40:49.64#ibcon#about to read 4, iclass 3, count 0 2006.253.07:40:49.64#ibcon#read 4, iclass 3, count 0 2006.253.07:40:49.64#ibcon#about to read 5, iclass 3, count 0 2006.253.07:40:49.64#ibcon#read 5, iclass 3, count 0 2006.253.07:40:49.64#ibcon#about to read 6, iclass 3, count 0 2006.253.07:40:49.64#ibcon#read 6, iclass 3, count 0 2006.253.07:40:49.64#ibcon#end of sib2, iclass 3, count 0 2006.253.07:40:49.64#ibcon#*after write, iclass 3, count 0 2006.253.07:40:49.64#ibcon#*before return 0, iclass 3, count 0 2006.253.07:40:49.64#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.253.07:40:49.64#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.253.07:40:49.64#ibcon#about to clear, iclass 3 cls_cnt 0 2006.253.07:40:49.64#ibcon#cleared, iclass 3 cls_cnt 0 2006.253.07:40:49.64$vc4f8/va=6,7 2006.253.07:40:49.64#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.253.07:40:49.64#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.253.07:40:49.64#ibcon#ireg 11 cls_cnt 2 2006.253.07:40:49.64#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.253.07:40:49.69#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.253.07:40:49.69#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.253.07:40:49.69#ibcon#enter wrdev, iclass 5, count 2 2006.253.07:40:49.69#ibcon#first serial, iclass 5, count 2 2006.253.07:40:49.69#ibcon#enter sib2, iclass 5, count 2 2006.253.07:40:49.69#ibcon#flushed, iclass 5, count 2 2006.253.07:40:49.69#ibcon#about to write, iclass 5, count 2 2006.253.07:40:49.69#ibcon#wrote, iclass 5, count 2 2006.253.07:40:49.69#ibcon#about to read 3, iclass 5, count 2 2006.253.07:40:49.71#ibcon#read 3, iclass 5, count 2 2006.253.07:40:49.71#ibcon#about to read 4, iclass 5, count 2 2006.253.07:40:49.71#ibcon#read 4, iclass 5, count 2 2006.253.07:40:49.71#ibcon#about to read 5, iclass 5, count 2 2006.253.07:40:49.71#ibcon#read 5, iclass 5, count 2 2006.253.07:40:49.71#ibcon#about to read 6, iclass 5, count 2 2006.253.07:40:49.71#ibcon#read 6, iclass 5, count 2 2006.253.07:40:49.71#ibcon#end of sib2, iclass 5, count 2 2006.253.07:40:49.71#ibcon#*mode == 0, iclass 5, count 2 2006.253.07:40:49.71#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.253.07:40:49.71#ibcon#[25=AT06-07\r\n] 2006.253.07:40:49.71#ibcon#*before write, iclass 5, count 2 2006.253.07:40:49.71#ibcon#enter sib2, iclass 5, count 2 2006.253.07:40:49.71#ibcon#flushed, iclass 5, count 2 2006.253.07:40:49.71#ibcon#about to write, iclass 5, count 2 2006.253.07:40:49.71#ibcon#wrote, iclass 5, count 2 2006.253.07:40:49.71#ibcon#about to read 3, iclass 5, count 2 2006.253.07:40:49.74#ibcon#read 3, iclass 5, count 2 2006.253.07:40:49.74#ibcon#about to read 4, iclass 5, count 2 2006.253.07:40:49.74#ibcon#read 4, iclass 5, count 2 2006.253.07:40:49.74#ibcon#about to read 5, iclass 5, count 2 2006.253.07:40:49.74#ibcon#read 5, iclass 5, count 2 2006.253.07:40:49.74#ibcon#about to read 6, iclass 5, count 2 2006.253.07:40:49.74#ibcon#read 6, iclass 5, count 2 2006.253.07:40:49.74#ibcon#end of sib2, iclass 5, count 2 2006.253.07:40:49.74#ibcon#*after write, iclass 5, count 2 2006.253.07:40:49.74#ibcon#*before return 0, iclass 5, count 2 2006.253.07:40:49.74#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.253.07:40:49.74#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.253.07:40:49.74#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.253.07:40:49.74#ibcon#ireg 7 cls_cnt 0 2006.253.07:40:49.74#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.253.07:40:49.86#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.253.07:40:49.86#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.253.07:40:49.86#ibcon#enter wrdev, iclass 5, count 0 2006.253.07:40:49.86#ibcon#first serial, iclass 5, count 0 2006.253.07:40:49.86#ibcon#enter sib2, iclass 5, count 0 2006.253.07:40:49.86#ibcon#flushed, iclass 5, count 0 2006.253.07:40:49.86#ibcon#about to write, iclass 5, count 0 2006.253.07:40:49.86#ibcon#wrote, iclass 5, count 0 2006.253.07:40:49.86#ibcon#about to read 3, iclass 5, count 0 2006.253.07:40:49.88#ibcon#read 3, iclass 5, count 0 2006.253.07:40:49.88#ibcon#about to read 4, iclass 5, count 0 2006.253.07:40:49.88#ibcon#read 4, iclass 5, count 0 2006.253.07:40:49.88#ibcon#about to read 5, iclass 5, count 0 2006.253.07:40:49.88#ibcon#read 5, iclass 5, count 0 2006.253.07:40:49.88#ibcon#about to read 6, iclass 5, count 0 2006.253.07:40:49.88#ibcon#read 6, iclass 5, count 0 2006.253.07:40:49.88#ibcon#end of sib2, iclass 5, count 0 2006.253.07:40:49.88#ibcon#*mode == 0, iclass 5, count 0 2006.253.07:40:49.88#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.253.07:40:49.88#ibcon#[25=USB\r\n] 2006.253.07:40:49.88#ibcon#*before write, iclass 5, count 0 2006.253.07:40:49.88#ibcon#enter sib2, iclass 5, count 0 2006.253.07:40:49.88#ibcon#flushed, iclass 5, count 0 2006.253.07:40:49.88#ibcon#about to write, iclass 5, count 0 2006.253.07:40:49.88#ibcon#wrote, iclass 5, count 0 2006.253.07:40:49.88#ibcon#about to read 3, iclass 5, count 0 2006.253.07:40:49.91#ibcon#read 3, iclass 5, count 0 2006.253.07:40:49.91#ibcon#about to read 4, iclass 5, count 0 2006.253.07:40:49.91#ibcon#read 4, iclass 5, count 0 2006.253.07:40:49.91#ibcon#about to read 5, iclass 5, count 0 2006.253.07:40:49.91#ibcon#read 5, iclass 5, count 0 2006.253.07:40:49.91#ibcon#about to read 6, iclass 5, count 0 2006.253.07:40:49.91#ibcon#read 6, iclass 5, count 0 2006.253.07:40:49.91#ibcon#end of sib2, iclass 5, count 0 2006.253.07:40:49.91#ibcon#*after write, iclass 5, count 0 2006.253.07:40:49.91#ibcon#*before return 0, iclass 5, count 0 2006.253.07:40:49.91#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.253.07:40:49.91#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.253.07:40:49.91#ibcon#about to clear, iclass 5 cls_cnt 0 2006.253.07:40:49.91#ibcon#cleared, iclass 5 cls_cnt 0 2006.253.07:40:49.91$vc4f8/valo=7,832.99 2006.253.07:40:49.91#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.253.07:40:49.91#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.253.07:40:49.91#ibcon#ireg 17 cls_cnt 0 2006.253.07:40:49.91#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.253.07:40:49.91#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.253.07:40:49.91#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.253.07:40:49.91#ibcon#enter wrdev, iclass 7, count 0 2006.253.07:40:49.91#ibcon#first serial, iclass 7, count 0 2006.253.07:40:49.91#ibcon#enter sib2, iclass 7, count 0 2006.253.07:40:49.91#ibcon#flushed, iclass 7, count 0 2006.253.07:40:49.91#ibcon#about to write, iclass 7, count 0 2006.253.07:40:49.91#ibcon#wrote, iclass 7, count 0 2006.253.07:40:49.91#ibcon#about to read 3, iclass 7, count 0 2006.253.07:40:49.93#ibcon#read 3, iclass 7, count 0 2006.253.07:40:49.93#ibcon#about to read 4, iclass 7, count 0 2006.253.07:40:49.93#ibcon#read 4, iclass 7, count 0 2006.253.07:40:49.93#ibcon#about to read 5, iclass 7, count 0 2006.253.07:40:49.93#ibcon#read 5, iclass 7, count 0 2006.253.07:40:49.93#ibcon#about to read 6, iclass 7, count 0 2006.253.07:40:49.93#ibcon#read 6, iclass 7, count 0 2006.253.07:40:49.93#ibcon#end of sib2, iclass 7, count 0 2006.253.07:40:49.93#ibcon#*mode == 0, iclass 7, count 0 2006.253.07:40:49.93#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.253.07:40:49.93#ibcon#[26=FRQ=07,832.99\r\n] 2006.253.07:40:49.93#ibcon#*before write, iclass 7, count 0 2006.253.07:40:49.93#ibcon#enter sib2, iclass 7, count 0 2006.253.07:40:49.93#ibcon#flushed, iclass 7, count 0 2006.253.07:40:49.93#ibcon#about to write, iclass 7, count 0 2006.253.07:40:49.93#ibcon#wrote, iclass 7, count 0 2006.253.07:40:49.93#ibcon#about to read 3, iclass 7, count 0 2006.253.07:40:49.97#ibcon#read 3, iclass 7, count 0 2006.253.07:40:49.97#ibcon#about to read 4, iclass 7, count 0 2006.253.07:40:49.97#ibcon#read 4, iclass 7, count 0 2006.253.07:40:49.97#ibcon#about to read 5, iclass 7, count 0 2006.253.07:40:49.97#ibcon#read 5, iclass 7, count 0 2006.253.07:40:49.97#ibcon#about to read 6, iclass 7, count 0 2006.253.07:40:49.97#ibcon#read 6, iclass 7, count 0 2006.253.07:40:49.97#ibcon#end of sib2, iclass 7, count 0 2006.253.07:40:49.97#ibcon#*after write, iclass 7, count 0 2006.253.07:40:49.97#ibcon#*before return 0, iclass 7, count 0 2006.253.07:40:49.97#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.253.07:40:49.97#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.253.07:40:49.97#ibcon#about to clear, iclass 7 cls_cnt 0 2006.253.07:40:49.97#ibcon#cleared, iclass 7 cls_cnt 0 2006.253.07:40:49.97$vc4f8/va=7,7 2006.253.07:40:49.97#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.253.07:40:49.97#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.253.07:40:49.97#ibcon#ireg 11 cls_cnt 2 2006.253.07:40:49.97#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.253.07:40:50.03#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.253.07:40:50.03#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.253.07:40:50.03#ibcon#enter wrdev, iclass 11, count 2 2006.253.07:40:50.03#ibcon#first serial, iclass 11, count 2 2006.253.07:40:50.03#ibcon#enter sib2, iclass 11, count 2 2006.253.07:40:50.03#ibcon#flushed, iclass 11, count 2 2006.253.07:40:50.03#ibcon#about to write, iclass 11, count 2 2006.253.07:40:50.03#ibcon#wrote, iclass 11, count 2 2006.253.07:40:50.03#ibcon#about to read 3, iclass 11, count 2 2006.253.07:40:50.05#ibcon#read 3, iclass 11, count 2 2006.253.07:40:50.05#ibcon#about to read 4, iclass 11, count 2 2006.253.07:40:50.05#ibcon#read 4, iclass 11, count 2 2006.253.07:40:50.05#ibcon#about to read 5, iclass 11, count 2 2006.253.07:40:50.05#ibcon#read 5, iclass 11, count 2 2006.253.07:40:50.05#ibcon#about to read 6, iclass 11, count 2 2006.253.07:40:50.05#ibcon#read 6, iclass 11, count 2 2006.253.07:40:50.05#ibcon#end of sib2, iclass 11, count 2 2006.253.07:40:50.05#ibcon#*mode == 0, iclass 11, count 2 2006.253.07:40:50.05#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.253.07:40:50.05#ibcon#[25=AT07-07\r\n] 2006.253.07:40:50.05#ibcon#*before write, iclass 11, count 2 2006.253.07:40:50.05#ibcon#enter sib2, iclass 11, count 2 2006.253.07:40:50.05#ibcon#flushed, iclass 11, count 2 2006.253.07:40:50.05#ibcon#about to write, iclass 11, count 2 2006.253.07:40:50.05#ibcon#wrote, iclass 11, count 2 2006.253.07:40:50.05#ibcon#about to read 3, iclass 11, count 2 2006.253.07:40:50.08#ibcon#read 3, iclass 11, count 2 2006.253.07:40:50.08#ibcon#about to read 4, iclass 11, count 2 2006.253.07:40:50.08#ibcon#read 4, iclass 11, count 2 2006.253.07:40:50.08#ibcon#about to read 5, iclass 11, count 2 2006.253.07:40:50.08#ibcon#read 5, iclass 11, count 2 2006.253.07:40:50.08#ibcon#about to read 6, iclass 11, count 2 2006.253.07:40:50.08#ibcon#read 6, iclass 11, count 2 2006.253.07:40:50.08#ibcon#end of sib2, iclass 11, count 2 2006.253.07:40:50.08#ibcon#*after write, iclass 11, count 2 2006.253.07:40:50.08#ibcon#*before return 0, iclass 11, count 2 2006.253.07:40:50.08#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.253.07:40:50.08#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.253.07:40:50.08#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.253.07:40:50.08#ibcon#ireg 7 cls_cnt 0 2006.253.07:40:50.08#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.253.07:40:50.20#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.253.07:40:50.20#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.253.07:40:50.20#ibcon#enter wrdev, iclass 11, count 0 2006.253.07:40:50.20#ibcon#first serial, iclass 11, count 0 2006.253.07:40:50.20#ibcon#enter sib2, iclass 11, count 0 2006.253.07:40:50.20#ibcon#flushed, iclass 11, count 0 2006.253.07:40:50.20#ibcon#about to write, iclass 11, count 0 2006.253.07:40:50.20#ibcon#wrote, iclass 11, count 0 2006.253.07:40:50.20#ibcon#about to read 3, iclass 11, count 0 2006.253.07:40:50.23#ibcon#read 3, iclass 11, count 0 2006.253.07:40:50.23#ibcon#about to read 4, iclass 11, count 0 2006.253.07:40:50.23#ibcon#read 4, iclass 11, count 0 2006.253.07:40:50.23#ibcon#about to read 5, iclass 11, count 0 2006.253.07:40:50.23#ibcon#read 5, iclass 11, count 0 2006.253.07:40:50.23#ibcon#about to read 6, iclass 11, count 0 2006.253.07:40:50.23#ibcon#read 6, iclass 11, count 0 2006.253.07:40:50.23#ibcon#end of sib2, iclass 11, count 0 2006.253.07:40:50.23#ibcon#*mode == 0, iclass 11, count 0 2006.253.07:40:50.23#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.253.07:40:50.23#ibcon#[25=USB\r\n] 2006.253.07:40:50.23#ibcon#*before write, iclass 11, count 0 2006.253.07:40:50.23#ibcon#enter sib2, iclass 11, count 0 2006.253.07:40:50.23#ibcon#flushed, iclass 11, count 0 2006.253.07:40:50.23#ibcon#about to write, iclass 11, count 0 2006.253.07:40:50.23#ibcon#wrote, iclass 11, count 0 2006.253.07:40:50.23#ibcon#about to read 3, iclass 11, count 0 2006.253.07:40:50.27#ibcon#read 3, iclass 11, count 0 2006.253.07:40:50.27#ibcon#about to read 4, iclass 11, count 0 2006.253.07:40:50.27#ibcon#read 4, iclass 11, count 0 2006.253.07:40:50.27#ibcon#about to read 5, iclass 11, count 0 2006.253.07:40:50.27#ibcon#read 5, iclass 11, count 0 2006.253.07:40:50.27#ibcon#about to read 6, iclass 11, count 0 2006.253.07:40:50.27#ibcon#read 6, iclass 11, count 0 2006.253.07:40:50.27#ibcon#end of sib2, iclass 11, count 0 2006.253.07:40:50.27#ibcon#*after write, iclass 11, count 0 2006.253.07:40:50.27#ibcon#*before return 0, iclass 11, count 0 2006.253.07:40:50.27#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.253.07:40:50.27#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.253.07:40:50.27#ibcon#about to clear, iclass 11 cls_cnt 0 2006.253.07:40:50.27#ibcon#cleared, iclass 11 cls_cnt 0 2006.253.07:40:50.27$vc4f8/valo=8,852.99 2006.253.07:40:50.27#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.253.07:40:50.27#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.253.07:40:50.27#ibcon#ireg 17 cls_cnt 0 2006.253.07:40:50.27#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.253.07:40:50.27#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.253.07:40:50.27#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.253.07:40:50.27#ibcon#enter wrdev, iclass 13, count 0 2006.253.07:40:50.27#ibcon#first serial, iclass 13, count 0 2006.253.07:40:50.27#ibcon#enter sib2, iclass 13, count 0 2006.253.07:40:50.27#ibcon#flushed, iclass 13, count 0 2006.253.07:40:50.27#ibcon#about to write, iclass 13, count 0 2006.253.07:40:50.27#ibcon#wrote, iclass 13, count 0 2006.253.07:40:50.27#ibcon#about to read 3, iclass 13, count 0 2006.253.07:40:50.29#ibcon#read 3, iclass 13, count 0 2006.253.07:40:50.29#ibcon#about to read 4, iclass 13, count 0 2006.253.07:40:50.29#ibcon#read 4, iclass 13, count 0 2006.253.07:40:50.29#ibcon#about to read 5, iclass 13, count 0 2006.253.07:40:50.29#ibcon#read 5, iclass 13, count 0 2006.253.07:40:50.29#ibcon#about to read 6, iclass 13, count 0 2006.253.07:40:50.29#ibcon#read 6, iclass 13, count 0 2006.253.07:40:50.29#ibcon#end of sib2, iclass 13, count 0 2006.253.07:40:50.29#ibcon#*mode == 0, iclass 13, count 0 2006.253.07:40:50.29#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.253.07:40:50.29#ibcon#[26=FRQ=08,852.99\r\n] 2006.253.07:40:50.29#ibcon#*before write, iclass 13, count 0 2006.253.07:40:50.29#ibcon#enter sib2, iclass 13, count 0 2006.253.07:40:50.29#ibcon#flushed, iclass 13, count 0 2006.253.07:40:50.29#ibcon#about to write, iclass 13, count 0 2006.253.07:40:50.29#ibcon#wrote, iclass 13, count 0 2006.253.07:40:50.29#ibcon#about to read 3, iclass 13, count 0 2006.253.07:40:50.33#ibcon#read 3, iclass 13, count 0 2006.253.07:40:50.33#ibcon#about to read 4, iclass 13, count 0 2006.253.07:40:50.33#ibcon#read 4, iclass 13, count 0 2006.253.07:40:50.33#ibcon#about to read 5, iclass 13, count 0 2006.253.07:40:50.33#ibcon#read 5, iclass 13, count 0 2006.253.07:40:50.33#ibcon#about to read 6, iclass 13, count 0 2006.253.07:40:50.33#ibcon#read 6, iclass 13, count 0 2006.253.07:40:50.33#ibcon#end of sib2, iclass 13, count 0 2006.253.07:40:50.33#ibcon#*after write, iclass 13, count 0 2006.253.07:40:50.33#ibcon#*before return 0, iclass 13, count 0 2006.253.07:40:50.33#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.253.07:40:50.33#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.253.07:40:50.33#ibcon#about to clear, iclass 13 cls_cnt 0 2006.253.07:40:50.33#ibcon#cleared, iclass 13 cls_cnt 0 2006.253.07:40:50.33$vc4f8/va=8,7 2006.253.07:40:50.33#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.253.07:40:50.33#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.253.07:40:50.33#ibcon#ireg 11 cls_cnt 2 2006.253.07:40:50.33#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.253.07:40:50.34#abcon#<5=/08 1.1 4.1 31.47 731006.3\r\n> 2006.253.07:40:50.36#abcon#{5=INTERFACE CLEAR} 2006.253.07:40:50.39#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.253.07:40:50.39#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.253.07:40:50.39#ibcon#enter wrdev, iclass 16, count 2 2006.253.07:40:50.39#ibcon#first serial, iclass 16, count 2 2006.253.07:40:50.39#ibcon#enter sib2, iclass 16, count 2 2006.253.07:40:50.39#ibcon#flushed, iclass 16, count 2 2006.253.07:40:50.39#ibcon#about to write, iclass 16, count 2 2006.253.07:40:50.39#ibcon#wrote, iclass 16, count 2 2006.253.07:40:50.39#ibcon#about to read 3, iclass 16, count 2 2006.253.07:40:50.41#ibcon#read 3, iclass 16, count 2 2006.253.07:40:50.41#ibcon#about to read 4, iclass 16, count 2 2006.253.07:40:50.41#ibcon#read 4, iclass 16, count 2 2006.253.07:40:50.41#ibcon#about to read 5, iclass 16, count 2 2006.253.07:40:50.41#ibcon#read 5, iclass 16, count 2 2006.253.07:40:50.41#ibcon#about to read 6, iclass 16, count 2 2006.253.07:40:50.41#ibcon#read 6, iclass 16, count 2 2006.253.07:40:50.41#ibcon#end of sib2, iclass 16, count 2 2006.253.07:40:50.41#ibcon#*mode == 0, iclass 16, count 2 2006.253.07:40:50.41#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.253.07:40:50.41#ibcon#[25=AT08-07\r\n] 2006.253.07:40:50.41#ibcon#*before write, iclass 16, count 2 2006.253.07:40:50.41#ibcon#enter sib2, iclass 16, count 2 2006.253.07:40:50.41#ibcon#flushed, iclass 16, count 2 2006.253.07:40:50.41#ibcon#about to write, iclass 16, count 2 2006.253.07:40:50.41#ibcon#wrote, iclass 16, count 2 2006.253.07:40:50.41#ibcon#about to read 3, iclass 16, count 2 2006.253.07:40:50.42#abcon#[5=S1D000X0/0*\r\n] 2006.253.07:40:50.44#ibcon#read 3, iclass 16, count 2 2006.253.07:40:50.44#ibcon#about to read 4, iclass 16, count 2 2006.253.07:40:50.44#ibcon#read 4, iclass 16, count 2 2006.253.07:40:50.44#ibcon#about to read 5, iclass 16, count 2 2006.253.07:40:50.44#ibcon#read 5, iclass 16, count 2 2006.253.07:40:50.44#ibcon#about to read 6, iclass 16, count 2 2006.253.07:40:50.44#ibcon#read 6, iclass 16, count 2 2006.253.07:40:50.44#ibcon#end of sib2, iclass 16, count 2 2006.253.07:40:50.44#ibcon#*after write, iclass 16, count 2 2006.253.07:40:50.44#ibcon#*before return 0, iclass 16, count 2 2006.253.07:40:50.44#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.253.07:40:50.44#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.253.07:40:50.44#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.253.07:40:50.44#ibcon#ireg 7 cls_cnt 0 2006.253.07:40:50.44#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.253.07:40:50.56#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.253.07:40:50.56#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.253.07:40:50.56#ibcon#enter wrdev, iclass 16, count 0 2006.253.07:40:50.56#ibcon#first serial, iclass 16, count 0 2006.253.07:40:50.56#ibcon#enter sib2, iclass 16, count 0 2006.253.07:40:50.56#ibcon#flushed, iclass 16, count 0 2006.253.07:40:50.56#ibcon#about to write, iclass 16, count 0 2006.253.07:40:50.56#ibcon#wrote, iclass 16, count 0 2006.253.07:40:50.56#ibcon#about to read 3, iclass 16, count 0 2006.253.07:40:50.58#ibcon#read 3, iclass 16, count 0 2006.253.07:40:50.58#ibcon#about to read 4, iclass 16, count 0 2006.253.07:40:50.58#ibcon#read 4, iclass 16, count 0 2006.253.07:40:50.58#ibcon#about to read 5, iclass 16, count 0 2006.253.07:40:50.58#ibcon#read 5, iclass 16, count 0 2006.253.07:40:50.58#ibcon#about to read 6, iclass 16, count 0 2006.253.07:40:50.58#ibcon#read 6, iclass 16, count 0 2006.253.07:40:50.58#ibcon#end of sib2, iclass 16, count 0 2006.253.07:40:50.58#ibcon#*mode == 0, iclass 16, count 0 2006.253.07:40:50.58#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.253.07:40:50.58#ibcon#[25=USB\r\n] 2006.253.07:40:50.58#ibcon#*before write, iclass 16, count 0 2006.253.07:40:50.58#ibcon#enter sib2, iclass 16, count 0 2006.253.07:40:50.58#ibcon#flushed, iclass 16, count 0 2006.253.07:40:50.58#ibcon#about to write, iclass 16, count 0 2006.253.07:40:50.58#ibcon#wrote, iclass 16, count 0 2006.253.07:40:50.58#ibcon#about to read 3, iclass 16, count 0 2006.253.07:40:50.61#ibcon#read 3, iclass 16, count 0 2006.253.07:40:50.61#ibcon#about to read 4, iclass 16, count 0 2006.253.07:40:50.61#ibcon#read 4, iclass 16, count 0 2006.253.07:40:50.61#ibcon#about to read 5, iclass 16, count 0 2006.253.07:40:50.61#ibcon#read 5, iclass 16, count 0 2006.253.07:40:50.61#ibcon#about to read 6, iclass 16, count 0 2006.253.07:40:50.61#ibcon#read 6, iclass 16, count 0 2006.253.07:40:50.61#ibcon#end of sib2, iclass 16, count 0 2006.253.07:40:50.61#ibcon#*after write, iclass 16, count 0 2006.253.07:40:50.61#ibcon#*before return 0, iclass 16, count 0 2006.253.07:40:50.61#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.253.07:40:50.61#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.253.07:40:50.61#ibcon#about to clear, iclass 16 cls_cnt 0 2006.253.07:40:50.61#ibcon#cleared, iclass 16 cls_cnt 0 2006.253.07:40:50.61$vc4f8/vblo=1,632.99 2006.253.07:40:50.61#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.253.07:40:50.61#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.253.07:40:50.61#ibcon#ireg 17 cls_cnt 0 2006.253.07:40:50.61#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.253.07:40:50.61#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.253.07:40:50.61#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.253.07:40:50.61#ibcon#enter wrdev, iclass 21, count 0 2006.253.07:40:50.61#ibcon#first serial, iclass 21, count 0 2006.253.07:40:50.61#ibcon#enter sib2, iclass 21, count 0 2006.253.07:40:50.61#ibcon#flushed, iclass 21, count 0 2006.253.07:40:50.61#ibcon#about to write, iclass 21, count 0 2006.253.07:40:50.61#ibcon#wrote, iclass 21, count 0 2006.253.07:40:50.61#ibcon#about to read 3, iclass 21, count 0 2006.253.07:40:50.63#ibcon#read 3, iclass 21, count 0 2006.253.07:40:50.63#ibcon#about to read 4, iclass 21, count 0 2006.253.07:40:50.63#ibcon#read 4, iclass 21, count 0 2006.253.07:40:50.63#ibcon#about to read 5, iclass 21, count 0 2006.253.07:40:50.63#ibcon#read 5, iclass 21, count 0 2006.253.07:40:50.63#ibcon#about to read 6, iclass 21, count 0 2006.253.07:40:50.63#ibcon#read 6, iclass 21, count 0 2006.253.07:40:50.63#ibcon#end of sib2, iclass 21, count 0 2006.253.07:40:50.63#ibcon#*mode == 0, iclass 21, count 0 2006.253.07:40:50.63#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.253.07:40:50.63#ibcon#[28=FRQ=01,632.99\r\n] 2006.253.07:40:50.63#ibcon#*before write, iclass 21, count 0 2006.253.07:40:50.63#ibcon#enter sib2, iclass 21, count 0 2006.253.07:40:50.63#ibcon#flushed, iclass 21, count 0 2006.253.07:40:50.63#ibcon#about to write, iclass 21, count 0 2006.253.07:40:50.63#ibcon#wrote, iclass 21, count 0 2006.253.07:40:50.63#ibcon#about to read 3, iclass 21, count 0 2006.253.07:40:50.67#ibcon#read 3, iclass 21, count 0 2006.253.07:40:50.67#ibcon#about to read 4, iclass 21, count 0 2006.253.07:40:50.67#ibcon#read 4, iclass 21, count 0 2006.253.07:40:50.67#ibcon#about to read 5, iclass 21, count 0 2006.253.07:40:50.67#ibcon#read 5, iclass 21, count 0 2006.253.07:40:50.67#ibcon#about to read 6, iclass 21, count 0 2006.253.07:40:50.67#ibcon#read 6, iclass 21, count 0 2006.253.07:40:50.67#ibcon#end of sib2, iclass 21, count 0 2006.253.07:40:50.67#ibcon#*after write, iclass 21, count 0 2006.253.07:40:50.67#ibcon#*before return 0, iclass 21, count 0 2006.253.07:40:50.67#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.253.07:40:50.67#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.253.07:40:50.67#ibcon#about to clear, iclass 21 cls_cnt 0 2006.253.07:40:50.67#ibcon#cleared, iclass 21 cls_cnt 0 2006.253.07:40:50.67$vc4f8/vb=1,4 2006.253.07:40:50.67#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.253.07:40:50.67#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.253.07:40:50.67#ibcon#ireg 11 cls_cnt 2 2006.253.07:40:50.67#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.253.07:40:50.67#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.253.07:40:50.67#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.253.07:40:50.67#ibcon#enter wrdev, iclass 23, count 2 2006.253.07:40:50.67#ibcon#first serial, iclass 23, count 2 2006.253.07:40:50.67#ibcon#enter sib2, iclass 23, count 2 2006.253.07:40:50.67#ibcon#flushed, iclass 23, count 2 2006.253.07:40:50.67#ibcon#about to write, iclass 23, count 2 2006.253.07:40:50.67#ibcon#wrote, iclass 23, count 2 2006.253.07:40:50.67#ibcon#about to read 3, iclass 23, count 2 2006.253.07:40:50.69#ibcon#read 3, iclass 23, count 2 2006.253.07:40:50.69#ibcon#about to read 4, iclass 23, count 2 2006.253.07:40:50.69#ibcon#read 4, iclass 23, count 2 2006.253.07:40:50.69#ibcon#about to read 5, iclass 23, count 2 2006.253.07:40:50.69#ibcon#read 5, iclass 23, count 2 2006.253.07:40:50.69#ibcon#about to read 6, iclass 23, count 2 2006.253.07:40:50.69#ibcon#read 6, iclass 23, count 2 2006.253.07:40:50.69#ibcon#end of sib2, iclass 23, count 2 2006.253.07:40:50.69#ibcon#*mode == 0, iclass 23, count 2 2006.253.07:40:50.69#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.253.07:40:50.69#ibcon#[27=AT01-04\r\n] 2006.253.07:40:50.69#ibcon#*before write, iclass 23, count 2 2006.253.07:40:50.69#ibcon#enter sib2, iclass 23, count 2 2006.253.07:40:50.69#ibcon#flushed, iclass 23, count 2 2006.253.07:40:50.69#ibcon#about to write, iclass 23, count 2 2006.253.07:40:50.69#ibcon#wrote, iclass 23, count 2 2006.253.07:40:50.69#ibcon#about to read 3, iclass 23, count 2 2006.253.07:40:50.72#ibcon#read 3, iclass 23, count 2 2006.253.07:40:50.72#ibcon#about to read 4, iclass 23, count 2 2006.253.07:40:50.72#ibcon#read 4, iclass 23, count 2 2006.253.07:40:50.72#ibcon#about to read 5, iclass 23, count 2 2006.253.07:40:50.72#ibcon#read 5, iclass 23, count 2 2006.253.07:40:50.72#ibcon#about to read 6, iclass 23, count 2 2006.253.07:40:50.72#ibcon#read 6, iclass 23, count 2 2006.253.07:40:50.72#ibcon#end of sib2, iclass 23, count 2 2006.253.07:40:50.72#ibcon#*after write, iclass 23, count 2 2006.253.07:40:50.72#ibcon#*before return 0, iclass 23, count 2 2006.253.07:40:50.72#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.253.07:40:50.72#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.253.07:40:50.72#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.253.07:40:50.72#ibcon#ireg 7 cls_cnt 0 2006.253.07:40:50.72#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.253.07:40:50.84#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.253.07:40:50.84#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.253.07:40:50.84#ibcon#enter wrdev, iclass 23, count 0 2006.253.07:40:50.84#ibcon#first serial, iclass 23, count 0 2006.253.07:40:50.84#ibcon#enter sib2, iclass 23, count 0 2006.253.07:40:50.84#ibcon#flushed, iclass 23, count 0 2006.253.07:40:50.84#ibcon#about to write, iclass 23, count 0 2006.253.07:40:50.84#ibcon#wrote, iclass 23, count 0 2006.253.07:40:50.84#ibcon#about to read 3, iclass 23, count 0 2006.253.07:40:50.86#ibcon#read 3, iclass 23, count 0 2006.253.07:40:50.86#ibcon#about to read 4, iclass 23, count 0 2006.253.07:40:50.86#ibcon#read 4, iclass 23, count 0 2006.253.07:40:50.86#ibcon#about to read 5, iclass 23, count 0 2006.253.07:40:50.86#ibcon#read 5, iclass 23, count 0 2006.253.07:40:50.86#ibcon#about to read 6, iclass 23, count 0 2006.253.07:40:50.86#ibcon#read 6, iclass 23, count 0 2006.253.07:40:50.86#ibcon#end of sib2, iclass 23, count 0 2006.253.07:40:50.86#ibcon#*mode == 0, iclass 23, count 0 2006.253.07:40:50.86#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.253.07:40:50.86#ibcon#[27=USB\r\n] 2006.253.07:40:50.86#ibcon#*before write, iclass 23, count 0 2006.253.07:40:50.86#ibcon#enter sib2, iclass 23, count 0 2006.253.07:40:50.86#ibcon#flushed, iclass 23, count 0 2006.253.07:40:50.86#ibcon#about to write, iclass 23, count 0 2006.253.07:40:50.86#ibcon#wrote, iclass 23, count 0 2006.253.07:40:50.86#ibcon#about to read 3, iclass 23, count 0 2006.253.07:40:50.89#ibcon#read 3, iclass 23, count 0 2006.253.07:40:50.89#ibcon#about to read 4, iclass 23, count 0 2006.253.07:40:50.89#ibcon#read 4, iclass 23, count 0 2006.253.07:40:50.89#ibcon#about to read 5, iclass 23, count 0 2006.253.07:40:50.89#ibcon#read 5, iclass 23, count 0 2006.253.07:40:50.89#ibcon#about to read 6, iclass 23, count 0 2006.253.07:40:50.89#ibcon#read 6, iclass 23, count 0 2006.253.07:40:50.89#ibcon#end of sib2, iclass 23, count 0 2006.253.07:40:50.89#ibcon#*after write, iclass 23, count 0 2006.253.07:40:50.89#ibcon#*before return 0, iclass 23, count 0 2006.253.07:40:50.89#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.253.07:40:50.89#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.253.07:40:50.89#ibcon#about to clear, iclass 23 cls_cnt 0 2006.253.07:40:50.89#ibcon#cleared, iclass 23 cls_cnt 0 2006.253.07:40:50.89$vc4f8/vblo=2,640.99 2006.253.07:40:50.89#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.253.07:40:50.89#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.253.07:40:50.89#ibcon#ireg 17 cls_cnt 0 2006.253.07:40:50.89#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.253.07:40:50.89#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.253.07:40:50.89#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.253.07:40:50.89#ibcon#enter wrdev, iclass 25, count 0 2006.253.07:40:50.89#ibcon#first serial, iclass 25, count 0 2006.253.07:40:50.89#ibcon#enter sib2, iclass 25, count 0 2006.253.07:40:50.89#ibcon#flushed, iclass 25, count 0 2006.253.07:40:50.89#ibcon#about to write, iclass 25, count 0 2006.253.07:40:50.89#ibcon#wrote, iclass 25, count 0 2006.253.07:40:50.89#ibcon#about to read 3, iclass 25, count 0 2006.253.07:40:50.91#ibcon#read 3, iclass 25, count 0 2006.253.07:40:50.91#ibcon#about to read 4, iclass 25, count 0 2006.253.07:40:50.91#ibcon#read 4, iclass 25, count 0 2006.253.07:40:50.91#ibcon#about to read 5, iclass 25, count 0 2006.253.07:40:50.91#ibcon#read 5, iclass 25, count 0 2006.253.07:40:50.91#ibcon#about to read 6, iclass 25, count 0 2006.253.07:40:50.91#ibcon#read 6, iclass 25, count 0 2006.253.07:40:50.91#ibcon#end of sib2, iclass 25, count 0 2006.253.07:40:50.91#ibcon#*mode == 0, iclass 25, count 0 2006.253.07:40:50.91#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.253.07:40:50.91#ibcon#[28=FRQ=02,640.99\r\n] 2006.253.07:40:50.91#ibcon#*before write, iclass 25, count 0 2006.253.07:40:50.91#ibcon#enter sib2, iclass 25, count 0 2006.253.07:40:50.91#ibcon#flushed, iclass 25, count 0 2006.253.07:40:50.91#ibcon#about to write, iclass 25, count 0 2006.253.07:40:50.91#ibcon#wrote, iclass 25, count 0 2006.253.07:40:50.91#ibcon#about to read 3, iclass 25, count 0 2006.253.07:40:50.95#ibcon#read 3, iclass 25, count 0 2006.253.07:40:50.95#ibcon#about to read 4, iclass 25, count 0 2006.253.07:40:50.95#ibcon#read 4, iclass 25, count 0 2006.253.07:40:50.95#ibcon#about to read 5, iclass 25, count 0 2006.253.07:40:50.95#ibcon#read 5, iclass 25, count 0 2006.253.07:40:50.95#ibcon#about to read 6, iclass 25, count 0 2006.253.07:40:50.95#ibcon#read 6, iclass 25, count 0 2006.253.07:40:50.95#ibcon#end of sib2, iclass 25, count 0 2006.253.07:40:50.95#ibcon#*after write, iclass 25, count 0 2006.253.07:40:50.95#ibcon#*before return 0, iclass 25, count 0 2006.253.07:40:50.95#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.253.07:40:50.95#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.253.07:40:50.95#ibcon#about to clear, iclass 25 cls_cnt 0 2006.253.07:40:50.95#ibcon#cleared, iclass 25 cls_cnt 0 2006.253.07:40:50.95$vc4f8/vb=2,5 2006.253.07:40:50.95#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.253.07:40:50.95#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.253.07:40:50.95#ibcon#ireg 11 cls_cnt 2 2006.253.07:40:50.95#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.253.07:40:51.01#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.253.07:40:51.01#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.253.07:40:51.01#ibcon#enter wrdev, iclass 27, count 2 2006.253.07:40:51.01#ibcon#first serial, iclass 27, count 2 2006.253.07:40:51.01#ibcon#enter sib2, iclass 27, count 2 2006.253.07:40:51.01#ibcon#flushed, iclass 27, count 2 2006.253.07:40:51.01#ibcon#about to write, iclass 27, count 2 2006.253.07:40:51.01#ibcon#wrote, iclass 27, count 2 2006.253.07:40:51.01#ibcon#about to read 3, iclass 27, count 2 2006.253.07:40:51.03#ibcon#read 3, iclass 27, count 2 2006.253.07:40:51.03#ibcon#about to read 4, iclass 27, count 2 2006.253.07:40:51.03#ibcon#read 4, iclass 27, count 2 2006.253.07:40:51.03#ibcon#about to read 5, iclass 27, count 2 2006.253.07:40:51.03#ibcon#read 5, iclass 27, count 2 2006.253.07:40:51.03#ibcon#about to read 6, iclass 27, count 2 2006.253.07:40:51.03#ibcon#read 6, iclass 27, count 2 2006.253.07:40:51.03#ibcon#end of sib2, iclass 27, count 2 2006.253.07:40:51.03#ibcon#*mode == 0, iclass 27, count 2 2006.253.07:40:51.03#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.253.07:40:51.03#ibcon#[27=AT02-05\r\n] 2006.253.07:40:51.03#ibcon#*before write, iclass 27, count 2 2006.253.07:40:51.03#ibcon#enter sib2, iclass 27, count 2 2006.253.07:40:51.03#ibcon#flushed, iclass 27, count 2 2006.253.07:40:51.03#ibcon#about to write, iclass 27, count 2 2006.253.07:40:51.03#ibcon#wrote, iclass 27, count 2 2006.253.07:40:51.03#ibcon#about to read 3, iclass 27, count 2 2006.253.07:40:51.06#ibcon#read 3, iclass 27, count 2 2006.253.07:40:51.06#ibcon#about to read 4, iclass 27, count 2 2006.253.07:40:51.06#ibcon#read 4, iclass 27, count 2 2006.253.07:40:51.06#ibcon#about to read 5, iclass 27, count 2 2006.253.07:40:51.06#ibcon#read 5, iclass 27, count 2 2006.253.07:40:51.06#ibcon#about to read 6, iclass 27, count 2 2006.253.07:40:51.06#ibcon#read 6, iclass 27, count 2 2006.253.07:40:51.06#ibcon#end of sib2, iclass 27, count 2 2006.253.07:40:51.06#ibcon#*after write, iclass 27, count 2 2006.253.07:40:51.06#ibcon#*before return 0, iclass 27, count 2 2006.253.07:40:51.06#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.253.07:40:51.06#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.253.07:40:51.06#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.253.07:40:51.06#ibcon#ireg 7 cls_cnt 0 2006.253.07:40:51.06#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.253.07:40:51.18#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.253.07:40:51.18#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.253.07:40:51.18#ibcon#enter wrdev, iclass 27, count 0 2006.253.07:40:51.18#ibcon#first serial, iclass 27, count 0 2006.253.07:40:51.18#ibcon#enter sib2, iclass 27, count 0 2006.253.07:40:51.18#ibcon#flushed, iclass 27, count 0 2006.253.07:40:51.18#ibcon#about to write, iclass 27, count 0 2006.253.07:40:51.18#ibcon#wrote, iclass 27, count 0 2006.253.07:40:51.18#ibcon#about to read 3, iclass 27, count 0 2006.253.07:40:51.20#ibcon#read 3, iclass 27, count 0 2006.253.07:40:51.20#ibcon#about to read 4, iclass 27, count 0 2006.253.07:40:51.20#ibcon#read 4, iclass 27, count 0 2006.253.07:40:51.20#ibcon#about to read 5, iclass 27, count 0 2006.253.07:40:51.20#ibcon#read 5, iclass 27, count 0 2006.253.07:40:51.20#ibcon#about to read 6, iclass 27, count 0 2006.253.07:40:51.20#ibcon#read 6, iclass 27, count 0 2006.253.07:40:51.20#ibcon#end of sib2, iclass 27, count 0 2006.253.07:40:51.20#ibcon#*mode == 0, iclass 27, count 0 2006.253.07:40:51.20#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.253.07:40:51.20#ibcon#[27=USB\r\n] 2006.253.07:40:51.20#ibcon#*before write, iclass 27, count 0 2006.253.07:40:51.20#ibcon#enter sib2, iclass 27, count 0 2006.253.07:40:51.20#ibcon#flushed, iclass 27, count 0 2006.253.07:40:51.20#ibcon#about to write, iclass 27, count 0 2006.253.07:40:51.20#ibcon#wrote, iclass 27, count 0 2006.253.07:40:51.20#ibcon#about to read 3, iclass 27, count 0 2006.253.07:40:51.23#ibcon#read 3, iclass 27, count 0 2006.253.07:40:51.23#ibcon#about to read 4, iclass 27, count 0 2006.253.07:40:51.23#ibcon#read 4, iclass 27, count 0 2006.253.07:40:51.23#ibcon#about to read 5, iclass 27, count 0 2006.253.07:40:51.23#ibcon#read 5, iclass 27, count 0 2006.253.07:40:51.23#ibcon#about to read 6, iclass 27, count 0 2006.253.07:40:51.23#ibcon#read 6, iclass 27, count 0 2006.253.07:40:51.23#ibcon#end of sib2, iclass 27, count 0 2006.253.07:40:51.23#ibcon#*after write, iclass 27, count 0 2006.253.07:40:51.23#ibcon#*before return 0, iclass 27, count 0 2006.253.07:40:51.23#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.253.07:40:51.23#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.253.07:40:51.23#ibcon#about to clear, iclass 27 cls_cnt 0 2006.253.07:40:51.23#ibcon#cleared, iclass 27 cls_cnt 0 2006.253.07:40:51.23$vc4f8/vblo=3,656.99 2006.253.07:40:51.23#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.253.07:40:51.23#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.253.07:40:51.23#ibcon#ireg 17 cls_cnt 0 2006.253.07:40:51.23#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.253.07:40:51.23#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.253.07:40:51.23#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.253.07:40:51.23#ibcon#enter wrdev, iclass 29, count 0 2006.253.07:40:51.23#ibcon#first serial, iclass 29, count 0 2006.253.07:40:51.23#ibcon#enter sib2, iclass 29, count 0 2006.253.07:40:51.23#ibcon#flushed, iclass 29, count 0 2006.253.07:40:51.23#ibcon#about to write, iclass 29, count 0 2006.253.07:40:51.23#ibcon#wrote, iclass 29, count 0 2006.253.07:40:51.23#ibcon#about to read 3, iclass 29, count 0 2006.253.07:40:51.25#ibcon#read 3, iclass 29, count 0 2006.253.07:40:51.25#ibcon#about to read 4, iclass 29, count 0 2006.253.07:40:51.25#ibcon#read 4, iclass 29, count 0 2006.253.07:40:51.25#ibcon#about to read 5, iclass 29, count 0 2006.253.07:40:51.25#ibcon#read 5, iclass 29, count 0 2006.253.07:40:51.25#ibcon#about to read 6, iclass 29, count 0 2006.253.07:40:51.25#ibcon#read 6, iclass 29, count 0 2006.253.07:40:51.25#ibcon#end of sib2, iclass 29, count 0 2006.253.07:40:51.25#ibcon#*mode == 0, iclass 29, count 0 2006.253.07:40:51.25#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.253.07:40:51.25#ibcon#[28=FRQ=03,656.99\r\n] 2006.253.07:40:51.25#ibcon#*before write, iclass 29, count 0 2006.253.07:40:51.25#ibcon#enter sib2, iclass 29, count 0 2006.253.07:40:51.25#ibcon#flushed, iclass 29, count 0 2006.253.07:40:51.25#ibcon#about to write, iclass 29, count 0 2006.253.07:40:51.25#ibcon#wrote, iclass 29, count 0 2006.253.07:40:51.25#ibcon#about to read 3, iclass 29, count 0 2006.253.07:40:51.29#ibcon#read 3, iclass 29, count 0 2006.253.07:40:51.29#ibcon#about to read 4, iclass 29, count 0 2006.253.07:40:51.29#ibcon#read 4, iclass 29, count 0 2006.253.07:40:51.29#ibcon#about to read 5, iclass 29, count 0 2006.253.07:40:51.29#ibcon#read 5, iclass 29, count 0 2006.253.07:40:51.29#ibcon#about to read 6, iclass 29, count 0 2006.253.07:40:51.29#ibcon#read 6, iclass 29, count 0 2006.253.07:40:51.29#ibcon#end of sib2, iclass 29, count 0 2006.253.07:40:51.29#ibcon#*after write, iclass 29, count 0 2006.253.07:40:51.29#ibcon#*before return 0, iclass 29, count 0 2006.253.07:40:51.29#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.253.07:40:51.29#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.253.07:40:51.29#ibcon#about to clear, iclass 29 cls_cnt 0 2006.253.07:40:51.29#ibcon#cleared, iclass 29 cls_cnt 0 2006.253.07:40:51.29$vc4f8/vb=3,4 2006.253.07:40:51.29#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.253.07:40:51.29#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.253.07:40:51.29#ibcon#ireg 11 cls_cnt 2 2006.253.07:40:51.29#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.253.07:40:51.35#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.253.07:40:51.35#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.253.07:40:51.35#ibcon#enter wrdev, iclass 31, count 2 2006.253.07:40:51.35#ibcon#first serial, iclass 31, count 2 2006.253.07:40:51.35#ibcon#enter sib2, iclass 31, count 2 2006.253.07:40:51.35#ibcon#flushed, iclass 31, count 2 2006.253.07:40:51.35#ibcon#about to write, iclass 31, count 2 2006.253.07:40:51.35#ibcon#wrote, iclass 31, count 2 2006.253.07:40:51.35#ibcon#about to read 3, iclass 31, count 2 2006.253.07:40:51.37#ibcon#read 3, iclass 31, count 2 2006.253.07:40:51.37#ibcon#about to read 4, iclass 31, count 2 2006.253.07:40:51.37#ibcon#read 4, iclass 31, count 2 2006.253.07:40:51.37#ibcon#about to read 5, iclass 31, count 2 2006.253.07:40:51.37#ibcon#read 5, iclass 31, count 2 2006.253.07:40:51.37#ibcon#about to read 6, iclass 31, count 2 2006.253.07:40:51.37#ibcon#read 6, iclass 31, count 2 2006.253.07:40:51.37#ibcon#end of sib2, iclass 31, count 2 2006.253.07:40:51.37#ibcon#*mode == 0, iclass 31, count 2 2006.253.07:40:51.37#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.253.07:40:51.37#ibcon#[27=AT03-04\r\n] 2006.253.07:40:51.37#ibcon#*before write, iclass 31, count 2 2006.253.07:40:51.37#ibcon#enter sib2, iclass 31, count 2 2006.253.07:40:51.37#ibcon#flushed, iclass 31, count 2 2006.253.07:40:51.37#ibcon#about to write, iclass 31, count 2 2006.253.07:40:51.37#ibcon#wrote, iclass 31, count 2 2006.253.07:40:51.37#ibcon#about to read 3, iclass 31, count 2 2006.253.07:40:51.40#ibcon#read 3, iclass 31, count 2 2006.253.07:40:51.40#ibcon#about to read 4, iclass 31, count 2 2006.253.07:40:51.40#ibcon#read 4, iclass 31, count 2 2006.253.07:40:51.40#ibcon#about to read 5, iclass 31, count 2 2006.253.07:40:51.40#ibcon#read 5, iclass 31, count 2 2006.253.07:40:51.40#ibcon#about to read 6, iclass 31, count 2 2006.253.07:40:51.40#ibcon#read 6, iclass 31, count 2 2006.253.07:40:51.40#ibcon#end of sib2, iclass 31, count 2 2006.253.07:40:51.40#ibcon#*after write, iclass 31, count 2 2006.253.07:40:51.40#ibcon#*before return 0, iclass 31, count 2 2006.253.07:40:51.40#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.253.07:40:51.40#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.253.07:40:51.40#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.253.07:40:51.40#ibcon#ireg 7 cls_cnt 0 2006.253.07:40:51.40#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.253.07:40:51.52#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.253.07:40:51.52#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.253.07:40:51.52#ibcon#enter wrdev, iclass 31, count 0 2006.253.07:40:51.52#ibcon#first serial, iclass 31, count 0 2006.253.07:40:51.52#ibcon#enter sib2, iclass 31, count 0 2006.253.07:40:51.52#ibcon#flushed, iclass 31, count 0 2006.253.07:40:51.52#ibcon#about to write, iclass 31, count 0 2006.253.07:40:51.52#ibcon#wrote, iclass 31, count 0 2006.253.07:40:51.52#ibcon#about to read 3, iclass 31, count 0 2006.253.07:40:51.54#ibcon#read 3, iclass 31, count 0 2006.253.07:40:51.54#ibcon#about to read 4, iclass 31, count 0 2006.253.07:40:51.54#ibcon#read 4, iclass 31, count 0 2006.253.07:40:51.54#ibcon#about to read 5, iclass 31, count 0 2006.253.07:40:51.54#ibcon#read 5, iclass 31, count 0 2006.253.07:40:51.54#ibcon#about to read 6, iclass 31, count 0 2006.253.07:40:51.54#ibcon#read 6, iclass 31, count 0 2006.253.07:40:51.54#ibcon#end of sib2, iclass 31, count 0 2006.253.07:40:51.54#ibcon#*mode == 0, iclass 31, count 0 2006.253.07:40:51.54#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.253.07:40:51.54#ibcon#[27=USB\r\n] 2006.253.07:40:51.54#ibcon#*before write, iclass 31, count 0 2006.253.07:40:51.54#ibcon#enter sib2, iclass 31, count 0 2006.253.07:40:51.54#ibcon#flushed, iclass 31, count 0 2006.253.07:40:51.54#ibcon#about to write, iclass 31, count 0 2006.253.07:40:51.54#ibcon#wrote, iclass 31, count 0 2006.253.07:40:51.54#ibcon#about to read 3, iclass 31, count 0 2006.253.07:40:51.57#ibcon#read 3, iclass 31, count 0 2006.253.07:40:51.57#ibcon#about to read 4, iclass 31, count 0 2006.253.07:40:51.57#ibcon#read 4, iclass 31, count 0 2006.253.07:40:51.57#ibcon#about to read 5, iclass 31, count 0 2006.253.07:40:51.57#ibcon#read 5, iclass 31, count 0 2006.253.07:40:51.57#ibcon#about to read 6, iclass 31, count 0 2006.253.07:40:51.57#ibcon#read 6, iclass 31, count 0 2006.253.07:40:51.57#ibcon#end of sib2, iclass 31, count 0 2006.253.07:40:51.57#ibcon#*after write, iclass 31, count 0 2006.253.07:40:51.57#ibcon#*before return 0, iclass 31, count 0 2006.253.07:40:51.57#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.253.07:40:51.57#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.253.07:40:51.57#ibcon#about to clear, iclass 31 cls_cnt 0 2006.253.07:40:51.57#ibcon#cleared, iclass 31 cls_cnt 0 2006.253.07:40:51.57$vc4f8/vblo=4,712.99 2006.253.07:40:51.57#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.253.07:40:51.57#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.253.07:40:51.57#ibcon#ireg 17 cls_cnt 0 2006.253.07:40:51.57#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.253.07:40:51.57#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.253.07:40:51.57#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.253.07:40:51.57#ibcon#enter wrdev, iclass 33, count 0 2006.253.07:40:51.57#ibcon#first serial, iclass 33, count 0 2006.253.07:40:51.57#ibcon#enter sib2, iclass 33, count 0 2006.253.07:40:51.57#ibcon#flushed, iclass 33, count 0 2006.253.07:40:51.57#ibcon#about to write, iclass 33, count 0 2006.253.07:40:51.57#ibcon#wrote, iclass 33, count 0 2006.253.07:40:51.57#ibcon#about to read 3, iclass 33, count 0 2006.253.07:40:51.59#ibcon#read 3, iclass 33, count 0 2006.253.07:40:51.59#ibcon#about to read 4, iclass 33, count 0 2006.253.07:40:51.59#ibcon#read 4, iclass 33, count 0 2006.253.07:40:51.59#ibcon#about to read 5, iclass 33, count 0 2006.253.07:40:51.59#ibcon#read 5, iclass 33, count 0 2006.253.07:40:51.59#ibcon#about to read 6, iclass 33, count 0 2006.253.07:40:51.59#ibcon#read 6, iclass 33, count 0 2006.253.07:40:51.59#ibcon#end of sib2, iclass 33, count 0 2006.253.07:40:51.59#ibcon#*mode == 0, iclass 33, count 0 2006.253.07:40:51.59#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.253.07:40:51.59#ibcon#[28=FRQ=04,712.99\r\n] 2006.253.07:40:51.59#ibcon#*before write, iclass 33, count 0 2006.253.07:40:51.59#ibcon#enter sib2, iclass 33, count 0 2006.253.07:40:51.59#ibcon#flushed, iclass 33, count 0 2006.253.07:40:51.59#ibcon#about to write, iclass 33, count 0 2006.253.07:40:51.59#ibcon#wrote, iclass 33, count 0 2006.253.07:40:51.59#ibcon#about to read 3, iclass 33, count 0 2006.253.07:40:51.63#ibcon#read 3, iclass 33, count 0 2006.253.07:40:51.63#ibcon#about to read 4, iclass 33, count 0 2006.253.07:40:51.63#ibcon#read 4, iclass 33, count 0 2006.253.07:40:51.63#ibcon#about to read 5, iclass 33, count 0 2006.253.07:40:51.63#ibcon#read 5, iclass 33, count 0 2006.253.07:40:51.63#ibcon#about to read 6, iclass 33, count 0 2006.253.07:40:51.63#ibcon#read 6, iclass 33, count 0 2006.253.07:40:51.63#ibcon#end of sib2, iclass 33, count 0 2006.253.07:40:51.63#ibcon#*after write, iclass 33, count 0 2006.253.07:40:51.63#ibcon#*before return 0, iclass 33, count 0 2006.253.07:40:51.63#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.253.07:40:51.63#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.253.07:40:51.63#ibcon#about to clear, iclass 33 cls_cnt 0 2006.253.07:40:51.63#ibcon#cleared, iclass 33 cls_cnt 0 2006.253.07:40:51.63$vc4f8/vb=4,4 2006.253.07:40:51.63#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.253.07:40:51.63#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.253.07:40:51.63#ibcon#ireg 11 cls_cnt 2 2006.253.07:40:51.63#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.253.07:40:51.69#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.253.07:40:51.69#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.253.07:40:51.69#ibcon#enter wrdev, iclass 35, count 2 2006.253.07:40:51.69#ibcon#first serial, iclass 35, count 2 2006.253.07:40:51.69#ibcon#enter sib2, iclass 35, count 2 2006.253.07:40:51.69#ibcon#flushed, iclass 35, count 2 2006.253.07:40:51.69#ibcon#about to write, iclass 35, count 2 2006.253.07:40:51.69#ibcon#wrote, iclass 35, count 2 2006.253.07:40:51.69#ibcon#about to read 3, iclass 35, count 2 2006.253.07:40:51.71#ibcon#read 3, iclass 35, count 2 2006.253.07:40:51.71#ibcon#about to read 4, iclass 35, count 2 2006.253.07:40:51.71#ibcon#read 4, iclass 35, count 2 2006.253.07:40:51.71#ibcon#about to read 5, iclass 35, count 2 2006.253.07:40:51.71#ibcon#read 5, iclass 35, count 2 2006.253.07:40:51.71#ibcon#about to read 6, iclass 35, count 2 2006.253.07:40:51.71#ibcon#read 6, iclass 35, count 2 2006.253.07:40:51.71#ibcon#end of sib2, iclass 35, count 2 2006.253.07:40:51.71#ibcon#*mode == 0, iclass 35, count 2 2006.253.07:40:51.71#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.253.07:40:51.71#ibcon#[27=AT04-04\r\n] 2006.253.07:40:51.71#ibcon#*before write, iclass 35, count 2 2006.253.07:40:51.71#ibcon#enter sib2, iclass 35, count 2 2006.253.07:40:51.71#ibcon#flushed, iclass 35, count 2 2006.253.07:40:51.71#ibcon#about to write, iclass 35, count 2 2006.253.07:40:51.71#ibcon#wrote, iclass 35, count 2 2006.253.07:40:51.71#ibcon#about to read 3, iclass 35, count 2 2006.253.07:40:51.74#ibcon#read 3, iclass 35, count 2 2006.253.07:40:51.74#ibcon#about to read 4, iclass 35, count 2 2006.253.07:40:51.74#ibcon#read 4, iclass 35, count 2 2006.253.07:40:51.74#ibcon#about to read 5, iclass 35, count 2 2006.253.07:40:51.74#ibcon#read 5, iclass 35, count 2 2006.253.07:40:51.74#ibcon#about to read 6, iclass 35, count 2 2006.253.07:40:51.74#ibcon#read 6, iclass 35, count 2 2006.253.07:40:51.74#ibcon#end of sib2, iclass 35, count 2 2006.253.07:40:51.74#ibcon#*after write, iclass 35, count 2 2006.253.07:40:51.74#ibcon#*before return 0, iclass 35, count 2 2006.253.07:40:51.74#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.253.07:40:51.74#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.253.07:40:51.74#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.253.07:40:51.74#ibcon#ireg 7 cls_cnt 0 2006.253.07:40:51.74#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.253.07:40:51.86#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.253.07:40:51.86#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.253.07:40:51.86#ibcon#enter wrdev, iclass 35, count 0 2006.253.07:40:51.86#ibcon#first serial, iclass 35, count 0 2006.253.07:40:51.86#ibcon#enter sib2, iclass 35, count 0 2006.253.07:40:51.86#ibcon#flushed, iclass 35, count 0 2006.253.07:40:51.86#ibcon#about to write, iclass 35, count 0 2006.253.07:40:51.86#ibcon#wrote, iclass 35, count 0 2006.253.07:40:51.86#ibcon#about to read 3, iclass 35, count 0 2006.253.07:40:51.88#ibcon#read 3, iclass 35, count 0 2006.253.07:40:51.88#ibcon#about to read 4, iclass 35, count 0 2006.253.07:40:51.88#ibcon#read 4, iclass 35, count 0 2006.253.07:40:51.88#ibcon#about to read 5, iclass 35, count 0 2006.253.07:40:51.88#ibcon#read 5, iclass 35, count 0 2006.253.07:40:51.88#ibcon#about to read 6, iclass 35, count 0 2006.253.07:40:51.88#ibcon#read 6, iclass 35, count 0 2006.253.07:40:51.88#ibcon#end of sib2, iclass 35, count 0 2006.253.07:40:51.88#ibcon#*mode == 0, iclass 35, count 0 2006.253.07:40:51.88#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.253.07:40:51.88#ibcon#[27=USB\r\n] 2006.253.07:40:51.88#ibcon#*before write, iclass 35, count 0 2006.253.07:40:51.88#ibcon#enter sib2, iclass 35, count 0 2006.253.07:40:51.88#ibcon#flushed, iclass 35, count 0 2006.253.07:40:51.88#ibcon#about to write, iclass 35, count 0 2006.253.07:40:51.88#ibcon#wrote, iclass 35, count 0 2006.253.07:40:51.88#ibcon#about to read 3, iclass 35, count 0 2006.253.07:40:51.91#ibcon#read 3, iclass 35, count 0 2006.253.07:40:51.91#ibcon#about to read 4, iclass 35, count 0 2006.253.07:40:51.91#ibcon#read 4, iclass 35, count 0 2006.253.07:40:51.91#ibcon#about to read 5, iclass 35, count 0 2006.253.07:40:51.91#ibcon#read 5, iclass 35, count 0 2006.253.07:40:51.91#ibcon#about to read 6, iclass 35, count 0 2006.253.07:40:51.91#ibcon#read 6, iclass 35, count 0 2006.253.07:40:51.91#ibcon#end of sib2, iclass 35, count 0 2006.253.07:40:51.91#ibcon#*after write, iclass 35, count 0 2006.253.07:40:51.91#ibcon#*before return 0, iclass 35, count 0 2006.253.07:40:51.91#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.253.07:40:51.91#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.253.07:40:51.91#ibcon#about to clear, iclass 35 cls_cnt 0 2006.253.07:40:51.91#ibcon#cleared, iclass 35 cls_cnt 0 2006.253.07:40:51.91$vc4f8/vblo=5,744.99 2006.253.07:40:51.91#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.253.07:40:51.91#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.253.07:40:51.91#ibcon#ireg 17 cls_cnt 0 2006.253.07:40:51.91#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.253.07:40:51.91#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.253.07:40:51.91#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.253.07:40:51.91#ibcon#enter wrdev, iclass 37, count 0 2006.253.07:40:51.91#ibcon#first serial, iclass 37, count 0 2006.253.07:40:51.91#ibcon#enter sib2, iclass 37, count 0 2006.253.07:40:51.91#ibcon#flushed, iclass 37, count 0 2006.253.07:40:51.91#ibcon#about to write, iclass 37, count 0 2006.253.07:40:51.91#ibcon#wrote, iclass 37, count 0 2006.253.07:40:51.91#ibcon#about to read 3, iclass 37, count 0 2006.253.07:40:51.93#ibcon#read 3, iclass 37, count 0 2006.253.07:40:51.93#ibcon#about to read 4, iclass 37, count 0 2006.253.07:40:51.93#ibcon#read 4, iclass 37, count 0 2006.253.07:40:51.93#ibcon#about to read 5, iclass 37, count 0 2006.253.07:40:51.93#ibcon#read 5, iclass 37, count 0 2006.253.07:40:51.93#ibcon#about to read 6, iclass 37, count 0 2006.253.07:40:51.93#ibcon#read 6, iclass 37, count 0 2006.253.07:40:51.93#ibcon#end of sib2, iclass 37, count 0 2006.253.07:40:51.93#ibcon#*mode == 0, iclass 37, count 0 2006.253.07:40:51.93#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.253.07:40:51.93#ibcon#[28=FRQ=05,744.99\r\n] 2006.253.07:40:51.93#ibcon#*before write, iclass 37, count 0 2006.253.07:40:51.93#ibcon#enter sib2, iclass 37, count 0 2006.253.07:40:51.93#ibcon#flushed, iclass 37, count 0 2006.253.07:40:51.93#ibcon#about to write, iclass 37, count 0 2006.253.07:40:51.93#ibcon#wrote, iclass 37, count 0 2006.253.07:40:51.93#ibcon#about to read 3, iclass 37, count 0 2006.253.07:40:51.98#ibcon#read 3, iclass 37, count 0 2006.253.07:40:51.98#ibcon#about to read 4, iclass 37, count 0 2006.253.07:40:51.98#ibcon#read 4, iclass 37, count 0 2006.253.07:40:51.98#ibcon#about to read 5, iclass 37, count 0 2006.253.07:40:51.98#ibcon#read 5, iclass 37, count 0 2006.253.07:40:51.98#ibcon#about to read 6, iclass 37, count 0 2006.253.07:40:51.98#ibcon#read 6, iclass 37, count 0 2006.253.07:40:51.98#ibcon#end of sib2, iclass 37, count 0 2006.253.07:40:51.98#ibcon#*after write, iclass 37, count 0 2006.253.07:40:51.98#ibcon#*before return 0, iclass 37, count 0 2006.253.07:40:51.98#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.253.07:40:51.98#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.253.07:40:51.98#ibcon#about to clear, iclass 37 cls_cnt 0 2006.253.07:40:51.98#ibcon#cleared, iclass 37 cls_cnt 0 2006.253.07:40:51.98$vc4f8/vb=5,4 2006.253.07:40:51.98#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.253.07:40:51.98#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.253.07:40:51.98#ibcon#ireg 11 cls_cnt 2 2006.253.07:40:51.98#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.253.07:40:52.03#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.253.07:40:52.03#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.253.07:40:52.03#ibcon#enter wrdev, iclass 39, count 2 2006.253.07:40:52.03#ibcon#first serial, iclass 39, count 2 2006.253.07:40:52.03#ibcon#enter sib2, iclass 39, count 2 2006.253.07:40:52.03#ibcon#flushed, iclass 39, count 2 2006.253.07:40:52.03#ibcon#about to write, iclass 39, count 2 2006.253.07:40:52.03#ibcon#wrote, iclass 39, count 2 2006.253.07:40:52.03#ibcon#about to read 3, iclass 39, count 2 2006.253.07:40:52.05#ibcon#read 3, iclass 39, count 2 2006.253.07:40:52.05#ibcon#about to read 4, iclass 39, count 2 2006.253.07:40:52.05#ibcon#read 4, iclass 39, count 2 2006.253.07:40:52.05#ibcon#about to read 5, iclass 39, count 2 2006.253.07:40:52.05#ibcon#read 5, iclass 39, count 2 2006.253.07:40:52.05#ibcon#about to read 6, iclass 39, count 2 2006.253.07:40:52.05#ibcon#read 6, iclass 39, count 2 2006.253.07:40:52.05#ibcon#end of sib2, iclass 39, count 2 2006.253.07:40:52.05#ibcon#*mode == 0, iclass 39, count 2 2006.253.07:40:52.05#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.253.07:40:52.05#ibcon#[27=AT05-04\r\n] 2006.253.07:40:52.05#ibcon#*before write, iclass 39, count 2 2006.253.07:40:52.05#ibcon#enter sib2, iclass 39, count 2 2006.253.07:40:52.05#ibcon#flushed, iclass 39, count 2 2006.253.07:40:52.05#ibcon#about to write, iclass 39, count 2 2006.253.07:40:52.05#ibcon#wrote, iclass 39, count 2 2006.253.07:40:52.05#ibcon#about to read 3, iclass 39, count 2 2006.253.07:40:52.08#ibcon#read 3, iclass 39, count 2 2006.253.07:40:52.08#ibcon#about to read 4, iclass 39, count 2 2006.253.07:40:52.08#ibcon#read 4, iclass 39, count 2 2006.253.07:40:52.08#ibcon#about to read 5, iclass 39, count 2 2006.253.07:40:52.08#ibcon#read 5, iclass 39, count 2 2006.253.07:40:52.08#ibcon#about to read 6, iclass 39, count 2 2006.253.07:40:52.08#ibcon#read 6, iclass 39, count 2 2006.253.07:40:52.08#ibcon#end of sib2, iclass 39, count 2 2006.253.07:40:52.08#ibcon#*after write, iclass 39, count 2 2006.253.07:40:52.08#ibcon#*before return 0, iclass 39, count 2 2006.253.07:40:52.08#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.253.07:40:52.08#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.253.07:40:52.08#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.253.07:40:52.08#ibcon#ireg 7 cls_cnt 0 2006.253.07:40:52.08#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.253.07:40:52.20#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.253.07:40:52.20#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.253.07:40:52.20#ibcon#enter wrdev, iclass 39, count 0 2006.253.07:40:52.20#ibcon#first serial, iclass 39, count 0 2006.253.07:40:52.20#ibcon#enter sib2, iclass 39, count 0 2006.253.07:40:52.20#ibcon#flushed, iclass 39, count 0 2006.253.07:40:52.20#ibcon#about to write, iclass 39, count 0 2006.253.07:40:52.20#ibcon#wrote, iclass 39, count 0 2006.253.07:40:52.20#ibcon#about to read 3, iclass 39, count 0 2006.253.07:40:52.22#ibcon#read 3, iclass 39, count 0 2006.253.07:40:52.22#ibcon#about to read 4, iclass 39, count 0 2006.253.07:40:52.22#ibcon#read 4, iclass 39, count 0 2006.253.07:40:52.22#ibcon#about to read 5, iclass 39, count 0 2006.253.07:40:52.22#ibcon#read 5, iclass 39, count 0 2006.253.07:40:52.22#ibcon#about to read 6, iclass 39, count 0 2006.253.07:40:52.22#ibcon#read 6, iclass 39, count 0 2006.253.07:40:52.22#ibcon#end of sib2, iclass 39, count 0 2006.253.07:40:52.22#ibcon#*mode == 0, iclass 39, count 0 2006.253.07:40:52.22#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.253.07:40:52.22#ibcon#[27=USB\r\n] 2006.253.07:40:52.22#ibcon#*before write, iclass 39, count 0 2006.253.07:40:52.22#ibcon#enter sib2, iclass 39, count 0 2006.253.07:40:52.22#ibcon#flushed, iclass 39, count 0 2006.253.07:40:52.22#ibcon#about to write, iclass 39, count 0 2006.253.07:40:52.22#ibcon#wrote, iclass 39, count 0 2006.253.07:40:52.22#ibcon#about to read 3, iclass 39, count 0 2006.253.07:40:52.25#ibcon#read 3, iclass 39, count 0 2006.253.07:40:52.25#ibcon#about to read 4, iclass 39, count 0 2006.253.07:40:52.25#ibcon#read 4, iclass 39, count 0 2006.253.07:40:52.25#ibcon#about to read 5, iclass 39, count 0 2006.253.07:40:52.25#ibcon#read 5, iclass 39, count 0 2006.253.07:40:52.25#ibcon#about to read 6, iclass 39, count 0 2006.253.07:40:52.25#ibcon#read 6, iclass 39, count 0 2006.253.07:40:52.25#ibcon#end of sib2, iclass 39, count 0 2006.253.07:40:52.25#ibcon#*after write, iclass 39, count 0 2006.253.07:40:52.25#ibcon#*before return 0, iclass 39, count 0 2006.253.07:40:52.25#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.253.07:40:52.25#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.253.07:40:52.25#ibcon#about to clear, iclass 39 cls_cnt 0 2006.253.07:40:52.25#ibcon#cleared, iclass 39 cls_cnt 0 2006.253.07:40:52.25$vc4f8/vblo=6,752.99 2006.253.07:40:52.25#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.253.07:40:52.25#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.253.07:40:52.25#ibcon#ireg 17 cls_cnt 0 2006.253.07:40:52.25#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.253.07:40:52.25#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.253.07:40:52.25#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.253.07:40:52.25#ibcon#enter wrdev, iclass 3, count 0 2006.253.07:40:52.25#ibcon#first serial, iclass 3, count 0 2006.253.07:40:52.25#ibcon#enter sib2, iclass 3, count 0 2006.253.07:40:52.25#ibcon#flushed, iclass 3, count 0 2006.253.07:40:52.25#ibcon#about to write, iclass 3, count 0 2006.253.07:40:52.25#ibcon#wrote, iclass 3, count 0 2006.253.07:40:52.25#ibcon#about to read 3, iclass 3, count 0 2006.253.07:40:52.27#ibcon#read 3, iclass 3, count 0 2006.253.07:40:52.27#ibcon#about to read 4, iclass 3, count 0 2006.253.07:40:52.27#ibcon#read 4, iclass 3, count 0 2006.253.07:40:52.27#ibcon#about to read 5, iclass 3, count 0 2006.253.07:40:52.27#ibcon#read 5, iclass 3, count 0 2006.253.07:40:52.27#ibcon#about to read 6, iclass 3, count 0 2006.253.07:40:52.27#ibcon#read 6, iclass 3, count 0 2006.253.07:40:52.27#ibcon#end of sib2, iclass 3, count 0 2006.253.07:40:52.27#ibcon#*mode == 0, iclass 3, count 0 2006.253.07:40:52.27#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.253.07:40:52.27#ibcon#[28=FRQ=06,752.99\r\n] 2006.253.07:40:52.27#ibcon#*before write, iclass 3, count 0 2006.253.07:40:52.27#ibcon#enter sib2, iclass 3, count 0 2006.253.07:40:52.27#ibcon#flushed, iclass 3, count 0 2006.253.07:40:52.27#ibcon#about to write, iclass 3, count 0 2006.253.07:40:52.27#ibcon#wrote, iclass 3, count 0 2006.253.07:40:52.27#ibcon#about to read 3, iclass 3, count 0 2006.253.07:40:52.31#ibcon#read 3, iclass 3, count 0 2006.253.07:40:52.31#ibcon#about to read 4, iclass 3, count 0 2006.253.07:40:52.31#ibcon#read 4, iclass 3, count 0 2006.253.07:40:52.31#ibcon#about to read 5, iclass 3, count 0 2006.253.07:40:52.31#ibcon#read 5, iclass 3, count 0 2006.253.07:40:52.31#ibcon#about to read 6, iclass 3, count 0 2006.253.07:40:52.31#ibcon#read 6, iclass 3, count 0 2006.253.07:40:52.31#ibcon#end of sib2, iclass 3, count 0 2006.253.07:40:52.31#ibcon#*after write, iclass 3, count 0 2006.253.07:40:52.31#ibcon#*before return 0, iclass 3, count 0 2006.253.07:40:52.31#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.253.07:40:52.31#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.253.07:40:52.31#ibcon#about to clear, iclass 3 cls_cnt 0 2006.253.07:40:52.31#ibcon#cleared, iclass 3 cls_cnt 0 2006.253.07:40:52.31$vc4f8/vb=6,4 2006.253.07:40:52.31#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.253.07:40:52.31#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.253.07:40:52.31#ibcon#ireg 11 cls_cnt 2 2006.253.07:40:52.31#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.253.07:40:52.37#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.253.07:40:52.37#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.253.07:40:52.37#ibcon#enter wrdev, iclass 5, count 2 2006.253.07:40:52.37#ibcon#first serial, iclass 5, count 2 2006.253.07:40:52.37#ibcon#enter sib2, iclass 5, count 2 2006.253.07:40:52.37#ibcon#flushed, iclass 5, count 2 2006.253.07:40:52.37#ibcon#about to write, iclass 5, count 2 2006.253.07:40:52.37#ibcon#wrote, iclass 5, count 2 2006.253.07:40:52.37#ibcon#about to read 3, iclass 5, count 2 2006.253.07:40:52.39#ibcon#read 3, iclass 5, count 2 2006.253.07:40:52.39#ibcon#about to read 4, iclass 5, count 2 2006.253.07:40:52.39#ibcon#read 4, iclass 5, count 2 2006.253.07:40:52.39#ibcon#about to read 5, iclass 5, count 2 2006.253.07:40:52.39#ibcon#read 5, iclass 5, count 2 2006.253.07:40:52.39#ibcon#about to read 6, iclass 5, count 2 2006.253.07:40:52.39#ibcon#read 6, iclass 5, count 2 2006.253.07:40:52.39#ibcon#end of sib2, iclass 5, count 2 2006.253.07:40:52.39#ibcon#*mode == 0, iclass 5, count 2 2006.253.07:40:52.39#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.253.07:40:52.39#ibcon#[27=AT06-04\r\n] 2006.253.07:40:52.39#ibcon#*before write, iclass 5, count 2 2006.253.07:40:52.39#ibcon#enter sib2, iclass 5, count 2 2006.253.07:40:52.39#ibcon#flushed, iclass 5, count 2 2006.253.07:40:52.39#ibcon#about to write, iclass 5, count 2 2006.253.07:40:52.39#ibcon#wrote, iclass 5, count 2 2006.253.07:40:52.39#ibcon#about to read 3, iclass 5, count 2 2006.253.07:40:52.42#ibcon#read 3, iclass 5, count 2 2006.253.07:40:52.42#ibcon#about to read 4, iclass 5, count 2 2006.253.07:40:52.42#ibcon#read 4, iclass 5, count 2 2006.253.07:40:52.42#ibcon#about to read 5, iclass 5, count 2 2006.253.07:40:52.42#ibcon#read 5, iclass 5, count 2 2006.253.07:40:52.42#ibcon#about to read 6, iclass 5, count 2 2006.253.07:40:52.42#ibcon#read 6, iclass 5, count 2 2006.253.07:40:52.42#ibcon#end of sib2, iclass 5, count 2 2006.253.07:40:52.42#ibcon#*after write, iclass 5, count 2 2006.253.07:40:52.42#ibcon#*before return 0, iclass 5, count 2 2006.253.07:40:52.42#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.253.07:40:52.42#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.253.07:40:52.42#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.253.07:40:52.42#ibcon#ireg 7 cls_cnt 0 2006.253.07:40:52.42#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.253.07:40:52.54#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.253.07:40:52.54#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.253.07:40:52.54#ibcon#enter wrdev, iclass 5, count 0 2006.253.07:40:52.54#ibcon#first serial, iclass 5, count 0 2006.253.07:40:52.54#ibcon#enter sib2, iclass 5, count 0 2006.253.07:40:52.54#ibcon#flushed, iclass 5, count 0 2006.253.07:40:52.54#ibcon#about to write, iclass 5, count 0 2006.253.07:40:52.54#ibcon#wrote, iclass 5, count 0 2006.253.07:40:52.54#ibcon#about to read 3, iclass 5, count 0 2006.253.07:40:52.56#ibcon#read 3, iclass 5, count 0 2006.253.07:40:52.56#ibcon#about to read 4, iclass 5, count 0 2006.253.07:40:52.56#ibcon#read 4, iclass 5, count 0 2006.253.07:40:52.56#ibcon#about to read 5, iclass 5, count 0 2006.253.07:40:52.56#ibcon#read 5, iclass 5, count 0 2006.253.07:40:52.56#ibcon#about to read 6, iclass 5, count 0 2006.253.07:40:52.56#ibcon#read 6, iclass 5, count 0 2006.253.07:40:52.56#ibcon#end of sib2, iclass 5, count 0 2006.253.07:40:52.56#ibcon#*mode == 0, iclass 5, count 0 2006.253.07:40:52.56#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.253.07:40:52.56#ibcon#[27=USB\r\n] 2006.253.07:40:52.56#ibcon#*before write, iclass 5, count 0 2006.253.07:40:52.56#ibcon#enter sib2, iclass 5, count 0 2006.253.07:40:52.56#ibcon#flushed, iclass 5, count 0 2006.253.07:40:52.56#ibcon#about to write, iclass 5, count 0 2006.253.07:40:52.56#ibcon#wrote, iclass 5, count 0 2006.253.07:40:52.56#ibcon#about to read 3, iclass 5, count 0 2006.253.07:40:52.59#ibcon#read 3, iclass 5, count 0 2006.253.07:40:52.59#ibcon#about to read 4, iclass 5, count 0 2006.253.07:40:52.59#ibcon#read 4, iclass 5, count 0 2006.253.07:40:52.59#ibcon#about to read 5, iclass 5, count 0 2006.253.07:40:52.59#ibcon#read 5, iclass 5, count 0 2006.253.07:40:52.59#ibcon#about to read 6, iclass 5, count 0 2006.253.07:40:52.59#ibcon#read 6, iclass 5, count 0 2006.253.07:40:52.59#ibcon#end of sib2, iclass 5, count 0 2006.253.07:40:52.59#ibcon#*after write, iclass 5, count 0 2006.253.07:40:52.59#ibcon#*before return 0, iclass 5, count 0 2006.253.07:40:52.59#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.253.07:40:52.59#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.253.07:40:52.59#ibcon#about to clear, iclass 5 cls_cnt 0 2006.253.07:40:52.59#ibcon#cleared, iclass 5 cls_cnt 0 2006.253.07:40:52.59$vc4f8/vabw=wide 2006.253.07:40:52.59#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.253.07:40:52.59#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.253.07:40:52.59#ibcon#ireg 8 cls_cnt 0 2006.253.07:40:52.59#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.253.07:40:52.59#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.253.07:40:52.59#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.253.07:40:52.59#ibcon#enter wrdev, iclass 7, count 0 2006.253.07:40:52.59#ibcon#first serial, iclass 7, count 0 2006.253.07:40:52.59#ibcon#enter sib2, iclass 7, count 0 2006.253.07:40:52.59#ibcon#flushed, iclass 7, count 0 2006.253.07:40:52.59#ibcon#about to write, iclass 7, count 0 2006.253.07:40:52.59#ibcon#wrote, iclass 7, count 0 2006.253.07:40:52.59#ibcon#about to read 3, iclass 7, count 0 2006.253.07:40:52.61#ibcon#read 3, iclass 7, count 0 2006.253.07:40:52.61#ibcon#about to read 4, iclass 7, count 0 2006.253.07:40:52.61#ibcon#read 4, iclass 7, count 0 2006.253.07:40:52.61#ibcon#about to read 5, iclass 7, count 0 2006.253.07:40:52.61#ibcon#read 5, iclass 7, count 0 2006.253.07:40:52.61#ibcon#about to read 6, iclass 7, count 0 2006.253.07:40:52.61#ibcon#read 6, iclass 7, count 0 2006.253.07:40:52.61#ibcon#end of sib2, iclass 7, count 0 2006.253.07:40:52.61#ibcon#*mode == 0, iclass 7, count 0 2006.253.07:40:52.61#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.253.07:40:52.61#ibcon#[25=BW32\r\n] 2006.253.07:40:52.61#ibcon#*before write, iclass 7, count 0 2006.253.07:40:52.61#ibcon#enter sib2, iclass 7, count 0 2006.253.07:40:52.61#ibcon#flushed, iclass 7, count 0 2006.253.07:40:52.61#ibcon#about to write, iclass 7, count 0 2006.253.07:40:52.61#ibcon#wrote, iclass 7, count 0 2006.253.07:40:52.61#ibcon#about to read 3, iclass 7, count 0 2006.253.07:40:52.65#ibcon#read 3, iclass 7, count 0 2006.253.07:40:52.65#ibcon#about to read 4, iclass 7, count 0 2006.253.07:40:52.65#ibcon#read 4, iclass 7, count 0 2006.253.07:40:52.65#ibcon#about to read 5, iclass 7, count 0 2006.253.07:40:52.65#ibcon#read 5, iclass 7, count 0 2006.253.07:40:52.65#ibcon#about to read 6, iclass 7, count 0 2006.253.07:40:52.65#ibcon#read 6, iclass 7, count 0 2006.253.07:40:52.65#ibcon#end of sib2, iclass 7, count 0 2006.253.07:40:52.65#ibcon#*after write, iclass 7, count 0 2006.253.07:40:52.65#ibcon#*before return 0, iclass 7, count 0 2006.253.07:40:52.65#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.253.07:40:52.65#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.253.07:40:52.65#ibcon#about to clear, iclass 7 cls_cnt 0 2006.253.07:40:52.65#ibcon#cleared, iclass 7 cls_cnt 0 2006.253.07:40:52.65$vc4f8/vbbw=wide 2006.253.07:40:52.65#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.253.07:40:52.65#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.253.07:40:52.65#ibcon#ireg 8 cls_cnt 0 2006.253.07:40:52.65#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.253.07:40:52.71#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.253.07:40:52.71#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.253.07:40:52.71#ibcon#enter wrdev, iclass 11, count 0 2006.253.07:40:52.71#ibcon#first serial, iclass 11, count 0 2006.253.07:40:52.71#ibcon#enter sib2, iclass 11, count 0 2006.253.07:40:52.71#ibcon#flushed, iclass 11, count 0 2006.253.07:40:52.71#ibcon#about to write, iclass 11, count 0 2006.253.07:40:52.71#ibcon#wrote, iclass 11, count 0 2006.253.07:40:52.71#ibcon#about to read 3, iclass 11, count 0 2006.253.07:40:52.73#ibcon#read 3, iclass 11, count 0 2006.253.07:40:52.73#ibcon#about to read 4, iclass 11, count 0 2006.253.07:40:52.73#ibcon#read 4, iclass 11, count 0 2006.253.07:40:52.73#ibcon#about to read 5, iclass 11, count 0 2006.253.07:40:52.73#ibcon#read 5, iclass 11, count 0 2006.253.07:40:52.73#ibcon#about to read 6, iclass 11, count 0 2006.253.07:40:52.73#ibcon#read 6, iclass 11, count 0 2006.253.07:40:52.73#ibcon#end of sib2, iclass 11, count 0 2006.253.07:40:52.73#ibcon#*mode == 0, iclass 11, count 0 2006.253.07:40:52.73#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.253.07:40:52.73#ibcon#[27=BW32\r\n] 2006.253.07:40:52.73#ibcon#*before write, iclass 11, count 0 2006.253.07:40:52.73#ibcon#enter sib2, iclass 11, count 0 2006.253.07:40:52.73#ibcon#flushed, iclass 11, count 0 2006.253.07:40:52.73#ibcon#about to write, iclass 11, count 0 2006.253.07:40:52.73#ibcon#wrote, iclass 11, count 0 2006.253.07:40:52.73#ibcon#about to read 3, iclass 11, count 0 2006.253.07:40:52.76#ibcon#read 3, iclass 11, count 0 2006.253.07:40:52.76#ibcon#about to read 4, iclass 11, count 0 2006.253.07:40:52.76#ibcon#read 4, iclass 11, count 0 2006.253.07:40:52.76#ibcon#about to read 5, iclass 11, count 0 2006.253.07:40:52.76#ibcon#read 5, iclass 11, count 0 2006.253.07:40:52.76#ibcon#about to read 6, iclass 11, count 0 2006.253.07:40:52.76#ibcon#read 6, iclass 11, count 0 2006.253.07:40:52.76#ibcon#end of sib2, iclass 11, count 0 2006.253.07:40:52.76#ibcon#*after write, iclass 11, count 0 2006.253.07:40:52.76#ibcon#*before return 0, iclass 11, count 0 2006.253.07:40:52.76#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.253.07:40:52.76#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.253.07:40:52.76#ibcon#about to clear, iclass 11 cls_cnt 0 2006.253.07:40:52.76#ibcon#cleared, iclass 11 cls_cnt 0 2006.253.07:40:52.76$4f8m12a/ifd4f 2006.253.07:40:52.76$ifd4f/lo= 2006.253.07:40:52.76$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.253.07:40:52.76$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.253.07:40:52.76$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.253.07:40:52.76$ifd4f/patch= 2006.253.07:40:52.76$ifd4f/patch=lo1,a1,a2,a3,a4 2006.253.07:40:52.76$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.253.07:40:52.76$ifd4f/patch=lo3,a5,a6,a7,a8 2006.253.07:40:52.76$4f8m12a/"form=m,16.000,1:2 2006.253.07:40:52.76$4f8m12a/"tpicd 2006.253.07:40:52.76$4f8m12a/echo=off 2006.253.07:40:52.76$4f8m12a/xlog=off 2006.253.07:40:52.76:!2006.253.07:41:20 2006.253.07:41:03.14#trakl#Source acquired 2006.253.07:41:05.14#flagr#flagr/antenna,acquired 2006.253.07:41:20.00:preob 2006.253.07:41:21.14/onsource/TRACKING 2006.253.07:41:21.14:!2006.253.07:41:30 2006.253.07:41:30.00:data_valid=on 2006.253.07:41:30.00:midob 2006.253.07:41:30.14/onsource/TRACKING 2006.253.07:41:30.14/wx/31.46,1006.3,72 2006.253.07:41:30.29/cable/+6.3701E-03 2006.253.07:41:31.38/va/01,08,usb,yes,31,32 2006.253.07:41:31.38/va/02,07,usb,yes,31,32 2006.253.07:41:31.38/va/03,06,usb,yes,33,33 2006.253.07:41:31.38/va/04,07,usb,yes,32,35 2006.253.07:41:31.38/va/05,07,usb,yes,33,35 2006.253.07:41:31.38/va/06,07,usb,yes,29,29 2006.253.07:41:31.38/va/07,07,usb,yes,29,29 2006.253.07:41:31.38/va/08,07,usb,yes,31,31 2006.253.07:41:31.61/valo/01,532.99,yes,locked 2006.253.07:41:31.61/valo/02,572.99,yes,locked 2006.253.07:41:31.61/valo/03,672.99,yes,locked 2006.253.07:41:31.61/valo/04,832.99,yes,locked 2006.253.07:41:31.61/valo/05,652.99,yes,locked 2006.253.07:41:31.61/valo/06,772.99,yes,locked 2006.253.07:41:31.61/valo/07,832.99,yes,locked 2006.253.07:41:31.61/valo/08,852.99,yes,locked 2006.253.07:41:32.70/vb/01,04,usb,yes,30,29 2006.253.07:41:32.70/vb/02,05,usb,yes,28,29 2006.253.07:41:32.70/vb/03,04,usb,yes,28,32 2006.253.07:41:32.70/vb/04,04,usb,yes,29,29 2006.253.07:41:32.70/vb/05,04,usb,yes,27,32 2006.253.07:41:32.70/vb/06,04,usb,yes,28,31 2006.253.07:41:32.70/vb/07,04,usb,yes,31,31 2006.253.07:41:32.70/vb/08,04,usb,yes,28,32 2006.253.07:41:32.94/vblo/01,632.99,yes,locked 2006.253.07:41:32.94/vblo/02,640.99,yes,locked 2006.253.07:41:32.94/vblo/03,656.99,yes,locked 2006.253.07:41:32.94/vblo/04,712.99,yes,locked 2006.253.07:41:32.94/vblo/05,744.99,yes,locked 2006.253.07:41:32.94/vblo/06,752.99,yes,locked 2006.253.07:41:32.94/vblo/07,734.99,yes,locked 2006.253.07:41:32.94/vblo/08,744.99,yes,locked 2006.253.07:41:33.09/vabw/8 2006.253.07:41:33.24/vbbw/8 2006.253.07:41:33.33/xfe/off,on,14.0 2006.253.07:41:33.70/ifatt/23,28,28,28 2006.253.07:41:34.08/fmout-gps/S +4.75E-07 2006.253.07:41:34.15:!2006.253.07:42:30 2006.253.07:42:30.00:data_valid=off 2006.253.07:42:30.00:postob 2006.253.07:42:30.20/cable/+6.3701E-03 2006.253.07:42:30.20/wx/31.44,1006.3,72 2006.253.07:42:31.08/fmout-gps/S +4.74E-07 2006.253.07:42:31.08:scan_name=253-0743,k06253,60 2006.253.07:42:31.08:source=1418+546,141946.60,542314.8,2000.0,ccw 2006.253.07:42:31.14#flagr#flagr/antenna,new-source 2006.253.07:42:32.14:checkk5 2006.253.07:42:32.51/chk_autoobs//k5ts1/ autoobs is running! 2006.253.07:42:32.88/chk_autoobs//k5ts2/ autoobs is running! 2006.253.07:42:33.28/chk_autoobs//k5ts3/ autoobs is running! 2006.253.07:42:33.65/chk_autoobs//k5ts4/ autoobs is running! 2006.253.07:42:34.02/chk_obsdata//k5ts1/T2530741??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.07:42:34.39/chk_obsdata//k5ts2/T2530741??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.07:42:34.76/chk_obsdata//k5ts3/T2530741??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.07:42:35.13/chk_obsdata//k5ts4/T2530741??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.07:42:35.83/k5log//k5ts1_log_newline 2006.253.07:42:36.55/k5log//k5ts2_log_newline 2006.253.07:42:37.24/k5log//k5ts3_log_newline 2006.253.07:42:37.93/k5log//k5ts4_log_newline 2006.253.07:42:37.96/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.253.07:42:37.96:4f8m12a=1 2006.253.07:42:37.96$4f8m12a/echo=on 2006.253.07:42:37.96$4f8m12a/pcalon 2006.253.07:42:37.96$pcalon/"no phase cal control is implemented here 2006.253.07:42:37.96$4f8m12a/"tpicd=stop 2006.253.07:42:37.96$4f8m12a/vc4f8 2006.253.07:42:37.96$vc4f8/valo=1,532.99 2006.253.07:42:37.96#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.253.07:42:37.96#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.253.07:42:37.96#ibcon#ireg 17 cls_cnt 0 2006.253.07:42:37.96#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.253.07:42:37.96#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.253.07:42:37.96#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.253.07:42:37.96#ibcon#enter wrdev, iclass 18, count 0 2006.253.07:42:37.96#ibcon#first serial, iclass 18, count 0 2006.253.07:42:37.96#ibcon#enter sib2, iclass 18, count 0 2006.253.07:42:37.96#ibcon#flushed, iclass 18, count 0 2006.253.07:42:37.96#ibcon#about to write, iclass 18, count 0 2006.253.07:42:37.96#ibcon#wrote, iclass 18, count 0 2006.253.07:42:37.96#ibcon#about to read 3, iclass 18, count 0 2006.253.07:42:37.98#ibcon#read 3, iclass 18, count 0 2006.253.07:42:37.98#ibcon#about to read 4, iclass 18, count 0 2006.253.07:42:37.98#ibcon#read 4, iclass 18, count 0 2006.253.07:42:37.98#ibcon#about to read 5, iclass 18, count 0 2006.253.07:42:37.98#ibcon#read 5, iclass 18, count 0 2006.253.07:42:37.98#ibcon#about to read 6, iclass 18, count 0 2006.253.07:42:37.98#ibcon#read 6, iclass 18, count 0 2006.253.07:42:37.98#ibcon#end of sib2, iclass 18, count 0 2006.253.07:42:37.98#ibcon#*mode == 0, iclass 18, count 0 2006.253.07:42:37.98#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.253.07:42:37.98#ibcon#[26=FRQ=01,532.99\r\n] 2006.253.07:42:37.98#ibcon#*before write, iclass 18, count 0 2006.253.07:42:37.98#ibcon#enter sib2, iclass 18, count 0 2006.253.07:42:37.98#ibcon#flushed, iclass 18, count 0 2006.253.07:42:37.98#ibcon#about to write, iclass 18, count 0 2006.253.07:42:37.98#ibcon#wrote, iclass 18, count 0 2006.253.07:42:37.98#ibcon#about to read 3, iclass 18, count 0 2006.253.07:42:38.03#ibcon#read 3, iclass 18, count 0 2006.253.07:42:38.03#ibcon#about to read 4, iclass 18, count 0 2006.253.07:42:38.03#ibcon#read 4, iclass 18, count 0 2006.253.07:42:38.03#ibcon#about to read 5, iclass 18, count 0 2006.253.07:42:38.03#ibcon#read 5, iclass 18, count 0 2006.253.07:42:38.03#ibcon#about to read 6, iclass 18, count 0 2006.253.07:42:38.03#ibcon#read 6, iclass 18, count 0 2006.253.07:42:38.03#ibcon#end of sib2, iclass 18, count 0 2006.253.07:42:38.03#ibcon#*after write, iclass 18, count 0 2006.253.07:42:38.03#ibcon#*before return 0, iclass 18, count 0 2006.253.07:42:38.03#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.253.07:42:38.03#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.253.07:42:38.03#ibcon#about to clear, iclass 18 cls_cnt 0 2006.253.07:42:38.03#ibcon#cleared, iclass 18 cls_cnt 0 2006.253.07:42:38.03$vc4f8/va=1,8 2006.253.07:42:38.03#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.253.07:42:38.03#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.253.07:42:38.03#ibcon#ireg 11 cls_cnt 2 2006.253.07:42:38.03#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.253.07:42:38.03#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.253.07:42:38.03#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.253.07:42:38.03#ibcon#enter wrdev, iclass 20, count 2 2006.253.07:42:38.03#ibcon#first serial, iclass 20, count 2 2006.253.07:42:38.03#ibcon#enter sib2, iclass 20, count 2 2006.253.07:42:38.03#ibcon#flushed, iclass 20, count 2 2006.253.07:42:38.03#ibcon#about to write, iclass 20, count 2 2006.253.07:42:38.03#ibcon#wrote, iclass 20, count 2 2006.253.07:42:38.03#ibcon#about to read 3, iclass 20, count 2 2006.253.07:42:38.05#ibcon#read 3, iclass 20, count 2 2006.253.07:42:38.05#ibcon#about to read 4, iclass 20, count 2 2006.253.07:42:38.05#ibcon#read 4, iclass 20, count 2 2006.253.07:42:38.05#ibcon#about to read 5, iclass 20, count 2 2006.253.07:42:38.05#ibcon#read 5, iclass 20, count 2 2006.253.07:42:38.05#ibcon#about to read 6, iclass 20, count 2 2006.253.07:42:38.05#ibcon#read 6, iclass 20, count 2 2006.253.07:42:38.05#ibcon#end of sib2, iclass 20, count 2 2006.253.07:42:38.05#ibcon#*mode == 0, iclass 20, count 2 2006.253.07:42:38.05#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.253.07:42:38.05#ibcon#[25=AT01-08\r\n] 2006.253.07:42:38.05#ibcon#*before write, iclass 20, count 2 2006.253.07:42:38.05#ibcon#enter sib2, iclass 20, count 2 2006.253.07:42:38.05#ibcon#flushed, iclass 20, count 2 2006.253.07:42:38.05#ibcon#about to write, iclass 20, count 2 2006.253.07:42:38.05#ibcon#wrote, iclass 20, count 2 2006.253.07:42:38.05#ibcon#about to read 3, iclass 20, count 2 2006.253.07:42:38.08#ibcon#read 3, iclass 20, count 2 2006.253.07:42:38.08#ibcon#about to read 4, iclass 20, count 2 2006.253.07:42:38.08#ibcon#read 4, iclass 20, count 2 2006.253.07:42:38.08#ibcon#about to read 5, iclass 20, count 2 2006.253.07:42:38.08#ibcon#read 5, iclass 20, count 2 2006.253.07:42:38.08#ibcon#about to read 6, iclass 20, count 2 2006.253.07:42:38.08#ibcon#read 6, iclass 20, count 2 2006.253.07:42:38.08#ibcon#end of sib2, iclass 20, count 2 2006.253.07:42:38.08#ibcon#*after write, iclass 20, count 2 2006.253.07:42:38.08#ibcon#*before return 0, iclass 20, count 2 2006.253.07:42:38.08#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.253.07:42:38.08#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.253.07:42:38.08#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.253.07:42:38.08#ibcon#ireg 7 cls_cnt 0 2006.253.07:42:38.08#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.253.07:42:38.20#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.253.07:42:38.20#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.253.07:42:38.20#ibcon#enter wrdev, iclass 20, count 0 2006.253.07:42:38.20#ibcon#first serial, iclass 20, count 0 2006.253.07:42:38.20#ibcon#enter sib2, iclass 20, count 0 2006.253.07:42:38.20#ibcon#flushed, iclass 20, count 0 2006.253.07:42:38.20#ibcon#about to write, iclass 20, count 0 2006.253.07:42:38.20#ibcon#wrote, iclass 20, count 0 2006.253.07:42:38.20#ibcon#about to read 3, iclass 20, count 0 2006.253.07:42:38.22#ibcon#read 3, iclass 20, count 0 2006.253.07:42:38.22#ibcon#about to read 4, iclass 20, count 0 2006.253.07:42:38.22#ibcon#read 4, iclass 20, count 0 2006.253.07:42:38.22#ibcon#about to read 5, iclass 20, count 0 2006.253.07:42:38.22#ibcon#read 5, iclass 20, count 0 2006.253.07:42:38.22#ibcon#about to read 6, iclass 20, count 0 2006.253.07:42:38.22#ibcon#read 6, iclass 20, count 0 2006.253.07:42:38.22#ibcon#end of sib2, iclass 20, count 0 2006.253.07:42:38.22#ibcon#*mode == 0, iclass 20, count 0 2006.253.07:42:38.22#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.253.07:42:38.22#ibcon#[25=USB\r\n] 2006.253.07:42:38.22#ibcon#*before write, iclass 20, count 0 2006.253.07:42:38.22#ibcon#enter sib2, iclass 20, count 0 2006.253.07:42:38.22#ibcon#flushed, iclass 20, count 0 2006.253.07:42:38.22#ibcon#about to write, iclass 20, count 0 2006.253.07:42:38.22#ibcon#wrote, iclass 20, count 0 2006.253.07:42:38.22#ibcon#about to read 3, iclass 20, count 0 2006.253.07:42:38.25#ibcon#read 3, iclass 20, count 0 2006.253.07:42:38.25#ibcon#about to read 4, iclass 20, count 0 2006.253.07:42:38.25#ibcon#read 4, iclass 20, count 0 2006.253.07:42:38.25#ibcon#about to read 5, iclass 20, count 0 2006.253.07:42:38.25#ibcon#read 5, iclass 20, count 0 2006.253.07:42:38.25#ibcon#about to read 6, iclass 20, count 0 2006.253.07:42:38.25#ibcon#read 6, iclass 20, count 0 2006.253.07:42:38.25#ibcon#end of sib2, iclass 20, count 0 2006.253.07:42:38.25#ibcon#*after write, iclass 20, count 0 2006.253.07:42:38.25#ibcon#*before return 0, iclass 20, count 0 2006.253.07:42:38.25#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.253.07:42:38.25#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.253.07:42:38.25#ibcon#about to clear, iclass 20 cls_cnt 0 2006.253.07:42:38.25#ibcon#cleared, iclass 20 cls_cnt 0 2006.253.07:42:38.25$vc4f8/valo=2,572.99 2006.253.07:42:38.25#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.253.07:42:38.25#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.253.07:42:38.25#ibcon#ireg 17 cls_cnt 0 2006.253.07:42:38.25#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.253.07:42:38.25#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.253.07:42:38.25#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.253.07:42:38.25#ibcon#enter wrdev, iclass 22, count 0 2006.253.07:42:38.25#ibcon#first serial, iclass 22, count 0 2006.253.07:42:38.25#ibcon#enter sib2, iclass 22, count 0 2006.253.07:42:38.25#ibcon#flushed, iclass 22, count 0 2006.253.07:42:38.25#ibcon#about to write, iclass 22, count 0 2006.253.07:42:38.25#ibcon#wrote, iclass 22, count 0 2006.253.07:42:38.25#ibcon#about to read 3, iclass 22, count 0 2006.253.07:42:38.27#ibcon#read 3, iclass 22, count 0 2006.253.07:42:38.27#ibcon#about to read 4, iclass 22, count 0 2006.253.07:42:38.27#ibcon#read 4, iclass 22, count 0 2006.253.07:42:38.27#ibcon#about to read 5, iclass 22, count 0 2006.253.07:42:38.27#ibcon#read 5, iclass 22, count 0 2006.253.07:42:38.27#ibcon#about to read 6, iclass 22, count 0 2006.253.07:42:38.27#ibcon#read 6, iclass 22, count 0 2006.253.07:42:38.27#ibcon#end of sib2, iclass 22, count 0 2006.253.07:42:38.27#ibcon#*mode == 0, iclass 22, count 0 2006.253.07:42:38.27#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.253.07:42:38.27#ibcon#[26=FRQ=02,572.99\r\n] 2006.253.07:42:38.27#ibcon#*before write, iclass 22, count 0 2006.253.07:42:38.27#ibcon#enter sib2, iclass 22, count 0 2006.253.07:42:38.27#ibcon#flushed, iclass 22, count 0 2006.253.07:42:38.27#ibcon#about to write, iclass 22, count 0 2006.253.07:42:38.27#ibcon#wrote, iclass 22, count 0 2006.253.07:42:38.27#ibcon#about to read 3, iclass 22, count 0 2006.253.07:42:38.31#ibcon#read 3, iclass 22, count 0 2006.253.07:42:38.31#ibcon#about to read 4, iclass 22, count 0 2006.253.07:42:38.31#ibcon#read 4, iclass 22, count 0 2006.253.07:42:38.31#ibcon#about to read 5, iclass 22, count 0 2006.253.07:42:38.31#ibcon#read 5, iclass 22, count 0 2006.253.07:42:38.31#ibcon#about to read 6, iclass 22, count 0 2006.253.07:42:38.31#ibcon#read 6, iclass 22, count 0 2006.253.07:42:38.31#ibcon#end of sib2, iclass 22, count 0 2006.253.07:42:38.31#ibcon#*after write, iclass 22, count 0 2006.253.07:42:38.31#ibcon#*before return 0, iclass 22, count 0 2006.253.07:42:38.31#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.253.07:42:38.31#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.253.07:42:38.31#ibcon#about to clear, iclass 22 cls_cnt 0 2006.253.07:42:38.31#ibcon#cleared, iclass 22 cls_cnt 0 2006.253.07:42:38.31$vc4f8/va=2,7 2006.253.07:42:38.31#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.253.07:42:38.31#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.253.07:42:38.31#ibcon#ireg 11 cls_cnt 2 2006.253.07:42:38.31#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.253.07:42:38.37#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.253.07:42:38.37#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.253.07:42:38.37#ibcon#enter wrdev, iclass 24, count 2 2006.253.07:42:38.37#ibcon#first serial, iclass 24, count 2 2006.253.07:42:38.37#ibcon#enter sib2, iclass 24, count 2 2006.253.07:42:38.37#ibcon#flushed, iclass 24, count 2 2006.253.07:42:38.37#ibcon#about to write, iclass 24, count 2 2006.253.07:42:38.37#ibcon#wrote, iclass 24, count 2 2006.253.07:42:38.37#ibcon#about to read 3, iclass 24, count 2 2006.253.07:42:38.39#ibcon#read 3, iclass 24, count 2 2006.253.07:42:38.39#ibcon#about to read 4, iclass 24, count 2 2006.253.07:42:38.39#ibcon#read 4, iclass 24, count 2 2006.253.07:42:38.39#ibcon#about to read 5, iclass 24, count 2 2006.253.07:42:38.39#ibcon#read 5, iclass 24, count 2 2006.253.07:42:38.39#ibcon#about to read 6, iclass 24, count 2 2006.253.07:42:38.39#ibcon#read 6, iclass 24, count 2 2006.253.07:42:38.39#ibcon#end of sib2, iclass 24, count 2 2006.253.07:42:38.39#ibcon#*mode == 0, iclass 24, count 2 2006.253.07:42:38.39#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.253.07:42:38.39#ibcon#[25=AT02-07\r\n] 2006.253.07:42:38.39#ibcon#*before write, iclass 24, count 2 2006.253.07:42:38.39#ibcon#enter sib2, iclass 24, count 2 2006.253.07:42:38.39#ibcon#flushed, iclass 24, count 2 2006.253.07:42:38.39#ibcon#about to write, iclass 24, count 2 2006.253.07:42:38.39#ibcon#wrote, iclass 24, count 2 2006.253.07:42:38.39#ibcon#about to read 3, iclass 24, count 2 2006.253.07:42:38.43#ibcon#read 3, iclass 24, count 2 2006.253.07:42:38.43#ibcon#about to read 4, iclass 24, count 2 2006.253.07:42:38.43#ibcon#read 4, iclass 24, count 2 2006.253.07:42:38.43#ibcon#about to read 5, iclass 24, count 2 2006.253.07:42:38.43#ibcon#read 5, iclass 24, count 2 2006.253.07:42:38.43#ibcon#about to read 6, iclass 24, count 2 2006.253.07:42:38.43#ibcon#read 6, iclass 24, count 2 2006.253.07:42:38.43#ibcon#end of sib2, iclass 24, count 2 2006.253.07:42:38.43#ibcon#*after write, iclass 24, count 2 2006.253.07:42:38.43#ibcon#*before return 0, iclass 24, count 2 2006.253.07:42:38.43#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.253.07:42:38.43#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.253.07:42:38.43#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.253.07:42:38.43#ibcon#ireg 7 cls_cnt 0 2006.253.07:42:38.43#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.253.07:42:38.55#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.253.07:42:38.55#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.253.07:42:38.55#ibcon#enter wrdev, iclass 24, count 0 2006.253.07:42:38.55#ibcon#first serial, iclass 24, count 0 2006.253.07:42:38.55#ibcon#enter sib2, iclass 24, count 0 2006.253.07:42:38.55#ibcon#flushed, iclass 24, count 0 2006.253.07:42:38.55#ibcon#about to write, iclass 24, count 0 2006.253.07:42:38.55#ibcon#wrote, iclass 24, count 0 2006.253.07:42:38.55#ibcon#about to read 3, iclass 24, count 0 2006.253.07:42:38.57#ibcon#read 3, iclass 24, count 0 2006.253.07:42:38.57#ibcon#about to read 4, iclass 24, count 0 2006.253.07:42:38.57#ibcon#read 4, iclass 24, count 0 2006.253.07:42:38.57#ibcon#about to read 5, iclass 24, count 0 2006.253.07:42:38.57#ibcon#read 5, iclass 24, count 0 2006.253.07:42:38.57#ibcon#about to read 6, iclass 24, count 0 2006.253.07:42:38.57#ibcon#read 6, iclass 24, count 0 2006.253.07:42:38.57#ibcon#end of sib2, iclass 24, count 0 2006.253.07:42:38.57#ibcon#*mode == 0, iclass 24, count 0 2006.253.07:42:38.57#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.253.07:42:38.57#ibcon#[25=USB\r\n] 2006.253.07:42:38.57#ibcon#*before write, iclass 24, count 0 2006.253.07:42:38.57#ibcon#enter sib2, iclass 24, count 0 2006.253.07:42:38.57#ibcon#flushed, iclass 24, count 0 2006.253.07:42:38.57#ibcon#about to write, iclass 24, count 0 2006.253.07:42:38.57#ibcon#wrote, iclass 24, count 0 2006.253.07:42:38.57#ibcon#about to read 3, iclass 24, count 0 2006.253.07:42:38.60#ibcon#read 3, iclass 24, count 0 2006.253.07:42:38.60#ibcon#about to read 4, iclass 24, count 0 2006.253.07:42:38.60#ibcon#read 4, iclass 24, count 0 2006.253.07:42:38.60#ibcon#about to read 5, iclass 24, count 0 2006.253.07:42:38.60#ibcon#read 5, iclass 24, count 0 2006.253.07:42:38.60#ibcon#about to read 6, iclass 24, count 0 2006.253.07:42:38.60#ibcon#read 6, iclass 24, count 0 2006.253.07:42:38.60#ibcon#end of sib2, iclass 24, count 0 2006.253.07:42:38.60#ibcon#*after write, iclass 24, count 0 2006.253.07:42:38.60#ibcon#*before return 0, iclass 24, count 0 2006.253.07:42:38.60#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.253.07:42:38.60#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.253.07:42:38.60#ibcon#about to clear, iclass 24 cls_cnt 0 2006.253.07:42:38.60#ibcon#cleared, iclass 24 cls_cnt 0 2006.253.07:42:38.60$vc4f8/valo=3,672.99 2006.253.07:42:38.60#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.253.07:42:38.60#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.253.07:42:38.60#ibcon#ireg 17 cls_cnt 0 2006.253.07:42:38.60#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.253.07:42:38.60#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.253.07:42:38.60#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.253.07:42:38.60#ibcon#enter wrdev, iclass 26, count 0 2006.253.07:42:38.60#ibcon#first serial, iclass 26, count 0 2006.253.07:42:38.60#ibcon#enter sib2, iclass 26, count 0 2006.253.07:42:38.60#ibcon#flushed, iclass 26, count 0 2006.253.07:42:38.60#ibcon#about to write, iclass 26, count 0 2006.253.07:42:38.60#ibcon#wrote, iclass 26, count 0 2006.253.07:42:38.60#ibcon#about to read 3, iclass 26, count 0 2006.253.07:42:38.62#ibcon#read 3, iclass 26, count 0 2006.253.07:42:38.62#ibcon#about to read 4, iclass 26, count 0 2006.253.07:42:38.62#ibcon#read 4, iclass 26, count 0 2006.253.07:42:38.62#ibcon#about to read 5, iclass 26, count 0 2006.253.07:42:38.62#ibcon#read 5, iclass 26, count 0 2006.253.07:42:38.62#ibcon#about to read 6, iclass 26, count 0 2006.253.07:42:38.62#ibcon#read 6, iclass 26, count 0 2006.253.07:42:38.62#ibcon#end of sib2, iclass 26, count 0 2006.253.07:42:38.62#ibcon#*mode == 0, iclass 26, count 0 2006.253.07:42:38.62#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.253.07:42:38.62#ibcon#[26=FRQ=03,672.99\r\n] 2006.253.07:42:38.62#ibcon#*before write, iclass 26, count 0 2006.253.07:42:38.62#ibcon#enter sib2, iclass 26, count 0 2006.253.07:42:38.62#ibcon#flushed, iclass 26, count 0 2006.253.07:42:38.62#ibcon#about to write, iclass 26, count 0 2006.253.07:42:38.62#ibcon#wrote, iclass 26, count 0 2006.253.07:42:38.62#ibcon#about to read 3, iclass 26, count 0 2006.253.07:42:38.67#ibcon#read 3, iclass 26, count 0 2006.253.07:42:38.67#ibcon#about to read 4, iclass 26, count 0 2006.253.07:42:38.67#ibcon#read 4, iclass 26, count 0 2006.253.07:42:38.67#ibcon#about to read 5, iclass 26, count 0 2006.253.07:42:38.67#ibcon#read 5, iclass 26, count 0 2006.253.07:42:38.67#ibcon#about to read 6, iclass 26, count 0 2006.253.07:42:38.67#ibcon#read 6, iclass 26, count 0 2006.253.07:42:38.67#ibcon#end of sib2, iclass 26, count 0 2006.253.07:42:38.67#ibcon#*after write, iclass 26, count 0 2006.253.07:42:38.67#ibcon#*before return 0, iclass 26, count 0 2006.253.07:42:38.67#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.253.07:42:38.67#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.253.07:42:38.67#ibcon#about to clear, iclass 26 cls_cnt 0 2006.253.07:42:38.67#ibcon#cleared, iclass 26 cls_cnt 0 2006.253.07:42:38.67$vc4f8/va=3,6 2006.253.07:42:38.67#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.253.07:42:38.67#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.253.07:42:38.67#ibcon#ireg 11 cls_cnt 2 2006.253.07:42:38.67#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.253.07:42:38.72#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.253.07:42:38.72#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.253.07:42:38.72#ibcon#enter wrdev, iclass 28, count 2 2006.253.07:42:38.72#ibcon#first serial, iclass 28, count 2 2006.253.07:42:38.72#ibcon#enter sib2, iclass 28, count 2 2006.253.07:42:38.72#ibcon#flushed, iclass 28, count 2 2006.253.07:42:38.72#ibcon#about to write, iclass 28, count 2 2006.253.07:42:38.72#ibcon#wrote, iclass 28, count 2 2006.253.07:42:38.72#ibcon#about to read 3, iclass 28, count 2 2006.253.07:42:38.74#ibcon#read 3, iclass 28, count 2 2006.253.07:42:38.74#ibcon#about to read 4, iclass 28, count 2 2006.253.07:42:38.74#ibcon#read 4, iclass 28, count 2 2006.253.07:42:38.74#ibcon#about to read 5, iclass 28, count 2 2006.253.07:42:38.74#ibcon#read 5, iclass 28, count 2 2006.253.07:42:38.74#ibcon#about to read 6, iclass 28, count 2 2006.253.07:42:38.74#ibcon#read 6, iclass 28, count 2 2006.253.07:42:38.74#ibcon#end of sib2, iclass 28, count 2 2006.253.07:42:38.74#ibcon#*mode == 0, iclass 28, count 2 2006.253.07:42:38.74#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.253.07:42:38.74#ibcon#[25=AT03-06\r\n] 2006.253.07:42:38.74#ibcon#*before write, iclass 28, count 2 2006.253.07:42:38.74#ibcon#enter sib2, iclass 28, count 2 2006.253.07:42:38.74#ibcon#flushed, iclass 28, count 2 2006.253.07:42:38.74#ibcon#about to write, iclass 28, count 2 2006.253.07:42:38.74#ibcon#wrote, iclass 28, count 2 2006.253.07:42:38.74#ibcon#about to read 3, iclass 28, count 2 2006.253.07:42:38.77#ibcon#read 3, iclass 28, count 2 2006.253.07:42:38.77#ibcon#about to read 4, iclass 28, count 2 2006.253.07:42:38.77#ibcon#read 4, iclass 28, count 2 2006.253.07:42:38.77#ibcon#about to read 5, iclass 28, count 2 2006.253.07:42:38.77#ibcon#read 5, iclass 28, count 2 2006.253.07:42:38.77#ibcon#about to read 6, iclass 28, count 2 2006.253.07:42:38.77#ibcon#read 6, iclass 28, count 2 2006.253.07:42:38.77#ibcon#end of sib2, iclass 28, count 2 2006.253.07:42:38.77#ibcon#*after write, iclass 28, count 2 2006.253.07:42:38.77#ibcon#*before return 0, iclass 28, count 2 2006.253.07:42:38.77#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.253.07:42:38.77#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.253.07:42:38.77#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.253.07:42:38.77#ibcon#ireg 7 cls_cnt 0 2006.253.07:42:38.77#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.253.07:42:38.89#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.253.07:42:38.89#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.253.07:42:38.89#ibcon#enter wrdev, iclass 28, count 0 2006.253.07:42:38.89#ibcon#first serial, iclass 28, count 0 2006.253.07:42:38.89#ibcon#enter sib2, iclass 28, count 0 2006.253.07:42:38.89#ibcon#flushed, iclass 28, count 0 2006.253.07:42:38.89#ibcon#about to write, iclass 28, count 0 2006.253.07:42:38.89#ibcon#wrote, iclass 28, count 0 2006.253.07:42:38.89#ibcon#about to read 3, iclass 28, count 0 2006.253.07:42:38.91#ibcon#read 3, iclass 28, count 0 2006.253.07:42:38.91#ibcon#about to read 4, iclass 28, count 0 2006.253.07:42:38.91#ibcon#read 4, iclass 28, count 0 2006.253.07:42:38.91#ibcon#about to read 5, iclass 28, count 0 2006.253.07:42:38.91#ibcon#read 5, iclass 28, count 0 2006.253.07:42:38.91#ibcon#about to read 6, iclass 28, count 0 2006.253.07:42:38.91#ibcon#read 6, iclass 28, count 0 2006.253.07:42:38.91#ibcon#end of sib2, iclass 28, count 0 2006.253.07:42:38.91#ibcon#*mode == 0, iclass 28, count 0 2006.253.07:42:38.91#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.253.07:42:38.91#ibcon#[25=USB\r\n] 2006.253.07:42:38.91#ibcon#*before write, iclass 28, count 0 2006.253.07:42:38.91#ibcon#enter sib2, iclass 28, count 0 2006.253.07:42:38.91#ibcon#flushed, iclass 28, count 0 2006.253.07:42:38.91#ibcon#about to write, iclass 28, count 0 2006.253.07:42:38.91#ibcon#wrote, iclass 28, count 0 2006.253.07:42:38.91#ibcon#about to read 3, iclass 28, count 0 2006.253.07:42:38.94#ibcon#read 3, iclass 28, count 0 2006.253.07:42:38.94#ibcon#about to read 4, iclass 28, count 0 2006.253.07:42:38.94#ibcon#read 4, iclass 28, count 0 2006.253.07:42:38.94#ibcon#about to read 5, iclass 28, count 0 2006.253.07:42:38.94#ibcon#read 5, iclass 28, count 0 2006.253.07:42:38.94#ibcon#about to read 6, iclass 28, count 0 2006.253.07:42:38.94#ibcon#read 6, iclass 28, count 0 2006.253.07:42:38.94#ibcon#end of sib2, iclass 28, count 0 2006.253.07:42:38.94#ibcon#*after write, iclass 28, count 0 2006.253.07:42:38.94#ibcon#*before return 0, iclass 28, count 0 2006.253.07:42:38.94#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.253.07:42:38.94#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.253.07:42:38.94#ibcon#about to clear, iclass 28 cls_cnt 0 2006.253.07:42:38.94#ibcon#cleared, iclass 28 cls_cnt 0 2006.253.07:42:38.94$vc4f8/valo=4,832.99 2006.253.07:42:38.94#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.253.07:42:38.94#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.253.07:42:38.94#ibcon#ireg 17 cls_cnt 0 2006.253.07:42:38.94#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.253.07:42:38.94#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.253.07:42:38.94#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.253.07:42:38.94#ibcon#enter wrdev, iclass 30, count 0 2006.253.07:42:38.94#ibcon#first serial, iclass 30, count 0 2006.253.07:42:38.94#ibcon#enter sib2, iclass 30, count 0 2006.253.07:42:38.94#ibcon#flushed, iclass 30, count 0 2006.253.07:42:38.94#ibcon#about to write, iclass 30, count 0 2006.253.07:42:38.94#ibcon#wrote, iclass 30, count 0 2006.253.07:42:38.94#ibcon#about to read 3, iclass 30, count 0 2006.253.07:42:38.96#ibcon#read 3, iclass 30, count 0 2006.253.07:42:38.96#ibcon#about to read 4, iclass 30, count 0 2006.253.07:42:38.96#ibcon#read 4, iclass 30, count 0 2006.253.07:42:38.96#ibcon#about to read 5, iclass 30, count 0 2006.253.07:42:38.96#ibcon#read 5, iclass 30, count 0 2006.253.07:42:38.96#ibcon#about to read 6, iclass 30, count 0 2006.253.07:42:38.96#ibcon#read 6, iclass 30, count 0 2006.253.07:42:38.96#ibcon#end of sib2, iclass 30, count 0 2006.253.07:42:38.96#ibcon#*mode == 0, iclass 30, count 0 2006.253.07:42:38.96#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.253.07:42:38.96#ibcon#[26=FRQ=04,832.99\r\n] 2006.253.07:42:38.96#ibcon#*before write, iclass 30, count 0 2006.253.07:42:38.96#ibcon#enter sib2, iclass 30, count 0 2006.253.07:42:38.96#ibcon#flushed, iclass 30, count 0 2006.253.07:42:38.96#ibcon#about to write, iclass 30, count 0 2006.253.07:42:38.96#ibcon#wrote, iclass 30, count 0 2006.253.07:42:38.96#ibcon#about to read 3, iclass 30, count 0 2006.253.07:42:39.01#ibcon#read 3, iclass 30, count 0 2006.253.07:42:39.01#ibcon#about to read 4, iclass 30, count 0 2006.253.07:42:39.01#ibcon#read 4, iclass 30, count 0 2006.253.07:42:39.01#ibcon#about to read 5, iclass 30, count 0 2006.253.07:42:39.01#ibcon#read 5, iclass 30, count 0 2006.253.07:42:39.01#ibcon#about to read 6, iclass 30, count 0 2006.253.07:42:39.01#ibcon#read 6, iclass 30, count 0 2006.253.07:42:39.01#ibcon#end of sib2, iclass 30, count 0 2006.253.07:42:39.01#ibcon#*after write, iclass 30, count 0 2006.253.07:42:39.01#ibcon#*before return 0, iclass 30, count 0 2006.253.07:42:39.01#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.253.07:42:39.01#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.253.07:42:39.01#ibcon#about to clear, iclass 30 cls_cnt 0 2006.253.07:42:39.01#ibcon#cleared, iclass 30 cls_cnt 0 2006.253.07:42:39.01$vc4f8/va=4,7 2006.253.07:42:39.01#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.253.07:42:39.01#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.253.07:42:39.01#ibcon#ireg 11 cls_cnt 2 2006.253.07:42:39.01#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.253.07:42:39.06#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.253.07:42:39.06#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.253.07:42:39.06#ibcon#enter wrdev, iclass 32, count 2 2006.253.07:42:39.06#ibcon#first serial, iclass 32, count 2 2006.253.07:42:39.06#ibcon#enter sib2, iclass 32, count 2 2006.253.07:42:39.06#ibcon#flushed, iclass 32, count 2 2006.253.07:42:39.06#ibcon#about to write, iclass 32, count 2 2006.253.07:42:39.06#ibcon#wrote, iclass 32, count 2 2006.253.07:42:39.06#ibcon#about to read 3, iclass 32, count 2 2006.253.07:42:39.08#ibcon#read 3, iclass 32, count 2 2006.253.07:42:39.08#ibcon#about to read 4, iclass 32, count 2 2006.253.07:42:39.08#ibcon#read 4, iclass 32, count 2 2006.253.07:42:39.08#ibcon#about to read 5, iclass 32, count 2 2006.253.07:42:39.08#ibcon#read 5, iclass 32, count 2 2006.253.07:42:39.08#ibcon#about to read 6, iclass 32, count 2 2006.253.07:42:39.08#ibcon#read 6, iclass 32, count 2 2006.253.07:42:39.08#ibcon#end of sib2, iclass 32, count 2 2006.253.07:42:39.08#ibcon#*mode == 0, iclass 32, count 2 2006.253.07:42:39.08#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.253.07:42:39.08#ibcon#[25=AT04-07\r\n] 2006.253.07:42:39.08#ibcon#*before write, iclass 32, count 2 2006.253.07:42:39.08#ibcon#enter sib2, iclass 32, count 2 2006.253.07:42:39.08#ibcon#flushed, iclass 32, count 2 2006.253.07:42:39.08#ibcon#about to write, iclass 32, count 2 2006.253.07:42:39.08#ibcon#wrote, iclass 32, count 2 2006.253.07:42:39.08#ibcon#about to read 3, iclass 32, count 2 2006.253.07:42:39.11#ibcon#read 3, iclass 32, count 2 2006.253.07:42:39.11#ibcon#about to read 4, iclass 32, count 2 2006.253.07:42:39.11#ibcon#read 4, iclass 32, count 2 2006.253.07:42:39.11#ibcon#about to read 5, iclass 32, count 2 2006.253.07:42:39.11#ibcon#read 5, iclass 32, count 2 2006.253.07:42:39.11#ibcon#about to read 6, iclass 32, count 2 2006.253.07:42:39.11#ibcon#read 6, iclass 32, count 2 2006.253.07:42:39.11#ibcon#end of sib2, iclass 32, count 2 2006.253.07:42:39.11#ibcon#*after write, iclass 32, count 2 2006.253.07:42:39.11#ibcon#*before return 0, iclass 32, count 2 2006.253.07:42:39.11#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.253.07:42:39.11#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.253.07:42:39.11#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.253.07:42:39.11#ibcon#ireg 7 cls_cnt 0 2006.253.07:42:39.11#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.253.07:42:39.23#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.253.07:42:39.23#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.253.07:42:39.23#ibcon#enter wrdev, iclass 32, count 0 2006.253.07:42:39.23#ibcon#first serial, iclass 32, count 0 2006.253.07:42:39.23#ibcon#enter sib2, iclass 32, count 0 2006.253.07:42:39.23#ibcon#flushed, iclass 32, count 0 2006.253.07:42:39.23#ibcon#about to write, iclass 32, count 0 2006.253.07:42:39.23#ibcon#wrote, iclass 32, count 0 2006.253.07:42:39.23#ibcon#about to read 3, iclass 32, count 0 2006.253.07:42:39.25#ibcon#read 3, iclass 32, count 0 2006.253.07:42:39.25#ibcon#about to read 4, iclass 32, count 0 2006.253.07:42:39.25#ibcon#read 4, iclass 32, count 0 2006.253.07:42:39.25#ibcon#about to read 5, iclass 32, count 0 2006.253.07:42:39.25#ibcon#read 5, iclass 32, count 0 2006.253.07:42:39.25#ibcon#about to read 6, iclass 32, count 0 2006.253.07:42:39.25#ibcon#read 6, iclass 32, count 0 2006.253.07:42:39.25#ibcon#end of sib2, iclass 32, count 0 2006.253.07:42:39.25#ibcon#*mode == 0, iclass 32, count 0 2006.253.07:42:39.25#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.253.07:42:39.25#ibcon#[25=USB\r\n] 2006.253.07:42:39.25#ibcon#*before write, iclass 32, count 0 2006.253.07:42:39.25#ibcon#enter sib2, iclass 32, count 0 2006.253.07:42:39.25#ibcon#flushed, iclass 32, count 0 2006.253.07:42:39.25#ibcon#about to write, iclass 32, count 0 2006.253.07:42:39.25#ibcon#wrote, iclass 32, count 0 2006.253.07:42:39.25#ibcon#about to read 3, iclass 32, count 0 2006.253.07:42:39.28#ibcon#read 3, iclass 32, count 0 2006.253.07:42:39.28#ibcon#about to read 4, iclass 32, count 0 2006.253.07:42:39.28#ibcon#read 4, iclass 32, count 0 2006.253.07:42:39.28#ibcon#about to read 5, iclass 32, count 0 2006.253.07:42:39.28#ibcon#read 5, iclass 32, count 0 2006.253.07:42:39.28#ibcon#about to read 6, iclass 32, count 0 2006.253.07:42:39.28#ibcon#read 6, iclass 32, count 0 2006.253.07:42:39.28#ibcon#end of sib2, iclass 32, count 0 2006.253.07:42:39.28#ibcon#*after write, iclass 32, count 0 2006.253.07:42:39.28#ibcon#*before return 0, iclass 32, count 0 2006.253.07:42:39.28#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.253.07:42:39.28#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.253.07:42:39.28#ibcon#about to clear, iclass 32 cls_cnt 0 2006.253.07:42:39.28#ibcon#cleared, iclass 32 cls_cnt 0 2006.253.07:42:39.28$vc4f8/valo=5,652.99 2006.253.07:42:39.28#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.253.07:42:39.28#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.253.07:42:39.28#ibcon#ireg 17 cls_cnt 0 2006.253.07:42:39.28#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.253.07:42:39.28#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.253.07:42:39.28#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.253.07:42:39.28#ibcon#enter wrdev, iclass 34, count 0 2006.253.07:42:39.28#ibcon#first serial, iclass 34, count 0 2006.253.07:42:39.28#ibcon#enter sib2, iclass 34, count 0 2006.253.07:42:39.28#ibcon#flushed, iclass 34, count 0 2006.253.07:42:39.28#ibcon#about to write, iclass 34, count 0 2006.253.07:42:39.28#ibcon#wrote, iclass 34, count 0 2006.253.07:42:39.28#ibcon#about to read 3, iclass 34, count 0 2006.253.07:42:39.30#ibcon#read 3, iclass 34, count 0 2006.253.07:42:39.30#ibcon#about to read 4, iclass 34, count 0 2006.253.07:42:39.30#ibcon#read 4, iclass 34, count 0 2006.253.07:42:39.30#ibcon#about to read 5, iclass 34, count 0 2006.253.07:42:39.30#ibcon#read 5, iclass 34, count 0 2006.253.07:42:39.30#ibcon#about to read 6, iclass 34, count 0 2006.253.07:42:39.30#ibcon#read 6, iclass 34, count 0 2006.253.07:42:39.30#ibcon#end of sib2, iclass 34, count 0 2006.253.07:42:39.30#ibcon#*mode == 0, iclass 34, count 0 2006.253.07:42:39.30#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.253.07:42:39.30#ibcon#[26=FRQ=05,652.99\r\n] 2006.253.07:42:39.30#ibcon#*before write, iclass 34, count 0 2006.253.07:42:39.30#ibcon#enter sib2, iclass 34, count 0 2006.253.07:42:39.30#ibcon#flushed, iclass 34, count 0 2006.253.07:42:39.30#ibcon#about to write, iclass 34, count 0 2006.253.07:42:39.30#ibcon#wrote, iclass 34, count 0 2006.253.07:42:39.30#ibcon#about to read 3, iclass 34, count 0 2006.253.07:42:39.34#ibcon#read 3, iclass 34, count 0 2006.253.07:42:39.34#ibcon#about to read 4, iclass 34, count 0 2006.253.07:42:39.34#ibcon#read 4, iclass 34, count 0 2006.253.07:42:39.34#ibcon#about to read 5, iclass 34, count 0 2006.253.07:42:39.34#ibcon#read 5, iclass 34, count 0 2006.253.07:42:39.34#ibcon#about to read 6, iclass 34, count 0 2006.253.07:42:39.34#ibcon#read 6, iclass 34, count 0 2006.253.07:42:39.34#ibcon#end of sib2, iclass 34, count 0 2006.253.07:42:39.34#ibcon#*after write, iclass 34, count 0 2006.253.07:42:39.34#ibcon#*before return 0, iclass 34, count 0 2006.253.07:42:39.34#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.253.07:42:39.34#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.253.07:42:39.34#ibcon#about to clear, iclass 34 cls_cnt 0 2006.253.07:42:39.34#ibcon#cleared, iclass 34 cls_cnt 0 2006.253.07:42:39.34$vc4f8/va=5,7 2006.253.07:42:39.34#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.253.07:42:39.34#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.253.07:42:39.34#ibcon#ireg 11 cls_cnt 2 2006.253.07:42:39.34#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.253.07:42:39.40#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.253.07:42:39.40#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.253.07:42:39.40#ibcon#enter wrdev, iclass 36, count 2 2006.253.07:42:39.40#ibcon#first serial, iclass 36, count 2 2006.253.07:42:39.40#ibcon#enter sib2, iclass 36, count 2 2006.253.07:42:39.40#ibcon#flushed, iclass 36, count 2 2006.253.07:42:39.40#ibcon#about to write, iclass 36, count 2 2006.253.07:42:39.40#ibcon#wrote, iclass 36, count 2 2006.253.07:42:39.40#ibcon#about to read 3, iclass 36, count 2 2006.253.07:42:39.42#ibcon#read 3, iclass 36, count 2 2006.253.07:42:39.42#ibcon#about to read 4, iclass 36, count 2 2006.253.07:42:39.42#ibcon#read 4, iclass 36, count 2 2006.253.07:42:39.42#ibcon#about to read 5, iclass 36, count 2 2006.253.07:42:39.42#ibcon#read 5, iclass 36, count 2 2006.253.07:42:39.42#ibcon#about to read 6, iclass 36, count 2 2006.253.07:42:39.42#ibcon#read 6, iclass 36, count 2 2006.253.07:42:39.42#ibcon#end of sib2, iclass 36, count 2 2006.253.07:42:39.42#ibcon#*mode == 0, iclass 36, count 2 2006.253.07:42:39.42#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.253.07:42:39.42#ibcon#[25=AT05-07\r\n] 2006.253.07:42:39.42#ibcon#*before write, iclass 36, count 2 2006.253.07:42:39.42#ibcon#enter sib2, iclass 36, count 2 2006.253.07:42:39.42#ibcon#flushed, iclass 36, count 2 2006.253.07:42:39.42#ibcon#about to write, iclass 36, count 2 2006.253.07:42:39.42#ibcon#wrote, iclass 36, count 2 2006.253.07:42:39.42#ibcon#about to read 3, iclass 36, count 2 2006.253.07:42:39.45#ibcon#read 3, iclass 36, count 2 2006.253.07:42:39.45#ibcon#about to read 4, iclass 36, count 2 2006.253.07:42:39.45#ibcon#read 4, iclass 36, count 2 2006.253.07:42:39.45#ibcon#about to read 5, iclass 36, count 2 2006.253.07:42:39.45#ibcon#read 5, iclass 36, count 2 2006.253.07:42:39.45#ibcon#about to read 6, iclass 36, count 2 2006.253.07:42:39.45#ibcon#read 6, iclass 36, count 2 2006.253.07:42:39.45#ibcon#end of sib2, iclass 36, count 2 2006.253.07:42:39.45#ibcon#*after write, iclass 36, count 2 2006.253.07:42:39.45#ibcon#*before return 0, iclass 36, count 2 2006.253.07:42:39.45#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.253.07:42:39.45#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.253.07:42:39.45#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.253.07:42:39.45#ibcon#ireg 7 cls_cnt 0 2006.253.07:42:39.45#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.253.07:42:39.57#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.253.07:42:39.57#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.253.07:42:39.57#ibcon#enter wrdev, iclass 36, count 0 2006.253.07:42:39.57#ibcon#first serial, iclass 36, count 0 2006.253.07:42:39.57#ibcon#enter sib2, iclass 36, count 0 2006.253.07:42:39.57#ibcon#flushed, iclass 36, count 0 2006.253.07:42:39.57#ibcon#about to write, iclass 36, count 0 2006.253.07:42:39.57#ibcon#wrote, iclass 36, count 0 2006.253.07:42:39.57#ibcon#about to read 3, iclass 36, count 0 2006.253.07:42:39.59#ibcon#read 3, iclass 36, count 0 2006.253.07:42:39.59#ibcon#about to read 4, iclass 36, count 0 2006.253.07:42:39.59#ibcon#read 4, iclass 36, count 0 2006.253.07:42:39.59#ibcon#about to read 5, iclass 36, count 0 2006.253.07:42:39.59#ibcon#read 5, iclass 36, count 0 2006.253.07:42:39.59#ibcon#about to read 6, iclass 36, count 0 2006.253.07:42:39.59#ibcon#read 6, iclass 36, count 0 2006.253.07:42:39.59#ibcon#end of sib2, iclass 36, count 0 2006.253.07:42:39.59#ibcon#*mode == 0, iclass 36, count 0 2006.253.07:42:39.59#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.253.07:42:39.59#ibcon#[25=USB\r\n] 2006.253.07:42:39.59#ibcon#*before write, iclass 36, count 0 2006.253.07:42:39.59#ibcon#enter sib2, iclass 36, count 0 2006.253.07:42:39.59#ibcon#flushed, iclass 36, count 0 2006.253.07:42:39.59#ibcon#about to write, iclass 36, count 0 2006.253.07:42:39.59#ibcon#wrote, iclass 36, count 0 2006.253.07:42:39.59#ibcon#about to read 3, iclass 36, count 0 2006.253.07:42:39.62#ibcon#read 3, iclass 36, count 0 2006.253.07:42:39.62#ibcon#about to read 4, iclass 36, count 0 2006.253.07:42:39.62#ibcon#read 4, iclass 36, count 0 2006.253.07:42:39.62#ibcon#about to read 5, iclass 36, count 0 2006.253.07:42:39.62#ibcon#read 5, iclass 36, count 0 2006.253.07:42:39.62#ibcon#about to read 6, iclass 36, count 0 2006.253.07:42:39.62#ibcon#read 6, iclass 36, count 0 2006.253.07:42:39.62#ibcon#end of sib2, iclass 36, count 0 2006.253.07:42:39.62#ibcon#*after write, iclass 36, count 0 2006.253.07:42:39.62#ibcon#*before return 0, iclass 36, count 0 2006.253.07:42:39.62#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.253.07:42:39.62#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.253.07:42:39.62#ibcon#about to clear, iclass 36 cls_cnt 0 2006.253.07:42:39.62#ibcon#cleared, iclass 36 cls_cnt 0 2006.253.07:42:39.62$vc4f8/valo=6,772.99 2006.253.07:42:39.62#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.253.07:42:39.62#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.253.07:42:39.62#ibcon#ireg 17 cls_cnt 0 2006.253.07:42:39.62#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.253.07:42:39.62#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.253.07:42:39.62#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.253.07:42:39.62#ibcon#enter wrdev, iclass 38, count 0 2006.253.07:42:39.62#ibcon#first serial, iclass 38, count 0 2006.253.07:42:39.62#ibcon#enter sib2, iclass 38, count 0 2006.253.07:42:39.62#ibcon#flushed, iclass 38, count 0 2006.253.07:42:39.62#ibcon#about to write, iclass 38, count 0 2006.253.07:42:39.62#ibcon#wrote, iclass 38, count 0 2006.253.07:42:39.62#ibcon#about to read 3, iclass 38, count 0 2006.253.07:42:39.64#ibcon#read 3, iclass 38, count 0 2006.253.07:42:39.64#ibcon#about to read 4, iclass 38, count 0 2006.253.07:42:39.64#ibcon#read 4, iclass 38, count 0 2006.253.07:42:39.64#ibcon#about to read 5, iclass 38, count 0 2006.253.07:42:39.64#ibcon#read 5, iclass 38, count 0 2006.253.07:42:39.64#ibcon#about to read 6, iclass 38, count 0 2006.253.07:42:39.64#ibcon#read 6, iclass 38, count 0 2006.253.07:42:39.64#ibcon#end of sib2, iclass 38, count 0 2006.253.07:42:39.64#ibcon#*mode == 0, iclass 38, count 0 2006.253.07:42:39.64#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.253.07:42:39.64#ibcon#[26=FRQ=06,772.99\r\n] 2006.253.07:42:39.64#ibcon#*before write, iclass 38, count 0 2006.253.07:42:39.64#ibcon#enter sib2, iclass 38, count 0 2006.253.07:42:39.64#ibcon#flushed, iclass 38, count 0 2006.253.07:42:39.64#ibcon#about to write, iclass 38, count 0 2006.253.07:42:39.64#ibcon#wrote, iclass 38, count 0 2006.253.07:42:39.64#ibcon#about to read 3, iclass 38, count 0 2006.253.07:42:39.68#ibcon#read 3, iclass 38, count 0 2006.253.07:42:39.68#ibcon#about to read 4, iclass 38, count 0 2006.253.07:42:39.68#ibcon#read 4, iclass 38, count 0 2006.253.07:42:39.68#ibcon#about to read 5, iclass 38, count 0 2006.253.07:42:39.68#ibcon#read 5, iclass 38, count 0 2006.253.07:42:39.68#ibcon#about to read 6, iclass 38, count 0 2006.253.07:42:39.68#ibcon#read 6, iclass 38, count 0 2006.253.07:42:39.68#ibcon#end of sib2, iclass 38, count 0 2006.253.07:42:39.68#ibcon#*after write, iclass 38, count 0 2006.253.07:42:39.68#ibcon#*before return 0, iclass 38, count 0 2006.253.07:42:39.68#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.253.07:42:39.68#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.253.07:42:39.68#ibcon#about to clear, iclass 38 cls_cnt 0 2006.253.07:42:39.68#ibcon#cleared, iclass 38 cls_cnt 0 2006.253.07:42:39.68$vc4f8/va=6,7 2006.253.07:42:39.68#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.253.07:42:39.68#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.253.07:42:39.68#ibcon#ireg 11 cls_cnt 2 2006.253.07:42:39.68#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.253.07:42:39.74#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.253.07:42:39.74#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.253.07:42:39.74#ibcon#enter wrdev, iclass 40, count 2 2006.253.07:42:39.74#ibcon#first serial, iclass 40, count 2 2006.253.07:42:39.74#ibcon#enter sib2, iclass 40, count 2 2006.253.07:42:39.74#ibcon#flushed, iclass 40, count 2 2006.253.07:42:39.74#ibcon#about to write, iclass 40, count 2 2006.253.07:42:39.74#ibcon#wrote, iclass 40, count 2 2006.253.07:42:39.74#ibcon#about to read 3, iclass 40, count 2 2006.253.07:42:39.76#ibcon#read 3, iclass 40, count 2 2006.253.07:42:39.76#ibcon#about to read 4, iclass 40, count 2 2006.253.07:42:39.76#ibcon#read 4, iclass 40, count 2 2006.253.07:42:39.76#ibcon#about to read 5, iclass 40, count 2 2006.253.07:42:39.76#ibcon#read 5, iclass 40, count 2 2006.253.07:42:39.76#ibcon#about to read 6, iclass 40, count 2 2006.253.07:42:39.76#ibcon#read 6, iclass 40, count 2 2006.253.07:42:39.76#ibcon#end of sib2, iclass 40, count 2 2006.253.07:42:39.76#ibcon#*mode == 0, iclass 40, count 2 2006.253.07:42:39.76#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.253.07:42:39.76#ibcon#[25=AT06-07\r\n] 2006.253.07:42:39.76#ibcon#*before write, iclass 40, count 2 2006.253.07:42:39.76#ibcon#enter sib2, iclass 40, count 2 2006.253.07:42:39.76#ibcon#flushed, iclass 40, count 2 2006.253.07:42:39.76#ibcon#about to write, iclass 40, count 2 2006.253.07:42:39.76#ibcon#wrote, iclass 40, count 2 2006.253.07:42:39.76#ibcon#about to read 3, iclass 40, count 2 2006.253.07:42:39.79#ibcon#read 3, iclass 40, count 2 2006.253.07:42:39.79#ibcon#about to read 4, iclass 40, count 2 2006.253.07:42:39.79#ibcon#read 4, iclass 40, count 2 2006.253.07:42:39.79#ibcon#about to read 5, iclass 40, count 2 2006.253.07:42:39.79#ibcon#read 5, iclass 40, count 2 2006.253.07:42:39.79#ibcon#about to read 6, iclass 40, count 2 2006.253.07:42:39.79#ibcon#read 6, iclass 40, count 2 2006.253.07:42:39.79#ibcon#end of sib2, iclass 40, count 2 2006.253.07:42:39.79#ibcon#*after write, iclass 40, count 2 2006.253.07:42:39.79#ibcon#*before return 0, iclass 40, count 2 2006.253.07:42:39.79#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.253.07:42:39.79#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.253.07:42:39.79#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.253.07:42:39.79#ibcon#ireg 7 cls_cnt 0 2006.253.07:42:39.79#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.253.07:42:39.91#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.253.07:42:39.91#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.253.07:42:39.91#ibcon#enter wrdev, iclass 40, count 0 2006.253.07:42:39.91#ibcon#first serial, iclass 40, count 0 2006.253.07:42:39.91#ibcon#enter sib2, iclass 40, count 0 2006.253.07:42:39.91#ibcon#flushed, iclass 40, count 0 2006.253.07:42:39.91#ibcon#about to write, iclass 40, count 0 2006.253.07:42:39.91#ibcon#wrote, iclass 40, count 0 2006.253.07:42:39.91#ibcon#about to read 3, iclass 40, count 0 2006.253.07:42:39.93#ibcon#read 3, iclass 40, count 0 2006.253.07:42:39.93#ibcon#about to read 4, iclass 40, count 0 2006.253.07:42:39.93#ibcon#read 4, iclass 40, count 0 2006.253.07:42:39.93#ibcon#about to read 5, iclass 40, count 0 2006.253.07:42:39.93#ibcon#read 5, iclass 40, count 0 2006.253.07:42:39.93#ibcon#about to read 6, iclass 40, count 0 2006.253.07:42:39.93#ibcon#read 6, iclass 40, count 0 2006.253.07:42:39.93#ibcon#end of sib2, iclass 40, count 0 2006.253.07:42:39.93#ibcon#*mode == 0, iclass 40, count 0 2006.253.07:42:39.93#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.253.07:42:39.93#ibcon#[25=USB\r\n] 2006.253.07:42:39.93#ibcon#*before write, iclass 40, count 0 2006.253.07:42:39.93#ibcon#enter sib2, iclass 40, count 0 2006.253.07:42:39.93#ibcon#flushed, iclass 40, count 0 2006.253.07:42:39.93#ibcon#about to write, iclass 40, count 0 2006.253.07:42:39.93#ibcon#wrote, iclass 40, count 0 2006.253.07:42:39.93#ibcon#about to read 3, iclass 40, count 0 2006.253.07:42:39.96#ibcon#read 3, iclass 40, count 0 2006.253.07:42:39.96#ibcon#about to read 4, iclass 40, count 0 2006.253.07:42:39.96#ibcon#read 4, iclass 40, count 0 2006.253.07:42:39.96#ibcon#about to read 5, iclass 40, count 0 2006.253.07:42:39.96#ibcon#read 5, iclass 40, count 0 2006.253.07:42:39.96#ibcon#about to read 6, iclass 40, count 0 2006.253.07:42:39.96#ibcon#read 6, iclass 40, count 0 2006.253.07:42:39.96#ibcon#end of sib2, iclass 40, count 0 2006.253.07:42:39.96#ibcon#*after write, iclass 40, count 0 2006.253.07:42:39.96#ibcon#*before return 0, iclass 40, count 0 2006.253.07:42:39.96#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.253.07:42:39.96#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.253.07:42:39.96#ibcon#about to clear, iclass 40 cls_cnt 0 2006.253.07:42:39.96#ibcon#cleared, iclass 40 cls_cnt 0 2006.253.07:42:39.96$vc4f8/valo=7,832.99 2006.253.07:42:39.96#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.253.07:42:39.96#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.253.07:42:39.96#ibcon#ireg 17 cls_cnt 0 2006.253.07:42:39.96#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.253.07:42:39.96#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.253.07:42:39.96#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.253.07:42:39.96#ibcon#enter wrdev, iclass 4, count 0 2006.253.07:42:39.96#ibcon#first serial, iclass 4, count 0 2006.253.07:42:39.96#ibcon#enter sib2, iclass 4, count 0 2006.253.07:42:39.96#ibcon#flushed, iclass 4, count 0 2006.253.07:42:39.96#ibcon#about to write, iclass 4, count 0 2006.253.07:42:39.96#ibcon#wrote, iclass 4, count 0 2006.253.07:42:39.96#ibcon#about to read 3, iclass 4, count 0 2006.253.07:42:39.98#ibcon#read 3, iclass 4, count 0 2006.253.07:42:39.98#ibcon#about to read 4, iclass 4, count 0 2006.253.07:42:39.98#ibcon#read 4, iclass 4, count 0 2006.253.07:42:39.98#ibcon#about to read 5, iclass 4, count 0 2006.253.07:42:39.98#ibcon#read 5, iclass 4, count 0 2006.253.07:42:39.98#ibcon#about to read 6, iclass 4, count 0 2006.253.07:42:39.98#ibcon#read 6, iclass 4, count 0 2006.253.07:42:39.98#ibcon#end of sib2, iclass 4, count 0 2006.253.07:42:39.98#ibcon#*mode == 0, iclass 4, count 0 2006.253.07:42:39.98#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.253.07:42:39.98#ibcon#[26=FRQ=07,832.99\r\n] 2006.253.07:42:39.98#ibcon#*before write, iclass 4, count 0 2006.253.07:42:39.98#ibcon#enter sib2, iclass 4, count 0 2006.253.07:42:39.98#ibcon#flushed, iclass 4, count 0 2006.253.07:42:39.98#ibcon#about to write, iclass 4, count 0 2006.253.07:42:39.98#ibcon#wrote, iclass 4, count 0 2006.253.07:42:39.98#ibcon#about to read 3, iclass 4, count 0 2006.253.07:42:40.02#ibcon#read 3, iclass 4, count 0 2006.253.07:42:40.02#ibcon#about to read 4, iclass 4, count 0 2006.253.07:42:40.02#ibcon#read 4, iclass 4, count 0 2006.253.07:42:40.02#ibcon#about to read 5, iclass 4, count 0 2006.253.07:42:40.02#ibcon#read 5, iclass 4, count 0 2006.253.07:42:40.02#ibcon#about to read 6, iclass 4, count 0 2006.253.07:42:40.02#ibcon#read 6, iclass 4, count 0 2006.253.07:42:40.02#ibcon#end of sib2, iclass 4, count 0 2006.253.07:42:40.02#ibcon#*after write, iclass 4, count 0 2006.253.07:42:40.02#ibcon#*before return 0, iclass 4, count 0 2006.253.07:42:40.02#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.253.07:42:40.02#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.253.07:42:40.02#ibcon#about to clear, iclass 4 cls_cnt 0 2006.253.07:42:40.02#ibcon#cleared, iclass 4 cls_cnt 0 2006.253.07:42:40.02$vc4f8/va=7,7 2006.253.07:42:40.02#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.253.07:42:40.02#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.253.07:42:40.02#ibcon#ireg 11 cls_cnt 2 2006.253.07:42:40.02#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.253.07:42:40.08#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.253.07:42:40.08#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.253.07:42:40.08#ibcon#enter wrdev, iclass 6, count 2 2006.253.07:42:40.08#ibcon#first serial, iclass 6, count 2 2006.253.07:42:40.08#ibcon#enter sib2, iclass 6, count 2 2006.253.07:42:40.08#ibcon#flushed, iclass 6, count 2 2006.253.07:42:40.08#ibcon#about to write, iclass 6, count 2 2006.253.07:42:40.08#ibcon#wrote, iclass 6, count 2 2006.253.07:42:40.08#ibcon#about to read 3, iclass 6, count 2 2006.253.07:42:40.10#ibcon#read 3, iclass 6, count 2 2006.253.07:42:40.10#ibcon#about to read 4, iclass 6, count 2 2006.253.07:42:40.10#ibcon#read 4, iclass 6, count 2 2006.253.07:42:40.10#ibcon#about to read 5, iclass 6, count 2 2006.253.07:42:40.10#ibcon#read 5, iclass 6, count 2 2006.253.07:42:40.10#ibcon#about to read 6, iclass 6, count 2 2006.253.07:42:40.10#ibcon#read 6, iclass 6, count 2 2006.253.07:42:40.10#ibcon#end of sib2, iclass 6, count 2 2006.253.07:42:40.10#ibcon#*mode == 0, iclass 6, count 2 2006.253.07:42:40.10#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.253.07:42:40.10#ibcon#[25=AT07-07\r\n] 2006.253.07:42:40.10#ibcon#*before write, iclass 6, count 2 2006.253.07:42:40.10#ibcon#enter sib2, iclass 6, count 2 2006.253.07:42:40.10#ibcon#flushed, iclass 6, count 2 2006.253.07:42:40.10#ibcon#about to write, iclass 6, count 2 2006.253.07:42:40.10#ibcon#wrote, iclass 6, count 2 2006.253.07:42:40.10#ibcon#about to read 3, iclass 6, count 2 2006.253.07:42:40.13#ibcon#read 3, iclass 6, count 2 2006.253.07:42:40.13#ibcon#about to read 4, iclass 6, count 2 2006.253.07:42:40.13#ibcon#read 4, iclass 6, count 2 2006.253.07:42:40.13#ibcon#about to read 5, iclass 6, count 2 2006.253.07:42:40.13#ibcon#read 5, iclass 6, count 2 2006.253.07:42:40.13#ibcon#about to read 6, iclass 6, count 2 2006.253.07:42:40.13#ibcon#read 6, iclass 6, count 2 2006.253.07:42:40.13#ibcon#end of sib2, iclass 6, count 2 2006.253.07:42:40.13#ibcon#*after write, iclass 6, count 2 2006.253.07:42:40.13#ibcon#*before return 0, iclass 6, count 2 2006.253.07:42:40.13#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.253.07:42:40.13#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.253.07:42:40.13#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.253.07:42:40.13#ibcon#ireg 7 cls_cnt 0 2006.253.07:42:40.13#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.253.07:42:40.25#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.253.07:42:40.25#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.253.07:42:40.25#ibcon#enter wrdev, iclass 6, count 0 2006.253.07:42:40.25#ibcon#first serial, iclass 6, count 0 2006.253.07:42:40.25#ibcon#enter sib2, iclass 6, count 0 2006.253.07:42:40.25#ibcon#flushed, iclass 6, count 0 2006.253.07:42:40.25#ibcon#about to write, iclass 6, count 0 2006.253.07:42:40.25#ibcon#wrote, iclass 6, count 0 2006.253.07:42:40.25#ibcon#about to read 3, iclass 6, count 0 2006.253.07:42:40.27#ibcon#read 3, iclass 6, count 0 2006.253.07:42:40.27#ibcon#about to read 4, iclass 6, count 0 2006.253.07:42:40.27#ibcon#read 4, iclass 6, count 0 2006.253.07:42:40.27#ibcon#about to read 5, iclass 6, count 0 2006.253.07:42:40.27#ibcon#read 5, iclass 6, count 0 2006.253.07:42:40.27#ibcon#about to read 6, iclass 6, count 0 2006.253.07:42:40.27#ibcon#read 6, iclass 6, count 0 2006.253.07:42:40.27#ibcon#end of sib2, iclass 6, count 0 2006.253.07:42:40.27#ibcon#*mode == 0, iclass 6, count 0 2006.253.07:42:40.27#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.253.07:42:40.27#ibcon#[25=USB\r\n] 2006.253.07:42:40.27#ibcon#*before write, iclass 6, count 0 2006.253.07:42:40.27#ibcon#enter sib2, iclass 6, count 0 2006.253.07:42:40.27#ibcon#flushed, iclass 6, count 0 2006.253.07:42:40.27#ibcon#about to write, iclass 6, count 0 2006.253.07:42:40.27#ibcon#wrote, iclass 6, count 0 2006.253.07:42:40.27#ibcon#about to read 3, iclass 6, count 0 2006.253.07:42:40.30#ibcon#read 3, iclass 6, count 0 2006.253.07:42:40.30#ibcon#about to read 4, iclass 6, count 0 2006.253.07:42:40.30#ibcon#read 4, iclass 6, count 0 2006.253.07:42:40.30#ibcon#about to read 5, iclass 6, count 0 2006.253.07:42:40.30#ibcon#read 5, iclass 6, count 0 2006.253.07:42:40.30#ibcon#about to read 6, iclass 6, count 0 2006.253.07:42:40.30#ibcon#read 6, iclass 6, count 0 2006.253.07:42:40.30#ibcon#end of sib2, iclass 6, count 0 2006.253.07:42:40.30#ibcon#*after write, iclass 6, count 0 2006.253.07:42:40.30#ibcon#*before return 0, iclass 6, count 0 2006.253.07:42:40.30#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.253.07:42:40.30#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.253.07:42:40.30#ibcon#about to clear, iclass 6 cls_cnt 0 2006.253.07:42:40.30#ibcon#cleared, iclass 6 cls_cnt 0 2006.253.07:42:40.30$vc4f8/valo=8,852.99 2006.253.07:42:40.30#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.253.07:42:40.30#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.253.07:42:40.30#ibcon#ireg 17 cls_cnt 0 2006.253.07:42:40.30#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.253.07:42:40.30#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.253.07:42:40.30#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.253.07:42:40.30#ibcon#enter wrdev, iclass 10, count 0 2006.253.07:42:40.30#ibcon#first serial, iclass 10, count 0 2006.253.07:42:40.30#ibcon#enter sib2, iclass 10, count 0 2006.253.07:42:40.30#ibcon#flushed, iclass 10, count 0 2006.253.07:42:40.30#ibcon#about to write, iclass 10, count 0 2006.253.07:42:40.30#ibcon#wrote, iclass 10, count 0 2006.253.07:42:40.30#ibcon#about to read 3, iclass 10, count 0 2006.253.07:42:40.32#ibcon#read 3, iclass 10, count 0 2006.253.07:42:40.32#ibcon#about to read 4, iclass 10, count 0 2006.253.07:42:40.32#ibcon#read 4, iclass 10, count 0 2006.253.07:42:40.32#ibcon#about to read 5, iclass 10, count 0 2006.253.07:42:40.32#ibcon#read 5, iclass 10, count 0 2006.253.07:42:40.32#ibcon#about to read 6, iclass 10, count 0 2006.253.07:42:40.32#ibcon#read 6, iclass 10, count 0 2006.253.07:42:40.32#ibcon#end of sib2, iclass 10, count 0 2006.253.07:42:40.32#ibcon#*mode == 0, iclass 10, count 0 2006.253.07:42:40.32#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.253.07:42:40.32#ibcon#[26=FRQ=08,852.99\r\n] 2006.253.07:42:40.32#ibcon#*before write, iclass 10, count 0 2006.253.07:42:40.32#ibcon#enter sib2, iclass 10, count 0 2006.253.07:42:40.32#ibcon#flushed, iclass 10, count 0 2006.253.07:42:40.32#ibcon#about to write, iclass 10, count 0 2006.253.07:42:40.32#ibcon#wrote, iclass 10, count 0 2006.253.07:42:40.32#ibcon#about to read 3, iclass 10, count 0 2006.253.07:42:40.36#ibcon#read 3, iclass 10, count 0 2006.253.07:42:40.36#ibcon#about to read 4, iclass 10, count 0 2006.253.07:42:40.36#ibcon#read 4, iclass 10, count 0 2006.253.07:42:40.36#ibcon#about to read 5, iclass 10, count 0 2006.253.07:42:40.36#ibcon#read 5, iclass 10, count 0 2006.253.07:42:40.36#ibcon#about to read 6, iclass 10, count 0 2006.253.07:42:40.36#ibcon#read 6, iclass 10, count 0 2006.253.07:42:40.36#ibcon#end of sib2, iclass 10, count 0 2006.253.07:42:40.36#ibcon#*after write, iclass 10, count 0 2006.253.07:42:40.36#ibcon#*before return 0, iclass 10, count 0 2006.253.07:42:40.36#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.253.07:42:40.36#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.253.07:42:40.36#ibcon#about to clear, iclass 10 cls_cnt 0 2006.253.07:42:40.36#ibcon#cleared, iclass 10 cls_cnt 0 2006.253.07:42:40.36$vc4f8/va=8,7 2006.253.07:42:40.36#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.253.07:42:40.36#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.253.07:42:40.36#ibcon#ireg 11 cls_cnt 2 2006.253.07:42:40.36#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.253.07:42:40.42#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.253.07:42:40.42#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.253.07:42:40.42#ibcon#enter wrdev, iclass 12, count 2 2006.253.07:42:40.42#ibcon#first serial, iclass 12, count 2 2006.253.07:42:40.42#ibcon#enter sib2, iclass 12, count 2 2006.253.07:42:40.42#ibcon#flushed, iclass 12, count 2 2006.253.07:42:40.42#ibcon#about to write, iclass 12, count 2 2006.253.07:42:40.42#ibcon#wrote, iclass 12, count 2 2006.253.07:42:40.42#ibcon#about to read 3, iclass 12, count 2 2006.253.07:42:40.44#ibcon#read 3, iclass 12, count 2 2006.253.07:42:40.44#ibcon#about to read 4, iclass 12, count 2 2006.253.07:42:40.44#ibcon#read 4, iclass 12, count 2 2006.253.07:42:40.44#ibcon#about to read 5, iclass 12, count 2 2006.253.07:42:40.44#ibcon#read 5, iclass 12, count 2 2006.253.07:42:40.44#ibcon#about to read 6, iclass 12, count 2 2006.253.07:42:40.44#ibcon#read 6, iclass 12, count 2 2006.253.07:42:40.44#ibcon#end of sib2, iclass 12, count 2 2006.253.07:42:40.44#ibcon#*mode == 0, iclass 12, count 2 2006.253.07:42:40.44#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.253.07:42:40.44#ibcon#[25=AT08-07\r\n] 2006.253.07:42:40.44#ibcon#*before write, iclass 12, count 2 2006.253.07:42:40.44#ibcon#enter sib2, iclass 12, count 2 2006.253.07:42:40.44#ibcon#flushed, iclass 12, count 2 2006.253.07:42:40.44#ibcon#about to write, iclass 12, count 2 2006.253.07:42:40.44#ibcon#wrote, iclass 12, count 2 2006.253.07:42:40.44#ibcon#about to read 3, iclass 12, count 2 2006.253.07:42:40.47#ibcon#read 3, iclass 12, count 2 2006.253.07:42:40.47#ibcon#about to read 4, iclass 12, count 2 2006.253.07:42:40.47#ibcon#read 4, iclass 12, count 2 2006.253.07:42:40.47#ibcon#about to read 5, iclass 12, count 2 2006.253.07:42:40.47#ibcon#read 5, iclass 12, count 2 2006.253.07:42:40.47#ibcon#about to read 6, iclass 12, count 2 2006.253.07:42:40.47#ibcon#read 6, iclass 12, count 2 2006.253.07:42:40.47#ibcon#end of sib2, iclass 12, count 2 2006.253.07:42:40.47#ibcon#*after write, iclass 12, count 2 2006.253.07:42:40.47#ibcon#*before return 0, iclass 12, count 2 2006.253.07:42:40.47#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.253.07:42:40.47#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.253.07:42:40.47#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.253.07:42:40.47#ibcon#ireg 7 cls_cnt 0 2006.253.07:42:40.47#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.253.07:42:40.59#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.253.07:42:40.59#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.253.07:42:40.59#ibcon#enter wrdev, iclass 12, count 0 2006.253.07:42:40.59#ibcon#first serial, iclass 12, count 0 2006.253.07:42:40.59#ibcon#enter sib2, iclass 12, count 0 2006.253.07:42:40.59#ibcon#flushed, iclass 12, count 0 2006.253.07:42:40.59#ibcon#about to write, iclass 12, count 0 2006.253.07:42:40.59#ibcon#wrote, iclass 12, count 0 2006.253.07:42:40.59#ibcon#about to read 3, iclass 12, count 0 2006.253.07:42:40.61#ibcon#read 3, iclass 12, count 0 2006.253.07:42:40.61#ibcon#about to read 4, iclass 12, count 0 2006.253.07:42:40.61#ibcon#read 4, iclass 12, count 0 2006.253.07:42:40.61#ibcon#about to read 5, iclass 12, count 0 2006.253.07:42:40.61#ibcon#read 5, iclass 12, count 0 2006.253.07:42:40.61#ibcon#about to read 6, iclass 12, count 0 2006.253.07:42:40.61#ibcon#read 6, iclass 12, count 0 2006.253.07:42:40.61#ibcon#end of sib2, iclass 12, count 0 2006.253.07:42:40.61#ibcon#*mode == 0, iclass 12, count 0 2006.253.07:42:40.61#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.253.07:42:40.61#ibcon#[25=USB\r\n] 2006.253.07:42:40.61#ibcon#*before write, iclass 12, count 0 2006.253.07:42:40.61#ibcon#enter sib2, iclass 12, count 0 2006.253.07:42:40.61#ibcon#flushed, iclass 12, count 0 2006.253.07:42:40.61#ibcon#about to write, iclass 12, count 0 2006.253.07:42:40.61#ibcon#wrote, iclass 12, count 0 2006.253.07:42:40.61#ibcon#about to read 3, iclass 12, count 0 2006.253.07:42:40.64#ibcon#read 3, iclass 12, count 0 2006.253.07:42:40.64#ibcon#about to read 4, iclass 12, count 0 2006.253.07:42:40.64#ibcon#read 4, iclass 12, count 0 2006.253.07:42:40.64#ibcon#about to read 5, iclass 12, count 0 2006.253.07:42:40.64#ibcon#read 5, iclass 12, count 0 2006.253.07:42:40.64#ibcon#about to read 6, iclass 12, count 0 2006.253.07:42:40.64#ibcon#read 6, iclass 12, count 0 2006.253.07:42:40.64#ibcon#end of sib2, iclass 12, count 0 2006.253.07:42:40.64#ibcon#*after write, iclass 12, count 0 2006.253.07:42:40.64#ibcon#*before return 0, iclass 12, count 0 2006.253.07:42:40.64#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.253.07:42:40.64#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.253.07:42:40.64#ibcon#about to clear, iclass 12 cls_cnt 0 2006.253.07:42:40.64#ibcon#cleared, iclass 12 cls_cnt 0 2006.253.07:42:40.64$vc4f8/vblo=1,632.99 2006.253.07:42:40.64#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.253.07:42:40.64#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.253.07:42:40.64#ibcon#ireg 17 cls_cnt 0 2006.253.07:42:40.64#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.253.07:42:40.64#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.253.07:42:40.64#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.253.07:42:40.64#ibcon#enter wrdev, iclass 14, count 0 2006.253.07:42:40.64#ibcon#first serial, iclass 14, count 0 2006.253.07:42:40.64#ibcon#enter sib2, iclass 14, count 0 2006.253.07:42:40.64#ibcon#flushed, iclass 14, count 0 2006.253.07:42:40.64#ibcon#about to write, iclass 14, count 0 2006.253.07:42:40.64#ibcon#wrote, iclass 14, count 0 2006.253.07:42:40.64#ibcon#about to read 3, iclass 14, count 0 2006.253.07:42:40.66#ibcon#read 3, iclass 14, count 0 2006.253.07:42:40.66#ibcon#about to read 4, iclass 14, count 0 2006.253.07:42:40.66#ibcon#read 4, iclass 14, count 0 2006.253.07:42:40.66#ibcon#about to read 5, iclass 14, count 0 2006.253.07:42:40.66#ibcon#read 5, iclass 14, count 0 2006.253.07:42:40.66#ibcon#about to read 6, iclass 14, count 0 2006.253.07:42:40.66#ibcon#read 6, iclass 14, count 0 2006.253.07:42:40.66#ibcon#end of sib2, iclass 14, count 0 2006.253.07:42:40.66#ibcon#*mode == 0, iclass 14, count 0 2006.253.07:42:40.66#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.253.07:42:40.66#ibcon#[28=FRQ=01,632.99\r\n] 2006.253.07:42:40.66#ibcon#*before write, iclass 14, count 0 2006.253.07:42:40.66#ibcon#enter sib2, iclass 14, count 0 2006.253.07:42:40.66#ibcon#flushed, iclass 14, count 0 2006.253.07:42:40.66#ibcon#about to write, iclass 14, count 0 2006.253.07:42:40.66#ibcon#wrote, iclass 14, count 0 2006.253.07:42:40.66#ibcon#about to read 3, iclass 14, count 0 2006.253.07:42:40.71#ibcon#read 3, iclass 14, count 0 2006.253.07:42:40.71#ibcon#about to read 4, iclass 14, count 0 2006.253.07:42:40.71#ibcon#read 4, iclass 14, count 0 2006.253.07:42:40.71#ibcon#about to read 5, iclass 14, count 0 2006.253.07:42:40.71#ibcon#read 5, iclass 14, count 0 2006.253.07:42:40.71#ibcon#about to read 6, iclass 14, count 0 2006.253.07:42:40.71#ibcon#read 6, iclass 14, count 0 2006.253.07:42:40.71#ibcon#end of sib2, iclass 14, count 0 2006.253.07:42:40.71#ibcon#*after write, iclass 14, count 0 2006.253.07:42:40.71#ibcon#*before return 0, iclass 14, count 0 2006.253.07:42:40.71#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.253.07:42:40.71#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.253.07:42:40.71#ibcon#about to clear, iclass 14 cls_cnt 0 2006.253.07:42:40.71#ibcon#cleared, iclass 14 cls_cnt 0 2006.253.07:42:40.71$vc4f8/vb=1,4 2006.253.07:42:40.71#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.253.07:42:40.71#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.253.07:42:40.71#ibcon#ireg 11 cls_cnt 2 2006.253.07:42:40.71#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.253.07:42:40.71#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.253.07:42:40.71#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.253.07:42:40.71#ibcon#enter wrdev, iclass 16, count 2 2006.253.07:42:40.71#ibcon#first serial, iclass 16, count 2 2006.253.07:42:40.71#ibcon#enter sib2, iclass 16, count 2 2006.253.07:42:40.71#ibcon#flushed, iclass 16, count 2 2006.253.07:42:40.71#ibcon#about to write, iclass 16, count 2 2006.253.07:42:40.71#ibcon#wrote, iclass 16, count 2 2006.253.07:42:40.71#ibcon#about to read 3, iclass 16, count 2 2006.253.07:42:40.73#ibcon#read 3, iclass 16, count 2 2006.253.07:42:40.73#ibcon#about to read 4, iclass 16, count 2 2006.253.07:42:40.73#ibcon#read 4, iclass 16, count 2 2006.253.07:42:40.73#ibcon#about to read 5, iclass 16, count 2 2006.253.07:42:40.73#ibcon#read 5, iclass 16, count 2 2006.253.07:42:40.73#ibcon#about to read 6, iclass 16, count 2 2006.253.07:42:40.73#ibcon#read 6, iclass 16, count 2 2006.253.07:42:40.73#ibcon#end of sib2, iclass 16, count 2 2006.253.07:42:40.73#ibcon#*mode == 0, iclass 16, count 2 2006.253.07:42:40.73#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.253.07:42:40.73#ibcon#[27=AT01-04\r\n] 2006.253.07:42:40.73#ibcon#*before write, iclass 16, count 2 2006.253.07:42:40.73#ibcon#enter sib2, iclass 16, count 2 2006.253.07:42:40.73#ibcon#flushed, iclass 16, count 2 2006.253.07:42:40.73#ibcon#about to write, iclass 16, count 2 2006.253.07:42:40.73#ibcon#wrote, iclass 16, count 2 2006.253.07:42:40.73#ibcon#about to read 3, iclass 16, count 2 2006.253.07:42:40.76#ibcon#read 3, iclass 16, count 2 2006.253.07:42:40.76#ibcon#about to read 4, iclass 16, count 2 2006.253.07:42:40.76#ibcon#read 4, iclass 16, count 2 2006.253.07:42:40.76#ibcon#about to read 5, iclass 16, count 2 2006.253.07:42:40.76#ibcon#read 5, iclass 16, count 2 2006.253.07:42:40.76#ibcon#about to read 6, iclass 16, count 2 2006.253.07:42:40.76#ibcon#read 6, iclass 16, count 2 2006.253.07:42:40.76#ibcon#end of sib2, iclass 16, count 2 2006.253.07:42:40.76#ibcon#*after write, iclass 16, count 2 2006.253.07:42:40.76#ibcon#*before return 0, iclass 16, count 2 2006.253.07:42:40.76#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.253.07:42:40.76#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.253.07:42:40.76#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.253.07:42:40.76#ibcon#ireg 7 cls_cnt 0 2006.253.07:42:40.76#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.253.07:42:40.88#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.253.07:42:40.88#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.253.07:42:40.88#ibcon#enter wrdev, iclass 16, count 0 2006.253.07:42:40.88#ibcon#first serial, iclass 16, count 0 2006.253.07:42:40.88#ibcon#enter sib2, iclass 16, count 0 2006.253.07:42:40.88#ibcon#flushed, iclass 16, count 0 2006.253.07:42:40.88#ibcon#about to write, iclass 16, count 0 2006.253.07:42:40.88#ibcon#wrote, iclass 16, count 0 2006.253.07:42:40.88#ibcon#about to read 3, iclass 16, count 0 2006.253.07:42:40.90#ibcon#read 3, iclass 16, count 0 2006.253.07:42:40.90#ibcon#about to read 4, iclass 16, count 0 2006.253.07:42:40.90#ibcon#read 4, iclass 16, count 0 2006.253.07:42:40.90#ibcon#about to read 5, iclass 16, count 0 2006.253.07:42:40.90#ibcon#read 5, iclass 16, count 0 2006.253.07:42:40.90#ibcon#about to read 6, iclass 16, count 0 2006.253.07:42:40.90#ibcon#read 6, iclass 16, count 0 2006.253.07:42:40.90#ibcon#end of sib2, iclass 16, count 0 2006.253.07:42:40.90#ibcon#*mode == 0, iclass 16, count 0 2006.253.07:42:40.90#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.253.07:42:40.90#ibcon#[27=USB\r\n] 2006.253.07:42:40.90#ibcon#*before write, iclass 16, count 0 2006.253.07:42:40.90#ibcon#enter sib2, iclass 16, count 0 2006.253.07:42:40.90#ibcon#flushed, iclass 16, count 0 2006.253.07:42:40.90#ibcon#about to write, iclass 16, count 0 2006.253.07:42:40.90#ibcon#wrote, iclass 16, count 0 2006.253.07:42:40.90#ibcon#about to read 3, iclass 16, count 0 2006.253.07:42:40.93#ibcon#read 3, iclass 16, count 0 2006.253.07:42:40.93#ibcon#about to read 4, iclass 16, count 0 2006.253.07:42:40.93#ibcon#read 4, iclass 16, count 0 2006.253.07:42:40.93#ibcon#about to read 5, iclass 16, count 0 2006.253.07:42:40.93#ibcon#read 5, iclass 16, count 0 2006.253.07:42:40.93#ibcon#about to read 6, iclass 16, count 0 2006.253.07:42:40.93#ibcon#read 6, iclass 16, count 0 2006.253.07:42:40.93#ibcon#end of sib2, iclass 16, count 0 2006.253.07:42:40.93#ibcon#*after write, iclass 16, count 0 2006.253.07:42:40.93#ibcon#*before return 0, iclass 16, count 0 2006.253.07:42:40.93#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.253.07:42:40.93#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.253.07:42:40.93#ibcon#about to clear, iclass 16 cls_cnt 0 2006.253.07:42:40.93#ibcon#cleared, iclass 16 cls_cnt 0 2006.253.07:42:40.93$vc4f8/vblo=2,640.99 2006.253.07:42:40.93#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.253.07:42:40.93#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.253.07:42:40.93#ibcon#ireg 17 cls_cnt 0 2006.253.07:42:40.93#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.253.07:42:40.93#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.253.07:42:40.93#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.253.07:42:40.93#ibcon#enter wrdev, iclass 18, count 0 2006.253.07:42:40.93#ibcon#first serial, iclass 18, count 0 2006.253.07:42:40.93#ibcon#enter sib2, iclass 18, count 0 2006.253.07:42:40.93#ibcon#flushed, iclass 18, count 0 2006.253.07:42:40.93#ibcon#about to write, iclass 18, count 0 2006.253.07:42:40.93#ibcon#wrote, iclass 18, count 0 2006.253.07:42:40.93#ibcon#about to read 3, iclass 18, count 0 2006.253.07:42:40.95#ibcon#read 3, iclass 18, count 0 2006.253.07:42:40.95#ibcon#about to read 4, iclass 18, count 0 2006.253.07:42:40.95#ibcon#read 4, iclass 18, count 0 2006.253.07:42:40.95#ibcon#about to read 5, iclass 18, count 0 2006.253.07:42:40.95#ibcon#read 5, iclass 18, count 0 2006.253.07:42:40.95#ibcon#about to read 6, iclass 18, count 0 2006.253.07:42:40.95#ibcon#read 6, iclass 18, count 0 2006.253.07:42:40.95#ibcon#end of sib2, iclass 18, count 0 2006.253.07:42:40.95#ibcon#*mode == 0, iclass 18, count 0 2006.253.07:42:40.95#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.253.07:42:40.95#ibcon#[28=FRQ=02,640.99\r\n] 2006.253.07:42:40.95#ibcon#*before write, iclass 18, count 0 2006.253.07:42:40.95#ibcon#enter sib2, iclass 18, count 0 2006.253.07:42:40.95#ibcon#flushed, iclass 18, count 0 2006.253.07:42:40.95#ibcon#about to write, iclass 18, count 0 2006.253.07:42:40.95#ibcon#wrote, iclass 18, count 0 2006.253.07:42:40.95#ibcon#about to read 3, iclass 18, count 0 2006.253.07:42:40.99#ibcon#read 3, iclass 18, count 0 2006.253.07:42:40.99#ibcon#about to read 4, iclass 18, count 0 2006.253.07:42:40.99#ibcon#read 4, iclass 18, count 0 2006.253.07:42:40.99#ibcon#about to read 5, iclass 18, count 0 2006.253.07:42:40.99#ibcon#read 5, iclass 18, count 0 2006.253.07:42:40.99#ibcon#about to read 6, iclass 18, count 0 2006.253.07:42:40.99#ibcon#read 6, iclass 18, count 0 2006.253.07:42:40.99#ibcon#end of sib2, iclass 18, count 0 2006.253.07:42:40.99#ibcon#*after write, iclass 18, count 0 2006.253.07:42:40.99#ibcon#*before return 0, iclass 18, count 0 2006.253.07:42:40.99#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.253.07:42:40.99#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.253.07:42:40.99#ibcon#about to clear, iclass 18 cls_cnt 0 2006.253.07:42:40.99#ibcon#cleared, iclass 18 cls_cnt 0 2006.253.07:42:40.99$vc4f8/vb=2,5 2006.253.07:42:40.99#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.253.07:42:40.99#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.253.07:42:40.99#ibcon#ireg 11 cls_cnt 2 2006.253.07:42:40.99#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.253.07:42:41.05#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.253.07:42:41.05#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.253.07:42:41.05#ibcon#enter wrdev, iclass 20, count 2 2006.253.07:42:41.05#ibcon#first serial, iclass 20, count 2 2006.253.07:42:41.05#ibcon#enter sib2, iclass 20, count 2 2006.253.07:42:41.05#ibcon#flushed, iclass 20, count 2 2006.253.07:42:41.05#ibcon#about to write, iclass 20, count 2 2006.253.07:42:41.05#ibcon#wrote, iclass 20, count 2 2006.253.07:42:41.05#ibcon#about to read 3, iclass 20, count 2 2006.253.07:42:41.07#ibcon#read 3, iclass 20, count 2 2006.253.07:42:41.07#ibcon#about to read 4, iclass 20, count 2 2006.253.07:42:41.07#ibcon#read 4, iclass 20, count 2 2006.253.07:42:41.07#ibcon#about to read 5, iclass 20, count 2 2006.253.07:42:41.07#ibcon#read 5, iclass 20, count 2 2006.253.07:42:41.07#ibcon#about to read 6, iclass 20, count 2 2006.253.07:42:41.07#ibcon#read 6, iclass 20, count 2 2006.253.07:42:41.07#ibcon#end of sib2, iclass 20, count 2 2006.253.07:42:41.07#ibcon#*mode == 0, iclass 20, count 2 2006.253.07:42:41.07#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.253.07:42:41.07#ibcon#[27=AT02-05\r\n] 2006.253.07:42:41.07#ibcon#*before write, iclass 20, count 2 2006.253.07:42:41.07#ibcon#enter sib2, iclass 20, count 2 2006.253.07:42:41.07#ibcon#flushed, iclass 20, count 2 2006.253.07:42:41.07#ibcon#about to write, iclass 20, count 2 2006.253.07:42:41.07#ibcon#wrote, iclass 20, count 2 2006.253.07:42:41.07#ibcon#about to read 3, iclass 20, count 2 2006.253.07:42:41.10#ibcon#read 3, iclass 20, count 2 2006.253.07:42:41.10#ibcon#about to read 4, iclass 20, count 2 2006.253.07:42:41.10#ibcon#read 4, iclass 20, count 2 2006.253.07:42:41.10#ibcon#about to read 5, iclass 20, count 2 2006.253.07:42:41.10#ibcon#read 5, iclass 20, count 2 2006.253.07:42:41.10#ibcon#about to read 6, iclass 20, count 2 2006.253.07:42:41.10#ibcon#read 6, iclass 20, count 2 2006.253.07:42:41.10#ibcon#end of sib2, iclass 20, count 2 2006.253.07:42:41.10#ibcon#*after write, iclass 20, count 2 2006.253.07:42:41.10#ibcon#*before return 0, iclass 20, count 2 2006.253.07:42:41.10#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.253.07:42:41.10#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.253.07:42:41.10#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.253.07:42:41.10#ibcon#ireg 7 cls_cnt 0 2006.253.07:42:41.10#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.253.07:42:41.22#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.253.07:42:41.22#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.253.07:42:41.22#ibcon#enter wrdev, iclass 20, count 0 2006.253.07:42:41.22#ibcon#first serial, iclass 20, count 0 2006.253.07:42:41.22#ibcon#enter sib2, iclass 20, count 0 2006.253.07:42:41.22#ibcon#flushed, iclass 20, count 0 2006.253.07:42:41.22#ibcon#about to write, iclass 20, count 0 2006.253.07:42:41.22#ibcon#wrote, iclass 20, count 0 2006.253.07:42:41.22#ibcon#about to read 3, iclass 20, count 0 2006.253.07:42:41.24#ibcon#read 3, iclass 20, count 0 2006.253.07:42:41.24#ibcon#about to read 4, iclass 20, count 0 2006.253.07:42:41.24#ibcon#read 4, iclass 20, count 0 2006.253.07:42:41.24#ibcon#about to read 5, iclass 20, count 0 2006.253.07:42:41.24#ibcon#read 5, iclass 20, count 0 2006.253.07:42:41.24#ibcon#about to read 6, iclass 20, count 0 2006.253.07:42:41.24#ibcon#read 6, iclass 20, count 0 2006.253.07:42:41.24#ibcon#end of sib2, iclass 20, count 0 2006.253.07:42:41.24#ibcon#*mode == 0, iclass 20, count 0 2006.253.07:42:41.24#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.253.07:42:41.24#ibcon#[27=USB\r\n] 2006.253.07:42:41.24#ibcon#*before write, iclass 20, count 0 2006.253.07:42:41.24#ibcon#enter sib2, iclass 20, count 0 2006.253.07:42:41.24#ibcon#flushed, iclass 20, count 0 2006.253.07:42:41.24#ibcon#about to write, iclass 20, count 0 2006.253.07:42:41.24#ibcon#wrote, iclass 20, count 0 2006.253.07:42:41.24#ibcon#about to read 3, iclass 20, count 0 2006.253.07:42:41.27#ibcon#read 3, iclass 20, count 0 2006.253.07:42:41.27#ibcon#about to read 4, iclass 20, count 0 2006.253.07:42:41.27#ibcon#read 4, iclass 20, count 0 2006.253.07:42:41.27#ibcon#about to read 5, iclass 20, count 0 2006.253.07:42:41.27#ibcon#read 5, iclass 20, count 0 2006.253.07:42:41.27#ibcon#about to read 6, iclass 20, count 0 2006.253.07:42:41.27#ibcon#read 6, iclass 20, count 0 2006.253.07:42:41.27#ibcon#end of sib2, iclass 20, count 0 2006.253.07:42:41.27#ibcon#*after write, iclass 20, count 0 2006.253.07:42:41.27#ibcon#*before return 0, iclass 20, count 0 2006.253.07:42:41.27#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.253.07:42:41.27#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.253.07:42:41.27#ibcon#about to clear, iclass 20 cls_cnt 0 2006.253.07:42:41.27#ibcon#cleared, iclass 20 cls_cnt 0 2006.253.07:42:41.27$vc4f8/vblo=3,656.99 2006.253.07:42:41.27#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.253.07:42:41.27#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.253.07:42:41.27#ibcon#ireg 17 cls_cnt 0 2006.253.07:42:41.27#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.253.07:42:41.27#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.253.07:42:41.27#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.253.07:42:41.27#ibcon#enter wrdev, iclass 22, count 0 2006.253.07:42:41.27#ibcon#first serial, iclass 22, count 0 2006.253.07:42:41.27#ibcon#enter sib2, iclass 22, count 0 2006.253.07:42:41.27#ibcon#flushed, iclass 22, count 0 2006.253.07:42:41.27#ibcon#about to write, iclass 22, count 0 2006.253.07:42:41.27#ibcon#wrote, iclass 22, count 0 2006.253.07:42:41.27#ibcon#about to read 3, iclass 22, count 0 2006.253.07:42:41.29#ibcon#read 3, iclass 22, count 0 2006.253.07:42:41.29#ibcon#about to read 4, iclass 22, count 0 2006.253.07:42:41.29#ibcon#read 4, iclass 22, count 0 2006.253.07:42:41.29#ibcon#about to read 5, iclass 22, count 0 2006.253.07:42:41.29#ibcon#read 5, iclass 22, count 0 2006.253.07:42:41.29#ibcon#about to read 6, iclass 22, count 0 2006.253.07:42:41.29#ibcon#read 6, iclass 22, count 0 2006.253.07:42:41.29#ibcon#end of sib2, iclass 22, count 0 2006.253.07:42:41.29#ibcon#*mode == 0, iclass 22, count 0 2006.253.07:42:41.29#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.253.07:42:41.29#ibcon#[28=FRQ=03,656.99\r\n] 2006.253.07:42:41.29#ibcon#*before write, iclass 22, count 0 2006.253.07:42:41.29#ibcon#enter sib2, iclass 22, count 0 2006.253.07:42:41.29#ibcon#flushed, iclass 22, count 0 2006.253.07:42:41.29#ibcon#about to write, iclass 22, count 0 2006.253.07:42:41.29#ibcon#wrote, iclass 22, count 0 2006.253.07:42:41.29#ibcon#about to read 3, iclass 22, count 0 2006.253.07:42:41.33#ibcon#read 3, iclass 22, count 0 2006.253.07:42:41.33#ibcon#about to read 4, iclass 22, count 0 2006.253.07:42:41.33#ibcon#read 4, iclass 22, count 0 2006.253.07:42:41.33#ibcon#about to read 5, iclass 22, count 0 2006.253.07:42:41.33#ibcon#read 5, iclass 22, count 0 2006.253.07:42:41.33#ibcon#about to read 6, iclass 22, count 0 2006.253.07:42:41.33#ibcon#read 6, iclass 22, count 0 2006.253.07:42:41.33#ibcon#end of sib2, iclass 22, count 0 2006.253.07:42:41.33#ibcon#*after write, iclass 22, count 0 2006.253.07:42:41.33#ibcon#*before return 0, iclass 22, count 0 2006.253.07:42:41.33#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.253.07:42:41.33#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.253.07:42:41.33#ibcon#about to clear, iclass 22 cls_cnt 0 2006.253.07:42:41.33#ibcon#cleared, iclass 22 cls_cnt 0 2006.253.07:42:41.33$vc4f8/vb=3,4 2006.253.07:42:41.33#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.253.07:42:41.33#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.253.07:42:41.33#ibcon#ireg 11 cls_cnt 2 2006.253.07:42:41.33#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.253.07:42:41.39#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.253.07:42:41.39#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.253.07:42:41.39#ibcon#enter wrdev, iclass 24, count 2 2006.253.07:42:41.39#ibcon#first serial, iclass 24, count 2 2006.253.07:42:41.39#ibcon#enter sib2, iclass 24, count 2 2006.253.07:42:41.39#ibcon#flushed, iclass 24, count 2 2006.253.07:42:41.39#ibcon#about to write, iclass 24, count 2 2006.253.07:42:41.39#ibcon#wrote, iclass 24, count 2 2006.253.07:42:41.39#ibcon#about to read 3, iclass 24, count 2 2006.253.07:42:41.41#ibcon#read 3, iclass 24, count 2 2006.253.07:42:41.41#ibcon#about to read 4, iclass 24, count 2 2006.253.07:42:41.41#ibcon#read 4, iclass 24, count 2 2006.253.07:42:41.41#ibcon#about to read 5, iclass 24, count 2 2006.253.07:42:41.41#ibcon#read 5, iclass 24, count 2 2006.253.07:42:41.41#ibcon#about to read 6, iclass 24, count 2 2006.253.07:42:41.41#ibcon#read 6, iclass 24, count 2 2006.253.07:42:41.41#ibcon#end of sib2, iclass 24, count 2 2006.253.07:42:41.41#ibcon#*mode == 0, iclass 24, count 2 2006.253.07:42:41.41#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.253.07:42:41.41#ibcon#[27=AT03-04\r\n] 2006.253.07:42:41.41#ibcon#*before write, iclass 24, count 2 2006.253.07:42:41.41#ibcon#enter sib2, iclass 24, count 2 2006.253.07:42:41.41#ibcon#flushed, iclass 24, count 2 2006.253.07:42:41.41#ibcon#about to write, iclass 24, count 2 2006.253.07:42:41.41#ibcon#wrote, iclass 24, count 2 2006.253.07:42:41.41#ibcon#about to read 3, iclass 24, count 2 2006.253.07:42:41.44#ibcon#read 3, iclass 24, count 2 2006.253.07:42:41.44#ibcon#about to read 4, iclass 24, count 2 2006.253.07:42:41.44#ibcon#read 4, iclass 24, count 2 2006.253.07:42:41.44#ibcon#about to read 5, iclass 24, count 2 2006.253.07:42:41.44#ibcon#read 5, iclass 24, count 2 2006.253.07:42:41.44#ibcon#about to read 6, iclass 24, count 2 2006.253.07:42:41.44#ibcon#read 6, iclass 24, count 2 2006.253.07:42:41.44#ibcon#end of sib2, iclass 24, count 2 2006.253.07:42:41.44#ibcon#*after write, iclass 24, count 2 2006.253.07:42:41.44#ibcon#*before return 0, iclass 24, count 2 2006.253.07:42:41.44#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.253.07:42:41.44#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.253.07:42:41.44#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.253.07:42:41.44#ibcon#ireg 7 cls_cnt 0 2006.253.07:42:41.44#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.253.07:42:41.56#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.253.07:42:41.56#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.253.07:42:41.56#ibcon#enter wrdev, iclass 24, count 0 2006.253.07:42:41.56#ibcon#first serial, iclass 24, count 0 2006.253.07:42:41.56#ibcon#enter sib2, iclass 24, count 0 2006.253.07:42:41.56#ibcon#flushed, iclass 24, count 0 2006.253.07:42:41.56#ibcon#about to write, iclass 24, count 0 2006.253.07:42:41.56#ibcon#wrote, iclass 24, count 0 2006.253.07:42:41.56#ibcon#about to read 3, iclass 24, count 0 2006.253.07:42:41.58#ibcon#read 3, iclass 24, count 0 2006.253.07:42:41.58#ibcon#about to read 4, iclass 24, count 0 2006.253.07:42:41.58#ibcon#read 4, iclass 24, count 0 2006.253.07:42:41.58#ibcon#about to read 5, iclass 24, count 0 2006.253.07:42:41.58#ibcon#read 5, iclass 24, count 0 2006.253.07:42:41.58#ibcon#about to read 6, iclass 24, count 0 2006.253.07:42:41.58#ibcon#read 6, iclass 24, count 0 2006.253.07:42:41.58#ibcon#end of sib2, iclass 24, count 0 2006.253.07:42:41.58#ibcon#*mode == 0, iclass 24, count 0 2006.253.07:42:41.58#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.253.07:42:41.58#ibcon#[27=USB\r\n] 2006.253.07:42:41.58#ibcon#*before write, iclass 24, count 0 2006.253.07:42:41.58#ibcon#enter sib2, iclass 24, count 0 2006.253.07:42:41.58#ibcon#flushed, iclass 24, count 0 2006.253.07:42:41.58#ibcon#about to write, iclass 24, count 0 2006.253.07:42:41.58#ibcon#wrote, iclass 24, count 0 2006.253.07:42:41.58#ibcon#about to read 3, iclass 24, count 0 2006.253.07:42:41.61#ibcon#read 3, iclass 24, count 0 2006.253.07:42:41.61#ibcon#about to read 4, iclass 24, count 0 2006.253.07:42:41.61#ibcon#read 4, iclass 24, count 0 2006.253.07:42:41.61#ibcon#about to read 5, iclass 24, count 0 2006.253.07:42:41.61#ibcon#read 5, iclass 24, count 0 2006.253.07:42:41.61#ibcon#about to read 6, iclass 24, count 0 2006.253.07:42:41.61#ibcon#read 6, iclass 24, count 0 2006.253.07:42:41.61#ibcon#end of sib2, iclass 24, count 0 2006.253.07:42:41.61#ibcon#*after write, iclass 24, count 0 2006.253.07:42:41.61#ibcon#*before return 0, iclass 24, count 0 2006.253.07:42:41.61#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.253.07:42:41.61#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.253.07:42:41.61#ibcon#about to clear, iclass 24 cls_cnt 0 2006.253.07:42:41.61#ibcon#cleared, iclass 24 cls_cnt 0 2006.253.07:42:41.61$vc4f8/vblo=4,712.99 2006.253.07:42:41.61#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.253.07:42:41.61#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.253.07:42:41.61#ibcon#ireg 17 cls_cnt 0 2006.253.07:42:41.61#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.253.07:42:41.61#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.253.07:42:41.61#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.253.07:42:41.61#ibcon#enter wrdev, iclass 26, count 0 2006.253.07:42:41.61#ibcon#first serial, iclass 26, count 0 2006.253.07:42:41.61#ibcon#enter sib2, iclass 26, count 0 2006.253.07:42:41.61#ibcon#flushed, iclass 26, count 0 2006.253.07:42:41.61#ibcon#about to write, iclass 26, count 0 2006.253.07:42:41.61#ibcon#wrote, iclass 26, count 0 2006.253.07:42:41.61#ibcon#about to read 3, iclass 26, count 0 2006.253.07:42:41.63#ibcon#read 3, iclass 26, count 0 2006.253.07:42:41.63#ibcon#about to read 4, iclass 26, count 0 2006.253.07:42:41.63#ibcon#read 4, iclass 26, count 0 2006.253.07:42:41.63#ibcon#about to read 5, iclass 26, count 0 2006.253.07:42:41.63#ibcon#read 5, iclass 26, count 0 2006.253.07:42:41.63#ibcon#about to read 6, iclass 26, count 0 2006.253.07:42:41.63#ibcon#read 6, iclass 26, count 0 2006.253.07:42:41.63#ibcon#end of sib2, iclass 26, count 0 2006.253.07:42:41.63#ibcon#*mode == 0, iclass 26, count 0 2006.253.07:42:41.63#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.253.07:42:41.63#ibcon#[28=FRQ=04,712.99\r\n] 2006.253.07:42:41.63#ibcon#*before write, iclass 26, count 0 2006.253.07:42:41.63#ibcon#enter sib2, iclass 26, count 0 2006.253.07:42:41.63#ibcon#flushed, iclass 26, count 0 2006.253.07:42:41.63#ibcon#about to write, iclass 26, count 0 2006.253.07:42:41.63#ibcon#wrote, iclass 26, count 0 2006.253.07:42:41.63#ibcon#about to read 3, iclass 26, count 0 2006.253.07:42:41.67#ibcon#read 3, iclass 26, count 0 2006.253.07:42:41.67#ibcon#about to read 4, iclass 26, count 0 2006.253.07:42:41.67#ibcon#read 4, iclass 26, count 0 2006.253.07:42:41.67#ibcon#about to read 5, iclass 26, count 0 2006.253.07:42:41.67#ibcon#read 5, iclass 26, count 0 2006.253.07:42:41.67#ibcon#about to read 6, iclass 26, count 0 2006.253.07:42:41.67#ibcon#read 6, iclass 26, count 0 2006.253.07:42:41.67#ibcon#end of sib2, iclass 26, count 0 2006.253.07:42:41.67#ibcon#*after write, iclass 26, count 0 2006.253.07:42:41.67#ibcon#*before return 0, iclass 26, count 0 2006.253.07:42:41.67#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.253.07:42:41.67#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.253.07:42:41.67#ibcon#about to clear, iclass 26 cls_cnt 0 2006.253.07:42:41.67#ibcon#cleared, iclass 26 cls_cnt 0 2006.253.07:42:41.67$vc4f8/vb=4,4 2006.253.07:42:41.67#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.253.07:42:41.67#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.253.07:42:41.67#ibcon#ireg 11 cls_cnt 2 2006.253.07:42:41.67#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.253.07:42:41.73#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.253.07:42:41.73#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.253.07:42:41.73#ibcon#enter wrdev, iclass 28, count 2 2006.253.07:42:41.73#ibcon#first serial, iclass 28, count 2 2006.253.07:42:41.73#ibcon#enter sib2, iclass 28, count 2 2006.253.07:42:41.73#ibcon#flushed, iclass 28, count 2 2006.253.07:42:41.73#ibcon#about to write, iclass 28, count 2 2006.253.07:42:41.73#ibcon#wrote, iclass 28, count 2 2006.253.07:42:41.73#ibcon#about to read 3, iclass 28, count 2 2006.253.07:42:41.75#ibcon#read 3, iclass 28, count 2 2006.253.07:42:41.75#ibcon#about to read 4, iclass 28, count 2 2006.253.07:42:41.75#ibcon#read 4, iclass 28, count 2 2006.253.07:42:41.75#ibcon#about to read 5, iclass 28, count 2 2006.253.07:42:41.75#ibcon#read 5, iclass 28, count 2 2006.253.07:42:41.75#ibcon#about to read 6, iclass 28, count 2 2006.253.07:42:41.75#ibcon#read 6, iclass 28, count 2 2006.253.07:42:41.75#ibcon#end of sib2, iclass 28, count 2 2006.253.07:42:41.75#ibcon#*mode == 0, iclass 28, count 2 2006.253.07:42:41.75#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.253.07:42:41.75#ibcon#[27=AT04-04\r\n] 2006.253.07:42:41.75#ibcon#*before write, iclass 28, count 2 2006.253.07:42:41.75#ibcon#enter sib2, iclass 28, count 2 2006.253.07:42:41.75#ibcon#flushed, iclass 28, count 2 2006.253.07:42:41.75#ibcon#about to write, iclass 28, count 2 2006.253.07:42:41.75#ibcon#wrote, iclass 28, count 2 2006.253.07:42:41.75#ibcon#about to read 3, iclass 28, count 2 2006.253.07:42:41.78#ibcon#read 3, iclass 28, count 2 2006.253.07:42:41.78#ibcon#about to read 4, iclass 28, count 2 2006.253.07:42:41.78#ibcon#read 4, iclass 28, count 2 2006.253.07:42:41.78#ibcon#about to read 5, iclass 28, count 2 2006.253.07:42:41.78#ibcon#read 5, iclass 28, count 2 2006.253.07:42:41.78#ibcon#about to read 6, iclass 28, count 2 2006.253.07:42:41.78#ibcon#read 6, iclass 28, count 2 2006.253.07:42:41.78#ibcon#end of sib2, iclass 28, count 2 2006.253.07:42:41.78#ibcon#*after write, iclass 28, count 2 2006.253.07:42:41.78#ibcon#*before return 0, iclass 28, count 2 2006.253.07:42:41.78#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.253.07:42:41.78#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.253.07:42:41.78#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.253.07:42:41.78#ibcon#ireg 7 cls_cnt 0 2006.253.07:42:41.78#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.253.07:42:41.90#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.253.07:42:41.90#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.253.07:42:41.90#ibcon#enter wrdev, iclass 28, count 0 2006.253.07:42:41.90#ibcon#first serial, iclass 28, count 0 2006.253.07:42:41.90#ibcon#enter sib2, iclass 28, count 0 2006.253.07:42:41.90#ibcon#flushed, iclass 28, count 0 2006.253.07:42:41.90#ibcon#about to write, iclass 28, count 0 2006.253.07:42:41.90#ibcon#wrote, iclass 28, count 0 2006.253.07:42:41.90#ibcon#about to read 3, iclass 28, count 0 2006.253.07:42:41.92#ibcon#read 3, iclass 28, count 0 2006.253.07:42:41.92#ibcon#about to read 4, iclass 28, count 0 2006.253.07:42:41.92#ibcon#read 4, iclass 28, count 0 2006.253.07:42:41.92#ibcon#about to read 5, iclass 28, count 0 2006.253.07:42:41.92#ibcon#read 5, iclass 28, count 0 2006.253.07:42:41.92#ibcon#about to read 6, iclass 28, count 0 2006.253.07:42:41.92#ibcon#read 6, iclass 28, count 0 2006.253.07:42:41.92#ibcon#end of sib2, iclass 28, count 0 2006.253.07:42:41.92#ibcon#*mode == 0, iclass 28, count 0 2006.253.07:42:41.92#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.253.07:42:41.92#ibcon#[27=USB\r\n] 2006.253.07:42:41.92#ibcon#*before write, iclass 28, count 0 2006.253.07:42:41.92#ibcon#enter sib2, iclass 28, count 0 2006.253.07:42:41.92#ibcon#flushed, iclass 28, count 0 2006.253.07:42:41.92#ibcon#about to write, iclass 28, count 0 2006.253.07:42:41.92#ibcon#wrote, iclass 28, count 0 2006.253.07:42:41.92#ibcon#about to read 3, iclass 28, count 0 2006.253.07:42:41.95#ibcon#read 3, iclass 28, count 0 2006.253.07:42:41.95#ibcon#about to read 4, iclass 28, count 0 2006.253.07:42:41.95#ibcon#read 4, iclass 28, count 0 2006.253.07:42:41.95#ibcon#about to read 5, iclass 28, count 0 2006.253.07:42:41.95#ibcon#read 5, iclass 28, count 0 2006.253.07:42:41.95#ibcon#about to read 6, iclass 28, count 0 2006.253.07:42:41.95#ibcon#read 6, iclass 28, count 0 2006.253.07:42:41.95#ibcon#end of sib2, iclass 28, count 0 2006.253.07:42:41.95#ibcon#*after write, iclass 28, count 0 2006.253.07:42:41.95#ibcon#*before return 0, iclass 28, count 0 2006.253.07:42:41.95#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.253.07:42:41.95#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.253.07:42:41.95#ibcon#about to clear, iclass 28 cls_cnt 0 2006.253.07:42:41.95#ibcon#cleared, iclass 28 cls_cnt 0 2006.253.07:42:41.95$vc4f8/vblo=5,744.99 2006.253.07:42:41.95#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.253.07:42:41.95#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.253.07:42:41.95#ibcon#ireg 17 cls_cnt 0 2006.253.07:42:41.95#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.253.07:42:41.95#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.253.07:42:41.95#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.253.07:42:41.95#ibcon#enter wrdev, iclass 30, count 0 2006.253.07:42:41.95#ibcon#first serial, iclass 30, count 0 2006.253.07:42:41.95#ibcon#enter sib2, iclass 30, count 0 2006.253.07:42:41.95#ibcon#flushed, iclass 30, count 0 2006.253.07:42:41.95#ibcon#about to write, iclass 30, count 0 2006.253.07:42:41.95#ibcon#wrote, iclass 30, count 0 2006.253.07:42:41.95#ibcon#about to read 3, iclass 30, count 0 2006.253.07:42:41.97#ibcon#read 3, iclass 30, count 0 2006.253.07:42:41.97#ibcon#about to read 4, iclass 30, count 0 2006.253.07:42:41.97#ibcon#read 4, iclass 30, count 0 2006.253.07:42:41.97#ibcon#about to read 5, iclass 30, count 0 2006.253.07:42:41.97#ibcon#read 5, iclass 30, count 0 2006.253.07:42:41.97#ibcon#about to read 6, iclass 30, count 0 2006.253.07:42:41.97#ibcon#read 6, iclass 30, count 0 2006.253.07:42:41.97#ibcon#end of sib2, iclass 30, count 0 2006.253.07:42:41.97#ibcon#*mode == 0, iclass 30, count 0 2006.253.07:42:41.97#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.253.07:42:41.97#ibcon#[28=FRQ=05,744.99\r\n] 2006.253.07:42:41.97#ibcon#*before write, iclass 30, count 0 2006.253.07:42:41.97#ibcon#enter sib2, iclass 30, count 0 2006.253.07:42:41.97#ibcon#flushed, iclass 30, count 0 2006.253.07:42:41.97#ibcon#about to write, iclass 30, count 0 2006.253.07:42:41.97#ibcon#wrote, iclass 30, count 0 2006.253.07:42:41.97#ibcon#about to read 3, iclass 30, count 0 2006.253.07:42:42.01#ibcon#read 3, iclass 30, count 0 2006.253.07:42:42.01#ibcon#about to read 4, iclass 30, count 0 2006.253.07:42:42.01#ibcon#read 4, iclass 30, count 0 2006.253.07:42:42.01#ibcon#about to read 5, iclass 30, count 0 2006.253.07:42:42.01#ibcon#read 5, iclass 30, count 0 2006.253.07:42:42.01#ibcon#about to read 6, iclass 30, count 0 2006.253.07:42:42.01#ibcon#read 6, iclass 30, count 0 2006.253.07:42:42.01#ibcon#end of sib2, iclass 30, count 0 2006.253.07:42:42.01#ibcon#*after write, iclass 30, count 0 2006.253.07:42:42.01#ibcon#*before return 0, iclass 30, count 0 2006.253.07:42:42.01#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.253.07:42:42.01#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.253.07:42:42.01#ibcon#about to clear, iclass 30 cls_cnt 0 2006.253.07:42:42.01#ibcon#cleared, iclass 30 cls_cnt 0 2006.253.07:42:42.01$vc4f8/vb=5,4 2006.253.07:42:42.01#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.253.07:42:42.01#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.253.07:42:42.01#ibcon#ireg 11 cls_cnt 2 2006.253.07:42:42.01#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.253.07:42:42.07#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.253.07:42:42.07#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.253.07:42:42.07#ibcon#enter wrdev, iclass 32, count 2 2006.253.07:42:42.07#ibcon#first serial, iclass 32, count 2 2006.253.07:42:42.07#ibcon#enter sib2, iclass 32, count 2 2006.253.07:42:42.07#ibcon#flushed, iclass 32, count 2 2006.253.07:42:42.07#ibcon#about to write, iclass 32, count 2 2006.253.07:42:42.07#ibcon#wrote, iclass 32, count 2 2006.253.07:42:42.07#ibcon#about to read 3, iclass 32, count 2 2006.253.07:42:42.09#ibcon#read 3, iclass 32, count 2 2006.253.07:42:42.09#ibcon#about to read 4, iclass 32, count 2 2006.253.07:42:42.09#ibcon#read 4, iclass 32, count 2 2006.253.07:42:42.09#ibcon#about to read 5, iclass 32, count 2 2006.253.07:42:42.09#ibcon#read 5, iclass 32, count 2 2006.253.07:42:42.09#ibcon#about to read 6, iclass 32, count 2 2006.253.07:42:42.09#ibcon#read 6, iclass 32, count 2 2006.253.07:42:42.09#ibcon#end of sib2, iclass 32, count 2 2006.253.07:42:42.09#ibcon#*mode == 0, iclass 32, count 2 2006.253.07:42:42.09#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.253.07:42:42.09#ibcon#[27=AT05-04\r\n] 2006.253.07:42:42.09#ibcon#*before write, iclass 32, count 2 2006.253.07:42:42.09#ibcon#enter sib2, iclass 32, count 2 2006.253.07:42:42.09#ibcon#flushed, iclass 32, count 2 2006.253.07:42:42.09#ibcon#about to write, iclass 32, count 2 2006.253.07:42:42.09#ibcon#wrote, iclass 32, count 2 2006.253.07:42:42.09#ibcon#about to read 3, iclass 32, count 2 2006.253.07:42:42.12#ibcon#read 3, iclass 32, count 2 2006.253.07:42:42.12#ibcon#about to read 4, iclass 32, count 2 2006.253.07:42:42.12#ibcon#read 4, iclass 32, count 2 2006.253.07:42:42.12#ibcon#about to read 5, iclass 32, count 2 2006.253.07:42:42.12#ibcon#read 5, iclass 32, count 2 2006.253.07:42:42.12#ibcon#about to read 6, iclass 32, count 2 2006.253.07:42:42.12#ibcon#read 6, iclass 32, count 2 2006.253.07:42:42.12#ibcon#end of sib2, iclass 32, count 2 2006.253.07:42:42.12#ibcon#*after write, iclass 32, count 2 2006.253.07:42:42.12#ibcon#*before return 0, iclass 32, count 2 2006.253.07:42:42.12#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.253.07:42:42.12#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.253.07:42:42.12#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.253.07:42:42.12#ibcon#ireg 7 cls_cnt 0 2006.253.07:42:42.12#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.253.07:42:42.21#abcon#<5=/08 1.2 4.1 31.43 731006.3\r\n> 2006.253.07:42:42.23#abcon#{5=INTERFACE CLEAR} 2006.253.07:42:42.24#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.253.07:42:42.24#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.253.07:42:42.24#ibcon#enter wrdev, iclass 32, count 0 2006.253.07:42:42.24#ibcon#first serial, iclass 32, count 0 2006.253.07:42:42.24#ibcon#enter sib2, iclass 32, count 0 2006.253.07:42:42.24#ibcon#flushed, iclass 32, count 0 2006.253.07:42:42.24#ibcon#about to write, iclass 32, count 0 2006.253.07:42:42.24#ibcon#wrote, iclass 32, count 0 2006.253.07:42:42.24#ibcon#about to read 3, iclass 32, count 0 2006.253.07:42:42.26#ibcon#read 3, iclass 32, count 0 2006.253.07:42:42.26#ibcon#about to read 4, iclass 32, count 0 2006.253.07:42:42.26#ibcon#read 4, iclass 32, count 0 2006.253.07:42:42.26#ibcon#about to read 5, iclass 32, count 0 2006.253.07:42:42.26#ibcon#read 5, iclass 32, count 0 2006.253.07:42:42.26#ibcon#about to read 6, iclass 32, count 0 2006.253.07:42:42.26#ibcon#read 6, iclass 32, count 0 2006.253.07:42:42.26#ibcon#end of sib2, iclass 32, count 0 2006.253.07:42:42.26#ibcon#*mode == 0, iclass 32, count 0 2006.253.07:42:42.26#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.253.07:42:42.26#ibcon#[27=USB\r\n] 2006.253.07:42:42.26#ibcon#*before write, iclass 32, count 0 2006.253.07:42:42.26#ibcon#enter sib2, iclass 32, count 0 2006.253.07:42:42.26#ibcon#flushed, iclass 32, count 0 2006.253.07:42:42.26#ibcon#about to write, iclass 32, count 0 2006.253.07:42:42.26#ibcon#wrote, iclass 32, count 0 2006.253.07:42:42.26#ibcon#about to read 3, iclass 32, count 0 2006.253.07:42:42.29#abcon#[5=S1D000X0/0*\r\n] 2006.253.07:42:42.29#ibcon#read 3, iclass 32, count 0 2006.253.07:42:42.29#ibcon#about to read 4, iclass 32, count 0 2006.253.07:42:42.29#ibcon#read 4, iclass 32, count 0 2006.253.07:42:42.29#ibcon#about to read 5, iclass 32, count 0 2006.253.07:42:42.29#ibcon#read 5, iclass 32, count 0 2006.253.07:42:42.29#ibcon#about to read 6, iclass 32, count 0 2006.253.07:42:42.29#ibcon#read 6, iclass 32, count 0 2006.253.07:42:42.29#ibcon#end of sib2, iclass 32, count 0 2006.253.07:42:42.29#ibcon#*after write, iclass 32, count 0 2006.253.07:42:42.29#ibcon#*before return 0, iclass 32, count 0 2006.253.07:42:42.29#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.253.07:42:42.29#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.253.07:42:42.29#ibcon#about to clear, iclass 32 cls_cnt 0 2006.253.07:42:42.29#ibcon#cleared, iclass 32 cls_cnt 0 2006.253.07:42:42.29$vc4f8/vblo=6,752.99 2006.253.07:42:42.29#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.253.07:42:42.29#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.253.07:42:42.29#ibcon#ireg 17 cls_cnt 0 2006.253.07:42:42.29#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.253.07:42:42.29#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.253.07:42:42.29#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.253.07:42:42.29#ibcon#enter wrdev, iclass 38, count 0 2006.253.07:42:42.29#ibcon#first serial, iclass 38, count 0 2006.253.07:42:42.29#ibcon#enter sib2, iclass 38, count 0 2006.253.07:42:42.29#ibcon#flushed, iclass 38, count 0 2006.253.07:42:42.29#ibcon#about to write, iclass 38, count 0 2006.253.07:42:42.29#ibcon#wrote, iclass 38, count 0 2006.253.07:42:42.29#ibcon#about to read 3, iclass 38, count 0 2006.253.07:42:42.31#ibcon#read 3, iclass 38, count 0 2006.253.07:42:42.31#ibcon#about to read 4, iclass 38, count 0 2006.253.07:42:42.31#ibcon#read 4, iclass 38, count 0 2006.253.07:42:42.31#ibcon#about to read 5, iclass 38, count 0 2006.253.07:42:42.31#ibcon#read 5, iclass 38, count 0 2006.253.07:42:42.31#ibcon#about to read 6, iclass 38, count 0 2006.253.07:42:42.31#ibcon#read 6, iclass 38, count 0 2006.253.07:42:42.31#ibcon#end of sib2, iclass 38, count 0 2006.253.07:42:42.31#ibcon#*mode == 0, iclass 38, count 0 2006.253.07:42:42.31#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.253.07:42:42.31#ibcon#[28=FRQ=06,752.99\r\n] 2006.253.07:42:42.31#ibcon#*before write, iclass 38, count 0 2006.253.07:42:42.31#ibcon#enter sib2, iclass 38, count 0 2006.253.07:42:42.31#ibcon#flushed, iclass 38, count 0 2006.253.07:42:42.31#ibcon#about to write, iclass 38, count 0 2006.253.07:42:42.31#ibcon#wrote, iclass 38, count 0 2006.253.07:42:42.31#ibcon#about to read 3, iclass 38, count 0 2006.253.07:42:42.35#ibcon#read 3, iclass 38, count 0 2006.253.07:42:42.35#ibcon#about to read 4, iclass 38, count 0 2006.253.07:42:42.35#ibcon#read 4, iclass 38, count 0 2006.253.07:42:42.35#ibcon#about to read 5, iclass 38, count 0 2006.253.07:42:42.35#ibcon#read 5, iclass 38, count 0 2006.253.07:42:42.35#ibcon#about to read 6, iclass 38, count 0 2006.253.07:42:42.35#ibcon#read 6, iclass 38, count 0 2006.253.07:42:42.35#ibcon#end of sib2, iclass 38, count 0 2006.253.07:42:42.35#ibcon#*after write, iclass 38, count 0 2006.253.07:42:42.35#ibcon#*before return 0, iclass 38, count 0 2006.253.07:42:42.35#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.253.07:42:42.35#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.253.07:42:42.35#ibcon#about to clear, iclass 38 cls_cnt 0 2006.253.07:42:42.35#ibcon#cleared, iclass 38 cls_cnt 0 2006.253.07:42:42.35$vc4f8/vb=6,4 2006.253.07:42:42.35#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.253.07:42:42.35#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.253.07:42:42.35#ibcon#ireg 11 cls_cnt 2 2006.253.07:42:42.35#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.253.07:42:42.41#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.253.07:42:42.41#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.253.07:42:42.41#ibcon#enter wrdev, iclass 40, count 2 2006.253.07:42:42.41#ibcon#first serial, iclass 40, count 2 2006.253.07:42:42.41#ibcon#enter sib2, iclass 40, count 2 2006.253.07:42:42.41#ibcon#flushed, iclass 40, count 2 2006.253.07:42:42.41#ibcon#about to write, iclass 40, count 2 2006.253.07:42:42.41#ibcon#wrote, iclass 40, count 2 2006.253.07:42:42.41#ibcon#about to read 3, iclass 40, count 2 2006.253.07:42:42.43#ibcon#read 3, iclass 40, count 2 2006.253.07:42:42.43#ibcon#about to read 4, iclass 40, count 2 2006.253.07:42:42.43#ibcon#read 4, iclass 40, count 2 2006.253.07:42:42.43#ibcon#about to read 5, iclass 40, count 2 2006.253.07:42:42.43#ibcon#read 5, iclass 40, count 2 2006.253.07:42:42.43#ibcon#about to read 6, iclass 40, count 2 2006.253.07:42:42.43#ibcon#read 6, iclass 40, count 2 2006.253.07:42:42.43#ibcon#end of sib2, iclass 40, count 2 2006.253.07:42:42.43#ibcon#*mode == 0, iclass 40, count 2 2006.253.07:42:42.43#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.253.07:42:42.43#ibcon#[27=AT06-04\r\n] 2006.253.07:42:42.43#ibcon#*before write, iclass 40, count 2 2006.253.07:42:42.43#ibcon#enter sib2, iclass 40, count 2 2006.253.07:42:42.43#ibcon#flushed, iclass 40, count 2 2006.253.07:42:42.43#ibcon#about to write, iclass 40, count 2 2006.253.07:42:42.43#ibcon#wrote, iclass 40, count 2 2006.253.07:42:42.43#ibcon#about to read 3, iclass 40, count 2 2006.253.07:42:42.46#ibcon#read 3, iclass 40, count 2 2006.253.07:42:42.46#ibcon#about to read 4, iclass 40, count 2 2006.253.07:42:42.46#ibcon#read 4, iclass 40, count 2 2006.253.07:42:42.46#ibcon#about to read 5, iclass 40, count 2 2006.253.07:42:42.46#ibcon#read 5, iclass 40, count 2 2006.253.07:42:42.46#ibcon#about to read 6, iclass 40, count 2 2006.253.07:42:42.46#ibcon#read 6, iclass 40, count 2 2006.253.07:42:42.46#ibcon#end of sib2, iclass 40, count 2 2006.253.07:42:42.46#ibcon#*after write, iclass 40, count 2 2006.253.07:42:42.46#ibcon#*before return 0, iclass 40, count 2 2006.253.07:42:42.46#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.253.07:42:42.46#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.253.07:42:42.46#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.253.07:42:42.46#ibcon#ireg 7 cls_cnt 0 2006.253.07:42:42.46#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.253.07:42:42.58#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.253.07:42:42.58#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.253.07:42:42.58#ibcon#enter wrdev, iclass 40, count 0 2006.253.07:42:42.58#ibcon#first serial, iclass 40, count 0 2006.253.07:42:42.58#ibcon#enter sib2, iclass 40, count 0 2006.253.07:42:42.58#ibcon#flushed, iclass 40, count 0 2006.253.07:42:42.58#ibcon#about to write, iclass 40, count 0 2006.253.07:42:42.58#ibcon#wrote, iclass 40, count 0 2006.253.07:42:42.58#ibcon#about to read 3, iclass 40, count 0 2006.253.07:42:42.60#ibcon#read 3, iclass 40, count 0 2006.253.07:42:42.60#ibcon#about to read 4, iclass 40, count 0 2006.253.07:42:42.60#ibcon#read 4, iclass 40, count 0 2006.253.07:42:42.60#ibcon#about to read 5, iclass 40, count 0 2006.253.07:42:42.60#ibcon#read 5, iclass 40, count 0 2006.253.07:42:42.60#ibcon#about to read 6, iclass 40, count 0 2006.253.07:42:42.60#ibcon#read 6, iclass 40, count 0 2006.253.07:42:42.60#ibcon#end of sib2, iclass 40, count 0 2006.253.07:42:42.60#ibcon#*mode == 0, iclass 40, count 0 2006.253.07:42:42.60#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.253.07:42:42.60#ibcon#[27=USB\r\n] 2006.253.07:42:42.60#ibcon#*before write, iclass 40, count 0 2006.253.07:42:42.60#ibcon#enter sib2, iclass 40, count 0 2006.253.07:42:42.60#ibcon#flushed, iclass 40, count 0 2006.253.07:42:42.60#ibcon#about to write, iclass 40, count 0 2006.253.07:42:42.60#ibcon#wrote, iclass 40, count 0 2006.253.07:42:42.60#ibcon#about to read 3, iclass 40, count 0 2006.253.07:42:42.63#ibcon#read 3, iclass 40, count 0 2006.253.07:42:42.63#ibcon#about to read 4, iclass 40, count 0 2006.253.07:42:42.63#ibcon#read 4, iclass 40, count 0 2006.253.07:42:42.63#ibcon#about to read 5, iclass 40, count 0 2006.253.07:42:42.63#ibcon#read 5, iclass 40, count 0 2006.253.07:42:42.63#ibcon#about to read 6, iclass 40, count 0 2006.253.07:42:42.63#ibcon#read 6, iclass 40, count 0 2006.253.07:42:42.63#ibcon#end of sib2, iclass 40, count 0 2006.253.07:42:42.63#ibcon#*after write, iclass 40, count 0 2006.253.07:42:42.63#ibcon#*before return 0, iclass 40, count 0 2006.253.07:42:42.63#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.253.07:42:42.63#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.253.07:42:42.63#ibcon#about to clear, iclass 40 cls_cnt 0 2006.253.07:42:42.63#ibcon#cleared, iclass 40 cls_cnt 0 2006.253.07:42:42.63$vc4f8/vabw=wide 2006.253.07:42:42.63#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.253.07:42:42.63#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.253.07:42:42.63#ibcon#ireg 8 cls_cnt 0 2006.253.07:42:42.63#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.253.07:42:42.63#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.253.07:42:42.63#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.253.07:42:42.63#ibcon#enter wrdev, iclass 4, count 0 2006.253.07:42:42.63#ibcon#first serial, iclass 4, count 0 2006.253.07:42:42.63#ibcon#enter sib2, iclass 4, count 0 2006.253.07:42:42.63#ibcon#flushed, iclass 4, count 0 2006.253.07:42:42.63#ibcon#about to write, iclass 4, count 0 2006.253.07:42:42.63#ibcon#wrote, iclass 4, count 0 2006.253.07:42:42.63#ibcon#about to read 3, iclass 4, count 0 2006.253.07:42:42.65#ibcon#read 3, iclass 4, count 0 2006.253.07:42:42.65#ibcon#about to read 4, iclass 4, count 0 2006.253.07:42:42.65#ibcon#read 4, iclass 4, count 0 2006.253.07:42:42.65#ibcon#about to read 5, iclass 4, count 0 2006.253.07:42:42.65#ibcon#read 5, iclass 4, count 0 2006.253.07:42:42.65#ibcon#about to read 6, iclass 4, count 0 2006.253.07:42:42.65#ibcon#read 6, iclass 4, count 0 2006.253.07:42:42.65#ibcon#end of sib2, iclass 4, count 0 2006.253.07:42:42.65#ibcon#*mode == 0, iclass 4, count 0 2006.253.07:42:42.65#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.253.07:42:42.65#ibcon#[25=BW32\r\n] 2006.253.07:42:42.65#ibcon#*before write, iclass 4, count 0 2006.253.07:42:42.65#ibcon#enter sib2, iclass 4, count 0 2006.253.07:42:42.65#ibcon#flushed, iclass 4, count 0 2006.253.07:42:42.65#ibcon#about to write, iclass 4, count 0 2006.253.07:42:42.65#ibcon#wrote, iclass 4, count 0 2006.253.07:42:42.65#ibcon#about to read 3, iclass 4, count 0 2006.253.07:42:42.68#ibcon#read 3, iclass 4, count 0 2006.253.07:42:42.68#ibcon#about to read 4, iclass 4, count 0 2006.253.07:42:42.68#ibcon#read 4, iclass 4, count 0 2006.253.07:42:42.68#ibcon#about to read 5, iclass 4, count 0 2006.253.07:42:42.68#ibcon#read 5, iclass 4, count 0 2006.253.07:42:42.68#ibcon#about to read 6, iclass 4, count 0 2006.253.07:42:42.68#ibcon#read 6, iclass 4, count 0 2006.253.07:42:42.68#ibcon#end of sib2, iclass 4, count 0 2006.253.07:42:42.68#ibcon#*after write, iclass 4, count 0 2006.253.07:42:42.68#ibcon#*before return 0, iclass 4, count 0 2006.253.07:42:42.68#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.253.07:42:42.68#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.253.07:42:42.68#ibcon#about to clear, iclass 4 cls_cnt 0 2006.253.07:42:42.68#ibcon#cleared, iclass 4 cls_cnt 0 2006.253.07:42:42.68$vc4f8/vbbw=wide 2006.253.07:42:42.68#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.253.07:42:42.68#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.253.07:42:42.68#ibcon#ireg 8 cls_cnt 0 2006.253.07:42:42.68#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.253.07:42:42.75#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.253.07:42:42.75#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.253.07:42:42.75#ibcon#enter wrdev, iclass 6, count 0 2006.253.07:42:42.75#ibcon#first serial, iclass 6, count 0 2006.253.07:42:42.75#ibcon#enter sib2, iclass 6, count 0 2006.253.07:42:42.75#ibcon#flushed, iclass 6, count 0 2006.253.07:42:42.75#ibcon#about to write, iclass 6, count 0 2006.253.07:42:42.75#ibcon#wrote, iclass 6, count 0 2006.253.07:42:42.75#ibcon#about to read 3, iclass 6, count 0 2006.253.07:42:42.77#ibcon#read 3, iclass 6, count 0 2006.253.07:42:42.77#ibcon#about to read 4, iclass 6, count 0 2006.253.07:42:42.77#ibcon#read 4, iclass 6, count 0 2006.253.07:42:42.77#ibcon#about to read 5, iclass 6, count 0 2006.253.07:42:42.77#ibcon#read 5, iclass 6, count 0 2006.253.07:42:42.77#ibcon#about to read 6, iclass 6, count 0 2006.253.07:42:42.77#ibcon#read 6, iclass 6, count 0 2006.253.07:42:42.77#ibcon#end of sib2, iclass 6, count 0 2006.253.07:42:42.77#ibcon#*mode == 0, iclass 6, count 0 2006.253.07:42:42.77#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.253.07:42:42.77#ibcon#[27=BW32\r\n] 2006.253.07:42:42.77#ibcon#*before write, iclass 6, count 0 2006.253.07:42:42.77#ibcon#enter sib2, iclass 6, count 0 2006.253.07:42:42.77#ibcon#flushed, iclass 6, count 0 2006.253.07:42:42.77#ibcon#about to write, iclass 6, count 0 2006.253.07:42:42.77#ibcon#wrote, iclass 6, count 0 2006.253.07:42:42.77#ibcon#about to read 3, iclass 6, count 0 2006.253.07:42:42.80#ibcon#read 3, iclass 6, count 0 2006.253.07:42:42.80#ibcon#about to read 4, iclass 6, count 0 2006.253.07:42:42.80#ibcon#read 4, iclass 6, count 0 2006.253.07:42:42.80#ibcon#about to read 5, iclass 6, count 0 2006.253.07:42:42.80#ibcon#read 5, iclass 6, count 0 2006.253.07:42:42.80#ibcon#about to read 6, iclass 6, count 0 2006.253.07:42:42.80#ibcon#read 6, iclass 6, count 0 2006.253.07:42:42.80#ibcon#end of sib2, iclass 6, count 0 2006.253.07:42:42.80#ibcon#*after write, iclass 6, count 0 2006.253.07:42:42.80#ibcon#*before return 0, iclass 6, count 0 2006.253.07:42:42.80#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.253.07:42:42.80#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.253.07:42:42.80#ibcon#about to clear, iclass 6 cls_cnt 0 2006.253.07:42:42.80#ibcon#cleared, iclass 6 cls_cnt 0 2006.253.07:42:42.80$4f8m12a/ifd4f 2006.253.07:42:42.80$ifd4f/lo= 2006.253.07:42:42.80$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.253.07:42:42.80$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.253.07:42:42.80$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.253.07:42:42.80$ifd4f/patch= 2006.253.07:42:42.80$ifd4f/patch=lo1,a1,a2,a3,a4 2006.253.07:42:42.80$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.253.07:42:42.80$ifd4f/patch=lo3,a5,a6,a7,a8 2006.253.07:42:42.80$4f8m12a/"form=m,16.000,1:2 2006.253.07:42:42.80$4f8m12a/"tpicd 2006.253.07:42:42.80$4f8m12a/echo=off 2006.253.07:42:42.80$4f8m12a/xlog=off 2006.253.07:42:42.80:!2006.253.07:43:10 2006.253.07:42:53.14#trakl#Source acquired 2006.253.07:42:55.14#flagr#flagr/antenna,acquired 2006.253.07:43:10.00:preob 2006.253.07:43:11.14/onsource/TRACKING 2006.253.07:43:11.14:!2006.253.07:43:20 2006.253.07:43:20.00:data_valid=on 2006.253.07:43:20.00:midob 2006.253.07:43:20.14/onsource/TRACKING 2006.253.07:43:20.14/wx/31.43,1006.3,72 2006.253.07:43:20.27/cable/+6.3690E-03 2006.253.07:43:21.36/va/01,08,usb,yes,31,33 2006.253.07:43:21.36/va/02,07,usb,yes,31,32 2006.253.07:43:21.36/va/03,06,usb,yes,33,33 2006.253.07:43:21.36/va/04,07,usb,yes,32,35 2006.253.07:43:21.36/va/05,07,usb,yes,33,35 2006.253.07:43:21.36/va/06,07,usb,yes,29,29 2006.253.07:43:21.36/va/07,07,usb,yes,29,29 2006.253.07:43:21.36/va/08,07,usb,yes,31,31 2006.253.07:43:21.59/valo/01,532.99,yes,locked 2006.253.07:43:21.59/valo/02,572.99,yes,locked 2006.253.07:43:21.59/valo/03,672.99,yes,locked 2006.253.07:43:21.59/valo/04,832.99,yes,locked 2006.253.07:43:21.59/valo/05,652.99,yes,locked 2006.253.07:43:21.59/valo/06,772.99,yes,locked 2006.253.07:43:21.59/valo/07,832.99,yes,locked 2006.253.07:43:21.59/valo/08,852.99,yes,locked 2006.253.07:43:22.68/vb/01,04,usb,yes,30,29 2006.253.07:43:22.68/vb/02,05,usb,yes,28,29 2006.253.07:43:22.68/vb/03,04,usb,yes,28,32 2006.253.07:43:22.68/vb/04,04,usb,yes,30,29 2006.253.07:43:22.68/vb/05,04,usb,yes,27,32 2006.253.07:43:22.68/vb/06,04,usb,yes,28,31 2006.253.07:43:22.68/vb/07,04,usb,yes,31,31 2006.253.07:43:22.68/vb/08,04,usb,yes,28,31 2006.253.07:43:22.91/vblo/01,632.99,yes,locked 2006.253.07:43:22.91/vblo/02,640.99,yes,locked 2006.253.07:43:22.91/vblo/03,656.99,yes,locked 2006.253.07:43:22.91/vblo/04,712.99,yes,locked 2006.253.07:43:22.91/vblo/05,744.99,yes,locked 2006.253.07:43:22.91/vblo/06,752.99,yes,locked 2006.253.07:43:22.91/vblo/07,734.99,yes,locked 2006.253.07:43:22.91/vblo/08,744.99,yes,locked 2006.253.07:43:23.06/vabw/8 2006.253.07:43:23.21/vbbw/8 2006.253.07:43:23.30/xfe/off,on,14.0 2006.253.07:43:23.68/ifatt/23,28,28,28 2006.253.07:43:24.08/fmout-gps/S +4.76E-07 2006.253.07:43:24.12:!2006.253.07:44:20 2006.253.07:44:20.02:data_valid=off 2006.253.07:44:20.02:postob 2006.253.07:44:20.12/cable/+6.3696E-03 2006.253.07:44:20.12/wx/31.41,1006.4,73 2006.253.07:44:21.08/fmout-gps/S +4.75E-07 2006.253.07:44:21.08:scan_name=253-0745,k06253,60 2006.253.07:44:21.08:source=0718+793,072611.74,791131.0,2000.0,neutral 2006.253.07:44:21.14#flagr#flagr/antenna,new-source 2006.253.07:44:22.14:checkk5 2006.253.07:44:22.51/chk_autoobs//k5ts1/ autoobs is running! 2006.253.07:44:22.89/chk_autoobs//k5ts2/ autoobs is running! 2006.253.07:44:23.26/chk_autoobs//k5ts3/ autoobs is running! 2006.253.07:44:23.64/chk_autoobs//k5ts4/ autoobs is running! 2006.253.07:44:24.01/chk_obsdata//k5ts1/T2530743??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.07:44:24.38/chk_obsdata//k5ts2/T2530743??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.07:44:24.75/chk_obsdata//k5ts3/T2530743??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.07:44:25.12/chk_obsdata//k5ts4/T2530743??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.07:44:25.81/k5log//k5ts1_log_newline 2006.253.07:44:26.49/k5log//k5ts2_log_newline 2006.253.07:44:27.18/k5log//k5ts3_log_newline 2006.253.07:44:27.87/k5log//k5ts4_log_newline 2006.253.07:44:27.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.253.07:44:27.90:4f8m12a=1 2006.253.07:44:27.90$4f8m12a/echo=on 2006.253.07:44:27.90$4f8m12a/pcalon 2006.253.07:44:27.90$pcalon/"no phase cal control is implemented here 2006.253.07:44:27.90$4f8m12a/"tpicd=stop 2006.253.07:44:27.90$4f8m12a/vc4f8 2006.253.07:44:27.90$vc4f8/valo=1,532.99 2006.253.07:44:27.91#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.253.07:44:27.91#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.253.07:44:27.91#ibcon#ireg 17 cls_cnt 0 2006.253.07:44:27.91#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.253.07:44:27.91#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.253.07:44:27.91#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.253.07:44:27.91#ibcon#enter wrdev, iclass 15, count 0 2006.253.07:44:27.91#ibcon#first serial, iclass 15, count 0 2006.253.07:44:27.91#ibcon#enter sib2, iclass 15, count 0 2006.253.07:44:27.91#ibcon#flushed, iclass 15, count 0 2006.253.07:44:27.91#ibcon#about to write, iclass 15, count 0 2006.253.07:44:27.91#ibcon#wrote, iclass 15, count 0 2006.253.07:44:27.91#ibcon#about to read 3, iclass 15, count 0 2006.253.07:44:27.95#ibcon#read 3, iclass 15, count 0 2006.253.07:44:27.95#ibcon#about to read 4, iclass 15, count 0 2006.253.07:44:27.95#ibcon#read 4, iclass 15, count 0 2006.253.07:44:27.95#ibcon#about to read 5, iclass 15, count 0 2006.253.07:44:27.95#ibcon#read 5, iclass 15, count 0 2006.253.07:44:27.95#ibcon#about to read 6, iclass 15, count 0 2006.253.07:44:27.95#ibcon#read 6, iclass 15, count 0 2006.253.07:44:27.95#ibcon#end of sib2, iclass 15, count 0 2006.253.07:44:27.95#ibcon#*mode == 0, iclass 15, count 0 2006.253.07:44:27.95#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.253.07:44:27.95#ibcon#[26=FRQ=01,532.99\r\n] 2006.253.07:44:27.95#ibcon#*before write, iclass 15, count 0 2006.253.07:44:27.95#ibcon#enter sib2, iclass 15, count 0 2006.253.07:44:27.95#ibcon#flushed, iclass 15, count 0 2006.253.07:44:27.95#ibcon#about to write, iclass 15, count 0 2006.253.07:44:27.95#ibcon#wrote, iclass 15, count 0 2006.253.07:44:27.95#ibcon#about to read 3, iclass 15, count 0 2006.253.07:44:27.99#ibcon#read 3, iclass 15, count 0 2006.253.07:44:27.99#ibcon#about to read 4, iclass 15, count 0 2006.253.07:44:27.99#ibcon#read 4, iclass 15, count 0 2006.253.07:44:27.99#ibcon#about to read 5, iclass 15, count 0 2006.253.07:44:28.00#ibcon#read 5, iclass 15, count 0 2006.253.07:44:28.00#ibcon#about to read 6, iclass 15, count 0 2006.253.07:44:28.00#ibcon#read 6, iclass 15, count 0 2006.253.07:44:28.00#ibcon#end of sib2, iclass 15, count 0 2006.253.07:44:28.00#ibcon#*after write, iclass 15, count 0 2006.253.07:44:28.00#ibcon#*before return 0, iclass 15, count 0 2006.253.07:44:28.00#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.253.07:44:28.00#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.253.07:44:28.00#ibcon#about to clear, iclass 15 cls_cnt 0 2006.253.07:44:28.00#ibcon#cleared, iclass 15 cls_cnt 0 2006.253.07:44:28.00$vc4f8/va=1,8 2006.253.07:44:28.00#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.253.07:44:28.00#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.253.07:44:28.00#ibcon#ireg 11 cls_cnt 2 2006.253.07:44:28.00#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.253.07:44:28.00#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.253.07:44:28.00#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.253.07:44:28.00#ibcon#enter wrdev, iclass 17, count 2 2006.253.07:44:28.00#ibcon#first serial, iclass 17, count 2 2006.253.07:44:28.00#ibcon#enter sib2, iclass 17, count 2 2006.253.07:44:28.00#ibcon#flushed, iclass 17, count 2 2006.253.07:44:28.00#ibcon#about to write, iclass 17, count 2 2006.253.07:44:28.00#ibcon#wrote, iclass 17, count 2 2006.253.07:44:28.00#ibcon#about to read 3, iclass 17, count 2 2006.253.07:44:28.02#ibcon#read 3, iclass 17, count 2 2006.253.07:44:28.02#ibcon#about to read 4, iclass 17, count 2 2006.253.07:44:28.02#ibcon#read 4, iclass 17, count 2 2006.253.07:44:28.02#ibcon#about to read 5, iclass 17, count 2 2006.253.07:44:28.02#ibcon#read 5, iclass 17, count 2 2006.253.07:44:28.02#ibcon#about to read 6, iclass 17, count 2 2006.253.07:44:28.02#ibcon#read 6, iclass 17, count 2 2006.253.07:44:28.02#ibcon#end of sib2, iclass 17, count 2 2006.253.07:44:28.02#ibcon#*mode == 0, iclass 17, count 2 2006.253.07:44:28.02#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.253.07:44:28.02#ibcon#[25=AT01-08\r\n] 2006.253.07:44:28.02#ibcon#*before write, iclass 17, count 2 2006.253.07:44:28.02#ibcon#enter sib2, iclass 17, count 2 2006.253.07:44:28.02#ibcon#flushed, iclass 17, count 2 2006.253.07:44:28.02#ibcon#about to write, iclass 17, count 2 2006.253.07:44:28.02#ibcon#wrote, iclass 17, count 2 2006.253.07:44:28.02#ibcon#about to read 3, iclass 17, count 2 2006.253.07:44:28.05#ibcon#read 3, iclass 17, count 2 2006.253.07:44:28.06#ibcon#about to read 4, iclass 17, count 2 2006.253.07:44:28.06#ibcon#read 4, iclass 17, count 2 2006.253.07:44:28.06#ibcon#about to read 5, iclass 17, count 2 2006.253.07:44:28.06#ibcon#read 5, iclass 17, count 2 2006.253.07:44:28.06#ibcon#about to read 6, iclass 17, count 2 2006.253.07:44:28.06#ibcon#read 6, iclass 17, count 2 2006.253.07:44:28.06#ibcon#end of sib2, iclass 17, count 2 2006.253.07:44:28.06#ibcon#*after write, iclass 17, count 2 2006.253.07:44:28.06#ibcon#*before return 0, iclass 17, count 2 2006.253.07:44:28.06#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.253.07:44:28.06#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.253.07:44:28.06#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.253.07:44:28.06#ibcon#ireg 7 cls_cnt 0 2006.253.07:44:28.06#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.253.07:44:28.17#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.253.07:44:28.17#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.253.07:44:28.17#ibcon#enter wrdev, iclass 17, count 0 2006.253.07:44:28.17#ibcon#first serial, iclass 17, count 0 2006.253.07:44:28.17#ibcon#enter sib2, iclass 17, count 0 2006.253.07:44:28.17#ibcon#flushed, iclass 17, count 0 2006.253.07:44:28.18#ibcon#about to write, iclass 17, count 0 2006.253.07:44:28.18#ibcon#wrote, iclass 17, count 0 2006.253.07:44:28.18#ibcon#about to read 3, iclass 17, count 0 2006.253.07:44:28.19#ibcon#read 3, iclass 17, count 0 2006.253.07:44:28.19#ibcon#about to read 4, iclass 17, count 0 2006.253.07:44:28.19#ibcon#read 4, iclass 17, count 0 2006.253.07:44:28.19#ibcon#about to read 5, iclass 17, count 0 2006.253.07:44:28.19#ibcon#read 5, iclass 17, count 0 2006.253.07:44:28.20#ibcon#about to read 6, iclass 17, count 0 2006.253.07:44:28.20#ibcon#read 6, iclass 17, count 0 2006.253.07:44:28.20#ibcon#end of sib2, iclass 17, count 0 2006.253.07:44:28.20#ibcon#*mode == 0, iclass 17, count 0 2006.253.07:44:28.20#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.253.07:44:28.20#ibcon#[25=USB\r\n] 2006.253.07:44:28.20#ibcon#*before write, iclass 17, count 0 2006.253.07:44:28.20#ibcon#enter sib2, iclass 17, count 0 2006.253.07:44:28.20#ibcon#flushed, iclass 17, count 0 2006.253.07:44:28.20#ibcon#about to write, iclass 17, count 0 2006.253.07:44:28.20#ibcon#wrote, iclass 17, count 0 2006.253.07:44:28.20#ibcon#about to read 3, iclass 17, count 0 2006.253.07:44:28.22#ibcon#read 3, iclass 17, count 0 2006.253.07:44:28.22#ibcon#about to read 4, iclass 17, count 0 2006.253.07:44:28.22#ibcon#read 4, iclass 17, count 0 2006.253.07:44:28.22#ibcon#about to read 5, iclass 17, count 0 2006.253.07:44:28.22#ibcon#read 5, iclass 17, count 0 2006.253.07:44:28.23#ibcon#about to read 6, iclass 17, count 0 2006.253.07:44:28.23#ibcon#read 6, iclass 17, count 0 2006.253.07:44:28.23#ibcon#end of sib2, iclass 17, count 0 2006.253.07:44:28.23#ibcon#*after write, iclass 17, count 0 2006.253.07:44:28.23#ibcon#*before return 0, iclass 17, count 0 2006.253.07:44:28.23#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.253.07:44:28.23#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.253.07:44:28.23#ibcon#about to clear, iclass 17 cls_cnt 0 2006.253.07:44:28.23#ibcon#cleared, iclass 17 cls_cnt 0 2006.253.07:44:28.23$vc4f8/valo=2,572.99 2006.253.07:44:28.23#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.253.07:44:28.23#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.253.07:44:28.23#ibcon#ireg 17 cls_cnt 0 2006.253.07:44:28.23#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.253.07:44:28.23#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.253.07:44:28.23#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.253.07:44:28.23#ibcon#enter wrdev, iclass 19, count 0 2006.253.07:44:28.23#ibcon#first serial, iclass 19, count 0 2006.253.07:44:28.23#ibcon#enter sib2, iclass 19, count 0 2006.253.07:44:28.23#ibcon#flushed, iclass 19, count 0 2006.253.07:44:28.23#ibcon#about to write, iclass 19, count 0 2006.253.07:44:28.23#ibcon#wrote, iclass 19, count 0 2006.253.07:44:28.23#ibcon#about to read 3, iclass 19, count 0 2006.253.07:44:28.24#ibcon#read 3, iclass 19, count 0 2006.253.07:44:28.24#ibcon#about to read 4, iclass 19, count 0 2006.253.07:44:28.24#ibcon#read 4, iclass 19, count 0 2006.253.07:44:28.24#ibcon#about to read 5, iclass 19, count 0 2006.253.07:44:28.25#ibcon#read 5, iclass 19, count 0 2006.253.07:44:28.25#ibcon#about to read 6, iclass 19, count 0 2006.253.07:44:28.25#ibcon#read 6, iclass 19, count 0 2006.253.07:44:28.25#ibcon#end of sib2, iclass 19, count 0 2006.253.07:44:28.25#ibcon#*mode == 0, iclass 19, count 0 2006.253.07:44:28.25#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.253.07:44:28.25#ibcon#[26=FRQ=02,572.99\r\n] 2006.253.07:44:28.25#ibcon#*before write, iclass 19, count 0 2006.253.07:44:28.25#ibcon#enter sib2, iclass 19, count 0 2006.253.07:44:28.25#ibcon#flushed, iclass 19, count 0 2006.253.07:44:28.25#ibcon#about to write, iclass 19, count 0 2006.253.07:44:28.25#ibcon#wrote, iclass 19, count 0 2006.253.07:44:28.25#ibcon#about to read 3, iclass 19, count 0 2006.253.07:44:28.28#ibcon#read 3, iclass 19, count 0 2006.253.07:44:28.28#ibcon#about to read 4, iclass 19, count 0 2006.253.07:44:28.28#ibcon#read 4, iclass 19, count 0 2006.253.07:44:28.28#ibcon#about to read 5, iclass 19, count 0 2006.253.07:44:28.28#ibcon#read 5, iclass 19, count 0 2006.253.07:44:28.29#ibcon#about to read 6, iclass 19, count 0 2006.253.07:44:28.29#ibcon#read 6, iclass 19, count 0 2006.253.07:44:28.29#ibcon#end of sib2, iclass 19, count 0 2006.253.07:44:28.29#ibcon#*after write, iclass 19, count 0 2006.253.07:44:28.29#ibcon#*before return 0, iclass 19, count 0 2006.253.07:44:28.29#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.253.07:44:28.29#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.253.07:44:28.29#ibcon#about to clear, iclass 19 cls_cnt 0 2006.253.07:44:28.29#ibcon#cleared, iclass 19 cls_cnt 0 2006.253.07:44:28.29$vc4f8/va=2,7 2006.253.07:44:28.29#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.253.07:44:28.29#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.253.07:44:28.29#ibcon#ireg 11 cls_cnt 2 2006.253.07:44:28.29#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.253.07:44:28.34#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.253.07:44:28.34#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.253.07:44:28.35#ibcon#enter wrdev, iclass 21, count 2 2006.253.07:44:28.35#ibcon#first serial, iclass 21, count 2 2006.253.07:44:28.35#ibcon#enter sib2, iclass 21, count 2 2006.253.07:44:28.35#ibcon#flushed, iclass 21, count 2 2006.253.07:44:28.35#ibcon#about to write, iclass 21, count 2 2006.253.07:44:28.35#ibcon#wrote, iclass 21, count 2 2006.253.07:44:28.35#ibcon#about to read 3, iclass 21, count 2 2006.253.07:44:28.36#ibcon#read 3, iclass 21, count 2 2006.253.07:44:28.36#ibcon#about to read 4, iclass 21, count 2 2006.253.07:44:28.36#ibcon#read 4, iclass 21, count 2 2006.253.07:44:28.36#ibcon#about to read 5, iclass 21, count 2 2006.253.07:44:28.36#ibcon#read 5, iclass 21, count 2 2006.253.07:44:28.37#ibcon#about to read 6, iclass 21, count 2 2006.253.07:44:28.37#ibcon#read 6, iclass 21, count 2 2006.253.07:44:28.37#ibcon#end of sib2, iclass 21, count 2 2006.253.07:44:28.37#ibcon#*mode == 0, iclass 21, count 2 2006.253.07:44:28.37#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.253.07:44:28.37#ibcon#[25=AT02-07\r\n] 2006.253.07:44:28.37#ibcon#*before write, iclass 21, count 2 2006.253.07:44:28.37#ibcon#enter sib2, iclass 21, count 2 2006.253.07:44:28.37#ibcon#flushed, iclass 21, count 2 2006.253.07:44:28.37#ibcon#about to write, iclass 21, count 2 2006.253.07:44:28.37#ibcon#wrote, iclass 21, count 2 2006.253.07:44:28.37#ibcon#about to read 3, iclass 21, count 2 2006.253.07:44:28.39#ibcon#read 3, iclass 21, count 2 2006.253.07:44:28.39#ibcon#about to read 4, iclass 21, count 2 2006.253.07:44:28.39#ibcon#read 4, iclass 21, count 2 2006.253.07:44:28.39#ibcon#about to read 5, iclass 21, count 2 2006.253.07:44:28.39#ibcon#read 5, iclass 21, count 2 2006.253.07:44:28.40#ibcon#about to read 6, iclass 21, count 2 2006.253.07:44:28.40#ibcon#read 6, iclass 21, count 2 2006.253.07:44:28.40#ibcon#end of sib2, iclass 21, count 2 2006.253.07:44:28.40#ibcon#*after write, iclass 21, count 2 2006.253.07:44:28.40#ibcon#*before return 0, iclass 21, count 2 2006.253.07:44:28.40#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.253.07:44:28.40#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.253.07:44:28.40#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.253.07:44:28.40#ibcon#ireg 7 cls_cnt 0 2006.253.07:44:28.40#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.253.07:44:28.52#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.253.07:44:28.52#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.253.07:44:28.52#ibcon#enter wrdev, iclass 21, count 0 2006.253.07:44:28.52#ibcon#first serial, iclass 21, count 0 2006.253.07:44:28.52#ibcon#enter sib2, iclass 21, count 0 2006.253.07:44:28.52#ibcon#flushed, iclass 21, count 0 2006.253.07:44:28.52#ibcon#about to write, iclass 21, count 0 2006.253.07:44:28.52#ibcon#wrote, iclass 21, count 0 2006.253.07:44:28.52#ibcon#about to read 3, iclass 21, count 0 2006.253.07:44:28.53#ibcon#read 3, iclass 21, count 0 2006.253.07:44:28.53#ibcon#about to read 4, iclass 21, count 0 2006.253.07:44:28.53#ibcon#read 4, iclass 21, count 0 2006.253.07:44:28.53#ibcon#about to read 5, iclass 21, count 0 2006.253.07:44:28.54#ibcon#read 5, iclass 21, count 0 2006.253.07:44:28.54#ibcon#about to read 6, iclass 21, count 0 2006.253.07:44:28.54#ibcon#read 6, iclass 21, count 0 2006.253.07:44:28.54#ibcon#end of sib2, iclass 21, count 0 2006.253.07:44:28.54#ibcon#*mode == 0, iclass 21, count 0 2006.253.07:44:28.54#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.253.07:44:28.54#ibcon#[25=USB\r\n] 2006.253.07:44:28.54#ibcon#*before write, iclass 21, count 0 2006.253.07:44:28.54#ibcon#enter sib2, iclass 21, count 0 2006.253.07:44:28.54#ibcon#flushed, iclass 21, count 0 2006.253.07:44:28.54#ibcon#about to write, iclass 21, count 0 2006.253.07:44:28.54#ibcon#wrote, iclass 21, count 0 2006.253.07:44:28.54#ibcon#about to read 3, iclass 21, count 0 2006.253.07:44:28.56#ibcon#read 3, iclass 21, count 0 2006.253.07:44:28.56#ibcon#about to read 4, iclass 21, count 0 2006.253.07:44:28.56#ibcon#read 4, iclass 21, count 0 2006.253.07:44:28.56#ibcon#about to read 5, iclass 21, count 0 2006.253.07:44:28.56#ibcon#read 5, iclass 21, count 0 2006.253.07:44:28.57#ibcon#about to read 6, iclass 21, count 0 2006.253.07:44:28.57#ibcon#read 6, iclass 21, count 0 2006.253.07:44:28.57#ibcon#end of sib2, iclass 21, count 0 2006.253.07:44:28.57#ibcon#*after write, iclass 21, count 0 2006.253.07:44:28.57#ibcon#*before return 0, iclass 21, count 0 2006.253.07:44:28.57#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.253.07:44:28.57#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.253.07:44:28.57#ibcon#about to clear, iclass 21 cls_cnt 0 2006.253.07:44:28.57#ibcon#cleared, iclass 21 cls_cnt 0 2006.253.07:44:28.57$vc4f8/valo=3,672.99 2006.253.07:44:28.57#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.253.07:44:28.57#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.253.07:44:28.57#ibcon#ireg 17 cls_cnt 0 2006.253.07:44:28.57#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.253.07:44:28.57#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.253.07:44:28.57#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.253.07:44:28.57#ibcon#enter wrdev, iclass 23, count 0 2006.253.07:44:28.57#ibcon#first serial, iclass 23, count 0 2006.253.07:44:28.57#ibcon#enter sib2, iclass 23, count 0 2006.253.07:44:28.57#ibcon#flushed, iclass 23, count 0 2006.253.07:44:28.57#ibcon#about to write, iclass 23, count 0 2006.253.07:44:28.57#ibcon#wrote, iclass 23, count 0 2006.253.07:44:28.57#ibcon#about to read 3, iclass 23, count 0 2006.253.07:44:28.59#ibcon#read 3, iclass 23, count 0 2006.253.07:44:28.59#ibcon#about to read 4, iclass 23, count 0 2006.253.07:44:28.59#ibcon#read 4, iclass 23, count 0 2006.253.07:44:28.59#ibcon#about to read 5, iclass 23, count 0 2006.253.07:44:28.59#ibcon#read 5, iclass 23, count 0 2006.253.07:44:28.59#ibcon#about to read 6, iclass 23, count 0 2006.253.07:44:28.59#ibcon#read 6, iclass 23, count 0 2006.253.07:44:28.59#ibcon#end of sib2, iclass 23, count 0 2006.253.07:44:28.59#ibcon#*mode == 0, iclass 23, count 0 2006.253.07:44:28.59#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.253.07:44:28.59#ibcon#[26=FRQ=03,672.99\r\n] 2006.253.07:44:28.59#ibcon#*before write, iclass 23, count 0 2006.253.07:44:28.59#ibcon#enter sib2, iclass 23, count 0 2006.253.07:44:28.59#ibcon#flushed, iclass 23, count 0 2006.253.07:44:28.59#ibcon#about to write, iclass 23, count 0 2006.253.07:44:28.59#ibcon#wrote, iclass 23, count 0 2006.253.07:44:28.59#ibcon#about to read 3, iclass 23, count 0 2006.253.07:44:28.63#ibcon#read 3, iclass 23, count 0 2006.253.07:44:28.63#ibcon#about to read 4, iclass 23, count 0 2006.253.07:44:28.64#ibcon#read 4, iclass 23, count 0 2006.253.07:44:28.64#ibcon#about to read 5, iclass 23, count 0 2006.253.07:44:28.64#ibcon#read 5, iclass 23, count 0 2006.253.07:44:28.64#ibcon#about to read 6, iclass 23, count 0 2006.253.07:44:28.64#ibcon#read 6, iclass 23, count 0 2006.253.07:44:28.64#ibcon#end of sib2, iclass 23, count 0 2006.253.07:44:28.64#ibcon#*after write, iclass 23, count 0 2006.253.07:44:28.64#ibcon#*before return 0, iclass 23, count 0 2006.253.07:44:28.64#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.253.07:44:28.64#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.253.07:44:28.64#ibcon#about to clear, iclass 23 cls_cnt 0 2006.253.07:44:28.64#ibcon#cleared, iclass 23 cls_cnt 0 2006.253.07:44:28.64$vc4f8/va=3,6 2006.253.07:44:28.64#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.253.07:44:28.64#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.253.07:44:28.64#ibcon#ireg 11 cls_cnt 2 2006.253.07:44:28.64#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.253.07:44:28.69#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.253.07:44:28.69#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.253.07:44:28.69#ibcon#enter wrdev, iclass 25, count 2 2006.253.07:44:28.69#ibcon#first serial, iclass 25, count 2 2006.253.07:44:28.69#ibcon#enter sib2, iclass 25, count 2 2006.253.07:44:28.69#ibcon#flushed, iclass 25, count 2 2006.253.07:44:28.69#ibcon#about to write, iclass 25, count 2 2006.253.07:44:28.69#ibcon#wrote, iclass 25, count 2 2006.253.07:44:28.69#ibcon#about to read 3, iclass 25, count 2 2006.253.07:44:28.70#ibcon#read 3, iclass 25, count 2 2006.253.07:44:28.70#ibcon#about to read 4, iclass 25, count 2 2006.253.07:44:28.70#ibcon#read 4, iclass 25, count 2 2006.253.07:44:28.70#ibcon#about to read 5, iclass 25, count 2 2006.253.07:44:28.70#ibcon#read 5, iclass 25, count 2 2006.253.07:44:28.71#ibcon#about to read 6, iclass 25, count 2 2006.253.07:44:28.71#ibcon#read 6, iclass 25, count 2 2006.253.07:44:28.71#ibcon#end of sib2, iclass 25, count 2 2006.253.07:44:28.71#ibcon#*mode == 0, iclass 25, count 2 2006.253.07:44:28.71#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.253.07:44:28.71#ibcon#[25=AT03-06\r\n] 2006.253.07:44:28.71#ibcon#*before write, iclass 25, count 2 2006.253.07:44:28.71#ibcon#enter sib2, iclass 25, count 2 2006.253.07:44:28.71#ibcon#flushed, iclass 25, count 2 2006.253.07:44:28.71#ibcon#about to write, iclass 25, count 2 2006.253.07:44:28.71#ibcon#wrote, iclass 25, count 2 2006.253.07:44:28.71#ibcon#about to read 3, iclass 25, count 2 2006.253.07:44:28.73#ibcon#read 3, iclass 25, count 2 2006.253.07:44:28.73#ibcon#about to read 4, iclass 25, count 2 2006.253.07:44:28.74#ibcon#read 4, iclass 25, count 2 2006.253.07:44:28.74#ibcon#about to read 5, iclass 25, count 2 2006.253.07:44:28.74#ibcon#read 5, iclass 25, count 2 2006.253.07:44:28.74#ibcon#about to read 6, iclass 25, count 2 2006.253.07:44:28.74#ibcon#read 6, iclass 25, count 2 2006.253.07:44:28.74#ibcon#end of sib2, iclass 25, count 2 2006.253.07:44:28.74#ibcon#*after write, iclass 25, count 2 2006.253.07:44:28.74#ibcon#*before return 0, iclass 25, count 2 2006.253.07:44:28.74#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.253.07:44:28.74#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.253.07:44:28.74#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.253.07:44:28.74#ibcon#ireg 7 cls_cnt 0 2006.253.07:44:28.74#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.253.07:44:28.85#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.253.07:44:28.85#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.253.07:44:28.85#ibcon#enter wrdev, iclass 25, count 0 2006.253.07:44:28.85#ibcon#first serial, iclass 25, count 0 2006.253.07:44:28.85#ibcon#enter sib2, iclass 25, count 0 2006.253.07:44:28.85#ibcon#flushed, iclass 25, count 0 2006.253.07:44:28.85#ibcon#about to write, iclass 25, count 0 2006.253.07:44:28.86#ibcon#wrote, iclass 25, count 0 2006.253.07:44:28.86#ibcon#about to read 3, iclass 25, count 0 2006.253.07:44:28.87#ibcon#read 3, iclass 25, count 0 2006.253.07:44:28.87#ibcon#about to read 4, iclass 25, count 0 2006.253.07:44:28.87#ibcon#read 4, iclass 25, count 0 2006.253.07:44:28.87#ibcon#about to read 5, iclass 25, count 0 2006.253.07:44:28.87#ibcon#read 5, iclass 25, count 0 2006.253.07:44:28.88#ibcon#about to read 6, iclass 25, count 0 2006.253.07:44:28.88#ibcon#read 6, iclass 25, count 0 2006.253.07:44:28.88#ibcon#end of sib2, iclass 25, count 0 2006.253.07:44:28.88#ibcon#*mode == 0, iclass 25, count 0 2006.253.07:44:28.88#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.253.07:44:28.88#ibcon#[25=USB\r\n] 2006.253.07:44:28.88#ibcon#*before write, iclass 25, count 0 2006.253.07:44:28.88#ibcon#enter sib2, iclass 25, count 0 2006.253.07:44:28.88#ibcon#flushed, iclass 25, count 0 2006.253.07:44:28.88#ibcon#about to write, iclass 25, count 0 2006.253.07:44:28.88#ibcon#wrote, iclass 25, count 0 2006.253.07:44:28.88#ibcon#about to read 3, iclass 25, count 0 2006.253.07:44:28.90#ibcon#read 3, iclass 25, count 0 2006.253.07:44:28.90#ibcon#about to read 4, iclass 25, count 0 2006.253.07:44:28.90#ibcon#read 4, iclass 25, count 0 2006.253.07:44:28.90#ibcon#about to read 5, iclass 25, count 0 2006.253.07:44:28.90#ibcon#read 5, iclass 25, count 0 2006.253.07:44:28.91#ibcon#about to read 6, iclass 25, count 0 2006.253.07:44:28.91#ibcon#read 6, iclass 25, count 0 2006.253.07:44:28.91#ibcon#end of sib2, iclass 25, count 0 2006.253.07:44:28.91#ibcon#*after write, iclass 25, count 0 2006.253.07:44:28.91#ibcon#*before return 0, iclass 25, count 0 2006.253.07:44:28.91#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.253.07:44:28.91#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.253.07:44:28.91#ibcon#about to clear, iclass 25 cls_cnt 0 2006.253.07:44:28.91#ibcon#cleared, iclass 25 cls_cnt 0 2006.253.07:44:28.91$vc4f8/valo=4,832.99 2006.253.07:44:28.91#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.253.07:44:28.91#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.253.07:44:28.91#ibcon#ireg 17 cls_cnt 0 2006.253.07:44:28.91#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.253.07:44:28.91#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.253.07:44:28.91#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.253.07:44:28.91#ibcon#enter wrdev, iclass 27, count 0 2006.253.07:44:28.91#ibcon#first serial, iclass 27, count 0 2006.253.07:44:28.91#ibcon#enter sib2, iclass 27, count 0 2006.253.07:44:28.91#ibcon#flushed, iclass 27, count 0 2006.253.07:44:28.91#ibcon#about to write, iclass 27, count 0 2006.253.07:44:28.91#ibcon#wrote, iclass 27, count 0 2006.253.07:44:28.91#ibcon#about to read 3, iclass 27, count 0 2006.253.07:44:28.92#ibcon#read 3, iclass 27, count 0 2006.253.07:44:28.92#ibcon#about to read 4, iclass 27, count 0 2006.253.07:44:28.92#ibcon#read 4, iclass 27, count 0 2006.253.07:44:28.92#ibcon#about to read 5, iclass 27, count 0 2006.253.07:44:28.92#ibcon#read 5, iclass 27, count 0 2006.253.07:44:28.93#ibcon#about to read 6, iclass 27, count 0 2006.253.07:44:28.93#ibcon#read 6, iclass 27, count 0 2006.253.07:44:28.93#ibcon#end of sib2, iclass 27, count 0 2006.253.07:44:28.93#ibcon#*mode == 0, iclass 27, count 0 2006.253.07:44:28.93#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.253.07:44:28.93#ibcon#[26=FRQ=04,832.99\r\n] 2006.253.07:44:28.93#ibcon#*before write, iclass 27, count 0 2006.253.07:44:28.93#ibcon#enter sib2, iclass 27, count 0 2006.253.07:44:28.93#ibcon#flushed, iclass 27, count 0 2006.253.07:44:28.93#ibcon#about to write, iclass 27, count 0 2006.253.07:44:28.93#ibcon#wrote, iclass 27, count 0 2006.253.07:44:28.93#ibcon#about to read 3, iclass 27, count 0 2006.253.07:44:28.96#ibcon#read 3, iclass 27, count 0 2006.253.07:44:28.96#ibcon#about to read 4, iclass 27, count 0 2006.253.07:44:28.96#ibcon#read 4, iclass 27, count 0 2006.253.07:44:28.96#ibcon#about to read 5, iclass 27, count 0 2006.253.07:44:28.97#ibcon#read 5, iclass 27, count 0 2006.253.07:44:28.97#ibcon#about to read 6, iclass 27, count 0 2006.253.07:44:28.97#ibcon#read 6, iclass 27, count 0 2006.253.07:44:28.97#ibcon#end of sib2, iclass 27, count 0 2006.253.07:44:28.97#ibcon#*after write, iclass 27, count 0 2006.253.07:44:28.97#ibcon#*before return 0, iclass 27, count 0 2006.253.07:44:28.97#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.253.07:44:28.97#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.253.07:44:28.97#ibcon#about to clear, iclass 27 cls_cnt 0 2006.253.07:44:28.97#ibcon#cleared, iclass 27 cls_cnt 0 2006.253.07:44:28.97$vc4f8/va=4,7 2006.253.07:44:28.97#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.253.07:44:28.97#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.253.07:44:28.97#ibcon#ireg 11 cls_cnt 2 2006.253.07:44:28.97#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.253.07:44:29.02#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.253.07:44:29.02#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.253.07:44:29.02#ibcon#enter wrdev, iclass 29, count 2 2006.253.07:44:29.02#ibcon#first serial, iclass 29, count 2 2006.253.07:44:29.02#ibcon#enter sib2, iclass 29, count 2 2006.253.07:44:29.02#ibcon#flushed, iclass 29, count 2 2006.253.07:44:29.03#ibcon#about to write, iclass 29, count 2 2006.253.07:44:29.03#ibcon#wrote, iclass 29, count 2 2006.253.07:44:29.03#ibcon#about to read 3, iclass 29, count 2 2006.253.07:44:29.04#ibcon#read 3, iclass 29, count 2 2006.253.07:44:29.04#ibcon#about to read 4, iclass 29, count 2 2006.253.07:44:29.04#ibcon#read 4, iclass 29, count 2 2006.253.07:44:29.04#ibcon#about to read 5, iclass 29, count 2 2006.253.07:44:29.04#ibcon#read 5, iclass 29, count 2 2006.253.07:44:29.04#ibcon#about to read 6, iclass 29, count 2 2006.253.07:44:29.05#ibcon#read 6, iclass 29, count 2 2006.253.07:44:29.05#ibcon#end of sib2, iclass 29, count 2 2006.253.07:44:29.05#ibcon#*mode == 0, iclass 29, count 2 2006.253.07:44:29.05#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.253.07:44:29.05#ibcon#[25=AT04-07\r\n] 2006.253.07:44:29.05#ibcon#*before write, iclass 29, count 2 2006.253.07:44:29.05#ibcon#enter sib2, iclass 29, count 2 2006.253.07:44:29.05#ibcon#flushed, iclass 29, count 2 2006.253.07:44:29.05#ibcon#about to write, iclass 29, count 2 2006.253.07:44:29.05#ibcon#wrote, iclass 29, count 2 2006.253.07:44:29.05#ibcon#about to read 3, iclass 29, count 2 2006.253.07:44:29.07#ibcon#read 3, iclass 29, count 2 2006.253.07:44:29.07#ibcon#about to read 4, iclass 29, count 2 2006.253.07:44:29.08#ibcon#read 4, iclass 29, count 2 2006.253.07:44:29.08#ibcon#about to read 5, iclass 29, count 2 2006.253.07:44:29.08#ibcon#read 5, iclass 29, count 2 2006.253.07:44:29.08#ibcon#about to read 6, iclass 29, count 2 2006.253.07:44:29.08#ibcon#read 6, iclass 29, count 2 2006.253.07:44:29.08#ibcon#end of sib2, iclass 29, count 2 2006.253.07:44:29.08#ibcon#*after write, iclass 29, count 2 2006.253.07:44:29.08#ibcon#*before return 0, iclass 29, count 2 2006.253.07:44:29.08#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.253.07:44:29.08#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.253.07:44:29.08#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.253.07:44:29.08#ibcon#ireg 7 cls_cnt 0 2006.253.07:44:29.08#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.253.07:44:29.19#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.253.07:44:29.19#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.253.07:44:29.19#ibcon#enter wrdev, iclass 29, count 0 2006.253.07:44:29.19#ibcon#first serial, iclass 29, count 0 2006.253.07:44:29.19#ibcon#enter sib2, iclass 29, count 0 2006.253.07:44:29.19#ibcon#flushed, iclass 29, count 0 2006.253.07:44:29.20#ibcon#about to write, iclass 29, count 0 2006.253.07:44:29.20#ibcon#wrote, iclass 29, count 0 2006.253.07:44:29.20#ibcon#about to read 3, iclass 29, count 0 2006.253.07:44:29.21#ibcon#read 3, iclass 29, count 0 2006.253.07:44:29.21#ibcon#about to read 4, iclass 29, count 0 2006.253.07:44:29.21#ibcon#read 4, iclass 29, count 0 2006.253.07:44:29.21#ibcon#about to read 5, iclass 29, count 0 2006.253.07:44:29.21#ibcon#read 5, iclass 29, count 0 2006.253.07:44:29.22#ibcon#about to read 6, iclass 29, count 0 2006.253.07:44:29.22#ibcon#read 6, iclass 29, count 0 2006.253.07:44:29.22#ibcon#end of sib2, iclass 29, count 0 2006.253.07:44:29.22#ibcon#*mode == 0, iclass 29, count 0 2006.253.07:44:29.22#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.253.07:44:29.22#ibcon#[25=USB\r\n] 2006.253.07:44:29.22#ibcon#*before write, iclass 29, count 0 2006.253.07:44:29.22#ibcon#enter sib2, iclass 29, count 0 2006.253.07:44:29.22#ibcon#flushed, iclass 29, count 0 2006.253.07:44:29.22#ibcon#about to write, iclass 29, count 0 2006.253.07:44:29.22#ibcon#wrote, iclass 29, count 0 2006.253.07:44:29.22#ibcon#about to read 3, iclass 29, count 0 2006.253.07:44:29.24#ibcon#read 3, iclass 29, count 0 2006.253.07:44:29.24#ibcon#about to read 4, iclass 29, count 0 2006.253.07:44:29.24#ibcon#read 4, iclass 29, count 0 2006.253.07:44:29.24#ibcon#about to read 5, iclass 29, count 0 2006.253.07:44:29.25#ibcon#read 5, iclass 29, count 0 2006.253.07:44:29.25#ibcon#about to read 6, iclass 29, count 0 2006.253.07:44:29.25#ibcon#read 6, iclass 29, count 0 2006.253.07:44:29.25#ibcon#end of sib2, iclass 29, count 0 2006.253.07:44:29.25#ibcon#*after write, iclass 29, count 0 2006.253.07:44:29.25#ibcon#*before return 0, iclass 29, count 0 2006.253.07:44:29.25#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.253.07:44:29.25#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.253.07:44:29.25#ibcon#about to clear, iclass 29 cls_cnt 0 2006.253.07:44:29.25#ibcon#cleared, iclass 29 cls_cnt 0 2006.253.07:44:29.25$vc4f8/valo=5,652.99 2006.253.07:44:29.25#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.253.07:44:29.25#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.253.07:44:29.25#ibcon#ireg 17 cls_cnt 0 2006.253.07:44:29.25#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.253.07:44:29.25#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.253.07:44:29.25#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.253.07:44:29.25#ibcon#enter wrdev, iclass 31, count 0 2006.253.07:44:29.25#ibcon#first serial, iclass 31, count 0 2006.253.07:44:29.25#ibcon#enter sib2, iclass 31, count 0 2006.253.07:44:29.25#ibcon#flushed, iclass 31, count 0 2006.253.07:44:29.25#ibcon#about to write, iclass 31, count 0 2006.253.07:44:29.25#ibcon#wrote, iclass 31, count 0 2006.253.07:44:29.25#ibcon#about to read 3, iclass 31, count 0 2006.253.07:44:29.26#ibcon#read 3, iclass 31, count 0 2006.253.07:44:29.26#ibcon#about to read 4, iclass 31, count 0 2006.253.07:44:29.26#ibcon#read 4, iclass 31, count 0 2006.253.07:44:29.26#ibcon#about to read 5, iclass 31, count 0 2006.253.07:44:29.27#ibcon#read 5, iclass 31, count 0 2006.253.07:44:29.27#ibcon#about to read 6, iclass 31, count 0 2006.253.07:44:29.27#ibcon#read 6, iclass 31, count 0 2006.253.07:44:29.27#ibcon#end of sib2, iclass 31, count 0 2006.253.07:44:29.27#ibcon#*mode == 0, iclass 31, count 0 2006.253.07:44:29.27#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.253.07:44:29.27#ibcon#[26=FRQ=05,652.99\r\n] 2006.253.07:44:29.27#ibcon#*before write, iclass 31, count 0 2006.253.07:44:29.27#ibcon#enter sib2, iclass 31, count 0 2006.253.07:44:29.27#ibcon#flushed, iclass 31, count 0 2006.253.07:44:29.27#ibcon#about to write, iclass 31, count 0 2006.253.07:44:29.27#ibcon#wrote, iclass 31, count 0 2006.253.07:44:29.27#ibcon#about to read 3, iclass 31, count 0 2006.253.07:44:29.30#ibcon#read 3, iclass 31, count 0 2006.253.07:44:29.30#ibcon#about to read 4, iclass 31, count 0 2006.253.07:44:29.30#ibcon#read 4, iclass 31, count 0 2006.253.07:44:29.30#ibcon#about to read 5, iclass 31, count 0 2006.253.07:44:29.31#ibcon#read 5, iclass 31, count 0 2006.253.07:44:29.31#ibcon#about to read 6, iclass 31, count 0 2006.253.07:44:29.31#ibcon#read 6, iclass 31, count 0 2006.253.07:44:29.31#ibcon#end of sib2, iclass 31, count 0 2006.253.07:44:29.31#ibcon#*after write, iclass 31, count 0 2006.253.07:44:29.31#ibcon#*before return 0, iclass 31, count 0 2006.253.07:44:29.31#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.253.07:44:29.31#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.253.07:44:29.31#ibcon#about to clear, iclass 31 cls_cnt 0 2006.253.07:44:29.31#ibcon#cleared, iclass 31 cls_cnt 0 2006.253.07:44:29.31$vc4f8/va=5,7 2006.253.07:44:29.31#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.253.07:44:29.31#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.253.07:44:29.31#ibcon#ireg 11 cls_cnt 2 2006.253.07:44:29.31#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.253.07:44:29.36#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.253.07:44:29.36#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.253.07:44:29.36#ibcon#enter wrdev, iclass 33, count 2 2006.253.07:44:29.36#ibcon#first serial, iclass 33, count 2 2006.253.07:44:29.36#ibcon#enter sib2, iclass 33, count 2 2006.253.07:44:29.36#ibcon#flushed, iclass 33, count 2 2006.253.07:44:29.37#ibcon#about to write, iclass 33, count 2 2006.253.07:44:29.37#ibcon#wrote, iclass 33, count 2 2006.253.07:44:29.37#ibcon#about to read 3, iclass 33, count 2 2006.253.07:44:29.38#ibcon#read 3, iclass 33, count 2 2006.253.07:44:29.38#ibcon#about to read 4, iclass 33, count 2 2006.253.07:44:29.38#ibcon#read 4, iclass 33, count 2 2006.253.07:44:29.39#ibcon#about to read 5, iclass 33, count 2 2006.253.07:44:29.39#ibcon#read 5, iclass 33, count 2 2006.253.07:44:29.39#ibcon#about to read 6, iclass 33, count 2 2006.253.07:44:29.39#ibcon#read 6, iclass 33, count 2 2006.253.07:44:29.39#ibcon#end of sib2, iclass 33, count 2 2006.253.07:44:29.39#ibcon#*mode == 0, iclass 33, count 2 2006.253.07:44:29.39#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.253.07:44:29.39#ibcon#[25=AT05-07\r\n] 2006.253.07:44:29.39#ibcon#*before write, iclass 33, count 2 2006.253.07:44:29.39#ibcon#enter sib2, iclass 33, count 2 2006.253.07:44:29.39#ibcon#flushed, iclass 33, count 2 2006.253.07:44:29.39#ibcon#about to write, iclass 33, count 2 2006.253.07:44:29.39#ibcon#wrote, iclass 33, count 2 2006.253.07:44:29.39#ibcon#about to read 3, iclass 33, count 2 2006.253.07:44:29.41#ibcon#read 3, iclass 33, count 2 2006.253.07:44:29.41#ibcon#about to read 4, iclass 33, count 2 2006.253.07:44:29.41#ibcon#read 4, iclass 33, count 2 2006.253.07:44:29.42#ibcon#about to read 5, iclass 33, count 2 2006.253.07:44:29.42#ibcon#read 5, iclass 33, count 2 2006.253.07:44:29.42#ibcon#about to read 6, iclass 33, count 2 2006.253.07:44:29.42#ibcon#read 6, iclass 33, count 2 2006.253.07:44:29.42#ibcon#end of sib2, iclass 33, count 2 2006.253.07:44:29.42#ibcon#*after write, iclass 33, count 2 2006.253.07:44:29.42#ibcon#*before return 0, iclass 33, count 2 2006.253.07:44:29.42#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.253.07:44:29.42#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.253.07:44:29.42#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.253.07:44:29.42#ibcon#ireg 7 cls_cnt 0 2006.253.07:44:29.42#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.253.07:44:29.53#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.253.07:44:29.53#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.253.07:44:29.53#ibcon#enter wrdev, iclass 33, count 0 2006.253.07:44:29.53#ibcon#first serial, iclass 33, count 0 2006.253.07:44:29.53#ibcon#enter sib2, iclass 33, count 0 2006.253.07:44:29.53#ibcon#flushed, iclass 33, count 0 2006.253.07:44:29.54#ibcon#about to write, iclass 33, count 0 2006.253.07:44:29.54#ibcon#wrote, iclass 33, count 0 2006.253.07:44:29.54#ibcon#about to read 3, iclass 33, count 0 2006.253.07:44:29.55#ibcon#read 3, iclass 33, count 0 2006.253.07:44:29.55#ibcon#about to read 4, iclass 33, count 0 2006.253.07:44:29.55#ibcon#read 4, iclass 33, count 0 2006.253.07:44:29.55#ibcon#about to read 5, iclass 33, count 0 2006.253.07:44:29.55#ibcon#read 5, iclass 33, count 0 2006.253.07:44:29.56#ibcon#about to read 6, iclass 33, count 0 2006.253.07:44:29.56#ibcon#read 6, iclass 33, count 0 2006.253.07:44:29.56#ibcon#end of sib2, iclass 33, count 0 2006.253.07:44:29.56#ibcon#*mode == 0, iclass 33, count 0 2006.253.07:44:29.56#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.253.07:44:29.56#ibcon#[25=USB\r\n] 2006.253.07:44:29.56#ibcon#*before write, iclass 33, count 0 2006.253.07:44:29.56#ibcon#enter sib2, iclass 33, count 0 2006.253.07:44:29.56#ibcon#flushed, iclass 33, count 0 2006.253.07:44:29.56#ibcon#about to write, iclass 33, count 0 2006.253.07:44:29.56#ibcon#wrote, iclass 33, count 0 2006.253.07:44:29.56#ibcon#about to read 3, iclass 33, count 0 2006.253.07:44:29.58#ibcon#read 3, iclass 33, count 0 2006.253.07:44:29.58#ibcon#about to read 4, iclass 33, count 0 2006.253.07:44:29.58#ibcon#read 4, iclass 33, count 0 2006.253.07:44:29.58#ibcon#about to read 5, iclass 33, count 0 2006.253.07:44:29.58#ibcon#read 5, iclass 33, count 0 2006.253.07:44:29.59#ibcon#about to read 6, iclass 33, count 0 2006.253.07:44:29.59#ibcon#read 6, iclass 33, count 0 2006.253.07:44:29.59#ibcon#end of sib2, iclass 33, count 0 2006.253.07:44:29.59#ibcon#*after write, iclass 33, count 0 2006.253.07:44:29.59#ibcon#*before return 0, iclass 33, count 0 2006.253.07:44:29.59#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.253.07:44:29.59#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.253.07:44:29.59#ibcon#about to clear, iclass 33 cls_cnt 0 2006.253.07:44:29.59#ibcon#cleared, iclass 33 cls_cnt 0 2006.253.07:44:29.59$vc4f8/valo=6,772.99 2006.253.07:44:29.59#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.253.07:44:29.59#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.253.07:44:29.59#ibcon#ireg 17 cls_cnt 0 2006.253.07:44:29.59#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.253.07:44:29.59#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.253.07:44:29.59#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.253.07:44:29.59#ibcon#enter wrdev, iclass 35, count 0 2006.253.07:44:29.59#ibcon#first serial, iclass 35, count 0 2006.253.07:44:29.59#ibcon#enter sib2, iclass 35, count 0 2006.253.07:44:29.59#ibcon#flushed, iclass 35, count 0 2006.253.07:44:29.59#ibcon#about to write, iclass 35, count 0 2006.253.07:44:29.59#ibcon#wrote, iclass 35, count 0 2006.253.07:44:29.59#ibcon#about to read 3, iclass 35, count 0 2006.253.07:44:29.60#ibcon#read 3, iclass 35, count 0 2006.253.07:44:29.60#ibcon#about to read 4, iclass 35, count 0 2006.253.07:44:29.60#ibcon#read 4, iclass 35, count 0 2006.253.07:44:29.60#ibcon#about to read 5, iclass 35, count 0 2006.253.07:44:29.60#ibcon#read 5, iclass 35, count 0 2006.253.07:44:29.61#ibcon#about to read 6, iclass 35, count 0 2006.253.07:44:29.61#ibcon#read 6, iclass 35, count 0 2006.253.07:44:29.61#ibcon#end of sib2, iclass 35, count 0 2006.253.07:44:29.61#ibcon#*mode == 0, iclass 35, count 0 2006.253.07:44:29.61#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.253.07:44:29.61#ibcon#[26=FRQ=06,772.99\r\n] 2006.253.07:44:29.61#ibcon#*before write, iclass 35, count 0 2006.253.07:44:29.61#ibcon#enter sib2, iclass 35, count 0 2006.253.07:44:29.61#ibcon#flushed, iclass 35, count 0 2006.253.07:44:29.61#ibcon#about to write, iclass 35, count 0 2006.253.07:44:29.61#ibcon#wrote, iclass 35, count 0 2006.253.07:44:29.61#ibcon#about to read 3, iclass 35, count 0 2006.253.07:44:29.64#ibcon#read 3, iclass 35, count 0 2006.253.07:44:29.64#ibcon#about to read 4, iclass 35, count 0 2006.253.07:44:29.64#ibcon#read 4, iclass 35, count 0 2006.253.07:44:29.64#ibcon#about to read 5, iclass 35, count 0 2006.253.07:44:29.65#ibcon#read 5, iclass 35, count 0 2006.253.07:44:29.65#ibcon#about to read 6, iclass 35, count 0 2006.253.07:44:29.65#ibcon#read 6, iclass 35, count 0 2006.253.07:44:29.65#ibcon#end of sib2, iclass 35, count 0 2006.253.07:44:29.65#ibcon#*after write, iclass 35, count 0 2006.253.07:44:29.65#ibcon#*before return 0, iclass 35, count 0 2006.253.07:44:29.65#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.253.07:44:29.65#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.253.07:44:29.65#ibcon#about to clear, iclass 35 cls_cnt 0 2006.253.07:44:29.65#ibcon#cleared, iclass 35 cls_cnt 0 2006.253.07:44:29.65$vc4f8/va=6,7 2006.253.07:44:29.65#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.253.07:44:29.65#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.253.07:44:29.65#ibcon#ireg 11 cls_cnt 2 2006.253.07:44:29.65#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.253.07:44:29.70#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.253.07:44:29.70#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.253.07:44:29.70#ibcon#enter wrdev, iclass 37, count 2 2006.253.07:44:29.70#ibcon#first serial, iclass 37, count 2 2006.253.07:44:29.70#ibcon#enter sib2, iclass 37, count 2 2006.253.07:44:29.70#ibcon#flushed, iclass 37, count 2 2006.253.07:44:29.71#ibcon#about to write, iclass 37, count 2 2006.253.07:44:29.71#ibcon#wrote, iclass 37, count 2 2006.253.07:44:29.71#ibcon#about to read 3, iclass 37, count 2 2006.253.07:44:29.72#ibcon#read 3, iclass 37, count 2 2006.253.07:44:29.72#ibcon#about to read 4, iclass 37, count 2 2006.253.07:44:29.72#ibcon#read 4, iclass 37, count 2 2006.253.07:44:29.72#ibcon#about to read 5, iclass 37, count 2 2006.253.07:44:29.72#ibcon#read 5, iclass 37, count 2 2006.253.07:44:29.73#ibcon#about to read 6, iclass 37, count 2 2006.253.07:44:29.73#ibcon#read 6, iclass 37, count 2 2006.253.07:44:29.73#ibcon#end of sib2, iclass 37, count 2 2006.253.07:44:29.73#ibcon#*mode == 0, iclass 37, count 2 2006.253.07:44:29.73#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.253.07:44:29.73#ibcon#[25=AT06-07\r\n] 2006.253.07:44:29.73#ibcon#*before write, iclass 37, count 2 2006.253.07:44:29.73#ibcon#enter sib2, iclass 37, count 2 2006.253.07:44:29.73#ibcon#flushed, iclass 37, count 2 2006.253.07:44:29.73#ibcon#about to write, iclass 37, count 2 2006.253.07:44:29.73#ibcon#wrote, iclass 37, count 2 2006.253.07:44:29.73#ibcon#about to read 3, iclass 37, count 2 2006.253.07:44:29.75#ibcon#read 3, iclass 37, count 2 2006.253.07:44:29.75#ibcon#about to read 4, iclass 37, count 2 2006.253.07:44:29.75#ibcon#read 4, iclass 37, count 2 2006.253.07:44:29.76#ibcon#about to read 5, iclass 37, count 2 2006.253.07:44:29.76#ibcon#read 5, iclass 37, count 2 2006.253.07:44:29.76#ibcon#about to read 6, iclass 37, count 2 2006.253.07:44:29.76#ibcon#read 6, iclass 37, count 2 2006.253.07:44:29.76#ibcon#end of sib2, iclass 37, count 2 2006.253.07:44:29.76#ibcon#*after write, iclass 37, count 2 2006.253.07:44:29.76#ibcon#*before return 0, iclass 37, count 2 2006.253.07:44:29.76#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.253.07:44:29.76#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.253.07:44:29.76#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.253.07:44:29.76#ibcon#ireg 7 cls_cnt 0 2006.253.07:44:29.76#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.253.07:44:29.87#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.253.07:44:29.87#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.253.07:44:29.87#ibcon#enter wrdev, iclass 37, count 0 2006.253.07:44:29.87#ibcon#first serial, iclass 37, count 0 2006.253.07:44:29.87#ibcon#enter sib2, iclass 37, count 0 2006.253.07:44:29.87#ibcon#flushed, iclass 37, count 0 2006.253.07:44:29.87#ibcon#about to write, iclass 37, count 0 2006.253.07:44:29.88#ibcon#wrote, iclass 37, count 0 2006.253.07:44:29.88#ibcon#about to read 3, iclass 37, count 0 2006.253.07:44:29.89#ibcon#read 3, iclass 37, count 0 2006.253.07:44:29.89#ibcon#about to read 4, iclass 37, count 0 2006.253.07:44:29.89#ibcon#read 4, iclass 37, count 0 2006.253.07:44:29.89#ibcon#about to read 5, iclass 37, count 0 2006.253.07:44:29.89#ibcon#read 5, iclass 37, count 0 2006.253.07:44:29.90#ibcon#about to read 6, iclass 37, count 0 2006.253.07:44:29.90#ibcon#read 6, iclass 37, count 0 2006.253.07:44:29.90#ibcon#end of sib2, iclass 37, count 0 2006.253.07:44:29.90#ibcon#*mode == 0, iclass 37, count 0 2006.253.07:44:29.90#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.253.07:44:29.90#ibcon#[25=USB\r\n] 2006.253.07:44:29.90#ibcon#*before write, iclass 37, count 0 2006.253.07:44:29.90#ibcon#enter sib2, iclass 37, count 0 2006.253.07:44:29.90#ibcon#flushed, iclass 37, count 0 2006.253.07:44:29.90#ibcon#about to write, iclass 37, count 0 2006.253.07:44:29.90#ibcon#wrote, iclass 37, count 0 2006.253.07:44:29.90#ibcon#about to read 3, iclass 37, count 0 2006.253.07:44:29.92#ibcon#read 3, iclass 37, count 0 2006.253.07:44:29.92#ibcon#about to read 4, iclass 37, count 0 2006.253.07:44:29.92#ibcon#read 4, iclass 37, count 0 2006.253.07:44:29.92#ibcon#about to read 5, iclass 37, count 0 2006.253.07:44:29.92#ibcon#read 5, iclass 37, count 0 2006.253.07:44:29.93#ibcon#about to read 6, iclass 37, count 0 2006.253.07:44:29.93#ibcon#read 6, iclass 37, count 0 2006.253.07:44:29.93#ibcon#end of sib2, iclass 37, count 0 2006.253.07:44:29.93#ibcon#*after write, iclass 37, count 0 2006.253.07:44:29.93#ibcon#*before return 0, iclass 37, count 0 2006.253.07:44:29.93#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.253.07:44:29.93#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.253.07:44:29.93#ibcon#about to clear, iclass 37 cls_cnt 0 2006.253.07:44:29.93#ibcon#cleared, iclass 37 cls_cnt 0 2006.253.07:44:29.93$vc4f8/valo=7,832.99 2006.253.07:44:29.93#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.253.07:44:29.93#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.253.07:44:29.93#ibcon#ireg 17 cls_cnt 0 2006.253.07:44:29.93#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.253.07:44:29.93#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.253.07:44:29.93#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.253.07:44:29.93#ibcon#enter wrdev, iclass 39, count 0 2006.253.07:44:29.93#ibcon#first serial, iclass 39, count 0 2006.253.07:44:29.93#ibcon#enter sib2, iclass 39, count 0 2006.253.07:44:29.93#ibcon#flushed, iclass 39, count 0 2006.253.07:44:29.93#ibcon#about to write, iclass 39, count 0 2006.253.07:44:29.93#ibcon#wrote, iclass 39, count 0 2006.253.07:44:29.93#ibcon#about to read 3, iclass 39, count 0 2006.253.07:44:29.94#ibcon#read 3, iclass 39, count 0 2006.253.07:44:29.94#ibcon#about to read 4, iclass 39, count 0 2006.253.07:44:29.94#ibcon#read 4, iclass 39, count 0 2006.253.07:44:29.94#ibcon#about to read 5, iclass 39, count 0 2006.253.07:44:29.94#ibcon#read 5, iclass 39, count 0 2006.253.07:44:29.94#ibcon#about to read 6, iclass 39, count 0 2006.253.07:44:29.95#ibcon#read 6, iclass 39, count 0 2006.253.07:44:29.95#ibcon#end of sib2, iclass 39, count 0 2006.253.07:44:29.95#ibcon#*mode == 0, iclass 39, count 0 2006.253.07:44:29.95#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.253.07:44:29.95#ibcon#[26=FRQ=07,832.99\r\n] 2006.253.07:44:29.95#ibcon#*before write, iclass 39, count 0 2006.253.07:44:29.95#ibcon#enter sib2, iclass 39, count 0 2006.253.07:44:29.95#ibcon#flushed, iclass 39, count 0 2006.253.07:44:29.95#ibcon#about to write, iclass 39, count 0 2006.253.07:44:29.95#ibcon#wrote, iclass 39, count 0 2006.253.07:44:29.95#ibcon#about to read 3, iclass 39, count 0 2006.253.07:44:29.98#ibcon#read 3, iclass 39, count 0 2006.253.07:44:29.98#ibcon#about to read 4, iclass 39, count 0 2006.253.07:44:29.98#ibcon#read 4, iclass 39, count 0 2006.253.07:44:29.98#ibcon#about to read 5, iclass 39, count 0 2006.253.07:44:29.99#ibcon#read 5, iclass 39, count 0 2006.253.07:44:29.99#ibcon#about to read 6, iclass 39, count 0 2006.253.07:44:29.99#ibcon#read 6, iclass 39, count 0 2006.253.07:44:29.99#ibcon#end of sib2, iclass 39, count 0 2006.253.07:44:29.99#ibcon#*after write, iclass 39, count 0 2006.253.07:44:29.99#ibcon#*before return 0, iclass 39, count 0 2006.253.07:44:29.99#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.253.07:44:29.99#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.253.07:44:29.99#ibcon#about to clear, iclass 39 cls_cnt 0 2006.253.07:44:29.99#ibcon#cleared, iclass 39 cls_cnt 0 2006.253.07:44:29.99$vc4f8/va=7,7 2006.253.07:44:29.99#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.253.07:44:29.99#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.253.07:44:29.99#ibcon#ireg 11 cls_cnt 2 2006.253.07:44:29.99#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.253.07:44:30.05#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.253.07:44:30.05#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.253.07:44:30.05#ibcon#enter wrdev, iclass 3, count 2 2006.253.07:44:30.05#ibcon#first serial, iclass 3, count 2 2006.253.07:44:30.05#ibcon#enter sib2, iclass 3, count 2 2006.253.07:44:30.05#ibcon#flushed, iclass 3, count 2 2006.253.07:44:30.05#ibcon#about to write, iclass 3, count 2 2006.253.07:44:30.05#ibcon#wrote, iclass 3, count 2 2006.253.07:44:30.05#ibcon#about to read 3, iclass 3, count 2 2006.253.07:44:30.06#ibcon#read 3, iclass 3, count 2 2006.253.07:44:30.06#ibcon#about to read 4, iclass 3, count 2 2006.253.07:44:30.06#ibcon#read 4, iclass 3, count 2 2006.253.07:44:30.06#ibcon#about to read 5, iclass 3, count 2 2006.253.07:44:30.07#ibcon#read 5, iclass 3, count 2 2006.253.07:44:30.07#ibcon#about to read 6, iclass 3, count 2 2006.253.07:44:30.07#ibcon#read 6, iclass 3, count 2 2006.253.07:44:30.07#ibcon#end of sib2, iclass 3, count 2 2006.253.07:44:30.07#ibcon#*mode == 0, iclass 3, count 2 2006.253.07:44:30.07#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.253.07:44:30.07#ibcon#[25=AT07-07\r\n] 2006.253.07:44:30.07#ibcon#*before write, iclass 3, count 2 2006.253.07:44:30.07#ibcon#enter sib2, iclass 3, count 2 2006.253.07:44:30.07#ibcon#flushed, iclass 3, count 2 2006.253.07:44:30.07#ibcon#about to write, iclass 3, count 2 2006.253.07:44:30.07#ibcon#wrote, iclass 3, count 2 2006.253.07:44:30.07#ibcon#about to read 3, iclass 3, count 2 2006.253.07:44:30.09#ibcon#read 3, iclass 3, count 2 2006.253.07:44:30.09#ibcon#about to read 4, iclass 3, count 2 2006.253.07:44:30.09#ibcon#read 4, iclass 3, count 2 2006.253.07:44:30.10#ibcon#about to read 5, iclass 3, count 2 2006.253.07:44:30.10#ibcon#read 5, iclass 3, count 2 2006.253.07:44:30.10#ibcon#about to read 6, iclass 3, count 2 2006.253.07:44:30.10#ibcon#read 6, iclass 3, count 2 2006.253.07:44:30.10#ibcon#end of sib2, iclass 3, count 2 2006.253.07:44:30.10#ibcon#*after write, iclass 3, count 2 2006.253.07:44:30.10#ibcon#*before return 0, iclass 3, count 2 2006.253.07:44:30.10#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.253.07:44:30.10#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.253.07:44:30.10#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.253.07:44:30.10#ibcon#ireg 7 cls_cnt 0 2006.253.07:44:30.10#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.253.07:44:30.21#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.253.07:44:30.21#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.253.07:44:30.21#ibcon#enter wrdev, iclass 3, count 0 2006.253.07:44:30.21#ibcon#first serial, iclass 3, count 0 2006.253.07:44:30.21#ibcon#enter sib2, iclass 3, count 0 2006.253.07:44:30.21#ibcon#flushed, iclass 3, count 0 2006.253.07:44:30.21#ibcon#about to write, iclass 3, count 0 2006.253.07:44:30.22#ibcon#wrote, iclass 3, count 0 2006.253.07:44:30.22#ibcon#about to read 3, iclass 3, count 0 2006.253.07:44:30.25#ibcon#read 3, iclass 3, count 0 2006.253.07:44:30.25#ibcon#about to read 4, iclass 3, count 0 2006.253.07:44:30.25#ibcon#read 4, iclass 3, count 0 2006.253.07:44:30.25#ibcon#about to read 5, iclass 3, count 0 2006.253.07:44:30.25#ibcon#read 5, iclass 3, count 0 2006.253.07:44:30.25#ibcon#about to read 6, iclass 3, count 0 2006.253.07:44:30.25#ibcon#read 6, iclass 3, count 0 2006.253.07:44:30.25#ibcon#end of sib2, iclass 3, count 0 2006.253.07:44:30.25#ibcon#*mode == 0, iclass 3, count 0 2006.253.07:44:30.25#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.253.07:44:30.25#ibcon#[25=USB\r\n] 2006.253.07:44:30.25#ibcon#*before write, iclass 3, count 0 2006.253.07:44:30.25#ibcon#enter sib2, iclass 3, count 0 2006.253.07:44:30.25#ibcon#flushed, iclass 3, count 0 2006.253.07:44:30.25#ibcon#about to write, iclass 3, count 0 2006.253.07:44:30.25#ibcon#wrote, iclass 3, count 0 2006.253.07:44:30.25#ibcon#about to read 3, iclass 3, count 0 2006.253.07:44:30.27#ibcon#read 3, iclass 3, count 0 2006.253.07:44:30.27#ibcon#about to read 4, iclass 3, count 0 2006.253.07:44:30.27#ibcon#read 4, iclass 3, count 0 2006.253.07:44:30.28#ibcon#about to read 5, iclass 3, count 0 2006.253.07:44:30.28#ibcon#read 5, iclass 3, count 0 2006.253.07:44:30.28#ibcon#about to read 6, iclass 3, count 0 2006.253.07:44:30.28#ibcon#read 6, iclass 3, count 0 2006.253.07:44:30.28#ibcon#end of sib2, iclass 3, count 0 2006.253.07:44:30.28#ibcon#*after write, iclass 3, count 0 2006.253.07:44:30.28#ibcon#*before return 0, iclass 3, count 0 2006.253.07:44:30.28#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.253.07:44:30.28#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.253.07:44:30.28#ibcon#about to clear, iclass 3 cls_cnt 0 2006.253.07:44:30.28#ibcon#cleared, iclass 3 cls_cnt 0 2006.253.07:44:30.28$vc4f8/valo=8,852.99 2006.253.07:44:30.28#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.253.07:44:30.28#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.253.07:44:30.28#ibcon#ireg 17 cls_cnt 0 2006.253.07:44:30.28#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.253.07:44:30.28#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.253.07:44:30.28#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.253.07:44:30.28#ibcon#enter wrdev, iclass 5, count 0 2006.253.07:44:30.28#ibcon#first serial, iclass 5, count 0 2006.253.07:44:30.28#ibcon#enter sib2, iclass 5, count 0 2006.253.07:44:30.28#ibcon#flushed, iclass 5, count 0 2006.253.07:44:30.28#ibcon#about to write, iclass 5, count 0 2006.253.07:44:30.28#ibcon#wrote, iclass 5, count 0 2006.253.07:44:30.28#ibcon#about to read 3, iclass 5, count 0 2006.253.07:44:30.29#ibcon#read 3, iclass 5, count 0 2006.253.07:44:30.29#ibcon#about to read 4, iclass 5, count 0 2006.253.07:44:30.29#ibcon#read 4, iclass 5, count 0 2006.253.07:44:30.29#ibcon#about to read 5, iclass 5, count 0 2006.253.07:44:30.29#ibcon#read 5, iclass 5, count 0 2006.253.07:44:30.30#ibcon#about to read 6, iclass 5, count 0 2006.253.07:44:30.30#ibcon#read 6, iclass 5, count 0 2006.253.07:44:30.30#ibcon#end of sib2, iclass 5, count 0 2006.253.07:44:30.30#ibcon#*mode == 0, iclass 5, count 0 2006.253.07:44:30.30#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.253.07:44:30.30#ibcon#[26=FRQ=08,852.99\r\n] 2006.253.07:44:30.30#ibcon#*before write, iclass 5, count 0 2006.253.07:44:30.30#ibcon#enter sib2, iclass 5, count 0 2006.253.07:44:30.30#ibcon#flushed, iclass 5, count 0 2006.253.07:44:30.30#ibcon#about to write, iclass 5, count 0 2006.253.07:44:30.30#ibcon#wrote, iclass 5, count 0 2006.253.07:44:30.30#ibcon#about to read 3, iclass 5, count 0 2006.253.07:44:30.33#ibcon#read 3, iclass 5, count 0 2006.253.07:44:30.33#ibcon#about to read 4, iclass 5, count 0 2006.253.07:44:30.33#ibcon#read 4, iclass 5, count 0 2006.253.07:44:30.33#ibcon#about to read 5, iclass 5, count 0 2006.253.07:44:30.33#ibcon#read 5, iclass 5, count 0 2006.253.07:44:30.33#ibcon#about to read 6, iclass 5, count 0 2006.253.07:44:30.34#ibcon#read 6, iclass 5, count 0 2006.253.07:44:30.34#ibcon#end of sib2, iclass 5, count 0 2006.253.07:44:30.34#ibcon#*after write, iclass 5, count 0 2006.253.07:44:30.34#ibcon#*before return 0, iclass 5, count 0 2006.253.07:44:30.34#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.253.07:44:30.34#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.253.07:44:30.34#ibcon#about to clear, iclass 5 cls_cnt 0 2006.253.07:44:30.34#ibcon#cleared, iclass 5 cls_cnt 0 2006.253.07:44:30.34$vc4f8/va=8,7 2006.253.07:44:30.34#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.253.07:44:30.34#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.253.07:44:30.34#ibcon#ireg 11 cls_cnt 2 2006.253.07:44:30.34#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.253.07:44:30.39#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.253.07:44:30.39#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.253.07:44:30.39#ibcon#enter wrdev, iclass 7, count 2 2006.253.07:44:30.39#ibcon#first serial, iclass 7, count 2 2006.253.07:44:30.39#ibcon#enter sib2, iclass 7, count 2 2006.253.07:44:30.39#ibcon#flushed, iclass 7, count 2 2006.253.07:44:30.39#ibcon#about to write, iclass 7, count 2 2006.253.07:44:30.40#ibcon#wrote, iclass 7, count 2 2006.253.07:44:30.40#ibcon#about to read 3, iclass 7, count 2 2006.253.07:44:30.41#ibcon#read 3, iclass 7, count 2 2006.253.07:44:30.41#ibcon#about to read 4, iclass 7, count 2 2006.253.07:44:30.41#ibcon#read 4, iclass 7, count 2 2006.253.07:44:30.41#ibcon#about to read 5, iclass 7, count 2 2006.253.07:44:30.41#ibcon#read 5, iclass 7, count 2 2006.253.07:44:30.42#ibcon#about to read 6, iclass 7, count 2 2006.253.07:44:30.42#ibcon#read 6, iclass 7, count 2 2006.253.07:44:30.42#ibcon#end of sib2, iclass 7, count 2 2006.253.07:44:30.42#ibcon#*mode == 0, iclass 7, count 2 2006.253.07:44:30.42#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.253.07:44:30.42#ibcon#[25=AT08-07\r\n] 2006.253.07:44:30.42#ibcon#*before write, iclass 7, count 2 2006.253.07:44:30.42#ibcon#enter sib2, iclass 7, count 2 2006.253.07:44:30.42#ibcon#flushed, iclass 7, count 2 2006.253.07:44:30.42#ibcon#about to write, iclass 7, count 2 2006.253.07:44:30.42#ibcon#wrote, iclass 7, count 2 2006.253.07:44:30.42#ibcon#about to read 3, iclass 7, count 2 2006.253.07:44:30.44#ibcon#read 3, iclass 7, count 2 2006.253.07:44:30.44#ibcon#about to read 4, iclass 7, count 2 2006.253.07:44:30.44#ibcon#read 4, iclass 7, count 2 2006.253.07:44:30.44#ibcon#about to read 5, iclass 7, count 2 2006.253.07:44:30.44#ibcon#read 5, iclass 7, count 2 2006.253.07:44:30.44#ibcon#about to read 6, iclass 7, count 2 2006.253.07:44:30.45#ibcon#read 6, iclass 7, count 2 2006.253.07:44:30.45#ibcon#end of sib2, iclass 7, count 2 2006.253.07:44:30.45#ibcon#*after write, iclass 7, count 2 2006.253.07:44:30.45#ibcon#*before return 0, iclass 7, count 2 2006.253.07:44:30.45#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.253.07:44:30.45#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.253.07:44:30.45#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.253.07:44:30.45#ibcon#ireg 7 cls_cnt 0 2006.253.07:44:30.45#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.253.07:44:30.56#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.253.07:44:30.56#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.253.07:44:30.56#ibcon#enter wrdev, iclass 7, count 0 2006.253.07:44:30.56#ibcon#first serial, iclass 7, count 0 2006.253.07:44:30.56#ibcon#enter sib2, iclass 7, count 0 2006.253.07:44:30.56#ibcon#flushed, iclass 7, count 0 2006.253.07:44:30.57#ibcon#about to write, iclass 7, count 0 2006.253.07:44:30.57#ibcon#wrote, iclass 7, count 0 2006.253.07:44:30.57#ibcon#about to read 3, iclass 7, count 0 2006.253.07:44:30.58#ibcon#read 3, iclass 7, count 0 2006.253.07:44:30.58#ibcon#about to read 4, iclass 7, count 0 2006.253.07:44:30.58#ibcon#read 4, iclass 7, count 0 2006.253.07:44:30.58#ibcon#about to read 5, iclass 7, count 0 2006.253.07:44:30.58#ibcon#read 5, iclass 7, count 0 2006.253.07:44:30.58#ibcon#about to read 6, iclass 7, count 0 2006.253.07:44:30.59#ibcon#read 6, iclass 7, count 0 2006.253.07:44:30.59#ibcon#end of sib2, iclass 7, count 0 2006.253.07:44:30.59#ibcon#*mode == 0, iclass 7, count 0 2006.253.07:44:30.59#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.253.07:44:30.59#ibcon#[25=USB\r\n] 2006.253.07:44:30.59#ibcon#*before write, iclass 7, count 0 2006.253.07:44:30.59#ibcon#enter sib2, iclass 7, count 0 2006.253.07:44:30.59#ibcon#flushed, iclass 7, count 0 2006.253.07:44:30.59#ibcon#about to write, iclass 7, count 0 2006.253.07:44:30.59#ibcon#wrote, iclass 7, count 0 2006.253.07:44:30.59#ibcon#about to read 3, iclass 7, count 0 2006.253.07:44:30.61#ibcon#read 3, iclass 7, count 0 2006.253.07:44:30.61#ibcon#about to read 4, iclass 7, count 0 2006.253.07:44:30.61#ibcon#read 4, iclass 7, count 0 2006.253.07:44:30.61#ibcon#about to read 5, iclass 7, count 0 2006.253.07:44:30.61#ibcon#read 5, iclass 7, count 0 2006.253.07:44:30.61#ibcon#about to read 6, iclass 7, count 0 2006.253.07:44:30.62#ibcon#read 6, iclass 7, count 0 2006.253.07:44:30.62#ibcon#end of sib2, iclass 7, count 0 2006.253.07:44:30.62#ibcon#*after write, iclass 7, count 0 2006.253.07:44:30.62#ibcon#*before return 0, iclass 7, count 0 2006.253.07:44:30.62#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.253.07:44:30.62#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.253.07:44:30.62#ibcon#about to clear, iclass 7 cls_cnt 0 2006.253.07:44:30.62#ibcon#cleared, iclass 7 cls_cnt 0 2006.253.07:44:30.62$vc4f8/vblo=1,632.99 2006.253.07:44:30.62#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.253.07:44:30.62#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.253.07:44:30.62#ibcon#ireg 17 cls_cnt 0 2006.253.07:44:30.62#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.253.07:44:30.62#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.253.07:44:30.62#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.253.07:44:30.62#ibcon#enter wrdev, iclass 11, count 0 2006.253.07:44:30.62#ibcon#first serial, iclass 11, count 0 2006.253.07:44:30.62#ibcon#enter sib2, iclass 11, count 0 2006.253.07:44:30.62#ibcon#flushed, iclass 11, count 0 2006.253.07:44:30.62#ibcon#about to write, iclass 11, count 0 2006.253.07:44:30.62#ibcon#wrote, iclass 11, count 0 2006.253.07:44:30.62#ibcon#about to read 3, iclass 11, count 0 2006.253.07:44:30.63#ibcon#read 3, iclass 11, count 0 2006.253.07:44:30.63#ibcon#about to read 4, iclass 11, count 0 2006.253.07:44:30.63#ibcon#read 4, iclass 11, count 0 2006.253.07:44:30.63#ibcon#about to read 5, iclass 11, count 0 2006.253.07:44:30.63#ibcon#read 5, iclass 11, count 0 2006.253.07:44:30.63#ibcon#about to read 6, iclass 11, count 0 2006.253.07:44:30.64#ibcon#read 6, iclass 11, count 0 2006.253.07:44:30.64#ibcon#end of sib2, iclass 11, count 0 2006.253.07:44:30.64#ibcon#*mode == 0, iclass 11, count 0 2006.253.07:44:30.64#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.253.07:44:30.64#ibcon#[28=FRQ=01,632.99\r\n] 2006.253.07:44:30.64#ibcon#*before write, iclass 11, count 0 2006.253.07:44:30.64#ibcon#enter sib2, iclass 11, count 0 2006.253.07:44:30.64#ibcon#flushed, iclass 11, count 0 2006.253.07:44:30.64#ibcon#about to write, iclass 11, count 0 2006.253.07:44:30.64#ibcon#wrote, iclass 11, count 0 2006.253.07:44:30.64#ibcon#about to read 3, iclass 11, count 0 2006.253.07:44:30.67#ibcon#read 3, iclass 11, count 0 2006.253.07:44:30.67#ibcon#about to read 4, iclass 11, count 0 2006.253.07:44:30.67#ibcon#read 4, iclass 11, count 0 2006.253.07:44:30.67#ibcon#about to read 5, iclass 11, count 0 2006.253.07:44:30.68#ibcon#read 5, iclass 11, count 0 2006.253.07:44:30.68#ibcon#about to read 6, iclass 11, count 0 2006.253.07:44:30.68#ibcon#read 6, iclass 11, count 0 2006.253.07:44:30.68#ibcon#end of sib2, iclass 11, count 0 2006.253.07:44:30.68#ibcon#*after write, iclass 11, count 0 2006.253.07:44:30.68#ibcon#*before return 0, iclass 11, count 0 2006.253.07:44:30.68#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.253.07:44:30.68#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.253.07:44:30.68#ibcon#about to clear, iclass 11 cls_cnt 0 2006.253.07:44:30.68#ibcon#cleared, iclass 11 cls_cnt 0 2006.253.07:44:30.68$vc4f8/vb=1,4 2006.253.07:44:30.68#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.253.07:44:30.68#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.253.07:44:30.68#ibcon#ireg 11 cls_cnt 2 2006.253.07:44:30.68#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.253.07:44:30.68#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.253.07:44:30.68#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.253.07:44:30.68#ibcon#enter wrdev, iclass 13, count 2 2006.253.07:44:30.68#ibcon#first serial, iclass 13, count 2 2006.253.07:44:30.68#ibcon#enter sib2, iclass 13, count 2 2006.253.07:44:30.68#ibcon#flushed, iclass 13, count 2 2006.253.07:44:30.68#ibcon#about to write, iclass 13, count 2 2006.253.07:44:30.68#ibcon#wrote, iclass 13, count 2 2006.253.07:44:30.68#ibcon#about to read 3, iclass 13, count 2 2006.253.07:44:30.69#ibcon#read 3, iclass 13, count 2 2006.253.07:44:30.69#ibcon#about to read 4, iclass 13, count 2 2006.253.07:44:30.69#ibcon#read 4, iclass 13, count 2 2006.253.07:44:30.69#ibcon#about to read 5, iclass 13, count 2 2006.253.07:44:30.69#ibcon#read 5, iclass 13, count 2 2006.253.07:44:30.70#ibcon#about to read 6, iclass 13, count 2 2006.253.07:44:30.70#ibcon#read 6, iclass 13, count 2 2006.253.07:44:30.70#ibcon#end of sib2, iclass 13, count 2 2006.253.07:44:30.70#ibcon#*mode == 0, iclass 13, count 2 2006.253.07:44:30.70#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.253.07:44:30.70#ibcon#[27=AT01-04\r\n] 2006.253.07:44:30.70#ibcon#*before write, iclass 13, count 2 2006.253.07:44:30.70#ibcon#enter sib2, iclass 13, count 2 2006.253.07:44:30.70#ibcon#flushed, iclass 13, count 2 2006.253.07:44:30.70#ibcon#about to write, iclass 13, count 2 2006.253.07:44:30.70#ibcon#wrote, iclass 13, count 2 2006.253.07:44:30.70#ibcon#about to read 3, iclass 13, count 2 2006.253.07:44:30.72#ibcon#read 3, iclass 13, count 2 2006.253.07:44:30.72#ibcon#about to read 4, iclass 13, count 2 2006.253.07:44:30.72#ibcon#read 4, iclass 13, count 2 2006.253.07:44:30.72#ibcon#about to read 5, iclass 13, count 2 2006.253.07:44:30.72#ibcon#read 5, iclass 13, count 2 2006.253.07:44:30.72#ibcon#about to read 6, iclass 13, count 2 2006.253.07:44:30.73#ibcon#read 6, iclass 13, count 2 2006.253.07:44:30.73#ibcon#end of sib2, iclass 13, count 2 2006.253.07:44:30.73#ibcon#*after write, iclass 13, count 2 2006.253.07:44:30.73#ibcon#*before return 0, iclass 13, count 2 2006.253.07:44:30.73#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.253.07:44:30.73#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.253.07:44:30.73#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.253.07:44:30.73#ibcon#ireg 7 cls_cnt 0 2006.253.07:44:30.73#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.253.07:44:30.85#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.253.07:44:30.85#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.253.07:44:30.85#ibcon#enter wrdev, iclass 13, count 0 2006.253.07:44:30.85#ibcon#first serial, iclass 13, count 0 2006.253.07:44:30.85#ibcon#enter sib2, iclass 13, count 0 2006.253.07:44:30.85#ibcon#flushed, iclass 13, count 0 2006.253.07:44:30.85#ibcon#about to write, iclass 13, count 0 2006.253.07:44:30.85#ibcon#wrote, iclass 13, count 0 2006.253.07:44:30.85#ibcon#about to read 3, iclass 13, count 0 2006.253.07:44:30.86#ibcon#read 3, iclass 13, count 0 2006.253.07:44:30.86#ibcon#about to read 4, iclass 13, count 0 2006.253.07:44:30.86#ibcon#read 4, iclass 13, count 0 2006.253.07:44:30.86#ibcon#about to read 5, iclass 13, count 0 2006.253.07:44:30.86#ibcon#read 5, iclass 13, count 0 2006.253.07:44:30.87#ibcon#about to read 6, iclass 13, count 0 2006.253.07:44:30.87#ibcon#read 6, iclass 13, count 0 2006.253.07:44:30.87#ibcon#end of sib2, iclass 13, count 0 2006.253.07:44:30.87#ibcon#*mode == 0, iclass 13, count 0 2006.253.07:44:30.87#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.253.07:44:30.87#ibcon#[27=USB\r\n] 2006.253.07:44:30.87#ibcon#*before write, iclass 13, count 0 2006.253.07:44:30.87#ibcon#enter sib2, iclass 13, count 0 2006.253.07:44:30.87#ibcon#flushed, iclass 13, count 0 2006.253.07:44:30.87#ibcon#about to write, iclass 13, count 0 2006.253.07:44:30.87#ibcon#wrote, iclass 13, count 0 2006.253.07:44:30.87#ibcon#about to read 3, iclass 13, count 0 2006.253.07:44:30.89#ibcon#read 3, iclass 13, count 0 2006.253.07:44:30.89#ibcon#about to read 4, iclass 13, count 0 2006.253.07:44:30.89#ibcon#read 4, iclass 13, count 0 2006.253.07:44:30.89#ibcon#about to read 5, iclass 13, count 0 2006.253.07:44:30.89#ibcon#read 5, iclass 13, count 0 2006.253.07:44:30.90#ibcon#about to read 6, iclass 13, count 0 2006.253.07:44:30.90#ibcon#read 6, iclass 13, count 0 2006.253.07:44:30.90#ibcon#end of sib2, iclass 13, count 0 2006.253.07:44:30.90#ibcon#*after write, iclass 13, count 0 2006.253.07:44:30.90#ibcon#*before return 0, iclass 13, count 0 2006.253.07:44:30.90#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.253.07:44:30.90#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.253.07:44:30.90#ibcon#about to clear, iclass 13 cls_cnt 0 2006.253.07:44:30.90#ibcon#cleared, iclass 13 cls_cnt 0 2006.253.07:44:30.90$vc4f8/vblo=2,640.99 2006.253.07:44:30.90#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.253.07:44:30.90#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.253.07:44:30.90#ibcon#ireg 17 cls_cnt 0 2006.253.07:44:30.90#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.253.07:44:30.90#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.253.07:44:30.90#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.253.07:44:30.90#ibcon#enter wrdev, iclass 15, count 0 2006.253.07:44:30.90#ibcon#first serial, iclass 15, count 0 2006.253.07:44:30.90#ibcon#enter sib2, iclass 15, count 0 2006.253.07:44:30.90#ibcon#flushed, iclass 15, count 0 2006.253.07:44:30.90#ibcon#about to write, iclass 15, count 0 2006.253.07:44:30.90#ibcon#wrote, iclass 15, count 0 2006.253.07:44:30.90#ibcon#about to read 3, iclass 15, count 0 2006.253.07:44:30.92#ibcon#read 3, iclass 15, count 0 2006.253.07:44:30.92#ibcon#about to read 4, iclass 15, count 0 2006.253.07:44:30.92#ibcon#read 4, iclass 15, count 0 2006.253.07:44:30.92#ibcon#about to read 5, iclass 15, count 0 2006.253.07:44:30.92#ibcon#read 5, iclass 15, count 0 2006.253.07:44:30.92#ibcon#about to read 6, iclass 15, count 0 2006.253.07:44:30.92#ibcon#read 6, iclass 15, count 0 2006.253.07:44:30.92#ibcon#end of sib2, iclass 15, count 0 2006.253.07:44:30.92#ibcon#*mode == 0, iclass 15, count 0 2006.253.07:44:30.92#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.253.07:44:30.92#ibcon#[28=FRQ=02,640.99\r\n] 2006.253.07:44:30.92#ibcon#*before write, iclass 15, count 0 2006.253.07:44:30.92#ibcon#enter sib2, iclass 15, count 0 2006.253.07:44:30.92#ibcon#flushed, iclass 15, count 0 2006.253.07:44:30.92#ibcon#about to write, iclass 15, count 0 2006.253.07:44:30.92#ibcon#wrote, iclass 15, count 0 2006.253.07:44:30.92#ibcon#about to read 3, iclass 15, count 0 2006.253.07:44:30.96#ibcon#read 3, iclass 15, count 0 2006.253.07:44:30.96#ibcon#about to read 4, iclass 15, count 0 2006.253.07:44:30.97#ibcon#read 4, iclass 15, count 0 2006.253.07:44:30.97#ibcon#about to read 5, iclass 15, count 0 2006.253.07:44:30.97#ibcon#read 5, iclass 15, count 0 2006.253.07:44:30.97#ibcon#about to read 6, iclass 15, count 0 2006.253.07:44:30.97#ibcon#read 6, iclass 15, count 0 2006.253.07:44:30.97#ibcon#end of sib2, iclass 15, count 0 2006.253.07:44:30.97#ibcon#*after write, iclass 15, count 0 2006.253.07:44:30.97#ibcon#*before return 0, iclass 15, count 0 2006.253.07:44:30.97#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.253.07:44:30.97#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.253.07:44:30.97#ibcon#about to clear, iclass 15 cls_cnt 0 2006.253.07:44:30.97#ibcon#cleared, iclass 15 cls_cnt 0 2006.253.07:44:30.97$vc4f8/vb=2,5 2006.253.07:44:30.97#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.253.07:44:30.97#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.253.07:44:30.97#ibcon#ireg 11 cls_cnt 2 2006.253.07:44:30.97#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.253.07:44:31.01#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.253.07:44:31.01#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.253.07:44:31.01#ibcon#enter wrdev, iclass 17, count 2 2006.253.07:44:31.01#ibcon#first serial, iclass 17, count 2 2006.253.07:44:31.01#ibcon#enter sib2, iclass 17, count 2 2006.253.07:44:31.01#ibcon#flushed, iclass 17, count 2 2006.253.07:44:31.01#ibcon#about to write, iclass 17, count 2 2006.253.07:44:31.02#ibcon#wrote, iclass 17, count 2 2006.253.07:44:31.02#ibcon#about to read 3, iclass 17, count 2 2006.253.07:44:31.03#ibcon#read 3, iclass 17, count 2 2006.253.07:44:31.03#ibcon#about to read 4, iclass 17, count 2 2006.253.07:44:31.03#ibcon#read 4, iclass 17, count 2 2006.253.07:44:31.03#ibcon#about to read 5, iclass 17, count 2 2006.253.07:44:31.03#ibcon#read 5, iclass 17, count 2 2006.253.07:44:31.03#ibcon#about to read 6, iclass 17, count 2 2006.253.07:44:31.04#ibcon#read 6, iclass 17, count 2 2006.253.07:44:31.04#ibcon#end of sib2, iclass 17, count 2 2006.253.07:44:31.04#ibcon#*mode == 0, iclass 17, count 2 2006.253.07:44:31.04#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.253.07:44:31.04#ibcon#[27=AT02-05\r\n] 2006.253.07:44:31.04#ibcon#*before write, iclass 17, count 2 2006.253.07:44:31.04#ibcon#enter sib2, iclass 17, count 2 2006.253.07:44:31.04#ibcon#flushed, iclass 17, count 2 2006.253.07:44:31.04#ibcon#about to write, iclass 17, count 2 2006.253.07:44:31.04#ibcon#wrote, iclass 17, count 2 2006.253.07:44:31.04#ibcon#about to read 3, iclass 17, count 2 2006.253.07:44:31.06#ibcon#read 3, iclass 17, count 2 2006.253.07:44:31.06#ibcon#about to read 4, iclass 17, count 2 2006.253.07:44:31.06#ibcon#read 4, iclass 17, count 2 2006.253.07:44:31.07#ibcon#about to read 5, iclass 17, count 2 2006.253.07:44:31.07#ibcon#read 5, iclass 17, count 2 2006.253.07:44:31.07#ibcon#about to read 6, iclass 17, count 2 2006.253.07:44:31.07#ibcon#read 6, iclass 17, count 2 2006.253.07:44:31.07#ibcon#end of sib2, iclass 17, count 2 2006.253.07:44:31.07#ibcon#*after write, iclass 17, count 2 2006.253.07:44:31.07#ibcon#*before return 0, iclass 17, count 2 2006.253.07:44:31.07#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.253.07:44:31.07#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.253.07:44:31.07#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.253.07:44:31.07#ibcon#ireg 7 cls_cnt 0 2006.253.07:44:31.07#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.253.07:44:31.18#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.253.07:44:31.18#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.253.07:44:31.18#ibcon#enter wrdev, iclass 17, count 0 2006.253.07:44:31.18#ibcon#first serial, iclass 17, count 0 2006.253.07:44:31.18#ibcon#enter sib2, iclass 17, count 0 2006.253.07:44:31.18#ibcon#flushed, iclass 17, count 0 2006.253.07:44:31.18#ibcon#about to write, iclass 17, count 0 2006.253.07:44:31.19#ibcon#wrote, iclass 17, count 0 2006.253.07:44:31.19#ibcon#about to read 3, iclass 17, count 0 2006.253.07:44:31.20#ibcon#read 3, iclass 17, count 0 2006.253.07:44:31.20#ibcon#about to read 4, iclass 17, count 0 2006.253.07:44:31.20#ibcon#read 4, iclass 17, count 0 2006.253.07:44:31.20#ibcon#about to read 5, iclass 17, count 0 2006.253.07:44:31.20#ibcon#read 5, iclass 17, count 0 2006.253.07:44:31.20#ibcon#about to read 6, iclass 17, count 0 2006.253.07:44:31.21#ibcon#read 6, iclass 17, count 0 2006.253.07:44:31.21#ibcon#end of sib2, iclass 17, count 0 2006.253.07:44:31.21#ibcon#*mode == 0, iclass 17, count 0 2006.253.07:44:31.21#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.253.07:44:31.21#ibcon#[27=USB\r\n] 2006.253.07:44:31.21#ibcon#*before write, iclass 17, count 0 2006.253.07:44:31.21#ibcon#enter sib2, iclass 17, count 0 2006.253.07:44:31.21#ibcon#flushed, iclass 17, count 0 2006.253.07:44:31.21#ibcon#about to write, iclass 17, count 0 2006.253.07:44:31.21#ibcon#wrote, iclass 17, count 0 2006.253.07:44:31.21#ibcon#about to read 3, iclass 17, count 0 2006.253.07:44:31.23#ibcon#read 3, iclass 17, count 0 2006.253.07:44:31.23#ibcon#about to read 4, iclass 17, count 0 2006.253.07:44:31.23#ibcon#read 4, iclass 17, count 0 2006.253.07:44:31.23#ibcon#about to read 5, iclass 17, count 0 2006.253.07:44:31.24#ibcon#read 5, iclass 17, count 0 2006.253.07:44:31.24#ibcon#about to read 6, iclass 17, count 0 2006.253.07:44:31.24#ibcon#read 6, iclass 17, count 0 2006.253.07:44:31.24#ibcon#end of sib2, iclass 17, count 0 2006.253.07:44:31.24#ibcon#*after write, iclass 17, count 0 2006.253.07:44:31.24#ibcon#*before return 0, iclass 17, count 0 2006.253.07:44:31.24#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.253.07:44:31.24#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.253.07:44:31.24#ibcon#about to clear, iclass 17 cls_cnt 0 2006.253.07:44:31.24#ibcon#cleared, iclass 17 cls_cnt 0 2006.253.07:44:31.24$vc4f8/vblo=3,656.99 2006.253.07:44:31.24#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.253.07:44:31.24#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.253.07:44:31.24#ibcon#ireg 17 cls_cnt 0 2006.253.07:44:31.24#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.253.07:44:31.24#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.253.07:44:31.24#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.253.07:44:31.24#ibcon#enter wrdev, iclass 19, count 0 2006.253.07:44:31.24#ibcon#first serial, iclass 19, count 0 2006.253.07:44:31.24#ibcon#enter sib2, iclass 19, count 0 2006.253.07:44:31.24#ibcon#flushed, iclass 19, count 0 2006.253.07:44:31.24#ibcon#about to write, iclass 19, count 0 2006.253.07:44:31.24#ibcon#wrote, iclass 19, count 0 2006.253.07:44:31.24#ibcon#about to read 3, iclass 19, count 0 2006.253.07:44:31.25#ibcon#read 3, iclass 19, count 0 2006.253.07:44:31.25#ibcon#about to read 4, iclass 19, count 0 2006.253.07:44:31.25#ibcon#read 4, iclass 19, count 0 2006.253.07:44:31.25#ibcon#about to read 5, iclass 19, count 0 2006.253.07:44:31.25#ibcon#read 5, iclass 19, count 0 2006.253.07:44:31.26#ibcon#about to read 6, iclass 19, count 0 2006.253.07:44:31.26#ibcon#read 6, iclass 19, count 0 2006.253.07:44:31.26#ibcon#end of sib2, iclass 19, count 0 2006.253.07:44:31.26#ibcon#*mode == 0, iclass 19, count 0 2006.253.07:44:31.26#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.253.07:44:31.26#ibcon#[28=FRQ=03,656.99\r\n] 2006.253.07:44:31.26#ibcon#*before write, iclass 19, count 0 2006.253.07:44:31.26#ibcon#enter sib2, iclass 19, count 0 2006.253.07:44:31.26#ibcon#flushed, iclass 19, count 0 2006.253.07:44:31.26#ibcon#about to write, iclass 19, count 0 2006.253.07:44:31.26#ibcon#wrote, iclass 19, count 0 2006.253.07:44:31.26#ibcon#about to read 3, iclass 19, count 0 2006.253.07:44:31.29#ibcon#read 3, iclass 19, count 0 2006.253.07:44:31.29#ibcon#about to read 4, iclass 19, count 0 2006.253.07:44:31.29#ibcon#read 4, iclass 19, count 0 2006.253.07:44:31.29#ibcon#about to read 5, iclass 19, count 0 2006.253.07:44:31.29#ibcon#read 5, iclass 19, count 0 2006.253.07:44:31.29#ibcon#about to read 6, iclass 19, count 0 2006.253.07:44:31.30#ibcon#read 6, iclass 19, count 0 2006.253.07:44:31.30#ibcon#end of sib2, iclass 19, count 0 2006.253.07:44:31.30#ibcon#*after write, iclass 19, count 0 2006.253.07:44:31.30#ibcon#*before return 0, iclass 19, count 0 2006.253.07:44:31.30#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.253.07:44:31.30#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.253.07:44:31.30#ibcon#about to clear, iclass 19 cls_cnt 0 2006.253.07:44:31.30#ibcon#cleared, iclass 19 cls_cnt 0 2006.253.07:44:31.30$vc4f8/vb=3,4 2006.253.07:44:31.30#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.253.07:44:31.30#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.253.07:44:31.30#ibcon#ireg 11 cls_cnt 2 2006.253.07:44:31.30#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.253.07:44:31.35#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.253.07:44:31.35#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.253.07:44:31.35#ibcon#enter wrdev, iclass 21, count 2 2006.253.07:44:31.35#ibcon#first serial, iclass 21, count 2 2006.253.07:44:31.35#ibcon#enter sib2, iclass 21, count 2 2006.253.07:44:31.35#ibcon#flushed, iclass 21, count 2 2006.253.07:44:31.35#ibcon#about to write, iclass 21, count 2 2006.253.07:44:31.36#ibcon#wrote, iclass 21, count 2 2006.253.07:44:31.36#ibcon#about to read 3, iclass 21, count 2 2006.253.07:44:31.37#ibcon#read 3, iclass 21, count 2 2006.253.07:44:31.37#ibcon#about to read 4, iclass 21, count 2 2006.253.07:44:31.37#ibcon#read 4, iclass 21, count 2 2006.253.07:44:31.37#ibcon#about to read 5, iclass 21, count 2 2006.253.07:44:31.37#ibcon#read 5, iclass 21, count 2 2006.253.07:44:31.37#ibcon#about to read 6, iclass 21, count 2 2006.253.07:44:31.38#ibcon#read 6, iclass 21, count 2 2006.253.07:44:31.38#ibcon#end of sib2, iclass 21, count 2 2006.253.07:44:31.38#ibcon#*mode == 0, iclass 21, count 2 2006.253.07:44:31.38#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.253.07:44:31.38#ibcon#[27=AT03-04\r\n] 2006.253.07:44:31.38#ibcon#*before write, iclass 21, count 2 2006.253.07:44:31.38#ibcon#enter sib2, iclass 21, count 2 2006.253.07:44:31.38#ibcon#flushed, iclass 21, count 2 2006.253.07:44:31.38#ibcon#about to write, iclass 21, count 2 2006.253.07:44:31.38#ibcon#wrote, iclass 21, count 2 2006.253.07:44:31.38#ibcon#about to read 3, iclass 21, count 2 2006.253.07:44:31.40#ibcon#read 3, iclass 21, count 2 2006.253.07:44:31.40#ibcon#about to read 4, iclass 21, count 2 2006.253.07:44:31.40#ibcon#read 4, iclass 21, count 2 2006.253.07:44:31.40#ibcon#about to read 5, iclass 21, count 2 2006.253.07:44:31.40#ibcon#read 5, iclass 21, count 2 2006.253.07:44:31.40#ibcon#about to read 6, iclass 21, count 2 2006.253.07:44:31.41#ibcon#read 6, iclass 21, count 2 2006.253.07:44:31.41#ibcon#end of sib2, iclass 21, count 2 2006.253.07:44:31.41#ibcon#*after write, iclass 21, count 2 2006.253.07:44:31.41#ibcon#*before return 0, iclass 21, count 2 2006.253.07:44:31.41#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.253.07:44:31.41#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.253.07:44:31.41#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.253.07:44:31.41#ibcon#ireg 7 cls_cnt 0 2006.253.07:44:31.41#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.253.07:44:31.52#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.253.07:44:31.52#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.253.07:44:31.52#ibcon#enter wrdev, iclass 21, count 0 2006.253.07:44:31.52#ibcon#first serial, iclass 21, count 0 2006.253.07:44:31.52#ibcon#enter sib2, iclass 21, count 0 2006.253.07:44:31.52#ibcon#flushed, iclass 21, count 0 2006.253.07:44:31.53#ibcon#about to write, iclass 21, count 0 2006.253.07:44:31.53#ibcon#wrote, iclass 21, count 0 2006.253.07:44:31.53#ibcon#about to read 3, iclass 21, count 0 2006.253.07:44:31.54#ibcon#read 3, iclass 21, count 0 2006.253.07:44:31.54#ibcon#about to read 4, iclass 21, count 0 2006.253.07:44:31.54#ibcon#read 4, iclass 21, count 0 2006.253.07:44:31.54#ibcon#about to read 5, iclass 21, count 0 2006.253.07:44:31.54#ibcon#read 5, iclass 21, count 0 2006.253.07:44:31.54#ibcon#about to read 6, iclass 21, count 0 2006.253.07:44:31.55#ibcon#read 6, iclass 21, count 0 2006.253.07:44:31.55#ibcon#end of sib2, iclass 21, count 0 2006.253.07:44:31.55#ibcon#*mode == 0, iclass 21, count 0 2006.253.07:44:31.55#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.253.07:44:31.55#ibcon#[27=USB\r\n] 2006.253.07:44:31.55#ibcon#*before write, iclass 21, count 0 2006.253.07:44:31.55#ibcon#enter sib2, iclass 21, count 0 2006.253.07:44:31.55#ibcon#flushed, iclass 21, count 0 2006.253.07:44:31.55#ibcon#about to write, iclass 21, count 0 2006.253.07:44:31.55#ibcon#wrote, iclass 21, count 0 2006.253.07:44:31.55#ibcon#about to read 3, iclass 21, count 0 2006.253.07:44:31.57#ibcon#read 3, iclass 21, count 0 2006.253.07:44:31.57#ibcon#about to read 4, iclass 21, count 0 2006.253.07:44:31.57#ibcon#read 4, iclass 21, count 0 2006.253.07:44:31.57#ibcon#about to read 5, iclass 21, count 0 2006.253.07:44:31.57#ibcon#read 5, iclass 21, count 0 2006.253.07:44:31.57#ibcon#about to read 6, iclass 21, count 0 2006.253.07:44:31.58#ibcon#read 6, iclass 21, count 0 2006.253.07:44:31.58#ibcon#end of sib2, iclass 21, count 0 2006.253.07:44:31.58#ibcon#*after write, iclass 21, count 0 2006.253.07:44:31.58#ibcon#*before return 0, iclass 21, count 0 2006.253.07:44:31.58#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.253.07:44:31.58#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.253.07:44:31.58#ibcon#about to clear, iclass 21 cls_cnt 0 2006.253.07:44:31.58#ibcon#cleared, iclass 21 cls_cnt 0 2006.253.07:44:31.58$vc4f8/vblo=4,712.99 2006.253.07:44:31.58#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.253.07:44:31.58#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.253.07:44:31.58#ibcon#ireg 17 cls_cnt 0 2006.253.07:44:31.58#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.253.07:44:31.58#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.253.07:44:31.58#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.253.07:44:31.58#ibcon#enter wrdev, iclass 23, count 0 2006.253.07:44:31.58#ibcon#first serial, iclass 23, count 0 2006.253.07:44:31.58#ibcon#enter sib2, iclass 23, count 0 2006.253.07:44:31.58#ibcon#flushed, iclass 23, count 0 2006.253.07:44:31.58#ibcon#about to write, iclass 23, count 0 2006.253.07:44:31.58#ibcon#wrote, iclass 23, count 0 2006.253.07:44:31.58#ibcon#about to read 3, iclass 23, count 0 2006.253.07:44:31.60#ibcon#read 3, iclass 23, count 0 2006.253.07:44:31.60#ibcon#about to read 4, iclass 23, count 0 2006.253.07:44:31.60#ibcon#read 4, iclass 23, count 0 2006.253.07:44:31.60#ibcon#about to read 5, iclass 23, count 0 2006.253.07:44:31.60#ibcon#read 5, iclass 23, count 0 2006.253.07:44:31.60#ibcon#about to read 6, iclass 23, count 0 2006.253.07:44:31.60#ibcon#read 6, iclass 23, count 0 2006.253.07:44:31.60#ibcon#end of sib2, iclass 23, count 0 2006.253.07:44:31.60#ibcon#*mode == 0, iclass 23, count 0 2006.253.07:44:31.60#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.253.07:44:31.60#ibcon#[28=FRQ=04,712.99\r\n] 2006.253.07:44:31.60#ibcon#*before write, iclass 23, count 0 2006.253.07:44:31.60#ibcon#enter sib2, iclass 23, count 0 2006.253.07:44:31.60#ibcon#flushed, iclass 23, count 0 2006.253.07:44:31.60#ibcon#about to write, iclass 23, count 0 2006.253.07:44:31.60#ibcon#wrote, iclass 23, count 0 2006.253.07:44:31.60#ibcon#about to read 3, iclass 23, count 0 2006.253.07:44:31.64#ibcon#read 3, iclass 23, count 0 2006.253.07:44:31.64#ibcon#about to read 4, iclass 23, count 0 2006.253.07:44:31.65#ibcon#read 4, iclass 23, count 0 2006.253.07:44:31.65#ibcon#about to read 5, iclass 23, count 0 2006.253.07:44:31.65#ibcon#read 5, iclass 23, count 0 2006.253.07:44:31.65#ibcon#about to read 6, iclass 23, count 0 2006.253.07:44:31.65#ibcon#read 6, iclass 23, count 0 2006.253.07:44:31.65#ibcon#end of sib2, iclass 23, count 0 2006.253.07:44:31.65#ibcon#*after write, iclass 23, count 0 2006.253.07:44:31.65#ibcon#*before return 0, iclass 23, count 0 2006.253.07:44:31.65#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.253.07:44:31.65#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.253.07:44:31.65#ibcon#about to clear, iclass 23 cls_cnt 0 2006.253.07:44:31.65#ibcon#cleared, iclass 23 cls_cnt 0 2006.253.07:44:31.65$vc4f8/vb=4,4 2006.253.07:44:31.65#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.253.07:44:31.65#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.253.07:44:31.65#ibcon#ireg 11 cls_cnt 2 2006.253.07:44:31.65#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.253.07:44:31.69#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.253.07:44:31.69#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.253.07:44:31.69#ibcon#enter wrdev, iclass 25, count 2 2006.253.07:44:31.69#ibcon#first serial, iclass 25, count 2 2006.253.07:44:31.69#ibcon#enter sib2, iclass 25, count 2 2006.253.07:44:31.69#ibcon#flushed, iclass 25, count 2 2006.253.07:44:31.69#ibcon#about to write, iclass 25, count 2 2006.253.07:44:31.70#ibcon#wrote, iclass 25, count 2 2006.253.07:44:31.70#ibcon#about to read 3, iclass 25, count 2 2006.253.07:44:31.71#ibcon#read 3, iclass 25, count 2 2006.253.07:44:31.71#ibcon#about to read 4, iclass 25, count 2 2006.253.07:44:31.71#ibcon#read 4, iclass 25, count 2 2006.253.07:44:31.72#ibcon#about to read 5, iclass 25, count 2 2006.253.07:44:31.72#ibcon#read 5, iclass 25, count 2 2006.253.07:44:31.72#ibcon#about to read 6, iclass 25, count 2 2006.253.07:44:31.72#ibcon#read 6, iclass 25, count 2 2006.253.07:44:31.72#ibcon#end of sib2, iclass 25, count 2 2006.253.07:44:31.72#ibcon#*mode == 0, iclass 25, count 2 2006.253.07:44:31.72#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.253.07:44:31.72#ibcon#[27=AT04-04\r\n] 2006.253.07:44:31.72#ibcon#*before write, iclass 25, count 2 2006.253.07:44:31.72#ibcon#enter sib2, iclass 25, count 2 2006.253.07:44:31.72#ibcon#flushed, iclass 25, count 2 2006.253.07:44:31.72#ibcon#about to write, iclass 25, count 2 2006.253.07:44:31.72#ibcon#wrote, iclass 25, count 2 2006.253.07:44:31.72#ibcon#about to read 3, iclass 25, count 2 2006.253.07:44:31.74#ibcon#read 3, iclass 25, count 2 2006.253.07:44:31.74#ibcon#about to read 4, iclass 25, count 2 2006.253.07:44:31.74#ibcon#read 4, iclass 25, count 2 2006.253.07:44:31.75#ibcon#about to read 5, iclass 25, count 2 2006.253.07:44:31.75#ibcon#read 5, iclass 25, count 2 2006.253.07:44:31.75#ibcon#about to read 6, iclass 25, count 2 2006.253.07:44:31.75#ibcon#read 6, iclass 25, count 2 2006.253.07:44:31.75#ibcon#end of sib2, iclass 25, count 2 2006.253.07:44:31.75#ibcon#*after write, iclass 25, count 2 2006.253.07:44:31.75#ibcon#*before return 0, iclass 25, count 2 2006.253.07:44:31.75#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.253.07:44:31.75#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.253.07:44:31.75#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.253.07:44:31.75#ibcon#ireg 7 cls_cnt 0 2006.253.07:44:31.75#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.253.07:44:31.86#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.253.07:44:31.86#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.253.07:44:31.86#ibcon#enter wrdev, iclass 25, count 0 2006.253.07:44:31.86#ibcon#first serial, iclass 25, count 0 2006.253.07:44:31.86#ibcon#enter sib2, iclass 25, count 0 2006.253.07:44:31.86#ibcon#flushed, iclass 25, count 0 2006.253.07:44:31.86#ibcon#about to write, iclass 25, count 0 2006.253.07:44:31.87#ibcon#wrote, iclass 25, count 0 2006.253.07:44:31.87#ibcon#about to read 3, iclass 25, count 0 2006.253.07:44:31.88#ibcon#read 3, iclass 25, count 0 2006.253.07:44:31.88#ibcon#about to read 4, iclass 25, count 0 2006.253.07:44:31.88#ibcon#read 4, iclass 25, count 0 2006.253.07:44:31.88#ibcon#about to read 5, iclass 25, count 0 2006.253.07:44:31.88#ibcon#read 5, iclass 25, count 0 2006.253.07:44:31.88#ibcon#about to read 6, iclass 25, count 0 2006.253.07:44:31.89#ibcon#read 6, iclass 25, count 0 2006.253.07:44:31.89#ibcon#end of sib2, iclass 25, count 0 2006.253.07:44:31.89#ibcon#*mode == 0, iclass 25, count 0 2006.253.07:44:31.89#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.253.07:44:31.89#ibcon#[27=USB\r\n] 2006.253.07:44:31.89#ibcon#*before write, iclass 25, count 0 2006.253.07:44:31.89#ibcon#enter sib2, iclass 25, count 0 2006.253.07:44:31.89#ibcon#flushed, iclass 25, count 0 2006.253.07:44:31.89#ibcon#about to write, iclass 25, count 0 2006.253.07:44:31.89#ibcon#wrote, iclass 25, count 0 2006.253.07:44:31.89#ibcon#about to read 3, iclass 25, count 0 2006.253.07:44:31.91#ibcon#read 3, iclass 25, count 0 2006.253.07:44:31.91#ibcon#about to read 4, iclass 25, count 0 2006.253.07:44:31.91#ibcon#read 4, iclass 25, count 0 2006.253.07:44:31.91#ibcon#about to read 5, iclass 25, count 0 2006.253.07:44:31.91#ibcon#read 5, iclass 25, count 0 2006.253.07:44:31.91#ibcon#about to read 6, iclass 25, count 0 2006.253.07:44:31.92#ibcon#read 6, iclass 25, count 0 2006.253.07:44:31.92#ibcon#end of sib2, iclass 25, count 0 2006.253.07:44:31.92#ibcon#*after write, iclass 25, count 0 2006.253.07:44:31.92#ibcon#*before return 0, iclass 25, count 0 2006.253.07:44:31.92#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.253.07:44:31.92#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.253.07:44:31.92#ibcon#about to clear, iclass 25 cls_cnt 0 2006.253.07:44:31.92#ibcon#cleared, iclass 25 cls_cnt 0 2006.253.07:44:31.92$vc4f8/vblo=5,744.99 2006.253.07:44:31.92#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.253.07:44:31.92#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.253.07:44:31.92#ibcon#ireg 17 cls_cnt 0 2006.253.07:44:31.92#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.253.07:44:31.92#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.253.07:44:31.92#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.253.07:44:31.92#ibcon#enter wrdev, iclass 27, count 0 2006.253.07:44:31.92#ibcon#first serial, iclass 27, count 0 2006.253.07:44:31.92#ibcon#enter sib2, iclass 27, count 0 2006.253.07:44:31.92#ibcon#flushed, iclass 27, count 0 2006.253.07:44:31.92#ibcon#about to write, iclass 27, count 0 2006.253.07:44:31.92#ibcon#wrote, iclass 27, count 0 2006.253.07:44:31.92#ibcon#about to read 3, iclass 27, count 0 2006.253.07:44:31.93#ibcon#read 3, iclass 27, count 0 2006.253.07:44:31.93#ibcon#about to read 4, iclass 27, count 0 2006.253.07:44:31.93#ibcon#read 4, iclass 27, count 0 2006.253.07:44:31.93#ibcon#about to read 5, iclass 27, count 0 2006.253.07:44:31.93#ibcon#read 5, iclass 27, count 0 2006.253.07:44:31.93#ibcon#about to read 6, iclass 27, count 0 2006.253.07:44:31.94#ibcon#read 6, iclass 27, count 0 2006.253.07:44:31.94#ibcon#end of sib2, iclass 27, count 0 2006.253.07:44:31.94#ibcon#*mode == 0, iclass 27, count 0 2006.253.07:44:31.94#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.253.07:44:31.94#ibcon#[28=FRQ=05,744.99\r\n] 2006.253.07:44:31.94#ibcon#*before write, iclass 27, count 0 2006.253.07:44:31.94#ibcon#enter sib2, iclass 27, count 0 2006.253.07:44:31.94#ibcon#flushed, iclass 27, count 0 2006.253.07:44:31.94#ibcon#about to write, iclass 27, count 0 2006.253.07:44:31.94#ibcon#wrote, iclass 27, count 0 2006.253.07:44:31.94#ibcon#about to read 3, iclass 27, count 0 2006.253.07:44:31.97#ibcon#read 3, iclass 27, count 0 2006.253.07:44:31.97#ibcon#about to read 4, iclass 27, count 0 2006.253.07:44:31.97#ibcon#read 4, iclass 27, count 0 2006.253.07:44:31.97#ibcon#about to read 5, iclass 27, count 0 2006.253.07:44:31.97#ibcon#read 5, iclass 27, count 0 2006.253.07:44:31.98#ibcon#about to read 6, iclass 27, count 0 2006.253.07:44:31.98#ibcon#read 6, iclass 27, count 0 2006.253.07:44:31.98#ibcon#end of sib2, iclass 27, count 0 2006.253.07:44:31.98#ibcon#*after write, iclass 27, count 0 2006.253.07:44:31.98#ibcon#*before return 0, iclass 27, count 0 2006.253.07:44:31.98#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.253.07:44:31.98#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.253.07:44:31.98#ibcon#about to clear, iclass 27 cls_cnt 0 2006.253.07:44:31.98#ibcon#cleared, iclass 27 cls_cnt 0 2006.253.07:44:31.98$vc4f8/vb=5,4 2006.253.07:44:31.98#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.253.07:44:31.98#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.253.07:44:31.98#ibcon#ireg 11 cls_cnt 2 2006.253.07:44:31.98#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.253.07:44:32.03#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.253.07:44:32.03#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.253.07:44:32.03#ibcon#enter wrdev, iclass 29, count 2 2006.253.07:44:32.03#ibcon#first serial, iclass 29, count 2 2006.253.07:44:32.03#ibcon#enter sib2, iclass 29, count 2 2006.253.07:44:32.03#ibcon#flushed, iclass 29, count 2 2006.253.07:44:32.03#ibcon#about to write, iclass 29, count 2 2006.253.07:44:32.04#ibcon#wrote, iclass 29, count 2 2006.253.07:44:32.04#ibcon#about to read 3, iclass 29, count 2 2006.253.07:44:32.05#ibcon#read 3, iclass 29, count 2 2006.253.07:44:32.05#ibcon#about to read 4, iclass 29, count 2 2006.253.07:44:32.05#ibcon#read 4, iclass 29, count 2 2006.253.07:44:32.05#ibcon#about to read 5, iclass 29, count 2 2006.253.07:44:32.06#ibcon#read 5, iclass 29, count 2 2006.253.07:44:32.06#ibcon#about to read 6, iclass 29, count 2 2006.253.07:44:32.06#ibcon#read 6, iclass 29, count 2 2006.253.07:44:32.06#ibcon#end of sib2, iclass 29, count 2 2006.253.07:44:32.06#ibcon#*mode == 0, iclass 29, count 2 2006.253.07:44:32.06#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.253.07:44:32.06#ibcon#[27=AT05-04\r\n] 2006.253.07:44:32.06#ibcon#*before write, iclass 29, count 2 2006.253.07:44:32.06#ibcon#enter sib2, iclass 29, count 2 2006.253.07:44:32.06#ibcon#flushed, iclass 29, count 2 2006.253.07:44:32.06#ibcon#about to write, iclass 29, count 2 2006.253.07:44:32.06#ibcon#wrote, iclass 29, count 2 2006.253.07:44:32.06#ibcon#about to read 3, iclass 29, count 2 2006.253.07:44:32.08#ibcon#read 3, iclass 29, count 2 2006.253.07:44:32.08#ibcon#about to read 4, iclass 29, count 2 2006.253.07:44:32.08#ibcon#read 4, iclass 29, count 2 2006.253.07:44:32.09#ibcon#about to read 5, iclass 29, count 2 2006.253.07:44:32.09#ibcon#read 5, iclass 29, count 2 2006.253.07:44:32.09#ibcon#about to read 6, iclass 29, count 2 2006.253.07:44:32.09#ibcon#read 6, iclass 29, count 2 2006.253.07:44:32.09#ibcon#end of sib2, iclass 29, count 2 2006.253.07:44:32.09#ibcon#*after write, iclass 29, count 2 2006.253.07:44:32.09#ibcon#*before return 0, iclass 29, count 2 2006.253.07:44:32.09#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.253.07:44:32.09#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.253.07:44:32.09#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.253.07:44:32.09#ibcon#ireg 7 cls_cnt 0 2006.253.07:44:32.09#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.253.07:44:32.20#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.253.07:44:32.20#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.253.07:44:32.20#ibcon#enter wrdev, iclass 29, count 0 2006.253.07:44:32.20#ibcon#first serial, iclass 29, count 0 2006.253.07:44:32.20#ibcon#enter sib2, iclass 29, count 0 2006.253.07:44:32.20#ibcon#flushed, iclass 29, count 0 2006.253.07:44:32.20#ibcon#about to write, iclass 29, count 0 2006.253.07:44:32.21#ibcon#wrote, iclass 29, count 0 2006.253.07:44:32.21#ibcon#about to read 3, iclass 29, count 0 2006.253.07:44:32.22#ibcon#read 3, iclass 29, count 0 2006.253.07:44:32.22#ibcon#about to read 4, iclass 29, count 0 2006.253.07:44:32.22#ibcon#read 4, iclass 29, count 0 2006.253.07:44:32.22#ibcon#about to read 5, iclass 29, count 0 2006.253.07:44:32.22#ibcon#read 5, iclass 29, count 0 2006.253.07:44:32.22#ibcon#about to read 6, iclass 29, count 0 2006.253.07:44:32.23#ibcon#read 6, iclass 29, count 0 2006.253.07:44:32.23#ibcon#end of sib2, iclass 29, count 0 2006.253.07:44:32.23#ibcon#*mode == 0, iclass 29, count 0 2006.253.07:44:32.23#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.253.07:44:32.23#ibcon#[27=USB\r\n] 2006.253.07:44:32.23#ibcon#*before write, iclass 29, count 0 2006.253.07:44:32.23#ibcon#enter sib2, iclass 29, count 0 2006.253.07:44:32.23#ibcon#flushed, iclass 29, count 0 2006.253.07:44:32.23#ibcon#about to write, iclass 29, count 0 2006.253.07:44:32.23#ibcon#wrote, iclass 29, count 0 2006.253.07:44:32.23#ibcon#about to read 3, iclass 29, count 0 2006.253.07:44:32.25#ibcon#read 3, iclass 29, count 0 2006.253.07:44:32.25#ibcon#about to read 4, iclass 29, count 0 2006.253.07:44:32.25#ibcon#read 4, iclass 29, count 0 2006.253.07:44:32.25#ibcon#about to read 5, iclass 29, count 0 2006.253.07:44:32.25#ibcon#read 5, iclass 29, count 0 2006.253.07:44:32.26#ibcon#about to read 6, iclass 29, count 0 2006.253.07:44:32.26#ibcon#read 6, iclass 29, count 0 2006.253.07:44:32.26#ibcon#end of sib2, iclass 29, count 0 2006.253.07:44:32.26#ibcon#*after write, iclass 29, count 0 2006.253.07:44:32.26#ibcon#*before return 0, iclass 29, count 0 2006.253.07:44:32.26#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.253.07:44:32.26#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.253.07:44:32.26#ibcon#about to clear, iclass 29 cls_cnt 0 2006.253.07:44:32.26#ibcon#cleared, iclass 29 cls_cnt 0 2006.253.07:44:32.26$vc4f8/vblo=6,752.99 2006.253.07:44:32.26#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.253.07:44:32.26#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.253.07:44:32.26#ibcon#ireg 17 cls_cnt 0 2006.253.07:44:32.26#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.253.07:44:32.26#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.253.07:44:32.26#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.253.07:44:32.26#ibcon#enter wrdev, iclass 31, count 0 2006.253.07:44:32.26#ibcon#first serial, iclass 31, count 0 2006.253.07:44:32.26#ibcon#enter sib2, iclass 31, count 0 2006.253.07:44:32.26#ibcon#flushed, iclass 31, count 0 2006.253.07:44:32.26#ibcon#about to write, iclass 31, count 0 2006.253.07:44:32.26#ibcon#wrote, iclass 31, count 0 2006.253.07:44:32.26#ibcon#about to read 3, iclass 31, count 0 2006.253.07:44:32.27#ibcon#read 3, iclass 31, count 0 2006.253.07:44:32.27#ibcon#about to read 4, iclass 31, count 0 2006.253.07:44:32.27#ibcon#read 4, iclass 31, count 0 2006.253.07:44:32.27#ibcon#about to read 5, iclass 31, count 0 2006.253.07:44:32.27#ibcon#read 5, iclass 31, count 0 2006.253.07:44:32.28#ibcon#about to read 6, iclass 31, count 0 2006.253.07:44:32.28#ibcon#read 6, iclass 31, count 0 2006.253.07:44:32.28#ibcon#end of sib2, iclass 31, count 0 2006.253.07:44:32.28#ibcon#*mode == 0, iclass 31, count 0 2006.253.07:44:32.28#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.253.07:44:32.28#ibcon#[28=FRQ=06,752.99\r\n] 2006.253.07:44:32.28#ibcon#*before write, iclass 31, count 0 2006.253.07:44:32.28#ibcon#enter sib2, iclass 31, count 0 2006.253.07:44:32.28#ibcon#flushed, iclass 31, count 0 2006.253.07:44:32.28#ibcon#about to write, iclass 31, count 0 2006.253.07:44:32.28#ibcon#wrote, iclass 31, count 0 2006.253.07:44:32.28#ibcon#about to read 3, iclass 31, count 0 2006.253.07:44:32.31#ibcon#read 3, iclass 31, count 0 2006.253.07:44:32.31#ibcon#about to read 4, iclass 31, count 0 2006.253.07:44:32.31#ibcon#read 4, iclass 31, count 0 2006.253.07:44:32.31#ibcon#about to read 5, iclass 31, count 0 2006.253.07:44:32.31#ibcon#read 5, iclass 31, count 0 2006.253.07:44:32.31#ibcon#about to read 6, iclass 31, count 0 2006.253.07:44:32.32#ibcon#read 6, iclass 31, count 0 2006.253.07:44:32.32#ibcon#end of sib2, iclass 31, count 0 2006.253.07:44:32.32#ibcon#*after write, iclass 31, count 0 2006.253.07:44:32.32#ibcon#*before return 0, iclass 31, count 0 2006.253.07:44:32.32#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.253.07:44:32.32#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.253.07:44:32.32#ibcon#about to clear, iclass 31 cls_cnt 0 2006.253.07:44:32.32#ibcon#cleared, iclass 31 cls_cnt 0 2006.253.07:44:32.32$vc4f8/vb=6,4 2006.253.07:44:32.32#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.253.07:44:32.32#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.253.07:44:32.32#ibcon#ireg 11 cls_cnt 2 2006.253.07:44:32.32#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.253.07:44:32.37#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.253.07:44:32.37#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.253.07:44:32.37#ibcon#enter wrdev, iclass 33, count 2 2006.253.07:44:32.37#ibcon#first serial, iclass 33, count 2 2006.253.07:44:32.37#ibcon#enter sib2, iclass 33, count 2 2006.253.07:44:32.37#ibcon#flushed, iclass 33, count 2 2006.253.07:44:32.37#ibcon#about to write, iclass 33, count 2 2006.253.07:44:32.38#ibcon#wrote, iclass 33, count 2 2006.253.07:44:32.38#ibcon#about to read 3, iclass 33, count 2 2006.253.07:44:32.39#ibcon#read 3, iclass 33, count 2 2006.253.07:44:32.39#ibcon#about to read 4, iclass 33, count 2 2006.253.07:44:32.39#ibcon#read 4, iclass 33, count 2 2006.253.07:44:32.39#ibcon#about to read 5, iclass 33, count 2 2006.253.07:44:32.39#ibcon#read 5, iclass 33, count 2 2006.253.07:44:32.40#ibcon#about to read 6, iclass 33, count 2 2006.253.07:44:32.40#ibcon#read 6, iclass 33, count 2 2006.253.07:44:32.40#ibcon#end of sib2, iclass 33, count 2 2006.253.07:44:32.40#ibcon#*mode == 0, iclass 33, count 2 2006.253.07:44:32.40#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.253.07:44:32.40#ibcon#[27=AT06-04\r\n] 2006.253.07:44:32.40#ibcon#*before write, iclass 33, count 2 2006.253.07:44:32.40#ibcon#enter sib2, iclass 33, count 2 2006.253.07:44:32.40#ibcon#flushed, iclass 33, count 2 2006.253.07:44:32.40#ibcon#about to write, iclass 33, count 2 2006.253.07:44:32.40#ibcon#wrote, iclass 33, count 2 2006.253.07:44:32.40#ibcon#about to read 3, iclass 33, count 2 2006.253.07:44:32.42#ibcon#read 3, iclass 33, count 2 2006.253.07:44:32.42#ibcon#about to read 4, iclass 33, count 2 2006.253.07:44:32.42#ibcon#read 4, iclass 33, count 2 2006.253.07:44:32.42#ibcon#about to read 5, iclass 33, count 2 2006.253.07:44:32.42#ibcon#read 5, iclass 33, count 2 2006.253.07:44:32.42#ibcon#about to read 6, iclass 33, count 2 2006.253.07:44:32.43#ibcon#read 6, iclass 33, count 2 2006.253.07:44:32.43#ibcon#end of sib2, iclass 33, count 2 2006.253.07:44:32.43#ibcon#*after write, iclass 33, count 2 2006.253.07:44:32.43#ibcon#*before return 0, iclass 33, count 2 2006.253.07:44:32.43#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.253.07:44:32.43#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.253.07:44:32.43#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.253.07:44:32.43#ibcon#ireg 7 cls_cnt 0 2006.253.07:44:32.43#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.253.07:44:32.54#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.253.07:44:32.54#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.253.07:44:32.54#ibcon#enter wrdev, iclass 33, count 0 2006.253.07:44:32.54#ibcon#first serial, iclass 33, count 0 2006.253.07:44:32.54#ibcon#enter sib2, iclass 33, count 0 2006.253.07:44:32.54#ibcon#flushed, iclass 33, count 0 2006.253.07:44:32.54#ibcon#about to write, iclass 33, count 0 2006.253.07:44:32.55#ibcon#wrote, iclass 33, count 0 2006.253.07:44:32.55#ibcon#about to read 3, iclass 33, count 0 2006.253.07:44:32.56#ibcon#read 3, iclass 33, count 0 2006.253.07:44:32.56#ibcon#about to read 4, iclass 33, count 0 2006.253.07:44:32.56#ibcon#read 4, iclass 33, count 0 2006.253.07:44:32.56#ibcon#about to read 5, iclass 33, count 0 2006.253.07:44:32.56#ibcon#read 5, iclass 33, count 0 2006.253.07:44:32.56#ibcon#about to read 6, iclass 33, count 0 2006.253.07:44:32.57#ibcon#read 6, iclass 33, count 0 2006.253.07:44:32.57#ibcon#end of sib2, iclass 33, count 0 2006.253.07:44:32.57#ibcon#*mode == 0, iclass 33, count 0 2006.253.07:44:32.57#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.253.07:44:32.57#ibcon#[27=USB\r\n] 2006.253.07:44:32.57#ibcon#*before write, iclass 33, count 0 2006.253.07:44:32.57#ibcon#enter sib2, iclass 33, count 0 2006.253.07:44:32.57#ibcon#flushed, iclass 33, count 0 2006.253.07:44:32.57#ibcon#about to write, iclass 33, count 0 2006.253.07:44:32.57#ibcon#wrote, iclass 33, count 0 2006.253.07:44:32.57#ibcon#about to read 3, iclass 33, count 0 2006.253.07:44:32.59#ibcon#read 3, iclass 33, count 0 2006.253.07:44:32.59#ibcon#about to read 4, iclass 33, count 0 2006.253.07:44:32.59#ibcon#read 4, iclass 33, count 0 2006.253.07:44:32.59#ibcon#about to read 5, iclass 33, count 0 2006.253.07:44:32.59#ibcon#read 5, iclass 33, count 0 2006.253.07:44:32.59#ibcon#about to read 6, iclass 33, count 0 2006.253.07:44:32.60#ibcon#read 6, iclass 33, count 0 2006.253.07:44:32.60#ibcon#end of sib2, iclass 33, count 0 2006.253.07:44:32.60#ibcon#*after write, iclass 33, count 0 2006.253.07:44:32.60#ibcon#*before return 0, iclass 33, count 0 2006.253.07:44:32.60#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.253.07:44:32.60#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.253.07:44:32.60#ibcon#about to clear, iclass 33 cls_cnt 0 2006.253.07:44:32.60#ibcon#cleared, iclass 33 cls_cnt 0 2006.253.07:44:32.60$vc4f8/vabw=wide 2006.253.07:44:32.60#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.253.07:44:32.60#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.253.07:44:32.60#ibcon#ireg 8 cls_cnt 0 2006.253.07:44:32.60#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.253.07:44:32.60#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.253.07:44:32.60#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.253.07:44:32.60#ibcon#enter wrdev, iclass 35, count 0 2006.253.07:44:32.60#ibcon#first serial, iclass 35, count 0 2006.253.07:44:32.60#ibcon#enter sib2, iclass 35, count 0 2006.253.07:44:32.60#ibcon#flushed, iclass 35, count 0 2006.253.07:44:32.60#ibcon#about to write, iclass 35, count 0 2006.253.07:44:32.60#ibcon#wrote, iclass 35, count 0 2006.253.07:44:32.60#ibcon#about to read 3, iclass 35, count 0 2006.253.07:44:32.61#ibcon#read 3, iclass 35, count 0 2006.253.07:44:32.61#ibcon#about to read 4, iclass 35, count 0 2006.253.07:44:32.61#ibcon#read 4, iclass 35, count 0 2006.253.07:44:32.61#ibcon#about to read 5, iclass 35, count 0 2006.253.07:44:32.61#ibcon#read 5, iclass 35, count 0 2006.253.07:44:32.61#ibcon#about to read 6, iclass 35, count 0 2006.253.07:44:32.62#ibcon#read 6, iclass 35, count 0 2006.253.07:44:32.62#ibcon#end of sib2, iclass 35, count 0 2006.253.07:44:32.62#ibcon#*mode == 0, iclass 35, count 0 2006.253.07:44:32.62#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.253.07:44:32.62#ibcon#[25=BW32\r\n] 2006.253.07:44:32.62#ibcon#*before write, iclass 35, count 0 2006.253.07:44:32.62#ibcon#enter sib2, iclass 35, count 0 2006.253.07:44:32.62#ibcon#flushed, iclass 35, count 0 2006.253.07:44:32.62#ibcon#about to write, iclass 35, count 0 2006.253.07:44:32.62#ibcon#wrote, iclass 35, count 0 2006.253.07:44:32.62#ibcon#about to read 3, iclass 35, count 0 2006.253.07:44:32.64#ibcon#read 3, iclass 35, count 0 2006.253.07:44:32.64#ibcon#about to read 4, iclass 35, count 0 2006.253.07:44:32.64#ibcon#read 4, iclass 35, count 0 2006.253.07:44:32.64#ibcon#about to read 5, iclass 35, count 0 2006.253.07:44:32.64#ibcon#read 5, iclass 35, count 0 2006.253.07:44:32.64#ibcon#about to read 6, iclass 35, count 0 2006.253.07:44:32.65#ibcon#read 6, iclass 35, count 0 2006.253.07:44:32.65#ibcon#end of sib2, iclass 35, count 0 2006.253.07:44:32.65#ibcon#*after write, iclass 35, count 0 2006.253.07:44:32.65#ibcon#*before return 0, iclass 35, count 0 2006.253.07:44:32.65#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.253.07:44:32.65#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.253.07:44:32.65#ibcon#about to clear, iclass 35 cls_cnt 0 2006.253.07:44:32.65#ibcon#cleared, iclass 35 cls_cnt 0 2006.253.07:44:32.65$vc4f8/vbbw=wide 2006.253.07:44:32.65#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.253.07:44:32.65#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.253.07:44:32.65#ibcon#ireg 8 cls_cnt 0 2006.253.07:44:32.65#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.253.07:44:32.71#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.253.07:44:32.71#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.253.07:44:32.71#ibcon#enter wrdev, iclass 37, count 0 2006.253.07:44:32.71#ibcon#first serial, iclass 37, count 0 2006.253.07:44:32.71#ibcon#enter sib2, iclass 37, count 0 2006.253.07:44:32.71#ibcon#flushed, iclass 37, count 0 2006.253.07:44:32.71#ibcon#about to write, iclass 37, count 0 2006.253.07:44:32.72#ibcon#wrote, iclass 37, count 0 2006.253.07:44:32.72#ibcon#about to read 3, iclass 37, count 0 2006.253.07:44:32.73#ibcon#read 3, iclass 37, count 0 2006.253.07:44:32.73#ibcon#about to read 4, iclass 37, count 0 2006.253.07:44:32.73#ibcon#read 4, iclass 37, count 0 2006.253.07:44:32.73#ibcon#about to read 5, iclass 37, count 0 2006.253.07:44:32.73#ibcon#read 5, iclass 37, count 0 2006.253.07:44:32.73#ibcon#about to read 6, iclass 37, count 0 2006.253.07:44:32.74#ibcon#read 6, iclass 37, count 0 2006.253.07:44:32.74#ibcon#end of sib2, iclass 37, count 0 2006.253.07:44:32.74#ibcon#*mode == 0, iclass 37, count 0 2006.253.07:44:32.74#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.253.07:44:32.74#ibcon#[27=BW32\r\n] 2006.253.07:44:32.74#ibcon#*before write, iclass 37, count 0 2006.253.07:44:32.74#ibcon#enter sib2, iclass 37, count 0 2006.253.07:44:32.74#ibcon#flushed, iclass 37, count 0 2006.253.07:44:32.74#ibcon#about to write, iclass 37, count 0 2006.253.07:44:32.74#ibcon#wrote, iclass 37, count 0 2006.253.07:44:32.74#ibcon#about to read 3, iclass 37, count 0 2006.253.07:44:32.76#ibcon#read 3, iclass 37, count 0 2006.253.07:44:32.76#ibcon#about to read 4, iclass 37, count 0 2006.253.07:44:32.76#ibcon#read 4, iclass 37, count 0 2006.253.07:44:32.77#ibcon#about to read 5, iclass 37, count 0 2006.253.07:44:32.77#ibcon#read 5, iclass 37, count 0 2006.253.07:44:32.77#ibcon#about to read 6, iclass 37, count 0 2006.253.07:44:32.77#ibcon#read 6, iclass 37, count 0 2006.253.07:44:32.77#ibcon#end of sib2, iclass 37, count 0 2006.253.07:44:32.77#ibcon#*after write, iclass 37, count 0 2006.253.07:44:32.77#ibcon#*before return 0, iclass 37, count 0 2006.253.07:44:32.77#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.253.07:44:32.77#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.253.07:44:32.77#ibcon#about to clear, iclass 37 cls_cnt 0 2006.253.07:44:32.77#ibcon#cleared, iclass 37 cls_cnt 0 2006.253.07:44:32.77$4f8m12a/ifd4f 2006.253.07:44:32.77$ifd4f/lo= 2006.253.07:44:32.77$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.253.07:44:32.77$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.253.07:44:32.77$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.253.07:44:32.77$ifd4f/patch= 2006.253.07:44:32.77$ifd4f/patch=lo1,a1,a2,a3,a4 2006.253.07:44:32.77$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.253.07:44:32.77$ifd4f/patch=lo3,a5,a6,a7,a8 2006.253.07:44:32.77$4f8m12a/"form=m,16.000,1:2 2006.253.07:44:32.77$4f8m12a/"tpicd 2006.253.07:44:32.77$4f8m12a/echo=off 2006.253.07:44:32.77$4f8m12a/xlog=off 2006.253.07:44:32.77:!2006.253.07:45:00 2006.253.07:44:45.14#trakl#Source acquired 2006.253.07:44:45.15#flagr#flagr/antenna,acquired 2006.253.07:45:00.02:preob 2006.253.07:45:01.15/onsource/TRACKING 2006.253.07:45:01.15:!2006.253.07:45:10 2006.253.07:45:10.02:data_valid=on 2006.253.07:45:10.02:midob 2006.253.07:45:11.15/onsource/TRACKING 2006.253.07:45:11.15/wx/31.40,1006.4,73 2006.253.07:45:11.28/cable/+6.3687E-03 2006.253.07:45:12.37/va/01,08,usb,yes,33,34 2006.253.07:45:12.37/va/02,07,usb,yes,33,34 2006.253.07:45:12.37/va/03,06,usb,yes,35,35 2006.253.07:45:12.37/va/04,07,usb,yes,34,37 2006.253.07:45:12.37/va/05,07,usb,yes,35,37 2006.253.07:45:12.37/va/06,07,usb,yes,31,31 2006.253.07:45:12.37/va/07,07,usb,yes,31,30 2006.253.07:45:12.37/va/08,07,usb,yes,33,33 2006.253.07:45:12.60/valo/01,532.99,yes,locked 2006.253.07:45:12.60/valo/02,572.99,yes,locked 2006.253.07:45:12.60/valo/03,672.99,yes,locked 2006.253.07:45:12.60/valo/04,832.99,yes,locked 2006.253.07:45:12.60/valo/05,652.99,yes,locked 2006.253.07:45:12.60/valo/06,772.99,yes,locked 2006.253.07:45:12.60/valo/07,832.99,yes,locked 2006.253.07:45:12.60/valo/08,852.99,yes,locked 2006.253.07:45:13.69/vb/01,04,usb,yes,31,29 2006.253.07:45:13.69/vb/02,05,usb,yes,29,30 2006.253.07:45:13.69/vb/03,04,usb,yes,29,33 2006.253.07:45:13.69/vb/04,04,usb,yes,30,30 2006.253.07:45:13.69/vb/05,04,usb,yes,28,32 2006.253.07:45:13.69/vb/06,04,usb,yes,29,32 2006.253.07:45:13.69/vb/07,04,usb,yes,31,31 2006.253.07:45:13.69/vb/08,04,usb,yes,29,32 2006.253.07:45:13.92/vblo/01,632.99,yes,locked 2006.253.07:45:13.92/vblo/02,640.99,yes,locked 2006.253.07:45:13.92/vblo/03,656.99,yes,locked 2006.253.07:45:13.92/vblo/04,712.99,yes,locked 2006.253.07:45:13.92/vblo/05,744.99,yes,locked 2006.253.07:45:13.92/vblo/06,752.99,yes,locked 2006.253.07:45:13.93/vblo/07,734.99,yes,locked 2006.253.07:45:13.93/vblo/08,744.99,yes,locked 2006.253.07:45:14.07/vabw/8 2006.253.07:45:14.22/vbbw/8 2006.253.07:45:14.38/xfe/off,on,14.2 2006.253.07:45:14.75/ifatt/23,28,28,28 2006.253.07:45:15.07/fmout-gps/S +4.75E-07 2006.253.07:45:15.12:!2006.253.07:46:10 2006.253.07:46:10.02:data_valid=off 2006.253.07:46:10.02:postob 2006.253.07:46:10.08/cable/+6.3678E-03 2006.253.07:46:10.09/wx/31.38,1006.4,73 2006.253.07:46:11.07/fmout-gps/S +4.75E-07 2006.253.07:46:11.08:scan_name=253-0747,k06253,60 2006.253.07:46:11.08:source=3c371,180650.68,694928.1,2000.0,cw 2006.253.07:46:12.14#flagr#flagr/antenna,new-source 2006.253.07:46:12.14:checkk5 2006.253.07:46:12.52/chk_autoobs//k5ts1/ autoobs is running! 2006.253.07:46:12.89/chk_autoobs//k5ts2/ autoobs is running! 2006.253.07:46:13.30/chk_autoobs//k5ts3/ autoobs is running! 2006.253.07:46:13.67/chk_autoobs//k5ts4/ autoobs is running! 2006.253.07:46:14.04/chk_obsdata//k5ts1/T2530745??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.253.07:46:14.41/chk_obsdata//k5ts2/T2530745??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.253.07:46:14.77/chk_obsdata//k5ts3/T2530745??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.253.07:46:15.15/chk_obsdata//k5ts4/T2530745??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.253.07:46:15.86/k5log//k5ts1_log_newline 2006.253.07:46:16.57/k5log//k5ts2_log_newline 2006.253.07:46:17.27/k5log//k5ts3_log_newline 2006.253.07:46:17.97/k5log//k5ts4_log_newline 2006.253.07:46:17.99/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.253.07:46:17.99:4f8m12a=1 2006.253.07:46:17.99$4f8m12a/echo=on 2006.253.07:46:17.99$4f8m12a/pcalon 2006.253.07:46:17.99$pcalon/"no phase cal control is implemented here 2006.253.07:46:17.99$4f8m12a/"tpicd=stop 2006.253.07:46:17.99$4f8m12a/vc4f8 2006.253.07:46:17.99$vc4f8/valo=1,532.99 2006.253.07:46:18.00#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.253.07:46:18.00#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.253.07:46:18.00#ibcon#ireg 17 cls_cnt 0 2006.253.07:46:18.00#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.253.07:46:18.00#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.253.07:46:18.00#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.253.07:46:18.00#ibcon#enter wrdev, iclass 12, count 0 2006.253.07:46:18.00#ibcon#first serial, iclass 12, count 0 2006.253.07:46:18.00#ibcon#enter sib2, iclass 12, count 0 2006.253.07:46:18.00#ibcon#flushed, iclass 12, count 0 2006.253.07:46:18.00#ibcon#about to write, iclass 12, count 0 2006.253.07:46:18.00#ibcon#wrote, iclass 12, count 0 2006.253.07:46:18.00#ibcon#about to read 3, iclass 12, count 0 2006.253.07:46:18.04#ibcon#read 3, iclass 12, count 0 2006.253.07:46:18.04#ibcon#about to read 4, iclass 12, count 0 2006.253.07:46:18.04#ibcon#read 4, iclass 12, count 0 2006.253.07:46:18.04#ibcon#about to read 5, iclass 12, count 0 2006.253.07:46:18.04#ibcon#read 5, iclass 12, count 0 2006.253.07:46:18.04#ibcon#about to read 6, iclass 12, count 0 2006.253.07:46:18.04#ibcon#read 6, iclass 12, count 0 2006.253.07:46:18.04#ibcon#end of sib2, iclass 12, count 0 2006.253.07:46:18.04#ibcon#*mode == 0, iclass 12, count 0 2006.253.07:46:18.04#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.253.07:46:18.04#ibcon#[26=FRQ=01,532.99\r\n] 2006.253.07:46:18.04#ibcon#*before write, iclass 12, count 0 2006.253.07:46:18.04#ibcon#enter sib2, iclass 12, count 0 2006.253.07:46:18.04#ibcon#flushed, iclass 12, count 0 2006.253.07:46:18.04#ibcon#about to write, iclass 12, count 0 2006.253.07:46:18.04#ibcon#wrote, iclass 12, count 0 2006.253.07:46:18.04#ibcon#about to read 3, iclass 12, count 0 2006.253.07:46:18.08#ibcon#read 3, iclass 12, count 0 2006.253.07:46:18.08#ibcon#about to read 4, iclass 12, count 0 2006.253.07:46:18.08#ibcon#read 4, iclass 12, count 0 2006.253.07:46:18.08#ibcon#about to read 5, iclass 12, count 0 2006.253.07:46:18.08#ibcon#read 5, iclass 12, count 0 2006.253.07:46:18.08#ibcon#about to read 6, iclass 12, count 0 2006.253.07:46:18.08#ibcon#read 6, iclass 12, count 0 2006.253.07:46:18.08#ibcon#end of sib2, iclass 12, count 0 2006.253.07:46:18.08#ibcon#*after write, iclass 12, count 0 2006.253.07:46:18.08#ibcon#*before return 0, iclass 12, count 0 2006.253.07:46:18.08#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.253.07:46:18.08#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.253.07:46:18.08#ibcon#about to clear, iclass 12 cls_cnt 0 2006.253.07:46:18.08#ibcon#cleared, iclass 12 cls_cnt 0 2006.253.07:46:18.08$vc4f8/va=1,8 2006.253.07:46:18.09#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.253.07:46:18.09#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.253.07:46:18.09#ibcon#ireg 11 cls_cnt 2 2006.253.07:46:18.09#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.253.07:46:18.09#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.253.07:46:18.09#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.253.07:46:18.09#ibcon#enter wrdev, iclass 14, count 2 2006.253.07:46:18.09#ibcon#first serial, iclass 14, count 2 2006.253.07:46:18.09#ibcon#enter sib2, iclass 14, count 2 2006.253.07:46:18.09#ibcon#flushed, iclass 14, count 2 2006.253.07:46:18.09#ibcon#about to write, iclass 14, count 2 2006.253.07:46:18.09#ibcon#wrote, iclass 14, count 2 2006.253.07:46:18.09#ibcon#about to read 3, iclass 14, count 2 2006.253.07:46:18.10#ibcon#read 3, iclass 14, count 2 2006.253.07:46:18.10#ibcon#about to read 4, iclass 14, count 2 2006.253.07:46:18.10#ibcon#read 4, iclass 14, count 2 2006.253.07:46:18.10#ibcon#about to read 5, iclass 14, count 2 2006.253.07:46:18.10#ibcon#read 5, iclass 14, count 2 2006.253.07:46:18.10#ibcon#about to read 6, iclass 14, count 2 2006.253.07:46:18.10#ibcon#read 6, iclass 14, count 2 2006.253.07:46:18.10#ibcon#end of sib2, iclass 14, count 2 2006.253.07:46:18.10#ibcon#*mode == 0, iclass 14, count 2 2006.253.07:46:18.10#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.253.07:46:18.10#ibcon#[25=AT01-08\r\n] 2006.253.07:46:18.10#ibcon#*before write, iclass 14, count 2 2006.253.07:46:18.10#ibcon#enter sib2, iclass 14, count 2 2006.253.07:46:18.10#ibcon#flushed, iclass 14, count 2 2006.253.07:46:18.10#ibcon#about to write, iclass 14, count 2 2006.253.07:46:18.10#ibcon#wrote, iclass 14, count 2 2006.253.07:46:18.10#ibcon#about to read 3, iclass 14, count 2 2006.253.07:46:18.13#ibcon#read 3, iclass 14, count 2 2006.253.07:46:18.13#ibcon#about to read 4, iclass 14, count 2 2006.253.07:46:18.13#ibcon#read 4, iclass 14, count 2 2006.253.07:46:18.13#ibcon#about to read 5, iclass 14, count 2 2006.253.07:46:18.13#ibcon#read 5, iclass 14, count 2 2006.253.07:46:18.13#ibcon#about to read 6, iclass 14, count 2 2006.253.07:46:18.13#ibcon#read 6, iclass 14, count 2 2006.253.07:46:18.13#ibcon#end of sib2, iclass 14, count 2 2006.253.07:46:18.13#ibcon#*after write, iclass 14, count 2 2006.253.07:46:18.13#ibcon#*before return 0, iclass 14, count 2 2006.253.07:46:18.13#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.253.07:46:18.13#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.253.07:46:18.13#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.253.07:46:18.13#ibcon#ireg 7 cls_cnt 0 2006.253.07:46:18.13#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.253.07:46:18.25#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.253.07:46:18.25#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.253.07:46:18.25#ibcon#enter wrdev, iclass 14, count 0 2006.253.07:46:18.25#ibcon#first serial, iclass 14, count 0 2006.253.07:46:18.25#ibcon#enter sib2, iclass 14, count 0 2006.253.07:46:18.25#ibcon#flushed, iclass 14, count 0 2006.253.07:46:18.25#ibcon#about to write, iclass 14, count 0 2006.253.07:46:18.25#ibcon#wrote, iclass 14, count 0 2006.253.07:46:18.25#ibcon#about to read 3, iclass 14, count 0 2006.253.07:46:18.27#ibcon#read 3, iclass 14, count 0 2006.253.07:46:18.27#ibcon#about to read 4, iclass 14, count 0 2006.253.07:46:18.27#ibcon#read 4, iclass 14, count 0 2006.253.07:46:18.27#ibcon#about to read 5, iclass 14, count 0 2006.253.07:46:18.27#ibcon#read 5, iclass 14, count 0 2006.253.07:46:18.27#ibcon#about to read 6, iclass 14, count 0 2006.253.07:46:18.27#ibcon#read 6, iclass 14, count 0 2006.253.07:46:18.27#ibcon#end of sib2, iclass 14, count 0 2006.253.07:46:18.27#ibcon#*mode == 0, iclass 14, count 0 2006.253.07:46:18.27#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.253.07:46:18.27#ibcon#[25=USB\r\n] 2006.253.07:46:18.27#ibcon#*before write, iclass 14, count 0 2006.253.07:46:18.27#ibcon#enter sib2, iclass 14, count 0 2006.253.07:46:18.27#ibcon#flushed, iclass 14, count 0 2006.253.07:46:18.27#ibcon#about to write, iclass 14, count 0 2006.253.07:46:18.27#ibcon#wrote, iclass 14, count 0 2006.253.07:46:18.27#ibcon#about to read 3, iclass 14, count 0 2006.253.07:46:18.30#ibcon#read 3, iclass 14, count 0 2006.253.07:46:18.30#ibcon#about to read 4, iclass 14, count 0 2006.253.07:46:18.30#ibcon#read 4, iclass 14, count 0 2006.253.07:46:18.30#ibcon#about to read 5, iclass 14, count 0 2006.253.07:46:18.30#ibcon#read 5, iclass 14, count 0 2006.253.07:46:18.30#ibcon#about to read 6, iclass 14, count 0 2006.253.07:46:18.30#ibcon#read 6, iclass 14, count 0 2006.253.07:46:18.30#ibcon#end of sib2, iclass 14, count 0 2006.253.07:46:18.30#ibcon#*after write, iclass 14, count 0 2006.253.07:46:18.30#ibcon#*before return 0, iclass 14, count 0 2006.253.07:46:18.30#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.253.07:46:18.30#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.253.07:46:18.30#ibcon#about to clear, iclass 14 cls_cnt 0 2006.253.07:46:18.30#ibcon#cleared, iclass 14 cls_cnt 0 2006.253.07:46:18.30$vc4f8/valo=2,572.99 2006.253.07:46:18.31#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.253.07:46:18.31#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.253.07:46:18.31#ibcon#ireg 17 cls_cnt 0 2006.253.07:46:18.31#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.253.07:46:18.31#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.253.07:46:18.31#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.253.07:46:18.31#ibcon#enter wrdev, iclass 16, count 0 2006.253.07:46:18.31#ibcon#first serial, iclass 16, count 0 2006.253.07:46:18.31#ibcon#enter sib2, iclass 16, count 0 2006.253.07:46:18.31#ibcon#flushed, iclass 16, count 0 2006.253.07:46:18.31#ibcon#about to write, iclass 16, count 0 2006.253.07:46:18.31#ibcon#wrote, iclass 16, count 0 2006.253.07:46:18.31#ibcon#about to read 3, iclass 16, count 0 2006.253.07:46:18.33#ibcon#read 3, iclass 16, count 0 2006.253.07:46:18.33#ibcon#about to read 4, iclass 16, count 0 2006.253.07:46:18.33#ibcon#read 4, iclass 16, count 0 2006.253.07:46:18.33#ibcon#about to read 5, iclass 16, count 0 2006.253.07:46:18.33#ibcon#read 5, iclass 16, count 0 2006.253.07:46:18.33#ibcon#about to read 6, iclass 16, count 0 2006.253.07:46:18.33#ibcon#read 6, iclass 16, count 0 2006.253.07:46:18.33#ibcon#end of sib2, iclass 16, count 0 2006.253.07:46:18.33#ibcon#*mode == 0, iclass 16, count 0 2006.253.07:46:18.33#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.253.07:46:18.33#ibcon#[26=FRQ=02,572.99\r\n] 2006.253.07:46:18.33#ibcon#*before write, iclass 16, count 0 2006.253.07:46:18.33#ibcon#enter sib2, iclass 16, count 0 2006.253.07:46:18.33#ibcon#flushed, iclass 16, count 0 2006.253.07:46:18.33#ibcon#about to write, iclass 16, count 0 2006.253.07:46:18.33#ibcon#wrote, iclass 16, count 0 2006.253.07:46:18.33#ibcon#about to read 3, iclass 16, count 0 2006.253.07:46:18.37#ibcon#read 3, iclass 16, count 0 2006.253.07:46:18.37#ibcon#about to read 4, iclass 16, count 0 2006.253.07:46:18.37#ibcon#read 4, iclass 16, count 0 2006.253.07:46:18.37#ibcon#about to read 5, iclass 16, count 0 2006.253.07:46:18.37#ibcon#read 5, iclass 16, count 0 2006.253.07:46:18.37#ibcon#about to read 6, iclass 16, count 0 2006.253.07:46:18.37#ibcon#read 6, iclass 16, count 0 2006.253.07:46:18.37#ibcon#end of sib2, iclass 16, count 0 2006.253.07:46:18.37#ibcon#*after write, iclass 16, count 0 2006.253.07:46:18.37#ibcon#*before return 0, iclass 16, count 0 2006.253.07:46:18.37#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.253.07:46:18.37#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.253.07:46:18.37#ibcon#about to clear, iclass 16 cls_cnt 0 2006.253.07:46:18.37#ibcon#cleared, iclass 16 cls_cnt 0 2006.253.07:46:18.38$vc4f8/va=2,7 2006.253.07:46:18.38#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.253.07:46:18.38#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.253.07:46:18.38#ibcon#ireg 11 cls_cnt 2 2006.253.07:46:18.38#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.253.07:46:18.41#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.253.07:46:18.41#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.253.07:46:18.41#ibcon#enter wrdev, iclass 18, count 2 2006.253.07:46:18.41#ibcon#first serial, iclass 18, count 2 2006.253.07:46:18.41#ibcon#enter sib2, iclass 18, count 2 2006.253.07:46:18.41#ibcon#flushed, iclass 18, count 2 2006.253.07:46:18.41#ibcon#about to write, iclass 18, count 2 2006.253.07:46:18.41#ibcon#wrote, iclass 18, count 2 2006.253.07:46:18.41#ibcon#about to read 3, iclass 18, count 2 2006.253.07:46:18.43#ibcon#read 3, iclass 18, count 2 2006.253.07:46:18.43#ibcon#about to read 4, iclass 18, count 2 2006.253.07:46:18.43#ibcon#read 4, iclass 18, count 2 2006.253.07:46:18.43#ibcon#about to read 5, iclass 18, count 2 2006.253.07:46:18.43#ibcon#read 5, iclass 18, count 2 2006.253.07:46:18.43#ibcon#about to read 6, iclass 18, count 2 2006.253.07:46:18.43#ibcon#read 6, iclass 18, count 2 2006.253.07:46:18.43#ibcon#end of sib2, iclass 18, count 2 2006.253.07:46:18.43#ibcon#*mode == 0, iclass 18, count 2 2006.253.07:46:18.43#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.253.07:46:18.43#ibcon#[25=AT02-07\r\n] 2006.253.07:46:18.43#ibcon#*before write, iclass 18, count 2 2006.253.07:46:18.43#ibcon#enter sib2, iclass 18, count 2 2006.253.07:46:18.43#ibcon#flushed, iclass 18, count 2 2006.253.07:46:18.43#ibcon#about to write, iclass 18, count 2 2006.253.07:46:18.43#ibcon#wrote, iclass 18, count 2 2006.253.07:46:18.43#ibcon#about to read 3, iclass 18, count 2 2006.253.07:46:18.46#ibcon#read 3, iclass 18, count 2 2006.253.07:46:18.46#ibcon#about to read 4, iclass 18, count 2 2006.253.07:46:18.46#ibcon#read 4, iclass 18, count 2 2006.253.07:46:18.46#ibcon#about to read 5, iclass 18, count 2 2006.253.07:46:18.46#ibcon#read 5, iclass 18, count 2 2006.253.07:46:18.46#ibcon#about to read 6, iclass 18, count 2 2006.253.07:46:18.46#ibcon#read 6, iclass 18, count 2 2006.253.07:46:18.46#ibcon#end of sib2, iclass 18, count 2 2006.253.07:46:18.46#ibcon#*after write, iclass 18, count 2 2006.253.07:46:18.46#ibcon#*before return 0, iclass 18, count 2 2006.253.07:46:18.46#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.253.07:46:18.46#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.253.07:46:18.46#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.253.07:46:18.46#ibcon#ireg 7 cls_cnt 0 2006.253.07:46:18.46#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.253.07:46:18.58#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.253.07:46:18.58#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.253.07:46:18.58#ibcon#enter wrdev, iclass 18, count 0 2006.253.07:46:18.58#ibcon#first serial, iclass 18, count 0 2006.253.07:46:18.58#ibcon#enter sib2, iclass 18, count 0 2006.253.07:46:18.58#ibcon#flushed, iclass 18, count 0 2006.253.07:46:18.58#ibcon#about to write, iclass 18, count 0 2006.253.07:46:18.58#ibcon#wrote, iclass 18, count 0 2006.253.07:46:18.58#ibcon#about to read 3, iclass 18, count 0 2006.253.07:46:18.60#ibcon#read 3, iclass 18, count 0 2006.253.07:46:18.60#ibcon#about to read 4, iclass 18, count 0 2006.253.07:46:18.60#ibcon#read 4, iclass 18, count 0 2006.253.07:46:18.60#ibcon#about to read 5, iclass 18, count 0 2006.253.07:46:18.60#ibcon#read 5, iclass 18, count 0 2006.253.07:46:18.60#ibcon#about to read 6, iclass 18, count 0 2006.253.07:46:18.60#ibcon#read 6, iclass 18, count 0 2006.253.07:46:18.60#ibcon#end of sib2, iclass 18, count 0 2006.253.07:46:18.60#ibcon#*mode == 0, iclass 18, count 0 2006.253.07:46:18.60#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.253.07:46:18.60#ibcon#[25=USB\r\n] 2006.253.07:46:18.60#ibcon#*before write, iclass 18, count 0 2006.253.07:46:18.60#ibcon#enter sib2, iclass 18, count 0 2006.253.07:46:18.60#ibcon#flushed, iclass 18, count 0 2006.253.07:46:18.60#ibcon#about to write, iclass 18, count 0 2006.253.07:46:18.60#ibcon#wrote, iclass 18, count 0 2006.253.07:46:18.60#ibcon#about to read 3, iclass 18, count 0 2006.253.07:46:18.63#ibcon#read 3, iclass 18, count 0 2006.253.07:46:18.63#ibcon#about to read 4, iclass 18, count 0 2006.253.07:46:18.63#ibcon#read 4, iclass 18, count 0 2006.253.07:46:18.63#ibcon#about to read 5, iclass 18, count 0 2006.253.07:46:18.63#ibcon#read 5, iclass 18, count 0 2006.253.07:46:18.63#ibcon#about to read 6, iclass 18, count 0 2006.253.07:46:18.63#ibcon#read 6, iclass 18, count 0 2006.253.07:46:18.63#ibcon#end of sib2, iclass 18, count 0 2006.253.07:46:18.63#ibcon#*after write, iclass 18, count 0 2006.253.07:46:18.63#ibcon#*before return 0, iclass 18, count 0 2006.253.07:46:18.63#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.253.07:46:18.63#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.253.07:46:18.63#ibcon#about to clear, iclass 18 cls_cnt 0 2006.253.07:46:18.63#ibcon#cleared, iclass 18 cls_cnt 0 2006.253.07:46:18.63$vc4f8/valo=3,672.99 2006.253.07:46:18.64#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.253.07:46:18.64#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.253.07:46:18.64#ibcon#ireg 17 cls_cnt 0 2006.253.07:46:18.64#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.253.07:46:18.64#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.253.07:46:18.64#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.253.07:46:18.64#ibcon#enter wrdev, iclass 20, count 0 2006.253.07:46:18.64#ibcon#first serial, iclass 20, count 0 2006.253.07:46:18.64#ibcon#enter sib2, iclass 20, count 0 2006.253.07:46:18.64#ibcon#flushed, iclass 20, count 0 2006.253.07:46:18.64#ibcon#about to write, iclass 20, count 0 2006.253.07:46:18.64#ibcon#wrote, iclass 20, count 0 2006.253.07:46:18.64#ibcon#about to read 3, iclass 20, count 0 2006.253.07:46:18.66#ibcon#read 3, iclass 20, count 0 2006.253.07:46:18.66#ibcon#about to read 4, iclass 20, count 0 2006.253.07:46:18.66#ibcon#read 4, iclass 20, count 0 2006.253.07:46:18.66#ibcon#about to read 5, iclass 20, count 0 2006.253.07:46:18.66#ibcon#read 5, iclass 20, count 0 2006.253.07:46:18.66#ibcon#about to read 6, iclass 20, count 0 2006.253.07:46:18.66#ibcon#read 6, iclass 20, count 0 2006.253.07:46:18.66#ibcon#end of sib2, iclass 20, count 0 2006.253.07:46:18.66#ibcon#*mode == 0, iclass 20, count 0 2006.253.07:46:18.66#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.253.07:46:18.66#ibcon#[26=FRQ=03,672.99\r\n] 2006.253.07:46:18.66#ibcon#*before write, iclass 20, count 0 2006.253.07:46:18.66#ibcon#enter sib2, iclass 20, count 0 2006.253.07:46:18.66#ibcon#flushed, iclass 20, count 0 2006.253.07:46:18.66#ibcon#about to write, iclass 20, count 0 2006.253.07:46:18.66#ibcon#wrote, iclass 20, count 0 2006.253.07:46:18.66#ibcon#about to read 3, iclass 20, count 0 2006.253.07:46:18.70#ibcon#read 3, iclass 20, count 0 2006.253.07:46:18.70#ibcon#about to read 4, iclass 20, count 0 2006.253.07:46:18.70#ibcon#read 4, iclass 20, count 0 2006.253.07:46:18.70#ibcon#about to read 5, iclass 20, count 0 2006.253.07:46:18.70#ibcon#read 5, iclass 20, count 0 2006.253.07:46:18.70#ibcon#about to read 6, iclass 20, count 0 2006.253.07:46:18.70#ibcon#read 6, iclass 20, count 0 2006.253.07:46:18.70#ibcon#end of sib2, iclass 20, count 0 2006.253.07:46:18.70#ibcon#*after write, iclass 20, count 0 2006.253.07:46:18.70#ibcon#*before return 0, iclass 20, count 0 2006.253.07:46:18.70#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.253.07:46:18.70#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.253.07:46:18.70#ibcon#about to clear, iclass 20 cls_cnt 0 2006.253.07:46:18.70#ibcon#cleared, iclass 20 cls_cnt 0 2006.253.07:46:18.71$vc4f8/va=3,6 2006.253.07:46:18.71#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.253.07:46:18.71#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.253.07:46:18.71#ibcon#ireg 11 cls_cnt 2 2006.253.07:46:18.71#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.253.07:46:18.74#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.253.07:46:18.74#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.253.07:46:18.74#ibcon#enter wrdev, iclass 22, count 2 2006.253.07:46:18.74#ibcon#first serial, iclass 22, count 2 2006.253.07:46:18.74#ibcon#enter sib2, iclass 22, count 2 2006.253.07:46:18.74#ibcon#flushed, iclass 22, count 2 2006.253.07:46:18.74#ibcon#about to write, iclass 22, count 2 2006.253.07:46:18.74#ibcon#wrote, iclass 22, count 2 2006.253.07:46:18.74#ibcon#about to read 3, iclass 22, count 2 2006.253.07:46:18.77#ibcon#read 3, iclass 22, count 2 2006.253.07:46:18.77#ibcon#about to read 4, iclass 22, count 2 2006.253.07:46:18.77#ibcon#read 4, iclass 22, count 2 2006.253.07:46:18.77#ibcon#about to read 5, iclass 22, count 2 2006.253.07:46:18.77#ibcon#read 5, iclass 22, count 2 2006.253.07:46:18.77#ibcon#about to read 6, iclass 22, count 2 2006.253.07:46:18.77#ibcon#read 6, iclass 22, count 2 2006.253.07:46:18.77#ibcon#end of sib2, iclass 22, count 2 2006.253.07:46:18.77#ibcon#*mode == 0, iclass 22, count 2 2006.253.07:46:18.77#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.253.07:46:18.77#ibcon#[25=AT03-06\r\n] 2006.253.07:46:18.77#ibcon#*before write, iclass 22, count 2 2006.253.07:46:18.77#ibcon#enter sib2, iclass 22, count 2 2006.253.07:46:18.77#ibcon#flushed, iclass 22, count 2 2006.253.07:46:18.77#ibcon#about to write, iclass 22, count 2 2006.253.07:46:18.77#ibcon#wrote, iclass 22, count 2 2006.253.07:46:18.77#ibcon#about to read 3, iclass 22, count 2 2006.253.07:46:18.80#ibcon#read 3, iclass 22, count 2 2006.253.07:46:18.80#ibcon#about to read 4, iclass 22, count 2 2006.253.07:46:18.80#ibcon#read 4, iclass 22, count 2 2006.253.07:46:18.80#ibcon#about to read 5, iclass 22, count 2 2006.253.07:46:18.80#ibcon#read 5, iclass 22, count 2 2006.253.07:46:18.80#ibcon#about to read 6, iclass 22, count 2 2006.253.07:46:18.80#ibcon#read 6, iclass 22, count 2 2006.253.07:46:18.80#ibcon#end of sib2, iclass 22, count 2 2006.253.07:46:18.80#ibcon#*after write, iclass 22, count 2 2006.253.07:46:18.80#ibcon#*before return 0, iclass 22, count 2 2006.253.07:46:18.80#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.253.07:46:18.80#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.253.07:46:18.80#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.253.07:46:18.80#ibcon#ireg 7 cls_cnt 0 2006.253.07:46:18.80#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.253.07:46:18.92#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.253.07:46:18.92#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.253.07:46:18.92#ibcon#enter wrdev, iclass 22, count 0 2006.253.07:46:18.92#ibcon#first serial, iclass 22, count 0 2006.253.07:46:18.92#ibcon#enter sib2, iclass 22, count 0 2006.253.07:46:18.92#ibcon#flushed, iclass 22, count 0 2006.253.07:46:18.92#ibcon#about to write, iclass 22, count 0 2006.253.07:46:18.92#ibcon#wrote, iclass 22, count 0 2006.253.07:46:18.92#ibcon#about to read 3, iclass 22, count 0 2006.253.07:46:18.94#ibcon#read 3, iclass 22, count 0 2006.253.07:46:18.94#ibcon#about to read 4, iclass 22, count 0 2006.253.07:46:18.94#ibcon#read 4, iclass 22, count 0 2006.253.07:46:18.94#ibcon#about to read 5, iclass 22, count 0 2006.253.07:46:18.94#ibcon#read 5, iclass 22, count 0 2006.253.07:46:18.94#ibcon#about to read 6, iclass 22, count 0 2006.253.07:46:18.94#ibcon#read 6, iclass 22, count 0 2006.253.07:46:18.94#ibcon#end of sib2, iclass 22, count 0 2006.253.07:46:18.94#ibcon#*mode == 0, iclass 22, count 0 2006.253.07:46:18.94#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.253.07:46:18.94#ibcon#[25=USB\r\n] 2006.253.07:46:18.94#ibcon#*before write, iclass 22, count 0 2006.253.07:46:18.94#ibcon#enter sib2, iclass 22, count 0 2006.253.07:46:18.94#ibcon#flushed, iclass 22, count 0 2006.253.07:46:18.94#ibcon#about to write, iclass 22, count 0 2006.253.07:46:18.94#ibcon#wrote, iclass 22, count 0 2006.253.07:46:18.94#ibcon#about to read 3, iclass 22, count 0 2006.253.07:46:18.97#ibcon#read 3, iclass 22, count 0 2006.253.07:46:18.97#ibcon#about to read 4, iclass 22, count 0 2006.253.07:46:18.97#ibcon#read 4, iclass 22, count 0 2006.253.07:46:18.97#ibcon#about to read 5, iclass 22, count 0 2006.253.07:46:18.97#ibcon#read 5, iclass 22, count 0 2006.253.07:46:18.97#ibcon#about to read 6, iclass 22, count 0 2006.253.07:46:18.97#ibcon#read 6, iclass 22, count 0 2006.253.07:46:18.97#ibcon#end of sib2, iclass 22, count 0 2006.253.07:46:18.97#ibcon#*after write, iclass 22, count 0 2006.253.07:46:18.97#ibcon#*before return 0, iclass 22, count 0 2006.253.07:46:18.97#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.253.07:46:18.97#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.253.07:46:18.97#ibcon#about to clear, iclass 22 cls_cnt 0 2006.253.07:46:18.97#ibcon#cleared, iclass 22 cls_cnt 0 2006.253.07:46:18.97$vc4f8/valo=4,832.99 2006.253.07:46:18.98#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.253.07:46:18.98#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.253.07:46:18.98#ibcon#ireg 17 cls_cnt 0 2006.253.07:46:18.98#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.253.07:46:18.98#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.253.07:46:18.98#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.253.07:46:18.98#ibcon#enter wrdev, iclass 24, count 0 2006.253.07:46:18.98#ibcon#first serial, iclass 24, count 0 2006.253.07:46:18.98#ibcon#enter sib2, iclass 24, count 0 2006.253.07:46:18.98#ibcon#flushed, iclass 24, count 0 2006.253.07:46:18.98#ibcon#about to write, iclass 24, count 0 2006.253.07:46:18.98#ibcon#wrote, iclass 24, count 0 2006.253.07:46:18.98#ibcon#about to read 3, iclass 24, count 0 2006.253.07:46:18.99#ibcon#read 3, iclass 24, count 0 2006.253.07:46:18.99#ibcon#about to read 4, iclass 24, count 0 2006.253.07:46:18.99#ibcon#read 4, iclass 24, count 0 2006.253.07:46:18.99#ibcon#about to read 5, iclass 24, count 0 2006.253.07:46:18.99#ibcon#read 5, iclass 24, count 0 2006.253.07:46:18.99#ibcon#about to read 6, iclass 24, count 0 2006.253.07:46:18.99#ibcon#read 6, iclass 24, count 0 2006.253.07:46:18.99#ibcon#end of sib2, iclass 24, count 0 2006.253.07:46:18.99#ibcon#*mode == 0, iclass 24, count 0 2006.253.07:46:18.99#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.253.07:46:18.99#ibcon#[26=FRQ=04,832.99\r\n] 2006.253.07:46:18.99#ibcon#*before write, iclass 24, count 0 2006.253.07:46:18.99#ibcon#enter sib2, iclass 24, count 0 2006.253.07:46:18.99#ibcon#flushed, iclass 24, count 0 2006.253.07:46:18.99#ibcon#about to write, iclass 24, count 0 2006.253.07:46:18.99#ibcon#wrote, iclass 24, count 0 2006.253.07:46:18.99#ibcon#about to read 3, iclass 24, count 0 2006.253.07:46:19.03#ibcon#read 3, iclass 24, count 0 2006.253.07:46:19.03#ibcon#about to read 4, iclass 24, count 0 2006.253.07:46:19.03#ibcon#read 4, iclass 24, count 0 2006.253.07:46:19.03#ibcon#about to read 5, iclass 24, count 0 2006.253.07:46:19.03#ibcon#read 5, iclass 24, count 0 2006.253.07:46:19.03#ibcon#about to read 6, iclass 24, count 0 2006.253.07:46:19.03#ibcon#read 6, iclass 24, count 0 2006.253.07:46:19.03#ibcon#end of sib2, iclass 24, count 0 2006.253.07:46:19.03#ibcon#*after write, iclass 24, count 0 2006.253.07:46:19.03#ibcon#*before return 0, iclass 24, count 0 2006.253.07:46:19.03#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.253.07:46:19.03#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.253.07:46:19.03#ibcon#about to clear, iclass 24 cls_cnt 0 2006.253.07:46:19.03#ibcon#cleared, iclass 24 cls_cnt 0 2006.253.07:46:19.03$vc4f8/va=4,7 2006.253.07:46:19.04#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.253.07:46:19.04#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.253.07:46:19.04#ibcon#ireg 11 cls_cnt 2 2006.253.07:46:19.04#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.253.07:46:19.08#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.253.07:46:19.08#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.253.07:46:19.08#ibcon#enter wrdev, iclass 26, count 2 2006.253.07:46:19.08#ibcon#first serial, iclass 26, count 2 2006.253.07:46:19.08#ibcon#enter sib2, iclass 26, count 2 2006.253.07:46:19.08#ibcon#flushed, iclass 26, count 2 2006.253.07:46:19.08#ibcon#about to write, iclass 26, count 2 2006.253.07:46:19.08#ibcon#wrote, iclass 26, count 2 2006.253.07:46:19.08#ibcon#about to read 3, iclass 26, count 2 2006.253.07:46:19.10#ibcon#read 3, iclass 26, count 2 2006.253.07:46:19.10#ibcon#about to read 4, iclass 26, count 2 2006.253.07:46:19.10#ibcon#read 4, iclass 26, count 2 2006.253.07:46:19.10#ibcon#about to read 5, iclass 26, count 2 2006.253.07:46:19.10#ibcon#read 5, iclass 26, count 2 2006.253.07:46:19.10#ibcon#about to read 6, iclass 26, count 2 2006.253.07:46:19.10#ibcon#read 6, iclass 26, count 2 2006.253.07:46:19.10#ibcon#end of sib2, iclass 26, count 2 2006.253.07:46:19.10#ibcon#*mode == 0, iclass 26, count 2 2006.253.07:46:19.10#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.253.07:46:19.10#ibcon#[25=AT04-07\r\n] 2006.253.07:46:19.10#ibcon#*before write, iclass 26, count 2 2006.253.07:46:19.10#ibcon#enter sib2, iclass 26, count 2 2006.253.07:46:19.10#ibcon#flushed, iclass 26, count 2 2006.253.07:46:19.10#ibcon#about to write, iclass 26, count 2 2006.253.07:46:19.10#ibcon#wrote, iclass 26, count 2 2006.253.07:46:19.10#ibcon#about to read 3, iclass 26, count 2 2006.253.07:46:19.13#ibcon#read 3, iclass 26, count 2 2006.253.07:46:19.13#ibcon#about to read 4, iclass 26, count 2 2006.253.07:46:19.13#ibcon#read 4, iclass 26, count 2 2006.253.07:46:19.13#ibcon#about to read 5, iclass 26, count 2 2006.253.07:46:19.13#ibcon#read 5, iclass 26, count 2 2006.253.07:46:19.13#ibcon#about to read 6, iclass 26, count 2 2006.253.07:46:19.13#ibcon#read 6, iclass 26, count 2 2006.253.07:46:19.13#ibcon#end of sib2, iclass 26, count 2 2006.253.07:46:19.13#ibcon#*after write, iclass 26, count 2 2006.253.07:46:19.13#ibcon#*before return 0, iclass 26, count 2 2006.253.07:46:19.13#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.253.07:46:19.13#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.253.07:46:19.13#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.253.07:46:19.13#ibcon#ireg 7 cls_cnt 0 2006.253.07:46:19.13#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.253.07:46:19.25#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.253.07:46:19.25#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.253.07:46:19.25#ibcon#enter wrdev, iclass 26, count 0 2006.253.07:46:19.25#ibcon#first serial, iclass 26, count 0 2006.253.07:46:19.25#ibcon#enter sib2, iclass 26, count 0 2006.253.07:46:19.25#ibcon#flushed, iclass 26, count 0 2006.253.07:46:19.25#ibcon#about to write, iclass 26, count 0 2006.253.07:46:19.25#ibcon#wrote, iclass 26, count 0 2006.253.07:46:19.25#ibcon#about to read 3, iclass 26, count 0 2006.253.07:46:19.27#ibcon#read 3, iclass 26, count 0 2006.253.07:46:19.27#ibcon#about to read 4, iclass 26, count 0 2006.253.07:46:19.27#ibcon#read 4, iclass 26, count 0 2006.253.07:46:19.27#ibcon#about to read 5, iclass 26, count 0 2006.253.07:46:19.27#ibcon#read 5, iclass 26, count 0 2006.253.07:46:19.27#ibcon#about to read 6, iclass 26, count 0 2006.253.07:46:19.27#ibcon#read 6, iclass 26, count 0 2006.253.07:46:19.27#ibcon#end of sib2, iclass 26, count 0 2006.253.07:46:19.27#ibcon#*mode == 0, iclass 26, count 0 2006.253.07:46:19.27#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.253.07:46:19.27#ibcon#[25=USB\r\n] 2006.253.07:46:19.27#ibcon#*before write, iclass 26, count 0 2006.253.07:46:19.27#ibcon#enter sib2, iclass 26, count 0 2006.253.07:46:19.27#ibcon#flushed, iclass 26, count 0 2006.253.07:46:19.27#ibcon#about to write, iclass 26, count 0 2006.253.07:46:19.27#ibcon#wrote, iclass 26, count 0 2006.253.07:46:19.27#ibcon#about to read 3, iclass 26, count 0 2006.253.07:46:19.30#ibcon#read 3, iclass 26, count 0 2006.253.07:46:19.30#ibcon#about to read 4, iclass 26, count 0 2006.253.07:46:19.30#ibcon#read 4, iclass 26, count 0 2006.253.07:46:19.30#ibcon#about to read 5, iclass 26, count 0 2006.253.07:46:19.30#ibcon#read 5, iclass 26, count 0 2006.253.07:46:19.30#ibcon#about to read 6, iclass 26, count 0 2006.253.07:46:19.30#ibcon#read 6, iclass 26, count 0 2006.253.07:46:19.30#ibcon#end of sib2, iclass 26, count 0 2006.253.07:46:19.30#ibcon#*after write, iclass 26, count 0 2006.253.07:46:19.30#ibcon#*before return 0, iclass 26, count 0 2006.253.07:46:19.30#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.253.07:46:19.30#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.253.07:46:19.30#ibcon#about to clear, iclass 26 cls_cnt 0 2006.253.07:46:19.30#ibcon#cleared, iclass 26 cls_cnt 0 2006.253.07:46:19.30$vc4f8/valo=5,652.99 2006.253.07:46:19.31#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.253.07:46:19.31#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.253.07:46:19.31#ibcon#ireg 17 cls_cnt 0 2006.253.07:46:19.31#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.253.07:46:19.31#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.253.07:46:19.31#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.253.07:46:19.31#ibcon#enter wrdev, iclass 28, count 0 2006.253.07:46:19.31#ibcon#first serial, iclass 28, count 0 2006.253.07:46:19.31#ibcon#enter sib2, iclass 28, count 0 2006.253.07:46:19.31#ibcon#flushed, iclass 28, count 0 2006.253.07:46:19.31#ibcon#about to write, iclass 28, count 0 2006.253.07:46:19.31#ibcon#wrote, iclass 28, count 0 2006.253.07:46:19.31#ibcon#about to read 3, iclass 28, count 0 2006.253.07:46:19.32#ibcon#read 3, iclass 28, count 0 2006.253.07:46:19.32#ibcon#about to read 4, iclass 28, count 0 2006.253.07:46:19.32#ibcon#read 4, iclass 28, count 0 2006.253.07:46:19.32#ibcon#about to read 5, iclass 28, count 0 2006.253.07:46:19.32#ibcon#read 5, iclass 28, count 0 2006.253.07:46:19.32#ibcon#about to read 6, iclass 28, count 0 2006.253.07:46:19.32#ibcon#read 6, iclass 28, count 0 2006.253.07:46:19.32#ibcon#end of sib2, iclass 28, count 0 2006.253.07:46:19.32#ibcon#*mode == 0, iclass 28, count 0 2006.253.07:46:19.32#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.253.07:46:19.32#ibcon#[26=FRQ=05,652.99\r\n] 2006.253.07:46:19.32#ibcon#*before write, iclass 28, count 0 2006.253.07:46:19.32#ibcon#enter sib2, iclass 28, count 0 2006.253.07:46:19.32#ibcon#flushed, iclass 28, count 0 2006.253.07:46:19.32#ibcon#about to write, iclass 28, count 0 2006.253.07:46:19.32#ibcon#wrote, iclass 28, count 0 2006.253.07:46:19.32#ibcon#about to read 3, iclass 28, count 0 2006.253.07:46:19.36#ibcon#read 3, iclass 28, count 0 2006.253.07:46:19.36#ibcon#about to read 4, iclass 28, count 0 2006.253.07:46:19.36#ibcon#read 4, iclass 28, count 0 2006.253.07:46:19.36#ibcon#about to read 5, iclass 28, count 0 2006.253.07:46:19.36#ibcon#read 5, iclass 28, count 0 2006.253.07:46:19.36#ibcon#about to read 6, iclass 28, count 0 2006.253.07:46:19.36#ibcon#read 6, iclass 28, count 0 2006.253.07:46:19.36#ibcon#end of sib2, iclass 28, count 0 2006.253.07:46:19.36#ibcon#*after write, iclass 28, count 0 2006.253.07:46:19.36#ibcon#*before return 0, iclass 28, count 0 2006.253.07:46:19.36#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.253.07:46:19.36#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.253.07:46:19.36#ibcon#about to clear, iclass 28 cls_cnt 0 2006.253.07:46:19.36#ibcon#cleared, iclass 28 cls_cnt 0 2006.253.07:46:19.36$vc4f8/va=5,7 2006.253.07:46:19.37#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.253.07:46:19.37#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.253.07:46:19.37#ibcon#ireg 11 cls_cnt 2 2006.253.07:46:19.37#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.253.07:46:19.41#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.253.07:46:19.41#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.253.07:46:19.41#ibcon#enter wrdev, iclass 30, count 2 2006.253.07:46:19.41#ibcon#first serial, iclass 30, count 2 2006.253.07:46:19.41#ibcon#enter sib2, iclass 30, count 2 2006.253.07:46:19.41#ibcon#flushed, iclass 30, count 2 2006.253.07:46:19.41#ibcon#about to write, iclass 30, count 2 2006.253.07:46:19.41#ibcon#wrote, iclass 30, count 2 2006.253.07:46:19.41#ibcon#about to read 3, iclass 30, count 2 2006.253.07:46:19.43#ibcon#read 3, iclass 30, count 2 2006.253.07:46:19.43#ibcon#about to read 4, iclass 30, count 2 2006.253.07:46:19.43#ibcon#read 4, iclass 30, count 2 2006.253.07:46:19.43#ibcon#about to read 5, iclass 30, count 2 2006.253.07:46:19.43#ibcon#read 5, iclass 30, count 2 2006.253.07:46:19.43#ibcon#about to read 6, iclass 30, count 2 2006.253.07:46:19.43#ibcon#read 6, iclass 30, count 2 2006.253.07:46:19.43#ibcon#end of sib2, iclass 30, count 2 2006.253.07:46:19.43#ibcon#*mode == 0, iclass 30, count 2 2006.253.07:46:19.43#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.253.07:46:19.43#ibcon#[25=AT05-07\r\n] 2006.253.07:46:19.43#ibcon#*before write, iclass 30, count 2 2006.253.07:46:19.43#ibcon#enter sib2, iclass 30, count 2 2006.253.07:46:19.43#ibcon#flushed, iclass 30, count 2 2006.253.07:46:19.43#ibcon#about to write, iclass 30, count 2 2006.253.07:46:19.43#ibcon#wrote, iclass 30, count 2 2006.253.07:46:19.43#ibcon#about to read 3, iclass 30, count 2 2006.253.07:46:19.46#ibcon#read 3, iclass 30, count 2 2006.253.07:46:19.46#ibcon#about to read 4, iclass 30, count 2 2006.253.07:46:19.46#ibcon#read 4, iclass 30, count 2 2006.253.07:46:19.46#ibcon#about to read 5, iclass 30, count 2 2006.253.07:46:19.46#ibcon#read 5, iclass 30, count 2 2006.253.07:46:19.46#ibcon#about to read 6, iclass 30, count 2 2006.253.07:46:19.46#ibcon#read 6, iclass 30, count 2 2006.253.07:46:19.46#ibcon#end of sib2, iclass 30, count 2 2006.253.07:46:19.46#ibcon#*after write, iclass 30, count 2 2006.253.07:46:19.46#ibcon#*before return 0, iclass 30, count 2 2006.253.07:46:19.46#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.253.07:46:19.46#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.253.07:46:19.46#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.253.07:46:19.46#ibcon#ireg 7 cls_cnt 0 2006.253.07:46:19.46#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.253.07:46:19.58#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.253.07:46:19.58#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.253.07:46:19.58#ibcon#enter wrdev, iclass 30, count 0 2006.253.07:46:19.58#ibcon#first serial, iclass 30, count 0 2006.253.07:46:19.58#ibcon#enter sib2, iclass 30, count 0 2006.253.07:46:19.58#ibcon#flushed, iclass 30, count 0 2006.253.07:46:19.58#ibcon#about to write, iclass 30, count 0 2006.253.07:46:19.58#ibcon#wrote, iclass 30, count 0 2006.253.07:46:19.58#ibcon#about to read 3, iclass 30, count 0 2006.253.07:46:19.60#ibcon#read 3, iclass 30, count 0 2006.253.07:46:19.60#ibcon#about to read 4, iclass 30, count 0 2006.253.07:46:19.60#ibcon#read 4, iclass 30, count 0 2006.253.07:46:19.60#ibcon#about to read 5, iclass 30, count 0 2006.253.07:46:19.60#ibcon#read 5, iclass 30, count 0 2006.253.07:46:19.60#ibcon#about to read 6, iclass 30, count 0 2006.253.07:46:19.60#ibcon#read 6, iclass 30, count 0 2006.253.07:46:19.60#ibcon#end of sib2, iclass 30, count 0 2006.253.07:46:19.60#ibcon#*mode == 0, iclass 30, count 0 2006.253.07:46:19.60#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.253.07:46:19.60#ibcon#[25=USB\r\n] 2006.253.07:46:19.60#ibcon#*before write, iclass 30, count 0 2006.253.07:46:19.60#ibcon#enter sib2, iclass 30, count 0 2006.253.07:46:19.60#ibcon#flushed, iclass 30, count 0 2006.253.07:46:19.60#ibcon#about to write, iclass 30, count 0 2006.253.07:46:19.60#ibcon#wrote, iclass 30, count 0 2006.253.07:46:19.60#ibcon#about to read 3, iclass 30, count 0 2006.253.07:46:19.63#ibcon#read 3, iclass 30, count 0 2006.253.07:46:19.63#ibcon#about to read 4, iclass 30, count 0 2006.253.07:46:19.63#ibcon#read 4, iclass 30, count 0 2006.253.07:46:19.63#ibcon#about to read 5, iclass 30, count 0 2006.253.07:46:19.63#ibcon#read 5, iclass 30, count 0 2006.253.07:46:19.63#ibcon#about to read 6, iclass 30, count 0 2006.253.07:46:19.63#ibcon#read 6, iclass 30, count 0 2006.253.07:46:19.63#ibcon#end of sib2, iclass 30, count 0 2006.253.07:46:19.63#ibcon#*after write, iclass 30, count 0 2006.253.07:46:19.63#ibcon#*before return 0, iclass 30, count 0 2006.253.07:46:19.63#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.253.07:46:19.63#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.253.07:46:19.63#ibcon#about to clear, iclass 30 cls_cnt 0 2006.253.07:46:19.63#ibcon#cleared, iclass 30 cls_cnt 0 2006.253.07:46:19.63$vc4f8/valo=6,772.99 2006.253.07:46:19.64#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.253.07:46:19.64#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.253.07:46:19.64#ibcon#ireg 17 cls_cnt 0 2006.253.07:46:19.64#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.253.07:46:19.64#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.253.07:46:19.64#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.253.07:46:19.64#ibcon#enter wrdev, iclass 32, count 0 2006.253.07:46:19.64#ibcon#first serial, iclass 32, count 0 2006.253.07:46:19.64#ibcon#enter sib2, iclass 32, count 0 2006.253.07:46:19.64#ibcon#flushed, iclass 32, count 0 2006.253.07:46:19.64#ibcon#about to write, iclass 32, count 0 2006.253.07:46:19.64#ibcon#wrote, iclass 32, count 0 2006.253.07:46:19.64#ibcon#about to read 3, iclass 32, count 0 2006.253.07:46:19.66#ibcon#read 3, iclass 32, count 0 2006.253.07:46:19.66#ibcon#about to read 4, iclass 32, count 0 2006.253.07:46:19.66#ibcon#read 4, iclass 32, count 0 2006.253.07:46:19.66#ibcon#about to read 5, iclass 32, count 0 2006.253.07:46:19.66#ibcon#read 5, iclass 32, count 0 2006.253.07:46:19.66#ibcon#about to read 6, iclass 32, count 0 2006.253.07:46:19.66#ibcon#read 6, iclass 32, count 0 2006.253.07:46:19.66#ibcon#end of sib2, iclass 32, count 0 2006.253.07:46:19.66#ibcon#*mode == 0, iclass 32, count 0 2006.253.07:46:19.66#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.253.07:46:19.66#ibcon#[26=FRQ=06,772.99\r\n] 2006.253.07:46:19.66#ibcon#*before write, iclass 32, count 0 2006.253.07:46:19.66#ibcon#enter sib2, iclass 32, count 0 2006.253.07:46:19.66#ibcon#flushed, iclass 32, count 0 2006.253.07:46:19.66#ibcon#about to write, iclass 32, count 0 2006.253.07:46:19.66#ibcon#wrote, iclass 32, count 0 2006.253.07:46:19.66#ibcon#about to read 3, iclass 32, count 0 2006.253.07:46:19.70#ibcon#read 3, iclass 32, count 0 2006.253.07:46:19.70#ibcon#about to read 4, iclass 32, count 0 2006.253.07:46:19.70#ibcon#read 4, iclass 32, count 0 2006.253.07:46:19.70#ibcon#about to read 5, iclass 32, count 0 2006.253.07:46:19.70#ibcon#read 5, iclass 32, count 0 2006.253.07:46:19.70#ibcon#about to read 6, iclass 32, count 0 2006.253.07:46:19.70#ibcon#read 6, iclass 32, count 0 2006.253.07:46:19.70#ibcon#end of sib2, iclass 32, count 0 2006.253.07:46:19.70#ibcon#*after write, iclass 32, count 0 2006.253.07:46:19.70#ibcon#*before return 0, iclass 32, count 0 2006.253.07:46:19.70#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.253.07:46:19.70#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.253.07:46:19.70#ibcon#about to clear, iclass 32 cls_cnt 0 2006.253.07:46:19.70#ibcon#cleared, iclass 32 cls_cnt 0 2006.253.07:46:19.71$vc4f8/va=6,7 2006.253.07:46:19.71#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.253.07:46:19.71#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.253.07:46:19.71#ibcon#ireg 11 cls_cnt 2 2006.253.07:46:19.71#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.253.07:46:19.74#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.253.07:46:19.74#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.253.07:46:19.74#ibcon#enter wrdev, iclass 34, count 2 2006.253.07:46:19.74#ibcon#first serial, iclass 34, count 2 2006.253.07:46:19.74#ibcon#enter sib2, iclass 34, count 2 2006.253.07:46:19.74#ibcon#flushed, iclass 34, count 2 2006.253.07:46:19.74#ibcon#about to write, iclass 34, count 2 2006.253.07:46:19.74#ibcon#wrote, iclass 34, count 2 2006.253.07:46:19.74#ibcon#about to read 3, iclass 34, count 2 2006.253.07:46:19.77#ibcon#read 3, iclass 34, count 2 2006.253.07:46:19.77#ibcon#about to read 4, iclass 34, count 2 2006.253.07:46:19.77#ibcon#read 4, iclass 34, count 2 2006.253.07:46:19.77#ibcon#about to read 5, iclass 34, count 2 2006.253.07:46:19.77#ibcon#read 5, iclass 34, count 2 2006.253.07:46:19.77#ibcon#about to read 6, iclass 34, count 2 2006.253.07:46:19.77#ibcon#read 6, iclass 34, count 2 2006.253.07:46:19.77#ibcon#end of sib2, iclass 34, count 2 2006.253.07:46:19.77#ibcon#*mode == 0, iclass 34, count 2 2006.253.07:46:19.77#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.253.07:46:19.77#ibcon#[25=AT06-07\r\n] 2006.253.07:46:19.77#ibcon#*before write, iclass 34, count 2 2006.253.07:46:19.77#ibcon#enter sib2, iclass 34, count 2 2006.253.07:46:19.77#ibcon#flushed, iclass 34, count 2 2006.253.07:46:19.77#ibcon#about to write, iclass 34, count 2 2006.253.07:46:19.77#ibcon#wrote, iclass 34, count 2 2006.253.07:46:19.77#ibcon#about to read 3, iclass 34, count 2 2006.253.07:46:19.80#ibcon#read 3, iclass 34, count 2 2006.253.07:46:19.80#ibcon#about to read 4, iclass 34, count 2 2006.253.07:46:19.80#ibcon#read 4, iclass 34, count 2 2006.253.07:46:19.80#ibcon#about to read 5, iclass 34, count 2 2006.253.07:46:19.80#ibcon#read 5, iclass 34, count 2 2006.253.07:46:19.80#ibcon#about to read 6, iclass 34, count 2 2006.253.07:46:19.80#ibcon#read 6, iclass 34, count 2 2006.253.07:46:19.80#ibcon#end of sib2, iclass 34, count 2 2006.253.07:46:19.80#ibcon#*after write, iclass 34, count 2 2006.253.07:46:19.80#ibcon#*before return 0, iclass 34, count 2 2006.253.07:46:19.80#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.253.07:46:19.80#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.253.07:46:19.80#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.253.07:46:19.80#ibcon#ireg 7 cls_cnt 0 2006.253.07:46:19.80#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.253.07:46:19.92#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.253.07:46:19.92#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.253.07:46:19.92#ibcon#enter wrdev, iclass 34, count 0 2006.253.07:46:19.92#ibcon#first serial, iclass 34, count 0 2006.253.07:46:19.92#ibcon#enter sib2, iclass 34, count 0 2006.253.07:46:19.92#ibcon#flushed, iclass 34, count 0 2006.253.07:46:19.92#ibcon#about to write, iclass 34, count 0 2006.253.07:46:19.92#ibcon#wrote, iclass 34, count 0 2006.253.07:46:19.92#ibcon#about to read 3, iclass 34, count 0 2006.253.07:46:19.94#ibcon#read 3, iclass 34, count 0 2006.253.07:46:19.94#ibcon#about to read 4, iclass 34, count 0 2006.253.07:46:19.94#ibcon#read 4, iclass 34, count 0 2006.253.07:46:19.94#ibcon#about to read 5, iclass 34, count 0 2006.253.07:46:19.94#ibcon#read 5, iclass 34, count 0 2006.253.07:46:19.94#ibcon#about to read 6, iclass 34, count 0 2006.253.07:46:19.94#ibcon#read 6, iclass 34, count 0 2006.253.07:46:19.94#ibcon#end of sib2, iclass 34, count 0 2006.253.07:46:19.94#ibcon#*mode == 0, iclass 34, count 0 2006.253.07:46:19.94#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.253.07:46:19.94#ibcon#[25=USB\r\n] 2006.253.07:46:19.94#ibcon#*before write, iclass 34, count 0 2006.253.07:46:19.94#ibcon#enter sib2, iclass 34, count 0 2006.253.07:46:19.94#ibcon#flushed, iclass 34, count 0 2006.253.07:46:19.94#ibcon#about to write, iclass 34, count 0 2006.253.07:46:19.94#ibcon#wrote, iclass 34, count 0 2006.253.07:46:19.94#ibcon#about to read 3, iclass 34, count 0 2006.253.07:46:19.97#ibcon#read 3, iclass 34, count 0 2006.253.07:46:19.97#ibcon#about to read 4, iclass 34, count 0 2006.253.07:46:19.97#ibcon#read 4, iclass 34, count 0 2006.253.07:46:19.97#ibcon#about to read 5, iclass 34, count 0 2006.253.07:46:19.97#ibcon#read 5, iclass 34, count 0 2006.253.07:46:19.97#ibcon#about to read 6, iclass 34, count 0 2006.253.07:46:19.97#ibcon#read 6, iclass 34, count 0 2006.253.07:46:19.97#ibcon#end of sib2, iclass 34, count 0 2006.253.07:46:19.97#ibcon#*after write, iclass 34, count 0 2006.253.07:46:19.97#ibcon#*before return 0, iclass 34, count 0 2006.253.07:46:19.97#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.253.07:46:19.97#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.253.07:46:19.97#ibcon#about to clear, iclass 34 cls_cnt 0 2006.253.07:46:19.97#ibcon#cleared, iclass 34 cls_cnt 0 2006.253.07:46:19.97$vc4f8/valo=7,832.99 2006.253.07:46:19.98#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.253.07:46:19.98#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.253.07:46:19.98#ibcon#ireg 17 cls_cnt 0 2006.253.07:46:19.98#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.253.07:46:19.98#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.253.07:46:19.98#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.253.07:46:19.98#ibcon#enter wrdev, iclass 36, count 0 2006.253.07:46:19.98#ibcon#first serial, iclass 36, count 0 2006.253.07:46:19.98#ibcon#enter sib2, iclass 36, count 0 2006.253.07:46:19.98#ibcon#flushed, iclass 36, count 0 2006.253.07:46:19.98#ibcon#about to write, iclass 36, count 0 2006.253.07:46:19.98#ibcon#wrote, iclass 36, count 0 2006.253.07:46:19.98#ibcon#about to read 3, iclass 36, count 0 2006.253.07:46:19.99#ibcon#read 3, iclass 36, count 0 2006.253.07:46:19.99#ibcon#about to read 4, iclass 36, count 0 2006.253.07:46:19.99#ibcon#read 4, iclass 36, count 0 2006.253.07:46:19.99#ibcon#about to read 5, iclass 36, count 0 2006.253.07:46:19.99#ibcon#read 5, iclass 36, count 0 2006.253.07:46:19.99#ibcon#about to read 6, iclass 36, count 0 2006.253.07:46:19.99#ibcon#read 6, iclass 36, count 0 2006.253.07:46:19.99#ibcon#end of sib2, iclass 36, count 0 2006.253.07:46:19.99#ibcon#*mode == 0, iclass 36, count 0 2006.253.07:46:19.99#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.253.07:46:19.99#ibcon#[26=FRQ=07,832.99\r\n] 2006.253.07:46:19.99#ibcon#*before write, iclass 36, count 0 2006.253.07:46:19.99#ibcon#enter sib2, iclass 36, count 0 2006.253.07:46:19.99#ibcon#flushed, iclass 36, count 0 2006.253.07:46:19.99#ibcon#about to write, iclass 36, count 0 2006.253.07:46:19.99#ibcon#wrote, iclass 36, count 0 2006.253.07:46:19.99#ibcon#about to read 3, iclass 36, count 0 2006.253.07:46:20.03#ibcon#read 3, iclass 36, count 0 2006.253.07:46:20.03#ibcon#about to read 4, iclass 36, count 0 2006.253.07:46:20.03#ibcon#read 4, iclass 36, count 0 2006.253.07:46:20.03#ibcon#about to read 5, iclass 36, count 0 2006.253.07:46:20.03#ibcon#read 5, iclass 36, count 0 2006.253.07:46:20.03#ibcon#about to read 6, iclass 36, count 0 2006.253.07:46:20.03#ibcon#read 6, iclass 36, count 0 2006.253.07:46:20.03#ibcon#end of sib2, iclass 36, count 0 2006.253.07:46:20.03#ibcon#*after write, iclass 36, count 0 2006.253.07:46:20.03#ibcon#*before return 0, iclass 36, count 0 2006.253.07:46:20.03#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.253.07:46:20.03#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.253.07:46:20.03#ibcon#about to clear, iclass 36 cls_cnt 0 2006.253.07:46:20.03#ibcon#cleared, iclass 36 cls_cnt 0 2006.253.07:46:20.03$vc4f8/va=7,7 2006.253.07:46:20.04#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.253.07:46:20.04#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.253.07:46:20.04#ibcon#ireg 11 cls_cnt 2 2006.253.07:46:20.04#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.253.07:46:20.08#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.253.07:46:20.08#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.253.07:46:20.08#ibcon#enter wrdev, iclass 38, count 2 2006.253.07:46:20.08#ibcon#first serial, iclass 38, count 2 2006.253.07:46:20.08#ibcon#enter sib2, iclass 38, count 2 2006.253.07:46:20.08#ibcon#flushed, iclass 38, count 2 2006.253.07:46:20.08#ibcon#about to write, iclass 38, count 2 2006.253.07:46:20.08#ibcon#wrote, iclass 38, count 2 2006.253.07:46:20.08#ibcon#about to read 3, iclass 38, count 2 2006.253.07:46:20.10#ibcon#read 3, iclass 38, count 2 2006.253.07:46:20.10#ibcon#about to read 4, iclass 38, count 2 2006.253.07:46:20.10#ibcon#read 4, iclass 38, count 2 2006.253.07:46:20.10#ibcon#about to read 5, iclass 38, count 2 2006.253.07:46:20.10#ibcon#read 5, iclass 38, count 2 2006.253.07:46:20.10#ibcon#about to read 6, iclass 38, count 2 2006.253.07:46:20.10#ibcon#read 6, iclass 38, count 2 2006.253.07:46:20.10#ibcon#end of sib2, iclass 38, count 2 2006.253.07:46:20.10#ibcon#*mode == 0, iclass 38, count 2 2006.253.07:46:20.10#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.253.07:46:20.10#ibcon#[25=AT07-07\r\n] 2006.253.07:46:20.10#ibcon#*before write, iclass 38, count 2 2006.253.07:46:20.10#ibcon#enter sib2, iclass 38, count 2 2006.253.07:46:20.10#ibcon#flushed, iclass 38, count 2 2006.253.07:46:20.10#ibcon#about to write, iclass 38, count 2 2006.253.07:46:20.10#ibcon#wrote, iclass 38, count 2 2006.253.07:46:20.10#ibcon#about to read 3, iclass 38, count 2 2006.253.07:46:20.13#ibcon#read 3, iclass 38, count 2 2006.253.07:46:20.13#ibcon#about to read 4, iclass 38, count 2 2006.253.07:46:20.13#ibcon#read 4, iclass 38, count 2 2006.253.07:46:20.13#ibcon#about to read 5, iclass 38, count 2 2006.253.07:46:20.13#ibcon#read 5, iclass 38, count 2 2006.253.07:46:20.13#ibcon#about to read 6, iclass 38, count 2 2006.253.07:46:20.13#ibcon#read 6, iclass 38, count 2 2006.253.07:46:20.13#ibcon#end of sib2, iclass 38, count 2 2006.253.07:46:20.13#ibcon#*after write, iclass 38, count 2 2006.253.07:46:20.13#ibcon#*before return 0, iclass 38, count 2 2006.253.07:46:20.13#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.253.07:46:20.13#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.253.07:46:20.13#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.253.07:46:20.13#ibcon#ireg 7 cls_cnt 0 2006.253.07:46:20.13#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.253.07:46:20.25#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.253.07:46:20.25#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.253.07:46:20.25#ibcon#enter wrdev, iclass 38, count 0 2006.253.07:46:20.25#ibcon#first serial, iclass 38, count 0 2006.253.07:46:20.25#ibcon#enter sib2, iclass 38, count 0 2006.253.07:46:20.25#ibcon#flushed, iclass 38, count 0 2006.253.07:46:20.25#ibcon#about to write, iclass 38, count 0 2006.253.07:46:20.25#ibcon#wrote, iclass 38, count 0 2006.253.07:46:20.25#ibcon#about to read 3, iclass 38, count 0 2006.253.07:46:20.27#ibcon#read 3, iclass 38, count 0 2006.253.07:46:20.27#ibcon#about to read 4, iclass 38, count 0 2006.253.07:46:20.27#ibcon#read 4, iclass 38, count 0 2006.253.07:46:20.27#ibcon#about to read 5, iclass 38, count 0 2006.253.07:46:20.27#ibcon#read 5, iclass 38, count 0 2006.253.07:46:20.27#ibcon#about to read 6, iclass 38, count 0 2006.253.07:46:20.27#ibcon#read 6, iclass 38, count 0 2006.253.07:46:20.27#ibcon#end of sib2, iclass 38, count 0 2006.253.07:46:20.27#ibcon#*mode == 0, iclass 38, count 0 2006.253.07:46:20.27#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.253.07:46:20.27#ibcon#[25=USB\r\n] 2006.253.07:46:20.27#ibcon#*before write, iclass 38, count 0 2006.253.07:46:20.27#ibcon#enter sib2, iclass 38, count 0 2006.253.07:46:20.27#ibcon#flushed, iclass 38, count 0 2006.253.07:46:20.27#ibcon#about to write, iclass 38, count 0 2006.253.07:46:20.27#ibcon#wrote, iclass 38, count 0 2006.253.07:46:20.27#ibcon#about to read 3, iclass 38, count 0 2006.253.07:46:20.30#ibcon#read 3, iclass 38, count 0 2006.253.07:46:20.30#ibcon#about to read 4, iclass 38, count 0 2006.253.07:46:20.30#ibcon#read 4, iclass 38, count 0 2006.253.07:46:20.30#ibcon#about to read 5, iclass 38, count 0 2006.253.07:46:20.30#ibcon#read 5, iclass 38, count 0 2006.253.07:46:20.30#ibcon#about to read 6, iclass 38, count 0 2006.253.07:46:20.30#ibcon#read 6, iclass 38, count 0 2006.253.07:46:20.30#ibcon#end of sib2, iclass 38, count 0 2006.253.07:46:20.30#ibcon#*after write, iclass 38, count 0 2006.253.07:46:20.30#ibcon#*before return 0, iclass 38, count 0 2006.253.07:46:20.30#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.253.07:46:20.30#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.253.07:46:20.30#ibcon#about to clear, iclass 38 cls_cnt 0 2006.253.07:46:20.30#ibcon#cleared, iclass 38 cls_cnt 0 2006.253.07:46:20.30$vc4f8/valo=8,852.99 2006.253.07:46:20.31#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.253.07:46:20.31#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.253.07:46:20.31#ibcon#ireg 17 cls_cnt 0 2006.253.07:46:20.31#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.253.07:46:20.31#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.253.07:46:20.31#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.253.07:46:20.31#ibcon#enter wrdev, iclass 40, count 0 2006.253.07:46:20.31#ibcon#first serial, iclass 40, count 0 2006.253.07:46:20.31#ibcon#enter sib2, iclass 40, count 0 2006.253.07:46:20.31#ibcon#flushed, iclass 40, count 0 2006.253.07:46:20.31#ibcon#about to write, iclass 40, count 0 2006.253.07:46:20.31#ibcon#wrote, iclass 40, count 0 2006.253.07:46:20.31#ibcon#about to read 3, iclass 40, count 0 2006.253.07:46:20.32#ibcon#read 3, iclass 40, count 0 2006.253.07:46:20.32#ibcon#about to read 4, iclass 40, count 0 2006.253.07:46:20.32#ibcon#read 4, iclass 40, count 0 2006.253.07:46:20.32#ibcon#about to read 5, iclass 40, count 0 2006.253.07:46:20.32#ibcon#read 5, iclass 40, count 0 2006.253.07:46:20.32#ibcon#about to read 6, iclass 40, count 0 2006.253.07:46:20.32#ibcon#read 6, iclass 40, count 0 2006.253.07:46:20.32#ibcon#end of sib2, iclass 40, count 0 2006.253.07:46:20.32#ibcon#*mode == 0, iclass 40, count 0 2006.253.07:46:20.32#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.253.07:46:20.32#ibcon#[26=FRQ=08,852.99\r\n] 2006.253.07:46:20.32#ibcon#*before write, iclass 40, count 0 2006.253.07:46:20.32#ibcon#enter sib2, iclass 40, count 0 2006.253.07:46:20.32#ibcon#flushed, iclass 40, count 0 2006.253.07:46:20.32#ibcon#about to write, iclass 40, count 0 2006.253.07:46:20.32#ibcon#wrote, iclass 40, count 0 2006.253.07:46:20.32#ibcon#about to read 3, iclass 40, count 0 2006.253.07:46:20.36#ibcon#read 3, iclass 40, count 0 2006.253.07:46:20.36#ibcon#about to read 4, iclass 40, count 0 2006.253.07:46:20.36#ibcon#read 4, iclass 40, count 0 2006.253.07:46:20.36#ibcon#about to read 5, iclass 40, count 0 2006.253.07:46:20.36#ibcon#read 5, iclass 40, count 0 2006.253.07:46:20.36#ibcon#about to read 6, iclass 40, count 0 2006.253.07:46:20.36#ibcon#read 6, iclass 40, count 0 2006.253.07:46:20.36#ibcon#end of sib2, iclass 40, count 0 2006.253.07:46:20.36#ibcon#*after write, iclass 40, count 0 2006.253.07:46:20.36#ibcon#*before return 0, iclass 40, count 0 2006.253.07:46:20.36#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.253.07:46:20.36#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.253.07:46:20.36#ibcon#about to clear, iclass 40 cls_cnt 0 2006.253.07:46:20.36#ibcon#cleared, iclass 40 cls_cnt 0 2006.253.07:46:20.36$vc4f8/va=8,7 2006.253.07:46:20.37#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.253.07:46:20.37#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.253.07:46:20.37#ibcon#ireg 11 cls_cnt 2 2006.253.07:46:20.37#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.253.07:46:20.41#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.253.07:46:20.41#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.253.07:46:20.41#ibcon#enter wrdev, iclass 4, count 2 2006.253.07:46:20.41#ibcon#first serial, iclass 4, count 2 2006.253.07:46:20.41#ibcon#enter sib2, iclass 4, count 2 2006.253.07:46:20.41#ibcon#flushed, iclass 4, count 2 2006.253.07:46:20.41#ibcon#about to write, iclass 4, count 2 2006.253.07:46:20.41#ibcon#wrote, iclass 4, count 2 2006.253.07:46:20.41#ibcon#about to read 3, iclass 4, count 2 2006.253.07:46:20.43#ibcon#read 3, iclass 4, count 2 2006.253.07:46:20.43#ibcon#about to read 4, iclass 4, count 2 2006.253.07:46:20.43#ibcon#read 4, iclass 4, count 2 2006.253.07:46:20.43#ibcon#about to read 5, iclass 4, count 2 2006.253.07:46:20.43#ibcon#read 5, iclass 4, count 2 2006.253.07:46:20.43#ibcon#about to read 6, iclass 4, count 2 2006.253.07:46:20.43#ibcon#read 6, iclass 4, count 2 2006.253.07:46:20.43#ibcon#end of sib2, iclass 4, count 2 2006.253.07:46:20.43#ibcon#*mode == 0, iclass 4, count 2 2006.253.07:46:20.43#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.253.07:46:20.43#ibcon#[25=AT08-07\r\n] 2006.253.07:46:20.43#ibcon#*before write, iclass 4, count 2 2006.253.07:46:20.43#ibcon#enter sib2, iclass 4, count 2 2006.253.07:46:20.43#ibcon#flushed, iclass 4, count 2 2006.253.07:46:20.43#ibcon#about to write, iclass 4, count 2 2006.253.07:46:20.43#ibcon#wrote, iclass 4, count 2 2006.253.07:46:20.43#ibcon#about to read 3, iclass 4, count 2 2006.253.07:46:20.46#ibcon#read 3, iclass 4, count 2 2006.253.07:46:20.46#ibcon#about to read 4, iclass 4, count 2 2006.253.07:46:20.46#ibcon#read 4, iclass 4, count 2 2006.253.07:46:20.46#ibcon#about to read 5, iclass 4, count 2 2006.253.07:46:20.46#ibcon#read 5, iclass 4, count 2 2006.253.07:46:20.46#ibcon#about to read 6, iclass 4, count 2 2006.253.07:46:20.46#ibcon#read 6, iclass 4, count 2 2006.253.07:46:20.46#ibcon#end of sib2, iclass 4, count 2 2006.253.07:46:20.46#ibcon#*after write, iclass 4, count 2 2006.253.07:46:20.46#ibcon#*before return 0, iclass 4, count 2 2006.253.07:46:20.46#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.253.07:46:20.46#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.253.07:46:20.46#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.253.07:46:20.46#ibcon#ireg 7 cls_cnt 0 2006.253.07:46:20.46#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.253.07:46:20.58#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.253.07:46:20.58#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.253.07:46:20.58#ibcon#enter wrdev, iclass 4, count 0 2006.253.07:46:20.58#ibcon#first serial, iclass 4, count 0 2006.253.07:46:20.58#ibcon#enter sib2, iclass 4, count 0 2006.253.07:46:20.58#ibcon#flushed, iclass 4, count 0 2006.253.07:46:20.58#ibcon#about to write, iclass 4, count 0 2006.253.07:46:20.58#ibcon#wrote, iclass 4, count 0 2006.253.07:46:20.58#ibcon#about to read 3, iclass 4, count 0 2006.253.07:46:20.60#ibcon#read 3, iclass 4, count 0 2006.253.07:46:20.60#ibcon#about to read 4, iclass 4, count 0 2006.253.07:46:20.60#ibcon#read 4, iclass 4, count 0 2006.253.07:46:20.60#ibcon#about to read 5, iclass 4, count 0 2006.253.07:46:20.60#ibcon#read 5, iclass 4, count 0 2006.253.07:46:20.60#ibcon#about to read 6, iclass 4, count 0 2006.253.07:46:20.60#ibcon#read 6, iclass 4, count 0 2006.253.07:46:20.60#ibcon#end of sib2, iclass 4, count 0 2006.253.07:46:20.60#ibcon#*mode == 0, iclass 4, count 0 2006.253.07:46:20.60#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.253.07:46:20.60#ibcon#[25=USB\r\n] 2006.253.07:46:20.60#ibcon#*before write, iclass 4, count 0 2006.253.07:46:20.60#ibcon#enter sib2, iclass 4, count 0 2006.253.07:46:20.60#ibcon#flushed, iclass 4, count 0 2006.253.07:46:20.60#ibcon#about to write, iclass 4, count 0 2006.253.07:46:20.60#ibcon#wrote, iclass 4, count 0 2006.253.07:46:20.60#ibcon#about to read 3, iclass 4, count 0 2006.253.07:46:20.63#ibcon#read 3, iclass 4, count 0 2006.253.07:46:20.63#ibcon#about to read 4, iclass 4, count 0 2006.253.07:46:20.63#ibcon#read 4, iclass 4, count 0 2006.253.07:46:20.63#ibcon#about to read 5, iclass 4, count 0 2006.253.07:46:20.63#ibcon#read 5, iclass 4, count 0 2006.253.07:46:20.63#ibcon#about to read 6, iclass 4, count 0 2006.253.07:46:20.63#ibcon#read 6, iclass 4, count 0 2006.253.07:46:20.63#ibcon#end of sib2, iclass 4, count 0 2006.253.07:46:20.63#ibcon#*after write, iclass 4, count 0 2006.253.07:46:20.63#ibcon#*before return 0, iclass 4, count 0 2006.253.07:46:20.63#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.253.07:46:20.63#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.253.07:46:20.63#ibcon#about to clear, iclass 4 cls_cnt 0 2006.253.07:46:20.63#ibcon#cleared, iclass 4 cls_cnt 0 2006.253.07:46:20.64$vc4f8/vblo=1,632.99 2006.253.07:46:20.64#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.253.07:46:20.64#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.253.07:46:20.64#ibcon#ireg 17 cls_cnt 0 2006.253.07:46:20.64#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.253.07:46:20.64#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.253.07:46:20.64#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.253.07:46:20.64#ibcon#enter wrdev, iclass 6, count 0 2006.253.07:46:20.64#ibcon#first serial, iclass 6, count 0 2006.253.07:46:20.64#ibcon#enter sib2, iclass 6, count 0 2006.253.07:46:20.64#ibcon#flushed, iclass 6, count 0 2006.253.07:46:20.64#ibcon#about to write, iclass 6, count 0 2006.253.07:46:20.64#ibcon#wrote, iclass 6, count 0 2006.253.07:46:20.64#ibcon#about to read 3, iclass 6, count 0 2006.253.07:46:20.65#ibcon#read 3, iclass 6, count 0 2006.253.07:46:20.65#ibcon#about to read 4, iclass 6, count 0 2006.253.07:46:20.65#ibcon#read 4, iclass 6, count 0 2006.253.07:46:20.65#ibcon#about to read 5, iclass 6, count 0 2006.253.07:46:20.65#ibcon#read 5, iclass 6, count 0 2006.253.07:46:20.65#ibcon#about to read 6, iclass 6, count 0 2006.253.07:46:20.65#ibcon#read 6, iclass 6, count 0 2006.253.07:46:20.65#ibcon#end of sib2, iclass 6, count 0 2006.253.07:46:20.65#ibcon#*mode == 0, iclass 6, count 0 2006.253.07:46:20.65#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.253.07:46:20.65#ibcon#[28=FRQ=01,632.99\r\n] 2006.253.07:46:20.65#ibcon#*before write, iclass 6, count 0 2006.253.07:46:20.65#ibcon#enter sib2, iclass 6, count 0 2006.253.07:46:20.65#ibcon#flushed, iclass 6, count 0 2006.253.07:46:20.65#ibcon#about to write, iclass 6, count 0 2006.253.07:46:20.65#ibcon#wrote, iclass 6, count 0 2006.253.07:46:20.65#ibcon#about to read 3, iclass 6, count 0 2006.253.07:46:20.69#ibcon#read 3, iclass 6, count 0 2006.253.07:46:20.69#ibcon#about to read 4, iclass 6, count 0 2006.253.07:46:20.69#ibcon#read 4, iclass 6, count 0 2006.253.07:46:20.69#ibcon#about to read 5, iclass 6, count 0 2006.253.07:46:20.69#ibcon#read 5, iclass 6, count 0 2006.253.07:46:20.69#ibcon#about to read 6, iclass 6, count 0 2006.253.07:46:20.69#ibcon#read 6, iclass 6, count 0 2006.253.07:46:20.69#ibcon#end of sib2, iclass 6, count 0 2006.253.07:46:20.69#ibcon#*after write, iclass 6, count 0 2006.253.07:46:20.69#ibcon#*before return 0, iclass 6, count 0 2006.253.07:46:20.69#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.253.07:46:20.69#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.253.07:46:20.69#ibcon#about to clear, iclass 6 cls_cnt 0 2006.253.07:46:20.69#ibcon#cleared, iclass 6 cls_cnt 0 2006.253.07:46:20.69$vc4f8/vb=1,4 2006.253.07:46:20.70#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.253.07:46:20.70#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.253.07:46:20.70#ibcon#ireg 11 cls_cnt 2 2006.253.07:46:20.70#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.253.07:46:20.70#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.253.07:46:20.70#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.253.07:46:20.70#ibcon#enter wrdev, iclass 10, count 2 2006.253.07:46:20.70#ibcon#first serial, iclass 10, count 2 2006.253.07:46:20.70#ibcon#enter sib2, iclass 10, count 2 2006.253.07:46:20.70#ibcon#flushed, iclass 10, count 2 2006.253.07:46:20.70#ibcon#about to write, iclass 10, count 2 2006.253.07:46:20.70#ibcon#wrote, iclass 10, count 2 2006.253.07:46:20.70#ibcon#about to read 3, iclass 10, count 2 2006.253.07:46:20.71#ibcon#read 3, iclass 10, count 2 2006.253.07:46:20.71#ibcon#about to read 4, iclass 10, count 2 2006.253.07:46:20.71#ibcon#read 4, iclass 10, count 2 2006.253.07:46:20.71#ibcon#about to read 5, iclass 10, count 2 2006.253.07:46:20.71#ibcon#read 5, iclass 10, count 2 2006.253.07:46:20.71#ibcon#about to read 6, iclass 10, count 2 2006.253.07:46:20.71#ibcon#read 6, iclass 10, count 2 2006.253.07:46:20.71#ibcon#end of sib2, iclass 10, count 2 2006.253.07:46:20.71#ibcon#*mode == 0, iclass 10, count 2 2006.253.07:46:20.71#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.253.07:46:20.71#ibcon#[27=AT01-04\r\n] 2006.253.07:46:20.71#ibcon#*before write, iclass 10, count 2 2006.253.07:46:20.71#ibcon#enter sib2, iclass 10, count 2 2006.253.07:46:20.71#ibcon#flushed, iclass 10, count 2 2006.253.07:46:20.71#ibcon#about to write, iclass 10, count 2 2006.253.07:46:20.71#ibcon#wrote, iclass 10, count 2 2006.253.07:46:20.71#ibcon#about to read 3, iclass 10, count 2 2006.253.07:46:20.74#ibcon#read 3, iclass 10, count 2 2006.253.07:46:20.74#ibcon#about to read 4, iclass 10, count 2 2006.253.07:46:20.74#ibcon#read 4, iclass 10, count 2 2006.253.07:46:20.74#ibcon#about to read 5, iclass 10, count 2 2006.253.07:46:20.74#ibcon#read 5, iclass 10, count 2 2006.253.07:46:20.74#ibcon#about to read 6, iclass 10, count 2 2006.253.07:46:20.74#ibcon#read 6, iclass 10, count 2 2006.253.07:46:20.74#ibcon#end of sib2, iclass 10, count 2 2006.253.07:46:20.74#ibcon#*after write, iclass 10, count 2 2006.253.07:46:20.74#ibcon#*before return 0, iclass 10, count 2 2006.253.07:46:20.74#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.253.07:46:20.74#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.253.07:46:20.74#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.253.07:46:20.74#ibcon#ireg 7 cls_cnt 0 2006.253.07:46:20.74#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.253.07:46:20.86#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.253.07:46:20.86#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.253.07:46:20.86#ibcon#enter wrdev, iclass 10, count 0 2006.253.07:46:20.86#ibcon#first serial, iclass 10, count 0 2006.253.07:46:20.86#ibcon#enter sib2, iclass 10, count 0 2006.253.07:46:20.86#ibcon#flushed, iclass 10, count 0 2006.253.07:46:20.86#ibcon#about to write, iclass 10, count 0 2006.253.07:46:20.86#ibcon#wrote, iclass 10, count 0 2006.253.07:46:20.86#ibcon#about to read 3, iclass 10, count 0 2006.253.07:46:20.88#ibcon#read 3, iclass 10, count 0 2006.253.07:46:20.88#ibcon#about to read 4, iclass 10, count 0 2006.253.07:46:20.88#ibcon#read 4, iclass 10, count 0 2006.253.07:46:20.88#ibcon#about to read 5, iclass 10, count 0 2006.253.07:46:20.88#ibcon#read 5, iclass 10, count 0 2006.253.07:46:20.88#ibcon#about to read 6, iclass 10, count 0 2006.253.07:46:20.88#ibcon#read 6, iclass 10, count 0 2006.253.07:46:20.88#ibcon#end of sib2, iclass 10, count 0 2006.253.07:46:20.88#ibcon#*mode == 0, iclass 10, count 0 2006.253.07:46:20.88#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.253.07:46:20.88#ibcon#[27=USB\r\n] 2006.253.07:46:20.88#ibcon#*before write, iclass 10, count 0 2006.253.07:46:20.88#ibcon#enter sib2, iclass 10, count 0 2006.253.07:46:20.88#ibcon#flushed, iclass 10, count 0 2006.253.07:46:20.88#ibcon#about to write, iclass 10, count 0 2006.253.07:46:20.88#ibcon#wrote, iclass 10, count 0 2006.253.07:46:20.88#ibcon#about to read 3, iclass 10, count 0 2006.253.07:46:20.91#ibcon#read 3, iclass 10, count 0 2006.253.07:46:20.91#ibcon#about to read 4, iclass 10, count 0 2006.253.07:46:20.91#ibcon#read 4, iclass 10, count 0 2006.253.07:46:20.91#ibcon#about to read 5, iclass 10, count 0 2006.253.07:46:20.91#ibcon#read 5, iclass 10, count 0 2006.253.07:46:20.91#ibcon#about to read 6, iclass 10, count 0 2006.253.07:46:20.91#ibcon#read 6, iclass 10, count 0 2006.253.07:46:20.91#ibcon#end of sib2, iclass 10, count 0 2006.253.07:46:20.91#ibcon#*after write, iclass 10, count 0 2006.253.07:46:20.91#ibcon#*before return 0, iclass 10, count 0 2006.253.07:46:20.91#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.253.07:46:20.91#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.253.07:46:20.91#ibcon#about to clear, iclass 10 cls_cnt 0 2006.253.07:46:20.91#ibcon#cleared, iclass 10 cls_cnt 0 2006.253.07:46:20.91$vc4f8/vblo=2,640.99 2006.253.07:46:20.92#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.253.07:46:20.92#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.253.07:46:20.92#ibcon#ireg 17 cls_cnt 0 2006.253.07:46:20.92#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.253.07:46:20.92#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.253.07:46:20.92#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.253.07:46:20.92#ibcon#enter wrdev, iclass 12, count 0 2006.253.07:46:20.92#ibcon#first serial, iclass 12, count 0 2006.253.07:46:20.92#ibcon#enter sib2, iclass 12, count 0 2006.253.07:46:20.92#ibcon#flushed, iclass 12, count 0 2006.253.07:46:20.92#ibcon#about to write, iclass 12, count 0 2006.253.07:46:20.92#ibcon#wrote, iclass 12, count 0 2006.253.07:46:20.92#ibcon#about to read 3, iclass 12, count 0 2006.253.07:46:20.93#ibcon#read 3, iclass 12, count 0 2006.253.07:46:20.93#ibcon#about to read 4, iclass 12, count 0 2006.253.07:46:20.93#ibcon#read 4, iclass 12, count 0 2006.253.07:46:20.93#ibcon#about to read 5, iclass 12, count 0 2006.253.07:46:20.93#ibcon#read 5, iclass 12, count 0 2006.253.07:46:20.93#ibcon#about to read 6, iclass 12, count 0 2006.253.07:46:20.93#ibcon#read 6, iclass 12, count 0 2006.253.07:46:20.93#ibcon#end of sib2, iclass 12, count 0 2006.253.07:46:20.93#ibcon#*mode == 0, iclass 12, count 0 2006.253.07:46:20.93#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.253.07:46:20.93#ibcon#[28=FRQ=02,640.99\r\n] 2006.253.07:46:20.93#ibcon#*before write, iclass 12, count 0 2006.253.07:46:20.93#ibcon#enter sib2, iclass 12, count 0 2006.253.07:46:20.93#ibcon#flushed, iclass 12, count 0 2006.253.07:46:20.93#ibcon#about to write, iclass 12, count 0 2006.253.07:46:20.93#ibcon#wrote, iclass 12, count 0 2006.253.07:46:20.93#ibcon#about to read 3, iclass 12, count 0 2006.253.07:46:20.97#ibcon#read 3, iclass 12, count 0 2006.253.07:46:20.97#ibcon#about to read 4, iclass 12, count 0 2006.253.07:46:20.97#ibcon#read 4, iclass 12, count 0 2006.253.07:46:20.97#ibcon#about to read 5, iclass 12, count 0 2006.253.07:46:20.97#ibcon#read 5, iclass 12, count 0 2006.253.07:46:20.97#ibcon#about to read 6, iclass 12, count 0 2006.253.07:46:20.97#ibcon#read 6, iclass 12, count 0 2006.253.07:46:20.97#ibcon#end of sib2, iclass 12, count 0 2006.253.07:46:20.97#ibcon#*after write, iclass 12, count 0 2006.253.07:46:20.97#ibcon#*before return 0, iclass 12, count 0 2006.253.07:46:20.97#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.253.07:46:20.97#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.253.07:46:20.97#ibcon#about to clear, iclass 12 cls_cnt 0 2006.253.07:46:20.97#ibcon#cleared, iclass 12 cls_cnt 0 2006.253.07:46:20.97$vc4f8/vb=2,5 2006.253.07:46:20.98#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.253.07:46:20.98#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.253.07:46:20.98#ibcon#ireg 11 cls_cnt 2 2006.253.07:46:20.98#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.253.07:46:21.02#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.253.07:46:21.02#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.253.07:46:21.02#ibcon#enter wrdev, iclass 14, count 2 2006.253.07:46:21.02#ibcon#first serial, iclass 14, count 2 2006.253.07:46:21.02#ibcon#enter sib2, iclass 14, count 2 2006.253.07:46:21.02#ibcon#flushed, iclass 14, count 2 2006.253.07:46:21.02#ibcon#about to write, iclass 14, count 2 2006.253.07:46:21.02#ibcon#wrote, iclass 14, count 2 2006.253.07:46:21.02#ibcon#about to read 3, iclass 14, count 2 2006.253.07:46:21.04#ibcon#read 3, iclass 14, count 2 2006.253.07:46:21.04#ibcon#about to read 4, iclass 14, count 2 2006.253.07:46:21.04#ibcon#read 4, iclass 14, count 2 2006.253.07:46:21.04#ibcon#about to read 5, iclass 14, count 2 2006.253.07:46:21.04#ibcon#read 5, iclass 14, count 2 2006.253.07:46:21.04#ibcon#about to read 6, iclass 14, count 2 2006.253.07:46:21.04#ibcon#read 6, iclass 14, count 2 2006.253.07:46:21.04#ibcon#end of sib2, iclass 14, count 2 2006.253.07:46:21.04#ibcon#*mode == 0, iclass 14, count 2 2006.253.07:46:21.04#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.253.07:46:21.04#ibcon#[27=AT02-05\r\n] 2006.253.07:46:21.04#ibcon#*before write, iclass 14, count 2 2006.253.07:46:21.04#ibcon#enter sib2, iclass 14, count 2 2006.253.07:46:21.04#ibcon#flushed, iclass 14, count 2 2006.253.07:46:21.04#ibcon#about to write, iclass 14, count 2 2006.253.07:46:21.04#ibcon#wrote, iclass 14, count 2 2006.253.07:46:21.04#ibcon#about to read 3, iclass 14, count 2 2006.253.07:46:21.07#ibcon#read 3, iclass 14, count 2 2006.253.07:46:21.07#ibcon#about to read 4, iclass 14, count 2 2006.253.07:46:21.07#ibcon#read 4, iclass 14, count 2 2006.253.07:46:21.07#ibcon#about to read 5, iclass 14, count 2 2006.253.07:46:21.07#ibcon#read 5, iclass 14, count 2 2006.253.07:46:21.07#ibcon#about to read 6, iclass 14, count 2 2006.253.07:46:21.07#ibcon#read 6, iclass 14, count 2 2006.253.07:46:21.07#ibcon#end of sib2, iclass 14, count 2 2006.253.07:46:21.07#ibcon#*after write, iclass 14, count 2 2006.253.07:46:21.07#ibcon#*before return 0, iclass 14, count 2 2006.253.07:46:21.07#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.253.07:46:21.07#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.253.07:46:21.07#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.253.07:46:21.07#ibcon#ireg 7 cls_cnt 0 2006.253.07:46:21.07#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.253.07:46:21.19#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.253.07:46:21.19#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.253.07:46:21.19#ibcon#enter wrdev, iclass 14, count 0 2006.253.07:46:21.19#ibcon#first serial, iclass 14, count 0 2006.253.07:46:21.19#ibcon#enter sib2, iclass 14, count 0 2006.253.07:46:21.19#ibcon#flushed, iclass 14, count 0 2006.253.07:46:21.19#ibcon#about to write, iclass 14, count 0 2006.253.07:46:21.19#ibcon#wrote, iclass 14, count 0 2006.253.07:46:21.19#ibcon#about to read 3, iclass 14, count 0 2006.253.07:46:21.21#ibcon#read 3, iclass 14, count 0 2006.253.07:46:21.21#ibcon#about to read 4, iclass 14, count 0 2006.253.07:46:21.21#ibcon#read 4, iclass 14, count 0 2006.253.07:46:21.21#ibcon#about to read 5, iclass 14, count 0 2006.253.07:46:21.21#ibcon#read 5, iclass 14, count 0 2006.253.07:46:21.21#ibcon#about to read 6, iclass 14, count 0 2006.253.07:46:21.21#ibcon#read 6, iclass 14, count 0 2006.253.07:46:21.21#ibcon#end of sib2, iclass 14, count 0 2006.253.07:46:21.21#ibcon#*mode == 0, iclass 14, count 0 2006.253.07:46:21.21#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.253.07:46:21.21#ibcon#[27=USB\r\n] 2006.253.07:46:21.21#ibcon#*before write, iclass 14, count 0 2006.253.07:46:21.21#ibcon#enter sib2, iclass 14, count 0 2006.253.07:46:21.21#ibcon#flushed, iclass 14, count 0 2006.253.07:46:21.21#ibcon#about to write, iclass 14, count 0 2006.253.07:46:21.21#ibcon#wrote, iclass 14, count 0 2006.253.07:46:21.21#ibcon#about to read 3, iclass 14, count 0 2006.253.07:46:21.24#ibcon#read 3, iclass 14, count 0 2006.253.07:46:21.24#ibcon#about to read 4, iclass 14, count 0 2006.253.07:46:21.24#ibcon#read 4, iclass 14, count 0 2006.253.07:46:21.24#ibcon#about to read 5, iclass 14, count 0 2006.253.07:46:21.24#ibcon#read 5, iclass 14, count 0 2006.253.07:46:21.24#ibcon#about to read 6, iclass 14, count 0 2006.253.07:46:21.24#ibcon#read 6, iclass 14, count 0 2006.253.07:46:21.24#ibcon#end of sib2, iclass 14, count 0 2006.253.07:46:21.24#ibcon#*after write, iclass 14, count 0 2006.253.07:46:21.24#ibcon#*before return 0, iclass 14, count 0 2006.253.07:46:21.24#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.253.07:46:21.25#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.253.07:46:21.25#ibcon#about to clear, iclass 14 cls_cnt 0 2006.253.07:46:21.25#ibcon#cleared, iclass 14 cls_cnt 0 2006.253.07:46:21.25$vc4f8/vblo=3,656.99 2006.253.07:46:21.25#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.253.07:46:21.25#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.253.07:46:21.25#ibcon#ireg 17 cls_cnt 0 2006.253.07:46:21.25#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.253.07:46:21.25#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.253.07:46:21.25#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.253.07:46:21.25#ibcon#enter wrdev, iclass 16, count 0 2006.253.07:46:21.25#ibcon#first serial, iclass 16, count 0 2006.253.07:46:21.25#ibcon#enter sib2, iclass 16, count 0 2006.253.07:46:21.25#ibcon#flushed, iclass 16, count 0 2006.253.07:46:21.25#ibcon#about to write, iclass 16, count 0 2006.253.07:46:21.25#ibcon#wrote, iclass 16, count 0 2006.253.07:46:21.25#ibcon#about to read 3, iclass 16, count 0 2006.253.07:46:21.26#ibcon#read 3, iclass 16, count 0 2006.253.07:46:21.26#ibcon#about to read 4, iclass 16, count 0 2006.253.07:46:21.26#ibcon#read 4, iclass 16, count 0 2006.253.07:46:21.26#ibcon#about to read 5, iclass 16, count 0 2006.253.07:46:21.26#ibcon#read 5, iclass 16, count 0 2006.253.07:46:21.26#ibcon#about to read 6, iclass 16, count 0 2006.253.07:46:21.26#ibcon#read 6, iclass 16, count 0 2006.253.07:46:21.26#ibcon#end of sib2, iclass 16, count 0 2006.253.07:46:21.26#ibcon#*mode == 0, iclass 16, count 0 2006.253.07:46:21.26#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.253.07:46:21.26#ibcon#[28=FRQ=03,656.99\r\n] 2006.253.07:46:21.26#ibcon#*before write, iclass 16, count 0 2006.253.07:46:21.26#ibcon#enter sib2, iclass 16, count 0 2006.253.07:46:21.26#ibcon#flushed, iclass 16, count 0 2006.253.07:46:21.26#ibcon#about to write, iclass 16, count 0 2006.253.07:46:21.26#ibcon#wrote, iclass 16, count 0 2006.253.07:46:21.26#ibcon#about to read 3, iclass 16, count 0 2006.253.07:46:21.30#ibcon#read 3, iclass 16, count 0 2006.253.07:46:21.30#ibcon#about to read 4, iclass 16, count 0 2006.253.07:46:21.30#ibcon#read 4, iclass 16, count 0 2006.253.07:46:21.30#ibcon#about to read 5, iclass 16, count 0 2006.253.07:46:21.30#ibcon#read 5, iclass 16, count 0 2006.253.07:46:21.30#ibcon#about to read 6, iclass 16, count 0 2006.253.07:46:21.30#ibcon#read 6, iclass 16, count 0 2006.253.07:46:21.30#ibcon#end of sib2, iclass 16, count 0 2006.253.07:46:21.30#ibcon#*after write, iclass 16, count 0 2006.253.07:46:21.30#ibcon#*before return 0, iclass 16, count 0 2006.253.07:46:21.30#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.253.07:46:21.30#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.253.07:46:21.30#ibcon#about to clear, iclass 16 cls_cnt 0 2006.253.07:46:21.30#ibcon#cleared, iclass 16 cls_cnt 0 2006.253.07:46:21.30$vc4f8/vb=3,4 2006.253.07:46:21.31#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.253.07:46:21.31#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.253.07:46:21.31#ibcon#ireg 11 cls_cnt 2 2006.253.07:46:21.31#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.253.07:46:21.36#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.253.07:46:21.36#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.253.07:46:21.36#ibcon#enter wrdev, iclass 18, count 2 2006.253.07:46:21.36#ibcon#first serial, iclass 18, count 2 2006.253.07:46:21.36#ibcon#enter sib2, iclass 18, count 2 2006.253.07:46:21.36#ibcon#flushed, iclass 18, count 2 2006.253.07:46:21.36#ibcon#about to write, iclass 18, count 2 2006.253.07:46:21.36#ibcon#wrote, iclass 18, count 2 2006.253.07:46:21.36#ibcon#about to read 3, iclass 18, count 2 2006.253.07:46:21.38#ibcon#read 3, iclass 18, count 2 2006.253.07:46:21.38#ibcon#about to read 4, iclass 18, count 2 2006.253.07:46:21.38#ibcon#read 4, iclass 18, count 2 2006.253.07:46:21.38#ibcon#about to read 5, iclass 18, count 2 2006.253.07:46:21.38#ibcon#read 5, iclass 18, count 2 2006.253.07:46:21.38#ibcon#about to read 6, iclass 18, count 2 2006.253.07:46:21.38#ibcon#read 6, iclass 18, count 2 2006.253.07:46:21.38#ibcon#end of sib2, iclass 18, count 2 2006.253.07:46:21.38#ibcon#*mode == 0, iclass 18, count 2 2006.253.07:46:21.38#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.253.07:46:21.38#ibcon#[27=AT03-04\r\n] 2006.253.07:46:21.38#ibcon#*before write, iclass 18, count 2 2006.253.07:46:21.38#ibcon#enter sib2, iclass 18, count 2 2006.253.07:46:21.38#ibcon#flushed, iclass 18, count 2 2006.253.07:46:21.38#ibcon#about to write, iclass 18, count 2 2006.253.07:46:21.38#ibcon#wrote, iclass 18, count 2 2006.253.07:46:21.38#ibcon#about to read 3, iclass 18, count 2 2006.253.07:46:21.41#ibcon#read 3, iclass 18, count 2 2006.253.07:46:21.41#ibcon#about to read 4, iclass 18, count 2 2006.253.07:46:21.41#ibcon#read 4, iclass 18, count 2 2006.253.07:46:21.41#ibcon#about to read 5, iclass 18, count 2 2006.253.07:46:21.41#ibcon#read 5, iclass 18, count 2 2006.253.07:46:21.41#ibcon#about to read 6, iclass 18, count 2 2006.253.07:46:21.41#ibcon#read 6, iclass 18, count 2 2006.253.07:46:21.41#ibcon#end of sib2, iclass 18, count 2 2006.253.07:46:21.41#ibcon#*after write, iclass 18, count 2 2006.253.07:46:21.41#ibcon#*before return 0, iclass 18, count 2 2006.253.07:46:21.41#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.253.07:46:21.41#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.253.07:46:21.41#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.253.07:46:21.41#ibcon#ireg 7 cls_cnt 0 2006.253.07:46:21.41#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.253.07:46:21.53#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.253.07:46:21.53#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.253.07:46:21.53#ibcon#enter wrdev, iclass 18, count 0 2006.253.07:46:21.53#ibcon#first serial, iclass 18, count 0 2006.253.07:46:21.53#ibcon#enter sib2, iclass 18, count 0 2006.253.07:46:21.53#ibcon#flushed, iclass 18, count 0 2006.253.07:46:21.53#ibcon#about to write, iclass 18, count 0 2006.253.07:46:21.53#ibcon#wrote, iclass 18, count 0 2006.253.07:46:21.53#ibcon#about to read 3, iclass 18, count 0 2006.253.07:46:21.55#ibcon#read 3, iclass 18, count 0 2006.253.07:46:21.55#ibcon#about to read 4, iclass 18, count 0 2006.253.07:46:21.55#ibcon#read 4, iclass 18, count 0 2006.253.07:46:21.55#ibcon#about to read 5, iclass 18, count 0 2006.253.07:46:21.55#ibcon#read 5, iclass 18, count 0 2006.253.07:46:21.55#ibcon#about to read 6, iclass 18, count 0 2006.253.07:46:21.55#ibcon#read 6, iclass 18, count 0 2006.253.07:46:21.55#ibcon#end of sib2, iclass 18, count 0 2006.253.07:46:21.55#ibcon#*mode == 0, iclass 18, count 0 2006.253.07:46:21.55#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.253.07:46:21.55#ibcon#[27=USB\r\n] 2006.253.07:46:21.55#ibcon#*before write, iclass 18, count 0 2006.253.07:46:21.55#ibcon#enter sib2, iclass 18, count 0 2006.253.07:46:21.55#ibcon#flushed, iclass 18, count 0 2006.253.07:46:21.55#ibcon#about to write, iclass 18, count 0 2006.253.07:46:21.55#ibcon#wrote, iclass 18, count 0 2006.253.07:46:21.55#ibcon#about to read 3, iclass 18, count 0 2006.253.07:46:21.58#ibcon#read 3, iclass 18, count 0 2006.253.07:46:21.58#ibcon#about to read 4, iclass 18, count 0 2006.253.07:46:21.58#ibcon#read 4, iclass 18, count 0 2006.253.07:46:21.58#ibcon#about to read 5, iclass 18, count 0 2006.253.07:46:21.58#ibcon#read 5, iclass 18, count 0 2006.253.07:46:21.58#ibcon#about to read 6, iclass 18, count 0 2006.253.07:46:21.58#ibcon#read 6, iclass 18, count 0 2006.253.07:46:21.58#ibcon#end of sib2, iclass 18, count 0 2006.253.07:46:21.58#ibcon#*after write, iclass 18, count 0 2006.253.07:46:21.58#ibcon#*before return 0, iclass 18, count 0 2006.253.07:46:21.58#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.253.07:46:21.58#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.253.07:46:21.58#ibcon#about to clear, iclass 18 cls_cnt 0 2006.253.07:46:21.58#ibcon#cleared, iclass 18 cls_cnt 0 2006.253.07:46:21.58$vc4f8/vblo=4,712.99 2006.253.07:46:21.59#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.253.07:46:21.59#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.253.07:46:21.59#ibcon#ireg 17 cls_cnt 0 2006.253.07:46:21.59#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.253.07:46:21.59#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.253.07:46:21.59#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.253.07:46:21.59#ibcon#enter wrdev, iclass 20, count 0 2006.253.07:46:21.59#ibcon#first serial, iclass 20, count 0 2006.253.07:46:21.59#ibcon#enter sib2, iclass 20, count 0 2006.253.07:46:21.59#ibcon#flushed, iclass 20, count 0 2006.253.07:46:21.59#ibcon#about to write, iclass 20, count 0 2006.253.07:46:21.59#ibcon#wrote, iclass 20, count 0 2006.253.07:46:21.59#ibcon#about to read 3, iclass 20, count 0 2006.253.07:46:21.60#ibcon#read 3, iclass 20, count 0 2006.253.07:46:21.60#ibcon#about to read 4, iclass 20, count 0 2006.253.07:46:21.60#ibcon#read 4, iclass 20, count 0 2006.253.07:46:21.60#ibcon#about to read 5, iclass 20, count 0 2006.253.07:46:21.60#ibcon#read 5, iclass 20, count 0 2006.253.07:46:21.60#ibcon#about to read 6, iclass 20, count 0 2006.253.07:46:21.60#ibcon#read 6, iclass 20, count 0 2006.253.07:46:21.60#ibcon#end of sib2, iclass 20, count 0 2006.253.07:46:21.60#ibcon#*mode == 0, iclass 20, count 0 2006.253.07:46:21.60#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.253.07:46:21.60#ibcon#[28=FRQ=04,712.99\r\n] 2006.253.07:46:21.60#ibcon#*before write, iclass 20, count 0 2006.253.07:46:21.60#ibcon#enter sib2, iclass 20, count 0 2006.253.07:46:21.60#ibcon#flushed, iclass 20, count 0 2006.253.07:46:21.60#ibcon#about to write, iclass 20, count 0 2006.253.07:46:21.60#ibcon#wrote, iclass 20, count 0 2006.253.07:46:21.60#ibcon#about to read 3, iclass 20, count 0 2006.253.07:46:21.64#ibcon#read 3, iclass 20, count 0 2006.253.07:46:21.64#ibcon#about to read 4, iclass 20, count 0 2006.253.07:46:21.64#ibcon#read 4, iclass 20, count 0 2006.253.07:46:21.64#ibcon#about to read 5, iclass 20, count 0 2006.253.07:46:21.64#ibcon#read 5, iclass 20, count 0 2006.253.07:46:21.64#ibcon#about to read 6, iclass 20, count 0 2006.253.07:46:21.64#ibcon#read 6, iclass 20, count 0 2006.253.07:46:21.64#ibcon#end of sib2, iclass 20, count 0 2006.253.07:46:21.64#ibcon#*after write, iclass 20, count 0 2006.253.07:46:21.64#ibcon#*before return 0, iclass 20, count 0 2006.253.07:46:21.64#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.253.07:46:21.64#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.253.07:46:21.64#ibcon#about to clear, iclass 20 cls_cnt 0 2006.253.07:46:21.64#ibcon#cleared, iclass 20 cls_cnt 0 2006.253.07:46:21.64$vc4f8/vb=4,4 2006.253.07:46:21.65#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.253.07:46:21.65#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.253.07:46:21.65#ibcon#ireg 11 cls_cnt 2 2006.253.07:46:21.65#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.253.07:46:21.69#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.253.07:46:21.69#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.253.07:46:21.69#ibcon#enter wrdev, iclass 22, count 2 2006.253.07:46:21.69#ibcon#first serial, iclass 22, count 2 2006.253.07:46:21.69#ibcon#enter sib2, iclass 22, count 2 2006.253.07:46:21.69#ibcon#flushed, iclass 22, count 2 2006.253.07:46:21.69#ibcon#about to write, iclass 22, count 2 2006.253.07:46:21.69#ibcon#wrote, iclass 22, count 2 2006.253.07:46:21.69#ibcon#about to read 3, iclass 22, count 2 2006.253.07:46:21.71#ibcon#read 3, iclass 22, count 2 2006.253.07:46:21.71#ibcon#about to read 4, iclass 22, count 2 2006.253.07:46:21.71#ibcon#read 4, iclass 22, count 2 2006.253.07:46:21.71#ibcon#about to read 5, iclass 22, count 2 2006.253.07:46:21.71#ibcon#read 5, iclass 22, count 2 2006.253.07:46:21.71#ibcon#about to read 6, iclass 22, count 2 2006.253.07:46:21.71#ibcon#read 6, iclass 22, count 2 2006.253.07:46:21.71#ibcon#end of sib2, iclass 22, count 2 2006.253.07:46:21.71#ibcon#*mode == 0, iclass 22, count 2 2006.253.07:46:21.71#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.253.07:46:21.71#ibcon#[27=AT04-04\r\n] 2006.253.07:46:21.71#ibcon#*before write, iclass 22, count 2 2006.253.07:46:21.71#ibcon#enter sib2, iclass 22, count 2 2006.253.07:46:21.71#ibcon#flushed, iclass 22, count 2 2006.253.07:46:21.71#ibcon#about to write, iclass 22, count 2 2006.253.07:46:21.71#ibcon#wrote, iclass 22, count 2 2006.253.07:46:21.71#ibcon#about to read 3, iclass 22, count 2 2006.253.07:46:21.74#ibcon#read 3, iclass 22, count 2 2006.253.07:46:21.74#ibcon#about to read 4, iclass 22, count 2 2006.253.07:46:21.74#ibcon#read 4, iclass 22, count 2 2006.253.07:46:21.74#ibcon#about to read 5, iclass 22, count 2 2006.253.07:46:21.74#ibcon#read 5, iclass 22, count 2 2006.253.07:46:21.74#ibcon#about to read 6, iclass 22, count 2 2006.253.07:46:21.74#ibcon#read 6, iclass 22, count 2 2006.253.07:46:21.74#ibcon#end of sib2, iclass 22, count 2 2006.253.07:46:21.74#ibcon#*after write, iclass 22, count 2 2006.253.07:46:21.74#ibcon#*before return 0, iclass 22, count 2 2006.253.07:46:21.74#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.253.07:46:21.74#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.253.07:46:21.74#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.253.07:46:21.74#ibcon#ireg 7 cls_cnt 0 2006.253.07:46:21.74#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.253.07:46:21.86#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.253.07:46:21.86#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.253.07:46:21.86#ibcon#enter wrdev, iclass 22, count 0 2006.253.07:46:21.86#ibcon#first serial, iclass 22, count 0 2006.253.07:46:21.86#ibcon#enter sib2, iclass 22, count 0 2006.253.07:46:21.86#ibcon#flushed, iclass 22, count 0 2006.253.07:46:21.86#ibcon#about to write, iclass 22, count 0 2006.253.07:46:21.86#ibcon#wrote, iclass 22, count 0 2006.253.07:46:21.86#ibcon#about to read 3, iclass 22, count 0 2006.253.07:46:21.88#ibcon#read 3, iclass 22, count 0 2006.253.07:46:21.88#ibcon#about to read 4, iclass 22, count 0 2006.253.07:46:21.88#ibcon#read 4, iclass 22, count 0 2006.253.07:46:21.88#ibcon#about to read 5, iclass 22, count 0 2006.253.07:46:21.88#ibcon#read 5, iclass 22, count 0 2006.253.07:46:21.88#ibcon#about to read 6, iclass 22, count 0 2006.253.07:46:21.88#ibcon#read 6, iclass 22, count 0 2006.253.07:46:21.88#ibcon#end of sib2, iclass 22, count 0 2006.253.07:46:21.88#ibcon#*mode == 0, iclass 22, count 0 2006.253.07:46:21.88#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.253.07:46:21.88#ibcon#[27=USB\r\n] 2006.253.07:46:21.88#ibcon#*before write, iclass 22, count 0 2006.253.07:46:21.88#ibcon#enter sib2, iclass 22, count 0 2006.253.07:46:21.88#ibcon#flushed, iclass 22, count 0 2006.253.07:46:21.88#ibcon#about to write, iclass 22, count 0 2006.253.07:46:21.88#ibcon#wrote, iclass 22, count 0 2006.253.07:46:21.88#ibcon#about to read 3, iclass 22, count 0 2006.253.07:46:21.91#ibcon#read 3, iclass 22, count 0 2006.253.07:46:21.91#ibcon#about to read 4, iclass 22, count 0 2006.253.07:46:21.91#ibcon#read 4, iclass 22, count 0 2006.253.07:46:21.91#ibcon#about to read 5, iclass 22, count 0 2006.253.07:46:21.91#ibcon#read 5, iclass 22, count 0 2006.253.07:46:21.91#ibcon#about to read 6, iclass 22, count 0 2006.253.07:46:21.91#ibcon#read 6, iclass 22, count 0 2006.253.07:46:21.91#ibcon#end of sib2, iclass 22, count 0 2006.253.07:46:21.91#ibcon#*after write, iclass 22, count 0 2006.253.07:46:21.91#ibcon#*before return 0, iclass 22, count 0 2006.253.07:46:21.91#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.253.07:46:21.91#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.253.07:46:21.91#ibcon#about to clear, iclass 22 cls_cnt 0 2006.253.07:46:21.91#ibcon#cleared, iclass 22 cls_cnt 0 2006.253.07:46:21.91$vc4f8/vblo=5,744.99 2006.253.07:46:21.92#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.253.07:46:21.92#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.253.07:46:21.92#ibcon#ireg 17 cls_cnt 0 2006.253.07:46:21.92#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.253.07:46:21.92#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.253.07:46:21.92#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.253.07:46:21.92#ibcon#enter wrdev, iclass 24, count 0 2006.253.07:46:21.92#ibcon#first serial, iclass 24, count 0 2006.253.07:46:21.92#ibcon#enter sib2, iclass 24, count 0 2006.253.07:46:21.92#ibcon#flushed, iclass 24, count 0 2006.253.07:46:21.92#ibcon#about to write, iclass 24, count 0 2006.253.07:46:21.92#ibcon#wrote, iclass 24, count 0 2006.253.07:46:21.92#ibcon#about to read 3, iclass 24, count 0 2006.253.07:46:21.93#ibcon#read 3, iclass 24, count 0 2006.253.07:46:21.93#ibcon#about to read 4, iclass 24, count 0 2006.253.07:46:21.93#ibcon#read 4, iclass 24, count 0 2006.253.07:46:21.93#ibcon#about to read 5, iclass 24, count 0 2006.253.07:46:21.93#ibcon#read 5, iclass 24, count 0 2006.253.07:46:21.93#ibcon#about to read 6, iclass 24, count 0 2006.253.07:46:21.93#ibcon#read 6, iclass 24, count 0 2006.253.07:46:21.93#ibcon#end of sib2, iclass 24, count 0 2006.253.07:46:21.93#ibcon#*mode == 0, iclass 24, count 0 2006.253.07:46:21.93#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.253.07:46:21.93#ibcon#[28=FRQ=05,744.99\r\n] 2006.253.07:46:21.93#ibcon#*before write, iclass 24, count 0 2006.253.07:46:21.93#ibcon#enter sib2, iclass 24, count 0 2006.253.07:46:21.93#ibcon#flushed, iclass 24, count 0 2006.253.07:46:21.93#ibcon#about to write, iclass 24, count 0 2006.253.07:46:21.93#ibcon#wrote, iclass 24, count 0 2006.253.07:46:21.93#ibcon#about to read 3, iclass 24, count 0 2006.253.07:46:21.97#ibcon#read 3, iclass 24, count 0 2006.253.07:46:21.97#ibcon#about to read 4, iclass 24, count 0 2006.253.07:46:21.97#ibcon#read 4, iclass 24, count 0 2006.253.07:46:21.97#ibcon#about to read 5, iclass 24, count 0 2006.253.07:46:21.97#ibcon#read 5, iclass 24, count 0 2006.253.07:46:21.97#ibcon#about to read 6, iclass 24, count 0 2006.253.07:46:21.97#ibcon#read 6, iclass 24, count 0 2006.253.07:46:21.97#ibcon#end of sib2, iclass 24, count 0 2006.253.07:46:21.97#ibcon#*after write, iclass 24, count 0 2006.253.07:46:21.97#ibcon#*before return 0, iclass 24, count 0 2006.253.07:46:21.97#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.253.07:46:21.97#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.253.07:46:21.97#ibcon#about to clear, iclass 24 cls_cnt 0 2006.253.07:46:21.97#ibcon#cleared, iclass 24 cls_cnt 0 2006.253.07:46:21.97$vc4f8/vb=5,4 2006.253.07:46:21.98#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.253.07:46:21.98#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.253.07:46:21.98#ibcon#ireg 11 cls_cnt 2 2006.253.07:46:21.98#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.253.07:46:22.03#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.253.07:46:22.03#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.253.07:46:22.03#ibcon#enter wrdev, iclass 26, count 2 2006.253.07:46:22.03#ibcon#first serial, iclass 26, count 2 2006.253.07:46:22.03#ibcon#enter sib2, iclass 26, count 2 2006.253.07:46:22.03#ibcon#flushed, iclass 26, count 2 2006.253.07:46:22.03#ibcon#about to write, iclass 26, count 2 2006.253.07:46:22.03#ibcon#wrote, iclass 26, count 2 2006.253.07:46:22.03#ibcon#about to read 3, iclass 26, count 2 2006.253.07:46:22.04#ibcon#read 3, iclass 26, count 2 2006.253.07:46:22.04#ibcon#about to read 4, iclass 26, count 2 2006.253.07:46:22.04#ibcon#read 4, iclass 26, count 2 2006.253.07:46:22.04#ibcon#about to read 5, iclass 26, count 2 2006.253.07:46:22.04#ibcon#read 5, iclass 26, count 2 2006.253.07:46:22.04#ibcon#about to read 6, iclass 26, count 2 2006.253.07:46:22.04#ibcon#read 6, iclass 26, count 2 2006.253.07:46:22.04#ibcon#end of sib2, iclass 26, count 2 2006.253.07:46:22.04#ibcon#*mode == 0, iclass 26, count 2 2006.253.07:46:22.04#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.253.07:46:22.04#ibcon#[27=AT05-04\r\n] 2006.253.07:46:22.04#ibcon#*before write, iclass 26, count 2 2006.253.07:46:22.04#ibcon#enter sib2, iclass 26, count 2 2006.253.07:46:22.04#ibcon#flushed, iclass 26, count 2 2006.253.07:46:22.04#ibcon#about to write, iclass 26, count 2 2006.253.07:46:22.04#ibcon#wrote, iclass 26, count 2 2006.253.07:46:22.04#ibcon#about to read 3, iclass 26, count 2 2006.253.07:46:22.07#ibcon#read 3, iclass 26, count 2 2006.253.07:46:22.07#ibcon#about to read 4, iclass 26, count 2 2006.253.07:46:22.07#ibcon#read 4, iclass 26, count 2 2006.253.07:46:22.07#ibcon#about to read 5, iclass 26, count 2 2006.253.07:46:22.07#ibcon#read 5, iclass 26, count 2 2006.253.07:46:22.07#ibcon#about to read 6, iclass 26, count 2 2006.253.07:46:22.07#ibcon#read 6, iclass 26, count 2 2006.253.07:46:22.07#ibcon#end of sib2, iclass 26, count 2 2006.253.07:46:22.07#ibcon#*after write, iclass 26, count 2 2006.253.07:46:22.07#ibcon#*before return 0, iclass 26, count 2 2006.253.07:46:22.07#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.253.07:46:22.07#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.253.07:46:22.07#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.253.07:46:22.07#ibcon#ireg 7 cls_cnt 0 2006.253.07:46:22.07#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.253.07:46:22.19#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.253.07:46:22.19#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.253.07:46:22.19#ibcon#enter wrdev, iclass 26, count 0 2006.253.07:46:22.19#ibcon#first serial, iclass 26, count 0 2006.253.07:46:22.19#ibcon#enter sib2, iclass 26, count 0 2006.253.07:46:22.19#ibcon#flushed, iclass 26, count 0 2006.253.07:46:22.19#ibcon#about to write, iclass 26, count 0 2006.253.07:46:22.19#ibcon#wrote, iclass 26, count 0 2006.253.07:46:22.19#ibcon#about to read 3, iclass 26, count 0 2006.253.07:46:22.21#ibcon#read 3, iclass 26, count 0 2006.253.07:46:22.21#ibcon#about to read 4, iclass 26, count 0 2006.253.07:46:22.21#ibcon#read 4, iclass 26, count 0 2006.253.07:46:22.21#ibcon#about to read 5, iclass 26, count 0 2006.253.07:46:22.21#ibcon#read 5, iclass 26, count 0 2006.253.07:46:22.21#ibcon#about to read 6, iclass 26, count 0 2006.253.07:46:22.21#ibcon#read 6, iclass 26, count 0 2006.253.07:46:22.21#ibcon#end of sib2, iclass 26, count 0 2006.253.07:46:22.21#ibcon#*mode == 0, iclass 26, count 0 2006.253.07:46:22.21#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.253.07:46:22.21#ibcon#[27=USB\r\n] 2006.253.07:46:22.21#ibcon#*before write, iclass 26, count 0 2006.253.07:46:22.21#ibcon#enter sib2, iclass 26, count 0 2006.253.07:46:22.21#ibcon#flushed, iclass 26, count 0 2006.253.07:46:22.21#ibcon#about to write, iclass 26, count 0 2006.253.07:46:22.21#ibcon#wrote, iclass 26, count 0 2006.253.07:46:22.21#ibcon#about to read 3, iclass 26, count 0 2006.253.07:46:22.24#ibcon#read 3, iclass 26, count 0 2006.253.07:46:22.24#ibcon#about to read 4, iclass 26, count 0 2006.253.07:46:22.24#ibcon#read 4, iclass 26, count 0 2006.253.07:46:22.24#ibcon#about to read 5, iclass 26, count 0 2006.253.07:46:22.24#ibcon#read 5, iclass 26, count 0 2006.253.07:46:22.24#ibcon#about to read 6, iclass 26, count 0 2006.253.07:46:22.24#ibcon#read 6, iclass 26, count 0 2006.253.07:46:22.24#ibcon#end of sib2, iclass 26, count 0 2006.253.07:46:22.24#ibcon#*after write, iclass 26, count 0 2006.253.07:46:22.24#ibcon#*before return 0, iclass 26, count 0 2006.253.07:46:22.24#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.253.07:46:22.24#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.253.07:46:22.24#ibcon#about to clear, iclass 26 cls_cnt 0 2006.253.07:46:22.24#ibcon#cleared, iclass 26 cls_cnt 0 2006.253.07:46:22.24$vc4f8/vblo=6,752.99 2006.253.07:46:22.25#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.253.07:46:22.25#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.253.07:46:22.25#ibcon#ireg 17 cls_cnt 0 2006.253.07:46:22.25#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.253.07:46:22.25#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.253.07:46:22.25#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.253.07:46:22.25#ibcon#enter wrdev, iclass 28, count 0 2006.253.07:46:22.25#ibcon#first serial, iclass 28, count 0 2006.253.07:46:22.25#ibcon#enter sib2, iclass 28, count 0 2006.253.07:46:22.25#ibcon#flushed, iclass 28, count 0 2006.253.07:46:22.25#ibcon#about to write, iclass 28, count 0 2006.253.07:46:22.25#ibcon#wrote, iclass 28, count 0 2006.253.07:46:22.25#ibcon#about to read 3, iclass 28, count 0 2006.253.07:46:22.26#ibcon#read 3, iclass 28, count 0 2006.253.07:46:22.26#ibcon#about to read 4, iclass 28, count 0 2006.253.07:46:22.26#ibcon#read 4, iclass 28, count 0 2006.253.07:46:22.26#ibcon#about to read 5, iclass 28, count 0 2006.253.07:46:22.26#ibcon#read 5, iclass 28, count 0 2006.253.07:46:22.26#ibcon#about to read 6, iclass 28, count 0 2006.253.07:46:22.26#ibcon#read 6, iclass 28, count 0 2006.253.07:46:22.26#ibcon#end of sib2, iclass 28, count 0 2006.253.07:46:22.26#ibcon#*mode == 0, iclass 28, count 0 2006.253.07:46:22.26#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.253.07:46:22.26#ibcon#[28=FRQ=06,752.99\r\n] 2006.253.07:46:22.26#ibcon#*before write, iclass 28, count 0 2006.253.07:46:22.26#ibcon#enter sib2, iclass 28, count 0 2006.253.07:46:22.26#ibcon#flushed, iclass 28, count 0 2006.253.07:46:22.26#ibcon#about to write, iclass 28, count 0 2006.253.07:46:22.26#ibcon#wrote, iclass 28, count 0 2006.253.07:46:22.26#ibcon#about to read 3, iclass 28, count 0 2006.253.07:46:22.30#ibcon#read 3, iclass 28, count 0 2006.253.07:46:22.30#ibcon#about to read 4, iclass 28, count 0 2006.253.07:46:22.30#ibcon#read 4, iclass 28, count 0 2006.253.07:46:22.30#ibcon#about to read 5, iclass 28, count 0 2006.253.07:46:22.30#ibcon#read 5, iclass 28, count 0 2006.253.07:46:22.30#ibcon#about to read 6, iclass 28, count 0 2006.253.07:46:22.30#ibcon#read 6, iclass 28, count 0 2006.253.07:46:22.30#ibcon#end of sib2, iclass 28, count 0 2006.253.07:46:22.30#ibcon#*after write, iclass 28, count 0 2006.253.07:46:22.30#ibcon#*before return 0, iclass 28, count 0 2006.253.07:46:22.30#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.253.07:46:22.30#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.253.07:46:22.30#ibcon#about to clear, iclass 28 cls_cnt 0 2006.253.07:46:22.30#ibcon#cleared, iclass 28 cls_cnt 0 2006.253.07:46:22.31$vc4f8/vb=6,4 2006.253.07:46:22.31#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.253.07:46:22.31#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.253.07:46:22.31#ibcon#ireg 11 cls_cnt 2 2006.253.07:46:22.31#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.253.07:46:22.35#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.253.07:46:22.35#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.253.07:46:22.35#ibcon#enter wrdev, iclass 30, count 2 2006.253.07:46:22.35#ibcon#first serial, iclass 30, count 2 2006.253.07:46:22.35#ibcon#enter sib2, iclass 30, count 2 2006.253.07:46:22.35#ibcon#flushed, iclass 30, count 2 2006.253.07:46:22.35#ibcon#about to write, iclass 30, count 2 2006.253.07:46:22.35#ibcon#wrote, iclass 30, count 2 2006.253.07:46:22.35#ibcon#about to read 3, iclass 30, count 2 2006.253.07:46:22.37#ibcon#read 3, iclass 30, count 2 2006.253.07:46:22.37#ibcon#about to read 4, iclass 30, count 2 2006.253.07:46:22.37#ibcon#read 4, iclass 30, count 2 2006.253.07:46:22.37#ibcon#about to read 5, iclass 30, count 2 2006.253.07:46:22.37#ibcon#read 5, iclass 30, count 2 2006.253.07:46:22.37#ibcon#about to read 6, iclass 30, count 2 2006.253.07:46:22.37#ibcon#read 6, iclass 30, count 2 2006.253.07:46:22.37#ibcon#end of sib2, iclass 30, count 2 2006.253.07:46:22.37#ibcon#*mode == 0, iclass 30, count 2 2006.253.07:46:22.37#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.253.07:46:22.37#ibcon#[27=AT06-04\r\n] 2006.253.07:46:22.37#ibcon#*before write, iclass 30, count 2 2006.253.07:46:22.37#ibcon#enter sib2, iclass 30, count 2 2006.253.07:46:22.37#ibcon#flushed, iclass 30, count 2 2006.253.07:46:22.37#ibcon#about to write, iclass 30, count 2 2006.253.07:46:22.37#ibcon#wrote, iclass 30, count 2 2006.253.07:46:22.37#ibcon#about to read 3, iclass 30, count 2 2006.253.07:46:22.40#ibcon#read 3, iclass 30, count 2 2006.253.07:46:22.40#ibcon#about to read 4, iclass 30, count 2 2006.253.07:46:22.40#ibcon#read 4, iclass 30, count 2 2006.253.07:46:22.40#ibcon#about to read 5, iclass 30, count 2 2006.253.07:46:22.40#ibcon#read 5, iclass 30, count 2 2006.253.07:46:22.40#ibcon#about to read 6, iclass 30, count 2 2006.253.07:46:22.40#ibcon#read 6, iclass 30, count 2 2006.253.07:46:22.40#ibcon#end of sib2, iclass 30, count 2 2006.253.07:46:22.40#ibcon#*after write, iclass 30, count 2 2006.253.07:46:22.40#ibcon#*before return 0, iclass 30, count 2 2006.253.07:46:22.40#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.253.07:46:22.40#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.253.07:46:22.40#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.253.07:46:22.40#ibcon#ireg 7 cls_cnt 0 2006.253.07:46:22.40#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.253.07:46:22.52#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.253.07:46:22.52#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.253.07:46:22.52#ibcon#enter wrdev, iclass 30, count 0 2006.253.07:46:22.52#ibcon#first serial, iclass 30, count 0 2006.253.07:46:22.52#ibcon#enter sib2, iclass 30, count 0 2006.253.07:46:22.52#ibcon#flushed, iclass 30, count 0 2006.253.07:46:22.52#ibcon#about to write, iclass 30, count 0 2006.253.07:46:22.52#ibcon#wrote, iclass 30, count 0 2006.253.07:46:22.52#ibcon#about to read 3, iclass 30, count 0 2006.253.07:46:22.54#ibcon#read 3, iclass 30, count 0 2006.253.07:46:22.54#ibcon#about to read 4, iclass 30, count 0 2006.253.07:46:22.54#ibcon#read 4, iclass 30, count 0 2006.253.07:46:22.54#ibcon#about to read 5, iclass 30, count 0 2006.253.07:46:22.54#ibcon#read 5, iclass 30, count 0 2006.253.07:46:22.54#ibcon#about to read 6, iclass 30, count 0 2006.253.07:46:22.54#ibcon#read 6, iclass 30, count 0 2006.253.07:46:22.54#ibcon#end of sib2, iclass 30, count 0 2006.253.07:46:22.54#ibcon#*mode == 0, iclass 30, count 0 2006.253.07:46:22.54#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.253.07:46:22.54#ibcon#[27=USB\r\n] 2006.253.07:46:22.54#ibcon#*before write, iclass 30, count 0 2006.253.07:46:22.54#ibcon#enter sib2, iclass 30, count 0 2006.253.07:46:22.54#ibcon#flushed, iclass 30, count 0 2006.253.07:46:22.54#ibcon#about to write, iclass 30, count 0 2006.253.07:46:22.54#ibcon#wrote, iclass 30, count 0 2006.253.07:46:22.54#ibcon#about to read 3, iclass 30, count 0 2006.253.07:46:22.57#ibcon#read 3, iclass 30, count 0 2006.253.07:46:22.57#ibcon#about to read 4, iclass 30, count 0 2006.253.07:46:22.57#ibcon#read 4, iclass 30, count 0 2006.253.07:46:22.57#ibcon#about to read 5, iclass 30, count 0 2006.253.07:46:22.57#ibcon#read 5, iclass 30, count 0 2006.253.07:46:22.57#ibcon#about to read 6, iclass 30, count 0 2006.253.07:46:22.57#ibcon#read 6, iclass 30, count 0 2006.253.07:46:22.57#ibcon#end of sib2, iclass 30, count 0 2006.253.07:46:22.57#ibcon#*after write, iclass 30, count 0 2006.253.07:46:22.57#ibcon#*before return 0, iclass 30, count 0 2006.253.07:46:22.57#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.253.07:46:22.57#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.253.07:46:22.57#ibcon#about to clear, iclass 30 cls_cnt 0 2006.253.07:46:22.57#ibcon#cleared, iclass 30 cls_cnt 0 2006.253.07:46:22.57$vc4f8/vabw=wide 2006.253.07:46:22.58#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.253.07:46:22.58#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.253.07:46:22.58#ibcon#ireg 8 cls_cnt 0 2006.253.07:46:22.58#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.253.07:46:22.58#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.253.07:46:22.58#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.253.07:46:22.58#ibcon#enter wrdev, iclass 32, count 0 2006.253.07:46:22.58#ibcon#first serial, iclass 32, count 0 2006.253.07:46:22.58#ibcon#enter sib2, iclass 32, count 0 2006.253.07:46:22.58#ibcon#flushed, iclass 32, count 0 2006.253.07:46:22.58#ibcon#about to write, iclass 32, count 0 2006.253.07:46:22.58#ibcon#wrote, iclass 32, count 0 2006.253.07:46:22.58#ibcon#about to read 3, iclass 32, count 0 2006.253.07:46:22.59#ibcon#read 3, iclass 32, count 0 2006.253.07:46:22.59#ibcon#about to read 4, iclass 32, count 0 2006.253.07:46:22.59#ibcon#read 4, iclass 32, count 0 2006.253.07:46:22.59#ibcon#about to read 5, iclass 32, count 0 2006.253.07:46:22.59#ibcon#read 5, iclass 32, count 0 2006.253.07:46:22.59#ibcon#about to read 6, iclass 32, count 0 2006.253.07:46:22.59#ibcon#read 6, iclass 32, count 0 2006.253.07:46:22.59#ibcon#end of sib2, iclass 32, count 0 2006.253.07:46:22.59#ibcon#*mode == 0, iclass 32, count 0 2006.253.07:46:22.59#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.253.07:46:22.59#ibcon#[25=BW32\r\n] 2006.253.07:46:22.59#ibcon#*before write, iclass 32, count 0 2006.253.07:46:22.59#ibcon#enter sib2, iclass 32, count 0 2006.253.07:46:22.59#ibcon#flushed, iclass 32, count 0 2006.253.07:46:22.59#ibcon#about to write, iclass 32, count 0 2006.253.07:46:22.59#ibcon#wrote, iclass 32, count 0 2006.253.07:46:22.59#ibcon#about to read 3, iclass 32, count 0 2006.253.07:46:22.62#ibcon#read 3, iclass 32, count 0 2006.253.07:46:22.62#ibcon#about to read 4, iclass 32, count 0 2006.253.07:46:22.62#ibcon#read 4, iclass 32, count 0 2006.253.07:46:22.62#ibcon#about to read 5, iclass 32, count 0 2006.253.07:46:22.62#ibcon#read 5, iclass 32, count 0 2006.253.07:46:22.62#ibcon#about to read 6, iclass 32, count 0 2006.253.07:46:22.62#ibcon#read 6, iclass 32, count 0 2006.253.07:46:22.62#ibcon#end of sib2, iclass 32, count 0 2006.253.07:46:22.62#ibcon#*after write, iclass 32, count 0 2006.253.07:46:22.62#ibcon#*before return 0, iclass 32, count 0 2006.253.07:46:22.62#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.253.07:46:22.62#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.253.07:46:22.62#ibcon#about to clear, iclass 32 cls_cnt 0 2006.253.07:46:22.62#ibcon#cleared, iclass 32 cls_cnt 0 2006.253.07:46:22.62$vc4f8/vbbw=wide 2006.253.07:46:22.62#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.253.07:46:22.62#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.253.07:46:22.63#ibcon#ireg 8 cls_cnt 0 2006.253.07:46:22.63#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.253.07:46:22.68#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.253.07:46:22.68#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.253.07:46:22.68#ibcon#enter wrdev, iclass 34, count 0 2006.253.07:46:22.68#ibcon#first serial, iclass 34, count 0 2006.253.07:46:22.68#ibcon#enter sib2, iclass 34, count 0 2006.253.07:46:22.68#ibcon#flushed, iclass 34, count 0 2006.253.07:46:22.68#ibcon#about to write, iclass 34, count 0 2006.253.07:46:22.68#ibcon#wrote, iclass 34, count 0 2006.253.07:46:22.68#ibcon#about to read 3, iclass 34, count 0 2006.253.07:46:22.70#ibcon#read 3, iclass 34, count 0 2006.253.07:46:22.70#ibcon#about to read 4, iclass 34, count 0 2006.253.07:46:22.70#ibcon#read 4, iclass 34, count 0 2006.253.07:46:22.70#ibcon#about to read 5, iclass 34, count 0 2006.253.07:46:22.70#ibcon#read 5, iclass 34, count 0 2006.253.07:46:22.70#ibcon#about to read 6, iclass 34, count 0 2006.253.07:46:22.70#ibcon#read 6, iclass 34, count 0 2006.253.07:46:22.70#ibcon#end of sib2, iclass 34, count 0 2006.253.07:46:22.70#ibcon#*mode == 0, iclass 34, count 0 2006.253.07:46:22.70#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.253.07:46:22.70#ibcon#[27=BW32\r\n] 2006.253.07:46:22.70#ibcon#*before write, iclass 34, count 0 2006.253.07:46:22.70#ibcon#enter sib2, iclass 34, count 0 2006.253.07:46:22.70#ibcon#flushed, iclass 34, count 0 2006.253.07:46:22.70#ibcon#about to write, iclass 34, count 0 2006.253.07:46:22.70#ibcon#wrote, iclass 34, count 0 2006.253.07:46:22.70#ibcon#about to read 3, iclass 34, count 0 2006.253.07:46:22.73#ibcon#read 3, iclass 34, count 0 2006.253.07:46:22.73#ibcon#about to read 4, iclass 34, count 0 2006.253.07:46:22.73#ibcon#read 4, iclass 34, count 0 2006.253.07:46:22.73#ibcon#about to read 5, iclass 34, count 0 2006.253.07:46:22.73#ibcon#read 5, iclass 34, count 0 2006.253.07:46:22.73#ibcon#about to read 6, iclass 34, count 0 2006.253.07:46:22.73#ibcon#read 6, iclass 34, count 0 2006.253.07:46:22.73#ibcon#end of sib2, iclass 34, count 0 2006.253.07:46:22.73#ibcon#*after write, iclass 34, count 0 2006.253.07:46:22.73#ibcon#*before return 0, iclass 34, count 0 2006.253.07:46:22.73#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.253.07:46:22.73#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.253.07:46:22.73#ibcon#about to clear, iclass 34 cls_cnt 0 2006.253.07:46:22.73#ibcon#cleared, iclass 34 cls_cnt 0 2006.253.07:46:22.73$4f8m12a/ifd4f 2006.253.07:46:22.74$ifd4f/lo= 2006.253.07:46:22.74$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.253.07:46:22.74$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.253.07:46:22.74$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.253.07:46:22.74$ifd4f/patch= 2006.253.07:46:22.74$ifd4f/patch=lo1,a1,a2,a3,a4 2006.253.07:46:22.74$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.253.07:46:22.74$ifd4f/patch=lo3,a5,a6,a7,a8 2006.253.07:46:22.74$4f8m12a/"form=m,16.000,1:2 2006.253.07:46:22.74$4f8m12a/"tpicd 2006.253.07:46:22.74$4f8m12a/echo=off 2006.253.07:46:22.74$4f8m12a/xlog=off 2006.253.07:46:22.74:!2006.253.07:46:50 2006.253.07:46:31.13#trakl#Source acquired 2006.253.07:46:32.13#flagr#flagr/antenna,acquired 2006.253.07:46:50.01:preob 2006.253.07:46:51.13/onsource/TRACKING 2006.253.07:46:51.14:!2006.253.07:47:00 2006.253.07:47:00.01:data_valid=on 2006.253.07:47:00.02:midob 2006.253.07:47:01.13/onsource/TRACKING 2006.253.07:47:01.14/wx/31.37,1006.4,73 2006.253.07:47:01.23/cable/+6.3678E-03 2006.253.07:47:02.32/va/01,08,usb,yes,32,33 2006.253.07:47:02.32/va/02,07,usb,yes,31,33 2006.253.07:47:02.32/va/03,06,usb,yes,34,34 2006.253.07:47:02.32/va/04,07,usb,yes,33,35 2006.253.07:47:02.32/va/05,07,usb,yes,34,36 2006.253.07:47:02.32/va/06,07,usb,yes,30,30 2006.253.07:47:02.32/va/07,07,usb,yes,30,29 2006.253.07:47:02.32/va/08,07,usb,yes,32,32 2006.253.07:47:02.55/valo/01,532.99,yes,locked 2006.253.07:47:02.55/valo/02,572.99,yes,locked 2006.253.07:47:02.55/valo/03,672.99,yes,locked 2006.253.07:47:02.55/valo/04,832.99,yes,locked 2006.253.07:47:02.55/valo/05,652.99,yes,locked 2006.253.07:47:02.55/valo/06,772.99,yes,locked 2006.253.07:47:02.55/valo/07,832.99,yes,locked 2006.253.07:47:02.55/valo/08,852.99,yes,locked 2006.253.07:47:03.64/vb/01,04,usb,yes,30,29 2006.253.07:47:03.64/vb/02,05,usb,yes,28,29 2006.253.07:47:03.64/vb/03,04,usb,yes,28,32 2006.253.07:47:03.64/vb/04,04,usb,yes,29,29 2006.253.07:47:03.64/vb/05,04,usb,yes,28,32 2006.253.07:47:03.64/vb/06,04,usb,yes,29,31 2006.253.07:47:03.64/vb/07,04,usb,yes,31,31 2006.253.07:47:03.64/vb/08,04,usb,yes,28,32 2006.253.07:47:03.88/vblo/01,632.99,yes,locked 2006.253.07:47:03.88/vblo/02,640.99,yes,locked 2006.253.07:47:03.88/vblo/03,656.99,yes,locked 2006.253.07:47:03.88/vblo/04,712.99,yes,locked 2006.253.07:47:03.88/vblo/05,744.99,yes,locked 2006.253.07:47:03.88/vblo/06,752.99,yes,locked 2006.253.07:47:03.88/vblo/07,734.99,yes,locked 2006.253.07:47:03.88/vblo/08,744.99,yes,locked 2006.253.07:47:04.03/vabw/8 2006.253.07:47:04.18/vbbw/8 2006.253.07:47:04.27/xfe/off,on,14.7 2006.253.07:47:04.64/ifatt/23,28,28,28 2006.253.07:47:05.07/fmout-gps/S +4.74E-07 2006.253.07:47:05.12:!2006.253.07:48:00 2006.253.07:48:00.00:data_valid=off 2006.253.07:48:00.01:postob 2006.253.07:48:00.08/cable/+6.3684E-03 2006.253.07:48:00.09/wx/31.35,1006.4,73 2006.253.07:48:01.07/fmout-gps/S +4.74E-07 2006.253.07:48:01.08:scan_name=253-0748,k06253,60 2006.253.07:48:01.08:source=nrao512,164029.63,394646.0,2000.0,cw 2006.253.07:48:02.14#flagr#flagr/antenna,new-source 2006.253.07:48:02.15:checkk5 2006.253.07:48:02.53/chk_autoobs//k5ts1/ autoobs is running! 2006.253.07:48:02.90/chk_autoobs//k5ts2/ autoobs is running! 2006.253.07:48:03.28/chk_autoobs//k5ts3/ autoobs is running! 2006.253.07:48:03.65/chk_autoobs//k5ts4/ autoobs is running! 2006.253.07:48:04.02/chk_obsdata//k5ts1/T2530747??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.07:48:04.39/chk_obsdata//k5ts2/T2530747??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.07:48:04.75/chk_obsdata//k5ts3/T2530747??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.07:48:05.13/chk_obsdata//k5ts4/T2530747??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.07:48:05.83/k5log//k5ts1_log_newline 2006.253.07:48:06.52/k5log//k5ts2_log_newline 2006.253.07:48:07.20/k5log//k5ts3_log_newline 2006.253.07:48:07.90/k5log//k5ts4_log_newline 2006.253.07:48:07.92/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.253.07:48:07.92:4f8m12a=1 2006.253.07:48:07.92$4f8m12a/echo=on 2006.253.07:48:07.92$4f8m12a/pcalon 2006.253.07:48:07.92$pcalon/"no phase cal control is implemented here 2006.253.07:48:07.92$4f8m12a/"tpicd=stop 2006.253.07:48:07.92$4f8m12a/vc4f8 2006.253.07:48:07.92$vc4f8/valo=1,532.99 2006.253.07:48:07.93#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.253.07:48:07.93#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.253.07:48:07.93#ibcon#ireg 17 cls_cnt 0 2006.253.07:48:07.93#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.253.07:48:07.93#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.253.07:48:07.93#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.253.07:48:07.93#ibcon#enter wrdev, iclass 7, count 0 2006.253.07:48:07.93#ibcon#first serial, iclass 7, count 0 2006.253.07:48:07.93#ibcon#enter sib2, iclass 7, count 0 2006.253.07:48:07.93#ibcon#flushed, iclass 7, count 0 2006.253.07:48:07.93#ibcon#about to write, iclass 7, count 0 2006.253.07:48:07.93#ibcon#wrote, iclass 7, count 0 2006.253.07:48:07.93#ibcon#about to read 3, iclass 7, count 0 2006.253.07:48:07.96#ibcon#read 3, iclass 7, count 0 2006.253.07:48:07.96#ibcon#about to read 4, iclass 7, count 0 2006.253.07:48:07.96#ibcon#read 4, iclass 7, count 0 2006.253.07:48:07.96#ibcon#about to read 5, iclass 7, count 0 2006.253.07:48:07.96#ibcon#read 5, iclass 7, count 0 2006.253.07:48:07.96#ibcon#about to read 6, iclass 7, count 0 2006.253.07:48:07.96#ibcon#read 6, iclass 7, count 0 2006.253.07:48:07.96#ibcon#end of sib2, iclass 7, count 0 2006.253.07:48:07.96#ibcon#*mode == 0, iclass 7, count 0 2006.253.07:48:07.96#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.253.07:48:07.96#ibcon#[26=FRQ=01,532.99\r\n] 2006.253.07:48:07.96#ibcon#*before write, iclass 7, count 0 2006.253.07:48:07.96#ibcon#enter sib2, iclass 7, count 0 2006.253.07:48:07.96#ibcon#flushed, iclass 7, count 0 2006.253.07:48:07.96#ibcon#about to write, iclass 7, count 0 2006.253.07:48:07.96#ibcon#wrote, iclass 7, count 0 2006.253.07:48:07.96#ibcon#about to read 3, iclass 7, count 0 2006.253.07:48:08.01#ibcon#read 3, iclass 7, count 0 2006.253.07:48:08.01#ibcon#about to read 4, iclass 7, count 0 2006.253.07:48:08.01#ibcon#read 4, iclass 7, count 0 2006.253.07:48:08.01#ibcon#about to read 5, iclass 7, count 0 2006.253.07:48:08.01#ibcon#read 5, iclass 7, count 0 2006.253.07:48:08.01#ibcon#about to read 6, iclass 7, count 0 2006.253.07:48:08.01#ibcon#read 6, iclass 7, count 0 2006.253.07:48:08.01#ibcon#end of sib2, iclass 7, count 0 2006.253.07:48:08.01#ibcon#*after write, iclass 7, count 0 2006.253.07:48:08.01#ibcon#*before return 0, iclass 7, count 0 2006.253.07:48:08.01#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.253.07:48:08.01#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.253.07:48:08.01#ibcon#about to clear, iclass 7 cls_cnt 0 2006.253.07:48:08.01#ibcon#cleared, iclass 7 cls_cnt 0 2006.253.07:48:08.01$vc4f8/va=1,8 2006.253.07:48:08.01#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.253.07:48:08.01#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.253.07:48:08.01#ibcon#ireg 11 cls_cnt 2 2006.253.07:48:08.01#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.253.07:48:08.01#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.253.07:48:08.01#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.253.07:48:08.01#ibcon#enter wrdev, iclass 11, count 2 2006.253.07:48:08.01#ibcon#first serial, iclass 11, count 2 2006.253.07:48:08.01#ibcon#enter sib2, iclass 11, count 2 2006.253.07:48:08.01#ibcon#flushed, iclass 11, count 2 2006.253.07:48:08.01#ibcon#about to write, iclass 11, count 2 2006.253.07:48:08.01#ibcon#wrote, iclass 11, count 2 2006.253.07:48:08.01#ibcon#about to read 3, iclass 11, count 2 2006.253.07:48:08.04#ibcon#read 3, iclass 11, count 2 2006.253.07:48:08.04#ibcon#about to read 4, iclass 11, count 2 2006.253.07:48:08.04#ibcon#read 4, iclass 11, count 2 2006.253.07:48:08.04#ibcon#about to read 5, iclass 11, count 2 2006.253.07:48:08.04#ibcon#read 5, iclass 11, count 2 2006.253.07:48:08.04#ibcon#about to read 6, iclass 11, count 2 2006.253.07:48:08.04#ibcon#read 6, iclass 11, count 2 2006.253.07:48:08.04#ibcon#end of sib2, iclass 11, count 2 2006.253.07:48:08.04#ibcon#*mode == 0, iclass 11, count 2 2006.253.07:48:08.04#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.253.07:48:08.04#ibcon#[25=AT01-08\r\n] 2006.253.07:48:08.04#ibcon#*before write, iclass 11, count 2 2006.253.07:48:08.04#ibcon#enter sib2, iclass 11, count 2 2006.253.07:48:08.04#ibcon#flushed, iclass 11, count 2 2006.253.07:48:08.04#ibcon#about to write, iclass 11, count 2 2006.253.07:48:08.04#ibcon#wrote, iclass 11, count 2 2006.253.07:48:08.04#ibcon#about to read 3, iclass 11, count 2 2006.253.07:48:08.06#ibcon#read 3, iclass 11, count 2 2006.253.07:48:08.06#ibcon#about to read 4, iclass 11, count 2 2006.253.07:48:08.06#ibcon#read 4, iclass 11, count 2 2006.253.07:48:08.06#ibcon#about to read 5, iclass 11, count 2 2006.253.07:48:08.06#ibcon#read 5, iclass 11, count 2 2006.253.07:48:08.06#ibcon#about to read 6, iclass 11, count 2 2006.253.07:48:08.06#ibcon#read 6, iclass 11, count 2 2006.253.07:48:08.06#ibcon#end of sib2, iclass 11, count 2 2006.253.07:48:08.06#ibcon#*after write, iclass 11, count 2 2006.253.07:48:08.06#ibcon#*before return 0, iclass 11, count 2 2006.253.07:48:08.06#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.253.07:48:08.06#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.253.07:48:08.06#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.253.07:48:08.06#ibcon#ireg 7 cls_cnt 0 2006.253.07:48:08.06#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.253.07:48:08.18#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.253.07:48:08.18#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.253.07:48:08.18#ibcon#enter wrdev, iclass 11, count 0 2006.253.07:48:08.18#ibcon#first serial, iclass 11, count 0 2006.253.07:48:08.18#ibcon#enter sib2, iclass 11, count 0 2006.253.07:48:08.18#ibcon#flushed, iclass 11, count 0 2006.253.07:48:08.18#ibcon#about to write, iclass 11, count 0 2006.253.07:48:08.18#ibcon#wrote, iclass 11, count 0 2006.253.07:48:08.18#ibcon#about to read 3, iclass 11, count 0 2006.253.07:48:08.20#ibcon#read 3, iclass 11, count 0 2006.253.07:48:08.20#ibcon#about to read 4, iclass 11, count 0 2006.253.07:48:08.20#ibcon#read 4, iclass 11, count 0 2006.253.07:48:08.20#ibcon#about to read 5, iclass 11, count 0 2006.253.07:48:08.20#ibcon#read 5, iclass 11, count 0 2006.253.07:48:08.20#ibcon#about to read 6, iclass 11, count 0 2006.253.07:48:08.20#ibcon#read 6, iclass 11, count 0 2006.253.07:48:08.20#ibcon#end of sib2, iclass 11, count 0 2006.253.07:48:08.20#ibcon#*mode == 0, iclass 11, count 0 2006.253.07:48:08.20#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.253.07:48:08.20#ibcon#[25=USB\r\n] 2006.253.07:48:08.20#ibcon#*before write, iclass 11, count 0 2006.253.07:48:08.20#ibcon#enter sib2, iclass 11, count 0 2006.253.07:48:08.20#ibcon#flushed, iclass 11, count 0 2006.253.07:48:08.20#ibcon#about to write, iclass 11, count 0 2006.253.07:48:08.20#ibcon#wrote, iclass 11, count 0 2006.253.07:48:08.20#ibcon#about to read 3, iclass 11, count 0 2006.253.07:48:08.24#ibcon#read 3, iclass 11, count 0 2006.253.07:48:08.24#ibcon#about to read 4, iclass 11, count 0 2006.253.07:48:08.24#ibcon#read 4, iclass 11, count 0 2006.253.07:48:08.24#ibcon#about to read 5, iclass 11, count 0 2006.253.07:48:08.24#ibcon#read 5, iclass 11, count 0 2006.253.07:48:08.24#ibcon#about to read 6, iclass 11, count 0 2006.253.07:48:08.24#ibcon#read 6, iclass 11, count 0 2006.253.07:48:08.24#ibcon#end of sib2, iclass 11, count 0 2006.253.07:48:08.24#ibcon#*after write, iclass 11, count 0 2006.253.07:48:08.24#ibcon#*before return 0, iclass 11, count 0 2006.253.07:48:08.24#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.253.07:48:08.24#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.253.07:48:08.24#ibcon#about to clear, iclass 11 cls_cnt 0 2006.253.07:48:08.24#ibcon#cleared, iclass 11 cls_cnt 0 2006.253.07:48:08.24$vc4f8/valo=2,572.99 2006.253.07:48:08.24#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.253.07:48:08.24#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.253.07:48:08.24#ibcon#ireg 17 cls_cnt 0 2006.253.07:48:08.24#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.253.07:48:08.24#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.253.07:48:08.24#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.253.07:48:08.24#ibcon#enter wrdev, iclass 13, count 0 2006.253.07:48:08.24#ibcon#first serial, iclass 13, count 0 2006.253.07:48:08.24#ibcon#enter sib2, iclass 13, count 0 2006.253.07:48:08.24#ibcon#flushed, iclass 13, count 0 2006.253.07:48:08.24#ibcon#about to write, iclass 13, count 0 2006.253.07:48:08.24#ibcon#wrote, iclass 13, count 0 2006.253.07:48:08.24#ibcon#about to read 3, iclass 13, count 0 2006.253.07:48:08.25#ibcon#read 3, iclass 13, count 0 2006.253.07:48:08.25#ibcon#about to read 4, iclass 13, count 0 2006.253.07:48:08.25#ibcon#read 4, iclass 13, count 0 2006.253.07:48:08.25#ibcon#about to read 5, iclass 13, count 0 2006.253.07:48:08.25#ibcon#read 5, iclass 13, count 0 2006.253.07:48:08.25#ibcon#about to read 6, iclass 13, count 0 2006.253.07:48:08.25#ibcon#read 6, iclass 13, count 0 2006.253.07:48:08.25#ibcon#end of sib2, iclass 13, count 0 2006.253.07:48:08.25#ibcon#*mode == 0, iclass 13, count 0 2006.253.07:48:08.25#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.253.07:48:08.25#ibcon#[26=FRQ=02,572.99\r\n] 2006.253.07:48:08.25#ibcon#*before write, iclass 13, count 0 2006.253.07:48:08.25#ibcon#enter sib2, iclass 13, count 0 2006.253.07:48:08.25#ibcon#flushed, iclass 13, count 0 2006.253.07:48:08.25#ibcon#about to write, iclass 13, count 0 2006.253.07:48:08.25#ibcon#wrote, iclass 13, count 0 2006.253.07:48:08.25#ibcon#about to read 3, iclass 13, count 0 2006.253.07:48:08.29#ibcon#read 3, iclass 13, count 0 2006.253.07:48:08.29#ibcon#about to read 4, iclass 13, count 0 2006.253.07:48:08.29#ibcon#read 4, iclass 13, count 0 2006.253.07:48:08.29#ibcon#about to read 5, iclass 13, count 0 2006.253.07:48:08.29#ibcon#read 5, iclass 13, count 0 2006.253.07:48:08.29#ibcon#about to read 6, iclass 13, count 0 2006.253.07:48:08.29#ibcon#read 6, iclass 13, count 0 2006.253.07:48:08.29#ibcon#end of sib2, iclass 13, count 0 2006.253.07:48:08.29#ibcon#*after write, iclass 13, count 0 2006.253.07:48:08.29#ibcon#*before return 0, iclass 13, count 0 2006.253.07:48:08.29#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.253.07:48:08.29#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.253.07:48:08.29#ibcon#about to clear, iclass 13 cls_cnt 0 2006.253.07:48:08.29#ibcon#cleared, iclass 13 cls_cnt 0 2006.253.07:48:08.29$vc4f8/va=2,7 2006.253.07:48:08.29#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.253.07:48:08.29#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.253.07:48:08.29#ibcon#ireg 11 cls_cnt 2 2006.253.07:48:08.29#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.253.07:48:08.36#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.253.07:48:08.36#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.253.07:48:08.36#ibcon#enter wrdev, iclass 15, count 2 2006.253.07:48:08.36#ibcon#first serial, iclass 15, count 2 2006.253.07:48:08.36#ibcon#enter sib2, iclass 15, count 2 2006.253.07:48:08.36#ibcon#flushed, iclass 15, count 2 2006.253.07:48:08.36#ibcon#about to write, iclass 15, count 2 2006.253.07:48:08.36#ibcon#wrote, iclass 15, count 2 2006.253.07:48:08.36#ibcon#about to read 3, iclass 15, count 2 2006.253.07:48:08.38#ibcon#read 3, iclass 15, count 2 2006.253.07:48:08.38#ibcon#about to read 4, iclass 15, count 2 2006.253.07:48:08.38#ibcon#read 4, iclass 15, count 2 2006.253.07:48:08.38#ibcon#about to read 5, iclass 15, count 2 2006.253.07:48:08.38#ibcon#read 5, iclass 15, count 2 2006.253.07:48:08.38#ibcon#about to read 6, iclass 15, count 2 2006.253.07:48:08.38#ibcon#read 6, iclass 15, count 2 2006.253.07:48:08.38#ibcon#end of sib2, iclass 15, count 2 2006.253.07:48:08.38#ibcon#*mode == 0, iclass 15, count 2 2006.253.07:48:08.38#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.253.07:48:08.38#ibcon#[25=AT02-07\r\n] 2006.253.07:48:08.38#ibcon#*before write, iclass 15, count 2 2006.253.07:48:08.38#ibcon#enter sib2, iclass 15, count 2 2006.253.07:48:08.38#ibcon#flushed, iclass 15, count 2 2006.253.07:48:08.38#ibcon#about to write, iclass 15, count 2 2006.253.07:48:08.38#ibcon#wrote, iclass 15, count 2 2006.253.07:48:08.38#ibcon#about to read 3, iclass 15, count 2 2006.253.07:48:08.41#ibcon#read 3, iclass 15, count 2 2006.253.07:48:08.41#ibcon#about to read 4, iclass 15, count 2 2006.253.07:48:08.41#ibcon#read 4, iclass 15, count 2 2006.253.07:48:08.41#ibcon#about to read 5, iclass 15, count 2 2006.253.07:48:08.41#ibcon#read 5, iclass 15, count 2 2006.253.07:48:08.41#ibcon#about to read 6, iclass 15, count 2 2006.253.07:48:08.41#ibcon#read 6, iclass 15, count 2 2006.253.07:48:08.41#ibcon#end of sib2, iclass 15, count 2 2006.253.07:48:08.41#ibcon#*after write, iclass 15, count 2 2006.253.07:48:08.41#ibcon#*before return 0, iclass 15, count 2 2006.253.07:48:08.41#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.253.07:48:08.41#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.253.07:48:08.41#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.253.07:48:08.41#ibcon#ireg 7 cls_cnt 0 2006.253.07:48:08.41#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.253.07:48:08.54#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.253.07:48:08.54#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.253.07:48:08.54#ibcon#enter wrdev, iclass 15, count 0 2006.253.07:48:08.54#ibcon#first serial, iclass 15, count 0 2006.253.07:48:08.54#ibcon#enter sib2, iclass 15, count 0 2006.253.07:48:08.54#ibcon#flushed, iclass 15, count 0 2006.253.07:48:08.54#ibcon#about to write, iclass 15, count 0 2006.253.07:48:08.54#ibcon#wrote, iclass 15, count 0 2006.253.07:48:08.54#ibcon#about to read 3, iclass 15, count 0 2006.253.07:48:08.55#ibcon#read 3, iclass 15, count 0 2006.253.07:48:08.55#ibcon#about to read 4, iclass 15, count 0 2006.253.07:48:08.55#ibcon#read 4, iclass 15, count 0 2006.253.07:48:08.55#ibcon#about to read 5, iclass 15, count 0 2006.253.07:48:08.55#ibcon#read 5, iclass 15, count 0 2006.253.07:48:08.55#ibcon#about to read 6, iclass 15, count 0 2006.253.07:48:08.55#ibcon#read 6, iclass 15, count 0 2006.253.07:48:08.55#ibcon#end of sib2, iclass 15, count 0 2006.253.07:48:08.55#ibcon#*mode == 0, iclass 15, count 0 2006.253.07:48:08.55#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.253.07:48:08.55#ibcon#[25=USB\r\n] 2006.253.07:48:08.55#ibcon#*before write, iclass 15, count 0 2006.253.07:48:08.55#ibcon#enter sib2, iclass 15, count 0 2006.253.07:48:08.55#ibcon#flushed, iclass 15, count 0 2006.253.07:48:08.55#ibcon#about to write, iclass 15, count 0 2006.253.07:48:08.55#ibcon#wrote, iclass 15, count 0 2006.253.07:48:08.55#ibcon#about to read 3, iclass 15, count 0 2006.253.07:48:08.58#ibcon#read 3, iclass 15, count 0 2006.253.07:48:08.58#ibcon#about to read 4, iclass 15, count 0 2006.253.07:48:08.58#ibcon#read 4, iclass 15, count 0 2006.253.07:48:08.58#ibcon#about to read 5, iclass 15, count 0 2006.253.07:48:08.58#ibcon#read 5, iclass 15, count 0 2006.253.07:48:08.58#ibcon#about to read 6, iclass 15, count 0 2006.253.07:48:08.58#ibcon#read 6, iclass 15, count 0 2006.253.07:48:08.58#ibcon#end of sib2, iclass 15, count 0 2006.253.07:48:08.58#ibcon#*after write, iclass 15, count 0 2006.253.07:48:08.58#ibcon#*before return 0, iclass 15, count 0 2006.253.07:48:08.58#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.253.07:48:08.58#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.253.07:48:08.58#ibcon#about to clear, iclass 15 cls_cnt 0 2006.253.07:48:08.58#ibcon#cleared, iclass 15 cls_cnt 0 2006.253.07:48:08.58$vc4f8/valo=3,672.99 2006.253.07:48:08.58#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.253.07:48:08.58#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.253.07:48:08.58#ibcon#ireg 17 cls_cnt 0 2006.253.07:48:08.58#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.253.07:48:08.58#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.253.07:48:08.58#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.253.07:48:08.58#ibcon#enter wrdev, iclass 17, count 0 2006.253.07:48:08.58#ibcon#first serial, iclass 17, count 0 2006.253.07:48:08.58#ibcon#enter sib2, iclass 17, count 0 2006.253.07:48:08.58#ibcon#flushed, iclass 17, count 0 2006.253.07:48:08.58#ibcon#about to write, iclass 17, count 0 2006.253.07:48:08.58#ibcon#wrote, iclass 17, count 0 2006.253.07:48:08.58#ibcon#about to read 3, iclass 17, count 0 2006.253.07:48:08.61#ibcon#read 3, iclass 17, count 0 2006.253.07:48:08.61#ibcon#about to read 4, iclass 17, count 0 2006.253.07:48:08.61#ibcon#read 4, iclass 17, count 0 2006.253.07:48:08.61#ibcon#about to read 5, iclass 17, count 0 2006.253.07:48:08.61#ibcon#read 5, iclass 17, count 0 2006.253.07:48:08.61#ibcon#about to read 6, iclass 17, count 0 2006.253.07:48:08.61#ibcon#read 6, iclass 17, count 0 2006.253.07:48:08.61#ibcon#end of sib2, iclass 17, count 0 2006.253.07:48:08.61#ibcon#*mode == 0, iclass 17, count 0 2006.253.07:48:08.61#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.253.07:48:08.61#ibcon#[26=FRQ=03,672.99\r\n] 2006.253.07:48:08.61#ibcon#*before write, iclass 17, count 0 2006.253.07:48:08.61#ibcon#enter sib2, iclass 17, count 0 2006.253.07:48:08.61#ibcon#flushed, iclass 17, count 0 2006.253.07:48:08.61#ibcon#about to write, iclass 17, count 0 2006.253.07:48:08.61#ibcon#wrote, iclass 17, count 0 2006.253.07:48:08.61#ibcon#about to read 3, iclass 17, count 0 2006.253.07:48:08.65#ibcon#read 3, iclass 17, count 0 2006.253.07:48:08.65#ibcon#about to read 4, iclass 17, count 0 2006.253.07:48:08.65#ibcon#read 4, iclass 17, count 0 2006.253.07:48:08.65#ibcon#about to read 5, iclass 17, count 0 2006.253.07:48:08.65#ibcon#read 5, iclass 17, count 0 2006.253.07:48:08.65#ibcon#about to read 6, iclass 17, count 0 2006.253.07:48:08.65#ibcon#read 6, iclass 17, count 0 2006.253.07:48:08.65#ibcon#end of sib2, iclass 17, count 0 2006.253.07:48:08.65#ibcon#*after write, iclass 17, count 0 2006.253.07:48:08.65#ibcon#*before return 0, iclass 17, count 0 2006.253.07:48:08.65#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.253.07:48:08.65#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.253.07:48:08.65#ibcon#about to clear, iclass 17 cls_cnt 0 2006.253.07:48:08.65#ibcon#cleared, iclass 17 cls_cnt 0 2006.253.07:48:08.65$vc4f8/va=3,6 2006.253.07:48:08.65#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.253.07:48:08.65#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.253.07:48:08.65#ibcon#ireg 11 cls_cnt 2 2006.253.07:48:08.65#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.253.07:48:08.71#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.253.07:48:08.71#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.253.07:48:08.71#ibcon#enter wrdev, iclass 19, count 2 2006.253.07:48:08.71#ibcon#first serial, iclass 19, count 2 2006.253.07:48:08.71#ibcon#enter sib2, iclass 19, count 2 2006.253.07:48:08.71#ibcon#flushed, iclass 19, count 2 2006.253.07:48:08.71#ibcon#about to write, iclass 19, count 2 2006.253.07:48:08.71#ibcon#wrote, iclass 19, count 2 2006.253.07:48:08.71#ibcon#about to read 3, iclass 19, count 2 2006.253.07:48:08.72#ibcon#read 3, iclass 19, count 2 2006.253.07:48:08.72#ibcon#about to read 4, iclass 19, count 2 2006.253.07:48:08.72#ibcon#read 4, iclass 19, count 2 2006.253.07:48:08.72#ibcon#about to read 5, iclass 19, count 2 2006.253.07:48:08.72#ibcon#read 5, iclass 19, count 2 2006.253.07:48:08.72#ibcon#about to read 6, iclass 19, count 2 2006.253.07:48:08.72#ibcon#read 6, iclass 19, count 2 2006.253.07:48:08.72#ibcon#end of sib2, iclass 19, count 2 2006.253.07:48:08.72#ibcon#*mode == 0, iclass 19, count 2 2006.253.07:48:08.72#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.253.07:48:08.72#ibcon#[25=AT03-06\r\n] 2006.253.07:48:08.72#ibcon#*before write, iclass 19, count 2 2006.253.07:48:08.72#ibcon#enter sib2, iclass 19, count 2 2006.253.07:48:08.72#ibcon#flushed, iclass 19, count 2 2006.253.07:48:08.72#ibcon#about to write, iclass 19, count 2 2006.253.07:48:08.72#ibcon#wrote, iclass 19, count 2 2006.253.07:48:08.72#ibcon#about to read 3, iclass 19, count 2 2006.253.07:48:08.75#ibcon#read 3, iclass 19, count 2 2006.253.07:48:08.75#ibcon#about to read 4, iclass 19, count 2 2006.253.07:48:08.75#ibcon#read 4, iclass 19, count 2 2006.253.07:48:08.75#ibcon#about to read 5, iclass 19, count 2 2006.253.07:48:08.75#ibcon#read 5, iclass 19, count 2 2006.253.07:48:08.75#ibcon#about to read 6, iclass 19, count 2 2006.253.07:48:08.75#ibcon#read 6, iclass 19, count 2 2006.253.07:48:08.75#ibcon#end of sib2, iclass 19, count 2 2006.253.07:48:08.75#ibcon#*after write, iclass 19, count 2 2006.253.07:48:08.75#ibcon#*before return 0, iclass 19, count 2 2006.253.07:48:08.75#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.253.07:48:08.75#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.253.07:48:08.75#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.253.07:48:08.75#ibcon#ireg 7 cls_cnt 0 2006.253.07:48:08.75#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.253.07:48:08.87#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.253.07:48:08.87#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.253.07:48:08.87#ibcon#enter wrdev, iclass 19, count 0 2006.253.07:48:08.87#ibcon#first serial, iclass 19, count 0 2006.253.07:48:08.87#ibcon#enter sib2, iclass 19, count 0 2006.253.07:48:08.87#ibcon#flushed, iclass 19, count 0 2006.253.07:48:08.87#ibcon#about to write, iclass 19, count 0 2006.253.07:48:08.87#ibcon#wrote, iclass 19, count 0 2006.253.07:48:08.87#ibcon#about to read 3, iclass 19, count 0 2006.253.07:48:08.89#ibcon#read 3, iclass 19, count 0 2006.253.07:48:08.89#ibcon#about to read 4, iclass 19, count 0 2006.253.07:48:08.89#ibcon#read 4, iclass 19, count 0 2006.253.07:48:08.89#ibcon#about to read 5, iclass 19, count 0 2006.253.07:48:08.89#ibcon#read 5, iclass 19, count 0 2006.253.07:48:08.89#ibcon#about to read 6, iclass 19, count 0 2006.253.07:48:08.89#ibcon#read 6, iclass 19, count 0 2006.253.07:48:08.89#ibcon#end of sib2, iclass 19, count 0 2006.253.07:48:08.89#ibcon#*mode == 0, iclass 19, count 0 2006.253.07:48:08.89#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.253.07:48:08.89#ibcon#[25=USB\r\n] 2006.253.07:48:08.89#ibcon#*before write, iclass 19, count 0 2006.253.07:48:08.89#ibcon#enter sib2, iclass 19, count 0 2006.253.07:48:08.89#ibcon#flushed, iclass 19, count 0 2006.253.07:48:08.89#ibcon#about to write, iclass 19, count 0 2006.253.07:48:08.89#ibcon#wrote, iclass 19, count 0 2006.253.07:48:08.89#ibcon#about to read 3, iclass 19, count 0 2006.253.07:48:08.92#ibcon#read 3, iclass 19, count 0 2006.253.07:48:08.92#ibcon#about to read 4, iclass 19, count 0 2006.253.07:48:08.92#ibcon#read 4, iclass 19, count 0 2006.253.07:48:08.92#ibcon#about to read 5, iclass 19, count 0 2006.253.07:48:08.92#ibcon#read 5, iclass 19, count 0 2006.253.07:48:08.92#ibcon#about to read 6, iclass 19, count 0 2006.253.07:48:08.92#ibcon#read 6, iclass 19, count 0 2006.253.07:48:08.92#ibcon#end of sib2, iclass 19, count 0 2006.253.07:48:08.92#ibcon#*after write, iclass 19, count 0 2006.253.07:48:08.92#ibcon#*before return 0, iclass 19, count 0 2006.253.07:48:08.92#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.253.07:48:08.92#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.253.07:48:08.92#ibcon#about to clear, iclass 19 cls_cnt 0 2006.253.07:48:08.92#ibcon#cleared, iclass 19 cls_cnt 0 2006.253.07:48:08.92$vc4f8/valo=4,832.99 2006.253.07:48:08.92#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.253.07:48:08.92#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.253.07:48:08.92#ibcon#ireg 17 cls_cnt 0 2006.253.07:48:08.92#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.253.07:48:08.92#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.253.07:48:08.92#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.253.07:48:08.92#ibcon#enter wrdev, iclass 21, count 0 2006.253.07:48:08.92#ibcon#first serial, iclass 21, count 0 2006.253.07:48:08.92#ibcon#enter sib2, iclass 21, count 0 2006.253.07:48:08.92#ibcon#flushed, iclass 21, count 0 2006.253.07:48:08.92#ibcon#about to write, iclass 21, count 0 2006.253.07:48:08.92#ibcon#wrote, iclass 21, count 0 2006.253.07:48:08.92#ibcon#about to read 3, iclass 21, count 0 2006.253.07:48:08.94#ibcon#read 3, iclass 21, count 0 2006.253.07:48:08.94#ibcon#about to read 4, iclass 21, count 0 2006.253.07:48:08.94#ibcon#read 4, iclass 21, count 0 2006.253.07:48:08.94#ibcon#about to read 5, iclass 21, count 0 2006.253.07:48:08.94#ibcon#read 5, iclass 21, count 0 2006.253.07:48:08.94#ibcon#about to read 6, iclass 21, count 0 2006.253.07:48:08.94#ibcon#read 6, iclass 21, count 0 2006.253.07:48:08.94#ibcon#end of sib2, iclass 21, count 0 2006.253.07:48:08.94#ibcon#*mode == 0, iclass 21, count 0 2006.253.07:48:08.94#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.253.07:48:08.94#ibcon#[26=FRQ=04,832.99\r\n] 2006.253.07:48:08.94#ibcon#*before write, iclass 21, count 0 2006.253.07:48:08.94#ibcon#enter sib2, iclass 21, count 0 2006.253.07:48:08.94#ibcon#flushed, iclass 21, count 0 2006.253.07:48:08.94#ibcon#about to write, iclass 21, count 0 2006.253.07:48:08.94#ibcon#wrote, iclass 21, count 0 2006.253.07:48:08.94#ibcon#about to read 3, iclass 21, count 0 2006.253.07:48:08.98#ibcon#read 3, iclass 21, count 0 2006.253.07:48:08.98#ibcon#about to read 4, iclass 21, count 0 2006.253.07:48:08.98#ibcon#read 4, iclass 21, count 0 2006.253.07:48:08.98#ibcon#about to read 5, iclass 21, count 0 2006.253.07:48:08.98#ibcon#read 5, iclass 21, count 0 2006.253.07:48:08.98#ibcon#about to read 6, iclass 21, count 0 2006.253.07:48:08.98#ibcon#read 6, iclass 21, count 0 2006.253.07:48:08.98#ibcon#end of sib2, iclass 21, count 0 2006.253.07:48:08.98#ibcon#*after write, iclass 21, count 0 2006.253.07:48:08.98#ibcon#*before return 0, iclass 21, count 0 2006.253.07:48:08.98#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.253.07:48:08.98#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.253.07:48:08.98#ibcon#about to clear, iclass 21 cls_cnt 0 2006.253.07:48:08.98#ibcon#cleared, iclass 21 cls_cnt 0 2006.253.07:48:08.98$vc4f8/va=4,7 2006.253.07:48:08.98#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.253.07:48:08.98#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.253.07:48:08.98#ibcon#ireg 11 cls_cnt 2 2006.253.07:48:08.98#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.253.07:48:09.04#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.253.07:48:09.04#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.253.07:48:09.04#ibcon#enter wrdev, iclass 23, count 2 2006.253.07:48:09.04#ibcon#first serial, iclass 23, count 2 2006.253.07:48:09.04#ibcon#enter sib2, iclass 23, count 2 2006.253.07:48:09.04#ibcon#flushed, iclass 23, count 2 2006.253.07:48:09.04#ibcon#about to write, iclass 23, count 2 2006.253.07:48:09.04#ibcon#wrote, iclass 23, count 2 2006.253.07:48:09.04#ibcon#about to read 3, iclass 23, count 2 2006.253.07:48:09.06#ibcon#read 3, iclass 23, count 2 2006.253.07:48:09.06#ibcon#about to read 4, iclass 23, count 2 2006.253.07:48:09.06#ibcon#read 4, iclass 23, count 2 2006.253.07:48:09.06#ibcon#about to read 5, iclass 23, count 2 2006.253.07:48:09.06#ibcon#read 5, iclass 23, count 2 2006.253.07:48:09.06#ibcon#about to read 6, iclass 23, count 2 2006.253.07:48:09.06#ibcon#read 6, iclass 23, count 2 2006.253.07:48:09.06#ibcon#end of sib2, iclass 23, count 2 2006.253.07:48:09.06#ibcon#*mode == 0, iclass 23, count 2 2006.253.07:48:09.06#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.253.07:48:09.06#ibcon#[25=AT04-07\r\n] 2006.253.07:48:09.06#ibcon#*before write, iclass 23, count 2 2006.253.07:48:09.06#ibcon#enter sib2, iclass 23, count 2 2006.253.07:48:09.06#ibcon#flushed, iclass 23, count 2 2006.253.07:48:09.06#ibcon#about to write, iclass 23, count 2 2006.253.07:48:09.06#ibcon#wrote, iclass 23, count 2 2006.253.07:48:09.06#ibcon#about to read 3, iclass 23, count 2 2006.253.07:48:09.09#ibcon#read 3, iclass 23, count 2 2006.253.07:48:09.09#ibcon#about to read 4, iclass 23, count 2 2006.253.07:48:09.09#ibcon#read 4, iclass 23, count 2 2006.253.07:48:09.09#ibcon#about to read 5, iclass 23, count 2 2006.253.07:48:09.09#ibcon#read 5, iclass 23, count 2 2006.253.07:48:09.09#ibcon#about to read 6, iclass 23, count 2 2006.253.07:48:09.09#ibcon#read 6, iclass 23, count 2 2006.253.07:48:09.09#ibcon#end of sib2, iclass 23, count 2 2006.253.07:48:09.09#ibcon#*after write, iclass 23, count 2 2006.253.07:48:09.09#ibcon#*before return 0, iclass 23, count 2 2006.253.07:48:09.09#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.253.07:48:09.09#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.253.07:48:09.09#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.253.07:48:09.09#ibcon#ireg 7 cls_cnt 0 2006.253.07:48:09.09#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.253.07:48:09.21#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.253.07:48:09.21#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.253.07:48:09.21#ibcon#enter wrdev, iclass 23, count 0 2006.253.07:48:09.21#ibcon#first serial, iclass 23, count 0 2006.253.07:48:09.21#ibcon#enter sib2, iclass 23, count 0 2006.253.07:48:09.21#ibcon#flushed, iclass 23, count 0 2006.253.07:48:09.21#ibcon#about to write, iclass 23, count 0 2006.253.07:48:09.21#ibcon#wrote, iclass 23, count 0 2006.253.07:48:09.21#ibcon#about to read 3, iclass 23, count 0 2006.253.07:48:09.23#ibcon#read 3, iclass 23, count 0 2006.253.07:48:09.23#ibcon#about to read 4, iclass 23, count 0 2006.253.07:48:09.23#ibcon#read 4, iclass 23, count 0 2006.253.07:48:09.23#ibcon#about to read 5, iclass 23, count 0 2006.253.07:48:09.23#ibcon#read 5, iclass 23, count 0 2006.253.07:48:09.23#ibcon#about to read 6, iclass 23, count 0 2006.253.07:48:09.23#ibcon#read 6, iclass 23, count 0 2006.253.07:48:09.23#ibcon#end of sib2, iclass 23, count 0 2006.253.07:48:09.23#ibcon#*mode == 0, iclass 23, count 0 2006.253.07:48:09.23#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.253.07:48:09.23#ibcon#[25=USB\r\n] 2006.253.07:48:09.23#ibcon#*before write, iclass 23, count 0 2006.253.07:48:09.23#ibcon#enter sib2, iclass 23, count 0 2006.253.07:48:09.23#ibcon#flushed, iclass 23, count 0 2006.253.07:48:09.23#ibcon#about to write, iclass 23, count 0 2006.253.07:48:09.23#ibcon#wrote, iclass 23, count 0 2006.253.07:48:09.23#ibcon#about to read 3, iclass 23, count 0 2006.253.07:48:09.26#ibcon#read 3, iclass 23, count 0 2006.253.07:48:09.26#ibcon#about to read 4, iclass 23, count 0 2006.253.07:48:09.26#ibcon#read 4, iclass 23, count 0 2006.253.07:48:09.26#ibcon#about to read 5, iclass 23, count 0 2006.253.07:48:09.26#ibcon#read 5, iclass 23, count 0 2006.253.07:48:09.26#ibcon#about to read 6, iclass 23, count 0 2006.253.07:48:09.26#ibcon#read 6, iclass 23, count 0 2006.253.07:48:09.26#ibcon#end of sib2, iclass 23, count 0 2006.253.07:48:09.26#ibcon#*after write, iclass 23, count 0 2006.253.07:48:09.26#ibcon#*before return 0, iclass 23, count 0 2006.253.07:48:09.26#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.253.07:48:09.26#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.253.07:48:09.26#ibcon#about to clear, iclass 23 cls_cnt 0 2006.253.07:48:09.26#ibcon#cleared, iclass 23 cls_cnt 0 2006.253.07:48:09.26$vc4f8/valo=5,652.99 2006.253.07:48:09.26#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.253.07:48:09.26#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.253.07:48:09.26#ibcon#ireg 17 cls_cnt 0 2006.253.07:48:09.26#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.253.07:48:09.26#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.253.07:48:09.26#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.253.07:48:09.26#ibcon#enter wrdev, iclass 25, count 0 2006.253.07:48:09.26#ibcon#first serial, iclass 25, count 0 2006.253.07:48:09.26#ibcon#enter sib2, iclass 25, count 0 2006.253.07:48:09.26#ibcon#flushed, iclass 25, count 0 2006.253.07:48:09.26#ibcon#about to write, iclass 25, count 0 2006.253.07:48:09.26#ibcon#wrote, iclass 25, count 0 2006.253.07:48:09.26#ibcon#about to read 3, iclass 25, count 0 2006.253.07:48:09.28#ibcon#read 3, iclass 25, count 0 2006.253.07:48:09.28#ibcon#about to read 4, iclass 25, count 0 2006.253.07:48:09.28#ibcon#read 4, iclass 25, count 0 2006.253.07:48:09.28#ibcon#about to read 5, iclass 25, count 0 2006.253.07:48:09.28#ibcon#read 5, iclass 25, count 0 2006.253.07:48:09.28#ibcon#about to read 6, iclass 25, count 0 2006.253.07:48:09.28#ibcon#read 6, iclass 25, count 0 2006.253.07:48:09.28#ibcon#end of sib2, iclass 25, count 0 2006.253.07:48:09.28#ibcon#*mode == 0, iclass 25, count 0 2006.253.07:48:09.28#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.253.07:48:09.28#ibcon#[26=FRQ=05,652.99\r\n] 2006.253.07:48:09.28#ibcon#*before write, iclass 25, count 0 2006.253.07:48:09.28#ibcon#enter sib2, iclass 25, count 0 2006.253.07:48:09.28#ibcon#flushed, iclass 25, count 0 2006.253.07:48:09.28#ibcon#about to write, iclass 25, count 0 2006.253.07:48:09.28#ibcon#wrote, iclass 25, count 0 2006.253.07:48:09.28#ibcon#about to read 3, iclass 25, count 0 2006.253.07:48:09.32#ibcon#read 3, iclass 25, count 0 2006.253.07:48:09.32#ibcon#about to read 4, iclass 25, count 0 2006.253.07:48:09.32#ibcon#read 4, iclass 25, count 0 2006.253.07:48:09.32#ibcon#about to read 5, iclass 25, count 0 2006.253.07:48:09.32#ibcon#read 5, iclass 25, count 0 2006.253.07:48:09.32#ibcon#about to read 6, iclass 25, count 0 2006.253.07:48:09.32#ibcon#read 6, iclass 25, count 0 2006.253.07:48:09.32#ibcon#end of sib2, iclass 25, count 0 2006.253.07:48:09.32#ibcon#*after write, iclass 25, count 0 2006.253.07:48:09.32#ibcon#*before return 0, iclass 25, count 0 2006.253.07:48:09.32#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.253.07:48:09.32#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.253.07:48:09.32#ibcon#about to clear, iclass 25 cls_cnt 0 2006.253.07:48:09.32#ibcon#cleared, iclass 25 cls_cnt 0 2006.253.07:48:09.32$vc4f8/va=5,7 2006.253.07:48:09.32#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.253.07:48:09.32#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.253.07:48:09.32#ibcon#ireg 11 cls_cnt 2 2006.253.07:48:09.32#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.253.07:48:09.38#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.253.07:48:09.38#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.253.07:48:09.38#ibcon#enter wrdev, iclass 27, count 2 2006.253.07:48:09.38#ibcon#first serial, iclass 27, count 2 2006.253.07:48:09.38#ibcon#enter sib2, iclass 27, count 2 2006.253.07:48:09.38#ibcon#flushed, iclass 27, count 2 2006.253.07:48:09.38#ibcon#about to write, iclass 27, count 2 2006.253.07:48:09.38#ibcon#wrote, iclass 27, count 2 2006.253.07:48:09.38#ibcon#about to read 3, iclass 27, count 2 2006.253.07:48:09.40#ibcon#read 3, iclass 27, count 2 2006.253.07:48:09.40#ibcon#about to read 4, iclass 27, count 2 2006.253.07:48:09.40#ibcon#read 4, iclass 27, count 2 2006.253.07:48:09.40#ibcon#about to read 5, iclass 27, count 2 2006.253.07:48:09.40#ibcon#read 5, iclass 27, count 2 2006.253.07:48:09.40#ibcon#about to read 6, iclass 27, count 2 2006.253.07:48:09.40#ibcon#read 6, iclass 27, count 2 2006.253.07:48:09.40#ibcon#end of sib2, iclass 27, count 2 2006.253.07:48:09.40#ibcon#*mode == 0, iclass 27, count 2 2006.253.07:48:09.40#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.253.07:48:09.40#ibcon#[25=AT05-07\r\n] 2006.253.07:48:09.40#ibcon#*before write, iclass 27, count 2 2006.253.07:48:09.40#ibcon#enter sib2, iclass 27, count 2 2006.253.07:48:09.40#ibcon#flushed, iclass 27, count 2 2006.253.07:48:09.40#ibcon#about to write, iclass 27, count 2 2006.253.07:48:09.40#ibcon#wrote, iclass 27, count 2 2006.253.07:48:09.40#ibcon#about to read 3, iclass 27, count 2 2006.253.07:48:09.43#ibcon#read 3, iclass 27, count 2 2006.253.07:48:09.43#ibcon#about to read 4, iclass 27, count 2 2006.253.07:48:09.43#ibcon#read 4, iclass 27, count 2 2006.253.07:48:09.43#ibcon#about to read 5, iclass 27, count 2 2006.253.07:48:09.43#ibcon#read 5, iclass 27, count 2 2006.253.07:48:09.43#ibcon#about to read 6, iclass 27, count 2 2006.253.07:48:09.43#ibcon#read 6, iclass 27, count 2 2006.253.07:48:09.43#ibcon#end of sib2, iclass 27, count 2 2006.253.07:48:09.43#ibcon#*after write, iclass 27, count 2 2006.253.07:48:09.43#ibcon#*before return 0, iclass 27, count 2 2006.253.07:48:09.43#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.253.07:48:09.43#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.253.07:48:09.43#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.253.07:48:09.43#ibcon#ireg 7 cls_cnt 0 2006.253.07:48:09.43#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.253.07:48:09.55#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.253.07:48:09.55#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.253.07:48:09.55#ibcon#enter wrdev, iclass 27, count 0 2006.253.07:48:09.55#ibcon#first serial, iclass 27, count 0 2006.253.07:48:09.55#ibcon#enter sib2, iclass 27, count 0 2006.253.07:48:09.55#ibcon#flushed, iclass 27, count 0 2006.253.07:48:09.55#ibcon#about to write, iclass 27, count 0 2006.253.07:48:09.55#ibcon#wrote, iclass 27, count 0 2006.253.07:48:09.55#ibcon#about to read 3, iclass 27, count 0 2006.253.07:48:09.57#ibcon#read 3, iclass 27, count 0 2006.253.07:48:09.57#ibcon#about to read 4, iclass 27, count 0 2006.253.07:48:09.57#ibcon#read 4, iclass 27, count 0 2006.253.07:48:09.57#ibcon#about to read 5, iclass 27, count 0 2006.253.07:48:09.57#ibcon#read 5, iclass 27, count 0 2006.253.07:48:09.57#ibcon#about to read 6, iclass 27, count 0 2006.253.07:48:09.57#ibcon#read 6, iclass 27, count 0 2006.253.07:48:09.57#ibcon#end of sib2, iclass 27, count 0 2006.253.07:48:09.57#ibcon#*mode == 0, iclass 27, count 0 2006.253.07:48:09.57#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.253.07:48:09.57#ibcon#[25=USB\r\n] 2006.253.07:48:09.57#ibcon#*before write, iclass 27, count 0 2006.253.07:48:09.57#ibcon#enter sib2, iclass 27, count 0 2006.253.07:48:09.57#ibcon#flushed, iclass 27, count 0 2006.253.07:48:09.57#ibcon#about to write, iclass 27, count 0 2006.253.07:48:09.57#ibcon#wrote, iclass 27, count 0 2006.253.07:48:09.57#ibcon#about to read 3, iclass 27, count 0 2006.253.07:48:09.60#ibcon#read 3, iclass 27, count 0 2006.253.07:48:09.60#ibcon#about to read 4, iclass 27, count 0 2006.253.07:48:09.60#ibcon#read 4, iclass 27, count 0 2006.253.07:48:09.60#ibcon#about to read 5, iclass 27, count 0 2006.253.07:48:09.60#ibcon#read 5, iclass 27, count 0 2006.253.07:48:09.60#ibcon#about to read 6, iclass 27, count 0 2006.253.07:48:09.60#ibcon#read 6, iclass 27, count 0 2006.253.07:48:09.60#ibcon#end of sib2, iclass 27, count 0 2006.253.07:48:09.60#ibcon#*after write, iclass 27, count 0 2006.253.07:48:09.60#ibcon#*before return 0, iclass 27, count 0 2006.253.07:48:09.60#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.253.07:48:09.60#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.253.07:48:09.60#ibcon#about to clear, iclass 27 cls_cnt 0 2006.253.07:48:09.60#ibcon#cleared, iclass 27 cls_cnt 0 2006.253.07:48:09.60$vc4f8/valo=6,772.99 2006.253.07:48:09.60#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.253.07:48:09.60#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.253.07:48:09.60#ibcon#ireg 17 cls_cnt 0 2006.253.07:48:09.60#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.253.07:48:09.60#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.253.07:48:09.60#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.253.07:48:09.60#ibcon#enter wrdev, iclass 29, count 0 2006.253.07:48:09.60#ibcon#first serial, iclass 29, count 0 2006.253.07:48:09.60#ibcon#enter sib2, iclass 29, count 0 2006.253.07:48:09.60#ibcon#flushed, iclass 29, count 0 2006.253.07:48:09.60#ibcon#about to write, iclass 29, count 0 2006.253.07:48:09.60#ibcon#wrote, iclass 29, count 0 2006.253.07:48:09.60#ibcon#about to read 3, iclass 29, count 0 2006.253.07:48:09.63#ibcon#read 3, iclass 29, count 0 2006.253.07:48:09.63#ibcon#about to read 4, iclass 29, count 0 2006.253.07:48:09.63#ibcon#read 4, iclass 29, count 0 2006.253.07:48:09.63#ibcon#about to read 5, iclass 29, count 0 2006.253.07:48:09.63#ibcon#read 5, iclass 29, count 0 2006.253.07:48:09.63#ibcon#about to read 6, iclass 29, count 0 2006.253.07:48:09.63#ibcon#read 6, iclass 29, count 0 2006.253.07:48:09.63#ibcon#end of sib2, iclass 29, count 0 2006.253.07:48:09.63#ibcon#*mode == 0, iclass 29, count 0 2006.253.07:48:09.63#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.253.07:48:09.63#ibcon#[26=FRQ=06,772.99\r\n] 2006.253.07:48:09.63#ibcon#*before write, iclass 29, count 0 2006.253.07:48:09.63#ibcon#enter sib2, iclass 29, count 0 2006.253.07:48:09.63#ibcon#flushed, iclass 29, count 0 2006.253.07:48:09.63#ibcon#about to write, iclass 29, count 0 2006.253.07:48:09.63#ibcon#wrote, iclass 29, count 0 2006.253.07:48:09.63#ibcon#about to read 3, iclass 29, count 0 2006.253.07:48:09.67#ibcon#read 3, iclass 29, count 0 2006.253.07:48:09.67#ibcon#about to read 4, iclass 29, count 0 2006.253.07:48:09.67#ibcon#read 4, iclass 29, count 0 2006.253.07:48:09.67#ibcon#about to read 5, iclass 29, count 0 2006.253.07:48:09.67#ibcon#read 5, iclass 29, count 0 2006.253.07:48:09.67#ibcon#about to read 6, iclass 29, count 0 2006.253.07:48:09.67#ibcon#read 6, iclass 29, count 0 2006.253.07:48:09.67#ibcon#end of sib2, iclass 29, count 0 2006.253.07:48:09.67#ibcon#*after write, iclass 29, count 0 2006.253.07:48:09.67#ibcon#*before return 0, iclass 29, count 0 2006.253.07:48:09.67#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.253.07:48:09.67#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.253.07:48:09.67#ibcon#about to clear, iclass 29 cls_cnt 0 2006.253.07:48:09.67#ibcon#cleared, iclass 29 cls_cnt 0 2006.253.07:48:09.67$vc4f8/va=6,7 2006.253.07:48:09.67#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.253.07:48:09.67#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.253.07:48:09.67#ibcon#ireg 11 cls_cnt 2 2006.253.07:48:09.67#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.253.07:48:09.72#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.253.07:48:09.72#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.253.07:48:09.72#ibcon#enter wrdev, iclass 31, count 2 2006.253.07:48:09.72#ibcon#first serial, iclass 31, count 2 2006.253.07:48:09.72#ibcon#enter sib2, iclass 31, count 2 2006.253.07:48:09.72#ibcon#flushed, iclass 31, count 2 2006.253.07:48:09.72#ibcon#about to write, iclass 31, count 2 2006.253.07:48:09.72#ibcon#wrote, iclass 31, count 2 2006.253.07:48:09.72#ibcon#about to read 3, iclass 31, count 2 2006.253.07:48:09.74#ibcon#read 3, iclass 31, count 2 2006.253.07:48:09.74#ibcon#about to read 4, iclass 31, count 2 2006.253.07:48:09.74#ibcon#read 4, iclass 31, count 2 2006.253.07:48:09.74#ibcon#about to read 5, iclass 31, count 2 2006.253.07:48:09.74#ibcon#read 5, iclass 31, count 2 2006.253.07:48:09.74#ibcon#about to read 6, iclass 31, count 2 2006.253.07:48:09.74#ibcon#read 6, iclass 31, count 2 2006.253.07:48:09.74#ibcon#end of sib2, iclass 31, count 2 2006.253.07:48:09.74#ibcon#*mode == 0, iclass 31, count 2 2006.253.07:48:09.74#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.253.07:48:09.74#ibcon#[25=AT06-07\r\n] 2006.253.07:48:09.74#ibcon#*before write, iclass 31, count 2 2006.253.07:48:09.74#ibcon#enter sib2, iclass 31, count 2 2006.253.07:48:09.74#ibcon#flushed, iclass 31, count 2 2006.253.07:48:09.74#ibcon#about to write, iclass 31, count 2 2006.253.07:48:09.74#ibcon#wrote, iclass 31, count 2 2006.253.07:48:09.74#ibcon#about to read 3, iclass 31, count 2 2006.253.07:48:09.77#ibcon#read 3, iclass 31, count 2 2006.253.07:48:09.77#ibcon#about to read 4, iclass 31, count 2 2006.253.07:48:09.77#ibcon#read 4, iclass 31, count 2 2006.253.07:48:09.77#ibcon#about to read 5, iclass 31, count 2 2006.253.07:48:09.77#ibcon#read 5, iclass 31, count 2 2006.253.07:48:09.77#ibcon#about to read 6, iclass 31, count 2 2006.253.07:48:09.77#ibcon#read 6, iclass 31, count 2 2006.253.07:48:09.77#ibcon#end of sib2, iclass 31, count 2 2006.253.07:48:09.77#ibcon#*after write, iclass 31, count 2 2006.253.07:48:09.77#ibcon#*before return 0, iclass 31, count 2 2006.253.07:48:09.77#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.253.07:48:09.77#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.253.07:48:09.77#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.253.07:48:09.77#ibcon#ireg 7 cls_cnt 0 2006.253.07:48:09.77#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.253.07:48:09.89#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.253.07:48:09.89#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.253.07:48:09.89#ibcon#enter wrdev, iclass 31, count 0 2006.253.07:48:09.89#ibcon#first serial, iclass 31, count 0 2006.253.07:48:09.89#ibcon#enter sib2, iclass 31, count 0 2006.253.07:48:09.89#ibcon#flushed, iclass 31, count 0 2006.253.07:48:09.89#ibcon#about to write, iclass 31, count 0 2006.253.07:48:09.89#ibcon#wrote, iclass 31, count 0 2006.253.07:48:09.89#ibcon#about to read 3, iclass 31, count 0 2006.253.07:48:09.91#ibcon#read 3, iclass 31, count 0 2006.253.07:48:09.91#ibcon#about to read 4, iclass 31, count 0 2006.253.07:48:09.91#ibcon#read 4, iclass 31, count 0 2006.253.07:48:09.91#ibcon#about to read 5, iclass 31, count 0 2006.253.07:48:09.91#ibcon#read 5, iclass 31, count 0 2006.253.07:48:09.91#ibcon#about to read 6, iclass 31, count 0 2006.253.07:48:09.91#ibcon#read 6, iclass 31, count 0 2006.253.07:48:09.91#ibcon#end of sib2, iclass 31, count 0 2006.253.07:48:09.91#ibcon#*mode == 0, iclass 31, count 0 2006.253.07:48:09.91#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.253.07:48:09.91#ibcon#[25=USB\r\n] 2006.253.07:48:09.91#ibcon#*before write, iclass 31, count 0 2006.253.07:48:09.91#ibcon#enter sib2, iclass 31, count 0 2006.253.07:48:09.91#ibcon#flushed, iclass 31, count 0 2006.253.07:48:09.91#ibcon#about to write, iclass 31, count 0 2006.253.07:48:09.91#ibcon#wrote, iclass 31, count 0 2006.253.07:48:09.91#ibcon#about to read 3, iclass 31, count 0 2006.253.07:48:09.94#ibcon#read 3, iclass 31, count 0 2006.253.07:48:09.94#ibcon#about to read 4, iclass 31, count 0 2006.253.07:48:09.94#ibcon#read 4, iclass 31, count 0 2006.253.07:48:09.94#ibcon#about to read 5, iclass 31, count 0 2006.253.07:48:09.94#ibcon#read 5, iclass 31, count 0 2006.253.07:48:09.94#ibcon#about to read 6, iclass 31, count 0 2006.253.07:48:09.94#ibcon#read 6, iclass 31, count 0 2006.253.07:48:09.94#ibcon#end of sib2, iclass 31, count 0 2006.253.07:48:09.94#ibcon#*after write, iclass 31, count 0 2006.253.07:48:09.94#ibcon#*before return 0, iclass 31, count 0 2006.253.07:48:09.94#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.253.07:48:09.94#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.253.07:48:09.94#ibcon#about to clear, iclass 31 cls_cnt 0 2006.253.07:48:09.94#ibcon#cleared, iclass 31 cls_cnt 0 2006.253.07:48:09.94$vc4f8/valo=7,832.99 2006.253.07:48:09.94#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.253.07:48:09.94#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.253.07:48:09.94#ibcon#ireg 17 cls_cnt 0 2006.253.07:48:09.94#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.253.07:48:09.94#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.253.07:48:09.94#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.253.07:48:09.94#ibcon#enter wrdev, iclass 33, count 0 2006.253.07:48:09.94#ibcon#first serial, iclass 33, count 0 2006.253.07:48:09.94#ibcon#enter sib2, iclass 33, count 0 2006.253.07:48:09.94#ibcon#flushed, iclass 33, count 0 2006.253.07:48:09.94#ibcon#about to write, iclass 33, count 0 2006.253.07:48:09.94#ibcon#wrote, iclass 33, count 0 2006.253.07:48:09.94#ibcon#about to read 3, iclass 33, count 0 2006.253.07:48:09.96#ibcon#read 3, iclass 33, count 0 2006.253.07:48:09.96#ibcon#about to read 4, iclass 33, count 0 2006.253.07:48:09.96#ibcon#read 4, iclass 33, count 0 2006.253.07:48:09.96#ibcon#about to read 5, iclass 33, count 0 2006.253.07:48:09.96#ibcon#read 5, iclass 33, count 0 2006.253.07:48:09.96#ibcon#about to read 6, iclass 33, count 0 2006.253.07:48:09.96#ibcon#read 6, iclass 33, count 0 2006.253.07:48:09.96#ibcon#end of sib2, iclass 33, count 0 2006.253.07:48:09.96#ibcon#*mode == 0, iclass 33, count 0 2006.253.07:48:09.96#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.253.07:48:09.96#ibcon#[26=FRQ=07,832.99\r\n] 2006.253.07:48:09.96#ibcon#*before write, iclass 33, count 0 2006.253.07:48:09.96#ibcon#enter sib2, iclass 33, count 0 2006.253.07:48:09.96#ibcon#flushed, iclass 33, count 0 2006.253.07:48:09.96#ibcon#about to write, iclass 33, count 0 2006.253.07:48:09.96#ibcon#wrote, iclass 33, count 0 2006.253.07:48:09.96#ibcon#about to read 3, iclass 33, count 0 2006.253.07:48:10.00#ibcon#read 3, iclass 33, count 0 2006.253.07:48:10.00#ibcon#about to read 4, iclass 33, count 0 2006.253.07:48:10.00#ibcon#read 4, iclass 33, count 0 2006.253.07:48:10.00#ibcon#about to read 5, iclass 33, count 0 2006.253.07:48:10.00#ibcon#read 5, iclass 33, count 0 2006.253.07:48:10.00#ibcon#about to read 6, iclass 33, count 0 2006.253.07:48:10.00#ibcon#read 6, iclass 33, count 0 2006.253.07:48:10.00#ibcon#end of sib2, iclass 33, count 0 2006.253.07:48:10.00#ibcon#*after write, iclass 33, count 0 2006.253.07:48:10.00#ibcon#*before return 0, iclass 33, count 0 2006.253.07:48:10.00#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.253.07:48:10.00#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.253.07:48:10.00#ibcon#about to clear, iclass 33 cls_cnt 0 2006.253.07:48:10.00#ibcon#cleared, iclass 33 cls_cnt 0 2006.253.07:48:10.00$vc4f8/va=7,7 2006.253.07:48:10.00#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.253.07:48:10.00#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.253.07:48:10.00#ibcon#ireg 11 cls_cnt 2 2006.253.07:48:10.00#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.253.07:48:10.06#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.253.07:48:10.06#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.253.07:48:10.06#ibcon#enter wrdev, iclass 35, count 2 2006.253.07:48:10.06#ibcon#first serial, iclass 35, count 2 2006.253.07:48:10.06#ibcon#enter sib2, iclass 35, count 2 2006.253.07:48:10.06#ibcon#flushed, iclass 35, count 2 2006.253.07:48:10.06#ibcon#about to write, iclass 35, count 2 2006.253.07:48:10.06#ibcon#wrote, iclass 35, count 2 2006.253.07:48:10.06#ibcon#about to read 3, iclass 35, count 2 2006.253.07:48:10.08#ibcon#read 3, iclass 35, count 2 2006.253.07:48:10.08#ibcon#about to read 4, iclass 35, count 2 2006.253.07:48:10.08#ibcon#read 4, iclass 35, count 2 2006.253.07:48:10.08#ibcon#about to read 5, iclass 35, count 2 2006.253.07:48:10.08#ibcon#read 5, iclass 35, count 2 2006.253.07:48:10.08#ibcon#about to read 6, iclass 35, count 2 2006.253.07:48:10.08#ibcon#read 6, iclass 35, count 2 2006.253.07:48:10.08#ibcon#end of sib2, iclass 35, count 2 2006.253.07:48:10.08#ibcon#*mode == 0, iclass 35, count 2 2006.253.07:48:10.08#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.253.07:48:10.08#ibcon#[25=AT07-07\r\n] 2006.253.07:48:10.08#ibcon#*before write, iclass 35, count 2 2006.253.07:48:10.08#ibcon#enter sib2, iclass 35, count 2 2006.253.07:48:10.08#ibcon#flushed, iclass 35, count 2 2006.253.07:48:10.08#ibcon#about to write, iclass 35, count 2 2006.253.07:48:10.08#ibcon#wrote, iclass 35, count 2 2006.253.07:48:10.08#ibcon#about to read 3, iclass 35, count 2 2006.253.07:48:10.11#ibcon#read 3, iclass 35, count 2 2006.253.07:48:10.11#ibcon#about to read 4, iclass 35, count 2 2006.253.07:48:10.11#ibcon#read 4, iclass 35, count 2 2006.253.07:48:10.11#ibcon#about to read 5, iclass 35, count 2 2006.253.07:48:10.11#ibcon#read 5, iclass 35, count 2 2006.253.07:48:10.11#ibcon#about to read 6, iclass 35, count 2 2006.253.07:48:10.11#ibcon#read 6, iclass 35, count 2 2006.253.07:48:10.11#ibcon#end of sib2, iclass 35, count 2 2006.253.07:48:10.11#ibcon#*after write, iclass 35, count 2 2006.253.07:48:10.11#ibcon#*before return 0, iclass 35, count 2 2006.253.07:48:10.11#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.253.07:48:10.11#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.253.07:48:10.11#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.253.07:48:10.11#ibcon#ireg 7 cls_cnt 0 2006.253.07:48:10.11#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.253.07:48:10.23#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.253.07:48:10.23#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.253.07:48:10.23#ibcon#enter wrdev, iclass 35, count 0 2006.253.07:48:10.23#ibcon#first serial, iclass 35, count 0 2006.253.07:48:10.23#ibcon#enter sib2, iclass 35, count 0 2006.253.07:48:10.23#ibcon#flushed, iclass 35, count 0 2006.253.07:48:10.23#ibcon#about to write, iclass 35, count 0 2006.253.07:48:10.23#ibcon#wrote, iclass 35, count 0 2006.253.07:48:10.23#ibcon#about to read 3, iclass 35, count 0 2006.253.07:48:10.25#ibcon#read 3, iclass 35, count 0 2006.253.07:48:10.25#ibcon#about to read 4, iclass 35, count 0 2006.253.07:48:10.25#ibcon#read 4, iclass 35, count 0 2006.253.07:48:10.25#ibcon#about to read 5, iclass 35, count 0 2006.253.07:48:10.25#ibcon#read 5, iclass 35, count 0 2006.253.07:48:10.25#ibcon#about to read 6, iclass 35, count 0 2006.253.07:48:10.25#ibcon#read 6, iclass 35, count 0 2006.253.07:48:10.25#ibcon#end of sib2, iclass 35, count 0 2006.253.07:48:10.25#ibcon#*mode == 0, iclass 35, count 0 2006.253.07:48:10.25#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.253.07:48:10.25#ibcon#[25=USB\r\n] 2006.253.07:48:10.25#ibcon#*before write, iclass 35, count 0 2006.253.07:48:10.25#ibcon#enter sib2, iclass 35, count 0 2006.253.07:48:10.25#ibcon#flushed, iclass 35, count 0 2006.253.07:48:10.25#ibcon#about to write, iclass 35, count 0 2006.253.07:48:10.25#ibcon#wrote, iclass 35, count 0 2006.253.07:48:10.25#ibcon#about to read 3, iclass 35, count 0 2006.253.07:48:10.28#ibcon#read 3, iclass 35, count 0 2006.253.07:48:10.28#ibcon#about to read 4, iclass 35, count 0 2006.253.07:48:10.28#ibcon#read 4, iclass 35, count 0 2006.253.07:48:10.28#ibcon#about to read 5, iclass 35, count 0 2006.253.07:48:10.28#ibcon#read 5, iclass 35, count 0 2006.253.07:48:10.28#ibcon#about to read 6, iclass 35, count 0 2006.253.07:48:10.28#ibcon#read 6, iclass 35, count 0 2006.253.07:48:10.28#ibcon#end of sib2, iclass 35, count 0 2006.253.07:48:10.28#ibcon#*after write, iclass 35, count 0 2006.253.07:48:10.28#ibcon#*before return 0, iclass 35, count 0 2006.253.07:48:10.28#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.253.07:48:10.28#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.253.07:48:10.28#ibcon#about to clear, iclass 35 cls_cnt 0 2006.253.07:48:10.28#ibcon#cleared, iclass 35 cls_cnt 0 2006.253.07:48:10.28$vc4f8/valo=8,852.99 2006.253.07:48:10.28#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.253.07:48:10.28#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.253.07:48:10.28#ibcon#ireg 17 cls_cnt 0 2006.253.07:48:10.28#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.253.07:48:10.28#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.253.07:48:10.28#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.253.07:48:10.28#ibcon#enter wrdev, iclass 37, count 0 2006.253.07:48:10.28#ibcon#first serial, iclass 37, count 0 2006.253.07:48:10.28#ibcon#enter sib2, iclass 37, count 0 2006.253.07:48:10.28#ibcon#flushed, iclass 37, count 0 2006.253.07:48:10.28#ibcon#about to write, iclass 37, count 0 2006.253.07:48:10.28#ibcon#wrote, iclass 37, count 0 2006.253.07:48:10.28#ibcon#about to read 3, iclass 37, count 0 2006.253.07:48:10.30#ibcon#read 3, iclass 37, count 0 2006.253.07:48:10.30#ibcon#about to read 4, iclass 37, count 0 2006.253.07:48:10.30#ibcon#read 4, iclass 37, count 0 2006.253.07:48:10.30#ibcon#about to read 5, iclass 37, count 0 2006.253.07:48:10.30#ibcon#read 5, iclass 37, count 0 2006.253.07:48:10.30#ibcon#about to read 6, iclass 37, count 0 2006.253.07:48:10.30#ibcon#read 6, iclass 37, count 0 2006.253.07:48:10.30#ibcon#end of sib2, iclass 37, count 0 2006.253.07:48:10.30#ibcon#*mode == 0, iclass 37, count 0 2006.253.07:48:10.30#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.253.07:48:10.30#ibcon#[26=FRQ=08,852.99\r\n] 2006.253.07:48:10.30#ibcon#*before write, iclass 37, count 0 2006.253.07:48:10.30#ibcon#enter sib2, iclass 37, count 0 2006.253.07:48:10.30#ibcon#flushed, iclass 37, count 0 2006.253.07:48:10.30#ibcon#about to write, iclass 37, count 0 2006.253.07:48:10.30#ibcon#wrote, iclass 37, count 0 2006.253.07:48:10.30#ibcon#about to read 3, iclass 37, count 0 2006.253.07:48:10.34#ibcon#read 3, iclass 37, count 0 2006.253.07:48:10.34#ibcon#about to read 4, iclass 37, count 0 2006.253.07:48:10.34#ibcon#read 4, iclass 37, count 0 2006.253.07:48:10.34#ibcon#about to read 5, iclass 37, count 0 2006.253.07:48:10.34#ibcon#read 5, iclass 37, count 0 2006.253.07:48:10.34#ibcon#about to read 6, iclass 37, count 0 2006.253.07:48:10.34#ibcon#read 6, iclass 37, count 0 2006.253.07:48:10.34#ibcon#end of sib2, iclass 37, count 0 2006.253.07:48:10.34#ibcon#*after write, iclass 37, count 0 2006.253.07:48:10.34#ibcon#*before return 0, iclass 37, count 0 2006.253.07:48:10.34#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.253.07:48:10.34#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.253.07:48:10.34#ibcon#about to clear, iclass 37 cls_cnt 0 2006.253.07:48:10.34#ibcon#cleared, iclass 37 cls_cnt 0 2006.253.07:48:10.34$vc4f8/va=8,7 2006.253.07:48:10.34#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.253.07:48:10.34#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.253.07:48:10.34#ibcon#ireg 11 cls_cnt 2 2006.253.07:48:10.34#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.253.07:48:10.41#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.253.07:48:10.41#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.253.07:48:10.41#ibcon#enter wrdev, iclass 39, count 2 2006.253.07:48:10.41#ibcon#first serial, iclass 39, count 2 2006.253.07:48:10.41#ibcon#enter sib2, iclass 39, count 2 2006.253.07:48:10.41#ibcon#flushed, iclass 39, count 2 2006.253.07:48:10.41#ibcon#about to write, iclass 39, count 2 2006.253.07:48:10.41#ibcon#wrote, iclass 39, count 2 2006.253.07:48:10.41#ibcon#about to read 3, iclass 39, count 2 2006.253.07:48:10.42#ibcon#read 3, iclass 39, count 2 2006.253.07:48:10.42#ibcon#about to read 4, iclass 39, count 2 2006.253.07:48:10.42#ibcon#read 4, iclass 39, count 2 2006.253.07:48:10.42#ibcon#about to read 5, iclass 39, count 2 2006.253.07:48:10.42#ibcon#read 5, iclass 39, count 2 2006.253.07:48:10.42#ibcon#about to read 6, iclass 39, count 2 2006.253.07:48:10.42#ibcon#read 6, iclass 39, count 2 2006.253.07:48:10.42#ibcon#end of sib2, iclass 39, count 2 2006.253.07:48:10.42#ibcon#*mode == 0, iclass 39, count 2 2006.253.07:48:10.42#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.253.07:48:10.42#ibcon#[25=AT08-07\r\n] 2006.253.07:48:10.42#ibcon#*before write, iclass 39, count 2 2006.253.07:48:10.42#ibcon#enter sib2, iclass 39, count 2 2006.253.07:48:10.42#ibcon#flushed, iclass 39, count 2 2006.253.07:48:10.42#ibcon#about to write, iclass 39, count 2 2006.253.07:48:10.42#ibcon#wrote, iclass 39, count 2 2006.253.07:48:10.42#ibcon#about to read 3, iclass 39, count 2 2006.253.07:48:10.45#ibcon#read 3, iclass 39, count 2 2006.253.07:48:10.45#ibcon#about to read 4, iclass 39, count 2 2006.253.07:48:10.45#ibcon#read 4, iclass 39, count 2 2006.253.07:48:10.45#ibcon#about to read 5, iclass 39, count 2 2006.253.07:48:10.45#ibcon#read 5, iclass 39, count 2 2006.253.07:48:10.45#ibcon#about to read 6, iclass 39, count 2 2006.253.07:48:10.45#ibcon#read 6, iclass 39, count 2 2006.253.07:48:10.45#ibcon#end of sib2, iclass 39, count 2 2006.253.07:48:10.45#ibcon#*after write, iclass 39, count 2 2006.253.07:48:10.45#ibcon#*before return 0, iclass 39, count 2 2006.253.07:48:10.45#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.253.07:48:10.45#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.253.07:48:10.45#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.253.07:48:10.45#ibcon#ireg 7 cls_cnt 0 2006.253.07:48:10.45#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.253.07:48:10.57#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.253.07:48:10.57#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.253.07:48:10.57#ibcon#enter wrdev, iclass 39, count 0 2006.253.07:48:10.57#ibcon#first serial, iclass 39, count 0 2006.253.07:48:10.57#ibcon#enter sib2, iclass 39, count 0 2006.253.07:48:10.57#ibcon#flushed, iclass 39, count 0 2006.253.07:48:10.57#ibcon#about to write, iclass 39, count 0 2006.253.07:48:10.57#ibcon#wrote, iclass 39, count 0 2006.253.07:48:10.57#ibcon#about to read 3, iclass 39, count 0 2006.253.07:48:10.59#ibcon#read 3, iclass 39, count 0 2006.253.07:48:10.59#ibcon#about to read 4, iclass 39, count 0 2006.253.07:48:10.59#ibcon#read 4, iclass 39, count 0 2006.253.07:48:10.59#ibcon#about to read 5, iclass 39, count 0 2006.253.07:48:10.59#ibcon#read 5, iclass 39, count 0 2006.253.07:48:10.59#ibcon#about to read 6, iclass 39, count 0 2006.253.07:48:10.59#ibcon#read 6, iclass 39, count 0 2006.253.07:48:10.59#ibcon#end of sib2, iclass 39, count 0 2006.253.07:48:10.59#ibcon#*mode == 0, iclass 39, count 0 2006.253.07:48:10.59#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.253.07:48:10.59#ibcon#[25=USB\r\n] 2006.253.07:48:10.59#ibcon#*before write, iclass 39, count 0 2006.253.07:48:10.59#ibcon#enter sib2, iclass 39, count 0 2006.253.07:48:10.59#ibcon#flushed, iclass 39, count 0 2006.253.07:48:10.59#ibcon#about to write, iclass 39, count 0 2006.253.07:48:10.59#ibcon#wrote, iclass 39, count 0 2006.253.07:48:10.59#ibcon#about to read 3, iclass 39, count 0 2006.253.07:48:10.62#ibcon#read 3, iclass 39, count 0 2006.253.07:48:10.62#ibcon#about to read 4, iclass 39, count 0 2006.253.07:48:10.62#ibcon#read 4, iclass 39, count 0 2006.253.07:48:10.62#ibcon#about to read 5, iclass 39, count 0 2006.253.07:48:10.62#ibcon#read 5, iclass 39, count 0 2006.253.07:48:10.62#ibcon#about to read 6, iclass 39, count 0 2006.253.07:48:10.62#ibcon#read 6, iclass 39, count 0 2006.253.07:48:10.62#ibcon#end of sib2, iclass 39, count 0 2006.253.07:48:10.62#ibcon#*after write, iclass 39, count 0 2006.253.07:48:10.62#ibcon#*before return 0, iclass 39, count 0 2006.253.07:48:10.62#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.253.07:48:10.62#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.253.07:48:10.62#ibcon#about to clear, iclass 39 cls_cnt 0 2006.253.07:48:10.62#ibcon#cleared, iclass 39 cls_cnt 0 2006.253.07:48:10.62$vc4f8/vblo=1,632.99 2006.253.07:48:10.62#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.253.07:48:10.62#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.253.07:48:10.62#ibcon#ireg 17 cls_cnt 0 2006.253.07:48:10.62#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.253.07:48:10.62#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.253.07:48:10.62#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.253.07:48:10.62#ibcon#enter wrdev, iclass 3, count 0 2006.253.07:48:10.62#ibcon#first serial, iclass 3, count 0 2006.253.07:48:10.62#ibcon#enter sib2, iclass 3, count 0 2006.253.07:48:10.62#ibcon#flushed, iclass 3, count 0 2006.253.07:48:10.62#ibcon#about to write, iclass 3, count 0 2006.253.07:48:10.62#ibcon#wrote, iclass 3, count 0 2006.253.07:48:10.62#ibcon#about to read 3, iclass 3, count 0 2006.253.07:48:10.64#ibcon#read 3, iclass 3, count 0 2006.253.07:48:10.64#ibcon#about to read 4, iclass 3, count 0 2006.253.07:48:10.64#ibcon#read 4, iclass 3, count 0 2006.253.07:48:10.64#ibcon#about to read 5, iclass 3, count 0 2006.253.07:48:10.64#ibcon#read 5, iclass 3, count 0 2006.253.07:48:10.64#ibcon#about to read 6, iclass 3, count 0 2006.253.07:48:10.64#ibcon#read 6, iclass 3, count 0 2006.253.07:48:10.64#ibcon#end of sib2, iclass 3, count 0 2006.253.07:48:10.64#ibcon#*mode == 0, iclass 3, count 0 2006.253.07:48:10.64#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.253.07:48:10.64#ibcon#[28=FRQ=01,632.99\r\n] 2006.253.07:48:10.64#ibcon#*before write, iclass 3, count 0 2006.253.07:48:10.64#ibcon#enter sib2, iclass 3, count 0 2006.253.07:48:10.64#ibcon#flushed, iclass 3, count 0 2006.253.07:48:10.64#ibcon#about to write, iclass 3, count 0 2006.253.07:48:10.64#ibcon#wrote, iclass 3, count 0 2006.253.07:48:10.64#ibcon#about to read 3, iclass 3, count 0 2006.253.07:48:10.68#ibcon#read 3, iclass 3, count 0 2006.253.07:48:10.68#ibcon#about to read 4, iclass 3, count 0 2006.253.07:48:10.68#ibcon#read 4, iclass 3, count 0 2006.253.07:48:10.68#ibcon#about to read 5, iclass 3, count 0 2006.253.07:48:10.68#ibcon#read 5, iclass 3, count 0 2006.253.07:48:10.68#ibcon#about to read 6, iclass 3, count 0 2006.253.07:48:10.68#ibcon#read 6, iclass 3, count 0 2006.253.07:48:10.68#ibcon#end of sib2, iclass 3, count 0 2006.253.07:48:10.68#ibcon#*after write, iclass 3, count 0 2006.253.07:48:10.68#ibcon#*before return 0, iclass 3, count 0 2006.253.07:48:10.68#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.253.07:48:10.68#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.253.07:48:10.68#ibcon#about to clear, iclass 3 cls_cnt 0 2006.253.07:48:10.68#ibcon#cleared, iclass 3 cls_cnt 0 2006.253.07:48:10.68$vc4f8/vb=1,4 2006.253.07:48:10.68#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.253.07:48:10.68#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.253.07:48:10.68#ibcon#ireg 11 cls_cnt 2 2006.253.07:48:10.68#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.253.07:48:10.68#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.253.07:48:10.68#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.253.07:48:10.68#ibcon#enter wrdev, iclass 5, count 2 2006.253.07:48:10.68#ibcon#first serial, iclass 5, count 2 2006.253.07:48:10.68#ibcon#enter sib2, iclass 5, count 2 2006.253.07:48:10.68#ibcon#flushed, iclass 5, count 2 2006.253.07:48:10.68#ibcon#about to write, iclass 5, count 2 2006.253.07:48:10.68#ibcon#wrote, iclass 5, count 2 2006.253.07:48:10.68#ibcon#about to read 3, iclass 5, count 2 2006.253.07:48:10.70#ibcon#read 3, iclass 5, count 2 2006.253.07:48:10.70#ibcon#about to read 4, iclass 5, count 2 2006.253.07:48:10.70#ibcon#read 4, iclass 5, count 2 2006.253.07:48:10.70#ibcon#about to read 5, iclass 5, count 2 2006.253.07:48:10.70#ibcon#read 5, iclass 5, count 2 2006.253.07:48:10.70#ibcon#about to read 6, iclass 5, count 2 2006.253.07:48:10.70#ibcon#read 6, iclass 5, count 2 2006.253.07:48:10.70#ibcon#end of sib2, iclass 5, count 2 2006.253.07:48:10.70#ibcon#*mode == 0, iclass 5, count 2 2006.253.07:48:10.70#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.253.07:48:10.70#ibcon#[27=AT01-04\r\n] 2006.253.07:48:10.70#ibcon#*before write, iclass 5, count 2 2006.253.07:48:10.70#ibcon#enter sib2, iclass 5, count 2 2006.253.07:48:10.70#ibcon#flushed, iclass 5, count 2 2006.253.07:48:10.70#ibcon#about to write, iclass 5, count 2 2006.253.07:48:10.70#ibcon#wrote, iclass 5, count 2 2006.253.07:48:10.70#ibcon#about to read 3, iclass 5, count 2 2006.253.07:48:10.73#ibcon#read 3, iclass 5, count 2 2006.253.07:48:10.73#ibcon#about to read 4, iclass 5, count 2 2006.253.07:48:10.73#ibcon#read 4, iclass 5, count 2 2006.253.07:48:10.73#ibcon#about to read 5, iclass 5, count 2 2006.253.07:48:10.73#ibcon#read 5, iclass 5, count 2 2006.253.07:48:10.73#ibcon#about to read 6, iclass 5, count 2 2006.253.07:48:10.73#ibcon#read 6, iclass 5, count 2 2006.253.07:48:10.73#ibcon#end of sib2, iclass 5, count 2 2006.253.07:48:10.73#ibcon#*after write, iclass 5, count 2 2006.253.07:48:10.73#ibcon#*before return 0, iclass 5, count 2 2006.253.07:48:10.73#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.253.07:48:10.73#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.253.07:48:10.73#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.253.07:48:10.73#ibcon#ireg 7 cls_cnt 0 2006.253.07:48:10.73#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.253.07:48:10.85#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.253.07:48:10.85#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.253.07:48:10.85#ibcon#enter wrdev, iclass 5, count 0 2006.253.07:48:10.85#ibcon#first serial, iclass 5, count 0 2006.253.07:48:10.85#ibcon#enter sib2, iclass 5, count 0 2006.253.07:48:10.85#ibcon#flushed, iclass 5, count 0 2006.253.07:48:10.85#ibcon#about to write, iclass 5, count 0 2006.253.07:48:10.85#ibcon#wrote, iclass 5, count 0 2006.253.07:48:10.85#ibcon#about to read 3, iclass 5, count 0 2006.253.07:48:10.87#ibcon#read 3, iclass 5, count 0 2006.253.07:48:10.87#ibcon#about to read 4, iclass 5, count 0 2006.253.07:48:10.87#ibcon#read 4, iclass 5, count 0 2006.253.07:48:10.87#ibcon#about to read 5, iclass 5, count 0 2006.253.07:48:10.87#ibcon#read 5, iclass 5, count 0 2006.253.07:48:10.87#ibcon#about to read 6, iclass 5, count 0 2006.253.07:48:10.87#ibcon#read 6, iclass 5, count 0 2006.253.07:48:10.87#ibcon#end of sib2, iclass 5, count 0 2006.253.07:48:10.87#ibcon#*mode == 0, iclass 5, count 0 2006.253.07:48:10.87#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.253.07:48:10.87#ibcon#[27=USB\r\n] 2006.253.07:48:10.87#ibcon#*before write, iclass 5, count 0 2006.253.07:48:10.87#ibcon#enter sib2, iclass 5, count 0 2006.253.07:48:10.87#ibcon#flushed, iclass 5, count 0 2006.253.07:48:10.87#ibcon#about to write, iclass 5, count 0 2006.253.07:48:10.87#ibcon#wrote, iclass 5, count 0 2006.253.07:48:10.87#ibcon#about to read 3, iclass 5, count 0 2006.253.07:48:10.90#ibcon#read 3, iclass 5, count 0 2006.253.07:48:10.90#ibcon#about to read 4, iclass 5, count 0 2006.253.07:48:10.90#ibcon#read 4, iclass 5, count 0 2006.253.07:48:10.90#ibcon#about to read 5, iclass 5, count 0 2006.253.07:48:10.90#ibcon#read 5, iclass 5, count 0 2006.253.07:48:10.90#ibcon#about to read 6, iclass 5, count 0 2006.253.07:48:10.90#ibcon#read 6, iclass 5, count 0 2006.253.07:48:10.90#ibcon#end of sib2, iclass 5, count 0 2006.253.07:48:10.90#ibcon#*after write, iclass 5, count 0 2006.253.07:48:10.90#ibcon#*before return 0, iclass 5, count 0 2006.253.07:48:10.90#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.253.07:48:10.90#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.253.07:48:10.90#ibcon#about to clear, iclass 5 cls_cnt 0 2006.253.07:48:10.90#ibcon#cleared, iclass 5 cls_cnt 0 2006.253.07:48:10.90$vc4f8/vblo=2,640.99 2006.253.07:48:10.90#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.253.07:48:10.90#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.253.07:48:10.90#ibcon#ireg 17 cls_cnt 0 2006.253.07:48:10.90#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.253.07:48:10.90#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.253.07:48:10.90#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.253.07:48:10.90#ibcon#enter wrdev, iclass 7, count 0 2006.253.07:48:10.90#ibcon#first serial, iclass 7, count 0 2006.253.07:48:10.90#ibcon#enter sib2, iclass 7, count 0 2006.253.07:48:10.90#ibcon#flushed, iclass 7, count 0 2006.253.07:48:10.90#ibcon#about to write, iclass 7, count 0 2006.253.07:48:10.90#ibcon#wrote, iclass 7, count 0 2006.253.07:48:10.90#ibcon#about to read 3, iclass 7, count 0 2006.253.07:48:10.92#ibcon#read 3, iclass 7, count 0 2006.253.07:48:10.92#ibcon#about to read 4, iclass 7, count 0 2006.253.07:48:10.92#ibcon#read 4, iclass 7, count 0 2006.253.07:48:10.92#ibcon#about to read 5, iclass 7, count 0 2006.253.07:48:10.92#ibcon#read 5, iclass 7, count 0 2006.253.07:48:10.92#ibcon#about to read 6, iclass 7, count 0 2006.253.07:48:10.92#ibcon#read 6, iclass 7, count 0 2006.253.07:48:10.92#ibcon#end of sib2, iclass 7, count 0 2006.253.07:48:10.92#ibcon#*mode == 0, iclass 7, count 0 2006.253.07:48:10.92#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.253.07:48:10.92#ibcon#[28=FRQ=02,640.99\r\n] 2006.253.07:48:10.92#ibcon#*before write, iclass 7, count 0 2006.253.07:48:10.92#ibcon#enter sib2, iclass 7, count 0 2006.253.07:48:10.92#ibcon#flushed, iclass 7, count 0 2006.253.07:48:10.92#ibcon#about to write, iclass 7, count 0 2006.253.07:48:10.92#ibcon#wrote, iclass 7, count 0 2006.253.07:48:10.92#ibcon#about to read 3, iclass 7, count 0 2006.253.07:48:10.96#ibcon#read 3, iclass 7, count 0 2006.253.07:48:10.96#ibcon#about to read 4, iclass 7, count 0 2006.253.07:48:10.96#ibcon#read 4, iclass 7, count 0 2006.253.07:48:10.96#ibcon#about to read 5, iclass 7, count 0 2006.253.07:48:10.96#ibcon#read 5, iclass 7, count 0 2006.253.07:48:10.96#ibcon#about to read 6, iclass 7, count 0 2006.253.07:48:10.96#ibcon#read 6, iclass 7, count 0 2006.253.07:48:10.96#ibcon#end of sib2, iclass 7, count 0 2006.253.07:48:10.96#ibcon#*after write, iclass 7, count 0 2006.253.07:48:10.96#ibcon#*before return 0, iclass 7, count 0 2006.253.07:48:10.96#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.253.07:48:10.96#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.253.07:48:10.96#ibcon#about to clear, iclass 7 cls_cnt 0 2006.253.07:48:10.96#ibcon#cleared, iclass 7 cls_cnt 0 2006.253.07:48:10.97$vc4f8/vb=2,5 2006.253.07:48:10.97#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.253.07:48:10.97#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.253.07:48:10.97#ibcon#ireg 11 cls_cnt 2 2006.253.07:48:10.97#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.253.07:48:11.01#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.253.07:48:11.01#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.253.07:48:11.01#ibcon#enter wrdev, iclass 11, count 2 2006.253.07:48:11.01#ibcon#first serial, iclass 11, count 2 2006.253.07:48:11.01#ibcon#enter sib2, iclass 11, count 2 2006.253.07:48:11.01#ibcon#flushed, iclass 11, count 2 2006.253.07:48:11.01#ibcon#about to write, iclass 11, count 2 2006.253.07:48:11.01#ibcon#wrote, iclass 11, count 2 2006.253.07:48:11.01#ibcon#about to read 3, iclass 11, count 2 2006.253.07:48:11.03#ibcon#read 3, iclass 11, count 2 2006.253.07:48:11.03#ibcon#about to read 4, iclass 11, count 2 2006.253.07:48:11.03#ibcon#read 4, iclass 11, count 2 2006.253.07:48:11.03#ibcon#about to read 5, iclass 11, count 2 2006.253.07:48:11.03#ibcon#read 5, iclass 11, count 2 2006.253.07:48:11.03#ibcon#about to read 6, iclass 11, count 2 2006.253.07:48:11.03#ibcon#read 6, iclass 11, count 2 2006.253.07:48:11.03#ibcon#end of sib2, iclass 11, count 2 2006.253.07:48:11.03#ibcon#*mode == 0, iclass 11, count 2 2006.253.07:48:11.03#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.253.07:48:11.03#ibcon#[27=AT02-05\r\n] 2006.253.07:48:11.03#ibcon#*before write, iclass 11, count 2 2006.253.07:48:11.03#ibcon#enter sib2, iclass 11, count 2 2006.253.07:48:11.03#ibcon#flushed, iclass 11, count 2 2006.253.07:48:11.03#ibcon#about to write, iclass 11, count 2 2006.253.07:48:11.03#ibcon#wrote, iclass 11, count 2 2006.253.07:48:11.03#ibcon#about to read 3, iclass 11, count 2 2006.253.07:48:11.06#ibcon#read 3, iclass 11, count 2 2006.253.07:48:11.06#ibcon#about to read 4, iclass 11, count 2 2006.253.07:48:11.06#ibcon#read 4, iclass 11, count 2 2006.253.07:48:11.06#ibcon#about to read 5, iclass 11, count 2 2006.253.07:48:11.06#ibcon#read 5, iclass 11, count 2 2006.253.07:48:11.06#ibcon#about to read 6, iclass 11, count 2 2006.253.07:48:11.06#ibcon#read 6, iclass 11, count 2 2006.253.07:48:11.06#ibcon#end of sib2, iclass 11, count 2 2006.253.07:48:11.06#ibcon#*after write, iclass 11, count 2 2006.253.07:48:11.06#ibcon#*before return 0, iclass 11, count 2 2006.253.07:48:11.06#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.253.07:48:11.06#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.253.07:48:11.06#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.253.07:48:11.06#ibcon#ireg 7 cls_cnt 0 2006.253.07:48:11.06#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.253.07:48:11.18#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.253.07:48:11.18#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.253.07:48:11.18#ibcon#enter wrdev, iclass 11, count 0 2006.253.07:48:11.18#ibcon#first serial, iclass 11, count 0 2006.253.07:48:11.18#ibcon#enter sib2, iclass 11, count 0 2006.253.07:48:11.18#ibcon#flushed, iclass 11, count 0 2006.253.07:48:11.18#ibcon#about to write, iclass 11, count 0 2006.253.07:48:11.18#ibcon#wrote, iclass 11, count 0 2006.253.07:48:11.18#ibcon#about to read 3, iclass 11, count 0 2006.253.07:48:11.20#ibcon#read 3, iclass 11, count 0 2006.253.07:48:11.20#ibcon#about to read 4, iclass 11, count 0 2006.253.07:48:11.20#ibcon#read 4, iclass 11, count 0 2006.253.07:48:11.20#ibcon#about to read 5, iclass 11, count 0 2006.253.07:48:11.20#ibcon#read 5, iclass 11, count 0 2006.253.07:48:11.20#ibcon#about to read 6, iclass 11, count 0 2006.253.07:48:11.20#ibcon#read 6, iclass 11, count 0 2006.253.07:48:11.20#ibcon#end of sib2, iclass 11, count 0 2006.253.07:48:11.20#ibcon#*mode == 0, iclass 11, count 0 2006.253.07:48:11.20#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.253.07:48:11.20#ibcon#[27=USB\r\n] 2006.253.07:48:11.20#ibcon#*before write, iclass 11, count 0 2006.253.07:48:11.20#ibcon#enter sib2, iclass 11, count 0 2006.253.07:48:11.20#ibcon#flushed, iclass 11, count 0 2006.253.07:48:11.20#ibcon#about to write, iclass 11, count 0 2006.253.07:48:11.20#ibcon#wrote, iclass 11, count 0 2006.253.07:48:11.20#ibcon#about to read 3, iclass 11, count 0 2006.253.07:48:11.23#ibcon#read 3, iclass 11, count 0 2006.253.07:48:11.23#ibcon#about to read 4, iclass 11, count 0 2006.253.07:48:11.23#ibcon#read 4, iclass 11, count 0 2006.253.07:48:11.23#ibcon#about to read 5, iclass 11, count 0 2006.253.07:48:11.23#ibcon#read 5, iclass 11, count 0 2006.253.07:48:11.23#ibcon#about to read 6, iclass 11, count 0 2006.253.07:48:11.23#ibcon#read 6, iclass 11, count 0 2006.253.07:48:11.23#ibcon#end of sib2, iclass 11, count 0 2006.253.07:48:11.23#ibcon#*after write, iclass 11, count 0 2006.253.07:48:11.23#ibcon#*before return 0, iclass 11, count 0 2006.253.07:48:11.23#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.253.07:48:11.23#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.253.07:48:11.23#ibcon#about to clear, iclass 11 cls_cnt 0 2006.253.07:48:11.23#ibcon#cleared, iclass 11 cls_cnt 0 2006.253.07:48:11.23$vc4f8/vblo=3,656.99 2006.253.07:48:11.23#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.253.07:48:11.23#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.253.07:48:11.23#ibcon#ireg 17 cls_cnt 0 2006.253.07:48:11.23#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.253.07:48:11.23#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.253.07:48:11.23#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.253.07:48:11.23#ibcon#enter wrdev, iclass 13, count 0 2006.253.07:48:11.23#ibcon#first serial, iclass 13, count 0 2006.253.07:48:11.23#ibcon#enter sib2, iclass 13, count 0 2006.253.07:48:11.23#ibcon#flushed, iclass 13, count 0 2006.253.07:48:11.23#ibcon#about to write, iclass 13, count 0 2006.253.07:48:11.23#ibcon#wrote, iclass 13, count 0 2006.253.07:48:11.23#ibcon#about to read 3, iclass 13, count 0 2006.253.07:48:11.25#ibcon#read 3, iclass 13, count 0 2006.253.07:48:11.25#ibcon#about to read 4, iclass 13, count 0 2006.253.07:48:11.25#ibcon#read 4, iclass 13, count 0 2006.253.07:48:11.25#ibcon#about to read 5, iclass 13, count 0 2006.253.07:48:11.25#ibcon#read 5, iclass 13, count 0 2006.253.07:48:11.25#ibcon#about to read 6, iclass 13, count 0 2006.253.07:48:11.25#ibcon#read 6, iclass 13, count 0 2006.253.07:48:11.25#ibcon#end of sib2, iclass 13, count 0 2006.253.07:48:11.25#ibcon#*mode == 0, iclass 13, count 0 2006.253.07:48:11.25#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.253.07:48:11.25#ibcon#[28=FRQ=03,656.99\r\n] 2006.253.07:48:11.25#ibcon#*before write, iclass 13, count 0 2006.253.07:48:11.25#ibcon#enter sib2, iclass 13, count 0 2006.253.07:48:11.25#ibcon#flushed, iclass 13, count 0 2006.253.07:48:11.25#ibcon#about to write, iclass 13, count 0 2006.253.07:48:11.25#ibcon#wrote, iclass 13, count 0 2006.253.07:48:11.25#ibcon#about to read 3, iclass 13, count 0 2006.253.07:48:11.29#ibcon#read 3, iclass 13, count 0 2006.253.07:48:11.29#ibcon#about to read 4, iclass 13, count 0 2006.253.07:48:11.29#ibcon#read 4, iclass 13, count 0 2006.253.07:48:11.29#ibcon#about to read 5, iclass 13, count 0 2006.253.07:48:11.29#ibcon#read 5, iclass 13, count 0 2006.253.07:48:11.29#ibcon#about to read 6, iclass 13, count 0 2006.253.07:48:11.29#ibcon#read 6, iclass 13, count 0 2006.253.07:48:11.29#ibcon#end of sib2, iclass 13, count 0 2006.253.07:48:11.29#ibcon#*after write, iclass 13, count 0 2006.253.07:48:11.29#ibcon#*before return 0, iclass 13, count 0 2006.253.07:48:11.29#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.253.07:48:11.29#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.253.07:48:11.29#ibcon#about to clear, iclass 13 cls_cnt 0 2006.253.07:48:11.29#ibcon#cleared, iclass 13 cls_cnt 0 2006.253.07:48:11.29$vc4f8/vb=3,4 2006.253.07:48:11.29#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.253.07:48:11.29#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.253.07:48:11.29#ibcon#ireg 11 cls_cnt 2 2006.253.07:48:11.29#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.253.07:48:11.35#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.253.07:48:11.35#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.253.07:48:11.35#ibcon#enter wrdev, iclass 15, count 2 2006.253.07:48:11.35#ibcon#first serial, iclass 15, count 2 2006.253.07:48:11.35#ibcon#enter sib2, iclass 15, count 2 2006.253.07:48:11.35#ibcon#flushed, iclass 15, count 2 2006.253.07:48:11.35#ibcon#about to write, iclass 15, count 2 2006.253.07:48:11.35#ibcon#wrote, iclass 15, count 2 2006.253.07:48:11.35#ibcon#about to read 3, iclass 15, count 2 2006.253.07:48:11.37#ibcon#read 3, iclass 15, count 2 2006.253.07:48:11.37#ibcon#about to read 4, iclass 15, count 2 2006.253.07:48:11.37#ibcon#read 4, iclass 15, count 2 2006.253.07:48:11.37#ibcon#about to read 5, iclass 15, count 2 2006.253.07:48:11.37#ibcon#read 5, iclass 15, count 2 2006.253.07:48:11.37#ibcon#about to read 6, iclass 15, count 2 2006.253.07:48:11.37#ibcon#read 6, iclass 15, count 2 2006.253.07:48:11.37#ibcon#end of sib2, iclass 15, count 2 2006.253.07:48:11.37#ibcon#*mode == 0, iclass 15, count 2 2006.253.07:48:11.37#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.253.07:48:11.37#ibcon#[27=AT03-04\r\n] 2006.253.07:48:11.37#ibcon#*before write, iclass 15, count 2 2006.253.07:48:11.37#ibcon#enter sib2, iclass 15, count 2 2006.253.07:48:11.37#ibcon#flushed, iclass 15, count 2 2006.253.07:48:11.37#ibcon#about to write, iclass 15, count 2 2006.253.07:48:11.37#ibcon#wrote, iclass 15, count 2 2006.253.07:48:11.37#ibcon#about to read 3, iclass 15, count 2 2006.253.07:48:11.40#ibcon#read 3, iclass 15, count 2 2006.253.07:48:11.40#ibcon#about to read 4, iclass 15, count 2 2006.253.07:48:11.40#ibcon#read 4, iclass 15, count 2 2006.253.07:48:11.40#ibcon#about to read 5, iclass 15, count 2 2006.253.07:48:11.40#ibcon#read 5, iclass 15, count 2 2006.253.07:48:11.40#ibcon#about to read 6, iclass 15, count 2 2006.253.07:48:11.40#ibcon#read 6, iclass 15, count 2 2006.253.07:48:11.40#ibcon#end of sib2, iclass 15, count 2 2006.253.07:48:11.40#ibcon#*after write, iclass 15, count 2 2006.253.07:48:11.40#ibcon#*before return 0, iclass 15, count 2 2006.253.07:48:11.40#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.253.07:48:11.40#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.253.07:48:11.40#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.253.07:48:11.40#ibcon#ireg 7 cls_cnt 0 2006.253.07:48:11.40#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.253.07:48:11.52#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.253.07:48:11.52#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.253.07:48:11.52#ibcon#enter wrdev, iclass 15, count 0 2006.253.07:48:11.52#ibcon#first serial, iclass 15, count 0 2006.253.07:48:11.52#ibcon#enter sib2, iclass 15, count 0 2006.253.07:48:11.52#ibcon#flushed, iclass 15, count 0 2006.253.07:48:11.52#ibcon#about to write, iclass 15, count 0 2006.253.07:48:11.52#ibcon#wrote, iclass 15, count 0 2006.253.07:48:11.52#ibcon#about to read 3, iclass 15, count 0 2006.253.07:48:11.54#ibcon#read 3, iclass 15, count 0 2006.253.07:48:11.54#ibcon#about to read 4, iclass 15, count 0 2006.253.07:48:11.54#ibcon#read 4, iclass 15, count 0 2006.253.07:48:11.54#ibcon#about to read 5, iclass 15, count 0 2006.253.07:48:11.54#ibcon#read 5, iclass 15, count 0 2006.253.07:48:11.54#ibcon#about to read 6, iclass 15, count 0 2006.253.07:48:11.54#ibcon#read 6, iclass 15, count 0 2006.253.07:48:11.54#ibcon#end of sib2, iclass 15, count 0 2006.253.07:48:11.54#ibcon#*mode == 0, iclass 15, count 0 2006.253.07:48:11.54#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.253.07:48:11.54#ibcon#[27=USB\r\n] 2006.253.07:48:11.54#ibcon#*before write, iclass 15, count 0 2006.253.07:48:11.54#ibcon#enter sib2, iclass 15, count 0 2006.253.07:48:11.54#ibcon#flushed, iclass 15, count 0 2006.253.07:48:11.54#ibcon#about to write, iclass 15, count 0 2006.253.07:48:11.54#ibcon#wrote, iclass 15, count 0 2006.253.07:48:11.54#ibcon#about to read 3, iclass 15, count 0 2006.253.07:48:11.57#ibcon#read 3, iclass 15, count 0 2006.253.07:48:11.57#ibcon#about to read 4, iclass 15, count 0 2006.253.07:48:11.57#ibcon#read 4, iclass 15, count 0 2006.253.07:48:11.57#ibcon#about to read 5, iclass 15, count 0 2006.253.07:48:11.57#ibcon#read 5, iclass 15, count 0 2006.253.07:48:11.57#ibcon#about to read 6, iclass 15, count 0 2006.253.07:48:11.57#ibcon#read 6, iclass 15, count 0 2006.253.07:48:11.57#ibcon#end of sib2, iclass 15, count 0 2006.253.07:48:11.57#ibcon#*after write, iclass 15, count 0 2006.253.07:48:11.57#ibcon#*before return 0, iclass 15, count 0 2006.253.07:48:11.57#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.253.07:48:11.57#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.253.07:48:11.57#ibcon#about to clear, iclass 15 cls_cnt 0 2006.253.07:48:11.57#ibcon#cleared, iclass 15 cls_cnt 0 2006.253.07:48:11.57$vc4f8/vblo=4,712.99 2006.253.07:48:11.57#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.253.07:48:11.57#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.253.07:48:11.57#ibcon#ireg 17 cls_cnt 0 2006.253.07:48:11.57#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.253.07:48:11.57#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.253.07:48:11.57#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.253.07:48:11.57#ibcon#enter wrdev, iclass 17, count 0 2006.253.07:48:11.57#ibcon#first serial, iclass 17, count 0 2006.253.07:48:11.57#ibcon#enter sib2, iclass 17, count 0 2006.253.07:48:11.57#ibcon#flushed, iclass 17, count 0 2006.253.07:48:11.57#ibcon#about to write, iclass 17, count 0 2006.253.07:48:11.57#ibcon#wrote, iclass 17, count 0 2006.253.07:48:11.57#ibcon#about to read 3, iclass 17, count 0 2006.253.07:48:11.59#ibcon#read 3, iclass 17, count 0 2006.253.07:48:11.59#ibcon#about to read 4, iclass 17, count 0 2006.253.07:48:11.59#ibcon#read 4, iclass 17, count 0 2006.253.07:48:11.59#ibcon#about to read 5, iclass 17, count 0 2006.253.07:48:11.59#ibcon#read 5, iclass 17, count 0 2006.253.07:48:11.59#ibcon#about to read 6, iclass 17, count 0 2006.253.07:48:11.59#ibcon#read 6, iclass 17, count 0 2006.253.07:48:11.59#ibcon#end of sib2, iclass 17, count 0 2006.253.07:48:11.59#ibcon#*mode == 0, iclass 17, count 0 2006.253.07:48:11.59#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.253.07:48:11.59#ibcon#[28=FRQ=04,712.99\r\n] 2006.253.07:48:11.59#ibcon#*before write, iclass 17, count 0 2006.253.07:48:11.59#ibcon#enter sib2, iclass 17, count 0 2006.253.07:48:11.59#ibcon#flushed, iclass 17, count 0 2006.253.07:48:11.59#ibcon#about to write, iclass 17, count 0 2006.253.07:48:11.59#ibcon#wrote, iclass 17, count 0 2006.253.07:48:11.59#ibcon#about to read 3, iclass 17, count 0 2006.253.07:48:11.63#ibcon#read 3, iclass 17, count 0 2006.253.07:48:11.63#ibcon#about to read 4, iclass 17, count 0 2006.253.07:48:11.63#ibcon#read 4, iclass 17, count 0 2006.253.07:48:11.63#ibcon#about to read 5, iclass 17, count 0 2006.253.07:48:11.63#ibcon#read 5, iclass 17, count 0 2006.253.07:48:11.63#ibcon#about to read 6, iclass 17, count 0 2006.253.07:48:11.63#ibcon#read 6, iclass 17, count 0 2006.253.07:48:11.63#ibcon#end of sib2, iclass 17, count 0 2006.253.07:48:11.63#ibcon#*after write, iclass 17, count 0 2006.253.07:48:11.63#ibcon#*before return 0, iclass 17, count 0 2006.253.07:48:11.63#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.253.07:48:11.63#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.253.07:48:11.63#ibcon#about to clear, iclass 17 cls_cnt 0 2006.253.07:48:11.63#ibcon#cleared, iclass 17 cls_cnt 0 2006.253.07:48:11.63$vc4f8/vb=4,4 2006.253.07:48:11.63#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.253.07:48:11.63#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.253.07:48:11.63#ibcon#ireg 11 cls_cnt 2 2006.253.07:48:11.63#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.253.07:48:11.70#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.253.07:48:11.70#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.253.07:48:11.70#ibcon#enter wrdev, iclass 19, count 2 2006.253.07:48:11.70#ibcon#first serial, iclass 19, count 2 2006.253.07:48:11.70#ibcon#enter sib2, iclass 19, count 2 2006.253.07:48:11.70#ibcon#flushed, iclass 19, count 2 2006.253.07:48:11.70#ibcon#about to write, iclass 19, count 2 2006.253.07:48:11.70#ibcon#wrote, iclass 19, count 2 2006.253.07:48:11.70#ibcon#about to read 3, iclass 19, count 2 2006.253.07:48:11.71#ibcon#read 3, iclass 19, count 2 2006.253.07:48:11.71#ibcon#about to read 4, iclass 19, count 2 2006.253.07:48:11.71#ibcon#read 4, iclass 19, count 2 2006.253.07:48:11.71#ibcon#about to read 5, iclass 19, count 2 2006.253.07:48:11.71#ibcon#read 5, iclass 19, count 2 2006.253.07:48:11.71#ibcon#about to read 6, iclass 19, count 2 2006.253.07:48:11.71#ibcon#read 6, iclass 19, count 2 2006.253.07:48:11.71#ibcon#end of sib2, iclass 19, count 2 2006.253.07:48:11.71#ibcon#*mode == 0, iclass 19, count 2 2006.253.07:48:11.71#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.253.07:48:11.71#ibcon#[27=AT04-04\r\n] 2006.253.07:48:11.71#ibcon#*before write, iclass 19, count 2 2006.253.07:48:11.71#ibcon#enter sib2, iclass 19, count 2 2006.253.07:48:11.71#ibcon#flushed, iclass 19, count 2 2006.253.07:48:11.71#ibcon#about to write, iclass 19, count 2 2006.253.07:48:11.71#ibcon#wrote, iclass 19, count 2 2006.253.07:48:11.71#ibcon#about to read 3, iclass 19, count 2 2006.253.07:48:11.74#ibcon#read 3, iclass 19, count 2 2006.253.07:48:11.74#ibcon#about to read 4, iclass 19, count 2 2006.253.07:48:11.74#ibcon#read 4, iclass 19, count 2 2006.253.07:48:11.74#ibcon#about to read 5, iclass 19, count 2 2006.253.07:48:11.74#ibcon#read 5, iclass 19, count 2 2006.253.07:48:11.74#ibcon#about to read 6, iclass 19, count 2 2006.253.07:48:11.74#ibcon#read 6, iclass 19, count 2 2006.253.07:48:11.74#ibcon#end of sib2, iclass 19, count 2 2006.253.07:48:11.74#ibcon#*after write, iclass 19, count 2 2006.253.07:48:11.74#ibcon#*before return 0, iclass 19, count 2 2006.253.07:48:11.74#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.253.07:48:11.74#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.253.07:48:11.74#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.253.07:48:11.74#ibcon#ireg 7 cls_cnt 0 2006.253.07:48:11.74#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.253.07:48:11.86#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.253.07:48:11.86#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.253.07:48:11.86#ibcon#enter wrdev, iclass 19, count 0 2006.253.07:48:11.86#ibcon#first serial, iclass 19, count 0 2006.253.07:48:11.86#ibcon#enter sib2, iclass 19, count 0 2006.253.07:48:11.86#ibcon#flushed, iclass 19, count 0 2006.253.07:48:11.86#ibcon#about to write, iclass 19, count 0 2006.253.07:48:11.86#ibcon#wrote, iclass 19, count 0 2006.253.07:48:11.86#ibcon#about to read 3, iclass 19, count 0 2006.253.07:48:11.88#ibcon#read 3, iclass 19, count 0 2006.253.07:48:11.88#ibcon#about to read 4, iclass 19, count 0 2006.253.07:48:11.88#ibcon#read 4, iclass 19, count 0 2006.253.07:48:11.88#ibcon#about to read 5, iclass 19, count 0 2006.253.07:48:11.88#ibcon#read 5, iclass 19, count 0 2006.253.07:48:11.88#ibcon#about to read 6, iclass 19, count 0 2006.253.07:48:11.88#ibcon#read 6, iclass 19, count 0 2006.253.07:48:11.88#ibcon#end of sib2, iclass 19, count 0 2006.253.07:48:11.88#ibcon#*mode == 0, iclass 19, count 0 2006.253.07:48:11.88#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.253.07:48:11.88#ibcon#[27=USB\r\n] 2006.253.07:48:11.88#ibcon#*before write, iclass 19, count 0 2006.253.07:48:11.88#ibcon#enter sib2, iclass 19, count 0 2006.253.07:48:11.88#ibcon#flushed, iclass 19, count 0 2006.253.07:48:11.88#ibcon#about to write, iclass 19, count 0 2006.253.07:48:11.88#ibcon#wrote, iclass 19, count 0 2006.253.07:48:11.88#ibcon#about to read 3, iclass 19, count 0 2006.253.07:48:11.91#ibcon#read 3, iclass 19, count 0 2006.253.07:48:11.91#ibcon#about to read 4, iclass 19, count 0 2006.253.07:48:11.91#ibcon#read 4, iclass 19, count 0 2006.253.07:48:11.91#ibcon#about to read 5, iclass 19, count 0 2006.253.07:48:11.91#ibcon#read 5, iclass 19, count 0 2006.253.07:48:11.91#ibcon#about to read 6, iclass 19, count 0 2006.253.07:48:11.91#ibcon#read 6, iclass 19, count 0 2006.253.07:48:11.91#ibcon#end of sib2, iclass 19, count 0 2006.253.07:48:11.91#ibcon#*after write, iclass 19, count 0 2006.253.07:48:11.91#ibcon#*before return 0, iclass 19, count 0 2006.253.07:48:11.91#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.253.07:48:11.91#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.253.07:48:11.91#ibcon#about to clear, iclass 19 cls_cnt 0 2006.253.07:48:11.91#ibcon#cleared, iclass 19 cls_cnt 0 2006.253.07:48:11.91$vc4f8/vblo=5,744.99 2006.253.07:48:11.91#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.253.07:48:11.91#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.253.07:48:11.91#ibcon#ireg 17 cls_cnt 0 2006.253.07:48:11.91#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.253.07:48:11.91#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.253.07:48:11.91#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.253.07:48:11.91#ibcon#enter wrdev, iclass 21, count 0 2006.253.07:48:11.91#ibcon#first serial, iclass 21, count 0 2006.253.07:48:11.91#ibcon#enter sib2, iclass 21, count 0 2006.253.07:48:11.91#ibcon#flushed, iclass 21, count 0 2006.253.07:48:11.91#ibcon#about to write, iclass 21, count 0 2006.253.07:48:11.91#ibcon#wrote, iclass 21, count 0 2006.253.07:48:11.91#ibcon#about to read 3, iclass 21, count 0 2006.253.07:48:11.94#ibcon#read 3, iclass 21, count 0 2006.253.07:48:11.94#ibcon#about to read 4, iclass 21, count 0 2006.253.07:48:11.94#ibcon#read 4, iclass 21, count 0 2006.253.07:48:11.94#ibcon#about to read 5, iclass 21, count 0 2006.253.07:48:11.94#ibcon#read 5, iclass 21, count 0 2006.253.07:48:11.94#ibcon#about to read 6, iclass 21, count 0 2006.253.07:48:11.94#ibcon#read 6, iclass 21, count 0 2006.253.07:48:11.94#ibcon#end of sib2, iclass 21, count 0 2006.253.07:48:11.94#ibcon#*mode == 0, iclass 21, count 0 2006.253.07:48:11.94#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.253.07:48:11.94#ibcon#[28=FRQ=05,744.99\r\n] 2006.253.07:48:11.94#ibcon#*before write, iclass 21, count 0 2006.253.07:48:11.94#ibcon#enter sib2, iclass 21, count 0 2006.253.07:48:11.94#ibcon#flushed, iclass 21, count 0 2006.253.07:48:11.94#ibcon#about to write, iclass 21, count 0 2006.253.07:48:11.94#ibcon#wrote, iclass 21, count 0 2006.253.07:48:11.94#ibcon#about to read 3, iclass 21, count 0 2006.253.07:48:11.98#ibcon#read 3, iclass 21, count 0 2006.253.07:48:11.98#ibcon#about to read 4, iclass 21, count 0 2006.253.07:48:11.98#ibcon#read 4, iclass 21, count 0 2006.253.07:48:11.98#ibcon#about to read 5, iclass 21, count 0 2006.253.07:48:11.98#ibcon#read 5, iclass 21, count 0 2006.253.07:48:11.98#ibcon#about to read 6, iclass 21, count 0 2006.253.07:48:11.98#ibcon#read 6, iclass 21, count 0 2006.253.07:48:11.98#ibcon#end of sib2, iclass 21, count 0 2006.253.07:48:11.98#ibcon#*after write, iclass 21, count 0 2006.253.07:48:11.98#ibcon#*before return 0, iclass 21, count 0 2006.253.07:48:11.98#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.253.07:48:11.98#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.253.07:48:11.98#ibcon#about to clear, iclass 21 cls_cnt 0 2006.253.07:48:11.98#ibcon#cleared, iclass 21 cls_cnt 0 2006.253.07:48:11.98$vc4f8/vb=5,4 2006.253.07:48:11.98#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.253.07:48:11.98#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.253.07:48:11.98#ibcon#ireg 11 cls_cnt 2 2006.253.07:48:11.98#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.253.07:48:12.03#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.253.07:48:12.03#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.253.07:48:12.03#ibcon#enter wrdev, iclass 23, count 2 2006.253.07:48:12.03#ibcon#first serial, iclass 23, count 2 2006.253.07:48:12.03#ibcon#enter sib2, iclass 23, count 2 2006.253.07:48:12.03#ibcon#flushed, iclass 23, count 2 2006.253.07:48:12.03#ibcon#about to write, iclass 23, count 2 2006.253.07:48:12.03#ibcon#wrote, iclass 23, count 2 2006.253.07:48:12.03#ibcon#about to read 3, iclass 23, count 2 2006.253.07:48:12.05#ibcon#read 3, iclass 23, count 2 2006.253.07:48:12.05#ibcon#about to read 4, iclass 23, count 2 2006.253.07:48:12.05#ibcon#read 4, iclass 23, count 2 2006.253.07:48:12.05#ibcon#about to read 5, iclass 23, count 2 2006.253.07:48:12.05#ibcon#read 5, iclass 23, count 2 2006.253.07:48:12.05#ibcon#about to read 6, iclass 23, count 2 2006.253.07:48:12.05#ibcon#read 6, iclass 23, count 2 2006.253.07:48:12.05#ibcon#end of sib2, iclass 23, count 2 2006.253.07:48:12.05#ibcon#*mode == 0, iclass 23, count 2 2006.253.07:48:12.05#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.253.07:48:12.05#ibcon#[27=AT05-04\r\n] 2006.253.07:48:12.05#ibcon#*before write, iclass 23, count 2 2006.253.07:48:12.05#ibcon#enter sib2, iclass 23, count 2 2006.253.07:48:12.05#ibcon#flushed, iclass 23, count 2 2006.253.07:48:12.05#ibcon#about to write, iclass 23, count 2 2006.253.07:48:12.05#ibcon#wrote, iclass 23, count 2 2006.253.07:48:12.05#ibcon#about to read 3, iclass 23, count 2 2006.253.07:48:12.08#ibcon#read 3, iclass 23, count 2 2006.253.07:48:12.08#ibcon#about to read 4, iclass 23, count 2 2006.253.07:48:12.08#ibcon#read 4, iclass 23, count 2 2006.253.07:48:12.08#ibcon#about to read 5, iclass 23, count 2 2006.253.07:48:12.08#ibcon#read 5, iclass 23, count 2 2006.253.07:48:12.08#ibcon#about to read 6, iclass 23, count 2 2006.253.07:48:12.08#ibcon#read 6, iclass 23, count 2 2006.253.07:48:12.08#ibcon#end of sib2, iclass 23, count 2 2006.253.07:48:12.08#ibcon#*after write, iclass 23, count 2 2006.253.07:48:12.08#ibcon#*before return 0, iclass 23, count 2 2006.253.07:48:12.08#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.253.07:48:12.08#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.253.07:48:12.08#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.253.07:48:12.08#ibcon#ireg 7 cls_cnt 0 2006.253.07:48:12.08#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.253.07:48:12.20#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.253.07:48:12.20#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.253.07:48:12.20#ibcon#enter wrdev, iclass 23, count 0 2006.253.07:48:12.20#ibcon#first serial, iclass 23, count 0 2006.253.07:48:12.20#ibcon#enter sib2, iclass 23, count 0 2006.253.07:48:12.20#ibcon#flushed, iclass 23, count 0 2006.253.07:48:12.20#ibcon#about to write, iclass 23, count 0 2006.253.07:48:12.20#ibcon#wrote, iclass 23, count 0 2006.253.07:48:12.20#ibcon#about to read 3, iclass 23, count 0 2006.253.07:48:12.22#ibcon#read 3, iclass 23, count 0 2006.253.07:48:12.22#ibcon#about to read 4, iclass 23, count 0 2006.253.07:48:12.22#ibcon#read 4, iclass 23, count 0 2006.253.07:48:12.22#ibcon#about to read 5, iclass 23, count 0 2006.253.07:48:12.22#ibcon#read 5, iclass 23, count 0 2006.253.07:48:12.22#ibcon#about to read 6, iclass 23, count 0 2006.253.07:48:12.22#ibcon#read 6, iclass 23, count 0 2006.253.07:48:12.22#ibcon#end of sib2, iclass 23, count 0 2006.253.07:48:12.22#ibcon#*mode == 0, iclass 23, count 0 2006.253.07:48:12.22#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.253.07:48:12.22#ibcon#[27=USB\r\n] 2006.253.07:48:12.22#ibcon#*before write, iclass 23, count 0 2006.253.07:48:12.22#ibcon#enter sib2, iclass 23, count 0 2006.253.07:48:12.22#ibcon#flushed, iclass 23, count 0 2006.253.07:48:12.22#ibcon#about to write, iclass 23, count 0 2006.253.07:48:12.22#ibcon#wrote, iclass 23, count 0 2006.253.07:48:12.22#ibcon#about to read 3, iclass 23, count 0 2006.253.07:48:12.25#ibcon#read 3, iclass 23, count 0 2006.253.07:48:12.25#ibcon#about to read 4, iclass 23, count 0 2006.253.07:48:12.25#ibcon#read 4, iclass 23, count 0 2006.253.07:48:12.25#ibcon#about to read 5, iclass 23, count 0 2006.253.07:48:12.25#ibcon#read 5, iclass 23, count 0 2006.253.07:48:12.25#ibcon#about to read 6, iclass 23, count 0 2006.253.07:48:12.25#ibcon#read 6, iclass 23, count 0 2006.253.07:48:12.25#ibcon#end of sib2, iclass 23, count 0 2006.253.07:48:12.25#ibcon#*after write, iclass 23, count 0 2006.253.07:48:12.25#ibcon#*before return 0, iclass 23, count 0 2006.253.07:48:12.25#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.253.07:48:12.25#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.253.07:48:12.25#ibcon#about to clear, iclass 23 cls_cnt 0 2006.253.07:48:12.25#ibcon#cleared, iclass 23 cls_cnt 0 2006.253.07:48:12.25$vc4f8/vblo=6,752.99 2006.253.07:48:12.25#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.253.07:48:12.25#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.253.07:48:12.25#ibcon#ireg 17 cls_cnt 0 2006.253.07:48:12.25#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.253.07:48:12.25#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.253.07:48:12.25#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.253.07:48:12.25#ibcon#enter wrdev, iclass 25, count 0 2006.253.07:48:12.25#ibcon#first serial, iclass 25, count 0 2006.253.07:48:12.25#ibcon#enter sib2, iclass 25, count 0 2006.253.07:48:12.25#ibcon#flushed, iclass 25, count 0 2006.253.07:48:12.25#ibcon#about to write, iclass 25, count 0 2006.253.07:48:12.25#ibcon#wrote, iclass 25, count 0 2006.253.07:48:12.25#ibcon#about to read 3, iclass 25, count 0 2006.253.07:48:12.27#ibcon#read 3, iclass 25, count 0 2006.253.07:48:12.27#ibcon#about to read 4, iclass 25, count 0 2006.253.07:48:12.27#ibcon#read 4, iclass 25, count 0 2006.253.07:48:12.27#ibcon#about to read 5, iclass 25, count 0 2006.253.07:48:12.27#ibcon#read 5, iclass 25, count 0 2006.253.07:48:12.27#ibcon#about to read 6, iclass 25, count 0 2006.253.07:48:12.27#ibcon#read 6, iclass 25, count 0 2006.253.07:48:12.27#ibcon#end of sib2, iclass 25, count 0 2006.253.07:48:12.27#ibcon#*mode == 0, iclass 25, count 0 2006.253.07:48:12.27#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.253.07:48:12.27#ibcon#[28=FRQ=06,752.99\r\n] 2006.253.07:48:12.27#ibcon#*before write, iclass 25, count 0 2006.253.07:48:12.27#ibcon#enter sib2, iclass 25, count 0 2006.253.07:48:12.27#ibcon#flushed, iclass 25, count 0 2006.253.07:48:12.27#ibcon#about to write, iclass 25, count 0 2006.253.07:48:12.27#ibcon#wrote, iclass 25, count 0 2006.253.07:48:12.27#ibcon#about to read 3, iclass 25, count 0 2006.253.07:48:12.31#ibcon#read 3, iclass 25, count 0 2006.253.07:48:12.31#ibcon#about to read 4, iclass 25, count 0 2006.253.07:48:12.31#ibcon#read 4, iclass 25, count 0 2006.253.07:48:12.31#ibcon#about to read 5, iclass 25, count 0 2006.253.07:48:12.31#ibcon#read 5, iclass 25, count 0 2006.253.07:48:12.31#ibcon#about to read 6, iclass 25, count 0 2006.253.07:48:12.31#ibcon#read 6, iclass 25, count 0 2006.253.07:48:12.31#ibcon#end of sib2, iclass 25, count 0 2006.253.07:48:12.31#ibcon#*after write, iclass 25, count 0 2006.253.07:48:12.31#ibcon#*before return 0, iclass 25, count 0 2006.253.07:48:12.31#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.253.07:48:12.31#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.253.07:48:12.31#ibcon#about to clear, iclass 25 cls_cnt 0 2006.253.07:48:12.31#ibcon#cleared, iclass 25 cls_cnt 0 2006.253.07:48:12.31$vc4f8/vb=6,4 2006.253.07:48:12.31#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.253.07:48:12.31#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.253.07:48:12.31#ibcon#ireg 11 cls_cnt 2 2006.253.07:48:12.31#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.253.07:48:12.37#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.253.07:48:12.37#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.253.07:48:12.37#ibcon#enter wrdev, iclass 27, count 2 2006.253.07:48:12.37#ibcon#first serial, iclass 27, count 2 2006.253.07:48:12.37#ibcon#enter sib2, iclass 27, count 2 2006.253.07:48:12.37#ibcon#flushed, iclass 27, count 2 2006.253.07:48:12.37#ibcon#about to write, iclass 27, count 2 2006.253.07:48:12.37#ibcon#wrote, iclass 27, count 2 2006.253.07:48:12.37#ibcon#about to read 3, iclass 27, count 2 2006.253.07:48:12.39#ibcon#read 3, iclass 27, count 2 2006.253.07:48:12.39#ibcon#about to read 4, iclass 27, count 2 2006.253.07:48:12.39#ibcon#read 4, iclass 27, count 2 2006.253.07:48:12.39#ibcon#about to read 5, iclass 27, count 2 2006.253.07:48:12.39#ibcon#read 5, iclass 27, count 2 2006.253.07:48:12.39#ibcon#about to read 6, iclass 27, count 2 2006.253.07:48:12.39#ibcon#read 6, iclass 27, count 2 2006.253.07:48:12.39#ibcon#end of sib2, iclass 27, count 2 2006.253.07:48:12.39#ibcon#*mode == 0, iclass 27, count 2 2006.253.07:48:12.39#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.253.07:48:12.39#ibcon#[27=AT06-04\r\n] 2006.253.07:48:12.39#ibcon#*before write, iclass 27, count 2 2006.253.07:48:12.39#ibcon#enter sib2, iclass 27, count 2 2006.253.07:48:12.39#ibcon#flushed, iclass 27, count 2 2006.253.07:48:12.39#ibcon#about to write, iclass 27, count 2 2006.253.07:48:12.39#ibcon#wrote, iclass 27, count 2 2006.253.07:48:12.39#ibcon#about to read 3, iclass 27, count 2 2006.253.07:48:12.42#ibcon#read 3, iclass 27, count 2 2006.253.07:48:12.42#ibcon#about to read 4, iclass 27, count 2 2006.253.07:48:12.42#ibcon#read 4, iclass 27, count 2 2006.253.07:48:12.42#ibcon#about to read 5, iclass 27, count 2 2006.253.07:48:12.42#ibcon#read 5, iclass 27, count 2 2006.253.07:48:12.42#ibcon#about to read 6, iclass 27, count 2 2006.253.07:48:12.42#ibcon#read 6, iclass 27, count 2 2006.253.07:48:12.42#ibcon#end of sib2, iclass 27, count 2 2006.253.07:48:12.42#ibcon#*after write, iclass 27, count 2 2006.253.07:48:12.42#ibcon#*before return 0, iclass 27, count 2 2006.253.07:48:12.42#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.253.07:48:12.42#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.253.07:48:12.42#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.253.07:48:12.42#ibcon#ireg 7 cls_cnt 0 2006.253.07:48:12.42#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.253.07:48:12.54#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.253.07:48:12.54#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.253.07:48:12.54#ibcon#enter wrdev, iclass 27, count 0 2006.253.07:48:12.54#ibcon#first serial, iclass 27, count 0 2006.253.07:48:12.54#ibcon#enter sib2, iclass 27, count 0 2006.253.07:48:12.54#ibcon#flushed, iclass 27, count 0 2006.253.07:48:12.54#ibcon#about to write, iclass 27, count 0 2006.253.07:48:12.54#ibcon#wrote, iclass 27, count 0 2006.253.07:48:12.54#ibcon#about to read 3, iclass 27, count 0 2006.253.07:48:12.56#ibcon#read 3, iclass 27, count 0 2006.253.07:48:12.56#ibcon#about to read 4, iclass 27, count 0 2006.253.07:48:12.56#ibcon#read 4, iclass 27, count 0 2006.253.07:48:12.56#ibcon#about to read 5, iclass 27, count 0 2006.253.07:48:12.56#ibcon#read 5, iclass 27, count 0 2006.253.07:48:12.56#ibcon#about to read 6, iclass 27, count 0 2006.253.07:48:12.56#ibcon#read 6, iclass 27, count 0 2006.253.07:48:12.56#ibcon#end of sib2, iclass 27, count 0 2006.253.07:48:12.56#ibcon#*mode == 0, iclass 27, count 0 2006.253.07:48:12.56#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.253.07:48:12.56#ibcon#[27=USB\r\n] 2006.253.07:48:12.56#ibcon#*before write, iclass 27, count 0 2006.253.07:48:12.56#ibcon#enter sib2, iclass 27, count 0 2006.253.07:48:12.56#ibcon#flushed, iclass 27, count 0 2006.253.07:48:12.56#ibcon#about to write, iclass 27, count 0 2006.253.07:48:12.56#ibcon#wrote, iclass 27, count 0 2006.253.07:48:12.56#ibcon#about to read 3, iclass 27, count 0 2006.253.07:48:12.59#ibcon#read 3, iclass 27, count 0 2006.253.07:48:12.59#ibcon#about to read 4, iclass 27, count 0 2006.253.07:48:12.59#ibcon#read 4, iclass 27, count 0 2006.253.07:48:12.59#ibcon#about to read 5, iclass 27, count 0 2006.253.07:48:12.59#ibcon#read 5, iclass 27, count 0 2006.253.07:48:12.59#ibcon#about to read 6, iclass 27, count 0 2006.253.07:48:12.59#ibcon#read 6, iclass 27, count 0 2006.253.07:48:12.59#ibcon#end of sib2, iclass 27, count 0 2006.253.07:48:12.59#ibcon#*after write, iclass 27, count 0 2006.253.07:48:12.59#ibcon#*before return 0, iclass 27, count 0 2006.253.07:48:12.59#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.253.07:48:12.59#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.253.07:48:12.59#ibcon#about to clear, iclass 27 cls_cnt 0 2006.253.07:48:12.59#ibcon#cleared, iclass 27 cls_cnt 0 2006.253.07:48:12.59$vc4f8/vabw=wide 2006.253.07:48:12.59#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.253.07:48:12.59#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.253.07:48:12.59#ibcon#ireg 8 cls_cnt 0 2006.253.07:48:12.59#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.253.07:48:12.59#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.253.07:48:12.59#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.253.07:48:12.59#ibcon#enter wrdev, iclass 29, count 0 2006.253.07:48:12.59#ibcon#first serial, iclass 29, count 0 2006.253.07:48:12.59#ibcon#enter sib2, iclass 29, count 0 2006.253.07:48:12.59#ibcon#flushed, iclass 29, count 0 2006.253.07:48:12.59#ibcon#about to write, iclass 29, count 0 2006.253.07:48:12.59#ibcon#wrote, iclass 29, count 0 2006.253.07:48:12.59#ibcon#about to read 3, iclass 29, count 0 2006.253.07:48:12.62#ibcon#read 3, iclass 29, count 0 2006.253.07:48:12.62#ibcon#about to read 4, iclass 29, count 0 2006.253.07:48:12.62#ibcon#read 4, iclass 29, count 0 2006.253.07:48:12.62#ibcon#about to read 5, iclass 29, count 0 2006.253.07:48:12.62#ibcon#read 5, iclass 29, count 0 2006.253.07:48:12.62#ibcon#about to read 6, iclass 29, count 0 2006.253.07:48:12.62#ibcon#read 6, iclass 29, count 0 2006.253.07:48:12.62#ibcon#end of sib2, iclass 29, count 0 2006.253.07:48:12.62#ibcon#*mode == 0, iclass 29, count 0 2006.253.07:48:12.62#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.253.07:48:12.62#ibcon#[25=BW32\r\n] 2006.253.07:48:12.62#ibcon#*before write, iclass 29, count 0 2006.253.07:48:12.62#ibcon#enter sib2, iclass 29, count 0 2006.253.07:48:12.62#ibcon#flushed, iclass 29, count 0 2006.253.07:48:12.62#ibcon#about to write, iclass 29, count 0 2006.253.07:48:12.62#ibcon#wrote, iclass 29, count 0 2006.253.07:48:12.62#ibcon#about to read 3, iclass 29, count 0 2006.253.07:48:12.65#ibcon#read 3, iclass 29, count 0 2006.253.07:48:12.65#ibcon#about to read 4, iclass 29, count 0 2006.253.07:48:12.65#ibcon#read 4, iclass 29, count 0 2006.253.07:48:12.65#ibcon#about to read 5, iclass 29, count 0 2006.253.07:48:12.65#ibcon#read 5, iclass 29, count 0 2006.253.07:48:12.65#ibcon#about to read 6, iclass 29, count 0 2006.253.07:48:12.65#ibcon#read 6, iclass 29, count 0 2006.253.07:48:12.65#ibcon#end of sib2, iclass 29, count 0 2006.253.07:48:12.65#ibcon#*after write, iclass 29, count 0 2006.253.07:48:12.65#ibcon#*before return 0, iclass 29, count 0 2006.253.07:48:12.65#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.253.07:48:12.65#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.253.07:48:12.65#ibcon#about to clear, iclass 29 cls_cnt 0 2006.253.07:48:12.65#ibcon#cleared, iclass 29 cls_cnt 0 2006.253.07:48:12.65$vc4f8/vbbw=wide 2006.253.07:48:12.65#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.253.07:48:12.65#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.253.07:48:12.65#ibcon#ireg 8 cls_cnt 0 2006.253.07:48:12.65#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.253.07:48:12.71#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.253.07:48:12.71#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.253.07:48:12.71#ibcon#enter wrdev, iclass 31, count 0 2006.253.07:48:12.71#ibcon#first serial, iclass 31, count 0 2006.253.07:48:12.71#ibcon#enter sib2, iclass 31, count 0 2006.253.07:48:12.71#ibcon#flushed, iclass 31, count 0 2006.253.07:48:12.71#ibcon#about to write, iclass 31, count 0 2006.253.07:48:12.71#ibcon#wrote, iclass 31, count 0 2006.253.07:48:12.71#ibcon#about to read 3, iclass 31, count 0 2006.253.07:48:12.73#ibcon#read 3, iclass 31, count 0 2006.253.07:48:12.73#ibcon#about to read 4, iclass 31, count 0 2006.253.07:48:12.73#ibcon#read 4, iclass 31, count 0 2006.253.07:48:12.73#ibcon#about to read 5, iclass 31, count 0 2006.253.07:48:12.73#ibcon#read 5, iclass 31, count 0 2006.253.07:48:12.73#ibcon#about to read 6, iclass 31, count 0 2006.253.07:48:12.73#ibcon#read 6, iclass 31, count 0 2006.253.07:48:12.73#ibcon#end of sib2, iclass 31, count 0 2006.253.07:48:12.73#ibcon#*mode == 0, iclass 31, count 0 2006.253.07:48:12.73#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.253.07:48:12.73#ibcon#[27=BW32\r\n] 2006.253.07:48:12.73#ibcon#*before write, iclass 31, count 0 2006.253.07:48:12.73#ibcon#enter sib2, iclass 31, count 0 2006.253.07:48:12.73#ibcon#flushed, iclass 31, count 0 2006.253.07:48:12.73#ibcon#about to write, iclass 31, count 0 2006.253.07:48:12.73#ibcon#wrote, iclass 31, count 0 2006.253.07:48:12.73#ibcon#about to read 3, iclass 31, count 0 2006.253.07:48:12.76#ibcon#read 3, iclass 31, count 0 2006.253.07:48:12.76#ibcon#about to read 4, iclass 31, count 0 2006.253.07:48:12.76#ibcon#read 4, iclass 31, count 0 2006.253.07:48:12.76#ibcon#about to read 5, iclass 31, count 0 2006.253.07:48:12.76#ibcon#read 5, iclass 31, count 0 2006.253.07:48:12.76#ibcon#about to read 6, iclass 31, count 0 2006.253.07:48:12.76#ibcon#read 6, iclass 31, count 0 2006.253.07:48:12.76#ibcon#end of sib2, iclass 31, count 0 2006.253.07:48:12.76#ibcon#*after write, iclass 31, count 0 2006.253.07:48:12.76#ibcon#*before return 0, iclass 31, count 0 2006.253.07:48:12.76#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.253.07:48:12.76#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.253.07:48:12.76#ibcon#about to clear, iclass 31 cls_cnt 0 2006.253.07:48:12.76#ibcon#cleared, iclass 31 cls_cnt 0 2006.253.07:48:12.76$4f8m12a/ifd4f 2006.253.07:48:12.76$ifd4f/lo= 2006.253.07:48:12.76$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.253.07:48:12.76$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.253.07:48:12.77$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.253.07:48:12.77$ifd4f/patch= 2006.253.07:48:12.77$ifd4f/patch=lo1,a1,a2,a3,a4 2006.253.07:48:12.77$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.253.07:48:12.77$ifd4f/patch=lo3,a5,a6,a7,a8 2006.253.07:48:12.77$4f8m12a/"form=m,16.000,1:2 2006.253.07:48:12.77$4f8m12a/"tpicd 2006.253.07:48:12.77$4f8m12a/echo=off 2006.253.07:48:12.77$4f8m12a/xlog=off 2006.253.07:48:12.77:!2006.253.07:48:40 2006.253.07:48:24.14#trakl#Source acquired 2006.253.07:48:25.14#flagr#flagr/antenna,acquired 2006.253.07:48:40.01:preob 2006.253.07:48:41.14/onsource/TRACKING 2006.253.07:48:41.14:!2006.253.07:48:50 2006.253.07:48:50.00:data_valid=on 2006.253.07:48:50.00:midob 2006.253.07:48:50.14/onsource/TRACKING 2006.253.07:48:50.14/wx/31.34,1006.4,73 2006.253.07:48:50.27/cable/+6.3687E-03 2006.253.07:48:51.36/va/01,08,usb,yes,31,33 2006.253.07:48:51.36/va/02,07,usb,yes,31,33 2006.253.07:48:51.36/va/03,06,usb,yes,33,34 2006.253.07:48:51.36/va/04,07,usb,yes,32,35 2006.253.07:48:51.36/va/05,07,usb,yes,34,36 2006.253.07:48:51.36/va/06,07,usb,yes,29,29 2006.253.07:48:51.36/va/07,07,usb,yes,29,29 2006.253.07:48:51.36/va/08,07,usb,yes,32,31 2006.253.07:48:51.59/valo/01,532.99,yes,locked 2006.253.07:48:51.59/valo/02,572.99,yes,locked 2006.253.07:48:51.59/valo/03,672.99,yes,locked 2006.253.07:48:51.59/valo/04,832.99,yes,locked 2006.253.07:48:51.59/valo/05,652.99,yes,locked 2006.253.07:48:51.59/valo/06,772.99,yes,locked 2006.253.07:48:51.59/valo/07,832.99,yes,locked 2006.253.07:48:51.59/valo/08,852.99,yes,locked 2006.253.07:48:52.68/vb/01,04,usb,yes,30,29 2006.253.07:48:52.68/vb/02,05,usb,yes,28,29 2006.253.07:48:52.68/vb/03,04,usb,yes,28,32 2006.253.07:48:52.68/vb/04,04,usb,yes,29,29 2006.253.07:48:52.68/vb/05,04,usb,yes,28,32 2006.253.07:48:52.68/vb/06,04,usb,yes,29,32 2006.253.07:48:52.68/vb/07,04,usb,yes,31,31 2006.253.07:48:52.68/vb/08,04,usb,yes,28,32 2006.253.07:48:52.92/vblo/01,632.99,yes,locked 2006.253.07:48:52.92/vblo/02,640.99,yes,locked 2006.253.07:48:52.92/vblo/03,656.99,yes,locked 2006.253.07:48:52.92/vblo/04,712.99,yes,locked 2006.253.07:48:52.92/vblo/05,744.99,yes,locked 2006.253.07:48:52.92/vblo/06,752.99,yes,locked 2006.253.07:48:52.92/vblo/07,734.99,yes,locked 2006.253.07:48:52.92/vblo/08,744.99,yes,locked 2006.253.07:48:53.07/vabw/8 2006.253.07:48:53.22/vbbw/8 2006.253.07:48:53.31/xfe/off,on,14.2 2006.253.07:48:53.69/ifatt/23,28,28,28 2006.253.07:48:54.07/fmout-gps/S +4.74E-07 2006.253.07:48:54.15:!2006.253.07:49:50 2006.253.07:49:50.00:data_valid=off 2006.253.07:49:50.01:postob 2006.253.07:49:50.12/cable/+6.3669E-03 2006.253.07:49:50.13/wx/31.33,1006.4,73 2006.253.07:49:51.07/fmout-gps/S +4.75E-07 2006.253.07:49:51.08:scan_name=253-0750,k06253,70 2006.253.07:49:51.08:source=3c418,203837.03,511912.7,2000.0,cw 2006.253.07:49:51.14#flagr#flagr/antenna,new-source 2006.253.07:49:52.14:checkk5 2006.253.07:49:52.51/chk_autoobs//k5ts1/ autoobs is running! 2006.253.07:49:52.88/chk_autoobs//k5ts2/ autoobs is running! 2006.253.07:49:53.30/chk_autoobs//k5ts3/ autoobs is running! 2006.253.07:49:53.67/chk_autoobs//k5ts4/ autoobs is running! 2006.253.07:49:54.04/chk_obsdata//k5ts1/T2530748??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.07:49:54.41/chk_obsdata//k5ts2/T2530748??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.07:49:54.78/chk_obsdata//k5ts3/T2530748??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.07:49:55.15/chk_obsdata//k5ts4/T2530748??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.07:49:55.84/k5log//k5ts1_log_newline 2006.253.07:49:56.53/k5log//k5ts2_log_newline 2006.253.07:49:57.23/k5log//k5ts3_log_newline 2006.253.07:49:57.92/k5log//k5ts4_log_newline 2006.253.07:49:57.94/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.253.07:49:57.94:4f8m12a=1 2006.253.07:49:57.94$4f8m12a/echo=on 2006.253.07:49:57.94$4f8m12a/pcalon 2006.253.07:49:57.94$pcalon/"no phase cal control is implemented here 2006.253.07:49:57.94$4f8m12a/"tpicd=stop 2006.253.07:49:57.94$4f8m12a/vc4f8 2006.253.07:49:57.94$vc4f8/valo=1,532.99 2006.253.07:49:57.94#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.253.07:49:57.94#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.253.07:49:57.95#ibcon#ireg 17 cls_cnt 0 2006.253.07:49:57.95#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.253.07:49:57.95#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.253.07:49:57.95#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.253.07:49:57.95#ibcon#enter wrdev, iclass 35, count 0 2006.253.07:49:57.95#ibcon#first serial, iclass 35, count 0 2006.253.07:49:57.95#ibcon#enter sib2, iclass 35, count 0 2006.253.07:49:57.95#ibcon#flushed, iclass 35, count 0 2006.253.07:49:57.95#ibcon#about to write, iclass 35, count 0 2006.253.07:49:57.95#ibcon#wrote, iclass 35, count 0 2006.253.07:49:57.95#ibcon#about to read 3, iclass 35, count 0 2006.253.07:49:57.99#ibcon#read 3, iclass 35, count 0 2006.253.07:49:57.99#ibcon#about to read 4, iclass 35, count 0 2006.253.07:49:57.99#ibcon#read 4, iclass 35, count 0 2006.253.07:49:57.99#ibcon#about to read 5, iclass 35, count 0 2006.253.07:49:57.99#ibcon#read 5, iclass 35, count 0 2006.253.07:49:57.99#ibcon#about to read 6, iclass 35, count 0 2006.253.07:49:57.99#ibcon#read 6, iclass 35, count 0 2006.253.07:49:57.99#ibcon#end of sib2, iclass 35, count 0 2006.253.07:49:57.99#ibcon#*mode == 0, iclass 35, count 0 2006.253.07:49:57.99#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.253.07:49:57.99#ibcon#[26=FRQ=01,532.99\r\n] 2006.253.07:49:57.99#ibcon#*before write, iclass 35, count 0 2006.253.07:49:57.99#ibcon#enter sib2, iclass 35, count 0 2006.253.07:49:57.99#ibcon#flushed, iclass 35, count 0 2006.253.07:49:57.99#ibcon#about to write, iclass 35, count 0 2006.253.07:49:57.99#ibcon#wrote, iclass 35, count 0 2006.253.07:49:57.99#ibcon#about to read 3, iclass 35, count 0 2006.253.07:49:58.03#ibcon#read 3, iclass 35, count 0 2006.253.07:49:58.03#ibcon#about to read 4, iclass 35, count 0 2006.253.07:49:58.03#ibcon#read 4, iclass 35, count 0 2006.253.07:49:58.03#ibcon#about to read 5, iclass 35, count 0 2006.253.07:49:58.03#ibcon#read 5, iclass 35, count 0 2006.253.07:49:58.03#ibcon#about to read 6, iclass 35, count 0 2006.253.07:49:58.03#ibcon#read 6, iclass 35, count 0 2006.253.07:49:58.03#ibcon#end of sib2, iclass 35, count 0 2006.253.07:49:58.03#ibcon#*after write, iclass 35, count 0 2006.253.07:49:58.03#ibcon#*before return 0, iclass 35, count 0 2006.253.07:49:58.03#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.253.07:49:58.03#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.253.07:49:58.03#ibcon#about to clear, iclass 35 cls_cnt 0 2006.253.07:49:58.03#ibcon#cleared, iclass 35 cls_cnt 0 2006.253.07:49:58.03$vc4f8/va=1,8 2006.253.07:49:58.03#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.253.07:49:58.03#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.253.07:49:58.03#ibcon#ireg 11 cls_cnt 2 2006.253.07:49:58.03#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.253.07:49:58.03#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.253.07:49:58.03#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.253.07:49:58.03#ibcon#enter wrdev, iclass 37, count 2 2006.253.07:49:58.03#ibcon#first serial, iclass 37, count 2 2006.253.07:49:58.03#ibcon#enter sib2, iclass 37, count 2 2006.253.07:49:58.03#ibcon#flushed, iclass 37, count 2 2006.253.07:49:58.03#ibcon#about to write, iclass 37, count 2 2006.253.07:49:58.03#ibcon#wrote, iclass 37, count 2 2006.253.07:49:58.03#ibcon#about to read 3, iclass 37, count 2 2006.253.07:49:58.05#ibcon#read 3, iclass 37, count 2 2006.253.07:49:58.05#ibcon#about to read 4, iclass 37, count 2 2006.253.07:49:58.05#ibcon#read 4, iclass 37, count 2 2006.253.07:49:58.05#ibcon#about to read 5, iclass 37, count 2 2006.253.07:49:58.05#ibcon#read 5, iclass 37, count 2 2006.253.07:49:58.05#ibcon#about to read 6, iclass 37, count 2 2006.253.07:49:58.05#ibcon#read 6, iclass 37, count 2 2006.253.07:49:58.05#ibcon#end of sib2, iclass 37, count 2 2006.253.07:49:58.05#ibcon#*mode == 0, iclass 37, count 2 2006.253.07:49:58.05#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.253.07:49:58.05#ibcon#[25=AT01-08\r\n] 2006.253.07:49:58.05#ibcon#*before write, iclass 37, count 2 2006.253.07:49:58.05#ibcon#enter sib2, iclass 37, count 2 2006.253.07:49:58.05#ibcon#flushed, iclass 37, count 2 2006.253.07:49:58.05#ibcon#about to write, iclass 37, count 2 2006.253.07:49:58.05#ibcon#wrote, iclass 37, count 2 2006.253.07:49:58.05#ibcon#about to read 3, iclass 37, count 2 2006.253.07:49:58.08#ibcon#read 3, iclass 37, count 2 2006.253.07:49:58.08#ibcon#about to read 4, iclass 37, count 2 2006.253.07:49:58.08#ibcon#read 4, iclass 37, count 2 2006.253.07:49:58.08#ibcon#about to read 5, iclass 37, count 2 2006.253.07:49:58.08#ibcon#read 5, iclass 37, count 2 2006.253.07:49:58.08#ibcon#about to read 6, iclass 37, count 2 2006.253.07:49:58.08#ibcon#read 6, iclass 37, count 2 2006.253.07:49:58.08#ibcon#end of sib2, iclass 37, count 2 2006.253.07:49:58.08#ibcon#*after write, iclass 37, count 2 2006.253.07:49:58.08#ibcon#*before return 0, iclass 37, count 2 2006.253.07:49:58.08#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.253.07:49:58.08#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.253.07:49:58.08#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.253.07:49:58.08#ibcon#ireg 7 cls_cnt 0 2006.253.07:49:58.08#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.253.07:49:58.20#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.253.07:49:58.20#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.253.07:49:58.20#ibcon#enter wrdev, iclass 37, count 0 2006.253.07:49:58.20#ibcon#first serial, iclass 37, count 0 2006.253.07:49:58.20#ibcon#enter sib2, iclass 37, count 0 2006.253.07:49:58.20#ibcon#flushed, iclass 37, count 0 2006.253.07:49:58.20#ibcon#about to write, iclass 37, count 0 2006.253.07:49:58.20#ibcon#wrote, iclass 37, count 0 2006.253.07:49:58.20#ibcon#about to read 3, iclass 37, count 0 2006.253.07:49:58.22#ibcon#read 3, iclass 37, count 0 2006.253.07:49:58.22#ibcon#about to read 4, iclass 37, count 0 2006.253.07:49:58.22#ibcon#read 4, iclass 37, count 0 2006.253.07:49:58.22#ibcon#about to read 5, iclass 37, count 0 2006.253.07:49:58.22#ibcon#read 5, iclass 37, count 0 2006.253.07:49:58.22#ibcon#about to read 6, iclass 37, count 0 2006.253.07:49:58.22#ibcon#read 6, iclass 37, count 0 2006.253.07:49:58.22#ibcon#end of sib2, iclass 37, count 0 2006.253.07:49:58.22#ibcon#*mode == 0, iclass 37, count 0 2006.253.07:49:58.22#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.253.07:49:58.22#ibcon#[25=USB\r\n] 2006.253.07:49:58.22#ibcon#*before write, iclass 37, count 0 2006.253.07:49:58.22#ibcon#enter sib2, iclass 37, count 0 2006.253.07:49:58.22#ibcon#flushed, iclass 37, count 0 2006.253.07:49:58.22#ibcon#about to write, iclass 37, count 0 2006.253.07:49:58.22#ibcon#wrote, iclass 37, count 0 2006.253.07:49:58.22#ibcon#about to read 3, iclass 37, count 0 2006.253.07:49:58.25#ibcon#read 3, iclass 37, count 0 2006.253.07:49:58.25#ibcon#about to read 4, iclass 37, count 0 2006.253.07:49:58.25#ibcon#read 4, iclass 37, count 0 2006.253.07:49:58.25#ibcon#about to read 5, iclass 37, count 0 2006.253.07:49:58.25#ibcon#read 5, iclass 37, count 0 2006.253.07:49:58.25#ibcon#about to read 6, iclass 37, count 0 2006.253.07:49:58.25#ibcon#read 6, iclass 37, count 0 2006.253.07:49:58.25#ibcon#end of sib2, iclass 37, count 0 2006.253.07:49:58.25#ibcon#*after write, iclass 37, count 0 2006.253.07:49:58.25#ibcon#*before return 0, iclass 37, count 0 2006.253.07:49:58.25#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.253.07:49:58.25#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.253.07:49:58.25#ibcon#about to clear, iclass 37 cls_cnt 0 2006.253.07:49:58.25#ibcon#cleared, iclass 37 cls_cnt 0 2006.253.07:49:58.25$vc4f8/valo=2,572.99 2006.253.07:49:58.25#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.253.07:49:58.25#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.253.07:49:58.25#ibcon#ireg 17 cls_cnt 0 2006.253.07:49:58.25#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.253.07:49:58.25#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.253.07:49:58.25#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.253.07:49:58.25#ibcon#enter wrdev, iclass 39, count 0 2006.253.07:49:58.25#ibcon#first serial, iclass 39, count 0 2006.253.07:49:58.25#ibcon#enter sib2, iclass 39, count 0 2006.253.07:49:58.25#ibcon#flushed, iclass 39, count 0 2006.253.07:49:58.25#ibcon#about to write, iclass 39, count 0 2006.253.07:49:58.25#ibcon#wrote, iclass 39, count 0 2006.253.07:49:58.25#ibcon#about to read 3, iclass 39, count 0 2006.253.07:49:58.28#ibcon#read 3, iclass 39, count 0 2006.253.07:49:58.28#ibcon#about to read 4, iclass 39, count 0 2006.253.07:49:58.28#ibcon#read 4, iclass 39, count 0 2006.253.07:49:58.28#ibcon#about to read 5, iclass 39, count 0 2006.253.07:49:58.28#ibcon#read 5, iclass 39, count 0 2006.253.07:49:58.28#ibcon#about to read 6, iclass 39, count 0 2006.253.07:49:58.28#ibcon#read 6, iclass 39, count 0 2006.253.07:49:58.28#ibcon#end of sib2, iclass 39, count 0 2006.253.07:49:58.28#ibcon#*mode == 0, iclass 39, count 0 2006.253.07:49:58.28#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.253.07:49:58.28#ibcon#[26=FRQ=02,572.99\r\n] 2006.253.07:49:58.28#ibcon#*before write, iclass 39, count 0 2006.253.07:49:58.28#ibcon#enter sib2, iclass 39, count 0 2006.253.07:49:58.28#ibcon#flushed, iclass 39, count 0 2006.253.07:49:58.28#ibcon#about to write, iclass 39, count 0 2006.253.07:49:58.28#ibcon#wrote, iclass 39, count 0 2006.253.07:49:58.28#ibcon#about to read 3, iclass 39, count 0 2006.253.07:49:58.32#ibcon#read 3, iclass 39, count 0 2006.253.07:49:58.32#ibcon#about to read 4, iclass 39, count 0 2006.253.07:49:58.32#ibcon#read 4, iclass 39, count 0 2006.253.07:49:58.32#ibcon#about to read 5, iclass 39, count 0 2006.253.07:49:58.32#ibcon#read 5, iclass 39, count 0 2006.253.07:49:58.32#ibcon#about to read 6, iclass 39, count 0 2006.253.07:49:58.32#ibcon#read 6, iclass 39, count 0 2006.253.07:49:58.32#ibcon#end of sib2, iclass 39, count 0 2006.253.07:49:58.32#ibcon#*after write, iclass 39, count 0 2006.253.07:49:58.32#ibcon#*before return 0, iclass 39, count 0 2006.253.07:49:58.32#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.253.07:49:58.32#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.253.07:49:58.32#ibcon#about to clear, iclass 39 cls_cnt 0 2006.253.07:49:58.32#ibcon#cleared, iclass 39 cls_cnt 0 2006.253.07:49:58.32$vc4f8/va=2,7 2006.253.07:49:58.32#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.253.07:49:58.32#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.253.07:49:58.32#ibcon#ireg 11 cls_cnt 2 2006.253.07:49:58.32#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.253.07:49:58.38#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.253.07:49:58.38#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.253.07:49:58.38#ibcon#enter wrdev, iclass 3, count 2 2006.253.07:49:58.38#ibcon#first serial, iclass 3, count 2 2006.253.07:49:58.38#ibcon#enter sib2, iclass 3, count 2 2006.253.07:49:58.38#ibcon#flushed, iclass 3, count 2 2006.253.07:49:58.38#ibcon#about to write, iclass 3, count 2 2006.253.07:49:58.38#ibcon#wrote, iclass 3, count 2 2006.253.07:49:58.38#ibcon#about to read 3, iclass 3, count 2 2006.253.07:49:58.39#ibcon#read 3, iclass 3, count 2 2006.253.07:49:58.39#ibcon#about to read 4, iclass 3, count 2 2006.253.07:49:58.39#ibcon#read 4, iclass 3, count 2 2006.253.07:49:58.39#ibcon#about to read 5, iclass 3, count 2 2006.253.07:49:58.39#ibcon#read 5, iclass 3, count 2 2006.253.07:49:58.39#ibcon#about to read 6, iclass 3, count 2 2006.253.07:49:58.39#ibcon#read 6, iclass 3, count 2 2006.253.07:49:58.39#ibcon#end of sib2, iclass 3, count 2 2006.253.07:49:58.39#ibcon#*mode == 0, iclass 3, count 2 2006.253.07:49:58.39#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.253.07:49:58.39#ibcon#[25=AT02-07\r\n] 2006.253.07:49:58.39#ibcon#*before write, iclass 3, count 2 2006.253.07:49:58.39#ibcon#enter sib2, iclass 3, count 2 2006.253.07:49:58.39#ibcon#flushed, iclass 3, count 2 2006.253.07:49:58.39#ibcon#about to write, iclass 3, count 2 2006.253.07:49:58.39#ibcon#wrote, iclass 3, count 2 2006.253.07:49:58.39#ibcon#about to read 3, iclass 3, count 2 2006.253.07:49:58.42#ibcon#read 3, iclass 3, count 2 2006.253.07:49:58.42#ibcon#about to read 4, iclass 3, count 2 2006.253.07:49:58.42#ibcon#read 4, iclass 3, count 2 2006.253.07:49:58.42#ibcon#about to read 5, iclass 3, count 2 2006.253.07:49:58.42#ibcon#read 5, iclass 3, count 2 2006.253.07:49:58.42#ibcon#about to read 6, iclass 3, count 2 2006.253.07:49:58.42#ibcon#read 6, iclass 3, count 2 2006.253.07:49:58.42#ibcon#end of sib2, iclass 3, count 2 2006.253.07:49:58.42#ibcon#*after write, iclass 3, count 2 2006.253.07:49:58.42#ibcon#*before return 0, iclass 3, count 2 2006.253.07:49:58.42#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.253.07:49:58.42#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.253.07:49:58.42#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.253.07:49:58.42#ibcon#ireg 7 cls_cnt 0 2006.253.07:49:58.42#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.253.07:49:58.54#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.253.07:49:58.54#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.253.07:49:58.54#ibcon#enter wrdev, iclass 3, count 0 2006.253.07:49:58.54#ibcon#first serial, iclass 3, count 0 2006.253.07:49:58.54#ibcon#enter sib2, iclass 3, count 0 2006.253.07:49:58.54#ibcon#flushed, iclass 3, count 0 2006.253.07:49:58.54#ibcon#about to write, iclass 3, count 0 2006.253.07:49:58.54#ibcon#wrote, iclass 3, count 0 2006.253.07:49:58.54#ibcon#about to read 3, iclass 3, count 0 2006.253.07:49:58.56#ibcon#read 3, iclass 3, count 0 2006.253.07:49:58.56#ibcon#about to read 4, iclass 3, count 0 2006.253.07:49:58.56#ibcon#read 4, iclass 3, count 0 2006.253.07:49:58.56#ibcon#about to read 5, iclass 3, count 0 2006.253.07:49:58.56#ibcon#read 5, iclass 3, count 0 2006.253.07:49:58.56#ibcon#about to read 6, iclass 3, count 0 2006.253.07:49:58.56#ibcon#read 6, iclass 3, count 0 2006.253.07:49:58.56#ibcon#end of sib2, iclass 3, count 0 2006.253.07:49:58.56#ibcon#*mode == 0, iclass 3, count 0 2006.253.07:49:58.56#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.253.07:49:58.56#ibcon#[25=USB\r\n] 2006.253.07:49:58.56#ibcon#*before write, iclass 3, count 0 2006.253.07:49:58.56#ibcon#enter sib2, iclass 3, count 0 2006.253.07:49:58.56#ibcon#flushed, iclass 3, count 0 2006.253.07:49:58.56#ibcon#about to write, iclass 3, count 0 2006.253.07:49:58.56#ibcon#wrote, iclass 3, count 0 2006.253.07:49:58.56#ibcon#about to read 3, iclass 3, count 0 2006.253.07:49:58.59#ibcon#read 3, iclass 3, count 0 2006.253.07:49:58.59#ibcon#about to read 4, iclass 3, count 0 2006.253.07:49:58.59#ibcon#read 4, iclass 3, count 0 2006.253.07:49:58.59#ibcon#about to read 5, iclass 3, count 0 2006.253.07:49:58.59#ibcon#read 5, iclass 3, count 0 2006.253.07:49:58.59#ibcon#about to read 6, iclass 3, count 0 2006.253.07:49:58.59#ibcon#read 6, iclass 3, count 0 2006.253.07:49:58.59#ibcon#end of sib2, iclass 3, count 0 2006.253.07:49:58.59#ibcon#*after write, iclass 3, count 0 2006.253.07:49:58.59#ibcon#*before return 0, iclass 3, count 0 2006.253.07:49:58.59#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.253.07:49:58.59#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.253.07:49:58.59#ibcon#about to clear, iclass 3 cls_cnt 0 2006.253.07:49:58.59#ibcon#cleared, iclass 3 cls_cnt 0 2006.253.07:49:58.59$vc4f8/valo=3,672.99 2006.253.07:49:58.59#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.253.07:49:58.59#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.253.07:49:58.59#ibcon#ireg 17 cls_cnt 0 2006.253.07:49:58.59#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.253.07:49:58.59#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.253.07:49:58.59#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.253.07:49:58.59#ibcon#enter wrdev, iclass 5, count 0 2006.253.07:49:58.59#ibcon#first serial, iclass 5, count 0 2006.253.07:49:58.59#ibcon#enter sib2, iclass 5, count 0 2006.253.07:49:58.59#ibcon#flushed, iclass 5, count 0 2006.253.07:49:58.59#ibcon#about to write, iclass 5, count 0 2006.253.07:49:58.59#ibcon#wrote, iclass 5, count 0 2006.253.07:49:58.59#ibcon#about to read 3, iclass 5, count 0 2006.253.07:49:58.61#ibcon#read 3, iclass 5, count 0 2006.253.07:49:58.61#ibcon#about to read 4, iclass 5, count 0 2006.253.07:49:58.61#ibcon#read 4, iclass 5, count 0 2006.253.07:49:58.61#ibcon#about to read 5, iclass 5, count 0 2006.253.07:49:58.61#ibcon#read 5, iclass 5, count 0 2006.253.07:49:58.61#ibcon#about to read 6, iclass 5, count 0 2006.253.07:49:58.61#ibcon#read 6, iclass 5, count 0 2006.253.07:49:58.61#ibcon#end of sib2, iclass 5, count 0 2006.253.07:49:58.61#ibcon#*mode == 0, iclass 5, count 0 2006.253.07:49:58.61#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.253.07:49:58.61#ibcon#[26=FRQ=03,672.99\r\n] 2006.253.07:49:58.61#ibcon#*before write, iclass 5, count 0 2006.253.07:49:58.61#ibcon#enter sib2, iclass 5, count 0 2006.253.07:49:58.61#ibcon#flushed, iclass 5, count 0 2006.253.07:49:58.61#ibcon#about to write, iclass 5, count 0 2006.253.07:49:58.61#ibcon#wrote, iclass 5, count 0 2006.253.07:49:58.61#ibcon#about to read 3, iclass 5, count 0 2006.253.07:49:58.65#ibcon#read 3, iclass 5, count 0 2006.253.07:49:58.65#ibcon#about to read 4, iclass 5, count 0 2006.253.07:49:58.65#ibcon#read 4, iclass 5, count 0 2006.253.07:49:58.65#ibcon#about to read 5, iclass 5, count 0 2006.253.07:49:58.65#ibcon#read 5, iclass 5, count 0 2006.253.07:49:58.65#ibcon#about to read 6, iclass 5, count 0 2006.253.07:49:58.65#ibcon#read 6, iclass 5, count 0 2006.253.07:49:58.65#ibcon#end of sib2, iclass 5, count 0 2006.253.07:49:58.65#ibcon#*after write, iclass 5, count 0 2006.253.07:49:58.65#ibcon#*before return 0, iclass 5, count 0 2006.253.07:49:58.65#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.253.07:49:58.65#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.253.07:49:58.65#ibcon#about to clear, iclass 5 cls_cnt 0 2006.253.07:49:58.65#ibcon#cleared, iclass 5 cls_cnt 0 2006.253.07:49:58.65$vc4f8/va=3,6 2006.253.07:49:58.65#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.253.07:49:58.65#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.253.07:49:58.65#ibcon#ireg 11 cls_cnt 2 2006.253.07:49:58.65#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.253.07:49:58.72#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.253.07:49:58.72#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.253.07:49:58.72#ibcon#enter wrdev, iclass 7, count 2 2006.253.07:49:58.72#ibcon#first serial, iclass 7, count 2 2006.253.07:49:58.72#ibcon#enter sib2, iclass 7, count 2 2006.253.07:49:58.72#ibcon#flushed, iclass 7, count 2 2006.253.07:49:58.72#ibcon#about to write, iclass 7, count 2 2006.253.07:49:58.72#ibcon#wrote, iclass 7, count 2 2006.253.07:49:58.72#ibcon#about to read 3, iclass 7, count 2 2006.253.07:49:58.73#ibcon#read 3, iclass 7, count 2 2006.253.07:49:58.73#ibcon#about to read 4, iclass 7, count 2 2006.253.07:49:58.73#ibcon#read 4, iclass 7, count 2 2006.253.07:49:58.73#ibcon#about to read 5, iclass 7, count 2 2006.253.07:49:58.73#ibcon#read 5, iclass 7, count 2 2006.253.07:49:58.73#ibcon#about to read 6, iclass 7, count 2 2006.253.07:49:58.73#ibcon#read 6, iclass 7, count 2 2006.253.07:49:58.73#ibcon#end of sib2, iclass 7, count 2 2006.253.07:49:58.73#ibcon#*mode == 0, iclass 7, count 2 2006.253.07:49:58.73#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.253.07:49:58.73#ibcon#[25=AT03-06\r\n] 2006.253.07:49:58.73#ibcon#*before write, iclass 7, count 2 2006.253.07:49:58.73#ibcon#enter sib2, iclass 7, count 2 2006.253.07:49:58.73#ibcon#flushed, iclass 7, count 2 2006.253.07:49:58.73#ibcon#about to write, iclass 7, count 2 2006.253.07:49:58.73#ibcon#wrote, iclass 7, count 2 2006.253.07:49:58.73#ibcon#about to read 3, iclass 7, count 2 2006.253.07:49:58.76#ibcon#read 3, iclass 7, count 2 2006.253.07:49:58.76#ibcon#about to read 4, iclass 7, count 2 2006.253.07:49:58.76#ibcon#read 4, iclass 7, count 2 2006.253.07:49:58.76#ibcon#about to read 5, iclass 7, count 2 2006.253.07:49:58.76#ibcon#read 5, iclass 7, count 2 2006.253.07:49:58.76#ibcon#about to read 6, iclass 7, count 2 2006.253.07:49:58.76#ibcon#read 6, iclass 7, count 2 2006.253.07:49:58.76#ibcon#end of sib2, iclass 7, count 2 2006.253.07:49:58.76#ibcon#*after write, iclass 7, count 2 2006.253.07:49:58.76#ibcon#*before return 0, iclass 7, count 2 2006.253.07:49:58.76#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.253.07:49:58.76#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.253.07:49:58.76#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.253.07:49:58.76#ibcon#ireg 7 cls_cnt 0 2006.253.07:49:58.76#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.253.07:49:58.88#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.253.07:49:58.88#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.253.07:49:58.88#ibcon#enter wrdev, iclass 7, count 0 2006.253.07:49:58.88#ibcon#first serial, iclass 7, count 0 2006.253.07:49:58.88#ibcon#enter sib2, iclass 7, count 0 2006.253.07:49:58.88#ibcon#flushed, iclass 7, count 0 2006.253.07:49:58.88#ibcon#about to write, iclass 7, count 0 2006.253.07:49:58.88#ibcon#wrote, iclass 7, count 0 2006.253.07:49:58.88#ibcon#about to read 3, iclass 7, count 0 2006.253.07:49:58.90#ibcon#read 3, iclass 7, count 0 2006.253.07:49:58.90#ibcon#about to read 4, iclass 7, count 0 2006.253.07:49:58.90#ibcon#read 4, iclass 7, count 0 2006.253.07:49:58.90#ibcon#about to read 5, iclass 7, count 0 2006.253.07:49:58.90#ibcon#read 5, iclass 7, count 0 2006.253.07:49:58.90#ibcon#about to read 6, iclass 7, count 0 2006.253.07:49:58.90#ibcon#read 6, iclass 7, count 0 2006.253.07:49:58.90#ibcon#end of sib2, iclass 7, count 0 2006.253.07:49:58.90#ibcon#*mode == 0, iclass 7, count 0 2006.253.07:49:58.90#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.253.07:49:58.90#ibcon#[25=USB\r\n] 2006.253.07:49:58.90#ibcon#*before write, iclass 7, count 0 2006.253.07:49:58.90#ibcon#enter sib2, iclass 7, count 0 2006.253.07:49:58.90#ibcon#flushed, iclass 7, count 0 2006.253.07:49:58.90#ibcon#about to write, iclass 7, count 0 2006.253.07:49:58.90#ibcon#wrote, iclass 7, count 0 2006.253.07:49:58.90#ibcon#about to read 3, iclass 7, count 0 2006.253.07:49:58.93#ibcon#read 3, iclass 7, count 0 2006.253.07:49:58.93#ibcon#about to read 4, iclass 7, count 0 2006.253.07:49:58.93#ibcon#read 4, iclass 7, count 0 2006.253.07:49:58.93#ibcon#about to read 5, iclass 7, count 0 2006.253.07:49:58.93#ibcon#read 5, iclass 7, count 0 2006.253.07:49:58.93#ibcon#about to read 6, iclass 7, count 0 2006.253.07:49:58.93#ibcon#read 6, iclass 7, count 0 2006.253.07:49:58.93#ibcon#end of sib2, iclass 7, count 0 2006.253.07:49:58.93#ibcon#*after write, iclass 7, count 0 2006.253.07:49:58.93#ibcon#*before return 0, iclass 7, count 0 2006.253.07:49:58.93#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.253.07:49:58.93#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.253.07:49:58.93#ibcon#about to clear, iclass 7 cls_cnt 0 2006.253.07:49:58.93#ibcon#cleared, iclass 7 cls_cnt 0 2006.253.07:49:58.93$vc4f8/valo=4,832.99 2006.253.07:49:58.93#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.253.07:49:58.93#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.253.07:49:58.93#ibcon#ireg 17 cls_cnt 0 2006.253.07:49:58.93#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.253.07:49:58.93#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.253.07:49:58.93#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.253.07:49:58.93#ibcon#enter wrdev, iclass 11, count 0 2006.253.07:49:58.93#ibcon#first serial, iclass 11, count 0 2006.253.07:49:58.93#ibcon#enter sib2, iclass 11, count 0 2006.253.07:49:58.93#ibcon#flushed, iclass 11, count 0 2006.253.07:49:58.93#ibcon#about to write, iclass 11, count 0 2006.253.07:49:58.93#ibcon#wrote, iclass 11, count 0 2006.253.07:49:58.93#ibcon#about to read 3, iclass 11, count 0 2006.253.07:49:58.95#ibcon#read 3, iclass 11, count 0 2006.253.07:49:58.95#ibcon#about to read 4, iclass 11, count 0 2006.253.07:49:58.95#ibcon#read 4, iclass 11, count 0 2006.253.07:49:58.95#ibcon#about to read 5, iclass 11, count 0 2006.253.07:49:58.95#ibcon#read 5, iclass 11, count 0 2006.253.07:49:58.95#ibcon#about to read 6, iclass 11, count 0 2006.253.07:49:58.95#ibcon#read 6, iclass 11, count 0 2006.253.07:49:58.95#ibcon#end of sib2, iclass 11, count 0 2006.253.07:49:58.95#ibcon#*mode == 0, iclass 11, count 0 2006.253.07:49:58.95#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.253.07:49:58.95#ibcon#[26=FRQ=04,832.99\r\n] 2006.253.07:49:58.95#ibcon#*before write, iclass 11, count 0 2006.253.07:49:58.95#ibcon#enter sib2, iclass 11, count 0 2006.253.07:49:58.95#ibcon#flushed, iclass 11, count 0 2006.253.07:49:58.95#ibcon#about to write, iclass 11, count 0 2006.253.07:49:58.95#ibcon#wrote, iclass 11, count 0 2006.253.07:49:58.95#ibcon#about to read 3, iclass 11, count 0 2006.253.07:49:58.99#ibcon#read 3, iclass 11, count 0 2006.253.07:49:58.99#ibcon#about to read 4, iclass 11, count 0 2006.253.07:49:58.99#ibcon#read 4, iclass 11, count 0 2006.253.07:49:58.99#ibcon#about to read 5, iclass 11, count 0 2006.253.07:49:58.99#ibcon#read 5, iclass 11, count 0 2006.253.07:49:58.99#ibcon#about to read 6, iclass 11, count 0 2006.253.07:49:58.99#ibcon#read 6, iclass 11, count 0 2006.253.07:49:58.99#ibcon#end of sib2, iclass 11, count 0 2006.253.07:49:58.99#ibcon#*after write, iclass 11, count 0 2006.253.07:49:58.99#ibcon#*before return 0, iclass 11, count 0 2006.253.07:49:58.99#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.253.07:49:58.99#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.253.07:49:58.99#ibcon#about to clear, iclass 11 cls_cnt 0 2006.253.07:49:58.99#ibcon#cleared, iclass 11 cls_cnt 0 2006.253.07:49:58.99$vc4f8/va=4,7 2006.253.07:49:58.99#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.253.07:49:58.99#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.253.07:49:58.99#ibcon#ireg 11 cls_cnt 2 2006.253.07:49:58.99#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.253.07:49:59.06#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.253.07:49:59.06#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.253.07:49:59.06#ibcon#enter wrdev, iclass 13, count 2 2006.253.07:49:59.06#ibcon#first serial, iclass 13, count 2 2006.253.07:49:59.06#ibcon#enter sib2, iclass 13, count 2 2006.253.07:49:59.06#ibcon#flushed, iclass 13, count 2 2006.253.07:49:59.06#ibcon#about to write, iclass 13, count 2 2006.253.07:49:59.06#ibcon#wrote, iclass 13, count 2 2006.253.07:49:59.06#ibcon#about to read 3, iclass 13, count 2 2006.253.07:49:59.07#ibcon#read 3, iclass 13, count 2 2006.253.07:49:59.07#ibcon#about to read 4, iclass 13, count 2 2006.253.07:49:59.07#ibcon#read 4, iclass 13, count 2 2006.253.07:49:59.07#ibcon#about to read 5, iclass 13, count 2 2006.253.07:49:59.07#ibcon#read 5, iclass 13, count 2 2006.253.07:49:59.07#ibcon#about to read 6, iclass 13, count 2 2006.253.07:49:59.07#ibcon#read 6, iclass 13, count 2 2006.253.07:49:59.07#ibcon#end of sib2, iclass 13, count 2 2006.253.07:49:59.07#ibcon#*mode == 0, iclass 13, count 2 2006.253.07:49:59.07#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.253.07:49:59.07#ibcon#[25=AT04-07\r\n] 2006.253.07:49:59.07#ibcon#*before write, iclass 13, count 2 2006.253.07:49:59.07#ibcon#enter sib2, iclass 13, count 2 2006.253.07:49:59.07#ibcon#flushed, iclass 13, count 2 2006.253.07:49:59.07#ibcon#about to write, iclass 13, count 2 2006.253.07:49:59.07#ibcon#wrote, iclass 13, count 2 2006.253.07:49:59.07#ibcon#about to read 3, iclass 13, count 2 2006.253.07:49:59.10#ibcon#read 3, iclass 13, count 2 2006.253.07:49:59.10#ibcon#about to read 4, iclass 13, count 2 2006.253.07:49:59.10#ibcon#read 4, iclass 13, count 2 2006.253.07:49:59.10#ibcon#about to read 5, iclass 13, count 2 2006.253.07:49:59.10#ibcon#read 5, iclass 13, count 2 2006.253.07:49:59.10#ibcon#about to read 6, iclass 13, count 2 2006.253.07:49:59.10#ibcon#read 6, iclass 13, count 2 2006.253.07:49:59.10#ibcon#end of sib2, iclass 13, count 2 2006.253.07:49:59.10#ibcon#*after write, iclass 13, count 2 2006.253.07:49:59.10#ibcon#*before return 0, iclass 13, count 2 2006.253.07:49:59.10#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.253.07:49:59.10#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.253.07:49:59.10#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.253.07:49:59.10#ibcon#ireg 7 cls_cnt 0 2006.253.07:49:59.10#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.253.07:49:59.22#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.253.07:49:59.22#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.253.07:49:59.22#ibcon#enter wrdev, iclass 13, count 0 2006.253.07:49:59.22#ibcon#first serial, iclass 13, count 0 2006.253.07:49:59.22#ibcon#enter sib2, iclass 13, count 0 2006.253.07:49:59.22#ibcon#flushed, iclass 13, count 0 2006.253.07:49:59.22#ibcon#about to write, iclass 13, count 0 2006.253.07:49:59.22#ibcon#wrote, iclass 13, count 0 2006.253.07:49:59.22#ibcon#about to read 3, iclass 13, count 0 2006.253.07:49:59.24#ibcon#read 3, iclass 13, count 0 2006.253.07:49:59.24#ibcon#about to read 4, iclass 13, count 0 2006.253.07:49:59.24#ibcon#read 4, iclass 13, count 0 2006.253.07:49:59.24#ibcon#about to read 5, iclass 13, count 0 2006.253.07:49:59.24#ibcon#read 5, iclass 13, count 0 2006.253.07:49:59.24#ibcon#about to read 6, iclass 13, count 0 2006.253.07:49:59.24#ibcon#read 6, iclass 13, count 0 2006.253.07:49:59.24#ibcon#end of sib2, iclass 13, count 0 2006.253.07:49:59.24#ibcon#*mode == 0, iclass 13, count 0 2006.253.07:49:59.24#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.253.07:49:59.24#ibcon#[25=USB\r\n] 2006.253.07:49:59.24#ibcon#*before write, iclass 13, count 0 2006.253.07:49:59.24#ibcon#enter sib2, iclass 13, count 0 2006.253.07:49:59.24#ibcon#flushed, iclass 13, count 0 2006.253.07:49:59.24#ibcon#about to write, iclass 13, count 0 2006.253.07:49:59.24#ibcon#wrote, iclass 13, count 0 2006.253.07:49:59.24#ibcon#about to read 3, iclass 13, count 0 2006.253.07:49:59.27#ibcon#read 3, iclass 13, count 0 2006.253.07:49:59.27#ibcon#about to read 4, iclass 13, count 0 2006.253.07:49:59.27#ibcon#read 4, iclass 13, count 0 2006.253.07:49:59.27#ibcon#about to read 5, iclass 13, count 0 2006.253.07:49:59.27#ibcon#read 5, iclass 13, count 0 2006.253.07:49:59.27#ibcon#about to read 6, iclass 13, count 0 2006.253.07:49:59.27#ibcon#read 6, iclass 13, count 0 2006.253.07:49:59.27#ibcon#end of sib2, iclass 13, count 0 2006.253.07:49:59.27#ibcon#*after write, iclass 13, count 0 2006.253.07:49:59.27#ibcon#*before return 0, iclass 13, count 0 2006.253.07:49:59.27#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.253.07:49:59.27#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.253.07:49:59.27#ibcon#about to clear, iclass 13 cls_cnt 0 2006.253.07:49:59.27#ibcon#cleared, iclass 13 cls_cnt 0 2006.253.07:49:59.27$vc4f8/valo=5,652.99 2006.253.07:49:59.27#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.253.07:49:59.27#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.253.07:49:59.27#ibcon#ireg 17 cls_cnt 0 2006.253.07:49:59.27#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.253.07:49:59.27#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.253.07:49:59.27#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.253.07:49:59.27#ibcon#enter wrdev, iclass 15, count 0 2006.253.07:49:59.27#ibcon#first serial, iclass 15, count 0 2006.253.07:49:59.27#ibcon#enter sib2, iclass 15, count 0 2006.253.07:49:59.27#ibcon#flushed, iclass 15, count 0 2006.253.07:49:59.27#ibcon#about to write, iclass 15, count 0 2006.253.07:49:59.27#ibcon#wrote, iclass 15, count 0 2006.253.07:49:59.27#ibcon#about to read 3, iclass 15, count 0 2006.253.07:49:59.29#ibcon#read 3, iclass 15, count 0 2006.253.07:49:59.29#ibcon#about to read 4, iclass 15, count 0 2006.253.07:49:59.29#ibcon#read 4, iclass 15, count 0 2006.253.07:49:59.29#ibcon#about to read 5, iclass 15, count 0 2006.253.07:49:59.29#ibcon#read 5, iclass 15, count 0 2006.253.07:49:59.29#ibcon#about to read 6, iclass 15, count 0 2006.253.07:49:59.29#ibcon#read 6, iclass 15, count 0 2006.253.07:49:59.29#ibcon#end of sib2, iclass 15, count 0 2006.253.07:49:59.29#ibcon#*mode == 0, iclass 15, count 0 2006.253.07:49:59.29#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.253.07:49:59.29#ibcon#[26=FRQ=05,652.99\r\n] 2006.253.07:49:59.29#ibcon#*before write, iclass 15, count 0 2006.253.07:49:59.29#ibcon#enter sib2, iclass 15, count 0 2006.253.07:49:59.29#ibcon#flushed, iclass 15, count 0 2006.253.07:49:59.29#ibcon#about to write, iclass 15, count 0 2006.253.07:49:59.29#ibcon#wrote, iclass 15, count 0 2006.253.07:49:59.29#ibcon#about to read 3, iclass 15, count 0 2006.253.07:49:59.33#ibcon#read 3, iclass 15, count 0 2006.253.07:49:59.33#ibcon#about to read 4, iclass 15, count 0 2006.253.07:49:59.33#ibcon#read 4, iclass 15, count 0 2006.253.07:49:59.33#ibcon#about to read 5, iclass 15, count 0 2006.253.07:49:59.33#ibcon#read 5, iclass 15, count 0 2006.253.07:49:59.33#ibcon#about to read 6, iclass 15, count 0 2006.253.07:49:59.33#ibcon#read 6, iclass 15, count 0 2006.253.07:49:59.33#ibcon#end of sib2, iclass 15, count 0 2006.253.07:49:59.33#ibcon#*after write, iclass 15, count 0 2006.253.07:49:59.33#ibcon#*before return 0, iclass 15, count 0 2006.253.07:49:59.33#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.253.07:49:59.33#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.253.07:49:59.33#ibcon#about to clear, iclass 15 cls_cnt 0 2006.253.07:49:59.33#ibcon#cleared, iclass 15 cls_cnt 0 2006.253.07:49:59.33$vc4f8/va=5,7 2006.253.07:49:59.33#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.253.07:49:59.33#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.253.07:49:59.33#ibcon#ireg 11 cls_cnt 2 2006.253.07:49:59.33#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.253.07:49:59.39#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.253.07:49:59.39#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.253.07:49:59.39#ibcon#enter wrdev, iclass 17, count 2 2006.253.07:49:59.39#ibcon#first serial, iclass 17, count 2 2006.253.07:49:59.39#ibcon#enter sib2, iclass 17, count 2 2006.253.07:49:59.39#ibcon#flushed, iclass 17, count 2 2006.253.07:49:59.39#ibcon#about to write, iclass 17, count 2 2006.253.07:49:59.39#ibcon#wrote, iclass 17, count 2 2006.253.07:49:59.39#ibcon#about to read 3, iclass 17, count 2 2006.253.07:49:59.41#ibcon#read 3, iclass 17, count 2 2006.253.07:49:59.41#ibcon#about to read 4, iclass 17, count 2 2006.253.07:49:59.41#ibcon#read 4, iclass 17, count 2 2006.253.07:49:59.41#ibcon#about to read 5, iclass 17, count 2 2006.253.07:49:59.41#ibcon#read 5, iclass 17, count 2 2006.253.07:49:59.41#ibcon#about to read 6, iclass 17, count 2 2006.253.07:49:59.41#ibcon#read 6, iclass 17, count 2 2006.253.07:49:59.41#ibcon#end of sib2, iclass 17, count 2 2006.253.07:49:59.41#ibcon#*mode == 0, iclass 17, count 2 2006.253.07:49:59.41#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.253.07:49:59.41#ibcon#[25=AT05-07\r\n] 2006.253.07:49:59.41#ibcon#*before write, iclass 17, count 2 2006.253.07:49:59.41#ibcon#enter sib2, iclass 17, count 2 2006.253.07:49:59.41#ibcon#flushed, iclass 17, count 2 2006.253.07:49:59.41#ibcon#about to write, iclass 17, count 2 2006.253.07:49:59.41#ibcon#wrote, iclass 17, count 2 2006.253.07:49:59.41#ibcon#about to read 3, iclass 17, count 2 2006.253.07:49:59.44#ibcon#read 3, iclass 17, count 2 2006.253.07:49:59.44#ibcon#about to read 4, iclass 17, count 2 2006.253.07:49:59.44#ibcon#read 4, iclass 17, count 2 2006.253.07:49:59.44#ibcon#about to read 5, iclass 17, count 2 2006.253.07:49:59.44#ibcon#read 5, iclass 17, count 2 2006.253.07:49:59.44#ibcon#about to read 6, iclass 17, count 2 2006.253.07:49:59.44#ibcon#read 6, iclass 17, count 2 2006.253.07:49:59.44#ibcon#end of sib2, iclass 17, count 2 2006.253.07:49:59.44#ibcon#*after write, iclass 17, count 2 2006.253.07:49:59.44#ibcon#*before return 0, iclass 17, count 2 2006.253.07:49:59.44#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.253.07:49:59.44#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.253.07:49:59.44#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.253.07:49:59.44#ibcon#ireg 7 cls_cnt 0 2006.253.07:49:59.44#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.253.07:49:59.56#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.253.07:49:59.56#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.253.07:49:59.56#ibcon#enter wrdev, iclass 17, count 0 2006.253.07:49:59.56#ibcon#first serial, iclass 17, count 0 2006.253.07:49:59.56#ibcon#enter sib2, iclass 17, count 0 2006.253.07:49:59.56#ibcon#flushed, iclass 17, count 0 2006.253.07:49:59.56#ibcon#about to write, iclass 17, count 0 2006.253.07:49:59.56#ibcon#wrote, iclass 17, count 0 2006.253.07:49:59.56#ibcon#about to read 3, iclass 17, count 0 2006.253.07:49:59.58#ibcon#read 3, iclass 17, count 0 2006.253.07:49:59.58#ibcon#about to read 4, iclass 17, count 0 2006.253.07:49:59.58#ibcon#read 4, iclass 17, count 0 2006.253.07:49:59.58#ibcon#about to read 5, iclass 17, count 0 2006.253.07:49:59.58#ibcon#read 5, iclass 17, count 0 2006.253.07:49:59.58#ibcon#about to read 6, iclass 17, count 0 2006.253.07:49:59.58#ibcon#read 6, iclass 17, count 0 2006.253.07:49:59.58#ibcon#end of sib2, iclass 17, count 0 2006.253.07:49:59.58#ibcon#*mode == 0, iclass 17, count 0 2006.253.07:49:59.58#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.253.07:49:59.58#ibcon#[25=USB\r\n] 2006.253.07:49:59.58#ibcon#*before write, iclass 17, count 0 2006.253.07:49:59.58#ibcon#enter sib2, iclass 17, count 0 2006.253.07:49:59.58#ibcon#flushed, iclass 17, count 0 2006.253.07:49:59.58#ibcon#about to write, iclass 17, count 0 2006.253.07:49:59.58#ibcon#wrote, iclass 17, count 0 2006.253.07:49:59.58#ibcon#about to read 3, iclass 17, count 0 2006.253.07:49:59.61#ibcon#read 3, iclass 17, count 0 2006.253.07:49:59.61#ibcon#about to read 4, iclass 17, count 0 2006.253.07:49:59.61#ibcon#read 4, iclass 17, count 0 2006.253.07:49:59.61#ibcon#about to read 5, iclass 17, count 0 2006.253.07:49:59.61#ibcon#read 5, iclass 17, count 0 2006.253.07:49:59.61#ibcon#about to read 6, iclass 17, count 0 2006.253.07:49:59.61#ibcon#read 6, iclass 17, count 0 2006.253.07:49:59.61#ibcon#end of sib2, iclass 17, count 0 2006.253.07:49:59.61#ibcon#*after write, iclass 17, count 0 2006.253.07:49:59.61#ibcon#*before return 0, iclass 17, count 0 2006.253.07:49:59.61#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.253.07:49:59.61#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.253.07:49:59.61#ibcon#about to clear, iclass 17 cls_cnt 0 2006.253.07:49:59.61#ibcon#cleared, iclass 17 cls_cnt 0 2006.253.07:49:59.61$vc4f8/valo=6,772.99 2006.253.07:49:59.61#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.253.07:49:59.61#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.253.07:49:59.61#ibcon#ireg 17 cls_cnt 0 2006.253.07:49:59.61#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.253.07:49:59.61#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.253.07:49:59.61#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.253.07:49:59.61#ibcon#enter wrdev, iclass 19, count 0 2006.253.07:49:59.61#ibcon#first serial, iclass 19, count 0 2006.253.07:49:59.61#ibcon#enter sib2, iclass 19, count 0 2006.253.07:49:59.61#ibcon#flushed, iclass 19, count 0 2006.253.07:49:59.61#ibcon#about to write, iclass 19, count 0 2006.253.07:49:59.61#ibcon#wrote, iclass 19, count 0 2006.253.07:49:59.61#ibcon#about to read 3, iclass 19, count 0 2006.253.07:49:59.63#ibcon#read 3, iclass 19, count 0 2006.253.07:49:59.63#ibcon#about to read 4, iclass 19, count 0 2006.253.07:49:59.63#ibcon#read 4, iclass 19, count 0 2006.253.07:49:59.63#ibcon#about to read 5, iclass 19, count 0 2006.253.07:49:59.63#ibcon#read 5, iclass 19, count 0 2006.253.07:49:59.63#ibcon#about to read 6, iclass 19, count 0 2006.253.07:49:59.63#ibcon#read 6, iclass 19, count 0 2006.253.07:49:59.63#ibcon#end of sib2, iclass 19, count 0 2006.253.07:49:59.63#ibcon#*mode == 0, iclass 19, count 0 2006.253.07:49:59.63#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.253.07:49:59.63#ibcon#[26=FRQ=06,772.99\r\n] 2006.253.07:49:59.63#ibcon#*before write, iclass 19, count 0 2006.253.07:49:59.63#ibcon#enter sib2, iclass 19, count 0 2006.253.07:49:59.63#ibcon#flushed, iclass 19, count 0 2006.253.07:49:59.63#ibcon#about to write, iclass 19, count 0 2006.253.07:49:59.63#ibcon#wrote, iclass 19, count 0 2006.253.07:49:59.63#ibcon#about to read 3, iclass 19, count 0 2006.253.07:49:59.67#ibcon#read 3, iclass 19, count 0 2006.253.07:49:59.67#ibcon#about to read 4, iclass 19, count 0 2006.253.07:49:59.67#ibcon#read 4, iclass 19, count 0 2006.253.07:49:59.67#ibcon#about to read 5, iclass 19, count 0 2006.253.07:49:59.67#ibcon#read 5, iclass 19, count 0 2006.253.07:49:59.67#ibcon#about to read 6, iclass 19, count 0 2006.253.07:49:59.67#ibcon#read 6, iclass 19, count 0 2006.253.07:49:59.67#ibcon#end of sib2, iclass 19, count 0 2006.253.07:49:59.67#ibcon#*after write, iclass 19, count 0 2006.253.07:49:59.67#ibcon#*before return 0, iclass 19, count 0 2006.253.07:49:59.67#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.253.07:49:59.67#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.253.07:49:59.67#ibcon#about to clear, iclass 19 cls_cnt 0 2006.253.07:49:59.67#ibcon#cleared, iclass 19 cls_cnt 0 2006.253.07:49:59.67$vc4f8/va=6,7 2006.253.07:49:59.67#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.253.07:49:59.67#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.253.07:49:59.67#ibcon#ireg 11 cls_cnt 2 2006.253.07:49:59.67#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.253.07:49:59.74#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.253.07:49:59.74#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.253.07:49:59.74#ibcon#enter wrdev, iclass 21, count 2 2006.253.07:49:59.74#ibcon#first serial, iclass 21, count 2 2006.253.07:49:59.74#ibcon#enter sib2, iclass 21, count 2 2006.253.07:49:59.74#ibcon#flushed, iclass 21, count 2 2006.253.07:49:59.74#ibcon#about to write, iclass 21, count 2 2006.253.07:49:59.74#ibcon#wrote, iclass 21, count 2 2006.253.07:49:59.74#ibcon#about to read 3, iclass 21, count 2 2006.253.07:49:59.75#ibcon#read 3, iclass 21, count 2 2006.253.07:49:59.75#ibcon#about to read 4, iclass 21, count 2 2006.253.07:49:59.75#ibcon#read 4, iclass 21, count 2 2006.253.07:49:59.75#ibcon#about to read 5, iclass 21, count 2 2006.253.07:49:59.75#ibcon#read 5, iclass 21, count 2 2006.253.07:49:59.75#ibcon#about to read 6, iclass 21, count 2 2006.253.07:49:59.75#ibcon#read 6, iclass 21, count 2 2006.253.07:49:59.75#ibcon#end of sib2, iclass 21, count 2 2006.253.07:49:59.75#ibcon#*mode == 0, iclass 21, count 2 2006.253.07:49:59.75#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.253.07:49:59.75#ibcon#[25=AT06-07\r\n] 2006.253.07:49:59.75#ibcon#*before write, iclass 21, count 2 2006.253.07:49:59.75#ibcon#enter sib2, iclass 21, count 2 2006.253.07:49:59.75#ibcon#flushed, iclass 21, count 2 2006.253.07:49:59.75#ibcon#about to write, iclass 21, count 2 2006.253.07:49:59.75#ibcon#wrote, iclass 21, count 2 2006.253.07:49:59.75#ibcon#about to read 3, iclass 21, count 2 2006.253.07:49:59.78#ibcon#read 3, iclass 21, count 2 2006.253.07:49:59.78#ibcon#about to read 4, iclass 21, count 2 2006.253.07:49:59.78#ibcon#read 4, iclass 21, count 2 2006.253.07:49:59.78#ibcon#about to read 5, iclass 21, count 2 2006.253.07:49:59.78#ibcon#read 5, iclass 21, count 2 2006.253.07:49:59.78#ibcon#about to read 6, iclass 21, count 2 2006.253.07:49:59.78#ibcon#read 6, iclass 21, count 2 2006.253.07:49:59.78#ibcon#end of sib2, iclass 21, count 2 2006.253.07:49:59.78#ibcon#*after write, iclass 21, count 2 2006.253.07:49:59.78#ibcon#*before return 0, iclass 21, count 2 2006.253.07:49:59.78#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.253.07:49:59.78#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.253.07:49:59.78#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.253.07:49:59.78#ibcon#ireg 7 cls_cnt 0 2006.253.07:49:59.78#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.253.07:49:59.90#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.253.07:49:59.90#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.253.07:49:59.90#ibcon#enter wrdev, iclass 21, count 0 2006.253.07:49:59.90#ibcon#first serial, iclass 21, count 0 2006.253.07:49:59.90#ibcon#enter sib2, iclass 21, count 0 2006.253.07:49:59.90#ibcon#flushed, iclass 21, count 0 2006.253.07:49:59.90#ibcon#about to write, iclass 21, count 0 2006.253.07:49:59.90#ibcon#wrote, iclass 21, count 0 2006.253.07:49:59.90#ibcon#about to read 3, iclass 21, count 0 2006.253.07:49:59.92#ibcon#read 3, iclass 21, count 0 2006.253.07:49:59.92#ibcon#about to read 4, iclass 21, count 0 2006.253.07:49:59.92#ibcon#read 4, iclass 21, count 0 2006.253.07:49:59.92#ibcon#about to read 5, iclass 21, count 0 2006.253.07:49:59.92#ibcon#read 5, iclass 21, count 0 2006.253.07:49:59.92#ibcon#about to read 6, iclass 21, count 0 2006.253.07:49:59.92#ibcon#read 6, iclass 21, count 0 2006.253.07:49:59.92#ibcon#end of sib2, iclass 21, count 0 2006.253.07:49:59.92#ibcon#*mode == 0, iclass 21, count 0 2006.253.07:49:59.92#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.253.07:49:59.92#ibcon#[25=USB\r\n] 2006.253.07:49:59.92#ibcon#*before write, iclass 21, count 0 2006.253.07:49:59.92#ibcon#enter sib2, iclass 21, count 0 2006.253.07:49:59.92#ibcon#flushed, iclass 21, count 0 2006.253.07:49:59.92#ibcon#about to write, iclass 21, count 0 2006.253.07:49:59.92#ibcon#wrote, iclass 21, count 0 2006.253.07:49:59.92#ibcon#about to read 3, iclass 21, count 0 2006.253.07:49:59.95#ibcon#read 3, iclass 21, count 0 2006.253.07:49:59.95#ibcon#about to read 4, iclass 21, count 0 2006.253.07:49:59.95#ibcon#read 4, iclass 21, count 0 2006.253.07:49:59.95#ibcon#about to read 5, iclass 21, count 0 2006.253.07:49:59.95#ibcon#read 5, iclass 21, count 0 2006.253.07:49:59.95#ibcon#about to read 6, iclass 21, count 0 2006.253.07:49:59.95#ibcon#read 6, iclass 21, count 0 2006.253.07:49:59.95#ibcon#end of sib2, iclass 21, count 0 2006.253.07:49:59.95#ibcon#*after write, iclass 21, count 0 2006.253.07:49:59.95#ibcon#*before return 0, iclass 21, count 0 2006.253.07:49:59.95#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.253.07:49:59.95#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.253.07:49:59.95#ibcon#about to clear, iclass 21 cls_cnt 0 2006.253.07:49:59.95#ibcon#cleared, iclass 21 cls_cnt 0 2006.253.07:49:59.95$vc4f8/valo=7,832.99 2006.253.07:49:59.95#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.253.07:49:59.95#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.253.07:49:59.95#ibcon#ireg 17 cls_cnt 0 2006.253.07:49:59.95#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.253.07:49:59.95#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.253.07:49:59.95#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.253.07:49:59.95#ibcon#enter wrdev, iclass 23, count 0 2006.253.07:49:59.95#ibcon#first serial, iclass 23, count 0 2006.253.07:49:59.95#ibcon#enter sib2, iclass 23, count 0 2006.253.07:49:59.95#ibcon#flushed, iclass 23, count 0 2006.253.07:49:59.95#ibcon#about to write, iclass 23, count 0 2006.253.07:49:59.95#ibcon#wrote, iclass 23, count 0 2006.253.07:49:59.95#ibcon#about to read 3, iclass 23, count 0 2006.253.07:49:59.97#ibcon#read 3, iclass 23, count 0 2006.253.07:49:59.97#ibcon#about to read 4, iclass 23, count 0 2006.253.07:49:59.97#ibcon#read 4, iclass 23, count 0 2006.253.07:49:59.97#ibcon#about to read 5, iclass 23, count 0 2006.253.07:49:59.97#ibcon#read 5, iclass 23, count 0 2006.253.07:49:59.97#ibcon#about to read 6, iclass 23, count 0 2006.253.07:49:59.97#ibcon#read 6, iclass 23, count 0 2006.253.07:49:59.97#ibcon#end of sib2, iclass 23, count 0 2006.253.07:49:59.97#ibcon#*mode == 0, iclass 23, count 0 2006.253.07:49:59.97#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.253.07:49:59.97#ibcon#[26=FRQ=07,832.99\r\n] 2006.253.07:49:59.97#ibcon#*before write, iclass 23, count 0 2006.253.07:49:59.97#ibcon#enter sib2, iclass 23, count 0 2006.253.07:49:59.97#ibcon#flushed, iclass 23, count 0 2006.253.07:49:59.97#ibcon#about to write, iclass 23, count 0 2006.253.07:49:59.97#ibcon#wrote, iclass 23, count 0 2006.253.07:49:59.97#ibcon#about to read 3, iclass 23, count 0 2006.253.07:50:00.01#ibcon#read 3, iclass 23, count 0 2006.253.07:50:00.01#ibcon#about to read 4, iclass 23, count 0 2006.253.07:50:00.01#ibcon#read 4, iclass 23, count 0 2006.253.07:50:00.01#ibcon#about to read 5, iclass 23, count 0 2006.253.07:50:00.01#ibcon#read 5, iclass 23, count 0 2006.253.07:50:00.01#ibcon#about to read 6, iclass 23, count 0 2006.253.07:50:00.01#ibcon#read 6, iclass 23, count 0 2006.253.07:50:00.01#ibcon#end of sib2, iclass 23, count 0 2006.253.07:50:00.01#ibcon#*after write, iclass 23, count 0 2006.253.07:50:00.01#ibcon#*before return 0, iclass 23, count 0 2006.253.07:50:00.01#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.253.07:50:00.01#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.253.07:50:00.01#ibcon#about to clear, iclass 23 cls_cnt 0 2006.253.07:50:00.01#ibcon#cleared, iclass 23 cls_cnt 0 2006.253.07:50:00.01$vc4f8/va=7,7 2006.253.07:50:00.01#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.253.07:50:00.01#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.253.07:50:00.01#ibcon#ireg 11 cls_cnt 2 2006.253.07:50:00.01#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.253.07:50:00.07#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.253.07:50:00.07#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.253.07:50:00.07#ibcon#enter wrdev, iclass 25, count 2 2006.253.07:50:00.07#ibcon#first serial, iclass 25, count 2 2006.253.07:50:00.07#ibcon#enter sib2, iclass 25, count 2 2006.253.07:50:00.07#ibcon#flushed, iclass 25, count 2 2006.253.07:50:00.07#ibcon#about to write, iclass 25, count 2 2006.253.07:50:00.07#ibcon#wrote, iclass 25, count 2 2006.253.07:50:00.07#ibcon#about to read 3, iclass 25, count 2 2006.253.07:50:00.09#ibcon#read 3, iclass 25, count 2 2006.253.07:50:00.09#ibcon#about to read 4, iclass 25, count 2 2006.253.07:50:00.09#ibcon#read 4, iclass 25, count 2 2006.253.07:50:00.09#ibcon#about to read 5, iclass 25, count 2 2006.253.07:50:00.09#ibcon#read 5, iclass 25, count 2 2006.253.07:50:00.09#ibcon#about to read 6, iclass 25, count 2 2006.253.07:50:00.09#ibcon#read 6, iclass 25, count 2 2006.253.07:50:00.09#ibcon#end of sib2, iclass 25, count 2 2006.253.07:50:00.09#ibcon#*mode == 0, iclass 25, count 2 2006.253.07:50:00.09#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.253.07:50:00.09#ibcon#[25=AT07-07\r\n] 2006.253.07:50:00.09#ibcon#*before write, iclass 25, count 2 2006.253.07:50:00.09#ibcon#enter sib2, iclass 25, count 2 2006.253.07:50:00.09#ibcon#flushed, iclass 25, count 2 2006.253.07:50:00.09#ibcon#about to write, iclass 25, count 2 2006.253.07:50:00.09#ibcon#wrote, iclass 25, count 2 2006.253.07:50:00.09#ibcon#about to read 3, iclass 25, count 2 2006.253.07:50:00.12#ibcon#read 3, iclass 25, count 2 2006.253.07:50:00.12#ibcon#about to read 4, iclass 25, count 2 2006.253.07:50:00.12#ibcon#read 4, iclass 25, count 2 2006.253.07:50:00.12#ibcon#about to read 5, iclass 25, count 2 2006.253.07:50:00.12#ibcon#read 5, iclass 25, count 2 2006.253.07:50:00.12#ibcon#about to read 6, iclass 25, count 2 2006.253.07:50:00.12#ibcon#read 6, iclass 25, count 2 2006.253.07:50:00.12#ibcon#end of sib2, iclass 25, count 2 2006.253.07:50:00.12#ibcon#*after write, iclass 25, count 2 2006.253.07:50:00.12#ibcon#*before return 0, iclass 25, count 2 2006.253.07:50:00.12#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.253.07:50:00.12#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.253.07:50:00.12#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.253.07:50:00.12#ibcon#ireg 7 cls_cnt 0 2006.253.07:50:00.12#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.253.07:50:00.24#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.253.07:50:00.24#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.253.07:50:00.24#ibcon#enter wrdev, iclass 25, count 0 2006.253.07:50:00.24#ibcon#first serial, iclass 25, count 0 2006.253.07:50:00.24#ibcon#enter sib2, iclass 25, count 0 2006.253.07:50:00.24#ibcon#flushed, iclass 25, count 0 2006.253.07:50:00.24#ibcon#about to write, iclass 25, count 0 2006.253.07:50:00.24#ibcon#wrote, iclass 25, count 0 2006.253.07:50:00.24#ibcon#about to read 3, iclass 25, count 0 2006.253.07:50:00.26#ibcon#read 3, iclass 25, count 0 2006.253.07:50:00.26#ibcon#about to read 4, iclass 25, count 0 2006.253.07:50:00.26#ibcon#read 4, iclass 25, count 0 2006.253.07:50:00.26#ibcon#about to read 5, iclass 25, count 0 2006.253.07:50:00.26#ibcon#read 5, iclass 25, count 0 2006.253.07:50:00.26#ibcon#about to read 6, iclass 25, count 0 2006.253.07:50:00.26#ibcon#read 6, iclass 25, count 0 2006.253.07:50:00.26#ibcon#end of sib2, iclass 25, count 0 2006.253.07:50:00.26#ibcon#*mode == 0, iclass 25, count 0 2006.253.07:50:00.26#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.253.07:50:00.26#ibcon#[25=USB\r\n] 2006.253.07:50:00.26#ibcon#*before write, iclass 25, count 0 2006.253.07:50:00.26#ibcon#enter sib2, iclass 25, count 0 2006.253.07:50:00.26#ibcon#flushed, iclass 25, count 0 2006.253.07:50:00.26#ibcon#about to write, iclass 25, count 0 2006.253.07:50:00.26#ibcon#wrote, iclass 25, count 0 2006.253.07:50:00.26#ibcon#about to read 3, iclass 25, count 0 2006.253.07:50:00.29#ibcon#read 3, iclass 25, count 0 2006.253.07:50:00.29#ibcon#about to read 4, iclass 25, count 0 2006.253.07:50:00.29#ibcon#read 4, iclass 25, count 0 2006.253.07:50:00.29#ibcon#about to read 5, iclass 25, count 0 2006.253.07:50:00.29#ibcon#read 5, iclass 25, count 0 2006.253.07:50:00.29#ibcon#about to read 6, iclass 25, count 0 2006.253.07:50:00.29#ibcon#read 6, iclass 25, count 0 2006.253.07:50:00.29#ibcon#end of sib2, iclass 25, count 0 2006.253.07:50:00.29#ibcon#*after write, iclass 25, count 0 2006.253.07:50:00.29#ibcon#*before return 0, iclass 25, count 0 2006.253.07:50:00.29#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.253.07:50:00.29#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.253.07:50:00.29#ibcon#about to clear, iclass 25 cls_cnt 0 2006.253.07:50:00.29#ibcon#cleared, iclass 25 cls_cnt 0 2006.253.07:50:00.29$vc4f8/valo=8,852.99 2006.253.07:50:00.29#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.253.07:50:00.29#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.253.07:50:00.29#ibcon#ireg 17 cls_cnt 0 2006.253.07:50:00.29#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.253.07:50:00.29#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.253.07:50:00.29#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.253.07:50:00.29#ibcon#enter wrdev, iclass 27, count 0 2006.253.07:50:00.29#ibcon#first serial, iclass 27, count 0 2006.253.07:50:00.29#ibcon#enter sib2, iclass 27, count 0 2006.253.07:50:00.29#ibcon#flushed, iclass 27, count 0 2006.253.07:50:00.29#ibcon#about to write, iclass 27, count 0 2006.253.07:50:00.29#ibcon#wrote, iclass 27, count 0 2006.253.07:50:00.29#ibcon#about to read 3, iclass 27, count 0 2006.253.07:50:00.31#ibcon#read 3, iclass 27, count 0 2006.253.07:50:00.31#ibcon#about to read 4, iclass 27, count 0 2006.253.07:50:00.31#ibcon#read 4, iclass 27, count 0 2006.253.07:50:00.31#ibcon#about to read 5, iclass 27, count 0 2006.253.07:50:00.31#ibcon#read 5, iclass 27, count 0 2006.253.07:50:00.31#ibcon#about to read 6, iclass 27, count 0 2006.253.07:50:00.31#ibcon#read 6, iclass 27, count 0 2006.253.07:50:00.31#ibcon#end of sib2, iclass 27, count 0 2006.253.07:50:00.31#ibcon#*mode == 0, iclass 27, count 0 2006.253.07:50:00.31#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.253.07:50:00.31#ibcon#[26=FRQ=08,852.99\r\n] 2006.253.07:50:00.31#ibcon#*before write, iclass 27, count 0 2006.253.07:50:00.31#ibcon#enter sib2, iclass 27, count 0 2006.253.07:50:00.31#ibcon#flushed, iclass 27, count 0 2006.253.07:50:00.31#ibcon#about to write, iclass 27, count 0 2006.253.07:50:00.31#ibcon#wrote, iclass 27, count 0 2006.253.07:50:00.31#ibcon#about to read 3, iclass 27, count 0 2006.253.07:50:00.35#ibcon#read 3, iclass 27, count 0 2006.253.07:50:00.35#ibcon#about to read 4, iclass 27, count 0 2006.253.07:50:00.35#ibcon#read 4, iclass 27, count 0 2006.253.07:50:00.35#ibcon#about to read 5, iclass 27, count 0 2006.253.07:50:00.35#ibcon#read 5, iclass 27, count 0 2006.253.07:50:00.35#ibcon#about to read 6, iclass 27, count 0 2006.253.07:50:00.35#ibcon#read 6, iclass 27, count 0 2006.253.07:50:00.35#ibcon#end of sib2, iclass 27, count 0 2006.253.07:50:00.35#ibcon#*after write, iclass 27, count 0 2006.253.07:50:00.35#ibcon#*before return 0, iclass 27, count 0 2006.253.07:50:00.35#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.253.07:50:00.35#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.253.07:50:00.35#ibcon#about to clear, iclass 27 cls_cnt 0 2006.253.07:50:00.35#ibcon#cleared, iclass 27 cls_cnt 0 2006.253.07:50:00.35$vc4f8/va=8,7 2006.253.07:50:00.35#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.253.07:50:00.35#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.253.07:50:00.35#ibcon#ireg 11 cls_cnt 2 2006.253.07:50:00.35#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.253.07:50:00.42#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.253.07:50:00.42#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.253.07:50:00.42#ibcon#enter wrdev, iclass 29, count 2 2006.253.07:50:00.42#ibcon#first serial, iclass 29, count 2 2006.253.07:50:00.42#ibcon#enter sib2, iclass 29, count 2 2006.253.07:50:00.42#ibcon#flushed, iclass 29, count 2 2006.253.07:50:00.42#ibcon#about to write, iclass 29, count 2 2006.253.07:50:00.42#ibcon#wrote, iclass 29, count 2 2006.253.07:50:00.42#ibcon#about to read 3, iclass 29, count 2 2006.253.07:50:00.43#ibcon#read 3, iclass 29, count 2 2006.253.07:50:00.43#ibcon#about to read 4, iclass 29, count 2 2006.253.07:50:00.43#ibcon#read 4, iclass 29, count 2 2006.253.07:50:00.43#ibcon#about to read 5, iclass 29, count 2 2006.253.07:50:00.43#ibcon#read 5, iclass 29, count 2 2006.253.07:50:00.43#ibcon#about to read 6, iclass 29, count 2 2006.253.07:50:00.43#ibcon#read 6, iclass 29, count 2 2006.253.07:50:00.43#ibcon#end of sib2, iclass 29, count 2 2006.253.07:50:00.43#ibcon#*mode == 0, iclass 29, count 2 2006.253.07:50:00.43#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.253.07:50:00.43#ibcon#[25=AT08-07\r\n] 2006.253.07:50:00.43#ibcon#*before write, iclass 29, count 2 2006.253.07:50:00.43#ibcon#enter sib2, iclass 29, count 2 2006.253.07:50:00.43#ibcon#flushed, iclass 29, count 2 2006.253.07:50:00.43#ibcon#about to write, iclass 29, count 2 2006.253.07:50:00.43#ibcon#wrote, iclass 29, count 2 2006.253.07:50:00.43#ibcon#about to read 3, iclass 29, count 2 2006.253.07:50:00.46#ibcon#read 3, iclass 29, count 2 2006.253.07:50:00.46#ibcon#about to read 4, iclass 29, count 2 2006.253.07:50:00.46#ibcon#read 4, iclass 29, count 2 2006.253.07:50:00.46#ibcon#about to read 5, iclass 29, count 2 2006.253.07:50:00.46#ibcon#read 5, iclass 29, count 2 2006.253.07:50:00.46#ibcon#about to read 6, iclass 29, count 2 2006.253.07:50:00.46#ibcon#read 6, iclass 29, count 2 2006.253.07:50:00.46#ibcon#end of sib2, iclass 29, count 2 2006.253.07:50:00.46#ibcon#*after write, iclass 29, count 2 2006.253.07:50:00.46#ibcon#*before return 0, iclass 29, count 2 2006.253.07:50:00.46#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.253.07:50:00.46#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.253.07:50:00.46#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.253.07:50:00.46#ibcon#ireg 7 cls_cnt 0 2006.253.07:50:00.46#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.253.07:50:00.58#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.253.07:50:00.58#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.253.07:50:00.58#ibcon#enter wrdev, iclass 29, count 0 2006.253.07:50:00.58#ibcon#first serial, iclass 29, count 0 2006.253.07:50:00.58#ibcon#enter sib2, iclass 29, count 0 2006.253.07:50:00.58#ibcon#flushed, iclass 29, count 0 2006.253.07:50:00.58#ibcon#about to write, iclass 29, count 0 2006.253.07:50:00.58#ibcon#wrote, iclass 29, count 0 2006.253.07:50:00.58#ibcon#about to read 3, iclass 29, count 0 2006.253.07:50:00.60#ibcon#read 3, iclass 29, count 0 2006.253.07:50:00.60#ibcon#about to read 4, iclass 29, count 0 2006.253.07:50:00.60#ibcon#read 4, iclass 29, count 0 2006.253.07:50:00.60#ibcon#about to read 5, iclass 29, count 0 2006.253.07:50:00.60#ibcon#read 5, iclass 29, count 0 2006.253.07:50:00.60#ibcon#about to read 6, iclass 29, count 0 2006.253.07:50:00.60#ibcon#read 6, iclass 29, count 0 2006.253.07:50:00.60#ibcon#end of sib2, iclass 29, count 0 2006.253.07:50:00.60#ibcon#*mode == 0, iclass 29, count 0 2006.253.07:50:00.60#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.253.07:50:00.60#ibcon#[25=USB\r\n] 2006.253.07:50:00.60#ibcon#*before write, iclass 29, count 0 2006.253.07:50:00.60#ibcon#enter sib2, iclass 29, count 0 2006.253.07:50:00.60#ibcon#flushed, iclass 29, count 0 2006.253.07:50:00.60#ibcon#about to write, iclass 29, count 0 2006.253.07:50:00.60#ibcon#wrote, iclass 29, count 0 2006.253.07:50:00.60#ibcon#about to read 3, iclass 29, count 0 2006.253.07:50:00.63#ibcon#read 3, iclass 29, count 0 2006.253.07:50:00.63#ibcon#about to read 4, iclass 29, count 0 2006.253.07:50:00.63#ibcon#read 4, iclass 29, count 0 2006.253.07:50:00.63#ibcon#about to read 5, iclass 29, count 0 2006.253.07:50:00.63#ibcon#read 5, iclass 29, count 0 2006.253.07:50:00.63#ibcon#about to read 6, iclass 29, count 0 2006.253.07:50:00.63#ibcon#read 6, iclass 29, count 0 2006.253.07:50:00.63#ibcon#end of sib2, iclass 29, count 0 2006.253.07:50:00.63#ibcon#*after write, iclass 29, count 0 2006.253.07:50:00.63#ibcon#*before return 0, iclass 29, count 0 2006.253.07:50:00.63#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.253.07:50:00.63#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.253.07:50:00.63#ibcon#about to clear, iclass 29 cls_cnt 0 2006.253.07:50:00.63#ibcon#cleared, iclass 29 cls_cnt 0 2006.253.07:50:00.63$vc4f8/vblo=1,632.99 2006.253.07:50:00.63#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.253.07:50:00.63#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.253.07:50:00.63#ibcon#ireg 17 cls_cnt 0 2006.253.07:50:00.63#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.253.07:50:00.63#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.253.07:50:00.63#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.253.07:50:00.63#ibcon#enter wrdev, iclass 31, count 0 2006.253.07:50:00.63#ibcon#first serial, iclass 31, count 0 2006.253.07:50:00.63#ibcon#enter sib2, iclass 31, count 0 2006.253.07:50:00.63#ibcon#flushed, iclass 31, count 0 2006.253.07:50:00.63#ibcon#about to write, iclass 31, count 0 2006.253.07:50:00.63#ibcon#wrote, iclass 31, count 0 2006.253.07:50:00.63#ibcon#about to read 3, iclass 31, count 0 2006.253.07:50:00.65#ibcon#read 3, iclass 31, count 0 2006.253.07:50:00.65#ibcon#about to read 4, iclass 31, count 0 2006.253.07:50:00.65#ibcon#read 4, iclass 31, count 0 2006.253.07:50:00.65#ibcon#about to read 5, iclass 31, count 0 2006.253.07:50:00.65#ibcon#read 5, iclass 31, count 0 2006.253.07:50:00.65#ibcon#about to read 6, iclass 31, count 0 2006.253.07:50:00.65#ibcon#read 6, iclass 31, count 0 2006.253.07:50:00.65#ibcon#end of sib2, iclass 31, count 0 2006.253.07:50:00.65#ibcon#*mode == 0, iclass 31, count 0 2006.253.07:50:00.65#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.253.07:50:00.65#ibcon#[28=FRQ=01,632.99\r\n] 2006.253.07:50:00.65#ibcon#*before write, iclass 31, count 0 2006.253.07:50:00.65#ibcon#enter sib2, iclass 31, count 0 2006.253.07:50:00.65#ibcon#flushed, iclass 31, count 0 2006.253.07:50:00.65#ibcon#about to write, iclass 31, count 0 2006.253.07:50:00.65#ibcon#wrote, iclass 31, count 0 2006.253.07:50:00.65#ibcon#about to read 3, iclass 31, count 0 2006.253.07:50:00.69#ibcon#read 3, iclass 31, count 0 2006.253.07:50:00.69#ibcon#about to read 4, iclass 31, count 0 2006.253.07:50:00.69#ibcon#read 4, iclass 31, count 0 2006.253.07:50:00.69#ibcon#about to read 5, iclass 31, count 0 2006.253.07:50:00.69#ibcon#read 5, iclass 31, count 0 2006.253.07:50:00.69#ibcon#about to read 6, iclass 31, count 0 2006.253.07:50:00.69#ibcon#read 6, iclass 31, count 0 2006.253.07:50:00.69#ibcon#end of sib2, iclass 31, count 0 2006.253.07:50:00.69#ibcon#*after write, iclass 31, count 0 2006.253.07:50:00.69#ibcon#*before return 0, iclass 31, count 0 2006.253.07:50:00.69#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.253.07:50:00.69#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.253.07:50:00.69#ibcon#about to clear, iclass 31 cls_cnt 0 2006.253.07:50:00.69#ibcon#cleared, iclass 31 cls_cnt 0 2006.253.07:50:00.69$vc4f8/vb=1,4 2006.253.07:50:00.69#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.253.07:50:00.69#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.253.07:50:00.69#ibcon#ireg 11 cls_cnt 2 2006.253.07:50:00.69#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.253.07:50:00.69#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.253.07:50:00.69#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.253.07:50:00.69#ibcon#enter wrdev, iclass 33, count 2 2006.253.07:50:00.69#ibcon#first serial, iclass 33, count 2 2006.253.07:50:00.69#ibcon#enter sib2, iclass 33, count 2 2006.253.07:50:00.69#ibcon#flushed, iclass 33, count 2 2006.253.07:50:00.69#ibcon#about to write, iclass 33, count 2 2006.253.07:50:00.69#ibcon#wrote, iclass 33, count 2 2006.253.07:50:00.69#ibcon#about to read 3, iclass 33, count 2 2006.253.07:50:00.71#ibcon#read 3, iclass 33, count 2 2006.253.07:50:00.71#ibcon#about to read 4, iclass 33, count 2 2006.253.07:50:00.71#ibcon#read 4, iclass 33, count 2 2006.253.07:50:00.71#ibcon#about to read 5, iclass 33, count 2 2006.253.07:50:00.71#ibcon#read 5, iclass 33, count 2 2006.253.07:50:00.71#ibcon#about to read 6, iclass 33, count 2 2006.253.07:50:00.71#ibcon#read 6, iclass 33, count 2 2006.253.07:50:00.71#ibcon#end of sib2, iclass 33, count 2 2006.253.07:50:00.71#ibcon#*mode == 0, iclass 33, count 2 2006.253.07:50:00.71#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.253.07:50:00.71#ibcon#[27=AT01-04\r\n] 2006.253.07:50:00.71#ibcon#*before write, iclass 33, count 2 2006.253.07:50:00.71#ibcon#enter sib2, iclass 33, count 2 2006.253.07:50:00.71#ibcon#flushed, iclass 33, count 2 2006.253.07:50:00.71#ibcon#about to write, iclass 33, count 2 2006.253.07:50:00.71#ibcon#wrote, iclass 33, count 2 2006.253.07:50:00.71#ibcon#about to read 3, iclass 33, count 2 2006.253.07:50:00.74#ibcon#read 3, iclass 33, count 2 2006.253.07:50:00.74#ibcon#about to read 4, iclass 33, count 2 2006.253.07:50:00.74#ibcon#read 4, iclass 33, count 2 2006.253.07:50:00.74#ibcon#about to read 5, iclass 33, count 2 2006.253.07:50:00.74#ibcon#read 5, iclass 33, count 2 2006.253.07:50:00.74#ibcon#about to read 6, iclass 33, count 2 2006.253.07:50:00.74#ibcon#read 6, iclass 33, count 2 2006.253.07:50:00.74#ibcon#end of sib2, iclass 33, count 2 2006.253.07:50:00.74#ibcon#*after write, iclass 33, count 2 2006.253.07:50:00.74#ibcon#*before return 0, iclass 33, count 2 2006.253.07:50:00.74#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.253.07:50:00.74#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.253.07:50:00.74#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.253.07:50:00.74#ibcon#ireg 7 cls_cnt 0 2006.253.07:50:00.74#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.253.07:50:00.86#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.253.07:50:00.86#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.253.07:50:00.86#ibcon#enter wrdev, iclass 33, count 0 2006.253.07:50:00.86#ibcon#first serial, iclass 33, count 0 2006.253.07:50:00.86#ibcon#enter sib2, iclass 33, count 0 2006.253.07:50:00.86#ibcon#flushed, iclass 33, count 0 2006.253.07:50:00.86#ibcon#about to write, iclass 33, count 0 2006.253.07:50:00.86#ibcon#wrote, iclass 33, count 0 2006.253.07:50:00.86#ibcon#about to read 3, iclass 33, count 0 2006.253.07:50:00.88#ibcon#read 3, iclass 33, count 0 2006.253.07:50:00.88#ibcon#about to read 4, iclass 33, count 0 2006.253.07:50:00.88#ibcon#read 4, iclass 33, count 0 2006.253.07:50:00.88#ibcon#about to read 5, iclass 33, count 0 2006.253.07:50:00.88#ibcon#read 5, iclass 33, count 0 2006.253.07:50:00.88#ibcon#about to read 6, iclass 33, count 0 2006.253.07:50:00.88#ibcon#read 6, iclass 33, count 0 2006.253.07:50:00.88#ibcon#end of sib2, iclass 33, count 0 2006.253.07:50:00.88#ibcon#*mode == 0, iclass 33, count 0 2006.253.07:50:00.88#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.253.07:50:00.88#ibcon#[27=USB\r\n] 2006.253.07:50:00.88#ibcon#*before write, iclass 33, count 0 2006.253.07:50:00.88#ibcon#enter sib2, iclass 33, count 0 2006.253.07:50:00.88#ibcon#flushed, iclass 33, count 0 2006.253.07:50:00.88#ibcon#about to write, iclass 33, count 0 2006.253.07:50:00.88#ibcon#wrote, iclass 33, count 0 2006.253.07:50:00.88#ibcon#about to read 3, iclass 33, count 0 2006.253.07:50:00.91#ibcon#read 3, iclass 33, count 0 2006.253.07:50:00.91#ibcon#about to read 4, iclass 33, count 0 2006.253.07:50:00.91#ibcon#read 4, iclass 33, count 0 2006.253.07:50:00.91#ibcon#about to read 5, iclass 33, count 0 2006.253.07:50:00.91#ibcon#read 5, iclass 33, count 0 2006.253.07:50:00.91#ibcon#about to read 6, iclass 33, count 0 2006.253.07:50:00.91#ibcon#read 6, iclass 33, count 0 2006.253.07:50:00.91#ibcon#end of sib2, iclass 33, count 0 2006.253.07:50:00.91#ibcon#*after write, iclass 33, count 0 2006.253.07:50:00.91#ibcon#*before return 0, iclass 33, count 0 2006.253.07:50:00.91#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.253.07:50:00.91#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.253.07:50:00.91#ibcon#about to clear, iclass 33 cls_cnt 0 2006.253.07:50:00.91#ibcon#cleared, iclass 33 cls_cnt 0 2006.253.07:50:00.91$vc4f8/vblo=2,640.99 2006.253.07:50:00.91#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.253.07:50:00.91#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.253.07:50:00.91#ibcon#ireg 17 cls_cnt 0 2006.253.07:50:00.91#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.253.07:50:00.91#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.253.07:50:00.91#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.253.07:50:00.91#ibcon#enter wrdev, iclass 35, count 0 2006.253.07:50:00.91#ibcon#first serial, iclass 35, count 0 2006.253.07:50:00.91#ibcon#enter sib2, iclass 35, count 0 2006.253.07:50:00.91#ibcon#flushed, iclass 35, count 0 2006.253.07:50:00.91#ibcon#about to write, iclass 35, count 0 2006.253.07:50:00.91#ibcon#wrote, iclass 35, count 0 2006.253.07:50:00.91#ibcon#about to read 3, iclass 35, count 0 2006.253.07:50:00.93#ibcon#read 3, iclass 35, count 0 2006.253.07:50:00.93#ibcon#about to read 4, iclass 35, count 0 2006.253.07:50:00.93#ibcon#read 4, iclass 35, count 0 2006.253.07:50:00.93#ibcon#about to read 5, iclass 35, count 0 2006.253.07:50:00.93#ibcon#read 5, iclass 35, count 0 2006.253.07:50:00.93#ibcon#about to read 6, iclass 35, count 0 2006.253.07:50:00.93#ibcon#read 6, iclass 35, count 0 2006.253.07:50:00.93#ibcon#end of sib2, iclass 35, count 0 2006.253.07:50:00.93#ibcon#*mode == 0, iclass 35, count 0 2006.253.07:50:00.93#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.253.07:50:00.93#ibcon#[28=FRQ=02,640.99\r\n] 2006.253.07:50:00.93#ibcon#*before write, iclass 35, count 0 2006.253.07:50:00.93#ibcon#enter sib2, iclass 35, count 0 2006.253.07:50:00.93#ibcon#flushed, iclass 35, count 0 2006.253.07:50:00.93#ibcon#about to write, iclass 35, count 0 2006.253.07:50:00.93#ibcon#wrote, iclass 35, count 0 2006.253.07:50:00.93#ibcon#about to read 3, iclass 35, count 0 2006.253.07:50:00.97#ibcon#read 3, iclass 35, count 0 2006.253.07:50:00.97#ibcon#about to read 4, iclass 35, count 0 2006.253.07:50:00.97#ibcon#read 4, iclass 35, count 0 2006.253.07:50:00.97#ibcon#about to read 5, iclass 35, count 0 2006.253.07:50:00.97#ibcon#read 5, iclass 35, count 0 2006.253.07:50:00.97#ibcon#about to read 6, iclass 35, count 0 2006.253.07:50:00.97#ibcon#read 6, iclass 35, count 0 2006.253.07:50:00.97#ibcon#end of sib2, iclass 35, count 0 2006.253.07:50:00.97#ibcon#*after write, iclass 35, count 0 2006.253.07:50:00.97#ibcon#*before return 0, iclass 35, count 0 2006.253.07:50:00.97#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.253.07:50:00.97#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.253.07:50:00.97#ibcon#about to clear, iclass 35 cls_cnt 0 2006.253.07:50:00.97#ibcon#cleared, iclass 35 cls_cnt 0 2006.253.07:50:00.97$vc4f8/vb=2,5 2006.253.07:50:00.97#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.253.07:50:00.97#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.253.07:50:00.97#ibcon#ireg 11 cls_cnt 2 2006.253.07:50:00.97#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.253.07:50:01.03#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.253.07:50:01.03#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.253.07:50:01.03#ibcon#enter wrdev, iclass 37, count 2 2006.253.07:50:01.03#ibcon#first serial, iclass 37, count 2 2006.253.07:50:01.03#ibcon#enter sib2, iclass 37, count 2 2006.253.07:50:01.03#ibcon#flushed, iclass 37, count 2 2006.253.07:50:01.03#ibcon#about to write, iclass 37, count 2 2006.253.07:50:01.03#ibcon#wrote, iclass 37, count 2 2006.253.07:50:01.03#ibcon#about to read 3, iclass 37, count 2 2006.253.07:50:01.05#ibcon#read 3, iclass 37, count 2 2006.253.07:50:01.05#ibcon#about to read 4, iclass 37, count 2 2006.253.07:50:01.05#ibcon#read 4, iclass 37, count 2 2006.253.07:50:01.05#ibcon#about to read 5, iclass 37, count 2 2006.253.07:50:01.05#ibcon#read 5, iclass 37, count 2 2006.253.07:50:01.05#ibcon#about to read 6, iclass 37, count 2 2006.253.07:50:01.05#ibcon#read 6, iclass 37, count 2 2006.253.07:50:01.05#ibcon#end of sib2, iclass 37, count 2 2006.253.07:50:01.05#ibcon#*mode == 0, iclass 37, count 2 2006.253.07:50:01.05#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.253.07:50:01.05#ibcon#[27=AT02-05\r\n] 2006.253.07:50:01.05#ibcon#*before write, iclass 37, count 2 2006.253.07:50:01.05#ibcon#enter sib2, iclass 37, count 2 2006.253.07:50:01.05#ibcon#flushed, iclass 37, count 2 2006.253.07:50:01.05#ibcon#about to write, iclass 37, count 2 2006.253.07:50:01.05#ibcon#wrote, iclass 37, count 2 2006.253.07:50:01.05#ibcon#about to read 3, iclass 37, count 2 2006.253.07:50:01.08#ibcon#read 3, iclass 37, count 2 2006.253.07:50:01.08#ibcon#about to read 4, iclass 37, count 2 2006.253.07:50:01.08#ibcon#read 4, iclass 37, count 2 2006.253.07:50:01.08#ibcon#about to read 5, iclass 37, count 2 2006.253.07:50:01.08#ibcon#read 5, iclass 37, count 2 2006.253.07:50:01.08#ibcon#about to read 6, iclass 37, count 2 2006.253.07:50:01.08#ibcon#read 6, iclass 37, count 2 2006.253.07:50:01.08#ibcon#end of sib2, iclass 37, count 2 2006.253.07:50:01.08#ibcon#*after write, iclass 37, count 2 2006.253.07:50:01.08#ibcon#*before return 0, iclass 37, count 2 2006.253.07:50:01.08#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.253.07:50:01.08#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.253.07:50:01.08#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.253.07:50:01.08#ibcon#ireg 7 cls_cnt 0 2006.253.07:50:01.08#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.253.07:50:01.20#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.253.07:50:01.20#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.253.07:50:01.20#ibcon#enter wrdev, iclass 37, count 0 2006.253.07:50:01.20#ibcon#first serial, iclass 37, count 0 2006.253.07:50:01.20#ibcon#enter sib2, iclass 37, count 0 2006.253.07:50:01.20#ibcon#flushed, iclass 37, count 0 2006.253.07:50:01.20#ibcon#about to write, iclass 37, count 0 2006.253.07:50:01.20#ibcon#wrote, iclass 37, count 0 2006.253.07:50:01.20#ibcon#about to read 3, iclass 37, count 0 2006.253.07:50:01.22#ibcon#read 3, iclass 37, count 0 2006.253.07:50:01.22#ibcon#about to read 4, iclass 37, count 0 2006.253.07:50:01.22#ibcon#read 4, iclass 37, count 0 2006.253.07:50:01.22#ibcon#about to read 5, iclass 37, count 0 2006.253.07:50:01.22#ibcon#read 5, iclass 37, count 0 2006.253.07:50:01.22#ibcon#about to read 6, iclass 37, count 0 2006.253.07:50:01.22#ibcon#read 6, iclass 37, count 0 2006.253.07:50:01.22#ibcon#end of sib2, iclass 37, count 0 2006.253.07:50:01.22#ibcon#*mode == 0, iclass 37, count 0 2006.253.07:50:01.22#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.253.07:50:01.22#ibcon#[27=USB\r\n] 2006.253.07:50:01.22#ibcon#*before write, iclass 37, count 0 2006.253.07:50:01.22#ibcon#enter sib2, iclass 37, count 0 2006.253.07:50:01.22#ibcon#flushed, iclass 37, count 0 2006.253.07:50:01.22#ibcon#about to write, iclass 37, count 0 2006.253.07:50:01.22#ibcon#wrote, iclass 37, count 0 2006.253.07:50:01.22#ibcon#about to read 3, iclass 37, count 0 2006.253.07:50:01.25#ibcon#read 3, iclass 37, count 0 2006.253.07:50:01.25#ibcon#about to read 4, iclass 37, count 0 2006.253.07:50:01.25#ibcon#read 4, iclass 37, count 0 2006.253.07:50:01.25#ibcon#about to read 5, iclass 37, count 0 2006.253.07:50:01.25#ibcon#read 5, iclass 37, count 0 2006.253.07:50:01.25#ibcon#about to read 6, iclass 37, count 0 2006.253.07:50:01.25#ibcon#read 6, iclass 37, count 0 2006.253.07:50:01.25#ibcon#end of sib2, iclass 37, count 0 2006.253.07:50:01.25#ibcon#*after write, iclass 37, count 0 2006.253.07:50:01.25#ibcon#*before return 0, iclass 37, count 0 2006.253.07:50:01.25#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.253.07:50:01.25#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.253.07:50:01.25#ibcon#about to clear, iclass 37 cls_cnt 0 2006.253.07:50:01.25#ibcon#cleared, iclass 37 cls_cnt 0 2006.253.07:50:01.25$vc4f8/vblo=3,656.99 2006.253.07:50:01.25#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.253.07:50:01.25#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.253.07:50:01.25#ibcon#ireg 17 cls_cnt 0 2006.253.07:50:01.25#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.253.07:50:01.25#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.253.07:50:01.25#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.253.07:50:01.25#ibcon#enter wrdev, iclass 39, count 0 2006.253.07:50:01.25#ibcon#first serial, iclass 39, count 0 2006.253.07:50:01.25#ibcon#enter sib2, iclass 39, count 0 2006.253.07:50:01.25#ibcon#flushed, iclass 39, count 0 2006.253.07:50:01.25#ibcon#about to write, iclass 39, count 0 2006.253.07:50:01.25#ibcon#wrote, iclass 39, count 0 2006.253.07:50:01.25#ibcon#about to read 3, iclass 39, count 0 2006.253.07:50:01.27#ibcon#read 3, iclass 39, count 0 2006.253.07:50:01.27#ibcon#about to read 4, iclass 39, count 0 2006.253.07:50:01.27#ibcon#read 4, iclass 39, count 0 2006.253.07:50:01.27#ibcon#about to read 5, iclass 39, count 0 2006.253.07:50:01.27#ibcon#read 5, iclass 39, count 0 2006.253.07:50:01.27#ibcon#about to read 6, iclass 39, count 0 2006.253.07:50:01.27#ibcon#read 6, iclass 39, count 0 2006.253.07:50:01.27#ibcon#end of sib2, iclass 39, count 0 2006.253.07:50:01.27#ibcon#*mode == 0, iclass 39, count 0 2006.253.07:50:01.27#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.253.07:50:01.27#ibcon#[28=FRQ=03,656.99\r\n] 2006.253.07:50:01.27#ibcon#*before write, iclass 39, count 0 2006.253.07:50:01.27#ibcon#enter sib2, iclass 39, count 0 2006.253.07:50:01.27#ibcon#flushed, iclass 39, count 0 2006.253.07:50:01.27#ibcon#about to write, iclass 39, count 0 2006.253.07:50:01.27#ibcon#wrote, iclass 39, count 0 2006.253.07:50:01.27#ibcon#about to read 3, iclass 39, count 0 2006.253.07:50:01.31#ibcon#read 3, iclass 39, count 0 2006.253.07:50:01.31#ibcon#about to read 4, iclass 39, count 0 2006.253.07:50:01.31#ibcon#read 4, iclass 39, count 0 2006.253.07:50:01.31#ibcon#about to read 5, iclass 39, count 0 2006.253.07:50:01.31#ibcon#read 5, iclass 39, count 0 2006.253.07:50:01.31#ibcon#about to read 6, iclass 39, count 0 2006.253.07:50:01.31#ibcon#read 6, iclass 39, count 0 2006.253.07:50:01.31#ibcon#end of sib2, iclass 39, count 0 2006.253.07:50:01.31#ibcon#*after write, iclass 39, count 0 2006.253.07:50:01.31#ibcon#*before return 0, iclass 39, count 0 2006.253.07:50:01.31#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.253.07:50:01.31#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.253.07:50:01.31#ibcon#about to clear, iclass 39 cls_cnt 0 2006.253.07:50:01.31#ibcon#cleared, iclass 39 cls_cnt 0 2006.253.07:50:01.31$vc4f8/vb=3,4 2006.253.07:50:01.31#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.253.07:50:01.31#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.253.07:50:01.31#ibcon#ireg 11 cls_cnt 2 2006.253.07:50:01.31#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.253.07:50:01.37#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.253.07:50:01.37#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.253.07:50:01.37#ibcon#enter wrdev, iclass 3, count 2 2006.253.07:50:01.37#ibcon#first serial, iclass 3, count 2 2006.253.07:50:01.37#ibcon#enter sib2, iclass 3, count 2 2006.253.07:50:01.37#ibcon#flushed, iclass 3, count 2 2006.253.07:50:01.37#ibcon#about to write, iclass 3, count 2 2006.253.07:50:01.37#ibcon#wrote, iclass 3, count 2 2006.253.07:50:01.37#ibcon#about to read 3, iclass 3, count 2 2006.253.07:50:01.39#ibcon#read 3, iclass 3, count 2 2006.253.07:50:01.39#ibcon#about to read 4, iclass 3, count 2 2006.253.07:50:01.39#ibcon#read 4, iclass 3, count 2 2006.253.07:50:01.39#ibcon#about to read 5, iclass 3, count 2 2006.253.07:50:01.39#ibcon#read 5, iclass 3, count 2 2006.253.07:50:01.39#ibcon#about to read 6, iclass 3, count 2 2006.253.07:50:01.39#ibcon#read 6, iclass 3, count 2 2006.253.07:50:01.39#ibcon#end of sib2, iclass 3, count 2 2006.253.07:50:01.39#ibcon#*mode == 0, iclass 3, count 2 2006.253.07:50:01.39#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.253.07:50:01.39#ibcon#[27=AT03-04\r\n] 2006.253.07:50:01.39#ibcon#*before write, iclass 3, count 2 2006.253.07:50:01.39#ibcon#enter sib2, iclass 3, count 2 2006.253.07:50:01.39#ibcon#flushed, iclass 3, count 2 2006.253.07:50:01.39#ibcon#about to write, iclass 3, count 2 2006.253.07:50:01.39#ibcon#wrote, iclass 3, count 2 2006.253.07:50:01.39#ibcon#about to read 3, iclass 3, count 2 2006.253.07:50:01.42#ibcon#read 3, iclass 3, count 2 2006.253.07:50:01.42#ibcon#about to read 4, iclass 3, count 2 2006.253.07:50:01.42#ibcon#read 4, iclass 3, count 2 2006.253.07:50:01.42#ibcon#about to read 5, iclass 3, count 2 2006.253.07:50:01.42#ibcon#read 5, iclass 3, count 2 2006.253.07:50:01.42#ibcon#about to read 6, iclass 3, count 2 2006.253.07:50:01.42#ibcon#read 6, iclass 3, count 2 2006.253.07:50:01.42#ibcon#end of sib2, iclass 3, count 2 2006.253.07:50:01.42#ibcon#*after write, iclass 3, count 2 2006.253.07:50:01.42#ibcon#*before return 0, iclass 3, count 2 2006.253.07:50:01.42#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.253.07:50:01.42#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.253.07:50:01.42#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.253.07:50:01.42#ibcon#ireg 7 cls_cnt 0 2006.253.07:50:01.42#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.253.07:50:01.54#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.253.07:50:01.54#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.253.07:50:01.54#ibcon#enter wrdev, iclass 3, count 0 2006.253.07:50:01.54#ibcon#first serial, iclass 3, count 0 2006.253.07:50:01.54#ibcon#enter sib2, iclass 3, count 0 2006.253.07:50:01.54#ibcon#flushed, iclass 3, count 0 2006.253.07:50:01.54#ibcon#about to write, iclass 3, count 0 2006.253.07:50:01.54#ibcon#wrote, iclass 3, count 0 2006.253.07:50:01.54#ibcon#about to read 3, iclass 3, count 0 2006.253.07:50:01.56#ibcon#read 3, iclass 3, count 0 2006.253.07:50:01.56#ibcon#about to read 4, iclass 3, count 0 2006.253.07:50:01.56#ibcon#read 4, iclass 3, count 0 2006.253.07:50:01.56#ibcon#about to read 5, iclass 3, count 0 2006.253.07:50:01.56#ibcon#read 5, iclass 3, count 0 2006.253.07:50:01.56#ibcon#about to read 6, iclass 3, count 0 2006.253.07:50:01.56#ibcon#read 6, iclass 3, count 0 2006.253.07:50:01.56#ibcon#end of sib2, iclass 3, count 0 2006.253.07:50:01.56#ibcon#*mode == 0, iclass 3, count 0 2006.253.07:50:01.56#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.253.07:50:01.56#ibcon#[27=USB\r\n] 2006.253.07:50:01.56#ibcon#*before write, iclass 3, count 0 2006.253.07:50:01.56#ibcon#enter sib2, iclass 3, count 0 2006.253.07:50:01.56#ibcon#flushed, iclass 3, count 0 2006.253.07:50:01.56#ibcon#about to write, iclass 3, count 0 2006.253.07:50:01.56#ibcon#wrote, iclass 3, count 0 2006.253.07:50:01.56#ibcon#about to read 3, iclass 3, count 0 2006.253.07:50:01.59#ibcon#read 3, iclass 3, count 0 2006.253.07:50:01.59#ibcon#about to read 4, iclass 3, count 0 2006.253.07:50:01.59#ibcon#read 4, iclass 3, count 0 2006.253.07:50:01.59#ibcon#about to read 5, iclass 3, count 0 2006.253.07:50:01.59#ibcon#read 5, iclass 3, count 0 2006.253.07:50:01.59#ibcon#about to read 6, iclass 3, count 0 2006.253.07:50:01.59#ibcon#read 6, iclass 3, count 0 2006.253.07:50:01.59#ibcon#end of sib2, iclass 3, count 0 2006.253.07:50:01.59#ibcon#*after write, iclass 3, count 0 2006.253.07:50:01.59#ibcon#*before return 0, iclass 3, count 0 2006.253.07:50:01.59#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.253.07:50:01.59#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.253.07:50:01.59#ibcon#about to clear, iclass 3 cls_cnt 0 2006.253.07:50:01.59#ibcon#cleared, iclass 3 cls_cnt 0 2006.253.07:50:01.59$vc4f8/vblo=4,712.99 2006.253.07:50:01.59#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.253.07:50:01.59#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.253.07:50:01.59#ibcon#ireg 17 cls_cnt 0 2006.253.07:50:01.59#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.253.07:50:01.59#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.253.07:50:01.59#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.253.07:50:01.59#ibcon#enter wrdev, iclass 5, count 0 2006.253.07:50:01.59#ibcon#first serial, iclass 5, count 0 2006.253.07:50:01.59#ibcon#enter sib2, iclass 5, count 0 2006.253.07:50:01.59#ibcon#flushed, iclass 5, count 0 2006.253.07:50:01.59#ibcon#about to write, iclass 5, count 0 2006.253.07:50:01.59#ibcon#wrote, iclass 5, count 0 2006.253.07:50:01.59#ibcon#about to read 3, iclass 5, count 0 2006.253.07:50:01.61#ibcon#read 3, iclass 5, count 0 2006.253.07:50:01.61#ibcon#about to read 4, iclass 5, count 0 2006.253.07:50:01.61#ibcon#read 4, iclass 5, count 0 2006.253.07:50:01.61#ibcon#about to read 5, iclass 5, count 0 2006.253.07:50:01.61#ibcon#read 5, iclass 5, count 0 2006.253.07:50:01.61#ibcon#about to read 6, iclass 5, count 0 2006.253.07:50:01.61#ibcon#read 6, iclass 5, count 0 2006.253.07:50:01.61#ibcon#end of sib2, iclass 5, count 0 2006.253.07:50:01.61#ibcon#*mode == 0, iclass 5, count 0 2006.253.07:50:01.61#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.253.07:50:01.61#ibcon#[28=FRQ=04,712.99\r\n] 2006.253.07:50:01.61#ibcon#*before write, iclass 5, count 0 2006.253.07:50:01.61#ibcon#enter sib2, iclass 5, count 0 2006.253.07:50:01.61#ibcon#flushed, iclass 5, count 0 2006.253.07:50:01.61#ibcon#about to write, iclass 5, count 0 2006.253.07:50:01.61#ibcon#wrote, iclass 5, count 0 2006.253.07:50:01.61#ibcon#about to read 3, iclass 5, count 0 2006.253.07:50:01.65#ibcon#read 3, iclass 5, count 0 2006.253.07:50:01.65#ibcon#about to read 4, iclass 5, count 0 2006.253.07:50:01.65#ibcon#read 4, iclass 5, count 0 2006.253.07:50:01.65#ibcon#about to read 5, iclass 5, count 0 2006.253.07:50:01.65#ibcon#read 5, iclass 5, count 0 2006.253.07:50:01.65#ibcon#about to read 6, iclass 5, count 0 2006.253.07:50:01.65#ibcon#read 6, iclass 5, count 0 2006.253.07:50:01.65#ibcon#end of sib2, iclass 5, count 0 2006.253.07:50:01.65#ibcon#*after write, iclass 5, count 0 2006.253.07:50:01.65#ibcon#*before return 0, iclass 5, count 0 2006.253.07:50:01.65#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.253.07:50:01.65#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.253.07:50:01.65#ibcon#about to clear, iclass 5 cls_cnt 0 2006.253.07:50:01.65#ibcon#cleared, iclass 5 cls_cnt 0 2006.253.07:50:01.65$vc4f8/vb=4,4 2006.253.07:50:01.65#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.253.07:50:01.65#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.253.07:50:01.65#ibcon#ireg 11 cls_cnt 2 2006.253.07:50:01.65#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.253.07:50:01.71#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.253.07:50:01.71#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.253.07:50:01.71#ibcon#enter wrdev, iclass 7, count 2 2006.253.07:50:01.71#ibcon#first serial, iclass 7, count 2 2006.253.07:50:01.71#ibcon#enter sib2, iclass 7, count 2 2006.253.07:50:01.71#ibcon#flushed, iclass 7, count 2 2006.253.07:50:01.71#ibcon#about to write, iclass 7, count 2 2006.253.07:50:01.71#ibcon#wrote, iclass 7, count 2 2006.253.07:50:01.71#ibcon#about to read 3, iclass 7, count 2 2006.253.07:50:01.73#ibcon#read 3, iclass 7, count 2 2006.253.07:50:01.73#ibcon#about to read 4, iclass 7, count 2 2006.253.07:50:01.73#ibcon#read 4, iclass 7, count 2 2006.253.07:50:01.73#ibcon#about to read 5, iclass 7, count 2 2006.253.07:50:01.73#ibcon#read 5, iclass 7, count 2 2006.253.07:50:01.73#ibcon#about to read 6, iclass 7, count 2 2006.253.07:50:01.73#ibcon#read 6, iclass 7, count 2 2006.253.07:50:01.73#ibcon#end of sib2, iclass 7, count 2 2006.253.07:50:01.73#ibcon#*mode == 0, iclass 7, count 2 2006.253.07:50:01.73#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.253.07:50:01.73#ibcon#[27=AT04-04\r\n] 2006.253.07:50:01.73#ibcon#*before write, iclass 7, count 2 2006.253.07:50:01.73#ibcon#enter sib2, iclass 7, count 2 2006.253.07:50:01.73#ibcon#flushed, iclass 7, count 2 2006.253.07:50:01.73#ibcon#about to write, iclass 7, count 2 2006.253.07:50:01.73#ibcon#wrote, iclass 7, count 2 2006.253.07:50:01.73#ibcon#about to read 3, iclass 7, count 2 2006.253.07:50:01.76#ibcon#read 3, iclass 7, count 2 2006.253.07:50:01.76#ibcon#about to read 4, iclass 7, count 2 2006.253.07:50:01.76#ibcon#read 4, iclass 7, count 2 2006.253.07:50:01.76#ibcon#about to read 5, iclass 7, count 2 2006.253.07:50:01.76#ibcon#read 5, iclass 7, count 2 2006.253.07:50:01.76#ibcon#about to read 6, iclass 7, count 2 2006.253.07:50:01.76#ibcon#read 6, iclass 7, count 2 2006.253.07:50:01.76#ibcon#end of sib2, iclass 7, count 2 2006.253.07:50:01.76#ibcon#*after write, iclass 7, count 2 2006.253.07:50:01.76#ibcon#*before return 0, iclass 7, count 2 2006.253.07:50:01.76#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.253.07:50:01.76#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.253.07:50:01.76#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.253.07:50:01.76#ibcon#ireg 7 cls_cnt 0 2006.253.07:50:01.76#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.253.07:50:01.88#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.253.07:50:01.88#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.253.07:50:01.88#ibcon#enter wrdev, iclass 7, count 0 2006.253.07:50:01.88#ibcon#first serial, iclass 7, count 0 2006.253.07:50:01.88#ibcon#enter sib2, iclass 7, count 0 2006.253.07:50:01.88#ibcon#flushed, iclass 7, count 0 2006.253.07:50:01.88#ibcon#about to write, iclass 7, count 0 2006.253.07:50:01.88#ibcon#wrote, iclass 7, count 0 2006.253.07:50:01.88#ibcon#about to read 3, iclass 7, count 0 2006.253.07:50:01.90#ibcon#read 3, iclass 7, count 0 2006.253.07:50:01.90#ibcon#about to read 4, iclass 7, count 0 2006.253.07:50:01.90#ibcon#read 4, iclass 7, count 0 2006.253.07:50:01.90#ibcon#about to read 5, iclass 7, count 0 2006.253.07:50:01.90#ibcon#read 5, iclass 7, count 0 2006.253.07:50:01.90#ibcon#about to read 6, iclass 7, count 0 2006.253.07:50:01.90#ibcon#read 6, iclass 7, count 0 2006.253.07:50:01.90#ibcon#end of sib2, iclass 7, count 0 2006.253.07:50:01.90#ibcon#*mode == 0, iclass 7, count 0 2006.253.07:50:01.90#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.253.07:50:01.90#ibcon#[27=USB\r\n] 2006.253.07:50:01.90#ibcon#*before write, iclass 7, count 0 2006.253.07:50:01.90#ibcon#enter sib2, iclass 7, count 0 2006.253.07:50:01.90#ibcon#flushed, iclass 7, count 0 2006.253.07:50:01.90#ibcon#about to write, iclass 7, count 0 2006.253.07:50:01.90#ibcon#wrote, iclass 7, count 0 2006.253.07:50:01.90#ibcon#about to read 3, iclass 7, count 0 2006.253.07:50:01.93#ibcon#read 3, iclass 7, count 0 2006.253.07:50:01.93#ibcon#about to read 4, iclass 7, count 0 2006.253.07:50:01.93#ibcon#read 4, iclass 7, count 0 2006.253.07:50:01.93#ibcon#about to read 5, iclass 7, count 0 2006.253.07:50:01.93#ibcon#read 5, iclass 7, count 0 2006.253.07:50:01.93#ibcon#about to read 6, iclass 7, count 0 2006.253.07:50:01.93#ibcon#read 6, iclass 7, count 0 2006.253.07:50:01.93#ibcon#end of sib2, iclass 7, count 0 2006.253.07:50:01.93#ibcon#*after write, iclass 7, count 0 2006.253.07:50:01.93#ibcon#*before return 0, iclass 7, count 0 2006.253.07:50:01.93#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.253.07:50:01.93#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.253.07:50:01.93#ibcon#about to clear, iclass 7 cls_cnt 0 2006.253.07:50:01.93#ibcon#cleared, iclass 7 cls_cnt 0 2006.253.07:50:01.93$vc4f8/vblo=5,744.99 2006.253.07:50:01.93#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.253.07:50:01.93#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.253.07:50:01.93#ibcon#ireg 17 cls_cnt 0 2006.253.07:50:01.93#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.253.07:50:01.93#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.253.07:50:01.93#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.253.07:50:01.93#ibcon#enter wrdev, iclass 11, count 0 2006.253.07:50:01.93#ibcon#first serial, iclass 11, count 0 2006.253.07:50:01.93#ibcon#enter sib2, iclass 11, count 0 2006.253.07:50:01.93#ibcon#flushed, iclass 11, count 0 2006.253.07:50:01.93#ibcon#about to write, iclass 11, count 0 2006.253.07:50:01.93#ibcon#wrote, iclass 11, count 0 2006.253.07:50:01.93#ibcon#about to read 3, iclass 11, count 0 2006.253.07:50:01.95#ibcon#read 3, iclass 11, count 0 2006.253.07:50:01.95#ibcon#about to read 4, iclass 11, count 0 2006.253.07:50:01.95#ibcon#read 4, iclass 11, count 0 2006.253.07:50:01.95#ibcon#about to read 5, iclass 11, count 0 2006.253.07:50:01.95#ibcon#read 5, iclass 11, count 0 2006.253.07:50:01.95#ibcon#about to read 6, iclass 11, count 0 2006.253.07:50:01.95#ibcon#read 6, iclass 11, count 0 2006.253.07:50:01.95#ibcon#end of sib2, iclass 11, count 0 2006.253.07:50:01.95#ibcon#*mode == 0, iclass 11, count 0 2006.253.07:50:01.95#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.253.07:50:01.95#ibcon#[28=FRQ=05,744.99\r\n] 2006.253.07:50:01.95#ibcon#*before write, iclass 11, count 0 2006.253.07:50:01.95#ibcon#enter sib2, iclass 11, count 0 2006.253.07:50:01.95#ibcon#flushed, iclass 11, count 0 2006.253.07:50:01.95#ibcon#about to write, iclass 11, count 0 2006.253.07:50:01.95#ibcon#wrote, iclass 11, count 0 2006.253.07:50:01.95#ibcon#about to read 3, iclass 11, count 0 2006.253.07:50:01.99#ibcon#read 3, iclass 11, count 0 2006.253.07:50:01.99#ibcon#about to read 4, iclass 11, count 0 2006.253.07:50:01.99#ibcon#read 4, iclass 11, count 0 2006.253.07:50:01.99#ibcon#about to read 5, iclass 11, count 0 2006.253.07:50:01.99#ibcon#read 5, iclass 11, count 0 2006.253.07:50:01.99#ibcon#about to read 6, iclass 11, count 0 2006.253.07:50:01.99#ibcon#read 6, iclass 11, count 0 2006.253.07:50:01.99#ibcon#end of sib2, iclass 11, count 0 2006.253.07:50:01.99#ibcon#*after write, iclass 11, count 0 2006.253.07:50:01.99#ibcon#*before return 0, iclass 11, count 0 2006.253.07:50:01.99#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.253.07:50:01.99#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.253.07:50:01.99#ibcon#about to clear, iclass 11 cls_cnt 0 2006.253.07:50:01.99#ibcon#cleared, iclass 11 cls_cnt 0 2006.253.07:50:01.99$vc4f8/vb=5,4 2006.253.07:50:01.99#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.253.07:50:01.99#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.253.07:50:01.99#ibcon#ireg 11 cls_cnt 2 2006.253.07:50:01.99#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.253.07:50:02.06#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.253.07:50:02.06#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.253.07:50:02.06#ibcon#enter wrdev, iclass 13, count 2 2006.253.07:50:02.06#ibcon#first serial, iclass 13, count 2 2006.253.07:50:02.06#ibcon#enter sib2, iclass 13, count 2 2006.253.07:50:02.06#ibcon#flushed, iclass 13, count 2 2006.253.07:50:02.06#ibcon#about to write, iclass 13, count 2 2006.253.07:50:02.06#ibcon#wrote, iclass 13, count 2 2006.253.07:50:02.06#ibcon#about to read 3, iclass 13, count 2 2006.253.07:50:02.07#ibcon#read 3, iclass 13, count 2 2006.253.07:50:02.07#ibcon#about to read 4, iclass 13, count 2 2006.253.07:50:02.07#ibcon#read 4, iclass 13, count 2 2006.253.07:50:02.07#ibcon#about to read 5, iclass 13, count 2 2006.253.07:50:02.07#ibcon#read 5, iclass 13, count 2 2006.253.07:50:02.07#ibcon#about to read 6, iclass 13, count 2 2006.253.07:50:02.07#ibcon#read 6, iclass 13, count 2 2006.253.07:50:02.07#ibcon#end of sib2, iclass 13, count 2 2006.253.07:50:02.07#ibcon#*mode == 0, iclass 13, count 2 2006.253.07:50:02.07#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.253.07:50:02.07#ibcon#[27=AT05-04\r\n] 2006.253.07:50:02.07#ibcon#*before write, iclass 13, count 2 2006.253.07:50:02.07#ibcon#enter sib2, iclass 13, count 2 2006.253.07:50:02.07#ibcon#flushed, iclass 13, count 2 2006.253.07:50:02.07#ibcon#about to write, iclass 13, count 2 2006.253.07:50:02.07#ibcon#wrote, iclass 13, count 2 2006.253.07:50:02.07#ibcon#about to read 3, iclass 13, count 2 2006.253.07:50:02.10#ibcon#read 3, iclass 13, count 2 2006.253.07:50:02.10#ibcon#about to read 4, iclass 13, count 2 2006.253.07:50:02.10#ibcon#read 4, iclass 13, count 2 2006.253.07:50:02.10#ibcon#about to read 5, iclass 13, count 2 2006.253.07:50:02.10#ibcon#read 5, iclass 13, count 2 2006.253.07:50:02.10#ibcon#about to read 6, iclass 13, count 2 2006.253.07:50:02.10#ibcon#read 6, iclass 13, count 2 2006.253.07:50:02.10#ibcon#end of sib2, iclass 13, count 2 2006.253.07:50:02.10#ibcon#*after write, iclass 13, count 2 2006.253.07:50:02.10#ibcon#*before return 0, iclass 13, count 2 2006.253.07:50:02.10#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.253.07:50:02.10#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.253.07:50:02.10#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.253.07:50:02.10#ibcon#ireg 7 cls_cnt 0 2006.253.07:50:02.10#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.253.07:50:02.22#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.253.07:50:02.22#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.253.07:50:02.22#ibcon#enter wrdev, iclass 13, count 0 2006.253.07:50:02.22#ibcon#first serial, iclass 13, count 0 2006.253.07:50:02.22#ibcon#enter sib2, iclass 13, count 0 2006.253.07:50:02.22#ibcon#flushed, iclass 13, count 0 2006.253.07:50:02.22#ibcon#about to write, iclass 13, count 0 2006.253.07:50:02.22#ibcon#wrote, iclass 13, count 0 2006.253.07:50:02.22#ibcon#about to read 3, iclass 13, count 0 2006.253.07:50:02.26#ibcon#read 3, iclass 13, count 0 2006.253.07:50:02.26#ibcon#about to read 4, iclass 13, count 0 2006.253.07:50:02.26#ibcon#read 4, iclass 13, count 0 2006.253.07:50:02.26#ibcon#about to read 5, iclass 13, count 0 2006.253.07:50:02.26#ibcon#read 5, iclass 13, count 0 2006.253.07:50:02.26#ibcon#about to read 6, iclass 13, count 0 2006.253.07:50:02.26#ibcon#read 6, iclass 13, count 0 2006.253.07:50:02.26#ibcon#end of sib2, iclass 13, count 0 2006.253.07:50:02.26#ibcon#*mode == 0, iclass 13, count 0 2006.253.07:50:02.26#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.253.07:50:02.26#ibcon#[27=USB\r\n] 2006.253.07:50:02.26#ibcon#*before write, iclass 13, count 0 2006.253.07:50:02.26#ibcon#enter sib2, iclass 13, count 0 2006.253.07:50:02.26#ibcon#flushed, iclass 13, count 0 2006.253.07:50:02.26#ibcon#about to write, iclass 13, count 0 2006.253.07:50:02.26#ibcon#wrote, iclass 13, count 0 2006.253.07:50:02.26#ibcon#about to read 3, iclass 13, count 0 2006.253.07:50:02.29#ibcon#read 3, iclass 13, count 0 2006.253.07:50:02.29#ibcon#about to read 4, iclass 13, count 0 2006.253.07:50:02.29#ibcon#read 4, iclass 13, count 0 2006.253.07:50:02.29#ibcon#about to read 5, iclass 13, count 0 2006.253.07:50:02.29#ibcon#read 5, iclass 13, count 0 2006.253.07:50:02.29#ibcon#about to read 6, iclass 13, count 0 2006.253.07:50:02.29#ibcon#read 6, iclass 13, count 0 2006.253.07:50:02.29#ibcon#end of sib2, iclass 13, count 0 2006.253.07:50:02.29#ibcon#*after write, iclass 13, count 0 2006.253.07:50:02.29#ibcon#*before return 0, iclass 13, count 0 2006.253.07:50:02.29#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.253.07:50:02.29#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.253.07:50:02.29#ibcon#about to clear, iclass 13 cls_cnt 0 2006.253.07:50:02.29#ibcon#cleared, iclass 13 cls_cnt 0 2006.253.07:50:02.29$vc4f8/vblo=6,752.99 2006.253.07:50:02.29#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.253.07:50:02.29#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.253.07:50:02.29#ibcon#ireg 17 cls_cnt 0 2006.253.07:50:02.29#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.253.07:50:02.29#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.253.07:50:02.29#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.253.07:50:02.29#ibcon#enter wrdev, iclass 15, count 0 2006.253.07:50:02.29#ibcon#first serial, iclass 15, count 0 2006.253.07:50:02.29#ibcon#enter sib2, iclass 15, count 0 2006.253.07:50:02.29#ibcon#flushed, iclass 15, count 0 2006.253.07:50:02.29#ibcon#about to write, iclass 15, count 0 2006.253.07:50:02.29#ibcon#wrote, iclass 15, count 0 2006.253.07:50:02.29#ibcon#about to read 3, iclass 15, count 0 2006.253.07:50:02.31#ibcon#read 3, iclass 15, count 0 2006.253.07:50:02.31#ibcon#about to read 4, iclass 15, count 0 2006.253.07:50:02.31#ibcon#read 4, iclass 15, count 0 2006.253.07:50:02.31#ibcon#about to read 5, iclass 15, count 0 2006.253.07:50:02.31#ibcon#read 5, iclass 15, count 0 2006.253.07:50:02.31#ibcon#about to read 6, iclass 15, count 0 2006.253.07:50:02.31#ibcon#read 6, iclass 15, count 0 2006.253.07:50:02.31#ibcon#end of sib2, iclass 15, count 0 2006.253.07:50:02.31#ibcon#*mode == 0, iclass 15, count 0 2006.253.07:50:02.31#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.253.07:50:02.31#ibcon#[28=FRQ=06,752.99\r\n] 2006.253.07:50:02.31#ibcon#*before write, iclass 15, count 0 2006.253.07:50:02.31#ibcon#enter sib2, iclass 15, count 0 2006.253.07:50:02.31#ibcon#flushed, iclass 15, count 0 2006.253.07:50:02.31#ibcon#about to write, iclass 15, count 0 2006.253.07:50:02.31#ibcon#wrote, iclass 15, count 0 2006.253.07:50:02.31#ibcon#about to read 3, iclass 15, count 0 2006.253.07:50:02.35#ibcon#read 3, iclass 15, count 0 2006.253.07:50:02.35#ibcon#about to read 4, iclass 15, count 0 2006.253.07:50:02.35#ibcon#read 4, iclass 15, count 0 2006.253.07:50:02.35#ibcon#about to read 5, iclass 15, count 0 2006.253.07:50:02.35#ibcon#read 5, iclass 15, count 0 2006.253.07:50:02.35#ibcon#about to read 6, iclass 15, count 0 2006.253.07:50:02.35#ibcon#read 6, iclass 15, count 0 2006.253.07:50:02.35#ibcon#end of sib2, iclass 15, count 0 2006.253.07:50:02.35#ibcon#*after write, iclass 15, count 0 2006.253.07:50:02.35#ibcon#*before return 0, iclass 15, count 0 2006.253.07:50:02.35#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.253.07:50:02.35#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.253.07:50:02.35#ibcon#about to clear, iclass 15 cls_cnt 0 2006.253.07:50:02.35#ibcon#cleared, iclass 15 cls_cnt 0 2006.253.07:50:02.35$vc4f8/vb=6,4 2006.253.07:50:02.35#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.253.07:50:02.35#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.253.07:50:02.35#ibcon#ireg 11 cls_cnt 2 2006.253.07:50:02.35#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.253.07:50:02.41#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.253.07:50:02.41#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.253.07:50:02.41#ibcon#enter wrdev, iclass 17, count 2 2006.253.07:50:02.41#ibcon#first serial, iclass 17, count 2 2006.253.07:50:02.41#ibcon#enter sib2, iclass 17, count 2 2006.253.07:50:02.41#ibcon#flushed, iclass 17, count 2 2006.253.07:50:02.41#ibcon#about to write, iclass 17, count 2 2006.253.07:50:02.41#ibcon#wrote, iclass 17, count 2 2006.253.07:50:02.41#ibcon#about to read 3, iclass 17, count 2 2006.253.07:50:02.43#ibcon#read 3, iclass 17, count 2 2006.253.07:50:02.43#ibcon#about to read 4, iclass 17, count 2 2006.253.07:50:02.43#ibcon#read 4, iclass 17, count 2 2006.253.07:50:02.43#ibcon#about to read 5, iclass 17, count 2 2006.253.07:50:02.43#ibcon#read 5, iclass 17, count 2 2006.253.07:50:02.43#ibcon#about to read 6, iclass 17, count 2 2006.253.07:50:02.43#ibcon#read 6, iclass 17, count 2 2006.253.07:50:02.43#ibcon#end of sib2, iclass 17, count 2 2006.253.07:50:02.43#ibcon#*mode == 0, iclass 17, count 2 2006.253.07:50:02.43#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.253.07:50:02.43#ibcon#[27=AT06-04\r\n] 2006.253.07:50:02.43#ibcon#*before write, iclass 17, count 2 2006.253.07:50:02.43#ibcon#enter sib2, iclass 17, count 2 2006.253.07:50:02.43#ibcon#flushed, iclass 17, count 2 2006.253.07:50:02.43#ibcon#about to write, iclass 17, count 2 2006.253.07:50:02.43#ibcon#wrote, iclass 17, count 2 2006.253.07:50:02.43#ibcon#about to read 3, iclass 17, count 2 2006.253.07:50:02.46#abcon#{5=INTERFACE CLEAR} 2006.253.07:50:02.46#ibcon#read 3, iclass 17, count 2 2006.253.07:50:02.46#ibcon#about to read 4, iclass 17, count 2 2006.253.07:50:02.46#ibcon#read 4, iclass 17, count 2 2006.253.07:50:02.46#ibcon#about to read 5, iclass 17, count 2 2006.253.07:50:02.46#ibcon#read 5, iclass 17, count 2 2006.253.07:50:02.46#ibcon#about to read 6, iclass 17, count 2 2006.253.07:50:02.46#ibcon#read 6, iclass 17, count 2 2006.253.07:50:02.46#ibcon#end of sib2, iclass 17, count 2 2006.253.07:50:02.46#ibcon#*after write, iclass 17, count 2 2006.253.07:50:02.46#ibcon#*before return 0, iclass 17, count 2 2006.253.07:50:02.46#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.253.07:50:02.46#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.253.07:50:02.46#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.253.07:50:02.46#ibcon#ireg 7 cls_cnt 0 2006.253.07:50:02.46#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.253.07:50:02.52#abcon#[5=S1D000X0/0*\r\n] 2006.253.07:50:02.58#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.253.07:50:02.58#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.253.07:50:02.58#ibcon#enter wrdev, iclass 17, count 0 2006.253.07:50:02.58#ibcon#first serial, iclass 17, count 0 2006.253.07:50:02.58#ibcon#enter sib2, iclass 17, count 0 2006.253.07:50:02.58#ibcon#flushed, iclass 17, count 0 2006.253.07:50:02.58#ibcon#about to write, iclass 17, count 0 2006.253.07:50:02.58#ibcon#wrote, iclass 17, count 0 2006.253.07:50:02.58#ibcon#about to read 3, iclass 17, count 0 2006.253.07:50:02.60#ibcon#read 3, iclass 17, count 0 2006.253.07:50:02.60#ibcon#about to read 4, iclass 17, count 0 2006.253.07:50:02.60#ibcon#read 4, iclass 17, count 0 2006.253.07:50:02.60#ibcon#about to read 5, iclass 17, count 0 2006.253.07:50:02.60#ibcon#read 5, iclass 17, count 0 2006.253.07:50:02.60#ibcon#about to read 6, iclass 17, count 0 2006.253.07:50:02.60#ibcon#read 6, iclass 17, count 0 2006.253.07:50:02.60#ibcon#end of sib2, iclass 17, count 0 2006.253.07:50:02.60#ibcon#*mode == 0, iclass 17, count 0 2006.253.07:50:02.60#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.253.07:50:02.60#ibcon#[27=USB\r\n] 2006.253.07:50:02.60#ibcon#*before write, iclass 17, count 0 2006.253.07:50:02.60#ibcon#enter sib2, iclass 17, count 0 2006.253.07:50:02.60#ibcon#flushed, iclass 17, count 0 2006.253.07:50:02.60#ibcon#about to write, iclass 17, count 0 2006.253.07:50:02.60#ibcon#wrote, iclass 17, count 0 2006.253.07:50:02.60#ibcon#about to read 3, iclass 17, count 0 2006.253.07:50:02.63#ibcon#read 3, iclass 17, count 0 2006.253.07:50:02.63#ibcon#about to read 4, iclass 17, count 0 2006.253.07:50:02.63#ibcon#read 4, iclass 17, count 0 2006.253.07:50:02.63#ibcon#about to read 5, iclass 17, count 0 2006.253.07:50:02.63#ibcon#read 5, iclass 17, count 0 2006.253.07:50:02.63#ibcon#about to read 6, iclass 17, count 0 2006.253.07:50:02.63#ibcon#read 6, iclass 17, count 0 2006.253.07:50:02.63#ibcon#end of sib2, iclass 17, count 0 2006.253.07:50:02.63#ibcon#*after write, iclass 17, count 0 2006.253.07:50:02.63#ibcon#*before return 0, iclass 17, count 0 2006.253.07:50:02.63#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.253.07:50:02.63#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.253.07:50:02.63#ibcon#about to clear, iclass 17 cls_cnt 0 2006.253.07:50:02.63#ibcon#cleared, iclass 17 cls_cnt 0 2006.253.07:50:02.63$vc4f8/vabw=wide 2006.253.07:50:02.63#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.253.07:50:02.63#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.253.07:50:02.63#ibcon#ireg 8 cls_cnt 0 2006.253.07:50:02.63#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.253.07:50:02.63#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.253.07:50:02.63#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.253.07:50:02.63#ibcon#enter wrdev, iclass 21, count 0 2006.253.07:50:02.63#ibcon#first serial, iclass 21, count 0 2006.253.07:50:02.63#ibcon#enter sib2, iclass 21, count 0 2006.253.07:50:02.63#ibcon#flushed, iclass 21, count 0 2006.253.07:50:02.63#ibcon#about to write, iclass 21, count 0 2006.253.07:50:02.63#ibcon#wrote, iclass 21, count 0 2006.253.07:50:02.63#ibcon#about to read 3, iclass 21, count 0 2006.253.07:50:02.65#ibcon#read 3, iclass 21, count 0 2006.253.07:50:02.65#ibcon#about to read 4, iclass 21, count 0 2006.253.07:50:02.65#ibcon#read 4, iclass 21, count 0 2006.253.07:50:02.65#ibcon#about to read 5, iclass 21, count 0 2006.253.07:50:02.65#ibcon#read 5, iclass 21, count 0 2006.253.07:50:02.65#ibcon#about to read 6, iclass 21, count 0 2006.253.07:50:02.65#ibcon#read 6, iclass 21, count 0 2006.253.07:50:02.65#ibcon#end of sib2, iclass 21, count 0 2006.253.07:50:02.65#ibcon#*mode == 0, iclass 21, count 0 2006.253.07:50:02.65#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.253.07:50:02.65#ibcon#[25=BW32\r\n] 2006.253.07:50:02.65#ibcon#*before write, iclass 21, count 0 2006.253.07:50:02.65#ibcon#enter sib2, iclass 21, count 0 2006.253.07:50:02.65#ibcon#flushed, iclass 21, count 0 2006.253.07:50:02.65#ibcon#about to write, iclass 21, count 0 2006.253.07:50:02.65#ibcon#wrote, iclass 21, count 0 2006.253.07:50:02.65#ibcon#about to read 3, iclass 21, count 0 2006.253.07:50:02.68#ibcon#read 3, iclass 21, count 0 2006.253.07:50:02.68#ibcon#about to read 4, iclass 21, count 0 2006.253.07:50:02.68#ibcon#read 4, iclass 21, count 0 2006.253.07:50:02.68#ibcon#about to read 5, iclass 21, count 0 2006.253.07:50:02.68#ibcon#read 5, iclass 21, count 0 2006.253.07:50:02.68#ibcon#about to read 6, iclass 21, count 0 2006.253.07:50:02.68#ibcon#read 6, iclass 21, count 0 2006.253.07:50:02.68#ibcon#end of sib2, iclass 21, count 0 2006.253.07:50:02.68#ibcon#*after write, iclass 21, count 0 2006.253.07:50:02.68#ibcon#*before return 0, iclass 21, count 0 2006.253.07:50:02.68#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.253.07:50:02.68#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.253.07:50:02.68#ibcon#about to clear, iclass 21 cls_cnt 0 2006.253.07:50:02.68#ibcon#cleared, iclass 21 cls_cnt 0 2006.253.07:50:02.68$vc4f8/vbbw=wide 2006.253.07:50:02.68#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.253.07:50:02.68#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.253.07:50:02.68#ibcon#ireg 8 cls_cnt 0 2006.253.07:50:02.68#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.253.07:50:02.75#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.253.07:50:02.75#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.253.07:50:02.75#ibcon#enter wrdev, iclass 23, count 0 2006.253.07:50:02.75#ibcon#first serial, iclass 23, count 0 2006.253.07:50:02.75#ibcon#enter sib2, iclass 23, count 0 2006.253.07:50:02.75#ibcon#flushed, iclass 23, count 0 2006.253.07:50:02.75#ibcon#about to write, iclass 23, count 0 2006.253.07:50:02.75#ibcon#wrote, iclass 23, count 0 2006.253.07:50:02.75#ibcon#about to read 3, iclass 23, count 0 2006.253.07:50:02.77#ibcon#read 3, iclass 23, count 0 2006.253.07:50:02.77#ibcon#about to read 4, iclass 23, count 0 2006.253.07:50:02.77#ibcon#read 4, iclass 23, count 0 2006.253.07:50:02.77#ibcon#about to read 5, iclass 23, count 0 2006.253.07:50:02.77#ibcon#read 5, iclass 23, count 0 2006.253.07:50:02.77#ibcon#about to read 6, iclass 23, count 0 2006.253.07:50:02.77#ibcon#read 6, iclass 23, count 0 2006.253.07:50:02.77#ibcon#end of sib2, iclass 23, count 0 2006.253.07:50:02.77#ibcon#*mode == 0, iclass 23, count 0 2006.253.07:50:02.77#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.253.07:50:02.77#ibcon#[27=BW32\r\n] 2006.253.07:50:02.77#ibcon#*before write, iclass 23, count 0 2006.253.07:50:02.77#ibcon#enter sib2, iclass 23, count 0 2006.253.07:50:02.77#ibcon#flushed, iclass 23, count 0 2006.253.07:50:02.77#ibcon#about to write, iclass 23, count 0 2006.253.07:50:02.77#ibcon#wrote, iclass 23, count 0 2006.253.07:50:02.77#ibcon#about to read 3, iclass 23, count 0 2006.253.07:50:02.80#ibcon#read 3, iclass 23, count 0 2006.253.07:50:02.80#ibcon#about to read 4, iclass 23, count 0 2006.253.07:50:02.80#ibcon#read 4, iclass 23, count 0 2006.253.07:50:02.80#ibcon#about to read 5, iclass 23, count 0 2006.253.07:50:02.80#ibcon#read 5, iclass 23, count 0 2006.253.07:50:02.80#ibcon#about to read 6, iclass 23, count 0 2006.253.07:50:02.80#ibcon#read 6, iclass 23, count 0 2006.253.07:50:02.80#ibcon#end of sib2, iclass 23, count 0 2006.253.07:50:02.80#ibcon#*after write, iclass 23, count 0 2006.253.07:50:02.80#ibcon#*before return 0, iclass 23, count 0 2006.253.07:50:02.80#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.253.07:50:02.80#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.253.07:50:02.80#ibcon#about to clear, iclass 23 cls_cnt 0 2006.253.07:50:02.80#ibcon#cleared, iclass 23 cls_cnt 0 2006.253.07:50:02.80$4f8m12a/ifd4f 2006.253.07:50:02.80$ifd4f/lo= 2006.253.07:50:02.80$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.253.07:50:02.80$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.253.07:50:02.80$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.253.07:50:02.80$ifd4f/patch= 2006.253.07:50:02.80$ifd4f/patch=lo1,a1,a2,a3,a4 2006.253.07:50:02.81$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.253.07:50:02.81$ifd4f/patch=lo3,a5,a6,a7,a8 2006.253.07:50:02.81$4f8m12a/"form=m,16.000,1:2 2006.253.07:50:02.81$4f8m12a/"tpicd 2006.253.07:50:02.81$4f8m12a/echo=off 2006.253.07:50:02.81$4f8m12a/xlog=off 2006.253.07:50:02.81:!2006.253.07:50:30 2006.253.07:50:17.14#trakl#Source acquired 2006.253.07:50:18.14#flagr#flagr/antenna,acquired 2006.253.07:50:30.01:preob 2006.253.07:50:31.14/onsource/TRACKING 2006.253.07:50:31.14:!2006.253.07:50:40 2006.253.07:50:40.00:data_valid=on 2006.253.07:50:40.00:midob 2006.253.07:50:40.14/onsource/TRACKING 2006.253.07:50:40.14/wx/31.31,1006.4,73 2006.253.07:50:40.28/cable/+6.3666E-03 2006.253.07:50:41.37/va/01,08,usb,yes,32,33 2006.253.07:50:41.37/va/02,07,usb,yes,32,33 2006.253.07:50:41.37/va/03,06,usb,yes,34,34 2006.253.07:50:41.37/va/04,07,usb,yes,33,36 2006.253.07:50:41.37/va/05,07,usb,yes,34,36 2006.253.07:50:41.37/va/06,07,usb,yes,30,30 2006.253.07:50:41.37/va/07,07,usb,yes,30,30 2006.253.07:50:41.37/va/08,07,usb,yes,32,32 2006.253.07:50:41.60/valo/01,532.99,yes,locked 2006.253.07:50:41.60/valo/02,572.99,yes,locked 2006.253.07:50:41.60/valo/03,672.99,yes,locked 2006.253.07:50:41.60/valo/04,832.99,yes,locked 2006.253.07:50:41.60/valo/05,652.99,yes,locked 2006.253.07:50:41.60/valo/06,772.99,yes,locked 2006.253.07:50:41.60/valo/07,832.99,yes,locked 2006.253.07:50:41.60/valo/08,852.99,yes,locked 2006.253.07:50:42.69/vb/01,04,usb,yes,31,30 2006.253.07:50:42.69/vb/02,05,usb,yes,29,30 2006.253.07:50:42.69/vb/03,04,usb,yes,29,33 2006.253.07:50:42.69/vb/04,04,usb,yes,30,30 2006.253.07:50:42.69/vb/05,04,usb,yes,28,32 2006.253.07:50:42.69/vb/06,04,usb,yes,29,32 2006.253.07:50:42.69/vb/07,04,usb,yes,31,31 2006.253.07:50:42.69/vb/08,04,usb,yes,29,32 2006.253.07:50:42.93/vblo/01,632.99,yes,locked 2006.253.07:50:42.93/vblo/02,640.99,yes,locked 2006.253.07:50:42.93/vblo/03,656.99,yes,locked 2006.253.07:50:42.93/vblo/04,712.99,yes,locked 2006.253.07:50:42.93/vblo/05,744.99,yes,locked 2006.253.07:50:42.93/vblo/06,752.99,yes,locked 2006.253.07:50:42.93/vblo/07,734.99,yes,locked 2006.253.07:50:42.93/vblo/08,744.99,yes,locked 2006.253.07:50:43.08/vabw/8 2006.253.07:50:43.23/vbbw/8 2006.253.07:50:43.32/xfe/off,on,14.2 2006.253.07:50:43.69/ifatt/23,28,28,28 2006.253.07:50:44.07/fmout-gps/S +4.75E-07 2006.253.07:50:44.12:!2006.253.07:51:50 2006.253.07:51:50.01:data_valid=off 2006.253.07:51:50.02:postob 2006.253.07:51:50.14/cable/+6.3684E-03 2006.253.07:51:50.15/wx/31.28,1006.4,73 2006.253.07:51:51.07/fmout-gps/S +4.73E-07 2006.253.07:51:51.08:scan_name=253-0752,k06253,60 2006.253.07:51:51.08:source=1357+769,135755.37,764321.1,2000.0,ccw 2006.253.07:51:52.14#flagr#flagr/antenna,new-source 2006.253.07:51:52.15:checkk5 2006.253.07:51:52.52/chk_autoobs//k5ts1/ autoobs is running! 2006.253.07:51:52.90/chk_autoobs//k5ts2/ autoobs is running! 2006.253.07:51:53.29/chk_autoobs//k5ts3/ autoobs is running! 2006.253.07:51:53.66/chk_autoobs//k5ts4/ autoobs is running! 2006.253.07:51:54.04/chk_obsdata//k5ts1/T2530750??a.dat file size is correct (nominal:560MB, actual:560MB). 2006.253.07:51:54.41/chk_obsdata//k5ts2/T2530750??b.dat file size is correct (nominal:560MB, actual:560MB). 2006.253.07:51:54.78/chk_obsdata//k5ts3/T2530750??c.dat file size is correct (nominal:560MB, actual:560MB). 2006.253.07:51:55.15/chk_obsdata//k5ts4/T2530750??d.dat file size is correct (nominal:560MB, actual:560MB). 2006.253.07:51:55.84/k5log//k5ts1_log_newline 2006.253.07:51:56.54/k5log//k5ts2_log_newline 2006.253.07:51:57.23/k5log//k5ts3_log_newline 2006.253.07:51:57.92/k5log//k5ts4_log_newline 2006.253.07:51:57.94/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.253.07:51:57.94:4f8m12a=1 2006.253.07:51:57.94$4f8m12a/echo=on 2006.253.07:51:57.94$4f8m12a/pcalon 2006.253.07:51:57.94$pcalon/"no phase cal control is implemented here 2006.253.07:51:57.94$4f8m12a/"tpicd=stop 2006.253.07:51:57.94$4f8m12a/vc4f8 2006.253.07:51:57.94$vc4f8/valo=1,532.99 2006.253.07:51:57.94#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.253.07:51:57.94#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.253.07:51:57.94#ibcon#ireg 17 cls_cnt 0 2006.253.07:51:57.94#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.253.07:51:57.94#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.253.07:51:57.94#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.253.07:51:57.94#ibcon#enter wrdev, iclass 34, count 0 2006.253.07:51:57.94#ibcon#first serial, iclass 34, count 0 2006.253.07:51:57.94#ibcon#enter sib2, iclass 34, count 0 2006.253.07:51:57.94#ibcon#flushed, iclass 34, count 0 2006.253.07:51:57.94#ibcon#about to write, iclass 34, count 0 2006.253.07:51:57.94#ibcon#wrote, iclass 34, count 0 2006.253.07:51:57.94#ibcon#about to read 3, iclass 34, count 0 2006.253.07:51:57.98#ibcon#read 3, iclass 34, count 0 2006.253.07:51:57.98#ibcon#about to read 4, iclass 34, count 0 2006.253.07:51:57.98#ibcon#read 4, iclass 34, count 0 2006.253.07:51:57.98#ibcon#about to read 5, iclass 34, count 0 2006.253.07:51:57.98#ibcon#read 5, iclass 34, count 0 2006.253.07:51:57.98#ibcon#about to read 6, iclass 34, count 0 2006.253.07:51:57.98#ibcon#read 6, iclass 34, count 0 2006.253.07:51:57.98#ibcon#end of sib2, iclass 34, count 0 2006.253.07:51:57.98#ibcon#*mode == 0, iclass 34, count 0 2006.253.07:51:57.98#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.253.07:51:57.98#ibcon#[26=FRQ=01,532.99\r\n] 2006.253.07:51:57.98#ibcon#*before write, iclass 34, count 0 2006.253.07:51:57.98#ibcon#enter sib2, iclass 34, count 0 2006.253.07:51:57.98#ibcon#flushed, iclass 34, count 0 2006.253.07:51:57.98#ibcon#about to write, iclass 34, count 0 2006.253.07:51:57.98#ibcon#wrote, iclass 34, count 0 2006.253.07:51:57.98#ibcon#about to read 3, iclass 34, count 0 2006.253.07:51:58.03#ibcon#read 3, iclass 34, count 0 2006.253.07:51:58.03#ibcon#about to read 4, iclass 34, count 0 2006.253.07:51:58.03#ibcon#read 4, iclass 34, count 0 2006.253.07:51:58.03#ibcon#about to read 5, iclass 34, count 0 2006.253.07:51:58.03#ibcon#read 5, iclass 34, count 0 2006.253.07:51:58.03#ibcon#about to read 6, iclass 34, count 0 2006.253.07:51:58.03#ibcon#read 6, iclass 34, count 0 2006.253.07:51:58.03#ibcon#end of sib2, iclass 34, count 0 2006.253.07:51:58.03#ibcon#*after write, iclass 34, count 0 2006.253.07:51:58.03#ibcon#*before return 0, iclass 34, count 0 2006.253.07:51:58.03#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.253.07:51:58.03#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.253.07:51:58.03#ibcon#about to clear, iclass 34 cls_cnt 0 2006.253.07:51:58.03#ibcon#cleared, iclass 34 cls_cnt 0 2006.253.07:51:58.03$vc4f8/va=1,8 2006.253.07:51:58.03#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.253.07:51:58.03#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.253.07:51:58.03#ibcon#ireg 11 cls_cnt 2 2006.253.07:51:58.03#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.253.07:51:58.03#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.253.07:51:58.03#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.253.07:51:58.03#ibcon#enter wrdev, iclass 36, count 2 2006.253.07:51:58.03#ibcon#first serial, iclass 36, count 2 2006.253.07:51:58.03#ibcon#enter sib2, iclass 36, count 2 2006.253.07:51:58.03#ibcon#flushed, iclass 36, count 2 2006.253.07:51:58.03#ibcon#about to write, iclass 36, count 2 2006.253.07:51:58.03#ibcon#wrote, iclass 36, count 2 2006.253.07:51:58.03#ibcon#about to read 3, iclass 36, count 2 2006.253.07:51:58.06#ibcon#read 3, iclass 36, count 2 2006.253.07:51:58.06#ibcon#about to read 4, iclass 36, count 2 2006.253.07:51:58.06#ibcon#read 4, iclass 36, count 2 2006.253.07:51:58.06#ibcon#about to read 5, iclass 36, count 2 2006.253.07:51:58.06#ibcon#read 5, iclass 36, count 2 2006.253.07:51:58.06#ibcon#about to read 6, iclass 36, count 2 2006.253.07:51:58.06#ibcon#read 6, iclass 36, count 2 2006.253.07:51:58.06#ibcon#end of sib2, iclass 36, count 2 2006.253.07:51:58.06#ibcon#*mode == 0, iclass 36, count 2 2006.253.07:51:58.06#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.253.07:51:58.06#ibcon#[25=AT01-08\r\n] 2006.253.07:51:58.06#ibcon#*before write, iclass 36, count 2 2006.253.07:51:58.06#ibcon#enter sib2, iclass 36, count 2 2006.253.07:51:58.06#ibcon#flushed, iclass 36, count 2 2006.253.07:51:58.06#ibcon#about to write, iclass 36, count 2 2006.253.07:51:58.06#ibcon#wrote, iclass 36, count 2 2006.253.07:51:58.06#ibcon#about to read 3, iclass 36, count 2 2006.253.07:51:58.09#ibcon#read 3, iclass 36, count 2 2006.253.07:51:58.09#ibcon#about to read 4, iclass 36, count 2 2006.253.07:51:58.09#ibcon#read 4, iclass 36, count 2 2006.253.07:51:58.09#ibcon#about to read 5, iclass 36, count 2 2006.253.07:51:58.09#ibcon#read 5, iclass 36, count 2 2006.253.07:51:58.09#ibcon#about to read 6, iclass 36, count 2 2006.253.07:51:58.09#ibcon#read 6, iclass 36, count 2 2006.253.07:51:58.09#ibcon#end of sib2, iclass 36, count 2 2006.253.07:51:58.09#ibcon#*after write, iclass 36, count 2 2006.253.07:51:58.09#ibcon#*before return 0, iclass 36, count 2 2006.253.07:51:58.09#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.253.07:51:58.09#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.253.07:51:58.09#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.253.07:51:58.09#ibcon#ireg 7 cls_cnt 0 2006.253.07:51:58.09#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.253.07:51:58.21#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.253.07:51:58.21#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.253.07:51:58.21#ibcon#enter wrdev, iclass 36, count 0 2006.253.07:51:58.21#ibcon#first serial, iclass 36, count 0 2006.253.07:51:58.21#ibcon#enter sib2, iclass 36, count 0 2006.253.07:51:58.21#ibcon#flushed, iclass 36, count 0 2006.253.07:51:58.21#ibcon#about to write, iclass 36, count 0 2006.253.07:51:58.21#ibcon#wrote, iclass 36, count 0 2006.253.07:51:58.21#ibcon#about to read 3, iclass 36, count 0 2006.253.07:51:58.23#ibcon#read 3, iclass 36, count 0 2006.253.07:51:58.23#ibcon#about to read 4, iclass 36, count 0 2006.253.07:51:58.23#ibcon#read 4, iclass 36, count 0 2006.253.07:51:58.23#ibcon#about to read 5, iclass 36, count 0 2006.253.07:51:58.23#ibcon#read 5, iclass 36, count 0 2006.253.07:51:58.23#ibcon#about to read 6, iclass 36, count 0 2006.253.07:51:58.23#ibcon#read 6, iclass 36, count 0 2006.253.07:51:58.23#ibcon#end of sib2, iclass 36, count 0 2006.253.07:51:58.23#ibcon#*mode == 0, iclass 36, count 0 2006.253.07:51:58.23#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.253.07:51:58.23#ibcon#[25=USB\r\n] 2006.253.07:51:58.23#ibcon#*before write, iclass 36, count 0 2006.253.07:51:58.23#ibcon#enter sib2, iclass 36, count 0 2006.253.07:51:58.23#ibcon#flushed, iclass 36, count 0 2006.253.07:51:58.23#ibcon#about to write, iclass 36, count 0 2006.253.07:51:58.23#ibcon#wrote, iclass 36, count 0 2006.253.07:51:58.23#ibcon#about to read 3, iclass 36, count 0 2006.253.07:51:58.26#ibcon#read 3, iclass 36, count 0 2006.253.07:51:58.26#ibcon#about to read 4, iclass 36, count 0 2006.253.07:51:58.26#ibcon#read 4, iclass 36, count 0 2006.253.07:51:58.26#ibcon#about to read 5, iclass 36, count 0 2006.253.07:51:58.26#ibcon#read 5, iclass 36, count 0 2006.253.07:51:58.26#ibcon#about to read 6, iclass 36, count 0 2006.253.07:51:58.26#ibcon#read 6, iclass 36, count 0 2006.253.07:51:58.26#ibcon#end of sib2, iclass 36, count 0 2006.253.07:51:58.26#ibcon#*after write, iclass 36, count 0 2006.253.07:51:58.26#ibcon#*before return 0, iclass 36, count 0 2006.253.07:51:58.26#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.253.07:51:58.26#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.253.07:51:58.26#ibcon#about to clear, iclass 36 cls_cnt 0 2006.253.07:51:58.26#ibcon#cleared, iclass 36 cls_cnt 0 2006.253.07:51:58.26$vc4f8/valo=2,572.99 2006.253.07:51:58.26#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.253.07:51:58.26#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.253.07:51:58.26#ibcon#ireg 17 cls_cnt 0 2006.253.07:51:58.26#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.253.07:51:58.26#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.253.07:51:58.26#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.253.07:51:58.26#ibcon#enter wrdev, iclass 38, count 0 2006.253.07:51:58.26#ibcon#first serial, iclass 38, count 0 2006.253.07:51:58.26#ibcon#enter sib2, iclass 38, count 0 2006.253.07:51:58.26#ibcon#flushed, iclass 38, count 0 2006.253.07:51:58.26#ibcon#about to write, iclass 38, count 0 2006.253.07:51:58.26#ibcon#wrote, iclass 38, count 0 2006.253.07:51:58.26#ibcon#about to read 3, iclass 38, count 0 2006.253.07:51:58.28#ibcon#read 3, iclass 38, count 0 2006.253.07:51:58.28#ibcon#about to read 4, iclass 38, count 0 2006.253.07:51:58.28#ibcon#read 4, iclass 38, count 0 2006.253.07:51:58.28#ibcon#about to read 5, iclass 38, count 0 2006.253.07:51:58.28#ibcon#read 5, iclass 38, count 0 2006.253.07:51:58.28#ibcon#about to read 6, iclass 38, count 0 2006.253.07:51:58.28#ibcon#read 6, iclass 38, count 0 2006.253.07:51:58.28#ibcon#end of sib2, iclass 38, count 0 2006.253.07:51:58.28#ibcon#*mode == 0, iclass 38, count 0 2006.253.07:51:58.28#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.253.07:51:58.28#ibcon#[26=FRQ=02,572.99\r\n] 2006.253.07:51:58.28#ibcon#*before write, iclass 38, count 0 2006.253.07:51:58.28#ibcon#enter sib2, iclass 38, count 0 2006.253.07:51:58.28#ibcon#flushed, iclass 38, count 0 2006.253.07:51:58.28#ibcon#about to write, iclass 38, count 0 2006.253.07:51:58.28#ibcon#wrote, iclass 38, count 0 2006.253.07:51:58.28#ibcon#about to read 3, iclass 38, count 0 2006.253.07:51:58.32#ibcon#read 3, iclass 38, count 0 2006.253.07:51:58.32#ibcon#about to read 4, iclass 38, count 0 2006.253.07:51:58.32#ibcon#read 4, iclass 38, count 0 2006.253.07:51:58.32#ibcon#about to read 5, iclass 38, count 0 2006.253.07:51:58.32#ibcon#read 5, iclass 38, count 0 2006.253.07:51:58.32#ibcon#about to read 6, iclass 38, count 0 2006.253.07:51:58.32#ibcon#read 6, iclass 38, count 0 2006.253.07:51:58.32#ibcon#end of sib2, iclass 38, count 0 2006.253.07:51:58.32#ibcon#*after write, iclass 38, count 0 2006.253.07:51:58.32#ibcon#*before return 0, iclass 38, count 0 2006.253.07:51:58.32#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.253.07:51:58.32#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.253.07:51:58.32#ibcon#about to clear, iclass 38 cls_cnt 0 2006.253.07:51:58.32#ibcon#cleared, iclass 38 cls_cnt 0 2006.253.07:51:58.32$vc4f8/va=2,7 2006.253.07:51:58.32#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.253.07:51:58.32#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.253.07:51:58.32#ibcon#ireg 11 cls_cnt 2 2006.253.07:51:58.32#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.253.07:51:58.38#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.253.07:51:58.38#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.253.07:51:58.38#ibcon#enter wrdev, iclass 40, count 2 2006.253.07:51:58.38#ibcon#first serial, iclass 40, count 2 2006.253.07:51:58.38#ibcon#enter sib2, iclass 40, count 2 2006.253.07:51:58.38#ibcon#flushed, iclass 40, count 2 2006.253.07:51:58.38#ibcon#about to write, iclass 40, count 2 2006.253.07:51:58.38#ibcon#wrote, iclass 40, count 2 2006.253.07:51:58.38#ibcon#about to read 3, iclass 40, count 2 2006.253.07:51:58.40#ibcon#read 3, iclass 40, count 2 2006.253.07:51:58.40#ibcon#about to read 4, iclass 40, count 2 2006.253.07:51:58.40#ibcon#read 4, iclass 40, count 2 2006.253.07:51:58.40#ibcon#about to read 5, iclass 40, count 2 2006.253.07:51:58.40#ibcon#read 5, iclass 40, count 2 2006.253.07:51:58.40#ibcon#about to read 6, iclass 40, count 2 2006.253.07:51:58.40#ibcon#read 6, iclass 40, count 2 2006.253.07:51:58.40#ibcon#end of sib2, iclass 40, count 2 2006.253.07:51:58.40#ibcon#*mode == 0, iclass 40, count 2 2006.253.07:51:58.40#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.253.07:51:58.40#ibcon#[25=AT02-07\r\n] 2006.253.07:51:58.40#ibcon#*before write, iclass 40, count 2 2006.253.07:51:58.40#ibcon#enter sib2, iclass 40, count 2 2006.253.07:51:58.40#ibcon#flushed, iclass 40, count 2 2006.253.07:51:58.40#ibcon#about to write, iclass 40, count 2 2006.253.07:51:58.40#ibcon#wrote, iclass 40, count 2 2006.253.07:51:58.40#ibcon#about to read 3, iclass 40, count 2 2006.253.07:51:58.43#ibcon#read 3, iclass 40, count 2 2006.253.07:51:58.43#ibcon#about to read 4, iclass 40, count 2 2006.253.07:51:58.43#ibcon#read 4, iclass 40, count 2 2006.253.07:51:58.43#ibcon#about to read 5, iclass 40, count 2 2006.253.07:51:58.43#ibcon#read 5, iclass 40, count 2 2006.253.07:51:58.43#ibcon#about to read 6, iclass 40, count 2 2006.253.07:51:58.43#ibcon#read 6, iclass 40, count 2 2006.253.07:51:58.43#ibcon#end of sib2, iclass 40, count 2 2006.253.07:51:58.43#ibcon#*after write, iclass 40, count 2 2006.253.07:51:58.43#ibcon#*before return 0, iclass 40, count 2 2006.253.07:51:58.43#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.253.07:51:58.43#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.253.07:51:58.43#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.253.07:51:58.43#ibcon#ireg 7 cls_cnt 0 2006.253.07:51:58.43#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.253.07:51:58.56#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.253.07:51:58.56#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.253.07:51:58.56#ibcon#enter wrdev, iclass 40, count 0 2006.253.07:51:58.56#ibcon#first serial, iclass 40, count 0 2006.253.07:51:58.56#ibcon#enter sib2, iclass 40, count 0 2006.253.07:51:58.56#ibcon#flushed, iclass 40, count 0 2006.253.07:51:58.56#ibcon#about to write, iclass 40, count 0 2006.253.07:51:58.56#ibcon#wrote, iclass 40, count 0 2006.253.07:51:58.56#ibcon#about to read 3, iclass 40, count 0 2006.253.07:51:58.57#ibcon#read 3, iclass 40, count 0 2006.253.07:51:58.57#ibcon#about to read 4, iclass 40, count 0 2006.253.07:51:58.57#ibcon#read 4, iclass 40, count 0 2006.253.07:51:58.57#ibcon#about to read 5, iclass 40, count 0 2006.253.07:51:58.57#ibcon#read 5, iclass 40, count 0 2006.253.07:51:58.57#ibcon#about to read 6, iclass 40, count 0 2006.253.07:51:58.57#ibcon#read 6, iclass 40, count 0 2006.253.07:51:58.57#ibcon#end of sib2, iclass 40, count 0 2006.253.07:51:58.57#ibcon#*mode == 0, iclass 40, count 0 2006.253.07:51:58.57#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.253.07:51:58.57#ibcon#[25=USB\r\n] 2006.253.07:51:58.57#ibcon#*before write, iclass 40, count 0 2006.253.07:51:58.57#ibcon#enter sib2, iclass 40, count 0 2006.253.07:51:58.57#ibcon#flushed, iclass 40, count 0 2006.253.07:51:58.57#ibcon#about to write, iclass 40, count 0 2006.253.07:51:58.57#ibcon#wrote, iclass 40, count 0 2006.253.07:51:58.57#ibcon#about to read 3, iclass 40, count 0 2006.253.07:51:58.60#ibcon#read 3, iclass 40, count 0 2006.253.07:51:58.60#ibcon#about to read 4, iclass 40, count 0 2006.253.07:51:58.60#ibcon#read 4, iclass 40, count 0 2006.253.07:51:58.60#ibcon#about to read 5, iclass 40, count 0 2006.253.07:51:58.60#ibcon#read 5, iclass 40, count 0 2006.253.07:51:58.60#ibcon#about to read 6, iclass 40, count 0 2006.253.07:51:58.60#ibcon#read 6, iclass 40, count 0 2006.253.07:51:58.60#ibcon#end of sib2, iclass 40, count 0 2006.253.07:51:58.60#ibcon#*after write, iclass 40, count 0 2006.253.07:51:58.60#ibcon#*before return 0, iclass 40, count 0 2006.253.07:51:58.60#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.253.07:51:58.60#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.253.07:51:58.60#ibcon#about to clear, iclass 40 cls_cnt 0 2006.253.07:51:58.60#ibcon#cleared, iclass 40 cls_cnt 0 2006.253.07:51:58.60$vc4f8/valo=3,672.99 2006.253.07:51:58.60#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.253.07:51:58.60#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.253.07:51:58.60#ibcon#ireg 17 cls_cnt 0 2006.253.07:51:58.60#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.253.07:51:58.60#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.253.07:51:58.60#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.253.07:51:58.60#ibcon#enter wrdev, iclass 4, count 0 2006.253.07:51:58.60#ibcon#first serial, iclass 4, count 0 2006.253.07:51:58.60#ibcon#enter sib2, iclass 4, count 0 2006.253.07:51:58.60#ibcon#flushed, iclass 4, count 0 2006.253.07:51:58.60#ibcon#about to write, iclass 4, count 0 2006.253.07:51:58.60#ibcon#wrote, iclass 4, count 0 2006.253.07:51:58.60#ibcon#about to read 3, iclass 4, count 0 2006.253.07:51:58.63#ibcon#read 3, iclass 4, count 0 2006.253.07:51:58.63#ibcon#about to read 4, iclass 4, count 0 2006.253.07:51:58.63#ibcon#read 4, iclass 4, count 0 2006.253.07:51:58.63#ibcon#about to read 5, iclass 4, count 0 2006.253.07:51:58.63#ibcon#read 5, iclass 4, count 0 2006.253.07:51:58.63#ibcon#about to read 6, iclass 4, count 0 2006.253.07:51:58.63#ibcon#read 6, iclass 4, count 0 2006.253.07:51:58.63#ibcon#end of sib2, iclass 4, count 0 2006.253.07:51:58.63#ibcon#*mode == 0, iclass 4, count 0 2006.253.07:51:58.63#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.253.07:51:58.63#ibcon#[26=FRQ=03,672.99\r\n] 2006.253.07:51:58.63#ibcon#*before write, iclass 4, count 0 2006.253.07:51:58.63#ibcon#enter sib2, iclass 4, count 0 2006.253.07:51:58.63#ibcon#flushed, iclass 4, count 0 2006.253.07:51:58.63#ibcon#about to write, iclass 4, count 0 2006.253.07:51:58.63#ibcon#wrote, iclass 4, count 0 2006.253.07:51:58.63#ibcon#about to read 3, iclass 4, count 0 2006.253.07:51:58.67#ibcon#read 3, iclass 4, count 0 2006.253.07:51:58.67#ibcon#about to read 4, iclass 4, count 0 2006.253.07:51:58.67#ibcon#read 4, iclass 4, count 0 2006.253.07:51:58.67#ibcon#about to read 5, iclass 4, count 0 2006.253.07:51:58.67#ibcon#read 5, iclass 4, count 0 2006.253.07:51:58.67#ibcon#about to read 6, iclass 4, count 0 2006.253.07:51:58.67#ibcon#read 6, iclass 4, count 0 2006.253.07:51:58.67#ibcon#end of sib2, iclass 4, count 0 2006.253.07:51:58.67#ibcon#*after write, iclass 4, count 0 2006.253.07:51:58.67#ibcon#*before return 0, iclass 4, count 0 2006.253.07:51:58.67#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.253.07:51:58.67#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.253.07:51:58.67#ibcon#about to clear, iclass 4 cls_cnt 0 2006.253.07:51:58.67#ibcon#cleared, iclass 4 cls_cnt 0 2006.253.07:51:58.67$vc4f8/va=3,6 2006.253.07:51:58.67#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.253.07:51:58.67#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.253.07:51:58.67#ibcon#ireg 11 cls_cnt 2 2006.253.07:51:58.67#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.253.07:51:58.72#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.253.07:51:58.72#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.253.07:51:58.72#ibcon#enter wrdev, iclass 6, count 2 2006.253.07:51:58.72#ibcon#first serial, iclass 6, count 2 2006.253.07:51:58.72#ibcon#enter sib2, iclass 6, count 2 2006.253.07:51:58.72#ibcon#flushed, iclass 6, count 2 2006.253.07:51:58.73#ibcon#about to write, iclass 6, count 2 2006.253.07:51:58.73#ibcon#wrote, iclass 6, count 2 2006.253.07:51:58.73#ibcon#about to read 3, iclass 6, count 2 2006.253.07:51:58.74#ibcon#read 3, iclass 6, count 2 2006.253.07:51:58.74#ibcon#about to read 4, iclass 6, count 2 2006.253.07:51:58.74#ibcon#read 4, iclass 6, count 2 2006.253.07:51:58.74#ibcon#about to read 5, iclass 6, count 2 2006.253.07:51:58.74#ibcon#read 5, iclass 6, count 2 2006.253.07:51:58.74#ibcon#about to read 6, iclass 6, count 2 2006.253.07:51:58.74#ibcon#read 6, iclass 6, count 2 2006.253.07:51:58.74#ibcon#end of sib2, iclass 6, count 2 2006.253.07:51:58.74#ibcon#*mode == 0, iclass 6, count 2 2006.253.07:51:58.74#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.253.07:51:58.74#ibcon#[25=AT03-06\r\n] 2006.253.07:51:58.74#ibcon#*before write, iclass 6, count 2 2006.253.07:51:58.74#ibcon#enter sib2, iclass 6, count 2 2006.253.07:51:58.74#ibcon#flushed, iclass 6, count 2 2006.253.07:51:58.74#ibcon#about to write, iclass 6, count 2 2006.253.07:51:58.74#ibcon#wrote, iclass 6, count 2 2006.253.07:51:58.74#ibcon#about to read 3, iclass 6, count 2 2006.253.07:51:58.77#ibcon#read 3, iclass 6, count 2 2006.253.07:51:58.77#ibcon#about to read 4, iclass 6, count 2 2006.253.07:51:58.77#ibcon#read 4, iclass 6, count 2 2006.253.07:51:58.77#ibcon#about to read 5, iclass 6, count 2 2006.253.07:51:58.77#ibcon#read 5, iclass 6, count 2 2006.253.07:51:58.77#ibcon#about to read 6, iclass 6, count 2 2006.253.07:51:58.77#ibcon#read 6, iclass 6, count 2 2006.253.07:51:58.77#ibcon#end of sib2, iclass 6, count 2 2006.253.07:51:58.77#ibcon#*after write, iclass 6, count 2 2006.253.07:51:58.77#ibcon#*before return 0, iclass 6, count 2 2006.253.07:51:58.77#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.253.07:51:58.77#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.253.07:51:58.77#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.253.07:51:58.77#ibcon#ireg 7 cls_cnt 0 2006.253.07:51:58.77#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.253.07:51:58.89#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.253.07:51:58.89#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.253.07:51:58.89#ibcon#enter wrdev, iclass 6, count 0 2006.253.07:51:58.89#ibcon#first serial, iclass 6, count 0 2006.253.07:51:58.89#ibcon#enter sib2, iclass 6, count 0 2006.253.07:51:58.89#ibcon#flushed, iclass 6, count 0 2006.253.07:51:58.89#ibcon#about to write, iclass 6, count 0 2006.253.07:51:58.89#ibcon#wrote, iclass 6, count 0 2006.253.07:51:58.89#ibcon#about to read 3, iclass 6, count 0 2006.253.07:51:58.91#ibcon#read 3, iclass 6, count 0 2006.253.07:51:58.91#ibcon#about to read 4, iclass 6, count 0 2006.253.07:51:58.91#ibcon#read 4, iclass 6, count 0 2006.253.07:51:58.91#ibcon#about to read 5, iclass 6, count 0 2006.253.07:51:58.91#ibcon#read 5, iclass 6, count 0 2006.253.07:51:58.91#ibcon#about to read 6, iclass 6, count 0 2006.253.07:51:58.91#ibcon#read 6, iclass 6, count 0 2006.253.07:51:58.91#ibcon#end of sib2, iclass 6, count 0 2006.253.07:51:58.91#ibcon#*mode == 0, iclass 6, count 0 2006.253.07:51:58.91#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.253.07:51:58.91#ibcon#[25=USB\r\n] 2006.253.07:51:58.91#ibcon#*before write, iclass 6, count 0 2006.253.07:51:58.91#ibcon#enter sib2, iclass 6, count 0 2006.253.07:51:58.91#ibcon#flushed, iclass 6, count 0 2006.253.07:51:58.91#ibcon#about to write, iclass 6, count 0 2006.253.07:51:58.91#ibcon#wrote, iclass 6, count 0 2006.253.07:51:58.91#ibcon#about to read 3, iclass 6, count 0 2006.253.07:51:58.94#ibcon#read 3, iclass 6, count 0 2006.253.07:51:58.94#ibcon#about to read 4, iclass 6, count 0 2006.253.07:51:58.94#ibcon#read 4, iclass 6, count 0 2006.253.07:51:58.94#ibcon#about to read 5, iclass 6, count 0 2006.253.07:51:58.94#ibcon#read 5, iclass 6, count 0 2006.253.07:51:58.94#ibcon#about to read 6, iclass 6, count 0 2006.253.07:51:58.94#ibcon#read 6, iclass 6, count 0 2006.253.07:51:58.94#ibcon#end of sib2, iclass 6, count 0 2006.253.07:51:58.94#ibcon#*after write, iclass 6, count 0 2006.253.07:51:58.94#ibcon#*before return 0, iclass 6, count 0 2006.253.07:51:58.94#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.253.07:51:58.94#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.253.07:51:58.94#ibcon#about to clear, iclass 6 cls_cnt 0 2006.253.07:51:58.94#ibcon#cleared, iclass 6 cls_cnt 0 2006.253.07:51:58.94$vc4f8/valo=4,832.99 2006.253.07:51:58.94#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.253.07:51:58.94#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.253.07:51:58.94#ibcon#ireg 17 cls_cnt 0 2006.253.07:51:58.94#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.253.07:51:58.94#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.253.07:51:58.94#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.253.07:51:58.94#ibcon#enter wrdev, iclass 10, count 0 2006.253.07:51:58.94#ibcon#first serial, iclass 10, count 0 2006.253.07:51:58.94#ibcon#enter sib2, iclass 10, count 0 2006.253.07:51:58.94#ibcon#flushed, iclass 10, count 0 2006.253.07:51:58.94#ibcon#about to write, iclass 10, count 0 2006.253.07:51:58.94#ibcon#wrote, iclass 10, count 0 2006.253.07:51:58.94#ibcon#about to read 3, iclass 10, count 0 2006.253.07:51:58.96#ibcon#read 3, iclass 10, count 0 2006.253.07:51:58.96#ibcon#about to read 4, iclass 10, count 0 2006.253.07:51:58.96#ibcon#read 4, iclass 10, count 0 2006.253.07:51:58.96#ibcon#about to read 5, iclass 10, count 0 2006.253.07:51:58.96#ibcon#read 5, iclass 10, count 0 2006.253.07:51:58.96#ibcon#about to read 6, iclass 10, count 0 2006.253.07:51:58.96#ibcon#read 6, iclass 10, count 0 2006.253.07:51:58.96#ibcon#end of sib2, iclass 10, count 0 2006.253.07:51:58.96#ibcon#*mode == 0, iclass 10, count 0 2006.253.07:51:58.96#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.253.07:51:58.96#ibcon#[26=FRQ=04,832.99\r\n] 2006.253.07:51:58.96#ibcon#*before write, iclass 10, count 0 2006.253.07:51:58.96#ibcon#enter sib2, iclass 10, count 0 2006.253.07:51:58.96#ibcon#flushed, iclass 10, count 0 2006.253.07:51:58.96#ibcon#about to write, iclass 10, count 0 2006.253.07:51:58.96#ibcon#wrote, iclass 10, count 0 2006.253.07:51:58.96#ibcon#about to read 3, iclass 10, count 0 2006.253.07:51:59.00#ibcon#read 3, iclass 10, count 0 2006.253.07:51:59.00#ibcon#about to read 4, iclass 10, count 0 2006.253.07:51:59.00#ibcon#read 4, iclass 10, count 0 2006.253.07:51:59.00#ibcon#about to read 5, iclass 10, count 0 2006.253.07:51:59.00#ibcon#read 5, iclass 10, count 0 2006.253.07:51:59.00#ibcon#about to read 6, iclass 10, count 0 2006.253.07:51:59.00#ibcon#read 6, iclass 10, count 0 2006.253.07:51:59.00#ibcon#end of sib2, iclass 10, count 0 2006.253.07:51:59.00#ibcon#*after write, iclass 10, count 0 2006.253.07:51:59.00#ibcon#*before return 0, iclass 10, count 0 2006.253.07:51:59.00#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.253.07:51:59.00#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.253.07:51:59.00#ibcon#about to clear, iclass 10 cls_cnt 0 2006.253.07:51:59.00#ibcon#cleared, iclass 10 cls_cnt 0 2006.253.07:51:59.00$vc4f8/va=4,7 2006.253.07:51:59.00#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.253.07:51:59.00#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.253.07:51:59.00#ibcon#ireg 11 cls_cnt 2 2006.253.07:51:59.00#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.253.07:51:59.06#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.253.07:51:59.06#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.253.07:51:59.06#ibcon#enter wrdev, iclass 12, count 2 2006.253.07:51:59.06#ibcon#first serial, iclass 12, count 2 2006.253.07:51:59.06#ibcon#enter sib2, iclass 12, count 2 2006.253.07:51:59.06#ibcon#flushed, iclass 12, count 2 2006.253.07:51:59.06#ibcon#about to write, iclass 12, count 2 2006.253.07:51:59.06#ibcon#wrote, iclass 12, count 2 2006.253.07:51:59.06#ibcon#about to read 3, iclass 12, count 2 2006.253.07:51:59.08#ibcon#read 3, iclass 12, count 2 2006.253.07:51:59.08#ibcon#about to read 4, iclass 12, count 2 2006.253.07:51:59.08#ibcon#read 4, iclass 12, count 2 2006.253.07:51:59.08#ibcon#about to read 5, iclass 12, count 2 2006.253.07:51:59.08#ibcon#read 5, iclass 12, count 2 2006.253.07:51:59.08#ibcon#about to read 6, iclass 12, count 2 2006.253.07:51:59.08#ibcon#read 6, iclass 12, count 2 2006.253.07:51:59.08#ibcon#end of sib2, iclass 12, count 2 2006.253.07:51:59.08#ibcon#*mode == 0, iclass 12, count 2 2006.253.07:51:59.08#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.253.07:51:59.08#ibcon#[25=AT04-07\r\n] 2006.253.07:51:59.08#ibcon#*before write, iclass 12, count 2 2006.253.07:51:59.08#ibcon#enter sib2, iclass 12, count 2 2006.253.07:51:59.08#ibcon#flushed, iclass 12, count 2 2006.253.07:51:59.08#ibcon#about to write, iclass 12, count 2 2006.253.07:51:59.08#ibcon#wrote, iclass 12, count 2 2006.253.07:51:59.08#ibcon#about to read 3, iclass 12, count 2 2006.253.07:51:59.11#ibcon#read 3, iclass 12, count 2 2006.253.07:51:59.11#ibcon#about to read 4, iclass 12, count 2 2006.253.07:51:59.11#ibcon#read 4, iclass 12, count 2 2006.253.07:51:59.11#ibcon#about to read 5, iclass 12, count 2 2006.253.07:51:59.11#ibcon#read 5, iclass 12, count 2 2006.253.07:51:59.11#ibcon#about to read 6, iclass 12, count 2 2006.253.07:51:59.11#ibcon#read 6, iclass 12, count 2 2006.253.07:51:59.11#ibcon#end of sib2, iclass 12, count 2 2006.253.07:51:59.11#ibcon#*after write, iclass 12, count 2 2006.253.07:51:59.11#ibcon#*before return 0, iclass 12, count 2 2006.253.07:51:59.11#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.253.07:51:59.11#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.253.07:51:59.11#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.253.07:51:59.11#ibcon#ireg 7 cls_cnt 0 2006.253.07:51:59.11#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.253.07:51:59.23#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.253.07:51:59.23#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.253.07:51:59.23#ibcon#enter wrdev, iclass 12, count 0 2006.253.07:51:59.23#ibcon#first serial, iclass 12, count 0 2006.253.07:51:59.23#ibcon#enter sib2, iclass 12, count 0 2006.253.07:51:59.23#ibcon#flushed, iclass 12, count 0 2006.253.07:51:59.23#ibcon#about to write, iclass 12, count 0 2006.253.07:51:59.23#ibcon#wrote, iclass 12, count 0 2006.253.07:51:59.23#ibcon#about to read 3, iclass 12, count 0 2006.253.07:51:59.25#ibcon#read 3, iclass 12, count 0 2006.253.07:51:59.25#ibcon#about to read 4, iclass 12, count 0 2006.253.07:51:59.25#ibcon#read 4, iclass 12, count 0 2006.253.07:51:59.25#ibcon#about to read 5, iclass 12, count 0 2006.253.07:51:59.25#ibcon#read 5, iclass 12, count 0 2006.253.07:51:59.25#ibcon#about to read 6, iclass 12, count 0 2006.253.07:51:59.25#ibcon#read 6, iclass 12, count 0 2006.253.07:51:59.25#ibcon#end of sib2, iclass 12, count 0 2006.253.07:51:59.25#ibcon#*mode == 0, iclass 12, count 0 2006.253.07:51:59.25#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.253.07:51:59.25#ibcon#[25=USB\r\n] 2006.253.07:51:59.25#ibcon#*before write, iclass 12, count 0 2006.253.07:51:59.25#ibcon#enter sib2, iclass 12, count 0 2006.253.07:51:59.25#ibcon#flushed, iclass 12, count 0 2006.253.07:51:59.25#ibcon#about to write, iclass 12, count 0 2006.253.07:51:59.25#ibcon#wrote, iclass 12, count 0 2006.253.07:51:59.25#ibcon#about to read 3, iclass 12, count 0 2006.253.07:51:59.28#ibcon#read 3, iclass 12, count 0 2006.253.07:51:59.28#ibcon#about to read 4, iclass 12, count 0 2006.253.07:51:59.28#ibcon#read 4, iclass 12, count 0 2006.253.07:51:59.28#ibcon#about to read 5, iclass 12, count 0 2006.253.07:51:59.28#ibcon#read 5, iclass 12, count 0 2006.253.07:51:59.28#ibcon#about to read 6, iclass 12, count 0 2006.253.07:51:59.28#ibcon#read 6, iclass 12, count 0 2006.253.07:51:59.28#ibcon#end of sib2, iclass 12, count 0 2006.253.07:51:59.28#ibcon#*after write, iclass 12, count 0 2006.253.07:51:59.28#ibcon#*before return 0, iclass 12, count 0 2006.253.07:51:59.28#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.253.07:51:59.28#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.253.07:51:59.28#ibcon#about to clear, iclass 12 cls_cnt 0 2006.253.07:51:59.28#ibcon#cleared, iclass 12 cls_cnt 0 2006.253.07:51:59.28$vc4f8/valo=5,652.99 2006.253.07:51:59.28#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.253.07:51:59.28#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.253.07:51:59.28#ibcon#ireg 17 cls_cnt 0 2006.253.07:51:59.28#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.253.07:51:59.28#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.253.07:51:59.28#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.253.07:51:59.28#ibcon#enter wrdev, iclass 14, count 0 2006.253.07:51:59.28#ibcon#first serial, iclass 14, count 0 2006.253.07:51:59.28#ibcon#enter sib2, iclass 14, count 0 2006.253.07:51:59.28#ibcon#flushed, iclass 14, count 0 2006.253.07:51:59.28#ibcon#about to write, iclass 14, count 0 2006.253.07:51:59.28#ibcon#wrote, iclass 14, count 0 2006.253.07:51:59.28#ibcon#about to read 3, iclass 14, count 0 2006.253.07:51:59.30#ibcon#read 3, iclass 14, count 0 2006.253.07:51:59.30#ibcon#about to read 4, iclass 14, count 0 2006.253.07:51:59.30#ibcon#read 4, iclass 14, count 0 2006.253.07:51:59.30#ibcon#about to read 5, iclass 14, count 0 2006.253.07:51:59.30#ibcon#read 5, iclass 14, count 0 2006.253.07:51:59.30#ibcon#about to read 6, iclass 14, count 0 2006.253.07:51:59.30#ibcon#read 6, iclass 14, count 0 2006.253.07:51:59.30#ibcon#end of sib2, iclass 14, count 0 2006.253.07:51:59.30#ibcon#*mode == 0, iclass 14, count 0 2006.253.07:51:59.30#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.253.07:51:59.30#ibcon#[26=FRQ=05,652.99\r\n] 2006.253.07:51:59.30#ibcon#*before write, iclass 14, count 0 2006.253.07:51:59.30#ibcon#enter sib2, iclass 14, count 0 2006.253.07:51:59.30#ibcon#flushed, iclass 14, count 0 2006.253.07:51:59.30#ibcon#about to write, iclass 14, count 0 2006.253.07:51:59.30#ibcon#wrote, iclass 14, count 0 2006.253.07:51:59.30#ibcon#about to read 3, iclass 14, count 0 2006.253.07:51:59.34#ibcon#read 3, iclass 14, count 0 2006.253.07:51:59.34#ibcon#about to read 4, iclass 14, count 0 2006.253.07:51:59.34#ibcon#read 4, iclass 14, count 0 2006.253.07:51:59.34#ibcon#about to read 5, iclass 14, count 0 2006.253.07:51:59.34#ibcon#read 5, iclass 14, count 0 2006.253.07:51:59.34#ibcon#about to read 6, iclass 14, count 0 2006.253.07:51:59.34#ibcon#read 6, iclass 14, count 0 2006.253.07:51:59.34#ibcon#end of sib2, iclass 14, count 0 2006.253.07:51:59.34#ibcon#*after write, iclass 14, count 0 2006.253.07:51:59.34#ibcon#*before return 0, iclass 14, count 0 2006.253.07:51:59.34#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.253.07:51:59.34#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.253.07:51:59.34#ibcon#about to clear, iclass 14 cls_cnt 0 2006.253.07:51:59.34#ibcon#cleared, iclass 14 cls_cnt 0 2006.253.07:51:59.34$vc4f8/va=5,7 2006.253.07:51:59.34#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.253.07:51:59.34#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.253.07:51:59.34#ibcon#ireg 11 cls_cnt 2 2006.253.07:51:59.34#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.253.07:51:59.40#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.253.07:51:59.40#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.253.07:51:59.40#ibcon#enter wrdev, iclass 16, count 2 2006.253.07:51:59.40#ibcon#first serial, iclass 16, count 2 2006.253.07:51:59.40#ibcon#enter sib2, iclass 16, count 2 2006.253.07:51:59.40#ibcon#flushed, iclass 16, count 2 2006.253.07:51:59.40#ibcon#about to write, iclass 16, count 2 2006.253.07:51:59.41#ibcon#wrote, iclass 16, count 2 2006.253.07:51:59.41#ibcon#about to read 3, iclass 16, count 2 2006.253.07:51:59.42#ibcon#read 3, iclass 16, count 2 2006.253.07:51:59.42#ibcon#about to read 4, iclass 16, count 2 2006.253.07:51:59.42#ibcon#read 4, iclass 16, count 2 2006.253.07:51:59.42#ibcon#about to read 5, iclass 16, count 2 2006.253.07:51:59.42#ibcon#read 5, iclass 16, count 2 2006.253.07:51:59.42#ibcon#about to read 6, iclass 16, count 2 2006.253.07:51:59.42#ibcon#read 6, iclass 16, count 2 2006.253.07:51:59.42#ibcon#end of sib2, iclass 16, count 2 2006.253.07:51:59.42#ibcon#*mode == 0, iclass 16, count 2 2006.253.07:51:59.42#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.253.07:51:59.42#ibcon#[25=AT05-07\r\n] 2006.253.07:51:59.42#ibcon#*before write, iclass 16, count 2 2006.253.07:51:59.42#ibcon#enter sib2, iclass 16, count 2 2006.253.07:51:59.42#ibcon#flushed, iclass 16, count 2 2006.253.07:51:59.42#ibcon#about to write, iclass 16, count 2 2006.253.07:51:59.42#ibcon#wrote, iclass 16, count 2 2006.253.07:51:59.42#ibcon#about to read 3, iclass 16, count 2 2006.253.07:51:59.45#ibcon#read 3, iclass 16, count 2 2006.253.07:51:59.45#ibcon#about to read 4, iclass 16, count 2 2006.253.07:51:59.45#ibcon#read 4, iclass 16, count 2 2006.253.07:51:59.45#ibcon#about to read 5, iclass 16, count 2 2006.253.07:51:59.45#ibcon#read 5, iclass 16, count 2 2006.253.07:51:59.45#ibcon#about to read 6, iclass 16, count 2 2006.253.07:51:59.45#ibcon#read 6, iclass 16, count 2 2006.253.07:51:59.45#ibcon#end of sib2, iclass 16, count 2 2006.253.07:51:59.45#ibcon#*after write, iclass 16, count 2 2006.253.07:51:59.45#ibcon#*before return 0, iclass 16, count 2 2006.253.07:51:59.45#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.253.07:51:59.45#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.253.07:51:59.45#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.253.07:51:59.45#ibcon#ireg 7 cls_cnt 0 2006.253.07:51:59.45#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.253.07:51:59.57#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.253.07:51:59.57#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.253.07:51:59.57#ibcon#enter wrdev, iclass 16, count 0 2006.253.07:51:59.57#ibcon#first serial, iclass 16, count 0 2006.253.07:51:59.57#ibcon#enter sib2, iclass 16, count 0 2006.253.07:51:59.57#ibcon#flushed, iclass 16, count 0 2006.253.07:51:59.57#ibcon#about to write, iclass 16, count 0 2006.253.07:51:59.57#ibcon#wrote, iclass 16, count 0 2006.253.07:51:59.57#ibcon#about to read 3, iclass 16, count 0 2006.253.07:51:59.59#ibcon#read 3, iclass 16, count 0 2006.253.07:51:59.59#ibcon#about to read 4, iclass 16, count 0 2006.253.07:51:59.59#ibcon#read 4, iclass 16, count 0 2006.253.07:51:59.59#ibcon#about to read 5, iclass 16, count 0 2006.253.07:51:59.59#ibcon#read 5, iclass 16, count 0 2006.253.07:51:59.59#ibcon#about to read 6, iclass 16, count 0 2006.253.07:51:59.59#ibcon#read 6, iclass 16, count 0 2006.253.07:51:59.59#ibcon#end of sib2, iclass 16, count 0 2006.253.07:51:59.59#ibcon#*mode == 0, iclass 16, count 0 2006.253.07:51:59.59#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.253.07:51:59.59#ibcon#[25=USB\r\n] 2006.253.07:51:59.59#ibcon#*before write, iclass 16, count 0 2006.253.07:51:59.59#ibcon#enter sib2, iclass 16, count 0 2006.253.07:51:59.59#ibcon#flushed, iclass 16, count 0 2006.253.07:51:59.59#ibcon#about to write, iclass 16, count 0 2006.253.07:51:59.59#ibcon#wrote, iclass 16, count 0 2006.253.07:51:59.59#ibcon#about to read 3, iclass 16, count 0 2006.253.07:51:59.62#ibcon#read 3, iclass 16, count 0 2006.253.07:51:59.62#ibcon#about to read 4, iclass 16, count 0 2006.253.07:51:59.62#ibcon#read 4, iclass 16, count 0 2006.253.07:51:59.62#ibcon#about to read 5, iclass 16, count 0 2006.253.07:51:59.62#ibcon#read 5, iclass 16, count 0 2006.253.07:51:59.62#ibcon#about to read 6, iclass 16, count 0 2006.253.07:51:59.62#ibcon#read 6, iclass 16, count 0 2006.253.07:51:59.62#ibcon#end of sib2, iclass 16, count 0 2006.253.07:51:59.62#ibcon#*after write, iclass 16, count 0 2006.253.07:51:59.62#ibcon#*before return 0, iclass 16, count 0 2006.253.07:51:59.62#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.253.07:51:59.62#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.253.07:51:59.62#ibcon#about to clear, iclass 16 cls_cnt 0 2006.253.07:51:59.62#ibcon#cleared, iclass 16 cls_cnt 0 2006.253.07:51:59.62$vc4f8/valo=6,772.99 2006.253.07:51:59.62#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.253.07:51:59.62#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.253.07:51:59.62#ibcon#ireg 17 cls_cnt 0 2006.253.07:51:59.62#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.253.07:51:59.62#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.253.07:51:59.62#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.253.07:51:59.62#ibcon#enter wrdev, iclass 18, count 0 2006.253.07:51:59.62#ibcon#first serial, iclass 18, count 0 2006.253.07:51:59.62#ibcon#enter sib2, iclass 18, count 0 2006.253.07:51:59.62#ibcon#flushed, iclass 18, count 0 2006.253.07:51:59.62#ibcon#about to write, iclass 18, count 0 2006.253.07:51:59.62#ibcon#wrote, iclass 18, count 0 2006.253.07:51:59.62#ibcon#about to read 3, iclass 18, count 0 2006.253.07:51:59.65#ibcon#read 3, iclass 18, count 0 2006.253.07:51:59.65#ibcon#about to read 4, iclass 18, count 0 2006.253.07:51:59.65#ibcon#read 4, iclass 18, count 0 2006.253.07:51:59.65#ibcon#about to read 5, iclass 18, count 0 2006.253.07:51:59.65#ibcon#read 5, iclass 18, count 0 2006.253.07:51:59.65#ibcon#about to read 6, iclass 18, count 0 2006.253.07:51:59.65#ibcon#read 6, iclass 18, count 0 2006.253.07:51:59.65#ibcon#end of sib2, iclass 18, count 0 2006.253.07:51:59.65#ibcon#*mode == 0, iclass 18, count 0 2006.253.07:51:59.65#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.253.07:51:59.65#ibcon#[26=FRQ=06,772.99\r\n] 2006.253.07:51:59.65#ibcon#*before write, iclass 18, count 0 2006.253.07:51:59.65#ibcon#enter sib2, iclass 18, count 0 2006.253.07:51:59.65#ibcon#flushed, iclass 18, count 0 2006.253.07:51:59.65#ibcon#about to write, iclass 18, count 0 2006.253.07:51:59.65#ibcon#wrote, iclass 18, count 0 2006.253.07:51:59.65#ibcon#about to read 3, iclass 18, count 0 2006.253.07:51:59.69#ibcon#read 3, iclass 18, count 0 2006.253.07:51:59.69#ibcon#about to read 4, iclass 18, count 0 2006.253.07:51:59.69#ibcon#read 4, iclass 18, count 0 2006.253.07:51:59.69#ibcon#about to read 5, iclass 18, count 0 2006.253.07:51:59.69#ibcon#read 5, iclass 18, count 0 2006.253.07:51:59.69#ibcon#about to read 6, iclass 18, count 0 2006.253.07:51:59.69#ibcon#read 6, iclass 18, count 0 2006.253.07:51:59.69#ibcon#end of sib2, iclass 18, count 0 2006.253.07:51:59.69#ibcon#*after write, iclass 18, count 0 2006.253.07:51:59.69#ibcon#*before return 0, iclass 18, count 0 2006.253.07:51:59.69#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.253.07:51:59.69#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.253.07:51:59.69#ibcon#about to clear, iclass 18 cls_cnt 0 2006.253.07:51:59.69#ibcon#cleared, iclass 18 cls_cnt 0 2006.253.07:51:59.69$vc4f8/va=6,7 2006.253.07:51:59.69#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.253.07:51:59.69#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.253.07:51:59.69#ibcon#ireg 11 cls_cnt 2 2006.253.07:51:59.69#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.253.07:51:59.74#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.253.07:51:59.74#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.253.07:51:59.74#ibcon#enter wrdev, iclass 20, count 2 2006.253.07:51:59.74#ibcon#first serial, iclass 20, count 2 2006.253.07:51:59.74#ibcon#enter sib2, iclass 20, count 2 2006.253.07:51:59.74#ibcon#flushed, iclass 20, count 2 2006.253.07:51:59.74#ibcon#about to write, iclass 20, count 2 2006.253.07:51:59.74#ibcon#wrote, iclass 20, count 2 2006.253.07:51:59.74#ibcon#about to read 3, iclass 20, count 2 2006.253.07:51:59.76#ibcon#read 3, iclass 20, count 2 2006.253.07:51:59.76#ibcon#about to read 4, iclass 20, count 2 2006.253.07:51:59.76#ibcon#read 4, iclass 20, count 2 2006.253.07:51:59.76#ibcon#about to read 5, iclass 20, count 2 2006.253.07:51:59.76#ibcon#read 5, iclass 20, count 2 2006.253.07:51:59.76#ibcon#about to read 6, iclass 20, count 2 2006.253.07:51:59.76#ibcon#read 6, iclass 20, count 2 2006.253.07:51:59.76#ibcon#end of sib2, iclass 20, count 2 2006.253.07:51:59.76#ibcon#*mode == 0, iclass 20, count 2 2006.253.07:51:59.76#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.253.07:51:59.76#ibcon#[25=AT06-07\r\n] 2006.253.07:51:59.76#ibcon#*before write, iclass 20, count 2 2006.253.07:51:59.76#ibcon#enter sib2, iclass 20, count 2 2006.253.07:51:59.76#ibcon#flushed, iclass 20, count 2 2006.253.07:51:59.76#ibcon#about to write, iclass 20, count 2 2006.253.07:51:59.76#ibcon#wrote, iclass 20, count 2 2006.253.07:51:59.76#ibcon#about to read 3, iclass 20, count 2 2006.253.07:51:59.79#ibcon#read 3, iclass 20, count 2 2006.253.07:51:59.79#ibcon#about to read 4, iclass 20, count 2 2006.253.07:51:59.79#ibcon#read 4, iclass 20, count 2 2006.253.07:51:59.79#ibcon#about to read 5, iclass 20, count 2 2006.253.07:51:59.79#ibcon#read 5, iclass 20, count 2 2006.253.07:51:59.79#ibcon#about to read 6, iclass 20, count 2 2006.253.07:51:59.79#ibcon#read 6, iclass 20, count 2 2006.253.07:51:59.79#ibcon#end of sib2, iclass 20, count 2 2006.253.07:51:59.79#ibcon#*after write, iclass 20, count 2 2006.253.07:51:59.79#ibcon#*before return 0, iclass 20, count 2 2006.253.07:51:59.79#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.253.07:51:59.79#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.253.07:51:59.79#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.253.07:51:59.79#ibcon#ireg 7 cls_cnt 0 2006.253.07:51:59.79#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.253.07:51:59.91#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.253.07:51:59.91#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.253.07:51:59.91#ibcon#enter wrdev, iclass 20, count 0 2006.253.07:51:59.91#ibcon#first serial, iclass 20, count 0 2006.253.07:51:59.91#ibcon#enter sib2, iclass 20, count 0 2006.253.07:51:59.91#ibcon#flushed, iclass 20, count 0 2006.253.07:51:59.91#ibcon#about to write, iclass 20, count 0 2006.253.07:51:59.91#ibcon#wrote, iclass 20, count 0 2006.253.07:51:59.91#ibcon#about to read 3, iclass 20, count 0 2006.253.07:51:59.93#ibcon#read 3, iclass 20, count 0 2006.253.07:51:59.93#ibcon#about to read 4, iclass 20, count 0 2006.253.07:51:59.93#ibcon#read 4, iclass 20, count 0 2006.253.07:51:59.93#ibcon#about to read 5, iclass 20, count 0 2006.253.07:51:59.93#ibcon#read 5, iclass 20, count 0 2006.253.07:51:59.93#ibcon#about to read 6, iclass 20, count 0 2006.253.07:51:59.93#ibcon#read 6, iclass 20, count 0 2006.253.07:51:59.93#ibcon#end of sib2, iclass 20, count 0 2006.253.07:51:59.93#ibcon#*mode == 0, iclass 20, count 0 2006.253.07:51:59.93#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.253.07:51:59.93#ibcon#[25=USB\r\n] 2006.253.07:51:59.93#ibcon#*before write, iclass 20, count 0 2006.253.07:51:59.93#ibcon#enter sib2, iclass 20, count 0 2006.253.07:51:59.93#ibcon#flushed, iclass 20, count 0 2006.253.07:51:59.93#ibcon#about to write, iclass 20, count 0 2006.253.07:51:59.93#ibcon#wrote, iclass 20, count 0 2006.253.07:51:59.93#ibcon#about to read 3, iclass 20, count 0 2006.253.07:51:59.96#ibcon#read 3, iclass 20, count 0 2006.253.07:51:59.96#ibcon#about to read 4, iclass 20, count 0 2006.253.07:51:59.96#ibcon#read 4, iclass 20, count 0 2006.253.07:51:59.96#ibcon#about to read 5, iclass 20, count 0 2006.253.07:51:59.96#ibcon#read 5, iclass 20, count 0 2006.253.07:51:59.96#ibcon#about to read 6, iclass 20, count 0 2006.253.07:51:59.96#ibcon#read 6, iclass 20, count 0 2006.253.07:51:59.96#ibcon#end of sib2, iclass 20, count 0 2006.253.07:51:59.96#ibcon#*after write, iclass 20, count 0 2006.253.07:51:59.96#ibcon#*before return 0, iclass 20, count 0 2006.253.07:51:59.96#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.253.07:51:59.96#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.253.07:51:59.96#ibcon#about to clear, iclass 20 cls_cnt 0 2006.253.07:51:59.96#ibcon#cleared, iclass 20 cls_cnt 0 2006.253.07:51:59.96$vc4f8/valo=7,832.99 2006.253.07:51:59.96#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.253.07:51:59.96#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.253.07:51:59.96#ibcon#ireg 17 cls_cnt 0 2006.253.07:51:59.96#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.253.07:51:59.96#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.253.07:51:59.96#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.253.07:51:59.96#ibcon#enter wrdev, iclass 22, count 0 2006.253.07:51:59.96#ibcon#first serial, iclass 22, count 0 2006.253.07:51:59.96#ibcon#enter sib2, iclass 22, count 0 2006.253.07:51:59.96#ibcon#flushed, iclass 22, count 0 2006.253.07:51:59.96#ibcon#about to write, iclass 22, count 0 2006.253.07:51:59.96#ibcon#wrote, iclass 22, count 0 2006.253.07:51:59.96#ibcon#about to read 3, iclass 22, count 0 2006.253.07:51:59.98#ibcon#read 3, iclass 22, count 0 2006.253.07:51:59.98#ibcon#about to read 4, iclass 22, count 0 2006.253.07:51:59.98#ibcon#read 4, iclass 22, count 0 2006.253.07:51:59.98#ibcon#about to read 5, iclass 22, count 0 2006.253.07:51:59.98#ibcon#read 5, iclass 22, count 0 2006.253.07:51:59.98#ibcon#about to read 6, iclass 22, count 0 2006.253.07:51:59.98#ibcon#read 6, iclass 22, count 0 2006.253.07:51:59.98#ibcon#end of sib2, iclass 22, count 0 2006.253.07:51:59.98#ibcon#*mode == 0, iclass 22, count 0 2006.253.07:51:59.98#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.253.07:51:59.98#ibcon#[26=FRQ=07,832.99\r\n] 2006.253.07:51:59.98#ibcon#*before write, iclass 22, count 0 2006.253.07:51:59.98#ibcon#enter sib2, iclass 22, count 0 2006.253.07:51:59.98#ibcon#flushed, iclass 22, count 0 2006.253.07:51:59.98#ibcon#about to write, iclass 22, count 0 2006.253.07:51:59.98#ibcon#wrote, iclass 22, count 0 2006.253.07:51:59.98#ibcon#about to read 3, iclass 22, count 0 2006.253.07:52:00.02#ibcon#read 3, iclass 22, count 0 2006.253.07:52:00.02#ibcon#about to read 4, iclass 22, count 0 2006.253.07:52:00.02#ibcon#read 4, iclass 22, count 0 2006.253.07:52:00.02#ibcon#about to read 5, iclass 22, count 0 2006.253.07:52:00.02#ibcon#read 5, iclass 22, count 0 2006.253.07:52:00.02#ibcon#about to read 6, iclass 22, count 0 2006.253.07:52:00.02#ibcon#read 6, iclass 22, count 0 2006.253.07:52:00.02#ibcon#end of sib2, iclass 22, count 0 2006.253.07:52:00.02#ibcon#*after write, iclass 22, count 0 2006.253.07:52:00.02#ibcon#*before return 0, iclass 22, count 0 2006.253.07:52:00.02#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.253.07:52:00.02#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.253.07:52:00.02#ibcon#about to clear, iclass 22 cls_cnt 0 2006.253.07:52:00.02#ibcon#cleared, iclass 22 cls_cnt 0 2006.253.07:52:00.02$vc4f8/va=7,7 2006.253.07:52:00.02#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.253.07:52:00.02#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.253.07:52:00.02#ibcon#ireg 11 cls_cnt 2 2006.253.07:52:00.02#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.253.07:52:00.09#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.253.07:52:00.09#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.253.07:52:00.09#ibcon#enter wrdev, iclass 24, count 2 2006.253.07:52:00.09#ibcon#first serial, iclass 24, count 2 2006.253.07:52:00.09#ibcon#enter sib2, iclass 24, count 2 2006.253.07:52:00.09#ibcon#flushed, iclass 24, count 2 2006.253.07:52:00.09#ibcon#about to write, iclass 24, count 2 2006.253.07:52:00.09#ibcon#wrote, iclass 24, count 2 2006.253.07:52:00.09#ibcon#about to read 3, iclass 24, count 2 2006.253.07:52:00.10#ibcon#read 3, iclass 24, count 2 2006.253.07:52:00.10#ibcon#about to read 4, iclass 24, count 2 2006.253.07:52:00.10#ibcon#read 4, iclass 24, count 2 2006.253.07:52:00.10#ibcon#about to read 5, iclass 24, count 2 2006.253.07:52:00.10#ibcon#read 5, iclass 24, count 2 2006.253.07:52:00.10#ibcon#about to read 6, iclass 24, count 2 2006.253.07:52:00.10#ibcon#read 6, iclass 24, count 2 2006.253.07:52:00.10#ibcon#end of sib2, iclass 24, count 2 2006.253.07:52:00.10#ibcon#*mode == 0, iclass 24, count 2 2006.253.07:52:00.10#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.253.07:52:00.10#ibcon#[25=AT07-07\r\n] 2006.253.07:52:00.10#ibcon#*before write, iclass 24, count 2 2006.253.07:52:00.10#ibcon#enter sib2, iclass 24, count 2 2006.253.07:52:00.10#ibcon#flushed, iclass 24, count 2 2006.253.07:52:00.10#ibcon#about to write, iclass 24, count 2 2006.253.07:52:00.10#ibcon#wrote, iclass 24, count 2 2006.253.07:52:00.10#ibcon#about to read 3, iclass 24, count 2 2006.253.07:52:00.13#ibcon#read 3, iclass 24, count 2 2006.253.07:52:00.13#ibcon#about to read 4, iclass 24, count 2 2006.253.07:52:00.13#ibcon#read 4, iclass 24, count 2 2006.253.07:52:00.13#ibcon#about to read 5, iclass 24, count 2 2006.253.07:52:00.13#ibcon#read 5, iclass 24, count 2 2006.253.07:52:00.13#ibcon#about to read 6, iclass 24, count 2 2006.253.07:52:00.13#ibcon#read 6, iclass 24, count 2 2006.253.07:52:00.13#ibcon#end of sib2, iclass 24, count 2 2006.253.07:52:00.13#ibcon#*after write, iclass 24, count 2 2006.253.07:52:00.13#ibcon#*before return 0, iclass 24, count 2 2006.253.07:52:00.13#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.253.07:52:00.13#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.253.07:52:00.13#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.253.07:52:00.13#ibcon#ireg 7 cls_cnt 0 2006.253.07:52:00.13#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.253.07:52:00.25#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.253.07:52:00.25#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.253.07:52:00.25#ibcon#enter wrdev, iclass 24, count 0 2006.253.07:52:00.25#ibcon#first serial, iclass 24, count 0 2006.253.07:52:00.25#ibcon#enter sib2, iclass 24, count 0 2006.253.07:52:00.25#ibcon#flushed, iclass 24, count 0 2006.253.07:52:00.25#ibcon#about to write, iclass 24, count 0 2006.253.07:52:00.25#ibcon#wrote, iclass 24, count 0 2006.253.07:52:00.25#ibcon#about to read 3, iclass 24, count 0 2006.253.07:52:00.27#ibcon#read 3, iclass 24, count 0 2006.253.07:52:00.27#ibcon#about to read 4, iclass 24, count 0 2006.253.07:52:00.27#ibcon#read 4, iclass 24, count 0 2006.253.07:52:00.27#ibcon#about to read 5, iclass 24, count 0 2006.253.07:52:00.27#ibcon#read 5, iclass 24, count 0 2006.253.07:52:00.27#ibcon#about to read 6, iclass 24, count 0 2006.253.07:52:00.27#ibcon#read 6, iclass 24, count 0 2006.253.07:52:00.27#ibcon#end of sib2, iclass 24, count 0 2006.253.07:52:00.27#ibcon#*mode == 0, iclass 24, count 0 2006.253.07:52:00.27#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.253.07:52:00.27#ibcon#[25=USB\r\n] 2006.253.07:52:00.27#ibcon#*before write, iclass 24, count 0 2006.253.07:52:00.27#ibcon#enter sib2, iclass 24, count 0 2006.253.07:52:00.27#ibcon#flushed, iclass 24, count 0 2006.253.07:52:00.27#ibcon#about to write, iclass 24, count 0 2006.253.07:52:00.27#ibcon#wrote, iclass 24, count 0 2006.253.07:52:00.27#ibcon#about to read 3, iclass 24, count 0 2006.253.07:52:00.30#ibcon#read 3, iclass 24, count 0 2006.253.07:52:00.30#ibcon#about to read 4, iclass 24, count 0 2006.253.07:52:00.30#ibcon#read 4, iclass 24, count 0 2006.253.07:52:00.30#ibcon#about to read 5, iclass 24, count 0 2006.253.07:52:00.30#ibcon#read 5, iclass 24, count 0 2006.253.07:52:00.30#ibcon#about to read 6, iclass 24, count 0 2006.253.07:52:00.30#ibcon#read 6, iclass 24, count 0 2006.253.07:52:00.30#ibcon#end of sib2, iclass 24, count 0 2006.253.07:52:00.30#ibcon#*after write, iclass 24, count 0 2006.253.07:52:00.30#ibcon#*before return 0, iclass 24, count 0 2006.253.07:52:00.30#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.253.07:52:00.30#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.253.07:52:00.30#ibcon#about to clear, iclass 24 cls_cnt 0 2006.253.07:52:00.30#ibcon#cleared, iclass 24 cls_cnt 0 2006.253.07:52:00.30$vc4f8/valo=8,852.99 2006.253.07:52:00.30#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.253.07:52:00.30#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.253.07:52:00.30#ibcon#ireg 17 cls_cnt 0 2006.253.07:52:00.30#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.253.07:52:00.30#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.253.07:52:00.30#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.253.07:52:00.30#ibcon#enter wrdev, iclass 26, count 0 2006.253.07:52:00.30#ibcon#first serial, iclass 26, count 0 2006.253.07:52:00.30#ibcon#enter sib2, iclass 26, count 0 2006.253.07:52:00.30#ibcon#flushed, iclass 26, count 0 2006.253.07:52:00.30#ibcon#about to write, iclass 26, count 0 2006.253.07:52:00.30#ibcon#wrote, iclass 26, count 0 2006.253.07:52:00.30#ibcon#about to read 3, iclass 26, count 0 2006.253.07:52:00.33#ibcon#read 3, iclass 26, count 0 2006.253.07:52:00.33#ibcon#about to read 4, iclass 26, count 0 2006.253.07:52:00.33#ibcon#read 4, iclass 26, count 0 2006.253.07:52:00.33#ibcon#about to read 5, iclass 26, count 0 2006.253.07:52:00.33#ibcon#read 5, iclass 26, count 0 2006.253.07:52:00.33#ibcon#about to read 6, iclass 26, count 0 2006.253.07:52:00.33#ibcon#read 6, iclass 26, count 0 2006.253.07:52:00.33#ibcon#end of sib2, iclass 26, count 0 2006.253.07:52:00.33#ibcon#*mode == 0, iclass 26, count 0 2006.253.07:52:00.33#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.253.07:52:00.33#ibcon#[26=FRQ=08,852.99\r\n] 2006.253.07:52:00.33#ibcon#*before write, iclass 26, count 0 2006.253.07:52:00.33#ibcon#enter sib2, iclass 26, count 0 2006.253.07:52:00.33#ibcon#flushed, iclass 26, count 0 2006.253.07:52:00.33#ibcon#about to write, iclass 26, count 0 2006.253.07:52:00.33#ibcon#wrote, iclass 26, count 0 2006.253.07:52:00.33#ibcon#about to read 3, iclass 26, count 0 2006.253.07:52:00.37#ibcon#read 3, iclass 26, count 0 2006.253.07:52:00.37#ibcon#about to read 4, iclass 26, count 0 2006.253.07:52:00.37#ibcon#read 4, iclass 26, count 0 2006.253.07:52:00.37#ibcon#about to read 5, iclass 26, count 0 2006.253.07:52:00.37#ibcon#read 5, iclass 26, count 0 2006.253.07:52:00.37#ibcon#about to read 6, iclass 26, count 0 2006.253.07:52:00.37#ibcon#read 6, iclass 26, count 0 2006.253.07:52:00.37#ibcon#end of sib2, iclass 26, count 0 2006.253.07:52:00.37#ibcon#*after write, iclass 26, count 0 2006.253.07:52:00.37#ibcon#*before return 0, iclass 26, count 0 2006.253.07:52:00.37#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.253.07:52:00.37#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.253.07:52:00.37#ibcon#about to clear, iclass 26 cls_cnt 0 2006.253.07:52:00.37#ibcon#cleared, iclass 26 cls_cnt 0 2006.253.07:52:00.37$vc4f8/va=8,7 2006.253.07:52:00.37#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.253.07:52:00.37#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.253.07:52:00.37#ibcon#ireg 11 cls_cnt 2 2006.253.07:52:00.37#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.253.07:52:00.42#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.253.07:52:00.42#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.253.07:52:00.42#ibcon#enter wrdev, iclass 28, count 2 2006.253.07:52:00.42#ibcon#first serial, iclass 28, count 2 2006.253.07:52:00.42#ibcon#enter sib2, iclass 28, count 2 2006.253.07:52:00.42#ibcon#flushed, iclass 28, count 2 2006.253.07:52:00.42#ibcon#about to write, iclass 28, count 2 2006.253.07:52:00.42#ibcon#wrote, iclass 28, count 2 2006.253.07:52:00.42#ibcon#about to read 3, iclass 28, count 2 2006.253.07:52:00.44#ibcon#read 3, iclass 28, count 2 2006.253.07:52:00.44#ibcon#about to read 4, iclass 28, count 2 2006.253.07:52:00.44#ibcon#read 4, iclass 28, count 2 2006.253.07:52:00.44#ibcon#about to read 5, iclass 28, count 2 2006.253.07:52:00.44#ibcon#read 5, iclass 28, count 2 2006.253.07:52:00.44#ibcon#about to read 6, iclass 28, count 2 2006.253.07:52:00.44#ibcon#read 6, iclass 28, count 2 2006.253.07:52:00.44#ibcon#end of sib2, iclass 28, count 2 2006.253.07:52:00.44#ibcon#*mode == 0, iclass 28, count 2 2006.253.07:52:00.44#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.253.07:52:00.44#ibcon#[25=AT08-07\r\n] 2006.253.07:52:00.44#ibcon#*before write, iclass 28, count 2 2006.253.07:52:00.44#ibcon#enter sib2, iclass 28, count 2 2006.253.07:52:00.44#ibcon#flushed, iclass 28, count 2 2006.253.07:52:00.44#ibcon#about to write, iclass 28, count 2 2006.253.07:52:00.44#ibcon#wrote, iclass 28, count 2 2006.253.07:52:00.44#ibcon#about to read 3, iclass 28, count 2 2006.253.07:52:00.47#ibcon#read 3, iclass 28, count 2 2006.253.07:52:00.47#ibcon#about to read 4, iclass 28, count 2 2006.253.07:52:00.47#ibcon#read 4, iclass 28, count 2 2006.253.07:52:00.47#ibcon#about to read 5, iclass 28, count 2 2006.253.07:52:00.47#ibcon#read 5, iclass 28, count 2 2006.253.07:52:00.47#ibcon#about to read 6, iclass 28, count 2 2006.253.07:52:00.47#ibcon#read 6, iclass 28, count 2 2006.253.07:52:00.47#ibcon#end of sib2, iclass 28, count 2 2006.253.07:52:00.47#ibcon#*after write, iclass 28, count 2 2006.253.07:52:00.47#ibcon#*before return 0, iclass 28, count 2 2006.253.07:52:00.47#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.253.07:52:00.47#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.253.07:52:00.47#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.253.07:52:00.47#ibcon#ireg 7 cls_cnt 0 2006.253.07:52:00.47#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.253.07:52:00.59#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.253.07:52:00.59#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.253.07:52:00.59#ibcon#enter wrdev, iclass 28, count 0 2006.253.07:52:00.59#ibcon#first serial, iclass 28, count 0 2006.253.07:52:00.59#ibcon#enter sib2, iclass 28, count 0 2006.253.07:52:00.59#ibcon#flushed, iclass 28, count 0 2006.253.07:52:00.59#ibcon#about to write, iclass 28, count 0 2006.253.07:52:00.59#ibcon#wrote, iclass 28, count 0 2006.253.07:52:00.59#ibcon#about to read 3, iclass 28, count 0 2006.253.07:52:00.61#ibcon#read 3, iclass 28, count 0 2006.253.07:52:00.61#ibcon#about to read 4, iclass 28, count 0 2006.253.07:52:00.61#ibcon#read 4, iclass 28, count 0 2006.253.07:52:00.61#ibcon#about to read 5, iclass 28, count 0 2006.253.07:52:00.61#ibcon#read 5, iclass 28, count 0 2006.253.07:52:00.61#ibcon#about to read 6, iclass 28, count 0 2006.253.07:52:00.61#ibcon#read 6, iclass 28, count 0 2006.253.07:52:00.61#ibcon#end of sib2, iclass 28, count 0 2006.253.07:52:00.61#ibcon#*mode == 0, iclass 28, count 0 2006.253.07:52:00.61#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.253.07:52:00.61#ibcon#[25=USB\r\n] 2006.253.07:52:00.61#ibcon#*before write, iclass 28, count 0 2006.253.07:52:00.61#ibcon#enter sib2, iclass 28, count 0 2006.253.07:52:00.61#ibcon#flushed, iclass 28, count 0 2006.253.07:52:00.61#ibcon#about to write, iclass 28, count 0 2006.253.07:52:00.61#ibcon#wrote, iclass 28, count 0 2006.253.07:52:00.61#ibcon#about to read 3, iclass 28, count 0 2006.253.07:52:00.64#ibcon#read 3, iclass 28, count 0 2006.253.07:52:00.64#ibcon#about to read 4, iclass 28, count 0 2006.253.07:52:00.64#ibcon#read 4, iclass 28, count 0 2006.253.07:52:00.64#ibcon#about to read 5, iclass 28, count 0 2006.253.07:52:00.64#ibcon#read 5, iclass 28, count 0 2006.253.07:52:00.64#ibcon#about to read 6, iclass 28, count 0 2006.253.07:52:00.64#ibcon#read 6, iclass 28, count 0 2006.253.07:52:00.64#ibcon#end of sib2, iclass 28, count 0 2006.253.07:52:00.64#ibcon#*after write, iclass 28, count 0 2006.253.07:52:00.64#ibcon#*before return 0, iclass 28, count 0 2006.253.07:52:00.64#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.253.07:52:00.64#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.253.07:52:00.64#ibcon#about to clear, iclass 28 cls_cnt 0 2006.253.07:52:00.64#ibcon#cleared, iclass 28 cls_cnt 0 2006.253.07:52:00.64$vc4f8/vblo=1,632.99 2006.253.07:52:00.64#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.253.07:52:00.64#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.253.07:52:00.64#ibcon#ireg 17 cls_cnt 0 2006.253.07:52:00.64#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.253.07:52:00.64#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.253.07:52:00.64#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.253.07:52:00.64#ibcon#enter wrdev, iclass 30, count 0 2006.253.07:52:00.64#ibcon#first serial, iclass 30, count 0 2006.253.07:52:00.64#ibcon#enter sib2, iclass 30, count 0 2006.253.07:52:00.64#ibcon#flushed, iclass 30, count 0 2006.253.07:52:00.64#ibcon#about to write, iclass 30, count 0 2006.253.07:52:00.64#ibcon#wrote, iclass 30, count 0 2006.253.07:52:00.64#ibcon#about to read 3, iclass 30, count 0 2006.253.07:52:00.66#ibcon#read 3, iclass 30, count 0 2006.253.07:52:00.66#ibcon#about to read 4, iclass 30, count 0 2006.253.07:52:00.66#ibcon#read 4, iclass 30, count 0 2006.253.07:52:00.66#ibcon#about to read 5, iclass 30, count 0 2006.253.07:52:00.66#ibcon#read 5, iclass 30, count 0 2006.253.07:52:00.66#ibcon#about to read 6, iclass 30, count 0 2006.253.07:52:00.66#ibcon#read 6, iclass 30, count 0 2006.253.07:52:00.66#ibcon#end of sib2, iclass 30, count 0 2006.253.07:52:00.66#ibcon#*mode == 0, iclass 30, count 0 2006.253.07:52:00.66#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.253.07:52:00.66#ibcon#[28=FRQ=01,632.99\r\n] 2006.253.07:52:00.66#ibcon#*before write, iclass 30, count 0 2006.253.07:52:00.66#ibcon#enter sib2, iclass 30, count 0 2006.253.07:52:00.66#ibcon#flushed, iclass 30, count 0 2006.253.07:52:00.66#ibcon#about to write, iclass 30, count 0 2006.253.07:52:00.66#ibcon#wrote, iclass 30, count 0 2006.253.07:52:00.66#ibcon#about to read 3, iclass 30, count 0 2006.253.07:52:00.70#ibcon#read 3, iclass 30, count 0 2006.253.07:52:00.70#ibcon#about to read 4, iclass 30, count 0 2006.253.07:52:00.70#ibcon#read 4, iclass 30, count 0 2006.253.07:52:00.70#ibcon#about to read 5, iclass 30, count 0 2006.253.07:52:00.70#ibcon#read 5, iclass 30, count 0 2006.253.07:52:00.70#ibcon#about to read 6, iclass 30, count 0 2006.253.07:52:00.70#ibcon#read 6, iclass 30, count 0 2006.253.07:52:00.70#ibcon#end of sib2, iclass 30, count 0 2006.253.07:52:00.70#ibcon#*after write, iclass 30, count 0 2006.253.07:52:00.70#ibcon#*before return 0, iclass 30, count 0 2006.253.07:52:00.70#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.253.07:52:00.70#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.253.07:52:00.70#ibcon#about to clear, iclass 30 cls_cnt 0 2006.253.07:52:00.70#ibcon#cleared, iclass 30 cls_cnt 0 2006.253.07:52:00.70$vc4f8/vb=1,4 2006.253.07:52:00.70#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.253.07:52:00.70#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.253.07:52:00.70#ibcon#ireg 11 cls_cnt 2 2006.253.07:52:00.70#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.253.07:52:00.70#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.253.07:52:00.70#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.253.07:52:00.70#ibcon#enter wrdev, iclass 32, count 2 2006.253.07:52:00.70#ibcon#first serial, iclass 32, count 2 2006.253.07:52:00.70#ibcon#enter sib2, iclass 32, count 2 2006.253.07:52:00.70#ibcon#flushed, iclass 32, count 2 2006.253.07:52:00.70#ibcon#about to write, iclass 32, count 2 2006.253.07:52:00.70#ibcon#wrote, iclass 32, count 2 2006.253.07:52:00.70#ibcon#about to read 3, iclass 32, count 2 2006.253.07:52:00.72#ibcon#read 3, iclass 32, count 2 2006.253.07:52:00.72#ibcon#about to read 4, iclass 32, count 2 2006.253.07:52:00.72#ibcon#read 4, iclass 32, count 2 2006.253.07:52:00.72#ibcon#about to read 5, iclass 32, count 2 2006.253.07:52:00.72#ibcon#read 5, iclass 32, count 2 2006.253.07:52:00.72#ibcon#about to read 6, iclass 32, count 2 2006.253.07:52:00.72#ibcon#read 6, iclass 32, count 2 2006.253.07:52:00.72#ibcon#end of sib2, iclass 32, count 2 2006.253.07:52:00.72#ibcon#*mode == 0, iclass 32, count 2 2006.253.07:52:00.72#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.253.07:52:00.72#ibcon#[27=AT01-04\r\n] 2006.253.07:52:00.72#ibcon#*before write, iclass 32, count 2 2006.253.07:52:00.72#ibcon#enter sib2, iclass 32, count 2 2006.253.07:52:00.72#ibcon#flushed, iclass 32, count 2 2006.253.07:52:00.72#ibcon#about to write, iclass 32, count 2 2006.253.07:52:00.72#ibcon#wrote, iclass 32, count 2 2006.253.07:52:00.72#ibcon#about to read 3, iclass 32, count 2 2006.253.07:52:00.75#ibcon#read 3, iclass 32, count 2 2006.253.07:52:00.75#ibcon#about to read 4, iclass 32, count 2 2006.253.07:52:00.75#ibcon#read 4, iclass 32, count 2 2006.253.07:52:00.75#ibcon#about to read 5, iclass 32, count 2 2006.253.07:52:00.75#ibcon#read 5, iclass 32, count 2 2006.253.07:52:00.75#ibcon#about to read 6, iclass 32, count 2 2006.253.07:52:00.75#ibcon#read 6, iclass 32, count 2 2006.253.07:52:00.75#ibcon#end of sib2, iclass 32, count 2 2006.253.07:52:00.75#ibcon#*after write, iclass 32, count 2 2006.253.07:52:00.75#ibcon#*before return 0, iclass 32, count 2 2006.253.07:52:00.75#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.253.07:52:00.75#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.253.07:52:00.75#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.253.07:52:00.75#ibcon#ireg 7 cls_cnt 0 2006.253.07:52:00.75#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.253.07:52:00.88#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.253.07:52:00.88#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.253.07:52:00.88#ibcon#enter wrdev, iclass 32, count 0 2006.253.07:52:00.88#ibcon#first serial, iclass 32, count 0 2006.253.07:52:00.88#ibcon#enter sib2, iclass 32, count 0 2006.253.07:52:00.88#ibcon#flushed, iclass 32, count 0 2006.253.07:52:00.88#ibcon#about to write, iclass 32, count 0 2006.253.07:52:00.88#ibcon#wrote, iclass 32, count 0 2006.253.07:52:00.88#ibcon#about to read 3, iclass 32, count 0 2006.253.07:52:00.89#ibcon#read 3, iclass 32, count 0 2006.253.07:52:00.89#ibcon#about to read 4, iclass 32, count 0 2006.253.07:52:00.89#ibcon#read 4, iclass 32, count 0 2006.253.07:52:00.89#ibcon#about to read 5, iclass 32, count 0 2006.253.07:52:00.89#ibcon#read 5, iclass 32, count 0 2006.253.07:52:00.89#ibcon#about to read 6, iclass 32, count 0 2006.253.07:52:00.89#ibcon#read 6, iclass 32, count 0 2006.253.07:52:00.89#ibcon#end of sib2, iclass 32, count 0 2006.253.07:52:00.89#ibcon#*mode == 0, iclass 32, count 0 2006.253.07:52:00.89#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.253.07:52:00.89#ibcon#[27=USB\r\n] 2006.253.07:52:00.89#ibcon#*before write, iclass 32, count 0 2006.253.07:52:00.89#ibcon#enter sib2, iclass 32, count 0 2006.253.07:52:00.89#ibcon#flushed, iclass 32, count 0 2006.253.07:52:00.89#ibcon#about to write, iclass 32, count 0 2006.253.07:52:00.89#ibcon#wrote, iclass 32, count 0 2006.253.07:52:00.89#ibcon#about to read 3, iclass 32, count 0 2006.253.07:52:00.92#ibcon#read 3, iclass 32, count 0 2006.253.07:52:00.92#ibcon#about to read 4, iclass 32, count 0 2006.253.07:52:00.92#ibcon#read 4, iclass 32, count 0 2006.253.07:52:00.92#ibcon#about to read 5, iclass 32, count 0 2006.253.07:52:00.92#ibcon#read 5, iclass 32, count 0 2006.253.07:52:00.92#ibcon#about to read 6, iclass 32, count 0 2006.253.07:52:00.92#ibcon#read 6, iclass 32, count 0 2006.253.07:52:00.92#ibcon#end of sib2, iclass 32, count 0 2006.253.07:52:00.92#ibcon#*after write, iclass 32, count 0 2006.253.07:52:00.92#ibcon#*before return 0, iclass 32, count 0 2006.253.07:52:00.92#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.253.07:52:00.92#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.253.07:52:00.92#ibcon#about to clear, iclass 32 cls_cnt 0 2006.253.07:52:00.92#ibcon#cleared, iclass 32 cls_cnt 0 2006.253.07:52:00.92$vc4f8/vblo=2,640.99 2006.253.07:52:00.92#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.253.07:52:00.92#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.253.07:52:00.92#ibcon#ireg 17 cls_cnt 0 2006.253.07:52:00.92#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.253.07:52:00.92#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.253.07:52:00.92#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.253.07:52:00.92#ibcon#enter wrdev, iclass 34, count 0 2006.253.07:52:00.92#ibcon#first serial, iclass 34, count 0 2006.253.07:52:00.92#ibcon#enter sib2, iclass 34, count 0 2006.253.07:52:00.92#ibcon#flushed, iclass 34, count 0 2006.253.07:52:00.92#ibcon#about to write, iclass 34, count 0 2006.253.07:52:00.92#ibcon#wrote, iclass 34, count 0 2006.253.07:52:00.92#ibcon#about to read 3, iclass 34, count 0 2006.253.07:52:00.95#ibcon#read 3, iclass 34, count 0 2006.253.07:52:00.95#ibcon#about to read 4, iclass 34, count 0 2006.253.07:52:00.95#ibcon#read 4, iclass 34, count 0 2006.253.07:52:00.95#ibcon#about to read 5, iclass 34, count 0 2006.253.07:52:00.95#ibcon#read 5, iclass 34, count 0 2006.253.07:52:00.95#ibcon#about to read 6, iclass 34, count 0 2006.253.07:52:00.95#ibcon#read 6, iclass 34, count 0 2006.253.07:52:00.95#ibcon#end of sib2, iclass 34, count 0 2006.253.07:52:00.95#ibcon#*mode == 0, iclass 34, count 0 2006.253.07:52:00.95#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.253.07:52:00.95#ibcon#[28=FRQ=02,640.99\r\n] 2006.253.07:52:00.95#ibcon#*before write, iclass 34, count 0 2006.253.07:52:00.95#ibcon#enter sib2, iclass 34, count 0 2006.253.07:52:00.95#ibcon#flushed, iclass 34, count 0 2006.253.07:52:00.95#ibcon#about to write, iclass 34, count 0 2006.253.07:52:00.95#ibcon#wrote, iclass 34, count 0 2006.253.07:52:00.95#ibcon#about to read 3, iclass 34, count 0 2006.253.07:52:00.99#ibcon#read 3, iclass 34, count 0 2006.253.07:52:00.99#ibcon#about to read 4, iclass 34, count 0 2006.253.07:52:00.99#ibcon#read 4, iclass 34, count 0 2006.253.07:52:00.99#ibcon#about to read 5, iclass 34, count 0 2006.253.07:52:00.99#ibcon#read 5, iclass 34, count 0 2006.253.07:52:00.99#ibcon#about to read 6, iclass 34, count 0 2006.253.07:52:00.99#ibcon#read 6, iclass 34, count 0 2006.253.07:52:00.99#ibcon#end of sib2, iclass 34, count 0 2006.253.07:52:00.99#ibcon#*after write, iclass 34, count 0 2006.253.07:52:00.99#ibcon#*before return 0, iclass 34, count 0 2006.253.07:52:00.99#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.253.07:52:00.99#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.253.07:52:00.99#ibcon#about to clear, iclass 34 cls_cnt 0 2006.253.07:52:00.99#ibcon#cleared, iclass 34 cls_cnt 0 2006.253.07:52:00.99$vc4f8/vb=2,5 2006.253.07:52:00.99#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.253.07:52:00.99#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.253.07:52:00.99#ibcon#ireg 11 cls_cnt 2 2006.253.07:52:00.99#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.253.07:52:01.05#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.253.07:52:01.05#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.253.07:52:01.05#ibcon#enter wrdev, iclass 36, count 2 2006.253.07:52:01.05#ibcon#first serial, iclass 36, count 2 2006.253.07:52:01.05#ibcon#enter sib2, iclass 36, count 2 2006.253.07:52:01.05#ibcon#flushed, iclass 36, count 2 2006.253.07:52:01.05#ibcon#about to write, iclass 36, count 2 2006.253.07:52:01.05#ibcon#wrote, iclass 36, count 2 2006.253.07:52:01.05#ibcon#about to read 3, iclass 36, count 2 2006.253.07:52:01.06#ibcon#read 3, iclass 36, count 2 2006.253.07:52:01.06#ibcon#about to read 4, iclass 36, count 2 2006.253.07:52:01.06#ibcon#read 4, iclass 36, count 2 2006.253.07:52:01.06#ibcon#about to read 5, iclass 36, count 2 2006.253.07:52:01.06#ibcon#read 5, iclass 36, count 2 2006.253.07:52:01.06#ibcon#about to read 6, iclass 36, count 2 2006.253.07:52:01.06#ibcon#read 6, iclass 36, count 2 2006.253.07:52:01.06#ibcon#end of sib2, iclass 36, count 2 2006.253.07:52:01.06#ibcon#*mode == 0, iclass 36, count 2 2006.253.07:52:01.06#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.253.07:52:01.06#ibcon#[27=AT02-05\r\n] 2006.253.07:52:01.06#ibcon#*before write, iclass 36, count 2 2006.253.07:52:01.06#ibcon#enter sib2, iclass 36, count 2 2006.253.07:52:01.06#ibcon#flushed, iclass 36, count 2 2006.253.07:52:01.06#ibcon#about to write, iclass 36, count 2 2006.253.07:52:01.06#ibcon#wrote, iclass 36, count 2 2006.253.07:52:01.06#ibcon#about to read 3, iclass 36, count 2 2006.253.07:52:01.09#ibcon#read 3, iclass 36, count 2 2006.253.07:52:01.09#ibcon#about to read 4, iclass 36, count 2 2006.253.07:52:01.09#ibcon#read 4, iclass 36, count 2 2006.253.07:52:01.09#ibcon#about to read 5, iclass 36, count 2 2006.253.07:52:01.09#ibcon#read 5, iclass 36, count 2 2006.253.07:52:01.09#ibcon#about to read 6, iclass 36, count 2 2006.253.07:52:01.09#ibcon#read 6, iclass 36, count 2 2006.253.07:52:01.09#ibcon#end of sib2, iclass 36, count 2 2006.253.07:52:01.09#ibcon#*after write, iclass 36, count 2 2006.253.07:52:01.09#ibcon#*before return 0, iclass 36, count 2 2006.253.07:52:01.09#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.253.07:52:01.09#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.253.07:52:01.09#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.253.07:52:01.09#ibcon#ireg 7 cls_cnt 0 2006.253.07:52:01.09#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.253.07:52:01.21#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.253.07:52:01.21#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.253.07:52:01.21#ibcon#enter wrdev, iclass 36, count 0 2006.253.07:52:01.21#ibcon#first serial, iclass 36, count 0 2006.253.07:52:01.21#ibcon#enter sib2, iclass 36, count 0 2006.253.07:52:01.21#ibcon#flushed, iclass 36, count 0 2006.253.07:52:01.21#ibcon#about to write, iclass 36, count 0 2006.253.07:52:01.21#ibcon#wrote, iclass 36, count 0 2006.253.07:52:01.21#ibcon#about to read 3, iclass 36, count 0 2006.253.07:52:01.23#ibcon#read 3, iclass 36, count 0 2006.253.07:52:01.23#ibcon#about to read 4, iclass 36, count 0 2006.253.07:52:01.23#ibcon#read 4, iclass 36, count 0 2006.253.07:52:01.23#ibcon#about to read 5, iclass 36, count 0 2006.253.07:52:01.23#ibcon#read 5, iclass 36, count 0 2006.253.07:52:01.23#ibcon#about to read 6, iclass 36, count 0 2006.253.07:52:01.23#ibcon#read 6, iclass 36, count 0 2006.253.07:52:01.23#ibcon#end of sib2, iclass 36, count 0 2006.253.07:52:01.23#ibcon#*mode == 0, iclass 36, count 0 2006.253.07:52:01.23#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.253.07:52:01.23#ibcon#[27=USB\r\n] 2006.253.07:52:01.23#ibcon#*before write, iclass 36, count 0 2006.253.07:52:01.23#ibcon#enter sib2, iclass 36, count 0 2006.253.07:52:01.23#ibcon#flushed, iclass 36, count 0 2006.253.07:52:01.23#ibcon#about to write, iclass 36, count 0 2006.253.07:52:01.23#ibcon#wrote, iclass 36, count 0 2006.253.07:52:01.23#ibcon#about to read 3, iclass 36, count 0 2006.253.07:52:01.26#ibcon#read 3, iclass 36, count 0 2006.253.07:52:01.26#ibcon#about to read 4, iclass 36, count 0 2006.253.07:52:01.26#ibcon#read 4, iclass 36, count 0 2006.253.07:52:01.26#ibcon#about to read 5, iclass 36, count 0 2006.253.07:52:01.26#ibcon#read 5, iclass 36, count 0 2006.253.07:52:01.26#ibcon#about to read 6, iclass 36, count 0 2006.253.07:52:01.26#ibcon#read 6, iclass 36, count 0 2006.253.07:52:01.26#ibcon#end of sib2, iclass 36, count 0 2006.253.07:52:01.26#ibcon#*after write, iclass 36, count 0 2006.253.07:52:01.26#ibcon#*before return 0, iclass 36, count 0 2006.253.07:52:01.26#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.253.07:52:01.26#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.253.07:52:01.26#ibcon#about to clear, iclass 36 cls_cnt 0 2006.253.07:52:01.26#ibcon#cleared, iclass 36 cls_cnt 0 2006.253.07:52:01.26$vc4f8/vblo=3,656.99 2006.253.07:52:01.26#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.253.07:52:01.26#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.253.07:52:01.26#ibcon#ireg 17 cls_cnt 0 2006.253.07:52:01.26#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.253.07:52:01.26#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.253.07:52:01.26#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.253.07:52:01.26#ibcon#enter wrdev, iclass 38, count 0 2006.253.07:52:01.26#ibcon#first serial, iclass 38, count 0 2006.253.07:52:01.26#ibcon#enter sib2, iclass 38, count 0 2006.253.07:52:01.26#ibcon#flushed, iclass 38, count 0 2006.253.07:52:01.26#ibcon#about to write, iclass 38, count 0 2006.253.07:52:01.26#ibcon#wrote, iclass 38, count 0 2006.253.07:52:01.26#ibcon#about to read 3, iclass 38, count 0 2006.253.07:52:01.28#ibcon#read 3, iclass 38, count 0 2006.253.07:52:01.28#ibcon#about to read 4, iclass 38, count 0 2006.253.07:52:01.28#ibcon#read 4, iclass 38, count 0 2006.253.07:52:01.28#ibcon#about to read 5, iclass 38, count 0 2006.253.07:52:01.28#ibcon#read 5, iclass 38, count 0 2006.253.07:52:01.28#ibcon#about to read 6, iclass 38, count 0 2006.253.07:52:01.28#ibcon#read 6, iclass 38, count 0 2006.253.07:52:01.28#ibcon#end of sib2, iclass 38, count 0 2006.253.07:52:01.28#ibcon#*mode == 0, iclass 38, count 0 2006.253.07:52:01.28#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.253.07:52:01.28#ibcon#[28=FRQ=03,656.99\r\n] 2006.253.07:52:01.28#ibcon#*before write, iclass 38, count 0 2006.253.07:52:01.28#ibcon#enter sib2, iclass 38, count 0 2006.253.07:52:01.28#ibcon#flushed, iclass 38, count 0 2006.253.07:52:01.28#ibcon#about to write, iclass 38, count 0 2006.253.07:52:01.28#ibcon#wrote, iclass 38, count 0 2006.253.07:52:01.28#ibcon#about to read 3, iclass 38, count 0 2006.253.07:52:01.32#ibcon#read 3, iclass 38, count 0 2006.253.07:52:01.32#ibcon#about to read 4, iclass 38, count 0 2006.253.07:52:01.32#ibcon#read 4, iclass 38, count 0 2006.253.07:52:01.32#ibcon#about to read 5, iclass 38, count 0 2006.253.07:52:01.32#ibcon#read 5, iclass 38, count 0 2006.253.07:52:01.32#ibcon#about to read 6, iclass 38, count 0 2006.253.07:52:01.32#ibcon#read 6, iclass 38, count 0 2006.253.07:52:01.32#ibcon#end of sib2, iclass 38, count 0 2006.253.07:52:01.32#ibcon#*after write, iclass 38, count 0 2006.253.07:52:01.32#ibcon#*before return 0, iclass 38, count 0 2006.253.07:52:01.32#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.253.07:52:01.32#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.253.07:52:01.32#ibcon#about to clear, iclass 38 cls_cnt 0 2006.253.07:52:01.32#ibcon#cleared, iclass 38 cls_cnt 0 2006.253.07:52:01.32$vc4f8/vb=3,4 2006.253.07:52:01.32#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.253.07:52:01.32#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.253.07:52:01.32#ibcon#ireg 11 cls_cnt 2 2006.253.07:52:01.32#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.253.07:52:01.38#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.253.07:52:01.38#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.253.07:52:01.38#ibcon#enter wrdev, iclass 40, count 2 2006.253.07:52:01.38#ibcon#first serial, iclass 40, count 2 2006.253.07:52:01.38#ibcon#enter sib2, iclass 40, count 2 2006.253.07:52:01.38#ibcon#flushed, iclass 40, count 2 2006.253.07:52:01.38#ibcon#about to write, iclass 40, count 2 2006.253.07:52:01.38#ibcon#wrote, iclass 40, count 2 2006.253.07:52:01.38#ibcon#about to read 3, iclass 40, count 2 2006.253.07:52:01.40#ibcon#read 3, iclass 40, count 2 2006.253.07:52:01.40#ibcon#about to read 4, iclass 40, count 2 2006.253.07:52:01.40#ibcon#read 4, iclass 40, count 2 2006.253.07:52:01.40#ibcon#about to read 5, iclass 40, count 2 2006.253.07:52:01.40#ibcon#read 5, iclass 40, count 2 2006.253.07:52:01.40#ibcon#about to read 6, iclass 40, count 2 2006.253.07:52:01.40#ibcon#read 6, iclass 40, count 2 2006.253.07:52:01.40#ibcon#end of sib2, iclass 40, count 2 2006.253.07:52:01.40#ibcon#*mode == 0, iclass 40, count 2 2006.253.07:52:01.40#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.253.07:52:01.40#ibcon#[27=AT03-04\r\n] 2006.253.07:52:01.40#ibcon#*before write, iclass 40, count 2 2006.253.07:52:01.40#ibcon#enter sib2, iclass 40, count 2 2006.253.07:52:01.40#ibcon#flushed, iclass 40, count 2 2006.253.07:52:01.40#ibcon#about to write, iclass 40, count 2 2006.253.07:52:01.40#ibcon#wrote, iclass 40, count 2 2006.253.07:52:01.40#ibcon#about to read 3, iclass 40, count 2 2006.253.07:52:01.43#ibcon#read 3, iclass 40, count 2 2006.253.07:52:01.43#ibcon#about to read 4, iclass 40, count 2 2006.253.07:52:01.43#ibcon#read 4, iclass 40, count 2 2006.253.07:52:01.43#ibcon#about to read 5, iclass 40, count 2 2006.253.07:52:01.43#ibcon#read 5, iclass 40, count 2 2006.253.07:52:01.43#ibcon#about to read 6, iclass 40, count 2 2006.253.07:52:01.43#ibcon#read 6, iclass 40, count 2 2006.253.07:52:01.43#ibcon#end of sib2, iclass 40, count 2 2006.253.07:52:01.43#ibcon#*after write, iclass 40, count 2 2006.253.07:52:01.43#ibcon#*before return 0, iclass 40, count 2 2006.253.07:52:01.43#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.253.07:52:01.43#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.253.07:52:01.43#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.253.07:52:01.43#ibcon#ireg 7 cls_cnt 0 2006.253.07:52:01.43#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.253.07:52:01.55#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.253.07:52:01.55#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.253.07:52:01.55#ibcon#enter wrdev, iclass 40, count 0 2006.253.07:52:01.55#ibcon#first serial, iclass 40, count 0 2006.253.07:52:01.55#ibcon#enter sib2, iclass 40, count 0 2006.253.07:52:01.55#ibcon#flushed, iclass 40, count 0 2006.253.07:52:01.55#ibcon#about to write, iclass 40, count 0 2006.253.07:52:01.55#ibcon#wrote, iclass 40, count 0 2006.253.07:52:01.55#ibcon#about to read 3, iclass 40, count 0 2006.253.07:52:01.57#ibcon#read 3, iclass 40, count 0 2006.253.07:52:01.57#ibcon#about to read 4, iclass 40, count 0 2006.253.07:52:01.57#ibcon#read 4, iclass 40, count 0 2006.253.07:52:01.57#ibcon#about to read 5, iclass 40, count 0 2006.253.07:52:01.57#ibcon#read 5, iclass 40, count 0 2006.253.07:52:01.57#ibcon#about to read 6, iclass 40, count 0 2006.253.07:52:01.57#ibcon#read 6, iclass 40, count 0 2006.253.07:52:01.57#ibcon#end of sib2, iclass 40, count 0 2006.253.07:52:01.57#ibcon#*mode == 0, iclass 40, count 0 2006.253.07:52:01.57#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.253.07:52:01.57#ibcon#[27=USB\r\n] 2006.253.07:52:01.57#ibcon#*before write, iclass 40, count 0 2006.253.07:52:01.57#ibcon#enter sib2, iclass 40, count 0 2006.253.07:52:01.57#ibcon#flushed, iclass 40, count 0 2006.253.07:52:01.57#ibcon#about to write, iclass 40, count 0 2006.253.07:52:01.57#ibcon#wrote, iclass 40, count 0 2006.253.07:52:01.57#ibcon#about to read 3, iclass 40, count 0 2006.253.07:52:01.60#ibcon#read 3, iclass 40, count 0 2006.253.07:52:01.60#ibcon#about to read 4, iclass 40, count 0 2006.253.07:52:01.60#ibcon#read 4, iclass 40, count 0 2006.253.07:52:01.60#ibcon#about to read 5, iclass 40, count 0 2006.253.07:52:01.60#ibcon#read 5, iclass 40, count 0 2006.253.07:52:01.60#ibcon#about to read 6, iclass 40, count 0 2006.253.07:52:01.60#ibcon#read 6, iclass 40, count 0 2006.253.07:52:01.60#ibcon#end of sib2, iclass 40, count 0 2006.253.07:52:01.60#ibcon#*after write, iclass 40, count 0 2006.253.07:52:01.60#ibcon#*before return 0, iclass 40, count 0 2006.253.07:52:01.60#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.253.07:52:01.60#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.253.07:52:01.60#ibcon#about to clear, iclass 40 cls_cnt 0 2006.253.07:52:01.60#ibcon#cleared, iclass 40 cls_cnt 0 2006.253.07:52:01.60$vc4f8/vblo=4,712.99 2006.253.07:52:01.60#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.253.07:52:01.60#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.253.07:52:01.60#ibcon#ireg 17 cls_cnt 0 2006.253.07:52:01.60#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.253.07:52:01.60#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.253.07:52:01.60#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.253.07:52:01.60#ibcon#enter wrdev, iclass 4, count 0 2006.253.07:52:01.60#ibcon#first serial, iclass 4, count 0 2006.253.07:52:01.60#ibcon#enter sib2, iclass 4, count 0 2006.253.07:52:01.60#ibcon#flushed, iclass 4, count 0 2006.253.07:52:01.60#ibcon#about to write, iclass 4, count 0 2006.253.07:52:01.60#ibcon#wrote, iclass 4, count 0 2006.253.07:52:01.60#ibcon#about to read 3, iclass 4, count 0 2006.253.07:52:01.63#ibcon#read 3, iclass 4, count 0 2006.253.07:52:01.63#ibcon#about to read 4, iclass 4, count 0 2006.253.07:52:01.63#ibcon#read 4, iclass 4, count 0 2006.253.07:52:01.63#ibcon#about to read 5, iclass 4, count 0 2006.253.07:52:01.63#ibcon#read 5, iclass 4, count 0 2006.253.07:52:01.63#ibcon#about to read 6, iclass 4, count 0 2006.253.07:52:01.63#ibcon#read 6, iclass 4, count 0 2006.253.07:52:01.63#ibcon#end of sib2, iclass 4, count 0 2006.253.07:52:01.63#ibcon#*mode == 0, iclass 4, count 0 2006.253.07:52:01.63#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.253.07:52:01.63#ibcon#[28=FRQ=04,712.99\r\n] 2006.253.07:52:01.63#ibcon#*before write, iclass 4, count 0 2006.253.07:52:01.63#ibcon#enter sib2, iclass 4, count 0 2006.253.07:52:01.63#ibcon#flushed, iclass 4, count 0 2006.253.07:52:01.63#ibcon#about to write, iclass 4, count 0 2006.253.07:52:01.63#ibcon#wrote, iclass 4, count 0 2006.253.07:52:01.63#ibcon#about to read 3, iclass 4, count 0 2006.253.07:52:01.67#ibcon#read 3, iclass 4, count 0 2006.253.07:52:01.67#ibcon#about to read 4, iclass 4, count 0 2006.253.07:52:01.67#ibcon#read 4, iclass 4, count 0 2006.253.07:52:01.67#ibcon#about to read 5, iclass 4, count 0 2006.253.07:52:01.67#ibcon#read 5, iclass 4, count 0 2006.253.07:52:01.67#ibcon#about to read 6, iclass 4, count 0 2006.253.07:52:01.67#ibcon#read 6, iclass 4, count 0 2006.253.07:52:01.67#ibcon#end of sib2, iclass 4, count 0 2006.253.07:52:01.67#ibcon#*after write, iclass 4, count 0 2006.253.07:52:01.67#ibcon#*before return 0, iclass 4, count 0 2006.253.07:52:01.67#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.253.07:52:01.67#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.253.07:52:01.67#ibcon#about to clear, iclass 4 cls_cnt 0 2006.253.07:52:01.67#ibcon#cleared, iclass 4 cls_cnt 0 2006.253.07:52:01.67$vc4f8/vb=4,4 2006.253.07:52:01.67#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.253.07:52:01.67#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.253.07:52:01.67#ibcon#ireg 11 cls_cnt 2 2006.253.07:52:01.67#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.253.07:52:01.72#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.253.07:52:01.72#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.253.07:52:01.72#ibcon#enter wrdev, iclass 6, count 2 2006.253.07:52:01.72#ibcon#first serial, iclass 6, count 2 2006.253.07:52:01.72#ibcon#enter sib2, iclass 6, count 2 2006.253.07:52:01.72#ibcon#flushed, iclass 6, count 2 2006.253.07:52:01.73#ibcon#about to write, iclass 6, count 2 2006.253.07:52:01.73#ibcon#wrote, iclass 6, count 2 2006.253.07:52:01.73#ibcon#about to read 3, iclass 6, count 2 2006.253.07:52:01.74#ibcon#read 3, iclass 6, count 2 2006.253.07:52:01.74#ibcon#about to read 4, iclass 6, count 2 2006.253.07:52:01.74#ibcon#read 4, iclass 6, count 2 2006.253.07:52:01.74#ibcon#about to read 5, iclass 6, count 2 2006.253.07:52:01.74#ibcon#read 5, iclass 6, count 2 2006.253.07:52:01.74#ibcon#about to read 6, iclass 6, count 2 2006.253.07:52:01.74#ibcon#read 6, iclass 6, count 2 2006.253.07:52:01.74#ibcon#end of sib2, iclass 6, count 2 2006.253.07:52:01.74#ibcon#*mode == 0, iclass 6, count 2 2006.253.07:52:01.74#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.253.07:52:01.74#ibcon#[27=AT04-04\r\n] 2006.253.07:52:01.74#ibcon#*before write, iclass 6, count 2 2006.253.07:52:01.74#ibcon#enter sib2, iclass 6, count 2 2006.253.07:52:01.74#ibcon#flushed, iclass 6, count 2 2006.253.07:52:01.74#ibcon#about to write, iclass 6, count 2 2006.253.07:52:01.74#ibcon#wrote, iclass 6, count 2 2006.253.07:52:01.74#ibcon#about to read 3, iclass 6, count 2 2006.253.07:52:01.77#ibcon#read 3, iclass 6, count 2 2006.253.07:52:01.77#ibcon#about to read 4, iclass 6, count 2 2006.253.07:52:01.77#ibcon#read 4, iclass 6, count 2 2006.253.07:52:01.77#ibcon#about to read 5, iclass 6, count 2 2006.253.07:52:01.77#ibcon#read 5, iclass 6, count 2 2006.253.07:52:01.77#ibcon#about to read 6, iclass 6, count 2 2006.253.07:52:01.77#ibcon#read 6, iclass 6, count 2 2006.253.07:52:01.77#ibcon#end of sib2, iclass 6, count 2 2006.253.07:52:01.77#ibcon#*after write, iclass 6, count 2 2006.253.07:52:01.77#ibcon#*before return 0, iclass 6, count 2 2006.253.07:52:01.77#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.253.07:52:01.77#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.253.07:52:01.77#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.253.07:52:01.77#ibcon#ireg 7 cls_cnt 0 2006.253.07:52:01.77#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.253.07:52:01.89#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.253.07:52:01.89#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.253.07:52:01.89#ibcon#enter wrdev, iclass 6, count 0 2006.253.07:52:01.89#ibcon#first serial, iclass 6, count 0 2006.253.07:52:01.89#ibcon#enter sib2, iclass 6, count 0 2006.253.07:52:01.89#ibcon#flushed, iclass 6, count 0 2006.253.07:52:01.89#ibcon#about to write, iclass 6, count 0 2006.253.07:52:01.89#ibcon#wrote, iclass 6, count 0 2006.253.07:52:01.89#ibcon#about to read 3, iclass 6, count 0 2006.253.07:52:01.91#ibcon#read 3, iclass 6, count 0 2006.253.07:52:01.91#ibcon#about to read 4, iclass 6, count 0 2006.253.07:52:01.91#ibcon#read 4, iclass 6, count 0 2006.253.07:52:01.91#ibcon#about to read 5, iclass 6, count 0 2006.253.07:52:01.91#ibcon#read 5, iclass 6, count 0 2006.253.07:52:01.91#ibcon#about to read 6, iclass 6, count 0 2006.253.07:52:01.91#ibcon#read 6, iclass 6, count 0 2006.253.07:52:01.91#ibcon#end of sib2, iclass 6, count 0 2006.253.07:52:01.91#ibcon#*mode == 0, iclass 6, count 0 2006.253.07:52:01.91#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.253.07:52:01.91#ibcon#[27=USB\r\n] 2006.253.07:52:01.91#ibcon#*before write, iclass 6, count 0 2006.253.07:52:01.91#ibcon#enter sib2, iclass 6, count 0 2006.253.07:52:01.91#ibcon#flushed, iclass 6, count 0 2006.253.07:52:01.91#ibcon#about to write, iclass 6, count 0 2006.253.07:52:01.91#ibcon#wrote, iclass 6, count 0 2006.253.07:52:01.91#ibcon#about to read 3, iclass 6, count 0 2006.253.07:52:01.94#ibcon#read 3, iclass 6, count 0 2006.253.07:52:01.94#ibcon#about to read 4, iclass 6, count 0 2006.253.07:52:01.94#ibcon#read 4, iclass 6, count 0 2006.253.07:52:01.94#ibcon#about to read 5, iclass 6, count 0 2006.253.07:52:01.94#ibcon#read 5, iclass 6, count 0 2006.253.07:52:01.94#ibcon#about to read 6, iclass 6, count 0 2006.253.07:52:01.94#ibcon#read 6, iclass 6, count 0 2006.253.07:52:01.94#ibcon#end of sib2, iclass 6, count 0 2006.253.07:52:01.94#ibcon#*after write, iclass 6, count 0 2006.253.07:52:01.94#ibcon#*before return 0, iclass 6, count 0 2006.253.07:52:01.94#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.253.07:52:01.94#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.253.07:52:01.94#ibcon#about to clear, iclass 6 cls_cnt 0 2006.253.07:52:01.94#ibcon#cleared, iclass 6 cls_cnt 0 2006.253.07:52:01.94$vc4f8/vblo=5,744.99 2006.253.07:52:01.94#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.253.07:52:01.94#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.253.07:52:01.94#ibcon#ireg 17 cls_cnt 0 2006.253.07:52:01.94#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.253.07:52:01.94#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.253.07:52:01.94#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.253.07:52:01.94#ibcon#enter wrdev, iclass 10, count 0 2006.253.07:52:01.94#ibcon#first serial, iclass 10, count 0 2006.253.07:52:01.94#ibcon#enter sib2, iclass 10, count 0 2006.253.07:52:01.94#ibcon#flushed, iclass 10, count 0 2006.253.07:52:01.94#ibcon#about to write, iclass 10, count 0 2006.253.07:52:01.94#ibcon#wrote, iclass 10, count 0 2006.253.07:52:01.94#ibcon#about to read 3, iclass 10, count 0 2006.253.07:52:01.96#ibcon#read 3, iclass 10, count 0 2006.253.07:52:01.96#ibcon#about to read 4, iclass 10, count 0 2006.253.07:52:01.96#ibcon#read 4, iclass 10, count 0 2006.253.07:52:01.96#ibcon#about to read 5, iclass 10, count 0 2006.253.07:52:01.96#ibcon#read 5, iclass 10, count 0 2006.253.07:52:01.96#ibcon#about to read 6, iclass 10, count 0 2006.253.07:52:01.96#ibcon#read 6, iclass 10, count 0 2006.253.07:52:01.96#ibcon#end of sib2, iclass 10, count 0 2006.253.07:52:01.96#ibcon#*mode == 0, iclass 10, count 0 2006.253.07:52:01.96#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.253.07:52:01.96#ibcon#[28=FRQ=05,744.99\r\n] 2006.253.07:52:01.96#ibcon#*before write, iclass 10, count 0 2006.253.07:52:01.96#ibcon#enter sib2, iclass 10, count 0 2006.253.07:52:01.96#ibcon#flushed, iclass 10, count 0 2006.253.07:52:01.96#ibcon#about to write, iclass 10, count 0 2006.253.07:52:01.96#ibcon#wrote, iclass 10, count 0 2006.253.07:52:01.96#ibcon#about to read 3, iclass 10, count 0 2006.253.07:52:02.00#ibcon#read 3, iclass 10, count 0 2006.253.07:52:02.00#ibcon#about to read 4, iclass 10, count 0 2006.253.07:52:02.00#ibcon#read 4, iclass 10, count 0 2006.253.07:52:02.00#ibcon#about to read 5, iclass 10, count 0 2006.253.07:52:02.00#ibcon#read 5, iclass 10, count 0 2006.253.07:52:02.00#ibcon#about to read 6, iclass 10, count 0 2006.253.07:52:02.00#ibcon#read 6, iclass 10, count 0 2006.253.07:52:02.00#ibcon#end of sib2, iclass 10, count 0 2006.253.07:52:02.00#ibcon#*after write, iclass 10, count 0 2006.253.07:52:02.00#ibcon#*before return 0, iclass 10, count 0 2006.253.07:52:02.00#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.253.07:52:02.00#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.253.07:52:02.00#ibcon#about to clear, iclass 10 cls_cnt 0 2006.253.07:52:02.00#ibcon#cleared, iclass 10 cls_cnt 0 2006.253.07:52:02.00$vc4f8/vb=5,4 2006.253.07:52:02.00#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.253.07:52:02.00#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.253.07:52:02.00#ibcon#ireg 11 cls_cnt 2 2006.253.07:52:02.00#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.253.07:52:02.06#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.253.07:52:02.06#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.253.07:52:02.06#ibcon#enter wrdev, iclass 12, count 2 2006.253.07:52:02.06#ibcon#first serial, iclass 12, count 2 2006.253.07:52:02.06#ibcon#enter sib2, iclass 12, count 2 2006.253.07:52:02.06#ibcon#flushed, iclass 12, count 2 2006.253.07:52:02.06#ibcon#about to write, iclass 12, count 2 2006.253.07:52:02.06#ibcon#wrote, iclass 12, count 2 2006.253.07:52:02.06#ibcon#about to read 3, iclass 12, count 2 2006.253.07:52:02.08#ibcon#read 3, iclass 12, count 2 2006.253.07:52:02.08#ibcon#about to read 4, iclass 12, count 2 2006.253.07:52:02.08#ibcon#read 4, iclass 12, count 2 2006.253.07:52:02.08#ibcon#about to read 5, iclass 12, count 2 2006.253.07:52:02.08#ibcon#read 5, iclass 12, count 2 2006.253.07:52:02.08#ibcon#about to read 6, iclass 12, count 2 2006.253.07:52:02.08#ibcon#read 6, iclass 12, count 2 2006.253.07:52:02.08#ibcon#end of sib2, iclass 12, count 2 2006.253.07:52:02.08#ibcon#*mode == 0, iclass 12, count 2 2006.253.07:52:02.08#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.253.07:52:02.08#ibcon#[27=AT05-04\r\n] 2006.253.07:52:02.08#ibcon#*before write, iclass 12, count 2 2006.253.07:52:02.08#ibcon#enter sib2, iclass 12, count 2 2006.253.07:52:02.08#ibcon#flushed, iclass 12, count 2 2006.253.07:52:02.08#ibcon#about to write, iclass 12, count 2 2006.253.07:52:02.08#ibcon#wrote, iclass 12, count 2 2006.253.07:52:02.08#ibcon#about to read 3, iclass 12, count 2 2006.253.07:52:02.11#ibcon#read 3, iclass 12, count 2 2006.253.07:52:02.11#ibcon#about to read 4, iclass 12, count 2 2006.253.07:52:02.11#ibcon#read 4, iclass 12, count 2 2006.253.07:52:02.11#ibcon#about to read 5, iclass 12, count 2 2006.253.07:52:02.11#ibcon#read 5, iclass 12, count 2 2006.253.07:52:02.11#ibcon#about to read 6, iclass 12, count 2 2006.253.07:52:02.11#ibcon#read 6, iclass 12, count 2 2006.253.07:52:02.11#ibcon#end of sib2, iclass 12, count 2 2006.253.07:52:02.11#ibcon#*after write, iclass 12, count 2 2006.253.07:52:02.11#ibcon#*before return 0, iclass 12, count 2 2006.253.07:52:02.11#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.253.07:52:02.11#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.253.07:52:02.11#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.253.07:52:02.11#ibcon#ireg 7 cls_cnt 0 2006.253.07:52:02.11#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.253.07:52:02.23#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.253.07:52:02.23#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.253.07:52:02.23#ibcon#enter wrdev, iclass 12, count 0 2006.253.07:52:02.23#ibcon#first serial, iclass 12, count 0 2006.253.07:52:02.23#ibcon#enter sib2, iclass 12, count 0 2006.253.07:52:02.23#ibcon#flushed, iclass 12, count 0 2006.253.07:52:02.23#ibcon#about to write, iclass 12, count 0 2006.253.07:52:02.23#ibcon#wrote, iclass 12, count 0 2006.253.07:52:02.23#ibcon#about to read 3, iclass 12, count 0 2006.253.07:52:02.25#ibcon#read 3, iclass 12, count 0 2006.253.07:52:02.25#ibcon#about to read 4, iclass 12, count 0 2006.253.07:52:02.25#ibcon#read 4, iclass 12, count 0 2006.253.07:52:02.25#ibcon#about to read 5, iclass 12, count 0 2006.253.07:52:02.25#ibcon#read 5, iclass 12, count 0 2006.253.07:52:02.25#ibcon#about to read 6, iclass 12, count 0 2006.253.07:52:02.25#ibcon#read 6, iclass 12, count 0 2006.253.07:52:02.25#ibcon#end of sib2, iclass 12, count 0 2006.253.07:52:02.25#ibcon#*mode == 0, iclass 12, count 0 2006.253.07:52:02.25#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.253.07:52:02.25#ibcon#[27=USB\r\n] 2006.253.07:52:02.25#ibcon#*before write, iclass 12, count 0 2006.253.07:52:02.25#ibcon#enter sib2, iclass 12, count 0 2006.253.07:52:02.25#ibcon#flushed, iclass 12, count 0 2006.253.07:52:02.25#ibcon#about to write, iclass 12, count 0 2006.253.07:52:02.25#ibcon#wrote, iclass 12, count 0 2006.253.07:52:02.25#ibcon#about to read 3, iclass 12, count 0 2006.253.07:52:02.28#ibcon#read 3, iclass 12, count 0 2006.253.07:52:02.28#ibcon#about to read 4, iclass 12, count 0 2006.253.07:52:02.28#ibcon#read 4, iclass 12, count 0 2006.253.07:52:02.28#ibcon#about to read 5, iclass 12, count 0 2006.253.07:52:02.28#ibcon#read 5, iclass 12, count 0 2006.253.07:52:02.28#ibcon#about to read 6, iclass 12, count 0 2006.253.07:52:02.28#ibcon#read 6, iclass 12, count 0 2006.253.07:52:02.28#ibcon#end of sib2, iclass 12, count 0 2006.253.07:52:02.28#ibcon#*after write, iclass 12, count 0 2006.253.07:52:02.28#ibcon#*before return 0, iclass 12, count 0 2006.253.07:52:02.28#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.253.07:52:02.28#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.253.07:52:02.28#ibcon#about to clear, iclass 12 cls_cnt 0 2006.253.07:52:02.28#ibcon#cleared, iclass 12 cls_cnt 0 2006.253.07:52:02.28$vc4f8/vblo=6,752.99 2006.253.07:52:02.28#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.253.07:52:02.28#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.253.07:52:02.28#ibcon#ireg 17 cls_cnt 0 2006.253.07:52:02.28#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.253.07:52:02.28#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.253.07:52:02.28#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.253.07:52:02.28#ibcon#enter wrdev, iclass 14, count 0 2006.253.07:52:02.28#ibcon#first serial, iclass 14, count 0 2006.253.07:52:02.28#ibcon#enter sib2, iclass 14, count 0 2006.253.07:52:02.28#ibcon#flushed, iclass 14, count 0 2006.253.07:52:02.28#ibcon#about to write, iclass 14, count 0 2006.253.07:52:02.28#ibcon#wrote, iclass 14, count 0 2006.253.07:52:02.28#ibcon#about to read 3, iclass 14, count 0 2006.253.07:52:02.30#ibcon#read 3, iclass 14, count 0 2006.253.07:52:02.30#ibcon#about to read 4, iclass 14, count 0 2006.253.07:52:02.30#ibcon#read 4, iclass 14, count 0 2006.253.07:52:02.30#ibcon#about to read 5, iclass 14, count 0 2006.253.07:52:02.30#ibcon#read 5, iclass 14, count 0 2006.253.07:52:02.30#ibcon#about to read 6, iclass 14, count 0 2006.253.07:52:02.30#ibcon#read 6, iclass 14, count 0 2006.253.07:52:02.30#ibcon#end of sib2, iclass 14, count 0 2006.253.07:52:02.30#ibcon#*mode == 0, iclass 14, count 0 2006.253.07:52:02.30#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.253.07:52:02.30#ibcon#[28=FRQ=06,752.99\r\n] 2006.253.07:52:02.30#ibcon#*before write, iclass 14, count 0 2006.253.07:52:02.30#ibcon#enter sib2, iclass 14, count 0 2006.253.07:52:02.30#ibcon#flushed, iclass 14, count 0 2006.253.07:52:02.30#ibcon#about to write, iclass 14, count 0 2006.253.07:52:02.30#ibcon#wrote, iclass 14, count 0 2006.253.07:52:02.30#ibcon#about to read 3, iclass 14, count 0 2006.253.07:52:02.34#ibcon#read 3, iclass 14, count 0 2006.253.07:52:02.34#ibcon#about to read 4, iclass 14, count 0 2006.253.07:52:02.34#ibcon#read 4, iclass 14, count 0 2006.253.07:52:02.34#ibcon#about to read 5, iclass 14, count 0 2006.253.07:52:02.34#ibcon#read 5, iclass 14, count 0 2006.253.07:52:02.34#ibcon#about to read 6, iclass 14, count 0 2006.253.07:52:02.34#ibcon#read 6, iclass 14, count 0 2006.253.07:52:02.34#ibcon#end of sib2, iclass 14, count 0 2006.253.07:52:02.34#ibcon#*after write, iclass 14, count 0 2006.253.07:52:02.34#ibcon#*before return 0, iclass 14, count 0 2006.253.07:52:02.34#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.253.07:52:02.34#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.253.07:52:02.34#ibcon#about to clear, iclass 14 cls_cnt 0 2006.253.07:52:02.34#ibcon#cleared, iclass 14 cls_cnt 0 2006.253.07:52:02.34$vc4f8/vb=6,4 2006.253.07:52:02.34#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.253.07:52:02.34#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.253.07:52:02.34#ibcon#ireg 11 cls_cnt 2 2006.253.07:52:02.34#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.253.07:52:02.40#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.253.07:52:02.40#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.253.07:52:02.40#ibcon#enter wrdev, iclass 16, count 2 2006.253.07:52:02.40#ibcon#first serial, iclass 16, count 2 2006.253.07:52:02.40#ibcon#enter sib2, iclass 16, count 2 2006.253.07:52:02.40#ibcon#flushed, iclass 16, count 2 2006.253.07:52:02.40#ibcon#about to write, iclass 16, count 2 2006.253.07:52:02.40#ibcon#wrote, iclass 16, count 2 2006.253.07:52:02.40#ibcon#about to read 3, iclass 16, count 2 2006.253.07:52:02.42#ibcon#read 3, iclass 16, count 2 2006.253.07:52:02.42#ibcon#about to read 4, iclass 16, count 2 2006.253.07:52:02.42#ibcon#read 4, iclass 16, count 2 2006.253.07:52:02.42#ibcon#about to read 5, iclass 16, count 2 2006.253.07:52:02.42#ibcon#read 5, iclass 16, count 2 2006.253.07:52:02.42#ibcon#about to read 6, iclass 16, count 2 2006.253.07:52:02.42#ibcon#read 6, iclass 16, count 2 2006.253.07:52:02.42#ibcon#end of sib2, iclass 16, count 2 2006.253.07:52:02.42#ibcon#*mode == 0, iclass 16, count 2 2006.253.07:52:02.42#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.253.07:52:02.42#ibcon#[27=AT06-04\r\n] 2006.253.07:52:02.42#ibcon#*before write, iclass 16, count 2 2006.253.07:52:02.42#ibcon#enter sib2, iclass 16, count 2 2006.253.07:52:02.42#ibcon#flushed, iclass 16, count 2 2006.253.07:52:02.42#ibcon#about to write, iclass 16, count 2 2006.253.07:52:02.42#ibcon#wrote, iclass 16, count 2 2006.253.07:52:02.42#ibcon#about to read 3, iclass 16, count 2 2006.253.07:52:02.45#ibcon#read 3, iclass 16, count 2 2006.253.07:52:02.45#ibcon#about to read 4, iclass 16, count 2 2006.253.07:52:02.45#ibcon#read 4, iclass 16, count 2 2006.253.07:52:02.45#ibcon#about to read 5, iclass 16, count 2 2006.253.07:52:02.45#ibcon#read 5, iclass 16, count 2 2006.253.07:52:02.45#ibcon#about to read 6, iclass 16, count 2 2006.253.07:52:02.45#ibcon#read 6, iclass 16, count 2 2006.253.07:52:02.45#ibcon#end of sib2, iclass 16, count 2 2006.253.07:52:02.45#ibcon#*after write, iclass 16, count 2 2006.253.07:52:02.45#ibcon#*before return 0, iclass 16, count 2 2006.253.07:52:02.45#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.253.07:52:02.45#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.253.07:52:02.45#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.253.07:52:02.45#ibcon#ireg 7 cls_cnt 0 2006.253.07:52:02.45#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.253.07:52:02.57#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.253.07:52:02.57#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.253.07:52:02.57#ibcon#enter wrdev, iclass 16, count 0 2006.253.07:52:02.57#ibcon#first serial, iclass 16, count 0 2006.253.07:52:02.57#ibcon#enter sib2, iclass 16, count 0 2006.253.07:52:02.57#ibcon#flushed, iclass 16, count 0 2006.253.07:52:02.57#ibcon#about to write, iclass 16, count 0 2006.253.07:52:02.57#ibcon#wrote, iclass 16, count 0 2006.253.07:52:02.57#ibcon#about to read 3, iclass 16, count 0 2006.253.07:52:02.59#ibcon#read 3, iclass 16, count 0 2006.253.07:52:02.59#ibcon#about to read 4, iclass 16, count 0 2006.253.07:52:02.59#ibcon#read 4, iclass 16, count 0 2006.253.07:52:02.59#ibcon#about to read 5, iclass 16, count 0 2006.253.07:52:02.59#ibcon#read 5, iclass 16, count 0 2006.253.07:52:02.59#ibcon#about to read 6, iclass 16, count 0 2006.253.07:52:02.59#ibcon#read 6, iclass 16, count 0 2006.253.07:52:02.59#ibcon#end of sib2, iclass 16, count 0 2006.253.07:52:02.59#ibcon#*mode == 0, iclass 16, count 0 2006.253.07:52:02.59#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.253.07:52:02.59#ibcon#[27=USB\r\n] 2006.253.07:52:02.59#ibcon#*before write, iclass 16, count 0 2006.253.07:52:02.59#ibcon#enter sib2, iclass 16, count 0 2006.253.07:52:02.59#ibcon#flushed, iclass 16, count 0 2006.253.07:52:02.59#ibcon#about to write, iclass 16, count 0 2006.253.07:52:02.59#ibcon#wrote, iclass 16, count 0 2006.253.07:52:02.59#ibcon#about to read 3, iclass 16, count 0 2006.253.07:52:02.62#ibcon#read 3, iclass 16, count 0 2006.253.07:52:02.62#ibcon#about to read 4, iclass 16, count 0 2006.253.07:52:02.62#ibcon#read 4, iclass 16, count 0 2006.253.07:52:02.62#ibcon#about to read 5, iclass 16, count 0 2006.253.07:52:02.62#ibcon#read 5, iclass 16, count 0 2006.253.07:52:02.62#ibcon#about to read 6, iclass 16, count 0 2006.253.07:52:02.62#ibcon#read 6, iclass 16, count 0 2006.253.07:52:02.62#ibcon#end of sib2, iclass 16, count 0 2006.253.07:52:02.62#ibcon#*after write, iclass 16, count 0 2006.253.07:52:02.62#ibcon#*before return 0, iclass 16, count 0 2006.253.07:52:02.62#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.253.07:52:02.62#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.253.07:52:02.62#ibcon#about to clear, iclass 16 cls_cnt 0 2006.253.07:52:02.62#ibcon#cleared, iclass 16 cls_cnt 0 2006.253.07:52:02.62$vc4f8/vabw=wide 2006.253.07:52:02.62#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.253.07:52:02.62#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.253.07:52:02.62#ibcon#ireg 8 cls_cnt 0 2006.253.07:52:02.62#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.253.07:52:02.62#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.253.07:52:02.62#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.253.07:52:02.62#ibcon#enter wrdev, iclass 18, count 0 2006.253.07:52:02.62#ibcon#first serial, iclass 18, count 0 2006.253.07:52:02.62#ibcon#enter sib2, iclass 18, count 0 2006.253.07:52:02.62#ibcon#flushed, iclass 18, count 0 2006.253.07:52:02.62#ibcon#about to write, iclass 18, count 0 2006.253.07:52:02.62#ibcon#wrote, iclass 18, count 0 2006.253.07:52:02.62#ibcon#about to read 3, iclass 18, count 0 2006.253.07:52:02.65#ibcon#read 3, iclass 18, count 0 2006.253.07:52:02.65#ibcon#about to read 4, iclass 18, count 0 2006.253.07:52:02.65#ibcon#read 4, iclass 18, count 0 2006.253.07:52:02.65#ibcon#about to read 5, iclass 18, count 0 2006.253.07:52:02.65#ibcon#read 5, iclass 18, count 0 2006.253.07:52:02.65#ibcon#about to read 6, iclass 18, count 0 2006.253.07:52:02.65#ibcon#read 6, iclass 18, count 0 2006.253.07:52:02.65#ibcon#end of sib2, iclass 18, count 0 2006.253.07:52:02.65#ibcon#*mode == 0, iclass 18, count 0 2006.253.07:52:02.65#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.253.07:52:02.65#ibcon#[25=BW32\r\n] 2006.253.07:52:02.65#ibcon#*before write, iclass 18, count 0 2006.253.07:52:02.65#ibcon#enter sib2, iclass 18, count 0 2006.253.07:52:02.65#ibcon#flushed, iclass 18, count 0 2006.253.07:52:02.65#ibcon#about to write, iclass 18, count 0 2006.253.07:52:02.65#ibcon#wrote, iclass 18, count 0 2006.253.07:52:02.65#ibcon#about to read 3, iclass 18, count 0 2006.253.07:52:02.68#ibcon#read 3, iclass 18, count 0 2006.253.07:52:02.68#ibcon#about to read 4, iclass 18, count 0 2006.253.07:52:02.68#ibcon#read 4, iclass 18, count 0 2006.253.07:52:02.68#ibcon#about to read 5, iclass 18, count 0 2006.253.07:52:02.68#ibcon#read 5, iclass 18, count 0 2006.253.07:52:02.68#ibcon#about to read 6, iclass 18, count 0 2006.253.07:52:02.68#ibcon#read 6, iclass 18, count 0 2006.253.07:52:02.68#ibcon#end of sib2, iclass 18, count 0 2006.253.07:52:02.68#ibcon#*after write, iclass 18, count 0 2006.253.07:52:02.68#ibcon#*before return 0, iclass 18, count 0 2006.253.07:52:02.68#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.253.07:52:02.68#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.253.07:52:02.68#ibcon#about to clear, iclass 18 cls_cnt 0 2006.253.07:52:02.68#ibcon#cleared, iclass 18 cls_cnt 0 2006.253.07:52:02.68$vc4f8/vbbw=wide 2006.253.07:52:02.68#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.253.07:52:02.68#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.253.07:52:02.68#ibcon#ireg 8 cls_cnt 0 2006.253.07:52:02.68#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.253.07:52:02.74#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.253.07:52:02.74#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.253.07:52:02.74#ibcon#enter wrdev, iclass 20, count 0 2006.253.07:52:02.74#ibcon#first serial, iclass 20, count 0 2006.253.07:52:02.74#ibcon#enter sib2, iclass 20, count 0 2006.253.07:52:02.74#ibcon#flushed, iclass 20, count 0 2006.253.07:52:02.74#ibcon#about to write, iclass 20, count 0 2006.253.07:52:02.75#ibcon#wrote, iclass 20, count 0 2006.253.07:52:02.75#ibcon#about to read 3, iclass 20, count 0 2006.253.07:52:02.76#ibcon#read 3, iclass 20, count 0 2006.253.07:52:02.76#ibcon#about to read 4, iclass 20, count 0 2006.253.07:52:02.76#ibcon#read 4, iclass 20, count 0 2006.253.07:52:02.76#ibcon#about to read 5, iclass 20, count 0 2006.253.07:52:02.76#ibcon#read 5, iclass 20, count 0 2006.253.07:52:02.76#ibcon#about to read 6, iclass 20, count 0 2006.253.07:52:02.76#ibcon#read 6, iclass 20, count 0 2006.253.07:52:02.76#ibcon#end of sib2, iclass 20, count 0 2006.253.07:52:02.76#ibcon#*mode == 0, iclass 20, count 0 2006.253.07:52:02.76#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.253.07:52:02.76#ibcon#[27=BW32\r\n] 2006.253.07:52:02.76#ibcon#*before write, iclass 20, count 0 2006.253.07:52:02.76#ibcon#enter sib2, iclass 20, count 0 2006.253.07:52:02.76#ibcon#flushed, iclass 20, count 0 2006.253.07:52:02.76#ibcon#about to write, iclass 20, count 0 2006.253.07:52:02.76#ibcon#wrote, iclass 20, count 0 2006.253.07:52:02.76#ibcon#about to read 3, iclass 20, count 0 2006.253.07:52:02.79#ibcon#read 3, iclass 20, count 0 2006.253.07:52:02.79#ibcon#about to read 4, iclass 20, count 0 2006.253.07:52:02.79#ibcon#read 4, iclass 20, count 0 2006.253.07:52:02.79#ibcon#about to read 5, iclass 20, count 0 2006.253.07:52:02.79#ibcon#read 5, iclass 20, count 0 2006.253.07:52:02.79#ibcon#about to read 6, iclass 20, count 0 2006.253.07:52:02.79#ibcon#read 6, iclass 20, count 0 2006.253.07:52:02.79#ibcon#end of sib2, iclass 20, count 0 2006.253.07:52:02.79#ibcon#*after write, iclass 20, count 0 2006.253.07:52:02.79#ibcon#*before return 0, iclass 20, count 0 2006.253.07:52:02.79#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.253.07:52:02.79#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.253.07:52:02.79#ibcon#about to clear, iclass 20 cls_cnt 0 2006.253.07:52:02.79#ibcon#cleared, iclass 20 cls_cnt 0 2006.253.07:52:02.79$4f8m12a/ifd4f 2006.253.07:52:02.79$ifd4f/lo= 2006.253.07:52:02.79$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.253.07:52:02.79$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.253.07:52:02.79$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.253.07:52:02.79$ifd4f/patch= 2006.253.07:52:02.79$ifd4f/patch=lo1,a1,a2,a3,a4 2006.253.07:52:02.79$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.253.07:52:02.79$ifd4f/patch=lo3,a5,a6,a7,a8 2006.253.07:52:02.79$4f8m12a/"form=m,16.000,1:2 2006.253.07:52:02.80$4f8m12a/"tpicd 2006.253.07:52:02.80$4f8m12a/echo=off 2006.253.07:52:02.80$4f8m12a/xlog=off 2006.253.07:52:02.80:!2006.253.07:52:40 2006.253.07:52:21.14#trakl#Source acquired 2006.253.07:52:23.14#flagr#flagr/antenna,acquired 2006.253.07:52:40.01:preob 2006.253.07:52:41.14/onsource/TRACKING 2006.253.07:52:41.14:!2006.253.07:52:50 2006.253.07:52:50.00:data_valid=on 2006.253.07:52:50.00:midob 2006.253.07:52:50.14/onsource/TRACKING 2006.253.07:52:50.14/wx/31.27,1006.4,73 2006.253.07:52:50.24/cable/+6.3689E-03 2006.253.07:52:51.33/va/01,08,usb,yes,32,33 2006.253.07:52:51.33/va/02,07,usb,yes,32,33 2006.253.07:52:51.33/va/03,06,usb,yes,34,34 2006.253.07:52:51.33/va/04,07,usb,yes,33,36 2006.253.07:52:51.33/va/05,07,usb,yes,34,36 2006.253.07:52:51.33/va/06,07,usb,yes,30,30 2006.253.07:52:51.33/va/07,07,usb,yes,30,29 2006.253.07:52:51.33/va/08,07,usb,yes,32,32 2006.253.07:52:51.56/valo/01,532.99,yes,locked 2006.253.07:52:51.56/valo/02,572.99,yes,locked 2006.253.07:52:51.56/valo/03,672.99,yes,locked 2006.253.07:52:51.56/valo/04,832.99,yes,locked 2006.253.07:52:51.56/valo/05,652.99,yes,locked 2006.253.07:52:51.56/valo/06,772.99,yes,locked 2006.253.07:52:51.56/valo/07,832.99,yes,locked 2006.253.07:52:51.56/valo/08,852.99,yes,locked 2006.253.07:52:52.65/vb/01,04,usb,yes,30,29 2006.253.07:52:52.65/vb/02,05,usb,yes,28,29 2006.253.07:52:52.65/vb/03,04,usb,yes,28,32 2006.253.07:52:52.65/vb/04,04,usb,yes,29,29 2006.253.07:52:52.65/vb/05,04,usb,yes,28,32 2006.253.07:52:52.65/vb/06,04,usb,yes,29,32 2006.253.07:52:52.65/vb/07,04,usb,yes,31,31 2006.253.07:52:52.65/vb/08,04,usb,yes,28,32 2006.253.07:52:52.89/vblo/01,632.99,yes,locked 2006.253.07:52:52.89/vblo/02,640.99,yes,locked 2006.253.07:52:52.89/vblo/03,656.99,yes,locked 2006.253.07:52:52.89/vblo/04,712.99,yes,locked 2006.253.07:52:52.89/vblo/05,744.99,yes,locked 2006.253.07:52:52.89/vblo/06,752.99,yes,locked 2006.253.07:52:52.89/vblo/07,734.99,yes,locked 2006.253.07:52:52.89/vblo/08,744.99,yes,locked 2006.253.07:52:53.04/vabw/8 2006.253.07:52:53.19/vbbw/8 2006.253.07:52:53.28/xfe/off,on,14.0 2006.253.07:52:53.65/ifatt/23,28,28,28 2006.253.07:52:54.07/fmout-gps/S +4.73E-07 2006.253.07:52:54.11:!2006.253.07:53:50 2006.253.07:53:50.01:data_valid=off 2006.253.07:53:50.02:postob 2006.253.07:53:50.15/cable/+6.3697E-03 2006.253.07:53:50.16/wx/31.24,1006.4,73 2006.253.07:53:51.07/fmout-gps/S +4.72E-07 2006.253.07:53:51.08:scan_name=253-0755,k06253,60 2006.253.07:53:51.08:source=4c39.25,092703.01,390220.9,2000.0,ccw 2006.253.07:53:52.14#flagr#flagr/antenna,new-source 2006.253.07:53:52.15:checkk5 2006.253.07:53:52.52/chk_autoobs//k5ts1/ autoobs is running! 2006.253.07:53:52.90/chk_autoobs//k5ts2/ autoobs is running! 2006.253.07:53:53.24/chk_autoobs//k5ts3/ autoobs is running! 2006.253.07:53:53.61/chk_autoobs//k5ts4/ autoobs is running! 2006.253.07:53:53.99/chk_obsdata//k5ts1/T2530752??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.07:53:54.36/chk_obsdata//k5ts2/T2530752??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.07:53:54.73/chk_obsdata//k5ts3/T2530752??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.07:53:55.10/chk_obsdata//k5ts4/T2530752??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.07:53:55.80/k5log//k5ts1_log_newline 2006.253.07:53:56.49/k5log//k5ts2_log_newline 2006.253.07:53:57.18/k5log//k5ts3_log_newline 2006.253.07:53:57.87/k5log//k5ts4_log_newline 2006.253.07:53:57.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.253.07:53:57.89:4f8m12a=2 2006.253.07:53:57.89$4f8m12a/echo=on 2006.253.07:53:57.89$4f8m12a/pcalon 2006.253.07:53:57.89$pcalon/"no phase cal control is implemented here 2006.253.07:53:57.89$4f8m12a/"tpicd=stop 2006.253.07:53:57.89$4f8m12a/vc4f8 2006.253.07:53:57.89$vc4f8/valo=1,532.99 2006.253.07:53:57.90#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.253.07:53:57.90#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.253.07:53:57.90#ibcon#ireg 17 cls_cnt 0 2006.253.07:53:57.90#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.253.07:53:57.90#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.253.07:53:57.90#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.253.07:53:57.90#ibcon#enter wrdev, iclass 35, count 0 2006.253.07:53:57.90#ibcon#first serial, iclass 35, count 0 2006.253.07:53:57.90#ibcon#enter sib2, iclass 35, count 0 2006.253.07:53:57.90#ibcon#flushed, iclass 35, count 0 2006.253.07:53:57.90#ibcon#about to write, iclass 35, count 0 2006.253.07:53:57.90#ibcon#wrote, iclass 35, count 0 2006.253.07:53:57.90#ibcon#about to read 3, iclass 35, count 0 2006.253.07:53:57.94#ibcon#read 3, iclass 35, count 0 2006.253.07:53:57.94#ibcon#about to read 4, iclass 35, count 0 2006.253.07:53:57.94#ibcon#read 4, iclass 35, count 0 2006.253.07:53:57.94#ibcon#about to read 5, iclass 35, count 0 2006.253.07:53:57.94#ibcon#read 5, iclass 35, count 0 2006.253.07:53:57.94#ibcon#about to read 6, iclass 35, count 0 2006.253.07:53:57.94#ibcon#read 6, iclass 35, count 0 2006.253.07:53:57.94#ibcon#end of sib2, iclass 35, count 0 2006.253.07:53:57.94#ibcon#*mode == 0, iclass 35, count 0 2006.253.07:53:57.94#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.253.07:53:57.94#ibcon#[26=FRQ=01,532.99\r\n] 2006.253.07:53:57.94#ibcon#*before write, iclass 35, count 0 2006.253.07:53:57.94#ibcon#enter sib2, iclass 35, count 0 2006.253.07:53:57.94#ibcon#flushed, iclass 35, count 0 2006.253.07:53:57.94#ibcon#about to write, iclass 35, count 0 2006.253.07:53:57.94#ibcon#wrote, iclass 35, count 0 2006.253.07:53:57.94#ibcon#about to read 3, iclass 35, count 0 2006.253.07:53:57.98#ibcon#read 3, iclass 35, count 0 2006.253.07:53:57.98#ibcon#about to read 4, iclass 35, count 0 2006.253.07:53:57.98#ibcon#read 4, iclass 35, count 0 2006.253.07:53:57.98#ibcon#about to read 5, iclass 35, count 0 2006.253.07:53:57.98#ibcon#read 5, iclass 35, count 0 2006.253.07:53:57.98#ibcon#about to read 6, iclass 35, count 0 2006.253.07:53:57.98#ibcon#read 6, iclass 35, count 0 2006.253.07:53:57.98#ibcon#end of sib2, iclass 35, count 0 2006.253.07:53:57.98#ibcon#*after write, iclass 35, count 0 2006.253.07:53:57.98#ibcon#*before return 0, iclass 35, count 0 2006.253.07:53:57.98#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.253.07:53:57.98#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.253.07:53:57.98#ibcon#about to clear, iclass 35 cls_cnt 0 2006.253.07:53:57.98#ibcon#cleared, iclass 35 cls_cnt 0 2006.253.07:53:57.98$vc4f8/va=1,8 2006.253.07:53:57.98#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.253.07:53:57.98#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.253.07:53:57.98#ibcon#ireg 11 cls_cnt 2 2006.253.07:53:57.98#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.253.07:53:57.98#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.253.07:53:57.98#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.253.07:53:57.98#ibcon#enter wrdev, iclass 37, count 2 2006.253.07:53:57.98#ibcon#first serial, iclass 37, count 2 2006.253.07:53:57.98#ibcon#enter sib2, iclass 37, count 2 2006.253.07:53:57.98#ibcon#flushed, iclass 37, count 2 2006.253.07:53:57.98#ibcon#about to write, iclass 37, count 2 2006.253.07:53:57.98#ibcon#wrote, iclass 37, count 2 2006.253.07:53:57.98#ibcon#about to read 3, iclass 37, count 2 2006.253.07:53:58.01#ibcon#read 3, iclass 37, count 2 2006.253.07:53:58.01#ibcon#about to read 4, iclass 37, count 2 2006.253.07:53:58.01#ibcon#read 4, iclass 37, count 2 2006.253.07:53:58.01#ibcon#about to read 5, iclass 37, count 2 2006.253.07:53:58.01#ibcon#read 5, iclass 37, count 2 2006.253.07:53:58.01#ibcon#about to read 6, iclass 37, count 2 2006.253.07:53:58.01#ibcon#read 6, iclass 37, count 2 2006.253.07:53:58.01#ibcon#end of sib2, iclass 37, count 2 2006.253.07:53:58.01#ibcon#*mode == 0, iclass 37, count 2 2006.253.07:53:58.01#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.253.07:53:58.01#ibcon#[25=AT01-08\r\n] 2006.253.07:53:58.01#ibcon#*before write, iclass 37, count 2 2006.253.07:53:58.01#ibcon#enter sib2, iclass 37, count 2 2006.253.07:53:58.01#ibcon#flushed, iclass 37, count 2 2006.253.07:53:58.01#ibcon#about to write, iclass 37, count 2 2006.253.07:53:58.01#ibcon#wrote, iclass 37, count 2 2006.253.07:53:58.01#ibcon#about to read 3, iclass 37, count 2 2006.253.07:53:58.04#ibcon#read 3, iclass 37, count 2 2006.253.07:53:58.04#ibcon#about to read 4, iclass 37, count 2 2006.253.07:53:58.04#ibcon#read 4, iclass 37, count 2 2006.253.07:53:58.04#ibcon#about to read 5, iclass 37, count 2 2006.253.07:53:58.04#ibcon#read 5, iclass 37, count 2 2006.253.07:53:58.04#ibcon#about to read 6, iclass 37, count 2 2006.253.07:53:58.04#ibcon#read 6, iclass 37, count 2 2006.253.07:53:58.04#ibcon#end of sib2, iclass 37, count 2 2006.253.07:53:58.04#ibcon#*after write, iclass 37, count 2 2006.253.07:53:58.04#ibcon#*before return 0, iclass 37, count 2 2006.253.07:53:58.04#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.253.07:53:58.04#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.253.07:53:58.04#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.253.07:53:58.04#ibcon#ireg 7 cls_cnt 0 2006.253.07:53:58.04#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.253.07:53:58.16#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.253.07:53:58.16#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.253.07:53:58.16#ibcon#enter wrdev, iclass 37, count 0 2006.253.07:53:58.16#ibcon#first serial, iclass 37, count 0 2006.253.07:53:58.16#ibcon#enter sib2, iclass 37, count 0 2006.253.07:53:58.16#ibcon#flushed, iclass 37, count 0 2006.253.07:53:58.16#ibcon#about to write, iclass 37, count 0 2006.253.07:53:58.16#ibcon#wrote, iclass 37, count 0 2006.253.07:53:58.16#ibcon#about to read 3, iclass 37, count 0 2006.253.07:53:58.18#ibcon#read 3, iclass 37, count 0 2006.253.07:53:58.18#ibcon#about to read 4, iclass 37, count 0 2006.253.07:53:58.18#ibcon#read 4, iclass 37, count 0 2006.253.07:53:58.18#ibcon#about to read 5, iclass 37, count 0 2006.253.07:53:58.18#ibcon#read 5, iclass 37, count 0 2006.253.07:53:58.18#ibcon#about to read 6, iclass 37, count 0 2006.253.07:53:58.18#ibcon#read 6, iclass 37, count 0 2006.253.07:53:58.18#ibcon#end of sib2, iclass 37, count 0 2006.253.07:53:58.18#ibcon#*mode == 0, iclass 37, count 0 2006.253.07:53:58.18#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.253.07:53:58.18#ibcon#[25=USB\r\n] 2006.253.07:53:58.18#ibcon#*before write, iclass 37, count 0 2006.253.07:53:58.18#ibcon#enter sib2, iclass 37, count 0 2006.253.07:53:58.18#ibcon#flushed, iclass 37, count 0 2006.253.07:53:58.18#ibcon#about to write, iclass 37, count 0 2006.253.07:53:58.18#ibcon#wrote, iclass 37, count 0 2006.253.07:53:58.18#ibcon#about to read 3, iclass 37, count 0 2006.253.07:53:58.21#ibcon#read 3, iclass 37, count 0 2006.253.07:53:58.21#ibcon#about to read 4, iclass 37, count 0 2006.253.07:53:58.21#ibcon#read 4, iclass 37, count 0 2006.253.07:53:58.21#ibcon#about to read 5, iclass 37, count 0 2006.253.07:53:58.21#ibcon#read 5, iclass 37, count 0 2006.253.07:53:58.21#ibcon#about to read 6, iclass 37, count 0 2006.253.07:53:58.21#ibcon#read 6, iclass 37, count 0 2006.253.07:53:58.21#ibcon#end of sib2, iclass 37, count 0 2006.253.07:53:58.21#ibcon#*after write, iclass 37, count 0 2006.253.07:53:58.21#ibcon#*before return 0, iclass 37, count 0 2006.253.07:53:58.21#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.253.07:53:58.21#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.253.07:53:58.21#ibcon#about to clear, iclass 37 cls_cnt 0 2006.253.07:53:58.21#ibcon#cleared, iclass 37 cls_cnt 0 2006.253.07:53:58.21$vc4f8/valo=2,572.99 2006.253.07:53:58.21#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.253.07:53:58.21#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.253.07:53:58.21#ibcon#ireg 17 cls_cnt 0 2006.253.07:53:58.21#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.253.07:53:58.21#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.253.07:53:58.21#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.253.07:53:58.21#ibcon#enter wrdev, iclass 39, count 0 2006.253.07:53:58.21#ibcon#first serial, iclass 39, count 0 2006.253.07:53:58.21#ibcon#enter sib2, iclass 39, count 0 2006.253.07:53:58.21#ibcon#flushed, iclass 39, count 0 2006.253.07:53:58.21#ibcon#about to write, iclass 39, count 0 2006.253.07:53:58.21#ibcon#wrote, iclass 39, count 0 2006.253.07:53:58.21#ibcon#about to read 3, iclass 39, count 0 2006.253.07:53:58.23#ibcon#read 3, iclass 39, count 0 2006.253.07:53:58.23#ibcon#about to read 4, iclass 39, count 0 2006.253.07:53:58.23#ibcon#read 4, iclass 39, count 0 2006.253.07:53:58.23#ibcon#about to read 5, iclass 39, count 0 2006.253.07:53:58.23#ibcon#read 5, iclass 39, count 0 2006.253.07:53:58.23#ibcon#about to read 6, iclass 39, count 0 2006.253.07:53:58.23#ibcon#read 6, iclass 39, count 0 2006.253.07:53:58.23#ibcon#end of sib2, iclass 39, count 0 2006.253.07:53:58.23#ibcon#*mode == 0, iclass 39, count 0 2006.253.07:53:58.23#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.253.07:53:58.23#ibcon#[26=FRQ=02,572.99\r\n] 2006.253.07:53:58.23#ibcon#*before write, iclass 39, count 0 2006.253.07:53:58.23#ibcon#enter sib2, iclass 39, count 0 2006.253.07:53:58.23#ibcon#flushed, iclass 39, count 0 2006.253.07:53:58.23#ibcon#about to write, iclass 39, count 0 2006.253.07:53:58.23#ibcon#wrote, iclass 39, count 0 2006.253.07:53:58.23#ibcon#about to read 3, iclass 39, count 0 2006.253.07:53:58.27#ibcon#read 3, iclass 39, count 0 2006.253.07:53:58.27#ibcon#about to read 4, iclass 39, count 0 2006.253.07:53:58.27#ibcon#read 4, iclass 39, count 0 2006.253.07:53:58.27#ibcon#about to read 5, iclass 39, count 0 2006.253.07:53:58.27#ibcon#read 5, iclass 39, count 0 2006.253.07:53:58.27#ibcon#about to read 6, iclass 39, count 0 2006.253.07:53:58.27#ibcon#read 6, iclass 39, count 0 2006.253.07:53:58.27#ibcon#end of sib2, iclass 39, count 0 2006.253.07:53:58.27#ibcon#*after write, iclass 39, count 0 2006.253.07:53:58.27#ibcon#*before return 0, iclass 39, count 0 2006.253.07:53:58.27#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.253.07:53:58.27#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.253.07:53:58.27#ibcon#about to clear, iclass 39 cls_cnt 0 2006.253.07:53:58.27#ibcon#cleared, iclass 39 cls_cnt 0 2006.253.07:53:58.27$vc4f8/va=2,7 2006.253.07:53:58.27#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.253.07:53:58.27#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.253.07:53:58.27#ibcon#ireg 11 cls_cnt 2 2006.253.07:53:58.27#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.253.07:53:58.33#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.253.07:53:58.33#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.253.07:53:58.33#ibcon#enter wrdev, iclass 3, count 2 2006.253.07:53:58.33#ibcon#first serial, iclass 3, count 2 2006.253.07:53:58.33#ibcon#enter sib2, iclass 3, count 2 2006.253.07:53:58.33#ibcon#flushed, iclass 3, count 2 2006.253.07:53:58.33#ibcon#about to write, iclass 3, count 2 2006.253.07:53:58.33#ibcon#wrote, iclass 3, count 2 2006.253.07:53:58.33#ibcon#about to read 3, iclass 3, count 2 2006.253.07:53:58.35#ibcon#read 3, iclass 3, count 2 2006.253.07:53:58.35#ibcon#about to read 4, iclass 3, count 2 2006.253.07:53:58.35#ibcon#read 4, iclass 3, count 2 2006.253.07:53:58.35#ibcon#about to read 5, iclass 3, count 2 2006.253.07:53:58.35#ibcon#read 5, iclass 3, count 2 2006.253.07:53:58.35#ibcon#about to read 6, iclass 3, count 2 2006.253.07:53:58.35#ibcon#read 6, iclass 3, count 2 2006.253.07:53:58.35#ibcon#end of sib2, iclass 3, count 2 2006.253.07:53:58.35#ibcon#*mode == 0, iclass 3, count 2 2006.253.07:53:58.35#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.253.07:53:58.35#ibcon#[25=AT02-07\r\n] 2006.253.07:53:58.35#ibcon#*before write, iclass 3, count 2 2006.253.07:53:58.35#ibcon#enter sib2, iclass 3, count 2 2006.253.07:53:58.35#ibcon#flushed, iclass 3, count 2 2006.253.07:53:58.35#ibcon#about to write, iclass 3, count 2 2006.253.07:53:58.35#ibcon#wrote, iclass 3, count 2 2006.253.07:53:58.35#ibcon#about to read 3, iclass 3, count 2 2006.253.07:53:58.38#ibcon#read 3, iclass 3, count 2 2006.253.07:53:58.38#ibcon#about to read 4, iclass 3, count 2 2006.253.07:53:58.38#ibcon#read 4, iclass 3, count 2 2006.253.07:53:58.38#ibcon#about to read 5, iclass 3, count 2 2006.253.07:53:58.38#ibcon#read 5, iclass 3, count 2 2006.253.07:53:58.38#ibcon#about to read 6, iclass 3, count 2 2006.253.07:53:58.38#ibcon#read 6, iclass 3, count 2 2006.253.07:53:58.38#ibcon#end of sib2, iclass 3, count 2 2006.253.07:53:58.38#ibcon#*after write, iclass 3, count 2 2006.253.07:53:58.38#ibcon#*before return 0, iclass 3, count 2 2006.253.07:53:58.38#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.253.07:53:58.38#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.253.07:53:58.38#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.253.07:53:58.38#ibcon#ireg 7 cls_cnt 0 2006.253.07:53:58.38#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.253.07:53:58.51#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.253.07:53:58.51#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.253.07:53:58.51#ibcon#enter wrdev, iclass 3, count 0 2006.253.07:53:58.51#ibcon#first serial, iclass 3, count 0 2006.253.07:53:58.51#ibcon#enter sib2, iclass 3, count 0 2006.253.07:53:58.51#ibcon#flushed, iclass 3, count 0 2006.253.07:53:58.51#ibcon#about to write, iclass 3, count 0 2006.253.07:53:58.51#ibcon#wrote, iclass 3, count 0 2006.253.07:53:58.51#ibcon#about to read 3, iclass 3, count 0 2006.253.07:53:58.52#ibcon#read 3, iclass 3, count 0 2006.253.07:53:58.52#ibcon#about to read 4, iclass 3, count 0 2006.253.07:53:58.52#ibcon#read 4, iclass 3, count 0 2006.253.07:53:58.52#ibcon#about to read 5, iclass 3, count 0 2006.253.07:53:58.52#ibcon#read 5, iclass 3, count 0 2006.253.07:53:58.52#ibcon#about to read 6, iclass 3, count 0 2006.253.07:53:58.52#ibcon#read 6, iclass 3, count 0 2006.253.07:53:58.52#ibcon#end of sib2, iclass 3, count 0 2006.253.07:53:58.52#ibcon#*mode == 0, iclass 3, count 0 2006.253.07:53:58.52#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.253.07:53:58.52#ibcon#[25=USB\r\n] 2006.253.07:53:58.52#ibcon#*before write, iclass 3, count 0 2006.253.07:53:58.52#ibcon#enter sib2, iclass 3, count 0 2006.253.07:53:58.52#ibcon#flushed, iclass 3, count 0 2006.253.07:53:58.52#ibcon#about to write, iclass 3, count 0 2006.253.07:53:58.52#ibcon#wrote, iclass 3, count 0 2006.253.07:53:58.52#ibcon#about to read 3, iclass 3, count 0 2006.253.07:53:58.55#ibcon#read 3, iclass 3, count 0 2006.253.07:53:58.55#ibcon#about to read 4, iclass 3, count 0 2006.253.07:53:58.55#ibcon#read 4, iclass 3, count 0 2006.253.07:53:58.55#ibcon#about to read 5, iclass 3, count 0 2006.253.07:53:58.55#ibcon#read 5, iclass 3, count 0 2006.253.07:53:58.55#ibcon#about to read 6, iclass 3, count 0 2006.253.07:53:58.55#ibcon#read 6, iclass 3, count 0 2006.253.07:53:58.55#ibcon#end of sib2, iclass 3, count 0 2006.253.07:53:58.55#ibcon#*after write, iclass 3, count 0 2006.253.07:53:58.55#ibcon#*before return 0, iclass 3, count 0 2006.253.07:53:58.55#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.253.07:53:58.55#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.253.07:53:58.55#ibcon#about to clear, iclass 3 cls_cnt 0 2006.253.07:53:58.55#ibcon#cleared, iclass 3 cls_cnt 0 2006.253.07:53:58.55$vc4f8/valo=3,672.99 2006.253.07:53:58.55#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.253.07:53:58.55#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.253.07:53:58.55#ibcon#ireg 17 cls_cnt 0 2006.253.07:53:58.55#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.253.07:53:58.55#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.253.07:53:58.55#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.253.07:53:58.55#ibcon#enter wrdev, iclass 5, count 0 2006.253.07:53:58.55#ibcon#first serial, iclass 5, count 0 2006.253.07:53:58.55#ibcon#enter sib2, iclass 5, count 0 2006.253.07:53:58.55#ibcon#flushed, iclass 5, count 0 2006.253.07:53:58.55#ibcon#about to write, iclass 5, count 0 2006.253.07:53:58.55#ibcon#wrote, iclass 5, count 0 2006.253.07:53:58.55#ibcon#about to read 3, iclass 5, count 0 2006.253.07:53:58.58#ibcon#read 3, iclass 5, count 0 2006.253.07:53:58.58#ibcon#about to read 4, iclass 5, count 0 2006.253.07:53:58.58#ibcon#read 4, iclass 5, count 0 2006.253.07:53:58.58#ibcon#about to read 5, iclass 5, count 0 2006.253.07:53:58.58#ibcon#read 5, iclass 5, count 0 2006.253.07:53:58.58#ibcon#about to read 6, iclass 5, count 0 2006.253.07:53:58.58#ibcon#read 6, iclass 5, count 0 2006.253.07:53:58.58#ibcon#end of sib2, iclass 5, count 0 2006.253.07:53:58.58#ibcon#*mode == 0, iclass 5, count 0 2006.253.07:53:58.58#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.253.07:53:58.58#ibcon#[26=FRQ=03,672.99\r\n] 2006.253.07:53:58.58#ibcon#*before write, iclass 5, count 0 2006.253.07:53:58.58#ibcon#enter sib2, iclass 5, count 0 2006.253.07:53:58.58#ibcon#flushed, iclass 5, count 0 2006.253.07:53:58.58#ibcon#about to write, iclass 5, count 0 2006.253.07:53:58.58#ibcon#wrote, iclass 5, count 0 2006.253.07:53:58.58#ibcon#about to read 3, iclass 5, count 0 2006.253.07:53:58.62#ibcon#read 3, iclass 5, count 0 2006.253.07:53:58.62#ibcon#about to read 4, iclass 5, count 0 2006.253.07:53:58.62#ibcon#read 4, iclass 5, count 0 2006.253.07:53:58.62#ibcon#about to read 5, iclass 5, count 0 2006.253.07:53:58.62#ibcon#read 5, iclass 5, count 0 2006.253.07:53:58.62#ibcon#about to read 6, iclass 5, count 0 2006.253.07:53:58.62#ibcon#read 6, iclass 5, count 0 2006.253.07:53:58.62#ibcon#end of sib2, iclass 5, count 0 2006.253.07:53:58.62#ibcon#*after write, iclass 5, count 0 2006.253.07:53:58.62#ibcon#*before return 0, iclass 5, count 0 2006.253.07:53:58.62#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.253.07:53:58.62#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.253.07:53:58.62#ibcon#about to clear, iclass 5 cls_cnt 0 2006.253.07:53:58.62#ibcon#cleared, iclass 5 cls_cnt 0 2006.253.07:53:58.62$vc4f8/va=3,6 2006.253.07:53:58.62#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.253.07:53:58.62#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.253.07:53:58.62#ibcon#ireg 11 cls_cnt 2 2006.253.07:53:58.62#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.253.07:53:58.67#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.253.07:53:58.67#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.253.07:53:58.67#ibcon#enter wrdev, iclass 7, count 2 2006.253.07:53:58.67#ibcon#first serial, iclass 7, count 2 2006.253.07:53:58.67#ibcon#enter sib2, iclass 7, count 2 2006.253.07:53:58.67#ibcon#flushed, iclass 7, count 2 2006.253.07:53:58.67#ibcon#about to write, iclass 7, count 2 2006.253.07:53:58.67#ibcon#wrote, iclass 7, count 2 2006.253.07:53:58.67#ibcon#about to read 3, iclass 7, count 2 2006.253.07:53:58.69#ibcon#read 3, iclass 7, count 2 2006.253.07:53:58.69#ibcon#about to read 4, iclass 7, count 2 2006.253.07:53:58.69#ibcon#read 4, iclass 7, count 2 2006.253.07:53:58.69#ibcon#about to read 5, iclass 7, count 2 2006.253.07:53:58.69#ibcon#read 5, iclass 7, count 2 2006.253.07:53:58.69#ibcon#about to read 6, iclass 7, count 2 2006.253.07:53:58.69#ibcon#read 6, iclass 7, count 2 2006.253.07:53:58.69#ibcon#end of sib2, iclass 7, count 2 2006.253.07:53:58.69#ibcon#*mode == 0, iclass 7, count 2 2006.253.07:53:58.69#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.253.07:53:58.69#ibcon#[25=AT03-06\r\n] 2006.253.07:53:58.69#ibcon#*before write, iclass 7, count 2 2006.253.07:53:58.69#ibcon#enter sib2, iclass 7, count 2 2006.253.07:53:58.69#ibcon#flushed, iclass 7, count 2 2006.253.07:53:58.69#ibcon#about to write, iclass 7, count 2 2006.253.07:53:58.69#ibcon#wrote, iclass 7, count 2 2006.253.07:53:58.69#ibcon#about to read 3, iclass 7, count 2 2006.253.07:53:58.72#ibcon#read 3, iclass 7, count 2 2006.253.07:53:58.72#ibcon#about to read 4, iclass 7, count 2 2006.253.07:53:58.72#ibcon#read 4, iclass 7, count 2 2006.253.07:53:58.72#ibcon#about to read 5, iclass 7, count 2 2006.253.07:53:58.72#ibcon#read 5, iclass 7, count 2 2006.253.07:53:58.72#ibcon#about to read 6, iclass 7, count 2 2006.253.07:53:58.72#ibcon#read 6, iclass 7, count 2 2006.253.07:53:58.72#ibcon#end of sib2, iclass 7, count 2 2006.253.07:53:58.72#ibcon#*after write, iclass 7, count 2 2006.253.07:53:58.72#ibcon#*before return 0, iclass 7, count 2 2006.253.07:53:58.72#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.253.07:53:58.72#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.253.07:53:58.72#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.253.07:53:58.72#ibcon#ireg 7 cls_cnt 0 2006.253.07:53:58.72#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.253.07:53:58.84#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.253.07:53:58.84#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.253.07:53:58.84#ibcon#enter wrdev, iclass 7, count 0 2006.253.07:53:58.84#ibcon#first serial, iclass 7, count 0 2006.253.07:53:58.84#ibcon#enter sib2, iclass 7, count 0 2006.253.07:53:58.84#ibcon#flushed, iclass 7, count 0 2006.253.07:53:58.84#ibcon#about to write, iclass 7, count 0 2006.253.07:53:58.84#ibcon#wrote, iclass 7, count 0 2006.253.07:53:58.84#ibcon#about to read 3, iclass 7, count 0 2006.253.07:53:58.86#ibcon#read 3, iclass 7, count 0 2006.253.07:53:58.86#ibcon#about to read 4, iclass 7, count 0 2006.253.07:53:58.86#ibcon#read 4, iclass 7, count 0 2006.253.07:53:58.86#ibcon#about to read 5, iclass 7, count 0 2006.253.07:53:58.86#ibcon#read 5, iclass 7, count 0 2006.253.07:53:58.86#ibcon#about to read 6, iclass 7, count 0 2006.253.07:53:58.86#ibcon#read 6, iclass 7, count 0 2006.253.07:53:58.86#ibcon#end of sib2, iclass 7, count 0 2006.253.07:53:58.86#ibcon#*mode == 0, iclass 7, count 0 2006.253.07:53:58.86#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.253.07:53:58.86#ibcon#[25=USB\r\n] 2006.253.07:53:58.86#ibcon#*before write, iclass 7, count 0 2006.253.07:53:58.86#ibcon#enter sib2, iclass 7, count 0 2006.253.07:53:58.86#ibcon#flushed, iclass 7, count 0 2006.253.07:53:58.86#ibcon#about to write, iclass 7, count 0 2006.253.07:53:58.86#ibcon#wrote, iclass 7, count 0 2006.253.07:53:58.86#ibcon#about to read 3, iclass 7, count 0 2006.253.07:53:58.89#ibcon#read 3, iclass 7, count 0 2006.253.07:53:58.89#ibcon#about to read 4, iclass 7, count 0 2006.253.07:53:58.89#ibcon#read 4, iclass 7, count 0 2006.253.07:53:58.89#ibcon#about to read 5, iclass 7, count 0 2006.253.07:53:58.89#ibcon#read 5, iclass 7, count 0 2006.253.07:53:58.89#ibcon#about to read 6, iclass 7, count 0 2006.253.07:53:58.89#ibcon#read 6, iclass 7, count 0 2006.253.07:53:58.89#ibcon#end of sib2, iclass 7, count 0 2006.253.07:53:58.89#ibcon#*after write, iclass 7, count 0 2006.253.07:53:58.89#ibcon#*before return 0, iclass 7, count 0 2006.253.07:53:58.89#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.253.07:53:58.89#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.253.07:53:58.89#ibcon#about to clear, iclass 7 cls_cnt 0 2006.253.07:53:58.89#ibcon#cleared, iclass 7 cls_cnt 0 2006.253.07:53:58.89$vc4f8/valo=4,832.99 2006.253.07:53:58.89#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.253.07:53:58.89#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.253.07:53:58.89#ibcon#ireg 17 cls_cnt 0 2006.253.07:53:58.89#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.253.07:53:58.89#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.253.07:53:58.89#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.253.07:53:58.89#ibcon#enter wrdev, iclass 11, count 0 2006.253.07:53:58.89#ibcon#first serial, iclass 11, count 0 2006.253.07:53:58.89#ibcon#enter sib2, iclass 11, count 0 2006.253.07:53:58.89#ibcon#flushed, iclass 11, count 0 2006.253.07:53:58.89#ibcon#about to write, iclass 11, count 0 2006.253.07:53:58.89#ibcon#wrote, iclass 11, count 0 2006.253.07:53:58.89#ibcon#about to read 3, iclass 11, count 0 2006.253.07:53:58.91#ibcon#read 3, iclass 11, count 0 2006.253.07:53:58.91#ibcon#about to read 4, iclass 11, count 0 2006.253.07:53:58.91#ibcon#read 4, iclass 11, count 0 2006.253.07:53:58.91#ibcon#about to read 5, iclass 11, count 0 2006.253.07:53:58.91#ibcon#read 5, iclass 11, count 0 2006.253.07:53:58.91#ibcon#about to read 6, iclass 11, count 0 2006.253.07:53:58.91#ibcon#read 6, iclass 11, count 0 2006.253.07:53:58.91#ibcon#end of sib2, iclass 11, count 0 2006.253.07:53:58.91#ibcon#*mode == 0, iclass 11, count 0 2006.253.07:53:58.91#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.253.07:53:58.91#ibcon#[26=FRQ=04,832.99\r\n] 2006.253.07:53:58.91#ibcon#*before write, iclass 11, count 0 2006.253.07:53:58.91#ibcon#enter sib2, iclass 11, count 0 2006.253.07:53:58.91#ibcon#flushed, iclass 11, count 0 2006.253.07:53:58.91#ibcon#about to write, iclass 11, count 0 2006.253.07:53:58.91#ibcon#wrote, iclass 11, count 0 2006.253.07:53:58.91#ibcon#about to read 3, iclass 11, count 0 2006.253.07:53:58.95#ibcon#read 3, iclass 11, count 0 2006.253.07:53:58.95#ibcon#about to read 4, iclass 11, count 0 2006.253.07:53:58.95#ibcon#read 4, iclass 11, count 0 2006.253.07:53:58.95#ibcon#about to read 5, iclass 11, count 0 2006.253.07:53:58.95#ibcon#read 5, iclass 11, count 0 2006.253.07:53:58.95#ibcon#about to read 6, iclass 11, count 0 2006.253.07:53:58.95#ibcon#read 6, iclass 11, count 0 2006.253.07:53:58.95#ibcon#end of sib2, iclass 11, count 0 2006.253.07:53:58.95#ibcon#*after write, iclass 11, count 0 2006.253.07:53:58.95#ibcon#*before return 0, iclass 11, count 0 2006.253.07:53:58.95#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.253.07:53:58.95#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.253.07:53:58.95#ibcon#about to clear, iclass 11 cls_cnt 0 2006.253.07:53:58.95#ibcon#cleared, iclass 11 cls_cnt 0 2006.253.07:53:58.95$vc4f8/va=4,7 2006.253.07:53:58.95#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.253.07:53:58.95#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.253.07:53:58.95#ibcon#ireg 11 cls_cnt 2 2006.253.07:53:58.95#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.253.07:53:59.01#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.253.07:53:59.01#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.253.07:53:59.01#ibcon#enter wrdev, iclass 13, count 2 2006.253.07:53:59.01#ibcon#first serial, iclass 13, count 2 2006.253.07:53:59.01#ibcon#enter sib2, iclass 13, count 2 2006.253.07:53:59.01#ibcon#flushed, iclass 13, count 2 2006.253.07:53:59.01#ibcon#about to write, iclass 13, count 2 2006.253.07:53:59.01#ibcon#wrote, iclass 13, count 2 2006.253.07:53:59.01#ibcon#about to read 3, iclass 13, count 2 2006.253.07:53:59.03#ibcon#read 3, iclass 13, count 2 2006.253.07:53:59.03#ibcon#about to read 4, iclass 13, count 2 2006.253.07:53:59.03#ibcon#read 4, iclass 13, count 2 2006.253.07:53:59.03#ibcon#about to read 5, iclass 13, count 2 2006.253.07:53:59.03#ibcon#read 5, iclass 13, count 2 2006.253.07:53:59.03#ibcon#about to read 6, iclass 13, count 2 2006.253.07:53:59.03#ibcon#read 6, iclass 13, count 2 2006.253.07:53:59.03#ibcon#end of sib2, iclass 13, count 2 2006.253.07:53:59.03#ibcon#*mode == 0, iclass 13, count 2 2006.253.07:53:59.03#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.253.07:53:59.03#ibcon#[25=AT04-07\r\n] 2006.253.07:53:59.03#ibcon#*before write, iclass 13, count 2 2006.253.07:53:59.03#ibcon#enter sib2, iclass 13, count 2 2006.253.07:53:59.03#ibcon#flushed, iclass 13, count 2 2006.253.07:53:59.03#ibcon#about to write, iclass 13, count 2 2006.253.07:53:59.03#ibcon#wrote, iclass 13, count 2 2006.253.07:53:59.03#ibcon#about to read 3, iclass 13, count 2 2006.253.07:53:59.06#ibcon#read 3, iclass 13, count 2 2006.253.07:53:59.06#ibcon#about to read 4, iclass 13, count 2 2006.253.07:53:59.06#ibcon#read 4, iclass 13, count 2 2006.253.07:53:59.06#ibcon#about to read 5, iclass 13, count 2 2006.253.07:53:59.06#ibcon#read 5, iclass 13, count 2 2006.253.07:53:59.06#ibcon#about to read 6, iclass 13, count 2 2006.253.07:53:59.06#ibcon#read 6, iclass 13, count 2 2006.253.07:53:59.06#ibcon#end of sib2, iclass 13, count 2 2006.253.07:53:59.06#ibcon#*after write, iclass 13, count 2 2006.253.07:53:59.06#ibcon#*before return 0, iclass 13, count 2 2006.253.07:53:59.06#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.253.07:53:59.06#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.253.07:53:59.06#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.253.07:53:59.06#ibcon#ireg 7 cls_cnt 0 2006.253.07:53:59.06#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.253.07:53:59.18#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.253.07:53:59.18#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.253.07:53:59.18#ibcon#enter wrdev, iclass 13, count 0 2006.253.07:53:59.18#ibcon#first serial, iclass 13, count 0 2006.253.07:53:59.18#ibcon#enter sib2, iclass 13, count 0 2006.253.07:53:59.18#ibcon#flushed, iclass 13, count 0 2006.253.07:53:59.18#ibcon#about to write, iclass 13, count 0 2006.253.07:53:59.18#ibcon#wrote, iclass 13, count 0 2006.253.07:53:59.18#ibcon#about to read 3, iclass 13, count 0 2006.253.07:53:59.20#ibcon#read 3, iclass 13, count 0 2006.253.07:53:59.20#ibcon#about to read 4, iclass 13, count 0 2006.253.07:53:59.20#ibcon#read 4, iclass 13, count 0 2006.253.07:53:59.20#ibcon#about to read 5, iclass 13, count 0 2006.253.07:53:59.20#ibcon#read 5, iclass 13, count 0 2006.253.07:53:59.20#ibcon#about to read 6, iclass 13, count 0 2006.253.07:53:59.20#ibcon#read 6, iclass 13, count 0 2006.253.07:53:59.20#ibcon#end of sib2, iclass 13, count 0 2006.253.07:53:59.20#ibcon#*mode == 0, iclass 13, count 0 2006.253.07:53:59.20#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.253.07:53:59.20#ibcon#[25=USB\r\n] 2006.253.07:53:59.20#ibcon#*before write, iclass 13, count 0 2006.253.07:53:59.20#ibcon#enter sib2, iclass 13, count 0 2006.253.07:53:59.20#ibcon#flushed, iclass 13, count 0 2006.253.07:53:59.20#ibcon#about to write, iclass 13, count 0 2006.253.07:53:59.20#ibcon#wrote, iclass 13, count 0 2006.253.07:53:59.20#ibcon#about to read 3, iclass 13, count 0 2006.253.07:53:59.23#ibcon#read 3, iclass 13, count 0 2006.253.07:53:59.23#ibcon#about to read 4, iclass 13, count 0 2006.253.07:53:59.23#ibcon#read 4, iclass 13, count 0 2006.253.07:53:59.23#ibcon#about to read 5, iclass 13, count 0 2006.253.07:53:59.23#ibcon#read 5, iclass 13, count 0 2006.253.07:53:59.23#ibcon#about to read 6, iclass 13, count 0 2006.253.07:53:59.23#ibcon#read 6, iclass 13, count 0 2006.253.07:53:59.23#ibcon#end of sib2, iclass 13, count 0 2006.253.07:53:59.23#ibcon#*after write, iclass 13, count 0 2006.253.07:53:59.23#ibcon#*before return 0, iclass 13, count 0 2006.253.07:53:59.23#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.253.07:53:59.23#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.253.07:53:59.23#ibcon#about to clear, iclass 13 cls_cnt 0 2006.253.07:53:59.23#ibcon#cleared, iclass 13 cls_cnt 0 2006.253.07:53:59.23$vc4f8/valo=5,652.99 2006.253.07:53:59.23#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.253.07:53:59.23#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.253.07:53:59.23#ibcon#ireg 17 cls_cnt 0 2006.253.07:53:59.23#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.253.07:53:59.23#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.253.07:53:59.23#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.253.07:53:59.23#ibcon#enter wrdev, iclass 15, count 0 2006.253.07:53:59.23#ibcon#first serial, iclass 15, count 0 2006.253.07:53:59.23#ibcon#enter sib2, iclass 15, count 0 2006.253.07:53:59.23#ibcon#flushed, iclass 15, count 0 2006.253.07:53:59.23#ibcon#about to write, iclass 15, count 0 2006.253.07:53:59.23#ibcon#wrote, iclass 15, count 0 2006.253.07:53:59.23#ibcon#about to read 3, iclass 15, count 0 2006.253.07:53:59.25#ibcon#read 3, iclass 15, count 0 2006.253.07:53:59.25#ibcon#about to read 4, iclass 15, count 0 2006.253.07:53:59.25#ibcon#read 4, iclass 15, count 0 2006.253.07:53:59.25#ibcon#about to read 5, iclass 15, count 0 2006.253.07:53:59.25#ibcon#read 5, iclass 15, count 0 2006.253.07:53:59.25#ibcon#about to read 6, iclass 15, count 0 2006.253.07:53:59.25#ibcon#read 6, iclass 15, count 0 2006.253.07:53:59.25#ibcon#end of sib2, iclass 15, count 0 2006.253.07:53:59.25#ibcon#*mode == 0, iclass 15, count 0 2006.253.07:53:59.25#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.253.07:53:59.25#ibcon#[26=FRQ=05,652.99\r\n] 2006.253.07:53:59.25#ibcon#*before write, iclass 15, count 0 2006.253.07:53:59.25#ibcon#enter sib2, iclass 15, count 0 2006.253.07:53:59.25#ibcon#flushed, iclass 15, count 0 2006.253.07:53:59.25#ibcon#about to write, iclass 15, count 0 2006.253.07:53:59.25#ibcon#wrote, iclass 15, count 0 2006.253.07:53:59.25#ibcon#about to read 3, iclass 15, count 0 2006.253.07:53:59.29#ibcon#read 3, iclass 15, count 0 2006.253.07:53:59.29#ibcon#about to read 4, iclass 15, count 0 2006.253.07:53:59.29#ibcon#read 4, iclass 15, count 0 2006.253.07:53:59.29#ibcon#about to read 5, iclass 15, count 0 2006.253.07:53:59.29#ibcon#read 5, iclass 15, count 0 2006.253.07:53:59.29#ibcon#about to read 6, iclass 15, count 0 2006.253.07:53:59.29#ibcon#read 6, iclass 15, count 0 2006.253.07:53:59.29#ibcon#end of sib2, iclass 15, count 0 2006.253.07:53:59.29#ibcon#*after write, iclass 15, count 0 2006.253.07:53:59.29#ibcon#*before return 0, iclass 15, count 0 2006.253.07:53:59.29#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.253.07:53:59.29#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.253.07:53:59.29#ibcon#about to clear, iclass 15 cls_cnt 0 2006.253.07:53:59.29#ibcon#cleared, iclass 15 cls_cnt 0 2006.253.07:53:59.29$vc4f8/va=5,7 2006.253.07:53:59.29#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.253.07:53:59.29#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.253.07:53:59.29#ibcon#ireg 11 cls_cnt 2 2006.253.07:53:59.29#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.253.07:53:59.35#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.253.07:53:59.35#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.253.07:53:59.35#ibcon#enter wrdev, iclass 17, count 2 2006.253.07:53:59.35#ibcon#first serial, iclass 17, count 2 2006.253.07:53:59.35#ibcon#enter sib2, iclass 17, count 2 2006.253.07:53:59.35#ibcon#flushed, iclass 17, count 2 2006.253.07:53:59.35#ibcon#about to write, iclass 17, count 2 2006.253.07:53:59.35#ibcon#wrote, iclass 17, count 2 2006.253.07:53:59.35#ibcon#about to read 3, iclass 17, count 2 2006.253.07:53:59.37#ibcon#read 3, iclass 17, count 2 2006.253.07:53:59.37#ibcon#about to read 4, iclass 17, count 2 2006.253.07:53:59.37#ibcon#read 4, iclass 17, count 2 2006.253.07:53:59.37#ibcon#about to read 5, iclass 17, count 2 2006.253.07:53:59.37#ibcon#read 5, iclass 17, count 2 2006.253.07:53:59.37#ibcon#about to read 6, iclass 17, count 2 2006.253.07:53:59.37#ibcon#read 6, iclass 17, count 2 2006.253.07:53:59.37#ibcon#end of sib2, iclass 17, count 2 2006.253.07:53:59.37#ibcon#*mode == 0, iclass 17, count 2 2006.253.07:53:59.37#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.253.07:53:59.37#ibcon#[25=AT05-07\r\n] 2006.253.07:53:59.37#ibcon#*before write, iclass 17, count 2 2006.253.07:53:59.37#ibcon#enter sib2, iclass 17, count 2 2006.253.07:53:59.37#ibcon#flushed, iclass 17, count 2 2006.253.07:53:59.37#ibcon#about to write, iclass 17, count 2 2006.253.07:53:59.37#ibcon#wrote, iclass 17, count 2 2006.253.07:53:59.37#ibcon#about to read 3, iclass 17, count 2 2006.253.07:53:59.40#ibcon#read 3, iclass 17, count 2 2006.253.07:53:59.40#ibcon#about to read 4, iclass 17, count 2 2006.253.07:53:59.40#ibcon#read 4, iclass 17, count 2 2006.253.07:53:59.40#ibcon#about to read 5, iclass 17, count 2 2006.253.07:53:59.40#ibcon#read 5, iclass 17, count 2 2006.253.07:53:59.40#ibcon#about to read 6, iclass 17, count 2 2006.253.07:53:59.40#ibcon#read 6, iclass 17, count 2 2006.253.07:53:59.40#ibcon#end of sib2, iclass 17, count 2 2006.253.07:53:59.40#ibcon#*after write, iclass 17, count 2 2006.253.07:53:59.40#ibcon#*before return 0, iclass 17, count 2 2006.253.07:53:59.40#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.253.07:53:59.40#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.253.07:53:59.40#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.253.07:53:59.40#ibcon#ireg 7 cls_cnt 0 2006.253.07:53:59.40#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.253.07:53:59.52#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.253.07:53:59.52#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.253.07:53:59.52#ibcon#enter wrdev, iclass 17, count 0 2006.253.07:53:59.52#ibcon#first serial, iclass 17, count 0 2006.253.07:53:59.52#ibcon#enter sib2, iclass 17, count 0 2006.253.07:53:59.52#ibcon#flushed, iclass 17, count 0 2006.253.07:53:59.52#ibcon#about to write, iclass 17, count 0 2006.253.07:53:59.52#ibcon#wrote, iclass 17, count 0 2006.253.07:53:59.52#ibcon#about to read 3, iclass 17, count 0 2006.253.07:53:59.54#ibcon#read 3, iclass 17, count 0 2006.253.07:53:59.54#ibcon#about to read 4, iclass 17, count 0 2006.253.07:53:59.54#ibcon#read 4, iclass 17, count 0 2006.253.07:53:59.54#ibcon#about to read 5, iclass 17, count 0 2006.253.07:53:59.54#ibcon#read 5, iclass 17, count 0 2006.253.07:53:59.54#ibcon#about to read 6, iclass 17, count 0 2006.253.07:53:59.54#ibcon#read 6, iclass 17, count 0 2006.253.07:53:59.54#ibcon#end of sib2, iclass 17, count 0 2006.253.07:53:59.54#ibcon#*mode == 0, iclass 17, count 0 2006.253.07:53:59.54#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.253.07:53:59.54#ibcon#[25=USB\r\n] 2006.253.07:53:59.54#ibcon#*before write, iclass 17, count 0 2006.253.07:53:59.54#ibcon#enter sib2, iclass 17, count 0 2006.253.07:53:59.54#ibcon#flushed, iclass 17, count 0 2006.253.07:53:59.54#ibcon#about to write, iclass 17, count 0 2006.253.07:53:59.54#ibcon#wrote, iclass 17, count 0 2006.253.07:53:59.54#ibcon#about to read 3, iclass 17, count 0 2006.253.07:53:59.57#ibcon#read 3, iclass 17, count 0 2006.253.07:53:59.57#ibcon#about to read 4, iclass 17, count 0 2006.253.07:53:59.57#ibcon#read 4, iclass 17, count 0 2006.253.07:53:59.57#ibcon#about to read 5, iclass 17, count 0 2006.253.07:53:59.57#ibcon#read 5, iclass 17, count 0 2006.253.07:53:59.57#ibcon#about to read 6, iclass 17, count 0 2006.253.07:53:59.57#ibcon#read 6, iclass 17, count 0 2006.253.07:53:59.57#ibcon#end of sib2, iclass 17, count 0 2006.253.07:53:59.57#ibcon#*after write, iclass 17, count 0 2006.253.07:53:59.57#ibcon#*before return 0, iclass 17, count 0 2006.253.07:53:59.57#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.253.07:53:59.57#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.253.07:53:59.57#ibcon#about to clear, iclass 17 cls_cnt 0 2006.253.07:53:59.57#ibcon#cleared, iclass 17 cls_cnt 0 2006.253.07:53:59.57$vc4f8/valo=6,772.99 2006.253.07:53:59.57#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.253.07:53:59.57#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.253.07:53:59.57#ibcon#ireg 17 cls_cnt 0 2006.253.07:53:59.57#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.253.07:53:59.57#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.253.07:53:59.57#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.253.07:53:59.57#ibcon#enter wrdev, iclass 19, count 0 2006.253.07:53:59.57#ibcon#first serial, iclass 19, count 0 2006.253.07:53:59.57#ibcon#enter sib2, iclass 19, count 0 2006.253.07:53:59.57#ibcon#flushed, iclass 19, count 0 2006.253.07:53:59.57#ibcon#about to write, iclass 19, count 0 2006.253.07:53:59.57#ibcon#wrote, iclass 19, count 0 2006.253.07:53:59.57#ibcon#about to read 3, iclass 19, count 0 2006.253.07:53:59.59#ibcon#read 3, iclass 19, count 0 2006.253.07:53:59.59#ibcon#about to read 4, iclass 19, count 0 2006.253.07:53:59.59#ibcon#read 4, iclass 19, count 0 2006.253.07:53:59.59#ibcon#about to read 5, iclass 19, count 0 2006.253.07:53:59.59#ibcon#read 5, iclass 19, count 0 2006.253.07:53:59.59#ibcon#about to read 6, iclass 19, count 0 2006.253.07:53:59.59#ibcon#read 6, iclass 19, count 0 2006.253.07:53:59.59#ibcon#end of sib2, iclass 19, count 0 2006.253.07:53:59.59#ibcon#*mode == 0, iclass 19, count 0 2006.253.07:53:59.59#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.253.07:53:59.59#ibcon#[26=FRQ=06,772.99\r\n] 2006.253.07:53:59.59#ibcon#*before write, iclass 19, count 0 2006.253.07:53:59.59#ibcon#enter sib2, iclass 19, count 0 2006.253.07:53:59.59#ibcon#flushed, iclass 19, count 0 2006.253.07:53:59.59#ibcon#about to write, iclass 19, count 0 2006.253.07:53:59.59#ibcon#wrote, iclass 19, count 0 2006.253.07:53:59.59#ibcon#about to read 3, iclass 19, count 0 2006.253.07:53:59.63#ibcon#read 3, iclass 19, count 0 2006.253.07:53:59.63#ibcon#about to read 4, iclass 19, count 0 2006.253.07:53:59.63#ibcon#read 4, iclass 19, count 0 2006.253.07:53:59.63#ibcon#about to read 5, iclass 19, count 0 2006.253.07:53:59.63#ibcon#read 5, iclass 19, count 0 2006.253.07:53:59.63#ibcon#about to read 6, iclass 19, count 0 2006.253.07:53:59.63#ibcon#read 6, iclass 19, count 0 2006.253.07:53:59.63#ibcon#end of sib2, iclass 19, count 0 2006.253.07:53:59.63#ibcon#*after write, iclass 19, count 0 2006.253.07:53:59.63#ibcon#*before return 0, iclass 19, count 0 2006.253.07:53:59.63#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.253.07:53:59.63#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.253.07:53:59.63#ibcon#about to clear, iclass 19 cls_cnt 0 2006.253.07:53:59.63#ibcon#cleared, iclass 19 cls_cnt 0 2006.253.07:53:59.63$vc4f8/va=6,7 2006.253.07:53:59.63#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.253.07:53:59.63#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.253.07:53:59.63#ibcon#ireg 11 cls_cnt 2 2006.253.07:53:59.63#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.253.07:53:59.69#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.253.07:53:59.69#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.253.07:53:59.69#ibcon#enter wrdev, iclass 21, count 2 2006.253.07:53:59.69#ibcon#first serial, iclass 21, count 2 2006.253.07:53:59.69#ibcon#enter sib2, iclass 21, count 2 2006.253.07:53:59.69#ibcon#flushed, iclass 21, count 2 2006.253.07:53:59.69#ibcon#about to write, iclass 21, count 2 2006.253.07:53:59.69#ibcon#wrote, iclass 21, count 2 2006.253.07:53:59.69#ibcon#about to read 3, iclass 21, count 2 2006.253.07:53:59.71#ibcon#read 3, iclass 21, count 2 2006.253.07:53:59.71#ibcon#about to read 4, iclass 21, count 2 2006.253.07:53:59.71#ibcon#read 4, iclass 21, count 2 2006.253.07:53:59.71#ibcon#about to read 5, iclass 21, count 2 2006.253.07:53:59.71#ibcon#read 5, iclass 21, count 2 2006.253.07:53:59.71#ibcon#about to read 6, iclass 21, count 2 2006.253.07:53:59.71#ibcon#read 6, iclass 21, count 2 2006.253.07:53:59.71#ibcon#end of sib2, iclass 21, count 2 2006.253.07:53:59.71#ibcon#*mode == 0, iclass 21, count 2 2006.253.07:53:59.71#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.253.07:53:59.71#ibcon#[25=AT06-07\r\n] 2006.253.07:53:59.71#ibcon#*before write, iclass 21, count 2 2006.253.07:53:59.71#ibcon#enter sib2, iclass 21, count 2 2006.253.07:53:59.71#ibcon#flushed, iclass 21, count 2 2006.253.07:53:59.71#ibcon#about to write, iclass 21, count 2 2006.253.07:53:59.71#ibcon#wrote, iclass 21, count 2 2006.253.07:53:59.71#ibcon#about to read 3, iclass 21, count 2 2006.253.07:53:59.74#ibcon#read 3, iclass 21, count 2 2006.253.07:53:59.74#ibcon#about to read 4, iclass 21, count 2 2006.253.07:53:59.74#ibcon#read 4, iclass 21, count 2 2006.253.07:53:59.74#ibcon#about to read 5, iclass 21, count 2 2006.253.07:53:59.74#ibcon#read 5, iclass 21, count 2 2006.253.07:53:59.74#ibcon#about to read 6, iclass 21, count 2 2006.253.07:53:59.74#ibcon#read 6, iclass 21, count 2 2006.253.07:53:59.74#ibcon#end of sib2, iclass 21, count 2 2006.253.07:53:59.74#ibcon#*after write, iclass 21, count 2 2006.253.07:53:59.74#ibcon#*before return 0, iclass 21, count 2 2006.253.07:53:59.74#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.253.07:53:59.74#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.253.07:53:59.74#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.253.07:53:59.74#ibcon#ireg 7 cls_cnt 0 2006.253.07:53:59.74#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.253.07:53:59.86#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.253.07:53:59.86#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.253.07:53:59.86#ibcon#enter wrdev, iclass 21, count 0 2006.253.07:53:59.86#ibcon#first serial, iclass 21, count 0 2006.253.07:53:59.86#ibcon#enter sib2, iclass 21, count 0 2006.253.07:53:59.86#ibcon#flushed, iclass 21, count 0 2006.253.07:53:59.86#ibcon#about to write, iclass 21, count 0 2006.253.07:53:59.86#ibcon#wrote, iclass 21, count 0 2006.253.07:53:59.86#ibcon#about to read 3, iclass 21, count 0 2006.253.07:53:59.88#ibcon#read 3, iclass 21, count 0 2006.253.07:53:59.88#ibcon#about to read 4, iclass 21, count 0 2006.253.07:53:59.88#ibcon#read 4, iclass 21, count 0 2006.253.07:53:59.88#ibcon#about to read 5, iclass 21, count 0 2006.253.07:53:59.88#ibcon#read 5, iclass 21, count 0 2006.253.07:53:59.88#ibcon#about to read 6, iclass 21, count 0 2006.253.07:53:59.88#ibcon#read 6, iclass 21, count 0 2006.253.07:53:59.88#ibcon#end of sib2, iclass 21, count 0 2006.253.07:53:59.88#ibcon#*mode == 0, iclass 21, count 0 2006.253.07:53:59.88#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.253.07:53:59.88#ibcon#[25=USB\r\n] 2006.253.07:53:59.88#ibcon#*before write, iclass 21, count 0 2006.253.07:53:59.88#ibcon#enter sib2, iclass 21, count 0 2006.253.07:53:59.88#ibcon#flushed, iclass 21, count 0 2006.253.07:53:59.88#ibcon#about to write, iclass 21, count 0 2006.253.07:53:59.88#ibcon#wrote, iclass 21, count 0 2006.253.07:53:59.88#ibcon#about to read 3, iclass 21, count 0 2006.253.07:53:59.91#ibcon#read 3, iclass 21, count 0 2006.253.07:53:59.91#ibcon#about to read 4, iclass 21, count 0 2006.253.07:53:59.91#ibcon#read 4, iclass 21, count 0 2006.253.07:53:59.91#ibcon#about to read 5, iclass 21, count 0 2006.253.07:53:59.91#ibcon#read 5, iclass 21, count 0 2006.253.07:53:59.91#ibcon#about to read 6, iclass 21, count 0 2006.253.07:53:59.91#ibcon#read 6, iclass 21, count 0 2006.253.07:53:59.91#ibcon#end of sib2, iclass 21, count 0 2006.253.07:53:59.91#ibcon#*after write, iclass 21, count 0 2006.253.07:53:59.91#ibcon#*before return 0, iclass 21, count 0 2006.253.07:53:59.91#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.253.07:53:59.91#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.253.07:53:59.91#ibcon#about to clear, iclass 21 cls_cnt 0 2006.253.07:53:59.91#ibcon#cleared, iclass 21 cls_cnt 0 2006.253.07:53:59.91$vc4f8/valo=7,832.99 2006.253.07:53:59.91#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.253.07:53:59.91#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.253.07:53:59.91#ibcon#ireg 17 cls_cnt 0 2006.253.07:53:59.91#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.253.07:53:59.91#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.253.07:53:59.91#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.253.07:53:59.91#ibcon#enter wrdev, iclass 23, count 0 2006.253.07:53:59.91#ibcon#first serial, iclass 23, count 0 2006.253.07:53:59.91#ibcon#enter sib2, iclass 23, count 0 2006.253.07:53:59.91#ibcon#flushed, iclass 23, count 0 2006.253.07:53:59.91#ibcon#about to write, iclass 23, count 0 2006.253.07:53:59.91#ibcon#wrote, iclass 23, count 0 2006.253.07:53:59.91#ibcon#about to read 3, iclass 23, count 0 2006.253.07:53:59.93#ibcon#read 3, iclass 23, count 0 2006.253.07:53:59.93#ibcon#about to read 4, iclass 23, count 0 2006.253.07:53:59.93#ibcon#read 4, iclass 23, count 0 2006.253.07:53:59.93#ibcon#about to read 5, iclass 23, count 0 2006.253.07:53:59.93#ibcon#read 5, iclass 23, count 0 2006.253.07:53:59.93#ibcon#about to read 6, iclass 23, count 0 2006.253.07:53:59.93#ibcon#read 6, iclass 23, count 0 2006.253.07:53:59.93#ibcon#end of sib2, iclass 23, count 0 2006.253.07:53:59.93#ibcon#*mode == 0, iclass 23, count 0 2006.253.07:53:59.93#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.253.07:53:59.93#ibcon#[26=FRQ=07,832.99\r\n] 2006.253.07:53:59.93#ibcon#*before write, iclass 23, count 0 2006.253.07:53:59.93#ibcon#enter sib2, iclass 23, count 0 2006.253.07:53:59.93#ibcon#flushed, iclass 23, count 0 2006.253.07:53:59.93#ibcon#about to write, iclass 23, count 0 2006.253.07:53:59.93#ibcon#wrote, iclass 23, count 0 2006.253.07:53:59.93#ibcon#about to read 3, iclass 23, count 0 2006.253.07:53:59.97#ibcon#read 3, iclass 23, count 0 2006.253.07:53:59.97#ibcon#about to read 4, iclass 23, count 0 2006.253.07:53:59.97#ibcon#read 4, iclass 23, count 0 2006.253.07:53:59.97#ibcon#about to read 5, iclass 23, count 0 2006.253.07:53:59.97#ibcon#read 5, iclass 23, count 0 2006.253.07:53:59.97#ibcon#about to read 6, iclass 23, count 0 2006.253.07:53:59.97#ibcon#read 6, iclass 23, count 0 2006.253.07:53:59.97#ibcon#end of sib2, iclass 23, count 0 2006.253.07:53:59.97#ibcon#*after write, iclass 23, count 0 2006.253.07:53:59.97#ibcon#*before return 0, iclass 23, count 0 2006.253.07:53:59.97#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.253.07:53:59.97#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.253.07:53:59.97#ibcon#about to clear, iclass 23 cls_cnt 0 2006.253.07:53:59.97#ibcon#cleared, iclass 23 cls_cnt 0 2006.253.07:53:59.97$vc4f8/va=7,7 2006.253.07:53:59.97#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.253.07:53:59.97#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.253.07:53:59.97#ibcon#ireg 11 cls_cnt 2 2006.253.07:53:59.97#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.253.07:54:00.03#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.253.07:54:00.03#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.253.07:54:00.03#ibcon#enter wrdev, iclass 25, count 2 2006.253.07:54:00.03#ibcon#first serial, iclass 25, count 2 2006.253.07:54:00.03#ibcon#enter sib2, iclass 25, count 2 2006.253.07:54:00.03#ibcon#flushed, iclass 25, count 2 2006.253.07:54:00.03#ibcon#about to write, iclass 25, count 2 2006.253.07:54:00.03#ibcon#wrote, iclass 25, count 2 2006.253.07:54:00.03#ibcon#about to read 3, iclass 25, count 2 2006.253.07:54:00.05#ibcon#read 3, iclass 25, count 2 2006.253.07:54:00.05#ibcon#about to read 4, iclass 25, count 2 2006.253.07:54:00.05#ibcon#read 4, iclass 25, count 2 2006.253.07:54:00.05#ibcon#about to read 5, iclass 25, count 2 2006.253.07:54:00.05#ibcon#read 5, iclass 25, count 2 2006.253.07:54:00.05#ibcon#about to read 6, iclass 25, count 2 2006.253.07:54:00.05#ibcon#read 6, iclass 25, count 2 2006.253.07:54:00.05#ibcon#end of sib2, iclass 25, count 2 2006.253.07:54:00.05#ibcon#*mode == 0, iclass 25, count 2 2006.253.07:54:00.05#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.253.07:54:00.05#ibcon#[25=AT07-07\r\n] 2006.253.07:54:00.05#ibcon#*before write, iclass 25, count 2 2006.253.07:54:00.05#ibcon#enter sib2, iclass 25, count 2 2006.253.07:54:00.05#ibcon#flushed, iclass 25, count 2 2006.253.07:54:00.05#ibcon#about to write, iclass 25, count 2 2006.253.07:54:00.05#ibcon#wrote, iclass 25, count 2 2006.253.07:54:00.05#ibcon#about to read 3, iclass 25, count 2 2006.253.07:54:00.08#ibcon#read 3, iclass 25, count 2 2006.253.07:54:00.08#ibcon#about to read 4, iclass 25, count 2 2006.253.07:54:00.08#ibcon#read 4, iclass 25, count 2 2006.253.07:54:00.08#ibcon#about to read 5, iclass 25, count 2 2006.253.07:54:00.08#ibcon#read 5, iclass 25, count 2 2006.253.07:54:00.08#ibcon#about to read 6, iclass 25, count 2 2006.253.07:54:00.08#ibcon#read 6, iclass 25, count 2 2006.253.07:54:00.08#ibcon#end of sib2, iclass 25, count 2 2006.253.07:54:00.08#ibcon#*after write, iclass 25, count 2 2006.253.07:54:00.08#ibcon#*before return 0, iclass 25, count 2 2006.253.07:54:00.08#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.253.07:54:00.08#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.253.07:54:00.08#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.253.07:54:00.08#ibcon#ireg 7 cls_cnt 0 2006.253.07:54:00.08#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.253.07:54:00.20#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.253.07:54:00.20#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.253.07:54:00.20#ibcon#enter wrdev, iclass 25, count 0 2006.253.07:54:00.20#ibcon#first serial, iclass 25, count 0 2006.253.07:54:00.20#ibcon#enter sib2, iclass 25, count 0 2006.253.07:54:00.20#ibcon#flushed, iclass 25, count 0 2006.253.07:54:00.20#ibcon#about to write, iclass 25, count 0 2006.253.07:54:00.20#ibcon#wrote, iclass 25, count 0 2006.253.07:54:00.20#ibcon#about to read 3, iclass 25, count 0 2006.253.07:54:00.24#ibcon#read 3, iclass 25, count 0 2006.253.07:54:00.24#ibcon#about to read 4, iclass 25, count 0 2006.253.07:54:00.24#ibcon#read 4, iclass 25, count 0 2006.253.07:54:00.24#ibcon#about to read 5, iclass 25, count 0 2006.253.07:54:00.24#ibcon#read 5, iclass 25, count 0 2006.253.07:54:00.24#ibcon#about to read 6, iclass 25, count 0 2006.253.07:54:00.24#ibcon#read 6, iclass 25, count 0 2006.253.07:54:00.24#ibcon#end of sib2, iclass 25, count 0 2006.253.07:54:00.24#ibcon#*mode == 0, iclass 25, count 0 2006.253.07:54:00.24#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.253.07:54:00.24#ibcon#[25=USB\r\n] 2006.253.07:54:00.24#ibcon#*before write, iclass 25, count 0 2006.253.07:54:00.24#ibcon#enter sib2, iclass 25, count 0 2006.253.07:54:00.24#ibcon#flushed, iclass 25, count 0 2006.253.07:54:00.24#ibcon#about to write, iclass 25, count 0 2006.253.07:54:00.24#ibcon#wrote, iclass 25, count 0 2006.253.07:54:00.24#ibcon#about to read 3, iclass 25, count 0 2006.253.07:54:00.26#ibcon#read 3, iclass 25, count 0 2006.253.07:54:00.26#ibcon#about to read 4, iclass 25, count 0 2006.253.07:54:00.26#ibcon#read 4, iclass 25, count 0 2006.253.07:54:00.26#ibcon#about to read 5, iclass 25, count 0 2006.253.07:54:00.26#ibcon#read 5, iclass 25, count 0 2006.253.07:54:00.26#ibcon#about to read 6, iclass 25, count 0 2006.253.07:54:00.26#ibcon#read 6, iclass 25, count 0 2006.253.07:54:00.26#ibcon#end of sib2, iclass 25, count 0 2006.253.07:54:00.26#ibcon#*after write, iclass 25, count 0 2006.253.07:54:00.26#ibcon#*before return 0, iclass 25, count 0 2006.253.07:54:00.26#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.253.07:54:00.26#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.253.07:54:00.26#ibcon#about to clear, iclass 25 cls_cnt 0 2006.253.07:54:00.26#ibcon#cleared, iclass 25 cls_cnt 0 2006.253.07:54:00.26$vc4f8/valo=8,852.99 2006.253.07:54:00.26#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.253.07:54:00.26#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.253.07:54:00.26#ibcon#ireg 17 cls_cnt 0 2006.253.07:54:00.26#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.253.07:54:00.26#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.253.07:54:00.26#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.253.07:54:00.26#ibcon#enter wrdev, iclass 27, count 0 2006.253.07:54:00.26#ibcon#first serial, iclass 27, count 0 2006.253.07:54:00.26#ibcon#enter sib2, iclass 27, count 0 2006.253.07:54:00.26#ibcon#flushed, iclass 27, count 0 2006.253.07:54:00.26#ibcon#about to write, iclass 27, count 0 2006.253.07:54:00.26#ibcon#wrote, iclass 27, count 0 2006.253.07:54:00.26#ibcon#about to read 3, iclass 27, count 0 2006.253.07:54:00.28#ibcon#read 3, iclass 27, count 0 2006.253.07:54:00.28#ibcon#about to read 4, iclass 27, count 0 2006.253.07:54:00.28#ibcon#read 4, iclass 27, count 0 2006.253.07:54:00.28#ibcon#about to read 5, iclass 27, count 0 2006.253.07:54:00.28#ibcon#read 5, iclass 27, count 0 2006.253.07:54:00.28#ibcon#about to read 6, iclass 27, count 0 2006.253.07:54:00.28#ibcon#read 6, iclass 27, count 0 2006.253.07:54:00.28#ibcon#end of sib2, iclass 27, count 0 2006.253.07:54:00.28#ibcon#*mode == 0, iclass 27, count 0 2006.253.07:54:00.28#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.253.07:54:00.28#ibcon#[26=FRQ=08,852.99\r\n] 2006.253.07:54:00.28#ibcon#*before write, iclass 27, count 0 2006.253.07:54:00.28#ibcon#enter sib2, iclass 27, count 0 2006.253.07:54:00.28#ibcon#flushed, iclass 27, count 0 2006.253.07:54:00.28#ibcon#about to write, iclass 27, count 0 2006.253.07:54:00.28#ibcon#wrote, iclass 27, count 0 2006.253.07:54:00.28#ibcon#about to read 3, iclass 27, count 0 2006.253.07:54:00.32#ibcon#read 3, iclass 27, count 0 2006.253.07:54:00.32#ibcon#about to read 4, iclass 27, count 0 2006.253.07:54:00.32#ibcon#read 4, iclass 27, count 0 2006.253.07:54:00.32#ibcon#about to read 5, iclass 27, count 0 2006.253.07:54:00.32#ibcon#read 5, iclass 27, count 0 2006.253.07:54:00.32#ibcon#about to read 6, iclass 27, count 0 2006.253.07:54:00.32#ibcon#read 6, iclass 27, count 0 2006.253.07:54:00.32#ibcon#end of sib2, iclass 27, count 0 2006.253.07:54:00.32#ibcon#*after write, iclass 27, count 0 2006.253.07:54:00.32#ibcon#*before return 0, iclass 27, count 0 2006.253.07:54:00.32#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.253.07:54:00.32#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.253.07:54:00.32#ibcon#about to clear, iclass 27 cls_cnt 0 2006.253.07:54:00.32#ibcon#cleared, iclass 27 cls_cnt 0 2006.253.07:54:00.32$vc4f8/va=8,7 2006.253.07:54:00.32#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.253.07:54:00.32#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.253.07:54:00.32#ibcon#ireg 11 cls_cnt 2 2006.253.07:54:00.32#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.253.07:54:00.38#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.253.07:54:00.38#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.253.07:54:00.38#ibcon#enter wrdev, iclass 29, count 2 2006.253.07:54:00.38#ibcon#first serial, iclass 29, count 2 2006.253.07:54:00.38#ibcon#enter sib2, iclass 29, count 2 2006.253.07:54:00.38#ibcon#flushed, iclass 29, count 2 2006.253.07:54:00.38#ibcon#about to write, iclass 29, count 2 2006.253.07:54:00.38#ibcon#wrote, iclass 29, count 2 2006.253.07:54:00.38#ibcon#about to read 3, iclass 29, count 2 2006.253.07:54:00.40#ibcon#read 3, iclass 29, count 2 2006.253.07:54:00.40#ibcon#about to read 4, iclass 29, count 2 2006.253.07:54:00.40#ibcon#read 4, iclass 29, count 2 2006.253.07:54:00.40#ibcon#about to read 5, iclass 29, count 2 2006.253.07:54:00.40#ibcon#read 5, iclass 29, count 2 2006.253.07:54:00.40#ibcon#about to read 6, iclass 29, count 2 2006.253.07:54:00.40#ibcon#read 6, iclass 29, count 2 2006.253.07:54:00.40#ibcon#end of sib2, iclass 29, count 2 2006.253.07:54:00.40#ibcon#*mode == 0, iclass 29, count 2 2006.253.07:54:00.40#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.253.07:54:00.40#ibcon#[25=AT08-07\r\n] 2006.253.07:54:00.40#ibcon#*before write, iclass 29, count 2 2006.253.07:54:00.40#ibcon#enter sib2, iclass 29, count 2 2006.253.07:54:00.40#ibcon#flushed, iclass 29, count 2 2006.253.07:54:00.40#ibcon#about to write, iclass 29, count 2 2006.253.07:54:00.40#ibcon#wrote, iclass 29, count 2 2006.253.07:54:00.40#ibcon#about to read 3, iclass 29, count 2 2006.253.07:54:00.43#ibcon#read 3, iclass 29, count 2 2006.253.07:54:00.43#ibcon#about to read 4, iclass 29, count 2 2006.253.07:54:00.43#ibcon#read 4, iclass 29, count 2 2006.253.07:54:00.43#ibcon#about to read 5, iclass 29, count 2 2006.253.07:54:00.43#ibcon#read 5, iclass 29, count 2 2006.253.07:54:00.43#ibcon#about to read 6, iclass 29, count 2 2006.253.07:54:00.43#ibcon#read 6, iclass 29, count 2 2006.253.07:54:00.43#ibcon#end of sib2, iclass 29, count 2 2006.253.07:54:00.43#ibcon#*after write, iclass 29, count 2 2006.253.07:54:00.43#ibcon#*before return 0, iclass 29, count 2 2006.253.07:54:00.43#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.253.07:54:00.43#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.253.07:54:00.43#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.253.07:54:00.43#ibcon#ireg 7 cls_cnt 0 2006.253.07:54:00.43#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.253.07:54:00.55#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.253.07:54:00.55#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.253.07:54:00.55#ibcon#enter wrdev, iclass 29, count 0 2006.253.07:54:00.55#ibcon#first serial, iclass 29, count 0 2006.253.07:54:00.55#ibcon#enter sib2, iclass 29, count 0 2006.253.07:54:00.55#ibcon#flushed, iclass 29, count 0 2006.253.07:54:00.55#ibcon#about to write, iclass 29, count 0 2006.253.07:54:00.55#ibcon#wrote, iclass 29, count 0 2006.253.07:54:00.55#ibcon#about to read 3, iclass 29, count 0 2006.253.07:54:00.57#ibcon#read 3, iclass 29, count 0 2006.253.07:54:00.57#ibcon#about to read 4, iclass 29, count 0 2006.253.07:54:00.57#ibcon#read 4, iclass 29, count 0 2006.253.07:54:00.57#ibcon#about to read 5, iclass 29, count 0 2006.253.07:54:00.57#ibcon#read 5, iclass 29, count 0 2006.253.07:54:00.57#ibcon#about to read 6, iclass 29, count 0 2006.253.07:54:00.57#ibcon#read 6, iclass 29, count 0 2006.253.07:54:00.57#ibcon#end of sib2, iclass 29, count 0 2006.253.07:54:00.57#ibcon#*mode == 0, iclass 29, count 0 2006.253.07:54:00.57#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.253.07:54:00.57#ibcon#[25=USB\r\n] 2006.253.07:54:00.57#ibcon#*before write, iclass 29, count 0 2006.253.07:54:00.57#ibcon#enter sib2, iclass 29, count 0 2006.253.07:54:00.57#ibcon#flushed, iclass 29, count 0 2006.253.07:54:00.57#ibcon#about to write, iclass 29, count 0 2006.253.07:54:00.57#ibcon#wrote, iclass 29, count 0 2006.253.07:54:00.57#ibcon#about to read 3, iclass 29, count 0 2006.253.07:54:00.60#ibcon#read 3, iclass 29, count 0 2006.253.07:54:00.60#ibcon#about to read 4, iclass 29, count 0 2006.253.07:54:00.60#ibcon#read 4, iclass 29, count 0 2006.253.07:54:00.60#ibcon#about to read 5, iclass 29, count 0 2006.253.07:54:00.60#ibcon#read 5, iclass 29, count 0 2006.253.07:54:00.60#ibcon#about to read 6, iclass 29, count 0 2006.253.07:54:00.60#ibcon#read 6, iclass 29, count 0 2006.253.07:54:00.60#ibcon#end of sib2, iclass 29, count 0 2006.253.07:54:00.60#ibcon#*after write, iclass 29, count 0 2006.253.07:54:00.60#ibcon#*before return 0, iclass 29, count 0 2006.253.07:54:00.60#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.253.07:54:00.60#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.253.07:54:00.60#ibcon#about to clear, iclass 29 cls_cnt 0 2006.253.07:54:00.60#ibcon#cleared, iclass 29 cls_cnt 0 2006.253.07:54:00.60$vc4f8/vblo=1,632.99 2006.253.07:54:00.60#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.253.07:54:00.60#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.253.07:54:00.60#ibcon#ireg 17 cls_cnt 0 2006.253.07:54:00.60#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.253.07:54:00.60#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.253.07:54:00.60#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.253.07:54:00.60#ibcon#enter wrdev, iclass 31, count 0 2006.253.07:54:00.60#ibcon#first serial, iclass 31, count 0 2006.253.07:54:00.60#ibcon#enter sib2, iclass 31, count 0 2006.253.07:54:00.60#ibcon#flushed, iclass 31, count 0 2006.253.07:54:00.60#ibcon#about to write, iclass 31, count 0 2006.253.07:54:00.60#ibcon#wrote, iclass 31, count 0 2006.253.07:54:00.60#ibcon#about to read 3, iclass 31, count 0 2006.253.07:54:00.62#ibcon#read 3, iclass 31, count 0 2006.253.07:54:00.62#ibcon#about to read 4, iclass 31, count 0 2006.253.07:54:00.62#ibcon#read 4, iclass 31, count 0 2006.253.07:54:00.62#ibcon#about to read 5, iclass 31, count 0 2006.253.07:54:00.62#ibcon#read 5, iclass 31, count 0 2006.253.07:54:00.62#ibcon#about to read 6, iclass 31, count 0 2006.253.07:54:00.62#ibcon#read 6, iclass 31, count 0 2006.253.07:54:00.62#ibcon#end of sib2, iclass 31, count 0 2006.253.07:54:00.62#ibcon#*mode == 0, iclass 31, count 0 2006.253.07:54:00.62#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.253.07:54:00.62#ibcon#[28=FRQ=01,632.99\r\n] 2006.253.07:54:00.62#ibcon#*before write, iclass 31, count 0 2006.253.07:54:00.62#ibcon#enter sib2, iclass 31, count 0 2006.253.07:54:00.62#ibcon#flushed, iclass 31, count 0 2006.253.07:54:00.62#ibcon#about to write, iclass 31, count 0 2006.253.07:54:00.62#ibcon#wrote, iclass 31, count 0 2006.253.07:54:00.62#ibcon#about to read 3, iclass 31, count 0 2006.253.07:54:00.66#ibcon#read 3, iclass 31, count 0 2006.253.07:54:00.66#ibcon#about to read 4, iclass 31, count 0 2006.253.07:54:00.66#ibcon#read 4, iclass 31, count 0 2006.253.07:54:00.66#ibcon#about to read 5, iclass 31, count 0 2006.253.07:54:00.66#ibcon#read 5, iclass 31, count 0 2006.253.07:54:00.66#ibcon#about to read 6, iclass 31, count 0 2006.253.07:54:00.66#ibcon#read 6, iclass 31, count 0 2006.253.07:54:00.66#ibcon#end of sib2, iclass 31, count 0 2006.253.07:54:00.66#ibcon#*after write, iclass 31, count 0 2006.253.07:54:00.66#ibcon#*before return 0, iclass 31, count 0 2006.253.07:54:00.66#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.253.07:54:00.66#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.253.07:54:00.66#ibcon#about to clear, iclass 31 cls_cnt 0 2006.253.07:54:00.66#ibcon#cleared, iclass 31 cls_cnt 0 2006.253.07:54:00.66$vc4f8/vb=1,4 2006.253.07:54:00.66#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.253.07:54:00.66#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.253.07:54:00.66#ibcon#ireg 11 cls_cnt 2 2006.253.07:54:00.66#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.253.07:54:00.66#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.253.07:54:00.66#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.253.07:54:00.66#ibcon#enter wrdev, iclass 33, count 2 2006.253.07:54:00.66#ibcon#first serial, iclass 33, count 2 2006.253.07:54:00.66#ibcon#enter sib2, iclass 33, count 2 2006.253.07:54:00.66#ibcon#flushed, iclass 33, count 2 2006.253.07:54:00.66#ibcon#about to write, iclass 33, count 2 2006.253.07:54:00.66#ibcon#wrote, iclass 33, count 2 2006.253.07:54:00.66#ibcon#about to read 3, iclass 33, count 2 2006.253.07:54:00.68#ibcon#read 3, iclass 33, count 2 2006.253.07:54:00.68#ibcon#about to read 4, iclass 33, count 2 2006.253.07:54:00.68#ibcon#read 4, iclass 33, count 2 2006.253.07:54:00.68#ibcon#about to read 5, iclass 33, count 2 2006.253.07:54:00.68#ibcon#read 5, iclass 33, count 2 2006.253.07:54:00.68#ibcon#about to read 6, iclass 33, count 2 2006.253.07:54:00.68#ibcon#read 6, iclass 33, count 2 2006.253.07:54:00.68#ibcon#end of sib2, iclass 33, count 2 2006.253.07:54:00.68#ibcon#*mode == 0, iclass 33, count 2 2006.253.07:54:00.68#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.253.07:54:00.68#ibcon#[27=AT01-04\r\n] 2006.253.07:54:00.68#ibcon#*before write, iclass 33, count 2 2006.253.07:54:00.68#ibcon#enter sib2, iclass 33, count 2 2006.253.07:54:00.68#ibcon#flushed, iclass 33, count 2 2006.253.07:54:00.68#ibcon#about to write, iclass 33, count 2 2006.253.07:54:00.68#ibcon#wrote, iclass 33, count 2 2006.253.07:54:00.68#ibcon#about to read 3, iclass 33, count 2 2006.253.07:54:00.71#ibcon#read 3, iclass 33, count 2 2006.253.07:54:00.71#ibcon#about to read 4, iclass 33, count 2 2006.253.07:54:00.71#ibcon#read 4, iclass 33, count 2 2006.253.07:54:00.71#ibcon#about to read 5, iclass 33, count 2 2006.253.07:54:00.71#ibcon#read 5, iclass 33, count 2 2006.253.07:54:00.71#ibcon#about to read 6, iclass 33, count 2 2006.253.07:54:00.71#ibcon#read 6, iclass 33, count 2 2006.253.07:54:00.71#ibcon#end of sib2, iclass 33, count 2 2006.253.07:54:00.71#ibcon#*after write, iclass 33, count 2 2006.253.07:54:00.71#ibcon#*before return 0, iclass 33, count 2 2006.253.07:54:00.71#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.253.07:54:00.71#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.253.07:54:00.71#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.253.07:54:00.71#ibcon#ireg 7 cls_cnt 0 2006.253.07:54:00.71#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.253.07:54:00.83#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.253.07:54:00.83#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.253.07:54:00.83#ibcon#enter wrdev, iclass 33, count 0 2006.253.07:54:00.83#ibcon#first serial, iclass 33, count 0 2006.253.07:54:00.83#ibcon#enter sib2, iclass 33, count 0 2006.253.07:54:00.83#ibcon#flushed, iclass 33, count 0 2006.253.07:54:00.83#ibcon#about to write, iclass 33, count 0 2006.253.07:54:00.83#ibcon#wrote, iclass 33, count 0 2006.253.07:54:00.83#ibcon#about to read 3, iclass 33, count 0 2006.253.07:54:00.85#ibcon#read 3, iclass 33, count 0 2006.253.07:54:00.85#ibcon#about to read 4, iclass 33, count 0 2006.253.07:54:00.85#ibcon#read 4, iclass 33, count 0 2006.253.07:54:00.85#ibcon#about to read 5, iclass 33, count 0 2006.253.07:54:00.85#ibcon#read 5, iclass 33, count 0 2006.253.07:54:00.85#ibcon#about to read 6, iclass 33, count 0 2006.253.07:54:00.85#ibcon#read 6, iclass 33, count 0 2006.253.07:54:00.85#ibcon#end of sib2, iclass 33, count 0 2006.253.07:54:00.85#ibcon#*mode == 0, iclass 33, count 0 2006.253.07:54:00.85#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.253.07:54:00.85#ibcon#[27=USB\r\n] 2006.253.07:54:00.85#ibcon#*before write, iclass 33, count 0 2006.253.07:54:00.85#ibcon#enter sib2, iclass 33, count 0 2006.253.07:54:00.85#ibcon#flushed, iclass 33, count 0 2006.253.07:54:00.85#ibcon#about to write, iclass 33, count 0 2006.253.07:54:00.85#ibcon#wrote, iclass 33, count 0 2006.253.07:54:00.85#ibcon#about to read 3, iclass 33, count 0 2006.253.07:54:00.88#ibcon#read 3, iclass 33, count 0 2006.253.07:54:00.88#ibcon#about to read 4, iclass 33, count 0 2006.253.07:54:00.88#ibcon#read 4, iclass 33, count 0 2006.253.07:54:00.88#ibcon#about to read 5, iclass 33, count 0 2006.253.07:54:00.88#ibcon#read 5, iclass 33, count 0 2006.253.07:54:00.88#ibcon#about to read 6, iclass 33, count 0 2006.253.07:54:00.88#ibcon#read 6, iclass 33, count 0 2006.253.07:54:00.88#ibcon#end of sib2, iclass 33, count 0 2006.253.07:54:00.88#ibcon#*after write, iclass 33, count 0 2006.253.07:54:00.88#ibcon#*before return 0, iclass 33, count 0 2006.253.07:54:00.88#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.253.07:54:00.88#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.253.07:54:00.88#ibcon#about to clear, iclass 33 cls_cnt 0 2006.253.07:54:00.88#ibcon#cleared, iclass 33 cls_cnt 0 2006.253.07:54:00.88$vc4f8/vblo=2,640.99 2006.253.07:54:00.88#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.253.07:54:00.88#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.253.07:54:00.88#ibcon#ireg 17 cls_cnt 0 2006.253.07:54:00.88#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.253.07:54:00.88#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.253.07:54:00.88#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.253.07:54:00.88#ibcon#enter wrdev, iclass 35, count 0 2006.253.07:54:00.88#ibcon#first serial, iclass 35, count 0 2006.253.07:54:00.88#ibcon#enter sib2, iclass 35, count 0 2006.253.07:54:00.88#ibcon#flushed, iclass 35, count 0 2006.253.07:54:00.88#ibcon#about to write, iclass 35, count 0 2006.253.07:54:00.88#ibcon#wrote, iclass 35, count 0 2006.253.07:54:00.88#ibcon#about to read 3, iclass 35, count 0 2006.253.07:54:00.91#ibcon#read 3, iclass 35, count 0 2006.253.07:54:00.91#ibcon#about to read 4, iclass 35, count 0 2006.253.07:54:00.91#ibcon#read 4, iclass 35, count 0 2006.253.07:54:00.91#ibcon#about to read 5, iclass 35, count 0 2006.253.07:54:00.91#ibcon#read 5, iclass 35, count 0 2006.253.07:54:00.91#ibcon#about to read 6, iclass 35, count 0 2006.253.07:54:00.91#ibcon#read 6, iclass 35, count 0 2006.253.07:54:00.91#ibcon#end of sib2, iclass 35, count 0 2006.253.07:54:00.91#ibcon#*mode == 0, iclass 35, count 0 2006.253.07:54:00.91#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.253.07:54:00.91#ibcon#[28=FRQ=02,640.99\r\n] 2006.253.07:54:00.91#ibcon#*before write, iclass 35, count 0 2006.253.07:54:00.91#ibcon#enter sib2, iclass 35, count 0 2006.253.07:54:00.91#ibcon#flushed, iclass 35, count 0 2006.253.07:54:00.91#ibcon#about to write, iclass 35, count 0 2006.253.07:54:00.91#ibcon#wrote, iclass 35, count 0 2006.253.07:54:00.91#ibcon#about to read 3, iclass 35, count 0 2006.253.07:54:00.95#ibcon#read 3, iclass 35, count 0 2006.253.07:54:00.95#ibcon#about to read 4, iclass 35, count 0 2006.253.07:54:00.95#ibcon#read 4, iclass 35, count 0 2006.253.07:54:00.95#ibcon#about to read 5, iclass 35, count 0 2006.253.07:54:00.95#ibcon#read 5, iclass 35, count 0 2006.253.07:54:00.95#ibcon#about to read 6, iclass 35, count 0 2006.253.07:54:00.95#ibcon#read 6, iclass 35, count 0 2006.253.07:54:00.95#ibcon#end of sib2, iclass 35, count 0 2006.253.07:54:00.95#ibcon#*after write, iclass 35, count 0 2006.253.07:54:00.95#ibcon#*before return 0, iclass 35, count 0 2006.253.07:54:00.95#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.253.07:54:00.95#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.253.07:54:00.95#ibcon#about to clear, iclass 35 cls_cnt 0 2006.253.07:54:00.95#ibcon#cleared, iclass 35 cls_cnt 0 2006.253.07:54:00.95$vc4f8/vb=2,5 2006.253.07:54:00.95#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.253.07:54:00.95#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.253.07:54:00.95#ibcon#ireg 11 cls_cnt 2 2006.253.07:54:00.95#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.253.07:54:01.00#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.253.07:54:01.00#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.253.07:54:01.00#ibcon#enter wrdev, iclass 37, count 2 2006.253.07:54:01.00#ibcon#first serial, iclass 37, count 2 2006.253.07:54:01.00#ibcon#enter sib2, iclass 37, count 2 2006.253.07:54:01.00#ibcon#flushed, iclass 37, count 2 2006.253.07:54:01.00#ibcon#about to write, iclass 37, count 2 2006.253.07:54:01.00#ibcon#wrote, iclass 37, count 2 2006.253.07:54:01.00#ibcon#about to read 3, iclass 37, count 2 2006.253.07:54:01.02#ibcon#read 3, iclass 37, count 2 2006.253.07:54:01.02#ibcon#about to read 4, iclass 37, count 2 2006.253.07:54:01.02#ibcon#read 4, iclass 37, count 2 2006.253.07:54:01.02#ibcon#about to read 5, iclass 37, count 2 2006.253.07:54:01.02#ibcon#read 5, iclass 37, count 2 2006.253.07:54:01.02#ibcon#about to read 6, iclass 37, count 2 2006.253.07:54:01.02#ibcon#read 6, iclass 37, count 2 2006.253.07:54:01.02#ibcon#end of sib2, iclass 37, count 2 2006.253.07:54:01.02#ibcon#*mode == 0, iclass 37, count 2 2006.253.07:54:01.02#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.253.07:54:01.02#ibcon#[27=AT02-05\r\n] 2006.253.07:54:01.02#ibcon#*before write, iclass 37, count 2 2006.253.07:54:01.02#ibcon#enter sib2, iclass 37, count 2 2006.253.07:54:01.02#ibcon#flushed, iclass 37, count 2 2006.253.07:54:01.02#ibcon#about to write, iclass 37, count 2 2006.253.07:54:01.02#ibcon#wrote, iclass 37, count 2 2006.253.07:54:01.02#ibcon#about to read 3, iclass 37, count 2 2006.253.07:54:01.05#ibcon#read 3, iclass 37, count 2 2006.253.07:54:01.05#ibcon#about to read 4, iclass 37, count 2 2006.253.07:54:01.05#ibcon#read 4, iclass 37, count 2 2006.253.07:54:01.05#ibcon#about to read 5, iclass 37, count 2 2006.253.07:54:01.05#ibcon#read 5, iclass 37, count 2 2006.253.07:54:01.05#ibcon#about to read 6, iclass 37, count 2 2006.253.07:54:01.05#ibcon#read 6, iclass 37, count 2 2006.253.07:54:01.05#ibcon#end of sib2, iclass 37, count 2 2006.253.07:54:01.05#ibcon#*after write, iclass 37, count 2 2006.253.07:54:01.05#ibcon#*before return 0, iclass 37, count 2 2006.253.07:54:01.05#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.253.07:54:01.05#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.253.07:54:01.05#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.253.07:54:01.05#ibcon#ireg 7 cls_cnt 0 2006.253.07:54:01.05#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.253.07:54:01.17#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.253.07:54:01.17#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.253.07:54:01.17#ibcon#enter wrdev, iclass 37, count 0 2006.253.07:54:01.17#ibcon#first serial, iclass 37, count 0 2006.253.07:54:01.17#ibcon#enter sib2, iclass 37, count 0 2006.253.07:54:01.17#ibcon#flushed, iclass 37, count 0 2006.253.07:54:01.17#ibcon#about to write, iclass 37, count 0 2006.253.07:54:01.17#ibcon#wrote, iclass 37, count 0 2006.253.07:54:01.17#ibcon#about to read 3, iclass 37, count 0 2006.253.07:54:01.19#ibcon#read 3, iclass 37, count 0 2006.253.07:54:01.19#ibcon#about to read 4, iclass 37, count 0 2006.253.07:54:01.19#ibcon#read 4, iclass 37, count 0 2006.253.07:54:01.19#ibcon#about to read 5, iclass 37, count 0 2006.253.07:54:01.19#ibcon#read 5, iclass 37, count 0 2006.253.07:54:01.19#ibcon#about to read 6, iclass 37, count 0 2006.253.07:54:01.19#ibcon#read 6, iclass 37, count 0 2006.253.07:54:01.19#ibcon#end of sib2, iclass 37, count 0 2006.253.07:54:01.19#ibcon#*mode == 0, iclass 37, count 0 2006.253.07:54:01.19#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.253.07:54:01.19#ibcon#[27=USB\r\n] 2006.253.07:54:01.19#ibcon#*before write, iclass 37, count 0 2006.253.07:54:01.19#ibcon#enter sib2, iclass 37, count 0 2006.253.07:54:01.19#ibcon#flushed, iclass 37, count 0 2006.253.07:54:01.19#ibcon#about to write, iclass 37, count 0 2006.253.07:54:01.19#ibcon#wrote, iclass 37, count 0 2006.253.07:54:01.19#ibcon#about to read 3, iclass 37, count 0 2006.253.07:54:01.22#ibcon#read 3, iclass 37, count 0 2006.253.07:54:01.22#ibcon#about to read 4, iclass 37, count 0 2006.253.07:54:01.22#ibcon#read 4, iclass 37, count 0 2006.253.07:54:01.22#ibcon#about to read 5, iclass 37, count 0 2006.253.07:54:01.22#ibcon#read 5, iclass 37, count 0 2006.253.07:54:01.22#ibcon#about to read 6, iclass 37, count 0 2006.253.07:54:01.22#ibcon#read 6, iclass 37, count 0 2006.253.07:54:01.22#ibcon#end of sib2, iclass 37, count 0 2006.253.07:54:01.22#ibcon#*after write, iclass 37, count 0 2006.253.07:54:01.22#ibcon#*before return 0, iclass 37, count 0 2006.253.07:54:01.22#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.253.07:54:01.22#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.253.07:54:01.22#ibcon#about to clear, iclass 37 cls_cnt 0 2006.253.07:54:01.22#ibcon#cleared, iclass 37 cls_cnt 0 2006.253.07:54:01.22$vc4f8/vblo=3,656.99 2006.253.07:54:01.22#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.253.07:54:01.22#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.253.07:54:01.22#ibcon#ireg 17 cls_cnt 0 2006.253.07:54:01.22#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.253.07:54:01.22#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.253.07:54:01.22#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.253.07:54:01.22#ibcon#enter wrdev, iclass 39, count 0 2006.253.07:54:01.22#ibcon#first serial, iclass 39, count 0 2006.253.07:54:01.22#ibcon#enter sib2, iclass 39, count 0 2006.253.07:54:01.22#ibcon#flushed, iclass 39, count 0 2006.253.07:54:01.22#ibcon#about to write, iclass 39, count 0 2006.253.07:54:01.22#ibcon#wrote, iclass 39, count 0 2006.253.07:54:01.22#ibcon#about to read 3, iclass 39, count 0 2006.253.07:54:01.24#ibcon#read 3, iclass 39, count 0 2006.253.07:54:01.24#ibcon#about to read 4, iclass 39, count 0 2006.253.07:54:01.24#ibcon#read 4, iclass 39, count 0 2006.253.07:54:01.24#ibcon#about to read 5, iclass 39, count 0 2006.253.07:54:01.24#ibcon#read 5, iclass 39, count 0 2006.253.07:54:01.24#ibcon#about to read 6, iclass 39, count 0 2006.253.07:54:01.24#ibcon#read 6, iclass 39, count 0 2006.253.07:54:01.24#ibcon#end of sib2, iclass 39, count 0 2006.253.07:54:01.24#ibcon#*mode == 0, iclass 39, count 0 2006.253.07:54:01.24#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.253.07:54:01.24#ibcon#[28=FRQ=03,656.99\r\n] 2006.253.07:54:01.24#ibcon#*before write, iclass 39, count 0 2006.253.07:54:01.24#ibcon#enter sib2, iclass 39, count 0 2006.253.07:54:01.24#ibcon#flushed, iclass 39, count 0 2006.253.07:54:01.24#ibcon#about to write, iclass 39, count 0 2006.253.07:54:01.24#ibcon#wrote, iclass 39, count 0 2006.253.07:54:01.24#ibcon#about to read 3, iclass 39, count 0 2006.253.07:54:01.28#ibcon#read 3, iclass 39, count 0 2006.253.07:54:01.28#ibcon#about to read 4, iclass 39, count 0 2006.253.07:54:01.28#ibcon#read 4, iclass 39, count 0 2006.253.07:54:01.28#ibcon#about to read 5, iclass 39, count 0 2006.253.07:54:01.28#ibcon#read 5, iclass 39, count 0 2006.253.07:54:01.28#ibcon#about to read 6, iclass 39, count 0 2006.253.07:54:01.28#ibcon#read 6, iclass 39, count 0 2006.253.07:54:01.28#ibcon#end of sib2, iclass 39, count 0 2006.253.07:54:01.28#ibcon#*after write, iclass 39, count 0 2006.253.07:54:01.28#ibcon#*before return 0, iclass 39, count 0 2006.253.07:54:01.28#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.253.07:54:01.28#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.253.07:54:01.28#ibcon#about to clear, iclass 39 cls_cnt 0 2006.253.07:54:01.28#ibcon#cleared, iclass 39 cls_cnt 0 2006.253.07:54:01.28$vc4f8/vb=3,4 2006.253.07:54:01.28#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.253.07:54:01.28#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.253.07:54:01.28#ibcon#ireg 11 cls_cnt 2 2006.253.07:54:01.28#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.253.07:54:01.34#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.253.07:54:01.34#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.253.07:54:01.34#ibcon#enter wrdev, iclass 3, count 2 2006.253.07:54:01.34#ibcon#first serial, iclass 3, count 2 2006.253.07:54:01.34#ibcon#enter sib2, iclass 3, count 2 2006.253.07:54:01.34#ibcon#flushed, iclass 3, count 2 2006.253.07:54:01.34#ibcon#about to write, iclass 3, count 2 2006.253.07:54:01.34#ibcon#wrote, iclass 3, count 2 2006.253.07:54:01.34#ibcon#about to read 3, iclass 3, count 2 2006.253.07:54:01.36#ibcon#read 3, iclass 3, count 2 2006.253.07:54:01.36#ibcon#about to read 4, iclass 3, count 2 2006.253.07:54:01.36#ibcon#read 4, iclass 3, count 2 2006.253.07:54:01.36#ibcon#about to read 5, iclass 3, count 2 2006.253.07:54:01.36#ibcon#read 5, iclass 3, count 2 2006.253.07:54:01.36#ibcon#about to read 6, iclass 3, count 2 2006.253.07:54:01.36#ibcon#read 6, iclass 3, count 2 2006.253.07:54:01.36#ibcon#end of sib2, iclass 3, count 2 2006.253.07:54:01.36#ibcon#*mode == 0, iclass 3, count 2 2006.253.07:54:01.36#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.253.07:54:01.36#ibcon#[27=AT03-04\r\n] 2006.253.07:54:01.36#ibcon#*before write, iclass 3, count 2 2006.253.07:54:01.36#ibcon#enter sib2, iclass 3, count 2 2006.253.07:54:01.36#ibcon#flushed, iclass 3, count 2 2006.253.07:54:01.36#ibcon#about to write, iclass 3, count 2 2006.253.07:54:01.36#ibcon#wrote, iclass 3, count 2 2006.253.07:54:01.36#ibcon#about to read 3, iclass 3, count 2 2006.253.07:54:01.39#ibcon#read 3, iclass 3, count 2 2006.253.07:54:01.39#ibcon#about to read 4, iclass 3, count 2 2006.253.07:54:01.39#ibcon#read 4, iclass 3, count 2 2006.253.07:54:01.39#ibcon#about to read 5, iclass 3, count 2 2006.253.07:54:01.39#ibcon#read 5, iclass 3, count 2 2006.253.07:54:01.39#ibcon#about to read 6, iclass 3, count 2 2006.253.07:54:01.39#ibcon#read 6, iclass 3, count 2 2006.253.07:54:01.39#ibcon#end of sib2, iclass 3, count 2 2006.253.07:54:01.39#ibcon#*after write, iclass 3, count 2 2006.253.07:54:01.39#ibcon#*before return 0, iclass 3, count 2 2006.253.07:54:01.39#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.253.07:54:01.39#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.253.07:54:01.39#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.253.07:54:01.39#ibcon#ireg 7 cls_cnt 0 2006.253.07:54:01.39#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.253.07:54:01.51#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.253.07:54:01.51#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.253.07:54:01.51#ibcon#enter wrdev, iclass 3, count 0 2006.253.07:54:01.51#ibcon#first serial, iclass 3, count 0 2006.253.07:54:01.51#ibcon#enter sib2, iclass 3, count 0 2006.253.07:54:01.51#ibcon#flushed, iclass 3, count 0 2006.253.07:54:01.51#ibcon#about to write, iclass 3, count 0 2006.253.07:54:01.51#ibcon#wrote, iclass 3, count 0 2006.253.07:54:01.51#ibcon#about to read 3, iclass 3, count 0 2006.253.07:54:01.53#ibcon#read 3, iclass 3, count 0 2006.253.07:54:01.53#ibcon#about to read 4, iclass 3, count 0 2006.253.07:54:01.53#ibcon#read 4, iclass 3, count 0 2006.253.07:54:01.53#ibcon#about to read 5, iclass 3, count 0 2006.253.07:54:01.53#ibcon#read 5, iclass 3, count 0 2006.253.07:54:01.53#ibcon#about to read 6, iclass 3, count 0 2006.253.07:54:01.53#ibcon#read 6, iclass 3, count 0 2006.253.07:54:01.53#ibcon#end of sib2, iclass 3, count 0 2006.253.07:54:01.53#ibcon#*mode == 0, iclass 3, count 0 2006.253.07:54:01.53#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.253.07:54:01.53#ibcon#[27=USB\r\n] 2006.253.07:54:01.53#ibcon#*before write, iclass 3, count 0 2006.253.07:54:01.53#ibcon#enter sib2, iclass 3, count 0 2006.253.07:54:01.53#ibcon#flushed, iclass 3, count 0 2006.253.07:54:01.53#ibcon#about to write, iclass 3, count 0 2006.253.07:54:01.53#ibcon#wrote, iclass 3, count 0 2006.253.07:54:01.53#ibcon#about to read 3, iclass 3, count 0 2006.253.07:54:01.56#ibcon#read 3, iclass 3, count 0 2006.253.07:54:01.56#ibcon#about to read 4, iclass 3, count 0 2006.253.07:54:01.56#ibcon#read 4, iclass 3, count 0 2006.253.07:54:01.56#ibcon#about to read 5, iclass 3, count 0 2006.253.07:54:01.56#ibcon#read 5, iclass 3, count 0 2006.253.07:54:01.56#ibcon#about to read 6, iclass 3, count 0 2006.253.07:54:01.56#ibcon#read 6, iclass 3, count 0 2006.253.07:54:01.56#ibcon#end of sib2, iclass 3, count 0 2006.253.07:54:01.56#ibcon#*after write, iclass 3, count 0 2006.253.07:54:01.56#ibcon#*before return 0, iclass 3, count 0 2006.253.07:54:01.56#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.253.07:54:01.56#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.253.07:54:01.56#ibcon#about to clear, iclass 3 cls_cnt 0 2006.253.07:54:01.56#ibcon#cleared, iclass 3 cls_cnt 0 2006.253.07:54:01.56$vc4f8/vblo=4,712.99 2006.253.07:54:01.56#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.253.07:54:01.56#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.253.07:54:01.56#ibcon#ireg 17 cls_cnt 0 2006.253.07:54:01.56#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.253.07:54:01.56#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.253.07:54:01.56#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.253.07:54:01.56#ibcon#enter wrdev, iclass 5, count 0 2006.253.07:54:01.56#ibcon#first serial, iclass 5, count 0 2006.253.07:54:01.56#ibcon#enter sib2, iclass 5, count 0 2006.253.07:54:01.56#ibcon#flushed, iclass 5, count 0 2006.253.07:54:01.56#ibcon#about to write, iclass 5, count 0 2006.253.07:54:01.56#ibcon#wrote, iclass 5, count 0 2006.253.07:54:01.56#ibcon#about to read 3, iclass 5, count 0 2006.253.07:54:01.59#ibcon#read 3, iclass 5, count 0 2006.253.07:54:01.59#ibcon#about to read 4, iclass 5, count 0 2006.253.07:54:01.59#ibcon#read 4, iclass 5, count 0 2006.253.07:54:01.59#ibcon#about to read 5, iclass 5, count 0 2006.253.07:54:01.59#ibcon#read 5, iclass 5, count 0 2006.253.07:54:01.59#ibcon#about to read 6, iclass 5, count 0 2006.253.07:54:01.59#ibcon#read 6, iclass 5, count 0 2006.253.07:54:01.59#ibcon#end of sib2, iclass 5, count 0 2006.253.07:54:01.59#ibcon#*mode == 0, iclass 5, count 0 2006.253.07:54:01.59#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.253.07:54:01.59#ibcon#[28=FRQ=04,712.99\r\n] 2006.253.07:54:01.59#ibcon#*before write, iclass 5, count 0 2006.253.07:54:01.59#ibcon#enter sib2, iclass 5, count 0 2006.253.07:54:01.59#ibcon#flushed, iclass 5, count 0 2006.253.07:54:01.59#ibcon#about to write, iclass 5, count 0 2006.253.07:54:01.59#ibcon#wrote, iclass 5, count 0 2006.253.07:54:01.59#ibcon#about to read 3, iclass 5, count 0 2006.253.07:54:01.63#ibcon#read 3, iclass 5, count 0 2006.253.07:54:01.63#ibcon#about to read 4, iclass 5, count 0 2006.253.07:54:01.63#ibcon#read 4, iclass 5, count 0 2006.253.07:54:01.63#ibcon#about to read 5, iclass 5, count 0 2006.253.07:54:01.63#ibcon#read 5, iclass 5, count 0 2006.253.07:54:01.63#ibcon#about to read 6, iclass 5, count 0 2006.253.07:54:01.63#ibcon#read 6, iclass 5, count 0 2006.253.07:54:01.63#ibcon#end of sib2, iclass 5, count 0 2006.253.07:54:01.63#ibcon#*after write, iclass 5, count 0 2006.253.07:54:01.63#ibcon#*before return 0, iclass 5, count 0 2006.253.07:54:01.63#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.253.07:54:01.63#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.253.07:54:01.63#ibcon#about to clear, iclass 5 cls_cnt 0 2006.253.07:54:01.63#ibcon#cleared, iclass 5 cls_cnt 0 2006.253.07:54:01.63$vc4f8/vb=4,4 2006.253.07:54:01.63#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.253.07:54:01.63#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.253.07:54:01.63#ibcon#ireg 11 cls_cnt 2 2006.253.07:54:01.63#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.253.07:54:01.68#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.253.07:54:01.68#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.253.07:54:01.68#ibcon#enter wrdev, iclass 7, count 2 2006.253.07:54:01.68#ibcon#first serial, iclass 7, count 2 2006.253.07:54:01.68#ibcon#enter sib2, iclass 7, count 2 2006.253.07:54:01.68#ibcon#flushed, iclass 7, count 2 2006.253.07:54:01.68#ibcon#about to write, iclass 7, count 2 2006.253.07:54:01.68#ibcon#wrote, iclass 7, count 2 2006.253.07:54:01.68#ibcon#about to read 3, iclass 7, count 2 2006.253.07:54:01.70#ibcon#read 3, iclass 7, count 2 2006.253.07:54:01.70#ibcon#about to read 4, iclass 7, count 2 2006.253.07:54:01.70#ibcon#read 4, iclass 7, count 2 2006.253.07:54:01.70#ibcon#about to read 5, iclass 7, count 2 2006.253.07:54:01.70#ibcon#read 5, iclass 7, count 2 2006.253.07:54:01.70#ibcon#about to read 6, iclass 7, count 2 2006.253.07:54:01.70#ibcon#read 6, iclass 7, count 2 2006.253.07:54:01.70#ibcon#end of sib2, iclass 7, count 2 2006.253.07:54:01.70#ibcon#*mode == 0, iclass 7, count 2 2006.253.07:54:01.70#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.253.07:54:01.70#ibcon#[27=AT04-04\r\n] 2006.253.07:54:01.70#ibcon#*before write, iclass 7, count 2 2006.253.07:54:01.70#ibcon#enter sib2, iclass 7, count 2 2006.253.07:54:01.70#ibcon#flushed, iclass 7, count 2 2006.253.07:54:01.70#ibcon#about to write, iclass 7, count 2 2006.253.07:54:01.70#ibcon#wrote, iclass 7, count 2 2006.253.07:54:01.70#ibcon#about to read 3, iclass 7, count 2 2006.253.07:54:01.73#ibcon#read 3, iclass 7, count 2 2006.253.07:54:01.73#ibcon#about to read 4, iclass 7, count 2 2006.253.07:54:01.73#ibcon#read 4, iclass 7, count 2 2006.253.07:54:01.73#ibcon#about to read 5, iclass 7, count 2 2006.253.07:54:01.73#ibcon#read 5, iclass 7, count 2 2006.253.07:54:01.73#ibcon#about to read 6, iclass 7, count 2 2006.253.07:54:01.73#ibcon#read 6, iclass 7, count 2 2006.253.07:54:01.73#ibcon#end of sib2, iclass 7, count 2 2006.253.07:54:01.73#ibcon#*after write, iclass 7, count 2 2006.253.07:54:01.73#ibcon#*before return 0, iclass 7, count 2 2006.253.07:54:01.73#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.253.07:54:01.73#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.253.07:54:01.73#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.253.07:54:01.73#ibcon#ireg 7 cls_cnt 0 2006.253.07:54:01.73#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.253.07:54:01.85#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.253.07:54:01.85#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.253.07:54:01.85#ibcon#enter wrdev, iclass 7, count 0 2006.253.07:54:01.85#ibcon#first serial, iclass 7, count 0 2006.253.07:54:01.85#ibcon#enter sib2, iclass 7, count 0 2006.253.07:54:01.85#ibcon#flushed, iclass 7, count 0 2006.253.07:54:01.85#ibcon#about to write, iclass 7, count 0 2006.253.07:54:01.85#ibcon#wrote, iclass 7, count 0 2006.253.07:54:01.85#ibcon#about to read 3, iclass 7, count 0 2006.253.07:54:01.87#ibcon#read 3, iclass 7, count 0 2006.253.07:54:01.87#ibcon#about to read 4, iclass 7, count 0 2006.253.07:54:01.87#ibcon#read 4, iclass 7, count 0 2006.253.07:54:01.87#ibcon#about to read 5, iclass 7, count 0 2006.253.07:54:01.87#ibcon#read 5, iclass 7, count 0 2006.253.07:54:01.87#ibcon#about to read 6, iclass 7, count 0 2006.253.07:54:01.87#ibcon#read 6, iclass 7, count 0 2006.253.07:54:01.87#ibcon#end of sib2, iclass 7, count 0 2006.253.07:54:01.87#ibcon#*mode == 0, iclass 7, count 0 2006.253.07:54:01.87#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.253.07:54:01.87#ibcon#[27=USB\r\n] 2006.253.07:54:01.87#ibcon#*before write, iclass 7, count 0 2006.253.07:54:01.87#ibcon#enter sib2, iclass 7, count 0 2006.253.07:54:01.87#ibcon#flushed, iclass 7, count 0 2006.253.07:54:01.87#ibcon#about to write, iclass 7, count 0 2006.253.07:54:01.87#ibcon#wrote, iclass 7, count 0 2006.253.07:54:01.87#ibcon#about to read 3, iclass 7, count 0 2006.253.07:54:01.90#ibcon#read 3, iclass 7, count 0 2006.253.07:54:01.90#ibcon#about to read 4, iclass 7, count 0 2006.253.07:54:01.90#ibcon#read 4, iclass 7, count 0 2006.253.07:54:01.90#ibcon#about to read 5, iclass 7, count 0 2006.253.07:54:01.90#ibcon#read 5, iclass 7, count 0 2006.253.07:54:01.90#ibcon#about to read 6, iclass 7, count 0 2006.253.07:54:01.90#ibcon#read 6, iclass 7, count 0 2006.253.07:54:01.90#ibcon#end of sib2, iclass 7, count 0 2006.253.07:54:01.90#ibcon#*after write, iclass 7, count 0 2006.253.07:54:01.90#ibcon#*before return 0, iclass 7, count 0 2006.253.07:54:01.90#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.253.07:54:01.90#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.253.07:54:01.90#ibcon#about to clear, iclass 7 cls_cnt 0 2006.253.07:54:01.90#ibcon#cleared, iclass 7 cls_cnt 0 2006.253.07:54:01.90$vc4f8/vblo=5,744.99 2006.253.07:54:01.90#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.253.07:54:01.90#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.253.07:54:01.90#ibcon#ireg 17 cls_cnt 0 2006.253.07:54:01.90#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.253.07:54:01.90#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.253.07:54:01.90#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.253.07:54:01.90#ibcon#enter wrdev, iclass 11, count 0 2006.253.07:54:01.90#ibcon#first serial, iclass 11, count 0 2006.253.07:54:01.90#ibcon#enter sib2, iclass 11, count 0 2006.253.07:54:01.90#ibcon#flushed, iclass 11, count 0 2006.253.07:54:01.90#ibcon#about to write, iclass 11, count 0 2006.253.07:54:01.90#ibcon#wrote, iclass 11, count 0 2006.253.07:54:01.90#ibcon#about to read 3, iclass 11, count 0 2006.253.07:54:01.92#ibcon#read 3, iclass 11, count 0 2006.253.07:54:01.92#ibcon#about to read 4, iclass 11, count 0 2006.253.07:54:01.92#ibcon#read 4, iclass 11, count 0 2006.253.07:54:01.92#ibcon#about to read 5, iclass 11, count 0 2006.253.07:54:01.92#ibcon#read 5, iclass 11, count 0 2006.253.07:54:01.92#ibcon#about to read 6, iclass 11, count 0 2006.253.07:54:01.92#ibcon#read 6, iclass 11, count 0 2006.253.07:54:01.92#ibcon#end of sib2, iclass 11, count 0 2006.253.07:54:01.92#ibcon#*mode == 0, iclass 11, count 0 2006.253.07:54:01.92#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.253.07:54:01.92#ibcon#[28=FRQ=05,744.99\r\n] 2006.253.07:54:01.92#ibcon#*before write, iclass 11, count 0 2006.253.07:54:01.92#ibcon#enter sib2, iclass 11, count 0 2006.253.07:54:01.92#ibcon#flushed, iclass 11, count 0 2006.253.07:54:01.92#ibcon#about to write, iclass 11, count 0 2006.253.07:54:01.92#ibcon#wrote, iclass 11, count 0 2006.253.07:54:01.92#ibcon#about to read 3, iclass 11, count 0 2006.253.07:54:01.96#ibcon#read 3, iclass 11, count 0 2006.253.07:54:01.96#ibcon#about to read 4, iclass 11, count 0 2006.253.07:54:01.96#ibcon#read 4, iclass 11, count 0 2006.253.07:54:01.96#ibcon#about to read 5, iclass 11, count 0 2006.253.07:54:01.96#ibcon#read 5, iclass 11, count 0 2006.253.07:54:01.96#ibcon#about to read 6, iclass 11, count 0 2006.253.07:54:01.96#ibcon#read 6, iclass 11, count 0 2006.253.07:54:01.96#ibcon#end of sib2, iclass 11, count 0 2006.253.07:54:01.96#ibcon#*after write, iclass 11, count 0 2006.253.07:54:01.96#ibcon#*before return 0, iclass 11, count 0 2006.253.07:54:01.96#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.253.07:54:01.96#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.253.07:54:01.96#ibcon#about to clear, iclass 11 cls_cnt 0 2006.253.07:54:01.96#ibcon#cleared, iclass 11 cls_cnt 0 2006.253.07:54:01.96$vc4f8/vb=5,4 2006.253.07:54:01.96#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.253.07:54:01.96#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.253.07:54:01.96#ibcon#ireg 11 cls_cnt 2 2006.253.07:54:01.96#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.253.07:54:02.02#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.253.07:54:02.02#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.253.07:54:02.02#ibcon#enter wrdev, iclass 13, count 2 2006.253.07:54:02.02#ibcon#first serial, iclass 13, count 2 2006.253.07:54:02.02#ibcon#enter sib2, iclass 13, count 2 2006.253.07:54:02.02#ibcon#flushed, iclass 13, count 2 2006.253.07:54:02.02#ibcon#about to write, iclass 13, count 2 2006.253.07:54:02.02#ibcon#wrote, iclass 13, count 2 2006.253.07:54:02.02#ibcon#about to read 3, iclass 13, count 2 2006.253.07:54:02.04#ibcon#read 3, iclass 13, count 2 2006.253.07:54:02.04#ibcon#about to read 4, iclass 13, count 2 2006.253.07:54:02.04#ibcon#read 4, iclass 13, count 2 2006.253.07:54:02.04#ibcon#about to read 5, iclass 13, count 2 2006.253.07:54:02.04#ibcon#read 5, iclass 13, count 2 2006.253.07:54:02.04#ibcon#about to read 6, iclass 13, count 2 2006.253.07:54:02.04#ibcon#read 6, iclass 13, count 2 2006.253.07:54:02.04#ibcon#end of sib2, iclass 13, count 2 2006.253.07:54:02.04#ibcon#*mode == 0, iclass 13, count 2 2006.253.07:54:02.04#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.253.07:54:02.04#ibcon#[27=AT05-04\r\n] 2006.253.07:54:02.04#ibcon#*before write, iclass 13, count 2 2006.253.07:54:02.04#ibcon#enter sib2, iclass 13, count 2 2006.253.07:54:02.04#ibcon#flushed, iclass 13, count 2 2006.253.07:54:02.04#ibcon#about to write, iclass 13, count 2 2006.253.07:54:02.04#ibcon#wrote, iclass 13, count 2 2006.253.07:54:02.04#ibcon#about to read 3, iclass 13, count 2 2006.253.07:54:02.07#ibcon#read 3, iclass 13, count 2 2006.253.07:54:02.07#ibcon#about to read 4, iclass 13, count 2 2006.253.07:54:02.07#ibcon#read 4, iclass 13, count 2 2006.253.07:54:02.07#ibcon#about to read 5, iclass 13, count 2 2006.253.07:54:02.07#ibcon#read 5, iclass 13, count 2 2006.253.07:54:02.07#ibcon#about to read 6, iclass 13, count 2 2006.253.07:54:02.07#ibcon#read 6, iclass 13, count 2 2006.253.07:54:02.07#ibcon#end of sib2, iclass 13, count 2 2006.253.07:54:02.07#ibcon#*after write, iclass 13, count 2 2006.253.07:54:02.07#ibcon#*before return 0, iclass 13, count 2 2006.253.07:54:02.07#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.253.07:54:02.07#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.253.07:54:02.07#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.253.07:54:02.07#ibcon#ireg 7 cls_cnt 0 2006.253.07:54:02.07#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.253.07:54:02.19#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.253.07:54:02.19#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.253.07:54:02.19#ibcon#enter wrdev, iclass 13, count 0 2006.253.07:54:02.19#ibcon#first serial, iclass 13, count 0 2006.253.07:54:02.19#ibcon#enter sib2, iclass 13, count 0 2006.253.07:54:02.19#ibcon#flushed, iclass 13, count 0 2006.253.07:54:02.19#ibcon#about to write, iclass 13, count 0 2006.253.07:54:02.19#ibcon#wrote, iclass 13, count 0 2006.253.07:54:02.19#ibcon#about to read 3, iclass 13, count 0 2006.253.07:54:02.21#ibcon#read 3, iclass 13, count 0 2006.253.07:54:02.21#ibcon#about to read 4, iclass 13, count 0 2006.253.07:54:02.21#ibcon#read 4, iclass 13, count 0 2006.253.07:54:02.21#ibcon#about to read 5, iclass 13, count 0 2006.253.07:54:02.21#ibcon#read 5, iclass 13, count 0 2006.253.07:54:02.21#ibcon#about to read 6, iclass 13, count 0 2006.253.07:54:02.21#ibcon#read 6, iclass 13, count 0 2006.253.07:54:02.21#ibcon#end of sib2, iclass 13, count 0 2006.253.07:54:02.21#ibcon#*mode == 0, iclass 13, count 0 2006.253.07:54:02.21#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.253.07:54:02.21#ibcon#[27=USB\r\n] 2006.253.07:54:02.21#ibcon#*before write, iclass 13, count 0 2006.253.07:54:02.21#ibcon#enter sib2, iclass 13, count 0 2006.253.07:54:02.21#ibcon#flushed, iclass 13, count 0 2006.253.07:54:02.21#ibcon#about to write, iclass 13, count 0 2006.253.07:54:02.21#ibcon#wrote, iclass 13, count 0 2006.253.07:54:02.21#ibcon#about to read 3, iclass 13, count 0 2006.253.07:54:02.24#ibcon#read 3, iclass 13, count 0 2006.253.07:54:02.24#ibcon#about to read 4, iclass 13, count 0 2006.253.07:54:02.24#ibcon#read 4, iclass 13, count 0 2006.253.07:54:02.24#ibcon#about to read 5, iclass 13, count 0 2006.253.07:54:02.24#ibcon#read 5, iclass 13, count 0 2006.253.07:54:02.24#ibcon#about to read 6, iclass 13, count 0 2006.253.07:54:02.24#ibcon#read 6, iclass 13, count 0 2006.253.07:54:02.24#ibcon#end of sib2, iclass 13, count 0 2006.253.07:54:02.24#ibcon#*after write, iclass 13, count 0 2006.253.07:54:02.24#ibcon#*before return 0, iclass 13, count 0 2006.253.07:54:02.24#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.253.07:54:02.24#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.253.07:54:02.24#ibcon#about to clear, iclass 13 cls_cnt 0 2006.253.07:54:02.24#ibcon#cleared, iclass 13 cls_cnt 0 2006.253.07:54:02.24$vc4f8/vblo=6,752.99 2006.253.07:54:02.24#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.253.07:54:02.24#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.253.07:54:02.24#ibcon#ireg 17 cls_cnt 0 2006.253.07:54:02.24#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.253.07:54:02.24#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.253.07:54:02.24#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.253.07:54:02.24#ibcon#enter wrdev, iclass 15, count 0 2006.253.07:54:02.24#ibcon#first serial, iclass 15, count 0 2006.253.07:54:02.24#ibcon#enter sib2, iclass 15, count 0 2006.253.07:54:02.24#ibcon#flushed, iclass 15, count 0 2006.253.07:54:02.24#ibcon#about to write, iclass 15, count 0 2006.253.07:54:02.24#ibcon#wrote, iclass 15, count 0 2006.253.07:54:02.24#ibcon#about to read 3, iclass 15, count 0 2006.253.07:54:02.26#ibcon#read 3, iclass 15, count 0 2006.253.07:54:02.26#ibcon#about to read 4, iclass 15, count 0 2006.253.07:54:02.26#ibcon#read 4, iclass 15, count 0 2006.253.07:54:02.26#ibcon#about to read 5, iclass 15, count 0 2006.253.07:54:02.26#ibcon#read 5, iclass 15, count 0 2006.253.07:54:02.26#ibcon#about to read 6, iclass 15, count 0 2006.253.07:54:02.26#ibcon#read 6, iclass 15, count 0 2006.253.07:54:02.26#ibcon#end of sib2, iclass 15, count 0 2006.253.07:54:02.26#ibcon#*mode == 0, iclass 15, count 0 2006.253.07:54:02.26#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.253.07:54:02.26#ibcon#[28=FRQ=06,752.99\r\n] 2006.253.07:54:02.26#ibcon#*before write, iclass 15, count 0 2006.253.07:54:02.26#ibcon#enter sib2, iclass 15, count 0 2006.253.07:54:02.26#ibcon#flushed, iclass 15, count 0 2006.253.07:54:02.26#ibcon#about to write, iclass 15, count 0 2006.253.07:54:02.26#ibcon#wrote, iclass 15, count 0 2006.253.07:54:02.26#ibcon#about to read 3, iclass 15, count 0 2006.253.07:54:02.30#ibcon#read 3, iclass 15, count 0 2006.253.07:54:02.30#ibcon#about to read 4, iclass 15, count 0 2006.253.07:54:02.30#ibcon#read 4, iclass 15, count 0 2006.253.07:54:02.30#ibcon#about to read 5, iclass 15, count 0 2006.253.07:54:02.30#ibcon#read 5, iclass 15, count 0 2006.253.07:54:02.30#ibcon#about to read 6, iclass 15, count 0 2006.253.07:54:02.30#ibcon#read 6, iclass 15, count 0 2006.253.07:54:02.30#ibcon#end of sib2, iclass 15, count 0 2006.253.07:54:02.30#ibcon#*after write, iclass 15, count 0 2006.253.07:54:02.30#ibcon#*before return 0, iclass 15, count 0 2006.253.07:54:02.30#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.253.07:54:02.30#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.253.07:54:02.30#ibcon#about to clear, iclass 15 cls_cnt 0 2006.253.07:54:02.30#ibcon#cleared, iclass 15 cls_cnt 0 2006.253.07:54:02.30$vc4f8/vb=6,4 2006.253.07:54:02.30#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.253.07:54:02.30#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.253.07:54:02.30#ibcon#ireg 11 cls_cnt 2 2006.253.07:54:02.30#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.253.07:54:02.36#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.253.07:54:02.36#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.253.07:54:02.36#ibcon#enter wrdev, iclass 17, count 2 2006.253.07:54:02.36#ibcon#first serial, iclass 17, count 2 2006.253.07:54:02.36#ibcon#enter sib2, iclass 17, count 2 2006.253.07:54:02.36#ibcon#flushed, iclass 17, count 2 2006.253.07:54:02.36#ibcon#about to write, iclass 17, count 2 2006.253.07:54:02.36#ibcon#wrote, iclass 17, count 2 2006.253.07:54:02.36#ibcon#about to read 3, iclass 17, count 2 2006.253.07:54:02.38#ibcon#read 3, iclass 17, count 2 2006.253.07:54:02.38#ibcon#about to read 4, iclass 17, count 2 2006.253.07:54:02.38#ibcon#read 4, iclass 17, count 2 2006.253.07:54:02.38#ibcon#about to read 5, iclass 17, count 2 2006.253.07:54:02.38#ibcon#read 5, iclass 17, count 2 2006.253.07:54:02.38#ibcon#about to read 6, iclass 17, count 2 2006.253.07:54:02.38#ibcon#read 6, iclass 17, count 2 2006.253.07:54:02.38#ibcon#end of sib2, iclass 17, count 2 2006.253.07:54:02.38#ibcon#*mode == 0, iclass 17, count 2 2006.253.07:54:02.38#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.253.07:54:02.38#ibcon#[27=AT06-04\r\n] 2006.253.07:54:02.38#ibcon#*before write, iclass 17, count 2 2006.253.07:54:02.38#ibcon#enter sib2, iclass 17, count 2 2006.253.07:54:02.38#ibcon#flushed, iclass 17, count 2 2006.253.07:54:02.38#ibcon#about to write, iclass 17, count 2 2006.253.07:54:02.38#ibcon#wrote, iclass 17, count 2 2006.253.07:54:02.38#ibcon#about to read 3, iclass 17, count 2 2006.253.07:54:02.41#ibcon#read 3, iclass 17, count 2 2006.253.07:54:02.41#ibcon#about to read 4, iclass 17, count 2 2006.253.07:54:02.41#ibcon#read 4, iclass 17, count 2 2006.253.07:54:02.41#ibcon#about to read 5, iclass 17, count 2 2006.253.07:54:02.41#ibcon#read 5, iclass 17, count 2 2006.253.07:54:02.41#ibcon#about to read 6, iclass 17, count 2 2006.253.07:54:02.41#ibcon#read 6, iclass 17, count 2 2006.253.07:54:02.41#ibcon#end of sib2, iclass 17, count 2 2006.253.07:54:02.41#ibcon#*after write, iclass 17, count 2 2006.253.07:54:02.41#ibcon#*before return 0, iclass 17, count 2 2006.253.07:54:02.41#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.253.07:54:02.41#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.253.07:54:02.41#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.253.07:54:02.41#ibcon#ireg 7 cls_cnt 0 2006.253.07:54:02.41#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.253.07:54:02.53#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.253.07:54:02.53#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.253.07:54:02.53#ibcon#enter wrdev, iclass 17, count 0 2006.253.07:54:02.53#ibcon#first serial, iclass 17, count 0 2006.253.07:54:02.53#ibcon#enter sib2, iclass 17, count 0 2006.253.07:54:02.53#ibcon#flushed, iclass 17, count 0 2006.253.07:54:02.53#ibcon#about to write, iclass 17, count 0 2006.253.07:54:02.53#ibcon#wrote, iclass 17, count 0 2006.253.07:54:02.53#ibcon#about to read 3, iclass 17, count 0 2006.253.07:54:02.55#ibcon#read 3, iclass 17, count 0 2006.253.07:54:02.55#ibcon#about to read 4, iclass 17, count 0 2006.253.07:54:02.55#ibcon#read 4, iclass 17, count 0 2006.253.07:54:02.55#ibcon#about to read 5, iclass 17, count 0 2006.253.07:54:02.55#ibcon#read 5, iclass 17, count 0 2006.253.07:54:02.55#ibcon#about to read 6, iclass 17, count 0 2006.253.07:54:02.55#ibcon#read 6, iclass 17, count 0 2006.253.07:54:02.55#ibcon#end of sib2, iclass 17, count 0 2006.253.07:54:02.55#ibcon#*mode == 0, iclass 17, count 0 2006.253.07:54:02.55#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.253.07:54:02.55#ibcon#[27=USB\r\n] 2006.253.07:54:02.55#ibcon#*before write, iclass 17, count 0 2006.253.07:54:02.55#ibcon#enter sib2, iclass 17, count 0 2006.253.07:54:02.55#ibcon#flushed, iclass 17, count 0 2006.253.07:54:02.55#ibcon#about to write, iclass 17, count 0 2006.253.07:54:02.55#ibcon#wrote, iclass 17, count 0 2006.253.07:54:02.55#ibcon#about to read 3, iclass 17, count 0 2006.253.07:54:02.58#ibcon#read 3, iclass 17, count 0 2006.253.07:54:02.58#ibcon#about to read 4, iclass 17, count 0 2006.253.07:54:02.58#ibcon#read 4, iclass 17, count 0 2006.253.07:54:02.58#ibcon#about to read 5, iclass 17, count 0 2006.253.07:54:02.58#ibcon#read 5, iclass 17, count 0 2006.253.07:54:02.58#ibcon#about to read 6, iclass 17, count 0 2006.253.07:54:02.58#ibcon#read 6, iclass 17, count 0 2006.253.07:54:02.58#ibcon#end of sib2, iclass 17, count 0 2006.253.07:54:02.58#ibcon#*after write, iclass 17, count 0 2006.253.07:54:02.58#ibcon#*before return 0, iclass 17, count 0 2006.253.07:54:02.58#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.253.07:54:02.58#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.253.07:54:02.58#ibcon#about to clear, iclass 17 cls_cnt 0 2006.253.07:54:02.58#ibcon#cleared, iclass 17 cls_cnt 0 2006.253.07:54:02.58$vc4f8/vabw=wide 2006.253.07:54:02.58#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.253.07:54:02.58#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.253.07:54:02.58#ibcon#ireg 8 cls_cnt 0 2006.253.07:54:02.58#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.253.07:54:02.58#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.253.07:54:02.58#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.253.07:54:02.58#ibcon#enter wrdev, iclass 19, count 0 2006.253.07:54:02.58#ibcon#first serial, iclass 19, count 0 2006.253.07:54:02.58#ibcon#enter sib2, iclass 19, count 0 2006.253.07:54:02.58#ibcon#flushed, iclass 19, count 0 2006.253.07:54:02.58#ibcon#about to write, iclass 19, count 0 2006.253.07:54:02.58#ibcon#wrote, iclass 19, count 0 2006.253.07:54:02.58#ibcon#about to read 3, iclass 19, count 0 2006.253.07:54:02.60#ibcon#read 3, iclass 19, count 0 2006.253.07:54:02.60#ibcon#about to read 4, iclass 19, count 0 2006.253.07:54:02.60#ibcon#read 4, iclass 19, count 0 2006.253.07:54:02.60#ibcon#about to read 5, iclass 19, count 0 2006.253.07:54:02.60#ibcon#read 5, iclass 19, count 0 2006.253.07:54:02.60#ibcon#about to read 6, iclass 19, count 0 2006.253.07:54:02.60#ibcon#read 6, iclass 19, count 0 2006.253.07:54:02.60#ibcon#end of sib2, iclass 19, count 0 2006.253.07:54:02.60#ibcon#*mode == 0, iclass 19, count 0 2006.253.07:54:02.60#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.253.07:54:02.60#ibcon#[25=BW32\r\n] 2006.253.07:54:02.60#ibcon#*before write, iclass 19, count 0 2006.253.07:54:02.60#ibcon#enter sib2, iclass 19, count 0 2006.253.07:54:02.60#ibcon#flushed, iclass 19, count 0 2006.253.07:54:02.60#ibcon#about to write, iclass 19, count 0 2006.253.07:54:02.60#ibcon#wrote, iclass 19, count 0 2006.253.07:54:02.60#ibcon#about to read 3, iclass 19, count 0 2006.253.07:54:02.63#ibcon#read 3, iclass 19, count 0 2006.253.07:54:02.63#ibcon#about to read 4, iclass 19, count 0 2006.253.07:54:02.63#ibcon#read 4, iclass 19, count 0 2006.253.07:54:02.63#ibcon#about to read 5, iclass 19, count 0 2006.253.07:54:02.63#ibcon#read 5, iclass 19, count 0 2006.253.07:54:02.63#ibcon#about to read 6, iclass 19, count 0 2006.253.07:54:02.63#ibcon#read 6, iclass 19, count 0 2006.253.07:54:02.63#ibcon#end of sib2, iclass 19, count 0 2006.253.07:54:02.63#ibcon#*after write, iclass 19, count 0 2006.253.07:54:02.63#ibcon#*before return 0, iclass 19, count 0 2006.253.07:54:02.63#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.253.07:54:02.63#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.253.07:54:02.63#ibcon#about to clear, iclass 19 cls_cnt 0 2006.253.07:54:02.63#ibcon#cleared, iclass 19 cls_cnt 0 2006.253.07:54:02.63$vc4f8/vbbw=wide 2006.253.07:54:02.63#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.253.07:54:02.63#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.253.07:54:02.63#ibcon#ireg 8 cls_cnt 0 2006.253.07:54:02.63#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.253.07:54:02.70#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.253.07:54:02.70#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.253.07:54:02.70#ibcon#enter wrdev, iclass 21, count 0 2006.253.07:54:02.70#ibcon#first serial, iclass 21, count 0 2006.253.07:54:02.70#ibcon#enter sib2, iclass 21, count 0 2006.253.07:54:02.70#ibcon#flushed, iclass 21, count 0 2006.253.07:54:02.70#ibcon#about to write, iclass 21, count 0 2006.253.07:54:02.70#ibcon#wrote, iclass 21, count 0 2006.253.07:54:02.70#ibcon#about to read 3, iclass 21, count 0 2006.253.07:54:02.72#ibcon#read 3, iclass 21, count 0 2006.253.07:54:02.72#ibcon#about to read 4, iclass 21, count 0 2006.253.07:54:02.72#ibcon#read 4, iclass 21, count 0 2006.253.07:54:02.72#ibcon#about to read 5, iclass 21, count 0 2006.253.07:54:02.72#ibcon#read 5, iclass 21, count 0 2006.253.07:54:02.72#ibcon#about to read 6, iclass 21, count 0 2006.253.07:54:02.72#ibcon#read 6, iclass 21, count 0 2006.253.07:54:02.72#ibcon#end of sib2, iclass 21, count 0 2006.253.07:54:02.72#ibcon#*mode == 0, iclass 21, count 0 2006.253.07:54:02.72#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.253.07:54:02.72#ibcon#[27=BW32\r\n] 2006.253.07:54:02.72#ibcon#*before write, iclass 21, count 0 2006.253.07:54:02.72#ibcon#enter sib2, iclass 21, count 0 2006.253.07:54:02.72#ibcon#flushed, iclass 21, count 0 2006.253.07:54:02.72#ibcon#about to write, iclass 21, count 0 2006.253.07:54:02.72#ibcon#wrote, iclass 21, count 0 2006.253.07:54:02.72#ibcon#about to read 3, iclass 21, count 0 2006.253.07:54:02.75#ibcon#read 3, iclass 21, count 0 2006.253.07:54:02.75#ibcon#about to read 4, iclass 21, count 0 2006.253.07:54:02.75#ibcon#read 4, iclass 21, count 0 2006.253.07:54:02.75#ibcon#about to read 5, iclass 21, count 0 2006.253.07:54:02.75#ibcon#read 5, iclass 21, count 0 2006.253.07:54:02.75#ibcon#about to read 6, iclass 21, count 0 2006.253.07:54:02.75#ibcon#read 6, iclass 21, count 0 2006.253.07:54:02.75#ibcon#end of sib2, iclass 21, count 0 2006.253.07:54:02.75#ibcon#*after write, iclass 21, count 0 2006.253.07:54:02.75#ibcon#*before return 0, iclass 21, count 0 2006.253.07:54:02.75#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.253.07:54:02.75#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.253.07:54:02.75#ibcon#about to clear, iclass 21 cls_cnt 0 2006.253.07:54:02.75#ibcon#cleared, iclass 21 cls_cnt 0 2006.253.07:54:02.75$4f8m12a/ifd4f 2006.253.07:54:02.75$ifd4f/lo= 2006.253.07:54:02.75$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.253.07:54:02.75$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.253.07:54:02.75$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.253.07:54:02.75$ifd4f/patch= 2006.253.07:54:02.75$ifd4f/patch=lo1,a1,a2,a3,a4 2006.253.07:54:02.75$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.253.07:54:02.75$ifd4f/patch=lo3,a5,a6,a7,a8 2006.253.07:54:02.75$4f8m12a/"form=m,16.000,1:2 2006.253.07:54:02.75$4f8m12a/"tpicd 2006.253.07:54:02.75$4f8m12a/echo=off 2006.253.07:54:02.75$4f8m12a/xlog=off 2006.253.07:54:02.75:!2006.253.07:55:10 2006.253.07:54:15.14#trakl#Source acquired 2006.253.07:54:17.13#flagr#flagr/antenna,acquired 2006.253.07:55:10.00:preob 2006.253.07:55:10.13/onsource/TRACKING 2006.253.07:55:10.13:!2006.253.07:55:20 2006.253.07:55:20.00:data_valid=on 2006.253.07:55:20.00:midob 2006.253.07:55:20.13/onsource/TRACKING 2006.253.07:55:20.13/wx/31.21,1006.4,74 2006.253.07:55:20.19/cable/+6.3692E-03 2006.253.07:55:21.28/va/01,08,usb,yes,45,48 2006.253.07:55:21.28/va/02,07,usb,yes,45,47 2006.253.07:55:21.28/va/03,06,usb,yes,48,48 2006.253.07:55:21.28/va/04,07,usb,yes,46,50 2006.253.07:55:21.28/va/05,07,usb,yes,48,51 2006.253.07:55:21.28/va/06,07,usb,yes,42,42 2006.253.07:55:21.28/va/07,07,usb,yes,42,42 2006.253.07:55:21.28/va/08,07,usb,yes,45,44 2006.253.07:55:21.51/valo/01,532.99,yes,locked 2006.253.07:55:21.51/valo/02,572.99,yes,locked 2006.253.07:55:21.51/valo/03,672.99,yes,locked 2006.253.07:55:21.51/valo/04,832.99,yes,locked 2006.253.07:55:21.51/valo/05,652.99,yes,locked 2006.253.07:55:21.51/valo/06,772.99,yes,locked 2006.253.07:55:21.51/valo/07,832.99,yes,locked 2006.253.07:55:21.51/valo/08,852.99,yes,locked 2006.253.07:55:22.60/vb/01,04,usb,yes,41,40 2006.253.07:55:22.60/vb/02,05,usb,yes,38,40 2006.253.07:55:22.60/vb/03,04,usb,yes,39,44 2006.253.07:55:22.60/vb/04,04,usb,yes,40,41 2006.253.07:55:22.60/vb/05,04,usb,yes,38,43 2006.253.07:55:22.60/vb/06,04,usb,yes,39,43 2006.253.07:55:22.60/vb/07,04,usb,yes,42,42 2006.253.07:55:22.60/vb/08,04,usb,yes,38,43 2006.253.07:55:22.83/vblo/01,632.99,yes,locked 2006.253.07:55:22.83/vblo/02,640.99,yes,locked 2006.253.07:55:22.83/vblo/03,656.99,yes,locked 2006.253.07:55:22.83/vblo/04,712.99,yes,locked 2006.253.07:55:22.83/vblo/05,744.99,yes,locked 2006.253.07:55:22.83/vblo/06,752.99,yes,locked 2006.253.07:55:22.83/vblo/07,734.99,yes,locked 2006.253.07:55:22.83/vblo/08,744.99,yes,locked 2006.253.07:55:22.98/vabw/8 2006.253.07:55:23.13/vbbw/8 2006.253.07:55:23.22/xfe/off,on,14.2 2006.253.07:55:23.59/ifatt/23,28,28,28 2006.253.07:55:24.07/fmout-gps/S +4.72E-07 2006.253.07:55:24.15:!2006.253.07:56:20 2006.253.07:56:20.00:data_valid=off 2006.253.07:56:20.01:postob 2006.253.07:56:20.16/cable/+6.3696E-03 2006.253.07:56:20.17/wx/31.19,1006.3,74 2006.253.07:56:21.07/fmout-gps/S +4.74E-07 2006.253.07:56:21.08:scan_name=253-0758,k06253,60 2006.253.07:56:21.08:source=0059+581,010245.76,582411.1,2000.0,cw 2006.253.07:56:21.13#flagr#flagr/antenna,new-source 2006.253.07:56:22.14:checkk5 2006.253.07:56:22.53/chk_autoobs//k5ts1/ autoobs is running! 2006.253.07:56:22.89/chk_autoobs//k5ts2/ autoobs is running! 2006.253.07:56:23.28/chk_autoobs//k5ts3/ autoobs is running! 2006.253.07:56:23.65/chk_autoobs//k5ts4/ autoobs is running! 2006.253.07:56:24.02/chk_obsdata//k5ts1/T2530755??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.07:56:24.39/chk_obsdata//k5ts2/T2530755??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.07:56:24.79/chk_obsdata//k5ts3/T2530755??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.07:56:25.16/chk_obsdata//k5ts4/T2530755??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.07:56:25.86/k5log//k5ts1_log_newline 2006.253.07:56:26.55/k5log//k5ts2_log_newline 2006.253.07:56:27.24/k5log//k5ts3_log_newline 2006.253.07:56:27.93/k5log//k5ts4_log_newline 2006.253.07:56:27.95/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.253.07:56:27.95:4f8m12a=2 2006.253.07:56:27.95$4f8m12a/echo=on 2006.253.07:56:27.95$4f8m12a/pcalon 2006.253.07:56:27.95$pcalon/"no phase cal control is implemented here 2006.253.07:56:27.95$4f8m12a/"tpicd=stop 2006.253.07:56:27.95$4f8m12a/vc4f8 2006.253.07:56:27.95$vc4f8/valo=1,532.99 2006.253.07:56:27.96#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.253.07:56:27.96#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.253.07:56:27.96#ibcon#ireg 17 cls_cnt 0 2006.253.07:56:27.96#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.253.07:56:27.96#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.253.07:56:27.96#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.253.07:56:27.96#ibcon#enter wrdev, iclass 6, count 0 2006.253.07:56:27.96#ibcon#first serial, iclass 6, count 0 2006.253.07:56:27.96#ibcon#enter sib2, iclass 6, count 0 2006.253.07:56:27.96#ibcon#flushed, iclass 6, count 0 2006.253.07:56:27.96#ibcon#about to write, iclass 6, count 0 2006.253.07:56:27.96#ibcon#wrote, iclass 6, count 0 2006.253.07:56:27.96#ibcon#about to read 3, iclass 6, count 0 2006.253.07:56:28.00#ibcon#read 3, iclass 6, count 0 2006.253.07:56:28.00#ibcon#about to read 4, iclass 6, count 0 2006.253.07:56:28.00#ibcon#read 4, iclass 6, count 0 2006.253.07:56:28.00#ibcon#about to read 5, iclass 6, count 0 2006.253.07:56:28.00#ibcon#read 5, iclass 6, count 0 2006.253.07:56:28.00#ibcon#about to read 6, iclass 6, count 0 2006.253.07:56:28.00#ibcon#read 6, iclass 6, count 0 2006.253.07:56:28.00#ibcon#end of sib2, iclass 6, count 0 2006.253.07:56:28.00#ibcon#*mode == 0, iclass 6, count 0 2006.253.07:56:28.00#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.253.07:56:28.00#ibcon#[26=FRQ=01,532.99\r\n] 2006.253.07:56:28.00#ibcon#*before write, iclass 6, count 0 2006.253.07:56:28.00#ibcon#enter sib2, iclass 6, count 0 2006.253.07:56:28.00#ibcon#flushed, iclass 6, count 0 2006.253.07:56:28.00#ibcon#about to write, iclass 6, count 0 2006.253.07:56:28.00#ibcon#wrote, iclass 6, count 0 2006.253.07:56:28.00#ibcon#about to read 3, iclass 6, count 0 2006.253.07:56:28.04#ibcon#read 3, iclass 6, count 0 2006.253.07:56:28.04#ibcon#about to read 4, iclass 6, count 0 2006.253.07:56:28.04#ibcon#read 4, iclass 6, count 0 2006.253.07:56:28.04#ibcon#about to read 5, iclass 6, count 0 2006.253.07:56:28.04#ibcon#read 5, iclass 6, count 0 2006.253.07:56:28.04#ibcon#about to read 6, iclass 6, count 0 2006.253.07:56:28.04#ibcon#read 6, iclass 6, count 0 2006.253.07:56:28.04#ibcon#end of sib2, iclass 6, count 0 2006.253.07:56:28.04#ibcon#*after write, iclass 6, count 0 2006.253.07:56:28.04#ibcon#*before return 0, iclass 6, count 0 2006.253.07:56:28.04#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.253.07:56:28.04#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.253.07:56:28.04#ibcon#about to clear, iclass 6 cls_cnt 0 2006.253.07:56:28.04#ibcon#cleared, iclass 6 cls_cnt 0 2006.253.07:56:28.04$vc4f8/va=1,8 2006.253.07:56:28.04#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.253.07:56:28.04#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.253.07:56:28.04#ibcon#ireg 11 cls_cnt 2 2006.253.07:56:28.04#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.253.07:56:28.04#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.253.07:56:28.04#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.253.07:56:28.04#ibcon#enter wrdev, iclass 10, count 2 2006.253.07:56:28.04#ibcon#first serial, iclass 10, count 2 2006.253.07:56:28.04#ibcon#enter sib2, iclass 10, count 2 2006.253.07:56:28.04#ibcon#flushed, iclass 10, count 2 2006.253.07:56:28.04#ibcon#about to write, iclass 10, count 2 2006.253.07:56:28.04#ibcon#wrote, iclass 10, count 2 2006.253.07:56:28.04#ibcon#about to read 3, iclass 10, count 2 2006.253.07:56:28.06#ibcon#read 3, iclass 10, count 2 2006.253.07:56:28.06#ibcon#about to read 4, iclass 10, count 2 2006.253.07:56:28.06#ibcon#read 4, iclass 10, count 2 2006.253.07:56:28.06#ibcon#about to read 5, iclass 10, count 2 2006.253.07:56:28.06#ibcon#read 5, iclass 10, count 2 2006.253.07:56:28.06#ibcon#about to read 6, iclass 10, count 2 2006.253.07:56:28.06#ibcon#read 6, iclass 10, count 2 2006.253.07:56:28.06#ibcon#end of sib2, iclass 10, count 2 2006.253.07:56:28.06#ibcon#*mode == 0, iclass 10, count 2 2006.253.07:56:28.06#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.253.07:56:28.06#ibcon#[25=AT01-08\r\n] 2006.253.07:56:28.06#ibcon#*before write, iclass 10, count 2 2006.253.07:56:28.06#ibcon#enter sib2, iclass 10, count 2 2006.253.07:56:28.06#ibcon#flushed, iclass 10, count 2 2006.253.07:56:28.06#ibcon#about to write, iclass 10, count 2 2006.253.07:56:28.06#ibcon#wrote, iclass 10, count 2 2006.253.07:56:28.06#ibcon#about to read 3, iclass 10, count 2 2006.253.07:56:28.09#ibcon#read 3, iclass 10, count 2 2006.253.07:56:28.09#ibcon#about to read 4, iclass 10, count 2 2006.253.07:56:28.09#ibcon#read 4, iclass 10, count 2 2006.253.07:56:28.09#ibcon#about to read 5, iclass 10, count 2 2006.253.07:56:28.09#ibcon#read 5, iclass 10, count 2 2006.253.07:56:28.09#ibcon#about to read 6, iclass 10, count 2 2006.253.07:56:28.09#ibcon#read 6, iclass 10, count 2 2006.253.07:56:28.09#ibcon#end of sib2, iclass 10, count 2 2006.253.07:56:28.09#ibcon#*after write, iclass 10, count 2 2006.253.07:56:28.09#ibcon#*before return 0, iclass 10, count 2 2006.253.07:56:28.09#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.253.07:56:28.09#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.253.07:56:28.09#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.253.07:56:28.09#ibcon#ireg 7 cls_cnt 0 2006.253.07:56:28.09#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.253.07:56:28.21#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.253.07:56:28.21#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.253.07:56:28.21#ibcon#enter wrdev, iclass 10, count 0 2006.253.07:56:28.21#ibcon#first serial, iclass 10, count 0 2006.253.07:56:28.21#ibcon#enter sib2, iclass 10, count 0 2006.253.07:56:28.21#ibcon#flushed, iclass 10, count 0 2006.253.07:56:28.21#ibcon#about to write, iclass 10, count 0 2006.253.07:56:28.21#ibcon#wrote, iclass 10, count 0 2006.253.07:56:28.21#ibcon#about to read 3, iclass 10, count 0 2006.253.07:56:28.23#ibcon#read 3, iclass 10, count 0 2006.253.07:56:28.23#ibcon#about to read 4, iclass 10, count 0 2006.253.07:56:28.23#ibcon#read 4, iclass 10, count 0 2006.253.07:56:28.23#ibcon#about to read 5, iclass 10, count 0 2006.253.07:56:28.23#ibcon#read 5, iclass 10, count 0 2006.253.07:56:28.23#ibcon#about to read 6, iclass 10, count 0 2006.253.07:56:28.23#ibcon#read 6, iclass 10, count 0 2006.253.07:56:28.23#ibcon#end of sib2, iclass 10, count 0 2006.253.07:56:28.23#ibcon#*mode == 0, iclass 10, count 0 2006.253.07:56:28.23#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.253.07:56:28.23#ibcon#[25=USB\r\n] 2006.253.07:56:28.23#ibcon#*before write, iclass 10, count 0 2006.253.07:56:28.23#ibcon#enter sib2, iclass 10, count 0 2006.253.07:56:28.23#ibcon#flushed, iclass 10, count 0 2006.253.07:56:28.23#ibcon#about to write, iclass 10, count 0 2006.253.07:56:28.23#ibcon#wrote, iclass 10, count 0 2006.253.07:56:28.23#ibcon#about to read 3, iclass 10, count 0 2006.253.07:56:28.26#ibcon#read 3, iclass 10, count 0 2006.253.07:56:28.26#ibcon#about to read 4, iclass 10, count 0 2006.253.07:56:28.26#ibcon#read 4, iclass 10, count 0 2006.253.07:56:28.26#ibcon#about to read 5, iclass 10, count 0 2006.253.07:56:28.26#ibcon#read 5, iclass 10, count 0 2006.253.07:56:28.26#ibcon#about to read 6, iclass 10, count 0 2006.253.07:56:28.26#ibcon#read 6, iclass 10, count 0 2006.253.07:56:28.26#ibcon#end of sib2, iclass 10, count 0 2006.253.07:56:28.26#ibcon#*after write, iclass 10, count 0 2006.253.07:56:28.26#ibcon#*before return 0, iclass 10, count 0 2006.253.07:56:28.26#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.253.07:56:28.26#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.253.07:56:28.26#ibcon#about to clear, iclass 10 cls_cnt 0 2006.253.07:56:28.26#ibcon#cleared, iclass 10 cls_cnt 0 2006.253.07:56:28.26$vc4f8/valo=2,572.99 2006.253.07:56:28.26#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.253.07:56:28.26#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.253.07:56:28.26#ibcon#ireg 17 cls_cnt 0 2006.253.07:56:28.26#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.253.07:56:28.26#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.253.07:56:28.26#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.253.07:56:28.26#ibcon#enter wrdev, iclass 12, count 0 2006.253.07:56:28.26#ibcon#first serial, iclass 12, count 0 2006.253.07:56:28.26#ibcon#enter sib2, iclass 12, count 0 2006.253.07:56:28.26#ibcon#flushed, iclass 12, count 0 2006.253.07:56:28.26#ibcon#about to write, iclass 12, count 0 2006.253.07:56:28.26#ibcon#wrote, iclass 12, count 0 2006.253.07:56:28.26#ibcon#about to read 3, iclass 12, count 0 2006.253.07:56:28.29#ibcon#read 3, iclass 12, count 0 2006.253.07:56:28.29#ibcon#about to read 4, iclass 12, count 0 2006.253.07:56:28.29#ibcon#read 4, iclass 12, count 0 2006.253.07:56:28.29#ibcon#about to read 5, iclass 12, count 0 2006.253.07:56:28.29#ibcon#read 5, iclass 12, count 0 2006.253.07:56:28.29#ibcon#about to read 6, iclass 12, count 0 2006.253.07:56:28.29#ibcon#read 6, iclass 12, count 0 2006.253.07:56:28.29#ibcon#end of sib2, iclass 12, count 0 2006.253.07:56:28.29#ibcon#*mode == 0, iclass 12, count 0 2006.253.07:56:28.29#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.253.07:56:28.29#ibcon#[26=FRQ=02,572.99\r\n] 2006.253.07:56:28.29#ibcon#*before write, iclass 12, count 0 2006.253.07:56:28.29#ibcon#enter sib2, iclass 12, count 0 2006.253.07:56:28.29#ibcon#flushed, iclass 12, count 0 2006.253.07:56:28.29#ibcon#about to write, iclass 12, count 0 2006.253.07:56:28.29#ibcon#wrote, iclass 12, count 0 2006.253.07:56:28.29#ibcon#about to read 3, iclass 12, count 0 2006.253.07:56:28.33#ibcon#read 3, iclass 12, count 0 2006.253.07:56:28.33#ibcon#about to read 4, iclass 12, count 0 2006.253.07:56:28.33#ibcon#read 4, iclass 12, count 0 2006.253.07:56:28.33#ibcon#about to read 5, iclass 12, count 0 2006.253.07:56:28.33#ibcon#read 5, iclass 12, count 0 2006.253.07:56:28.33#ibcon#about to read 6, iclass 12, count 0 2006.253.07:56:28.33#ibcon#read 6, iclass 12, count 0 2006.253.07:56:28.33#ibcon#end of sib2, iclass 12, count 0 2006.253.07:56:28.33#ibcon#*after write, iclass 12, count 0 2006.253.07:56:28.33#ibcon#*before return 0, iclass 12, count 0 2006.253.07:56:28.33#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.253.07:56:28.33#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.253.07:56:28.33#ibcon#about to clear, iclass 12 cls_cnt 0 2006.253.07:56:28.33#ibcon#cleared, iclass 12 cls_cnt 0 2006.253.07:56:28.33$vc4f8/va=2,7 2006.253.07:56:28.33#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.253.07:56:28.33#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.253.07:56:28.33#ibcon#ireg 11 cls_cnt 2 2006.253.07:56:28.33#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.253.07:56:28.38#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.253.07:56:28.38#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.253.07:56:28.38#ibcon#enter wrdev, iclass 14, count 2 2006.253.07:56:28.38#ibcon#first serial, iclass 14, count 2 2006.253.07:56:28.38#ibcon#enter sib2, iclass 14, count 2 2006.253.07:56:28.38#ibcon#flushed, iclass 14, count 2 2006.253.07:56:28.38#ibcon#about to write, iclass 14, count 2 2006.253.07:56:28.38#ibcon#wrote, iclass 14, count 2 2006.253.07:56:28.38#ibcon#about to read 3, iclass 14, count 2 2006.253.07:56:28.40#ibcon#read 3, iclass 14, count 2 2006.253.07:56:28.40#ibcon#about to read 4, iclass 14, count 2 2006.253.07:56:28.40#ibcon#read 4, iclass 14, count 2 2006.253.07:56:28.40#ibcon#about to read 5, iclass 14, count 2 2006.253.07:56:28.40#ibcon#read 5, iclass 14, count 2 2006.253.07:56:28.40#ibcon#about to read 6, iclass 14, count 2 2006.253.07:56:28.40#ibcon#read 6, iclass 14, count 2 2006.253.07:56:28.40#ibcon#end of sib2, iclass 14, count 2 2006.253.07:56:28.40#ibcon#*mode == 0, iclass 14, count 2 2006.253.07:56:28.40#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.253.07:56:28.40#ibcon#[25=AT02-07\r\n] 2006.253.07:56:28.40#ibcon#*before write, iclass 14, count 2 2006.253.07:56:28.40#ibcon#enter sib2, iclass 14, count 2 2006.253.07:56:28.40#ibcon#flushed, iclass 14, count 2 2006.253.07:56:28.40#ibcon#about to write, iclass 14, count 2 2006.253.07:56:28.40#ibcon#wrote, iclass 14, count 2 2006.253.07:56:28.40#ibcon#about to read 3, iclass 14, count 2 2006.253.07:56:28.43#ibcon#read 3, iclass 14, count 2 2006.253.07:56:28.43#ibcon#about to read 4, iclass 14, count 2 2006.253.07:56:28.43#ibcon#read 4, iclass 14, count 2 2006.253.07:56:28.43#ibcon#about to read 5, iclass 14, count 2 2006.253.07:56:28.43#ibcon#read 5, iclass 14, count 2 2006.253.07:56:28.43#ibcon#about to read 6, iclass 14, count 2 2006.253.07:56:28.43#ibcon#read 6, iclass 14, count 2 2006.253.07:56:28.43#ibcon#end of sib2, iclass 14, count 2 2006.253.07:56:28.43#ibcon#*after write, iclass 14, count 2 2006.253.07:56:28.43#ibcon#*before return 0, iclass 14, count 2 2006.253.07:56:28.43#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.253.07:56:28.43#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.253.07:56:28.43#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.253.07:56:28.43#ibcon#ireg 7 cls_cnt 0 2006.253.07:56:28.43#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.253.07:56:28.55#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.253.07:56:28.55#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.253.07:56:28.55#ibcon#enter wrdev, iclass 14, count 0 2006.253.07:56:28.55#ibcon#first serial, iclass 14, count 0 2006.253.07:56:28.55#ibcon#enter sib2, iclass 14, count 0 2006.253.07:56:28.55#ibcon#flushed, iclass 14, count 0 2006.253.07:56:28.55#ibcon#about to write, iclass 14, count 0 2006.253.07:56:28.55#ibcon#wrote, iclass 14, count 0 2006.253.07:56:28.55#ibcon#about to read 3, iclass 14, count 0 2006.253.07:56:28.57#ibcon#read 3, iclass 14, count 0 2006.253.07:56:28.57#ibcon#about to read 4, iclass 14, count 0 2006.253.07:56:28.57#ibcon#read 4, iclass 14, count 0 2006.253.07:56:28.57#ibcon#about to read 5, iclass 14, count 0 2006.253.07:56:28.57#ibcon#read 5, iclass 14, count 0 2006.253.07:56:28.57#ibcon#about to read 6, iclass 14, count 0 2006.253.07:56:28.57#ibcon#read 6, iclass 14, count 0 2006.253.07:56:28.57#ibcon#end of sib2, iclass 14, count 0 2006.253.07:56:28.57#ibcon#*mode == 0, iclass 14, count 0 2006.253.07:56:28.57#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.253.07:56:28.57#ibcon#[25=USB\r\n] 2006.253.07:56:28.57#ibcon#*before write, iclass 14, count 0 2006.253.07:56:28.57#ibcon#enter sib2, iclass 14, count 0 2006.253.07:56:28.57#ibcon#flushed, iclass 14, count 0 2006.253.07:56:28.57#ibcon#about to write, iclass 14, count 0 2006.253.07:56:28.57#ibcon#wrote, iclass 14, count 0 2006.253.07:56:28.57#ibcon#about to read 3, iclass 14, count 0 2006.253.07:56:28.60#ibcon#read 3, iclass 14, count 0 2006.253.07:56:28.60#ibcon#about to read 4, iclass 14, count 0 2006.253.07:56:28.60#ibcon#read 4, iclass 14, count 0 2006.253.07:56:28.60#ibcon#about to read 5, iclass 14, count 0 2006.253.07:56:28.60#ibcon#read 5, iclass 14, count 0 2006.253.07:56:28.60#ibcon#about to read 6, iclass 14, count 0 2006.253.07:56:28.60#ibcon#read 6, iclass 14, count 0 2006.253.07:56:28.60#ibcon#end of sib2, iclass 14, count 0 2006.253.07:56:28.60#ibcon#*after write, iclass 14, count 0 2006.253.07:56:28.60#ibcon#*before return 0, iclass 14, count 0 2006.253.07:56:28.60#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.253.07:56:28.60#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.253.07:56:28.60#ibcon#about to clear, iclass 14 cls_cnt 0 2006.253.07:56:28.60#ibcon#cleared, iclass 14 cls_cnt 0 2006.253.07:56:28.60$vc4f8/valo=3,672.99 2006.253.07:56:28.60#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.253.07:56:28.60#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.253.07:56:28.60#ibcon#ireg 17 cls_cnt 0 2006.253.07:56:28.60#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.253.07:56:28.60#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.253.07:56:28.60#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.253.07:56:28.60#ibcon#enter wrdev, iclass 16, count 0 2006.253.07:56:28.60#ibcon#first serial, iclass 16, count 0 2006.253.07:56:28.60#ibcon#enter sib2, iclass 16, count 0 2006.253.07:56:28.60#ibcon#flushed, iclass 16, count 0 2006.253.07:56:28.60#ibcon#about to write, iclass 16, count 0 2006.253.07:56:28.60#ibcon#wrote, iclass 16, count 0 2006.253.07:56:28.60#ibcon#about to read 3, iclass 16, count 0 2006.253.07:56:28.63#ibcon#read 3, iclass 16, count 0 2006.253.07:56:28.63#ibcon#about to read 4, iclass 16, count 0 2006.253.07:56:28.63#ibcon#read 4, iclass 16, count 0 2006.253.07:56:28.63#ibcon#about to read 5, iclass 16, count 0 2006.253.07:56:28.63#ibcon#read 5, iclass 16, count 0 2006.253.07:56:28.63#ibcon#about to read 6, iclass 16, count 0 2006.253.07:56:28.63#ibcon#read 6, iclass 16, count 0 2006.253.07:56:28.63#ibcon#end of sib2, iclass 16, count 0 2006.253.07:56:28.63#ibcon#*mode == 0, iclass 16, count 0 2006.253.07:56:28.63#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.253.07:56:28.63#ibcon#[26=FRQ=03,672.99\r\n] 2006.253.07:56:28.63#ibcon#*before write, iclass 16, count 0 2006.253.07:56:28.63#ibcon#enter sib2, iclass 16, count 0 2006.253.07:56:28.63#ibcon#flushed, iclass 16, count 0 2006.253.07:56:28.63#ibcon#about to write, iclass 16, count 0 2006.253.07:56:28.63#ibcon#wrote, iclass 16, count 0 2006.253.07:56:28.63#ibcon#about to read 3, iclass 16, count 0 2006.253.07:56:28.67#ibcon#read 3, iclass 16, count 0 2006.253.07:56:28.67#ibcon#about to read 4, iclass 16, count 0 2006.253.07:56:28.67#ibcon#read 4, iclass 16, count 0 2006.253.07:56:28.67#ibcon#about to read 5, iclass 16, count 0 2006.253.07:56:28.67#ibcon#read 5, iclass 16, count 0 2006.253.07:56:28.67#ibcon#about to read 6, iclass 16, count 0 2006.253.07:56:28.67#ibcon#read 6, iclass 16, count 0 2006.253.07:56:28.67#ibcon#end of sib2, iclass 16, count 0 2006.253.07:56:28.67#ibcon#*after write, iclass 16, count 0 2006.253.07:56:28.67#ibcon#*before return 0, iclass 16, count 0 2006.253.07:56:28.67#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.253.07:56:28.67#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.253.07:56:28.67#ibcon#about to clear, iclass 16 cls_cnt 0 2006.253.07:56:28.67#ibcon#cleared, iclass 16 cls_cnt 0 2006.253.07:56:28.67$vc4f8/va=3,6 2006.253.07:56:28.67#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.253.07:56:28.67#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.253.07:56:28.67#ibcon#ireg 11 cls_cnt 2 2006.253.07:56:28.67#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.253.07:56:28.72#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.253.07:56:28.72#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.253.07:56:28.72#ibcon#enter wrdev, iclass 18, count 2 2006.253.07:56:28.72#ibcon#first serial, iclass 18, count 2 2006.253.07:56:28.72#ibcon#enter sib2, iclass 18, count 2 2006.253.07:56:28.72#ibcon#flushed, iclass 18, count 2 2006.253.07:56:28.72#ibcon#about to write, iclass 18, count 2 2006.253.07:56:28.72#ibcon#wrote, iclass 18, count 2 2006.253.07:56:28.72#ibcon#about to read 3, iclass 18, count 2 2006.253.07:56:28.74#ibcon#read 3, iclass 18, count 2 2006.253.07:56:28.74#ibcon#about to read 4, iclass 18, count 2 2006.253.07:56:28.74#ibcon#read 4, iclass 18, count 2 2006.253.07:56:28.74#ibcon#about to read 5, iclass 18, count 2 2006.253.07:56:28.74#ibcon#read 5, iclass 18, count 2 2006.253.07:56:28.74#ibcon#about to read 6, iclass 18, count 2 2006.253.07:56:28.74#ibcon#read 6, iclass 18, count 2 2006.253.07:56:28.74#ibcon#end of sib2, iclass 18, count 2 2006.253.07:56:28.74#ibcon#*mode == 0, iclass 18, count 2 2006.253.07:56:28.74#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.253.07:56:28.74#ibcon#[25=AT03-06\r\n] 2006.253.07:56:28.74#ibcon#*before write, iclass 18, count 2 2006.253.07:56:28.74#ibcon#enter sib2, iclass 18, count 2 2006.253.07:56:28.74#ibcon#flushed, iclass 18, count 2 2006.253.07:56:28.74#ibcon#about to write, iclass 18, count 2 2006.253.07:56:28.74#ibcon#wrote, iclass 18, count 2 2006.253.07:56:28.74#ibcon#about to read 3, iclass 18, count 2 2006.253.07:56:28.77#ibcon#read 3, iclass 18, count 2 2006.253.07:56:28.77#ibcon#about to read 4, iclass 18, count 2 2006.253.07:56:28.77#ibcon#read 4, iclass 18, count 2 2006.253.07:56:28.77#ibcon#about to read 5, iclass 18, count 2 2006.253.07:56:28.77#ibcon#read 5, iclass 18, count 2 2006.253.07:56:28.77#ibcon#about to read 6, iclass 18, count 2 2006.253.07:56:28.77#ibcon#read 6, iclass 18, count 2 2006.253.07:56:28.77#ibcon#end of sib2, iclass 18, count 2 2006.253.07:56:28.77#ibcon#*after write, iclass 18, count 2 2006.253.07:56:28.77#ibcon#*before return 0, iclass 18, count 2 2006.253.07:56:28.77#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.253.07:56:28.77#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.253.07:56:28.77#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.253.07:56:28.77#ibcon#ireg 7 cls_cnt 0 2006.253.07:56:28.77#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.253.07:56:28.89#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.253.07:56:28.89#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.253.07:56:28.89#ibcon#enter wrdev, iclass 18, count 0 2006.253.07:56:28.89#ibcon#first serial, iclass 18, count 0 2006.253.07:56:28.89#ibcon#enter sib2, iclass 18, count 0 2006.253.07:56:28.89#ibcon#flushed, iclass 18, count 0 2006.253.07:56:28.89#ibcon#about to write, iclass 18, count 0 2006.253.07:56:28.89#ibcon#wrote, iclass 18, count 0 2006.253.07:56:28.89#ibcon#about to read 3, iclass 18, count 0 2006.253.07:56:28.90#abcon#<5=/07 1.4 3.4 31.18 741006.3\r\n> 2006.253.07:56:28.91#ibcon#read 3, iclass 18, count 0 2006.253.07:56:28.91#ibcon#about to read 4, iclass 18, count 0 2006.253.07:56:28.91#ibcon#read 4, iclass 18, count 0 2006.253.07:56:28.91#ibcon#about to read 5, iclass 18, count 0 2006.253.07:56:28.91#ibcon#read 5, iclass 18, count 0 2006.253.07:56:28.91#ibcon#about to read 6, iclass 18, count 0 2006.253.07:56:28.91#ibcon#read 6, iclass 18, count 0 2006.253.07:56:28.91#ibcon#end of sib2, iclass 18, count 0 2006.253.07:56:28.91#ibcon#*mode == 0, iclass 18, count 0 2006.253.07:56:28.91#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.253.07:56:28.91#ibcon#[25=USB\r\n] 2006.253.07:56:28.91#ibcon#*before write, iclass 18, count 0 2006.253.07:56:28.91#ibcon#enter sib2, iclass 18, count 0 2006.253.07:56:28.91#ibcon#flushed, iclass 18, count 0 2006.253.07:56:28.91#ibcon#about to write, iclass 18, count 0 2006.253.07:56:28.91#ibcon#wrote, iclass 18, count 0 2006.253.07:56:28.91#ibcon#about to read 3, iclass 18, count 0 2006.253.07:56:28.92#abcon#{5=INTERFACE CLEAR} 2006.253.07:56:28.94#ibcon#read 3, iclass 18, count 0 2006.253.07:56:28.94#ibcon#about to read 4, iclass 18, count 0 2006.253.07:56:28.94#ibcon#read 4, iclass 18, count 0 2006.253.07:56:28.94#ibcon#about to read 5, iclass 18, count 0 2006.253.07:56:28.94#ibcon#read 5, iclass 18, count 0 2006.253.07:56:28.94#ibcon#about to read 6, iclass 18, count 0 2006.253.07:56:28.94#ibcon#read 6, iclass 18, count 0 2006.253.07:56:28.94#ibcon#end of sib2, iclass 18, count 0 2006.253.07:56:28.94#ibcon#*after write, iclass 18, count 0 2006.253.07:56:28.94#ibcon#*before return 0, iclass 18, count 0 2006.253.07:56:28.94#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.253.07:56:28.94#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.253.07:56:28.94#ibcon#about to clear, iclass 18 cls_cnt 0 2006.253.07:56:28.94#ibcon#cleared, iclass 18 cls_cnt 0 2006.253.07:56:28.94$vc4f8/valo=4,832.99 2006.253.07:56:28.94#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.253.07:56:28.94#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.253.07:56:28.94#ibcon#ireg 17 cls_cnt 0 2006.253.07:56:28.94#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.253.07:56:28.94#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.253.07:56:28.94#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.253.07:56:28.94#ibcon#enter wrdev, iclass 23, count 0 2006.253.07:56:28.94#ibcon#first serial, iclass 23, count 0 2006.253.07:56:28.94#ibcon#enter sib2, iclass 23, count 0 2006.253.07:56:28.94#ibcon#flushed, iclass 23, count 0 2006.253.07:56:28.94#ibcon#about to write, iclass 23, count 0 2006.253.07:56:28.94#ibcon#wrote, iclass 23, count 0 2006.253.07:56:28.94#ibcon#about to read 3, iclass 23, count 0 2006.253.07:56:28.96#ibcon#read 3, iclass 23, count 0 2006.253.07:56:28.96#ibcon#about to read 4, iclass 23, count 0 2006.253.07:56:28.96#ibcon#read 4, iclass 23, count 0 2006.253.07:56:28.96#ibcon#about to read 5, iclass 23, count 0 2006.253.07:56:28.96#ibcon#read 5, iclass 23, count 0 2006.253.07:56:28.96#ibcon#about to read 6, iclass 23, count 0 2006.253.07:56:28.96#ibcon#read 6, iclass 23, count 0 2006.253.07:56:28.96#ibcon#end of sib2, iclass 23, count 0 2006.253.07:56:28.96#ibcon#*mode == 0, iclass 23, count 0 2006.253.07:56:28.96#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.253.07:56:28.96#ibcon#[26=FRQ=04,832.99\r\n] 2006.253.07:56:28.96#ibcon#*before write, iclass 23, count 0 2006.253.07:56:28.96#ibcon#enter sib2, iclass 23, count 0 2006.253.07:56:28.96#ibcon#flushed, iclass 23, count 0 2006.253.07:56:28.96#ibcon#about to write, iclass 23, count 0 2006.253.07:56:28.96#ibcon#wrote, iclass 23, count 0 2006.253.07:56:28.96#ibcon#about to read 3, iclass 23, count 0 2006.253.07:56:28.98#abcon#[5=S1D000X0/0*\r\n] 2006.253.07:56:29.00#ibcon#read 3, iclass 23, count 0 2006.253.07:56:29.00#ibcon#about to read 4, iclass 23, count 0 2006.253.07:56:29.00#ibcon#read 4, iclass 23, count 0 2006.253.07:56:29.00#ibcon#about to read 5, iclass 23, count 0 2006.253.07:56:29.00#ibcon#read 5, iclass 23, count 0 2006.253.07:56:29.00#ibcon#about to read 6, iclass 23, count 0 2006.253.07:56:29.00#ibcon#read 6, iclass 23, count 0 2006.253.07:56:29.00#ibcon#end of sib2, iclass 23, count 0 2006.253.07:56:29.00#ibcon#*after write, iclass 23, count 0 2006.253.07:56:29.00#ibcon#*before return 0, iclass 23, count 0 2006.253.07:56:29.00#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.253.07:56:29.00#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.253.07:56:29.00#ibcon#about to clear, iclass 23 cls_cnt 0 2006.253.07:56:29.00#ibcon#cleared, iclass 23 cls_cnt 0 2006.253.07:56:29.00$vc4f8/va=4,7 2006.253.07:56:29.00#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.253.07:56:29.00#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.253.07:56:29.00#ibcon#ireg 11 cls_cnt 2 2006.253.07:56:29.00#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.253.07:56:29.06#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.253.07:56:29.06#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.253.07:56:29.06#ibcon#enter wrdev, iclass 26, count 2 2006.253.07:56:29.06#ibcon#first serial, iclass 26, count 2 2006.253.07:56:29.06#ibcon#enter sib2, iclass 26, count 2 2006.253.07:56:29.06#ibcon#flushed, iclass 26, count 2 2006.253.07:56:29.06#ibcon#about to write, iclass 26, count 2 2006.253.07:56:29.06#ibcon#wrote, iclass 26, count 2 2006.253.07:56:29.06#ibcon#about to read 3, iclass 26, count 2 2006.253.07:56:29.08#ibcon#read 3, iclass 26, count 2 2006.253.07:56:29.08#ibcon#about to read 4, iclass 26, count 2 2006.253.07:56:29.08#ibcon#read 4, iclass 26, count 2 2006.253.07:56:29.08#ibcon#about to read 5, iclass 26, count 2 2006.253.07:56:29.08#ibcon#read 5, iclass 26, count 2 2006.253.07:56:29.08#ibcon#about to read 6, iclass 26, count 2 2006.253.07:56:29.08#ibcon#read 6, iclass 26, count 2 2006.253.07:56:29.08#ibcon#end of sib2, iclass 26, count 2 2006.253.07:56:29.08#ibcon#*mode == 0, iclass 26, count 2 2006.253.07:56:29.08#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.253.07:56:29.08#ibcon#[25=AT04-07\r\n] 2006.253.07:56:29.08#ibcon#*before write, iclass 26, count 2 2006.253.07:56:29.08#ibcon#enter sib2, iclass 26, count 2 2006.253.07:56:29.08#ibcon#flushed, iclass 26, count 2 2006.253.07:56:29.08#ibcon#about to write, iclass 26, count 2 2006.253.07:56:29.08#ibcon#wrote, iclass 26, count 2 2006.253.07:56:29.08#ibcon#about to read 3, iclass 26, count 2 2006.253.07:56:29.11#ibcon#read 3, iclass 26, count 2 2006.253.07:56:29.11#ibcon#about to read 4, iclass 26, count 2 2006.253.07:56:29.11#ibcon#read 4, iclass 26, count 2 2006.253.07:56:29.11#ibcon#about to read 5, iclass 26, count 2 2006.253.07:56:29.11#ibcon#read 5, iclass 26, count 2 2006.253.07:56:29.11#ibcon#about to read 6, iclass 26, count 2 2006.253.07:56:29.11#ibcon#read 6, iclass 26, count 2 2006.253.07:56:29.11#ibcon#end of sib2, iclass 26, count 2 2006.253.07:56:29.11#ibcon#*after write, iclass 26, count 2 2006.253.07:56:29.11#ibcon#*before return 0, iclass 26, count 2 2006.253.07:56:29.11#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.253.07:56:29.11#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.253.07:56:29.11#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.253.07:56:29.11#ibcon#ireg 7 cls_cnt 0 2006.253.07:56:29.11#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.253.07:56:29.23#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.253.07:56:29.23#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.253.07:56:29.23#ibcon#enter wrdev, iclass 26, count 0 2006.253.07:56:29.23#ibcon#first serial, iclass 26, count 0 2006.253.07:56:29.23#ibcon#enter sib2, iclass 26, count 0 2006.253.07:56:29.23#ibcon#flushed, iclass 26, count 0 2006.253.07:56:29.23#ibcon#about to write, iclass 26, count 0 2006.253.07:56:29.23#ibcon#wrote, iclass 26, count 0 2006.253.07:56:29.23#ibcon#about to read 3, iclass 26, count 0 2006.253.07:56:29.25#ibcon#read 3, iclass 26, count 0 2006.253.07:56:29.25#ibcon#about to read 4, iclass 26, count 0 2006.253.07:56:29.25#ibcon#read 4, iclass 26, count 0 2006.253.07:56:29.25#ibcon#about to read 5, iclass 26, count 0 2006.253.07:56:29.25#ibcon#read 5, iclass 26, count 0 2006.253.07:56:29.25#ibcon#about to read 6, iclass 26, count 0 2006.253.07:56:29.25#ibcon#read 6, iclass 26, count 0 2006.253.07:56:29.25#ibcon#end of sib2, iclass 26, count 0 2006.253.07:56:29.25#ibcon#*mode == 0, iclass 26, count 0 2006.253.07:56:29.25#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.253.07:56:29.25#ibcon#[25=USB\r\n] 2006.253.07:56:29.25#ibcon#*before write, iclass 26, count 0 2006.253.07:56:29.25#ibcon#enter sib2, iclass 26, count 0 2006.253.07:56:29.25#ibcon#flushed, iclass 26, count 0 2006.253.07:56:29.25#ibcon#about to write, iclass 26, count 0 2006.253.07:56:29.25#ibcon#wrote, iclass 26, count 0 2006.253.07:56:29.25#ibcon#about to read 3, iclass 26, count 0 2006.253.07:56:29.28#ibcon#read 3, iclass 26, count 0 2006.253.07:56:29.28#ibcon#about to read 4, iclass 26, count 0 2006.253.07:56:29.28#ibcon#read 4, iclass 26, count 0 2006.253.07:56:29.28#ibcon#about to read 5, iclass 26, count 0 2006.253.07:56:29.28#ibcon#read 5, iclass 26, count 0 2006.253.07:56:29.28#ibcon#about to read 6, iclass 26, count 0 2006.253.07:56:29.28#ibcon#read 6, iclass 26, count 0 2006.253.07:56:29.28#ibcon#end of sib2, iclass 26, count 0 2006.253.07:56:29.28#ibcon#*after write, iclass 26, count 0 2006.253.07:56:29.28#ibcon#*before return 0, iclass 26, count 0 2006.253.07:56:29.28#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.253.07:56:29.28#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.253.07:56:29.28#ibcon#about to clear, iclass 26 cls_cnt 0 2006.253.07:56:29.28#ibcon#cleared, iclass 26 cls_cnt 0 2006.253.07:56:29.28$vc4f8/valo=5,652.99 2006.253.07:56:29.28#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.253.07:56:29.28#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.253.07:56:29.28#ibcon#ireg 17 cls_cnt 0 2006.253.07:56:29.28#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.253.07:56:29.28#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.253.07:56:29.28#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.253.07:56:29.28#ibcon#enter wrdev, iclass 28, count 0 2006.253.07:56:29.28#ibcon#first serial, iclass 28, count 0 2006.253.07:56:29.28#ibcon#enter sib2, iclass 28, count 0 2006.253.07:56:29.28#ibcon#flushed, iclass 28, count 0 2006.253.07:56:29.28#ibcon#about to write, iclass 28, count 0 2006.253.07:56:29.28#ibcon#wrote, iclass 28, count 0 2006.253.07:56:29.28#ibcon#about to read 3, iclass 28, count 0 2006.253.07:56:29.30#ibcon#read 3, iclass 28, count 0 2006.253.07:56:29.30#ibcon#about to read 4, iclass 28, count 0 2006.253.07:56:29.30#ibcon#read 4, iclass 28, count 0 2006.253.07:56:29.30#ibcon#about to read 5, iclass 28, count 0 2006.253.07:56:29.30#ibcon#read 5, iclass 28, count 0 2006.253.07:56:29.30#ibcon#about to read 6, iclass 28, count 0 2006.253.07:56:29.30#ibcon#read 6, iclass 28, count 0 2006.253.07:56:29.30#ibcon#end of sib2, iclass 28, count 0 2006.253.07:56:29.30#ibcon#*mode == 0, iclass 28, count 0 2006.253.07:56:29.30#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.253.07:56:29.30#ibcon#[26=FRQ=05,652.99\r\n] 2006.253.07:56:29.30#ibcon#*before write, iclass 28, count 0 2006.253.07:56:29.30#ibcon#enter sib2, iclass 28, count 0 2006.253.07:56:29.30#ibcon#flushed, iclass 28, count 0 2006.253.07:56:29.30#ibcon#about to write, iclass 28, count 0 2006.253.07:56:29.30#ibcon#wrote, iclass 28, count 0 2006.253.07:56:29.30#ibcon#about to read 3, iclass 28, count 0 2006.253.07:56:29.34#ibcon#read 3, iclass 28, count 0 2006.253.07:56:29.34#ibcon#about to read 4, iclass 28, count 0 2006.253.07:56:29.34#ibcon#read 4, iclass 28, count 0 2006.253.07:56:29.34#ibcon#about to read 5, iclass 28, count 0 2006.253.07:56:29.34#ibcon#read 5, iclass 28, count 0 2006.253.07:56:29.34#ibcon#about to read 6, iclass 28, count 0 2006.253.07:56:29.34#ibcon#read 6, iclass 28, count 0 2006.253.07:56:29.34#ibcon#end of sib2, iclass 28, count 0 2006.253.07:56:29.34#ibcon#*after write, iclass 28, count 0 2006.253.07:56:29.34#ibcon#*before return 0, iclass 28, count 0 2006.253.07:56:29.34#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.253.07:56:29.34#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.253.07:56:29.34#ibcon#about to clear, iclass 28 cls_cnt 0 2006.253.07:56:29.34#ibcon#cleared, iclass 28 cls_cnt 0 2006.253.07:56:29.34$vc4f8/va=5,7 2006.253.07:56:29.34#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.253.07:56:29.34#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.253.07:56:29.34#ibcon#ireg 11 cls_cnt 2 2006.253.07:56:29.34#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.253.07:56:29.40#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.253.07:56:29.40#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.253.07:56:29.40#ibcon#enter wrdev, iclass 30, count 2 2006.253.07:56:29.40#ibcon#first serial, iclass 30, count 2 2006.253.07:56:29.40#ibcon#enter sib2, iclass 30, count 2 2006.253.07:56:29.40#ibcon#flushed, iclass 30, count 2 2006.253.07:56:29.40#ibcon#about to write, iclass 30, count 2 2006.253.07:56:29.40#ibcon#wrote, iclass 30, count 2 2006.253.07:56:29.40#ibcon#about to read 3, iclass 30, count 2 2006.253.07:56:29.42#ibcon#read 3, iclass 30, count 2 2006.253.07:56:29.42#ibcon#about to read 4, iclass 30, count 2 2006.253.07:56:29.42#ibcon#read 4, iclass 30, count 2 2006.253.07:56:29.42#ibcon#about to read 5, iclass 30, count 2 2006.253.07:56:29.42#ibcon#read 5, iclass 30, count 2 2006.253.07:56:29.42#ibcon#about to read 6, iclass 30, count 2 2006.253.07:56:29.42#ibcon#read 6, iclass 30, count 2 2006.253.07:56:29.42#ibcon#end of sib2, iclass 30, count 2 2006.253.07:56:29.42#ibcon#*mode == 0, iclass 30, count 2 2006.253.07:56:29.42#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.253.07:56:29.42#ibcon#[25=AT05-07\r\n] 2006.253.07:56:29.42#ibcon#*before write, iclass 30, count 2 2006.253.07:56:29.42#ibcon#enter sib2, iclass 30, count 2 2006.253.07:56:29.42#ibcon#flushed, iclass 30, count 2 2006.253.07:56:29.42#ibcon#about to write, iclass 30, count 2 2006.253.07:56:29.42#ibcon#wrote, iclass 30, count 2 2006.253.07:56:29.42#ibcon#about to read 3, iclass 30, count 2 2006.253.07:56:29.45#ibcon#read 3, iclass 30, count 2 2006.253.07:56:29.45#ibcon#about to read 4, iclass 30, count 2 2006.253.07:56:29.45#ibcon#read 4, iclass 30, count 2 2006.253.07:56:29.45#ibcon#about to read 5, iclass 30, count 2 2006.253.07:56:29.45#ibcon#read 5, iclass 30, count 2 2006.253.07:56:29.45#ibcon#about to read 6, iclass 30, count 2 2006.253.07:56:29.45#ibcon#read 6, iclass 30, count 2 2006.253.07:56:29.45#ibcon#end of sib2, iclass 30, count 2 2006.253.07:56:29.45#ibcon#*after write, iclass 30, count 2 2006.253.07:56:29.45#ibcon#*before return 0, iclass 30, count 2 2006.253.07:56:29.45#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.253.07:56:29.45#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.253.07:56:29.45#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.253.07:56:29.45#ibcon#ireg 7 cls_cnt 0 2006.253.07:56:29.45#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.253.07:56:29.57#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.253.07:56:29.57#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.253.07:56:29.57#ibcon#enter wrdev, iclass 30, count 0 2006.253.07:56:29.57#ibcon#first serial, iclass 30, count 0 2006.253.07:56:29.57#ibcon#enter sib2, iclass 30, count 0 2006.253.07:56:29.57#ibcon#flushed, iclass 30, count 0 2006.253.07:56:29.57#ibcon#about to write, iclass 30, count 0 2006.253.07:56:29.57#ibcon#wrote, iclass 30, count 0 2006.253.07:56:29.57#ibcon#about to read 3, iclass 30, count 0 2006.253.07:56:29.59#ibcon#read 3, iclass 30, count 0 2006.253.07:56:29.59#ibcon#about to read 4, iclass 30, count 0 2006.253.07:56:29.59#ibcon#read 4, iclass 30, count 0 2006.253.07:56:29.59#ibcon#about to read 5, iclass 30, count 0 2006.253.07:56:29.59#ibcon#read 5, iclass 30, count 0 2006.253.07:56:29.59#ibcon#about to read 6, iclass 30, count 0 2006.253.07:56:29.59#ibcon#read 6, iclass 30, count 0 2006.253.07:56:29.59#ibcon#end of sib2, iclass 30, count 0 2006.253.07:56:29.59#ibcon#*mode == 0, iclass 30, count 0 2006.253.07:56:29.59#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.253.07:56:29.59#ibcon#[25=USB\r\n] 2006.253.07:56:29.59#ibcon#*before write, iclass 30, count 0 2006.253.07:56:29.59#ibcon#enter sib2, iclass 30, count 0 2006.253.07:56:29.59#ibcon#flushed, iclass 30, count 0 2006.253.07:56:29.59#ibcon#about to write, iclass 30, count 0 2006.253.07:56:29.59#ibcon#wrote, iclass 30, count 0 2006.253.07:56:29.59#ibcon#about to read 3, iclass 30, count 0 2006.253.07:56:29.62#ibcon#read 3, iclass 30, count 0 2006.253.07:56:29.62#ibcon#about to read 4, iclass 30, count 0 2006.253.07:56:29.62#ibcon#read 4, iclass 30, count 0 2006.253.07:56:29.62#ibcon#about to read 5, iclass 30, count 0 2006.253.07:56:29.62#ibcon#read 5, iclass 30, count 0 2006.253.07:56:29.62#ibcon#about to read 6, iclass 30, count 0 2006.253.07:56:29.62#ibcon#read 6, iclass 30, count 0 2006.253.07:56:29.62#ibcon#end of sib2, iclass 30, count 0 2006.253.07:56:29.62#ibcon#*after write, iclass 30, count 0 2006.253.07:56:29.62#ibcon#*before return 0, iclass 30, count 0 2006.253.07:56:29.62#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.253.07:56:29.62#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.253.07:56:29.62#ibcon#about to clear, iclass 30 cls_cnt 0 2006.253.07:56:29.62#ibcon#cleared, iclass 30 cls_cnt 0 2006.253.07:56:29.62$vc4f8/valo=6,772.99 2006.253.07:56:29.62#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.253.07:56:29.62#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.253.07:56:29.62#ibcon#ireg 17 cls_cnt 0 2006.253.07:56:29.62#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.253.07:56:29.62#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.253.07:56:29.62#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.253.07:56:29.62#ibcon#enter wrdev, iclass 32, count 0 2006.253.07:56:29.62#ibcon#first serial, iclass 32, count 0 2006.253.07:56:29.62#ibcon#enter sib2, iclass 32, count 0 2006.253.07:56:29.62#ibcon#flushed, iclass 32, count 0 2006.253.07:56:29.62#ibcon#about to write, iclass 32, count 0 2006.253.07:56:29.62#ibcon#wrote, iclass 32, count 0 2006.253.07:56:29.62#ibcon#about to read 3, iclass 32, count 0 2006.253.07:56:29.65#ibcon#read 3, iclass 32, count 0 2006.253.07:56:29.65#ibcon#about to read 4, iclass 32, count 0 2006.253.07:56:29.65#ibcon#read 4, iclass 32, count 0 2006.253.07:56:29.65#ibcon#about to read 5, iclass 32, count 0 2006.253.07:56:29.65#ibcon#read 5, iclass 32, count 0 2006.253.07:56:29.65#ibcon#about to read 6, iclass 32, count 0 2006.253.07:56:29.65#ibcon#read 6, iclass 32, count 0 2006.253.07:56:29.65#ibcon#end of sib2, iclass 32, count 0 2006.253.07:56:29.65#ibcon#*mode == 0, iclass 32, count 0 2006.253.07:56:29.65#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.253.07:56:29.65#ibcon#[26=FRQ=06,772.99\r\n] 2006.253.07:56:29.65#ibcon#*before write, iclass 32, count 0 2006.253.07:56:29.65#ibcon#enter sib2, iclass 32, count 0 2006.253.07:56:29.65#ibcon#flushed, iclass 32, count 0 2006.253.07:56:29.65#ibcon#about to write, iclass 32, count 0 2006.253.07:56:29.65#ibcon#wrote, iclass 32, count 0 2006.253.07:56:29.65#ibcon#about to read 3, iclass 32, count 0 2006.253.07:56:29.69#ibcon#read 3, iclass 32, count 0 2006.253.07:56:29.69#ibcon#about to read 4, iclass 32, count 0 2006.253.07:56:29.69#ibcon#read 4, iclass 32, count 0 2006.253.07:56:29.69#ibcon#about to read 5, iclass 32, count 0 2006.253.07:56:29.69#ibcon#read 5, iclass 32, count 0 2006.253.07:56:29.69#ibcon#about to read 6, iclass 32, count 0 2006.253.07:56:29.69#ibcon#read 6, iclass 32, count 0 2006.253.07:56:29.69#ibcon#end of sib2, iclass 32, count 0 2006.253.07:56:29.69#ibcon#*after write, iclass 32, count 0 2006.253.07:56:29.69#ibcon#*before return 0, iclass 32, count 0 2006.253.07:56:29.69#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.253.07:56:29.69#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.253.07:56:29.69#ibcon#about to clear, iclass 32 cls_cnt 0 2006.253.07:56:29.69#ibcon#cleared, iclass 32 cls_cnt 0 2006.253.07:56:29.69$vc4f8/va=6,7 2006.253.07:56:29.69#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.253.07:56:29.69#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.253.07:56:29.69#ibcon#ireg 11 cls_cnt 2 2006.253.07:56:29.69#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.253.07:56:29.74#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.253.07:56:29.74#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.253.07:56:29.74#ibcon#enter wrdev, iclass 34, count 2 2006.253.07:56:29.74#ibcon#first serial, iclass 34, count 2 2006.253.07:56:29.74#ibcon#enter sib2, iclass 34, count 2 2006.253.07:56:29.74#ibcon#flushed, iclass 34, count 2 2006.253.07:56:29.74#ibcon#about to write, iclass 34, count 2 2006.253.07:56:29.74#ibcon#wrote, iclass 34, count 2 2006.253.07:56:29.74#ibcon#about to read 3, iclass 34, count 2 2006.253.07:56:29.76#ibcon#read 3, iclass 34, count 2 2006.253.07:56:29.76#ibcon#about to read 4, iclass 34, count 2 2006.253.07:56:29.76#ibcon#read 4, iclass 34, count 2 2006.253.07:56:29.76#ibcon#about to read 5, iclass 34, count 2 2006.253.07:56:29.76#ibcon#read 5, iclass 34, count 2 2006.253.07:56:29.76#ibcon#about to read 6, iclass 34, count 2 2006.253.07:56:29.76#ibcon#read 6, iclass 34, count 2 2006.253.07:56:29.76#ibcon#end of sib2, iclass 34, count 2 2006.253.07:56:29.76#ibcon#*mode == 0, iclass 34, count 2 2006.253.07:56:29.76#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.253.07:56:29.76#ibcon#[25=AT06-07\r\n] 2006.253.07:56:29.76#ibcon#*before write, iclass 34, count 2 2006.253.07:56:29.76#ibcon#enter sib2, iclass 34, count 2 2006.253.07:56:29.76#ibcon#flushed, iclass 34, count 2 2006.253.07:56:29.76#ibcon#about to write, iclass 34, count 2 2006.253.07:56:29.76#ibcon#wrote, iclass 34, count 2 2006.253.07:56:29.76#ibcon#about to read 3, iclass 34, count 2 2006.253.07:56:29.79#ibcon#read 3, iclass 34, count 2 2006.253.07:56:29.79#ibcon#about to read 4, iclass 34, count 2 2006.253.07:56:29.79#ibcon#read 4, iclass 34, count 2 2006.253.07:56:29.79#ibcon#about to read 5, iclass 34, count 2 2006.253.07:56:29.79#ibcon#read 5, iclass 34, count 2 2006.253.07:56:29.79#ibcon#about to read 6, iclass 34, count 2 2006.253.07:56:29.79#ibcon#read 6, iclass 34, count 2 2006.253.07:56:29.79#ibcon#end of sib2, iclass 34, count 2 2006.253.07:56:29.79#ibcon#*after write, iclass 34, count 2 2006.253.07:56:29.79#ibcon#*before return 0, iclass 34, count 2 2006.253.07:56:29.79#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.253.07:56:29.79#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.253.07:56:29.79#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.253.07:56:29.79#ibcon#ireg 7 cls_cnt 0 2006.253.07:56:29.79#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.253.07:56:29.91#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.253.07:56:29.91#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.253.07:56:29.91#ibcon#enter wrdev, iclass 34, count 0 2006.253.07:56:29.91#ibcon#first serial, iclass 34, count 0 2006.253.07:56:29.91#ibcon#enter sib2, iclass 34, count 0 2006.253.07:56:29.91#ibcon#flushed, iclass 34, count 0 2006.253.07:56:29.91#ibcon#about to write, iclass 34, count 0 2006.253.07:56:29.91#ibcon#wrote, iclass 34, count 0 2006.253.07:56:29.91#ibcon#about to read 3, iclass 34, count 0 2006.253.07:56:29.93#ibcon#read 3, iclass 34, count 0 2006.253.07:56:29.93#ibcon#about to read 4, iclass 34, count 0 2006.253.07:56:29.93#ibcon#read 4, iclass 34, count 0 2006.253.07:56:29.93#ibcon#about to read 5, iclass 34, count 0 2006.253.07:56:29.93#ibcon#read 5, iclass 34, count 0 2006.253.07:56:29.93#ibcon#about to read 6, iclass 34, count 0 2006.253.07:56:29.93#ibcon#read 6, iclass 34, count 0 2006.253.07:56:29.93#ibcon#end of sib2, iclass 34, count 0 2006.253.07:56:29.93#ibcon#*mode == 0, iclass 34, count 0 2006.253.07:56:29.93#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.253.07:56:29.93#ibcon#[25=USB\r\n] 2006.253.07:56:29.93#ibcon#*before write, iclass 34, count 0 2006.253.07:56:29.93#ibcon#enter sib2, iclass 34, count 0 2006.253.07:56:29.93#ibcon#flushed, iclass 34, count 0 2006.253.07:56:29.93#ibcon#about to write, iclass 34, count 0 2006.253.07:56:29.93#ibcon#wrote, iclass 34, count 0 2006.253.07:56:29.93#ibcon#about to read 3, iclass 34, count 0 2006.253.07:56:29.96#ibcon#read 3, iclass 34, count 0 2006.253.07:56:29.96#ibcon#about to read 4, iclass 34, count 0 2006.253.07:56:29.96#ibcon#read 4, iclass 34, count 0 2006.253.07:56:29.96#ibcon#about to read 5, iclass 34, count 0 2006.253.07:56:29.96#ibcon#read 5, iclass 34, count 0 2006.253.07:56:29.96#ibcon#about to read 6, iclass 34, count 0 2006.253.07:56:29.96#ibcon#read 6, iclass 34, count 0 2006.253.07:56:29.96#ibcon#end of sib2, iclass 34, count 0 2006.253.07:56:29.96#ibcon#*after write, iclass 34, count 0 2006.253.07:56:29.96#ibcon#*before return 0, iclass 34, count 0 2006.253.07:56:29.96#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.253.07:56:29.96#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.253.07:56:29.96#ibcon#about to clear, iclass 34 cls_cnt 0 2006.253.07:56:29.96#ibcon#cleared, iclass 34 cls_cnt 0 2006.253.07:56:29.96$vc4f8/valo=7,832.99 2006.253.07:56:29.96#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.253.07:56:29.96#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.253.07:56:29.96#ibcon#ireg 17 cls_cnt 0 2006.253.07:56:29.96#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.253.07:56:29.96#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.253.07:56:29.96#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.253.07:56:29.96#ibcon#enter wrdev, iclass 36, count 0 2006.253.07:56:29.96#ibcon#first serial, iclass 36, count 0 2006.253.07:56:29.96#ibcon#enter sib2, iclass 36, count 0 2006.253.07:56:29.96#ibcon#flushed, iclass 36, count 0 2006.253.07:56:29.96#ibcon#about to write, iclass 36, count 0 2006.253.07:56:29.96#ibcon#wrote, iclass 36, count 0 2006.253.07:56:29.96#ibcon#about to read 3, iclass 36, count 0 2006.253.07:56:29.98#ibcon#read 3, iclass 36, count 0 2006.253.07:56:29.98#ibcon#about to read 4, iclass 36, count 0 2006.253.07:56:29.98#ibcon#read 4, iclass 36, count 0 2006.253.07:56:29.98#ibcon#about to read 5, iclass 36, count 0 2006.253.07:56:29.98#ibcon#read 5, iclass 36, count 0 2006.253.07:56:29.98#ibcon#about to read 6, iclass 36, count 0 2006.253.07:56:29.98#ibcon#read 6, iclass 36, count 0 2006.253.07:56:29.98#ibcon#end of sib2, iclass 36, count 0 2006.253.07:56:29.98#ibcon#*mode == 0, iclass 36, count 0 2006.253.07:56:29.98#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.253.07:56:29.98#ibcon#[26=FRQ=07,832.99\r\n] 2006.253.07:56:29.98#ibcon#*before write, iclass 36, count 0 2006.253.07:56:29.98#ibcon#enter sib2, iclass 36, count 0 2006.253.07:56:29.98#ibcon#flushed, iclass 36, count 0 2006.253.07:56:29.98#ibcon#about to write, iclass 36, count 0 2006.253.07:56:29.98#ibcon#wrote, iclass 36, count 0 2006.253.07:56:29.98#ibcon#about to read 3, iclass 36, count 0 2006.253.07:56:30.02#ibcon#read 3, iclass 36, count 0 2006.253.07:56:30.02#ibcon#about to read 4, iclass 36, count 0 2006.253.07:56:30.02#ibcon#read 4, iclass 36, count 0 2006.253.07:56:30.02#ibcon#about to read 5, iclass 36, count 0 2006.253.07:56:30.02#ibcon#read 5, iclass 36, count 0 2006.253.07:56:30.02#ibcon#about to read 6, iclass 36, count 0 2006.253.07:56:30.02#ibcon#read 6, iclass 36, count 0 2006.253.07:56:30.02#ibcon#end of sib2, iclass 36, count 0 2006.253.07:56:30.02#ibcon#*after write, iclass 36, count 0 2006.253.07:56:30.02#ibcon#*before return 0, iclass 36, count 0 2006.253.07:56:30.02#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.253.07:56:30.02#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.253.07:56:30.02#ibcon#about to clear, iclass 36 cls_cnt 0 2006.253.07:56:30.02#ibcon#cleared, iclass 36 cls_cnt 0 2006.253.07:56:30.02$vc4f8/va=7,7 2006.253.07:56:30.02#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.253.07:56:30.02#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.253.07:56:30.02#ibcon#ireg 11 cls_cnt 2 2006.253.07:56:30.02#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.253.07:56:30.08#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.253.07:56:30.08#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.253.07:56:30.08#ibcon#enter wrdev, iclass 38, count 2 2006.253.07:56:30.08#ibcon#first serial, iclass 38, count 2 2006.253.07:56:30.08#ibcon#enter sib2, iclass 38, count 2 2006.253.07:56:30.08#ibcon#flushed, iclass 38, count 2 2006.253.07:56:30.08#ibcon#about to write, iclass 38, count 2 2006.253.07:56:30.08#ibcon#wrote, iclass 38, count 2 2006.253.07:56:30.08#ibcon#about to read 3, iclass 38, count 2 2006.253.07:56:30.10#ibcon#read 3, iclass 38, count 2 2006.253.07:56:30.10#ibcon#about to read 4, iclass 38, count 2 2006.253.07:56:30.10#ibcon#read 4, iclass 38, count 2 2006.253.07:56:30.10#ibcon#about to read 5, iclass 38, count 2 2006.253.07:56:30.10#ibcon#read 5, iclass 38, count 2 2006.253.07:56:30.10#ibcon#about to read 6, iclass 38, count 2 2006.253.07:56:30.10#ibcon#read 6, iclass 38, count 2 2006.253.07:56:30.10#ibcon#end of sib2, iclass 38, count 2 2006.253.07:56:30.10#ibcon#*mode == 0, iclass 38, count 2 2006.253.07:56:30.10#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.253.07:56:30.10#ibcon#[25=AT07-07\r\n] 2006.253.07:56:30.10#ibcon#*before write, iclass 38, count 2 2006.253.07:56:30.10#ibcon#enter sib2, iclass 38, count 2 2006.253.07:56:30.10#ibcon#flushed, iclass 38, count 2 2006.253.07:56:30.10#ibcon#about to write, iclass 38, count 2 2006.253.07:56:30.10#ibcon#wrote, iclass 38, count 2 2006.253.07:56:30.10#ibcon#about to read 3, iclass 38, count 2 2006.253.07:56:30.13#ibcon#read 3, iclass 38, count 2 2006.253.07:56:30.13#ibcon#about to read 4, iclass 38, count 2 2006.253.07:56:30.13#ibcon#read 4, iclass 38, count 2 2006.253.07:56:30.13#ibcon#about to read 5, iclass 38, count 2 2006.253.07:56:30.13#ibcon#read 5, iclass 38, count 2 2006.253.07:56:30.13#ibcon#about to read 6, iclass 38, count 2 2006.253.07:56:30.13#ibcon#read 6, iclass 38, count 2 2006.253.07:56:30.13#ibcon#end of sib2, iclass 38, count 2 2006.253.07:56:30.13#ibcon#*after write, iclass 38, count 2 2006.253.07:56:30.13#ibcon#*before return 0, iclass 38, count 2 2006.253.07:56:30.13#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.253.07:56:30.13#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.253.07:56:30.13#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.253.07:56:30.13#ibcon#ireg 7 cls_cnt 0 2006.253.07:56:30.13#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.253.07:56:30.25#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.253.07:56:30.25#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.253.07:56:30.25#ibcon#enter wrdev, iclass 38, count 0 2006.253.07:56:30.25#ibcon#first serial, iclass 38, count 0 2006.253.07:56:30.25#ibcon#enter sib2, iclass 38, count 0 2006.253.07:56:30.25#ibcon#flushed, iclass 38, count 0 2006.253.07:56:30.25#ibcon#about to write, iclass 38, count 0 2006.253.07:56:30.25#ibcon#wrote, iclass 38, count 0 2006.253.07:56:30.25#ibcon#about to read 3, iclass 38, count 0 2006.253.07:56:30.27#ibcon#read 3, iclass 38, count 0 2006.253.07:56:30.27#ibcon#about to read 4, iclass 38, count 0 2006.253.07:56:30.27#ibcon#read 4, iclass 38, count 0 2006.253.07:56:30.27#ibcon#about to read 5, iclass 38, count 0 2006.253.07:56:30.27#ibcon#read 5, iclass 38, count 0 2006.253.07:56:30.27#ibcon#about to read 6, iclass 38, count 0 2006.253.07:56:30.27#ibcon#read 6, iclass 38, count 0 2006.253.07:56:30.27#ibcon#end of sib2, iclass 38, count 0 2006.253.07:56:30.27#ibcon#*mode == 0, iclass 38, count 0 2006.253.07:56:30.27#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.253.07:56:30.27#ibcon#[25=USB\r\n] 2006.253.07:56:30.27#ibcon#*before write, iclass 38, count 0 2006.253.07:56:30.27#ibcon#enter sib2, iclass 38, count 0 2006.253.07:56:30.27#ibcon#flushed, iclass 38, count 0 2006.253.07:56:30.27#ibcon#about to write, iclass 38, count 0 2006.253.07:56:30.27#ibcon#wrote, iclass 38, count 0 2006.253.07:56:30.27#ibcon#about to read 3, iclass 38, count 0 2006.253.07:56:30.30#ibcon#read 3, iclass 38, count 0 2006.253.07:56:30.30#ibcon#about to read 4, iclass 38, count 0 2006.253.07:56:30.30#ibcon#read 4, iclass 38, count 0 2006.253.07:56:30.30#ibcon#about to read 5, iclass 38, count 0 2006.253.07:56:30.30#ibcon#read 5, iclass 38, count 0 2006.253.07:56:30.30#ibcon#about to read 6, iclass 38, count 0 2006.253.07:56:30.30#ibcon#read 6, iclass 38, count 0 2006.253.07:56:30.30#ibcon#end of sib2, iclass 38, count 0 2006.253.07:56:30.30#ibcon#*after write, iclass 38, count 0 2006.253.07:56:30.30#ibcon#*before return 0, iclass 38, count 0 2006.253.07:56:30.30#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.253.07:56:30.30#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.253.07:56:30.30#ibcon#about to clear, iclass 38 cls_cnt 0 2006.253.07:56:30.30#ibcon#cleared, iclass 38 cls_cnt 0 2006.253.07:56:30.30$vc4f8/valo=8,852.99 2006.253.07:56:30.30#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.253.07:56:30.30#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.253.07:56:30.30#ibcon#ireg 17 cls_cnt 0 2006.253.07:56:30.30#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.253.07:56:30.30#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.253.07:56:30.30#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.253.07:56:30.30#ibcon#enter wrdev, iclass 40, count 0 2006.253.07:56:30.30#ibcon#first serial, iclass 40, count 0 2006.253.07:56:30.30#ibcon#enter sib2, iclass 40, count 0 2006.253.07:56:30.30#ibcon#flushed, iclass 40, count 0 2006.253.07:56:30.30#ibcon#about to write, iclass 40, count 0 2006.253.07:56:30.30#ibcon#wrote, iclass 40, count 0 2006.253.07:56:30.30#ibcon#about to read 3, iclass 40, count 0 2006.253.07:56:30.33#ibcon#read 3, iclass 40, count 0 2006.253.07:56:30.33#ibcon#about to read 4, iclass 40, count 0 2006.253.07:56:30.33#ibcon#read 4, iclass 40, count 0 2006.253.07:56:30.33#ibcon#about to read 5, iclass 40, count 0 2006.253.07:56:30.33#ibcon#read 5, iclass 40, count 0 2006.253.07:56:30.33#ibcon#about to read 6, iclass 40, count 0 2006.253.07:56:30.33#ibcon#read 6, iclass 40, count 0 2006.253.07:56:30.33#ibcon#end of sib2, iclass 40, count 0 2006.253.07:56:30.33#ibcon#*mode == 0, iclass 40, count 0 2006.253.07:56:30.33#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.253.07:56:30.33#ibcon#[26=FRQ=08,852.99\r\n] 2006.253.07:56:30.33#ibcon#*before write, iclass 40, count 0 2006.253.07:56:30.33#ibcon#enter sib2, iclass 40, count 0 2006.253.07:56:30.33#ibcon#flushed, iclass 40, count 0 2006.253.07:56:30.33#ibcon#about to write, iclass 40, count 0 2006.253.07:56:30.33#ibcon#wrote, iclass 40, count 0 2006.253.07:56:30.33#ibcon#about to read 3, iclass 40, count 0 2006.253.07:56:30.37#ibcon#read 3, iclass 40, count 0 2006.253.07:56:30.37#ibcon#about to read 4, iclass 40, count 0 2006.253.07:56:30.37#ibcon#read 4, iclass 40, count 0 2006.253.07:56:30.37#ibcon#about to read 5, iclass 40, count 0 2006.253.07:56:30.37#ibcon#read 5, iclass 40, count 0 2006.253.07:56:30.37#ibcon#about to read 6, iclass 40, count 0 2006.253.07:56:30.37#ibcon#read 6, iclass 40, count 0 2006.253.07:56:30.37#ibcon#end of sib2, iclass 40, count 0 2006.253.07:56:30.37#ibcon#*after write, iclass 40, count 0 2006.253.07:56:30.37#ibcon#*before return 0, iclass 40, count 0 2006.253.07:56:30.37#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.253.07:56:30.37#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.253.07:56:30.37#ibcon#about to clear, iclass 40 cls_cnt 0 2006.253.07:56:30.37#ibcon#cleared, iclass 40 cls_cnt 0 2006.253.07:56:30.37$vc4f8/va=8,7 2006.253.07:56:30.37#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.253.07:56:30.37#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.253.07:56:30.37#ibcon#ireg 11 cls_cnt 2 2006.253.07:56:30.37#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.253.07:56:30.42#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.253.07:56:30.42#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.253.07:56:30.42#ibcon#enter wrdev, iclass 4, count 2 2006.253.07:56:30.42#ibcon#first serial, iclass 4, count 2 2006.253.07:56:30.42#ibcon#enter sib2, iclass 4, count 2 2006.253.07:56:30.42#ibcon#flushed, iclass 4, count 2 2006.253.07:56:30.42#ibcon#about to write, iclass 4, count 2 2006.253.07:56:30.42#ibcon#wrote, iclass 4, count 2 2006.253.07:56:30.42#ibcon#about to read 3, iclass 4, count 2 2006.253.07:56:30.44#ibcon#read 3, iclass 4, count 2 2006.253.07:56:30.44#ibcon#about to read 4, iclass 4, count 2 2006.253.07:56:30.44#ibcon#read 4, iclass 4, count 2 2006.253.07:56:30.44#ibcon#about to read 5, iclass 4, count 2 2006.253.07:56:30.44#ibcon#read 5, iclass 4, count 2 2006.253.07:56:30.44#ibcon#about to read 6, iclass 4, count 2 2006.253.07:56:30.44#ibcon#read 6, iclass 4, count 2 2006.253.07:56:30.44#ibcon#end of sib2, iclass 4, count 2 2006.253.07:56:30.44#ibcon#*mode == 0, iclass 4, count 2 2006.253.07:56:30.44#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.253.07:56:30.44#ibcon#[25=AT08-07\r\n] 2006.253.07:56:30.44#ibcon#*before write, iclass 4, count 2 2006.253.07:56:30.44#ibcon#enter sib2, iclass 4, count 2 2006.253.07:56:30.44#ibcon#flushed, iclass 4, count 2 2006.253.07:56:30.44#ibcon#about to write, iclass 4, count 2 2006.253.07:56:30.44#ibcon#wrote, iclass 4, count 2 2006.253.07:56:30.44#ibcon#about to read 3, iclass 4, count 2 2006.253.07:56:30.47#ibcon#read 3, iclass 4, count 2 2006.253.07:56:30.47#ibcon#about to read 4, iclass 4, count 2 2006.253.07:56:30.47#ibcon#read 4, iclass 4, count 2 2006.253.07:56:30.47#ibcon#about to read 5, iclass 4, count 2 2006.253.07:56:30.47#ibcon#read 5, iclass 4, count 2 2006.253.07:56:30.47#ibcon#about to read 6, iclass 4, count 2 2006.253.07:56:30.47#ibcon#read 6, iclass 4, count 2 2006.253.07:56:30.47#ibcon#end of sib2, iclass 4, count 2 2006.253.07:56:30.47#ibcon#*after write, iclass 4, count 2 2006.253.07:56:30.47#ibcon#*before return 0, iclass 4, count 2 2006.253.07:56:30.47#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.253.07:56:30.47#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.253.07:56:30.47#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.253.07:56:30.47#ibcon#ireg 7 cls_cnt 0 2006.253.07:56:30.47#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.253.07:56:30.59#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.253.07:56:30.59#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.253.07:56:30.59#ibcon#enter wrdev, iclass 4, count 0 2006.253.07:56:30.59#ibcon#first serial, iclass 4, count 0 2006.253.07:56:30.59#ibcon#enter sib2, iclass 4, count 0 2006.253.07:56:30.59#ibcon#flushed, iclass 4, count 0 2006.253.07:56:30.59#ibcon#about to write, iclass 4, count 0 2006.253.07:56:30.59#ibcon#wrote, iclass 4, count 0 2006.253.07:56:30.59#ibcon#about to read 3, iclass 4, count 0 2006.253.07:56:30.61#ibcon#read 3, iclass 4, count 0 2006.253.07:56:30.61#ibcon#about to read 4, iclass 4, count 0 2006.253.07:56:30.61#ibcon#read 4, iclass 4, count 0 2006.253.07:56:30.61#ibcon#about to read 5, iclass 4, count 0 2006.253.07:56:30.61#ibcon#read 5, iclass 4, count 0 2006.253.07:56:30.61#ibcon#about to read 6, iclass 4, count 0 2006.253.07:56:30.61#ibcon#read 6, iclass 4, count 0 2006.253.07:56:30.61#ibcon#end of sib2, iclass 4, count 0 2006.253.07:56:30.61#ibcon#*mode == 0, iclass 4, count 0 2006.253.07:56:30.61#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.253.07:56:30.61#ibcon#[25=USB\r\n] 2006.253.07:56:30.61#ibcon#*before write, iclass 4, count 0 2006.253.07:56:30.61#ibcon#enter sib2, iclass 4, count 0 2006.253.07:56:30.61#ibcon#flushed, iclass 4, count 0 2006.253.07:56:30.61#ibcon#about to write, iclass 4, count 0 2006.253.07:56:30.61#ibcon#wrote, iclass 4, count 0 2006.253.07:56:30.61#ibcon#about to read 3, iclass 4, count 0 2006.253.07:56:30.64#ibcon#read 3, iclass 4, count 0 2006.253.07:56:30.64#ibcon#about to read 4, iclass 4, count 0 2006.253.07:56:30.64#ibcon#read 4, iclass 4, count 0 2006.253.07:56:30.64#ibcon#about to read 5, iclass 4, count 0 2006.253.07:56:30.64#ibcon#read 5, iclass 4, count 0 2006.253.07:56:30.64#ibcon#about to read 6, iclass 4, count 0 2006.253.07:56:30.64#ibcon#read 6, iclass 4, count 0 2006.253.07:56:30.64#ibcon#end of sib2, iclass 4, count 0 2006.253.07:56:30.64#ibcon#*after write, iclass 4, count 0 2006.253.07:56:30.64#ibcon#*before return 0, iclass 4, count 0 2006.253.07:56:30.64#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.253.07:56:30.64#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.253.07:56:30.64#ibcon#about to clear, iclass 4 cls_cnt 0 2006.253.07:56:30.64#ibcon#cleared, iclass 4 cls_cnt 0 2006.253.07:56:30.64$vc4f8/vblo=1,632.99 2006.253.07:56:30.64#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.253.07:56:30.64#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.253.07:56:30.64#ibcon#ireg 17 cls_cnt 0 2006.253.07:56:30.64#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.253.07:56:30.64#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.253.07:56:30.64#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.253.07:56:30.64#ibcon#enter wrdev, iclass 6, count 0 2006.253.07:56:30.64#ibcon#first serial, iclass 6, count 0 2006.253.07:56:30.64#ibcon#enter sib2, iclass 6, count 0 2006.253.07:56:30.64#ibcon#flushed, iclass 6, count 0 2006.253.07:56:30.64#ibcon#about to write, iclass 6, count 0 2006.253.07:56:30.64#ibcon#wrote, iclass 6, count 0 2006.253.07:56:30.64#ibcon#about to read 3, iclass 6, count 0 2006.253.07:56:30.66#ibcon#read 3, iclass 6, count 0 2006.253.07:56:30.66#ibcon#about to read 4, iclass 6, count 0 2006.253.07:56:30.66#ibcon#read 4, iclass 6, count 0 2006.253.07:56:30.66#ibcon#about to read 5, iclass 6, count 0 2006.253.07:56:30.66#ibcon#read 5, iclass 6, count 0 2006.253.07:56:30.66#ibcon#about to read 6, iclass 6, count 0 2006.253.07:56:30.66#ibcon#read 6, iclass 6, count 0 2006.253.07:56:30.66#ibcon#end of sib2, iclass 6, count 0 2006.253.07:56:30.66#ibcon#*mode == 0, iclass 6, count 0 2006.253.07:56:30.66#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.253.07:56:30.66#ibcon#[28=FRQ=01,632.99\r\n] 2006.253.07:56:30.66#ibcon#*before write, iclass 6, count 0 2006.253.07:56:30.66#ibcon#enter sib2, iclass 6, count 0 2006.253.07:56:30.66#ibcon#flushed, iclass 6, count 0 2006.253.07:56:30.66#ibcon#about to write, iclass 6, count 0 2006.253.07:56:30.66#ibcon#wrote, iclass 6, count 0 2006.253.07:56:30.66#ibcon#about to read 3, iclass 6, count 0 2006.253.07:56:30.70#ibcon#read 3, iclass 6, count 0 2006.253.07:56:30.70#ibcon#about to read 4, iclass 6, count 0 2006.253.07:56:30.70#ibcon#read 4, iclass 6, count 0 2006.253.07:56:30.70#ibcon#about to read 5, iclass 6, count 0 2006.253.07:56:30.70#ibcon#read 5, iclass 6, count 0 2006.253.07:56:30.70#ibcon#about to read 6, iclass 6, count 0 2006.253.07:56:30.70#ibcon#read 6, iclass 6, count 0 2006.253.07:56:30.70#ibcon#end of sib2, iclass 6, count 0 2006.253.07:56:30.70#ibcon#*after write, iclass 6, count 0 2006.253.07:56:30.70#ibcon#*before return 0, iclass 6, count 0 2006.253.07:56:30.70#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.253.07:56:30.70#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.253.07:56:30.70#ibcon#about to clear, iclass 6 cls_cnt 0 2006.253.07:56:30.70#ibcon#cleared, iclass 6 cls_cnt 0 2006.253.07:56:30.70$vc4f8/vb=1,4 2006.253.07:56:30.70#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.253.07:56:30.70#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.253.07:56:30.70#ibcon#ireg 11 cls_cnt 2 2006.253.07:56:30.70#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.253.07:56:30.70#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.253.07:56:30.70#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.253.07:56:30.70#ibcon#enter wrdev, iclass 10, count 2 2006.253.07:56:30.70#ibcon#first serial, iclass 10, count 2 2006.253.07:56:30.70#ibcon#enter sib2, iclass 10, count 2 2006.253.07:56:30.70#ibcon#flushed, iclass 10, count 2 2006.253.07:56:30.70#ibcon#about to write, iclass 10, count 2 2006.253.07:56:30.70#ibcon#wrote, iclass 10, count 2 2006.253.07:56:30.70#ibcon#about to read 3, iclass 10, count 2 2006.253.07:56:30.72#ibcon#read 3, iclass 10, count 2 2006.253.07:56:30.72#ibcon#about to read 4, iclass 10, count 2 2006.253.07:56:30.72#ibcon#read 4, iclass 10, count 2 2006.253.07:56:30.72#ibcon#about to read 5, iclass 10, count 2 2006.253.07:56:30.72#ibcon#read 5, iclass 10, count 2 2006.253.07:56:30.72#ibcon#about to read 6, iclass 10, count 2 2006.253.07:56:30.72#ibcon#read 6, iclass 10, count 2 2006.253.07:56:30.72#ibcon#end of sib2, iclass 10, count 2 2006.253.07:56:30.72#ibcon#*mode == 0, iclass 10, count 2 2006.253.07:56:30.72#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.253.07:56:30.72#ibcon#[27=AT01-04\r\n] 2006.253.07:56:30.72#ibcon#*before write, iclass 10, count 2 2006.253.07:56:30.72#ibcon#enter sib2, iclass 10, count 2 2006.253.07:56:30.72#ibcon#flushed, iclass 10, count 2 2006.253.07:56:30.72#ibcon#about to write, iclass 10, count 2 2006.253.07:56:30.72#ibcon#wrote, iclass 10, count 2 2006.253.07:56:30.72#ibcon#about to read 3, iclass 10, count 2 2006.253.07:56:30.75#ibcon#read 3, iclass 10, count 2 2006.253.07:56:30.75#ibcon#about to read 4, iclass 10, count 2 2006.253.07:56:30.75#ibcon#read 4, iclass 10, count 2 2006.253.07:56:30.75#ibcon#about to read 5, iclass 10, count 2 2006.253.07:56:30.75#ibcon#read 5, iclass 10, count 2 2006.253.07:56:30.75#ibcon#about to read 6, iclass 10, count 2 2006.253.07:56:30.75#ibcon#read 6, iclass 10, count 2 2006.253.07:56:30.75#ibcon#end of sib2, iclass 10, count 2 2006.253.07:56:30.75#ibcon#*after write, iclass 10, count 2 2006.253.07:56:30.75#ibcon#*before return 0, iclass 10, count 2 2006.253.07:56:30.75#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.253.07:56:30.75#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.253.07:56:30.75#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.253.07:56:30.75#ibcon#ireg 7 cls_cnt 0 2006.253.07:56:30.75#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.253.07:56:30.88#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.253.07:56:30.88#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.253.07:56:30.88#ibcon#enter wrdev, iclass 10, count 0 2006.253.07:56:30.88#ibcon#first serial, iclass 10, count 0 2006.253.07:56:30.88#ibcon#enter sib2, iclass 10, count 0 2006.253.07:56:30.88#ibcon#flushed, iclass 10, count 0 2006.253.07:56:30.88#ibcon#about to write, iclass 10, count 0 2006.253.07:56:30.88#ibcon#wrote, iclass 10, count 0 2006.253.07:56:30.88#ibcon#about to read 3, iclass 10, count 0 2006.253.07:56:30.89#ibcon#read 3, iclass 10, count 0 2006.253.07:56:30.89#ibcon#about to read 4, iclass 10, count 0 2006.253.07:56:30.89#ibcon#read 4, iclass 10, count 0 2006.253.07:56:30.89#ibcon#about to read 5, iclass 10, count 0 2006.253.07:56:30.89#ibcon#read 5, iclass 10, count 0 2006.253.07:56:30.89#ibcon#about to read 6, iclass 10, count 0 2006.253.07:56:30.89#ibcon#read 6, iclass 10, count 0 2006.253.07:56:30.89#ibcon#end of sib2, iclass 10, count 0 2006.253.07:56:30.89#ibcon#*mode == 0, iclass 10, count 0 2006.253.07:56:30.89#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.253.07:56:30.89#ibcon#[27=USB\r\n] 2006.253.07:56:30.89#ibcon#*before write, iclass 10, count 0 2006.253.07:56:30.89#ibcon#enter sib2, iclass 10, count 0 2006.253.07:56:30.89#ibcon#flushed, iclass 10, count 0 2006.253.07:56:30.89#ibcon#about to write, iclass 10, count 0 2006.253.07:56:30.89#ibcon#wrote, iclass 10, count 0 2006.253.07:56:30.89#ibcon#about to read 3, iclass 10, count 0 2006.253.07:56:30.92#ibcon#read 3, iclass 10, count 0 2006.253.07:56:30.92#ibcon#about to read 4, iclass 10, count 0 2006.253.07:56:30.92#ibcon#read 4, iclass 10, count 0 2006.253.07:56:30.92#ibcon#about to read 5, iclass 10, count 0 2006.253.07:56:30.92#ibcon#read 5, iclass 10, count 0 2006.253.07:56:30.92#ibcon#about to read 6, iclass 10, count 0 2006.253.07:56:30.92#ibcon#read 6, iclass 10, count 0 2006.253.07:56:30.92#ibcon#end of sib2, iclass 10, count 0 2006.253.07:56:30.92#ibcon#*after write, iclass 10, count 0 2006.253.07:56:30.92#ibcon#*before return 0, iclass 10, count 0 2006.253.07:56:30.92#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.253.07:56:30.92#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.253.07:56:30.92#ibcon#about to clear, iclass 10 cls_cnt 0 2006.253.07:56:30.92#ibcon#cleared, iclass 10 cls_cnt 0 2006.253.07:56:30.92$vc4f8/vblo=2,640.99 2006.253.07:56:30.92#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.253.07:56:30.92#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.253.07:56:30.92#ibcon#ireg 17 cls_cnt 0 2006.253.07:56:30.92#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.253.07:56:30.92#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.253.07:56:30.92#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.253.07:56:30.92#ibcon#enter wrdev, iclass 12, count 0 2006.253.07:56:30.92#ibcon#first serial, iclass 12, count 0 2006.253.07:56:30.92#ibcon#enter sib2, iclass 12, count 0 2006.253.07:56:30.92#ibcon#flushed, iclass 12, count 0 2006.253.07:56:30.92#ibcon#about to write, iclass 12, count 0 2006.253.07:56:30.92#ibcon#wrote, iclass 12, count 0 2006.253.07:56:30.92#ibcon#about to read 3, iclass 12, count 0 2006.253.07:56:30.95#ibcon#read 3, iclass 12, count 0 2006.253.07:56:30.95#ibcon#about to read 4, iclass 12, count 0 2006.253.07:56:30.95#ibcon#read 4, iclass 12, count 0 2006.253.07:56:30.95#ibcon#about to read 5, iclass 12, count 0 2006.253.07:56:30.95#ibcon#read 5, iclass 12, count 0 2006.253.07:56:30.95#ibcon#about to read 6, iclass 12, count 0 2006.253.07:56:30.95#ibcon#read 6, iclass 12, count 0 2006.253.07:56:30.95#ibcon#end of sib2, iclass 12, count 0 2006.253.07:56:30.95#ibcon#*mode == 0, iclass 12, count 0 2006.253.07:56:30.95#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.253.07:56:30.95#ibcon#[28=FRQ=02,640.99\r\n] 2006.253.07:56:30.95#ibcon#*before write, iclass 12, count 0 2006.253.07:56:30.95#ibcon#enter sib2, iclass 12, count 0 2006.253.07:56:30.95#ibcon#flushed, iclass 12, count 0 2006.253.07:56:30.95#ibcon#about to write, iclass 12, count 0 2006.253.07:56:30.95#ibcon#wrote, iclass 12, count 0 2006.253.07:56:30.95#ibcon#about to read 3, iclass 12, count 0 2006.253.07:56:30.99#ibcon#read 3, iclass 12, count 0 2006.253.07:56:30.99#ibcon#about to read 4, iclass 12, count 0 2006.253.07:56:30.99#ibcon#read 4, iclass 12, count 0 2006.253.07:56:30.99#ibcon#about to read 5, iclass 12, count 0 2006.253.07:56:30.99#ibcon#read 5, iclass 12, count 0 2006.253.07:56:30.99#ibcon#about to read 6, iclass 12, count 0 2006.253.07:56:30.99#ibcon#read 6, iclass 12, count 0 2006.253.07:56:30.99#ibcon#end of sib2, iclass 12, count 0 2006.253.07:56:30.99#ibcon#*after write, iclass 12, count 0 2006.253.07:56:30.99#ibcon#*before return 0, iclass 12, count 0 2006.253.07:56:30.99#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.253.07:56:30.99#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.253.07:56:30.99#ibcon#about to clear, iclass 12 cls_cnt 0 2006.253.07:56:30.99#ibcon#cleared, iclass 12 cls_cnt 0 2006.253.07:56:30.99$vc4f8/vb=2,5 2006.253.07:56:30.99#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.253.07:56:30.99#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.253.07:56:30.99#ibcon#ireg 11 cls_cnt 2 2006.253.07:56:30.99#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.253.07:56:31.04#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.253.07:56:31.04#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.253.07:56:31.04#ibcon#enter wrdev, iclass 14, count 2 2006.253.07:56:31.04#ibcon#first serial, iclass 14, count 2 2006.253.07:56:31.04#ibcon#enter sib2, iclass 14, count 2 2006.253.07:56:31.04#ibcon#flushed, iclass 14, count 2 2006.253.07:56:31.04#ibcon#about to write, iclass 14, count 2 2006.253.07:56:31.04#ibcon#wrote, iclass 14, count 2 2006.253.07:56:31.04#ibcon#about to read 3, iclass 14, count 2 2006.253.07:56:31.06#ibcon#read 3, iclass 14, count 2 2006.253.07:56:31.06#ibcon#about to read 4, iclass 14, count 2 2006.253.07:56:31.06#ibcon#read 4, iclass 14, count 2 2006.253.07:56:31.06#ibcon#about to read 5, iclass 14, count 2 2006.253.07:56:31.06#ibcon#read 5, iclass 14, count 2 2006.253.07:56:31.06#ibcon#about to read 6, iclass 14, count 2 2006.253.07:56:31.06#ibcon#read 6, iclass 14, count 2 2006.253.07:56:31.06#ibcon#end of sib2, iclass 14, count 2 2006.253.07:56:31.06#ibcon#*mode == 0, iclass 14, count 2 2006.253.07:56:31.06#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.253.07:56:31.06#ibcon#[27=AT02-05\r\n] 2006.253.07:56:31.06#ibcon#*before write, iclass 14, count 2 2006.253.07:56:31.06#ibcon#enter sib2, iclass 14, count 2 2006.253.07:56:31.06#ibcon#flushed, iclass 14, count 2 2006.253.07:56:31.06#ibcon#about to write, iclass 14, count 2 2006.253.07:56:31.06#ibcon#wrote, iclass 14, count 2 2006.253.07:56:31.06#ibcon#about to read 3, iclass 14, count 2 2006.253.07:56:31.09#ibcon#read 3, iclass 14, count 2 2006.253.07:56:31.09#ibcon#about to read 4, iclass 14, count 2 2006.253.07:56:31.09#ibcon#read 4, iclass 14, count 2 2006.253.07:56:31.09#ibcon#about to read 5, iclass 14, count 2 2006.253.07:56:31.09#ibcon#read 5, iclass 14, count 2 2006.253.07:56:31.09#ibcon#about to read 6, iclass 14, count 2 2006.253.07:56:31.09#ibcon#read 6, iclass 14, count 2 2006.253.07:56:31.09#ibcon#end of sib2, iclass 14, count 2 2006.253.07:56:31.09#ibcon#*after write, iclass 14, count 2 2006.253.07:56:31.09#ibcon#*before return 0, iclass 14, count 2 2006.253.07:56:31.09#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.253.07:56:31.09#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.253.07:56:31.09#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.253.07:56:31.09#ibcon#ireg 7 cls_cnt 0 2006.253.07:56:31.09#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.253.07:56:31.21#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.253.07:56:31.21#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.253.07:56:31.21#ibcon#enter wrdev, iclass 14, count 0 2006.253.07:56:31.21#ibcon#first serial, iclass 14, count 0 2006.253.07:56:31.21#ibcon#enter sib2, iclass 14, count 0 2006.253.07:56:31.21#ibcon#flushed, iclass 14, count 0 2006.253.07:56:31.21#ibcon#about to write, iclass 14, count 0 2006.253.07:56:31.21#ibcon#wrote, iclass 14, count 0 2006.253.07:56:31.21#ibcon#about to read 3, iclass 14, count 0 2006.253.07:56:31.23#ibcon#read 3, iclass 14, count 0 2006.253.07:56:31.23#ibcon#about to read 4, iclass 14, count 0 2006.253.07:56:31.23#ibcon#read 4, iclass 14, count 0 2006.253.07:56:31.23#ibcon#about to read 5, iclass 14, count 0 2006.253.07:56:31.23#ibcon#read 5, iclass 14, count 0 2006.253.07:56:31.23#ibcon#about to read 6, iclass 14, count 0 2006.253.07:56:31.23#ibcon#read 6, iclass 14, count 0 2006.253.07:56:31.23#ibcon#end of sib2, iclass 14, count 0 2006.253.07:56:31.23#ibcon#*mode == 0, iclass 14, count 0 2006.253.07:56:31.23#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.253.07:56:31.23#ibcon#[27=USB\r\n] 2006.253.07:56:31.23#ibcon#*before write, iclass 14, count 0 2006.253.07:56:31.23#ibcon#enter sib2, iclass 14, count 0 2006.253.07:56:31.23#ibcon#flushed, iclass 14, count 0 2006.253.07:56:31.23#ibcon#about to write, iclass 14, count 0 2006.253.07:56:31.23#ibcon#wrote, iclass 14, count 0 2006.253.07:56:31.23#ibcon#about to read 3, iclass 14, count 0 2006.253.07:56:31.26#ibcon#read 3, iclass 14, count 0 2006.253.07:56:31.26#ibcon#about to read 4, iclass 14, count 0 2006.253.07:56:31.26#ibcon#read 4, iclass 14, count 0 2006.253.07:56:31.26#ibcon#about to read 5, iclass 14, count 0 2006.253.07:56:31.26#ibcon#read 5, iclass 14, count 0 2006.253.07:56:31.26#ibcon#about to read 6, iclass 14, count 0 2006.253.07:56:31.26#ibcon#read 6, iclass 14, count 0 2006.253.07:56:31.26#ibcon#end of sib2, iclass 14, count 0 2006.253.07:56:31.26#ibcon#*after write, iclass 14, count 0 2006.253.07:56:31.26#ibcon#*before return 0, iclass 14, count 0 2006.253.07:56:31.26#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.253.07:56:31.26#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.253.07:56:31.26#ibcon#about to clear, iclass 14 cls_cnt 0 2006.253.07:56:31.26#ibcon#cleared, iclass 14 cls_cnt 0 2006.253.07:56:31.26$vc4f8/vblo=3,656.99 2006.253.07:56:31.26#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.253.07:56:31.26#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.253.07:56:31.26#ibcon#ireg 17 cls_cnt 0 2006.253.07:56:31.26#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.253.07:56:31.26#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.253.07:56:31.26#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.253.07:56:31.26#ibcon#enter wrdev, iclass 16, count 0 2006.253.07:56:31.26#ibcon#first serial, iclass 16, count 0 2006.253.07:56:31.26#ibcon#enter sib2, iclass 16, count 0 2006.253.07:56:31.26#ibcon#flushed, iclass 16, count 0 2006.253.07:56:31.26#ibcon#about to write, iclass 16, count 0 2006.253.07:56:31.26#ibcon#wrote, iclass 16, count 0 2006.253.07:56:31.26#ibcon#about to read 3, iclass 16, count 0 2006.253.07:56:31.28#ibcon#read 3, iclass 16, count 0 2006.253.07:56:31.28#ibcon#about to read 4, iclass 16, count 0 2006.253.07:56:31.28#ibcon#read 4, iclass 16, count 0 2006.253.07:56:31.28#ibcon#about to read 5, iclass 16, count 0 2006.253.07:56:31.28#ibcon#read 5, iclass 16, count 0 2006.253.07:56:31.28#ibcon#about to read 6, iclass 16, count 0 2006.253.07:56:31.28#ibcon#read 6, iclass 16, count 0 2006.253.07:56:31.28#ibcon#end of sib2, iclass 16, count 0 2006.253.07:56:31.28#ibcon#*mode == 0, iclass 16, count 0 2006.253.07:56:31.28#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.253.07:56:31.28#ibcon#[28=FRQ=03,656.99\r\n] 2006.253.07:56:31.28#ibcon#*before write, iclass 16, count 0 2006.253.07:56:31.28#ibcon#enter sib2, iclass 16, count 0 2006.253.07:56:31.28#ibcon#flushed, iclass 16, count 0 2006.253.07:56:31.28#ibcon#about to write, iclass 16, count 0 2006.253.07:56:31.28#ibcon#wrote, iclass 16, count 0 2006.253.07:56:31.28#ibcon#about to read 3, iclass 16, count 0 2006.253.07:56:31.32#ibcon#read 3, iclass 16, count 0 2006.253.07:56:31.32#ibcon#about to read 4, iclass 16, count 0 2006.253.07:56:31.32#ibcon#read 4, iclass 16, count 0 2006.253.07:56:31.32#ibcon#about to read 5, iclass 16, count 0 2006.253.07:56:31.32#ibcon#read 5, iclass 16, count 0 2006.253.07:56:31.32#ibcon#about to read 6, iclass 16, count 0 2006.253.07:56:31.32#ibcon#read 6, iclass 16, count 0 2006.253.07:56:31.32#ibcon#end of sib2, iclass 16, count 0 2006.253.07:56:31.32#ibcon#*after write, iclass 16, count 0 2006.253.07:56:31.32#ibcon#*before return 0, iclass 16, count 0 2006.253.07:56:31.32#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.253.07:56:31.32#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.253.07:56:31.32#ibcon#about to clear, iclass 16 cls_cnt 0 2006.253.07:56:31.32#ibcon#cleared, iclass 16 cls_cnt 0 2006.253.07:56:31.32$vc4f8/vb=3,4 2006.253.07:56:31.32#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.253.07:56:31.32#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.253.07:56:31.32#ibcon#ireg 11 cls_cnt 2 2006.253.07:56:31.32#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.253.07:56:31.38#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.253.07:56:31.38#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.253.07:56:31.38#ibcon#enter wrdev, iclass 18, count 2 2006.253.07:56:31.38#ibcon#first serial, iclass 18, count 2 2006.253.07:56:31.38#ibcon#enter sib2, iclass 18, count 2 2006.253.07:56:31.38#ibcon#flushed, iclass 18, count 2 2006.253.07:56:31.38#ibcon#about to write, iclass 18, count 2 2006.253.07:56:31.38#ibcon#wrote, iclass 18, count 2 2006.253.07:56:31.38#ibcon#about to read 3, iclass 18, count 2 2006.253.07:56:31.40#ibcon#read 3, iclass 18, count 2 2006.253.07:56:31.40#ibcon#about to read 4, iclass 18, count 2 2006.253.07:56:31.40#ibcon#read 4, iclass 18, count 2 2006.253.07:56:31.40#ibcon#about to read 5, iclass 18, count 2 2006.253.07:56:31.40#ibcon#read 5, iclass 18, count 2 2006.253.07:56:31.40#ibcon#about to read 6, iclass 18, count 2 2006.253.07:56:31.40#ibcon#read 6, iclass 18, count 2 2006.253.07:56:31.40#ibcon#end of sib2, iclass 18, count 2 2006.253.07:56:31.40#ibcon#*mode == 0, iclass 18, count 2 2006.253.07:56:31.40#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.253.07:56:31.40#ibcon#[27=AT03-04\r\n] 2006.253.07:56:31.40#ibcon#*before write, iclass 18, count 2 2006.253.07:56:31.40#ibcon#enter sib2, iclass 18, count 2 2006.253.07:56:31.40#ibcon#flushed, iclass 18, count 2 2006.253.07:56:31.40#ibcon#about to write, iclass 18, count 2 2006.253.07:56:31.40#ibcon#wrote, iclass 18, count 2 2006.253.07:56:31.40#ibcon#about to read 3, iclass 18, count 2 2006.253.07:56:31.43#ibcon#read 3, iclass 18, count 2 2006.253.07:56:31.43#ibcon#about to read 4, iclass 18, count 2 2006.253.07:56:31.43#ibcon#read 4, iclass 18, count 2 2006.253.07:56:31.43#ibcon#about to read 5, iclass 18, count 2 2006.253.07:56:31.43#ibcon#read 5, iclass 18, count 2 2006.253.07:56:31.43#ibcon#about to read 6, iclass 18, count 2 2006.253.07:56:31.43#ibcon#read 6, iclass 18, count 2 2006.253.07:56:31.43#ibcon#end of sib2, iclass 18, count 2 2006.253.07:56:31.43#ibcon#*after write, iclass 18, count 2 2006.253.07:56:31.43#ibcon#*before return 0, iclass 18, count 2 2006.253.07:56:31.43#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.253.07:56:31.43#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.253.07:56:31.43#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.253.07:56:31.43#ibcon#ireg 7 cls_cnt 0 2006.253.07:56:31.43#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.253.07:56:31.55#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.253.07:56:31.55#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.253.07:56:31.55#ibcon#enter wrdev, iclass 18, count 0 2006.253.07:56:31.55#ibcon#first serial, iclass 18, count 0 2006.253.07:56:31.55#ibcon#enter sib2, iclass 18, count 0 2006.253.07:56:31.55#ibcon#flushed, iclass 18, count 0 2006.253.07:56:31.55#ibcon#about to write, iclass 18, count 0 2006.253.07:56:31.55#ibcon#wrote, iclass 18, count 0 2006.253.07:56:31.55#ibcon#about to read 3, iclass 18, count 0 2006.253.07:56:31.57#ibcon#read 3, iclass 18, count 0 2006.253.07:56:31.57#ibcon#about to read 4, iclass 18, count 0 2006.253.07:56:31.57#ibcon#read 4, iclass 18, count 0 2006.253.07:56:31.57#ibcon#about to read 5, iclass 18, count 0 2006.253.07:56:31.57#ibcon#read 5, iclass 18, count 0 2006.253.07:56:31.57#ibcon#about to read 6, iclass 18, count 0 2006.253.07:56:31.57#ibcon#read 6, iclass 18, count 0 2006.253.07:56:31.57#ibcon#end of sib2, iclass 18, count 0 2006.253.07:56:31.57#ibcon#*mode == 0, iclass 18, count 0 2006.253.07:56:31.57#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.253.07:56:31.57#ibcon#[27=USB\r\n] 2006.253.07:56:31.57#ibcon#*before write, iclass 18, count 0 2006.253.07:56:31.57#ibcon#enter sib2, iclass 18, count 0 2006.253.07:56:31.57#ibcon#flushed, iclass 18, count 0 2006.253.07:56:31.57#ibcon#about to write, iclass 18, count 0 2006.253.07:56:31.57#ibcon#wrote, iclass 18, count 0 2006.253.07:56:31.57#ibcon#about to read 3, iclass 18, count 0 2006.253.07:56:31.60#ibcon#read 3, iclass 18, count 0 2006.253.07:56:31.60#ibcon#about to read 4, iclass 18, count 0 2006.253.07:56:31.60#ibcon#read 4, iclass 18, count 0 2006.253.07:56:31.60#ibcon#about to read 5, iclass 18, count 0 2006.253.07:56:31.60#ibcon#read 5, iclass 18, count 0 2006.253.07:56:31.60#ibcon#about to read 6, iclass 18, count 0 2006.253.07:56:31.60#ibcon#read 6, iclass 18, count 0 2006.253.07:56:31.60#ibcon#end of sib2, iclass 18, count 0 2006.253.07:56:31.60#ibcon#*after write, iclass 18, count 0 2006.253.07:56:31.60#ibcon#*before return 0, iclass 18, count 0 2006.253.07:56:31.60#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.253.07:56:31.60#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.253.07:56:31.60#ibcon#about to clear, iclass 18 cls_cnt 0 2006.253.07:56:31.60#ibcon#cleared, iclass 18 cls_cnt 0 2006.253.07:56:31.60$vc4f8/vblo=4,712.99 2006.253.07:56:31.60#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.253.07:56:31.60#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.253.07:56:31.60#ibcon#ireg 17 cls_cnt 0 2006.253.07:56:31.60#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.253.07:56:31.60#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.253.07:56:31.60#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.253.07:56:31.60#ibcon#enter wrdev, iclass 20, count 0 2006.253.07:56:31.60#ibcon#first serial, iclass 20, count 0 2006.253.07:56:31.60#ibcon#enter sib2, iclass 20, count 0 2006.253.07:56:31.60#ibcon#flushed, iclass 20, count 0 2006.253.07:56:31.60#ibcon#about to write, iclass 20, count 0 2006.253.07:56:31.60#ibcon#wrote, iclass 20, count 0 2006.253.07:56:31.60#ibcon#about to read 3, iclass 20, count 0 2006.253.07:56:31.63#ibcon#read 3, iclass 20, count 0 2006.253.07:56:31.63#ibcon#about to read 4, iclass 20, count 0 2006.253.07:56:31.63#ibcon#read 4, iclass 20, count 0 2006.253.07:56:31.63#ibcon#about to read 5, iclass 20, count 0 2006.253.07:56:31.63#ibcon#read 5, iclass 20, count 0 2006.253.07:56:31.63#ibcon#about to read 6, iclass 20, count 0 2006.253.07:56:31.63#ibcon#read 6, iclass 20, count 0 2006.253.07:56:31.63#ibcon#end of sib2, iclass 20, count 0 2006.253.07:56:31.63#ibcon#*mode == 0, iclass 20, count 0 2006.253.07:56:31.63#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.253.07:56:31.63#ibcon#[28=FRQ=04,712.99\r\n] 2006.253.07:56:31.63#ibcon#*before write, iclass 20, count 0 2006.253.07:56:31.63#ibcon#enter sib2, iclass 20, count 0 2006.253.07:56:31.63#ibcon#flushed, iclass 20, count 0 2006.253.07:56:31.63#ibcon#about to write, iclass 20, count 0 2006.253.07:56:31.63#ibcon#wrote, iclass 20, count 0 2006.253.07:56:31.63#ibcon#about to read 3, iclass 20, count 0 2006.253.07:56:31.67#ibcon#read 3, iclass 20, count 0 2006.253.07:56:31.67#ibcon#about to read 4, iclass 20, count 0 2006.253.07:56:31.67#ibcon#read 4, iclass 20, count 0 2006.253.07:56:31.67#ibcon#about to read 5, iclass 20, count 0 2006.253.07:56:31.67#ibcon#read 5, iclass 20, count 0 2006.253.07:56:31.67#ibcon#about to read 6, iclass 20, count 0 2006.253.07:56:31.67#ibcon#read 6, iclass 20, count 0 2006.253.07:56:31.67#ibcon#end of sib2, iclass 20, count 0 2006.253.07:56:31.67#ibcon#*after write, iclass 20, count 0 2006.253.07:56:31.67#ibcon#*before return 0, iclass 20, count 0 2006.253.07:56:31.67#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.253.07:56:31.67#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.253.07:56:31.67#ibcon#about to clear, iclass 20 cls_cnt 0 2006.253.07:56:31.67#ibcon#cleared, iclass 20 cls_cnt 0 2006.253.07:56:31.67$vc4f8/vb=4,4 2006.253.07:56:31.67#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.253.07:56:31.67#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.253.07:56:31.67#ibcon#ireg 11 cls_cnt 2 2006.253.07:56:31.67#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.253.07:56:31.72#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.253.07:56:31.72#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.253.07:56:31.72#ibcon#enter wrdev, iclass 22, count 2 2006.253.07:56:31.72#ibcon#first serial, iclass 22, count 2 2006.253.07:56:31.72#ibcon#enter sib2, iclass 22, count 2 2006.253.07:56:31.72#ibcon#flushed, iclass 22, count 2 2006.253.07:56:31.72#ibcon#about to write, iclass 22, count 2 2006.253.07:56:31.72#ibcon#wrote, iclass 22, count 2 2006.253.07:56:31.72#ibcon#about to read 3, iclass 22, count 2 2006.253.07:56:31.74#ibcon#read 3, iclass 22, count 2 2006.253.07:56:31.74#ibcon#about to read 4, iclass 22, count 2 2006.253.07:56:31.74#ibcon#read 4, iclass 22, count 2 2006.253.07:56:31.74#ibcon#about to read 5, iclass 22, count 2 2006.253.07:56:31.74#ibcon#read 5, iclass 22, count 2 2006.253.07:56:31.74#ibcon#about to read 6, iclass 22, count 2 2006.253.07:56:31.74#ibcon#read 6, iclass 22, count 2 2006.253.07:56:31.74#ibcon#end of sib2, iclass 22, count 2 2006.253.07:56:31.74#ibcon#*mode == 0, iclass 22, count 2 2006.253.07:56:31.74#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.253.07:56:31.74#ibcon#[27=AT04-04\r\n] 2006.253.07:56:31.74#ibcon#*before write, iclass 22, count 2 2006.253.07:56:31.74#ibcon#enter sib2, iclass 22, count 2 2006.253.07:56:31.74#ibcon#flushed, iclass 22, count 2 2006.253.07:56:31.74#ibcon#about to write, iclass 22, count 2 2006.253.07:56:31.74#ibcon#wrote, iclass 22, count 2 2006.253.07:56:31.74#ibcon#about to read 3, iclass 22, count 2 2006.253.07:56:31.77#ibcon#read 3, iclass 22, count 2 2006.253.07:56:31.77#ibcon#about to read 4, iclass 22, count 2 2006.253.07:56:31.77#ibcon#read 4, iclass 22, count 2 2006.253.07:56:31.77#ibcon#about to read 5, iclass 22, count 2 2006.253.07:56:31.77#ibcon#read 5, iclass 22, count 2 2006.253.07:56:31.77#ibcon#about to read 6, iclass 22, count 2 2006.253.07:56:31.77#ibcon#read 6, iclass 22, count 2 2006.253.07:56:31.77#ibcon#end of sib2, iclass 22, count 2 2006.253.07:56:31.77#ibcon#*after write, iclass 22, count 2 2006.253.07:56:31.77#ibcon#*before return 0, iclass 22, count 2 2006.253.07:56:31.77#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.253.07:56:31.77#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.253.07:56:31.77#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.253.07:56:31.77#ibcon#ireg 7 cls_cnt 0 2006.253.07:56:31.77#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.253.07:56:31.89#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.253.07:56:31.89#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.253.07:56:31.89#ibcon#enter wrdev, iclass 22, count 0 2006.253.07:56:31.89#ibcon#first serial, iclass 22, count 0 2006.253.07:56:31.89#ibcon#enter sib2, iclass 22, count 0 2006.253.07:56:31.89#ibcon#flushed, iclass 22, count 0 2006.253.07:56:31.89#ibcon#about to write, iclass 22, count 0 2006.253.07:56:31.89#ibcon#wrote, iclass 22, count 0 2006.253.07:56:31.89#ibcon#about to read 3, iclass 22, count 0 2006.253.07:56:31.91#ibcon#read 3, iclass 22, count 0 2006.253.07:56:31.91#ibcon#about to read 4, iclass 22, count 0 2006.253.07:56:31.91#ibcon#read 4, iclass 22, count 0 2006.253.07:56:31.91#ibcon#about to read 5, iclass 22, count 0 2006.253.07:56:31.91#ibcon#read 5, iclass 22, count 0 2006.253.07:56:31.91#ibcon#about to read 6, iclass 22, count 0 2006.253.07:56:31.91#ibcon#read 6, iclass 22, count 0 2006.253.07:56:31.91#ibcon#end of sib2, iclass 22, count 0 2006.253.07:56:31.91#ibcon#*mode == 0, iclass 22, count 0 2006.253.07:56:31.91#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.253.07:56:31.91#ibcon#[27=USB\r\n] 2006.253.07:56:31.91#ibcon#*before write, iclass 22, count 0 2006.253.07:56:31.91#ibcon#enter sib2, iclass 22, count 0 2006.253.07:56:31.91#ibcon#flushed, iclass 22, count 0 2006.253.07:56:31.91#ibcon#about to write, iclass 22, count 0 2006.253.07:56:31.91#ibcon#wrote, iclass 22, count 0 2006.253.07:56:31.91#ibcon#about to read 3, iclass 22, count 0 2006.253.07:56:31.94#ibcon#read 3, iclass 22, count 0 2006.253.07:56:31.94#ibcon#about to read 4, iclass 22, count 0 2006.253.07:56:31.94#ibcon#read 4, iclass 22, count 0 2006.253.07:56:31.94#ibcon#about to read 5, iclass 22, count 0 2006.253.07:56:31.94#ibcon#read 5, iclass 22, count 0 2006.253.07:56:31.94#ibcon#about to read 6, iclass 22, count 0 2006.253.07:56:31.94#ibcon#read 6, iclass 22, count 0 2006.253.07:56:31.94#ibcon#end of sib2, iclass 22, count 0 2006.253.07:56:31.94#ibcon#*after write, iclass 22, count 0 2006.253.07:56:31.94#ibcon#*before return 0, iclass 22, count 0 2006.253.07:56:31.94#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.253.07:56:31.94#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.253.07:56:31.94#ibcon#about to clear, iclass 22 cls_cnt 0 2006.253.07:56:31.94#ibcon#cleared, iclass 22 cls_cnt 0 2006.253.07:56:31.94$vc4f8/vblo=5,744.99 2006.253.07:56:31.94#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.253.07:56:31.94#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.253.07:56:31.94#ibcon#ireg 17 cls_cnt 0 2006.253.07:56:31.94#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.253.07:56:31.94#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.253.07:56:31.94#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.253.07:56:31.94#ibcon#enter wrdev, iclass 24, count 0 2006.253.07:56:31.94#ibcon#first serial, iclass 24, count 0 2006.253.07:56:31.94#ibcon#enter sib2, iclass 24, count 0 2006.253.07:56:31.94#ibcon#flushed, iclass 24, count 0 2006.253.07:56:31.94#ibcon#about to write, iclass 24, count 0 2006.253.07:56:31.94#ibcon#wrote, iclass 24, count 0 2006.253.07:56:31.94#ibcon#about to read 3, iclass 24, count 0 2006.253.07:56:31.96#ibcon#read 3, iclass 24, count 0 2006.253.07:56:31.96#ibcon#about to read 4, iclass 24, count 0 2006.253.07:56:31.96#ibcon#read 4, iclass 24, count 0 2006.253.07:56:31.96#ibcon#about to read 5, iclass 24, count 0 2006.253.07:56:31.96#ibcon#read 5, iclass 24, count 0 2006.253.07:56:31.96#ibcon#about to read 6, iclass 24, count 0 2006.253.07:56:31.96#ibcon#read 6, iclass 24, count 0 2006.253.07:56:31.96#ibcon#end of sib2, iclass 24, count 0 2006.253.07:56:31.96#ibcon#*mode == 0, iclass 24, count 0 2006.253.07:56:31.96#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.253.07:56:31.96#ibcon#[28=FRQ=05,744.99\r\n] 2006.253.07:56:31.96#ibcon#*before write, iclass 24, count 0 2006.253.07:56:31.96#ibcon#enter sib2, iclass 24, count 0 2006.253.07:56:31.96#ibcon#flushed, iclass 24, count 0 2006.253.07:56:31.96#ibcon#about to write, iclass 24, count 0 2006.253.07:56:31.96#ibcon#wrote, iclass 24, count 0 2006.253.07:56:31.96#ibcon#about to read 3, iclass 24, count 0 2006.253.07:56:32.00#ibcon#read 3, iclass 24, count 0 2006.253.07:56:32.00#ibcon#about to read 4, iclass 24, count 0 2006.253.07:56:32.00#ibcon#read 4, iclass 24, count 0 2006.253.07:56:32.00#ibcon#about to read 5, iclass 24, count 0 2006.253.07:56:32.00#ibcon#read 5, iclass 24, count 0 2006.253.07:56:32.00#ibcon#about to read 6, iclass 24, count 0 2006.253.07:56:32.00#ibcon#read 6, iclass 24, count 0 2006.253.07:56:32.00#ibcon#end of sib2, iclass 24, count 0 2006.253.07:56:32.00#ibcon#*after write, iclass 24, count 0 2006.253.07:56:32.00#ibcon#*before return 0, iclass 24, count 0 2006.253.07:56:32.00#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.253.07:56:32.00#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.253.07:56:32.00#ibcon#about to clear, iclass 24 cls_cnt 0 2006.253.07:56:32.00#ibcon#cleared, iclass 24 cls_cnt 0 2006.253.07:56:32.00$vc4f8/vb=5,4 2006.253.07:56:32.00#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.253.07:56:32.00#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.253.07:56:32.00#ibcon#ireg 11 cls_cnt 2 2006.253.07:56:32.00#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.253.07:56:32.06#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.253.07:56:32.06#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.253.07:56:32.06#ibcon#enter wrdev, iclass 26, count 2 2006.253.07:56:32.06#ibcon#first serial, iclass 26, count 2 2006.253.07:56:32.06#ibcon#enter sib2, iclass 26, count 2 2006.253.07:56:32.06#ibcon#flushed, iclass 26, count 2 2006.253.07:56:32.06#ibcon#about to write, iclass 26, count 2 2006.253.07:56:32.06#ibcon#wrote, iclass 26, count 2 2006.253.07:56:32.06#ibcon#about to read 3, iclass 26, count 2 2006.253.07:56:32.08#ibcon#read 3, iclass 26, count 2 2006.253.07:56:32.08#ibcon#about to read 4, iclass 26, count 2 2006.253.07:56:32.08#ibcon#read 4, iclass 26, count 2 2006.253.07:56:32.08#ibcon#about to read 5, iclass 26, count 2 2006.253.07:56:32.08#ibcon#read 5, iclass 26, count 2 2006.253.07:56:32.08#ibcon#about to read 6, iclass 26, count 2 2006.253.07:56:32.08#ibcon#read 6, iclass 26, count 2 2006.253.07:56:32.08#ibcon#end of sib2, iclass 26, count 2 2006.253.07:56:32.08#ibcon#*mode == 0, iclass 26, count 2 2006.253.07:56:32.08#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.253.07:56:32.08#ibcon#[27=AT05-04\r\n] 2006.253.07:56:32.08#ibcon#*before write, iclass 26, count 2 2006.253.07:56:32.08#ibcon#enter sib2, iclass 26, count 2 2006.253.07:56:32.08#ibcon#flushed, iclass 26, count 2 2006.253.07:56:32.08#ibcon#about to write, iclass 26, count 2 2006.253.07:56:32.08#ibcon#wrote, iclass 26, count 2 2006.253.07:56:32.08#ibcon#about to read 3, iclass 26, count 2 2006.253.07:56:32.11#ibcon#read 3, iclass 26, count 2 2006.253.07:56:32.11#ibcon#about to read 4, iclass 26, count 2 2006.253.07:56:32.11#ibcon#read 4, iclass 26, count 2 2006.253.07:56:32.11#ibcon#about to read 5, iclass 26, count 2 2006.253.07:56:32.11#ibcon#read 5, iclass 26, count 2 2006.253.07:56:32.11#ibcon#about to read 6, iclass 26, count 2 2006.253.07:56:32.11#ibcon#read 6, iclass 26, count 2 2006.253.07:56:32.11#ibcon#end of sib2, iclass 26, count 2 2006.253.07:56:32.11#ibcon#*after write, iclass 26, count 2 2006.253.07:56:32.11#ibcon#*before return 0, iclass 26, count 2 2006.253.07:56:32.11#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.253.07:56:32.11#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.253.07:56:32.11#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.253.07:56:32.11#ibcon#ireg 7 cls_cnt 0 2006.253.07:56:32.11#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.253.07:56:32.23#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.253.07:56:32.23#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.253.07:56:32.23#ibcon#enter wrdev, iclass 26, count 0 2006.253.07:56:32.23#ibcon#first serial, iclass 26, count 0 2006.253.07:56:32.23#ibcon#enter sib2, iclass 26, count 0 2006.253.07:56:32.23#ibcon#flushed, iclass 26, count 0 2006.253.07:56:32.23#ibcon#about to write, iclass 26, count 0 2006.253.07:56:32.23#ibcon#wrote, iclass 26, count 0 2006.253.07:56:32.23#ibcon#about to read 3, iclass 26, count 0 2006.253.07:56:32.25#ibcon#read 3, iclass 26, count 0 2006.253.07:56:32.25#ibcon#about to read 4, iclass 26, count 0 2006.253.07:56:32.25#ibcon#read 4, iclass 26, count 0 2006.253.07:56:32.25#ibcon#about to read 5, iclass 26, count 0 2006.253.07:56:32.25#ibcon#read 5, iclass 26, count 0 2006.253.07:56:32.25#ibcon#about to read 6, iclass 26, count 0 2006.253.07:56:32.25#ibcon#read 6, iclass 26, count 0 2006.253.07:56:32.25#ibcon#end of sib2, iclass 26, count 0 2006.253.07:56:32.25#ibcon#*mode == 0, iclass 26, count 0 2006.253.07:56:32.25#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.253.07:56:32.25#ibcon#[27=USB\r\n] 2006.253.07:56:32.25#ibcon#*before write, iclass 26, count 0 2006.253.07:56:32.25#ibcon#enter sib2, iclass 26, count 0 2006.253.07:56:32.25#ibcon#flushed, iclass 26, count 0 2006.253.07:56:32.25#ibcon#about to write, iclass 26, count 0 2006.253.07:56:32.25#ibcon#wrote, iclass 26, count 0 2006.253.07:56:32.25#ibcon#about to read 3, iclass 26, count 0 2006.253.07:56:32.28#ibcon#read 3, iclass 26, count 0 2006.253.07:56:32.28#ibcon#about to read 4, iclass 26, count 0 2006.253.07:56:32.28#ibcon#read 4, iclass 26, count 0 2006.253.07:56:32.28#ibcon#about to read 5, iclass 26, count 0 2006.253.07:56:32.28#ibcon#read 5, iclass 26, count 0 2006.253.07:56:32.28#ibcon#about to read 6, iclass 26, count 0 2006.253.07:56:32.28#ibcon#read 6, iclass 26, count 0 2006.253.07:56:32.28#ibcon#end of sib2, iclass 26, count 0 2006.253.07:56:32.28#ibcon#*after write, iclass 26, count 0 2006.253.07:56:32.28#ibcon#*before return 0, iclass 26, count 0 2006.253.07:56:32.28#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.253.07:56:32.28#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.253.07:56:32.28#ibcon#about to clear, iclass 26 cls_cnt 0 2006.253.07:56:32.28#ibcon#cleared, iclass 26 cls_cnt 0 2006.253.07:56:32.28$vc4f8/vblo=6,752.99 2006.253.07:56:32.28#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.253.07:56:32.28#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.253.07:56:32.28#ibcon#ireg 17 cls_cnt 0 2006.253.07:56:32.28#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.253.07:56:32.28#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.253.07:56:32.28#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.253.07:56:32.28#ibcon#enter wrdev, iclass 28, count 0 2006.253.07:56:32.28#ibcon#first serial, iclass 28, count 0 2006.253.07:56:32.28#ibcon#enter sib2, iclass 28, count 0 2006.253.07:56:32.28#ibcon#flushed, iclass 28, count 0 2006.253.07:56:32.28#ibcon#about to write, iclass 28, count 0 2006.253.07:56:32.28#ibcon#wrote, iclass 28, count 0 2006.253.07:56:32.28#ibcon#about to read 3, iclass 28, count 0 2006.253.07:56:32.30#ibcon#read 3, iclass 28, count 0 2006.253.07:56:32.30#ibcon#about to read 4, iclass 28, count 0 2006.253.07:56:32.30#ibcon#read 4, iclass 28, count 0 2006.253.07:56:32.30#ibcon#about to read 5, iclass 28, count 0 2006.253.07:56:32.30#ibcon#read 5, iclass 28, count 0 2006.253.07:56:32.30#ibcon#about to read 6, iclass 28, count 0 2006.253.07:56:32.30#ibcon#read 6, iclass 28, count 0 2006.253.07:56:32.30#ibcon#end of sib2, iclass 28, count 0 2006.253.07:56:32.30#ibcon#*mode == 0, iclass 28, count 0 2006.253.07:56:32.30#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.253.07:56:32.30#ibcon#[28=FRQ=06,752.99\r\n] 2006.253.07:56:32.30#ibcon#*before write, iclass 28, count 0 2006.253.07:56:32.30#ibcon#enter sib2, iclass 28, count 0 2006.253.07:56:32.30#ibcon#flushed, iclass 28, count 0 2006.253.07:56:32.30#ibcon#about to write, iclass 28, count 0 2006.253.07:56:32.30#ibcon#wrote, iclass 28, count 0 2006.253.07:56:32.30#ibcon#about to read 3, iclass 28, count 0 2006.253.07:56:32.34#ibcon#read 3, iclass 28, count 0 2006.253.07:56:32.34#ibcon#about to read 4, iclass 28, count 0 2006.253.07:56:32.34#ibcon#read 4, iclass 28, count 0 2006.253.07:56:32.34#ibcon#about to read 5, iclass 28, count 0 2006.253.07:56:32.34#ibcon#read 5, iclass 28, count 0 2006.253.07:56:32.34#ibcon#about to read 6, iclass 28, count 0 2006.253.07:56:32.34#ibcon#read 6, iclass 28, count 0 2006.253.07:56:32.34#ibcon#end of sib2, iclass 28, count 0 2006.253.07:56:32.34#ibcon#*after write, iclass 28, count 0 2006.253.07:56:32.34#ibcon#*before return 0, iclass 28, count 0 2006.253.07:56:32.34#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.253.07:56:32.34#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.253.07:56:32.34#ibcon#about to clear, iclass 28 cls_cnt 0 2006.253.07:56:32.34#ibcon#cleared, iclass 28 cls_cnt 0 2006.253.07:56:32.34$vc4f8/vb=6,4 2006.253.07:56:32.34#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.253.07:56:32.34#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.253.07:56:32.34#ibcon#ireg 11 cls_cnt 2 2006.253.07:56:32.34#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.253.07:56:32.40#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.253.07:56:32.40#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.253.07:56:32.40#ibcon#enter wrdev, iclass 30, count 2 2006.253.07:56:32.40#ibcon#first serial, iclass 30, count 2 2006.253.07:56:32.40#ibcon#enter sib2, iclass 30, count 2 2006.253.07:56:32.40#ibcon#flushed, iclass 30, count 2 2006.253.07:56:32.40#ibcon#about to write, iclass 30, count 2 2006.253.07:56:32.40#ibcon#wrote, iclass 30, count 2 2006.253.07:56:32.40#ibcon#about to read 3, iclass 30, count 2 2006.253.07:56:32.42#ibcon#read 3, iclass 30, count 2 2006.253.07:56:32.42#ibcon#about to read 4, iclass 30, count 2 2006.253.07:56:32.42#ibcon#read 4, iclass 30, count 2 2006.253.07:56:32.42#ibcon#about to read 5, iclass 30, count 2 2006.253.07:56:32.42#ibcon#read 5, iclass 30, count 2 2006.253.07:56:32.42#ibcon#about to read 6, iclass 30, count 2 2006.253.07:56:32.42#ibcon#read 6, iclass 30, count 2 2006.253.07:56:32.42#ibcon#end of sib2, iclass 30, count 2 2006.253.07:56:32.42#ibcon#*mode == 0, iclass 30, count 2 2006.253.07:56:32.42#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.253.07:56:32.42#ibcon#[27=AT06-04\r\n] 2006.253.07:56:32.42#ibcon#*before write, iclass 30, count 2 2006.253.07:56:32.42#ibcon#enter sib2, iclass 30, count 2 2006.253.07:56:32.42#ibcon#flushed, iclass 30, count 2 2006.253.07:56:32.42#ibcon#about to write, iclass 30, count 2 2006.253.07:56:32.42#ibcon#wrote, iclass 30, count 2 2006.253.07:56:32.42#ibcon#about to read 3, iclass 30, count 2 2006.253.07:56:32.45#ibcon#read 3, iclass 30, count 2 2006.253.07:56:32.45#ibcon#about to read 4, iclass 30, count 2 2006.253.07:56:32.45#ibcon#read 4, iclass 30, count 2 2006.253.07:56:32.45#ibcon#about to read 5, iclass 30, count 2 2006.253.07:56:32.45#ibcon#read 5, iclass 30, count 2 2006.253.07:56:32.45#ibcon#about to read 6, iclass 30, count 2 2006.253.07:56:32.45#ibcon#read 6, iclass 30, count 2 2006.253.07:56:32.45#ibcon#end of sib2, iclass 30, count 2 2006.253.07:56:32.45#ibcon#*after write, iclass 30, count 2 2006.253.07:56:32.45#ibcon#*before return 0, iclass 30, count 2 2006.253.07:56:32.45#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.253.07:56:32.45#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.253.07:56:32.45#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.253.07:56:32.45#ibcon#ireg 7 cls_cnt 0 2006.253.07:56:32.45#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.253.07:56:32.57#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.253.07:56:32.57#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.253.07:56:32.57#ibcon#enter wrdev, iclass 30, count 0 2006.253.07:56:32.57#ibcon#first serial, iclass 30, count 0 2006.253.07:56:32.57#ibcon#enter sib2, iclass 30, count 0 2006.253.07:56:32.57#ibcon#flushed, iclass 30, count 0 2006.253.07:56:32.57#ibcon#about to write, iclass 30, count 0 2006.253.07:56:32.57#ibcon#wrote, iclass 30, count 0 2006.253.07:56:32.57#ibcon#about to read 3, iclass 30, count 0 2006.253.07:56:32.59#ibcon#read 3, iclass 30, count 0 2006.253.07:56:32.59#ibcon#about to read 4, iclass 30, count 0 2006.253.07:56:32.59#ibcon#read 4, iclass 30, count 0 2006.253.07:56:32.59#ibcon#about to read 5, iclass 30, count 0 2006.253.07:56:32.59#ibcon#read 5, iclass 30, count 0 2006.253.07:56:32.59#ibcon#about to read 6, iclass 30, count 0 2006.253.07:56:32.59#ibcon#read 6, iclass 30, count 0 2006.253.07:56:32.59#ibcon#end of sib2, iclass 30, count 0 2006.253.07:56:32.59#ibcon#*mode == 0, iclass 30, count 0 2006.253.07:56:32.59#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.253.07:56:32.59#ibcon#[27=USB\r\n] 2006.253.07:56:32.59#ibcon#*before write, iclass 30, count 0 2006.253.07:56:32.59#ibcon#enter sib2, iclass 30, count 0 2006.253.07:56:32.59#ibcon#flushed, iclass 30, count 0 2006.253.07:56:32.59#ibcon#about to write, iclass 30, count 0 2006.253.07:56:32.59#ibcon#wrote, iclass 30, count 0 2006.253.07:56:32.59#ibcon#about to read 3, iclass 30, count 0 2006.253.07:56:32.62#ibcon#read 3, iclass 30, count 0 2006.253.07:56:32.62#ibcon#about to read 4, iclass 30, count 0 2006.253.07:56:32.62#ibcon#read 4, iclass 30, count 0 2006.253.07:56:32.62#ibcon#about to read 5, iclass 30, count 0 2006.253.07:56:32.62#ibcon#read 5, iclass 30, count 0 2006.253.07:56:32.62#ibcon#about to read 6, iclass 30, count 0 2006.253.07:56:32.62#ibcon#read 6, iclass 30, count 0 2006.253.07:56:32.62#ibcon#end of sib2, iclass 30, count 0 2006.253.07:56:32.62#ibcon#*after write, iclass 30, count 0 2006.253.07:56:32.62#ibcon#*before return 0, iclass 30, count 0 2006.253.07:56:32.62#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.253.07:56:32.62#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.253.07:56:32.62#ibcon#about to clear, iclass 30 cls_cnt 0 2006.253.07:56:32.62#ibcon#cleared, iclass 30 cls_cnt 0 2006.253.07:56:32.62$vc4f8/vabw=wide 2006.253.07:56:32.62#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.253.07:56:32.62#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.253.07:56:32.62#ibcon#ireg 8 cls_cnt 0 2006.253.07:56:32.62#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.253.07:56:32.62#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.253.07:56:32.62#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.253.07:56:32.62#ibcon#enter wrdev, iclass 32, count 0 2006.253.07:56:32.62#ibcon#first serial, iclass 32, count 0 2006.253.07:56:32.62#ibcon#enter sib2, iclass 32, count 0 2006.253.07:56:32.62#ibcon#flushed, iclass 32, count 0 2006.253.07:56:32.62#ibcon#about to write, iclass 32, count 0 2006.253.07:56:32.62#ibcon#wrote, iclass 32, count 0 2006.253.07:56:32.62#ibcon#about to read 3, iclass 32, count 0 2006.253.07:56:32.65#ibcon#read 3, iclass 32, count 0 2006.253.07:56:32.65#ibcon#about to read 4, iclass 32, count 0 2006.253.07:56:32.65#ibcon#read 4, iclass 32, count 0 2006.253.07:56:32.65#ibcon#about to read 5, iclass 32, count 0 2006.253.07:56:32.65#ibcon#read 5, iclass 32, count 0 2006.253.07:56:32.65#ibcon#about to read 6, iclass 32, count 0 2006.253.07:56:32.65#ibcon#read 6, iclass 32, count 0 2006.253.07:56:32.65#ibcon#end of sib2, iclass 32, count 0 2006.253.07:56:32.65#ibcon#*mode == 0, iclass 32, count 0 2006.253.07:56:32.65#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.253.07:56:32.65#ibcon#[25=BW32\r\n] 2006.253.07:56:32.65#ibcon#*before write, iclass 32, count 0 2006.253.07:56:32.65#ibcon#enter sib2, iclass 32, count 0 2006.253.07:56:32.65#ibcon#flushed, iclass 32, count 0 2006.253.07:56:32.65#ibcon#about to write, iclass 32, count 0 2006.253.07:56:32.65#ibcon#wrote, iclass 32, count 0 2006.253.07:56:32.65#ibcon#about to read 3, iclass 32, count 0 2006.253.07:56:32.68#ibcon#read 3, iclass 32, count 0 2006.253.07:56:32.68#ibcon#about to read 4, iclass 32, count 0 2006.253.07:56:32.68#ibcon#read 4, iclass 32, count 0 2006.253.07:56:32.68#ibcon#about to read 5, iclass 32, count 0 2006.253.07:56:32.68#ibcon#read 5, iclass 32, count 0 2006.253.07:56:32.68#ibcon#about to read 6, iclass 32, count 0 2006.253.07:56:32.68#ibcon#read 6, iclass 32, count 0 2006.253.07:56:32.68#ibcon#end of sib2, iclass 32, count 0 2006.253.07:56:32.68#ibcon#*after write, iclass 32, count 0 2006.253.07:56:32.68#ibcon#*before return 0, iclass 32, count 0 2006.253.07:56:32.68#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.253.07:56:32.68#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.253.07:56:32.68#ibcon#about to clear, iclass 32 cls_cnt 0 2006.253.07:56:32.68#ibcon#cleared, iclass 32 cls_cnt 0 2006.253.07:56:32.68$vc4f8/vbbw=wide 2006.253.07:56:32.68#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.253.07:56:32.68#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.253.07:56:32.68#ibcon#ireg 8 cls_cnt 0 2006.253.07:56:32.68#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.253.07:56:32.74#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.253.07:56:32.74#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.253.07:56:32.74#ibcon#enter wrdev, iclass 34, count 0 2006.253.07:56:32.74#ibcon#first serial, iclass 34, count 0 2006.253.07:56:32.74#ibcon#enter sib2, iclass 34, count 0 2006.253.07:56:32.74#ibcon#flushed, iclass 34, count 0 2006.253.07:56:32.74#ibcon#about to write, iclass 34, count 0 2006.253.07:56:32.74#ibcon#wrote, iclass 34, count 0 2006.253.07:56:32.74#ibcon#about to read 3, iclass 34, count 0 2006.253.07:56:32.76#ibcon#read 3, iclass 34, count 0 2006.253.07:56:32.76#ibcon#about to read 4, iclass 34, count 0 2006.253.07:56:32.76#ibcon#read 4, iclass 34, count 0 2006.253.07:56:32.76#ibcon#about to read 5, iclass 34, count 0 2006.253.07:56:32.76#ibcon#read 5, iclass 34, count 0 2006.253.07:56:32.76#ibcon#about to read 6, iclass 34, count 0 2006.253.07:56:32.76#ibcon#read 6, iclass 34, count 0 2006.253.07:56:32.76#ibcon#end of sib2, iclass 34, count 0 2006.253.07:56:32.76#ibcon#*mode == 0, iclass 34, count 0 2006.253.07:56:32.76#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.253.07:56:32.76#ibcon#[27=BW32\r\n] 2006.253.07:56:32.76#ibcon#*before write, iclass 34, count 0 2006.253.07:56:32.76#ibcon#enter sib2, iclass 34, count 0 2006.253.07:56:32.76#ibcon#flushed, iclass 34, count 0 2006.253.07:56:32.76#ibcon#about to write, iclass 34, count 0 2006.253.07:56:32.76#ibcon#wrote, iclass 34, count 0 2006.253.07:56:32.76#ibcon#about to read 3, iclass 34, count 0 2006.253.07:56:32.79#ibcon#read 3, iclass 34, count 0 2006.253.07:56:32.79#ibcon#about to read 4, iclass 34, count 0 2006.253.07:56:32.79#ibcon#read 4, iclass 34, count 0 2006.253.07:56:32.79#ibcon#about to read 5, iclass 34, count 0 2006.253.07:56:32.79#ibcon#read 5, iclass 34, count 0 2006.253.07:56:32.79#ibcon#about to read 6, iclass 34, count 0 2006.253.07:56:32.79#ibcon#read 6, iclass 34, count 0 2006.253.07:56:32.79#ibcon#end of sib2, iclass 34, count 0 2006.253.07:56:32.79#ibcon#*after write, iclass 34, count 0 2006.253.07:56:32.79#ibcon#*before return 0, iclass 34, count 0 2006.253.07:56:32.79#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.253.07:56:32.79#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.253.07:56:32.79#ibcon#about to clear, iclass 34 cls_cnt 0 2006.253.07:56:32.79#ibcon#cleared, iclass 34 cls_cnt 0 2006.253.07:56:32.79$4f8m12a/ifd4f 2006.253.07:56:32.79$ifd4f/lo= 2006.253.07:56:32.79$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.253.07:56:32.79$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.253.07:56:32.79$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.253.07:56:32.79$ifd4f/patch= 2006.253.07:56:32.79$ifd4f/patch=lo1,a1,a2,a3,a4 2006.253.07:56:32.79$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.253.07:56:32.79$ifd4f/patch=lo3,a5,a6,a7,a8 2006.253.07:56:32.79$4f8m12a/"form=m,16.000,1:2 2006.253.07:56:32.79$4f8m12a/"tpicd 2006.253.07:56:32.79$4f8m12a/echo=off 2006.253.07:56:32.79$4f8m12a/xlog=off 2006.253.07:56:32.79:!2006.253.07:58:40 2006.253.07:56:55.14#trakl#Source acquired 2006.253.07:56:57.14#flagr#flagr/antenna,acquired 2006.253.07:58:40.00:preob 2006.253.07:58:40.14/onsource/TRACKING 2006.253.07:58:40.14:!2006.253.07:58:50 2006.253.07:58:50.00:data_valid=on 2006.253.07:58:50.00:midob 2006.253.07:58:51.14/onsource/TRACKING 2006.253.07:58:51.14/wx/31.14,1006.4,73 2006.253.07:58:51.20/cable/+6.3664E-03 2006.253.07:58:52.29/va/01,08,usb,yes,34,36 2006.253.07:58:52.29/va/02,07,usb,yes,34,36 2006.253.07:58:52.29/va/03,06,usb,yes,36,37 2006.253.07:58:52.29/va/04,07,usb,yes,35,38 2006.253.07:58:52.29/va/05,07,usb,yes,37,39 2006.253.07:58:52.29/va/06,07,usb,yes,33,33 2006.253.07:58:52.29/va/07,07,usb,yes,32,32 2006.253.07:58:52.29/va/08,07,usb,yes,35,35 2006.253.07:58:52.52/valo/01,532.99,yes,locked 2006.253.07:58:52.52/valo/02,572.99,yes,locked 2006.253.07:58:52.52/valo/03,672.99,yes,locked 2006.253.07:58:52.52/valo/04,832.99,yes,locked 2006.253.07:58:52.52/valo/05,652.99,yes,locked 2006.253.07:58:52.52/valo/06,772.99,yes,locked 2006.253.07:58:52.52/valo/07,832.99,yes,locked 2006.253.07:58:52.52/valo/08,852.99,yes,locked 2006.253.07:58:53.61/vb/01,04,usb,yes,33,31 2006.253.07:58:53.61/vb/02,05,usb,yes,30,32 2006.253.07:58:53.61/vb/03,04,usb,yes,31,35 2006.253.07:58:53.61/vb/04,04,usb,yes,32,32 2006.253.07:58:53.61/vb/05,04,usb,yes,30,34 2006.253.07:58:53.61/vb/06,04,usb,yes,31,34 2006.253.07:58:53.61/vb/07,04,usb,yes,33,34 2006.253.07:58:53.61/vb/08,04,usb,yes,31,34 2006.253.07:58:53.85/vblo/01,632.99,yes,locked 2006.253.07:58:53.85/vblo/02,640.99,yes,locked 2006.253.07:58:53.85/vblo/03,656.99,yes,locked 2006.253.07:58:53.85/vblo/04,712.99,yes,locked 2006.253.07:58:53.85/vblo/05,744.99,yes,locked 2006.253.07:58:53.85/vblo/06,752.99,yes,locked 2006.253.07:58:53.85/vblo/07,734.99,yes,locked 2006.253.07:58:53.85/vblo/08,744.99,yes,locked 2006.253.07:58:54.00/vabw/8 2006.253.07:58:54.15/vbbw/8 2006.253.07:58:54.28/xfe/off,on,14.2 2006.253.07:58:54.71/ifatt/23,28,28,28 2006.253.07:58:55.07/fmout-gps/S +4.73E-07 2006.253.07:58:55.15:!2006.253.07:59:50 2006.253.07:59:50.00:data_valid=off 2006.253.07:59:50.00:postob 2006.253.07:59:50.07/cable/+6.3675E-03 2006.253.07:59:50.07/wx/31.12,1006.4,73 2006.253.07:59:51.08/fmout-gps/S +4.74E-07 2006.253.07:59:51.08:scan_name=253-0800,k06253,60 2006.253.07:59:51.08:source=1300+580,130252.47,574837.6,2000.0,ccw 2006.253.07:59:51.14#flagr#flagr/antenna,new-source 2006.253.07:59:52.14:checkk5 2006.253.07:59:52.53/chk_autoobs//k5ts1/ autoobs is running! 2006.253.07:59:52.96/chk_autoobs//k5ts2/ autoobs is running! 2006.253.07:59:53.33/chk_autoobs//k5ts3/ autoobs is running! 2006.253.07:59:53.70/chk_autoobs//k5ts4/ autoobs is running! 2006.253.07:59:54.07/chk_obsdata//k5ts1/T2530758??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.07:59:54.44/chk_obsdata//k5ts2/T2530758??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.07:59:54.81/chk_obsdata//k5ts3/T2530758??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.07:59:55.18/chk_obsdata//k5ts4/T2530758??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.07:59:55.88/k5log//k5ts1_log_newline 2006.253.07:59:56.58/k5log//k5ts2_log_newline 2006.253.07:59:57.27/k5log//k5ts3_log_newline 2006.253.07:59:57.96/k5log//k5ts4_log_newline 2006.253.07:59:57.98/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.253.07:59:57.98:4f8m12a=2 2006.253.07:59:57.98$4f8m12a/echo=on 2006.253.07:59:57.98$4f8m12a/pcalon 2006.253.07:59:57.98$pcalon/"no phase cal control is implemented here 2006.253.07:59:57.98$4f8m12a/"tpicd=stop 2006.253.07:59:57.98$4f8m12a/vc4f8 2006.253.07:59:57.98$vc4f8/valo=1,532.99 2006.253.07:59:57.99#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.253.07:59:57.99#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.253.07:59:57.99#ibcon#ireg 17 cls_cnt 0 2006.253.07:59:57.99#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.253.07:59:57.99#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.253.07:59:57.99#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.253.07:59:57.99#ibcon#enter wrdev, iclass 40, count 0 2006.253.07:59:57.99#ibcon#first serial, iclass 40, count 0 2006.253.07:59:57.99#ibcon#enter sib2, iclass 40, count 0 2006.253.07:59:57.99#ibcon#flushed, iclass 40, count 0 2006.253.07:59:57.99#ibcon#about to write, iclass 40, count 0 2006.253.07:59:57.99#ibcon#wrote, iclass 40, count 0 2006.253.07:59:57.99#ibcon#about to read 3, iclass 40, count 0 2006.253.07:59:58.03#ibcon#read 3, iclass 40, count 0 2006.253.07:59:58.03#ibcon#about to read 4, iclass 40, count 0 2006.253.07:59:58.03#ibcon#read 4, iclass 40, count 0 2006.253.07:59:58.03#ibcon#about to read 5, iclass 40, count 0 2006.253.07:59:58.03#ibcon#read 5, iclass 40, count 0 2006.253.07:59:58.03#ibcon#about to read 6, iclass 40, count 0 2006.253.07:59:58.03#ibcon#read 6, iclass 40, count 0 2006.253.07:59:58.03#ibcon#end of sib2, iclass 40, count 0 2006.253.07:59:58.03#ibcon#*mode == 0, iclass 40, count 0 2006.253.07:59:58.03#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.253.07:59:58.03#ibcon#[26=FRQ=01,532.99\r\n] 2006.253.07:59:58.03#ibcon#*before write, iclass 40, count 0 2006.253.07:59:58.03#ibcon#enter sib2, iclass 40, count 0 2006.253.07:59:58.03#ibcon#flushed, iclass 40, count 0 2006.253.07:59:58.03#ibcon#about to write, iclass 40, count 0 2006.253.07:59:58.03#ibcon#wrote, iclass 40, count 0 2006.253.07:59:58.03#ibcon#about to read 3, iclass 40, count 0 2006.253.07:59:58.07#ibcon#read 3, iclass 40, count 0 2006.253.07:59:58.07#ibcon#about to read 4, iclass 40, count 0 2006.253.07:59:58.07#ibcon#read 4, iclass 40, count 0 2006.253.07:59:58.07#ibcon#about to read 5, iclass 40, count 0 2006.253.07:59:58.07#ibcon#read 5, iclass 40, count 0 2006.253.07:59:58.07#ibcon#about to read 6, iclass 40, count 0 2006.253.07:59:58.07#ibcon#read 6, iclass 40, count 0 2006.253.07:59:58.07#ibcon#end of sib2, iclass 40, count 0 2006.253.07:59:58.07#ibcon#*after write, iclass 40, count 0 2006.253.07:59:58.07#ibcon#*before return 0, iclass 40, count 0 2006.253.07:59:58.07#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.253.07:59:58.07#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.253.07:59:58.07#ibcon#about to clear, iclass 40 cls_cnt 0 2006.253.07:59:58.07#ibcon#cleared, iclass 40 cls_cnt 0 2006.253.07:59:58.07$vc4f8/va=1,8 2006.253.07:59:58.07#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.253.07:59:58.07#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.253.07:59:58.07#ibcon#ireg 11 cls_cnt 2 2006.253.07:59:58.07#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.253.07:59:58.07#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.253.07:59:58.07#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.253.07:59:58.07#ibcon#enter wrdev, iclass 4, count 2 2006.253.07:59:58.07#ibcon#first serial, iclass 4, count 2 2006.253.07:59:58.07#ibcon#enter sib2, iclass 4, count 2 2006.253.07:59:58.07#ibcon#flushed, iclass 4, count 2 2006.253.07:59:58.07#ibcon#about to write, iclass 4, count 2 2006.253.07:59:58.07#ibcon#wrote, iclass 4, count 2 2006.253.07:59:58.07#ibcon#about to read 3, iclass 4, count 2 2006.253.07:59:58.09#ibcon#read 3, iclass 4, count 2 2006.253.07:59:58.09#ibcon#about to read 4, iclass 4, count 2 2006.253.07:59:58.09#ibcon#read 4, iclass 4, count 2 2006.253.07:59:58.09#ibcon#about to read 5, iclass 4, count 2 2006.253.07:59:58.09#ibcon#read 5, iclass 4, count 2 2006.253.07:59:58.09#ibcon#about to read 6, iclass 4, count 2 2006.253.07:59:58.09#ibcon#read 6, iclass 4, count 2 2006.253.07:59:58.09#ibcon#end of sib2, iclass 4, count 2 2006.253.07:59:58.09#ibcon#*mode == 0, iclass 4, count 2 2006.253.07:59:58.09#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.253.07:59:58.09#ibcon#[25=AT01-08\r\n] 2006.253.07:59:58.09#ibcon#*before write, iclass 4, count 2 2006.253.07:59:58.09#ibcon#enter sib2, iclass 4, count 2 2006.253.07:59:58.09#ibcon#flushed, iclass 4, count 2 2006.253.07:59:58.09#ibcon#about to write, iclass 4, count 2 2006.253.07:59:58.09#ibcon#wrote, iclass 4, count 2 2006.253.07:59:58.09#ibcon#about to read 3, iclass 4, count 2 2006.253.07:59:58.13#ibcon#read 3, iclass 4, count 2 2006.253.07:59:58.13#ibcon#about to read 4, iclass 4, count 2 2006.253.07:59:58.13#ibcon#read 4, iclass 4, count 2 2006.253.07:59:58.13#ibcon#about to read 5, iclass 4, count 2 2006.253.07:59:58.13#ibcon#read 5, iclass 4, count 2 2006.253.07:59:58.13#ibcon#about to read 6, iclass 4, count 2 2006.253.07:59:58.13#ibcon#read 6, iclass 4, count 2 2006.253.07:59:58.13#ibcon#end of sib2, iclass 4, count 2 2006.253.07:59:58.13#ibcon#*after write, iclass 4, count 2 2006.253.07:59:58.13#ibcon#*before return 0, iclass 4, count 2 2006.253.07:59:58.13#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.253.07:59:58.13#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.253.07:59:58.13#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.253.07:59:58.13#ibcon#ireg 7 cls_cnt 0 2006.253.07:59:58.13#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.253.07:59:58.24#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.253.07:59:58.24#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.253.07:59:58.24#ibcon#enter wrdev, iclass 4, count 0 2006.253.07:59:58.24#ibcon#first serial, iclass 4, count 0 2006.253.07:59:58.24#ibcon#enter sib2, iclass 4, count 0 2006.253.07:59:58.24#ibcon#flushed, iclass 4, count 0 2006.253.07:59:58.24#ibcon#about to write, iclass 4, count 0 2006.253.07:59:58.24#ibcon#wrote, iclass 4, count 0 2006.253.07:59:58.24#ibcon#about to read 3, iclass 4, count 0 2006.253.07:59:58.26#ibcon#read 3, iclass 4, count 0 2006.253.07:59:58.26#ibcon#about to read 4, iclass 4, count 0 2006.253.07:59:58.26#ibcon#read 4, iclass 4, count 0 2006.253.07:59:58.26#ibcon#about to read 5, iclass 4, count 0 2006.253.07:59:58.26#ibcon#read 5, iclass 4, count 0 2006.253.07:59:58.26#ibcon#about to read 6, iclass 4, count 0 2006.253.07:59:58.26#ibcon#read 6, iclass 4, count 0 2006.253.07:59:58.26#ibcon#end of sib2, iclass 4, count 0 2006.253.07:59:58.26#ibcon#*mode == 0, iclass 4, count 0 2006.253.07:59:58.26#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.253.07:59:58.26#ibcon#[25=USB\r\n] 2006.253.07:59:58.26#ibcon#*before write, iclass 4, count 0 2006.253.07:59:58.26#ibcon#enter sib2, iclass 4, count 0 2006.253.07:59:58.26#ibcon#flushed, iclass 4, count 0 2006.253.07:59:58.26#ibcon#about to write, iclass 4, count 0 2006.253.07:59:58.26#ibcon#wrote, iclass 4, count 0 2006.253.07:59:58.26#ibcon#about to read 3, iclass 4, count 0 2006.253.07:59:58.29#ibcon#read 3, iclass 4, count 0 2006.253.07:59:58.29#ibcon#about to read 4, iclass 4, count 0 2006.253.07:59:58.29#ibcon#read 4, iclass 4, count 0 2006.253.07:59:58.29#ibcon#about to read 5, iclass 4, count 0 2006.253.07:59:58.29#ibcon#read 5, iclass 4, count 0 2006.253.07:59:58.29#ibcon#about to read 6, iclass 4, count 0 2006.253.07:59:58.29#ibcon#read 6, iclass 4, count 0 2006.253.07:59:58.29#ibcon#end of sib2, iclass 4, count 0 2006.253.07:59:58.29#ibcon#*after write, iclass 4, count 0 2006.253.07:59:58.29#ibcon#*before return 0, iclass 4, count 0 2006.253.07:59:58.29#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.253.07:59:58.29#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.253.07:59:58.29#ibcon#about to clear, iclass 4 cls_cnt 0 2006.253.07:59:58.29#ibcon#cleared, iclass 4 cls_cnt 0 2006.253.07:59:58.29$vc4f8/valo=2,572.99 2006.253.07:59:58.29#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.253.07:59:58.29#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.253.07:59:58.29#ibcon#ireg 17 cls_cnt 0 2006.253.07:59:58.29#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.253.07:59:58.29#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.253.07:59:58.29#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.253.07:59:58.29#ibcon#enter wrdev, iclass 6, count 0 2006.253.07:59:58.29#ibcon#first serial, iclass 6, count 0 2006.253.07:59:58.29#ibcon#enter sib2, iclass 6, count 0 2006.253.07:59:58.29#ibcon#flushed, iclass 6, count 0 2006.253.07:59:58.29#ibcon#about to write, iclass 6, count 0 2006.253.07:59:58.29#ibcon#wrote, iclass 6, count 0 2006.253.07:59:58.29#ibcon#about to read 3, iclass 6, count 0 2006.253.07:59:58.32#ibcon#read 3, iclass 6, count 0 2006.253.07:59:58.32#ibcon#about to read 4, iclass 6, count 0 2006.253.07:59:58.32#ibcon#read 4, iclass 6, count 0 2006.253.07:59:58.32#ibcon#about to read 5, iclass 6, count 0 2006.253.07:59:58.32#ibcon#read 5, iclass 6, count 0 2006.253.07:59:58.32#ibcon#about to read 6, iclass 6, count 0 2006.253.07:59:58.32#ibcon#read 6, iclass 6, count 0 2006.253.07:59:58.32#ibcon#end of sib2, iclass 6, count 0 2006.253.07:59:58.32#ibcon#*mode == 0, iclass 6, count 0 2006.253.07:59:58.32#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.253.07:59:58.32#ibcon#[26=FRQ=02,572.99\r\n] 2006.253.07:59:58.32#ibcon#*before write, iclass 6, count 0 2006.253.07:59:58.32#ibcon#enter sib2, iclass 6, count 0 2006.253.07:59:58.32#ibcon#flushed, iclass 6, count 0 2006.253.07:59:58.32#ibcon#about to write, iclass 6, count 0 2006.253.07:59:58.32#ibcon#wrote, iclass 6, count 0 2006.253.07:59:58.32#ibcon#about to read 3, iclass 6, count 0 2006.253.07:59:58.36#ibcon#read 3, iclass 6, count 0 2006.253.07:59:58.36#ibcon#about to read 4, iclass 6, count 0 2006.253.07:59:58.36#ibcon#read 4, iclass 6, count 0 2006.253.07:59:58.36#ibcon#about to read 5, iclass 6, count 0 2006.253.07:59:58.36#ibcon#read 5, iclass 6, count 0 2006.253.07:59:58.36#ibcon#about to read 6, iclass 6, count 0 2006.253.07:59:58.36#ibcon#read 6, iclass 6, count 0 2006.253.07:59:58.36#ibcon#end of sib2, iclass 6, count 0 2006.253.07:59:58.36#ibcon#*after write, iclass 6, count 0 2006.253.07:59:58.36#ibcon#*before return 0, iclass 6, count 0 2006.253.07:59:58.36#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.253.07:59:58.36#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.253.07:59:58.36#ibcon#about to clear, iclass 6 cls_cnt 0 2006.253.07:59:58.36#ibcon#cleared, iclass 6 cls_cnt 0 2006.253.07:59:58.36$vc4f8/va=2,7 2006.253.07:59:58.36#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.253.07:59:58.36#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.253.07:59:58.36#ibcon#ireg 11 cls_cnt 2 2006.253.07:59:58.36#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.253.07:59:58.41#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.253.07:59:58.41#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.253.07:59:58.41#ibcon#enter wrdev, iclass 10, count 2 2006.253.07:59:58.41#ibcon#first serial, iclass 10, count 2 2006.253.07:59:58.41#ibcon#enter sib2, iclass 10, count 2 2006.253.07:59:58.41#ibcon#flushed, iclass 10, count 2 2006.253.07:59:58.41#ibcon#about to write, iclass 10, count 2 2006.253.07:59:58.41#ibcon#wrote, iclass 10, count 2 2006.253.07:59:58.41#ibcon#about to read 3, iclass 10, count 2 2006.253.07:59:58.43#ibcon#read 3, iclass 10, count 2 2006.253.07:59:58.43#ibcon#about to read 4, iclass 10, count 2 2006.253.07:59:58.43#ibcon#read 4, iclass 10, count 2 2006.253.07:59:58.43#ibcon#about to read 5, iclass 10, count 2 2006.253.07:59:58.43#ibcon#read 5, iclass 10, count 2 2006.253.07:59:58.43#ibcon#about to read 6, iclass 10, count 2 2006.253.07:59:58.43#ibcon#read 6, iclass 10, count 2 2006.253.07:59:58.43#ibcon#end of sib2, iclass 10, count 2 2006.253.07:59:58.43#ibcon#*mode == 0, iclass 10, count 2 2006.253.07:59:58.43#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.253.07:59:58.43#ibcon#[25=AT02-07\r\n] 2006.253.07:59:58.43#ibcon#*before write, iclass 10, count 2 2006.253.07:59:58.43#ibcon#enter sib2, iclass 10, count 2 2006.253.07:59:58.43#ibcon#flushed, iclass 10, count 2 2006.253.07:59:58.43#ibcon#about to write, iclass 10, count 2 2006.253.07:59:58.43#ibcon#wrote, iclass 10, count 2 2006.253.07:59:58.43#ibcon#about to read 3, iclass 10, count 2 2006.253.07:59:58.46#ibcon#read 3, iclass 10, count 2 2006.253.07:59:58.46#ibcon#about to read 4, iclass 10, count 2 2006.253.07:59:58.46#ibcon#read 4, iclass 10, count 2 2006.253.07:59:58.46#ibcon#about to read 5, iclass 10, count 2 2006.253.07:59:58.46#ibcon#read 5, iclass 10, count 2 2006.253.07:59:58.46#ibcon#about to read 6, iclass 10, count 2 2006.253.07:59:58.46#ibcon#read 6, iclass 10, count 2 2006.253.07:59:58.46#ibcon#end of sib2, iclass 10, count 2 2006.253.07:59:58.46#ibcon#*after write, iclass 10, count 2 2006.253.07:59:58.46#ibcon#*before return 0, iclass 10, count 2 2006.253.07:59:58.46#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.253.07:59:58.46#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.253.07:59:58.46#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.253.07:59:58.46#ibcon#ireg 7 cls_cnt 0 2006.253.07:59:58.46#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.253.07:59:58.58#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.253.07:59:58.58#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.253.07:59:58.58#ibcon#enter wrdev, iclass 10, count 0 2006.253.07:59:58.58#ibcon#first serial, iclass 10, count 0 2006.253.07:59:58.58#ibcon#enter sib2, iclass 10, count 0 2006.253.07:59:58.58#ibcon#flushed, iclass 10, count 0 2006.253.07:59:58.58#ibcon#about to write, iclass 10, count 0 2006.253.07:59:58.58#ibcon#wrote, iclass 10, count 0 2006.253.07:59:58.58#ibcon#about to read 3, iclass 10, count 0 2006.253.07:59:58.60#ibcon#read 3, iclass 10, count 0 2006.253.07:59:58.60#ibcon#about to read 4, iclass 10, count 0 2006.253.07:59:58.60#ibcon#read 4, iclass 10, count 0 2006.253.07:59:58.60#ibcon#about to read 5, iclass 10, count 0 2006.253.07:59:58.60#ibcon#read 5, iclass 10, count 0 2006.253.07:59:58.60#ibcon#about to read 6, iclass 10, count 0 2006.253.07:59:58.60#ibcon#read 6, iclass 10, count 0 2006.253.07:59:58.60#ibcon#end of sib2, iclass 10, count 0 2006.253.07:59:58.60#ibcon#*mode == 0, iclass 10, count 0 2006.253.07:59:58.60#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.253.07:59:58.60#ibcon#[25=USB\r\n] 2006.253.07:59:58.60#ibcon#*before write, iclass 10, count 0 2006.253.07:59:58.60#ibcon#enter sib2, iclass 10, count 0 2006.253.07:59:58.60#ibcon#flushed, iclass 10, count 0 2006.253.07:59:58.60#ibcon#about to write, iclass 10, count 0 2006.253.07:59:58.60#ibcon#wrote, iclass 10, count 0 2006.253.07:59:58.60#ibcon#about to read 3, iclass 10, count 0 2006.253.07:59:58.63#ibcon#read 3, iclass 10, count 0 2006.253.07:59:58.63#ibcon#about to read 4, iclass 10, count 0 2006.253.07:59:58.63#ibcon#read 4, iclass 10, count 0 2006.253.07:59:58.63#ibcon#about to read 5, iclass 10, count 0 2006.253.07:59:58.63#ibcon#read 5, iclass 10, count 0 2006.253.07:59:58.63#ibcon#about to read 6, iclass 10, count 0 2006.253.07:59:58.63#ibcon#read 6, iclass 10, count 0 2006.253.07:59:58.63#ibcon#end of sib2, iclass 10, count 0 2006.253.07:59:58.63#ibcon#*after write, iclass 10, count 0 2006.253.07:59:58.63#ibcon#*before return 0, iclass 10, count 0 2006.253.07:59:58.63#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.253.07:59:58.63#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.253.07:59:58.63#ibcon#about to clear, iclass 10 cls_cnt 0 2006.253.07:59:58.63#ibcon#cleared, iclass 10 cls_cnt 0 2006.253.07:59:58.63$vc4f8/valo=3,672.99 2006.253.07:59:58.63#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.253.07:59:58.63#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.253.07:59:58.63#ibcon#ireg 17 cls_cnt 0 2006.253.07:59:58.63#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.253.07:59:58.63#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.253.07:59:58.63#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.253.07:59:58.63#ibcon#enter wrdev, iclass 12, count 0 2006.253.07:59:58.63#ibcon#first serial, iclass 12, count 0 2006.253.07:59:58.63#ibcon#enter sib2, iclass 12, count 0 2006.253.07:59:58.63#ibcon#flushed, iclass 12, count 0 2006.253.07:59:58.63#ibcon#about to write, iclass 12, count 0 2006.253.07:59:58.63#ibcon#wrote, iclass 12, count 0 2006.253.07:59:58.63#ibcon#about to read 3, iclass 12, count 0 2006.253.07:59:58.66#ibcon#read 3, iclass 12, count 0 2006.253.07:59:58.66#ibcon#about to read 4, iclass 12, count 0 2006.253.07:59:58.66#ibcon#read 4, iclass 12, count 0 2006.253.07:59:58.66#ibcon#about to read 5, iclass 12, count 0 2006.253.07:59:58.66#ibcon#read 5, iclass 12, count 0 2006.253.07:59:58.66#ibcon#about to read 6, iclass 12, count 0 2006.253.07:59:58.66#ibcon#read 6, iclass 12, count 0 2006.253.07:59:58.66#ibcon#end of sib2, iclass 12, count 0 2006.253.07:59:58.66#ibcon#*mode == 0, iclass 12, count 0 2006.253.07:59:58.66#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.253.07:59:58.66#ibcon#[26=FRQ=03,672.99\r\n] 2006.253.07:59:58.66#ibcon#*before write, iclass 12, count 0 2006.253.07:59:58.66#ibcon#enter sib2, iclass 12, count 0 2006.253.07:59:58.66#ibcon#flushed, iclass 12, count 0 2006.253.07:59:58.66#ibcon#about to write, iclass 12, count 0 2006.253.07:59:58.66#ibcon#wrote, iclass 12, count 0 2006.253.07:59:58.66#ibcon#about to read 3, iclass 12, count 0 2006.253.07:59:58.70#ibcon#read 3, iclass 12, count 0 2006.253.07:59:58.70#ibcon#about to read 4, iclass 12, count 0 2006.253.07:59:58.70#ibcon#read 4, iclass 12, count 0 2006.253.07:59:58.70#ibcon#about to read 5, iclass 12, count 0 2006.253.07:59:58.70#ibcon#read 5, iclass 12, count 0 2006.253.07:59:58.70#ibcon#about to read 6, iclass 12, count 0 2006.253.07:59:58.70#ibcon#read 6, iclass 12, count 0 2006.253.07:59:58.70#ibcon#end of sib2, iclass 12, count 0 2006.253.07:59:58.70#ibcon#*after write, iclass 12, count 0 2006.253.07:59:58.70#ibcon#*before return 0, iclass 12, count 0 2006.253.07:59:58.70#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.253.07:59:58.70#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.253.07:59:58.70#ibcon#about to clear, iclass 12 cls_cnt 0 2006.253.07:59:58.70#ibcon#cleared, iclass 12 cls_cnt 0 2006.253.07:59:58.70$vc4f8/va=3,6 2006.253.07:59:58.70#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.253.07:59:58.70#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.253.07:59:58.70#ibcon#ireg 11 cls_cnt 2 2006.253.07:59:58.70#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.253.07:59:58.75#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.253.07:59:58.75#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.253.07:59:58.75#ibcon#enter wrdev, iclass 14, count 2 2006.253.07:59:58.75#ibcon#first serial, iclass 14, count 2 2006.253.07:59:58.75#ibcon#enter sib2, iclass 14, count 2 2006.253.07:59:58.75#ibcon#flushed, iclass 14, count 2 2006.253.07:59:58.75#ibcon#about to write, iclass 14, count 2 2006.253.07:59:58.75#ibcon#wrote, iclass 14, count 2 2006.253.07:59:58.75#ibcon#about to read 3, iclass 14, count 2 2006.253.07:59:58.77#ibcon#read 3, iclass 14, count 2 2006.253.07:59:58.77#ibcon#about to read 4, iclass 14, count 2 2006.253.07:59:58.77#ibcon#read 4, iclass 14, count 2 2006.253.07:59:58.77#ibcon#about to read 5, iclass 14, count 2 2006.253.07:59:58.77#ibcon#read 5, iclass 14, count 2 2006.253.07:59:58.77#ibcon#about to read 6, iclass 14, count 2 2006.253.07:59:58.77#ibcon#read 6, iclass 14, count 2 2006.253.07:59:58.77#ibcon#end of sib2, iclass 14, count 2 2006.253.07:59:58.77#ibcon#*mode == 0, iclass 14, count 2 2006.253.07:59:58.77#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.253.07:59:58.77#ibcon#[25=AT03-06\r\n] 2006.253.07:59:58.77#ibcon#*before write, iclass 14, count 2 2006.253.07:59:58.77#ibcon#enter sib2, iclass 14, count 2 2006.253.07:59:58.77#ibcon#flushed, iclass 14, count 2 2006.253.07:59:58.77#ibcon#about to write, iclass 14, count 2 2006.253.07:59:58.77#ibcon#wrote, iclass 14, count 2 2006.253.07:59:58.77#ibcon#about to read 3, iclass 14, count 2 2006.253.07:59:58.80#ibcon#read 3, iclass 14, count 2 2006.253.07:59:58.80#ibcon#about to read 4, iclass 14, count 2 2006.253.07:59:58.80#ibcon#read 4, iclass 14, count 2 2006.253.07:59:58.80#ibcon#about to read 5, iclass 14, count 2 2006.253.07:59:58.80#ibcon#read 5, iclass 14, count 2 2006.253.07:59:58.80#ibcon#about to read 6, iclass 14, count 2 2006.253.07:59:58.80#ibcon#read 6, iclass 14, count 2 2006.253.07:59:58.80#ibcon#end of sib2, iclass 14, count 2 2006.253.07:59:58.80#ibcon#*after write, iclass 14, count 2 2006.253.07:59:58.80#ibcon#*before return 0, iclass 14, count 2 2006.253.07:59:58.80#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.253.07:59:58.80#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.253.07:59:58.80#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.253.07:59:58.80#ibcon#ireg 7 cls_cnt 0 2006.253.07:59:58.80#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.253.07:59:58.92#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.253.07:59:58.92#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.253.07:59:58.92#ibcon#enter wrdev, iclass 14, count 0 2006.253.07:59:58.92#ibcon#first serial, iclass 14, count 0 2006.253.07:59:58.92#ibcon#enter sib2, iclass 14, count 0 2006.253.07:59:58.92#ibcon#flushed, iclass 14, count 0 2006.253.07:59:58.92#ibcon#about to write, iclass 14, count 0 2006.253.07:59:58.92#ibcon#wrote, iclass 14, count 0 2006.253.07:59:58.92#ibcon#about to read 3, iclass 14, count 0 2006.253.07:59:58.94#ibcon#read 3, iclass 14, count 0 2006.253.07:59:58.94#ibcon#about to read 4, iclass 14, count 0 2006.253.07:59:58.94#ibcon#read 4, iclass 14, count 0 2006.253.07:59:58.94#ibcon#about to read 5, iclass 14, count 0 2006.253.07:59:58.94#ibcon#read 5, iclass 14, count 0 2006.253.07:59:58.94#ibcon#about to read 6, iclass 14, count 0 2006.253.07:59:58.94#ibcon#read 6, iclass 14, count 0 2006.253.07:59:58.94#ibcon#end of sib2, iclass 14, count 0 2006.253.07:59:58.94#ibcon#*mode == 0, iclass 14, count 0 2006.253.07:59:58.94#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.253.07:59:58.94#ibcon#[25=USB\r\n] 2006.253.07:59:58.94#ibcon#*before write, iclass 14, count 0 2006.253.07:59:58.94#ibcon#enter sib2, iclass 14, count 0 2006.253.07:59:58.94#ibcon#flushed, iclass 14, count 0 2006.253.07:59:58.94#ibcon#about to write, iclass 14, count 0 2006.253.07:59:58.94#ibcon#wrote, iclass 14, count 0 2006.253.07:59:58.94#ibcon#about to read 3, iclass 14, count 0 2006.253.07:59:58.97#ibcon#read 3, iclass 14, count 0 2006.253.07:59:58.97#ibcon#about to read 4, iclass 14, count 0 2006.253.07:59:58.97#ibcon#read 4, iclass 14, count 0 2006.253.07:59:58.97#ibcon#about to read 5, iclass 14, count 0 2006.253.07:59:58.97#ibcon#read 5, iclass 14, count 0 2006.253.07:59:58.97#ibcon#about to read 6, iclass 14, count 0 2006.253.07:59:58.97#ibcon#read 6, iclass 14, count 0 2006.253.07:59:58.97#ibcon#end of sib2, iclass 14, count 0 2006.253.07:59:58.97#ibcon#*after write, iclass 14, count 0 2006.253.07:59:58.97#ibcon#*before return 0, iclass 14, count 0 2006.253.07:59:58.97#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.253.07:59:58.97#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.253.07:59:58.97#ibcon#about to clear, iclass 14 cls_cnt 0 2006.253.07:59:58.97#ibcon#cleared, iclass 14 cls_cnt 0 2006.253.07:59:58.97$vc4f8/valo=4,832.99 2006.253.07:59:58.97#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.253.07:59:58.97#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.253.07:59:58.97#ibcon#ireg 17 cls_cnt 0 2006.253.07:59:58.97#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.253.07:59:58.97#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.253.07:59:58.97#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.253.07:59:58.97#ibcon#enter wrdev, iclass 16, count 0 2006.253.07:59:58.97#ibcon#first serial, iclass 16, count 0 2006.253.07:59:58.97#ibcon#enter sib2, iclass 16, count 0 2006.253.07:59:58.97#ibcon#flushed, iclass 16, count 0 2006.253.07:59:58.97#ibcon#about to write, iclass 16, count 0 2006.253.07:59:58.97#ibcon#wrote, iclass 16, count 0 2006.253.07:59:58.97#ibcon#about to read 3, iclass 16, count 0 2006.253.07:59:59.00#ibcon#read 3, iclass 16, count 0 2006.253.07:59:59.00#ibcon#about to read 4, iclass 16, count 0 2006.253.07:59:59.00#ibcon#read 4, iclass 16, count 0 2006.253.07:59:59.00#ibcon#about to read 5, iclass 16, count 0 2006.253.07:59:59.00#ibcon#read 5, iclass 16, count 0 2006.253.07:59:59.00#ibcon#about to read 6, iclass 16, count 0 2006.253.07:59:59.00#ibcon#read 6, iclass 16, count 0 2006.253.07:59:59.00#ibcon#end of sib2, iclass 16, count 0 2006.253.07:59:59.00#ibcon#*mode == 0, iclass 16, count 0 2006.253.07:59:59.00#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.253.07:59:59.00#ibcon#[26=FRQ=04,832.99\r\n] 2006.253.07:59:59.00#ibcon#*before write, iclass 16, count 0 2006.253.07:59:59.00#ibcon#enter sib2, iclass 16, count 0 2006.253.07:59:59.00#ibcon#flushed, iclass 16, count 0 2006.253.07:59:59.00#ibcon#about to write, iclass 16, count 0 2006.253.07:59:59.00#ibcon#wrote, iclass 16, count 0 2006.253.07:59:59.00#ibcon#about to read 3, iclass 16, count 0 2006.253.07:59:59.04#ibcon#read 3, iclass 16, count 0 2006.253.07:59:59.04#ibcon#about to read 4, iclass 16, count 0 2006.253.07:59:59.04#ibcon#read 4, iclass 16, count 0 2006.253.07:59:59.04#ibcon#about to read 5, iclass 16, count 0 2006.253.07:59:59.04#ibcon#read 5, iclass 16, count 0 2006.253.07:59:59.04#ibcon#about to read 6, iclass 16, count 0 2006.253.07:59:59.04#ibcon#read 6, iclass 16, count 0 2006.253.07:59:59.04#ibcon#end of sib2, iclass 16, count 0 2006.253.07:59:59.04#ibcon#*after write, iclass 16, count 0 2006.253.07:59:59.04#ibcon#*before return 0, iclass 16, count 0 2006.253.07:59:59.04#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.253.07:59:59.04#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.253.07:59:59.04#ibcon#about to clear, iclass 16 cls_cnt 0 2006.253.07:59:59.04#ibcon#cleared, iclass 16 cls_cnt 0 2006.253.07:59:59.04$vc4f8/va=4,7 2006.253.07:59:59.04#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.253.07:59:59.04#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.253.07:59:59.04#ibcon#ireg 11 cls_cnt 2 2006.253.07:59:59.04#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.253.07:59:59.09#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.253.07:59:59.09#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.253.07:59:59.09#ibcon#enter wrdev, iclass 18, count 2 2006.253.07:59:59.09#ibcon#first serial, iclass 18, count 2 2006.253.07:59:59.09#ibcon#enter sib2, iclass 18, count 2 2006.253.07:59:59.09#ibcon#flushed, iclass 18, count 2 2006.253.07:59:59.09#ibcon#about to write, iclass 18, count 2 2006.253.07:59:59.09#ibcon#wrote, iclass 18, count 2 2006.253.07:59:59.09#ibcon#about to read 3, iclass 18, count 2 2006.253.07:59:59.11#ibcon#read 3, iclass 18, count 2 2006.253.07:59:59.11#ibcon#about to read 4, iclass 18, count 2 2006.253.07:59:59.11#ibcon#read 4, iclass 18, count 2 2006.253.07:59:59.11#ibcon#about to read 5, iclass 18, count 2 2006.253.07:59:59.11#ibcon#read 5, iclass 18, count 2 2006.253.07:59:59.11#ibcon#about to read 6, iclass 18, count 2 2006.253.07:59:59.11#ibcon#read 6, iclass 18, count 2 2006.253.07:59:59.11#ibcon#end of sib2, iclass 18, count 2 2006.253.07:59:59.11#ibcon#*mode == 0, iclass 18, count 2 2006.253.07:59:59.11#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.253.07:59:59.11#ibcon#[25=AT04-07\r\n] 2006.253.07:59:59.11#ibcon#*before write, iclass 18, count 2 2006.253.07:59:59.11#ibcon#enter sib2, iclass 18, count 2 2006.253.07:59:59.11#ibcon#flushed, iclass 18, count 2 2006.253.07:59:59.11#ibcon#about to write, iclass 18, count 2 2006.253.07:59:59.11#ibcon#wrote, iclass 18, count 2 2006.253.07:59:59.11#ibcon#about to read 3, iclass 18, count 2 2006.253.07:59:59.14#ibcon#read 3, iclass 18, count 2 2006.253.07:59:59.14#ibcon#about to read 4, iclass 18, count 2 2006.253.07:59:59.14#ibcon#read 4, iclass 18, count 2 2006.253.07:59:59.14#ibcon#about to read 5, iclass 18, count 2 2006.253.07:59:59.14#ibcon#read 5, iclass 18, count 2 2006.253.07:59:59.14#ibcon#about to read 6, iclass 18, count 2 2006.253.07:59:59.14#ibcon#read 6, iclass 18, count 2 2006.253.07:59:59.14#ibcon#end of sib2, iclass 18, count 2 2006.253.07:59:59.14#ibcon#*after write, iclass 18, count 2 2006.253.07:59:59.14#ibcon#*before return 0, iclass 18, count 2 2006.253.07:59:59.14#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.253.07:59:59.14#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.253.07:59:59.14#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.253.07:59:59.14#ibcon#ireg 7 cls_cnt 0 2006.253.07:59:59.14#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.253.07:59:59.26#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.253.07:59:59.26#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.253.07:59:59.26#ibcon#enter wrdev, iclass 18, count 0 2006.253.07:59:59.26#ibcon#first serial, iclass 18, count 0 2006.253.07:59:59.26#ibcon#enter sib2, iclass 18, count 0 2006.253.07:59:59.26#ibcon#flushed, iclass 18, count 0 2006.253.07:59:59.26#ibcon#about to write, iclass 18, count 0 2006.253.07:59:59.26#ibcon#wrote, iclass 18, count 0 2006.253.07:59:59.26#ibcon#about to read 3, iclass 18, count 0 2006.253.07:59:59.28#ibcon#read 3, iclass 18, count 0 2006.253.07:59:59.28#ibcon#about to read 4, iclass 18, count 0 2006.253.07:59:59.28#ibcon#read 4, iclass 18, count 0 2006.253.07:59:59.28#ibcon#about to read 5, iclass 18, count 0 2006.253.07:59:59.28#ibcon#read 5, iclass 18, count 0 2006.253.07:59:59.28#ibcon#about to read 6, iclass 18, count 0 2006.253.07:59:59.28#ibcon#read 6, iclass 18, count 0 2006.253.07:59:59.28#ibcon#end of sib2, iclass 18, count 0 2006.253.07:59:59.28#ibcon#*mode == 0, iclass 18, count 0 2006.253.07:59:59.28#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.253.07:59:59.28#ibcon#[25=USB\r\n] 2006.253.07:59:59.28#ibcon#*before write, iclass 18, count 0 2006.253.07:59:59.28#ibcon#enter sib2, iclass 18, count 0 2006.253.07:59:59.28#ibcon#flushed, iclass 18, count 0 2006.253.07:59:59.28#ibcon#about to write, iclass 18, count 0 2006.253.07:59:59.28#ibcon#wrote, iclass 18, count 0 2006.253.07:59:59.28#ibcon#about to read 3, iclass 18, count 0 2006.253.07:59:59.31#ibcon#read 3, iclass 18, count 0 2006.253.07:59:59.31#ibcon#about to read 4, iclass 18, count 0 2006.253.07:59:59.31#ibcon#read 4, iclass 18, count 0 2006.253.07:59:59.31#ibcon#about to read 5, iclass 18, count 0 2006.253.07:59:59.31#ibcon#read 5, iclass 18, count 0 2006.253.07:59:59.31#ibcon#about to read 6, iclass 18, count 0 2006.253.07:59:59.31#ibcon#read 6, iclass 18, count 0 2006.253.07:59:59.31#ibcon#end of sib2, iclass 18, count 0 2006.253.07:59:59.31#ibcon#*after write, iclass 18, count 0 2006.253.07:59:59.31#ibcon#*before return 0, iclass 18, count 0 2006.253.07:59:59.31#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.253.07:59:59.31#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.253.07:59:59.31#ibcon#about to clear, iclass 18 cls_cnt 0 2006.253.07:59:59.31#ibcon#cleared, iclass 18 cls_cnt 0 2006.253.07:59:59.31$vc4f8/valo=5,652.99 2006.253.07:59:59.31#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.253.07:59:59.31#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.253.07:59:59.31#ibcon#ireg 17 cls_cnt 0 2006.253.07:59:59.31#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.253.07:59:59.31#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.253.07:59:59.31#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.253.07:59:59.31#ibcon#enter wrdev, iclass 20, count 0 2006.253.07:59:59.31#ibcon#first serial, iclass 20, count 0 2006.253.07:59:59.31#ibcon#enter sib2, iclass 20, count 0 2006.253.07:59:59.31#ibcon#flushed, iclass 20, count 0 2006.253.07:59:59.31#ibcon#about to write, iclass 20, count 0 2006.253.07:59:59.31#ibcon#wrote, iclass 20, count 0 2006.253.07:59:59.31#ibcon#about to read 3, iclass 20, count 0 2006.253.07:59:59.33#ibcon#read 3, iclass 20, count 0 2006.253.07:59:59.33#ibcon#about to read 4, iclass 20, count 0 2006.253.07:59:59.33#ibcon#read 4, iclass 20, count 0 2006.253.07:59:59.33#ibcon#about to read 5, iclass 20, count 0 2006.253.07:59:59.33#ibcon#read 5, iclass 20, count 0 2006.253.07:59:59.33#ibcon#about to read 6, iclass 20, count 0 2006.253.07:59:59.33#ibcon#read 6, iclass 20, count 0 2006.253.07:59:59.33#ibcon#end of sib2, iclass 20, count 0 2006.253.07:59:59.33#ibcon#*mode == 0, iclass 20, count 0 2006.253.07:59:59.33#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.253.07:59:59.33#ibcon#[26=FRQ=05,652.99\r\n] 2006.253.07:59:59.33#ibcon#*before write, iclass 20, count 0 2006.253.07:59:59.33#ibcon#enter sib2, iclass 20, count 0 2006.253.07:59:59.33#ibcon#flushed, iclass 20, count 0 2006.253.07:59:59.33#ibcon#about to write, iclass 20, count 0 2006.253.07:59:59.33#ibcon#wrote, iclass 20, count 0 2006.253.07:59:59.33#ibcon#about to read 3, iclass 20, count 0 2006.253.07:59:59.37#ibcon#read 3, iclass 20, count 0 2006.253.07:59:59.37#ibcon#about to read 4, iclass 20, count 0 2006.253.07:59:59.37#ibcon#read 4, iclass 20, count 0 2006.253.07:59:59.37#ibcon#about to read 5, iclass 20, count 0 2006.253.07:59:59.37#ibcon#read 5, iclass 20, count 0 2006.253.07:59:59.37#ibcon#about to read 6, iclass 20, count 0 2006.253.07:59:59.37#ibcon#read 6, iclass 20, count 0 2006.253.07:59:59.37#ibcon#end of sib2, iclass 20, count 0 2006.253.07:59:59.37#ibcon#*after write, iclass 20, count 0 2006.253.07:59:59.37#ibcon#*before return 0, iclass 20, count 0 2006.253.07:59:59.37#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.253.07:59:59.37#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.253.07:59:59.37#ibcon#about to clear, iclass 20 cls_cnt 0 2006.253.07:59:59.37#ibcon#cleared, iclass 20 cls_cnt 0 2006.253.07:59:59.37$vc4f8/va=5,7 2006.253.07:59:59.37#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.253.07:59:59.37#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.253.07:59:59.37#ibcon#ireg 11 cls_cnt 2 2006.253.07:59:59.37#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.253.07:59:59.43#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.253.07:59:59.43#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.253.07:59:59.43#ibcon#enter wrdev, iclass 22, count 2 2006.253.07:59:59.43#ibcon#first serial, iclass 22, count 2 2006.253.07:59:59.43#ibcon#enter sib2, iclass 22, count 2 2006.253.07:59:59.43#ibcon#flushed, iclass 22, count 2 2006.253.07:59:59.43#ibcon#about to write, iclass 22, count 2 2006.253.07:59:59.43#ibcon#wrote, iclass 22, count 2 2006.253.07:59:59.43#ibcon#about to read 3, iclass 22, count 2 2006.253.07:59:59.45#ibcon#read 3, iclass 22, count 2 2006.253.07:59:59.45#ibcon#about to read 4, iclass 22, count 2 2006.253.07:59:59.45#ibcon#read 4, iclass 22, count 2 2006.253.07:59:59.45#ibcon#about to read 5, iclass 22, count 2 2006.253.07:59:59.45#ibcon#read 5, iclass 22, count 2 2006.253.07:59:59.45#ibcon#about to read 6, iclass 22, count 2 2006.253.07:59:59.45#ibcon#read 6, iclass 22, count 2 2006.253.07:59:59.45#ibcon#end of sib2, iclass 22, count 2 2006.253.07:59:59.45#ibcon#*mode == 0, iclass 22, count 2 2006.253.07:59:59.45#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.253.07:59:59.45#ibcon#[25=AT05-07\r\n] 2006.253.07:59:59.45#ibcon#*before write, iclass 22, count 2 2006.253.07:59:59.45#ibcon#enter sib2, iclass 22, count 2 2006.253.07:59:59.45#ibcon#flushed, iclass 22, count 2 2006.253.07:59:59.45#ibcon#about to write, iclass 22, count 2 2006.253.07:59:59.45#ibcon#wrote, iclass 22, count 2 2006.253.07:59:59.45#ibcon#about to read 3, iclass 22, count 2 2006.253.07:59:59.48#ibcon#read 3, iclass 22, count 2 2006.253.07:59:59.48#ibcon#about to read 4, iclass 22, count 2 2006.253.07:59:59.48#ibcon#read 4, iclass 22, count 2 2006.253.07:59:59.48#ibcon#about to read 5, iclass 22, count 2 2006.253.07:59:59.48#ibcon#read 5, iclass 22, count 2 2006.253.07:59:59.48#ibcon#about to read 6, iclass 22, count 2 2006.253.07:59:59.48#ibcon#read 6, iclass 22, count 2 2006.253.07:59:59.48#ibcon#end of sib2, iclass 22, count 2 2006.253.07:59:59.48#ibcon#*after write, iclass 22, count 2 2006.253.07:59:59.48#ibcon#*before return 0, iclass 22, count 2 2006.253.07:59:59.48#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.253.07:59:59.48#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.253.07:59:59.48#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.253.07:59:59.48#ibcon#ireg 7 cls_cnt 0 2006.253.07:59:59.48#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.253.07:59:59.60#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.253.07:59:59.60#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.253.07:59:59.60#ibcon#enter wrdev, iclass 22, count 0 2006.253.07:59:59.60#ibcon#first serial, iclass 22, count 0 2006.253.07:59:59.60#ibcon#enter sib2, iclass 22, count 0 2006.253.07:59:59.60#ibcon#flushed, iclass 22, count 0 2006.253.07:59:59.60#ibcon#about to write, iclass 22, count 0 2006.253.07:59:59.60#ibcon#wrote, iclass 22, count 0 2006.253.07:59:59.60#ibcon#about to read 3, iclass 22, count 0 2006.253.07:59:59.62#ibcon#read 3, iclass 22, count 0 2006.253.07:59:59.62#ibcon#about to read 4, iclass 22, count 0 2006.253.07:59:59.62#ibcon#read 4, iclass 22, count 0 2006.253.07:59:59.62#ibcon#about to read 5, iclass 22, count 0 2006.253.07:59:59.62#ibcon#read 5, iclass 22, count 0 2006.253.07:59:59.62#ibcon#about to read 6, iclass 22, count 0 2006.253.07:59:59.62#ibcon#read 6, iclass 22, count 0 2006.253.07:59:59.62#ibcon#end of sib2, iclass 22, count 0 2006.253.07:59:59.62#ibcon#*mode == 0, iclass 22, count 0 2006.253.07:59:59.62#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.253.07:59:59.62#ibcon#[25=USB\r\n] 2006.253.07:59:59.62#ibcon#*before write, iclass 22, count 0 2006.253.07:59:59.62#ibcon#enter sib2, iclass 22, count 0 2006.253.07:59:59.62#ibcon#flushed, iclass 22, count 0 2006.253.07:59:59.62#ibcon#about to write, iclass 22, count 0 2006.253.07:59:59.62#ibcon#wrote, iclass 22, count 0 2006.253.07:59:59.62#ibcon#about to read 3, iclass 22, count 0 2006.253.07:59:59.65#ibcon#read 3, iclass 22, count 0 2006.253.07:59:59.65#ibcon#about to read 4, iclass 22, count 0 2006.253.07:59:59.65#ibcon#read 4, iclass 22, count 0 2006.253.07:59:59.65#ibcon#about to read 5, iclass 22, count 0 2006.253.07:59:59.65#ibcon#read 5, iclass 22, count 0 2006.253.07:59:59.65#ibcon#about to read 6, iclass 22, count 0 2006.253.07:59:59.65#ibcon#read 6, iclass 22, count 0 2006.253.07:59:59.65#ibcon#end of sib2, iclass 22, count 0 2006.253.07:59:59.65#ibcon#*after write, iclass 22, count 0 2006.253.07:59:59.65#ibcon#*before return 0, iclass 22, count 0 2006.253.07:59:59.65#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.253.07:59:59.65#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.253.07:59:59.65#ibcon#about to clear, iclass 22 cls_cnt 0 2006.253.07:59:59.65#ibcon#cleared, iclass 22 cls_cnt 0 2006.253.07:59:59.65$vc4f8/valo=6,772.99 2006.253.07:59:59.65#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.253.07:59:59.65#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.253.07:59:59.65#ibcon#ireg 17 cls_cnt 0 2006.253.07:59:59.65#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.253.07:59:59.65#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.253.07:59:59.65#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.253.07:59:59.65#ibcon#enter wrdev, iclass 24, count 0 2006.253.07:59:59.65#ibcon#first serial, iclass 24, count 0 2006.253.07:59:59.65#ibcon#enter sib2, iclass 24, count 0 2006.253.07:59:59.65#ibcon#flushed, iclass 24, count 0 2006.253.07:59:59.65#ibcon#about to write, iclass 24, count 0 2006.253.07:59:59.65#ibcon#wrote, iclass 24, count 0 2006.253.07:59:59.65#ibcon#about to read 3, iclass 24, count 0 2006.253.07:59:59.68#ibcon#read 3, iclass 24, count 0 2006.253.07:59:59.68#ibcon#about to read 4, iclass 24, count 0 2006.253.07:59:59.68#ibcon#read 4, iclass 24, count 0 2006.253.07:59:59.68#ibcon#about to read 5, iclass 24, count 0 2006.253.07:59:59.68#ibcon#read 5, iclass 24, count 0 2006.253.07:59:59.68#ibcon#about to read 6, iclass 24, count 0 2006.253.07:59:59.68#ibcon#read 6, iclass 24, count 0 2006.253.07:59:59.68#ibcon#end of sib2, iclass 24, count 0 2006.253.07:59:59.68#ibcon#*mode == 0, iclass 24, count 0 2006.253.07:59:59.68#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.253.07:59:59.68#ibcon#[26=FRQ=06,772.99\r\n] 2006.253.07:59:59.68#ibcon#*before write, iclass 24, count 0 2006.253.07:59:59.68#ibcon#enter sib2, iclass 24, count 0 2006.253.07:59:59.68#ibcon#flushed, iclass 24, count 0 2006.253.07:59:59.68#ibcon#about to write, iclass 24, count 0 2006.253.07:59:59.68#ibcon#wrote, iclass 24, count 0 2006.253.07:59:59.68#ibcon#about to read 3, iclass 24, count 0 2006.253.07:59:59.72#ibcon#read 3, iclass 24, count 0 2006.253.07:59:59.72#ibcon#about to read 4, iclass 24, count 0 2006.253.07:59:59.72#ibcon#read 4, iclass 24, count 0 2006.253.07:59:59.72#ibcon#about to read 5, iclass 24, count 0 2006.253.07:59:59.72#ibcon#read 5, iclass 24, count 0 2006.253.07:59:59.72#ibcon#about to read 6, iclass 24, count 0 2006.253.07:59:59.72#ibcon#read 6, iclass 24, count 0 2006.253.07:59:59.72#ibcon#end of sib2, iclass 24, count 0 2006.253.07:59:59.72#ibcon#*after write, iclass 24, count 0 2006.253.07:59:59.72#ibcon#*before return 0, iclass 24, count 0 2006.253.07:59:59.72#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.253.07:59:59.72#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.253.07:59:59.72#ibcon#about to clear, iclass 24 cls_cnt 0 2006.253.07:59:59.72#ibcon#cleared, iclass 24 cls_cnt 0 2006.253.07:59:59.72$vc4f8/va=6,7 2006.253.07:59:59.72#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.253.07:59:59.72#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.253.07:59:59.72#ibcon#ireg 11 cls_cnt 2 2006.253.07:59:59.72#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.253.07:59:59.77#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.253.07:59:59.77#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.253.07:59:59.77#ibcon#enter wrdev, iclass 26, count 2 2006.253.07:59:59.77#ibcon#first serial, iclass 26, count 2 2006.253.07:59:59.77#ibcon#enter sib2, iclass 26, count 2 2006.253.07:59:59.77#ibcon#flushed, iclass 26, count 2 2006.253.07:59:59.77#ibcon#about to write, iclass 26, count 2 2006.253.07:59:59.77#ibcon#wrote, iclass 26, count 2 2006.253.07:59:59.77#ibcon#about to read 3, iclass 26, count 2 2006.253.07:59:59.79#ibcon#read 3, iclass 26, count 2 2006.253.07:59:59.79#ibcon#about to read 4, iclass 26, count 2 2006.253.07:59:59.79#ibcon#read 4, iclass 26, count 2 2006.253.07:59:59.79#ibcon#about to read 5, iclass 26, count 2 2006.253.07:59:59.79#ibcon#read 5, iclass 26, count 2 2006.253.07:59:59.79#ibcon#about to read 6, iclass 26, count 2 2006.253.07:59:59.79#ibcon#read 6, iclass 26, count 2 2006.253.07:59:59.79#ibcon#end of sib2, iclass 26, count 2 2006.253.07:59:59.79#ibcon#*mode == 0, iclass 26, count 2 2006.253.07:59:59.79#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.253.07:59:59.79#ibcon#[25=AT06-07\r\n] 2006.253.07:59:59.79#ibcon#*before write, iclass 26, count 2 2006.253.07:59:59.79#ibcon#enter sib2, iclass 26, count 2 2006.253.07:59:59.79#ibcon#flushed, iclass 26, count 2 2006.253.07:59:59.79#ibcon#about to write, iclass 26, count 2 2006.253.07:59:59.79#ibcon#wrote, iclass 26, count 2 2006.253.07:59:59.79#ibcon#about to read 3, iclass 26, count 2 2006.253.07:59:59.82#ibcon#read 3, iclass 26, count 2 2006.253.07:59:59.82#ibcon#about to read 4, iclass 26, count 2 2006.253.07:59:59.82#ibcon#read 4, iclass 26, count 2 2006.253.07:59:59.82#ibcon#about to read 5, iclass 26, count 2 2006.253.07:59:59.82#ibcon#read 5, iclass 26, count 2 2006.253.07:59:59.82#ibcon#about to read 6, iclass 26, count 2 2006.253.07:59:59.82#ibcon#read 6, iclass 26, count 2 2006.253.07:59:59.82#ibcon#end of sib2, iclass 26, count 2 2006.253.07:59:59.82#ibcon#*after write, iclass 26, count 2 2006.253.07:59:59.82#ibcon#*before return 0, iclass 26, count 2 2006.253.07:59:59.82#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.253.07:59:59.82#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.253.07:59:59.82#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.253.07:59:59.82#ibcon#ireg 7 cls_cnt 0 2006.253.07:59:59.82#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.253.07:59:59.94#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.253.07:59:59.94#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.253.07:59:59.94#ibcon#enter wrdev, iclass 26, count 0 2006.253.07:59:59.94#ibcon#first serial, iclass 26, count 0 2006.253.07:59:59.94#ibcon#enter sib2, iclass 26, count 0 2006.253.07:59:59.94#ibcon#flushed, iclass 26, count 0 2006.253.07:59:59.94#ibcon#about to write, iclass 26, count 0 2006.253.07:59:59.94#ibcon#wrote, iclass 26, count 0 2006.253.07:59:59.94#ibcon#about to read 3, iclass 26, count 0 2006.253.07:59:59.96#ibcon#read 3, iclass 26, count 0 2006.253.07:59:59.96#ibcon#about to read 4, iclass 26, count 0 2006.253.07:59:59.96#ibcon#read 4, iclass 26, count 0 2006.253.07:59:59.96#ibcon#about to read 5, iclass 26, count 0 2006.253.07:59:59.96#ibcon#read 5, iclass 26, count 0 2006.253.07:59:59.96#ibcon#about to read 6, iclass 26, count 0 2006.253.07:59:59.96#ibcon#read 6, iclass 26, count 0 2006.253.07:59:59.96#ibcon#end of sib2, iclass 26, count 0 2006.253.07:59:59.96#ibcon#*mode == 0, iclass 26, count 0 2006.253.07:59:59.96#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.253.07:59:59.96#ibcon#[25=USB\r\n] 2006.253.07:59:59.96#ibcon#*before write, iclass 26, count 0 2006.253.07:59:59.96#ibcon#enter sib2, iclass 26, count 0 2006.253.07:59:59.96#ibcon#flushed, iclass 26, count 0 2006.253.07:59:59.96#ibcon#about to write, iclass 26, count 0 2006.253.07:59:59.96#ibcon#wrote, iclass 26, count 0 2006.253.07:59:59.96#ibcon#about to read 3, iclass 26, count 0 2006.253.07:59:59.99#ibcon#read 3, iclass 26, count 0 2006.253.07:59:59.99#ibcon#about to read 4, iclass 26, count 0 2006.253.07:59:59.99#ibcon#read 4, iclass 26, count 0 2006.253.07:59:59.99#ibcon#about to read 5, iclass 26, count 0 2006.253.07:59:59.99#ibcon#read 5, iclass 26, count 0 2006.253.07:59:59.99#ibcon#about to read 6, iclass 26, count 0 2006.253.07:59:59.99#ibcon#read 6, iclass 26, count 0 2006.253.07:59:59.99#ibcon#end of sib2, iclass 26, count 0 2006.253.07:59:59.99#ibcon#*after write, iclass 26, count 0 2006.253.07:59:59.99#ibcon#*before return 0, iclass 26, count 0 2006.253.07:59:59.99#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.253.07:59:59.99#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.253.07:59:59.99#ibcon#about to clear, iclass 26 cls_cnt 0 2006.253.07:59:59.99#ibcon#cleared, iclass 26 cls_cnt 0 2006.253.07:59:59.99$vc4f8/valo=7,832.99 2006.253.07:59:59.99#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.253.07:59:59.99#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.253.07:59:59.99#ibcon#ireg 17 cls_cnt 0 2006.253.07:59:59.99#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.253.07:59:59.99#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.253.07:59:59.99#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.253.07:59:59.99#ibcon#enter wrdev, iclass 28, count 0 2006.253.07:59:59.99#ibcon#first serial, iclass 28, count 0 2006.253.07:59:59.99#ibcon#enter sib2, iclass 28, count 0 2006.253.07:59:59.99#ibcon#flushed, iclass 28, count 0 2006.253.07:59:59.99#ibcon#about to write, iclass 28, count 0 2006.253.07:59:59.99#ibcon#wrote, iclass 28, count 0 2006.253.07:59:59.99#ibcon#about to read 3, iclass 28, count 0 2006.253.08:00:00.01#ibcon#read 3, iclass 28, count 0 2006.253.08:00:00.01#ibcon#about to read 4, iclass 28, count 0 2006.253.08:00:00.01#ibcon#read 4, iclass 28, count 0 2006.253.08:00:00.01#ibcon#about to read 5, iclass 28, count 0 2006.253.08:00:00.01#ibcon#read 5, iclass 28, count 0 2006.253.08:00:00.01#ibcon#about to read 6, iclass 28, count 0 2006.253.08:00:00.01#ibcon#read 6, iclass 28, count 0 2006.253.08:00:00.01#ibcon#end of sib2, iclass 28, count 0 2006.253.08:00:00.01#ibcon#*mode == 0, iclass 28, count 0 2006.253.08:00:00.01#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.253.08:00:00.01#ibcon#[26=FRQ=07,832.99\r\n] 2006.253.08:00:00.01#ibcon#*before write, iclass 28, count 0 2006.253.08:00:00.01#ibcon#enter sib2, iclass 28, count 0 2006.253.08:00:00.01#ibcon#flushed, iclass 28, count 0 2006.253.08:00:00.01#ibcon#about to write, iclass 28, count 0 2006.253.08:00:00.01#ibcon#wrote, iclass 28, count 0 2006.253.08:00:00.01#ibcon#about to read 3, iclass 28, count 0 2006.253.08:00:00.05#ibcon#read 3, iclass 28, count 0 2006.253.08:00:00.05#ibcon#about to read 4, iclass 28, count 0 2006.253.08:00:00.05#ibcon#read 4, iclass 28, count 0 2006.253.08:00:00.05#ibcon#about to read 5, iclass 28, count 0 2006.253.08:00:00.05#ibcon#read 5, iclass 28, count 0 2006.253.08:00:00.05#ibcon#about to read 6, iclass 28, count 0 2006.253.08:00:00.05#ibcon#read 6, iclass 28, count 0 2006.253.08:00:00.05#ibcon#end of sib2, iclass 28, count 0 2006.253.08:00:00.05#ibcon#*after write, iclass 28, count 0 2006.253.08:00:00.05#ibcon#*before return 0, iclass 28, count 0 2006.253.08:00:00.05#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.253.08:00:00.05#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.253.08:00:00.05#ibcon#about to clear, iclass 28 cls_cnt 0 2006.253.08:00:00.05#ibcon#cleared, iclass 28 cls_cnt 0 2006.253.08:00:00.05$vc4f8/va=7,7 2006.253.08:00:00.05#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.253.08:00:00.05#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.253.08:00:00.05#ibcon#ireg 11 cls_cnt 2 2006.253.08:00:00.05#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.253.08:00:00.11#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.253.08:00:00.11#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.253.08:00:00.11#ibcon#enter wrdev, iclass 30, count 2 2006.253.08:00:00.11#ibcon#first serial, iclass 30, count 2 2006.253.08:00:00.11#ibcon#enter sib2, iclass 30, count 2 2006.253.08:00:00.11#ibcon#flushed, iclass 30, count 2 2006.253.08:00:00.11#ibcon#about to write, iclass 30, count 2 2006.253.08:00:00.11#ibcon#wrote, iclass 30, count 2 2006.253.08:00:00.11#ibcon#about to read 3, iclass 30, count 2 2006.253.08:00:00.13#ibcon#read 3, iclass 30, count 2 2006.253.08:00:00.13#ibcon#about to read 4, iclass 30, count 2 2006.253.08:00:00.13#ibcon#read 4, iclass 30, count 2 2006.253.08:00:00.13#ibcon#about to read 5, iclass 30, count 2 2006.253.08:00:00.13#ibcon#read 5, iclass 30, count 2 2006.253.08:00:00.13#ibcon#about to read 6, iclass 30, count 2 2006.253.08:00:00.13#ibcon#read 6, iclass 30, count 2 2006.253.08:00:00.13#ibcon#end of sib2, iclass 30, count 2 2006.253.08:00:00.13#ibcon#*mode == 0, iclass 30, count 2 2006.253.08:00:00.13#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.253.08:00:00.13#ibcon#[25=AT07-07\r\n] 2006.253.08:00:00.13#ibcon#*before write, iclass 30, count 2 2006.253.08:00:00.13#ibcon#enter sib2, iclass 30, count 2 2006.253.08:00:00.13#ibcon#flushed, iclass 30, count 2 2006.253.08:00:00.13#ibcon#about to write, iclass 30, count 2 2006.253.08:00:00.13#ibcon#wrote, iclass 30, count 2 2006.253.08:00:00.13#ibcon#about to read 3, iclass 30, count 2 2006.253.08:00:00.16#ibcon#read 3, iclass 30, count 2 2006.253.08:00:00.16#ibcon#about to read 4, iclass 30, count 2 2006.253.08:00:00.16#ibcon#read 4, iclass 30, count 2 2006.253.08:00:00.16#ibcon#about to read 5, iclass 30, count 2 2006.253.08:00:00.16#ibcon#read 5, iclass 30, count 2 2006.253.08:00:00.16#ibcon#about to read 6, iclass 30, count 2 2006.253.08:00:00.16#ibcon#read 6, iclass 30, count 2 2006.253.08:00:00.16#ibcon#end of sib2, iclass 30, count 2 2006.253.08:00:00.16#ibcon#*after write, iclass 30, count 2 2006.253.08:00:00.16#ibcon#*before return 0, iclass 30, count 2 2006.253.08:00:00.16#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.253.08:00:00.16#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.253.08:00:00.16#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.253.08:00:00.16#ibcon#ireg 7 cls_cnt 0 2006.253.08:00:00.16#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.253.08:00:00.28#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.253.08:00:00.28#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.253.08:00:00.28#ibcon#enter wrdev, iclass 30, count 0 2006.253.08:00:00.28#ibcon#first serial, iclass 30, count 0 2006.253.08:00:00.28#ibcon#enter sib2, iclass 30, count 0 2006.253.08:00:00.28#ibcon#flushed, iclass 30, count 0 2006.253.08:00:00.28#ibcon#about to write, iclass 30, count 0 2006.253.08:00:00.28#ibcon#wrote, iclass 30, count 0 2006.253.08:00:00.28#ibcon#about to read 3, iclass 30, count 0 2006.253.08:00:00.30#ibcon#read 3, iclass 30, count 0 2006.253.08:00:00.30#ibcon#about to read 4, iclass 30, count 0 2006.253.08:00:00.30#ibcon#read 4, iclass 30, count 0 2006.253.08:00:00.30#ibcon#about to read 5, iclass 30, count 0 2006.253.08:00:00.30#ibcon#read 5, iclass 30, count 0 2006.253.08:00:00.30#ibcon#about to read 6, iclass 30, count 0 2006.253.08:00:00.30#ibcon#read 6, iclass 30, count 0 2006.253.08:00:00.30#ibcon#end of sib2, iclass 30, count 0 2006.253.08:00:00.30#ibcon#*mode == 0, iclass 30, count 0 2006.253.08:00:00.30#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.253.08:00:00.30#ibcon#[25=USB\r\n] 2006.253.08:00:00.30#ibcon#*before write, iclass 30, count 0 2006.253.08:00:00.30#ibcon#enter sib2, iclass 30, count 0 2006.253.08:00:00.30#ibcon#flushed, iclass 30, count 0 2006.253.08:00:00.30#ibcon#about to write, iclass 30, count 0 2006.253.08:00:00.30#ibcon#wrote, iclass 30, count 0 2006.253.08:00:00.30#ibcon#about to read 3, iclass 30, count 0 2006.253.08:00:00.33#ibcon#read 3, iclass 30, count 0 2006.253.08:00:00.33#ibcon#about to read 4, iclass 30, count 0 2006.253.08:00:00.33#ibcon#read 4, iclass 30, count 0 2006.253.08:00:00.33#ibcon#about to read 5, iclass 30, count 0 2006.253.08:00:00.33#ibcon#read 5, iclass 30, count 0 2006.253.08:00:00.33#ibcon#about to read 6, iclass 30, count 0 2006.253.08:00:00.33#ibcon#read 6, iclass 30, count 0 2006.253.08:00:00.33#ibcon#end of sib2, iclass 30, count 0 2006.253.08:00:00.33#ibcon#*after write, iclass 30, count 0 2006.253.08:00:00.33#ibcon#*before return 0, iclass 30, count 0 2006.253.08:00:00.33#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.253.08:00:00.33#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.253.08:00:00.33#ibcon#about to clear, iclass 30 cls_cnt 0 2006.253.08:00:00.33#ibcon#cleared, iclass 30 cls_cnt 0 2006.253.08:00:00.33$vc4f8/valo=8,852.99 2006.253.08:00:00.33#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.253.08:00:00.33#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.253.08:00:00.33#ibcon#ireg 17 cls_cnt 0 2006.253.08:00:00.33#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.253.08:00:00.33#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.253.08:00:00.33#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.253.08:00:00.33#ibcon#enter wrdev, iclass 32, count 0 2006.253.08:00:00.33#ibcon#first serial, iclass 32, count 0 2006.253.08:00:00.33#ibcon#enter sib2, iclass 32, count 0 2006.253.08:00:00.33#ibcon#flushed, iclass 32, count 0 2006.253.08:00:00.33#ibcon#about to write, iclass 32, count 0 2006.253.08:00:00.33#ibcon#wrote, iclass 32, count 0 2006.253.08:00:00.33#ibcon#about to read 3, iclass 32, count 0 2006.253.08:00:00.35#ibcon#read 3, iclass 32, count 0 2006.253.08:00:00.35#ibcon#about to read 4, iclass 32, count 0 2006.253.08:00:00.35#ibcon#read 4, iclass 32, count 0 2006.253.08:00:00.35#ibcon#about to read 5, iclass 32, count 0 2006.253.08:00:00.35#ibcon#read 5, iclass 32, count 0 2006.253.08:00:00.35#ibcon#about to read 6, iclass 32, count 0 2006.253.08:00:00.35#ibcon#read 6, iclass 32, count 0 2006.253.08:00:00.35#ibcon#end of sib2, iclass 32, count 0 2006.253.08:00:00.35#ibcon#*mode == 0, iclass 32, count 0 2006.253.08:00:00.35#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.253.08:00:00.35#ibcon#[26=FRQ=08,852.99\r\n] 2006.253.08:00:00.35#ibcon#*before write, iclass 32, count 0 2006.253.08:00:00.35#ibcon#enter sib2, iclass 32, count 0 2006.253.08:00:00.35#ibcon#flushed, iclass 32, count 0 2006.253.08:00:00.35#ibcon#about to write, iclass 32, count 0 2006.253.08:00:00.35#ibcon#wrote, iclass 32, count 0 2006.253.08:00:00.35#ibcon#about to read 3, iclass 32, count 0 2006.253.08:00:00.39#ibcon#read 3, iclass 32, count 0 2006.253.08:00:00.39#ibcon#about to read 4, iclass 32, count 0 2006.253.08:00:00.39#ibcon#read 4, iclass 32, count 0 2006.253.08:00:00.39#ibcon#about to read 5, iclass 32, count 0 2006.253.08:00:00.39#ibcon#read 5, iclass 32, count 0 2006.253.08:00:00.39#ibcon#about to read 6, iclass 32, count 0 2006.253.08:00:00.39#ibcon#read 6, iclass 32, count 0 2006.253.08:00:00.39#ibcon#end of sib2, iclass 32, count 0 2006.253.08:00:00.39#ibcon#*after write, iclass 32, count 0 2006.253.08:00:00.39#ibcon#*before return 0, iclass 32, count 0 2006.253.08:00:00.39#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.253.08:00:00.39#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.253.08:00:00.39#ibcon#about to clear, iclass 32 cls_cnt 0 2006.253.08:00:00.39#ibcon#cleared, iclass 32 cls_cnt 0 2006.253.08:00:00.39$vc4f8/va=8,7 2006.253.08:00:00.39#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.253.08:00:00.39#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.253.08:00:00.39#ibcon#ireg 11 cls_cnt 2 2006.253.08:00:00.39#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.253.08:00:00.45#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.253.08:00:00.45#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.253.08:00:00.45#ibcon#enter wrdev, iclass 34, count 2 2006.253.08:00:00.45#ibcon#first serial, iclass 34, count 2 2006.253.08:00:00.45#ibcon#enter sib2, iclass 34, count 2 2006.253.08:00:00.45#ibcon#flushed, iclass 34, count 2 2006.253.08:00:00.45#ibcon#about to write, iclass 34, count 2 2006.253.08:00:00.45#ibcon#wrote, iclass 34, count 2 2006.253.08:00:00.45#ibcon#about to read 3, iclass 34, count 2 2006.253.08:00:00.47#ibcon#read 3, iclass 34, count 2 2006.253.08:00:00.47#ibcon#about to read 4, iclass 34, count 2 2006.253.08:00:00.47#ibcon#read 4, iclass 34, count 2 2006.253.08:00:00.47#ibcon#about to read 5, iclass 34, count 2 2006.253.08:00:00.47#ibcon#read 5, iclass 34, count 2 2006.253.08:00:00.47#ibcon#about to read 6, iclass 34, count 2 2006.253.08:00:00.47#ibcon#read 6, iclass 34, count 2 2006.253.08:00:00.47#ibcon#end of sib2, iclass 34, count 2 2006.253.08:00:00.47#ibcon#*mode == 0, iclass 34, count 2 2006.253.08:00:00.47#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.253.08:00:00.47#ibcon#[25=AT08-07\r\n] 2006.253.08:00:00.47#ibcon#*before write, iclass 34, count 2 2006.253.08:00:00.47#ibcon#enter sib2, iclass 34, count 2 2006.253.08:00:00.47#ibcon#flushed, iclass 34, count 2 2006.253.08:00:00.47#ibcon#about to write, iclass 34, count 2 2006.253.08:00:00.47#ibcon#wrote, iclass 34, count 2 2006.253.08:00:00.47#ibcon#about to read 3, iclass 34, count 2 2006.253.08:00:00.50#ibcon#read 3, iclass 34, count 2 2006.253.08:00:00.50#ibcon#about to read 4, iclass 34, count 2 2006.253.08:00:00.50#ibcon#read 4, iclass 34, count 2 2006.253.08:00:00.50#ibcon#about to read 5, iclass 34, count 2 2006.253.08:00:00.50#ibcon#read 5, iclass 34, count 2 2006.253.08:00:00.50#ibcon#about to read 6, iclass 34, count 2 2006.253.08:00:00.50#ibcon#read 6, iclass 34, count 2 2006.253.08:00:00.50#ibcon#end of sib2, iclass 34, count 2 2006.253.08:00:00.50#ibcon#*after write, iclass 34, count 2 2006.253.08:00:00.50#ibcon#*before return 0, iclass 34, count 2 2006.253.08:00:00.50#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.253.08:00:00.50#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.253.08:00:00.50#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.253.08:00:00.50#ibcon#ireg 7 cls_cnt 0 2006.253.08:00:00.50#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.253.08:00:00.62#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.253.08:00:00.62#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.253.08:00:00.62#ibcon#enter wrdev, iclass 34, count 0 2006.253.08:00:00.62#ibcon#first serial, iclass 34, count 0 2006.253.08:00:00.62#ibcon#enter sib2, iclass 34, count 0 2006.253.08:00:00.62#ibcon#flushed, iclass 34, count 0 2006.253.08:00:00.62#ibcon#about to write, iclass 34, count 0 2006.253.08:00:00.62#ibcon#wrote, iclass 34, count 0 2006.253.08:00:00.62#ibcon#about to read 3, iclass 34, count 0 2006.253.08:00:00.64#ibcon#read 3, iclass 34, count 0 2006.253.08:00:00.64#ibcon#about to read 4, iclass 34, count 0 2006.253.08:00:00.64#ibcon#read 4, iclass 34, count 0 2006.253.08:00:00.64#ibcon#about to read 5, iclass 34, count 0 2006.253.08:00:00.64#ibcon#read 5, iclass 34, count 0 2006.253.08:00:00.64#ibcon#about to read 6, iclass 34, count 0 2006.253.08:00:00.64#ibcon#read 6, iclass 34, count 0 2006.253.08:00:00.64#ibcon#end of sib2, iclass 34, count 0 2006.253.08:00:00.64#ibcon#*mode == 0, iclass 34, count 0 2006.253.08:00:00.64#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.253.08:00:00.64#ibcon#[25=USB\r\n] 2006.253.08:00:00.64#ibcon#*before write, iclass 34, count 0 2006.253.08:00:00.64#ibcon#enter sib2, iclass 34, count 0 2006.253.08:00:00.64#ibcon#flushed, iclass 34, count 0 2006.253.08:00:00.64#ibcon#about to write, iclass 34, count 0 2006.253.08:00:00.64#ibcon#wrote, iclass 34, count 0 2006.253.08:00:00.64#ibcon#about to read 3, iclass 34, count 0 2006.253.08:00:00.67#ibcon#read 3, iclass 34, count 0 2006.253.08:00:00.67#ibcon#about to read 4, iclass 34, count 0 2006.253.08:00:00.67#ibcon#read 4, iclass 34, count 0 2006.253.08:00:00.67#ibcon#about to read 5, iclass 34, count 0 2006.253.08:00:00.67#ibcon#read 5, iclass 34, count 0 2006.253.08:00:00.67#ibcon#about to read 6, iclass 34, count 0 2006.253.08:00:00.67#ibcon#read 6, iclass 34, count 0 2006.253.08:00:00.67#ibcon#end of sib2, iclass 34, count 0 2006.253.08:00:00.67#ibcon#*after write, iclass 34, count 0 2006.253.08:00:00.67#ibcon#*before return 0, iclass 34, count 0 2006.253.08:00:00.67#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.253.08:00:00.67#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.253.08:00:00.67#ibcon#about to clear, iclass 34 cls_cnt 0 2006.253.08:00:00.67#ibcon#cleared, iclass 34 cls_cnt 0 2006.253.08:00:00.67$vc4f8/vblo=1,632.99 2006.253.08:00:00.67#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.253.08:00:00.67#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.253.08:00:00.67#ibcon#ireg 17 cls_cnt 0 2006.253.08:00:00.67#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.253.08:00:00.67#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.253.08:00:00.67#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.253.08:00:00.67#ibcon#enter wrdev, iclass 36, count 0 2006.253.08:00:00.67#ibcon#first serial, iclass 36, count 0 2006.253.08:00:00.67#ibcon#enter sib2, iclass 36, count 0 2006.253.08:00:00.67#ibcon#flushed, iclass 36, count 0 2006.253.08:00:00.67#ibcon#about to write, iclass 36, count 0 2006.253.08:00:00.67#ibcon#wrote, iclass 36, count 0 2006.253.08:00:00.67#ibcon#about to read 3, iclass 36, count 0 2006.253.08:00:00.70#ibcon#read 3, iclass 36, count 0 2006.253.08:00:00.70#ibcon#about to read 4, iclass 36, count 0 2006.253.08:00:00.70#ibcon#read 4, iclass 36, count 0 2006.253.08:00:00.70#ibcon#about to read 5, iclass 36, count 0 2006.253.08:00:00.70#ibcon#read 5, iclass 36, count 0 2006.253.08:00:00.70#ibcon#about to read 6, iclass 36, count 0 2006.253.08:00:00.70#ibcon#read 6, iclass 36, count 0 2006.253.08:00:00.70#ibcon#end of sib2, iclass 36, count 0 2006.253.08:00:00.70#ibcon#*mode == 0, iclass 36, count 0 2006.253.08:00:00.70#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.253.08:00:00.70#ibcon#[28=FRQ=01,632.99\r\n] 2006.253.08:00:00.70#ibcon#*before write, iclass 36, count 0 2006.253.08:00:00.70#ibcon#enter sib2, iclass 36, count 0 2006.253.08:00:00.70#ibcon#flushed, iclass 36, count 0 2006.253.08:00:00.70#ibcon#about to write, iclass 36, count 0 2006.253.08:00:00.70#ibcon#wrote, iclass 36, count 0 2006.253.08:00:00.70#ibcon#about to read 3, iclass 36, count 0 2006.253.08:00:00.74#ibcon#read 3, iclass 36, count 0 2006.253.08:00:00.74#ibcon#about to read 4, iclass 36, count 0 2006.253.08:00:00.74#ibcon#read 4, iclass 36, count 0 2006.253.08:00:00.74#ibcon#about to read 5, iclass 36, count 0 2006.253.08:00:00.74#ibcon#read 5, iclass 36, count 0 2006.253.08:00:00.74#ibcon#about to read 6, iclass 36, count 0 2006.253.08:00:00.74#ibcon#read 6, iclass 36, count 0 2006.253.08:00:00.74#ibcon#end of sib2, iclass 36, count 0 2006.253.08:00:00.74#ibcon#*after write, iclass 36, count 0 2006.253.08:00:00.74#ibcon#*before return 0, iclass 36, count 0 2006.253.08:00:00.74#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.253.08:00:00.74#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.253.08:00:00.74#ibcon#about to clear, iclass 36 cls_cnt 0 2006.253.08:00:00.74#ibcon#cleared, iclass 36 cls_cnt 0 2006.253.08:00:00.74$vc4f8/vb=1,4 2006.253.08:00:00.74#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.253.08:00:00.74#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.253.08:00:00.74#ibcon#ireg 11 cls_cnt 2 2006.253.08:00:00.74#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.253.08:00:00.74#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.253.08:00:00.74#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.253.08:00:00.74#ibcon#enter wrdev, iclass 38, count 2 2006.253.08:00:00.74#ibcon#first serial, iclass 38, count 2 2006.253.08:00:00.74#ibcon#enter sib2, iclass 38, count 2 2006.253.08:00:00.74#ibcon#flushed, iclass 38, count 2 2006.253.08:00:00.74#ibcon#about to write, iclass 38, count 2 2006.253.08:00:00.74#ibcon#wrote, iclass 38, count 2 2006.253.08:00:00.74#ibcon#about to read 3, iclass 38, count 2 2006.253.08:00:00.76#ibcon#read 3, iclass 38, count 2 2006.253.08:00:00.76#ibcon#about to read 4, iclass 38, count 2 2006.253.08:00:00.76#ibcon#read 4, iclass 38, count 2 2006.253.08:00:00.76#ibcon#about to read 5, iclass 38, count 2 2006.253.08:00:00.76#ibcon#read 5, iclass 38, count 2 2006.253.08:00:00.76#ibcon#about to read 6, iclass 38, count 2 2006.253.08:00:00.76#ibcon#read 6, iclass 38, count 2 2006.253.08:00:00.76#ibcon#end of sib2, iclass 38, count 2 2006.253.08:00:00.76#ibcon#*mode == 0, iclass 38, count 2 2006.253.08:00:00.76#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.253.08:00:00.76#ibcon#[27=AT01-04\r\n] 2006.253.08:00:00.76#ibcon#*before write, iclass 38, count 2 2006.253.08:00:00.76#ibcon#enter sib2, iclass 38, count 2 2006.253.08:00:00.76#ibcon#flushed, iclass 38, count 2 2006.253.08:00:00.76#ibcon#about to write, iclass 38, count 2 2006.253.08:00:00.76#ibcon#wrote, iclass 38, count 2 2006.253.08:00:00.76#ibcon#about to read 3, iclass 38, count 2 2006.253.08:00:00.79#ibcon#read 3, iclass 38, count 2 2006.253.08:00:00.79#ibcon#about to read 4, iclass 38, count 2 2006.253.08:00:00.79#ibcon#read 4, iclass 38, count 2 2006.253.08:00:00.79#ibcon#about to read 5, iclass 38, count 2 2006.253.08:00:00.79#ibcon#read 5, iclass 38, count 2 2006.253.08:00:00.79#ibcon#about to read 6, iclass 38, count 2 2006.253.08:00:00.79#ibcon#read 6, iclass 38, count 2 2006.253.08:00:00.79#ibcon#end of sib2, iclass 38, count 2 2006.253.08:00:00.79#ibcon#*after write, iclass 38, count 2 2006.253.08:00:00.79#ibcon#*before return 0, iclass 38, count 2 2006.253.08:00:00.79#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.253.08:00:00.79#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.253.08:00:00.79#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.253.08:00:00.79#ibcon#ireg 7 cls_cnt 0 2006.253.08:00:00.79#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.253.08:00:00.91#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.253.08:00:00.91#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.253.08:00:00.91#ibcon#enter wrdev, iclass 38, count 0 2006.253.08:00:00.91#ibcon#first serial, iclass 38, count 0 2006.253.08:00:00.91#ibcon#enter sib2, iclass 38, count 0 2006.253.08:00:00.91#ibcon#flushed, iclass 38, count 0 2006.253.08:00:00.91#ibcon#about to write, iclass 38, count 0 2006.253.08:00:00.91#ibcon#wrote, iclass 38, count 0 2006.253.08:00:00.91#ibcon#about to read 3, iclass 38, count 0 2006.253.08:00:00.93#ibcon#read 3, iclass 38, count 0 2006.253.08:00:00.93#ibcon#about to read 4, iclass 38, count 0 2006.253.08:00:00.93#ibcon#read 4, iclass 38, count 0 2006.253.08:00:00.93#ibcon#about to read 5, iclass 38, count 0 2006.253.08:00:00.93#ibcon#read 5, iclass 38, count 0 2006.253.08:00:00.93#ibcon#about to read 6, iclass 38, count 0 2006.253.08:00:00.93#ibcon#read 6, iclass 38, count 0 2006.253.08:00:00.93#ibcon#end of sib2, iclass 38, count 0 2006.253.08:00:00.93#ibcon#*mode == 0, iclass 38, count 0 2006.253.08:00:00.93#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.253.08:00:00.93#ibcon#[27=USB\r\n] 2006.253.08:00:00.93#ibcon#*before write, iclass 38, count 0 2006.253.08:00:00.93#ibcon#enter sib2, iclass 38, count 0 2006.253.08:00:00.93#ibcon#flushed, iclass 38, count 0 2006.253.08:00:00.93#ibcon#about to write, iclass 38, count 0 2006.253.08:00:00.93#ibcon#wrote, iclass 38, count 0 2006.253.08:00:00.93#ibcon#about to read 3, iclass 38, count 0 2006.253.08:00:00.96#ibcon#read 3, iclass 38, count 0 2006.253.08:00:00.96#ibcon#about to read 4, iclass 38, count 0 2006.253.08:00:00.96#ibcon#read 4, iclass 38, count 0 2006.253.08:00:00.96#ibcon#about to read 5, iclass 38, count 0 2006.253.08:00:00.96#ibcon#read 5, iclass 38, count 0 2006.253.08:00:00.96#ibcon#about to read 6, iclass 38, count 0 2006.253.08:00:00.96#ibcon#read 6, iclass 38, count 0 2006.253.08:00:00.96#ibcon#end of sib2, iclass 38, count 0 2006.253.08:00:00.96#ibcon#*after write, iclass 38, count 0 2006.253.08:00:00.96#ibcon#*before return 0, iclass 38, count 0 2006.253.08:00:00.96#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.253.08:00:00.96#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.253.08:00:00.96#ibcon#about to clear, iclass 38 cls_cnt 0 2006.253.08:00:00.96#ibcon#cleared, iclass 38 cls_cnt 0 2006.253.08:00:00.96$vc4f8/vblo=2,640.99 2006.253.08:00:00.96#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.253.08:00:00.96#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.253.08:00:00.96#ibcon#ireg 17 cls_cnt 0 2006.253.08:00:00.96#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.253.08:00:00.96#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.253.08:00:00.96#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.253.08:00:00.96#ibcon#enter wrdev, iclass 40, count 0 2006.253.08:00:00.96#ibcon#first serial, iclass 40, count 0 2006.253.08:00:00.96#ibcon#enter sib2, iclass 40, count 0 2006.253.08:00:00.96#ibcon#flushed, iclass 40, count 0 2006.253.08:00:00.96#ibcon#about to write, iclass 40, count 0 2006.253.08:00:00.96#ibcon#wrote, iclass 40, count 0 2006.253.08:00:00.96#ibcon#about to read 3, iclass 40, count 0 2006.253.08:00:00.98#ibcon#read 3, iclass 40, count 0 2006.253.08:00:00.98#ibcon#about to read 4, iclass 40, count 0 2006.253.08:00:00.98#ibcon#read 4, iclass 40, count 0 2006.253.08:00:00.98#ibcon#about to read 5, iclass 40, count 0 2006.253.08:00:00.98#ibcon#read 5, iclass 40, count 0 2006.253.08:00:00.98#ibcon#about to read 6, iclass 40, count 0 2006.253.08:00:00.98#ibcon#read 6, iclass 40, count 0 2006.253.08:00:00.98#ibcon#end of sib2, iclass 40, count 0 2006.253.08:00:00.98#ibcon#*mode == 0, iclass 40, count 0 2006.253.08:00:00.98#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.253.08:00:00.98#ibcon#[28=FRQ=02,640.99\r\n] 2006.253.08:00:00.98#ibcon#*before write, iclass 40, count 0 2006.253.08:00:00.98#ibcon#enter sib2, iclass 40, count 0 2006.253.08:00:00.98#ibcon#flushed, iclass 40, count 0 2006.253.08:00:00.98#ibcon#about to write, iclass 40, count 0 2006.253.08:00:00.98#ibcon#wrote, iclass 40, count 0 2006.253.08:00:00.98#ibcon#about to read 3, iclass 40, count 0 2006.253.08:00:01.02#ibcon#read 3, iclass 40, count 0 2006.253.08:00:01.02#ibcon#about to read 4, iclass 40, count 0 2006.253.08:00:01.02#ibcon#read 4, iclass 40, count 0 2006.253.08:00:01.02#ibcon#about to read 5, iclass 40, count 0 2006.253.08:00:01.02#ibcon#read 5, iclass 40, count 0 2006.253.08:00:01.02#ibcon#about to read 6, iclass 40, count 0 2006.253.08:00:01.02#ibcon#read 6, iclass 40, count 0 2006.253.08:00:01.02#ibcon#end of sib2, iclass 40, count 0 2006.253.08:00:01.02#ibcon#*after write, iclass 40, count 0 2006.253.08:00:01.02#ibcon#*before return 0, iclass 40, count 0 2006.253.08:00:01.02#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.253.08:00:01.02#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.253.08:00:01.02#ibcon#about to clear, iclass 40 cls_cnt 0 2006.253.08:00:01.02#ibcon#cleared, iclass 40 cls_cnt 0 2006.253.08:00:01.02$vc4f8/vb=2,5 2006.253.08:00:01.02#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.253.08:00:01.02#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.253.08:00:01.02#ibcon#ireg 11 cls_cnt 2 2006.253.08:00:01.02#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.253.08:00:01.08#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.253.08:00:01.08#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.253.08:00:01.08#ibcon#enter wrdev, iclass 4, count 2 2006.253.08:00:01.08#ibcon#first serial, iclass 4, count 2 2006.253.08:00:01.08#ibcon#enter sib2, iclass 4, count 2 2006.253.08:00:01.08#ibcon#flushed, iclass 4, count 2 2006.253.08:00:01.08#ibcon#about to write, iclass 4, count 2 2006.253.08:00:01.08#ibcon#wrote, iclass 4, count 2 2006.253.08:00:01.08#ibcon#about to read 3, iclass 4, count 2 2006.253.08:00:01.10#ibcon#read 3, iclass 4, count 2 2006.253.08:00:01.10#ibcon#about to read 4, iclass 4, count 2 2006.253.08:00:01.10#ibcon#read 4, iclass 4, count 2 2006.253.08:00:01.10#ibcon#about to read 5, iclass 4, count 2 2006.253.08:00:01.10#ibcon#read 5, iclass 4, count 2 2006.253.08:00:01.10#ibcon#about to read 6, iclass 4, count 2 2006.253.08:00:01.10#ibcon#read 6, iclass 4, count 2 2006.253.08:00:01.10#ibcon#end of sib2, iclass 4, count 2 2006.253.08:00:01.10#ibcon#*mode == 0, iclass 4, count 2 2006.253.08:00:01.10#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.253.08:00:01.10#ibcon#[27=AT02-05\r\n] 2006.253.08:00:01.10#ibcon#*before write, iclass 4, count 2 2006.253.08:00:01.10#ibcon#enter sib2, iclass 4, count 2 2006.253.08:00:01.10#ibcon#flushed, iclass 4, count 2 2006.253.08:00:01.10#ibcon#about to write, iclass 4, count 2 2006.253.08:00:01.10#ibcon#wrote, iclass 4, count 2 2006.253.08:00:01.10#ibcon#about to read 3, iclass 4, count 2 2006.253.08:00:01.13#ibcon#read 3, iclass 4, count 2 2006.253.08:00:01.13#ibcon#about to read 4, iclass 4, count 2 2006.253.08:00:01.13#ibcon#read 4, iclass 4, count 2 2006.253.08:00:01.13#ibcon#about to read 5, iclass 4, count 2 2006.253.08:00:01.13#ibcon#read 5, iclass 4, count 2 2006.253.08:00:01.13#ibcon#about to read 6, iclass 4, count 2 2006.253.08:00:01.13#ibcon#read 6, iclass 4, count 2 2006.253.08:00:01.13#ibcon#end of sib2, iclass 4, count 2 2006.253.08:00:01.13#ibcon#*after write, iclass 4, count 2 2006.253.08:00:01.13#ibcon#*before return 0, iclass 4, count 2 2006.253.08:00:01.13#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.253.08:00:01.13#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.253.08:00:01.13#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.253.08:00:01.13#ibcon#ireg 7 cls_cnt 0 2006.253.08:00:01.13#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.253.08:00:01.25#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.253.08:00:01.25#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.253.08:00:01.25#ibcon#enter wrdev, iclass 4, count 0 2006.253.08:00:01.25#ibcon#first serial, iclass 4, count 0 2006.253.08:00:01.25#ibcon#enter sib2, iclass 4, count 0 2006.253.08:00:01.25#ibcon#flushed, iclass 4, count 0 2006.253.08:00:01.25#ibcon#about to write, iclass 4, count 0 2006.253.08:00:01.25#ibcon#wrote, iclass 4, count 0 2006.253.08:00:01.25#ibcon#about to read 3, iclass 4, count 0 2006.253.08:00:01.27#ibcon#read 3, iclass 4, count 0 2006.253.08:00:01.27#ibcon#about to read 4, iclass 4, count 0 2006.253.08:00:01.27#ibcon#read 4, iclass 4, count 0 2006.253.08:00:01.27#ibcon#about to read 5, iclass 4, count 0 2006.253.08:00:01.27#ibcon#read 5, iclass 4, count 0 2006.253.08:00:01.27#ibcon#about to read 6, iclass 4, count 0 2006.253.08:00:01.27#ibcon#read 6, iclass 4, count 0 2006.253.08:00:01.27#ibcon#end of sib2, iclass 4, count 0 2006.253.08:00:01.27#ibcon#*mode == 0, iclass 4, count 0 2006.253.08:00:01.27#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.253.08:00:01.27#ibcon#[27=USB\r\n] 2006.253.08:00:01.27#ibcon#*before write, iclass 4, count 0 2006.253.08:00:01.27#ibcon#enter sib2, iclass 4, count 0 2006.253.08:00:01.27#ibcon#flushed, iclass 4, count 0 2006.253.08:00:01.27#ibcon#about to write, iclass 4, count 0 2006.253.08:00:01.27#ibcon#wrote, iclass 4, count 0 2006.253.08:00:01.27#ibcon#about to read 3, iclass 4, count 0 2006.253.08:00:01.30#ibcon#read 3, iclass 4, count 0 2006.253.08:00:01.30#ibcon#about to read 4, iclass 4, count 0 2006.253.08:00:01.30#ibcon#read 4, iclass 4, count 0 2006.253.08:00:01.30#ibcon#about to read 5, iclass 4, count 0 2006.253.08:00:01.30#ibcon#read 5, iclass 4, count 0 2006.253.08:00:01.30#ibcon#about to read 6, iclass 4, count 0 2006.253.08:00:01.30#ibcon#read 6, iclass 4, count 0 2006.253.08:00:01.30#ibcon#end of sib2, iclass 4, count 0 2006.253.08:00:01.30#ibcon#*after write, iclass 4, count 0 2006.253.08:00:01.30#ibcon#*before return 0, iclass 4, count 0 2006.253.08:00:01.30#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.253.08:00:01.30#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.253.08:00:01.30#ibcon#about to clear, iclass 4 cls_cnt 0 2006.253.08:00:01.30#ibcon#cleared, iclass 4 cls_cnt 0 2006.253.08:00:01.30$vc4f8/vblo=3,656.99 2006.253.08:00:01.30#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.253.08:00:01.30#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.253.08:00:01.30#ibcon#ireg 17 cls_cnt 0 2006.253.08:00:01.30#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.253.08:00:01.30#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.253.08:00:01.30#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.253.08:00:01.30#ibcon#enter wrdev, iclass 6, count 0 2006.253.08:00:01.30#ibcon#first serial, iclass 6, count 0 2006.253.08:00:01.30#ibcon#enter sib2, iclass 6, count 0 2006.253.08:00:01.30#ibcon#flushed, iclass 6, count 0 2006.253.08:00:01.30#ibcon#about to write, iclass 6, count 0 2006.253.08:00:01.30#ibcon#wrote, iclass 6, count 0 2006.253.08:00:01.30#ibcon#about to read 3, iclass 6, count 0 2006.253.08:00:01.32#ibcon#read 3, iclass 6, count 0 2006.253.08:00:01.32#ibcon#about to read 4, iclass 6, count 0 2006.253.08:00:01.32#ibcon#read 4, iclass 6, count 0 2006.253.08:00:01.32#ibcon#about to read 5, iclass 6, count 0 2006.253.08:00:01.32#ibcon#read 5, iclass 6, count 0 2006.253.08:00:01.32#ibcon#about to read 6, iclass 6, count 0 2006.253.08:00:01.32#ibcon#read 6, iclass 6, count 0 2006.253.08:00:01.32#ibcon#end of sib2, iclass 6, count 0 2006.253.08:00:01.32#ibcon#*mode == 0, iclass 6, count 0 2006.253.08:00:01.32#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.253.08:00:01.32#ibcon#[28=FRQ=03,656.99\r\n] 2006.253.08:00:01.32#ibcon#*before write, iclass 6, count 0 2006.253.08:00:01.32#ibcon#enter sib2, iclass 6, count 0 2006.253.08:00:01.32#ibcon#flushed, iclass 6, count 0 2006.253.08:00:01.32#ibcon#about to write, iclass 6, count 0 2006.253.08:00:01.32#ibcon#wrote, iclass 6, count 0 2006.253.08:00:01.32#ibcon#about to read 3, iclass 6, count 0 2006.253.08:00:01.36#ibcon#read 3, iclass 6, count 0 2006.253.08:00:01.36#ibcon#about to read 4, iclass 6, count 0 2006.253.08:00:01.36#ibcon#read 4, iclass 6, count 0 2006.253.08:00:01.36#ibcon#about to read 5, iclass 6, count 0 2006.253.08:00:01.36#ibcon#read 5, iclass 6, count 0 2006.253.08:00:01.36#ibcon#about to read 6, iclass 6, count 0 2006.253.08:00:01.36#ibcon#read 6, iclass 6, count 0 2006.253.08:00:01.36#ibcon#end of sib2, iclass 6, count 0 2006.253.08:00:01.36#ibcon#*after write, iclass 6, count 0 2006.253.08:00:01.36#ibcon#*before return 0, iclass 6, count 0 2006.253.08:00:01.36#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.253.08:00:01.36#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.253.08:00:01.36#ibcon#about to clear, iclass 6 cls_cnt 0 2006.253.08:00:01.36#ibcon#cleared, iclass 6 cls_cnt 0 2006.253.08:00:01.36$vc4f8/vb=3,4 2006.253.08:00:01.36#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.253.08:00:01.36#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.253.08:00:01.36#ibcon#ireg 11 cls_cnt 2 2006.253.08:00:01.36#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.253.08:00:01.42#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.253.08:00:01.42#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.253.08:00:01.42#ibcon#enter wrdev, iclass 10, count 2 2006.253.08:00:01.42#ibcon#first serial, iclass 10, count 2 2006.253.08:00:01.42#ibcon#enter sib2, iclass 10, count 2 2006.253.08:00:01.42#ibcon#flushed, iclass 10, count 2 2006.253.08:00:01.42#ibcon#about to write, iclass 10, count 2 2006.253.08:00:01.42#ibcon#wrote, iclass 10, count 2 2006.253.08:00:01.42#ibcon#about to read 3, iclass 10, count 2 2006.253.08:00:01.44#ibcon#read 3, iclass 10, count 2 2006.253.08:00:01.44#ibcon#about to read 4, iclass 10, count 2 2006.253.08:00:01.44#ibcon#read 4, iclass 10, count 2 2006.253.08:00:01.44#ibcon#about to read 5, iclass 10, count 2 2006.253.08:00:01.44#ibcon#read 5, iclass 10, count 2 2006.253.08:00:01.44#ibcon#about to read 6, iclass 10, count 2 2006.253.08:00:01.44#ibcon#read 6, iclass 10, count 2 2006.253.08:00:01.44#ibcon#end of sib2, iclass 10, count 2 2006.253.08:00:01.44#ibcon#*mode == 0, iclass 10, count 2 2006.253.08:00:01.44#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.253.08:00:01.44#ibcon#[27=AT03-04\r\n] 2006.253.08:00:01.44#ibcon#*before write, iclass 10, count 2 2006.253.08:00:01.44#ibcon#enter sib2, iclass 10, count 2 2006.253.08:00:01.44#ibcon#flushed, iclass 10, count 2 2006.253.08:00:01.44#ibcon#about to write, iclass 10, count 2 2006.253.08:00:01.44#ibcon#wrote, iclass 10, count 2 2006.253.08:00:01.44#ibcon#about to read 3, iclass 10, count 2 2006.253.08:00:01.47#ibcon#read 3, iclass 10, count 2 2006.253.08:00:01.47#ibcon#about to read 4, iclass 10, count 2 2006.253.08:00:01.47#ibcon#read 4, iclass 10, count 2 2006.253.08:00:01.47#ibcon#about to read 5, iclass 10, count 2 2006.253.08:00:01.47#ibcon#read 5, iclass 10, count 2 2006.253.08:00:01.47#ibcon#about to read 6, iclass 10, count 2 2006.253.08:00:01.47#ibcon#read 6, iclass 10, count 2 2006.253.08:00:01.47#ibcon#end of sib2, iclass 10, count 2 2006.253.08:00:01.47#ibcon#*after write, iclass 10, count 2 2006.253.08:00:01.47#ibcon#*before return 0, iclass 10, count 2 2006.253.08:00:01.47#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.253.08:00:01.47#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.253.08:00:01.47#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.253.08:00:01.47#ibcon#ireg 7 cls_cnt 0 2006.253.08:00:01.47#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.253.08:00:01.59#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.253.08:00:01.59#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.253.08:00:01.59#ibcon#enter wrdev, iclass 10, count 0 2006.253.08:00:01.59#ibcon#first serial, iclass 10, count 0 2006.253.08:00:01.59#ibcon#enter sib2, iclass 10, count 0 2006.253.08:00:01.59#ibcon#flushed, iclass 10, count 0 2006.253.08:00:01.59#ibcon#about to write, iclass 10, count 0 2006.253.08:00:01.59#ibcon#wrote, iclass 10, count 0 2006.253.08:00:01.59#ibcon#about to read 3, iclass 10, count 0 2006.253.08:00:01.61#ibcon#read 3, iclass 10, count 0 2006.253.08:00:01.61#ibcon#about to read 4, iclass 10, count 0 2006.253.08:00:01.61#ibcon#read 4, iclass 10, count 0 2006.253.08:00:01.61#ibcon#about to read 5, iclass 10, count 0 2006.253.08:00:01.61#ibcon#read 5, iclass 10, count 0 2006.253.08:00:01.61#ibcon#about to read 6, iclass 10, count 0 2006.253.08:00:01.61#ibcon#read 6, iclass 10, count 0 2006.253.08:00:01.61#ibcon#end of sib2, iclass 10, count 0 2006.253.08:00:01.61#ibcon#*mode == 0, iclass 10, count 0 2006.253.08:00:01.61#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.253.08:00:01.61#ibcon#[27=USB\r\n] 2006.253.08:00:01.61#ibcon#*before write, iclass 10, count 0 2006.253.08:00:01.61#ibcon#enter sib2, iclass 10, count 0 2006.253.08:00:01.61#ibcon#flushed, iclass 10, count 0 2006.253.08:00:01.61#ibcon#about to write, iclass 10, count 0 2006.253.08:00:01.61#ibcon#wrote, iclass 10, count 0 2006.253.08:00:01.61#ibcon#about to read 3, iclass 10, count 0 2006.253.08:00:01.64#ibcon#read 3, iclass 10, count 0 2006.253.08:00:01.64#ibcon#about to read 4, iclass 10, count 0 2006.253.08:00:01.64#ibcon#read 4, iclass 10, count 0 2006.253.08:00:01.64#ibcon#about to read 5, iclass 10, count 0 2006.253.08:00:01.64#ibcon#read 5, iclass 10, count 0 2006.253.08:00:01.64#ibcon#about to read 6, iclass 10, count 0 2006.253.08:00:01.64#ibcon#read 6, iclass 10, count 0 2006.253.08:00:01.64#ibcon#end of sib2, iclass 10, count 0 2006.253.08:00:01.64#ibcon#*after write, iclass 10, count 0 2006.253.08:00:01.64#ibcon#*before return 0, iclass 10, count 0 2006.253.08:00:01.64#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.253.08:00:01.64#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.253.08:00:01.64#ibcon#about to clear, iclass 10 cls_cnt 0 2006.253.08:00:01.64#ibcon#cleared, iclass 10 cls_cnt 0 2006.253.08:00:01.64$vc4f8/vblo=4,712.99 2006.253.08:00:01.64#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.253.08:00:01.64#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.253.08:00:01.64#ibcon#ireg 17 cls_cnt 0 2006.253.08:00:01.64#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.253.08:00:01.64#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.253.08:00:01.64#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.253.08:00:01.64#ibcon#enter wrdev, iclass 12, count 0 2006.253.08:00:01.64#ibcon#first serial, iclass 12, count 0 2006.253.08:00:01.64#ibcon#enter sib2, iclass 12, count 0 2006.253.08:00:01.64#ibcon#flushed, iclass 12, count 0 2006.253.08:00:01.64#ibcon#about to write, iclass 12, count 0 2006.253.08:00:01.64#ibcon#wrote, iclass 12, count 0 2006.253.08:00:01.64#ibcon#about to read 3, iclass 12, count 0 2006.253.08:00:01.66#ibcon#read 3, iclass 12, count 0 2006.253.08:00:01.66#ibcon#about to read 4, iclass 12, count 0 2006.253.08:00:01.66#ibcon#read 4, iclass 12, count 0 2006.253.08:00:01.66#ibcon#about to read 5, iclass 12, count 0 2006.253.08:00:01.66#ibcon#read 5, iclass 12, count 0 2006.253.08:00:01.66#ibcon#about to read 6, iclass 12, count 0 2006.253.08:00:01.66#ibcon#read 6, iclass 12, count 0 2006.253.08:00:01.66#ibcon#end of sib2, iclass 12, count 0 2006.253.08:00:01.66#ibcon#*mode == 0, iclass 12, count 0 2006.253.08:00:01.66#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.253.08:00:01.66#ibcon#[28=FRQ=04,712.99\r\n] 2006.253.08:00:01.66#ibcon#*before write, iclass 12, count 0 2006.253.08:00:01.66#ibcon#enter sib2, iclass 12, count 0 2006.253.08:00:01.66#ibcon#flushed, iclass 12, count 0 2006.253.08:00:01.66#ibcon#about to write, iclass 12, count 0 2006.253.08:00:01.66#ibcon#wrote, iclass 12, count 0 2006.253.08:00:01.66#ibcon#about to read 3, iclass 12, count 0 2006.253.08:00:01.70#ibcon#read 3, iclass 12, count 0 2006.253.08:00:01.70#ibcon#about to read 4, iclass 12, count 0 2006.253.08:00:01.70#ibcon#read 4, iclass 12, count 0 2006.253.08:00:01.70#ibcon#about to read 5, iclass 12, count 0 2006.253.08:00:01.70#ibcon#read 5, iclass 12, count 0 2006.253.08:00:01.70#ibcon#about to read 6, iclass 12, count 0 2006.253.08:00:01.70#ibcon#read 6, iclass 12, count 0 2006.253.08:00:01.70#ibcon#end of sib2, iclass 12, count 0 2006.253.08:00:01.70#ibcon#*after write, iclass 12, count 0 2006.253.08:00:01.70#ibcon#*before return 0, iclass 12, count 0 2006.253.08:00:01.70#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.253.08:00:01.70#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.253.08:00:01.70#ibcon#about to clear, iclass 12 cls_cnt 0 2006.253.08:00:01.70#ibcon#cleared, iclass 12 cls_cnt 0 2006.253.08:00:01.70$vc4f8/vb=4,4 2006.253.08:00:01.70#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.253.08:00:01.70#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.253.08:00:01.70#ibcon#ireg 11 cls_cnt 2 2006.253.08:00:01.70#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.253.08:00:01.76#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.253.08:00:01.76#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.253.08:00:01.76#ibcon#enter wrdev, iclass 14, count 2 2006.253.08:00:01.76#ibcon#first serial, iclass 14, count 2 2006.253.08:00:01.76#ibcon#enter sib2, iclass 14, count 2 2006.253.08:00:01.76#ibcon#flushed, iclass 14, count 2 2006.253.08:00:01.76#ibcon#about to write, iclass 14, count 2 2006.253.08:00:01.76#ibcon#wrote, iclass 14, count 2 2006.253.08:00:01.76#ibcon#about to read 3, iclass 14, count 2 2006.253.08:00:01.78#ibcon#read 3, iclass 14, count 2 2006.253.08:00:01.78#ibcon#about to read 4, iclass 14, count 2 2006.253.08:00:01.78#ibcon#read 4, iclass 14, count 2 2006.253.08:00:01.78#ibcon#about to read 5, iclass 14, count 2 2006.253.08:00:01.78#ibcon#read 5, iclass 14, count 2 2006.253.08:00:01.78#ibcon#about to read 6, iclass 14, count 2 2006.253.08:00:01.78#ibcon#read 6, iclass 14, count 2 2006.253.08:00:01.78#ibcon#end of sib2, iclass 14, count 2 2006.253.08:00:01.78#ibcon#*mode == 0, iclass 14, count 2 2006.253.08:00:01.78#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.253.08:00:01.78#ibcon#[27=AT04-04\r\n] 2006.253.08:00:01.78#ibcon#*before write, iclass 14, count 2 2006.253.08:00:01.78#ibcon#enter sib2, iclass 14, count 2 2006.253.08:00:01.78#ibcon#flushed, iclass 14, count 2 2006.253.08:00:01.78#ibcon#about to write, iclass 14, count 2 2006.253.08:00:01.78#ibcon#wrote, iclass 14, count 2 2006.253.08:00:01.78#ibcon#about to read 3, iclass 14, count 2 2006.253.08:00:01.81#ibcon#read 3, iclass 14, count 2 2006.253.08:00:01.81#ibcon#about to read 4, iclass 14, count 2 2006.253.08:00:01.81#ibcon#read 4, iclass 14, count 2 2006.253.08:00:01.81#ibcon#about to read 5, iclass 14, count 2 2006.253.08:00:01.81#ibcon#read 5, iclass 14, count 2 2006.253.08:00:01.81#ibcon#about to read 6, iclass 14, count 2 2006.253.08:00:01.81#ibcon#read 6, iclass 14, count 2 2006.253.08:00:01.81#ibcon#end of sib2, iclass 14, count 2 2006.253.08:00:01.81#ibcon#*after write, iclass 14, count 2 2006.253.08:00:01.81#ibcon#*before return 0, iclass 14, count 2 2006.253.08:00:01.81#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.253.08:00:01.81#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.253.08:00:01.81#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.253.08:00:01.81#ibcon#ireg 7 cls_cnt 0 2006.253.08:00:01.81#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.253.08:00:01.93#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.253.08:00:01.93#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.253.08:00:01.93#ibcon#enter wrdev, iclass 14, count 0 2006.253.08:00:01.93#ibcon#first serial, iclass 14, count 0 2006.253.08:00:01.93#ibcon#enter sib2, iclass 14, count 0 2006.253.08:00:01.93#ibcon#flushed, iclass 14, count 0 2006.253.08:00:01.93#ibcon#about to write, iclass 14, count 0 2006.253.08:00:01.93#ibcon#wrote, iclass 14, count 0 2006.253.08:00:01.93#ibcon#about to read 3, iclass 14, count 0 2006.253.08:00:01.95#ibcon#read 3, iclass 14, count 0 2006.253.08:00:01.95#ibcon#about to read 4, iclass 14, count 0 2006.253.08:00:01.95#ibcon#read 4, iclass 14, count 0 2006.253.08:00:01.95#ibcon#about to read 5, iclass 14, count 0 2006.253.08:00:01.95#ibcon#read 5, iclass 14, count 0 2006.253.08:00:01.95#ibcon#about to read 6, iclass 14, count 0 2006.253.08:00:01.95#ibcon#read 6, iclass 14, count 0 2006.253.08:00:01.95#ibcon#end of sib2, iclass 14, count 0 2006.253.08:00:01.95#ibcon#*mode == 0, iclass 14, count 0 2006.253.08:00:01.95#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.253.08:00:01.95#ibcon#[27=USB\r\n] 2006.253.08:00:01.95#ibcon#*before write, iclass 14, count 0 2006.253.08:00:01.95#ibcon#enter sib2, iclass 14, count 0 2006.253.08:00:01.95#ibcon#flushed, iclass 14, count 0 2006.253.08:00:01.95#ibcon#about to write, iclass 14, count 0 2006.253.08:00:01.95#ibcon#wrote, iclass 14, count 0 2006.253.08:00:01.95#ibcon#about to read 3, iclass 14, count 0 2006.253.08:00:01.98#ibcon#read 3, iclass 14, count 0 2006.253.08:00:01.98#ibcon#about to read 4, iclass 14, count 0 2006.253.08:00:01.98#ibcon#read 4, iclass 14, count 0 2006.253.08:00:01.98#ibcon#about to read 5, iclass 14, count 0 2006.253.08:00:01.98#ibcon#read 5, iclass 14, count 0 2006.253.08:00:01.98#ibcon#about to read 6, iclass 14, count 0 2006.253.08:00:01.98#ibcon#read 6, iclass 14, count 0 2006.253.08:00:01.98#ibcon#end of sib2, iclass 14, count 0 2006.253.08:00:01.98#ibcon#*after write, iclass 14, count 0 2006.253.08:00:01.98#ibcon#*before return 0, iclass 14, count 0 2006.253.08:00:01.98#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.253.08:00:01.98#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.253.08:00:01.98#ibcon#about to clear, iclass 14 cls_cnt 0 2006.253.08:00:01.98#ibcon#cleared, iclass 14 cls_cnt 0 2006.253.08:00:01.98$vc4f8/vblo=5,744.99 2006.253.08:00:01.98#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.253.08:00:01.98#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.253.08:00:01.98#ibcon#ireg 17 cls_cnt 0 2006.253.08:00:01.98#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.253.08:00:01.98#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.253.08:00:01.98#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.253.08:00:01.98#ibcon#enter wrdev, iclass 16, count 0 2006.253.08:00:01.98#ibcon#first serial, iclass 16, count 0 2006.253.08:00:01.98#ibcon#enter sib2, iclass 16, count 0 2006.253.08:00:01.98#ibcon#flushed, iclass 16, count 0 2006.253.08:00:01.98#ibcon#about to write, iclass 16, count 0 2006.253.08:00:01.98#ibcon#wrote, iclass 16, count 0 2006.253.08:00:01.98#ibcon#about to read 3, iclass 16, count 0 2006.253.08:00:02.00#ibcon#read 3, iclass 16, count 0 2006.253.08:00:02.00#ibcon#about to read 4, iclass 16, count 0 2006.253.08:00:02.00#ibcon#read 4, iclass 16, count 0 2006.253.08:00:02.00#ibcon#about to read 5, iclass 16, count 0 2006.253.08:00:02.00#ibcon#read 5, iclass 16, count 0 2006.253.08:00:02.00#ibcon#about to read 6, iclass 16, count 0 2006.253.08:00:02.00#ibcon#read 6, iclass 16, count 0 2006.253.08:00:02.00#ibcon#end of sib2, iclass 16, count 0 2006.253.08:00:02.00#ibcon#*mode == 0, iclass 16, count 0 2006.253.08:00:02.00#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.253.08:00:02.00#ibcon#[28=FRQ=05,744.99\r\n] 2006.253.08:00:02.00#ibcon#*before write, iclass 16, count 0 2006.253.08:00:02.00#ibcon#enter sib2, iclass 16, count 0 2006.253.08:00:02.00#ibcon#flushed, iclass 16, count 0 2006.253.08:00:02.00#ibcon#about to write, iclass 16, count 0 2006.253.08:00:02.00#ibcon#wrote, iclass 16, count 0 2006.253.08:00:02.00#ibcon#about to read 3, iclass 16, count 0 2006.253.08:00:02.04#ibcon#read 3, iclass 16, count 0 2006.253.08:00:02.04#ibcon#about to read 4, iclass 16, count 0 2006.253.08:00:02.04#ibcon#read 4, iclass 16, count 0 2006.253.08:00:02.04#ibcon#about to read 5, iclass 16, count 0 2006.253.08:00:02.04#ibcon#read 5, iclass 16, count 0 2006.253.08:00:02.04#ibcon#about to read 6, iclass 16, count 0 2006.253.08:00:02.04#ibcon#read 6, iclass 16, count 0 2006.253.08:00:02.04#ibcon#end of sib2, iclass 16, count 0 2006.253.08:00:02.04#ibcon#*after write, iclass 16, count 0 2006.253.08:00:02.04#ibcon#*before return 0, iclass 16, count 0 2006.253.08:00:02.04#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.253.08:00:02.04#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.253.08:00:02.04#ibcon#about to clear, iclass 16 cls_cnt 0 2006.253.08:00:02.04#ibcon#cleared, iclass 16 cls_cnt 0 2006.253.08:00:02.04$vc4f8/vb=5,4 2006.253.08:00:02.04#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.253.08:00:02.04#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.253.08:00:02.04#ibcon#ireg 11 cls_cnt 2 2006.253.08:00:02.04#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.253.08:00:02.10#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.253.08:00:02.10#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.253.08:00:02.10#ibcon#enter wrdev, iclass 18, count 2 2006.253.08:00:02.10#ibcon#first serial, iclass 18, count 2 2006.253.08:00:02.10#ibcon#enter sib2, iclass 18, count 2 2006.253.08:00:02.10#ibcon#flushed, iclass 18, count 2 2006.253.08:00:02.10#ibcon#about to write, iclass 18, count 2 2006.253.08:00:02.10#ibcon#wrote, iclass 18, count 2 2006.253.08:00:02.10#ibcon#about to read 3, iclass 18, count 2 2006.253.08:00:02.12#ibcon#read 3, iclass 18, count 2 2006.253.08:00:02.12#ibcon#about to read 4, iclass 18, count 2 2006.253.08:00:02.12#ibcon#read 4, iclass 18, count 2 2006.253.08:00:02.12#ibcon#about to read 5, iclass 18, count 2 2006.253.08:00:02.12#ibcon#read 5, iclass 18, count 2 2006.253.08:00:02.12#ibcon#about to read 6, iclass 18, count 2 2006.253.08:00:02.12#ibcon#read 6, iclass 18, count 2 2006.253.08:00:02.12#ibcon#end of sib2, iclass 18, count 2 2006.253.08:00:02.12#ibcon#*mode == 0, iclass 18, count 2 2006.253.08:00:02.12#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.253.08:00:02.12#ibcon#[27=AT05-04\r\n] 2006.253.08:00:02.12#ibcon#*before write, iclass 18, count 2 2006.253.08:00:02.12#ibcon#enter sib2, iclass 18, count 2 2006.253.08:00:02.12#ibcon#flushed, iclass 18, count 2 2006.253.08:00:02.12#ibcon#about to write, iclass 18, count 2 2006.253.08:00:02.12#ibcon#wrote, iclass 18, count 2 2006.253.08:00:02.12#ibcon#about to read 3, iclass 18, count 2 2006.253.08:00:02.15#ibcon#read 3, iclass 18, count 2 2006.253.08:00:02.15#ibcon#about to read 4, iclass 18, count 2 2006.253.08:00:02.15#ibcon#read 4, iclass 18, count 2 2006.253.08:00:02.15#ibcon#about to read 5, iclass 18, count 2 2006.253.08:00:02.15#ibcon#read 5, iclass 18, count 2 2006.253.08:00:02.15#ibcon#about to read 6, iclass 18, count 2 2006.253.08:00:02.15#ibcon#read 6, iclass 18, count 2 2006.253.08:00:02.15#ibcon#end of sib2, iclass 18, count 2 2006.253.08:00:02.15#ibcon#*after write, iclass 18, count 2 2006.253.08:00:02.15#ibcon#*before return 0, iclass 18, count 2 2006.253.08:00:02.15#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.253.08:00:02.15#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.253.08:00:02.15#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.253.08:00:02.15#ibcon#ireg 7 cls_cnt 0 2006.253.08:00:02.15#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.253.08:00:02.27#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.253.08:00:02.27#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.253.08:00:02.27#ibcon#enter wrdev, iclass 18, count 0 2006.253.08:00:02.27#ibcon#first serial, iclass 18, count 0 2006.253.08:00:02.27#ibcon#enter sib2, iclass 18, count 0 2006.253.08:00:02.27#ibcon#flushed, iclass 18, count 0 2006.253.08:00:02.27#ibcon#about to write, iclass 18, count 0 2006.253.08:00:02.27#ibcon#wrote, iclass 18, count 0 2006.253.08:00:02.27#ibcon#about to read 3, iclass 18, count 0 2006.253.08:00:02.29#ibcon#read 3, iclass 18, count 0 2006.253.08:00:02.29#ibcon#about to read 4, iclass 18, count 0 2006.253.08:00:02.29#ibcon#read 4, iclass 18, count 0 2006.253.08:00:02.29#ibcon#about to read 5, iclass 18, count 0 2006.253.08:00:02.29#ibcon#read 5, iclass 18, count 0 2006.253.08:00:02.29#ibcon#about to read 6, iclass 18, count 0 2006.253.08:00:02.29#ibcon#read 6, iclass 18, count 0 2006.253.08:00:02.29#ibcon#end of sib2, iclass 18, count 0 2006.253.08:00:02.29#ibcon#*mode == 0, iclass 18, count 0 2006.253.08:00:02.29#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.253.08:00:02.29#ibcon#[27=USB\r\n] 2006.253.08:00:02.29#ibcon#*before write, iclass 18, count 0 2006.253.08:00:02.29#ibcon#enter sib2, iclass 18, count 0 2006.253.08:00:02.29#ibcon#flushed, iclass 18, count 0 2006.253.08:00:02.29#ibcon#about to write, iclass 18, count 0 2006.253.08:00:02.29#ibcon#wrote, iclass 18, count 0 2006.253.08:00:02.29#ibcon#about to read 3, iclass 18, count 0 2006.253.08:00:02.32#ibcon#read 3, iclass 18, count 0 2006.253.08:00:02.32#ibcon#about to read 4, iclass 18, count 0 2006.253.08:00:02.32#ibcon#read 4, iclass 18, count 0 2006.253.08:00:02.32#ibcon#about to read 5, iclass 18, count 0 2006.253.08:00:02.32#ibcon#read 5, iclass 18, count 0 2006.253.08:00:02.32#ibcon#about to read 6, iclass 18, count 0 2006.253.08:00:02.32#ibcon#read 6, iclass 18, count 0 2006.253.08:00:02.32#ibcon#end of sib2, iclass 18, count 0 2006.253.08:00:02.32#ibcon#*after write, iclass 18, count 0 2006.253.08:00:02.32#ibcon#*before return 0, iclass 18, count 0 2006.253.08:00:02.32#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.253.08:00:02.32#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.253.08:00:02.32#ibcon#about to clear, iclass 18 cls_cnt 0 2006.253.08:00:02.32#ibcon#cleared, iclass 18 cls_cnt 0 2006.253.08:00:02.32$vc4f8/vblo=6,752.99 2006.253.08:00:02.32#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.253.08:00:02.32#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.253.08:00:02.32#ibcon#ireg 17 cls_cnt 0 2006.253.08:00:02.32#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.253.08:00:02.32#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.253.08:00:02.32#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.253.08:00:02.32#ibcon#enter wrdev, iclass 20, count 0 2006.253.08:00:02.32#ibcon#first serial, iclass 20, count 0 2006.253.08:00:02.32#ibcon#enter sib2, iclass 20, count 0 2006.253.08:00:02.32#ibcon#flushed, iclass 20, count 0 2006.253.08:00:02.32#ibcon#about to write, iclass 20, count 0 2006.253.08:00:02.32#ibcon#wrote, iclass 20, count 0 2006.253.08:00:02.32#ibcon#about to read 3, iclass 20, count 0 2006.253.08:00:02.35#ibcon#read 3, iclass 20, count 0 2006.253.08:00:02.35#ibcon#about to read 4, iclass 20, count 0 2006.253.08:00:02.35#ibcon#read 4, iclass 20, count 0 2006.253.08:00:02.35#ibcon#about to read 5, iclass 20, count 0 2006.253.08:00:02.35#ibcon#read 5, iclass 20, count 0 2006.253.08:00:02.35#ibcon#about to read 6, iclass 20, count 0 2006.253.08:00:02.35#ibcon#read 6, iclass 20, count 0 2006.253.08:00:02.35#ibcon#end of sib2, iclass 20, count 0 2006.253.08:00:02.35#ibcon#*mode == 0, iclass 20, count 0 2006.253.08:00:02.35#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.253.08:00:02.35#ibcon#[28=FRQ=06,752.99\r\n] 2006.253.08:00:02.35#ibcon#*before write, iclass 20, count 0 2006.253.08:00:02.35#ibcon#enter sib2, iclass 20, count 0 2006.253.08:00:02.35#ibcon#flushed, iclass 20, count 0 2006.253.08:00:02.35#ibcon#about to write, iclass 20, count 0 2006.253.08:00:02.35#ibcon#wrote, iclass 20, count 0 2006.253.08:00:02.35#ibcon#about to read 3, iclass 20, count 0 2006.253.08:00:02.39#ibcon#read 3, iclass 20, count 0 2006.253.08:00:02.39#ibcon#about to read 4, iclass 20, count 0 2006.253.08:00:02.39#ibcon#read 4, iclass 20, count 0 2006.253.08:00:02.39#ibcon#about to read 5, iclass 20, count 0 2006.253.08:00:02.39#ibcon#read 5, iclass 20, count 0 2006.253.08:00:02.39#ibcon#about to read 6, iclass 20, count 0 2006.253.08:00:02.39#ibcon#read 6, iclass 20, count 0 2006.253.08:00:02.39#ibcon#end of sib2, iclass 20, count 0 2006.253.08:00:02.39#ibcon#*after write, iclass 20, count 0 2006.253.08:00:02.39#ibcon#*before return 0, iclass 20, count 0 2006.253.08:00:02.39#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.253.08:00:02.39#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.253.08:00:02.39#ibcon#about to clear, iclass 20 cls_cnt 0 2006.253.08:00:02.39#ibcon#cleared, iclass 20 cls_cnt 0 2006.253.08:00:02.39$vc4f8/vb=6,4 2006.253.08:00:02.39#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.253.08:00:02.39#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.253.08:00:02.39#ibcon#ireg 11 cls_cnt 2 2006.253.08:00:02.39#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.253.08:00:02.44#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.253.08:00:02.44#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.253.08:00:02.44#ibcon#enter wrdev, iclass 22, count 2 2006.253.08:00:02.44#ibcon#first serial, iclass 22, count 2 2006.253.08:00:02.44#ibcon#enter sib2, iclass 22, count 2 2006.253.08:00:02.44#ibcon#flushed, iclass 22, count 2 2006.253.08:00:02.44#ibcon#about to write, iclass 22, count 2 2006.253.08:00:02.44#ibcon#wrote, iclass 22, count 2 2006.253.08:00:02.44#ibcon#about to read 3, iclass 22, count 2 2006.253.08:00:02.46#ibcon#read 3, iclass 22, count 2 2006.253.08:00:02.46#ibcon#about to read 4, iclass 22, count 2 2006.253.08:00:02.46#ibcon#read 4, iclass 22, count 2 2006.253.08:00:02.46#ibcon#about to read 5, iclass 22, count 2 2006.253.08:00:02.46#ibcon#read 5, iclass 22, count 2 2006.253.08:00:02.46#ibcon#about to read 6, iclass 22, count 2 2006.253.08:00:02.46#ibcon#read 6, iclass 22, count 2 2006.253.08:00:02.46#ibcon#end of sib2, iclass 22, count 2 2006.253.08:00:02.46#ibcon#*mode == 0, iclass 22, count 2 2006.253.08:00:02.46#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.253.08:00:02.46#ibcon#[27=AT06-04\r\n] 2006.253.08:00:02.46#ibcon#*before write, iclass 22, count 2 2006.253.08:00:02.46#ibcon#enter sib2, iclass 22, count 2 2006.253.08:00:02.46#ibcon#flushed, iclass 22, count 2 2006.253.08:00:02.46#ibcon#about to write, iclass 22, count 2 2006.253.08:00:02.46#ibcon#wrote, iclass 22, count 2 2006.253.08:00:02.46#ibcon#about to read 3, iclass 22, count 2 2006.253.08:00:02.49#ibcon#read 3, iclass 22, count 2 2006.253.08:00:02.49#ibcon#about to read 4, iclass 22, count 2 2006.253.08:00:02.49#ibcon#read 4, iclass 22, count 2 2006.253.08:00:02.49#ibcon#about to read 5, iclass 22, count 2 2006.253.08:00:02.49#ibcon#read 5, iclass 22, count 2 2006.253.08:00:02.49#ibcon#about to read 6, iclass 22, count 2 2006.253.08:00:02.49#ibcon#read 6, iclass 22, count 2 2006.253.08:00:02.49#ibcon#end of sib2, iclass 22, count 2 2006.253.08:00:02.49#ibcon#*after write, iclass 22, count 2 2006.253.08:00:02.49#ibcon#*before return 0, iclass 22, count 2 2006.253.08:00:02.49#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.253.08:00:02.49#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.253.08:00:02.49#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.253.08:00:02.49#ibcon#ireg 7 cls_cnt 0 2006.253.08:00:02.49#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.253.08:00:02.61#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.253.08:00:02.61#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.253.08:00:02.61#ibcon#enter wrdev, iclass 22, count 0 2006.253.08:00:02.61#ibcon#first serial, iclass 22, count 0 2006.253.08:00:02.61#ibcon#enter sib2, iclass 22, count 0 2006.253.08:00:02.61#ibcon#flushed, iclass 22, count 0 2006.253.08:00:02.61#ibcon#about to write, iclass 22, count 0 2006.253.08:00:02.61#ibcon#wrote, iclass 22, count 0 2006.253.08:00:02.61#ibcon#about to read 3, iclass 22, count 0 2006.253.08:00:02.63#ibcon#read 3, iclass 22, count 0 2006.253.08:00:02.63#ibcon#about to read 4, iclass 22, count 0 2006.253.08:00:02.63#ibcon#read 4, iclass 22, count 0 2006.253.08:00:02.63#ibcon#about to read 5, iclass 22, count 0 2006.253.08:00:02.63#ibcon#read 5, iclass 22, count 0 2006.253.08:00:02.63#ibcon#about to read 6, iclass 22, count 0 2006.253.08:00:02.63#ibcon#read 6, iclass 22, count 0 2006.253.08:00:02.63#ibcon#end of sib2, iclass 22, count 0 2006.253.08:00:02.63#ibcon#*mode == 0, iclass 22, count 0 2006.253.08:00:02.63#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.253.08:00:02.63#ibcon#[27=USB\r\n] 2006.253.08:00:02.63#ibcon#*before write, iclass 22, count 0 2006.253.08:00:02.63#ibcon#enter sib2, iclass 22, count 0 2006.253.08:00:02.63#ibcon#flushed, iclass 22, count 0 2006.253.08:00:02.63#ibcon#about to write, iclass 22, count 0 2006.253.08:00:02.63#ibcon#wrote, iclass 22, count 0 2006.253.08:00:02.63#ibcon#about to read 3, iclass 22, count 0 2006.253.08:00:02.66#ibcon#read 3, iclass 22, count 0 2006.253.08:00:02.66#ibcon#about to read 4, iclass 22, count 0 2006.253.08:00:02.66#ibcon#read 4, iclass 22, count 0 2006.253.08:00:02.66#ibcon#about to read 5, iclass 22, count 0 2006.253.08:00:02.66#ibcon#read 5, iclass 22, count 0 2006.253.08:00:02.66#ibcon#about to read 6, iclass 22, count 0 2006.253.08:00:02.66#ibcon#read 6, iclass 22, count 0 2006.253.08:00:02.66#ibcon#end of sib2, iclass 22, count 0 2006.253.08:00:02.66#ibcon#*after write, iclass 22, count 0 2006.253.08:00:02.66#ibcon#*before return 0, iclass 22, count 0 2006.253.08:00:02.66#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.253.08:00:02.66#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.253.08:00:02.66#ibcon#about to clear, iclass 22 cls_cnt 0 2006.253.08:00:02.66#ibcon#cleared, iclass 22 cls_cnt 0 2006.253.08:00:02.66$vc4f8/vabw=wide 2006.253.08:00:02.66#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.253.08:00:02.66#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.253.08:00:02.66#ibcon#ireg 8 cls_cnt 0 2006.253.08:00:02.66#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.253.08:00:02.66#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.253.08:00:02.66#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.253.08:00:02.66#ibcon#enter wrdev, iclass 24, count 0 2006.253.08:00:02.66#ibcon#first serial, iclass 24, count 0 2006.253.08:00:02.66#ibcon#enter sib2, iclass 24, count 0 2006.253.08:00:02.66#ibcon#flushed, iclass 24, count 0 2006.253.08:00:02.66#ibcon#about to write, iclass 24, count 0 2006.253.08:00:02.66#ibcon#wrote, iclass 24, count 0 2006.253.08:00:02.66#ibcon#about to read 3, iclass 24, count 0 2006.253.08:00:02.68#ibcon#read 3, iclass 24, count 0 2006.253.08:00:02.68#ibcon#about to read 4, iclass 24, count 0 2006.253.08:00:02.68#ibcon#read 4, iclass 24, count 0 2006.253.08:00:02.68#ibcon#about to read 5, iclass 24, count 0 2006.253.08:00:02.68#ibcon#read 5, iclass 24, count 0 2006.253.08:00:02.68#ibcon#about to read 6, iclass 24, count 0 2006.253.08:00:02.68#ibcon#read 6, iclass 24, count 0 2006.253.08:00:02.68#ibcon#end of sib2, iclass 24, count 0 2006.253.08:00:02.68#ibcon#*mode == 0, iclass 24, count 0 2006.253.08:00:02.68#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.253.08:00:02.68#ibcon#[25=BW32\r\n] 2006.253.08:00:02.68#ibcon#*before write, iclass 24, count 0 2006.253.08:00:02.68#ibcon#enter sib2, iclass 24, count 0 2006.253.08:00:02.68#ibcon#flushed, iclass 24, count 0 2006.253.08:00:02.68#ibcon#about to write, iclass 24, count 0 2006.253.08:00:02.68#ibcon#wrote, iclass 24, count 0 2006.253.08:00:02.68#ibcon#about to read 3, iclass 24, count 0 2006.253.08:00:02.71#ibcon#read 3, iclass 24, count 0 2006.253.08:00:02.71#ibcon#about to read 4, iclass 24, count 0 2006.253.08:00:02.71#ibcon#read 4, iclass 24, count 0 2006.253.08:00:02.71#ibcon#about to read 5, iclass 24, count 0 2006.253.08:00:02.71#ibcon#read 5, iclass 24, count 0 2006.253.08:00:02.71#ibcon#about to read 6, iclass 24, count 0 2006.253.08:00:02.71#ibcon#read 6, iclass 24, count 0 2006.253.08:00:02.71#ibcon#end of sib2, iclass 24, count 0 2006.253.08:00:02.71#ibcon#*after write, iclass 24, count 0 2006.253.08:00:02.71#ibcon#*before return 0, iclass 24, count 0 2006.253.08:00:02.71#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.253.08:00:02.71#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.253.08:00:02.71#ibcon#about to clear, iclass 24 cls_cnt 0 2006.253.08:00:02.71#ibcon#cleared, iclass 24 cls_cnt 0 2006.253.08:00:02.71$vc4f8/vbbw=wide 2006.253.08:00:02.71#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.253.08:00:02.71#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.253.08:00:02.71#ibcon#ireg 8 cls_cnt 0 2006.253.08:00:02.71#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.253.08:00:02.78#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.253.08:00:02.78#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.253.08:00:02.78#ibcon#enter wrdev, iclass 26, count 0 2006.253.08:00:02.78#ibcon#first serial, iclass 26, count 0 2006.253.08:00:02.78#ibcon#enter sib2, iclass 26, count 0 2006.253.08:00:02.78#ibcon#flushed, iclass 26, count 0 2006.253.08:00:02.78#ibcon#about to write, iclass 26, count 0 2006.253.08:00:02.78#ibcon#wrote, iclass 26, count 0 2006.253.08:00:02.78#ibcon#about to read 3, iclass 26, count 0 2006.253.08:00:02.80#ibcon#read 3, iclass 26, count 0 2006.253.08:00:02.80#ibcon#about to read 4, iclass 26, count 0 2006.253.08:00:02.80#ibcon#read 4, iclass 26, count 0 2006.253.08:00:02.80#ibcon#about to read 5, iclass 26, count 0 2006.253.08:00:02.80#ibcon#read 5, iclass 26, count 0 2006.253.08:00:02.80#ibcon#about to read 6, iclass 26, count 0 2006.253.08:00:02.80#ibcon#read 6, iclass 26, count 0 2006.253.08:00:02.80#ibcon#end of sib2, iclass 26, count 0 2006.253.08:00:02.80#ibcon#*mode == 0, iclass 26, count 0 2006.253.08:00:02.80#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.253.08:00:02.80#ibcon#[27=BW32\r\n] 2006.253.08:00:02.80#ibcon#*before write, iclass 26, count 0 2006.253.08:00:02.80#ibcon#enter sib2, iclass 26, count 0 2006.253.08:00:02.80#ibcon#flushed, iclass 26, count 0 2006.253.08:00:02.80#ibcon#about to write, iclass 26, count 0 2006.253.08:00:02.80#ibcon#wrote, iclass 26, count 0 2006.253.08:00:02.80#ibcon#about to read 3, iclass 26, count 0 2006.253.08:00:02.83#ibcon#read 3, iclass 26, count 0 2006.253.08:00:02.83#ibcon#about to read 4, iclass 26, count 0 2006.253.08:00:02.83#ibcon#read 4, iclass 26, count 0 2006.253.08:00:02.83#ibcon#about to read 5, iclass 26, count 0 2006.253.08:00:02.83#ibcon#read 5, iclass 26, count 0 2006.253.08:00:02.83#ibcon#about to read 6, iclass 26, count 0 2006.253.08:00:02.83#ibcon#read 6, iclass 26, count 0 2006.253.08:00:02.83#ibcon#end of sib2, iclass 26, count 0 2006.253.08:00:02.83#ibcon#*after write, iclass 26, count 0 2006.253.08:00:02.83#ibcon#*before return 0, iclass 26, count 0 2006.253.08:00:02.83#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.253.08:00:02.83#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.253.08:00:02.83#ibcon#about to clear, iclass 26 cls_cnt 0 2006.253.08:00:02.83#ibcon#cleared, iclass 26 cls_cnt 0 2006.253.08:00:02.83$4f8m12a/ifd4f 2006.253.08:00:02.83$ifd4f/lo= 2006.253.08:00:02.83$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.253.08:00:02.83$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.253.08:00:02.83$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.253.08:00:02.83$ifd4f/patch= 2006.253.08:00:02.83$ifd4f/patch=lo1,a1,a2,a3,a4 2006.253.08:00:02.83$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.253.08:00:02.83$ifd4f/patch=lo3,a5,a6,a7,a8 2006.253.08:00:02.83$4f8m12a/"form=m,16.000,1:2 2006.253.08:00:02.83$4f8m12a/"tpicd 2006.253.08:00:02.83$4f8m12a/echo=off 2006.253.08:00:02.83$4f8m12a/xlog=off 2006.253.08:00:02.83:!2006.253.08:00:40 2006.253.08:00:22.14#trakl#Source acquired 2006.253.08:00:24.14#flagr#flagr/antenna,acquired 2006.253.08:00:40.00:preob 2006.253.08:00:40.14/onsource/TRACKING 2006.253.08:00:40.14:!2006.253.08:00:50 2006.253.08:00:50.00:data_valid=on 2006.253.08:00:50.00:midob 2006.253.08:00:51.14/onsource/TRACKING 2006.253.08:00:51.14/wx/31.10,1006.3,73 2006.253.08:00:51.35/cable/+6.3695E-03 2006.253.08:00:52.44/va/01,08,usb,yes,31,33 2006.253.08:00:52.44/va/02,07,usb,yes,31,32 2006.253.08:00:52.44/va/03,06,usb,yes,33,33 2006.253.08:00:52.44/va/04,07,usb,yes,32,35 2006.253.08:00:52.44/va/05,07,usb,yes,34,35 2006.253.08:00:52.44/va/06,07,usb,yes,29,29 2006.253.08:00:52.44/va/07,07,usb,yes,29,29 2006.253.08:00:52.44/va/08,07,usb,yes,32,31 2006.253.08:00:52.67/valo/01,532.99,yes,locked 2006.253.08:00:52.67/valo/02,572.99,yes,locked 2006.253.08:00:52.67/valo/03,672.99,yes,locked 2006.253.08:00:52.67/valo/04,832.99,yes,locked 2006.253.08:00:52.67/valo/05,652.99,yes,locked 2006.253.08:00:52.67/valo/06,772.99,yes,locked 2006.253.08:00:52.67/valo/07,832.99,yes,locked 2006.253.08:00:52.67/valo/08,852.99,yes,locked 2006.253.08:00:53.76/vb/01,04,usb,yes,30,29 2006.253.08:00:53.76/vb/02,05,usb,yes,28,29 2006.253.08:00:53.76/vb/03,04,usb,yes,28,32 2006.253.08:00:53.76/vb/04,04,usb,yes,29,29 2006.253.08:00:53.76/vb/05,04,usb,yes,28,32 2006.253.08:00:53.76/vb/06,04,usb,yes,29,31 2006.253.08:00:53.76/vb/07,04,usb,yes,31,31 2006.253.08:00:53.76/vb/08,04,usb,yes,28,32 2006.253.08:00:54.00/vblo/01,632.99,yes,locked 2006.253.08:00:54.00/vblo/02,640.99,yes,locked 2006.253.08:00:54.00/vblo/03,656.99,yes,locked 2006.253.08:00:54.00/vblo/04,712.99,yes,locked 2006.253.08:00:54.00/vblo/05,744.99,yes,locked 2006.253.08:00:54.00/vblo/06,752.99,yes,locked 2006.253.08:00:54.00/vblo/07,734.99,yes,locked 2006.253.08:00:54.00/vblo/08,744.99,yes,locked 2006.253.08:00:54.15/vabw/8 2006.253.08:00:54.30/vbbw/8 2006.253.08:00:54.39/xfe/off,on,14.2 2006.253.08:00:54.76/ifatt/23,28,28,28 2006.253.08:00:55.08/fmout-gps/S +4.73E-07 2006.253.08:00:55.12:!2006.253.08:01:50 2006.253.08:01:50.00:data_valid=off 2006.253.08:01:50.00:postob 2006.253.08:01:50.12/cable/+6.3679E-03 2006.253.08:01:50.12/wx/31.09,1006.4,73 2006.253.08:01:51.08/fmout-gps/S +4.74E-07 2006.253.08:01:51.08:scan_name=253-0802,k06253,60 2006.253.08:01:51.08:source=1128+385,113053.28,381518.5,2000.0,ccw 2006.253.08:01:51.14#flagr#flagr/antenna,new-source 2006.253.08:01:52.14:checkk5 2006.253.08:01:52.54/chk_autoobs//k5ts1/ autoobs is running! 2006.253.08:01:52.91/chk_autoobs//k5ts2/ autoobs is running! 2006.253.08:01:53.28/chk_autoobs//k5ts3/ autoobs is running! 2006.253.08:01:53.67/chk_autoobs//k5ts4/ autoobs is running! 2006.253.08:01:54.04/chk_obsdata//k5ts1/T2530800??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.08:01:54.41/chk_obsdata//k5ts2/T2530800??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.08:01:54.78/chk_obsdata//k5ts3/T2530800??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.08:01:55.15/chk_obsdata//k5ts4/T2530800??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.08:01:55.86/k5log//k5ts1_log_newline 2006.253.08:01:56.55/k5log//k5ts2_log_newline 2006.253.08:01:57.29/k5log//k5ts3_log_newline 2006.253.08:01:57.98/k5log//k5ts4_log_newline 2006.253.08:01:58.00/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.253.08:01:58.00:4f8m12a=2 2006.253.08:01:58.00$4f8m12a/echo=on 2006.253.08:01:58.00$4f8m12a/pcalon 2006.253.08:01:58.00$pcalon/"no phase cal control is implemented here 2006.253.08:01:58.00$4f8m12a/"tpicd=stop 2006.253.08:01:58.00$4f8m12a/vc4f8 2006.253.08:01:58.00$vc4f8/valo=1,532.99 2006.253.08:01:58.00#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.253.08:01:58.00#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.253.08:01:58.00#ibcon#ireg 17 cls_cnt 0 2006.253.08:01:58.00#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.253.08:01:58.00#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.253.08:01:58.00#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.253.08:01:58.00#ibcon#enter wrdev, iclass 3, count 0 2006.253.08:01:58.00#ibcon#first serial, iclass 3, count 0 2006.253.08:01:58.00#ibcon#enter sib2, iclass 3, count 0 2006.253.08:01:58.00#ibcon#flushed, iclass 3, count 0 2006.253.08:01:58.00#ibcon#about to write, iclass 3, count 0 2006.253.08:01:58.00#ibcon#wrote, iclass 3, count 0 2006.253.08:01:58.00#ibcon#about to read 3, iclass 3, count 0 2006.253.08:01:58.02#ibcon#read 3, iclass 3, count 0 2006.253.08:01:58.02#ibcon#about to read 4, iclass 3, count 0 2006.253.08:01:58.02#ibcon#read 4, iclass 3, count 0 2006.253.08:01:58.02#ibcon#about to read 5, iclass 3, count 0 2006.253.08:01:58.02#ibcon#read 5, iclass 3, count 0 2006.253.08:01:58.02#ibcon#about to read 6, iclass 3, count 0 2006.253.08:01:58.02#ibcon#read 6, iclass 3, count 0 2006.253.08:01:58.02#ibcon#end of sib2, iclass 3, count 0 2006.253.08:01:58.02#ibcon#*mode == 0, iclass 3, count 0 2006.253.08:01:58.02#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.253.08:01:58.02#ibcon#[26=FRQ=01,532.99\r\n] 2006.253.08:01:58.02#ibcon#*before write, iclass 3, count 0 2006.253.08:01:58.02#ibcon#enter sib2, iclass 3, count 0 2006.253.08:01:58.02#ibcon#flushed, iclass 3, count 0 2006.253.08:01:58.02#ibcon#about to write, iclass 3, count 0 2006.253.08:01:58.02#ibcon#wrote, iclass 3, count 0 2006.253.08:01:58.02#ibcon#about to read 3, iclass 3, count 0 2006.253.08:01:58.07#ibcon#read 3, iclass 3, count 0 2006.253.08:01:58.07#ibcon#about to read 4, iclass 3, count 0 2006.253.08:01:58.07#ibcon#read 4, iclass 3, count 0 2006.253.08:01:58.07#ibcon#about to read 5, iclass 3, count 0 2006.253.08:01:58.07#ibcon#read 5, iclass 3, count 0 2006.253.08:01:58.07#ibcon#about to read 6, iclass 3, count 0 2006.253.08:01:58.07#ibcon#read 6, iclass 3, count 0 2006.253.08:01:58.07#ibcon#end of sib2, iclass 3, count 0 2006.253.08:01:58.07#ibcon#*after write, iclass 3, count 0 2006.253.08:01:58.07#ibcon#*before return 0, iclass 3, count 0 2006.253.08:01:58.07#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.253.08:01:58.07#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.253.08:01:58.07#ibcon#about to clear, iclass 3 cls_cnt 0 2006.253.08:01:58.07#ibcon#cleared, iclass 3 cls_cnt 0 2006.253.08:01:58.07$vc4f8/va=1,8 2006.253.08:01:58.07#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.253.08:01:58.07#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.253.08:01:58.07#ibcon#ireg 11 cls_cnt 2 2006.253.08:01:58.07#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.253.08:01:58.07#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.253.08:01:58.07#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.253.08:01:58.07#ibcon#enter wrdev, iclass 5, count 2 2006.253.08:01:58.07#ibcon#first serial, iclass 5, count 2 2006.253.08:01:58.07#ibcon#enter sib2, iclass 5, count 2 2006.253.08:01:58.07#ibcon#flushed, iclass 5, count 2 2006.253.08:01:58.07#ibcon#about to write, iclass 5, count 2 2006.253.08:01:58.07#ibcon#wrote, iclass 5, count 2 2006.253.08:01:58.07#ibcon#about to read 3, iclass 5, count 2 2006.253.08:01:58.09#ibcon#read 3, iclass 5, count 2 2006.253.08:01:58.09#ibcon#about to read 4, iclass 5, count 2 2006.253.08:01:58.09#ibcon#read 4, iclass 5, count 2 2006.253.08:01:58.09#ibcon#about to read 5, iclass 5, count 2 2006.253.08:01:58.09#ibcon#read 5, iclass 5, count 2 2006.253.08:01:58.09#ibcon#about to read 6, iclass 5, count 2 2006.253.08:01:58.09#ibcon#read 6, iclass 5, count 2 2006.253.08:01:58.09#ibcon#end of sib2, iclass 5, count 2 2006.253.08:01:58.09#ibcon#*mode == 0, iclass 5, count 2 2006.253.08:01:58.09#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.253.08:01:58.09#ibcon#[25=AT01-08\r\n] 2006.253.08:01:58.09#ibcon#*before write, iclass 5, count 2 2006.253.08:01:58.09#ibcon#enter sib2, iclass 5, count 2 2006.253.08:01:58.09#ibcon#flushed, iclass 5, count 2 2006.253.08:01:58.09#ibcon#about to write, iclass 5, count 2 2006.253.08:01:58.09#ibcon#wrote, iclass 5, count 2 2006.253.08:01:58.09#ibcon#about to read 3, iclass 5, count 2 2006.253.08:01:58.12#ibcon#read 3, iclass 5, count 2 2006.253.08:01:58.12#ibcon#about to read 4, iclass 5, count 2 2006.253.08:01:58.12#ibcon#read 4, iclass 5, count 2 2006.253.08:01:58.12#ibcon#about to read 5, iclass 5, count 2 2006.253.08:01:58.12#ibcon#read 5, iclass 5, count 2 2006.253.08:01:58.12#ibcon#about to read 6, iclass 5, count 2 2006.253.08:01:58.12#ibcon#read 6, iclass 5, count 2 2006.253.08:01:58.12#ibcon#end of sib2, iclass 5, count 2 2006.253.08:01:58.12#ibcon#*after write, iclass 5, count 2 2006.253.08:01:58.12#ibcon#*before return 0, iclass 5, count 2 2006.253.08:01:58.12#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.253.08:01:58.12#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.253.08:01:58.12#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.253.08:01:58.12#ibcon#ireg 7 cls_cnt 0 2006.253.08:01:58.12#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.253.08:01:58.24#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.253.08:01:58.24#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.253.08:01:58.24#ibcon#enter wrdev, iclass 5, count 0 2006.253.08:01:58.24#ibcon#first serial, iclass 5, count 0 2006.253.08:01:58.24#ibcon#enter sib2, iclass 5, count 0 2006.253.08:01:58.24#ibcon#flushed, iclass 5, count 0 2006.253.08:01:58.24#ibcon#about to write, iclass 5, count 0 2006.253.08:01:58.24#ibcon#wrote, iclass 5, count 0 2006.253.08:01:58.24#ibcon#about to read 3, iclass 5, count 0 2006.253.08:01:58.26#ibcon#read 3, iclass 5, count 0 2006.253.08:01:58.26#ibcon#about to read 4, iclass 5, count 0 2006.253.08:01:58.26#ibcon#read 4, iclass 5, count 0 2006.253.08:01:58.26#ibcon#about to read 5, iclass 5, count 0 2006.253.08:01:58.26#ibcon#read 5, iclass 5, count 0 2006.253.08:01:58.26#ibcon#about to read 6, iclass 5, count 0 2006.253.08:01:58.26#ibcon#read 6, iclass 5, count 0 2006.253.08:01:58.26#ibcon#end of sib2, iclass 5, count 0 2006.253.08:01:58.26#ibcon#*mode == 0, iclass 5, count 0 2006.253.08:01:58.26#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.253.08:01:58.26#ibcon#[25=USB\r\n] 2006.253.08:01:58.26#ibcon#*before write, iclass 5, count 0 2006.253.08:01:58.26#ibcon#enter sib2, iclass 5, count 0 2006.253.08:01:58.26#ibcon#flushed, iclass 5, count 0 2006.253.08:01:58.26#ibcon#about to write, iclass 5, count 0 2006.253.08:01:58.26#ibcon#wrote, iclass 5, count 0 2006.253.08:01:58.26#ibcon#about to read 3, iclass 5, count 0 2006.253.08:01:58.29#ibcon#read 3, iclass 5, count 0 2006.253.08:01:58.29#ibcon#about to read 4, iclass 5, count 0 2006.253.08:01:58.29#ibcon#read 4, iclass 5, count 0 2006.253.08:01:58.29#ibcon#about to read 5, iclass 5, count 0 2006.253.08:01:58.29#ibcon#read 5, iclass 5, count 0 2006.253.08:01:58.29#ibcon#about to read 6, iclass 5, count 0 2006.253.08:01:58.29#ibcon#read 6, iclass 5, count 0 2006.253.08:01:58.29#ibcon#end of sib2, iclass 5, count 0 2006.253.08:01:58.29#ibcon#*after write, iclass 5, count 0 2006.253.08:01:58.29#ibcon#*before return 0, iclass 5, count 0 2006.253.08:01:58.29#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.253.08:01:58.29#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.253.08:01:58.29#ibcon#about to clear, iclass 5 cls_cnt 0 2006.253.08:01:58.29#ibcon#cleared, iclass 5 cls_cnt 0 2006.253.08:01:58.29$vc4f8/valo=2,572.99 2006.253.08:01:58.29#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.253.08:01:58.29#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.253.08:01:58.29#ibcon#ireg 17 cls_cnt 0 2006.253.08:01:58.29#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.253.08:01:58.29#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.253.08:01:58.29#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.253.08:01:58.29#ibcon#enter wrdev, iclass 7, count 0 2006.253.08:01:58.29#ibcon#first serial, iclass 7, count 0 2006.253.08:01:58.29#ibcon#enter sib2, iclass 7, count 0 2006.253.08:01:58.29#ibcon#flushed, iclass 7, count 0 2006.253.08:01:58.29#ibcon#about to write, iclass 7, count 0 2006.253.08:01:58.29#ibcon#wrote, iclass 7, count 0 2006.253.08:01:58.29#ibcon#about to read 3, iclass 7, count 0 2006.253.08:01:58.32#ibcon#read 3, iclass 7, count 0 2006.253.08:01:58.32#ibcon#about to read 4, iclass 7, count 0 2006.253.08:01:58.32#ibcon#read 4, iclass 7, count 0 2006.253.08:01:58.32#ibcon#about to read 5, iclass 7, count 0 2006.253.08:01:58.32#ibcon#read 5, iclass 7, count 0 2006.253.08:01:58.32#ibcon#about to read 6, iclass 7, count 0 2006.253.08:01:58.32#ibcon#read 6, iclass 7, count 0 2006.253.08:01:58.32#ibcon#end of sib2, iclass 7, count 0 2006.253.08:01:58.32#ibcon#*mode == 0, iclass 7, count 0 2006.253.08:01:58.32#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.253.08:01:58.32#ibcon#[26=FRQ=02,572.99\r\n] 2006.253.08:01:58.32#ibcon#*before write, iclass 7, count 0 2006.253.08:01:58.32#ibcon#enter sib2, iclass 7, count 0 2006.253.08:01:58.32#ibcon#flushed, iclass 7, count 0 2006.253.08:01:58.32#ibcon#about to write, iclass 7, count 0 2006.253.08:01:58.32#ibcon#wrote, iclass 7, count 0 2006.253.08:01:58.32#ibcon#about to read 3, iclass 7, count 0 2006.253.08:01:58.36#ibcon#read 3, iclass 7, count 0 2006.253.08:01:58.36#ibcon#about to read 4, iclass 7, count 0 2006.253.08:01:58.36#ibcon#read 4, iclass 7, count 0 2006.253.08:01:58.36#ibcon#about to read 5, iclass 7, count 0 2006.253.08:01:58.36#ibcon#read 5, iclass 7, count 0 2006.253.08:01:58.36#ibcon#about to read 6, iclass 7, count 0 2006.253.08:01:58.36#ibcon#read 6, iclass 7, count 0 2006.253.08:01:58.36#ibcon#end of sib2, iclass 7, count 0 2006.253.08:01:58.36#ibcon#*after write, iclass 7, count 0 2006.253.08:01:58.36#ibcon#*before return 0, iclass 7, count 0 2006.253.08:01:58.36#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.253.08:01:58.36#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.253.08:01:58.36#ibcon#about to clear, iclass 7 cls_cnt 0 2006.253.08:01:58.36#ibcon#cleared, iclass 7 cls_cnt 0 2006.253.08:01:58.36$vc4f8/va=2,7 2006.253.08:01:58.36#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.253.08:01:58.36#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.253.08:01:58.36#ibcon#ireg 11 cls_cnt 2 2006.253.08:01:58.36#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.253.08:01:58.41#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.253.08:01:58.41#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.253.08:01:58.41#ibcon#enter wrdev, iclass 11, count 2 2006.253.08:01:58.41#ibcon#first serial, iclass 11, count 2 2006.253.08:01:58.41#ibcon#enter sib2, iclass 11, count 2 2006.253.08:01:58.41#ibcon#flushed, iclass 11, count 2 2006.253.08:01:58.41#ibcon#about to write, iclass 11, count 2 2006.253.08:01:58.41#ibcon#wrote, iclass 11, count 2 2006.253.08:01:58.41#ibcon#about to read 3, iclass 11, count 2 2006.253.08:01:58.43#ibcon#read 3, iclass 11, count 2 2006.253.08:01:58.43#ibcon#about to read 4, iclass 11, count 2 2006.253.08:01:58.43#ibcon#read 4, iclass 11, count 2 2006.253.08:01:58.43#ibcon#about to read 5, iclass 11, count 2 2006.253.08:01:58.43#ibcon#read 5, iclass 11, count 2 2006.253.08:01:58.43#ibcon#about to read 6, iclass 11, count 2 2006.253.08:01:58.43#ibcon#read 6, iclass 11, count 2 2006.253.08:01:58.43#ibcon#end of sib2, iclass 11, count 2 2006.253.08:01:58.43#ibcon#*mode == 0, iclass 11, count 2 2006.253.08:01:58.43#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.253.08:01:58.43#ibcon#[25=AT02-07\r\n] 2006.253.08:01:58.43#ibcon#*before write, iclass 11, count 2 2006.253.08:01:58.43#ibcon#enter sib2, iclass 11, count 2 2006.253.08:01:58.43#ibcon#flushed, iclass 11, count 2 2006.253.08:01:58.43#ibcon#about to write, iclass 11, count 2 2006.253.08:01:58.43#ibcon#wrote, iclass 11, count 2 2006.253.08:01:58.43#ibcon#about to read 3, iclass 11, count 2 2006.253.08:01:58.46#ibcon#read 3, iclass 11, count 2 2006.253.08:01:58.46#ibcon#about to read 4, iclass 11, count 2 2006.253.08:01:58.46#ibcon#read 4, iclass 11, count 2 2006.253.08:01:58.46#ibcon#about to read 5, iclass 11, count 2 2006.253.08:01:58.46#ibcon#read 5, iclass 11, count 2 2006.253.08:01:58.46#ibcon#about to read 6, iclass 11, count 2 2006.253.08:01:58.46#ibcon#read 6, iclass 11, count 2 2006.253.08:01:58.46#ibcon#end of sib2, iclass 11, count 2 2006.253.08:01:58.46#ibcon#*after write, iclass 11, count 2 2006.253.08:01:58.46#ibcon#*before return 0, iclass 11, count 2 2006.253.08:01:58.46#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.253.08:01:58.46#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.253.08:01:58.46#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.253.08:01:58.46#ibcon#ireg 7 cls_cnt 0 2006.253.08:01:58.46#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.253.08:01:58.58#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.253.08:01:58.58#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.253.08:01:58.58#ibcon#enter wrdev, iclass 11, count 0 2006.253.08:01:58.58#ibcon#first serial, iclass 11, count 0 2006.253.08:01:58.58#ibcon#enter sib2, iclass 11, count 0 2006.253.08:01:58.58#ibcon#flushed, iclass 11, count 0 2006.253.08:01:58.58#ibcon#about to write, iclass 11, count 0 2006.253.08:01:58.58#ibcon#wrote, iclass 11, count 0 2006.253.08:01:58.58#ibcon#about to read 3, iclass 11, count 0 2006.253.08:01:58.60#ibcon#read 3, iclass 11, count 0 2006.253.08:01:58.60#ibcon#about to read 4, iclass 11, count 0 2006.253.08:01:58.60#ibcon#read 4, iclass 11, count 0 2006.253.08:01:58.60#ibcon#about to read 5, iclass 11, count 0 2006.253.08:01:58.60#ibcon#read 5, iclass 11, count 0 2006.253.08:01:58.60#ibcon#about to read 6, iclass 11, count 0 2006.253.08:01:58.60#ibcon#read 6, iclass 11, count 0 2006.253.08:01:58.60#ibcon#end of sib2, iclass 11, count 0 2006.253.08:01:58.60#ibcon#*mode == 0, iclass 11, count 0 2006.253.08:01:58.60#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.253.08:01:58.60#ibcon#[25=USB\r\n] 2006.253.08:01:58.60#ibcon#*before write, iclass 11, count 0 2006.253.08:01:58.60#ibcon#enter sib2, iclass 11, count 0 2006.253.08:01:58.60#ibcon#flushed, iclass 11, count 0 2006.253.08:01:58.60#ibcon#about to write, iclass 11, count 0 2006.253.08:01:58.60#ibcon#wrote, iclass 11, count 0 2006.253.08:01:58.60#ibcon#about to read 3, iclass 11, count 0 2006.253.08:01:58.63#ibcon#read 3, iclass 11, count 0 2006.253.08:01:58.63#ibcon#about to read 4, iclass 11, count 0 2006.253.08:01:58.63#ibcon#read 4, iclass 11, count 0 2006.253.08:01:58.63#ibcon#about to read 5, iclass 11, count 0 2006.253.08:01:58.63#ibcon#read 5, iclass 11, count 0 2006.253.08:01:58.63#ibcon#about to read 6, iclass 11, count 0 2006.253.08:01:58.63#ibcon#read 6, iclass 11, count 0 2006.253.08:01:58.63#ibcon#end of sib2, iclass 11, count 0 2006.253.08:01:58.63#ibcon#*after write, iclass 11, count 0 2006.253.08:01:58.63#ibcon#*before return 0, iclass 11, count 0 2006.253.08:01:58.63#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.253.08:01:58.63#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.253.08:01:58.63#ibcon#about to clear, iclass 11 cls_cnt 0 2006.253.08:01:58.63#ibcon#cleared, iclass 11 cls_cnt 0 2006.253.08:01:58.63$vc4f8/valo=3,672.99 2006.253.08:01:58.63#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.253.08:01:58.63#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.253.08:01:58.63#ibcon#ireg 17 cls_cnt 0 2006.253.08:01:58.63#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.253.08:01:58.63#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.253.08:01:58.63#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.253.08:01:58.63#ibcon#enter wrdev, iclass 13, count 0 2006.253.08:01:58.63#ibcon#first serial, iclass 13, count 0 2006.253.08:01:58.63#ibcon#enter sib2, iclass 13, count 0 2006.253.08:01:58.63#ibcon#flushed, iclass 13, count 0 2006.253.08:01:58.63#ibcon#about to write, iclass 13, count 0 2006.253.08:01:58.63#ibcon#wrote, iclass 13, count 0 2006.253.08:01:58.63#ibcon#about to read 3, iclass 13, count 0 2006.253.08:01:58.66#ibcon#read 3, iclass 13, count 0 2006.253.08:01:58.66#ibcon#about to read 4, iclass 13, count 0 2006.253.08:01:58.66#ibcon#read 4, iclass 13, count 0 2006.253.08:01:58.66#ibcon#about to read 5, iclass 13, count 0 2006.253.08:01:58.66#ibcon#read 5, iclass 13, count 0 2006.253.08:01:58.66#ibcon#about to read 6, iclass 13, count 0 2006.253.08:01:58.66#ibcon#read 6, iclass 13, count 0 2006.253.08:01:58.66#ibcon#end of sib2, iclass 13, count 0 2006.253.08:01:58.66#ibcon#*mode == 0, iclass 13, count 0 2006.253.08:01:58.66#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.253.08:01:58.66#ibcon#[26=FRQ=03,672.99\r\n] 2006.253.08:01:58.66#ibcon#*before write, iclass 13, count 0 2006.253.08:01:58.66#ibcon#enter sib2, iclass 13, count 0 2006.253.08:01:58.66#ibcon#flushed, iclass 13, count 0 2006.253.08:01:58.66#ibcon#about to write, iclass 13, count 0 2006.253.08:01:58.66#ibcon#wrote, iclass 13, count 0 2006.253.08:01:58.66#ibcon#about to read 3, iclass 13, count 0 2006.253.08:01:58.70#ibcon#read 3, iclass 13, count 0 2006.253.08:01:58.70#ibcon#about to read 4, iclass 13, count 0 2006.253.08:01:58.70#ibcon#read 4, iclass 13, count 0 2006.253.08:01:58.70#ibcon#about to read 5, iclass 13, count 0 2006.253.08:01:58.70#ibcon#read 5, iclass 13, count 0 2006.253.08:01:58.70#ibcon#about to read 6, iclass 13, count 0 2006.253.08:01:58.70#ibcon#read 6, iclass 13, count 0 2006.253.08:01:58.70#ibcon#end of sib2, iclass 13, count 0 2006.253.08:01:58.70#ibcon#*after write, iclass 13, count 0 2006.253.08:01:58.70#ibcon#*before return 0, iclass 13, count 0 2006.253.08:01:58.70#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.253.08:01:58.70#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.253.08:01:58.70#ibcon#about to clear, iclass 13 cls_cnt 0 2006.253.08:01:58.70#ibcon#cleared, iclass 13 cls_cnt 0 2006.253.08:01:58.70$vc4f8/va=3,6 2006.253.08:01:58.70#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.253.08:01:58.70#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.253.08:01:58.70#ibcon#ireg 11 cls_cnt 2 2006.253.08:01:58.70#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.253.08:01:58.75#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.253.08:01:58.75#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.253.08:01:58.75#ibcon#enter wrdev, iclass 15, count 2 2006.253.08:01:58.75#ibcon#first serial, iclass 15, count 2 2006.253.08:01:58.75#ibcon#enter sib2, iclass 15, count 2 2006.253.08:01:58.75#ibcon#flushed, iclass 15, count 2 2006.253.08:01:58.75#ibcon#about to write, iclass 15, count 2 2006.253.08:01:58.75#ibcon#wrote, iclass 15, count 2 2006.253.08:01:58.75#ibcon#about to read 3, iclass 15, count 2 2006.253.08:01:58.77#ibcon#read 3, iclass 15, count 2 2006.253.08:01:58.77#ibcon#about to read 4, iclass 15, count 2 2006.253.08:01:58.77#ibcon#read 4, iclass 15, count 2 2006.253.08:01:58.77#ibcon#about to read 5, iclass 15, count 2 2006.253.08:01:58.77#ibcon#read 5, iclass 15, count 2 2006.253.08:01:58.77#ibcon#about to read 6, iclass 15, count 2 2006.253.08:01:58.77#ibcon#read 6, iclass 15, count 2 2006.253.08:01:58.77#ibcon#end of sib2, iclass 15, count 2 2006.253.08:01:58.77#ibcon#*mode == 0, iclass 15, count 2 2006.253.08:01:58.77#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.253.08:01:58.77#ibcon#[25=AT03-06\r\n] 2006.253.08:01:58.77#ibcon#*before write, iclass 15, count 2 2006.253.08:01:58.77#ibcon#enter sib2, iclass 15, count 2 2006.253.08:01:58.77#ibcon#flushed, iclass 15, count 2 2006.253.08:01:58.77#ibcon#about to write, iclass 15, count 2 2006.253.08:01:58.77#ibcon#wrote, iclass 15, count 2 2006.253.08:01:58.77#ibcon#about to read 3, iclass 15, count 2 2006.253.08:01:58.80#ibcon#read 3, iclass 15, count 2 2006.253.08:01:58.80#ibcon#about to read 4, iclass 15, count 2 2006.253.08:01:58.80#ibcon#read 4, iclass 15, count 2 2006.253.08:01:58.80#ibcon#about to read 5, iclass 15, count 2 2006.253.08:01:58.80#ibcon#read 5, iclass 15, count 2 2006.253.08:01:58.80#ibcon#about to read 6, iclass 15, count 2 2006.253.08:01:58.80#ibcon#read 6, iclass 15, count 2 2006.253.08:01:58.80#ibcon#end of sib2, iclass 15, count 2 2006.253.08:01:58.80#ibcon#*after write, iclass 15, count 2 2006.253.08:01:58.80#ibcon#*before return 0, iclass 15, count 2 2006.253.08:01:58.80#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.253.08:01:58.80#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.253.08:01:58.80#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.253.08:01:58.80#ibcon#ireg 7 cls_cnt 0 2006.253.08:01:58.80#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.253.08:01:58.92#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.253.08:01:58.92#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.253.08:01:58.92#ibcon#enter wrdev, iclass 15, count 0 2006.253.08:01:58.92#ibcon#first serial, iclass 15, count 0 2006.253.08:01:58.92#ibcon#enter sib2, iclass 15, count 0 2006.253.08:01:58.92#ibcon#flushed, iclass 15, count 0 2006.253.08:01:58.92#ibcon#about to write, iclass 15, count 0 2006.253.08:01:58.92#ibcon#wrote, iclass 15, count 0 2006.253.08:01:58.92#ibcon#about to read 3, iclass 15, count 0 2006.253.08:01:58.94#ibcon#read 3, iclass 15, count 0 2006.253.08:01:58.94#ibcon#about to read 4, iclass 15, count 0 2006.253.08:01:58.94#ibcon#read 4, iclass 15, count 0 2006.253.08:01:58.94#ibcon#about to read 5, iclass 15, count 0 2006.253.08:01:58.94#ibcon#read 5, iclass 15, count 0 2006.253.08:01:58.94#ibcon#about to read 6, iclass 15, count 0 2006.253.08:01:58.94#ibcon#read 6, iclass 15, count 0 2006.253.08:01:58.94#ibcon#end of sib2, iclass 15, count 0 2006.253.08:01:58.94#ibcon#*mode == 0, iclass 15, count 0 2006.253.08:01:58.94#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.253.08:01:58.94#ibcon#[25=USB\r\n] 2006.253.08:01:58.94#ibcon#*before write, iclass 15, count 0 2006.253.08:01:58.94#ibcon#enter sib2, iclass 15, count 0 2006.253.08:01:58.94#ibcon#flushed, iclass 15, count 0 2006.253.08:01:58.94#ibcon#about to write, iclass 15, count 0 2006.253.08:01:58.94#ibcon#wrote, iclass 15, count 0 2006.253.08:01:58.94#ibcon#about to read 3, iclass 15, count 0 2006.253.08:01:58.97#ibcon#read 3, iclass 15, count 0 2006.253.08:01:58.97#ibcon#about to read 4, iclass 15, count 0 2006.253.08:01:58.97#ibcon#read 4, iclass 15, count 0 2006.253.08:01:58.97#ibcon#about to read 5, iclass 15, count 0 2006.253.08:01:58.97#ibcon#read 5, iclass 15, count 0 2006.253.08:01:58.97#ibcon#about to read 6, iclass 15, count 0 2006.253.08:01:58.97#ibcon#read 6, iclass 15, count 0 2006.253.08:01:58.97#ibcon#end of sib2, iclass 15, count 0 2006.253.08:01:58.97#ibcon#*after write, iclass 15, count 0 2006.253.08:01:58.97#ibcon#*before return 0, iclass 15, count 0 2006.253.08:01:58.97#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.253.08:01:58.97#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.253.08:01:58.97#ibcon#about to clear, iclass 15 cls_cnt 0 2006.253.08:01:58.97#ibcon#cleared, iclass 15 cls_cnt 0 2006.253.08:01:58.97$vc4f8/valo=4,832.99 2006.253.08:01:58.97#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.253.08:01:58.97#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.253.08:01:58.97#ibcon#ireg 17 cls_cnt 0 2006.253.08:01:58.97#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.253.08:01:58.97#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.253.08:01:58.97#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.253.08:01:58.97#ibcon#enter wrdev, iclass 17, count 0 2006.253.08:01:58.97#ibcon#first serial, iclass 17, count 0 2006.253.08:01:58.97#ibcon#enter sib2, iclass 17, count 0 2006.253.08:01:58.97#ibcon#flushed, iclass 17, count 0 2006.253.08:01:58.97#ibcon#about to write, iclass 17, count 0 2006.253.08:01:58.97#ibcon#wrote, iclass 17, count 0 2006.253.08:01:58.97#ibcon#about to read 3, iclass 17, count 0 2006.253.08:01:59.00#ibcon#read 3, iclass 17, count 0 2006.253.08:01:59.00#ibcon#about to read 4, iclass 17, count 0 2006.253.08:01:59.00#ibcon#read 4, iclass 17, count 0 2006.253.08:01:59.00#ibcon#about to read 5, iclass 17, count 0 2006.253.08:01:59.00#ibcon#read 5, iclass 17, count 0 2006.253.08:01:59.00#ibcon#about to read 6, iclass 17, count 0 2006.253.08:01:59.00#ibcon#read 6, iclass 17, count 0 2006.253.08:01:59.00#ibcon#end of sib2, iclass 17, count 0 2006.253.08:01:59.00#ibcon#*mode == 0, iclass 17, count 0 2006.253.08:01:59.00#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.253.08:01:59.00#ibcon#[26=FRQ=04,832.99\r\n] 2006.253.08:01:59.00#ibcon#*before write, iclass 17, count 0 2006.253.08:01:59.00#ibcon#enter sib2, iclass 17, count 0 2006.253.08:01:59.00#ibcon#flushed, iclass 17, count 0 2006.253.08:01:59.00#ibcon#about to write, iclass 17, count 0 2006.253.08:01:59.00#ibcon#wrote, iclass 17, count 0 2006.253.08:01:59.00#ibcon#about to read 3, iclass 17, count 0 2006.253.08:01:59.04#ibcon#read 3, iclass 17, count 0 2006.253.08:01:59.04#ibcon#about to read 4, iclass 17, count 0 2006.253.08:01:59.04#ibcon#read 4, iclass 17, count 0 2006.253.08:01:59.04#ibcon#about to read 5, iclass 17, count 0 2006.253.08:01:59.04#ibcon#read 5, iclass 17, count 0 2006.253.08:01:59.04#ibcon#about to read 6, iclass 17, count 0 2006.253.08:01:59.04#ibcon#read 6, iclass 17, count 0 2006.253.08:01:59.04#ibcon#end of sib2, iclass 17, count 0 2006.253.08:01:59.04#ibcon#*after write, iclass 17, count 0 2006.253.08:01:59.04#ibcon#*before return 0, iclass 17, count 0 2006.253.08:01:59.04#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.253.08:01:59.04#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.253.08:01:59.04#ibcon#about to clear, iclass 17 cls_cnt 0 2006.253.08:01:59.04#ibcon#cleared, iclass 17 cls_cnt 0 2006.253.08:01:59.04$vc4f8/va=4,7 2006.253.08:01:59.04#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.253.08:01:59.04#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.253.08:01:59.04#ibcon#ireg 11 cls_cnt 2 2006.253.08:01:59.04#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.253.08:01:59.09#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.253.08:01:59.09#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.253.08:01:59.09#ibcon#enter wrdev, iclass 19, count 2 2006.253.08:01:59.09#ibcon#first serial, iclass 19, count 2 2006.253.08:01:59.09#ibcon#enter sib2, iclass 19, count 2 2006.253.08:01:59.09#ibcon#flushed, iclass 19, count 2 2006.253.08:01:59.09#ibcon#about to write, iclass 19, count 2 2006.253.08:01:59.09#ibcon#wrote, iclass 19, count 2 2006.253.08:01:59.09#ibcon#about to read 3, iclass 19, count 2 2006.253.08:01:59.11#ibcon#read 3, iclass 19, count 2 2006.253.08:01:59.11#ibcon#about to read 4, iclass 19, count 2 2006.253.08:01:59.11#ibcon#read 4, iclass 19, count 2 2006.253.08:01:59.11#ibcon#about to read 5, iclass 19, count 2 2006.253.08:01:59.11#ibcon#read 5, iclass 19, count 2 2006.253.08:01:59.11#ibcon#about to read 6, iclass 19, count 2 2006.253.08:01:59.11#ibcon#read 6, iclass 19, count 2 2006.253.08:01:59.11#ibcon#end of sib2, iclass 19, count 2 2006.253.08:01:59.11#ibcon#*mode == 0, iclass 19, count 2 2006.253.08:01:59.11#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.253.08:01:59.11#ibcon#[25=AT04-07\r\n] 2006.253.08:01:59.11#ibcon#*before write, iclass 19, count 2 2006.253.08:01:59.11#ibcon#enter sib2, iclass 19, count 2 2006.253.08:01:59.11#ibcon#flushed, iclass 19, count 2 2006.253.08:01:59.11#ibcon#about to write, iclass 19, count 2 2006.253.08:01:59.11#ibcon#wrote, iclass 19, count 2 2006.253.08:01:59.11#ibcon#about to read 3, iclass 19, count 2 2006.253.08:01:59.14#ibcon#read 3, iclass 19, count 2 2006.253.08:01:59.14#ibcon#about to read 4, iclass 19, count 2 2006.253.08:01:59.14#ibcon#read 4, iclass 19, count 2 2006.253.08:01:59.14#ibcon#about to read 5, iclass 19, count 2 2006.253.08:01:59.14#ibcon#read 5, iclass 19, count 2 2006.253.08:01:59.14#ibcon#about to read 6, iclass 19, count 2 2006.253.08:01:59.14#ibcon#read 6, iclass 19, count 2 2006.253.08:01:59.14#ibcon#end of sib2, iclass 19, count 2 2006.253.08:01:59.14#ibcon#*after write, iclass 19, count 2 2006.253.08:01:59.14#ibcon#*before return 0, iclass 19, count 2 2006.253.08:01:59.14#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.253.08:01:59.14#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.253.08:01:59.14#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.253.08:01:59.14#ibcon#ireg 7 cls_cnt 0 2006.253.08:01:59.14#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.253.08:01:59.26#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.253.08:01:59.26#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.253.08:01:59.26#ibcon#enter wrdev, iclass 19, count 0 2006.253.08:01:59.26#ibcon#first serial, iclass 19, count 0 2006.253.08:01:59.26#ibcon#enter sib2, iclass 19, count 0 2006.253.08:01:59.26#ibcon#flushed, iclass 19, count 0 2006.253.08:01:59.26#ibcon#about to write, iclass 19, count 0 2006.253.08:01:59.26#ibcon#wrote, iclass 19, count 0 2006.253.08:01:59.26#ibcon#about to read 3, iclass 19, count 0 2006.253.08:01:59.28#ibcon#read 3, iclass 19, count 0 2006.253.08:01:59.28#ibcon#about to read 4, iclass 19, count 0 2006.253.08:01:59.28#ibcon#read 4, iclass 19, count 0 2006.253.08:01:59.28#ibcon#about to read 5, iclass 19, count 0 2006.253.08:01:59.28#ibcon#read 5, iclass 19, count 0 2006.253.08:01:59.28#ibcon#about to read 6, iclass 19, count 0 2006.253.08:01:59.28#ibcon#read 6, iclass 19, count 0 2006.253.08:01:59.28#ibcon#end of sib2, iclass 19, count 0 2006.253.08:01:59.28#ibcon#*mode == 0, iclass 19, count 0 2006.253.08:01:59.28#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.253.08:01:59.28#ibcon#[25=USB\r\n] 2006.253.08:01:59.28#ibcon#*before write, iclass 19, count 0 2006.253.08:01:59.28#ibcon#enter sib2, iclass 19, count 0 2006.253.08:01:59.28#ibcon#flushed, iclass 19, count 0 2006.253.08:01:59.28#ibcon#about to write, iclass 19, count 0 2006.253.08:01:59.28#ibcon#wrote, iclass 19, count 0 2006.253.08:01:59.28#ibcon#about to read 3, iclass 19, count 0 2006.253.08:01:59.31#ibcon#read 3, iclass 19, count 0 2006.253.08:01:59.31#ibcon#about to read 4, iclass 19, count 0 2006.253.08:01:59.31#ibcon#read 4, iclass 19, count 0 2006.253.08:01:59.31#ibcon#about to read 5, iclass 19, count 0 2006.253.08:01:59.31#ibcon#read 5, iclass 19, count 0 2006.253.08:01:59.31#ibcon#about to read 6, iclass 19, count 0 2006.253.08:01:59.31#ibcon#read 6, iclass 19, count 0 2006.253.08:01:59.31#ibcon#end of sib2, iclass 19, count 0 2006.253.08:01:59.31#ibcon#*after write, iclass 19, count 0 2006.253.08:01:59.31#ibcon#*before return 0, iclass 19, count 0 2006.253.08:01:59.31#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.253.08:01:59.31#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.253.08:01:59.31#ibcon#about to clear, iclass 19 cls_cnt 0 2006.253.08:01:59.31#ibcon#cleared, iclass 19 cls_cnt 0 2006.253.08:01:59.31$vc4f8/valo=5,652.99 2006.253.08:01:59.31#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.253.08:01:59.31#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.253.08:01:59.31#ibcon#ireg 17 cls_cnt 0 2006.253.08:01:59.31#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.253.08:01:59.31#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.253.08:01:59.31#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.253.08:01:59.31#ibcon#enter wrdev, iclass 21, count 0 2006.253.08:01:59.31#ibcon#first serial, iclass 21, count 0 2006.253.08:01:59.31#ibcon#enter sib2, iclass 21, count 0 2006.253.08:01:59.31#ibcon#flushed, iclass 21, count 0 2006.253.08:01:59.31#ibcon#about to write, iclass 21, count 0 2006.253.08:01:59.31#ibcon#wrote, iclass 21, count 0 2006.253.08:01:59.31#ibcon#about to read 3, iclass 21, count 0 2006.253.08:01:59.33#ibcon#read 3, iclass 21, count 0 2006.253.08:01:59.33#ibcon#about to read 4, iclass 21, count 0 2006.253.08:01:59.33#ibcon#read 4, iclass 21, count 0 2006.253.08:01:59.33#ibcon#about to read 5, iclass 21, count 0 2006.253.08:01:59.33#ibcon#read 5, iclass 21, count 0 2006.253.08:01:59.33#ibcon#about to read 6, iclass 21, count 0 2006.253.08:01:59.33#ibcon#read 6, iclass 21, count 0 2006.253.08:01:59.33#ibcon#end of sib2, iclass 21, count 0 2006.253.08:01:59.33#ibcon#*mode == 0, iclass 21, count 0 2006.253.08:01:59.33#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.253.08:01:59.33#ibcon#[26=FRQ=05,652.99\r\n] 2006.253.08:01:59.33#ibcon#*before write, iclass 21, count 0 2006.253.08:01:59.33#ibcon#enter sib2, iclass 21, count 0 2006.253.08:01:59.33#ibcon#flushed, iclass 21, count 0 2006.253.08:01:59.33#ibcon#about to write, iclass 21, count 0 2006.253.08:01:59.33#ibcon#wrote, iclass 21, count 0 2006.253.08:01:59.33#ibcon#about to read 3, iclass 21, count 0 2006.253.08:01:59.37#ibcon#read 3, iclass 21, count 0 2006.253.08:01:59.37#ibcon#about to read 4, iclass 21, count 0 2006.253.08:01:59.37#ibcon#read 4, iclass 21, count 0 2006.253.08:01:59.37#ibcon#about to read 5, iclass 21, count 0 2006.253.08:01:59.37#ibcon#read 5, iclass 21, count 0 2006.253.08:01:59.37#ibcon#about to read 6, iclass 21, count 0 2006.253.08:01:59.37#ibcon#read 6, iclass 21, count 0 2006.253.08:01:59.37#ibcon#end of sib2, iclass 21, count 0 2006.253.08:01:59.37#ibcon#*after write, iclass 21, count 0 2006.253.08:01:59.37#ibcon#*before return 0, iclass 21, count 0 2006.253.08:01:59.37#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.253.08:01:59.37#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.253.08:01:59.37#ibcon#about to clear, iclass 21 cls_cnt 0 2006.253.08:01:59.37#ibcon#cleared, iclass 21 cls_cnt 0 2006.253.08:01:59.37$vc4f8/va=5,7 2006.253.08:01:59.37#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.253.08:01:59.37#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.253.08:01:59.37#ibcon#ireg 11 cls_cnt 2 2006.253.08:01:59.37#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.253.08:01:59.43#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.253.08:01:59.43#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.253.08:01:59.43#ibcon#enter wrdev, iclass 23, count 2 2006.253.08:01:59.43#ibcon#first serial, iclass 23, count 2 2006.253.08:01:59.43#ibcon#enter sib2, iclass 23, count 2 2006.253.08:01:59.43#ibcon#flushed, iclass 23, count 2 2006.253.08:01:59.43#ibcon#about to write, iclass 23, count 2 2006.253.08:01:59.43#ibcon#wrote, iclass 23, count 2 2006.253.08:01:59.43#ibcon#about to read 3, iclass 23, count 2 2006.253.08:01:59.45#ibcon#read 3, iclass 23, count 2 2006.253.08:01:59.45#ibcon#about to read 4, iclass 23, count 2 2006.253.08:01:59.45#ibcon#read 4, iclass 23, count 2 2006.253.08:01:59.45#ibcon#about to read 5, iclass 23, count 2 2006.253.08:01:59.45#ibcon#read 5, iclass 23, count 2 2006.253.08:01:59.45#ibcon#about to read 6, iclass 23, count 2 2006.253.08:01:59.45#ibcon#read 6, iclass 23, count 2 2006.253.08:01:59.45#ibcon#end of sib2, iclass 23, count 2 2006.253.08:01:59.45#ibcon#*mode == 0, iclass 23, count 2 2006.253.08:01:59.45#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.253.08:01:59.45#ibcon#[25=AT05-07\r\n] 2006.253.08:01:59.45#ibcon#*before write, iclass 23, count 2 2006.253.08:01:59.45#ibcon#enter sib2, iclass 23, count 2 2006.253.08:01:59.45#ibcon#flushed, iclass 23, count 2 2006.253.08:01:59.45#ibcon#about to write, iclass 23, count 2 2006.253.08:01:59.45#ibcon#wrote, iclass 23, count 2 2006.253.08:01:59.45#ibcon#about to read 3, iclass 23, count 2 2006.253.08:01:59.48#ibcon#read 3, iclass 23, count 2 2006.253.08:01:59.48#ibcon#about to read 4, iclass 23, count 2 2006.253.08:01:59.48#ibcon#read 4, iclass 23, count 2 2006.253.08:01:59.48#ibcon#about to read 5, iclass 23, count 2 2006.253.08:01:59.48#ibcon#read 5, iclass 23, count 2 2006.253.08:01:59.48#ibcon#about to read 6, iclass 23, count 2 2006.253.08:01:59.48#ibcon#read 6, iclass 23, count 2 2006.253.08:01:59.48#ibcon#end of sib2, iclass 23, count 2 2006.253.08:01:59.48#ibcon#*after write, iclass 23, count 2 2006.253.08:01:59.48#ibcon#*before return 0, iclass 23, count 2 2006.253.08:01:59.48#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.253.08:01:59.48#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.253.08:01:59.48#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.253.08:01:59.48#ibcon#ireg 7 cls_cnt 0 2006.253.08:01:59.48#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.253.08:01:59.60#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.253.08:01:59.60#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.253.08:01:59.60#ibcon#enter wrdev, iclass 23, count 0 2006.253.08:01:59.60#ibcon#first serial, iclass 23, count 0 2006.253.08:01:59.60#ibcon#enter sib2, iclass 23, count 0 2006.253.08:01:59.60#ibcon#flushed, iclass 23, count 0 2006.253.08:01:59.60#ibcon#about to write, iclass 23, count 0 2006.253.08:01:59.60#ibcon#wrote, iclass 23, count 0 2006.253.08:01:59.60#ibcon#about to read 3, iclass 23, count 0 2006.253.08:01:59.62#ibcon#read 3, iclass 23, count 0 2006.253.08:01:59.62#ibcon#about to read 4, iclass 23, count 0 2006.253.08:01:59.62#ibcon#read 4, iclass 23, count 0 2006.253.08:01:59.62#ibcon#about to read 5, iclass 23, count 0 2006.253.08:01:59.62#ibcon#read 5, iclass 23, count 0 2006.253.08:01:59.62#ibcon#about to read 6, iclass 23, count 0 2006.253.08:01:59.62#ibcon#read 6, iclass 23, count 0 2006.253.08:01:59.62#ibcon#end of sib2, iclass 23, count 0 2006.253.08:01:59.62#ibcon#*mode == 0, iclass 23, count 0 2006.253.08:01:59.62#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.253.08:01:59.62#ibcon#[25=USB\r\n] 2006.253.08:01:59.62#ibcon#*before write, iclass 23, count 0 2006.253.08:01:59.62#ibcon#enter sib2, iclass 23, count 0 2006.253.08:01:59.62#ibcon#flushed, iclass 23, count 0 2006.253.08:01:59.62#ibcon#about to write, iclass 23, count 0 2006.253.08:01:59.62#ibcon#wrote, iclass 23, count 0 2006.253.08:01:59.62#ibcon#about to read 3, iclass 23, count 0 2006.253.08:01:59.65#ibcon#read 3, iclass 23, count 0 2006.253.08:01:59.65#ibcon#about to read 4, iclass 23, count 0 2006.253.08:01:59.65#ibcon#read 4, iclass 23, count 0 2006.253.08:01:59.65#ibcon#about to read 5, iclass 23, count 0 2006.253.08:01:59.65#ibcon#read 5, iclass 23, count 0 2006.253.08:01:59.65#ibcon#about to read 6, iclass 23, count 0 2006.253.08:01:59.65#ibcon#read 6, iclass 23, count 0 2006.253.08:01:59.65#ibcon#end of sib2, iclass 23, count 0 2006.253.08:01:59.65#ibcon#*after write, iclass 23, count 0 2006.253.08:01:59.65#ibcon#*before return 0, iclass 23, count 0 2006.253.08:01:59.65#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.253.08:01:59.65#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.253.08:01:59.65#ibcon#about to clear, iclass 23 cls_cnt 0 2006.253.08:01:59.65#ibcon#cleared, iclass 23 cls_cnt 0 2006.253.08:01:59.65$vc4f8/valo=6,772.99 2006.253.08:01:59.65#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.253.08:01:59.65#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.253.08:01:59.65#ibcon#ireg 17 cls_cnt 0 2006.253.08:01:59.65#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.253.08:01:59.65#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.253.08:01:59.65#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.253.08:01:59.65#ibcon#enter wrdev, iclass 25, count 0 2006.253.08:01:59.65#ibcon#first serial, iclass 25, count 0 2006.253.08:01:59.65#ibcon#enter sib2, iclass 25, count 0 2006.253.08:01:59.65#ibcon#flushed, iclass 25, count 0 2006.253.08:01:59.65#ibcon#about to write, iclass 25, count 0 2006.253.08:01:59.65#ibcon#wrote, iclass 25, count 0 2006.253.08:01:59.65#ibcon#about to read 3, iclass 25, count 0 2006.253.08:01:59.68#ibcon#read 3, iclass 25, count 0 2006.253.08:01:59.68#ibcon#about to read 4, iclass 25, count 0 2006.253.08:01:59.68#ibcon#read 4, iclass 25, count 0 2006.253.08:01:59.68#ibcon#about to read 5, iclass 25, count 0 2006.253.08:01:59.68#ibcon#read 5, iclass 25, count 0 2006.253.08:01:59.68#ibcon#about to read 6, iclass 25, count 0 2006.253.08:01:59.68#ibcon#read 6, iclass 25, count 0 2006.253.08:01:59.68#ibcon#end of sib2, iclass 25, count 0 2006.253.08:01:59.68#ibcon#*mode == 0, iclass 25, count 0 2006.253.08:01:59.68#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.253.08:01:59.68#ibcon#[26=FRQ=06,772.99\r\n] 2006.253.08:01:59.68#ibcon#*before write, iclass 25, count 0 2006.253.08:01:59.68#ibcon#enter sib2, iclass 25, count 0 2006.253.08:01:59.68#ibcon#flushed, iclass 25, count 0 2006.253.08:01:59.68#ibcon#about to write, iclass 25, count 0 2006.253.08:01:59.68#ibcon#wrote, iclass 25, count 0 2006.253.08:01:59.68#ibcon#about to read 3, iclass 25, count 0 2006.253.08:01:59.72#ibcon#read 3, iclass 25, count 0 2006.253.08:01:59.72#ibcon#about to read 4, iclass 25, count 0 2006.253.08:01:59.72#ibcon#read 4, iclass 25, count 0 2006.253.08:01:59.72#ibcon#about to read 5, iclass 25, count 0 2006.253.08:01:59.72#ibcon#read 5, iclass 25, count 0 2006.253.08:01:59.72#ibcon#about to read 6, iclass 25, count 0 2006.253.08:01:59.72#ibcon#read 6, iclass 25, count 0 2006.253.08:01:59.72#ibcon#end of sib2, iclass 25, count 0 2006.253.08:01:59.72#ibcon#*after write, iclass 25, count 0 2006.253.08:01:59.72#ibcon#*before return 0, iclass 25, count 0 2006.253.08:01:59.72#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.253.08:01:59.72#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.253.08:01:59.72#ibcon#about to clear, iclass 25 cls_cnt 0 2006.253.08:01:59.72#ibcon#cleared, iclass 25 cls_cnt 0 2006.253.08:01:59.72$vc4f8/va=6,7 2006.253.08:01:59.72#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.253.08:01:59.72#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.253.08:01:59.72#ibcon#ireg 11 cls_cnt 2 2006.253.08:01:59.72#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.253.08:01:59.77#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.253.08:01:59.77#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.253.08:01:59.77#ibcon#enter wrdev, iclass 27, count 2 2006.253.08:01:59.77#ibcon#first serial, iclass 27, count 2 2006.253.08:01:59.77#ibcon#enter sib2, iclass 27, count 2 2006.253.08:01:59.77#ibcon#flushed, iclass 27, count 2 2006.253.08:01:59.77#ibcon#about to write, iclass 27, count 2 2006.253.08:01:59.77#ibcon#wrote, iclass 27, count 2 2006.253.08:01:59.77#ibcon#about to read 3, iclass 27, count 2 2006.253.08:01:59.79#ibcon#read 3, iclass 27, count 2 2006.253.08:01:59.79#ibcon#about to read 4, iclass 27, count 2 2006.253.08:01:59.79#ibcon#read 4, iclass 27, count 2 2006.253.08:01:59.79#ibcon#about to read 5, iclass 27, count 2 2006.253.08:01:59.79#ibcon#read 5, iclass 27, count 2 2006.253.08:01:59.79#ibcon#about to read 6, iclass 27, count 2 2006.253.08:01:59.79#ibcon#read 6, iclass 27, count 2 2006.253.08:01:59.79#ibcon#end of sib2, iclass 27, count 2 2006.253.08:01:59.79#ibcon#*mode == 0, iclass 27, count 2 2006.253.08:01:59.79#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.253.08:01:59.79#ibcon#[25=AT06-07\r\n] 2006.253.08:01:59.79#ibcon#*before write, iclass 27, count 2 2006.253.08:01:59.79#ibcon#enter sib2, iclass 27, count 2 2006.253.08:01:59.79#ibcon#flushed, iclass 27, count 2 2006.253.08:01:59.79#ibcon#about to write, iclass 27, count 2 2006.253.08:01:59.79#ibcon#wrote, iclass 27, count 2 2006.253.08:01:59.79#ibcon#about to read 3, iclass 27, count 2 2006.253.08:01:59.82#ibcon#read 3, iclass 27, count 2 2006.253.08:01:59.82#ibcon#about to read 4, iclass 27, count 2 2006.253.08:01:59.82#ibcon#read 4, iclass 27, count 2 2006.253.08:01:59.82#ibcon#about to read 5, iclass 27, count 2 2006.253.08:01:59.82#ibcon#read 5, iclass 27, count 2 2006.253.08:01:59.82#ibcon#about to read 6, iclass 27, count 2 2006.253.08:01:59.82#ibcon#read 6, iclass 27, count 2 2006.253.08:01:59.82#ibcon#end of sib2, iclass 27, count 2 2006.253.08:01:59.82#ibcon#*after write, iclass 27, count 2 2006.253.08:01:59.82#ibcon#*before return 0, iclass 27, count 2 2006.253.08:01:59.82#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.253.08:01:59.82#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.253.08:01:59.82#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.253.08:01:59.82#ibcon#ireg 7 cls_cnt 0 2006.253.08:01:59.82#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.253.08:01:59.94#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.253.08:01:59.94#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.253.08:01:59.94#ibcon#enter wrdev, iclass 27, count 0 2006.253.08:01:59.94#ibcon#first serial, iclass 27, count 0 2006.253.08:01:59.94#ibcon#enter sib2, iclass 27, count 0 2006.253.08:01:59.94#ibcon#flushed, iclass 27, count 0 2006.253.08:01:59.94#ibcon#about to write, iclass 27, count 0 2006.253.08:01:59.94#ibcon#wrote, iclass 27, count 0 2006.253.08:01:59.94#ibcon#about to read 3, iclass 27, count 0 2006.253.08:01:59.96#ibcon#read 3, iclass 27, count 0 2006.253.08:01:59.96#ibcon#about to read 4, iclass 27, count 0 2006.253.08:01:59.96#ibcon#read 4, iclass 27, count 0 2006.253.08:01:59.96#ibcon#about to read 5, iclass 27, count 0 2006.253.08:01:59.96#ibcon#read 5, iclass 27, count 0 2006.253.08:01:59.96#ibcon#about to read 6, iclass 27, count 0 2006.253.08:01:59.96#ibcon#read 6, iclass 27, count 0 2006.253.08:01:59.96#ibcon#end of sib2, iclass 27, count 0 2006.253.08:01:59.96#ibcon#*mode == 0, iclass 27, count 0 2006.253.08:01:59.96#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.253.08:01:59.96#ibcon#[25=USB\r\n] 2006.253.08:01:59.96#ibcon#*before write, iclass 27, count 0 2006.253.08:01:59.96#ibcon#enter sib2, iclass 27, count 0 2006.253.08:01:59.96#ibcon#flushed, iclass 27, count 0 2006.253.08:01:59.96#ibcon#about to write, iclass 27, count 0 2006.253.08:01:59.96#ibcon#wrote, iclass 27, count 0 2006.253.08:01:59.96#ibcon#about to read 3, iclass 27, count 0 2006.253.08:01:59.99#ibcon#read 3, iclass 27, count 0 2006.253.08:01:59.99#ibcon#about to read 4, iclass 27, count 0 2006.253.08:01:59.99#ibcon#read 4, iclass 27, count 0 2006.253.08:01:59.99#ibcon#about to read 5, iclass 27, count 0 2006.253.08:01:59.99#ibcon#read 5, iclass 27, count 0 2006.253.08:01:59.99#ibcon#about to read 6, iclass 27, count 0 2006.253.08:01:59.99#ibcon#read 6, iclass 27, count 0 2006.253.08:01:59.99#ibcon#end of sib2, iclass 27, count 0 2006.253.08:01:59.99#ibcon#*after write, iclass 27, count 0 2006.253.08:01:59.99#ibcon#*before return 0, iclass 27, count 0 2006.253.08:01:59.99#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.253.08:01:59.99#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.253.08:01:59.99#ibcon#about to clear, iclass 27 cls_cnt 0 2006.253.08:01:59.99#ibcon#cleared, iclass 27 cls_cnt 0 2006.253.08:01:59.99$vc4f8/valo=7,832.99 2006.253.08:01:59.99#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.253.08:01:59.99#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.253.08:01:59.99#ibcon#ireg 17 cls_cnt 0 2006.253.08:01:59.99#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.253.08:01:59.99#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.253.08:01:59.99#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.253.08:01:59.99#ibcon#enter wrdev, iclass 29, count 0 2006.253.08:01:59.99#ibcon#first serial, iclass 29, count 0 2006.253.08:01:59.99#ibcon#enter sib2, iclass 29, count 0 2006.253.08:01:59.99#ibcon#flushed, iclass 29, count 0 2006.253.08:01:59.99#ibcon#about to write, iclass 29, count 0 2006.253.08:01:59.99#ibcon#wrote, iclass 29, count 0 2006.253.08:01:59.99#ibcon#about to read 3, iclass 29, count 0 2006.253.08:02:00.01#ibcon#read 3, iclass 29, count 0 2006.253.08:02:00.01#ibcon#about to read 4, iclass 29, count 0 2006.253.08:02:00.01#ibcon#read 4, iclass 29, count 0 2006.253.08:02:00.01#ibcon#about to read 5, iclass 29, count 0 2006.253.08:02:00.01#ibcon#read 5, iclass 29, count 0 2006.253.08:02:00.01#ibcon#about to read 6, iclass 29, count 0 2006.253.08:02:00.01#ibcon#read 6, iclass 29, count 0 2006.253.08:02:00.01#ibcon#end of sib2, iclass 29, count 0 2006.253.08:02:00.01#ibcon#*mode == 0, iclass 29, count 0 2006.253.08:02:00.01#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.253.08:02:00.01#ibcon#[26=FRQ=07,832.99\r\n] 2006.253.08:02:00.01#ibcon#*before write, iclass 29, count 0 2006.253.08:02:00.01#ibcon#enter sib2, iclass 29, count 0 2006.253.08:02:00.01#ibcon#flushed, iclass 29, count 0 2006.253.08:02:00.01#ibcon#about to write, iclass 29, count 0 2006.253.08:02:00.01#ibcon#wrote, iclass 29, count 0 2006.253.08:02:00.01#ibcon#about to read 3, iclass 29, count 0 2006.253.08:02:00.05#ibcon#read 3, iclass 29, count 0 2006.253.08:02:00.05#ibcon#about to read 4, iclass 29, count 0 2006.253.08:02:00.05#ibcon#read 4, iclass 29, count 0 2006.253.08:02:00.05#ibcon#about to read 5, iclass 29, count 0 2006.253.08:02:00.05#ibcon#read 5, iclass 29, count 0 2006.253.08:02:00.05#ibcon#about to read 6, iclass 29, count 0 2006.253.08:02:00.05#ibcon#read 6, iclass 29, count 0 2006.253.08:02:00.05#ibcon#end of sib2, iclass 29, count 0 2006.253.08:02:00.05#ibcon#*after write, iclass 29, count 0 2006.253.08:02:00.05#ibcon#*before return 0, iclass 29, count 0 2006.253.08:02:00.05#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.253.08:02:00.05#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.253.08:02:00.05#ibcon#about to clear, iclass 29 cls_cnt 0 2006.253.08:02:00.05#ibcon#cleared, iclass 29 cls_cnt 0 2006.253.08:02:00.05$vc4f8/va=7,7 2006.253.08:02:00.05#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.253.08:02:00.05#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.253.08:02:00.05#ibcon#ireg 11 cls_cnt 2 2006.253.08:02:00.05#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.253.08:02:00.11#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.253.08:02:00.11#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.253.08:02:00.11#ibcon#enter wrdev, iclass 31, count 2 2006.253.08:02:00.11#ibcon#first serial, iclass 31, count 2 2006.253.08:02:00.11#ibcon#enter sib2, iclass 31, count 2 2006.253.08:02:00.11#ibcon#flushed, iclass 31, count 2 2006.253.08:02:00.11#ibcon#about to write, iclass 31, count 2 2006.253.08:02:00.11#ibcon#wrote, iclass 31, count 2 2006.253.08:02:00.11#ibcon#about to read 3, iclass 31, count 2 2006.253.08:02:00.13#ibcon#read 3, iclass 31, count 2 2006.253.08:02:00.13#ibcon#about to read 4, iclass 31, count 2 2006.253.08:02:00.13#ibcon#read 4, iclass 31, count 2 2006.253.08:02:00.13#ibcon#about to read 5, iclass 31, count 2 2006.253.08:02:00.13#ibcon#read 5, iclass 31, count 2 2006.253.08:02:00.13#ibcon#about to read 6, iclass 31, count 2 2006.253.08:02:00.13#ibcon#read 6, iclass 31, count 2 2006.253.08:02:00.13#ibcon#end of sib2, iclass 31, count 2 2006.253.08:02:00.13#ibcon#*mode == 0, iclass 31, count 2 2006.253.08:02:00.13#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.253.08:02:00.13#ibcon#[25=AT07-07\r\n] 2006.253.08:02:00.13#ibcon#*before write, iclass 31, count 2 2006.253.08:02:00.13#ibcon#enter sib2, iclass 31, count 2 2006.253.08:02:00.13#ibcon#flushed, iclass 31, count 2 2006.253.08:02:00.13#ibcon#about to write, iclass 31, count 2 2006.253.08:02:00.13#ibcon#wrote, iclass 31, count 2 2006.253.08:02:00.13#ibcon#about to read 3, iclass 31, count 2 2006.253.08:02:00.16#ibcon#read 3, iclass 31, count 2 2006.253.08:02:00.16#ibcon#about to read 4, iclass 31, count 2 2006.253.08:02:00.16#ibcon#read 4, iclass 31, count 2 2006.253.08:02:00.16#ibcon#about to read 5, iclass 31, count 2 2006.253.08:02:00.16#ibcon#read 5, iclass 31, count 2 2006.253.08:02:00.16#ibcon#about to read 6, iclass 31, count 2 2006.253.08:02:00.16#ibcon#read 6, iclass 31, count 2 2006.253.08:02:00.16#ibcon#end of sib2, iclass 31, count 2 2006.253.08:02:00.16#ibcon#*after write, iclass 31, count 2 2006.253.08:02:00.16#ibcon#*before return 0, iclass 31, count 2 2006.253.08:02:00.16#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.253.08:02:00.16#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.253.08:02:00.16#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.253.08:02:00.16#ibcon#ireg 7 cls_cnt 0 2006.253.08:02:00.16#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.253.08:02:00.28#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.253.08:02:00.28#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.253.08:02:00.28#ibcon#enter wrdev, iclass 31, count 0 2006.253.08:02:00.28#ibcon#first serial, iclass 31, count 0 2006.253.08:02:00.28#ibcon#enter sib2, iclass 31, count 0 2006.253.08:02:00.28#ibcon#flushed, iclass 31, count 0 2006.253.08:02:00.28#ibcon#about to write, iclass 31, count 0 2006.253.08:02:00.28#ibcon#wrote, iclass 31, count 0 2006.253.08:02:00.28#ibcon#about to read 3, iclass 31, count 0 2006.253.08:02:00.30#ibcon#read 3, iclass 31, count 0 2006.253.08:02:00.30#ibcon#about to read 4, iclass 31, count 0 2006.253.08:02:00.30#ibcon#read 4, iclass 31, count 0 2006.253.08:02:00.30#ibcon#about to read 5, iclass 31, count 0 2006.253.08:02:00.30#ibcon#read 5, iclass 31, count 0 2006.253.08:02:00.30#ibcon#about to read 6, iclass 31, count 0 2006.253.08:02:00.30#ibcon#read 6, iclass 31, count 0 2006.253.08:02:00.30#ibcon#end of sib2, iclass 31, count 0 2006.253.08:02:00.30#ibcon#*mode == 0, iclass 31, count 0 2006.253.08:02:00.30#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.253.08:02:00.30#ibcon#[25=USB\r\n] 2006.253.08:02:00.30#ibcon#*before write, iclass 31, count 0 2006.253.08:02:00.30#ibcon#enter sib2, iclass 31, count 0 2006.253.08:02:00.30#ibcon#flushed, iclass 31, count 0 2006.253.08:02:00.30#ibcon#about to write, iclass 31, count 0 2006.253.08:02:00.30#ibcon#wrote, iclass 31, count 0 2006.253.08:02:00.30#ibcon#about to read 3, iclass 31, count 0 2006.253.08:02:00.33#ibcon#read 3, iclass 31, count 0 2006.253.08:02:00.33#ibcon#about to read 4, iclass 31, count 0 2006.253.08:02:00.33#ibcon#read 4, iclass 31, count 0 2006.253.08:02:00.33#ibcon#about to read 5, iclass 31, count 0 2006.253.08:02:00.33#ibcon#read 5, iclass 31, count 0 2006.253.08:02:00.33#ibcon#about to read 6, iclass 31, count 0 2006.253.08:02:00.33#ibcon#read 6, iclass 31, count 0 2006.253.08:02:00.33#ibcon#end of sib2, iclass 31, count 0 2006.253.08:02:00.33#ibcon#*after write, iclass 31, count 0 2006.253.08:02:00.33#ibcon#*before return 0, iclass 31, count 0 2006.253.08:02:00.33#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.253.08:02:00.33#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.253.08:02:00.33#ibcon#about to clear, iclass 31 cls_cnt 0 2006.253.08:02:00.33#ibcon#cleared, iclass 31 cls_cnt 0 2006.253.08:02:00.33$vc4f8/valo=8,852.99 2006.253.08:02:00.33#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.253.08:02:00.33#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.253.08:02:00.33#ibcon#ireg 17 cls_cnt 0 2006.253.08:02:00.33#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.253.08:02:00.33#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.253.08:02:00.33#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.253.08:02:00.33#ibcon#enter wrdev, iclass 33, count 0 2006.253.08:02:00.33#ibcon#first serial, iclass 33, count 0 2006.253.08:02:00.33#ibcon#enter sib2, iclass 33, count 0 2006.253.08:02:00.33#ibcon#flushed, iclass 33, count 0 2006.253.08:02:00.33#ibcon#about to write, iclass 33, count 0 2006.253.08:02:00.33#ibcon#wrote, iclass 33, count 0 2006.253.08:02:00.33#ibcon#about to read 3, iclass 33, count 0 2006.253.08:02:00.35#ibcon#read 3, iclass 33, count 0 2006.253.08:02:00.35#ibcon#about to read 4, iclass 33, count 0 2006.253.08:02:00.35#ibcon#read 4, iclass 33, count 0 2006.253.08:02:00.35#ibcon#about to read 5, iclass 33, count 0 2006.253.08:02:00.35#ibcon#read 5, iclass 33, count 0 2006.253.08:02:00.35#ibcon#about to read 6, iclass 33, count 0 2006.253.08:02:00.35#ibcon#read 6, iclass 33, count 0 2006.253.08:02:00.35#ibcon#end of sib2, iclass 33, count 0 2006.253.08:02:00.35#ibcon#*mode == 0, iclass 33, count 0 2006.253.08:02:00.35#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.253.08:02:00.35#ibcon#[26=FRQ=08,852.99\r\n] 2006.253.08:02:00.35#ibcon#*before write, iclass 33, count 0 2006.253.08:02:00.35#ibcon#enter sib2, iclass 33, count 0 2006.253.08:02:00.35#ibcon#flushed, iclass 33, count 0 2006.253.08:02:00.35#ibcon#about to write, iclass 33, count 0 2006.253.08:02:00.35#ibcon#wrote, iclass 33, count 0 2006.253.08:02:00.35#ibcon#about to read 3, iclass 33, count 0 2006.253.08:02:00.39#ibcon#read 3, iclass 33, count 0 2006.253.08:02:00.39#ibcon#about to read 4, iclass 33, count 0 2006.253.08:02:00.39#ibcon#read 4, iclass 33, count 0 2006.253.08:02:00.39#ibcon#about to read 5, iclass 33, count 0 2006.253.08:02:00.39#ibcon#read 5, iclass 33, count 0 2006.253.08:02:00.39#ibcon#about to read 6, iclass 33, count 0 2006.253.08:02:00.39#ibcon#read 6, iclass 33, count 0 2006.253.08:02:00.39#ibcon#end of sib2, iclass 33, count 0 2006.253.08:02:00.39#ibcon#*after write, iclass 33, count 0 2006.253.08:02:00.39#ibcon#*before return 0, iclass 33, count 0 2006.253.08:02:00.39#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.253.08:02:00.39#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.253.08:02:00.39#ibcon#about to clear, iclass 33 cls_cnt 0 2006.253.08:02:00.39#ibcon#cleared, iclass 33 cls_cnt 0 2006.253.08:02:00.39$vc4f8/va=8,7 2006.253.08:02:00.39#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.253.08:02:00.39#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.253.08:02:00.39#ibcon#ireg 11 cls_cnt 2 2006.253.08:02:00.39#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.253.08:02:00.45#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.253.08:02:00.45#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.253.08:02:00.45#ibcon#enter wrdev, iclass 35, count 2 2006.253.08:02:00.45#ibcon#first serial, iclass 35, count 2 2006.253.08:02:00.45#ibcon#enter sib2, iclass 35, count 2 2006.253.08:02:00.45#ibcon#flushed, iclass 35, count 2 2006.253.08:02:00.45#ibcon#about to write, iclass 35, count 2 2006.253.08:02:00.45#ibcon#wrote, iclass 35, count 2 2006.253.08:02:00.45#ibcon#about to read 3, iclass 35, count 2 2006.253.08:02:00.47#ibcon#read 3, iclass 35, count 2 2006.253.08:02:00.47#ibcon#about to read 4, iclass 35, count 2 2006.253.08:02:00.47#ibcon#read 4, iclass 35, count 2 2006.253.08:02:00.47#ibcon#about to read 5, iclass 35, count 2 2006.253.08:02:00.47#ibcon#read 5, iclass 35, count 2 2006.253.08:02:00.47#ibcon#about to read 6, iclass 35, count 2 2006.253.08:02:00.47#ibcon#read 6, iclass 35, count 2 2006.253.08:02:00.47#ibcon#end of sib2, iclass 35, count 2 2006.253.08:02:00.47#ibcon#*mode == 0, iclass 35, count 2 2006.253.08:02:00.47#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.253.08:02:00.47#ibcon#[25=AT08-07\r\n] 2006.253.08:02:00.47#ibcon#*before write, iclass 35, count 2 2006.253.08:02:00.47#ibcon#enter sib2, iclass 35, count 2 2006.253.08:02:00.47#ibcon#flushed, iclass 35, count 2 2006.253.08:02:00.47#ibcon#about to write, iclass 35, count 2 2006.253.08:02:00.47#ibcon#wrote, iclass 35, count 2 2006.253.08:02:00.47#ibcon#about to read 3, iclass 35, count 2 2006.253.08:02:00.50#ibcon#read 3, iclass 35, count 2 2006.253.08:02:00.50#ibcon#about to read 4, iclass 35, count 2 2006.253.08:02:00.50#ibcon#read 4, iclass 35, count 2 2006.253.08:02:00.50#ibcon#about to read 5, iclass 35, count 2 2006.253.08:02:00.50#ibcon#read 5, iclass 35, count 2 2006.253.08:02:00.50#ibcon#about to read 6, iclass 35, count 2 2006.253.08:02:00.50#ibcon#read 6, iclass 35, count 2 2006.253.08:02:00.50#ibcon#end of sib2, iclass 35, count 2 2006.253.08:02:00.50#ibcon#*after write, iclass 35, count 2 2006.253.08:02:00.50#ibcon#*before return 0, iclass 35, count 2 2006.253.08:02:00.50#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.253.08:02:00.50#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.253.08:02:00.50#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.253.08:02:00.50#ibcon#ireg 7 cls_cnt 0 2006.253.08:02:00.50#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.253.08:02:00.62#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.253.08:02:00.62#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.253.08:02:00.62#ibcon#enter wrdev, iclass 35, count 0 2006.253.08:02:00.62#ibcon#first serial, iclass 35, count 0 2006.253.08:02:00.62#ibcon#enter sib2, iclass 35, count 0 2006.253.08:02:00.62#ibcon#flushed, iclass 35, count 0 2006.253.08:02:00.62#ibcon#about to write, iclass 35, count 0 2006.253.08:02:00.62#ibcon#wrote, iclass 35, count 0 2006.253.08:02:00.62#ibcon#about to read 3, iclass 35, count 0 2006.253.08:02:00.64#ibcon#read 3, iclass 35, count 0 2006.253.08:02:00.64#ibcon#about to read 4, iclass 35, count 0 2006.253.08:02:00.64#ibcon#read 4, iclass 35, count 0 2006.253.08:02:00.64#ibcon#about to read 5, iclass 35, count 0 2006.253.08:02:00.64#ibcon#read 5, iclass 35, count 0 2006.253.08:02:00.64#ibcon#about to read 6, iclass 35, count 0 2006.253.08:02:00.64#ibcon#read 6, iclass 35, count 0 2006.253.08:02:00.64#ibcon#end of sib2, iclass 35, count 0 2006.253.08:02:00.64#ibcon#*mode == 0, iclass 35, count 0 2006.253.08:02:00.64#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.253.08:02:00.64#ibcon#[25=USB\r\n] 2006.253.08:02:00.64#ibcon#*before write, iclass 35, count 0 2006.253.08:02:00.64#ibcon#enter sib2, iclass 35, count 0 2006.253.08:02:00.64#ibcon#flushed, iclass 35, count 0 2006.253.08:02:00.64#ibcon#about to write, iclass 35, count 0 2006.253.08:02:00.64#ibcon#wrote, iclass 35, count 0 2006.253.08:02:00.64#ibcon#about to read 3, iclass 35, count 0 2006.253.08:02:00.67#ibcon#read 3, iclass 35, count 0 2006.253.08:02:00.67#ibcon#about to read 4, iclass 35, count 0 2006.253.08:02:00.67#ibcon#read 4, iclass 35, count 0 2006.253.08:02:00.67#ibcon#about to read 5, iclass 35, count 0 2006.253.08:02:00.67#ibcon#read 5, iclass 35, count 0 2006.253.08:02:00.67#ibcon#about to read 6, iclass 35, count 0 2006.253.08:02:00.67#ibcon#read 6, iclass 35, count 0 2006.253.08:02:00.67#ibcon#end of sib2, iclass 35, count 0 2006.253.08:02:00.67#ibcon#*after write, iclass 35, count 0 2006.253.08:02:00.67#ibcon#*before return 0, iclass 35, count 0 2006.253.08:02:00.67#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.253.08:02:00.67#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.253.08:02:00.67#ibcon#about to clear, iclass 35 cls_cnt 0 2006.253.08:02:00.67#ibcon#cleared, iclass 35 cls_cnt 0 2006.253.08:02:00.67$vc4f8/vblo=1,632.99 2006.253.08:02:00.67#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.253.08:02:00.67#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.253.08:02:00.67#ibcon#ireg 17 cls_cnt 0 2006.253.08:02:00.67#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.253.08:02:00.67#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.253.08:02:00.67#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.253.08:02:00.67#ibcon#enter wrdev, iclass 37, count 0 2006.253.08:02:00.67#ibcon#first serial, iclass 37, count 0 2006.253.08:02:00.67#ibcon#enter sib2, iclass 37, count 0 2006.253.08:02:00.67#ibcon#flushed, iclass 37, count 0 2006.253.08:02:00.67#ibcon#about to write, iclass 37, count 0 2006.253.08:02:00.67#ibcon#wrote, iclass 37, count 0 2006.253.08:02:00.67#ibcon#about to read 3, iclass 37, count 0 2006.253.08:02:00.70#ibcon#read 3, iclass 37, count 0 2006.253.08:02:00.70#ibcon#about to read 4, iclass 37, count 0 2006.253.08:02:00.70#ibcon#read 4, iclass 37, count 0 2006.253.08:02:00.70#ibcon#about to read 5, iclass 37, count 0 2006.253.08:02:00.70#ibcon#read 5, iclass 37, count 0 2006.253.08:02:00.70#ibcon#about to read 6, iclass 37, count 0 2006.253.08:02:00.70#ibcon#read 6, iclass 37, count 0 2006.253.08:02:00.70#ibcon#end of sib2, iclass 37, count 0 2006.253.08:02:00.70#ibcon#*mode == 0, iclass 37, count 0 2006.253.08:02:00.70#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.253.08:02:00.70#ibcon#[28=FRQ=01,632.99\r\n] 2006.253.08:02:00.70#ibcon#*before write, iclass 37, count 0 2006.253.08:02:00.70#ibcon#enter sib2, iclass 37, count 0 2006.253.08:02:00.70#ibcon#flushed, iclass 37, count 0 2006.253.08:02:00.70#ibcon#about to write, iclass 37, count 0 2006.253.08:02:00.70#ibcon#wrote, iclass 37, count 0 2006.253.08:02:00.70#ibcon#about to read 3, iclass 37, count 0 2006.253.08:02:00.74#ibcon#read 3, iclass 37, count 0 2006.253.08:02:00.74#ibcon#about to read 4, iclass 37, count 0 2006.253.08:02:00.74#ibcon#read 4, iclass 37, count 0 2006.253.08:02:00.74#ibcon#about to read 5, iclass 37, count 0 2006.253.08:02:00.74#ibcon#read 5, iclass 37, count 0 2006.253.08:02:00.74#ibcon#about to read 6, iclass 37, count 0 2006.253.08:02:00.74#ibcon#read 6, iclass 37, count 0 2006.253.08:02:00.74#ibcon#end of sib2, iclass 37, count 0 2006.253.08:02:00.74#ibcon#*after write, iclass 37, count 0 2006.253.08:02:00.74#ibcon#*before return 0, iclass 37, count 0 2006.253.08:02:00.74#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.253.08:02:00.74#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.253.08:02:00.74#ibcon#about to clear, iclass 37 cls_cnt 0 2006.253.08:02:00.74#ibcon#cleared, iclass 37 cls_cnt 0 2006.253.08:02:00.74$vc4f8/vb=1,4 2006.253.08:02:00.74#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.253.08:02:00.74#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.253.08:02:00.74#ibcon#ireg 11 cls_cnt 2 2006.253.08:02:00.74#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.253.08:02:00.74#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.253.08:02:00.74#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.253.08:02:00.74#ibcon#enter wrdev, iclass 39, count 2 2006.253.08:02:00.74#ibcon#first serial, iclass 39, count 2 2006.253.08:02:00.74#ibcon#enter sib2, iclass 39, count 2 2006.253.08:02:00.74#ibcon#flushed, iclass 39, count 2 2006.253.08:02:00.74#ibcon#about to write, iclass 39, count 2 2006.253.08:02:00.74#ibcon#wrote, iclass 39, count 2 2006.253.08:02:00.74#ibcon#about to read 3, iclass 39, count 2 2006.253.08:02:00.76#ibcon#read 3, iclass 39, count 2 2006.253.08:02:00.76#ibcon#about to read 4, iclass 39, count 2 2006.253.08:02:00.76#ibcon#read 4, iclass 39, count 2 2006.253.08:02:00.76#ibcon#about to read 5, iclass 39, count 2 2006.253.08:02:00.76#ibcon#read 5, iclass 39, count 2 2006.253.08:02:00.76#ibcon#about to read 6, iclass 39, count 2 2006.253.08:02:00.76#ibcon#read 6, iclass 39, count 2 2006.253.08:02:00.76#ibcon#end of sib2, iclass 39, count 2 2006.253.08:02:00.76#ibcon#*mode == 0, iclass 39, count 2 2006.253.08:02:00.76#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.253.08:02:00.76#ibcon#[27=AT01-04\r\n] 2006.253.08:02:00.76#ibcon#*before write, iclass 39, count 2 2006.253.08:02:00.76#ibcon#enter sib2, iclass 39, count 2 2006.253.08:02:00.76#ibcon#flushed, iclass 39, count 2 2006.253.08:02:00.76#ibcon#about to write, iclass 39, count 2 2006.253.08:02:00.76#ibcon#wrote, iclass 39, count 2 2006.253.08:02:00.76#ibcon#about to read 3, iclass 39, count 2 2006.253.08:02:00.79#ibcon#read 3, iclass 39, count 2 2006.253.08:02:00.79#ibcon#about to read 4, iclass 39, count 2 2006.253.08:02:00.79#ibcon#read 4, iclass 39, count 2 2006.253.08:02:00.79#ibcon#about to read 5, iclass 39, count 2 2006.253.08:02:00.79#ibcon#read 5, iclass 39, count 2 2006.253.08:02:00.79#ibcon#about to read 6, iclass 39, count 2 2006.253.08:02:00.79#ibcon#read 6, iclass 39, count 2 2006.253.08:02:00.79#ibcon#end of sib2, iclass 39, count 2 2006.253.08:02:00.79#ibcon#*after write, iclass 39, count 2 2006.253.08:02:00.79#ibcon#*before return 0, iclass 39, count 2 2006.253.08:02:00.79#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.253.08:02:00.79#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.253.08:02:00.79#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.253.08:02:00.79#ibcon#ireg 7 cls_cnt 0 2006.253.08:02:00.79#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.253.08:02:00.91#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.253.08:02:00.91#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.253.08:02:00.91#ibcon#enter wrdev, iclass 39, count 0 2006.253.08:02:00.91#ibcon#first serial, iclass 39, count 0 2006.253.08:02:00.91#ibcon#enter sib2, iclass 39, count 0 2006.253.08:02:00.91#ibcon#flushed, iclass 39, count 0 2006.253.08:02:00.91#ibcon#about to write, iclass 39, count 0 2006.253.08:02:00.91#ibcon#wrote, iclass 39, count 0 2006.253.08:02:00.91#ibcon#about to read 3, iclass 39, count 0 2006.253.08:02:00.93#ibcon#read 3, iclass 39, count 0 2006.253.08:02:00.93#ibcon#about to read 4, iclass 39, count 0 2006.253.08:02:00.93#ibcon#read 4, iclass 39, count 0 2006.253.08:02:00.93#ibcon#about to read 5, iclass 39, count 0 2006.253.08:02:00.93#ibcon#read 5, iclass 39, count 0 2006.253.08:02:00.93#ibcon#about to read 6, iclass 39, count 0 2006.253.08:02:00.93#ibcon#read 6, iclass 39, count 0 2006.253.08:02:00.93#ibcon#end of sib2, iclass 39, count 0 2006.253.08:02:00.93#ibcon#*mode == 0, iclass 39, count 0 2006.253.08:02:00.93#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.253.08:02:00.93#ibcon#[27=USB\r\n] 2006.253.08:02:00.93#ibcon#*before write, iclass 39, count 0 2006.253.08:02:00.93#ibcon#enter sib2, iclass 39, count 0 2006.253.08:02:00.93#ibcon#flushed, iclass 39, count 0 2006.253.08:02:00.93#ibcon#about to write, iclass 39, count 0 2006.253.08:02:00.93#ibcon#wrote, iclass 39, count 0 2006.253.08:02:00.93#ibcon#about to read 3, iclass 39, count 0 2006.253.08:02:00.96#ibcon#read 3, iclass 39, count 0 2006.253.08:02:00.96#ibcon#about to read 4, iclass 39, count 0 2006.253.08:02:00.96#ibcon#read 4, iclass 39, count 0 2006.253.08:02:00.96#ibcon#about to read 5, iclass 39, count 0 2006.253.08:02:00.96#ibcon#read 5, iclass 39, count 0 2006.253.08:02:00.96#ibcon#about to read 6, iclass 39, count 0 2006.253.08:02:00.96#ibcon#read 6, iclass 39, count 0 2006.253.08:02:00.96#ibcon#end of sib2, iclass 39, count 0 2006.253.08:02:00.96#ibcon#*after write, iclass 39, count 0 2006.253.08:02:00.96#ibcon#*before return 0, iclass 39, count 0 2006.253.08:02:00.96#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.253.08:02:00.96#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.253.08:02:00.96#ibcon#about to clear, iclass 39 cls_cnt 0 2006.253.08:02:00.96#ibcon#cleared, iclass 39 cls_cnt 0 2006.253.08:02:00.96$vc4f8/vblo=2,640.99 2006.253.08:02:00.96#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.253.08:02:00.96#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.253.08:02:00.96#ibcon#ireg 17 cls_cnt 0 2006.253.08:02:00.96#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.253.08:02:00.96#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.253.08:02:00.96#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.253.08:02:00.96#ibcon#enter wrdev, iclass 3, count 0 2006.253.08:02:00.96#ibcon#first serial, iclass 3, count 0 2006.253.08:02:00.96#ibcon#enter sib2, iclass 3, count 0 2006.253.08:02:00.96#ibcon#flushed, iclass 3, count 0 2006.253.08:02:00.96#ibcon#about to write, iclass 3, count 0 2006.253.08:02:00.96#ibcon#wrote, iclass 3, count 0 2006.253.08:02:00.96#ibcon#about to read 3, iclass 3, count 0 2006.253.08:02:00.98#ibcon#read 3, iclass 3, count 0 2006.253.08:02:00.98#ibcon#about to read 4, iclass 3, count 0 2006.253.08:02:00.98#ibcon#read 4, iclass 3, count 0 2006.253.08:02:00.98#ibcon#about to read 5, iclass 3, count 0 2006.253.08:02:00.98#ibcon#read 5, iclass 3, count 0 2006.253.08:02:00.98#ibcon#about to read 6, iclass 3, count 0 2006.253.08:02:00.98#ibcon#read 6, iclass 3, count 0 2006.253.08:02:00.98#ibcon#end of sib2, iclass 3, count 0 2006.253.08:02:00.98#ibcon#*mode == 0, iclass 3, count 0 2006.253.08:02:00.98#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.253.08:02:00.98#ibcon#[28=FRQ=02,640.99\r\n] 2006.253.08:02:00.98#ibcon#*before write, iclass 3, count 0 2006.253.08:02:00.98#ibcon#enter sib2, iclass 3, count 0 2006.253.08:02:00.98#ibcon#flushed, iclass 3, count 0 2006.253.08:02:00.98#ibcon#about to write, iclass 3, count 0 2006.253.08:02:00.98#ibcon#wrote, iclass 3, count 0 2006.253.08:02:00.98#ibcon#about to read 3, iclass 3, count 0 2006.253.08:02:01.02#ibcon#read 3, iclass 3, count 0 2006.253.08:02:01.02#ibcon#about to read 4, iclass 3, count 0 2006.253.08:02:01.02#ibcon#read 4, iclass 3, count 0 2006.253.08:02:01.02#ibcon#about to read 5, iclass 3, count 0 2006.253.08:02:01.02#ibcon#read 5, iclass 3, count 0 2006.253.08:02:01.02#ibcon#about to read 6, iclass 3, count 0 2006.253.08:02:01.02#ibcon#read 6, iclass 3, count 0 2006.253.08:02:01.02#ibcon#end of sib2, iclass 3, count 0 2006.253.08:02:01.02#ibcon#*after write, iclass 3, count 0 2006.253.08:02:01.02#ibcon#*before return 0, iclass 3, count 0 2006.253.08:02:01.02#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.253.08:02:01.02#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.253.08:02:01.02#ibcon#about to clear, iclass 3 cls_cnt 0 2006.253.08:02:01.02#ibcon#cleared, iclass 3 cls_cnt 0 2006.253.08:02:01.02$vc4f8/vb=2,5 2006.253.08:02:01.02#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.253.08:02:01.02#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.253.08:02:01.02#ibcon#ireg 11 cls_cnt 2 2006.253.08:02:01.02#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.253.08:02:01.08#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.253.08:02:01.08#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.253.08:02:01.08#ibcon#enter wrdev, iclass 5, count 2 2006.253.08:02:01.08#ibcon#first serial, iclass 5, count 2 2006.253.08:02:01.08#ibcon#enter sib2, iclass 5, count 2 2006.253.08:02:01.08#ibcon#flushed, iclass 5, count 2 2006.253.08:02:01.08#ibcon#about to write, iclass 5, count 2 2006.253.08:02:01.08#ibcon#wrote, iclass 5, count 2 2006.253.08:02:01.08#ibcon#about to read 3, iclass 5, count 2 2006.253.08:02:01.10#ibcon#read 3, iclass 5, count 2 2006.253.08:02:01.10#ibcon#about to read 4, iclass 5, count 2 2006.253.08:02:01.10#ibcon#read 4, iclass 5, count 2 2006.253.08:02:01.10#ibcon#about to read 5, iclass 5, count 2 2006.253.08:02:01.10#ibcon#read 5, iclass 5, count 2 2006.253.08:02:01.10#ibcon#about to read 6, iclass 5, count 2 2006.253.08:02:01.10#ibcon#read 6, iclass 5, count 2 2006.253.08:02:01.10#ibcon#end of sib2, iclass 5, count 2 2006.253.08:02:01.10#ibcon#*mode == 0, iclass 5, count 2 2006.253.08:02:01.10#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.253.08:02:01.10#ibcon#[27=AT02-05\r\n] 2006.253.08:02:01.10#ibcon#*before write, iclass 5, count 2 2006.253.08:02:01.10#ibcon#enter sib2, iclass 5, count 2 2006.253.08:02:01.10#ibcon#flushed, iclass 5, count 2 2006.253.08:02:01.10#ibcon#about to write, iclass 5, count 2 2006.253.08:02:01.10#ibcon#wrote, iclass 5, count 2 2006.253.08:02:01.10#ibcon#about to read 3, iclass 5, count 2 2006.253.08:02:01.13#ibcon#read 3, iclass 5, count 2 2006.253.08:02:01.13#ibcon#about to read 4, iclass 5, count 2 2006.253.08:02:01.13#ibcon#read 4, iclass 5, count 2 2006.253.08:02:01.13#ibcon#about to read 5, iclass 5, count 2 2006.253.08:02:01.13#ibcon#read 5, iclass 5, count 2 2006.253.08:02:01.13#ibcon#about to read 6, iclass 5, count 2 2006.253.08:02:01.13#ibcon#read 6, iclass 5, count 2 2006.253.08:02:01.13#ibcon#end of sib2, iclass 5, count 2 2006.253.08:02:01.13#ibcon#*after write, iclass 5, count 2 2006.253.08:02:01.13#ibcon#*before return 0, iclass 5, count 2 2006.253.08:02:01.13#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.253.08:02:01.13#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.253.08:02:01.13#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.253.08:02:01.13#ibcon#ireg 7 cls_cnt 0 2006.253.08:02:01.13#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.253.08:02:01.25#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.253.08:02:01.25#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.253.08:02:01.25#ibcon#enter wrdev, iclass 5, count 0 2006.253.08:02:01.25#ibcon#first serial, iclass 5, count 0 2006.253.08:02:01.25#ibcon#enter sib2, iclass 5, count 0 2006.253.08:02:01.25#ibcon#flushed, iclass 5, count 0 2006.253.08:02:01.25#ibcon#about to write, iclass 5, count 0 2006.253.08:02:01.25#ibcon#wrote, iclass 5, count 0 2006.253.08:02:01.25#ibcon#about to read 3, iclass 5, count 0 2006.253.08:02:01.27#ibcon#read 3, iclass 5, count 0 2006.253.08:02:01.27#ibcon#about to read 4, iclass 5, count 0 2006.253.08:02:01.27#ibcon#read 4, iclass 5, count 0 2006.253.08:02:01.27#ibcon#about to read 5, iclass 5, count 0 2006.253.08:02:01.27#ibcon#read 5, iclass 5, count 0 2006.253.08:02:01.27#ibcon#about to read 6, iclass 5, count 0 2006.253.08:02:01.27#ibcon#read 6, iclass 5, count 0 2006.253.08:02:01.27#ibcon#end of sib2, iclass 5, count 0 2006.253.08:02:01.27#ibcon#*mode == 0, iclass 5, count 0 2006.253.08:02:01.27#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.253.08:02:01.27#ibcon#[27=USB\r\n] 2006.253.08:02:01.27#ibcon#*before write, iclass 5, count 0 2006.253.08:02:01.27#ibcon#enter sib2, iclass 5, count 0 2006.253.08:02:01.27#ibcon#flushed, iclass 5, count 0 2006.253.08:02:01.27#ibcon#about to write, iclass 5, count 0 2006.253.08:02:01.27#ibcon#wrote, iclass 5, count 0 2006.253.08:02:01.27#ibcon#about to read 3, iclass 5, count 0 2006.253.08:02:01.30#ibcon#read 3, iclass 5, count 0 2006.253.08:02:01.30#ibcon#about to read 4, iclass 5, count 0 2006.253.08:02:01.30#ibcon#read 4, iclass 5, count 0 2006.253.08:02:01.30#ibcon#about to read 5, iclass 5, count 0 2006.253.08:02:01.30#ibcon#read 5, iclass 5, count 0 2006.253.08:02:01.30#ibcon#about to read 6, iclass 5, count 0 2006.253.08:02:01.30#ibcon#read 6, iclass 5, count 0 2006.253.08:02:01.30#ibcon#end of sib2, iclass 5, count 0 2006.253.08:02:01.30#ibcon#*after write, iclass 5, count 0 2006.253.08:02:01.30#ibcon#*before return 0, iclass 5, count 0 2006.253.08:02:01.30#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.253.08:02:01.30#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.253.08:02:01.30#ibcon#about to clear, iclass 5 cls_cnt 0 2006.253.08:02:01.30#ibcon#cleared, iclass 5 cls_cnt 0 2006.253.08:02:01.30$vc4f8/vblo=3,656.99 2006.253.08:02:01.30#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.253.08:02:01.30#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.253.08:02:01.30#ibcon#ireg 17 cls_cnt 0 2006.253.08:02:01.30#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.253.08:02:01.30#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.253.08:02:01.30#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.253.08:02:01.30#ibcon#enter wrdev, iclass 7, count 0 2006.253.08:02:01.30#ibcon#first serial, iclass 7, count 0 2006.253.08:02:01.30#ibcon#enter sib2, iclass 7, count 0 2006.253.08:02:01.30#ibcon#flushed, iclass 7, count 0 2006.253.08:02:01.30#ibcon#about to write, iclass 7, count 0 2006.253.08:02:01.30#ibcon#wrote, iclass 7, count 0 2006.253.08:02:01.30#ibcon#about to read 3, iclass 7, count 0 2006.253.08:02:01.32#ibcon#read 3, iclass 7, count 0 2006.253.08:02:01.32#ibcon#about to read 4, iclass 7, count 0 2006.253.08:02:01.32#ibcon#read 4, iclass 7, count 0 2006.253.08:02:01.32#ibcon#about to read 5, iclass 7, count 0 2006.253.08:02:01.32#ibcon#read 5, iclass 7, count 0 2006.253.08:02:01.32#ibcon#about to read 6, iclass 7, count 0 2006.253.08:02:01.32#ibcon#read 6, iclass 7, count 0 2006.253.08:02:01.32#ibcon#end of sib2, iclass 7, count 0 2006.253.08:02:01.32#ibcon#*mode == 0, iclass 7, count 0 2006.253.08:02:01.32#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.253.08:02:01.32#ibcon#[28=FRQ=03,656.99\r\n] 2006.253.08:02:01.32#ibcon#*before write, iclass 7, count 0 2006.253.08:02:01.32#ibcon#enter sib2, iclass 7, count 0 2006.253.08:02:01.32#ibcon#flushed, iclass 7, count 0 2006.253.08:02:01.32#ibcon#about to write, iclass 7, count 0 2006.253.08:02:01.32#ibcon#wrote, iclass 7, count 0 2006.253.08:02:01.32#ibcon#about to read 3, iclass 7, count 0 2006.253.08:02:01.36#ibcon#read 3, iclass 7, count 0 2006.253.08:02:01.36#ibcon#about to read 4, iclass 7, count 0 2006.253.08:02:01.36#ibcon#read 4, iclass 7, count 0 2006.253.08:02:01.36#ibcon#about to read 5, iclass 7, count 0 2006.253.08:02:01.36#ibcon#read 5, iclass 7, count 0 2006.253.08:02:01.36#ibcon#about to read 6, iclass 7, count 0 2006.253.08:02:01.36#ibcon#read 6, iclass 7, count 0 2006.253.08:02:01.36#ibcon#end of sib2, iclass 7, count 0 2006.253.08:02:01.36#ibcon#*after write, iclass 7, count 0 2006.253.08:02:01.36#ibcon#*before return 0, iclass 7, count 0 2006.253.08:02:01.36#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.253.08:02:01.36#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.253.08:02:01.36#ibcon#about to clear, iclass 7 cls_cnt 0 2006.253.08:02:01.36#ibcon#cleared, iclass 7 cls_cnt 0 2006.253.08:02:01.36$vc4f8/vb=3,4 2006.253.08:02:01.36#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.253.08:02:01.36#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.253.08:02:01.36#ibcon#ireg 11 cls_cnt 2 2006.253.08:02:01.36#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.253.08:02:01.42#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.253.08:02:01.42#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.253.08:02:01.42#ibcon#enter wrdev, iclass 11, count 2 2006.253.08:02:01.42#ibcon#first serial, iclass 11, count 2 2006.253.08:02:01.42#ibcon#enter sib2, iclass 11, count 2 2006.253.08:02:01.42#ibcon#flushed, iclass 11, count 2 2006.253.08:02:01.42#ibcon#about to write, iclass 11, count 2 2006.253.08:02:01.42#ibcon#wrote, iclass 11, count 2 2006.253.08:02:01.42#ibcon#about to read 3, iclass 11, count 2 2006.253.08:02:01.44#ibcon#read 3, iclass 11, count 2 2006.253.08:02:01.44#ibcon#about to read 4, iclass 11, count 2 2006.253.08:02:01.44#ibcon#read 4, iclass 11, count 2 2006.253.08:02:01.44#ibcon#about to read 5, iclass 11, count 2 2006.253.08:02:01.44#ibcon#read 5, iclass 11, count 2 2006.253.08:02:01.44#ibcon#about to read 6, iclass 11, count 2 2006.253.08:02:01.44#ibcon#read 6, iclass 11, count 2 2006.253.08:02:01.44#ibcon#end of sib2, iclass 11, count 2 2006.253.08:02:01.44#ibcon#*mode == 0, iclass 11, count 2 2006.253.08:02:01.44#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.253.08:02:01.44#ibcon#[27=AT03-04\r\n] 2006.253.08:02:01.44#ibcon#*before write, iclass 11, count 2 2006.253.08:02:01.44#ibcon#enter sib2, iclass 11, count 2 2006.253.08:02:01.44#ibcon#flushed, iclass 11, count 2 2006.253.08:02:01.44#ibcon#about to write, iclass 11, count 2 2006.253.08:02:01.44#ibcon#wrote, iclass 11, count 2 2006.253.08:02:01.44#ibcon#about to read 3, iclass 11, count 2 2006.253.08:02:01.47#ibcon#read 3, iclass 11, count 2 2006.253.08:02:01.47#ibcon#about to read 4, iclass 11, count 2 2006.253.08:02:01.47#ibcon#read 4, iclass 11, count 2 2006.253.08:02:01.47#ibcon#about to read 5, iclass 11, count 2 2006.253.08:02:01.47#ibcon#read 5, iclass 11, count 2 2006.253.08:02:01.47#ibcon#about to read 6, iclass 11, count 2 2006.253.08:02:01.47#ibcon#read 6, iclass 11, count 2 2006.253.08:02:01.47#ibcon#end of sib2, iclass 11, count 2 2006.253.08:02:01.47#ibcon#*after write, iclass 11, count 2 2006.253.08:02:01.47#ibcon#*before return 0, iclass 11, count 2 2006.253.08:02:01.47#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.253.08:02:01.47#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.253.08:02:01.47#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.253.08:02:01.47#ibcon#ireg 7 cls_cnt 0 2006.253.08:02:01.47#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.253.08:02:01.59#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.253.08:02:01.59#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.253.08:02:01.59#ibcon#enter wrdev, iclass 11, count 0 2006.253.08:02:01.59#ibcon#first serial, iclass 11, count 0 2006.253.08:02:01.59#ibcon#enter sib2, iclass 11, count 0 2006.253.08:02:01.59#ibcon#flushed, iclass 11, count 0 2006.253.08:02:01.59#ibcon#about to write, iclass 11, count 0 2006.253.08:02:01.59#ibcon#wrote, iclass 11, count 0 2006.253.08:02:01.59#ibcon#about to read 3, iclass 11, count 0 2006.253.08:02:01.61#ibcon#read 3, iclass 11, count 0 2006.253.08:02:01.61#ibcon#about to read 4, iclass 11, count 0 2006.253.08:02:01.61#ibcon#read 4, iclass 11, count 0 2006.253.08:02:01.61#ibcon#about to read 5, iclass 11, count 0 2006.253.08:02:01.61#ibcon#read 5, iclass 11, count 0 2006.253.08:02:01.61#ibcon#about to read 6, iclass 11, count 0 2006.253.08:02:01.61#ibcon#read 6, iclass 11, count 0 2006.253.08:02:01.61#ibcon#end of sib2, iclass 11, count 0 2006.253.08:02:01.61#ibcon#*mode == 0, iclass 11, count 0 2006.253.08:02:01.61#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.253.08:02:01.61#ibcon#[27=USB\r\n] 2006.253.08:02:01.61#ibcon#*before write, iclass 11, count 0 2006.253.08:02:01.61#ibcon#enter sib2, iclass 11, count 0 2006.253.08:02:01.61#ibcon#flushed, iclass 11, count 0 2006.253.08:02:01.61#ibcon#about to write, iclass 11, count 0 2006.253.08:02:01.61#ibcon#wrote, iclass 11, count 0 2006.253.08:02:01.61#ibcon#about to read 3, iclass 11, count 0 2006.253.08:02:01.64#ibcon#read 3, iclass 11, count 0 2006.253.08:02:01.64#ibcon#about to read 4, iclass 11, count 0 2006.253.08:02:01.64#ibcon#read 4, iclass 11, count 0 2006.253.08:02:01.64#ibcon#about to read 5, iclass 11, count 0 2006.253.08:02:01.64#ibcon#read 5, iclass 11, count 0 2006.253.08:02:01.64#ibcon#about to read 6, iclass 11, count 0 2006.253.08:02:01.64#ibcon#read 6, iclass 11, count 0 2006.253.08:02:01.64#ibcon#end of sib2, iclass 11, count 0 2006.253.08:02:01.64#ibcon#*after write, iclass 11, count 0 2006.253.08:02:01.64#ibcon#*before return 0, iclass 11, count 0 2006.253.08:02:01.64#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.253.08:02:01.64#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.253.08:02:01.64#ibcon#about to clear, iclass 11 cls_cnt 0 2006.253.08:02:01.64#ibcon#cleared, iclass 11 cls_cnt 0 2006.253.08:02:01.64$vc4f8/vblo=4,712.99 2006.253.08:02:01.64#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.253.08:02:01.64#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.253.08:02:01.64#ibcon#ireg 17 cls_cnt 0 2006.253.08:02:01.64#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.253.08:02:01.64#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.253.08:02:01.64#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.253.08:02:01.64#ibcon#enter wrdev, iclass 13, count 0 2006.253.08:02:01.64#ibcon#first serial, iclass 13, count 0 2006.253.08:02:01.64#ibcon#enter sib2, iclass 13, count 0 2006.253.08:02:01.64#ibcon#flushed, iclass 13, count 0 2006.253.08:02:01.64#ibcon#about to write, iclass 13, count 0 2006.253.08:02:01.64#ibcon#wrote, iclass 13, count 0 2006.253.08:02:01.64#ibcon#about to read 3, iclass 13, count 0 2006.253.08:02:01.66#ibcon#read 3, iclass 13, count 0 2006.253.08:02:01.66#ibcon#about to read 4, iclass 13, count 0 2006.253.08:02:01.66#ibcon#read 4, iclass 13, count 0 2006.253.08:02:01.66#ibcon#about to read 5, iclass 13, count 0 2006.253.08:02:01.66#ibcon#read 5, iclass 13, count 0 2006.253.08:02:01.66#ibcon#about to read 6, iclass 13, count 0 2006.253.08:02:01.66#ibcon#read 6, iclass 13, count 0 2006.253.08:02:01.66#ibcon#end of sib2, iclass 13, count 0 2006.253.08:02:01.66#ibcon#*mode == 0, iclass 13, count 0 2006.253.08:02:01.66#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.253.08:02:01.66#ibcon#[28=FRQ=04,712.99\r\n] 2006.253.08:02:01.66#ibcon#*before write, iclass 13, count 0 2006.253.08:02:01.66#ibcon#enter sib2, iclass 13, count 0 2006.253.08:02:01.66#ibcon#flushed, iclass 13, count 0 2006.253.08:02:01.66#ibcon#about to write, iclass 13, count 0 2006.253.08:02:01.66#ibcon#wrote, iclass 13, count 0 2006.253.08:02:01.66#ibcon#about to read 3, iclass 13, count 0 2006.253.08:02:01.70#ibcon#read 3, iclass 13, count 0 2006.253.08:02:01.70#ibcon#about to read 4, iclass 13, count 0 2006.253.08:02:01.70#ibcon#read 4, iclass 13, count 0 2006.253.08:02:01.70#ibcon#about to read 5, iclass 13, count 0 2006.253.08:02:01.70#ibcon#read 5, iclass 13, count 0 2006.253.08:02:01.70#ibcon#about to read 6, iclass 13, count 0 2006.253.08:02:01.70#ibcon#read 6, iclass 13, count 0 2006.253.08:02:01.70#ibcon#end of sib2, iclass 13, count 0 2006.253.08:02:01.70#ibcon#*after write, iclass 13, count 0 2006.253.08:02:01.70#ibcon#*before return 0, iclass 13, count 0 2006.253.08:02:01.70#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.253.08:02:01.70#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.253.08:02:01.70#ibcon#about to clear, iclass 13 cls_cnt 0 2006.253.08:02:01.70#ibcon#cleared, iclass 13 cls_cnt 0 2006.253.08:02:01.70$vc4f8/vb=4,4 2006.253.08:02:01.70#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.253.08:02:01.70#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.253.08:02:01.70#ibcon#ireg 11 cls_cnt 2 2006.253.08:02:01.70#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.253.08:02:01.76#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.253.08:02:01.76#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.253.08:02:01.76#ibcon#enter wrdev, iclass 15, count 2 2006.253.08:02:01.76#ibcon#first serial, iclass 15, count 2 2006.253.08:02:01.76#ibcon#enter sib2, iclass 15, count 2 2006.253.08:02:01.76#ibcon#flushed, iclass 15, count 2 2006.253.08:02:01.76#ibcon#about to write, iclass 15, count 2 2006.253.08:02:01.76#ibcon#wrote, iclass 15, count 2 2006.253.08:02:01.76#ibcon#about to read 3, iclass 15, count 2 2006.253.08:02:01.78#ibcon#read 3, iclass 15, count 2 2006.253.08:02:01.78#ibcon#about to read 4, iclass 15, count 2 2006.253.08:02:01.78#ibcon#read 4, iclass 15, count 2 2006.253.08:02:01.78#ibcon#about to read 5, iclass 15, count 2 2006.253.08:02:01.78#ibcon#read 5, iclass 15, count 2 2006.253.08:02:01.78#ibcon#about to read 6, iclass 15, count 2 2006.253.08:02:01.78#ibcon#read 6, iclass 15, count 2 2006.253.08:02:01.78#ibcon#end of sib2, iclass 15, count 2 2006.253.08:02:01.78#ibcon#*mode == 0, iclass 15, count 2 2006.253.08:02:01.78#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.253.08:02:01.78#ibcon#[27=AT04-04\r\n] 2006.253.08:02:01.78#ibcon#*before write, iclass 15, count 2 2006.253.08:02:01.78#ibcon#enter sib2, iclass 15, count 2 2006.253.08:02:01.78#ibcon#flushed, iclass 15, count 2 2006.253.08:02:01.78#ibcon#about to write, iclass 15, count 2 2006.253.08:02:01.78#ibcon#wrote, iclass 15, count 2 2006.253.08:02:01.78#ibcon#about to read 3, iclass 15, count 2 2006.253.08:02:01.81#ibcon#read 3, iclass 15, count 2 2006.253.08:02:01.81#ibcon#about to read 4, iclass 15, count 2 2006.253.08:02:01.81#ibcon#read 4, iclass 15, count 2 2006.253.08:02:01.81#ibcon#about to read 5, iclass 15, count 2 2006.253.08:02:01.81#ibcon#read 5, iclass 15, count 2 2006.253.08:02:01.81#ibcon#about to read 6, iclass 15, count 2 2006.253.08:02:01.81#ibcon#read 6, iclass 15, count 2 2006.253.08:02:01.81#ibcon#end of sib2, iclass 15, count 2 2006.253.08:02:01.81#ibcon#*after write, iclass 15, count 2 2006.253.08:02:01.81#ibcon#*before return 0, iclass 15, count 2 2006.253.08:02:01.81#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.253.08:02:01.81#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.253.08:02:01.81#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.253.08:02:01.81#ibcon#ireg 7 cls_cnt 0 2006.253.08:02:01.81#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.253.08:02:01.93#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.253.08:02:01.93#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.253.08:02:01.93#ibcon#enter wrdev, iclass 15, count 0 2006.253.08:02:01.93#ibcon#first serial, iclass 15, count 0 2006.253.08:02:01.93#ibcon#enter sib2, iclass 15, count 0 2006.253.08:02:01.93#ibcon#flushed, iclass 15, count 0 2006.253.08:02:01.93#ibcon#about to write, iclass 15, count 0 2006.253.08:02:01.93#ibcon#wrote, iclass 15, count 0 2006.253.08:02:01.93#ibcon#about to read 3, iclass 15, count 0 2006.253.08:02:01.95#ibcon#read 3, iclass 15, count 0 2006.253.08:02:01.95#ibcon#about to read 4, iclass 15, count 0 2006.253.08:02:01.95#ibcon#read 4, iclass 15, count 0 2006.253.08:02:01.95#ibcon#about to read 5, iclass 15, count 0 2006.253.08:02:01.95#ibcon#read 5, iclass 15, count 0 2006.253.08:02:01.95#ibcon#about to read 6, iclass 15, count 0 2006.253.08:02:01.95#ibcon#read 6, iclass 15, count 0 2006.253.08:02:01.95#ibcon#end of sib2, iclass 15, count 0 2006.253.08:02:01.95#ibcon#*mode == 0, iclass 15, count 0 2006.253.08:02:01.95#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.253.08:02:01.95#ibcon#[27=USB\r\n] 2006.253.08:02:01.95#ibcon#*before write, iclass 15, count 0 2006.253.08:02:01.95#ibcon#enter sib2, iclass 15, count 0 2006.253.08:02:01.95#ibcon#flushed, iclass 15, count 0 2006.253.08:02:01.95#ibcon#about to write, iclass 15, count 0 2006.253.08:02:01.95#ibcon#wrote, iclass 15, count 0 2006.253.08:02:01.95#ibcon#about to read 3, iclass 15, count 0 2006.253.08:02:01.98#ibcon#read 3, iclass 15, count 0 2006.253.08:02:01.98#ibcon#about to read 4, iclass 15, count 0 2006.253.08:02:01.98#ibcon#read 4, iclass 15, count 0 2006.253.08:02:01.98#ibcon#about to read 5, iclass 15, count 0 2006.253.08:02:01.98#ibcon#read 5, iclass 15, count 0 2006.253.08:02:01.98#ibcon#about to read 6, iclass 15, count 0 2006.253.08:02:01.98#ibcon#read 6, iclass 15, count 0 2006.253.08:02:01.98#ibcon#end of sib2, iclass 15, count 0 2006.253.08:02:01.98#ibcon#*after write, iclass 15, count 0 2006.253.08:02:01.98#ibcon#*before return 0, iclass 15, count 0 2006.253.08:02:01.98#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.253.08:02:01.98#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.253.08:02:01.98#ibcon#about to clear, iclass 15 cls_cnt 0 2006.253.08:02:01.98#ibcon#cleared, iclass 15 cls_cnt 0 2006.253.08:02:01.98$vc4f8/vblo=5,744.99 2006.253.08:02:01.98#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.253.08:02:01.98#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.253.08:02:01.98#ibcon#ireg 17 cls_cnt 0 2006.253.08:02:01.98#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.253.08:02:01.98#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.253.08:02:01.98#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.253.08:02:01.98#ibcon#enter wrdev, iclass 17, count 0 2006.253.08:02:01.98#ibcon#first serial, iclass 17, count 0 2006.253.08:02:01.98#ibcon#enter sib2, iclass 17, count 0 2006.253.08:02:01.98#ibcon#flushed, iclass 17, count 0 2006.253.08:02:01.98#ibcon#about to write, iclass 17, count 0 2006.253.08:02:01.98#ibcon#wrote, iclass 17, count 0 2006.253.08:02:01.98#ibcon#about to read 3, iclass 17, count 0 2006.253.08:02:02.00#ibcon#read 3, iclass 17, count 0 2006.253.08:02:02.00#ibcon#about to read 4, iclass 17, count 0 2006.253.08:02:02.00#ibcon#read 4, iclass 17, count 0 2006.253.08:02:02.00#ibcon#about to read 5, iclass 17, count 0 2006.253.08:02:02.00#ibcon#read 5, iclass 17, count 0 2006.253.08:02:02.00#ibcon#about to read 6, iclass 17, count 0 2006.253.08:02:02.00#ibcon#read 6, iclass 17, count 0 2006.253.08:02:02.00#ibcon#end of sib2, iclass 17, count 0 2006.253.08:02:02.00#ibcon#*mode == 0, iclass 17, count 0 2006.253.08:02:02.00#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.253.08:02:02.00#ibcon#[28=FRQ=05,744.99\r\n] 2006.253.08:02:02.00#ibcon#*before write, iclass 17, count 0 2006.253.08:02:02.00#ibcon#enter sib2, iclass 17, count 0 2006.253.08:02:02.00#ibcon#flushed, iclass 17, count 0 2006.253.08:02:02.00#ibcon#about to write, iclass 17, count 0 2006.253.08:02:02.00#ibcon#wrote, iclass 17, count 0 2006.253.08:02:02.00#ibcon#about to read 3, iclass 17, count 0 2006.253.08:02:02.04#ibcon#read 3, iclass 17, count 0 2006.253.08:02:02.04#ibcon#about to read 4, iclass 17, count 0 2006.253.08:02:02.04#ibcon#read 4, iclass 17, count 0 2006.253.08:02:02.04#ibcon#about to read 5, iclass 17, count 0 2006.253.08:02:02.04#ibcon#read 5, iclass 17, count 0 2006.253.08:02:02.04#ibcon#about to read 6, iclass 17, count 0 2006.253.08:02:02.04#ibcon#read 6, iclass 17, count 0 2006.253.08:02:02.04#ibcon#end of sib2, iclass 17, count 0 2006.253.08:02:02.04#ibcon#*after write, iclass 17, count 0 2006.253.08:02:02.04#ibcon#*before return 0, iclass 17, count 0 2006.253.08:02:02.04#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.253.08:02:02.04#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.253.08:02:02.04#ibcon#about to clear, iclass 17 cls_cnt 0 2006.253.08:02:02.04#ibcon#cleared, iclass 17 cls_cnt 0 2006.253.08:02:02.04$vc4f8/vb=5,4 2006.253.08:02:02.04#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.253.08:02:02.04#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.253.08:02:02.04#ibcon#ireg 11 cls_cnt 2 2006.253.08:02:02.04#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.253.08:02:02.10#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.253.08:02:02.10#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.253.08:02:02.10#ibcon#enter wrdev, iclass 19, count 2 2006.253.08:02:02.10#ibcon#first serial, iclass 19, count 2 2006.253.08:02:02.10#ibcon#enter sib2, iclass 19, count 2 2006.253.08:02:02.10#ibcon#flushed, iclass 19, count 2 2006.253.08:02:02.10#ibcon#about to write, iclass 19, count 2 2006.253.08:02:02.10#ibcon#wrote, iclass 19, count 2 2006.253.08:02:02.10#ibcon#about to read 3, iclass 19, count 2 2006.253.08:02:02.12#ibcon#read 3, iclass 19, count 2 2006.253.08:02:02.12#ibcon#about to read 4, iclass 19, count 2 2006.253.08:02:02.12#ibcon#read 4, iclass 19, count 2 2006.253.08:02:02.12#ibcon#about to read 5, iclass 19, count 2 2006.253.08:02:02.12#ibcon#read 5, iclass 19, count 2 2006.253.08:02:02.12#ibcon#about to read 6, iclass 19, count 2 2006.253.08:02:02.12#ibcon#read 6, iclass 19, count 2 2006.253.08:02:02.12#ibcon#end of sib2, iclass 19, count 2 2006.253.08:02:02.12#ibcon#*mode == 0, iclass 19, count 2 2006.253.08:02:02.12#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.253.08:02:02.12#ibcon#[27=AT05-04\r\n] 2006.253.08:02:02.12#ibcon#*before write, iclass 19, count 2 2006.253.08:02:02.12#ibcon#enter sib2, iclass 19, count 2 2006.253.08:02:02.12#ibcon#flushed, iclass 19, count 2 2006.253.08:02:02.12#ibcon#about to write, iclass 19, count 2 2006.253.08:02:02.12#ibcon#wrote, iclass 19, count 2 2006.253.08:02:02.12#ibcon#about to read 3, iclass 19, count 2 2006.253.08:02:02.15#ibcon#read 3, iclass 19, count 2 2006.253.08:02:02.15#ibcon#about to read 4, iclass 19, count 2 2006.253.08:02:02.15#ibcon#read 4, iclass 19, count 2 2006.253.08:02:02.15#ibcon#about to read 5, iclass 19, count 2 2006.253.08:02:02.15#ibcon#read 5, iclass 19, count 2 2006.253.08:02:02.15#ibcon#about to read 6, iclass 19, count 2 2006.253.08:02:02.15#ibcon#read 6, iclass 19, count 2 2006.253.08:02:02.15#ibcon#end of sib2, iclass 19, count 2 2006.253.08:02:02.15#ibcon#*after write, iclass 19, count 2 2006.253.08:02:02.15#ibcon#*before return 0, iclass 19, count 2 2006.253.08:02:02.15#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.253.08:02:02.15#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.253.08:02:02.15#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.253.08:02:02.15#ibcon#ireg 7 cls_cnt 0 2006.253.08:02:02.15#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.253.08:02:02.27#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.253.08:02:02.27#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.253.08:02:02.27#ibcon#enter wrdev, iclass 19, count 0 2006.253.08:02:02.27#ibcon#first serial, iclass 19, count 0 2006.253.08:02:02.27#ibcon#enter sib2, iclass 19, count 0 2006.253.08:02:02.27#ibcon#flushed, iclass 19, count 0 2006.253.08:02:02.27#ibcon#about to write, iclass 19, count 0 2006.253.08:02:02.27#ibcon#wrote, iclass 19, count 0 2006.253.08:02:02.27#ibcon#about to read 3, iclass 19, count 0 2006.253.08:02:02.29#ibcon#read 3, iclass 19, count 0 2006.253.08:02:02.29#ibcon#about to read 4, iclass 19, count 0 2006.253.08:02:02.29#ibcon#read 4, iclass 19, count 0 2006.253.08:02:02.29#ibcon#about to read 5, iclass 19, count 0 2006.253.08:02:02.29#ibcon#read 5, iclass 19, count 0 2006.253.08:02:02.29#ibcon#about to read 6, iclass 19, count 0 2006.253.08:02:02.29#ibcon#read 6, iclass 19, count 0 2006.253.08:02:02.29#ibcon#end of sib2, iclass 19, count 0 2006.253.08:02:02.29#ibcon#*mode == 0, iclass 19, count 0 2006.253.08:02:02.29#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.253.08:02:02.29#ibcon#[27=USB\r\n] 2006.253.08:02:02.29#ibcon#*before write, iclass 19, count 0 2006.253.08:02:02.29#ibcon#enter sib2, iclass 19, count 0 2006.253.08:02:02.29#ibcon#flushed, iclass 19, count 0 2006.253.08:02:02.29#ibcon#about to write, iclass 19, count 0 2006.253.08:02:02.29#ibcon#wrote, iclass 19, count 0 2006.253.08:02:02.29#ibcon#about to read 3, iclass 19, count 0 2006.253.08:02:02.32#ibcon#read 3, iclass 19, count 0 2006.253.08:02:02.32#ibcon#about to read 4, iclass 19, count 0 2006.253.08:02:02.32#ibcon#read 4, iclass 19, count 0 2006.253.08:02:02.32#ibcon#about to read 5, iclass 19, count 0 2006.253.08:02:02.32#ibcon#read 5, iclass 19, count 0 2006.253.08:02:02.32#ibcon#about to read 6, iclass 19, count 0 2006.253.08:02:02.32#ibcon#read 6, iclass 19, count 0 2006.253.08:02:02.32#ibcon#end of sib2, iclass 19, count 0 2006.253.08:02:02.32#ibcon#*after write, iclass 19, count 0 2006.253.08:02:02.32#ibcon#*before return 0, iclass 19, count 0 2006.253.08:02:02.32#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.253.08:02:02.32#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.253.08:02:02.32#ibcon#about to clear, iclass 19 cls_cnt 0 2006.253.08:02:02.32#ibcon#cleared, iclass 19 cls_cnt 0 2006.253.08:02:02.32$vc4f8/vblo=6,752.99 2006.253.08:02:02.32#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.253.08:02:02.32#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.253.08:02:02.32#ibcon#ireg 17 cls_cnt 0 2006.253.08:02:02.32#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.253.08:02:02.32#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.253.08:02:02.32#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.253.08:02:02.32#ibcon#enter wrdev, iclass 21, count 0 2006.253.08:02:02.32#ibcon#first serial, iclass 21, count 0 2006.253.08:02:02.32#ibcon#enter sib2, iclass 21, count 0 2006.253.08:02:02.32#ibcon#flushed, iclass 21, count 0 2006.253.08:02:02.32#ibcon#about to write, iclass 21, count 0 2006.253.08:02:02.32#ibcon#wrote, iclass 21, count 0 2006.253.08:02:02.32#ibcon#about to read 3, iclass 21, count 0 2006.253.08:02:02.35#ibcon#read 3, iclass 21, count 0 2006.253.08:02:02.35#ibcon#about to read 4, iclass 21, count 0 2006.253.08:02:02.35#ibcon#read 4, iclass 21, count 0 2006.253.08:02:02.35#ibcon#about to read 5, iclass 21, count 0 2006.253.08:02:02.35#ibcon#read 5, iclass 21, count 0 2006.253.08:02:02.35#ibcon#about to read 6, iclass 21, count 0 2006.253.08:02:02.35#ibcon#read 6, iclass 21, count 0 2006.253.08:02:02.35#ibcon#end of sib2, iclass 21, count 0 2006.253.08:02:02.35#ibcon#*mode == 0, iclass 21, count 0 2006.253.08:02:02.35#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.253.08:02:02.35#ibcon#[28=FRQ=06,752.99\r\n] 2006.253.08:02:02.35#ibcon#*before write, iclass 21, count 0 2006.253.08:02:02.35#ibcon#enter sib2, iclass 21, count 0 2006.253.08:02:02.35#ibcon#flushed, iclass 21, count 0 2006.253.08:02:02.35#ibcon#about to write, iclass 21, count 0 2006.253.08:02:02.35#ibcon#wrote, iclass 21, count 0 2006.253.08:02:02.35#ibcon#about to read 3, iclass 21, count 0 2006.253.08:02:02.39#ibcon#read 3, iclass 21, count 0 2006.253.08:02:02.39#ibcon#about to read 4, iclass 21, count 0 2006.253.08:02:02.39#ibcon#read 4, iclass 21, count 0 2006.253.08:02:02.39#ibcon#about to read 5, iclass 21, count 0 2006.253.08:02:02.39#ibcon#read 5, iclass 21, count 0 2006.253.08:02:02.39#ibcon#about to read 6, iclass 21, count 0 2006.253.08:02:02.39#ibcon#read 6, iclass 21, count 0 2006.253.08:02:02.39#ibcon#end of sib2, iclass 21, count 0 2006.253.08:02:02.39#ibcon#*after write, iclass 21, count 0 2006.253.08:02:02.39#ibcon#*before return 0, iclass 21, count 0 2006.253.08:02:02.39#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.253.08:02:02.39#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.253.08:02:02.39#ibcon#about to clear, iclass 21 cls_cnt 0 2006.253.08:02:02.39#ibcon#cleared, iclass 21 cls_cnt 0 2006.253.08:02:02.39$vc4f8/vb=6,4 2006.253.08:02:02.39#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.253.08:02:02.39#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.253.08:02:02.39#ibcon#ireg 11 cls_cnt 2 2006.253.08:02:02.39#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.253.08:02:02.44#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.253.08:02:02.44#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.253.08:02:02.44#ibcon#enter wrdev, iclass 23, count 2 2006.253.08:02:02.44#ibcon#first serial, iclass 23, count 2 2006.253.08:02:02.44#ibcon#enter sib2, iclass 23, count 2 2006.253.08:02:02.44#ibcon#flushed, iclass 23, count 2 2006.253.08:02:02.44#ibcon#about to write, iclass 23, count 2 2006.253.08:02:02.44#ibcon#wrote, iclass 23, count 2 2006.253.08:02:02.44#ibcon#about to read 3, iclass 23, count 2 2006.253.08:02:02.46#ibcon#read 3, iclass 23, count 2 2006.253.08:02:02.46#ibcon#about to read 4, iclass 23, count 2 2006.253.08:02:02.46#ibcon#read 4, iclass 23, count 2 2006.253.08:02:02.46#ibcon#about to read 5, iclass 23, count 2 2006.253.08:02:02.46#ibcon#read 5, iclass 23, count 2 2006.253.08:02:02.46#ibcon#about to read 6, iclass 23, count 2 2006.253.08:02:02.46#ibcon#read 6, iclass 23, count 2 2006.253.08:02:02.46#ibcon#end of sib2, iclass 23, count 2 2006.253.08:02:02.46#ibcon#*mode == 0, iclass 23, count 2 2006.253.08:02:02.46#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.253.08:02:02.46#ibcon#[27=AT06-04\r\n] 2006.253.08:02:02.46#ibcon#*before write, iclass 23, count 2 2006.253.08:02:02.46#ibcon#enter sib2, iclass 23, count 2 2006.253.08:02:02.46#ibcon#flushed, iclass 23, count 2 2006.253.08:02:02.46#ibcon#about to write, iclass 23, count 2 2006.253.08:02:02.46#ibcon#wrote, iclass 23, count 2 2006.253.08:02:02.46#ibcon#about to read 3, iclass 23, count 2 2006.253.08:02:02.49#ibcon#read 3, iclass 23, count 2 2006.253.08:02:02.49#ibcon#about to read 4, iclass 23, count 2 2006.253.08:02:02.49#ibcon#read 4, iclass 23, count 2 2006.253.08:02:02.49#ibcon#about to read 5, iclass 23, count 2 2006.253.08:02:02.49#ibcon#read 5, iclass 23, count 2 2006.253.08:02:02.49#ibcon#about to read 6, iclass 23, count 2 2006.253.08:02:02.49#ibcon#read 6, iclass 23, count 2 2006.253.08:02:02.49#ibcon#end of sib2, iclass 23, count 2 2006.253.08:02:02.49#ibcon#*after write, iclass 23, count 2 2006.253.08:02:02.49#ibcon#*before return 0, iclass 23, count 2 2006.253.08:02:02.49#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.253.08:02:02.49#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.253.08:02:02.49#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.253.08:02:02.49#ibcon#ireg 7 cls_cnt 0 2006.253.08:02:02.49#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.253.08:02:02.61#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.253.08:02:02.61#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.253.08:02:02.61#ibcon#enter wrdev, iclass 23, count 0 2006.253.08:02:02.61#ibcon#first serial, iclass 23, count 0 2006.253.08:02:02.61#ibcon#enter sib2, iclass 23, count 0 2006.253.08:02:02.61#ibcon#flushed, iclass 23, count 0 2006.253.08:02:02.61#ibcon#about to write, iclass 23, count 0 2006.253.08:02:02.61#ibcon#wrote, iclass 23, count 0 2006.253.08:02:02.61#ibcon#about to read 3, iclass 23, count 0 2006.253.08:02:02.63#ibcon#read 3, iclass 23, count 0 2006.253.08:02:02.63#ibcon#about to read 4, iclass 23, count 0 2006.253.08:02:02.63#ibcon#read 4, iclass 23, count 0 2006.253.08:02:02.63#ibcon#about to read 5, iclass 23, count 0 2006.253.08:02:02.63#ibcon#read 5, iclass 23, count 0 2006.253.08:02:02.63#ibcon#about to read 6, iclass 23, count 0 2006.253.08:02:02.63#ibcon#read 6, iclass 23, count 0 2006.253.08:02:02.63#ibcon#end of sib2, iclass 23, count 0 2006.253.08:02:02.63#ibcon#*mode == 0, iclass 23, count 0 2006.253.08:02:02.63#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.253.08:02:02.63#ibcon#[27=USB\r\n] 2006.253.08:02:02.63#ibcon#*before write, iclass 23, count 0 2006.253.08:02:02.63#ibcon#enter sib2, iclass 23, count 0 2006.253.08:02:02.63#ibcon#flushed, iclass 23, count 0 2006.253.08:02:02.63#ibcon#about to write, iclass 23, count 0 2006.253.08:02:02.63#ibcon#wrote, iclass 23, count 0 2006.253.08:02:02.63#ibcon#about to read 3, iclass 23, count 0 2006.253.08:02:02.66#ibcon#read 3, iclass 23, count 0 2006.253.08:02:02.66#ibcon#about to read 4, iclass 23, count 0 2006.253.08:02:02.66#ibcon#read 4, iclass 23, count 0 2006.253.08:02:02.66#ibcon#about to read 5, iclass 23, count 0 2006.253.08:02:02.66#ibcon#read 5, iclass 23, count 0 2006.253.08:02:02.66#ibcon#about to read 6, iclass 23, count 0 2006.253.08:02:02.66#ibcon#read 6, iclass 23, count 0 2006.253.08:02:02.66#ibcon#end of sib2, iclass 23, count 0 2006.253.08:02:02.66#ibcon#*after write, iclass 23, count 0 2006.253.08:02:02.66#ibcon#*before return 0, iclass 23, count 0 2006.253.08:02:02.66#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.253.08:02:02.66#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.253.08:02:02.66#ibcon#about to clear, iclass 23 cls_cnt 0 2006.253.08:02:02.66#ibcon#cleared, iclass 23 cls_cnt 0 2006.253.08:02:02.66$vc4f8/vabw=wide 2006.253.08:02:02.66#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.253.08:02:02.66#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.253.08:02:02.66#ibcon#ireg 8 cls_cnt 0 2006.253.08:02:02.66#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.253.08:02:02.66#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.253.08:02:02.66#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.253.08:02:02.66#ibcon#enter wrdev, iclass 25, count 0 2006.253.08:02:02.66#ibcon#first serial, iclass 25, count 0 2006.253.08:02:02.66#ibcon#enter sib2, iclass 25, count 0 2006.253.08:02:02.66#ibcon#flushed, iclass 25, count 0 2006.253.08:02:02.66#ibcon#about to write, iclass 25, count 0 2006.253.08:02:02.66#ibcon#wrote, iclass 25, count 0 2006.253.08:02:02.66#ibcon#about to read 3, iclass 25, count 0 2006.253.08:02:02.68#ibcon#read 3, iclass 25, count 0 2006.253.08:02:02.68#ibcon#about to read 4, iclass 25, count 0 2006.253.08:02:02.68#ibcon#read 4, iclass 25, count 0 2006.253.08:02:02.68#ibcon#about to read 5, iclass 25, count 0 2006.253.08:02:02.68#ibcon#read 5, iclass 25, count 0 2006.253.08:02:02.68#ibcon#about to read 6, iclass 25, count 0 2006.253.08:02:02.68#ibcon#read 6, iclass 25, count 0 2006.253.08:02:02.68#ibcon#end of sib2, iclass 25, count 0 2006.253.08:02:02.68#ibcon#*mode == 0, iclass 25, count 0 2006.253.08:02:02.68#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.253.08:02:02.68#ibcon#[25=BW32\r\n] 2006.253.08:02:02.68#ibcon#*before write, iclass 25, count 0 2006.253.08:02:02.68#ibcon#enter sib2, iclass 25, count 0 2006.253.08:02:02.68#ibcon#flushed, iclass 25, count 0 2006.253.08:02:02.68#ibcon#about to write, iclass 25, count 0 2006.253.08:02:02.68#ibcon#wrote, iclass 25, count 0 2006.253.08:02:02.68#ibcon#about to read 3, iclass 25, count 0 2006.253.08:02:02.71#ibcon#read 3, iclass 25, count 0 2006.253.08:02:02.71#ibcon#about to read 4, iclass 25, count 0 2006.253.08:02:02.71#ibcon#read 4, iclass 25, count 0 2006.253.08:02:02.71#ibcon#about to read 5, iclass 25, count 0 2006.253.08:02:02.71#ibcon#read 5, iclass 25, count 0 2006.253.08:02:02.71#ibcon#about to read 6, iclass 25, count 0 2006.253.08:02:02.71#ibcon#read 6, iclass 25, count 0 2006.253.08:02:02.71#ibcon#end of sib2, iclass 25, count 0 2006.253.08:02:02.71#ibcon#*after write, iclass 25, count 0 2006.253.08:02:02.71#ibcon#*before return 0, iclass 25, count 0 2006.253.08:02:02.71#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.253.08:02:02.71#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.253.08:02:02.71#ibcon#about to clear, iclass 25 cls_cnt 0 2006.253.08:02:02.71#ibcon#cleared, iclass 25 cls_cnt 0 2006.253.08:02:02.71$vc4f8/vbbw=wide 2006.253.08:02:02.71#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.253.08:02:02.71#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.253.08:02:02.71#ibcon#ireg 8 cls_cnt 0 2006.253.08:02:02.71#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.253.08:02:02.78#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.253.08:02:02.78#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.253.08:02:02.78#ibcon#enter wrdev, iclass 27, count 0 2006.253.08:02:02.78#ibcon#first serial, iclass 27, count 0 2006.253.08:02:02.78#ibcon#enter sib2, iclass 27, count 0 2006.253.08:02:02.78#ibcon#flushed, iclass 27, count 0 2006.253.08:02:02.78#ibcon#about to write, iclass 27, count 0 2006.253.08:02:02.78#ibcon#wrote, iclass 27, count 0 2006.253.08:02:02.78#ibcon#about to read 3, iclass 27, count 0 2006.253.08:02:02.80#ibcon#read 3, iclass 27, count 0 2006.253.08:02:02.80#ibcon#about to read 4, iclass 27, count 0 2006.253.08:02:02.80#ibcon#read 4, iclass 27, count 0 2006.253.08:02:02.80#ibcon#about to read 5, iclass 27, count 0 2006.253.08:02:02.80#ibcon#read 5, iclass 27, count 0 2006.253.08:02:02.80#ibcon#about to read 6, iclass 27, count 0 2006.253.08:02:02.80#ibcon#read 6, iclass 27, count 0 2006.253.08:02:02.80#ibcon#end of sib2, iclass 27, count 0 2006.253.08:02:02.80#ibcon#*mode == 0, iclass 27, count 0 2006.253.08:02:02.80#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.253.08:02:02.80#ibcon#[27=BW32\r\n] 2006.253.08:02:02.80#ibcon#*before write, iclass 27, count 0 2006.253.08:02:02.80#ibcon#enter sib2, iclass 27, count 0 2006.253.08:02:02.80#ibcon#flushed, iclass 27, count 0 2006.253.08:02:02.80#ibcon#about to write, iclass 27, count 0 2006.253.08:02:02.80#ibcon#wrote, iclass 27, count 0 2006.253.08:02:02.80#ibcon#about to read 3, iclass 27, count 0 2006.253.08:02:02.83#ibcon#read 3, iclass 27, count 0 2006.253.08:02:02.83#ibcon#about to read 4, iclass 27, count 0 2006.253.08:02:02.83#ibcon#read 4, iclass 27, count 0 2006.253.08:02:02.83#ibcon#about to read 5, iclass 27, count 0 2006.253.08:02:02.83#ibcon#read 5, iclass 27, count 0 2006.253.08:02:02.83#ibcon#about to read 6, iclass 27, count 0 2006.253.08:02:02.83#ibcon#read 6, iclass 27, count 0 2006.253.08:02:02.83#ibcon#end of sib2, iclass 27, count 0 2006.253.08:02:02.83#ibcon#*after write, iclass 27, count 0 2006.253.08:02:02.83#ibcon#*before return 0, iclass 27, count 0 2006.253.08:02:02.83#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.253.08:02:02.83#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.253.08:02:02.83#ibcon#about to clear, iclass 27 cls_cnt 0 2006.253.08:02:02.83#ibcon#cleared, iclass 27 cls_cnt 0 2006.253.08:02:02.83$4f8m12a/ifd4f 2006.253.08:02:02.83$ifd4f/lo= 2006.253.08:02:02.83$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.253.08:02:02.83$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.253.08:02:02.83$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.253.08:02:02.83$ifd4f/patch= 2006.253.08:02:02.83$ifd4f/patch=lo1,a1,a2,a3,a4 2006.253.08:02:02.83$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.253.08:02:02.83$ifd4f/patch=lo3,a5,a6,a7,a8 2006.253.08:02:02.83$4f8m12a/"form=m,16.000,1:2 2006.253.08:02:02.83$4f8m12a/"tpicd 2006.253.08:02:02.83$4f8m12a/echo=off 2006.253.08:02:02.83$4f8m12a/xlog=off 2006.253.08:02:02.83:!2006.253.08:02:30 2006.253.08:02:10.14#trakl#Source acquired 2006.253.08:02:12.14#flagr#flagr/antenna,acquired 2006.253.08:02:30.00:preob 2006.253.08:02:31.14/onsource/TRACKING 2006.253.08:02:31.14:!2006.253.08:02:40 2006.253.08:02:40.00:data_valid=on 2006.253.08:02:40.00:midob 2006.253.08:02:40.14/onsource/TRACKING 2006.253.08:02:40.14/wx/31.08,1006.4,73 2006.253.08:02:40.28/cable/+6.3694E-03 2006.253.08:02:41.37/va/01,08,usb,yes,32,33 2006.253.08:02:41.37/va/02,07,usb,yes,32,33 2006.253.08:02:41.37/va/03,06,usb,yes,34,34 2006.253.08:02:41.37/va/04,07,usb,yes,33,36 2006.253.08:02:41.37/va/05,07,usb,yes,35,37 2006.253.08:02:41.37/va/06,07,usb,yes,30,30 2006.253.08:02:41.37/va/07,07,usb,yes,30,30 2006.253.08:02:41.37/va/08,07,usb,yes,33,32 2006.253.08:02:41.60/valo/01,532.99,yes,locked 2006.253.08:02:41.60/valo/02,572.99,yes,locked 2006.253.08:02:41.60/valo/03,672.99,yes,locked 2006.253.08:02:41.60/valo/04,832.99,yes,locked 2006.253.08:02:41.60/valo/05,652.99,yes,locked 2006.253.08:02:41.60/valo/06,772.99,yes,locked 2006.253.08:02:41.60/valo/07,832.99,yes,locked 2006.253.08:02:41.60/valo/08,852.99,yes,locked 2006.253.08:02:42.69/vb/01,04,usb,yes,31,30 2006.253.08:02:42.69/vb/02,05,usb,yes,29,30 2006.253.08:02:42.69/vb/03,04,usb,yes,29,33 2006.253.08:02:42.69/vb/04,04,usb,yes,30,30 2006.253.08:02:42.69/vb/05,04,usb,yes,28,32 2006.253.08:02:42.69/vb/06,04,usb,yes,29,32 2006.253.08:02:42.69/vb/07,04,usb,yes,32,31 2006.253.08:02:42.69/vb/08,04,usb,yes,29,32 2006.253.08:02:42.93/vblo/01,632.99,yes,locked 2006.253.08:02:42.93/vblo/02,640.99,yes,locked 2006.253.08:02:42.93/vblo/03,656.99,yes,locked 2006.253.08:02:42.93/vblo/04,712.99,yes,locked 2006.253.08:02:42.93/vblo/05,744.99,yes,locked 2006.253.08:02:42.93/vblo/06,752.99,yes,locked 2006.253.08:02:42.93/vblo/07,734.99,yes,locked 2006.253.08:02:42.93/vblo/08,744.99,yes,locked 2006.253.08:02:43.08/vabw/8 2006.253.08:02:43.23/vbbw/8 2006.253.08:02:43.32/xfe/off,on,14.2 2006.253.08:02:43.69/ifatt/23,28,28,28 2006.253.08:02:44.08/fmout-gps/S +4.75E-07 2006.253.08:02:44.16:!2006.253.08:03:40 2006.253.08:03:40.00:data_valid=off 2006.253.08:03:40.00:postob 2006.253.08:03:40.21/cable/+6.3699E-03 2006.253.08:03:40.21/wx/31.08,1006.4,74 2006.253.08:03:41.08/fmout-gps/S +4.75E-07 2006.253.08:03:41.08:scan_name=253-0804,k06253,60 2006.253.08:03:41.09:source=1044+719,104827.62,714335.9,2000.0,ccw 2006.253.08:03:41.13#flagr#flagr/antenna,new-source 2006.253.08:03:42.13:checkk5 2006.253.08:03:42.51/chk_autoobs//k5ts1/ autoobs is running! 2006.253.08:03:42.89/chk_autoobs//k5ts2/ autoobs is running! 2006.253.08:03:43.27/chk_autoobs//k5ts3/ autoobs is running! 2006.253.08:03:43.64/chk_autoobs//k5ts4/ autoobs is running! 2006.253.08:03:44.02/chk_obsdata//k5ts1/T2530802??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.08:03:44.38/chk_obsdata//k5ts2/T2530802??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.08:03:44.75/chk_obsdata//k5ts3/T2530802??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.08:03:45.12/chk_obsdata//k5ts4/T2530802??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.08:03:45.83/k5log//k5ts1_log_newline 2006.253.08:03:46.51/k5log//k5ts2_log_newline 2006.253.08:03:47.20/k5log//k5ts3_log_newline 2006.253.08:03:47.89/k5log//k5ts4_log_newline 2006.253.08:03:47.91/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.253.08:03:47.91:4f8m12a=2 2006.253.08:03:47.91$4f8m12a/echo=on 2006.253.08:03:47.91$4f8m12a/pcalon 2006.253.08:03:47.91$pcalon/"no phase cal control is implemented here 2006.253.08:03:47.91$4f8m12a/"tpicd=stop 2006.253.08:03:47.91$4f8m12a/vc4f8 2006.253.08:03:47.91$vc4f8/valo=1,532.99 2006.253.08:03:47.91#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.253.08:03:47.91#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.253.08:03:47.91#ibcon#ireg 17 cls_cnt 0 2006.253.08:03:47.91#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.253.08:03:47.91#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.253.08:03:47.91#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.253.08:03:47.91#ibcon#enter wrdev, iclass 31, count 0 2006.253.08:03:47.91#ibcon#first serial, iclass 31, count 0 2006.253.08:03:47.91#ibcon#enter sib2, iclass 31, count 0 2006.253.08:03:47.91#ibcon#flushed, iclass 31, count 0 2006.253.08:03:47.91#ibcon#about to write, iclass 31, count 0 2006.253.08:03:47.91#ibcon#wrote, iclass 31, count 0 2006.253.08:03:47.91#ibcon#about to read 3, iclass 31, count 0 2006.253.08:03:47.96#ibcon#read 3, iclass 31, count 0 2006.253.08:03:47.96#ibcon#about to read 4, iclass 31, count 0 2006.253.08:03:47.96#ibcon#read 4, iclass 31, count 0 2006.253.08:03:47.96#ibcon#about to read 5, iclass 31, count 0 2006.253.08:03:47.96#ibcon#read 5, iclass 31, count 0 2006.253.08:03:47.96#ibcon#about to read 6, iclass 31, count 0 2006.253.08:03:47.96#ibcon#read 6, iclass 31, count 0 2006.253.08:03:47.96#ibcon#end of sib2, iclass 31, count 0 2006.253.08:03:47.96#ibcon#*mode == 0, iclass 31, count 0 2006.253.08:03:47.96#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.253.08:03:47.96#ibcon#[26=FRQ=01,532.99\r\n] 2006.253.08:03:47.96#ibcon#*before write, iclass 31, count 0 2006.253.08:03:47.96#ibcon#enter sib2, iclass 31, count 0 2006.253.08:03:47.96#ibcon#flushed, iclass 31, count 0 2006.253.08:03:47.96#ibcon#about to write, iclass 31, count 0 2006.253.08:03:47.96#ibcon#wrote, iclass 31, count 0 2006.253.08:03:47.96#ibcon#about to read 3, iclass 31, count 0 2006.253.08:03:48.00#ibcon#read 3, iclass 31, count 0 2006.253.08:03:48.00#ibcon#about to read 4, iclass 31, count 0 2006.253.08:03:48.00#ibcon#read 4, iclass 31, count 0 2006.253.08:03:48.00#ibcon#about to read 5, iclass 31, count 0 2006.253.08:03:48.00#ibcon#read 5, iclass 31, count 0 2006.253.08:03:48.00#ibcon#about to read 6, iclass 31, count 0 2006.253.08:03:48.00#ibcon#read 6, iclass 31, count 0 2006.253.08:03:48.00#ibcon#end of sib2, iclass 31, count 0 2006.253.08:03:48.00#ibcon#*after write, iclass 31, count 0 2006.253.08:03:48.00#ibcon#*before return 0, iclass 31, count 0 2006.253.08:03:48.00#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.253.08:03:48.00#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.253.08:03:48.00#ibcon#about to clear, iclass 31 cls_cnt 0 2006.253.08:03:48.00#ibcon#cleared, iclass 31 cls_cnt 0 2006.253.08:03:48.00$vc4f8/va=1,8 2006.253.08:03:48.00#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.253.08:03:48.00#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.253.08:03:48.00#ibcon#ireg 11 cls_cnt 2 2006.253.08:03:48.00#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.253.08:03:48.00#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.253.08:03:48.00#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.253.08:03:48.00#ibcon#enter wrdev, iclass 33, count 2 2006.253.08:03:48.00#ibcon#first serial, iclass 33, count 2 2006.253.08:03:48.00#ibcon#enter sib2, iclass 33, count 2 2006.253.08:03:48.00#ibcon#flushed, iclass 33, count 2 2006.253.08:03:48.00#ibcon#about to write, iclass 33, count 2 2006.253.08:03:48.00#ibcon#wrote, iclass 33, count 2 2006.253.08:03:48.00#ibcon#about to read 3, iclass 33, count 2 2006.253.08:03:48.02#ibcon#read 3, iclass 33, count 2 2006.253.08:03:48.02#ibcon#about to read 4, iclass 33, count 2 2006.253.08:03:48.02#ibcon#read 4, iclass 33, count 2 2006.253.08:03:48.02#ibcon#about to read 5, iclass 33, count 2 2006.253.08:03:48.02#ibcon#read 5, iclass 33, count 2 2006.253.08:03:48.02#ibcon#about to read 6, iclass 33, count 2 2006.253.08:03:48.02#ibcon#read 6, iclass 33, count 2 2006.253.08:03:48.02#ibcon#end of sib2, iclass 33, count 2 2006.253.08:03:48.02#ibcon#*mode == 0, iclass 33, count 2 2006.253.08:03:48.02#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.253.08:03:48.02#ibcon#[25=AT01-08\r\n] 2006.253.08:03:48.02#ibcon#*before write, iclass 33, count 2 2006.253.08:03:48.02#ibcon#enter sib2, iclass 33, count 2 2006.253.08:03:48.02#ibcon#flushed, iclass 33, count 2 2006.253.08:03:48.02#ibcon#about to write, iclass 33, count 2 2006.253.08:03:48.02#ibcon#wrote, iclass 33, count 2 2006.253.08:03:48.02#ibcon#about to read 3, iclass 33, count 2 2006.253.08:03:48.05#ibcon#read 3, iclass 33, count 2 2006.253.08:03:48.05#ibcon#about to read 4, iclass 33, count 2 2006.253.08:03:48.05#ibcon#read 4, iclass 33, count 2 2006.253.08:03:48.05#ibcon#about to read 5, iclass 33, count 2 2006.253.08:03:48.05#ibcon#read 5, iclass 33, count 2 2006.253.08:03:48.05#ibcon#about to read 6, iclass 33, count 2 2006.253.08:03:48.05#ibcon#read 6, iclass 33, count 2 2006.253.08:03:48.05#ibcon#end of sib2, iclass 33, count 2 2006.253.08:03:48.05#ibcon#*after write, iclass 33, count 2 2006.253.08:03:48.05#ibcon#*before return 0, iclass 33, count 2 2006.253.08:03:48.05#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.253.08:03:48.05#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.253.08:03:48.05#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.253.08:03:48.05#ibcon#ireg 7 cls_cnt 0 2006.253.08:03:48.05#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.253.08:03:48.17#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.253.08:03:48.17#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.253.08:03:48.17#ibcon#enter wrdev, iclass 33, count 0 2006.253.08:03:48.17#ibcon#first serial, iclass 33, count 0 2006.253.08:03:48.17#ibcon#enter sib2, iclass 33, count 0 2006.253.08:03:48.17#ibcon#flushed, iclass 33, count 0 2006.253.08:03:48.17#ibcon#about to write, iclass 33, count 0 2006.253.08:03:48.17#ibcon#wrote, iclass 33, count 0 2006.253.08:03:48.17#ibcon#about to read 3, iclass 33, count 0 2006.253.08:03:48.19#ibcon#read 3, iclass 33, count 0 2006.253.08:03:48.19#ibcon#about to read 4, iclass 33, count 0 2006.253.08:03:48.19#ibcon#read 4, iclass 33, count 0 2006.253.08:03:48.19#ibcon#about to read 5, iclass 33, count 0 2006.253.08:03:48.19#ibcon#read 5, iclass 33, count 0 2006.253.08:03:48.19#ibcon#about to read 6, iclass 33, count 0 2006.253.08:03:48.19#ibcon#read 6, iclass 33, count 0 2006.253.08:03:48.19#ibcon#end of sib2, iclass 33, count 0 2006.253.08:03:48.19#ibcon#*mode == 0, iclass 33, count 0 2006.253.08:03:48.19#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.253.08:03:48.19#ibcon#[25=USB\r\n] 2006.253.08:03:48.19#ibcon#*before write, iclass 33, count 0 2006.253.08:03:48.19#ibcon#enter sib2, iclass 33, count 0 2006.253.08:03:48.19#ibcon#flushed, iclass 33, count 0 2006.253.08:03:48.19#ibcon#about to write, iclass 33, count 0 2006.253.08:03:48.19#ibcon#wrote, iclass 33, count 0 2006.253.08:03:48.19#ibcon#about to read 3, iclass 33, count 0 2006.253.08:03:48.22#ibcon#read 3, iclass 33, count 0 2006.253.08:03:48.22#ibcon#about to read 4, iclass 33, count 0 2006.253.08:03:48.22#ibcon#read 4, iclass 33, count 0 2006.253.08:03:48.22#ibcon#about to read 5, iclass 33, count 0 2006.253.08:03:48.22#ibcon#read 5, iclass 33, count 0 2006.253.08:03:48.22#ibcon#about to read 6, iclass 33, count 0 2006.253.08:03:48.22#ibcon#read 6, iclass 33, count 0 2006.253.08:03:48.22#ibcon#end of sib2, iclass 33, count 0 2006.253.08:03:48.22#ibcon#*after write, iclass 33, count 0 2006.253.08:03:48.22#ibcon#*before return 0, iclass 33, count 0 2006.253.08:03:48.22#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.253.08:03:48.22#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.253.08:03:48.22#ibcon#about to clear, iclass 33 cls_cnt 0 2006.253.08:03:48.22#ibcon#cleared, iclass 33 cls_cnt 0 2006.253.08:03:48.22$vc4f8/valo=2,572.99 2006.253.08:03:48.22#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.253.08:03:48.22#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.253.08:03:48.22#ibcon#ireg 17 cls_cnt 0 2006.253.08:03:48.22#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.253.08:03:48.22#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.253.08:03:48.22#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.253.08:03:48.22#ibcon#enter wrdev, iclass 35, count 0 2006.253.08:03:48.22#ibcon#first serial, iclass 35, count 0 2006.253.08:03:48.22#ibcon#enter sib2, iclass 35, count 0 2006.253.08:03:48.22#ibcon#flushed, iclass 35, count 0 2006.253.08:03:48.22#ibcon#about to write, iclass 35, count 0 2006.253.08:03:48.22#ibcon#wrote, iclass 35, count 0 2006.253.08:03:48.22#ibcon#about to read 3, iclass 35, count 0 2006.253.08:03:48.24#ibcon#read 3, iclass 35, count 0 2006.253.08:03:48.24#ibcon#about to read 4, iclass 35, count 0 2006.253.08:03:48.24#ibcon#read 4, iclass 35, count 0 2006.253.08:03:48.24#ibcon#about to read 5, iclass 35, count 0 2006.253.08:03:48.24#ibcon#read 5, iclass 35, count 0 2006.253.08:03:48.24#ibcon#about to read 6, iclass 35, count 0 2006.253.08:03:48.24#ibcon#read 6, iclass 35, count 0 2006.253.08:03:48.24#ibcon#end of sib2, iclass 35, count 0 2006.253.08:03:48.24#ibcon#*mode == 0, iclass 35, count 0 2006.253.08:03:48.24#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.253.08:03:48.24#ibcon#[26=FRQ=02,572.99\r\n] 2006.253.08:03:48.24#ibcon#*before write, iclass 35, count 0 2006.253.08:03:48.24#ibcon#enter sib2, iclass 35, count 0 2006.253.08:03:48.24#ibcon#flushed, iclass 35, count 0 2006.253.08:03:48.24#ibcon#about to write, iclass 35, count 0 2006.253.08:03:48.24#ibcon#wrote, iclass 35, count 0 2006.253.08:03:48.24#ibcon#about to read 3, iclass 35, count 0 2006.253.08:03:48.28#ibcon#read 3, iclass 35, count 0 2006.253.08:03:48.28#ibcon#about to read 4, iclass 35, count 0 2006.253.08:03:48.28#ibcon#read 4, iclass 35, count 0 2006.253.08:03:48.28#ibcon#about to read 5, iclass 35, count 0 2006.253.08:03:48.28#ibcon#read 5, iclass 35, count 0 2006.253.08:03:48.28#ibcon#about to read 6, iclass 35, count 0 2006.253.08:03:48.28#ibcon#read 6, iclass 35, count 0 2006.253.08:03:48.28#ibcon#end of sib2, iclass 35, count 0 2006.253.08:03:48.28#ibcon#*after write, iclass 35, count 0 2006.253.08:03:48.28#ibcon#*before return 0, iclass 35, count 0 2006.253.08:03:48.28#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.253.08:03:48.28#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.253.08:03:48.28#ibcon#about to clear, iclass 35 cls_cnt 0 2006.253.08:03:48.28#ibcon#cleared, iclass 35 cls_cnt 0 2006.253.08:03:48.28$vc4f8/va=2,7 2006.253.08:03:48.28#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.253.08:03:48.28#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.253.08:03:48.28#ibcon#ireg 11 cls_cnt 2 2006.253.08:03:48.28#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.253.08:03:48.35#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.253.08:03:48.35#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.253.08:03:48.35#ibcon#enter wrdev, iclass 37, count 2 2006.253.08:03:48.35#ibcon#first serial, iclass 37, count 2 2006.253.08:03:48.35#ibcon#enter sib2, iclass 37, count 2 2006.253.08:03:48.35#ibcon#flushed, iclass 37, count 2 2006.253.08:03:48.35#ibcon#about to write, iclass 37, count 2 2006.253.08:03:48.35#ibcon#wrote, iclass 37, count 2 2006.253.08:03:48.35#ibcon#about to read 3, iclass 37, count 2 2006.253.08:03:48.36#ibcon#read 3, iclass 37, count 2 2006.253.08:03:48.36#ibcon#about to read 4, iclass 37, count 2 2006.253.08:03:48.36#ibcon#read 4, iclass 37, count 2 2006.253.08:03:48.36#ibcon#about to read 5, iclass 37, count 2 2006.253.08:03:48.36#ibcon#read 5, iclass 37, count 2 2006.253.08:03:48.36#ibcon#about to read 6, iclass 37, count 2 2006.253.08:03:48.36#ibcon#read 6, iclass 37, count 2 2006.253.08:03:48.36#ibcon#end of sib2, iclass 37, count 2 2006.253.08:03:48.36#ibcon#*mode == 0, iclass 37, count 2 2006.253.08:03:48.36#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.253.08:03:48.36#ibcon#[25=AT02-07\r\n] 2006.253.08:03:48.36#ibcon#*before write, iclass 37, count 2 2006.253.08:03:48.36#ibcon#enter sib2, iclass 37, count 2 2006.253.08:03:48.36#ibcon#flushed, iclass 37, count 2 2006.253.08:03:48.36#ibcon#about to write, iclass 37, count 2 2006.253.08:03:48.36#ibcon#wrote, iclass 37, count 2 2006.253.08:03:48.36#ibcon#about to read 3, iclass 37, count 2 2006.253.08:03:48.39#ibcon#read 3, iclass 37, count 2 2006.253.08:03:48.39#ibcon#about to read 4, iclass 37, count 2 2006.253.08:03:48.39#ibcon#read 4, iclass 37, count 2 2006.253.08:03:48.39#ibcon#about to read 5, iclass 37, count 2 2006.253.08:03:48.39#ibcon#read 5, iclass 37, count 2 2006.253.08:03:48.39#ibcon#about to read 6, iclass 37, count 2 2006.253.08:03:48.39#ibcon#read 6, iclass 37, count 2 2006.253.08:03:48.39#ibcon#end of sib2, iclass 37, count 2 2006.253.08:03:48.39#ibcon#*after write, iclass 37, count 2 2006.253.08:03:48.39#ibcon#*before return 0, iclass 37, count 2 2006.253.08:03:48.39#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.253.08:03:48.39#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.253.08:03:48.39#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.253.08:03:48.39#ibcon#ireg 7 cls_cnt 0 2006.253.08:03:48.39#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.253.08:03:48.51#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.253.08:03:48.51#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.253.08:03:48.51#ibcon#enter wrdev, iclass 37, count 0 2006.253.08:03:48.51#ibcon#first serial, iclass 37, count 0 2006.253.08:03:48.51#ibcon#enter sib2, iclass 37, count 0 2006.253.08:03:48.51#ibcon#flushed, iclass 37, count 0 2006.253.08:03:48.51#ibcon#about to write, iclass 37, count 0 2006.253.08:03:48.51#ibcon#wrote, iclass 37, count 0 2006.253.08:03:48.51#ibcon#about to read 3, iclass 37, count 0 2006.253.08:03:48.53#ibcon#read 3, iclass 37, count 0 2006.253.08:03:48.53#ibcon#about to read 4, iclass 37, count 0 2006.253.08:03:48.53#ibcon#read 4, iclass 37, count 0 2006.253.08:03:48.53#ibcon#about to read 5, iclass 37, count 0 2006.253.08:03:48.53#ibcon#read 5, iclass 37, count 0 2006.253.08:03:48.53#ibcon#about to read 6, iclass 37, count 0 2006.253.08:03:48.53#ibcon#read 6, iclass 37, count 0 2006.253.08:03:48.53#ibcon#end of sib2, iclass 37, count 0 2006.253.08:03:48.53#ibcon#*mode == 0, iclass 37, count 0 2006.253.08:03:48.53#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.253.08:03:48.53#ibcon#[25=USB\r\n] 2006.253.08:03:48.53#ibcon#*before write, iclass 37, count 0 2006.253.08:03:48.53#ibcon#enter sib2, iclass 37, count 0 2006.253.08:03:48.53#ibcon#flushed, iclass 37, count 0 2006.253.08:03:48.53#ibcon#about to write, iclass 37, count 0 2006.253.08:03:48.53#ibcon#wrote, iclass 37, count 0 2006.253.08:03:48.53#ibcon#about to read 3, iclass 37, count 0 2006.253.08:03:48.56#ibcon#read 3, iclass 37, count 0 2006.253.08:03:48.56#ibcon#about to read 4, iclass 37, count 0 2006.253.08:03:48.56#ibcon#read 4, iclass 37, count 0 2006.253.08:03:48.56#ibcon#about to read 5, iclass 37, count 0 2006.253.08:03:48.56#ibcon#read 5, iclass 37, count 0 2006.253.08:03:48.56#ibcon#about to read 6, iclass 37, count 0 2006.253.08:03:48.56#ibcon#read 6, iclass 37, count 0 2006.253.08:03:48.56#ibcon#end of sib2, iclass 37, count 0 2006.253.08:03:48.56#ibcon#*after write, iclass 37, count 0 2006.253.08:03:48.56#ibcon#*before return 0, iclass 37, count 0 2006.253.08:03:48.56#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.253.08:03:48.56#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.253.08:03:48.56#ibcon#about to clear, iclass 37 cls_cnt 0 2006.253.08:03:48.56#ibcon#cleared, iclass 37 cls_cnt 0 2006.253.08:03:48.56$vc4f8/valo=3,672.99 2006.253.08:03:48.56#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.253.08:03:48.56#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.253.08:03:48.56#ibcon#ireg 17 cls_cnt 0 2006.253.08:03:48.56#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.253.08:03:48.56#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.253.08:03:48.56#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.253.08:03:48.56#ibcon#enter wrdev, iclass 39, count 0 2006.253.08:03:48.56#ibcon#first serial, iclass 39, count 0 2006.253.08:03:48.56#ibcon#enter sib2, iclass 39, count 0 2006.253.08:03:48.56#ibcon#flushed, iclass 39, count 0 2006.253.08:03:48.56#ibcon#about to write, iclass 39, count 0 2006.253.08:03:48.56#ibcon#wrote, iclass 39, count 0 2006.253.08:03:48.56#ibcon#about to read 3, iclass 39, count 0 2006.253.08:03:48.59#ibcon#read 3, iclass 39, count 0 2006.253.08:03:48.59#ibcon#about to read 4, iclass 39, count 0 2006.253.08:03:48.59#ibcon#read 4, iclass 39, count 0 2006.253.08:03:48.59#ibcon#about to read 5, iclass 39, count 0 2006.253.08:03:48.59#ibcon#read 5, iclass 39, count 0 2006.253.08:03:48.59#ibcon#about to read 6, iclass 39, count 0 2006.253.08:03:48.59#ibcon#read 6, iclass 39, count 0 2006.253.08:03:48.59#ibcon#end of sib2, iclass 39, count 0 2006.253.08:03:48.59#ibcon#*mode == 0, iclass 39, count 0 2006.253.08:03:48.59#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.253.08:03:48.59#ibcon#[26=FRQ=03,672.99\r\n] 2006.253.08:03:48.59#ibcon#*before write, iclass 39, count 0 2006.253.08:03:48.59#ibcon#enter sib2, iclass 39, count 0 2006.253.08:03:48.59#ibcon#flushed, iclass 39, count 0 2006.253.08:03:48.59#ibcon#about to write, iclass 39, count 0 2006.253.08:03:48.59#ibcon#wrote, iclass 39, count 0 2006.253.08:03:48.59#ibcon#about to read 3, iclass 39, count 0 2006.253.08:03:48.63#ibcon#read 3, iclass 39, count 0 2006.253.08:03:48.63#ibcon#about to read 4, iclass 39, count 0 2006.253.08:03:48.63#ibcon#read 4, iclass 39, count 0 2006.253.08:03:48.63#ibcon#about to read 5, iclass 39, count 0 2006.253.08:03:48.63#ibcon#read 5, iclass 39, count 0 2006.253.08:03:48.63#ibcon#about to read 6, iclass 39, count 0 2006.253.08:03:48.63#ibcon#read 6, iclass 39, count 0 2006.253.08:03:48.63#ibcon#end of sib2, iclass 39, count 0 2006.253.08:03:48.63#ibcon#*after write, iclass 39, count 0 2006.253.08:03:48.63#ibcon#*before return 0, iclass 39, count 0 2006.253.08:03:48.63#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.253.08:03:48.63#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.253.08:03:48.63#ibcon#about to clear, iclass 39 cls_cnt 0 2006.253.08:03:48.63#ibcon#cleared, iclass 39 cls_cnt 0 2006.253.08:03:48.63$vc4f8/va=3,6 2006.253.08:03:48.63#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.253.08:03:48.63#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.253.08:03:48.63#ibcon#ireg 11 cls_cnt 2 2006.253.08:03:48.63#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.253.08:03:48.68#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.253.08:03:48.68#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.253.08:03:48.68#ibcon#enter wrdev, iclass 3, count 2 2006.253.08:03:48.68#ibcon#first serial, iclass 3, count 2 2006.253.08:03:48.68#ibcon#enter sib2, iclass 3, count 2 2006.253.08:03:48.68#ibcon#flushed, iclass 3, count 2 2006.253.08:03:48.68#ibcon#about to write, iclass 3, count 2 2006.253.08:03:48.68#ibcon#wrote, iclass 3, count 2 2006.253.08:03:48.68#ibcon#about to read 3, iclass 3, count 2 2006.253.08:03:48.70#ibcon#read 3, iclass 3, count 2 2006.253.08:03:48.70#ibcon#about to read 4, iclass 3, count 2 2006.253.08:03:48.70#ibcon#read 4, iclass 3, count 2 2006.253.08:03:48.70#ibcon#about to read 5, iclass 3, count 2 2006.253.08:03:48.70#ibcon#read 5, iclass 3, count 2 2006.253.08:03:48.70#ibcon#about to read 6, iclass 3, count 2 2006.253.08:03:48.70#ibcon#read 6, iclass 3, count 2 2006.253.08:03:48.70#ibcon#end of sib2, iclass 3, count 2 2006.253.08:03:48.70#ibcon#*mode == 0, iclass 3, count 2 2006.253.08:03:48.70#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.253.08:03:48.70#ibcon#[25=AT03-06\r\n] 2006.253.08:03:48.70#ibcon#*before write, iclass 3, count 2 2006.253.08:03:48.70#ibcon#enter sib2, iclass 3, count 2 2006.253.08:03:48.70#ibcon#flushed, iclass 3, count 2 2006.253.08:03:48.70#ibcon#about to write, iclass 3, count 2 2006.253.08:03:48.70#ibcon#wrote, iclass 3, count 2 2006.253.08:03:48.70#ibcon#about to read 3, iclass 3, count 2 2006.253.08:03:48.73#ibcon#read 3, iclass 3, count 2 2006.253.08:03:48.73#ibcon#about to read 4, iclass 3, count 2 2006.253.08:03:48.73#ibcon#read 4, iclass 3, count 2 2006.253.08:03:48.73#ibcon#about to read 5, iclass 3, count 2 2006.253.08:03:48.73#ibcon#read 5, iclass 3, count 2 2006.253.08:03:48.73#ibcon#about to read 6, iclass 3, count 2 2006.253.08:03:48.73#ibcon#read 6, iclass 3, count 2 2006.253.08:03:48.73#ibcon#end of sib2, iclass 3, count 2 2006.253.08:03:48.73#ibcon#*after write, iclass 3, count 2 2006.253.08:03:48.73#ibcon#*before return 0, iclass 3, count 2 2006.253.08:03:48.73#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.253.08:03:48.73#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.253.08:03:48.73#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.253.08:03:48.73#ibcon#ireg 7 cls_cnt 0 2006.253.08:03:48.73#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.253.08:03:48.85#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.253.08:03:48.85#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.253.08:03:48.85#ibcon#enter wrdev, iclass 3, count 0 2006.253.08:03:48.85#ibcon#first serial, iclass 3, count 0 2006.253.08:03:48.85#ibcon#enter sib2, iclass 3, count 0 2006.253.08:03:48.85#ibcon#flushed, iclass 3, count 0 2006.253.08:03:48.85#ibcon#about to write, iclass 3, count 0 2006.253.08:03:48.85#ibcon#wrote, iclass 3, count 0 2006.253.08:03:48.85#ibcon#about to read 3, iclass 3, count 0 2006.253.08:03:48.87#ibcon#read 3, iclass 3, count 0 2006.253.08:03:48.87#ibcon#about to read 4, iclass 3, count 0 2006.253.08:03:48.87#ibcon#read 4, iclass 3, count 0 2006.253.08:03:48.87#ibcon#about to read 5, iclass 3, count 0 2006.253.08:03:48.87#ibcon#read 5, iclass 3, count 0 2006.253.08:03:48.87#ibcon#about to read 6, iclass 3, count 0 2006.253.08:03:48.87#ibcon#read 6, iclass 3, count 0 2006.253.08:03:48.87#ibcon#end of sib2, iclass 3, count 0 2006.253.08:03:48.87#ibcon#*mode == 0, iclass 3, count 0 2006.253.08:03:48.87#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.253.08:03:48.87#ibcon#[25=USB\r\n] 2006.253.08:03:48.87#ibcon#*before write, iclass 3, count 0 2006.253.08:03:48.87#ibcon#enter sib2, iclass 3, count 0 2006.253.08:03:48.87#ibcon#flushed, iclass 3, count 0 2006.253.08:03:48.87#ibcon#about to write, iclass 3, count 0 2006.253.08:03:48.87#ibcon#wrote, iclass 3, count 0 2006.253.08:03:48.87#ibcon#about to read 3, iclass 3, count 0 2006.253.08:03:48.90#ibcon#read 3, iclass 3, count 0 2006.253.08:03:48.90#ibcon#about to read 4, iclass 3, count 0 2006.253.08:03:48.90#ibcon#read 4, iclass 3, count 0 2006.253.08:03:48.90#ibcon#about to read 5, iclass 3, count 0 2006.253.08:03:48.90#ibcon#read 5, iclass 3, count 0 2006.253.08:03:48.90#ibcon#about to read 6, iclass 3, count 0 2006.253.08:03:48.90#ibcon#read 6, iclass 3, count 0 2006.253.08:03:48.90#ibcon#end of sib2, iclass 3, count 0 2006.253.08:03:48.90#ibcon#*after write, iclass 3, count 0 2006.253.08:03:48.90#ibcon#*before return 0, iclass 3, count 0 2006.253.08:03:48.90#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.253.08:03:48.90#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.253.08:03:48.90#ibcon#about to clear, iclass 3 cls_cnt 0 2006.253.08:03:48.90#ibcon#cleared, iclass 3 cls_cnt 0 2006.253.08:03:48.90$vc4f8/valo=4,832.99 2006.253.08:03:48.90#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.253.08:03:48.90#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.253.08:03:48.90#ibcon#ireg 17 cls_cnt 0 2006.253.08:03:48.90#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.253.08:03:48.90#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.253.08:03:48.90#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.253.08:03:48.90#ibcon#enter wrdev, iclass 5, count 0 2006.253.08:03:48.90#ibcon#first serial, iclass 5, count 0 2006.253.08:03:48.90#ibcon#enter sib2, iclass 5, count 0 2006.253.08:03:48.90#ibcon#flushed, iclass 5, count 0 2006.253.08:03:48.90#ibcon#about to write, iclass 5, count 0 2006.253.08:03:48.90#ibcon#wrote, iclass 5, count 0 2006.253.08:03:48.90#ibcon#about to read 3, iclass 5, count 0 2006.253.08:03:48.93#ibcon#read 3, iclass 5, count 0 2006.253.08:03:48.93#ibcon#about to read 4, iclass 5, count 0 2006.253.08:03:48.93#ibcon#read 4, iclass 5, count 0 2006.253.08:03:48.93#ibcon#about to read 5, iclass 5, count 0 2006.253.08:03:48.93#ibcon#read 5, iclass 5, count 0 2006.253.08:03:48.93#ibcon#about to read 6, iclass 5, count 0 2006.253.08:03:48.93#ibcon#read 6, iclass 5, count 0 2006.253.08:03:48.93#ibcon#end of sib2, iclass 5, count 0 2006.253.08:03:48.93#ibcon#*mode == 0, iclass 5, count 0 2006.253.08:03:48.93#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.253.08:03:48.93#ibcon#[26=FRQ=04,832.99\r\n] 2006.253.08:03:48.93#ibcon#*before write, iclass 5, count 0 2006.253.08:03:48.93#ibcon#enter sib2, iclass 5, count 0 2006.253.08:03:48.93#ibcon#flushed, iclass 5, count 0 2006.253.08:03:48.93#ibcon#about to write, iclass 5, count 0 2006.253.08:03:48.93#ibcon#wrote, iclass 5, count 0 2006.253.08:03:48.93#ibcon#about to read 3, iclass 5, count 0 2006.253.08:03:48.97#ibcon#read 3, iclass 5, count 0 2006.253.08:03:48.97#ibcon#about to read 4, iclass 5, count 0 2006.253.08:03:48.97#ibcon#read 4, iclass 5, count 0 2006.253.08:03:48.97#ibcon#about to read 5, iclass 5, count 0 2006.253.08:03:48.97#ibcon#read 5, iclass 5, count 0 2006.253.08:03:48.97#ibcon#about to read 6, iclass 5, count 0 2006.253.08:03:48.97#ibcon#read 6, iclass 5, count 0 2006.253.08:03:48.97#ibcon#end of sib2, iclass 5, count 0 2006.253.08:03:48.97#ibcon#*after write, iclass 5, count 0 2006.253.08:03:48.97#ibcon#*before return 0, iclass 5, count 0 2006.253.08:03:48.97#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.253.08:03:48.97#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.253.08:03:48.97#ibcon#about to clear, iclass 5 cls_cnt 0 2006.253.08:03:48.97#ibcon#cleared, iclass 5 cls_cnt 0 2006.253.08:03:48.97$vc4f8/va=4,7 2006.253.08:03:48.97#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.253.08:03:48.97#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.253.08:03:48.97#ibcon#ireg 11 cls_cnt 2 2006.253.08:03:48.97#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.253.08:03:49.02#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.253.08:03:49.02#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.253.08:03:49.02#ibcon#enter wrdev, iclass 7, count 2 2006.253.08:03:49.02#ibcon#first serial, iclass 7, count 2 2006.253.08:03:49.02#ibcon#enter sib2, iclass 7, count 2 2006.253.08:03:49.02#ibcon#flushed, iclass 7, count 2 2006.253.08:03:49.02#ibcon#about to write, iclass 7, count 2 2006.253.08:03:49.02#ibcon#wrote, iclass 7, count 2 2006.253.08:03:49.02#ibcon#about to read 3, iclass 7, count 2 2006.253.08:03:49.04#ibcon#read 3, iclass 7, count 2 2006.253.08:03:49.04#ibcon#about to read 4, iclass 7, count 2 2006.253.08:03:49.04#ibcon#read 4, iclass 7, count 2 2006.253.08:03:49.04#ibcon#about to read 5, iclass 7, count 2 2006.253.08:03:49.04#ibcon#read 5, iclass 7, count 2 2006.253.08:03:49.04#ibcon#about to read 6, iclass 7, count 2 2006.253.08:03:49.04#ibcon#read 6, iclass 7, count 2 2006.253.08:03:49.04#ibcon#end of sib2, iclass 7, count 2 2006.253.08:03:49.04#ibcon#*mode == 0, iclass 7, count 2 2006.253.08:03:49.04#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.253.08:03:49.04#ibcon#[25=AT04-07\r\n] 2006.253.08:03:49.04#ibcon#*before write, iclass 7, count 2 2006.253.08:03:49.04#ibcon#enter sib2, iclass 7, count 2 2006.253.08:03:49.04#ibcon#flushed, iclass 7, count 2 2006.253.08:03:49.04#ibcon#about to write, iclass 7, count 2 2006.253.08:03:49.04#ibcon#wrote, iclass 7, count 2 2006.253.08:03:49.04#ibcon#about to read 3, iclass 7, count 2 2006.253.08:03:49.07#ibcon#read 3, iclass 7, count 2 2006.253.08:03:49.07#ibcon#about to read 4, iclass 7, count 2 2006.253.08:03:49.07#ibcon#read 4, iclass 7, count 2 2006.253.08:03:49.07#ibcon#about to read 5, iclass 7, count 2 2006.253.08:03:49.07#ibcon#read 5, iclass 7, count 2 2006.253.08:03:49.07#ibcon#about to read 6, iclass 7, count 2 2006.253.08:03:49.07#ibcon#read 6, iclass 7, count 2 2006.253.08:03:49.07#ibcon#end of sib2, iclass 7, count 2 2006.253.08:03:49.07#ibcon#*after write, iclass 7, count 2 2006.253.08:03:49.07#ibcon#*before return 0, iclass 7, count 2 2006.253.08:03:49.07#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.253.08:03:49.07#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.253.08:03:49.07#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.253.08:03:49.07#ibcon#ireg 7 cls_cnt 0 2006.253.08:03:49.07#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.253.08:03:49.19#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.253.08:03:49.19#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.253.08:03:49.19#ibcon#enter wrdev, iclass 7, count 0 2006.253.08:03:49.19#ibcon#first serial, iclass 7, count 0 2006.253.08:03:49.19#ibcon#enter sib2, iclass 7, count 0 2006.253.08:03:49.19#ibcon#flushed, iclass 7, count 0 2006.253.08:03:49.19#ibcon#about to write, iclass 7, count 0 2006.253.08:03:49.19#ibcon#wrote, iclass 7, count 0 2006.253.08:03:49.19#ibcon#about to read 3, iclass 7, count 0 2006.253.08:03:49.21#ibcon#read 3, iclass 7, count 0 2006.253.08:03:49.21#ibcon#about to read 4, iclass 7, count 0 2006.253.08:03:49.21#ibcon#read 4, iclass 7, count 0 2006.253.08:03:49.21#ibcon#about to read 5, iclass 7, count 0 2006.253.08:03:49.21#ibcon#read 5, iclass 7, count 0 2006.253.08:03:49.21#ibcon#about to read 6, iclass 7, count 0 2006.253.08:03:49.21#ibcon#read 6, iclass 7, count 0 2006.253.08:03:49.21#ibcon#end of sib2, iclass 7, count 0 2006.253.08:03:49.21#ibcon#*mode == 0, iclass 7, count 0 2006.253.08:03:49.21#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.253.08:03:49.21#ibcon#[25=USB\r\n] 2006.253.08:03:49.21#ibcon#*before write, iclass 7, count 0 2006.253.08:03:49.21#ibcon#enter sib2, iclass 7, count 0 2006.253.08:03:49.21#ibcon#flushed, iclass 7, count 0 2006.253.08:03:49.21#ibcon#about to write, iclass 7, count 0 2006.253.08:03:49.21#ibcon#wrote, iclass 7, count 0 2006.253.08:03:49.21#ibcon#about to read 3, iclass 7, count 0 2006.253.08:03:49.24#ibcon#read 3, iclass 7, count 0 2006.253.08:03:49.24#ibcon#about to read 4, iclass 7, count 0 2006.253.08:03:49.24#ibcon#read 4, iclass 7, count 0 2006.253.08:03:49.24#ibcon#about to read 5, iclass 7, count 0 2006.253.08:03:49.24#ibcon#read 5, iclass 7, count 0 2006.253.08:03:49.24#ibcon#about to read 6, iclass 7, count 0 2006.253.08:03:49.24#ibcon#read 6, iclass 7, count 0 2006.253.08:03:49.24#ibcon#end of sib2, iclass 7, count 0 2006.253.08:03:49.24#ibcon#*after write, iclass 7, count 0 2006.253.08:03:49.24#ibcon#*before return 0, iclass 7, count 0 2006.253.08:03:49.24#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.253.08:03:49.24#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.253.08:03:49.24#ibcon#about to clear, iclass 7 cls_cnt 0 2006.253.08:03:49.24#ibcon#cleared, iclass 7 cls_cnt 0 2006.253.08:03:49.24$vc4f8/valo=5,652.99 2006.253.08:03:49.24#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.253.08:03:49.24#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.253.08:03:49.24#ibcon#ireg 17 cls_cnt 0 2006.253.08:03:49.24#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.253.08:03:49.24#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.253.08:03:49.24#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.253.08:03:49.24#ibcon#enter wrdev, iclass 11, count 0 2006.253.08:03:49.24#ibcon#first serial, iclass 11, count 0 2006.253.08:03:49.24#ibcon#enter sib2, iclass 11, count 0 2006.253.08:03:49.24#ibcon#flushed, iclass 11, count 0 2006.253.08:03:49.24#ibcon#about to write, iclass 11, count 0 2006.253.08:03:49.24#ibcon#wrote, iclass 11, count 0 2006.253.08:03:49.24#ibcon#about to read 3, iclass 11, count 0 2006.253.08:03:49.26#ibcon#read 3, iclass 11, count 0 2006.253.08:03:49.26#ibcon#about to read 4, iclass 11, count 0 2006.253.08:03:49.26#ibcon#read 4, iclass 11, count 0 2006.253.08:03:49.26#ibcon#about to read 5, iclass 11, count 0 2006.253.08:03:49.26#ibcon#read 5, iclass 11, count 0 2006.253.08:03:49.26#ibcon#about to read 6, iclass 11, count 0 2006.253.08:03:49.26#ibcon#read 6, iclass 11, count 0 2006.253.08:03:49.26#ibcon#end of sib2, iclass 11, count 0 2006.253.08:03:49.26#ibcon#*mode == 0, iclass 11, count 0 2006.253.08:03:49.26#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.253.08:03:49.26#ibcon#[26=FRQ=05,652.99\r\n] 2006.253.08:03:49.26#ibcon#*before write, iclass 11, count 0 2006.253.08:03:49.26#ibcon#enter sib2, iclass 11, count 0 2006.253.08:03:49.26#ibcon#flushed, iclass 11, count 0 2006.253.08:03:49.26#ibcon#about to write, iclass 11, count 0 2006.253.08:03:49.26#ibcon#wrote, iclass 11, count 0 2006.253.08:03:49.26#ibcon#about to read 3, iclass 11, count 0 2006.253.08:03:49.30#ibcon#read 3, iclass 11, count 0 2006.253.08:03:49.30#ibcon#about to read 4, iclass 11, count 0 2006.253.08:03:49.30#ibcon#read 4, iclass 11, count 0 2006.253.08:03:49.30#ibcon#about to read 5, iclass 11, count 0 2006.253.08:03:49.30#ibcon#read 5, iclass 11, count 0 2006.253.08:03:49.30#ibcon#about to read 6, iclass 11, count 0 2006.253.08:03:49.30#ibcon#read 6, iclass 11, count 0 2006.253.08:03:49.30#ibcon#end of sib2, iclass 11, count 0 2006.253.08:03:49.30#ibcon#*after write, iclass 11, count 0 2006.253.08:03:49.30#ibcon#*before return 0, iclass 11, count 0 2006.253.08:03:49.30#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.253.08:03:49.30#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.253.08:03:49.30#ibcon#about to clear, iclass 11 cls_cnt 0 2006.253.08:03:49.30#ibcon#cleared, iclass 11 cls_cnt 0 2006.253.08:03:49.30$vc4f8/va=5,7 2006.253.08:03:49.30#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.253.08:03:49.30#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.253.08:03:49.30#ibcon#ireg 11 cls_cnt 2 2006.253.08:03:49.30#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.253.08:03:49.36#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.253.08:03:49.36#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.253.08:03:49.36#ibcon#enter wrdev, iclass 13, count 2 2006.253.08:03:49.36#ibcon#first serial, iclass 13, count 2 2006.253.08:03:49.36#ibcon#enter sib2, iclass 13, count 2 2006.253.08:03:49.36#ibcon#flushed, iclass 13, count 2 2006.253.08:03:49.36#ibcon#about to write, iclass 13, count 2 2006.253.08:03:49.36#ibcon#wrote, iclass 13, count 2 2006.253.08:03:49.36#ibcon#about to read 3, iclass 13, count 2 2006.253.08:03:49.38#ibcon#read 3, iclass 13, count 2 2006.253.08:03:49.38#ibcon#about to read 4, iclass 13, count 2 2006.253.08:03:49.38#ibcon#read 4, iclass 13, count 2 2006.253.08:03:49.38#ibcon#about to read 5, iclass 13, count 2 2006.253.08:03:49.38#ibcon#read 5, iclass 13, count 2 2006.253.08:03:49.38#ibcon#about to read 6, iclass 13, count 2 2006.253.08:03:49.38#ibcon#read 6, iclass 13, count 2 2006.253.08:03:49.38#ibcon#end of sib2, iclass 13, count 2 2006.253.08:03:49.38#ibcon#*mode == 0, iclass 13, count 2 2006.253.08:03:49.38#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.253.08:03:49.38#ibcon#[25=AT05-07\r\n] 2006.253.08:03:49.38#ibcon#*before write, iclass 13, count 2 2006.253.08:03:49.38#ibcon#enter sib2, iclass 13, count 2 2006.253.08:03:49.38#ibcon#flushed, iclass 13, count 2 2006.253.08:03:49.38#ibcon#about to write, iclass 13, count 2 2006.253.08:03:49.38#ibcon#wrote, iclass 13, count 2 2006.253.08:03:49.38#ibcon#about to read 3, iclass 13, count 2 2006.253.08:03:49.41#ibcon#read 3, iclass 13, count 2 2006.253.08:03:49.41#ibcon#about to read 4, iclass 13, count 2 2006.253.08:03:49.41#ibcon#read 4, iclass 13, count 2 2006.253.08:03:49.41#ibcon#about to read 5, iclass 13, count 2 2006.253.08:03:49.41#ibcon#read 5, iclass 13, count 2 2006.253.08:03:49.41#ibcon#about to read 6, iclass 13, count 2 2006.253.08:03:49.41#ibcon#read 6, iclass 13, count 2 2006.253.08:03:49.41#ibcon#end of sib2, iclass 13, count 2 2006.253.08:03:49.41#ibcon#*after write, iclass 13, count 2 2006.253.08:03:49.41#ibcon#*before return 0, iclass 13, count 2 2006.253.08:03:49.41#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.253.08:03:49.41#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.253.08:03:49.41#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.253.08:03:49.41#ibcon#ireg 7 cls_cnt 0 2006.253.08:03:49.41#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.253.08:03:49.53#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.253.08:03:49.53#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.253.08:03:49.53#ibcon#enter wrdev, iclass 13, count 0 2006.253.08:03:49.53#ibcon#first serial, iclass 13, count 0 2006.253.08:03:49.53#ibcon#enter sib2, iclass 13, count 0 2006.253.08:03:49.53#ibcon#flushed, iclass 13, count 0 2006.253.08:03:49.53#ibcon#about to write, iclass 13, count 0 2006.253.08:03:49.53#ibcon#wrote, iclass 13, count 0 2006.253.08:03:49.53#ibcon#about to read 3, iclass 13, count 0 2006.253.08:03:49.55#ibcon#read 3, iclass 13, count 0 2006.253.08:03:49.55#ibcon#about to read 4, iclass 13, count 0 2006.253.08:03:49.55#ibcon#read 4, iclass 13, count 0 2006.253.08:03:49.55#ibcon#about to read 5, iclass 13, count 0 2006.253.08:03:49.55#ibcon#read 5, iclass 13, count 0 2006.253.08:03:49.55#ibcon#about to read 6, iclass 13, count 0 2006.253.08:03:49.55#ibcon#read 6, iclass 13, count 0 2006.253.08:03:49.55#ibcon#end of sib2, iclass 13, count 0 2006.253.08:03:49.55#ibcon#*mode == 0, iclass 13, count 0 2006.253.08:03:49.55#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.253.08:03:49.55#ibcon#[25=USB\r\n] 2006.253.08:03:49.55#ibcon#*before write, iclass 13, count 0 2006.253.08:03:49.55#ibcon#enter sib2, iclass 13, count 0 2006.253.08:03:49.55#ibcon#flushed, iclass 13, count 0 2006.253.08:03:49.55#ibcon#about to write, iclass 13, count 0 2006.253.08:03:49.55#ibcon#wrote, iclass 13, count 0 2006.253.08:03:49.55#ibcon#about to read 3, iclass 13, count 0 2006.253.08:03:49.58#ibcon#read 3, iclass 13, count 0 2006.253.08:03:49.58#ibcon#about to read 4, iclass 13, count 0 2006.253.08:03:49.58#ibcon#read 4, iclass 13, count 0 2006.253.08:03:49.58#ibcon#about to read 5, iclass 13, count 0 2006.253.08:03:49.58#ibcon#read 5, iclass 13, count 0 2006.253.08:03:49.58#ibcon#about to read 6, iclass 13, count 0 2006.253.08:03:49.58#ibcon#read 6, iclass 13, count 0 2006.253.08:03:49.58#ibcon#end of sib2, iclass 13, count 0 2006.253.08:03:49.58#ibcon#*after write, iclass 13, count 0 2006.253.08:03:49.58#ibcon#*before return 0, iclass 13, count 0 2006.253.08:03:49.58#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.253.08:03:49.58#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.253.08:03:49.58#ibcon#about to clear, iclass 13 cls_cnt 0 2006.253.08:03:49.58#ibcon#cleared, iclass 13 cls_cnt 0 2006.253.08:03:49.58$vc4f8/valo=6,772.99 2006.253.08:03:49.58#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.253.08:03:49.58#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.253.08:03:49.58#ibcon#ireg 17 cls_cnt 0 2006.253.08:03:49.58#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.253.08:03:49.58#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.253.08:03:49.58#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.253.08:03:49.58#ibcon#enter wrdev, iclass 15, count 0 2006.253.08:03:49.58#ibcon#first serial, iclass 15, count 0 2006.253.08:03:49.58#ibcon#enter sib2, iclass 15, count 0 2006.253.08:03:49.58#ibcon#flushed, iclass 15, count 0 2006.253.08:03:49.58#ibcon#about to write, iclass 15, count 0 2006.253.08:03:49.58#ibcon#wrote, iclass 15, count 0 2006.253.08:03:49.58#ibcon#about to read 3, iclass 15, count 0 2006.253.08:03:49.61#ibcon#read 3, iclass 15, count 0 2006.253.08:03:49.61#ibcon#about to read 4, iclass 15, count 0 2006.253.08:03:49.61#ibcon#read 4, iclass 15, count 0 2006.253.08:03:49.61#ibcon#about to read 5, iclass 15, count 0 2006.253.08:03:49.61#ibcon#read 5, iclass 15, count 0 2006.253.08:03:49.61#ibcon#about to read 6, iclass 15, count 0 2006.253.08:03:49.61#ibcon#read 6, iclass 15, count 0 2006.253.08:03:49.61#ibcon#end of sib2, iclass 15, count 0 2006.253.08:03:49.61#ibcon#*mode == 0, iclass 15, count 0 2006.253.08:03:49.61#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.253.08:03:49.61#ibcon#[26=FRQ=06,772.99\r\n] 2006.253.08:03:49.61#ibcon#*before write, iclass 15, count 0 2006.253.08:03:49.61#ibcon#enter sib2, iclass 15, count 0 2006.253.08:03:49.61#ibcon#flushed, iclass 15, count 0 2006.253.08:03:49.61#ibcon#about to write, iclass 15, count 0 2006.253.08:03:49.61#ibcon#wrote, iclass 15, count 0 2006.253.08:03:49.61#ibcon#about to read 3, iclass 15, count 0 2006.253.08:03:49.65#ibcon#read 3, iclass 15, count 0 2006.253.08:03:49.65#ibcon#about to read 4, iclass 15, count 0 2006.253.08:03:49.65#ibcon#read 4, iclass 15, count 0 2006.253.08:03:49.65#ibcon#about to read 5, iclass 15, count 0 2006.253.08:03:49.65#ibcon#read 5, iclass 15, count 0 2006.253.08:03:49.65#ibcon#about to read 6, iclass 15, count 0 2006.253.08:03:49.65#ibcon#read 6, iclass 15, count 0 2006.253.08:03:49.65#ibcon#end of sib2, iclass 15, count 0 2006.253.08:03:49.65#ibcon#*after write, iclass 15, count 0 2006.253.08:03:49.65#ibcon#*before return 0, iclass 15, count 0 2006.253.08:03:49.65#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.253.08:03:49.65#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.253.08:03:49.65#ibcon#about to clear, iclass 15 cls_cnt 0 2006.253.08:03:49.65#ibcon#cleared, iclass 15 cls_cnt 0 2006.253.08:03:49.65$vc4f8/va=6,7 2006.253.08:03:49.65#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.253.08:03:49.65#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.253.08:03:49.65#ibcon#ireg 11 cls_cnt 2 2006.253.08:03:49.65#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.253.08:03:49.70#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.253.08:03:49.70#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.253.08:03:49.70#ibcon#enter wrdev, iclass 17, count 2 2006.253.08:03:49.70#ibcon#first serial, iclass 17, count 2 2006.253.08:03:49.70#ibcon#enter sib2, iclass 17, count 2 2006.253.08:03:49.70#ibcon#flushed, iclass 17, count 2 2006.253.08:03:49.70#ibcon#about to write, iclass 17, count 2 2006.253.08:03:49.70#ibcon#wrote, iclass 17, count 2 2006.253.08:03:49.70#ibcon#about to read 3, iclass 17, count 2 2006.253.08:03:49.72#ibcon#read 3, iclass 17, count 2 2006.253.08:03:49.72#ibcon#about to read 4, iclass 17, count 2 2006.253.08:03:49.72#ibcon#read 4, iclass 17, count 2 2006.253.08:03:49.72#ibcon#about to read 5, iclass 17, count 2 2006.253.08:03:49.72#ibcon#read 5, iclass 17, count 2 2006.253.08:03:49.72#ibcon#about to read 6, iclass 17, count 2 2006.253.08:03:49.72#ibcon#read 6, iclass 17, count 2 2006.253.08:03:49.72#ibcon#end of sib2, iclass 17, count 2 2006.253.08:03:49.72#ibcon#*mode == 0, iclass 17, count 2 2006.253.08:03:49.72#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.253.08:03:49.72#ibcon#[25=AT06-07\r\n] 2006.253.08:03:49.72#ibcon#*before write, iclass 17, count 2 2006.253.08:03:49.72#ibcon#enter sib2, iclass 17, count 2 2006.253.08:03:49.72#ibcon#flushed, iclass 17, count 2 2006.253.08:03:49.72#ibcon#about to write, iclass 17, count 2 2006.253.08:03:49.72#ibcon#wrote, iclass 17, count 2 2006.253.08:03:49.72#ibcon#about to read 3, iclass 17, count 2 2006.253.08:03:49.75#ibcon#read 3, iclass 17, count 2 2006.253.08:03:49.75#ibcon#about to read 4, iclass 17, count 2 2006.253.08:03:49.75#ibcon#read 4, iclass 17, count 2 2006.253.08:03:49.75#ibcon#about to read 5, iclass 17, count 2 2006.253.08:03:49.75#ibcon#read 5, iclass 17, count 2 2006.253.08:03:49.75#ibcon#about to read 6, iclass 17, count 2 2006.253.08:03:49.75#ibcon#read 6, iclass 17, count 2 2006.253.08:03:49.75#ibcon#end of sib2, iclass 17, count 2 2006.253.08:03:49.75#ibcon#*after write, iclass 17, count 2 2006.253.08:03:49.75#ibcon#*before return 0, iclass 17, count 2 2006.253.08:03:49.75#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.253.08:03:49.75#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.253.08:03:49.75#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.253.08:03:49.75#ibcon#ireg 7 cls_cnt 0 2006.253.08:03:49.75#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.253.08:03:49.87#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.253.08:03:49.87#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.253.08:03:49.87#ibcon#enter wrdev, iclass 17, count 0 2006.253.08:03:49.87#ibcon#first serial, iclass 17, count 0 2006.253.08:03:49.87#ibcon#enter sib2, iclass 17, count 0 2006.253.08:03:49.87#ibcon#flushed, iclass 17, count 0 2006.253.08:03:49.87#ibcon#about to write, iclass 17, count 0 2006.253.08:03:49.87#ibcon#wrote, iclass 17, count 0 2006.253.08:03:49.87#ibcon#about to read 3, iclass 17, count 0 2006.253.08:03:49.89#ibcon#read 3, iclass 17, count 0 2006.253.08:03:49.89#ibcon#about to read 4, iclass 17, count 0 2006.253.08:03:49.89#ibcon#read 4, iclass 17, count 0 2006.253.08:03:49.89#ibcon#about to read 5, iclass 17, count 0 2006.253.08:03:49.89#ibcon#read 5, iclass 17, count 0 2006.253.08:03:49.89#ibcon#about to read 6, iclass 17, count 0 2006.253.08:03:49.89#ibcon#read 6, iclass 17, count 0 2006.253.08:03:49.89#ibcon#end of sib2, iclass 17, count 0 2006.253.08:03:49.89#ibcon#*mode == 0, iclass 17, count 0 2006.253.08:03:49.89#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.253.08:03:49.89#ibcon#[25=USB\r\n] 2006.253.08:03:49.89#ibcon#*before write, iclass 17, count 0 2006.253.08:03:49.89#ibcon#enter sib2, iclass 17, count 0 2006.253.08:03:49.89#ibcon#flushed, iclass 17, count 0 2006.253.08:03:49.89#ibcon#about to write, iclass 17, count 0 2006.253.08:03:49.89#ibcon#wrote, iclass 17, count 0 2006.253.08:03:49.89#ibcon#about to read 3, iclass 17, count 0 2006.253.08:03:49.92#ibcon#read 3, iclass 17, count 0 2006.253.08:03:49.92#ibcon#about to read 4, iclass 17, count 0 2006.253.08:03:49.92#ibcon#read 4, iclass 17, count 0 2006.253.08:03:49.92#ibcon#about to read 5, iclass 17, count 0 2006.253.08:03:49.92#ibcon#read 5, iclass 17, count 0 2006.253.08:03:49.92#ibcon#about to read 6, iclass 17, count 0 2006.253.08:03:49.92#ibcon#read 6, iclass 17, count 0 2006.253.08:03:49.92#ibcon#end of sib2, iclass 17, count 0 2006.253.08:03:49.92#ibcon#*after write, iclass 17, count 0 2006.253.08:03:49.92#ibcon#*before return 0, iclass 17, count 0 2006.253.08:03:49.92#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.253.08:03:49.92#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.253.08:03:49.92#ibcon#about to clear, iclass 17 cls_cnt 0 2006.253.08:03:49.92#ibcon#cleared, iclass 17 cls_cnt 0 2006.253.08:03:49.92$vc4f8/valo=7,832.99 2006.253.08:03:49.92#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.253.08:03:49.92#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.253.08:03:49.92#ibcon#ireg 17 cls_cnt 0 2006.253.08:03:49.92#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.253.08:03:49.92#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.253.08:03:49.92#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.253.08:03:49.92#ibcon#enter wrdev, iclass 19, count 0 2006.253.08:03:49.92#ibcon#first serial, iclass 19, count 0 2006.253.08:03:49.92#ibcon#enter sib2, iclass 19, count 0 2006.253.08:03:49.92#ibcon#flushed, iclass 19, count 0 2006.253.08:03:49.92#ibcon#about to write, iclass 19, count 0 2006.253.08:03:49.92#ibcon#wrote, iclass 19, count 0 2006.253.08:03:49.92#ibcon#about to read 3, iclass 19, count 0 2006.253.08:03:49.94#ibcon#read 3, iclass 19, count 0 2006.253.08:03:49.94#ibcon#about to read 4, iclass 19, count 0 2006.253.08:03:49.94#ibcon#read 4, iclass 19, count 0 2006.253.08:03:49.94#ibcon#about to read 5, iclass 19, count 0 2006.253.08:03:49.94#ibcon#read 5, iclass 19, count 0 2006.253.08:03:49.94#ibcon#about to read 6, iclass 19, count 0 2006.253.08:03:49.94#ibcon#read 6, iclass 19, count 0 2006.253.08:03:49.94#ibcon#end of sib2, iclass 19, count 0 2006.253.08:03:49.94#ibcon#*mode == 0, iclass 19, count 0 2006.253.08:03:49.94#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.253.08:03:49.94#ibcon#[26=FRQ=07,832.99\r\n] 2006.253.08:03:49.94#ibcon#*before write, iclass 19, count 0 2006.253.08:03:49.94#ibcon#enter sib2, iclass 19, count 0 2006.253.08:03:49.94#ibcon#flushed, iclass 19, count 0 2006.253.08:03:49.94#ibcon#about to write, iclass 19, count 0 2006.253.08:03:49.94#ibcon#wrote, iclass 19, count 0 2006.253.08:03:49.94#ibcon#about to read 3, iclass 19, count 0 2006.253.08:03:49.98#ibcon#read 3, iclass 19, count 0 2006.253.08:03:49.98#ibcon#about to read 4, iclass 19, count 0 2006.253.08:03:49.98#ibcon#read 4, iclass 19, count 0 2006.253.08:03:49.98#ibcon#about to read 5, iclass 19, count 0 2006.253.08:03:49.98#ibcon#read 5, iclass 19, count 0 2006.253.08:03:49.98#ibcon#about to read 6, iclass 19, count 0 2006.253.08:03:49.98#ibcon#read 6, iclass 19, count 0 2006.253.08:03:49.98#ibcon#end of sib2, iclass 19, count 0 2006.253.08:03:49.98#ibcon#*after write, iclass 19, count 0 2006.253.08:03:49.98#ibcon#*before return 0, iclass 19, count 0 2006.253.08:03:49.98#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.253.08:03:49.98#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.253.08:03:49.98#ibcon#about to clear, iclass 19 cls_cnt 0 2006.253.08:03:49.98#ibcon#cleared, iclass 19 cls_cnt 0 2006.253.08:03:49.98$vc4f8/va=7,7 2006.253.08:03:49.98#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.253.08:03:49.98#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.253.08:03:49.98#ibcon#ireg 11 cls_cnt 2 2006.253.08:03:49.98#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.253.08:03:50.04#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.253.08:03:50.04#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.253.08:03:50.04#ibcon#enter wrdev, iclass 21, count 2 2006.253.08:03:50.04#ibcon#first serial, iclass 21, count 2 2006.253.08:03:50.04#ibcon#enter sib2, iclass 21, count 2 2006.253.08:03:50.04#ibcon#flushed, iclass 21, count 2 2006.253.08:03:50.04#ibcon#about to write, iclass 21, count 2 2006.253.08:03:50.04#ibcon#wrote, iclass 21, count 2 2006.253.08:03:50.04#ibcon#about to read 3, iclass 21, count 2 2006.253.08:03:50.06#ibcon#read 3, iclass 21, count 2 2006.253.08:03:50.06#ibcon#about to read 4, iclass 21, count 2 2006.253.08:03:50.06#ibcon#read 4, iclass 21, count 2 2006.253.08:03:50.06#ibcon#about to read 5, iclass 21, count 2 2006.253.08:03:50.06#ibcon#read 5, iclass 21, count 2 2006.253.08:03:50.06#ibcon#about to read 6, iclass 21, count 2 2006.253.08:03:50.06#ibcon#read 6, iclass 21, count 2 2006.253.08:03:50.06#ibcon#end of sib2, iclass 21, count 2 2006.253.08:03:50.06#ibcon#*mode == 0, iclass 21, count 2 2006.253.08:03:50.06#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.253.08:03:50.06#ibcon#[25=AT07-07\r\n] 2006.253.08:03:50.06#ibcon#*before write, iclass 21, count 2 2006.253.08:03:50.06#ibcon#enter sib2, iclass 21, count 2 2006.253.08:03:50.06#ibcon#flushed, iclass 21, count 2 2006.253.08:03:50.06#ibcon#about to write, iclass 21, count 2 2006.253.08:03:50.06#ibcon#wrote, iclass 21, count 2 2006.253.08:03:50.06#ibcon#about to read 3, iclass 21, count 2 2006.253.08:03:50.09#ibcon#read 3, iclass 21, count 2 2006.253.08:03:50.09#ibcon#about to read 4, iclass 21, count 2 2006.253.08:03:50.09#ibcon#read 4, iclass 21, count 2 2006.253.08:03:50.09#ibcon#about to read 5, iclass 21, count 2 2006.253.08:03:50.09#ibcon#read 5, iclass 21, count 2 2006.253.08:03:50.09#ibcon#about to read 6, iclass 21, count 2 2006.253.08:03:50.09#ibcon#read 6, iclass 21, count 2 2006.253.08:03:50.09#ibcon#end of sib2, iclass 21, count 2 2006.253.08:03:50.09#ibcon#*after write, iclass 21, count 2 2006.253.08:03:50.09#ibcon#*before return 0, iclass 21, count 2 2006.253.08:03:50.09#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.253.08:03:50.09#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.253.08:03:50.09#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.253.08:03:50.09#ibcon#ireg 7 cls_cnt 0 2006.253.08:03:50.09#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.253.08:03:50.21#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.253.08:03:50.21#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.253.08:03:50.21#ibcon#enter wrdev, iclass 21, count 0 2006.253.08:03:50.21#ibcon#first serial, iclass 21, count 0 2006.253.08:03:50.21#ibcon#enter sib2, iclass 21, count 0 2006.253.08:03:50.21#ibcon#flushed, iclass 21, count 0 2006.253.08:03:50.21#ibcon#about to write, iclass 21, count 0 2006.253.08:03:50.21#ibcon#wrote, iclass 21, count 0 2006.253.08:03:50.21#ibcon#about to read 3, iclass 21, count 0 2006.253.08:03:50.23#ibcon#read 3, iclass 21, count 0 2006.253.08:03:50.23#ibcon#about to read 4, iclass 21, count 0 2006.253.08:03:50.23#ibcon#read 4, iclass 21, count 0 2006.253.08:03:50.23#ibcon#about to read 5, iclass 21, count 0 2006.253.08:03:50.23#ibcon#read 5, iclass 21, count 0 2006.253.08:03:50.23#ibcon#about to read 6, iclass 21, count 0 2006.253.08:03:50.23#ibcon#read 6, iclass 21, count 0 2006.253.08:03:50.23#ibcon#end of sib2, iclass 21, count 0 2006.253.08:03:50.23#ibcon#*mode == 0, iclass 21, count 0 2006.253.08:03:50.23#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.253.08:03:50.23#ibcon#[25=USB\r\n] 2006.253.08:03:50.23#ibcon#*before write, iclass 21, count 0 2006.253.08:03:50.23#ibcon#enter sib2, iclass 21, count 0 2006.253.08:03:50.23#ibcon#flushed, iclass 21, count 0 2006.253.08:03:50.23#ibcon#about to write, iclass 21, count 0 2006.253.08:03:50.23#ibcon#wrote, iclass 21, count 0 2006.253.08:03:50.23#ibcon#about to read 3, iclass 21, count 0 2006.253.08:03:50.26#ibcon#read 3, iclass 21, count 0 2006.253.08:03:50.26#ibcon#about to read 4, iclass 21, count 0 2006.253.08:03:50.26#ibcon#read 4, iclass 21, count 0 2006.253.08:03:50.26#ibcon#about to read 5, iclass 21, count 0 2006.253.08:03:50.26#ibcon#read 5, iclass 21, count 0 2006.253.08:03:50.26#ibcon#about to read 6, iclass 21, count 0 2006.253.08:03:50.26#ibcon#read 6, iclass 21, count 0 2006.253.08:03:50.26#ibcon#end of sib2, iclass 21, count 0 2006.253.08:03:50.26#ibcon#*after write, iclass 21, count 0 2006.253.08:03:50.26#ibcon#*before return 0, iclass 21, count 0 2006.253.08:03:50.26#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.253.08:03:50.26#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.253.08:03:50.26#ibcon#about to clear, iclass 21 cls_cnt 0 2006.253.08:03:50.26#ibcon#cleared, iclass 21 cls_cnt 0 2006.253.08:03:50.26$vc4f8/valo=8,852.99 2006.253.08:03:50.26#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.253.08:03:50.26#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.253.08:03:50.26#ibcon#ireg 17 cls_cnt 0 2006.253.08:03:50.26#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.253.08:03:50.26#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.253.08:03:50.26#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.253.08:03:50.26#ibcon#enter wrdev, iclass 23, count 0 2006.253.08:03:50.26#ibcon#first serial, iclass 23, count 0 2006.253.08:03:50.26#ibcon#enter sib2, iclass 23, count 0 2006.253.08:03:50.26#ibcon#flushed, iclass 23, count 0 2006.253.08:03:50.26#ibcon#about to write, iclass 23, count 0 2006.253.08:03:50.26#ibcon#wrote, iclass 23, count 0 2006.253.08:03:50.26#ibcon#about to read 3, iclass 23, count 0 2006.253.08:03:50.28#ibcon#read 3, iclass 23, count 0 2006.253.08:03:50.28#ibcon#about to read 4, iclass 23, count 0 2006.253.08:03:50.28#ibcon#read 4, iclass 23, count 0 2006.253.08:03:50.28#ibcon#about to read 5, iclass 23, count 0 2006.253.08:03:50.28#ibcon#read 5, iclass 23, count 0 2006.253.08:03:50.28#ibcon#about to read 6, iclass 23, count 0 2006.253.08:03:50.28#ibcon#read 6, iclass 23, count 0 2006.253.08:03:50.28#ibcon#end of sib2, iclass 23, count 0 2006.253.08:03:50.28#ibcon#*mode == 0, iclass 23, count 0 2006.253.08:03:50.28#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.253.08:03:50.28#ibcon#[26=FRQ=08,852.99\r\n] 2006.253.08:03:50.28#ibcon#*before write, iclass 23, count 0 2006.253.08:03:50.28#ibcon#enter sib2, iclass 23, count 0 2006.253.08:03:50.28#ibcon#flushed, iclass 23, count 0 2006.253.08:03:50.28#ibcon#about to write, iclass 23, count 0 2006.253.08:03:50.28#ibcon#wrote, iclass 23, count 0 2006.253.08:03:50.28#ibcon#about to read 3, iclass 23, count 0 2006.253.08:03:50.32#ibcon#read 3, iclass 23, count 0 2006.253.08:03:50.32#ibcon#about to read 4, iclass 23, count 0 2006.253.08:03:50.32#ibcon#read 4, iclass 23, count 0 2006.253.08:03:50.32#ibcon#about to read 5, iclass 23, count 0 2006.253.08:03:50.32#ibcon#read 5, iclass 23, count 0 2006.253.08:03:50.32#ibcon#about to read 6, iclass 23, count 0 2006.253.08:03:50.32#ibcon#read 6, iclass 23, count 0 2006.253.08:03:50.32#ibcon#end of sib2, iclass 23, count 0 2006.253.08:03:50.32#ibcon#*after write, iclass 23, count 0 2006.253.08:03:50.32#ibcon#*before return 0, iclass 23, count 0 2006.253.08:03:50.32#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.253.08:03:50.32#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.253.08:03:50.32#ibcon#about to clear, iclass 23 cls_cnt 0 2006.253.08:03:50.32#ibcon#cleared, iclass 23 cls_cnt 0 2006.253.08:03:50.32$vc4f8/va=8,7 2006.253.08:03:50.32#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.253.08:03:50.32#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.253.08:03:50.32#ibcon#ireg 11 cls_cnt 2 2006.253.08:03:50.32#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.253.08:03:50.38#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.253.08:03:50.38#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.253.08:03:50.38#ibcon#enter wrdev, iclass 25, count 2 2006.253.08:03:50.38#ibcon#first serial, iclass 25, count 2 2006.253.08:03:50.38#ibcon#enter sib2, iclass 25, count 2 2006.253.08:03:50.38#ibcon#flushed, iclass 25, count 2 2006.253.08:03:50.38#ibcon#about to write, iclass 25, count 2 2006.253.08:03:50.38#ibcon#wrote, iclass 25, count 2 2006.253.08:03:50.38#ibcon#about to read 3, iclass 25, count 2 2006.253.08:03:50.40#ibcon#read 3, iclass 25, count 2 2006.253.08:03:50.40#ibcon#about to read 4, iclass 25, count 2 2006.253.08:03:50.40#ibcon#read 4, iclass 25, count 2 2006.253.08:03:50.40#ibcon#about to read 5, iclass 25, count 2 2006.253.08:03:50.40#ibcon#read 5, iclass 25, count 2 2006.253.08:03:50.40#ibcon#about to read 6, iclass 25, count 2 2006.253.08:03:50.40#ibcon#read 6, iclass 25, count 2 2006.253.08:03:50.40#ibcon#end of sib2, iclass 25, count 2 2006.253.08:03:50.40#ibcon#*mode == 0, iclass 25, count 2 2006.253.08:03:50.40#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.253.08:03:50.40#ibcon#[25=AT08-07\r\n] 2006.253.08:03:50.40#ibcon#*before write, iclass 25, count 2 2006.253.08:03:50.40#ibcon#enter sib2, iclass 25, count 2 2006.253.08:03:50.40#ibcon#flushed, iclass 25, count 2 2006.253.08:03:50.40#ibcon#about to write, iclass 25, count 2 2006.253.08:03:50.40#ibcon#wrote, iclass 25, count 2 2006.253.08:03:50.40#ibcon#about to read 3, iclass 25, count 2 2006.253.08:03:50.43#ibcon#read 3, iclass 25, count 2 2006.253.08:03:50.43#ibcon#about to read 4, iclass 25, count 2 2006.253.08:03:50.43#ibcon#read 4, iclass 25, count 2 2006.253.08:03:50.43#ibcon#about to read 5, iclass 25, count 2 2006.253.08:03:50.43#ibcon#read 5, iclass 25, count 2 2006.253.08:03:50.43#ibcon#about to read 6, iclass 25, count 2 2006.253.08:03:50.43#ibcon#read 6, iclass 25, count 2 2006.253.08:03:50.43#ibcon#end of sib2, iclass 25, count 2 2006.253.08:03:50.43#ibcon#*after write, iclass 25, count 2 2006.253.08:03:50.43#ibcon#*before return 0, iclass 25, count 2 2006.253.08:03:50.43#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.253.08:03:50.43#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.253.08:03:50.43#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.253.08:03:50.43#ibcon#ireg 7 cls_cnt 0 2006.253.08:03:50.43#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.253.08:03:50.55#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.253.08:03:50.55#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.253.08:03:50.55#ibcon#enter wrdev, iclass 25, count 0 2006.253.08:03:50.55#ibcon#first serial, iclass 25, count 0 2006.253.08:03:50.55#ibcon#enter sib2, iclass 25, count 0 2006.253.08:03:50.55#ibcon#flushed, iclass 25, count 0 2006.253.08:03:50.55#ibcon#about to write, iclass 25, count 0 2006.253.08:03:50.55#ibcon#wrote, iclass 25, count 0 2006.253.08:03:50.55#ibcon#about to read 3, iclass 25, count 0 2006.253.08:03:50.57#ibcon#read 3, iclass 25, count 0 2006.253.08:03:50.57#ibcon#about to read 4, iclass 25, count 0 2006.253.08:03:50.57#ibcon#read 4, iclass 25, count 0 2006.253.08:03:50.57#ibcon#about to read 5, iclass 25, count 0 2006.253.08:03:50.57#ibcon#read 5, iclass 25, count 0 2006.253.08:03:50.57#ibcon#about to read 6, iclass 25, count 0 2006.253.08:03:50.57#ibcon#read 6, iclass 25, count 0 2006.253.08:03:50.57#ibcon#end of sib2, iclass 25, count 0 2006.253.08:03:50.57#ibcon#*mode == 0, iclass 25, count 0 2006.253.08:03:50.57#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.253.08:03:50.57#ibcon#[25=USB\r\n] 2006.253.08:03:50.57#ibcon#*before write, iclass 25, count 0 2006.253.08:03:50.57#ibcon#enter sib2, iclass 25, count 0 2006.253.08:03:50.57#ibcon#flushed, iclass 25, count 0 2006.253.08:03:50.57#ibcon#about to write, iclass 25, count 0 2006.253.08:03:50.57#ibcon#wrote, iclass 25, count 0 2006.253.08:03:50.57#ibcon#about to read 3, iclass 25, count 0 2006.253.08:03:50.60#ibcon#read 3, iclass 25, count 0 2006.253.08:03:50.60#ibcon#about to read 4, iclass 25, count 0 2006.253.08:03:50.60#ibcon#read 4, iclass 25, count 0 2006.253.08:03:50.60#ibcon#about to read 5, iclass 25, count 0 2006.253.08:03:50.60#ibcon#read 5, iclass 25, count 0 2006.253.08:03:50.60#ibcon#about to read 6, iclass 25, count 0 2006.253.08:03:50.60#ibcon#read 6, iclass 25, count 0 2006.253.08:03:50.60#ibcon#end of sib2, iclass 25, count 0 2006.253.08:03:50.60#ibcon#*after write, iclass 25, count 0 2006.253.08:03:50.60#ibcon#*before return 0, iclass 25, count 0 2006.253.08:03:50.60#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.253.08:03:50.60#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.253.08:03:50.60#ibcon#about to clear, iclass 25 cls_cnt 0 2006.253.08:03:50.60#ibcon#cleared, iclass 25 cls_cnt 0 2006.253.08:03:50.60$vc4f8/vblo=1,632.99 2006.253.08:03:50.60#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.253.08:03:50.60#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.253.08:03:50.60#ibcon#ireg 17 cls_cnt 0 2006.253.08:03:50.60#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.253.08:03:50.60#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.253.08:03:50.60#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.253.08:03:50.60#ibcon#enter wrdev, iclass 27, count 0 2006.253.08:03:50.60#ibcon#first serial, iclass 27, count 0 2006.253.08:03:50.60#ibcon#enter sib2, iclass 27, count 0 2006.253.08:03:50.60#ibcon#flushed, iclass 27, count 0 2006.253.08:03:50.60#ibcon#about to write, iclass 27, count 0 2006.253.08:03:50.60#ibcon#wrote, iclass 27, count 0 2006.253.08:03:50.60#ibcon#about to read 3, iclass 27, count 0 2006.253.08:03:50.62#ibcon#read 3, iclass 27, count 0 2006.253.08:03:50.62#ibcon#about to read 4, iclass 27, count 0 2006.253.08:03:50.62#ibcon#read 4, iclass 27, count 0 2006.253.08:03:50.62#ibcon#about to read 5, iclass 27, count 0 2006.253.08:03:50.62#ibcon#read 5, iclass 27, count 0 2006.253.08:03:50.62#ibcon#about to read 6, iclass 27, count 0 2006.253.08:03:50.62#ibcon#read 6, iclass 27, count 0 2006.253.08:03:50.62#ibcon#end of sib2, iclass 27, count 0 2006.253.08:03:50.62#ibcon#*mode == 0, iclass 27, count 0 2006.253.08:03:50.62#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.253.08:03:50.62#ibcon#[28=FRQ=01,632.99\r\n] 2006.253.08:03:50.62#ibcon#*before write, iclass 27, count 0 2006.253.08:03:50.62#ibcon#enter sib2, iclass 27, count 0 2006.253.08:03:50.62#ibcon#flushed, iclass 27, count 0 2006.253.08:03:50.62#ibcon#about to write, iclass 27, count 0 2006.253.08:03:50.62#ibcon#wrote, iclass 27, count 0 2006.253.08:03:50.62#ibcon#about to read 3, iclass 27, count 0 2006.253.08:03:50.66#ibcon#read 3, iclass 27, count 0 2006.253.08:03:50.66#ibcon#about to read 4, iclass 27, count 0 2006.253.08:03:50.66#ibcon#read 4, iclass 27, count 0 2006.253.08:03:50.66#ibcon#about to read 5, iclass 27, count 0 2006.253.08:03:50.66#ibcon#read 5, iclass 27, count 0 2006.253.08:03:50.66#ibcon#about to read 6, iclass 27, count 0 2006.253.08:03:50.66#ibcon#read 6, iclass 27, count 0 2006.253.08:03:50.66#ibcon#end of sib2, iclass 27, count 0 2006.253.08:03:50.66#ibcon#*after write, iclass 27, count 0 2006.253.08:03:50.66#ibcon#*before return 0, iclass 27, count 0 2006.253.08:03:50.66#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.253.08:03:50.66#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.253.08:03:50.66#ibcon#about to clear, iclass 27 cls_cnt 0 2006.253.08:03:50.66#ibcon#cleared, iclass 27 cls_cnt 0 2006.253.08:03:50.66$vc4f8/vb=1,4 2006.253.08:03:50.66#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.253.08:03:50.66#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.253.08:03:50.66#ibcon#ireg 11 cls_cnt 2 2006.253.08:03:50.66#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.253.08:03:50.66#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.253.08:03:50.66#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.253.08:03:50.66#ibcon#enter wrdev, iclass 29, count 2 2006.253.08:03:50.66#ibcon#first serial, iclass 29, count 2 2006.253.08:03:50.66#ibcon#enter sib2, iclass 29, count 2 2006.253.08:03:50.66#ibcon#flushed, iclass 29, count 2 2006.253.08:03:50.66#ibcon#about to write, iclass 29, count 2 2006.253.08:03:50.66#ibcon#wrote, iclass 29, count 2 2006.253.08:03:50.66#ibcon#about to read 3, iclass 29, count 2 2006.253.08:03:50.68#ibcon#read 3, iclass 29, count 2 2006.253.08:03:50.68#ibcon#about to read 4, iclass 29, count 2 2006.253.08:03:50.68#ibcon#read 4, iclass 29, count 2 2006.253.08:03:50.68#ibcon#about to read 5, iclass 29, count 2 2006.253.08:03:50.68#ibcon#read 5, iclass 29, count 2 2006.253.08:03:50.68#ibcon#about to read 6, iclass 29, count 2 2006.253.08:03:50.68#ibcon#read 6, iclass 29, count 2 2006.253.08:03:50.68#ibcon#end of sib2, iclass 29, count 2 2006.253.08:03:50.68#ibcon#*mode == 0, iclass 29, count 2 2006.253.08:03:50.68#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.253.08:03:50.68#ibcon#[27=AT01-04\r\n] 2006.253.08:03:50.68#ibcon#*before write, iclass 29, count 2 2006.253.08:03:50.68#ibcon#enter sib2, iclass 29, count 2 2006.253.08:03:50.68#ibcon#flushed, iclass 29, count 2 2006.253.08:03:50.68#ibcon#about to write, iclass 29, count 2 2006.253.08:03:50.68#ibcon#wrote, iclass 29, count 2 2006.253.08:03:50.68#ibcon#about to read 3, iclass 29, count 2 2006.253.08:03:50.71#ibcon#read 3, iclass 29, count 2 2006.253.08:03:50.71#ibcon#about to read 4, iclass 29, count 2 2006.253.08:03:50.71#ibcon#read 4, iclass 29, count 2 2006.253.08:03:50.71#ibcon#about to read 5, iclass 29, count 2 2006.253.08:03:50.71#ibcon#read 5, iclass 29, count 2 2006.253.08:03:50.71#ibcon#about to read 6, iclass 29, count 2 2006.253.08:03:50.71#ibcon#read 6, iclass 29, count 2 2006.253.08:03:50.71#ibcon#end of sib2, iclass 29, count 2 2006.253.08:03:50.71#ibcon#*after write, iclass 29, count 2 2006.253.08:03:50.71#ibcon#*before return 0, iclass 29, count 2 2006.253.08:03:50.71#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.253.08:03:50.71#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.253.08:03:50.71#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.253.08:03:50.71#ibcon#ireg 7 cls_cnt 0 2006.253.08:03:50.71#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.253.08:03:50.83#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.253.08:03:50.83#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.253.08:03:50.83#ibcon#enter wrdev, iclass 29, count 0 2006.253.08:03:50.83#ibcon#first serial, iclass 29, count 0 2006.253.08:03:50.83#ibcon#enter sib2, iclass 29, count 0 2006.253.08:03:50.83#ibcon#flushed, iclass 29, count 0 2006.253.08:03:50.83#ibcon#about to write, iclass 29, count 0 2006.253.08:03:50.83#ibcon#wrote, iclass 29, count 0 2006.253.08:03:50.83#ibcon#about to read 3, iclass 29, count 0 2006.253.08:03:50.85#ibcon#read 3, iclass 29, count 0 2006.253.08:03:50.85#ibcon#about to read 4, iclass 29, count 0 2006.253.08:03:50.85#ibcon#read 4, iclass 29, count 0 2006.253.08:03:50.85#ibcon#about to read 5, iclass 29, count 0 2006.253.08:03:50.85#ibcon#read 5, iclass 29, count 0 2006.253.08:03:50.85#ibcon#about to read 6, iclass 29, count 0 2006.253.08:03:50.85#ibcon#read 6, iclass 29, count 0 2006.253.08:03:50.85#ibcon#end of sib2, iclass 29, count 0 2006.253.08:03:50.85#ibcon#*mode == 0, iclass 29, count 0 2006.253.08:03:50.85#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.253.08:03:50.85#ibcon#[27=USB\r\n] 2006.253.08:03:50.85#ibcon#*before write, iclass 29, count 0 2006.253.08:03:50.85#ibcon#enter sib2, iclass 29, count 0 2006.253.08:03:50.85#ibcon#flushed, iclass 29, count 0 2006.253.08:03:50.85#ibcon#about to write, iclass 29, count 0 2006.253.08:03:50.85#ibcon#wrote, iclass 29, count 0 2006.253.08:03:50.85#ibcon#about to read 3, iclass 29, count 0 2006.253.08:03:50.88#ibcon#read 3, iclass 29, count 0 2006.253.08:03:50.88#ibcon#about to read 4, iclass 29, count 0 2006.253.08:03:50.88#ibcon#read 4, iclass 29, count 0 2006.253.08:03:50.88#ibcon#about to read 5, iclass 29, count 0 2006.253.08:03:50.88#ibcon#read 5, iclass 29, count 0 2006.253.08:03:50.88#ibcon#about to read 6, iclass 29, count 0 2006.253.08:03:50.88#ibcon#read 6, iclass 29, count 0 2006.253.08:03:50.88#ibcon#end of sib2, iclass 29, count 0 2006.253.08:03:50.88#ibcon#*after write, iclass 29, count 0 2006.253.08:03:50.88#ibcon#*before return 0, iclass 29, count 0 2006.253.08:03:50.88#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.253.08:03:50.88#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.253.08:03:50.88#ibcon#about to clear, iclass 29 cls_cnt 0 2006.253.08:03:50.88#ibcon#cleared, iclass 29 cls_cnt 0 2006.253.08:03:50.88$vc4f8/vblo=2,640.99 2006.253.08:03:50.88#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.253.08:03:50.88#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.253.08:03:50.88#ibcon#ireg 17 cls_cnt 0 2006.253.08:03:50.88#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.253.08:03:50.88#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.253.08:03:50.88#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.253.08:03:50.88#ibcon#enter wrdev, iclass 31, count 0 2006.253.08:03:50.88#ibcon#first serial, iclass 31, count 0 2006.253.08:03:50.88#ibcon#enter sib2, iclass 31, count 0 2006.253.08:03:50.88#ibcon#flushed, iclass 31, count 0 2006.253.08:03:50.88#ibcon#about to write, iclass 31, count 0 2006.253.08:03:50.88#ibcon#wrote, iclass 31, count 0 2006.253.08:03:50.88#ibcon#about to read 3, iclass 31, count 0 2006.253.08:03:50.90#ibcon#read 3, iclass 31, count 0 2006.253.08:03:50.90#ibcon#about to read 4, iclass 31, count 0 2006.253.08:03:50.90#ibcon#read 4, iclass 31, count 0 2006.253.08:03:50.90#ibcon#about to read 5, iclass 31, count 0 2006.253.08:03:50.90#ibcon#read 5, iclass 31, count 0 2006.253.08:03:50.90#ibcon#about to read 6, iclass 31, count 0 2006.253.08:03:50.90#ibcon#read 6, iclass 31, count 0 2006.253.08:03:50.90#ibcon#end of sib2, iclass 31, count 0 2006.253.08:03:50.90#ibcon#*mode == 0, iclass 31, count 0 2006.253.08:03:50.90#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.253.08:03:50.90#ibcon#[28=FRQ=02,640.99\r\n] 2006.253.08:03:50.90#ibcon#*before write, iclass 31, count 0 2006.253.08:03:50.90#ibcon#enter sib2, iclass 31, count 0 2006.253.08:03:50.90#ibcon#flushed, iclass 31, count 0 2006.253.08:03:50.90#ibcon#about to write, iclass 31, count 0 2006.253.08:03:50.90#ibcon#wrote, iclass 31, count 0 2006.253.08:03:50.90#ibcon#about to read 3, iclass 31, count 0 2006.253.08:03:50.94#ibcon#read 3, iclass 31, count 0 2006.253.08:03:50.94#ibcon#about to read 4, iclass 31, count 0 2006.253.08:03:50.94#ibcon#read 4, iclass 31, count 0 2006.253.08:03:50.94#ibcon#about to read 5, iclass 31, count 0 2006.253.08:03:50.94#ibcon#read 5, iclass 31, count 0 2006.253.08:03:50.94#ibcon#about to read 6, iclass 31, count 0 2006.253.08:03:50.94#ibcon#read 6, iclass 31, count 0 2006.253.08:03:50.94#ibcon#end of sib2, iclass 31, count 0 2006.253.08:03:50.94#ibcon#*after write, iclass 31, count 0 2006.253.08:03:50.94#ibcon#*before return 0, iclass 31, count 0 2006.253.08:03:50.94#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.253.08:03:50.94#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.253.08:03:50.94#ibcon#about to clear, iclass 31 cls_cnt 0 2006.253.08:03:50.94#ibcon#cleared, iclass 31 cls_cnt 0 2006.253.08:03:50.94$vc4f8/vb=2,5 2006.253.08:03:50.94#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.253.08:03:50.94#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.253.08:03:50.94#ibcon#ireg 11 cls_cnt 2 2006.253.08:03:50.94#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.253.08:03:51.00#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.253.08:03:51.00#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.253.08:03:51.00#ibcon#enter wrdev, iclass 33, count 2 2006.253.08:03:51.00#ibcon#first serial, iclass 33, count 2 2006.253.08:03:51.00#ibcon#enter sib2, iclass 33, count 2 2006.253.08:03:51.00#ibcon#flushed, iclass 33, count 2 2006.253.08:03:51.00#ibcon#about to write, iclass 33, count 2 2006.253.08:03:51.00#ibcon#wrote, iclass 33, count 2 2006.253.08:03:51.00#ibcon#about to read 3, iclass 33, count 2 2006.253.08:03:51.02#ibcon#read 3, iclass 33, count 2 2006.253.08:03:51.02#ibcon#about to read 4, iclass 33, count 2 2006.253.08:03:51.02#ibcon#read 4, iclass 33, count 2 2006.253.08:03:51.02#ibcon#about to read 5, iclass 33, count 2 2006.253.08:03:51.02#ibcon#read 5, iclass 33, count 2 2006.253.08:03:51.02#ibcon#about to read 6, iclass 33, count 2 2006.253.08:03:51.02#ibcon#read 6, iclass 33, count 2 2006.253.08:03:51.02#ibcon#end of sib2, iclass 33, count 2 2006.253.08:03:51.02#ibcon#*mode == 0, iclass 33, count 2 2006.253.08:03:51.02#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.253.08:03:51.02#ibcon#[27=AT02-05\r\n] 2006.253.08:03:51.02#ibcon#*before write, iclass 33, count 2 2006.253.08:03:51.02#ibcon#enter sib2, iclass 33, count 2 2006.253.08:03:51.02#ibcon#flushed, iclass 33, count 2 2006.253.08:03:51.02#ibcon#about to write, iclass 33, count 2 2006.253.08:03:51.02#ibcon#wrote, iclass 33, count 2 2006.253.08:03:51.02#ibcon#about to read 3, iclass 33, count 2 2006.253.08:03:51.05#ibcon#read 3, iclass 33, count 2 2006.253.08:03:51.05#ibcon#about to read 4, iclass 33, count 2 2006.253.08:03:51.05#ibcon#read 4, iclass 33, count 2 2006.253.08:03:51.05#ibcon#about to read 5, iclass 33, count 2 2006.253.08:03:51.05#ibcon#read 5, iclass 33, count 2 2006.253.08:03:51.05#ibcon#about to read 6, iclass 33, count 2 2006.253.08:03:51.05#ibcon#read 6, iclass 33, count 2 2006.253.08:03:51.05#ibcon#end of sib2, iclass 33, count 2 2006.253.08:03:51.05#ibcon#*after write, iclass 33, count 2 2006.253.08:03:51.05#ibcon#*before return 0, iclass 33, count 2 2006.253.08:03:51.05#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.253.08:03:51.05#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.253.08:03:51.05#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.253.08:03:51.05#ibcon#ireg 7 cls_cnt 0 2006.253.08:03:51.05#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.253.08:03:51.17#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.253.08:03:51.17#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.253.08:03:51.17#ibcon#enter wrdev, iclass 33, count 0 2006.253.08:03:51.17#ibcon#first serial, iclass 33, count 0 2006.253.08:03:51.17#ibcon#enter sib2, iclass 33, count 0 2006.253.08:03:51.17#ibcon#flushed, iclass 33, count 0 2006.253.08:03:51.17#ibcon#about to write, iclass 33, count 0 2006.253.08:03:51.17#ibcon#wrote, iclass 33, count 0 2006.253.08:03:51.17#ibcon#about to read 3, iclass 33, count 0 2006.253.08:03:51.20#ibcon#read 3, iclass 33, count 0 2006.253.08:03:51.20#ibcon#about to read 4, iclass 33, count 0 2006.253.08:03:51.20#ibcon#read 4, iclass 33, count 0 2006.253.08:03:51.20#ibcon#about to read 5, iclass 33, count 0 2006.253.08:03:51.20#ibcon#read 5, iclass 33, count 0 2006.253.08:03:51.20#ibcon#about to read 6, iclass 33, count 0 2006.253.08:03:51.20#ibcon#read 6, iclass 33, count 0 2006.253.08:03:51.20#ibcon#end of sib2, iclass 33, count 0 2006.253.08:03:51.20#ibcon#*mode == 0, iclass 33, count 0 2006.253.08:03:51.20#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.253.08:03:51.20#ibcon#[27=USB\r\n] 2006.253.08:03:51.20#ibcon#*before write, iclass 33, count 0 2006.253.08:03:51.20#ibcon#enter sib2, iclass 33, count 0 2006.253.08:03:51.20#ibcon#flushed, iclass 33, count 0 2006.253.08:03:51.20#ibcon#about to write, iclass 33, count 0 2006.253.08:03:51.21#ibcon#wrote, iclass 33, count 0 2006.253.08:03:51.21#ibcon#about to read 3, iclass 33, count 0 2006.253.08:03:51.23#ibcon#read 3, iclass 33, count 0 2006.253.08:03:51.23#ibcon#about to read 4, iclass 33, count 0 2006.253.08:03:51.23#ibcon#read 4, iclass 33, count 0 2006.253.08:03:51.23#ibcon#about to read 5, iclass 33, count 0 2006.253.08:03:51.23#ibcon#read 5, iclass 33, count 0 2006.253.08:03:51.23#ibcon#about to read 6, iclass 33, count 0 2006.253.08:03:51.23#ibcon#read 6, iclass 33, count 0 2006.253.08:03:51.23#ibcon#end of sib2, iclass 33, count 0 2006.253.08:03:51.23#ibcon#*after write, iclass 33, count 0 2006.253.08:03:51.23#ibcon#*before return 0, iclass 33, count 0 2006.253.08:03:51.23#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.253.08:03:51.23#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.253.08:03:51.23#ibcon#about to clear, iclass 33 cls_cnt 0 2006.253.08:03:51.23#ibcon#cleared, iclass 33 cls_cnt 0 2006.253.08:03:51.23$vc4f8/vblo=3,656.99 2006.253.08:03:51.23#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.253.08:03:51.23#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.253.08:03:51.23#ibcon#ireg 17 cls_cnt 0 2006.253.08:03:51.23#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.253.08:03:51.23#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.253.08:03:51.23#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.253.08:03:51.23#ibcon#enter wrdev, iclass 35, count 0 2006.253.08:03:51.23#ibcon#first serial, iclass 35, count 0 2006.253.08:03:51.23#ibcon#enter sib2, iclass 35, count 0 2006.253.08:03:51.23#ibcon#flushed, iclass 35, count 0 2006.253.08:03:51.23#ibcon#about to write, iclass 35, count 0 2006.253.08:03:51.23#ibcon#wrote, iclass 35, count 0 2006.253.08:03:51.23#ibcon#about to read 3, iclass 35, count 0 2006.253.08:03:51.25#ibcon#read 3, iclass 35, count 0 2006.253.08:03:51.25#ibcon#about to read 4, iclass 35, count 0 2006.253.08:03:51.25#ibcon#read 4, iclass 35, count 0 2006.253.08:03:51.25#ibcon#about to read 5, iclass 35, count 0 2006.253.08:03:51.25#ibcon#read 5, iclass 35, count 0 2006.253.08:03:51.25#ibcon#about to read 6, iclass 35, count 0 2006.253.08:03:51.25#ibcon#read 6, iclass 35, count 0 2006.253.08:03:51.25#ibcon#end of sib2, iclass 35, count 0 2006.253.08:03:51.25#ibcon#*mode == 0, iclass 35, count 0 2006.253.08:03:51.25#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.253.08:03:51.25#ibcon#[28=FRQ=03,656.99\r\n] 2006.253.08:03:51.25#ibcon#*before write, iclass 35, count 0 2006.253.08:03:51.25#ibcon#enter sib2, iclass 35, count 0 2006.253.08:03:51.25#ibcon#flushed, iclass 35, count 0 2006.253.08:03:51.25#ibcon#about to write, iclass 35, count 0 2006.253.08:03:51.25#ibcon#wrote, iclass 35, count 0 2006.253.08:03:51.25#ibcon#about to read 3, iclass 35, count 0 2006.253.08:03:51.29#ibcon#read 3, iclass 35, count 0 2006.253.08:03:51.29#ibcon#about to read 4, iclass 35, count 0 2006.253.08:03:51.29#ibcon#read 4, iclass 35, count 0 2006.253.08:03:51.29#ibcon#about to read 5, iclass 35, count 0 2006.253.08:03:51.29#ibcon#read 5, iclass 35, count 0 2006.253.08:03:51.29#ibcon#about to read 6, iclass 35, count 0 2006.253.08:03:51.29#ibcon#read 6, iclass 35, count 0 2006.253.08:03:51.29#ibcon#end of sib2, iclass 35, count 0 2006.253.08:03:51.29#ibcon#*after write, iclass 35, count 0 2006.253.08:03:51.29#ibcon#*before return 0, iclass 35, count 0 2006.253.08:03:51.29#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.253.08:03:51.29#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.253.08:03:51.29#ibcon#about to clear, iclass 35 cls_cnt 0 2006.253.08:03:51.29#ibcon#cleared, iclass 35 cls_cnt 0 2006.253.08:03:51.29$vc4f8/vb=3,4 2006.253.08:03:51.29#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.253.08:03:51.29#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.253.08:03:51.29#ibcon#ireg 11 cls_cnt 2 2006.253.08:03:51.29#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.253.08:03:51.35#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.253.08:03:51.35#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.253.08:03:51.35#ibcon#enter wrdev, iclass 37, count 2 2006.253.08:03:51.35#ibcon#first serial, iclass 37, count 2 2006.253.08:03:51.35#ibcon#enter sib2, iclass 37, count 2 2006.253.08:03:51.35#ibcon#flushed, iclass 37, count 2 2006.253.08:03:51.35#ibcon#about to write, iclass 37, count 2 2006.253.08:03:51.35#ibcon#wrote, iclass 37, count 2 2006.253.08:03:51.35#ibcon#about to read 3, iclass 37, count 2 2006.253.08:03:51.37#ibcon#read 3, iclass 37, count 2 2006.253.08:03:51.37#ibcon#about to read 4, iclass 37, count 2 2006.253.08:03:51.37#ibcon#read 4, iclass 37, count 2 2006.253.08:03:51.37#ibcon#about to read 5, iclass 37, count 2 2006.253.08:03:51.37#ibcon#read 5, iclass 37, count 2 2006.253.08:03:51.37#ibcon#about to read 6, iclass 37, count 2 2006.253.08:03:51.37#ibcon#read 6, iclass 37, count 2 2006.253.08:03:51.37#ibcon#end of sib2, iclass 37, count 2 2006.253.08:03:51.37#ibcon#*mode == 0, iclass 37, count 2 2006.253.08:03:51.37#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.253.08:03:51.37#ibcon#[27=AT03-04\r\n] 2006.253.08:03:51.37#ibcon#*before write, iclass 37, count 2 2006.253.08:03:51.37#ibcon#enter sib2, iclass 37, count 2 2006.253.08:03:51.37#ibcon#flushed, iclass 37, count 2 2006.253.08:03:51.37#ibcon#about to write, iclass 37, count 2 2006.253.08:03:51.37#ibcon#wrote, iclass 37, count 2 2006.253.08:03:51.37#ibcon#about to read 3, iclass 37, count 2 2006.253.08:03:51.40#ibcon#read 3, iclass 37, count 2 2006.253.08:03:51.40#ibcon#about to read 4, iclass 37, count 2 2006.253.08:03:51.40#ibcon#read 4, iclass 37, count 2 2006.253.08:03:51.40#ibcon#about to read 5, iclass 37, count 2 2006.253.08:03:51.40#ibcon#read 5, iclass 37, count 2 2006.253.08:03:51.40#ibcon#about to read 6, iclass 37, count 2 2006.253.08:03:51.40#ibcon#read 6, iclass 37, count 2 2006.253.08:03:51.40#ibcon#end of sib2, iclass 37, count 2 2006.253.08:03:51.40#ibcon#*after write, iclass 37, count 2 2006.253.08:03:51.40#ibcon#*before return 0, iclass 37, count 2 2006.253.08:03:51.40#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.253.08:03:51.40#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.253.08:03:51.40#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.253.08:03:51.40#ibcon#ireg 7 cls_cnt 0 2006.253.08:03:51.40#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.253.08:03:51.52#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.253.08:03:51.52#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.253.08:03:51.52#ibcon#enter wrdev, iclass 37, count 0 2006.253.08:03:51.52#ibcon#first serial, iclass 37, count 0 2006.253.08:03:51.52#ibcon#enter sib2, iclass 37, count 0 2006.253.08:03:51.52#ibcon#flushed, iclass 37, count 0 2006.253.08:03:51.52#ibcon#about to write, iclass 37, count 0 2006.253.08:03:51.52#ibcon#wrote, iclass 37, count 0 2006.253.08:03:51.52#ibcon#about to read 3, iclass 37, count 0 2006.253.08:03:51.54#ibcon#read 3, iclass 37, count 0 2006.253.08:03:51.54#ibcon#about to read 4, iclass 37, count 0 2006.253.08:03:51.54#ibcon#read 4, iclass 37, count 0 2006.253.08:03:51.54#ibcon#about to read 5, iclass 37, count 0 2006.253.08:03:51.54#ibcon#read 5, iclass 37, count 0 2006.253.08:03:51.54#ibcon#about to read 6, iclass 37, count 0 2006.253.08:03:51.54#ibcon#read 6, iclass 37, count 0 2006.253.08:03:51.54#ibcon#end of sib2, iclass 37, count 0 2006.253.08:03:51.54#ibcon#*mode == 0, iclass 37, count 0 2006.253.08:03:51.54#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.253.08:03:51.54#ibcon#[27=USB\r\n] 2006.253.08:03:51.54#ibcon#*before write, iclass 37, count 0 2006.253.08:03:51.54#ibcon#enter sib2, iclass 37, count 0 2006.253.08:03:51.54#ibcon#flushed, iclass 37, count 0 2006.253.08:03:51.54#ibcon#about to write, iclass 37, count 0 2006.253.08:03:51.54#ibcon#wrote, iclass 37, count 0 2006.253.08:03:51.54#ibcon#about to read 3, iclass 37, count 0 2006.253.08:03:51.57#ibcon#read 3, iclass 37, count 0 2006.253.08:03:51.57#ibcon#about to read 4, iclass 37, count 0 2006.253.08:03:51.57#ibcon#read 4, iclass 37, count 0 2006.253.08:03:51.57#ibcon#about to read 5, iclass 37, count 0 2006.253.08:03:51.57#ibcon#read 5, iclass 37, count 0 2006.253.08:03:51.57#ibcon#about to read 6, iclass 37, count 0 2006.253.08:03:51.57#ibcon#read 6, iclass 37, count 0 2006.253.08:03:51.57#ibcon#end of sib2, iclass 37, count 0 2006.253.08:03:51.57#ibcon#*after write, iclass 37, count 0 2006.253.08:03:51.57#ibcon#*before return 0, iclass 37, count 0 2006.253.08:03:51.57#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.253.08:03:51.57#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.253.08:03:51.57#ibcon#about to clear, iclass 37 cls_cnt 0 2006.253.08:03:51.57#ibcon#cleared, iclass 37 cls_cnt 0 2006.253.08:03:51.57$vc4f8/vblo=4,712.99 2006.253.08:03:51.57#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.253.08:03:51.57#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.253.08:03:51.57#ibcon#ireg 17 cls_cnt 0 2006.253.08:03:51.57#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.253.08:03:51.57#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.253.08:03:51.57#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.253.08:03:51.57#ibcon#enter wrdev, iclass 39, count 0 2006.253.08:03:51.57#ibcon#first serial, iclass 39, count 0 2006.253.08:03:51.57#ibcon#enter sib2, iclass 39, count 0 2006.253.08:03:51.57#ibcon#flushed, iclass 39, count 0 2006.253.08:03:51.57#ibcon#about to write, iclass 39, count 0 2006.253.08:03:51.57#ibcon#wrote, iclass 39, count 0 2006.253.08:03:51.57#ibcon#about to read 3, iclass 39, count 0 2006.253.08:03:51.59#ibcon#read 3, iclass 39, count 0 2006.253.08:03:51.59#ibcon#about to read 4, iclass 39, count 0 2006.253.08:03:51.59#ibcon#read 4, iclass 39, count 0 2006.253.08:03:51.59#ibcon#about to read 5, iclass 39, count 0 2006.253.08:03:51.59#ibcon#read 5, iclass 39, count 0 2006.253.08:03:51.59#ibcon#about to read 6, iclass 39, count 0 2006.253.08:03:51.59#ibcon#read 6, iclass 39, count 0 2006.253.08:03:51.59#ibcon#end of sib2, iclass 39, count 0 2006.253.08:03:51.59#ibcon#*mode == 0, iclass 39, count 0 2006.253.08:03:51.59#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.253.08:03:51.59#ibcon#[28=FRQ=04,712.99\r\n] 2006.253.08:03:51.59#ibcon#*before write, iclass 39, count 0 2006.253.08:03:51.59#ibcon#enter sib2, iclass 39, count 0 2006.253.08:03:51.59#ibcon#flushed, iclass 39, count 0 2006.253.08:03:51.59#ibcon#about to write, iclass 39, count 0 2006.253.08:03:51.59#ibcon#wrote, iclass 39, count 0 2006.253.08:03:51.59#ibcon#about to read 3, iclass 39, count 0 2006.253.08:03:51.63#ibcon#read 3, iclass 39, count 0 2006.253.08:03:51.63#ibcon#about to read 4, iclass 39, count 0 2006.253.08:03:51.63#ibcon#read 4, iclass 39, count 0 2006.253.08:03:51.63#ibcon#about to read 5, iclass 39, count 0 2006.253.08:03:51.63#ibcon#read 5, iclass 39, count 0 2006.253.08:03:51.63#ibcon#about to read 6, iclass 39, count 0 2006.253.08:03:51.63#ibcon#read 6, iclass 39, count 0 2006.253.08:03:51.63#ibcon#end of sib2, iclass 39, count 0 2006.253.08:03:51.63#ibcon#*after write, iclass 39, count 0 2006.253.08:03:51.63#ibcon#*before return 0, iclass 39, count 0 2006.253.08:03:51.63#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.253.08:03:51.63#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.253.08:03:51.63#ibcon#about to clear, iclass 39 cls_cnt 0 2006.253.08:03:51.63#ibcon#cleared, iclass 39 cls_cnt 0 2006.253.08:03:51.63$vc4f8/vb=4,4 2006.253.08:03:51.63#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.253.08:03:51.63#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.253.08:03:51.63#ibcon#ireg 11 cls_cnt 2 2006.253.08:03:51.63#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.253.08:03:51.69#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.253.08:03:51.69#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.253.08:03:51.69#ibcon#enter wrdev, iclass 3, count 2 2006.253.08:03:51.69#ibcon#first serial, iclass 3, count 2 2006.253.08:03:51.69#ibcon#enter sib2, iclass 3, count 2 2006.253.08:03:51.69#ibcon#flushed, iclass 3, count 2 2006.253.08:03:51.69#ibcon#about to write, iclass 3, count 2 2006.253.08:03:51.69#ibcon#wrote, iclass 3, count 2 2006.253.08:03:51.69#ibcon#about to read 3, iclass 3, count 2 2006.253.08:03:51.71#ibcon#read 3, iclass 3, count 2 2006.253.08:03:51.71#ibcon#about to read 4, iclass 3, count 2 2006.253.08:03:51.71#ibcon#read 4, iclass 3, count 2 2006.253.08:03:51.71#ibcon#about to read 5, iclass 3, count 2 2006.253.08:03:51.71#ibcon#read 5, iclass 3, count 2 2006.253.08:03:51.71#ibcon#about to read 6, iclass 3, count 2 2006.253.08:03:51.71#ibcon#read 6, iclass 3, count 2 2006.253.08:03:51.71#ibcon#end of sib2, iclass 3, count 2 2006.253.08:03:51.71#ibcon#*mode == 0, iclass 3, count 2 2006.253.08:03:51.71#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.253.08:03:51.71#ibcon#[27=AT04-04\r\n] 2006.253.08:03:51.71#ibcon#*before write, iclass 3, count 2 2006.253.08:03:51.71#ibcon#enter sib2, iclass 3, count 2 2006.253.08:03:51.71#ibcon#flushed, iclass 3, count 2 2006.253.08:03:51.71#ibcon#about to write, iclass 3, count 2 2006.253.08:03:51.71#ibcon#wrote, iclass 3, count 2 2006.253.08:03:51.71#ibcon#about to read 3, iclass 3, count 2 2006.253.08:03:51.74#ibcon#read 3, iclass 3, count 2 2006.253.08:03:51.74#ibcon#about to read 4, iclass 3, count 2 2006.253.08:03:51.74#ibcon#read 4, iclass 3, count 2 2006.253.08:03:51.74#ibcon#about to read 5, iclass 3, count 2 2006.253.08:03:51.74#ibcon#read 5, iclass 3, count 2 2006.253.08:03:51.74#ibcon#about to read 6, iclass 3, count 2 2006.253.08:03:51.74#ibcon#read 6, iclass 3, count 2 2006.253.08:03:51.74#ibcon#end of sib2, iclass 3, count 2 2006.253.08:03:51.74#ibcon#*after write, iclass 3, count 2 2006.253.08:03:51.74#ibcon#*before return 0, iclass 3, count 2 2006.253.08:03:51.74#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.253.08:03:51.74#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.253.08:03:51.74#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.253.08:03:51.74#ibcon#ireg 7 cls_cnt 0 2006.253.08:03:51.74#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.253.08:03:51.86#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.253.08:03:51.86#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.253.08:03:51.86#ibcon#enter wrdev, iclass 3, count 0 2006.253.08:03:51.86#ibcon#first serial, iclass 3, count 0 2006.253.08:03:51.86#ibcon#enter sib2, iclass 3, count 0 2006.253.08:03:51.86#ibcon#flushed, iclass 3, count 0 2006.253.08:03:51.86#ibcon#about to write, iclass 3, count 0 2006.253.08:03:51.86#ibcon#wrote, iclass 3, count 0 2006.253.08:03:51.86#ibcon#about to read 3, iclass 3, count 0 2006.253.08:03:51.88#ibcon#read 3, iclass 3, count 0 2006.253.08:03:51.88#ibcon#about to read 4, iclass 3, count 0 2006.253.08:03:51.88#ibcon#read 4, iclass 3, count 0 2006.253.08:03:51.88#ibcon#about to read 5, iclass 3, count 0 2006.253.08:03:51.88#ibcon#read 5, iclass 3, count 0 2006.253.08:03:51.88#ibcon#about to read 6, iclass 3, count 0 2006.253.08:03:51.88#ibcon#read 6, iclass 3, count 0 2006.253.08:03:51.88#ibcon#end of sib2, iclass 3, count 0 2006.253.08:03:51.88#ibcon#*mode == 0, iclass 3, count 0 2006.253.08:03:51.88#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.253.08:03:51.88#ibcon#[27=USB\r\n] 2006.253.08:03:51.88#ibcon#*before write, iclass 3, count 0 2006.253.08:03:51.88#ibcon#enter sib2, iclass 3, count 0 2006.253.08:03:51.88#ibcon#flushed, iclass 3, count 0 2006.253.08:03:51.88#ibcon#about to write, iclass 3, count 0 2006.253.08:03:51.88#ibcon#wrote, iclass 3, count 0 2006.253.08:03:51.88#ibcon#about to read 3, iclass 3, count 0 2006.253.08:03:51.91#ibcon#read 3, iclass 3, count 0 2006.253.08:03:51.91#ibcon#about to read 4, iclass 3, count 0 2006.253.08:03:51.91#ibcon#read 4, iclass 3, count 0 2006.253.08:03:51.91#ibcon#about to read 5, iclass 3, count 0 2006.253.08:03:51.91#ibcon#read 5, iclass 3, count 0 2006.253.08:03:51.91#ibcon#about to read 6, iclass 3, count 0 2006.253.08:03:51.91#ibcon#read 6, iclass 3, count 0 2006.253.08:03:51.91#ibcon#end of sib2, iclass 3, count 0 2006.253.08:03:51.91#ibcon#*after write, iclass 3, count 0 2006.253.08:03:51.91#ibcon#*before return 0, iclass 3, count 0 2006.253.08:03:51.91#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.253.08:03:51.91#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.253.08:03:51.91#ibcon#about to clear, iclass 3 cls_cnt 0 2006.253.08:03:51.91#ibcon#cleared, iclass 3 cls_cnt 0 2006.253.08:03:51.91$vc4f8/vblo=5,744.99 2006.253.08:03:51.91#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.253.08:03:51.91#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.253.08:03:51.91#ibcon#ireg 17 cls_cnt 0 2006.253.08:03:51.91#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.253.08:03:51.91#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.253.08:03:51.91#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.253.08:03:51.91#ibcon#enter wrdev, iclass 5, count 0 2006.253.08:03:51.91#ibcon#first serial, iclass 5, count 0 2006.253.08:03:51.91#ibcon#enter sib2, iclass 5, count 0 2006.253.08:03:51.91#ibcon#flushed, iclass 5, count 0 2006.253.08:03:51.91#ibcon#about to write, iclass 5, count 0 2006.253.08:03:51.91#ibcon#wrote, iclass 5, count 0 2006.253.08:03:51.91#ibcon#about to read 3, iclass 5, count 0 2006.253.08:03:51.94#ibcon#read 3, iclass 5, count 0 2006.253.08:03:51.94#ibcon#about to read 4, iclass 5, count 0 2006.253.08:03:51.94#ibcon#read 4, iclass 5, count 0 2006.253.08:03:51.94#ibcon#about to read 5, iclass 5, count 0 2006.253.08:03:51.94#ibcon#read 5, iclass 5, count 0 2006.253.08:03:51.94#ibcon#about to read 6, iclass 5, count 0 2006.253.08:03:51.94#ibcon#read 6, iclass 5, count 0 2006.253.08:03:51.94#ibcon#end of sib2, iclass 5, count 0 2006.253.08:03:51.94#ibcon#*mode == 0, iclass 5, count 0 2006.253.08:03:51.94#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.253.08:03:51.94#ibcon#[28=FRQ=05,744.99\r\n] 2006.253.08:03:51.94#ibcon#*before write, iclass 5, count 0 2006.253.08:03:51.94#ibcon#enter sib2, iclass 5, count 0 2006.253.08:03:51.94#ibcon#flushed, iclass 5, count 0 2006.253.08:03:51.94#ibcon#about to write, iclass 5, count 0 2006.253.08:03:51.94#ibcon#wrote, iclass 5, count 0 2006.253.08:03:51.94#ibcon#about to read 3, iclass 5, count 0 2006.253.08:03:51.98#ibcon#read 3, iclass 5, count 0 2006.253.08:03:51.98#ibcon#about to read 4, iclass 5, count 0 2006.253.08:03:51.98#ibcon#read 4, iclass 5, count 0 2006.253.08:03:51.98#ibcon#about to read 5, iclass 5, count 0 2006.253.08:03:51.98#ibcon#read 5, iclass 5, count 0 2006.253.08:03:51.98#ibcon#about to read 6, iclass 5, count 0 2006.253.08:03:51.98#ibcon#read 6, iclass 5, count 0 2006.253.08:03:51.98#ibcon#end of sib2, iclass 5, count 0 2006.253.08:03:51.98#ibcon#*after write, iclass 5, count 0 2006.253.08:03:51.98#ibcon#*before return 0, iclass 5, count 0 2006.253.08:03:51.98#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.253.08:03:51.98#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.253.08:03:51.98#ibcon#about to clear, iclass 5 cls_cnt 0 2006.253.08:03:51.98#ibcon#cleared, iclass 5 cls_cnt 0 2006.253.08:03:51.98$vc4f8/vb=5,4 2006.253.08:03:51.98#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.253.08:03:51.98#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.253.08:03:51.98#ibcon#ireg 11 cls_cnt 2 2006.253.08:03:51.98#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.253.08:03:52.03#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.253.08:03:52.03#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.253.08:03:52.03#ibcon#enter wrdev, iclass 7, count 2 2006.253.08:03:52.03#ibcon#first serial, iclass 7, count 2 2006.253.08:03:52.03#ibcon#enter sib2, iclass 7, count 2 2006.253.08:03:52.03#ibcon#flushed, iclass 7, count 2 2006.253.08:03:52.03#ibcon#about to write, iclass 7, count 2 2006.253.08:03:52.03#ibcon#wrote, iclass 7, count 2 2006.253.08:03:52.03#ibcon#about to read 3, iclass 7, count 2 2006.253.08:03:52.05#ibcon#read 3, iclass 7, count 2 2006.253.08:03:52.05#ibcon#about to read 4, iclass 7, count 2 2006.253.08:03:52.05#ibcon#read 4, iclass 7, count 2 2006.253.08:03:52.05#ibcon#about to read 5, iclass 7, count 2 2006.253.08:03:52.05#ibcon#read 5, iclass 7, count 2 2006.253.08:03:52.05#ibcon#about to read 6, iclass 7, count 2 2006.253.08:03:52.05#ibcon#read 6, iclass 7, count 2 2006.253.08:03:52.05#ibcon#end of sib2, iclass 7, count 2 2006.253.08:03:52.05#ibcon#*mode == 0, iclass 7, count 2 2006.253.08:03:52.05#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.253.08:03:52.05#ibcon#[27=AT05-04\r\n] 2006.253.08:03:52.05#ibcon#*before write, iclass 7, count 2 2006.253.08:03:52.05#ibcon#enter sib2, iclass 7, count 2 2006.253.08:03:52.05#ibcon#flushed, iclass 7, count 2 2006.253.08:03:52.05#ibcon#about to write, iclass 7, count 2 2006.253.08:03:52.05#ibcon#wrote, iclass 7, count 2 2006.253.08:03:52.05#ibcon#about to read 3, iclass 7, count 2 2006.253.08:03:52.08#ibcon#read 3, iclass 7, count 2 2006.253.08:03:52.08#ibcon#about to read 4, iclass 7, count 2 2006.253.08:03:52.08#ibcon#read 4, iclass 7, count 2 2006.253.08:03:52.08#ibcon#about to read 5, iclass 7, count 2 2006.253.08:03:52.08#ibcon#read 5, iclass 7, count 2 2006.253.08:03:52.08#ibcon#about to read 6, iclass 7, count 2 2006.253.08:03:52.08#ibcon#read 6, iclass 7, count 2 2006.253.08:03:52.08#ibcon#end of sib2, iclass 7, count 2 2006.253.08:03:52.08#ibcon#*after write, iclass 7, count 2 2006.253.08:03:52.08#ibcon#*before return 0, iclass 7, count 2 2006.253.08:03:52.08#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.253.08:03:52.08#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.253.08:03:52.08#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.253.08:03:52.08#ibcon#ireg 7 cls_cnt 0 2006.253.08:03:52.08#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.253.08:03:52.20#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.253.08:03:52.20#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.253.08:03:52.20#ibcon#enter wrdev, iclass 7, count 0 2006.253.08:03:52.20#ibcon#first serial, iclass 7, count 0 2006.253.08:03:52.20#ibcon#enter sib2, iclass 7, count 0 2006.253.08:03:52.20#ibcon#flushed, iclass 7, count 0 2006.253.08:03:52.20#ibcon#about to write, iclass 7, count 0 2006.253.08:03:52.20#ibcon#wrote, iclass 7, count 0 2006.253.08:03:52.20#ibcon#about to read 3, iclass 7, count 0 2006.253.08:03:52.22#ibcon#read 3, iclass 7, count 0 2006.253.08:03:52.22#ibcon#about to read 4, iclass 7, count 0 2006.253.08:03:52.22#ibcon#read 4, iclass 7, count 0 2006.253.08:03:52.22#ibcon#about to read 5, iclass 7, count 0 2006.253.08:03:52.22#ibcon#read 5, iclass 7, count 0 2006.253.08:03:52.22#ibcon#about to read 6, iclass 7, count 0 2006.253.08:03:52.22#ibcon#read 6, iclass 7, count 0 2006.253.08:03:52.22#ibcon#end of sib2, iclass 7, count 0 2006.253.08:03:52.22#ibcon#*mode == 0, iclass 7, count 0 2006.253.08:03:52.22#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.253.08:03:52.22#ibcon#[27=USB\r\n] 2006.253.08:03:52.22#ibcon#*before write, iclass 7, count 0 2006.253.08:03:52.22#ibcon#enter sib2, iclass 7, count 0 2006.253.08:03:52.22#ibcon#flushed, iclass 7, count 0 2006.253.08:03:52.22#ibcon#about to write, iclass 7, count 0 2006.253.08:03:52.22#ibcon#wrote, iclass 7, count 0 2006.253.08:03:52.22#ibcon#about to read 3, iclass 7, count 0 2006.253.08:03:52.25#ibcon#read 3, iclass 7, count 0 2006.253.08:03:52.25#ibcon#about to read 4, iclass 7, count 0 2006.253.08:03:52.25#ibcon#read 4, iclass 7, count 0 2006.253.08:03:52.25#ibcon#about to read 5, iclass 7, count 0 2006.253.08:03:52.25#ibcon#read 5, iclass 7, count 0 2006.253.08:03:52.25#ibcon#about to read 6, iclass 7, count 0 2006.253.08:03:52.25#ibcon#read 6, iclass 7, count 0 2006.253.08:03:52.25#ibcon#end of sib2, iclass 7, count 0 2006.253.08:03:52.25#ibcon#*after write, iclass 7, count 0 2006.253.08:03:52.25#ibcon#*before return 0, iclass 7, count 0 2006.253.08:03:52.25#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.253.08:03:52.25#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.253.08:03:52.25#ibcon#about to clear, iclass 7 cls_cnt 0 2006.253.08:03:52.25#ibcon#cleared, iclass 7 cls_cnt 0 2006.253.08:03:52.25$vc4f8/vblo=6,752.99 2006.253.08:03:52.25#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.253.08:03:52.25#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.253.08:03:52.25#ibcon#ireg 17 cls_cnt 0 2006.253.08:03:52.25#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.253.08:03:52.25#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.253.08:03:52.25#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.253.08:03:52.25#ibcon#enter wrdev, iclass 11, count 0 2006.253.08:03:52.25#ibcon#first serial, iclass 11, count 0 2006.253.08:03:52.25#ibcon#enter sib2, iclass 11, count 0 2006.253.08:03:52.25#ibcon#flushed, iclass 11, count 0 2006.253.08:03:52.25#ibcon#about to write, iclass 11, count 0 2006.253.08:03:52.25#ibcon#wrote, iclass 11, count 0 2006.253.08:03:52.25#ibcon#about to read 3, iclass 11, count 0 2006.253.08:03:52.27#ibcon#read 3, iclass 11, count 0 2006.253.08:03:52.27#ibcon#about to read 4, iclass 11, count 0 2006.253.08:03:52.27#ibcon#read 4, iclass 11, count 0 2006.253.08:03:52.27#ibcon#about to read 5, iclass 11, count 0 2006.253.08:03:52.27#ibcon#read 5, iclass 11, count 0 2006.253.08:03:52.27#ibcon#about to read 6, iclass 11, count 0 2006.253.08:03:52.27#ibcon#read 6, iclass 11, count 0 2006.253.08:03:52.27#ibcon#end of sib2, iclass 11, count 0 2006.253.08:03:52.27#ibcon#*mode == 0, iclass 11, count 0 2006.253.08:03:52.27#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.253.08:03:52.27#ibcon#[28=FRQ=06,752.99\r\n] 2006.253.08:03:52.27#ibcon#*before write, iclass 11, count 0 2006.253.08:03:52.27#ibcon#enter sib2, iclass 11, count 0 2006.253.08:03:52.27#ibcon#flushed, iclass 11, count 0 2006.253.08:03:52.27#ibcon#about to write, iclass 11, count 0 2006.253.08:03:52.27#ibcon#wrote, iclass 11, count 0 2006.253.08:03:52.27#ibcon#about to read 3, iclass 11, count 0 2006.253.08:03:52.31#ibcon#read 3, iclass 11, count 0 2006.253.08:03:52.31#ibcon#about to read 4, iclass 11, count 0 2006.253.08:03:52.31#ibcon#read 4, iclass 11, count 0 2006.253.08:03:52.31#ibcon#about to read 5, iclass 11, count 0 2006.253.08:03:52.31#ibcon#read 5, iclass 11, count 0 2006.253.08:03:52.31#ibcon#about to read 6, iclass 11, count 0 2006.253.08:03:52.31#ibcon#read 6, iclass 11, count 0 2006.253.08:03:52.31#ibcon#end of sib2, iclass 11, count 0 2006.253.08:03:52.31#ibcon#*after write, iclass 11, count 0 2006.253.08:03:52.31#ibcon#*before return 0, iclass 11, count 0 2006.253.08:03:52.31#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.253.08:03:52.31#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.253.08:03:52.31#ibcon#about to clear, iclass 11 cls_cnt 0 2006.253.08:03:52.31#ibcon#cleared, iclass 11 cls_cnt 0 2006.253.08:03:52.31$vc4f8/vb=6,4 2006.253.08:03:52.31#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.253.08:03:52.31#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.253.08:03:52.31#ibcon#ireg 11 cls_cnt 2 2006.253.08:03:52.31#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.253.08:03:52.37#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.253.08:03:52.37#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.253.08:03:52.37#ibcon#enter wrdev, iclass 13, count 2 2006.253.08:03:52.37#ibcon#first serial, iclass 13, count 2 2006.253.08:03:52.37#ibcon#enter sib2, iclass 13, count 2 2006.253.08:03:52.37#ibcon#flushed, iclass 13, count 2 2006.253.08:03:52.37#ibcon#about to write, iclass 13, count 2 2006.253.08:03:52.37#ibcon#wrote, iclass 13, count 2 2006.253.08:03:52.37#ibcon#about to read 3, iclass 13, count 2 2006.253.08:03:52.39#ibcon#read 3, iclass 13, count 2 2006.253.08:03:52.39#ibcon#about to read 4, iclass 13, count 2 2006.253.08:03:52.39#ibcon#read 4, iclass 13, count 2 2006.253.08:03:52.39#ibcon#about to read 5, iclass 13, count 2 2006.253.08:03:52.39#ibcon#read 5, iclass 13, count 2 2006.253.08:03:52.39#ibcon#about to read 6, iclass 13, count 2 2006.253.08:03:52.39#ibcon#read 6, iclass 13, count 2 2006.253.08:03:52.39#ibcon#end of sib2, iclass 13, count 2 2006.253.08:03:52.39#ibcon#*mode == 0, iclass 13, count 2 2006.253.08:03:52.39#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.253.08:03:52.39#ibcon#[27=AT06-04\r\n] 2006.253.08:03:52.39#ibcon#*before write, iclass 13, count 2 2006.253.08:03:52.39#ibcon#enter sib2, iclass 13, count 2 2006.253.08:03:52.39#ibcon#flushed, iclass 13, count 2 2006.253.08:03:52.39#ibcon#about to write, iclass 13, count 2 2006.253.08:03:52.39#ibcon#wrote, iclass 13, count 2 2006.253.08:03:52.39#ibcon#about to read 3, iclass 13, count 2 2006.253.08:03:52.42#ibcon#read 3, iclass 13, count 2 2006.253.08:03:52.42#ibcon#about to read 4, iclass 13, count 2 2006.253.08:03:52.42#ibcon#read 4, iclass 13, count 2 2006.253.08:03:52.42#ibcon#about to read 5, iclass 13, count 2 2006.253.08:03:52.42#ibcon#read 5, iclass 13, count 2 2006.253.08:03:52.42#ibcon#about to read 6, iclass 13, count 2 2006.253.08:03:52.42#ibcon#read 6, iclass 13, count 2 2006.253.08:03:52.42#ibcon#end of sib2, iclass 13, count 2 2006.253.08:03:52.42#ibcon#*after write, iclass 13, count 2 2006.253.08:03:52.42#ibcon#*before return 0, iclass 13, count 2 2006.253.08:03:52.42#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.253.08:03:52.42#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.253.08:03:52.42#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.253.08:03:52.42#ibcon#ireg 7 cls_cnt 0 2006.253.08:03:52.42#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.253.08:03:52.49#abcon#{5=INTERFACE CLEAR} 2006.253.08:03:52.54#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.253.08:03:52.54#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.253.08:03:52.54#ibcon#enter wrdev, iclass 13, count 0 2006.253.08:03:52.54#ibcon#first serial, iclass 13, count 0 2006.253.08:03:52.54#ibcon#enter sib2, iclass 13, count 0 2006.253.08:03:52.54#ibcon#flushed, iclass 13, count 0 2006.253.08:03:52.54#ibcon#about to write, iclass 13, count 0 2006.253.08:03:52.54#ibcon#wrote, iclass 13, count 0 2006.253.08:03:52.54#ibcon#about to read 3, iclass 13, count 0 2006.253.08:03:52.55#abcon#[5=S1D000X0/0*\r\n] 2006.253.08:03:52.56#ibcon#read 3, iclass 13, count 0 2006.253.08:03:52.56#ibcon#about to read 4, iclass 13, count 0 2006.253.08:03:52.56#ibcon#read 4, iclass 13, count 0 2006.253.08:03:52.56#ibcon#about to read 5, iclass 13, count 0 2006.253.08:03:52.56#ibcon#read 5, iclass 13, count 0 2006.253.08:03:52.56#ibcon#about to read 6, iclass 13, count 0 2006.253.08:03:52.56#ibcon#read 6, iclass 13, count 0 2006.253.08:03:52.56#ibcon#end of sib2, iclass 13, count 0 2006.253.08:03:52.56#ibcon#*mode == 0, iclass 13, count 0 2006.253.08:03:52.56#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.253.08:03:52.56#ibcon#[27=USB\r\n] 2006.253.08:03:52.56#ibcon#*before write, iclass 13, count 0 2006.253.08:03:52.56#ibcon#enter sib2, iclass 13, count 0 2006.253.08:03:52.56#ibcon#flushed, iclass 13, count 0 2006.253.08:03:52.56#ibcon#about to write, iclass 13, count 0 2006.253.08:03:52.56#ibcon#wrote, iclass 13, count 0 2006.253.08:03:52.56#ibcon#about to read 3, iclass 13, count 0 2006.253.08:03:52.59#ibcon#read 3, iclass 13, count 0 2006.253.08:03:52.59#ibcon#about to read 4, iclass 13, count 0 2006.253.08:03:52.59#ibcon#read 4, iclass 13, count 0 2006.253.08:03:52.59#ibcon#about to read 5, iclass 13, count 0 2006.253.08:03:52.59#ibcon#read 5, iclass 13, count 0 2006.253.08:03:52.59#ibcon#about to read 6, iclass 13, count 0 2006.253.08:03:52.59#ibcon#read 6, iclass 13, count 0 2006.253.08:03:52.59#ibcon#end of sib2, iclass 13, count 0 2006.253.08:03:52.59#ibcon#*after write, iclass 13, count 0 2006.253.08:03:52.59#ibcon#*before return 0, iclass 13, count 0 2006.253.08:03:52.59#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.253.08:03:52.59#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.253.08:03:52.59#ibcon#about to clear, iclass 13 cls_cnt 0 2006.253.08:03:52.59#ibcon#cleared, iclass 13 cls_cnt 0 2006.253.08:03:52.59$vc4f8/vabw=wide 2006.253.08:03:52.59#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.253.08:03:52.59#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.253.08:03:52.59#ibcon#ireg 8 cls_cnt 0 2006.253.08:03:52.59#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.253.08:03:52.59#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.253.08:03:52.59#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.253.08:03:52.59#ibcon#enter wrdev, iclass 17, count 0 2006.253.08:03:52.59#ibcon#first serial, iclass 17, count 0 2006.253.08:03:52.59#ibcon#enter sib2, iclass 17, count 0 2006.253.08:03:52.59#ibcon#flushed, iclass 17, count 0 2006.253.08:03:52.59#ibcon#about to write, iclass 17, count 0 2006.253.08:03:52.59#ibcon#wrote, iclass 17, count 0 2006.253.08:03:52.59#ibcon#about to read 3, iclass 17, count 0 2006.253.08:03:52.61#ibcon#read 3, iclass 17, count 0 2006.253.08:03:52.61#ibcon#about to read 4, iclass 17, count 0 2006.253.08:03:52.61#ibcon#read 4, iclass 17, count 0 2006.253.08:03:52.61#ibcon#about to read 5, iclass 17, count 0 2006.253.08:03:52.61#ibcon#read 5, iclass 17, count 0 2006.253.08:03:52.61#ibcon#about to read 6, iclass 17, count 0 2006.253.08:03:52.61#ibcon#read 6, iclass 17, count 0 2006.253.08:03:52.61#ibcon#end of sib2, iclass 17, count 0 2006.253.08:03:52.61#ibcon#*mode == 0, iclass 17, count 0 2006.253.08:03:52.61#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.253.08:03:52.61#ibcon#[25=BW32\r\n] 2006.253.08:03:52.61#ibcon#*before write, iclass 17, count 0 2006.253.08:03:52.61#ibcon#enter sib2, iclass 17, count 0 2006.253.08:03:52.61#ibcon#flushed, iclass 17, count 0 2006.253.08:03:52.61#ibcon#about to write, iclass 17, count 0 2006.253.08:03:52.61#ibcon#wrote, iclass 17, count 0 2006.253.08:03:52.61#ibcon#about to read 3, iclass 17, count 0 2006.253.08:03:52.64#ibcon#read 3, iclass 17, count 0 2006.253.08:03:52.64#ibcon#about to read 4, iclass 17, count 0 2006.253.08:03:52.64#ibcon#read 4, iclass 17, count 0 2006.253.08:03:52.64#ibcon#about to read 5, iclass 17, count 0 2006.253.08:03:52.64#ibcon#read 5, iclass 17, count 0 2006.253.08:03:52.64#ibcon#about to read 6, iclass 17, count 0 2006.253.08:03:52.64#ibcon#read 6, iclass 17, count 0 2006.253.08:03:52.64#ibcon#end of sib2, iclass 17, count 0 2006.253.08:03:52.64#ibcon#*after write, iclass 17, count 0 2006.253.08:03:52.64#ibcon#*before return 0, iclass 17, count 0 2006.253.08:03:52.64#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.253.08:03:52.64#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.253.08:03:52.64#ibcon#about to clear, iclass 17 cls_cnt 0 2006.253.08:03:52.64#ibcon#cleared, iclass 17 cls_cnt 0 2006.253.08:03:52.64$vc4f8/vbbw=wide 2006.253.08:03:52.64#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.253.08:03:52.64#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.253.08:03:52.64#ibcon#ireg 8 cls_cnt 0 2006.253.08:03:52.64#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.253.08:03:52.71#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.253.08:03:52.71#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.253.08:03:52.71#ibcon#enter wrdev, iclass 19, count 0 2006.253.08:03:52.71#ibcon#first serial, iclass 19, count 0 2006.253.08:03:52.71#ibcon#enter sib2, iclass 19, count 0 2006.253.08:03:52.71#ibcon#flushed, iclass 19, count 0 2006.253.08:03:52.71#ibcon#about to write, iclass 19, count 0 2006.253.08:03:52.71#ibcon#wrote, iclass 19, count 0 2006.253.08:03:52.71#ibcon#about to read 3, iclass 19, count 0 2006.253.08:03:52.73#ibcon#read 3, iclass 19, count 0 2006.253.08:03:52.73#ibcon#about to read 4, iclass 19, count 0 2006.253.08:03:52.73#ibcon#read 4, iclass 19, count 0 2006.253.08:03:52.73#ibcon#about to read 5, iclass 19, count 0 2006.253.08:03:52.73#ibcon#read 5, iclass 19, count 0 2006.253.08:03:52.73#ibcon#about to read 6, iclass 19, count 0 2006.253.08:03:52.73#ibcon#read 6, iclass 19, count 0 2006.253.08:03:52.73#ibcon#end of sib2, iclass 19, count 0 2006.253.08:03:52.73#ibcon#*mode == 0, iclass 19, count 0 2006.253.08:03:52.73#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.253.08:03:52.73#ibcon#[27=BW32\r\n] 2006.253.08:03:52.73#ibcon#*before write, iclass 19, count 0 2006.253.08:03:52.73#ibcon#enter sib2, iclass 19, count 0 2006.253.08:03:52.73#ibcon#flushed, iclass 19, count 0 2006.253.08:03:52.73#ibcon#about to write, iclass 19, count 0 2006.253.08:03:52.73#ibcon#wrote, iclass 19, count 0 2006.253.08:03:52.73#ibcon#about to read 3, iclass 19, count 0 2006.253.08:03:52.76#ibcon#read 3, iclass 19, count 0 2006.253.08:03:52.76#ibcon#about to read 4, iclass 19, count 0 2006.253.08:03:52.76#ibcon#read 4, iclass 19, count 0 2006.253.08:03:52.76#ibcon#about to read 5, iclass 19, count 0 2006.253.08:03:52.76#ibcon#read 5, iclass 19, count 0 2006.253.08:03:52.76#ibcon#about to read 6, iclass 19, count 0 2006.253.08:03:52.76#ibcon#read 6, iclass 19, count 0 2006.253.08:03:52.76#ibcon#end of sib2, iclass 19, count 0 2006.253.08:03:52.76#ibcon#*after write, iclass 19, count 0 2006.253.08:03:52.76#ibcon#*before return 0, iclass 19, count 0 2006.253.08:03:52.76#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.253.08:03:52.76#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.253.08:03:52.76#ibcon#about to clear, iclass 19 cls_cnt 0 2006.253.08:03:52.76#ibcon#cleared, iclass 19 cls_cnt 0 2006.253.08:03:52.76$4f8m12a/ifd4f 2006.253.08:03:52.76$ifd4f/lo= 2006.253.08:03:52.76$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.253.08:03:52.76$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.253.08:03:52.76$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.253.08:03:52.76$ifd4f/patch= 2006.253.08:03:52.76$ifd4f/patch=lo1,a1,a2,a3,a4 2006.253.08:03:52.76$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.253.08:03:52.76$ifd4f/patch=lo3,a5,a6,a7,a8 2006.253.08:03:52.76$4f8m12a/"form=m,16.000,1:2 2006.253.08:03:52.76$4f8m12a/"tpicd 2006.253.08:03:52.76$4f8m12a/echo=off 2006.253.08:03:52.76$4f8m12a/xlog=off 2006.253.08:03:52.76:!2006.253.08:04:20 2006.253.08:04:04.13#trakl#Source acquired 2006.253.08:04:05.13#flagr#flagr/antenna,acquired 2006.253.08:04:20.00:preob 2006.253.08:04:21.13/onsource/TRACKING 2006.253.08:04:21.13:!2006.253.08:04:30 2006.253.08:04:30.00:data_valid=on 2006.253.08:04:30.00:midob 2006.253.08:04:30.13/onsource/TRACKING 2006.253.08:04:30.13/wx/31.06,1006.4,73 2006.253.08:04:30.28/cable/+6.3690E-03 2006.253.08:04:31.37/va/01,08,usb,yes,32,33 2006.253.08:04:31.37/va/02,07,usb,yes,31,33 2006.253.08:04:31.37/va/03,06,usb,yes,34,34 2006.253.08:04:31.37/va/04,07,usb,yes,33,35 2006.253.08:04:31.37/va/05,07,usb,yes,34,36 2006.253.08:04:31.37/va/06,07,usb,yes,30,30 2006.253.08:04:31.37/va/07,07,usb,yes,30,30 2006.253.08:04:31.37/va/08,07,usb,yes,32,32 2006.253.08:04:31.60/valo/01,532.99,yes,locked 2006.253.08:04:31.60/valo/02,572.99,yes,locked 2006.253.08:04:31.60/valo/03,672.99,yes,locked 2006.253.08:04:31.60/valo/04,832.99,yes,locked 2006.253.08:04:31.60/valo/05,652.99,yes,locked 2006.253.08:04:31.60/valo/06,772.99,yes,locked 2006.253.08:04:31.60/valo/07,832.99,yes,locked 2006.253.08:04:31.60/valo/08,852.99,yes,locked 2006.253.08:04:32.69/vb/01,04,usb,yes,31,29 2006.253.08:04:32.69/vb/02,05,usb,yes,29,30 2006.253.08:04:32.69/vb/03,04,usb,yes,29,33 2006.253.08:04:32.69/vb/04,04,usb,yes,30,30 2006.253.08:04:32.69/vb/05,04,usb,yes,28,32 2006.253.08:04:32.69/vb/06,04,usb,yes,29,32 2006.253.08:04:32.69/vb/07,04,usb,yes,31,31 2006.253.08:04:32.69/vb/08,04,usb,yes,29,32 2006.253.08:04:32.93/vblo/01,632.99,yes,locked 2006.253.08:04:32.93/vblo/02,640.99,yes,locked 2006.253.08:04:32.93/vblo/03,656.99,yes,locked 2006.253.08:04:32.93/vblo/04,712.99,yes,locked 2006.253.08:04:32.93/vblo/05,744.99,yes,locked 2006.253.08:04:32.93/vblo/06,752.99,yes,locked 2006.253.08:04:32.93/vblo/07,734.99,yes,locked 2006.253.08:04:32.93/vblo/08,744.99,yes,locked 2006.253.08:04:33.08/vabw/8 2006.253.08:04:33.23/vbbw/8 2006.253.08:04:33.34/xfe/off,on,14.2 2006.253.08:04:33.72/ifatt/23,28,28,28 2006.253.08:04:34.08/fmout-gps/S +4.75E-07 2006.253.08:04:34.12:!2006.253.08:05:30 2006.253.08:05:30.01:data_valid=off 2006.253.08:05:30.01:postob 2006.253.08:05:30.19/cable/+6.3693E-03 2006.253.08:05:30.19/wx/31.04,1006.4,73 2006.253.08:05:31.08/fmout-gps/S +4.77E-07 2006.253.08:05:31.08:scan_name=253-0806,k06253,60 2006.253.08:05:31.09:source=1803+784,180045.68,782804.0,2000.0,neutral 2006.253.08:05:31.14#flagr#flagr/antenna,new-source 2006.253.08:05:32.14:checkk5 2006.253.08:05:32.53/chk_autoobs//k5ts1/ autoobs is running! 2006.253.08:05:32.91/chk_autoobs//k5ts2/ autoobs is running! 2006.253.08:05:33.29/chk_autoobs//k5ts3/ autoobs is running! 2006.253.08:05:33.65/chk_autoobs//k5ts4/ autoobs is running! 2006.253.08:05:34.02/chk_obsdata//k5ts1/T2530804??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.08:05:34.39/chk_obsdata//k5ts2/T2530804??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.08:05:34.76/chk_obsdata//k5ts3/T2530804??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.08:05:35.13/chk_obsdata//k5ts4/T2530804??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.08:05:35.83/k5log//k5ts1_log_newline 2006.253.08:05:36.53/k5log//k5ts2_log_newline 2006.253.08:05:37.23/k5log//k5ts3_log_newline 2006.253.08:05:37.92/k5log//k5ts4_log_newline 2006.253.08:05:37.94/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.253.08:05:37.94:4f8m12a=2 2006.253.08:05:37.94$4f8m12a/echo=on 2006.253.08:05:37.94$4f8m12a/pcalon 2006.253.08:05:37.94$pcalon/"no phase cal control is implemented here 2006.253.08:05:37.94$4f8m12a/"tpicd=stop 2006.253.08:05:37.94$4f8m12a/vc4f8 2006.253.08:05:37.94$vc4f8/valo=1,532.99 2006.253.08:05:37.94#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.253.08:05:37.94#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.253.08:05:37.94#ibcon#ireg 17 cls_cnt 0 2006.253.08:05:37.94#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.253.08:05:37.94#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.253.08:05:37.94#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.253.08:05:37.94#ibcon#enter wrdev, iclass 26, count 0 2006.253.08:05:37.94#ibcon#first serial, iclass 26, count 0 2006.253.08:05:37.94#ibcon#enter sib2, iclass 26, count 0 2006.253.08:05:37.94#ibcon#flushed, iclass 26, count 0 2006.253.08:05:37.94#ibcon#about to write, iclass 26, count 0 2006.253.08:05:37.94#ibcon#wrote, iclass 26, count 0 2006.253.08:05:37.94#ibcon#about to read 3, iclass 26, count 0 2006.253.08:05:37.96#ibcon#read 3, iclass 26, count 0 2006.253.08:05:37.96#ibcon#about to read 4, iclass 26, count 0 2006.253.08:05:37.96#ibcon#read 4, iclass 26, count 0 2006.253.08:05:37.96#ibcon#about to read 5, iclass 26, count 0 2006.253.08:05:37.96#ibcon#read 5, iclass 26, count 0 2006.253.08:05:37.96#ibcon#about to read 6, iclass 26, count 0 2006.253.08:05:37.96#ibcon#read 6, iclass 26, count 0 2006.253.08:05:37.96#ibcon#end of sib2, iclass 26, count 0 2006.253.08:05:37.96#ibcon#*mode == 0, iclass 26, count 0 2006.253.08:05:37.96#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.253.08:05:37.96#ibcon#[26=FRQ=01,532.99\r\n] 2006.253.08:05:37.96#ibcon#*before write, iclass 26, count 0 2006.253.08:05:37.96#ibcon#enter sib2, iclass 26, count 0 2006.253.08:05:37.96#ibcon#flushed, iclass 26, count 0 2006.253.08:05:37.96#ibcon#about to write, iclass 26, count 0 2006.253.08:05:37.96#ibcon#wrote, iclass 26, count 0 2006.253.08:05:37.96#ibcon#about to read 3, iclass 26, count 0 2006.253.08:05:38.01#ibcon#read 3, iclass 26, count 0 2006.253.08:05:38.01#ibcon#about to read 4, iclass 26, count 0 2006.253.08:05:38.01#ibcon#read 4, iclass 26, count 0 2006.253.08:05:38.01#ibcon#about to read 5, iclass 26, count 0 2006.253.08:05:38.01#ibcon#read 5, iclass 26, count 0 2006.253.08:05:38.01#ibcon#about to read 6, iclass 26, count 0 2006.253.08:05:38.01#ibcon#read 6, iclass 26, count 0 2006.253.08:05:38.01#ibcon#end of sib2, iclass 26, count 0 2006.253.08:05:38.01#ibcon#*after write, iclass 26, count 0 2006.253.08:05:38.01#ibcon#*before return 0, iclass 26, count 0 2006.253.08:05:38.01#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.253.08:05:38.01#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.253.08:05:38.01#ibcon#about to clear, iclass 26 cls_cnt 0 2006.253.08:05:38.01#ibcon#cleared, iclass 26 cls_cnt 0 2006.253.08:05:38.01$vc4f8/va=1,8 2006.253.08:05:38.01#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.253.08:05:38.01#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.253.08:05:38.01#ibcon#ireg 11 cls_cnt 2 2006.253.08:05:38.01#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.253.08:05:38.01#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.253.08:05:38.01#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.253.08:05:38.01#ibcon#enter wrdev, iclass 28, count 2 2006.253.08:05:38.01#ibcon#first serial, iclass 28, count 2 2006.253.08:05:38.01#ibcon#enter sib2, iclass 28, count 2 2006.253.08:05:38.01#ibcon#flushed, iclass 28, count 2 2006.253.08:05:38.01#ibcon#about to write, iclass 28, count 2 2006.253.08:05:38.01#ibcon#wrote, iclass 28, count 2 2006.253.08:05:38.01#ibcon#about to read 3, iclass 28, count 2 2006.253.08:05:38.03#ibcon#read 3, iclass 28, count 2 2006.253.08:05:38.03#ibcon#about to read 4, iclass 28, count 2 2006.253.08:05:38.03#ibcon#read 4, iclass 28, count 2 2006.253.08:05:38.03#ibcon#about to read 5, iclass 28, count 2 2006.253.08:05:38.03#ibcon#read 5, iclass 28, count 2 2006.253.08:05:38.03#ibcon#about to read 6, iclass 28, count 2 2006.253.08:05:38.03#ibcon#read 6, iclass 28, count 2 2006.253.08:05:38.03#ibcon#end of sib2, iclass 28, count 2 2006.253.08:05:38.03#ibcon#*mode == 0, iclass 28, count 2 2006.253.08:05:38.03#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.253.08:05:38.03#ibcon#[25=AT01-08\r\n] 2006.253.08:05:38.03#ibcon#*before write, iclass 28, count 2 2006.253.08:05:38.03#ibcon#enter sib2, iclass 28, count 2 2006.253.08:05:38.03#ibcon#flushed, iclass 28, count 2 2006.253.08:05:38.03#ibcon#about to write, iclass 28, count 2 2006.253.08:05:38.03#ibcon#wrote, iclass 28, count 2 2006.253.08:05:38.03#ibcon#about to read 3, iclass 28, count 2 2006.253.08:05:38.06#ibcon#read 3, iclass 28, count 2 2006.253.08:05:38.06#ibcon#about to read 4, iclass 28, count 2 2006.253.08:05:38.06#ibcon#read 4, iclass 28, count 2 2006.253.08:05:38.06#ibcon#about to read 5, iclass 28, count 2 2006.253.08:05:38.06#ibcon#read 5, iclass 28, count 2 2006.253.08:05:38.06#ibcon#about to read 6, iclass 28, count 2 2006.253.08:05:38.06#ibcon#read 6, iclass 28, count 2 2006.253.08:05:38.06#ibcon#end of sib2, iclass 28, count 2 2006.253.08:05:38.06#ibcon#*after write, iclass 28, count 2 2006.253.08:05:38.06#ibcon#*before return 0, iclass 28, count 2 2006.253.08:05:38.06#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.253.08:05:38.06#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.253.08:05:38.06#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.253.08:05:38.06#ibcon#ireg 7 cls_cnt 0 2006.253.08:05:38.06#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.253.08:05:38.18#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.253.08:05:38.18#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.253.08:05:38.18#ibcon#enter wrdev, iclass 28, count 0 2006.253.08:05:38.18#ibcon#first serial, iclass 28, count 0 2006.253.08:05:38.18#ibcon#enter sib2, iclass 28, count 0 2006.253.08:05:38.18#ibcon#flushed, iclass 28, count 0 2006.253.08:05:38.18#ibcon#about to write, iclass 28, count 0 2006.253.08:05:38.18#ibcon#wrote, iclass 28, count 0 2006.253.08:05:38.18#ibcon#about to read 3, iclass 28, count 0 2006.253.08:05:38.20#ibcon#read 3, iclass 28, count 0 2006.253.08:05:38.20#ibcon#about to read 4, iclass 28, count 0 2006.253.08:05:38.20#ibcon#read 4, iclass 28, count 0 2006.253.08:05:38.20#ibcon#about to read 5, iclass 28, count 0 2006.253.08:05:38.20#ibcon#read 5, iclass 28, count 0 2006.253.08:05:38.20#ibcon#about to read 6, iclass 28, count 0 2006.253.08:05:38.20#ibcon#read 6, iclass 28, count 0 2006.253.08:05:38.20#ibcon#end of sib2, iclass 28, count 0 2006.253.08:05:38.20#ibcon#*mode == 0, iclass 28, count 0 2006.253.08:05:38.20#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.253.08:05:38.20#ibcon#[25=USB\r\n] 2006.253.08:05:38.20#ibcon#*before write, iclass 28, count 0 2006.253.08:05:38.20#ibcon#enter sib2, iclass 28, count 0 2006.253.08:05:38.20#ibcon#flushed, iclass 28, count 0 2006.253.08:05:38.20#ibcon#about to write, iclass 28, count 0 2006.253.08:05:38.20#ibcon#wrote, iclass 28, count 0 2006.253.08:05:38.20#ibcon#about to read 3, iclass 28, count 0 2006.253.08:05:38.23#ibcon#read 3, iclass 28, count 0 2006.253.08:05:38.23#ibcon#about to read 4, iclass 28, count 0 2006.253.08:05:38.23#ibcon#read 4, iclass 28, count 0 2006.253.08:05:38.23#ibcon#about to read 5, iclass 28, count 0 2006.253.08:05:38.23#ibcon#read 5, iclass 28, count 0 2006.253.08:05:38.23#ibcon#about to read 6, iclass 28, count 0 2006.253.08:05:38.23#ibcon#read 6, iclass 28, count 0 2006.253.08:05:38.23#ibcon#end of sib2, iclass 28, count 0 2006.253.08:05:38.23#ibcon#*after write, iclass 28, count 0 2006.253.08:05:38.23#ibcon#*before return 0, iclass 28, count 0 2006.253.08:05:38.23#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.253.08:05:38.23#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.253.08:05:38.23#ibcon#about to clear, iclass 28 cls_cnt 0 2006.253.08:05:38.23#ibcon#cleared, iclass 28 cls_cnt 0 2006.253.08:05:38.23$vc4f8/valo=2,572.99 2006.253.08:05:38.23#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.253.08:05:38.23#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.253.08:05:38.23#ibcon#ireg 17 cls_cnt 0 2006.253.08:05:38.23#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.253.08:05:38.23#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.253.08:05:38.23#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.253.08:05:38.23#ibcon#enter wrdev, iclass 30, count 0 2006.253.08:05:38.23#ibcon#first serial, iclass 30, count 0 2006.253.08:05:38.23#ibcon#enter sib2, iclass 30, count 0 2006.253.08:05:38.23#ibcon#flushed, iclass 30, count 0 2006.253.08:05:38.23#ibcon#about to write, iclass 30, count 0 2006.253.08:05:38.23#ibcon#wrote, iclass 30, count 0 2006.253.08:05:38.23#ibcon#about to read 3, iclass 30, count 0 2006.253.08:05:38.25#ibcon#read 3, iclass 30, count 0 2006.253.08:05:38.25#ibcon#about to read 4, iclass 30, count 0 2006.253.08:05:38.25#ibcon#read 4, iclass 30, count 0 2006.253.08:05:38.25#ibcon#about to read 5, iclass 30, count 0 2006.253.08:05:38.25#ibcon#read 5, iclass 30, count 0 2006.253.08:05:38.25#ibcon#about to read 6, iclass 30, count 0 2006.253.08:05:38.25#ibcon#read 6, iclass 30, count 0 2006.253.08:05:38.25#ibcon#end of sib2, iclass 30, count 0 2006.253.08:05:38.25#ibcon#*mode == 0, iclass 30, count 0 2006.253.08:05:38.25#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.253.08:05:38.25#ibcon#[26=FRQ=02,572.99\r\n] 2006.253.08:05:38.25#ibcon#*before write, iclass 30, count 0 2006.253.08:05:38.25#ibcon#enter sib2, iclass 30, count 0 2006.253.08:05:38.25#ibcon#flushed, iclass 30, count 0 2006.253.08:05:38.25#ibcon#about to write, iclass 30, count 0 2006.253.08:05:38.25#ibcon#wrote, iclass 30, count 0 2006.253.08:05:38.25#ibcon#about to read 3, iclass 30, count 0 2006.253.08:05:38.29#ibcon#read 3, iclass 30, count 0 2006.253.08:05:38.29#ibcon#about to read 4, iclass 30, count 0 2006.253.08:05:38.29#ibcon#read 4, iclass 30, count 0 2006.253.08:05:38.29#ibcon#about to read 5, iclass 30, count 0 2006.253.08:05:38.29#ibcon#read 5, iclass 30, count 0 2006.253.08:05:38.29#ibcon#about to read 6, iclass 30, count 0 2006.253.08:05:38.29#ibcon#read 6, iclass 30, count 0 2006.253.08:05:38.29#ibcon#end of sib2, iclass 30, count 0 2006.253.08:05:38.29#ibcon#*after write, iclass 30, count 0 2006.253.08:05:38.29#ibcon#*before return 0, iclass 30, count 0 2006.253.08:05:38.29#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.253.08:05:38.29#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.253.08:05:38.29#ibcon#about to clear, iclass 30 cls_cnt 0 2006.253.08:05:38.29#ibcon#cleared, iclass 30 cls_cnt 0 2006.253.08:05:38.29$vc4f8/va=2,7 2006.253.08:05:38.29#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.253.08:05:38.29#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.253.08:05:38.29#ibcon#ireg 11 cls_cnt 2 2006.253.08:05:38.29#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.253.08:05:38.35#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.253.08:05:38.35#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.253.08:05:38.35#ibcon#enter wrdev, iclass 32, count 2 2006.253.08:05:38.35#ibcon#first serial, iclass 32, count 2 2006.253.08:05:38.35#ibcon#enter sib2, iclass 32, count 2 2006.253.08:05:38.35#ibcon#flushed, iclass 32, count 2 2006.253.08:05:38.35#ibcon#about to write, iclass 32, count 2 2006.253.08:05:38.35#ibcon#wrote, iclass 32, count 2 2006.253.08:05:38.35#ibcon#about to read 3, iclass 32, count 2 2006.253.08:05:38.37#ibcon#read 3, iclass 32, count 2 2006.253.08:05:38.37#ibcon#about to read 4, iclass 32, count 2 2006.253.08:05:38.37#ibcon#read 4, iclass 32, count 2 2006.253.08:05:38.37#ibcon#about to read 5, iclass 32, count 2 2006.253.08:05:38.37#ibcon#read 5, iclass 32, count 2 2006.253.08:05:38.37#ibcon#about to read 6, iclass 32, count 2 2006.253.08:05:38.37#ibcon#read 6, iclass 32, count 2 2006.253.08:05:38.37#ibcon#end of sib2, iclass 32, count 2 2006.253.08:05:38.37#ibcon#*mode == 0, iclass 32, count 2 2006.253.08:05:38.37#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.253.08:05:38.37#ibcon#[25=AT02-07\r\n] 2006.253.08:05:38.37#ibcon#*before write, iclass 32, count 2 2006.253.08:05:38.37#ibcon#enter sib2, iclass 32, count 2 2006.253.08:05:38.37#ibcon#flushed, iclass 32, count 2 2006.253.08:05:38.37#ibcon#about to write, iclass 32, count 2 2006.253.08:05:38.37#ibcon#wrote, iclass 32, count 2 2006.253.08:05:38.37#ibcon#about to read 3, iclass 32, count 2 2006.253.08:05:38.40#ibcon#read 3, iclass 32, count 2 2006.253.08:05:38.40#ibcon#about to read 4, iclass 32, count 2 2006.253.08:05:38.40#ibcon#read 4, iclass 32, count 2 2006.253.08:05:38.40#ibcon#about to read 5, iclass 32, count 2 2006.253.08:05:38.40#ibcon#read 5, iclass 32, count 2 2006.253.08:05:38.40#ibcon#about to read 6, iclass 32, count 2 2006.253.08:05:38.40#ibcon#read 6, iclass 32, count 2 2006.253.08:05:38.40#ibcon#end of sib2, iclass 32, count 2 2006.253.08:05:38.40#ibcon#*after write, iclass 32, count 2 2006.253.08:05:38.40#ibcon#*before return 0, iclass 32, count 2 2006.253.08:05:38.40#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.253.08:05:38.40#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.253.08:05:38.40#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.253.08:05:38.40#ibcon#ireg 7 cls_cnt 0 2006.253.08:05:38.40#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.253.08:05:38.52#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.253.08:05:38.52#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.253.08:05:38.52#ibcon#enter wrdev, iclass 32, count 0 2006.253.08:05:38.52#ibcon#first serial, iclass 32, count 0 2006.253.08:05:38.52#ibcon#enter sib2, iclass 32, count 0 2006.253.08:05:38.52#ibcon#flushed, iclass 32, count 0 2006.253.08:05:38.52#ibcon#about to write, iclass 32, count 0 2006.253.08:05:38.52#ibcon#wrote, iclass 32, count 0 2006.253.08:05:38.52#ibcon#about to read 3, iclass 32, count 0 2006.253.08:05:38.54#ibcon#read 3, iclass 32, count 0 2006.253.08:05:38.54#ibcon#about to read 4, iclass 32, count 0 2006.253.08:05:38.54#ibcon#read 4, iclass 32, count 0 2006.253.08:05:38.54#ibcon#about to read 5, iclass 32, count 0 2006.253.08:05:38.54#ibcon#read 5, iclass 32, count 0 2006.253.08:05:38.54#ibcon#about to read 6, iclass 32, count 0 2006.253.08:05:38.54#ibcon#read 6, iclass 32, count 0 2006.253.08:05:38.54#ibcon#end of sib2, iclass 32, count 0 2006.253.08:05:38.54#ibcon#*mode == 0, iclass 32, count 0 2006.253.08:05:38.54#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.253.08:05:38.54#ibcon#[25=USB\r\n] 2006.253.08:05:38.54#ibcon#*before write, iclass 32, count 0 2006.253.08:05:38.54#ibcon#enter sib2, iclass 32, count 0 2006.253.08:05:38.54#ibcon#flushed, iclass 32, count 0 2006.253.08:05:38.54#ibcon#about to write, iclass 32, count 0 2006.253.08:05:38.54#ibcon#wrote, iclass 32, count 0 2006.253.08:05:38.54#ibcon#about to read 3, iclass 32, count 0 2006.253.08:05:38.57#ibcon#read 3, iclass 32, count 0 2006.253.08:05:38.57#ibcon#about to read 4, iclass 32, count 0 2006.253.08:05:38.57#ibcon#read 4, iclass 32, count 0 2006.253.08:05:38.57#ibcon#about to read 5, iclass 32, count 0 2006.253.08:05:38.57#ibcon#read 5, iclass 32, count 0 2006.253.08:05:38.57#ibcon#about to read 6, iclass 32, count 0 2006.253.08:05:38.57#ibcon#read 6, iclass 32, count 0 2006.253.08:05:38.57#ibcon#end of sib2, iclass 32, count 0 2006.253.08:05:38.57#ibcon#*after write, iclass 32, count 0 2006.253.08:05:38.57#ibcon#*before return 0, iclass 32, count 0 2006.253.08:05:38.57#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.253.08:05:38.57#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.253.08:05:38.57#ibcon#about to clear, iclass 32 cls_cnt 0 2006.253.08:05:38.57#ibcon#cleared, iclass 32 cls_cnt 0 2006.253.08:05:38.57$vc4f8/valo=3,672.99 2006.253.08:05:38.57#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.253.08:05:38.57#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.253.08:05:38.57#ibcon#ireg 17 cls_cnt 0 2006.253.08:05:38.57#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.253.08:05:38.57#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.253.08:05:38.57#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.253.08:05:38.57#ibcon#enter wrdev, iclass 34, count 0 2006.253.08:05:38.57#ibcon#first serial, iclass 34, count 0 2006.253.08:05:38.57#ibcon#enter sib2, iclass 34, count 0 2006.253.08:05:38.57#ibcon#flushed, iclass 34, count 0 2006.253.08:05:38.57#ibcon#about to write, iclass 34, count 0 2006.253.08:05:38.57#ibcon#wrote, iclass 34, count 0 2006.253.08:05:38.57#ibcon#about to read 3, iclass 34, count 0 2006.253.08:05:38.59#ibcon#read 3, iclass 34, count 0 2006.253.08:05:38.59#ibcon#about to read 4, iclass 34, count 0 2006.253.08:05:38.59#ibcon#read 4, iclass 34, count 0 2006.253.08:05:38.59#ibcon#about to read 5, iclass 34, count 0 2006.253.08:05:38.59#ibcon#read 5, iclass 34, count 0 2006.253.08:05:38.59#ibcon#about to read 6, iclass 34, count 0 2006.253.08:05:38.59#ibcon#read 6, iclass 34, count 0 2006.253.08:05:38.59#ibcon#end of sib2, iclass 34, count 0 2006.253.08:05:38.59#ibcon#*mode == 0, iclass 34, count 0 2006.253.08:05:38.59#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.253.08:05:38.59#ibcon#[26=FRQ=03,672.99\r\n] 2006.253.08:05:38.59#ibcon#*before write, iclass 34, count 0 2006.253.08:05:38.59#ibcon#enter sib2, iclass 34, count 0 2006.253.08:05:38.59#ibcon#flushed, iclass 34, count 0 2006.253.08:05:38.59#ibcon#about to write, iclass 34, count 0 2006.253.08:05:38.59#ibcon#wrote, iclass 34, count 0 2006.253.08:05:38.59#ibcon#about to read 3, iclass 34, count 0 2006.253.08:05:38.63#ibcon#read 3, iclass 34, count 0 2006.253.08:05:38.63#ibcon#about to read 4, iclass 34, count 0 2006.253.08:05:38.63#ibcon#read 4, iclass 34, count 0 2006.253.08:05:38.63#ibcon#about to read 5, iclass 34, count 0 2006.253.08:05:38.63#ibcon#read 5, iclass 34, count 0 2006.253.08:05:38.63#ibcon#about to read 6, iclass 34, count 0 2006.253.08:05:38.63#ibcon#read 6, iclass 34, count 0 2006.253.08:05:38.63#ibcon#end of sib2, iclass 34, count 0 2006.253.08:05:38.63#ibcon#*after write, iclass 34, count 0 2006.253.08:05:38.63#ibcon#*before return 0, iclass 34, count 0 2006.253.08:05:38.63#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.253.08:05:38.63#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.253.08:05:38.63#ibcon#about to clear, iclass 34 cls_cnt 0 2006.253.08:05:38.63#ibcon#cleared, iclass 34 cls_cnt 0 2006.253.08:05:38.63$vc4f8/va=3,6 2006.253.08:05:38.63#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.253.08:05:38.63#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.253.08:05:38.63#ibcon#ireg 11 cls_cnt 2 2006.253.08:05:38.63#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.253.08:05:38.69#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.253.08:05:38.69#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.253.08:05:38.69#ibcon#enter wrdev, iclass 36, count 2 2006.253.08:05:38.69#ibcon#first serial, iclass 36, count 2 2006.253.08:05:38.69#ibcon#enter sib2, iclass 36, count 2 2006.253.08:05:38.69#ibcon#flushed, iclass 36, count 2 2006.253.08:05:38.69#ibcon#about to write, iclass 36, count 2 2006.253.08:05:38.69#ibcon#wrote, iclass 36, count 2 2006.253.08:05:38.69#ibcon#about to read 3, iclass 36, count 2 2006.253.08:05:38.71#ibcon#read 3, iclass 36, count 2 2006.253.08:05:38.71#ibcon#about to read 4, iclass 36, count 2 2006.253.08:05:38.71#ibcon#read 4, iclass 36, count 2 2006.253.08:05:38.71#ibcon#about to read 5, iclass 36, count 2 2006.253.08:05:38.71#ibcon#read 5, iclass 36, count 2 2006.253.08:05:38.71#ibcon#about to read 6, iclass 36, count 2 2006.253.08:05:38.71#ibcon#read 6, iclass 36, count 2 2006.253.08:05:38.71#ibcon#end of sib2, iclass 36, count 2 2006.253.08:05:38.71#ibcon#*mode == 0, iclass 36, count 2 2006.253.08:05:38.71#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.253.08:05:38.71#ibcon#[25=AT03-06\r\n] 2006.253.08:05:38.71#ibcon#*before write, iclass 36, count 2 2006.253.08:05:38.71#ibcon#enter sib2, iclass 36, count 2 2006.253.08:05:38.71#ibcon#flushed, iclass 36, count 2 2006.253.08:05:38.71#ibcon#about to write, iclass 36, count 2 2006.253.08:05:38.71#ibcon#wrote, iclass 36, count 2 2006.253.08:05:38.71#ibcon#about to read 3, iclass 36, count 2 2006.253.08:05:38.75#ibcon#read 3, iclass 36, count 2 2006.253.08:05:38.75#ibcon#about to read 4, iclass 36, count 2 2006.253.08:05:38.75#ibcon#read 4, iclass 36, count 2 2006.253.08:05:38.75#ibcon#about to read 5, iclass 36, count 2 2006.253.08:05:38.75#ibcon#read 5, iclass 36, count 2 2006.253.08:05:38.75#ibcon#about to read 6, iclass 36, count 2 2006.253.08:05:38.75#ibcon#read 6, iclass 36, count 2 2006.253.08:05:38.75#ibcon#end of sib2, iclass 36, count 2 2006.253.08:05:38.75#ibcon#*after write, iclass 36, count 2 2006.253.08:05:38.75#ibcon#*before return 0, iclass 36, count 2 2006.253.08:05:38.75#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.253.08:05:38.75#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.253.08:05:38.75#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.253.08:05:38.75#ibcon#ireg 7 cls_cnt 0 2006.253.08:05:38.75#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.253.08:05:38.86#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.253.08:05:38.86#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.253.08:05:38.86#ibcon#enter wrdev, iclass 36, count 0 2006.253.08:05:38.86#ibcon#first serial, iclass 36, count 0 2006.253.08:05:38.86#ibcon#enter sib2, iclass 36, count 0 2006.253.08:05:38.86#ibcon#flushed, iclass 36, count 0 2006.253.08:05:38.86#ibcon#about to write, iclass 36, count 0 2006.253.08:05:38.86#ibcon#wrote, iclass 36, count 0 2006.253.08:05:38.86#ibcon#about to read 3, iclass 36, count 0 2006.253.08:05:38.89#ibcon#read 3, iclass 36, count 0 2006.253.08:05:38.89#ibcon#about to read 4, iclass 36, count 0 2006.253.08:05:38.89#ibcon#read 4, iclass 36, count 0 2006.253.08:05:38.89#ibcon#about to read 5, iclass 36, count 0 2006.253.08:05:38.89#ibcon#read 5, iclass 36, count 0 2006.253.08:05:38.89#ibcon#about to read 6, iclass 36, count 0 2006.253.08:05:38.89#ibcon#read 6, iclass 36, count 0 2006.253.08:05:38.89#ibcon#end of sib2, iclass 36, count 0 2006.253.08:05:38.89#ibcon#*mode == 0, iclass 36, count 0 2006.253.08:05:38.89#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.253.08:05:38.89#ibcon#[25=USB\r\n] 2006.253.08:05:38.89#ibcon#*before write, iclass 36, count 0 2006.253.08:05:38.89#ibcon#enter sib2, iclass 36, count 0 2006.253.08:05:38.89#ibcon#flushed, iclass 36, count 0 2006.253.08:05:38.89#ibcon#about to write, iclass 36, count 0 2006.253.08:05:38.90#ibcon#wrote, iclass 36, count 0 2006.253.08:05:38.90#ibcon#about to read 3, iclass 36, count 0 2006.253.08:05:38.92#ibcon#read 3, iclass 36, count 0 2006.253.08:05:38.92#ibcon#about to read 4, iclass 36, count 0 2006.253.08:05:38.92#ibcon#read 4, iclass 36, count 0 2006.253.08:05:38.92#ibcon#about to read 5, iclass 36, count 0 2006.253.08:05:38.92#ibcon#read 5, iclass 36, count 0 2006.253.08:05:38.92#ibcon#about to read 6, iclass 36, count 0 2006.253.08:05:38.92#ibcon#read 6, iclass 36, count 0 2006.253.08:05:38.92#ibcon#end of sib2, iclass 36, count 0 2006.253.08:05:38.92#ibcon#*after write, iclass 36, count 0 2006.253.08:05:38.92#ibcon#*before return 0, iclass 36, count 0 2006.253.08:05:38.92#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.253.08:05:38.92#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.253.08:05:38.92#ibcon#about to clear, iclass 36 cls_cnt 0 2006.253.08:05:38.92#ibcon#cleared, iclass 36 cls_cnt 0 2006.253.08:05:38.92$vc4f8/valo=4,832.99 2006.253.08:05:38.92#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.253.08:05:38.92#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.253.08:05:38.92#ibcon#ireg 17 cls_cnt 0 2006.253.08:05:38.92#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.253.08:05:38.92#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.253.08:05:38.92#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.253.08:05:38.92#ibcon#enter wrdev, iclass 38, count 0 2006.253.08:05:38.92#ibcon#first serial, iclass 38, count 0 2006.253.08:05:38.92#ibcon#enter sib2, iclass 38, count 0 2006.253.08:05:38.92#ibcon#flushed, iclass 38, count 0 2006.253.08:05:38.92#ibcon#about to write, iclass 38, count 0 2006.253.08:05:38.92#ibcon#wrote, iclass 38, count 0 2006.253.08:05:38.92#ibcon#about to read 3, iclass 38, count 0 2006.253.08:05:38.94#ibcon#read 3, iclass 38, count 0 2006.253.08:05:38.94#ibcon#about to read 4, iclass 38, count 0 2006.253.08:05:38.94#ibcon#read 4, iclass 38, count 0 2006.253.08:05:38.94#ibcon#about to read 5, iclass 38, count 0 2006.253.08:05:38.94#ibcon#read 5, iclass 38, count 0 2006.253.08:05:38.94#ibcon#about to read 6, iclass 38, count 0 2006.253.08:05:38.94#ibcon#read 6, iclass 38, count 0 2006.253.08:05:38.94#ibcon#end of sib2, iclass 38, count 0 2006.253.08:05:38.94#ibcon#*mode == 0, iclass 38, count 0 2006.253.08:05:38.94#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.253.08:05:38.94#ibcon#[26=FRQ=04,832.99\r\n] 2006.253.08:05:38.94#ibcon#*before write, iclass 38, count 0 2006.253.08:05:38.94#ibcon#enter sib2, iclass 38, count 0 2006.253.08:05:38.94#ibcon#flushed, iclass 38, count 0 2006.253.08:05:38.94#ibcon#about to write, iclass 38, count 0 2006.253.08:05:38.94#ibcon#wrote, iclass 38, count 0 2006.253.08:05:38.94#ibcon#about to read 3, iclass 38, count 0 2006.253.08:05:38.98#ibcon#read 3, iclass 38, count 0 2006.253.08:05:38.98#ibcon#about to read 4, iclass 38, count 0 2006.253.08:05:38.98#ibcon#read 4, iclass 38, count 0 2006.253.08:05:38.98#ibcon#about to read 5, iclass 38, count 0 2006.253.08:05:38.98#ibcon#read 5, iclass 38, count 0 2006.253.08:05:38.98#ibcon#about to read 6, iclass 38, count 0 2006.253.08:05:38.98#ibcon#read 6, iclass 38, count 0 2006.253.08:05:38.98#ibcon#end of sib2, iclass 38, count 0 2006.253.08:05:38.98#ibcon#*after write, iclass 38, count 0 2006.253.08:05:38.98#ibcon#*before return 0, iclass 38, count 0 2006.253.08:05:38.98#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.253.08:05:38.98#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.253.08:05:38.98#ibcon#about to clear, iclass 38 cls_cnt 0 2006.253.08:05:38.98#ibcon#cleared, iclass 38 cls_cnt 0 2006.253.08:05:38.98$vc4f8/va=4,7 2006.253.08:05:38.98#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.253.08:05:38.98#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.253.08:05:38.98#ibcon#ireg 11 cls_cnt 2 2006.253.08:05:38.98#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.253.08:05:39.04#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.253.08:05:39.04#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.253.08:05:39.04#ibcon#enter wrdev, iclass 40, count 2 2006.253.08:05:39.04#ibcon#first serial, iclass 40, count 2 2006.253.08:05:39.04#ibcon#enter sib2, iclass 40, count 2 2006.253.08:05:39.04#ibcon#flushed, iclass 40, count 2 2006.253.08:05:39.04#ibcon#about to write, iclass 40, count 2 2006.253.08:05:39.04#ibcon#wrote, iclass 40, count 2 2006.253.08:05:39.04#ibcon#about to read 3, iclass 40, count 2 2006.253.08:05:39.06#ibcon#read 3, iclass 40, count 2 2006.253.08:05:39.06#ibcon#about to read 4, iclass 40, count 2 2006.253.08:05:39.06#ibcon#read 4, iclass 40, count 2 2006.253.08:05:39.06#ibcon#about to read 5, iclass 40, count 2 2006.253.08:05:39.06#ibcon#read 5, iclass 40, count 2 2006.253.08:05:39.06#ibcon#about to read 6, iclass 40, count 2 2006.253.08:05:39.06#ibcon#read 6, iclass 40, count 2 2006.253.08:05:39.06#ibcon#end of sib2, iclass 40, count 2 2006.253.08:05:39.06#ibcon#*mode == 0, iclass 40, count 2 2006.253.08:05:39.06#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.253.08:05:39.06#ibcon#[25=AT04-07\r\n] 2006.253.08:05:39.06#ibcon#*before write, iclass 40, count 2 2006.253.08:05:39.06#ibcon#enter sib2, iclass 40, count 2 2006.253.08:05:39.06#ibcon#flushed, iclass 40, count 2 2006.253.08:05:39.06#ibcon#about to write, iclass 40, count 2 2006.253.08:05:39.06#ibcon#wrote, iclass 40, count 2 2006.253.08:05:39.06#ibcon#about to read 3, iclass 40, count 2 2006.253.08:05:39.09#ibcon#read 3, iclass 40, count 2 2006.253.08:05:39.09#ibcon#about to read 4, iclass 40, count 2 2006.253.08:05:39.09#ibcon#read 4, iclass 40, count 2 2006.253.08:05:39.09#ibcon#about to read 5, iclass 40, count 2 2006.253.08:05:39.09#ibcon#read 5, iclass 40, count 2 2006.253.08:05:39.09#ibcon#about to read 6, iclass 40, count 2 2006.253.08:05:39.09#ibcon#read 6, iclass 40, count 2 2006.253.08:05:39.09#ibcon#end of sib2, iclass 40, count 2 2006.253.08:05:39.09#ibcon#*after write, iclass 40, count 2 2006.253.08:05:39.09#ibcon#*before return 0, iclass 40, count 2 2006.253.08:05:39.09#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.253.08:05:39.09#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.253.08:05:39.09#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.253.08:05:39.09#ibcon#ireg 7 cls_cnt 0 2006.253.08:05:39.09#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.253.08:05:39.21#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.253.08:05:39.21#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.253.08:05:39.21#ibcon#enter wrdev, iclass 40, count 0 2006.253.08:05:39.21#ibcon#first serial, iclass 40, count 0 2006.253.08:05:39.21#ibcon#enter sib2, iclass 40, count 0 2006.253.08:05:39.21#ibcon#flushed, iclass 40, count 0 2006.253.08:05:39.21#ibcon#about to write, iclass 40, count 0 2006.253.08:05:39.21#ibcon#wrote, iclass 40, count 0 2006.253.08:05:39.21#ibcon#about to read 3, iclass 40, count 0 2006.253.08:05:39.23#ibcon#read 3, iclass 40, count 0 2006.253.08:05:39.23#ibcon#about to read 4, iclass 40, count 0 2006.253.08:05:39.23#ibcon#read 4, iclass 40, count 0 2006.253.08:05:39.23#ibcon#about to read 5, iclass 40, count 0 2006.253.08:05:39.23#ibcon#read 5, iclass 40, count 0 2006.253.08:05:39.23#ibcon#about to read 6, iclass 40, count 0 2006.253.08:05:39.23#ibcon#read 6, iclass 40, count 0 2006.253.08:05:39.23#ibcon#end of sib2, iclass 40, count 0 2006.253.08:05:39.23#ibcon#*mode == 0, iclass 40, count 0 2006.253.08:05:39.23#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.253.08:05:39.23#ibcon#[25=USB\r\n] 2006.253.08:05:39.23#ibcon#*before write, iclass 40, count 0 2006.253.08:05:39.23#ibcon#enter sib2, iclass 40, count 0 2006.253.08:05:39.23#ibcon#flushed, iclass 40, count 0 2006.253.08:05:39.23#ibcon#about to write, iclass 40, count 0 2006.253.08:05:39.23#ibcon#wrote, iclass 40, count 0 2006.253.08:05:39.23#ibcon#about to read 3, iclass 40, count 0 2006.253.08:05:39.26#ibcon#read 3, iclass 40, count 0 2006.253.08:05:39.26#ibcon#about to read 4, iclass 40, count 0 2006.253.08:05:39.26#ibcon#read 4, iclass 40, count 0 2006.253.08:05:39.26#ibcon#about to read 5, iclass 40, count 0 2006.253.08:05:39.26#ibcon#read 5, iclass 40, count 0 2006.253.08:05:39.26#ibcon#about to read 6, iclass 40, count 0 2006.253.08:05:39.26#ibcon#read 6, iclass 40, count 0 2006.253.08:05:39.26#ibcon#end of sib2, iclass 40, count 0 2006.253.08:05:39.26#ibcon#*after write, iclass 40, count 0 2006.253.08:05:39.26#ibcon#*before return 0, iclass 40, count 0 2006.253.08:05:39.26#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.253.08:05:39.26#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.253.08:05:39.26#ibcon#about to clear, iclass 40 cls_cnt 0 2006.253.08:05:39.26#ibcon#cleared, iclass 40 cls_cnt 0 2006.253.08:05:39.26$vc4f8/valo=5,652.99 2006.253.08:05:39.26#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.253.08:05:39.26#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.253.08:05:39.26#ibcon#ireg 17 cls_cnt 0 2006.253.08:05:39.26#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.253.08:05:39.26#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.253.08:05:39.26#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.253.08:05:39.26#ibcon#enter wrdev, iclass 4, count 0 2006.253.08:05:39.26#ibcon#first serial, iclass 4, count 0 2006.253.08:05:39.26#ibcon#enter sib2, iclass 4, count 0 2006.253.08:05:39.26#ibcon#flushed, iclass 4, count 0 2006.253.08:05:39.26#ibcon#about to write, iclass 4, count 0 2006.253.08:05:39.26#ibcon#wrote, iclass 4, count 0 2006.253.08:05:39.26#ibcon#about to read 3, iclass 4, count 0 2006.253.08:05:39.28#ibcon#read 3, iclass 4, count 0 2006.253.08:05:39.28#ibcon#about to read 4, iclass 4, count 0 2006.253.08:05:39.28#ibcon#read 4, iclass 4, count 0 2006.253.08:05:39.28#ibcon#about to read 5, iclass 4, count 0 2006.253.08:05:39.28#ibcon#read 5, iclass 4, count 0 2006.253.08:05:39.28#ibcon#about to read 6, iclass 4, count 0 2006.253.08:05:39.28#ibcon#read 6, iclass 4, count 0 2006.253.08:05:39.28#ibcon#end of sib2, iclass 4, count 0 2006.253.08:05:39.28#ibcon#*mode == 0, iclass 4, count 0 2006.253.08:05:39.28#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.253.08:05:39.28#ibcon#[26=FRQ=05,652.99\r\n] 2006.253.08:05:39.28#ibcon#*before write, iclass 4, count 0 2006.253.08:05:39.28#ibcon#enter sib2, iclass 4, count 0 2006.253.08:05:39.28#ibcon#flushed, iclass 4, count 0 2006.253.08:05:39.28#ibcon#about to write, iclass 4, count 0 2006.253.08:05:39.28#ibcon#wrote, iclass 4, count 0 2006.253.08:05:39.28#ibcon#about to read 3, iclass 4, count 0 2006.253.08:05:39.32#ibcon#read 3, iclass 4, count 0 2006.253.08:05:39.32#ibcon#about to read 4, iclass 4, count 0 2006.253.08:05:39.32#ibcon#read 4, iclass 4, count 0 2006.253.08:05:39.32#ibcon#about to read 5, iclass 4, count 0 2006.253.08:05:39.32#ibcon#read 5, iclass 4, count 0 2006.253.08:05:39.32#ibcon#about to read 6, iclass 4, count 0 2006.253.08:05:39.32#ibcon#read 6, iclass 4, count 0 2006.253.08:05:39.32#ibcon#end of sib2, iclass 4, count 0 2006.253.08:05:39.32#ibcon#*after write, iclass 4, count 0 2006.253.08:05:39.32#ibcon#*before return 0, iclass 4, count 0 2006.253.08:05:39.32#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.253.08:05:39.32#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.253.08:05:39.32#ibcon#about to clear, iclass 4 cls_cnt 0 2006.253.08:05:39.32#ibcon#cleared, iclass 4 cls_cnt 0 2006.253.08:05:39.32$vc4f8/va=5,7 2006.253.08:05:39.32#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.253.08:05:39.32#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.253.08:05:39.32#ibcon#ireg 11 cls_cnt 2 2006.253.08:05:39.32#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.253.08:05:39.38#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.253.08:05:39.38#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.253.08:05:39.38#ibcon#enter wrdev, iclass 6, count 2 2006.253.08:05:39.38#ibcon#first serial, iclass 6, count 2 2006.253.08:05:39.38#ibcon#enter sib2, iclass 6, count 2 2006.253.08:05:39.38#ibcon#flushed, iclass 6, count 2 2006.253.08:05:39.38#ibcon#about to write, iclass 6, count 2 2006.253.08:05:39.38#ibcon#wrote, iclass 6, count 2 2006.253.08:05:39.38#ibcon#about to read 3, iclass 6, count 2 2006.253.08:05:39.40#ibcon#read 3, iclass 6, count 2 2006.253.08:05:39.40#ibcon#about to read 4, iclass 6, count 2 2006.253.08:05:39.40#ibcon#read 4, iclass 6, count 2 2006.253.08:05:39.40#ibcon#about to read 5, iclass 6, count 2 2006.253.08:05:39.40#ibcon#read 5, iclass 6, count 2 2006.253.08:05:39.40#ibcon#about to read 6, iclass 6, count 2 2006.253.08:05:39.40#ibcon#read 6, iclass 6, count 2 2006.253.08:05:39.40#ibcon#end of sib2, iclass 6, count 2 2006.253.08:05:39.40#ibcon#*mode == 0, iclass 6, count 2 2006.253.08:05:39.40#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.253.08:05:39.40#ibcon#[25=AT05-07\r\n] 2006.253.08:05:39.40#ibcon#*before write, iclass 6, count 2 2006.253.08:05:39.40#ibcon#enter sib2, iclass 6, count 2 2006.253.08:05:39.40#ibcon#flushed, iclass 6, count 2 2006.253.08:05:39.40#ibcon#about to write, iclass 6, count 2 2006.253.08:05:39.40#ibcon#wrote, iclass 6, count 2 2006.253.08:05:39.40#ibcon#about to read 3, iclass 6, count 2 2006.253.08:05:39.43#ibcon#read 3, iclass 6, count 2 2006.253.08:05:39.43#ibcon#about to read 4, iclass 6, count 2 2006.253.08:05:39.43#ibcon#read 4, iclass 6, count 2 2006.253.08:05:39.43#ibcon#about to read 5, iclass 6, count 2 2006.253.08:05:39.43#ibcon#read 5, iclass 6, count 2 2006.253.08:05:39.43#ibcon#about to read 6, iclass 6, count 2 2006.253.08:05:39.43#ibcon#read 6, iclass 6, count 2 2006.253.08:05:39.43#ibcon#end of sib2, iclass 6, count 2 2006.253.08:05:39.43#ibcon#*after write, iclass 6, count 2 2006.253.08:05:39.43#ibcon#*before return 0, iclass 6, count 2 2006.253.08:05:39.43#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.253.08:05:39.43#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.253.08:05:39.43#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.253.08:05:39.43#ibcon#ireg 7 cls_cnt 0 2006.253.08:05:39.43#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.253.08:05:39.55#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.253.08:05:39.55#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.253.08:05:39.55#ibcon#enter wrdev, iclass 6, count 0 2006.253.08:05:39.55#ibcon#first serial, iclass 6, count 0 2006.253.08:05:39.55#ibcon#enter sib2, iclass 6, count 0 2006.253.08:05:39.55#ibcon#flushed, iclass 6, count 0 2006.253.08:05:39.55#ibcon#about to write, iclass 6, count 0 2006.253.08:05:39.55#ibcon#wrote, iclass 6, count 0 2006.253.08:05:39.55#ibcon#about to read 3, iclass 6, count 0 2006.253.08:05:39.57#ibcon#read 3, iclass 6, count 0 2006.253.08:05:39.57#ibcon#about to read 4, iclass 6, count 0 2006.253.08:05:39.57#ibcon#read 4, iclass 6, count 0 2006.253.08:05:39.57#ibcon#about to read 5, iclass 6, count 0 2006.253.08:05:39.57#ibcon#read 5, iclass 6, count 0 2006.253.08:05:39.57#ibcon#about to read 6, iclass 6, count 0 2006.253.08:05:39.57#ibcon#read 6, iclass 6, count 0 2006.253.08:05:39.57#ibcon#end of sib2, iclass 6, count 0 2006.253.08:05:39.57#ibcon#*mode == 0, iclass 6, count 0 2006.253.08:05:39.57#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.253.08:05:39.57#ibcon#[25=USB\r\n] 2006.253.08:05:39.57#ibcon#*before write, iclass 6, count 0 2006.253.08:05:39.57#ibcon#enter sib2, iclass 6, count 0 2006.253.08:05:39.57#ibcon#flushed, iclass 6, count 0 2006.253.08:05:39.57#ibcon#about to write, iclass 6, count 0 2006.253.08:05:39.57#ibcon#wrote, iclass 6, count 0 2006.253.08:05:39.57#ibcon#about to read 3, iclass 6, count 0 2006.253.08:05:39.60#ibcon#read 3, iclass 6, count 0 2006.253.08:05:39.60#ibcon#about to read 4, iclass 6, count 0 2006.253.08:05:39.60#ibcon#read 4, iclass 6, count 0 2006.253.08:05:39.60#ibcon#about to read 5, iclass 6, count 0 2006.253.08:05:39.60#ibcon#read 5, iclass 6, count 0 2006.253.08:05:39.60#ibcon#about to read 6, iclass 6, count 0 2006.253.08:05:39.60#ibcon#read 6, iclass 6, count 0 2006.253.08:05:39.60#ibcon#end of sib2, iclass 6, count 0 2006.253.08:05:39.60#ibcon#*after write, iclass 6, count 0 2006.253.08:05:39.60#ibcon#*before return 0, iclass 6, count 0 2006.253.08:05:39.60#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.253.08:05:39.60#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.253.08:05:39.60#ibcon#about to clear, iclass 6 cls_cnt 0 2006.253.08:05:39.60#ibcon#cleared, iclass 6 cls_cnt 0 2006.253.08:05:39.60$vc4f8/valo=6,772.99 2006.253.08:05:39.60#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.253.08:05:39.60#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.253.08:05:39.60#ibcon#ireg 17 cls_cnt 0 2006.253.08:05:39.60#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.253.08:05:39.60#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.253.08:05:39.60#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.253.08:05:39.60#ibcon#enter wrdev, iclass 10, count 0 2006.253.08:05:39.60#ibcon#first serial, iclass 10, count 0 2006.253.08:05:39.60#ibcon#enter sib2, iclass 10, count 0 2006.253.08:05:39.60#ibcon#flushed, iclass 10, count 0 2006.253.08:05:39.60#ibcon#about to write, iclass 10, count 0 2006.253.08:05:39.60#ibcon#wrote, iclass 10, count 0 2006.253.08:05:39.60#ibcon#about to read 3, iclass 10, count 0 2006.253.08:05:39.63#ibcon#read 3, iclass 10, count 0 2006.253.08:05:39.63#ibcon#about to read 4, iclass 10, count 0 2006.253.08:05:39.63#ibcon#read 4, iclass 10, count 0 2006.253.08:05:39.63#ibcon#about to read 5, iclass 10, count 0 2006.253.08:05:39.63#ibcon#read 5, iclass 10, count 0 2006.253.08:05:39.63#ibcon#about to read 6, iclass 10, count 0 2006.253.08:05:39.63#ibcon#read 6, iclass 10, count 0 2006.253.08:05:39.63#ibcon#end of sib2, iclass 10, count 0 2006.253.08:05:39.63#ibcon#*mode == 0, iclass 10, count 0 2006.253.08:05:39.63#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.253.08:05:39.63#ibcon#[26=FRQ=06,772.99\r\n] 2006.253.08:05:39.63#ibcon#*before write, iclass 10, count 0 2006.253.08:05:39.63#ibcon#enter sib2, iclass 10, count 0 2006.253.08:05:39.63#ibcon#flushed, iclass 10, count 0 2006.253.08:05:39.63#ibcon#about to write, iclass 10, count 0 2006.253.08:05:39.63#ibcon#wrote, iclass 10, count 0 2006.253.08:05:39.63#ibcon#about to read 3, iclass 10, count 0 2006.253.08:05:39.67#ibcon#read 3, iclass 10, count 0 2006.253.08:05:39.67#ibcon#about to read 4, iclass 10, count 0 2006.253.08:05:39.67#ibcon#read 4, iclass 10, count 0 2006.253.08:05:39.67#ibcon#about to read 5, iclass 10, count 0 2006.253.08:05:39.67#ibcon#read 5, iclass 10, count 0 2006.253.08:05:39.67#ibcon#about to read 6, iclass 10, count 0 2006.253.08:05:39.67#ibcon#read 6, iclass 10, count 0 2006.253.08:05:39.67#ibcon#end of sib2, iclass 10, count 0 2006.253.08:05:39.67#ibcon#*after write, iclass 10, count 0 2006.253.08:05:39.67#ibcon#*before return 0, iclass 10, count 0 2006.253.08:05:39.67#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.253.08:05:39.67#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.253.08:05:39.67#ibcon#about to clear, iclass 10 cls_cnt 0 2006.253.08:05:39.67#ibcon#cleared, iclass 10 cls_cnt 0 2006.253.08:05:39.67$vc4f8/va=6,7 2006.253.08:05:39.67#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.253.08:05:39.67#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.253.08:05:39.67#ibcon#ireg 11 cls_cnt 2 2006.253.08:05:39.67#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.253.08:05:39.72#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.253.08:05:39.72#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.253.08:05:39.72#ibcon#enter wrdev, iclass 12, count 2 2006.253.08:05:39.72#ibcon#first serial, iclass 12, count 2 2006.253.08:05:39.72#ibcon#enter sib2, iclass 12, count 2 2006.253.08:05:39.72#ibcon#flushed, iclass 12, count 2 2006.253.08:05:39.72#ibcon#about to write, iclass 12, count 2 2006.253.08:05:39.72#ibcon#wrote, iclass 12, count 2 2006.253.08:05:39.72#ibcon#about to read 3, iclass 12, count 2 2006.253.08:05:39.74#ibcon#read 3, iclass 12, count 2 2006.253.08:05:39.74#ibcon#about to read 4, iclass 12, count 2 2006.253.08:05:39.74#ibcon#read 4, iclass 12, count 2 2006.253.08:05:39.74#ibcon#about to read 5, iclass 12, count 2 2006.253.08:05:39.74#ibcon#read 5, iclass 12, count 2 2006.253.08:05:39.74#ibcon#about to read 6, iclass 12, count 2 2006.253.08:05:39.74#ibcon#read 6, iclass 12, count 2 2006.253.08:05:39.74#ibcon#end of sib2, iclass 12, count 2 2006.253.08:05:39.74#ibcon#*mode == 0, iclass 12, count 2 2006.253.08:05:39.74#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.253.08:05:39.74#ibcon#[25=AT06-07\r\n] 2006.253.08:05:39.74#ibcon#*before write, iclass 12, count 2 2006.253.08:05:39.74#ibcon#enter sib2, iclass 12, count 2 2006.253.08:05:39.74#ibcon#flushed, iclass 12, count 2 2006.253.08:05:39.74#ibcon#about to write, iclass 12, count 2 2006.253.08:05:39.74#ibcon#wrote, iclass 12, count 2 2006.253.08:05:39.74#ibcon#about to read 3, iclass 12, count 2 2006.253.08:05:39.77#ibcon#read 3, iclass 12, count 2 2006.253.08:05:39.77#ibcon#about to read 4, iclass 12, count 2 2006.253.08:05:39.77#ibcon#read 4, iclass 12, count 2 2006.253.08:05:39.77#ibcon#about to read 5, iclass 12, count 2 2006.253.08:05:39.77#ibcon#read 5, iclass 12, count 2 2006.253.08:05:39.77#ibcon#about to read 6, iclass 12, count 2 2006.253.08:05:39.77#ibcon#read 6, iclass 12, count 2 2006.253.08:05:39.77#ibcon#end of sib2, iclass 12, count 2 2006.253.08:05:39.77#ibcon#*after write, iclass 12, count 2 2006.253.08:05:39.77#ibcon#*before return 0, iclass 12, count 2 2006.253.08:05:39.77#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.253.08:05:39.77#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.253.08:05:39.77#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.253.08:05:39.77#ibcon#ireg 7 cls_cnt 0 2006.253.08:05:39.77#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.253.08:05:39.89#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.253.08:05:39.89#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.253.08:05:39.89#ibcon#enter wrdev, iclass 12, count 0 2006.253.08:05:39.89#ibcon#first serial, iclass 12, count 0 2006.253.08:05:39.89#ibcon#enter sib2, iclass 12, count 0 2006.253.08:05:39.89#ibcon#flushed, iclass 12, count 0 2006.253.08:05:39.89#ibcon#about to write, iclass 12, count 0 2006.253.08:05:39.89#ibcon#wrote, iclass 12, count 0 2006.253.08:05:39.89#ibcon#about to read 3, iclass 12, count 0 2006.253.08:05:39.91#ibcon#read 3, iclass 12, count 0 2006.253.08:05:39.91#ibcon#about to read 4, iclass 12, count 0 2006.253.08:05:39.91#ibcon#read 4, iclass 12, count 0 2006.253.08:05:39.91#ibcon#about to read 5, iclass 12, count 0 2006.253.08:05:39.91#ibcon#read 5, iclass 12, count 0 2006.253.08:05:39.91#ibcon#about to read 6, iclass 12, count 0 2006.253.08:05:39.91#ibcon#read 6, iclass 12, count 0 2006.253.08:05:39.91#ibcon#end of sib2, iclass 12, count 0 2006.253.08:05:39.91#ibcon#*mode == 0, iclass 12, count 0 2006.253.08:05:39.91#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.253.08:05:39.91#ibcon#[25=USB\r\n] 2006.253.08:05:39.91#ibcon#*before write, iclass 12, count 0 2006.253.08:05:39.91#ibcon#enter sib2, iclass 12, count 0 2006.253.08:05:39.91#ibcon#flushed, iclass 12, count 0 2006.253.08:05:39.91#ibcon#about to write, iclass 12, count 0 2006.253.08:05:39.91#ibcon#wrote, iclass 12, count 0 2006.253.08:05:39.91#ibcon#about to read 3, iclass 12, count 0 2006.253.08:05:39.94#ibcon#read 3, iclass 12, count 0 2006.253.08:05:39.94#ibcon#about to read 4, iclass 12, count 0 2006.253.08:05:39.94#ibcon#read 4, iclass 12, count 0 2006.253.08:05:39.94#ibcon#about to read 5, iclass 12, count 0 2006.253.08:05:39.94#ibcon#read 5, iclass 12, count 0 2006.253.08:05:39.94#ibcon#about to read 6, iclass 12, count 0 2006.253.08:05:39.94#ibcon#read 6, iclass 12, count 0 2006.253.08:05:39.94#ibcon#end of sib2, iclass 12, count 0 2006.253.08:05:39.94#ibcon#*after write, iclass 12, count 0 2006.253.08:05:39.94#ibcon#*before return 0, iclass 12, count 0 2006.253.08:05:39.94#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.253.08:05:39.94#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.253.08:05:39.94#ibcon#about to clear, iclass 12 cls_cnt 0 2006.253.08:05:39.94#ibcon#cleared, iclass 12 cls_cnt 0 2006.253.08:05:39.94$vc4f8/valo=7,832.99 2006.253.08:05:39.94#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.253.08:05:39.94#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.253.08:05:39.94#ibcon#ireg 17 cls_cnt 0 2006.253.08:05:39.94#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.253.08:05:39.94#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.253.08:05:39.94#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.253.08:05:39.94#ibcon#enter wrdev, iclass 14, count 0 2006.253.08:05:39.94#ibcon#first serial, iclass 14, count 0 2006.253.08:05:39.94#ibcon#enter sib2, iclass 14, count 0 2006.253.08:05:39.94#ibcon#flushed, iclass 14, count 0 2006.253.08:05:39.94#ibcon#about to write, iclass 14, count 0 2006.253.08:05:39.94#ibcon#wrote, iclass 14, count 0 2006.253.08:05:39.94#ibcon#about to read 3, iclass 14, count 0 2006.253.08:05:39.96#ibcon#read 3, iclass 14, count 0 2006.253.08:05:39.96#ibcon#about to read 4, iclass 14, count 0 2006.253.08:05:39.96#ibcon#read 4, iclass 14, count 0 2006.253.08:05:39.96#ibcon#about to read 5, iclass 14, count 0 2006.253.08:05:39.96#ibcon#read 5, iclass 14, count 0 2006.253.08:05:39.96#ibcon#about to read 6, iclass 14, count 0 2006.253.08:05:39.96#ibcon#read 6, iclass 14, count 0 2006.253.08:05:39.96#ibcon#end of sib2, iclass 14, count 0 2006.253.08:05:39.96#ibcon#*mode == 0, iclass 14, count 0 2006.253.08:05:39.96#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.253.08:05:39.96#ibcon#[26=FRQ=07,832.99\r\n] 2006.253.08:05:39.96#ibcon#*before write, iclass 14, count 0 2006.253.08:05:39.96#ibcon#enter sib2, iclass 14, count 0 2006.253.08:05:39.96#ibcon#flushed, iclass 14, count 0 2006.253.08:05:39.96#ibcon#about to write, iclass 14, count 0 2006.253.08:05:39.96#ibcon#wrote, iclass 14, count 0 2006.253.08:05:39.96#ibcon#about to read 3, iclass 14, count 0 2006.253.08:05:40.00#ibcon#read 3, iclass 14, count 0 2006.253.08:05:40.00#ibcon#about to read 4, iclass 14, count 0 2006.253.08:05:40.00#ibcon#read 4, iclass 14, count 0 2006.253.08:05:40.00#ibcon#about to read 5, iclass 14, count 0 2006.253.08:05:40.00#ibcon#read 5, iclass 14, count 0 2006.253.08:05:40.00#ibcon#about to read 6, iclass 14, count 0 2006.253.08:05:40.00#ibcon#read 6, iclass 14, count 0 2006.253.08:05:40.00#ibcon#end of sib2, iclass 14, count 0 2006.253.08:05:40.00#ibcon#*after write, iclass 14, count 0 2006.253.08:05:40.00#ibcon#*before return 0, iclass 14, count 0 2006.253.08:05:40.00#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.253.08:05:40.00#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.253.08:05:40.00#ibcon#about to clear, iclass 14 cls_cnt 0 2006.253.08:05:40.00#ibcon#cleared, iclass 14 cls_cnt 0 2006.253.08:05:40.00$vc4f8/va=7,7 2006.253.08:05:40.00#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.253.08:05:40.00#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.253.08:05:40.00#ibcon#ireg 11 cls_cnt 2 2006.253.08:05:40.00#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.253.08:05:40.06#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.253.08:05:40.06#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.253.08:05:40.06#ibcon#enter wrdev, iclass 16, count 2 2006.253.08:05:40.06#ibcon#first serial, iclass 16, count 2 2006.253.08:05:40.06#ibcon#enter sib2, iclass 16, count 2 2006.253.08:05:40.06#ibcon#flushed, iclass 16, count 2 2006.253.08:05:40.06#ibcon#about to write, iclass 16, count 2 2006.253.08:05:40.06#ibcon#wrote, iclass 16, count 2 2006.253.08:05:40.06#ibcon#about to read 3, iclass 16, count 2 2006.253.08:05:40.08#ibcon#read 3, iclass 16, count 2 2006.253.08:05:40.08#ibcon#about to read 4, iclass 16, count 2 2006.253.08:05:40.08#ibcon#read 4, iclass 16, count 2 2006.253.08:05:40.08#ibcon#about to read 5, iclass 16, count 2 2006.253.08:05:40.08#ibcon#read 5, iclass 16, count 2 2006.253.08:05:40.08#ibcon#about to read 6, iclass 16, count 2 2006.253.08:05:40.08#ibcon#read 6, iclass 16, count 2 2006.253.08:05:40.08#ibcon#end of sib2, iclass 16, count 2 2006.253.08:05:40.08#ibcon#*mode == 0, iclass 16, count 2 2006.253.08:05:40.08#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.253.08:05:40.08#ibcon#[25=AT07-07\r\n] 2006.253.08:05:40.08#ibcon#*before write, iclass 16, count 2 2006.253.08:05:40.08#ibcon#enter sib2, iclass 16, count 2 2006.253.08:05:40.08#ibcon#flushed, iclass 16, count 2 2006.253.08:05:40.08#ibcon#about to write, iclass 16, count 2 2006.253.08:05:40.08#ibcon#wrote, iclass 16, count 2 2006.253.08:05:40.08#ibcon#about to read 3, iclass 16, count 2 2006.253.08:05:40.11#ibcon#read 3, iclass 16, count 2 2006.253.08:05:40.11#ibcon#about to read 4, iclass 16, count 2 2006.253.08:05:40.11#ibcon#read 4, iclass 16, count 2 2006.253.08:05:40.11#ibcon#about to read 5, iclass 16, count 2 2006.253.08:05:40.11#ibcon#read 5, iclass 16, count 2 2006.253.08:05:40.11#ibcon#about to read 6, iclass 16, count 2 2006.253.08:05:40.11#ibcon#read 6, iclass 16, count 2 2006.253.08:05:40.11#ibcon#end of sib2, iclass 16, count 2 2006.253.08:05:40.11#ibcon#*after write, iclass 16, count 2 2006.253.08:05:40.11#ibcon#*before return 0, iclass 16, count 2 2006.253.08:05:40.11#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.253.08:05:40.11#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.253.08:05:40.11#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.253.08:05:40.11#ibcon#ireg 7 cls_cnt 0 2006.253.08:05:40.11#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.253.08:05:40.23#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.253.08:05:40.23#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.253.08:05:40.23#ibcon#enter wrdev, iclass 16, count 0 2006.253.08:05:40.23#ibcon#first serial, iclass 16, count 0 2006.253.08:05:40.23#ibcon#enter sib2, iclass 16, count 0 2006.253.08:05:40.23#ibcon#flushed, iclass 16, count 0 2006.253.08:05:40.23#ibcon#about to write, iclass 16, count 0 2006.253.08:05:40.23#ibcon#wrote, iclass 16, count 0 2006.253.08:05:40.23#ibcon#about to read 3, iclass 16, count 0 2006.253.08:05:40.25#ibcon#read 3, iclass 16, count 0 2006.253.08:05:40.25#ibcon#about to read 4, iclass 16, count 0 2006.253.08:05:40.25#ibcon#read 4, iclass 16, count 0 2006.253.08:05:40.25#ibcon#about to read 5, iclass 16, count 0 2006.253.08:05:40.25#ibcon#read 5, iclass 16, count 0 2006.253.08:05:40.25#ibcon#about to read 6, iclass 16, count 0 2006.253.08:05:40.25#ibcon#read 6, iclass 16, count 0 2006.253.08:05:40.25#ibcon#end of sib2, iclass 16, count 0 2006.253.08:05:40.25#ibcon#*mode == 0, iclass 16, count 0 2006.253.08:05:40.25#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.253.08:05:40.25#ibcon#[25=USB\r\n] 2006.253.08:05:40.25#ibcon#*before write, iclass 16, count 0 2006.253.08:05:40.25#ibcon#enter sib2, iclass 16, count 0 2006.253.08:05:40.25#ibcon#flushed, iclass 16, count 0 2006.253.08:05:40.25#ibcon#about to write, iclass 16, count 0 2006.253.08:05:40.25#ibcon#wrote, iclass 16, count 0 2006.253.08:05:40.25#ibcon#about to read 3, iclass 16, count 0 2006.253.08:05:40.28#ibcon#read 3, iclass 16, count 0 2006.253.08:05:40.28#ibcon#about to read 4, iclass 16, count 0 2006.253.08:05:40.28#ibcon#read 4, iclass 16, count 0 2006.253.08:05:40.28#ibcon#about to read 5, iclass 16, count 0 2006.253.08:05:40.28#ibcon#read 5, iclass 16, count 0 2006.253.08:05:40.28#ibcon#about to read 6, iclass 16, count 0 2006.253.08:05:40.28#ibcon#read 6, iclass 16, count 0 2006.253.08:05:40.28#ibcon#end of sib2, iclass 16, count 0 2006.253.08:05:40.28#ibcon#*after write, iclass 16, count 0 2006.253.08:05:40.28#ibcon#*before return 0, iclass 16, count 0 2006.253.08:05:40.28#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.253.08:05:40.28#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.253.08:05:40.28#ibcon#about to clear, iclass 16 cls_cnt 0 2006.253.08:05:40.28#ibcon#cleared, iclass 16 cls_cnt 0 2006.253.08:05:40.28$vc4f8/valo=8,852.99 2006.253.08:05:40.28#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.253.08:05:40.28#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.253.08:05:40.28#ibcon#ireg 17 cls_cnt 0 2006.253.08:05:40.28#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.253.08:05:40.28#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.253.08:05:40.28#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.253.08:05:40.28#ibcon#enter wrdev, iclass 18, count 0 2006.253.08:05:40.28#ibcon#first serial, iclass 18, count 0 2006.253.08:05:40.28#ibcon#enter sib2, iclass 18, count 0 2006.253.08:05:40.28#ibcon#flushed, iclass 18, count 0 2006.253.08:05:40.28#ibcon#about to write, iclass 18, count 0 2006.253.08:05:40.28#ibcon#wrote, iclass 18, count 0 2006.253.08:05:40.28#ibcon#about to read 3, iclass 18, count 0 2006.253.08:05:40.30#ibcon#read 3, iclass 18, count 0 2006.253.08:05:40.30#ibcon#about to read 4, iclass 18, count 0 2006.253.08:05:40.30#ibcon#read 4, iclass 18, count 0 2006.253.08:05:40.30#ibcon#about to read 5, iclass 18, count 0 2006.253.08:05:40.30#ibcon#read 5, iclass 18, count 0 2006.253.08:05:40.30#ibcon#about to read 6, iclass 18, count 0 2006.253.08:05:40.30#ibcon#read 6, iclass 18, count 0 2006.253.08:05:40.30#ibcon#end of sib2, iclass 18, count 0 2006.253.08:05:40.30#ibcon#*mode == 0, iclass 18, count 0 2006.253.08:05:40.30#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.253.08:05:40.30#ibcon#[26=FRQ=08,852.99\r\n] 2006.253.08:05:40.30#ibcon#*before write, iclass 18, count 0 2006.253.08:05:40.30#ibcon#enter sib2, iclass 18, count 0 2006.253.08:05:40.30#ibcon#flushed, iclass 18, count 0 2006.253.08:05:40.30#ibcon#about to write, iclass 18, count 0 2006.253.08:05:40.30#ibcon#wrote, iclass 18, count 0 2006.253.08:05:40.30#ibcon#about to read 3, iclass 18, count 0 2006.253.08:05:40.34#ibcon#read 3, iclass 18, count 0 2006.253.08:05:40.34#ibcon#about to read 4, iclass 18, count 0 2006.253.08:05:40.34#ibcon#read 4, iclass 18, count 0 2006.253.08:05:40.34#ibcon#about to read 5, iclass 18, count 0 2006.253.08:05:40.34#ibcon#read 5, iclass 18, count 0 2006.253.08:05:40.34#ibcon#about to read 6, iclass 18, count 0 2006.253.08:05:40.34#ibcon#read 6, iclass 18, count 0 2006.253.08:05:40.34#ibcon#end of sib2, iclass 18, count 0 2006.253.08:05:40.34#ibcon#*after write, iclass 18, count 0 2006.253.08:05:40.34#ibcon#*before return 0, iclass 18, count 0 2006.253.08:05:40.34#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.253.08:05:40.34#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.253.08:05:40.34#ibcon#about to clear, iclass 18 cls_cnt 0 2006.253.08:05:40.34#ibcon#cleared, iclass 18 cls_cnt 0 2006.253.08:05:40.34$vc4f8/va=8,7 2006.253.08:05:40.34#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.253.08:05:40.34#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.253.08:05:40.34#ibcon#ireg 11 cls_cnt 2 2006.253.08:05:40.34#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.253.08:05:40.40#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.253.08:05:40.40#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.253.08:05:40.40#ibcon#enter wrdev, iclass 20, count 2 2006.253.08:05:40.40#ibcon#first serial, iclass 20, count 2 2006.253.08:05:40.40#ibcon#enter sib2, iclass 20, count 2 2006.253.08:05:40.40#ibcon#flushed, iclass 20, count 2 2006.253.08:05:40.40#ibcon#about to write, iclass 20, count 2 2006.253.08:05:40.40#ibcon#wrote, iclass 20, count 2 2006.253.08:05:40.40#ibcon#about to read 3, iclass 20, count 2 2006.253.08:05:40.42#ibcon#read 3, iclass 20, count 2 2006.253.08:05:40.42#ibcon#about to read 4, iclass 20, count 2 2006.253.08:05:40.42#ibcon#read 4, iclass 20, count 2 2006.253.08:05:40.42#ibcon#about to read 5, iclass 20, count 2 2006.253.08:05:40.42#ibcon#read 5, iclass 20, count 2 2006.253.08:05:40.42#ibcon#about to read 6, iclass 20, count 2 2006.253.08:05:40.42#ibcon#read 6, iclass 20, count 2 2006.253.08:05:40.42#ibcon#end of sib2, iclass 20, count 2 2006.253.08:05:40.42#ibcon#*mode == 0, iclass 20, count 2 2006.253.08:05:40.42#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.253.08:05:40.42#ibcon#[25=AT08-07\r\n] 2006.253.08:05:40.42#ibcon#*before write, iclass 20, count 2 2006.253.08:05:40.42#ibcon#enter sib2, iclass 20, count 2 2006.253.08:05:40.42#ibcon#flushed, iclass 20, count 2 2006.253.08:05:40.42#ibcon#about to write, iclass 20, count 2 2006.253.08:05:40.42#ibcon#wrote, iclass 20, count 2 2006.253.08:05:40.42#ibcon#about to read 3, iclass 20, count 2 2006.253.08:05:40.45#ibcon#read 3, iclass 20, count 2 2006.253.08:05:40.45#ibcon#about to read 4, iclass 20, count 2 2006.253.08:05:40.45#ibcon#read 4, iclass 20, count 2 2006.253.08:05:40.45#ibcon#about to read 5, iclass 20, count 2 2006.253.08:05:40.45#ibcon#read 5, iclass 20, count 2 2006.253.08:05:40.45#ibcon#about to read 6, iclass 20, count 2 2006.253.08:05:40.45#ibcon#read 6, iclass 20, count 2 2006.253.08:05:40.45#ibcon#end of sib2, iclass 20, count 2 2006.253.08:05:40.45#ibcon#*after write, iclass 20, count 2 2006.253.08:05:40.45#ibcon#*before return 0, iclass 20, count 2 2006.253.08:05:40.45#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.253.08:05:40.45#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.253.08:05:40.45#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.253.08:05:40.45#ibcon#ireg 7 cls_cnt 0 2006.253.08:05:40.45#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.253.08:05:40.57#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.253.08:05:40.57#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.253.08:05:40.57#ibcon#enter wrdev, iclass 20, count 0 2006.253.08:05:40.57#ibcon#first serial, iclass 20, count 0 2006.253.08:05:40.57#ibcon#enter sib2, iclass 20, count 0 2006.253.08:05:40.57#ibcon#flushed, iclass 20, count 0 2006.253.08:05:40.57#ibcon#about to write, iclass 20, count 0 2006.253.08:05:40.57#ibcon#wrote, iclass 20, count 0 2006.253.08:05:40.57#ibcon#about to read 3, iclass 20, count 0 2006.253.08:05:40.59#ibcon#read 3, iclass 20, count 0 2006.253.08:05:40.59#ibcon#about to read 4, iclass 20, count 0 2006.253.08:05:40.59#ibcon#read 4, iclass 20, count 0 2006.253.08:05:40.59#ibcon#about to read 5, iclass 20, count 0 2006.253.08:05:40.59#ibcon#read 5, iclass 20, count 0 2006.253.08:05:40.59#ibcon#about to read 6, iclass 20, count 0 2006.253.08:05:40.59#ibcon#read 6, iclass 20, count 0 2006.253.08:05:40.59#ibcon#end of sib2, iclass 20, count 0 2006.253.08:05:40.59#ibcon#*mode == 0, iclass 20, count 0 2006.253.08:05:40.59#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.253.08:05:40.59#ibcon#[25=USB\r\n] 2006.253.08:05:40.59#ibcon#*before write, iclass 20, count 0 2006.253.08:05:40.59#ibcon#enter sib2, iclass 20, count 0 2006.253.08:05:40.59#ibcon#flushed, iclass 20, count 0 2006.253.08:05:40.59#ibcon#about to write, iclass 20, count 0 2006.253.08:05:40.59#ibcon#wrote, iclass 20, count 0 2006.253.08:05:40.59#ibcon#about to read 3, iclass 20, count 0 2006.253.08:05:40.62#ibcon#read 3, iclass 20, count 0 2006.253.08:05:40.62#ibcon#about to read 4, iclass 20, count 0 2006.253.08:05:40.62#ibcon#read 4, iclass 20, count 0 2006.253.08:05:40.62#ibcon#about to read 5, iclass 20, count 0 2006.253.08:05:40.62#ibcon#read 5, iclass 20, count 0 2006.253.08:05:40.62#ibcon#about to read 6, iclass 20, count 0 2006.253.08:05:40.62#ibcon#read 6, iclass 20, count 0 2006.253.08:05:40.62#ibcon#end of sib2, iclass 20, count 0 2006.253.08:05:40.62#ibcon#*after write, iclass 20, count 0 2006.253.08:05:40.62#ibcon#*before return 0, iclass 20, count 0 2006.253.08:05:40.62#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.253.08:05:40.62#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.253.08:05:40.62#ibcon#about to clear, iclass 20 cls_cnt 0 2006.253.08:05:40.62#ibcon#cleared, iclass 20 cls_cnt 0 2006.253.08:05:40.62$vc4f8/vblo=1,632.99 2006.253.08:05:40.62#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.253.08:05:40.62#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.253.08:05:40.62#ibcon#ireg 17 cls_cnt 0 2006.253.08:05:40.62#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.253.08:05:40.62#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.253.08:05:40.62#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.253.08:05:40.62#ibcon#enter wrdev, iclass 22, count 0 2006.253.08:05:40.62#ibcon#first serial, iclass 22, count 0 2006.253.08:05:40.62#ibcon#enter sib2, iclass 22, count 0 2006.253.08:05:40.62#ibcon#flushed, iclass 22, count 0 2006.253.08:05:40.62#ibcon#about to write, iclass 22, count 0 2006.253.08:05:40.62#ibcon#wrote, iclass 22, count 0 2006.253.08:05:40.62#ibcon#about to read 3, iclass 22, count 0 2006.253.08:05:40.65#ibcon#read 3, iclass 22, count 0 2006.253.08:05:40.65#ibcon#about to read 4, iclass 22, count 0 2006.253.08:05:40.65#ibcon#read 4, iclass 22, count 0 2006.253.08:05:40.65#ibcon#about to read 5, iclass 22, count 0 2006.253.08:05:40.65#ibcon#read 5, iclass 22, count 0 2006.253.08:05:40.65#ibcon#about to read 6, iclass 22, count 0 2006.253.08:05:40.65#ibcon#read 6, iclass 22, count 0 2006.253.08:05:40.65#ibcon#end of sib2, iclass 22, count 0 2006.253.08:05:40.65#ibcon#*mode == 0, iclass 22, count 0 2006.253.08:05:40.65#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.253.08:05:40.65#ibcon#[28=FRQ=01,632.99\r\n] 2006.253.08:05:40.65#ibcon#*before write, iclass 22, count 0 2006.253.08:05:40.65#ibcon#enter sib2, iclass 22, count 0 2006.253.08:05:40.65#ibcon#flushed, iclass 22, count 0 2006.253.08:05:40.65#ibcon#about to write, iclass 22, count 0 2006.253.08:05:40.65#ibcon#wrote, iclass 22, count 0 2006.253.08:05:40.65#ibcon#about to read 3, iclass 22, count 0 2006.253.08:05:40.69#ibcon#read 3, iclass 22, count 0 2006.253.08:05:40.69#ibcon#about to read 4, iclass 22, count 0 2006.253.08:05:40.69#ibcon#read 4, iclass 22, count 0 2006.253.08:05:40.69#ibcon#about to read 5, iclass 22, count 0 2006.253.08:05:40.69#ibcon#read 5, iclass 22, count 0 2006.253.08:05:40.69#ibcon#about to read 6, iclass 22, count 0 2006.253.08:05:40.69#ibcon#read 6, iclass 22, count 0 2006.253.08:05:40.69#ibcon#end of sib2, iclass 22, count 0 2006.253.08:05:40.69#ibcon#*after write, iclass 22, count 0 2006.253.08:05:40.69#ibcon#*before return 0, iclass 22, count 0 2006.253.08:05:40.69#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.253.08:05:40.69#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.253.08:05:40.69#ibcon#about to clear, iclass 22 cls_cnt 0 2006.253.08:05:40.69#ibcon#cleared, iclass 22 cls_cnt 0 2006.253.08:05:40.69$vc4f8/vb=1,4 2006.253.08:05:40.69#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.253.08:05:40.69#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.253.08:05:40.69#ibcon#ireg 11 cls_cnt 2 2006.253.08:05:40.69#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.253.08:05:40.69#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.253.08:05:40.69#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.253.08:05:40.69#ibcon#enter wrdev, iclass 24, count 2 2006.253.08:05:40.69#ibcon#first serial, iclass 24, count 2 2006.253.08:05:40.69#ibcon#enter sib2, iclass 24, count 2 2006.253.08:05:40.69#ibcon#flushed, iclass 24, count 2 2006.253.08:05:40.69#ibcon#about to write, iclass 24, count 2 2006.253.08:05:40.69#ibcon#wrote, iclass 24, count 2 2006.253.08:05:40.69#ibcon#about to read 3, iclass 24, count 2 2006.253.08:05:40.71#ibcon#read 3, iclass 24, count 2 2006.253.08:05:40.71#ibcon#about to read 4, iclass 24, count 2 2006.253.08:05:40.71#ibcon#read 4, iclass 24, count 2 2006.253.08:05:40.71#ibcon#about to read 5, iclass 24, count 2 2006.253.08:05:40.71#ibcon#read 5, iclass 24, count 2 2006.253.08:05:40.71#ibcon#about to read 6, iclass 24, count 2 2006.253.08:05:40.71#ibcon#read 6, iclass 24, count 2 2006.253.08:05:40.71#ibcon#end of sib2, iclass 24, count 2 2006.253.08:05:40.71#ibcon#*mode == 0, iclass 24, count 2 2006.253.08:05:40.71#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.253.08:05:40.71#ibcon#[27=AT01-04\r\n] 2006.253.08:05:40.71#ibcon#*before write, iclass 24, count 2 2006.253.08:05:40.71#ibcon#enter sib2, iclass 24, count 2 2006.253.08:05:40.71#ibcon#flushed, iclass 24, count 2 2006.253.08:05:40.71#ibcon#about to write, iclass 24, count 2 2006.253.08:05:40.71#ibcon#wrote, iclass 24, count 2 2006.253.08:05:40.71#ibcon#about to read 3, iclass 24, count 2 2006.253.08:05:40.74#ibcon#read 3, iclass 24, count 2 2006.253.08:05:40.74#ibcon#about to read 4, iclass 24, count 2 2006.253.08:05:40.74#ibcon#read 4, iclass 24, count 2 2006.253.08:05:40.74#ibcon#about to read 5, iclass 24, count 2 2006.253.08:05:40.74#ibcon#read 5, iclass 24, count 2 2006.253.08:05:40.74#ibcon#about to read 6, iclass 24, count 2 2006.253.08:05:40.74#ibcon#read 6, iclass 24, count 2 2006.253.08:05:40.74#ibcon#end of sib2, iclass 24, count 2 2006.253.08:05:40.74#ibcon#*after write, iclass 24, count 2 2006.253.08:05:40.74#ibcon#*before return 0, iclass 24, count 2 2006.253.08:05:40.74#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.253.08:05:40.74#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.253.08:05:40.74#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.253.08:05:40.74#ibcon#ireg 7 cls_cnt 0 2006.253.08:05:40.74#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.253.08:05:40.86#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.253.08:05:40.86#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.253.08:05:40.86#ibcon#enter wrdev, iclass 24, count 0 2006.253.08:05:40.86#ibcon#first serial, iclass 24, count 0 2006.253.08:05:40.86#ibcon#enter sib2, iclass 24, count 0 2006.253.08:05:40.86#ibcon#flushed, iclass 24, count 0 2006.253.08:05:40.86#ibcon#about to write, iclass 24, count 0 2006.253.08:05:40.86#ibcon#wrote, iclass 24, count 0 2006.253.08:05:40.86#ibcon#about to read 3, iclass 24, count 0 2006.253.08:05:40.88#ibcon#read 3, iclass 24, count 0 2006.253.08:05:40.88#ibcon#about to read 4, iclass 24, count 0 2006.253.08:05:40.88#ibcon#read 4, iclass 24, count 0 2006.253.08:05:40.88#ibcon#about to read 5, iclass 24, count 0 2006.253.08:05:40.88#ibcon#read 5, iclass 24, count 0 2006.253.08:05:40.88#ibcon#about to read 6, iclass 24, count 0 2006.253.08:05:40.88#ibcon#read 6, iclass 24, count 0 2006.253.08:05:40.88#ibcon#end of sib2, iclass 24, count 0 2006.253.08:05:40.88#ibcon#*mode == 0, iclass 24, count 0 2006.253.08:05:40.88#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.253.08:05:40.88#ibcon#[27=USB\r\n] 2006.253.08:05:40.88#ibcon#*before write, iclass 24, count 0 2006.253.08:05:40.88#ibcon#enter sib2, iclass 24, count 0 2006.253.08:05:40.88#ibcon#flushed, iclass 24, count 0 2006.253.08:05:40.88#ibcon#about to write, iclass 24, count 0 2006.253.08:05:40.88#ibcon#wrote, iclass 24, count 0 2006.253.08:05:40.88#ibcon#about to read 3, iclass 24, count 0 2006.253.08:05:40.91#ibcon#read 3, iclass 24, count 0 2006.253.08:05:40.91#ibcon#about to read 4, iclass 24, count 0 2006.253.08:05:40.91#ibcon#read 4, iclass 24, count 0 2006.253.08:05:40.91#ibcon#about to read 5, iclass 24, count 0 2006.253.08:05:40.91#ibcon#read 5, iclass 24, count 0 2006.253.08:05:40.91#ibcon#about to read 6, iclass 24, count 0 2006.253.08:05:40.91#ibcon#read 6, iclass 24, count 0 2006.253.08:05:40.91#ibcon#end of sib2, iclass 24, count 0 2006.253.08:05:40.91#ibcon#*after write, iclass 24, count 0 2006.253.08:05:40.91#ibcon#*before return 0, iclass 24, count 0 2006.253.08:05:40.91#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.253.08:05:40.91#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.253.08:05:40.91#ibcon#about to clear, iclass 24 cls_cnt 0 2006.253.08:05:40.91#ibcon#cleared, iclass 24 cls_cnt 0 2006.253.08:05:40.91$vc4f8/vblo=2,640.99 2006.253.08:05:40.91#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.253.08:05:40.91#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.253.08:05:40.91#ibcon#ireg 17 cls_cnt 0 2006.253.08:05:40.91#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.253.08:05:40.91#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.253.08:05:40.91#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.253.08:05:40.91#ibcon#enter wrdev, iclass 26, count 0 2006.253.08:05:40.91#ibcon#first serial, iclass 26, count 0 2006.253.08:05:40.91#ibcon#enter sib2, iclass 26, count 0 2006.253.08:05:40.91#ibcon#flushed, iclass 26, count 0 2006.253.08:05:40.91#ibcon#about to write, iclass 26, count 0 2006.253.08:05:40.91#ibcon#wrote, iclass 26, count 0 2006.253.08:05:40.91#ibcon#about to read 3, iclass 26, count 0 2006.253.08:05:40.93#ibcon#read 3, iclass 26, count 0 2006.253.08:05:40.93#ibcon#about to read 4, iclass 26, count 0 2006.253.08:05:40.93#ibcon#read 4, iclass 26, count 0 2006.253.08:05:40.93#ibcon#about to read 5, iclass 26, count 0 2006.253.08:05:40.93#ibcon#read 5, iclass 26, count 0 2006.253.08:05:40.93#ibcon#about to read 6, iclass 26, count 0 2006.253.08:05:40.93#ibcon#read 6, iclass 26, count 0 2006.253.08:05:40.93#ibcon#end of sib2, iclass 26, count 0 2006.253.08:05:40.93#ibcon#*mode == 0, iclass 26, count 0 2006.253.08:05:40.93#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.253.08:05:40.93#ibcon#[28=FRQ=02,640.99\r\n] 2006.253.08:05:40.93#ibcon#*before write, iclass 26, count 0 2006.253.08:05:40.93#ibcon#enter sib2, iclass 26, count 0 2006.253.08:05:40.93#ibcon#flushed, iclass 26, count 0 2006.253.08:05:40.93#ibcon#about to write, iclass 26, count 0 2006.253.08:05:40.93#ibcon#wrote, iclass 26, count 0 2006.253.08:05:40.93#ibcon#about to read 3, iclass 26, count 0 2006.253.08:05:40.97#ibcon#read 3, iclass 26, count 0 2006.253.08:05:40.97#ibcon#about to read 4, iclass 26, count 0 2006.253.08:05:40.97#ibcon#read 4, iclass 26, count 0 2006.253.08:05:40.97#ibcon#about to read 5, iclass 26, count 0 2006.253.08:05:40.97#ibcon#read 5, iclass 26, count 0 2006.253.08:05:40.97#ibcon#about to read 6, iclass 26, count 0 2006.253.08:05:40.97#ibcon#read 6, iclass 26, count 0 2006.253.08:05:40.97#ibcon#end of sib2, iclass 26, count 0 2006.253.08:05:40.97#ibcon#*after write, iclass 26, count 0 2006.253.08:05:40.97#ibcon#*before return 0, iclass 26, count 0 2006.253.08:05:40.97#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.253.08:05:40.97#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.253.08:05:40.97#ibcon#about to clear, iclass 26 cls_cnt 0 2006.253.08:05:40.97#ibcon#cleared, iclass 26 cls_cnt 0 2006.253.08:05:40.97$vc4f8/vb=2,5 2006.253.08:05:40.97#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.253.08:05:40.97#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.253.08:05:40.97#ibcon#ireg 11 cls_cnt 2 2006.253.08:05:40.97#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.253.08:05:41.03#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.253.08:05:41.03#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.253.08:05:41.03#ibcon#enter wrdev, iclass 28, count 2 2006.253.08:05:41.03#ibcon#first serial, iclass 28, count 2 2006.253.08:05:41.03#ibcon#enter sib2, iclass 28, count 2 2006.253.08:05:41.03#ibcon#flushed, iclass 28, count 2 2006.253.08:05:41.03#ibcon#about to write, iclass 28, count 2 2006.253.08:05:41.03#ibcon#wrote, iclass 28, count 2 2006.253.08:05:41.03#ibcon#about to read 3, iclass 28, count 2 2006.253.08:05:41.05#ibcon#read 3, iclass 28, count 2 2006.253.08:05:41.05#ibcon#about to read 4, iclass 28, count 2 2006.253.08:05:41.05#ibcon#read 4, iclass 28, count 2 2006.253.08:05:41.05#ibcon#about to read 5, iclass 28, count 2 2006.253.08:05:41.05#ibcon#read 5, iclass 28, count 2 2006.253.08:05:41.05#ibcon#about to read 6, iclass 28, count 2 2006.253.08:05:41.05#ibcon#read 6, iclass 28, count 2 2006.253.08:05:41.05#ibcon#end of sib2, iclass 28, count 2 2006.253.08:05:41.05#ibcon#*mode == 0, iclass 28, count 2 2006.253.08:05:41.05#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.253.08:05:41.05#ibcon#[27=AT02-05\r\n] 2006.253.08:05:41.05#ibcon#*before write, iclass 28, count 2 2006.253.08:05:41.05#ibcon#enter sib2, iclass 28, count 2 2006.253.08:05:41.05#ibcon#flushed, iclass 28, count 2 2006.253.08:05:41.05#ibcon#about to write, iclass 28, count 2 2006.253.08:05:41.05#ibcon#wrote, iclass 28, count 2 2006.253.08:05:41.05#ibcon#about to read 3, iclass 28, count 2 2006.253.08:05:41.08#ibcon#read 3, iclass 28, count 2 2006.253.08:05:41.08#ibcon#about to read 4, iclass 28, count 2 2006.253.08:05:41.08#ibcon#read 4, iclass 28, count 2 2006.253.08:05:41.08#ibcon#about to read 5, iclass 28, count 2 2006.253.08:05:41.08#ibcon#read 5, iclass 28, count 2 2006.253.08:05:41.08#ibcon#about to read 6, iclass 28, count 2 2006.253.08:05:41.08#ibcon#read 6, iclass 28, count 2 2006.253.08:05:41.08#ibcon#end of sib2, iclass 28, count 2 2006.253.08:05:41.08#ibcon#*after write, iclass 28, count 2 2006.253.08:05:41.08#ibcon#*before return 0, iclass 28, count 2 2006.253.08:05:41.08#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.253.08:05:41.08#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.253.08:05:41.08#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.253.08:05:41.08#ibcon#ireg 7 cls_cnt 0 2006.253.08:05:41.08#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.253.08:05:41.20#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.253.08:05:41.20#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.253.08:05:41.20#ibcon#enter wrdev, iclass 28, count 0 2006.253.08:05:41.20#ibcon#first serial, iclass 28, count 0 2006.253.08:05:41.20#ibcon#enter sib2, iclass 28, count 0 2006.253.08:05:41.20#ibcon#flushed, iclass 28, count 0 2006.253.08:05:41.20#ibcon#about to write, iclass 28, count 0 2006.253.08:05:41.20#ibcon#wrote, iclass 28, count 0 2006.253.08:05:41.20#ibcon#about to read 3, iclass 28, count 0 2006.253.08:05:41.22#ibcon#read 3, iclass 28, count 0 2006.253.08:05:41.22#ibcon#about to read 4, iclass 28, count 0 2006.253.08:05:41.22#ibcon#read 4, iclass 28, count 0 2006.253.08:05:41.22#ibcon#about to read 5, iclass 28, count 0 2006.253.08:05:41.22#ibcon#read 5, iclass 28, count 0 2006.253.08:05:41.22#ibcon#about to read 6, iclass 28, count 0 2006.253.08:05:41.22#ibcon#read 6, iclass 28, count 0 2006.253.08:05:41.22#ibcon#end of sib2, iclass 28, count 0 2006.253.08:05:41.22#ibcon#*mode == 0, iclass 28, count 0 2006.253.08:05:41.22#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.253.08:05:41.22#ibcon#[27=USB\r\n] 2006.253.08:05:41.22#ibcon#*before write, iclass 28, count 0 2006.253.08:05:41.22#ibcon#enter sib2, iclass 28, count 0 2006.253.08:05:41.22#ibcon#flushed, iclass 28, count 0 2006.253.08:05:41.22#ibcon#about to write, iclass 28, count 0 2006.253.08:05:41.22#ibcon#wrote, iclass 28, count 0 2006.253.08:05:41.22#ibcon#about to read 3, iclass 28, count 0 2006.253.08:05:41.25#ibcon#read 3, iclass 28, count 0 2006.253.08:05:41.25#ibcon#about to read 4, iclass 28, count 0 2006.253.08:05:41.25#ibcon#read 4, iclass 28, count 0 2006.253.08:05:41.25#ibcon#about to read 5, iclass 28, count 0 2006.253.08:05:41.25#ibcon#read 5, iclass 28, count 0 2006.253.08:05:41.25#ibcon#about to read 6, iclass 28, count 0 2006.253.08:05:41.25#ibcon#read 6, iclass 28, count 0 2006.253.08:05:41.25#ibcon#end of sib2, iclass 28, count 0 2006.253.08:05:41.25#ibcon#*after write, iclass 28, count 0 2006.253.08:05:41.25#ibcon#*before return 0, iclass 28, count 0 2006.253.08:05:41.25#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.253.08:05:41.25#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.253.08:05:41.25#ibcon#about to clear, iclass 28 cls_cnt 0 2006.253.08:05:41.25#ibcon#cleared, iclass 28 cls_cnt 0 2006.253.08:05:41.25$vc4f8/vblo=3,656.99 2006.253.08:05:41.25#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.253.08:05:41.25#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.253.08:05:41.25#ibcon#ireg 17 cls_cnt 0 2006.253.08:05:41.25#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.253.08:05:41.25#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.253.08:05:41.25#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.253.08:05:41.25#ibcon#enter wrdev, iclass 30, count 0 2006.253.08:05:41.25#ibcon#first serial, iclass 30, count 0 2006.253.08:05:41.25#ibcon#enter sib2, iclass 30, count 0 2006.253.08:05:41.25#ibcon#flushed, iclass 30, count 0 2006.253.08:05:41.25#ibcon#about to write, iclass 30, count 0 2006.253.08:05:41.25#ibcon#wrote, iclass 30, count 0 2006.253.08:05:41.25#ibcon#about to read 3, iclass 30, count 0 2006.253.08:05:41.27#ibcon#read 3, iclass 30, count 0 2006.253.08:05:41.27#ibcon#about to read 4, iclass 30, count 0 2006.253.08:05:41.27#ibcon#read 4, iclass 30, count 0 2006.253.08:05:41.27#ibcon#about to read 5, iclass 30, count 0 2006.253.08:05:41.27#ibcon#read 5, iclass 30, count 0 2006.253.08:05:41.27#ibcon#about to read 6, iclass 30, count 0 2006.253.08:05:41.27#ibcon#read 6, iclass 30, count 0 2006.253.08:05:41.27#ibcon#end of sib2, iclass 30, count 0 2006.253.08:05:41.27#ibcon#*mode == 0, iclass 30, count 0 2006.253.08:05:41.27#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.253.08:05:41.27#ibcon#[28=FRQ=03,656.99\r\n] 2006.253.08:05:41.27#ibcon#*before write, iclass 30, count 0 2006.253.08:05:41.27#ibcon#enter sib2, iclass 30, count 0 2006.253.08:05:41.27#ibcon#flushed, iclass 30, count 0 2006.253.08:05:41.27#ibcon#about to write, iclass 30, count 0 2006.253.08:05:41.27#ibcon#wrote, iclass 30, count 0 2006.253.08:05:41.27#ibcon#about to read 3, iclass 30, count 0 2006.253.08:05:41.31#ibcon#read 3, iclass 30, count 0 2006.253.08:05:41.31#ibcon#about to read 4, iclass 30, count 0 2006.253.08:05:41.31#ibcon#read 4, iclass 30, count 0 2006.253.08:05:41.31#ibcon#about to read 5, iclass 30, count 0 2006.253.08:05:41.31#ibcon#read 5, iclass 30, count 0 2006.253.08:05:41.31#ibcon#about to read 6, iclass 30, count 0 2006.253.08:05:41.31#ibcon#read 6, iclass 30, count 0 2006.253.08:05:41.31#ibcon#end of sib2, iclass 30, count 0 2006.253.08:05:41.31#ibcon#*after write, iclass 30, count 0 2006.253.08:05:41.31#ibcon#*before return 0, iclass 30, count 0 2006.253.08:05:41.31#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.253.08:05:41.31#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.253.08:05:41.31#ibcon#about to clear, iclass 30 cls_cnt 0 2006.253.08:05:41.31#ibcon#cleared, iclass 30 cls_cnt 0 2006.253.08:05:41.31$vc4f8/vb=3,4 2006.253.08:05:41.31#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.253.08:05:41.31#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.253.08:05:41.31#ibcon#ireg 11 cls_cnt 2 2006.253.08:05:41.31#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.253.08:05:41.37#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.253.08:05:41.37#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.253.08:05:41.37#ibcon#enter wrdev, iclass 32, count 2 2006.253.08:05:41.37#ibcon#first serial, iclass 32, count 2 2006.253.08:05:41.37#ibcon#enter sib2, iclass 32, count 2 2006.253.08:05:41.37#ibcon#flushed, iclass 32, count 2 2006.253.08:05:41.37#ibcon#about to write, iclass 32, count 2 2006.253.08:05:41.37#ibcon#wrote, iclass 32, count 2 2006.253.08:05:41.37#ibcon#about to read 3, iclass 32, count 2 2006.253.08:05:41.39#ibcon#read 3, iclass 32, count 2 2006.253.08:05:41.39#ibcon#about to read 4, iclass 32, count 2 2006.253.08:05:41.39#ibcon#read 4, iclass 32, count 2 2006.253.08:05:41.39#ibcon#about to read 5, iclass 32, count 2 2006.253.08:05:41.39#ibcon#read 5, iclass 32, count 2 2006.253.08:05:41.39#ibcon#about to read 6, iclass 32, count 2 2006.253.08:05:41.39#ibcon#read 6, iclass 32, count 2 2006.253.08:05:41.39#ibcon#end of sib2, iclass 32, count 2 2006.253.08:05:41.39#ibcon#*mode == 0, iclass 32, count 2 2006.253.08:05:41.39#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.253.08:05:41.39#ibcon#[27=AT03-04\r\n] 2006.253.08:05:41.39#ibcon#*before write, iclass 32, count 2 2006.253.08:05:41.39#ibcon#enter sib2, iclass 32, count 2 2006.253.08:05:41.39#ibcon#flushed, iclass 32, count 2 2006.253.08:05:41.39#ibcon#about to write, iclass 32, count 2 2006.253.08:05:41.39#ibcon#wrote, iclass 32, count 2 2006.253.08:05:41.39#ibcon#about to read 3, iclass 32, count 2 2006.253.08:05:41.42#ibcon#read 3, iclass 32, count 2 2006.253.08:05:41.42#ibcon#about to read 4, iclass 32, count 2 2006.253.08:05:41.42#ibcon#read 4, iclass 32, count 2 2006.253.08:05:41.42#ibcon#about to read 5, iclass 32, count 2 2006.253.08:05:41.42#ibcon#read 5, iclass 32, count 2 2006.253.08:05:41.42#ibcon#about to read 6, iclass 32, count 2 2006.253.08:05:41.42#ibcon#read 6, iclass 32, count 2 2006.253.08:05:41.42#ibcon#end of sib2, iclass 32, count 2 2006.253.08:05:41.42#ibcon#*after write, iclass 32, count 2 2006.253.08:05:41.42#ibcon#*before return 0, iclass 32, count 2 2006.253.08:05:41.42#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.253.08:05:41.42#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.253.08:05:41.42#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.253.08:05:41.42#ibcon#ireg 7 cls_cnt 0 2006.253.08:05:41.42#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.253.08:05:41.54#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.253.08:05:41.54#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.253.08:05:41.54#ibcon#enter wrdev, iclass 32, count 0 2006.253.08:05:41.54#ibcon#first serial, iclass 32, count 0 2006.253.08:05:41.54#ibcon#enter sib2, iclass 32, count 0 2006.253.08:05:41.54#ibcon#flushed, iclass 32, count 0 2006.253.08:05:41.54#ibcon#about to write, iclass 32, count 0 2006.253.08:05:41.54#ibcon#wrote, iclass 32, count 0 2006.253.08:05:41.54#ibcon#about to read 3, iclass 32, count 0 2006.253.08:05:41.56#ibcon#read 3, iclass 32, count 0 2006.253.08:05:41.56#ibcon#about to read 4, iclass 32, count 0 2006.253.08:05:41.56#ibcon#read 4, iclass 32, count 0 2006.253.08:05:41.56#ibcon#about to read 5, iclass 32, count 0 2006.253.08:05:41.56#ibcon#read 5, iclass 32, count 0 2006.253.08:05:41.56#ibcon#about to read 6, iclass 32, count 0 2006.253.08:05:41.56#ibcon#read 6, iclass 32, count 0 2006.253.08:05:41.56#ibcon#end of sib2, iclass 32, count 0 2006.253.08:05:41.56#ibcon#*mode == 0, iclass 32, count 0 2006.253.08:05:41.56#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.253.08:05:41.56#ibcon#[27=USB\r\n] 2006.253.08:05:41.56#ibcon#*before write, iclass 32, count 0 2006.253.08:05:41.56#ibcon#enter sib2, iclass 32, count 0 2006.253.08:05:41.56#ibcon#flushed, iclass 32, count 0 2006.253.08:05:41.56#ibcon#about to write, iclass 32, count 0 2006.253.08:05:41.56#ibcon#wrote, iclass 32, count 0 2006.253.08:05:41.56#ibcon#about to read 3, iclass 32, count 0 2006.253.08:05:41.59#ibcon#read 3, iclass 32, count 0 2006.253.08:05:41.59#ibcon#about to read 4, iclass 32, count 0 2006.253.08:05:41.59#ibcon#read 4, iclass 32, count 0 2006.253.08:05:41.59#ibcon#about to read 5, iclass 32, count 0 2006.253.08:05:41.59#ibcon#read 5, iclass 32, count 0 2006.253.08:05:41.59#ibcon#about to read 6, iclass 32, count 0 2006.253.08:05:41.59#ibcon#read 6, iclass 32, count 0 2006.253.08:05:41.59#ibcon#end of sib2, iclass 32, count 0 2006.253.08:05:41.59#ibcon#*after write, iclass 32, count 0 2006.253.08:05:41.59#ibcon#*before return 0, iclass 32, count 0 2006.253.08:05:41.59#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.253.08:05:41.59#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.253.08:05:41.59#ibcon#about to clear, iclass 32 cls_cnt 0 2006.253.08:05:41.59#ibcon#cleared, iclass 32 cls_cnt 0 2006.253.08:05:41.59$vc4f8/vblo=4,712.99 2006.253.08:05:41.59#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.253.08:05:41.59#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.253.08:05:41.59#ibcon#ireg 17 cls_cnt 0 2006.253.08:05:41.59#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.253.08:05:41.59#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.253.08:05:41.59#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.253.08:05:41.59#ibcon#enter wrdev, iclass 34, count 0 2006.253.08:05:41.59#ibcon#first serial, iclass 34, count 0 2006.253.08:05:41.59#ibcon#enter sib2, iclass 34, count 0 2006.253.08:05:41.59#ibcon#flushed, iclass 34, count 0 2006.253.08:05:41.59#ibcon#about to write, iclass 34, count 0 2006.253.08:05:41.59#ibcon#wrote, iclass 34, count 0 2006.253.08:05:41.59#ibcon#about to read 3, iclass 34, count 0 2006.253.08:05:41.61#ibcon#read 3, iclass 34, count 0 2006.253.08:05:41.61#ibcon#about to read 4, iclass 34, count 0 2006.253.08:05:41.61#ibcon#read 4, iclass 34, count 0 2006.253.08:05:41.61#ibcon#about to read 5, iclass 34, count 0 2006.253.08:05:41.61#ibcon#read 5, iclass 34, count 0 2006.253.08:05:41.61#ibcon#about to read 6, iclass 34, count 0 2006.253.08:05:41.61#ibcon#read 6, iclass 34, count 0 2006.253.08:05:41.61#ibcon#end of sib2, iclass 34, count 0 2006.253.08:05:41.61#ibcon#*mode == 0, iclass 34, count 0 2006.253.08:05:41.61#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.253.08:05:41.61#ibcon#[28=FRQ=04,712.99\r\n] 2006.253.08:05:41.61#ibcon#*before write, iclass 34, count 0 2006.253.08:05:41.61#ibcon#enter sib2, iclass 34, count 0 2006.253.08:05:41.61#ibcon#flushed, iclass 34, count 0 2006.253.08:05:41.61#ibcon#about to write, iclass 34, count 0 2006.253.08:05:41.61#ibcon#wrote, iclass 34, count 0 2006.253.08:05:41.61#ibcon#about to read 3, iclass 34, count 0 2006.253.08:05:41.65#ibcon#read 3, iclass 34, count 0 2006.253.08:05:41.65#ibcon#about to read 4, iclass 34, count 0 2006.253.08:05:41.65#ibcon#read 4, iclass 34, count 0 2006.253.08:05:41.65#ibcon#about to read 5, iclass 34, count 0 2006.253.08:05:41.65#ibcon#read 5, iclass 34, count 0 2006.253.08:05:41.65#ibcon#about to read 6, iclass 34, count 0 2006.253.08:05:41.65#ibcon#read 6, iclass 34, count 0 2006.253.08:05:41.65#ibcon#end of sib2, iclass 34, count 0 2006.253.08:05:41.65#ibcon#*after write, iclass 34, count 0 2006.253.08:05:41.65#ibcon#*before return 0, iclass 34, count 0 2006.253.08:05:41.65#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.253.08:05:41.65#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.253.08:05:41.65#ibcon#about to clear, iclass 34 cls_cnt 0 2006.253.08:05:41.65#ibcon#cleared, iclass 34 cls_cnt 0 2006.253.08:05:41.65$vc4f8/vb=4,4 2006.253.08:05:41.65#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.253.08:05:41.65#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.253.08:05:41.65#ibcon#ireg 11 cls_cnt 2 2006.253.08:05:41.65#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.253.08:05:41.71#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.253.08:05:41.71#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.253.08:05:41.71#ibcon#enter wrdev, iclass 36, count 2 2006.253.08:05:41.71#ibcon#first serial, iclass 36, count 2 2006.253.08:05:41.71#ibcon#enter sib2, iclass 36, count 2 2006.253.08:05:41.71#ibcon#flushed, iclass 36, count 2 2006.253.08:05:41.71#ibcon#about to write, iclass 36, count 2 2006.253.08:05:41.71#ibcon#wrote, iclass 36, count 2 2006.253.08:05:41.71#ibcon#about to read 3, iclass 36, count 2 2006.253.08:05:41.73#ibcon#read 3, iclass 36, count 2 2006.253.08:05:41.73#ibcon#about to read 4, iclass 36, count 2 2006.253.08:05:41.73#ibcon#read 4, iclass 36, count 2 2006.253.08:05:41.73#ibcon#about to read 5, iclass 36, count 2 2006.253.08:05:41.73#ibcon#read 5, iclass 36, count 2 2006.253.08:05:41.73#ibcon#about to read 6, iclass 36, count 2 2006.253.08:05:41.73#ibcon#read 6, iclass 36, count 2 2006.253.08:05:41.73#ibcon#end of sib2, iclass 36, count 2 2006.253.08:05:41.73#ibcon#*mode == 0, iclass 36, count 2 2006.253.08:05:41.73#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.253.08:05:41.73#ibcon#[27=AT04-04\r\n] 2006.253.08:05:41.73#ibcon#*before write, iclass 36, count 2 2006.253.08:05:41.73#ibcon#enter sib2, iclass 36, count 2 2006.253.08:05:41.73#ibcon#flushed, iclass 36, count 2 2006.253.08:05:41.73#ibcon#about to write, iclass 36, count 2 2006.253.08:05:41.73#ibcon#wrote, iclass 36, count 2 2006.253.08:05:41.73#ibcon#about to read 3, iclass 36, count 2 2006.253.08:05:41.76#ibcon#read 3, iclass 36, count 2 2006.253.08:05:41.76#ibcon#about to read 4, iclass 36, count 2 2006.253.08:05:41.76#ibcon#read 4, iclass 36, count 2 2006.253.08:05:41.76#ibcon#about to read 5, iclass 36, count 2 2006.253.08:05:41.76#ibcon#read 5, iclass 36, count 2 2006.253.08:05:41.76#ibcon#about to read 6, iclass 36, count 2 2006.253.08:05:41.76#ibcon#read 6, iclass 36, count 2 2006.253.08:05:41.76#ibcon#end of sib2, iclass 36, count 2 2006.253.08:05:41.76#ibcon#*after write, iclass 36, count 2 2006.253.08:05:41.76#ibcon#*before return 0, iclass 36, count 2 2006.253.08:05:41.76#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.253.08:05:41.76#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.253.08:05:41.76#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.253.08:05:41.76#ibcon#ireg 7 cls_cnt 0 2006.253.08:05:41.76#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.253.08:05:41.88#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.253.08:05:41.88#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.253.08:05:41.88#ibcon#enter wrdev, iclass 36, count 0 2006.253.08:05:41.88#ibcon#first serial, iclass 36, count 0 2006.253.08:05:41.88#ibcon#enter sib2, iclass 36, count 0 2006.253.08:05:41.88#ibcon#flushed, iclass 36, count 0 2006.253.08:05:41.88#ibcon#about to write, iclass 36, count 0 2006.253.08:05:41.88#ibcon#wrote, iclass 36, count 0 2006.253.08:05:41.88#ibcon#about to read 3, iclass 36, count 0 2006.253.08:05:41.90#ibcon#read 3, iclass 36, count 0 2006.253.08:05:41.90#ibcon#about to read 4, iclass 36, count 0 2006.253.08:05:41.90#ibcon#read 4, iclass 36, count 0 2006.253.08:05:41.90#ibcon#about to read 5, iclass 36, count 0 2006.253.08:05:41.90#ibcon#read 5, iclass 36, count 0 2006.253.08:05:41.90#ibcon#about to read 6, iclass 36, count 0 2006.253.08:05:41.90#ibcon#read 6, iclass 36, count 0 2006.253.08:05:41.90#ibcon#end of sib2, iclass 36, count 0 2006.253.08:05:41.90#ibcon#*mode == 0, iclass 36, count 0 2006.253.08:05:41.90#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.253.08:05:41.90#ibcon#[27=USB\r\n] 2006.253.08:05:41.90#ibcon#*before write, iclass 36, count 0 2006.253.08:05:41.90#ibcon#enter sib2, iclass 36, count 0 2006.253.08:05:41.90#ibcon#flushed, iclass 36, count 0 2006.253.08:05:41.90#ibcon#about to write, iclass 36, count 0 2006.253.08:05:41.90#ibcon#wrote, iclass 36, count 0 2006.253.08:05:41.90#ibcon#about to read 3, iclass 36, count 0 2006.253.08:05:41.93#ibcon#read 3, iclass 36, count 0 2006.253.08:05:41.93#ibcon#about to read 4, iclass 36, count 0 2006.253.08:05:41.93#ibcon#read 4, iclass 36, count 0 2006.253.08:05:41.93#ibcon#about to read 5, iclass 36, count 0 2006.253.08:05:41.93#ibcon#read 5, iclass 36, count 0 2006.253.08:05:41.93#ibcon#about to read 6, iclass 36, count 0 2006.253.08:05:41.93#ibcon#read 6, iclass 36, count 0 2006.253.08:05:41.93#ibcon#end of sib2, iclass 36, count 0 2006.253.08:05:41.93#ibcon#*after write, iclass 36, count 0 2006.253.08:05:41.93#ibcon#*before return 0, iclass 36, count 0 2006.253.08:05:41.93#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.253.08:05:41.93#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.253.08:05:41.93#ibcon#about to clear, iclass 36 cls_cnt 0 2006.253.08:05:41.93#ibcon#cleared, iclass 36 cls_cnt 0 2006.253.08:05:41.93$vc4f8/vblo=5,744.99 2006.253.08:05:41.93#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.253.08:05:41.93#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.253.08:05:41.93#ibcon#ireg 17 cls_cnt 0 2006.253.08:05:41.93#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.253.08:05:41.93#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.253.08:05:41.93#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.253.08:05:41.93#ibcon#enter wrdev, iclass 38, count 0 2006.253.08:05:41.93#ibcon#first serial, iclass 38, count 0 2006.253.08:05:41.93#ibcon#enter sib2, iclass 38, count 0 2006.253.08:05:41.93#ibcon#flushed, iclass 38, count 0 2006.253.08:05:41.93#ibcon#about to write, iclass 38, count 0 2006.253.08:05:41.93#ibcon#wrote, iclass 38, count 0 2006.253.08:05:41.93#ibcon#about to read 3, iclass 38, count 0 2006.253.08:05:41.95#ibcon#read 3, iclass 38, count 0 2006.253.08:05:41.95#ibcon#about to read 4, iclass 38, count 0 2006.253.08:05:41.95#ibcon#read 4, iclass 38, count 0 2006.253.08:05:41.95#ibcon#about to read 5, iclass 38, count 0 2006.253.08:05:41.95#ibcon#read 5, iclass 38, count 0 2006.253.08:05:41.95#ibcon#about to read 6, iclass 38, count 0 2006.253.08:05:41.95#ibcon#read 6, iclass 38, count 0 2006.253.08:05:41.95#ibcon#end of sib2, iclass 38, count 0 2006.253.08:05:41.95#ibcon#*mode == 0, iclass 38, count 0 2006.253.08:05:41.95#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.253.08:05:41.95#ibcon#[28=FRQ=05,744.99\r\n] 2006.253.08:05:41.95#ibcon#*before write, iclass 38, count 0 2006.253.08:05:41.95#ibcon#enter sib2, iclass 38, count 0 2006.253.08:05:41.95#ibcon#flushed, iclass 38, count 0 2006.253.08:05:41.95#ibcon#about to write, iclass 38, count 0 2006.253.08:05:41.95#ibcon#wrote, iclass 38, count 0 2006.253.08:05:41.95#ibcon#about to read 3, iclass 38, count 0 2006.253.08:05:41.99#ibcon#read 3, iclass 38, count 0 2006.253.08:05:41.99#ibcon#about to read 4, iclass 38, count 0 2006.253.08:05:41.99#ibcon#read 4, iclass 38, count 0 2006.253.08:05:41.99#ibcon#about to read 5, iclass 38, count 0 2006.253.08:05:41.99#ibcon#read 5, iclass 38, count 0 2006.253.08:05:41.99#ibcon#about to read 6, iclass 38, count 0 2006.253.08:05:41.99#ibcon#read 6, iclass 38, count 0 2006.253.08:05:41.99#ibcon#end of sib2, iclass 38, count 0 2006.253.08:05:41.99#ibcon#*after write, iclass 38, count 0 2006.253.08:05:41.99#ibcon#*before return 0, iclass 38, count 0 2006.253.08:05:41.99#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.253.08:05:41.99#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.253.08:05:41.99#ibcon#about to clear, iclass 38 cls_cnt 0 2006.253.08:05:41.99#ibcon#cleared, iclass 38 cls_cnt 0 2006.253.08:05:41.99$vc4f8/vb=5,4 2006.253.08:05:41.99#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.253.08:05:41.99#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.253.08:05:41.99#ibcon#ireg 11 cls_cnt 2 2006.253.08:05:41.99#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.253.08:05:42.05#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.253.08:05:42.05#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.253.08:05:42.05#ibcon#enter wrdev, iclass 40, count 2 2006.253.08:05:42.05#ibcon#first serial, iclass 40, count 2 2006.253.08:05:42.05#ibcon#enter sib2, iclass 40, count 2 2006.253.08:05:42.05#ibcon#flushed, iclass 40, count 2 2006.253.08:05:42.05#ibcon#about to write, iclass 40, count 2 2006.253.08:05:42.05#ibcon#wrote, iclass 40, count 2 2006.253.08:05:42.05#ibcon#about to read 3, iclass 40, count 2 2006.253.08:05:42.07#ibcon#read 3, iclass 40, count 2 2006.253.08:05:42.07#ibcon#about to read 4, iclass 40, count 2 2006.253.08:05:42.07#ibcon#read 4, iclass 40, count 2 2006.253.08:05:42.07#ibcon#about to read 5, iclass 40, count 2 2006.253.08:05:42.07#ibcon#read 5, iclass 40, count 2 2006.253.08:05:42.07#ibcon#about to read 6, iclass 40, count 2 2006.253.08:05:42.07#ibcon#read 6, iclass 40, count 2 2006.253.08:05:42.07#ibcon#end of sib2, iclass 40, count 2 2006.253.08:05:42.07#ibcon#*mode == 0, iclass 40, count 2 2006.253.08:05:42.07#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.253.08:05:42.07#ibcon#[27=AT05-04\r\n] 2006.253.08:05:42.07#ibcon#*before write, iclass 40, count 2 2006.253.08:05:42.07#ibcon#enter sib2, iclass 40, count 2 2006.253.08:05:42.07#ibcon#flushed, iclass 40, count 2 2006.253.08:05:42.07#ibcon#about to write, iclass 40, count 2 2006.253.08:05:42.07#ibcon#wrote, iclass 40, count 2 2006.253.08:05:42.07#ibcon#about to read 3, iclass 40, count 2 2006.253.08:05:42.10#ibcon#read 3, iclass 40, count 2 2006.253.08:05:42.10#ibcon#about to read 4, iclass 40, count 2 2006.253.08:05:42.10#ibcon#read 4, iclass 40, count 2 2006.253.08:05:42.10#ibcon#about to read 5, iclass 40, count 2 2006.253.08:05:42.10#ibcon#read 5, iclass 40, count 2 2006.253.08:05:42.10#ibcon#about to read 6, iclass 40, count 2 2006.253.08:05:42.10#ibcon#read 6, iclass 40, count 2 2006.253.08:05:42.10#ibcon#end of sib2, iclass 40, count 2 2006.253.08:05:42.10#ibcon#*after write, iclass 40, count 2 2006.253.08:05:42.10#ibcon#*before return 0, iclass 40, count 2 2006.253.08:05:42.10#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.253.08:05:42.10#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.253.08:05:42.10#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.253.08:05:42.10#ibcon#ireg 7 cls_cnt 0 2006.253.08:05:42.10#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.253.08:05:42.22#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.253.08:05:42.22#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.253.08:05:42.22#ibcon#enter wrdev, iclass 40, count 0 2006.253.08:05:42.22#ibcon#first serial, iclass 40, count 0 2006.253.08:05:42.22#ibcon#enter sib2, iclass 40, count 0 2006.253.08:05:42.22#ibcon#flushed, iclass 40, count 0 2006.253.08:05:42.22#ibcon#about to write, iclass 40, count 0 2006.253.08:05:42.22#ibcon#wrote, iclass 40, count 0 2006.253.08:05:42.22#ibcon#about to read 3, iclass 40, count 0 2006.253.08:05:42.25#ibcon#read 3, iclass 40, count 0 2006.253.08:05:42.25#ibcon#about to read 4, iclass 40, count 0 2006.253.08:05:42.25#ibcon#read 4, iclass 40, count 0 2006.253.08:05:42.25#ibcon#about to read 5, iclass 40, count 0 2006.253.08:05:42.25#ibcon#read 5, iclass 40, count 0 2006.253.08:05:42.26#ibcon#about to read 6, iclass 40, count 0 2006.253.08:05:42.26#ibcon#read 6, iclass 40, count 0 2006.253.08:05:42.26#ibcon#end of sib2, iclass 40, count 0 2006.253.08:05:42.26#ibcon#*mode == 0, iclass 40, count 0 2006.253.08:05:42.26#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.253.08:05:42.26#ibcon#[27=USB\r\n] 2006.253.08:05:42.26#ibcon#*before write, iclass 40, count 0 2006.253.08:05:42.26#ibcon#enter sib2, iclass 40, count 0 2006.253.08:05:42.26#ibcon#flushed, iclass 40, count 0 2006.253.08:05:42.26#ibcon#about to write, iclass 40, count 0 2006.253.08:05:42.26#ibcon#wrote, iclass 40, count 0 2006.253.08:05:42.26#ibcon#about to read 3, iclass 40, count 0 2006.253.08:05:42.28#ibcon#read 3, iclass 40, count 0 2006.253.08:05:42.28#ibcon#about to read 4, iclass 40, count 0 2006.253.08:05:42.28#ibcon#read 4, iclass 40, count 0 2006.253.08:05:42.28#ibcon#about to read 5, iclass 40, count 0 2006.253.08:05:42.28#ibcon#read 5, iclass 40, count 0 2006.253.08:05:42.28#ibcon#about to read 6, iclass 40, count 0 2006.253.08:05:42.28#ibcon#read 6, iclass 40, count 0 2006.253.08:05:42.28#ibcon#end of sib2, iclass 40, count 0 2006.253.08:05:42.28#ibcon#*after write, iclass 40, count 0 2006.253.08:05:42.28#ibcon#*before return 0, iclass 40, count 0 2006.253.08:05:42.28#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.253.08:05:42.28#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.253.08:05:42.28#ibcon#about to clear, iclass 40 cls_cnt 0 2006.253.08:05:42.28#ibcon#cleared, iclass 40 cls_cnt 0 2006.253.08:05:42.28$vc4f8/vblo=6,752.99 2006.253.08:05:42.28#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.253.08:05:42.28#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.253.08:05:42.28#ibcon#ireg 17 cls_cnt 0 2006.253.08:05:42.28#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.253.08:05:42.28#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.253.08:05:42.28#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.253.08:05:42.28#ibcon#enter wrdev, iclass 4, count 0 2006.253.08:05:42.28#ibcon#first serial, iclass 4, count 0 2006.253.08:05:42.28#ibcon#enter sib2, iclass 4, count 0 2006.253.08:05:42.28#ibcon#flushed, iclass 4, count 0 2006.253.08:05:42.28#ibcon#about to write, iclass 4, count 0 2006.253.08:05:42.28#ibcon#wrote, iclass 4, count 0 2006.253.08:05:42.28#ibcon#about to read 3, iclass 4, count 0 2006.253.08:05:42.30#ibcon#read 3, iclass 4, count 0 2006.253.08:05:42.30#ibcon#about to read 4, iclass 4, count 0 2006.253.08:05:42.30#ibcon#read 4, iclass 4, count 0 2006.253.08:05:42.30#ibcon#about to read 5, iclass 4, count 0 2006.253.08:05:42.30#ibcon#read 5, iclass 4, count 0 2006.253.08:05:42.30#ibcon#about to read 6, iclass 4, count 0 2006.253.08:05:42.30#ibcon#read 6, iclass 4, count 0 2006.253.08:05:42.30#ibcon#end of sib2, iclass 4, count 0 2006.253.08:05:42.30#ibcon#*mode == 0, iclass 4, count 0 2006.253.08:05:42.30#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.253.08:05:42.30#ibcon#[28=FRQ=06,752.99\r\n] 2006.253.08:05:42.30#ibcon#*before write, iclass 4, count 0 2006.253.08:05:42.30#ibcon#enter sib2, iclass 4, count 0 2006.253.08:05:42.30#ibcon#flushed, iclass 4, count 0 2006.253.08:05:42.30#ibcon#about to write, iclass 4, count 0 2006.253.08:05:42.30#ibcon#wrote, iclass 4, count 0 2006.253.08:05:42.30#ibcon#about to read 3, iclass 4, count 0 2006.253.08:05:42.34#ibcon#read 3, iclass 4, count 0 2006.253.08:05:42.34#ibcon#about to read 4, iclass 4, count 0 2006.253.08:05:42.34#ibcon#read 4, iclass 4, count 0 2006.253.08:05:42.34#ibcon#about to read 5, iclass 4, count 0 2006.253.08:05:42.34#ibcon#read 5, iclass 4, count 0 2006.253.08:05:42.34#ibcon#about to read 6, iclass 4, count 0 2006.253.08:05:42.34#ibcon#read 6, iclass 4, count 0 2006.253.08:05:42.34#ibcon#end of sib2, iclass 4, count 0 2006.253.08:05:42.34#ibcon#*after write, iclass 4, count 0 2006.253.08:05:42.34#ibcon#*before return 0, iclass 4, count 0 2006.253.08:05:42.34#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.253.08:05:42.34#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.253.08:05:42.34#ibcon#about to clear, iclass 4 cls_cnt 0 2006.253.08:05:42.34#ibcon#cleared, iclass 4 cls_cnt 0 2006.253.08:05:42.34$vc4f8/vb=6,4 2006.253.08:05:42.34#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.253.08:05:42.34#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.253.08:05:42.34#ibcon#ireg 11 cls_cnt 2 2006.253.08:05:42.34#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.253.08:05:42.40#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.253.08:05:42.40#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.253.08:05:42.40#ibcon#enter wrdev, iclass 6, count 2 2006.253.08:05:42.40#ibcon#first serial, iclass 6, count 2 2006.253.08:05:42.40#ibcon#enter sib2, iclass 6, count 2 2006.253.08:05:42.40#ibcon#flushed, iclass 6, count 2 2006.253.08:05:42.40#ibcon#about to write, iclass 6, count 2 2006.253.08:05:42.40#ibcon#wrote, iclass 6, count 2 2006.253.08:05:42.40#ibcon#about to read 3, iclass 6, count 2 2006.253.08:05:42.42#ibcon#read 3, iclass 6, count 2 2006.253.08:05:42.42#ibcon#about to read 4, iclass 6, count 2 2006.253.08:05:42.42#ibcon#read 4, iclass 6, count 2 2006.253.08:05:42.42#ibcon#about to read 5, iclass 6, count 2 2006.253.08:05:42.42#ibcon#read 5, iclass 6, count 2 2006.253.08:05:42.42#ibcon#about to read 6, iclass 6, count 2 2006.253.08:05:42.42#ibcon#read 6, iclass 6, count 2 2006.253.08:05:42.42#ibcon#end of sib2, iclass 6, count 2 2006.253.08:05:42.42#ibcon#*mode == 0, iclass 6, count 2 2006.253.08:05:42.42#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.253.08:05:42.42#ibcon#[27=AT06-04\r\n] 2006.253.08:05:42.42#ibcon#*before write, iclass 6, count 2 2006.253.08:05:42.42#ibcon#enter sib2, iclass 6, count 2 2006.253.08:05:42.42#ibcon#flushed, iclass 6, count 2 2006.253.08:05:42.42#ibcon#about to write, iclass 6, count 2 2006.253.08:05:42.42#ibcon#wrote, iclass 6, count 2 2006.253.08:05:42.42#ibcon#about to read 3, iclass 6, count 2 2006.253.08:05:42.45#ibcon#read 3, iclass 6, count 2 2006.253.08:05:42.45#ibcon#about to read 4, iclass 6, count 2 2006.253.08:05:42.45#ibcon#read 4, iclass 6, count 2 2006.253.08:05:42.45#ibcon#about to read 5, iclass 6, count 2 2006.253.08:05:42.45#ibcon#read 5, iclass 6, count 2 2006.253.08:05:42.45#ibcon#about to read 6, iclass 6, count 2 2006.253.08:05:42.45#ibcon#read 6, iclass 6, count 2 2006.253.08:05:42.45#ibcon#end of sib2, iclass 6, count 2 2006.253.08:05:42.45#ibcon#*after write, iclass 6, count 2 2006.253.08:05:42.45#ibcon#*before return 0, iclass 6, count 2 2006.253.08:05:42.45#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.253.08:05:42.45#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.253.08:05:42.45#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.253.08:05:42.45#ibcon#ireg 7 cls_cnt 0 2006.253.08:05:42.45#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.253.08:05:42.57#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.253.08:05:42.57#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.253.08:05:42.57#ibcon#enter wrdev, iclass 6, count 0 2006.253.08:05:42.57#ibcon#first serial, iclass 6, count 0 2006.253.08:05:42.57#ibcon#enter sib2, iclass 6, count 0 2006.253.08:05:42.57#ibcon#flushed, iclass 6, count 0 2006.253.08:05:42.57#ibcon#about to write, iclass 6, count 0 2006.253.08:05:42.57#ibcon#wrote, iclass 6, count 0 2006.253.08:05:42.57#ibcon#about to read 3, iclass 6, count 0 2006.253.08:05:42.59#ibcon#read 3, iclass 6, count 0 2006.253.08:05:42.59#ibcon#about to read 4, iclass 6, count 0 2006.253.08:05:42.59#ibcon#read 4, iclass 6, count 0 2006.253.08:05:42.59#ibcon#about to read 5, iclass 6, count 0 2006.253.08:05:42.59#ibcon#read 5, iclass 6, count 0 2006.253.08:05:42.59#ibcon#about to read 6, iclass 6, count 0 2006.253.08:05:42.59#ibcon#read 6, iclass 6, count 0 2006.253.08:05:42.59#ibcon#end of sib2, iclass 6, count 0 2006.253.08:05:42.59#ibcon#*mode == 0, iclass 6, count 0 2006.253.08:05:42.59#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.253.08:05:42.59#ibcon#[27=USB\r\n] 2006.253.08:05:42.59#ibcon#*before write, iclass 6, count 0 2006.253.08:05:42.59#ibcon#enter sib2, iclass 6, count 0 2006.253.08:05:42.59#ibcon#flushed, iclass 6, count 0 2006.253.08:05:42.59#ibcon#about to write, iclass 6, count 0 2006.253.08:05:42.59#ibcon#wrote, iclass 6, count 0 2006.253.08:05:42.59#ibcon#about to read 3, iclass 6, count 0 2006.253.08:05:42.62#ibcon#read 3, iclass 6, count 0 2006.253.08:05:42.62#ibcon#about to read 4, iclass 6, count 0 2006.253.08:05:42.62#ibcon#read 4, iclass 6, count 0 2006.253.08:05:42.62#ibcon#about to read 5, iclass 6, count 0 2006.253.08:05:42.62#ibcon#read 5, iclass 6, count 0 2006.253.08:05:42.62#ibcon#about to read 6, iclass 6, count 0 2006.253.08:05:42.62#ibcon#read 6, iclass 6, count 0 2006.253.08:05:42.62#ibcon#end of sib2, iclass 6, count 0 2006.253.08:05:42.62#ibcon#*after write, iclass 6, count 0 2006.253.08:05:42.62#ibcon#*before return 0, iclass 6, count 0 2006.253.08:05:42.62#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.253.08:05:42.62#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.253.08:05:42.62#ibcon#about to clear, iclass 6 cls_cnt 0 2006.253.08:05:42.62#ibcon#cleared, iclass 6 cls_cnt 0 2006.253.08:05:42.62$vc4f8/vabw=wide 2006.253.08:05:42.62#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.253.08:05:42.62#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.253.08:05:42.62#ibcon#ireg 8 cls_cnt 0 2006.253.08:05:42.62#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.253.08:05:42.62#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.253.08:05:42.62#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.253.08:05:42.62#ibcon#enter wrdev, iclass 10, count 0 2006.253.08:05:42.62#ibcon#first serial, iclass 10, count 0 2006.253.08:05:42.62#ibcon#enter sib2, iclass 10, count 0 2006.253.08:05:42.62#ibcon#flushed, iclass 10, count 0 2006.253.08:05:42.62#ibcon#about to write, iclass 10, count 0 2006.253.08:05:42.62#ibcon#wrote, iclass 10, count 0 2006.253.08:05:42.62#ibcon#about to read 3, iclass 10, count 0 2006.253.08:05:42.64#ibcon#read 3, iclass 10, count 0 2006.253.08:05:42.64#ibcon#about to read 4, iclass 10, count 0 2006.253.08:05:42.64#ibcon#read 4, iclass 10, count 0 2006.253.08:05:42.64#ibcon#about to read 5, iclass 10, count 0 2006.253.08:05:42.64#ibcon#read 5, iclass 10, count 0 2006.253.08:05:42.64#ibcon#about to read 6, iclass 10, count 0 2006.253.08:05:42.64#ibcon#read 6, iclass 10, count 0 2006.253.08:05:42.64#ibcon#end of sib2, iclass 10, count 0 2006.253.08:05:42.64#ibcon#*mode == 0, iclass 10, count 0 2006.253.08:05:42.64#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.253.08:05:42.64#ibcon#[25=BW32\r\n] 2006.253.08:05:42.64#ibcon#*before write, iclass 10, count 0 2006.253.08:05:42.64#ibcon#enter sib2, iclass 10, count 0 2006.253.08:05:42.64#ibcon#flushed, iclass 10, count 0 2006.253.08:05:42.64#ibcon#about to write, iclass 10, count 0 2006.253.08:05:42.64#ibcon#wrote, iclass 10, count 0 2006.253.08:05:42.64#ibcon#about to read 3, iclass 10, count 0 2006.253.08:05:42.67#ibcon#read 3, iclass 10, count 0 2006.253.08:05:42.67#ibcon#about to read 4, iclass 10, count 0 2006.253.08:05:42.67#ibcon#read 4, iclass 10, count 0 2006.253.08:05:42.67#ibcon#about to read 5, iclass 10, count 0 2006.253.08:05:42.67#ibcon#read 5, iclass 10, count 0 2006.253.08:05:42.67#ibcon#about to read 6, iclass 10, count 0 2006.253.08:05:42.67#ibcon#read 6, iclass 10, count 0 2006.253.08:05:42.67#ibcon#end of sib2, iclass 10, count 0 2006.253.08:05:42.67#ibcon#*after write, iclass 10, count 0 2006.253.08:05:42.67#ibcon#*before return 0, iclass 10, count 0 2006.253.08:05:42.67#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.253.08:05:42.67#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.253.08:05:42.67#ibcon#about to clear, iclass 10 cls_cnt 0 2006.253.08:05:42.67#ibcon#cleared, iclass 10 cls_cnt 0 2006.253.08:05:42.67$vc4f8/vbbw=wide 2006.253.08:05:42.67#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.253.08:05:42.67#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.253.08:05:42.67#ibcon#ireg 8 cls_cnt 0 2006.253.08:05:42.67#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.253.08:05:42.74#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.253.08:05:42.74#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.253.08:05:42.74#ibcon#enter wrdev, iclass 12, count 0 2006.253.08:05:42.74#ibcon#first serial, iclass 12, count 0 2006.253.08:05:42.74#ibcon#enter sib2, iclass 12, count 0 2006.253.08:05:42.74#ibcon#flushed, iclass 12, count 0 2006.253.08:05:42.74#ibcon#about to write, iclass 12, count 0 2006.253.08:05:42.74#ibcon#wrote, iclass 12, count 0 2006.253.08:05:42.74#ibcon#about to read 3, iclass 12, count 0 2006.253.08:05:42.76#ibcon#read 3, iclass 12, count 0 2006.253.08:05:42.76#ibcon#about to read 4, iclass 12, count 0 2006.253.08:05:42.76#ibcon#read 4, iclass 12, count 0 2006.253.08:05:42.76#ibcon#about to read 5, iclass 12, count 0 2006.253.08:05:42.76#ibcon#read 5, iclass 12, count 0 2006.253.08:05:42.76#ibcon#about to read 6, iclass 12, count 0 2006.253.08:05:42.76#ibcon#read 6, iclass 12, count 0 2006.253.08:05:42.76#ibcon#end of sib2, iclass 12, count 0 2006.253.08:05:42.76#ibcon#*mode == 0, iclass 12, count 0 2006.253.08:05:42.76#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.253.08:05:42.76#ibcon#[27=BW32\r\n] 2006.253.08:05:42.76#ibcon#*before write, iclass 12, count 0 2006.253.08:05:42.76#ibcon#enter sib2, iclass 12, count 0 2006.253.08:05:42.76#ibcon#flushed, iclass 12, count 0 2006.253.08:05:42.76#ibcon#about to write, iclass 12, count 0 2006.253.08:05:42.76#ibcon#wrote, iclass 12, count 0 2006.253.08:05:42.76#ibcon#about to read 3, iclass 12, count 0 2006.253.08:05:42.79#ibcon#read 3, iclass 12, count 0 2006.253.08:05:42.79#ibcon#about to read 4, iclass 12, count 0 2006.253.08:05:42.79#ibcon#read 4, iclass 12, count 0 2006.253.08:05:42.79#ibcon#about to read 5, iclass 12, count 0 2006.253.08:05:42.79#ibcon#read 5, iclass 12, count 0 2006.253.08:05:42.79#ibcon#about to read 6, iclass 12, count 0 2006.253.08:05:42.79#ibcon#read 6, iclass 12, count 0 2006.253.08:05:42.79#ibcon#end of sib2, iclass 12, count 0 2006.253.08:05:42.79#ibcon#*after write, iclass 12, count 0 2006.253.08:05:42.79#ibcon#*before return 0, iclass 12, count 0 2006.253.08:05:42.79#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.253.08:05:42.79#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.253.08:05:42.79#ibcon#about to clear, iclass 12 cls_cnt 0 2006.253.08:05:42.79#ibcon#cleared, iclass 12 cls_cnt 0 2006.253.08:05:42.79$4f8m12a/ifd4f 2006.253.08:05:42.79$ifd4f/lo= 2006.253.08:05:42.79$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.253.08:05:42.79$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.253.08:05:42.79$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.253.08:05:42.79$ifd4f/patch= 2006.253.08:05:42.79$ifd4f/patch=lo1,a1,a2,a3,a4 2006.253.08:05:42.79$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.253.08:05:42.79$ifd4f/patch=lo3,a5,a6,a7,a8 2006.253.08:05:42.79$4f8m12a/"form=m,16.000,1:2 2006.253.08:05:42.79$4f8m12a/"tpicd 2006.253.08:05:42.79$4f8m12a/echo=off 2006.253.08:05:42.79$4f8m12a/xlog=off 2006.253.08:05:42.79:!2006.253.08:06:10 2006.253.08:05:50.14#trakl#Source acquired 2006.253.08:05:52.14#flagr#flagr/antenna,acquired 2006.253.08:06:10.00:preob 2006.253.08:06:11.14/onsource/TRACKING 2006.253.08:06:11.14:!2006.253.08:06:20 2006.253.08:06:20.00:data_valid=on 2006.253.08:06:20.00:midob 2006.253.08:06:20.14/onsource/TRACKING 2006.253.08:06:20.14/wx/31.03,1006.4,74 2006.253.08:06:20.20/cable/+6.3672E-03 2006.253.08:06:21.29/va/01,08,usb,yes,31,33 2006.253.08:06:21.29/va/02,07,usb,yes,31,33 2006.253.08:06:21.29/va/03,06,usb,yes,33,33 2006.253.08:06:21.29/va/04,07,usb,yes,32,35 2006.253.08:06:21.29/va/05,07,usb,yes,34,36 2006.253.08:06:21.29/va/06,07,usb,yes,29,29 2006.253.08:06:21.29/va/07,07,usb,yes,29,29 2006.253.08:06:21.29/va/08,07,usb,yes,32,31 2006.253.08:06:21.52/valo/01,532.99,yes,locked 2006.253.08:06:21.52/valo/02,572.99,yes,locked 2006.253.08:06:21.52/valo/03,672.99,yes,locked 2006.253.08:06:21.52/valo/04,832.99,yes,locked 2006.253.08:06:21.52/valo/05,652.99,yes,locked 2006.253.08:06:21.52/valo/06,772.99,yes,locked 2006.253.08:06:21.52/valo/07,832.99,yes,locked 2006.253.08:06:21.52/valo/08,852.99,yes,locked 2006.253.08:06:22.61/vb/01,04,usb,yes,30,29 2006.253.08:06:22.61/vb/02,05,usb,yes,28,30 2006.253.08:06:22.61/vb/03,04,usb,yes,28,32 2006.253.08:06:22.61/vb/04,04,usb,yes,29,30 2006.253.08:06:22.61/vb/05,04,usb,yes,28,32 2006.253.08:06:22.61/vb/06,04,usb,yes,29,32 2006.253.08:06:22.61/vb/07,04,usb,yes,31,31 2006.253.08:06:22.61/vb/08,04,usb,yes,28,32 2006.253.08:06:22.85/vblo/01,632.99,yes,locked 2006.253.08:06:22.85/vblo/02,640.99,yes,locked 2006.253.08:06:22.85/vblo/03,656.99,yes,locked 2006.253.08:06:22.85/vblo/04,712.99,yes,locked 2006.253.08:06:22.85/vblo/05,744.99,yes,locked 2006.253.08:06:22.85/vblo/06,752.99,yes,locked 2006.253.08:06:22.85/vblo/07,734.99,yes,locked 2006.253.08:06:22.85/vblo/08,744.99,yes,locked 2006.253.08:06:23.00/vabw/8 2006.253.08:06:23.15/vbbw/8 2006.253.08:06:23.24/xfe/off,on,14.2 2006.253.08:06:23.62/ifatt/23,28,28,28 2006.253.08:06:24.08/fmout-gps/S +4.77E-07 2006.253.08:06:24.16:!2006.253.08:07:20 2006.253.08:07:20.00:data_valid=off 2006.253.08:07:20.00:postob 2006.253.08:07:20.12/cable/+6.3685E-03 2006.253.08:07:20.12/wx/31.01,1006.4,74 2006.253.08:07:21.08/fmout-gps/S +4.76E-07 2006.253.08:07:21.08:scan_name=253-0808,k06253,60 2006.253.08:07:21.09:source=nrao512,164029.63,394646.0,2000.0,ccw 2006.253.08:07:21.14#flagr#flagr/antenna,new-source 2006.253.08:07:22.14:checkk5 2006.253.08:07:22.54/chk_autoobs//k5ts1/ autoobs is running! 2006.253.08:07:22.92/chk_autoobs//k5ts2/ autoobs is running! 2006.253.08:07:23.32/chk_autoobs//k5ts3/ autoobs is running! 2006.253.08:07:23.68/chk_autoobs//k5ts4/ autoobs is running! 2006.253.08:07:24.05/chk_obsdata//k5ts1/T2530806??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.08:07:24.43/chk_obsdata//k5ts2/T2530806??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.08:07:24.80/chk_obsdata//k5ts3/T2530806??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.08:07:25.17/chk_obsdata//k5ts4/T2530806??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.08:07:25.87/k5log//k5ts1_log_newline 2006.253.08:07:26.57/k5log//k5ts2_log_newline 2006.253.08:07:27.27/k5log//k5ts3_log_newline 2006.253.08:07:27.96/k5log//k5ts4_log_newline 2006.253.08:07:27.98/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.253.08:07:27.98:4f8m12a=2 2006.253.08:07:27.98$4f8m12a/echo=on 2006.253.08:07:27.98$4f8m12a/pcalon 2006.253.08:07:27.98$pcalon/"no phase cal control is implemented here 2006.253.08:07:27.98$4f8m12a/"tpicd=stop 2006.253.08:07:27.98$4f8m12a/vc4f8 2006.253.08:07:27.98$vc4f8/valo=1,532.99 2006.253.08:07:27.98#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.253.08:07:27.98#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.253.08:07:27.98#ibcon#ireg 17 cls_cnt 0 2006.253.08:07:27.98#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.253.08:07:27.98#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.253.08:07:27.98#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.253.08:07:27.98#ibcon#enter wrdev, iclass 23, count 0 2006.253.08:07:27.98#ibcon#first serial, iclass 23, count 0 2006.253.08:07:27.98#ibcon#enter sib2, iclass 23, count 0 2006.253.08:07:27.98#ibcon#flushed, iclass 23, count 0 2006.253.08:07:27.98#ibcon#about to write, iclass 23, count 0 2006.253.08:07:27.98#ibcon#wrote, iclass 23, count 0 2006.253.08:07:27.98#ibcon#about to read 3, iclass 23, count 0 2006.253.08:07:28.03#ibcon#read 3, iclass 23, count 0 2006.253.08:07:28.03#ibcon#about to read 4, iclass 23, count 0 2006.253.08:07:28.03#ibcon#read 4, iclass 23, count 0 2006.253.08:07:28.03#ibcon#about to read 5, iclass 23, count 0 2006.253.08:07:28.03#ibcon#read 5, iclass 23, count 0 2006.253.08:07:28.03#ibcon#about to read 6, iclass 23, count 0 2006.253.08:07:28.03#ibcon#read 6, iclass 23, count 0 2006.253.08:07:28.03#ibcon#end of sib2, iclass 23, count 0 2006.253.08:07:28.03#ibcon#*mode == 0, iclass 23, count 0 2006.253.08:07:28.03#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.253.08:07:28.03#ibcon#[26=FRQ=01,532.99\r\n] 2006.253.08:07:28.03#ibcon#*before write, iclass 23, count 0 2006.253.08:07:28.03#ibcon#enter sib2, iclass 23, count 0 2006.253.08:07:28.03#ibcon#flushed, iclass 23, count 0 2006.253.08:07:28.03#ibcon#about to write, iclass 23, count 0 2006.253.08:07:28.03#ibcon#wrote, iclass 23, count 0 2006.253.08:07:28.03#ibcon#about to read 3, iclass 23, count 0 2006.253.08:07:28.08#ibcon#read 3, iclass 23, count 0 2006.253.08:07:28.08#ibcon#about to read 4, iclass 23, count 0 2006.253.08:07:28.08#ibcon#read 4, iclass 23, count 0 2006.253.08:07:28.08#ibcon#about to read 5, iclass 23, count 0 2006.253.08:07:28.08#ibcon#read 5, iclass 23, count 0 2006.253.08:07:28.08#ibcon#about to read 6, iclass 23, count 0 2006.253.08:07:28.08#ibcon#read 6, iclass 23, count 0 2006.253.08:07:28.08#ibcon#end of sib2, iclass 23, count 0 2006.253.08:07:28.08#ibcon#*after write, iclass 23, count 0 2006.253.08:07:28.08#ibcon#*before return 0, iclass 23, count 0 2006.253.08:07:28.08#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.253.08:07:28.08#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.253.08:07:28.08#ibcon#about to clear, iclass 23 cls_cnt 0 2006.253.08:07:28.08#ibcon#cleared, iclass 23 cls_cnt 0 2006.253.08:07:28.08$vc4f8/va=1,8 2006.253.08:07:28.08#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.253.08:07:28.08#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.253.08:07:28.08#ibcon#ireg 11 cls_cnt 2 2006.253.08:07:28.08#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.253.08:07:28.08#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.253.08:07:28.08#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.253.08:07:28.08#ibcon#enter wrdev, iclass 25, count 2 2006.253.08:07:28.08#ibcon#first serial, iclass 25, count 2 2006.253.08:07:28.08#ibcon#enter sib2, iclass 25, count 2 2006.253.08:07:28.08#ibcon#flushed, iclass 25, count 2 2006.253.08:07:28.08#ibcon#about to write, iclass 25, count 2 2006.253.08:07:28.08#ibcon#wrote, iclass 25, count 2 2006.253.08:07:28.08#ibcon#about to read 3, iclass 25, count 2 2006.253.08:07:28.10#ibcon#read 3, iclass 25, count 2 2006.253.08:07:28.10#ibcon#about to read 4, iclass 25, count 2 2006.253.08:07:28.10#ibcon#read 4, iclass 25, count 2 2006.253.08:07:28.10#ibcon#about to read 5, iclass 25, count 2 2006.253.08:07:28.10#ibcon#read 5, iclass 25, count 2 2006.253.08:07:28.10#ibcon#about to read 6, iclass 25, count 2 2006.253.08:07:28.10#ibcon#read 6, iclass 25, count 2 2006.253.08:07:28.10#ibcon#end of sib2, iclass 25, count 2 2006.253.08:07:28.10#ibcon#*mode == 0, iclass 25, count 2 2006.253.08:07:28.10#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.253.08:07:28.10#ibcon#[25=AT01-08\r\n] 2006.253.08:07:28.10#ibcon#*before write, iclass 25, count 2 2006.253.08:07:28.10#ibcon#enter sib2, iclass 25, count 2 2006.253.08:07:28.10#ibcon#flushed, iclass 25, count 2 2006.253.08:07:28.10#ibcon#about to write, iclass 25, count 2 2006.253.08:07:28.10#ibcon#wrote, iclass 25, count 2 2006.253.08:07:28.10#ibcon#about to read 3, iclass 25, count 2 2006.253.08:07:28.13#ibcon#read 3, iclass 25, count 2 2006.253.08:07:28.13#ibcon#about to read 4, iclass 25, count 2 2006.253.08:07:28.13#ibcon#read 4, iclass 25, count 2 2006.253.08:07:28.13#ibcon#about to read 5, iclass 25, count 2 2006.253.08:07:28.13#ibcon#read 5, iclass 25, count 2 2006.253.08:07:28.13#ibcon#about to read 6, iclass 25, count 2 2006.253.08:07:28.13#ibcon#read 6, iclass 25, count 2 2006.253.08:07:28.13#ibcon#end of sib2, iclass 25, count 2 2006.253.08:07:28.13#ibcon#*after write, iclass 25, count 2 2006.253.08:07:28.13#ibcon#*before return 0, iclass 25, count 2 2006.253.08:07:28.13#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.253.08:07:28.13#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.253.08:07:28.13#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.253.08:07:28.13#ibcon#ireg 7 cls_cnt 0 2006.253.08:07:28.13#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.253.08:07:28.25#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.253.08:07:28.25#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.253.08:07:28.25#ibcon#enter wrdev, iclass 25, count 0 2006.253.08:07:28.25#ibcon#first serial, iclass 25, count 0 2006.253.08:07:28.25#ibcon#enter sib2, iclass 25, count 0 2006.253.08:07:28.25#ibcon#flushed, iclass 25, count 0 2006.253.08:07:28.25#ibcon#about to write, iclass 25, count 0 2006.253.08:07:28.25#ibcon#wrote, iclass 25, count 0 2006.253.08:07:28.25#ibcon#about to read 3, iclass 25, count 0 2006.253.08:07:28.27#ibcon#read 3, iclass 25, count 0 2006.253.08:07:28.27#ibcon#about to read 4, iclass 25, count 0 2006.253.08:07:28.27#ibcon#read 4, iclass 25, count 0 2006.253.08:07:28.27#ibcon#about to read 5, iclass 25, count 0 2006.253.08:07:28.27#ibcon#read 5, iclass 25, count 0 2006.253.08:07:28.27#ibcon#about to read 6, iclass 25, count 0 2006.253.08:07:28.27#ibcon#read 6, iclass 25, count 0 2006.253.08:07:28.27#ibcon#end of sib2, iclass 25, count 0 2006.253.08:07:28.27#ibcon#*mode == 0, iclass 25, count 0 2006.253.08:07:28.27#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.253.08:07:28.27#ibcon#[25=USB\r\n] 2006.253.08:07:28.27#ibcon#*before write, iclass 25, count 0 2006.253.08:07:28.27#ibcon#enter sib2, iclass 25, count 0 2006.253.08:07:28.27#ibcon#flushed, iclass 25, count 0 2006.253.08:07:28.27#ibcon#about to write, iclass 25, count 0 2006.253.08:07:28.27#ibcon#wrote, iclass 25, count 0 2006.253.08:07:28.27#ibcon#about to read 3, iclass 25, count 0 2006.253.08:07:28.30#ibcon#read 3, iclass 25, count 0 2006.253.08:07:28.30#ibcon#about to read 4, iclass 25, count 0 2006.253.08:07:28.30#ibcon#read 4, iclass 25, count 0 2006.253.08:07:28.30#ibcon#about to read 5, iclass 25, count 0 2006.253.08:07:28.30#ibcon#read 5, iclass 25, count 0 2006.253.08:07:28.30#ibcon#about to read 6, iclass 25, count 0 2006.253.08:07:28.30#ibcon#read 6, iclass 25, count 0 2006.253.08:07:28.30#ibcon#end of sib2, iclass 25, count 0 2006.253.08:07:28.30#ibcon#*after write, iclass 25, count 0 2006.253.08:07:28.30#ibcon#*before return 0, iclass 25, count 0 2006.253.08:07:28.30#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.253.08:07:28.30#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.253.08:07:28.30#ibcon#about to clear, iclass 25 cls_cnt 0 2006.253.08:07:28.30#ibcon#cleared, iclass 25 cls_cnt 0 2006.253.08:07:28.30$vc4f8/valo=2,572.99 2006.253.08:07:28.30#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.253.08:07:28.30#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.253.08:07:28.30#ibcon#ireg 17 cls_cnt 0 2006.253.08:07:28.30#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.253.08:07:28.30#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.253.08:07:28.30#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.253.08:07:28.30#ibcon#enter wrdev, iclass 27, count 0 2006.253.08:07:28.30#ibcon#first serial, iclass 27, count 0 2006.253.08:07:28.30#ibcon#enter sib2, iclass 27, count 0 2006.253.08:07:28.30#ibcon#flushed, iclass 27, count 0 2006.253.08:07:28.30#ibcon#about to write, iclass 27, count 0 2006.253.08:07:28.30#ibcon#wrote, iclass 27, count 0 2006.253.08:07:28.30#ibcon#about to read 3, iclass 27, count 0 2006.253.08:07:28.33#ibcon#read 3, iclass 27, count 0 2006.253.08:07:28.33#ibcon#about to read 4, iclass 27, count 0 2006.253.08:07:28.33#ibcon#read 4, iclass 27, count 0 2006.253.08:07:28.33#ibcon#about to read 5, iclass 27, count 0 2006.253.08:07:28.33#ibcon#read 5, iclass 27, count 0 2006.253.08:07:28.33#ibcon#about to read 6, iclass 27, count 0 2006.253.08:07:28.33#ibcon#read 6, iclass 27, count 0 2006.253.08:07:28.33#ibcon#end of sib2, iclass 27, count 0 2006.253.08:07:28.33#ibcon#*mode == 0, iclass 27, count 0 2006.253.08:07:28.33#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.253.08:07:28.33#ibcon#[26=FRQ=02,572.99\r\n] 2006.253.08:07:28.33#ibcon#*before write, iclass 27, count 0 2006.253.08:07:28.33#ibcon#enter sib2, iclass 27, count 0 2006.253.08:07:28.33#ibcon#flushed, iclass 27, count 0 2006.253.08:07:28.33#ibcon#about to write, iclass 27, count 0 2006.253.08:07:28.33#ibcon#wrote, iclass 27, count 0 2006.253.08:07:28.33#ibcon#about to read 3, iclass 27, count 0 2006.253.08:07:28.37#ibcon#read 3, iclass 27, count 0 2006.253.08:07:28.37#ibcon#about to read 4, iclass 27, count 0 2006.253.08:07:28.37#ibcon#read 4, iclass 27, count 0 2006.253.08:07:28.37#ibcon#about to read 5, iclass 27, count 0 2006.253.08:07:28.37#ibcon#read 5, iclass 27, count 0 2006.253.08:07:28.37#ibcon#about to read 6, iclass 27, count 0 2006.253.08:07:28.37#ibcon#read 6, iclass 27, count 0 2006.253.08:07:28.37#ibcon#end of sib2, iclass 27, count 0 2006.253.08:07:28.37#ibcon#*after write, iclass 27, count 0 2006.253.08:07:28.37#ibcon#*before return 0, iclass 27, count 0 2006.253.08:07:28.37#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.253.08:07:28.37#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.253.08:07:28.37#ibcon#about to clear, iclass 27 cls_cnt 0 2006.253.08:07:28.37#ibcon#cleared, iclass 27 cls_cnt 0 2006.253.08:07:28.37$vc4f8/va=2,7 2006.253.08:07:28.37#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.253.08:07:28.37#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.253.08:07:28.37#ibcon#ireg 11 cls_cnt 2 2006.253.08:07:28.37#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.253.08:07:28.42#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.253.08:07:28.42#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.253.08:07:28.42#ibcon#enter wrdev, iclass 29, count 2 2006.253.08:07:28.42#ibcon#first serial, iclass 29, count 2 2006.253.08:07:28.42#ibcon#enter sib2, iclass 29, count 2 2006.253.08:07:28.42#ibcon#flushed, iclass 29, count 2 2006.253.08:07:28.42#ibcon#about to write, iclass 29, count 2 2006.253.08:07:28.42#ibcon#wrote, iclass 29, count 2 2006.253.08:07:28.42#ibcon#about to read 3, iclass 29, count 2 2006.253.08:07:28.44#ibcon#read 3, iclass 29, count 2 2006.253.08:07:28.44#ibcon#about to read 4, iclass 29, count 2 2006.253.08:07:28.44#ibcon#read 4, iclass 29, count 2 2006.253.08:07:28.44#ibcon#about to read 5, iclass 29, count 2 2006.253.08:07:28.44#ibcon#read 5, iclass 29, count 2 2006.253.08:07:28.44#ibcon#about to read 6, iclass 29, count 2 2006.253.08:07:28.44#ibcon#read 6, iclass 29, count 2 2006.253.08:07:28.44#ibcon#end of sib2, iclass 29, count 2 2006.253.08:07:28.44#ibcon#*mode == 0, iclass 29, count 2 2006.253.08:07:28.44#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.253.08:07:28.44#ibcon#[25=AT02-07\r\n] 2006.253.08:07:28.44#ibcon#*before write, iclass 29, count 2 2006.253.08:07:28.44#ibcon#enter sib2, iclass 29, count 2 2006.253.08:07:28.44#ibcon#flushed, iclass 29, count 2 2006.253.08:07:28.44#ibcon#about to write, iclass 29, count 2 2006.253.08:07:28.44#ibcon#wrote, iclass 29, count 2 2006.253.08:07:28.44#ibcon#about to read 3, iclass 29, count 2 2006.253.08:07:28.47#ibcon#read 3, iclass 29, count 2 2006.253.08:07:28.47#ibcon#about to read 4, iclass 29, count 2 2006.253.08:07:28.47#ibcon#read 4, iclass 29, count 2 2006.253.08:07:28.47#ibcon#about to read 5, iclass 29, count 2 2006.253.08:07:28.47#ibcon#read 5, iclass 29, count 2 2006.253.08:07:28.47#ibcon#about to read 6, iclass 29, count 2 2006.253.08:07:28.47#ibcon#read 6, iclass 29, count 2 2006.253.08:07:28.47#ibcon#end of sib2, iclass 29, count 2 2006.253.08:07:28.47#ibcon#*after write, iclass 29, count 2 2006.253.08:07:28.47#ibcon#*before return 0, iclass 29, count 2 2006.253.08:07:28.47#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.253.08:07:28.47#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.253.08:07:28.47#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.253.08:07:28.47#ibcon#ireg 7 cls_cnt 0 2006.253.08:07:28.47#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.253.08:07:28.59#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.253.08:07:28.59#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.253.08:07:28.59#ibcon#enter wrdev, iclass 29, count 0 2006.253.08:07:28.59#ibcon#first serial, iclass 29, count 0 2006.253.08:07:28.59#ibcon#enter sib2, iclass 29, count 0 2006.253.08:07:28.59#ibcon#flushed, iclass 29, count 0 2006.253.08:07:28.59#ibcon#about to write, iclass 29, count 0 2006.253.08:07:28.59#ibcon#wrote, iclass 29, count 0 2006.253.08:07:28.59#ibcon#about to read 3, iclass 29, count 0 2006.253.08:07:28.61#ibcon#read 3, iclass 29, count 0 2006.253.08:07:28.61#ibcon#about to read 4, iclass 29, count 0 2006.253.08:07:28.61#ibcon#read 4, iclass 29, count 0 2006.253.08:07:28.61#ibcon#about to read 5, iclass 29, count 0 2006.253.08:07:28.61#ibcon#read 5, iclass 29, count 0 2006.253.08:07:28.61#ibcon#about to read 6, iclass 29, count 0 2006.253.08:07:28.61#ibcon#read 6, iclass 29, count 0 2006.253.08:07:28.61#ibcon#end of sib2, iclass 29, count 0 2006.253.08:07:28.61#ibcon#*mode == 0, iclass 29, count 0 2006.253.08:07:28.61#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.253.08:07:28.61#ibcon#[25=USB\r\n] 2006.253.08:07:28.61#ibcon#*before write, iclass 29, count 0 2006.253.08:07:28.61#ibcon#enter sib2, iclass 29, count 0 2006.253.08:07:28.61#ibcon#flushed, iclass 29, count 0 2006.253.08:07:28.61#ibcon#about to write, iclass 29, count 0 2006.253.08:07:28.61#ibcon#wrote, iclass 29, count 0 2006.253.08:07:28.61#ibcon#about to read 3, iclass 29, count 0 2006.253.08:07:28.64#ibcon#read 3, iclass 29, count 0 2006.253.08:07:28.64#ibcon#about to read 4, iclass 29, count 0 2006.253.08:07:28.64#ibcon#read 4, iclass 29, count 0 2006.253.08:07:28.64#ibcon#about to read 5, iclass 29, count 0 2006.253.08:07:28.64#ibcon#read 5, iclass 29, count 0 2006.253.08:07:28.64#ibcon#about to read 6, iclass 29, count 0 2006.253.08:07:28.64#ibcon#read 6, iclass 29, count 0 2006.253.08:07:28.64#ibcon#end of sib2, iclass 29, count 0 2006.253.08:07:28.64#ibcon#*after write, iclass 29, count 0 2006.253.08:07:28.64#ibcon#*before return 0, iclass 29, count 0 2006.253.08:07:28.64#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.253.08:07:28.64#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.253.08:07:28.64#ibcon#about to clear, iclass 29 cls_cnt 0 2006.253.08:07:28.64#ibcon#cleared, iclass 29 cls_cnt 0 2006.253.08:07:28.64$vc4f8/valo=3,672.99 2006.253.08:07:28.64#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.253.08:07:28.64#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.253.08:07:28.64#ibcon#ireg 17 cls_cnt 0 2006.253.08:07:28.64#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.253.08:07:28.64#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.253.08:07:28.64#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.253.08:07:28.64#ibcon#enter wrdev, iclass 31, count 0 2006.253.08:07:28.64#ibcon#first serial, iclass 31, count 0 2006.253.08:07:28.64#ibcon#enter sib2, iclass 31, count 0 2006.253.08:07:28.64#ibcon#flushed, iclass 31, count 0 2006.253.08:07:28.64#ibcon#about to write, iclass 31, count 0 2006.253.08:07:28.64#ibcon#wrote, iclass 31, count 0 2006.253.08:07:28.64#ibcon#about to read 3, iclass 31, count 0 2006.253.08:07:28.66#ibcon#read 3, iclass 31, count 0 2006.253.08:07:28.66#ibcon#about to read 4, iclass 31, count 0 2006.253.08:07:28.67#ibcon#read 4, iclass 31, count 0 2006.253.08:07:28.67#ibcon#about to read 5, iclass 31, count 0 2006.253.08:07:28.67#ibcon#read 5, iclass 31, count 0 2006.253.08:07:28.67#ibcon#about to read 6, iclass 31, count 0 2006.253.08:07:28.67#ibcon#read 6, iclass 31, count 0 2006.253.08:07:28.67#ibcon#end of sib2, iclass 31, count 0 2006.253.08:07:28.67#ibcon#*mode == 0, iclass 31, count 0 2006.253.08:07:28.67#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.253.08:07:28.67#ibcon#[26=FRQ=03,672.99\r\n] 2006.253.08:07:28.67#ibcon#*before write, iclass 31, count 0 2006.253.08:07:28.67#ibcon#enter sib2, iclass 31, count 0 2006.253.08:07:28.67#ibcon#flushed, iclass 31, count 0 2006.253.08:07:28.67#ibcon#about to write, iclass 31, count 0 2006.253.08:07:28.67#ibcon#wrote, iclass 31, count 0 2006.253.08:07:28.67#ibcon#about to read 3, iclass 31, count 0 2006.253.08:07:28.71#ibcon#read 3, iclass 31, count 0 2006.253.08:07:28.71#ibcon#about to read 4, iclass 31, count 0 2006.253.08:07:28.71#ibcon#read 4, iclass 31, count 0 2006.253.08:07:28.71#ibcon#about to read 5, iclass 31, count 0 2006.253.08:07:28.71#ibcon#read 5, iclass 31, count 0 2006.253.08:07:28.71#ibcon#about to read 6, iclass 31, count 0 2006.253.08:07:28.71#ibcon#read 6, iclass 31, count 0 2006.253.08:07:28.71#ibcon#end of sib2, iclass 31, count 0 2006.253.08:07:28.71#ibcon#*after write, iclass 31, count 0 2006.253.08:07:28.71#ibcon#*before return 0, iclass 31, count 0 2006.253.08:07:28.71#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.253.08:07:28.71#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.253.08:07:28.71#ibcon#about to clear, iclass 31 cls_cnt 0 2006.253.08:07:28.71#ibcon#cleared, iclass 31 cls_cnt 0 2006.253.08:07:28.71$vc4f8/va=3,6 2006.253.08:07:28.71#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.253.08:07:28.71#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.253.08:07:28.71#ibcon#ireg 11 cls_cnt 2 2006.253.08:07:28.71#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.253.08:07:28.76#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.253.08:07:28.76#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.253.08:07:28.76#ibcon#enter wrdev, iclass 33, count 2 2006.253.08:07:28.76#ibcon#first serial, iclass 33, count 2 2006.253.08:07:28.76#ibcon#enter sib2, iclass 33, count 2 2006.253.08:07:28.76#ibcon#flushed, iclass 33, count 2 2006.253.08:07:28.76#ibcon#about to write, iclass 33, count 2 2006.253.08:07:28.76#ibcon#wrote, iclass 33, count 2 2006.253.08:07:28.76#ibcon#about to read 3, iclass 33, count 2 2006.253.08:07:28.78#ibcon#read 3, iclass 33, count 2 2006.253.08:07:28.78#ibcon#about to read 4, iclass 33, count 2 2006.253.08:07:28.78#ibcon#read 4, iclass 33, count 2 2006.253.08:07:28.78#ibcon#about to read 5, iclass 33, count 2 2006.253.08:07:28.78#ibcon#read 5, iclass 33, count 2 2006.253.08:07:28.78#ibcon#about to read 6, iclass 33, count 2 2006.253.08:07:28.78#ibcon#read 6, iclass 33, count 2 2006.253.08:07:28.78#ibcon#end of sib2, iclass 33, count 2 2006.253.08:07:28.78#ibcon#*mode == 0, iclass 33, count 2 2006.253.08:07:28.78#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.253.08:07:28.78#ibcon#[25=AT03-06\r\n] 2006.253.08:07:28.78#ibcon#*before write, iclass 33, count 2 2006.253.08:07:28.78#ibcon#enter sib2, iclass 33, count 2 2006.253.08:07:28.78#ibcon#flushed, iclass 33, count 2 2006.253.08:07:28.78#ibcon#about to write, iclass 33, count 2 2006.253.08:07:28.78#ibcon#wrote, iclass 33, count 2 2006.253.08:07:28.78#ibcon#about to read 3, iclass 33, count 2 2006.253.08:07:28.81#ibcon#read 3, iclass 33, count 2 2006.253.08:07:28.81#ibcon#about to read 4, iclass 33, count 2 2006.253.08:07:28.81#ibcon#read 4, iclass 33, count 2 2006.253.08:07:28.81#ibcon#about to read 5, iclass 33, count 2 2006.253.08:07:28.81#ibcon#read 5, iclass 33, count 2 2006.253.08:07:28.81#ibcon#about to read 6, iclass 33, count 2 2006.253.08:07:28.81#ibcon#read 6, iclass 33, count 2 2006.253.08:07:28.81#ibcon#end of sib2, iclass 33, count 2 2006.253.08:07:28.81#ibcon#*after write, iclass 33, count 2 2006.253.08:07:28.81#ibcon#*before return 0, iclass 33, count 2 2006.253.08:07:28.81#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.253.08:07:28.81#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.253.08:07:28.81#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.253.08:07:28.81#ibcon#ireg 7 cls_cnt 0 2006.253.08:07:28.81#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.253.08:07:28.93#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.253.08:07:28.93#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.253.08:07:28.93#ibcon#enter wrdev, iclass 33, count 0 2006.253.08:07:28.93#ibcon#first serial, iclass 33, count 0 2006.253.08:07:28.93#ibcon#enter sib2, iclass 33, count 0 2006.253.08:07:28.93#ibcon#flushed, iclass 33, count 0 2006.253.08:07:28.93#ibcon#about to write, iclass 33, count 0 2006.253.08:07:28.93#ibcon#wrote, iclass 33, count 0 2006.253.08:07:28.93#ibcon#about to read 3, iclass 33, count 0 2006.253.08:07:28.95#ibcon#read 3, iclass 33, count 0 2006.253.08:07:28.95#ibcon#about to read 4, iclass 33, count 0 2006.253.08:07:28.95#ibcon#read 4, iclass 33, count 0 2006.253.08:07:28.95#ibcon#about to read 5, iclass 33, count 0 2006.253.08:07:28.95#ibcon#read 5, iclass 33, count 0 2006.253.08:07:28.95#ibcon#about to read 6, iclass 33, count 0 2006.253.08:07:28.95#ibcon#read 6, iclass 33, count 0 2006.253.08:07:28.95#ibcon#end of sib2, iclass 33, count 0 2006.253.08:07:28.95#ibcon#*mode == 0, iclass 33, count 0 2006.253.08:07:28.95#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.253.08:07:28.95#ibcon#[25=USB\r\n] 2006.253.08:07:28.95#ibcon#*before write, iclass 33, count 0 2006.253.08:07:28.95#ibcon#enter sib2, iclass 33, count 0 2006.253.08:07:28.95#ibcon#flushed, iclass 33, count 0 2006.253.08:07:28.95#ibcon#about to write, iclass 33, count 0 2006.253.08:07:28.95#ibcon#wrote, iclass 33, count 0 2006.253.08:07:28.95#ibcon#about to read 3, iclass 33, count 0 2006.253.08:07:28.98#ibcon#read 3, iclass 33, count 0 2006.253.08:07:28.98#ibcon#about to read 4, iclass 33, count 0 2006.253.08:07:28.98#ibcon#read 4, iclass 33, count 0 2006.253.08:07:28.98#ibcon#about to read 5, iclass 33, count 0 2006.253.08:07:28.98#ibcon#read 5, iclass 33, count 0 2006.253.08:07:28.98#ibcon#about to read 6, iclass 33, count 0 2006.253.08:07:28.98#ibcon#read 6, iclass 33, count 0 2006.253.08:07:28.98#ibcon#end of sib2, iclass 33, count 0 2006.253.08:07:28.98#ibcon#*after write, iclass 33, count 0 2006.253.08:07:28.98#ibcon#*before return 0, iclass 33, count 0 2006.253.08:07:28.98#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.253.08:07:28.98#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.253.08:07:28.98#ibcon#about to clear, iclass 33 cls_cnt 0 2006.253.08:07:28.98#ibcon#cleared, iclass 33 cls_cnt 0 2006.253.08:07:28.98$vc4f8/valo=4,832.99 2006.253.08:07:28.98#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.253.08:07:28.98#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.253.08:07:28.98#ibcon#ireg 17 cls_cnt 0 2006.253.08:07:28.98#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.253.08:07:28.98#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.253.08:07:28.98#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.253.08:07:28.98#ibcon#enter wrdev, iclass 35, count 0 2006.253.08:07:28.98#ibcon#first serial, iclass 35, count 0 2006.253.08:07:28.98#ibcon#enter sib2, iclass 35, count 0 2006.253.08:07:28.98#ibcon#flushed, iclass 35, count 0 2006.253.08:07:28.98#ibcon#about to write, iclass 35, count 0 2006.253.08:07:28.98#ibcon#wrote, iclass 35, count 0 2006.253.08:07:28.98#ibcon#about to read 3, iclass 35, count 0 2006.253.08:07:29.00#ibcon#read 3, iclass 35, count 0 2006.253.08:07:29.00#ibcon#about to read 4, iclass 35, count 0 2006.253.08:07:29.00#ibcon#read 4, iclass 35, count 0 2006.253.08:07:29.01#ibcon#about to read 5, iclass 35, count 0 2006.253.08:07:29.01#ibcon#read 5, iclass 35, count 0 2006.253.08:07:29.01#ibcon#about to read 6, iclass 35, count 0 2006.253.08:07:29.01#ibcon#read 6, iclass 35, count 0 2006.253.08:07:29.01#ibcon#end of sib2, iclass 35, count 0 2006.253.08:07:29.01#ibcon#*mode == 0, iclass 35, count 0 2006.253.08:07:29.01#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.253.08:07:29.01#ibcon#[26=FRQ=04,832.99\r\n] 2006.253.08:07:29.01#ibcon#*before write, iclass 35, count 0 2006.253.08:07:29.01#ibcon#enter sib2, iclass 35, count 0 2006.253.08:07:29.01#ibcon#flushed, iclass 35, count 0 2006.253.08:07:29.01#ibcon#about to write, iclass 35, count 0 2006.253.08:07:29.01#ibcon#wrote, iclass 35, count 0 2006.253.08:07:29.01#ibcon#about to read 3, iclass 35, count 0 2006.253.08:07:29.05#ibcon#read 3, iclass 35, count 0 2006.253.08:07:29.05#ibcon#about to read 4, iclass 35, count 0 2006.253.08:07:29.05#ibcon#read 4, iclass 35, count 0 2006.253.08:07:29.05#ibcon#about to read 5, iclass 35, count 0 2006.253.08:07:29.05#ibcon#read 5, iclass 35, count 0 2006.253.08:07:29.05#ibcon#about to read 6, iclass 35, count 0 2006.253.08:07:29.05#ibcon#read 6, iclass 35, count 0 2006.253.08:07:29.05#ibcon#end of sib2, iclass 35, count 0 2006.253.08:07:29.05#ibcon#*after write, iclass 35, count 0 2006.253.08:07:29.05#ibcon#*before return 0, iclass 35, count 0 2006.253.08:07:29.05#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.253.08:07:29.05#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.253.08:07:29.05#ibcon#about to clear, iclass 35 cls_cnt 0 2006.253.08:07:29.05#ibcon#cleared, iclass 35 cls_cnt 0 2006.253.08:07:29.05$vc4f8/va=4,7 2006.253.08:07:29.05#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.253.08:07:29.05#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.253.08:07:29.05#ibcon#ireg 11 cls_cnt 2 2006.253.08:07:29.05#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.253.08:07:29.10#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.253.08:07:29.10#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.253.08:07:29.10#ibcon#enter wrdev, iclass 37, count 2 2006.253.08:07:29.10#ibcon#first serial, iclass 37, count 2 2006.253.08:07:29.10#ibcon#enter sib2, iclass 37, count 2 2006.253.08:07:29.10#ibcon#flushed, iclass 37, count 2 2006.253.08:07:29.10#ibcon#about to write, iclass 37, count 2 2006.253.08:07:29.10#ibcon#wrote, iclass 37, count 2 2006.253.08:07:29.10#ibcon#about to read 3, iclass 37, count 2 2006.253.08:07:29.12#ibcon#read 3, iclass 37, count 2 2006.253.08:07:29.12#ibcon#about to read 4, iclass 37, count 2 2006.253.08:07:29.12#ibcon#read 4, iclass 37, count 2 2006.253.08:07:29.12#ibcon#about to read 5, iclass 37, count 2 2006.253.08:07:29.12#ibcon#read 5, iclass 37, count 2 2006.253.08:07:29.12#ibcon#about to read 6, iclass 37, count 2 2006.253.08:07:29.12#ibcon#read 6, iclass 37, count 2 2006.253.08:07:29.12#ibcon#end of sib2, iclass 37, count 2 2006.253.08:07:29.12#ibcon#*mode == 0, iclass 37, count 2 2006.253.08:07:29.12#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.253.08:07:29.12#ibcon#[25=AT04-07\r\n] 2006.253.08:07:29.12#ibcon#*before write, iclass 37, count 2 2006.253.08:07:29.12#ibcon#enter sib2, iclass 37, count 2 2006.253.08:07:29.12#ibcon#flushed, iclass 37, count 2 2006.253.08:07:29.12#ibcon#about to write, iclass 37, count 2 2006.253.08:07:29.12#ibcon#wrote, iclass 37, count 2 2006.253.08:07:29.12#ibcon#about to read 3, iclass 37, count 2 2006.253.08:07:29.15#ibcon#read 3, iclass 37, count 2 2006.253.08:07:29.15#ibcon#about to read 4, iclass 37, count 2 2006.253.08:07:29.15#ibcon#read 4, iclass 37, count 2 2006.253.08:07:29.15#ibcon#about to read 5, iclass 37, count 2 2006.253.08:07:29.15#ibcon#read 5, iclass 37, count 2 2006.253.08:07:29.15#ibcon#about to read 6, iclass 37, count 2 2006.253.08:07:29.15#ibcon#read 6, iclass 37, count 2 2006.253.08:07:29.15#ibcon#end of sib2, iclass 37, count 2 2006.253.08:07:29.15#ibcon#*after write, iclass 37, count 2 2006.253.08:07:29.15#ibcon#*before return 0, iclass 37, count 2 2006.253.08:07:29.15#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.253.08:07:29.15#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.253.08:07:29.15#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.253.08:07:29.15#ibcon#ireg 7 cls_cnt 0 2006.253.08:07:29.15#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.253.08:07:29.27#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.253.08:07:29.27#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.253.08:07:29.27#ibcon#enter wrdev, iclass 37, count 0 2006.253.08:07:29.27#ibcon#first serial, iclass 37, count 0 2006.253.08:07:29.27#ibcon#enter sib2, iclass 37, count 0 2006.253.08:07:29.27#ibcon#flushed, iclass 37, count 0 2006.253.08:07:29.27#ibcon#about to write, iclass 37, count 0 2006.253.08:07:29.27#ibcon#wrote, iclass 37, count 0 2006.253.08:07:29.27#ibcon#about to read 3, iclass 37, count 0 2006.253.08:07:29.29#ibcon#read 3, iclass 37, count 0 2006.253.08:07:29.29#ibcon#about to read 4, iclass 37, count 0 2006.253.08:07:29.29#ibcon#read 4, iclass 37, count 0 2006.253.08:07:29.29#ibcon#about to read 5, iclass 37, count 0 2006.253.08:07:29.29#ibcon#read 5, iclass 37, count 0 2006.253.08:07:29.29#ibcon#about to read 6, iclass 37, count 0 2006.253.08:07:29.29#ibcon#read 6, iclass 37, count 0 2006.253.08:07:29.29#ibcon#end of sib2, iclass 37, count 0 2006.253.08:07:29.29#ibcon#*mode == 0, iclass 37, count 0 2006.253.08:07:29.29#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.253.08:07:29.29#ibcon#[25=USB\r\n] 2006.253.08:07:29.29#ibcon#*before write, iclass 37, count 0 2006.253.08:07:29.29#ibcon#enter sib2, iclass 37, count 0 2006.253.08:07:29.29#ibcon#flushed, iclass 37, count 0 2006.253.08:07:29.29#ibcon#about to write, iclass 37, count 0 2006.253.08:07:29.29#ibcon#wrote, iclass 37, count 0 2006.253.08:07:29.29#ibcon#about to read 3, iclass 37, count 0 2006.253.08:07:29.32#ibcon#read 3, iclass 37, count 0 2006.253.08:07:29.32#ibcon#about to read 4, iclass 37, count 0 2006.253.08:07:29.32#ibcon#read 4, iclass 37, count 0 2006.253.08:07:29.32#ibcon#about to read 5, iclass 37, count 0 2006.253.08:07:29.32#ibcon#read 5, iclass 37, count 0 2006.253.08:07:29.32#ibcon#about to read 6, iclass 37, count 0 2006.253.08:07:29.32#ibcon#read 6, iclass 37, count 0 2006.253.08:07:29.32#ibcon#end of sib2, iclass 37, count 0 2006.253.08:07:29.32#ibcon#*after write, iclass 37, count 0 2006.253.08:07:29.32#ibcon#*before return 0, iclass 37, count 0 2006.253.08:07:29.32#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.253.08:07:29.32#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.253.08:07:29.32#ibcon#about to clear, iclass 37 cls_cnt 0 2006.253.08:07:29.32#ibcon#cleared, iclass 37 cls_cnt 0 2006.253.08:07:29.32$vc4f8/valo=5,652.99 2006.253.08:07:29.32#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.253.08:07:29.32#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.253.08:07:29.32#ibcon#ireg 17 cls_cnt 0 2006.253.08:07:29.32#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.253.08:07:29.32#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.253.08:07:29.32#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.253.08:07:29.32#ibcon#enter wrdev, iclass 39, count 0 2006.253.08:07:29.32#ibcon#first serial, iclass 39, count 0 2006.253.08:07:29.32#ibcon#enter sib2, iclass 39, count 0 2006.253.08:07:29.32#ibcon#flushed, iclass 39, count 0 2006.253.08:07:29.32#ibcon#about to write, iclass 39, count 0 2006.253.08:07:29.32#ibcon#wrote, iclass 39, count 0 2006.253.08:07:29.32#ibcon#about to read 3, iclass 39, count 0 2006.253.08:07:29.34#ibcon#read 3, iclass 39, count 0 2006.253.08:07:29.34#ibcon#about to read 4, iclass 39, count 0 2006.253.08:07:29.34#ibcon#read 4, iclass 39, count 0 2006.253.08:07:29.34#ibcon#about to read 5, iclass 39, count 0 2006.253.08:07:29.34#ibcon#read 5, iclass 39, count 0 2006.253.08:07:29.34#ibcon#about to read 6, iclass 39, count 0 2006.253.08:07:29.34#ibcon#read 6, iclass 39, count 0 2006.253.08:07:29.34#ibcon#end of sib2, iclass 39, count 0 2006.253.08:07:29.34#ibcon#*mode == 0, iclass 39, count 0 2006.253.08:07:29.34#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.253.08:07:29.34#ibcon#[26=FRQ=05,652.99\r\n] 2006.253.08:07:29.34#ibcon#*before write, iclass 39, count 0 2006.253.08:07:29.34#ibcon#enter sib2, iclass 39, count 0 2006.253.08:07:29.34#ibcon#flushed, iclass 39, count 0 2006.253.08:07:29.34#ibcon#about to write, iclass 39, count 0 2006.253.08:07:29.34#ibcon#wrote, iclass 39, count 0 2006.253.08:07:29.34#ibcon#about to read 3, iclass 39, count 0 2006.253.08:07:29.38#ibcon#read 3, iclass 39, count 0 2006.253.08:07:29.38#ibcon#about to read 4, iclass 39, count 0 2006.253.08:07:29.38#ibcon#read 4, iclass 39, count 0 2006.253.08:07:29.38#ibcon#about to read 5, iclass 39, count 0 2006.253.08:07:29.38#ibcon#read 5, iclass 39, count 0 2006.253.08:07:29.38#ibcon#about to read 6, iclass 39, count 0 2006.253.08:07:29.38#ibcon#read 6, iclass 39, count 0 2006.253.08:07:29.38#ibcon#end of sib2, iclass 39, count 0 2006.253.08:07:29.38#ibcon#*after write, iclass 39, count 0 2006.253.08:07:29.38#ibcon#*before return 0, iclass 39, count 0 2006.253.08:07:29.38#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.253.08:07:29.38#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.253.08:07:29.38#ibcon#about to clear, iclass 39 cls_cnt 0 2006.253.08:07:29.38#ibcon#cleared, iclass 39 cls_cnt 0 2006.253.08:07:29.38$vc4f8/va=5,7 2006.253.08:07:29.38#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.253.08:07:29.38#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.253.08:07:29.38#ibcon#ireg 11 cls_cnt 2 2006.253.08:07:29.38#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.253.08:07:29.44#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.253.08:07:29.44#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.253.08:07:29.44#ibcon#enter wrdev, iclass 3, count 2 2006.253.08:07:29.44#ibcon#first serial, iclass 3, count 2 2006.253.08:07:29.44#ibcon#enter sib2, iclass 3, count 2 2006.253.08:07:29.44#ibcon#flushed, iclass 3, count 2 2006.253.08:07:29.44#ibcon#about to write, iclass 3, count 2 2006.253.08:07:29.44#ibcon#wrote, iclass 3, count 2 2006.253.08:07:29.44#ibcon#about to read 3, iclass 3, count 2 2006.253.08:07:29.46#ibcon#read 3, iclass 3, count 2 2006.253.08:07:29.46#ibcon#about to read 4, iclass 3, count 2 2006.253.08:07:29.46#ibcon#read 4, iclass 3, count 2 2006.253.08:07:29.46#ibcon#about to read 5, iclass 3, count 2 2006.253.08:07:29.46#ibcon#read 5, iclass 3, count 2 2006.253.08:07:29.46#ibcon#about to read 6, iclass 3, count 2 2006.253.08:07:29.46#ibcon#read 6, iclass 3, count 2 2006.253.08:07:29.46#ibcon#end of sib2, iclass 3, count 2 2006.253.08:07:29.46#ibcon#*mode == 0, iclass 3, count 2 2006.253.08:07:29.46#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.253.08:07:29.46#ibcon#[25=AT05-07\r\n] 2006.253.08:07:29.46#ibcon#*before write, iclass 3, count 2 2006.253.08:07:29.46#ibcon#enter sib2, iclass 3, count 2 2006.253.08:07:29.46#ibcon#flushed, iclass 3, count 2 2006.253.08:07:29.46#ibcon#about to write, iclass 3, count 2 2006.253.08:07:29.46#ibcon#wrote, iclass 3, count 2 2006.253.08:07:29.46#ibcon#about to read 3, iclass 3, count 2 2006.253.08:07:29.49#ibcon#read 3, iclass 3, count 2 2006.253.08:07:29.49#ibcon#about to read 4, iclass 3, count 2 2006.253.08:07:29.49#ibcon#read 4, iclass 3, count 2 2006.253.08:07:29.49#ibcon#about to read 5, iclass 3, count 2 2006.253.08:07:29.49#ibcon#read 5, iclass 3, count 2 2006.253.08:07:29.49#ibcon#about to read 6, iclass 3, count 2 2006.253.08:07:29.49#ibcon#read 6, iclass 3, count 2 2006.253.08:07:29.49#ibcon#end of sib2, iclass 3, count 2 2006.253.08:07:29.49#ibcon#*after write, iclass 3, count 2 2006.253.08:07:29.49#ibcon#*before return 0, iclass 3, count 2 2006.253.08:07:29.49#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.253.08:07:29.49#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.253.08:07:29.49#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.253.08:07:29.49#ibcon#ireg 7 cls_cnt 0 2006.253.08:07:29.49#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.253.08:07:29.61#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.253.08:07:29.61#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.253.08:07:29.61#ibcon#enter wrdev, iclass 3, count 0 2006.253.08:07:29.61#ibcon#first serial, iclass 3, count 0 2006.253.08:07:29.61#ibcon#enter sib2, iclass 3, count 0 2006.253.08:07:29.61#ibcon#flushed, iclass 3, count 0 2006.253.08:07:29.61#ibcon#about to write, iclass 3, count 0 2006.253.08:07:29.61#ibcon#wrote, iclass 3, count 0 2006.253.08:07:29.61#ibcon#about to read 3, iclass 3, count 0 2006.253.08:07:29.63#ibcon#read 3, iclass 3, count 0 2006.253.08:07:29.63#ibcon#about to read 4, iclass 3, count 0 2006.253.08:07:29.63#ibcon#read 4, iclass 3, count 0 2006.253.08:07:29.63#ibcon#about to read 5, iclass 3, count 0 2006.253.08:07:29.63#ibcon#read 5, iclass 3, count 0 2006.253.08:07:29.63#ibcon#about to read 6, iclass 3, count 0 2006.253.08:07:29.63#ibcon#read 6, iclass 3, count 0 2006.253.08:07:29.63#ibcon#end of sib2, iclass 3, count 0 2006.253.08:07:29.63#ibcon#*mode == 0, iclass 3, count 0 2006.253.08:07:29.63#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.253.08:07:29.63#ibcon#[25=USB\r\n] 2006.253.08:07:29.63#ibcon#*before write, iclass 3, count 0 2006.253.08:07:29.63#ibcon#enter sib2, iclass 3, count 0 2006.253.08:07:29.63#ibcon#flushed, iclass 3, count 0 2006.253.08:07:29.63#ibcon#about to write, iclass 3, count 0 2006.253.08:07:29.63#ibcon#wrote, iclass 3, count 0 2006.253.08:07:29.63#ibcon#about to read 3, iclass 3, count 0 2006.253.08:07:29.66#ibcon#read 3, iclass 3, count 0 2006.253.08:07:29.66#ibcon#about to read 4, iclass 3, count 0 2006.253.08:07:29.66#ibcon#read 4, iclass 3, count 0 2006.253.08:07:29.66#ibcon#about to read 5, iclass 3, count 0 2006.253.08:07:29.66#ibcon#read 5, iclass 3, count 0 2006.253.08:07:29.66#ibcon#about to read 6, iclass 3, count 0 2006.253.08:07:29.66#ibcon#read 6, iclass 3, count 0 2006.253.08:07:29.66#ibcon#end of sib2, iclass 3, count 0 2006.253.08:07:29.66#ibcon#*after write, iclass 3, count 0 2006.253.08:07:29.66#ibcon#*before return 0, iclass 3, count 0 2006.253.08:07:29.66#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.253.08:07:29.66#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.253.08:07:29.66#ibcon#about to clear, iclass 3 cls_cnt 0 2006.253.08:07:29.66#ibcon#cleared, iclass 3 cls_cnt 0 2006.253.08:07:29.66$vc4f8/valo=6,772.99 2006.253.08:07:29.66#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.253.08:07:29.66#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.253.08:07:29.66#ibcon#ireg 17 cls_cnt 0 2006.253.08:07:29.66#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.253.08:07:29.66#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.253.08:07:29.66#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.253.08:07:29.66#ibcon#enter wrdev, iclass 5, count 0 2006.253.08:07:29.66#ibcon#first serial, iclass 5, count 0 2006.253.08:07:29.66#ibcon#enter sib2, iclass 5, count 0 2006.253.08:07:29.66#ibcon#flushed, iclass 5, count 0 2006.253.08:07:29.66#ibcon#about to write, iclass 5, count 0 2006.253.08:07:29.66#ibcon#wrote, iclass 5, count 0 2006.253.08:07:29.66#ibcon#about to read 3, iclass 5, count 0 2006.253.08:07:29.68#ibcon#read 3, iclass 5, count 0 2006.253.08:07:29.69#ibcon#about to read 4, iclass 5, count 0 2006.253.08:07:29.69#ibcon#read 4, iclass 5, count 0 2006.253.08:07:29.69#ibcon#about to read 5, iclass 5, count 0 2006.253.08:07:29.69#ibcon#read 5, iclass 5, count 0 2006.253.08:07:29.69#ibcon#about to read 6, iclass 5, count 0 2006.253.08:07:29.69#ibcon#read 6, iclass 5, count 0 2006.253.08:07:29.69#ibcon#end of sib2, iclass 5, count 0 2006.253.08:07:29.69#ibcon#*mode == 0, iclass 5, count 0 2006.253.08:07:29.69#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.253.08:07:29.69#ibcon#[26=FRQ=06,772.99\r\n] 2006.253.08:07:29.69#ibcon#*before write, iclass 5, count 0 2006.253.08:07:29.69#ibcon#enter sib2, iclass 5, count 0 2006.253.08:07:29.69#ibcon#flushed, iclass 5, count 0 2006.253.08:07:29.69#ibcon#about to write, iclass 5, count 0 2006.253.08:07:29.69#ibcon#wrote, iclass 5, count 0 2006.253.08:07:29.69#ibcon#about to read 3, iclass 5, count 0 2006.253.08:07:29.73#ibcon#read 3, iclass 5, count 0 2006.253.08:07:29.73#ibcon#about to read 4, iclass 5, count 0 2006.253.08:07:29.73#ibcon#read 4, iclass 5, count 0 2006.253.08:07:29.73#ibcon#about to read 5, iclass 5, count 0 2006.253.08:07:29.73#ibcon#read 5, iclass 5, count 0 2006.253.08:07:29.73#ibcon#about to read 6, iclass 5, count 0 2006.253.08:07:29.73#ibcon#read 6, iclass 5, count 0 2006.253.08:07:29.73#ibcon#end of sib2, iclass 5, count 0 2006.253.08:07:29.73#ibcon#*after write, iclass 5, count 0 2006.253.08:07:29.73#ibcon#*before return 0, iclass 5, count 0 2006.253.08:07:29.73#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.253.08:07:29.73#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.253.08:07:29.73#ibcon#about to clear, iclass 5 cls_cnt 0 2006.253.08:07:29.73#ibcon#cleared, iclass 5 cls_cnt 0 2006.253.08:07:29.73$vc4f8/va=6,7 2006.253.08:07:29.73#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.253.08:07:29.73#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.253.08:07:29.73#ibcon#ireg 11 cls_cnt 2 2006.253.08:07:29.73#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.253.08:07:29.78#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.253.08:07:29.78#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.253.08:07:29.78#ibcon#enter wrdev, iclass 7, count 2 2006.253.08:07:29.78#ibcon#first serial, iclass 7, count 2 2006.253.08:07:29.78#ibcon#enter sib2, iclass 7, count 2 2006.253.08:07:29.78#ibcon#flushed, iclass 7, count 2 2006.253.08:07:29.78#ibcon#about to write, iclass 7, count 2 2006.253.08:07:29.78#ibcon#wrote, iclass 7, count 2 2006.253.08:07:29.78#ibcon#about to read 3, iclass 7, count 2 2006.253.08:07:29.80#ibcon#read 3, iclass 7, count 2 2006.253.08:07:29.80#ibcon#about to read 4, iclass 7, count 2 2006.253.08:07:29.80#ibcon#read 4, iclass 7, count 2 2006.253.08:07:29.80#ibcon#about to read 5, iclass 7, count 2 2006.253.08:07:29.80#ibcon#read 5, iclass 7, count 2 2006.253.08:07:29.80#ibcon#about to read 6, iclass 7, count 2 2006.253.08:07:29.80#ibcon#read 6, iclass 7, count 2 2006.253.08:07:29.80#ibcon#end of sib2, iclass 7, count 2 2006.253.08:07:29.80#ibcon#*mode == 0, iclass 7, count 2 2006.253.08:07:29.80#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.253.08:07:29.80#ibcon#[25=AT06-07\r\n] 2006.253.08:07:29.80#ibcon#*before write, iclass 7, count 2 2006.253.08:07:29.80#ibcon#enter sib2, iclass 7, count 2 2006.253.08:07:29.80#ibcon#flushed, iclass 7, count 2 2006.253.08:07:29.80#ibcon#about to write, iclass 7, count 2 2006.253.08:07:29.80#ibcon#wrote, iclass 7, count 2 2006.253.08:07:29.80#ibcon#about to read 3, iclass 7, count 2 2006.253.08:07:29.83#ibcon#read 3, iclass 7, count 2 2006.253.08:07:29.83#ibcon#about to read 4, iclass 7, count 2 2006.253.08:07:29.83#ibcon#read 4, iclass 7, count 2 2006.253.08:07:29.83#ibcon#about to read 5, iclass 7, count 2 2006.253.08:07:29.83#ibcon#read 5, iclass 7, count 2 2006.253.08:07:29.83#ibcon#about to read 6, iclass 7, count 2 2006.253.08:07:29.83#ibcon#read 6, iclass 7, count 2 2006.253.08:07:29.83#ibcon#end of sib2, iclass 7, count 2 2006.253.08:07:29.83#ibcon#*after write, iclass 7, count 2 2006.253.08:07:29.83#ibcon#*before return 0, iclass 7, count 2 2006.253.08:07:29.83#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.253.08:07:29.83#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.253.08:07:29.83#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.253.08:07:29.83#ibcon#ireg 7 cls_cnt 0 2006.253.08:07:29.83#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.253.08:07:29.95#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.253.08:07:29.95#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.253.08:07:29.95#ibcon#enter wrdev, iclass 7, count 0 2006.253.08:07:29.95#ibcon#first serial, iclass 7, count 0 2006.253.08:07:29.95#ibcon#enter sib2, iclass 7, count 0 2006.253.08:07:29.95#ibcon#flushed, iclass 7, count 0 2006.253.08:07:29.95#ibcon#about to write, iclass 7, count 0 2006.253.08:07:29.95#ibcon#wrote, iclass 7, count 0 2006.253.08:07:29.95#ibcon#about to read 3, iclass 7, count 0 2006.253.08:07:29.97#ibcon#read 3, iclass 7, count 0 2006.253.08:07:29.97#ibcon#about to read 4, iclass 7, count 0 2006.253.08:07:29.97#ibcon#read 4, iclass 7, count 0 2006.253.08:07:29.97#ibcon#about to read 5, iclass 7, count 0 2006.253.08:07:29.97#ibcon#read 5, iclass 7, count 0 2006.253.08:07:29.97#ibcon#about to read 6, iclass 7, count 0 2006.253.08:07:29.97#ibcon#read 6, iclass 7, count 0 2006.253.08:07:29.97#ibcon#end of sib2, iclass 7, count 0 2006.253.08:07:29.97#ibcon#*mode == 0, iclass 7, count 0 2006.253.08:07:29.97#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.253.08:07:29.97#ibcon#[25=USB\r\n] 2006.253.08:07:29.97#ibcon#*before write, iclass 7, count 0 2006.253.08:07:29.97#ibcon#enter sib2, iclass 7, count 0 2006.253.08:07:29.97#ibcon#flushed, iclass 7, count 0 2006.253.08:07:29.97#ibcon#about to write, iclass 7, count 0 2006.253.08:07:29.97#ibcon#wrote, iclass 7, count 0 2006.253.08:07:29.97#ibcon#about to read 3, iclass 7, count 0 2006.253.08:07:30.00#ibcon#read 3, iclass 7, count 0 2006.253.08:07:30.00#ibcon#about to read 4, iclass 7, count 0 2006.253.08:07:30.00#ibcon#read 4, iclass 7, count 0 2006.253.08:07:30.00#ibcon#about to read 5, iclass 7, count 0 2006.253.08:07:30.00#ibcon#read 5, iclass 7, count 0 2006.253.08:07:30.00#ibcon#about to read 6, iclass 7, count 0 2006.253.08:07:30.00#ibcon#read 6, iclass 7, count 0 2006.253.08:07:30.00#ibcon#end of sib2, iclass 7, count 0 2006.253.08:07:30.00#ibcon#*after write, iclass 7, count 0 2006.253.08:07:30.00#ibcon#*before return 0, iclass 7, count 0 2006.253.08:07:30.00#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.253.08:07:30.00#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.253.08:07:30.00#ibcon#about to clear, iclass 7 cls_cnt 0 2006.253.08:07:30.00#ibcon#cleared, iclass 7 cls_cnt 0 2006.253.08:07:30.00$vc4f8/valo=7,832.99 2006.253.08:07:30.00#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.253.08:07:30.00#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.253.08:07:30.00#ibcon#ireg 17 cls_cnt 0 2006.253.08:07:30.00#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.253.08:07:30.00#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.253.08:07:30.00#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.253.08:07:30.00#ibcon#enter wrdev, iclass 11, count 0 2006.253.08:07:30.00#ibcon#first serial, iclass 11, count 0 2006.253.08:07:30.00#ibcon#enter sib2, iclass 11, count 0 2006.253.08:07:30.00#ibcon#flushed, iclass 11, count 0 2006.253.08:07:30.00#ibcon#about to write, iclass 11, count 0 2006.253.08:07:30.00#ibcon#wrote, iclass 11, count 0 2006.253.08:07:30.00#ibcon#about to read 3, iclass 11, count 0 2006.253.08:07:30.02#ibcon#read 3, iclass 11, count 0 2006.253.08:07:30.02#ibcon#about to read 4, iclass 11, count 0 2006.253.08:07:30.02#ibcon#read 4, iclass 11, count 0 2006.253.08:07:30.02#ibcon#about to read 5, iclass 11, count 0 2006.253.08:07:30.02#ibcon#read 5, iclass 11, count 0 2006.253.08:07:30.02#ibcon#about to read 6, iclass 11, count 0 2006.253.08:07:30.02#ibcon#read 6, iclass 11, count 0 2006.253.08:07:30.02#ibcon#end of sib2, iclass 11, count 0 2006.253.08:07:30.02#ibcon#*mode == 0, iclass 11, count 0 2006.253.08:07:30.02#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.253.08:07:30.02#ibcon#[26=FRQ=07,832.99\r\n] 2006.253.08:07:30.02#ibcon#*before write, iclass 11, count 0 2006.253.08:07:30.02#ibcon#enter sib2, iclass 11, count 0 2006.253.08:07:30.02#ibcon#flushed, iclass 11, count 0 2006.253.08:07:30.02#ibcon#about to write, iclass 11, count 0 2006.253.08:07:30.02#ibcon#wrote, iclass 11, count 0 2006.253.08:07:30.02#ibcon#about to read 3, iclass 11, count 0 2006.253.08:07:30.06#ibcon#read 3, iclass 11, count 0 2006.253.08:07:30.06#ibcon#about to read 4, iclass 11, count 0 2006.253.08:07:30.06#ibcon#read 4, iclass 11, count 0 2006.253.08:07:30.06#ibcon#about to read 5, iclass 11, count 0 2006.253.08:07:30.06#ibcon#read 5, iclass 11, count 0 2006.253.08:07:30.06#ibcon#about to read 6, iclass 11, count 0 2006.253.08:07:30.06#ibcon#read 6, iclass 11, count 0 2006.253.08:07:30.06#ibcon#end of sib2, iclass 11, count 0 2006.253.08:07:30.06#ibcon#*after write, iclass 11, count 0 2006.253.08:07:30.06#ibcon#*before return 0, iclass 11, count 0 2006.253.08:07:30.06#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.253.08:07:30.06#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.253.08:07:30.06#ibcon#about to clear, iclass 11 cls_cnt 0 2006.253.08:07:30.06#ibcon#cleared, iclass 11 cls_cnt 0 2006.253.08:07:30.06$vc4f8/va=7,7 2006.253.08:07:30.06#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.253.08:07:30.06#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.253.08:07:30.06#ibcon#ireg 11 cls_cnt 2 2006.253.08:07:30.06#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.253.08:07:30.12#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.253.08:07:30.12#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.253.08:07:30.12#ibcon#enter wrdev, iclass 13, count 2 2006.253.08:07:30.12#ibcon#first serial, iclass 13, count 2 2006.253.08:07:30.12#ibcon#enter sib2, iclass 13, count 2 2006.253.08:07:30.12#ibcon#flushed, iclass 13, count 2 2006.253.08:07:30.12#ibcon#about to write, iclass 13, count 2 2006.253.08:07:30.12#ibcon#wrote, iclass 13, count 2 2006.253.08:07:30.12#ibcon#about to read 3, iclass 13, count 2 2006.253.08:07:30.14#ibcon#read 3, iclass 13, count 2 2006.253.08:07:30.14#ibcon#about to read 4, iclass 13, count 2 2006.253.08:07:30.14#ibcon#read 4, iclass 13, count 2 2006.253.08:07:30.14#ibcon#about to read 5, iclass 13, count 2 2006.253.08:07:30.14#ibcon#read 5, iclass 13, count 2 2006.253.08:07:30.14#ibcon#about to read 6, iclass 13, count 2 2006.253.08:07:30.14#ibcon#read 6, iclass 13, count 2 2006.253.08:07:30.14#ibcon#end of sib2, iclass 13, count 2 2006.253.08:07:30.14#ibcon#*mode == 0, iclass 13, count 2 2006.253.08:07:30.14#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.253.08:07:30.14#ibcon#[25=AT07-07\r\n] 2006.253.08:07:30.14#ibcon#*before write, iclass 13, count 2 2006.253.08:07:30.14#ibcon#enter sib2, iclass 13, count 2 2006.253.08:07:30.14#ibcon#flushed, iclass 13, count 2 2006.253.08:07:30.14#ibcon#about to write, iclass 13, count 2 2006.253.08:07:30.14#ibcon#wrote, iclass 13, count 2 2006.253.08:07:30.14#ibcon#about to read 3, iclass 13, count 2 2006.253.08:07:30.17#ibcon#read 3, iclass 13, count 2 2006.253.08:07:30.17#ibcon#about to read 4, iclass 13, count 2 2006.253.08:07:30.17#ibcon#read 4, iclass 13, count 2 2006.253.08:07:30.17#ibcon#about to read 5, iclass 13, count 2 2006.253.08:07:30.17#ibcon#read 5, iclass 13, count 2 2006.253.08:07:30.17#ibcon#about to read 6, iclass 13, count 2 2006.253.08:07:30.17#ibcon#read 6, iclass 13, count 2 2006.253.08:07:30.17#ibcon#end of sib2, iclass 13, count 2 2006.253.08:07:30.17#ibcon#*after write, iclass 13, count 2 2006.253.08:07:30.17#ibcon#*before return 0, iclass 13, count 2 2006.253.08:07:30.17#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.253.08:07:30.17#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.253.08:07:30.17#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.253.08:07:30.17#ibcon#ireg 7 cls_cnt 0 2006.253.08:07:30.17#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.253.08:07:30.29#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.253.08:07:30.29#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.253.08:07:30.29#ibcon#enter wrdev, iclass 13, count 0 2006.253.08:07:30.29#ibcon#first serial, iclass 13, count 0 2006.253.08:07:30.29#ibcon#enter sib2, iclass 13, count 0 2006.253.08:07:30.29#ibcon#flushed, iclass 13, count 0 2006.253.08:07:30.29#ibcon#about to write, iclass 13, count 0 2006.253.08:07:30.29#ibcon#wrote, iclass 13, count 0 2006.253.08:07:30.29#ibcon#about to read 3, iclass 13, count 0 2006.253.08:07:30.31#ibcon#read 3, iclass 13, count 0 2006.253.08:07:30.31#ibcon#about to read 4, iclass 13, count 0 2006.253.08:07:30.31#ibcon#read 4, iclass 13, count 0 2006.253.08:07:30.31#ibcon#about to read 5, iclass 13, count 0 2006.253.08:07:30.31#ibcon#read 5, iclass 13, count 0 2006.253.08:07:30.31#ibcon#about to read 6, iclass 13, count 0 2006.253.08:07:30.31#ibcon#read 6, iclass 13, count 0 2006.253.08:07:30.31#ibcon#end of sib2, iclass 13, count 0 2006.253.08:07:30.31#ibcon#*mode == 0, iclass 13, count 0 2006.253.08:07:30.31#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.253.08:07:30.31#ibcon#[25=USB\r\n] 2006.253.08:07:30.31#ibcon#*before write, iclass 13, count 0 2006.253.08:07:30.31#ibcon#enter sib2, iclass 13, count 0 2006.253.08:07:30.31#ibcon#flushed, iclass 13, count 0 2006.253.08:07:30.31#ibcon#about to write, iclass 13, count 0 2006.253.08:07:30.31#ibcon#wrote, iclass 13, count 0 2006.253.08:07:30.31#ibcon#about to read 3, iclass 13, count 0 2006.253.08:07:30.34#ibcon#read 3, iclass 13, count 0 2006.253.08:07:30.34#ibcon#about to read 4, iclass 13, count 0 2006.253.08:07:30.34#ibcon#read 4, iclass 13, count 0 2006.253.08:07:30.34#ibcon#about to read 5, iclass 13, count 0 2006.253.08:07:30.34#ibcon#read 5, iclass 13, count 0 2006.253.08:07:30.34#ibcon#about to read 6, iclass 13, count 0 2006.253.08:07:30.34#ibcon#read 6, iclass 13, count 0 2006.253.08:07:30.34#ibcon#end of sib2, iclass 13, count 0 2006.253.08:07:30.34#ibcon#*after write, iclass 13, count 0 2006.253.08:07:30.34#ibcon#*before return 0, iclass 13, count 0 2006.253.08:07:30.34#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.253.08:07:30.34#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.253.08:07:30.34#ibcon#about to clear, iclass 13 cls_cnt 0 2006.253.08:07:30.34#ibcon#cleared, iclass 13 cls_cnt 0 2006.253.08:07:30.34$vc4f8/valo=8,852.99 2006.253.08:07:30.34#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.253.08:07:30.34#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.253.08:07:30.34#ibcon#ireg 17 cls_cnt 0 2006.253.08:07:30.34#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.253.08:07:30.34#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.253.08:07:30.34#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.253.08:07:30.34#ibcon#enter wrdev, iclass 15, count 0 2006.253.08:07:30.34#ibcon#first serial, iclass 15, count 0 2006.253.08:07:30.34#ibcon#enter sib2, iclass 15, count 0 2006.253.08:07:30.34#ibcon#flushed, iclass 15, count 0 2006.253.08:07:30.34#ibcon#about to write, iclass 15, count 0 2006.253.08:07:30.34#ibcon#wrote, iclass 15, count 0 2006.253.08:07:30.34#ibcon#about to read 3, iclass 15, count 0 2006.253.08:07:30.36#ibcon#read 3, iclass 15, count 0 2006.253.08:07:30.36#ibcon#about to read 4, iclass 15, count 0 2006.253.08:07:30.36#ibcon#read 4, iclass 15, count 0 2006.253.08:07:30.37#ibcon#about to read 5, iclass 15, count 0 2006.253.08:07:30.37#ibcon#read 5, iclass 15, count 0 2006.253.08:07:30.37#ibcon#about to read 6, iclass 15, count 0 2006.253.08:07:30.37#ibcon#read 6, iclass 15, count 0 2006.253.08:07:30.37#ibcon#end of sib2, iclass 15, count 0 2006.253.08:07:30.37#ibcon#*mode == 0, iclass 15, count 0 2006.253.08:07:30.37#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.253.08:07:30.37#ibcon#[26=FRQ=08,852.99\r\n] 2006.253.08:07:30.37#ibcon#*before write, iclass 15, count 0 2006.253.08:07:30.37#ibcon#enter sib2, iclass 15, count 0 2006.253.08:07:30.37#ibcon#flushed, iclass 15, count 0 2006.253.08:07:30.37#ibcon#about to write, iclass 15, count 0 2006.253.08:07:30.37#ibcon#wrote, iclass 15, count 0 2006.253.08:07:30.37#ibcon#about to read 3, iclass 15, count 0 2006.253.08:07:30.41#ibcon#read 3, iclass 15, count 0 2006.253.08:07:30.41#ibcon#about to read 4, iclass 15, count 0 2006.253.08:07:30.41#ibcon#read 4, iclass 15, count 0 2006.253.08:07:30.41#ibcon#about to read 5, iclass 15, count 0 2006.253.08:07:30.41#ibcon#read 5, iclass 15, count 0 2006.253.08:07:30.41#ibcon#about to read 6, iclass 15, count 0 2006.253.08:07:30.41#ibcon#read 6, iclass 15, count 0 2006.253.08:07:30.41#ibcon#end of sib2, iclass 15, count 0 2006.253.08:07:30.41#ibcon#*after write, iclass 15, count 0 2006.253.08:07:30.41#ibcon#*before return 0, iclass 15, count 0 2006.253.08:07:30.41#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.253.08:07:30.41#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.253.08:07:30.41#ibcon#about to clear, iclass 15 cls_cnt 0 2006.253.08:07:30.41#ibcon#cleared, iclass 15 cls_cnt 0 2006.253.08:07:30.41$vc4f8/va=8,7 2006.253.08:07:30.41#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.253.08:07:30.41#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.253.08:07:30.41#ibcon#ireg 11 cls_cnt 2 2006.253.08:07:30.41#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.253.08:07:30.46#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.253.08:07:30.46#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.253.08:07:30.46#ibcon#enter wrdev, iclass 17, count 2 2006.253.08:07:30.46#ibcon#first serial, iclass 17, count 2 2006.253.08:07:30.46#ibcon#enter sib2, iclass 17, count 2 2006.253.08:07:30.46#ibcon#flushed, iclass 17, count 2 2006.253.08:07:30.46#ibcon#about to write, iclass 17, count 2 2006.253.08:07:30.46#ibcon#wrote, iclass 17, count 2 2006.253.08:07:30.46#ibcon#about to read 3, iclass 17, count 2 2006.253.08:07:30.48#ibcon#read 3, iclass 17, count 2 2006.253.08:07:30.48#ibcon#about to read 4, iclass 17, count 2 2006.253.08:07:30.48#ibcon#read 4, iclass 17, count 2 2006.253.08:07:30.48#ibcon#about to read 5, iclass 17, count 2 2006.253.08:07:30.48#ibcon#read 5, iclass 17, count 2 2006.253.08:07:30.48#ibcon#about to read 6, iclass 17, count 2 2006.253.08:07:30.48#ibcon#read 6, iclass 17, count 2 2006.253.08:07:30.48#ibcon#end of sib2, iclass 17, count 2 2006.253.08:07:30.48#ibcon#*mode == 0, iclass 17, count 2 2006.253.08:07:30.48#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.253.08:07:30.48#ibcon#[25=AT08-07\r\n] 2006.253.08:07:30.48#ibcon#*before write, iclass 17, count 2 2006.253.08:07:30.48#ibcon#enter sib2, iclass 17, count 2 2006.253.08:07:30.48#ibcon#flushed, iclass 17, count 2 2006.253.08:07:30.48#ibcon#about to write, iclass 17, count 2 2006.253.08:07:30.48#ibcon#wrote, iclass 17, count 2 2006.253.08:07:30.48#ibcon#about to read 3, iclass 17, count 2 2006.253.08:07:30.51#ibcon#read 3, iclass 17, count 2 2006.253.08:07:30.51#ibcon#about to read 4, iclass 17, count 2 2006.253.08:07:30.51#ibcon#read 4, iclass 17, count 2 2006.253.08:07:30.51#ibcon#about to read 5, iclass 17, count 2 2006.253.08:07:30.51#ibcon#read 5, iclass 17, count 2 2006.253.08:07:30.51#ibcon#about to read 6, iclass 17, count 2 2006.253.08:07:30.51#ibcon#read 6, iclass 17, count 2 2006.253.08:07:30.51#ibcon#end of sib2, iclass 17, count 2 2006.253.08:07:30.51#ibcon#*after write, iclass 17, count 2 2006.253.08:07:30.51#ibcon#*before return 0, iclass 17, count 2 2006.253.08:07:30.51#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.253.08:07:30.51#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.253.08:07:30.51#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.253.08:07:30.51#ibcon#ireg 7 cls_cnt 0 2006.253.08:07:30.51#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.253.08:07:30.63#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.253.08:07:30.63#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.253.08:07:30.63#ibcon#enter wrdev, iclass 17, count 0 2006.253.08:07:30.63#ibcon#first serial, iclass 17, count 0 2006.253.08:07:30.63#ibcon#enter sib2, iclass 17, count 0 2006.253.08:07:30.63#ibcon#flushed, iclass 17, count 0 2006.253.08:07:30.63#ibcon#about to write, iclass 17, count 0 2006.253.08:07:30.63#ibcon#wrote, iclass 17, count 0 2006.253.08:07:30.63#ibcon#about to read 3, iclass 17, count 0 2006.253.08:07:30.65#ibcon#read 3, iclass 17, count 0 2006.253.08:07:30.65#ibcon#about to read 4, iclass 17, count 0 2006.253.08:07:30.65#ibcon#read 4, iclass 17, count 0 2006.253.08:07:30.65#ibcon#about to read 5, iclass 17, count 0 2006.253.08:07:30.65#ibcon#read 5, iclass 17, count 0 2006.253.08:07:30.65#ibcon#about to read 6, iclass 17, count 0 2006.253.08:07:30.65#ibcon#read 6, iclass 17, count 0 2006.253.08:07:30.65#ibcon#end of sib2, iclass 17, count 0 2006.253.08:07:30.65#ibcon#*mode == 0, iclass 17, count 0 2006.253.08:07:30.65#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.253.08:07:30.65#ibcon#[25=USB\r\n] 2006.253.08:07:30.65#ibcon#*before write, iclass 17, count 0 2006.253.08:07:30.65#ibcon#enter sib2, iclass 17, count 0 2006.253.08:07:30.65#ibcon#flushed, iclass 17, count 0 2006.253.08:07:30.65#ibcon#about to write, iclass 17, count 0 2006.253.08:07:30.65#ibcon#wrote, iclass 17, count 0 2006.253.08:07:30.65#ibcon#about to read 3, iclass 17, count 0 2006.253.08:07:30.68#ibcon#read 3, iclass 17, count 0 2006.253.08:07:30.68#ibcon#about to read 4, iclass 17, count 0 2006.253.08:07:30.68#ibcon#read 4, iclass 17, count 0 2006.253.08:07:30.68#ibcon#about to read 5, iclass 17, count 0 2006.253.08:07:30.68#ibcon#read 5, iclass 17, count 0 2006.253.08:07:30.68#ibcon#about to read 6, iclass 17, count 0 2006.253.08:07:30.68#ibcon#read 6, iclass 17, count 0 2006.253.08:07:30.68#ibcon#end of sib2, iclass 17, count 0 2006.253.08:07:30.68#ibcon#*after write, iclass 17, count 0 2006.253.08:07:30.68#ibcon#*before return 0, iclass 17, count 0 2006.253.08:07:30.68#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.253.08:07:30.68#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.253.08:07:30.68#ibcon#about to clear, iclass 17 cls_cnt 0 2006.253.08:07:30.68#ibcon#cleared, iclass 17 cls_cnt 0 2006.253.08:07:30.68$vc4f8/vblo=1,632.99 2006.253.08:07:30.68#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.253.08:07:30.68#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.253.08:07:30.68#ibcon#ireg 17 cls_cnt 0 2006.253.08:07:30.68#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.253.08:07:30.68#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.253.08:07:30.68#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.253.08:07:30.68#ibcon#enter wrdev, iclass 19, count 0 2006.253.08:07:30.68#ibcon#first serial, iclass 19, count 0 2006.253.08:07:30.68#ibcon#enter sib2, iclass 19, count 0 2006.253.08:07:30.68#ibcon#flushed, iclass 19, count 0 2006.253.08:07:30.68#ibcon#about to write, iclass 19, count 0 2006.253.08:07:30.68#ibcon#wrote, iclass 19, count 0 2006.253.08:07:30.68#ibcon#about to read 3, iclass 19, count 0 2006.253.08:07:30.70#ibcon#read 3, iclass 19, count 0 2006.253.08:07:30.70#ibcon#about to read 4, iclass 19, count 0 2006.253.08:07:30.70#ibcon#read 4, iclass 19, count 0 2006.253.08:07:30.70#ibcon#about to read 5, iclass 19, count 0 2006.253.08:07:30.70#ibcon#read 5, iclass 19, count 0 2006.253.08:07:30.70#ibcon#about to read 6, iclass 19, count 0 2006.253.08:07:30.70#ibcon#read 6, iclass 19, count 0 2006.253.08:07:30.70#ibcon#end of sib2, iclass 19, count 0 2006.253.08:07:30.70#ibcon#*mode == 0, iclass 19, count 0 2006.253.08:07:30.70#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.253.08:07:30.70#ibcon#[28=FRQ=01,632.99\r\n] 2006.253.08:07:30.70#ibcon#*before write, iclass 19, count 0 2006.253.08:07:30.70#ibcon#enter sib2, iclass 19, count 0 2006.253.08:07:30.70#ibcon#flushed, iclass 19, count 0 2006.253.08:07:30.70#ibcon#about to write, iclass 19, count 0 2006.253.08:07:30.70#ibcon#wrote, iclass 19, count 0 2006.253.08:07:30.70#ibcon#about to read 3, iclass 19, count 0 2006.253.08:07:30.74#ibcon#read 3, iclass 19, count 0 2006.253.08:07:30.74#ibcon#about to read 4, iclass 19, count 0 2006.253.08:07:30.74#ibcon#read 4, iclass 19, count 0 2006.253.08:07:30.74#ibcon#about to read 5, iclass 19, count 0 2006.253.08:07:30.74#ibcon#read 5, iclass 19, count 0 2006.253.08:07:30.74#ibcon#about to read 6, iclass 19, count 0 2006.253.08:07:30.74#ibcon#read 6, iclass 19, count 0 2006.253.08:07:30.74#ibcon#end of sib2, iclass 19, count 0 2006.253.08:07:30.74#ibcon#*after write, iclass 19, count 0 2006.253.08:07:30.74#ibcon#*before return 0, iclass 19, count 0 2006.253.08:07:30.74#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.253.08:07:30.74#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.253.08:07:30.74#ibcon#about to clear, iclass 19 cls_cnt 0 2006.253.08:07:30.74#ibcon#cleared, iclass 19 cls_cnt 0 2006.253.08:07:30.74$vc4f8/vb=1,4 2006.253.08:07:30.74#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.253.08:07:30.74#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.253.08:07:30.74#ibcon#ireg 11 cls_cnt 2 2006.253.08:07:30.74#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.253.08:07:30.74#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.253.08:07:30.74#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.253.08:07:30.74#ibcon#enter wrdev, iclass 21, count 2 2006.253.08:07:30.74#ibcon#first serial, iclass 21, count 2 2006.253.08:07:30.74#ibcon#enter sib2, iclass 21, count 2 2006.253.08:07:30.74#ibcon#flushed, iclass 21, count 2 2006.253.08:07:30.74#ibcon#about to write, iclass 21, count 2 2006.253.08:07:30.74#ibcon#wrote, iclass 21, count 2 2006.253.08:07:30.74#ibcon#about to read 3, iclass 21, count 2 2006.253.08:07:30.76#ibcon#read 3, iclass 21, count 2 2006.253.08:07:30.76#ibcon#about to read 4, iclass 21, count 2 2006.253.08:07:30.76#ibcon#read 4, iclass 21, count 2 2006.253.08:07:30.76#ibcon#about to read 5, iclass 21, count 2 2006.253.08:07:30.76#ibcon#read 5, iclass 21, count 2 2006.253.08:07:30.76#ibcon#about to read 6, iclass 21, count 2 2006.253.08:07:30.76#ibcon#read 6, iclass 21, count 2 2006.253.08:07:30.76#ibcon#end of sib2, iclass 21, count 2 2006.253.08:07:30.76#ibcon#*mode == 0, iclass 21, count 2 2006.253.08:07:30.76#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.253.08:07:30.76#ibcon#[27=AT01-04\r\n] 2006.253.08:07:30.76#ibcon#*before write, iclass 21, count 2 2006.253.08:07:30.76#ibcon#enter sib2, iclass 21, count 2 2006.253.08:07:30.76#ibcon#flushed, iclass 21, count 2 2006.253.08:07:30.76#ibcon#about to write, iclass 21, count 2 2006.253.08:07:30.76#ibcon#wrote, iclass 21, count 2 2006.253.08:07:30.76#ibcon#about to read 3, iclass 21, count 2 2006.253.08:07:30.79#ibcon#read 3, iclass 21, count 2 2006.253.08:07:30.79#ibcon#about to read 4, iclass 21, count 2 2006.253.08:07:30.79#ibcon#read 4, iclass 21, count 2 2006.253.08:07:30.79#ibcon#about to read 5, iclass 21, count 2 2006.253.08:07:30.79#ibcon#read 5, iclass 21, count 2 2006.253.08:07:30.79#ibcon#about to read 6, iclass 21, count 2 2006.253.08:07:30.79#ibcon#read 6, iclass 21, count 2 2006.253.08:07:30.79#ibcon#end of sib2, iclass 21, count 2 2006.253.08:07:30.79#ibcon#*after write, iclass 21, count 2 2006.253.08:07:30.79#ibcon#*before return 0, iclass 21, count 2 2006.253.08:07:30.79#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.253.08:07:30.79#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.253.08:07:30.79#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.253.08:07:30.79#ibcon#ireg 7 cls_cnt 0 2006.253.08:07:30.79#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.253.08:07:30.91#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.253.08:07:30.91#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.253.08:07:30.91#ibcon#enter wrdev, iclass 21, count 0 2006.253.08:07:30.91#ibcon#first serial, iclass 21, count 0 2006.253.08:07:30.91#ibcon#enter sib2, iclass 21, count 0 2006.253.08:07:30.91#ibcon#flushed, iclass 21, count 0 2006.253.08:07:30.91#ibcon#about to write, iclass 21, count 0 2006.253.08:07:30.91#ibcon#wrote, iclass 21, count 0 2006.253.08:07:30.91#ibcon#about to read 3, iclass 21, count 0 2006.253.08:07:30.93#ibcon#read 3, iclass 21, count 0 2006.253.08:07:30.93#ibcon#about to read 4, iclass 21, count 0 2006.253.08:07:30.93#ibcon#read 4, iclass 21, count 0 2006.253.08:07:30.93#ibcon#about to read 5, iclass 21, count 0 2006.253.08:07:30.93#ibcon#read 5, iclass 21, count 0 2006.253.08:07:30.93#ibcon#about to read 6, iclass 21, count 0 2006.253.08:07:30.93#ibcon#read 6, iclass 21, count 0 2006.253.08:07:30.93#ibcon#end of sib2, iclass 21, count 0 2006.253.08:07:30.93#ibcon#*mode == 0, iclass 21, count 0 2006.253.08:07:30.93#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.253.08:07:30.93#ibcon#[27=USB\r\n] 2006.253.08:07:30.93#ibcon#*before write, iclass 21, count 0 2006.253.08:07:30.93#ibcon#enter sib2, iclass 21, count 0 2006.253.08:07:30.93#ibcon#flushed, iclass 21, count 0 2006.253.08:07:30.93#ibcon#about to write, iclass 21, count 0 2006.253.08:07:30.93#ibcon#wrote, iclass 21, count 0 2006.253.08:07:30.93#ibcon#about to read 3, iclass 21, count 0 2006.253.08:07:30.96#ibcon#read 3, iclass 21, count 0 2006.253.08:07:30.96#ibcon#about to read 4, iclass 21, count 0 2006.253.08:07:30.96#ibcon#read 4, iclass 21, count 0 2006.253.08:07:30.96#ibcon#about to read 5, iclass 21, count 0 2006.253.08:07:30.96#ibcon#read 5, iclass 21, count 0 2006.253.08:07:30.96#ibcon#about to read 6, iclass 21, count 0 2006.253.08:07:30.96#ibcon#read 6, iclass 21, count 0 2006.253.08:07:30.96#ibcon#end of sib2, iclass 21, count 0 2006.253.08:07:30.96#ibcon#*after write, iclass 21, count 0 2006.253.08:07:30.96#ibcon#*before return 0, iclass 21, count 0 2006.253.08:07:30.96#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.253.08:07:30.96#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.253.08:07:30.96#ibcon#about to clear, iclass 21 cls_cnt 0 2006.253.08:07:30.96#ibcon#cleared, iclass 21 cls_cnt 0 2006.253.08:07:30.96$vc4f8/vblo=2,640.99 2006.253.08:07:30.96#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.253.08:07:30.96#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.253.08:07:30.96#ibcon#ireg 17 cls_cnt 0 2006.253.08:07:30.96#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.253.08:07:30.96#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.253.08:07:30.96#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.253.08:07:30.96#ibcon#enter wrdev, iclass 23, count 0 2006.253.08:07:30.96#ibcon#first serial, iclass 23, count 0 2006.253.08:07:30.96#ibcon#enter sib2, iclass 23, count 0 2006.253.08:07:30.96#ibcon#flushed, iclass 23, count 0 2006.253.08:07:30.96#ibcon#about to write, iclass 23, count 0 2006.253.08:07:30.96#ibcon#wrote, iclass 23, count 0 2006.253.08:07:30.96#ibcon#about to read 3, iclass 23, count 0 2006.253.08:07:30.98#ibcon#read 3, iclass 23, count 0 2006.253.08:07:30.98#ibcon#about to read 4, iclass 23, count 0 2006.253.08:07:30.99#ibcon#read 4, iclass 23, count 0 2006.253.08:07:30.99#ibcon#about to read 5, iclass 23, count 0 2006.253.08:07:30.99#ibcon#read 5, iclass 23, count 0 2006.253.08:07:30.99#ibcon#about to read 6, iclass 23, count 0 2006.253.08:07:30.99#ibcon#read 6, iclass 23, count 0 2006.253.08:07:30.99#ibcon#end of sib2, iclass 23, count 0 2006.253.08:07:30.99#ibcon#*mode == 0, iclass 23, count 0 2006.253.08:07:30.99#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.253.08:07:30.99#ibcon#[28=FRQ=02,640.99\r\n] 2006.253.08:07:30.99#ibcon#*before write, iclass 23, count 0 2006.253.08:07:30.99#ibcon#enter sib2, iclass 23, count 0 2006.253.08:07:30.99#ibcon#flushed, iclass 23, count 0 2006.253.08:07:30.99#ibcon#about to write, iclass 23, count 0 2006.253.08:07:30.99#ibcon#wrote, iclass 23, count 0 2006.253.08:07:30.99#ibcon#about to read 3, iclass 23, count 0 2006.253.08:07:31.03#ibcon#read 3, iclass 23, count 0 2006.253.08:07:31.03#ibcon#about to read 4, iclass 23, count 0 2006.253.08:07:31.03#ibcon#read 4, iclass 23, count 0 2006.253.08:07:31.03#ibcon#about to read 5, iclass 23, count 0 2006.253.08:07:31.03#ibcon#read 5, iclass 23, count 0 2006.253.08:07:31.03#ibcon#about to read 6, iclass 23, count 0 2006.253.08:07:31.03#ibcon#read 6, iclass 23, count 0 2006.253.08:07:31.03#ibcon#end of sib2, iclass 23, count 0 2006.253.08:07:31.03#ibcon#*after write, iclass 23, count 0 2006.253.08:07:31.03#ibcon#*before return 0, iclass 23, count 0 2006.253.08:07:31.03#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.253.08:07:31.03#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.253.08:07:31.03#ibcon#about to clear, iclass 23 cls_cnt 0 2006.253.08:07:31.03#ibcon#cleared, iclass 23 cls_cnt 0 2006.253.08:07:31.03$vc4f8/vb=2,5 2006.253.08:07:31.03#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.253.08:07:31.03#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.253.08:07:31.03#ibcon#ireg 11 cls_cnt 2 2006.253.08:07:31.03#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.253.08:07:31.08#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.253.08:07:31.08#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.253.08:07:31.08#ibcon#enter wrdev, iclass 25, count 2 2006.253.08:07:31.08#ibcon#first serial, iclass 25, count 2 2006.253.08:07:31.08#ibcon#enter sib2, iclass 25, count 2 2006.253.08:07:31.08#ibcon#flushed, iclass 25, count 2 2006.253.08:07:31.08#ibcon#about to write, iclass 25, count 2 2006.253.08:07:31.08#ibcon#wrote, iclass 25, count 2 2006.253.08:07:31.08#ibcon#about to read 3, iclass 25, count 2 2006.253.08:07:31.10#ibcon#read 3, iclass 25, count 2 2006.253.08:07:31.10#ibcon#about to read 4, iclass 25, count 2 2006.253.08:07:31.10#ibcon#read 4, iclass 25, count 2 2006.253.08:07:31.10#ibcon#about to read 5, iclass 25, count 2 2006.253.08:07:31.10#ibcon#read 5, iclass 25, count 2 2006.253.08:07:31.10#ibcon#about to read 6, iclass 25, count 2 2006.253.08:07:31.10#ibcon#read 6, iclass 25, count 2 2006.253.08:07:31.10#ibcon#end of sib2, iclass 25, count 2 2006.253.08:07:31.10#ibcon#*mode == 0, iclass 25, count 2 2006.253.08:07:31.10#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.253.08:07:31.10#ibcon#[27=AT02-05\r\n] 2006.253.08:07:31.10#ibcon#*before write, iclass 25, count 2 2006.253.08:07:31.10#ibcon#enter sib2, iclass 25, count 2 2006.253.08:07:31.10#ibcon#flushed, iclass 25, count 2 2006.253.08:07:31.10#ibcon#about to write, iclass 25, count 2 2006.253.08:07:31.10#ibcon#wrote, iclass 25, count 2 2006.253.08:07:31.10#ibcon#about to read 3, iclass 25, count 2 2006.253.08:07:31.13#ibcon#read 3, iclass 25, count 2 2006.253.08:07:31.13#ibcon#about to read 4, iclass 25, count 2 2006.253.08:07:31.13#ibcon#read 4, iclass 25, count 2 2006.253.08:07:31.13#ibcon#about to read 5, iclass 25, count 2 2006.253.08:07:31.13#ibcon#read 5, iclass 25, count 2 2006.253.08:07:31.13#ibcon#about to read 6, iclass 25, count 2 2006.253.08:07:31.13#ibcon#read 6, iclass 25, count 2 2006.253.08:07:31.13#ibcon#end of sib2, iclass 25, count 2 2006.253.08:07:31.13#ibcon#*after write, iclass 25, count 2 2006.253.08:07:31.13#ibcon#*before return 0, iclass 25, count 2 2006.253.08:07:31.13#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.253.08:07:31.13#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.253.08:07:31.13#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.253.08:07:31.13#ibcon#ireg 7 cls_cnt 0 2006.253.08:07:31.13#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.253.08:07:31.25#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.253.08:07:31.25#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.253.08:07:31.25#ibcon#enter wrdev, iclass 25, count 0 2006.253.08:07:31.25#ibcon#first serial, iclass 25, count 0 2006.253.08:07:31.25#ibcon#enter sib2, iclass 25, count 0 2006.253.08:07:31.25#ibcon#flushed, iclass 25, count 0 2006.253.08:07:31.25#ibcon#about to write, iclass 25, count 0 2006.253.08:07:31.25#ibcon#wrote, iclass 25, count 0 2006.253.08:07:31.25#ibcon#about to read 3, iclass 25, count 0 2006.253.08:07:31.27#ibcon#read 3, iclass 25, count 0 2006.253.08:07:31.27#ibcon#about to read 4, iclass 25, count 0 2006.253.08:07:31.27#ibcon#read 4, iclass 25, count 0 2006.253.08:07:31.27#ibcon#about to read 5, iclass 25, count 0 2006.253.08:07:31.27#ibcon#read 5, iclass 25, count 0 2006.253.08:07:31.27#ibcon#about to read 6, iclass 25, count 0 2006.253.08:07:31.27#ibcon#read 6, iclass 25, count 0 2006.253.08:07:31.27#ibcon#end of sib2, iclass 25, count 0 2006.253.08:07:31.27#ibcon#*mode == 0, iclass 25, count 0 2006.253.08:07:31.27#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.253.08:07:31.27#ibcon#[27=USB\r\n] 2006.253.08:07:31.27#ibcon#*before write, iclass 25, count 0 2006.253.08:07:31.27#ibcon#enter sib2, iclass 25, count 0 2006.253.08:07:31.27#ibcon#flushed, iclass 25, count 0 2006.253.08:07:31.27#ibcon#about to write, iclass 25, count 0 2006.253.08:07:31.27#ibcon#wrote, iclass 25, count 0 2006.253.08:07:31.27#ibcon#about to read 3, iclass 25, count 0 2006.253.08:07:31.30#ibcon#read 3, iclass 25, count 0 2006.253.08:07:31.30#ibcon#about to read 4, iclass 25, count 0 2006.253.08:07:31.30#ibcon#read 4, iclass 25, count 0 2006.253.08:07:31.30#ibcon#about to read 5, iclass 25, count 0 2006.253.08:07:31.30#ibcon#read 5, iclass 25, count 0 2006.253.08:07:31.30#ibcon#about to read 6, iclass 25, count 0 2006.253.08:07:31.30#ibcon#read 6, iclass 25, count 0 2006.253.08:07:31.30#ibcon#end of sib2, iclass 25, count 0 2006.253.08:07:31.30#ibcon#*after write, iclass 25, count 0 2006.253.08:07:31.30#ibcon#*before return 0, iclass 25, count 0 2006.253.08:07:31.30#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.253.08:07:31.30#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.253.08:07:31.30#ibcon#about to clear, iclass 25 cls_cnt 0 2006.253.08:07:31.30#ibcon#cleared, iclass 25 cls_cnt 0 2006.253.08:07:31.30$vc4f8/vblo=3,656.99 2006.253.08:07:31.30#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.253.08:07:31.30#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.253.08:07:31.30#ibcon#ireg 17 cls_cnt 0 2006.253.08:07:31.30#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.253.08:07:31.30#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.253.08:07:31.30#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.253.08:07:31.30#ibcon#enter wrdev, iclass 27, count 0 2006.253.08:07:31.30#ibcon#first serial, iclass 27, count 0 2006.253.08:07:31.30#ibcon#enter sib2, iclass 27, count 0 2006.253.08:07:31.30#ibcon#flushed, iclass 27, count 0 2006.253.08:07:31.30#ibcon#about to write, iclass 27, count 0 2006.253.08:07:31.30#ibcon#wrote, iclass 27, count 0 2006.253.08:07:31.30#ibcon#about to read 3, iclass 27, count 0 2006.253.08:07:31.32#ibcon#read 3, iclass 27, count 0 2006.253.08:07:31.32#ibcon#about to read 4, iclass 27, count 0 2006.253.08:07:31.32#ibcon#read 4, iclass 27, count 0 2006.253.08:07:31.32#ibcon#about to read 5, iclass 27, count 0 2006.253.08:07:31.32#ibcon#read 5, iclass 27, count 0 2006.253.08:07:31.32#ibcon#about to read 6, iclass 27, count 0 2006.253.08:07:31.32#ibcon#read 6, iclass 27, count 0 2006.253.08:07:31.32#ibcon#end of sib2, iclass 27, count 0 2006.253.08:07:31.32#ibcon#*mode == 0, iclass 27, count 0 2006.253.08:07:31.32#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.253.08:07:31.32#ibcon#[28=FRQ=03,656.99\r\n] 2006.253.08:07:31.32#ibcon#*before write, iclass 27, count 0 2006.253.08:07:31.32#ibcon#enter sib2, iclass 27, count 0 2006.253.08:07:31.32#ibcon#flushed, iclass 27, count 0 2006.253.08:07:31.32#ibcon#about to write, iclass 27, count 0 2006.253.08:07:31.32#ibcon#wrote, iclass 27, count 0 2006.253.08:07:31.32#ibcon#about to read 3, iclass 27, count 0 2006.253.08:07:31.36#ibcon#read 3, iclass 27, count 0 2006.253.08:07:31.36#ibcon#about to read 4, iclass 27, count 0 2006.253.08:07:31.36#ibcon#read 4, iclass 27, count 0 2006.253.08:07:31.36#ibcon#about to read 5, iclass 27, count 0 2006.253.08:07:31.36#ibcon#read 5, iclass 27, count 0 2006.253.08:07:31.36#ibcon#about to read 6, iclass 27, count 0 2006.253.08:07:31.36#ibcon#read 6, iclass 27, count 0 2006.253.08:07:31.36#ibcon#end of sib2, iclass 27, count 0 2006.253.08:07:31.36#ibcon#*after write, iclass 27, count 0 2006.253.08:07:31.36#ibcon#*before return 0, iclass 27, count 0 2006.253.08:07:31.36#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.253.08:07:31.36#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.253.08:07:31.36#ibcon#about to clear, iclass 27 cls_cnt 0 2006.253.08:07:31.36#ibcon#cleared, iclass 27 cls_cnt 0 2006.253.08:07:31.36$vc4f8/vb=3,4 2006.253.08:07:31.36#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.253.08:07:31.36#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.253.08:07:31.36#ibcon#ireg 11 cls_cnt 2 2006.253.08:07:31.36#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.253.08:07:31.42#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.253.08:07:31.42#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.253.08:07:31.42#ibcon#enter wrdev, iclass 29, count 2 2006.253.08:07:31.42#ibcon#first serial, iclass 29, count 2 2006.253.08:07:31.42#ibcon#enter sib2, iclass 29, count 2 2006.253.08:07:31.42#ibcon#flushed, iclass 29, count 2 2006.253.08:07:31.42#ibcon#about to write, iclass 29, count 2 2006.253.08:07:31.42#ibcon#wrote, iclass 29, count 2 2006.253.08:07:31.42#ibcon#about to read 3, iclass 29, count 2 2006.253.08:07:31.44#ibcon#read 3, iclass 29, count 2 2006.253.08:07:31.44#ibcon#about to read 4, iclass 29, count 2 2006.253.08:07:31.44#ibcon#read 4, iclass 29, count 2 2006.253.08:07:31.44#ibcon#about to read 5, iclass 29, count 2 2006.253.08:07:31.44#ibcon#read 5, iclass 29, count 2 2006.253.08:07:31.44#ibcon#about to read 6, iclass 29, count 2 2006.253.08:07:31.44#ibcon#read 6, iclass 29, count 2 2006.253.08:07:31.44#ibcon#end of sib2, iclass 29, count 2 2006.253.08:07:31.44#ibcon#*mode == 0, iclass 29, count 2 2006.253.08:07:31.44#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.253.08:07:31.44#ibcon#[27=AT03-04\r\n] 2006.253.08:07:31.44#ibcon#*before write, iclass 29, count 2 2006.253.08:07:31.44#ibcon#enter sib2, iclass 29, count 2 2006.253.08:07:31.44#ibcon#flushed, iclass 29, count 2 2006.253.08:07:31.44#ibcon#about to write, iclass 29, count 2 2006.253.08:07:31.44#ibcon#wrote, iclass 29, count 2 2006.253.08:07:31.44#ibcon#about to read 3, iclass 29, count 2 2006.253.08:07:31.47#ibcon#read 3, iclass 29, count 2 2006.253.08:07:31.47#ibcon#about to read 4, iclass 29, count 2 2006.253.08:07:31.47#ibcon#read 4, iclass 29, count 2 2006.253.08:07:31.47#ibcon#about to read 5, iclass 29, count 2 2006.253.08:07:31.47#ibcon#read 5, iclass 29, count 2 2006.253.08:07:31.47#ibcon#about to read 6, iclass 29, count 2 2006.253.08:07:31.47#ibcon#read 6, iclass 29, count 2 2006.253.08:07:31.47#ibcon#end of sib2, iclass 29, count 2 2006.253.08:07:31.47#ibcon#*after write, iclass 29, count 2 2006.253.08:07:31.47#ibcon#*before return 0, iclass 29, count 2 2006.253.08:07:31.47#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.253.08:07:31.47#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.253.08:07:31.47#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.253.08:07:31.47#ibcon#ireg 7 cls_cnt 0 2006.253.08:07:31.47#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.253.08:07:31.59#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.253.08:07:31.59#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.253.08:07:31.59#ibcon#enter wrdev, iclass 29, count 0 2006.253.08:07:31.59#ibcon#first serial, iclass 29, count 0 2006.253.08:07:31.59#ibcon#enter sib2, iclass 29, count 0 2006.253.08:07:31.59#ibcon#flushed, iclass 29, count 0 2006.253.08:07:31.59#ibcon#about to write, iclass 29, count 0 2006.253.08:07:31.59#ibcon#wrote, iclass 29, count 0 2006.253.08:07:31.59#ibcon#about to read 3, iclass 29, count 0 2006.253.08:07:31.61#ibcon#read 3, iclass 29, count 0 2006.253.08:07:31.61#ibcon#about to read 4, iclass 29, count 0 2006.253.08:07:31.61#ibcon#read 4, iclass 29, count 0 2006.253.08:07:31.61#ibcon#about to read 5, iclass 29, count 0 2006.253.08:07:31.61#ibcon#read 5, iclass 29, count 0 2006.253.08:07:31.61#ibcon#about to read 6, iclass 29, count 0 2006.253.08:07:31.61#ibcon#read 6, iclass 29, count 0 2006.253.08:07:31.61#ibcon#end of sib2, iclass 29, count 0 2006.253.08:07:31.61#ibcon#*mode == 0, iclass 29, count 0 2006.253.08:07:31.61#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.253.08:07:31.61#ibcon#[27=USB\r\n] 2006.253.08:07:31.61#ibcon#*before write, iclass 29, count 0 2006.253.08:07:31.61#ibcon#enter sib2, iclass 29, count 0 2006.253.08:07:31.61#ibcon#flushed, iclass 29, count 0 2006.253.08:07:31.61#ibcon#about to write, iclass 29, count 0 2006.253.08:07:31.61#ibcon#wrote, iclass 29, count 0 2006.253.08:07:31.61#ibcon#about to read 3, iclass 29, count 0 2006.253.08:07:31.64#ibcon#read 3, iclass 29, count 0 2006.253.08:07:31.64#ibcon#about to read 4, iclass 29, count 0 2006.253.08:07:31.64#ibcon#read 4, iclass 29, count 0 2006.253.08:07:31.64#ibcon#about to read 5, iclass 29, count 0 2006.253.08:07:31.64#ibcon#read 5, iclass 29, count 0 2006.253.08:07:31.64#ibcon#about to read 6, iclass 29, count 0 2006.253.08:07:31.64#ibcon#read 6, iclass 29, count 0 2006.253.08:07:31.64#ibcon#end of sib2, iclass 29, count 0 2006.253.08:07:31.64#ibcon#*after write, iclass 29, count 0 2006.253.08:07:31.64#ibcon#*before return 0, iclass 29, count 0 2006.253.08:07:31.64#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.253.08:07:31.64#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.253.08:07:31.64#ibcon#about to clear, iclass 29 cls_cnt 0 2006.253.08:07:31.64#ibcon#cleared, iclass 29 cls_cnt 0 2006.253.08:07:31.64$vc4f8/vblo=4,712.99 2006.253.08:07:31.64#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.253.08:07:31.64#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.253.08:07:31.64#ibcon#ireg 17 cls_cnt 0 2006.253.08:07:31.64#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.253.08:07:31.64#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.253.08:07:31.64#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.253.08:07:31.64#ibcon#enter wrdev, iclass 31, count 0 2006.253.08:07:31.64#ibcon#first serial, iclass 31, count 0 2006.253.08:07:31.64#ibcon#enter sib2, iclass 31, count 0 2006.253.08:07:31.64#ibcon#flushed, iclass 31, count 0 2006.253.08:07:31.64#ibcon#about to write, iclass 31, count 0 2006.253.08:07:31.64#ibcon#wrote, iclass 31, count 0 2006.253.08:07:31.64#ibcon#about to read 3, iclass 31, count 0 2006.253.08:07:31.66#ibcon#read 3, iclass 31, count 0 2006.253.08:07:31.66#ibcon#about to read 4, iclass 31, count 0 2006.253.08:07:31.66#ibcon#read 4, iclass 31, count 0 2006.253.08:07:31.66#ibcon#about to read 5, iclass 31, count 0 2006.253.08:07:31.66#ibcon#read 5, iclass 31, count 0 2006.253.08:07:31.66#ibcon#about to read 6, iclass 31, count 0 2006.253.08:07:31.66#ibcon#read 6, iclass 31, count 0 2006.253.08:07:31.66#ibcon#end of sib2, iclass 31, count 0 2006.253.08:07:31.66#ibcon#*mode == 0, iclass 31, count 0 2006.253.08:07:31.66#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.253.08:07:31.66#ibcon#[28=FRQ=04,712.99\r\n] 2006.253.08:07:31.66#ibcon#*before write, iclass 31, count 0 2006.253.08:07:31.66#ibcon#enter sib2, iclass 31, count 0 2006.253.08:07:31.66#ibcon#flushed, iclass 31, count 0 2006.253.08:07:31.66#ibcon#about to write, iclass 31, count 0 2006.253.08:07:31.66#ibcon#wrote, iclass 31, count 0 2006.253.08:07:31.66#ibcon#about to read 3, iclass 31, count 0 2006.253.08:07:31.70#ibcon#read 3, iclass 31, count 0 2006.253.08:07:31.70#ibcon#about to read 4, iclass 31, count 0 2006.253.08:07:31.70#ibcon#read 4, iclass 31, count 0 2006.253.08:07:31.70#ibcon#about to read 5, iclass 31, count 0 2006.253.08:07:31.70#ibcon#read 5, iclass 31, count 0 2006.253.08:07:31.70#ibcon#about to read 6, iclass 31, count 0 2006.253.08:07:31.70#ibcon#read 6, iclass 31, count 0 2006.253.08:07:31.70#ibcon#end of sib2, iclass 31, count 0 2006.253.08:07:31.70#ibcon#*after write, iclass 31, count 0 2006.253.08:07:31.70#ibcon#*before return 0, iclass 31, count 0 2006.253.08:07:31.70#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.253.08:07:31.70#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.253.08:07:31.70#ibcon#about to clear, iclass 31 cls_cnt 0 2006.253.08:07:31.70#ibcon#cleared, iclass 31 cls_cnt 0 2006.253.08:07:31.70$vc4f8/vb=4,4 2006.253.08:07:31.70#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.253.08:07:31.70#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.253.08:07:31.70#ibcon#ireg 11 cls_cnt 2 2006.253.08:07:31.70#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.253.08:07:31.76#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.253.08:07:31.76#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.253.08:07:31.76#ibcon#enter wrdev, iclass 33, count 2 2006.253.08:07:31.76#ibcon#first serial, iclass 33, count 2 2006.253.08:07:31.76#ibcon#enter sib2, iclass 33, count 2 2006.253.08:07:31.76#ibcon#flushed, iclass 33, count 2 2006.253.08:07:31.76#ibcon#about to write, iclass 33, count 2 2006.253.08:07:31.76#ibcon#wrote, iclass 33, count 2 2006.253.08:07:31.76#ibcon#about to read 3, iclass 33, count 2 2006.253.08:07:31.78#ibcon#read 3, iclass 33, count 2 2006.253.08:07:31.78#ibcon#about to read 4, iclass 33, count 2 2006.253.08:07:31.78#ibcon#read 4, iclass 33, count 2 2006.253.08:07:31.78#ibcon#about to read 5, iclass 33, count 2 2006.253.08:07:31.78#ibcon#read 5, iclass 33, count 2 2006.253.08:07:31.78#ibcon#about to read 6, iclass 33, count 2 2006.253.08:07:31.78#ibcon#read 6, iclass 33, count 2 2006.253.08:07:31.78#ibcon#end of sib2, iclass 33, count 2 2006.253.08:07:31.78#ibcon#*mode == 0, iclass 33, count 2 2006.253.08:07:31.78#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.253.08:07:31.78#ibcon#[27=AT04-04\r\n] 2006.253.08:07:31.78#ibcon#*before write, iclass 33, count 2 2006.253.08:07:31.78#ibcon#enter sib2, iclass 33, count 2 2006.253.08:07:31.78#ibcon#flushed, iclass 33, count 2 2006.253.08:07:31.78#ibcon#about to write, iclass 33, count 2 2006.253.08:07:31.78#ibcon#wrote, iclass 33, count 2 2006.253.08:07:31.78#ibcon#about to read 3, iclass 33, count 2 2006.253.08:07:31.81#ibcon#read 3, iclass 33, count 2 2006.253.08:07:31.81#ibcon#about to read 4, iclass 33, count 2 2006.253.08:07:31.81#ibcon#read 4, iclass 33, count 2 2006.253.08:07:31.81#ibcon#about to read 5, iclass 33, count 2 2006.253.08:07:31.81#ibcon#read 5, iclass 33, count 2 2006.253.08:07:31.81#ibcon#about to read 6, iclass 33, count 2 2006.253.08:07:31.81#ibcon#read 6, iclass 33, count 2 2006.253.08:07:31.81#ibcon#end of sib2, iclass 33, count 2 2006.253.08:07:31.81#ibcon#*after write, iclass 33, count 2 2006.253.08:07:31.81#ibcon#*before return 0, iclass 33, count 2 2006.253.08:07:31.81#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.253.08:07:31.81#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.253.08:07:31.81#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.253.08:07:31.81#ibcon#ireg 7 cls_cnt 0 2006.253.08:07:31.81#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.253.08:07:31.93#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.253.08:07:31.93#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.253.08:07:31.93#ibcon#enter wrdev, iclass 33, count 0 2006.253.08:07:31.93#ibcon#first serial, iclass 33, count 0 2006.253.08:07:31.93#ibcon#enter sib2, iclass 33, count 0 2006.253.08:07:31.93#ibcon#flushed, iclass 33, count 0 2006.253.08:07:31.93#ibcon#about to write, iclass 33, count 0 2006.253.08:07:31.93#ibcon#wrote, iclass 33, count 0 2006.253.08:07:31.93#ibcon#about to read 3, iclass 33, count 0 2006.253.08:07:31.95#ibcon#read 3, iclass 33, count 0 2006.253.08:07:31.95#ibcon#about to read 4, iclass 33, count 0 2006.253.08:07:31.95#ibcon#read 4, iclass 33, count 0 2006.253.08:07:31.95#ibcon#about to read 5, iclass 33, count 0 2006.253.08:07:31.95#ibcon#read 5, iclass 33, count 0 2006.253.08:07:31.95#ibcon#about to read 6, iclass 33, count 0 2006.253.08:07:31.95#ibcon#read 6, iclass 33, count 0 2006.253.08:07:31.95#ibcon#end of sib2, iclass 33, count 0 2006.253.08:07:31.95#ibcon#*mode == 0, iclass 33, count 0 2006.253.08:07:31.95#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.253.08:07:31.95#ibcon#[27=USB\r\n] 2006.253.08:07:31.95#ibcon#*before write, iclass 33, count 0 2006.253.08:07:31.95#ibcon#enter sib2, iclass 33, count 0 2006.253.08:07:31.95#ibcon#flushed, iclass 33, count 0 2006.253.08:07:31.95#ibcon#about to write, iclass 33, count 0 2006.253.08:07:31.95#ibcon#wrote, iclass 33, count 0 2006.253.08:07:31.95#ibcon#about to read 3, iclass 33, count 0 2006.253.08:07:31.98#ibcon#read 3, iclass 33, count 0 2006.253.08:07:31.98#ibcon#about to read 4, iclass 33, count 0 2006.253.08:07:31.98#ibcon#read 4, iclass 33, count 0 2006.253.08:07:31.98#ibcon#about to read 5, iclass 33, count 0 2006.253.08:07:31.98#ibcon#read 5, iclass 33, count 0 2006.253.08:07:31.98#ibcon#about to read 6, iclass 33, count 0 2006.253.08:07:31.98#ibcon#read 6, iclass 33, count 0 2006.253.08:07:31.98#ibcon#end of sib2, iclass 33, count 0 2006.253.08:07:31.98#ibcon#*after write, iclass 33, count 0 2006.253.08:07:31.98#ibcon#*before return 0, iclass 33, count 0 2006.253.08:07:31.98#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.253.08:07:31.98#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.253.08:07:31.98#ibcon#about to clear, iclass 33 cls_cnt 0 2006.253.08:07:31.98#ibcon#cleared, iclass 33 cls_cnt 0 2006.253.08:07:31.98$vc4f8/vblo=5,744.99 2006.253.08:07:31.98#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.253.08:07:31.98#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.253.08:07:31.98#ibcon#ireg 17 cls_cnt 0 2006.253.08:07:31.98#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.253.08:07:31.98#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.253.08:07:31.98#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.253.08:07:31.98#ibcon#enter wrdev, iclass 35, count 0 2006.253.08:07:31.98#ibcon#first serial, iclass 35, count 0 2006.253.08:07:31.98#ibcon#enter sib2, iclass 35, count 0 2006.253.08:07:31.98#ibcon#flushed, iclass 35, count 0 2006.253.08:07:31.98#ibcon#about to write, iclass 35, count 0 2006.253.08:07:31.98#ibcon#wrote, iclass 35, count 0 2006.253.08:07:31.98#ibcon#about to read 3, iclass 35, count 0 2006.253.08:07:32.00#ibcon#read 3, iclass 35, count 0 2006.253.08:07:32.00#ibcon#about to read 4, iclass 35, count 0 2006.253.08:07:32.01#ibcon#read 4, iclass 35, count 0 2006.253.08:07:32.01#ibcon#about to read 5, iclass 35, count 0 2006.253.08:07:32.01#ibcon#read 5, iclass 35, count 0 2006.253.08:07:32.01#ibcon#about to read 6, iclass 35, count 0 2006.253.08:07:32.01#ibcon#read 6, iclass 35, count 0 2006.253.08:07:32.01#ibcon#end of sib2, iclass 35, count 0 2006.253.08:07:32.01#ibcon#*mode == 0, iclass 35, count 0 2006.253.08:07:32.01#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.253.08:07:32.01#ibcon#[28=FRQ=05,744.99\r\n] 2006.253.08:07:32.01#ibcon#*before write, iclass 35, count 0 2006.253.08:07:32.01#ibcon#enter sib2, iclass 35, count 0 2006.253.08:07:32.01#ibcon#flushed, iclass 35, count 0 2006.253.08:07:32.01#ibcon#about to write, iclass 35, count 0 2006.253.08:07:32.01#ibcon#wrote, iclass 35, count 0 2006.253.08:07:32.01#ibcon#about to read 3, iclass 35, count 0 2006.253.08:07:32.05#ibcon#read 3, iclass 35, count 0 2006.253.08:07:32.05#ibcon#about to read 4, iclass 35, count 0 2006.253.08:07:32.05#ibcon#read 4, iclass 35, count 0 2006.253.08:07:32.05#ibcon#about to read 5, iclass 35, count 0 2006.253.08:07:32.05#ibcon#read 5, iclass 35, count 0 2006.253.08:07:32.05#ibcon#about to read 6, iclass 35, count 0 2006.253.08:07:32.05#ibcon#read 6, iclass 35, count 0 2006.253.08:07:32.05#ibcon#end of sib2, iclass 35, count 0 2006.253.08:07:32.05#ibcon#*after write, iclass 35, count 0 2006.253.08:07:32.05#ibcon#*before return 0, iclass 35, count 0 2006.253.08:07:32.05#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.253.08:07:32.05#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.253.08:07:32.05#ibcon#about to clear, iclass 35 cls_cnt 0 2006.253.08:07:32.05#ibcon#cleared, iclass 35 cls_cnt 0 2006.253.08:07:32.05$vc4f8/vb=5,4 2006.253.08:07:32.05#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.253.08:07:32.05#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.253.08:07:32.05#ibcon#ireg 11 cls_cnt 2 2006.253.08:07:32.05#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.253.08:07:32.10#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.253.08:07:32.10#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.253.08:07:32.10#ibcon#enter wrdev, iclass 37, count 2 2006.253.08:07:32.10#ibcon#first serial, iclass 37, count 2 2006.253.08:07:32.10#ibcon#enter sib2, iclass 37, count 2 2006.253.08:07:32.10#ibcon#flushed, iclass 37, count 2 2006.253.08:07:32.10#ibcon#about to write, iclass 37, count 2 2006.253.08:07:32.10#ibcon#wrote, iclass 37, count 2 2006.253.08:07:32.10#ibcon#about to read 3, iclass 37, count 2 2006.253.08:07:32.12#ibcon#read 3, iclass 37, count 2 2006.253.08:07:32.12#ibcon#about to read 4, iclass 37, count 2 2006.253.08:07:32.12#ibcon#read 4, iclass 37, count 2 2006.253.08:07:32.12#ibcon#about to read 5, iclass 37, count 2 2006.253.08:07:32.12#ibcon#read 5, iclass 37, count 2 2006.253.08:07:32.12#ibcon#about to read 6, iclass 37, count 2 2006.253.08:07:32.12#ibcon#read 6, iclass 37, count 2 2006.253.08:07:32.12#ibcon#end of sib2, iclass 37, count 2 2006.253.08:07:32.12#ibcon#*mode == 0, iclass 37, count 2 2006.253.08:07:32.12#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.253.08:07:32.12#ibcon#[27=AT05-04\r\n] 2006.253.08:07:32.12#ibcon#*before write, iclass 37, count 2 2006.253.08:07:32.12#ibcon#enter sib2, iclass 37, count 2 2006.253.08:07:32.12#ibcon#flushed, iclass 37, count 2 2006.253.08:07:32.12#ibcon#about to write, iclass 37, count 2 2006.253.08:07:32.12#ibcon#wrote, iclass 37, count 2 2006.253.08:07:32.12#ibcon#about to read 3, iclass 37, count 2 2006.253.08:07:32.15#ibcon#read 3, iclass 37, count 2 2006.253.08:07:32.15#ibcon#about to read 4, iclass 37, count 2 2006.253.08:07:32.15#ibcon#read 4, iclass 37, count 2 2006.253.08:07:32.15#ibcon#about to read 5, iclass 37, count 2 2006.253.08:07:32.15#ibcon#read 5, iclass 37, count 2 2006.253.08:07:32.15#ibcon#about to read 6, iclass 37, count 2 2006.253.08:07:32.15#ibcon#read 6, iclass 37, count 2 2006.253.08:07:32.15#ibcon#end of sib2, iclass 37, count 2 2006.253.08:07:32.15#ibcon#*after write, iclass 37, count 2 2006.253.08:07:32.15#ibcon#*before return 0, iclass 37, count 2 2006.253.08:07:32.15#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.253.08:07:32.15#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.253.08:07:32.15#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.253.08:07:32.15#ibcon#ireg 7 cls_cnt 0 2006.253.08:07:32.15#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.253.08:07:32.27#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.253.08:07:32.27#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.253.08:07:32.27#ibcon#enter wrdev, iclass 37, count 0 2006.253.08:07:32.27#ibcon#first serial, iclass 37, count 0 2006.253.08:07:32.27#ibcon#enter sib2, iclass 37, count 0 2006.253.08:07:32.27#ibcon#flushed, iclass 37, count 0 2006.253.08:07:32.27#ibcon#about to write, iclass 37, count 0 2006.253.08:07:32.27#ibcon#wrote, iclass 37, count 0 2006.253.08:07:32.27#ibcon#about to read 3, iclass 37, count 0 2006.253.08:07:32.29#ibcon#read 3, iclass 37, count 0 2006.253.08:07:32.29#ibcon#about to read 4, iclass 37, count 0 2006.253.08:07:32.29#ibcon#read 4, iclass 37, count 0 2006.253.08:07:32.29#ibcon#about to read 5, iclass 37, count 0 2006.253.08:07:32.29#ibcon#read 5, iclass 37, count 0 2006.253.08:07:32.29#ibcon#about to read 6, iclass 37, count 0 2006.253.08:07:32.29#ibcon#read 6, iclass 37, count 0 2006.253.08:07:32.29#ibcon#end of sib2, iclass 37, count 0 2006.253.08:07:32.29#ibcon#*mode == 0, iclass 37, count 0 2006.253.08:07:32.29#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.253.08:07:32.29#ibcon#[27=USB\r\n] 2006.253.08:07:32.29#ibcon#*before write, iclass 37, count 0 2006.253.08:07:32.29#ibcon#enter sib2, iclass 37, count 0 2006.253.08:07:32.29#ibcon#flushed, iclass 37, count 0 2006.253.08:07:32.29#ibcon#about to write, iclass 37, count 0 2006.253.08:07:32.29#ibcon#wrote, iclass 37, count 0 2006.253.08:07:32.29#ibcon#about to read 3, iclass 37, count 0 2006.253.08:07:32.32#ibcon#read 3, iclass 37, count 0 2006.253.08:07:32.32#ibcon#about to read 4, iclass 37, count 0 2006.253.08:07:32.32#ibcon#read 4, iclass 37, count 0 2006.253.08:07:32.32#ibcon#about to read 5, iclass 37, count 0 2006.253.08:07:32.32#ibcon#read 5, iclass 37, count 0 2006.253.08:07:32.32#ibcon#about to read 6, iclass 37, count 0 2006.253.08:07:32.32#ibcon#read 6, iclass 37, count 0 2006.253.08:07:32.32#ibcon#end of sib2, iclass 37, count 0 2006.253.08:07:32.32#ibcon#*after write, iclass 37, count 0 2006.253.08:07:32.32#ibcon#*before return 0, iclass 37, count 0 2006.253.08:07:32.32#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.253.08:07:32.32#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.253.08:07:32.32#ibcon#about to clear, iclass 37 cls_cnt 0 2006.253.08:07:32.32#ibcon#cleared, iclass 37 cls_cnt 0 2006.253.08:07:32.32$vc4f8/vblo=6,752.99 2006.253.08:07:32.32#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.253.08:07:32.32#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.253.08:07:32.32#ibcon#ireg 17 cls_cnt 0 2006.253.08:07:32.32#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.253.08:07:32.32#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.253.08:07:32.32#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.253.08:07:32.32#ibcon#enter wrdev, iclass 39, count 0 2006.253.08:07:32.32#ibcon#first serial, iclass 39, count 0 2006.253.08:07:32.32#ibcon#enter sib2, iclass 39, count 0 2006.253.08:07:32.32#ibcon#flushed, iclass 39, count 0 2006.253.08:07:32.32#ibcon#about to write, iclass 39, count 0 2006.253.08:07:32.32#ibcon#wrote, iclass 39, count 0 2006.253.08:07:32.32#ibcon#about to read 3, iclass 39, count 0 2006.253.08:07:32.34#ibcon#read 3, iclass 39, count 0 2006.253.08:07:32.34#ibcon#about to read 4, iclass 39, count 0 2006.253.08:07:32.34#ibcon#read 4, iclass 39, count 0 2006.253.08:07:32.34#ibcon#about to read 5, iclass 39, count 0 2006.253.08:07:32.34#ibcon#read 5, iclass 39, count 0 2006.253.08:07:32.34#ibcon#about to read 6, iclass 39, count 0 2006.253.08:07:32.34#ibcon#read 6, iclass 39, count 0 2006.253.08:07:32.34#ibcon#end of sib2, iclass 39, count 0 2006.253.08:07:32.34#ibcon#*mode == 0, iclass 39, count 0 2006.253.08:07:32.34#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.253.08:07:32.34#ibcon#[28=FRQ=06,752.99\r\n] 2006.253.08:07:32.34#ibcon#*before write, iclass 39, count 0 2006.253.08:07:32.34#ibcon#enter sib2, iclass 39, count 0 2006.253.08:07:32.34#ibcon#flushed, iclass 39, count 0 2006.253.08:07:32.34#ibcon#about to write, iclass 39, count 0 2006.253.08:07:32.34#ibcon#wrote, iclass 39, count 0 2006.253.08:07:32.34#ibcon#about to read 3, iclass 39, count 0 2006.253.08:07:32.38#ibcon#read 3, iclass 39, count 0 2006.253.08:07:32.38#ibcon#about to read 4, iclass 39, count 0 2006.253.08:07:32.38#ibcon#read 4, iclass 39, count 0 2006.253.08:07:32.38#ibcon#about to read 5, iclass 39, count 0 2006.253.08:07:32.38#ibcon#read 5, iclass 39, count 0 2006.253.08:07:32.38#ibcon#about to read 6, iclass 39, count 0 2006.253.08:07:32.38#ibcon#read 6, iclass 39, count 0 2006.253.08:07:32.38#ibcon#end of sib2, iclass 39, count 0 2006.253.08:07:32.38#ibcon#*after write, iclass 39, count 0 2006.253.08:07:32.38#ibcon#*before return 0, iclass 39, count 0 2006.253.08:07:32.38#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.253.08:07:32.38#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.253.08:07:32.38#ibcon#about to clear, iclass 39 cls_cnt 0 2006.253.08:07:32.38#ibcon#cleared, iclass 39 cls_cnt 0 2006.253.08:07:32.38$vc4f8/vb=6,4 2006.253.08:07:32.38#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.253.08:07:32.38#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.253.08:07:32.38#ibcon#ireg 11 cls_cnt 2 2006.253.08:07:32.38#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.253.08:07:32.44#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.253.08:07:32.44#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.253.08:07:32.44#ibcon#enter wrdev, iclass 3, count 2 2006.253.08:07:32.44#ibcon#first serial, iclass 3, count 2 2006.253.08:07:32.44#ibcon#enter sib2, iclass 3, count 2 2006.253.08:07:32.44#ibcon#flushed, iclass 3, count 2 2006.253.08:07:32.44#ibcon#about to write, iclass 3, count 2 2006.253.08:07:32.44#ibcon#wrote, iclass 3, count 2 2006.253.08:07:32.44#ibcon#about to read 3, iclass 3, count 2 2006.253.08:07:32.46#ibcon#read 3, iclass 3, count 2 2006.253.08:07:32.46#ibcon#about to read 4, iclass 3, count 2 2006.253.08:07:32.46#ibcon#read 4, iclass 3, count 2 2006.253.08:07:32.46#ibcon#about to read 5, iclass 3, count 2 2006.253.08:07:32.46#ibcon#read 5, iclass 3, count 2 2006.253.08:07:32.46#ibcon#about to read 6, iclass 3, count 2 2006.253.08:07:32.46#ibcon#read 6, iclass 3, count 2 2006.253.08:07:32.46#ibcon#end of sib2, iclass 3, count 2 2006.253.08:07:32.46#ibcon#*mode == 0, iclass 3, count 2 2006.253.08:07:32.46#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.253.08:07:32.46#ibcon#[27=AT06-04\r\n] 2006.253.08:07:32.46#ibcon#*before write, iclass 3, count 2 2006.253.08:07:32.46#ibcon#enter sib2, iclass 3, count 2 2006.253.08:07:32.46#ibcon#flushed, iclass 3, count 2 2006.253.08:07:32.46#ibcon#about to write, iclass 3, count 2 2006.253.08:07:32.46#ibcon#wrote, iclass 3, count 2 2006.253.08:07:32.46#ibcon#about to read 3, iclass 3, count 2 2006.253.08:07:32.49#ibcon#read 3, iclass 3, count 2 2006.253.08:07:32.49#ibcon#about to read 4, iclass 3, count 2 2006.253.08:07:32.49#ibcon#read 4, iclass 3, count 2 2006.253.08:07:32.49#ibcon#about to read 5, iclass 3, count 2 2006.253.08:07:32.49#ibcon#read 5, iclass 3, count 2 2006.253.08:07:32.49#ibcon#about to read 6, iclass 3, count 2 2006.253.08:07:32.49#ibcon#read 6, iclass 3, count 2 2006.253.08:07:32.49#ibcon#end of sib2, iclass 3, count 2 2006.253.08:07:32.49#ibcon#*after write, iclass 3, count 2 2006.253.08:07:32.49#ibcon#*before return 0, iclass 3, count 2 2006.253.08:07:32.49#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.253.08:07:32.49#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.253.08:07:32.49#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.253.08:07:32.49#ibcon#ireg 7 cls_cnt 0 2006.253.08:07:32.49#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.253.08:07:32.61#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.253.08:07:32.61#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.253.08:07:32.61#ibcon#enter wrdev, iclass 3, count 0 2006.253.08:07:32.61#ibcon#first serial, iclass 3, count 0 2006.253.08:07:32.61#ibcon#enter sib2, iclass 3, count 0 2006.253.08:07:32.61#ibcon#flushed, iclass 3, count 0 2006.253.08:07:32.61#ibcon#about to write, iclass 3, count 0 2006.253.08:07:32.61#ibcon#wrote, iclass 3, count 0 2006.253.08:07:32.61#ibcon#about to read 3, iclass 3, count 0 2006.253.08:07:32.63#ibcon#read 3, iclass 3, count 0 2006.253.08:07:32.63#ibcon#about to read 4, iclass 3, count 0 2006.253.08:07:32.63#ibcon#read 4, iclass 3, count 0 2006.253.08:07:32.63#ibcon#about to read 5, iclass 3, count 0 2006.253.08:07:32.63#ibcon#read 5, iclass 3, count 0 2006.253.08:07:32.63#ibcon#about to read 6, iclass 3, count 0 2006.253.08:07:32.63#ibcon#read 6, iclass 3, count 0 2006.253.08:07:32.63#ibcon#end of sib2, iclass 3, count 0 2006.253.08:07:32.63#ibcon#*mode == 0, iclass 3, count 0 2006.253.08:07:32.63#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.253.08:07:32.63#ibcon#[27=USB\r\n] 2006.253.08:07:32.63#ibcon#*before write, iclass 3, count 0 2006.253.08:07:32.63#ibcon#enter sib2, iclass 3, count 0 2006.253.08:07:32.63#ibcon#flushed, iclass 3, count 0 2006.253.08:07:32.63#ibcon#about to write, iclass 3, count 0 2006.253.08:07:32.63#ibcon#wrote, iclass 3, count 0 2006.253.08:07:32.63#ibcon#about to read 3, iclass 3, count 0 2006.253.08:07:32.66#ibcon#read 3, iclass 3, count 0 2006.253.08:07:32.66#ibcon#about to read 4, iclass 3, count 0 2006.253.08:07:32.66#ibcon#read 4, iclass 3, count 0 2006.253.08:07:32.66#ibcon#about to read 5, iclass 3, count 0 2006.253.08:07:32.66#ibcon#read 5, iclass 3, count 0 2006.253.08:07:32.66#ibcon#about to read 6, iclass 3, count 0 2006.253.08:07:32.66#ibcon#read 6, iclass 3, count 0 2006.253.08:07:32.66#ibcon#end of sib2, iclass 3, count 0 2006.253.08:07:32.66#ibcon#*after write, iclass 3, count 0 2006.253.08:07:32.66#ibcon#*before return 0, iclass 3, count 0 2006.253.08:07:32.66#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.253.08:07:32.66#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.253.08:07:32.66#ibcon#about to clear, iclass 3 cls_cnt 0 2006.253.08:07:32.66#ibcon#cleared, iclass 3 cls_cnt 0 2006.253.08:07:32.66$vc4f8/vabw=wide 2006.253.08:07:32.66#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.253.08:07:32.66#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.253.08:07:32.66#ibcon#ireg 8 cls_cnt 0 2006.253.08:07:32.66#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.253.08:07:32.66#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.253.08:07:32.66#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.253.08:07:32.66#ibcon#enter wrdev, iclass 5, count 0 2006.253.08:07:32.66#ibcon#first serial, iclass 5, count 0 2006.253.08:07:32.66#ibcon#enter sib2, iclass 5, count 0 2006.253.08:07:32.66#ibcon#flushed, iclass 5, count 0 2006.253.08:07:32.66#ibcon#about to write, iclass 5, count 0 2006.253.08:07:32.66#ibcon#wrote, iclass 5, count 0 2006.253.08:07:32.66#ibcon#about to read 3, iclass 5, count 0 2006.253.08:07:32.68#ibcon#read 3, iclass 5, count 0 2006.253.08:07:32.68#ibcon#about to read 4, iclass 5, count 0 2006.253.08:07:32.68#ibcon#read 4, iclass 5, count 0 2006.253.08:07:32.68#ibcon#about to read 5, iclass 5, count 0 2006.253.08:07:32.68#ibcon#read 5, iclass 5, count 0 2006.253.08:07:32.68#ibcon#about to read 6, iclass 5, count 0 2006.253.08:07:32.69#ibcon#read 6, iclass 5, count 0 2006.253.08:07:32.69#ibcon#end of sib2, iclass 5, count 0 2006.253.08:07:32.69#ibcon#*mode == 0, iclass 5, count 0 2006.253.08:07:32.69#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.253.08:07:32.69#ibcon#[25=BW32\r\n] 2006.253.08:07:32.69#ibcon#*before write, iclass 5, count 0 2006.253.08:07:32.69#ibcon#enter sib2, iclass 5, count 0 2006.253.08:07:32.69#ibcon#flushed, iclass 5, count 0 2006.253.08:07:32.69#ibcon#about to write, iclass 5, count 0 2006.253.08:07:32.69#ibcon#wrote, iclass 5, count 0 2006.253.08:07:32.69#ibcon#about to read 3, iclass 5, count 0 2006.253.08:07:32.72#ibcon#read 3, iclass 5, count 0 2006.253.08:07:32.72#ibcon#about to read 4, iclass 5, count 0 2006.253.08:07:32.72#ibcon#read 4, iclass 5, count 0 2006.253.08:07:32.72#ibcon#about to read 5, iclass 5, count 0 2006.253.08:07:32.72#ibcon#read 5, iclass 5, count 0 2006.253.08:07:32.72#ibcon#about to read 6, iclass 5, count 0 2006.253.08:07:32.72#ibcon#read 6, iclass 5, count 0 2006.253.08:07:32.72#ibcon#end of sib2, iclass 5, count 0 2006.253.08:07:32.72#ibcon#*after write, iclass 5, count 0 2006.253.08:07:32.72#ibcon#*before return 0, iclass 5, count 0 2006.253.08:07:32.72#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.253.08:07:32.72#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.253.08:07:32.72#ibcon#about to clear, iclass 5 cls_cnt 0 2006.253.08:07:32.72#ibcon#cleared, iclass 5 cls_cnt 0 2006.253.08:07:32.72$vc4f8/vbbw=wide 2006.253.08:07:32.72#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.253.08:07:32.72#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.253.08:07:32.72#ibcon#ireg 8 cls_cnt 0 2006.253.08:07:32.72#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.253.08:07:32.78#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.253.08:07:32.78#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.253.08:07:32.78#ibcon#enter wrdev, iclass 7, count 0 2006.253.08:07:32.78#ibcon#first serial, iclass 7, count 0 2006.253.08:07:32.78#ibcon#enter sib2, iclass 7, count 0 2006.253.08:07:32.78#ibcon#flushed, iclass 7, count 0 2006.253.08:07:32.78#ibcon#about to write, iclass 7, count 0 2006.253.08:07:32.78#ibcon#wrote, iclass 7, count 0 2006.253.08:07:32.78#ibcon#about to read 3, iclass 7, count 0 2006.253.08:07:32.80#ibcon#read 3, iclass 7, count 0 2006.253.08:07:32.80#ibcon#about to read 4, iclass 7, count 0 2006.253.08:07:32.80#ibcon#read 4, iclass 7, count 0 2006.253.08:07:32.80#ibcon#about to read 5, iclass 7, count 0 2006.253.08:07:32.80#ibcon#read 5, iclass 7, count 0 2006.253.08:07:32.80#ibcon#about to read 6, iclass 7, count 0 2006.253.08:07:32.80#ibcon#read 6, iclass 7, count 0 2006.253.08:07:32.80#ibcon#end of sib2, iclass 7, count 0 2006.253.08:07:32.80#ibcon#*mode == 0, iclass 7, count 0 2006.253.08:07:32.80#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.253.08:07:32.80#ibcon#[27=BW32\r\n] 2006.253.08:07:32.80#ibcon#*before write, iclass 7, count 0 2006.253.08:07:32.80#ibcon#enter sib2, iclass 7, count 0 2006.253.08:07:32.80#ibcon#flushed, iclass 7, count 0 2006.253.08:07:32.80#ibcon#about to write, iclass 7, count 0 2006.253.08:07:32.80#ibcon#wrote, iclass 7, count 0 2006.253.08:07:32.80#ibcon#about to read 3, iclass 7, count 0 2006.253.08:07:32.83#ibcon#read 3, iclass 7, count 0 2006.253.08:07:32.83#ibcon#about to read 4, iclass 7, count 0 2006.253.08:07:32.83#ibcon#read 4, iclass 7, count 0 2006.253.08:07:32.83#ibcon#about to read 5, iclass 7, count 0 2006.253.08:07:32.83#ibcon#read 5, iclass 7, count 0 2006.253.08:07:32.83#ibcon#about to read 6, iclass 7, count 0 2006.253.08:07:32.83#ibcon#read 6, iclass 7, count 0 2006.253.08:07:32.83#ibcon#end of sib2, iclass 7, count 0 2006.253.08:07:32.83#ibcon#*after write, iclass 7, count 0 2006.253.08:07:32.83#ibcon#*before return 0, iclass 7, count 0 2006.253.08:07:32.83#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.253.08:07:32.83#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.253.08:07:32.83#ibcon#about to clear, iclass 7 cls_cnt 0 2006.253.08:07:32.83#ibcon#cleared, iclass 7 cls_cnt 0 2006.253.08:07:32.83$4f8m12a/ifd4f 2006.253.08:07:32.83$ifd4f/lo= 2006.253.08:07:32.83$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.253.08:07:32.83$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.253.08:07:32.83$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.253.08:07:32.83$ifd4f/patch= 2006.253.08:07:32.83$ifd4f/patch=lo1,a1,a2,a3,a4 2006.253.08:07:32.83$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.253.08:07:32.83$ifd4f/patch=lo3,a5,a6,a7,a8 2006.253.08:07:32.83$4f8m12a/"form=m,16.000,1:2 2006.253.08:07:32.83$4f8m12a/"tpicd 2006.253.08:07:32.83$4f8m12a/echo=off 2006.253.08:07:32.83$4f8m12a/xlog=off 2006.253.08:07:32.83:!2006.253.08:08:00 2006.253.08:07:45.14#trakl#Source acquired 2006.253.08:07:45.14#flagr#flagr/antenna,acquired 2006.253.08:08:00.00:preob 2006.253.08:08:01.14/onsource/TRACKING 2006.253.08:08:01.14:!2006.253.08:08:10 2006.253.08:08:10.00:data_valid=on 2006.253.08:08:10.00:midob 2006.253.08:08:10.14/onsource/TRACKING 2006.253.08:08:10.14/wx/31.00,1006.4,74 2006.253.08:08:10.35/cable/+6.3685E-03 2006.253.08:08:11.44/va/01,08,usb,yes,31,32 2006.253.08:08:11.44/va/02,07,usb,yes,31,32 2006.253.08:08:11.44/va/03,06,usb,yes,33,33 2006.253.08:08:11.44/va/04,07,usb,yes,32,35 2006.253.08:08:11.44/va/05,07,usb,yes,33,35 2006.253.08:08:11.44/va/06,07,usb,yes,29,29 2006.253.08:08:11.44/va/07,07,usb,yes,29,29 2006.253.08:08:11.44/va/08,07,usb,yes,31,31 2006.253.08:08:11.67/valo/01,532.99,yes,locked 2006.253.08:08:11.67/valo/02,572.99,yes,locked 2006.253.08:08:11.67/valo/03,672.99,yes,locked 2006.253.08:08:11.67/valo/04,832.99,yes,locked 2006.253.08:08:11.67/valo/05,652.99,yes,locked 2006.253.08:08:11.67/valo/06,772.99,yes,locked 2006.253.08:08:11.67/valo/07,832.99,yes,locked 2006.253.08:08:11.67/valo/08,852.99,yes,locked 2006.253.08:08:12.76/vb/01,04,usb,yes,30,29 2006.253.08:08:12.76/vb/02,05,usb,yes,28,29 2006.253.08:08:12.76/vb/03,04,usb,yes,28,32 2006.253.08:08:12.76/vb/04,04,usb,yes,29,29 2006.253.08:08:12.76/vb/05,04,usb,yes,27,31 2006.253.08:08:12.76/vb/06,04,usb,yes,28,31 2006.253.08:08:12.76/vb/07,04,usb,yes,31,30 2006.253.08:08:12.76/vb/08,04,usb,yes,28,31 2006.253.08:08:12.99/vblo/01,632.99,yes,locked 2006.253.08:08:12.99/vblo/02,640.99,yes,locked 2006.253.08:08:12.99/vblo/03,656.99,yes,locked 2006.253.08:08:12.99/vblo/04,712.99,yes,locked 2006.253.08:08:12.99/vblo/05,744.99,yes,locked 2006.253.08:08:12.99/vblo/06,752.99,yes,locked 2006.253.08:08:12.99/vblo/07,734.99,yes,locked 2006.253.08:08:12.99/vblo/08,744.99,yes,locked 2006.253.08:08:13.14/vabw/8 2006.253.08:08:13.29/vbbw/8 2006.253.08:08:13.38/xfe/off,on,14.5 2006.253.08:08:13.76/ifatt/23,28,28,28 2006.253.08:08:14.08/fmout-gps/S +4.76E-07 2006.253.08:08:14.12:!2006.253.08:09:10 2006.253.08:09:10.00:data_valid=off 2006.253.08:09:10.00:postob 2006.253.08:09:10.12/cable/+6.3675E-03 2006.253.08:09:10.12/wx/30.98,1006.5,74 2006.253.08:09:11.08/fmout-gps/S +4.76E-07 2006.253.08:09:11.08:scan_name=253-0810,k06253,60 2006.253.08:09:11.08:source=3c371,180650.68,694928.1,2000.0,cw 2006.253.08:09:11.14#flagr#flagr/antenna,new-source 2006.253.08:09:12.14:checkk5 2006.253.08:09:12.53/chk_autoobs//k5ts1/ autoobs is running! 2006.253.08:09:12.90/chk_autoobs//k5ts2/ autoobs is running! 2006.253.08:09:13.28/chk_autoobs//k5ts3/ autoobs is running! 2006.253.08:09:13.66/chk_autoobs//k5ts4/ autoobs is running! 2006.253.08:09:14.02/chk_obsdata//k5ts1/T2530808??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.08:09:14.39/chk_obsdata//k5ts2/T2530808??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.08:09:14.77/chk_obsdata//k5ts3/T2530808??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.08:09:15.14/chk_obsdata//k5ts4/T2530808??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.08:09:15.84/k5log//k5ts1_log_newline 2006.253.08:09:16.53/k5log//k5ts2_log_newline 2006.253.08:09:17.23/k5log//k5ts3_log_newline 2006.253.08:09:17.92/k5log//k5ts4_log_newline 2006.253.08:09:17.95/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.253.08:09:17.95:4f8m12a=2 2006.253.08:09:17.95$4f8m12a/echo=on 2006.253.08:09:17.95$4f8m12a/pcalon 2006.253.08:09:17.95$pcalon/"no phase cal control is implemented here 2006.253.08:09:17.95$4f8m12a/"tpicd=stop 2006.253.08:09:17.95$4f8m12a/vc4f8 2006.253.08:09:17.95$vc4f8/valo=1,532.99 2006.253.08:09:17.95#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.253.08:09:17.95#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.253.08:09:17.95#ibcon#ireg 17 cls_cnt 0 2006.253.08:09:17.95#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.253.08:09:17.95#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.253.08:09:17.95#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.253.08:09:17.95#ibcon#enter wrdev, iclass 19, count 0 2006.253.08:09:17.95#ibcon#first serial, iclass 19, count 0 2006.253.08:09:17.95#ibcon#enter sib2, iclass 19, count 0 2006.253.08:09:17.95#ibcon#flushed, iclass 19, count 0 2006.253.08:09:17.95#ibcon#about to write, iclass 19, count 0 2006.253.08:09:17.95#ibcon#wrote, iclass 19, count 0 2006.253.08:09:17.95#ibcon#about to read 3, iclass 19, count 0 2006.253.08:09:17.99#ibcon#read 3, iclass 19, count 0 2006.253.08:09:17.99#ibcon#about to read 4, iclass 19, count 0 2006.253.08:09:17.99#ibcon#read 4, iclass 19, count 0 2006.253.08:09:17.99#ibcon#about to read 5, iclass 19, count 0 2006.253.08:09:17.99#ibcon#read 5, iclass 19, count 0 2006.253.08:09:17.99#ibcon#about to read 6, iclass 19, count 0 2006.253.08:09:17.99#ibcon#read 6, iclass 19, count 0 2006.253.08:09:17.99#ibcon#end of sib2, iclass 19, count 0 2006.253.08:09:17.99#ibcon#*mode == 0, iclass 19, count 0 2006.253.08:09:17.99#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.253.08:09:17.99#ibcon#[26=FRQ=01,532.99\r\n] 2006.253.08:09:17.99#ibcon#*before write, iclass 19, count 0 2006.253.08:09:17.99#ibcon#enter sib2, iclass 19, count 0 2006.253.08:09:17.99#ibcon#flushed, iclass 19, count 0 2006.253.08:09:17.99#ibcon#about to write, iclass 19, count 0 2006.253.08:09:17.99#ibcon#wrote, iclass 19, count 0 2006.253.08:09:17.99#ibcon#about to read 3, iclass 19, count 0 2006.253.08:09:18.01#abcon#[5=S1D000X0/0*\r\n] 2006.253.08:09:18.04#ibcon#read 3, iclass 19, count 0 2006.253.08:09:18.04#ibcon#about to read 4, iclass 19, count 0 2006.253.08:09:18.04#ibcon#read 4, iclass 19, count 0 2006.253.08:09:18.04#ibcon#about to read 5, iclass 19, count 0 2006.253.08:09:18.04#ibcon#read 5, iclass 19, count 0 2006.253.08:09:18.04#ibcon#about to read 6, iclass 19, count 0 2006.253.08:09:18.04#ibcon#read 6, iclass 19, count 0 2006.253.08:09:18.04#ibcon#end of sib2, iclass 19, count 0 2006.253.08:09:18.04#ibcon#*after write, iclass 19, count 0 2006.253.08:09:18.04#ibcon#*before return 0, iclass 19, count 0 2006.253.08:09:18.04#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.253.08:09:18.04#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.253.08:09:18.04#ibcon#about to clear, iclass 19 cls_cnt 0 2006.253.08:09:18.04#ibcon#cleared, iclass 19 cls_cnt 0 2006.253.08:09:18.04$vc4f8/va=1,8 2006.253.08:09:18.04#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.253.08:09:18.04#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.253.08:09:18.04#ibcon#ireg 11 cls_cnt 2 2006.253.08:09:18.04#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.253.08:09:18.04#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.253.08:09:18.04#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.253.08:09:18.04#ibcon#enter wrdev, iclass 22, count 2 2006.253.08:09:18.04#ibcon#first serial, iclass 22, count 2 2006.253.08:09:18.04#ibcon#enter sib2, iclass 22, count 2 2006.253.08:09:18.04#ibcon#flushed, iclass 22, count 2 2006.253.08:09:18.04#ibcon#about to write, iclass 22, count 2 2006.253.08:09:18.04#ibcon#wrote, iclass 22, count 2 2006.253.08:09:18.04#ibcon#about to read 3, iclass 22, count 2 2006.253.08:09:18.06#ibcon#read 3, iclass 22, count 2 2006.253.08:09:18.06#ibcon#about to read 4, iclass 22, count 2 2006.253.08:09:18.06#ibcon#read 4, iclass 22, count 2 2006.253.08:09:18.06#ibcon#about to read 5, iclass 22, count 2 2006.253.08:09:18.06#ibcon#read 5, iclass 22, count 2 2006.253.08:09:18.06#ibcon#about to read 6, iclass 22, count 2 2006.253.08:09:18.06#ibcon#read 6, iclass 22, count 2 2006.253.08:09:18.06#ibcon#end of sib2, iclass 22, count 2 2006.253.08:09:18.06#ibcon#*mode == 0, iclass 22, count 2 2006.253.08:09:18.06#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.253.08:09:18.06#ibcon#[25=AT01-08\r\n] 2006.253.08:09:18.06#ibcon#*before write, iclass 22, count 2 2006.253.08:09:18.06#ibcon#enter sib2, iclass 22, count 2 2006.253.08:09:18.06#ibcon#flushed, iclass 22, count 2 2006.253.08:09:18.06#ibcon#about to write, iclass 22, count 2 2006.253.08:09:18.06#ibcon#wrote, iclass 22, count 2 2006.253.08:09:18.06#ibcon#about to read 3, iclass 22, count 2 2006.253.08:09:18.09#ibcon#read 3, iclass 22, count 2 2006.253.08:09:18.09#ibcon#about to read 4, iclass 22, count 2 2006.253.08:09:18.09#ibcon#read 4, iclass 22, count 2 2006.253.08:09:18.09#ibcon#about to read 5, iclass 22, count 2 2006.253.08:09:18.09#ibcon#read 5, iclass 22, count 2 2006.253.08:09:18.09#ibcon#about to read 6, iclass 22, count 2 2006.253.08:09:18.09#ibcon#read 6, iclass 22, count 2 2006.253.08:09:18.09#ibcon#end of sib2, iclass 22, count 2 2006.253.08:09:18.09#ibcon#*after write, iclass 22, count 2 2006.253.08:09:18.09#ibcon#*before return 0, iclass 22, count 2 2006.253.08:09:18.09#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.253.08:09:18.09#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.253.08:09:18.09#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.253.08:09:18.09#ibcon#ireg 7 cls_cnt 0 2006.253.08:09:18.09#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.253.08:09:18.21#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.253.08:09:18.21#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.253.08:09:18.21#ibcon#enter wrdev, iclass 22, count 0 2006.253.08:09:18.21#ibcon#first serial, iclass 22, count 0 2006.253.08:09:18.21#ibcon#enter sib2, iclass 22, count 0 2006.253.08:09:18.21#ibcon#flushed, iclass 22, count 0 2006.253.08:09:18.21#ibcon#about to write, iclass 22, count 0 2006.253.08:09:18.21#ibcon#wrote, iclass 22, count 0 2006.253.08:09:18.21#ibcon#about to read 3, iclass 22, count 0 2006.253.08:09:18.23#ibcon#read 3, iclass 22, count 0 2006.253.08:09:18.23#ibcon#about to read 4, iclass 22, count 0 2006.253.08:09:18.23#ibcon#read 4, iclass 22, count 0 2006.253.08:09:18.23#ibcon#about to read 5, iclass 22, count 0 2006.253.08:09:18.23#ibcon#read 5, iclass 22, count 0 2006.253.08:09:18.23#ibcon#about to read 6, iclass 22, count 0 2006.253.08:09:18.23#ibcon#read 6, iclass 22, count 0 2006.253.08:09:18.23#ibcon#end of sib2, iclass 22, count 0 2006.253.08:09:18.23#ibcon#*mode == 0, iclass 22, count 0 2006.253.08:09:18.23#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.253.08:09:18.23#ibcon#[25=USB\r\n] 2006.253.08:09:18.23#ibcon#*before write, iclass 22, count 0 2006.253.08:09:18.23#ibcon#enter sib2, iclass 22, count 0 2006.253.08:09:18.23#ibcon#flushed, iclass 22, count 0 2006.253.08:09:18.23#ibcon#about to write, iclass 22, count 0 2006.253.08:09:18.23#ibcon#wrote, iclass 22, count 0 2006.253.08:09:18.23#ibcon#about to read 3, iclass 22, count 0 2006.253.08:09:18.26#ibcon#read 3, iclass 22, count 0 2006.253.08:09:18.26#ibcon#about to read 4, iclass 22, count 0 2006.253.08:09:18.26#ibcon#read 4, iclass 22, count 0 2006.253.08:09:18.26#ibcon#about to read 5, iclass 22, count 0 2006.253.08:09:18.26#ibcon#read 5, iclass 22, count 0 2006.253.08:09:18.26#ibcon#about to read 6, iclass 22, count 0 2006.253.08:09:18.26#ibcon#read 6, iclass 22, count 0 2006.253.08:09:18.26#ibcon#end of sib2, iclass 22, count 0 2006.253.08:09:18.26#ibcon#*after write, iclass 22, count 0 2006.253.08:09:18.26#ibcon#*before return 0, iclass 22, count 0 2006.253.08:09:18.26#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.253.08:09:18.26#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.253.08:09:18.26#ibcon#about to clear, iclass 22 cls_cnt 0 2006.253.08:09:18.26#ibcon#cleared, iclass 22 cls_cnt 0 2006.253.08:09:18.26$vc4f8/valo=2,572.99 2006.253.08:09:18.26#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.253.08:09:18.26#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.253.08:09:18.26#ibcon#ireg 17 cls_cnt 0 2006.253.08:09:18.26#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.253.08:09:18.26#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.253.08:09:18.26#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.253.08:09:18.26#ibcon#enter wrdev, iclass 24, count 0 2006.253.08:09:18.26#ibcon#first serial, iclass 24, count 0 2006.253.08:09:18.26#ibcon#enter sib2, iclass 24, count 0 2006.253.08:09:18.26#ibcon#flushed, iclass 24, count 0 2006.253.08:09:18.26#ibcon#about to write, iclass 24, count 0 2006.253.08:09:18.26#ibcon#wrote, iclass 24, count 0 2006.253.08:09:18.26#ibcon#about to read 3, iclass 24, count 0 2006.253.08:09:18.28#ibcon#read 3, iclass 24, count 0 2006.253.08:09:18.28#ibcon#about to read 4, iclass 24, count 0 2006.253.08:09:18.28#ibcon#read 4, iclass 24, count 0 2006.253.08:09:18.28#ibcon#about to read 5, iclass 24, count 0 2006.253.08:09:18.28#ibcon#read 5, iclass 24, count 0 2006.253.08:09:18.28#ibcon#about to read 6, iclass 24, count 0 2006.253.08:09:18.28#ibcon#read 6, iclass 24, count 0 2006.253.08:09:18.28#ibcon#end of sib2, iclass 24, count 0 2006.253.08:09:18.28#ibcon#*mode == 0, iclass 24, count 0 2006.253.08:09:18.28#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.253.08:09:18.28#ibcon#[26=FRQ=02,572.99\r\n] 2006.253.08:09:18.28#ibcon#*before write, iclass 24, count 0 2006.253.08:09:18.28#ibcon#enter sib2, iclass 24, count 0 2006.253.08:09:18.28#ibcon#flushed, iclass 24, count 0 2006.253.08:09:18.28#ibcon#about to write, iclass 24, count 0 2006.253.08:09:18.28#ibcon#wrote, iclass 24, count 0 2006.253.08:09:18.28#ibcon#about to read 3, iclass 24, count 0 2006.253.08:09:18.33#ibcon#read 3, iclass 24, count 0 2006.253.08:09:18.33#ibcon#about to read 4, iclass 24, count 0 2006.253.08:09:18.33#ibcon#read 4, iclass 24, count 0 2006.253.08:09:18.33#ibcon#about to read 5, iclass 24, count 0 2006.253.08:09:18.33#ibcon#read 5, iclass 24, count 0 2006.253.08:09:18.33#ibcon#about to read 6, iclass 24, count 0 2006.253.08:09:18.33#ibcon#read 6, iclass 24, count 0 2006.253.08:09:18.33#ibcon#end of sib2, iclass 24, count 0 2006.253.08:09:18.33#ibcon#*after write, iclass 24, count 0 2006.253.08:09:18.33#ibcon#*before return 0, iclass 24, count 0 2006.253.08:09:18.33#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.253.08:09:18.33#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.253.08:09:18.33#ibcon#about to clear, iclass 24 cls_cnt 0 2006.253.08:09:18.33#ibcon#cleared, iclass 24 cls_cnt 0 2006.253.08:09:18.33$vc4f8/va=2,7 2006.253.08:09:18.33#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.253.08:09:18.33#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.253.08:09:18.33#ibcon#ireg 11 cls_cnt 2 2006.253.08:09:18.33#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.253.08:09:18.38#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.253.08:09:18.38#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.253.08:09:18.38#ibcon#enter wrdev, iclass 26, count 2 2006.253.08:09:18.38#ibcon#first serial, iclass 26, count 2 2006.253.08:09:18.38#ibcon#enter sib2, iclass 26, count 2 2006.253.08:09:18.38#ibcon#flushed, iclass 26, count 2 2006.253.08:09:18.38#ibcon#about to write, iclass 26, count 2 2006.253.08:09:18.38#ibcon#wrote, iclass 26, count 2 2006.253.08:09:18.38#ibcon#about to read 3, iclass 26, count 2 2006.253.08:09:18.40#ibcon#read 3, iclass 26, count 2 2006.253.08:09:18.40#ibcon#about to read 4, iclass 26, count 2 2006.253.08:09:18.40#ibcon#read 4, iclass 26, count 2 2006.253.08:09:18.40#ibcon#about to read 5, iclass 26, count 2 2006.253.08:09:18.40#ibcon#read 5, iclass 26, count 2 2006.253.08:09:18.40#ibcon#about to read 6, iclass 26, count 2 2006.253.08:09:18.40#ibcon#read 6, iclass 26, count 2 2006.253.08:09:18.40#ibcon#end of sib2, iclass 26, count 2 2006.253.08:09:18.40#ibcon#*mode == 0, iclass 26, count 2 2006.253.08:09:18.40#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.253.08:09:18.40#ibcon#[25=AT02-07\r\n] 2006.253.08:09:18.40#ibcon#*before write, iclass 26, count 2 2006.253.08:09:18.40#ibcon#enter sib2, iclass 26, count 2 2006.253.08:09:18.40#ibcon#flushed, iclass 26, count 2 2006.253.08:09:18.40#ibcon#about to write, iclass 26, count 2 2006.253.08:09:18.40#ibcon#wrote, iclass 26, count 2 2006.253.08:09:18.40#ibcon#about to read 3, iclass 26, count 2 2006.253.08:09:18.43#ibcon#read 3, iclass 26, count 2 2006.253.08:09:18.43#ibcon#about to read 4, iclass 26, count 2 2006.253.08:09:18.43#ibcon#read 4, iclass 26, count 2 2006.253.08:09:18.43#ibcon#about to read 5, iclass 26, count 2 2006.253.08:09:18.43#ibcon#read 5, iclass 26, count 2 2006.253.08:09:18.43#ibcon#about to read 6, iclass 26, count 2 2006.253.08:09:18.43#ibcon#read 6, iclass 26, count 2 2006.253.08:09:18.43#ibcon#end of sib2, iclass 26, count 2 2006.253.08:09:18.43#ibcon#*after write, iclass 26, count 2 2006.253.08:09:18.43#ibcon#*before return 0, iclass 26, count 2 2006.253.08:09:18.43#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.253.08:09:18.43#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.253.08:09:18.43#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.253.08:09:18.43#ibcon#ireg 7 cls_cnt 0 2006.253.08:09:18.43#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.253.08:09:18.55#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.253.08:09:18.55#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.253.08:09:18.55#ibcon#enter wrdev, iclass 26, count 0 2006.253.08:09:18.55#ibcon#first serial, iclass 26, count 0 2006.253.08:09:18.55#ibcon#enter sib2, iclass 26, count 0 2006.253.08:09:18.55#ibcon#flushed, iclass 26, count 0 2006.253.08:09:18.55#ibcon#about to write, iclass 26, count 0 2006.253.08:09:18.55#ibcon#wrote, iclass 26, count 0 2006.253.08:09:18.55#ibcon#about to read 3, iclass 26, count 0 2006.253.08:09:18.57#ibcon#read 3, iclass 26, count 0 2006.253.08:09:18.57#ibcon#about to read 4, iclass 26, count 0 2006.253.08:09:18.57#ibcon#read 4, iclass 26, count 0 2006.253.08:09:18.57#ibcon#about to read 5, iclass 26, count 0 2006.253.08:09:18.57#ibcon#read 5, iclass 26, count 0 2006.253.08:09:18.57#ibcon#about to read 6, iclass 26, count 0 2006.253.08:09:18.57#ibcon#read 6, iclass 26, count 0 2006.253.08:09:18.57#ibcon#end of sib2, iclass 26, count 0 2006.253.08:09:18.57#ibcon#*mode == 0, iclass 26, count 0 2006.253.08:09:18.57#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.253.08:09:18.57#ibcon#[25=USB\r\n] 2006.253.08:09:18.57#ibcon#*before write, iclass 26, count 0 2006.253.08:09:18.57#ibcon#enter sib2, iclass 26, count 0 2006.253.08:09:18.57#ibcon#flushed, iclass 26, count 0 2006.253.08:09:18.57#ibcon#about to write, iclass 26, count 0 2006.253.08:09:18.57#ibcon#wrote, iclass 26, count 0 2006.253.08:09:18.57#ibcon#about to read 3, iclass 26, count 0 2006.253.08:09:18.60#ibcon#read 3, iclass 26, count 0 2006.253.08:09:18.60#ibcon#about to read 4, iclass 26, count 0 2006.253.08:09:18.60#ibcon#read 4, iclass 26, count 0 2006.253.08:09:18.60#ibcon#about to read 5, iclass 26, count 0 2006.253.08:09:18.60#ibcon#read 5, iclass 26, count 0 2006.253.08:09:18.60#ibcon#about to read 6, iclass 26, count 0 2006.253.08:09:18.60#ibcon#read 6, iclass 26, count 0 2006.253.08:09:18.60#ibcon#end of sib2, iclass 26, count 0 2006.253.08:09:18.60#ibcon#*after write, iclass 26, count 0 2006.253.08:09:18.60#ibcon#*before return 0, iclass 26, count 0 2006.253.08:09:18.60#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.253.08:09:18.60#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.253.08:09:18.60#ibcon#about to clear, iclass 26 cls_cnt 0 2006.253.08:09:18.60#ibcon#cleared, iclass 26 cls_cnt 0 2006.253.08:09:18.60$vc4f8/valo=3,672.99 2006.253.08:09:18.60#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.253.08:09:18.60#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.253.08:09:18.60#ibcon#ireg 17 cls_cnt 0 2006.253.08:09:18.60#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.253.08:09:18.60#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.253.08:09:18.60#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.253.08:09:18.60#ibcon#enter wrdev, iclass 28, count 0 2006.253.08:09:18.60#ibcon#first serial, iclass 28, count 0 2006.253.08:09:18.60#ibcon#enter sib2, iclass 28, count 0 2006.253.08:09:18.60#ibcon#flushed, iclass 28, count 0 2006.253.08:09:18.60#ibcon#about to write, iclass 28, count 0 2006.253.08:09:18.60#ibcon#wrote, iclass 28, count 0 2006.253.08:09:18.60#ibcon#about to read 3, iclass 28, count 0 2006.253.08:09:18.62#ibcon#read 3, iclass 28, count 0 2006.253.08:09:18.62#ibcon#about to read 4, iclass 28, count 0 2006.253.08:09:18.62#ibcon#read 4, iclass 28, count 0 2006.253.08:09:18.62#ibcon#about to read 5, iclass 28, count 0 2006.253.08:09:18.62#ibcon#read 5, iclass 28, count 0 2006.253.08:09:18.62#ibcon#about to read 6, iclass 28, count 0 2006.253.08:09:18.62#ibcon#read 6, iclass 28, count 0 2006.253.08:09:18.62#ibcon#end of sib2, iclass 28, count 0 2006.253.08:09:18.62#ibcon#*mode == 0, iclass 28, count 0 2006.253.08:09:18.62#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.253.08:09:18.62#ibcon#[26=FRQ=03,672.99\r\n] 2006.253.08:09:18.62#ibcon#*before write, iclass 28, count 0 2006.253.08:09:18.62#ibcon#enter sib2, iclass 28, count 0 2006.253.08:09:18.62#ibcon#flushed, iclass 28, count 0 2006.253.08:09:18.62#ibcon#about to write, iclass 28, count 0 2006.253.08:09:18.62#ibcon#wrote, iclass 28, count 0 2006.253.08:09:18.62#ibcon#about to read 3, iclass 28, count 0 2006.253.08:09:18.67#ibcon#read 3, iclass 28, count 0 2006.253.08:09:18.67#ibcon#about to read 4, iclass 28, count 0 2006.253.08:09:18.67#ibcon#read 4, iclass 28, count 0 2006.253.08:09:18.67#ibcon#about to read 5, iclass 28, count 0 2006.253.08:09:18.67#ibcon#read 5, iclass 28, count 0 2006.253.08:09:18.67#ibcon#about to read 6, iclass 28, count 0 2006.253.08:09:18.67#ibcon#read 6, iclass 28, count 0 2006.253.08:09:18.67#ibcon#end of sib2, iclass 28, count 0 2006.253.08:09:18.67#ibcon#*after write, iclass 28, count 0 2006.253.08:09:18.67#ibcon#*before return 0, iclass 28, count 0 2006.253.08:09:18.67#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.253.08:09:18.67#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.253.08:09:18.67#ibcon#about to clear, iclass 28 cls_cnt 0 2006.253.08:09:18.67#ibcon#cleared, iclass 28 cls_cnt 0 2006.253.08:09:18.67$vc4f8/va=3,6 2006.253.08:09:18.67#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.253.08:09:18.67#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.253.08:09:18.67#ibcon#ireg 11 cls_cnt 2 2006.253.08:09:18.67#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.253.08:09:18.72#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.253.08:09:18.72#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.253.08:09:18.72#ibcon#enter wrdev, iclass 30, count 2 2006.253.08:09:18.72#ibcon#first serial, iclass 30, count 2 2006.253.08:09:18.72#ibcon#enter sib2, iclass 30, count 2 2006.253.08:09:18.72#ibcon#flushed, iclass 30, count 2 2006.253.08:09:18.72#ibcon#about to write, iclass 30, count 2 2006.253.08:09:18.72#ibcon#wrote, iclass 30, count 2 2006.253.08:09:18.72#ibcon#about to read 3, iclass 30, count 2 2006.253.08:09:18.74#ibcon#read 3, iclass 30, count 2 2006.253.08:09:18.74#ibcon#about to read 4, iclass 30, count 2 2006.253.08:09:18.74#ibcon#read 4, iclass 30, count 2 2006.253.08:09:18.74#ibcon#about to read 5, iclass 30, count 2 2006.253.08:09:18.74#ibcon#read 5, iclass 30, count 2 2006.253.08:09:18.74#ibcon#about to read 6, iclass 30, count 2 2006.253.08:09:18.74#ibcon#read 6, iclass 30, count 2 2006.253.08:09:18.74#ibcon#end of sib2, iclass 30, count 2 2006.253.08:09:18.74#ibcon#*mode == 0, iclass 30, count 2 2006.253.08:09:18.74#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.253.08:09:18.74#ibcon#[25=AT03-06\r\n] 2006.253.08:09:18.74#ibcon#*before write, iclass 30, count 2 2006.253.08:09:18.74#ibcon#enter sib2, iclass 30, count 2 2006.253.08:09:18.74#ibcon#flushed, iclass 30, count 2 2006.253.08:09:18.74#ibcon#about to write, iclass 30, count 2 2006.253.08:09:18.74#ibcon#wrote, iclass 30, count 2 2006.253.08:09:18.74#ibcon#about to read 3, iclass 30, count 2 2006.253.08:09:18.77#ibcon#read 3, iclass 30, count 2 2006.253.08:09:18.77#ibcon#about to read 4, iclass 30, count 2 2006.253.08:09:18.77#ibcon#read 4, iclass 30, count 2 2006.253.08:09:18.77#ibcon#about to read 5, iclass 30, count 2 2006.253.08:09:18.77#ibcon#read 5, iclass 30, count 2 2006.253.08:09:18.77#ibcon#about to read 6, iclass 30, count 2 2006.253.08:09:18.77#ibcon#read 6, iclass 30, count 2 2006.253.08:09:18.77#ibcon#end of sib2, iclass 30, count 2 2006.253.08:09:18.77#ibcon#*after write, iclass 30, count 2 2006.253.08:09:18.77#ibcon#*before return 0, iclass 30, count 2 2006.253.08:09:18.77#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.253.08:09:18.77#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.253.08:09:18.77#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.253.08:09:18.77#ibcon#ireg 7 cls_cnt 0 2006.253.08:09:18.77#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.253.08:09:18.89#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.253.08:09:18.89#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.253.08:09:18.89#ibcon#enter wrdev, iclass 30, count 0 2006.253.08:09:18.89#ibcon#first serial, iclass 30, count 0 2006.253.08:09:18.89#ibcon#enter sib2, iclass 30, count 0 2006.253.08:09:18.89#ibcon#flushed, iclass 30, count 0 2006.253.08:09:18.89#ibcon#about to write, iclass 30, count 0 2006.253.08:09:18.89#ibcon#wrote, iclass 30, count 0 2006.253.08:09:18.89#ibcon#about to read 3, iclass 30, count 0 2006.253.08:09:18.91#ibcon#read 3, iclass 30, count 0 2006.253.08:09:18.91#ibcon#about to read 4, iclass 30, count 0 2006.253.08:09:18.91#ibcon#read 4, iclass 30, count 0 2006.253.08:09:18.91#ibcon#about to read 5, iclass 30, count 0 2006.253.08:09:18.91#ibcon#read 5, iclass 30, count 0 2006.253.08:09:18.91#ibcon#about to read 6, iclass 30, count 0 2006.253.08:09:18.91#ibcon#read 6, iclass 30, count 0 2006.253.08:09:18.91#ibcon#end of sib2, iclass 30, count 0 2006.253.08:09:18.91#ibcon#*mode == 0, iclass 30, count 0 2006.253.08:09:18.91#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.253.08:09:18.91#ibcon#[25=USB\r\n] 2006.253.08:09:18.91#ibcon#*before write, iclass 30, count 0 2006.253.08:09:18.91#ibcon#enter sib2, iclass 30, count 0 2006.253.08:09:18.91#ibcon#flushed, iclass 30, count 0 2006.253.08:09:18.91#ibcon#about to write, iclass 30, count 0 2006.253.08:09:18.91#ibcon#wrote, iclass 30, count 0 2006.253.08:09:18.91#ibcon#about to read 3, iclass 30, count 0 2006.253.08:09:18.94#ibcon#read 3, iclass 30, count 0 2006.253.08:09:18.94#ibcon#about to read 4, iclass 30, count 0 2006.253.08:09:18.94#ibcon#read 4, iclass 30, count 0 2006.253.08:09:18.94#ibcon#about to read 5, iclass 30, count 0 2006.253.08:09:18.94#ibcon#read 5, iclass 30, count 0 2006.253.08:09:18.94#ibcon#about to read 6, iclass 30, count 0 2006.253.08:09:18.94#ibcon#read 6, iclass 30, count 0 2006.253.08:09:18.94#ibcon#end of sib2, iclass 30, count 0 2006.253.08:09:18.94#ibcon#*after write, iclass 30, count 0 2006.253.08:09:18.94#ibcon#*before return 0, iclass 30, count 0 2006.253.08:09:18.94#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.253.08:09:18.94#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.253.08:09:18.94#ibcon#about to clear, iclass 30 cls_cnt 0 2006.253.08:09:18.94#ibcon#cleared, iclass 30 cls_cnt 0 2006.253.08:09:18.94$vc4f8/valo=4,832.99 2006.253.08:09:18.94#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.253.08:09:18.94#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.253.08:09:18.94#ibcon#ireg 17 cls_cnt 0 2006.253.08:09:18.94#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.253.08:09:18.94#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.253.08:09:18.94#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.253.08:09:18.94#ibcon#enter wrdev, iclass 32, count 0 2006.253.08:09:18.94#ibcon#first serial, iclass 32, count 0 2006.253.08:09:18.94#ibcon#enter sib2, iclass 32, count 0 2006.253.08:09:18.94#ibcon#flushed, iclass 32, count 0 2006.253.08:09:18.94#ibcon#about to write, iclass 32, count 0 2006.253.08:09:18.94#ibcon#wrote, iclass 32, count 0 2006.253.08:09:18.94#ibcon#about to read 3, iclass 32, count 0 2006.253.08:09:18.96#ibcon#read 3, iclass 32, count 0 2006.253.08:09:18.96#ibcon#about to read 4, iclass 32, count 0 2006.253.08:09:18.96#ibcon#read 4, iclass 32, count 0 2006.253.08:09:18.96#ibcon#about to read 5, iclass 32, count 0 2006.253.08:09:18.96#ibcon#read 5, iclass 32, count 0 2006.253.08:09:18.96#ibcon#about to read 6, iclass 32, count 0 2006.253.08:09:18.96#ibcon#read 6, iclass 32, count 0 2006.253.08:09:18.96#ibcon#end of sib2, iclass 32, count 0 2006.253.08:09:18.96#ibcon#*mode == 0, iclass 32, count 0 2006.253.08:09:18.96#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.253.08:09:18.96#ibcon#[26=FRQ=04,832.99\r\n] 2006.253.08:09:18.96#ibcon#*before write, iclass 32, count 0 2006.253.08:09:18.96#ibcon#enter sib2, iclass 32, count 0 2006.253.08:09:18.96#ibcon#flushed, iclass 32, count 0 2006.253.08:09:18.96#ibcon#about to write, iclass 32, count 0 2006.253.08:09:18.96#ibcon#wrote, iclass 32, count 0 2006.253.08:09:18.96#ibcon#about to read 3, iclass 32, count 0 2006.253.08:09:19.01#ibcon#read 3, iclass 32, count 0 2006.253.08:09:19.01#ibcon#about to read 4, iclass 32, count 0 2006.253.08:09:19.01#ibcon#read 4, iclass 32, count 0 2006.253.08:09:19.01#ibcon#about to read 5, iclass 32, count 0 2006.253.08:09:19.01#ibcon#read 5, iclass 32, count 0 2006.253.08:09:19.01#ibcon#about to read 6, iclass 32, count 0 2006.253.08:09:19.01#ibcon#read 6, iclass 32, count 0 2006.253.08:09:19.01#ibcon#end of sib2, iclass 32, count 0 2006.253.08:09:19.01#ibcon#*after write, iclass 32, count 0 2006.253.08:09:19.01#ibcon#*before return 0, iclass 32, count 0 2006.253.08:09:19.01#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.253.08:09:19.01#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.253.08:09:19.01#ibcon#about to clear, iclass 32 cls_cnt 0 2006.253.08:09:19.01#ibcon#cleared, iclass 32 cls_cnt 0 2006.253.08:09:19.01$vc4f8/va=4,7 2006.253.08:09:19.01#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.253.08:09:19.01#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.253.08:09:19.01#ibcon#ireg 11 cls_cnt 2 2006.253.08:09:19.01#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.253.08:09:19.06#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.253.08:09:19.06#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.253.08:09:19.06#ibcon#enter wrdev, iclass 34, count 2 2006.253.08:09:19.06#ibcon#first serial, iclass 34, count 2 2006.253.08:09:19.06#ibcon#enter sib2, iclass 34, count 2 2006.253.08:09:19.06#ibcon#flushed, iclass 34, count 2 2006.253.08:09:19.06#ibcon#about to write, iclass 34, count 2 2006.253.08:09:19.06#ibcon#wrote, iclass 34, count 2 2006.253.08:09:19.06#ibcon#about to read 3, iclass 34, count 2 2006.253.08:09:19.08#ibcon#read 3, iclass 34, count 2 2006.253.08:09:19.08#ibcon#about to read 4, iclass 34, count 2 2006.253.08:09:19.08#ibcon#read 4, iclass 34, count 2 2006.253.08:09:19.08#ibcon#about to read 5, iclass 34, count 2 2006.253.08:09:19.08#ibcon#read 5, iclass 34, count 2 2006.253.08:09:19.08#ibcon#about to read 6, iclass 34, count 2 2006.253.08:09:19.08#ibcon#read 6, iclass 34, count 2 2006.253.08:09:19.08#ibcon#end of sib2, iclass 34, count 2 2006.253.08:09:19.08#ibcon#*mode == 0, iclass 34, count 2 2006.253.08:09:19.08#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.253.08:09:19.08#ibcon#[25=AT04-07\r\n] 2006.253.08:09:19.08#ibcon#*before write, iclass 34, count 2 2006.253.08:09:19.08#ibcon#enter sib2, iclass 34, count 2 2006.253.08:09:19.08#ibcon#flushed, iclass 34, count 2 2006.253.08:09:19.08#ibcon#about to write, iclass 34, count 2 2006.253.08:09:19.08#ibcon#wrote, iclass 34, count 2 2006.253.08:09:19.08#ibcon#about to read 3, iclass 34, count 2 2006.253.08:09:19.11#ibcon#read 3, iclass 34, count 2 2006.253.08:09:19.11#ibcon#about to read 4, iclass 34, count 2 2006.253.08:09:19.11#ibcon#read 4, iclass 34, count 2 2006.253.08:09:19.11#ibcon#about to read 5, iclass 34, count 2 2006.253.08:09:19.11#ibcon#read 5, iclass 34, count 2 2006.253.08:09:19.11#ibcon#about to read 6, iclass 34, count 2 2006.253.08:09:19.11#ibcon#read 6, iclass 34, count 2 2006.253.08:09:19.11#ibcon#end of sib2, iclass 34, count 2 2006.253.08:09:19.11#ibcon#*after write, iclass 34, count 2 2006.253.08:09:19.11#ibcon#*before return 0, iclass 34, count 2 2006.253.08:09:19.11#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.253.08:09:19.11#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.253.08:09:19.11#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.253.08:09:19.11#ibcon#ireg 7 cls_cnt 0 2006.253.08:09:19.11#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.253.08:09:19.23#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.253.08:09:19.23#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.253.08:09:19.23#ibcon#enter wrdev, iclass 34, count 0 2006.253.08:09:19.23#ibcon#first serial, iclass 34, count 0 2006.253.08:09:19.23#ibcon#enter sib2, iclass 34, count 0 2006.253.08:09:19.23#ibcon#flushed, iclass 34, count 0 2006.253.08:09:19.23#ibcon#about to write, iclass 34, count 0 2006.253.08:09:19.23#ibcon#wrote, iclass 34, count 0 2006.253.08:09:19.23#ibcon#about to read 3, iclass 34, count 0 2006.253.08:09:19.25#ibcon#read 3, iclass 34, count 0 2006.253.08:09:19.25#ibcon#about to read 4, iclass 34, count 0 2006.253.08:09:19.25#ibcon#read 4, iclass 34, count 0 2006.253.08:09:19.25#ibcon#about to read 5, iclass 34, count 0 2006.253.08:09:19.25#ibcon#read 5, iclass 34, count 0 2006.253.08:09:19.25#ibcon#about to read 6, iclass 34, count 0 2006.253.08:09:19.25#ibcon#read 6, iclass 34, count 0 2006.253.08:09:19.25#ibcon#end of sib2, iclass 34, count 0 2006.253.08:09:19.25#ibcon#*mode == 0, iclass 34, count 0 2006.253.08:09:19.25#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.253.08:09:19.25#ibcon#[25=USB\r\n] 2006.253.08:09:19.25#ibcon#*before write, iclass 34, count 0 2006.253.08:09:19.25#ibcon#enter sib2, iclass 34, count 0 2006.253.08:09:19.25#ibcon#flushed, iclass 34, count 0 2006.253.08:09:19.25#ibcon#about to write, iclass 34, count 0 2006.253.08:09:19.25#ibcon#wrote, iclass 34, count 0 2006.253.08:09:19.25#ibcon#about to read 3, iclass 34, count 0 2006.253.08:09:19.28#ibcon#read 3, iclass 34, count 0 2006.253.08:09:19.28#ibcon#about to read 4, iclass 34, count 0 2006.253.08:09:19.28#ibcon#read 4, iclass 34, count 0 2006.253.08:09:19.28#ibcon#about to read 5, iclass 34, count 0 2006.253.08:09:19.28#ibcon#read 5, iclass 34, count 0 2006.253.08:09:19.28#ibcon#about to read 6, iclass 34, count 0 2006.253.08:09:19.28#ibcon#read 6, iclass 34, count 0 2006.253.08:09:19.28#ibcon#end of sib2, iclass 34, count 0 2006.253.08:09:19.28#ibcon#*after write, iclass 34, count 0 2006.253.08:09:19.28#ibcon#*before return 0, iclass 34, count 0 2006.253.08:09:19.28#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.253.08:09:19.28#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.253.08:09:19.28#ibcon#about to clear, iclass 34 cls_cnt 0 2006.253.08:09:19.28#ibcon#cleared, iclass 34 cls_cnt 0 2006.253.08:09:19.28$vc4f8/valo=5,652.99 2006.253.08:09:19.28#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.253.08:09:19.28#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.253.08:09:19.28#ibcon#ireg 17 cls_cnt 0 2006.253.08:09:19.28#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.253.08:09:19.28#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.253.08:09:19.28#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.253.08:09:19.28#ibcon#enter wrdev, iclass 36, count 0 2006.253.08:09:19.28#ibcon#first serial, iclass 36, count 0 2006.253.08:09:19.28#ibcon#enter sib2, iclass 36, count 0 2006.253.08:09:19.28#ibcon#flushed, iclass 36, count 0 2006.253.08:09:19.28#ibcon#about to write, iclass 36, count 0 2006.253.08:09:19.28#ibcon#wrote, iclass 36, count 0 2006.253.08:09:19.28#ibcon#about to read 3, iclass 36, count 0 2006.253.08:09:19.30#ibcon#read 3, iclass 36, count 0 2006.253.08:09:19.30#ibcon#about to read 4, iclass 36, count 0 2006.253.08:09:19.30#ibcon#read 4, iclass 36, count 0 2006.253.08:09:19.30#ibcon#about to read 5, iclass 36, count 0 2006.253.08:09:19.30#ibcon#read 5, iclass 36, count 0 2006.253.08:09:19.30#ibcon#about to read 6, iclass 36, count 0 2006.253.08:09:19.30#ibcon#read 6, iclass 36, count 0 2006.253.08:09:19.30#ibcon#end of sib2, iclass 36, count 0 2006.253.08:09:19.30#ibcon#*mode == 0, iclass 36, count 0 2006.253.08:09:19.30#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.253.08:09:19.30#ibcon#[26=FRQ=05,652.99\r\n] 2006.253.08:09:19.30#ibcon#*before write, iclass 36, count 0 2006.253.08:09:19.30#ibcon#enter sib2, iclass 36, count 0 2006.253.08:09:19.30#ibcon#flushed, iclass 36, count 0 2006.253.08:09:19.30#ibcon#about to write, iclass 36, count 0 2006.253.08:09:19.30#ibcon#wrote, iclass 36, count 0 2006.253.08:09:19.30#ibcon#about to read 3, iclass 36, count 0 2006.253.08:09:19.34#ibcon#read 3, iclass 36, count 0 2006.253.08:09:19.34#ibcon#about to read 4, iclass 36, count 0 2006.253.08:09:19.34#ibcon#read 4, iclass 36, count 0 2006.253.08:09:19.34#ibcon#about to read 5, iclass 36, count 0 2006.253.08:09:19.34#ibcon#read 5, iclass 36, count 0 2006.253.08:09:19.34#ibcon#about to read 6, iclass 36, count 0 2006.253.08:09:19.34#ibcon#read 6, iclass 36, count 0 2006.253.08:09:19.34#ibcon#end of sib2, iclass 36, count 0 2006.253.08:09:19.34#ibcon#*after write, iclass 36, count 0 2006.253.08:09:19.34#ibcon#*before return 0, iclass 36, count 0 2006.253.08:09:19.34#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.253.08:09:19.34#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.253.08:09:19.34#ibcon#about to clear, iclass 36 cls_cnt 0 2006.253.08:09:19.34#ibcon#cleared, iclass 36 cls_cnt 0 2006.253.08:09:19.34$vc4f8/va=5,7 2006.253.08:09:19.34#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.253.08:09:19.34#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.253.08:09:19.34#ibcon#ireg 11 cls_cnt 2 2006.253.08:09:19.34#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.253.08:09:19.40#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.253.08:09:19.40#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.253.08:09:19.40#ibcon#enter wrdev, iclass 38, count 2 2006.253.08:09:19.40#ibcon#first serial, iclass 38, count 2 2006.253.08:09:19.40#ibcon#enter sib2, iclass 38, count 2 2006.253.08:09:19.40#ibcon#flushed, iclass 38, count 2 2006.253.08:09:19.40#ibcon#about to write, iclass 38, count 2 2006.253.08:09:19.40#ibcon#wrote, iclass 38, count 2 2006.253.08:09:19.40#ibcon#about to read 3, iclass 38, count 2 2006.253.08:09:19.42#ibcon#read 3, iclass 38, count 2 2006.253.08:09:19.42#ibcon#about to read 4, iclass 38, count 2 2006.253.08:09:19.42#ibcon#read 4, iclass 38, count 2 2006.253.08:09:19.42#ibcon#about to read 5, iclass 38, count 2 2006.253.08:09:19.42#ibcon#read 5, iclass 38, count 2 2006.253.08:09:19.42#ibcon#about to read 6, iclass 38, count 2 2006.253.08:09:19.42#ibcon#read 6, iclass 38, count 2 2006.253.08:09:19.42#ibcon#end of sib2, iclass 38, count 2 2006.253.08:09:19.42#ibcon#*mode == 0, iclass 38, count 2 2006.253.08:09:19.42#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.253.08:09:19.42#ibcon#[25=AT05-07\r\n] 2006.253.08:09:19.42#ibcon#*before write, iclass 38, count 2 2006.253.08:09:19.42#ibcon#enter sib2, iclass 38, count 2 2006.253.08:09:19.42#ibcon#flushed, iclass 38, count 2 2006.253.08:09:19.42#ibcon#about to write, iclass 38, count 2 2006.253.08:09:19.42#ibcon#wrote, iclass 38, count 2 2006.253.08:09:19.42#ibcon#about to read 3, iclass 38, count 2 2006.253.08:09:19.45#ibcon#read 3, iclass 38, count 2 2006.253.08:09:19.45#ibcon#about to read 4, iclass 38, count 2 2006.253.08:09:19.45#ibcon#read 4, iclass 38, count 2 2006.253.08:09:19.45#ibcon#about to read 5, iclass 38, count 2 2006.253.08:09:19.45#ibcon#read 5, iclass 38, count 2 2006.253.08:09:19.45#ibcon#about to read 6, iclass 38, count 2 2006.253.08:09:19.45#ibcon#read 6, iclass 38, count 2 2006.253.08:09:19.45#ibcon#end of sib2, iclass 38, count 2 2006.253.08:09:19.45#ibcon#*after write, iclass 38, count 2 2006.253.08:09:19.45#ibcon#*before return 0, iclass 38, count 2 2006.253.08:09:19.45#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.253.08:09:19.45#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.253.08:09:19.45#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.253.08:09:19.45#ibcon#ireg 7 cls_cnt 0 2006.253.08:09:19.45#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.253.08:09:19.57#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.253.08:09:19.57#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.253.08:09:19.57#ibcon#enter wrdev, iclass 38, count 0 2006.253.08:09:19.57#ibcon#first serial, iclass 38, count 0 2006.253.08:09:19.57#ibcon#enter sib2, iclass 38, count 0 2006.253.08:09:19.57#ibcon#flushed, iclass 38, count 0 2006.253.08:09:19.57#ibcon#about to write, iclass 38, count 0 2006.253.08:09:19.57#ibcon#wrote, iclass 38, count 0 2006.253.08:09:19.57#ibcon#about to read 3, iclass 38, count 0 2006.253.08:09:19.59#ibcon#read 3, iclass 38, count 0 2006.253.08:09:19.59#ibcon#about to read 4, iclass 38, count 0 2006.253.08:09:19.59#ibcon#read 4, iclass 38, count 0 2006.253.08:09:19.59#ibcon#about to read 5, iclass 38, count 0 2006.253.08:09:19.59#ibcon#read 5, iclass 38, count 0 2006.253.08:09:19.59#ibcon#about to read 6, iclass 38, count 0 2006.253.08:09:19.59#ibcon#read 6, iclass 38, count 0 2006.253.08:09:19.59#ibcon#end of sib2, iclass 38, count 0 2006.253.08:09:19.59#ibcon#*mode == 0, iclass 38, count 0 2006.253.08:09:19.59#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.253.08:09:19.59#ibcon#[25=USB\r\n] 2006.253.08:09:19.59#ibcon#*before write, iclass 38, count 0 2006.253.08:09:19.59#ibcon#enter sib2, iclass 38, count 0 2006.253.08:09:19.59#ibcon#flushed, iclass 38, count 0 2006.253.08:09:19.59#ibcon#about to write, iclass 38, count 0 2006.253.08:09:19.59#ibcon#wrote, iclass 38, count 0 2006.253.08:09:19.59#ibcon#about to read 3, iclass 38, count 0 2006.253.08:09:19.62#ibcon#read 3, iclass 38, count 0 2006.253.08:09:19.62#ibcon#about to read 4, iclass 38, count 0 2006.253.08:09:19.62#ibcon#read 4, iclass 38, count 0 2006.253.08:09:19.62#ibcon#about to read 5, iclass 38, count 0 2006.253.08:09:19.62#ibcon#read 5, iclass 38, count 0 2006.253.08:09:19.62#ibcon#about to read 6, iclass 38, count 0 2006.253.08:09:19.62#ibcon#read 6, iclass 38, count 0 2006.253.08:09:19.62#ibcon#end of sib2, iclass 38, count 0 2006.253.08:09:19.62#ibcon#*after write, iclass 38, count 0 2006.253.08:09:19.62#ibcon#*before return 0, iclass 38, count 0 2006.253.08:09:19.62#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.253.08:09:19.62#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.253.08:09:19.62#ibcon#about to clear, iclass 38 cls_cnt 0 2006.253.08:09:19.62#ibcon#cleared, iclass 38 cls_cnt 0 2006.253.08:09:19.62$vc4f8/valo=6,772.99 2006.253.08:09:19.62#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.253.08:09:19.62#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.253.08:09:19.62#ibcon#ireg 17 cls_cnt 0 2006.253.08:09:19.62#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.253.08:09:19.62#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.253.08:09:19.62#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.253.08:09:19.62#ibcon#enter wrdev, iclass 40, count 0 2006.253.08:09:19.62#ibcon#first serial, iclass 40, count 0 2006.253.08:09:19.62#ibcon#enter sib2, iclass 40, count 0 2006.253.08:09:19.62#ibcon#flushed, iclass 40, count 0 2006.253.08:09:19.62#ibcon#about to write, iclass 40, count 0 2006.253.08:09:19.62#ibcon#wrote, iclass 40, count 0 2006.253.08:09:19.62#ibcon#about to read 3, iclass 40, count 0 2006.253.08:09:19.64#ibcon#read 3, iclass 40, count 0 2006.253.08:09:19.64#ibcon#about to read 4, iclass 40, count 0 2006.253.08:09:19.64#ibcon#read 4, iclass 40, count 0 2006.253.08:09:19.64#ibcon#about to read 5, iclass 40, count 0 2006.253.08:09:19.64#ibcon#read 5, iclass 40, count 0 2006.253.08:09:19.64#ibcon#about to read 6, iclass 40, count 0 2006.253.08:09:19.64#ibcon#read 6, iclass 40, count 0 2006.253.08:09:19.64#ibcon#end of sib2, iclass 40, count 0 2006.253.08:09:19.64#ibcon#*mode == 0, iclass 40, count 0 2006.253.08:09:19.64#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.253.08:09:19.64#ibcon#[26=FRQ=06,772.99\r\n] 2006.253.08:09:19.64#ibcon#*before write, iclass 40, count 0 2006.253.08:09:19.64#ibcon#enter sib2, iclass 40, count 0 2006.253.08:09:19.64#ibcon#flushed, iclass 40, count 0 2006.253.08:09:19.64#ibcon#about to write, iclass 40, count 0 2006.253.08:09:19.64#ibcon#wrote, iclass 40, count 0 2006.253.08:09:19.64#ibcon#about to read 3, iclass 40, count 0 2006.253.08:09:19.69#ibcon#read 3, iclass 40, count 0 2006.253.08:09:19.69#ibcon#about to read 4, iclass 40, count 0 2006.253.08:09:19.69#ibcon#read 4, iclass 40, count 0 2006.253.08:09:19.69#ibcon#about to read 5, iclass 40, count 0 2006.253.08:09:19.69#ibcon#read 5, iclass 40, count 0 2006.253.08:09:19.69#ibcon#about to read 6, iclass 40, count 0 2006.253.08:09:19.69#ibcon#read 6, iclass 40, count 0 2006.253.08:09:19.69#ibcon#end of sib2, iclass 40, count 0 2006.253.08:09:19.69#ibcon#*after write, iclass 40, count 0 2006.253.08:09:19.69#ibcon#*before return 0, iclass 40, count 0 2006.253.08:09:19.69#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.253.08:09:19.69#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.253.08:09:19.69#ibcon#about to clear, iclass 40 cls_cnt 0 2006.253.08:09:19.69#ibcon#cleared, iclass 40 cls_cnt 0 2006.253.08:09:19.69$vc4f8/va=6,7 2006.253.08:09:19.69#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.253.08:09:19.69#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.253.08:09:19.69#ibcon#ireg 11 cls_cnt 2 2006.253.08:09:19.69#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.253.08:09:19.74#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.253.08:09:19.74#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.253.08:09:19.74#ibcon#enter wrdev, iclass 4, count 2 2006.253.08:09:19.74#ibcon#first serial, iclass 4, count 2 2006.253.08:09:19.74#ibcon#enter sib2, iclass 4, count 2 2006.253.08:09:19.74#ibcon#flushed, iclass 4, count 2 2006.253.08:09:19.74#ibcon#about to write, iclass 4, count 2 2006.253.08:09:19.74#ibcon#wrote, iclass 4, count 2 2006.253.08:09:19.74#ibcon#about to read 3, iclass 4, count 2 2006.253.08:09:19.76#ibcon#read 3, iclass 4, count 2 2006.253.08:09:19.76#ibcon#about to read 4, iclass 4, count 2 2006.253.08:09:19.76#ibcon#read 4, iclass 4, count 2 2006.253.08:09:19.76#ibcon#about to read 5, iclass 4, count 2 2006.253.08:09:19.76#ibcon#read 5, iclass 4, count 2 2006.253.08:09:19.76#ibcon#about to read 6, iclass 4, count 2 2006.253.08:09:19.76#ibcon#read 6, iclass 4, count 2 2006.253.08:09:19.76#ibcon#end of sib2, iclass 4, count 2 2006.253.08:09:19.76#ibcon#*mode == 0, iclass 4, count 2 2006.253.08:09:19.76#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.253.08:09:19.76#ibcon#[25=AT06-07\r\n] 2006.253.08:09:19.76#ibcon#*before write, iclass 4, count 2 2006.253.08:09:19.76#ibcon#enter sib2, iclass 4, count 2 2006.253.08:09:19.76#ibcon#flushed, iclass 4, count 2 2006.253.08:09:19.76#ibcon#about to write, iclass 4, count 2 2006.253.08:09:19.76#ibcon#wrote, iclass 4, count 2 2006.253.08:09:19.76#ibcon#about to read 3, iclass 4, count 2 2006.253.08:09:19.79#ibcon#read 3, iclass 4, count 2 2006.253.08:09:19.79#ibcon#about to read 4, iclass 4, count 2 2006.253.08:09:19.79#ibcon#read 4, iclass 4, count 2 2006.253.08:09:19.79#ibcon#about to read 5, iclass 4, count 2 2006.253.08:09:19.79#ibcon#read 5, iclass 4, count 2 2006.253.08:09:19.79#ibcon#about to read 6, iclass 4, count 2 2006.253.08:09:19.79#ibcon#read 6, iclass 4, count 2 2006.253.08:09:19.79#ibcon#end of sib2, iclass 4, count 2 2006.253.08:09:19.79#ibcon#*after write, iclass 4, count 2 2006.253.08:09:19.79#ibcon#*before return 0, iclass 4, count 2 2006.253.08:09:19.79#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.253.08:09:19.79#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.253.08:09:19.79#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.253.08:09:19.79#ibcon#ireg 7 cls_cnt 0 2006.253.08:09:19.79#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.253.08:09:19.91#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.253.08:09:19.91#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.253.08:09:19.91#ibcon#enter wrdev, iclass 4, count 0 2006.253.08:09:19.91#ibcon#first serial, iclass 4, count 0 2006.253.08:09:19.91#ibcon#enter sib2, iclass 4, count 0 2006.253.08:09:19.91#ibcon#flushed, iclass 4, count 0 2006.253.08:09:19.91#ibcon#about to write, iclass 4, count 0 2006.253.08:09:19.91#ibcon#wrote, iclass 4, count 0 2006.253.08:09:19.91#ibcon#about to read 3, iclass 4, count 0 2006.253.08:09:19.93#ibcon#read 3, iclass 4, count 0 2006.253.08:09:19.93#ibcon#about to read 4, iclass 4, count 0 2006.253.08:09:19.93#ibcon#read 4, iclass 4, count 0 2006.253.08:09:19.93#ibcon#about to read 5, iclass 4, count 0 2006.253.08:09:19.93#ibcon#read 5, iclass 4, count 0 2006.253.08:09:19.93#ibcon#about to read 6, iclass 4, count 0 2006.253.08:09:19.93#ibcon#read 6, iclass 4, count 0 2006.253.08:09:19.93#ibcon#end of sib2, iclass 4, count 0 2006.253.08:09:19.93#ibcon#*mode == 0, iclass 4, count 0 2006.253.08:09:19.93#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.253.08:09:19.93#ibcon#[25=USB\r\n] 2006.253.08:09:19.93#ibcon#*before write, iclass 4, count 0 2006.253.08:09:19.93#ibcon#enter sib2, iclass 4, count 0 2006.253.08:09:19.93#ibcon#flushed, iclass 4, count 0 2006.253.08:09:19.93#ibcon#about to write, iclass 4, count 0 2006.253.08:09:19.93#ibcon#wrote, iclass 4, count 0 2006.253.08:09:19.93#ibcon#about to read 3, iclass 4, count 0 2006.253.08:09:19.96#ibcon#read 3, iclass 4, count 0 2006.253.08:09:19.96#ibcon#about to read 4, iclass 4, count 0 2006.253.08:09:19.96#ibcon#read 4, iclass 4, count 0 2006.253.08:09:19.96#ibcon#about to read 5, iclass 4, count 0 2006.253.08:09:19.96#ibcon#read 5, iclass 4, count 0 2006.253.08:09:19.96#ibcon#about to read 6, iclass 4, count 0 2006.253.08:09:19.96#ibcon#read 6, iclass 4, count 0 2006.253.08:09:19.96#ibcon#end of sib2, iclass 4, count 0 2006.253.08:09:19.96#ibcon#*after write, iclass 4, count 0 2006.253.08:09:19.96#ibcon#*before return 0, iclass 4, count 0 2006.253.08:09:19.96#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.253.08:09:19.96#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.253.08:09:19.96#ibcon#about to clear, iclass 4 cls_cnt 0 2006.253.08:09:19.96#ibcon#cleared, iclass 4 cls_cnt 0 2006.253.08:09:19.96$vc4f8/valo=7,832.99 2006.253.08:09:19.96#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.253.08:09:19.96#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.253.08:09:19.96#ibcon#ireg 17 cls_cnt 0 2006.253.08:09:19.96#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.253.08:09:19.96#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.253.08:09:19.96#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.253.08:09:19.96#ibcon#enter wrdev, iclass 6, count 0 2006.253.08:09:19.96#ibcon#first serial, iclass 6, count 0 2006.253.08:09:19.96#ibcon#enter sib2, iclass 6, count 0 2006.253.08:09:19.96#ibcon#flushed, iclass 6, count 0 2006.253.08:09:19.96#ibcon#about to write, iclass 6, count 0 2006.253.08:09:19.96#ibcon#wrote, iclass 6, count 0 2006.253.08:09:19.96#ibcon#about to read 3, iclass 6, count 0 2006.253.08:09:19.98#ibcon#read 3, iclass 6, count 0 2006.253.08:09:19.98#ibcon#about to read 4, iclass 6, count 0 2006.253.08:09:19.98#ibcon#read 4, iclass 6, count 0 2006.253.08:09:19.98#ibcon#about to read 5, iclass 6, count 0 2006.253.08:09:19.98#ibcon#read 5, iclass 6, count 0 2006.253.08:09:19.98#ibcon#about to read 6, iclass 6, count 0 2006.253.08:09:19.98#ibcon#read 6, iclass 6, count 0 2006.253.08:09:19.98#ibcon#end of sib2, iclass 6, count 0 2006.253.08:09:19.98#ibcon#*mode == 0, iclass 6, count 0 2006.253.08:09:19.98#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.253.08:09:19.98#ibcon#[26=FRQ=07,832.99\r\n] 2006.253.08:09:19.98#ibcon#*before write, iclass 6, count 0 2006.253.08:09:19.98#ibcon#enter sib2, iclass 6, count 0 2006.253.08:09:19.98#ibcon#flushed, iclass 6, count 0 2006.253.08:09:19.98#ibcon#about to write, iclass 6, count 0 2006.253.08:09:19.98#ibcon#wrote, iclass 6, count 0 2006.253.08:09:19.98#ibcon#about to read 3, iclass 6, count 0 2006.253.08:09:20.02#ibcon#read 3, iclass 6, count 0 2006.253.08:09:20.02#ibcon#about to read 4, iclass 6, count 0 2006.253.08:09:20.02#ibcon#read 4, iclass 6, count 0 2006.253.08:09:20.02#ibcon#about to read 5, iclass 6, count 0 2006.253.08:09:20.02#ibcon#read 5, iclass 6, count 0 2006.253.08:09:20.02#ibcon#about to read 6, iclass 6, count 0 2006.253.08:09:20.02#ibcon#read 6, iclass 6, count 0 2006.253.08:09:20.02#ibcon#end of sib2, iclass 6, count 0 2006.253.08:09:20.02#ibcon#*after write, iclass 6, count 0 2006.253.08:09:20.02#ibcon#*before return 0, iclass 6, count 0 2006.253.08:09:20.02#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.253.08:09:20.02#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.253.08:09:20.02#ibcon#about to clear, iclass 6 cls_cnt 0 2006.253.08:09:20.02#ibcon#cleared, iclass 6 cls_cnt 0 2006.253.08:09:20.02$vc4f8/va=7,7 2006.253.08:09:20.02#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.253.08:09:20.02#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.253.08:09:20.02#ibcon#ireg 11 cls_cnt 2 2006.253.08:09:20.02#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.253.08:09:20.08#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.253.08:09:20.08#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.253.08:09:20.08#ibcon#enter wrdev, iclass 10, count 2 2006.253.08:09:20.08#ibcon#first serial, iclass 10, count 2 2006.253.08:09:20.08#ibcon#enter sib2, iclass 10, count 2 2006.253.08:09:20.08#ibcon#flushed, iclass 10, count 2 2006.253.08:09:20.08#ibcon#about to write, iclass 10, count 2 2006.253.08:09:20.08#ibcon#wrote, iclass 10, count 2 2006.253.08:09:20.08#ibcon#about to read 3, iclass 10, count 2 2006.253.08:09:20.10#ibcon#read 3, iclass 10, count 2 2006.253.08:09:20.10#ibcon#about to read 4, iclass 10, count 2 2006.253.08:09:20.10#ibcon#read 4, iclass 10, count 2 2006.253.08:09:20.10#ibcon#about to read 5, iclass 10, count 2 2006.253.08:09:20.10#ibcon#read 5, iclass 10, count 2 2006.253.08:09:20.10#ibcon#about to read 6, iclass 10, count 2 2006.253.08:09:20.10#ibcon#read 6, iclass 10, count 2 2006.253.08:09:20.10#ibcon#end of sib2, iclass 10, count 2 2006.253.08:09:20.10#ibcon#*mode == 0, iclass 10, count 2 2006.253.08:09:20.10#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.253.08:09:20.10#ibcon#[25=AT07-07\r\n] 2006.253.08:09:20.10#ibcon#*before write, iclass 10, count 2 2006.253.08:09:20.10#ibcon#enter sib2, iclass 10, count 2 2006.253.08:09:20.10#ibcon#flushed, iclass 10, count 2 2006.253.08:09:20.10#ibcon#about to write, iclass 10, count 2 2006.253.08:09:20.10#ibcon#wrote, iclass 10, count 2 2006.253.08:09:20.10#ibcon#about to read 3, iclass 10, count 2 2006.253.08:09:20.13#ibcon#read 3, iclass 10, count 2 2006.253.08:09:20.13#ibcon#about to read 4, iclass 10, count 2 2006.253.08:09:20.13#ibcon#read 4, iclass 10, count 2 2006.253.08:09:20.13#ibcon#about to read 5, iclass 10, count 2 2006.253.08:09:20.13#ibcon#read 5, iclass 10, count 2 2006.253.08:09:20.13#ibcon#about to read 6, iclass 10, count 2 2006.253.08:09:20.13#ibcon#read 6, iclass 10, count 2 2006.253.08:09:20.13#ibcon#end of sib2, iclass 10, count 2 2006.253.08:09:20.13#ibcon#*after write, iclass 10, count 2 2006.253.08:09:20.13#ibcon#*before return 0, iclass 10, count 2 2006.253.08:09:20.13#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.253.08:09:20.13#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.253.08:09:20.13#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.253.08:09:20.13#ibcon#ireg 7 cls_cnt 0 2006.253.08:09:20.13#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.253.08:09:20.25#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.253.08:09:20.25#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.253.08:09:20.25#ibcon#enter wrdev, iclass 10, count 0 2006.253.08:09:20.25#ibcon#first serial, iclass 10, count 0 2006.253.08:09:20.25#ibcon#enter sib2, iclass 10, count 0 2006.253.08:09:20.25#ibcon#flushed, iclass 10, count 0 2006.253.08:09:20.25#ibcon#about to write, iclass 10, count 0 2006.253.08:09:20.25#ibcon#wrote, iclass 10, count 0 2006.253.08:09:20.25#ibcon#about to read 3, iclass 10, count 0 2006.253.08:09:20.27#ibcon#read 3, iclass 10, count 0 2006.253.08:09:20.27#ibcon#about to read 4, iclass 10, count 0 2006.253.08:09:20.27#ibcon#read 4, iclass 10, count 0 2006.253.08:09:20.27#ibcon#about to read 5, iclass 10, count 0 2006.253.08:09:20.27#ibcon#read 5, iclass 10, count 0 2006.253.08:09:20.27#ibcon#about to read 6, iclass 10, count 0 2006.253.08:09:20.27#ibcon#read 6, iclass 10, count 0 2006.253.08:09:20.27#ibcon#end of sib2, iclass 10, count 0 2006.253.08:09:20.27#ibcon#*mode == 0, iclass 10, count 0 2006.253.08:09:20.27#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.253.08:09:20.27#ibcon#[25=USB\r\n] 2006.253.08:09:20.27#ibcon#*before write, iclass 10, count 0 2006.253.08:09:20.27#ibcon#enter sib2, iclass 10, count 0 2006.253.08:09:20.27#ibcon#flushed, iclass 10, count 0 2006.253.08:09:20.27#ibcon#about to write, iclass 10, count 0 2006.253.08:09:20.27#ibcon#wrote, iclass 10, count 0 2006.253.08:09:20.27#ibcon#about to read 3, iclass 10, count 0 2006.253.08:09:20.30#ibcon#read 3, iclass 10, count 0 2006.253.08:09:20.30#ibcon#about to read 4, iclass 10, count 0 2006.253.08:09:20.30#ibcon#read 4, iclass 10, count 0 2006.253.08:09:20.30#ibcon#about to read 5, iclass 10, count 0 2006.253.08:09:20.30#ibcon#read 5, iclass 10, count 0 2006.253.08:09:20.30#ibcon#about to read 6, iclass 10, count 0 2006.253.08:09:20.30#ibcon#read 6, iclass 10, count 0 2006.253.08:09:20.30#ibcon#end of sib2, iclass 10, count 0 2006.253.08:09:20.30#ibcon#*after write, iclass 10, count 0 2006.253.08:09:20.30#ibcon#*before return 0, iclass 10, count 0 2006.253.08:09:20.30#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.253.08:09:20.30#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.253.08:09:20.30#ibcon#about to clear, iclass 10 cls_cnt 0 2006.253.08:09:20.30#ibcon#cleared, iclass 10 cls_cnt 0 2006.253.08:09:20.30$vc4f8/valo=8,852.99 2006.253.08:09:20.30#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.253.08:09:20.30#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.253.08:09:20.30#ibcon#ireg 17 cls_cnt 0 2006.253.08:09:20.30#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.253.08:09:20.30#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.253.08:09:20.30#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.253.08:09:20.30#ibcon#enter wrdev, iclass 12, count 0 2006.253.08:09:20.30#ibcon#first serial, iclass 12, count 0 2006.253.08:09:20.30#ibcon#enter sib2, iclass 12, count 0 2006.253.08:09:20.30#ibcon#flushed, iclass 12, count 0 2006.253.08:09:20.30#ibcon#about to write, iclass 12, count 0 2006.253.08:09:20.30#ibcon#wrote, iclass 12, count 0 2006.253.08:09:20.30#ibcon#about to read 3, iclass 12, count 0 2006.253.08:09:20.32#ibcon#read 3, iclass 12, count 0 2006.253.08:09:20.32#ibcon#about to read 4, iclass 12, count 0 2006.253.08:09:20.32#ibcon#read 4, iclass 12, count 0 2006.253.08:09:20.32#ibcon#about to read 5, iclass 12, count 0 2006.253.08:09:20.32#ibcon#read 5, iclass 12, count 0 2006.253.08:09:20.32#ibcon#about to read 6, iclass 12, count 0 2006.253.08:09:20.32#ibcon#read 6, iclass 12, count 0 2006.253.08:09:20.32#ibcon#end of sib2, iclass 12, count 0 2006.253.08:09:20.32#ibcon#*mode == 0, iclass 12, count 0 2006.253.08:09:20.32#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.253.08:09:20.32#ibcon#[26=FRQ=08,852.99\r\n] 2006.253.08:09:20.32#ibcon#*before write, iclass 12, count 0 2006.253.08:09:20.32#ibcon#enter sib2, iclass 12, count 0 2006.253.08:09:20.32#ibcon#flushed, iclass 12, count 0 2006.253.08:09:20.32#ibcon#about to write, iclass 12, count 0 2006.253.08:09:20.32#ibcon#wrote, iclass 12, count 0 2006.253.08:09:20.32#ibcon#about to read 3, iclass 12, count 0 2006.253.08:09:20.36#ibcon#read 3, iclass 12, count 0 2006.253.08:09:20.36#ibcon#about to read 4, iclass 12, count 0 2006.253.08:09:20.36#ibcon#read 4, iclass 12, count 0 2006.253.08:09:20.36#ibcon#about to read 5, iclass 12, count 0 2006.253.08:09:20.36#ibcon#read 5, iclass 12, count 0 2006.253.08:09:20.36#ibcon#about to read 6, iclass 12, count 0 2006.253.08:09:20.36#ibcon#read 6, iclass 12, count 0 2006.253.08:09:20.36#ibcon#end of sib2, iclass 12, count 0 2006.253.08:09:20.36#ibcon#*after write, iclass 12, count 0 2006.253.08:09:20.36#ibcon#*before return 0, iclass 12, count 0 2006.253.08:09:20.36#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.253.08:09:20.36#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.253.08:09:20.36#ibcon#about to clear, iclass 12 cls_cnt 0 2006.253.08:09:20.36#ibcon#cleared, iclass 12 cls_cnt 0 2006.253.08:09:20.36$vc4f8/va=8,7 2006.253.08:09:20.36#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.253.08:09:20.36#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.253.08:09:20.36#ibcon#ireg 11 cls_cnt 2 2006.253.08:09:20.36#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.253.08:09:20.42#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.253.08:09:20.42#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.253.08:09:20.42#ibcon#enter wrdev, iclass 14, count 2 2006.253.08:09:20.42#ibcon#first serial, iclass 14, count 2 2006.253.08:09:20.42#ibcon#enter sib2, iclass 14, count 2 2006.253.08:09:20.42#ibcon#flushed, iclass 14, count 2 2006.253.08:09:20.42#ibcon#about to write, iclass 14, count 2 2006.253.08:09:20.42#ibcon#wrote, iclass 14, count 2 2006.253.08:09:20.42#ibcon#about to read 3, iclass 14, count 2 2006.253.08:09:20.44#ibcon#read 3, iclass 14, count 2 2006.253.08:09:20.44#ibcon#about to read 4, iclass 14, count 2 2006.253.08:09:20.44#ibcon#read 4, iclass 14, count 2 2006.253.08:09:20.44#ibcon#about to read 5, iclass 14, count 2 2006.253.08:09:20.44#ibcon#read 5, iclass 14, count 2 2006.253.08:09:20.44#ibcon#about to read 6, iclass 14, count 2 2006.253.08:09:20.44#ibcon#read 6, iclass 14, count 2 2006.253.08:09:20.44#ibcon#end of sib2, iclass 14, count 2 2006.253.08:09:20.44#ibcon#*mode == 0, iclass 14, count 2 2006.253.08:09:20.44#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.253.08:09:20.44#ibcon#[25=AT08-07\r\n] 2006.253.08:09:20.44#ibcon#*before write, iclass 14, count 2 2006.253.08:09:20.44#ibcon#enter sib2, iclass 14, count 2 2006.253.08:09:20.44#ibcon#flushed, iclass 14, count 2 2006.253.08:09:20.44#ibcon#about to write, iclass 14, count 2 2006.253.08:09:20.44#ibcon#wrote, iclass 14, count 2 2006.253.08:09:20.44#ibcon#about to read 3, iclass 14, count 2 2006.253.08:09:20.47#ibcon#read 3, iclass 14, count 2 2006.253.08:09:20.47#ibcon#about to read 4, iclass 14, count 2 2006.253.08:09:20.47#ibcon#read 4, iclass 14, count 2 2006.253.08:09:20.47#ibcon#about to read 5, iclass 14, count 2 2006.253.08:09:20.47#ibcon#read 5, iclass 14, count 2 2006.253.08:09:20.47#ibcon#about to read 6, iclass 14, count 2 2006.253.08:09:20.47#ibcon#read 6, iclass 14, count 2 2006.253.08:09:20.47#ibcon#end of sib2, iclass 14, count 2 2006.253.08:09:20.47#ibcon#*after write, iclass 14, count 2 2006.253.08:09:20.47#ibcon#*before return 0, iclass 14, count 2 2006.253.08:09:20.47#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.253.08:09:20.47#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.253.08:09:20.47#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.253.08:09:20.47#ibcon#ireg 7 cls_cnt 0 2006.253.08:09:20.47#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.253.08:09:20.59#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.253.08:09:20.59#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.253.08:09:20.59#ibcon#enter wrdev, iclass 14, count 0 2006.253.08:09:20.59#ibcon#first serial, iclass 14, count 0 2006.253.08:09:20.59#ibcon#enter sib2, iclass 14, count 0 2006.253.08:09:20.59#ibcon#flushed, iclass 14, count 0 2006.253.08:09:20.59#ibcon#about to write, iclass 14, count 0 2006.253.08:09:20.59#ibcon#wrote, iclass 14, count 0 2006.253.08:09:20.59#ibcon#about to read 3, iclass 14, count 0 2006.253.08:09:20.61#ibcon#read 3, iclass 14, count 0 2006.253.08:09:20.61#ibcon#about to read 4, iclass 14, count 0 2006.253.08:09:20.61#ibcon#read 4, iclass 14, count 0 2006.253.08:09:20.61#ibcon#about to read 5, iclass 14, count 0 2006.253.08:09:20.61#ibcon#read 5, iclass 14, count 0 2006.253.08:09:20.61#ibcon#about to read 6, iclass 14, count 0 2006.253.08:09:20.61#ibcon#read 6, iclass 14, count 0 2006.253.08:09:20.61#ibcon#end of sib2, iclass 14, count 0 2006.253.08:09:20.61#ibcon#*mode == 0, iclass 14, count 0 2006.253.08:09:20.61#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.253.08:09:20.61#ibcon#[25=USB\r\n] 2006.253.08:09:20.61#ibcon#*before write, iclass 14, count 0 2006.253.08:09:20.61#ibcon#enter sib2, iclass 14, count 0 2006.253.08:09:20.61#ibcon#flushed, iclass 14, count 0 2006.253.08:09:20.61#ibcon#about to write, iclass 14, count 0 2006.253.08:09:20.61#ibcon#wrote, iclass 14, count 0 2006.253.08:09:20.61#ibcon#about to read 3, iclass 14, count 0 2006.253.08:09:20.64#ibcon#read 3, iclass 14, count 0 2006.253.08:09:20.64#ibcon#about to read 4, iclass 14, count 0 2006.253.08:09:20.64#ibcon#read 4, iclass 14, count 0 2006.253.08:09:20.64#ibcon#about to read 5, iclass 14, count 0 2006.253.08:09:20.64#ibcon#read 5, iclass 14, count 0 2006.253.08:09:20.64#ibcon#about to read 6, iclass 14, count 0 2006.253.08:09:20.64#ibcon#read 6, iclass 14, count 0 2006.253.08:09:20.64#ibcon#end of sib2, iclass 14, count 0 2006.253.08:09:20.64#ibcon#*after write, iclass 14, count 0 2006.253.08:09:20.64#ibcon#*before return 0, iclass 14, count 0 2006.253.08:09:20.64#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.253.08:09:20.64#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.253.08:09:20.64#ibcon#about to clear, iclass 14 cls_cnt 0 2006.253.08:09:20.64#ibcon#cleared, iclass 14 cls_cnt 0 2006.253.08:09:20.64$vc4f8/vblo=1,632.99 2006.253.08:09:20.64#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.253.08:09:20.64#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.253.08:09:20.64#ibcon#ireg 17 cls_cnt 0 2006.253.08:09:20.64#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.253.08:09:20.64#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.253.08:09:20.64#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.253.08:09:20.64#ibcon#enter wrdev, iclass 16, count 0 2006.253.08:09:20.64#ibcon#first serial, iclass 16, count 0 2006.253.08:09:20.64#ibcon#enter sib2, iclass 16, count 0 2006.253.08:09:20.64#ibcon#flushed, iclass 16, count 0 2006.253.08:09:20.64#ibcon#about to write, iclass 16, count 0 2006.253.08:09:20.64#ibcon#wrote, iclass 16, count 0 2006.253.08:09:20.64#ibcon#about to read 3, iclass 16, count 0 2006.253.08:09:20.66#ibcon#read 3, iclass 16, count 0 2006.253.08:09:20.66#ibcon#about to read 4, iclass 16, count 0 2006.253.08:09:20.66#ibcon#read 4, iclass 16, count 0 2006.253.08:09:20.66#ibcon#about to read 5, iclass 16, count 0 2006.253.08:09:20.66#ibcon#read 5, iclass 16, count 0 2006.253.08:09:20.66#ibcon#about to read 6, iclass 16, count 0 2006.253.08:09:20.66#ibcon#read 6, iclass 16, count 0 2006.253.08:09:20.66#ibcon#end of sib2, iclass 16, count 0 2006.253.08:09:20.66#ibcon#*mode == 0, iclass 16, count 0 2006.253.08:09:20.66#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.253.08:09:20.66#ibcon#[28=FRQ=01,632.99\r\n] 2006.253.08:09:20.66#ibcon#*before write, iclass 16, count 0 2006.253.08:09:20.66#ibcon#enter sib2, iclass 16, count 0 2006.253.08:09:20.66#ibcon#flushed, iclass 16, count 0 2006.253.08:09:20.66#ibcon#about to write, iclass 16, count 0 2006.253.08:09:20.66#ibcon#wrote, iclass 16, count 0 2006.253.08:09:20.66#ibcon#about to read 3, iclass 16, count 0 2006.253.08:09:20.71#ibcon#read 3, iclass 16, count 0 2006.253.08:09:20.71#ibcon#about to read 4, iclass 16, count 0 2006.253.08:09:20.71#ibcon#read 4, iclass 16, count 0 2006.253.08:09:20.71#ibcon#about to read 5, iclass 16, count 0 2006.253.08:09:20.71#ibcon#read 5, iclass 16, count 0 2006.253.08:09:20.71#ibcon#about to read 6, iclass 16, count 0 2006.253.08:09:20.71#ibcon#read 6, iclass 16, count 0 2006.253.08:09:20.71#ibcon#end of sib2, iclass 16, count 0 2006.253.08:09:20.71#ibcon#*after write, iclass 16, count 0 2006.253.08:09:20.71#ibcon#*before return 0, iclass 16, count 0 2006.253.08:09:20.71#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.253.08:09:20.71#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.253.08:09:20.71#ibcon#about to clear, iclass 16 cls_cnt 0 2006.253.08:09:20.71#ibcon#cleared, iclass 16 cls_cnt 0 2006.253.08:09:20.71$vc4f8/vb=1,4 2006.253.08:09:20.71#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.253.08:09:20.71#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.253.08:09:20.71#ibcon#ireg 11 cls_cnt 2 2006.253.08:09:20.71#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.253.08:09:20.71#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.253.08:09:20.71#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.253.08:09:20.71#ibcon#enter wrdev, iclass 18, count 2 2006.253.08:09:20.71#ibcon#first serial, iclass 18, count 2 2006.253.08:09:20.71#ibcon#enter sib2, iclass 18, count 2 2006.253.08:09:20.71#ibcon#flushed, iclass 18, count 2 2006.253.08:09:20.71#ibcon#about to write, iclass 18, count 2 2006.253.08:09:20.71#ibcon#wrote, iclass 18, count 2 2006.253.08:09:20.71#ibcon#about to read 3, iclass 18, count 2 2006.253.08:09:20.73#ibcon#read 3, iclass 18, count 2 2006.253.08:09:20.73#ibcon#about to read 4, iclass 18, count 2 2006.253.08:09:20.73#ibcon#read 4, iclass 18, count 2 2006.253.08:09:20.73#ibcon#about to read 5, iclass 18, count 2 2006.253.08:09:20.73#ibcon#read 5, iclass 18, count 2 2006.253.08:09:20.73#ibcon#about to read 6, iclass 18, count 2 2006.253.08:09:20.73#ibcon#read 6, iclass 18, count 2 2006.253.08:09:20.73#ibcon#end of sib2, iclass 18, count 2 2006.253.08:09:20.73#ibcon#*mode == 0, iclass 18, count 2 2006.253.08:09:20.73#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.253.08:09:20.73#ibcon#[27=AT01-04\r\n] 2006.253.08:09:20.73#ibcon#*before write, iclass 18, count 2 2006.253.08:09:20.73#ibcon#enter sib2, iclass 18, count 2 2006.253.08:09:20.73#ibcon#flushed, iclass 18, count 2 2006.253.08:09:20.73#ibcon#about to write, iclass 18, count 2 2006.253.08:09:20.73#ibcon#wrote, iclass 18, count 2 2006.253.08:09:20.73#ibcon#about to read 3, iclass 18, count 2 2006.253.08:09:20.76#ibcon#read 3, iclass 18, count 2 2006.253.08:09:20.76#ibcon#about to read 4, iclass 18, count 2 2006.253.08:09:20.76#ibcon#read 4, iclass 18, count 2 2006.253.08:09:20.76#ibcon#about to read 5, iclass 18, count 2 2006.253.08:09:20.76#ibcon#read 5, iclass 18, count 2 2006.253.08:09:20.76#ibcon#about to read 6, iclass 18, count 2 2006.253.08:09:20.76#ibcon#read 6, iclass 18, count 2 2006.253.08:09:20.76#ibcon#end of sib2, iclass 18, count 2 2006.253.08:09:20.76#ibcon#*after write, iclass 18, count 2 2006.253.08:09:20.76#ibcon#*before return 0, iclass 18, count 2 2006.253.08:09:20.76#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.253.08:09:20.76#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.253.08:09:20.76#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.253.08:09:20.76#ibcon#ireg 7 cls_cnt 0 2006.253.08:09:20.76#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.253.08:09:20.88#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.253.08:09:20.88#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.253.08:09:20.88#ibcon#enter wrdev, iclass 18, count 0 2006.253.08:09:20.88#ibcon#first serial, iclass 18, count 0 2006.253.08:09:20.88#ibcon#enter sib2, iclass 18, count 0 2006.253.08:09:20.88#ibcon#flushed, iclass 18, count 0 2006.253.08:09:20.88#ibcon#about to write, iclass 18, count 0 2006.253.08:09:20.88#ibcon#wrote, iclass 18, count 0 2006.253.08:09:20.88#ibcon#about to read 3, iclass 18, count 0 2006.253.08:09:20.90#ibcon#read 3, iclass 18, count 0 2006.253.08:09:20.90#ibcon#about to read 4, iclass 18, count 0 2006.253.08:09:20.90#ibcon#read 4, iclass 18, count 0 2006.253.08:09:20.90#ibcon#about to read 5, iclass 18, count 0 2006.253.08:09:20.90#ibcon#read 5, iclass 18, count 0 2006.253.08:09:20.90#ibcon#about to read 6, iclass 18, count 0 2006.253.08:09:20.90#ibcon#read 6, iclass 18, count 0 2006.253.08:09:20.90#ibcon#end of sib2, iclass 18, count 0 2006.253.08:09:20.90#ibcon#*mode == 0, iclass 18, count 0 2006.253.08:09:20.90#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.253.08:09:20.90#ibcon#[27=USB\r\n] 2006.253.08:09:20.90#ibcon#*before write, iclass 18, count 0 2006.253.08:09:20.90#ibcon#enter sib2, iclass 18, count 0 2006.253.08:09:20.90#ibcon#flushed, iclass 18, count 0 2006.253.08:09:20.90#ibcon#about to write, iclass 18, count 0 2006.253.08:09:20.90#ibcon#wrote, iclass 18, count 0 2006.253.08:09:20.90#ibcon#about to read 3, iclass 18, count 0 2006.253.08:09:20.93#ibcon#read 3, iclass 18, count 0 2006.253.08:09:20.93#ibcon#about to read 4, iclass 18, count 0 2006.253.08:09:20.93#ibcon#read 4, iclass 18, count 0 2006.253.08:09:20.93#ibcon#about to read 5, iclass 18, count 0 2006.253.08:09:20.93#ibcon#read 5, iclass 18, count 0 2006.253.08:09:20.93#ibcon#about to read 6, iclass 18, count 0 2006.253.08:09:20.93#ibcon#read 6, iclass 18, count 0 2006.253.08:09:20.93#ibcon#end of sib2, iclass 18, count 0 2006.253.08:09:20.93#ibcon#*after write, iclass 18, count 0 2006.253.08:09:20.93#ibcon#*before return 0, iclass 18, count 0 2006.253.08:09:20.93#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.253.08:09:20.93#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.253.08:09:20.93#ibcon#about to clear, iclass 18 cls_cnt 0 2006.253.08:09:20.93#ibcon#cleared, iclass 18 cls_cnt 0 2006.253.08:09:20.93$vc4f8/vblo=2,640.99 2006.253.08:09:20.93#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.253.08:09:20.93#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.253.08:09:20.93#ibcon#ireg 17 cls_cnt 0 2006.253.08:09:20.93#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.253.08:09:20.93#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.253.08:09:20.93#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.253.08:09:20.93#ibcon#enter wrdev, iclass 20, count 0 2006.253.08:09:20.93#ibcon#first serial, iclass 20, count 0 2006.253.08:09:20.93#ibcon#enter sib2, iclass 20, count 0 2006.253.08:09:20.93#ibcon#flushed, iclass 20, count 0 2006.253.08:09:20.93#ibcon#about to write, iclass 20, count 0 2006.253.08:09:20.93#ibcon#wrote, iclass 20, count 0 2006.253.08:09:20.93#ibcon#about to read 3, iclass 20, count 0 2006.253.08:09:20.95#ibcon#read 3, iclass 20, count 0 2006.253.08:09:20.95#ibcon#about to read 4, iclass 20, count 0 2006.253.08:09:20.95#ibcon#read 4, iclass 20, count 0 2006.253.08:09:20.95#ibcon#about to read 5, iclass 20, count 0 2006.253.08:09:20.95#ibcon#read 5, iclass 20, count 0 2006.253.08:09:20.95#ibcon#about to read 6, iclass 20, count 0 2006.253.08:09:20.95#ibcon#read 6, iclass 20, count 0 2006.253.08:09:20.95#ibcon#end of sib2, iclass 20, count 0 2006.253.08:09:20.95#ibcon#*mode == 0, iclass 20, count 0 2006.253.08:09:20.95#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.253.08:09:20.95#ibcon#[28=FRQ=02,640.99\r\n] 2006.253.08:09:20.95#ibcon#*before write, iclass 20, count 0 2006.253.08:09:20.95#ibcon#enter sib2, iclass 20, count 0 2006.253.08:09:20.95#ibcon#flushed, iclass 20, count 0 2006.253.08:09:20.95#ibcon#about to write, iclass 20, count 0 2006.253.08:09:20.95#ibcon#wrote, iclass 20, count 0 2006.253.08:09:20.95#ibcon#about to read 3, iclass 20, count 0 2006.253.08:09:20.99#ibcon#read 3, iclass 20, count 0 2006.253.08:09:20.99#ibcon#about to read 4, iclass 20, count 0 2006.253.08:09:20.99#ibcon#read 4, iclass 20, count 0 2006.253.08:09:20.99#ibcon#about to read 5, iclass 20, count 0 2006.253.08:09:20.99#ibcon#read 5, iclass 20, count 0 2006.253.08:09:20.99#ibcon#about to read 6, iclass 20, count 0 2006.253.08:09:20.99#ibcon#read 6, iclass 20, count 0 2006.253.08:09:20.99#ibcon#end of sib2, iclass 20, count 0 2006.253.08:09:20.99#ibcon#*after write, iclass 20, count 0 2006.253.08:09:20.99#ibcon#*before return 0, iclass 20, count 0 2006.253.08:09:20.99#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.253.08:09:20.99#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.253.08:09:20.99#ibcon#about to clear, iclass 20 cls_cnt 0 2006.253.08:09:20.99#ibcon#cleared, iclass 20 cls_cnt 0 2006.253.08:09:20.99$vc4f8/vb=2,5 2006.253.08:09:20.99#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.253.08:09:20.99#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.253.08:09:20.99#ibcon#ireg 11 cls_cnt 2 2006.253.08:09:20.99#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.253.08:09:21.05#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.253.08:09:21.05#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.253.08:09:21.05#ibcon#enter wrdev, iclass 22, count 2 2006.253.08:09:21.05#ibcon#first serial, iclass 22, count 2 2006.253.08:09:21.05#ibcon#enter sib2, iclass 22, count 2 2006.253.08:09:21.05#ibcon#flushed, iclass 22, count 2 2006.253.08:09:21.05#ibcon#about to write, iclass 22, count 2 2006.253.08:09:21.05#ibcon#wrote, iclass 22, count 2 2006.253.08:09:21.05#ibcon#about to read 3, iclass 22, count 2 2006.253.08:09:21.07#ibcon#read 3, iclass 22, count 2 2006.253.08:09:21.07#ibcon#about to read 4, iclass 22, count 2 2006.253.08:09:21.07#ibcon#read 4, iclass 22, count 2 2006.253.08:09:21.07#ibcon#about to read 5, iclass 22, count 2 2006.253.08:09:21.07#ibcon#read 5, iclass 22, count 2 2006.253.08:09:21.07#ibcon#about to read 6, iclass 22, count 2 2006.253.08:09:21.07#ibcon#read 6, iclass 22, count 2 2006.253.08:09:21.07#ibcon#end of sib2, iclass 22, count 2 2006.253.08:09:21.07#ibcon#*mode == 0, iclass 22, count 2 2006.253.08:09:21.07#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.253.08:09:21.07#ibcon#[27=AT02-05\r\n] 2006.253.08:09:21.07#ibcon#*before write, iclass 22, count 2 2006.253.08:09:21.07#ibcon#enter sib2, iclass 22, count 2 2006.253.08:09:21.07#ibcon#flushed, iclass 22, count 2 2006.253.08:09:21.07#ibcon#about to write, iclass 22, count 2 2006.253.08:09:21.07#ibcon#wrote, iclass 22, count 2 2006.253.08:09:21.07#ibcon#about to read 3, iclass 22, count 2 2006.253.08:09:21.10#ibcon#read 3, iclass 22, count 2 2006.253.08:09:21.10#ibcon#about to read 4, iclass 22, count 2 2006.253.08:09:21.10#ibcon#read 4, iclass 22, count 2 2006.253.08:09:21.10#ibcon#about to read 5, iclass 22, count 2 2006.253.08:09:21.10#ibcon#read 5, iclass 22, count 2 2006.253.08:09:21.10#ibcon#about to read 6, iclass 22, count 2 2006.253.08:09:21.10#ibcon#read 6, iclass 22, count 2 2006.253.08:09:21.10#ibcon#end of sib2, iclass 22, count 2 2006.253.08:09:21.10#ibcon#*after write, iclass 22, count 2 2006.253.08:09:21.10#ibcon#*before return 0, iclass 22, count 2 2006.253.08:09:21.10#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.253.08:09:21.10#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.253.08:09:21.10#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.253.08:09:21.10#ibcon#ireg 7 cls_cnt 0 2006.253.08:09:21.10#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.253.08:09:21.22#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.253.08:09:21.22#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.253.08:09:21.22#ibcon#enter wrdev, iclass 22, count 0 2006.253.08:09:21.22#ibcon#first serial, iclass 22, count 0 2006.253.08:09:21.22#ibcon#enter sib2, iclass 22, count 0 2006.253.08:09:21.22#ibcon#flushed, iclass 22, count 0 2006.253.08:09:21.22#ibcon#about to write, iclass 22, count 0 2006.253.08:09:21.22#ibcon#wrote, iclass 22, count 0 2006.253.08:09:21.22#ibcon#about to read 3, iclass 22, count 0 2006.253.08:09:21.25#ibcon#read 3, iclass 22, count 0 2006.253.08:09:21.25#ibcon#about to read 4, iclass 22, count 0 2006.253.08:09:21.25#ibcon#read 4, iclass 22, count 0 2006.253.08:09:21.25#ibcon#about to read 5, iclass 22, count 0 2006.253.08:09:21.25#ibcon#read 5, iclass 22, count 0 2006.253.08:09:21.25#ibcon#about to read 6, iclass 22, count 0 2006.253.08:09:21.25#ibcon#read 6, iclass 22, count 0 2006.253.08:09:21.25#ibcon#end of sib2, iclass 22, count 0 2006.253.08:09:21.25#ibcon#*mode == 0, iclass 22, count 0 2006.253.08:09:21.25#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.253.08:09:21.25#ibcon#[27=USB\r\n] 2006.253.08:09:21.25#ibcon#*before write, iclass 22, count 0 2006.253.08:09:21.25#ibcon#enter sib2, iclass 22, count 0 2006.253.08:09:21.25#ibcon#flushed, iclass 22, count 0 2006.253.08:09:21.25#ibcon#about to write, iclass 22, count 0 2006.253.08:09:21.25#ibcon#wrote, iclass 22, count 0 2006.253.08:09:21.25#ibcon#about to read 3, iclass 22, count 0 2006.253.08:09:21.28#ibcon#read 3, iclass 22, count 0 2006.253.08:09:21.28#ibcon#about to read 4, iclass 22, count 0 2006.253.08:09:21.28#ibcon#read 4, iclass 22, count 0 2006.253.08:09:21.28#ibcon#about to read 5, iclass 22, count 0 2006.253.08:09:21.28#ibcon#read 5, iclass 22, count 0 2006.253.08:09:21.28#ibcon#about to read 6, iclass 22, count 0 2006.253.08:09:21.28#ibcon#read 6, iclass 22, count 0 2006.253.08:09:21.28#ibcon#end of sib2, iclass 22, count 0 2006.253.08:09:21.28#ibcon#*after write, iclass 22, count 0 2006.253.08:09:21.28#ibcon#*before return 0, iclass 22, count 0 2006.253.08:09:21.28#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.253.08:09:21.28#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.253.08:09:21.28#ibcon#about to clear, iclass 22 cls_cnt 0 2006.253.08:09:21.28#ibcon#cleared, iclass 22 cls_cnt 0 2006.253.08:09:21.28$vc4f8/vblo=3,656.99 2006.253.08:09:21.28#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.253.08:09:21.28#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.253.08:09:21.28#ibcon#ireg 17 cls_cnt 0 2006.253.08:09:21.28#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.253.08:09:21.28#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.253.08:09:21.28#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.253.08:09:21.28#ibcon#enter wrdev, iclass 24, count 0 2006.253.08:09:21.28#ibcon#first serial, iclass 24, count 0 2006.253.08:09:21.28#ibcon#enter sib2, iclass 24, count 0 2006.253.08:09:21.28#ibcon#flushed, iclass 24, count 0 2006.253.08:09:21.28#ibcon#about to write, iclass 24, count 0 2006.253.08:09:21.28#ibcon#wrote, iclass 24, count 0 2006.253.08:09:21.28#ibcon#about to read 3, iclass 24, count 0 2006.253.08:09:21.30#ibcon#read 3, iclass 24, count 0 2006.253.08:09:21.30#ibcon#about to read 4, iclass 24, count 0 2006.253.08:09:21.30#ibcon#read 4, iclass 24, count 0 2006.253.08:09:21.30#ibcon#about to read 5, iclass 24, count 0 2006.253.08:09:21.30#ibcon#read 5, iclass 24, count 0 2006.253.08:09:21.30#ibcon#about to read 6, iclass 24, count 0 2006.253.08:09:21.30#ibcon#read 6, iclass 24, count 0 2006.253.08:09:21.30#ibcon#end of sib2, iclass 24, count 0 2006.253.08:09:21.30#ibcon#*mode == 0, iclass 24, count 0 2006.253.08:09:21.30#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.253.08:09:21.30#ibcon#[28=FRQ=03,656.99\r\n] 2006.253.08:09:21.30#ibcon#*before write, iclass 24, count 0 2006.253.08:09:21.30#ibcon#enter sib2, iclass 24, count 0 2006.253.08:09:21.30#ibcon#flushed, iclass 24, count 0 2006.253.08:09:21.30#ibcon#about to write, iclass 24, count 0 2006.253.08:09:21.30#ibcon#wrote, iclass 24, count 0 2006.253.08:09:21.30#ibcon#about to read 3, iclass 24, count 0 2006.253.08:09:21.34#ibcon#read 3, iclass 24, count 0 2006.253.08:09:21.34#ibcon#about to read 4, iclass 24, count 0 2006.253.08:09:21.34#ibcon#read 4, iclass 24, count 0 2006.253.08:09:21.34#ibcon#about to read 5, iclass 24, count 0 2006.253.08:09:21.34#ibcon#read 5, iclass 24, count 0 2006.253.08:09:21.34#ibcon#about to read 6, iclass 24, count 0 2006.253.08:09:21.34#ibcon#read 6, iclass 24, count 0 2006.253.08:09:21.34#ibcon#end of sib2, iclass 24, count 0 2006.253.08:09:21.34#ibcon#*after write, iclass 24, count 0 2006.253.08:09:21.34#ibcon#*before return 0, iclass 24, count 0 2006.253.08:09:21.34#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.253.08:09:21.34#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.253.08:09:21.34#ibcon#about to clear, iclass 24 cls_cnt 0 2006.253.08:09:21.34#ibcon#cleared, iclass 24 cls_cnt 0 2006.253.08:09:21.34$vc4f8/vb=3,4 2006.253.08:09:21.34#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.253.08:09:21.34#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.253.08:09:21.34#ibcon#ireg 11 cls_cnt 2 2006.253.08:09:21.34#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.253.08:09:21.40#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.253.08:09:21.40#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.253.08:09:21.40#ibcon#enter wrdev, iclass 26, count 2 2006.253.08:09:21.40#ibcon#first serial, iclass 26, count 2 2006.253.08:09:21.40#ibcon#enter sib2, iclass 26, count 2 2006.253.08:09:21.40#ibcon#flushed, iclass 26, count 2 2006.253.08:09:21.40#ibcon#about to write, iclass 26, count 2 2006.253.08:09:21.40#ibcon#wrote, iclass 26, count 2 2006.253.08:09:21.40#ibcon#about to read 3, iclass 26, count 2 2006.253.08:09:21.42#ibcon#read 3, iclass 26, count 2 2006.253.08:09:21.42#ibcon#about to read 4, iclass 26, count 2 2006.253.08:09:21.42#ibcon#read 4, iclass 26, count 2 2006.253.08:09:21.42#ibcon#about to read 5, iclass 26, count 2 2006.253.08:09:21.42#ibcon#read 5, iclass 26, count 2 2006.253.08:09:21.42#ibcon#about to read 6, iclass 26, count 2 2006.253.08:09:21.42#ibcon#read 6, iclass 26, count 2 2006.253.08:09:21.42#ibcon#end of sib2, iclass 26, count 2 2006.253.08:09:21.42#ibcon#*mode == 0, iclass 26, count 2 2006.253.08:09:21.42#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.253.08:09:21.42#ibcon#[27=AT03-04\r\n] 2006.253.08:09:21.42#ibcon#*before write, iclass 26, count 2 2006.253.08:09:21.42#ibcon#enter sib2, iclass 26, count 2 2006.253.08:09:21.42#ibcon#flushed, iclass 26, count 2 2006.253.08:09:21.42#ibcon#about to write, iclass 26, count 2 2006.253.08:09:21.42#ibcon#wrote, iclass 26, count 2 2006.253.08:09:21.42#ibcon#about to read 3, iclass 26, count 2 2006.253.08:09:21.45#ibcon#read 3, iclass 26, count 2 2006.253.08:09:21.45#ibcon#about to read 4, iclass 26, count 2 2006.253.08:09:21.45#ibcon#read 4, iclass 26, count 2 2006.253.08:09:21.45#ibcon#about to read 5, iclass 26, count 2 2006.253.08:09:21.45#ibcon#read 5, iclass 26, count 2 2006.253.08:09:21.45#ibcon#about to read 6, iclass 26, count 2 2006.253.08:09:21.45#ibcon#read 6, iclass 26, count 2 2006.253.08:09:21.45#ibcon#end of sib2, iclass 26, count 2 2006.253.08:09:21.45#ibcon#*after write, iclass 26, count 2 2006.253.08:09:21.45#ibcon#*before return 0, iclass 26, count 2 2006.253.08:09:21.45#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.253.08:09:21.45#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.253.08:09:21.45#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.253.08:09:21.45#ibcon#ireg 7 cls_cnt 0 2006.253.08:09:21.45#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.253.08:09:21.57#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.253.08:09:21.57#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.253.08:09:21.57#ibcon#enter wrdev, iclass 26, count 0 2006.253.08:09:21.57#ibcon#first serial, iclass 26, count 0 2006.253.08:09:21.57#ibcon#enter sib2, iclass 26, count 0 2006.253.08:09:21.57#ibcon#flushed, iclass 26, count 0 2006.253.08:09:21.57#ibcon#about to write, iclass 26, count 0 2006.253.08:09:21.57#ibcon#wrote, iclass 26, count 0 2006.253.08:09:21.57#ibcon#about to read 3, iclass 26, count 0 2006.253.08:09:21.59#ibcon#read 3, iclass 26, count 0 2006.253.08:09:21.59#ibcon#about to read 4, iclass 26, count 0 2006.253.08:09:21.59#ibcon#read 4, iclass 26, count 0 2006.253.08:09:21.59#ibcon#about to read 5, iclass 26, count 0 2006.253.08:09:21.59#ibcon#read 5, iclass 26, count 0 2006.253.08:09:21.59#ibcon#about to read 6, iclass 26, count 0 2006.253.08:09:21.59#ibcon#read 6, iclass 26, count 0 2006.253.08:09:21.59#ibcon#end of sib2, iclass 26, count 0 2006.253.08:09:21.59#ibcon#*mode == 0, iclass 26, count 0 2006.253.08:09:21.59#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.253.08:09:21.59#ibcon#[27=USB\r\n] 2006.253.08:09:21.59#ibcon#*before write, iclass 26, count 0 2006.253.08:09:21.59#ibcon#enter sib2, iclass 26, count 0 2006.253.08:09:21.59#ibcon#flushed, iclass 26, count 0 2006.253.08:09:21.59#ibcon#about to write, iclass 26, count 0 2006.253.08:09:21.59#ibcon#wrote, iclass 26, count 0 2006.253.08:09:21.59#ibcon#about to read 3, iclass 26, count 0 2006.253.08:09:21.62#ibcon#read 3, iclass 26, count 0 2006.253.08:09:21.62#ibcon#about to read 4, iclass 26, count 0 2006.253.08:09:21.62#ibcon#read 4, iclass 26, count 0 2006.253.08:09:21.62#ibcon#about to read 5, iclass 26, count 0 2006.253.08:09:21.62#ibcon#read 5, iclass 26, count 0 2006.253.08:09:21.62#ibcon#about to read 6, iclass 26, count 0 2006.253.08:09:21.62#ibcon#read 6, iclass 26, count 0 2006.253.08:09:21.62#ibcon#end of sib2, iclass 26, count 0 2006.253.08:09:21.62#ibcon#*after write, iclass 26, count 0 2006.253.08:09:21.62#ibcon#*before return 0, iclass 26, count 0 2006.253.08:09:21.62#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.253.08:09:21.62#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.253.08:09:21.62#ibcon#about to clear, iclass 26 cls_cnt 0 2006.253.08:09:21.62#ibcon#cleared, iclass 26 cls_cnt 0 2006.253.08:09:21.62$vc4f8/vblo=4,712.99 2006.253.08:09:21.62#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.253.08:09:21.62#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.253.08:09:21.62#ibcon#ireg 17 cls_cnt 0 2006.253.08:09:21.62#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.253.08:09:21.62#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.253.08:09:21.62#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.253.08:09:21.62#ibcon#enter wrdev, iclass 28, count 0 2006.253.08:09:21.62#ibcon#first serial, iclass 28, count 0 2006.253.08:09:21.62#ibcon#enter sib2, iclass 28, count 0 2006.253.08:09:21.62#ibcon#flushed, iclass 28, count 0 2006.253.08:09:21.62#ibcon#about to write, iclass 28, count 0 2006.253.08:09:21.62#ibcon#wrote, iclass 28, count 0 2006.253.08:09:21.62#ibcon#about to read 3, iclass 28, count 0 2006.253.08:09:21.64#ibcon#read 3, iclass 28, count 0 2006.253.08:09:21.64#ibcon#about to read 4, iclass 28, count 0 2006.253.08:09:21.64#ibcon#read 4, iclass 28, count 0 2006.253.08:09:21.64#ibcon#about to read 5, iclass 28, count 0 2006.253.08:09:21.64#ibcon#read 5, iclass 28, count 0 2006.253.08:09:21.64#ibcon#about to read 6, iclass 28, count 0 2006.253.08:09:21.64#ibcon#read 6, iclass 28, count 0 2006.253.08:09:21.64#ibcon#end of sib2, iclass 28, count 0 2006.253.08:09:21.64#ibcon#*mode == 0, iclass 28, count 0 2006.253.08:09:21.64#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.253.08:09:21.64#ibcon#[28=FRQ=04,712.99\r\n] 2006.253.08:09:21.64#ibcon#*before write, iclass 28, count 0 2006.253.08:09:21.64#ibcon#enter sib2, iclass 28, count 0 2006.253.08:09:21.64#ibcon#flushed, iclass 28, count 0 2006.253.08:09:21.64#ibcon#about to write, iclass 28, count 0 2006.253.08:09:21.64#ibcon#wrote, iclass 28, count 0 2006.253.08:09:21.64#ibcon#about to read 3, iclass 28, count 0 2006.253.08:09:21.68#ibcon#read 3, iclass 28, count 0 2006.253.08:09:21.68#ibcon#about to read 4, iclass 28, count 0 2006.253.08:09:21.68#ibcon#read 4, iclass 28, count 0 2006.253.08:09:21.68#ibcon#about to read 5, iclass 28, count 0 2006.253.08:09:21.68#ibcon#read 5, iclass 28, count 0 2006.253.08:09:21.68#ibcon#about to read 6, iclass 28, count 0 2006.253.08:09:21.68#ibcon#read 6, iclass 28, count 0 2006.253.08:09:21.68#ibcon#end of sib2, iclass 28, count 0 2006.253.08:09:21.68#ibcon#*after write, iclass 28, count 0 2006.253.08:09:21.68#ibcon#*before return 0, iclass 28, count 0 2006.253.08:09:21.68#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.253.08:09:21.68#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.253.08:09:21.68#ibcon#about to clear, iclass 28 cls_cnt 0 2006.253.08:09:21.68#ibcon#cleared, iclass 28 cls_cnt 0 2006.253.08:09:21.68$vc4f8/vb=4,4 2006.253.08:09:21.68#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.253.08:09:21.68#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.253.08:09:21.68#ibcon#ireg 11 cls_cnt 2 2006.253.08:09:21.68#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.253.08:09:21.74#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.253.08:09:21.74#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.253.08:09:21.74#ibcon#enter wrdev, iclass 30, count 2 2006.253.08:09:21.74#ibcon#first serial, iclass 30, count 2 2006.253.08:09:21.74#ibcon#enter sib2, iclass 30, count 2 2006.253.08:09:21.74#ibcon#flushed, iclass 30, count 2 2006.253.08:09:21.74#ibcon#about to write, iclass 30, count 2 2006.253.08:09:21.74#ibcon#wrote, iclass 30, count 2 2006.253.08:09:21.74#ibcon#about to read 3, iclass 30, count 2 2006.253.08:09:21.76#ibcon#read 3, iclass 30, count 2 2006.253.08:09:21.76#ibcon#about to read 4, iclass 30, count 2 2006.253.08:09:21.76#ibcon#read 4, iclass 30, count 2 2006.253.08:09:21.76#ibcon#about to read 5, iclass 30, count 2 2006.253.08:09:21.76#ibcon#read 5, iclass 30, count 2 2006.253.08:09:21.76#ibcon#about to read 6, iclass 30, count 2 2006.253.08:09:21.76#ibcon#read 6, iclass 30, count 2 2006.253.08:09:21.76#ibcon#end of sib2, iclass 30, count 2 2006.253.08:09:21.76#ibcon#*mode == 0, iclass 30, count 2 2006.253.08:09:21.76#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.253.08:09:21.76#ibcon#[27=AT04-04\r\n] 2006.253.08:09:21.76#ibcon#*before write, iclass 30, count 2 2006.253.08:09:21.76#ibcon#enter sib2, iclass 30, count 2 2006.253.08:09:21.76#ibcon#flushed, iclass 30, count 2 2006.253.08:09:21.76#ibcon#about to write, iclass 30, count 2 2006.253.08:09:21.76#ibcon#wrote, iclass 30, count 2 2006.253.08:09:21.76#ibcon#about to read 3, iclass 30, count 2 2006.253.08:09:21.79#ibcon#read 3, iclass 30, count 2 2006.253.08:09:21.79#ibcon#about to read 4, iclass 30, count 2 2006.253.08:09:21.79#ibcon#read 4, iclass 30, count 2 2006.253.08:09:21.79#ibcon#about to read 5, iclass 30, count 2 2006.253.08:09:21.79#ibcon#read 5, iclass 30, count 2 2006.253.08:09:21.79#ibcon#about to read 6, iclass 30, count 2 2006.253.08:09:21.79#ibcon#read 6, iclass 30, count 2 2006.253.08:09:21.79#ibcon#end of sib2, iclass 30, count 2 2006.253.08:09:21.79#ibcon#*after write, iclass 30, count 2 2006.253.08:09:21.79#ibcon#*before return 0, iclass 30, count 2 2006.253.08:09:21.79#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.253.08:09:21.79#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.253.08:09:21.79#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.253.08:09:21.79#ibcon#ireg 7 cls_cnt 0 2006.253.08:09:21.79#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.253.08:09:21.91#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.253.08:09:21.91#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.253.08:09:21.91#ibcon#enter wrdev, iclass 30, count 0 2006.253.08:09:21.91#ibcon#first serial, iclass 30, count 0 2006.253.08:09:21.91#ibcon#enter sib2, iclass 30, count 0 2006.253.08:09:21.91#ibcon#flushed, iclass 30, count 0 2006.253.08:09:21.91#ibcon#about to write, iclass 30, count 0 2006.253.08:09:21.91#ibcon#wrote, iclass 30, count 0 2006.253.08:09:21.91#ibcon#about to read 3, iclass 30, count 0 2006.253.08:09:21.93#ibcon#read 3, iclass 30, count 0 2006.253.08:09:21.93#ibcon#about to read 4, iclass 30, count 0 2006.253.08:09:21.93#ibcon#read 4, iclass 30, count 0 2006.253.08:09:21.93#ibcon#about to read 5, iclass 30, count 0 2006.253.08:09:21.93#ibcon#read 5, iclass 30, count 0 2006.253.08:09:21.93#ibcon#about to read 6, iclass 30, count 0 2006.253.08:09:21.93#ibcon#read 6, iclass 30, count 0 2006.253.08:09:21.93#ibcon#end of sib2, iclass 30, count 0 2006.253.08:09:21.93#ibcon#*mode == 0, iclass 30, count 0 2006.253.08:09:21.93#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.253.08:09:21.93#ibcon#[27=USB\r\n] 2006.253.08:09:21.93#ibcon#*before write, iclass 30, count 0 2006.253.08:09:21.93#ibcon#enter sib2, iclass 30, count 0 2006.253.08:09:21.93#ibcon#flushed, iclass 30, count 0 2006.253.08:09:21.93#ibcon#about to write, iclass 30, count 0 2006.253.08:09:21.93#ibcon#wrote, iclass 30, count 0 2006.253.08:09:21.93#ibcon#about to read 3, iclass 30, count 0 2006.253.08:09:21.96#ibcon#read 3, iclass 30, count 0 2006.253.08:09:21.96#ibcon#about to read 4, iclass 30, count 0 2006.253.08:09:21.96#ibcon#read 4, iclass 30, count 0 2006.253.08:09:21.96#ibcon#about to read 5, iclass 30, count 0 2006.253.08:09:21.96#ibcon#read 5, iclass 30, count 0 2006.253.08:09:21.96#ibcon#about to read 6, iclass 30, count 0 2006.253.08:09:21.96#ibcon#read 6, iclass 30, count 0 2006.253.08:09:21.96#ibcon#end of sib2, iclass 30, count 0 2006.253.08:09:21.96#ibcon#*after write, iclass 30, count 0 2006.253.08:09:21.96#ibcon#*before return 0, iclass 30, count 0 2006.253.08:09:21.96#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.253.08:09:21.96#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.253.08:09:21.96#ibcon#about to clear, iclass 30 cls_cnt 0 2006.253.08:09:21.96#ibcon#cleared, iclass 30 cls_cnt 0 2006.253.08:09:21.96$vc4f8/vblo=5,744.99 2006.253.08:09:21.96#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.253.08:09:21.96#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.253.08:09:21.96#ibcon#ireg 17 cls_cnt 0 2006.253.08:09:21.96#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.253.08:09:21.96#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.253.08:09:21.96#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.253.08:09:21.96#ibcon#enter wrdev, iclass 32, count 0 2006.253.08:09:21.96#ibcon#first serial, iclass 32, count 0 2006.253.08:09:21.96#ibcon#enter sib2, iclass 32, count 0 2006.253.08:09:21.96#ibcon#flushed, iclass 32, count 0 2006.253.08:09:21.96#ibcon#about to write, iclass 32, count 0 2006.253.08:09:21.96#ibcon#wrote, iclass 32, count 0 2006.253.08:09:21.96#ibcon#about to read 3, iclass 32, count 0 2006.253.08:09:21.98#ibcon#read 3, iclass 32, count 0 2006.253.08:09:21.98#ibcon#about to read 4, iclass 32, count 0 2006.253.08:09:21.98#ibcon#read 4, iclass 32, count 0 2006.253.08:09:21.98#ibcon#about to read 5, iclass 32, count 0 2006.253.08:09:21.98#ibcon#read 5, iclass 32, count 0 2006.253.08:09:21.98#ibcon#about to read 6, iclass 32, count 0 2006.253.08:09:21.98#ibcon#read 6, iclass 32, count 0 2006.253.08:09:21.98#ibcon#end of sib2, iclass 32, count 0 2006.253.08:09:21.98#ibcon#*mode == 0, iclass 32, count 0 2006.253.08:09:21.98#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.253.08:09:21.98#ibcon#[28=FRQ=05,744.99\r\n] 2006.253.08:09:21.98#ibcon#*before write, iclass 32, count 0 2006.253.08:09:21.98#ibcon#enter sib2, iclass 32, count 0 2006.253.08:09:21.98#ibcon#flushed, iclass 32, count 0 2006.253.08:09:21.98#ibcon#about to write, iclass 32, count 0 2006.253.08:09:21.98#ibcon#wrote, iclass 32, count 0 2006.253.08:09:21.98#ibcon#about to read 3, iclass 32, count 0 2006.253.08:09:22.03#ibcon#read 3, iclass 32, count 0 2006.253.08:09:22.03#ibcon#about to read 4, iclass 32, count 0 2006.253.08:09:22.03#ibcon#read 4, iclass 32, count 0 2006.253.08:09:22.03#ibcon#about to read 5, iclass 32, count 0 2006.253.08:09:22.03#ibcon#read 5, iclass 32, count 0 2006.253.08:09:22.03#ibcon#about to read 6, iclass 32, count 0 2006.253.08:09:22.03#ibcon#read 6, iclass 32, count 0 2006.253.08:09:22.03#ibcon#end of sib2, iclass 32, count 0 2006.253.08:09:22.03#ibcon#*after write, iclass 32, count 0 2006.253.08:09:22.03#ibcon#*before return 0, iclass 32, count 0 2006.253.08:09:22.03#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.253.08:09:22.03#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.253.08:09:22.03#ibcon#about to clear, iclass 32 cls_cnt 0 2006.253.08:09:22.03#ibcon#cleared, iclass 32 cls_cnt 0 2006.253.08:09:22.03$vc4f8/vb=5,4 2006.253.08:09:22.03#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.253.08:09:22.03#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.253.08:09:22.03#ibcon#ireg 11 cls_cnt 2 2006.253.08:09:22.03#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.253.08:09:22.08#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.253.08:09:22.08#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.253.08:09:22.08#ibcon#enter wrdev, iclass 34, count 2 2006.253.08:09:22.08#ibcon#first serial, iclass 34, count 2 2006.253.08:09:22.08#ibcon#enter sib2, iclass 34, count 2 2006.253.08:09:22.08#ibcon#flushed, iclass 34, count 2 2006.253.08:09:22.08#ibcon#about to write, iclass 34, count 2 2006.253.08:09:22.08#ibcon#wrote, iclass 34, count 2 2006.253.08:09:22.08#ibcon#about to read 3, iclass 34, count 2 2006.253.08:09:22.10#ibcon#read 3, iclass 34, count 2 2006.253.08:09:22.10#ibcon#about to read 4, iclass 34, count 2 2006.253.08:09:22.10#ibcon#read 4, iclass 34, count 2 2006.253.08:09:22.10#ibcon#about to read 5, iclass 34, count 2 2006.253.08:09:22.10#ibcon#read 5, iclass 34, count 2 2006.253.08:09:22.10#ibcon#about to read 6, iclass 34, count 2 2006.253.08:09:22.10#ibcon#read 6, iclass 34, count 2 2006.253.08:09:22.10#ibcon#end of sib2, iclass 34, count 2 2006.253.08:09:22.10#ibcon#*mode == 0, iclass 34, count 2 2006.253.08:09:22.10#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.253.08:09:22.10#ibcon#[27=AT05-04\r\n] 2006.253.08:09:22.10#ibcon#*before write, iclass 34, count 2 2006.253.08:09:22.10#ibcon#enter sib2, iclass 34, count 2 2006.253.08:09:22.10#ibcon#flushed, iclass 34, count 2 2006.253.08:09:22.10#ibcon#about to write, iclass 34, count 2 2006.253.08:09:22.10#ibcon#wrote, iclass 34, count 2 2006.253.08:09:22.10#ibcon#about to read 3, iclass 34, count 2 2006.253.08:09:22.13#ibcon#read 3, iclass 34, count 2 2006.253.08:09:22.13#ibcon#about to read 4, iclass 34, count 2 2006.253.08:09:22.13#ibcon#read 4, iclass 34, count 2 2006.253.08:09:22.13#ibcon#about to read 5, iclass 34, count 2 2006.253.08:09:22.13#ibcon#read 5, iclass 34, count 2 2006.253.08:09:22.13#ibcon#about to read 6, iclass 34, count 2 2006.253.08:09:22.13#ibcon#read 6, iclass 34, count 2 2006.253.08:09:22.13#ibcon#end of sib2, iclass 34, count 2 2006.253.08:09:22.13#ibcon#*after write, iclass 34, count 2 2006.253.08:09:22.13#ibcon#*before return 0, iclass 34, count 2 2006.253.08:09:22.13#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.253.08:09:22.13#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.253.08:09:22.13#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.253.08:09:22.13#ibcon#ireg 7 cls_cnt 0 2006.253.08:09:22.13#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.253.08:09:22.25#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.253.08:09:22.25#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.253.08:09:22.25#ibcon#enter wrdev, iclass 34, count 0 2006.253.08:09:22.25#ibcon#first serial, iclass 34, count 0 2006.253.08:09:22.25#ibcon#enter sib2, iclass 34, count 0 2006.253.08:09:22.25#ibcon#flushed, iclass 34, count 0 2006.253.08:09:22.25#ibcon#about to write, iclass 34, count 0 2006.253.08:09:22.25#ibcon#wrote, iclass 34, count 0 2006.253.08:09:22.25#ibcon#about to read 3, iclass 34, count 0 2006.253.08:09:22.27#ibcon#read 3, iclass 34, count 0 2006.253.08:09:22.27#ibcon#about to read 4, iclass 34, count 0 2006.253.08:09:22.27#ibcon#read 4, iclass 34, count 0 2006.253.08:09:22.27#ibcon#about to read 5, iclass 34, count 0 2006.253.08:09:22.27#ibcon#read 5, iclass 34, count 0 2006.253.08:09:22.27#ibcon#about to read 6, iclass 34, count 0 2006.253.08:09:22.27#ibcon#read 6, iclass 34, count 0 2006.253.08:09:22.27#ibcon#end of sib2, iclass 34, count 0 2006.253.08:09:22.27#ibcon#*mode == 0, iclass 34, count 0 2006.253.08:09:22.27#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.253.08:09:22.27#ibcon#[27=USB\r\n] 2006.253.08:09:22.27#ibcon#*before write, iclass 34, count 0 2006.253.08:09:22.27#ibcon#enter sib2, iclass 34, count 0 2006.253.08:09:22.27#ibcon#flushed, iclass 34, count 0 2006.253.08:09:22.27#ibcon#about to write, iclass 34, count 0 2006.253.08:09:22.27#ibcon#wrote, iclass 34, count 0 2006.253.08:09:22.27#ibcon#about to read 3, iclass 34, count 0 2006.253.08:09:22.30#ibcon#read 3, iclass 34, count 0 2006.253.08:09:22.30#ibcon#about to read 4, iclass 34, count 0 2006.253.08:09:22.30#ibcon#read 4, iclass 34, count 0 2006.253.08:09:22.30#ibcon#about to read 5, iclass 34, count 0 2006.253.08:09:22.30#ibcon#read 5, iclass 34, count 0 2006.253.08:09:22.30#ibcon#about to read 6, iclass 34, count 0 2006.253.08:09:22.30#ibcon#read 6, iclass 34, count 0 2006.253.08:09:22.30#ibcon#end of sib2, iclass 34, count 0 2006.253.08:09:22.30#ibcon#*after write, iclass 34, count 0 2006.253.08:09:22.30#ibcon#*before return 0, iclass 34, count 0 2006.253.08:09:22.30#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.253.08:09:22.30#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.253.08:09:22.30#ibcon#about to clear, iclass 34 cls_cnt 0 2006.253.08:09:22.30#ibcon#cleared, iclass 34 cls_cnt 0 2006.253.08:09:22.30$vc4f8/vblo=6,752.99 2006.253.08:09:22.30#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.253.08:09:22.30#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.253.08:09:22.30#ibcon#ireg 17 cls_cnt 0 2006.253.08:09:22.30#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.253.08:09:22.30#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.253.08:09:22.30#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.253.08:09:22.30#ibcon#enter wrdev, iclass 36, count 0 2006.253.08:09:22.30#ibcon#first serial, iclass 36, count 0 2006.253.08:09:22.30#ibcon#enter sib2, iclass 36, count 0 2006.253.08:09:22.30#ibcon#flushed, iclass 36, count 0 2006.253.08:09:22.30#ibcon#about to write, iclass 36, count 0 2006.253.08:09:22.30#ibcon#wrote, iclass 36, count 0 2006.253.08:09:22.30#ibcon#about to read 3, iclass 36, count 0 2006.253.08:09:22.32#ibcon#read 3, iclass 36, count 0 2006.253.08:09:22.32#ibcon#about to read 4, iclass 36, count 0 2006.253.08:09:22.32#ibcon#read 4, iclass 36, count 0 2006.253.08:09:22.32#ibcon#about to read 5, iclass 36, count 0 2006.253.08:09:22.32#ibcon#read 5, iclass 36, count 0 2006.253.08:09:22.32#ibcon#about to read 6, iclass 36, count 0 2006.253.08:09:22.32#ibcon#read 6, iclass 36, count 0 2006.253.08:09:22.32#ibcon#end of sib2, iclass 36, count 0 2006.253.08:09:22.32#ibcon#*mode == 0, iclass 36, count 0 2006.253.08:09:22.32#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.253.08:09:22.32#ibcon#[28=FRQ=06,752.99\r\n] 2006.253.08:09:22.32#ibcon#*before write, iclass 36, count 0 2006.253.08:09:22.32#ibcon#enter sib2, iclass 36, count 0 2006.253.08:09:22.32#ibcon#flushed, iclass 36, count 0 2006.253.08:09:22.32#ibcon#about to write, iclass 36, count 0 2006.253.08:09:22.32#ibcon#wrote, iclass 36, count 0 2006.253.08:09:22.32#ibcon#about to read 3, iclass 36, count 0 2006.253.08:09:22.36#ibcon#read 3, iclass 36, count 0 2006.253.08:09:22.36#ibcon#about to read 4, iclass 36, count 0 2006.253.08:09:22.36#ibcon#read 4, iclass 36, count 0 2006.253.08:09:22.36#ibcon#about to read 5, iclass 36, count 0 2006.253.08:09:22.36#ibcon#read 5, iclass 36, count 0 2006.253.08:09:22.36#ibcon#about to read 6, iclass 36, count 0 2006.253.08:09:22.36#ibcon#read 6, iclass 36, count 0 2006.253.08:09:22.36#ibcon#end of sib2, iclass 36, count 0 2006.253.08:09:22.36#ibcon#*after write, iclass 36, count 0 2006.253.08:09:22.36#ibcon#*before return 0, iclass 36, count 0 2006.253.08:09:22.36#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.253.08:09:22.36#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.253.08:09:22.36#ibcon#about to clear, iclass 36 cls_cnt 0 2006.253.08:09:22.36#ibcon#cleared, iclass 36 cls_cnt 0 2006.253.08:09:22.36$vc4f8/vb=6,4 2006.253.08:09:22.36#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.253.08:09:22.36#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.253.08:09:22.36#ibcon#ireg 11 cls_cnt 2 2006.253.08:09:22.36#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.253.08:09:22.42#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.253.08:09:22.42#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.253.08:09:22.42#ibcon#enter wrdev, iclass 38, count 2 2006.253.08:09:22.42#ibcon#first serial, iclass 38, count 2 2006.253.08:09:22.42#ibcon#enter sib2, iclass 38, count 2 2006.253.08:09:22.42#ibcon#flushed, iclass 38, count 2 2006.253.08:09:22.42#ibcon#about to write, iclass 38, count 2 2006.253.08:09:22.42#ibcon#wrote, iclass 38, count 2 2006.253.08:09:22.42#ibcon#about to read 3, iclass 38, count 2 2006.253.08:09:22.44#ibcon#read 3, iclass 38, count 2 2006.253.08:09:22.44#ibcon#about to read 4, iclass 38, count 2 2006.253.08:09:22.44#ibcon#read 4, iclass 38, count 2 2006.253.08:09:22.44#ibcon#about to read 5, iclass 38, count 2 2006.253.08:09:22.44#ibcon#read 5, iclass 38, count 2 2006.253.08:09:22.44#ibcon#about to read 6, iclass 38, count 2 2006.253.08:09:22.44#ibcon#read 6, iclass 38, count 2 2006.253.08:09:22.44#ibcon#end of sib2, iclass 38, count 2 2006.253.08:09:22.44#ibcon#*mode == 0, iclass 38, count 2 2006.253.08:09:22.44#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.253.08:09:22.44#ibcon#[27=AT06-04\r\n] 2006.253.08:09:22.44#ibcon#*before write, iclass 38, count 2 2006.253.08:09:22.44#ibcon#enter sib2, iclass 38, count 2 2006.253.08:09:22.44#ibcon#flushed, iclass 38, count 2 2006.253.08:09:22.44#ibcon#about to write, iclass 38, count 2 2006.253.08:09:22.44#ibcon#wrote, iclass 38, count 2 2006.253.08:09:22.44#ibcon#about to read 3, iclass 38, count 2 2006.253.08:09:22.47#ibcon#read 3, iclass 38, count 2 2006.253.08:09:22.47#ibcon#about to read 4, iclass 38, count 2 2006.253.08:09:22.47#ibcon#read 4, iclass 38, count 2 2006.253.08:09:22.47#ibcon#about to read 5, iclass 38, count 2 2006.253.08:09:22.47#ibcon#read 5, iclass 38, count 2 2006.253.08:09:22.47#ibcon#about to read 6, iclass 38, count 2 2006.253.08:09:22.47#ibcon#read 6, iclass 38, count 2 2006.253.08:09:22.47#ibcon#end of sib2, iclass 38, count 2 2006.253.08:09:22.47#ibcon#*after write, iclass 38, count 2 2006.253.08:09:22.47#ibcon#*before return 0, iclass 38, count 2 2006.253.08:09:22.47#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.253.08:09:22.47#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.253.08:09:22.47#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.253.08:09:22.47#ibcon#ireg 7 cls_cnt 0 2006.253.08:09:22.47#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.253.08:09:22.59#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.253.08:09:22.59#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.253.08:09:22.59#ibcon#enter wrdev, iclass 38, count 0 2006.253.08:09:22.59#ibcon#first serial, iclass 38, count 0 2006.253.08:09:22.59#ibcon#enter sib2, iclass 38, count 0 2006.253.08:09:22.59#ibcon#flushed, iclass 38, count 0 2006.253.08:09:22.59#ibcon#about to write, iclass 38, count 0 2006.253.08:09:22.59#ibcon#wrote, iclass 38, count 0 2006.253.08:09:22.59#ibcon#about to read 3, iclass 38, count 0 2006.253.08:09:22.61#ibcon#read 3, iclass 38, count 0 2006.253.08:09:22.61#ibcon#about to read 4, iclass 38, count 0 2006.253.08:09:22.61#ibcon#read 4, iclass 38, count 0 2006.253.08:09:22.61#ibcon#about to read 5, iclass 38, count 0 2006.253.08:09:22.61#ibcon#read 5, iclass 38, count 0 2006.253.08:09:22.61#ibcon#about to read 6, iclass 38, count 0 2006.253.08:09:22.61#ibcon#read 6, iclass 38, count 0 2006.253.08:09:22.61#ibcon#end of sib2, iclass 38, count 0 2006.253.08:09:22.61#ibcon#*mode == 0, iclass 38, count 0 2006.253.08:09:22.61#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.253.08:09:22.61#ibcon#[27=USB\r\n] 2006.253.08:09:22.61#ibcon#*before write, iclass 38, count 0 2006.253.08:09:22.61#ibcon#enter sib2, iclass 38, count 0 2006.253.08:09:22.61#ibcon#flushed, iclass 38, count 0 2006.253.08:09:22.61#ibcon#about to write, iclass 38, count 0 2006.253.08:09:22.61#ibcon#wrote, iclass 38, count 0 2006.253.08:09:22.61#ibcon#about to read 3, iclass 38, count 0 2006.253.08:09:22.64#ibcon#read 3, iclass 38, count 0 2006.253.08:09:22.64#ibcon#about to read 4, iclass 38, count 0 2006.253.08:09:22.64#ibcon#read 4, iclass 38, count 0 2006.253.08:09:22.64#ibcon#about to read 5, iclass 38, count 0 2006.253.08:09:22.64#ibcon#read 5, iclass 38, count 0 2006.253.08:09:22.64#ibcon#about to read 6, iclass 38, count 0 2006.253.08:09:22.64#ibcon#read 6, iclass 38, count 0 2006.253.08:09:22.64#ibcon#end of sib2, iclass 38, count 0 2006.253.08:09:22.64#ibcon#*after write, iclass 38, count 0 2006.253.08:09:22.64#ibcon#*before return 0, iclass 38, count 0 2006.253.08:09:22.64#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.253.08:09:22.64#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.253.08:09:22.64#ibcon#about to clear, iclass 38 cls_cnt 0 2006.253.08:09:22.64#ibcon#cleared, iclass 38 cls_cnt 0 2006.253.08:09:22.64$vc4f8/vabw=wide 2006.253.08:09:22.64#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.253.08:09:22.64#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.253.08:09:22.64#ibcon#ireg 8 cls_cnt 0 2006.253.08:09:22.64#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.253.08:09:22.64#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.253.08:09:22.64#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.253.08:09:22.64#ibcon#enter wrdev, iclass 40, count 0 2006.253.08:09:22.64#ibcon#first serial, iclass 40, count 0 2006.253.08:09:22.64#ibcon#enter sib2, iclass 40, count 0 2006.253.08:09:22.64#ibcon#flushed, iclass 40, count 0 2006.253.08:09:22.64#ibcon#about to write, iclass 40, count 0 2006.253.08:09:22.64#ibcon#wrote, iclass 40, count 0 2006.253.08:09:22.64#ibcon#about to read 3, iclass 40, count 0 2006.253.08:09:22.66#ibcon#read 3, iclass 40, count 0 2006.253.08:09:22.66#ibcon#about to read 4, iclass 40, count 0 2006.253.08:09:22.66#ibcon#read 4, iclass 40, count 0 2006.253.08:09:22.66#ibcon#about to read 5, iclass 40, count 0 2006.253.08:09:22.66#ibcon#read 5, iclass 40, count 0 2006.253.08:09:22.66#ibcon#about to read 6, iclass 40, count 0 2006.253.08:09:22.66#ibcon#read 6, iclass 40, count 0 2006.253.08:09:22.66#ibcon#end of sib2, iclass 40, count 0 2006.253.08:09:22.66#ibcon#*mode == 0, iclass 40, count 0 2006.253.08:09:22.66#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.253.08:09:22.66#ibcon#[25=BW32\r\n] 2006.253.08:09:22.66#ibcon#*before write, iclass 40, count 0 2006.253.08:09:22.66#ibcon#enter sib2, iclass 40, count 0 2006.253.08:09:22.66#ibcon#flushed, iclass 40, count 0 2006.253.08:09:22.66#ibcon#about to write, iclass 40, count 0 2006.253.08:09:22.66#ibcon#wrote, iclass 40, count 0 2006.253.08:09:22.66#ibcon#about to read 3, iclass 40, count 0 2006.253.08:09:22.70#ibcon#read 3, iclass 40, count 0 2006.253.08:09:22.70#ibcon#about to read 4, iclass 40, count 0 2006.253.08:09:22.70#ibcon#read 4, iclass 40, count 0 2006.253.08:09:22.70#ibcon#about to read 5, iclass 40, count 0 2006.253.08:09:22.70#ibcon#read 5, iclass 40, count 0 2006.253.08:09:22.70#ibcon#about to read 6, iclass 40, count 0 2006.253.08:09:22.70#ibcon#read 6, iclass 40, count 0 2006.253.08:09:22.70#ibcon#end of sib2, iclass 40, count 0 2006.253.08:09:22.70#ibcon#*after write, iclass 40, count 0 2006.253.08:09:22.70#ibcon#*before return 0, iclass 40, count 0 2006.253.08:09:22.70#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.253.08:09:22.70#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.253.08:09:22.70#ibcon#about to clear, iclass 40 cls_cnt 0 2006.253.08:09:22.70#ibcon#cleared, iclass 40 cls_cnt 0 2006.253.08:09:22.70$vc4f8/vbbw=wide 2006.253.08:09:22.70#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.253.08:09:22.70#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.253.08:09:22.70#ibcon#ireg 8 cls_cnt 0 2006.253.08:09:22.70#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.253.08:09:22.76#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.253.08:09:22.76#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.253.08:09:22.76#ibcon#enter wrdev, iclass 4, count 0 2006.253.08:09:22.76#ibcon#first serial, iclass 4, count 0 2006.253.08:09:22.76#ibcon#enter sib2, iclass 4, count 0 2006.253.08:09:22.76#ibcon#flushed, iclass 4, count 0 2006.253.08:09:22.76#ibcon#about to write, iclass 4, count 0 2006.253.08:09:22.76#ibcon#wrote, iclass 4, count 0 2006.253.08:09:22.76#ibcon#about to read 3, iclass 4, count 0 2006.253.08:09:22.78#ibcon#read 3, iclass 4, count 0 2006.253.08:09:22.78#ibcon#about to read 4, iclass 4, count 0 2006.253.08:09:22.78#ibcon#read 4, iclass 4, count 0 2006.253.08:09:22.78#ibcon#about to read 5, iclass 4, count 0 2006.253.08:09:22.78#ibcon#read 5, iclass 4, count 0 2006.253.08:09:22.78#ibcon#about to read 6, iclass 4, count 0 2006.253.08:09:22.78#ibcon#read 6, iclass 4, count 0 2006.253.08:09:22.78#ibcon#end of sib2, iclass 4, count 0 2006.253.08:09:22.78#ibcon#*mode == 0, iclass 4, count 0 2006.253.08:09:22.78#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.253.08:09:22.78#ibcon#[27=BW32\r\n] 2006.253.08:09:22.78#ibcon#*before write, iclass 4, count 0 2006.253.08:09:22.78#ibcon#enter sib2, iclass 4, count 0 2006.253.08:09:22.78#ibcon#flushed, iclass 4, count 0 2006.253.08:09:22.78#ibcon#about to write, iclass 4, count 0 2006.253.08:09:22.78#ibcon#wrote, iclass 4, count 0 2006.253.08:09:22.78#ibcon#about to read 3, iclass 4, count 0 2006.253.08:09:22.81#ibcon#read 3, iclass 4, count 0 2006.253.08:09:22.81#ibcon#about to read 4, iclass 4, count 0 2006.253.08:09:22.81#ibcon#read 4, iclass 4, count 0 2006.253.08:09:22.81#ibcon#about to read 5, iclass 4, count 0 2006.253.08:09:22.81#ibcon#read 5, iclass 4, count 0 2006.253.08:09:22.81#ibcon#about to read 6, iclass 4, count 0 2006.253.08:09:22.81#ibcon#read 6, iclass 4, count 0 2006.253.08:09:22.81#ibcon#end of sib2, iclass 4, count 0 2006.253.08:09:22.81#ibcon#*after write, iclass 4, count 0 2006.253.08:09:22.81#ibcon#*before return 0, iclass 4, count 0 2006.253.08:09:22.81#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.253.08:09:22.81#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.253.08:09:22.81#ibcon#about to clear, iclass 4 cls_cnt 0 2006.253.08:09:22.81#ibcon#cleared, iclass 4 cls_cnt 0 2006.253.08:09:22.81$4f8m12a/ifd4f 2006.253.08:09:22.81$ifd4f/lo= 2006.253.08:09:22.81$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.253.08:09:22.81$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.253.08:09:22.81$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.253.08:09:22.81$ifd4f/patch= 2006.253.08:09:22.81$ifd4f/patch=lo1,a1,a2,a3,a4 2006.253.08:09:22.81$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.253.08:09:22.81$ifd4f/patch=lo3,a5,a6,a7,a8 2006.253.08:09:22.81$4f8m12a/"form=m,16.000,1:2 2006.253.08:09:22.81$4f8m12a/"tpicd 2006.253.08:09:22.81$4f8m12a/echo=off 2006.253.08:09:22.81$4f8m12a/xlog=off 2006.253.08:09:22.81:!2006.253.08:09:50 2006.253.08:09:34.14#trakl#Source acquired 2006.253.08:09:35.14#flagr#flagr/antenna,acquired 2006.253.08:09:50.00:preob 2006.253.08:09:51.14/onsource/TRACKING 2006.253.08:09:51.14:!2006.253.08:10:00 2006.253.08:10:00.00:data_valid=on 2006.253.08:10:00.00:midob 2006.253.08:10:00.14/onsource/TRACKING 2006.253.08:10:00.14/wx/30.97,1006.5,74 2006.253.08:10:00.23/cable/+6.3685E-03 2006.253.08:10:01.32/va/01,08,usb,yes,31,32 2006.253.08:10:01.32/va/02,07,usb,yes,31,32 2006.253.08:10:01.32/va/03,06,usb,yes,33,33 2006.253.08:10:01.32/va/04,07,usb,yes,32,35 2006.253.08:10:01.32/va/05,07,usb,yes,34,35 2006.253.08:10:01.32/va/06,07,usb,yes,29,29 2006.253.08:10:01.32/va/07,07,usb,yes,29,29 2006.253.08:10:01.32/va/08,07,usb,yes,32,31 2006.253.08:10:01.55/valo/01,532.99,yes,locked 2006.253.08:10:01.55/valo/02,572.99,yes,locked 2006.253.08:10:01.55/valo/03,672.99,yes,locked 2006.253.08:10:01.55/valo/04,832.99,yes,locked 2006.253.08:10:01.55/valo/05,652.99,yes,locked 2006.253.08:10:01.55/valo/06,772.99,yes,locked 2006.253.08:10:01.55/valo/07,832.99,yes,locked 2006.253.08:10:01.55/valo/08,852.99,yes,locked 2006.253.08:10:02.64/vb/01,04,usb,yes,30,29 2006.253.08:10:02.64/vb/02,05,usb,yes,28,29 2006.253.08:10:02.64/vb/03,04,usb,yes,28,32 2006.253.08:10:02.64/vb/04,04,usb,yes,29,29 2006.253.08:10:02.64/vb/05,04,usb,yes,28,32 2006.253.08:10:02.64/vb/06,04,usb,yes,29,32 2006.253.08:10:02.64/vb/07,04,usb,yes,31,31 2006.253.08:10:02.64/vb/08,04,usb,yes,28,32 2006.253.08:10:02.88/vblo/01,632.99,yes,locked 2006.253.08:10:02.88/vblo/02,640.99,yes,locked 2006.253.08:10:02.88/vblo/03,656.99,yes,locked 2006.253.08:10:02.88/vblo/04,712.99,yes,locked 2006.253.08:10:02.88/vblo/05,744.99,yes,locked 2006.253.08:10:02.88/vblo/06,752.99,yes,locked 2006.253.08:10:02.88/vblo/07,734.99,yes,locked 2006.253.08:10:02.88/vblo/08,744.99,yes,locked 2006.253.08:10:03.03/vabw/8 2006.253.08:10:03.18/vbbw/8 2006.253.08:10:03.27/xfe/off,on,14.7 2006.253.08:10:03.65/ifatt/23,28,28,28 2006.253.08:10:04.08/fmout-gps/S +4.76E-07 2006.253.08:10:04.12:!2006.253.08:11:00 2006.253.08:11:00.00:data_valid=off 2006.253.08:11:00.00:postob 2006.253.08:11:00.08/cable/+6.3680E-03 2006.253.08:11:00.08/wx/30.97,1006.5,74 2006.253.08:11:01.08/fmout-gps/S +4.74E-07 2006.253.08:11:01.08:scan_name=253-0812,k06253,70 2006.253.08:11:01.08:source=1219+044,122222.55,041315.8,2000.0,ccw 2006.253.08:11:01.14#flagr#flagr/antenna,new-source 2006.253.08:11:02.14:checkk5 2006.253.08:11:02.54/chk_autoobs//k5ts1/ autoobs is running! 2006.253.08:11:02.91/chk_autoobs//k5ts2/ autoobs is running! 2006.253.08:11:03.29/chk_autoobs//k5ts3/ autoobs is running! 2006.253.08:11:03.65/chk_autoobs//k5ts4/ autoobs is running! 2006.253.08:11:04.02/chk_obsdata//k5ts1/T2530810??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.08:11:04.40/chk_obsdata//k5ts2/T2530810??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.08:11:04.77/chk_obsdata//k5ts3/T2530810??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.08:11:05.15/chk_obsdata//k5ts4/T2530810??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.08:11:05.85/k5log//k5ts1_log_newline 2006.253.08:11:06.54/k5log//k5ts2_log_newline 2006.253.08:11:07.24/k5log//k5ts3_log_newline 2006.253.08:11:07.93/k5log//k5ts4_log_newline 2006.253.08:11:07.95/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.253.08:11:07.95:4f8m12a=2 2006.253.08:11:07.95$4f8m12a/echo=on 2006.253.08:11:07.95$4f8m12a/pcalon 2006.253.08:11:07.95$pcalon/"no phase cal control is implemented here 2006.253.08:11:07.95$4f8m12a/"tpicd=stop 2006.253.08:11:07.95$4f8m12a/vc4f8 2006.253.08:11:07.95$vc4f8/valo=1,532.99 2006.253.08:11:07.96#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.253.08:11:07.96#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.253.08:11:07.96#ibcon#ireg 17 cls_cnt 0 2006.253.08:11:07.96#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.253.08:11:07.96#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.253.08:11:07.96#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.253.08:11:07.96#ibcon#enter wrdev, iclass 6, count 0 2006.253.08:11:07.96#ibcon#first serial, iclass 6, count 0 2006.253.08:11:07.96#ibcon#enter sib2, iclass 6, count 0 2006.253.08:11:07.96#ibcon#flushed, iclass 6, count 0 2006.253.08:11:07.96#ibcon#about to write, iclass 6, count 0 2006.253.08:11:07.96#ibcon#wrote, iclass 6, count 0 2006.253.08:11:07.96#ibcon#about to read 3, iclass 6, count 0 2006.253.08:11:08.00#ibcon#read 3, iclass 6, count 0 2006.253.08:11:08.00#ibcon#about to read 4, iclass 6, count 0 2006.253.08:11:08.00#ibcon#read 4, iclass 6, count 0 2006.253.08:11:08.00#ibcon#about to read 5, iclass 6, count 0 2006.253.08:11:08.00#ibcon#read 5, iclass 6, count 0 2006.253.08:11:08.00#ibcon#about to read 6, iclass 6, count 0 2006.253.08:11:08.00#ibcon#read 6, iclass 6, count 0 2006.253.08:11:08.00#ibcon#end of sib2, iclass 6, count 0 2006.253.08:11:08.00#ibcon#*mode == 0, iclass 6, count 0 2006.253.08:11:08.00#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.253.08:11:08.00#ibcon#[26=FRQ=01,532.99\r\n] 2006.253.08:11:08.00#ibcon#*before write, iclass 6, count 0 2006.253.08:11:08.00#ibcon#enter sib2, iclass 6, count 0 2006.253.08:11:08.00#ibcon#flushed, iclass 6, count 0 2006.253.08:11:08.00#ibcon#about to write, iclass 6, count 0 2006.253.08:11:08.00#ibcon#wrote, iclass 6, count 0 2006.253.08:11:08.00#ibcon#about to read 3, iclass 6, count 0 2006.253.08:11:08.05#ibcon#read 3, iclass 6, count 0 2006.253.08:11:08.05#ibcon#about to read 4, iclass 6, count 0 2006.253.08:11:08.05#ibcon#read 4, iclass 6, count 0 2006.253.08:11:08.05#ibcon#about to read 5, iclass 6, count 0 2006.253.08:11:08.05#ibcon#read 5, iclass 6, count 0 2006.253.08:11:08.05#ibcon#about to read 6, iclass 6, count 0 2006.253.08:11:08.05#ibcon#read 6, iclass 6, count 0 2006.253.08:11:08.05#ibcon#end of sib2, iclass 6, count 0 2006.253.08:11:08.05#ibcon#*after write, iclass 6, count 0 2006.253.08:11:08.05#ibcon#*before return 0, iclass 6, count 0 2006.253.08:11:08.05#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.253.08:11:08.05#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.253.08:11:08.05#ibcon#about to clear, iclass 6 cls_cnt 0 2006.253.08:11:08.05#ibcon#cleared, iclass 6 cls_cnt 0 2006.253.08:11:08.05$vc4f8/va=1,8 2006.253.08:11:08.05#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.253.08:11:08.05#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.253.08:11:08.05#ibcon#ireg 11 cls_cnt 2 2006.253.08:11:08.05#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.253.08:11:08.05#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.253.08:11:08.05#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.253.08:11:08.05#ibcon#enter wrdev, iclass 10, count 2 2006.253.08:11:08.05#ibcon#first serial, iclass 10, count 2 2006.253.08:11:08.05#ibcon#enter sib2, iclass 10, count 2 2006.253.08:11:08.05#ibcon#flushed, iclass 10, count 2 2006.253.08:11:08.05#ibcon#about to write, iclass 10, count 2 2006.253.08:11:08.05#ibcon#wrote, iclass 10, count 2 2006.253.08:11:08.05#ibcon#about to read 3, iclass 10, count 2 2006.253.08:11:08.07#ibcon#read 3, iclass 10, count 2 2006.253.08:11:08.07#ibcon#about to read 4, iclass 10, count 2 2006.253.08:11:08.07#ibcon#read 4, iclass 10, count 2 2006.253.08:11:08.07#ibcon#about to read 5, iclass 10, count 2 2006.253.08:11:08.07#ibcon#read 5, iclass 10, count 2 2006.253.08:11:08.07#ibcon#about to read 6, iclass 10, count 2 2006.253.08:11:08.07#ibcon#read 6, iclass 10, count 2 2006.253.08:11:08.07#ibcon#end of sib2, iclass 10, count 2 2006.253.08:11:08.07#ibcon#*mode == 0, iclass 10, count 2 2006.253.08:11:08.07#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.253.08:11:08.07#ibcon#[25=AT01-08\r\n] 2006.253.08:11:08.07#ibcon#*before write, iclass 10, count 2 2006.253.08:11:08.07#ibcon#enter sib2, iclass 10, count 2 2006.253.08:11:08.07#ibcon#flushed, iclass 10, count 2 2006.253.08:11:08.07#ibcon#about to write, iclass 10, count 2 2006.253.08:11:08.07#ibcon#wrote, iclass 10, count 2 2006.253.08:11:08.07#ibcon#about to read 3, iclass 10, count 2 2006.253.08:11:08.10#ibcon#read 3, iclass 10, count 2 2006.253.08:11:08.10#ibcon#about to read 4, iclass 10, count 2 2006.253.08:11:08.10#ibcon#read 4, iclass 10, count 2 2006.253.08:11:08.10#ibcon#about to read 5, iclass 10, count 2 2006.253.08:11:08.10#ibcon#read 5, iclass 10, count 2 2006.253.08:11:08.10#ibcon#about to read 6, iclass 10, count 2 2006.253.08:11:08.10#ibcon#read 6, iclass 10, count 2 2006.253.08:11:08.10#ibcon#end of sib2, iclass 10, count 2 2006.253.08:11:08.10#ibcon#*after write, iclass 10, count 2 2006.253.08:11:08.10#ibcon#*before return 0, iclass 10, count 2 2006.253.08:11:08.10#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.253.08:11:08.10#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.253.08:11:08.10#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.253.08:11:08.10#ibcon#ireg 7 cls_cnt 0 2006.253.08:11:08.10#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.253.08:11:08.22#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.253.08:11:08.22#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.253.08:11:08.22#ibcon#enter wrdev, iclass 10, count 0 2006.253.08:11:08.22#ibcon#first serial, iclass 10, count 0 2006.253.08:11:08.22#ibcon#enter sib2, iclass 10, count 0 2006.253.08:11:08.22#ibcon#flushed, iclass 10, count 0 2006.253.08:11:08.22#ibcon#about to write, iclass 10, count 0 2006.253.08:11:08.22#ibcon#wrote, iclass 10, count 0 2006.253.08:11:08.22#ibcon#about to read 3, iclass 10, count 0 2006.253.08:11:08.24#ibcon#read 3, iclass 10, count 0 2006.253.08:11:08.24#ibcon#about to read 4, iclass 10, count 0 2006.253.08:11:08.24#ibcon#read 4, iclass 10, count 0 2006.253.08:11:08.24#ibcon#about to read 5, iclass 10, count 0 2006.253.08:11:08.24#ibcon#read 5, iclass 10, count 0 2006.253.08:11:08.24#ibcon#about to read 6, iclass 10, count 0 2006.253.08:11:08.24#ibcon#read 6, iclass 10, count 0 2006.253.08:11:08.24#ibcon#end of sib2, iclass 10, count 0 2006.253.08:11:08.24#ibcon#*mode == 0, iclass 10, count 0 2006.253.08:11:08.24#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.253.08:11:08.24#ibcon#[25=USB\r\n] 2006.253.08:11:08.24#ibcon#*before write, iclass 10, count 0 2006.253.08:11:08.24#ibcon#enter sib2, iclass 10, count 0 2006.253.08:11:08.24#ibcon#flushed, iclass 10, count 0 2006.253.08:11:08.24#ibcon#about to write, iclass 10, count 0 2006.253.08:11:08.24#ibcon#wrote, iclass 10, count 0 2006.253.08:11:08.24#ibcon#about to read 3, iclass 10, count 0 2006.253.08:11:08.27#ibcon#read 3, iclass 10, count 0 2006.253.08:11:08.27#ibcon#about to read 4, iclass 10, count 0 2006.253.08:11:08.27#ibcon#read 4, iclass 10, count 0 2006.253.08:11:08.27#ibcon#about to read 5, iclass 10, count 0 2006.253.08:11:08.27#ibcon#read 5, iclass 10, count 0 2006.253.08:11:08.27#ibcon#about to read 6, iclass 10, count 0 2006.253.08:11:08.27#ibcon#read 6, iclass 10, count 0 2006.253.08:11:08.27#ibcon#end of sib2, iclass 10, count 0 2006.253.08:11:08.27#ibcon#*after write, iclass 10, count 0 2006.253.08:11:08.27#ibcon#*before return 0, iclass 10, count 0 2006.253.08:11:08.27#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.253.08:11:08.27#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.253.08:11:08.27#ibcon#about to clear, iclass 10 cls_cnt 0 2006.253.08:11:08.27#ibcon#cleared, iclass 10 cls_cnt 0 2006.253.08:11:08.27$vc4f8/valo=2,572.99 2006.253.08:11:08.27#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.253.08:11:08.27#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.253.08:11:08.27#ibcon#ireg 17 cls_cnt 0 2006.253.08:11:08.27#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.253.08:11:08.27#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.253.08:11:08.27#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.253.08:11:08.27#ibcon#enter wrdev, iclass 12, count 0 2006.253.08:11:08.27#ibcon#first serial, iclass 12, count 0 2006.253.08:11:08.27#ibcon#enter sib2, iclass 12, count 0 2006.253.08:11:08.27#ibcon#flushed, iclass 12, count 0 2006.253.08:11:08.27#ibcon#about to write, iclass 12, count 0 2006.253.08:11:08.27#ibcon#wrote, iclass 12, count 0 2006.253.08:11:08.27#ibcon#about to read 3, iclass 12, count 0 2006.253.08:11:08.29#ibcon#read 3, iclass 12, count 0 2006.253.08:11:08.29#ibcon#about to read 4, iclass 12, count 0 2006.253.08:11:08.29#ibcon#read 4, iclass 12, count 0 2006.253.08:11:08.29#ibcon#about to read 5, iclass 12, count 0 2006.253.08:11:08.29#ibcon#read 5, iclass 12, count 0 2006.253.08:11:08.29#ibcon#about to read 6, iclass 12, count 0 2006.253.08:11:08.29#ibcon#read 6, iclass 12, count 0 2006.253.08:11:08.29#ibcon#end of sib2, iclass 12, count 0 2006.253.08:11:08.29#ibcon#*mode == 0, iclass 12, count 0 2006.253.08:11:08.29#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.253.08:11:08.29#ibcon#[26=FRQ=02,572.99\r\n] 2006.253.08:11:08.29#ibcon#*before write, iclass 12, count 0 2006.253.08:11:08.29#ibcon#enter sib2, iclass 12, count 0 2006.253.08:11:08.29#ibcon#flushed, iclass 12, count 0 2006.253.08:11:08.29#ibcon#about to write, iclass 12, count 0 2006.253.08:11:08.29#ibcon#wrote, iclass 12, count 0 2006.253.08:11:08.29#ibcon#about to read 3, iclass 12, count 0 2006.253.08:11:08.34#ibcon#read 3, iclass 12, count 0 2006.253.08:11:08.34#ibcon#about to read 4, iclass 12, count 0 2006.253.08:11:08.34#ibcon#read 4, iclass 12, count 0 2006.253.08:11:08.34#ibcon#about to read 5, iclass 12, count 0 2006.253.08:11:08.34#ibcon#read 5, iclass 12, count 0 2006.253.08:11:08.34#ibcon#about to read 6, iclass 12, count 0 2006.253.08:11:08.34#ibcon#read 6, iclass 12, count 0 2006.253.08:11:08.34#ibcon#end of sib2, iclass 12, count 0 2006.253.08:11:08.34#ibcon#*after write, iclass 12, count 0 2006.253.08:11:08.34#ibcon#*before return 0, iclass 12, count 0 2006.253.08:11:08.34#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.253.08:11:08.34#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.253.08:11:08.34#ibcon#about to clear, iclass 12 cls_cnt 0 2006.253.08:11:08.34#ibcon#cleared, iclass 12 cls_cnt 0 2006.253.08:11:08.34$vc4f8/va=2,7 2006.253.08:11:08.34#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.253.08:11:08.34#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.253.08:11:08.34#ibcon#ireg 11 cls_cnt 2 2006.253.08:11:08.34#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.253.08:11:08.39#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.253.08:11:08.39#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.253.08:11:08.39#ibcon#enter wrdev, iclass 14, count 2 2006.253.08:11:08.39#ibcon#first serial, iclass 14, count 2 2006.253.08:11:08.39#ibcon#enter sib2, iclass 14, count 2 2006.253.08:11:08.39#ibcon#flushed, iclass 14, count 2 2006.253.08:11:08.39#ibcon#about to write, iclass 14, count 2 2006.253.08:11:08.39#ibcon#wrote, iclass 14, count 2 2006.253.08:11:08.39#ibcon#about to read 3, iclass 14, count 2 2006.253.08:11:08.41#ibcon#read 3, iclass 14, count 2 2006.253.08:11:08.41#ibcon#about to read 4, iclass 14, count 2 2006.253.08:11:08.41#ibcon#read 4, iclass 14, count 2 2006.253.08:11:08.41#ibcon#about to read 5, iclass 14, count 2 2006.253.08:11:08.41#ibcon#read 5, iclass 14, count 2 2006.253.08:11:08.41#ibcon#about to read 6, iclass 14, count 2 2006.253.08:11:08.41#ibcon#read 6, iclass 14, count 2 2006.253.08:11:08.41#ibcon#end of sib2, iclass 14, count 2 2006.253.08:11:08.41#ibcon#*mode == 0, iclass 14, count 2 2006.253.08:11:08.41#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.253.08:11:08.41#ibcon#[25=AT02-07\r\n] 2006.253.08:11:08.41#ibcon#*before write, iclass 14, count 2 2006.253.08:11:08.41#ibcon#enter sib2, iclass 14, count 2 2006.253.08:11:08.41#ibcon#flushed, iclass 14, count 2 2006.253.08:11:08.41#ibcon#about to write, iclass 14, count 2 2006.253.08:11:08.41#ibcon#wrote, iclass 14, count 2 2006.253.08:11:08.41#ibcon#about to read 3, iclass 14, count 2 2006.253.08:11:08.44#ibcon#read 3, iclass 14, count 2 2006.253.08:11:08.44#ibcon#about to read 4, iclass 14, count 2 2006.253.08:11:08.44#ibcon#read 4, iclass 14, count 2 2006.253.08:11:08.44#ibcon#about to read 5, iclass 14, count 2 2006.253.08:11:08.44#ibcon#read 5, iclass 14, count 2 2006.253.08:11:08.44#ibcon#about to read 6, iclass 14, count 2 2006.253.08:11:08.44#ibcon#read 6, iclass 14, count 2 2006.253.08:11:08.44#ibcon#end of sib2, iclass 14, count 2 2006.253.08:11:08.44#ibcon#*after write, iclass 14, count 2 2006.253.08:11:08.44#ibcon#*before return 0, iclass 14, count 2 2006.253.08:11:08.44#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.253.08:11:08.44#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.253.08:11:08.44#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.253.08:11:08.44#ibcon#ireg 7 cls_cnt 0 2006.253.08:11:08.44#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.253.08:11:08.56#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.253.08:11:08.56#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.253.08:11:08.56#ibcon#enter wrdev, iclass 14, count 0 2006.253.08:11:08.56#ibcon#first serial, iclass 14, count 0 2006.253.08:11:08.56#ibcon#enter sib2, iclass 14, count 0 2006.253.08:11:08.56#ibcon#flushed, iclass 14, count 0 2006.253.08:11:08.56#ibcon#about to write, iclass 14, count 0 2006.253.08:11:08.56#ibcon#wrote, iclass 14, count 0 2006.253.08:11:08.56#ibcon#about to read 3, iclass 14, count 0 2006.253.08:11:08.58#ibcon#read 3, iclass 14, count 0 2006.253.08:11:08.58#ibcon#about to read 4, iclass 14, count 0 2006.253.08:11:08.58#ibcon#read 4, iclass 14, count 0 2006.253.08:11:08.58#ibcon#about to read 5, iclass 14, count 0 2006.253.08:11:08.58#ibcon#read 5, iclass 14, count 0 2006.253.08:11:08.58#ibcon#about to read 6, iclass 14, count 0 2006.253.08:11:08.58#ibcon#read 6, iclass 14, count 0 2006.253.08:11:08.58#ibcon#end of sib2, iclass 14, count 0 2006.253.08:11:08.58#ibcon#*mode == 0, iclass 14, count 0 2006.253.08:11:08.58#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.253.08:11:08.58#ibcon#[25=USB\r\n] 2006.253.08:11:08.58#ibcon#*before write, iclass 14, count 0 2006.253.08:11:08.58#ibcon#enter sib2, iclass 14, count 0 2006.253.08:11:08.58#ibcon#flushed, iclass 14, count 0 2006.253.08:11:08.58#ibcon#about to write, iclass 14, count 0 2006.253.08:11:08.58#ibcon#wrote, iclass 14, count 0 2006.253.08:11:08.58#ibcon#about to read 3, iclass 14, count 0 2006.253.08:11:08.61#ibcon#read 3, iclass 14, count 0 2006.253.08:11:08.61#ibcon#about to read 4, iclass 14, count 0 2006.253.08:11:08.61#ibcon#read 4, iclass 14, count 0 2006.253.08:11:08.61#ibcon#about to read 5, iclass 14, count 0 2006.253.08:11:08.61#ibcon#read 5, iclass 14, count 0 2006.253.08:11:08.61#ibcon#about to read 6, iclass 14, count 0 2006.253.08:11:08.61#ibcon#read 6, iclass 14, count 0 2006.253.08:11:08.61#ibcon#end of sib2, iclass 14, count 0 2006.253.08:11:08.61#ibcon#*after write, iclass 14, count 0 2006.253.08:11:08.61#ibcon#*before return 0, iclass 14, count 0 2006.253.08:11:08.61#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.253.08:11:08.61#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.253.08:11:08.61#ibcon#about to clear, iclass 14 cls_cnt 0 2006.253.08:11:08.61#ibcon#cleared, iclass 14 cls_cnt 0 2006.253.08:11:08.61$vc4f8/valo=3,672.99 2006.253.08:11:08.61#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.253.08:11:08.61#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.253.08:11:08.61#ibcon#ireg 17 cls_cnt 0 2006.253.08:11:08.61#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.253.08:11:08.61#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.253.08:11:08.61#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.253.08:11:08.61#ibcon#enter wrdev, iclass 16, count 0 2006.253.08:11:08.61#ibcon#first serial, iclass 16, count 0 2006.253.08:11:08.61#ibcon#enter sib2, iclass 16, count 0 2006.253.08:11:08.61#ibcon#flushed, iclass 16, count 0 2006.253.08:11:08.61#ibcon#about to write, iclass 16, count 0 2006.253.08:11:08.61#ibcon#wrote, iclass 16, count 0 2006.253.08:11:08.61#ibcon#about to read 3, iclass 16, count 0 2006.253.08:11:08.63#ibcon#read 3, iclass 16, count 0 2006.253.08:11:08.63#ibcon#about to read 4, iclass 16, count 0 2006.253.08:11:08.63#ibcon#read 4, iclass 16, count 0 2006.253.08:11:08.63#ibcon#about to read 5, iclass 16, count 0 2006.253.08:11:08.63#ibcon#read 5, iclass 16, count 0 2006.253.08:11:08.63#ibcon#about to read 6, iclass 16, count 0 2006.253.08:11:08.63#ibcon#read 6, iclass 16, count 0 2006.253.08:11:08.63#ibcon#end of sib2, iclass 16, count 0 2006.253.08:11:08.63#ibcon#*mode == 0, iclass 16, count 0 2006.253.08:11:08.63#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.253.08:11:08.63#ibcon#[26=FRQ=03,672.99\r\n] 2006.253.08:11:08.63#ibcon#*before write, iclass 16, count 0 2006.253.08:11:08.63#ibcon#enter sib2, iclass 16, count 0 2006.253.08:11:08.63#ibcon#flushed, iclass 16, count 0 2006.253.08:11:08.63#ibcon#about to write, iclass 16, count 0 2006.253.08:11:08.63#ibcon#wrote, iclass 16, count 0 2006.253.08:11:08.63#ibcon#about to read 3, iclass 16, count 0 2006.253.08:11:08.67#ibcon#read 3, iclass 16, count 0 2006.253.08:11:08.67#ibcon#about to read 4, iclass 16, count 0 2006.253.08:11:08.67#ibcon#read 4, iclass 16, count 0 2006.253.08:11:08.67#ibcon#about to read 5, iclass 16, count 0 2006.253.08:11:08.67#ibcon#read 5, iclass 16, count 0 2006.253.08:11:08.67#ibcon#about to read 6, iclass 16, count 0 2006.253.08:11:08.67#ibcon#read 6, iclass 16, count 0 2006.253.08:11:08.67#ibcon#end of sib2, iclass 16, count 0 2006.253.08:11:08.67#ibcon#*after write, iclass 16, count 0 2006.253.08:11:08.67#ibcon#*before return 0, iclass 16, count 0 2006.253.08:11:08.67#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.253.08:11:08.67#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.253.08:11:08.67#ibcon#about to clear, iclass 16 cls_cnt 0 2006.253.08:11:08.67#ibcon#cleared, iclass 16 cls_cnt 0 2006.253.08:11:08.67$vc4f8/va=3,6 2006.253.08:11:08.67#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.253.08:11:08.67#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.253.08:11:08.67#ibcon#ireg 11 cls_cnt 2 2006.253.08:11:08.67#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.253.08:11:08.73#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.253.08:11:08.73#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.253.08:11:08.73#ibcon#enter wrdev, iclass 18, count 2 2006.253.08:11:08.73#ibcon#first serial, iclass 18, count 2 2006.253.08:11:08.73#ibcon#enter sib2, iclass 18, count 2 2006.253.08:11:08.73#ibcon#flushed, iclass 18, count 2 2006.253.08:11:08.73#ibcon#about to write, iclass 18, count 2 2006.253.08:11:08.73#ibcon#wrote, iclass 18, count 2 2006.253.08:11:08.73#ibcon#about to read 3, iclass 18, count 2 2006.253.08:11:08.75#ibcon#read 3, iclass 18, count 2 2006.253.08:11:08.75#ibcon#about to read 4, iclass 18, count 2 2006.253.08:11:08.75#ibcon#read 4, iclass 18, count 2 2006.253.08:11:08.75#ibcon#about to read 5, iclass 18, count 2 2006.253.08:11:08.75#ibcon#read 5, iclass 18, count 2 2006.253.08:11:08.75#ibcon#about to read 6, iclass 18, count 2 2006.253.08:11:08.75#ibcon#read 6, iclass 18, count 2 2006.253.08:11:08.75#ibcon#end of sib2, iclass 18, count 2 2006.253.08:11:08.75#ibcon#*mode == 0, iclass 18, count 2 2006.253.08:11:08.75#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.253.08:11:08.75#ibcon#[25=AT03-06\r\n] 2006.253.08:11:08.75#ibcon#*before write, iclass 18, count 2 2006.253.08:11:08.75#ibcon#enter sib2, iclass 18, count 2 2006.253.08:11:08.75#ibcon#flushed, iclass 18, count 2 2006.253.08:11:08.75#ibcon#about to write, iclass 18, count 2 2006.253.08:11:08.75#ibcon#wrote, iclass 18, count 2 2006.253.08:11:08.75#ibcon#about to read 3, iclass 18, count 2 2006.253.08:11:08.78#ibcon#read 3, iclass 18, count 2 2006.253.08:11:08.78#ibcon#about to read 4, iclass 18, count 2 2006.253.08:11:08.78#ibcon#read 4, iclass 18, count 2 2006.253.08:11:08.78#ibcon#about to read 5, iclass 18, count 2 2006.253.08:11:08.78#ibcon#read 5, iclass 18, count 2 2006.253.08:11:08.78#ibcon#about to read 6, iclass 18, count 2 2006.253.08:11:08.78#ibcon#read 6, iclass 18, count 2 2006.253.08:11:08.78#ibcon#end of sib2, iclass 18, count 2 2006.253.08:11:08.78#ibcon#*after write, iclass 18, count 2 2006.253.08:11:08.78#ibcon#*before return 0, iclass 18, count 2 2006.253.08:11:08.78#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.253.08:11:08.78#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.253.08:11:08.78#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.253.08:11:08.78#ibcon#ireg 7 cls_cnt 0 2006.253.08:11:08.78#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.253.08:11:08.90#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.253.08:11:08.90#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.253.08:11:08.90#ibcon#enter wrdev, iclass 18, count 0 2006.253.08:11:08.90#ibcon#first serial, iclass 18, count 0 2006.253.08:11:08.90#ibcon#enter sib2, iclass 18, count 0 2006.253.08:11:08.90#ibcon#flushed, iclass 18, count 0 2006.253.08:11:08.90#ibcon#about to write, iclass 18, count 0 2006.253.08:11:08.90#ibcon#wrote, iclass 18, count 0 2006.253.08:11:08.90#ibcon#about to read 3, iclass 18, count 0 2006.253.08:11:08.92#ibcon#read 3, iclass 18, count 0 2006.253.08:11:08.92#ibcon#about to read 4, iclass 18, count 0 2006.253.08:11:08.92#ibcon#read 4, iclass 18, count 0 2006.253.08:11:08.92#ibcon#about to read 5, iclass 18, count 0 2006.253.08:11:08.92#ibcon#read 5, iclass 18, count 0 2006.253.08:11:08.92#ibcon#about to read 6, iclass 18, count 0 2006.253.08:11:08.92#ibcon#read 6, iclass 18, count 0 2006.253.08:11:08.92#ibcon#end of sib2, iclass 18, count 0 2006.253.08:11:08.92#ibcon#*mode == 0, iclass 18, count 0 2006.253.08:11:08.92#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.253.08:11:08.92#ibcon#[25=USB\r\n] 2006.253.08:11:08.92#ibcon#*before write, iclass 18, count 0 2006.253.08:11:08.92#ibcon#enter sib2, iclass 18, count 0 2006.253.08:11:08.92#ibcon#flushed, iclass 18, count 0 2006.253.08:11:08.92#ibcon#about to write, iclass 18, count 0 2006.253.08:11:08.92#ibcon#wrote, iclass 18, count 0 2006.253.08:11:08.92#ibcon#about to read 3, iclass 18, count 0 2006.253.08:11:08.95#ibcon#read 3, iclass 18, count 0 2006.253.08:11:08.95#ibcon#about to read 4, iclass 18, count 0 2006.253.08:11:08.95#ibcon#read 4, iclass 18, count 0 2006.253.08:11:08.95#ibcon#about to read 5, iclass 18, count 0 2006.253.08:11:08.95#ibcon#read 5, iclass 18, count 0 2006.253.08:11:08.95#ibcon#about to read 6, iclass 18, count 0 2006.253.08:11:08.95#ibcon#read 6, iclass 18, count 0 2006.253.08:11:08.95#ibcon#end of sib2, iclass 18, count 0 2006.253.08:11:08.95#ibcon#*after write, iclass 18, count 0 2006.253.08:11:08.95#ibcon#*before return 0, iclass 18, count 0 2006.253.08:11:08.95#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.253.08:11:08.95#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.253.08:11:08.95#ibcon#about to clear, iclass 18 cls_cnt 0 2006.253.08:11:08.95#ibcon#cleared, iclass 18 cls_cnt 0 2006.253.08:11:08.95$vc4f8/valo=4,832.99 2006.253.08:11:08.95#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.253.08:11:08.95#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.253.08:11:08.95#ibcon#ireg 17 cls_cnt 0 2006.253.08:11:08.95#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.253.08:11:08.95#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.253.08:11:08.95#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.253.08:11:08.95#ibcon#enter wrdev, iclass 20, count 0 2006.253.08:11:08.95#ibcon#first serial, iclass 20, count 0 2006.253.08:11:08.95#ibcon#enter sib2, iclass 20, count 0 2006.253.08:11:08.95#ibcon#flushed, iclass 20, count 0 2006.253.08:11:08.95#ibcon#about to write, iclass 20, count 0 2006.253.08:11:08.95#ibcon#wrote, iclass 20, count 0 2006.253.08:11:08.95#ibcon#about to read 3, iclass 20, count 0 2006.253.08:11:08.97#ibcon#read 3, iclass 20, count 0 2006.253.08:11:08.97#ibcon#about to read 4, iclass 20, count 0 2006.253.08:11:08.97#ibcon#read 4, iclass 20, count 0 2006.253.08:11:08.97#ibcon#about to read 5, iclass 20, count 0 2006.253.08:11:08.97#ibcon#read 5, iclass 20, count 0 2006.253.08:11:08.97#ibcon#about to read 6, iclass 20, count 0 2006.253.08:11:08.97#ibcon#read 6, iclass 20, count 0 2006.253.08:11:08.97#ibcon#end of sib2, iclass 20, count 0 2006.253.08:11:08.97#ibcon#*mode == 0, iclass 20, count 0 2006.253.08:11:08.97#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.253.08:11:08.97#ibcon#[26=FRQ=04,832.99\r\n] 2006.253.08:11:08.97#ibcon#*before write, iclass 20, count 0 2006.253.08:11:08.97#ibcon#enter sib2, iclass 20, count 0 2006.253.08:11:08.97#ibcon#flushed, iclass 20, count 0 2006.253.08:11:08.97#ibcon#about to write, iclass 20, count 0 2006.253.08:11:08.97#ibcon#wrote, iclass 20, count 0 2006.253.08:11:08.97#ibcon#about to read 3, iclass 20, count 0 2006.253.08:11:09.01#ibcon#read 3, iclass 20, count 0 2006.253.08:11:09.01#ibcon#about to read 4, iclass 20, count 0 2006.253.08:11:09.01#ibcon#read 4, iclass 20, count 0 2006.253.08:11:09.01#ibcon#about to read 5, iclass 20, count 0 2006.253.08:11:09.01#ibcon#read 5, iclass 20, count 0 2006.253.08:11:09.01#ibcon#about to read 6, iclass 20, count 0 2006.253.08:11:09.01#ibcon#read 6, iclass 20, count 0 2006.253.08:11:09.01#ibcon#end of sib2, iclass 20, count 0 2006.253.08:11:09.01#ibcon#*after write, iclass 20, count 0 2006.253.08:11:09.01#ibcon#*before return 0, iclass 20, count 0 2006.253.08:11:09.01#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.253.08:11:09.01#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.253.08:11:09.01#ibcon#about to clear, iclass 20 cls_cnt 0 2006.253.08:11:09.01#ibcon#cleared, iclass 20 cls_cnt 0 2006.253.08:11:09.01$vc4f8/va=4,7 2006.253.08:11:09.01#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.253.08:11:09.01#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.253.08:11:09.01#ibcon#ireg 11 cls_cnt 2 2006.253.08:11:09.01#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.253.08:11:09.07#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.253.08:11:09.07#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.253.08:11:09.07#ibcon#enter wrdev, iclass 22, count 2 2006.253.08:11:09.07#ibcon#first serial, iclass 22, count 2 2006.253.08:11:09.07#ibcon#enter sib2, iclass 22, count 2 2006.253.08:11:09.07#ibcon#flushed, iclass 22, count 2 2006.253.08:11:09.07#ibcon#about to write, iclass 22, count 2 2006.253.08:11:09.07#ibcon#wrote, iclass 22, count 2 2006.253.08:11:09.07#ibcon#about to read 3, iclass 22, count 2 2006.253.08:11:09.09#ibcon#read 3, iclass 22, count 2 2006.253.08:11:09.09#ibcon#about to read 4, iclass 22, count 2 2006.253.08:11:09.09#ibcon#read 4, iclass 22, count 2 2006.253.08:11:09.09#ibcon#about to read 5, iclass 22, count 2 2006.253.08:11:09.09#ibcon#read 5, iclass 22, count 2 2006.253.08:11:09.09#ibcon#about to read 6, iclass 22, count 2 2006.253.08:11:09.09#ibcon#read 6, iclass 22, count 2 2006.253.08:11:09.09#ibcon#end of sib2, iclass 22, count 2 2006.253.08:11:09.09#ibcon#*mode == 0, iclass 22, count 2 2006.253.08:11:09.09#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.253.08:11:09.09#ibcon#[25=AT04-07\r\n] 2006.253.08:11:09.09#ibcon#*before write, iclass 22, count 2 2006.253.08:11:09.09#ibcon#enter sib2, iclass 22, count 2 2006.253.08:11:09.09#ibcon#flushed, iclass 22, count 2 2006.253.08:11:09.09#ibcon#about to write, iclass 22, count 2 2006.253.08:11:09.09#ibcon#wrote, iclass 22, count 2 2006.253.08:11:09.09#ibcon#about to read 3, iclass 22, count 2 2006.253.08:11:09.12#ibcon#read 3, iclass 22, count 2 2006.253.08:11:09.12#ibcon#about to read 4, iclass 22, count 2 2006.253.08:11:09.12#ibcon#read 4, iclass 22, count 2 2006.253.08:11:09.12#ibcon#about to read 5, iclass 22, count 2 2006.253.08:11:09.12#ibcon#read 5, iclass 22, count 2 2006.253.08:11:09.12#ibcon#about to read 6, iclass 22, count 2 2006.253.08:11:09.12#ibcon#read 6, iclass 22, count 2 2006.253.08:11:09.12#ibcon#end of sib2, iclass 22, count 2 2006.253.08:11:09.12#ibcon#*after write, iclass 22, count 2 2006.253.08:11:09.12#ibcon#*before return 0, iclass 22, count 2 2006.253.08:11:09.12#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.253.08:11:09.12#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.253.08:11:09.12#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.253.08:11:09.12#ibcon#ireg 7 cls_cnt 0 2006.253.08:11:09.12#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.253.08:11:09.24#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.253.08:11:09.24#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.253.08:11:09.24#ibcon#enter wrdev, iclass 22, count 0 2006.253.08:11:09.24#ibcon#first serial, iclass 22, count 0 2006.253.08:11:09.24#ibcon#enter sib2, iclass 22, count 0 2006.253.08:11:09.24#ibcon#flushed, iclass 22, count 0 2006.253.08:11:09.24#ibcon#about to write, iclass 22, count 0 2006.253.08:11:09.24#ibcon#wrote, iclass 22, count 0 2006.253.08:11:09.24#ibcon#about to read 3, iclass 22, count 0 2006.253.08:11:09.26#ibcon#read 3, iclass 22, count 0 2006.253.08:11:09.26#ibcon#about to read 4, iclass 22, count 0 2006.253.08:11:09.26#ibcon#read 4, iclass 22, count 0 2006.253.08:11:09.26#ibcon#about to read 5, iclass 22, count 0 2006.253.08:11:09.26#ibcon#read 5, iclass 22, count 0 2006.253.08:11:09.26#ibcon#about to read 6, iclass 22, count 0 2006.253.08:11:09.26#ibcon#read 6, iclass 22, count 0 2006.253.08:11:09.26#ibcon#end of sib2, iclass 22, count 0 2006.253.08:11:09.26#ibcon#*mode == 0, iclass 22, count 0 2006.253.08:11:09.26#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.253.08:11:09.26#ibcon#[25=USB\r\n] 2006.253.08:11:09.26#ibcon#*before write, iclass 22, count 0 2006.253.08:11:09.26#ibcon#enter sib2, iclass 22, count 0 2006.253.08:11:09.26#ibcon#flushed, iclass 22, count 0 2006.253.08:11:09.26#ibcon#about to write, iclass 22, count 0 2006.253.08:11:09.26#ibcon#wrote, iclass 22, count 0 2006.253.08:11:09.26#ibcon#about to read 3, iclass 22, count 0 2006.253.08:11:09.29#ibcon#read 3, iclass 22, count 0 2006.253.08:11:09.29#ibcon#about to read 4, iclass 22, count 0 2006.253.08:11:09.29#ibcon#read 4, iclass 22, count 0 2006.253.08:11:09.29#ibcon#about to read 5, iclass 22, count 0 2006.253.08:11:09.29#ibcon#read 5, iclass 22, count 0 2006.253.08:11:09.29#ibcon#about to read 6, iclass 22, count 0 2006.253.08:11:09.29#ibcon#read 6, iclass 22, count 0 2006.253.08:11:09.29#ibcon#end of sib2, iclass 22, count 0 2006.253.08:11:09.29#ibcon#*after write, iclass 22, count 0 2006.253.08:11:09.29#ibcon#*before return 0, iclass 22, count 0 2006.253.08:11:09.29#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.253.08:11:09.29#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.253.08:11:09.29#ibcon#about to clear, iclass 22 cls_cnt 0 2006.253.08:11:09.29#ibcon#cleared, iclass 22 cls_cnt 0 2006.253.08:11:09.29$vc4f8/valo=5,652.99 2006.253.08:11:09.29#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.253.08:11:09.29#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.253.08:11:09.29#ibcon#ireg 17 cls_cnt 0 2006.253.08:11:09.29#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.253.08:11:09.29#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.253.08:11:09.29#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.253.08:11:09.29#ibcon#enter wrdev, iclass 24, count 0 2006.253.08:11:09.29#ibcon#first serial, iclass 24, count 0 2006.253.08:11:09.29#ibcon#enter sib2, iclass 24, count 0 2006.253.08:11:09.29#ibcon#flushed, iclass 24, count 0 2006.253.08:11:09.29#ibcon#about to write, iclass 24, count 0 2006.253.08:11:09.29#ibcon#wrote, iclass 24, count 0 2006.253.08:11:09.29#ibcon#about to read 3, iclass 24, count 0 2006.253.08:11:09.31#ibcon#read 3, iclass 24, count 0 2006.253.08:11:09.31#ibcon#about to read 4, iclass 24, count 0 2006.253.08:11:09.31#ibcon#read 4, iclass 24, count 0 2006.253.08:11:09.31#ibcon#about to read 5, iclass 24, count 0 2006.253.08:11:09.31#ibcon#read 5, iclass 24, count 0 2006.253.08:11:09.31#ibcon#about to read 6, iclass 24, count 0 2006.253.08:11:09.31#ibcon#read 6, iclass 24, count 0 2006.253.08:11:09.31#ibcon#end of sib2, iclass 24, count 0 2006.253.08:11:09.31#ibcon#*mode == 0, iclass 24, count 0 2006.253.08:11:09.31#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.253.08:11:09.31#ibcon#[26=FRQ=05,652.99\r\n] 2006.253.08:11:09.31#ibcon#*before write, iclass 24, count 0 2006.253.08:11:09.31#ibcon#enter sib2, iclass 24, count 0 2006.253.08:11:09.31#ibcon#flushed, iclass 24, count 0 2006.253.08:11:09.31#ibcon#about to write, iclass 24, count 0 2006.253.08:11:09.31#ibcon#wrote, iclass 24, count 0 2006.253.08:11:09.31#ibcon#about to read 3, iclass 24, count 0 2006.253.08:11:09.35#ibcon#read 3, iclass 24, count 0 2006.253.08:11:09.35#ibcon#about to read 4, iclass 24, count 0 2006.253.08:11:09.35#ibcon#read 4, iclass 24, count 0 2006.253.08:11:09.35#ibcon#about to read 5, iclass 24, count 0 2006.253.08:11:09.35#ibcon#read 5, iclass 24, count 0 2006.253.08:11:09.35#ibcon#about to read 6, iclass 24, count 0 2006.253.08:11:09.35#ibcon#read 6, iclass 24, count 0 2006.253.08:11:09.35#ibcon#end of sib2, iclass 24, count 0 2006.253.08:11:09.35#ibcon#*after write, iclass 24, count 0 2006.253.08:11:09.35#ibcon#*before return 0, iclass 24, count 0 2006.253.08:11:09.35#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.253.08:11:09.35#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.253.08:11:09.35#ibcon#about to clear, iclass 24 cls_cnt 0 2006.253.08:11:09.35#ibcon#cleared, iclass 24 cls_cnt 0 2006.253.08:11:09.35$vc4f8/va=5,7 2006.253.08:11:09.35#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.253.08:11:09.35#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.253.08:11:09.35#ibcon#ireg 11 cls_cnt 2 2006.253.08:11:09.35#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.253.08:11:09.41#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.253.08:11:09.41#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.253.08:11:09.41#ibcon#enter wrdev, iclass 26, count 2 2006.253.08:11:09.41#ibcon#first serial, iclass 26, count 2 2006.253.08:11:09.41#ibcon#enter sib2, iclass 26, count 2 2006.253.08:11:09.41#ibcon#flushed, iclass 26, count 2 2006.253.08:11:09.41#ibcon#about to write, iclass 26, count 2 2006.253.08:11:09.41#ibcon#wrote, iclass 26, count 2 2006.253.08:11:09.41#ibcon#about to read 3, iclass 26, count 2 2006.253.08:11:09.43#ibcon#read 3, iclass 26, count 2 2006.253.08:11:09.43#ibcon#about to read 4, iclass 26, count 2 2006.253.08:11:09.43#ibcon#read 4, iclass 26, count 2 2006.253.08:11:09.43#ibcon#about to read 5, iclass 26, count 2 2006.253.08:11:09.43#ibcon#read 5, iclass 26, count 2 2006.253.08:11:09.43#ibcon#about to read 6, iclass 26, count 2 2006.253.08:11:09.43#ibcon#read 6, iclass 26, count 2 2006.253.08:11:09.43#ibcon#end of sib2, iclass 26, count 2 2006.253.08:11:09.43#ibcon#*mode == 0, iclass 26, count 2 2006.253.08:11:09.43#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.253.08:11:09.43#ibcon#[25=AT05-07\r\n] 2006.253.08:11:09.43#ibcon#*before write, iclass 26, count 2 2006.253.08:11:09.43#ibcon#enter sib2, iclass 26, count 2 2006.253.08:11:09.43#ibcon#flushed, iclass 26, count 2 2006.253.08:11:09.43#ibcon#about to write, iclass 26, count 2 2006.253.08:11:09.43#ibcon#wrote, iclass 26, count 2 2006.253.08:11:09.43#ibcon#about to read 3, iclass 26, count 2 2006.253.08:11:09.46#ibcon#read 3, iclass 26, count 2 2006.253.08:11:09.46#ibcon#about to read 4, iclass 26, count 2 2006.253.08:11:09.46#ibcon#read 4, iclass 26, count 2 2006.253.08:11:09.46#ibcon#about to read 5, iclass 26, count 2 2006.253.08:11:09.46#ibcon#read 5, iclass 26, count 2 2006.253.08:11:09.46#ibcon#about to read 6, iclass 26, count 2 2006.253.08:11:09.46#ibcon#read 6, iclass 26, count 2 2006.253.08:11:09.46#ibcon#end of sib2, iclass 26, count 2 2006.253.08:11:09.46#ibcon#*after write, iclass 26, count 2 2006.253.08:11:09.46#ibcon#*before return 0, iclass 26, count 2 2006.253.08:11:09.46#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.253.08:11:09.46#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.253.08:11:09.46#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.253.08:11:09.46#ibcon#ireg 7 cls_cnt 0 2006.253.08:11:09.46#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.253.08:11:09.58#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.253.08:11:09.58#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.253.08:11:09.58#ibcon#enter wrdev, iclass 26, count 0 2006.253.08:11:09.58#ibcon#first serial, iclass 26, count 0 2006.253.08:11:09.58#ibcon#enter sib2, iclass 26, count 0 2006.253.08:11:09.58#ibcon#flushed, iclass 26, count 0 2006.253.08:11:09.58#ibcon#about to write, iclass 26, count 0 2006.253.08:11:09.58#ibcon#wrote, iclass 26, count 0 2006.253.08:11:09.58#ibcon#about to read 3, iclass 26, count 0 2006.253.08:11:09.60#ibcon#read 3, iclass 26, count 0 2006.253.08:11:09.60#ibcon#about to read 4, iclass 26, count 0 2006.253.08:11:09.60#ibcon#read 4, iclass 26, count 0 2006.253.08:11:09.60#ibcon#about to read 5, iclass 26, count 0 2006.253.08:11:09.60#ibcon#read 5, iclass 26, count 0 2006.253.08:11:09.60#ibcon#about to read 6, iclass 26, count 0 2006.253.08:11:09.60#ibcon#read 6, iclass 26, count 0 2006.253.08:11:09.60#ibcon#end of sib2, iclass 26, count 0 2006.253.08:11:09.60#ibcon#*mode == 0, iclass 26, count 0 2006.253.08:11:09.60#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.253.08:11:09.60#ibcon#[25=USB\r\n] 2006.253.08:11:09.60#ibcon#*before write, iclass 26, count 0 2006.253.08:11:09.60#ibcon#enter sib2, iclass 26, count 0 2006.253.08:11:09.60#ibcon#flushed, iclass 26, count 0 2006.253.08:11:09.60#ibcon#about to write, iclass 26, count 0 2006.253.08:11:09.60#ibcon#wrote, iclass 26, count 0 2006.253.08:11:09.60#ibcon#about to read 3, iclass 26, count 0 2006.253.08:11:09.63#ibcon#read 3, iclass 26, count 0 2006.253.08:11:09.63#ibcon#about to read 4, iclass 26, count 0 2006.253.08:11:09.63#ibcon#read 4, iclass 26, count 0 2006.253.08:11:09.63#ibcon#about to read 5, iclass 26, count 0 2006.253.08:11:09.63#ibcon#read 5, iclass 26, count 0 2006.253.08:11:09.63#ibcon#about to read 6, iclass 26, count 0 2006.253.08:11:09.63#ibcon#read 6, iclass 26, count 0 2006.253.08:11:09.63#ibcon#end of sib2, iclass 26, count 0 2006.253.08:11:09.63#ibcon#*after write, iclass 26, count 0 2006.253.08:11:09.63#ibcon#*before return 0, iclass 26, count 0 2006.253.08:11:09.63#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.253.08:11:09.63#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.253.08:11:09.63#ibcon#about to clear, iclass 26 cls_cnt 0 2006.253.08:11:09.63#ibcon#cleared, iclass 26 cls_cnt 0 2006.253.08:11:09.63$vc4f8/valo=6,772.99 2006.253.08:11:09.63#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.253.08:11:09.63#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.253.08:11:09.63#ibcon#ireg 17 cls_cnt 0 2006.253.08:11:09.63#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.253.08:11:09.63#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.253.08:11:09.63#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.253.08:11:09.63#ibcon#enter wrdev, iclass 28, count 0 2006.253.08:11:09.63#ibcon#first serial, iclass 28, count 0 2006.253.08:11:09.63#ibcon#enter sib2, iclass 28, count 0 2006.253.08:11:09.63#ibcon#flushed, iclass 28, count 0 2006.253.08:11:09.63#ibcon#about to write, iclass 28, count 0 2006.253.08:11:09.63#ibcon#wrote, iclass 28, count 0 2006.253.08:11:09.63#ibcon#about to read 3, iclass 28, count 0 2006.253.08:11:09.65#ibcon#read 3, iclass 28, count 0 2006.253.08:11:09.65#ibcon#about to read 4, iclass 28, count 0 2006.253.08:11:09.65#ibcon#read 4, iclass 28, count 0 2006.253.08:11:09.65#ibcon#about to read 5, iclass 28, count 0 2006.253.08:11:09.65#ibcon#read 5, iclass 28, count 0 2006.253.08:11:09.65#ibcon#about to read 6, iclass 28, count 0 2006.253.08:11:09.65#ibcon#read 6, iclass 28, count 0 2006.253.08:11:09.65#ibcon#end of sib2, iclass 28, count 0 2006.253.08:11:09.65#ibcon#*mode == 0, iclass 28, count 0 2006.253.08:11:09.65#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.253.08:11:09.65#ibcon#[26=FRQ=06,772.99\r\n] 2006.253.08:11:09.65#ibcon#*before write, iclass 28, count 0 2006.253.08:11:09.65#ibcon#enter sib2, iclass 28, count 0 2006.253.08:11:09.65#ibcon#flushed, iclass 28, count 0 2006.253.08:11:09.65#ibcon#about to write, iclass 28, count 0 2006.253.08:11:09.65#ibcon#wrote, iclass 28, count 0 2006.253.08:11:09.65#ibcon#about to read 3, iclass 28, count 0 2006.253.08:11:09.69#ibcon#read 3, iclass 28, count 0 2006.253.08:11:09.69#ibcon#about to read 4, iclass 28, count 0 2006.253.08:11:09.69#ibcon#read 4, iclass 28, count 0 2006.253.08:11:09.69#ibcon#about to read 5, iclass 28, count 0 2006.253.08:11:09.69#ibcon#read 5, iclass 28, count 0 2006.253.08:11:09.69#ibcon#about to read 6, iclass 28, count 0 2006.253.08:11:09.69#ibcon#read 6, iclass 28, count 0 2006.253.08:11:09.69#ibcon#end of sib2, iclass 28, count 0 2006.253.08:11:09.69#ibcon#*after write, iclass 28, count 0 2006.253.08:11:09.69#ibcon#*before return 0, iclass 28, count 0 2006.253.08:11:09.69#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.253.08:11:09.69#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.253.08:11:09.69#ibcon#about to clear, iclass 28 cls_cnt 0 2006.253.08:11:09.69#ibcon#cleared, iclass 28 cls_cnt 0 2006.253.08:11:09.69$vc4f8/va=6,7 2006.253.08:11:09.69#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.253.08:11:09.69#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.253.08:11:09.69#ibcon#ireg 11 cls_cnt 2 2006.253.08:11:09.69#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.253.08:11:09.75#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.253.08:11:09.75#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.253.08:11:09.75#ibcon#enter wrdev, iclass 30, count 2 2006.253.08:11:09.75#ibcon#first serial, iclass 30, count 2 2006.253.08:11:09.75#ibcon#enter sib2, iclass 30, count 2 2006.253.08:11:09.75#ibcon#flushed, iclass 30, count 2 2006.253.08:11:09.75#ibcon#about to write, iclass 30, count 2 2006.253.08:11:09.75#ibcon#wrote, iclass 30, count 2 2006.253.08:11:09.75#ibcon#about to read 3, iclass 30, count 2 2006.253.08:11:09.77#ibcon#read 3, iclass 30, count 2 2006.253.08:11:09.77#ibcon#about to read 4, iclass 30, count 2 2006.253.08:11:09.77#ibcon#read 4, iclass 30, count 2 2006.253.08:11:09.77#ibcon#about to read 5, iclass 30, count 2 2006.253.08:11:09.77#ibcon#read 5, iclass 30, count 2 2006.253.08:11:09.77#ibcon#about to read 6, iclass 30, count 2 2006.253.08:11:09.77#ibcon#read 6, iclass 30, count 2 2006.253.08:11:09.77#ibcon#end of sib2, iclass 30, count 2 2006.253.08:11:09.77#ibcon#*mode == 0, iclass 30, count 2 2006.253.08:11:09.77#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.253.08:11:09.77#ibcon#[25=AT06-07\r\n] 2006.253.08:11:09.77#ibcon#*before write, iclass 30, count 2 2006.253.08:11:09.77#ibcon#enter sib2, iclass 30, count 2 2006.253.08:11:09.77#ibcon#flushed, iclass 30, count 2 2006.253.08:11:09.77#ibcon#about to write, iclass 30, count 2 2006.253.08:11:09.77#ibcon#wrote, iclass 30, count 2 2006.253.08:11:09.77#ibcon#about to read 3, iclass 30, count 2 2006.253.08:11:09.80#ibcon#read 3, iclass 30, count 2 2006.253.08:11:09.80#ibcon#about to read 4, iclass 30, count 2 2006.253.08:11:09.80#ibcon#read 4, iclass 30, count 2 2006.253.08:11:09.80#ibcon#about to read 5, iclass 30, count 2 2006.253.08:11:09.80#ibcon#read 5, iclass 30, count 2 2006.253.08:11:09.80#ibcon#about to read 6, iclass 30, count 2 2006.253.08:11:09.80#ibcon#read 6, iclass 30, count 2 2006.253.08:11:09.80#ibcon#end of sib2, iclass 30, count 2 2006.253.08:11:09.80#ibcon#*after write, iclass 30, count 2 2006.253.08:11:09.80#ibcon#*before return 0, iclass 30, count 2 2006.253.08:11:09.80#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.253.08:11:09.80#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.253.08:11:09.80#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.253.08:11:09.80#ibcon#ireg 7 cls_cnt 0 2006.253.08:11:09.80#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.253.08:11:09.92#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.253.08:11:09.92#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.253.08:11:09.92#ibcon#enter wrdev, iclass 30, count 0 2006.253.08:11:09.92#ibcon#first serial, iclass 30, count 0 2006.253.08:11:09.92#ibcon#enter sib2, iclass 30, count 0 2006.253.08:11:09.92#ibcon#flushed, iclass 30, count 0 2006.253.08:11:09.92#ibcon#about to write, iclass 30, count 0 2006.253.08:11:09.92#ibcon#wrote, iclass 30, count 0 2006.253.08:11:09.92#ibcon#about to read 3, iclass 30, count 0 2006.253.08:11:09.94#ibcon#read 3, iclass 30, count 0 2006.253.08:11:09.94#ibcon#about to read 4, iclass 30, count 0 2006.253.08:11:09.94#ibcon#read 4, iclass 30, count 0 2006.253.08:11:09.94#ibcon#about to read 5, iclass 30, count 0 2006.253.08:11:09.94#ibcon#read 5, iclass 30, count 0 2006.253.08:11:09.94#ibcon#about to read 6, iclass 30, count 0 2006.253.08:11:09.94#ibcon#read 6, iclass 30, count 0 2006.253.08:11:09.94#ibcon#end of sib2, iclass 30, count 0 2006.253.08:11:09.94#ibcon#*mode == 0, iclass 30, count 0 2006.253.08:11:09.94#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.253.08:11:09.94#ibcon#[25=USB\r\n] 2006.253.08:11:09.94#ibcon#*before write, iclass 30, count 0 2006.253.08:11:09.94#ibcon#enter sib2, iclass 30, count 0 2006.253.08:11:09.94#ibcon#flushed, iclass 30, count 0 2006.253.08:11:09.94#ibcon#about to write, iclass 30, count 0 2006.253.08:11:09.94#ibcon#wrote, iclass 30, count 0 2006.253.08:11:09.94#ibcon#about to read 3, iclass 30, count 0 2006.253.08:11:09.97#ibcon#read 3, iclass 30, count 0 2006.253.08:11:09.97#ibcon#about to read 4, iclass 30, count 0 2006.253.08:11:09.97#ibcon#read 4, iclass 30, count 0 2006.253.08:11:09.97#ibcon#about to read 5, iclass 30, count 0 2006.253.08:11:09.97#ibcon#read 5, iclass 30, count 0 2006.253.08:11:09.97#ibcon#about to read 6, iclass 30, count 0 2006.253.08:11:09.97#ibcon#read 6, iclass 30, count 0 2006.253.08:11:09.97#ibcon#end of sib2, iclass 30, count 0 2006.253.08:11:09.97#ibcon#*after write, iclass 30, count 0 2006.253.08:11:09.97#ibcon#*before return 0, iclass 30, count 0 2006.253.08:11:09.97#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.253.08:11:09.97#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.253.08:11:09.97#ibcon#about to clear, iclass 30 cls_cnt 0 2006.253.08:11:09.97#ibcon#cleared, iclass 30 cls_cnt 0 2006.253.08:11:09.97$vc4f8/valo=7,832.99 2006.253.08:11:09.97#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.253.08:11:09.97#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.253.08:11:09.97#ibcon#ireg 17 cls_cnt 0 2006.253.08:11:09.97#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.253.08:11:09.97#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.253.08:11:09.97#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.253.08:11:09.97#ibcon#enter wrdev, iclass 32, count 0 2006.253.08:11:09.97#ibcon#first serial, iclass 32, count 0 2006.253.08:11:09.97#ibcon#enter sib2, iclass 32, count 0 2006.253.08:11:09.97#ibcon#flushed, iclass 32, count 0 2006.253.08:11:09.97#ibcon#about to write, iclass 32, count 0 2006.253.08:11:09.97#ibcon#wrote, iclass 32, count 0 2006.253.08:11:09.97#ibcon#about to read 3, iclass 32, count 0 2006.253.08:11:09.99#ibcon#read 3, iclass 32, count 0 2006.253.08:11:09.99#ibcon#about to read 4, iclass 32, count 0 2006.253.08:11:09.99#ibcon#read 4, iclass 32, count 0 2006.253.08:11:09.99#ibcon#about to read 5, iclass 32, count 0 2006.253.08:11:09.99#ibcon#read 5, iclass 32, count 0 2006.253.08:11:09.99#ibcon#about to read 6, iclass 32, count 0 2006.253.08:11:09.99#ibcon#read 6, iclass 32, count 0 2006.253.08:11:09.99#ibcon#end of sib2, iclass 32, count 0 2006.253.08:11:09.99#ibcon#*mode == 0, iclass 32, count 0 2006.253.08:11:09.99#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.253.08:11:09.99#ibcon#[26=FRQ=07,832.99\r\n] 2006.253.08:11:09.99#ibcon#*before write, iclass 32, count 0 2006.253.08:11:09.99#ibcon#enter sib2, iclass 32, count 0 2006.253.08:11:09.99#ibcon#flushed, iclass 32, count 0 2006.253.08:11:09.99#ibcon#about to write, iclass 32, count 0 2006.253.08:11:09.99#ibcon#wrote, iclass 32, count 0 2006.253.08:11:09.99#ibcon#about to read 3, iclass 32, count 0 2006.253.08:11:10.03#ibcon#read 3, iclass 32, count 0 2006.253.08:11:10.03#ibcon#about to read 4, iclass 32, count 0 2006.253.08:11:10.03#ibcon#read 4, iclass 32, count 0 2006.253.08:11:10.03#ibcon#about to read 5, iclass 32, count 0 2006.253.08:11:10.03#ibcon#read 5, iclass 32, count 0 2006.253.08:11:10.03#ibcon#about to read 6, iclass 32, count 0 2006.253.08:11:10.03#ibcon#read 6, iclass 32, count 0 2006.253.08:11:10.03#ibcon#end of sib2, iclass 32, count 0 2006.253.08:11:10.03#ibcon#*after write, iclass 32, count 0 2006.253.08:11:10.03#ibcon#*before return 0, iclass 32, count 0 2006.253.08:11:10.03#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.253.08:11:10.03#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.253.08:11:10.03#ibcon#about to clear, iclass 32 cls_cnt 0 2006.253.08:11:10.03#ibcon#cleared, iclass 32 cls_cnt 0 2006.253.08:11:10.03$vc4f8/va=7,7 2006.253.08:11:10.03#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.253.08:11:10.03#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.253.08:11:10.03#ibcon#ireg 11 cls_cnt 2 2006.253.08:11:10.03#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.253.08:11:10.09#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.253.08:11:10.09#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.253.08:11:10.09#ibcon#enter wrdev, iclass 34, count 2 2006.253.08:11:10.09#ibcon#first serial, iclass 34, count 2 2006.253.08:11:10.09#ibcon#enter sib2, iclass 34, count 2 2006.253.08:11:10.09#ibcon#flushed, iclass 34, count 2 2006.253.08:11:10.09#ibcon#about to write, iclass 34, count 2 2006.253.08:11:10.09#ibcon#wrote, iclass 34, count 2 2006.253.08:11:10.09#ibcon#about to read 3, iclass 34, count 2 2006.253.08:11:10.11#ibcon#read 3, iclass 34, count 2 2006.253.08:11:10.11#ibcon#about to read 4, iclass 34, count 2 2006.253.08:11:10.11#ibcon#read 4, iclass 34, count 2 2006.253.08:11:10.11#ibcon#about to read 5, iclass 34, count 2 2006.253.08:11:10.11#ibcon#read 5, iclass 34, count 2 2006.253.08:11:10.11#ibcon#about to read 6, iclass 34, count 2 2006.253.08:11:10.11#ibcon#read 6, iclass 34, count 2 2006.253.08:11:10.11#ibcon#end of sib2, iclass 34, count 2 2006.253.08:11:10.11#ibcon#*mode == 0, iclass 34, count 2 2006.253.08:11:10.11#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.253.08:11:10.11#ibcon#[25=AT07-07\r\n] 2006.253.08:11:10.11#ibcon#*before write, iclass 34, count 2 2006.253.08:11:10.11#ibcon#enter sib2, iclass 34, count 2 2006.253.08:11:10.11#ibcon#flushed, iclass 34, count 2 2006.253.08:11:10.11#ibcon#about to write, iclass 34, count 2 2006.253.08:11:10.11#ibcon#wrote, iclass 34, count 2 2006.253.08:11:10.11#ibcon#about to read 3, iclass 34, count 2 2006.253.08:11:10.14#ibcon#read 3, iclass 34, count 2 2006.253.08:11:10.14#ibcon#about to read 4, iclass 34, count 2 2006.253.08:11:10.14#ibcon#read 4, iclass 34, count 2 2006.253.08:11:10.14#ibcon#about to read 5, iclass 34, count 2 2006.253.08:11:10.14#ibcon#read 5, iclass 34, count 2 2006.253.08:11:10.14#ibcon#about to read 6, iclass 34, count 2 2006.253.08:11:10.14#ibcon#read 6, iclass 34, count 2 2006.253.08:11:10.14#ibcon#end of sib2, iclass 34, count 2 2006.253.08:11:10.14#ibcon#*after write, iclass 34, count 2 2006.253.08:11:10.14#ibcon#*before return 0, iclass 34, count 2 2006.253.08:11:10.14#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.253.08:11:10.14#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.253.08:11:10.14#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.253.08:11:10.14#ibcon#ireg 7 cls_cnt 0 2006.253.08:11:10.14#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.253.08:11:10.26#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.253.08:11:10.26#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.253.08:11:10.26#ibcon#enter wrdev, iclass 34, count 0 2006.253.08:11:10.26#ibcon#first serial, iclass 34, count 0 2006.253.08:11:10.26#ibcon#enter sib2, iclass 34, count 0 2006.253.08:11:10.26#ibcon#flushed, iclass 34, count 0 2006.253.08:11:10.26#ibcon#about to write, iclass 34, count 0 2006.253.08:11:10.26#ibcon#wrote, iclass 34, count 0 2006.253.08:11:10.26#ibcon#about to read 3, iclass 34, count 0 2006.253.08:11:10.28#ibcon#read 3, iclass 34, count 0 2006.253.08:11:10.28#ibcon#about to read 4, iclass 34, count 0 2006.253.08:11:10.28#ibcon#read 4, iclass 34, count 0 2006.253.08:11:10.28#ibcon#about to read 5, iclass 34, count 0 2006.253.08:11:10.28#ibcon#read 5, iclass 34, count 0 2006.253.08:11:10.28#ibcon#about to read 6, iclass 34, count 0 2006.253.08:11:10.28#ibcon#read 6, iclass 34, count 0 2006.253.08:11:10.28#ibcon#end of sib2, iclass 34, count 0 2006.253.08:11:10.28#ibcon#*mode == 0, iclass 34, count 0 2006.253.08:11:10.28#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.253.08:11:10.28#ibcon#[25=USB\r\n] 2006.253.08:11:10.28#ibcon#*before write, iclass 34, count 0 2006.253.08:11:10.28#ibcon#enter sib2, iclass 34, count 0 2006.253.08:11:10.28#ibcon#flushed, iclass 34, count 0 2006.253.08:11:10.28#ibcon#about to write, iclass 34, count 0 2006.253.08:11:10.28#ibcon#wrote, iclass 34, count 0 2006.253.08:11:10.28#ibcon#about to read 3, iclass 34, count 0 2006.253.08:11:10.31#ibcon#read 3, iclass 34, count 0 2006.253.08:11:10.31#ibcon#about to read 4, iclass 34, count 0 2006.253.08:11:10.31#ibcon#read 4, iclass 34, count 0 2006.253.08:11:10.31#ibcon#about to read 5, iclass 34, count 0 2006.253.08:11:10.31#ibcon#read 5, iclass 34, count 0 2006.253.08:11:10.31#ibcon#about to read 6, iclass 34, count 0 2006.253.08:11:10.31#ibcon#read 6, iclass 34, count 0 2006.253.08:11:10.31#ibcon#end of sib2, iclass 34, count 0 2006.253.08:11:10.31#ibcon#*after write, iclass 34, count 0 2006.253.08:11:10.31#ibcon#*before return 0, iclass 34, count 0 2006.253.08:11:10.31#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.253.08:11:10.31#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.253.08:11:10.31#ibcon#about to clear, iclass 34 cls_cnt 0 2006.253.08:11:10.31#ibcon#cleared, iclass 34 cls_cnt 0 2006.253.08:11:10.31$vc4f8/valo=8,852.99 2006.253.08:11:10.31#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.253.08:11:10.31#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.253.08:11:10.31#ibcon#ireg 17 cls_cnt 0 2006.253.08:11:10.31#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.253.08:11:10.31#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.253.08:11:10.31#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.253.08:11:10.31#ibcon#enter wrdev, iclass 36, count 0 2006.253.08:11:10.31#ibcon#first serial, iclass 36, count 0 2006.253.08:11:10.31#ibcon#enter sib2, iclass 36, count 0 2006.253.08:11:10.31#ibcon#flushed, iclass 36, count 0 2006.253.08:11:10.31#ibcon#about to write, iclass 36, count 0 2006.253.08:11:10.31#ibcon#wrote, iclass 36, count 0 2006.253.08:11:10.31#ibcon#about to read 3, iclass 36, count 0 2006.253.08:11:10.33#ibcon#read 3, iclass 36, count 0 2006.253.08:11:10.33#ibcon#about to read 4, iclass 36, count 0 2006.253.08:11:10.33#ibcon#read 4, iclass 36, count 0 2006.253.08:11:10.33#ibcon#about to read 5, iclass 36, count 0 2006.253.08:11:10.33#ibcon#read 5, iclass 36, count 0 2006.253.08:11:10.33#ibcon#about to read 6, iclass 36, count 0 2006.253.08:11:10.33#ibcon#read 6, iclass 36, count 0 2006.253.08:11:10.33#ibcon#end of sib2, iclass 36, count 0 2006.253.08:11:10.33#ibcon#*mode == 0, iclass 36, count 0 2006.253.08:11:10.33#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.253.08:11:10.33#ibcon#[26=FRQ=08,852.99\r\n] 2006.253.08:11:10.33#ibcon#*before write, iclass 36, count 0 2006.253.08:11:10.33#ibcon#enter sib2, iclass 36, count 0 2006.253.08:11:10.33#ibcon#flushed, iclass 36, count 0 2006.253.08:11:10.33#ibcon#about to write, iclass 36, count 0 2006.253.08:11:10.33#ibcon#wrote, iclass 36, count 0 2006.253.08:11:10.33#ibcon#about to read 3, iclass 36, count 0 2006.253.08:11:10.37#ibcon#read 3, iclass 36, count 0 2006.253.08:11:10.37#ibcon#about to read 4, iclass 36, count 0 2006.253.08:11:10.37#ibcon#read 4, iclass 36, count 0 2006.253.08:11:10.37#ibcon#about to read 5, iclass 36, count 0 2006.253.08:11:10.37#ibcon#read 5, iclass 36, count 0 2006.253.08:11:10.37#ibcon#about to read 6, iclass 36, count 0 2006.253.08:11:10.37#ibcon#read 6, iclass 36, count 0 2006.253.08:11:10.37#ibcon#end of sib2, iclass 36, count 0 2006.253.08:11:10.37#ibcon#*after write, iclass 36, count 0 2006.253.08:11:10.37#ibcon#*before return 0, iclass 36, count 0 2006.253.08:11:10.37#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.253.08:11:10.37#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.253.08:11:10.37#ibcon#about to clear, iclass 36 cls_cnt 0 2006.253.08:11:10.37#ibcon#cleared, iclass 36 cls_cnt 0 2006.253.08:11:10.37$vc4f8/va=8,7 2006.253.08:11:10.37#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.253.08:11:10.37#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.253.08:11:10.37#ibcon#ireg 11 cls_cnt 2 2006.253.08:11:10.37#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.253.08:11:10.43#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.253.08:11:10.43#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.253.08:11:10.43#ibcon#enter wrdev, iclass 38, count 2 2006.253.08:11:10.43#ibcon#first serial, iclass 38, count 2 2006.253.08:11:10.43#ibcon#enter sib2, iclass 38, count 2 2006.253.08:11:10.43#ibcon#flushed, iclass 38, count 2 2006.253.08:11:10.43#ibcon#about to write, iclass 38, count 2 2006.253.08:11:10.43#ibcon#wrote, iclass 38, count 2 2006.253.08:11:10.43#ibcon#about to read 3, iclass 38, count 2 2006.253.08:11:10.45#ibcon#read 3, iclass 38, count 2 2006.253.08:11:10.45#ibcon#about to read 4, iclass 38, count 2 2006.253.08:11:10.45#ibcon#read 4, iclass 38, count 2 2006.253.08:11:10.45#ibcon#about to read 5, iclass 38, count 2 2006.253.08:11:10.45#ibcon#read 5, iclass 38, count 2 2006.253.08:11:10.45#ibcon#about to read 6, iclass 38, count 2 2006.253.08:11:10.45#ibcon#read 6, iclass 38, count 2 2006.253.08:11:10.45#ibcon#end of sib2, iclass 38, count 2 2006.253.08:11:10.45#ibcon#*mode == 0, iclass 38, count 2 2006.253.08:11:10.45#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.253.08:11:10.45#ibcon#[25=AT08-07\r\n] 2006.253.08:11:10.45#ibcon#*before write, iclass 38, count 2 2006.253.08:11:10.45#ibcon#enter sib2, iclass 38, count 2 2006.253.08:11:10.45#ibcon#flushed, iclass 38, count 2 2006.253.08:11:10.45#ibcon#about to write, iclass 38, count 2 2006.253.08:11:10.45#ibcon#wrote, iclass 38, count 2 2006.253.08:11:10.45#ibcon#about to read 3, iclass 38, count 2 2006.253.08:11:10.48#ibcon#read 3, iclass 38, count 2 2006.253.08:11:10.48#ibcon#about to read 4, iclass 38, count 2 2006.253.08:11:10.48#ibcon#read 4, iclass 38, count 2 2006.253.08:11:10.48#ibcon#about to read 5, iclass 38, count 2 2006.253.08:11:10.48#ibcon#read 5, iclass 38, count 2 2006.253.08:11:10.48#ibcon#about to read 6, iclass 38, count 2 2006.253.08:11:10.48#ibcon#read 6, iclass 38, count 2 2006.253.08:11:10.48#ibcon#end of sib2, iclass 38, count 2 2006.253.08:11:10.48#ibcon#*after write, iclass 38, count 2 2006.253.08:11:10.48#ibcon#*before return 0, iclass 38, count 2 2006.253.08:11:10.48#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.253.08:11:10.48#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.253.08:11:10.48#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.253.08:11:10.48#ibcon#ireg 7 cls_cnt 0 2006.253.08:11:10.48#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.253.08:11:10.60#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.253.08:11:10.60#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.253.08:11:10.60#ibcon#enter wrdev, iclass 38, count 0 2006.253.08:11:10.60#ibcon#first serial, iclass 38, count 0 2006.253.08:11:10.60#ibcon#enter sib2, iclass 38, count 0 2006.253.08:11:10.60#ibcon#flushed, iclass 38, count 0 2006.253.08:11:10.60#ibcon#about to write, iclass 38, count 0 2006.253.08:11:10.60#ibcon#wrote, iclass 38, count 0 2006.253.08:11:10.60#ibcon#about to read 3, iclass 38, count 0 2006.253.08:11:10.62#ibcon#read 3, iclass 38, count 0 2006.253.08:11:10.62#ibcon#about to read 4, iclass 38, count 0 2006.253.08:11:10.62#ibcon#read 4, iclass 38, count 0 2006.253.08:11:10.62#ibcon#about to read 5, iclass 38, count 0 2006.253.08:11:10.62#ibcon#read 5, iclass 38, count 0 2006.253.08:11:10.62#ibcon#about to read 6, iclass 38, count 0 2006.253.08:11:10.62#ibcon#read 6, iclass 38, count 0 2006.253.08:11:10.62#ibcon#end of sib2, iclass 38, count 0 2006.253.08:11:10.62#ibcon#*mode == 0, iclass 38, count 0 2006.253.08:11:10.62#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.253.08:11:10.62#ibcon#[25=USB\r\n] 2006.253.08:11:10.62#ibcon#*before write, iclass 38, count 0 2006.253.08:11:10.62#ibcon#enter sib2, iclass 38, count 0 2006.253.08:11:10.62#ibcon#flushed, iclass 38, count 0 2006.253.08:11:10.62#ibcon#about to write, iclass 38, count 0 2006.253.08:11:10.62#ibcon#wrote, iclass 38, count 0 2006.253.08:11:10.62#ibcon#about to read 3, iclass 38, count 0 2006.253.08:11:10.65#ibcon#read 3, iclass 38, count 0 2006.253.08:11:10.65#ibcon#about to read 4, iclass 38, count 0 2006.253.08:11:10.65#ibcon#read 4, iclass 38, count 0 2006.253.08:11:10.65#ibcon#about to read 5, iclass 38, count 0 2006.253.08:11:10.65#ibcon#read 5, iclass 38, count 0 2006.253.08:11:10.65#ibcon#about to read 6, iclass 38, count 0 2006.253.08:11:10.65#ibcon#read 6, iclass 38, count 0 2006.253.08:11:10.65#ibcon#end of sib2, iclass 38, count 0 2006.253.08:11:10.65#ibcon#*after write, iclass 38, count 0 2006.253.08:11:10.65#ibcon#*before return 0, iclass 38, count 0 2006.253.08:11:10.65#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.253.08:11:10.65#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.253.08:11:10.65#ibcon#about to clear, iclass 38 cls_cnt 0 2006.253.08:11:10.65#ibcon#cleared, iclass 38 cls_cnt 0 2006.253.08:11:10.65$vc4f8/vblo=1,632.99 2006.253.08:11:10.65#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.253.08:11:10.65#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.253.08:11:10.65#ibcon#ireg 17 cls_cnt 0 2006.253.08:11:10.65#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.253.08:11:10.65#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.253.08:11:10.65#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.253.08:11:10.65#ibcon#enter wrdev, iclass 40, count 0 2006.253.08:11:10.65#ibcon#first serial, iclass 40, count 0 2006.253.08:11:10.65#ibcon#enter sib2, iclass 40, count 0 2006.253.08:11:10.65#ibcon#flushed, iclass 40, count 0 2006.253.08:11:10.65#ibcon#about to write, iclass 40, count 0 2006.253.08:11:10.65#ibcon#wrote, iclass 40, count 0 2006.253.08:11:10.65#ibcon#about to read 3, iclass 40, count 0 2006.253.08:11:10.67#ibcon#read 3, iclass 40, count 0 2006.253.08:11:10.67#ibcon#about to read 4, iclass 40, count 0 2006.253.08:11:10.67#ibcon#read 4, iclass 40, count 0 2006.253.08:11:10.67#ibcon#about to read 5, iclass 40, count 0 2006.253.08:11:10.67#ibcon#read 5, iclass 40, count 0 2006.253.08:11:10.67#ibcon#about to read 6, iclass 40, count 0 2006.253.08:11:10.67#ibcon#read 6, iclass 40, count 0 2006.253.08:11:10.67#ibcon#end of sib2, iclass 40, count 0 2006.253.08:11:10.67#ibcon#*mode == 0, iclass 40, count 0 2006.253.08:11:10.67#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.253.08:11:10.67#ibcon#[28=FRQ=01,632.99\r\n] 2006.253.08:11:10.67#ibcon#*before write, iclass 40, count 0 2006.253.08:11:10.67#ibcon#enter sib2, iclass 40, count 0 2006.253.08:11:10.67#ibcon#flushed, iclass 40, count 0 2006.253.08:11:10.67#ibcon#about to write, iclass 40, count 0 2006.253.08:11:10.67#ibcon#wrote, iclass 40, count 0 2006.253.08:11:10.67#ibcon#about to read 3, iclass 40, count 0 2006.253.08:11:10.71#ibcon#read 3, iclass 40, count 0 2006.253.08:11:10.71#ibcon#about to read 4, iclass 40, count 0 2006.253.08:11:10.71#ibcon#read 4, iclass 40, count 0 2006.253.08:11:10.71#ibcon#about to read 5, iclass 40, count 0 2006.253.08:11:10.71#ibcon#read 5, iclass 40, count 0 2006.253.08:11:10.71#ibcon#about to read 6, iclass 40, count 0 2006.253.08:11:10.71#ibcon#read 6, iclass 40, count 0 2006.253.08:11:10.71#ibcon#end of sib2, iclass 40, count 0 2006.253.08:11:10.71#ibcon#*after write, iclass 40, count 0 2006.253.08:11:10.71#ibcon#*before return 0, iclass 40, count 0 2006.253.08:11:10.71#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.253.08:11:10.71#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.253.08:11:10.71#ibcon#about to clear, iclass 40 cls_cnt 0 2006.253.08:11:10.71#ibcon#cleared, iclass 40 cls_cnt 0 2006.253.08:11:10.71$vc4f8/vb=1,4 2006.253.08:11:10.71#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.253.08:11:10.71#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.253.08:11:10.71#ibcon#ireg 11 cls_cnt 2 2006.253.08:11:10.71#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.253.08:11:10.71#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.253.08:11:10.71#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.253.08:11:10.71#ibcon#enter wrdev, iclass 4, count 2 2006.253.08:11:10.71#ibcon#first serial, iclass 4, count 2 2006.253.08:11:10.71#ibcon#enter sib2, iclass 4, count 2 2006.253.08:11:10.71#ibcon#flushed, iclass 4, count 2 2006.253.08:11:10.71#ibcon#about to write, iclass 4, count 2 2006.253.08:11:10.71#ibcon#wrote, iclass 4, count 2 2006.253.08:11:10.71#ibcon#about to read 3, iclass 4, count 2 2006.253.08:11:10.73#ibcon#read 3, iclass 4, count 2 2006.253.08:11:10.73#ibcon#about to read 4, iclass 4, count 2 2006.253.08:11:10.73#ibcon#read 4, iclass 4, count 2 2006.253.08:11:10.73#ibcon#about to read 5, iclass 4, count 2 2006.253.08:11:10.73#ibcon#read 5, iclass 4, count 2 2006.253.08:11:10.73#ibcon#about to read 6, iclass 4, count 2 2006.253.08:11:10.73#ibcon#read 6, iclass 4, count 2 2006.253.08:11:10.73#ibcon#end of sib2, iclass 4, count 2 2006.253.08:11:10.73#ibcon#*mode == 0, iclass 4, count 2 2006.253.08:11:10.73#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.253.08:11:10.73#ibcon#[27=AT01-04\r\n] 2006.253.08:11:10.73#ibcon#*before write, iclass 4, count 2 2006.253.08:11:10.73#ibcon#enter sib2, iclass 4, count 2 2006.253.08:11:10.73#ibcon#flushed, iclass 4, count 2 2006.253.08:11:10.73#ibcon#about to write, iclass 4, count 2 2006.253.08:11:10.73#ibcon#wrote, iclass 4, count 2 2006.253.08:11:10.73#ibcon#about to read 3, iclass 4, count 2 2006.253.08:11:10.76#ibcon#read 3, iclass 4, count 2 2006.253.08:11:10.76#ibcon#about to read 4, iclass 4, count 2 2006.253.08:11:10.76#ibcon#read 4, iclass 4, count 2 2006.253.08:11:10.76#ibcon#about to read 5, iclass 4, count 2 2006.253.08:11:10.76#ibcon#read 5, iclass 4, count 2 2006.253.08:11:10.76#ibcon#about to read 6, iclass 4, count 2 2006.253.08:11:10.76#ibcon#read 6, iclass 4, count 2 2006.253.08:11:10.76#ibcon#end of sib2, iclass 4, count 2 2006.253.08:11:10.76#ibcon#*after write, iclass 4, count 2 2006.253.08:11:10.76#ibcon#*before return 0, iclass 4, count 2 2006.253.08:11:10.76#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.253.08:11:10.76#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.253.08:11:10.76#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.253.08:11:10.76#ibcon#ireg 7 cls_cnt 0 2006.253.08:11:10.76#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.253.08:11:10.88#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.253.08:11:10.88#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.253.08:11:10.88#ibcon#enter wrdev, iclass 4, count 0 2006.253.08:11:10.88#ibcon#first serial, iclass 4, count 0 2006.253.08:11:10.88#ibcon#enter sib2, iclass 4, count 0 2006.253.08:11:10.88#ibcon#flushed, iclass 4, count 0 2006.253.08:11:10.88#ibcon#about to write, iclass 4, count 0 2006.253.08:11:10.88#ibcon#wrote, iclass 4, count 0 2006.253.08:11:10.88#ibcon#about to read 3, iclass 4, count 0 2006.253.08:11:10.90#ibcon#read 3, iclass 4, count 0 2006.253.08:11:10.90#ibcon#about to read 4, iclass 4, count 0 2006.253.08:11:10.90#ibcon#read 4, iclass 4, count 0 2006.253.08:11:10.90#ibcon#about to read 5, iclass 4, count 0 2006.253.08:11:10.90#ibcon#read 5, iclass 4, count 0 2006.253.08:11:10.90#ibcon#about to read 6, iclass 4, count 0 2006.253.08:11:10.90#ibcon#read 6, iclass 4, count 0 2006.253.08:11:10.90#ibcon#end of sib2, iclass 4, count 0 2006.253.08:11:10.90#ibcon#*mode == 0, iclass 4, count 0 2006.253.08:11:10.90#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.253.08:11:10.90#ibcon#[27=USB\r\n] 2006.253.08:11:10.90#ibcon#*before write, iclass 4, count 0 2006.253.08:11:10.90#ibcon#enter sib2, iclass 4, count 0 2006.253.08:11:10.90#ibcon#flushed, iclass 4, count 0 2006.253.08:11:10.90#ibcon#about to write, iclass 4, count 0 2006.253.08:11:10.90#ibcon#wrote, iclass 4, count 0 2006.253.08:11:10.90#ibcon#about to read 3, iclass 4, count 0 2006.253.08:11:10.93#ibcon#read 3, iclass 4, count 0 2006.253.08:11:10.93#ibcon#about to read 4, iclass 4, count 0 2006.253.08:11:10.93#ibcon#read 4, iclass 4, count 0 2006.253.08:11:10.93#ibcon#about to read 5, iclass 4, count 0 2006.253.08:11:10.93#ibcon#read 5, iclass 4, count 0 2006.253.08:11:10.93#ibcon#about to read 6, iclass 4, count 0 2006.253.08:11:10.93#ibcon#read 6, iclass 4, count 0 2006.253.08:11:10.93#ibcon#end of sib2, iclass 4, count 0 2006.253.08:11:10.93#ibcon#*after write, iclass 4, count 0 2006.253.08:11:10.93#ibcon#*before return 0, iclass 4, count 0 2006.253.08:11:10.93#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.253.08:11:10.93#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.253.08:11:10.93#ibcon#about to clear, iclass 4 cls_cnt 0 2006.253.08:11:10.93#ibcon#cleared, iclass 4 cls_cnt 0 2006.253.08:11:10.93$vc4f8/vblo=2,640.99 2006.253.08:11:10.93#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.253.08:11:10.93#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.253.08:11:10.93#ibcon#ireg 17 cls_cnt 0 2006.253.08:11:10.93#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.253.08:11:10.93#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.253.08:11:10.93#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.253.08:11:10.93#ibcon#enter wrdev, iclass 6, count 0 2006.253.08:11:10.93#ibcon#first serial, iclass 6, count 0 2006.253.08:11:10.93#ibcon#enter sib2, iclass 6, count 0 2006.253.08:11:10.93#ibcon#flushed, iclass 6, count 0 2006.253.08:11:10.93#ibcon#about to write, iclass 6, count 0 2006.253.08:11:10.93#ibcon#wrote, iclass 6, count 0 2006.253.08:11:10.93#ibcon#about to read 3, iclass 6, count 0 2006.253.08:11:10.95#ibcon#read 3, iclass 6, count 0 2006.253.08:11:10.95#ibcon#about to read 4, iclass 6, count 0 2006.253.08:11:10.95#ibcon#read 4, iclass 6, count 0 2006.253.08:11:10.95#ibcon#about to read 5, iclass 6, count 0 2006.253.08:11:10.95#ibcon#read 5, iclass 6, count 0 2006.253.08:11:10.95#ibcon#about to read 6, iclass 6, count 0 2006.253.08:11:10.95#ibcon#read 6, iclass 6, count 0 2006.253.08:11:10.95#ibcon#end of sib2, iclass 6, count 0 2006.253.08:11:10.95#ibcon#*mode == 0, iclass 6, count 0 2006.253.08:11:10.95#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.253.08:11:10.95#ibcon#[28=FRQ=02,640.99\r\n] 2006.253.08:11:10.95#ibcon#*before write, iclass 6, count 0 2006.253.08:11:10.95#ibcon#enter sib2, iclass 6, count 0 2006.253.08:11:10.95#ibcon#flushed, iclass 6, count 0 2006.253.08:11:10.95#ibcon#about to write, iclass 6, count 0 2006.253.08:11:10.95#ibcon#wrote, iclass 6, count 0 2006.253.08:11:10.95#ibcon#about to read 3, iclass 6, count 0 2006.253.08:11:10.99#ibcon#read 3, iclass 6, count 0 2006.253.08:11:10.99#ibcon#about to read 4, iclass 6, count 0 2006.253.08:11:10.99#ibcon#read 4, iclass 6, count 0 2006.253.08:11:10.99#ibcon#about to read 5, iclass 6, count 0 2006.253.08:11:10.99#ibcon#read 5, iclass 6, count 0 2006.253.08:11:10.99#ibcon#about to read 6, iclass 6, count 0 2006.253.08:11:10.99#ibcon#read 6, iclass 6, count 0 2006.253.08:11:10.99#ibcon#end of sib2, iclass 6, count 0 2006.253.08:11:10.99#ibcon#*after write, iclass 6, count 0 2006.253.08:11:10.99#ibcon#*before return 0, iclass 6, count 0 2006.253.08:11:10.99#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.253.08:11:10.99#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.253.08:11:10.99#ibcon#about to clear, iclass 6 cls_cnt 0 2006.253.08:11:10.99#ibcon#cleared, iclass 6 cls_cnt 0 2006.253.08:11:10.99$vc4f8/vb=2,5 2006.253.08:11:10.99#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.253.08:11:10.99#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.253.08:11:10.99#ibcon#ireg 11 cls_cnt 2 2006.253.08:11:10.99#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.253.08:11:11.05#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.253.08:11:11.05#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.253.08:11:11.05#ibcon#enter wrdev, iclass 10, count 2 2006.253.08:11:11.05#ibcon#first serial, iclass 10, count 2 2006.253.08:11:11.05#ibcon#enter sib2, iclass 10, count 2 2006.253.08:11:11.05#ibcon#flushed, iclass 10, count 2 2006.253.08:11:11.05#ibcon#about to write, iclass 10, count 2 2006.253.08:11:11.05#ibcon#wrote, iclass 10, count 2 2006.253.08:11:11.05#ibcon#about to read 3, iclass 10, count 2 2006.253.08:11:11.07#ibcon#read 3, iclass 10, count 2 2006.253.08:11:11.07#ibcon#about to read 4, iclass 10, count 2 2006.253.08:11:11.07#ibcon#read 4, iclass 10, count 2 2006.253.08:11:11.07#ibcon#about to read 5, iclass 10, count 2 2006.253.08:11:11.07#ibcon#read 5, iclass 10, count 2 2006.253.08:11:11.07#ibcon#about to read 6, iclass 10, count 2 2006.253.08:11:11.07#ibcon#read 6, iclass 10, count 2 2006.253.08:11:11.07#ibcon#end of sib2, iclass 10, count 2 2006.253.08:11:11.07#ibcon#*mode == 0, iclass 10, count 2 2006.253.08:11:11.07#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.253.08:11:11.07#ibcon#[27=AT02-05\r\n] 2006.253.08:11:11.07#ibcon#*before write, iclass 10, count 2 2006.253.08:11:11.07#ibcon#enter sib2, iclass 10, count 2 2006.253.08:11:11.07#ibcon#flushed, iclass 10, count 2 2006.253.08:11:11.07#ibcon#about to write, iclass 10, count 2 2006.253.08:11:11.07#ibcon#wrote, iclass 10, count 2 2006.253.08:11:11.07#ibcon#about to read 3, iclass 10, count 2 2006.253.08:11:11.10#ibcon#read 3, iclass 10, count 2 2006.253.08:11:11.10#ibcon#about to read 4, iclass 10, count 2 2006.253.08:11:11.10#ibcon#read 4, iclass 10, count 2 2006.253.08:11:11.10#ibcon#about to read 5, iclass 10, count 2 2006.253.08:11:11.10#ibcon#read 5, iclass 10, count 2 2006.253.08:11:11.10#ibcon#about to read 6, iclass 10, count 2 2006.253.08:11:11.10#ibcon#read 6, iclass 10, count 2 2006.253.08:11:11.10#ibcon#end of sib2, iclass 10, count 2 2006.253.08:11:11.10#ibcon#*after write, iclass 10, count 2 2006.253.08:11:11.10#ibcon#*before return 0, iclass 10, count 2 2006.253.08:11:11.10#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.253.08:11:11.10#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.253.08:11:11.10#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.253.08:11:11.10#ibcon#ireg 7 cls_cnt 0 2006.253.08:11:11.10#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.253.08:11:11.22#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.253.08:11:11.22#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.253.08:11:11.22#ibcon#enter wrdev, iclass 10, count 0 2006.253.08:11:11.22#ibcon#first serial, iclass 10, count 0 2006.253.08:11:11.22#ibcon#enter sib2, iclass 10, count 0 2006.253.08:11:11.22#ibcon#flushed, iclass 10, count 0 2006.253.08:11:11.22#ibcon#about to write, iclass 10, count 0 2006.253.08:11:11.22#ibcon#wrote, iclass 10, count 0 2006.253.08:11:11.22#ibcon#about to read 3, iclass 10, count 0 2006.253.08:11:11.24#ibcon#read 3, iclass 10, count 0 2006.253.08:11:11.24#ibcon#about to read 4, iclass 10, count 0 2006.253.08:11:11.24#ibcon#read 4, iclass 10, count 0 2006.253.08:11:11.24#ibcon#about to read 5, iclass 10, count 0 2006.253.08:11:11.24#ibcon#read 5, iclass 10, count 0 2006.253.08:11:11.24#ibcon#about to read 6, iclass 10, count 0 2006.253.08:11:11.24#ibcon#read 6, iclass 10, count 0 2006.253.08:11:11.24#ibcon#end of sib2, iclass 10, count 0 2006.253.08:11:11.24#ibcon#*mode == 0, iclass 10, count 0 2006.253.08:11:11.24#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.253.08:11:11.24#ibcon#[27=USB\r\n] 2006.253.08:11:11.24#ibcon#*before write, iclass 10, count 0 2006.253.08:11:11.24#ibcon#enter sib2, iclass 10, count 0 2006.253.08:11:11.24#ibcon#flushed, iclass 10, count 0 2006.253.08:11:11.24#ibcon#about to write, iclass 10, count 0 2006.253.08:11:11.24#ibcon#wrote, iclass 10, count 0 2006.253.08:11:11.24#ibcon#about to read 3, iclass 10, count 0 2006.253.08:11:11.27#ibcon#read 3, iclass 10, count 0 2006.253.08:11:11.27#ibcon#about to read 4, iclass 10, count 0 2006.253.08:11:11.27#ibcon#read 4, iclass 10, count 0 2006.253.08:11:11.27#ibcon#about to read 5, iclass 10, count 0 2006.253.08:11:11.27#ibcon#read 5, iclass 10, count 0 2006.253.08:11:11.27#ibcon#about to read 6, iclass 10, count 0 2006.253.08:11:11.27#ibcon#read 6, iclass 10, count 0 2006.253.08:11:11.27#ibcon#end of sib2, iclass 10, count 0 2006.253.08:11:11.27#ibcon#*after write, iclass 10, count 0 2006.253.08:11:11.27#ibcon#*before return 0, iclass 10, count 0 2006.253.08:11:11.27#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.253.08:11:11.27#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.253.08:11:11.27#ibcon#about to clear, iclass 10 cls_cnt 0 2006.253.08:11:11.27#ibcon#cleared, iclass 10 cls_cnt 0 2006.253.08:11:11.27$vc4f8/vblo=3,656.99 2006.253.08:11:11.27#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.253.08:11:11.27#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.253.08:11:11.27#ibcon#ireg 17 cls_cnt 0 2006.253.08:11:11.27#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.253.08:11:11.27#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.253.08:11:11.27#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.253.08:11:11.27#ibcon#enter wrdev, iclass 12, count 0 2006.253.08:11:11.27#ibcon#first serial, iclass 12, count 0 2006.253.08:11:11.27#ibcon#enter sib2, iclass 12, count 0 2006.253.08:11:11.27#ibcon#flushed, iclass 12, count 0 2006.253.08:11:11.27#ibcon#about to write, iclass 12, count 0 2006.253.08:11:11.27#ibcon#wrote, iclass 12, count 0 2006.253.08:11:11.27#ibcon#about to read 3, iclass 12, count 0 2006.253.08:11:11.29#ibcon#read 3, iclass 12, count 0 2006.253.08:11:11.29#ibcon#about to read 4, iclass 12, count 0 2006.253.08:11:11.29#ibcon#read 4, iclass 12, count 0 2006.253.08:11:11.29#ibcon#about to read 5, iclass 12, count 0 2006.253.08:11:11.29#ibcon#read 5, iclass 12, count 0 2006.253.08:11:11.29#ibcon#about to read 6, iclass 12, count 0 2006.253.08:11:11.29#ibcon#read 6, iclass 12, count 0 2006.253.08:11:11.29#ibcon#end of sib2, iclass 12, count 0 2006.253.08:11:11.29#ibcon#*mode == 0, iclass 12, count 0 2006.253.08:11:11.29#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.253.08:11:11.29#ibcon#[28=FRQ=03,656.99\r\n] 2006.253.08:11:11.29#ibcon#*before write, iclass 12, count 0 2006.253.08:11:11.29#ibcon#enter sib2, iclass 12, count 0 2006.253.08:11:11.29#ibcon#flushed, iclass 12, count 0 2006.253.08:11:11.29#ibcon#about to write, iclass 12, count 0 2006.253.08:11:11.29#ibcon#wrote, iclass 12, count 0 2006.253.08:11:11.29#ibcon#about to read 3, iclass 12, count 0 2006.253.08:11:11.33#ibcon#read 3, iclass 12, count 0 2006.253.08:11:11.33#ibcon#about to read 4, iclass 12, count 0 2006.253.08:11:11.33#ibcon#read 4, iclass 12, count 0 2006.253.08:11:11.33#ibcon#about to read 5, iclass 12, count 0 2006.253.08:11:11.33#ibcon#read 5, iclass 12, count 0 2006.253.08:11:11.33#ibcon#about to read 6, iclass 12, count 0 2006.253.08:11:11.33#ibcon#read 6, iclass 12, count 0 2006.253.08:11:11.33#ibcon#end of sib2, iclass 12, count 0 2006.253.08:11:11.33#ibcon#*after write, iclass 12, count 0 2006.253.08:11:11.33#ibcon#*before return 0, iclass 12, count 0 2006.253.08:11:11.33#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.253.08:11:11.33#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.253.08:11:11.33#ibcon#about to clear, iclass 12 cls_cnt 0 2006.253.08:11:11.33#ibcon#cleared, iclass 12 cls_cnt 0 2006.253.08:11:11.33$vc4f8/vb=3,4 2006.253.08:11:11.33#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.253.08:11:11.33#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.253.08:11:11.33#ibcon#ireg 11 cls_cnt 2 2006.253.08:11:11.33#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.253.08:11:11.39#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.253.08:11:11.39#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.253.08:11:11.39#ibcon#enter wrdev, iclass 14, count 2 2006.253.08:11:11.39#ibcon#first serial, iclass 14, count 2 2006.253.08:11:11.39#ibcon#enter sib2, iclass 14, count 2 2006.253.08:11:11.39#ibcon#flushed, iclass 14, count 2 2006.253.08:11:11.39#ibcon#about to write, iclass 14, count 2 2006.253.08:11:11.39#ibcon#wrote, iclass 14, count 2 2006.253.08:11:11.39#ibcon#about to read 3, iclass 14, count 2 2006.253.08:11:11.41#ibcon#read 3, iclass 14, count 2 2006.253.08:11:11.41#ibcon#about to read 4, iclass 14, count 2 2006.253.08:11:11.41#ibcon#read 4, iclass 14, count 2 2006.253.08:11:11.41#ibcon#about to read 5, iclass 14, count 2 2006.253.08:11:11.41#ibcon#read 5, iclass 14, count 2 2006.253.08:11:11.41#ibcon#about to read 6, iclass 14, count 2 2006.253.08:11:11.41#ibcon#read 6, iclass 14, count 2 2006.253.08:11:11.41#ibcon#end of sib2, iclass 14, count 2 2006.253.08:11:11.41#ibcon#*mode == 0, iclass 14, count 2 2006.253.08:11:11.41#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.253.08:11:11.41#ibcon#[27=AT03-04\r\n] 2006.253.08:11:11.41#ibcon#*before write, iclass 14, count 2 2006.253.08:11:11.41#ibcon#enter sib2, iclass 14, count 2 2006.253.08:11:11.41#ibcon#flushed, iclass 14, count 2 2006.253.08:11:11.41#ibcon#about to write, iclass 14, count 2 2006.253.08:11:11.41#ibcon#wrote, iclass 14, count 2 2006.253.08:11:11.41#ibcon#about to read 3, iclass 14, count 2 2006.253.08:11:11.44#ibcon#read 3, iclass 14, count 2 2006.253.08:11:11.44#ibcon#about to read 4, iclass 14, count 2 2006.253.08:11:11.44#ibcon#read 4, iclass 14, count 2 2006.253.08:11:11.44#ibcon#about to read 5, iclass 14, count 2 2006.253.08:11:11.44#ibcon#read 5, iclass 14, count 2 2006.253.08:11:11.44#ibcon#about to read 6, iclass 14, count 2 2006.253.08:11:11.44#ibcon#read 6, iclass 14, count 2 2006.253.08:11:11.44#ibcon#end of sib2, iclass 14, count 2 2006.253.08:11:11.44#ibcon#*after write, iclass 14, count 2 2006.253.08:11:11.44#ibcon#*before return 0, iclass 14, count 2 2006.253.08:11:11.44#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.253.08:11:11.44#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.253.08:11:11.44#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.253.08:11:11.44#ibcon#ireg 7 cls_cnt 0 2006.253.08:11:11.44#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.253.08:11:11.56#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.253.08:11:11.56#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.253.08:11:11.56#ibcon#enter wrdev, iclass 14, count 0 2006.253.08:11:11.56#ibcon#first serial, iclass 14, count 0 2006.253.08:11:11.56#ibcon#enter sib2, iclass 14, count 0 2006.253.08:11:11.56#ibcon#flushed, iclass 14, count 0 2006.253.08:11:11.56#ibcon#about to write, iclass 14, count 0 2006.253.08:11:11.56#ibcon#wrote, iclass 14, count 0 2006.253.08:11:11.56#ibcon#about to read 3, iclass 14, count 0 2006.253.08:11:11.58#ibcon#read 3, iclass 14, count 0 2006.253.08:11:11.58#ibcon#about to read 4, iclass 14, count 0 2006.253.08:11:11.58#ibcon#read 4, iclass 14, count 0 2006.253.08:11:11.58#ibcon#about to read 5, iclass 14, count 0 2006.253.08:11:11.58#ibcon#read 5, iclass 14, count 0 2006.253.08:11:11.58#ibcon#about to read 6, iclass 14, count 0 2006.253.08:11:11.58#ibcon#read 6, iclass 14, count 0 2006.253.08:11:11.58#ibcon#end of sib2, iclass 14, count 0 2006.253.08:11:11.58#ibcon#*mode == 0, iclass 14, count 0 2006.253.08:11:11.58#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.253.08:11:11.58#ibcon#[27=USB\r\n] 2006.253.08:11:11.58#ibcon#*before write, iclass 14, count 0 2006.253.08:11:11.58#ibcon#enter sib2, iclass 14, count 0 2006.253.08:11:11.58#ibcon#flushed, iclass 14, count 0 2006.253.08:11:11.58#ibcon#about to write, iclass 14, count 0 2006.253.08:11:11.58#ibcon#wrote, iclass 14, count 0 2006.253.08:11:11.58#ibcon#about to read 3, iclass 14, count 0 2006.253.08:11:11.61#ibcon#read 3, iclass 14, count 0 2006.253.08:11:11.61#ibcon#about to read 4, iclass 14, count 0 2006.253.08:11:11.61#ibcon#read 4, iclass 14, count 0 2006.253.08:11:11.61#ibcon#about to read 5, iclass 14, count 0 2006.253.08:11:11.61#ibcon#read 5, iclass 14, count 0 2006.253.08:11:11.61#ibcon#about to read 6, iclass 14, count 0 2006.253.08:11:11.61#ibcon#read 6, iclass 14, count 0 2006.253.08:11:11.61#ibcon#end of sib2, iclass 14, count 0 2006.253.08:11:11.61#ibcon#*after write, iclass 14, count 0 2006.253.08:11:11.61#ibcon#*before return 0, iclass 14, count 0 2006.253.08:11:11.61#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.253.08:11:11.61#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.253.08:11:11.61#ibcon#about to clear, iclass 14 cls_cnt 0 2006.253.08:11:11.61#ibcon#cleared, iclass 14 cls_cnt 0 2006.253.08:11:11.61$vc4f8/vblo=4,712.99 2006.253.08:11:11.61#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.253.08:11:11.61#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.253.08:11:11.61#ibcon#ireg 17 cls_cnt 0 2006.253.08:11:11.61#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.253.08:11:11.61#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.253.08:11:11.61#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.253.08:11:11.61#ibcon#enter wrdev, iclass 16, count 0 2006.253.08:11:11.61#ibcon#first serial, iclass 16, count 0 2006.253.08:11:11.61#ibcon#enter sib2, iclass 16, count 0 2006.253.08:11:11.61#ibcon#flushed, iclass 16, count 0 2006.253.08:11:11.61#ibcon#about to write, iclass 16, count 0 2006.253.08:11:11.61#ibcon#wrote, iclass 16, count 0 2006.253.08:11:11.61#ibcon#about to read 3, iclass 16, count 0 2006.253.08:11:11.63#ibcon#read 3, iclass 16, count 0 2006.253.08:11:11.63#ibcon#about to read 4, iclass 16, count 0 2006.253.08:11:11.63#ibcon#read 4, iclass 16, count 0 2006.253.08:11:11.63#ibcon#about to read 5, iclass 16, count 0 2006.253.08:11:11.63#ibcon#read 5, iclass 16, count 0 2006.253.08:11:11.63#ibcon#about to read 6, iclass 16, count 0 2006.253.08:11:11.63#ibcon#read 6, iclass 16, count 0 2006.253.08:11:11.63#ibcon#end of sib2, iclass 16, count 0 2006.253.08:11:11.63#ibcon#*mode == 0, iclass 16, count 0 2006.253.08:11:11.63#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.253.08:11:11.63#ibcon#[28=FRQ=04,712.99\r\n] 2006.253.08:11:11.63#ibcon#*before write, iclass 16, count 0 2006.253.08:11:11.63#ibcon#enter sib2, iclass 16, count 0 2006.253.08:11:11.63#ibcon#flushed, iclass 16, count 0 2006.253.08:11:11.63#ibcon#about to write, iclass 16, count 0 2006.253.08:11:11.63#ibcon#wrote, iclass 16, count 0 2006.253.08:11:11.63#ibcon#about to read 3, iclass 16, count 0 2006.253.08:11:11.67#ibcon#read 3, iclass 16, count 0 2006.253.08:11:11.67#ibcon#about to read 4, iclass 16, count 0 2006.253.08:11:11.67#ibcon#read 4, iclass 16, count 0 2006.253.08:11:11.67#ibcon#about to read 5, iclass 16, count 0 2006.253.08:11:11.67#ibcon#read 5, iclass 16, count 0 2006.253.08:11:11.67#ibcon#about to read 6, iclass 16, count 0 2006.253.08:11:11.67#ibcon#read 6, iclass 16, count 0 2006.253.08:11:11.67#ibcon#end of sib2, iclass 16, count 0 2006.253.08:11:11.67#ibcon#*after write, iclass 16, count 0 2006.253.08:11:11.67#ibcon#*before return 0, iclass 16, count 0 2006.253.08:11:11.67#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.253.08:11:11.67#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.253.08:11:11.67#ibcon#about to clear, iclass 16 cls_cnt 0 2006.253.08:11:11.67#ibcon#cleared, iclass 16 cls_cnt 0 2006.253.08:11:11.67$vc4f8/vb=4,4 2006.253.08:11:11.67#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.253.08:11:11.67#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.253.08:11:11.67#ibcon#ireg 11 cls_cnt 2 2006.253.08:11:11.67#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.253.08:11:11.73#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.253.08:11:11.73#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.253.08:11:11.73#ibcon#enter wrdev, iclass 18, count 2 2006.253.08:11:11.73#ibcon#first serial, iclass 18, count 2 2006.253.08:11:11.73#ibcon#enter sib2, iclass 18, count 2 2006.253.08:11:11.73#ibcon#flushed, iclass 18, count 2 2006.253.08:11:11.73#ibcon#about to write, iclass 18, count 2 2006.253.08:11:11.73#ibcon#wrote, iclass 18, count 2 2006.253.08:11:11.73#ibcon#about to read 3, iclass 18, count 2 2006.253.08:11:11.75#ibcon#read 3, iclass 18, count 2 2006.253.08:11:11.75#ibcon#about to read 4, iclass 18, count 2 2006.253.08:11:11.75#ibcon#read 4, iclass 18, count 2 2006.253.08:11:11.75#ibcon#about to read 5, iclass 18, count 2 2006.253.08:11:11.75#ibcon#read 5, iclass 18, count 2 2006.253.08:11:11.75#ibcon#about to read 6, iclass 18, count 2 2006.253.08:11:11.75#ibcon#read 6, iclass 18, count 2 2006.253.08:11:11.75#ibcon#end of sib2, iclass 18, count 2 2006.253.08:11:11.75#ibcon#*mode == 0, iclass 18, count 2 2006.253.08:11:11.75#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.253.08:11:11.75#ibcon#[27=AT04-04\r\n] 2006.253.08:11:11.75#ibcon#*before write, iclass 18, count 2 2006.253.08:11:11.75#ibcon#enter sib2, iclass 18, count 2 2006.253.08:11:11.75#ibcon#flushed, iclass 18, count 2 2006.253.08:11:11.75#ibcon#about to write, iclass 18, count 2 2006.253.08:11:11.75#ibcon#wrote, iclass 18, count 2 2006.253.08:11:11.75#ibcon#about to read 3, iclass 18, count 2 2006.253.08:11:11.78#ibcon#read 3, iclass 18, count 2 2006.253.08:11:11.78#ibcon#about to read 4, iclass 18, count 2 2006.253.08:11:11.78#ibcon#read 4, iclass 18, count 2 2006.253.08:11:11.78#ibcon#about to read 5, iclass 18, count 2 2006.253.08:11:11.78#ibcon#read 5, iclass 18, count 2 2006.253.08:11:11.78#ibcon#about to read 6, iclass 18, count 2 2006.253.08:11:11.78#ibcon#read 6, iclass 18, count 2 2006.253.08:11:11.78#ibcon#end of sib2, iclass 18, count 2 2006.253.08:11:11.78#ibcon#*after write, iclass 18, count 2 2006.253.08:11:11.78#ibcon#*before return 0, iclass 18, count 2 2006.253.08:11:11.78#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.253.08:11:11.78#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.253.08:11:11.78#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.253.08:11:11.78#ibcon#ireg 7 cls_cnt 0 2006.253.08:11:11.78#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.253.08:11:11.90#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.253.08:11:11.90#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.253.08:11:11.90#ibcon#enter wrdev, iclass 18, count 0 2006.253.08:11:11.90#ibcon#first serial, iclass 18, count 0 2006.253.08:11:11.90#ibcon#enter sib2, iclass 18, count 0 2006.253.08:11:11.90#ibcon#flushed, iclass 18, count 0 2006.253.08:11:11.90#ibcon#about to write, iclass 18, count 0 2006.253.08:11:11.90#ibcon#wrote, iclass 18, count 0 2006.253.08:11:11.90#ibcon#about to read 3, iclass 18, count 0 2006.253.08:11:11.92#ibcon#read 3, iclass 18, count 0 2006.253.08:11:11.92#ibcon#about to read 4, iclass 18, count 0 2006.253.08:11:11.92#ibcon#read 4, iclass 18, count 0 2006.253.08:11:11.92#ibcon#about to read 5, iclass 18, count 0 2006.253.08:11:11.92#ibcon#read 5, iclass 18, count 0 2006.253.08:11:11.92#ibcon#about to read 6, iclass 18, count 0 2006.253.08:11:11.92#ibcon#read 6, iclass 18, count 0 2006.253.08:11:11.92#ibcon#end of sib2, iclass 18, count 0 2006.253.08:11:11.92#ibcon#*mode == 0, iclass 18, count 0 2006.253.08:11:11.92#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.253.08:11:11.92#ibcon#[27=USB\r\n] 2006.253.08:11:11.92#ibcon#*before write, iclass 18, count 0 2006.253.08:11:11.92#ibcon#enter sib2, iclass 18, count 0 2006.253.08:11:11.92#ibcon#flushed, iclass 18, count 0 2006.253.08:11:11.92#ibcon#about to write, iclass 18, count 0 2006.253.08:11:11.92#ibcon#wrote, iclass 18, count 0 2006.253.08:11:11.92#ibcon#about to read 3, iclass 18, count 0 2006.253.08:11:11.95#ibcon#read 3, iclass 18, count 0 2006.253.08:11:11.95#ibcon#about to read 4, iclass 18, count 0 2006.253.08:11:11.95#ibcon#read 4, iclass 18, count 0 2006.253.08:11:11.95#ibcon#about to read 5, iclass 18, count 0 2006.253.08:11:11.95#ibcon#read 5, iclass 18, count 0 2006.253.08:11:11.95#ibcon#about to read 6, iclass 18, count 0 2006.253.08:11:11.95#ibcon#read 6, iclass 18, count 0 2006.253.08:11:11.95#ibcon#end of sib2, iclass 18, count 0 2006.253.08:11:11.95#ibcon#*after write, iclass 18, count 0 2006.253.08:11:11.95#ibcon#*before return 0, iclass 18, count 0 2006.253.08:11:11.95#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.253.08:11:11.95#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.253.08:11:11.95#ibcon#about to clear, iclass 18 cls_cnt 0 2006.253.08:11:11.95#ibcon#cleared, iclass 18 cls_cnt 0 2006.253.08:11:11.95$vc4f8/vblo=5,744.99 2006.253.08:11:11.95#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.253.08:11:11.95#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.253.08:11:11.95#ibcon#ireg 17 cls_cnt 0 2006.253.08:11:11.95#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.253.08:11:11.95#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.253.08:11:11.95#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.253.08:11:11.95#ibcon#enter wrdev, iclass 20, count 0 2006.253.08:11:11.95#ibcon#first serial, iclass 20, count 0 2006.253.08:11:11.95#ibcon#enter sib2, iclass 20, count 0 2006.253.08:11:11.95#ibcon#flushed, iclass 20, count 0 2006.253.08:11:11.95#ibcon#about to write, iclass 20, count 0 2006.253.08:11:11.95#ibcon#wrote, iclass 20, count 0 2006.253.08:11:11.95#ibcon#about to read 3, iclass 20, count 0 2006.253.08:11:11.97#ibcon#read 3, iclass 20, count 0 2006.253.08:11:11.97#ibcon#about to read 4, iclass 20, count 0 2006.253.08:11:11.97#ibcon#read 4, iclass 20, count 0 2006.253.08:11:11.97#ibcon#about to read 5, iclass 20, count 0 2006.253.08:11:11.97#ibcon#read 5, iclass 20, count 0 2006.253.08:11:11.97#ibcon#about to read 6, iclass 20, count 0 2006.253.08:11:11.97#ibcon#read 6, iclass 20, count 0 2006.253.08:11:11.97#ibcon#end of sib2, iclass 20, count 0 2006.253.08:11:11.97#ibcon#*mode == 0, iclass 20, count 0 2006.253.08:11:11.97#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.253.08:11:11.97#ibcon#[28=FRQ=05,744.99\r\n] 2006.253.08:11:11.97#ibcon#*before write, iclass 20, count 0 2006.253.08:11:11.97#ibcon#enter sib2, iclass 20, count 0 2006.253.08:11:11.97#ibcon#flushed, iclass 20, count 0 2006.253.08:11:11.97#ibcon#about to write, iclass 20, count 0 2006.253.08:11:11.97#ibcon#wrote, iclass 20, count 0 2006.253.08:11:11.97#ibcon#about to read 3, iclass 20, count 0 2006.253.08:11:12.01#ibcon#read 3, iclass 20, count 0 2006.253.08:11:12.01#ibcon#about to read 4, iclass 20, count 0 2006.253.08:11:12.01#ibcon#read 4, iclass 20, count 0 2006.253.08:11:12.01#ibcon#about to read 5, iclass 20, count 0 2006.253.08:11:12.01#ibcon#read 5, iclass 20, count 0 2006.253.08:11:12.01#ibcon#about to read 6, iclass 20, count 0 2006.253.08:11:12.01#ibcon#read 6, iclass 20, count 0 2006.253.08:11:12.01#ibcon#end of sib2, iclass 20, count 0 2006.253.08:11:12.01#ibcon#*after write, iclass 20, count 0 2006.253.08:11:12.01#ibcon#*before return 0, iclass 20, count 0 2006.253.08:11:12.01#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.253.08:11:12.01#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.253.08:11:12.01#ibcon#about to clear, iclass 20 cls_cnt 0 2006.253.08:11:12.01#ibcon#cleared, iclass 20 cls_cnt 0 2006.253.08:11:12.01$vc4f8/vb=5,4 2006.253.08:11:12.01#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.253.08:11:12.01#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.253.08:11:12.01#ibcon#ireg 11 cls_cnt 2 2006.253.08:11:12.01#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.253.08:11:12.07#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.253.08:11:12.07#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.253.08:11:12.07#ibcon#enter wrdev, iclass 22, count 2 2006.253.08:11:12.07#ibcon#first serial, iclass 22, count 2 2006.253.08:11:12.07#ibcon#enter sib2, iclass 22, count 2 2006.253.08:11:12.07#ibcon#flushed, iclass 22, count 2 2006.253.08:11:12.07#ibcon#about to write, iclass 22, count 2 2006.253.08:11:12.07#ibcon#wrote, iclass 22, count 2 2006.253.08:11:12.07#ibcon#about to read 3, iclass 22, count 2 2006.253.08:11:12.09#ibcon#read 3, iclass 22, count 2 2006.253.08:11:12.09#ibcon#about to read 4, iclass 22, count 2 2006.253.08:11:12.09#ibcon#read 4, iclass 22, count 2 2006.253.08:11:12.09#ibcon#about to read 5, iclass 22, count 2 2006.253.08:11:12.09#ibcon#read 5, iclass 22, count 2 2006.253.08:11:12.09#ibcon#about to read 6, iclass 22, count 2 2006.253.08:11:12.09#ibcon#read 6, iclass 22, count 2 2006.253.08:11:12.09#ibcon#end of sib2, iclass 22, count 2 2006.253.08:11:12.09#ibcon#*mode == 0, iclass 22, count 2 2006.253.08:11:12.09#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.253.08:11:12.09#ibcon#[27=AT05-04\r\n] 2006.253.08:11:12.09#ibcon#*before write, iclass 22, count 2 2006.253.08:11:12.09#ibcon#enter sib2, iclass 22, count 2 2006.253.08:11:12.09#ibcon#flushed, iclass 22, count 2 2006.253.08:11:12.09#ibcon#about to write, iclass 22, count 2 2006.253.08:11:12.09#ibcon#wrote, iclass 22, count 2 2006.253.08:11:12.09#ibcon#about to read 3, iclass 22, count 2 2006.253.08:11:12.12#ibcon#read 3, iclass 22, count 2 2006.253.08:11:12.12#ibcon#about to read 4, iclass 22, count 2 2006.253.08:11:12.12#ibcon#read 4, iclass 22, count 2 2006.253.08:11:12.12#ibcon#about to read 5, iclass 22, count 2 2006.253.08:11:12.12#ibcon#read 5, iclass 22, count 2 2006.253.08:11:12.12#ibcon#about to read 6, iclass 22, count 2 2006.253.08:11:12.12#ibcon#read 6, iclass 22, count 2 2006.253.08:11:12.12#ibcon#end of sib2, iclass 22, count 2 2006.253.08:11:12.12#ibcon#*after write, iclass 22, count 2 2006.253.08:11:12.12#ibcon#*before return 0, iclass 22, count 2 2006.253.08:11:12.12#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.253.08:11:12.12#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.253.08:11:12.12#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.253.08:11:12.12#ibcon#ireg 7 cls_cnt 0 2006.253.08:11:12.12#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.253.08:11:12.24#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.253.08:11:12.24#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.253.08:11:12.24#ibcon#enter wrdev, iclass 22, count 0 2006.253.08:11:12.24#ibcon#first serial, iclass 22, count 0 2006.253.08:11:12.24#ibcon#enter sib2, iclass 22, count 0 2006.253.08:11:12.24#ibcon#flushed, iclass 22, count 0 2006.253.08:11:12.24#ibcon#about to write, iclass 22, count 0 2006.253.08:11:12.24#ibcon#wrote, iclass 22, count 0 2006.253.08:11:12.24#ibcon#about to read 3, iclass 22, count 0 2006.253.08:11:12.26#ibcon#read 3, iclass 22, count 0 2006.253.08:11:12.26#ibcon#about to read 4, iclass 22, count 0 2006.253.08:11:12.26#ibcon#read 4, iclass 22, count 0 2006.253.08:11:12.26#ibcon#about to read 5, iclass 22, count 0 2006.253.08:11:12.26#ibcon#read 5, iclass 22, count 0 2006.253.08:11:12.26#ibcon#about to read 6, iclass 22, count 0 2006.253.08:11:12.26#ibcon#read 6, iclass 22, count 0 2006.253.08:11:12.26#ibcon#end of sib2, iclass 22, count 0 2006.253.08:11:12.26#ibcon#*mode == 0, iclass 22, count 0 2006.253.08:11:12.26#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.253.08:11:12.26#ibcon#[27=USB\r\n] 2006.253.08:11:12.26#ibcon#*before write, iclass 22, count 0 2006.253.08:11:12.26#ibcon#enter sib2, iclass 22, count 0 2006.253.08:11:12.26#ibcon#flushed, iclass 22, count 0 2006.253.08:11:12.26#ibcon#about to write, iclass 22, count 0 2006.253.08:11:12.26#ibcon#wrote, iclass 22, count 0 2006.253.08:11:12.26#ibcon#about to read 3, iclass 22, count 0 2006.253.08:11:12.29#ibcon#read 3, iclass 22, count 0 2006.253.08:11:12.29#ibcon#about to read 4, iclass 22, count 0 2006.253.08:11:12.29#ibcon#read 4, iclass 22, count 0 2006.253.08:11:12.29#ibcon#about to read 5, iclass 22, count 0 2006.253.08:11:12.29#ibcon#read 5, iclass 22, count 0 2006.253.08:11:12.29#ibcon#about to read 6, iclass 22, count 0 2006.253.08:11:12.29#ibcon#read 6, iclass 22, count 0 2006.253.08:11:12.29#ibcon#end of sib2, iclass 22, count 0 2006.253.08:11:12.29#ibcon#*after write, iclass 22, count 0 2006.253.08:11:12.29#ibcon#*before return 0, iclass 22, count 0 2006.253.08:11:12.29#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.253.08:11:12.29#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.253.08:11:12.29#ibcon#about to clear, iclass 22 cls_cnt 0 2006.253.08:11:12.29#ibcon#cleared, iclass 22 cls_cnt 0 2006.253.08:11:12.29$vc4f8/vblo=6,752.99 2006.253.08:11:12.29#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.253.08:11:12.29#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.253.08:11:12.29#ibcon#ireg 17 cls_cnt 0 2006.253.08:11:12.29#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.253.08:11:12.29#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.253.08:11:12.29#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.253.08:11:12.29#ibcon#enter wrdev, iclass 24, count 0 2006.253.08:11:12.29#ibcon#first serial, iclass 24, count 0 2006.253.08:11:12.29#ibcon#enter sib2, iclass 24, count 0 2006.253.08:11:12.29#ibcon#flushed, iclass 24, count 0 2006.253.08:11:12.29#ibcon#about to write, iclass 24, count 0 2006.253.08:11:12.29#ibcon#wrote, iclass 24, count 0 2006.253.08:11:12.29#ibcon#about to read 3, iclass 24, count 0 2006.253.08:11:12.31#ibcon#read 3, iclass 24, count 0 2006.253.08:11:12.31#ibcon#about to read 4, iclass 24, count 0 2006.253.08:11:12.31#ibcon#read 4, iclass 24, count 0 2006.253.08:11:12.31#ibcon#about to read 5, iclass 24, count 0 2006.253.08:11:12.31#ibcon#read 5, iclass 24, count 0 2006.253.08:11:12.31#ibcon#about to read 6, iclass 24, count 0 2006.253.08:11:12.31#ibcon#read 6, iclass 24, count 0 2006.253.08:11:12.31#ibcon#end of sib2, iclass 24, count 0 2006.253.08:11:12.31#ibcon#*mode == 0, iclass 24, count 0 2006.253.08:11:12.31#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.253.08:11:12.31#ibcon#[28=FRQ=06,752.99\r\n] 2006.253.08:11:12.31#ibcon#*before write, iclass 24, count 0 2006.253.08:11:12.31#ibcon#enter sib2, iclass 24, count 0 2006.253.08:11:12.31#ibcon#flushed, iclass 24, count 0 2006.253.08:11:12.31#ibcon#about to write, iclass 24, count 0 2006.253.08:11:12.31#ibcon#wrote, iclass 24, count 0 2006.253.08:11:12.31#ibcon#about to read 3, iclass 24, count 0 2006.253.08:11:12.35#ibcon#read 3, iclass 24, count 0 2006.253.08:11:12.35#ibcon#about to read 4, iclass 24, count 0 2006.253.08:11:12.35#ibcon#read 4, iclass 24, count 0 2006.253.08:11:12.35#ibcon#about to read 5, iclass 24, count 0 2006.253.08:11:12.35#ibcon#read 5, iclass 24, count 0 2006.253.08:11:12.35#ibcon#about to read 6, iclass 24, count 0 2006.253.08:11:12.35#ibcon#read 6, iclass 24, count 0 2006.253.08:11:12.35#ibcon#end of sib2, iclass 24, count 0 2006.253.08:11:12.35#ibcon#*after write, iclass 24, count 0 2006.253.08:11:12.35#ibcon#*before return 0, iclass 24, count 0 2006.253.08:11:12.35#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.253.08:11:12.35#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.253.08:11:12.35#ibcon#about to clear, iclass 24 cls_cnt 0 2006.253.08:11:12.35#ibcon#cleared, iclass 24 cls_cnt 0 2006.253.08:11:12.35$vc4f8/vb=6,4 2006.253.08:11:12.35#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.253.08:11:12.35#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.253.08:11:12.35#ibcon#ireg 11 cls_cnt 2 2006.253.08:11:12.35#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.253.08:11:12.41#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.253.08:11:12.41#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.253.08:11:12.41#ibcon#enter wrdev, iclass 26, count 2 2006.253.08:11:12.41#ibcon#first serial, iclass 26, count 2 2006.253.08:11:12.41#ibcon#enter sib2, iclass 26, count 2 2006.253.08:11:12.41#ibcon#flushed, iclass 26, count 2 2006.253.08:11:12.41#ibcon#about to write, iclass 26, count 2 2006.253.08:11:12.41#ibcon#wrote, iclass 26, count 2 2006.253.08:11:12.41#ibcon#about to read 3, iclass 26, count 2 2006.253.08:11:12.43#ibcon#read 3, iclass 26, count 2 2006.253.08:11:12.43#ibcon#about to read 4, iclass 26, count 2 2006.253.08:11:12.43#ibcon#read 4, iclass 26, count 2 2006.253.08:11:12.43#ibcon#about to read 5, iclass 26, count 2 2006.253.08:11:12.43#ibcon#read 5, iclass 26, count 2 2006.253.08:11:12.43#ibcon#about to read 6, iclass 26, count 2 2006.253.08:11:12.43#ibcon#read 6, iclass 26, count 2 2006.253.08:11:12.43#ibcon#end of sib2, iclass 26, count 2 2006.253.08:11:12.43#ibcon#*mode == 0, iclass 26, count 2 2006.253.08:11:12.43#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.253.08:11:12.43#ibcon#[27=AT06-04\r\n] 2006.253.08:11:12.43#ibcon#*before write, iclass 26, count 2 2006.253.08:11:12.43#ibcon#enter sib2, iclass 26, count 2 2006.253.08:11:12.43#ibcon#flushed, iclass 26, count 2 2006.253.08:11:12.43#ibcon#about to write, iclass 26, count 2 2006.253.08:11:12.43#ibcon#wrote, iclass 26, count 2 2006.253.08:11:12.43#ibcon#about to read 3, iclass 26, count 2 2006.253.08:11:12.46#ibcon#read 3, iclass 26, count 2 2006.253.08:11:12.46#ibcon#about to read 4, iclass 26, count 2 2006.253.08:11:12.46#ibcon#read 4, iclass 26, count 2 2006.253.08:11:12.46#ibcon#about to read 5, iclass 26, count 2 2006.253.08:11:12.46#ibcon#read 5, iclass 26, count 2 2006.253.08:11:12.46#ibcon#about to read 6, iclass 26, count 2 2006.253.08:11:12.46#ibcon#read 6, iclass 26, count 2 2006.253.08:11:12.46#ibcon#end of sib2, iclass 26, count 2 2006.253.08:11:12.46#ibcon#*after write, iclass 26, count 2 2006.253.08:11:12.46#ibcon#*before return 0, iclass 26, count 2 2006.253.08:11:12.46#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.253.08:11:12.46#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.253.08:11:12.46#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.253.08:11:12.46#ibcon#ireg 7 cls_cnt 0 2006.253.08:11:12.46#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.253.08:11:12.58#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.253.08:11:12.58#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.253.08:11:12.58#ibcon#enter wrdev, iclass 26, count 0 2006.253.08:11:12.58#ibcon#first serial, iclass 26, count 0 2006.253.08:11:12.58#ibcon#enter sib2, iclass 26, count 0 2006.253.08:11:12.58#ibcon#flushed, iclass 26, count 0 2006.253.08:11:12.58#ibcon#about to write, iclass 26, count 0 2006.253.08:11:12.58#ibcon#wrote, iclass 26, count 0 2006.253.08:11:12.58#ibcon#about to read 3, iclass 26, count 0 2006.253.08:11:12.60#ibcon#read 3, iclass 26, count 0 2006.253.08:11:12.60#ibcon#about to read 4, iclass 26, count 0 2006.253.08:11:12.60#ibcon#read 4, iclass 26, count 0 2006.253.08:11:12.60#ibcon#about to read 5, iclass 26, count 0 2006.253.08:11:12.60#ibcon#read 5, iclass 26, count 0 2006.253.08:11:12.60#ibcon#about to read 6, iclass 26, count 0 2006.253.08:11:12.60#ibcon#read 6, iclass 26, count 0 2006.253.08:11:12.60#ibcon#end of sib2, iclass 26, count 0 2006.253.08:11:12.60#ibcon#*mode == 0, iclass 26, count 0 2006.253.08:11:12.60#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.253.08:11:12.60#ibcon#[27=USB\r\n] 2006.253.08:11:12.60#ibcon#*before write, iclass 26, count 0 2006.253.08:11:12.60#ibcon#enter sib2, iclass 26, count 0 2006.253.08:11:12.60#ibcon#flushed, iclass 26, count 0 2006.253.08:11:12.60#ibcon#about to write, iclass 26, count 0 2006.253.08:11:12.60#ibcon#wrote, iclass 26, count 0 2006.253.08:11:12.60#ibcon#about to read 3, iclass 26, count 0 2006.253.08:11:12.63#abcon#<5=/08 1.2 2.9 30.96 741006.5\r\n> 2006.253.08:11:12.63#ibcon#read 3, iclass 26, count 0 2006.253.08:11:12.63#ibcon#about to read 4, iclass 26, count 0 2006.253.08:11:12.63#ibcon#read 4, iclass 26, count 0 2006.253.08:11:12.63#ibcon#about to read 5, iclass 26, count 0 2006.253.08:11:12.63#ibcon#read 5, iclass 26, count 0 2006.253.08:11:12.63#ibcon#about to read 6, iclass 26, count 0 2006.253.08:11:12.63#ibcon#read 6, iclass 26, count 0 2006.253.08:11:12.63#ibcon#end of sib2, iclass 26, count 0 2006.253.08:11:12.63#ibcon#*after write, iclass 26, count 0 2006.253.08:11:12.63#ibcon#*before return 0, iclass 26, count 0 2006.253.08:11:12.63#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.253.08:11:12.63#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.253.08:11:12.63#ibcon#about to clear, iclass 26 cls_cnt 0 2006.253.08:11:12.63#ibcon#cleared, iclass 26 cls_cnt 0 2006.253.08:11:12.63$vc4f8/vabw=wide 2006.253.08:11:12.63#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.253.08:11:12.63#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.253.08:11:12.63#ibcon#ireg 8 cls_cnt 0 2006.253.08:11:12.63#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.253.08:11:12.63#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.253.08:11:12.63#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.253.08:11:12.63#ibcon#enter wrdev, iclass 31, count 0 2006.253.08:11:12.63#ibcon#first serial, iclass 31, count 0 2006.253.08:11:12.63#ibcon#enter sib2, iclass 31, count 0 2006.253.08:11:12.63#ibcon#flushed, iclass 31, count 0 2006.253.08:11:12.63#ibcon#about to write, iclass 31, count 0 2006.253.08:11:12.63#ibcon#wrote, iclass 31, count 0 2006.253.08:11:12.63#ibcon#about to read 3, iclass 31, count 0 2006.253.08:11:12.65#abcon#{5=INTERFACE CLEAR} 2006.253.08:11:12.65#ibcon#read 3, iclass 31, count 0 2006.253.08:11:12.65#ibcon#about to read 4, iclass 31, count 0 2006.253.08:11:12.65#ibcon#read 4, iclass 31, count 0 2006.253.08:11:12.65#ibcon#about to read 5, iclass 31, count 0 2006.253.08:11:12.65#ibcon#read 5, iclass 31, count 0 2006.253.08:11:12.65#ibcon#about to read 6, iclass 31, count 0 2006.253.08:11:12.65#ibcon#read 6, iclass 31, count 0 2006.253.08:11:12.65#ibcon#end of sib2, iclass 31, count 0 2006.253.08:11:12.65#ibcon#*mode == 0, iclass 31, count 0 2006.253.08:11:12.65#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.253.08:11:12.65#ibcon#[25=BW32\r\n] 2006.253.08:11:12.65#ibcon#*before write, iclass 31, count 0 2006.253.08:11:12.65#ibcon#enter sib2, iclass 31, count 0 2006.253.08:11:12.65#ibcon#flushed, iclass 31, count 0 2006.253.08:11:12.65#ibcon#about to write, iclass 31, count 0 2006.253.08:11:12.65#ibcon#wrote, iclass 31, count 0 2006.253.08:11:12.65#ibcon#about to read 3, iclass 31, count 0 2006.253.08:11:12.69#ibcon#read 3, iclass 31, count 0 2006.253.08:11:12.69#ibcon#about to read 4, iclass 31, count 0 2006.253.08:11:12.69#ibcon#read 4, iclass 31, count 0 2006.253.08:11:12.69#ibcon#about to read 5, iclass 31, count 0 2006.253.08:11:12.69#ibcon#read 5, iclass 31, count 0 2006.253.08:11:12.69#ibcon#about to read 6, iclass 31, count 0 2006.253.08:11:12.69#ibcon#read 6, iclass 31, count 0 2006.253.08:11:12.69#ibcon#end of sib2, iclass 31, count 0 2006.253.08:11:12.69#ibcon#*after write, iclass 31, count 0 2006.253.08:11:12.69#ibcon#*before return 0, iclass 31, count 0 2006.253.08:11:12.69#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.253.08:11:12.69#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.253.08:11:12.69#ibcon#about to clear, iclass 31 cls_cnt 0 2006.253.08:11:12.69#ibcon#cleared, iclass 31 cls_cnt 0 2006.253.08:11:12.69$vc4f8/vbbw=wide 2006.253.08:11:12.69#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.253.08:11:12.69#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.253.08:11:12.69#ibcon#ireg 8 cls_cnt 0 2006.253.08:11:12.69#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.253.08:11:12.71#abcon#[5=S1D000X0/0*\r\n] 2006.253.08:11:12.75#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.253.08:11:12.75#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.253.08:11:12.75#ibcon#enter wrdev, iclass 33, count 0 2006.253.08:11:12.75#ibcon#first serial, iclass 33, count 0 2006.253.08:11:12.75#ibcon#enter sib2, iclass 33, count 0 2006.253.08:11:12.75#ibcon#flushed, iclass 33, count 0 2006.253.08:11:12.75#ibcon#about to write, iclass 33, count 0 2006.253.08:11:12.75#ibcon#wrote, iclass 33, count 0 2006.253.08:11:12.75#ibcon#about to read 3, iclass 33, count 0 2006.253.08:11:12.77#ibcon#read 3, iclass 33, count 0 2006.253.08:11:12.77#ibcon#about to read 4, iclass 33, count 0 2006.253.08:11:12.77#ibcon#read 4, iclass 33, count 0 2006.253.08:11:12.77#ibcon#about to read 5, iclass 33, count 0 2006.253.08:11:12.77#ibcon#read 5, iclass 33, count 0 2006.253.08:11:12.77#ibcon#about to read 6, iclass 33, count 0 2006.253.08:11:12.77#ibcon#read 6, iclass 33, count 0 2006.253.08:11:12.77#ibcon#end of sib2, iclass 33, count 0 2006.253.08:11:12.77#ibcon#*mode == 0, iclass 33, count 0 2006.253.08:11:12.77#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.253.08:11:12.77#ibcon#[27=BW32\r\n] 2006.253.08:11:12.77#ibcon#*before write, iclass 33, count 0 2006.253.08:11:12.77#ibcon#enter sib2, iclass 33, count 0 2006.253.08:11:12.77#ibcon#flushed, iclass 33, count 0 2006.253.08:11:12.77#ibcon#about to write, iclass 33, count 0 2006.253.08:11:12.77#ibcon#wrote, iclass 33, count 0 2006.253.08:11:12.77#ibcon#about to read 3, iclass 33, count 0 2006.253.08:11:12.80#ibcon#read 3, iclass 33, count 0 2006.253.08:11:12.80#ibcon#about to read 4, iclass 33, count 0 2006.253.08:11:12.80#ibcon#read 4, iclass 33, count 0 2006.253.08:11:12.80#ibcon#about to read 5, iclass 33, count 0 2006.253.08:11:12.80#ibcon#read 5, iclass 33, count 0 2006.253.08:11:12.80#ibcon#about to read 6, iclass 33, count 0 2006.253.08:11:12.80#ibcon#read 6, iclass 33, count 0 2006.253.08:11:12.80#ibcon#end of sib2, iclass 33, count 0 2006.253.08:11:12.80#ibcon#*after write, iclass 33, count 0 2006.253.08:11:12.80#ibcon#*before return 0, iclass 33, count 0 2006.253.08:11:12.80#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.253.08:11:12.80#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.253.08:11:12.80#ibcon#about to clear, iclass 33 cls_cnt 0 2006.253.08:11:12.80#ibcon#cleared, iclass 33 cls_cnt 0 2006.253.08:11:12.80$4f8m12a/ifd4f 2006.253.08:11:12.80$ifd4f/lo= 2006.253.08:11:12.80$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.253.08:11:12.80$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.253.08:11:12.80$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.253.08:11:12.80$ifd4f/patch= 2006.253.08:11:12.80$ifd4f/patch=lo1,a1,a2,a3,a4 2006.253.08:11:12.80$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.253.08:11:12.80$ifd4f/patch=lo3,a5,a6,a7,a8 2006.253.08:11:12.80$4f8m12a/"form=m,16.000,1:2 2006.253.08:11:12.80$4f8m12a/"tpicd 2006.253.08:11:12.80$4f8m12a/echo=off 2006.253.08:11:12.80$4f8m12a/xlog=off 2006.253.08:11:12.80:!2006.253.08:12:10 2006.253.08:11:46.13#trakl#Source acquired 2006.253.08:11:46.13#flagr#flagr/antenna,acquired 2006.253.08:12:10.00:preob 2006.253.08:12:11.13/onsource/TRACKING 2006.253.08:12:11.13:!2006.253.08:12:20 2006.253.08:12:20.00:data_valid=on 2006.253.08:12:20.00:midob 2006.253.08:12:20.13/onsource/TRACKING 2006.253.08:12:20.13/wx/30.95,1006.5,74 2006.253.08:12:20.25/cable/+6.3690E-03 2006.253.08:12:21.34/va/01,08,usb,yes,33,34 2006.253.08:12:21.34/va/02,07,usb,yes,32,34 2006.253.08:12:21.34/va/03,06,usb,yes,35,35 2006.253.08:12:21.34/va/04,07,usb,yes,34,37 2006.253.08:12:21.34/va/05,07,usb,yes,35,37 2006.253.08:12:21.34/va/06,07,usb,yes,31,31 2006.253.08:12:21.34/va/07,07,usb,yes,31,31 2006.253.08:12:21.34/va/08,07,usb,yes,33,33 2006.253.08:12:21.57/valo/01,532.99,yes,locked 2006.253.08:12:21.57/valo/02,572.99,yes,locked 2006.253.08:12:21.57/valo/03,672.99,yes,locked 2006.253.08:12:21.57/valo/04,832.99,yes,locked 2006.253.08:12:21.57/valo/05,652.99,yes,locked 2006.253.08:12:21.57/valo/06,772.99,yes,locked 2006.253.08:12:21.57/valo/07,832.99,yes,locked 2006.253.08:12:21.57/valo/08,852.99,yes,locked 2006.253.08:12:22.66/vb/01,04,usb,yes,31,29 2006.253.08:12:22.66/vb/02,05,usb,yes,29,30 2006.253.08:12:22.66/vb/03,04,usb,yes,28,32 2006.253.08:12:22.66/vb/04,04,usb,yes,29,30 2006.253.08:12:22.66/vb/05,04,usb,yes,28,32 2006.253.08:12:22.66/vb/06,04,usb,yes,29,32 2006.253.08:12:22.66/vb/07,04,usb,yes,31,31 2006.253.08:12:22.66/vb/08,04,usb,yes,28,32 2006.253.08:12:22.90/vblo/01,632.99,yes,locked 2006.253.08:12:22.90/vblo/02,640.99,yes,locked 2006.253.08:12:22.90/vblo/03,656.99,yes,locked 2006.253.08:12:22.90/vblo/04,712.99,yes,locked 2006.253.08:12:22.90/vblo/05,744.99,yes,locked 2006.253.08:12:22.90/vblo/06,752.99,yes,locked 2006.253.08:12:22.90/vblo/07,734.99,yes,locked 2006.253.08:12:22.90/vblo/08,744.99,yes,locked 2006.253.08:12:23.05/vabw/8 2006.253.08:12:23.20/vbbw/8 2006.253.08:12:23.29/xfe/off,on,14.7 2006.253.08:12:23.67/ifatt/23,28,28,28 2006.253.08:12:24.08/fmout-gps/S +4.73E-07 2006.253.08:12:24.12:!2006.253.08:13:30 2006.253.08:13:30.00:data_valid=off 2006.253.08:13:30.00:postob 2006.253.08:13:30.12/cable/+6.3699E-03 2006.253.08:13:30.12/wx/30.93,1006.5,74 2006.253.08:13:31.08/fmout-gps/S +4.73E-07 2006.253.08:13:31.08:scan_name=253-0814,k06253,60 2006.253.08:13:31.08:source=1357+769,135755.37,764321.1,2000.0,ccw 2006.253.08:13:32.14#flagr#flagr/antenna,new-source 2006.253.08:13:32.14:checkk5 2006.253.08:13:32.52/chk_autoobs//k5ts1/ autoobs is running! 2006.253.08:13:32.90/chk_autoobs//k5ts2/ autoobs is running! 2006.253.08:13:33.29/chk_autoobs//k5ts3/ autoobs is running! 2006.253.08:13:33.67/chk_autoobs//k5ts4/ autoobs is running! 2006.253.08:13:34.04/chk_obsdata//k5ts1/T2530812??a.dat file size is correct (nominal:560MB, actual:552MB). 2006.253.08:13:34.41/chk_obsdata//k5ts2/T2530812??b.dat file size is correct (nominal:560MB, actual:552MB). 2006.253.08:13:34.78/chk_obsdata//k5ts3/T2530812??c.dat file size is correct (nominal:560MB, actual:552MB). 2006.253.08:13:35.15/chk_obsdata//k5ts4/T2530812??d.dat file size is correct (nominal:560MB, actual:552MB). 2006.253.08:13:35.86/k5log//k5ts1_log_newline 2006.253.08:13:36.56/k5log//k5ts2_log_newline 2006.253.08:13:37.25/k5log//k5ts3_log_newline 2006.253.08:13:37.94/k5log//k5ts4_log_newline 2006.253.08:13:37.96/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.253.08:13:37.96:4f8m12a=2 2006.253.08:13:37.96$4f8m12a/echo=on 2006.253.08:13:37.96$4f8m12a/pcalon 2006.253.08:13:37.96$pcalon/"no phase cal control is implemented here 2006.253.08:13:37.96$4f8m12a/"tpicd=stop 2006.253.08:13:37.96$4f8m12a/vc4f8 2006.253.08:13:37.96$vc4f8/valo=1,532.99 2006.253.08:13:37.97#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.253.08:13:37.97#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.253.08:13:37.97#ibcon#ireg 17 cls_cnt 0 2006.253.08:13:37.97#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.253.08:13:37.97#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.253.08:13:37.97#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.253.08:13:37.97#ibcon#enter wrdev, iclass 21, count 0 2006.253.08:13:37.97#ibcon#first serial, iclass 21, count 0 2006.253.08:13:37.97#ibcon#enter sib2, iclass 21, count 0 2006.253.08:13:37.97#ibcon#flushed, iclass 21, count 0 2006.253.08:13:37.97#ibcon#about to write, iclass 21, count 0 2006.253.08:13:37.97#ibcon#wrote, iclass 21, count 0 2006.253.08:13:37.97#ibcon#about to read 3, iclass 21, count 0 2006.253.08:13:38.01#ibcon#read 3, iclass 21, count 0 2006.253.08:13:38.01#ibcon#about to read 4, iclass 21, count 0 2006.253.08:13:38.01#ibcon#read 4, iclass 21, count 0 2006.253.08:13:38.01#ibcon#about to read 5, iclass 21, count 0 2006.253.08:13:38.01#ibcon#read 5, iclass 21, count 0 2006.253.08:13:38.01#ibcon#about to read 6, iclass 21, count 0 2006.253.08:13:38.01#ibcon#read 6, iclass 21, count 0 2006.253.08:13:38.01#ibcon#end of sib2, iclass 21, count 0 2006.253.08:13:38.01#ibcon#*mode == 0, iclass 21, count 0 2006.253.08:13:38.01#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.253.08:13:38.01#ibcon#[26=FRQ=01,532.99\r\n] 2006.253.08:13:38.01#ibcon#*before write, iclass 21, count 0 2006.253.08:13:38.01#ibcon#enter sib2, iclass 21, count 0 2006.253.08:13:38.01#ibcon#flushed, iclass 21, count 0 2006.253.08:13:38.01#ibcon#about to write, iclass 21, count 0 2006.253.08:13:38.01#ibcon#wrote, iclass 21, count 0 2006.253.08:13:38.01#ibcon#about to read 3, iclass 21, count 0 2006.253.08:13:38.06#ibcon#read 3, iclass 21, count 0 2006.253.08:13:38.06#ibcon#about to read 4, iclass 21, count 0 2006.253.08:13:38.06#ibcon#read 4, iclass 21, count 0 2006.253.08:13:38.06#ibcon#about to read 5, iclass 21, count 0 2006.253.08:13:38.06#ibcon#read 5, iclass 21, count 0 2006.253.08:13:38.06#ibcon#about to read 6, iclass 21, count 0 2006.253.08:13:38.06#ibcon#read 6, iclass 21, count 0 2006.253.08:13:38.06#ibcon#end of sib2, iclass 21, count 0 2006.253.08:13:38.06#ibcon#*after write, iclass 21, count 0 2006.253.08:13:38.06#ibcon#*before return 0, iclass 21, count 0 2006.253.08:13:38.06#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.253.08:13:38.06#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.253.08:13:38.06#ibcon#about to clear, iclass 21 cls_cnt 0 2006.253.08:13:38.06#ibcon#cleared, iclass 21 cls_cnt 0 2006.253.08:13:38.06$vc4f8/va=1,8 2006.253.08:13:38.06#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.253.08:13:38.06#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.253.08:13:38.06#ibcon#ireg 11 cls_cnt 2 2006.253.08:13:38.06#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.253.08:13:38.06#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.253.08:13:38.06#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.253.08:13:38.06#ibcon#enter wrdev, iclass 23, count 2 2006.253.08:13:38.06#ibcon#first serial, iclass 23, count 2 2006.253.08:13:38.06#ibcon#enter sib2, iclass 23, count 2 2006.253.08:13:38.06#ibcon#flushed, iclass 23, count 2 2006.253.08:13:38.06#ibcon#about to write, iclass 23, count 2 2006.253.08:13:38.06#ibcon#wrote, iclass 23, count 2 2006.253.08:13:38.06#ibcon#about to read 3, iclass 23, count 2 2006.253.08:13:38.08#ibcon#read 3, iclass 23, count 2 2006.253.08:13:38.08#ibcon#about to read 4, iclass 23, count 2 2006.253.08:13:38.08#ibcon#read 4, iclass 23, count 2 2006.253.08:13:38.08#ibcon#about to read 5, iclass 23, count 2 2006.253.08:13:38.08#ibcon#read 5, iclass 23, count 2 2006.253.08:13:38.08#ibcon#about to read 6, iclass 23, count 2 2006.253.08:13:38.08#ibcon#read 6, iclass 23, count 2 2006.253.08:13:38.08#ibcon#end of sib2, iclass 23, count 2 2006.253.08:13:38.08#ibcon#*mode == 0, iclass 23, count 2 2006.253.08:13:38.08#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.253.08:13:38.08#ibcon#[25=AT01-08\r\n] 2006.253.08:13:38.08#ibcon#*before write, iclass 23, count 2 2006.253.08:13:38.08#ibcon#enter sib2, iclass 23, count 2 2006.253.08:13:38.08#ibcon#flushed, iclass 23, count 2 2006.253.08:13:38.08#ibcon#about to write, iclass 23, count 2 2006.253.08:13:38.08#ibcon#wrote, iclass 23, count 2 2006.253.08:13:38.08#ibcon#about to read 3, iclass 23, count 2 2006.253.08:13:38.11#ibcon#read 3, iclass 23, count 2 2006.253.08:13:38.11#ibcon#about to read 4, iclass 23, count 2 2006.253.08:13:38.11#ibcon#read 4, iclass 23, count 2 2006.253.08:13:38.11#ibcon#about to read 5, iclass 23, count 2 2006.253.08:13:38.11#ibcon#read 5, iclass 23, count 2 2006.253.08:13:38.11#ibcon#about to read 6, iclass 23, count 2 2006.253.08:13:38.11#ibcon#read 6, iclass 23, count 2 2006.253.08:13:38.11#ibcon#end of sib2, iclass 23, count 2 2006.253.08:13:38.11#ibcon#*after write, iclass 23, count 2 2006.253.08:13:38.11#ibcon#*before return 0, iclass 23, count 2 2006.253.08:13:38.11#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.253.08:13:38.11#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.253.08:13:38.11#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.253.08:13:38.11#ibcon#ireg 7 cls_cnt 0 2006.253.08:13:38.11#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.253.08:13:38.23#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.253.08:13:38.23#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.253.08:13:38.23#ibcon#enter wrdev, iclass 23, count 0 2006.253.08:13:38.23#ibcon#first serial, iclass 23, count 0 2006.253.08:13:38.23#ibcon#enter sib2, iclass 23, count 0 2006.253.08:13:38.23#ibcon#flushed, iclass 23, count 0 2006.253.08:13:38.23#ibcon#about to write, iclass 23, count 0 2006.253.08:13:38.23#ibcon#wrote, iclass 23, count 0 2006.253.08:13:38.23#ibcon#about to read 3, iclass 23, count 0 2006.253.08:13:38.25#ibcon#read 3, iclass 23, count 0 2006.253.08:13:38.25#ibcon#about to read 4, iclass 23, count 0 2006.253.08:13:38.25#ibcon#read 4, iclass 23, count 0 2006.253.08:13:38.25#ibcon#about to read 5, iclass 23, count 0 2006.253.08:13:38.25#ibcon#read 5, iclass 23, count 0 2006.253.08:13:38.25#ibcon#about to read 6, iclass 23, count 0 2006.253.08:13:38.25#ibcon#read 6, iclass 23, count 0 2006.253.08:13:38.25#ibcon#end of sib2, iclass 23, count 0 2006.253.08:13:38.25#ibcon#*mode == 0, iclass 23, count 0 2006.253.08:13:38.25#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.253.08:13:38.25#ibcon#[25=USB\r\n] 2006.253.08:13:38.25#ibcon#*before write, iclass 23, count 0 2006.253.08:13:38.25#ibcon#enter sib2, iclass 23, count 0 2006.253.08:13:38.25#ibcon#flushed, iclass 23, count 0 2006.253.08:13:38.25#ibcon#about to write, iclass 23, count 0 2006.253.08:13:38.25#ibcon#wrote, iclass 23, count 0 2006.253.08:13:38.25#ibcon#about to read 3, iclass 23, count 0 2006.253.08:13:38.28#ibcon#read 3, iclass 23, count 0 2006.253.08:13:38.28#ibcon#about to read 4, iclass 23, count 0 2006.253.08:13:38.28#ibcon#read 4, iclass 23, count 0 2006.253.08:13:38.28#ibcon#about to read 5, iclass 23, count 0 2006.253.08:13:38.28#ibcon#read 5, iclass 23, count 0 2006.253.08:13:38.28#ibcon#about to read 6, iclass 23, count 0 2006.253.08:13:38.28#ibcon#read 6, iclass 23, count 0 2006.253.08:13:38.28#ibcon#end of sib2, iclass 23, count 0 2006.253.08:13:38.28#ibcon#*after write, iclass 23, count 0 2006.253.08:13:38.28#ibcon#*before return 0, iclass 23, count 0 2006.253.08:13:38.28#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.253.08:13:38.28#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.253.08:13:38.28#ibcon#about to clear, iclass 23 cls_cnt 0 2006.253.08:13:38.28#ibcon#cleared, iclass 23 cls_cnt 0 2006.253.08:13:38.28$vc4f8/valo=2,572.99 2006.253.08:13:38.28#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.253.08:13:38.28#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.253.08:13:38.28#ibcon#ireg 17 cls_cnt 0 2006.253.08:13:38.28#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.253.08:13:38.28#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.253.08:13:38.28#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.253.08:13:38.28#ibcon#enter wrdev, iclass 25, count 0 2006.253.08:13:38.28#ibcon#first serial, iclass 25, count 0 2006.253.08:13:38.28#ibcon#enter sib2, iclass 25, count 0 2006.253.08:13:38.28#ibcon#flushed, iclass 25, count 0 2006.253.08:13:38.28#ibcon#about to write, iclass 25, count 0 2006.253.08:13:38.28#ibcon#wrote, iclass 25, count 0 2006.253.08:13:38.28#ibcon#about to read 3, iclass 25, count 0 2006.253.08:13:38.30#ibcon#read 3, iclass 25, count 0 2006.253.08:13:38.30#ibcon#about to read 4, iclass 25, count 0 2006.253.08:13:38.30#ibcon#read 4, iclass 25, count 0 2006.253.08:13:38.30#ibcon#about to read 5, iclass 25, count 0 2006.253.08:13:38.30#ibcon#read 5, iclass 25, count 0 2006.253.08:13:38.30#ibcon#about to read 6, iclass 25, count 0 2006.253.08:13:38.30#ibcon#read 6, iclass 25, count 0 2006.253.08:13:38.30#ibcon#end of sib2, iclass 25, count 0 2006.253.08:13:38.30#ibcon#*mode == 0, iclass 25, count 0 2006.253.08:13:38.30#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.253.08:13:38.30#ibcon#[26=FRQ=02,572.99\r\n] 2006.253.08:13:38.30#ibcon#*before write, iclass 25, count 0 2006.253.08:13:38.30#ibcon#enter sib2, iclass 25, count 0 2006.253.08:13:38.30#ibcon#flushed, iclass 25, count 0 2006.253.08:13:38.30#ibcon#about to write, iclass 25, count 0 2006.253.08:13:38.30#ibcon#wrote, iclass 25, count 0 2006.253.08:13:38.30#ibcon#about to read 3, iclass 25, count 0 2006.253.08:13:38.35#ibcon#read 3, iclass 25, count 0 2006.253.08:13:38.35#ibcon#about to read 4, iclass 25, count 0 2006.253.08:13:38.35#ibcon#read 4, iclass 25, count 0 2006.253.08:13:38.35#ibcon#about to read 5, iclass 25, count 0 2006.253.08:13:38.35#ibcon#read 5, iclass 25, count 0 2006.253.08:13:38.35#ibcon#about to read 6, iclass 25, count 0 2006.253.08:13:38.35#ibcon#read 6, iclass 25, count 0 2006.253.08:13:38.35#ibcon#end of sib2, iclass 25, count 0 2006.253.08:13:38.35#ibcon#*after write, iclass 25, count 0 2006.253.08:13:38.35#ibcon#*before return 0, iclass 25, count 0 2006.253.08:13:38.35#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.253.08:13:38.35#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.253.08:13:38.35#ibcon#about to clear, iclass 25 cls_cnt 0 2006.253.08:13:38.35#ibcon#cleared, iclass 25 cls_cnt 0 2006.253.08:13:38.35$vc4f8/va=2,7 2006.253.08:13:38.35#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.253.08:13:38.35#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.253.08:13:38.35#ibcon#ireg 11 cls_cnt 2 2006.253.08:13:38.35#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.253.08:13:38.40#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.253.08:13:38.40#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.253.08:13:38.40#ibcon#enter wrdev, iclass 27, count 2 2006.253.08:13:38.40#ibcon#first serial, iclass 27, count 2 2006.253.08:13:38.40#ibcon#enter sib2, iclass 27, count 2 2006.253.08:13:38.40#ibcon#flushed, iclass 27, count 2 2006.253.08:13:38.40#ibcon#about to write, iclass 27, count 2 2006.253.08:13:38.40#ibcon#wrote, iclass 27, count 2 2006.253.08:13:38.40#ibcon#about to read 3, iclass 27, count 2 2006.253.08:13:38.42#ibcon#read 3, iclass 27, count 2 2006.253.08:13:38.42#ibcon#about to read 4, iclass 27, count 2 2006.253.08:13:38.42#ibcon#read 4, iclass 27, count 2 2006.253.08:13:38.42#ibcon#about to read 5, iclass 27, count 2 2006.253.08:13:38.42#ibcon#read 5, iclass 27, count 2 2006.253.08:13:38.42#ibcon#about to read 6, iclass 27, count 2 2006.253.08:13:38.42#ibcon#read 6, iclass 27, count 2 2006.253.08:13:38.42#ibcon#end of sib2, iclass 27, count 2 2006.253.08:13:38.42#ibcon#*mode == 0, iclass 27, count 2 2006.253.08:13:38.42#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.253.08:13:38.42#ibcon#[25=AT02-07\r\n] 2006.253.08:13:38.42#ibcon#*before write, iclass 27, count 2 2006.253.08:13:38.42#ibcon#enter sib2, iclass 27, count 2 2006.253.08:13:38.42#ibcon#flushed, iclass 27, count 2 2006.253.08:13:38.42#ibcon#about to write, iclass 27, count 2 2006.253.08:13:38.42#ibcon#wrote, iclass 27, count 2 2006.253.08:13:38.42#ibcon#about to read 3, iclass 27, count 2 2006.253.08:13:38.45#ibcon#read 3, iclass 27, count 2 2006.253.08:13:38.45#ibcon#about to read 4, iclass 27, count 2 2006.253.08:13:38.45#ibcon#read 4, iclass 27, count 2 2006.253.08:13:38.45#ibcon#about to read 5, iclass 27, count 2 2006.253.08:13:38.45#ibcon#read 5, iclass 27, count 2 2006.253.08:13:38.45#ibcon#about to read 6, iclass 27, count 2 2006.253.08:13:38.45#ibcon#read 6, iclass 27, count 2 2006.253.08:13:38.45#ibcon#end of sib2, iclass 27, count 2 2006.253.08:13:38.45#ibcon#*after write, iclass 27, count 2 2006.253.08:13:38.45#ibcon#*before return 0, iclass 27, count 2 2006.253.08:13:38.45#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.253.08:13:38.45#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.253.08:13:38.45#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.253.08:13:38.45#ibcon#ireg 7 cls_cnt 0 2006.253.08:13:38.45#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.253.08:13:38.57#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.253.08:13:38.57#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.253.08:13:38.57#ibcon#enter wrdev, iclass 27, count 0 2006.253.08:13:38.57#ibcon#first serial, iclass 27, count 0 2006.253.08:13:38.57#ibcon#enter sib2, iclass 27, count 0 2006.253.08:13:38.57#ibcon#flushed, iclass 27, count 0 2006.253.08:13:38.57#ibcon#about to write, iclass 27, count 0 2006.253.08:13:38.57#ibcon#wrote, iclass 27, count 0 2006.253.08:13:38.57#ibcon#about to read 3, iclass 27, count 0 2006.253.08:13:38.59#ibcon#read 3, iclass 27, count 0 2006.253.08:13:38.59#ibcon#about to read 4, iclass 27, count 0 2006.253.08:13:38.59#ibcon#read 4, iclass 27, count 0 2006.253.08:13:38.59#ibcon#about to read 5, iclass 27, count 0 2006.253.08:13:38.59#ibcon#read 5, iclass 27, count 0 2006.253.08:13:38.59#ibcon#about to read 6, iclass 27, count 0 2006.253.08:13:38.59#ibcon#read 6, iclass 27, count 0 2006.253.08:13:38.59#ibcon#end of sib2, iclass 27, count 0 2006.253.08:13:38.59#ibcon#*mode == 0, iclass 27, count 0 2006.253.08:13:38.59#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.253.08:13:38.59#ibcon#[25=USB\r\n] 2006.253.08:13:38.59#ibcon#*before write, iclass 27, count 0 2006.253.08:13:38.59#ibcon#enter sib2, iclass 27, count 0 2006.253.08:13:38.59#ibcon#flushed, iclass 27, count 0 2006.253.08:13:38.59#ibcon#about to write, iclass 27, count 0 2006.253.08:13:38.59#ibcon#wrote, iclass 27, count 0 2006.253.08:13:38.59#ibcon#about to read 3, iclass 27, count 0 2006.253.08:13:38.62#ibcon#read 3, iclass 27, count 0 2006.253.08:13:38.62#ibcon#about to read 4, iclass 27, count 0 2006.253.08:13:38.62#ibcon#read 4, iclass 27, count 0 2006.253.08:13:38.62#ibcon#about to read 5, iclass 27, count 0 2006.253.08:13:38.62#ibcon#read 5, iclass 27, count 0 2006.253.08:13:38.62#ibcon#about to read 6, iclass 27, count 0 2006.253.08:13:38.62#ibcon#read 6, iclass 27, count 0 2006.253.08:13:38.62#ibcon#end of sib2, iclass 27, count 0 2006.253.08:13:38.62#ibcon#*after write, iclass 27, count 0 2006.253.08:13:38.62#ibcon#*before return 0, iclass 27, count 0 2006.253.08:13:38.62#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.253.08:13:38.62#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.253.08:13:38.62#ibcon#about to clear, iclass 27 cls_cnt 0 2006.253.08:13:38.62#ibcon#cleared, iclass 27 cls_cnt 0 2006.253.08:13:38.62$vc4f8/valo=3,672.99 2006.253.08:13:38.62#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.253.08:13:38.62#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.253.08:13:38.62#ibcon#ireg 17 cls_cnt 0 2006.253.08:13:38.62#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.253.08:13:38.62#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.253.08:13:38.62#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.253.08:13:38.62#ibcon#enter wrdev, iclass 29, count 0 2006.253.08:13:38.62#ibcon#first serial, iclass 29, count 0 2006.253.08:13:38.62#ibcon#enter sib2, iclass 29, count 0 2006.253.08:13:38.62#ibcon#flushed, iclass 29, count 0 2006.253.08:13:38.62#ibcon#about to write, iclass 29, count 0 2006.253.08:13:38.62#ibcon#wrote, iclass 29, count 0 2006.253.08:13:38.62#ibcon#about to read 3, iclass 29, count 0 2006.253.08:13:38.64#ibcon#read 3, iclass 29, count 0 2006.253.08:13:38.64#ibcon#about to read 4, iclass 29, count 0 2006.253.08:13:38.64#ibcon#read 4, iclass 29, count 0 2006.253.08:13:38.64#ibcon#about to read 5, iclass 29, count 0 2006.253.08:13:38.64#ibcon#read 5, iclass 29, count 0 2006.253.08:13:38.64#ibcon#about to read 6, iclass 29, count 0 2006.253.08:13:38.64#ibcon#read 6, iclass 29, count 0 2006.253.08:13:38.64#ibcon#end of sib2, iclass 29, count 0 2006.253.08:13:38.64#ibcon#*mode == 0, iclass 29, count 0 2006.253.08:13:38.64#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.253.08:13:38.64#ibcon#[26=FRQ=03,672.99\r\n] 2006.253.08:13:38.64#ibcon#*before write, iclass 29, count 0 2006.253.08:13:38.64#ibcon#enter sib2, iclass 29, count 0 2006.253.08:13:38.64#ibcon#flushed, iclass 29, count 0 2006.253.08:13:38.64#ibcon#about to write, iclass 29, count 0 2006.253.08:13:38.64#ibcon#wrote, iclass 29, count 0 2006.253.08:13:38.64#ibcon#about to read 3, iclass 29, count 0 2006.253.08:13:38.69#ibcon#read 3, iclass 29, count 0 2006.253.08:13:38.69#ibcon#about to read 4, iclass 29, count 0 2006.253.08:13:38.69#ibcon#read 4, iclass 29, count 0 2006.253.08:13:38.69#ibcon#about to read 5, iclass 29, count 0 2006.253.08:13:38.69#ibcon#read 5, iclass 29, count 0 2006.253.08:13:38.69#ibcon#about to read 6, iclass 29, count 0 2006.253.08:13:38.69#ibcon#read 6, iclass 29, count 0 2006.253.08:13:38.69#ibcon#end of sib2, iclass 29, count 0 2006.253.08:13:38.69#ibcon#*after write, iclass 29, count 0 2006.253.08:13:38.69#ibcon#*before return 0, iclass 29, count 0 2006.253.08:13:38.69#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.253.08:13:38.69#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.253.08:13:38.69#ibcon#about to clear, iclass 29 cls_cnt 0 2006.253.08:13:38.69#ibcon#cleared, iclass 29 cls_cnt 0 2006.253.08:13:38.69$vc4f8/va=3,6 2006.253.08:13:38.69#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.253.08:13:38.69#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.253.08:13:38.69#ibcon#ireg 11 cls_cnt 2 2006.253.08:13:38.69#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.253.08:13:38.74#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.253.08:13:38.74#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.253.08:13:38.74#ibcon#enter wrdev, iclass 31, count 2 2006.253.08:13:38.74#ibcon#first serial, iclass 31, count 2 2006.253.08:13:38.74#ibcon#enter sib2, iclass 31, count 2 2006.253.08:13:38.74#ibcon#flushed, iclass 31, count 2 2006.253.08:13:38.74#ibcon#about to write, iclass 31, count 2 2006.253.08:13:38.74#ibcon#wrote, iclass 31, count 2 2006.253.08:13:38.74#ibcon#about to read 3, iclass 31, count 2 2006.253.08:13:38.76#ibcon#read 3, iclass 31, count 2 2006.253.08:13:38.76#ibcon#about to read 4, iclass 31, count 2 2006.253.08:13:38.76#ibcon#read 4, iclass 31, count 2 2006.253.08:13:38.76#ibcon#about to read 5, iclass 31, count 2 2006.253.08:13:38.76#ibcon#read 5, iclass 31, count 2 2006.253.08:13:38.76#ibcon#about to read 6, iclass 31, count 2 2006.253.08:13:38.76#ibcon#read 6, iclass 31, count 2 2006.253.08:13:38.76#ibcon#end of sib2, iclass 31, count 2 2006.253.08:13:38.76#ibcon#*mode == 0, iclass 31, count 2 2006.253.08:13:38.76#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.253.08:13:38.76#ibcon#[25=AT03-06\r\n] 2006.253.08:13:38.76#ibcon#*before write, iclass 31, count 2 2006.253.08:13:38.76#ibcon#enter sib2, iclass 31, count 2 2006.253.08:13:38.76#ibcon#flushed, iclass 31, count 2 2006.253.08:13:38.76#ibcon#about to write, iclass 31, count 2 2006.253.08:13:38.76#ibcon#wrote, iclass 31, count 2 2006.253.08:13:38.76#ibcon#about to read 3, iclass 31, count 2 2006.253.08:13:38.79#ibcon#read 3, iclass 31, count 2 2006.253.08:13:38.79#ibcon#about to read 4, iclass 31, count 2 2006.253.08:13:38.79#ibcon#read 4, iclass 31, count 2 2006.253.08:13:38.79#ibcon#about to read 5, iclass 31, count 2 2006.253.08:13:38.79#ibcon#read 5, iclass 31, count 2 2006.253.08:13:38.79#ibcon#about to read 6, iclass 31, count 2 2006.253.08:13:38.79#ibcon#read 6, iclass 31, count 2 2006.253.08:13:38.79#ibcon#end of sib2, iclass 31, count 2 2006.253.08:13:38.79#ibcon#*after write, iclass 31, count 2 2006.253.08:13:38.79#ibcon#*before return 0, iclass 31, count 2 2006.253.08:13:38.79#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.253.08:13:38.79#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.253.08:13:38.79#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.253.08:13:38.79#ibcon#ireg 7 cls_cnt 0 2006.253.08:13:38.79#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.253.08:13:38.91#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.253.08:13:38.91#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.253.08:13:38.91#ibcon#enter wrdev, iclass 31, count 0 2006.253.08:13:38.91#ibcon#first serial, iclass 31, count 0 2006.253.08:13:38.91#ibcon#enter sib2, iclass 31, count 0 2006.253.08:13:38.91#ibcon#flushed, iclass 31, count 0 2006.253.08:13:38.91#ibcon#about to write, iclass 31, count 0 2006.253.08:13:38.91#ibcon#wrote, iclass 31, count 0 2006.253.08:13:38.91#ibcon#about to read 3, iclass 31, count 0 2006.253.08:13:38.93#ibcon#read 3, iclass 31, count 0 2006.253.08:13:38.93#ibcon#about to read 4, iclass 31, count 0 2006.253.08:13:38.93#ibcon#read 4, iclass 31, count 0 2006.253.08:13:38.93#ibcon#about to read 5, iclass 31, count 0 2006.253.08:13:38.93#ibcon#read 5, iclass 31, count 0 2006.253.08:13:38.93#ibcon#about to read 6, iclass 31, count 0 2006.253.08:13:38.93#ibcon#read 6, iclass 31, count 0 2006.253.08:13:38.93#ibcon#end of sib2, iclass 31, count 0 2006.253.08:13:38.93#ibcon#*mode == 0, iclass 31, count 0 2006.253.08:13:38.93#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.253.08:13:38.93#ibcon#[25=USB\r\n] 2006.253.08:13:38.93#ibcon#*before write, iclass 31, count 0 2006.253.08:13:38.93#ibcon#enter sib2, iclass 31, count 0 2006.253.08:13:38.93#ibcon#flushed, iclass 31, count 0 2006.253.08:13:38.93#ibcon#about to write, iclass 31, count 0 2006.253.08:13:38.93#ibcon#wrote, iclass 31, count 0 2006.253.08:13:38.93#ibcon#about to read 3, iclass 31, count 0 2006.253.08:13:38.96#ibcon#read 3, iclass 31, count 0 2006.253.08:13:38.96#ibcon#about to read 4, iclass 31, count 0 2006.253.08:13:38.96#ibcon#read 4, iclass 31, count 0 2006.253.08:13:38.96#ibcon#about to read 5, iclass 31, count 0 2006.253.08:13:38.96#ibcon#read 5, iclass 31, count 0 2006.253.08:13:38.96#ibcon#about to read 6, iclass 31, count 0 2006.253.08:13:38.96#ibcon#read 6, iclass 31, count 0 2006.253.08:13:38.96#ibcon#end of sib2, iclass 31, count 0 2006.253.08:13:38.96#ibcon#*after write, iclass 31, count 0 2006.253.08:13:38.96#ibcon#*before return 0, iclass 31, count 0 2006.253.08:13:38.96#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.253.08:13:38.96#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.253.08:13:38.96#ibcon#about to clear, iclass 31 cls_cnt 0 2006.253.08:13:38.96#ibcon#cleared, iclass 31 cls_cnt 0 2006.253.08:13:38.96$vc4f8/valo=4,832.99 2006.253.08:13:38.96#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.253.08:13:38.96#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.253.08:13:38.96#ibcon#ireg 17 cls_cnt 0 2006.253.08:13:38.96#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.253.08:13:38.96#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.253.08:13:38.96#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.253.08:13:38.96#ibcon#enter wrdev, iclass 33, count 0 2006.253.08:13:38.96#ibcon#first serial, iclass 33, count 0 2006.253.08:13:38.96#ibcon#enter sib2, iclass 33, count 0 2006.253.08:13:38.96#ibcon#flushed, iclass 33, count 0 2006.253.08:13:38.96#ibcon#about to write, iclass 33, count 0 2006.253.08:13:38.96#ibcon#wrote, iclass 33, count 0 2006.253.08:13:38.96#ibcon#about to read 3, iclass 33, count 0 2006.253.08:13:38.98#ibcon#read 3, iclass 33, count 0 2006.253.08:13:38.98#ibcon#about to read 4, iclass 33, count 0 2006.253.08:13:38.98#ibcon#read 4, iclass 33, count 0 2006.253.08:13:38.98#ibcon#about to read 5, iclass 33, count 0 2006.253.08:13:38.98#ibcon#read 5, iclass 33, count 0 2006.253.08:13:38.98#ibcon#about to read 6, iclass 33, count 0 2006.253.08:13:38.98#ibcon#read 6, iclass 33, count 0 2006.253.08:13:38.98#ibcon#end of sib2, iclass 33, count 0 2006.253.08:13:38.98#ibcon#*mode == 0, iclass 33, count 0 2006.253.08:13:38.98#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.253.08:13:38.98#ibcon#[26=FRQ=04,832.99\r\n] 2006.253.08:13:38.98#ibcon#*before write, iclass 33, count 0 2006.253.08:13:38.98#ibcon#enter sib2, iclass 33, count 0 2006.253.08:13:38.98#ibcon#flushed, iclass 33, count 0 2006.253.08:13:38.98#ibcon#about to write, iclass 33, count 0 2006.253.08:13:38.98#ibcon#wrote, iclass 33, count 0 2006.253.08:13:38.98#ibcon#about to read 3, iclass 33, count 0 2006.253.08:13:39.03#ibcon#read 3, iclass 33, count 0 2006.253.08:13:39.03#ibcon#about to read 4, iclass 33, count 0 2006.253.08:13:39.03#ibcon#read 4, iclass 33, count 0 2006.253.08:13:39.03#ibcon#about to read 5, iclass 33, count 0 2006.253.08:13:39.03#ibcon#read 5, iclass 33, count 0 2006.253.08:13:39.03#ibcon#about to read 6, iclass 33, count 0 2006.253.08:13:39.03#ibcon#read 6, iclass 33, count 0 2006.253.08:13:39.03#ibcon#end of sib2, iclass 33, count 0 2006.253.08:13:39.03#ibcon#*after write, iclass 33, count 0 2006.253.08:13:39.03#ibcon#*before return 0, iclass 33, count 0 2006.253.08:13:39.03#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.253.08:13:39.03#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.253.08:13:39.03#ibcon#about to clear, iclass 33 cls_cnt 0 2006.253.08:13:39.03#ibcon#cleared, iclass 33 cls_cnt 0 2006.253.08:13:39.03$vc4f8/va=4,7 2006.253.08:13:39.03#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.253.08:13:39.03#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.253.08:13:39.03#ibcon#ireg 11 cls_cnt 2 2006.253.08:13:39.03#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.253.08:13:39.08#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.253.08:13:39.08#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.253.08:13:39.08#ibcon#enter wrdev, iclass 35, count 2 2006.253.08:13:39.08#ibcon#first serial, iclass 35, count 2 2006.253.08:13:39.08#ibcon#enter sib2, iclass 35, count 2 2006.253.08:13:39.08#ibcon#flushed, iclass 35, count 2 2006.253.08:13:39.08#ibcon#about to write, iclass 35, count 2 2006.253.08:13:39.08#ibcon#wrote, iclass 35, count 2 2006.253.08:13:39.08#ibcon#about to read 3, iclass 35, count 2 2006.253.08:13:39.10#ibcon#read 3, iclass 35, count 2 2006.253.08:13:39.10#ibcon#about to read 4, iclass 35, count 2 2006.253.08:13:39.10#ibcon#read 4, iclass 35, count 2 2006.253.08:13:39.10#ibcon#about to read 5, iclass 35, count 2 2006.253.08:13:39.10#ibcon#read 5, iclass 35, count 2 2006.253.08:13:39.10#ibcon#about to read 6, iclass 35, count 2 2006.253.08:13:39.10#ibcon#read 6, iclass 35, count 2 2006.253.08:13:39.10#ibcon#end of sib2, iclass 35, count 2 2006.253.08:13:39.10#ibcon#*mode == 0, iclass 35, count 2 2006.253.08:13:39.10#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.253.08:13:39.10#ibcon#[25=AT04-07\r\n] 2006.253.08:13:39.10#ibcon#*before write, iclass 35, count 2 2006.253.08:13:39.10#ibcon#enter sib2, iclass 35, count 2 2006.253.08:13:39.10#ibcon#flushed, iclass 35, count 2 2006.253.08:13:39.10#ibcon#about to write, iclass 35, count 2 2006.253.08:13:39.10#ibcon#wrote, iclass 35, count 2 2006.253.08:13:39.10#ibcon#about to read 3, iclass 35, count 2 2006.253.08:13:39.13#ibcon#read 3, iclass 35, count 2 2006.253.08:13:39.13#ibcon#about to read 4, iclass 35, count 2 2006.253.08:13:39.13#ibcon#read 4, iclass 35, count 2 2006.253.08:13:39.13#ibcon#about to read 5, iclass 35, count 2 2006.253.08:13:39.13#ibcon#read 5, iclass 35, count 2 2006.253.08:13:39.13#ibcon#about to read 6, iclass 35, count 2 2006.253.08:13:39.13#ibcon#read 6, iclass 35, count 2 2006.253.08:13:39.13#ibcon#end of sib2, iclass 35, count 2 2006.253.08:13:39.13#ibcon#*after write, iclass 35, count 2 2006.253.08:13:39.13#ibcon#*before return 0, iclass 35, count 2 2006.253.08:13:39.13#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.253.08:13:39.13#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.253.08:13:39.13#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.253.08:13:39.13#ibcon#ireg 7 cls_cnt 0 2006.253.08:13:39.13#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.253.08:13:39.25#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.253.08:13:39.25#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.253.08:13:39.25#ibcon#enter wrdev, iclass 35, count 0 2006.253.08:13:39.25#ibcon#first serial, iclass 35, count 0 2006.253.08:13:39.25#ibcon#enter sib2, iclass 35, count 0 2006.253.08:13:39.25#ibcon#flushed, iclass 35, count 0 2006.253.08:13:39.25#ibcon#about to write, iclass 35, count 0 2006.253.08:13:39.25#ibcon#wrote, iclass 35, count 0 2006.253.08:13:39.25#ibcon#about to read 3, iclass 35, count 0 2006.253.08:13:39.27#ibcon#read 3, iclass 35, count 0 2006.253.08:13:39.27#ibcon#about to read 4, iclass 35, count 0 2006.253.08:13:39.27#ibcon#read 4, iclass 35, count 0 2006.253.08:13:39.27#ibcon#about to read 5, iclass 35, count 0 2006.253.08:13:39.27#ibcon#read 5, iclass 35, count 0 2006.253.08:13:39.27#ibcon#about to read 6, iclass 35, count 0 2006.253.08:13:39.27#ibcon#read 6, iclass 35, count 0 2006.253.08:13:39.27#ibcon#end of sib2, iclass 35, count 0 2006.253.08:13:39.27#ibcon#*mode == 0, iclass 35, count 0 2006.253.08:13:39.27#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.253.08:13:39.27#ibcon#[25=USB\r\n] 2006.253.08:13:39.27#ibcon#*before write, iclass 35, count 0 2006.253.08:13:39.27#ibcon#enter sib2, iclass 35, count 0 2006.253.08:13:39.27#ibcon#flushed, iclass 35, count 0 2006.253.08:13:39.27#ibcon#about to write, iclass 35, count 0 2006.253.08:13:39.27#ibcon#wrote, iclass 35, count 0 2006.253.08:13:39.27#ibcon#about to read 3, iclass 35, count 0 2006.253.08:13:39.30#ibcon#read 3, iclass 35, count 0 2006.253.08:13:39.30#ibcon#about to read 4, iclass 35, count 0 2006.253.08:13:39.30#ibcon#read 4, iclass 35, count 0 2006.253.08:13:39.30#ibcon#about to read 5, iclass 35, count 0 2006.253.08:13:39.30#ibcon#read 5, iclass 35, count 0 2006.253.08:13:39.30#ibcon#about to read 6, iclass 35, count 0 2006.253.08:13:39.30#ibcon#read 6, iclass 35, count 0 2006.253.08:13:39.30#ibcon#end of sib2, iclass 35, count 0 2006.253.08:13:39.30#ibcon#*after write, iclass 35, count 0 2006.253.08:13:39.30#ibcon#*before return 0, iclass 35, count 0 2006.253.08:13:39.30#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.253.08:13:39.30#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.253.08:13:39.30#ibcon#about to clear, iclass 35 cls_cnt 0 2006.253.08:13:39.30#ibcon#cleared, iclass 35 cls_cnt 0 2006.253.08:13:39.30$vc4f8/valo=5,652.99 2006.253.08:13:39.30#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.253.08:13:39.30#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.253.08:13:39.30#ibcon#ireg 17 cls_cnt 0 2006.253.08:13:39.30#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.253.08:13:39.30#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.253.08:13:39.30#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.253.08:13:39.30#ibcon#enter wrdev, iclass 37, count 0 2006.253.08:13:39.30#ibcon#first serial, iclass 37, count 0 2006.253.08:13:39.30#ibcon#enter sib2, iclass 37, count 0 2006.253.08:13:39.30#ibcon#flushed, iclass 37, count 0 2006.253.08:13:39.30#ibcon#about to write, iclass 37, count 0 2006.253.08:13:39.30#ibcon#wrote, iclass 37, count 0 2006.253.08:13:39.30#ibcon#about to read 3, iclass 37, count 0 2006.253.08:13:39.32#ibcon#read 3, iclass 37, count 0 2006.253.08:13:39.32#ibcon#about to read 4, iclass 37, count 0 2006.253.08:13:39.32#ibcon#read 4, iclass 37, count 0 2006.253.08:13:39.32#ibcon#about to read 5, iclass 37, count 0 2006.253.08:13:39.32#ibcon#read 5, iclass 37, count 0 2006.253.08:13:39.32#ibcon#about to read 6, iclass 37, count 0 2006.253.08:13:39.32#ibcon#read 6, iclass 37, count 0 2006.253.08:13:39.32#ibcon#end of sib2, iclass 37, count 0 2006.253.08:13:39.32#ibcon#*mode == 0, iclass 37, count 0 2006.253.08:13:39.32#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.253.08:13:39.32#ibcon#[26=FRQ=05,652.99\r\n] 2006.253.08:13:39.32#ibcon#*before write, iclass 37, count 0 2006.253.08:13:39.32#ibcon#enter sib2, iclass 37, count 0 2006.253.08:13:39.32#ibcon#flushed, iclass 37, count 0 2006.253.08:13:39.32#ibcon#about to write, iclass 37, count 0 2006.253.08:13:39.32#ibcon#wrote, iclass 37, count 0 2006.253.08:13:39.32#ibcon#about to read 3, iclass 37, count 0 2006.253.08:13:39.36#ibcon#read 3, iclass 37, count 0 2006.253.08:13:39.36#ibcon#about to read 4, iclass 37, count 0 2006.253.08:13:39.36#ibcon#read 4, iclass 37, count 0 2006.253.08:13:39.36#ibcon#about to read 5, iclass 37, count 0 2006.253.08:13:39.36#ibcon#read 5, iclass 37, count 0 2006.253.08:13:39.36#ibcon#about to read 6, iclass 37, count 0 2006.253.08:13:39.36#ibcon#read 6, iclass 37, count 0 2006.253.08:13:39.36#ibcon#end of sib2, iclass 37, count 0 2006.253.08:13:39.36#ibcon#*after write, iclass 37, count 0 2006.253.08:13:39.36#ibcon#*before return 0, iclass 37, count 0 2006.253.08:13:39.36#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.253.08:13:39.36#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.253.08:13:39.36#ibcon#about to clear, iclass 37 cls_cnt 0 2006.253.08:13:39.36#ibcon#cleared, iclass 37 cls_cnt 0 2006.253.08:13:39.36$vc4f8/va=5,7 2006.253.08:13:39.36#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.253.08:13:39.36#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.253.08:13:39.36#ibcon#ireg 11 cls_cnt 2 2006.253.08:13:39.36#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.253.08:13:39.42#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.253.08:13:39.42#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.253.08:13:39.42#ibcon#enter wrdev, iclass 39, count 2 2006.253.08:13:39.42#ibcon#first serial, iclass 39, count 2 2006.253.08:13:39.42#ibcon#enter sib2, iclass 39, count 2 2006.253.08:13:39.42#ibcon#flushed, iclass 39, count 2 2006.253.08:13:39.42#ibcon#about to write, iclass 39, count 2 2006.253.08:13:39.42#ibcon#wrote, iclass 39, count 2 2006.253.08:13:39.42#ibcon#about to read 3, iclass 39, count 2 2006.253.08:13:39.44#ibcon#read 3, iclass 39, count 2 2006.253.08:13:39.44#ibcon#about to read 4, iclass 39, count 2 2006.253.08:13:39.44#ibcon#read 4, iclass 39, count 2 2006.253.08:13:39.44#ibcon#about to read 5, iclass 39, count 2 2006.253.08:13:39.44#ibcon#read 5, iclass 39, count 2 2006.253.08:13:39.44#ibcon#about to read 6, iclass 39, count 2 2006.253.08:13:39.44#ibcon#read 6, iclass 39, count 2 2006.253.08:13:39.44#ibcon#end of sib2, iclass 39, count 2 2006.253.08:13:39.44#ibcon#*mode == 0, iclass 39, count 2 2006.253.08:13:39.44#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.253.08:13:39.44#ibcon#[25=AT05-07\r\n] 2006.253.08:13:39.44#ibcon#*before write, iclass 39, count 2 2006.253.08:13:39.44#ibcon#enter sib2, iclass 39, count 2 2006.253.08:13:39.44#ibcon#flushed, iclass 39, count 2 2006.253.08:13:39.44#ibcon#about to write, iclass 39, count 2 2006.253.08:13:39.44#ibcon#wrote, iclass 39, count 2 2006.253.08:13:39.44#ibcon#about to read 3, iclass 39, count 2 2006.253.08:13:39.47#ibcon#read 3, iclass 39, count 2 2006.253.08:13:39.47#ibcon#about to read 4, iclass 39, count 2 2006.253.08:13:39.47#ibcon#read 4, iclass 39, count 2 2006.253.08:13:39.47#ibcon#about to read 5, iclass 39, count 2 2006.253.08:13:39.47#ibcon#read 5, iclass 39, count 2 2006.253.08:13:39.47#ibcon#about to read 6, iclass 39, count 2 2006.253.08:13:39.47#ibcon#read 6, iclass 39, count 2 2006.253.08:13:39.47#ibcon#end of sib2, iclass 39, count 2 2006.253.08:13:39.47#ibcon#*after write, iclass 39, count 2 2006.253.08:13:39.47#ibcon#*before return 0, iclass 39, count 2 2006.253.08:13:39.47#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.253.08:13:39.47#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.253.08:13:39.47#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.253.08:13:39.47#ibcon#ireg 7 cls_cnt 0 2006.253.08:13:39.47#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.253.08:13:39.59#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.253.08:13:39.59#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.253.08:13:39.59#ibcon#enter wrdev, iclass 39, count 0 2006.253.08:13:39.59#ibcon#first serial, iclass 39, count 0 2006.253.08:13:39.59#ibcon#enter sib2, iclass 39, count 0 2006.253.08:13:39.59#ibcon#flushed, iclass 39, count 0 2006.253.08:13:39.59#ibcon#about to write, iclass 39, count 0 2006.253.08:13:39.59#ibcon#wrote, iclass 39, count 0 2006.253.08:13:39.59#ibcon#about to read 3, iclass 39, count 0 2006.253.08:13:39.61#ibcon#read 3, iclass 39, count 0 2006.253.08:13:39.61#ibcon#about to read 4, iclass 39, count 0 2006.253.08:13:39.61#ibcon#read 4, iclass 39, count 0 2006.253.08:13:39.61#ibcon#about to read 5, iclass 39, count 0 2006.253.08:13:39.61#ibcon#read 5, iclass 39, count 0 2006.253.08:13:39.61#ibcon#about to read 6, iclass 39, count 0 2006.253.08:13:39.61#ibcon#read 6, iclass 39, count 0 2006.253.08:13:39.61#ibcon#end of sib2, iclass 39, count 0 2006.253.08:13:39.61#ibcon#*mode == 0, iclass 39, count 0 2006.253.08:13:39.61#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.253.08:13:39.61#ibcon#[25=USB\r\n] 2006.253.08:13:39.61#ibcon#*before write, iclass 39, count 0 2006.253.08:13:39.61#ibcon#enter sib2, iclass 39, count 0 2006.253.08:13:39.61#ibcon#flushed, iclass 39, count 0 2006.253.08:13:39.61#ibcon#about to write, iclass 39, count 0 2006.253.08:13:39.61#ibcon#wrote, iclass 39, count 0 2006.253.08:13:39.61#ibcon#about to read 3, iclass 39, count 0 2006.253.08:13:39.64#ibcon#read 3, iclass 39, count 0 2006.253.08:13:39.64#ibcon#about to read 4, iclass 39, count 0 2006.253.08:13:39.64#ibcon#read 4, iclass 39, count 0 2006.253.08:13:39.64#ibcon#about to read 5, iclass 39, count 0 2006.253.08:13:39.64#ibcon#read 5, iclass 39, count 0 2006.253.08:13:39.64#ibcon#about to read 6, iclass 39, count 0 2006.253.08:13:39.64#ibcon#read 6, iclass 39, count 0 2006.253.08:13:39.64#ibcon#end of sib2, iclass 39, count 0 2006.253.08:13:39.64#ibcon#*after write, iclass 39, count 0 2006.253.08:13:39.64#ibcon#*before return 0, iclass 39, count 0 2006.253.08:13:39.64#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.253.08:13:39.64#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.253.08:13:39.64#ibcon#about to clear, iclass 39 cls_cnt 0 2006.253.08:13:39.64#ibcon#cleared, iclass 39 cls_cnt 0 2006.253.08:13:39.64$vc4f8/valo=6,772.99 2006.253.08:13:39.64#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.253.08:13:39.64#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.253.08:13:39.64#ibcon#ireg 17 cls_cnt 0 2006.253.08:13:39.64#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.253.08:13:39.64#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.253.08:13:39.64#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.253.08:13:39.64#ibcon#enter wrdev, iclass 3, count 0 2006.253.08:13:39.64#ibcon#first serial, iclass 3, count 0 2006.253.08:13:39.64#ibcon#enter sib2, iclass 3, count 0 2006.253.08:13:39.64#ibcon#flushed, iclass 3, count 0 2006.253.08:13:39.64#ibcon#about to write, iclass 3, count 0 2006.253.08:13:39.64#ibcon#wrote, iclass 3, count 0 2006.253.08:13:39.64#ibcon#about to read 3, iclass 3, count 0 2006.253.08:13:39.66#ibcon#read 3, iclass 3, count 0 2006.253.08:13:39.66#ibcon#about to read 4, iclass 3, count 0 2006.253.08:13:39.66#ibcon#read 4, iclass 3, count 0 2006.253.08:13:39.66#ibcon#about to read 5, iclass 3, count 0 2006.253.08:13:39.66#ibcon#read 5, iclass 3, count 0 2006.253.08:13:39.66#ibcon#about to read 6, iclass 3, count 0 2006.253.08:13:39.66#ibcon#read 6, iclass 3, count 0 2006.253.08:13:39.66#ibcon#end of sib2, iclass 3, count 0 2006.253.08:13:39.66#ibcon#*mode == 0, iclass 3, count 0 2006.253.08:13:39.66#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.253.08:13:39.66#ibcon#[26=FRQ=06,772.99\r\n] 2006.253.08:13:39.66#ibcon#*before write, iclass 3, count 0 2006.253.08:13:39.66#ibcon#enter sib2, iclass 3, count 0 2006.253.08:13:39.66#ibcon#flushed, iclass 3, count 0 2006.253.08:13:39.66#ibcon#about to write, iclass 3, count 0 2006.253.08:13:39.66#ibcon#wrote, iclass 3, count 0 2006.253.08:13:39.66#ibcon#about to read 3, iclass 3, count 0 2006.253.08:13:39.71#ibcon#read 3, iclass 3, count 0 2006.253.08:13:39.71#ibcon#about to read 4, iclass 3, count 0 2006.253.08:13:39.71#ibcon#read 4, iclass 3, count 0 2006.253.08:13:39.71#ibcon#about to read 5, iclass 3, count 0 2006.253.08:13:39.71#ibcon#read 5, iclass 3, count 0 2006.253.08:13:39.71#ibcon#about to read 6, iclass 3, count 0 2006.253.08:13:39.71#ibcon#read 6, iclass 3, count 0 2006.253.08:13:39.71#ibcon#end of sib2, iclass 3, count 0 2006.253.08:13:39.71#ibcon#*after write, iclass 3, count 0 2006.253.08:13:39.71#ibcon#*before return 0, iclass 3, count 0 2006.253.08:13:39.71#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.253.08:13:39.71#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.253.08:13:39.71#ibcon#about to clear, iclass 3 cls_cnt 0 2006.253.08:13:39.71#ibcon#cleared, iclass 3 cls_cnt 0 2006.253.08:13:39.71$vc4f8/va=6,7 2006.253.08:13:39.71#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.253.08:13:39.71#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.253.08:13:39.71#ibcon#ireg 11 cls_cnt 2 2006.253.08:13:39.71#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.253.08:13:39.76#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.253.08:13:39.76#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.253.08:13:39.76#ibcon#enter wrdev, iclass 5, count 2 2006.253.08:13:39.76#ibcon#first serial, iclass 5, count 2 2006.253.08:13:39.76#ibcon#enter sib2, iclass 5, count 2 2006.253.08:13:39.76#ibcon#flushed, iclass 5, count 2 2006.253.08:13:39.76#ibcon#about to write, iclass 5, count 2 2006.253.08:13:39.76#ibcon#wrote, iclass 5, count 2 2006.253.08:13:39.76#ibcon#about to read 3, iclass 5, count 2 2006.253.08:13:39.78#ibcon#read 3, iclass 5, count 2 2006.253.08:13:39.78#ibcon#about to read 4, iclass 5, count 2 2006.253.08:13:39.78#ibcon#read 4, iclass 5, count 2 2006.253.08:13:39.78#ibcon#about to read 5, iclass 5, count 2 2006.253.08:13:39.78#ibcon#read 5, iclass 5, count 2 2006.253.08:13:39.78#ibcon#about to read 6, iclass 5, count 2 2006.253.08:13:39.78#ibcon#read 6, iclass 5, count 2 2006.253.08:13:39.78#ibcon#end of sib2, iclass 5, count 2 2006.253.08:13:39.78#ibcon#*mode == 0, iclass 5, count 2 2006.253.08:13:39.78#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.253.08:13:39.78#ibcon#[25=AT06-07\r\n] 2006.253.08:13:39.78#ibcon#*before write, iclass 5, count 2 2006.253.08:13:39.78#ibcon#enter sib2, iclass 5, count 2 2006.253.08:13:39.78#ibcon#flushed, iclass 5, count 2 2006.253.08:13:39.78#ibcon#about to write, iclass 5, count 2 2006.253.08:13:39.78#ibcon#wrote, iclass 5, count 2 2006.253.08:13:39.78#ibcon#about to read 3, iclass 5, count 2 2006.253.08:13:39.81#ibcon#read 3, iclass 5, count 2 2006.253.08:13:39.81#ibcon#about to read 4, iclass 5, count 2 2006.253.08:13:39.81#ibcon#read 4, iclass 5, count 2 2006.253.08:13:39.81#ibcon#about to read 5, iclass 5, count 2 2006.253.08:13:39.81#ibcon#read 5, iclass 5, count 2 2006.253.08:13:39.81#ibcon#about to read 6, iclass 5, count 2 2006.253.08:13:39.81#ibcon#read 6, iclass 5, count 2 2006.253.08:13:39.81#ibcon#end of sib2, iclass 5, count 2 2006.253.08:13:39.81#ibcon#*after write, iclass 5, count 2 2006.253.08:13:39.81#ibcon#*before return 0, iclass 5, count 2 2006.253.08:13:39.81#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.253.08:13:39.81#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.253.08:13:39.81#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.253.08:13:39.81#ibcon#ireg 7 cls_cnt 0 2006.253.08:13:39.81#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.253.08:13:39.93#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.253.08:13:39.93#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.253.08:13:39.93#ibcon#enter wrdev, iclass 5, count 0 2006.253.08:13:39.93#ibcon#first serial, iclass 5, count 0 2006.253.08:13:39.93#ibcon#enter sib2, iclass 5, count 0 2006.253.08:13:39.93#ibcon#flushed, iclass 5, count 0 2006.253.08:13:39.93#ibcon#about to write, iclass 5, count 0 2006.253.08:13:39.93#ibcon#wrote, iclass 5, count 0 2006.253.08:13:39.93#ibcon#about to read 3, iclass 5, count 0 2006.253.08:13:39.95#ibcon#read 3, iclass 5, count 0 2006.253.08:13:39.95#ibcon#about to read 4, iclass 5, count 0 2006.253.08:13:39.95#ibcon#read 4, iclass 5, count 0 2006.253.08:13:39.95#ibcon#about to read 5, iclass 5, count 0 2006.253.08:13:39.95#ibcon#read 5, iclass 5, count 0 2006.253.08:13:39.95#ibcon#about to read 6, iclass 5, count 0 2006.253.08:13:39.95#ibcon#read 6, iclass 5, count 0 2006.253.08:13:39.95#ibcon#end of sib2, iclass 5, count 0 2006.253.08:13:39.95#ibcon#*mode == 0, iclass 5, count 0 2006.253.08:13:39.95#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.253.08:13:39.95#ibcon#[25=USB\r\n] 2006.253.08:13:39.95#ibcon#*before write, iclass 5, count 0 2006.253.08:13:39.95#ibcon#enter sib2, iclass 5, count 0 2006.253.08:13:39.95#ibcon#flushed, iclass 5, count 0 2006.253.08:13:39.95#ibcon#about to write, iclass 5, count 0 2006.253.08:13:39.95#ibcon#wrote, iclass 5, count 0 2006.253.08:13:39.95#ibcon#about to read 3, iclass 5, count 0 2006.253.08:13:39.98#ibcon#read 3, iclass 5, count 0 2006.253.08:13:39.98#ibcon#about to read 4, iclass 5, count 0 2006.253.08:13:39.98#ibcon#read 4, iclass 5, count 0 2006.253.08:13:39.98#ibcon#about to read 5, iclass 5, count 0 2006.253.08:13:39.98#ibcon#read 5, iclass 5, count 0 2006.253.08:13:39.98#ibcon#about to read 6, iclass 5, count 0 2006.253.08:13:39.98#ibcon#read 6, iclass 5, count 0 2006.253.08:13:39.98#ibcon#end of sib2, iclass 5, count 0 2006.253.08:13:39.98#ibcon#*after write, iclass 5, count 0 2006.253.08:13:39.98#ibcon#*before return 0, iclass 5, count 0 2006.253.08:13:39.98#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.253.08:13:39.98#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.253.08:13:39.98#ibcon#about to clear, iclass 5 cls_cnt 0 2006.253.08:13:39.98#ibcon#cleared, iclass 5 cls_cnt 0 2006.253.08:13:39.98$vc4f8/valo=7,832.99 2006.253.08:13:39.98#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.253.08:13:39.98#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.253.08:13:39.98#ibcon#ireg 17 cls_cnt 0 2006.253.08:13:39.98#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.253.08:13:39.98#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.253.08:13:39.98#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.253.08:13:39.98#ibcon#enter wrdev, iclass 7, count 0 2006.253.08:13:39.98#ibcon#first serial, iclass 7, count 0 2006.253.08:13:39.98#ibcon#enter sib2, iclass 7, count 0 2006.253.08:13:39.98#ibcon#flushed, iclass 7, count 0 2006.253.08:13:39.98#ibcon#about to write, iclass 7, count 0 2006.253.08:13:39.98#ibcon#wrote, iclass 7, count 0 2006.253.08:13:39.98#ibcon#about to read 3, iclass 7, count 0 2006.253.08:13:40.00#ibcon#read 3, iclass 7, count 0 2006.253.08:13:40.00#ibcon#about to read 4, iclass 7, count 0 2006.253.08:13:40.00#ibcon#read 4, iclass 7, count 0 2006.253.08:13:40.00#ibcon#about to read 5, iclass 7, count 0 2006.253.08:13:40.00#ibcon#read 5, iclass 7, count 0 2006.253.08:13:40.00#ibcon#about to read 6, iclass 7, count 0 2006.253.08:13:40.00#ibcon#read 6, iclass 7, count 0 2006.253.08:13:40.00#ibcon#end of sib2, iclass 7, count 0 2006.253.08:13:40.00#ibcon#*mode == 0, iclass 7, count 0 2006.253.08:13:40.00#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.253.08:13:40.00#ibcon#[26=FRQ=07,832.99\r\n] 2006.253.08:13:40.00#ibcon#*before write, iclass 7, count 0 2006.253.08:13:40.00#ibcon#enter sib2, iclass 7, count 0 2006.253.08:13:40.00#ibcon#flushed, iclass 7, count 0 2006.253.08:13:40.00#ibcon#about to write, iclass 7, count 0 2006.253.08:13:40.00#ibcon#wrote, iclass 7, count 0 2006.253.08:13:40.00#ibcon#about to read 3, iclass 7, count 0 2006.253.08:13:40.04#ibcon#read 3, iclass 7, count 0 2006.253.08:13:40.04#ibcon#about to read 4, iclass 7, count 0 2006.253.08:13:40.04#ibcon#read 4, iclass 7, count 0 2006.253.08:13:40.04#ibcon#about to read 5, iclass 7, count 0 2006.253.08:13:40.04#ibcon#read 5, iclass 7, count 0 2006.253.08:13:40.04#ibcon#about to read 6, iclass 7, count 0 2006.253.08:13:40.04#ibcon#read 6, iclass 7, count 0 2006.253.08:13:40.04#ibcon#end of sib2, iclass 7, count 0 2006.253.08:13:40.04#ibcon#*after write, iclass 7, count 0 2006.253.08:13:40.04#ibcon#*before return 0, iclass 7, count 0 2006.253.08:13:40.04#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.253.08:13:40.04#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.253.08:13:40.04#ibcon#about to clear, iclass 7 cls_cnt 0 2006.253.08:13:40.04#ibcon#cleared, iclass 7 cls_cnt 0 2006.253.08:13:40.04$vc4f8/va=7,7 2006.253.08:13:40.04#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.253.08:13:40.04#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.253.08:13:40.04#ibcon#ireg 11 cls_cnt 2 2006.253.08:13:40.04#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.253.08:13:40.10#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.253.08:13:40.10#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.253.08:13:40.10#ibcon#enter wrdev, iclass 11, count 2 2006.253.08:13:40.10#ibcon#first serial, iclass 11, count 2 2006.253.08:13:40.10#ibcon#enter sib2, iclass 11, count 2 2006.253.08:13:40.10#ibcon#flushed, iclass 11, count 2 2006.253.08:13:40.10#ibcon#about to write, iclass 11, count 2 2006.253.08:13:40.10#ibcon#wrote, iclass 11, count 2 2006.253.08:13:40.10#ibcon#about to read 3, iclass 11, count 2 2006.253.08:13:40.12#ibcon#read 3, iclass 11, count 2 2006.253.08:13:40.12#ibcon#about to read 4, iclass 11, count 2 2006.253.08:13:40.12#ibcon#read 4, iclass 11, count 2 2006.253.08:13:40.12#ibcon#about to read 5, iclass 11, count 2 2006.253.08:13:40.12#ibcon#read 5, iclass 11, count 2 2006.253.08:13:40.12#ibcon#about to read 6, iclass 11, count 2 2006.253.08:13:40.12#ibcon#read 6, iclass 11, count 2 2006.253.08:13:40.12#ibcon#end of sib2, iclass 11, count 2 2006.253.08:13:40.12#ibcon#*mode == 0, iclass 11, count 2 2006.253.08:13:40.12#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.253.08:13:40.12#ibcon#[25=AT07-07\r\n] 2006.253.08:13:40.12#ibcon#*before write, iclass 11, count 2 2006.253.08:13:40.12#ibcon#enter sib2, iclass 11, count 2 2006.253.08:13:40.12#ibcon#flushed, iclass 11, count 2 2006.253.08:13:40.12#ibcon#about to write, iclass 11, count 2 2006.253.08:13:40.12#ibcon#wrote, iclass 11, count 2 2006.253.08:13:40.12#ibcon#about to read 3, iclass 11, count 2 2006.253.08:13:40.15#ibcon#read 3, iclass 11, count 2 2006.253.08:13:40.15#ibcon#about to read 4, iclass 11, count 2 2006.253.08:13:40.15#ibcon#read 4, iclass 11, count 2 2006.253.08:13:40.15#ibcon#about to read 5, iclass 11, count 2 2006.253.08:13:40.15#ibcon#read 5, iclass 11, count 2 2006.253.08:13:40.15#ibcon#about to read 6, iclass 11, count 2 2006.253.08:13:40.15#ibcon#read 6, iclass 11, count 2 2006.253.08:13:40.15#ibcon#end of sib2, iclass 11, count 2 2006.253.08:13:40.15#ibcon#*after write, iclass 11, count 2 2006.253.08:13:40.15#ibcon#*before return 0, iclass 11, count 2 2006.253.08:13:40.15#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.253.08:13:40.15#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.253.08:13:40.15#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.253.08:13:40.15#ibcon#ireg 7 cls_cnt 0 2006.253.08:13:40.15#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.253.08:13:40.27#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.253.08:13:40.27#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.253.08:13:40.27#ibcon#enter wrdev, iclass 11, count 0 2006.253.08:13:40.27#ibcon#first serial, iclass 11, count 0 2006.253.08:13:40.27#ibcon#enter sib2, iclass 11, count 0 2006.253.08:13:40.27#ibcon#flushed, iclass 11, count 0 2006.253.08:13:40.27#ibcon#about to write, iclass 11, count 0 2006.253.08:13:40.27#ibcon#wrote, iclass 11, count 0 2006.253.08:13:40.27#ibcon#about to read 3, iclass 11, count 0 2006.253.08:13:40.29#ibcon#read 3, iclass 11, count 0 2006.253.08:13:40.29#ibcon#about to read 4, iclass 11, count 0 2006.253.08:13:40.29#ibcon#read 4, iclass 11, count 0 2006.253.08:13:40.29#ibcon#about to read 5, iclass 11, count 0 2006.253.08:13:40.29#ibcon#read 5, iclass 11, count 0 2006.253.08:13:40.29#ibcon#about to read 6, iclass 11, count 0 2006.253.08:13:40.29#ibcon#read 6, iclass 11, count 0 2006.253.08:13:40.29#ibcon#end of sib2, iclass 11, count 0 2006.253.08:13:40.29#ibcon#*mode == 0, iclass 11, count 0 2006.253.08:13:40.29#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.253.08:13:40.29#ibcon#[25=USB\r\n] 2006.253.08:13:40.29#ibcon#*before write, iclass 11, count 0 2006.253.08:13:40.29#ibcon#enter sib2, iclass 11, count 0 2006.253.08:13:40.29#ibcon#flushed, iclass 11, count 0 2006.253.08:13:40.29#ibcon#about to write, iclass 11, count 0 2006.253.08:13:40.29#ibcon#wrote, iclass 11, count 0 2006.253.08:13:40.29#ibcon#about to read 3, iclass 11, count 0 2006.253.08:13:40.32#ibcon#read 3, iclass 11, count 0 2006.253.08:13:40.32#ibcon#about to read 4, iclass 11, count 0 2006.253.08:13:40.32#ibcon#read 4, iclass 11, count 0 2006.253.08:13:40.32#ibcon#about to read 5, iclass 11, count 0 2006.253.08:13:40.32#ibcon#read 5, iclass 11, count 0 2006.253.08:13:40.32#ibcon#about to read 6, iclass 11, count 0 2006.253.08:13:40.32#ibcon#read 6, iclass 11, count 0 2006.253.08:13:40.32#ibcon#end of sib2, iclass 11, count 0 2006.253.08:13:40.32#ibcon#*after write, iclass 11, count 0 2006.253.08:13:40.32#ibcon#*before return 0, iclass 11, count 0 2006.253.08:13:40.32#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.253.08:13:40.32#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.253.08:13:40.32#ibcon#about to clear, iclass 11 cls_cnt 0 2006.253.08:13:40.32#ibcon#cleared, iclass 11 cls_cnt 0 2006.253.08:13:40.32$vc4f8/valo=8,852.99 2006.253.08:13:40.32#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.253.08:13:40.32#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.253.08:13:40.32#ibcon#ireg 17 cls_cnt 0 2006.253.08:13:40.32#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.253.08:13:40.32#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.253.08:13:40.32#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.253.08:13:40.32#ibcon#enter wrdev, iclass 13, count 0 2006.253.08:13:40.32#ibcon#first serial, iclass 13, count 0 2006.253.08:13:40.32#ibcon#enter sib2, iclass 13, count 0 2006.253.08:13:40.32#ibcon#flushed, iclass 13, count 0 2006.253.08:13:40.32#ibcon#about to write, iclass 13, count 0 2006.253.08:13:40.32#ibcon#wrote, iclass 13, count 0 2006.253.08:13:40.32#ibcon#about to read 3, iclass 13, count 0 2006.253.08:13:40.34#ibcon#read 3, iclass 13, count 0 2006.253.08:13:40.34#ibcon#about to read 4, iclass 13, count 0 2006.253.08:13:40.34#ibcon#read 4, iclass 13, count 0 2006.253.08:13:40.34#ibcon#about to read 5, iclass 13, count 0 2006.253.08:13:40.34#ibcon#read 5, iclass 13, count 0 2006.253.08:13:40.34#ibcon#about to read 6, iclass 13, count 0 2006.253.08:13:40.34#ibcon#read 6, iclass 13, count 0 2006.253.08:13:40.34#ibcon#end of sib2, iclass 13, count 0 2006.253.08:13:40.34#ibcon#*mode == 0, iclass 13, count 0 2006.253.08:13:40.34#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.253.08:13:40.34#ibcon#[26=FRQ=08,852.99\r\n] 2006.253.08:13:40.34#ibcon#*before write, iclass 13, count 0 2006.253.08:13:40.34#ibcon#enter sib2, iclass 13, count 0 2006.253.08:13:40.34#ibcon#flushed, iclass 13, count 0 2006.253.08:13:40.34#ibcon#about to write, iclass 13, count 0 2006.253.08:13:40.34#ibcon#wrote, iclass 13, count 0 2006.253.08:13:40.34#ibcon#about to read 3, iclass 13, count 0 2006.253.08:13:40.38#ibcon#read 3, iclass 13, count 0 2006.253.08:13:40.38#ibcon#about to read 4, iclass 13, count 0 2006.253.08:13:40.38#ibcon#read 4, iclass 13, count 0 2006.253.08:13:40.38#ibcon#about to read 5, iclass 13, count 0 2006.253.08:13:40.38#ibcon#read 5, iclass 13, count 0 2006.253.08:13:40.38#ibcon#about to read 6, iclass 13, count 0 2006.253.08:13:40.38#ibcon#read 6, iclass 13, count 0 2006.253.08:13:40.38#ibcon#end of sib2, iclass 13, count 0 2006.253.08:13:40.38#ibcon#*after write, iclass 13, count 0 2006.253.08:13:40.38#ibcon#*before return 0, iclass 13, count 0 2006.253.08:13:40.38#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.253.08:13:40.38#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.253.08:13:40.38#ibcon#about to clear, iclass 13 cls_cnt 0 2006.253.08:13:40.38#ibcon#cleared, iclass 13 cls_cnt 0 2006.253.08:13:40.38$vc4f8/va=8,7 2006.253.08:13:40.38#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.253.08:13:40.38#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.253.08:13:40.38#ibcon#ireg 11 cls_cnt 2 2006.253.08:13:40.38#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.253.08:13:40.44#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.253.08:13:40.44#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.253.08:13:40.44#ibcon#enter wrdev, iclass 15, count 2 2006.253.08:13:40.44#ibcon#first serial, iclass 15, count 2 2006.253.08:13:40.44#ibcon#enter sib2, iclass 15, count 2 2006.253.08:13:40.44#ibcon#flushed, iclass 15, count 2 2006.253.08:13:40.44#ibcon#about to write, iclass 15, count 2 2006.253.08:13:40.44#ibcon#wrote, iclass 15, count 2 2006.253.08:13:40.44#ibcon#about to read 3, iclass 15, count 2 2006.253.08:13:40.46#ibcon#read 3, iclass 15, count 2 2006.253.08:13:40.46#ibcon#about to read 4, iclass 15, count 2 2006.253.08:13:40.46#ibcon#read 4, iclass 15, count 2 2006.253.08:13:40.46#ibcon#about to read 5, iclass 15, count 2 2006.253.08:13:40.46#ibcon#read 5, iclass 15, count 2 2006.253.08:13:40.46#ibcon#about to read 6, iclass 15, count 2 2006.253.08:13:40.46#ibcon#read 6, iclass 15, count 2 2006.253.08:13:40.46#ibcon#end of sib2, iclass 15, count 2 2006.253.08:13:40.46#ibcon#*mode == 0, iclass 15, count 2 2006.253.08:13:40.46#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.253.08:13:40.46#ibcon#[25=AT08-07\r\n] 2006.253.08:13:40.46#ibcon#*before write, iclass 15, count 2 2006.253.08:13:40.46#ibcon#enter sib2, iclass 15, count 2 2006.253.08:13:40.46#ibcon#flushed, iclass 15, count 2 2006.253.08:13:40.46#ibcon#about to write, iclass 15, count 2 2006.253.08:13:40.46#ibcon#wrote, iclass 15, count 2 2006.253.08:13:40.46#ibcon#about to read 3, iclass 15, count 2 2006.253.08:13:40.49#ibcon#read 3, iclass 15, count 2 2006.253.08:13:40.49#ibcon#about to read 4, iclass 15, count 2 2006.253.08:13:40.49#ibcon#read 4, iclass 15, count 2 2006.253.08:13:40.49#ibcon#about to read 5, iclass 15, count 2 2006.253.08:13:40.49#ibcon#read 5, iclass 15, count 2 2006.253.08:13:40.49#ibcon#about to read 6, iclass 15, count 2 2006.253.08:13:40.49#ibcon#read 6, iclass 15, count 2 2006.253.08:13:40.49#ibcon#end of sib2, iclass 15, count 2 2006.253.08:13:40.49#ibcon#*after write, iclass 15, count 2 2006.253.08:13:40.49#ibcon#*before return 0, iclass 15, count 2 2006.253.08:13:40.49#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.253.08:13:40.49#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.253.08:13:40.49#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.253.08:13:40.49#ibcon#ireg 7 cls_cnt 0 2006.253.08:13:40.49#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.253.08:13:40.61#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.253.08:13:40.61#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.253.08:13:40.61#ibcon#enter wrdev, iclass 15, count 0 2006.253.08:13:40.61#ibcon#first serial, iclass 15, count 0 2006.253.08:13:40.61#ibcon#enter sib2, iclass 15, count 0 2006.253.08:13:40.61#ibcon#flushed, iclass 15, count 0 2006.253.08:13:40.61#ibcon#about to write, iclass 15, count 0 2006.253.08:13:40.61#ibcon#wrote, iclass 15, count 0 2006.253.08:13:40.61#ibcon#about to read 3, iclass 15, count 0 2006.253.08:13:40.63#ibcon#read 3, iclass 15, count 0 2006.253.08:13:40.63#ibcon#about to read 4, iclass 15, count 0 2006.253.08:13:40.63#ibcon#read 4, iclass 15, count 0 2006.253.08:13:40.63#ibcon#about to read 5, iclass 15, count 0 2006.253.08:13:40.63#ibcon#read 5, iclass 15, count 0 2006.253.08:13:40.63#ibcon#about to read 6, iclass 15, count 0 2006.253.08:13:40.63#ibcon#read 6, iclass 15, count 0 2006.253.08:13:40.63#ibcon#end of sib2, iclass 15, count 0 2006.253.08:13:40.63#ibcon#*mode == 0, iclass 15, count 0 2006.253.08:13:40.63#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.253.08:13:40.63#ibcon#[25=USB\r\n] 2006.253.08:13:40.63#ibcon#*before write, iclass 15, count 0 2006.253.08:13:40.63#ibcon#enter sib2, iclass 15, count 0 2006.253.08:13:40.63#ibcon#flushed, iclass 15, count 0 2006.253.08:13:40.63#ibcon#about to write, iclass 15, count 0 2006.253.08:13:40.63#ibcon#wrote, iclass 15, count 0 2006.253.08:13:40.63#ibcon#about to read 3, iclass 15, count 0 2006.253.08:13:40.66#ibcon#read 3, iclass 15, count 0 2006.253.08:13:40.66#ibcon#about to read 4, iclass 15, count 0 2006.253.08:13:40.66#ibcon#read 4, iclass 15, count 0 2006.253.08:13:40.66#ibcon#about to read 5, iclass 15, count 0 2006.253.08:13:40.66#ibcon#read 5, iclass 15, count 0 2006.253.08:13:40.66#ibcon#about to read 6, iclass 15, count 0 2006.253.08:13:40.66#ibcon#read 6, iclass 15, count 0 2006.253.08:13:40.66#ibcon#end of sib2, iclass 15, count 0 2006.253.08:13:40.66#ibcon#*after write, iclass 15, count 0 2006.253.08:13:40.66#ibcon#*before return 0, iclass 15, count 0 2006.253.08:13:40.66#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.253.08:13:40.66#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.253.08:13:40.66#ibcon#about to clear, iclass 15 cls_cnt 0 2006.253.08:13:40.66#ibcon#cleared, iclass 15 cls_cnt 0 2006.253.08:13:40.66$vc4f8/vblo=1,632.99 2006.253.08:13:40.66#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.253.08:13:40.66#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.253.08:13:40.66#ibcon#ireg 17 cls_cnt 0 2006.253.08:13:40.66#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.253.08:13:40.66#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.253.08:13:40.66#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.253.08:13:40.66#ibcon#enter wrdev, iclass 17, count 0 2006.253.08:13:40.66#ibcon#first serial, iclass 17, count 0 2006.253.08:13:40.66#ibcon#enter sib2, iclass 17, count 0 2006.253.08:13:40.66#ibcon#flushed, iclass 17, count 0 2006.253.08:13:40.66#ibcon#about to write, iclass 17, count 0 2006.253.08:13:40.66#ibcon#wrote, iclass 17, count 0 2006.253.08:13:40.66#ibcon#about to read 3, iclass 17, count 0 2006.253.08:13:40.68#ibcon#read 3, iclass 17, count 0 2006.253.08:13:40.68#ibcon#about to read 4, iclass 17, count 0 2006.253.08:13:40.68#ibcon#read 4, iclass 17, count 0 2006.253.08:13:40.68#ibcon#about to read 5, iclass 17, count 0 2006.253.08:13:40.68#ibcon#read 5, iclass 17, count 0 2006.253.08:13:40.68#ibcon#about to read 6, iclass 17, count 0 2006.253.08:13:40.68#ibcon#read 6, iclass 17, count 0 2006.253.08:13:40.68#ibcon#end of sib2, iclass 17, count 0 2006.253.08:13:40.68#ibcon#*mode == 0, iclass 17, count 0 2006.253.08:13:40.68#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.253.08:13:40.68#ibcon#[28=FRQ=01,632.99\r\n] 2006.253.08:13:40.68#ibcon#*before write, iclass 17, count 0 2006.253.08:13:40.68#ibcon#enter sib2, iclass 17, count 0 2006.253.08:13:40.68#ibcon#flushed, iclass 17, count 0 2006.253.08:13:40.68#ibcon#about to write, iclass 17, count 0 2006.253.08:13:40.68#ibcon#wrote, iclass 17, count 0 2006.253.08:13:40.68#ibcon#about to read 3, iclass 17, count 0 2006.253.08:13:40.73#ibcon#read 3, iclass 17, count 0 2006.253.08:13:40.73#ibcon#about to read 4, iclass 17, count 0 2006.253.08:13:40.73#ibcon#read 4, iclass 17, count 0 2006.253.08:13:40.73#ibcon#about to read 5, iclass 17, count 0 2006.253.08:13:40.73#ibcon#read 5, iclass 17, count 0 2006.253.08:13:40.73#ibcon#about to read 6, iclass 17, count 0 2006.253.08:13:40.73#ibcon#read 6, iclass 17, count 0 2006.253.08:13:40.73#ibcon#end of sib2, iclass 17, count 0 2006.253.08:13:40.73#ibcon#*after write, iclass 17, count 0 2006.253.08:13:40.73#ibcon#*before return 0, iclass 17, count 0 2006.253.08:13:40.73#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.253.08:13:40.73#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.253.08:13:40.73#ibcon#about to clear, iclass 17 cls_cnt 0 2006.253.08:13:40.73#ibcon#cleared, iclass 17 cls_cnt 0 2006.253.08:13:40.73$vc4f8/vb=1,4 2006.253.08:13:40.73#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.253.08:13:40.73#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.253.08:13:40.73#ibcon#ireg 11 cls_cnt 2 2006.253.08:13:40.73#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.253.08:13:40.73#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.253.08:13:40.73#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.253.08:13:40.73#ibcon#enter wrdev, iclass 19, count 2 2006.253.08:13:40.73#ibcon#first serial, iclass 19, count 2 2006.253.08:13:40.73#ibcon#enter sib2, iclass 19, count 2 2006.253.08:13:40.73#ibcon#flushed, iclass 19, count 2 2006.253.08:13:40.73#ibcon#about to write, iclass 19, count 2 2006.253.08:13:40.73#ibcon#wrote, iclass 19, count 2 2006.253.08:13:40.73#ibcon#about to read 3, iclass 19, count 2 2006.253.08:13:40.75#ibcon#read 3, iclass 19, count 2 2006.253.08:13:40.75#ibcon#about to read 4, iclass 19, count 2 2006.253.08:13:40.75#ibcon#read 4, iclass 19, count 2 2006.253.08:13:40.75#ibcon#about to read 5, iclass 19, count 2 2006.253.08:13:40.75#ibcon#read 5, iclass 19, count 2 2006.253.08:13:40.75#ibcon#about to read 6, iclass 19, count 2 2006.253.08:13:40.75#ibcon#read 6, iclass 19, count 2 2006.253.08:13:40.75#ibcon#end of sib2, iclass 19, count 2 2006.253.08:13:40.75#ibcon#*mode == 0, iclass 19, count 2 2006.253.08:13:40.75#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.253.08:13:40.75#ibcon#[27=AT01-04\r\n] 2006.253.08:13:40.75#ibcon#*before write, iclass 19, count 2 2006.253.08:13:40.75#ibcon#enter sib2, iclass 19, count 2 2006.253.08:13:40.75#ibcon#flushed, iclass 19, count 2 2006.253.08:13:40.75#ibcon#about to write, iclass 19, count 2 2006.253.08:13:40.75#ibcon#wrote, iclass 19, count 2 2006.253.08:13:40.75#ibcon#about to read 3, iclass 19, count 2 2006.253.08:13:40.78#ibcon#read 3, iclass 19, count 2 2006.253.08:13:40.78#ibcon#about to read 4, iclass 19, count 2 2006.253.08:13:40.78#ibcon#read 4, iclass 19, count 2 2006.253.08:13:40.78#ibcon#about to read 5, iclass 19, count 2 2006.253.08:13:40.78#ibcon#read 5, iclass 19, count 2 2006.253.08:13:40.78#ibcon#about to read 6, iclass 19, count 2 2006.253.08:13:40.78#ibcon#read 6, iclass 19, count 2 2006.253.08:13:40.78#ibcon#end of sib2, iclass 19, count 2 2006.253.08:13:40.78#ibcon#*after write, iclass 19, count 2 2006.253.08:13:40.78#ibcon#*before return 0, iclass 19, count 2 2006.253.08:13:40.78#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.253.08:13:40.78#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.253.08:13:40.78#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.253.08:13:40.78#ibcon#ireg 7 cls_cnt 0 2006.253.08:13:40.78#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.253.08:13:40.90#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.253.08:13:40.90#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.253.08:13:40.90#ibcon#enter wrdev, iclass 19, count 0 2006.253.08:13:40.90#ibcon#first serial, iclass 19, count 0 2006.253.08:13:40.90#ibcon#enter sib2, iclass 19, count 0 2006.253.08:13:40.90#ibcon#flushed, iclass 19, count 0 2006.253.08:13:40.90#ibcon#about to write, iclass 19, count 0 2006.253.08:13:40.90#ibcon#wrote, iclass 19, count 0 2006.253.08:13:40.90#ibcon#about to read 3, iclass 19, count 0 2006.253.08:13:40.92#ibcon#read 3, iclass 19, count 0 2006.253.08:13:40.92#ibcon#about to read 4, iclass 19, count 0 2006.253.08:13:40.92#ibcon#read 4, iclass 19, count 0 2006.253.08:13:40.92#ibcon#about to read 5, iclass 19, count 0 2006.253.08:13:40.92#ibcon#read 5, iclass 19, count 0 2006.253.08:13:40.92#ibcon#about to read 6, iclass 19, count 0 2006.253.08:13:40.92#ibcon#read 6, iclass 19, count 0 2006.253.08:13:40.92#ibcon#end of sib2, iclass 19, count 0 2006.253.08:13:40.92#ibcon#*mode == 0, iclass 19, count 0 2006.253.08:13:40.92#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.253.08:13:40.92#ibcon#[27=USB\r\n] 2006.253.08:13:40.92#ibcon#*before write, iclass 19, count 0 2006.253.08:13:40.92#ibcon#enter sib2, iclass 19, count 0 2006.253.08:13:40.92#ibcon#flushed, iclass 19, count 0 2006.253.08:13:40.92#ibcon#about to write, iclass 19, count 0 2006.253.08:13:40.92#ibcon#wrote, iclass 19, count 0 2006.253.08:13:40.92#ibcon#about to read 3, iclass 19, count 0 2006.253.08:13:40.95#ibcon#read 3, iclass 19, count 0 2006.253.08:13:40.95#ibcon#about to read 4, iclass 19, count 0 2006.253.08:13:40.95#ibcon#read 4, iclass 19, count 0 2006.253.08:13:40.95#ibcon#about to read 5, iclass 19, count 0 2006.253.08:13:40.95#ibcon#read 5, iclass 19, count 0 2006.253.08:13:40.95#ibcon#about to read 6, iclass 19, count 0 2006.253.08:13:40.95#ibcon#read 6, iclass 19, count 0 2006.253.08:13:40.95#ibcon#end of sib2, iclass 19, count 0 2006.253.08:13:40.95#ibcon#*after write, iclass 19, count 0 2006.253.08:13:40.95#ibcon#*before return 0, iclass 19, count 0 2006.253.08:13:40.95#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.253.08:13:40.95#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.253.08:13:40.95#ibcon#about to clear, iclass 19 cls_cnt 0 2006.253.08:13:40.95#ibcon#cleared, iclass 19 cls_cnt 0 2006.253.08:13:40.95$vc4f8/vblo=2,640.99 2006.253.08:13:40.95#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.253.08:13:40.95#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.253.08:13:40.95#ibcon#ireg 17 cls_cnt 0 2006.253.08:13:40.95#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.253.08:13:40.95#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.253.08:13:40.95#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.253.08:13:40.95#ibcon#enter wrdev, iclass 21, count 0 2006.253.08:13:40.95#ibcon#first serial, iclass 21, count 0 2006.253.08:13:40.95#ibcon#enter sib2, iclass 21, count 0 2006.253.08:13:40.95#ibcon#flushed, iclass 21, count 0 2006.253.08:13:40.95#ibcon#about to write, iclass 21, count 0 2006.253.08:13:40.95#ibcon#wrote, iclass 21, count 0 2006.253.08:13:40.95#ibcon#about to read 3, iclass 21, count 0 2006.253.08:13:40.97#ibcon#read 3, iclass 21, count 0 2006.253.08:13:40.97#ibcon#about to read 4, iclass 21, count 0 2006.253.08:13:40.97#ibcon#read 4, iclass 21, count 0 2006.253.08:13:40.97#ibcon#about to read 5, iclass 21, count 0 2006.253.08:13:40.97#ibcon#read 5, iclass 21, count 0 2006.253.08:13:40.97#ibcon#about to read 6, iclass 21, count 0 2006.253.08:13:40.97#ibcon#read 6, iclass 21, count 0 2006.253.08:13:40.97#ibcon#end of sib2, iclass 21, count 0 2006.253.08:13:40.97#ibcon#*mode == 0, iclass 21, count 0 2006.253.08:13:40.97#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.253.08:13:40.97#ibcon#[28=FRQ=02,640.99\r\n] 2006.253.08:13:40.97#ibcon#*before write, iclass 21, count 0 2006.253.08:13:40.97#ibcon#enter sib2, iclass 21, count 0 2006.253.08:13:40.97#ibcon#flushed, iclass 21, count 0 2006.253.08:13:40.97#ibcon#about to write, iclass 21, count 0 2006.253.08:13:40.97#ibcon#wrote, iclass 21, count 0 2006.253.08:13:40.97#ibcon#about to read 3, iclass 21, count 0 2006.253.08:13:41.01#ibcon#read 3, iclass 21, count 0 2006.253.08:13:41.01#ibcon#about to read 4, iclass 21, count 0 2006.253.08:13:41.01#ibcon#read 4, iclass 21, count 0 2006.253.08:13:41.01#ibcon#about to read 5, iclass 21, count 0 2006.253.08:13:41.01#ibcon#read 5, iclass 21, count 0 2006.253.08:13:41.01#ibcon#about to read 6, iclass 21, count 0 2006.253.08:13:41.01#ibcon#read 6, iclass 21, count 0 2006.253.08:13:41.01#ibcon#end of sib2, iclass 21, count 0 2006.253.08:13:41.01#ibcon#*after write, iclass 21, count 0 2006.253.08:13:41.01#ibcon#*before return 0, iclass 21, count 0 2006.253.08:13:41.01#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.253.08:13:41.01#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.253.08:13:41.01#ibcon#about to clear, iclass 21 cls_cnt 0 2006.253.08:13:41.01#ibcon#cleared, iclass 21 cls_cnt 0 2006.253.08:13:41.01$vc4f8/vb=2,5 2006.253.08:13:41.01#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.253.08:13:41.01#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.253.08:13:41.01#ibcon#ireg 11 cls_cnt 2 2006.253.08:13:41.01#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.253.08:13:41.07#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.253.08:13:41.07#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.253.08:13:41.07#ibcon#enter wrdev, iclass 23, count 2 2006.253.08:13:41.07#ibcon#first serial, iclass 23, count 2 2006.253.08:13:41.07#ibcon#enter sib2, iclass 23, count 2 2006.253.08:13:41.07#ibcon#flushed, iclass 23, count 2 2006.253.08:13:41.07#ibcon#about to write, iclass 23, count 2 2006.253.08:13:41.07#ibcon#wrote, iclass 23, count 2 2006.253.08:13:41.07#ibcon#about to read 3, iclass 23, count 2 2006.253.08:13:41.09#ibcon#read 3, iclass 23, count 2 2006.253.08:13:41.09#ibcon#about to read 4, iclass 23, count 2 2006.253.08:13:41.09#ibcon#read 4, iclass 23, count 2 2006.253.08:13:41.09#ibcon#about to read 5, iclass 23, count 2 2006.253.08:13:41.09#ibcon#read 5, iclass 23, count 2 2006.253.08:13:41.09#ibcon#about to read 6, iclass 23, count 2 2006.253.08:13:41.09#ibcon#read 6, iclass 23, count 2 2006.253.08:13:41.09#ibcon#end of sib2, iclass 23, count 2 2006.253.08:13:41.09#ibcon#*mode == 0, iclass 23, count 2 2006.253.08:13:41.09#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.253.08:13:41.09#ibcon#[27=AT02-05\r\n] 2006.253.08:13:41.09#ibcon#*before write, iclass 23, count 2 2006.253.08:13:41.09#ibcon#enter sib2, iclass 23, count 2 2006.253.08:13:41.09#ibcon#flushed, iclass 23, count 2 2006.253.08:13:41.09#ibcon#about to write, iclass 23, count 2 2006.253.08:13:41.09#ibcon#wrote, iclass 23, count 2 2006.253.08:13:41.09#ibcon#about to read 3, iclass 23, count 2 2006.253.08:13:41.12#ibcon#read 3, iclass 23, count 2 2006.253.08:13:41.12#ibcon#about to read 4, iclass 23, count 2 2006.253.08:13:41.12#ibcon#read 4, iclass 23, count 2 2006.253.08:13:41.12#ibcon#about to read 5, iclass 23, count 2 2006.253.08:13:41.12#ibcon#read 5, iclass 23, count 2 2006.253.08:13:41.12#ibcon#about to read 6, iclass 23, count 2 2006.253.08:13:41.12#ibcon#read 6, iclass 23, count 2 2006.253.08:13:41.12#ibcon#end of sib2, iclass 23, count 2 2006.253.08:13:41.12#ibcon#*after write, iclass 23, count 2 2006.253.08:13:41.12#ibcon#*before return 0, iclass 23, count 2 2006.253.08:13:41.12#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.253.08:13:41.12#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.253.08:13:41.12#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.253.08:13:41.12#ibcon#ireg 7 cls_cnt 0 2006.253.08:13:41.12#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.253.08:13:41.24#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.253.08:13:41.24#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.253.08:13:41.24#ibcon#enter wrdev, iclass 23, count 0 2006.253.08:13:41.24#ibcon#first serial, iclass 23, count 0 2006.253.08:13:41.24#ibcon#enter sib2, iclass 23, count 0 2006.253.08:13:41.24#ibcon#flushed, iclass 23, count 0 2006.253.08:13:41.24#ibcon#about to write, iclass 23, count 0 2006.253.08:13:41.24#ibcon#wrote, iclass 23, count 0 2006.253.08:13:41.24#ibcon#about to read 3, iclass 23, count 0 2006.253.08:13:41.26#ibcon#read 3, iclass 23, count 0 2006.253.08:13:41.26#ibcon#about to read 4, iclass 23, count 0 2006.253.08:13:41.26#ibcon#read 4, iclass 23, count 0 2006.253.08:13:41.26#ibcon#about to read 5, iclass 23, count 0 2006.253.08:13:41.26#ibcon#read 5, iclass 23, count 0 2006.253.08:13:41.26#ibcon#about to read 6, iclass 23, count 0 2006.253.08:13:41.26#ibcon#read 6, iclass 23, count 0 2006.253.08:13:41.26#ibcon#end of sib2, iclass 23, count 0 2006.253.08:13:41.26#ibcon#*mode == 0, iclass 23, count 0 2006.253.08:13:41.26#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.253.08:13:41.26#ibcon#[27=USB\r\n] 2006.253.08:13:41.26#ibcon#*before write, iclass 23, count 0 2006.253.08:13:41.26#ibcon#enter sib2, iclass 23, count 0 2006.253.08:13:41.26#ibcon#flushed, iclass 23, count 0 2006.253.08:13:41.26#ibcon#about to write, iclass 23, count 0 2006.253.08:13:41.26#ibcon#wrote, iclass 23, count 0 2006.253.08:13:41.26#ibcon#about to read 3, iclass 23, count 0 2006.253.08:13:41.29#ibcon#read 3, iclass 23, count 0 2006.253.08:13:41.29#ibcon#about to read 4, iclass 23, count 0 2006.253.08:13:41.29#ibcon#read 4, iclass 23, count 0 2006.253.08:13:41.29#ibcon#about to read 5, iclass 23, count 0 2006.253.08:13:41.29#ibcon#read 5, iclass 23, count 0 2006.253.08:13:41.29#ibcon#about to read 6, iclass 23, count 0 2006.253.08:13:41.29#ibcon#read 6, iclass 23, count 0 2006.253.08:13:41.29#ibcon#end of sib2, iclass 23, count 0 2006.253.08:13:41.29#ibcon#*after write, iclass 23, count 0 2006.253.08:13:41.29#ibcon#*before return 0, iclass 23, count 0 2006.253.08:13:41.29#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.253.08:13:41.29#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.253.08:13:41.29#ibcon#about to clear, iclass 23 cls_cnt 0 2006.253.08:13:41.29#ibcon#cleared, iclass 23 cls_cnt 0 2006.253.08:13:41.29$vc4f8/vblo=3,656.99 2006.253.08:13:41.29#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.253.08:13:41.29#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.253.08:13:41.29#ibcon#ireg 17 cls_cnt 0 2006.253.08:13:41.29#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.253.08:13:41.29#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.253.08:13:41.29#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.253.08:13:41.29#ibcon#enter wrdev, iclass 25, count 0 2006.253.08:13:41.29#ibcon#first serial, iclass 25, count 0 2006.253.08:13:41.29#ibcon#enter sib2, iclass 25, count 0 2006.253.08:13:41.29#ibcon#flushed, iclass 25, count 0 2006.253.08:13:41.29#ibcon#about to write, iclass 25, count 0 2006.253.08:13:41.29#ibcon#wrote, iclass 25, count 0 2006.253.08:13:41.29#ibcon#about to read 3, iclass 25, count 0 2006.253.08:13:41.31#ibcon#read 3, iclass 25, count 0 2006.253.08:13:41.31#ibcon#about to read 4, iclass 25, count 0 2006.253.08:13:41.31#ibcon#read 4, iclass 25, count 0 2006.253.08:13:41.31#ibcon#about to read 5, iclass 25, count 0 2006.253.08:13:41.31#ibcon#read 5, iclass 25, count 0 2006.253.08:13:41.31#ibcon#about to read 6, iclass 25, count 0 2006.253.08:13:41.31#ibcon#read 6, iclass 25, count 0 2006.253.08:13:41.31#ibcon#end of sib2, iclass 25, count 0 2006.253.08:13:41.31#ibcon#*mode == 0, iclass 25, count 0 2006.253.08:13:41.31#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.253.08:13:41.31#ibcon#[28=FRQ=03,656.99\r\n] 2006.253.08:13:41.31#ibcon#*before write, iclass 25, count 0 2006.253.08:13:41.31#ibcon#enter sib2, iclass 25, count 0 2006.253.08:13:41.31#ibcon#flushed, iclass 25, count 0 2006.253.08:13:41.31#ibcon#about to write, iclass 25, count 0 2006.253.08:13:41.31#ibcon#wrote, iclass 25, count 0 2006.253.08:13:41.31#ibcon#about to read 3, iclass 25, count 0 2006.253.08:13:41.35#ibcon#read 3, iclass 25, count 0 2006.253.08:13:41.35#ibcon#about to read 4, iclass 25, count 0 2006.253.08:13:41.35#ibcon#read 4, iclass 25, count 0 2006.253.08:13:41.35#ibcon#about to read 5, iclass 25, count 0 2006.253.08:13:41.35#ibcon#read 5, iclass 25, count 0 2006.253.08:13:41.35#ibcon#about to read 6, iclass 25, count 0 2006.253.08:13:41.35#ibcon#read 6, iclass 25, count 0 2006.253.08:13:41.35#ibcon#end of sib2, iclass 25, count 0 2006.253.08:13:41.35#ibcon#*after write, iclass 25, count 0 2006.253.08:13:41.35#ibcon#*before return 0, iclass 25, count 0 2006.253.08:13:41.35#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.253.08:13:41.35#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.253.08:13:41.35#ibcon#about to clear, iclass 25 cls_cnt 0 2006.253.08:13:41.35#ibcon#cleared, iclass 25 cls_cnt 0 2006.253.08:13:41.35$vc4f8/vb=3,4 2006.253.08:13:41.35#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.253.08:13:41.35#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.253.08:13:41.35#ibcon#ireg 11 cls_cnt 2 2006.253.08:13:41.35#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.253.08:13:41.41#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.253.08:13:41.41#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.253.08:13:41.41#ibcon#enter wrdev, iclass 27, count 2 2006.253.08:13:41.41#ibcon#first serial, iclass 27, count 2 2006.253.08:13:41.41#ibcon#enter sib2, iclass 27, count 2 2006.253.08:13:41.41#ibcon#flushed, iclass 27, count 2 2006.253.08:13:41.41#ibcon#about to write, iclass 27, count 2 2006.253.08:13:41.41#ibcon#wrote, iclass 27, count 2 2006.253.08:13:41.41#ibcon#about to read 3, iclass 27, count 2 2006.253.08:13:41.43#ibcon#read 3, iclass 27, count 2 2006.253.08:13:41.43#ibcon#about to read 4, iclass 27, count 2 2006.253.08:13:41.43#ibcon#read 4, iclass 27, count 2 2006.253.08:13:41.43#ibcon#about to read 5, iclass 27, count 2 2006.253.08:13:41.43#ibcon#read 5, iclass 27, count 2 2006.253.08:13:41.43#ibcon#about to read 6, iclass 27, count 2 2006.253.08:13:41.43#ibcon#read 6, iclass 27, count 2 2006.253.08:13:41.43#ibcon#end of sib2, iclass 27, count 2 2006.253.08:13:41.43#ibcon#*mode == 0, iclass 27, count 2 2006.253.08:13:41.43#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.253.08:13:41.43#ibcon#[27=AT03-04\r\n] 2006.253.08:13:41.43#ibcon#*before write, iclass 27, count 2 2006.253.08:13:41.43#ibcon#enter sib2, iclass 27, count 2 2006.253.08:13:41.43#ibcon#flushed, iclass 27, count 2 2006.253.08:13:41.43#ibcon#about to write, iclass 27, count 2 2006.253.08:13:41.43#ibcon#wrote, iclass 27, count 2 2006.253.08:13:41.43#ibcon#about to read 3, iclass 27, count 2 2006.253.08:13:41.46#ibcon#read 3, iclass 27, count 2 2006.253.08:13:41.46#ibcon#about to read 4, iclass 27, count 2 2006.253.08:13:41.46#ibcon#read 4, iclass 27, count 2 2006.253.08:13:41.46#ibcon#about to read 5, iclass 27, count 2 2006.253.08:13:41.46#ibcon#read 5, iclass 27, count 2 2006.253.08:13:41.46#ibcon#about to read 6, iclass 27, count 2 2006.253.08:13:41.46#ibcon#read 6, iclass 27, count 2 2006.253.08:13:41.46#ibcon#end of sib2, iclass 27, count 2 2006.253.08:13:41.46#ibcon#*after write, iclass 27, count 2 2006.253.08:13:41.46#ibcon#*before return 0, iclass 27, count 2 2006.253.08:13:41.46#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.253.08:13:41.46#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.253.08:13:41.46#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.253.08:13:41.46#ibcon#ireg 7 cls_cnt 0 2006.253.08:13:41.46#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.253.08:13:41.58#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.253.08:13:41.58#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.253.08:13:41.58#ibcon#enter wrdev, iclass 27, count 0 2006.253.08:13:41.58#ibcon#first serial, iclass 27, count 0 2006.253.08:13:41.58#ibcon#enter sib2, iclass 27, count 0 2006.253.08:13:41.58#ibcon#flushed, iclass 27, count 0 2006.253.08:13:41.58#ibcon#about to write, iclass 27, count 0 2006.253.08:13:41.58#ibcon#wrote, iclass 27, count 0 2006.253.08:13:41.58#ibcon#about to read 3, iclass 27, count 0 2006.253.08:13:41.60#ibcon#read 3, iclass 27, count 0 2006.253.08:13:41.60#ibcon#about to read 4, iclass 27, count 0 2006.253.08:13:41.60#ibcon#read 4, iclass 27, count 0 2006.253.08:13:41.60#ibcon#about to read 5, iclass 27, count 0 2006.253.08:13:41.60#ibcon#read 5, iclass 27, count 0 2006.253.08:13:41.60#ibcon#about to read 6, iclass 27, count 0 2006.253.08:13:41.60#ibcon#read 6, iclass 27, count 0 2006.253.08:13:41.60#ibcon#end of sib2, iclass 27, count 0 2006.253.08:13:41.60#ibcon#*mode == 0, iclass 27, count 0 2006.253.08:13:41.60#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.253.08:13:41.60#ibcon#[27=USB\r\n] 2006.253.08:13:41.60#ibcon#*before write, iclass 27, count 0 2006.253.08:13:41.60#ibcon#enter sib2, iclass 27, count 0 2006.253.08:13:41.60#ibcon#flushed, iclass 27, count 0 2006.253.08:13:41.60#ibcon#about to write, iclass 27, count 0 2006.253.08:13:41.60#ibcon#wrote, iclass 27, count 0 2006.253.08:13:41.60#ibcon#about to read 3, iclass 27, count 0 2006.253.08:13:41.63#ibcon#read 3, iclass 27, count 0 2006.253.08:13:41.63#ibcon#about to read 4, iclass 27, count 0 2006.253.08:13:41.63#ibcon#read 4, iclass 27, count 0 2006.253.08:13:41.63#ibcon#about to read 5, iclass 27, count 0 2006.253.08:13:41.63#ibcon#read 5, iclass 27, count 0 2006.253.08:13:41.63#ibcon#about to read 6, iclass 27, count 0 2006.253.08:13:41.63#ibcon#read 6, iclass 27, count 0 2006.253.08:13:41.63#ibcon#end of sib2, iclass 27, count 0 2006.253.08:13:41.63#ibcon#*after write, iclass 27, count 0 2006.253.08:13:41.63#ibcon#*before return 0, iclass 27, count 0 2006.253.08:13:41.63#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.253.08:13:41.63#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.253.08:13:41.63#ibcon#about to clear, iclass 27 cls_cnt 0 2006.253.08:13:41.63#ibcon#cleared, iclass 27 cls_cnt 0 2006.253.08:13:41.63$vc4f8/vblo=4,712.99 2006.253.08:13:41.63#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.253.08:13:41.63#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.253.08:13:41.63#ibcon#ireg 17 cls_cnt 0 2006.253.08:13:41.63#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.253.08:13:41.63#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.253.08:13:41.63#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.253.08:13:41.63#ibcon#enter wrdev, iclass 29, count 0 2006.253.08:13:41.63#ibcon#first serial, iclass 29, count 0 2006.253.08:13:41.63#ibcon#enter sib2, iclass 29, count 0 2006.253.08:13:41.63#ibcon#flushed, iclass 29, count 0 2006.253.08:13:41.63#ibcon#about to write, iclass 29, count 0 2006.253.08:13:41.63#ibcon#wrote, iclass 29, count 0 2006.253.08:13:41.63#ibcon#about to read 3, iclass 29, count 0 2006.253.08:13:41.65#ibcon#read 3, iclass 29, count 0 2006.253.08:13:41.65#ibcon#about to read 4, iclass 29, count 0 2006.253.08:13:41.65#ibcon#read 4, iclass 29, count 0 2006.253.08:13:41.65#ibcon#about to read 5, iclass 29, count 0 2006.253.08:13:41.65#ibcon#read 5, iclass 29, count 0 2006.253.08:13:41.65#ibcon#about to read 6, iclass 29, count 0 2006.253.08:13:41.65#ibcon#read 6, iclass 29, count 0 2006.253.08:13:41.65#ibcon#end of sib2, iclass 29, count 0 2006.253.08:13:41.65#ibcon#*mode == 0, iclass 29, count 0 2006.253.08:13:41.65#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.253.08:13:41.65#ibcon#[28=FRQ=04,712.99\r\n] 2006.253.08:13:41.65#ibcon#*before write, iclass 29, count 0 2006.253.08:13:41.65#ibcon#enter sib2, iclass 29, count 0 2006.253.08:13:41.65#ibcon#flushed, iclass 29, count 0 2006.253.08:13:41.65#ibcon#about to write, iclass 29, count 0 2006.253.08:13:41.65#ibcon#wrote, iclass 29, count 0 2006.253.08:13:41.65#ibcon#about to read 3, iclass 29, count 0 2006.253.08:13:41.70#ibcon#read 3, iclass 29, count 0 2006.253.08:13:41.70#ibcon#about to read 4, iclass 29, count 0 2006.253.08:13:41.70#ibcon#read 4, iclass 29, count 0 2006.253.08:13:41.70#ibcon#about to read 5, iclass 29, count 0 2006.253.08:13:41.70#ibcon#read 5, iclass 29, count 0 2006.253.08:13:41.70#ibcon#about to read 6, iclass 29, count 0 2006.253.08:13:41.70#ibcon#read 6, iclass 29, count 0 2006.253.08:13:41.70#ibcon#end of sib2, iclass 29, count 0 2006.253.08:13:41.70#ibcon#*after write, iclass 29, count 0 2006.253.08:13:41.70#ibcon#*before return 0, iclass 29, count 0 2006.253.08:13:41.70#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.253.08:13:41.70#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.253.08:13:41.70#ibcon#about to clear, iclass 29 cls_cnt 0 2006.253.08:13:41.70#ibcon#cleared, iclass 29 cls_cnt 0 2006.253.08:13:41.70$vc4f8/vb=4,4 2006.253.08:13:41.70#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.253.08:13:41.70#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.253.08:13:41.70#ibcon#ireg 11 cls_cnt 2 2006.253.08:13:41.70#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.253.08:13:41.75#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.253.08:13:41.75#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.253.08:13:41.75#ibcon#enter wrdev, iclass 31, count 2 2006.253.08:13:41.75#ibcon#first serial, iclass 31, count 2 2006.253.08:13:41.75#ibcon#enter sib2, iclass 31, count 2 2006.253.08:13:41.75#ibcon#flushed, iclass 31, count 2 2006.253.08:13:41.75#ibcon#about to write, iclass 31, count 2 2006.253.08:13:41.75#ibcon#wrote, iclass 31, count 2 2006.253.08:13:41.75#ibcon#about to read 3, iclass 31, count 2 2006.253.08:13:41.77#ibcon#read 3, iclass 31, count 2 2006.253.08:13:41.77#ibcon#about to read 4, iclass 31, count 2 2006.253.08:13:41.77#ibcon#read 4, iclass 31, count 2 2006.253.08:13:41.77#ibcon#about to read 5, iclass 31, count 2 2006.253.08:13:41.77#ibcon#read 5, iclass 31, count 2 2006.253.08:13:41.77#ibcon#about to read 6, iclass 31, count 2 2006.253.08:13:41.77#ibcon#read 6, iclass 31, count 2 2006.253.08:13:41.77#ibcon#end of sib2, iclass 31, count 2 2006.253.08:13:41.77#ibcon#*mode == 0, iclass 31, count 2 2006.253.08:13:41.77#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.253.08:13:41.77#ibcon#[27=AT04-04\r\n] 2006.253.08:13:41.77#ibcon#*before write, iclass 31, count 2 2006.253.08:13:41.77#ibcon#enter sib2, iclass 31, count 2 2006.253.08:13:41.77#ibcon#flushed, iclass 31, count 2 2006.253.08:13:41.77#ibcon#about to write, iclass 31, count 2 2006.253.08:13:41.77#ibcon#wrote, iclass 31, count 2 2006.253.08:13:41.77#ibcon#about to read 3, iclass 31, count 2 2006.253.08:13:41.80#ibcon#read 3, iclass 31, count 2 2006.253.08:13:41.80#ibcon#about to read 4, iclass 31, count 2 2006.253.08:13:41.80#ibcon#read 4, iclass 31, count 2 2006.253.08:13:41.80#ibcon#about to read 5, iclass 31, count 2 2006.253.08:13:41.80#ibcon#read 5, iclass 31, count 2 2006.253.08:13:41.80#ibcon#about to read 6, iclass 31, count 2 2006.253.08:13:41.80#ibcon#read 6, iclass 31, count 2 2006.253.08:13:41.80#ibcon#end of sib2, iclass 31, count 2 2006.253.08:13:41.80#ibcon#*after write, iclass 31, count 2 2006.253.08:13:41.80#ibcon#*before return 0, iclass 31, count 2 2006.253.08:13:41.80#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.253.08:13:41.80#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.253.08:13:41.80#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.253.08:13:41.80#ibcon#ireg 7 cls_cnt 0 2006.253.08:13:41.80#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.253.08:13:41.92#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.253.08:13:41.92#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.253.08:13:41.92#ibcon#enter wrdev, iclass 31, count 0 2006.253.08:13:41.92#ibcon#first serial, iclass 31, count 0 2006.253.08:13:41.92#ibcon#enter sib2, iclass 31, count 0 2006.253.08:13:41.92#ibcon#flushed, iclass 31, count 0 2006.253.08:13:41.92#ibcon#about to write, iclass 31, count 0 2006.253.08:13:41.92#ibcon#wrote, iclass 31, count 0 2006.253.08:13:41.92#ibcon#about to read 3, iclass 31, count 0 2006.253.08:13:41.94#ibcon#read 3, iclass 31, count 0 2006.253.08:13:41.94#ibcon#about to read 4, iclass 31, count 0 2006.253.08:13:41.94#ibcon#read 4, iclass 31, count 0 2006.253.08:13:41.94#ibcon#about to read 5, iclass 31, count 0 2006.253.08:13:41.94#ibcon#read 5, iclass 31, count 0 2006.253.08:13:41.94#ibcon#about to read 6, iclass 31, count 0 2006.253.08:13:41.94#ibcon#read 6, iclass 31, count 0 2006.253.08:13:41.94#ibcon#end of sib2, iclass 31, count 0 2006.253.08:13:41.94#ibcon#*mode == 0, iclass 31, count 0 2006.253.08:13:41.94#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.253.08:13:41.94#ibcon#[27=USB\r\n] 2006.253.08:13:41.94#ibcon#*before write, iclass 31, count 0 2006.253.08:13:41.94#ibcon#enter sib2, iclass 31, count 0 2006.253.08:13:41.94#ibcon#flushed, iclass 31, count 0 2006.253.08:13:41.94#ibcon#about to write, iclass 31, count 0 2006.253.08:13:41.94#ibcon#wrote, iclass 31, count 0 2006.253.08:13:41.94#ibcon#about to read 3, iclass 31, count 0 2006.253.08:13:41.97#ibcon#read 3, iclass 31, count 0 2006.253.08:13:41.97#ibcon#about to read 4, iclass 31, count 0 2006.253.08:13:41.97#ibcon#read 4, iclass 31, count 0 2006.253.08:13:41.97#ibcon#about to read 5, iclass 31, count 0 2006.253.08:13:41.97#ibcon#read 5, iclass 31, count 0 2006.253.08:13:41.97#ibcon#about to read 6, iclass 31, count 0 2006.253.08:13:41.97#ibcon#read 6, iclass 31, count 0 2006.253.08:13:41.97#ibcon#end of sib2, iclass 31, count 0 2006.253.08:13:41.97#ibcon#*after write, iclass 31, count 0 2006.253.08:13:41.97#ibcon#*before return 0, iclass 31, count 0 2006.253.08:13:41.97#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.253.08:13:41.97#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.253.08:13:41.97#ibcon#about to clear, iclass 31 cls_cnt 0 2006.253.08:13:41.97#ibcon#cleared, iclass 31 cls_cnt 0 2006.253.08:13:41.97$vc4f8/vblo=5,744.99 2006.253.08:13:41.97#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.253.08:13:41.97#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.253.08:13:41.97#ibcon#ireg 17 cls_cnt 0 2006.253.08:13:41.97#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.253.08:13:41.97#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.253.08:13:41.97#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.253.08:13:41.97#ibcon#enter wrdev, iclass 33, count 0 2006.253.08:13:41.97#ibcon#first serial, iclass 33, count 0 2006.253.08:13:41.97#ibcon#enter sib2, iclass 33, count 0 2006.253.08:13:41.97#ibcon#flushed, iclass 33, count 0 2006.253.08:13:41.97#ibcon#about to write, iclass 33, count 0 2006.253.08:13:41.97#ibcon#wrote, iclass 33, count 0 2006.253.08:13:41.97#ibcon#about to read 3, iclass 33, count 0 2006.253.08:13:41.99#ibcon#read 3, iclass 33, count 0 2006.253.08:13:41.99#ibcon#about to read 4, iclass 33, count 0 2006.253.08:13:41.99#ibcon#read 4, iclass 33, count 0 2006.253.08:13:41.99#ibcon#about to read 5, iclass 33, count 0 2006.253.08:13:41.99#ibcon#read 5, iclass 33, count 0 2006.253.08:13:41.99#ibcon#about to read 6, iclass 33, count 0 2006.253.08:13:41.99#ibcon#read 6, iclass 33, count 0 2006.253.08:13:41.99#ibcon#end of sib2, iclass 33, count 0 2006.253.08:13:41.99#ibcon#*mode == 0, iclass 33, count 0 2006.253.08:13:41.99#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.253.08:13:41.99#ibcon#[28=FRQ=05,744.99\r\n] 2006.253.08:13:41.99#ibcon#*before write, iclass 33, count 0 2006.253.08:13:41.99#ibcon#enter sib2, iclass 33, count 0 2006.253.08:13:41.99#ibcon#flushed, iclass 33, count 0 2006.253.08:13:41.99#ibcon#about to write, iclass 33, count 0 2006.253.08:13:41.99#ibcon#wrote, iclass 33, count 0 2006.253.08:13:41.99#ibcon#about to read 3, iclass 33, count 0 2006.253.08:13:42.03#ibcon#read 3, iclass 33, count 0 2006.253.08:13:42.03#ibcon#about to read 4, iclass 33, count 0 2006.253.08:13:42.03#ibcon#read 4, iclass 33, count 0 2006.253.08:13:42.03#ibcon#about to read 5, iclass 33, count 0 2006.253.08:13:42.03#ibcon#read 5, iclass 33, count 0 2006.253.08:13:42.03#ibcon#about to read 6, iclass 33, count 0 2006.253.08:13:42.03#ibcon#read 6, iclass 33, count 0 2006.253.08:13:42.03#ibcon#end of sib2, iclass 33, count 0 2006.253.08:13:42.03#ibcon#*after write, iclass 33, count 0 2006.253.08:13:42.03#ibcon#*before return 0, iclass 33, count 0 2006.253.08:13:42.03#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.253.08:13:42.03#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.253.08:13:42.03#ibcon#about to clear, iclass 33 cls_cnt 0 2006.253.08:13:42.03#ibcon#cleared, iclass 33 cls_cnt 0 2006.253.08:13:42.03$vc4f8/vb=5,4 2006.253.08:13:42.03#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.253.08:13:42.03#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.253.08:13:42.03#ibcon#ireg 11 cls_cnt 2 2006.253.08:13:42.03#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.253.08:13:42.09#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.253.08:13:42.09#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.253.08:13:42.09#ibcon#enter wrdev, iclass 35, count 2 2006.253.08:13:42.09#ibcon#first serial, iclass 35, count 2 2006.253.08:13:42.09#ibcon#enter sib2, iclass 35, count 2 2006.253.08:13:42.09#ibcon#flushed, iclass 35, count 2 2006.253.08:13:42.09#ibcon#about to write, iclass 35, count 2 2006.253.08:13:42.09#ibcon#wrote, iclass 35, count 2 2006.253.08:13:42.09#ibcon#about to read 3, iclass 35, count 2 2006.253.08:13:42.11#ibcon#read 3, iclass 35, count 2 2006.253.08:13:42.11#ibcon#about to read 4, iclass 35, count 2 2006.253.08:13:42.11#ibcon#read 4, iclass 35, count 2 2006.253.08:13:42.11#ibcon#about to read 5, iclass 35, count 2 2006.253.08:13:42.11#ibcon#read 5, iclass 35, count 2 2006.253.08:13:42.11#ibcon#about to read 6, iclass 35, count 2 2006.253.08:13:42.11#ibcon#read 6, iclass 35, count 2 2006.253.08:13:42.11#ibcon#end of sib2, iclass 35, count 2 2006.253.08:13:42.11#ibcon#*mode == 0, iclass 35, count 2 2006.253.08:13:42.11#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.253.08:13:42.11#ibcon#[27=AT05-04\r\n] 2006.253.08:13:42.11#ibcon#*before write, iclass 35, count 2 2006.253.08:13:42.11#ibcon#enter sib2, iclass 35, count 2 2006.253.08:13:42.11#ibcon#flushed, iclass 35, count 2 2006.253.08:13:42.11#ibcon#about to write, iclass 35, count 2 2006.253.08:13:42.11#ibcon#wrote, iclass 35, count 2 2006.253.08:13:42.11#ibcon#about to read 3, iclass 35, count 2 2006.253.08:13:42.14#ibcon#read 3, iclass 35, count 2 2006.253.08:13:42.14#ibcon#about to read 4, iclass 35, count 2 2006.253.08:13:42.14#ibcon#read 4, iclass 35, count 2 2006.253.08:13:42.14#ibcon#about to read 5, iclass 35, count 2 2006.253.08:13:42.14#ibcon#read 5, iclass 35, count 2 2006.253.08:13:42.14#ibcon#about to read 6, iclass 35, count 2 2006.253.08:13:42.14#ibcon#read 6, iclass 35, count 2 2006.253.08:13:42.14#ibcon#end of sib2, iclass 35, count 2 2006.253.08:13:42.14#ibcon#*after write, iclass 35, count 2 2006.253.08:13:42.14#ibcon#*before return 0, iclass 35, count 2 2006.253.08:13:42.14#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.253.08:13:42.14#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.253.08:13:42.14#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.253.08:13:42.14#ibcon#ireg 7 cls_cnt 0 2006.253.08:13:42.14#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.253.08:13:42.26#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.253.08:13:42.26#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.253.08:13:42.26#ibcon#enter wrdev, iclass 35, count 0 2006.253.08:13:42.26#ibcon#first serial, iclass 35, count 0 2006.253.08:13:42.26#ibcon#enter sib2, iclass 35, count 0 2006.253.08:13:42.26#ibcon#flushed, iclass 35, count 0 2006.253.08:13:42.26#ibcon#about to write, iclass 35, count 0 2006.253.08:13:42.26#ibcon#wrote, iclass 35, count 0 2006.253.08:13:42.26#ibcon#about to read 3, iclass 35, count 0 2006.253.08:13:42.28#ibcon#read 3, iclass 35, count 0 2006.253.08:13:42.28#ibcon#about to read 4, iclass 35, count 0 2006.253.08:13:42.28#ibcon#read 4, iclass 35, count 0 2006.253.08:13:42.28#ibcon#about to read 5, iclass 35, count 0 2006.253.08:13:42.28#ibcon#read 5, iclass 35, count 0 2006.253.08:13:42.28#ibcon#about to read 6, iclass 35, count 0 2006.253.08:13:42.28#ibcon#read 6, iclass 35, count 0 2006.253.08:13:42.28#ibcon#end of sib2, iclass 35, count 0 2006.253.08:13:42.28#ibcon#*mode == 0, iclass 35, count 0 2006.253.08:13:42.28#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.253.08:13:42.28#ibcon#[27=USB\r\n] 2006.253.08:13:42.28#ibcon#*before write, iclass 35, count 0 2006.253.08:13:42.28#ibcon#enter sib2, iclass 35, count 0 2006.253.08:13:42.28#ibcon#flushed, iclass 35, count 0 2006.253.08:13:42.28#ibcon#about to write, iclass 35, count 0 2006.253.08:13:42.28#ibcon#wrote, iclass 35, count 0 2006.253.08:13:42.28#ibcon#about to read 3, iclass 35, count 0 2006.253.08:13:42.31#ibcon#read 3, iclass 35, count 0 2006.253.08:13:42.31#ibcon#about to read 4, iclass 35, count 0 2006.253.08:13:42.31#ibcon#read 4, iclass 35, count 0 2006.253.08:13:42.31#ibcon#about to read 5, iclass 35, count 0 2006.253.08:13:42.31#ibcon#read 5, iclass 35, count 0 2006.253.08:13:42.31#ibcon#about to read 6, iclass 35, count 0 2006.253.08:13:42.31#ibcon#read 6, iclass 35, count 0 2006.253.08:13:42.31#ibcon#end of sib2, iclass 35, count 0 2006.253.08:13:42.31#ibcon#*after write, iclass 35, count 0 2006.253.08:13:42.31#ibcon#*before return 0, iclass 35, count 0 2006.253.08:13:42.31#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.253.08:13:42.31#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.253.08:13:42.31#ibcon#about to clear, iclass 35 cls_cnt 0 2006.253.08:13:42.31#ibcon#cleared, iclass 35 cls_cnt 0 2006.253.08:13:42.31$vc4f8/vblo=6,752.99 2006.253.08:13:42.31#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.253.08:13:42.31#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.253.08:13:42.31#ibcon#ireg 17 cls_cnt 0 2006.253.08:13:42.31#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.253.08:13:42.31#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.253.08:13:42.31#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.253.08:13:42.31#ibcon#enter wrdev, iclass 37, count 0 2006.253.08:13:42.31#ibcon#first serial, iclass 37, count 0 2006.253.08:13:42.31#ibcon#enter sib2, iclass 37, count 0 2006.253.08:13:42.31#ibcon#flushed, iclass 37, count 0 2006.253.08:13:42.31#ibcon#about to write, iclass 37, count 0 2006.253.08:13:42.31#ibcon#wrote, iclass 37, count 0 2006.253.08:13:42.31#ibcon#about to read 3, iclass 37, count 0 2006.253.08:13:42.33#ibcon#read 3, iclass 37, count 0 2006.253.08:13:42.33#ibcon#about to read 4, iclass 37, count 0 2006.253.08:13:42.33#ibcon#read 4, iclass 37, count 0 2006.253.08:13:42.33#ibcon#about to read 5, iclass 37, count 0 2006.253.08:13:42.33#ibcon#read 5, iclass 37, count 0 2006.253.08:13:42.33#ibcon#about to read 6, iclass 37, count 0 2006.253.08:13:42.33#ibcon#read 6, iclass 37, count 0 2006.253.08:13:42.33#ibcon#end of sib2, iclass 37, count 0 2006.253.08:13:42.33#ibcon#*mode == 0, iclass 37, count 0 2006.253.08:13:42.33#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.253.08:13:42.33#ibcon#[28=FRQ=06,752.99\r\n] 2006.253.08:13:42.33#ibcon#*before write, iclass 37, count 0 2006.253.08:13:42.33#ibcon#enter sib2, iclass 37, count 0 2006.253.08:13:42.33#ibcon#flushed, iclass 37, count 0 2006.253.08:13:42.33#ibcon#about to write, iclass 37, count 0 2006.253.08:13:42.33#ibcon#wrote, iclass 37, count 0 2006.253.08:13:42.33#ibcon#about to read 3, iclass 37, count 0 2006.253.08:13:42.37#ibcon#read 3, iclass 37, count 0 2006.253.08:13:42.37#ibcon#about to read 4, iclass 37, count 0 2006.253.08:13:42.37#ibcon#read 4, iclass 37, count 0 2006.253.08:13:42.37#ibcon#about to read 5, iclass 37, count 0 2006.253.08:13:42.37#ibcon#read 5, iclass 37, count 0 2006.253.08:13:42.37#ibcon#about to read 6, iclass 37, count 0 2006.253.08:13:42.37#ibcon#read 6, iclass 37, count 0 2006.253.08:13:42.37#ibcon#end of sib2, iclass 37, count 0 2006.253.08:13:42.37#ibcon#*after write, iclass 37, count 0 2006.253.08:13:42.37#ibcon#*before return 0, iclass 37, count 0 2006.253.08:13:42.37#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.253.08:13:42.37#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.253.08:13:42.37#ibcon#about to clear, iclass 37 cls_cnt 0 2006.253.08:13:42.37#ibcon#cleared, iclass 37 cls_cnt 0 2006.253.08:13:42.37$vc4f8/vb=6,4 2006.253.08:13:42.37#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.253.08:13:42.37#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.253.08:13:42.37#ibcon#ireg 11 cls_cnt 2 2006.253.08:13:42.37#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.253.08:13:42.43#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.253.08:13:42.43#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.253.08:13:42.43#ibcon#enter wrdev, iclass 39, count 2 2006.253.08:13:42.43#ibcon#first serial, iclass 39, count 2 2006.253.08:13:42.43#ibcon#enter sib2, iclass 39, count 2 2006.253.08:13:42.43#ibcon#flushed, iclass 39, count 2 2006.253.08:13:42.43#ibcon#about to write, iclass 39, count 2 2006.253.08:13:42.43#ibcon#wrote, iclass 39, count 2 2006.253.08:13:42.43#ibcon#about to read 3, iclass 39, count 2 2006.253.08:13:42.45#ibcon#read 3, iclass 39, count 2 2006.253.08:13:42.45#ibcon#about to read 4, iclass 39, count 2 2006.253.08:13:42.45#ibcon#read 4, iclass 39, count 2 2006.253.08:13:42.45#ibcon#about to read 5, iclass 39, count 2 2006.253.08:13:42.45#ibcon#read 5, iclass 39, count 2 2006.253.08:13:42.45#ibcon#about to read 6, iclass 39, count 2 2006.253.08:13:42.45#ibcon#read 6, iclass 39, count 2 2006.253.08:13:42.45#ibcon#end of sib2, iclass 39, count 2 2006.253.08:13:42.45#ibcon#*mode == 0, iclass 39, count 2 2006.253.08:13:42.45#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.253.08:13:42.45#ibcon#[27=AT06-04\r\n] 2006.253.08:13:42.45#ibcon#*before write, iclass 39, count 2 2006.253.08:13:42.45#ibcon#enter sib2, iclass 39, count 2 2006.253.08:13:42.45#ibcon#flushed, iclass 39, count 2 2006.253.08:13:42.45#ibcon#about to write, iclass 39, count 2 2006.253.08:13:42.45#ibcon#wrote, iclass 39, count 2 2006.253.08:13:42.45#ibcon#about to read 3, iclass 39, count 2 2006.253.08:13:42.48#ibcon#read 3, iclass 39, count 2 2006.253.08:13:42.48#ibcon#about to read 4, iclass 39, count 2 2006.253.08:13:42.48#ibcon#read 4, iclass 39, count 2 2006.253.08:13:42.48#ibcon#about to read 5, iclass 39, count 2 2006.253.08:13:42.48#ibcon#read 5, iclass 39, count 2 2006.253.08:13:42.48#ibcon#about to read 6, iclass 39, count 2 2006.253.08:13:42.48#ibcon#read 6, iclass 39, count 2 2006.253.08:13:42.48#ibcon#end of sib2, iclass 39, count 2 2006.253.08:13:42.48#ibcon#*after write, iclass 39, count 2 2006.253.08:13:42.48#ibcon#*before return 0, iclass 39, count 2 2006.253.08:13:42.48#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.253.08:13:42.48#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.253.08:13:42.48#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.253.08:13:42.48#ibcon#ireg 7 cls_cnt 0 2006.253.08:13:42.48#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.253.08:13:42.60#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.253.08:13:42.60#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.253.08:13:42.60#ibcon#enter wrdev, iclass 39, count 0 2006.253.08:13:42.60#ibcon#first serial, iclass 39, count 0 2006.253.08:13:42.60#ibcon#enter sib2, iclass 39, count 0 2006.253.08:13:42.60#ibcon#flushed, iclass 39, count 0 2006.253.08:13:42.60#ibcon#about to write, iclass 39, count 0 2006.253.08:13:42.60#ibcon#wrote, iclass 39, count 0 2006.253.08:13:42.60#ibcon#about to read 3, iclass 39, count 0 2006.253.08:13:42.62#ibcon#read 3, iclass 39, count 0 2006.253.08:13:42.62#ibcon#about to read 4, iclass 39, count 0 2006.253.08:13:42.62#ibcon#read 4, iclass 39, count 0 2006.253.08:13:42.62#ibcon#about to read 5, iclass 39, count 0 2006.253.08:13:42.62#ibcon#read 5, iclass 39, count 0 2006.253.08:13:42.62#ibcon#about to read 6, iclass 39, count 0 2006.253.08:13:42.62#ibcon#read 6, iclass 39, count 0 2006.253.08:13:42.62#ibcon#end of sib2, iclass 39, count 0 2006.253.08:13:42.62#ibcon#*mode == 0, iclass 39, count 0 2006.253.08:13:42.62#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.253.08:13:42.62#ibcon#[27=USB\r\n] 2006.253.08:13:42.62#ibcon#*before write, iclass 39, count 0 2006.253.08:13:42.62#ibcon#enter sib2, iclass 39, count 0 2006.253.08:13:42.62#ibcon#flushed, iclass 39, count 0 2006.253.08:13:42.62#ibcon#about to write, iclass 39, count 0 2006.253.08:13:42.62#ibcon#wrote, iclass 39, count 0 2006.253.08:13:42.62#ibcon#about to read 3, iclass 39, count 0 2006.253.08:13:42.65#ibcon#read 3, iclass 39, count 0 2006.253.08:13:42.65#ibcon#about to read 4, iclass 39, count 0 2006.253.08:13:42.65#ibcon#read 4, iclass 39, count 0 2006.253.08:13:42.65#ibcon#about to read 5, iclass 39, count 0 2006.253.08:13:42.65#ibcon#read 5, iclass 39, count 0 2006.253.08:13:42.65#ibcon#about to read 6, iclass 39, count 0 2006.253.08:13:42.65#ibcon#read 6, iclass 39, count 0 2006.253.08:13:42.65#ibcon#end of sib2, iclass 39, count 0 2006.253.08:13:42.65#ibcon#*after write, iclass 39, count 0 2006.253.08:13:42.65#ibcon#*before return 0, iclass 39, count 0 2006.253.08:13:42.65#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.253.08:13:42.65#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.253.08:13:42.65#ibcon#about to clear, iclass 39 cls_cnt 0 2006.253.08:13:42.65#ibcon#cleared, iclass 39 cls_cnt 0 2006.253.08:13:42.65$vc4f8/vabw=wide 2006.253.08:13:42.65#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.253.08:13:42.65#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.253.08:13:42.65#ibcon#ireg 8 cls_cnt 0 2006.253.08:13:42.65#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.253.08:13:42.65#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.253.08:13:42.65#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.253.08:13:42.65#ibcon#enter wrdev, iclass 3, count 0 2006.253.08:13:42.65#ibcon#first serial, iclass 3, count 0 2006.253.08:13:42.65#ibcon#enter sib2, iclass 3, count 0 2006.253.08:13:42.65#ibcon#flushed, iclass 3, count 0 2006.253.08:13:42.65#ibcon#about to write, iclass 3, count 0 2006.253.08:13:42.65#ibcon#wrote, iclass 3, count 0 2006.253.08:13:42.65#ibcon#about to read 3, iclass 3, count 0 2006.253.08:13:42.67#ibcon#read 3, iclass 3, count 0 2006.253.08:13:42.67#ibcon#about to read 4, iclass 3, count 0 2006.253.08:13:42.67#ibcon#read 4, iclass 3, count 0 2006.253.08:13:42.67#ibcon#about to read 5, iclass 3, count 0 2006.253.08:13:42.67#ibcon#read 5, iclass 3, count 0 2006.253.08:13:42.67#ibcon#about to read 6, iclass 3, count 0 2006.253.08:13:42.67#ibcon#read 6, iclass 3, count 0 2006.253.08:13:42.67#ibcon#end of sib2, iclass 3, count 0 2006.253.08:13:42.67#ibcon#*mode == 0, iclass 3, count 0 2006.253.08:13:42.67#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.253.08:13:42.67#ibcon#[25=BW32\r\n] 2006.253.08:13:42.67#ibcon#*before write, iclass 3, count 0 2006.253.08:13:42.67#ibcon#enter sib2, iclass 3, count 0 2006.253.08:13:42.67#ibcon#flushed, iclass 3, count 0 2006.253.08:13:42.67#ibcon#about to write, iclass 3, count 0 2006.253.08:13:42.67#ibcon#wrote, iclass 3, count 0 2006.253.08:13:42.67#ibcon#about to read 3, iclass 3, count 0 2006.253.08:13:42.70#ibcon#read 3, iclass 3, count 0 2006.253.08:13:42.70#ibcon#about to read 4, iclass 3, count 0 2006.253.08:13:42.70#ibcon#read 4, iclass 3, count 0 2006.253.08:13:42.70#ibcon#about to read 5, iclass 3, count 0 2006.253.08:13:42.70#ibcon#read 5, iclass 3, count 0 2006.253.08:13:42.70#ibcon#about to read 6, iclass 3, count 0 2006.253.08:13:42.70#ibcon#read 6, iclass 3, count 0 2006.253.08:13:42.70#ibcon#end of sib2, iclass 3, count 0 2006.253.08:13:42.70#ibcon#*after write, iclass 3, count 0 2006.253.08:13:42.70#ibcon#*before return 0, iclass 3, count 0 2006.253.08:13:42.70#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.253.08:13:42.70#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.253.08:13:42.70#ibcon#about to clear, iclass 3 cls_cnt 0 2006.253.08:13:42.70#ibcon#cleared, iclass 3 cls_cnt 0 2006.253.08:13:42.70$vc4f8/vbbw=wide 2006.253.08:13:42.70#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.253.08:13:42.70#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.253.08:13:42.70#ibcon#ireg 8 cls_cnt 0 2006.253.08:13:42.70#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.253.08:13:42.77#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.253.08:13:42.77#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.253.08:13:42.77#ibcon#enter wrdev, iclass 5, count 0 2006.253.08:13:42.77#ibcon#first serial, iclass 5, count 0 2006.253.08:13:42.77#ibcon#enter sib2, iclass 5, count 0 2006.253.08:13:42.77#ibcon#flushed, iclass 5, count 0 2006.253.08:13:42.77#ibcon#about to write, iclass 5, count 0 2006.253.08:13:42.77#ibcon#wrote, iclass 5, count 0 2006.253.08:13:42.77#ibcon#about to read 3, iclass 5, count 0 2006.253.08:13:42.79#ibcon#read 3, iclass 5, count 0 2006.253.08:13:42.79#ibcon#about to read 4, iclass 5, count 0 2006.253.08:13:42.79#ibcon#read 4, iclass 5, count 0 2006.253.08:13:42.79#ibcon#about to read 5, iclass 5, count 0 2006.253.08:13:42.79#ibcon#read 5, iclass 5, count 0 2006.253.08:13:42.79#ibcon#about to read 6, iclass 5, count 0 2006.253.08:13:42.79#ibcon#read 6, iclass 5, count 0 2006.253.08:13:42.79#ibcon#end of sib2, iclass 5, count 0 2006.253.08:13:42.79#ibcon#*mode == 0, iclass 5, count 0 2006.253.08:13:42.79#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.253.08:13:42.79#ibcon#[27=BW32\r\n] 2006.253.08:13:42.79#ibcon#*before write, iclass 5, count 0 2006.253.08:13:42.79#ibcon#enter sib2, iclass 5, count 0 2006.253.08:13:42.79#ibcon#flushed, iclass 5, count 0 2006.253.08:13:42.79#ibcon#about to write, iclass 5, count 0 2006.253.08:13:42.79#ibcon#wrote, iclass 5, count 0 2006.253.08:13:42.79#ibcon#about to read 3, iclass 5, count 0 2006.253.08:13:42.82#ibcon#read 3, iclass 5, count 0 2006.253.08:13:42.82#ibcon#about to read 4, iclass 5, count 0 2006.253.08:13:42.82#ibcon#read 4, iclass 5, count 0 2006.253.08:13:42.82#ibcon#about to read 5, iclass 5, count 0 2006.253.08:13:42.82#ibcon#read 5, iclass 5, count 0 2006.253.08:13:42.82#ibcon#about to read 6, iclass 5, count 0 2006.253.08:13:42.82#ibcon#read 6, iclass 5, count 0 2006.253.08:13:42.82#ibcon#end of sib2, iclass 5, count 0 2006.253.08:13:42.82#ibcon#*after write, iclass 5, count 0 2006.253.08:13:42.82#ibcon#*before return 0, iclass 5, count 0 2006.253.08:13:42.82#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.253.08:13:42.82#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.253.08:13:42.82#ibcon#about to clear, iclass 5 cls_cnt 0 2006.253.08:13:42.82#ibcon#cleared, iclass 5 cls_cnt 0 2006.253.08:13:42.82$4f8m12a/ifd4f 2006.253.08:13:42.82$ifd4f/lo= 2006.253.08:13:42.82$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.253.08:13:42.82$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.253.08:13:42.82$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.253.08:13:42.82$ifd4f/patch= 2006.253.08:13:42.82$ifd4f/patch=lo1,a1,a2,a3,a4 2006.253.08:13:42.82$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.253.08:13:42.82$ifd4f/patch=lo3,a5,a6,a7,a8 2006.253.08:13:42.82$4f8m12a/"form=m,16.000,1:2 2006.253.08:13:42.82$4f8m12a/"tpicd 2006.253.08:13:42.82$4f8m12a/echo=off 2006.253.08:13:42.82$4f8m12a/xlog=off 2006.253.08:13:42.82:!2006.253.08:14:30 2006.253.08:14:09.14#trakl#Source acquired 2006.253.08:14:09.14#flagr#flagr/antenna,acquired 2006.253.08:14:30.00:preob 2006.253.08:14:31.14/onsource/TRACKING 2006.253.08:14:31.14:!2006.253.08:14:40 2006.253.08:14:40.00:data_valid=on 2006.253.08:14:40.00:midob 2006.253.08:14:40.14/onsource/TRACKING 2006.253.08:14:40.14/wx/30.91,1006.5,75 2006.253.08:14:40.24/cable/+6.3692E-03 2006.253.08:14:41.33/va/01,08,usb,yes,31,33 2006.253.08:14:41.33/va/02,07,usb,yes,31,33 2006.253.08:14:41.33/va/03,06,usb,yes,33,33 2006.253.08:14:41.33/va/04,07,usb,yes,32,35 2006.253.08:14:41.33/va/05,07,usb,yes,34,36 2006.253.08:14:41.33/va/06,07,usb,yes,29,29 2006.253.08:14:41.33/va/07,07,usb,yes,29,29 2006.253.08:14:41.33/va/08,07,usb,yes,32,31 2006.253.08:14:41.56/valo/01,532.99,yes,locked 2006.253.08:14:41.56/valo/02,572.99,yes,locked 2006.253.08:14:41.56/valo/03,672.99,yes,locked 2006.253.08:14:41.56/valo/04,832.99,yes,locked 2006.253.08:14:41.56/valo/05,652.99,yes,locked 2006.253.08:14:41.56/valo/06,772.99,yes,locked 2006.253.08:14:41.56/valo/07,832.99,yes,locked 2006.253.08:14:41.56/valo/08,852.99,yes,locked 2006.253.08:14:42.65/vb/01,04,usb,yes,30,29 2006.253.08:14:42.65/vb/02,05,usb,yes,28,29 2006.253.08:14:42.65/vb/03,04,usb,yes,28,32 2006.253.08:14:42.65/vb/04,04,usb,yes,29,29 2006.253.08:14:42.65/vb/05,04,usb,yes,28,32 2006.253.08:14:42.65/vb/06,04,usb,yes,29,32 2006.253.08:14:42.65/vb/07,04,usb,yes,31,31 2006.253.08:14:42.65/vb/08,04,usb,yes,28,32 2006.253.08:14:42.89/vblo/01,632.99,yes,locked 2006.253.08:14:42.89/vblo/02,640.99,yes,locked 2006.253.08:14:42.89/vblo/03,656.99,yes,locked 2006.253.08:14:42.89/vblo/04,712.99,yes,locked 2006.253.08:14:42.89/vblo/05,744.99,yes,locked 2006.253.08:14:42.89/vblo/06,752.99,yes,locked 2006.253.08:14:42.89/vblo/07,734.99,yes,locked 2006.253.08:14:42.89/vblo/08,744.99,yes,locked 2006.253.08:14:43.04/vabw/8 2006.253.08:14:43.19/vbbw/8 2006.253.08:14:43.37/xfe/off,on,14.5 2006.253.08:14:43.74/ifatt/23,28,28,28 2006.253.08:14:44.08/fmout-gps/S +4.72E-07 2006.253.08:14:44.12:!2006.253.08:15:40 2006.253.08:15:40.00:data_valid=off 2006.253.08:15:40.00:postob 2006.253.08:15:40.08/cable/+6.3682E-03 2006.253.08:15:40.09/wx/30.90,1006.5,74 2006.253.08:15:41.08/fmout-gps/S +4.72E-07 2006.253.08:15:41.08:scan_name=253-0816,k06253,60 2006.253.08:15:41.08:source=0955+476,095819.67,472507.8,2000.0,ccw 2006.253.08:15:41.14#flagr#flagr/antenna,new-source 2006.253.08:15:42.14:checkk5 2006.253.08:15:42.52/chk_autoobs//k5ts1/ autoobs is running! 2006.253.08:15:42.90/chk_autoobs//k5ts2/ autoobs is running! 2006.253.08:15:43.27/chk_autoobs//k5ts3/ autoobs is running! 2006.253.08:15:43.65/chk_autoobs//k5ts4/ autoobs is running! 2006.253.08:15:44.02/chk_obsdata//k5ts1/T2530814??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.08:15:44.39/chk_obsdata//k5ts2/T2530814??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.08:15:44.76/chk_obsdata//k5ts3/T2530814??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.08:15:45.13/chk_obsdata//k5ts4/T2530814??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.08:15:45.85/k5log//k5ts1_log_newline 2006.253.08:15:46.55/k5log//k5ts2_log_newline 2006.253.08:15:47.25/k5log//k5ts3_log_newline 2006.253.08:15:47.95/k5log//k5ts4_log_newline 2006.253.08:15:47.97/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.253.08:15:47.97:4f8m12a=2 2006.253.08:15:47.97$4f8m12a/echo=on 2006.253.08:15:47.97$4f8m12a/pcalon 2006.253.08:15:47.97$pcalon/"no phase cal control is implemented here 2006.253.08:15:47.97$4f8m12a/"tpicd=stop 2006.253.08:15:47.97$4f8m12a/vc4f8 2006.253.08:15:47.97$vc4f8/valo=1,532.99 2006.253.08:15:47.98#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.253.08:15:47.98#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.253.08:15:47.98#ibcon#ireg 17 cls_cnt 0 2006.253.08:15:47.98#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.253.08:15:47.98#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.253.08:15:47.98#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.253.08:15:47.98#ibcon#enter wrdev, iclass 26, count 0 2006.253.08:15:47.98#ibcon#first serial, iclass 26, count 0 2006.253.08:15:47.98#ibcon#enter sib2, iclass 26, count 0 2006.253.08:15:47.98#ibcon#flushed, iclass 26, count 0 2006.253.08:15:47.98#ibcon#about to write, iclass 26, count 0 2006.253.08:15:47.98#ibcon#wrote, iclass 26, count 0 2006.253.08:15:47.98#ibcon#about to read 3, iclass 26, count 0 2006.253.08:15:48.02#ibcon#read 3, iclass 26, count 0 2006.253.08:15:48.02#ibcon#about to read 4, iclass 26, count 0 2006.253.08:15:48.02#ibcon#read 4, iclass 26, count 0 2006.253.08:15:48.02#ibcon#about to read 5, iclass 26, count 0 2006.253.08:15:48.02#ibcon#read 5, iclass 26, count 0 2006.253.08:15:48.02#ibcon#about to read 6, iclass 26, count 0 2006.253.08:15:48.02#ibcon#read 6, iclass 26, count 0 2006.253.08:15:48.02#ibcon#end of sib2, iclass 26, count 0 2006.253.08:15:48.02#ibcon#*mode == 0, iclass 26, count 0 2006.253.08:15:48.02#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.253.08:15:48.02#ibcon#[26=FRQ=01,532.99\r\n] 2006.253.08:15:48.02#ibcon#*before write, iclass 26, count 0 2006.253.08:15:48.02#ibcon#enter sib2, iclass 26, count 0 2006.253.08:15:48.02#ibcon#flushed, iclass 26, count 0 2006.253.08:15:48.02#ibcon#about to write, iclass 26, count 0 2006.253.08:15:48.02#ibcon#wrote, iclass 26, count 0 2006.253.08:15:48.02#ibcon#about to read 3, iclass 26, count 0 2006.253.08:15:48.07#ibcon#read 3, iclass 26, count 0 2006.253.08:15:48.07#ibcon#about to read 4, iclass 26, count 0 2006.253.08:15:48.07#ibcon#read 4, iclass 26, count 0 2006.253.08:15:48.07#ibcon#about to read 5, iclass 26, count 0 2006.253.08:15:48.07#ibcon#read 5, iclass 26, count 0 2006.253.08:15:48.07#ibcon#about to read 6, iclass 26, count 0 2006.253.08:15:48.07#ibcon#read 6, iclass 26, count 0 2006.253.08:15:48.07#ibcon#end of sib2, iclass 26, count 0 2006.253.08:15:48.07#ibcon#*after write, iclass 26, count 0 2006.253.08:15:48.07#ibcon#*before return 0, iclass 26, count 0 2006.253.08:15:48.07#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.253.08:15:48.07#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.253.08:15:48.07#ibcon#about to clear, iclass 26 cls_cnt 0 2006.253.08:15:48.07#ibcon#cleared, iclass 26 cls_cnt 0 2006.253.08:15:48.07$vc4f8/va=1,8 2006.253.08:15:48.07#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.253.08:15:48.07#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.253.08:15:48.07#ibcon#ireg 11 cls_cnt 2 2006.253.08:15:48.07#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.253.08:15:48.07#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.253.08:15:48.07#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.253.08:15:48.07#ibcon#enter wrdev, iclass 28, count 2 2006.253.08:15:48.07#ibcon#first serial, iclass 28, count 2 2006.253.08:15:48.07#ibcon#enter sib2, iclass 28, count 2 2006.253.08:15:48.07#ibcon#flushed, iclass 28, count 2 2006.253.08:15:48.07#ibcon#about to write, iclass 28, count 2 2006.253.08:15:48.07#ibcon#wrote, iclass 28, count 2 2006.253.08:15:48.07#ibcon#about to read 3, iclass 28, count 2 2006.253.08:15:48.09#ibcon#read 3, iclass 28, count 2 2006.253.08:15:48.09#ibcon#about to read 4, iclass 28, count 2 2006.253.08:15:48.09#ibcon#read 4, iclass 28, count 2 2006.253.08:15:48.09#ibcon#about to read 5, iclass 28, count 2 2006.253.08:15:48.09#ibcon#read 5, iclass 28, count 2 2006.253.08:15:48.09#ibcon#about to read 6, iclass 28, count 2 2006.253.08:15:48.09#ibcon#read 6, iclass 28, count 2 2006.253.08:15:48.09#ibcon#end of sib2, iclass 28, count 2 2006.253.08:15:48.09#ibcon#*mode == 0, iclass 28, count 2 2006.253.08:15:48.09#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.253.08:15:48.09#ibcon#[25=AT01-08\r\n] 2006.253.08:15:48.09#ibcon#*before write, iclass 28, count 2 2006.253.08:15:48.09#ibcon#enter sib2, iclass 28, count 2 2006.253.08:15:48.09#ibcon#flushed, iclass 28, count 2 2006.253.08:15:48.09#ibcon#about to write, iclass 28, count 2 2006.253.08:15:48.09#ibcon#wrote, iclass 28, count 2 2006.253.08:15:48.09#ibcon#about to read 3, iclass 28, count 2 2006.253.08:15:48.12#ibcon#read 3, iclass 28, count 2 2006.253.08:15:48.12#ibcon#about to read 4, iclass 28, count 2 2006.253.08:15:48.12#ibcon#read 4, iclass 28, count 2 2006.253.08:15:48.12#ibcon#about to read 5, iclass 28, count 2 2006.253.08:15:48.12#ibcon#read 5, iclass 28, count 2 2006.253.08:15:48.12#ibcon#about to read 6, iclass 28, count 2 2006.253.08:15:48.12#ibcon#read 6, iclass 28, count 2 2006.253.08:15:48.12#ibcon#end of sib2, iclass 28, count 2 2006.253.08:15:48.12#ibcon#*after write, iclass 28, count 2 2006.253.08:15:48.12#ibcon#*before return 0, iclass 28, count 2 2006.253.08:15:48.12#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.253.08:15:48.12#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.253.08:15:48.12#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.253.08:15:48.12#ibcon#ireg 7 cls_cnt 0 2006.253.08:15:48.12#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.253.08:15:48.24#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.253.08:15:48.24#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.253.08:15:48.24#ibcon#enter wrdev, iclass 28, count 0 2006.253.08:15:48.24#ibcon#first serial, iclass 28, count 0 2006.253.08:15:48.24#ibcon#enter sib2, iclass 28, count 0 2006.253.08:15:48.24#ibcon#flushed, iclass 28, count 0 2006.253.08:15:48.24#ibcon#about to write, iclass 28, count 0 2006.253.08:15:48.24#ibcon#wrote, iclass 28, count 0 2006.253.08:15:48.24#ibcon#about to read 3, iclass 28, count 0 2006.253.08:15:48.26#ibcon#read 3, iclass 28, count 0 2006.253.08:15:48.26#ibcon#about to read 4, iclass 28, count 0 2006.253.08:15:48.26#ibcon#read 4, iclass 28, count 0 2006.253.08:15:48.26#ibcon#about to read 5, iclass 28, count 0 2006.253.08:15:48.26#ibcon#read 5, iclass 28, count 0 2006.253.08:15:48.26#ibcon#about to read 6, iclass 28, count 0 2006.253.08:15:48.26#ibcon#read 6, iclass 28, count 0 2006.253.08:15:48.26#ibcon#end of sib2, iclass 28, count 0 2006.253.08:15:48.26#ibcon#*mode == 0, iclass 28, count 0 2006.253.08:15:48.26#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.253.08:15:48.26#ibcon#[25=USB\r\n] 2006.253.08:15:48.26#ibcon#*before write, iclass 28, count 0 2006.253.08:15:48.26#ibcon#enter sib2, iclass 28, count 0 2006.253.08:15:48.26#ibcon#flushed, iclass 28, count 0 2006.253.08:15:48.26#ibcon#about to write, iclass 28, count 0 2006.253.08:15:48.26#ibcon#wrote, iclass 28, count 0 2006.253.08:15:48.26#ibcon#about to read 3, iclass 28, count 0 2006.253.08:15:48.29#ibcon#read 3, iclass 28, count 0 2006.253.08:15:48.29#ibcon#about to read 4, iclass 28, count 0 2006.253.08:15:48.29#ibcon#read 4, iclass 28, count 0 2006.253.08:15:48.29#ibcon#about to read 5, iclass 28, count 0 2006.253.08:15:48.29#ibcon#read 5, iclass 28, count 0 2006.253.08:15:48.29#ibcon#about to read 6, iclass 28, count 0 2006.253.08:15:48.29#ibcon#read 6, iclass 28, count 0 2006.253.08:15:48.29#ibcon#end of sib2, iclass 28, count 0 2006.253.08:15:48.29#ibcon#*after write, iclass 28, count 0 2006.253.08:15:48.29#ibcon#*before return 0, iclass 28, count 0 2006.253.08:15:48.29#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.253.08:15:48.29#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.253.08:15:48.29#ibcon#about to clear, iclass 28 cls_cnt 0 2006.253.08:15:48.29#ibcon#cleared, iclass 28 cls_cnt 0 2006.253.08:15:48.29$vc4f8/valo=2,572.99 2006.253.08:15:48.29#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.253.08:15:48.29#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.253.08:15:48.29#ibcon#ireg 17 cls_cnt 0 2006.253.08:15:48.29#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.253.08:15:48.29#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.253.08:15:48.29#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.253.08:15:48.29#ibcon#enter wrdev, iclass 30, count 0 2006.253.08:15:48.29#ibcon#first serial, iclass 30, count 0 2006.253.08:15:48.29#ibcon#enter sib2, iclass 30, count 0 2006.253.08:15:48.29#ibcon#flushed, iclass 30, count 0 2006.253.08:15:48.29#ibcon#about to write, iclass 30, count 0 2006.253.08:15:48.29#ibcon#wrote, iclass 30, count 0 2006.253.08:15:48.29#ibcon#about to read 3, iclass 30, count 0 2006.253.08:15:48.31#ibcon#read 3, iclass 30, count 0 2006.253.08:15:48.31#ibcon#about to read 4, iclass 30, count 0 2006.253.08:15:48.31#ibcon#read 4, iclass 30, count 0 2006.253.08:15:48.31#ibcon#about to read 5, iclass 30, count 0 2006.253.08:15:48.31#ibcon#read 5, iclass 30, count 0 2006.253.08:15:48.31#ibcon#about to read 6, iclass 30, count 0 2006.253.08:15:48.31#ibcon#read 6, iclass 30, count 0 2006.253.08:15:48.31#ibcon#end of sib2, iclass 30, count 0 2006.253.08:15:48.31#ibcon#*mode == 0, iclass 30, count 0 2006.253.08:15:48.31#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.253.08:15:48.31#ibcon#[26=FRQ=02,572.99\r\n] 2006.253.08:15:48.31#ibcon#*before write, iclass 30, count 0 2006.253.08:15:48.31#ibcon#enter sib2, iclass 30, count 0 2006.253.08:15:48.31#ibcon#flushed, iclass 30, count 0 2006.253.08:15:48.31#ibcon#about to write, iclass 30, count 0 2006.253.08:15:48.31#ibcon#wrote, iclass 30, count 0 2006.253.08:15:48.31#ibcon#about to read 3, iclass 30, count 0 2006.253.08:15:48.36#ibcon#read 3, iclass 30, count 0 2006.253.08:15:48.36#ibcon#about to read 4, iclass 30, count 0 2006.253.08:15:48.36#ibcon#read 4, iclass 30, count 0 2006.253.08:15:48.36#ibcon#about to read 5, iclass 30, count 0 2006.253.08:15:48.36#ibcon#read 5, iclass 30, count 0 2006.253.08:15:48.36#ibcon#about to read 6, iclass 30, count 0 2006.253.08:15:48.36#ibcon#read 6, iclass 30, count 0 2006.253.08:15:48.36#ibcon#end of sib2, iclass 30, count 0 2006.253.08:15:48.36#ibcon#*after write, iclass 30, count 0 2006.253.08:15:48.36#ibcon#*before return 0, iclass 30, count 0 2006.253.08:15:48.36#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.253.08:15:48.36#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.253.08:15:48.36#ibcon#about to clear, iclass 30 cls_cnt 0 2006.253.08:15:48.36#ibcon#cleared, iclass 30 cls_cnt 0 2006.253.08:15:48.36$vc4f8/va=2,7 2006.253.08:15:48.36#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.253.08:15:48.36#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.253.08:15:48.36#ibcon#ireg 11 cls_cnt 2 2006.253.08:15:48.36#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.253.08:15:48.41#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.253.08:15:48.41#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.253.08:15:48.41#ibcon#enter wrdev, iclass 32, count 2 2006.253.08:15:48.41#ibcon#first serial, iclass 32, count 2 2006.253.08:15:48.41#ibcon#enter sib2, iclass 32, count 2 2006.253.08:15:48.41#ibcon#flushed, iclass 32, count 2 2006.253.08:15:48.41#ibcon#about to write, iclass 32, count 2 2006.253.08:15:48.41#ibcon#wrote, iclass 32, count 2 2006.253.08:15:48.41#ibcon#about to read 3, iclass 32, count 2 2006.253.08:15:48.43#ibcon#read 3, iclass 32, count 2 2006.253.08:15:48.43#ibcon#about to read 4, iclass 32, count 2 2006.253.08:15:48.43#ibcon#read 4, iclass 32, count 2 2006.253.08:15:48.43#ibcon#about to read 5, iclass 32, count 2 2006.253.08:15:48.43#ibcon#read 5, iclass 32, count 2 2006.253.08:15:48.43#ibcon#about to read 6, iclass 32, count 2 2006.253.08:15:48.43#ibcon#read 6, iclass 32, count 2 2006.253.08:15:48.43#ibcon#end of sib2, iclass 32, count 2 2006.253.08:15:48.43#ibcon#*mode == 0, iclass 32, count 2 2006.253.08:15:48.43#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.253.08:15:48.43#ibcon#[25=AT02-07\r\n] 2006.253.08:15:48.43#ibcon#*before write, iclass 32, count 2 2006.253.08:15:48.43#ibcon#enter sib2, iclass 32, count 2 2006.253.08:15:48.43#ibcon#flushed, iclass 32, count 2 2006.253.08:15:48.43#ibcon#about to write, iclass 32, count 2 2006.253.08:15:48.43#ibcon#wrote, iclass 32, count 2 2006.253.08:15:48.43#ibcon#about to read 3, iclass 32, count 2 2006.253.08:15:48.46#ibcon#read 3, iclass 32, count 2 2006.253.08:15:48.46#ibcon#about to read 4, iclass 32, count 2 2006.253.08:15:48.46#ibcon#read 4, iclass 32, count 2 2006.253.08:15:48.46#ibcon#about to read 5, iclass 32, count 2 2006.253.08:15:48.46#ibcon#read 5, iclass 32, count 2 2006.253.08:15:48.46#ibcon#about to read 6, iclass 32, count 2 2006.253.08:15:48.46#ibcon#read 6, iclass 32, count 2 2006.253.08:15:48.46#ibcon#end of sib2, iclass 32, count 2 2006.253.08:15:48.46#ibcon#*after write, iclass 32, count 2 2006.253.08:15:48.46#ibcon#*before return 0, iclass 32, count 2 2006.253.08:15:48.46#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.253.08:15:48.46#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.253.08:15:48.46#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.253.08:15:48.46#ibcon#ireg 7 cls_cnt 0 2006.253.08:15:48.46#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.253.08:15:48.58#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.253.08:15:48.58#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.253.08:15:48.58#ibcon#enter wrdev, iclass 32, count 0 2006.253.08:15:48.58#ibcon#first serial, iclass 32, count 0 2006.253.08:15:48.58#ibcon#enter sib2, iclass 32, count 0 2006.253.08:15:48.58#ibcon#flushed, iclass 32, count 0 2006.253.08:15:48.58#ibcon#about to write, iclass 32, count 0 2006.253.08:15:48.58#ibcon#wrote, iclass 32, count 0 2006.253.08:15:48.58#ibcon#about to read 3, iclass 32, count 0 2006.253.08:15:48.60#ibcon#read 3, iclass 32, count 0 2006.253.08:15:48.60#ibcon#about to read 4, iclass 32, count 0 2006.253.08:15:48.60#ibcon#read 4, iclass 32, count 0 2006.253.08:15:48.60#ibcon#about to read 5, iclass 32, count 0 2006.253.08:15:48.60#ibcon#read 5, iclass 32, count 0 2006.253.08:15:48.60#ibcon#about to read 6, iclass 32, count 0 2006.253.08:15:48.60#ibcon#read 6, iclass 32, count 0 2006.253.08:15:48.60#ibcon#end of sib2, iclass 32, count 0 2006.253.08:15:48.60#ibcon#*mode == 0, iclass 32, count 0 2006.253.08:15:48.60#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.253.08:15:48.60#ibcon#[25=USB\r\n] 2006.253.08:15:48.60#ibcon#*before write, iclass 32, count 0 2006.253.08:15:48.60#ibcon#enter sib2, iclass 32, count 0 2006.253.08:15:48.60#ibcon#flushed, iclass 32, count 0 2006.253.08:15:48.60#ibcon#about to write, iclass 32, count 0 2006.253.08:15:48.60#ibcon#wrote, iclass 32, count 0 2006.253.08:15:48.60#ibcon#about to read 3, iclass 32, count 0 2006.253.08:15:48.63#ibcon#read 3, iclass 32, count 0 2006.253.08:15:48.63#ibcon#about to read 4, iclass 32, count 0 2006.253.08:15:48.63#ibcon#read 4, iclass 32, count 0 2006.253.08:15:48.63#ibcon#about to read 5, iclass 32, count 0 2006.253.08:15:48.63#ibcon#read 5, iclass 32, count 0 2006.253.08:15:48.63#ibcon#about to read 6, iclass 32, count 0 2006.253.08:15:48.63#ibcon#read 6, iclass 32, count 0 2006.253.08:15:48.63#ibcon#end of sib2, iclass 32, count 0 2006.253.08:15:48.63#ibcon#*after write, iclass 32, count 0 2006.253.08:15:48.63#ibcon#*before return 0, iclass 32, count 0 2006.253.08:15:48.63#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.253.08:15:48.63#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.253.08:15:48.63#ibcon#about to clear, iclass 32 cls_cnt 0 2006.253.08:15:48.63#ibcon#cleared, iclass 32 cls_cnt 0 2006.253.08:15:48.63$vc4f8/valo=3,672.99 2006.253.08:15:48.63#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.253.08:15:48.63#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.253.08:15:48.63#ibcon#ireg 17 cls_cnt 0 2006.253.08:15:48.63#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.253.08:15:48.63#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.253.08:15:48.63#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.253.08:15:48.63#ibcon#enter wrdev, iclass 34, count 0 2006.253.08:15:48.63#ibcon#first serial, iclass 34, count 0 2006.253.08:15:48.63#ibcon#enter sib2, iclass 34, count 0 2006.253.08:15:48.63#ibcon#flushed, iclass 34, count 0 2006.253.08:15:48.63#ibcon#about to write, iclass 34, count 0 2006.253.08:15:48.63#ibcon#wrote, iclass 34, count 0 2006.253.08:15:48.63#ibcon#about to read 3, iclass 34, count 0 2006.253.08:15:48.65#ibcon#read 3, iclass 34, count 0 2006.253.08:15:48.65#ibcon#about to read 4, iclass 34, count 0 2006.253.08:15:48.65#ibcon#read 4, iclass 34, count 0 2006.253.08:15:48.65#ibcon#about to read 5, iclass 34, count 0 2006.253.08:15:48.65#ibcon#read 5, iclass 34, count 0 2006.253.08:15:48.65#ibcon#about to read 6, iclass 34, count 0 2006.253.08:15:48.65#ibcon#read 6, iclass 34, count 0 2006.253.08:15:48.65#ibcon#end of sib2, iclass 34, count 0 2006.253.08:15:48.65#ibcon#*mode == 0, iclass 34, count 0 2006.253.08:15:48.65#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.253.08:15:48.65#ibcon#[26=FRQ=03,672.99\r\n] 2006.253.08:15:48.65#ibcon#*before write, iclass 34, count 0 2006.253.08:15:48.65#ibcon#enter sib2, iclass 34, count 0 2006.253.08:15:48.65#ibcon#flushed, iclass 34, count 0 2006.253.08:15:48.65#ibcon#about to write, iclass 34, count 0 2006.253.08:15:48.65#ibcon#wrote, iclass 34, count 0 2006.253.08:15:48.65#ibcon#about to read 3, iclass 34, count 0 2006.253.08:15:48.70#ibcon#read 3, iclass 34, count 0 2006.253.08:15:48.70#ibcon#about to read 4, iclass 34, count 0 2006.253.08:15:48.70#ibcon#read 4, iclass 34, count 0 2006.253.08:15:48.70#ibcon#about to read 5, iclass 34, count 0 2006.253.08:15:48.70#ibcon#read 5, iclass 34, count 0 2006.253.08:15:48.70#ibcon#about to read 6, iclass 34, count 0 2006.253.08:15:48.70#ibcon#read 6, iclass 34, count 0 2006.253.08:15:48.70#ibcon#end of sib2, iclass 34, count 0 2006.253.08:15:48.70#ibcon#*after write, iclass 34, count 0 2006.253.08:15:48.70#ibcon#*before return 0, iclass 34, count 0 2006.253.08:15:48.70#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.253.08:15:48.70#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.253.08:15:48.70#ibcon#about to clear, iclass 34 cls_cnt 0 2006.253.08:15:48.70#ibcon#cleared, iclass 34 cls_cnt 0 2006.253.08:15:48.70$vc4f8/va=3,6 2006.253.08:15:48.70#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.253.08:15:48.70#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.253.08:15:48.70#ibcon#ireg 11 cls_cnt 2 2006.253.08:15:48.70#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.253.08:15:48.75#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.253.08:15:48.75#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.253.08:15:48.75#ibcon#enter wrdev, iclass 36, count 2 2006.253.08:15:48.75#ibcon#first serial, iclass 36, count 2 2006.253.08:15:48.75#ibcon#enter sib2, iclass 36, count 2 2006.253.08:15:48.75#ibcon#flushed, iclass 36, count 2 2006.253.08:15:48.75#ibcon#about to write, iclass 36, count 2 2006.253.08:15:48.75#ibcon#wrote, iclass 36, count 2 2006.253.08:15:48.75#ibcon#about to read 3, iclass 36, count 2 2006.253.08:15:48.77#ibcon#read 3, iclass 36, count 2 2006.253.08:15:48.77#ibcon#about to read 4, iclass 36, count 2 2006.253.08:15:48.77#ibcon#read 4, iclass 36, count 2 2006.253.08:15:48.77#ibcon#about to read 5, iclass 36, count 2 2006.253.08:15:48.77#ibcon#read 5, iclass 36, count 2 2006.253.08:15:48.77#ibcon#about to read 6, iclass 36, count 2 2006.253.08:15:48.77#ibcon#read 6, iclass 36, count 2 2006.253.08:15:48.77#ibcon#end of sib2, iclass 36, count 2 2006.253.08:15:48.77#ibcon#*mode == 0, iclass 36, count 2 2006.253.08:15:48.77#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.253.08:15:48.77#ibcon#[25=AT03-06\r\n] 2006.253.08:15:48.77#ibcon#*before write, iclass 36, count 2 2006.253.08:15:48.77#ibcon#enter sib2, iclass 36, count 2 2006.253.08:15:48.77#ibcon#flushed, iclass 36, count 2 2006.253.08:15:48.77#ibcon#about to write, iclass 36, count 2 2006.253.08:15:48.77#ibcon#wrote, iclass 36, count 2 2006.253.08:15:48.77#ibcon#about to read 3, iclass 36, count 2 2006.253.08:15:48.80#ibcon#read 3, iclass 36, count 2 2006.253.08:15:48.80#ibcon#about to read 4, iclass 36, count 2 2006.253.08:15:48.80#ibcon#read 4, iclass 36, count 2 2006.253.08:15:48.80#ibcon#about to read 5, iclass 36, count 2 2006.253.08:15:48.80#ibcon#read 5, iclass 36, count 2 2006.253.08:15:48.80#ibcon#about to read 6, iclass 36, count 2 2006.253.08:15:48.80#ibcon#read 6, iclass 36, count 2 2006.253.08:15:48.80#ibcon#end of sib2, iclass 36, count 2 2006.253.08:15:48.80#ibcon#*after write, iclass 36, count 2 2006.253.08:15:48.80#ibcon#*before return 0, iclass 36, count 2 2006.253.08:15:48.80#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.253.08:15:48.80#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.253.08:15:48.80#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.253.08:15:48.80#ibcon#ireg 7 cls_cnt 0 2006.253.08:15:48.80#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.253.08:15:48.92#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.253.08:15:48.92#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.253.08:15:48.92#ibcon#enter wrdev, iclass 36, count 0 2006.253.08:15:48.92#ibcon#first serial, iclass 36, count 0 2006.253.08:15:48.92#ibcon#enter sib2, iclass 36, count 0 2006.253.08:15:48.92#ibcon#flushed, iclass 36, count 0 2006.253.08:15:48.92#ibcon#about to write, iclass 36, count 0 2006.253.08:15:48.92#ibcon#wrote, iclass 36, count 0 2006.253.08:15:48.92#ibcon#about to read 3, iclass 36, count 0 2006.253.08:15:48.94#ibcon#read 3, iclass 36, count 0 2006.253.08:15:48.94#ibcon#about to read 4, iclass 36, count 0 2006.253.08:15:48.94#ibcon#read 4, iclass 36, count 0 2006.253.08:15:48.94#ibcon#about to read 5, iclass 36, count 0 2006.253.08:15:48.94#ibcon#read 5, iclass 36, count 0 2006.253.08:15:48.94#ibcon#about to read 6, iclass 36, count 0 2006.253.08:15:48.94#ibcon#read 6, iclass 36, count 0 2006.253.08:15:48.94#ibcon#end of sib2, iclass 36, count 0 2006.253.08:15:48.94#ibcon#*mode == 0, iclass 36, count 0 2006.253.08:15:48.94#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.253.08:15:48.94#ibcon#[25=USB\r\n] 2006.253.08:15:48.94#ibcon#*before write, iclass 36, count 0 2006.253.08:15:48.94#ibcon#enter sib2, iclass 36, count 0 2006.253.08:15:48.94#ibcon#flushed, iclass 36, count 0 2006.253.08:15:48.94#ibcon#about to write, iclass 36, count 0 2006.253.08:15:48.94#ibcon#wrote, iclass 36, count 0 2006.253.08:15:48.94#ibcon#about to read 3, iclass 36, count 0 2006.253.08:15:48.97#ibcon#read 3, iclass 36, count 0 2006.253.08:15:48.97#ibcon#about to read 4, iclass 36, count 0 2006.253.08:15:48.97#ibcon#read 4, iclass 36, count 0 2006.253.08:15:48.97#ibcon#about to read 5, iclass 36, count 0 2006.253.08:15:48.97#ibcon#read 5, iclass 36, count 0 2006.253.08:15:48.97#ibcon#about to read 6, iclass 36, count 0 2006.253.08:15:48.97#ibcon#read 6, iclass 36, count 0 2006.253.08:15:48.97#ibcon#end of sib2, iclass 36, count 0 2006.253.08:15:48.97#ibcon#*after write, iclass 36, count 0 2006.253.08:15:48.97#ibcon#*before return 0, iclass 36, count 0 2006.253.08:15:48.97#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.253.08:15:48.97#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.253.08:15:48.97#ibcon#about to clear, iclass 36 cls_cnt 0 2006.253.08:15:48.97#ibcon#cleared, iclass 36 cls_cnt 0 2006.253.08:15:48.97$vc4f8/valo=4,832.99 2006.253.08:15:48.97#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.253.08:15:48.97#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.253.08:15:48.97#ibcon#ireg 17 cls_cnt 0 2006.253.08:15:48.97#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.253.08:15:48.97#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.253.08:15:48.97#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.253.08:15:48.97#ibcon#enter wrdev, iclass 38, count 0 2006.253.08:15:48.97#ibcon#first serial, iclass 38, count 0 2006.253.08:15:48.97#ibcon#enter sib2, iclass 38, count 0 2006.253.08:15:48.97#ibcon#flushed, iclass 38, count 0 2006.253.08:15:48.97#ibcon#about to write, iclass 38, count 0 2006.253.08:15:48.97#ibcon#wrote, iclass 38, count 0 2006.253.08:15:48.97#ibcon#about to read 3, iclass 38, count 0 2006.253.08:15:48.99#ibcon#read 3, iclass 38, count 0 2006.253.08:15:48.99#ibcon#about to read 4, iclass 38, count 0 2006.253.08:15:48.99#ibcon#read 4, iclass 38, count 0 2006.253.08:15:48.99#ibcon#about to read 5, iclass 38, count 0 2006.253.08:15:48.99#ibcon#read 5, iclass 38, count 0 2006.253.08:15:48.99#ibcon#about to read 6, iclass 38, count 0 2006.253.08:15:48.99#ibcon#read 6, iclass 38, count 0 2006.253.08:15:48.99#ibcon#end of sib2, iclass 38, count 0 2006.253.08:15:48.99#ibcon#*mode == 0, iclass 38, count 0 2006.253.08:15:48.99#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.253.08:15:48.99#ibcon#[26=FRQ=04,832.99\r\n] 2006.253.08:15:48.99#ibcon#*before write, iclass 38, count 0 2006.253.08:15:48.99#ibcon#enter sib2, iclass 38, count 0 2006.253.08:15:48.99#ibcon#flushed, iclass 38, count 0 2006.253.08:15:48.99#ibcon#about to write, iclass 38, count 0 2006.253.08:15:48.99#ibcon#wrote, iclass 38, count 0 2006.253.08:15:48.99#ibcon#about to read 3, iclass 38, count 0 2006.253.08:15:49.04#ibcon#read 3, iclass 38, count 0 2006.253.08:15:49.04#ibcon#about to read 4, iclass 38, count 0 2006.253.08:15:49.04#ibcon#read 4, iclass 38, count 0 2006.253.08:15:49.04#ibcon#about to read 5, iclass 38, count 0 2006.253.08:15:49.04#ibcon#read 5, iclass 38, count 0 2006.253.08:15:49.04#ibcon#about to read 6, iclass 38, count 0 2006.253.08:15:49.04#ibcon#read 6, iclass 38, count 0 2006.253.08:15:49.04#ibcon#end of sib2, iclass 38, count 0 2006.253.08:15:49.04#ibcon#*after write, iclass 38, count 0 2006.253.08:15:49.04#ibcon#*before return 0, iclass 38, count 0 2006.253.08:15:49.04#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.253.08:15:49.04#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.253.08:15:49.04#ibcon#about to clear, iclass 38 cls_cnt 0 2006.253.08:15:49.04#ibcon#cleared, iclass 38 cls_cnt 0 2006.253.08:15:49.04$vc4f8/va=4,7 2006.253.08:15:49.04#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.253.08:15:49.04#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.253.08:15:49.04#ibcon#ireg 11 cls_cnt 2 2006.253.08:15:49.04#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.253.08:15:49.09#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.253.08:15:49.09#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.253.08:15:49.09#ibcon#enter wrdev, iclass 40, count 2 2006.253.08:15:49.09#ibcon#first serial, iclass 40, count 2 2006.253.08:15:49.09#ibcon#enter sib2, iclass 40, count 2 2006.253.08:15:49.09#ibcon#flushed, iclass 40, count 2 2006.253.08:15:49.09#ibcon#about to write, iclass 40, count 2 2006.253.08:15:49.09#ibcon#wrote, iclass 40, count 2 2006.253.08:15:49.09#ibcon#about to read 3, iclass 40, count 2 2006.253.08:15:49.11#ibcon#read 3, iclass 40, count 2 2006.253.08:15:49.11#ibcon#about to read 4, iclass 40, count 2 2006.253.08:15:49.11#ibcon#read 4, iclass 40, count 2 2006.253.08:15:49.11#ibcon#about to read 5, iclass 40, count 2 2006.253.08:15:49.11#ibcon#read 5, iclass 40, count 2 2006.253.08:15:49.11#ibcon#about to read 6, iclass 40, count 2 2006.253.08:15:49.11#ibcon#read 6, iclass 40, count 2 2006.253.08:15:49.11#ibcon#end of sib2, iclass 40, count 2 2006.253.08:15:49.11#ibcon#*mode == 0, iclass 40, count 2 2006.253.08:15:49.11#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.253.08:15:49.11#ibcon#[25=AT04-07\r\n] 2006.253.08:15:49.11#ibcon#*before write, iclass 40, count 2 2006.253.08:15:49.11#ibcon#enter sib2, iclass 40, count 2 2006.253.08:15:49.11#ibcon#flushed, iclass 40, count 2 2006.253.08:15:49.11#ibcon#about to write, iclass 40, count 2 2006.253.08:15:49.11#ibcon#wrote, iclass 40, count 2 2006.253.08:15:49.11#ibcon#about to read 3, iclass 40, count 2 2006.253.08:15:49.14#ibcon#read 3, iclass 40, count 2 2006.253.08:15:49.14#ibcon#about to read 4, iclass 40, count 2 2006.253.08:15:49.14#ibcon#read 4, iclass 40, count 2 2006.253.08:15:49.14#ibcon#about to read 5, iclass 40, count 2 2006.253.08:15:49.14#ibcon#read 5, iclass 40, count 2 2006.253.08:15:49.14#ibcon#about to read 6, iclass 40, count 2 2006.253.08:15:49.14#ibcon#read 6, iclass 40, count 2 2006.253.08:15:49.14#ibcon#end of sib2, iclass 40, count 2 2006.253.08:15:49.14#ibcon#*after write, iclass 40, count 2 2006.253.08:15:49.14#ibcon#*before return 0, iclass 40, count 2 2006.253.08:15:49.14#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.253.08:15:49.14#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.253.08:15:49.14#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.253.08:15:49.14#ibcon#ireg 7 cls_cnt 0 2006.253.08:15:49.14#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.253.08:15:49.26#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.253.08:15:49.26#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.253.08:15:49.26#ibcon#enter wrdev, iclass 40, count 0 2006.253.08:15:49.26#ibcon#first serial, iclass 40, count 0 2006.253.08:15:49.26#ibcon#enter sib2, iclass 40, count 0 2006.253.08:15:49.26#ibcon#flushed, iclass 40, count 0 2006.253.08:15:49.26#ibcon#about to write, iclass 40, count 0 2006.253.08:15:49.26#ibcon#wrote, iclass 40, count 0 2006.253.08:15:49.26#ibcon#about to read 3, iclass 40, count 0 2006.253.08:15:49.28#ibcon#read 3, iclass 40, count 0 2006.253.08:15:49.28#ibcon#about to read 4, iclass 40, count 0 2006.253.08:15:49.28#ibcon#read 4, iclass 40, count 0 2006.253.08:15:49.28#ibcon#about to read 5, iclass 40, count 0 2006.253.08:15:49.28#ibcon#read 5, iclass 40, count 0 2006.253.08:15:49.28#ibcon#about to read 6, iclass 40, count 0 2006.253.08:15:49.28#ibcon#read 6, iclass 40, count 0 2006.253.08:15:49.28#ibcon#end of sib2, iclass 40, count 0 2006.253.08:15:49.28#ibcon#*mode == 0, iclass 40, count 0 2006.253.08:15:49.28#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.253.08:15:49.28#ibcon#[25=USB\r\n] 2006.253.08:15:49.28#ibcon#*before write, iclass 40, count 0 2006.253.08:15:49.28#ibcon#enter sib2, iclass 40, count 0 2006.253.08:15:49.28#ibcon#flushed, iclass 40, count 0 2006.253.08:15:49.28#ibcon#about to write, iclass 40, count 0 2006.253.08:15:49.28#ibcon#wrote, iclass 40, count 0 2006.253.08:15:49.28#ibcon#about to read 3, iclass 40, count 0 2006.253.08:15:49.31#ibcon#read 3, iclass 40, count 0 2006.253.08:15:49.31#ibcon#about to read 4, iclass 40, count 0 2006.253.08:15:49.31#ibcon#read 4, iclass 40, count 0 2006.253.08:15:49.31#ibcon#about to read 5, iclass 40, count 0 2006.253.08:15:49.31#ibcon#read 5, iclass 40, count 0 2006.253.08:15:49.31#ibcon#about to read 6, iclass 40, count 0 2006.253.08:15:49.31#ibcon#read 6, iclass 40, count 0 2006.253.08:15:49.31#ibcon#end of sib2, iclass 40, count 0 2006.253.08:15:49.31#ibcon#*after write, iclass 40, count 0 2006.253.08:15:49.31#ibcon#*before return 0, iclass 40, count 0 2006.253.08:15:49.31#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.253.08:15:49.31#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.253.08:15:49.31#ibcon#about to clear, iclass 40 cls_cnt 0 2006.253.08:15:49.31#ibcon#cleared, iclass 40 cls_cnt 0 2006.253.08:15:49.31$vc4f8/valo=5,652.99 2006.253.08:15:49.31#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.253.08:15:49.31#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.253.08:15:49.31#ibcon#ireg 17 cls_cnt 0 2006.253.08:15:49.31#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.253.08:15:49.31#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.253.08:15:49.31#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.253.08:15:49.31#ibcon#enter wrdev, iclass 4, count 0 2006.253.08:15:49.31#ibcon#first serial, iclass 4, count 0 2006.253.08:15:49.31#ibcon#enter sib2, iclass 4, count 0 2006.253.08:15:49.31#ibcon#flushed, iclass 4, count 0 2006.253.08:15:49.31#ibcon#about to write, iclass 4, count 0 2006.253.08:15:49.31#ibcon#wrote, iclass 4, count 0 2006.253.08:15:49.31#ibcon#about to read 3, iclass 4, count 0 2006.253.08:15:49.33#ibcon#read 3, iclass 4, count 0 2006.253.08:15:49.33#ibcon#about to read 4, iclass 4, count 0 2006.253.08:15:49.33#ibcon#read 4, iclass 4, count 0 2006.253.08:15:49.33#ibcon#about to read 5, iclass 4, count 0 2006.253.08:15:49.33#ibcon#read 5, iclass 4, count 0 2006.253.08:15:49.33#ibcon#about to read 6, iclass 4, count 0 2006.253.08:15:49.33#ibcon#read 6, iclass 4, count 0 2006.253.08:15:49.33#ibcon#end of sib2, iclass 4, count 0 2006.253.08:15:49.33#ibcon#*mode == 0, iclass 4, count 0 2006.253.08:15:49.33#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.253.08:15:49.33#ibcon#[26=FRQ=05,652.99\r\n] 2006.253.08:15:49.33#ibcon#*before write, iclass 4, count 0 2006.253.08:15:49.33#ibcon#enter sib2, iclass 4, count 0 2006.253.08:15:49.33#ibcon#flushed, iclass 4, count 0 2006.253.08:15:49.33#ibcon#about to write, iclass 4, count 0 2006.253.08:15:49.33#ibcon#wrote, iclass 4, count 0 2006.253.08:15:49.33#ibcon#about to read 3, iclass 4, count 0 2006.253.08:15:49.38#ibcon#read 3, iclass 4, count 0 2006.253.08:15:49.38#ibcon#about to read 4, iclass 4, count 0 2006.253.08:15:49.38#ibcon#read 4, iclass 4, count 0 2006.253.08:15:49.38#ibcon#about to read 5, iclass 4, count 0 2006.253.08:15:49.38#ibcon#read 5, iclass 4, count 0 2006.253.08:15:49.38#ibcon#about to read 6, iclass 4, count 0 2006.253.08:15:49.38#ibcon#read 6, iclass 4, count 0 2006.253.08:15:49.38#ibcon#end of sib2, iclass 4, count 0 2006.253.08:15:49.38#ibcon#*after write, iclass 4, count 0 2006.253.08:15:49.38#ibcon#*before return 0, iclass 4, count 0 2006.253.08:15:49.38#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.253.08:15:49.38#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.253.08:15:49.38#ibcon#about to clear, iclass 4 cls_cnt 0 2006.253.08:15:49.38#ibcon#cleared, iclass 4 cls_cnt 0 2006.253.08:15:49.38$vc4f8/va=5,7 2006.253.08:15:49.38#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.253.08:15:49.38#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.253.08:15:49.38#ibcon#ireg 11 cls_cnt 2 2006.253.08:15:49.38#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.253.08:15:49.43#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.253.08:15:49.43#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.253.08:15:49.43#ibcon#enter wrdev, iclass 6, count 2 2006.253.08:15:49.43#ibcon#first serial, iclass 6, count 2 2006.253.08:15:49.43#ibcon#enter sib2, iclass 6, count 2 2006.253.08:15:49.43#ibcon#flushed, iclass 6, count 2 2006.253.08:15:49.43#ibcon#about to write, iclass 6, count 2 2006.253.08:15:49.43#ibcon#wrote, iclass 6, count 2 2006.253.08:15:49.43#ibcon#about to read 3, iclass 6, count 2 2006.253.08:15:49.45#ibcon#read 3, iclass 6, count 2 2006.253.08:15:49.45#ibcon#about to read 4, iclass 6, count 2 2006.253.08:15:49.45#ibcon#read 4, iclass 6, count 2 2006.253.08:15:49.45#ibcon#about to read 5, iclass 6, count 2 2006.253.08:15:49.45#ibcon#read 5, iclass 6, count 2 2006.253.08:15:49.45#ibcon#about to read 6, iclass 6, count 2 2006.253.08:15:49.45#ibcon#read 6, iclass 6, count 2 2006.253.08:15:49.45#ibcon#end of sib2, iclass 6, count 2 2006.253.08:15:49.45#ibcon#*mode == 0, iclass 6, count 2 2006.253.08:15:49.45#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.253.08:15:49.45#ibcon#[25=AT05-07\r\n] 2006.253.08:15:49.45#ibcon#*before write, iclass 6, count 2 2006.253.08:15:49.45#ibcon#enter sib2, iclass 6, count 2 2006.253.08:15:49.45#ibcon#flushed, iclass 6, count 2 2006.253.08:15:49.45#ibcon#about to write, iclass 6, count 2 2006.253.08:15:49.45#ibcon#wrote, iclass 6, count 2 2006.253.08:15:49.45#ibcon#about to read 3, iclass 6, count 2 2006.253.08:15:49.48#ibcon#read 3, iclass 6, count 2 2006.253.08:15:49.48#ibcon#about to read 4, iclass 6, count 2 2006.253.08:15:49.48#ibcon#read 4, iclass 6, count 2 2006.253.08:15:49.48#ibcon#about to read 5, iclass 6, count 2 2006.253.08:15:49.48#ibcon#read 5, iclass 6, count 2 2006.253.08:15:49.48#ibcon#about to read 6, iclass 6, count 2 2006.253.08:15:49.48#ibcon#read 6, iclass 6, count 2 2006.253.08:15:49.48#ibcon#end of sib2, iclass 6, count 2 2006.253.08:15:49.48#ibcon#*after write, iclass 6, count 2 2006.253.08:15:49.48#ibcon#*before return 0, iclass 6, count 2 2006.253.08:15:49.48#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.253.08:15:49.48#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.253.08:15:49.48#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.253.08:15:49.48#ibcon#ireg 7 cls_cnt 0 2006.253.08:15:49.48#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.253.08:15:49.60#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.253.08:15:49.60#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.253.08:15:49.60#ibcon#enter wrdev, iclass 6, count 0 2006.253.08:15:49.60#ibcon#first serial, iclass 6, count 0 2006.253.08:15:49.60#ibcon#enter sib2, iclass 6, count 0 2006.253.08:15:49.60#ibcon#flushed, iclass 6, count 0 2006.253.08:15:49.60#ibcon#about to write, iclass 6, count 0 2006.253.08:15:49.60#ibcon#wrote, iclass 6, count 0 2006.253.08:15:49.60#ibcon#about to read 3, iclass 6, count 0 2006.253.08:15:49.62#ibcon#read 3, iclass 6, count 0 2006.253.08:15:49.62#ibcon#about to read 4, iclass 6, count 0 2006.253.08:15:49.62#ibcon#read 4, iclass 6, count 0 2006.253.08:15:49.62#ibcon#about to read 5, iclass 6, count 0 2006.253.08:15:49.62#ibcon#read 5, iclass 6, count 0 2006.253.08:15:49.62#ibcon#about to read 6, iclass 6, count 0 2006.253.08:15:49.62#ibcon#read 6, iclass 6, count 0 2006.253.08:15:49.62#ibcon#end of sib2, iclass 6, count 0 2006.253.08:15:49.62#ibcon#*mode == 0, iclass 6, count 0 2006.253.08:15:49.62#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.253.08:15:49.62#ibcon#[25=USB\r\n] 2006.253.08:15:49.62#ibcon#*before write, iclass 6, count 0 2006.253.08:15:49.62#ibcon#enter sib2, iclass 6, count 0 2006.253.08:15:49.62#ibcon#flushed, iclass 6, count 0 2006.253.08:15:49.62#ibcon#about to write, iclass 6, count 0 2006.253.08:15:49.62#ibcon#wrote, iclass 6, count 0 2006.253.08:15:49.62#ibcon#about to read 3, iclass 6, count 0 2006.253.08:15:49.65#ibcon#read 3, iclass 6, count 0 2006.253.08:15:49.65#ibcon#about to read 4, iclass 6, count 0 2006.253.08:15:49.65#ibcon#read 4, iclass 6, count 0 2006.253.08:15:49.65#ibcon#about to read 5, iclass 6, count 0 2006.253.08:15:49.65#ibcon#read 5, iclass 6, count 0 2006.253.08:15:49.65#ibcon#about to read 6, iclass 6, count 0 2006.253.08:15:49.65#ibcon#read 6, iclass 6, count 0 2006.253.08:15:49.65#ibcon#end of sib2, iclass 6, count 0 2006.253.08:15:49.65#ibcon#*after write, iclass 6, count 0 2006.253.08:15:49.65#ibcon#*before return 0, iclass 6, count 0 2006.253.08:15:49.65#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.253.08:15:49.65#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.253.08:15:49.65#ibcon#about to clear, iclass 6 cls_cnt 0 2006.253.08:15:49.65#ibcon#cleared, iclass 6 cls_cnt 0 2006.253.08:15:49.65$vc4f8/valo=6,772.99 2006.253.08:15:49.65#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.253.08:15:49.65#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.253.08:15:49.65#ibcon#ireg 17 cls_cnt 0 2006.253.08:15:49.65#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.253.08:15:49.65#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.253.08:15:49.65#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.253.08:15:49.65#ibcon#enter wrdev, iclass 10, count 0 2006.253.08:15:49.65#ibcon#first serial, iclass 10, count 0 2006.253.08:15:49.65#ibcon#enter sib2, iclass 10, count 0 2006.253.08:15:49.65#ibcon#flushed, iclass 10, count 0 2006.253.08:15:49.65#ibcon#about to write, iclass 10, count 0 2006.253.08:15:49.65#ibcon#wrote, iclass 10, count 0 2006.253.08:15:49.65#ibcon#about to read 3, iclass 10, count 0 2006.253.08:15:49.67#ibcon#read 3, iclass 10, count 0 2006.253.08:15:49.67#ibcon#about to read 4, iclass 10, count 0 2006.253.08:15:49.67#ibcon#read 4, iclass 10, count 0 2006.253.08:15:49.67#ibcon#about to read 5, iclass 10, count 0 2006.253.08:15:49.67#ibcon#read 5, iclass 10, count 0 2006.253.08:15:49.67#ibcon#about to read 6, iclass 10, count 0 2006.253.08:15:49.67#ibcon#read 6, iclass 10, count 0 2006.253.08:15:49.67#ibcon#end of sib2, iclass 10, count 0 2006.253.08:15:49.67#ibcon#*mode == 0, iclass 10, count 0 2006.253.08:15:49.67#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.253.08:15:49.67#ibcon#[26=FRQ=06,772.99\r\n] 2006.253.08:15:49.67#ibcon#*before write, iclass 10, count 0 2006.253.08:15:49.67#ibcon#enter sib2, iclass 10, count 0 2006.253.08:15:49.67#ibcon#flushed, iclass 10, count 0 2006.253.08:15:49.67#ibcon#about to write, iclass 10, count 0 2006.253.08:15:49.67#ibcon#wrote, iclass 10, count 0 2006.253.08:15:49.67#ibcon#about to read 3, iclass 10, count 0 2006.253.08:15:49.72#ibcon#read 3, iclass 10, count 0 2006.253.08:15:49.72#ibcon#about to read 4, iclass 10, count 0 2006.253.08:15:49.72#ibcon#read 4, iclass 10, count 0 2006.253.08:15:49.72#ibcon#about to read 5, iclass 10, count 0 2006.253.08:15:49.72#ibcon#read 5, iclass 10, count 0 2006.253.08:15:49.72#ibcon#about to read 6, iclass 10, count 0 2006.253.08:15:49.72#ibcon#read 6, iclass 10, count 0 2006.253.08:15:49.72#ibcon#end of sib2, iclass 10, count 0 2006.253.08:15:49.72#ibcon#*after write, iclass 10, count 0 2006.253.08:15:49.72#ibcon#*before return 0, iclass 10, count 0 2006.253.08:15:49.72#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.253.08:15:49.72#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.253.08:15:49.72#ibcon#about to clear, iclass 10 cls_cnt 0 2006.253.08:15:49.72#ibcon#cleared, iclass 10 cls_cnt 0 2006.253.08:15:49.72$vc4f8/va=6,7 2006.253.08:15:49.72#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.253.08:15:49.72#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.253.08:15:49.72#ibcon#ireg 11 cls_cnt 2 2006.253.08:15:49.72#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.253.08:15:49.77#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.253.08:15:49.77#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.253.08:15:49.77#ibcon#enter wrdev, iclass 12, count 2 2006.253.08:15:49.77#ibcon#first serial, iclass 12, count 2 2006.253.08:15:49.77#ibcon#enter sib2, iclass 12, count 2 2006.253.08:15:49.77#ibcon#flushed, iclass 12, count 2 2006.253.08:15:49.77#ibcon#about to write, iclass 12, count 2 2006.253.08:15:49.77#ibcon#wrote, iclass 12, count 2 2006.253.08:15:49.77#ibcon#about to read 3, iclass 12, count 2 2006.253.08:15:49.79#ibcon#read 3, iclass 12, count 2 2006.253.08:15:49.79#ibcon#about to read 4, iclass 12, count 2 2006.253.08:15:49.79#ibcon#read 4, iclass 12, count 2 2006.253.08:15:49.79#ibcon#about to read 5, iclass 12, count 2 2006.253.08:15:49.79#ibcon#read 5, iclass 12, count 2 2006.253.08:15:49.79#ibcon#about to read 6, iclass 12, count 2 2006.253.08:15:49.79#ibcon#read 6, iclass 12, count 2 2006.253.08:15:49.79#ibcon#end of sib2, iclass 12, count 2 2006.253.08:15:49.79#ibcon#*mode == 0, iclass 12, count 2 2006.253.08:15:49.79#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.253.08:15:49.79#ibcon#[25=AT06-07\r\n] 2006.253.08:15:49.79#ibcon#*before write, iclass 12, count 2 2006.253.08:15:49.79#ibcon#enter sib2, iclass 12, count 2 2006.253.08:15:49.79#ibcon#flushed, iclass 12, count 2 2006.253.08:15:49.79#ibcon#about to write, iclass 12, count 2 2006.253.08:15:49.79#ibcon#wrote, iclass 12, count 2 2006.253.08:15:49.79#ibcon#about to read 3, iclass 12, count 2 2006.253.08:15:49.82#ibcon#read 3, iclass 12, count 2 2006.253.08:15:49.82#ibcon#about to read 4, iclass 12, count 2 2006.253.08:15:49.82#ibcon#read 4, iclass 12, count 2 2006.253.08:15:49.82#ibcon#about to read 5, iclass 12, count 2 2006.253.08:15:49.82#ibcon#read 5, iclass 12, count 2 2006.253.08:15:49.82#ibcon#about to read 6, iclass 12, count 2 2006.253.08:15:49.82#ibcon#read 6, iclass 12, count 2 2006.253.08:15:49.82#ibcon#end of sib2, iclass 12, count 2 2006.253.08:15:49.82#ibcon#*after write, iclass 12, count 2 2006.253.08:15:49.82#ibcon#*before return 0, iclass 12, count 2 2006.253.08:15:49.82#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.253.08:15:49.82#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.253.08:15:49.82#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.253.08:15:49.82#ibcon#ireg 7 cls_cnt 0 2006.253.08:15:49.82#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.253.08:15:49.94#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.253.08:15:49.94#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.253.08:15:49.94#ibcon#enter wrdev, iclass 12, count 0 2006.253.08:15:49.94#ibcon#first serial, iclass 12, count 0 2006.253.08:15:49.94#ibcon#enter sib2, iclass 12, count 0 2006.253.08:15:49.94#ibcon#flushed, iclass 12, count 0 2006.253.08:15:49.94#ibcon#about to write, iclass 12, count 0 2006.253.08:15:49.94#ibcon#wrote, iclass 12, count 0 2006.253.08:15:49.94#ibcon#about to read 3, iclass 12, count 0 2006.253.08:15:49.96#ibcon#read 3, iclass 12, count 0 2006.253.08:15:49.96#ibcon#about to read 4, iclass 12, count 0 2006.253.08:15:49.96#ibcon#read 4, iclass 12, count 0 2006.253.08:15:49.96#ibcon#about to read 5, iclass 12, count 0 2006.253.08:15:49.96#ibcon#read 5, iclass 12, count 0 2006.253.08:15:49.96#ibcon#about to read 6, iclass 12, count 0 2006.253.08:15:49.96#ibcon#read 6, iclass 12, count 0 2006.253.08:15:49.96#ibcon#end of sib2, iclass 12, count 0 2006.253.08:15:49.96#ibcon#*mode == 0, iclass 12, count 0 2006.253.08:15:49.96#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.253.08:15:49.96#ibcon#[25=USB\r\n] 2006.253.08:15:49.96#ibcon#*before write, iclass 12, count 0 2006.253.08:15:49.96#ibcon#enter sib2, iclass 12, count 0 2006.253.08:15:49.96#ibcon#flushed, iclass 12, count 0 2006.253.08:15:49.96#ibcon#about to write, iclass 12, count 0 2006.253.08:15:49.96#ibcon#wrote, iclass 12, count 0 2006.253.08:15:49.96#ibcon#about to read 3, iclass 12, count 0 2006.253.08:15:49.99#ibcon#read 3, iclass 12, count 0 2006.253.08:15:49.99#ibcon#about to read 4, iclass 12, count 0 2006.253.08:15:49.99#ibcon#read 4, iclass 12, count 0 2006.253.08:15:49.99#ibcon#about to read 5, iclass 12, count 0 2006.253.08:15:49.99#ibcon#read 5, iclass 12, count 0 2006.253.08:15:49.99#ibcon#about to read 6, iclass 12, count 0 2006.253.08:15:49.99#ibcon#read 6, iclass 12, count 0 2006.253.08:15:49.99#ibcon#end of sib2, iclass 12, count 0 2006.253.08:15:49.99#ibcon#*after write, iclass 12, count 0 2006.253.08:15:49.99#ibcon#*before return 0, iclass 12, count 0 2006.253.08:15:49.99#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.253.08:15:49.99#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.253.08:15:49.99#ibcon#about to clear, iclass 12 cls_cnt 0 2006.253.08:15:49.99#ibcon#cleared, iclass 12 cls_cnt 0 2006.253.08:15:49.99$vc4f8/valo=7,832.99 2006.253.08:15:49.99#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.253.08:15:49.99#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.253.08:15:49.99#ibcon#ireg 17 cls_cnt 0 2006.253.08:15:49.99#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.253.08:15:49.99#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.253.08:15:49.99#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.253.08:15:49.99#ibcon#enter wrdev, iclass 14, count 0 2006.253.08:15:49.99#ibcon#first serial, iclass 14, count 0 2006.253.08:15:49.99#ibcon#enter sib2, iclass 14, count 0 2006.253.08:15:49.99#ibcon#flushed, iclass 14, count 0 2006.253.08:15:49.99#ibcon#about to write, iclass 14, count 0 2006.253.08:15:49.99#ibcon#wrote, iclass 14, count 0 2006.253.08:15:49.99#ibcon#about to read 3, iclass 14, count 0 2006.253.08:15:50.01#ibcon#read 3, iclass 14, count 0 2006.253.08:15:50.01#ibcon#about to read 4, iclass 14, count 0 2006.253.08:15:50.01#ibcon#read 4, iclass 14, count 0 2006.253.08:15:50.01#ibcon#about to read 5, iclass 14, count 0 2006.253.08:15:50.01#ibcon#read 5, iclass 14, count 0 2006.253.08:15:50.01#ibcon#about to read 6, iclass 14, count 0 2006.253.08:15:50.01#ibcon#read 6, iclass 14, count 0 2006.253.08:15:50.01#ibcon#end of sib2, iclass 14, count 0 2006.253.08:15:50.01#ibcon#*mode == 0, iclass 14, count 0 2006.253.08:15:50.01#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.253.08:15:50.01#ibcon#[26=FRQ=07,832.99\r\n] 2006.253.08:15:50.01#ibcon#*before write, iclass 14, count 0 2006.253.08:15:50.01#ibcon#enter sib2, iclass 14, count 0 2006.253.08:15:50.01#ibcon#flushed, iclass 14, count 0 2006.253.08:15:50.01#ibcon#about to write, iclass 14, count 0 2006.253.08:15:50.01#ibcon#wrote, iclass 14, count 0 2006.253.08:15:50.01#ibcon#about to read 3, iclass 14, count 0 2006.253.08:15:50.06#ibcon#read 3, iclass 14, count 0 2006.253.08:15:50.06#ibcon#about to read 4, iclass 14, count 0 2006.253.08:15:50.06#ibcon#read 4, iclass 14, count 0 2006.253.08:15:50.06#ibcon#about to read 5, iclass 14, count 0 2006.253.08:15:50.06#ibcon#read 5, iclass 14, count 0 2006.253.08:15:50.06#ibcon#about to read 6, iclass 14, count 0 2006.253.08:15:50.06#ibcon#read 6, iclass 14, count 0 2006.253.08:15:50.06#ibcon#end of sib2, iclass 14, count 0 2006.253.08:15:50.06#ibcon#*after write, iclass 14, count 0 2006.253.08:15:50.06#ibcon#*before return 0, iclass 14, count 0 2006.253.08:15:50.06#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.253.08:15:50.06#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.253.08:15:50.06#ibcon#about to clear, iclass 14 cls_cnt 0 2006.253.08:15:50.06#ibcon#cleared, iclass 14 cls_cnt 0 2006.253.08:15:50.06$vc4f8/va=7,7 2006.253.08:15:50.06#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.253.08:15:50.06#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.253.08:15:50.06#ibcon#ireg 11 cls_cnt 2 2006.253.08:15:50.06#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.253.08:15:50.11#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.253.08:15:50.11#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.253.08:15:50.11#ibcon#enter wrdev, iclass 16, count 2 2006.253.08:15:50.11#ibcon#first serial, iclass 16, count 2 2006.253.08:15:50.11#ibcon#enter sib2, iclass 16, count 2 2006.253.08:15:50.11#ibcon#flushed, iclass 16, count 2 2006.253.08:15:50.11#ibcon#about to write, iclass 16, count 2 2006.253.08:15:50.11#ibcon#wrote, iclass 16, count 2 2006.253.08:15:50.11#ibcon#about to read 3, iclass 16, count 2 2006.253.08:15:50.13#ibcon#read 3, iclass 16, count 2 2006.253.08:15:50.13#ibcon#about to read 4, iclass 16, count 2 2006.253.08:15:50.13#ibcon#read 4, iclass 16, count 2 2006.253.08:15:50.13#ibcon#about to read 5, iclass 16, count 2 2006.253.08:15:50.13#ibcon#read 5, iclass 16, count 2 2006.253.08:15:50.13#ibcon#about to read 6, iclass 16, count 2 2006.253.08:15:50.13#ibcon#read 6, iclass 16, count 2 2006.253.08:15:50.13#ibcon#end of sib2, iclass 16, count 2 2006.253.08:15:50.13#ibcon#*mode == 0, iclass 16, count 2 2006.253.08:15:50.13#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.253.08:15:50.13#ibcon#[25=AT07-07\r\n] 2006.253.08:15:50.13#ibcon#*before write, iclass 16, count 2 2006.253.08:15:50.13#ibcon#enter sib2, iclass 16, count 2 2006.253.08:15:50.13#ibcon#flushed, iclass 16, count 2 2006.253.08:15:50.13#ibcon#about to write, iclass 16, count 2 2006.253.08:15:50.13#ibcon#wrote, iclass 16, count 2 2006.253.08:15:50.13#ibcon#about to read 3, iclass 16, count 2 2006.253.08:15:50.16#ibcon#read 3, iclass 16, count 2 2006.253.08:15:50.16#ibcon#about to read 4, iclass 16, count 2 2006.253.08:15:50.16#ibcon#read 4, iclass 16, count 2 2006.253.08:15:50.16#ibcon#about to read 5, iclass 16, count 2 2006.253.08:15:50.16#ibcon#read 5, iclass 16, count 2 2006.253.08:15:50.16#ibcon#about to read 6, iclass 16, count 2 2006.253.08:15:50.16#ibcon#read 6, iclass 16, count 2 2006.253.08:15:50.16#ibcon#end of sib2, iclass 16, count 2 2006.253.08:15:50.16#ibcon#*after write, iclass 16, count 2 2006.253.08:15:50.16#ibcon#*before return 0, iclass 16, count 2 2006.253.08:15:50.16#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.253.08:15:50.16#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.253.08:15:50.16#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.253.08:15:50.16#ibcon#ireg 7 cls_cnt 0 2006.253.08:15:50.16#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.253.08:15:50.28#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.253.08:15:50.28#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.253.08:15:50.28#ibcon#enter wrdev, iclass 16, count 0 2006.253.08:15:50.28#ibcon#first serial, iclass 16, count 0 2006.253.08:15:50.28#ibcon#enter sib2, iclass 16, count 0 2006.253.08:15:50.28#ibcon#flushed, iclass 16, count 0 2006.253.08:15:50.28#ibcon#about to write, iclass 16, count 0 2006.253.08:15:50.28#ibcon#wrote, iclass 16, count 0 2006.253.08:15:50.28#ibcon#about to read 3, iclass 16, count 0 2006.253.08:15:50.30#ibcon#read 3, iclass 16, count 0 2006.253.08:15:50.30#ibcon#about to read 4, iclass 16, count 0 2006.253.08:15:50.30#ibcon#read 4, iclass 16, count 0 2006.253.08:15:50.30#ibcon#about to read 5, iclass 16, count 0 2006.253.08:15:50.30#ibcon#read 5, iclass 16, count 0 2006.253.08:15:50.30#ibcon#about to read 6, iclass 16, count 0 2006.253.08:15:50.30#ibcon#read 6, iclass 16, count 0 2006.253.08:15:50.30#ibcon#end of sib2, iclass 16, count 0 2006.253.08:15:50.30#ibcon#*mode == 0, iclass 16, count 0 2006.253.08:15:50.30#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.253.08:15:50.30#ibcon#[25=USB\r\n] 2006.253.08:15:50.30#ibcon#*before write, iclass 16, count 0 2006.253.08:15:50.30#ibcon#enter sib2, iclass 16, count 0 2006.253.08:15:50.30#ibcon#flushed, iclass 16, count 0 2006.253.08:15:50.30#ibcon#about to write, iclass 16, count 0 2006.253.08:15:50.30#ibcon#wrote, iclass 16, count 0 2006.253.08:15:50.30#ibcon#about to read 3, iclass 16, count 0 2006.253.08:15:50.33#ibcon#read 3, iclass 16, count 0 2006.253.08:15:50.33#ibcon#about to read 4, iclass 16, count 0 2006.253.08:15:50.33#ibcon#read 4, iclass 16, count 0 2006.253.08:15:50.33#ibcon#about to read 5, iclass 16, count 0 2006.253.08:15:50.33#ibcon#read 5, iclass 16, count 0 2006.253.08:15:50.33#ibcon#about to read 6, iclass 16, count 0 2006.253.08:15:50.33#ibcon#read 6, iclass 16, count 0 2006.253.08:15:50.33#ibcon#end of sib2, iclass 16, count 0 2006.253.08:15:50.33#ibcon#*after write, iclass 16, count 0 2006.253.08:15:50.33#ibcon#*before return 0, iclass 16, count 0 2006.253.08:15:50.33#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.253.08:15:50.33#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.253.08:15:50.33#ibcon#about to clear, iclass 16 cls_cnt 0 2006.253.08:15:50.33#ibcon#cleared, iclass 16 cls_cnt 0 2006.253.08:15:50.33$vc4f8/valo=8,852.99 2006.253.08:15:50.33#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.253.08:15:50.33#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.253.08:15:50.33#ibcon#ireg 17 cls_cnt 0 2006.253.08:15:50.33#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.253.08:15:50.33#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.253.08:15:50.33#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.253.08:15:50.33#ibcon#enter wrdev, iclass 18, count 0 2006.253.08:15:50.33#ibcon#first serial, iclass 18, count 0 2006.253.08:15:50.33#ibcon#enter sib2, iclass 18, count 0 2006.253.08:15:50.33#ibcon#flushed, iclass 18, count 0 2006.253.08:15:50.33#ibcon#about to write, iclass 18, count 0 2006.253.08:15:50.33#ibcon#wrote, iclass 18, count 0 2006.253.08:15:50.33#ibcon#about to read 3, iclass 18, count 0 2006.253.08:15:50.35#ibcon#read 3, iclass 18, count 0 2006.253.08:15:50.35#ibcon#about to read 4, iclass 18, count 0 2006.253.08:15:50.35#ibcon#read 4, iclass 18, count 0 2006.253.08:15:50.35#ibcon#about to read 5, iclass 18, count 0 2006.253.08:15:50.35#ibcon#read 5, iclass 18, count 0 2006.253.08:15:50.35#ibcon#about to read 6, iclass 18, count 0 2006.253.08:15:50.35#ibcon#read 6, iclass 18, count 0 2006.253.08:15:50.35#ibcon#end of sib2, iclass 18, count 0 2006.253.08:15:50.35#ibcon#*mode == 0, iclass 18, count 0 2006.253.08:15:50.35#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.253.08:15:50.35#ibcon#[26=FRQ=08,852.99\r\n] 2006.253.08:15:50.35#ibcon#*before write, iclass 18, count 0 2006.253.08:15:50.35#ibcon#enter sib2, iclass 18, count 0 2006.253.08:15:50.35#ibcon#flushed, iclass 18, count 0 2006.253.08:15:50.35#ibcon#about to write, iclass 18, count 0 2006.253.08:15:50.35#ibcon#wrote, iclass 18, count 0 2006.253.08:15:50.35#ibcon#about to read 3, iclass 18, count 0 2006.253.08:15:50.40#ibcon#read 3, iclass 18, count 0 2006.253.08:15:50.40#ibcon#about to read 4, iclass 18, count 0 2006.253.08:15:50.40#ibcon#read 4, iclass 18, count 0 2006.253.08:15:50.40#ibcon#about to read 5, iclass 18, count 0 2006.253.08:15:50.40#ibcon#read 5, iclass 18, count 0 2006.253.08:15:50.40#ibcon#about to read 6, iclass 18, count 0 2006.253.08:15:50.40#ibcon#read 6, iclass 18, count 0 2006.253.08:15:50.40#ibcon#end of sib2, iclass 18, count 0 2006.253.08:15:50.40#ibcon#*after write, iclass 18, count 0 2006.253.08:15:50.40#ibcon#*before return 0, iclass 18, count 0 2006.253.08:15:50.40#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.253.08:15:50.40#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.253.08:15:50.40#ibcon#about to clear, iclass 18 cls_cnt 0 2006.253.08:15:50.40#ibcon#cleared, iclass 18 cls_cnt 0 2006.253.08:15:50.40$vc4f8/va=8,7 2006.253.08:15:50.40#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.253.08:15:50.40#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.253.08:15:50.40#ibcon#ireg 11 cls_cnt 2 2006.253.08:15:50.40#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.253.08:15:50.45#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.253.08:15:50.45#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.253.08:15:50.45#ibcon#enter wrdev, iclass 20, count 2 2006.253.08:15:50.45#ibcon#first serial, iclass 20, count 2 2006.253.08:15:50.45#ibcon#enter sib2, iclass 20, count 2 2006.253.08:15:50.45#ibcon#flushed, iclass 20, count 2 2006.253.08:15:50.45#ibcon#about to write, iclass 20, count 2 2006.253.08:15:50.45#ibcon#wrote, iclass 20, count 2 2006.253.08:15:50.45#ibcon#about to read 3, iclass 20, count 2 2006.253.08:15:50.47#ibcon#read 3, iclass 20, count 2 2006.253.08:15:50.47#ibcon#about to read 4, iclass 20, count 2 2006.253.08:15:50.47#ibcon#read 4, iclass 20, count 2 2006.253.08:15:50.47#ibcon#about to read 5, iclass 20, count 2 2006.253.08:15:50.47#ibcon#read 5, iclass 20, count 2 2006.253.08:15:50.47#ibcon#about to read 6, iclass 20, count 2 2006.253.08:15:50.47#ibcon#read 6, iclass 20, count 2 2006.253.08:15:50.47#ibcon#end of sib2, iclass 20, count 2 2006.253.08:15:50.47#ibcon#*mode == 0, iclass 20, count 2 2006.253.08:15:50.47#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.253.08:15:50.47#ibcon#[25=AT08-07\r\n] 2006.253.08:15:50.47#ibcon#*before write, iclass 20, count 2 2006.253.08:15:50.47#ibcon#enter sib2, iclass 20, count 2 2006.253.08:15:50.47#ibcon#flushed, iclass 20, count 2 2006.253.08:15:50.47#ibcon#about to write, iclass 20, count 2 2006.253.08:15:50.47#ibcon#wrote, iclass 20, count 2 2006.253.08:15:50.47#ibcon#about to read 3, iclass 20, count 2 2006.253.08:15:50.50#ibcon#read 3, iclass 20, count 2 2006.253.08:15:50.50#ibcon#about to read 4, iclass 20, count 2 2006.253.08:15:50.50#ibcon#read 4, iclass 20, count 2 2006.253.08:15:50.50#ibcon#about to read 5, iclass 20, count 2 2006.253.08:15:50.50#ibcon#read 5, iclass 20, count 2 2006.253.08:15:50.50#ibcon#about to read 6, iclass 20, count 2 2006.253.08:15:50.50#ibcon#read 6, iclass 20, count 2 2006.253.08:15:50.50#ibcon#end of sib2, iclass 20, count 2 2006.253.08:15:50.50#ibcon#*after write, iclass 20, count 2 2006.253.08:15:50.50#ibcon#*before return 0, iclass 20, count 2 2006.253.08:15:50.50#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.253.08:15:50.50#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.253.08:15:50.50#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.253.08:15:50.50#ibcon#ireg 7 cls_cnt 0 2006.253.08:15:50.50#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.253.08:15:50.62#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.253.08:15:50.62#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.253.08:15:50.62#ibcon#enter wrdev, iclass 20, count 0 2006.253.08:15:50.62#ibcon#first serial, iclass 20, count 0 2006.253.08:15:50.62#ibcon#enter sib2, iclass 20, count 0 2006.253.08:15:50.62#ibcon#flushed, iclass 20, count 0 2006.253.08:15:50.62#ibcon#about to write, iclass 20, count 0 2006.253.08:15:50.62#ibcon#wrote, iclass 20, count 0 2006.253.08:15:50.62#ibcon#about to read 3, iclass 20, count 0 2006.253.08:15:50.64#ibcon#read 3, iclass 20, count 0 2006.253.08:15:50.64#ibcon#about to read 4, iclass 20, count 0 2006.253.08:15:50.64#ibcon#read 4, iclass 20, count 0 2006.253.08:15:50.64#ibcon#about to read 5, iclass 20, count 0 2006.253.08:15:50.64#ibcon#read 5, iclass 20, count 0 2006.253.08:15:50.64#ibcon#about to read 6, iclass 20, count 0 2006.253.08:15:50.64#ibcon#read 6, iclass 20, count 0 2006.253.08:15:50.64#ibcon#end of sib2, iclass 20, count 0 2006.253.08:15:50.64#ibcon#*mode == 0, iclass 20, count 0 2006.253.08:15:50.64#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.253.08:15:50.64#ibcon#[25=USB\r\n] 2006.253.08:15:50.64#ibcon#*before write, iclass 20, count 0 2006.253.08:15:50.64#ibcon#enter sib2, iclass 20, count 0 2006.253.08:15:50.64#ibcon#flushed, iclass 20, count 0 2006.253.08:15:50.64#ibcon#about to write, iclass 20, count 0 2006.253.08:15:50.64#ibcon#wrote, iclass 20, count 0 2006.253.08:15:50.64#ibcon#about to read 3, iclass 20, count 0 2006.253.08:15:50.67#ibcon#read 3, iclass 20, count 0 2006.253.08:15:50.67#ibcon#about to read 4, iclass 20, count 0 2006.253.08:15:50.67#ibcon#read 4, iclass 20, count 0 2006.253.08:15:50.67#ibcon#about to read 5, iclass 20, count 0 2006.253.08:15:50.67#ibcon#read 5, iclass 20, count 0 2006.253.08:15:50.67#ibcon#about to read 6, iclass 20, count 0 2006.253.08:15:50.67#ibcon#read 6, iclass 20, count 0 2006.253.08:15:50.67#ibcon#end of sib2, iclass 20, count 0 2006.253.08:15:50.67#ibcon#*after write, iclass 20, count 0 2006.253.08:15:50.67#ibcon#*before return 0, iclass 20, count 0 2006.253.08:15:50.67#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.253.08:15:50.67#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.253.08:15:50.67#ibcon#about to clear, iclass 20 cls_cnt 0 2006.253.08:15:50.67#ibcon#cleared, iclass 20 cls_cnt 0 2006.253.08:15:50.67$vc4f8/vblo=1,632.99 2006.253.08:15:50.67#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.253.08:15:50.67#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.253.08:15:50.67#ibcon#ireg 17 cls_cnt 0 2006.253.08:15:50.67#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.253.08:15:50.67#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.253.08:15:50.67#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.253.08:15:50.67#ibcon#enter wrdev, iclass 22, count 0 2006.253.08:15:50.67#ibcon#first serial, iclass 22, count 0 2006.253.08:15:50.67#ibcon#enter sib2, iclass 22, count 0 2006.253.08:15:50.67#ibcon#flushed, iclass 22, count 0 2006.253.08:15:50.67#ibcon#about to write, iclass 22, count 0 2006.253.08:15:50.67#ibcon#wrote, iclass 22, count 0 2006.253.08:15:50.67#ibcon#about to read 3, iclass 22, count 0 2006.253.08:15:50.69#ibcon#read 3, iclass 22, count 0 2006.253.08:15:50.69#ibcon#about to read 4, iclass 22, count 0 2006.253.08:15:50.69#ibcon#read 4, iclass 22, count 0 2006.253.08:15:50.69#ibcon#about to read 5, iclass 22, count 0 2006.253.08:15:50.69#ibcon#read 5, iclass 22, count 0 2006.253.08:15:50.69#ibcon#about to read 6, iclass 22, count 0 2006.253.08:15:50.69#ibcon#read 6, iclass 22, count 0 2006.253.08:15:50.69#ibcon#end of sib2, iclass 22, count 0 2006.253.08:15:50.69#ibcon#*mode == 0, iclass 22, count 0 2006.253.08:15:50.69#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.253.08:15:50.69#ibcon#[28=FRQ=01,632.99\r\n] 2006.253.08:15:50.69#ibcon#*before write, iclass 22, count 0 2006.253.08:15:50.69#ibcon#enter sib2, iclass 22, count 0 2006.253.08:15:50.69#ibcon#flushed, iclass 22, count 0 2006.253.08:15:50.69#ibcon#about to write, iclass 22, count 0 2006.253.08:15:50.69#ibcon#wrote, iclass 22, count 0 2006.253.08:15:50.69#ibcon#about to read 3, iclass 22, count 0 2006.253.08:15:50.73#ibcon#read 3, iclass 22, count 0 2006.253.08:15:50.73#ibcon#about to read 4, iclass 22, count 0 2006.253.08:15:50.73#ibcon#read 4, iclass 22, count 0 2006.253.08:15:50.73#ibcon#about to read 5, iclass 22, count 0 2006.253.08:15:50.73#ibcon#read 5, iclass 22, count 0 2006.253.08:15:50.73#ibcon#about to read 6, iclass 22, count 0 2006.253.08:15:50.73#ibcon#read 6, iclass 22, count 0 2006.253.08:15:50.73#ibcon#end of sib2, iclass 22, count 0 2006.253.08:15:50.73#ibcon#*after write, iclass 22, count 0 2006.253.08:15:50.73#ibcon#*before return 0, iclass 22, count 0 2006.253.08:15:50.73#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.253.08:15:50.73#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.253.08:15:50.73#ibcon#about to clear, iclass 22 cls_cnt 0 2006.253.08:15:50.73#ibcon#cleared, iclass 22 cls_cnt 0 2006.253.08:15:50.73$vc4f8/vb=1,4 2006.253.08:15:50.73#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.253.08:15:50.73#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.253.08:15:50.73#ibcon#ireg 11 cls_cnt 2 2006.253.08:15:50.73#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.253.08:15:50.73#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.253.08:15:50.73#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.253.08:15:50.73#ibcon#enter wrdev, iclass 24, count 2 2006.253.08:15:50.73#ibcon#first serial, iclass 24, count 2 2006.253.08:15:50.73#ibcon#enter sib2, iclass 24, count 2 2006.253.08:15:50.73#ibcon#flushed, iclass 24, count 2 2006.253.08:15:50.73#ibcon#about to write, iclass 24, count 2 2006.253.08:15:50.73#ibcon#wrote, iclass 24, count 2 2006.253.08:15:50.73#ibcon#about to read 3, iclass 24, count 2 2006.253.08:15:50.75#ibcon#read 3, iclass 24, count 2 2006.253.08:15:50.75#ibcon#about to read 4, iclass 24, count 2 2006.253.08:15:50.75#ibcon#read 4, iclass 24, count 2 2006.253.08:15:50.75#ibcon#about to read 5, iclass 24, count 2 2006.253.08:15:50.75#ibcon#read 5, iclass 24, count 2 2006.253.08:15:50.75#ibcon#about to read 6, iclass 24, count 2 2006.253.08:15:50.75#ibcon#read 6, iclass 24, count 2 2006.253.08:15:50.75#ibcon#end of sib2, iclass 24, count 2 2006.253.08:15:50.75#ibcon#*mode == 0, iclass 24, count 2 2006.253.08:15:50.75#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.253.08:15:50.75#ibcon#[27=AT01-04\r\n] 2006.253.08:15:50.75#ibcon#*before write, iclass 24, count 2 2006.253.08:15:50.75#ibcon#enter sib2, iclass 24, count 2 2006.253.08:15:50.75#ibcon#flushed, iclass 24, count 2 2006.253.08:15:50.75#ibcon#about to write, iclass 24, count 2 2006.253.08:15:50.75#ibcon#wrote, iclass 24, count 2 2006.253.08:15:50.75#ibcon#about to read 3, iclass 24, count 2 2006.253.08:15:50.78#ibcon#read 3, iclass 24, count 2 2006.253.08:15:50.78#ibcon#about to read 4, iclass 24, count 2 2006.253.08:15:50.78#ibcon#read 4, iclass 24, count 2 2006.253.08:15:50.78#ibcon#about to read 5, iclass 24, count 2 2006.253.08:15:50.78#ibcon#read 5, iclass 24, count 2 2006.253.08:15:50.78#ibcon#about to read 6, iclass 24, count 2 2006.253.08:15:50.78#ibcon#read 6, iclass 24, count 2 2006.253.08:15:50.78#ibcon#end of sib2, iclass 24, count 2 2006.253.08:15:50.78#ibcon#*after write, iclass 24, count 2 2006.253.08:15:50.78#ibcon#*before return 0, iclass 24, count 2 2006.253.08:15:50.78#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.253.08:15:50.78#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.253.08:15:50.78#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.253.08:15:50.78#ibcon#ireg 7 cls_cnt 0 2006.253.08:15:50.78#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.253.08:15:50.90#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.253.08:15:50.90#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.253.08:15:50.90#ibcon#enter wrdev, iclass 24, count 0 2006.253.08:15:50.90#ibcon#first serial, iclass 24, count 0 2006.253.08:15:50.90#ibcon#enter sib2, iclass 24, count 0 2006.253.08:15:50.90#ibcon#flushed, iclass 24, count 0 2006.253.08:15:50.90#ibcon#about to write, iclass 24, count 0 2006.253.08:15:50.90#ibcon#wrote, iclass 24, count 0 2006.253.08:15:50.90#ibcon#about to read 3, iclass 24, count 0 2006.253.08:15:50.92#ibcon#read 3, iclass 24, count 0 2006.253.08:15:50.92#ibcon#about to read 4, iclass 24, count 0 2006.253.08:15:50.92#ibcon#read 4, iclass 24, count 0 2006.253.08:15:50.92#ibcon#about to read 5, iclass 24, count 0 2006.253.08:15:50.92#ibcon#read 5, iclass 24, count 0 2006.253.08:15:50.92#ibcon#about to read 6, iclass 24, count 0 2006.253.08:15:50.92#ibcon#read 6, iclass 24, count 0 2006.253.08:15:50.92#ibcon#end of sib2, iclass 24, count 0 2006.253.08:15:50.92#ibcon#*mode == 0, iclass 24, count 0 2006.253.08:15:50.92#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.253.08:15:50.92#ibcon#[27=USB\r\n] 2006.253.08:15:50.92#ibcon#*before write, iclass 24, count 0 2006.253.08:15:50.92#ibcon#enter sib2, iclass 24, count 0 2006.253.08:15:50.92#ibcon#flushed, iclass 24, count 0 2006.253.08:15:50.92#ibcon#about to write, iclass 24, count 0 2006.253.08:15:50.92#ibcon#wrote, iclass 24, count 0 2006.253.08:15:50.92#ibcon#about to read 3, iclass 24, count 0 2006.253.08:15:50.95#ibcon#read 3, iclass 24, count 0 2006.253.08:15:50.95#ibcon#about to read 4, iclass 24, count 0 2006.253.08:15:50.95#ibcon#read 4, iclass 24, count 0 2006.253.08:15:50.95#ibcon#about to read 5, iclass 24, count 0 2006.253.08:15:50.95#ibcon#read 5, iclass 24, count 0 2006.253.08:15:50.95#ibcon#about to read 6, iclass 24, count 0 2006.253.08:15:50.95#ibcon#read 6, iclass 24, count 0 2006.253.08:15:50.95#ibcon#end of sib2, iclass 24, count 0 2006.253.08:15:50.95#ibcon#*after write, iclass 24, count 0 2006.253.08:15:50.95#ibcon#*before return 0, iclass 24, count 0 2006.253.08:15:50.95#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.253.08:15:50.95#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.253.08:15:50.95#ibcon#about to clear, iclass 24 cls_cnt 0 2006.253.08:15:50.95#ibcon#cleared, iclass 24 cls_cnt 0 2006.253.08:15:50.95$vc4f8/vblo=2,640.99 2006.253.08:15:50.95#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.253.08:15:50.95#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.253.08:15:50.95#ibcon#ireg 17 cls_cnt 0 2006.253.08:15:50.95#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.253.08:15:50.95#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.253.08:15:50.95#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.253.08:15:50.95#ibcon#enter wrdev, iclass 26, count 0 2006.253.08:15:50.95#ibcon#first serial, iclass 26, count 0 2006.253.08:15:50.95#ibcon#enter sib2, iclass 26, count 0 2006.253.08:15:50.95#ibcon#flushed, iclass 26, count 0 2006.253.08:15:50.95#ibcon#about to write, iclass 26, count 0 2006.253.08:15:50.95#ibcon#wrote, iclass 26, count 0 2006.253.08:15:50.95#ibcon#about to read 3, iclass 26, count 0 2006.253.08:15:50.97#ibcon#read 3, iclass 26, count 0 2006.253.08:15:50.97#ibcon#about to read 4, iclass 26, count 0 2006.253.08:15:50.97#ibcon#read 4, iclass 26, count 0 2006.253.08:15:50.97#ibcon#about to read 5, iclass 26, count 0 2006.253.08:15:50.97#ibcon#read 5, iclass 26, count 0 2006.253.08:15:50.97#ibcon#about to read 6, iclass 26, count 0 2006.253.08:15:50.97#ibcon#read 6, iclass 26, count 0 2006.253.08:15:50.97#ibcon#end of sib2, iclass 26, count 0 2006.253.08:15:50.97#ibcon#*mode == 0, iclass 26, count 0 2006.253.08:15:50.97#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.253.08:15:50.97#ibcon#[28=FRQ=02,640.99\r\n] 2006.253.08:15:50.97#ibcon#*before write, iclass 26, count 0 2006.253.08:15:50.97#ibcon#enter sib2, iclass 26, count 0 2006.253.08:15:50.97#ibcon#flushed, iclass 26, count 0 2006.253.08:15:50.97#ibcon#about to write, iclass 26, count 0 2006.253.08:15:50.97#ibcon#wrote, iclass 26, count 0 2006.253.08:15:50.97#ibcon#about to read 3, iclass 26, count 0 2006.253.08:15:51.02#ibcon#read 3, iclass 26, count 0 2006.253.08:15:51.02#ibcon#about to read 4, iclass 26, count 0 2006.253.08:15:51.02#ibcon#read 4, iclass 26, count 0 2006.253.08:15:51.02#ibcon#about to read 5, iclass 26, count 0 2006.253.08:15:51.02#ibcon#read 5, iclass 26, count 0 2006.253.08:15:51.02#ibcon#about to read 6, iclass 26, count 0 2006.253.08:15:51.02#ibcon#read 6, iclass 26, count 0 2006.253.08:15:51.02#ibcon#end of sib2, iclass 26, count 0 2006.253.08:15:51.02#ibcon#*after write, iclass 26, count 0 2006.253.08:15:51.02#ibcon#*before return 0, iclass 26, count 0 2006.253.08:15:51.02#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.253.08:15:51.02#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.253.08:15:51.02#ibcon#about to clear, iclass 26 cls_cnt 0 2006.253.08:15:51.02#ibcon#cleared, iclass 26 cls_cnt 0 2006.253.08:15:51.02$vc4f8/vb=2,5 2006.253.08:15:51.02#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.253.08:15:51.02#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.253.08:15:51.02#ibcon#ireg 11 cls_cnt 2 2006.253.08:15:51.02#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.253.08:15:51.07#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.253.08:15:51.07#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.253.08:15:51.07#ibcon#enter wrdev, iclass 28, count 2 2006.253.08:15:51.07#ibcon#first serial, iclass 28, count 2 2006.253.08:15:51.07#ibcon#enter sib2, iclass 28, count 2 2006.253.08:15:51.07#ibcon#flushed, iclass 28, count 2 2006.253.08:15:51.07#ibcon#about to write, iclass 28, count 2 2006.253.08:15:51.07#ibcon#wrote, iclass 28, count 2 2006.253.08:15:51.07#ibcon#about to read 3, iclass 28, count 2 2006.253.08:15:51.09#ibcon#read 3, iclass 28, count 2 2006.253.08:15:51.09#ibcon#about to read 4, iclass 28, count 2 2006.253.08:15:51.09#ibcon#read 4, iclass 28, count 2 2006.253.08:15:51.09#ibcon#about to read 5, iclass 28, count 2 2006.253.08:15:51.09#ibcon#read 5, iclass 28, count 2 2006.253.08:15:51.09#ibcon#about to read 6, iclass 28, count 2 2006.253.08:15:51.09#ibcon#read 6, iclass 28, count 2 2006.253.08:15:51.09#ibcon#end of sib2, iclass 28, count 2 2006.253.08:15:51.09#ibcon#*mode == 0, iclass 28, count 2 2006.253.08:15:51.09#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.253.08:15:51.09#ibcon#[27=AT02-05\r\n] 2006.253.08:15:51.09#ibcon#*before write, iclass 28, count 2 2006.253.08:15:51.09#ibcon#enter sib2, iclass 28, count 2 2006.253.08:15:51.09#ibcon#flushed, iclass 28, count 2 2006.253.08:15:51.09#ibcon#about to write, iclass 28, count 2 2006.253.08:15:51.09#ibcon#wrote, iclass 28, count 2 2006.253.08:15:51.09#ibcon#about to read 3, iclass 28, count 2 2006.253.08:15:51.12#ibcon#read 3, iclass 28, count 2 2006.253.08:15:51.12#ibcon#about to read 4, iclass 28, count 2 2006.253.08:15:51.12#ibcon#read 4, iclass 28, count 2 2006.253.08:15:51.12#ibcon#about to read 5, iclass 28, count 2 2006.253.08:15:51.12#ibcon#read 5, iclass 28, count 2 2006.253.08:15:51.12#ibcon#about to read 6, iclass 28, count 2 2006.253.08:15:51.12#ibcon#read 6, iclass 28, count 2 2006.253.08:15:51.12#ibcon#end of sib2, iclass 28, count 2 2006.253.08:15:51.12#ibcon#*after write, iclass 28, count 2 2006.253.08:15:51.12#ibcon#*before return 0, iclass 28, count 2 2006.253.08:15:51.12#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.253.08:15:51.12#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.253.08:15:51.12#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.253.08:15:51.12#ibcon#ireg 7 cls_cnt 0 2006.253.08:15:51.12#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.253.08:15:51.24#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.253.08:15:51.24#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.253.08:15:51.24#ibcon#enter wrdev, iclass 28, count 0 2006.253.08:15:51.24#ibcon#first serial, iclass 28, count 0 2006.253.08:15:51.24#ibcon#enter sib2, iclass 28, count 0 2006.253.08:15:51.24#ibcon#flushed, iclass 28, count 0 2006.253.08:15:51.24#ibcon#about to write, iclass 28, count 0 2006.253.08:15:51.24#ibcon#wrote, iclass 28, count 0 2006.253.08:15:51.24#ibcon#about to read 3, iclass 28, count 0 2006.253.08:15:51.26#ibcon#read 3, iclass 28, count 0 2006.253.08:15:51.26#ibcon#about to read 4, iclass 28, count 0 2006.253.08:15:51.26#ibcon#read 4, iclass 28, count 0 2006.253.08:15:51.26#ibcon#about to read 5, iclass 28, count 0 2006.253.08:15:51.26#ibcon#read 5, iclass 28, count 0 2006.253.08:15:51.26#ibcon#about to read 6, iclass 28, count 0 2006.253.08:15:51.26#ibcon#read 6, iclass 28, count 0 2006.253.08:15:51.26#ibcon#end of sib2, iclass 28, count 0 2006.253.08:15:51.26#ibcon#*mode == 0, iclass 28, count 0 2006.253.08:15:51.26#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.253.08:15:51.26#ibcon#[27=USB\r\n] 2006.253.08:15:51.26#ibcon#*before write, iclass 28, count 0 2006.253.08:15:51.26#ibcon#enter sib2, iclass 28, count 0 2006.253.08:15:51.26#ibcon#flushed, iclass 28, count 0 2006.253.08:15:51.26#ibcon#about to write, iclass 28, count 0 2006.253.08:15:51.26#ibcon#wrote, iclass 28, count 0 2006.253.08:15:51.26#ibcon#about to read 3, iclass 28, count 0 2006.253.08:15:51.29#ibcon#read 3, iclass 28, count 0 2006.253.08:15:51.29#ibcon#about to read 4, iclass 28, count 0 2006.253.08:15:51.29#ibcon#read 4, iclass 28, count 0 2006.253.08:15:51.29#ibcon#about to read 5, iclass 28, count 0 2006.253.08:15:51.29#ibcon#read 5, iclass 28, count 0 2006.253.08:15:51.29#ibcon#about to read 6, iclass 28, count 0 2006.253.08:15:51.29#ibcon#read 6, iclass 28, count 0 2006.253.08:15:51.29#ibcon#end of sib2, iclass 28, count 0 2006.253.08:15:51.29#ibcon#*after write, iclass 28, count 0 2006.253.08:15:51.29#ibcon#*before return 0, iclass 28, count 0 2006.253.08:15:51.29#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.253.08:15:51.29#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.253.08:15:51.29#ibcon#about to clear, iclass 28 cls_cnt 0 2006.253.08:15:51.29#ibcon#cleared, iclass 28 cls_cnt 0 2006.253.08:15:51.29$vc4f8/vblo=3,656.99 2006.253.08:15:51.29#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.253.08:15:51.29#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.253.08:15:51.29#ibcon#ireg 17 cls_cnt 0 2006.253.08:15:51.29#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.253.08:15:51.29#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.253.08:15:51.29#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.253.08:15:51.29#ibcon#enter wrdev, iclass 30, count 0 2006.253.08:15:51.29#ibcon#first serial, iclass 30, count 0 2006.253.08:15:51.29#ibcon#enter sib2, iclass 30, count 0 2006.253.08:15:51.29#ibcon#flushed, iclass 30, count 0 2006.253.08:15:51.29#ibcon#about to write, iclass 30, count 0 2006.253.08:15:51.29#ibcon#wrote, iclass 30, count 0 2006.253.08:15:51.29#ibcon#about to read 3, iclass 30, count 0 2006.253.08:15:51.31#ibcon#read 3, iclass 30, count 0 2006.253.08:15:51.31#ibcon#about to read 4, iclass 30, count 0 2006.253.08:15:51.31#ibcon#read 4, iclass 30, count 0 2006.253.08:15:51.31#ibcon#about to read 5, iclass 30, count 0 2006.253.08:15:51.31#ibcon#read 5, iclass 30, count 0 2006.253.08:15:51.31#ibcon#about to read 6, iclass 30, count 0 2006.253.08:15:51.31#ibcon#read 6, iclass 30, count 0 2006.253.08:15:51.31#ibcon#end of sib2, iclass 30, count 0 2006.253.08:15:51.31#ibcon#*mode == 0, iclass 30, count 0 2006.253.08:15:51.31#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.253.08:15:51.31#ibcon#[28=FRQ=03,656.99\r\n] 2006.253.08:15:51.31#ibcon#*before write, iclass 30, count 0 2006.253.08:15:51.31#ibcon#enter sib2, iclass 30, count 0 2006.253.08:15:51.31#ibcon#flushed, iclass 30, count 0 2006.253.08:15:51.31#ibcon#about to write, iclass 30, count 0 2006.253.08:15:51.31#ibcon#wrote, iclass 30, count 0 2006.253.08:15:51.31#ibcon#about to read 3, iclass 30, count 0 2006.253.08:15:51.35#ibcon#read 3, iclass 30, count 0 2006.253.08:15:51.35#ibcon#about to read 4, iclass 30, count 0 2006.253.08:15:51.35#ibcon#read 4, iclass 30, count 0 2006.253.08:15:51.35#ibcon#about to read 5, iclass 30, count 0 2006.253.08:15:51.35#ibcon#read 5, iclass 30, count 0 2006.253.08:15:51.35#ibcon#about to read 6, iclass 30, count 0 2006.253.08:15:51.35#ibcon#read 6, iclass 30, count 0 2006.253.08:15:51.35#ibcon#end of sib2, iclass 30, count 0 2006.253.08:15:51.35#ibcon#*after write, iclass 30, count 0 2006.253.08:15:51.35#ibcon#*before return 0, iclass 30, count 0 2006.253.08:15:51.35#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.253.08:15:51.35#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.253.08:15:51.35#ibcon#about to clear, iclass 30 cls_cnt 0 2006.253.08:15:51.35#ibcon#cleared, iclass 30 cls_cnt 0 2006.253.08:15:51.35$vc4f8/vb=3,4 2006.253.08:15:51.35#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.253.08:15:51.35#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.253.08:15:51.35#ibcon#ireg 11 cls_cnt 2 2006.253.08:15:51.35#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.253.08:15:51.41#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.253.08:15:51.41#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.253.08:15:51.41#ibcon#enter wrdev, iclass 32, count 2 2006.253.08:15:51.41#ibcon#first serial, iclass 32, count 2 2006.253.08:15:51.41#ibcon#enter sib2, iclass 32, count 2 2006.253.08:15:51.41#ibcon#flushed, iclass 32, count 2 2006.253.08:15:51.41#ibcon#about to write, iclass 32, count 2 2006.253.08:15:51.41#ibcon#wrote, iclass 32, count 2 2006.253.08:15:51.41#ibcon#about to read 3, iclass 32, count 2 2006.253.08:15:51.43#ibcon#read 3, iclass 32, count 2 2006.253.08:15:51.43#ibcon#about to read 4, iclass 32, count 2 2006.253.08:15:51.43#ibcon#read 4, iclass 32, count 2 2006.253.08:15:51.43#ibcon#about to read 5, iclass 32, count 2 2006.253.08:15:51.43#ibcon#read 5, iclass 32, count 2 2006.253.08:15:51.43#ibcon#about to read 6, iclass 32, count 2 2006.253.08:15:51.43#ibcon#read 6, iclass 32, count 2 2006.253.08:15:51.43#ibcon#end of sib2, iclass 32, count 2 2006.253.08:15:51.43#ibcon#*mode == 0, iclass 32, count 2 2006.253.08:15:51.43#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.253.08:15:51.43#ibcon#[27=AT03-04\r\n] 2006.253.08:15:51.43#ibcon#*before write, iclass 32, count 2 2006.253.08:15:51.43#ibcon#enter sib2, iclass 32, count 2 2006.253.08:15:51.43#ibcon#flushed, iclass 32, count 2 2006.253.08:15:51.43#ibcon#about to write, iclass 32, count 2 2006.253.08:15:51.43#ibcon#wrote, iclass 32, count 2 2006.253.08:15:51.43#ibcon#about to read 3, iclass 32, count 2 2006.253.08:15:51.46#ibcon#read 3, iclass 32, count 2 2006.253.08:15:51.46#ibcon#about to read 4, iclass 32, count 2 2006.253.08:15:51.46#ibcon#read 4, iclass 32, count 2 2006.253.08:15:51.46#ibcon#about to read 5, iclass 32, count 2 2006.253.08:15:51.46#ibcon#read 5, iclass 32, count 2 2006.253.08:15:51.46#ibcon#about to read 6, iclass 32, count 2 2006.253.08:15:51.46#ibcon#read 6, iclass 32, count 2 2006.253.08:15:51.46#ibcon#end of sib2, iclass 32, count 2 2006.253.08:15:51.46#ibcon#*after write, iclass 32, count 2 2006.253.08:15:51.46#ibcon#*before return 0, iclass 32, count 2 2006.253.08:15:51.46#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.253.08:15:51.46#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.253.08:15:51.46#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.253.08:15:51.46#ibcon#ireg 7 cls_cnt 0 2006.253.08:15:51.46#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.253.08:15:51.58#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.253.08:15:51.58#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.253.08:15:51.58#ibcon#enter wrdev, iclass 32, count 0 2006.253.08:15:51.58#ibcon#first serial, iclass 32, count 0 2006.253.08:15:51.58#ibcon#enter sib2, iclass 32, count 0 2006.253.08:15:51.58#ibcon#flushed, iclass 32, count 0 2006.253.08:15:51.58#ibcon#about to write, iclass 32, count 0 2006.253.08:15:51.58#ibcon#wrote, iclass 32, count 0 2006.253.08:15:51.58#ibcon#about to read 3, iclass 32, count 0 2006.253.08:15:51.60#ibcon#read 3, iclass 32, count 0 2006.253.08:15:51.60#ibcon#about to read 4, iclass 32, count 0 2006.253.08:15:51.60#ibcon#read 4, iclass 32, count 0 2006.253.08:15:51.60#ibcon#about to read 5, iclass 32, count 0 2006.253.08:15:51.60#ibcon#read 5, iclass 32, count 0 2006.253.08:15:51.60#ibcon#about to read 6, iclass 32, count 0 2006.253.08:15:51.60#ibcon#read 6, iclass 32, count 0 2006.253.08:15:51.60#ibcon#end of sib2, iclass 32, count 0 2006.253.08:15:51.60#ibcon#*mode == 0, iclass 32, count 0 2006.253.08:15:51.60#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.253.08:15:51.60#ibcon#[27=USB\r\n] 2006.253.08:15:51.60#ibcon#*before write, iclass 32, count 0 2006.253.08:15:51.60#ibcon#enter sib2, iclass 32, count 0 2006.253.08:15:51.60#ibcon#flushed, iclass 32, count 0 2006.253.08:15:51.60#ibcon#about to write, iclass 32, count 0 2006.253.08:15:51.60#ibcon#wrote, iclass 32, count 0 2006.253.08:15:51.60#ibcon#about to read 3, iclass 32, count 0 2006.253.08:15:51.63#ibcon#read 3, iclass 32, count 0 2006.253.08:15:51.63#ibcon#about to read 4, iclass 32, count 0 2006.253.08:15:51.63#ibcon#read 4, iclass 32, count 0 2006.253.08:15:51.63#ibcon#about to read 5, iclass 32, count 0 2006.253.08:15:51.63#ibcon#read 5, iclass 32, count 0 2006.253.08:15:51.63#ibcon#about to read 6, iclass 32, count 0 2006.253.08:15:51.63#ibcon#read 6, iclass 32, count 0 2006.253.08:15:51.63#ibcon#end of sib2, iclass 32, count 0 2006.253.08:15:51.63#ibcon#*after write, iclass 32, count 0 2006.253.08:15:51.63#ibcon#*before return 0, iclass 32, count 0 2006.253.08:15:51.63#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.253.08:15:51.63#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.253.08:15:51.63#ibcon#about to clear, iclass 32 cls_cnt 0 2006.253.08:15:51.63#ibcon#cleared, iclass 32 cls_cnt 0 2006.253.08:15:51.63$vc4f8/vblo=4,712.99 2006.253.08:15:51.63#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.253.08:15:51.63#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.253.08:15:51.63#ibcon#ireg 17 cls_cnt 0 2006.253.08:15:51.63#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.253.08:15:51.63#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.253.08:15:51.63#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.253.08:15:51.63#ibcon#enter wrdev, iclass 34, count 0 2006.253.08:15:51.63#ibcon#first serial, iclass 34, count 0 2006.253.08:15:51.63#ibcon#enter sib2, iclass 34, count 0 2006.253.08:15:51.63#ibcon#flushed, iclass 34, count 0 2006.253.08:15:51.63#ibcon#about to write, iclass 34, count 0 2006.253.08:15:51.63#ibcon#wrote, iclass 34, count 0 2006.253.08:15:51.63#ibcon#about to read 3, iclass 34, count 0 2006.253.08:15:51.65#ibcon#read 3, iclass 34, count 0 2006.253.08:15:51.65#ibcon#about to read 4, iclass 34, count 0 2006.253.08:15:51.65#ibcon#read 4, iclass 34, count 0 2006.253.08:15:51.65#ibcon#about to read 5, iclass 34, count 0 2006.253.08:15:51.65#ibcon#read 5, iclass 34, count 0 2006.253.08:15:51.65#ibcon#about to read 6, iclass 34, count 0 2006.253.08:15:51.65#ibcon#read 6, iclass 34, count 0 2006.253.08:15:51.65#ibcon#end of sib2, iclass 34, count 0 2006.253.08:15:51.65#ibcon#*mode == 0, iclass 34, count 0 2006.253.08:15:51.65#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.253.08:15:51.65#ibcon#[28=FRQ=04,712.99\r\n] 2006.253.08:15:51.65#ibcon#*before write, iclass 34, count 0 2006.253.08:15:51.65#ibcon#enter sib2, iclass 34, count 0 2006.253.08:15:51.65#ibcon#flushed, iclass 34, count 0 2006.253.08:15:51.65#ibcon#about to write, iclass 34, count 0 2006.253.08:15:51.65#ibcon#wrote, iclass 34, count 0 2006.253.08:15:51.65#ibcon#about to read 3, iclass 34, count 0 2006.253.08:15:51.70#ibcon#read 3, iclass 34, count 0 2006.253.08:15:51.70#ibcon#about to read 4, iclass 34, count 0 2006.253.08:15:51.70#ibcon#read 4, iclass 34, count 0 2006.253.08:15:51.70#ibcon#about to read 5, iclass 34, count 0 2006.253.08:15:51.70#ibcon#read 5, iclass 34, count 0 2006.253.08:15:51.70#ibcon#about to read 6, iclass 34, count 0 2006.253.08:15:51.70#ibcon#read 6, iclass 34, count 0 2006.253.08:15:51.70#ibcon#end of sib2, iclass 34, count 0 2006.253.08:15:51.70#ibcon#*after write, iclass 34, count 0 2006.253.08:15:51.70#ibcon#*before return 0, iclass 34, count 0 2006.253.08:15:51.70#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.253.08:15:51.70#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.253.08:15:51.70#ibcon#about to clear, iclass 34 cls_cnt 0 2006.253.08:15:51.70#ibcon#cleared, iclass 34 cls_cnt 0 2006.253.08:15:51.70$vc4f8/vb=4,4 2006.253.08:15:51.70#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.253.08:15:51.70#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.253.08:15:51.70#ibcon#ireg 11 cls_cnt 2 2006.253.08:15:51.70#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.253.08:15:51.75#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.253.08:15:51.75#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.253.08:15:51.75#ibcon#enter wrdev, iclass 36, count 2 2006.253.08:15:51.75#ibcon#first serial, iclass 36, count 2 2006.253.08:15:51.75#ibcon#enter sib2, iclass 36, count 2 2006.253.08:15:51.75#ibcon#flushed, iclass 36, count 2 2006.253.08:15:51.75#ibcon#about to write, iclass 36, count 2 2006.253.08:15:51.75#ibcon#wrote, iclass 36, count 2 2006.253.08:15:51.75#ibcon#about to read 3, iclass 36, count 2 2006.253.08:15:51.77#ibcon#read 3, iclass 36, count 2 2006.253.08:15:51.77#ibcon#about to read 4, iclass 36, count 2 2006.253.08:15:51.77#ibcon#read 4, iclass 36, count 2 2006.253.08:15:51.77#ibcon#about to read 5, iclass 36, count 2 2006.253.08:15:51.77#ibcon#read 5, iclass 36, count 2 2006.253.08:15:51.77#ibcon#about to read 6, iclass 36, count 2 2006.253.08:15:51.77#ibcon#read 6, iclass 36, count 2 2006.253.08:15:51.77#ibcon#end of sib2, iclass 36, count 2 2006.253.08:15:51.77#ibcon#*mode == 0, iclass 36, count 2 2006.253.08:15:51.77#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.253.08:15:51.77#ibcon#[27=AT04-04\r\n] 2006.253.08:15:51.77#ibcon#*before write, iclass 36, count 2 2006.253.08:15:51.77#ibcon#enter sib2, iclass 36, count 2 2006.253.08:15:51.77#ibcon#flushed, iclass 36, count 2 2006.253.08:15:51.77#ibcon#about to write, iclass 36, count 2 2006.253.08:15:51.77#ibcon#wrote, iclass 36, count 2 2006.253.08:15:51.77#ibcon#about to read 3, iclass 36, count 2 2006.253.08:15:51.80#ibcon#read 3, iclass 36, count 2 2006.253.08:15:51.80#ibcon#about to read 4, iclass 36, count 2 2006.253.08:15:51.80#ibcon#read 4, iclass 36, count 2 2006.253.08:15:51.80#ibcon#about to read 5, iclass 36, count 2 2006.253.08:15:51.80#ibcon#read 5, iclass 36, count 2 2006.253.08:15:51.80#ibcon#about to read 6, iclass 36, count 2 2006.253.08:15:51.80#ibcon#read 6, iclass 36, count 2 2006.253.08:15:51.80#ibcon#end of sib2, iclass 36, count 2 2006.253.08:15:51.80#ibcon#*after write, iclass 36, count 2 2006.253.08:15:51.80#ibcon#*before return 0, iclass 36, count 2 2006.253.08:15:51.80#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.253.08:15:51.80#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.253.08:15:51.80#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.253.08:15:51.80#ibcon#ireg 7 cls_cnt 0 2006.253.08:15:51.80#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.253.08:15:51.92#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.253.08:15:51.92#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.253.08:15:51.92#ibcon#enter wrdev, iclass 36, count 0 2006.253.08:15:51.92#ibcon#first serial, iclass 36, count 0 2006.253.08:15:51.92#ibcon#enter sib2, iclass 36, count 0 2006.253.08:15:51.92#ibcon#flushed, iclass 36, count 0 2006.253.08:15:51.92#ibcon#about to write, iclass 36, count 0 2006.253.08:15:51.92#ibcon#wrote, iclass 36, count 0 2006.253.08:15:51.92#ibcon#about to read 3, iclass 36, count 0 2006.253.08:15:51.94#ibcon#read 3, iclass 36, count 0 2006.253.08:15:51.94#ibcon#about to read 4, iclass 36, count 0 2006.253.08:15:51.94#ibcon#read 4, iclass 36, count 0 2006.253.08:15:51.94#ibcon#about to read 5, iclass 36, count 0 2006.253.08:15:51.94#ibcon#read 5, iclass 36, count 0 2006.253.08:15:51.94#ibcon#about to read 6, iclass 36, count 0 2006.253.08:15:51.94#ibcon#read 6, iclass 36, count 0 2006.253.08:15:51.94#ibcon#end of sib2, iclass 36, count 0 2006.253.08:15:51.94#ibcon#*mode == 0, iclass 36, count 0 2006.253.08:15:51.94#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.253.08:15:51.94#ibcon#[27=USB\r\n] 2006.253.08:15:51.94#ibcon#*before write, iclass 36, count 0 2006.253.08:15:51.94#ibcon#enter sib2, iclass 36, count 0 2006.253.08:15:51.94#ibcon#flushed, iclass 36, count 0 2006.253.08:15:51.94#ibcon#about to write, iclass 36, count 0 2006.253.08:15:51.94#ibcon#wrote, iclass 36, count 0 2006.253.08:15:51.94#ibcon#about to read 3, iclass 36, count 0 2006.253.08:15:51.97#ibcon#read 3, iclass 36, count 0 2006.253.08:15:51.97#ibcon#about to read 4, iclass 36, count 0 2006.253.08:15:51.97#ibcon#read 4, iclass 36, count 0 2006.253.08:15:51.97#ibcon#about to read 5, iclass 36, count 0 2006.253.08:15:51.97#ibcon#read 5, iclass 36, count 0 2006.253.08:15:51.97#ibcon#about to read 6, iclass 36, count 0 2006.253.08:15:51.97#ibcon#read 6, iclass 36, count 0 2006.253.08:15:51.97#ibcon#end of sib2, iclass 36, count 0 2006.253.08:15:51.97#ibcon#*after write, iclass 36, count 0 2006.253.08:15:51.97#ibcon#*before return 0, iclass 36, count 0 2006.253.08:15:51.97#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.253.08:15:51.97#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.253.08:15:51.97#ibcon#about to clear, iclass 36 cls_cnt 0 2006.253.08:15:51.97#ibcon#cleared, iclass 36 cls_cnt 0 2006.253.08:15:51.97$vc4f8/vblo=5,744.99 2006.253.08:15:51.97#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.253.08:15:51.97#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.253.08:15:51.97#ibcon#ireg 17 cls_cnt 0 2006.253.08:15:51.97#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.253.08:15:51.97#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.253.08:15:51.97#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.253.08:15:51.97#ibcon#enter wrdev, iclass 38, count 0 2006.253.08:15:51.97#ibcon#first serial, iclass 38, count 0 2006.253.08:15:51.97#ibcon#enter sib2, iclass 38, count 0 2006.253.08:15:51.97#ibcon#flushed, iclass 38, count 0 2006.253.08:15:51.97#ibcon#about to write, iclass 38, count 0 2006.253.08:15:51.97#ibcon#wrote, iclass 38, count 0 2006.253.08:15:51.97#ibcon#about to read 3, iclass 38, count 0 2006.253.08:15:51.99#ibcon#read 3, iclass 38, count 0 2006.253.08:15:51.99#ibcon#about to read 4, iclass 38, count 0 2006.253.08:15:51.99#ibcon#read 4, iclass 38, count 0 2006.253.08:15:51.99#ibcon#about to read 5, iclass 38, count 0 2006.253.08:15:51.99#ibcon#read 5, iclass 38, count 0 2006.253.08:15:51.99#ibcon#about to read 6, iclass 38, count 0 2006.253.08:15:51.99#ibcon#read 6, iclass 38, count 0 2006.253.08:15:51.99#ibcon#end of sib2, iclass 38, count 0 2006.253.08:15:51.99#ibcon#*mode == 0, iclass 38, count 0 2006.253.08:15:51.99#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.253.08:15:51.99#ibcon#[28=FRQ=05,744.99\r\n] 2006.253.08:15:51.99#ibcon#*before write, iclass 38, count 0 2006.253.08:15:51.99#ibcon#enter sib2, iclass 38, count 0 2006.253.08:15:51.99#ibcon#flushed, iclass 38, count 0 2006.253.08:15:51.99#ibcon#about to write, iclass 38, count 0 2006.253.08:15:51.99#ibcon#wrote, iclass 38, count 0 2006.253.08:15:51.99#ibcon#about to read 3, iclass 38, count 0 2006.253.08:15:52.03#ibcon#read 3, iclass 38, count 0 2006.253.08:15:52.03#ibcon#about to read 4, iclass 38, count 0 2006.253.08:15:52.03#ibcon#read 4, iclass 38, count 0 2006.253.08:15:52.03#ibcon#about to read 5, iclass 38, count 0 2006.253.08:15:52.03#ibcon#read 5, iclass 38, count 0 2006.253.08:15:52.03#ibcon#about to read 6, iclass 38, count 0 2006.253.08:15:52.03#ibcon#read 6, iclass 38, count 0 2006.253.08:15:52.03#ibcon#end of sib2, iclass 38, count 0 2006.253.08:15:52.03#ibcon#*after write, iclass 38, count 0 2006.253.08:15:52.03#ibcon#*before return 0, iclass 38, count 0 2006.253.08:15:52.03#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.253.08:15:52.03#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.253.08:15:52.03#ibcon#about to clear, iclass 38 cls_cnt 0 2006.253.08:15:52.03#ibcon#cleared, iclass 38 cls_cnt 0 2006.253.08:15:52.03$vc4f8/vb=5,4 2006.253.08:15:52.03#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.253.08:15:52.03#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.253.08:15:52.03#ibcon#ireg 11 cls_cnt 2 2006.253.08:15:52.03#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.253.08:15:52.09#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.253.08:15:52.09#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.253.08:15:52.09#ibcon#enter wrdev, iclass 40, count 2 2006.253.08:15:52.09#ibcon#first serial, iclass 40, count 2 2006.253.08:15:52.09#ibcon#enter sib2, iclass 40, count 2 2006.253.08:15:52.09#ibcon#flushed, iclass 40, count 2 2006.253.08:15:52.09#ibcon#about to write, iclass 40, count 2 2006.253.08:15:52.09#ibcon#wrote, iclass 40, count 2 2006.253.08:15:52.09#ibcon#about to read 3, iclass 40, count 2 2006.253.08:15:52.11#ibcon#read 3, iclass 40, count 2 2006.253.08:15:52.11#ibcon#about to read 4, iclass 40, count 2 2006.253.08:15:52.11#ibcon#read 4, iclass 40, count 2 2006.253.08:15:52.11#ibcon#about to read 5, iclass 40, count 2 2006.253.08:15:52.11#ibcon#read 5, iclass 40, count 2 2006.253.08:15:52.11#ibcon#about to read 6, iclass 40, count 2 2006.253.08:15:52.11#ibcon#read 6, iclass 40, count 2 2006.253.08:15:52.11#ibcon#end of sib2, iclass 40, count 2 2006.253.08:15:52.11#ibcon#*mode == 0, iclass 40, count 2 2006.253.08:15:52.11#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.253.08:15:52.11#ibcon#[27=AT05-04\r\n] 2006.253.08:15:52.11#ibcon#*before write, iclass 40, count 2 2006.253.08:15:52.11#ibcon#enter sib2, iclass 40, count 2 2006.253.08:15:52.11#ibcon#flushed, iclass 40, count 2 2006.253.08:15:52.11#ibcon#about to write, iclass 40, count 2 2006.253.08:15:52.11#ibcon#wrote, iclass 40, count 2 2006.253.08:15:52.11#ibcon#about to read 3, iclass 40, count 2 2006.253.08:15:52.14#ibcon#read 3, iclass 40, count 2 2006.253.08:15:52.14#ibcon#about to read 4, iclass 40, count 2 2006.253.08:15:52.14#ibcon#read 4, iclass 40, count 2 2006.253.08:15:52.14#ibcon#about to read 5, iclass 40, count 2 2006.253.08:15:52.14#ibcon#read 5, iclass 40, count 2 2006.253.08:15:52.14#ibcon#about to read 6, iclass 40, count 2 2006.253.08:15:52.14#ibcon#read 6, iclass 40, count 2 2006.253.08:15:52.14#ibcon#end of sib2, iclass 40, count 2 2006.253.08:15:52.14#ibcon#*after write, iclass 40, count 2 2006.253.08:15:52.14#ibcon#*before return 0, iclass 40, count 2 2006.253.08:15:52.14#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.253.08:15:52.14#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.253.08:15:52.14#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.253.08:15:52.14#ibcon#ireg 7 cls_cnt 0 2006.253.08:15:52.14#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.253.08:15:52.26#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.253.08:15:52.26#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.253.08:15:52.26#ibcon#enter wrdev, iclass 40, count 0 2006.253.08:15:52.26#ibcon#first serial, iclass 40, count 0 2006.253.08:15:52.26#ibcon#enter sib2, iclass 40, count 0 2006.253.08:15:52.26#ibcon#flushed, iclass 40, count 0 2006.253.08:15:52.26#ibcon#about to write, iclass 40, count 0 2006.253.08:15:52.26#ibcon#wrote, iclass 40, count 0 2006.253.08:15:52.26#ibcon#about to read 3, iclass 40, count 0 2006.253.08:15:52.28#ibcon#read 3, iclass 40, count 0 2006.253.08:15:52.28#ibcon#about to read 4, iclass 40, count 0 2006.253.08:15:52.28#ibcon#read 4, iclass 40, count 0 2006.253.08:15:52.28#ibcon#about to read 5, iclass 40, count 0 2006.253.08:15:52.28#ibcon#read 5, iclass 40, count 0 2006.253.08:15:52.28#ibcon#about to read 6, iclass 40, count 0 2006.253.08:15:52.28#ibcon#read 6, iclass 40, count 0 2006.253.08:15:52.28#ibcon#end of sib2, iclass 40, count 0 2006.253.08:15:52.28#ibcon#*mode == 0, iclass 40, count 0 2006.253.08:15:52.28#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.253.08:15:52.28#ibcon#[27=USB\r\n] 2006.253.08:15:52.28#ibcon#*before write, iclass 40, count 0 2006.253.08:15:52.28#ibcon#enter sib2, iclass 40, count 0 2006.253.08:15:52.28#ibcon#flushed, iclass 40, count 0 2006.253.08:15:52.28#ibcon#about to write, iclass 40, count 0 2006.253.08:15:52.28#ibcon#wrote, iclass 40, count 0 2006.253.08:15:52.28#ibcon#about to read 3, iclass 40, count 0 2006.253.08:15:52.31#ibcon#read 3, iclass 40, count 0 2006.253.08:15:52.31#ibcon#about to read 4, iclass 40, count 0 2006.253.08:15:52.31#ibcon#read 4, iclass 40, count 0 2006.253.08:15:52.31#ibcon#about to read 5, iclass 40, count 0 2006.253.08:15:52.31#ibcon#read 5, iclass 40, count 0 2006.253.08:15:52.31#ibcon#about to read 6, iclass 40, count 0 2006.253.08:15:52.31#ibcon#read 6, iclass 40, count 0 2006.253.08:15:52.31#ibcon#end of sib2, iclass 40, count 0 2006.253.08:15:52.31#ibcon#*after write, iclass 40, count 0 2006.253.08:15:52.31#ibcon#*before return 0, iclass 40, count 0 2006.253.08:15:52.31#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.253.08:15:52.31#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.253.08:15:52.31#ibcon#about to clear, iclass 40 cls_cnt 0 2006.253.08:15:52.31#ibcon#cleared, iclass 40 cls_cnt 0 2006.253.08:15:52.31$vc4f8/vblo=6,752.99 2006.253.08:15:52.31#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.253.08:15:52.31#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.253.08:15:52.31#ibcon#ireg 17 cls_cnt 0 2006.253.08:15:52.31#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.253.08:15:52.31#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.253.08:15:52.31#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.253.08:15:52.31#ibcon#enter wrdev, iclass 4, count 0 2006.253.08:15:52.31#ibcon#first serial, iclass 4, count 0 2006.253.08:15:52.31#ibcon#enter sib2, iclass 4, count 0 2006.253.08:15:52.31#ibcon#flushed, iclass 4, count 0 2006.253.08:15:52.31#ibcon#about to write, iclass 4, count 0 2006.253.08:15:52.31#ibcon#wrote, iclass 4, count 0 2006.253.08:15:52.31#ibcon#about to read 3, iclass 4, count 0 2006.253.08:15:52.33#ibcon#read 3, iclass 4, count 0 2006.253.08:15:52.33#ibcon#about to read 4, iclass 4, count 0 2006.253.08:15:52.33#ibcon#read 4, iclass 4, count 0 2006.253.08:15:52.33#ibcon#about to read 5, iclass 4, count 0 2006.253.08:15:52.33#ibcon#read 5, iclass 4, count 0 2006.253.08:15:52.33#ibcon#about to read 6, iclass 4, count 0 2006.253.08:15:52.33#ibcon#read 6, iclass 4, count 0 2006.253.08:15:52.33#ibcon#end of sib2, iclass 4, count 0 2006.253.08:15:52.33#ibcon#*mode == 0, iclass 4, count 0 2006.253.08:15:52.33#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.253.08:15:52.33#ibcon#[28=FRQ=06,752.99\r\n] 2006.253.08:15:52.33#ibcon#*before write, iclass 4, count 0 2006.253.08:15:52.33#ibcon#enter sib2, iclass 4, count 0 2006.253.08:15:52.33#ibcon#flushed, iclass 4, count 0 2006.253.08:15:52.33#ibcon#about to write, iclass 4, count 0 2006.253.08:15:52.33#ibcon#wrote, iclass 4, count 0 2006.253.08:15:52.33#ibcon#about to read 3, iclass 4, count 0 2006.253.08:15:52.37#ibcon#read 3, iclass 4, count 0 2006.253.08:15:52.37#ibcon#about to read 4, iclass 4, count 0 2006.253.08:15:52.37#ibcon#read 4, iclass 4, count 0 2006.253.08:15:52.37#ibcon#about to read 5, iclass 4, count 0 2006.253.08:15:52.37#ibcon#read 5, iclass 4, count 0 2006.253.08:15:52.37#ibcon#about to read 6, iclass 4, count 0 2006.253.08:15:52.37#ibcon#read 6, iclass 4, count 0 2006.253.08:15:52.37#ibcon#end of sib2, iclass 4, count 0 2006.253.08:15:52.37#ibcon#*after write, iclass 4, count 0 2006.253.08:15:52.37#ibcon#*before return 0, iclass 4, count 0 2006.253.08:15:52.37#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.253.08:15:52.37#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.253.08:15:52.37#ibcon#about to clear, iclass 4 cls_cnt 0 2006.253.08:15:52.37#ibcon#cleared, iclass 4 cls_cnt 0 2006.253.08:15:52.37$vc4f8/vb=6,4 2006.253.08:15:52.37#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.253.08:15:52.37#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.253.08:15:52.37#ibcon#ireg 11 cls_cnt 2 2006.253.08:15:52.37#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.253.08:15:52.43#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.253.08:15:52.43#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.253.08:15:52.43#ibcon#enter wrdev, iclass 6, count 2 2006.253.08:15:52.43#ibcon#first serial, iclass 6, count 2 2006.253.08:15:52.43#ibcon#enter sib2, iclass 6, count 2 2006.253.08:15:52.43#ibcon#flushed, iclass 6, count 2 2006.253.08:15:52.43#ibcon#about to write, iclass 6, count 2 2006.253.08:15:52.43#ibcon#wrote, iclass 6, count 2 2006.253.08:15:52.43#ibcon#about to read 3, iclass 6, count 2 2006.253.08:15:52.45#ibcon#read 3, iclass 6, count 2 2006.253.08:15:52.45#ibcon#about to read 4, iclass 6, count 2 2006.253.08:15:52.45#ibcon#read 4, iclass 6, count 2 2006.253.08:15:52.45#ibcon#about to read 5, iclass 6, count 2 2006.253.08:15:52.45#ibcon#read 5, iclass 6, count 2 2006.253.08:15:52.45#ibcon#about to read 6, iclass 6, count 2 2006.253.08:15:52.45#ibcon#read 6, iclass 6, count 2 2006.253.08:15:52.45#ibcon#end of sib2, iclass 6, count 2 2006.253.08:15:52.45#ibcon#*mode == 0, iclass 6, count 2 2006.253.08:15:52.45#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.253.08:15:52.45#ibcon#[27=AT06-04\r\n] 2006.253.08:15:52.45#ibcon#*before write, iclass 6, count 2 2006.253.08:15:52.45#ibcon#enter sib2, iclass 6, count 2 2006.253.08:15:52.45#ibcon#flushed, iclass 6, count 2 2006.253.08:15:52.45#ibcon#about to write, iclass 6, count 2 2006.253.08:15:52.45#ibcon#wrote, iclass 6, count 2 2006.253.08:15:52.45#ibcon#about to read 3, iclass 6, count 2 2006.253.08:15:52.48#ibcon#read 3, iclass 6, count 2 2006.253.08:15:52.48#ibcon#about to read 4, iclass 6, count 2 2006.253.08:15:52.48#ibcon#read 4, iclass 6, count 2 2006.253.08:15:52.48#ibcon#about to read 5, iclass 6, count 2 2006.253.08:15:52.48#ibcon#read 5, iclass 6, count 2 2006.253.08:15:52.48#ibcon#about to read 6, iclass 6, count 2 2006.253.08:15:52.48#ibcon#read 6, iclass 6, count 2 2006.253.08:15:52.48#ibcon#end of sib2, iclass 6, count 2 2006.253.08:15:52.48#ibcon#*after write, iclass 6, count 2 2006.253.08:15:52.48#ibcon#*before return 0, iclass 6, count 2 2006.253.08:15:52.48#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.253.08:15:52.48#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.253.08:15:52.48#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.253.08:15:52.48#ibcon#ireg 7 cls_cnt 0 2006.253.08:15:52.48#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.253.08:15:52.60#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.253.08:15:52.60#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.253.08:15:52.60#ibcon#enter wrdev, iclass 6, count 0 2006.253.08:15:52.60#ibcon#first serial, iclass 6, count 0 2006.253.08:15:52.60#ibcon#enter sib2, iclass 6, count 0 2006.253.08:15:52.60#ibcon#flushed, iclass 6, count 0 2006.253.08:15:52.60#ibcon#about to write, iclass 6, count 0 2006.253.08:15:52.60#ibcon#wrote, iclass 6, count 0 2006.253.08:15:52.60#ibcon#about to read 3, iclass 6, count 0 2006.253.08:15:52.62#ibcon#read 3, iclass 6, count 0 2006.253.08:15:52.62#ibcon#about to read 4, iclass 6, count 0 2006.253.08:15:52.62#ibcon#read 4, iclass 6, count 0 2006.253.08:15:52.62#ibcon#about to read 5, iclass 6, count 0 2006.253.08:15:52.62#ibcon#read 5, iclass 6, count 0 2006.253.08:15:52.62#ibcon#about to read 6, iclass 6, count 0 2006.253.08:15:52.62#ibcon#read 6, iclass 6, count 0 2006.253.08:15:52.62#ibcon#end of sib2, iclass 6, count 0 2006.253.08:15:52.62#ibcon#*mode == 0, iclass 6, count 0 2006.253.08:15:52.62#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.253.08:15:52.62#ibcon#[27=USB\r\n] 2006.253.08:15:52.62#ibcon#*before write, iclass 6, count 0 2006.253.08:15:52.62#ibcon#enter sib2, iclass 6, count 0 2006.253.08:15:52.62#ibcon#flushed, iclass 6, count 0 2006.253.08:15:52.62#ibcon#about to write, iclass 6, count 0 2006.253.08:15:52.62#ibcon#wrote, iclass 6, count 0 2006.253.08:15:52.62#ibcon#about to read 3, iclass 6, count 0 2006.253.08:15:52.65#ibcon#read 3, iclass 6, count 0 2006.253.08:15:52.65#ibcon#about to read 4, iclass 6, count 0 2006.253.08:15:52.65#ibcon#read 4, iclass 6, count 0 2006.253.08:15:52.65#ibcon#about to read 5, iclass 6, count 0 2006.253.08:15:52.65#ibcon#read 5, iclass 6, count 0 2006.253.08:15:52.65#ibcon#about to read 6, iclass 6, count 0 2006.253.08:15:52.65#ibcon#read 6, iclass 6, count 0 2006.253.08:15:52.65#ibcon#end of sib2, iclass 6, count 0 2006.253.08:15:52.65#ibcon#*after write, iclass 6, count 0 2006.253.08:15:52.65#ibcon#*before return 0, iclass 6, count 0 2006.253.08:15:52.65#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.253.08:15:52.65#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.253.08:15:52.65#ibcon#about to clear, iclass 6 cls_cnt 0 2006.253.08:15:52.65#ibcon#cleared, iclass 6 cls_cnt 0 2006.253.08:15:52.65$vc4f8/vabw=wide 2006.253.08:15:52.65#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.253.08:15:52.65#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.253.08:15:52.65#ibcon#ireg 8 cls_cnt 0 2006.253.08:15:52.65#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.253.08:15:52.65#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.253.08:15:52.65#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.253.08:15:52.65#ibcon#enter wrdev, iclass 10, count 0 2006.253.08:15:52.65#ibcon#first serial, iclass 10, count 0 2006.253.08:15:52.65#ibcon#enter sib2, iclass 10, count 0 2006.253.08:15:52.65#ibcon#flushed, iclass 10, count 0 2006.253.08:15:52.65#ibcon#about to write, iclass 10, count 0 2006.253.08:15:52.65#ibcon#wrote, iclass 10, count 0 2006.253.08:15:52.65#ibcon#about to read 3, iclass 10, count 0 2006.253.08:15:52.67#ibcon#read 3, iclass 10, count 0 2006.253.08:15:52.67#ibcon#about to read 4, iclass 10, count 0 2006.253.08:15:52.67#ibcon#read 4, iclass 10, count 0 2006.253.08:15:52.67#ibcon#about to read 5, iclass 10, count 0 2006.253.08:15:52.67#ibcon#read 5, iclass 10, count 0 2006.253.08:15:52.67#ibcon#about to read 6, iclass 10, count 0 2006.253.08:15:52.67#ibcon#read 6, iclass 10, count 0 2006.253.08:15:52.67#ibcon#end of sib2, iclass 10, count 0 2006.253.08:15:52.67#ibcon#*mode == 0, iclass 10, count 0 2006.253.08:15:52.67#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.253.08:15:52.67#ibcon#[25=BW32\r\n] 2006.253.08:15:52.67#ibcon#*before write, iclass 10, count 0 2006.253.08:15:52.67#ibcon#enter sib2, iclass 10, count 0 2006.253.08:15:52.67#ibcon#flushed, iclass 10, count 0 2006.253.08:15:52.67#ibcon#about to write, iclass 10, count 0 2006.253.08:15:52.67#ibcon#wrote, iclass 10, count 0 2006.253.08:15:52.67#ibcon#about to read 3, iclass 10, count 0 2006.253.08:15:52.71#ibcon#read 3, iclass 10, count 0 2006.253.08:15:52.71#ibcon#about to read 4, iclass 10, count 0 2006.253.08:15:52.71#ibcon#read 4, iclass 10, count 0 2006.253.08:15:52.71#ibcon#about to read 5, iclass 10, count 0 2006.253.08:15:52.71#ibcon#read 5, iclass 10, count 0 2006.253.08:15:52.71#ibcon#about to read 6, iclass 10, count 0 2006.253.08:15:52.71#ibcon#read 6, iclass 10, count 0 2006.253.08:15:52.71#ibcon#end of sib2, iclass 10, count 0 2006.253.08:15:52.71#ibcon#*after write, iclass 10, count 0 2006.253.08:15:52.71#ibcon#*before return 0, iclass 10, count 0 2006.253.08:15:52.71#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.253.08:15:52.71#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.253.08:15:52.71#ibcon#about to clear, iclass 10 cls_cnt 0 2006.253.08:15:52.71#ibcon#cleared, iclass 10 cls_cnt 0 2006.253.08:15:52.71$vc4f8/vbbw=wide 2006.253.08:15:52.71#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.253.08:15:52.71#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.253.08:15:52.71#ibcon#ireg 8 cls_cnt 0 2006.253.08:15:52.71#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.253.08:15:52.77#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.253.08:15:52.77#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.253.08:15:52.77#ibcon#enter wrdev, iclass 12, count 0 2006.253.08:15:52.77#ibcon#first serial, iclass 12, count 0 2006.253.08:15:52.77#ibcon#enter sib2, iclass 12, count 0 2006.253.08:15:52.77#ibcon#flushed, iclass 12, count 0 2006.253.08:15:52.77#ibcon#about to write, iclass 12, count 0 2006.253.08:15:52.77#ibcon#wrote, iclass 12, count 0 2006.253.08:15:52.77#ibcon#about to read 3, iclass 12, count 0 2006.253.08:15:52.79#ibcon#read 3, iclass 12, count 0 2006.253.08:15:52.79#ibcon#about to read 4, iclass 12, count 0 2006.253.08:15:52.79#ibcon#read 4, iclass 12, count 0 2006.253.08:15:52.79#ibcon#about to read 5, iclass 12, count 0 2006.253.08:15:52.79#ibcon#read 5, iclass 12, count 0 2006.253.08:15:52.79#ibcon#about to read 6, iclass 12, count 0 2006.253.08:15:52.79#ibcon#read 6, iclass 12, count 0 2006.253.08:15:52.79#ibcon#end of sib2, iclass 12, count 0 2006.253.08:15:52.79#ibcon#*mode == 0, iclass 12, count 0 2006.253.08:15:52.79#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.253.08:15:52.79#ibcon#[27=BW32\r\n] 2006.253.08:15:52.79#ibcon#*before write, iclass 12, count 0 2006.253.08:15:52.79#ibcon#enter sib2, iclass 12, count 0 2006.253.08:15:52.79#ibcon#flushed, iclass 12, count 0 2006.253.08:15:52.79#ibcon#about to write, iclass 12, count 0 2006.253.08:15:52.79#ibcon#wrote, iclass 12, count 0 2006.253.08:15:52.79#ibcon#about to read 3, iclass 12, count 0 2006.253.08:15:52.82#ibcon#read 3, iclass 12, count 0 2006.253.08:15:52.82#ibcon#about to read 4, iclass 12, count 0 2006.253.08:15:52.82#ibcon#read 4, iclass 12, count 0 2006.253.08:15:52.82#ibcon#about to read 5, iclass 12, count 0 2006.253.08:15:52.82#ibcon#read 5, iclass 12, count 0 2006.253.08:15:52.82#ibcon#about to read 6, iclass 12, count 0 2006.253.08:15:52.82#ibcon#read 6, iclass 12, count 0 2006.253.08:15:52.82#ibcon#end of sib2, iclass 12, count 0 2006.253.08:15:52.82#ibcon#*after write, iclass 12, count 0 2006.253.08:15:52.82#ibcon#*before return 0, iclass 12, count 0 2006.253.08:15:52.82#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.253.08:15:52.82#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.253.08:15:52.82#ibcon#about to clear, iclass 12 cls_cnt 0 2006.253.08:15:52.82#ibcon#cleared, iclass 12 cls_cnt 0 2006.253.08:15:52.82$4f8m12a/ifd4f 2006.253.08:15:52.82$ifd4f/lo= 2006.253.08:15:52.82$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.253.08:15:52.82$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.253.08:15:52.82$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.253.08:15:52.82$ifd4f/patch= 2006.253.08:15:52.82$ifd4f/patch=lo1,a1,a2,a3,a4 2006.253.08:15:52.82$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.253.08:15:52.82$ifd4f/patch=lo3,a5,a6,a7,a8 2006.253.08:15:52.82$4f8m12a/"form=m,16.000,1:2 2006.253.08:15:52.82$4f8m12a/"tpicd 2006.253.08:15:52.82$4f8m12a/echo=off 2006.253.08:15:52.82$4f8m12a/xlog=off 2006.253.08:15:52.82:!2006.253.08:16:20 2006.253.08:16:03.14#trakl#Source acquired 2006.253.08:16:05.14#flagr#flagr/antenna,acquired 2006.253.08:16:20.00:preob 2006.253.08:16:21.14/onsource/TRACKING 2006.253.08:16:21.14:!2006.253.08:16:30 2006.253.08:16:30.00:data_valid=on 2006.253.08:16:30.00:midob 2006.253.08:16:30.14/onsource/TRACKING 2006.253.08:16:30.14/wx/30.89,1006.5,74 2006.253.08:16:30.31/cable/+6.3682E-03 2006.253.08:16:31.40/va/01,08,usb,yes,34,35 2006.253.08:16:31.40/va/02,07,usb,yes,33,35 2006.253.08:16:31.40/va/03,06,usb,yes,36,36 2006.253.08:16:31.40/va/04,07,usb,yes,35,38 2006.253.08:16:31.40/va/05,07,usb,yes,37,39 2006.253.08:16:31.40/va/06,07,usb,yes,32,32 2006.253.08:16:31.40/va/07,07,usb,yes,32,32 2006.253.08:16:31.40/va/08,07,usb,yes,35,34 2006.253.08:16:31.63/valo/01,532.99,yes,locked 2006.253.08:16:31.63/valo/02,572.99,yes,locked 2006.253.08:16:31.63/valo/03,672.99,yes,locked 2006.253.08:16:31.63/valo/04,832.99,yes,locked 2006.253.08:16:31.63/valo/05,652.99,yes,locked 2006.253.08:16:31.63/valo/06,772.99,yes,locked 2006.253.08:16:31.63/valo/07,832.99,yes,locked 2006.253.08:16:31.63/valo/08,852.99,yes,locked 2006.253.08:16:32.72/vb/01,04,usb,yes,32,32 2006.253.08:16:32.72/vb/02,05,usb,yes,30,31 2006.253.08:16:32.72/vb/03,04,usb,yes,30,34 2006.253.08:16:32.72/vb/04,04,usb,yes,31,31 2006.253.08:16:32.72/vb/05,04,usb,yes,30,34 2006.253.08:16:32.72/vb/06,04,usb,yes,31,34 2006.253.08:16:32.72/vb/07,04,usb,yes,33,33 2006.253.08:16:32.72/vb/08,04,usb,yes,30,34 2006.253.08:16:32.96/vblo/01,632.99,yes,locked 2006.253.08:16:32.96/vblo/02,640.99,yes,locked 2006.253.08:16:32.96/vblo/03,656.99,yes,locked 2006.253.08:16:32.96/vblo/04,712.99,yes,locked 2006.253.08:16:32.96/vblo/05,744.99,yes,locked 2006.253.08:16:32.96/vblo/06,752.99,yes,locked 2006.253.08:16:32.96/vblo/07,734.99,yes,locked 2006.253.08:16:32.96/vblo/08,744.99,yes,locked 2006.253.08:16:33.11/vabw/8 2006.253.08:16:33.26/vbbw/8 2006.253.08:16:33.35/xfe/off,on,14.2 2006.253.08:16:33.73/ifatt/23,28,28,28 2006.253.08:16:34.08/fmout-gps/S +4.72E-07 2006.253.08:16:34.12:!2006.253.08:17:30 2006.253.08:17:30.00:data_valid=off 2006.253.08:17:30.00:postob 2006.253.08:17:30.09/cable/+6.3679E-03 2006.253.08:17:30.09/wx/30.87,1006.6,75 2006.253.08:17:31.08/fmout-gps/S +4.71E-07 2006.253.08:17:31.08:scan_name=253-0818,k06253,60 2006.253.08:17:31.08:source=1128+385,113053.28,381518.5,2000.0,ccw 2006.253.08:17:31.16#flagr#flagr/antenna,new-source 2006.253.08:17:32.14:checkk5 2006.253.08:17:32.52/chk_autoobs//k5ts1/ autoobs is running! 2006.253.08:17:32.90/chk_autoobs//k5ts2/ autoobs is running! 2006.253.08:17:33.27/chk_autoobs//k5ts3/ autoobs is running! 2006.253.08:17:33.65/chk_autoobs//k5ts4/ autoobs is running! 2006.253.08:17:34.01/chk_obsdata//k5ts1/T2530816??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.08:17:34.38/chk_obsdata//k5ts2/T2530816??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.08:17:34.75/chk_obsdata//k5ts3/T2530816??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.08:17:35.12/chk_obsdata//k5ts4/T2530816??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.08:17:35.83/k5log//k5ts1_log_newline 2006.253.08:17:36.54/k5log//k5ts2_log_newline 2006.253.08:17:37.25/k5log//k5ts3_log_newline 2006.253.08:17:37.95/k5log//k5ts4_log_newline 2006.253.08:17:37.98/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.253.08:17:37.98:4f8m12a=2 2006.253.08:17:37.98$4f8m12a/echo=on 2006.253.08:17:37.98$4f8m12a/pcalon 2006.253.08:17:37.98$pcalon/"no phase cal control is implemented here 2006.253.08:17:37.98$4f8m12a/"tpicd=stop 2006.253.08:17:37.98$4f8m12a/vc4f8 2006.253.08:17:37.98$vc4f8/valo=1,532.99 2006.253.08:17:37.98#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.253.08:17:37.98#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.253.08:17:37.98#ibcon#ireg 17 cls_cnt 0 2006.253.08:17:37.98#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.253.08:17:37.98#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.253.08:17:37.98#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.253.08:17:37.98#ibcon#enter wrdev, iclass 19, count 0 2006.253.08:17:37.98#ibcon#first serial, iclass 19, count 0 2006.253.08:17:37.98#ibcon#enter sib2, iclass 19, count 0 2006.253.08:17:37.98#ibcon#flushed, iclass 19, count 0 2006.253.08:17:37.98#ibcon#about to write, iclass 19, count 0 2006.253.08:17:37.98#ibcon#wrote, iclass 19, count 0 2006.253.08:17:37.98#ibcon#about to read 3, iclass 19, count 0 2006.253.08:17:38.00#ibcon#read 3, iclass 19, count 0 2006.253.08:17:38.00#ibcon#about to read 4, iclass 19, count 0 2006.253.08:17:38.00#ibcon#read 4, iclass 19, count 0 2006.253.08:17:38.00#ibcon#about to read 5, iclass 19, count 0 2006.253.08:17:38.00#ibcon#read 5, iclass 19, count 0 2006.253.08:17:38.00#ibcon#about to read 6, iclass 19, count 0 2006.253.08:17:38.00#ibcon#read 6, iclass 19, count 0 2006.253.08:17:38.00#ibcon#end of sib2, iclass 19, count 0 2006.253.08:17:38.00#ibcon#*mode == 0, iclass 19, count 0 2006.253.08:17:38.00#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.253.08:17:38.00#ibcon#[26=FRQ=01,532.99\r\n] 2006.253.08:17:38.00#ibcon#*before write, iclass 19, count 0 2006.253.08:17:38.00#ibcon#enter sib2, iclass 19, count 0 2006.253.08:17:38.00#ibcon#flushed, iclass 19, count 0 2006.253.08:17:38.00#ibcon#about to write, iclass 19, count 0 2006.253.08:17:38.00#ibcon#wrote, iclass 19, count 0 2006.253.08:17:38.00#ibcon#about to read 3, iclass 19, count 0 2006.253.08:17:38.05#ibcon#read 3, iclass 19, count 0 2006.253.08:17:38.05#ibcon#about to read 4, iclass 19, count 0 2006.253.08:17:38.05#ibcon#read 4, iclass 19, count 0 2006.253.08:17:38.05#ibcon#about to read 5, iclass 19, count 0 2006.253.08:17:38.05#ibcon#read 5, iclass 19, count 0 2006.253.08:17:38.05#ibcon#about to read 6, iclass 19, count 0 2006.253.08:17:38.05#ibcon#read 6, iclass 19, count 0 2006.253.08:17:38.05#ibcon#end of sib2, iclass 19, count 0 2006.253.08:17:38.05#ibcon#*after write, iclass 19, count 0 2006.253.08:17:38.05#ibcon#*before return 0, iclass 19, count 0 2006.253.08:17:38.05#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.253.08:17:38.05#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.253.08:17:38.05#ibcon#about to clear, iclass 19 cls_cnt 0 2006.253.08:17:38.05#ibcon#cleared, iclass 19 cls_cnt 0 2006.253.08:17:38.05$vc4f8/va=1,8 2006.253.08:17:38.05#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.253.08:17:38.05#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.253.08:17:38.05#ibcon#ireg 11 cls_cnt 2 2006.253.08:17:38.05#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.253.08:17:38.05#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.253.08:17:38.05#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.253.08:17:38.05#ibcon#enter wrdev, iclass 21, count 2 2006.253.08:17:38.05#ibcon#first serial, iclass 21, count 2 2006.253.08:17:38.05#ibcon#enter sib2, iclass 21, count 2 2006.253.08:17:38.05#ibcon#flushed, iclass 21, count 2 2006.253.08:17:38.05#ibcon#about to write, iclass 21, count 2 2006.253.08:17:38.05#ibcon#wrote, iclass 21, count 2 2006.253.08:17:38.05#ibcon#about to read 3, iclass 21, count 2 2006.253.08:17:38.07#ibcon#read 3, iclass 21, count 2 2006.253.08:17:38.07#ibcon#about to read 4, iclass 21, count 2 2006.253.08:17:38.07#ibcon#read 4, iclass 21, count 2 2006.253.08:17:38.07#ibcon#about to read 5, iclass 21, count 2 2006.253.08:17:38.07#ibcon#read 5, iclass 21, count 2 2006.253.08:17:38.07#ibcon#about to read 6, iclass 21, count 2 2006.253.08:17:38.07#ibcon#read 6, iclass 21, count 2 2006.253.08:17:38.07#ibcon#end of sib2, iclass 21, count 2 2006.253.08:17:38.07#ibcon#*mode == 0, iclass 21, count 2 2006.253.08:17:38.07#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.253.08:17:38.07#ibcon#[25=AT01-08\r\n] 2006.253.08:17:38.07#ibcon#*before write, iclass 21, count 2 2006.253.08:17:38.07#ibcon#enter sib2, iclass 21, count 2 2006.253.08:17:38.07#ibcon#flushed, iclass 21, count 2 2006.253.08:17:38.07#ibcon#about to write, iclass 21, count 2 2006.253.08:17:38.07#ibcon#wrote, iclass 21, count 2 2006.253.08:17:38.07#ibcon#about to read 3, iclass 21, count 2 2006.253.08:17:38.10#ibcon#read 3, iclass 21, count 2 2006.253.08:17:38.10#ibcon#about to read 4, iclass 21, count 2 2006.253.08:17:38.10#ibcon#read 4, iclass 21, count 2 2006.253.08:17:38.10#ibcon#about to read 5, iclass 21, count 2 2006.253.08:17:38.10#ibcon#read 5, iclass 21, count 2 2006.253.08:17:38.10#ibcon#about to read 6, iclass 21, count 2 2006.253.08:17:38.10#ibcon#read 6, iclass 21, count 2 2006.253.08:17:38.10#ibcon#end of sib2, iclass 21, count 2 2006.253.08:17:38.10#ibcon#*after write, iclass 21, count 2 2006.253.08:17:38.10#ibcon#*before return 0, iclass 21, count 2 2006.253.08:17:38.10#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.253.08:17:38.10#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.253.08:17:38.10#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.253.08:17:38.10#ibcon#ireg 7 cls_cnt 0 2006.253.08:17:38.10#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.253.08:17:38.22#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.253.08:17:38.22#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.253.08:17:38.22#ibcon#enter wrdev, iclass 21, count 0 2006.253.08:17:38.22#ibcon#first serial, iclass 21, count 0 2006.253.08:17:38.22#ibcon#enter sib2, iclass 21, count 0 2006.253.08:17:38.22#ibcon#flushed, iclass 21, count 0 2006.253.08:17:38.22#ibcon#about to write, iclass 21, count 0 2006.253.08:17:38.22#ibcon#wrote, iclass 21, count 0 2006.253.08:17:38.22#ibcon#about to read 3, iclass 21, count 0 2006.253.08:17:38.24#ibcon#read 3, iclass 21, count 0 2006.253.08:17:38.24#ibcon#about to read 4, iclass 21, count 0 2006.253.08:17:38.24#ibcon#read 4, iclass 21, count 0 2006.253.08:17:38.24#ibcon#about to read 5, iclass 21, count 0 2006.253.08:17:38.24#ibcon#read 5, iclass 21, count 0 2006.253.08:17:38.24#ibcon#about to read 6, iclass 21, count 0 2006.253.08:17:38.24#ibcon#read 6, iclass 21, count 0 2006.253.08:17:38.24#ibcon#end of sib2, iclass 21, count 0 2006.253.08:17:38.24#ibcon#*mode == 0, iclass 21, count 0 2006.253.08:17:38.24#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.253.08:17:38.24#ibcon#[25=USB\r\n] 2006.253.08:17:38.24#ibcon#*before write, iclass 21, count 0 2006.253.08:17:38.24#ibcon#enter sib2, iclass 21, count 0 2006.253.08:17:38.24#ibcon#flushed, iclass 21, count 0 2006.253.08:17:38.24#ibcon#about to write, iclass 21, count 0 2006.253.08:17:38.24#ibcon#wrote, iclass 21, count 0 2006.253.08:17:38.24#ibcon#about to read 3, iclass 21, count 0 2006.253.08:17:38.27#ibcon#read 3, iclass 21, count 0 2006.253.08:17:38.27#ibcon#about to read 4, iclass 21, count 0 2006.253.08:17:38.27#ibcon#read 4, iclass 21, count 0 2006.253.08:17:38.27#ibcon#about to read 5, iclass 21, count 0 2006.253.08:17:38.27#ibcon#read 5, iclass 21, count 0 2006.253.08:17:38.27#ibcon#about to read 6, iclass 21, count 0 2006.253.08:17:38.27#ibcon#read 6, iclass 21, count 0 2006.253.08:17:38.27#ibcon#end of sib2, iclass 21, count 0 2006.253.08:17:38.27#ibcon#*after write, iclass 21, count 0 2006.253.08:17:38.27#ibcon#*before return 0, iclass 21, count 0 2006.253.08:17:38.27#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.253.08:17:38.27#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.253.08:17:38.27#ibcon#about to clear, iclass 21 cls_cnt 0 2006.253.08:17:38.27#ibcon#cleared, iclass 21 cls_cnt 0 2006.253.08:17:38.27$vc4f8/valo=2,572.99 2006.253.08:17:38.27#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.253.08:17:38.27#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.253.08:17:38.27#ibcon#ireg 17 cls_cnt 0 2006.253.08:17:38.27#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.253.08:17:38.27#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.253.08:17:38.27#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.253.08:17:38.27#ibcon#enter wrdev, iclass 23, count 0 2006.253.08:17:38.27#ibcon#first serial, iclass 23, count 0 2006.253.08:17:38.27#ibcon#enter sib2, iclass 23, count 0 2006.253.08:17:38.27#ibcon#flushed, iclass 23, count 0 2006.253.08:17:38.27#ibcon#about to write, iclass 23, count 0 2006.253.08:17:38.27#ibcon#wrote, iclass 23, count 0 2006.253.08:17:38.27#ibcon#about to read 3, iclass 23, count 0 2006.253.08:17:38.29#ibcon#read 3, iclass 23, count 0 2006.253.08:17:38.29#ibcon#about to read 4, iclass 23, count 0 2006.253.08:17:38.29#ibcon#read 4, iclass 23, count 0 2006.253.08:17:38.29#ibcon#about to read 5, iclass 23, count 0 2006.253.08:17:38.29#ibcon#read 5, iclass 23, count 0 2006.253.08:17:38.29#ibcon#about to read 6, iclass 23, count 0 2006.253.08:17:38.29#ibcon#read 6, iclass 23, count 0 2006.253.08:17:38.29#ibcon#end of sib2, iclass 23, count 0 2006.253.08:17:38.29#ibcon#*mode == 0, iclass 23, count 0 2006.253.08:17:38.29#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.253.08:17:38.29#ibcon#[26=FRQ=02,572.99\r\n] 2006.253.08:17:38.29#ibcon#*before write, iclass 23, count 0 2006.253.08:17:38.29#ibcon#enter sib2, iclass 23, count 0 2006.253.08:17:38.29#ibcon#flushed, iclass 23, count 0 2006.253.08:17:38.29#ibcon#about to write, iclass 23, count 0 2006.253.08:17:38.29#ibcon#wrote, iclass 23, count 0 2006.253.08:17:38.29#ibcon#about to read 3, iclass 23, count 0 2006.253.08:17:38.34#ibcon#read 3, iclass 23, count 0 2006.253.08:17:38.34#ibcon#about to read 4, iclass 23, count 0 2006.253.08:17:38.34#ibcon#read 4, iclass 23, count 0 2006.253.08:17:38.34#ibcon#about to read 5, iclass 23, count 0 2006.253.08:17:38.34#ibcon#read 5, iclass 23, count 0 2006.253.08:17:38.34#ibcon#about to read 6, iclass 23, count 0 2006.253.08:17:38.34#ibcon#read 6, iclass 23, count 0 2006.253.08:17:38.34#ibcon#end of sib2, iclass 23, count 0 2006.253.08:17:38.34#ibcon#*after write, iclass 23, count 0 2006.253.08:17:38.34#ibcon#*before return 0, iclass 23, count 0 2006.253.08:17:38.34#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.253.08:17:38.34#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.253.08:17:38.34#ibcon#about to clear, iclass 23 cls_cnt 0 2006.253.08:17:38.34#ibcon#cleared, iclass 23 cls_cnt 0 2006.253.08:17:38.34$vc4f8/va=2,7 2006.253.08:17:38.34#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.253.08:17:38.34#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.253.08:17:38.34#ibcon#ireg 11 cls_cnt 2 2006.253.08:17:38.34#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.253.08:17:38.39#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.253.08:17:38.39#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.253.08:17:38.39#ibcon#enter wrdev, iclass 25, count 2 2006.253.08:17:38.39#ibcon#first serial, iclass 25, count 2 2006.253.08:17:38.39#ibcon#enter sib2, iclass 25, count 2 2006.253.08:17:38.39#ibcon#flushed, iclass 25, count 2 2006.253.08:17:38.39#ibcon#about to write, iclass 25, count 2 2006.253.08:17:38.39#ibcon#wrote, iclass 25, count 2 2006.253.08:17:38.39#ibcon#about to read 3, iclass 25, count 2 2006.253.08:17:38.41#ibcon#read 3, iclass 25, count 2 2006.253.08:17:38.41#ibcon#about to read 4, iclass 25, count 2 2006.253.08:17:38.41#ibcon#read 4, iclass 25, count 2 2006.253.08:17:38.41#ibcon#about to read 5, iclass 25, count 2 2006.253.08:17:38.41#ibcon#read 5, iclass 25, count 2 2006.253.08:17:38.41#ibcon#about to read 6, iclass 25, count 2 2006.253.08:17:38.41#ibcon#read 6, iclass 25, count 2 2006.253.08:17:38.41#ibcon#end of sib2, iclass 25, count 2 2006.253.08:17:38.41#ibcon#*mode == 0, iclass 25, count 2 2006.253.08:17:38.41#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.253.08:17:38.41#ibcon#[25=AT02-07\r\n] 2006.253.08:17:38.41#ibcon#*before write, iclass 25, count 2 2006.253.08:17:38.41#ibcon#enter sib2, iclass 25, count 2 2006.253.08:17:38.41#ibcon#flushed, iclass 25, count 2 2006.253.08:17:38.41#ibcon#about to write, iclass 25, count 2 2006.253.08:17:38.41#ibcon#wrote, iclass 25, count 2 2006.253.08:17:38.41#ibcon#about to read 3, iclass 25, count 2 2006.253.08:17:38.44#ibcon#read 3, iclass 25, count 2 2006.253.08:17:38.44#ibcon#about to read 4, iclass 25, count 2 2006.253.08:17:38.44#ibcon#read 4, iclass 25, count 2 2006.253.08:17:38.44#ibcon#about to read 5, iclass 25, count 2 2006.253.08:17:38.44#ibcon#read 5, iclass 25, count 2 2006.253.08:17:38.44#ibcon#about to read 6, iclass 25, count 2 2006.253.08:17:38.44#ibcon#read 6, iclass 25, count 2 2006.253.08:17:38.44#ibcon#end of sib2, iclass 25, count 2 2006.253.08:17:38.44#ibcon#*after write, iclass 25, count 2 2006.253.08:17:38.44#ibcon#*before return 0, iclass 25, count 2 2006.253.08:17:38.44#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.253.08:17:38.44#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.253.08:17:38.44#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.253.08:17:38.44#ibcon#ireg 7 cls_cnt 0 2006.253.08:17:38.44#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.253.08:17:38.56#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.253.08:17:38.56#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.253.08:17:38.56#ibcon#enter wrdev, iclass 25, count 0 2006.253.08:17:38.56#ibcon#first serial, iclass 25, count 0 2006.253.08:17:38.56#ibcon#enter sib2, iclass 25, count 0 2006.253.08:17:38.56#ibcon#flushed, iclass 25, count 0 2006.253.08:17:38.56#ibcon#about to write, iclass 25, count 0 2006.253.08:17:38.56#ibcon#wrote, iclass 25, count 0 2006.253.08:17:38.56#ibcon#about to read 3, iclass 25, count 0 2006.253.08:17:38.58#ibcon#read 3, iclass 25, count 0 2006.253.08:17:38.58#ibcon#about to read 4, iclass 25, count 0 2006.253.08:17:38.58#ibcon#read 4, iclass 25, count 0 2006.253.08:17:38.58#ibcon#about to read 5, iclass 25, count 0 2006.253.08:17:38.58#ibcon#read 5, iclass 25, count 0 2006.253.08:17:38.58#ibcon#about to read 6, iclass 25, count 0 2006.253.08:17:38.58#ibcon#read 6, iclass 25, count 0 2006.253.08:17:38.58#ibcon#end of sib2, iclass 25, count 0 2006.253.08:17:38.58#ibcon#*mode == 0, iclass 25, count 0 2006.253.08:17:38.58#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.253.08:17:38.58#ibcon#[25=USB\r\n] 2006.253.08:17:38.58#ibcon#*before write, iclass 25, count 0 2006.253.08:17:38.58#ibcon#enter sib2, iclass 25, count 0 2006.253.08:17:38.58#ibcon#flushed, iclass 25, count 0 2006.253.08:17:38.58#ibcon#about to write, iclass 25, count 0 2006.253.08:17:38.58#ibcon#wrote, iclass 25, count 0 2006.253.08:17:38.58#ibcon#about to read 3, iclass 25, count 0 2006.253.08:17:38.61#ibcon#read 3, iclass 25, count 0 2006.253.08:17:38.61#ibcon#about to read 4, iclass 25, count 0 2006.253.08:17:38.61#ibcon#read 4, iclass 25, count 0 2006.253.08:17:38.61#ibcon#about to read 5, iclass 25, count 0 2006.253.08:17:38.61#ibcon#read 5, iclass 25, count 0 2006.253.08:17:38.61#ibcon#about to read 6, iclass 25, count 0 2006.253.08:17:38.61#ibcon#read 6, iclass 25, count 0 2006.253.08:17:38.61#ibcon#end of sib2, iclass 25, count 0 2006.253.08:17:38.61#ibcon#*after write, iclass 25, count 0 2006.253.08:17:38.61#ibcon#*before return 0, iclass 25, count 0 2006.253.08:17:38.61#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.253.08:17:38.61#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.253.08:17:38.61#ibcon#about to clear, iclass 25 cls_cnt 0 2006.253.08:17:38.61#ibcon#cleared, iclass 25 cls_cnt 0 2006.253.08:17:38.61$vc4f8/valo=3,672.99 2006.253.08:17:38.61#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.253.08:17:38.61#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.253.08:17:38.61#ibcon#ireg 17 cls_cnt 0 2006.253.08:17:38.61#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.253.08:17:38.61#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.253.08:17:38.61#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.253.08:17:38.61#ibcon#enter wrdev, iclass 27, count 0 2006.253.08:17:38.61#ibcon#first serial, iclass 27, count 0 2006.253.08:17:38.61#ibcon#enter sib2, iclass 27, count 0 2006.253.08:17:38.61#ibcon#flushed, iclass 27, count 0 2006.253.08:17:38.61#ibcon#about to write, iclass 27, count 0 2006.253.08:17:38.61#ibcon#wrote, iclass 27, count 0 2006.253.08:17:38.61#ibcon#about to read 3, iclass 27, count 0 2006.253.08:17:38.63#ibcon#read 3, iclass 27, count 0 2006.253.08:17:38.63#ibcon#about to read 4, iclass 27, count 0 2006.253.08:17:38.63#ibcon#read 4, iclass 27, count 0 2006.253.08:17:38.63#ibcon#about to read 5, iclass 27, count 0 2006.253.08:17:38.63#ibcon#read 5, iclass 27, count 0 2006.253.08:17:38.63#ibcon#about to read 6, iclass 27, count 0 2006.253.08:17:38.63#ibcon#read 6, iclass 27, count 0 2006.253.08:17:38.63#ibcon#end of sib2, iclass 27, count 0 2006.253.08:17:38.63#ibcon#*mode == 0, iclass 27, count 0 2006.253.08:17:38.63#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.253.08:17:38.63#ibcon#[26=FRQ=03,672.99\r\n] 2006.253.08:17:38.63#ibcon#*before write, iclass 27, count 0 2006.253.08:17:38.63#ibcon#enter sib2, iclass 27, count 0 2006.253.08:17:38.63#ibcon#flushed, iclass 27, count 0 2006.253.08:17:38.63#ibcon#about to write, iclass 27, count 0 2006.253.08:17:38.63#ibcon#wrote, iclass 27, count 0 2006.253.08:17:38.63#ibcon#about to read 3, iclass 27, count 0 2006.253.08:17:38.68#ibcon#read 3, iclass 27, count 0 2006.253.08:17:38.68#ibcon#about to read 4, iclass 27, count 0 2006.253.08:17:38.68#ibcon#read 4, iclass 27, count 0 2006.253.08:17:38.68#ibcon#about to read 5, iclass 27, count 0 2006.253.08:17:38.68#ibcon#read 5, iclass 27, count 0 2006.253.08:17:38.68#ibcon#about to read 6, iclass 27, count 0 2006.253.08:17:38.68#ibcon#read 6, iclass 27, count 0 2006.253.08:17:38.68#ibcon#end of sib2, iclass 27, count 0 2006.253.08:17:38.68#ibcon#*after write, iclass 27, count 0 2006.253.08:17:38.68#ibcon#*before return 0, iclass 27, count 0 2006.253.08:17:38.68#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.253.08:17:38.68#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.253.08:17:38.68#ibcon#about to clear, iclass 27 cls_cnt 0 2006.253.08:17:38.68#ibcon#cleared, iclass 27 cls_cnt 0 2006.253.08:17:38.68$vc4f8/va=3,6 2006.253.08:17:38.68#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.253.08:17:38.68#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.253.08:17:38.68#ibcon#ireg 11 cls_cnt 2 2006.253.08:17:38.68#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.253.08:17:38.73#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.253.08:17:38.73#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.253.08:17:38.73#ibcon#enter wrdev, iclass 29, count 2 2006.253.08:17:38.73#ibcon#first serial, iclass 29, count 2 2006.253.08:17:38.73#ibcon#enter sib2, iclass 29, count 2 2006.253.08:17:38.73#ibcon#flushed, iclass 29, count 2 2006.253.08:17:38.73#ibcon#about to write, iclass 29, count 2 2006.253.08:17:38.73#ibcon#wrote, iclass 29, count 2 2006.253.08:17:38.73#ibcon#about to read 3, iclass 29, count 2 2006.253.08:17:38.75#ibcon#read 3, iclass 29, count 2 2006.253.08:17:38.75#ibcon#about to read 4, iclass 29, count 2 2006.253.08:17:38.75#ibcon#read 4, iclass 29, count 2 2006.253.08:17:38.75#ibcon#about to read 5, iclass 29, count 2 2006.253.08:17:38.75#ibcon#read 5, iclass 29, count 2 2006.253.08:17:38.75#ibcon#about to read 6, iclass 29, count 2 2006.253.08:17:38.75#ibcon#read 6, iclass 29, count 2 2006.253.08:17:38.75#ibcon#end of sib2, iclass 29, count 2 2006.253.08:17:38.75#ibcon#*mode == 0, iclass 29, count 2 2006.253.08:17:38.75#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.253.08:17:38.75#ibcon#[25=AT03-06\r\n] 2006.253.08:17:38.75#ibcon#*before write, iclass 29, count 2 2006.253.08:17:38.75#ibcon#enter sib2, iclass 29, count 2 2006.253.08:17:38.75#ibcon#flushed, iclass 29, count 2 2006.253.08:17:38.75#ibcon#about to write, iclass 29, count 2 2006.253.08:17:38.75#ibcon#wrote, iclass 29, count 2 2006.253.08:17:38.75#ibcon#about to read 3, iclass 29, count 2 2006.253.08:17:38.78#ibcon#read 3, iclass 29, count 2 2006.253.08:17:38.78#ibcon#about to read 4, iclass 29, count 2 2006.253.08:17:38.78#ibcon#read 4, iclass 29, count 2 2006.253.08:17:38.78#ibcon#about to read 5, iclass 29, count 2 2006.253.08:17:38.78#ibcon#read 5, iclass 29, count 2 2006.253.08:17:38.78#ibcon#about to read 6, iclass 29, count 2 2006.253.08:17:38.78#ibcon#read 6, iclass 29, count 2 2006.253.08:17:38.78#ibcon#end of sib2, iclass 29, count 2 2006.253.08:17:38.78#ibcon#*after write, iclass 29, count 2 2006.253.08:17:38.78#ibcon#*before return 0, iclass 29, count 2 2006.253.08:17:38.78#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.253.08:17:38.78#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.253.08:17:38.78#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.253.08:17:38.78#ibcon#ireg 7 cls_cnt 0 2006.253.08:17:38.78#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.253.08:17:38.90#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.253.08:17:38.90#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.253.08:17:38.90#ibcon#enter wrdev, iclass 29, count 0 2006.253.08:17:38.90#ibcon#first serial, iclass 29, count 0 2006.253.08:17:38.90#ibcon#enter sib2, iclass 29, count 0 2006.253.08:17:38.90#ibcon#flushed, iclass 29, count 0 2006.253.08:17:38.90#ibcon#about to write, iclass 29, count 0 2006.253.08:17:38.90#ibcon#wrote, iclass 29, count 0 2006.253.08:17:38.90#ibcon#about to read 3, iclass 29, count 0 2006.253.08:17:38.92#ibcon#read 3, iclass 29, count 0 2006.253.08:17:38.92#ibcon#about to read 4, iclass 29, count 0 2006.253.08:17:38.92#ibcon#read 4, iclass 29, count 0 2006.253.08:17:38.92#ibcon#about to read 5, iclass 29, count 0 2006.253.08:17:38.92#ibcon#read 5, iclass 29, count 0 2006.253.08:17:38.92#ibcon#about to read 6, iclass 29, count 0 2006.253.08:17:38.92#ibcon#read 6, iclass 29, count 0 2006.253.08:17:38.92#ibcon#end of sib2, iclass 29, count 0 2006.253.08:17:38.92#ibcon#*mode == 0, iclass 29, count 0 2006.253.08:17:38.92#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.253.08:17:38.92#ibcon#[25=USB\r\n] 2006.253.08:17:38.92#ibcon#*before write, iclass 29, count 0 2006.253.08:17:38.92#ibcon#enter sib2, iclass 29, count 0 2006.253.08:17:38.92#ibcon#flushed, iclass 29, count 0 2006.253.08:17:38.92#ibcon#about to write, iclass 29, count 0 2006.253.08:17:38.92#ibcon#wrote, iclass 29, count 0 2006.253.08:17:38.92#ibcon#about to read 3, iclass 29, count 0 2006.253.08:17:38.95#ibcon#read 3, iclass 29, count 0 2006.253.08:17:38.95#ibcon#about to read 4, iclass 29, count 0 2006.253.08:17:38.95#ibcon#read 4, iclass 29, count 0 2006.253.08:17:38.95#ibcon#about to read 5, iclass 29, count 0 2006.253.08:17:38.95#ibcon#read 5, iclass 29, count 0 2006.253.08:17:38.95#ibcon#about to read 6, iclass 29, count 0 2006.253.08:17:38.95#ibcon#read 6, iclass 29, count 0 2006.253.08:17:38.95#ibcon#end of sib2, iclass 29, count 0 2006.253.08:17:38.95#ibcon#*after write, iclass 29, count 0 2006.253.08:17:38.95#ibcon#*before return 0, iclass 29, count 0 2006.253.08:17:38.95#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.253.08:17:38.95#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.253.08:17:38.95#ibcon#about to clear, iclass 29 cls_cnt 0 2006.253.08:17:38.95#ibcon#cleared, iclass 29 cls_cnt 0 2006.253.08:17:38.95$vc4f8/valo=4,832.99 2006.253.08:17:38.95#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.253.08:17:38.95#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.253.08:17:38.95#ibcon#ireg 17 cls_cnt 0 2006.253.08:17:38.95#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.253.08:17:38.95#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.253.08:17:38.95#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.253.08:17:38.95#ibcon#enter wrdev, iclass 31, count 0 2006.253.08:17:38.95#ibcon#first serial, iclass 31, count 0 2006.253.08:17:38.95#ibcon#enter sib2, iclass 31, count 0 2006.253.08:17:38.95#ibcon#flushed, iclass 31, count 0 2006.253.08:17:38.95#ibcon#about to write, iclass 31, count 0 2006.253.08:17:38.95#ibcon#wrote, iclass 31, count 0 2006.253.08:17:38.95#ibcon#about to read 3, iclass 31, count 0 2006.253.08:17:38.97#ibcon#read 3, iclass 31, count 0 2006.253.08:17:38.97#ibcon#about to read 4, iclass 31, count 0 2006.253.08:17:38.97#ibcon#read 4, iclass 31, count 0 2006.253.08:17:38.97#ibcon#about to read 5, iclass 31, count 0 2006.253.08:17:38.97#ibcon#read 5, iclass 31, count 0 2006.253.08:17:38.97#ibcon#about to read 6, iclass 31, count 0 2006.253.08:17:38.97#ibcon#read 6, iclass 31, count 0 2006.253.08:17:38.97#ibcon#end of sib2, iclass 31, count 0 2006.253.08:17:38.97#ibcon#*mode == 0, iclass 31, count 0 2006.253.08:17:38.97#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.253.08:17:38.97#ibcon#[26=FRQ=04,832.99\r\n] 2006.253.08:17:38.97#ibcon#*before write, iclass 31, count 0 2006.253.08:17:38.97#ibcon#enter sib2, iclass 31, count 0 2006.253.08:17:38.97#ibcon#flushed, iclass 31, count 0 2006.253.08:17:38.97#ibcon#about to write, iclass 31, count 0 2006.253.08:17:38.97#ibcon#wrote, iclass 31, count 0 2006.253.08:17:38.97#ibcon#about to read 3, iclass 31, count 0 2006.253.08:17:39.02#ibcon#read 3, iclass 31, count 0 2006.253.08:17:39.02#ibcon#about to read 4, iclass 31, count 0 2006.253.08:17:39.02#ibcon#read 4, iclass 31, count 0 2006.253.08:17:39.02#ibcon#about to read 5, iclass 31, count 0 2006.253.08:17:39.02#ibcon#read 5, iclass 31, count 0 2006.253.08:17:39.02#ibcon#about to read 6, iclass 31, count 0 2006.253.08:17:39.02#ibcon#read 6, iclass 31, count 0 2006.253.08:17:39.02#ibcon#end of sib2, iclass 31, count 0 2006.253.08:17:39.02#ibcon#*after write, iclass 31, count 0 2006.253.08:17:39.02#ibcon#*before return 0, iclass 31, count 0 2006.253.08:17:39.02#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.253.08:17:39.02#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.253.08:17:39.02#ibcon#about to clear, iclass 31 cls_cnt 0 2006.253.08:17:39.02#ibcon#cleared, iclass 31 cls_cnt 0 2006.253.08:17:39.02$vc4f8/va=4,7 2006.253.08:17:39.02#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.253.08:17:39.02#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.253.08:17:39.02#ibcon#ireg 11 cls_cnt 2 2006.253.08:17:39.02#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.253.08:17:39.07#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.253.08:17:39.07#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.253.08:17:39.07#ibcon#enter wrdev, iclass 33, count 2 2006.253.08:17:39.07#ibcon#first serial, iclass 33, count 2 2006.253.08:17:39.07#ibcon#enter sib2, iclass 33, count 2 2006.253.08:17:39.07#ibcon#flushed, iclass 33, count 2 2006.253.08:17:39.07#ibcon#about to write, iclass 33, count 2 2006.253.08:17:39.07#ibcon#wrote, iclass 33, count 2 2006.253.08:17:39.07#ibcon#about to read 3, iclass 33, count 2 2006.253.08:17:39.09#ibcon#read 3, iclass 33, count 2 2006.253.08:17:39.09#ibcon#about to read 4, iclass 33, count 2 2006.253.08:17:39.09#ibcon#read 4, iclass 33, count 2 2006.253.08:17:39.09#ibcon#about to read 5, iclass 33, count 2 2006.253.08:17:39.09#ibcon#read 5, iclass 33, count 2 2006.253.08:17:39.09#ibcon#about to read 6, iclass 33, count 2 2006.253.08:17:39.09#ibcon#read 6, iclass 33, count 2 2006.253.08:17:39.09#ibcon#end of sib2, iclass 33, count 2 2006.253.08:17:39.09#ibcon#*mode == 0, iclass 33, count 2 2006.253.08:17:39.09#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.253.08:17:39.09#ibcon#[25=AT04-07\r\n] 2006.253.08:17:39.09#ibcon#*before write, iclass 33, count 2 2006.253.08:17:39.09#ibcon#enter sib2, iclass 33, count 2 2006.253.08:17:39.09#ibcon#flushed, iclass 33, count 2 2006.253.08:17:39.09#ibcon#about to write, iclass 33, count 2 2006.253.08:17:39.09#ibcon#wrote, iclass 33, count 2 2006.253.08:17:39.09#ibcon#about to read 3, iclass 33, count 2 2006.253.08:17:39.12#abcon#<5=/08 1.0 2.5 30.86 751006.6\r\n> 2006.253.08:17:39.12#ibcon#read 3, iclass 33, count 2 2006.253.08:17:39.12#ibcon#about to read 4, iclass 33, count 2 2006.253.08:17:39.12#ibcon#read 4, iclass 33, count 2 2006.253.08:17:39.12#ibcon#about to read 5, iclass 33, count 2 2006.253.08:17:39.12#ibcon#read 5, iclass 33, count 2 2006.253.08:17:39.12#ibcon#about to read 6, iclass 33, count 2 2006.253.08:17:39.12#ibcon#read 6, iclass 33, count 2 2006.253.08:17:39.12#ibcon#end of sib2, iclass 33, count 2 2006.253.08:17:39.12#ibcon#*after write, iclass 33, count 2 2006.253.08:17:39.12#ibcon#*before return 0, iclass 33, count 2 2006.253.08:17:39.12#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.253.08:17:39.12#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.253.08:17:39.12#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.253.08:17:39.12#ibcon#ireg 7 cls_cnt 0 2006.253.08:17:39.12#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.253.08:17:39.14#abcon#{5=INTERFACE CLEAR} 2006.253.08:17:39.20#abcon#[5=S1D000X0/0*\r\n] 2006.253.08:17:39.24#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.253.08:17:39.24#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.253.08:17:39.24#ibcon#enter wrdev, iclass 33, count 0 2006.253.08:17:39.24#ibcon#first serial, iclass 33, count 0 2006.253.08:17:39.24#ibcon#enter sib2, iclass 33, count 0 2006.253.08:17:39.24#ibcon#flushed, iclass 33, count 0 2006.253.08:17:39.24#ibcon#about to write, iclass 33, count 0 2006.253.08:17:39.24#ibcon#wrote, iclass 33, count 0 2006.253.08:17:39.24#ibcon#about to read 3, iclass 33, count 0 2006.253.08:17:39.26#ibcon#read 3, iclass 33, count 0 2006.253.08:17:39.26#ibcon#about to read 4, iclass 33, count 0 2006.253.08:17:39.26#ibcon#read 4, iclass 33, count 0 2006.253.08:17:39.26#ibcon#about to read 5, iclass 33, count 0 2006.253.08:17:39.26#ibcon#read 5, iclass 33, count 0 2006.253.08:17:39.26#ibcon#about to read 6, iclass 33, count 0 2006.253.08:17:39.26#ibcon#read 6, iclass 33, count 0 2006.253.08:17:39.26#ibcon#end of sib2, iclass 33, count 0 2006.253.08:17:39.26#ibcon#*mode == 0, iclass 33, count 0 2006.253.08:17:39.26#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.253.08:17:39.26#ibcon#[25=USB\r\n] 2006.253.08:17:39.26#ibcon#*before write, iclass 33, count 0 2006.253.08:17:39.26#ibcon#enter sib2, iclass 33, count 0 2006.253.08:17:39.26#ibcon#flushed, iclass 33, count 0 2006.253.08:17:39.26#ibcon#about to write, iclass 33, count 0 2006.253.08:17:39.26#ibcon#wrote, iclass 33, count 0 2006.253.08:17:39.26#ibcon#about to read 3, iclass 33, count 0 2006.253.08:17:39.29#ibcon#read 3, iclass 33, count 0 2006.253.08:17:39.29#ibcon#about to read 4, iclass 33, count 0 2006.253.08:17:39.29#ibcon#read 4, iclass 33, count 0 2006.253.08:17:39.29#ibcon#about to read 5, iclass 33, count 0 2006.253.08:17:39.29#ibcon#read 5, iclass 33, count 0 2006.253.08:17:39.29#ibcon#about to read 6, iclass 33, count 0 2006.253.08:17:39.29#ibcon#read 6, iclass 33, count 0 2006.253.08:17:39.29#ibcon#end of sib2, iclass 33, count 0 2006.253.08:17:39.29#ibcon#*after write, iclass 33, count 0 2006.253.08:17:39.29#ibcon#*before return 0, iclass 33, count 0 2006.253.08:17:39.29#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.253.08:17:39.29#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.253.08:17:39.29#ibcon#about to clear, iclass 33 cls_cnt 0 2006.253.08:17:39.29#ibcon#cleared, iclass 33 cls_cnt 0 2006.253.08:17:39.29$vc4f8/valo=5,652.99 2006.253.08:17:39.29#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.253.08:17:39.29#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.253.08:17:39.29#ibcon#ireg 17 cls_cnt 0 2006.253.08:17:39.29#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.253.08:17:39.29#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.253.08:17:39.29#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.253.08:17:39.29#ibcon#enter wrdev, iclass 39, count 0 2006.253.08:17:39.29#ibcon#first serial, iclass 39, count 0 2006.253.08:17:39.29#ibcon#enter sib2, iclass 39, count 0 2006.253.08:17:39.29#ibcon#flushed, iclass 39, count 0 2006.253.08:17:39.29#ibcon#about to write, iclass 39, count 0 2006.253.08:17:39.29#ibcon#wrote, iclass 39, count 0 2006.253.08:17:39.29#ibcon#about to read 3, iclass 39, count 0 2006.253.08:17:39.31#ibcon#read 3, iclass 39, count 0 2006.253.08:17:39.31#ibcon#about to read 4, iclass 39, count 0 2006.253.08:17:39.31#ibcon#read 4, iclass 39, count 0 2006.253.08:17:39.31#ibcon#about to read 5, iclass 39, count 0 2006.253.08:17:39.31#ibcon#read 5, iclass 39, count 0 2006.253.08:17:39.31#ibcon#about to read 6, iclass 39, count 0 2006.253.08:17:39.31#ibcon#read 6, iclass 39, count 0 2006.253.08:17:39.31#ibcon#end of sib2, iclass 39, count 0 2006.253.08:17:39.31#ibcon#*mode == 0, iclass 39, count 0 2006.253.08:17:39.31#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.253.08:17:39.31#ibcon#[26=FRQ=05,652.99\r\n] 2006.253.08:17:39.31#ibcon#*before write, iclass 39, count 0 2006.253.08:17:39.31#ibcon#enter sib2, iclass 39, count 0 2006.253.08:17:39.31#ibcon#flushed, iclass 39, count 0 2006.253.08:17:39.31#ibcon#about to write, iclass 39, count 0 2006.253.08:17:39.31#ibcon#wrote, iclass 39, count 0 2006.253.08:17:39.31#ibcon#about to read 3, iclass 39, count 0 2006.253.08:17:39.35#ibcon#read 3, iclass 39, count 0 2006.253.08:17:39.35#ibcon#about to read 4, iclass 39, count 0 2006.253.08:17:39.35#ibcon#read 4, iclass 39, count 0 2006.253.08:17:39.35#ibcon#about to read 5, iclass 39, count 0 2006.253.08:17:39.35#ibcon#read 5, iclass 39, count 0 2006.253.08:17:39.35#ibcon#about to read 6, iclass 39, count 0 2006.253.08:17:39.35#ibcon#read 6, iclass 39, count 0 2006.253.08:17:39.35#ibcon#end of sib2, iclass 39, count 0 2006.253.08:17:39.35#ibcon#*after write, iclass 39, count 0 2006.253.08:17:39.35#ibcon#*before return 0, iclass 39, count 0 2006.253.08:17:39.35#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.253.08:17:39.35#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.253.08:17:39.35#ibcon#about to clear, iclass 39 cls_cnt 0 2006.253.08:17:39.35#ibcon#cleared, iclass 39 cls_cnt 0 2006.253.08:17:39.35$vc4f8/va=5,7 2006.253.08:17:39.35#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.253.08:17:39.35#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.253.08:17:39.35#ibcon#ireg 11 cls_cnt 2 2006.253.08:17:39.35#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.253.08:17:39.41#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.253.08:17:39.41#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.253.08:17:39.41#ibcon#enter wrdev, iclass 3, count 2 2006.253.08:17:39.41#ibcon#first serial, iclass 3, count 2 2006.253.08:17:39.41#ibcon#enter sib2, iclass 3, count 2 2006.253.08:17:39.41#ibcon#flushed, iclass 3, count 2 2006.253.08:17:39.41#ibcon#about to write, iclass 3, count 2 2006.253.08:17:39.41#ibcon#wrote, iclass 3, count 2 2006.253.08:17:39.41#ibcon#about to read 3, iclass 3, count 2 2006.253.08:17:39.43#ibcon#read 3, iclass 3, count 2 2006.253.08:17:39.43#ibcon#about to read 4, iclass 3, count 2 2006.253.08:17:39.43#ibcon#read 4, iclass 3, count 2 2006.253.08:17:39.43#ibcon#about to read 5, iclass 3, count 2 2006.253.08:17:39.43#ibcon#read 5, iclass 3, count 2 2006.253.08:17:39.43#ibcon#about to read 6, iclass 3, count 2 2006.253.08:17:39.43#ibcon#read 6, iclass 3, count 2 2006.253.08:17:39.43#ibcon#end of sib2, iclass 3, count 2 2006.253.08:17:39.43#ibcon#*mode == 0, iclass 3, count 2 2006.253.08:17:39.43#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.253.08:17:39.43#ibcon#[25=AT05-07\r\n] 2006.253.08:17:39.43#ibcon#*before write, iclass 3, count 2 2006.253.08:17:39.43#ibcon#enter sib2, iclass 3, count 2 2006.253.08:17:39.43#ibcon#flushed, iclass 3, count 2 2006.253.08:17:39.43#ibcon#about to write, iclass 3, count 2 2006.253.08:17:39.43#ibcon#wrote, iclass 3, count 2 2006.253.08:17:39.43#ibcon#about to read 3, iclass 3, count 2 2006.253.08:17:39.46#ibcon#read 3, iclass 3, count 2 2006.253.08:17:39.46#ibcon#about to read 4, iclass 3, count 2 2006.253.08:17:39.46#ibcon#read 4, iclass 3, count 2 2006.253.08:17:39.46#ibcon#about to read 5, iclass 3, count 2 2006.253.08:17:39.46#ibcon#read 5, iclass 3, count 2 2006.253.08:17:39.46#ibcon#about to read 6, iclass 3, count 2 2006.253.08:17:39.46#ibcon#read 6, iclass 3, count 2 2006.253.08:17:39.46#ibcon#end of sib2, iclass 3, count 2 2006.253.08:17:39.46#ibcon#*after write, iclass 3, count 2 2006.253.08:17:39.46#ibcon#*before return 0, iclass 3, count 2 2006.253.08:17:39.46#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.253.08:17:39.46#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.253.08:17:39.46#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.253.08:17:39.46#ibcon#ireg 7 cls_cnt 0 2006.253.08:17:39.46#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.253.08:17:39.58#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.253.08:17:39.58#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.253.08:17:39.58#ibcon#enter wrdev, iclass 3, count 0 2006.253.08:17:39.58#ibcon#first serial, iclass 3, count 0 2006.253.08:17:39.58#ibcon#enter sib2, iclass 3, count 0 2006.253.08:17:39.58#ibcon#flushed, iclass 3, count 0 2006.253.08:17:39.58#ibcon#about to write, iclass 3, count 0 2006.253.08:17:39.58#ibcon#wrote, iclass 3, count 0 2006.253.08:17:39.58#ibcon#about to read 3, iclass 3, count 0 2006.253.08:17:39.60#ibcon#read 3, iclass 3, count 0 2006.253.08:17:39.60#ibcon#about to read 4, iclass 3, count 0 2006.253.08:17:39.60#ibcon#read 4, iclass 3, count 0 2006.253.08:17:39.60#ibcon#about to read 5, iclass 3, count 0 2006.253.08:17:39.60#ibcon#read 5, iclass 3, count 0 2006.253.08:17:39.60#ibcon#about to read 6, iclass 3, count 0 2006.253.08:17:39.60#ibcon#read 6, iclass 3, count 0 2006.253.08:17:39.60#ibcon#end of sib2, iclass 3, count 0 2006.253.08:17:39.60#ibcon#*mode == 0, iclass 3, count 0 2006.253.08:17:39.60#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.253.08:17:39.60#ibcon#[25=USB\r\n] 2006.253.08:17:39.60#ibcon#*before write, iclass 3, count 0 2006.253.08:17:39.60#ibcon#enter sib2, iclass 3, count 0 2006.253.08:17:39.60#ibcon#flushed, iclass 3, count 0 2006.253.08:17:39.60#ibcon#about to write, iclass 3, count 0 2006.253.08:17:39.60#ibcon#wrote, iclass 3, count 0 2006.253.08:17:39.60#ibcon#about to read 3, iclass 3, count 0 2006.253.08:17:39.63#ibcon#read 3, iclass 3, count 0 2006.253.08:17:39.63#ibcon#about to read 4, iclass 3, count 0 2006.253.08:17:39.63#ibcon#read 4, iclass 3, count 0 2006.253.08:17:39.63#ibcon#about to read 5, iclass 3, count 0 2006.253.08:17:39.63#ibcon#read 5, iclass 3, count 0 2006.253.08:17:39.63#ibcon#about to read 6, iclass 3, count 0 2006.253.08:17:39.63#ibcon#read 6, iclass 3, count 0 2006.253.08:17:39.63#ibcon#end of sib2, iclass 3, count 0 2006.253.08:17:39.63#ibcon#*after write, iclass 3, count 0 2006.253.08:17:39.63#ibcon#*before return 0, iclass 3, count 0 2006.253.08:17:39.63#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.253.08:17:39.63#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.253.08:17:39.63#ibcon#about to clear, iclass 3 cls_cnt 0 2006.253.08:17:39.63#ibcon#cleared, iclass 3 cls_cnt 0 2006.253.08:17:39.63$vc4f8/valo=6,772.99 2006.253.08:17:39.63#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.253.08:17:39.63#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.253.08:17:39.63#ibcon#ireg 17 cls_cnt 0 2006.253.08:17:39.63#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.253.08:17:39.63#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.253.08:17:39.63#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.253.08:17:39.63#ibcon#enter wrdev, iclass 5, count 0 2006.253.08:17:39.63#ibcon#first serial, iclass 5, count 0 2006.253.08:17:39.63#ibcon#enter sib2, iclass 5, count 0 2006.253.08:17:39.63#ibcon#flushed, iclass 5, count 0 2006.253.08:17:39.63#ibcon#about to write, iclass 5, count 0 2006.253.08:17:39.63#ibcon#wrote, iclass 5, count 0 2006.253.08:17:39.63#ibcon#about to read 3, iclass 5, count 0 2006.253.08:17:39.65#ibcon#read 3, iclass 5, count 0 2006.253.08:17:39.65#ibcon#about to read 4, iclass 5, count 0 2006.253.08:17:39.65#ibcon#read 4, iclass 5, count 0 2006.253.08:17:39.65#ibcon#about to read 5, iclass 5, count 0 2006.253.08:17:39.65#ibcon#read 5, iclass 5, count 0 2006.253.08:17:39.65#ibcon#about to read 6, iclass 5, count 0 2006.253.08:17:39.65#ibcon#read 6, iclass 5, count 0 2006.253.08:17:39.65#ibcon#end of sib2, iclass 5, count 0 2006.253.08:17:39.65#ibcon#*mode == 0, iclass 5, count 0 2006.253.08:17:39.65#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.253.08:17:39.65#ibcon#[26=FRQ=06,772.99\r\n] 2006.253.08:17:39.65#ibcon#*before write, iclass 5, count 0 2006.253.08:17:39.65#ibcon#enter sib2, iclass 5, count 0 2006.253.08:17:39.65#ibcon#flushed, iclass 5, count 0 2006.253.08:17:39.65#ibcon#about to write, iclass 5, count 0 2006.253.08:17:39.65#ibcon#wrote, iclass 5, count 0 2006.253.08:17:39.65#ibcon#about to read 3, iclass 5, count 0 2006.253.08:17:39.70#ibcon#read 3, iclass 5, count 0 2006.253.08:17:39.70#ibcon#about to read 4, iclass 5, count 0 2006.253.08:17:39.70#ibcon#read 4, iclass 5, count 0 2006.253.08:17:39.70#ibcon#about to read 5, iclass 5, count 0 2006.253.08:17:39.70#ibcon#read 5, iclass 5, count 0 2006.253.08:17:39.70#ibcon#about to read 6, iclass 5, count 0 2006.253.08:17:39.70#ibcon#read 6, iclass 5, count 0 2006.253.08:17:39.70#ibcon#end of sib2, iclass 5, count 0 2006.253.08:17:39.70#ibcon#*after write, iclass 5, count 0 2006.253.08:17:39.70#ibcon#*before return 0, iclass 5, count 0 2006.253.08:17:39.70#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.253.08:17:39.70#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.253.08:17:39.70#ibcon#about to clear, iclass 5 cls_cnt 0 2006.253.08:17:39.70#ibcon#cleared, iclass 5 cls_cnt 0 2006.253.08:17:39.70$vc4f8/va=6,7 2006.253.08:17:39.70#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.253.08:17:39.70#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.253.08:17:39.70#ibcon#ireg 11 cls_cnt 2 2006.253.08:17:39.70#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.253.08:17:39.75#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.253.08:17:39.75#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.253.08:17:39.75#ibcon#enter wrdev, iclass 7, count 2 2006.253.08:17:39.75#ibcon#first serial, iclass 7, count 2 2006.253.08:17:39.75#ibcon#enter sib2, iclass 7, count 2 2006.253.08:17:39.75#ibcon#flushed, iclass 7, count 2 2006.253.08:17:39.75#ibcon#about to write, iclass 7, count 2 2006.253.08:17:39.75#ibcon#wrote, iclass 7, count 2 2006.253.08:17:39.75#ibcon#about to read 3, iclass 7, count 2 2006.253.08:17:39.77#ibcon#read 3, iclass 7, count 2 2006.253.08:17:39.77#ibcon#about to read 4, iclass 7, count 2 2006.253.08:17:39.77#ibcon#read 4, iclass 7, count 2 2006.253.08:17:39.77#ibcon#about to read 5, iclass 7, count 2 2006.253.08:17:39.77#ibcon#read 5, iclass 7, count 2 2006.253.08:17:39.77#ibcon#about to read 6, iclass 7, count 2 2006.253.08:17:39.77#ibcon#read 6, iclass 7, count 2 2006.253.08:17:39.77#ibcon#end of sib2, iclass 7, count 2 2006.253.08:17:39.77#ibcon#*mode == 0, iclass 7, count 2 2006.253.08:17:39.77#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.253.08:17:39.77#ibcon#[25=AT06-07\r\n] 2006.253.08:17:39.77#ibcon#*before write, iclass 7, count 2 2006.253.08:17:39.77#ibcon#enter sib2, iclass 7, count 2 2006.253.08:17:39.77#ibcon#flushed, iclass 7, count 2 2006.253.08:17:39.77#ibcon#about to write, iclass 7, count 2 2006.253.08:17:39.77#ibcon#wrote, iclass 7, count 2 2006.253.08:17:39.77#ibcon#about to read 3, iclass 7, count 2 2006.253.08:17:39.80#ibcon#read 3, iclass 7, count 2 2006.253.08:17:39.80#ibcon#about to read 4, iclass 7, count 2 2006.253.08:17:39.80#ibcon#read 4, iclass 7, count 2 2006.253.08:17:39.80#ibcon#about to read 5, iclass 7, count 2 2006.253.08:17:39.80#ibcon#read 5, iclass 7, count 2 2006.253.08:17:39.80#ibcon#about to read 6, iclass 7, count 2 2006.253.08:17:39.80#ibcon#read 6, iclass 7, count 2 2006.253.08:17:39.80#ibcon#end of sib2, iclass 7, count 2 2006.253.08:17:39.80#ibcon#*after write, iclass 7, count 2 2006.253.08:17:39.80#ibcon#*before return 0, iclass 7, count 2 2006.253.08:17:39.80#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.253.08:17:39.80#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.253.08:17:39.80#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.253.08:17:39.80#ibcon#ireg 7 cls_cnt 0 2006.253.08:17:39.80#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.253.08:17:39.92#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.253.08:17:39.92#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.253.08:17:39.92#ibcon#enter wrdev, iclass 7, count 0 2006.253.08:17:39.92#ibcon#first serial, iclass 7, count 0 2006.253.08:17:39.92#ibcon#enter sib2, iclass 7, count 0 2006.253.08:17:39.92#ibcon#flushed, iclass 7, count 0 2006.253.08:17:39.92#ibcon#about to write, iclass 7, count 0 2006.253.08:17:39.92#ibcon#wrote, iclass 7, count 0 2006.253.08:17:39.92#ibcon#about to read 3, iclass 7, count 0 2006.253.08:17:39.94#ibcon#read 3, iclass 7, count 0 2006.253.08:17:39.94#ibcon#about to read 4, iclass 7, count 0 2006.253.08:17:39.94#ibcon#read 4, iclass 7, count 0 2006.253.08:17:39.94#ibcon#about to read 5, iclass 7, count 0 2006.253.08:17:39.94#ibcon#read 5, iclass 7, count 0 2006.253.08:17:39.94#ibcon#about to read 6, iclass 7, count 0 2006.253.08:17:39.94#ibcon#read 6, iclass 7, count 0 2006.253.08:17:39.94#ibcon#end of sib2, iclass 7, count 0 2006.253.08:17:39.94#ibcon#*mode == 0, iclass 7, count 0 2006.253.08:17:39.94#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.253.08:17:39.94#ibcon#[25=USB\r\n] 2006.253.08:17:39.94#ibcon#*before write, iclass 7, count 0 2006.253.08:17:39.94#ibcon#enter sib2, iclass 7, count 0 2006.253.08:17:39.94#ibcon#flushed, iclass 7, count 0 2006.253.08:17:39.94#ibcon#about to write, iclass 7, count 0 2006.253.08:17:39.94#ibcon#wrote, iclass 7, count 0 2006.253.08:17:39.94#ibcon#about to read 3, iclass 7, count 0 2006.253.08:17:39.97#ibcon#read 3, iclass 7, count 0 2006.253.08:17:39.97#ibcon#about to read 4, iclass 7, count 0 2006.253.08:17:39.97#ibcon#read 4, iclass 7, count 0 2006.253.08:17:39.97#ibcon#about to read 5, iclass 7, count 0 2006.253.08:17:39.97#ibcon#read 5, iclass 7, count 0 2006.253.08:17:39.97#ibcon#about to read 6, iclass 7, count 0 2006.253.08:17:39.97#ibcon#read 6, iclass 7, count 0 2006.253.08:17:39.97#ibcon#end of sib2, iclass 7, count 0 2006.253.08:17:39.97#ibcon#*after write, iclass 7, count 0 2006.253.08:17:39.97#ibcon#*before return 0, iclass 7, count 0 2006.253.08:17:39.97#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.253.08:17:39.97#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.253.08:17:39.97#ibcon#about to clear, iclass 7 cls_cnt 0 2006.253.08:17:39.97#ibcon#cleared, iclass 7 cls_cnt 0 2006.253.08:17:39.97$vc4f8/valo=7,832.99 2006.253.08:17:39.97#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.253.08:17:39.97#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.253.08:17:39.97#ibcon#ireg 17 cls_cnt 0 2006.253.08:17:39.97#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.253.08:17:39.97#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.253.08:17:39.97#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.253.08:17:39.97#ibcon#enter wrdev, iclass 11, count 0 2006.253.08:17:39.97#ibcon#first serial, iclass 11, count 0 2006.253.08:17:39.97#ibcon#enter sib2, iclass 11, count 0 2006.253.08:17:39.97#ibcon#flushed, iclass 11, count 0 2006.253.08:17:39.97#ibcon#about to write, iclass 11, count 0 2006.253.08:17:39.97#ibcon#wrote, iclass 11, count 0 2006.253.08:17:39.97#ibcon#about to read 3, iclass 11, count 0 2006.253.08:17:39.99#ibcon#read 3, iclass 11, count 0 2006.253.08:17:39.99#ibcon#about to read 4, iclass 11, count 0 2006.253.08:17:39.99#ibcon#read 4, iclass 11, count 0 2006.253.08:17:39.99#ibcon#about to read 5, iclass 11, count 0 2006.253.08:17:39.99#ibcon#read 5, iclass 11, count 0 2006.253.08:17:39.99#ibcon#about to read 6, iclass 11, count 0 2006.253.08:17:39.99#ibcon#read 6, iclass 11, count 0 2006.253.08:17:39.99#ibcon#end of sib2, iclass 11, count 0 2006.253.08:17:39.99#ibcon#*mode == 0, iclass 11, count 0 2006.253.08:17:39.99#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.253.08:17:39.99#ibcon#[26=FRQ=07,832.99\r\n] 2006.253.08:17:39.99#ibcon#*before write, iclass 11, count 0 2006.253.08:17:39.99#ibcon#enter sib2, iclass 11, count 0 2006.253.08:17:39.99#ibcon#flushed, iclass 11, count 0 2006.253.08:17:39.99#ibcon#about to write, iclass 11, count 0 2006.253.08:17:39.99#ibcon#wrote, iclass 11, count 0 2006.253.08:17:39.99#ibcon#about to read 3, iclass 11, count 0 2006.253.08:17:40.03#ibcon#read 3, iclass 11, count 0 2006.253.08:17:40.03#ibcon#about to read 4, iclass 11, count 0 2006.253.08:17:40.03#ibcon#read 4, iclass 11, count 0 2006.253.08:17:40.03#ibcon#about to read 5, iclass 11, count 0 2006.253.08:17:40.03#ibcon#read 5, iclass 11, count 0 2006.253.08:17:40.03#ibcon#about to read 6, iclass 11, count 0 2006.253.08:17:40.03#ibcon#read 6, iclass 11, count 0 2006.253.08:17:40.03#ibcon#end of sib2, iclass 11, count 0 2006.253.08:17:40.03#ibcon#*after write, iclass 11, count 0 2006.253.08:17:40.03#ibcon#*before return 0, iclass 11, count 0 2006.253.08:17:40.03#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.253.08:17:40.03#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.253.08:17:40.03#ibcon#about to clear, iclass 11 cls_cnt 0 2006.253.08:17:40.03#ibcon#cleared, iclass 11 cls_cnt 0 2006.253.08:17:40.03$vc4f8/va=7,7 2006.253.08:17:40.03#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.253.08:17:40.03#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.253.08:17:40.03#ibcon#ireg 11 cls_cnt 2 2006.253.08:17:40.03#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.253.08:17:40.09#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.253.08:17:40.09#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.253.08:17:40.09#ibcon#enter wrdev, iclass 13, count 2 2006.253.08:17:40.09#ibcon#first serial, iclass 13, count 2 2006.253.08:17:40.09#ibcon#enter sib2, iclass 13, count 2 2006.253.08:17:40.09#ibcon#flushed, iclass 13, count 2 2006.253.08:17:40.09#ibcon#about to write, iclass 13, count 2 2006.253.08:17:40.09#ibcon#wrote, iclass 13, count 2 2006.253.08:17:40.09#ibcon#about to read 3, iclass 13, count 2 2006.253.08:17:40.11#ibcon#read 3, iclass 13, count 2 2006.253.08:17:40.11#ibcon#about to read 4, iclass 13, count 2 2006.253.08:17:40.11#ibcon#read 4, iclass 13, count 2 2006.253.08:17:40.11#ibcon#about to read 5, iclass 13, count 2 2006.253.08:17:40.11#ibcon#read 5, iclass 13, count 2 2006.253.08:17:40.11#ibcon#about to read 6, iclass 13, count 2 2006.253.08:17:40.11#ibcon#read 6, iclass 13, count 2 2006.253.08:17:40.11#ibcon#end of sib2, iclass 13, count 2 2006.253.08:17:40.11#ibcon#*mode == 0, iclass 13, count 2 2006.253.08:17:40.11#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.253.08:17:40.11#ibcon#[25=AT07-07\r\n] 2006.253.08:17:40.11#ibcon#*before write, iclass 13, count 2 2006.253.08:17:40.11#ibcon#enter sib2, iclass 13, count 2 2006.253.08:17:40.11#ibcon#flushed, iclass 13, count 2 2006.253.08:17:40.11#ibcon#about to write, iclass 13, count 2 2006.253.08:17:40.11#ibcon#wrote, iclass 13, count 2 2006.253.08:17:40.11#ibcon#about to read 3, iclass 13, count 2 2006.253.08:17:40.14#ibcon#read 3, iclass 13, count 2 2006.253.08:17:40.14#ibcon#about to read 4, iclass 13, count 2 2006.253.08:17:40.14#ibcon#read 4, iclass 13, count 2 2006.253.08:17:40.14#ibcon#about to read 5, iclass 13, count 2 2006.253.08:17:40.14#ibcon#read 5, iclass 13, count 2 2006.253.08:17:40.14#ibcon#about to read 6, iclass 13, count 2 2006.253.08:17:40.14#ibcon#read 6, iclass 13, count 2 2006.253.08:17:40.14#ibcon#end of sib2, iclass 13, count 2 2006.253.08:17:40.14#ibcon#*after write, iclass 13, count 2 2006.253.08:17:40.14#ibcon#*before return 0, iclass 13, count 2 2006.253.08:17:40.14#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.253.08:17:40.14#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.253.08:17:40.14#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.253.08:17:40.14#ibcon#ireg 7 cls_cnt 0 2006.253.08:17:40.14#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.253.08:17:40.26#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.253.08:17:40.26#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.253.08:17:40.26#ibcon#enter wrdev, iclass 13, count 0 2006.253.08:17:40.26#ibcon#first serial, iclass 13, count 0 2006.253.08:17:40.26#ibcon#enter sib2, iclass 13, count 0 2006.253.08:17:40.26#ibcon#flushed, iclass 13, count 0 2006.253.08:17:40.26#ibcon#about to write, iclass 13, count 0 2006.253.08:17:40.26#ibcon#wrote, iclass 13, count 0 2006.253.08:17:40.26#ibcon#about to read 3, iclass 13, count 0 2006.253.08:17:40.28#ibcon#read 3, iclass 13, count 0 2006.253.08:17:40.28#ibcon#about to read 4, iclass 13, count 0 2006.253.08:17:40.28#ibcon#read 4, iclass 13, count 0 2006.253.08:17:40.28#ibcon#about to read 5, iclass 13, count 0 2006.253.08:17:40.28#ibcon#read 5, iclass 13, count 0 2006.253.08:17:40.28#ibcon#about to read 6, iclass 13, count 0 2006.253.08:17:40.28#ibcon#read 6, iclass 13, count 0 2006.253.08:17:40.28#ibcon#end of sib2, iclass 13, count 0 2006.253.08:17:40.28#ibcon#*mode == 0, iclass 13, count 0 2006.253.08:17:40.28#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.253.08:17:40.28#ibcon#[25=USB\r\n] 2006.253.08:17:40.28#ibcon#*before write, iclass 13, count 0 2006.253.08:17:40.28#ibcon#enter sib2, iclass 13, count 0 2006.253.08:17:40.28#ibcon#flushed, iclass 13, count 0 2006.253.08:17:40.28#ibcon#about to write, iclass 13, count 0 2006.253.08:17:40.28#ibcon#wrote, iclass 13, count 0 2006.253.08:17:40.28#ibcon#about to read 3, iclass 13, count 0 2006.253.08:17:40.31#ibcon#read 3, iclass 13, count 0 2006.253.08:17:40.31#ibcon#about to read 4, iclass 13, count 0 2006.253.08:17:40.31#ibcon#read 4, iclass 13, count 0 2006.253.08:17:40.31#ibcon#about to read 5, iclass 13, count 0 2006.253.08:17:40.31#ibcon#read 5, iclass 13, count 0 2006.253.08:17:40.31#ibcon#about to read 6, iclass 13, count 0 2006.253.08:17:40.31#ibcon#read 6, iclass 13, count 0 2006.253.08:17:40.31#ibcon#end of sib2, iclass 13, count 0 2006.253.08:17:40.31#ibcon#*after write, iclass 13, count 0 2006.253.08:17:40.31#ibcon#*before return 0, iclass 13, count 0 2006.253.08:17:40.31#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.253.08:17:40.31#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.253.08:17:40.31#ibcon#about to clear, iclass 13 cls_cnt 0 2006.253.08:17:40.31#ibcon#cleared, iclass 13 cls_cnt 0 2006.253.08:17:40.31$vc4f8/valo=8,852.99 2006.253.08:17:40.31#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.253.08:17:40.31#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.253.08:17:40.31#ibcon#ireg 17 cls_cnt 0 2006.253.08:17:40.31#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.253.08:17:40.31#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.253.08:17:40.31#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.253.08:17:40.31#ibcon#enter wrdev, iclass 15, count 0 2006.253.08:17:40.31#ibcon#first serial, iclass 15, count 0 2006.253.08:17:40.31#ibcon#enter sib2, iclass 15, count 0 2006.253.08:17:40.31#ibcon#flushed, iclass 15, count 0 2006.253.08:17:40.31#ibcon#about to write, iclass 15, count 0 2006.253.08:17:40.31#ibcon#wrote, iclass 15, count 0 2006.253.08:17:40.31#ibcon#about to read 3, iclass 15, count 0 2006.253.08:17:40.33#ibcon#read 3, iclass 15, count 0 2006.253.08:17:40.33#ibcon#about to read 4, iclass 15, count 0 2006.253.08:17:40.33#ibcon#read 4, iclass 15, count 0 2006.253.08:17:40.33#ibcon#about to read 5, iclass 15, count 0 2006.253.08:17:40.33#ibcon#read 5, iclass 15, count 0 2006.253.08:17:40.33#ibcon#about to read 6, iclass 15, count 0 2006.253.08:17:40.33#ibcon#read 6, iclass 15, count 0 2006.253.08:17:40.33#ibcon#end of sib2, iclass 15, count 0 2006.253.08:17:40.33#ibcon#*mode == 0, iclass 15, count 0 2006.253.08:17:40.33#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.253.08:17:40.33#ibcon#[26=FRQ=08,852.99\r\n] 2006.253.08:17:40.33#ibcon#*before write, iclass 15, count 0 2006.253.08:17:40.33#ibcon#enter sib2, iclass 15, count 0 2006.253.08:17:40.33#ibcon#flushed, iclass 15, count 0 2006.253.08:17:40.33#ibcon#about to write, iclass 15, count 0 2006.253.08:17:40.33#ibcon#wrote, iclass 15, count 0 2006.253.08:17:40.33#ibcon#about to read 3, iclass 15, count 0 2006.253.08:17:40.37#ibcon#read 3, iclass 15, count 0 2006.253.08:17:40.37#ibcon#about to read 4, iclass 15, count 0 2006.253.08:17:40.37#ibcon#read 4, iclass 15, count 0 2006.253.08:17:40.37#ibcon#about to read 5, iclass 15, count 0 2006.253.08:17:40.37#ibcon#read 5, iclass 15, count 0 2006.253.08:17:40.37#ibcon#about to read 6, iclass 15, count 0 2006.253.08:17:40.37#ibcon#read 6, iclass 15, count 0 2006.253.08:17:40.37#ibcon#end of sib2, iclass 15, count 0 2006.253.08:17:40.37#ibcon#*after write, iclass 15, count 0 2006.253.08:17:40.37#ibcon#*before return 0, iclass 15, count 0 2006.253.08:17:40.37#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.253.08:17:40.37#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.253.08:17:40.37#ibcon#about to clear, iclass 15 cls_cnt 0 2006.253.08:17:40.37#ibcon#cleared, iclass 15 cls_cnt 0 2006.253.08:17:40.37$vc4f8/va=8,7 2006.253.08:17:40.37#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.253.08:17:40.37#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.253.08:17:40.37#ibcon#ireg 11 cls_cnt 2 2006.253.08:17:40.37#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.253.08:17:40.43#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.253.08:17:40.43#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.253.08:17:40.43#ibcon#enter wrdev, iclass 17, count 2 2006.253.08:17:40.43#ibcon#first serial, iclass 17, count 2 2006.253.08:17:40.43#ibcon#enter sib2, iclass 17, count 2 2006.253.08:17:40.43#ibcon#flushed, iclass 17, count 2 2006.253.08:17:40.43#ibcon#about to write, iclass 17, count 2 2006.253.08:17:40.43#ibcon#wrote, iclass 17, count 2 2006.253.08:17:40.43#ibcon#about to read 3, iclass 17, count 2 2006.253.08:17:40.45#ibcon#read 3, iclass 17, count 2 2006.253.08:17:40.45#ibcon#about to read 4, iclass 17, count 2 2006.253.08:17:40.45#ibcon#read 4, iclass 17, count 2 2006.253.08:17:40.45#ibcon#about to read 5, iclass 17, count 2 2006.253.08:17:40.45#ibcon#read 5, iclass 17, count 2 2006.253.08:17:40.45#ibcon#about to read 6, iclass 17, count 2 2006.253.08:17:40.45#ibcon#read 6, iclass 17, count 2 2006.253.08:17:40.45#ibcon#end of sib2, iclass 17, count 2 2006.253.08:17:40.45#ibcon#*mode == 0, iclass 17, count 2 2006.253.08:17:40.45#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.253.08:17:40.45#ibcon#[25=AT08-07\r\n] 2006.253.08:17:40.45#ibcon#*before write, iclass 17, count 2 2006.253.08:17:40.45#ibcon#enter sib2, iclass 17, count 2 2006.253.08:17:40.45#ibcon#flushed, iclass 17, count 2 2006.253.08:17:40.45#ibcon#about to write, iclass 17, count 2 2006.253.08:17:40.45#ibcon#wrote, iclass 17, count 2 2006.253.08:17:40.45#ibcon#about to read 3, iclass 17, count 2 2006.253.08:17:40.48#ibcon#read 3, iclass 17, count 2 2006.253.08:17:40.48#ibcon#about to read 4, iclass 17, count 2 2006.253.08:17:40.48#ibcon#read 4, iclass 17, count 2 2006.253.08:17:40.48#ibcon#about to read 5, iclass 17, count 2 2006.253.08:17:40.48#ibcon#read 5, iclass 17, count 2 2006.253.08:17:40.48#ibcon#about to read 6, iclass 17, count 2 2006.253.08:17:40.48#ibcon#read 6, iclass 17, count 2 2006.253.08:17:40.48#ibcon#end of sib2, iclass 17, count 2 2006.253.08:17:40.48#ibcon#*after write, iclass 17, count 2 2006.253.08:17:40.48#ibcon#*before return 0, iclass 17, count 2 2006.253.08:17:40.48#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.253.08:17:40.48#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.253.08:17:40.48#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.253.08:17:40.48#ibcon#ireg 7 cls_cnt 0 2006.253.08:17:40.48#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.253.08:17:40.60#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.253.08:17:40.60#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.253.08:17:40.60#ibcon#enter wrdev, iclass 17, count 0 2006.253.08:17:40.60#ibcon#first serial, iclass 17, count 0 2006.253.08:17:40.60#ibcon#enter sib2, iclass 17, count 0 2006.253.08:17:40.60#ibcon#flushed, iclass 17, count 0 2006.253.08:17:40.60#ibcon#about to write, iclass 17, count 0 2006.253.08:17:40.60#ibcon#wrote, iclass 17, count 0 2006.253.08:17:40.60#ibcon#about to read 3, iclass 17, count 0 2006.253.08:17:40.62#ibcon#read 3, iclass 17, count 0 2006.253.08:17:40.62#ibcon#about to read 4, iclass 17, count 0 2006.253.08:17:40.62#ibcon#read 4, iclass 17, count 0 2006.253.08:17:40.62#ibcon#about to read 5, iclass 17, count 0 2006.253.08:17:40.62#ibcon#read 5, iclass 17, count 0 2006.253.08:17:40.62#ibcon#about to read 6, iclass 17, count 0 2006.253.08:17:40.62#ibcon#read 6, iclass 17, count 0 2006.253.08:17:40.62#ibcon#end of sib2, iclass 17, count 0 2006.253.08:17:40.62#ibcon#*mode == 0, iclass 17, count 0 2006.253.08:17:40.62#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.253.08:17:40.62#ibcon#[25=USB\r\n] 2006.253.08:17:40.62#ibcon#*before write, iclass 17, count 0 2006.253.08:17:40.62#ibcon#enter sib2, iclass 17, count 0 2006.253.08:17:40.62#ibcon#flushed, iclass 17, count 0 2006.253.08:17:40.62#ibcon#about to write, iclass 17, count 0 2006.253.08:17:40.62#ibcon#wrote, iclass 17, count 0 2006.253.08:17:40.62#ibcon#about to read 3, iclass 17, count 0 2006.253.08:17:40.65#ibcon#read 3, iclass 17, count 0 2006.253.08:17:40.65#ibcon#about to read 4, iclass 17, count 0 2006.253.08:17:40.65#ibcon#read 4, iclass 17, count 0 2006.253.08:17:40.65#ibcon#about to read 5, iclass 17, count 0 2006.253.08:17:40.65#ibcon#read 5, iclass 17, count 0 2006.253.08:17:40.65#ibcon#about to read 6, iclass 17, count 0 2006.253.08:17:40.65#ibcon#read 6, iclass 17, count 0 2006.253.08:17:40.65#ibcon#end of sib2, iclass 17, count 0 2006.253.08:17:40.65#ibcon#*after write, iclass 17, count 0 2006.253.08:17:40.65#ibcon#*before return 0, iclass 17, count 0 2006.253.08:17:40.65#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.253.08:17:40.65#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.253.08:17:40.65#ibcon#about to clear, iclass 17 cls_cnt 0 2006.253.08:17:40.65#ibcon#cleared, iclass 17 cls_cnt 0 2006.253.08:17:40.65$vc4f8/vblo=1,632.99 2006.253.08:17:40.65#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.253.08:17:40.65#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.253.08:17:40.65#ibcon#ireg 17 cls_cnt 0 2006.253.08:17:40.65#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.253.08:17:40.65#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.253.08:17:40.65#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.253.08:17:40.65#ibcon#enter wrdev, iclass 19, count 0 2006.253.08:17:40.65#ibcon#first serial, iclass 19, count 0 2006.253.08:17:40.65#ibcon#enter sib2, iclass 19, count 0 2006.253.08:17:40.65#ibcon#flushed, iclass 19, count 0 2006.253.08:17:40.65#ibcon#about to write, iclass 19, count 0 2006.253.08:17:40.65#ibcon#wrote, iclass 19, count 0 2006.253.08:17:40.65#ibcon#about to read 3, iclass 19, count 0 2006.253.08:17:40.67#ibcon#read 3, iclass 19, count 0 2006.253.08:17:40.67#ibcon#about to read 4, iclass 19, count 0 2006.253.08:17:40.67#ibcon#read 4, iclass 19, count 0 2006.253.08:17:40.67#ibcon#about to read 5, iclass 19, count 0 2006.253.08:17:40.67#ibcon#read 5, iclass 19, count 0 2006.253.08:17:40.67#ibcon#about to read 6, iclass 19, count 0 2006.253.08:17:40.67#ibcon#read 6, iclass 19, count 0 2006.253.08:17:40.67#ibcon#end of sib2, iclass 19, count 0 2006.253.08:17:40.67#ibcon#*mode == 0, iclass 19, count 0 2006.253.08:17:40.67#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.253.08:17:40.67#ibcon#[28=FRQ=01,632.99\r\n] 2006.253.08:17:40.67#ibcon#*before write, iclass 19, count 0 2006.253.08:17:40.67#ibcon#enter sib2, iclass 19, count 0 2006.253.08:17:40.67#ibcon#flushed, iclass 19, count 0 2006.253.08:17:40.67#ibcon#about to write, iclass 19, count 0 2006.253.08:17:40.67#ibcon#wrote, iclass 19, count 0 2006.253.08:17:40.67#ibcon#about to read 3, iclass 19, count 0 2006.253.08:17:40.72#ibcon#read 3, iclass 19, count 0 2006.253.08:17:40.72#ibcon#about to read 4, iclass 19, count 0 2006.253.08:17:40.72#ibcon#read 4, iclass 19, count 0 2006.253.08:17:40.72#ibcon#about to read 5, iclass 19, count 0 2006.253.08:17:40.72#ibcon#read 5, iclass 19, count 0 2006.253.08:17:40.72#ibcon#about to read 6, iclass 19, count 0 2006.253.08:17:40.72#ibcon#read 6, iclass 19, count 0 2006.253.08:17:40.72#ibcon#end of sib2, iclass 19, count 0 2006.253.08:17:40.72#ibcon#*after write, iclass 19, count 0 2006.253.08:17:40.72#ibcon#*before return 0, iclass 19, count 0 2006.253.08:17:40.72#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.253.08:17:40.72#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.253.08:17:40.72#ibcon#about to clear, iclass 19 cls_cnt 0 2006.253.08:17:40.72#ibcon#cleared, iclass 19 cls_cnt 0 2006.253.08:17:40.72$vc4f8/vb=1,4 2006.253.08:17:40.72#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.253.08:17:40.72#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.253.08:17:40.72#ibcon#ireg 11 cls_cnt 2 2006.253.08:17:40.72#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.253.08:17:40.72#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.253.08:17:40.72#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.253.08:17:40.72#ibcon#enter wrdev, iclass 21, count 2 2006.253.08:17:40.72#ibcon#first serial, iclass 21, count 2 2006.253.08:17:40.72#ibcon#enter sib2, iclass 21, count 2 2006.253.08:17:40.72#ibcon#flushed, iclass 21, count 2 2006.253.08:17:40.72#ibcon#about to write, iclass 21, count 2 2006.253.08:17:40.72#ibcon#wrote, iclass 21, count 2 2006.253.08:17:40.72#ibcon#about to read 3, iclass 21, count 2 2006.253.08:17:40.74#ibcon#read 3, iclass 21, count 2 2006.253.08:17:40.74#ibcon#about to read 4, iclass 21, count 2 2006.253.08:17:40.74#ibcon#read 4, iclass 21, count 2 2006.253.08:17:40.74#ibcon#about to read 5, iclass 21, count 2 2006.253.08:17:40.74#ibcon#read 5, iclass 21, count 2 2006.253.08:17:40.74#ibcon#about to read 6, iclass 21, count 2 2006.253.08:17:40.74#ibcon#read 6, iclass 21, count 2 2006.253.08:17:40.74#ibcon#end of sib2, iclass 21, count 2 2006.253.08:17:40.74#ibcon#*mode == 0, iclass 21, count 2 2006.253.08:17:40.74#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.253.08:17:40.74#ibcon#[27=AT01-04\r\n] 2006.253.08:17:40.74#ibcon#*before write, iclass 21, count 2 2006.253.08:17:40.74#ibcon#enter sib2, iclass 21, count 2 2006.253.08:17:40.74#ibcon#flushed, iclass 21, count 2 2006.253.08:17:40.74#ibcon#about to write, iclass 21, count 2 2006.253.08:17:40.74#ibcon#wrote, iclass 21, count 2 2006.253.08:17:40.74#ibcon#about to read 3, iclass 21, count 2 2006.253.08:17:40.77#ibcon#read 3, iclass 21, count 2 2006.253.08:17:40.77#ibcon#about to read 4, iclass 21, count 2 2006.253.08:17:40.77#ibcon#read 4, iclass 21, count 2 2006.253.08:17:40.77#ibcon#about to read 5, iclass 21, count 2 2006.253.08:17:40.77#ibcon#read 5, iclass 21, count 2 2006.253.08:17:40.77#ibcon#about to read 6, iclass 21, count 2 2006.253.08:17:40.77#ibcon#read 6, iclass 21, count 2 2006.253.08:17:40.77#ibcon#end of sib2, iclass 21, count 2 2006.253.08:17:40.77#ibcon#*after write, iclass 21, count 2 2006.253.08:17:40.77#ibcon#*before return 0, iclass 21, count 2 2006.253.08:17:40.77#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.253.08:17:40.77#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.253.08:17:40.77#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.253.08:17:40.77#ibcon#ireg 7 cls_cnt 0 2006.253.08:17:40.77#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.253.08:17:40.89#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.253.08:17:40.89#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.253.08:17:40.89#ibcon#enter wrdev, iclass 21, count 0 2006.253.08:17:40.89#ibcon#first serial, iclass 21, count 0 2006.253.08:17:40.89#ibcon#enter sib2, iclass 21, count 0 2006.253.08:17:40.89#ibcon#flushed, iclass 21, count 0 2006.253.08:17:40.89#ibcon#about to write, iclass 21, count 0 2006.253.08:17:40.89#ibcon#wrote, iclass 21, count 0 2006.253.08:17:40.89#ibcon#about to read 3, iclass 21, count 0 2006.253.08:17:40.91#ibcon#read 3, iclass 21, count 0 2006.253.08:17:40.91#ibcon#about to read 4, iclass 21, count 0 2006.253.08:17:40.91#ibcon#read 4, iclass 21, count 0 2006.253.08:17:40.91#ibcon#about to read 5, iclass 21, count 0 2006.253.08:17:40.91#ibcon#read 5, iclass 21, count 0 2006.253.08:17:40.91#ibcon#about to read 6, iclass 21, count 0 2006.253.08:17:40.91#ibcon#read 6, iclass 21, count 0 2006.253.08:17:40.91#ibcon#end of sib2, iclass 21, count 0 2006.253.08:17:40.91#ibcon#*mode == 0, iclass 21, count 0 2006.253.08:17:40.91#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.253.08:17:40.91#ibcon#[27=USB\r\n] 2006.253.08:17:40.91#ibcon#*before write, iclass 21, count 0 2006.253.08:17:40.91#ibcon#enter sib2, iclass 21, count 0 2006.253.08:17:40.91#ibcon#flushed, iclass 21, count 0 2006.253.08:17:40.91#ibcon#about to write, iclass 21, count 0 2006.253.08:17:40.91#ibcon#wrote, iclass 21, count 0 2006.253.08:17:40.91#ibcon#about to read 3, iclass 21, count 0 2006.253.08:17:40.94#ibcon#read 3, iclass 21, count 0 2006.253.08:17:40.94#ibcon#about to read 4, iclass 21, count 0 2006.253.08:17:40.94#ibcon#read 4, iclass 21, count 0 2006.253.08:17:40.94#ibcon#about to read 5, iclass 21, count 0 2006.253.08:17:40.94#ibcon#read 5, iclass 21, count 0 2006.253.08:17:40.94#ibcon#about to read 6, iclass 21, count 0 2006.253.08:17:40.94#ibcon#read 6, iclass 21, count 0 2006.253.08:17:40.94#ibcon#end of sib2, iclass 21, count 0 2006.253.08:17:40.94#ibcon#*after write, iclass 21, count 0 2006.253.08:17:40.94#ibcon#*before return 0, iclass 21, count 0 2006.253.08:17:40.94#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.253.08:17:40.94#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.253.08:17:40.94#ibcon#about to clear, iclass 21 cls_cnt 0 2006.253.08:17:40.94#ibcon#cleared, iclass 21 cls_cnt 0 2006.253.08:17:40.94$vc4f8/vblo=2,640.99 2006.253.08:17:40.94#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.253.08:17:40.94#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.253.08:17:40.94#ibcon#ireg 17 cls_cnt 0 2006.253.08:17:40.94#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.253.08:17:40.94#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.253.08:17:40.94#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.253.08:17:40.94#ibcon#enter wrdev, iclass 23, count 0 2006.253.08:17:40.94#ibcon#first serial, iclass 23, count 0 2006.253.08:17:40.94#ibcon#enter sib2, iclass 23, count 0 2006.253.08:17:40.94#ibcon#flushed, iclass 23, count 0 2006.253.08:17:40.94#ibcon#about to write, iclass 23, count 0 2006.253.08:17:40.94#ibcon#wrote, iclass 23, count 0 2006.253.08:17:40.94#ibcon#about to read 3, iclass 23, count 0 2006.253.08:17:40.96#ibcon#read 3, iclass 23, count 0 2006.253.08:17:40.96#ibcon#about to read 4, iclass 23, count 0 2006.253.08:17:40.96#ibcon#read 4, iclass 23, count 0 2006.253.08:17:40.96#ibcon#about to read 5, iclass 23, count 0 2006.253.08:17:40.96#ibcon#read 5, iclass 23, count 0 2006.253.08:17:40.96#ibcon#about to read 6, iclass 23, count 0 2006.253.08:17:40.96#ibcon#read 6, iclass 23, count 0 2006.253.08:17:40.96#ibcon#end of sib2, iclass 23, count 0 2006.253.08:17:40.96#ibcon#*mode == 0, iclass 23, count 0 2006.253.08:17:40.96#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.253.08:17:40.96#ibcon#[28=FRQ=02,640.99\r\n] 2006.253.08:17:40.96#ibcon#*before write, iclass 23, count 0 2006.253.08:17:40.96#ibcon#enter sib2, iclass 23, count 0 2006.253.08:17:40.96#ibcon#flushed, iclass 23, count 0 2006.253.08:17:40.96#ibcon#about to write, iclass 23, count 0 2006.253.08:17:40.96#ibcon#wrote, iclass 23, count 0 2006.253.08:17:40.96#ibcon#about to read 3, iclass 23, count 0 2006.253.08:17:41.00#ibcon#read 3, iclass 23, count 0 2006.253.08:17:41.00#ibcon#about to read 4, iclass 23, count 0 2006.253.08:17:41.00#ibcon#read 4, iclass 23, count 0 2006.253.08:17:41.00#ibcon#about to read 5, iclass 23, count 0 2006.253.08:17:41.00#ibcon#read 5, iclass 23, count 0 2006.253.08:17:41.00#ibcon#about to read 6, iclass 23, count 0 2006.253.08:17:41.00#ibcon#read 6, iclass 23, count 0 2006.253.08:17:41.00#ibcon#end of sib2, iclass 23, count 0 2006.253.08:17:41.00#ibcon#*after write, iclass 23, count 0 2006.253.08:17:41.00#ibcon#*before return 0, iclass 23, count 0 2006.253.08:17:41.00#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.253.08:17:41.00#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.253.08:17:41.00#ibcon#about to clear, iclass 23 cls_cnt 0 2006.253.08:17:41.00#ibcon#cleared, iclass 23 cls_cnt 0 2006.253.08:17:41.00$vc4f8/vb=2,5 2006.253.08:17:41.00#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.253.08:17:41.00#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.253.08:17:41.00#ibcon#ireg 11 cls_cnt 2 2006.253.08:17:41.00#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.253.08:17:41.06#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.253.08:17:41.06#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.253.08:17:41.06#ibcon#enter wrdev, iclass 25, count 2 2006.253.08:17:41.06#ibcon#first serial, iclass 25, count 2 2006.253.08:17:41.06#ibcon#enter sib2, iclass 25, count 2 2006.253.08:17:41.06#ibcon#flushed, iclass 25, count 2 2006.253.08:17:41.06#ibcon#about to write, iclass 25, count 2 2006.253.08:17:41.06#ibcon#wrote, iclass 25, count 2 2006.253.08:17:41.06#ibcon#about to read 3, iclass 25, count 2 2006.253.08:17:41.08#ibcon#read 3, iclass 25, count 2 2006.253.08:17:41.08#ibcon#about to read 4, iclass 25, count 2 2006.253.08:17:41.08#ibcon#read 4, iclass 25, count 2 2006.253.08:17:41.08#ibcon#about to read 5, iclass 25, count 2 2006.253.08:17:41.08#ibcon#read 5, iclass 25, count 2 2006.253.08:17:41.08#ibcon#about to read 6, iclass 25, count 2 2006.253.08:17:41.08#ibcon#read 6, iclass 25, count 2 2006.253.08:17:41.08#ibcon#end of sib2, iclass 25, count 2 2006.253.08:17:41.08#ibcon#*mode == 0, iclass 25, count 2 2006.253.08:17:41.08#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.253.08:17:41.08#ibcon#[27=AT02-05\r\n] 2006.253.08:17:41.08#ibcon#*before write, iclass 25, count 2 2006.253.08:17:41.08#ibcon#enter sib2, iclass 25, count 2 2006.253.08:17:41.08#ibcon#flushed, iclass 25, count 2 2006.253.08:17:41.08#ibcon#about to write, iclass 25, count 2 2006.253.08:17:41.08#ibcon#wrote, iclass 25, count 2 2006.253.08:17:41.08#ibcon#about to read 3, iclass 25, count 2 2006.253.08:17:41.11#ibcon#read 3, iclass 25, count 2 2006.253.08:17:41.11#ibcon#about to read 4, iclass 25, count 2 2006.253.08:17:41.11#ibcon#read 4, iclass 25, count 2 2006.253.08:17:41.11#ibcon#about to read 5, iclass 25, count 2 2006.253.08:17:41.11#ibcon#read 5, iclass 25, count 2 2006.253.08:17:41.11#ibcon#about to read 6, iclass 25, count 2 2006.253.08:17:41.11#ibcon#read 6, iclass 25, count 2 2006.253.08:17:41.11#ibcon#end of sib2, iclass 25, count 2 2006.253.08:17:41.11#ibcon#*after write, iclass 25, count 2 2006.253.08:17:41.11#ibcon#*before return 0, iclass 25, count 2 2006.253.08:17:41.11#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.253.08:17:41.11#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.253.08:17:41.11#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.253.08:17:41.11#ibcon#ireg 7 cls_cnt 0 2006.253.08:17:41.11#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.253.08:17:41.23#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.253.08:17:41.23#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.253.08:17:41.23#ibcon#enter wrdev, iclass 25, count 0 2006.253.08:17:41.23#ibcon#first serial, iclass 25, count 0 2006.253.08:17:41.23#ibcon#enter sib2, iclass 25, count 0 2006.253.08:17:41.23#ibcon#flushed, iclass 25, count 0 2006.253.08:17:41.23#ibcon#about to write, iclass 25, count 0 2006.253.08:17:41.23#ibcon#wrote, iclass 25, count 0 2006.253.08:17:41.23#ibcon#about to read 3, iclass 25, count 0 2006.253.08:17:41.25#ibcon#read 3, iclass 25, count 0 2006.253.08:17:41.25#ibcon#about to read 4, iclass 25, count 0 2006.253.08:17:41.25#ibcon#read 4, iclass 25, count 0 2006.253.08:17:41.25#ibcon#about to read 5, iclass 25, count 0 2006.253.08:17:41.25#ibcon#read 5, iclass 25, count 0 2006.253.08:17:41.25#ibcon#about to read 6, iclass 25, count 0 2006.253.08:17:41.25#ibcon#read 6, iclass 25, count 0 2006.253.08:17:41.25#ibcon#end of sib2, iclass 25, count 0 2006.253.08:17:41.25#ibcon#*mode == 0, iclass 25, count 0 2006.253.08:17:41.25#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.253.08:17:41.25#ibcon#[27=USB\r\n] 2006.253.08:17:41.25#ibcon#*before write, iclass 25, count 0 2006.253.08:17:41.25#ibcon#enter sib2, iclass 25, count 0 2006.253.08:17:41.25#ibcon#flushed, iclass 25, count 0 2006.253.08:17:41.25#ibcon#about to write, iclass 25, count 0 2006.253.08:17:41.25#ibcon#wrote, iclass 25, count 0 2006.253.08:17:41.25#ibcon#about to read 3, iclass 25, count 0 2006.253.08:17:41.28#ibcon#read 3, iclass 25, count 0 2006.253.08:17:41.28#ibcon#about to read 4, iclass 25, count 0 2006.253.08:17:41.28#ibcon#read 4, iclass 25, count 0 2006.253.08:17:41.28#ibcon#about to read 5, iclass 25, count 0 2006.253.08:17:41.28#ibcon#read 5, iclass 25, count 0 2006.253.08:17:41.28#ibcon#about to read 6, iclass 25, count 0 2006.253.08:17:41.28#ibcon#read 6, iclass 25, count 0 2006.253.08:17:41.28#ibcon#end of sib2, iclass 25, count 0 2006.253.08:17:41.28#ibcon#*after write, iclass 25, count 0 2006.253.08:17:41.28#ibcon#*before return 0, iclass 25, count 0 2006.253.08:17:41.28#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.253.08:17:41.28#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.253.08:17:41.28#ibcon#about to clear, iclass 25 cls_cnt 0 2006.253.08:17:41.28#ibcon#cleared, iclass 25 cls_cnt 0 2006.253.08:17:41.28$vc4f8/vblo=3,656.99 2006.253.08:17:41.28#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.253.08:17:41.28#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.253.08:17:41.28#ibcon#ireg 17 cls_cnt 0 2006.253.08:17:41.28#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.253.08:17:41.28#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.253.08:17:41.28#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.253.08:17:41.28#ibcon#enter wrdev, iclass 27, count 0 2006.253.08:17:41.28#ibcon#first serial, iclass 27, count 0 2006.253.08:17:41.28#ibcon#enter sib2, iclass 27, count 0 2006.253.08:17:41.28#ibcon#flushed, iclass 27, count 0 2006.253.08:17:41.28#ibcon#about to write, iclass 27, count 0 2006.253.08:17:41.28#ibcon#wrote, iclass 27, count 0 2006.253.08:17:41.28#ibcon#about to read 3, iclass 27, count 0 2006.253.08:17:41.30#ibcon#read 3, iclass 27, count 0 2006.253.08:17:41.30#ibcon#about to read 4, iclass 27, count 0 2006.253.08:17:41.30#ibcon#read 4, iclass 27, count 0 2006.253.08:17:41.30#ibcon#about to read 5, iclass 27, count 0 2006.253.08:17:41.30#ibcon#read 5, iclass 27, count 0 2006.253.08:17:41.30#ibcon#about to read 6, iclass 27, count 0 2006.253.08:17:41.30#ibcon#read 6, iclass 27, count 0 2006.253.08:17:41.30#ibcon#end of sib2, iclass 27, count 0 2006.253.08:17:41.30#ibcon#*mode == 0, iclass 27, count 0 2006.253.08:17:41.30#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.253.08:17:41.30#ibcon#[28=FRQ=03,656.99\r\n] 2006.253.08:17:41.30#ibcon#*before write, iclass 27, count 0 2006.253.08:17:41.30#ibcon#enter sib2, iclass 27, count 0 2006.253.08:17:41.30#ibcon#flushed, iclass 27, count 0 2006.253.08:17:41.30#ibcon#about to write, iclass 27, count 0 2006.253.08:17:41.30#ibcon#wrote, iclass 27, count 0 2006.253.08:17:41.30#ibcon#about to read 3, iclass 27, count 0 2006.253.08:17:41.34#ibcon#read 3, iclass 27, count 0 2006.253.08:17:41.34#ibcon#about to read 4, iclass 27, count 0 2006.253.08:17:41.34#ibcon#read 4, iclass 27, count 0 2006.253.08:17:41.34#ibcon#about to read 5, iclass 27, count 0 2006.253.08:17:41.34#ibcon#read 5, iclass 27, count 0 2006.253.08:17:41.34#ibcon#about to read 6, iclass 27, count 0 2006.253.08:17:41.34#ibcon#read 6, iclass 27, count 0 2006.253.08:17:41.34#ibcon#end of sib2, iclass 27, count 0 2006.253.08:17:41.34#ibcon#*after write, iclass 27, count 0 2006.253.08:17:41.34#ibcon#*before return 0, iclass 27, count 0 2006.253.08:17:41.34#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.253.08:17:41.34#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.253.08:17:41.34#ibcon#about to clear, iclass 27 cls_cnt 0 2006.253.08:17:41.34#ibcon#cleared, iclass 27 cls_cnt 0 2006.253.08:17:41.34$vc4f8/vb=3,4 2006.253.08:17:41.34#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.253.08:17:41.34#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.253.08:17:41.34#ibcon#ireg 11 cls_cnt 2 2006.253.08:17:41.34#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.253.08:17:41.40#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.253.08:17:41.40#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.253.08:17:41.40#ibcon#enter wrdev, iclass 29, count 2 2006.253.08:17:41.40#ibcon#first serial, iclass 29, count 2 2006.253.08:17:41.40#ibcon#enter sib2, iclass 29, count 2 2006.253.08:17:41.40#ibcon#flushed, iclass 29, count 2 2006.253.08:17:41.40#ibcon#about to write, iclass 29, count 2 2006.253.08:17:41.40#ibcon#wrote, iclass 29, count 2 2006.253.08:17:41.40#ibcon#about to read 3, iclass 29, count 2 2006.253.08:17:41.42#ibcon#read 3, iclass 29, count 2 2006.253.08:17:41.42#ibcon#about to read 4, iclass 29, count 2 2006.253.08:17:41.42#ibcon#read 4, iclass 29, count 2 2006.253.08:17:41.42#ibcon#about to read 5, iclass 29, count 2 2006.253.08:17:41.42#ibcon#read 5, iclass 29, count 2 2006.253.08:17:41.42#ibcon#about to read 6, iclass 29, count 2 2006.253.08:17:41.42#ibcon#read 6, iclass 29, count 2 2006.253.08:17:41.42#ibcon#end of sib2, iclass 29, count 2 2006.253.08:17:41.42#ibcon#*mode == 0, iclass 29, count 2 2006.253.08:17:41.42#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.253.08:17:41.42#ibcon#[27=AT03-04\r\n] 2006.253.08:17:41.42#ibcon#*before write, iclass 29, count 2 2006.253.08:17:41.42#ibcon#enter sib2, iclass 29, count 2 2006.253.08:17:41.42#ibcon#flushed, iclass 29, count 2 2006.253.08:17:41.42#ibcon#about to write, iclass 29, count 2 2006.253.08:17:41.42#ibcon#wrote, iclass 29, count 2 2006.253.08:17:41.42#ibcon#about to read 3, iclass 29, count 2 2006.253.08:17:41.45#ibcon#read 3, iclass 29, count 2 2006.253.08:17:41.45#ibcon#about to read 4, iclass 29, count 2 2006.253.08:17:41.45#ibcon#read 4, iclass 29, count 2 2006.253.08:17:41.45#ibcon#about to read 5, iclass 29, count 2 2006.253.08:17:41.45#ibcon#read 5, iclass 29, count 2 2006.253.08:17:41.45#ibcon#about to read 6, iclass 29, count 2 2006.253.08:17:41.45#ibcon#read 6, iclass 29, count 2 2006.253.08:17:41.45#ibcon#end of sib2, iclass 29, count 2 2006.253.08:17:41.45#ibcon#*after write, iclass 29, count 2 2006.253.08:17:41.45#ibcon#*before return 0, iclass 29, count 2 2006.253.08:17:41.45#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.253.08:17:41.45#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.253.08:17:41.45#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.253.08:17:41.45#ibcon#ireg 7 cls_cnt 0 2006.253.08:17:41.45#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.253.08:17:41.57#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.253.08:17:41.57#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.253.08:17:41.57#ibcon#enter wrdev, iclass 29, count 0 2006.253.08:17:41.57#ibcon#first serial, iclass 29, count 0 2006.253.08:17:41.57#ibcon#enter sib2, iclass 29, count 0 2006.253.08:17:41.57#ibcon#flushed, iclass 29, count 0 2006.253.08:17:41.57#ibcon#about to write, iclass 29, count 0 2006.253.08:17:41.57#ibcon#wrote, iclass 29, count 0 2006.253.08:17:41.57#ibcon#about to read 3, iclass 29, count 0 2006.253.08:17:41.59#ibcon#read 3, iclass 29, count 0 2006.253.08:17:41.59#ibcon#about to read 4, iclass 29, count 0 2006.253.08:17:41.59#ibcon#read 4, iclass 29, count 0 2006.253.08:17:41.59#ibcon#about to read 5, iclass 29, count 0 2006.253.08:17:41.59#ibcon#read 5, iclass 29, count 0 2006.253.08:17:41.59#ibcon#about to read 6, iclass 29, count 0 2006.253.08:17:41.59#ibcon#read 6, iclass 29, count 0 2006.253.08:17:41.59#ibcon#end of sib2, iclass 29, count 0 2006.253.08:17:41.59#ibcon#*mode == 0, iclass 29, count 0 2006.253.08:17:41.59#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.253.08:17:41.59#ibcon#[27=USB\r\n] 2006.253.08:17:41.59#ibcon#*before write, iclass 29, count 0 2006.253.08:17:41.59#ibcon#enter sib2, iclass 29, count 0 2006.253.08:17:41.59#ibcon#flushed, iclass 29, count 0 2006.253.08:17:41.59#ibcon#about to write, iclass 29, count 0 2006.253.08:17:41.59#ibcon#wrote, iclass 29, count 0 2006.253.08:17:41.59#ibcon#about to read 3, iclass 29, count 0 2006.253.08:17:41.62#ibcon#read 3, iclass 29, count 0 2006.253.08:17:41.62#ibcon#about to read 4, iclass 29, count 0 2006.253.08:17:41.62#ibcon#read 4, iclass 29, count 0 2006.253.08:17:41.62#ibcon#about to read 5, iclass 29, count 0 2006.253.08:17:41.62#ibcon#read 5, iclass 29, count 0 2006.253.08:17:41.62#ibcon#about to read 6, iclass 29, count 0 2006.253.08:17:41.62#ibcon#read 6, iclass 29, count 0 2006.253.08:17:41.62#ibcon#end of sib2, iclass 29, count 0 2006.253.08:17:41.62#ibcon#*after write, iclass 29, count 0 2006.253.08:17:41.62#ibcon#*before return 0, iclass 29, count 0 2006.253.08:17:41.62#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.253.08:17:41.62#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.253.08:17:41.62#ibcon#about to clear, iclass 29 cls_cnt 0 2006.253.08:17:41.62#ibcon#cleared, iclass 29 cls_cnt 0 2006.253.08:17:41.62$vc4f8/vblo=4,712.99 2006.253.08:17:41.62#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.253.08:17:41.62#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.253.08:17:41.62#ibcon#ireg 17 cls_cnt 0 2006.253.08:17:41.62#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.253.08:17:41.62#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.253.08:17:41.62#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.253.08:17:41.62#ibcon#enter wrdev, iclass 31, count 0 2006.253.08:17:41.62#ibcon#first serial, iclass 31, count 0 2006.253.08:17:41.62#ibcon#enter sib2, iclass 31, count 0 2006.253.08:17:41.62#ibcon#flushed, iclass 31, count 0 2006.253.08:17:41.62#ibcon#about to write, iclass 31, count 0 2006.253.08:17:41.62#ibcon#wrote, iclass 31, count 0 2006.253.08:17:41.62#ibcon#about to read 3, iclass 31, count 0 2006.253.08:17:41.64#ibcon#read 3, iclass 31, count 0 2006.253.08:17:41.64#ibcon#about to read 4, iclass 31, count 0 2006.253.08:17:41.64#ibcon#read 4, iclass 31, count 0 2006.253.08:17:41.64#ibcon#about to read 5, iclass 31, count 0 2006.253.08:17:41.64#ibcon#read 5, iclass 31, count 0 2006.253.08:17:41.64#ibcon#about to read 6, iclass 31, count 0 2006.253.08:17:41.64#ibcon#read 6, iclass 31, count 0 2006.253.08:17:41.64#ibcon#end of sib2, iclass 31, count 0 2006.253.08:17:41.64#ibcon#*mode == 0, iclass 31, count 0 2006.253.08:17:41.64#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.253.08:17:41.64#ibcon#[28=FRQ=04,712.99\r\n] 2006.253.08:17:41.64#ibcon#*before write, iclass 31, count 0 2006.253.08:17:41.64#ibcon#enter sib2, iclass 31, count 0 2006.253.08:17:41.64#ibcon#flushed, iclass 31, count 0 2006.253.08:17:41.64#ibcon#about to write, iclass 31, count 0 2006.253.08:17:41.64#ibcon#wrote, iclass 31, count 0 2006.253.08:17:41.64#ibcon#about to read 3, iclass 31, count 0 2006.253.08:17:41.68#ibcon#read 3, iclass 31, count 0 2006.253.08:17:41.68#ibcon#about to read 4, iclass 31, count 0 2006.253.08:17:41.68#ibcon#read 4, iclass 31, count 0 2006.253.08:17:41.68#ibcon#about to read 5, iclass 31, count 0 2006.253.08:17:41.68#ibcon#read 5, iclass 31, count 0 2006.253.08:17:41.68#ibcon#about to read 6, iclass 31, count 0 2006.253.08:17:41.68#ibcon#read 6, iclass 31, count 0 2006.253.08:17:41.68#ibcon#end of sib2, iclass 31, count 0 2006.253.08:17:41.68#ibcon#*after write, iclass 31, count 0 2006.253.08:17:41.68#ibcon#*before return 0, iclass 31, count 0 2006.253.08:17:41.68#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.253.08:17:41.68#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.253.08:17:41.68#ibcon#about to clear, iclass 31 cls_cnt 0 2006.253.08:17:41.68#ibcon#cleared, iclass 31 cls_cnt 0 2006.253.08:17:41.68$vc4f8/vb=4,4 2006.253.08:17:41.68#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.253.08:17:41.68#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.253.08:17:41.68#ibcon#ireg 11 cls_cnt 2 2006.253.08:17:41.68#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.253.08:17:41.74#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.253.08:17:41.74#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.253.08:17:41.74#ibcon#enter wrdev, iclass 33, count 2 2006.253.08:17:41.74#ibcon#first serial, iclass 33, count 2 2006.253.08:17:41.74#ibcon#enter sib2, iclass 33, count 2 2006.253.08:17:41.74#ibcon#flushed, iclass 33, count 2 2006.253.08:17:41.74#ibcon#about to write, iclass 33, count 2 2006.253.08:17:41.74#ibcon#wrote, iclass 33, count 2 2006.253.08:17:41.74#ibcon#about to read 3, iclass 33, count 2 2006.253.08:17:41.76#ibcon#read 3, iclass 33, count 2 2006.253.08:17:41.76#ibcon#about to read 4, iclass 33, count 2 2006.253.08:17:41.76#ibcon#read 4, iclass 33, count 2 2006.253.08:17:41.76#ibcon#about to read 5, iclass 33, count 2 2006.253.08:17:41.76#ibcon#read 5, iclass 33, count 2 2006.253.08:17:41.76#ibcon#about to read 6, iclass 33, count 2 2006.253.08:17:41.76#ibcon#read 6, iclass 33, count 2 2006.253.08:17:41.76#ibcon#end of sib2, iclass 33, count 2 2006.253.08:17:41.76#ibcon#*mode == 0, iclass 33, count 2 2006.253.08:17:41.76#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.253.08:17:41.76#ibcon#[27=AT04-04\r\n] 2006.253.08:17:41.76#ibcon#*before write, iclass 33, count 2 2006.253.08:17:41.76#ibcon#enter sib2, iclass 33, count 2 2006.253.08:17:41.76#ibcon#flushed, iclass 33, count 2 2006.253.08:17:41.76#ibcon#about to write, iclass 33, count 2 2006.253.08:17:41.76#ibcon#wrote, iclass 33, count 2 2006.253.08:17:41.76#ibcon#about to read 3, iclass 33, count 2 2006.253.08:17:41.79#ibcon#read 3, iclass 33, count 2 2006.253.08:17:41.79#ibcon#about to read 4, iclass 33, count 2 2006.253.08:17:41.79#ibcon#read 4, iclass 33, count 2 2006.253.08:17:41.79#ibcon#about to read 5, iclass 33, count 2 2006.253.08:17:41.79#ibcon#read 5, iclass 33, count 2 2006.253.08:17:41.79#ibcon#about to read 6, iclass 33, count 2 2006.253.08:17:41.79#ibcon#read 6, iclass 33, count 2 2006.253.08:17:41.79#ibcon#end of sib2, iclass 33, count 2 2006.253.08:17:41.79#ibcon#*after write, iclass 33, count 2 2006.253.08:17:41.79#ibcon#*before return 0, iclass 33, count 2 2006.253.08:17:41.79#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.253.08:17:41.79#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.253.08:17:41.79#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.253.08:17:41.79#ibcon#ireg 7 cls_cnt 0 2006.253.08:17:41.79#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.253.08:17:41.91#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.253.08:17:41.91#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.253.08:17:41.91#ibcon#enter wrdev, iclass 33, count 0 2006.253.08:17:41.91#ibcon#first serial, iclass 33, count 0 2006.253.08:17:41.91#ibcon#enter sib2, iclass 33, count 0 2006.253.08:17:41.91#ibcon#flushed, iclass 33, count 0 2006.253.08:17:41.91#ibcon#about to write, iclass 33, count 0 2006.253.08:17:41.91#ibcon#wrote, iclass 33, count 0 2006.253.08:17:41.91#ibcon#about to read 3, iclass 33, count 0 2006.253.08:17:41.93#ibcon#read 3, iclass 33, count 0 2006.253.08:17:41.93#ibcon#about to read 4, iclass 33, count 0 2006.253.08:17:41.93#ibcon#read 4, iclass 33, count 0 2006.253.08:17:41.93#ibcon#about to read 5, iclass 33, count 0 2006.253.08:17:41.93#ibcon#read 5, iclass 33, count 0 2006.253.08:17:41.93#ibcon#about to read 6, iclass 33, count 0 2006.253.08:17:41.93#ibcon#read 6, iclass 33, count 0 2006.253.08:17:41.93#ibcon#end of sib2, iclass 33, count 0 2006.253.08:17:41.93#ibcon#*mode == 0, iclass 33, count 0 2006.253.08:17:41.93#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.253.08:17:41.93#ibcon#[27=USB\r\n] 2006.253.08:17:41.93#ibcon#*before write, iclass 33, count 0 2006.253.08:17:41.93#ibcon#enter sib2, iclass 33, count 0 2006.253.08:17:41.93#ibcon#flushed, iclass 33, count 0 2006.253.08:17:41.93#ibcon#about to write, iclass 33, count 0 2006.253.08:17:41.93#ibcon#wrote, iclass 33, count 0 2006.253.08:17:41.93#ibcon#about to read 3, iclass 33, count 0 2006.253.08:17:41.96#ibcon#read 3, iclass 33, count 0 2006.253.08:17:41.96#ibcon#about to read 4, iclass 33, count 0 2006.253.08:17:41.96#ibcon#read 4, iclass 33, count 0 2006.253.08:17:41.96#ibcon#about to read 5, iclass 33, count 0 2006.253.08:17:41.96#ibcon#read 5, iclass 33, count 0 2006.253.08:17:41.96#ibcon#about to read 6, iclass 33, count 0 2006.253.08:17:41.96#ibcon#read 6, iclass 33, count 0 2006.253.08:17:41.96#ibcon#end of sib2, iclass 33, count 0 2006.253.08:17:41.96#ibcon#*after write, iclass 33, count 0 2006.253.08:17:41.96#ibcon#*before return 0, iclass 33, count 0 2006.253.08:17:41.96#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.253.08:17:41.96#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.253.08:17:41.96#ibcon#about to clear, iclass 33 cls_cnt 0 2006.253.08:17:41.96#ibcon#cleared, iclass 33 cls_cnt 0 2006.253.08:17:41.96$vc4f8/vblo=5,744.99 2006.253.08:17:41.96#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.253.08:17:41.96#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.253.08:17:41.96#ibcon#ireg 17 cls_cnt 0 2006.253.08:17:41.96#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.253.08:17:41.96#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.253.08:17:41.96#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.253.08:17:41.96#ibcon#enter wrdev, iclass 35, count 0 2006.253.08:17:41.96#ibcon#first serial, iclass 35, count 0 2006.253.08:17:41.96#ibcon#enter sib2, iclass 35, count 0 2006.253.08:17:41.96#ibcon#flushed, iclass 35, count 0 2006.253.08:17:41.96#ibcon#about to write, iclass 35, count 0 2006.253.08:17:41.96#ibcon#wrote, iclass 35, count 0 2006.253.08:17:41.96#ibcon#about to read 3, iclass 35, count 0 2006.253.08:17:41.98#ibcon#read 3, iclass 35, count 0 2006.253.08:17:41.98#ibcon#about to read 4, iclass 35, count 0 2006.253.08:17:41.98#ibcon#read 4, iclass 35, count 0 2006.253.08:17:41.98#ibcon#about to read 5, iclass 35, count 0 2006.253.08:17:41.98#ibcon#read 5, iclass 35, count 0 2006.253.08:17:41.98#ibcon#about to read 6, iclass 35, count 0 2006.253.08:17:41.98#ibcon#read 6, iclass 35, count 0 2006.253.08:17:41.98#ibcon#end of sib2, iclass 35, count 0 2006.253.08:17:41.98#ibcon#*mode == 0, iclass 35, count 0 2006.253.08:17:41.98#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.253.08:17:41.98#ibcon#[28=FRQ=05,744.99\r\n] 2006.253.08:17:41.98#ibcon#*before write, iclass 35, count 0 2006.253.08:17:41.98#ibcon#enter sib2, iclass 35, count 0 2006.253.08:17:41.98#ibcon#flushed, iclass 35, count 0 2006.253.08:17:41.98#ibcon#about to write, iclass 35, count 0 2006.253.08:17:41.98#ibcon#wrote, iclass 35, count 0 2006.253.08:17:41.98#ibcon#about to read 3, iclass 35, count 0 2006.253.08:17:42.02#ibcon#read 3, iclass 35, count 0 2006.253.08:17:42.02#ibcon#about to read 4, iclass 35, count 0 2006.253.08:17:42.02#ibcon#read 4, iclass 35, count 0 2006.253.08:17:42.02#ibcon#about to read 5, iclass 35, count 0 2006.253.08:17:42.02#ibcon#read 5, iclass 35, count 0 2006.253.08:17:42.02#ibcon#about to read 6, iclass 35, count 0 2006.253.08:17:42.02#ibcon#read 6, iclass 35, count 0 2006.253.08:17:42.02#ibcon#end of sib2, iclass 35, count 0 2006.253.08:17:42.02#ibcon#*after write, iclass 35, count 0 2006.253.08:17:42.02#ibcon#*before return 0, iclass 35, count 0 2006.253.08:17:42.02#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.253.08:17:42.02#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.253.08:17:42.02#ibcon#about to clear, iclass 35 cls_cnt 0 2006.253.08:17:42.02#ibcon#cleared, iclass 35 cls_cnt 0 2006.253.08:17:42.02$vc4f8/vb=5,4 2006.253.08:17:42.02#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.253.08:17:42.02#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.253.08:17:42.02#ibcon#ireg 11 cls_cnt 2 2006.253.08:17:42.02#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.253.08:17:42.08#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.253.08:17:42.08#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.253.08:17:42.08#ibcon#enter wrdev, iclass 37, count 2 2006.253.08:17:42.08#ibcon#first serial, iclass 37, count 2 2006.253.08:17:42.08#ibcon#enter sib2, iclass 37, count 2 2006.253.08:17:42.08#ibcon#flushed, iclass 37, count 2 2006.253.08:17:42.08#ibcon#about to write, iclass 37, count 2 2006.253.08:17:42.08#ibcon#wrote, iclass 37, count 2 2006.253.08:17:42.08#ibcon#about to read 3, iclass 37, count 2 2006.253.08:17:42.10#ibcon#read 3, iclass 37, count 2 2006.253.08:17:42.10#ibcon#about to read 4, iclass 37, count 2 2006.253.08:17:42.10#ibcon#read 4, iclass 37, count 2 2006.253.08:17:42.10#ibcon#about to read 5, iclass 37, count 2 2006.253.08:17:42.10#ibcon#read 5, iclass 37, count 2 2006.253.08:17:42.10#ibcon#about to read 6, iclass 37, count 2 2006.253.08:17:42.10#ibcon#read 6, iclass 37, count 2 2006.253.08:17:42.10#ibcon#end of sib2, iclass 37, count 2 2006.253.08:17:42.10#ibcon#*mode == 0, iclass 37, count 2 2006.253.08:17:42.10#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.253.08:17:42.10#ibcon#[27=AT05-04\r\n] 2006.253.08:17:42.10#ibcon#*before write, iclass 37, count 2 2006.253.08:17:42.10#ibcon#enter sib2, iclass 37, count 2 2006.253.08:17:42.10#ibcon#flushed, iclass 37, count 2 2006.253.08:17:42.10#ibcon#about to write, iclass 37, count 2 2006.253.08:17:42.10#ibcon#wrote, iclass 37, count 2 2006.253.08:17:42.10#ibcon#about to read 3, iclass 37, count 2 2006.253.08:17:42.13#ibcon#read 3, iclass 37, count 2 2006.253.08:17:42.13#ibcon#about to read 4, iclass 37, count 2 2006.253.08:17:42.13#ibcon#read 4, iclass 37, count 2 2006.253.08:17:42.13#ibcon#about to read 5, iclass 37, count 2 2006.253.08:17:42.13#ibcon#read 5, iclass 37, count 2 2006.253.08:17:42.13#ibcon#about to read 6, iclass 37, count 2 2006.253.08:17:42.13#ibcon#read 6, iclass 37, count 2 2006.253.08:17:42.13#ibcon#end of sib2, iclass 37, count 2 2006.253.08:17:42.13#ibcon#*after write, iclass 37, count 2 2006.253.08:17:42.13#ibcon#*before return 0, iclass 37, count 2 2006.253.08:17:42.13#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.253.08:17:42.13#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.253.08:17:42.13#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.253.08:17:42.13#ibcon#ireg 7 cls_cnt 0 2006.253.08:17:42.13#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.253.08:17:42.25#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.253.08:17:42.25#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.253.08:17:42.25#ibcon#enter wrdev, iclass 37, count 0 2006.253.08:17:42.25#ibcon#first serial, iclass 37, count 0 2006.253.08:17:42.25#ibcon#enter sib2, iclass 37, count 0 2006.253.08:17:42.25#ibcon#flushed, iclass 37, count 0 2006.253.08:17:42.25#ibcon#about to write, iclass 37, count 0 2006.253.08:17:42.25#ibcon#wrote, iclass 37, count 0 2006.253.08:17:42.25#ibcon#about to read 3, iclass 37, count 0 2006.253.08:17:42.27#ibcon#read 3, iclass 37, count 0 2006.253.08:17:42.27#ibcon#about to read 4, iclass 37, count 0 2006.253.08:17:42.27#ibcon#read 4, iclass 37, count 0 2006.253.08:17:42.27#ibcon#about to read 5, iclass 37, count 0 2006.253.08:17:42.27#ibcon#read 5, iclass 37, count 0 2006.253.08:17:42.27#ibcon#about to read 6, iclass 37, count 0 2006.253.08:17:42.27#ibcon#read 6, iclass 37, count 0 2006.253.08:17:42.27#ibcon#end of sib2, iclass 37, count 0 2006.253.08:17:42.27#ibcon#*mode == 0, iclass 37, count 0 2006.253.08:17:42.27#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.253.08:17:42.27#ibcon#[27=USB\r\n] 2006.253.08:17:42.27#ibcon#*before write, iclass 37, count 0 2006.253.08:17:42.27#ibcon#enter sib2, iclass 37, count 0 2006.253.08:17:42.27#ibcon#flushed, iclass 37, count 0 2006.253.08:17:42.27#ibcon#about to write, iclass 37, count 0 2006.253.08:17:42.27#ibcon#wrote, iclass 37, count 0 2006.253.08:17:42.27#ibcon#about to read 3, iclass 37, count 0 2006.253.08:17:42.30#ibcon#read 3, iclass 37, count 0 2006.253.08:17:42.30#ibcon#about to read 4, iclass 37, count 0 2006.253.08:17:42.30#ibcon#read 4, iclass 37, count 0 2006.253.08:17:42.30#ibcon#about to read 5, iclass 37, count 0 2006.253.08:17:42.30#ibcon#read 5, iclass 37, count 0 2006.253.08:17:42.30#ibcon#about to read 6, iclass 37, count 0 2006.253.08:17:42.30#ibcon#read 6, iclass 37, count 0 2006.253.08:17:42.30#ibcon#end of sib2, iclass 37, count 0 2006.253.08:17:42.30#ibcon#*after write, iclass 37, count 0 2006.253.08:17:42.30#ibcon#*before return 0, iclass 37, count 0 2006.253.08:17:42.30#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.253.08:17:42.30#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.253.08:17:42.30#ibcon#about to clear, iclass 37 cls_cnt 0 2006.253.08:17:42.30#ibcon#cleared, iclass 37 cls_cnt 0 2006.253.08:17:42.30$vc4f8/vblo=6,752.99 2006.253.08:17:42.30#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.253.08:17:42.30#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.253.08:17:42.30#ibcon#ireg 17 cls_cnt 0 2006.253.08:17:42.30#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.253.08:17:42.30#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.253.08:17:42.30#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.253.08:17:42.30#ibcon#enter wrdev, iclass 39, count 0 2006.253.08:17:42.30#ibcon#first serial, iclass 39, count 0 2006.253.08:17:42.30#ibcon#enter sib2, iclass 39, count 0 2006.253.08:17:42.30#ibcon#flushed, iclass 39, count 0 2006.253.08:17:42.30#ibcon#about to write, iclass 39, count 0 2006.253.08:17:42.30#ibcon#wrote, iclass 39, count 0 2006.253.08:17:42.30#ibcon#about to read 3, iclass 39, count 0 2006.253.08:17:42.32#ibcon#read 3, iclass 39, count 0 2006.253.08:17:42.32#ibcon#about to read 4, iclass 39, count 0 2006.253.08:17:42.32#ibcon#read 4, iclass 39, count 0 2006.253.08:17:42.32#ibcon#about to read 5, iclass 39, count 0 2006.253.08:17:42.32#ibcon#read 5, iclass 39, count 0 2006.253.08:17:42.32#ibcon#about to read 6, iclass 39, count 0 2006.253.08:17:42.32#ibcon#read 6, iclass 39, count 0 2006.253.08:17:42.32#ibcon#end of sib2, iclass 39, count 0 2006.253.08:17:42.32#ibcon#*mode == 0, iclass 39, count 0 2006.253.08:17:42.32#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.253.08:17:42.32#ibcon#[28=FRQ=06,752.99\r\n] 2006.253.08:17:42.32#ibcon#*before write, iclass 39, count 0 2006.253.08:17:42.32#ibcon#enter sib2, iclass 39, count 0 2006.253.08:17:42.32#ibcon#flushed, iclass 39, count 0 2006.253.08:17:42.32#ibcon#about to write, iclass 39, count 0 2006.253.08:17:42.32#ibcon#wrote, iclass 39, count 0 2006.253.08:17:42.32#ibcon#about to read 3, iclass 39, count 0 2006.253.08:17:42.36#ibcon#read 3, iclass 39, count 0 2006.253.08:17:42.36#ibcon#about to read 4, iclass 39, count 0 2006.253.08:17:42.36#ibcon#read 4, iclass 39, count 0 2006.253.08:17:42.36#ibcon#about to read 5, iclass 39, count 0 2006.253.08:17:42.36#ibcon#read 5, iclass 39, count 0 2006.253.08:17:42.36#ibcon#about to read 6, iclass 39, count 0 2006.253.08:17:42.36#ibcon#read 6, iclass 39, count 0 2006.253.08:17:42.36#ibcon#end of sib2, iclass 39, count 0 2006.253.08:17:42.36#ibcon#*after write, iclass 39, count 0 2006.253.08:17:42.36#ibcon#*before return 0, iclass 39, count 0 2006.253.08:17:42.36#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.253.08:17:42.36#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.253.08:17:42.36#ibcon#about to clear, iclass 39 cls_cnt 0 2006.253.08:17:42.36#ibcon#cleared, iclass 39 cls_cnt 0 2006.253.08:17:42.36$vc4f8/vb=6,4 2006.253.08:17:42.36#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.253.08:17:42.36#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.253.08:17:42.36#ibcon#ireg 11 cls_cnt 2 2006.253.08:17:42.36#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.253.08:17:42.42#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.253.08:17:42.42#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.253.08:17:42.42#ibcon#enter wrdev, iclass 3, count 2 2006.253.08:17:42.42#ibcon#first serial, iclass 3, count 2 2006.253.08:17:42.42#ibcon#enter sib2, iclass 3, count 2 2006.253.08:17:42.42#ibcon#flushed, iclass 3, count 2 2006.253.08:17:42.42#ibcon#about to write, iclass 3, count 2 2006.253.08:17:42.42#ibcon#wrote, iclass 3, count 2 2006.253.08:17:42.42#ibcon#about to read 3, iclass 3, count 2 2006.253.08:17:42.44#ibcon#read 3, iclass 3, count 2 2006.253.08:17:42.44#ibcon#about to read 4, iclass 3, count 2 2006.253.08:17:42.44#ibcon#read 4, iclass 3, count 2 2006.253.08:17:42.44#ibcon#about to read 5, iclass 3, count 2 2006.253.08:17:42.44#ibcon#read 5, iclass 3, count 2 2006.253.08:17:42.44#ibcon#about to read 6, iclass 3, count 2 2006.253.08:17:42.44#ibcon#read 6, iclass 3, count 2 2006.253.08:17:42.44#ibcon#end of sib2, iclass 3, count 2 2006.253.08:17:42.44#ibcon#*mode == 0, iclass 3, count 2 2006.253.08:17:42.44#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.253.08:17:42.44#ibcon#[27=AT06-04\r\n] 2006.253.08:17:42.44#ibcon#*before write, iclass 3, count 2 2006.253.08:17:42.44#ibcon#enter sib2, iclass 3, count 2 2006.253.08:17:42.44#ibcon#flushed, iclass 3, count 2 2006.253.08:17:42.44#ibcon#about to write, iclass 3, count 2 2006.253.08:17:42.44#ibcon#wrote, iclass 3, count 2 2006.253.08:17:42.44#ibcon#about to read 3, iclass 3, count 2 2006.253.08:17:42.47#ibcon#read 3, iclass 3, count 2 2006.253.08:17:42.47#ibcon#about to read 4, iclass 3, count 2 2006.253.08:17:42.47#ibcon#read 4, iclass 3, count 2 2006.253.08:17:42.47#ibcon#about to read 5, iclass 3, count 2 2006.253.08:17:42.47#ibcon#read 5, iclass 3, count 2 2006.253.08:17:42.47#ibcon#about to read 6, iclass 3, count 2 2006.253.08:17:42.47#ibcon#read 6, iclass 3, count 2 2006.253.08:17:42.47#ibcon#end of sib2, iclass 3, count 2 2006.253.08:17:42.47#ibcon#*after write, iclass 3, count 2 2006.253.08:17:42.47#ibcon#*before return 0, iclass 3, count 2 2006.253.08:17:42.47#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.253.08:17:42.47#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.253.08:17:42.47#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.253.08:17:42.47#ibcon#ireg 7 cls_cnt 0 2006.253.08:17:42.47#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.253.08:17:42.59#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.253.08:17:42.59#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.253.08:17:42.59#ibcon#enter wrdev, iclass 3, count 0 2006.253.08:17:42.59#ibcon#first serial, iclass 3, count 0 2006.253.08:17:42.59#ibcon#enter sib2, iclass 3, count 0 2006.253.08:17:42.59#ibcon#flushed, iclass 3, count 0 2006.253.08:17:42.59#ibcon#about to write, iclass 3, count 0 2006.253.08:17:42.59#ibcon#wrote, iclass 3, count 0 2006.253.08:17:42.59#ibcon#about to read 3, iclass 3, count 0 2006.253.08:17:42.61#ibcon#read 3, iclass 3, count 0 2006.253.08:17:42.61#ibcon#about to read 4, iclass 3, count 0 2006.253.08:17:42.61#ibcon#read 4, iclass 3, count 0 2006.253.08:17:42.61#ibcon#about to read 5, iclass 3, count 0 2006.253.08:17:42.61#ibcon#read 5, iclass 3, count 0 2006.253.08:17:42.61#ibcon#about to read 6, iclass 3, count 0 2006.253.08:17:42.61#ibcon#read 6, iclass 3, count 0 2006.253.08:17:42.61#ibcon#end of sib2, iclass 3, count 0 2006.253.08:17:42.61#ibcon#*mode == 0, iclass 3, count 0 2006.253.08:17:42.61#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.253.08:17:42.61#ibcon#[27=USB\r\n] 2006.253.08:17:42.61#ibcon#*before write, iclass 3, count 0 2006.253.08:17:42.61#ibcon#enter sib2, iclass 3, count 0 2006.253.08:17:42.61#ibcon#flushed, iclass 3, count 0 2006.253.08:17:42.61#ibcon#about to write, iclass 3, count 0 2006.253.08:17:42.61#ibcon#wrote, iclass 3, count 0 2006.253.08:17:42.61#ibcon#about to read 3, iclass 3, count 0 2006.253.08:17:42.64#ibcon#read 3, iclass 3, count 0 2006.253.08:17:42.64#ibcon#about to read 4, iclass 3, count 0 2006.253.08:17:42.64#ibcon#read 4, iclass 3, count 0 2006.253.08:17:42.64#ibcon#about to read 5, iclass 3, count 0 2006.253.08:17:42.64#ibcon#read 5, iclass 3, count 0 2006.253.08:17:42.64#ibcon#about to read 6, iclass 3, count 0 2006.253.08:17:42.64#ibcon#read 6, iclass 3, count 0 2006.253.08:17:42.64#ibcon#end of sib2, iclass 3, count 0 2006.253.08:17:42.64#ibcon#*after write, iclass 3, count 0 2006.253.08:17:42.64#ibcon#*before return 0, iclass 3, count 0 2006.253.08:17:42.64#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.253.08:17:42.64#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.253.08:17:42.64#ibcon#about to clear, iclass 3 cls_cnt 0 2006.253.08:17:42.64#ibcon#cleared, iclass 3 cls_cnt 0 2006.253.08:17:42.64$vc4f8/vabw=wide 2006.253.08:17:42.64#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.253.08:17:42.64#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.253.08:17:42.64#ibcon#ireg 8 cls_cnt 0 2006.253.08:17:42.64#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.253.08:17:42.64#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.253.08:17:42.64#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.253.08:17:42.64#ibcon#enter wrdev, iclass 5, count 0 2006.253.08:17:42.64#ibcon#first serial, iclass 5, count 0 2006.253.08:17:42.64#ibcon#enter sib2, iclass 5, count 0 2006.253.08:17:42.64#ibcon#flushed, iclass 5, count 0 2006.253.08:17:42.64#ibcon#about to write, iclass 5, count 0 2006.253.08:17:42.64#ibcon#wrote, iclass 5, count 0 2006.253.08:17:42.64#ibcon#about to read 3, iclass 5, count 0 2006.253.08:17:42.66#ibcon#read 3, iclass 5, count 0 2006.253.08:17:42.66#ibcon#about to read 4, iclass 5, count 0 2006.253.08:17:42.66#ibcon#read 4, iclass 5, count 0 2006.253.08:17:42.66#ibcon#about to read 5, iclass 5, count 0 2006.253.08:17:42.66#ibcon#read 5, iclass 5, count 0 2006.253.08:17:42.66#ibcon#about to read 6, iclass 5, count 0 2006.253.08:17:42.66#ibcon#read 6, iclass 5, count 0 2006.253.08:17:42.66#ibcon#end of sib2, iclass 5, count 0 2006.253.08:17:42.66#ibcon#*mode == 0, iclass 5, count 0 2006.253.08:17:42.66#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.253.08:17:42.66#ibcon#[25=BW32\r\n] 2006.253.08:17:42.66#ibcon#*before write, iclass 5, count 0 2006.253.08:17:42.66#ibcon#enter sib2, iclass 5, count 0 2006.253.08:17:42.66#ibcon#flushed, iclass 5, count 0 2006.253.08:17:42.66#ibcon#about to write, iclass 5, count 0 2006.253.08:17:42.66#ibcon#wrote, iclass 5, count 0 2006.253.08:17:42.66#ibcon#about to read 3, iclass 5, count 0 2006.253.08:17:42.69#ibcon#read 3, iclass 5, count 0 2006.253.08:17:42.69#ibcon#about to read 4, iclass 5, count 0 2006.253.08:17:42.69#ibcon#read 4, iclass 5, count 0 2006.253.08:17:42.69#ibcon#about to read 5, iclass 5, count 0 2006.253.08:17:42.69#ibcon#read 5, iclass 5, count 0 2006.253.08:17:42.69#ibcon#about to read 6, iclass 5, count 0 2006.253.08:17:42.69#ibcon#read 6, iclass 5, count 0 2006.253.08:17:42.69#ibcon#end of sib2, iclass 5, count 0 2006.253.08:17:42.69#ibcon#*after write, iclass 5, count 0 2006.253.08:17:42.69#ibcon#*before return 0, iclass 5, count 0 2006.253.08:17:42.69#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.253.08:17:42.69#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.253.08:17:42.69#ibcon#about to clear, iclass 5 cls_cnt 0 2006.253.08:17:42.69#ibcon#cleared, iclass 5 cls_cnt 0 2006.253.08:17:42.69$vc4f8/vbbw=wide 2006.253.08:17:42.69#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.253.08:17:42.69#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.253.08:17:42.69#ibcon#ireg 8 cls_cnt 0 2006.253.08:17:42.69#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.253.08:17:42.76#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.253.08:17:42.76#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.253.08:17:42.76#ibcon#enter wrdev, iclass 7, count 0 2006.253.08:17:42.76#ibcon#first serial, iclass 7, count 0 2006.253.08:17:42.76#ibcon#enter sib2, iclass 7, count 0 2006.253.08:17:42.76#ibcon#flushed, iclass 7, count 0 2006.253.08:17:42.76#ibcon#about to write, iclass 7, count 0 2006.253.08:17:42.76#ibcon#wrote, iclass 7, count 0 2006.253.08:17:42.76#ibcon#about to read 3, iclass 7, count 0 2006.253.08:17:42.78#ibcon#read 3, iclass 7, count 0 2006.253.08:17:42.78#ibcon#about to read 4, iclass 7, count 0 2006.253.08:17:42.78#ibcon#read 4, iclass 7, count 0 2006.253.08:17:42.78#ibcon#about to read 5, iclass 7, count 0 2006.253.08:17:42.78#ibcon#read 5, iclass 7, count 0 2006.253.08:17:42.78#ibcon#about to read 6, iclass 7, count 0 2006.253.08:17:42.78#ibcon#read 6, iclass 7, count 0 2006.253.08:17:42.78#ibcon#end of sib2, iclass 7, count 0 2006.253.08:17:42.78#ibcon#*mode == 0, iclass 7, count 0 2006.253.08:17:42.78#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.253.08:17:42.78#ibcon#[27=BW32\r\n] 2006.253.08:17:42.78#ibcon#*before write, iclass 7, count 0 2006.253.08:17:42.78#ibcon#enter sib2, iclass 7, count 0 2006.253.08:17:42.78#ibcon#flushed, iclass 7, count 0 2006.253.08:17:42.78#ibcon#about to write, iclass 7, count 0 2006.253.08:17:42.78#ibcon#wrote, iclass 7, count 0 2006.253.08:17:42.78#ibcon#about to read 3, iclass 7, count 0 2006.253.08:17:42.81#ibcon#read 3, iclass 7, count 0 2006.253.08:17:42.81#ibcon#about to read 4, iclass 7, count 0 2006.253.08:17:42.81#ibcon#read 4, iclass 7, count 0 2006.253.08:17:42.81#ibcon#about to read 5, iclass 7, count 0 2006.253.08:17:42.81#ibcon#read 5, iclass 7, count 0 2006.253.08:17:42.81#ibcon#about to read 6, iclass 7, count 0 2006.253.08:17:42.81#ibcon#read 6, iclass 7, count 0 2006.253.08:17:42.81#ibcon#end of sib2, iclass 7, count 0 2006.253.08:17:42.81#ibcon#*after write, iclass 7, count 0 2006.253.08:17:42.81#ibcon#*before return 0, iclass 7, count 0 2006.253.08:17:42.81#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.253.08:17:42.81#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.253.08:17:42.81#ibcon#about to clear, iclass 7 cls_cnt 0 2006.253.08:17:42.81#ibcon#cleared, iclass 7 cls_cnt 0 2006.253.08:17:42.81$4f8m12a/ifd4f 2006.253.08:17:42.81$ifd4f/lo= 2006.253.08:17:42.81$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.253.08:17:42.81$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.253.08:17:42.81$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.253.08:17:42.81$ifd4f/patch= 2006.253.08:17:42.81$ifd4f/patch=lo1,a1,a2,a3,a4 2006.253.08:17:42.81$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.253.08:17:42.81$ifd4f/patch=lo3,a5,a6,a7,a8 2006.253.08:17:42.81$4f8m12a/"form=m,16.000,1:2 2006.253.08:17:42.81$4f8m12a/"tpicd 2006.253.08:17:42.81$4f8m12a/echo=off 2006.253.08:17:42.81$4f8m12a/xlog=off 2006.253.08:17:42.81:!2006.253.08:18:10 2006.253.08:17:47.14#trakl#Source acquired 2006.253.08:17:49.14#flagr#flagr/antenna,acquired 2006.253.08:18:10.00:preob 2006.253.08:18:11.14/onsource/TRACKING 2006.253.08:18:11.14:!2006.253.08:18:20 2006.253.08:18:20.00:data_valid=on 2006.253.08:18:20.00:midob 2006.253.08:18:20.14/onsource/TRACKING 2006.253.08:18:20.14/wx/30.85,1006.6,75 2006.253.08:18:20.20/cable/+6.3670E-03 2006.253.08:18:21.29/va/01,08,usb,yes,33,34 2006.253.08:18:21.29/va/02,07,usb,yes,32,34 2006.253.08:18:21.29/va/03,06,usb,yes,35,35 2006.253.08:18:21.29/va/04,07,usb,yes,33,36 2006.253.08:18:21.29/va/05,07,usb,yes,35,37 2006.253.08:18:21.29/va/06,07,usb,yes,30,30 2006.253.08:18:21.29/va/07,07,usb,yes,30,30 2006.253.08:18:21.29/va/08,07,usb,yes,32,32 2006.253.08:18:21.52/valo/01,532.99,yes,locked 2006.253.08:18:21.52/valo/02,572.99,yes,locked 2006.253.08:18:21.52/valo/03,672.99,yes,locked 2006.253.08:18:21.52/valo/04,832.99,yes,locked 2006.253.08:18:21.52/valo/05,652.99,yes,locked 2006.253.08:18:21.52/valo/06,772.99,yes,locked 2006.253.08:18:21.52/valo/07,832.99,yes,locked 2006.253.08:18:21.52/valo/08,852.99,yes,locked 2006.253.08:18:22.61/vb/01,04,usb,yes,31,30 2006.253.08:18:22.61/vb/02,05,usb,yes,29,30 2006.253.08:18:22.61/vb/03,04,usb,yes,29,33 2006.253.08:18:22.61/vb/04,04,usb,yes,30,30 2006.253.08:18:22.61/vb/05,04,usb,yes,28,33 2006.253.08:18:22.61/vb/06,04,usb,yes,29,32 2006.253.08:18:22.61/vb/07,04,usb,yes,32,32 2006.253.08:18:22.61/vb/08,04,usb,yes,29,33 2006.253.08:18:22.84/vblo/01,632.99,yes,locked 2006.253.08:18:22.84/vblo/02,640.99,yes,locked 2006.253.08:18:22.84/vblo/03,656.99,yes,locked 2006.253.08:18:22.84/vblo/04,712.99,yes,locked 2006.253.08:18:22.84/vblo/05,744.99,yes,locked 2006.253.08:18:22.84/vblo/06,752.99,yes,locked 2006.253.08:18:22.84/vblo/07,734.99,yes,locked 2006.253.08:18:22.84/vblo/08,744.99,yes,locked 2006.253.08:18:22.99/vabw/8 2006.253.08:18:23.14/vbbw/8 2006.253.08:18:23.23/xfe/off,on,14.2 2006.253.08:18:23.60/ifatt/23,28,28,28 2006.253.08:18:24.08/fmout-gps/S +4.71E-07 2006.253.08:18:24.12:!2006.253.08:19:20 2006.253.08:19:20.02:data_valid=off 2006.253.08:19:20.02:postob 2006.253.08:19:20.24/cable/+6.3679E-03 2006.253.08:19:20.24/wx/30.83,1006.6,75 2006.253.08:19:21.08/fmout-gps/S +4.72E-07 2006.253.08:19:21.08:scan_name=253-0821,k06253,60 2006.253.08:19:21.08:source=1803+784,180045.68,782804.0,2000.0,neutral 2006.253.08:19:21.14#flagr#flagr/antenna,new-source 2006.253.08:19:22.14:checkk5 2006.253.08:19:22.52/chk_autoobs//k5ts1/ autoobs is running! 2006.253.08:19:22.90/chk_autoobs//k5ts2/ autoobs is running! 2006.253.08:19:23.27/chk_autoobs//k5ts3/ autoobs is running! 2006.253.08:19:23.65/chk_autoobs//k5ts4/ autoobs is running! 2006.253.08:19:24.01/chk_obsdata//k5ts1/T2530818??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.08:19:24.38/chk_obsdata//k5ts2/T2530818??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.08:19:24.75/chk_obsdata//k5ts3/T2530818??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.08:19:25.12/chk_obsdata//k5ts4/T2530818??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.08:19:25.82/k5log//k5ts1_log_newline 2006.253.08:19:26.52/k5log//k5ts2_log_newline 2006.253.08:19:27.20/k5log//k5ts3_log_newline 2006.253.08:19:27.89/k5log//k5ts4_log_newline 2006.253.08:19:27.91/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.253.08:19:27.91:4f8m12a=3 2006.253.08:19:27.91$4f8m12a/echo=on 2006.253.08:19:27.91$4f8m12a/pcalon 2006.253.08:19:27.92$pcalon/"no phase cal control is implemented here 2006.253.08:19:27.92$4f8m12a/"tpicd=stop 2006.253.08:19:27.92$4f8m12a/vc4f8 2006.253.08:19:27.92$vc4f8/valo=1,532.99 2006.253.08:19:27.92#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.253.08:19:27.92#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.253.08:19:27.92#ibcon#ireg 17 cls_cnt 0 2006.253.08:19:27.92#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.253.08:19:27.92#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.253.08:19:27.92#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.253.08:19:27.92#ibcon#enter wrdev, iclass 16, count 0 2006.253.08:19:27.92#ibcon#first serial, iclass 16, count 0 2006.253.08:19:27.92#ibcon#enter sib2, iclass 16, count 0 2006.253.08:19:27.92#ibcon#flushed, iclass 16, count 0 2006.253.08:19:27.92#ibcon#about to write, iclass 16, count 0 2006.253.08:19:27.92#ibcon#wrote, iclass 16, count 0 2006.253.08:19:27.92#ibcon#about to read 3, iclass 16, count 0 2006.253.08:19:27.96#ibcon#read 3, iclass 16, count 0 2006.253.08:19:27.96#ibcon#about to read 4, iclass 16, count 0 2006.253.08:19:27.96#ibcon#read 4, iclass 16, count 0 2006.253.08:19:27.96#ibcon#about to read 5, iclass 16, count 0 2006.253.08:19:27.96#ibcon#read 5, iclass 16, count 0 2006.253.08:19:27.96#ibcon#about to read 6, iclass 16, count 0 2006.253.08:19:27.96#ibcon#read 6, iclass 16, count 0 2006.253.08:19:27.96#ibcon#end of sib2, iclass 16, count 0 2006.253.08:19:27.96#ibcon#*mode == 0, iclass 16, count 0 2006.253.08:19:27.96#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.253.08:19:27.96#ibcon#[26=FRQ=01,532.99\r\n] 2006.253.08:19:27.96#ibcon#*before write, iclass 16, count 0 2006.253.08:19:27.96#ibcon#enter sib2, iclass 16, count 0 2006.253.08:19:27.96#ibcon#flushed, iclass 16, count 0 2006.253.08:19:27.96#ibcon#about to write, iclass 16, count 0 2006.253.08:19:27.96#ibcon#wrote, iclass 16, count 0 2006.253.08:19:27.96#ibcon#about to read 3, iclass 16, count 0 2006.253.08:19:28.00#ibcon#read 3, iclass 16, count 0 2006.253.08:19:28.00#ibcon#about to read 4, iclass 16, count 0 2006.253.08:19:28.00#ibcon#read 4, iclass 16, count 0 2006.253.08:19:28.01#ibcon#about to read 5, iclass 16, count 0 2006.253.08:19:28.01#ibcon#read 5, iclass 16, count 0 2006.253.08:19:28.01#ibcon#about to read 6, iclass 16, count 0 2006.253.08:19:28.01#ibcon#read 6, iclass 16, count 0 2006.253.08:19:28.01#ibcon#end of sib2, iclass 16, count 0 2006.253.08:19:28.01#ibcon#*after write, iclass 16, count 0 2006.253.08:19:28.01#ibcon#*before return 0, iclass 16, count 0 2006.253.08:19:28.01#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.253.08:19:28.01#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.253.08:19:28.01#ibcon#about to clear, iclass 16 cls_cnt 0 2006.253.08:19:28.01#ibcon#cleared, iclass 16 cls_cnt 0 2006.253.08:19:28.01$vc4f8/va=1,8 2006.253.08:19:28.01#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.253.08:19:28.01#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.253.08:19:28.01#ibcon#ireg 11 cls_cnt 2 2006.253.08:19:28.01#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.253.08:19:28.01#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.253.08:19:28.01#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.253.08:19:28.01#ibcon#enter wrdev, iclass 18, count 2 2006.253.08:19:28.01#ibcon#first serial, iclass 18, count 2 2006.253.08:19:28.01#ibcon#enter sib2, iclass 18, count 2 2006.253.08:19:28.01#ibcon#flushed, iclass 18, count 2 2006.253.08:19:28.01#ibcon#about to write, iclass 18, count 2 2006.253.08:19:28.01#ibcon#wrote, iclass 18, count 2 2006.253.08:19:28.01#ibcon#about to read 3, iclass 18, count 2 2006.253.08:19:28.03#ibcon#read 3, iclass 18, count 2 2006.253.08:19:28.03#ibcon#about to read 4, iclass 18, count 2 2006.253.08:19:28.03#ibcon#read 4, iclass 18, count 2 2006.253.08:19:28.03#ibcon#about to read 5, iclass 18, count 2 2006.253.08:19:28.03#ibcon#read 5, iclass 18, count 2 2006.253.08:19:28.03#ibcon#about to read 6, iclass 18, count 2 2006.253.08:19:28.03#ibcon#read 6, iclass 18, count 2 2006.253.08:19:28.03#ibcon#end of sib2, iclass 18, count 2 2006.253.08:19:28.03#ibcon#*mode == 0, iclass 18, count 2 2006.253.08:19:28.03#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.253.08:19:28.03#ibcon#[25=AT01-08\r\n] 2006.253.08:19:28.03#ibcon#*before write, iclass 18, count 2 2006.253.08:19:28.03#ibcon#enter sib2, iclass 18, count 2 2006.253.08:19:28.03#ibcon#flushed, iclass 18, count 2 2006.253.08:19:28.03#ibcon#about to write, iclass 18, count 2 2006.253.08:19:28.03#ibcon#wrote, iclass 18, count 2 2006.253.08:19:28.03#ibcon#about to read 3, iclass 18, count 2 2006.253.08:19:28.06#ibcon#read 3, iclass 18, count 2 2006.253.08:19:28.06#ibcon#about to read 4, iclass 18, count 2 2006.253.08:19:28.06#ibcon#read 4, iclass 18, count 2 2006.253.08:19:28.06#ibcon#about to read 5, iclass 18, count 2 2006.253.08:19:28.06#ibcon#read 5, iclass 18, count 2 2006.253.08:19:28.06#ibcon#about to read 6, iclass 18, count 2 2006.253.08:19:28.06#ibcon#read 6, iclass 18, count 2 2006.253.08:19:28.06#ibcon#end of sib2, iclass 18, count 2 2006.253.08:19:28.06#ibcon#*after write, iclass 18, count 2 2006.253.08:19:28.06#ibcon#*before return 0, iclass 18, count 2 2006.253.08:19:28.06#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.253.08:19:28.06#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.253.08:19:28.06#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.253.08:19:28.06#ibcon#ireg 7 cls_cnt 0 2006.253.08:19:28.06#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.253.08:19:28.17#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.253.08:19:28.17#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.253.08:19:28.17#ibcon#enter wrdev, iclass 18, count 0 2006.253.08:19:28.17#ibcon#first serial, iclass 18, count 0 2006.253.08:19:28.18#ibcon#enter sib2, iclass 18, count 0 2006.253.08:19:28.18#ibcon#flushed, iclass 18, count 0 2006.253.08:19:28.18#ibcon#about to write, iclass 18, count 0 2006.253.08:19:28.18#ibcon#wrote, iclass 18, count 0 2006.253.08:19:28.18#ibcon#about to read 3, iclass 18, count 0 2006.253.08:19:28.19#ibcon#read 3, iclass 18, count 0 2006.253.08:19:28.19#ibcon#about to read 4, iclass 18, count 0 2006.253.08:19:28.19#ibcon#read 4, iclass 18, count 0 2006.253.08:19:28.19#ibcon#about to read 5, iclass 18, count 0 2006.253.08:19:28.20#ibcon#read 5, iclass 18, count 0 2006.253.08:19:28.20#ibcon#about to read 6, iclass 18, count 0 2006.253.08:19:28.20#ibcon#read 6, iclass 18, count 0 2006.253.08:19:28.20#ibcon#end of sib2, iclass 18, count 0 2006.253.08:19:28.20#ibcon#*mode == 0, iclass 18, count 0 2006.253.08:19:28.20#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.253.08:19:28.20#ibcon#[25=USB\r\n] 2006.253.08:19:28.20#ibcon#*before write, iclass 18, count 0 2006.253.08:19:28.20#ibcon#enter sib2, iclass 18, count 0 2006.253.08:19:28.20#ibcon#flushed, iclass 18, count 0 2006.253.08:19:28.20#ibcon#about to write, iclass 18, count 0 2006.253.08:19:28.20#ibcon#wrote, iclass 18, count 0 2006.253.08:19:28.20#ibcon#about to read 3, iclass 18, count 0 2006.253.08:19:28.23#ibcon#read 3, iclass 18, count 0 2006.253.08:19:28.23#ibcon#about to read 4, iclass 18, count 0 2006.253.08:19:28.23#ibcon#read 4, iclass 18, count 0 2006.253.08:19:28.23#ibcon#about to read 5, iclass 18, count 0 2006.253.08:19:28.23#ibcon#read 5, iclass 18, count 0 2006.253.08:19:28.23#ibcon#about to read 6, iclass 18, count 0 2006.253.08:19:28.23#ibcon#read 6, iclass 18, count 0 2006.253.08:19:28.23#ibcon#end of sib2, iclass 18, count 0 2006.253.08:19:28.23#ibcon#*after write, iclass 18, count 0 2006.253.08:19:28.23#ibcon#*before return 0, iclass 18, count 0 2006.253.08:19:28.23#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.253.08:19:28.23#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.253.08:19:28.23#ibcon#about to clear, iclass 18 cls_cnt 0 2006.253.08:19:28.23#ibcon#cleared, iclass 18 cls_cnt 0 2006.253.08:19:28.23$vc4f8/valo=2,572.99 2006.253.08:19:28.23#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.253.08:19:28.23#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.253.08:19:28.23#ibcon#ireg 17 cls_cnt 0 2006.253.08:19:28.23#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.253.08:19:28.23#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.253.08:19:28.23#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.253.08:19:28.23#ibcon#enter wrdev, iclass 20, count 0 2006.253.08:19:28.23#ibcon#first serial, iclass 20, count 0 2006.253.08:19:28.23#ibcon#enter sib2, iclass 20, count 0 2006.253.08:19:28.23#ibcon#flushed, iclass 20, count 0 2006.253.08:19:28.23#ibcon#about to write, iclass 20, count 0 2006.253.08:19:28.23#ibcon#wrote, iclass 20, count 0 2006.253.08:19:28.23#ibcon#about to read 3, iclass 20, count 0 2006.253.08:19:28.25#ibcon#read 3, iclass 20, count 0 2006.253.08:19:28.25#ibcon#about to read 4, iclass 20, count 0 2006.253.08:19:28.25#ibcon#read 4, iclass 20, count 0 2006.253.08:19:28.25#ibcon#about to read 5, iclass 20, count 0 2006.253.08:19:28.25#ibcon#read 5, iclass 20, count 0 2006.253.08:19:28.25#ibcon#about to read 6, iclass 20, count 0 2006.253.08:19:28.25#ibcon#read 6, iclass 20, count 0 2006.253.08:19:28.25#ibcon#end of sib2, iclass 20, count 0 2006.253.08:19:28.25#ibcon#*mode == 0, iclass 20, count 0 2006.253.08:19:28.25#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.253.08:19:28.25#ibcon#[26=FRQ=02,572.99\r\n] 2006.253.08:19:28.25#ibcon#*before write, iclass 20, count 0 2006.253.08:19:28.25#ibcon#enter sib2, iclass 20, count 0 2006.253.08:19:28.25#ibcon#flushed, iclass 20, count 0 2006.253.08:19:28.25#ibcon#about to write, iclass 20, count 0 2006.253.08:19:28.25#ibcon#wrote, iclass 20, count 0 2006.253.08:19:28.25#ibcon#about to read 3, iclass 20, count 0 2006.253.08:19:28.28#ibcon#read 3, iclass 20, count 0 2006.253.08:19:28.28#ibcon#about to read 4, iclass 20, count 0 2006.253.08:19:28.29#ibcon#read 4, iclass 20, count 0 2006.253.08:19:28.29#ibcon#about to read 5, iclass 20, count 0 2006.253.08:19:28.29#ibcon#read 5, iclass 20, count 0 2006.253.08:19:28.29#ibcon#about to read 6, iclass 20, count 0 2006.253.08:19:28.29#ibcon#read 6, iclass 20, count 0 2006.253.08:19:28.29#ibcon#end of sib2, iclass 20, count 0 2006.253.08:19:28.29#ibcon#*after write, iclass 20, count 0 2006.253.08:19:28.29#ibcon#*before return 0, iclass 20, count 0 2006.253.08:19:28.29#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.253.08:19:28.29#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.253.08:19:28.29#ibcon#about to clear, iclass 20 cls_cnt 0 2006.253.08:19:28.29#ibcon#cleared, iclass 20 cls_cnt 0 2006.253.08:19:28.29$vc4f8/va=2,7 2006.253.08:19:28.29#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.253.08:19:28.29#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.253.08:19:28.29#ibcon#ireg 11 cls_cnt 2 2006.253.08:19:28.29#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.253.08:19:28.35#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.253.08:19:28.35#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.253.08:19:28.35#ibcon#enter wrdev, iclass 22, count 2 2006.253.08:19:28.35#ibcon#first serial, iclass 22, count 2 2006.253.08:19:28.35#ibcon#enter sib2, iclass 22, count 2 2006.253.08:19:28.35#ibcon#flushed, iclass 22, count 2 2006.253.08:19:28.35#ibcon#about to write, iclass 22, count 2 2006.253.08:19:28.35#ibcon#wrote, iclass 22, count 2 2006.253.08:19:28.35#ibcon#about to read 3, iclass 22, count 2 2006.253.08:19:28.37#ibcon#read 3, iclass 22, count 2 2006.253.08:19:28.37#ibcon#about to read 4, iclass 22, count 2 2006.253.08:19:28.37#ibcon#read 4, iclass 22, count 2 2006.253.08:19:28.37#ibcon#about to read 5, iclass 22, count 2 2006.253.08:19:28.37#ibcon#read 5, iclass 22, count 2 2006.253.08:19:28.37#ibcon#about to read 6, iclass 22, count 2 2006.253.08:19:28.37#ibcon#read 6, iclass 22, count 2 2006.253.08:19:28.37#ibcon#end of sib2, iclass 22, count 2 2006.253.08:19:28.37#ibcon#*mode == 0, iclass 22, count 2 2006.253.08:19:28.37#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.253.08:19:28.37#ibcon#[25=AT02-07\r\n] 2006.253.08:19:28.37#ibcon#*before write, iclass 22, count 2 2006.253.08:19:28.37#ibcon#enter sib2, iclass 22, count 2 2006.253.08:19:28.37#ibcon#flushed, iclass 22, count 2 2006.253.08:19:28.37#ibcon#about to write, iclass 22, count 2 2006.253.08:19:28.37#ibcon#wrote, iclass 22, count 2 2006.253.08:19:28.37#ibcon#about to read 3, iclass 22, count 2 2006.253.08:19:28.39#ibcon#read 3, iclass 22, count 2 2006.253.08:19:28.39#ibcon#about to read 4, iclass 22, count 2 2006.253.08:19:28.39#ibcon#read 4, iclass 22, count 2 2006.253.08:19:28.39#ibcon#about to read 5, iclass 22, count 2 2006.253.08:19:28.40#ibcon#read 5, iclass 22, count 2 2006.253.08:19:28.40#ibcon#about to read 6, iclass 22, count 2 2006.253.08:19:28.40#ibcon#read 6, iclass 22, count 2 2006.253.08:19:28.40#ibcon#end of sib2, iclass 22, count 2 2006.253.08:19:28.40#ibcon#*after write, iclass 22, count 2 2006.253.08:19:28.40#ibcon#*before return 0, iclass 22, count 2 2006.253.08:19:28.40#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.253.08:19:28.40#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.253.08:19:28.40#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.253.08:19:28.40#ibcon#ireg 7 cls_cnt 0 2006.253.08:19:28.40#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.253.08:19:28.51#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.253.08:19:28.51#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.253.08:19:28.51#ibcon#enter wrdev, iclass 22, count 0 2006.253.08:19:28.51#ibcon#first serial, iclass 22, count 0 2006.253.08:19:28.51#ibcon#enter sib2, iclass 22, count 0 2006.253.08:19:28.52#ibcon#flushed, iclass 22, count 0 2006.253.08:19:28.52#ibcon#about to write, iclass 22, count 0 2006.253.08:19:28.52#ibcon#wrote, iclass 22, count 0 2006.253.08:19:28.52#ibcon#about to read 3, iclass 22, count 0 2006.253.08:19:28.53#ibcon#read 3, iclass 22, count 0 2006.253.08:19:28.53#ibcon#about to read 4, iclass 22, count 0 2006.253.08:19:28.53#ibcon#read 4, iclass 22, count 0 2006.253.08:19:28.53#ibcon#about to read 5, iclass 22, count 0 2006.253.08:19:28.54#ibcon#read 5, iclass 22, count 0 2006.253.08:19:28.54#ibcon#about to read 6, iclass 22, count 0 2006.253.08:19:28.54#ibcon#read 6, iclass 22, count 0 2006.253.08:19:28.54#ibcon#end of sib2, iclass 22, count 0 2006.253.08:19:28.54#ibcon#*mode == 0, iclass 22, count 0 2006.253.08:19:28.54#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.253.08:19:28.54#ibcon#[25=USB\r\n] 2006.253.08:19:28.54#ibcon#*before write, iclass 22, count 0 2006.253.08:19:28.54#ibcon#enter sib2, iclass 22, count 0 2006.253.08:19:28.54#ibcon#flushed, iclass 22, count 0 2006.253.08:19:28.54#ibcon#about to write, iclass 22, count 0 2006.253.08:19:28.54#ibcon#wrote, iclass 22, count 0 2006.253.08:19:28.54#ibcon#about to read 3, iclass 22, count 0 2006.253.08:19:28.56#ibcon#read 3, iclass 22, count 0 2006.253.08:19:28.56#ibcon#about to read 4, iclass 22, count 0 2006.253.08:19:28.56#ibcon#read 4, iclass 22, count 0 2006.253.08:19:28.56#ibcon#about to read 5, iclass 22, count 0 2006.253.08:19:28.57#ibcon#read 5, iclass 22, count 0 2006.253.08:19:28.57#ibcon#about to read 6, iclass 22, count 0 2006.253.08:19:28.57#ibcon#read 6, iclass 22, count 0 2006.253.08:19:28.57#ibcon#end of sib2, iclass 22, count 0 2006.253.08:19:28.57#ibcon#*after write, iclass 22, count 0 2006.253.08:19:28.57#ibcon#*before return 0, iclass 22, count 0 2006.253.08:19:28.57#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.253.08:19:28.57#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.253.08:19:28.57#ibcon#about to clear, iclass 22 cls_cnt 0 2006.253.08:19:28.57#ibcon#cleared, iclass 22 cls_cnt 0 2006.253.08:19:28.57$vc4f8/valo=3,672.99 2006.253.08:19:28.57#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.253.08:19:28.57#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.253.08:19:28.57#ibcon#ireg 17 cls_cnt 0 2006.253.08:19:28.57#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.253.08:19:28.57#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.253.08:19:28.57#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.253.08:19:28.57#ibcon#enter wrdev, iclass 24, count 0 2006.253.08:19:28.57#ibcon#first serial, iclass 24, count 0 2006.253.08:19:28.57#ibcon#enter sib2, iclass 24, count 0 2006.253.08:19:28.57#ibcon#flushed, iclass 24, count 0 2006.253.08:19:28.57#ibcon#about to write, iclass 24, count 0 2006.253.08:19:28.57#ibcon#wrote, iclass 24, count 0 2006.253.08:19:28.57#ibcon#about to read 3, iclass 24, count 0 2006.253.08:19:28.59#ibcon#read 3, iclass 24, count 0 2006.253.08:19:28.59#ibcon#about to read 4, iclass 24, count 0 2006.253.08:19:28.59#ibcon#read 4, iclass 24, count 0 2006.253.08:19:28.59#ibcon#about to read 5, iclass 24, count 0 2006.253.08:19:28.59#ibcon#read 5, iclass 24, count 0 2006.253.08:19:28.59#ibcon#about to read 6, iclass 24, count 0 2006.253.08:19:28.59#ibcon#read 6, iclass 24, count 0 2006.253.08:19:28.59#ibcon#end of sib2, iclass 24, count 0 2006.253.08:19:28.59#ibcon#*mode == 0, iclass 24, count 0 2006.253.08:19:28.59#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.253.08:19:28.59#ibcon#[26=FRQ=03,672.99\r\n] 2006.253.08:19:28.59#ibcon#*before write, iclass 24, count 0 2006.253.08:19:28.59#ibcon#enter sib2, iclass 24, count 0 2006.253.08:19:28.59#ibcon#flushed, iclass 24, count 0 2006.253.08:19:28.59#ibcon#about to write, iclass 24, count 0 2006.253.08:19:28.59#ibcon#wrote, iclass 24, count 0 2006.253.08:19:28.59#ibcon#about to read 3, iclass 24, count 0 2006.253.08:19:28.63#ibcon#read 3, iclass 24, count 0 2006.253.08:19:28.64#ibcon#about to read 4, iclass 24, count 0 2006.253.08:19:28.64#ibcon#read 4, iclass 24, count 0 2006.253.08:19:28.64#ibcon#about to read 5, iclass 24, count 0 2006.253.08:19:28.64#ibcon#read 5, iclass 24, count 0 2006.253.08:19:28.64#ibcon#about to read 6, iclass 24, count 0 2006.253.08:19:28.64#ibcon#read 6, iclass 24, count 0 2006.253.08:19:28.64#ibcon#end of sib2, iclass 24, count 0 2006.253.08:19:28.64#ibcon#*after write, iclass 24, count 0 2006.253.08:19:28.64#ibcon#*before return 0, iclass 24, count 0 2006.253.08:19:28.64#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.253.08:19:28.64#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.253.08:19:28.64#ibcon#about to clear, iclass 24 cls_cnt 0 2006.253.08:19:28.64#ibcon#cleared, iclass 24 cls_cnt 0 2006.253.08:19:28.64$vc4f8/va=3,6 2006.253.08:19:28.64#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.253.08:19:28.64#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.253.08:19:28.64#ibcon#ireg 11 cls_cnt 2 2006.253.08:19:28.64#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.253.08:19:28.69#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.253.08:19:28.69#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.253.08:19:28.69#ibcon#enter wrdev, iclass 26, count 2 2006.253.08:19:28.69#ibcon#first serial, iclass 26, count 2 2006.253.08:19:28.69#ibcon#enter sib2, iclass 26, count 2 2006.253.08:19:28.69#ibcon#flushed, iclass 26, count 2 2006.253.08:19:28.69#ibcon#about to write, iclass 26, count 2 2006.253.08:19:28.69#ibcon#wrote, iclass 26, count 2 2006.253.08:19:28.69#ibcon#about to read 3, iclass 26, count 2 2006.253.08:19:28.70#ibcon#read 3, iclass 26, count 2 2006.253.08:19:28.70#ibcon#about to read 4, iclass 26, count 2 2006.253.08:19:28.71#ibcon#read 4, iclass 26, count 2 2006.253.08:19:28.71#ibcon#about to read 5, iclass 26, count 2 2006.253.08:19:28.71#ibcon#read 5, iclass 26, count 2 2006.253.08:19:28.71#ibcon#about to read 6, iclass 26, count 2 2006.253.08:19:28.71#ibcon#read 6, iclass 26, count 2 2006.253.08:19:28.71#ibcon#end of sib2, iclass 26, count 2 2006.253.08:19:28.71#ibcon#*mode == 0, iclass 26, count 2 2006.253.08:19:28.71#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.253.08:19:28.71#ibcon#[25=AT03-06\r\n] 2006.253.08:19:28.71#ibcon#*before write, iclass 26, count 2 2006.253.08:19:28.71#ibcon#enter sib2, iclass 26, count 2 2006.253.08:19:28.71#ibcon#flushed, iclass 26, count 2 2006.253.08:19:28.71#ibcon#about to write, iclass 26, count 2 2006.253.08:19:28.71#ibcon#wrote, iclass 26, count 2 2006.253.08:19:28.71#ibcon#about to read 3, iclass 26, count 2 2006.253.08:19:28.73#ibcon#read 3, iclass 26, count 2 2006.253.08:19:28.73#ibcon#about to read 4, iclass 26, count 2 2006.253.08:19:28.74#ibcon#read 4, iclass 26, count 2 2006.253.08:19:28.74#ibcon#about to read 5, iclass 26, count 2 2006.253.08:19:28.74#ibcon#read 5, iclass 26, count 2 2006.253.08:19:28.74#ibcon#about to read 6, iclass 26, count 2 2006.253.08:19:28.74#ibcon#read 6, iclass 26, count 2 2006.253.08:19:28.74#ibcon#end of sib2, iclass 26, count 2 2006.253.08:19:28.74#ibcon#*after write, iclass 26, count 2 2006.253.08:19:28.74#ibcon#*before return 0, iclass 26, count 2 2006.253.08:19:28.74#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.253.08:19:28.74#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.253.08:19:28.74#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.253.08:19:28.74#ibcon#ireg 7 cls_cnt 0 2006.253.08:19:28.74#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.253.08:19:28.85#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.253.08:19:28.85#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.253.08:19:28.85#ibcon#enter wrdev, iclass 26, count 0 2006.253.08:19:28.85#ibcon#first serial, iclass 26, count 0 2006.253.08:19:28.85#ibcon#enter sib2, iclass 26, count 0 2006.253.08:19:28.86#ibcon#flushed, iclass 26, count 0 2006.253.08:19:28.86#ibcon#about to write, iclass 26, count 0 2006.253.08:19:28.86#ibcon#wrote, iclass 26, count 0 2006.253.08:19:28.86#ibcon#about to read 3, iclass 26, count 0 2006.253.08:19:28.87#ibcon#read 3, iclass 26, count 0 2006.253.08:19:28.87#ibcon#about to read 4, iclass 26, count 0 2006.253.08:19:28.87#ibcon#read 4, iclass 26, count 0 2006.253.08:19:28.87#ibcon#about to read 5, iclass 26, count 0 2006.253.08:19:28.88#ibcon#read 5, iclass 26, count 0 2006.253.08:19:28.88#ibcon#about to read 6, iclass 26, count 0 2006.253.08:19:28.88#ibcon#read 6, iclass 26, count 0 2006.253.08:19:28.88#ibcon#end of sib2, iclass 26, count 0 2006.253.08:19:28.88#ibcon#*mode == 0, iclass 26, count 0 2006.253.08:19:28.88#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.253.08:19:28.88#ibcon#[25=USB\r\n] 2006.253.08:19:28.88#ibcon#*before write, iclass 26, count 0 2006.253.08:19:28.88#ibcon#enter sib2, iclass 26, count 0 2006.253.08:19:28.88#ibcon#flushed, iclass 26, count 0 2006.253.08:19:28.88#ibcon#about to write, iclass 26, count 0 2006.253.08:19:28.88#ibcon#wrote, iclass 26, count 0 2006.253.08:19:28.88#ibcon#about to read 3, iclass 26, count 0 2006.253.08:19:28.90#ibcon#read 3, iclass 26, count 0 2006.253.08:19:28.90#ibcon#about to read 4, iclass 26, count 0 2006.253.08:19:28.90#ibcon#read 4, iclass 26, count 0 2006.253.08:19:28.90#ibcon#about to read 5, iclass 26, count 0 2006.253.08:19:28.91#ibcon#read 5, iclass 26, count 0 2006.253.08:19:28.91#ibcon#about to read 6, iclass 26, count 0 2006.253.08:19:28.91#ibcon#read 6, iclass 26, count 0 2006.253.08:19:28.91#ibcon#end of sib2, iclass 26, count 0 2006.253.08:19:28.91#ibcon#*after write, iclass 26, count 0 2006.253.08:19:28.91#ibcon#*before return 0, iclass 26, count 0 2006.253.08:19:28.91#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.253.08:19:28.91#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.253.08:19:28.91#ibcon#about to clear, iclass 26 cls_cnt 0 2006.253.08:19:28.91#ibcon#cleared, iclass 26 cls_cnt 0 2006.253.08:19:28.91$vc4f8/valo=4,832.99 2006.253.08:19:28.91#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.253.08:19:28.91#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.253.08:19:28.91#ibcon#ireg 17 cls_cnt 0 2006.253.08:19:28.91#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.253.08:19:28.91#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.253.08:19:28.91#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.253.08:19:28.91#ibcon#enter wrdev, iclass 28, count 0 2006.253.08:19:28.91#ibcon#first serial, iclass 28, count 0 2006.253.08:19:28.91#ibcon#enter sib2, iclass 28, count 0 2006.253.08:19:28.91#ibcon#flushed, iclass 28, count 0 2006.253.08:19:28.91#ibcon#about to write, iclass 28, count 0 2006.253.08:19:28.91#ibcon#wrote, iclass 28, count 0 2006.253.08:19:28.91#ibcon#about to read 3, iclass 28, count 0 2006.253.08:19:28.92#ibcon#read 3, iclass 28, count 0 2006.253.08:19:28.92#ibcon#about to read 4, iclass 28, count 0 2006.253.08:19:28.92#ibcon#read 4, iclass 28, count 0 2006.253.08:19:28.92#ibcon#about to read 5, iclass 28, count 0 2006.253.08:19:28.93#ibcon#read 5, iclass 28, count 0 2006.253.08:19:28.93#ibcon#about to read 6, iclass 28, count 0 2006.253.08:19:28.93#ibcon#read 6, iclass 28, count 0 2006.253.08:19:28.93#ibcon#end of sib2, iclass 28, count 0 2006.253.08:19:28.93#ibcon#*mode == 0, iclass 28, count 0 2006.253.08:19:28.93#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.253.08:19:28.93#ibcon#[26=FRQ=04,832.99\r\n] 2006.253.08:19:28.93#ibcon#*before write, iclass 28, count 0 2006.253.08:19:28.93#ibcon#enter sib2, iclass 28, count 0 2006.253.08:19:28.93#ibcon#flushed, iclass 28, count 0 2006.253.08:19:28.93#ibcon#about to write, iclass 28, count 0 2006.253.08:19:28.93#ibcon#wrote, iclass 28, count 0 2006.253.08:19:28.93#ibcon#about to read 3, iclass 28, count 0 2006.253.08:19:28.96#ibcon#read 3, iclass 28, count 0 2006.253.08:19:28.96#ibcon#about to read 4, iclass 28, count 0 2006.253.08:19:28.96#ibcon#read 4, iclass 28, count 0 2006.253.08:19:28.97#ibcon#about to read 5, iclass 28, count 0 2006.253.08:19:28.97#ibcon#read 5, iclass 28, count 0 2006.253.08:19:28.97#ibcon#about to read 6, iclass 28, count 0 2006.253.08:19:28.97#ibcon#read 6, iclass 28, count 0 2006.253.08:19:28.97#ibcon#end of sib2, iclass 28, count 0 2006.253.08:19:28.97#ibcon#*after write, iclass 28, count 0 2006.253.08:19:28.97#ibcon#*before return 0, iclass 28, count 0 2006.253.08:19:28.97#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.253.08:19:28.97#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.253.08:19:28.97#ibcon#about to clear, iclass 28 cls_cnt 0 2006.253.08:19:28.97#ibcon#cleared, iclass 28 cls_cnt 0 2006.253.08:19:28.97$vc4f8/va=4,7 2006.253.08:19:28.97#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.253.08:19:28.97#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.253.08:19:28.97#ibcon#ireg 11 cls_cnt 2 2006.253.08:19:28.97#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.253.08:19:29.02#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.253.08:19:29.02#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.253.08:19:29.02#ibcon#enter wrdev, iclass 30, count 2 2006.253.08:19:29.02#ibcon#first serial, iclass 30, count 2 2006.253.08:19:29.02#ibcon#enter sib2, iclass 30, count 2 2006.253.08:19:29.03#ibcon#flushed, iclass 30, count 2 2006.253.08:19:29.03#ibcon#about to write, iclass 30, count 2 2006.253.08:19:29.03#ibcon#wrote, iclass 30, count 2 2006.253.08:19:29.03#ibcon#about to read 3, iclass 30, count 2 2006.253.08:19:29.04#ibcon#read 3, iclass 30, count 2 2006.253.08:19:29.04#ibcon#about to read 4, iclass 30, count 2 2006.253.08:19:29.04#ibcon#read 4, iclass 30, count 2 2006.253.08:19:29.04#ibcon#about to read 5, iclass 30, count 2 2006.253.08:19:29.04#ibcon#read 5, iclass 30, count 2 2006.253.08:19:29.05#ibcon#about to read 6, iclass 30, count 2 2006.253.08:19:29.05#ibcon#read 6, iclass 30, count 2 2006.253.08:19:29.05#ibcon#end of sib2, iclass 30, count 2 2006.253.08:19:29.05#ibcon#*mode == 0, iclass 30, count 2 2006.253.08:19:29.05#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.253.08:19:29.05#ibcon#[25=AT04-07\r\n] 2006.253.08:19:29.05#ibcon#*before write, iclass 30, count 2 2006.253.08:19:29.05#ibcon#enter sib2, iclass 30, count 2 2006.253.08:19:29.05#ibcon#flushed, iclass 30, count 2 2006.253.08:19:29.05#ibcon#about to write, iclass 30, count 2 2006.253.08:19:29.05#ibcon#wrote, iclass 30, count 2 2006.253.08:19:29.05#ibcon#about to read 3, iclass 30, count 2 2006.253.08:19:29.07#ibcon#read 3, iclass 30, count 2 2006.253.08:19:29.07#ibcon#about to read 4, iclass 30, count 2 2006.253.08:19:29.08#ibcon#read 4, iclass 30, count 2 2006.253.08:19:29.08#ibcon#about to read 5, iclass 30, count 2 2006.253.08:19:29.08#ibcon#read 5, iclass 30, count 2 2006.253.08:19:29.08#ibcon#about to read 6, iclass 30, count 2 2006.253.08:19:29.08#ibcon#read 6, iclass 30, count 2 2006.253.08:19:29.08#ibcon#end of sib2, iclass 30, count 2 2006.253.08:19:29.08#ibcon#*after write, iclass 30, count 2 2006.253.08:19:29.08#ibcon#*before return 0, iclass 30, count 2 2006.253.08:19:29.08#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.253.08:19:29.08#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.253.08:19:29.08#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.253.08:19:29.08#ibcon#ireg 7 cls_cnt 0 2006.253.08:19:29.08#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.253.08:19:29.19#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.253.08:19:29.19#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.253.08:19:29.19#ibcon#enter wrdev, iclass 30, count 0 2006.253.08:19:29.19#ibcon#first serial, iclass 30, count 0 2006.253.08:19:29.19#ibcon#enter sib2, iclass 30, count 0 2006.253.08:19:29.20#ibcon#flushed, iclass 30, count 0 2006.253.08:19:29.20#ibcon#about to write, iclass 30, count 0 2006.253.08:19:29.20#ibcon#wrote, iclass 30, count 0 2006.253.08:19:29.20#ibcon#about to read 3, iclass 30, count 0 2006.253.08:19:29.21#ibcon#read 3, iclass 30, count 0 2006.253.08:19:29.21#ibcon#about to read 4, iclass 30, count 0 2006.253.08:19:29.21#ibcon#read 4, iclass 30, count 0 2006.253.08:19:29.21#ibcon#about to read 5, iclass 30, count 0 2006.253.08:19:29.22#ibcon#read 5, iclass 30, count 0 2006.253.08:19:29.22#ibcon#about to read 6, iclass 30, count 0 2006.253.08:19:29.22#ibcon#read 6, iclass 30, count 0 2006.253.08:19:29.22#ibcon#end of sib2, iclass 30, count 0 2006.253.08:19:29.22#ibcon#*mode == 0, iclass 30, count 0 2006.253.08:19:29.22#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.253.08:19:29.22#ibcon#[25=USB\r\n] 2006.253.08:19:29.22#ibcon#*before write, iclass 30, count 0 2006.253.08:19:29.22#ibcon#enter sib2, iclass 30, count 0 2006.253.08:19:29.22#ibcon#flushed, iclass 30, count 0 2006.253.08:19:29.22#ibcon#about to write, iclass 30, count 0 2006.253.08:19:29.22#ibcon#wrote, iclass 30, count 0 2006.253.08:19:29.22#ibcon#about to read 3, iclass 30, count 0 2006.253.08:19:29.24#ibcon#read 3, iclass 30, count 0 2006.253.08:19:29.24#ibcon#about to read 4, iclass 30, count 0 2006.253.08:19:29.25#ibcon#read 4, iclass 30, count 0 2006.253.08:19:29.25#ibcon#about to read 5, iclass 30, count 0 2006.253.08:19:29.25#ibcon#read 5, iclass 30, count 0 2006.253.08:19:29.25#ibcon#about to read 6, iclass 30, count 0 2006.253.08:19:29.25#ibcon#read 6, iclass 30, count 0 2006.253.08:19:29.25#ibcon#end of sib2, iclass 30, count 0 2006.253.08:19:29.25#ibcon#*after write, iclass 30, count 0 2006.253.08:19:29.25#ibcon#*before return 0, iclass 30, count 0 2006.253.08:19:29.25#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.253.08:19:29.25#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.253.08:19:29.25#ibcon#about to clear, iclass 30 cls_cnt 0 2006.253.08:19:29.25#ibcon#cleared, iclass 30 cls_cnt 0 2006.253.08:19:29.25$vc4f8/valo=5,652.99 2006.253.08:19:29.25#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.253.08:19:29.25#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.253.08:19:29.25#ibcon#ireg 17 cls_cnt 0 2006.253.08:19:29.25#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.253.08:19:29.25#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.253.08:19:29.25#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.253.08:19:29.25#ibcon#enter wrdev, iclass 32, count 0 2006.253.08:19:29.25#ibcon#first serial, iclass 32, count 0 2006.253.08:19:29.25#ibcon#enter sib2, iclass 32, count 0 2006.253.08:19:29.25#ibcon#flushed, iclass 32, count 0 2006.253.08:19:29.25#ibcon#about to write, iclass 32, count 0 2006.253.08:19:29.25#ibcon#wrote, iclass 32, count 0 2006.253.08:19:29.25#ibcon#about to read 3, iclass 32, count 0 2006.253.08:19:29.26#ibcon#read 3, iclass 32, count 0 2006.253.08:19:29.26#ibcon#about to read 4, iclass 32, count 0 2006.253.08:19:29.26#ibcon#read 4, iclass 32, count 0 2006.253.08:19:29.26#ibcon#about to read 5, iclass 32, count 0 2006.253.08:19:29.27#ibcon#read 5, iclass 32, count 0 2006.253.08:19:29.27#ibcon#about to read 6, iclass 32, count 0 2006.253.08:19:29.27#ibcon#read 6, iclass 32, count 0 2006.253.08:19:29.27#ibcon#end of sib2, iclass 32, count 0 2006.253.08:19:29.27#ibcon#*mode == 0, iclass 32, count 0 2006.253.08:19:29.27#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.253.08:19:29.27#ibcon#[26=FRQ=05,652.99\r\n] 2006.253.08:19:29.27#ibcon#*before write, iclass 32, count 0 2006.253.08:19:29.27#ibcon#enter sib2, iclass 32, count 0 2006.253.08:19:29.27#ibcon#flushed, iclass 32, count 0 2006.253.08:19:29.27#ibcon#about to write, iclass 32, count 0 2006.253.08:19:29.27#ibcon#wrote, iclass 32, count 0 2006.253.08:19:29.27#ibcon#about to read 3, iclass 32, count 0 2006.253.08:19:29.30#ibcon#read 3, iclass 32, count 0 2006.253.08:19:29.30#ibcon#about to read 4, iclass 32, count 0 2006.253.08:19:29.31#ibcon#read 4, iclass 32, count 0 2006.253.08:19:29.31#ibcon#about to read 5, iclass 32, count 0 2006.253.08:19:29.31#ibcon#read 5, iclass 32, count 0 2006.253.08:19:29.31#ibcon#about to read 6, iclass 32, count 0 2006.253.08:19:29.31#ibcon#read 6, iclass 32, count 0 2006.253.08:19:29.31#ibcon#end of sib2, iclass 32, count 0 2006.253.08:19:29.31#ibcon#*after write, iclass 32, count 0 2006.253.08:19:29.31#ibcon#*before return 0, iclass 32, count 0 2006.253.08:19:29.31#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.253.08:19:29.31#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.253.08:19:29.31#ibcon#about to clear, iclass 32 cls_cnt 0 2006.253.08:19:29.31#ibcon#cleared, iclass 32 cls_cnt 0 2006.253.08:19:29.31$vc4f8/va=5,7 2006.253.08:19:29.31#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.253.08:19:29.31#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.253.08:19:29.31#ibcon#ireg 11 cls_cnt 2 2006.253.08:19:29.31#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.253.08:19:29.36#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.253.08:19:29.36#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.253.08:19:29.36#ibcon#enter wrdev, iclass 34, count 2 2006.253.08:19:29.36#ibcon#first serial, iclass 34, count 2 2006.253.08:19:29.36#ibcon#enter sib2, iclass 34, count 2 2006.253.08:19:29.37#ibcon#flushed, iclass 34, count 2 2006.253.08:19:29.37#ibcon#about to write, iclass 34, count 2 2006.253.08:19:29.37#ibcon#wrote, iclass 34, count 2 2006.253.08:19:29.37#ibcon#about to read 3, iclass 34, count 2 2006.253.08:19:29.38#ibcon#read 3, iclass 34, count 2 2006.253.08:19:29.38#ibcon#about to read 4, iclass 34, count 2 2006.253.08:19:29.38#ibcon#read 4, iclass 34, count 2 2006.253.08:19:29.38#ibcon#about to read 5, iclass 34, count 2 2006.253.08:19:29.39#ibcon#read 5, iclass 34, count 2 2006.253.08:19:29.39#ibcon#about to read 6, iclass 34, count 2 2006.253.08:19:29.39#ibcon#read 6, iclass 34, count 2 2006.253.08:19:29.39#ibcon#end of sib2, iclass 34, count 2 2006.253.08:19:29.39#ibcon#*mode == 0, iclass 34, count 2 2006.253.08:19:29.39#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.253.08:19:29.39#ibcon#[25=AT05-07\r\n] 2006.253.08:19:29.39#ibcon#*before write, iclass 34, count 2 2006.253.08:19:29.39#ibcon#enter sib2, iclass 34, count 2 2006.253.08:19:29.39#ibcon#flushed, iclass 34, count 2 2006.253.08:19:29.39#ibcon#about to write, iclass 34, count 2 2006.253.08:19:29.39#ibcon#wrote, iclass 34, count 2 2006.253.08:19:29.39#ibcon#about to read 3, iclass 34, count 2 2006.253.08:19:29.41#ibcon#read 3, iclass 34, count 2 2006.253.08:19:29.41#ibcon#about to read 4, iclass 34, count 2 2006.253.08:19:29.41#ibcon#read 4, iclass 34, count 2 2006.253.08:19:29.42#ibcon#about to read 5, iclass 34, count 2 2006.253.08:19:29.42#ibcon#read 5, iclass 34, count 2 2006.253.08:19:29.42#ibcon#about to read 6, iclass 34, count 2 2006.253.08:19:29.42#ibcon#read 6, iclass 34, count 2 2006.253.08:19:29.42#ibcon#end of sib2, iclass 34, count 2 2006.253.08:19:29.42#ibcon#*after write, iclass 34, count 2 2006.253.08:19:29.42#ibcon#*before return 0, iclass 34, count 2 2006.253.08:19:29.42#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.253.08:19:29.42#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.253.08:19:29.42#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.253.08:19:29.42#ibcon#ireg 7 cls_cnt 0 2006.253.08:19:29.42#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.253.08:19:29.53#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.253.08:19:29.53#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.253.08:19:29.53#ibcon#enter wrdev, iclass 34, count 0 2006.253.08:19:29.53#ibcon#first serial, iclass 34, count 0 2006.253.08:19:29.53#ibcon#enter sib2, iclass 34, count 0 2006.253.08:19:29.54#ibcon#flushed, iclass 34, count 0 2006.253.08:19:29.54#ibcon#about to write, iclass 34, count 0 2006.253.08:19:29.54#ibcon#wrote, iclass 34, count 0 2006.253.08:19:29.54#ibcon#about to read 3, iclass 34, count 0 2006.253.08:19:29.55#ibcon#read 3, iclass 34, count 0 2006.253.08:19:29.55#ibcon#about to read 4, iclass 34, count 0 2006.253.08:19:29.55#ibcon#read 4, iclass 34, count 0 2006.253.08:19:29.55#ibcon#about to read 5, iclass 34, count 0 2006.253.08:19:29.56#ibcon#read 5, iclass 34, count 0 2006.253.08:19:29.56#ibcon#about to read 6, iclass 34, count 0 2006.253.08:19:29.56#ibcon#read 6, iclass 34, count 0 2006.253.08:19:29.56#ibcon#end of sib2, iclass 34, count 0 2006.253.08:19:29.56#ibcon#*mode == 0, iclass 34, count 0 2006.253.08:19:29.56#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.253.08:19:29.56#ibcon#[25=USB\r\n] 2006.253.08:19:29.56#ibcon#*before write, iclass 34, count 0 2006.253.08:19:29.56#ibcon#enter sib2, iclass 34, count 0 2006.253.08:19:29.56#ibcon#flushed, iclass 34, count 0 2006.253.08:19:29.56#ibcon#about to write, iclass 34, count 0 2006.253.08:19:29.56#ibcon#wrote, iclass 34, count 0 2006.253.08:19:29.56#ibcon#about to read 3, iclass 34, count 0 2006.253.08:19:29.58#ibcon#read 3, iclass 34, count 0 2006.253.08:19:29.58#ibcon#about to read 4, iclass 34, count 0 2006.253.08:19:29.58#ibcon#read 4, iclass 34, count 0 2006.253.08:19:29.58#ibcon#about to read 5, iclass 34, count 0 2006.253.08:19:29.59#ibcon#read 5, iclass 34, count 0 2006.253.08:19:29.59#ibcon#about to read 6, iclass 34, count 0 2006.253.08:19:29.59#ibcon#read 6, iclass 34, count 0 2006.253.08:19:29.59#ibcon#end of sib2, iclass 34, count 0 2006.253.08:19:29.59#ibcon#*after write, iclass 34, count 0 2006.253.08:19:29.59#ibcon#*before return 0, iclass 34, count 0 2006.253.08:19:29.59#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.253.08:19:29.59#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.253.08:19:29.59#ibcon#about to clear, iclass 34 cls_cnt 0 2006.253.08:19:29.59#ibcon#cleared, iclass 34 cls_cnt 0 2006.253.08:19:29.59$vc4f8/valo=6,772.99 2006.253.08:19:29.59#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.253.08:19:29.59#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.253.08:19:29.59#ibcon#ireg 17 cls_cnt 0 2006.253.08:19:29.59#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.253.08:19:29.59#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.253.08:19:29.59#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.253.08:19:29.59#ibcon#enter wrdev, iclass 36, count 0 2006.253.08:19:29.59#ibcon#first serial, iclass 36, count 0 2006.253.08:19:29.59#ibcon#enter sib2, iclass 36, count 0 2006.253.08:19:29.59#ibcon#flushed, iclass 36, count 0 2006.253.08:19:29.59#ibcon#about to write, iclass 36, count 0 2006.253.08:19:29.59#ibcon#wrote, iclass 36, count 0 2006.253.08:19:29.59#ibcon#about to read 3, iclass 36, count 0 2006.253.08:19:29.60#ibcon#read 3, iclass 36, count 0 2006.253.08:19:29.60#ibcon#about to read 4, iclass 36, count 0 2006.253.08:19:29.60#ibcon#read 4, iclass 36, count 0 2006.253.08:19:29.60#ibcon#about to read 5, iclass 36, count 0 2006.253.08:19:29.61#ibcon#read 5, iclass 36, count 0 2006.253.08:19:29.61#ibcon#about to read 6, iclass 36, count 0 2006.253.08:19:29.61#ibcon#read 6, iclass 36, count 0 2006.253.08:19:29.61#ibcon#end of sib2, iclass 36, count 0 2006.253.08:19:29.61#ibcon#*mode == 0, iclass 36, count 0 2006.253.08:19:29.61#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.253.08:19:29.61#ibcon#[26=FRQ=06,772.99\r\n] 2006.253.08:19:29.61#ibcon#*before write, iclass 36, count 0 2006.253.08:19:29.61#ibcon#enter sib2, iclass 36, count 0 2006.253.08:19:29.61#ibcon#flushed, iclass 36, count 0 2006.253.08:19:29.61#ibcon#about to write, iclass 36, count 0 2006.253.08:19:29.61#ibcon#wrote, iclass 36, count 0 2006.253.08:19:29.61#ibcon#about to read 3, iclass 36, count 0 2006.253.08:19:29.64#ibcon#read 3, iclass 36, count 0 2006.253.08:19:29.64#ibcon#about to read 4, iclass 36, count 0 2006.253.08:19:29.64#ibcon#read 4, iclass 36, count 0 2006.253.08:19:29.65#ibcon#about to read 5, iclass 36, count 0 2006.253.08:19:29.65#ibcon#read 5, iclass 36, count 0 2006.253.08:19:29.65#ibcon#about to read 6, iclass 36, count 0 2006.253.08:19:29.65#ibcon#read 6, iclass 36, count 0 2006.253.08:19:29.65#ibcon#end of sib2, iclass 36, count 0 2006.253.08:19:29.65#ibcon#*after write, iclass 36, count 0 2006.253.08:19:29.65#ibcon#*before return 0, iclass 36, count 0 2006.253.08:19:29.65#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.253.08:19:29.65#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.253.08:19:29.65#ibcon#about to clear, iclass 36 cls_cnt 0 2006.253.08:19:29.65#ibcon#cleared, iclass 36 cls_cnt 0 2006.253.08:19:29.65$vc4f8/va=6,7 2006.253.08:19:29.65#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.253.08:19:29.65#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.253.08:19:29.65#ibcon#ireg 11 cls_cnt 2 2006.253.08:19:29.65#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.253.08:19:29.70#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.253.08:19:29.70#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.253.08:19:29.70#ibcon#enter wrdev, iclass 38, count 2 2006.253.08:19:29.70#ibcon#first serial, iclass 38, count 2 2006.253.08:19:29.70#ibcon#enter sib2, iclass 38, count 2 2006.253.08:19:29.71#ibcon#flushed, iclass 38, count 2 2006.253.08:19:29.71#ibcon#about to write, iclass 38, count 2 2006.253.08:19:29.71#ibcon#wrote, iclass 38, count 2 2006.253.08:19:29.71#ibcon#about to read 3, iclass 38, count 2 2006.253.08:19:29.72#ibcon#read 3, iclass 38, count 2 2006.253.08:19:29.72#ibcon#about to read 4, iclass 38, count 2 2006.253.08:19:29.72#ibcon#read 4, iclass 38, count 2 2006.253.08:19:29.72#ibcon#about to read 5, iclass 38, count 2 2006.253.08:19:29.73#ibcon#read 5, iclass 38, count 2 2006.253.08:19:29.73#ibcon#about to read 6, iclass 38, count 2 2006.253.08:19:29.73#ibcon#read 6, iclass 38, count 2 2006.253.08:19:29.73#ibcon#end of sib2, iclass 38, count 2 2006.253.08:19:29.73#ibcon#*mode == 0, iclass 38, count 2 2006.253.08:19:29.73#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.253.08:19:29.73#ibcon#[25=AT06-07\r\n] 2006.253.08:19:29.73#ibcon#*before write, iclass 38, count 2 2006.253.08:19:29.73#ibcon#enter sib2, iclass 38, count 2 2006.253.08:19:29.73#ibcon#flushed, iclass 38, count 2 2006.253.08:19:29.73#ibcon#about to write, iclass 38, count 2 2006.253.08:19:29.73#ibcon#wrote, iclass 38, count 2 2006.253.08:19:29.73#ibcon#about to read 3, iclass 38, count 2 2006.253.08:19:29.75#ibcon#read 3, iclass 38, count 2 2006.253.08:19:29.75#ibcon#about to read 4, iclass 38, count 2 2006.253.08:19:29.76#ibcon#read 4, iclass 38, count 2 2006.253.08:19:29.76#ibcon#about to read 5, iclass 38, count 2 2006.253.08:19:29.76#ibcon#read 5, iclass 38, count 2 2006.253.08:19:29.76#ibcon#about to read 6, iclass 38, count 2 2006.253.08:19:29.76#ibcon#read 6, iclass 38, count 2 2006.253.08:19:29.76#ibcon#end of sib2, iclass 38, count 2 2006.253.08:19:29.76#ibcon#*after write, iclass 38, count 2 2006.253.08:19:29.76#ibcon#*before return 0, iclass 38, count 2 2006.253.08:19:29.76#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.253.08:19:29.76#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.253.08:19:29.76#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.253.08:19:29.76#ibcon#ireg 7 cls_cnt 0 2006.253.08:19:29.76#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.253.08:19:29.87#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.253.08:19:29.87#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.253.08:19:29.87#ibcon#enter wrdev, iclass 38, count 0 2006.253.08:19:29.87#ibcon#first serial, iclass 38, count 0 2006.253.08:19:29.87#ibcon#enter sib2, iclass 38, count 0 2006.253.08:19:29.88#ibcon#flushed, iclass 38, count 0 2006.253.08:19:29.88#ibcon#about to write, iclass 38, count 0 2006.253.08:19:29.88#ibcon#wrote, iclass 38, count 0 2006.253.08:19:29.88#ibcon#about to read 3, iclass 38, count 0 2006.253.08:19:29.89#ibcon#read 3, iclass 38, count 0 2006.253.08:19:29.89#ibcon#about to read 4, iclass 38, count 0 2006.253.08:19:29.89#ibcon#read 4, iclass 38, count 0 2006.253.08:19:29.89#ibcon#about to read 5, iclass 38, count 0 2006.253.08:19:29.90#ibcon#read 5, iclass 38, count 0 2006.253.08:19:29.90#ibcon#about to read 6, iclass 38, count 0 2006.253.08:19:29.90#ibcon#read 6, iclass 38, count 0 2006.253.08:19:29.90#ibcon#end of sib2, iclass 38, count 0 2006.253.08:19:29.90#ibcon#*mode == 0, iclass 38, count 0 2006.253.08:19:29.90#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.253.08:19:29.90#ibcon#[25=USB\r\n] 2006.253.08:19:29.90#ibcon#*before write, iclass 38, count 0 2006.253.08:19:29.90#ibcon#enter sib2, iclass 38, count 0 2006.253.08:19:29.90#ibcon#flushed, iclass 38, count 0 2006.253.08:19:29.90#ibcon#about to write, iclass 38, count 0 2006.253.08:19:29.90#ibcon#wrote, iclass 38, count 0 2006.253.08:19:29.90#ibcon#about to read 3, iclass 38, count 0 2006.253.08:19:29.92#ibcon#read 3, iclass 38, count 0 2006.253.08:19:29.92#ibcon#about to read 4, iclass 38, count 0 2006.253.08:19:29.92#ibcon#read 4, iclass 38, count 0 2006.253.08:19:29.92#ibcon#about to read 5, iclass 38, count 0 2006.253.08:19:29.93#ibcon#read 5, iclass 38, count 0 2006.253.08:19:29.93#ibcon#about to read 6, iclass 38, count 0 2006.253.08:19:29.93#ibcon#read 6, iclass 38, count 0 2006.253.08:19:29.93#ibcon#end of sib2, iclass 38, count 0 2006.253.08:19:29.93#ibcon#*after write, iclass 38, count 0 2006.253.08:19:29.93#ibcon#*before return 0, iclass 38, count 0 2006.253.08:19:29.93#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.253.08:19:29.93#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.253.08:19:29.93#ibcon#about to clear, iclass 38 cls_cnt 0 2006.253.08:19:29.93#ibcon#cleared, iclass 38 cls_cnt 0 2006.253.08:19:29.93$vc4f8/valo=7,832.99 2006.253.08:19:29.93#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.253.08:19:29.93#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.253.08:19:29.93#ibcon#ireg 17 cls_cnt 0 2006.253.08:19:29.93#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.253.08:19:29.93#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.253.08:19:29.93#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.253.08:19:29.93#ibcon#enter wrdev, iclass 40, count 0 2006.253.08:19:29.93#ibcon#first serial, iclass 40, count 0 2006.253.08:19:29.93#ibcon#enter sib2, iclass 40, count 0 2006.253.08:19:29.93#ibcon#flushed, iclass 40, count 0 2006.253.08:19:29.93#ibcon#about to write, iclass 40, count 0 2006.253.08:19:29.93#ibcon#wrote, iclass 40, count 0 2006.253.08:19:29.93#ibcon#about to read 3, iclass 40, count 0 2006.253.08:19:29.94#ibcon#read 3, iclass 40, count 0 2006.253.08:19:29.94#ibcon#about to read 4, iclass 40, count 0 2006.253.08:19:29.94#ibcon#read 4, iclass 40, count 0 2006.253.08:19:29.94#ibcon#about to read 5, iclass 40, count 0 2006.253.08:19:29.95#ibcon#read 5, iclass 40, count 0 2006.253.08:19:29.95#ibcon#about to read 6, iclass 40, count 0 2006.253.08:19:29.95#ibcon#read 6, iclass 40, count 0 2006.253.08:19:29.95#ibcon#end of sib2, iclass 40, count 0 2006.253.08:19:29.95#ibcon#*mode == 0, iclass 40, count 0 2006.253.08:19:29.95#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.253.08:19:29.95#ibcon#[26=FRQ=07,832.99\r\n] 2006.253.08:19:29.95#ibcon#*before write, iclass 40, count 0 2006.253.08:19:29.95#ibcon#enter sib2, iclass 40, count 0 2006.253.08:19:29.95#ibcon#flushed, iclass 40, count 0 2006.253.08:19:29.95#ibcon#about to write, iclass 40, count 0 2006.253.08:19:29.95#ibcon#wrote, iclass 40, count 0 2006.253.08:19:29.95#ibcon#about to read 3, iclass 40, count 0 2006.253.08:19:29.98#ibcon#read 3, iclass 40, count 0 2006.253.08:19:29.98#ibcon#about to read 4, iclass 40, count 0 2006.253.08:19:29.98#ibcon#read 4, iclass 40, count 0 2006.253.08:19:29.99#ibcon#about to read 5, iclass 40, count 0 2006.253.08:19:29.99#ibcon#read 5, iclass 40, count 0 2006.253.08:19:29.99#ibcon#about to read 6, iclass 40, count 0 2006.253.08:19:29.99#ibcon#read 6, iclass 40, count 0 2006.253.08:19:29.99#ibcon#end of sib2, iclass 40, count 0 2006.253.08:19:29.99#ibcon#*after write, iclass 40, count 0 2006.253.08:19:29.99#ibcon#*before return 0, iclass 40, count 0 2006.253.08:19:29.99#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.253.08:19:29.99#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.253.08:19:29.99#ibcon#about to clear, iclass 40 cls_cnt 0 2006.253.08:19:29.99#ibcon#cleared, iclass 40 cls_cnt 0 2006.253.08:19:29.99$vc4f8/va=7,7 2006.253.08:19:29.99#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.253.08:19:29.99#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.253.08:19:29.99#ibcon#ireg 11 cls_cnt 2 2006.253.08:19:29.99#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.253.08:19:30.04#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.253.08:19:30.04#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.253.08:19:30.04#ibcon#enter wrdev, iclass 4, count 2 2006.253.08:19:30.04#ibcon#first serial, iclass 4, count 2 2006.253.08:19:30.04#ibcon#enter sib2, iclass 4, count 2 2006.253.08:19:30.05#ibcon#flushed, iclass 4, count 2 2006.253.08:19:30.05#ibcon#about to write, iclass 4, count 2 2006.253.08:19:30.05#ibcon#wrote, iclass 4, count 2 2006.253.08:19:30.05#ibcon#about to read 3, iclass 4, count 2 2006.253.08:19:30.06#ibcon#read 3, iclass 4, count 2 2006.253.08:19:30.06#ibcon#about to read 4, iclass 4, count 2 2006.253.08:19:30.06#ibcon#read 4, iclass 4, count 2 2006.253.08:19:30.06#ibcon#about to read 5, iclass 4, count 2 2006.253.08:19:30.06#ibcon#read 5, iclass 4, count 2 2006.253.08:19:30.07#ibcon#about to read 6, iclass 4, count 2 2006.253.08:19:30.07#ibcon#read 6, iclass 4, count 2 2006.253.08:19:30.07#ibcon#end of sib2, iclass 4, count 2 2006.253.08:19:30.07#ibcon#*mode == 0, iclass 4, count 2 2006.253.08:19:30.07#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.253.08:19:30.07#ibcon#[25=AT07-07\r\n] 2006.253.08:19:30.07#ibcon#*before write, iclass 4, count 2 2006.253.08:19:30.07#ibcon#enter sib2, iclass 4, count 2 2006.253.08:19:30.07#ibcon#flushed, iclass 4, count 2 2006.253.08:19:30.07#ibcon#about to write, iclass 4, count 2 2006.253.08:19:30.07#ibcon#wrote, iclass 4, count 2 2006.253.08:19:30.07#ibcon#about to read 3, iclass 4, count 2 2006.253.08:19:30.09#ibcon#read 3, iclass 4, count 2 2006.253.08:19:30.09#ibcon#about to read 4, iclass 4, count 2 2006.253.08:19:30.10#ibcon#read 4, iclass 4, count 2 2006.253.08:19:30.10#ibcon#about to read 5, iclass 4, count 2 2006.253.08:19:30.10#ibcon#read 5, iclass 4, count 2 2006.253.08:19:30.10#ibcon#about to read 6, iclass 4, count 2 2006.253.08:19:30.10#ibcon#read 6, iclass 4, count 2 2006.253.08:19:30.10#ibcon#end of sib2, iclass 4, count 2 2006.253.08:19:30.10#ibcon#*after write, iclass 4, count 2 2006.253.08:19:30.10#ibcon#*before return 0, iclass 4, count 2 2006.253.08:19:30.10#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.253.08:19:30.10#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.253.08:19:30.10#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.253.08:19:30.10#ibcon#ireg 7 cls_cnt 0 2006.253.08:19:30.10#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.253.08:19:30.21#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.253.08:19:30.21#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.253.08:19:30.21#ibcon#enter wrdev, iclass 4, count 0 2006.253.08:19:30.21#ibcon#first serial, iclass 4, count 0 2006.253.08:19:30.21#ibcon#enter sib2, iclass 4, count 0 2006.253.08:19:30.21#ibcon#flushed, iclass 4, count 0 2006.253.08:19:30.22#ibcon#about to write, iclass 4, count 0 2006.253.08:19:30.22#ibcon#wrote, iclass 4, count 0 2006.253.08:19:30.22#ibcon#about to read 3, iclass 4, count 0 2006.253.08:19:30.23#ibcon#read 3, iclass 4, count 0 2006.253.08:19:30.23#ibcon#about to read 4, iclass 4, count 0 2006.253.08:19:30.23#ibcon#read 4, iclass 4, count 0 2006.253.08:19:30.23#ibcon#about to read 5, iclass 4, count 0 2006.253.08:19:30.23#ibcon#read 5, iclass 4, count 0 2006.253.08:19:30.24#ibcon#about to read 6, iclass 4, count 0 2006.253.08:19:30.24#ibcon#read 6, iclass 4, count 0 2006.253.08:19:30.24#ibcon#end of sib2, iclass 4, count 0 2006.253.08:19:30.24#ibcon#*mode == 0, iclass 4, count 0 2006.253.08:19:30.24#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.253.08:19:30.24#ibcon#[25=USB\r\n] 2006.253.08:19:30.24#ibcon#*before write, iclass 4, count 0 2006.253.08:19:30.24#ibcon#enter sib2, iclass 4, count 0 2006.253.08:19:30.24#ibcon#flushed, iclass 4, count 0 2006.253.08:19:30.24#ibcon#about to write, iclass 4, count 0 2006.253.08:19:30.24#ibcon#wrote, iclass 4, count 0 2006.253.08:19:30.24#ibcon#about to read 3, iclass 4, count 0 2006.253.08:19:30.26#ibcon#read 3, iclass 4, count 0 2006.253.08:19:30.26#ibcon#about to read 4, iclass 4, count 0 2006.253.08:19:30.27#ibcon#read 4, iclass 4, count 0 2006.253.08:19:30.27#ibcon#about to read 5, iclass 4, count 0 2006.253.08:19:30.27#ibcon#read 5, iclass 4, count 0 2006.253.08:19:30.27#ibcon#about to read 6, iclass 4, count 0 2006.253.08:19:30.27#ibcon#read 6, iclass 4, count 0 2006.253.08:19:30.27#ibcon#end of sib2, iclass 4, count 0 2006.253.08:19:30.27#ibcon#*after write, iclass 4, count 0 2006.253.08:19:30.27#ibcon#*before return 0, iclass 4, count 0 2006.253.08:19:30.27#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.253.08:19:30.27#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.253.08:19:30.27#ibcon#about to clear, iclass 4 cls_cnt 0 2006.253.08:19:30.27#ibcon#cleared, iclass 4 cls_cnt 0 2006.253.08:19:30.27$vc4f8/valo=8,852.99 2006.253.08:19:30.27#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.253.08:19:30.27#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.253.08:19:30.27#ibcon#ireg 17 cls_cnt 0 2006.253.08:19:30.27#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.253.08:19:30.27#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.253.08:19:30.27#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.253.08:19:30.27#ibcon#enter wrdev, iclass 6, count 0 2006.253.08:19:30.27#ibcon#first serial, iclass 6, count 0 2006.253.08:19:30.27#ibcon#enter sib2, iclass 6, count 0 2006.253.08:19:30.27#ibcon#flushed, iclass 6, count 0 2006.253.08:19:30.27#ibcon#about to write, iclass 6, count 0 2006.253.08:19:30.27#ibcon#wrote, iclass 6, count 0 2006.253.08:19:30.27#ibcon#about to read 3, iclass 6, count 0 2006.253.08:19:30.28#ibcon#read 3, iclass 6, count 0 2006.253.08:19:30.28#ibcon#about to read 4, iclass 6, count 0 2006.253.08:19:30.28#ibcon#read 4, iclass 6, count 0 2006.253.08:19:30.28#ibcon#about to read 5, iclass 6, count 0 2006.253.08:19:30.29#ibcon#read 5, iclass 6, count 0 2006.253.08:19:30.29#ibcon#about to read 6, iclass 6, count 0 2006.253.08:19:30.29#ibcon#read 6, iclass 6, count 0 2006.253.08:19:30.29#ibcon#end of sib2, iclass 6, count 0 2006.253.08:19:30.29#ibcon#*mode == 0, iclass 6, count 0 2006.253.08:19:30.29#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.253.08:19:30.29#ibcon#[26=FRQ=08,852.99\r\n] 2006.253.08:19:30.29#ibcon#*before write, iclass 6, count 0 2006.253.08:19:30.29#ibcon#enter sib2, iclass 6, count 0 2006.253.08:19:30.29#ibcon#flushed, iclass 6, count 0 2006.253.08:19:30.29#ibcon#about to write, iclass 6, count 0 2006.253.08:19:30.29#ibcon#wrote, iclass 6, count 0 2006.253.08:19:30.29#ibcon#about to read 3, iclass 6, count 0 2006.253.08:19:30.32#ibcon#read 3, iclass 6, count 0 2006.253.08:19:30.33#ibcon#about to read 4, iclass 6, count 0 2006.253.08:19:30.33#ibcon#read 4, iclass 6, count 0 2006.253.08:19:30.33#ibcon#about to read 5, iclass 6, count 0 2006.253.08:19:30.33#ibcon#read 5, iclass 6, count 0 2006.253.08:19:30.33#ibcon#about to read 6, iclass 6, count 0 2006.253.08:19:30.33#ibcon#read 6, iclass 6, count 0 2006.253.08:19:30.33#ibcon#end of sib2, iclass 6, count 0 2006.253.08:19:30.33#ibcon#*after write, iclass 6, count 0 2006.253.08:19:30.33#ibcon#*before return 0, iclass 6, count 0 2006.253.08:19:30.33#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.253.08:19:30.33#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.253.08:19:30.33#ibcon#about to clear, iclass 6 cls_cnt 0 2006.253.08:19:30.33#ibcon#cleared, iclass 6 cls_cnt 0 2006.253.08:19:30.33$vc4f8/va=8,7 2006.253.08:19:30.33#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.253.08:19:30.33#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.253.08:19:30.33#ibcon#ireg 11 cls_cnt 2 2006.253.08:19:30.33#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.253.08:19:30.38#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.253.08:19:30.38#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.253.08:19:30.38#ibcon#enter wrdev, iclass 10, count 2 2006.253.08:19:30.38#ibcon#first serial, iclass 10, count 2 2006.253.08:19:30.38#ibcon#enter sib2, iclass 10, count 2 2006.253.08:19:30.39#ibcon#flushed, iclass 10, count 2 2006.253.08:19:30.39#ibcon#about to write, iclass 10, count 2 2006.253.08:19:30.39#ibcon#wrote, iclass 10, count 2 2006.253.08:19:30.39#ibcon#about to read 3, iclass 10, count 2 2006.253.08:19:30.40#ibcon#read 3, iclass 10, count 2 2006.253.08:19:30.41#ibcon#about to read 4, iclass 10, count 2 2006.253.08:19:30.41#ibcon#read 4, iclass 10, count 2 2006.253.08:19:30.41#ibcon#about to read 5, iclass 10, count 2 2006.253.08:19:30.41#ibcon#read 5, iclass 10, count 2 2006.253.08:19:30.41#ibcon#about to read 6, iclass 10, count 2 2006.253.08:19:30.41#ibcon#read 6, iclass 10, count 2 2006.253.08:19:30.41#ibcon#end of sib2, iclass 10, count 2 2006.253.08:19:30.41#ibcon#*mode == 0, iclass 10, count 2 2006.253.08:19:30.41#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.253.08:19:30.41#ibcon#[25=AT08-07\r\n] 2006.253.08:19:30.41#ibcon#*before write, iclass 10, count 2 2006.253.08:19:30.41#ibcon#enter sib2, iclass 10, count 2 2006.253.08:19:30.41#ibcon#flushed, iclass 10, count 2 2006.253.08:19:30.41#ibcon#about to write, iclass 10, count 2 2006.253.08:19:30.41#ibcon#wrote, iclass 10, count 2 2006.253.08:19:30.41#ibcon#about to read 3, iclass 10, count 2 2006.253.08:19:30.43#ibcon#read 3, iclass 10, count 2 2006.253.08:19:30.43#ibcon#about to read 4, iclass 10, count 2 2006.253.08:19:30.43#ibcon#read 4, iclass 10, count 2 2006.253.08:19:30.43#ibcon#about to read 5, iclass 10, count 2 2006.253.08:19:30.43#ibcon#read 5, iclass 10, count 2 2006.253.08:19:30.44#ibcon#about to read 6, iclass 10, count 2 2006.253.08:19:30.44#ibcon#read 6, iclass 10, count 2 2006.253.08:19:30.44#ibcon#end of sib2, iclass 10, count 2 2006.253.08:19:30.44#ibcon#*after write, iclass 10, count 2 2006.253.08:19:30.44#ibcon#*before return 0, iclass 10, count 2 2006.253.08:19:30.44#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.253.08:19:30.44#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.253.08:19:30.44#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.253.08:19:30.44#ibcon#ireg 7 cls_cnt 0 2006.253.08:19:30.44#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.253.08:19:30.55#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.253.08:19:30.55#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.253.08:19:30.55#ibcon#enter wrdev, iclass 10, count 0 2006.253.08:19:30.55#ibcon#first serial, iclass 10, count 0 2006.253.08:19:30.55#ibcon#enter sib2, iclass 10, count 0 2006.253.08:19:30.56#ibcon#flushed, iclass 10, count 0 2006.253.08:19:30.56#ibcon#about to write, iclass 10, count 0 2006.253.08:19:30.56#ibcon#wrote, iclass 10, count 0 2006.253.08:19:30.56#ibcon#about to read 3, iclass 10, count 0 2006.253.08:19:30.57#ibcon#read 3, iclass 10, count 0 2006.253.08:19:30.57#ibcon#about to read 4, iclass 10, count 0 2006.253.08:19:30.57#ibcon#read 4, iclass 10, count 0 2006.253.08:19:30.57#ibcon#about to read 5, iclass 10, count 0 2006.253.08:19:30.58#ibcon#read 5, iclass 10, count 0 2006.253.08:19:30.58#ibcon#about to read 6, iclass 10, count 0 2006.253.08:19:30.58#ibcon#read 6, iclass 10, count 0 2006.253.08:19:30.58#ibcon#end of sib2, iclass 10, count 0 2006.253.08:19:30.58#ibcon#*mode == 0, iclass 10, count 0 2006.253.08:19:30.58#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.253.08:19:30.58#ibcon#[25=USB\r\n] 2006.253.08:19:30.58#ibcon#*before write, iclass 10, count 0 2006.253.08:19:30.58#ibcon#enter sib2, iclass 10, count 0 2006.253.08:19:30.58#ibcon#flushed, iclass 10, count 0 2006.253.08:19:30.58#ibcon#about to write, iclass 10, count 0 2006.253.08:19:30.58#ibcon#wrote, iclass 10, count 0 2006.253.08:19:30.58#ibcon#about to read 3, iclass 10, count 0 2006.253.08:19:30.60#ibcon#read 3, iclass 10, count 0 2006.253.08:19:30.60#ibcon#about to read 4, iclass 10, count 0 2006.253.08:19:30.60#ibcon#read 4, iclass 10, count 0 2006.253.08:19:30.60#ibcon#about to read 5, iclass 10, count 0 2006.253.08:19:30.61#ibcon#read 5, iclass 10, count 0 2006.253.08:19:30.61#ibcon#about to read 6, iclass 10, count 0 2006.253.08:19:30.61#ibcon#read 6, iclass 10, count 0 2006.253.08:19:30.61#ibcon#end of sib2, iclass 10, count 0 2006.253.08:19:30.61#ibcon#*after write, iclass 10, count 0 2006.253.08:19:30.61#ibcon#*before return 0, iclass 10, count 0 2006.253.08:19:30.61#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.253.08:19:30.61#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.253.08:19:30.61#ibcon#about to clear, iclass 10 cls_cnt 0 2006.253.08:19:30.61#ibcon#cleared, iclass 10 cls_cnt 0 2006.253.08:19:30.61$vc4f8/vblo=1,632.99 2006.253.08:19:30.61#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.253.08:19:30.61#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.253.08:19:30.61#ibcon#ireg 17 cls_cnt 0 2006.253.08:19:30.61#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.253.08:19:30.61#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.253.08:19:30.61#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.253.08:19:30.61#ibcon#enter wrdev, iclass 12, count 0 2006.253.08:19:30.61#ibcon#first serial, iclass 12, count 0 2006.253.08:19:30.61#ibcon#enter sib2, iclass 12, count 0 2006.253.08:19:30.61#ibcon#flushed, iclass 12, count 0 2006.253.08:19:30.61#ibcon#about to write, iclass 12, count 0 2006.253.08:19:30.61#ibcon#wrote, iclass 12, count 0 2006.253.08:19:30.61#ibcon#about to read 3, iclass 12, count 0 2006.253.08:19:30.62#ibcon#read 3, iclass 12, count 0 2006.253.08:19:30.62#ibcon#about to read 4, iclass 12, count 0 2006.253.08:19:30.62#ibcon#read 4, iclass 12, count 0 2006.253.08:19:30.62#ibcon#about to read 5, iclass 12, count 0 2006.253.08:19:30.63#ibcon#read 5, iclass 12, count 0 2006.253.08:19:30.63#ibcon#about to read 6, iclass 12, count 0 2006.253.08:19:30.63#ibcon#read 6, iclass 12, count 0 2006.253.08:19:30.63#ibcon#end of sib2, iclass 12, count 0 2006.253.08:19:30.63#ibcon#*mode == 0, iclass 12, count 0 2006.253.08:19:30.63#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.253.08:19:30.63#ibcon#[28=FRQ=01,632.99\r\n] 2006.253.08:19:30.63#ibcon#*before write, iclass 12, count 0 2006.253.08:19:30.63#ibcon#enter sib2, iclass 12, count 0 2006.253.08:19:30.63#ibcon#flushed, iclass 12, count 0 2006.253.08:19:30.63#ibcon#about to write, iclass 12, count 0 2006.253.08:19:30.63#ibcon#wrote, iclass 12, count 0 2006.253.08:19:30.63#ibcon#about to read 3, iclass 12, count 0 2006.253.08:19:30.66#ibcon#read 3, iclass 12, count 0 2006.253.08:19:30.66#ibcon#about to read 4, iclass 12, count 0 2006.253.08:19:30.66#ibcon#read 4, iclass 12, count 0 2006.253.08:19:30.66#ibcon#about to read 5, iclass 12, count 0 2006.253.08:19:30.67#ibcon#read 5, iclass 12, count 0 2006.253.08:19:30.67#ibcon#about to read 6, iclass 12, count 0 2006.253.08:19:30.67#ibcon#read 6, iclass 12, count 0 2006.253.08:19:30.67#ibcon#end of sib2, iclass 12, count 0 2006.253.08:19:30.67#ibcon#*after write, iclass 12, count 0 2006.253.08:19:30.67#ibcon#*before return 0, iclass 12, count 0 2006.253.08:19:30.67#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.253.08:19:30.67#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.253.08:19:30.67#ibcon#about to clear, iclass 12 cls_cnt 0 2006.253.08:19:30.67#ibcon#cleared, iclass 12 cls_cnt 0 2006.253.08:19:30.67$vc4f8/vb=1,4 2006.253.08:19:30.67#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.253.08:19:30.67#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.253.08:19:30.67#ibcon#ireg 11 cls_cnt 2 2006.253.08:19:30.67#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.253.08:19:30.67#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.253.08:19:30.67#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.253.08:19:30.67#ibcon#enter wrdev, iclass 14, count 2 2006.253.08:19:30.67#ibcon#first serial, iclass 14, count 2 2006.253.08:19:30.67#ibcon#enter sib2, iclass 14, count 2 2006.253.08:19:30.67#ibcon#flushed, iclass 14, count 2 2006.253.08:19:30.67#ibcon#about to write, iclass 14, count 2 2006.253.08:19:30.67#ibcon#wrote, iclass 14, count 2 2006.253.08:19:30.67#ibcon#about to read 3, iclass 14, count 2 2006.253.08:19:30.68#ibcon#read 3, iclass 14, count 2 2006.253.08:19:30.68#ibcon#about to read 4, iclass 14, count 2 2006.253.08:19:30.68#ibcon#read 4, iclass 14, count 2 2006.253.08:19:30.68#ibcon#about to read 5, iclass 14, count 2 2006.253.08:19:30.69#ibcon#read 5, iclass 14, count 2 2006.253.08:19:30.69#ibcon#about to read 6, iclass 14, count 2 2006.253.08:19:30.69#ibcon#read 6, iclass 14, count 2 2006.253.08:19:30.69#ibcon#end of sib2, iclass 14, count 2 2006.253.08:19:30.69#ibcon#*mode == 0, iclass 14, count 2 2006.253.08:19:30.69#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.253.08:19:30.69#ibcon#[27=AT01-04\r\n] 2006.253.08:19:30.69#ibcon#*before write, iclass 14, count 2 2006.253.08:19:30.69#ibcon#enter sib2, iclass 14, count 2 2006.253.08:19:30.69#ibcon#flushed, iclass 14, count 2 2006.253.08:19:30.69#ibcon#about to write, iclass 14, count 2 2006.253.08:19:30.69#ibcon#wrote, iclass 14, count 2 2006.253.08:19:30.69#ibcon#about to read 3, iclass 14, count 2 2006.253.08:19:30.71#ibcon#read 3, iclass 14, count 2 2006.253.08:19:30.71#ibcon#about to read 4, iclass 14, count 2 2006.253.08:19:30.71#ibcon#read 4, iclass 14, count 2 2006.253.08:19:30.71#ibcon#about to read 5, iclass 14, count 2 2006.253.08:19:30.72#ibcon#read 5, iclass 14, count 2 2006.253.08:19:30.72#ibcon#about to read 6, iclass 14, count 2 2006.253.08:19:30.72#ibcon#read 6, iclass 14, count 2 2006.253.08:19:30.72#ibcon#end of sib2, iclass 14, count 2 2006.253.08:19:30.72#ibcon#*after write, iclass 14, count 2 2006.253.08:19:30.72#ibcon#*before return 0, iclass 14, count 2 2006.253.08:19:30.72#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.253.08:19:30.72#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.253.08:19:30.72#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.253.08:19:30.72#ibcon#ireg 7 cls_cnt 0 2006.253.08:19:30.72#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.253.08:19:30.83#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.253.08:19:30.83#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.253.08:19:30.83#ibcon#enter wrdev, iclass 14, count 0 2006.253.08:19:30.83#ibcon#first serial, iclass 14, count 0 2006.253.08:19:30.83#ibcon#enter sib2, iclass 14, count 0 2006.253.08:19:30.83#ibcon#flushed, iclass 14, count 0 2006.253.08:19:30.84#ibcon#about to write, iclass 14, count 0 2006.253.08:19:30.84#ibcon#wrote, iclass 14, count 0 2006.253.08:19:30.84#ibcon#about to read 3, iclass 14, count 0 2006.253.08:19:30.85#ibcon#read 3, iclass 14, count 0 2006.253.08:19:30.85#ibcon#about to read 4, iclass 14, count 0 2006.253.08:19:30.85#ibcon#read 4, iclass 14, count 0 2006.253.08:19:30.85#ibcon#about to read 5, iclass 14, count 0 2006.253.08:19:30.86#ibcon#read 5, iclass 14, count 0 2006.253.08:19:30.86#ibcon#about to read 6, iclass 14, count 0 2006.253.08:19:30.86#ibcon#read 6, iclass 14, count 0 2006.253.08:19:30.86#ibcon#end of sib2, iclass 14, count 0 2006.253.08:19:30.86#ibcon#*mode == 0, iclass 14, count 0 2006.253.08:19:30.86#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.253.08:19:30.86#ibcon#[27=USB\r\n] 2006.253.08:19:30.86#ibcon#*before write, iclass 14, count 0 2006.253.08:19:30.86#ibcon#enter sib2, iclass 14, count 0 2006.253.08:19:30.86#ibcon#flushed, iclass 14, count 0 2006.253.08:19:30.86#ibcon#about to write, iclass 14, count 0 2006.253.08:19:30.86#ibcon#wrote, iclass 14, count 0 2006.253.08:19:30.86#ibcon#about to read 3, iclass 14, count 0 2006.253.08:19:30.88#ibcon#read 3, iclass 14, count 0 2006.253.08:19:30.88#ibcon#about to read 4, iclass 14, count 0 2006.253.08:19:30.88#ibcon#read 4, iclass 14, count 0 2006.253.08:19:30.88#ibcon#about to read 5, iclass 14, count 0 2006.253.08:19:30.89#ibcon#read 5, iclass 14, count 0 2006.253.08:19:30.89#ibcon#about to read 6, iclass 14, count 0 2006.253.08:19:30.89#ibcon#read 6, iclass 14, count 0 2006.253.08:19:30.89#ibcon#end of sib2, iclass 14, count 0 2006.253.08:19:30.89#ibcon#*after write, iclass 14, count 0 2006.253.08:19:30.89#ibcon#*before return 0, iclass 14, count 0 2006.253.08:19:30.89#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.253.08:19:30.89#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.253.08:19:30.89#ibcon#about to clear, iclass 14 cls_cnt 0 2006.253.08:19:30.89#ibcon#cleared, iclass 14 cls_cnt 0 2006.253.08:19:30.89$vc4f8/vblo=2,640.99 2006.253.08:19:30.89#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.253.08:19:30.89#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.253.08:19:30.89#ibcon#ireg 17 cls_cnt 0 2006.253.08:19:30.89#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.253.08:19:30.89#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.253.08:19:30.89#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.253.08:19:30.89#ibcon#enter wrdev, iclass 16, count 0 2006.253.08:19:30.89#ibcon#first serial, iclass 16, count 0 2006.253.08:19:30.89#ibcon#enter sib2, iclass 16, count 0 2006.253.08:19:30.89#ibcon#flushed, iclass 16, count 0 2006.253.08:19:30.89#ibcon#about to write, iclass 16, count 0 2006.253.08:19:30.89#ibcon#wrote, iclass 16, count 0 2006.253.08:19:30.89#ibcon#about to read 3, iclass 16, count 0 2006.253.08:19:30.90#ibcon#read 3, iclass 16, count 0 2006.253.08:19:30.90#ibcon#about to read 4, iclass 16, count 0 2006.253.08:19:30.90#ibcon#read 4, iclass 16, count 0 2006.253.08:19:30.90#ibcon#about to read 5, iclass 16, count 0 2006.253.08:19:30.91#ibcon#read 5, iclass 16, count 0 2006.253.08:19:30.91#ibcon#about to read 6, iclass 16, count 0 2006.253.08:19:30.91#ibcon#read 6, iclass 16, count 0 2006.253.08:19:30.91#ibcon#end of sib2, iclass 16, count 0 2006.253.08:19:30.91#ibcon#*mode == 0, iclass 16, count 0 2006.253.08:19:30.91#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.253.08:19:30.91#ibcon#[28=FRQ=02,640.99\r\n] 2006.253.08:19:30.91#ibcon#*before write, iclass 16, count 0 2006.253.08:19:30.91#ibcon#enter sib2, iclass 16, count 0 2006.253.08:19:30.91#ibcon#flushed, iclass 16, count 0 2006.253.08:19:30.91#ibcon#about to write, iclass 16, count 0 2006.253.08:19:30.91#ibcon#wrote, iclass 16, count 0 2006.253.08:19:30.91#ibcon#about to read 3, iclass 16, count 0 2006.253.08:19:30.94#ibcon#read 3, iclass 16, count 0 2006.253.08:19:30.94#ibcon#about to read 4, iclass 16, count 0 2006.253.08:19:30.94#ibcon#read 4, iclass 16, count 0 2006.253.08:19:30.94#ibcon#about to read 5, iclass 16, count 0 2006.253.08:19:30.95#ibcon#read 5, iclass 16, count 0 2006.253.08:19:30.95#ibcon#about to read 6, iclass 16, count 0 2006.253.08:19:30.95#ibcon#read 6, iclass 16, count 0 2006.253.08:19:30.95#ibcon#end of sib2, iclass 16, count 0 2006.253.08:19:30.95#ibcon#*after write, iclass 16, count 0 2006.253.08:19:30.95#ibcon#*before return 0, iclass 16, count 0 2006.253.08:19:30.95#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.253.08:19:30.95#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.253.08:19:30.95#ibcon#about to clear, iclass 16 cls_cnt 0 2006.253.08:19:30.95#ibcon#cleared, iclass 16 cls_cnt 0 2006.253.08:19:30.95$vc4f8/vb=2,5 2006.253.08:19:30.95#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.253.08:19:30.95#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.253.08:19:30.95#ibcon#ireg 11 cls_cnt 2 2006.253.08:19:30.95#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.253.08:19:31.01#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.253.08:19:31.01#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.253.08:19:31.01#ibcon#enter wrdev, iclass 18, count 2 2006.253.08:19:31.01#ibcon#first serial, iclass 18, count 2 2006.253.08:19:31.01#ibcon#enter sib2, iclass 18, count 2 2006.253.08:19:31.01#ibcon#flushed, iclass 18, count 2 2006.253.08:19:31.01#ibcon#about to write, iclass 18, count 2 2006.253.08:19:31.01#ibcon#wrote, iclass 18, count 2 2006.253.08:19:31.01#ibcon#about to read 3, iclass 18, count 2 2006.253.08:19:31.02#ibcon#read 3, iclass 18, count 2 2006.253.08:19:31.02#ibcon#about to read 4, iclass 18, count 2 2006.253.08:19:31.02#ibcon#read 4, iclass 18, count 2 2006.253.08:19:31.02#ibcon#about to read 5, iclass 18, count 2 2006.253.08:19:31.02#ibcon#read 5, iclass 18, count 2 2006.253.08:19:31.03#ibcon#about to read 6, iclass 18, count 2 2006.253.08:19:31.03#ibcon#read 6, iclass 18, count 2 2006.253.08:19:31.03#ibcon#end of sib2, iclass 18, count 2 2006.253.08:19:31.03#ibcon#*mode == 0, iclass 18, count 2 2006.253.08:19:31.03#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.253.08:19:31.03#ibcon#[27=AT02-05\r\n] 2006.253.08:19:31.03#ibcon#*before write, iclass 18, count 2 2006.253.08:19:31.03#ibcon#enter sib2, iclass 18, count 2 2006.253.08:19:31.03#ibcon#flushed, iclass 18, count 2 2006.253.08:19:31.03#ibcon#about to write, iclass 18, count 2 2006.253.08:19:31.03#ibcon#wrote, iclass 18, count 2 2006.253.08:19:31.03#ibcon#about to read 3, iclass 18, count 2 2006.253.08:19:31.06#ibcon#read 3, iclass 18, count 2 2006.253.08:19:31.06#ibcon#about to read 4, iclass 18, count 2 2006.253.08:19:31.06#ibcon#read 4, iclass 18, count 2 2006.253.08:19:31.06#ibcon#about to read 5, iclass 18, count 2 2006.253.08:19:31.06#ibcon#read 5, iclass 18, count 2 2006.253.08:19:31.06#ibcon#about to read 6, iclass 18, count 2 2006.253.08:19:31.06#ibcon#read 6, iclass 18, count 2 2006.253.08:19:31.06#ibcon#end of sib2, iclass 18, count 2 2006.253.08:19:31.06#ibcon#*after write, iclass 18, count 2 2006.253.08:19:31.06#ibcon#*before return 0, iclass 18, count 2 2006.253.08:19:31.06#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.253.08:19:31.06#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.253.08:19:31.06#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.253.08:19:31.06#ibcon#ireg 7 cls_cnt 0 2006.253.08:19:31.06#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.253.08:19:31.08#abcon#<5=/08 0.9 2.5 30.83 751006.6\r\n> 2006.253.08:19:31.10#abcon#{5=INTERFACE CLEAR} 2006.253.08:19:31.16#abcon#[5=S1D000X0/0*\r\n] 2006.253.08:19:31.17#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.253.08:19:31.17#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.253.08:19:31.17#ibcon#enter wrdev, iclass 18, count 0 2006.253.08:19:31.17#ibcon#first serial, iclass 18, count 0 2006.253.08:19:31.17#ibcon#enter sib2, iclass 18, count 0 2006.253.08:19:31.17#ibcon#flushed, iclass 18, count 0 2006.253.08:19:31.18#ibcon#about to write, iclass 18, count 0 2006.253.08:19:31.18#ibcon#wrote, iclass 18, count 0 2006.253.08:19:31.18#ibcon#about to read 3, iclass 18, count 0 2006.253.08:19:31.21#ibcon#read 3, iclass 18, count 0 2006.253.08:19:31.21#ibcon#about to read 4, iclass 18, count 0 2006.253.08:19:31.21#ibcon#read 4, iclass 18, count 0 2006.253.08:19:31.21#ibcon#about to read 5, iclass 18, count 0 2006.253.08:19:31.21#ibcon#read 5, iclass 18, count 0 2006.253.08:19:31.21#ibcon#about to read 6, iclass 18, count 0 2006.253.08:19:31.21#ibcon#read 6, iclass 18, count 0 2006.253.08:19:31.21#ibcon#end of sib2, iclass 18, count 0 2006.253.08:19:31.21#ibcon#*mode == 0, iclass 18, count 0 2006.253.08:19:31.21#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.253.08:19:31.21#ibcon#[27=USB\r\n] 2006.253.08:19:31.21#ibcon#*before write, iclass 18, count 0 2006.253.08:19:31.21#ibcon#enter sib2, iclass 18, count 0 2006.253.08:19:31.21#ibcon#flushed, iclass 18, count 0 2006.253.08:19:31.21#ibcon#about to write, iclass 18, count 0 2006.253.08:19:31.21#ibcon#wrote, iclass 18, count 0 2006.253.08:19:31.21#ibcon#about to read 3, iclass 18, count 0 2006.253.08:19:31.23#ibcon#read 3, iclass 18, count 0 2006.253.08:19:31.23#ibcon#about to read 4, iclass 18, count 0 2006.253.08:19:31.23#ibcon#read 4, iclass 18, count 0 2006.253.08:19:31.23#ibcon#about to read 5, iclass 18, count 0 2006.253.08:19:31.24#ibcon#read 5, iclass 18, count 0 2006.253.08:19:31.24#ibcon#about to read 6, iclass 18, count 0 2006.253.08:19:31.24#ibcon#read 6, iclass 18, count 0 2006.253.08:19:31.24#ibcon#end of sib2, iclass 18, count 0 2006.253.08:19:31.24#ibcon#*after write, iclass 18, count 0 2006.253.08:19:31.24#ibcon#*before return 0, iclass 18, count 0 2006.253.08:19:31.24#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.253.08:19:31.24#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.253.08:19:31.24#ibcon#about to clear, iclass 18 cls_cnt 0 2006.253.08:19:31.24#ibcon#cleared, iclass 18 cls_cnt 0 2006.253.08:19:31.24$vc4f8/vblo=3,656.99 2006.253.08:19:31.24#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.253.08:19:31.24#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.253.08:19:31.24#ibcon#ireg 17 cls_cnt 0 2006.253.08:19:31.24#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.253.08:19:31.24#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.253.08:19:31.24#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.253.08:19:31.24#ibcon#enter wrdev, iclass 24, count 0 2006.253.08:19:31.24#ibcon#first serial, iclass 24, count 0 2006.253.08:19:31.24#ibcon#enter sib2, iclass 24, count 0 2006.253.08:19:31.24#ibcon#flushed, iclass 24, count 0 2006.253.08:19:31.24#ibcon#about to write, iclass 24, count 0 2006.253.08:19:31.24#ibcon#wrote, iclass 24, count 0 2006.253.08:19:31.24#ibcon#about to read 3, iclass 24, count 0 2006.253.08:19:31.25#ibcon#read 3, iclass 24, count 0 2006.253.08:19:31.25#ibcon#about to read 4, iclass 24, count 0 2006.253.08:19:31.25#ibcon#read 4, iclass 24, count 0 2006.253.08:19:31.25#ibcon#about to read 5, iclass 24, count 0 2006.253.08:19:31.26#ibcon#read 5, iclass 24, count 0 2006.253.08:19:31.26#ibcon#about to read 6, iclass 24, count 0 2006.253.08:19:31.26#ibcon#read 6, iclass 24, count 0 2006.253.08:19:31.26#ibcon#end of sib2, iclass 24, count 0 2006.253.08:19:31.26#ibcon#*mode == 0, iclass 24, count 0 2006.253.08:19:31.26#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.253.08:19:31.26#ibcon#[28=FRQ=03,656.99\r\n] 2006.253.08:19:31.26#ibcon#*before write, iclass 24, count 0 2006.253.08:19:31.26#ibcon#enter sib2, iclass 24, count 0 2006.253.08:19:31.26#ibcon#flushed, iclass 24, count 0 2006.253.08:19:31.26#ibcon#about to write, iclass 24, count 0 2006.253.08:19:31.26#ibcon#wrote, iclass 24, count 0 2006.253.08:19:31.26#ibcon#about to read 3, iclass 24, count 0 2006.253.08:19:31.30#ibcon#read 3, iclass 24, count 0 2006.253.08:19:31.30#ibcon#about to read 4, iclass 24, count 0 2006.253.08:19:31.30#ibcon#read 4, iclass 24, count 0 2006.253.08:19:31.30#ibcon#about to read 5, iclass 24, count 0 2006.253.08:19:31.30#ibcon#read 5, iclass 24, count 0 2006.253.08:19:31.30#ibcon#about to read 6, iclass 24, count 0 2006.253.08:19:31.30#ibcon#read 6, iclass 24, count 0 2006.253.08:19:31.30#ibcon#end of sib2, iclass 24, count 0 2006.253.08:19:31.30#ibcon#*after write, iclass 24, count 0 2006.253.08:19:31.30#ibcon#*before return 0, iclass 24, count 0 2006.253.08:19:31.30#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.253.08:19:31.30#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.253.08:19:31.30#ibcon#about to clear, iclass 24 cls_cnt 0 2006.253.08:19:31.30#ibcon#cleared, iclass 24 cls_cnt 0 2006.253.08:19:31.30$vc4f8/vb=3,4 2006.253.08:19:31.30#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.253.08:19:31.30#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.253.08:19:31.30#ibcon#ireg 11 cls_cnt 2 2006.253.08:19:31.30#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.253.08:19:31.35#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.253.08:19:31.35#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.253.08:19:31.35#ibcon#enter wrdev, iclass 26, count 2 2006.253.08:19:31.35#ibcon#first serial, iclass 26, count 2 2006.253.08:19:31.35#ibcon#enter sib2, iclass 26, count 2 2006.253.08:19:31.35#ibcon#flushed, iclass 26, count 2 2006.253.08:19:31.36#ibcon#about to write, iclass 26, count 2 2006.253.08:19:31.36#ibcon#wrote, iclass 26, count 2 2006.253.08:19:31.36#ibcon#about to read 3, iclass 26, count 2 2006.253.08:19:31.37#ibcon#read 3, iclass 26, count 2 2006.253.08:19:31.37#ibcon#about to read 4, iclass 26, count 2 2006.253.08:19:31.37#ibcon#read 4, iclass 26, count 2 2006.253.08:19:31.37#ibcon#about to read 5, iclass 26, count 2 2006.253.08:19:31.37#ibcon#read 5, iclass 26, count 2 2006.253.08:19:31.38#ibcon#about to read 6, iclass 26, count 2 2006.253.08:19:31.38#ibcon#read 6, iclass 26, count 2 2006.253.08:19:31.38#ibcon#end of sib2, iclass 26, count 2 2006.253.08:19:31.38#ibcon#*mode == 0, iclass 26, count 2 2006.253.08:19:31.38#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.253.08:19:31.38#ibcon#[27=AT03-04\r\n] 2006.253.08:19:31.38#ibcon#*before write, iclass 26, count 2 2006.253.08:19:31.38#ibcon#enter sib2, iclass 26, count 2 2006.253.08:19:31.38#ibcon#flushed, iclass 26, count 2 2006.253.08:19:31.38#ibcon#about to write, iclass 26, count 2 2006.253.08:19:31.38#ibcon#wrote, iclass 26, count 2 2006.253.08:19:31.38#ibcon#about to read 3, iclass 26, count 2 2006.253.08:19:31.40#ibcon#read 3, iclass 26, count 2 2006.253.08:19:31.40#ibcon#about to read 4, iclass 26, count 2 2006.253.08:19:31.40#ibcon#read 4, iclass 26, count 2 2006.253.08:19:31.40#ibcon#about to read 5, iclass 26, count 2 2006.253.08:19:31.41#ibcon#read 5, iclass 26, count 2 2006.253.08:19:31.41#ibcon#about to read 6, iclass 26, count 2 2006.253.08:19:31.41#ibcon#read 6, iclass 26, count 2 2006.253.08:19:31.41#ibcon#end of sib2, iclass 26, count 2 2006.253.08:19:31.41#ibcon#*after write, iclass 26, count 2 2006.253.08:19:31.41#ibcon#*before return 0, iclass 26, count 2 2006.253.08:19:31.41#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.253.08:19:31.41#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.253.08:19:31.41#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.253.08:19:31.41#ibcon#ireg 7 cls_cnt 0 2006.253.08:19:31.41#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.253.08:19:31.52#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.253.08:19:31.52#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.253.08:19:31.52#ibcon#enter wrdev, iclass 26, count 0 2006.253.08:19:31.52#ibcon#first serial, iclass 26, count 0 2006.253.08:19:31.52#ibcon#enter sib2, iclass 26, count 0 2006.253.08:19:31.52#ibcon#flushed, iclass 26, count 0 2006.253.08:19:31.53#ibcon#about to write, iclass 26, count 0 2006.253.08:19:31.53#ibcon#wrote, iclass 26, count 0 2006.253.08:19:31.53#ibcon#about to read 3, iclass 26, count 0 2006.253.08:19:31.54#ibcon#read 3, iclass 26, count 0 2006.253.08:19:31.54#ibcon#about to read 4, iclass 26, count 0 2006.253.08:19:31.54#ibcon#read 4, iclass 26, count 0 2006.253.08:19:31.55#ibcon#about to read 5, iclass 26, count 0 2006.253.08:19:31.55#ibcon#read 5, iclass 26, count 0 2006.253.08:19:31.55#ibcon#about to read 6, iclass 26, count 0 2006.253.08:19:31.55#ibcon#read 6, iclass 26, count 0 2006.253.08:19:31.55#ibcon#end of sib2, iclass 26, count 0 2006.253.08:19:31.55#ibcon#*mode == 0, iclass 26, count 0 2006.253.08:19:31.55#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.253.08:19:31.55#ibcon#[27=USB\r\n] 2006.253.08:19:31.55#ibcon#*before write, iclass 26, count 0 2006.253.08:19:31.55#ibcon#enter sib2, iclass 26, count 0 2006.253.08:19:31.55#ibcon#flushed, iclass 26, count 0 2006.253.08:19:31.55#ibcon#about to write, iclass 26, count 0 2006.253.08:19:31.55#ibcon#wrote, iclass 26, count 0 2006.253.08:19:31.55#ibcon#about to read 3, iclass 26, count 0 2006.253.08:19:31.57#ibcon#read 3, iclass 26, count 0 2006.253.08:19:31.57#ibcon#about to read 4, iclass 26, count 0 2006.253.08:19:31.57#ibcon#read 4, iclass 26, count 0 2006.253.08:19:31.57#ibcon#about to read 5, iclass 26, count 0 2006.253.08:19:31.57#ibcon#read 5, iclass 26, count 0 2006.253.08:19:31.58#ibcon#about to read 6, iclass 26, count 0 2006.253.08:19:31.58#ibcon#read 6, iclass 26, count 0 2006.253.08:19:31.58#ibcon#end of sib2, iclass 26, count 0 2006.253.08:19:31.58#ibcon#*after write, iclass 26, count 0 2006.253.08:19:31.58#ibcon#*before return 0, iclass 26, count 0 2006.253.08:19:31.58#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.253.08:19:31.58#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.253.08:19:31.58#ibcon#about to clear, iclass 26 cls_cnt 0 2006.253.08:19:31.58#ibcon#cleared, iclass 26 cls_cnt 0 2006.253.08:19:31.58$vc4f8/vblo=4,712.99 2006.253.08:19:31.58#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.253.08:19:31.58#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.253.08:19:31.58#ibcon#ireg 17 cls_cnt 0 2006.253.08:19:31.58#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.253.08:19:31.58#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.253.08:19:31.58#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.253.08:19:31.58#ibcon#enter wrdev, iclass 28, count 0 2006.253.08:19:31.58#ibcon#first serial, iclass 28, count 0 2006.253.08:19:31.58#ibcon#enter sib2, iclass 28, count 0 2006.253.08:19:31.58#ibcon#flushed, iclass 28, count 0 2006.253.08:19:31.58#ibcon#about to write, iclass 28, count 0 2006.253.08:19:31.58#ibcon#wrote, iclass 28, count 0 2006.253.08:19:31.58#ibcon#about to read 3, iclass 28, count 0 2006.253.08:19:31.59#ibcon#read 3, iclass 28, count 0 2006.253.08:19:31.59#ibcon#about to read 4, iclass 28, count 0 2006.253.08:19:31.59#ibcon#read 4, iclass 28, count 0 2006.253.08:19:31.59#ibcon#about to read 5, iclass 28, count 0 2006.253.08:19:31.59#ibcon#read 5, iclass 28, count 0 2006.253.08:19:31.60#ibcon#about to read 6, iclass 28, count 0 2006.253.08:19:31.60#ibcon#read 6, iclass 28, count 0 2006.253.08:19:31.60#ibcon#end of sib2, iclass 28, count 0 2006.253.08:19:31.60#ibcon#*mode == 0, iclass 28, count 0 2006.253.08:19:31.60#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.253.08:19:31.60#ibcon#[28=FRQ=04,712.99\r\n] 2006.253.08:19:31.60#ibcon#*before write, iclass 28, count 0 2006.253.08:19:31.60#ibcon#enter sib2, iclass 28, count 0 2006.253.08:19:31.60#ibcon#flushed, iclass 28, count 0 2006.253.08:19:31.60#ibcon#about to write, iclass 28, count 0 2006.253.08:19:31.60#ibcon#wrote, iclass 28, count 0 2006.253.08:19:31.60#ibcon#about to read 3, iclass 28, count 0 2006.253.08:19:31.63#ibcon#read 3, iclass 28, count 0 2006.253.08:19:31.63#ibcon#about to read 4, iclass 28, count 0 2006.253.08:19:31.63#ibcon#read 4, iclass 28, count 0 2006.253.08:19:31.63#ibcon#about to read 5, iclass 28, count 0 2006.253.08:19:31.64#ibcon#read 5, iclass 28, count 0 2006.253.08:19:31.64#ibcon#about to read 6, iclass 28, count 0 2006.253.08:19:31.64#ibcon#read 6, iclass 28, count 0 2006.253.08:19:31.64#ibcon#end of sib2, iclass 28, count 0 2006.253.08:19:31.64#ibcon#*after write, iclass 28, count 0 2006.253.08:19:31.64#ibcon#*before return 0, iclass 28, count 0 2006.253.08:19:31.64#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.253.08:19:31.64#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.253.08:19:31.64#ibcon#about to clear, iclass 28 cls_cnt 0 2006.253.08:19:31.64#ibcon#cleared, iclass 28 cls_cnt 0 2006.253.08:19:31.64$vc4f8/vb=4,4 2006.253.08:19:31.64#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.253.08:19:31.64#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.253.08:19:31.64#ibcon#ireg 11 cls_cnt 2 2006.253.08:19:31.64#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.253.08:19:31.69#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.253.08:19:31.69#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.253.08:19:31.69#ibcon#enter wrdev, iclass 30, count 2 2006.253.08:19:31.69#ibcon#first serial, iclass 30, count 2 2006.253.08:19:31.69#ibcon#enter sib2, iclass 30, count 2 2006.253.08:19:31.69#ibcon#flushed, iclass 30, count 2 2006.253.08:19:31.70#ibcon#about to write, iclass 30, count 2 2006.253.08:19:31.70#ibcon#wrote, iclass 30, count 2 2006.253.08:19:31.70#ibcon#about to read 3, iclass 30, count 2 2006.253.08:19:31.71#ibcon#read 3, iclass 30, count 2 2006.253.08:19:31.71#ibcon#about to read 4, iclass 30, count 2 2006.253.08:19:31.71#ibcon#read 4, iclass 30, count 2 2006.253.08:19:31.71#ibcon#about to read 5, iclass 30, count 2 2006.253.08:19:31.72#ibcon#read 5, iclass 30, count 2 2006.253.08:19:31.72#ibcon#about to read 6, iclass 30, count 2 2006.253.08:19:31.72#ibcon#read 6, iclass 30, count 2 2006.253.08:19:31.72#ibcon#end of sib2, iclass 30, count 2 2006.253.08:19:31.72#ibcon#*mode == 0, iclass 30, count 2 2006.253.08:19:31.72#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.253.08:19:31.72#ibcon#[27=AT04-04\r\n] 2006.253.08:19:31.72#ibcon#*before write, iclass 30, count 2 2006.253.08:19:31.72#ibcon#enter sib2, iclass 30, count 2 2006.253.08:19:31.72#ibcon#flushed, iclass 30, count 2 2006.253.08:19:31.72#ibcon#about to write, iclass 30, count 2 2006.253.08:19:31.72#ibcon#wrote, iclass 30, count 2 2006.253.08:19:31.72#ibcon#about to read 3, iclass 30, count 2 2006.253.08:19:31.74#ibcon#read 3, iclass 30, count 2 2006.253.08:19:31.74#ibcon#about to read 4, iclass 30, count 2 2006.253.08:19:31.75#ibcon#read 4, iclass 30, count 2 2006.253.08:19:31.75#ibcon#about to read 5, iclass 30, count 2 2006.253.08:19:31.75#ibcon#read 5, iclass 30, count 2 2006.253.08:19:31.75#ibcon#about to read 6, iclass 30, count 2 2006.253.08:19:31.75#ibcon#read 6, iclass 30, count 2 2006.253.08:19:31.75#ibcon#end of sib2, iclass 30, count 2 2006.253.08:19:31.75#ibcon#*after write, iclass 30, count 2 2006.253.08:19:31.75#ibcon#*before return 0, iclass 30, count 2 2006.253.08:19:31.75#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.253.08:19:31.75#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.253.08:19:31.75#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.253.08:19:31.75#ibcon#ireg 7 cls_cnt 0 2006.253.08:19:31.75#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.253.08:19:31.86#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.253.08:19:31.86#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.253.08:19:31.86#ibcon#enter wrdev, iclass 30, count 0 2006.253.08:19:31.86#ibcon#first serial, iclass 30, count 0 2006.253.08:19:31.86#ibcon#enter sib2, iclass 30, count 0 2006.253.08:19:31.86#ibcon#flushed, iclass 30, count 0 2006.253.08:19:31.87#ibcon#about to write, iclass 30, count 0 2006.253.08:19:31.87#ibcon#wrote, iclass 30, count 0 2006.253.08:19:31.87#ibcon#about to read 3, iclass 30, count 0 2006.253.08:19:31.88#ibcon#read 3, iclass 30, count 0 2006.253.08:19:31.88#ibcon#about to read 4, iclass 30, count 0 2006.253.08:19:31.88#ibcon#read 4, iclass 30, count 0 2006.253.08:19:31.88#ibcon#about to read 5, iclass 30, count 0 2006.253.08:19:31.88#ibcon#read 5, iclass 30, count 0 2006.253.08:19:31.89#ibcon#about to read 6, iclass 30, count 0 2006.253.08:19:31.89#ibcon#read 6, iclass 30, count 0 2006.253.08:19:31.89#ibcon#end of sib2, iclass 30, count 0 2006.253.08:19:31.89#ibcon#*mode == 0, iclass 30, count 0 2006.253.08:19:31.89#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.253.08:19:31.89#ibcon#[27=USB\r\n] 2006.253.08:19:31.89#ibcon#*before write, iclass 30, count 0 2006.253.08:19:31.89#ibcon#enter sib2, iclass 30, count 0 2006.253.08:19:31.89#ibcon#flushed, iclass 30, count 0 2006.253.08:19:31.89#ibcon#about to write, iclass 30, count 0 2006.253.08:19:31.89#ibcon#wrote, iclass 30, count 0 2006.253.08:19:31.89#ibcon#about to read 3, iclass 30, count 0 2006.253.08:19:31.91#ibcon#read 3, iclass 30, count 0 2006.253.08:19:31.91#ibcon#about to read 4, iclass 30, count 0 2006.253.08:19:31.91#ibcon#read 4, iclass 30, count 0 2006.253.08:19:31.91#ibcon#about to read 5, iclass 30, count 0 2006.253.08:19:31.91#ibcon#read 5, iclass 30, count 0 2006.253.08:19:31.92#ibcon#about to read 6, iclass 30, count 0 2006.253.08:19:31.92#ibcon#read 6, iclass 30, count 0 2006.253.08:19:31.92#ibcon#end of sib2, iclass 30, count 0 2006.253.08:19:31.92#ibcon#*after write, iclass 30, count 0 2006.253.08:19:31.92#ibcon#*before return 0, iclass 30, count 0 2006.253.08:19:31.92#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.253.08:19:31.92#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.253.08:19:31.92#ibcon#about to clear, iclass 30 cls_cnt 0 2006.253.08:19:31.92#ibcon#cleared, iclass 30 cls_cnt 0 2006.253.08:19:31.92$vc4f8/vblo=5,744.99 2006.253.08:19:31.92#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.253.08:19:31.92#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.253.08:19:31.92#ibcon#ireg 17 cls_cnt 0 2006.253.08:19:31.92#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.253.08:19:31.92#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.253.08:19:31.92#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.253.08:19:31.92#ibcon#enter wrdev, iclass 32, count 0 2006.253.08:19:31.92#ibcon#first serial, iclass 32, count 0 2006.253.08:19:31.92#ibcon#enter sib2, iclass 32, count 0 2006.253.08:19:31.92#ibcon#flushed, iclass 32, count 0 2006.253.08:19:31.92#ibcon#about to write, iclass 32, count 0 2006.253.08:19:31.92#ibcon#wrote, iclass 32, count 0 2006.253.08:19:31.92#ibcon#about to read 3, iclass 32, count 0 2006.253.08:19:31.93#ibcon#read 3, iclass 32, count 0 2006.253.08:19:31.93#ibcon#about to read 4, iclass 32, count 0 2006.253.08:19:31.93#ibcon#read 4, iclass 32, count 0 2006.253.08:19:31.93#ibcon#about to read 5, iclass 32, count 0 2006.253.08:19:31.93#ibcon#read 5, iclass 32, count 0 2006.253.08:19:31.94#ibcon#about to read 6, iclass 32, count 0 2006.253.08:19:31.94#ibcon#read 6, iclass 32, count 0 2006.253.08:19:31.94#ibcon#end of sib2, iclass 32, count 0 2006.253.08:19:31.94#ibcon#*mode == 0, iclass 32, count 0 2006.253.08:19:31.94#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.253.08:19:31.94#ibcon#[28=FRQ=05,744.99\r\n] 2006.253.08:19:31.94#ibcon#*before write, iclass 32, count 0 2006.253.08:19:31.94#ibcon#enter sib2, iclass 32, count 0 2006.253.08:19:31.94#ibcon#flushed, iclass 32, count 0 2006.253.08:19:31.94#ibcon#about to write, iclass 32, count 0 2006.253.08:19:31.94#ibcon#wrote, iclass 32, count 0 2006.253.08:19:31.94#ibcon#about to read 3, iclass 32, count 0 2006.253.08:19:31.97#ibcon#read 3, iclass 32, count 0 2006.253.08:19:31.97#ibcon#about to read 4, iclass 32, count 0 2006.253.08:19:31.97#ibcon#read 4, iclass 32, count 0 2006.253.08:19:31.97#ibcon#about to read 5, iclass 32, count 0 2006.253.08:19:31.98#ibcon#read 5, iclass 32, count 0 2006.253.08:19:31.98#ibcon#about to read 6, iclass 32, count 0 2006.253.08:19:31.98#ibcon#read 6, iclass 32, count 0 2006.253.08:19:31.98#ibcon#end of sib2, iclass 32, count 0 2006.253.08:19:31.98#ibcon#*after write, iclass 32, count 0 2006.253.08:19:31.98#ibcon#*before return 0, iclass 32, count 0 2006.253.08:19:31.98#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.253.08:19:31.98#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.253.08:19:31.98#ibcon#about to clear, iclass 32 cls_cnt 0 2006.253.08:19:31.98#ibcon#cleared, iclass 32 cls_cnt 0 2006.253.08:19:31.98$vc4f8/vb=5,4 2006.253.08:19:31.98#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.253.08:19:31.98#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.253.08:19:31.98#ibcon#ireg 11 cls_cnt 2 2006.253.08:19:31.98#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.253.08:19:32.04#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.253.08:19:32.04#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.253.08:19:32.04#ibcon#enter wrdev, iclass 34, count 2 2006.253.08:19:32.04#ibcon#first serial, iclass 34, count 2 2006.253.08:19:32.04#ibcon#enter sib2, iclass 34, count 2 2006.253.08:19:32.04#ibcon#flushed, iclass 34, count 2 2006.253.08:19:32.04#ibcon#about to write, iclass 34, count 2 2006.253.08:19:32.04#ibcon#wrote, iclass 34, count 2 2006.253.08:19:32.04#ibcon#about to read 3, iclass 34, count 2 2006.253.08:19:32.05#ibcon#read 3, iclass 34, count 2 2006.253.08:19:32.05#ibcon#about to read 4, iclass 34, count 2 2006.253.08:19:32.06#ibcon#read 4, iclass 34, count 2 2006.253.08:19:32.06#ibcon#about to read 5, iclass 34, count 2 2006.253.08:19:32.06#ibcon#read 5, iclass 34, count 2 2006.253.08:19:32.06#ibcon#about to read 6, iclass 34, count 2 2006.253.08:19:32.06#ibcon#read 6, iclass 34, count 2 2006.253.08:19:32.06#ibcon#end of sib2, iclass 34, count 2 2006.253.08:19:32.06#ibcon#*mode == 0, iclass 34, count 2 2006.253.08:19:32.06#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.253.08:19:32.06#ibcon#[27=AT05-04\r\n] 2006.253.08:19:32.06#ibcon#*before write, iclass 34, count 2 2006.253.08:19:32.06#ibcon#enter sib2, iclass 34, count 2 2006.253.08:19:32.06#ibcon#flushed, iclass 34, count 2 2006.253.08:19:32.06#ibcon#about to write, iclass 34, count 2 2006.253.08:19:32.06#ibcon#wrote, iclass 34, count 2 2006.253.08:19:32.06#ibcon#about to read 3, iclass 34, count 2 2006.253.08:19:32.08#ibcon#read 3, iclass 34, count 2 2006.253.08:19:32.08#ibcon#about to read 4, iclass 34, count 2 2006.253.08:19:32.09#ibcon#read 4, iclass 34, count 2 2006.253.08:19:32.09#ibcon#about to read 5, iclass 34, count 2 2006.253.08:19:32.09#ibcon#read 5, iclass 34, count 2 2006.253.08:19:32.09#ibcon#about to read 6, iclass 34, count 2 2006.253.08:19:32.09#ibcon#read 6, iclass 34, count 2 2006.253.08:19:32.09#ibcon#end of sib2, iclass 34, count 2 2006.253.08:19:32.09#ibcon#*after write, iclass 34, count 2 2006.253.08:19:32.09#ibcon#*before return 0, iclass 34, count 2 2006.253.08:19:32.09#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.253.08:19:32.09#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.253.08:19:32.09#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.253.08:19:32.09#ibcon#ireg 7 cls_cnt 0 2006.253.08:19:32.09#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.253.08:19:32.20#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.253.08:19:32.20#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.253.08:19:32.20#ibcon#enter wrdev, iclass 34, count 0 2006.253.08:19:32.20#ibcon#first serial, iclass 34, count 0 2006.253.08:19:32.20#ibcon#enter sib2, iclass 34, count 0 2006.253.08:19:32.20#ibcon#flushed, iclass 34, count 0 2006.253.08:19:32.21#ibcon#about to write, iclass 34, count 0 2006.253.08:19:32.21#ibcon#wrote, iclass 34, count 0 2006.253.08:19:32.21#ibcon#about to read 3, iclass 34, count 0 2006.253.08:19:32.22#ibcon#read 3, iclass 34, count 0 2006.253.08:19:32.22#ibcon#about to read 4, iclass 34, count 0 2006.253.08:19:32.22#ibcon#read 4, iclass 34, count 0 2006.253.08:19:32.22#ibcon#about to read 5, iclass 34, count 0 2006.253.08:19:32.22#ibcon#read 5, iclass 34, count 0 2006.253.08:19:32.23#ibcon#about to read 6, iclass 34, count 0 2006.253.08:19:32.23#ibcon#read 6, iclass 34, count 0 2006.253.08:19:32.23#ibcon#end of sib2, iclass 34, count 0 2006.253.08:19:32.23#ibcon#*mode == 0, iclass 34, count 0 2006.253.08:19:32.23#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.253.08:19:32.23#ibcon#[27=USB\r\n] 2006.253.08:19:32.23#ibcon#*before write, iclass 34, count 0 2006.253.08:19:32.23#ibcon#enter sib2, iclass 34, count 0 2006.253.08:19:32.23#ibcon#flushed, iclass 34, count 0 2006.253.08:19:32.23#ibcon#about to write, iclass 34, count 0 2006.253.08:19:32.23#ibcon#wrote, iclass 34, count 0 2006.253.08:19:32.23#ibcon#about to read 3, iclass 34, count 0 2006.253.08:19:32.25#ibcon#read 3, iclass 34, count 0 2006.253.08:19:32.25#ibcon#about to read 4, iclass 34, count 0 2006.253.08:19:32.25#ibcon#read 4, iclass 34, count 0 2006.253.08:19:32.25#ibcon#about to read 5, iclass 34, count 0 2006.253.08:19:32.25#ibcon#read 5, iclass 34, count 0 2006.253.08:19:32.26#ibcon#about to read 6, iclass 34, count 0 2006.253.08:19:32.26#ibcon#read 6, iclass 34, count 0 2006.253.08:19:32.26#ibcon#end of sib2, iclass 34, count 0 2006.253.08:19:32.26#ibcon#*after write, iclass 34, count 0 2006.253.08:19:32.26#ibcon#*before return 0, iclass 34, count 0 2006.253.08:19:32.26#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.253.08:19:32.26#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.253.08:19:32.26#ibcon#about to clear, iclass 34 cls_cnt 0 2006.253.08:19:32.26#ibcon#cleared, iclass 34 cls_cnt 0 2006.253.08:19:32.26$vc4f8/vblo=6,752.99 2006.253.08:19:32.26#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.253.08:19:32.26#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.253.08:19:32.26#ibcon#ireg 17 cls_cnt 0 2006.253.08:19:32.26#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.253.08:19:32.26#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.253.08:19:32.26#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.253.08:19:32.26#ibcon#enter wrdev, iclass 36, count 0 2006.253.08:19:32.26#ibcon#first serial, iclass 36, count 0 2006.253.08:19:32.26#ibcon#enter sib2, iclass 36, count 0 2006.253.08:19:32.26#ibcon#flushed, iclass 36, count 0 2006.253.08:19:32.26#ibcon#about to write, iclass 36, count 0 2006.253.08:19:32.26#ibcon#wrote, iclass 36, count 0 2006.253.08:19:32.26#ibcon#about to read 3, iclass 36, count 0 2006.253.08:19:32.27#ibcon#read 3, iclass 36, count 0 2006.253.08:19:32.27#ibcon#about to read 4, iclass 36, count 0 2006.253.08:19:32.27#ibcon#read 4, iclass 36, count 0 2006.253.08:19:32.27#ibcon#about to read 5, iclass 36, count 0 2006.253.08:19:32.28#ibcon#read 5, iclass 36, count 0 2006.253.08:19:32.28#ibcon#about to read 6, iclass 36, count 0 2006.253.08:19:32.28#ibcon#read 6, iclass 36, count 0 2006.253.08:19:32.28#ibcon#end of sib2, iclass 36, count 0 2006.253.08:19:32.28#ibcon#*mode == 0, iclass 36, count 0 2006.253.08:19:32.28#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.253.08:19:32.28#ibcon#[28=FRQ=06,752.99\r\n] 2006.253.08:19:32.28#ibcon#*before write, iclass 36, count 0 2006.253.08:19:32.28#ibcon#enter sib2, iclass 36, count 0 2006.253.08:19:32.28#ibcon#flushed, iclass 36, count 0 2006.253.08:19:32.28#ibcon#about to write, iclass 36, count 0 2006.253.08:19:32.28#ibcon#wrote, iclass 36, count 0 2006.253.08:19:32.28#ibcon#about to read 3, iclass 36, count 0 2006.253.08:19:32.31#ibcon#read 3, iclass 36, count 0 2006.253.08:19:32.31#ibcon#about to read 4, iclass 36, count 0 2006.253.08:19:32.31#ibcon#read 4, iclass 36, count 0 2006.253.08:19:32.31#ibcon#about to read 5, iclass 36, count 0 2006.253.08:19:32.31#ibcon#read 5, iclass 36, count 0 2006.253.08:19:32.32#ibcon#about to read 6, iclass 36, count 0 2006.253.08:19:32.32#ibcon#read 6, iclass 36, count 0 2006.253.08:19:32.32#ibcon#end of sib2, iclass 36, count 0 2006.253.08:19:32.32#ibcon#*after write, iclass 36, count 0 2006.253.08:19:32.32#ibcon#*before return 0, iclass 36, count 0 2006.253.08:19:32.32#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.253.08:19:32.32#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.253.08:19:32.32#ibcon#about to clear, iclass 36 cls_cnt 0 2006.253.08:19:32.32#ibcon#cleared, iclass 36 cls_cnt 0 2006.253.08:19:32.32$vc4f8/vb=6,4 2006.253.08:19:32.32#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.253.08:19:32.32#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.253.08:19:32.32#ibcon#ireg 11 cls_cnt 2 2006.253.08:19:32.32#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.253.08:19:32.37#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.253.08:19:32.37#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.253.08:19:32.37#ibcon#enter wrdev, iclass 38, count 2 2006.253.08:19:32.37#ibcon#first serial, iclass 38, count 2 2006.253.08:19:32.37#ibcon#enter sib2, iclass 38, count 2 2006.253.08:19:32.37#ibcon#flushed, iclass 38, count 2 2006.253.08:19:32.38#ibcon#about to write, iclass 38, count 2 2006.253.08:19:32.38#ibcon#wrote, iclass 38, count 2 2006.253.08:19:32.38#ibcon#about to read 3, iclass 38, count 2 2006.253.08:19:32.39#ibcon#read 3, iclass 38, count 2 2006.253.08:19:32.39#ibcon#about to read 4, iclass 38, count 2 2006.253.08:19:32.39#ibcon#read 4, iclass 38, count 2 2006.253.08:19:32.39#ibcon#about to read 5, iclass 38, count 2 2006.253.08:19:32.39#ibcon#read 5, iclass 38, count 2 2006.253.08:19:32.39#ibcon#about to read 6, iclass 38, count 2 2006.253.08:19:32.40#ibcon#read 6, iclass 38, count 2 2006.253.08:19:32.40#ibcon#end of sib2, iclass 38, count 2 2006.253.08:19:32.40#ibcon#*mode == 0, iclass 38, count 2 2006.253.08:19:32.40#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.253.08:19:32.40#ibcon#[27=AT06-04\r\n] 2006.253.08:19:32.40#ibcon#*before write, iclass 38, count 2 2006.253.08:19:32.40#ibcon#enter sib2, iclass 38, count 2 2006.253.08:19:32.40#ibcon#flushed, iclass 38, count 2 2006.253.08:19:32.40#ibcon#about to write, iclass 38, count 2 2006.253.08:19:32.40#ibcon#wrote, iclass 38, count 2 2006.253.08:19:32.40#ibcon#about to read 3, iclass 38, count 2 2006.253.08:19:32.42#ibcon#read 3, iclass 38, count 2 2006.253.08:19:32.42#ibcon#about to read 4, iclass 38, count 2 2006.253.08:19:32.42#ibcon#read 4, iclass 38, count 2 2006.253.08:19:32.42#ibcon#about to read 5, iclass 38, count 2 2006.253.08:19:32.42#ibcon#read 5, iclass 38, count 2 2006.253.08:19:32.43#ibcon#about to read 6, iclass 38, count 2 2006.253.08:19:32.43#ibcon#read 6, iclass 38, count 2 2006.253.08:19:32.43#ibcon#end of sib2, iclass 38, count 2 2006.253.08:19:32.43#ibcon#*after write, iclass 38, count 2 2006.253.08:19:32.43#ibcon#*before return 0, iclass 38, count 2 2006.253.08:19:32.43#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.253.08:19:32.43#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.253.08:19:32.43#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.253.08:19:32.43#ibcon#ireg 7 cls_cnt 0 2006.253.08:19:32.43#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.253.08:19:32.54#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.253.08:19:32.54#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.253.08:19:32.54#ibcon#enter wrdev, iclass 38, count 0 2006.253.08:19:32.54#ibcon#first serial, iclass 38, count 0 2006.253.08:19:32.54#ibcon#enter sib2, iclass 38, count 0 2006.253.08:19:32.54#ibcon#flushed, iclass 38, count 0 2006.253.08:19:32.55#ibcon#about to write, iclass 38, count 0 2006.253.08:19:32.55#ibcon#wrote, iclass 38, count 0 2006.253.08:19:32.55#ibcon#about to read 3, iclass 38, count 0 2006.253.08:19:32.56#ibcon#read 3, iclass 38, count 0 2006.253.08:19:32.56#ibcon#about to read 4, iclass 38, count 0 2006.253.08:19:32.56#ibcon#read 4, iclass 38, count 0 2006.253.08:19:32.56#ibcon#about to read 5, iclass 38, count 0 2006.253.08:19:32.56#ibcon#read 5, iclass 38, count 0 2006.253.08:19:32.57#ibcon#about to read 6, iclass 38, count 0 2006.253.08:19:32.57#ibcon#read 6, iclass 38, count 0 2006.253.08:19:32.57#ibcon#end of sib2, iclass 38, count 0 2006.253.08:19:32.57#ibcon#*mode == 0, iclass 38, count 0 2006.253.08:19:32.57#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.253.08:19:32.57#ibcon#[27=USB\r\n] 2006.253.08:19:32.57#ibcon#*before write, iclass 38, count 0 2006.253.08:19:32.57#ibcon#enter sib2, iclass 38, count 0 2006.253.08:19:32.57#ibcon#flushed, iclass 38, count 0 2006.253.08:19:32.57#ibcon#about to write, iclass 38, count 0 2006.253.08:19:32.57#ibcon#wrote, iclass 38, count 0 2006.253.08:19:32.57#ibcon#about to read 3, iclass 38, count 0 2006.253.08:19:32.59#ibcon#read 3, iclass 38, count 0 2006.253.08:19:32.59#ibcon#about to read 4, iclass 38, count 0 2006.253.08:19:32.59#ibcon#read 4, iclass 38, count 0 2006.253.08:19:32.59#ibcon#about to read 5, iclass 38, count 0 2006.253.08:19:32.59#ibcon#read 5, iclass 38, count 0 2006.253.08:19:32.60#ibcon#about to read 6, iclass 38, count 0 2006.253.08:19:32.60#ibcon#read 6, iclass 38, count 0 2006.253.08:19:32.60#ibcon#end of sib2, iclass 38, count 0 2006.253.08:19:32.60#ibcon#*after write, iclass 38, count 0 2006.253.08:19:32.60#ibcon#*before return 0, iclass 38, count 0 2006.253.08:19:32.60#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.253.08:19:32.60#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.253.08:19:32.60#ibcon#about to clear, iclass 38 cls_cnt 0 2006.253.08:19:32.60#ibcon#cleared, iclass 38 cls_cnt 0 2006.253.08:19:32.60$vc4f8/vabw=wide 2006.253.08:19:32.60#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.253.08:19:32.60#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.253.08:19:32.60#ibcon#ireg 8 cls_cnt 0 2006.253.08:19:32.60#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.253.08:19:32.60#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.253.08:19:32.60#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.253.08:19:32.60#ibcon#enter wrdev, iclass 40, count 0 2006.253.08:19:32.60#ibcon#first serial, iclass 40, count 0 2006.253.08:19:32.60#ibcon#enter sib2, iclass 40, count 0 2006.253.08:19:32.60#ibcon#flushed, iclass 40, count 0 2006.253.08:19:32.60#ibcon#about to write, iclass 40, count 0 2006.253.08:19:32.60#ibcon#wrote, iclass 40, count 0 2006.253.08:19:32.60#ibcon#about to read 3, iclass 40, count 0 2006.253.08:19:32.61#ibcon#read 3, iclass 40, count 0 2006.253.08:19:32.61#ibcon#about to read 4, iclass 40, count 0 2006.253.08:19:32.61#ibcon#read 4, iclass 40, count 0 2006.253.08:19:32.61#ibcon#about to read 5, iclass 40, count 0 2006.253.08:19:32.61#ibcon#read 5, iclass 40, count 0 2006.253.08:19:32.62#ibcon#about to read 6, iclass 40, count 0 2006.253.08:19:32.62#ibcon#read 6, iclass 40, count 0 2006.253.08:19:32.62#ibcon#end of sib2, iclass 40, count 0 2006.253.08:19:32.62#ibcon#*mode == 0, iclass 40, count 0 2006.253.08:19:32.62#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.253.08:19:32.62#ibcon#[25=BW32\r\n] 2006.253.08:19:32.62#ibcon#*before write, iclass 40, count 0 2006.253.08:19:32.62#ibcon#enter sib2, iclass 40, count 0 2006.253.08:19:32.62#ibcon#flushed, iclass 40, count 0 2006.253.08:19:32.62#ibcon#about to write, iclass 40, count 0 2006.253.08:19:32.62#ibcon#wrote, iclass 40, count 0 2006.253.08:19:32.62#ibcon#about to read 3, iclass 40, count 0 2006.253.08:19:32.64#ibcon#read 3, iclass 40, count 0 2006.253.08:19:32.64#ibcon#about to read 4, iclass 40, count 0 2006.253.08:19:32.64#ibcon#read 4, iclass 40, count 0 2006.253.08:19:32.64#ibcon#about to read 5, iclass 40, count 0 2006.253.08:19:32.64#ibcon#read 5, iclass 40, count 0 2006.253.08:19:32.65#ibcon#about to read 6, iclass 40, count 0 2006.253.08:19:32.65#ibcon#read 6, iclass 40, count 0 2006.253.08:19:32.65#ibcon#end of sib2, iclass 40, count 0 2006.253.08:19:32.65#ibcon#*after write, iclass 40, count 0 2006.253.08:19:32.65#ibcon#*before return 0, iclass 40, count 0 2006.253.08:19:32.65#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.253.08:19:32.65#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.253.08:19:32.65#ibcon#about to clear, iclass 40 cls_cnt 0 2006.253.08:19:32.65#ibcon#cleared, iclass 40 cls_cnt 0 2006.253.08:19:32.65$vc4f8/vbbw=wide 2006.253.08:19:32.65#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.253.08:19:32.65#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.253.08:19:32.65#ibcon#ireg 8 cls_cnt 0 2006.253.08:19:32.65#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.253.08:19:32.71#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.253.08:19:32.71#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.253.08:19:32.71#ibcon#enter wrdev, iclass 4, count 0 2006.253.08:19:32.71#ibcon#first serial, iclass 4, count 0 2006.253.08:19:32.71#ibcon#enter sib2, iclass 4, count 0 2006.253.08:19:32.71#ibcon#flushed, iclass 4, count 0 2006.253.08:19:32.71#ibcon#about to write, iclass 4, count 0 2006.253.08:19:32.72#ibcon#wrote, iclass 4, count 0 2006.253.08:19:32.72#ibcon#about to read 3, iclass 4, count 0 2006.253.08:19:32.73#ibcon#read 3, iclass 4, count 0 2006.253.08:19:32.73#ibcon#about to read 4, iclass 4, count 0 2006.253.08:19:32.73#ibcon#read 4, iclass 4, count 0 2006.253.08:19:32.73#ibcon#about to read 5, iclass 4, count 0 2006.253.08:19:32.74#ibcon#read 5, iclass 4, count 0 2006.253.08:19:32.74#ibcon#about to read 6, iclass 4, count 0 2006.253.08:19:32.74#ibcon#read 6, iclass 4, count 0 2006.253.08:19:32.74#ibcon#end of sib2, iclass 4, count 0 2006.253.08:19:32.74#ibcon#*mode == 0, iclass 4, count 0 2006.253.08:19:32.74#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.253.08:19:32.74#ibcon#[27=BW32\r\n] 2006.253.08:19:32.74#ibcon#*before write, iclass 4, count 0 2006.253.08:19:32.74#ibcon#enter sib2, iclass 4, count 0 2006.253.08:19:32.74#ibcon#flushed, iclass 4, count 0 2006.253.08:19:32.74#ibcon#about to write, iclass 4, count 0 2006.253.08:19:32.74#ibcon#wrote, iclass 4, count 0 2006.253.08:19:32.74#ibcon#about to read 3, iclass 4, count 0 2006.253.08:19:32.76#ibcon#read 3, iclass 4, count 0 2006.253.08:19:32.76#ibcon#about to read 4, iclass 4, count 0 2006.253.08:19:32.77#ibcon#read 4, iclass 4, count 0 2006.253.08:19:32.77#ibcon#about to read 5, iclass 4, count 0 2006.253.08:19:32.77#ibcon#read 5, iclass 4, count 0 2006.253.08:19:32.77#ibcon#about to read 6, iclass 4, count 0 2006.253.08:19:32.77#ibcon#read 6, iclass 4, count 0 2006.253.08:19:32.77#ibcon#end of sib2, iclass 4, count 0 2006.253.08:19:32.77#ibcon#*after write, iclass 4, count 0 2006.253.08:19:32.77#ibcon#*before return 0, iclass 4, count 0 2006.253.08:19:32.77#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.253.08:19:32.77#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.253.08:19:32.77#ibcon#about to clear, iclass 4 cls_cnt 0 2006.253.08:19:32.77#ibcon#cleared, iclass 4 cls_cnt 0 2006.253.08:19:32.77$4f8m12a/ifd4f 2006.253.08:19:32.77$ifd4f/lo= 2006.253.08:19:32.77$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.253.08:19:32.77$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.253.08:19:32.77$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.253.08:19:32.77$ifd4f/patch= 2006.253.08:19:32.77$ifd4f/patch=lo1,a1,a2,a3,a4 2006.253.08:19:32.77$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.253.08:19:32.77$ifd4f/patch=lo3,a5,a6,a7,a8 2006.253.08:19:32.77$4f8m12a/"form=m,16.000,1:2 2006.253.08:19:32.77$4f8m12a/"tpicd 2006.253.08:19:32.77$4f8m12a/echo=off 2006.253.08:19:32.77$4f8m12a/xlog=off 2006.253.08:19:32.77:!2006.253.08:21:00 2006.253.08:19:52.13#trakl#Source acquired 2006.253.08:19:54.14#flagr#flagr/antenna,acquired 2006.253.08:21:00.02:preob 2006.253.08:21:01.14/onsource/TRACKING 2006.253.08:21:01.14:!2006.253.08:21:10 2006.253.08:21:10.02:data_valid=on 2006.253.08:21:10.02:midob 2006.253.08:21:11.14/onsource/TRACKING 2006.253.08:21:11.14/wx/30.79,1006.7,75 2006.253.08:21:11.27/cable/+6.3678E-03 2006.253.08:21:12.36/va/01,08,usb,yes,32,33 2006.253.08:21:12.36/va/02,07,usb,yes,31,33 2006.253.08:21:12.36/va/03,06,usb,yes,33,34 2006.253.08:21:12.36/va/04,07,usb,yes,32,35 2006.253.08:21:12.36/va/05,07,usb,yes,34,36 2006.253.08:21:12.36/va/06,07,usb,yes,29,29 2006.253.08:21:12.36/va/07,07,usb,yes,29,28 2006.253.08:21:12.36/va/08,07,usb,yes,31,31 2006.253.08:21:12.59/valo/01,532.99,yes,locked 2006.253.08:21:12.59/valo/02,572.99,yes,locked 2006.253.08:21:12.59/valo/03,672.99,yes,locked 2006.253.08:21:12.59/valo/04,832.99,yes,locked 2006.253.08:21:12.59/valo/05,652.99,yes,locked 2006.253.08:21:12.59/valo/06,772.99,yes,locked 2006.253.08:21:12.59/valo/07,832.99,yes,locked 2006.253.08:21:12.59/valo/08,852.99,yes,locked 2006.253.08:21:13.68/vb/01,04,usb,yes,30,29 2006.253.08:21:13.68/vb/02,05,usb,yes,29,30 2006.253.08:21:13.68/vb/03,04,usb,yes,29,33 2006.253.08:21:13.68/vb/04,04,usb,yes,29,30 2006.253.08:21:13.68/vb/05,04,usb,yes,28,32 2006.253.08:21:13.68/vb/06,04,usb,yes,29,32 2006.253.08:21:13.68/vb/07,04,usb,yes,31,31 2006.253.08:21:13.68/vb/08,04,usb,yes,28,32 2006.253.08:21:13.91/vblo/01,632.99,yes,locked 2006.253.08:21:13.91/vblo/02,640.99,yes,locked 2006.253.08:21:13.91/vblo/03,656.99,yes,locked 2006.253.08:21:13.91/vblo/04,712.99,yes,locked 2006.253.08:21:13.91/vblo/05,744.99,yes,locked 2006.253.08:21:13.91/vblo/06,752.99,yes,locked 2006.253.08:21:13.91/vblo/07,734.99,yes,locked 2006.253.08:21:13.91/vblo/08,744.99,yes,locked 2006.253.08:21:14.06/vabw/8 2006.253.08:21:14.21/vbbw/8 2006.253.08:21:14.30/xfe/off,on,14.2 2006.253.08:21:14.68/ifatt/23,28,28,28 2006.253.08:21:15.07/fmout-gps/S +4.70E-07 2006.253.08:21:15.12:!2006.253.08:22:10 2006.253.08:22:10.01:data_valid=off 2006.253.08:22:10.02:postob 2006.253.08:22:10.15/cable/+6.3660E-03 2006.253.08:22:10.16/wx/30.78,1006.7,75 2006.253.08:22:11.07/fmout-gps/S +4.70E-07 2006.253.08:22:11.08:scan_name=253-0824,k06253,60 2006.253.08:22:11.08:source=1611+343,161341.06,341247.9,2000.0,ccw 2006.253.08:22:12.12#flagr#flagr/antenna,new-source 2006.253.08:22:12.13:checkk5 2006.253.08:22:12.51/chk_autoobs//k5ts1/ autoobs is running! 2006.253.08:22:12.89/chk_autoobs//k5ts2/ autoobs is running! 2006.253.08:22:13.29/chk_autoobs//k5ts3/ autoobs is running! 2006.253.08:22:13.66/chk_autoobs//k5ts4/ autoobs is running! 2006.253.08:22:14.02/chk_obsdata//k5ts1/T2530821??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.08:22:14.39/chk_obsdata//k5ts2/T2530821??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.08:22:14.75/chk_obsdata//k5ts3/T2530821??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.08:22:15.12/chk_obsdata//k5ts4/T2530821??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.253.08:22:15.82/k5log//k5ts1_log_newline 2006.253.08:22:16.51/k5log//k5ts2_log_newline 2006.253.08:22:17.19/k5log//k5ts3_log_newline 2006.253.08:22:17.89/k5log//k5ts4_log_newline 2006.253.08:22:17.91/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.253.08:22:17.91:4f8m12a=3 2006.253.08:22:17.91$4f8m12a/echo=on 2006.253.08:22:17.91$4f8m12a/pcalon 2006.253.08:22:17.91$pcalon/"no phase cal control is implemented here 2006.253.08:22:17.91$4f8m12a/"tpicd=stop 2006.253.08:22:17.92$4f8m12a/vc4f8 2006.253.08:22:17.92$vc4f8/valo=1,532.99 2006.253.08:22:17.92#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.253.08:22:17.92#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.253.08:22:17.92#ibcon#ireg 17 cls_cnt 0 2006.253.08:22:17.92#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.253.08:22:17.92#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.253.08:22:17.92#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.253.08:22:17.92#ibcon#enter wrdev, iclass 37, count 0 2006.253.08:22:17.92#ibcon#first serial, iclass 37, count 0 2006.253.08:22:17.92#ibcon#enter sib2, iclass 37, count 0 2006.253.08:22:17.92#ibcon#flushed, iclass 37, count 0 2006.253.08:22:17.92#ibcon#about to write, iclass 37, count 0 2006.253.08:22:17.92#ibcon#wrote, iclass 37, count 0 2006.253.08:22:17.92#ibcon#about to read 3, iclass 37, count 0 2006.253.08:22:17.96#ibcon#read 3, iclass 37, count 0 2006.253.08:22:17.96#ibcon#about to read 4, iclass 37, count 0 2006.253.08:22:17.96#ibcon#read 4, iclass 37, count 0 2006.253.08:22:17.96#ibcon#about to read 5, iclass 37, count 0 2006.253.08:22:17.96#ibcon#read 5, iclass 37, count 0 2006.253.08:22:17.96#ibcon#about to read 6, iclass 37, count 0 2006.253.08:22:17.96#ibcon#read 6, iclass 37, count 0 2006.253.08:22:17.96#ibcon#end of sib2, iclass 37, count 0 2006.253.08:22:17.96#ibcon#*mode == 0, iclass 37, count 0 2006.253.08:22:17.96#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.253.08:22:17.96#ibcon#[26=FRQ=01,532.99\r\n] 2006.253.08:22:17.96#ibcon#*before write, iclass 37, count 0 2006.253.08:22:17.96#ibcon#enter sib2, iclass 37, count 0 2006.253.08:22:17.96#ibcon#flushed, iclass 37, count 0 2006.253.08:22:17.96#ibcon#about to write, iclass 37, count 0 2006.253.08:22:17.96#ibcon#wrote, iclass 37, count 0 2006.253.08:22:17.96#ibcon#about to read 3, iclass 37, count 0 2006.253.08:22:18.00#ibcon#read 3, iclass 37, count 0 2006.253.08:22:18.00#ibcon#about to read 4, iclass 37, count 0 2006.253.08:22:18.00#ibcon#read 4, iclass 37, count 0 2006.253.08:22:18.00#ibcon#about to read 5, iclass 37, count 0 2006.253.08:22:18.00#ibcon#read 5, iclass 37, count 0 2006.253.08:22:18.00#ibcon#about to read 6, iclass 37, count 0 2006.253.08:22:18.00#ibcon#read 6, iclass 37, count 0 2006.253.08:22:18.00#ibcon#end of sib2, iclass 37, count 0 2006.253.08:22:18.00#ibcon#*after write, iclass 37, count 0 2006.253.08:22:18.00#ibcon#*before return 0, iclass 37, count 0 2006.253.08:22:18.00#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.253.08:22:18.00#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.253.08:22:18.00#ibcon#about to clear, iclass 37 cls_cnt 0 2006.253.08:22:18.00#ibcon#cleared, iclass 37 cls_cnt 0 2006.253.08:22:18.01$vc4f8/va=1,8 2006.253.08:22:18.01#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.253.08:22:18.01#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.253.08:22:18.01#ibcon#ireg 11 cls_cnt 2 2006.253.08:22:18.01#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.253.08:22:18.01#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.253.08:22:18.01#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.253.08:22:18.01#ibcon#enter wrdev, iclass 39, count 2 2006.253.08:22:18.01#ibcon#first serial, iclass 39, count 2 2006.253.08:22:18.01#ibcon#enter sib2, iclass 39, count 2 2006.253.08:22:18.01#ibcon#flushed, iclass 39, count 2 2006.253.08:22:18.01#ibcon#about to write, iclass 39, count 2 2006.253.08:22:18.01#ibcon#wrote, iclass 39, count 2 2006.253.08:22:18.01#ibcon#about to read 3, iclass 39, count 2 2006.253.08:22:18.02#ibcon#read 3, iclass 39, count 2 2006.253.08:22:18.02#ibcon#about to read 4, iclass 39, count 2 2006.253.08:22:18.02#ibcon#read 4, iclass 39, count 2 2006.253.08:22:18.02#ibcon#about to read 5, iclass 39, count 2 2006.253.08:22:18.02#ibcon#read 5, iclass 39, count 2 2006.253.08:22:18.02#ibcon#about to read 6, iclass 39, count 2 2006.253.08:22:18.02#ibcon#read 6, iclass 39, count 2 2006.253.08:22:18.02#ibcon#end of sib2, iclass 39, count 2 2006.253.08:22:18.02#ibcon#*mode == 0, iclass 39, count 2 2006.253.08:22:18.02#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.253.08:22:18.02#ibcon#[25=AT01-08\r\n] 2006.253.08:22:18.02#ibcon#*before write, iclass 39, count 2 2006.253.08:22:18.02#ibcon#enter sib2, iclass 39, count 2 2006.253.08:22:18.02#ibcon#flushed, iclass 39, count 2 2006.253.08:22:18.02#ibcon#about to write, iclass 39, count 2 2006.253.08:22:18.02#ibcon#wrote, iclass 39, count 2 2006.253.08:22:18.02#ibcon#about to read 3, iclass 39, count 2 2006.253.08:22:18.05#ibcon#read 3, iclass 39, count 2 2006.253.08:22:18.05#ibcon#about to read 4, iclass 39, count 2 2006.253.08:22:18.05#ibcon#read 4, iclass 39, count 2 2006.253.08:22:18.05#ibcon#about to read 5, iclass 39, count 2 2006.253.08:22:18.05#ibcon#read 5, iclass 39, count 2 2006.253.08:22:18.05#ibcon#about to read 6, iclass 39, count 2 2006.253.08:22:18.05#ibcon#read 6, iclass 39, count 2 2006.253.08:22:18.05#ibcon#end of sib2, iclass 39, count 2 2006.253.08:22:18.05#ibcon#*after write, iclass 39, count 2 2006.253.08:22:18.05#ibcon#*before return 0, iclass 39, count 2 2006.253.08:22:18.05#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.253.08:22:18.05#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.253.08:22:18.05#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.253.08:22:18.05#ibcon#ireg 7 cls_cnt 0 2006.253.08:22:18.05#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.253.08:22:18.18#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.253.08:22:18.18#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.253.08:22:18.18#ibcon#enter wrdev, iclass 39, count 0 2006.253.08:22:18.18#ibcon#first serial, iclass 39, count 0 2006.253.08:22:18.18#ibcon#enter sib2, iclass 39, count 0 2006.253.08:22:18.18#ibcon#flushed, iclass 39, count 0 2006.253.08:22:18.18#ibcon#about to write, iclass 39, count 0 2006.253.08:22:18.18#ibcon#wrote, iclass 39, count 0 2006.253.08:22:18.18#ibcon#about to read 3, iclass 39, count 0 2006.253.08:22:18.19#ibcon#read 3, iclass 39, count 0 2006.253.08:22:18.19#ibcon#about to read 4, iclass 39, count 0 2006.253.08:22:18.19#ibcon#read 4, iclass 39, count 0 2006.253.08:22:18.19#ibcon#about to read 5, iclass 39, count 0 2006.253.08:22:18.19#ibcon#read 5, iclass 39, count 0 2006.253.08:22:18.19#ibcon#about to read 6, iclass 39, count 0 2006.253.08:22:18.19#ibcon#read 6, iclass 39, count 0 2006.253.08:22:18.19#ibcon#end of sib2, iclass 39, count 0 2006.253.08:22:18.19#ibcon#*mode == 0, iclass 39, count 0 2006.253.08:22:18.19#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.253.08:22:18.19#ibcon#[25=USB\r\n] 2006.253.08:22:18.19#ibcon#*before write, iclass 39, count 0 2006.253.08:22:18.19#ibcon#enter sib2, iclass 39, count 0 2006.253.08:22:18.19#ibcon#flushed, iclass 39, count 0 2006.253.08:22:18.19#ibcon#about to write, iclass 39, count 0 2006.253.08:22:18.19#ibcon#wrote, iclass 39, count 0 2006.253.08:22:18.19#ibcon#about to read 3, iclass 39, count 0 2006.253.08:22:18.22#ibcon#read 3, iclass 39, count 0 2006.253.08:22:18.22#ibcon#about to read 4, iclass 39, count 0 2006.253.08:22:18.22#ibcon#read 4, iclass 39, count 0 2006.253.08:22:18.22#ibcon#about to read 5, iclass 39, count 0 2006.253.08:22:18.22#ibcon#read 5, iclass 39, count 0 2006.253.08:22:18.22#ibcon#about to read 6, iclass 39, count 0 2006.253.08:22:18.22#ibcon#read 6, iclass 39, count 0 2006.253.08:22:18.22#ibcon#end of sib2, iclass 39, count 0 2006.253.08:22:18.22#ibcon#*after write, iclass 39, count 0 2006.253.08:22:18.22#ibcon#*before return 0, iclass 39, count 0 2006.253.08:22:18.22#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.253.08:22:18.22#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.253.08:22:18.22#ibcon#about to clear, iclass 39 cls_cnt 0 2006.253.08:22:18.22#ibcon#cleared, iclass 39 cls_cnt 0 2006.253.08:22:18.22$vc4f8/valo=2,572.99 2006.253.08:22:18.23#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.253.08:22:18.23#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.253.08:22:18.23#ibcon#ireg 17 cls_cnt 0 2006.253.08:22:18.23#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.253.08:22:18.23#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.253.08:22:18.23#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.253.08:22:18.23#ibcon#enter wrdev, iclass 3, count 0 2006.253.08:22:18.23#ibcon#first serial, iclass 3, count 0 2006.253.08:22:18.23#ibcon#enter sib2, iclass 3, count 0 2006.253.08:22:18.23#ibcon#flushed, iclass 3, count 0 2006.253.08:22:18.23#ibcon#about to write, iclass 3, count 0 2006.253.08:22:18.23#ibcon#wrote, iclass 3, count 0 2006.253.08:22:18.23#ibcon#about to read 3, iclass 3, count 0 2006.253.08:22:18.25#ibcon#read 3, iclass 3, count 0 2006.253.08:22:18.25#ibcon#about to read 4, iclass 3, count 0 2006.253.08:22:18.25#ibcon#read 4, iclass 3, count 0 2006.253.08:22:18.25#ibcon#about to read 5, iclass 3, count 0 2006.253.08:22:18.25#ibcon#read 5, iclass 3, count 0 2006.253.08:22:18.25#ibcon#about to read 6, iclass 3, count 0 2006.253.08:22:18.25#ibcon#read 6, iclass 3, count 0 2006.253.08:22:18.25#ibcon#end of sib2, iclass 3, count 0 2006.253.08:22:18.25#ibcon#*mode == 0, iclass 3, count 0 2006.253.08:22:18.25#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.253.08:22:18.25#ibcon#[26=FRQ=02,572.99\r\n] 2006.253.08:22:18.25#ibcon#*before write, iclass 3, count 0 2006.253.08:22:18.25#ibcon#enter sib2, iclass 3, count 0 2006.253.08:22:18.25#ibcon#flushed, iclass 3, count 0 2006.253.08:22:18.25#ibcon#about to write, iclass 3, count 0 2006.253.08:22:18.25#ibcon#wrote, iclass 3, count 0 2006.253.08:22:18.25#ibcon#about to read 3, iclass 3, count 0 2006.253.08:22:18.29#ibcon#read 3, iclass 3, count 0 2006.253.08:22:18.29#ibcon#about to read 4, iclass 3, count 0 2006.253.08:22:18.29#ibcon#read 4, iclass 3, count 0 2006.253.08:22:18.29#ibcon#about to read 5, iclass 3, count 0 2006.253.08:22:18.29#ibcon#read 5, iclass 3, count 0 2006.253.08:22:18.29#ibcon#about to read 6, iclass 3, count 0 2006.253.08:22:18.29#ibcon#read 6, iclass 3, count 0 2006.253.08:22:18.29#ibcon#end of sib2, iclass 3, count 0 2006.253.08:22:18.29#ibcon#*after write, iclass 3, count 0 2006.253.08:22:18.29#ibcon#*before return 0, iclass 3, count 0 2006.253.08:22:18.29#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.253.08:22:18.29#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.253.08:22:18.29#ibcon#about to clear, iclass 3 cls_cnt 0 2006.253.08:22:18.29#ibcon#cleared, iclass 3 cls_cnt 0 2006.253.08:22:18.30$vc4f8/va=2,7 2006.253.08:22:18.30#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.253.08:22:18.30#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.253.08:22:18.30#ibcon#ireg 11 cls_cnt 2 2006.253.08:22:18.30#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.253.08:22:18.33#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.253.08:22:18.33#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.253.08:22:18.33#ibcon#enter wrdev, iclass 5, count 2 2006.253.08:22:18.33#ibcon#first serial, iclass 5, count 2 2006.253.08:22:18.33#ibcon#enter sib2, iclass 5, count 2 2006.253.08:22:18.33#ibcon#flushed, iclass 5, count 2 2006.253.08:22:18.33#ibcon#about to write, iclass 5, count 2 2006.253.08:22:18.33#ibcon#wrote, iclass 5, count 2 2006.253.08:22:18.33#ibcon#about to read 3, iclass 5, count 2 2006.253.08:22:18.36#ibcon#read 3, iclass 5, count 2 2006.253.08:22:18.36#ibcon#about to read 4, iclass 5, count 2 2006.253.08:22:18.36#ibcon#read 4, iclass 5, count 2 2006.253.08:22:18.36#ibcon#about to read 5, iclass 5, count 2 2006.253.08:22:18.36#ibcon#read 5, iclass 5, count 2 2006.253.08:22:18.36#ibcon#about to read 6, iclass 5, count 2 2006.253.08:22:18.36#ibcon#read 6, iclass 5, count 2 2006.253.08:22:18.36#ibcon#end of sib2, iclass 5, count 2 2006.253.08:22:18.36#ibcon#*mode == 0, iclass 5, count 2 2006.253.08:22:18.36#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.253.08:22:18.36#ibcon#[25=AT02-07\r\n] 2006.253.08:22:18.36#ibcon#*before write, iclass 5, count 2 2006.253.08:22:18.36#ibcon#enter sib2, iclass 5, count 2 2006.253.08:22:18.36#ibcon#flushed, iclass 5, count 2 2006.253.08:22:18.36#ibcon#about to write, iclass 5, count 2 2006.253.08:22:18.36#ibcon#wrote, iclass 5, count 2 2006.253.08:22:18.36#ibcon#about to read 3, iclass 5, count 2 2006.253.08:22:18.39#ibcon#read 3, iclass 5, count 2 2006.253.08:22:18.39#ibcon#about to read 4, iclass 5, count 2 2006.253.08:22:18.39#ibcon#read 4, iclass 5, count 2 2006.253.08:22:18.39#ibcon#about to read 5, iclass 5, count 2 2006.253.08:22:18.39#ibcon#read 5, iclass 5, count 2 2006.253.08:22:18.39#ibcon#about to read 6, iclass 5, count 2 2006.253.08:22:18.39#ibcon#read 6, iclass 5, count 2 2006.253.08:22:18.39#ibcon#end of sib2, iclass 5, count 2 2006.253.08:22:18.39#ibcon#*after write, iclass 5, count 2 2006.253.08:22:18.39#ibcon#*before return 0, iclass 5, count 2 2006.253.08:22:18.39#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.253.08:22:18.39#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.253.08:22:18.39#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.253.08:22:18.39#ibcon#ireg 7 cls_cnt 0 2006.253.08:22:18.39#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.253.08:22:18.51#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.253.08:22:18.51#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.253.08:22:18.51#ibcon#enter wrdev, iclass 5, count 0 2006.253.08:22:18.51#ibcon#first serial, iclass 5, count 0 2006.253.08:22:18.51#ibcon#enter sib2, iclass 5, count 0 2006.253.08:22:18.51#ibcon#flushed, iclass 5, count 0 2006.253.08:22:18.51#ibcon#about to write, iclass 5, count 0 2006.253.08:22:18.51#ibcon#wrote, iclass 5, count 0 2006.253.08:22:18.51#ibcon#about to read 3, iclass 5, count 0 2006.253.08:22:18.53#ibcon#read 3, iclass 5, count 0 2006.253.08:22:18.53#ibcon#about to read 4, iclass 5, count 0 2006.253.08:22:18.53#ibcon#read 4, iclass 5, count 0 2006.253.08:22:18.53#ibcon#about to read 5, iclass 5, count 0 2006.253.08:22:18.53#ibcon#read 5, iclass 5, count 0 2006.253.08:22:18.53#ibcon#about to read 6, iclass 5, count 0 2006.253.08:22:18.53#ibcon#read 6, iclass 5, count 0 2006.253.08:22:18.53#ibcon#end of sib2, iclass 5, count 0 2006.253.08:22:18.53#ibcon#*mode == 0, iclass 5, count 0 2006.253.08:22:18.53#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.253.08:22:18.53#ibcon#[25=USB\r\n] 2006.253.08:22:18.53#ibcon#*before write, iclass 5, count 0 2006.253.08:22:18.53#ibcon#enter sib2, iclass 5, count 0 2006.253.08:22:18.53#ibcon#flushed, iclass 5, count 0 2006.253.08:22:18.53#ibcon#about to write, iclass 5, count 0 2006.253.08:22:18.53#ibcon#wrote, iclass 5, count 0 2006.253.08:22:18.53#ibcon#about to read 3, iclass 5, count 0 2006.253.08:22:18.56#ibcon#read 3, iclass 5, count 0 2006.253.08:22:18.56#ibcon#about to read 4, iclass 5, count 0 2006.253.08:22:18.56#ibcon#read 4, iclass 5, count 0 2006.253.08:22:18.56#ibcon#about to read 5, iclass 5, count 0 2006.253.08:22:18.56#ibcon#read 5, iclass 5, count 0 2006.253.08:22:18.56#ibcon#about to read 6, iclass 5, count 0 2006.253.08:22:18.56#ibcon#read 6, iclass 5, count 0 2006.253.08:22:18.56#ibcon#end of sib2, iclass 5, count 0 2006.253.08:22:18.56#ibcon#*after write, iclass 5, count 0 2006.253.08:22:18.56#ibcon#*before return 0, iclass 5, count 0 2006.253.08:22:18.56#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.253.08:22:18.56#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.253.08:22:18.56#ibcon#about to clear, iclass 5 cls_cnt 0 2006.253.08:22:18.56#ibcon#cleared, iclass 5 cls_cnt 0 2006.253.08:22:18.57$vc4f8/valo=3,672.99 2006.253.08:22:18.57#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.253.08:22:18.57#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.253.08:22:18.57#ibcon#ireg 17 cls_cnt 0 2006.253.08:22:18.57#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.253.08:22:18.57#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.253.08:22:18.57#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.253.08:22:18.57#ibcon#enter wrdev, iclass 7, count 0 2006.253.08:22:18.57#ibcon#first serial, iclass 7, count 0 2006.253.08:22:18.57#ibcon#enter sib2, iclass 7, count 0 2006.253.08:22:18.57#ibcon#flushed, iclass 7, count 0 2006.253.08:22:18.57#ibcon#about to write, iclass 7, count 0 2006.253.08:22:18.57#ibcon#wrote, iclass 7, count 0 2006.253.08:22:18.57#ibcon#about to read 3, iclass 7, count 0 2006.253.08:22:18.58#ibcon#read 3, iclass 7, count 0 2006.253.08:22:18.58#ibcon#about to read 4, iclass 7, count 0 2006.253.08:22:18.58#ibcon#read 4, iclass 7, count 0 2006.253.08:22:18.58#ibcon#about to read 5, iclass 7, count 0 2006.253.08:22:18.58#ibcon#read 5, iclass 7, count 0 2006.253.08:22:18.58#ibcon#about to read 6, iclass 7, count 0 2006.253.08:22:18.58#ibcon#read 6, iclass 7, count 0 2006.253.08:22:18.58#ibcon#end of sib2, iclass 7, count 0 2006.253.08:22:18.58#ibcon#*mode == 0, iclass 7, count 0 2006.253.08:22:18.58#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.253.08:22:18.58#ibcon#[26=FRQ=03,672.99\r\n] 2006.253.08:22:18.58#ibcon#*before write, iclass 7, count 0 2006.253.08:22:18.58#ibcon#enter sib2, iclass 7, count 0 2006.253.08:22:18.58#ibcon#flushed, iclass 7, count 0 2006.253.08:22:18.58#ibcon#about to write, iclass 7, count 0 2006.253.08:22:18.58#ibcon#wrote, iclass 7, count 0 2006.253.08:22:18.58#ibcon#about to read 3, iclass 7, count 0 2006.253.08:22:18.62#ibcon#read 3, iclass 7, count 0 2006.253.08:22:18.62#ibcon#about to read 4, iclass 7, count 0 2006.253.08:22:18.62#ibcon#read 4, iclass 7, count 0 2006.253.08:22:18.62#ibcon#about to read 5, iclass 7, count 0 2006.253.08:22:18.62#ibcon#read 5, iclass 7, count 0 2006.253.08:22:18.62#ibcon#about to read 6, iclass 7, count 0 2006.253.08:22:18.62#ibcon#read 6, iclass 7, count 0 2006.253.08:22:18.62#ibcon#end of sib2, iclass 7, count 0 2006.253.08:22:18.62#ibcon#*after write, iclass 7, count 0 2006.253.08:22:18.62#ibcon#*before return 0, iclass 7, count 0 2006.253.08:22:18.62#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.253.08:22:18.62#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.253.08:22:18.62#ibcon#about to clear, iclass 7 cls_cnt 0 2006.253.08:22:18.62#ibcon#cleared, iclass 7 cls_cnt 0 2006.253.08:22:18.63$vc4f8/va=3,6 2006.253.08:22:18.63#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.253.08:22:18.63#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.253.08:22:18.63#ibcon#ireg 11 cls_cnt 2 2006.253.08:22:18.63#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.253.08:22:18.68#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.253.08:22:18.68#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.253.08:22:18.68#ibcon#enter wrdev, iclass 11, count 2 2006.253.08:22:18.68#ibcon#first serial, iclass 11, count 2 2006.253.08:22:18.68#ibcon#enter sib2, iclass 11, count 2 2006.253.08:22:18.68#ibcon#flushed, iclass 11, count 2 2006.253.08:22:18.68#ibcon#about to write, iclass 11, count 2 2006.253.08:22:18.68#ibcon#wrote, iclass 11, count 2 2006.253.08:22:18.68#ibcon#about to read 3, iclass 11, count 2 2006.253.08:22:18.69#ibcon#read 3, iclass 11, count 2 2006.253.08:22:18.69#ibcon#about to read 4, iclass 11, count 2 2006.253.08:22:18.69#ibcon#read 4, iclass 11, count 2 2006.253.08:22:18.69#ibcon#about to read 5, iclass 11, count 2 2006.253.08:22:18.69#ibcon#read 5, iclass 11, count 2 2006.253.08:22:18.69#ibcon#about to read 6, iclass 11, count 2 2006.253.08:22:18.69#ibcon#read 6, iclass 11, count 2 2006.253.08:22:18.69#ibcon#end of sib2, iclass 11, count 2 2006.253.08:22:18.69#ibcon#*mode == 0, iclass 11, count 2 2006.253.08:22:18.69#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.253.08:22:18.69#ibcon#[25=AT03-06\r\n] 2006.253.08:22:18.69#ibcon#*before write, iclass 11, count 2 2006.253.08:22:18.69#ibcon#enter sib2, iclass 11, count 2 2006.253.08:22:18.69#ibcon#flushed, iclass 11, count 2 2006.253.08:22:18.69#ibcon#about to write, iclass 11, count 2 2006.253.08:22:18.69#ibcon#wrote, iclass 11, count 2 2006.253.08:22:18.69#ibcon#about to read 3, iclass 11, count 2 2006.253.08:22:18.72#ibcon#read 3, iclass 11, count 2 2006.253.08:22:18.72#ibcon#about to read 4, iclass 11, count 2 2006.253.08:22:18.72#ibcon#read 4, iclass 11, count 2 2006.253.08:22:18.72#ibcon#about to read 5, iclass 11, count 2 2006.253.08:22:18.72#ibcon#read 5, iclass 11, count 2 2006.253.08:22:18.72#ibcon#about to read 6, iclass 11, count 2 2006.253.08:22:18.72#ibcon#read 6, iclass 11, count 2 2006.253.08:22:18.72#ibcon#end of sib2, iclass 11, count 2 2006.253.08:22:18.72#ibcon#*after write, iclass 11, count 2 2006.253.08:22:18.72#ibcon#*before return 0, iclass 11, count 2 2006.253.08:22:18.72#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.253.08:22:18.72#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.253.08:22:18.72#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.253.08:22:18.72#ibcon#ireg 7 cls_cnt 0 2006.253.08:22:18.72#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.253.08:22:18.84#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.253.08:22:18.84#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.253.08:22:18.84#ibcon#enter wrdev, iclass 11, count 0 2006.253.08:22:18.84#ibcon#first serial, iclass 11, count 0 2006.253.08:22:18.84#ibcon#enter sib2, iclass 11, count 0 2006.253.08:22:18.84#ibcon#flushed, iclass 11, count 0 2006.253.08:22:18.84#ibcon#about to write, iclass 11, count 0 2006.253.08:22:18.84#ibcon#wrote, iclass 11, count 0 2006.253.08:22:18.84#ibcon#about to read 3, iclass 11, count 0 2006.253.08:22:18.86#ibcon#read 3, iclass 11, count 0 2006.253.08:22:18.86#ibcon#about to read 4, iclass 11, count 0 2006.253.08:22:18.86#ibcon#read 4, iclass 11, count 0 2006.253.08:22:18.86#ibcon#about to read 5, iclass 11, count 0 2006.253.08:22:18.86#ibcon#read 5, iclass 11, count 0 2006.253.08:22:18.86#ibcon#about to read 6, iclass 11, count 0 2006.253.08:22:18.86#ibcon#read 6, iclass 11, count 0 2006.253.08:22:18.86#ibcon#end of sib2, iclass 11, count 0 2006.253.08:22:18.86#ibcon#*mode == 0, iclass 11, count 0 2006.253.08:22:18.86#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.253.08:22:18.86#ibcon#[25=USB\r\n] 2006.253.08:22:18.86#ibcon#*before write, iclass 11, count 0 2006.253.08:22:18.86#ibcon#enter sib2, iclass 11, count 0 2006.253.08:22:18.86#ibcon#flushed, iclass 11, count 0 2006.253.08:22:18.86#ibcon#about to write, iclass 11, count 0 2006.253.08:22:18.86#ibcon#wrote, iclass 11, count 0 2006.253.08:22:18.86#ibcon#about to read 3, iclass 11, count 0 2006.253.08:22:18.89#ibcon#read 3, iclass 11, count 0 2006.253.08:22:18.89#ibcon#about to read 4, iclass 11, count 0 2006.253.08:22:18.89#ibcon#read 4, iclass 11, count 0 2006.253.08:22:18.89#ibcon#about to read 5, iclass 11, count 0 2006.253.08:22:18.89#ibcon#read 5, iclass 11, count 0 2006.253.08:22:18.89#ibcon#about to read 6, iclass 11, count 0 2006.253.08:22:18.89#ibcon#read 6, iclass 11, count 0 2006.253.08:22:18.89#ibcon#end of sib2, iclass 11, count 0 2006.253.08:22:18.89#ibcon#*after write, iclass 11, count 0 2006.253.08:22:18.89#ibcon#*before return 0, iclass 11, count 0 2006.253.08:22:18.89#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.253.08:22:18.89#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.253.08:22:18.89#ibcon#about to clear, iclass 11 cls_cnt 0 2006.253.08:22:18.89#ibcon#cleared, iclass 11 cls_cnt 0 2006.253.08:22:18.90$vc4f8/valo=4,832.99 2006.253.08:22:18.90#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.253.08:22:18.90#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.253.08:22:18.90#ibcon#ireg 17 cls_cnt 0 2006.253.08:22:18.90#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.253.08:22:18.90#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.253.08:22:18.90#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.253.08:22:18.90#ibcon#enter wrdev, iclass 13, count 0 2006.253.08:22:18.90#ibcon#first serial, iclass 13, count 0 2006.253.08:22:18.90#ibcon#enter sib2, iclass 13, count 0 2006.253.08:22:18.90#ibcon#flushed, iclass 13, count 0 2006.253.08:22:18.90#ibcon#about to write, iclass 13, count 0 2006.253.08:22:18.90#ibcon#wrote, iclass 13, count 0 2006.253.08:22:18.90#ibcon#about to read 3, iclass 13, count 0 2006.253.08:22:18.91#ibcon#read 3, iclass 13, count 0 2006.253.08:22:18.91#ibcon#about to read 4, iclass 13, count 0 2006.253.08:22:18.91#ibcon#read 4, iclass 13, count 0 2006.253.08:22:18.91#ibcon#about to read 5, iclass 13, count 0 2006.253.08:22:18.91#ibcon#read 5, iclass 13, count 0 2006.253.08:22:18.91#ibcon#about to read 6, iclass 13, count 0 2006.253.08:22:18.91#ibcon#read 6, iclass 13, count 0 2006.253.08:22:18.91#ibcon#end of sib2, iclass 13, count 0 2006.253.08:22:18.91#ibcon#*mode == 0, iclass 13, count 0 2006.253.08:22:18.91#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.253.08:22:18.91#ibcon#[26=FRQ=04,832.99\r\n] 2006.253.08:22:18.91#ibcon#*before write, iclass 13, count 0 2006.253.08:22:18.91#ibcon#enter sib2, iclass 13, count 0 2006.253.08:22:18.91#ibcon#flushed, iclass 13, count 0 2006.253.08:22:18.91#ibcon#about to write, iclass 13, count 0 2006.253.08:22:18.91#ibcon#wrote, iclass 13, count 0 2006.253.08:22:18.91#ibcon#about to read 3, iclass 13, count 0 2006.253.08:22:18.95#ibcon#read 3, iclass 13, count 0 2006.253.08:22:18.95#ibcon#about to read 4, iclass 13, count 0 2006.253.08:22:18.95#ibcon#read 4, iclass 13, count 0 2006.253.08:22:18.95#ibcon#about to read 5, iclass 13, count 0 2006.253.08:22:18.95#ibcon#read 5, iclass 13, count 0 2006.253.08:22:18.95#ibcon#about to read 6, iclass 13, count 0 2006.253.08:22:18.95#ibcon#read 6, iclass 13, count 0 2006.253.08:22:18.95#ibcon#end of sib2, iclass 13, count 0 2006.253.08:22:18.95#ibcon#*after write, iclass 13, count 0 2006.253.08:22:18.95#ibcon#*before return 0, iclass 13, count 0 2006.253.08:22:18.95#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.253.08:22:18.95#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.253.08:22:18.95#ibcon#about to clear, iclass 13 cls_cnt 0 2006.253.08:22:18.95#ibcon#cleared, iclass 13 cls_cnt 0 2006.253.08:22:18.96$vc4f8/va=4,7 2006.253.08:22:18.96#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.253.08:22:18.96#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.253.08:22:18.96#ibcon#ireg 11 cls_cnt 2 2006.253.08:22:18.96#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.253.08:22:19.01#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.253.08:22:19.01#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.253.08:22:19.01#ibcon#enter wrdev, iclass 15, count 2 2006.253.08:22:19.01#ibcon#first serial, iclass 15, count 2 2006.253.08:22:19.01#ibcon#enter sib2, iclass 15, count 2 2006.253.08:22:19.01#ibcon#flushed, iclass 15, count 2 2006.253.08:22:19.01#ibcon#about to write, iclass 15, count 2 2006.253.08:22:19.01#ibcon#wrote, iclass 15, count 2 2006.253.08:22:19.01#ibcon#about to read 3, iclass 15, count 2 2006.253.08:22:19.02#ibcon#read 3, iclass 15, count 2 2006.253.08:22:19.02#ibcon#about to read 4, iclass 15, count 2 2006.253.08:22:19.02#ibcon#read 4, iclass 15, count 2 2006.253.08:22:19.02#ibcon#about to read 5, iclass 15, count 2 2006.253.08:22:19.02#ibcon#read 5, iclass 15, count 2 2006.253.08:22:19.02#ibcon#about to read 6, iclass 15, count 2 2006.253.08:22:19.02#ibcon#read 6, iclass 15, count 2 2006.253.08:22:19.02#ibcon#end of sib2, iclass 15, count 2 2006.253.08:22:19.02#ibcon#*mode == 0, iclass 15, count 2 2006.253.08:22:19.02#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.253.08:22:19.02#ibcon#[25=AT04-07\r\n] 2006.253.08:22:19.02#ibcon#*before write, iclass 15, count 2 2006.253.08:22:19.02#ibcon#enter sib2, iclass 15, count 2 2006.253.08:22:19.02#ibcon#flushed, iclass 15, count 2 2006.253.08:22:19.02#ibcon#about to write, iclass 15, count 2 2006.253.08:22:19.02#ibcon#wrote, iclass 15, count 2 2006.253.08:22:19.02#ibcon#about to read 3, iclass 15, count 2 2006.253.08:22:19.05#ibcon#read 3, iclass 15, count 2 2006.253.08:22:19.05#ibcon#about to read 4, iclass 15, count 2 2006.253.08:22:19.05#ibcon#read 4, iclass 15, count 2 2006.253.08:22:19.05#ibcon#about to read 5, iclass 15, count 2 2006.253.08:22:19.05#ibcon#read 5, iclass 15, count 2 2006.253.08:22:19.05#ibcon#about to read 6, iclass 15, count 2 2006.253.08:22:19.05#ibcon#read 6, iclass 15, count 2 2006.253.08:22:19.05#ibcon#end of sib2, iclass 15, count 2 2006.253.08:22:19.05#ibcon#*after write, iclass 15, count 2 2006.253.08:22:19.05#ibcon#*before return 0, iclass 15, count 2 2006.253.08:22:19.05#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.253.08:22:19.05#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.253.08:22:19.05#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.253.08:22:19.05#ibcon#ireg 7 cls_cnt 0 2006.253.08:22:19.05#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.253.08:22:19.17#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.253.08:22:19.17#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.253.08:22:19.17#ibcon#enter wrdev, iclass 15, count 0 2006.253.08:22:19.17#ibcon#first serial, iclass 15, count 0 2006.253.08:22:19.17#ibcon#enter sib2, iclass 15, count 0 2006.253.08:22:19.17#ibcon#flushed, iclass 15, count 0 2006.253.08:22:19.17#ibcon#about to write, iclass 15, count 0 2006.253.08:22:19.17#ibcon#wrote, iclass 15, count 0 2006.253.08:22:19.17#ibcon#about to read 3, iclass 15, count 0 2006.253.08:22:19.19#ibcon#read 3, iclass 15, count 0 2006.253.08:22:19.19#ibcon#about to read 4, iclass 15, count 0 2006.253.08:22:19.19#ibcon#read 4, iclass 15, count 0 2006.253.08:22:19.19#ibcon#about to read 5, iclass 15, count 0 2006.253.08:22:19.19#ibcon#read 5, iclass 15, count 0 2006.253.08:22:19.19#ibcon#about to read 6, iclass 15, count 0 2006.253.08:22:19.19#ibcon#read 6, iclass 15, count 0 2006.253.08:22:19.19#ibcon#end of sib2, iclass 15, count 0 2006.253.08:22:19.19#ibcon#*mode == 0, iclass 15, count 0 2006.253.08:22:19.19#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.253.08:22:19.19#ibcon#[25=USB\r\n] 2006.253.08:22:19.19#ibcon#*before write, iclass 15, count 0 2006.253.08:22:19.19#ibcon#enter sib2, iclass 15, count 0 2006.253.08:22:19.19#ibcon#flushed, iclass 15, count 0 2006.253.08:22:19.19#ibcon#about to write, iclass 15, count 0 2006.253.08:22:19.19#ibcon#wrote, iclass 15, count 0 2006.253.08:22:19.19#ibcon#about to read 3, iclass 15, count 0 2006.253.08:22:19.22#ibcon#read 3, iclass 15, count 0 2006.253.08:22:19.22#ibcon#about to read 4, iclass 15, count 0 2006.253.08:22:19.22#ibcon#read 4, iclass 15, count 0 2006.253.08:22:19.22#ibcon#about to read 5, iclass 15, count 0 2006.253.08:22:19.22#ibcon#read 5, iclass 15, count 0 2006.253.08:22:19.22#ibcon#about to read 6, iclass 15, count 0 2006.253.08:22:19.22#ibcon#read 6, iclass 15, count 0 2006.253.08:22:19.22#ibcon#end of sib2, iclass 15, count 0 2006.253.08:22:19.22#ibcon#*after write, iclass 15, count 0 2006.253.08:22:19.22#ibcon#*before return 0, iclass 15, count 0 2006.253.08:22:19.22#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.253.08:22:19.22#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.253.08:22:19.22#ibcon#about to clear, iclass 15 cls_cnt 0 2006.253.08:22:19.22#ibcon#cleared, iclass 15 cls_cnt 0 2006.253.08:22:19.22$vc4f8/valo=5,652.99 2006.253.08:22:19.22#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.253.08:22:19.22#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.253.08:22:19.22#ibcon#ireg 17 cls_cnt 0 2006.253.08:22:19.22#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.253.08:22:19.23#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.253.08:22:19.23#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.253.08:22:19.23#ibcon#enter wrdev, iclass 17, count 0 2006.253.08:22:19.23#ibcon#first serial, iclass 17, count 0 2006.253.08:22:19.23#ibcon#enter sib2, iclass 17, count 0 2006.253.08:22:19.23#ibcon#flushed, iclass 17, count 0 2006.253.08:22:19.23#ibcon#about to write, iclass 17, count 0 2006.253.08:22:19.23#ibcon#wrote, iclass 17, count 0 2006.253.08:22:19.23#ibcon#about to read 3, iclass 17, count 0 2006.253.08:22:19.24#ibcon#read 3, iclass 17, count 0 2006.253.08:22:19.24#ibcon#about to read 4, iclass 17, count 0 2006.253.08:22:19.24#ibcon#read 4, iclass 17, count 0 2006.253.08:22:19.24#ibcon#about to read 5, iclass 17, count 0 2006.253.08:22:19.24#ibcon#read 5, iclass 17, count 0 2006.253.08:22:19.24#ibcon#about to read 6, iclass 17, count 0 2006.253.08:22:19.24#ibcon#read 6, iclass 17, count 0 2006.253.08:22:19.24#ibcon#end of sib2, iclass 17, count 0 2006.253.08:22:19.24#ibcon#*mode == 0, iclass 17, count 0 2006.253.08:22:19.24#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.253.08:22:19.24#ibcon#[26=FRQ=05,652.99\r\n] 2006.253.08:22:19.24#ibcon#*before write, iclass 17, count 0 2006.253.08:22:19.24#ibcon#enter sib2, iclass 17, count 0 2006.253.08:22:19.24#ibcon#flushed, iclass 17, count 0 2006.253.08:22:19.24#ibcon#about to write, iclass 17, count 0 2006.253.08:22:19.24#ibcon#wrote, iclass 17, count 0 2006.253.08:22:19.24#ibcon#about to read 3, iclass 17, count 0 2006.253.08:22:19.28#ibcon#read 3, iclass 17, count 0 2006.253.08:22:19.28#ibcon#about to read 4, iclass 17, count 0 2006.253.08:22:19.28#ibcon#read 4, iclass 17, count 0 2006.253.08:22:19.28#ibcon#about to read 5, iclass 17, count 0 2006.253.08:22:19.28#ibcon#read 5, iclass 17, count 0 2006.253.08:22:19.28#ibcon#about to read 6, iclass 17, count 0 2006.253.08:22:19.28#ibcon#read 6, iclass 17, count 0 2006.253.08:22:19.28#ibcon#end of sib2, iclass 17, count 0 2006.253.08:22:19.28#ibcon#*after write, iclass 17, count 0 2006.253.08:22:19.28#ibcon#*before return 0, iclass 17, count 0 2006.253.08:22:19.28#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.253.08:22:19.28#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.253.08:22:19.28#ibcon#about to clear, iclass 17 cls_cnt 0 2006.253.08:22:19.28#ibcon#cleared, iclass 17 cls_cnt 0 2006.253.08:22:19.29$vc4f8/va=5,7 2006.253.08:22:19.29#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.253.08:22:19.29#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.253.08:22:19.29#ibcon#ireg 11 cls_cnt 2 2006.253.08:22:19.29#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.253.08:22:19.33#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.253.08:22:19.33#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.253.08:22:19.33#ibcon#enter wrdev, iclass 19, count 2 2006.253.08:22:19.33#ibcon#first serial, iclass 19, count 2 2006.253.08:22:19.33#ibcon#enter sib2, iclass 19, count 2 2006.253.08:22:19.33#ibcon#flushed, iclass 19, count 2 2006.253.08:22:19.33#ibcon#about to write, iclass 19, count 2 2006.253.08:22:19.33#ibcon#wrote, iclass 19, count 2 2006.253.08:22:19.33#ibcon#about to read 3, iclass 19, count 2 2006.253.08:22:19.35#ibcon#read 3, iclass 19, count 2 2006.253.08:22:19.35#ibcon#about to read 4, iclass 19, count 2 2006.253.08:22:19.35#ibcon#read 4, iclass 19, count 2 2006.253.08:22:19.35#ibcon#about to read 5, iclass 19, count 2 2006.253.08:22:19.35#ibcon#read 5, iclass 19, count 2 2006.253.08:22:19.35#ibcon#about to read 6, iclass 19, count 2 2006.253.08:22:19.35#ibcon#read 6, iclass 19, count 2 2006.253.08:22:19.35#ibcon#end of sib2, iclass 19, count 2 2006.253.08:22:19.35#ibcon#*mode == 0, iclass 19, count 2 2006.253.08:22:19.35#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.253.08:22:19.35#ibcon#[25=AT05-07\r\n] 2006.253.08:22:19.35#ibcon#*before write, iclass 19, count 2 2006.253.08:22:19.35#ibcon#enter sib2, iclass 19, count 2 2006.253.08:22:19.35#ibcon#flushed, iclass 19, count 2 2006.253.08:22:19.35#ibcon#about to write, iclass 19, count 2 2006.253.08:22:19.35#ibcon#wrote, iclass 19, count 2 2006.253.08:22:19.35#ibcon#about to read 3, iclass 19, count 2 2006.253.08:22:19.39#ibcon#read 3, iclass 19, count 2 2006.253.08:22:19.39#ibcon#about to read 4, iclass 19, count 2 2006.253.08:22:19.39#ibcon#read 4, iclass 19, count 2 2006.253.08:22:19.39#ibcon#about to read 5, iclass 19, count 2 2006.253.08:22:19.39#ibcon#read 5, iclass 19, count 2 2006.253.08:22:19.39#ibcon#about to read 6, iclass 19, count 2 2006.253.08:22:19.39#ibcon#read 6, iclass 19, count 2 2006.253.08:22:19.39#ibcon#end of sib2, iclass 19, count 2 2006.253.08:22:19.39#ibcon#*after write, iclass 19, count 2 2006.253.08:22:19.39#ibcon#*before return 0, iclass 19, count 2 2006.253.08:22:19.39#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.253.08:22:19.39#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.253.08:22:19.39#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.253.08:22:19.39#ibcon#ireg 7 cls_cnt 0 2006.253.08:22:19.39#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.253.08:22:19.50#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.253.08:22:19.50#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.253.08:22:19.50#ibcon#enter wrdev, iclass 19, count 0 2006.253.08:22:19.50#ibcon#first serial, iclass 19, count 0 2006.253.08:22:19.50#ibcon#enter sib2, iclass 19, count 0 2006.253.08:22:19.50#ibcon#flushed, iclass 19, count 0 2006.253.08:22:19.50#ibcon#about to write, iclass 19, count 0 2006.253.08:22:19.50#ibcon#wrote, iclass 19, count 0 2006.253.08:22:19.50#ibcon#about to read 3, iclass 19, count 0 2006.253.08:22:19.52#ibcon#read 3, iclass 19, count 0 2006.253.08:22:19.52#ibcon#about to read 4, iclass 19, count 0 2006.253.08:22:19.52#ibcon#read 4, iclass 19, count 0 2006.253.08:22:19.52#ibcon#about to read 5, iclass 19, count 0 2006.253.08:22:19.52#ibcon#read 5, iclass 19, count 0 2006.253.08:22:19.52#ibcon#about to read 6, iclass 19, count 0 2006.253.08:22:19.52#ibcon#read 6, iclass 19, count 0 2006.253.08:22:19.52#ibcon#end of sib2, iclass 19, count 0 2006.253.08:22:19.52#ibcon#*mode == 0, iclass 19, count 0 2006.253.08:22:19.52#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.253.08:22:19.52#ibcon#[25=USB\r\n] 2006.253.08:22:19.52#ibcon#*before write, iclass 19, count 0 2006.253.08:22:19.52#ibcon#enter sib2, iclass 19, count 0 2006.253.08:22:19.52#ibcon#flushed, iclass 19, count 0 2006.253.08:22:19.52#ibcon#about to write, iclass 19, count 0 2006.253.08:22:19.52#ibcon#wrote, iclass 19, count 0 2006.253.08:22:19.52#ibcon#about to read 3, iclass 19, count 0 2006.253.08:22:19.55#ibcon#read 3, iclass 19, count 0 2006.253.08:22:19.55#ibcon#about to read 4, iclass 19, count 0 2006.253.08:22:19.55#ibcon#read 4, iclass 19, count 0 2006.253.08:22:19.55#ibcon#about to read 5, iclass 19, count 0 2006.253.08:22:19.55#ibcon#read 5, iclass 19, count 0 2006.253.08:22:19.55#ibcon#about to read 6, iclass 19, count 0 2006.253.08:22:19.55#ibcon#read 6, iclass 19, count 0 2006.253.08:22:19.55#ibcon#end of sib2, iclass 19, count 0 2006.253.08:22:19.55#ibcon#*after write, iclass 19, count 0 2006.253.08:22:19.55#ibcon#*before return 0, iclass 19, count 0 2006.253.08:22:19.55#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.253.08:22:19.55#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.253.08:22:19.55#ibcon#about to clear, iclass 19 cls_cnt 0 2006.253.08:22:19.55#ibcon#cleared, iclass 19 cls_cnt 0 2006.253.08:22:19.55$vc4f8/valo=6,772.99 2006.253.08:22:19.55#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.253.08:22:19.55#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.253.08:22:19.55#ibcon#ireg 17 cls_cnt 0 2006.253.08:22:19.55#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.253.08:22:19.55#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.253.08:22:19.55#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.253.08:22:19.55#ibcon#enter wrdev, iclass 21, count 0 2006.253.08:22:19.55#ibcon#first serial, iclass 21, count 0 2006.253.08:22:19.55#ibcon#enter sib2, iclass 21, count 0 2006.253.08:22:19.56#ibcon#flushed, iclass 21, count 0 2006.253.08:22:19.56#ibcon#about to write, iclass 21, count 0 2006.253.08:22:19.56#ibcon#wrote, iclass 21, count 0 2006.253.08:22:19.56#ibcon#about to read 3, iclass 21, count 0 2006.253.08:22:19.58#ibcon#read 3, iclass 21, count 0 2006.253.08:22:19.58#ibcon#about to read 4, iclass 21, count 0 2006.253.08:22:19.58#ibcon#read 4, iclass 21, count 0 2006.253.08:22:19.58#ibcon#about to read 5, iclass 21, count 0 2006.253.08:22:19.58#ibcon#read 5, iclass 21, count 0 2006.253.08:22:19.58#ibcon#about to read 6, iclass 21, count 0 2006.253.08:22:19.58#ibcon#read 6, iclass 21, count 0 2006.253.08:22:19.58#ibcon#end of sib2, iclass 21, count 0 2006.253.08:22:19.58#ibcon#*mode == 0, iclass 21, count 0 2006.253.08:22:19.58#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.253.08:22:19.58#ibcon#[26=FRQ=06,772.99\r\n] 2006.253.08:22:19.58#ibcon#*before write, iclass 21, count 0 2006.253.08:22:19.58#ibcon#enter sib2, iclass 21, count 0 2006.253.08:22:19.58#ibcon#flushed, iclass 21, count 0 2006.253.08:22:19.58#ibcon#about to write, iclass 21, count 0 2006.253.08:22:19.58#ibcon#wrote, iclass 21, count 0 2006.253.08:22:19.58#ibcon#about to read 3, iclass 21, count 0 2006.253.08:22:19.62#ibcon#read 3, iclass 21, count 0 2006.253.08:22:19.62#ibcon#about to read 4, iclass 21, count 0 2006.253.08:22:19.62#ibcon#read 4, iclass 21, count 0 2006.253.08:22:19.62#ibcon#about to read 5, iclass 21, count 0 2006.253.08:22:19.62#ibcon#read 5, iclass 21, count 0 2006.253.08:22:19.62#ibcon#about to read 6, iclass 21, count 0 2006.253.08:22:19.62#ibcon#read 6, iclass 21, count 0 2006.253.08:22:19.62#ibcon#end of sib2, iclass 21, count 0 2006.253.08:22:19.62#ibcon#*after write, iclass 21, count 0 2006.253.08:22:19.62#ibcon#*before return 0, iclass 21, count 0 2006.253.08:22:19.62#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.253.08:22:19.62#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.253.08:22:19.62#ibcon#about to clear, iclass 21 cls_cnt 0 2006.253.08:22:19.62#ibcon#cleared, iclass 21 cls_cnt 0 2006.253.08:22:19.62$vc4f8/va=6,7 2006.253.08:22:19.62#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.253.08:22:19.62#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.253.08:22:19.62#ibcon#ireg 11 cls_cnt 2 2006.253.08:22:19.62#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.253.08:22:19.68#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.253.08:22:19.68#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.253.08:22:19.68#ibcon#enter wrdev, iclass 23, count 2 2006.253.08:22:19.68#ibcon#first serial, iclass 23, count 2 2006.253.08:22:19.68#ibcon#enter sib2, iclass 23, count 2 2006.253.08:22:19.68#ibcon#flushed, iclass 23, count 2 2006.253.08:22:19.68#ibcon#about to write, iclass 23, count 2 2006.253.08:22:19.68#ibcon#wrote, iclass 23, count 2 2006.253.08:22:19.68#ibcon#about to read 3, iclass 23, count 2 2006.253.08:22:19.69#ibcon#read 3, iclass 23, count 2 2006.253.08:22:19.69#ibcon#about to read 4, iclass 23, count 2 2006.253.08:22:19.69#ibcon#read 4, iclass 23, count 2 2006.253.08:22:19.69#ibcon#about to read 5, iclass 23, count 2 2006.253.08:22:19.69#ibcon#read 5, iclass 23, count 2 2006.253.08:22:19.69#ibcon#about to read 6, iclass 23, count 2 2006.253.08:22:19.69#ibcon#read 6, iclass 23, count 2 2006.253.08:22:19.69#ibcon#end of sib2, iclass 23, count 2 2006.253.08:22:19.69#ibcon#*mode == 0, iclass 23, count 2 2006.253.08:22:19.69#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.253.08:22:19.69#ibcon#[25=AT06-07\r\n] 2006.253.08:22:19.69#ibcon#*before write, iclass 23, count 2 2006.253.08:22:19.69#ibcon#enter sib2, iclass 23, count 2 2006.253.08:22:19.69#ibcon#flushed, iclass 23, count 2 2006.253.08:22:19.69#ibcon#about to write, iclass 23, count 2 2006.253.08:22:19.69#ibcon#wrote, iclass 23, count 2 2006.253.08:22:19.69#ibcon#about to read 3, iclass 23, count 2 2006.253.08:22:19.72#ibcon#read 3, iclass 23, count 2 2006.253.08:22:19.72#ibcon#about to read 4, iclass 23, count 2 2006.253.08:22:19.72#ibcon#read 4, iclass 23, count 2 2006.253.08:22:19.72#ibcon#about to read 5, iclass 23, count 2 2006.253.08:22:19.72#ibcon#read 5, iclass 23, count 2 2006.253.08:22:19.72#ibcon#about to read 6, iclass 23, count 2 2006.253.08:22:19.72#ibcon#read 6, iclass 23, count 2 2006.253.08:22:19.72#ibcon#end of sib2, iclass 23, count 2 2006.253.08:22:19.72#ibcon#*after write, iclass 23, count 2 2006.253.08:22:19.72#ibcon#*before return 0, iclass 23, count 2 2006.253.08:22:19.72#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.253.08:22:19.72#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.253.08:22:19.72#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.253.08:22:19.72#ibcon#ireg 7 cls_cnt 0 2006.253.08:22:19.72#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.253.08:22:19.84#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.253.08:22:19.84#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.253.08:22:19.84#ibcon#enter wrdev, iclass 23, count 0 2006.253.08:22:19.84#ibcon#first serial, iclass 23, count 0 2006.253.08:22:19.84#ibcon#enter sib2, iclass 23, count 0 2006.253.08:22:19.84#ibcon#flushed, iclass 23, count 0 2006.253.08:22:19.84#ibcon#about to write, iclass 23, count 0 2006.253.08:22:19.84#ibcon#wrote, iclass 23, count 0 2006.253.08:22:19.84#ibcon#about to read 3, iclass 23, count 0 2006.253.08:22:19.86#ibcon#read 3, iclass 23, count 0 2006.253.08:22:19.86#ibcon#about to read 4, iclass 23, count 0 2006.253.08:22:19.86#ibcon#read 4, iclass 23, count 0 2006.253.08:22:19.86#ibcon#about to read 5, iclass 23, count 0 2006.253.08:22:19.86#ibcon#read 5, iclass 23, count 0 2006.253.08:22:19.86#ibcon#about to read 6, iclass 23, count 0 2006.253.08:22:19.86#ibcon#read 6, iclass 23, count 0 2006.253.08:22:19.86#ibcon#end of sib2, iclass 23, count 0 2006.253.08:22:19.86#ibcon#*mode == 0, iclass 23, count 0 2006.253.08:22:19.86#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.253.08:22:19.86#ibcon#[25=USB\r\n] 2006.253.08:22:19.86#ibcon#*before write, iclass 23, count 0 2006.253.08:22:19.86#ibcon#enter sib2, iclass 23, count 0 2006.253.08:22:19.86#ibcon#flushed, iclass 23, count 0 2006.253.08:22:19.86#ibcon#about to write, iclass 23, count 0 2006.253.08:22:19.86#ibcon#wrote, iclass 23, count 0 2006.253.08:22:19.86#ibcon#about to read 3, iclass 23, count 0 2006.253.08:22:19.89#ibcon#read 3, iclass 23, count 0 2006.253.08:22:19.89#ibcon#about to read 4, iclass 23, count 0 2006.253.08:22:19.89#ibcon#read 4, iclass 23, count 0 2006.253.08:22:19.89#ibcon#about to read 5, iclass 23, count 0 2006.253.08:22:19.89#ibcon#read 5, iclass 23, count 0 2006.253.08:22:19.89#ibcon#about to read 6, iclass 23, count 0 2006.253.08:22:19.89#ibcon#read 6, iclass 23, count 0 2006.253.08:22:19.89#ibcon#end of sib2, iclass 23, count 0 2006.253.08:22:19.89#ibcon#*after write, iclass 23, count 0 2006.253.08:22:19.89#ibcon#*before return 0, iclass 23, count 0 2006.253.08:22:19.89#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.253.08:22:19.89#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.253.08:22:19.89#ibcon#about to clear, iclass 23 cls_cnt 0 2006.253.08:22:19.89#ibcon#cleared, iclass 23 cls_cnt 0 2006.253.08:22:19.89$vc4f8/valo=7,832.99 2006.253.08:22:19.89#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.253.08:22:19.89#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.253.08:22:19.89#ibcon#ireg 17 cls_cnt 0 2006.253.08:22:19.89#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.253.08:22:19.89#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.253.08:22:19.89#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.253.08:22:19.89#ibcon#enter wrdev, iclass 25, count 0 2006.253.08:22:19.89#ibcon#first serial, iclass 25, count 0 2006.253.08:22:19.89#ibcon#enter sib2, iclass 25, count 0 2006.253.08:22:19.89#ibcon#flushed, iclass 25, count 0 2006.253.08:22:19.89#ibcon#about to write, iclass 25, count 0 2006.253.08:22:19.89#ibcon#wrote, iclass 25, count 0 2006.253.08:22:19.89#ibcon#about to read 3, iclass 25, count 0 2006.253.08:22:19.91#ibcon#read 3, iclass 25, count 0 2006.253.08:22:19.91#ibcon#about to read 4, iclass 25, count 0 2006.253.08:22:19.91#ibcon#read 4, iclass 25, count 0 2006.253.08:22:19.91#ibcon#about to read 5, iclass 25, count 0 2006.253.08:22:19.91#ibcon#read 5, iclass 25, count 0 2006.253.08:22:19.91#ibcon#about to read 6, iclass 25, count 0 2006.253.08:22:19.91#ibcon#read 6, iclass 25, count 0 2006.253.08:22:19.91#ibcon#end of sib2, iclass 25, count 0 2006.253.08:22:19.91#ibcon#*mode == 0, iclass 25, count 0 2006.253.08:22:19.91#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.253.08:22:19.91#ibcon#[26=FRQ=07,832.99\r\n] 2006.253.08:22:19.91#ibcon#*before write, iclass 25, count 0 2006.253.08:22:19.91#ibcon#enter sib2, iclass 25, count 0 2006.253.08:22:19.91#ibcon#flushed, iclass 25, count 0 2006.253.08:22:19.91#ibcon#about to write, iclass 25, count 0 2006.253.08:22:19.91#ibcon#wrote, iclass 25, count 0 2006.253.08:22:19.91#ibcon#about to read 3, iclass 25, count 0 2006.253.08:22:19.95#ibcon#read 3, iclass 25, count 0 2006.253.08:22:19.95#ibcon#about to read 4, iclass 25, count 0 2006.253.08:22:19.95#ibcon#read 4, iclass 25, count 0 2006.253.08:22:19.95#ibcon#about to read 5, iclass 25, count 0 2006.253.08:22:19.95#ibcon#read 5, iclass 25, count 0 2006.253.08:22:19.95#ibcon#about to read 6, iclass 25, count 0 2006.253.08:22:19.95#ibcon#read 6, iclass 25, count 0 2006.253.08:22:19.95#ibcon#end of sib2, iclass 25, count 0 2006.253.08:22:19.95#ibcon#*after write, iclass 25, count 0 2006.253.08:22:19.95#ibcon#*before return 0, iclass 25, count 0 2006.253.08:22:19.95#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.253.08:22:19.95#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.253.08:22:19.95#ibcon#about to clear, iclass 25 cls_cnt 0 2006.253.08:22:19.95#ibcon#cleared, iclass 25 cls_cnt 0 2006.253.08:22:19.95$vc4f8/va=7,7 2006.253.08:22:19.95#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.253.08:22:19.95#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.253.08:22:19.95#ibcon#ireg 11 cls_cnt 2 2006.253.08:22:19.95#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.253.08:22:20.01#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.253.08:22:20.01#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.253.08:22:20.01#ibcon#enter wrdev, iclass 27, count 2 2006.253.08:22:20.01#ibcon#first serial, iclass 27, count 2 2006.253.08:22:20.01#ibcon#enter sib2, iclass 27, count 2 2006.253.08:22:20.01#ibcon#flushed, iclass 27, count 2 2006.253.08:22:20.01#ibcon#about to write, iclass 27, count 2 2006.253.08:22:20.01#ibcon#wrote, iclass 27, count 2 2006.253.08:22:20.01#ibcon#about to read 3, iclass 27, count 2 2006.253.08:22:20.03#ibcon#read 3, iclass 27, count 2 2006.253.08:22:20.03#ibcon#about to read 4, iclass 27, count 2 2006.253.08:22:20.03#ibcon#read 4, iclass 27, count 2 2006.253.08:22:20.03#ibcon#about to read 5, iclass 27, count 2 2006.253.08:22:20.03#ibcon#read 5, iclass 27, count 2 2006.253.08:22:20.03#ibcon#about to read 6, iclass 27, count 2 2006.253.08:22:20.03#ibcon#read 6, iclass 27, count 2 2006.253.08:22:20.03#ibcon#end of sib2, iclass 27, count 2 2006.253.08:22:20.03#ibcon#*mode == 0, iclass 27, count 2 2006.253.08:22:20.03#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.253.08:22:20.03#ibcon#[25=AT07-07\r\n] 2006.253.08:22:20.03#ibcon#*before write, iclass 27, count 2 2006.253.08:22:20.03#ibcon#enter sib2, iclass 27, count 2 2006.253.08:22:20.03#ibcon#flushed, iclass 27, count 2 2006.253.08:22:20.03#ibcon#about to write, iclass 27, count 2 2006.253.08:22:20.03#ibcon#wrote, iclass 27, count 2 2006.253.08:22:20.03#ibcon#about to read 3, iclass 27, count 2 2006.253.08:22:20.06#ibcon#read 3, iclass 27, count 2 2006.253.08:22:20.06#ibcon#about to read 4, iclass 27, count 2 2006.253.08:22:20.06#ibcon#read 4, iclass 27, count 2 2006.253.08:22:20.06#ibcon#about to read 5, iclass 27, count 2 2006.253.08:22:20.06#ibcon#read 5, iclass 27, count 2 2006.253.08:22:20.06#ibcon#about to read 6, iclass 27, count 2 2006.253.08:22:20.06#ibcon#read 6, iclass 27, count 2 2006.253.08:22:20.06#ibcon#end of sib2, iclass 27, count 2 2006.253.08:22:20.06#ibcon#*after write, iclass 27, count 2 2006.253.08:22:20.06#ibcon#*before return 0, iclass 27, count 2 2006.253.08:22:20.06#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.253.08:22:20.06#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.253.08:22:20.06#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.253.08:22:20.06#ibcon#ireg 7 cls_cnt 0 2006.253.08:22:20.06#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.253.08:22:20.18#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.253.08:22:20.18#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.253.08:22:20.18#ibcon#enter wrdev, iclass 27, count 0 2006.253.08:22:20.18#ibcon#first serial, iclass 27, count 0 2006.253.08:22:20.18#ibcon#enter sib2, iclass 27, count 0 2006.253.08:22:20.18#ibcon#flushed, iclass 27, count 0 2006.253.08:22:20.18#ibcon#about to write, iclass 27, count 0 2006.253.08:22:20.18#ibcon#wrote, iclass 27, count 0 2006.253.08:22:20.18#ibcon#about to read 3, iclass 27, count 0 2006.253.08:22:20.22#ibcon#read 3, iclass 27, count 0 2006.253.08:22:20.22#ibcon#about to read 4, iclass 27, count 0 2006.253.08:22:20.22#ibcon#read 4, iclass 27, count 0 2006.253.08:22:20.22#ibcon#about to read 5, iclass 27, count 0 2006.253.08:22:20.22#ibcon#read 5, iclass 27, count 0 2006.253.08:22:20.22#ibcon#about to read 6, iclass 27, count 0 2006.253.08:22:20.22#ibcon#read 6, iclass 27, count 0 2006.253.08:22:20.22#ibcon#end of sib2, iclass 27, count 0 2006.253.08:22:20.22#ibcon#*mode == 0, iclass 27, count 0 2006.253.08:22:20.22#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.253.08:22:20.22#ibcon#[25=USB\r\n] 2006.253.08:22:20.22#ibcon#*before write, iclass 27, count 0 2006.253.08:22:20.22#ibcon#enter sib2, iclass 27, count 0 2006.253.08:22:20.22#ibcon#flushed, iclass 27, count 0 2006.253.08:22:20.22#ibcon#about to write, iclass 27, count 0 2006.253.08:22:20.22#ibcon#wrote, iclass 27, count 0 2006.253.08:22:20.22#ibcon#about to read 3, iclass 27, count 0 2006.253.08:22:20.24#ibcon#read 3, iclass 27, count 0 2006.253.08:22:20.24#ibcon#about to read 4, iclass 27, count 0 2006.253.08:22:20.24#ibcon#read 4, iclass 27, count 0 2006.253.08:22:20.24#ibcon#about to read 5, iclass 27, count 0 2006.253.08:22:20.24#ibcon#read 5, iclass 27, count 0 2006.253.08:22:20.24#ibcon#about to read 6, iclass 27, count 0 2006.253.08:22:20.24#ibcon#read 6, iclass 27, count 0 2006.253.08:22:20.24#ibcon#end of sib2, iclass 27, count 0 2006.253.08:22:20.24#ibcon#*after write, iclass 27, count 0 2006.253.08:22:20.24#ibcon#*before return 0, iclass 27, count 0 2006.253.08:22:20.24#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.253.08:22:20.24#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.253.08:22:20.24#ibcon#about to clear, iclass 27 cls_cnt 0 2006.253.08:22:20.24#ibcon#cleared, iclass 27 cls_cnt 0 2006.253.08:22:20.24$vc4f8/valo=8,852.99 2006.253.08:22:20.24#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.253.08:22:20.24#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.253.08:22:20.24#ibcon#ireg 17 cls_cnt 0 2006.253.08:22:20.24#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.253.08:22:20.24#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.253.08:22:20.24#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.253.08:22:20.24#ibcon#enter wrdev, iclass 29, count 0 2006.253.08:22:20.24#ibcon#first serial, iclass 29, count 0 2006.253.08:22:20.24#ibcon#enter sib2, iclass 29, count 0 2006.253.08:22:20.24#ibcon#flushed, iclass 29, count 0 2006.253.08:22:20.24#ibcon#about to write, iclass 29, count 0 2006.253.08:22:20.24#ibcon#wrote, iclass 29, count 0 2006.253.08:22:20.25#ibcon#about to read 3, iclass 29, count 0 2006.253.08:22:20.26#ibcon#read 3, iclass 29, count 0 2006.253.08:22:20.26#ibcon#about to read 4, iclass 29, count 0 2006.253.08:22:20.26#ibcon#read 4, iclass 29, count 0 2006.253.08:22:20.26#ibcon#about to read 5, iclass 29, count 0 2006.253.08:22:20.26#ibcon#read 5, iclass 29, count 0 2006.253.08:22:20.26#ibcon#about to read 6, iclass 29, count 0 2006.253.08:22:20.26#ibcon#read 6, iclass 29, count 0 2006.253.08:22:20.26#ibcon#end of sib2, iclass 29, count 0 2006.253.08:22:20.26#ibcon#*mode == 0, iclass 29, count 0 2006.253.08:22:20.26#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.253.08:22:20.26#ibcon#[26=FRQ=08,852.99\r\n] 2006.253.08:22:20.26#ibcon#*before write, iclass 29, count 0 2006.253.08:22:20.26#ibcon#enter sib2, iclass 29, count 0 2006.253.08:22:20.26#ibcon#flushed, iclass 29, count 0 2006.253.08:22:20.26#ibcon#about to write, iclass 29, count 0 2006.253.08:22:20.26#ibcon#wrote, iclass 29, count 0 2006.253.08:22:20.26#ibcon#about to read 3, iclass 29, count 0 2006.253.08:22:20.31#ibcon#read 3, iclass 29, count 0 2006.253.08:22:20.31#ibcon#about to read 4, iclass 29, count 0 2006.253.08:22:20.31#ibcon#read 4, iclass 29, count 0 2006.253.08:22:20.31#ibcon#about to read 5, iclass 29, count 0 2006.253.08:22:20.31#ibcon#read 5, iclass 29, count 0 2006.253.08:22:20.31#ibcon#about to read 6, iclass 29, count 0 2006.253.08:22:20.31#ibcon#read 6, iclass 29, count 0 2006.253.08:22:20.31#ibcon#end of sib2, iclass 29, count 0 2006.253.08:22:20.31#ibcon#*after write, iclass 29, count 0 2006.253.08:22:20.31#ibcon#*before return 0, iclass 29, count 0 2006.253.08:22:20.31#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.253.08:22:20.31#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.253.08:22:20.31#ibcon#about to clear, iclass 29 cls_cnt 0 2006.253.08:22:20.31#ibcon#cleared, iclass 29 cls_cnt 0 2006.253.08:22:20.31$vc4f8/va=8,7 2006.253.08:22:20.31#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.253.08:22:20.31#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.253.08:22:20.31#ibcon#ireg 11 cls_cnt 2 2006.253.08:22:20.31#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.253.08:22:20.35#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.253.08:22:20.35#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.253.08:22:20.35#ibcon#enter wrdev, iclass 31, count 2 2006.253.08:22:20.35#ibcon#first serial, iclass 31, count 2 2006.253.08:22:20.35#ibcon#enter sib2, iclass 31, count 2 2006.253.08:22:20.35#ibcon#flushed, iclass 31, count 2 2006.253.08:22:20.35#ibcon#about to write, iclass 31, count 2 2006.253.08:22:20.35#ibcon#wrote, iclass 31, count 2 2006.253.08:22:20.35#ibcon#about to read 3, iclass 31, count 2 2006.253.08:22:20.37#ibcon#read 3, iclass 31, count 2 2006.253.08:22:20.37#ibcon#about to read 4, iclass 31, count 2 2006.253.08:22:20.37#ibcon#read 4, iclass 31, count 2 2006.253.08:22:20.37#ibcon#about to read 5, iclass 31, count 2 2006.253.08:22:20.37#ibcon#read 5, iclass 31, count 2 2006.253.08:22:20.37#ibcon#about to read 6, iclass 31, count 2 2006.253.08:22:20.37#ibcon#read 6, iclass 31, count 2 2006.253.08:22:20.37#ibcon#end of sib2, iclass 31, count 2 2006.253.08:22:20.37#ibcon#*mode == 0, iclass 31, count 2 2006.253.08:22:20.37#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.253.08:22:20.37#ibcon#[25=AT08-07\r\n] 2006.253.08:22:20.37#ibcon#*before write, iclass 31, count 2 2006.253.08:22:20.37#ibcon#enter sib2, iclass 31, count 2 2006.253.08:22:20.37#ibcon#flushed, iclass 31, count 2 2006.253.08:22:20.37#ibcon#about to write, iclass 31, count 2 2006.253.08:22:20.37#ibcon#wrote, iclass 31, count 2 2006.253.08:22:20.37#ibcon#about to read 3, iclass 31, count 2 2006.253.08:22:20.40#ibcon#read 3, iclass 31, count 2 2006.253.08:22:20.40#ibcon#about to read 4, iclass 31, count 2 2006.253.08:22:20.40#ibcon#read 4, iclass 31, count 2 2006.253.08:22:20.40#ibcon#about to read 5, iclass 31, count 2 2006.253.08:22:20.40#ibcon#read 5, iclass 31, count 2 2006.253.08:22:20.40#ibcon#about to read 6, iclass 31, count 2 2006.253.08:22:20.40#ibcon#read 6, iclass 31, count 2 2006.253.08:22:20.40#ibcon#end of sib2, iclass 31, count 2 2006.253.08:22:20.40#ibcon#*after write, iclass 31, count 2 2006.253.08:22:20.40#ibcon#*before return 0, iclass 31, count 2 2006.253.08:22:20.40#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.253.08:22:20.40#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.253.08:22:20.40#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.253.08:22:20.40#ibcon#ireg 7 cls_cnt 0 2006.253.08:22:20.40#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.253.08:22:20.52#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.253.08:22:20.52#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.253.08:22:20.52#ibcon#enter wrdev, iclass 31, count 0 2006.253.08:22:20.52#ibcon#first serial, iclass 31, count 0 2006.253.08:22:20.52#ibcon#enter sib2, iclass 31, count 0 2006.253.08:22:20.52#ibcon#flushed, iclass 31, count 0 2006.253.08:22:20.52#ibcon#about to write, iclass 31, count 0 2006.253.08:22:20.52#ibcon#wrote, iclass 31, count 0 2006.253.08:22:20.52#ibcon#about to read 3, iclass 31, count 0 2006.253.08:22:20.54#ibcon#read 3, iclass 31, count 0 2006.253.08:22:20.54#ibcon#about to read 4, iclass 31, count 0 2006.253.08:22:20.54#ibcon#read 4, iclass 31, count 0 2006.253.08:22:20.54#ibcon#about to read 5, iclass 31, count 0 2006.253.08:22:20.54#ibcon#read 5, iclass 31, count 0 2006.253.08:22:20.54#ibcon#about to read 6, iclass 31, count 0 2006.253.08:22:20.54#ibcon#read 6, iclass 31, count 0 2006.253.08:22:20.54#ibcon#end of sib2, iclass 31, count 0 2006.253.08:22:20.54#ibcon#*mode == 0, iclass 31, count 0 2006.253.08:22:20.54#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.253.08:22:20.54#ibcon#[25=USB\r\n] 2006.253.08:22:20.54#ibcon#*before write, iclass 31, count 0 2006.253.08:22:20.54#ibcon#enter sib2, iclass 31, count 0 2006.253.08:22:20.54#ibcon#flushed, iclass 31, count 0 2006.253.08:22:20.54#ibcon#about to write, iclass 31, count 0 2006.253.08:22:20.54#ibcon#wrote, iclass 31, count 0 2006.253.08:22:20.54#ibcon#about to read 3, iclass 31, count 0 2006.253.08:22:20.57#ibcon#read 3, iclass 31, count 0 2006.253.08:22:20.57#ibcon#about to read 4, iclass 31, count 0 2006.253.08:22:20.57#ibcon#read 4, iclass 31, count 0 2006.253.08:22:20.57#ibcon#about to read 5, iclass 31, count 0 2006.253.08:22:20.57#ibcon#read 5, iclass 31, count 0 2006.253.08:22:20.57#ibcon#about to read 6, iclass 31, count 0 2006.253.08:22:20.57#ibcon#read 6, iclass 31, count 0 2006.253.08:22:20.57#ibcon#end of sib2, iclass 31, count 0 2006.253.08:22:20.57#ibcon#*after write, iclass 31, count 0 2006.253.08:22:20.57#ibcon#*before return 0, iclass 31, count 0 2006.253.08:22:20.57#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.253.08:22:20.57#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.253.08:22:20.57#ibcon#about to clear, iclass 31 cls_cnt 0 2006.253.08:22:20.57#ibcon#cleared, iclass 31 cls_cnt 0 2006.253.08:22:20.57$vc4f8/vblo=1,632.99 2006.253.08:22:20.57#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.253.08:22:20.57#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.253.08:22:20.57#ibcon#ireg 17 cls_cnt 0 2006.253.08:22:20.57#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.253.08:22:20.57#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.253.08:22:20.57#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.253.08:22:20.57#ibcon#enter wrdev, iclass 33, count 0 2006.253.08:22:20.57#ibcon#first serial, iclass 33, count 0 2006.253.08:22:20.57#ibcon#enter sib2, iclass 33, count 0 2006.253.08:22:20.57#ibcon#flushed, iclass 33, count 0 2006.253.08:22:20.57#ibcon#about to write, iclass 33, count 0 2006.253.08:22:20.57#ibcon#wrote, iclass 33, count 0 2006.253.08:22:20.57#ibcon#about to read 3, iclass 33, count 0 2006.253.08:22:20.59#ibcon#read 3, iclass 33, count 0 2006.253.08:22:20.59#ibcon#about to read 4, iclass 33, count 0 2006.253.08:22:20.59#ibcon#read 4, iclass 33, count 0 2006.253.08:22:20.59#ibcon#about to read 5, iclass 33, count 0 2006.253.08:22:20.59#ibcon#read 5, iclass 33, count 0 2006.253.08:22:20.59#ibcon#about to read 6, iclass 33, count 0 2006.253.08:22:20.59#ibcon#read 6, iclass 33, count 0 2006.253.08:22:20.59#ibcon#end of sib2, iclass 33, count 0 2006.253.08:22:20.59#ibcon#*mode == 0, iclass 33, count 0 2006.253.08:22:20.59#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.253.08:22:20.59#ibcon#[28=FRQ=01,632.99\r\n] 2006.253.08:22:20.59#ibcon#*before write, iclass 33, count 0 2006.253.08:22:20.59#ibcon#enter sib2, iclass 33, count 0 2006.253.08:22:20.59#ibcon#flushed, iclass 33, count 0 2006.253.08:22:20.59#ibcon#about to write, iclass 33, count 0 2006.253.08:22:20.59#ibcon#wrote, iclass 33, count 0 2006.253.08:22:20.59#ibcon#about to read 3, iclass 33, count 0 2006.253.08:22:20.63#ibcon#read 3, iclass 33, count 0 2006.253.08:22:20.63#ibcon#about to read 4, iclass 33, count 0 2006.253.08:22:20.63#ibcon#read 4, iclass 33, count 0 2006.253.08:22:20.63#ibcon#about to read 5, iclass 33, count 0 2006.253.08:22:20.63#ibcon#read 5, iclass 33, count 0 2006.253.08:22:20.63#ibcon#about to read 6, iclass 33, count 0 2006.253.08:22:20.63#ibcon#read 6, iclass 33, count 0 2006.253.08:22:20.63#ibcon#end of sib2, iclass 33, count 0 2006.253.08:22:20.63#ibcon#*after write, iclass 33, count 0 2006.253.08:22:20.63#ibcon#*before return 0, iclass 33, count 0 2006.253.08:22:20.63#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.253.08:22:20.63#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.253.08:22:20.63#ibcon#about to clear, iclass 33 cls_cnt 0 2006.253.08:22:20.63#ibcon#cleared, iclass 33 cls_cnt 0 2006.253.08:22:20.63$vc4f8/vb=1,4 2006.253.08:22:20.63#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.253.08:22:20.63#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.253.08:22:20.63#ibcon#ireg 11 cls_cnt 2 2006.253.08:22:20.63#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.253.08:22:20.63#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.253.08:22:20.63#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.253.08:22:20.63#ibcon#enter wrdev, iclass 35, count 2 2006.253.08:22:20.63#ibcon#first serial, iclass 35, count 2 2006.253.08:22:20.63#ibcon#enter sib2, iclass 35, count 2 2006.253.08:22:20.63#ibcon#flushed, iclass 35, count 2 2006.253.08:22:20.63#ibcon#about to write, iclass 35, count 2 2006.253.08:22:20.63#ibcon#wrote, iclass 35, count 2 2006.253.08:22:20.63#ibcon#about to read 3, iclass 35, count 2 2006.253.08:22:20.65#ibcon#read 3, iclass 35, count 2 2006.253.08:22:20.65#ibcon#about to read 4, iclass 35, count 2 2006.253.08:22:20.65#ibcon#read 4, iclass 35, count 2 2006.253.08:22:20.65#ibcon#about to read 5, iclass 35, count 2 2006.253.08:22:20.65#ibcon#read 5, iclass 35, count 2 2006.253.08:22:20.65#ibcon#about to read 6, iclass 35, count 2 2006.253.08:22:20.65#ibcon#read 6, iclass 35, count 2 2006.253.08:22:20.65#ibcon#end of sib2, iclass 35, count 2 2006.253.08:22:20.65#ibcon#*mode == 0, iclass 35, count 2 2006.253.08:22:20.65#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.253.08:22:20.65#ibcon#[27=AT01-04\r\n] 2006.253.08:22:20.65#ibcon#*before write, iclass 35, count 2 2006.253.08:22:20.65#ibcon#enter sib2, iclass 35, count 2 2006.253.08:22:20.65#ibcon#flushed, iclass 35, count 2 2006.253.08:22:20.65#ibcon#about to write, iclass 35, count 2 2006.253.08:22:20.65#ibcon#wrote, iclass 35, count 2 2006.253.08:22:20.65#ibcon#about to read 3, iclass 35, count 2 2006.253.08:22:20.68#ibcon#read 3, iclass 35, count 2 2006.253.08:22:20.68#ibcon#about to read 4, iclass 35, count 2 2006.253.08:22:20.68#ibcon#read 4, iclass 35, count 2 2006.253.08:22:20.68#ibcon#about to read 5, iclass 35, count 2 2006.253.08:22:20.68#ibcon#read 5, iclass 35, count 2 2006.253.08:22:20.68#ibcon#about to read 6, iclass 35, count 2 2006.253.08:22:20.68#ibcon#read 6, iclass 35, count 2 2006.253.08:22:20.68#ibcon#end of sib2, iclass 35, count 2 2006.253.08:22:20.68#ibcon#*after write, iclass 35, count 2 2006.253.08:22:20.68#ibcon#*before return 0, iclass 35, count 2 2006.253.08:22:20.68#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.253.08:22:20.68#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.253.08:22:20.68#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.253.08:22:20.68#ibcon#ireg 7 cls_cnt 0 2006.253.08:22:20.68#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.253.08:22:20.80#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.253.08:22:20.80#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.253.08:22:20.80#ibcon#enter wrdev, iclass 35, count 0 2006.253.08:22:20.80#ibcon#first serial, iclass 35, count 0 2006.253.08:22:20.80#ibcon#enter sib2, iclass 35, count 0 2006.253.08:22:20.80#ibcon#flushed, iclass 35, count 0 2006.253.08:22:20.80#ibcon#about to write, iclass 35, count 0 2006.253.08:22:20.80#ibcon#wrote, iclass 35, count 0 2006.253.08:22:20.80#ibcon#about to read 3, iclass 35, count 0 2006.253.08:22:20.82#ibcon#read 3, iclass 35, count 0 2006.253.08:22:20.82#ibcon#about to read 4, iclass 35, count 0 2006.253.08:22:20.82#ibcon#read 4, iclass 35, count 0 2006.253.08:22:20.82#ibcon#about to read 5, iclass 35, count 0 2006.253.08:22:20.82#ibcon#read 5, iclass 35, count 0 2006.253.08:22:20.82#ibcon#about to read 6, iclass 35, count 0 2006.253.08:22:20.82#ibcon#read 6, iclass 35, count 0 2006.253.08:22:20.82#ibcon#end of sib2, iclass 35, count 0 2006.253.08:22:20.82#ibcon#*mode == 0, iclass 35, count 0 2006.253.08:22:20.82#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.253.08:22:20.82#ibcon#[27=USB\r\n] 2006.253.08:22:20.82#ibcon#*before write, iclass 35, count 0 2006.253.08:22:20.82#ibcon#enter sib2, iclass 35, count 0 2006.253.08:22:20.82#ibcon#flushed, iclass 35, count 0 2006.253.08:22:20.82#ibcon#about to write, iclass 35, count 0 2006.253.08:22:20.82#ibcon#wrote, iclass 35, count 0 2006.253.08:22:20.82#ibcon#about to read 3, iclass 35, count 0 2006.253.08:22:20.85#ibcon#read 3, iclass 35, count 0 2006.253.08:22:20.85#ibcon#about to read 4, iclass 35, count 0 2006.253.08:22:20.85#ibcon#read 4, iclass 35, count 0 2006.253.08:22:20.85#ibcon#about to read 5, iclass 35, count 0 2006.253.08:22:20.85#ibcon#read 5, iclass 35, count 0 2006.253.08:22:20.85#ibcon#about to read 6, iclass 35, count 0 2006.253.08:22:20.85#ibcon#read 6, iclass 35, count 0 2006.253.08:22:20.85#ibcon#end of sib2, iclass 35, count 0 2006.253.08:22:20.85#ibcon#*after write, iclass 35, count 0 2006.253.08:22:20.85#ibcon#*before return 0, iclass 35, count 0 2006.253.08:22:20.85#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.253.08:22:20.85#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.253.08:22:20.85#ibcon#about to clear, iclass 35 cls_cnt 0 2006.253.08:22:20.85#ibcon#cleared, iclass 35 cls_cnt 0 2006.253.08:22:20.85$vc4f8/vblo=2,640.99 2006.253.08:22:20.85#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.253.08:22:20.85#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.253.08:22:20.85#ibcon#ireg 17 cls_cnt 0 2006.253.08:22:20.85#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.253.08:22:20.85#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.253.08:22:20.85#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.253.08:22:20.85#ibcon#enter wrdev, iclass 37, count 0 2006.253.08:22:20.85#ibcon#first serial, iclass 37, count 0 2006.253.08:22:20.85#ibcon#enter sib2, iclass 37, count 0 2006.253.08:22:20.85#ibcon#flushed, iclass 37, count 0 2006.253.08:22:20.85#ibcon#about to write, iclass 37, count 0 2006.253.08:22:20.85#ibcon#wrote, iclass 37, count 0 2006.253.08:22:20.85#ibcon#about to read 3, iclass 37, count 0 2006.253.08:22:20.87#ibcon#read 3, iclass 37, count 0 2006.253.08:22:20.87#ibcon#about to read 4, iclass 37, count 0 2006.253.08:22:20.87#ibcon#read 4, iclass 37, count 0 2006.253.08:22:20.87#ibcon#about to read 5, iclass 37, count 0 2006.253.08:22:20.87#ibcon#read 5, iclass 37, count 0 2006.253.08:22:20.87#ibcon#about to read 6, iclass 37, count 0 2006.253.08:22:20.87#ibcon#read 6, iclass 37, count 0 2006.253.08:22:20.87#ibcon#end of sib2, iclass 37, count 0 2006.253.08:22:20.87#ibcon#*mode == 0, iclass 37, count 0 2006.253.08:22:20.87#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.253.08:22:20.87#ibcon#[28=FRQ=02,640.99\r\n] 2006.253.08:22:20.87#ibcon#*before write, iclass 37, count 0 2006.253.08:22:20.87#ibcon#enter sib2, iclass 37, count 0 2006.253.08:22:20.87#ibcon#flushed, iclass 37, count 0 2006.253.08:22:20.87#ibcon#about to write, iclass 37, count 0 2006.253.08:22:20.87#ibcon#wrote, iclass 37, count 0 2006.253.08:22:20.87#ibcon#about to read 3, iclass 37, count 0 2006.253.08:22:20.91#ibcon#read 3, iclass 37, count 0 2006.253.08:22:20.91#ibcon#about to read 4, iclass 37, count 0 2006.253.08:22:20.91#ibcon#read 4, iclass 37, count 0 2006.253.08:22:20.91#ibcon#about to read 5, iclass 37, count 0 2006.253.08:22:20.91#ibcon#read 5, iclass 37, count 0 2006.253.08:22:20.91#ibcon#about to read 6, iclass 37, count 0 2006.253.08:22:20.91#ibcon#read 6, iclass 37, count 0 2006.253.08:22:20.91#ibcon#end of sib2, iclass 37, count 0 2006.253.08:22:20.91#ibcon#*after write, iclass 37, count 0 2006.253.08:22:20.91#ibcon#*before return 0, iclass 37, count 0 2006.253.08:22:20.91#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.253.08:22:20.91#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.253.08:22:20.91#ibcon#about to clear, iclass 37 cls_cnt 0 2006.253.08:22:20.91#ibcon#cleared, iclass 37 cls_cnt 0 2006.253.08:22:20.91$vc4f8/vb=2,5 2006.253.08:22:20.91#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.253.08:22:20.91#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.253.08:22:20.91#ibcon#ireg 11 cls_cnt 2 2006.253.08:22:20.91#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.253.08:22:20.97#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.253.08:22:20.97#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.253.08:22:20.97#ibcon#enter wrdev, iclass 39, count 2 2006.253.08:22:20.97#ibcon#first serial, iclass 39, count 2 2006.253.08:22:20.97#ibcon#enter sib2, iclass 39, count 2 2006.253.08:22:20.97#ibcon#flushed, iclass 39, count 2 2006.253.08:22:20.97#ibcon#about to write, iclass 39, count 2 2006.253.08:22:20.97#ibcon#wrote, iclass 39, count 2 2006.253.08:22:20.97#ibcon#about to read 3, iclass 39, count 2 2006.253.08:22:20.99#ibcon#read 3, iclass 39, count 2 2006.253.08:22:20.99#ibcon#about to read 4, iclass 39, count 2 2006.253.08:22:20.99#ibcon#read 4, iclass 39, count 2 2006.253.08:22:20.99#ibcon#about to read 5, iclass 39, count 2 2006.253.08:22:20.99#ibcon#read 5, iclass 39, count 2 2006.253.08:22:20.99#ibcon#about to read 6, iclass 39, count 2 2006.253.08:22:20.99#ibcon#read 6, iclass 39, count 2 2006.253.08:22:20.99#ibcon#end of sib2, iclass 39, count 2 2006.253.08:22:20.99#ibcon#*mode == 0, iclass 39, count 2 2006.253.08:22:20.99#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.253.08:22:20.99#ibcon#[27=AT02-05\r\n] 2006.253.08:22:20.99#ibcon#*before write, iclass 39, count 2 2006.253.08:22:20.99#ibcon#enter sib2, iclass 39, count 2 2006.253.08:22:20.99#ibcon#flushed, iclass 39, count 2 2006.253.08:22:20.99#ibcon#about to write, iclass 39, count 2 2006.253.08:22:20.99#ibcon#wrote, iclass 39, count 2 2006.253.08:22:20.99#ibcon#about to read 3, iclass 39, count 2 2006.253.08:22:21.02#ibcon#read 3, iclass 39, count 2 2006.253.08:22:21.02#ibcon#about to read 4, iclass 39, count 2 2006.253.08:22:21.02#ibcon#read 4, iclass 39, count 2 2006.253.08:22:21.02#ibcon#about to read 5, iclass 39, count 2 2006.253.08:22:21.02#ibcon#read 5, iclass 39, count 2 2006.253.08:22:21.02#ibcon#about to read 6, iclass 39, count 2 2006.253.08:22:21.02#ibcon#read 6, iclass 39, count 2 2006.253.08:22:21.02#ibcon#end of sib2, iclass 39, count 2 2006.253.08:22:21.02#ibcon#*after write, iclass 39, count 2 2006.253.08:22:21.02#ibcon#*before return 0, iclass 39, count 2 2006.253.08:22:21.02#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.253.08:22:21.02#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.253.08:22:21.02#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.253.08:22:21.02#ibcon#ireg 7 cls_cnt 0 2006.253.08:22:21.02#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.253.08:22:21.14#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.253.08:22:21.14#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.253.08:22:21.14#ibcon#enter wrdev, iclass 39, count 0 2006.253.08:22:21.14#ibcon#first serial, iclass 39, count 0 2006.253.08:22:21.15#ibcon#enter sib2, iclass 39, count 0 2006.253.08:22:21.15#ibcon#flushed, iclass 39, count 0 2006.253.08:22:21.15#ibcon#about to write, iclass 39, count 0 2006.253.08:22:21.15#ibcon#wrote, iclass 39, count 0 2006.253.08:22:21.15#ibcon#about to read 3, iclass 39, count 0 2006.253.08:22:21.16#ibcon#read 3, iclass 39, count 0 2006.253.08:22:21.16#ibcon#about to read 4, iclass 39, count 0 2006.253.08:22:21.16#ibcon#read 4, iclass 39, count 0 2006.253.08:22:21.16#ibcon#about to read 5, iclass 39, count 0 2006.253.08:22:21.16#ibcon#read 5, iclass 39, count 0 2006.253.08:22:21.16#ibcon#about to read 6, iclass 39, count 0 2006.253.08:22:21.16#ibcon#read 6, iclass 39, count 0 2006.253.08:22:21.16#ibcon#end of sib2, iclass 39, count 0 2006.253.08:22:21.16#ibcon#*mode == 0, iclass 39, count 0 2006.253.08:22:21.16#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.253.08:22:21.16#ibcon#[27=USB\r\n] 2006.253.08:22:21.16#ibcon#*before write, iclass 39, count 0 2006.253.08:22:21.16#ibcon#enter sib2, iclass 39, count 0 2006.253.08:22:21.16#ibcon#flushed, iclass 39, count 0 2006.253.08:22:21.16#ibcon#about to write, iclass 39, count 0 2006.253.08:22:21.16#ibcon#wrote, iclass 39, count 0 2006.253.08:22:21.16#ibcon#about to read 3, iclass 39, count 0 2006.253.08:22:21.19#ibcon#read 3, iclass 39, count 0 2006.253.08:22:21.19#ibcon#about to read 4, iclass 39, count 0 2006.253.08:22:21.19#ibcon#read 4, iclass 39, count 0 2006.253.08:22:21.19#ibcon#about to read 5, iclass 39, count 0 2006.253.08:22:21.19#ibcon#read 5, iclass 39, count 0 2006.253.08:22:21.19#ibcon#about to read 6, iclass 39, count 0 2006.253.08:22:21.19#ibcon#read 6, iclass 39, count 0 2006.253.08:22:21.19#ibcon#end of sib2, iclass 39, count 0 2006.253.08:22:21.19#ibcon#*after write, iclass 39, count 0 2006.253.08:22:21.19#ibcon#*before return 0, iclass 39, count 0 2006.253.08:22:21.19#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.253.08:22:21.19#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.253.08:22:21.19#ibcon#about to clear, iclass 39 cls_cnt 0 2006.253.08:22:21.19#ibcon#cleared, iclass 39 cls_cnt 0 2006.253.08:22:21.19$vc4f8/vblo=3,656.99 2006.253.08:22:21.19#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.253.08:22:21.19#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.253.08:22:21.19#ibcon#ireg 17 cls_cnt 0 2006.253.08:22:21.19#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.253.08:22:21.19#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.253.08:22:21.19#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.253.08:22:21.19#ibcon#enter wrdev, iclass 3, count 0 2006.253.08:22:21.19#ibcon#first serial, iclass 3, count 0 2006.253.08:22:21.19#ibcon#enter sib2, iclass 3, count 0 2006.253.08:22:21.19#ibcon#flushed, iclass 3, count 0 2006.253.08:22:21.19#ibcon#about to write, iclass 3, count 0 2006.253.08:22:21.19#ibcon#wrote, iclass 3, count 0 2006.253.08:22:21.19#ibcon#about to read 3, iclass 3, count 0 2006.253.08:22:21.22#ibcon#read 3, iclass 3, count 0 2006.253.08:22:21.22#ibcon#about to read 4, iclass 3, count 0 2006.253.08:22:21.22#ibcon#read 4, iclass 3, count 0 2006.253.08:22:21.22#ibcon#about to read 5, iclass 3, count 0 2006.253.08:22:21.22#ibcon#read 5, iclass 3, count 0 2006.253.08:22:21.22#ibcon#about to read 6, iclass 3, count 0 2006.253.08:22:21.22#ibcon#read 6, iclass 3, count 0 2006.253.08:22:21.22#ibcon#end of sib2, iclass 3, count 0 2006.253.08:22:21.22#ibcon#*mode == 0, iclass 3, count 0 2006.253.08:22:21.22#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.253.08:22:21.22#ibcon#[28=FRQ=03,656.99\r\n] 2006.253.08:22:21.22#ibcon#*before write, iclass 3, count 0 2006.253.08:22:21.22#ibcon#enter sib2, iclass 3, count 0 2006.253.08:22:21.22#ibcon#flushed, iclass 3, count 0 2006.253.08:22:21.22#ibcon#about to write, iclass 3, count 0 2006.253.08:22:21.22#ibcon#wrote, iclass 3, count 0 2006.253.08:22:21.22#ibcon#about to read 3, iclass 3, count 0 2006.253.08:22:21.26#ibcon#read 3, iclass 3, count 0 2006.253.08:22:21.26#ibcon#about to read 4, iclass 3, count 0 2006.253.08:22:21.26#ibcon#read 4, iclass 3, count 0 2006.253.08:22:21.26#ibcon#about to read 5, iclass 3, count 0 2006.253.08:22:21.26#ibcon#read 5, iclass 3, count 0 2006.253.08:22:21.26#ibcon#about to read 6, iclass 3, count 0 2006.253.08:22:21.26#ibcon#read 6, iclass 3, count 0 2006.253.08:22:21.26#ibcon#end of sib2, iclass 3, count 0 2006.253.08:22:21.26#ibcon#*after write, iclass 3, count 0 2006.253.08:22:21.26#ibcon#*before return 0, iclass 3, count 0 2006.253.08:22:21.26#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.253.08:22:21.26#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.253.08:22:21.26#ibcon#about to clear, iclass 3 cls_cnt 0 2006.253.08:22:21.26#ibcon#cleared, iclass 3 cls_cnt 0 2006.253.08:22:21.26$vc4f8/vb=3,4 2006.253.08:22:21.26#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.253.08:22:21.26#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.253.08:22:21.26#ibcon#ireg 11 cls_cnt 2 2006.253.08:22:21.26#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.253.08:22:21.31#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.253.08:22:21.31#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.253.08:22:21.31#ibcon#enter wrdev, iclass 5, count 2 2006.253.08:22:21.31#ibcon#first serial, iclass 5, count 2 2006.253.08:22:21.31#ibcon#enter sib2, iclass 5, count 2 2006.253.08:22:21.31#ibcon#flushed, iclass 5, count 2 2006.253.08:22:21.31#ibcon#about to write, iclass 5, count 2 2006.253.08:22:21.31#ibcon#wrote, iclass 5, count 2 2006.253.08:22:21.31#ibcon#about to read 3, iclass 5, count 2 2006.253.08:22:21.33#ibcon#read 3, iclass 5, count 2 2006.253.08:22:21.33#ibcon#about to read 4, iclass 5, count 2 2006.253.08:22:21.33#ibcon#read 4, iclass 5, count 2 2006.253.08:22:21.33#ibcon#about to read 5, iclass 5, count 2 2006.253.08:22:21.33#ibcon#read 5, iclass 5, count 2 2006.253.08:22:21.33#ibcon#about to read 6, iclass 5, count 2 2006.253.08:22:21.33#ibcon#read 6, iclass 5, count 2 2006.253.08:22:21.33#ibcon#end of sib2, iclass 5, count 2 2006.253.08:22:21.33#ibcon#*mode == 0, iclass 5, count 2 2006.253.08:22:21.33#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.253.08:22:21.33#ibcon#[27=AT03-04\r\n] 2006.253.08:22:21.33#ibcon#*before write, iclass 5, count 2 2006.253.08:22:21.33#ibcon#enter sib2, iclass 5, count 2 2006.253.08:22:21.33#ibcon#flushed, iclass 5, count 2 2006.253.08:22:21.33#ibcon#about to write, iclass 5, count 2 2006.253.08:22:21.33#ibcon#wrote, iclass 5, count 2 2006.253.08:22:21.33#ibcon#about to read 3, iclass 5, count 2 2006.253.08:22:21.36#ibcon#read 3, iclass 5, count 2 2006.253.08:22:21.36#ibcon#about to read 4, iclass 5, count 2 2006.253.08:22:21.36#ibcon#read 4, iclass 5, count 2 2006.253.08:22:21.36#ibcon#about to read 5, iclass 5, count 2 2006.253.08:22:21.36#ibcon#read 5, iclass 5, count 2 2006.253.08:22:21.36#ibcon#about to read 6, iclass 5, count 2 2006.253.08:22:21.36#ibcon#read 6, iclass 5, count 2 2006.253.08:22:21.36#ibcon#end of sib2, iclass 5, count 2 2006.253.08:22:21.36#ibcon#*after write, iclass 5, count 2 2006.253.08:22:21.36#ibcon#*before return 0, iclass 5, count 2 2006.253.08:22:21.36#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.253.08:22:21.36#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.253.08:22:21.36#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.253.08:22:21.36#ibcon#ireg 7 cls_cnt 0 2006.253.08:22:21.36#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.253.08:22:21.48#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.253.08:22:21.48#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.253.08:22:21.48#ibcon#enter wrdev, iclass 5, count 0 2006.253.08:22:21.48#ibcon#first serial, iclass 5, count 0 2006.253.08:22:21.48#ibcon#enter sib2, iclass 5, count 0 2006.253.08:22:21.48#ibcon#flushed, iclass 5, count 0 2006.253.08:22:21.48#ibcon#about to write, iclass 5, count 0 2006.253.08:22:21.48#ibcon#wrote, iclass 5, count 0 2006.253.08:22:21.48#ibcon#about to read 3, iclass 5, count 0 2006.253.08:22:21.50#ibcon#read 3, iclass 5, count 0 2006.253.08:22:21.50#ibcon#about to read 4, iclass 5, count 0 2006.253.08:22:21.50#ibcon#read 4, iclass 5, count 0 2006.253.08:22:21.50#ibcon#about to read 5, iclass 5, count 0 2006.253.08:22:21.50#ibcon#read 5, iclass 5, count 0 2006.253.08:22:21.50#ibcon#about to read 6, iclass 5, count 0 2006.253.08:22:21.50#ibcon#read 6, iclass 5, count 0 2006.253.08:22:21.50#ibcon#end of sib2, iclass 5, count 0 2006.253.08:22:21.50#ibcon#*mode == 0, iclass 5, count 0 2006.253.08:22:21.50#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.253.08:22:21.50#ibcon#[27=USB\r\n] 2006.253.08:22:21.50#ibcon#*before write, iclass 5, count 0 2006.253.08:22:21.50#ibcon#enter sib2, iclass 5, count 0 2006.253.08:22:21.50#ibcon#flushed, iclass 5, count 0 2006.253.08:22:21.50#ibcon#about to write, iclass 5, count 0 2006.253.08:22:21.50#ibcon#wrote, iclass 5, count 0 2006.253.08:22:21.50#ibcon#about to read 3, iclass 5, count 0 2006.253.08:22:21.53#ibcon#read 3, iclass 5, count 0 2006.253.08:22:21.53#ibcon#about to read 4, iclass 5, count 0 2006.253.08:22:21.53#ibcon#read 4, iclass 5, count 0 2006.253.08:22:21.53#ibcon#about to read 5, iclass 5, count 0 2006.253.08:22:21.53#ibcon#read 5, iclass 5, count 0 2006.253.08:22:21.53#ibcon#about to read 6, iclass 5, count 0 2006.253.08:22:21.53#ibcon#read 6, iclass 5, count 0 2006.253.08:22:21.53#ibcon#end of sib2, iclass 5, count 0 2006.253.08:22:21.53#ibcon#*after write, iclass 5, count 0 2006.253.08:22:21.53#ibcon#*before return 0, iclass 5, count 0 2006.253.08:22:21.53#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.253.08:22:21.53#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.253.08:22:21.53#ibcon#about to clear, iclass 5 cls_cnt 0 2006.253.08:22:21.53#ibcon#cleared, iclass 5 cls_cnt 0 2006.253.08:22:21.53$vc4f8/vblo=4,712.99 2006.253.08:22:21.53#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.253.08:22:21.53#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.253.08:22:21.53#ibcon#ireg 17 cls_cnt 0 2006.253.08:22:21.53#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.253.08:22:21.53#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.253.08:22:21.53#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.253.08:22:21.53#ibcon#enter wrdev, iclass 7, count 0 2006.253.08:22:21.53#ibcon#first serial, iclass 7, count 0 2006.253.08:22:21.53#ibcon#enter sib2, iclass 7, count 0 2006.253.08:22:21.53#ibcon#flushed, iclass 7, count 0 2006.253.08:22:21.53#ibcon#about to write, iclass 7, count 0 2006.253.08:22:21.53#ibcon#wrote, iclass 7, count 0 2006.253.08:22:21.53#ibcon#about to read 3, iclass 7, count 0 2006.253.08:22:21.55#ibcon#read 3, iclass 7, count 0 2006.253.08:22:21.55#ibcon#about to read 4, iclass 7, count 0 2006.253.08:22:21.55#ibcon#read 4, iclass 7, count 0 2006.253.08:22:21.55#ibcon#about to read 5, iclass 7, count 0 2006.253.08:22:21.55#ibcon#read 5, iclass 7, count 0 2006.253.08:22:21.55#ibcon#about to read 6, iclass 7, count 0 2006.253.08:22:21.55#ibcon#read 6, iclass 7, count 0 2006.253.08:22:21.55#ibcon#end of sib2, iclass 7, count 0 2006.253.08:22:21.55#ibcon#*mode == 0, iclass 7, count 0 2006.253.08:22:21.55#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.253.08:22:21.55#ibcon#[28=FRQ=04,712.99\r\n] 2006.253.08:22:21.55#ibcon#*before write, iclass 7, count 0 2006.253.08:22:21.55#ibcon#enter sib2, iclass 7, count 0 2006.253.08:22:21.55#ibcon#flushed, iclass 7, count 0 2006.253.08:22:21.55#ibcon#about to write, iclass 7, count 0 2006.253.08:22:21.55#ibcon#wrote, iclass 7, count 0 2006.253.08:22:21.55#ibcon#about to read 3, iclass 7, count 0 2006.253.08:22:21.59#ibcon#read 3, iclass 7, count 0 2006.253.08:22:21.59#ibcon#about to read 4, iclass 7, count 0 2006.253.08:22:21.59#ibcon#read 4, iclass 7, count 0 2006.253.08:22:21.59#ibcon#about to read 5, iclass 7, count 0 2006.253.08:22:21.59#ibcon#read 5, iclass 7, count 0 2006.253.08:22:21.59#ibcon#about to read 6, iclass 7, count 0 2006.253.08:22:21.59#ibcon#read 6, iclass 7, count 0 2006.253.08:22:21.59#ibcon#end of sib2, iclass 7, count 0 2006.253.08:22:21.59#ibcon#*after write, iclass 7, count 0 2006.253.08:22:21.59#ibcon#*before return 0, iclass 7, count 0 2006.253.08:22:21.59#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.253.08:22:21.59#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.253.08:22:21.59#ibcon#about to clear, iclass 7 cls_cnt 0 2006.253.08:22:21.59#ibcon#cleared, iclass 7 cls_cnt 0 2006.253.08:22:21.59$vc4f8/vb=4,4 2006.253.08:22:21.59#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.253.08:22:21.59#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.253.08:22:21.59#ibcon#ireg 11 cls_cnt 2 2006.253.08:22:21.59#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.253.08:22:21.65#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.253.08:22:21.65#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.253.08:22:21.65#ibcon#enter wrdev, iclass 11, count 2 2006.253.08:22:21.65#ibcon#first serial, iclass 11, count 2 2006.253.08:22:21.65#ibcon#enter sib2, iclass 11, count 2 2006.253.08:22:21.65#ibcon#flushed, iclass 11, count 2 2006.253.08:22:21.65#ibcon#about to write, iclass 11, count 2 2006.253.08:22:21.65#ibcon#wrote, iclass 11, count 2 2006.253.08:22:21.65#ibcon#about to read 3, iclass 11, count 2 2006.253.08:22:21.67#ibcon#read 3, iclass 11, count 2 2006.253.08:22:21.67#ibcon#about to read 4, iclass 11, count 2 2006.253.08:22:21.67#ibcon#read 4, iclass 11, count 2 2006.253.08:22:21.67#ibcon#about to read 5, iclass 11, count 2 2006.253.08:22:21.67#ibcon#read 5, iclass 11, count 2 2006.253.08:22:21.67#ibcon#about to read 6, iclass 11, count 2 2006.253.08:22:21.67#ibcon#read 6, iclass 11, count 2 2006.253.08:22:21.67#ibcon#end of sib2, iclass 11, count 2 2006.253.08:22:21.67#ibcon#*mode == 0, iclass 11, count 2 2006.253.08:22:21.67#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.253.08:22:21.67#ibcon#[27=AT04-04\r\n] 2006.253.08:22:21.67#ibcon#*before write, iclass 11, count 2 2006.253.08:22:21.67#ibcon#enter sib2, iclass 11, count 2 2006.253.08:22:21.67#ibcon#flushed, iclass 11, count 2 2006.253.08:22:21.67#ibcon#about to write, iclass 11, count 2 2006.253.08:22:21.67#ibcon#wrote, iclass 11, count 2 2006.253.08:22:21.67#ibcon#about to read 3, iclass 11, count 2 2006.253.08:22:21.70#ibcon#read 3, iclass 11, count 2 2006.253.08:22:21.70#ibcon#about to read 4, iclass 11, count 2 2006.253.08:22:21.70#ibcon#read 4, iclass 11, count 2 2006.253.08:22:21.70#ibcon#about to read 5, iclass 11, count 2 2006.253.08:22:21.70#ibcon#read 5, iclass 11, count 2 2006.253.08:22:21.70#ibcon#about to read 6, iclass 11, count 2 2006.253.08:22:21.70#ibcon#read 6, iclass 11, count 2 2006.253.08:22:21.70#ibcon#end of sib2, iclass 11, count 2 2006.253.08:22:21.70#ibcon#*after write, iclass 11, count 2 2006.253.08:22:21.70#ibcon#*before return 0, iclass 11, count 2 2006.253.08:22:21.70#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.253.08:22:21.70#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.253.08:22:21.70#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.253.08:22:21.70#ibcon#ireg 7 cls_cnt 0 2006.253.08:22:21.70#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.253.08:22:21.82#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.253.08:22:21.82#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.253.08:22:21.82#ibcon#enter wrdev, iclass 11, count 0 2006.253.08:22:21.82#ibcon#first serial, iclass 11, count 0 2006.253.08:22:21.82#ibcon#enter sib2, iclass 11, count 0 2006.253.08:22:21.82#ibcon#flushed, iclass 11, count 0 2006.253.08:22:21.82#ibcon#about to write, iclass 11, count 0 2006.253.08:22:21.82#ibcon#wrote, iclass 11, count 0 2006.253.08:22:21.82#ibcon#about to read 3, iclass 11, count 0 2006.253.08:22:21.84#ibcon#read 3, iclass 11, count 0 2006.253.08:22:21.84#ibcon#about to read 4, iclass 11, count 0 2006.253.08:22:21.84#ibcon#read 4, iclass 11, count 0 2006.253.08:22:21.84#ibcon#about to read 5, iclass 11, count 0 2006.253.08:22:21.84#ibcon#read 5, iclass 11, count 0 2006.253.08:22:21.84#ibcon#about to read 6, iclass 11, count 0 2006.253.08:22:21.84#ibcon#read 6, iclass 11, count 0 2006.253.08:22:21.84#ibcon#end of sib2, iclass 11, count 0 2006.253.08:22:21.84#ibcon#*mode == 0, iclass 11, count 0 2006.253.08:22:21.84#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.253.08:22:21.84#ibcon#[27=USB\r\n] 2006.253.08:22:21.84#ibcon#*before write, iclass 11, count 0 2006.253.08:22:21.84#ibcon#enter sib2, iclass 11, count 0 2006.253.08:22:21.84#ibcon#flushed, iclass 11, count 0 2006.253.08:22:21.84#ibcon#about to write, iclass 11, count 0 2006.253.08:22:21.84#ibcon#wrote, iclass 11, count 0 2006.253.08:22:21.84#ibcon#about to read 3, iclass 11, count 0 2006.253.08:22:21.87#ibcon#read 3, iclass 11, count 0 2006.253.08:22:21.87#ibcon#about to read 4, iclass 11, count 0 2006.253.08:22:21.87#ibcon#read 4, iclass 11, count 0 2006.253.08:22:21.87#ibcon#about to read 5, iclass 11, count 0 2006.253.08:22:21.87#ibcon#read 5, iclass 11, count 0 2006.253.08:22:21.87#ibcon#about to read 6, iclass 11, count 0 2006.253.08:22:21.87#ibcon#read 6, iclass 11, count 0 2006.253.08:22:21.87#ibcon#end of sib2, iclass 11, count 0 2006.253.08:22:21.87#ibcon#*after write, iclass 11, count 0 2006.253.08:22:21.87#ibcon#*before return 0, iclass 11, count 0 2006.253.08:22:21.87#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.253.08:22:21.87#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.253.08:22:21.87#ibcon#about to clear, iclass 11 cls_cnt 0 2006.253.08:22:21.87#ibcon#cleared, iclass 11 cls_cnt 0 2006.253.08:22:21.87$vc4f8/vblo=5,744.99 2006.253.08:22:21.87#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.253.08:22:21.87#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.253.08:22:21.87#ibcon#ireg 17 cls_cnt 0 2006.253.08:22:21.87#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.253.08:22:21.87#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.253.08:22:21.87#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.253.08:22:21.87#ibcon#enter wrdev, iclass 13, count 0 2006.253.08:22:21.87#ibcon#first serial, iclass 13, count 0 2006.253.08:22:21.87#ibcon#enter sib2, iclass 13, count 0 2006.253.08:22:21.87#ibcon#flushed, iclass 13, count 0 2006.253.08:22:21.87#ibcon#about to write, iclass 13, count 0 2006.253.08:22:21.87#ibcon#wrote, iclass 13, count 0 2006.253.08:22:21.87#ibcon#about to read 3, iclass 13, count 0 2006.253.08:22:21.89#ibcon#read 3, iclass 13, count 0 2006.253.08:22:21.89#ibcon#about to read 4, iclass 13, count 0 2006.253.08:22:21.89#ibcon#read 4, iclass 13, count 0 2006.253.08:22:21.89#ibcon#about to read 5, iclass 13, count 0 2006.253.08:22:21.89#ibcon#read 5, iclass 13, count 0 2006.253.08:22:21.89#ibcon#about to read 6, iclass 13, count 0 2006.253.08:22:21.89#ibcon#read 6, iclass 13, count 0 2006.253.08:22:21.89#ibcon#end of sib2, iclass 13, count 0 2006.253.08:22:21.89#ibcon#*mode == 0, iclass 13, count 0 2006.253.08:22:21.89#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.253.08:22:21.89#ibcon#[28=FRQ=05,744.99\r\n] 2006.253.08:22:21.89#ibcon#*before write, iclass 13, count 0 2006.253.08:22:21.89#ibcon#enter sib2, iclass 13, count 0 2006.253.08:22:21.89#ibcon#flushed, iclass 13, count 0 2006.253.08:22:21.89#ibcon#about to write, iclass 13, count 0 2006.253.08:22:21.89#ibcon#wrote, iclass 13, count 0 2006.253.08:22:21.89#ibcon#about to read 3, iclass 13, count 0 2006.253.08:22:21.93#ibcon#read 3, iclass 13, count 0 2006.253.08:22:21.93#ibcon#about to read 4, iclass 13, count 0 2006.253.08:22:21.93#ibcon#read 4, iclass 13, count 0 2006.253.08:22:21.93#ibcon#about to read 5, iclass 13, count 0 2006.253.08:22:21.93#ibcon#read 5, iclass 13, count 0 2006.253.08:22:21.93#ibcon#about to read 6, iclass 13, count 0 2006.253.08:22:21.93#ibcon#read 6, iclass 13, count 0 2006.253.08:22:21.93#ibcon#end of sib2, iclass 13, count 0 2006.253.08:22:21.93#ibcon#*after write, iclass 13, count 0 2006.253.08:22:21.93#ibcon#*before return 0, iclass 13, count 0 2006.253.08:22:21.93#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.253.08:22:21.93#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.253.08:22:21.93#ibcon#about to clear, iclass 13 cls_cnt 0 2006.253.08:22:21.93#ibcon#cleared, iclass 13 cls_cnt 0 2006.253.08:22:21.93$vc4f8/vb=5,4 2006.253.08:22:21.93#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.253.08:22:21.93#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.253.08:22:21.93#ibcon#ireg 11 cls_cnt 2 2006.253.08:22:21.93#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.253.08:22:22.00#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.253.08:22:22.00#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.253.08:22:22.00#ibcon#enter wrdev, iclass 15, count 2 2006.253.08:22:22.00#ibcon#first serial, iclass 15, count 2 2006.253.08:22:22.00#ibcon#enter sib2, iclass 15, count 2 2006.253.08:22:22.00#ibcon#flushed, iclass 15, count 2 2006.253.08:22:22.00#ibcon#about to write, iclass 15, count 2 2006.253.08:22:22.00#ibcon#wrote, iclass 15, count 2 2006.253.08:22:22.00#ibcon#about to read 3, iclass 15, count 2 2006.253.08:22:22.01#ibcon#read 3, iclass 15, count 2 2006.253.08:22:22.01#ibcon#about to read 4, iclass 15, count 2 2006.253.08:22:22.01#ibcon#read 4, iclass 15, count 2 2006.253.08:22:22.01#ibcon#about to read 5, iclass 15, count 2 2006.253.08:22:22.01#ibcon#read 5, iclass 15, count 2 2006.253.08:22:22.01#ibcon#about to read 6, iclass 15, count 2 2006.253.08:22:22.01#ibcon#read 6, iclass 15, count 2 2006.253.08:22:22.01#ibcon#end of sib2, iclass 15, count 2 2006.253.08:22:22.01#ibcon#*mode == 0, iclass 15, count 2 2006.253.08:22:22.01#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.253.08:22:22.01#ibcon#[27=AT05-04\r\n] 2006.253.08:22:22.01#ibcon#*before write, iclass 15, count 2 2006.253.08:22:22.01#ibcon#enter sib2, iclass 15, count 2 2006.253.08:22:22.01#ibcon#flushed, iclass 15, count 2 2006.253.08:22:22.01#ibcon#about to write, iclass 15, count 2 2006.253.08:22:22.01#ibcon#wrote, iclass 15, count 2 2006.253.08:22:22.01#ibcon#about to read 3, iclass 15, count 2 2006.253.08:22:22.04#ibcon#read 3, iclass 15, count 2 2006.253.08:22:22.04#ibcon#about to read 4, iclass 15, count 2 2006.253.08:22:22.04#ibcon#read 4, iclass 15, count 2 2006.253.08:22:22.04#ibcon#about to read 5, iclass 15, count 2 2006.253.08:22:22.04#ibcon#read 5, iclass 15, count 2 2006.253.08:22:22.04#ibcon#about to read 6, iclass 15, count 2 2006.253.08:22:22.04#ibcon#read 6, iclass 15, count 2 2006.253.08:22:22.04#ibcon#end of sib2, iclass 15, count 2 2006.253.08:22:22.04#ibcon#*after write, iclass 15, count 2 2006.253.08:22:22.04#ibcon#*before return 0, iclass 15, count 2 2006.253.08:22:22.04#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.253.08:22:22.04#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.253.08:22:22.04#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.253.08:22:22.04#ibcon#ireg 7 cls_cnt 0 2006.253.08:22:22.04#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.253.08:22:22.16#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.253.08:22:22.16#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.253.08:22:22.16#ibcon#enter wrdev, iclass 15, count 0 2006.253.08:22:22.16#ibcon#first serial, iclass 15, count 0 2006.253.08:22:22.16#ibcon#enter sib2, iclass 15, count 0 2006.253.08:22:22.16#ibcon#flushed, iclass 15, count 0 2006.253.08:22:22.16#ibcon#about to write, iclass 15, count 0 2006.253.08:22:22.16#ibcon#wrote, iclass 15, count 0 2006.253.08:22:22.16#ibcon#about to read 3, iclass 15, count 0 2006.253.08:22:22.18#ibcon#read 3, iclass 15, count 0 2006.253.08:22:22.18#ibcon#about to read 4, iclass 15, count 0 2006.253.08:22:22.18#ibcon#read 4, iclass 15, count 0 2006.253.08:22:22.18#ibcon#about to read 5, iclass 15, count 0 2006.253.08:22:22.18#ibcon#read 5, iclass 15, count 0 2006.253.08:22:22.18#ibcon#about to read 6, iclass 15, count 0 2006.253.08:22:22.18#ibcon#read 6, iclass 15, count 0 2006.253.08:22:22.18#ibcon#end of sib2, iclass 15, count 0 2006.253.08:22:22.18#ibcon#*mode == 0, iclass 15, count 0 2006.253.08:22:22.18#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.253.08:22:22.18#ibcon#[27=USB\r\n] 2006.253.08:22:22.18#ibcon#*before write, iclass 15, count 0 2006.253.08:22:22.18#ibcon#enter sib2, iclass 15, count 0 2006.253.08:22:22.18#ibcon#flushed, iclass 15, count 0 2006.253.08:22:22.18#ibcon#about to write, iclass 15, count 0 2006.253.08:22:22.18#ibcon#wrote, iclass 15, count 0 2006.253.08:22:22.18#ibcon#about to read 3, iclass 15, count 0 2006.253.08:22:22.21#ibcon#read 3, iclass 15, count 0 2006.253.08:22:22.21#ibcon#about to read 4, iclass 15, count 0 2006.253.08:22:22.21#ibcon#read 4, iclass 15, count 0 2006.253.08:22:22.21#ibcon#about to read 5, iclass 15, count 0 2006.253.08:22:22.21#ibcon#read 5, iclass 15, count 0 2006.253.08:22:22.21#ibcon#about to read 6, iclass 15, count 0 2006.253.08:22:22.21#ibcon#read 6, iclass 15, count 0 2006.253.08:22:22.21#ibcon#end of sib2, iclass 15, count 0 2006.253.08:22:22.21#ibcon#*after write, iclass 15, count 0 2006.253.08:22:22.21#ibcon#*before return 0, iclass 15, count 0 2006.253.08:22:22.21#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.253.08:22:22.21#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.253.08:22:22.21#ibcon#about to clear, iclass 15 cls_cnt 0 2006.253.08:22:22.21#ibcon#cleared, iclass 15 cls_cnt 0 2006.253.08:22:22.21$vc4f8/vblo=6,752.99 2006.253.08:22:22.21#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.253.08:22:22.21#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.253.08:22:22.21#ibcon#ireg 17 cls_cnt 0 2006.253.08:22:22.21#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.253.08:22:22.21#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.253.08:22:22.21#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.253.08:22:22.21#ibcon#enter wrdev, iclass 17, count 0 2006.253.08:22:22.21#ibcon#first serial, iclass 17, count 0 2006.253.08:22:22.21#ibcon#enter sib2, iclass 17, count 0 2006.253.08:22:22.21#ibcon#flushed, iclass 17, count 0 2006.253.08:22:22.21#ibcon#about to write, iclass 17, count 0 2006.253.08:22:22.21#ibcon#wrote, iclass 17, count 0 2006.253.08:22:22.21#ibcon#about to read 3, iclass 17, count 0 2006.253.08:22:22.23#ibcon#read 3, iclass 17, count 0 2006.253.08:22:22.23#ibcon#about to read 4, iclass 17, count 0 2006.253.08:22:22.23#ibcon#read 4, iclass 17, count 0 2006.253.08:22:22.23#ibcon#about to read 5, iclass 17, count 0 2006.253.08:22:22.23#ibcon#read 5, iclass 17, count 0 2006.253.08:22:22.23#ibcon#about to read 6, iclass 17, count 0 2006.253.08:22:22.23#ibcon#read 6, iclass 17, count 0 2006.253.08:22:22.23#ibcon#end of sib2, iclass 17, count 0 2006.253.08:22:22.23#ibcon#*mode == 0, iclass 17, count 0 2006.253.08:22:22.23#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.253.08:22:22.23#ibcon#[28=FRQ=06,752.99\r\n] 2006.253.08:22:22.23#ibcon#*before write, iclass 17, count 0 2006.253.08:22:22.23#ibcon#enter sib2, iclass 17, count 0 2006.253.08:22:22.23#ibcon#flushed, iclass 17, count 0 2006.253.08:22:22.23#ibcon#about to write, iclass 17, count 0 2006.253.08:22:22.23#ibcon#wrote, iclass 17, count 0 2006.253.08:22:22.23#ibcon#about to read 3, iclass 17, count 0 2006.253.08:22:22.27#ibcon#read 3, iclass 17, count 0 2006.253.08:22:22.27#ibcon#about to read 4, iclass 17, count 0 2006.253.08:22:22.27#ibcon#read 4, iclass 17, count 0 2006.253.08:22:22.27#ibcon#about to read 5, iclass 17, count 0 2006.253.08:22:22.27#ibcon#read 5, iclass 17, count 0 2006.253.08:22:22.27#ibcon#about to read 6, iclass 17, count 0 2006.253.08:22:22.27#ibcon#read 6, iclass 17, count 0 2006.253.08:22:22.27#ibcon#end of sib2, iclass 17, count 0 2006.253.08:22:22.27#ibcon#*after write, iclass 17, count 0 2006.253.08:22:22.27#ibcon#*before return 0, iclass 17, count 0 2006.253.08:22:22.27#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.253.08:22:22.27#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.253.08:22:22.27#ibcon#about to clear, iclass 17 cls_cnt 0 2006.253.08:22:22.27#ibcon#cleared, iclass 17 cls_cnt 0 2006.253.08:22:22.27$vc4f8/vb=6,4 2006.253.08:22:22.27#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.253.08:22:22.27#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.253.08:22:22.27#ibcon#ireg 11 cls_cnt 2 2006.253.08:22:22.27#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.253.08:22:22.33#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.253.08:22:22.33#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.253.08:22:22.33#ibcon#enter wrdev, iclass 19, count 2 2006.253.08:22:22.33#ibcon#first serial, iclass 19, count 2 2006.253.08:22:22.33#ibcon#enter sib2, iclass 19, count 2 2006.253.08:22:22.33#ibcon#flushed, iclass 19, count 2 2006.253.08:22:22.33#ibcon#about to write, iclass 19, count 2 2006.253.08:22:22.33#ibcon#wrote, iclass 19, count 2 2006.253.08:22:22.33#ibcon#about to read 3, iclass 19, count 2 2006.253.08:22:22.35#ibcon#read 3, iclass 19, count 2 2006.253.08:22:22.35#ibcon#about to read 4, iclass 19, count 2 2006.253.08:22:22.35#ibcon#read 4, iclass 19, count 2 2006.253.08:22:22.35#ibcon#about to read 5, iclass 19, count 2 2006.253.08:22:22.35#ibcon#read 5, iclass 19, count 2 2006.253.08:22:22.35#ibcon#about to read 6, iclass 19, count 2 2006.253.08:22:22.35#ibcon#read 6, iclass 19, count 2 2006.253.08:22:22.35#ibcon#end of sib2, iclass 19, count 2 2006.253.08:22:22.35#ibcon#*mode == 0, iclass 19, count 2 2006.253.08:22:22.35#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.253.08:22:22.35#ibcon#[27=AT06-04\r\n] 2006.253.08:22:22.35#ibcon#*before write, iclass 19, count 2 2006.253.08:22:22.35#ibcon#enter sib2, iclass 19, count 2 2006.253.08:22:22.35#ibcon#flushed, iclass 19, count 2 2006.253.08:22:22.35#ibcon#about to write, iclass 19, count 2 2006.253.08:22:22.35#ibcon#wrote, iclass 19, count 2 2006.253.08:22:22.35#ibcon#about to read 3, iclass 19, count 2 2006.253.08:22:22.38#ibcon#read 3, iclass 19, count 2 2006.253.08:22:22.38#ibcon#about to read 4, iclass 19, count 2 2006.253.08:22:22.38#ibcon#read 4, iclass 19, count 2 2006.253.08:22:22.38#ibcon#about to read 5, iclass 19, count 2 2006.253.08:22:22.38#ibcon#read 5, iclass 19, count 2 2006.253.08:22:22.38#ibcon#about to read 6, iclass 19, count 2 2006.253.08:22:22.38#ibcon#read 6, iclass 19, count 2 2006.253.08:22:22.38#ibcon#end of sib2, iclass 19, count 2 2006.253.08:22:22.38#ibcon#*after write, iclass 19, count 2 2006.253.08:22:22.38#ibcon#*before return 0, iclass 19, count 2 2006.253.08:22:22.38#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.253.08:22:22.38#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.253.08:22:22.38#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.253.08:22:22.38#ibcon#ireg 7 cls_cnt 0 2006.253.08:22:22.38#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.253.08:22:22.51#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.253.08:22:22.51#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.253.08:22:22.51#ibcon#enter wrdev, iclass 19, count 0 2006.253.08:22:22.51#ibcon#first serial, iclass 19, count 0 2006.253.08:22:22.51#ibcon#enter sib2, iclass 19, count 0 2006.253.08:22:22.51#ibcon#flushed, iclass 19, count 0 2006.253.08:22:22.51#ibcon#about to write, iclass 19, count 0 2006.253.08:22:22.51#ibcon#wrote, iclass 19, count 0 2006.253.08:22:22.51#ibcon#about to read 3, iclass 19, count 0 2006.253.08:22:22.52#ibcon#read 3, iclass 19, count 0 2006.253.08:22:22.52#ibcon#about to read 4, iclass 19, count 0 2006.253.08:22:22.52#ibcon#read 4, iclass 19, count 0 2006.253.08:22:22.52#ibcon#about to read 5, iclass 19, count 0 2006.253.08:22:22.52#ibcon#read 5, iclass 19, count 0 2006.253.08:22:22.52#ibcon#about to read 6, iclass 19, count 0 2006.253.08:22:22.52#ibcon#read 6, iclass 19, count 0 2006.253.08:22:22.52#ibcon#end of sib2, iclass 19, count 0 2006.253.08:22:22.52#ibcon#*mode == 0, iclass 19, count 0 2006.253.08:22:22.52#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.253.08:22:22.52#ibcon#[27=USB\r\n] 2006.253.08:22:22.52#ibcon#*before write, iclass 19, count 0 2006.253.08:22:22.52#ibcon#enter sib2, iclass 19, count 0 2006.253.08:22:22.52#ibcon#flushed, iclass 19, count 0 2006.253.08:22:22.52#ibcon#about to write, iclass 19, count 0 2006.253.08:22:22.52#ibcon#wrote, iclass 19, count 0 2006.253.08:22:22.52#ibcon#about to read 3, iclass 19, count 0 2006.253.08:22:22.55#ibcon#read 3, iclass 19, count 0 2006.253.08:22:22.55#ibcon#about to read 4, iclass 19, count 0 2006.253.08:22:22.55#ibcon#read 4, iclass 19, count 0 2006.253.08:22:22.55#ibcon#about to read 5, iclass 19, count 0 2006.253.08:22:22.55#ibcon#read 5, iclass 19, count 0 2006.253.08:22:22.55#ibcon#about to read 6, iclass 19, count 0 2006.253.08:22:22.55#ibcon#read 6, iclass 19, count 0 2006.253.08:22:22.55#ibcon#end of sib2, iclass 19, count 0 2006.253.08:22:22.55#ibcon#*after write, iclass 19, count 0 2006.253.08:22:22.55#ibcon#*before return 0, iclass 19, count 0 2006.253.08:22:22.55#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.253.08:22:22.55#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.253.08:22:22.55#ibcon#about to clear, iclass 19 cls_cnt 0 2006.253.08:22:22.55#ibcon#cleared, iclass 19 cls_cnt 0 2006.253.08:22:22.55$vc4f8/vabw=wide 2006.253.08:22:22.55#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.253.08:22:22.55#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.253.08:22:22.55#ibcon#ireg 8 cls_cnt 0 2006.253.08:22:22.55#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.253.08:22:22.55#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.253.08:22:22.55#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.253.08:22:22.55#ibcon#enter wrdev, iclass 21, count 0 2006.253.08:22:22.55#ibcon#first serial, iclass 21, count 0 2006.253.08:22:22.55#ibcon#enter sib2, iclass 21, count 0 2006.253.08:22:22.55#ibcon#flushed, iclass 21, count 0 2006.253.08:22:22.55#ibcon#about to write, iclass 21, count 0 2006.253.08:22:22.55#ibcon#wrote, iclass 21, count 0 2006.253.08:22:22.55#ibcon#about to read 3, iclass 21, count 0 2006.253.08:22:22.58#ibcon#read 3, iclass 21, count 0 2006.253.08:22:22.58#ibcon#about to read 4, iclass 21, count 0 2006.253.08:22:22.58#ibcon#read 4, iclass 21, count 0 2006.253.08:22:22.58#ibcon#about to read 5, iclass 21, count 0 2006.253.08:22:22.58#ibcon#read 5, iclass 21, count 0 2006.253.08:22:22.58#ibcon#about to read 6, iclass 21, count 0 2006.253.08:22:22.58#ibcon#read 6, iclass 21, count 0 2006.253.08:22:22.58#ibcon#end of sib2, iclass 21, count 0 2006.253.08:22:22.58#ibcon#*mode == 0, iclass 21, count 0 2006.253.08:22:22.58#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.253.08:22:22.58#ibcon#[25=BW32\r\n] 2006.253.08:22:22.58#ibcon#*before write, iclass 21, count 0 2006.253.08:22:22.58#ibcon#enter sib2, iclass 21, count 0 2006.253.08:22:22.58#ibcon#flushed, iclass 21, count 0 2006.253.08:22:22.58#ibcon#about to write, iclass 21, count 0 2006.253.08:22:22.58#ibcon#wrote, iclass 21, count 0 2006.253.08:22:22.58#ibcon#about to read 3, iclass 21, count 0 2006.253.08:22:22.61#ibcon#read 3, iclass 21, count 0 2006.253.08:22:22.61#ibcon#about to read 4, iclass 21, count 0 2006.253.08:22:22.61#ibcon#read 4, iclass 21, count 0 2006.253.08:22:22.61#ibcon#about to read 5, iclass 21, count 0 2006.253.08:22:22.61#ibcon#read 5, iclass 21, count 0 2006.253.08:22:22.61#ibcon#about to read 6, iclass 21, count 0 2006.253.08:22:22.61#ibcon#read 6, iclass 21, count 0 2006.253.08:22:22.61#ibcon#end of sib2, iclass 21, count 0 2006.253.08:22:22.61#ibcon#*after write, iclass 21, count 0 2006.253.08:22:22.61#ibcon#*before return 0, iclass 21, count 0 2006.253.08:22:22.61#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.253.08:22:22.61#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.253.08:22:22.61#ibcon#about to clear, iclass 21 cls_cnt 0 2006.253.08:22:22.61#ibcon#cleared, iclass 21 cls_cnt 0 2006.253.08:22:22.61$vc4f8/vbbw=wide 2006.253.08:22:22.61#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.253.08:22:22.61#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.253.08:22:22.61#ibcon#ireg 8 cls_cnt 0 2006.253.08:22:22.61#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.253.08:22:22.68#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.253.08:22:22.68#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.253.08:22:22.68#ibcon#enter wrdev, iclass 23, count 0 2006.253.08:22:22.68#ibcon#first serial, iclass 23, count 0 2006.253.08:22:22.68#ibcon#enter sib2, iclass 23, count 0 2006.253.08:22:22.68#ibcon#flushed, iclass 23, count 0 2006.253.08:22:22.68#ibcon#about to write, iclass 23, count 0 2006.253.08:22:22.68#ibcon#wrote, iclass 23, count 0 2006.253.08:22:22.68#ibcon#about to read 3, iclass 23, count 0 2006.253.08:22:22.69#ibcon#read 3, iclass 23, count 0 2006.253.08:22:22.69#ibcon#about to read 4, iclass 23, count 0 2006.253.08:22:22.69#ibcon#read 4, iclass 23, count 0 2006.253.08:22:22.69#ibcon#about to read 5, iclass 23, count 0 2006.253.08:22:22.69#ibcon#read 5, iclass 23, count 0 2006.253.08:22:22.69#ibcon#about to read 6, iclass 23, count 0 2006.253.08:22:22.69#ibcon#read 6, iclass 23, count 0 2006.253.08:22:22.69#ibcon#end of sib2, iclass 23, count 0 2006.253.08:22:22.69#ibcon#*mode == 0, iclass 23, count 0 2006.253.08:22:22.69#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.253.08:22:22.69#ibcon#[27=BW32\r\n] 2006.253.08:22:22.69#ibcon#*before write, iclass 23, count 0 2006.253.08:22:22.69#ibcon#enter sib2, iclass 23, count 0 2006.253.08:22:22.69#ibcon#flushed, iclass 23, count 0 2006.253.08:22:22.69#ibcon#about to write, iclass 23, count 0 2006.253.08:22:22.69#ibcon#wrote, iclass 23, count 0 2006.253.08:22:22.69#ibcon#about to read 3, iclass 23, count 0 2006.253.08:22:22.72#ibcon#read 3, iclass 23, count 0 2006.253.08:22:22.72#ibcon#about to read 4, iclass 23, count 0 2006.253.08:22:22.72#ibcon#read 4, iclass 23, count 0 2006.253.08:22:22.72#ibcon#about to read 5, iclass 23, count 0 2006.253.08:22:22.72#ibcon#read 5, iclass 23, count 0 2006.253.08:22:22.72#ibcon#about to read 6, iclass 23, count 0 2006.253.08:22:22.72#ibcon#read 6, iclass 23, count 0 2006.253.08:22:22.72#ibcon#end of sib2, iclass 23, count 0 2006.253.08:22:22.72#ibcon#*after write, iclass 23, count 0 2006.253.08:22:22.72#ibcon#*before return 0, iclass 23, count 0 2006.253.08:22:22.72#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.253.08:22:22.72#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.253.08:22:22.72#ibcon#about to clear, iclass 23 cls_cnt 0 2006.253.08:22:22.72#ibcon#cleared, iclass 23 cls_cnt 0 2006.253.08:22:22.72$4f8m12a/ifd4f 2006.253.08:22:22.72$ifd4f/lo= 2006.253.08:22:22.73$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.253.08:22:22.73$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.253.08:22:22.73$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.253.08:22:22.73$ifd4f/patch= 2006.253.08:22:22.73$ifd4f/patch=lo1,a1,a2,a3,a4 2006.253.08:22:22.73$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.253.08:22:22.73$ifd4f/patch=lo3,a5,a6,a7,a8 2006.253.08:22:22.73$4f8m12a/"form=m,16.000,1:2 2006.253.08:22:22.73$4f8m12a/"tpicd 2006.253.08:22:22.73$4f8m12a/echo=off 2006.253.08:22:22.73$4f8m12a/xlog=off 2006.253.08:22:22.73:!2006.253.08:24:30 2006.253.08:22:53.14#trakl#Source acquired 2006.253.08:22:55.14#flagr#flagr/antenna,acquired 2006.253.08:24:30.01:preob 2006.253.08:24:31.14/onsource/TRACKING 2006.253.08:24:31.14:!2006.253.08:24:40 2006.253.08:24:40.00:data_valid=on 2006.253.08:24:40.00:midob 2006.253.08:24:40.14/onsource/TRACKING 2006.253.08:24:40.14/wx/30.73,1006.7,75 2006.253.08:24:40.24/cable/+6.3698E-03 2006.253.08:24:41.33/va/01,08,usb,yes,31,33 2006.253.08:24:41.33/va/02,07,usb,yes,31,33 2006.253.08:24:41.33/va/03,06,usb,yes,33,33 2006.253.08:24:41.33/va/04,07,usb,yes,32,35 2006.253.08:24:41.33/va/05,07,usb,yes,33,35 2006.253.08:24:41.33/va/06,07,usb,yes,29,29 2006.253.08:24:41.33/va/07,07,usb,yes,28,28 2006.253.08:24:41.33/va/08,07,usb,yes,31,30 2006.253.08:24:41.56/valo/01,532.99,yes,locked 2006.253.08:24:41.56/valo/02,572.99,yes,locked 2006.253.08:24:41.56/valo/03,672.99,yes,locked 2006.253.08:24:41.56/valo/04,832.99,yes,locked 2006.253.08:24:41.56/valo/05,652.99,yes,locked 2006.253.08:24:41.56/valo/06,772.99,yes,locked 2006.253.08:24:41.56/valo/07,832.99,yes,locked 2006.253.08:24:41.56/valo/08,852.99,yes,locked 2006.253.08:24:42.65/vb/01,04,usb,yes,30,29 2006.253.08:24:42.65/vb/02,05,usb,yes,28,30 2006.253.08:24:42.65/vb/03,04,usb,yes,29,32 2006.253.08:24:42.65/vb/04,04,usb,yes,29,30 2006.253.08:24:42.65/vb/05,04,usb,yes,28,32 2006.253.08:24:42.65/vb/06,04,usb,yes,29,32 2006.253.08:24:42.65/vb/07,04,usb,yes,31,31 2006.253.08:24:42.65/vb/08,04,usb,yes,28,32 2006.253.08:24:42.89/vblo/01,632.99,yes,locked 2006.253.08:24:42.89/vblo/02,640.99,yes,locked 2006.253.08:24:42.89/vblo/03,656.99,yes,locked 2006.253.08:24:42.89/vblo/04,712.99,yes,locked 2006.253.08:24:42.89/vblo/05,744.99,yes,locked 2006.253.08:24:42.89/vblo/06,752.99,yes,locked 2006.253.08:24:42.89/vblo/07,734.99,yes,locked 2006.253.08:24:42.89/vblo/08,744.99,yes,locked 2006.253.08:24:43.04/vabw/8 2006.253.08:24:43.19/vbbw/8 2006.253.08:24:43.28/xfe/off,on,14.5 2006.253.08:24:43.66/ifatt/23,28,28,28 2006.253.08:24:44.07/fmout-gps/S +4.71E-07 2006.253.08:24:44.12:!2006.253.08:25:40 2006.253.08:25:40.01:data_valid=off 2006.253.08:25:40.02:postob 2006.253.08:25:40.09/cable/+6.3680E-03 2006.253.08:25:40.09/wx/30.71,1006.7,75 2006.253.08:25:41.07/fmout-gps/S +4.71E-07 2006.253.08:25:41.08:scan_name=253-0826,k06253,70 2006.253.08:25:41.08:source=1219+044,122222.55,041315.8,2000.0,ccw 2006.253.08:25:42.14#flagr#flagr/antenna,new-source 2006.253.08:25:42.15:checkk5 2006.253.08:25:42.54/chk_autoobs//k5ts1/ autoobs is running! 2006.253.08:25:42.92/chk_autoobs//k5ts2/ autoobs is running! 2006.253.08:25:43.30/chk_autoobs//k5ts3/ autoobs is running! 2006.253.08:25:43.68/chk_autoobs//k5ts4/ autoobs is running! 2006.253.08:25:44.05/chk_obsdata//k5ts1/T2530824??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.253.08:25:44.42/chk_obsdata//k5ts2/T2530824??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.253.08:25:44.81/chk_obsdata//k5ts3/T2530824??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.253.08:25:45.19/chk_obsdata//k5ts4/T2530824??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.253.08:25:45.89/k5log//k5ts1_log_newline 2006.253.08:25:46.58/k5log//k5ts2_log_newline 2006.253.08:25:47.28/k5log//k5ts3_log_newline 2006.253.08:25:47.96/k5log//k5ts4_log_newline 2006.253.08:25:47.98/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.253.08:25:47.98:4f8m12a=3 2006.253.08:25:47.99$4f8m12a/echo=on 2006.253.08:25:47.99$4f8m12a/pcalon 2006.253.08:25:47.99$pcalon/"no phase cal control is implemented here 2006.253.08:25:47.99$4f8m12a/"tpicd=stop 2006.253.08:25:47.99$4f8m12a/vc4f8 2006.253.08:25:47.99$vc4f8/valo=1,532.99 2006.253.08:25:47.99#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.253.08:25:47.99#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.253.08:25:47.99#ibcon#ireg 17 cls_cnt 0 2006.253.08:25:47.99#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.253.08:25:47.99#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.253.08:25:47.99#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.253.08:25:47.99#ibcon#enter wrdev, iclass 38, count 0 2006.253.08:25:47.99#ibcon#first serial, iclass 38, count 0 2006.253.08:25:47.99#ibcon#enter sib2, iclass 38, count 0 2006.253.08:25:47.99#ibcon#flushed, iclass 38, count 0 2006.253.08:25:47.99#ibcon#about to write, iclass 38, count 0 2006.253.08:25:47.99#ibcon#wrote, iclass 38, count 0 2006.253.08:25:47.99#ibcon#about to read 3, iclass 38, count 0 2006.253.08:25:48.00#ibcon#read 3, iclass 38, count 0 2006.253.08:25:48.00#ibcon#about to read 4, iclass 38, count 0 2006.253.08:25:48.00#ibcon#read 4, iclass 38, count 0 2006.253.08:25:48.00#ibcon#about to read 5, iclass 38, count 0 2006.253.08:25:48.00#ibcon#read 5, iclass 38, count 0 2006.253.08:25:48.00#ibcon#about to read 6, iclass 38, count 0 2006.253.08:25:48.00#ibcon#read 6, iclass 38, count 0 2006.253.08:25:48.00#ibcon#end of sib2, iclass 38, count 0 2006.253.08:25:48.00#ibcon#*mode == 0, iclass 38, count 0 2006.253.08:25:48.00#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.253.08:25:48.00#ibcon#[26=FRQ=01,532.99\r\n] 2006.253.08:25:48.00#ibcon#*before write, iclass 38, count 0 2006.253.08:25:48.00#ibcon#enter sib2, iclass 38, count 0 2006.253.08:25:48.00#ibcon#flushed, iclass 38, count 0 2006.253.08:25:48.00#ibcon#about to write, iclass 38, count 0 2006.253.08:25:48.00#ibcon#wrote, iclass 38, count 0 2006.253.08:25:48.00#ibcon#about to read 3, iclass 38, count 0 2006.253.08:25:48.05#ibcon#read 3, iclass 38, count 0 2006.253.08:25:48.05#ibcon#about to read 4, iclass 38, count 0 2006.253.08:25:48.05#ibcon#read 4, iclass 38, count 0 2006.253.08:25:48.05#ibcon#about to read 5, iclass 38, count 0 2006.253.08:25:48.05#ibcon#read 5, iclass 38, count 0 2006.253.08:25:48.05#ibcon#about to read 6, iclass 38, count 0 2006.253.08:25:48.05#ibcon#read 6, iclass 38, count 0 2006.253.08:25:48.05#ibcon#end of sib2, iclass 38, count 0 2006.253.08:25:48.05#ibcon#*after write, iclass 38, count 0 2006.253.08:25:48.05#ibcon#*before return 0, iclass 38, count 0 2006.253.08:25:48.05#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.253.08:25:48.05#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.253.08:25:48.05#ibcon#about to clear, iclass 38 cls_cnt 0 2006.253.08:25:48.05#ibcon#cleared, iclass 38 cls_cnt 0 2006.253.08:25:48.05$vc4f8/va=1,8 2006.253.08:25:48.05#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.253.08:25:48.05#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.253.08:25:48.05#ibcon#ireg 11 cls_cnt 2 2006.253.08:25:48.05#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.253.08:25:48.05#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.253.08:25:48.05#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.253.08:25:48.05#ibcon#enter wrdev, iclass 40, count 2 2006.253.08:25:48.05#ibcon#first serial, iclass 40, count 2 2006.253.08:25:48.05#ibcon#enter sib2, iclass 40, count 2 2006.253.08:25:48.05#ibcon#flushed, iclass 40, count 2 2006.253.08:25:48.05#ibcon#about to write, iclass 40, count 2 2006.253.08:25:48.05#ibcon#wrote, iclass 40, count 2 2006.253.08:25:48.05#ibcon#about to read 3, iclass 40, count 2 2006.253.08:25:48.07#ibcon#read 3, iclass 40, count 2 2006.253.08:25:48.07#ibcon#about to read 4, iclass 40, count 2 2006.253.08:25:48.07#ibcon#read 4, iclass 40, count 2 2006.253.08:25:48.07#ibcon#about to read 5, iclass 40, count 2 2006.253.08:25:48.07#ibcon#read 5, iclass 40, count 2 2006.253.08:25:48.07#ibcon#about to read 6, iclass 40, count 2 2006.253.08:25:48.07#ibcon#read 6, iclass 40, count 2 2006.253.08:25:48.07#ibcon#end of sib2, iclass 40, count 2 2006.253.08:25:48.07#ibcon#*mode == 0, iclass 40, count 2 2006.253.08:25:48.07#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.253.08:25:48.07#ibcon#[25=AT01-08\r\n] 2006.253.08:25:48.07#ibcon#*before write, iclass 40, count 2 2006.253.08:25:48.07#ibcon#enter sib2, iclass 40, count 2 2006.253.08:25:48.07#ibcon#flushed, iclass 40, count 2 2006.253.08:25:48.07#ibcon#about to write, iclass 40, count 2 2006.253.08:25:48.07#ibcon#wrote, iclass 40, count 2 2006.253.08:25:48.07#ibcon#about to read 3, iclass 40, count 2 2006.253.08:25:48.11#ibcon#read 3, iclass 40, count 2 2006.253.08:25:48.11#ibcon#about to read 4, iclass 40, count 2 2006.253.08:25:48.11#ibcon#read 4, iclass 40, count 2 2006.253.08:25:48.11#ibcon#about to read 5, iclass 40, count 2 2006.253.08:25:48.11#ibcon#read 5, iclass 40, count 2 2006.253.08:25:48.11#ibcon#about to read 6, iclass 40, count 2 2006.253.08:25:48.11#ibcon#read 6, iclass 40, count 2 2006.253.08:25:48.11#ibcon#end of sib2, iclass 40, count 2 2006.253.08:25:48.11#ibcon#*after write, iclass 40, count 2 2006.253.08:25:48.11#ibcon#*before return 0, iclass 40, count 2 2006.253.08:25:48.11#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.253.08:25:48.11#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.253.08:25:48.11#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.253.08:25:48.11#ibcon#ireg 7 cls_cnt 0 2006.253.08:25:48.11#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.253.08:25:48.22#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.253.08:25:48.22#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.253.08:25:48.22#ibcon#enter wrdev, iclass 40, count 0 2006.253.08:25:48.22#ibcon#first serial, iclass 40, count 0 2006.253.08:25:48.22#ibcon#enter sib2, iclass 40, count 0 2006.253.08:25:48.22#ibcon#flushed, iclass 40, count 0 2006.253.08:25:48.22#ibcon#about to write, iclass 40, count 0 2006.253.08:25:48.22#ibcon#wrote, iclass 40, count 0 2006.253.08:25:48.22#ibcon#about to read 3, iclass 40, count 0 2006.253.08:25:48.24#ibcon#read 3, iclass 40, count 0 2006.253.08:25:48.24#ibcon#about to read 4, iclass 40, count 0 2006.253.08:25:48.24#ibcon#read 4, iclass 40, count 0 2006.253.08:25:48.24#ibcon#about to read 5, iclass 40, count 0 2006.253.08:25:48.24#ibcon#read 5, iclass 40, count 0 2006.253.08:25:48.24#ibcon#about to read 6, iclass 40, count 0 2006.253.08:25:48.24#ibcon#read 6, iclass 40, count 0 2006.253.08:25:48.24#ibcon#end of sib2, iclass 40, count 0 2006.253.08:25:48.24#ibcon#*mode == 0, iclass 40, count 0 2006.253.08:25:48.24#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.253.08:25:48.24#ibcon#[25=USB\r\n] 2006.253.08:25:48.24#ibcon#*before write, iclass 40, count 0 2006.253.08:25:48.24#ibcon#enter sib2, iclass 40, count 0 2006.253.08:25:48.24#ibcon#flushed, iclass 40, count 0 2006.253.08:25:48.24#ibcon#about to write, iclass 40, count 0 2006.253.08:25:48.24#ibcon#wrote, iclass 40, count 0 2006.253.08:25:48.24#ibcon#about to read 3, iclass 40, count 0 2006.253.08:25:48.27#ibcon#read 3, iclass 40, count 0 2006.253.08:25:48.27#ibcon#about to read 4, iclass 40, count 0 2006.253.08:25:48.27#ibcon#read 4, iclass 40, count 0 2006.253.08:25:48.27#ibcon#about to read 5, iclass 40, count 0 2006.253.08:25:48.27#ibcon#read 5, iclass 40, count 0 2006.253.08:25:48.27#ibcon#about to read 6, iclass 40, count 0 2006.253.08:25:48.27#ibcon#read 6, iclass 40, count 0 2006.253.08:25:48.27#ibcon#end of sib2, iclass 40, count 0 2006.253.08:25:48.27#ibcon#*after write, iclass 40, count 0 2006.253.08:25:48.27#ibcon#*before return 0, iclass 40, count 0 2006.253.08:25:48.27#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.253.08:25:48.27#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.253.08:25:48.27#ibcon#about to clear, iclass 40 cls_cnt 0 2006.253.08:25:48.27#ibcon#cleared, iclass 40 cls_cnt 0 2006.253.08:25:48.27$vc4f8/valo=2,572.99 2006.253.08:25:48.27#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.253.08:25:48.27#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.253.08:25:48.27#ibcon#ireg 17 cls_cnt 0 2006.253.08:25:48.27#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.253.08:25:48.27#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.253.08:25:48.27#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.253.08:25:48.27#ibcon#enter wrdev, iclass 4, count 0 2006.253.08:25:48.27#ibcon#first serial, iclass 4, count 0 2006.253.08:25:48.27#ibcon#enter sib2, iclass 4, count 0 2006.253.08:25:48.27#ibcon#flushed, iclass 4, count 0 2006.253.08:25:48.27#ibcon#about to write, iclass 4, count 0 2006.253.08:25:48.27#ibcon#wrote, iclass 4, count 0 2006.253.08:25:48.27#ibcon#about to read 3, iclass 4, count 0 2006.253.08:25:48.30#ibcon#read 3, iclass 4, count 0 2006.253.08:25:48.30#ibcon#about to read 4, iclass 4, count 0 2006.253.08:25:48.30#ibcon#read 4, iclass 4, count 0 2006.253.08:25:48.30#ibcon#about to read 5, iclass 4, count 0 2006.253.08:25:48.30#ibcon#read 5, iclass 4, count 0 2006.253.08:25:48.30#ibcon#about to read 6, iclass 4, count 0 2006.253.08:25:48.30#ibcon#read 6, iclass 4, count 0 2006.253.08:25:48.30#ibcon#end of sib2, iclass 4, count 0 2006.253.08:25:48.30#ibcon#*mode == 0, iclass 4, count 0 2006.253.08:25:48.30#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.253.08:25:48.30#ibcon#[26=FRQ=02,572.99\r\n] 2006.253.08:25:48.30#ibcon#*before write, iclass 4, count 0 2006.253.08:25:48.30#ibcon#enter sib2, iclass 4, count 0 2006.253.08:25:48.30#ibcon#flushed, iclass 4, count 0 2006.253.08:25:48.30#ibcon#about to write, iclass 4, count 0 2006.253.08:25:48.30#ibcon#wrote, iclass 4, count 0 2006.253.08:25:48.30#ibcon#about to read 3, iclass 4, count 0 2006.253.08:25:48.34#ibcon#read 3, iclass 4, count 0 2006.253.08:25:48.34#ibcon#about to read 4, iclass 4, count 0 2006.253.08:25:48.34#ibcon#read 4, iclass 4, count 0 2006.253.08:25:48.34#ibcon#about to read 5, iclass 4, count 0 2006.253.08:25:48.34#ibcon#read 5, iclass 4, count 0 2006.253.08:25:48.34#ibcon#about to read 6, iclass 4, count 0 2006.253.08:25:48.34#ibcon#read 6, iclass 4, count 0 2006.253.08:25:48.34#ibcon#end of sib2, iclass 4, count 0 2006.253.08:25:48.34#ibcon#*after write, iclass 4, count 0 2006.253.08:25:48.34#ibcon#*before return 0, iclass 4, count 0 2006.253.08:25:48.34#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.253.08:25:48.34#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.253.08:25:48.34#ibcon#about to clear, iclass 4 cls_cnt 0 2006.253.08:25:48.34#ibcon#cleared, iclass 4 cls_cnt 0 2006.253.08:25:48.34$vc4f8/va=2,7 2006.253.08:25:48.34#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.253.08:25:48.34#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.253.08:25:48.34#ibcon#ireg 11 cls_cnt 2 2006.253.08:25:48.34#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.253.08:25:48.40#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.253.08:25:48.40#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.253.08:25:48.40#ibcon#enter wrdev, iclass 6, count 2 2006.253.08:25:48.40#ibcon#first serial, iclass 6, count 2 2006.253.08:25:48.40#ibcon#enter sib2, iclass 6, count 2 2006.253.08:25:48.40#ibcon#flushed, iclass 6, count 2 2006.253.08:25:48.40#ibcon#about to write, iclass 6, count 2 2006.253.08:25:48.40#ibcon#wrote, iclass 6, count 2 2006.253.08:25:48.40#ibcon#about to read 3, iclass 6, count 2 2006.253.08:25:48.41#ibcon#read 3, iclass 6, count 2 2006.253.08:25:48.41#ibcon#about to read 4, iclass 6, count 2 2006.253.08:25:48.41#ibcon#read 4, iclass 6, count 2 2006.253.08:25:48.41#ibcon#about to read 5, iclass 6, count 2 2006.253.08:25:48.41#ibcon#read 5, iclass 6, count 2 2006.253.08:25:48.41#ibcon#about to read 6, iclass 6, count 2 2006.253.08:25:48.41#ibcon#read 6, iclass 6, count 2 2006.253.08:25:48.41#ibcon#end of sib2, iclass 6, count 2 2006.253.08:25:48.41#ibcon#*mode == 0, iclass 6, count 2 2006.253.08:25:48.41#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.253.08:25:48.41#ibcon#[25=AT02-07\r\n] 2006.253.08:25:48.41#ibcon#*before write, iclass 6, count 2 2006.253.08:25:48.41#ibcon#enter sib2, iclass 6, count 2 2006.253.08:25:48.41#ibcon#flushed, iclass 6, count 2 2006.253.08:25:48.41#ibcon#about to write, iclass 6, count 2 2006.253.08:25:48.41#ibcon#wrote, iclass 6, count 2 2006.253.08:25:48.41#ibcon#about to read 3, iclass 6, count 2 2006.253.08:25:48.44#ibcon#read 3, iclass 6, count 2 2006.253.08:25:48.44#ibcon#about to read 4, iclass 6, count 2 2006.253.08:25:48.44#ibcon#read 4, iclass 6, count 2 2006.253.08:25:48.44#ibcon#about to read 5, iclass 6, count 2 2006.253.08:25:48.44#ibcon#read 5, iclass 6, count 2 2006.253.08:25:48.44#ibcon#about to read 6, iclass 6, count 2 2006.253.08:25:48.44#ibcon#read 6, iclass 6, count 2 2006.253.08:25:48.44#ibcon#end of sib2, iclass 6, count 2 2006.253.08:25:48.44#ibcon#*after write, iclass 6, count 2 2006.253.08:25:48.44#ibcon#*before return 0, iclass 6, count 2 2006.253.08:25:48.44#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.253.08:25:48.44#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.253.08:25:48.44#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.253.08:25:48.44#ibcon#ireg 7 cls_cnt 0 2006.253.08:25:48.44#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.253.08:25:48.56#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.253.08:25:48.56#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.253.08:25:48.56#ibcon#enter wrdev, iclass 6, count 0 2006.253.08:25:48.56#ibcon#first serial, iclass 6, count 0 2006.253.08:25:48.56#ibcon#enter sib2, iclass 6, count 0 2006.253.08:25:48.56#ibcon#flushed, iclass 6, count 0 2006.253.08:25:48.56#ibcon#about to write, iclass 6, count 0 2006.253.08:25:48.56#ibcon#wrote, iclass 6, count 0 2006.253.08:25:48.56#ibcon#about to read 3, iclass 6, count 0 2006.253.08:25:48.58#ibcon#read 3, iclass 6, count 0 2006.253.08:25:48.58#ibcon#about to read 4, iclass 6, count 0 2006.253.08:25:48.58#ibcon#read 4, iclass 6, count 0 2006.253.08:25:48.58#ibcon#about to read 5, iclass 6, count 0 2006.253.08:25:48.58#ibcon#read 5, iclass 6, count 0 2006.253.08:25:48.58#ibcon#about to read 6, iclass 6, count 0 2006.253.08:25:48.58#ibcon#read 6, iclass 6, count 0 2006.253.08:25:48.58#ibcon#end of sib2, iclass 6, count 0 2006.253.08:25:48.58#ibcon#*mode == 0, iclass 6, count 0 2006.253.08:25:48.58#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.253.08:25:48.58#ibcon#[25=USB\r\n] 2006.253.08:25:48.58#ibcon#*before write, iclass 6, count 0 2006.253.08:25:48.58#ibcon#enter sib2, iclass 6, count 0 2006.253.08:25:48.58#ibcon#flushed, iclass 6, count 0 2006.253.08:25:48.58#ibcon#about to write, iclass 6, count 0 2006.253.08:25:48.58#ibcon#wrote, iclass 6, count 0 2006.253.08:25:48.58#ibcon#about to read 3, iclass 6, count 0 2006.253.08:25:48.61#ibcon#read 3, iclass 6, count 0 2006.253.08:25:48.61#ibcon#about to read 4, iclass 6, count 0 2006.253.08:25:48.61#ibcon#read 4, iclass 6, count 0 2006.253.08:25:48.61#ibcon#about to read 5, iclass 6, count 0 2006.253.08:25:48.61#ibcon#read 5, iclass 6, count 0 2006.253.08:25:48.61#ibcon#about to read 6, iclass 6, count 0 2006.253.08:25:48.61#ibcon#read 6, iclass 6, count 0 2006.253.08:25:48.61#ibcon#end of sib2, iclass 6, count 0 2006.253.08:25:48.61#ibcon#*after write, iclass 6, count 0 2006.253.08:25:48.61#ibcon#*before return 0, iclass 6, count 0 2006.253.08:25:48.61#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.253.08:25:48.61#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.253.08:25:48.61#ibcon#about to clear, iclass 6 cls_cnt 0 2006.253.08:25:48.61#ibcon#cleared, iclass 6 cls_cnt 0 2006.253.08:25:48.61$vc4f8/valo=3,672.99 2006.253.08:25:48.61#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.253.08:25:48.61#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.253.08:25:48.61#ibcon#ireg 17 cls_cnt 0 2006.253.08:25:48.61#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.253.08:25:48.61#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.253.08:25:48.61#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.253.08:25:48.61#ibcon#enter wrdev, iclass 10, count 0 2006.253.08:25:48.61#ibcon#first serial, iclass 10, count 0 2006.253.08:25:48.61#ibcon#enter sib2, iclass 10, count 0 2006.253.08:25:48.61#ibcon#flushed, iclass 10, count 0 2006.253.08:25:48.61#ibcon#about to write, iclass 10, count 0 2006.253.08:25:48.61#ibcon#wrote, iclass 10, count 0 2006.253.08:25:48.61#ibcon#about to read 3, iclass 10, count 0 2006.253.08:25:48.63#ibcon#read 3, iclass 10, count 0 2006.253.08:25:48.63#ibcon#about to read 4, iclass 10, count 0 2006.253.08:25:48.63#ibcon#read 4, iclass 10, count 0 2006.253.08:25:48.63#ibcon#about to read 5, iclass 10, count 0 2006.253.08:25:48.63#ibcon#read 5, iclass 10, count 0 2006.253.08:25:48.63#ibcon#about to read 6, iclass 10, count 0 2006.253.08:25:48.63#ibcon#read 6, iclass 10, count 0 2006.253.08:25:48.63#ibcon#end of sib2, iclass 10, count 0 2006.253.08:25:48.63#ibcon#*mode == 0, iclass 10, count 0 2006.253.08:25:48.63#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.253.08:25:48.63#ibcon#[26=FRQ=03,672.99\r\n] 2006.253.08:25:48.63#ibcon#*before write, iclass 10, count 0 2006.253.08:25:48.63#ibcon#enter sib2, iclass 10, count 0 2006.253.08:25:48.63#ibcon#flushed, iclass 10, count 0 2006.253.08:25:48.63#ibcon#about to write, iclass 10, count 0 2006.253.08:25:48.63#ibcon#wrote, iclass 10, count 0 2006.253.08:25:48.63#ibcon#about to read 3, iclass 10, count 0 2006.253.08:25:48.67#ibcon#read 3, iclass 10, count 0 2006.253.08:25:48.67#ibcon#about to read 4, iclass 10, count 0 2006.253.08:25:48.67#ibcon#read 4, iclass 10, count 0 2006.253.08:25:48.67#ibcon#about to read 5, iclass 10, count 0 2006.253.08:25:48.67#ibcon#read 5, iclass 10, count 0 2006.253.08:25:48.67#ibcon#about to read 6, iclass 10, count 0 2006.253.08:25:48.67#ibcon#read 6, iclass 10, count 0 2006.253.08:25:48.67#ibcon#end of sib2, iclass 10, count 0 2006.253.08:25:48.67#ibcon#*after write, iclass 10, count 0 2006.253.08:25:48.67#ibcon#*before return 0, iclass 10, count 0 2006.253.08:25:48.67#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.253.08:25:48.67#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.253.08:25:48.67#ibcon#about to clear, iclass 10 cls_cnt 0 2006.253.08:25:48.67#ibcon#cleared, iclass 10 cls_cnt 0 2006.253.08:25:48.67$vc4f8/va=3,6 2006.253.08:25:48.67#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.253.08:25:48.67#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.253.08:25:48.67#ibcon#ireg 11 cls_cnt 2 2006.253.08:25:48.67#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.253.08:25:48.74#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.253.08:25:48.74#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.253.08:25:48.74#ibcon#enter wrdev, iclass 12, count 2 2006.253.08:25:48.74#ibcon#first serial, iclass 12, count 2 2006.253.08:25:48.74#ibcon#enter sib2, iclass 12, count 2 2006.253.08:25:48.74#ibcon#flushed, iclass 12, count 2 2006.253.08:25:48.74#ibcon#about to write, iclass 12, count 2 2006.253.08:25:48.74#ibcon#wrote, iclass 12, count 2 2006.253.08:25:48.74#ibcon#about to read 3, iclass 12, count 2 2006.253.08:25:48.75#ibcon#read 3, iclass 12, count 2 2006.253.08:25:48.75#ibcon#about to read 4, iclass 12, count 2 2006.253.08:25:48.75#ibcon#read 4, iclass 12, count 2 2006.253.08:25:48.75#ibcon#about to read 5, iclass 12, count 2 2006.253.08:25:48.75#ibcon#read 5, iclass 12, count 2 2006.253.08:25:48.75#ibcon#about to read 6, iclass 12, count 2 2006.253.08:25:48.75#ibcon#read 6, iclass 12, count 2 2006.253.08:25:48.75#ibcon#end of sib2, iclass 12, count 2 2006.253.08:25:48.75#ibcon#*mode == 0, iclass 12, count 2 2006.253.08:25:48.75#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.253.08:25:48.75#ibcon#[25=AT03-06\r\n] 2006.253.08:25:48.75#ibcon#*before write, iclass 12, count 2 2006.253.08:25:48.75#ibcon#enter sib2, iclass 12, count 2 2006.253.08:25:48.75#ibcon#flushed, iclass 12, count 2 2006.253.08:25:48.75#ibcon#about to write, iclass 12, count 2 2006.253.08:25:48.75#ibcon#wrote, iclass 12, count 2 2006.253.08:25:48.75#ibcon#about to read 3, iclass 12, count 2 2006.253.08:25:48.78#ibcon#read 3, iclass 12, count 2 2006.253.08:25:48.78#ibcon#about to read 4, iclass 12, count 2 2006.253.08:25:48.78#ibcon#read 4, iclass 12, count 2 2006.253.08:25:48.78#ibcon#about to read 5, iclass 12, count 2 2006.253.08:25:48.78#ibcon#read 5, iclass 12, count 2 2006.253.08:25:48.78#ibcon#about to read 6, iclass 12, count 2 2006.253.08:25:48.78#ibcon#read 6, iclass 12, count 2 2006.253.08:25:48.78#ibcon#end of sib2, iclass 12, count 2 2006.253.08:25:48.78#ibcon#*after write, iclass 12, count 2 2006.253.08:25:48.78#ibcon#*before return 0, iclass 12, count 2 2006.253.08:25:48.78#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.253.08:25:48.78#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.253.08:25:48.78#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.253.08:25:48.78#ibcon#ireg 7 cls_cnt 0 2006.253.08:25:48.78#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.253.08:25:48.90#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.253.08:25:48.90#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.253.08:25:48.90#ibcon#enter wrdev, iclass 12, count 0 2006.253.08:25:48.90#ibcon#first serial, iclass 12, count 0 2006.253.08:25:48.90#ibcon#enter sib2, iclass 12, count 0 2006.253.08:25:48.90#ibcon#flushed, iclass 12, count 0 2006.253.08:25:48.90#ibcon#about to write, iclass 12, count 0 2006.253.08:25:48.90#ibcon#wrote, iclass 12, count 0 2006.253.08:25:48.90#ibcon#about to read 3, iclass 12, count 0 2006.253.08:25:48.92#ibcon#read 3, iclass 12, count 0 2006.253.08:25:48.92#ibcon#about to read 4, iclass 12, count 0 2006.253.08:25:48.92#ibcon#read 4, iclass 12, count 0 2006.253.08:25:48.92#ibcon#about to read 5, iclass 12, count 0 2006.253.08:25:48.92#ibcon#read 5, iclass 12, count 0 2006.253.08:25:48.92#ibcon#about to read 6, iclass 12, count 0 2006.253.08:25:48.92#ibcon#read 6, iclass 12, count 0 2006.253.08:25:48.92#ibcon#end of sib2, iclass 12, count 0 2006.253.08:25:48.92#ibcon#*mode == 0, iclass 12, count 0 2006.253.08:25:48.92#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.253.08:25:48.92#ibcon#[25=USB\r\n] 2006.253.08:25:48.92#ibcon#*before write, iclass 12, count 0 2006.253.08:25:48.92#ibcon#enter sib2, iclass 12, count 0 2006.253.08:25:48.92#ibcon#flushed, iclass 12, count 0 2006.253.08:25:48.92#ibcon#about to write, iclass 12, count 0 2006.253.08:25:48.92#ibcon#wrote, iclass 12, count 0 2006.253.08:25:48.92#ibcon#about to read 3, iclass 12, count 0 2006.253.08:25:48.95#ibcon#read 3, iclass 12, count 0 2006.253.08:25:48.95#ibcon#about to read 4, iclass 12, count 0 2006.253.08:25:48.95#ibcon#read 4, iclass 12, count 0 2006.253.08:25:48.95#ibcon#about to read 5, iclass 12, count 0 2006.253.08:25:48.95#ibcon#read 5, iclass 12, count 0 2006.253.08:25:48.95#ibcon#about to read 6, iclass 12, count 0 2006.253.08:25:48.95#ibcon#read 6, iclass 12, count 0 2006.253.08:25:48.95#ibcon#end of sib2, iclass 12, count 0 2006.253.08:25:48.95#ibcon#*after write, iclass 12, count 0 2006.253.08:25:48.95#ibcon#*before return 0, iclass 12, count 0 2006.253.08:25:48.95#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.253.08:25:48.95#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.253.08:25:48.95#ibcon#about to clear, iclass 12 cls_cnt 0 2006.253.08:25:48.95#ibcon#cleared, iclass 12 cls_cnt 0 2006.253.08:25:48.95$vc4f8/valo=4,832.99 2006.253.08:25:48.95#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.253.08:25:48.95#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.253.08:25:48.95#ibcon#ireg 17 cls_cnt 0 2006.253.08:25:48.95#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.253.08:25:48.95#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.253.08:25:48.95#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.253.08:25:48.95#ibcon#enter wrdev, iclass 14, count 0 2006.253.08:25:48.95#ibcon#first serial, iclass 14, count 0 2006.253.08:25:48.95#ibcon#enter sib2, iclass 14, count 0 2006.253.08:25:48.95#ibcon#flushed, iclass 14, count 0 2006.253.08:25:48.95#ibcon#about to write, iclass 14, count 0 2006.253.08:25:48.95#ibcon#wrote, iclass 14, count 0 2006.253.08:25:48.95#ibcon#about to read 3, iclass 14, count 0 2006.253.08:25:48.97#ibcon#read 3, iclass 14, count 0 2006.253.08:25:48.97#ibcon#about to read 4, iclass 14, count 0 2006.253.08:25:48.97#ibcon#read 4, iclass 14, count 0 2006.253.08:25:48.97#ibcon#about to read 5, iclass 14, count 0 2006.253.08:25:48.97#ibcon#read 5, iclass 14, count 0 2006.253.08:25:48.97#ibcon#about to read 6, iclass 14, count 0 2006.253.08:25:48.97#ibcon#read 6, iclass 14, count 0 2006.253.08:25:48.97#ibcon#end of sib2, iclass 14, count 0 2006.253.08:25:48.97#ibcon#*mode == 0, iclass 14, count 0 2006.253.08:25:48.97#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.253.08:25:48.97#ibcon#[26=FRQ=04,832.99\r\n] 2006.253.08:25:48.97#ibcon#*before write, iclass 14, count 0 2006.253.08:25:48.97#ibcon#enter sib2, iclass 14, count 0 2006.253.08:25:48.97#ibcon#flushed, iclass 14, count 0 2006.253.08:25:48.97#ibcon#about to write, iclass 14, count 0 2006.253.08:25:48.97#ibcon#wrote, iclass 14, count 0 2006.253.08:25:48.97#ibcon#about to read 3, iclass 14, count 0 2006.253.08:25:49.01#ibcon#read 3, iclass 14, count 0 2006.253.08:25:49.01#ibcon#about to read 4, iclass 14, count 0 2006.253.08:25:49.01#ibcon#read 4, iclass 14, count 0 2006.253.08:25:49.01#ibcon#about to read 5, iclass 14, count 0 2006.253.08:25:49.01#ibcon#read 5, iclass 14, count 0 2006.253.08:25:49.01#ibcon#about to read 6, iclass 14, count 0 2006.253.08:25:49.01#ibcon#read 6, iclass 14, count 0 2006.253.08:25:49.01#ibcon#end of sib2, iclass 14, count 0 2006.253.08:25:49.01#ibcon#*after write, iclass 14, count 0 2006.253.08:25:49.01#ibcon#*before return 0, iclass 14, count 0 2006.253.08:25:49.01#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.253.08:25:49.01#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.253.08:25:49.01#ibcon#about to clear, iclass 14 cls_cnt 0 2006.253.08:25:49.01#ibcon#cleared, iclass 14 cls_cnt 0 2006.253.08:25:49.01$vc4f8/va=4,7 2006.253.08:25:49.01#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.253.08:25:49.01#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.253.08:25:49.01#ibcon#ireg 11 cls_cnt 2 2006.253.08:25:49.01#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.253.08:25:49.07#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.253.08:25:49.07#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.253.08:25:49.07#ibcon#enter wrdev, iclass 16, count 2 2006.253.08:25:49.07#ibcon#first serial, iclass 16, count 2 2006.253.08:25:49.07#ibcon#enter sib2, iclass 16, count 2 2006.253.08:25:49.07#ibcon#flushed, iclass 16, count 2 2006.253.08:25:49.07#ibcon#about to write, iclass 16, count 2 2006.253.08:25:49.07#ibcon#wrote, iclass 16, count 2 2006.253.08:25:49.07#ibcon#about to read 3, iclass 16, count 2 2006.253.08:25:49.09#ibcon#read 3, iclass 16, count 2 2006.253.08:25:49.09#ibcon#about to read 4, iclass 16, count 2 2006.253.08:25:49.09#ibcon#read 4, iclass 16, count 2 2006.253.08:25:49.09#ibcon#about to read 5, iclass 16, count 2 2006.253.08:25:49.09#ibcon#read 5, iclass 16, count 2 2006.253.08:25:49.09#ibcon#about to read 6, iclass 16, count 2 2006.253.08:25:49.09#ibcon#read 6, iclass 16, count 2 2006.253.08:25:49.09#ibcon#end of sib2, iclass 16, count 2 2006.253.08:25:49.09#ibcon#*mode == 0, iclass 16, count 2 2006.253.08:25:49.09#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.253.08:25:49.09#ibcon#[25=AT04-07\r\n] 2006.253.08:25:49.09#ibcon#*before write, iclass 16, count 2 2006.253.08:25:49.09#ibcon#enter sib2, iclass 16, count 2 2006.253.08:25:49.09#ibcon#flushed, iclass 16, count 2 2006.253.08:25:49.09#ibcon#about to write, iclass 16, count 2 2006.253.08:25:49.09#ibcon#wrote, iclass 16, count 2 2006.253.08:25:49.09#ibcon#about to read 3, iclass 16, count 2 2006.253.08:25:49.12#ibcon#read 3, iclass 16, count 2 2006.253.08:25:49.12#ibcon#about to read 4, iclass 16, count 2 2006.253.08:25:49.12#ibcon#read 4, iclass 16, count 2 2006.253.08:25:49.12#ibcon#about to read 5, iclass 16, count 2 2006.253.08:25:49.12#ibcon#read 5, iclass 16, count 2 2006.253.08:25:49.12#ibcon#about to read 6, iclass 16, count 2 2006.253.08:25:49.12#ibcon#read 6, iclass 16, count 2 2006.253.08:25:49.12#ibcon#end of sib2, iclass 16, count 2 2006.253.08:25:49.12#ibcon#*after write, iclass 16, count 2 2006.253.08:25:49.12#ibcon#*before return 0, iclass 16, count 2 2006.253.08:25:49.12#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.253.08:25:49.12#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.253.08:25:49.12#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.253.08:25:49.12#ibcon#ireg 7 cls_cnt 0 2006.253.08:25:49.12#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.253.08:25:49.24#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.253.08:25:49.24#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.253.08:25:49.24#ibcon#enter wrdev, iclass 16, count 0 2006.253.08:25:49.24#ibcon#first serial, iclass 16, count 0 2006.253.08:25:49.24#ibcon#enter sib2, iclass 16, count 0 2006.253.08:25:49.24#ibcon#flushed, iclass 16, count 0 2006.253.08:25:49.24#ibcon#about to write, iclass 16, count 0 2006.253.08:25:49.24#ibcon#wrote, iclass 16, count 0 2006.253.08:25:49.24#ibcon#about to read 3, iclass 16, count 0 2006.253.08:25:49.26#ibcon#read 3, iclass 16, count 0 2006.253.08:25:49.26#ibcon#about to read 4, iclass 16, count 0 2006.253.08:25:49.26#ibcon#read 4, iclass 16, count 0 2006.253.08:25:49.26#ibcon#about to read 5, iclass 16, count 0 2006.253.08:25:49.26#ibcon#read 5, iclass 16, count 0 2006.253.08:25:49.26#ibcon#about to read 6, iclass 16, count 0 2006.253.08:25:49.26#ibcon#read 6, iclass 16, count 0 2006.253.08:25:49.26#ibcon#end of sib2, iclass 16, count 0 2006.253.08:25:49.26#ibcon#*mode == 0, iclass 16, count 0 2006.253.08:25:49.26#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.253.08:25:49.26#ibcon#[25=USB\r\n] 2006.253.08:25:49.26#ibcon#*before write, iclass 16, count 0 2006.253.08:25:49.26#ibcon#enter sib2, iclass 16, count 0 2006.253.08:25:49.26#ibcon#flushed, iclass 16, count 0 2006.253.08:25:49.26#ibcon#about to write, iclass 16, count 0 2006.253.08:25:49.26#ibcon#wrote, iclass 16, count 0 2006.253.08:25:49.26#ibcon#about to read 3, iclass 16, count 0 2006.253.08:25:49.29#ibcon#read 3, iclass 16, count 0 2006.253.08:25:49.29#ibcon#about to read 4, iclass 16, count 0 2006.253.08:25:49.29#ibcon#read 4, iclass 16, count 0 2006.253.08:25:49.29#ibcon#about to read 5, iclass 16, count 0 2006.253.08:25:49.29#ibcon#read 5, iclass 16, count 0 2006.253.08:25:49.29#ibcon#about to read 6, iclass 16, count 0 2006.253.08:25:49.29#ibcon#read 6, iclass 16, count 0 2006.253.08:25:49.29#ibcon#end of sib2, iclass 16, count 0 2006.253.08:25:49.29#ibcon#*after write, iclass 16, count 0 2006.253.08:25:49.29#ibcon#*before return 0, iclass 16, count 0 2006.253.08:25:49.29#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.253.08:25:49.29#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.253.08:25:49.29#ibcon#about to clear, iclass 16 cls_cnt 0 2006.253.08:25:49.29#ibcon#cleared, iclass 16 cls_cnt 0 2006.253.08:25:49.29$vc4f8/valo=5,652.99 2006.253.08:25:49.29#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.253.08:25:49.29#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.253.08:25:49.29#ibcon#ireg 17 cls_cnt 0 2006.253.08:25:49.29#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.253.08:25:49.29#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.253.08:25:49.29#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.253.08:25:49.29#ibcon#enter wrdev, iclass 18, count 0 2006.253.08:25:49.29#ibcon#first serial, iclass 18, count 0 2006.253.08:25:49.29#ibcon#enter sib2, iclass 18, count 0 2006.253.08:25:49.29#ibcon#flushed, iclass 18, count 0 2006.253.08:25:49.29#ibcon#about to write, iclass 18, count 0 2006.253.08:25:49.29#ibcon#wrote, iclass 18, count 0 2006.253.08:25:49.29#ibcon#about to read 3, iclass 18, count 0 2006.253.08:25:49.31#ibcon#read 3, iclass 18, count 0 2006.253.08:25:49.31#ibcon#about to read 4, iclass 18, count 0 2006.253.08:25:49.31#ibcon#read 4, iclass 18, count 0 2006.253.08:25:49.31#ibcon#about to read 5, iclass 18, count 0 2006.253.08:25:49.31#ibcon#read 5, iclass 18, count 0 2006.253.08:25:49.31#ibcon#about to read 6, iclass 18, count 0 2006.253.08:25:49.31#ibcon#read 6, iclass 18, count 0 2006.253.08:25:49.31#ibcon#end of sib2, iclass 18, count 0 2006.253.08:25:49.31#ibcon#*mode == 0, iclass 18, count 0 2006.253.08:25:49.31#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.253.08:25:49.31#ibcon#[26=FRQ=05,652.99\r\n] 2006.253.08:25:49.31#ibcon#*before write, iclass 18, count 0 2006.253.08:25:49.31#ibcon#enter sib2, iclass 18, count 0 2006.253.08:25:49.31#ibcon#flushed, iclass 18, count 0 2006.253.08:25:49.31#ibcon#about to write, iclass 18, count 0 2006.253.08:25:49.31#ibcon#wrote, iclass 18, count 0 2006.253.08:25:49.31#ibcon#about to read 3, iclass 18, count 0 2006.253.08:25:49.35#ibcon#read 3, iclass 18, count 0 2006.253.08:25:49.35#ibcon#about to read 4, iclass 18, count 0 2006.253.08:25:49.35#ibcon#read 4, iclass 18, count 0 2006.253.08:25:49.35#ibcon#about to read 5, iclass 18, count 0 2006.253.08:25:49.35#ibcon#read 5, iclass 18, count 0 2006.253.08:25:49.35#ibcon#about to read 6, iclass 18, count 0 2006.253.08:25:49.35#ibcon#read 6, iclass 18, count 0 2006.253.08:25:49.35#ibcon#end of sib2, iclass 18, count 0 2006.253.08:25:49.35#ibcon#*after write, iclass 18, count 0 2006.253.08:25:49.35#ibcon#*before return 0, iclass 18, count 0 2006.253.08:25:49.35#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.253.08:25:49.35#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.253.08:25:49.35#ibcon#about to clear, iclass 18 cls_cnt 0 2006.253.08:25:49.35#ibcon#cleared, iclass 18 cls_cnt 0 2006.253.08:25:49.35$vc4f8/va=5,7 2006.253.08:25:49.35#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.253.08:25:49.35#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.253.08:25:49.35#ibcon#ireg 11 cls_cnt 2 2006.253.08:25:49.35#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.253.08:25:49.41#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.253.08:25:49.41#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.253.08:25:49.41#ibcon#enter wrdev, iclass 20, count 2 2006.253.08:25:49.41#ibcon#first serial, iclass 20, count 2 2006.253.08:25:49.41#ibcon#enter sib2, iclass 20, count 2 2006.253.08:25:49.41#ibcon#flushed, iclass 20, count 2 2006.253.08:25:49.41#ibcon#about to write, iclass 20, count 2 2006.253.08:25:49.41#ibcon#wrote, iclass 20, count 2 2006.253.08:25:49.41#ibcon#about to read 3, iclass 20, count 2 2006.253.08:25:49.43#ibcon#read 3, iclass 20, count 2 2006.253.08:25:49.43#ibcon#about to read 4, iclass 20, count 2 2006.253.08:25:49.43#ibcon#read 4, iclass 20, count 2 2006.253.08:25:49.43#ibcon#about to read 5, iclass 20, count 2 2006.253.08:25:49.43#ibcon#read 5, iclass 20, count 2 2006.253.08:25:49.43#ibcon#about to read 6, iclass 20, count 2 2006.253.08:25:49.43#ibcon#read 6, iclass 20, count 2 2006.253.08:25:49.43#ibcon#end of sib2, iclass 20, count 2 2006.253.08:25:49.43#ibcon#*mode == 0, iclass 20, count 2 2006.253.08:25:49.43#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.253.08:25:49.43#ibcon#[25=AT05-07\r\n] 2006.253.08:25:49.43#ibcon#*before write, iclass 20, count 2 2006.253.08:25:49.43#ibcon#enter sib2, iclass 20, count 2 2006.253.08:25:49.43#ibcon#flushed, iclass 20, count 2 2006.253.08:25:49.43#ibcon#about to write, iclass 20, count 2 2006.253.08:25:49.43#ibcon#wrote, iclass 20, count 2 2006.253.08:25:49.43#ibcon#about to read 3, iclass 20, count 2 2006.253.08:25:49.46#ibcon#read 3, iclass 20, count 2 2006.253.08:25:49.46#ibcon#about to read 4, iclass 20, count 2 2006.253.08:25:49.46#ibcon#read 4, iclass 20, count 2 2006.253.08:25:49.46#ibcon#about to read 5, iclass 20, count 2 2006.253.08:25:49.46#ibcon#read 5, iclass 20, count 2 2006.253.08:25:49.46#ibcon#about to read 6, iclass 20, count 2 2006.253.08:25:49.46#ibcon#read 6, iclass 20, count 2 2006.253.08:25:49.46#ibcon#end of sib2, iclass 20, count 2 2006.253.08:25:49.46#ibcon#*after write, iclass 20, count 2 2006.253.08:25:49.46#ibcon#*before return 0, iclass 20, count 2 2006.253.08:25:49.46#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.253.08:25:49.46#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.253.08:25:49.46#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.253.08:25:49.46#ibcon#ireg 7 cls_cnt 0 2006.253.08:25:49.46#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.253.08:25:49.58#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.253.08:25:49.58#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.253.08:25:49.58#ibcon#enter wrdev, iclass 20, count 0 2006.253.08:25:49.58#ibcon#first serial, iclass 20, count 0 2006.253.08:25:49.58#ibcon#enter sib2, iclass 20, count 0 2006.253.08:25:49.58#ibcon#flushed, iclass 20, count 0 2006.253.08:25:49.58#ibcon#about to write, iclass 20, count 0 2006.253.08:25:49.58#ibcon#wrote, iclass 20, count 0 2006.253.08:25:49.58#ibcon#about to read 3, iclass 20, count 0 2006.253.08:25:49.60#ibcon#read 3, iclass 20, count 0 2006.253.08:25:49.60#ibcon#about to read 4, iclass 20, count 0 2006.253.08:25:49.60#ibcon#read 4, iclass 20, count 0 2006.253.08:25:49.60#ibcon#about to read 5, iclass 20, count 0 2006.253.08:25:49.60#ibcon#read 5, iclass 20, count 0 2006.253.08:25:49.60#ibcon#about to read 6, iclass 20, count 0 2006.253.08:25:49.60#ibcon#read 6, iclass 20, count 0 2006.253.08:25:49.60#ibcon#end of sib2, iclass 20, count 0 2006.253.08:25:49.60#ibcon#*mode == 0, iclass 20, count 0 2006.253.08:25:49.60#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.253.08:25:49.60#ibcon#[25=USB\r\n] 2006.253.08:25:49.60#ibcon#*before write, iclass 20, count 0 2006.253.08:25:49.60#ibcon#enter sib2, iclass 20, count 0 2006.253.08:25:49.60#ibcon#flushed, iclass 20, count 0 2006.253.08:25:49.60#ibcon#about to write, iclass 20, count 0 2006.253.08:25:49.60#ibcon#wrote, iclass 20, count 0 2006.253.08:25:49.60#ibcon#about to read 3, iclass 20, count 0 2006.253.08:25:49.63#ibcon#read 3, iclass 20, count 0 2006.253.08:25:49.63#ibcon#about to read 4, iclass 20, count 0 2006.253.08:25:49.63#ibcon#read 4, iclass 20, count 0 2006.253.08:25:49.63#ibcon#about to read 5, iclass 20, count 0 2006.253.08:25:49.63#ibcon#read 5, iclass 20, count 0 2006.253.08:25:49.63#ibcon#about to read 6, iclass 20, count 0 2006.253.08:25:49.63#ibcon#read 6, iclass 20, count 0 2006.253.08:25:49.63#ibcon#end of sib2, iclass 20, count 0 2006.253.08:25:49.63#ibcon#*after write, iclass 20, count 0 2006.253.08:25:49.63#ibcon#*before return 0, iclass 20, count 0 2006.253.08:25:49.63#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.253.08:25:49.63#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.253.08:25:49.63#ibcon#about to clear, iclass 20 cls_cnt 0 2006.253.08:25:49.63#ibcon#cleared, iclass 20 cls_cnt 0 2006.253.08:25:49.63$vc4f8/valo=6,772.99 2006.253.08:25:49.63#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.253.08:25:49.63#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.253.08:25:49.63#ibcon#ireg 17 cls_cnt 0 2006.253.08:25:49.63#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.253.08:25:49.63#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.253.08:25:49.63#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.253.08:25:49.63#ibcon#enter wrdev, iclass 22, count 0 2006.253.08:25:49.63#ibcon#first serial, iclass 22, count 0 2006.253.08:25:49.63#ibcon#enter sib2, iclass 22, count 0 2006.253.08:25:49.63#ibcon#flushed, iclass 22, count 0 2006.253.08:25:49.63#ibcon#about to write, iclass 22, count 0 2006.253.08:25:49.63#ibcon#wrote, iclass 22, count 0 2006.253.08:25:49.63#ibcon#about to read 3, iclass 22, count 0 2006.253.08:25:49.65#ibcon#read 3, iclass 22, count 0 2006.253.08:25:49.65#ibcon#about to read 4, iclass 22, count 0 2006.253.08:25:49.65#ibcon#read 4, iclass 22, count 0 2006.253.08:25:49.65#ibcon#about to read 5, iclass 22, count 0 2006.253.08:25:49.65#ibcon#read 5, iclass 22, count 0 2006.253.08:25:49.65#ibcon#about to read 6, iclass 22, count 0 2006.253.08:25:49.65#ibcon#read 6, iclass 22, count 0 2006.253.08:25:49.65#ibcon#end of sib2, iclass 22, count 0 2006.253.08:25:49.65#ibcon#*mode == 0, iclass 22, count 0 2006.253.08:25:49.65#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.253.08:25:49.65#ibcon#[26=FRQ=06,772.99\r\n] 2006.253.08:25:49.65#ibcon#*before write, iclass 22, count 0 2006.253.08:25:49.65#ibcon#enter sib2, iclass 22, count 0 2006.253.08:25:49.65#ibcon#flushed, iclass 22, count 0 2006.253.08:25:49.65#ibcon#about to write, iclass 22, count 0 2006.253.08:25:49.65#ibcon#wrote, iclass 22, count 0 2006.253.08:25:49.65#ibcon#about to read 3, iclass 22, count 0 2006.253.08:25:49.69#ibcon#read 3, iclass 22, count 0 2006.253.08:25:49.69#ibcon#about to read 4, iclass 22, count 0 2006.253.08:25:49.69#ibcon#read 4, iclass 22, count 0 2006.253.08:25:49.69#ibcon#about to read 5, iclass 22, count 0 2006.253.08:25:49.69#ibcon#read 5, iclass 22, count 0 2006.253.08:25:49.69#ibcon#about to read 6, iclass 22, count 0 2006.253.08:25:49.69#ibcon#read 6, iclass 22, count 0 2006.253.08:25:49.69#ibcon#end of sib2, iclass 22, count 0 2006.253.08:25:49.69#ibcon#*after write, iclass 22, count 0 2006.253.08:25:49.69#ibcon#*before return 0, iclass 22, count 0 2006.253.08:25:49.69#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.253.08:25:49.69#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.253.08:25:49.69#ibcon#about to clear, iclass 22 cls_cnt 0 2006.253.08:25:49.69#ibcon#cleared, iclass 22 cls_cnt 0 2006.253.08:25:49.69$vc4f8/va=6,7 2006.253.08:25:49.69#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.253.08:25:49.69#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.253.08:25:49.69#ibcon#ireg 11 cls_cnt 2 2006.253.08:25:49.69#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.253.08:25:49.76#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.253.08:25:49.76#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.253.08:25:49.76#ibcon#enter wrdev, iclass 24, count 2 2006.253.08:25:49.76#ibcon#first serial, iclass 24, count 2 2006.253.08:25:49.76#ibcon#enter sib2, iclass 24, count 2 2006.253.08:25:49.76#ibcon#flushed, iclass 24, count 2 2006.253.08:25:49.76#ibcon#about to write, iclass 24, count 2 2006.253.08:25:49.76#ibcon#wrote, iclass 24, count 2 2006.253.08:25:49.76#ibcon#about to read 3, iclass 24, count 2 2006.253.08:25:49.77#ibcon#read 3, iclass 24, count 2 2006.253.08:25:49.77#ibcon#about to read 4, iclass 24, count 2 2006.253.08:25:49.77#ibcon#read 4, iclass 24, count 2 2006.253.08:25:49.77#ibcon#about to read 5, iclass 24, count 2 2006.253.08:25:49.77#ibcon#read 5, iclass 24, count 2 2006.253.08:25:49.77#ibcon#about to read 6, iclass 24, count 2 2006.253.08:25:49.77#ibcon#read 6, iclass 24, count 2 2006.253.08:25:49.77#ibcon#end of sib2, iclass 24, count 2 2006.253.08:25:49.77#ibcon#*mode == 0, iclass 24, count 2 2006.253.08:25:49.77#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.253.08:25:49.77#ibcon#[25=AT06-07\r\n] 2006.253.08:25:49.77#ibcon#*before write, iclass 24, count 2 2006.253.08:25:49.77#ibcon#enter sib2, iclass 24, count 2 2006.253.08:25:49.77#ibcon#flushed, iclass 24, count 2 2006.253.08:25:49.77#ibcon#about to write, iclass 24, count 2 2006.253.08:25:49.77#ibcon#wrote, iclass 24, count 2 2006.253.08:25:49.77#ibcon#about to read 3, iclass 24, count 2 2006.253.08:25:49.80#ibcon#read 3, iclass 24, count 2 2006.253.08:25:49.80#ibcon#about to read 4, iclass 24, count 2 2006.253.08:25:49.80#ibcon#read 4, iclass 24, count 2 2006.253.08:25:49.80#ibcon#about to read 5, iclass 24, count 2 2006.253.08:25:49.80#ibcon#read 5, iclass 24, count 2 2006.253.08:25:49.80#ibcon#about to read 6, iclass 24, count 2 2006.253.08:25:49.80#ibcon#read 6, iclass 24, count 2 2006.253.08:25:49.80#ibcon#end of sib2, iclass 24, count 2 2006.253.08:25:49.80#ibcon#*after write, iclass 24, count 2 2006.253.08:25:49.80#ibcon#*before return 0, iclass 24, count 2 2006.253.08:25:49.80#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.253.08:25:49.80#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.253.08:25:49.80#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.253.08:25:49.80#ibcon#ireg 7 cls_cnt 0 2006.253.08:25:49.80#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.253.08:25:49.92#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.253.08:25:49.92#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.253.08:25:49.92#ibcon#enter wrdev, iclass 24, count 0 2006.253.08:25:49.92#ibcon#first serial, iclass 24, count 0 2006.253.08:25:49.92#ibcon#enter sib2, iclass 24, count 0 2006.253.08:25:49.92#ibcon#flushed, iclass 24, count 0 2006.253.08:25:49.92#ibcon#about to write, iclass 24, count 0 2006.253.08:25:49.92#ibcon#wrote, iclass 24, count 0 2006.253.08:25:49.92#ibcon#about to read 3, iclass 24, count 0 2006.253.08:25:49.94#ibcon#read 3, iclass 24, count 0 2006.253.08:25:49.94#ibcon#about to read 4, iclass 24, count 0 2006.253.08:25:49.94#ibcon#read 4, iclass 24, count 0 2006.253.08:25:49.94#ibcon#about to read 5, iclass 24, count 0 2006.253.08:25:49.94#ibcon#read 5, iclass 24, count 0 2006.253.08:25:49.94#ibcon#about to read 6, iclass 24, count 0 2006.253.08:25:49.94#ibcon#read 6, iclass 24, count 0 2006.253.08:25:49.94#ibcon#end of sib2, iclass 24, count 0 2006.253.08:25:49.94#ibcon#*mode == 0, iclass 24, count 0 2006.253.08:25:49.94#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.253.08:25:49.94#ibcon#[25=USB\r\n] 2006.253.08:25:49.94#ibcon#*before write, iclass 24, count 0 2006.253.08:25:49.94#ibcon#enter sib2, iclass 24, count 0 2006.253.08:25:49.94#ibcon#flushed, iclass 24, count 0 2006.253.08:25:49.94#ibcon#about to write, iclass 24, count 0 2006.253.08:25:49.94#ibcon#wrote, iclass 24, count 0 2006.253.08:25:49.94#ibcon#about to read 3, iclass 24, count 0 2006.253.08:25:49.97#ibcon#read 3, iclass 24, count 0 2006.253.08:25:49.97#ibcon#about to read 4, iclass 24, count 0 2006.253.08:25:49.97#ibcon#read 4, iclass 24, count 0 2006.253.08:25:49.97#ibcon#about to read 5, iclass 24, count 0 2006.253.08:25:49.97#ibcon#read 5, iclass 24, count 0 2006.253.08:25:49.97#ibcon#about to read 6, iclass 24, count 0 2006.253.08:25:49.97#ibcon#read 6, iclass 24, count 0 2006.253.08:25:49.97#ibcon#end of sib2, iclass 24, count 0 2006.253.08:25:49.97#ibcon#*after write, iclass 24, count 0 2006.253.08:25:49.97#ibcon#*before return 0, iclass 24, count 0 2006.253.08:25:49.97#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.253.08:25:49.97#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.253.08:25:49.97#ibcon#about to clear, iclass 24 cls_cnt 0 2006.253.08:25:49.97#ibcon#cleared, iclass 24 cls_cnt 0 2006.253.08:25:49.97$vc4f8/valo=7,832.99 2006.253.08:25:49.97#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.253.08:25:49.97#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.253.08:25:49.97#ibcon#ireg 17 cls_cnt 0 2006.253.08:25:49.97#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.253.08:25:49.97#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.253.08:25:49.97#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.253.08:25:49.97#ibcon#enter wrdev, iclass 26, count 0 2006.253.08:25:49.97#ibcon#first serial, iclass 26, count 0 2006.253.08:25:49.97#ibcon#enter sib2, iclass 26, count 0 2006.253.08:25:49.97#ibcon#flushed, iclass 26, count 0 2006.253.08:25:49.97#ibcon#about to write, iclass 26, count 0 2006.253.08:25:49.97#ibcon#wrote, iclass 26, count 0 2006.253.08:25:49.97#ibcon#about to read 3, iclass 26, count 0 2006.253.08:25:49.99#ibcon#read 3, iclass 26, count 0 2006.253.08:25:49.99#ibcon#about to read 4, iclass 26, count 0 2006.253.08:25:49.99#ibcon#read 4, iclass 26, count 0 2006.253.08:25:49.99#ibcon#about to read 5, iclass 26, count 0 2006.253.08:25:49.99#ibcon#read 5, iclass 26, count 0 2006.253.08:25:49.99#ibcon#about to read 6, iclass 26, count 0 2006.253.08:25:49.99#ibcon#read 6, iclass 26, count 0 2006.253.08:25:49.99#ibcon#end of sib2, iclass 26, count 0 2006.253.08:25:49.99#ibcon#*mode == 0, iclass 26, count 0 2006.253.08:25:49.99#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.253.08:25:49.99#ibcon#[26=FRQ=07,832.99\r\n] 2006.253.08:25:49.99#ibcon#*before write, iclass 26, count 0 2006.253.08:25:49.99#ibcon#enter sib2, iclass 26, count 0 2006.253.08:25:49.99#ibcon#flushed, iclass 26, count 0 2006.253.08:25:49.99#ibcon#about to write, iclass 26, count 0 2006.253.08:25:49.99#ibcon#wrote, iclass 26, count 0 2006.253.08:25:49.99#ibcon#about to read 3, iclass 26, count 0 2006.253.08:25:50.03#ibcon#read 3, iclass 26, count 0 2006.253.08:25:50.03#ibcon#about to read 4, iclass 26, count 0 2006.253.08:25:50.03#ibcon#read 4, iclass 26, count 0 2006.253.08:25:50.03#ibcon#about to read 5, iclass 26, count 0 2006.253.08:25:50.03#ibcon#read 5, iclass 26, count 0 2006.253.08:25:50.03#ibcon#about to read 6, iclass 26, count 0 2006.253.08:25:50.03#ibcon#read 6, iclass 26, count 0 2006.253.08:25:50.03#ibcon#end of sib2, iclass 26, count 0 2006.253.08:25:50.03#ibcon#*after write, iclass 26, count 0 2006.253.08:25:50.03#ibcon#*before return 0, iclass 26, count 0 2006.253.08:25:50.03#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.253.08:25:50.03#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.253.08:25:50.03#ibcon#about to clear, iclass 26 cls_cnt 0 2006.253.08:25:50.03#ibcon#cleared, iclass 26 cls_cnt 0 2006.253.08:25:50.03$vc4f8/va=7,7 2006.253.08:25:50.03#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.253.08:25:50.03#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.253.08:25:50.03#ibcon#ireg 11 cls_cnt 2 2006.253.08:25:50.03#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.253.08:25:50.09#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.253.08:25:50.09#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.253.08:25:50.09#ibcon#enter wrdev, iclass 28, count 2 2006.253.08:25:50.09#ibcon#first serial, iclass 28, count 2 2006.253.08:25:50.09#ibcon#enter sib2, iclass 28, count 2 2006.253.08:25:50.09#ibcon#flushed, iclass 28, count 2 2006.253.08:25:50.09#ibcon#about to write, iclass 28, count 2 2006.253.08:25:50.09#ibcon#wrote, iclass 28, count 2 2006.253.08:25:50.09#ibcon#about to read 3, iclass 28, count 2 2006.253.08:25:50.11#ibcon#read 3, iclass 28, count 2 2006.253.08:25:50.11#ibcon#about to read 4, iclass 28, count 2 2006.253.08:25:50.11#ibcon#read 4, iclass 28, count 2 2006.253.08:25:50.11#ibcon#about to read 5, iclass 28, count 2 2006.253.08:25:50.11#ibcon#read 5, iclass 28, count 2 2006.253.08:25:50.11#ibcon#about to read 6, iclass 28, count 2 2006.253.08:25:50.11#ibcon#read 6, iclass 28, count 2 2006.253.08:25:50.11#ibcon#end of sib2, iclass 28, count 2 2006.253.08:25:50.11#ibcon#*mode == 0, iclass 28, count 2 2006.253.08:25:50.11#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.253.08:25:50.11#ibcon#[25=AT07-07\r\n] 2006.253.08:25:50.11#ibcon#*before write, iclass 28, count 2 2006.253.08:25:50.11#ibcon#enter sib2, iclass 28, count 2 2006.253.08:25:50.11#ibcon#flushed, iclass 28, count 2 2006.253.08:25:50.11#ibcon#about to write, iclass 28, count 2 2006.253.08:25:50.11#ibcon#wrote, iclass 28, count 2 2006.253.08:25:50.11#ibcon#about to read 3, iclass 28, count 2 2006.253.08:25:50.14#ibcon#read 3, iclass 28, count 2 2006.253.08:25:50.14#ibcon#about to read 4, iclass 28, count 2 2006.253.08:25:50.14#ibcon#read 4, iclass 28, count 2 2006.253.08:25:50.14#ibcon#about to read 5, iclass 28, count 2 2006.253.08:25:50.14#ibcon#read 5, iclass 28, count 2 2006.253.08:25:50.14#ibcon#about to read 6, iclass 28, count 2 2006.253.08:25:50.14#ibcon#read 6, iclass 28, count 2 2006.253.08:25:50.14#ibcon#end of sib2, iclass 28, count 2 2006.253.08:25:50.14#ibcon#*after write, iclass 28, count 2 2006.253.08:25:50.14#ibcon#*before return 0, iclass 28, count 2 2006.253.08:25:50.14#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.253.08:25:50.14#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.253.08:25:50.14#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.253.08:25:50.14#ibcon#ireg 7 cls_cnt 0 2006.253.08:25:50.14#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.253.08:25:50.26#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.253.08:25:50.26#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.253.08:25:50.26#ibcon#enter wrdev, iclass 28, count 0 2006.253.08:25:50.26#ibcon#first serial, iclass 28, count 0 2006.253.08:25:50.26#ibcon#enter sib2, iclass 28, count 0 2006.253.08:25:50.26#ibcon#flushed, iclass 28, count 0 2006.253.08:25:50.26#ibcon#about to write, iclass 28, count 0 2006.253.08:25:50.26#ibcon#wrote, iclass 28, count 0 2006.253.08:25:50.26#ibcon#about to read 3, iclass 28, count 0 2006.253.08:25:50.28#ibcon#read 3, iclass 28, count 0 2006.253.08:25:50.28#ibcon#about to read 4, iclass 28, count 0 2006.253.08:25:50.28#ibcon#read 4, iclass 28, count 0 2006.253.08:25:50.28#ibcon#about to read 5, iclass 28, count 0 2006.253.08:25:50.28#ibcon#read 5, iclass 28, count 0 2006.253.08:25:50.28#ibcon#about to read 6, iclass 28, count 0 2006.253.08:25:50.28#ibcon#read 6, iclass 28, count 0 2006.253.08:25:50.28#ibcon#end of sib2, iclass 28, count 0 2006.253.08:25:50.28#ibcon#*mode == 0, iclass 28, count 0 2006.253.08:25:50.28#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.253.08:25:50.28#ibcon#[25=USB\r\n] 2006.253.08:25:50.28#ibcon#*before write, iclass 28, count 0 2006.253.08:25:50.28#ibcon#enter sib2, iclass 28, count 0 2006.253.08:25:50.28#ibcon#flushed, iclass 28, count 0 2006.253.08:25:50.28#ibcon#about to write, iclass 28, count 0 2006.253.08:25:50.28#ibcon#wrote, iclass 28, count 0 2006.253.08:25:50.28#ibcon#about to read 3, iclass 28, count 0 2006.253.08:25:50.31#ibcon#read 3, iclass 28, count 0 2006.253.08:25:50.31#ibcon#about to read 4, iclass 28, count 0 2006.253.08:25:50.31#ibcon#read 4, iclass 28, count 0 2006.253.08:25:50.31#ibcon#about to read 5, iclass 28, count 0 2006.253.08:25:50.31#ibcon#read 5, iclass 28, count 0 2006.253.08:25:50.31#ibcon#about to read 6, iclass 28, count 0 2006.253.08:25:50.31#ibcon#read 6, iclass 28, count 0 2006.253.08:25:50.31#ibcon#end of sib2, iclass 28, count 0 2006.253.08:25:50.31#ibcon#*after write, iclass 28, count 0 2006.253.08:25:50.31#ibcon#*before return 0, iclass 28, count 0 2006.253.08:25:50.31#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.253.08:25:50.31#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.253.08:25:50.31#ibcon#about to clear, iclass 28 cls_cnt 0 2006.253.08:25:50.31#ibcon#cleared, iclass 28 cls_cnt 0 2006.253.08:25:50.31$vc4f8/valo=8,852.99 2006.253.08:25:50.31#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.253.08:25:50.31#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.253.08:25:50.31#ibcon#ireg 17 cls_cnt 0 2006.253.08:25:50.31#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.253.08:25:50.31#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.253.08:25:50.31#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.253.08:25:50.31#ibcon#enter wrdev, iclass 30, count 0 2006.253.08:25:50.31#ibcon#first serial, iclass 30, count 0 2006.253.08:25:50.31#ibcon#enter sib2, iclass 30, count 0 2006.253.08:25:50.31#ibcon#flushed, iclass 30, count 0 2006.253.08:25:50.31#ibcon#about to write, iclass 30, count 0 2006.253.08:25:50.31#ibcon#wrote, iclass 30, count 0 2006.253.08:25:50.31#ibcon#about to read 3, iclass 30, count 0 2006.253.08:25:50.33#ibcon#read 3, iclass 30, count 0 2006.253.08:25:50.33#ibcon#about to read 4, iclass 30, count 0 2006.253.08:25:50.33#ibcon#read 4, iclass 30, count 0 2006.253.08:25:50.33#ibcon#about to read 5, iclass 30, count 0 2006.253.08:25:50.33#ibcon#read 5, iclass 30, count 0 2006.253.08:25:50.33#ibcon#about to read 6, iclass 30, count 0 2006.253.08:25:50.33#ibcon#read 6, iclass 30, count 0 2006.253.08:25:50.33#ibcon#end of sib2, iclass 30, count 0 2006.253.08:25:50.33#ibcon#*mode == 0, iclass 30, count 0 2006.253.08:25:50.33#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.253.08:25:50.33#ibcon#[26=FRQ=08,852.99\r\n] 2006.253.08:25:50.33#ibcon#*before write, iclass 30, count 0 2006.253.08:25:50.33#ibcon#enter sib2, iclass 30, count 0 2006.253.08:25:50.33#ibcon#flushed, iclass 30, count 0 2006.253.08:25:50.33#ibcon#about to write, iclass 30, count 0 2006.253.08:25:50.33#ibcon#wrote, iclass 30, count 0 2006.253.08:25:50.33#ibcon#about to read 3, iclass 30, count 0 2006.253.08:25:50.37#ibcon#read 3, iclass 30, count 0 2006.253.08:25:50.37#ibcon#about to read 4, iclass 30, count 0 2006.253.08:25:50.37#ibcon#read 4, iclass 30, count 0 2006.253.08:25:50.37#ibcon#about to read 5, iclass 30, count 0 2006.253.08:25:50.37#ibcon#read 5, iclass 30, count 0 2006.253.08:25:50.37#ibcon#about to read 6, iclass 30, count 0 2006.253.08:25:50.37#ibcon#read 6, iclass 30, count 0 2006.253.08:25:50.37#ibcon#end of sib2, iclass 30, count 0 2006.253.08:25:50.37#ibcon#*after write, iclass 30, count 0 2006.253.08:25:50.37#ibcon#*before return 0, iclass 30, count 0 2006.253.08:25:50.37#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.253.08:25:50.37#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.253.08:25:50.37#ibcon#about to clear, iclass 30 cls_cnt 0 2006.253.08:25:50.37#ibcon#cleared, iclass 30 cls_cnt 0 2006.253.08:25:50.37$vc4f8/va=8,7 2006.253.08:25:50.37#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.253.08:25:50.37#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.253.08:25:50.37#ibcon#ireg 11 cls_cnt 2 2006.253.08:25:50.37#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.253.08:25:50.44#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.253.08:25:50.44#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.253.08:25:50.44#ibcon#enter wrdev, iclass 32, count 2 2006.253.08:25:50.44#ibcon#first serial, iclass 32, count 2 2006.253.08:25:50.44#ibcon#enter sib2, iclass 32, count 2 2006.253.08:25:50.44#ibcon#flushed, iclass 32, count 2 2006.253.08:25:50.44#ibcon#about to write, iclass 32, count 2 2006.253.08:25:50.44#ibcon#wrote, iclass 32, count 2 2006.253.08:25:50.44#ibcon#about to read 3, iclass 32, count 2 2006.253.08:25:50.45#ibcon#read 3, iclass 32, count 2 2006.253.08:25:50.45#ibcon#about to read 4, iclass 32, count 2 2006.253.08:25:50.45#ibcon#read 4, iclass 32, count 2 2006.253.08:25:50.45#ibcon#about to read 5, iclass 32, count 2 2006.253.08:25:50.45#ibcon#read 5, iclass 32, count 2 2006.253.08:25:50.45#ibcon#about to read 6, iclass 32, count 2 2006.253.08:25:50.45#ibcon#read 6, iclass 32, count 2 2006.253.08:25:50.45#ibcon#end of sib2, iclass 32, count 2 2006.253.08:25:50.45#ibcon#*mode == 0, iclass 32, count 2 2006.253.08:25:50.45#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.253.08:25:50.45#ibcon#[25=AT08-07\r\n] 2006.253.08:25:50.45#ibcon#*before write, iclass 32, count 2 2006.253.08:25:50.45#ibcon#enter sib2, iclass 32, count 2 2006.253.08:25:50.45#ibcon#flushed, iclass 32, count 2 2006.253.08:25:50.45#ibcon#about to write, iclass 32, count 2 2006.253.08:25:50.45#ibcon#wrote, iclass 32, count 2 2006.253.08:25:50.45#ibcon#about to read 3, iclass 32, count 2 2006.253.08:25:50.48#ibcon#read 3, iclass 32, count 2 2006.253.08:25:50.48#ibcon#about to read 4, iclass 32, count 2 2006.253.08:25:50.48#ibcon#read 4, iclass 32, count 2 2006.253.08:25:50.48#ibcon#about to read 5, iclass 32, count 2 2006.253.08:25:50.48#ibcon#read 5, iclass 32, count 2 2006.253.08:25:50.48#ibcon#about to read 6, iclass 32, count 2 2006.253.08:25:50.48#ibcon#read 6, iclass 32, count 2 2006.253.08:25:50.48#ibcon#end of sib2, iclass 32, count 2 2006.253.08:25:50.48#ibcon#*after write, iclass 32, count 2 2006.253.08:25:50.48#ibcon#*before return 0, iclass 32, count 2 2006.253.08:25:50.48#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.253.08:25:50.48#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.253.08:25:50.48#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.253.08:25:50.48#ibcon#ireg 7 cls_cnt 0 2006.253.08:25:50.48#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.253.08:25:50.60#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.253.08:25:50.60#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.253.08:25:50.60#ibcon#enter wrdev, iclass 32, count 0 2006.253.08:25:50.60#ibcon#first serial, iclass 32, count 0 2006.253.08:25:50.60#ibcon#enter sib2, iclass 32, count 0 2006.253.08:25:50.60#ibcon#flushed, iclass 32, count 0 2006.253.08:25:50.60#ibcon#about to write, iclass 32, count 0 2006.253.08:25:50.60#ibcon#wrote, iclass 32, count 0 2006.253.08:25:50.60#ibcon#about to read 3, iclass 32, count 0 2006.253.08:25:50.62#ibcon#read 3, iclass 32, count 0 2006.253.08:25:50.62#ibcon#about to read 4, iclass 32, count 0 2006.253.08:25:50.62#ibcon#read 4, iclass 32, count 0 2006.253.08:25:50.62#ibcon#about to read 5, iclass 32, count 0 2006.253.08:25:50.62#ibcon#read 5, iclass 32, count 0 2006.253.08:25:50.62#ibcon#about to read 6, iclass 32, count 0 2006.253.08:25:50.62#ibcon#read 6, iclass 32, count 0 2006.253.08:25:50.62#ibcon#end of sib2, iclass 32, count 0 2006.253.08:25:50.62#ibcon#*mode == 0, iclass 32, count 0 2006.253.08:25:50.62#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.253.08:25:50.62#ibcon#[25=USB\r\n] 2006.253.08:25:50.62#ibcon#*before write, iclass 32, count 0 2006.253.08:25:50.62#ibcon#enter sib2, iclass 32, count 0 2006.253.08:25:50.62#ibcon#flushed, iclass 32, count 0 2006.253.08:25:50.62#ibcon#about to write, iclass 32, count 0 2006.253.08:25:50.62#ibcon#wrote, iclass 32, count 0 2006.253.08:25:50.62#ibcon#about to read 3, iclass 32, count 0 2006.253.08:25:50.65#ibcon#read 3, iclass 32, count 0 2006.253.08:25:50.65#ibcon#about to read 4, iclass 32, count 0 2006.253.08:25:50.65#ibcon#read 4, iclass 32, count 0 2006.253.08:25:50.65#ibcon#about to read 5, iclass 32, count 0 2006.253.08:25:50.65#ibcon#read 5, iclass 32, count 0 2006.253.08:25:50.65#ibcon#about to read 6, iclass 32, count 0 2006.253.08:25:50.65#ibcon#read 6, iclass 32, count 0 2006.253.08:25:50.65#ibcon#end of sib2, iclass 32, count 0 2006.253.08:25:50.65#ibcon#*after write, iclass 32, count 0 2006.253.08:25:50.65#ibcon#*before return 0, iclass 32, count 0 2006.253.08:25:50.65#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.253.08:25:50.65#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.253.08:25:50.65#ibcon#about to clear, iclass 32 cls_cnt 0 2006.253.08:25:50.65#ibcon#cleared, iclass 32 cls_cnt 0 2006.253.08:25:50.65$vc4f8/vblo=1,632.99 2006.253.08:25:50.65#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.253.08:25:50.65#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.253.08:25:50.65#ibcon#ireg 17 cls_cnt 0 2006.253.08:25:50.65#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.253.08:25:50.65#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.253.08:25:50.65#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.253.08:25:50.65#ibcon#enter wrdev, iclass 34, count 0 2006.253.08:25:50.65#ibcon#first serial, iclass 34, count 0 2006.253.08:25:50.65#ibcon#enter sib2, iclass 34, count 0 2006.253.08:25:50.65#ibcon#flushed, iclass 34, count 0 2006.253.08:25:50.65#ibcon#about to write, iclass 34, count 0 2006.253.08:25:50.65#ibcon#wrote, iclass 34, count 0 2006.253.08:25:50.65#ibcon#about to read 3, iclass 34, count 0 2006.253.08:25:50.67#ibcon#read 3, iclass 34, count 0 2006.253.08:25:50.67#ibcon#about to read 4, iclass 34, count 0 2006.253.08:25:50.67#ibcon#read 4, iclass 34, count 0 2006.253.08:25:50.67#ibcon#about to read 5, iclass 34, count 0 2006.253.08:25:50.67#ibcon#read 5, iclass 34, count 0 2006.253.08:25:50.67#ibcon#about to read 6, iclass 34, count 0 2006.253.08:25:50.67#ibcon#read 6, iclass 34, count 0 2006.253.08:25:50.67#ibcon#end of sib2, iclass 34, count 0 2006.253.08:25:50.67#ibcon#*mode == 0, iclass 34, count 0 2006.253.08:25:50.67#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.253.08:25:50.67#ibcon#[28=FRQ=01,632.99\r\n] 2006.253.08:25:50.67#ibcon#*before write, iclass 34, count 0 2006.253.08:25:50.67#ibcon#enter sib2, iclass 34, count 0 2006.253.08:25:50.67#ibcon#flushed, iclass 34, count 0 2006.253.08:25:50.67#ibcon#about to write, iclass 34, count 0 2006.253.08:25:50.67#ibcon#wrote, iclass 34, count 0 2006.253.08:25:50.67#ibcon#about to read 3, iclass 34, count 0 2006.253.08:25:50.71#ibcon#read 3, iclass 34, count 0 2006.253.08:25:50.71#ibcon#about to read 4, iclass 34, count 0 2006.253.08:25:50.71#ibcon#read 4, iclass 34, count 0 2006.253.08:25:50.71#ibcon#about to read 5, iclass 34, count 0 2006.253.08:25:50.71#ibcon#read 5, iclass 34, count 0 2006.253.08:25:50.71#ibcon#about to read 6, iclass 34, count 0 2006.253.08:25:50.71#ibcon#read 6, iclass 34, count 0 2006.253.08:25:50.71#ibcon#end of sib2, iclass 34, count 0 2006.253.08:25:50.71#ibcon#*after write, iclass 34, count 0 2006.253.08:25:50.71#ibcon#*before return 0, iclass 34, count 0 2006.253.08:25:50.71#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.253.08:25:50.71#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.253.08:25:50.71#ibcon#about to clear, iclass 34 cls_cnt 0 2006.253.08:25:50.71#ibcon#cleared, iclass 34 cls_cnt 0 2006.253.08:25:50.71$vc4f8/vb=1,4 2006.253.08:25:50.71#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.253.08:25:50.71#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.253.08:25:50.71#ibcon#ireg 11 cls_cnt 2 2006.253.08:25:50.71#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.253.08:25:50.71#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.253.08:25:50.71#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.253.08:25:50.71#ibcon#enter wrdev, iclass 36, count 2 2006.253.08:25:50.71#ibcon#first serial, iclass 36, count 2 2006.253.08:25:50.71#ibcon#enter sib2, iclass 36, count 2 2006.253.08:25:50.71#ibcon#flushed, iclass 36, count 2 2006.253.08:25:50.71#ibcon#about to write, iclass 36, count 2 2006.253.08:25:50.71#ibcon#wrote, iclass 36, count 2 2006.253.08:25:50.71#ibcon#about to read 3, iclass 36, count 2 2006.253.08:25:50.73#ibcon#read 3, iclass 36, count 2 2006.253.08:25:50.73#ibcon#about to read 4, iclass 36, count 2 2006.253.08:25:50.73#ibcon#read 4, iclass 36, count 2 2006.253.08:25:50.73#ibcon#about to read 5, iclass 36, count 2 2006.253.08:25:50.73#ibcon#read 5, iclass 36, count 2 2006.253.08:25:50.73#ibcon#about to read 6, iclass 36, count 2 2006.253.08:25:50.73#ibcon#read 6, iclass 36, count 2 2006.253.08:25:50.73#ibcon#end of sib2, iclass 36, count 2 2006.253.08:25:50.73#ibcon#*mode == 0, iclass 36, count 2 2006.253.08:25:50.73#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.253.08:25:50.73#ibcon#[27=AT01-04\r\n] 2006.253.08:25:50.73#ibcon#*before write, iclass 36, count 2 2006.253.08:25:50.73#ibcon#enter sib2, iclass 36, count 2 2006.253.08:25:50.73#ibcon#flushed, iclass 36, count 2 2006.253.08:25:50.73#ibcon#about to write, iclass 36, count 2 2006.253.08:25:50.73#ibcon#wrote, iclass 36, count 2 2006.253.08:25:50.73#ibcon#about to read 3, iclass 36, count 2 2006.253.08:25:50.76#ibcon#read 3, iclass 36, count 2 2006.253.08:25:50.76#ibcon#about to read 4, iclass 36, count 2 2006.253.08:25:50.76#ibcon#read 4, iclass 36, count 2 2006.253.08:25:50.76#ibcon#about to read 5, iclass 36, count 2 2006.253.08:25:50.76#ibcon#read 5, iclass 36, count 2 2006.253.08:25:50.76#ibcon#about to read 6, iclass 36, count 2 2006.253.08:25:50.76#ibcon#read 6, iclass 36, count 2 2006.253.08:25:50.76#ibcon#end of sib2, iclass 36, count 2 2006.253.08:25:50.76#ibcon#*after write, iclass 36, count 2 2006.253.08:25:50.76#ibcon#*before return 0, iclass 36, count 2 2006.253.08:25:50.76#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.253.08:25:50.76#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.253.08:25:50.76#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.253.08:25:50.76#ibcon#ireg 7 cls_cnt 0 2006.253.08:25:50.76#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.253.08:25:50.88#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.253.08:25:50.88#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.253.08:25:50.88#ibcon#enter wrdev, iclass 36, count 0 2006.253.08:25:50.88#ibcon#first serial, iclass 36, count 0 2006.253.08:25:50.88#ibcon#enter sib2, iclass 36, count 0 2006.253.08:25:50.88#ibcon#flushed, iclass 36, count 0 2006.253.08:25:50.88#ibcon#about to write, iclass 36, count 0 2006.253.08:25:50.88#ibcon#wrote, iclass 36, count 0 2006.253.08:25:50.88#ibcon#about to read 3, iclass 36, count 0 2006.253.08:25:50.90#ibcon#read 3, iclass 36, count 0 2006.253.08:25:50.90#ibcon#about to read 4, iclass 36, count 0 2006.253.08:25:50.90#ibcon#read 4, iclass 36, count 0 2006.253.08:25:50.90#ibcon#about to read 5, iclass 36, count 0 2006.253.08:25:50.90#ibcon#read 5, iclass 36, count 0 2006.253.08:25:50.90#ibcon#about to read 6, iclass 36, count 0 2006.253.08:25:50.90#ibcon#read 6, iclass 36, count 0 2006.253.08:25:50.90#ibcon#end of sib2, iclass 36, count 0 2006.253.08:25:50.90#ibcon#*mode == 0, iclass 36, count 0 2006.253.08:25:50.90#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.253.08:25:50.90#ibcon#[27=USB\r\n] 2006.253.08:25:50.90#ibcon#*before write, iclass 36, count 0 2006.253.08:25:50.90#ibcon#enter sib2, iclass 36, count 0 2006.253.08:25:50.90#ibcon#flushed, iclass 36, count 0 2006.253.08:25:50.90#ibcon#about to write, iclass 36, count 0 2006.253.08:25:50.90#ibcon#wrote, iclass 36, count 0 2006.253.08:25:50.90#ibcon#about to read 3, iclass 36, count 0 2006.253.08:25:50.93#ibcon#read 3, iclass 36, count 0 2006.253.08:25:50.93#ibcon#about to read 4, iclass 36, count 0 2006.253.08:25:50.93#ibcon#read 4, iclass 36, count 0 2006.253.08:25:50.93#ibcon#about to read 5, iclass 36, count 0 2006.253.08:25:50.93#ibcon#read 5, iclass 36, count 0 2006.253.08:25:50.93#ibcon#about to read 6, iclass 36, count 0 2006.253.08:25:50.93#ibcon#read 6, iclass 36, count 0 2006.253.08:25:50.93#ibcon#end of sib2, iclass 36, count 0 2006.253.08:25:50.93#ibcon#*after write, iclass 36, count 0 2006.253.08:25:50.93#ibcon#*before return 0, iclass 36, count 0 2006.253.08:25:50.93#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.253.08:25:50.93#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.253.08:25:50.93#ibcon#about to clear, iclass 36 cls_cnt 0 2006.253.08:25:50.93#ibcon#cleared, iclass 36 cls_cnt 0 2006.253.08:25:50.93$vc4f8/vblo=2,640.99 2006.253.08:25:50.93#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.253.08:25:50.93#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.253.08:25:50.93#ibcon#ireg 17 cls_cnt 0 2006.253.08:25:50.93#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.253.08:25:50.93#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.253.08:25:50.93#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.253.08:25:50.93#ibcon#enter wrdev, iclass 38, count 0 2006.253.08:25:50.93#ibcon#first serial, iclass 38, count 0 2006.253.08:25:50.93#ibcon#enter sib2, iclass 38, count 0 2006.253.08:25:50.93#ibcon#flushed, iclass 38, count 0 2006.253.08:25:50.93#ibcon#about to write, iclass 38, count 0 2006.253.08:25:50.93#ibcon#wrote, iclass 38, count 0 2006.253.08:25:50.93#ibcon#about to read 3, iclass 38, count 0 2006.253.08:25:50.95#ibcon#read 3, iclass 38, count 0 2006.253.08:25:50.95#ibcon#about to read 4, iclass 38, count 0 2006.253.08:25:50.95#ibcon#read 4, iclass 38, count 0 2006.253.08:25:50.95#ibcon#about to read 5, iclass 38, count 0 2006.253.08:25:50.95#ibcon#read 5, iclass 38, count 0 2006.253.08:25:50.95#ibcon#about to read 6, iclass 38, count 0 2006.253.08:25:50.95#ibcon#read 6, iclass 38, count 0 2006.253.08:25:50.95#ibcon#end of sib2, iclass 38, count 0 2006.253.08:25:50.95#ibcon#*mode == 0, iclass 38, count 0 2006.253.08:25:50.95#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.253.08:25:50.95#ibcon#[28=FRQ=02,640.99\r\n] 2006.253.08:25:50.95#ibcon#*before write, iclass 38, count 0 2006.253.08:25:50.95#ibcon#enter sib2, iclass 38, count 0 2006.253.08:25:50.95#ibcon#flushed, iclass 38, count 0 2006.253.08:25:50.95#ibcon#about to write, iclass 38, count 0 2006.253.08:25:50.95#ibcon#wrote, iclass 38, count 0 2006.253.08:25:50.95#ibcon#about to read 3, iclass 38, count 0 2006.253.08:25:50.99#ibcon#read 3, iclass 38, count 0 2006.253.08:25:50.99#ibcon#about to read 4, iclass 38, count 0 2006.253.08:25:50.99#ibcon#read 4, iclass 38, count 0 2006.253.08:25:50.99#ibcon#about to read 5, iclass 38, count 0 2006.253.08:25:50.99#ibcon#read 5, iclass 38, count 0 2006.253.08:25:50.99#ibcon#about to read 6, iclass 38, count 0 2006.253.08:25:50.99#ibcon#read 6, iclass 38, count 0 2006.253.08:25:50.99#ibcon#end of sib2, iclass 38, count 0 2006.253.08:25:50.99#ibcon#*after write, iclass 38, count 0 2006.253.08:25:50.99#ibcon#*before return 0, iclass 38, count 0 2006.253.08:25:50.99#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.253.08:25:50.99#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.253.08:25:50.99#ibcon#about to clear, iclass 38 cls_cnt 0 2006.253.08:25:50.99#ibcon#cleared, iclass 38 cls_cnt 0 2006.253.08:25:50.99$vc4f8/vb=2,5 2006.253.08:25:50.99#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.253.08:25:50.99#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.253.08:25:50.99#ibcon#ireg 11 cls_cnt 2 2006.253.08:25:50.99#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.253.08:25:51.06#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.253.08:25:51.06#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.253.08:25:51.06#ibcon#enter wrdev, iclass 40, count 2 2006.253.08:25:51.06#ibcon#first serial, iclass 40, count 2 2006.253.08:25:51.06#ibcon#enter sib2, iclass 40, count 2 2006.253.08:25:51.06#ibcon#flushed, iclass 40, count 2 2006.253.08:25:51.06#ibcon#about to write, iclass 40, count 2 2006.253.08:25:51.06#ibcon#wrote, iclass 40, count 2 2006.253.08:25:51.06#ibcon#about to read 3, iclass 40, count 2 2006.253.08:25:51.07#ibcon#read 3, iclass 40, count 2 2006.253.08:25:51.07#ibcon#about to read 4, iclass 40, count 2 2006.253.08:25:51.07#ibcon#read 4, iclass 40, count 2 2006.253.08:25:51.07#ibcon#about to read 5, iclass 40, count 2 2006.253.08:25:51.07#ibcon#read 5, iclass 40, count 2 2006.253.08:25:51.07#ibcon#about to read 6, iclass 40, count 2 2006.253.08:25:51.07#ibcon#read 6, iclass 40, count 2 2006.253.08:25:51.07#ibcon#end of sib2, iclass 40, count 2 2006.253.08:25:51.07#ibcon#*mode == 0, iclass 40, count 2 2006.253.08:25:51.07#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.253.08:25:51.07#ibcon#[27=AT02-05\r\n] 2006.253.08:25:51.07#ibcon#*before write, iclass 40, count 2 2006.253.08:25:51.07#ibcon#enter sib2, iclass 40, count 2 2006.253.08:25:51.07#ibcon#flushed, iclass 40, count 2 2006.253.08:25:51.07#ibcon#about to write, iclass 40, count 2 2006.253.08:25:51.07#ibcon#wrote, iclass 40, count 2 2006.253.08:25:51.07#ibcon#about to read 3, iclass 40, count 2 2006.253.08:25:51.10#ibcon#read 3, iclass 40, count 2 2006.253.08:25:51.10#ibcon#about to read 4, iclass 40, count 2 2006.253.08:25:51.10#ibcon#read 4, iclass 40, count 2 2006.253.08:25:51.10#ibcon#about to read 5, iclass 40, count 2 2006.253.08:25:51.10#ibcon#read 5, iclass 40, count 2 2006.253.08:25:51.10#ibcon#about to read 6, iclass 40, count 2 2006.253.08:25:51.10#ibcon#read 6, iclass 40, count 2 2006.253.08:25:51.10#ibcon#end of sib2, iclass 40, count 2 2006.253.08:25:51.10#ibcon#*after write, iclass 40, count 2 2006.253.08:25:51.10#ibcon#*before return 0, iclass 40, count 2 2006.253.08:25:51.10#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.253.08:25:51.10#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.253.08:25:51.10#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.253.08:25:51.10#ibcon#ireg 7 cls_cnt 0 2006.253.08:25:51.10#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.253.08:25:51.22#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.253.08:25:51.22#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.253.08:25:51.22#ibcon#enter wrdev, iclass 40, count 0 2006.253.08:25:51.22#ibcon#first serial, iclass 40, count 0 2006.253.08:25:51.22#ibcon#enter sib2, iclass 40, count 0 2006.253.08:25:51.22#ibcon#flushed, iclass 40, count 0 2006.253.08:25:51.22#ibcon#about to write, iclass 40, count 0 2006.253.08:25:51.22#ibcon#wrote, iclass 40, count 0 2006.253.08:25:51.22#ibcon#about to read 3, iclass 40, count 0 2006.253.08:25:51.26#ibcon#read 3, iclass 40, count 0 2006.253.08:25:51.26#ibcon#about to read 4, iclass 40, count 0 2006.253.08:25:51.26#ibcon#read 4, iclass 40, count 0 2006.253.08:25:51.26#ibcon#about to read 5, iclass 40, count 0 2006.253.08:25:51.26#ibcon#read 5, iclass 40, count 0 2006.253.08:25:51.26#ibcon#about to read 6, iclass 40, count 0 2006.253.08:25:51.26#ibcon#read 6, iclass 40, count 0 2006.253.08:25:51.26#ibcon#end of sib2, iclass 40, count 0 2006.253.08:25:51.26#ibcon#*mode == 0, iclass 40, count 0 2006.253.08:25:51.26#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.253.08:25:51.26#ibcon#[27=USB\r\n] 2006.253.08:25:51.26#ibcon#*before write, iclass 40, count 0 2006.253.08:25:51.26#ibcon#enter sib2, iclass 40, count 0 2006.253.08:25:51.26#ibcon#flushed, iclass 40, count 0 2006.253.08:25:51.26#ibcon#about to write, iclass 40, count 0 2006.253.08:25:51.26#ibcon#wrote, iclass 40, count 0 2006.253.08:25:51.26#ibcon#about to read 3, iclass 40, count 0 2006.253.08:25:51.28#ibcon#read 3, iclass 40, count 0 2006.253.08:25:51.28#ibcon#about to read 4, iclass 40, count 0 2006.253.08:25:51.28#ibcon#read 4, iclass 40, count 0 2006.253.08:25:51.28#ibcon#about to read 5, iclass 40, count 0 2006.253.08:25:51.28#ibcon#read 5, iclass 40, count 0 2006.253.08:25:51.28#ibcon#about to read 6, iclass 40, count 0 2006.253.08:25:51.28#ibcon#read 6, iclass 40, count 0 2006.253.08:25:51.28#ibcon#end of sib2, iclass 40, count 0 2006.253.08:25:51.28#ibcon#*after write, iclass 40, count 0 2006.253.08:25:51.28#ibcon#*before return 0, iclass 40, count 0 2006.253.08:25:51.28#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.253.08:25:51.28#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.253.08:25:51.28#ibcon#about to clear, iclass 40 cls_cnt 0 2006.253.08:25:51.28#ibcon#cleared, iclass 40 cls_cnt 0 2006.253.08:25:51.28$vc4f8/vblo=3,656.99 2006.253.08:25:51.28#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.253.08:25:51.28#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.253.08:25:51.28#ibcon#ireg 17 cls_cnt 0 2006.253.08:25:51.28#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.253.08:25:51.28#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.253.08:25:51.28#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.253.08:25:51.28#ibcon#enter wrdev, iclass 4, count 0 2006.253.08:25:51.28#ibcon#first serial, iclass 4, count 0 2006.253.08:25:51.28#ibcon#enter sib2, iclass 4, count 0 2006.253.08:25:51.28#ibcon#flushed, iclass 4, count 0 2006.253.08:25:51.28#ibcon#about to write, iclass 4, count 0 2006.253.08:25:51.28#ibcon#wrote, iclass 4, count 0 2006.253.08:25:51.28#ibcon#about to read 3, iclass 4, count 0 2006.253.08:25:51.30#ibcon#read 3, iclass 4, count 0 2006.253.08:25:51.30#ibcon#about to read 4, iclass 4, count 0 2006.253.08:25:51.30#ibcon#read 4, iclass 4, count 0 2006.253.08:25:51.30#ibcon#about to read 5, iclass 4, count 0 2006.253.08:25:51.30#ibcon#read 5, iclass 4, count 0 2006.253.08:25:51.30#ibcon#about to read 6, iclass 4, count 0 2006.253.08:25:51.30#ibcon#read 6, iclass 4, count 0 2006.253.08:25:51.30#ibcon#end of sib2, iclass 4, count 0 2006.253.08:25:51.30#ibcon#*mode == 0, iclass 4, count 0 2006.253.08:25:51.30#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.253.08:25:51.30#ibcon#[28=FRQ=03,656.99\r\n] 2006.253.08:25:51.30#ibcon#*before write, iclass 4, count 0 2006.253.08:25:51.30#ibcon#enter sib2, iclass 4, count 0 2006.253.08:25:51.30#ibcon#flushed, iclass 4, count 0 2006.253.08:25:51.30#ibcon#about to write, iclass 4, count 0 2006.253.08:25:51.30#ibcon#wrote, iclass 4, count 0 2006.253.08:25:51.30#ibcon#about to read 3, iclass 4, count 0 2006.253.08:25:51.34#ibcon#read 3, iclass 4, count 0 2006.253.08:25:51.34#ibcon#about to read 4, iclass 4, count 0 2006.253.08:25:51.34#ibcon#read 4, iclass 4, count 0 2006.253.08:25:51.34#ibcon#about to read 5, iclass 4, count 0 2006.253.08:25:51.34#ibcon#read 5, iclass 4, count 0 2006.253.08:25:51.34#ibcon#about to read 6, iclass 4, count 0 2006.253.08:25:51.34#ibcon#read 6, iclass 4, count 0 2006.253.08:25:51.34#ibcon#end of sib2, iclass 4, count 0 2006.253.08:25:51.34#ibcon#*after write, iclass 4, count 0 2006.253.08:25:51.34#ibcon#*before return 0, iclass 4, count 0 2006.253.08:25:51.34#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.253.08:25:51.34#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.253.08:25:51.34#ibcon#about to clear, iclass 4 cls_cnt 0 2006.253.08:25:51.34#ibcon#cleared, iclass 4 cls_cnt 0 2006.253.08:25:51.34$vc4f8/vb=3,4 2006.253.08:25:51.34#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.253.08:25:51.34#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.253.08:25:51.34#ibcon#ireg 11 cls_cnt 2 2006.253.08:25:51.34#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.253.08:25:51.40#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.253.08:25:51.40#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.253.08:25:51.40#ibcon#enter wrdev, iclass 6, count 2 2006.253.08:25:51.40#ibcon#first serial, iclass 6, count 2 2006.253.08:25:51.40#ibcon#enter sib2, iclass 6, count 2 2006.253.08:25:51.40#ibcon#flushed, iclass 6, count 2 2006.253.08:25:51.40#ibcon#about to write, iclass 6, count 2 2006.253.08:25:51.40#ibcon#wrote, iclass 6, count 2 2006.253.08:25:51.40#ibcon#about to read 3, iclass 6, count 2 2006.253.08:25:51.42#ibcon#read 3, iclass 6, count 2 2006.253.08:25:51.42#ibcon#about to read 4, iclass 6, count 2 2006.253.08:25:51.42#ibcon#read 4, iclass 6, count 2 2006.253.08:25:51.42#ibcon#about to read 5, iclass 6, count 2 2006.253.08:25:51.42#ibcon#read 5, iclass 6, count 2 2006.253.08:25:51.42#ibcon#about to read 6, iclass 6, count 2 2006.253.08:25:51.42#ibcon#read 6, iclass 6, count 2 2006.253.08:25:51.42#ibcon#end of sib2, iclass 6, count 2 2006.253.08:25:51.42#ibcon#*mode == 0, iclass 6, count 2 2006.253.08:25:51.42#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.253.08:25:51.42#ibcon#[27=AT03-04\r\n] 2006.253.08:25:51.42#ibcon#*before write, iclass 6, count 2 2006.253.08:25:51.42#ibcon#enter sib2, iclass 6, count 2 2006.253.08:25:51.42#ibcon#flushed, iclass 6, count 2 2006.253.08:25:51.42#ibcon#about to write, iclass 6, count 2 2006.253.08:25:51.42#ibcon#wrote, iclass 6, count 2 2006.253.08:25:51.42#ibcon#about to read 3, iclass 6, count 2 2006.253.08:25:51.45#ibcon#read 3, iclass 6, count 2 2006.253.08:25:51.45#ibcon#about to read 4, iclass 6, count 2 2006.253.08:25:51.45#ibcon#read 4, iclass 6, count 2 2006.253.08:25:51.45#ibcon#about to read 5, iclass 6, count 2 2006.253.08:25:51.45#ibcon#read 5, iclass 6, count 2 2006.253.08:25:51.45#ibcon#about to read 6, iclass 6, count 2 2006.253.08:25:51.45#ibcon#read 6, iclass 6, count 2 2006.253.08:25:51.45#ibcon#end of sib2, iclass 6, count 2 2006.253.08:25:51.45#ibcon#*after write, iclass 6, count 2 2006.253.08:25:51.45#ibcon#*before return 0, iclass 6, count 2 2006.253.08:25:51.45#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.253.08:25:51.45#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.253.08:25:51.45#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.253.08:25:51.45#ibcon#ireg 7 cls_cnt 0 2006.253.08:25:51.45#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.253.08:25:51.57#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.253.08:25:51.57#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.253.08:25:51.57#ibcon#enter wrdev, iclass 6, count 0 2006.253.08:25:51.57#ibcon#first serial, iclass 6, count 0 2006.253.08:25:51.57#ibcon#enter sib2, iclass 6, count 0 2006.253.08:25:51.57#ibcon#flushed, iclass 6, count 0 2006.253.08:25:51.57#ibcon#about to write, iclass 6, count 0 2006.253.08:25:51.57#ibcon#wrote, iclass 6, count 0 2006.253.08:25:51.57#ibcon#about to read 3, iclass 6, count 0 2006.253.08:25:51.59#ibcon#read 3, iclass 6, count 0 2006.253.08:25:51.59#ibcon#about to read 4, iclass 6, count 0 2006.253.08:25:51.59#ibcon#read 4, iclass 6, count 0 2006.253.08:25:51.59#ibcon#about to read 5, iclass 6, count 0 2006.253.08:25:51.59#ibcon#read 5, iclass 6, count 0 2006.253.08:25:51.59#ibcon#about to read 6, iclass 6, count 0 2006.253.08:25:51.59#ibcon#read 6, iclass 6, count 0 2006.253.08:25:51.59#ibcon#end of sib2, iclass 6, count 0 2006.253.08:25:51.59#ibcon#*mode == 0, iclass 6, count 0 2006.253.08:25:51.59#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.253.08:25:51.59#ibcon#[27=USB\r\n] 2006.253.08:25:51.59#ibcon#*before write, iclass 6, count 0 2006.253.08:25:51.59#ibcon#enter sib2, iclass 6, count 0 2006.253.08:25:51.59#ibcon#flushed, iclass 6, count 0 2006.253.08:25:51.59#ibcon#about to write, iclass 6, count 0 2006.253.08:25:51.59#ibcon#wrote, iclass 6, count 0 2006.253.08:25:51.59#ibcon#about to read 3, iclass 6, count 0 2006.253.08:25:51.62#ibcon#read 3, iclass 6, count 0 2006.253.08:25:51.62#ibcon#about to read 4, iclass 6, count 0 2006.253.08:25:51.62#ibcon#read 4, iclass 6, count 0 2006.253.08:25:51.62#ibcon#about to read 5, iclass 6, count 0 2006.253.08:25:51.62#ibcon#read 5, iclass 6, count 0 2006.253.08:25:51.62#ibcon#about to read 6, iclass 6, count 0 2006.253.08:25:51.62#ibcon#read 6, iclass 6, count 0 2006.253.08:25:51.62#ibcon#end of sib2, iclass 6, count 0 2006.253.08:25:51.62#ibcon#*after write, iclass 6, count 0 2006.253.08:25:51.62#ibcon#*before return 0, iclass 6, count 0 2006.253.08:25:51.62#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.253.08:25:51.62#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.253.08:25:51.62#ibcon#about to clear, iclass 6 cls_cnt 0 2006.253.08:25:51.62#ibcon#cleared, iclass 6 cls_cnt 0 2006.253.08:25:51.62$vc4f8/vblo=4,712.99 2006.253.08:25:51.62#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.253.08:25:51.62#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.253.08:25:51.62#ibcon#ireg 17 cls_cnt 0 2006.253.08:25:51.62#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.253.08:25:51.62#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.253.08:25:51.62#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.253.08:25:51.62#ibcon#enter wrdev, iclass 10, count 0 2006.253.08:25:51.62#ibcon#first serial, iclass 10, count 0 2006.253.08:25:51.62#ibcon#enter sib2, iclass 10, count 0 2006.253.08:25:51.62#ibcon#flushed, iclass 10, count 0 2006.253.08:25:51.62#ibcon#about to write, iclass 10, count 0 2006.253.08:25:51.62#ibcon#wrote, iclass 10, count 0 2006.253.08:25:51.62#ibcon#about to read 3, iclass 10, count 0 2006.253.08:25:51.64#ibcon#read 3, iclass 10, count 0 2006.253.08:25:51.64#ibcon#about to read 4, iclass 10, count 0 2006.253.08:25:51.64#ibcon#read 4, iclass 10, count 0 2006.253.08:25:51.64#ibcon#about to read 5, iclass 10, count 0 2006.253.08:25:51.64#ibcon#read 5, iclass 10, count 0 2006.253.08:25:51.64#ibcon#about to read 6, iclass 10, count 0 2006.253.08:25:51.64#ibcon#read 6, iclass 10, count 0 2006.253.08:25:51.64#ibcon#end of sib2, iclass 10, count 0 2006.253.08:25:51.64#ibcon#*mode == 0, iclass 10, count 0 2006.253.08:25:51.64#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.253.08:25:51.64#ibcon#[28=FRQ=04,712.99\r\n] 2006.253.08:25:51.64#ibcon#*before write, iclass 10, count 0 2006.253.08:25:51.64#ibcon#enter sib2, iclass 10, count 0 2006.253.08:25:51.64#ibcon#flushed, iclass 10, count 0 2006.253.08:25:51.64#ibcon#about to write, iclass 10, count 0 2006.253.08:25:51.64#ibcon#wrote, iclass 10, count 0 2006.253.08:25:51.64#ibcon#about to read 3, iclass 10, count 0 2006.253.08:25:51.68#ibcon#read 3, iclass 10, count 0 2006.253.08:25:51.68#ibcon#about to read 4, iclass 10, count 0 2006.253.08:25:51.68#ibcon#read 4, iclass 10, count 0 2006.253.08:25:51.68#ibcon#about to read 5, iclass 10, count 0 2006.253.08:25:51.68#ibcon#read 5, iclass 10, count 0 2006.253.08:25:51.68#ibcon#about to read 6, iclass 10, count 0 2006.253.08:25:51.68#ibcon#read 6, iclass 10, count 0 2006.253.08:25:51.68#ibcon#end of sib2, iclass 10, count 0 2006.253.08:25:51.68#ibcon#*after write, iclass 10, count 0 2006.253.08:25:51.68#ibcon#*before return 0, iclass 10, count 0 2006.253.08:25:51.68#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.253.08:25:51.68#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.253.08:25:51.68#ibcon#about to clear, iclass 10 cls_cnt 0 2006.253.08:25:51.68#ibcon#cleared, iclass 10 cls_cnt 0 2006.253.08:25:51.68$vc4f8/vb=4,4 2006.253.08:25:51.68#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.253.08:25:51.68#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.253.08:25:51.68#ibcon#ireg 11 cls_cnt 2 2006.253.08:25:51.68#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.253.08:25:51.75#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.253.08:25:51.75#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.253.08:25:51.75#ibcon#enter wrdev, iclass 12, count 2 2006.253.08:25:51.75#ibcon#first serial, iclass 12, count 2 2006.253.08:25:51.75#ibcon#enter sib2, iclass 12, count 2 2006.253.08:25:51.75#ibcon#flushed, iclass 12, count 2 2006.253.08:25:51.75#ibcon#about to write, iclass 12, count 2 2006.253.08:25:51.75#ibcon#wrote, iclass 12, count 2 2006.253.08:25:51.75#ibcon#about to read 3, iclass 12, count 2 2006.253.08:25:51.76#ibcon#read 3, iclass 12, count 2 2006.253.08:25:51.76#ibcon#about to read 4, iclass 12, count 2 2006.253.08:25:51.76#ibcon#read 4, iclass 12, count 2 2006.253.08:25:51.76#ibcon#about to read 5, iclass 12, count 2 2006.253.08:25:51.76#ibcon#read 5, iclass 12, count 2 2006.253.08:25:51.76#ibcon#about to read 6, iclass 12, count 2 2006.253.08:25:51.76#ibcon#read 6, iclass 12, count 2 2006.253.08:25:51.76#ibcon#end of sib2, iclass 12, count 2 2006.253.08:25:51.76#ibcon#*mode == 0, iclass 12, count 2 2006.253.08:25:51.76#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.253.08:25:51.76#ibcon#[27=AT04-04\r\n] 2006.253.08:25:51.76#ibcon#*before write, iclass 12, count 2 2006.253.08:25:51.76#ibcon#enter sib2, iclass 12, count 2 2006.253.08:25:51.76#ibcon#flushed, iclass 12, count 2 2006.253.08:25:51.76#ibcon#about to write, iclass 12, count 2 2006.253.08:25:51.76#ibcon#wrote, iclass 12, count 2 2006.253.08:25:51.76#ibcon#about to read 3, iclass 12, count 2 2006.253.08:25:51.79#ibcon#read 3, iclass 12, count 2 2006.253.08:25:51.79#ibcon#about to read 4, iclass 12, count 2 2006.253.08:25:51.79#ibcon#read 4, iclass 12, count 2 2006.253.08:25:51.79#ibcon#about to read 5, iclass 12, count 2 2006.253.08:25:51.79#ibcon#read 5, iclass 12, count 2 2006.253.08:25:51.79#ibcon#about to read 6, iclass 12, count 2 2006.253.08:25:51.79#ibcon#read 6, iclass 12, count 2 2006.253.08:25:51.79#ibcon#end of sib2, iclass 12, count 2 2006.253.08:25:51.79#ibcon#*after write, iclass 12, count 2 2006.253.08:25:51.79#ibcon#*before return 0, iclass 12, count 2 2006.253.08:25:51.79#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.253.08:25:51.79#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.253.08:25:51.79#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.253.08:25:51.79#ibcon#ireg 7 cls_cnt 0 2006.253.08:25:51.79#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.253.08:25:51.91#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.253.08:25:51.91#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.253.08:25:51.91#ibcon#enter wrdev, iclass 12, count 0 2006.253.08:25:51.91#ibcon#first serial, iclass 12, count 0 2006.253.08:25:51.91#ibcon#enter sib2, iclass 12, count 0 2006.253.08:25:51.91#ibcon#flushed, iclass 12, count 0 2006.253.08:25:51.91#ibcon#about to write, iclass 12, count 0 2006.253.08:25:51.91#ibcon#wrote, iclass 12, count 0 2006.253.08:25:51.91#ibcon#about to read 3, iclass 12, count 0 2006.253.08:25:51.93#ibcon#read 3, iclass 12, count 0 2006.253.08:25:51.93#ibcon#about to read 4, iclass 12, count 0 2006.253.08:25:51.93#ibcon#read 4, iclass 12, count 0 2006.253.08:25:51.93#ibcon#about to read 5, iclass 12, count 0 2006.253.08:25:51.93#ibcon#read 5, iclass 12, count 0 2006.253.08:25:51.93#ibcon#about to read 6, iclass 12, count 0 2006.253.08:25:51.93#ibcon#read 6, iclass 12, count 0 2006.253.08:25:51.93#ibcon#end of sib2, iclass 12, count 0 2006.253.08:25:51.93#ibcon#*mode == 0, iclass 12, count 0 2006.253.08:25:51.93#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.253.08:25:51.93#ibcon#[27=USB\r\n] 2006.253.08:25:51.93#ibcon#*before write, iclass 12, count 0 2006.253.08:25:51.93#ibcon#enter sib2, iclass 12, count 0 2006.253.08:25:51.93#ibcon#flushed, iclass 12, count 0 2006.253.08:25:51.93#ibcon#about to write, iclass 12, count 0 2006.253.08:25:51.93#ibcon#wrote, iclass 12, count 0 2006.253.08:25:51.93#ibcon#about to read 3, iclass 12, count 0 2006.253.08:25:51.96#ibcon#read 3, iclass 12, count 0 2006.253.08:25:51.96#ibcon#about to read 4, iclass 12, count 0 2006.253.08:25:51.96#ibcon#read 4, iclass 12, count 0 2006.253.08:25:51.96#ibcon#about to read 5, iclass 12, count 0 2006.253.08:25:51.96#ibcon#read 5, iclass 12, count 0 2006.253.08:25:51.96#ibcon#about to read 6, iclass 12, count 0 2006.253.08:25:51.96#ibcon#read 6, iclass 12, count 0 2006.253.08:25:51.96#ibcon#end of sib2, iclass 12, count 0 2006.253.08:25:51.96#ibcon#*after write, iclass 12, count 0 2006.253.08:25:51.96#ibcon#*before return 0, iclass 12, count 0 2006.253.08:25:51.96#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.253.08:25:51.96#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.253.08:25:51.96#ibcon#about to clear, iclass 12 cls_cnt 0 2006.253.08:25:51.96#ibcon#cleared, iclass 12 cls_cnt 0 2006.253.08:25:51.96$vc4f8/vblo=5,744.99 2006.253.08:25:51.96#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.253.08:25:51.96#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.253.08:25:51.96#ibcon#ireg 17 cls_cnt 0 2006.253.08:25:51.96#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.253.08:25:51.96#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.253.08:25:51.96#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.253.08:25:51.96#ibcon#enter wrdev, iclass 14, count 0 2006.253.08:25:51.96#ibcon#first serial, iclass 14, count 0 2006.253.08:25:51.96#ibcon#enter sib2, iclass 14, count 0 2006.253.08:25:51.96#ibcon#flushed, iclass 14, count 0 2006.253.08:25:51.96#ibcon#about to write, iclass 14, count 0 2006.253.08:25:51.96#ibcon#wrote, iclass 14, count 0 2006.253.08:25:51.96#ibcon#about to read 3, iclass 14, count 0 2006.253.08:25:51.98#ibcon#read 3, iclass 14, count 0 2006.253.08:25:51.98#ibcon#about to read 4, iclass 14, count 0 2006.253.08:25:51.98#ibcon#read 4, iclass 14, count 0 2006.253.08:25:51.98#ibcon#about to read 5, iclass 14, count 0 2006.253.08:25:51.98#ibcon#read 5, iclass 14, count 0 2006.253.08:25:51.98#ibcon#about to read 6, iclass 14, count 0 2006.253.08:25:51.98#ibcon#read 6, iclass 14, count 0 2006.253.08:25:51.98#ibcon#end of sib2, iclass 14, count 0 2006.253.08:25:51.98#ibcon#*mode == 0, iclass 14, count 0 2006.253.08:25:51.98#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.253.08:25:51.98#ibcon#[28=FRQ=05,744.99\r\n] 2006.253.08:25:51.98#ibcon#*before write, iclass 14, count 0 2006.253.08:25:51.98#ibcon#enter sib2, iclass 14, count 0 2006.253.08:25:51.98#ibcon#flushed, iclass 14, count 0 2006.253.08:25:51.98#ibcon#about to write, iclass 14, count 0 2006.253.08:25:51.98#ibcon#wrote, iclass 14, count 0 2006.253.08:25:51.98#ibcon#about to read 3, iclass 14, count 0 2006.253.08:25:52.02#ibcon#read 3, iclass 14, count 0 2006.253.08:25:52.02#ibcon#about to read 4, iclass 14, count 0 2006.253.08:25:52.02#ibcon#read 4, iclass 14, count 0 2006.253.08:25:52.02#ibcon#about to read 5, iclass 14, count 0 2006.253.08:25:52.02#ibcon#read 5, iclass 14, count 0 2006.253.08:25:52.02#ibcon#about to read 6, iclass 14, count 0 2006.253.08:25:52.02#ibcon#read 6, iclass 14, count 0 2006.253.08:25:52.02#ibcon#end of sib2, iclass 14, count 0 2006.253.08:25:52.02#ibcon#*after write, iclass 14, count 0 2006.253.08:25:52.02#ibcon#*before return 0, iclass 14, count 0 2006.253.08:25:52.02#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.253.08:25:52.02#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.253.08:25:52.02#ibcon#about to clear, iclass 14 cls_cnt 0 2006.253.08:25:52.02#ibcon#cleared, iclass 14 cls_cnt 0 2006.253.08:25:52.02$vc4f8/vb=5,4 2006.253.08:25:52.02#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.253.08:25:52.02#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.253.08:25:52.02#ibcon#ireg 11 cls_cnt 2 2006.253.08:25:52.02#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.253.08:25:52.09#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.253.08:25:52.09#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.253.08:25:52.09#ibcon#enter wrdev, iclass 16, count 2 2006.253.08:25:52.09#ibcon#first serial, iclass 16, count 2 2006.253.08:25:52.09#ibcon#enter sib2, iclass 16, count 2 2006.253.08:25:52.09#ibcon#flushed, iclass 16, count 2 2006.253.08:25:52.09#ibcon#about to write, iclass 16, count 2 2006.253.08:25:52.09#ibcon#wrote, iclass 16, count 2 2006.253.08:25:52.09#ibcon#about to read 3, iclass 16, count 2 2006.253.08:25:52.10#ibcon#read 3, iclass 16, count 2 2006.253.08:25:52.10#ibcon#about to read 4, iclass 16, count 2 2006.253.08:25:52.10#ibcon#read 4, iclass 16, count 2 2006.253.08:25:52.10#ibcon#about to read 5, iclass 16, count 2 2006.253.08:25:52.10#ibcon#read 5, iclass 16, count 2 2006.253.08:25:52.10#ibcon#about to read 6, iclass 16, count 2 2006.253.08:25:52.10#ibcon#read 6, iclass 16, count 2 2006.253.08:25:52.10#ibcon#end of sib2, iclass 16, count 2 2006.253.08:25:52.10#ibcon#*mode == 0, iclass 16, count 2 2006.253.08:25:52.10#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.253.08:25:52.10#ibcon#[27=AT05-04\r\n] 2006.253.08:25:52.10#ibcon#*before write, iclass 16, count 2 2006.253.08:25:52.10#ibcon#enter sib2, iclass 16, count 2 2006.253.08:25:52.10#ibcon#flushed, iclass 16, count 2 2006.253.08:25:52.10#ibcon#about to write, iclass 16, count 2 2006.253.08:25:52.10#ibcon#wrote, iclass 16, count 2 2006.253.08:25:52.10#ibcon#about to read 3, iclass 16, count 2 2006.253.08:25:52.13#ibcon#read 3, iclass 16, count 2 2006.253.08:25:52.13#ibcon#about to read 4, iclass 16, count 2 2006.253.08:25:52.13#ibcon#read 4, iclass 16, count 2 2006.253.08:25:52.13#ibcon#about to read 5, iclass 16, count 2 2006.253.08:25:52.13#ibcon#read 5, iclass 16, count 2 2006.253.08:25:52.13#ibcon#about to read 6, iclass 16, count 2 2006.253.08:25:52.13#ibcon#read 6, iclass 16, count 2 2006.253.08:25:52.13#ibcon#end of sib2, iclass 16, count 2 2006.253.08:25:52.13#ibcon#*after write, iclass 16, count 2 2006.253.08:25:52.13#ibcon#*before return 0, iclass 16, count 2 2006.253.08:25:52.13#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.253.08:25:52.13#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.253.08:25:52.13#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.253.08:25:52.13#ibcon#ireg 7 cls_cnt 0 2006.253.08:25:52.13#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.253.08:25:52.25#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.253.08:25:52.25#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.253.08:25:52.25#ibcon#enter wrdev, iclass 16, count 0 2006.253.08:25:52.25#ibcon#first serial, iclass 16, count 0 2006.253.08:25:52.25#ibcon#enter sib2, iclass 16, count 0 2006.253.08:25:52.25#ibcon#flushed, iclass 16, count 0 2006.253.08:25:52.25#ibcon#about to write, iclass 16, count 0 2006.253.08:25:52.25#ibcon#wrote, iclass 16, count 0 2006.253.08:25:52.25#ibcon#about to read 3, iclass 16, count 0 2006.253.08:25:52.27#ibcon#read 3, iclass 16, count 0 2006.253.08:25:52.27#ibcon#about to read 4, iclass 16, count 0 2006.253.08:25:52.27#ibcon#read 4, iclass 16, count 0 2006.253.08:25:52.27#ibcon#about to read 5, iclass 16, count 0 2006.253.08:25:52.27#ibcon#read 5, iclass 16, count 0 2006.253.08:25:52.27#ibcon#about to read 6, iclass 16, count 0 2006.253.08:25:52.27#ibcon#read 6, iclass 16, count 0 2006.253.08:25:52.27#ibcon#end of sib2, iclass 16, count 0 2006.253.08:25:52.27#ibcon#*mode == 0, iclass 16, count 0 2006.253.08:25:52.27#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.253.08:25:52.27#ibcon#[27=USB\r\n] 2006.253.08:25:52.27#ibcon#*before write, iclass 16, count 0 2006.253.08:25:52.27#ibcon#enter sib2, iclass 16, count 0 2006.253.08:25:52.27#ibcon#flushed, iclass 16, count 0 2006.253.08:25:52.27#ibcon#about to write, iclass 16, count 0 2006.253.08:25:52.27#ibcon#wrote, iclass 16, count 0 2006.253.08:25:52.27#ibcon#about to read 3, iclass 16, count 0 2006.253.08:25:52.30#ibcon#read 3, iclass 16, count 0 2006.253.08:25:52.30#ibcon#about to read 4, iclass 16, count 0 2006.253.08:25:52.30#ibcon#read 4, iclass 16, count 0 2006.253.08:25:52.30#ibcon#about to read 5, iclass 16, count 0 2006.253.08:25:52.30#ibcon#read 5, iclass 16, count 0 2006.253.08:25:52.30#ibcon#about to read 6, iclass 16, count 0 2006.253.08:25:52.30#ibcon#read 6, iclass 16, count 0 2006.253.08:25:52.30#ibcon#end of sib2, iclass 16, count 0 2006.253.08:25:52.30#ibcon#*after write, iclass 16, count 0 2006.253.08:25:52.30#ibcon#*before return 0, iclass 16, count 0 2006.253.08:25:52.30#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.253.08:25:52.30#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.253.08:25:52.30#ibcon#about to clear, iclass 16 cls_cnt 0 2006.253.08:25:52.30#ibcon#cleared, iclass 16 cls_cnt 0 2006.253.08:25:52.30$vc4f8/vblo=6,752.99 2006.253.08:25:52.30#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.253.08:25:52.30#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.253.08:25:52.30#ibcon#ireg 17 cls_cnt 0 2006.253.08:25:52.30#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.253.08:25:52.30#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.253.08:25:52.30#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.253.08:25:52.30#ibcon#enter wrdev, iclass 18, count 0 2006.253.08:25:52.30#ibcon#first serial, iclass 18, count 0 2006.253.08:25:52.30#ibcon#enter sib2, iclass 18, count 0 2006.253.08:25:52.30#ibcon#flushed, iclass 18, count 0 2006.253.08:25:52.30#ibcon#about to write, iclass 18, count 0 2006.253.08:25:52.30#ibcon#wrote, iclass 18, count 0 2006.253.08:25:52.30#ibcon#about to read 3, iclass 18, count 0 2006.253.08:25:52.32#ibcon#read 3, iclass 18, count 0 2006.253.08:25:52.32#ibcon#about to read 4, iclass 18, count 0 2006.253.08:25:52.32#ibcon#read 4, iclass 18, count 0 2006.253.08:25:52.32#ibcon#about to read 5, iclass 18, count 0 2006.253.08:25:52.32#ibcon#read 5, iclass 18, count 0 2006.253.08:25:52.32#ibcon#about to read 6, iclass 18, count 0 2006.253.08:25:52.32#ibcon#read 6, iclass 18, count 0 2006.253.08:25:52.32#ibcon#end of sib2, iclass 18, count 0 2006.253.08:25:52.32#ibcon#*mode == 0, iclass 18, count 0 2006.253.08:25:52.32#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.253.08:25:52.32#ibcon#[28=FRQ=06,752.99\r\n] 2006.253.08:25:52.32#ibcon#*before write, iclass 18, count 0 2006.253.08:25:52.32#ibcon#enter sib2, iclass 18, count 0 2006.253.08:25:52.32#ibcon#flushed, iclass 18, count 0 2006.253.08:25:52.32#ibcon#about to write, iclass 18, count 0 2006.253.08:25:52.32#ibcon#wrote, iclass 18, count 0 2006.253.08:25:52.32#ibcon#about to read 3, iclass 18, count 0 2006.253.08:25:52.36#ibcon#read 3, iclass 18, count 0 2006.253.08:25:52.36#ibcon#about to read 4, iclass 18, count 0 2006.253.08:25:52.36#ibcon#read 4, iclass 18, count 0 2006.253.08:25:52.36#ibcon#about to read 5, iclass 18, count 0 2006.253.08:25:52.36#ibcon#read 5, iclass 18, count 0 2006.253.08:25:52.36#ibcon#about to read 6, iclass 18, count 0 2006.253.08:25:52.36#ibcon#read 6, iclass 18, count 0 2006.253.08:25:52.36#ibcon#end of sib2, iclass 18, count 0 2006.253.08:25:52.36#ibcon#*after write, iclass 18, count 0 2006.253.08:25:52.36#ibcon#*before return 0, iclass 18, count 0 2006.253.08:25:52.36#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.253.08:25:52.36#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.253.08:25:52.36#ibcon#about to clear, iclass 18 cls_cnt 0 2006.253.08:25:52.36#ibcon#cleared, iclass 18 cls_cnt 0 2006.253.08:25:52.36$vc4f8/vb=6,4 2006.253.08:25:52.36#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.253.08:25:52.36#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.253.08:25:52.36#ibcon#ireg 11 cls_cnt 2 2006.253.08:25:52.36#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.253.08:25:52.42#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.253.08:25:52.42#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.253.08:25:52.42#ibcon#enter wrdev, iclass 20, count 2 2006.253.08:25:52.42#ibcon#first serial, iclass 20, count 2 2006.253.08:25:52.42#ibcon#enter sib2, iclass 20, count 2 2006.253.08:25:52.42#ibcon#flushed, iclass 20, count 2 2006.253.08:25:52.42#ibcon#about to write, iclass 20, count 2 2006.253.08:25:52.42#ibcon#wrote, iclass 20, count 2 2006.253.08:25:52.42#ibcon#about to read 3, iclass 20, count 2 2006.253.08:25:52.44#ibcon#read 3, iclass 20, count 2 2006.253.08:25:52.44#ibcon#about to read 4, iclass 20, count 2 2006.253.08:25:52.44#ibcon#read 4, iclass 20, count 2 2006.253.08:25:52.44#ibcon#about to read 5, iclass 20, count 2 2006.253.08:25:52.44#ibcon#read 5, iclass 20, count 2 2006.253.08:25:52.44#ibcon#about to read 6, iclass 20, count 2 2006.253.08:25:52.44#ibcon#read 6, iclass 20, count 2 2006.253.08:25:52.44#ibcon#end of sib2, iclass 20, count 2 2006.253.08:25:52.44#ibcon#*mode == 0, iclass 20, count 2 2006.253.08:25:52.44#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.253.08:25:52.44#ibcon#[27=AT06-04\r\n] 2006.253.08:25:52.44#ibcon#*before write, iclass 20, count 2 2006.253.08:25:52.44#ibcon#enter sib2, iclass 20, count 2 2006.253.08:25:52.44#ibcon#flushed, iclass 20, count 2 2006.253.08:25:52.44#ibcon#about to write, iclass 20, count 2 2006.253.08:25:52.44#ibcon#wrote, iclass 20, count 2 2006.253.08:25:52.44#ibcon#about to read 3, iclass 20, count 2 2006.253.08:25:52.47#ibcon#read 3, iclass 20, count 2 2006.253.08:25:52.47#ibcon#about to read 4, iclass 20, count 2 2006.253.08:25:52.47#ibcon#read 4, iclass 20, count 2 2006.253.08:25:52.47#ibcon#about to read 5, iclass 20, count 2 2006.253.08:25:52.47#ibcon#read 5, iclass 20, count 2 2006.253.08:25:52.47#ibcon#about to read 6, iclass 20, count 2 2006.253.08:25:52.47#ibcon#read 6, iclass 20, count 2 2006.253.08:25:52.47#ibcon#end of sib2, iclass 20, count 2 2006.253.08:25:52.47#ibcon#*after write, iclass 20, count 2 2006.253.08:25:52.47#ibcon#*before return 0, iclass 20, count 2 2006.253.08:25:52.47#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.253.08:25:52.47#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.253.08:25:52.47#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.253.08:25:52.47#ibcon#ireg 7 cls_cnt 0 2006.253.08:25:52.47#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.253.08:25:52.59#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.253.08:25:52.59#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.253.08:25:52.59#ibcon#enter wrdev, iclass 20, count 0 2006.253.08:25:52.59#ibcon#first serial, iclass 20, count 0 2006.253.08:25:52.59#ibcon#enter sib2, iclass 20, count 0 2006.253.08:25:52.59#ibcon#flushed, iclass 20, count 0 2006.253.08:25:52.59#ibcon#about to write, iclass 20, count 0 2006.253.08:25:52.59#ibcon#wrote, iclass 20, count 0 2006.253.08:25:52.59#ibcon#about to read 3, iclass 20, count 0 2006.253.08:25:52.61#ibcon#read 3, iclass 20, count 0 2006.253.08:25:52.61#ibcon#about to read 4, iclass 20, count 0 2006.253.08:25:52.61#ibcon#read 4, iclass 20, count 0 2006.253.08:25:52.61#ibcon#about to read 5, iclass 20, count 0 2006.253.08:25:52.61#ibcon#read 5, iclass 20, count 0 2006.253.08:25:52.61#ibcon#about to read 6, iclass 20, count 0 2006.253.08:25:52.61#ibcon#read 6, iclass 20, count 0 2006.253.08:25:52.61#ibcon#end of sib2, iclass 20, count 0 2006.253.08:25:52.61#ibcon#*mode == 0, iclass 20, count 0 2006.253.08:25:52.61#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.253.08:25:52.61#ibcon#[27=USB\r\n] 2006.253.08:25:52.61#ibcon#*before write, iclass 20, count 0 2006.253.08:25:52.61#ibcon#enter sib2, iclass 20, count 0 2006.253.08:25:52.61#ibcon#flushed, iclass 20, count 0 2006.253.08:25:52.61#ibcon#about to write, iclass 20, count 0 2006.253.08:25:52.61#ibcon#wrote, iclass 20, count 0 2006.253.08:25:52.61#ibcon#about to read 3, iclass 20, count 0 2006.253.08:25:52.64#ibcon#read 3, iclass 20, count 0 2006.253.08:25:52.64#ibcon#about to read 4, iclass 20, count 0 2006.253.08:25:52.64#ibcon#read 4, iclass 20, count 0 2006.253.08:25:52.64#ibcon#about to read 5, iclass 20, count 0 2006.253.08:25:52.64#ibcon#read 5, iclass 20, count 0 2006.253.08:25:52.64#ibcon#about to read 6, iclass 20, count 0 2006.253.08:25:52.64#ibcon#read 6, iclass 20, count 0 2006.253.08:25:52.64#ibcon#end of sib2, iclass 20, count 0 2006.253.08:25:52.64#ibcon#*after write, iclass 20, count 0 2006.253.08:25:52.64#ibcon#*before return 0, iclass 20, count 0 2006.253.08:25:52.64#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.253.08:25:52.64#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.253.08:25:52.64#ibcon#about to clear, iclass 20 cls_cnt 0 2006.253.08:25:52.64#ibcon#cleared, iclass 20 cls_cnt 0 2006.253.08:25:52.64$vc4f8/vabw=wide 2006.253.08:25:52.64#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.253.08:25:52.64#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.253.08:25:52.64#ibcon#ireg 8 cls_cnt 0 2006.253.08:25:52.64#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.253.08:25:52.64#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.253.08:25:52.64#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.253.08:25:52.64#ibcon#enter wrdev, iclass 22, count 0 2006.253.08:25:52.64#ibcon#first serial, iclass 22, count 0 2006.253.08:25:52.64#ibcon#enter sib2, iclass 22, count 0 2006.253.08:25:52.64#ibcon#flushed, iclass 22, count 0 2006.253.08:25:52.64#ibcon#about to write, iclass 22, count 0 2006.253.08:25:52.64#ibcon#wrote, iclass 22, count 0 2006.253.08:25:52.64#ibcon#about to read 3, iclass 22, count 0 2006.253.08:25:52.66#ibcon#read 3, iclass 22, count 0 2006.253.08:25:52.66#ibcon#about to read 4, iclass 22, count 0 2006.253.08:25:52.66#ibcon#read 4, iclass 22, count 0 2006.253.08:25:52.66#ibcon#about to read 5, iclass 22, count 0 2006.253.08:25:52.66#ibcon#read 5, iclass 22, count 0 2006.253.08:25:52.66#ibcon#about to read 6, iclass 22, count 0 2006.253.08:25:52.66#ibcon#read 6, iclass 22, count 0 2006.253.08:25:52.66#ibcon#end of sib2, iclass 22, count 0 2006.253.08:25:52.66#ibcon#*mode == 0, iclass 22, count 0 2006.253.08:25:52.66#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.253.08:25:52.66#ibcon#[25=BW32\r\n] 2006.253.08:25:52.66#ibcon#*before write, iclass 22, count 0 2006.253.08:25:52.66#ibcon#enter sib2, iclass 22, count 0 2006.253.08:25:52.66#ibcon#flushed, iclass 22, count 0 2006.253.08:25:52.66#ibcon#about to write, iclass 22, count 0 2006.253.08:25:52.66#ibcon#wrote, iclass 22, count 0 2006.253.08:25:52.66#ibcon#about to read 3, iclass 22, count 0 2006.253.08:25:52.69#ibcon#read 3, iclass 22, count 0 2006.253.08:25:52.69#ibcon#about to read 4, iclass 22, count 0 2006.253.08:25:52.69#ibcon#read 4, iclass 22, count 0 2006.253.08:25:52.69#ibcon#about to read 5, iclass 22, count 0 2006.253.08:25:52.69#ibcon#read 5, iclass 22, count 0 2006.253.08:25:52.69#ibcon#about to read 6, iclass 22, count 0 2006.253.08:25:52.69#ibcon#read 6, iclass 22, count 0 2006.253.08:25:52.69#ibcon#end of sib2, iclass 22, count 0 2006.253.08:25:52.69#ibcon#*after write, iclass 22, count 0 2006.253.08:25:52.69#ibcon#*before return 0, iclass 22, count 0 2006.253.08:25:52.69#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.253.08:25:52.69#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.253.08:25:52.69#ibcon#about to clear, iclass 22 cls_cnt 0 2006.253.08:25:52.69#ibcon#cleared, iclass 22 cls_cnt 0 2006.253.08:25:52.69$vc4f8/vbbw=wide 2006.253.08:25:52.69#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.253.08:25:52.69#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.253.08:25:52.69#ibcon#ireg 8 cls_cnt 0 2006.253.08:25:52.69#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.253.08:25:52.77#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.253.08:25:52.77#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.253.08:25:52.77#ibcon#enter wrdev, iclass 24, count 0 2006.253.08:25:52.77#ibcon#first serial, iclass 24, count 0 2006.253.08:25:52.77#ibcon#enter sib2, iclass 24, count 0 2006.253.08:25:52.77#ibcon#flushed, iclass 24, count 0 2006.253.08:25:52.77#ibcon#about to write, iclass 24, count 0 2006.253.08:25:52.77#ibcon#wrote, iclass 24, count 0 2006.253.08:25:52.77#ibcon#about to read 3, iclass 24, count 0 2006.253.08:25:52.78#ibcon#read 3, iclass 24, count 0 2006.253.08:25:52.78#ibcon#about to read 4, iclass 24, count 0 2006.253.08:25:52.78#ibcon#read 4, iclass 24, count 0 2006.253.08:25:52.78#ibcon#about to read 5, iclass 24, count 0 2006.253.08:25:52.78#ibcon#read 5, iclass 24, count 0 2006.253.08:25:52.78#ibcon#about to read 6, iclass 24, count 0 2006.253.08:25:52.78#ibcon#read 6, iclass 24, count 0 2006.253.08:25:52.78#ibcon#end of sib2, iclass 24, count 0 2006.253.08:25:52.78#ibcon#*mode == 0, iclass 24, count 0 2006.253.08:25:52.78#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.253.08:25:52.78#ibcon#[27=BW32\r\n] 2006.253.08:25:52.78#ibcon#*before write, iclass 24, count 0 2006.253.08:25:52.78#ibcon#enter sib2, iclass 24, count 0 2006.253.08:25:52.78#ibcon#flushed, iclass 24, count 0 2006.253.08:25:52.78#ibcon#about to write, iclass 24, count 0 2006.253.08:25:52.78#ibcon#wrote, iclass 24, count 0 2006.253.08:25:52.78#ibcon#about to read 3, iclass 24, count 0 2006.253.08:25:52.81#ibcon#read 3, iclass 24, count 0 2006.253.08:25:52.81#ibcon#about to read 4, iclass 24, count 0 2006.253.08:25:52.81#ibcon#read 4, iclass 24, count 0 2006.253.08:25:52.81#ibcon#about to read 5, iclass 24, count 0 2006.253.08:25:52.81#ibcon#read 5, iclass 24, count 0 2006.253.08:25:52.81#ibcon#about to read 6, iclass 24, count 0 2006.253.08:25:52.81#ibcon#read 6, iclass 24, count 0 2006.253.08:25:52.81#ibcon#end of sib2, iclass 24, count 0 2006.253.08:25:52.81#ibcon#*after write, iclass 24, count 0 2006.253.08:25:52.81#ibcon#*before return 0, iclass 24, count 0 2006.253.08:25:52.81#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.253.08:25:52.81#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.253.08:25:52.81#ibcon#about to clear, iclass 24 cls_cnt 0 2006.253.08:25:52.81#ibcon#cleared, iclass 24 cls_cnt 0 2006.253.08:25:52.81$4f8m12a/ifd4f 2006.253.08:25:52.81$ifd4f/lo= 2006.253.08:25:52.81$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.253.08:25:52.81$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.253.08:25:52.81$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.253.08:25:52.81$ifd4f/patch= 2006.253.08:25:52.81$ifd4f/patch=lo1,a1,a2,a3,a4 2006.253.08:25:52.81$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.253.08:25:52.82$ifd4f/patch=lo3,a5,a6,a7,a8 2006.253.08:25:52.82$4f8m12a/"form=m,16.000,1:2 2006.253.08:25:52.82$4f8m12a/"tpicd 2006.253.08:25:52.82$4f8m12a/echo=off 2006.253.08:25:52.82$4f8m12a/xlog=off 2006.253.08:25:52.82:!2006.253.08:26:30 2006.253.08:26:13.14#trakl#Source acquired 2006.253.08:26:13.14#flagr#flagr/antenna,acquired 2006.253.08:26:30.01:preob 2006.253.08:26:31.14/onsource/TRACKING 2006.253.08:26:31.14:!2006.253.08:26:40 2006.253.08:26:40.00:data_valid=on 2006.253.08:26:40.00:midob 2006.253.08:26:40.14/onsource/TRACKING 2006.253.08:26:40.14/wx/30.70,1006.7,75 2006.253.08:26:40.19/cable/+6.3690E-03 2006.253.08:26:41.28/va/01,08,usb,yes,34,35 2006.253.08:26:41.28/va/02,07,usb,yes,34,35 2006.253.08:26:41.28/va/03,06,usb,yes,36,36 2006.253.08:26:41.28/va/04,07,usb,yes,34,37 2006.253.08:26:41.28/va/05,07,usb,yes,36,38 2006.253.08:26:41.28/va/06,07,usb,yes,31,31 2006.253.08:26:41.28/va/07,07,usb,yes,31,31 2006.253.08:26:41.28/va/08,07,usb,yes,34,33 2006.253.08:26:41.51/valo/01,532.99,yes,locked 2006.253.08:26:41.51/valo/02,572.99,yes,locked 2006.253.08:26:41.51/valo/03,672.99,yes,locked 2006.253.08:26:41.51/valo/04,832.99,yes,locked 2006.253.08:26:41.51/valo/05,652.99,yes,locked 2006.253.08:26:41.51/valo/06,772.99,yes,locked 2006.253.08:26:41.51/valo/07,832.99,yes,locked 2006.253.08:26:41.51/valo/08,852.99,yes,locked 2006.253.08:26:42.60/vb/01,04,usb,yes,28,27 2006.253.08:26:42.60/vb/02,05,usb,yes,26,27 2006.253.08:26:42.60/vb/03,04,usb,yes,26,30 2006.253.08:26:42.60/vb/04,04,usb,yes,27,27 2006.253.08:26:42.60/vb/05,04,usb,yes,25,29 2006.253.08:26:42.60/vb/06,04,usb,yes,26,29 2006.253.08:26:42.60/vb/07,04,usb,yes,28,28 2006.253.08:26:42.60/vb/08,04,usb,yes,26,29 2006.253.08:26:42.84/vblo/01,632.99,yes,locked 2006.253.08:26:42.84/vblo/02,640.99,yes,locked 2006.253.08:26:42.84/vblo/03,656.99,yes,locked 2006.253.08:26:42.84/vblo/04,712.99,yes,locked 2006.253.08:26:42.84/vblo/05,744.99,yes,locked 2006.253.08:26:42.84/vblo/06,752.99,yes,locked 2006.253.08:26:42.84/vblo/07,734.99,yes,locked 2006.253.08:26:42.84/vblo/08,744.99,yes,locked 2006.253.08:26:42.99/vabw/8 2006.253.08:26:43.14/vbbw/8 2006.253.08:26:43.23/xfe/off,on,14.2 2006.253.08:26:43.61/ifatt/23,28,28,28 2006.253.08:26:44.07/fmout-gps/S +4.72E-07 2006.253.08:26:44.15:!2006.253.08:27:50 2006.253.08:27:50.00:data_valid=off 2006.253.08:27:50.01:postob 2006.253.08:27:50.15/cable/+6.3675E-03 2006.253.08:27:50.16/wx/30.67,1006.7,76 2006.253.08:27:51.07/fmout-gps/S +4.73E-07 2006.253.08:27:51.08:checkk5last 2006.253.08:27:51.08&checkk5last/chk_obsdata=1 2006.253.08:27:51.08&checkk5last/chk_obsdata=2 2006.253.08:27:51.09&checkk5last/chk_obsdata=3 2006.253.08:27:51.09&checkk5last/chk_obsdata=4 2006.253.08:27:51.09&checkk5last/k5log=1 2006.253.08:27:51.10&checkk5last/k5log=2 2006.253.08:27:51.10&checkk5last/k5log=3 2006.253.08:27:51.10&checkk5last/k5log=4 2006.253.08:27:51.11&checkk5last/obsinfo 2006.253.08:27:51.49/chk_obsdata//k5ts1/T2530826??a.dat file size is correct (nominal:560MB, actual:552MB). 2006.253.08:27:51.86/chk_obsdata//k5ts2/T2530826??b.dat file size is correct (nominal:560MB, actual:552MB). 2006.253.08:27:52.23/chk_obsdata//k5ts3/T2530826??c.dat file size is correct (nominal:560MB, actual:552MB). 2006.253.08:27:52.60/chk_obsdata//k5ts4/T2530826??d.dat file size is correct (nominal:560MB, actual:552MB). 2006.253.08:27:53.31/k5log//k5ts1_log_newline 2006.253.08:27:54.01/k5log//k5ts2_log_newline 2006.253.08:27:54.70/k5log//k5ts3_log_newline 2006.253.08:27:55.39/k5log//k5ts4_log_newline 2006.253.08:27:55.42/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.253.08:27:55.42:sched_end 2006.253.08:27:55.42&sched_end/stopcheck 2006.253.08:27:55.42&stopcheck/sy=killall check_fsrun.pl 2006.253.08:27:55.42&stopcheck/" sy=killall chmem.sh 2006.253.08:27:55.51:source=idle 2006.253.08:27:57.14#flagr#flagr/antenna,new-source 2006.253.08:27:57.15:stow 2006.253.08:27:57.15&stow/source=idle 2006.253.08:27:57.15&stow/"this is stow command. 2006.253.08:27:57.16&stow/antenna=m3 2006.253.08:28:01.01:!+10m 2006.253.08:38:01.03:standby 2006.253.08:38:01.03&standby/"this is standby command. 2006.253.08:38:01.04&standby/antenna=m0 2006.253.08:38:02.01:checkk5hdd 2006.253.08:38:02.01&checkk5hdd/chk_hdd=1 2006.253.08:38:02.02&checkk5hdd/chk_hdd=2 2006.253.08:38:02.02&checkk5hdd/chk_hdd=3 2006.253.08:38:02.02&checkk5hdd/chk_hdd=4 2006.253.08:38:04.84/chk_hdd//k5ts1/GSI00275:T253073000a.dat~T253082640a.dat[13177323520Byte] 2006.253.08:38:07.66/chk_hdd//k5ts2/GSI00163:T253073000b.dat~T253082640b.dat[13177323520Byte] 2006.253.08:38:10.50/chk_hdd//k5ts3/GSI00278:T253073000c.dat~T253082640c.dat[13177323520Byte] 2006.253.08:38:13.30/chk_hdd//k5ts4/GSI00141:T253073000d.dat~T253082640d.dat[13177323520Byte] 2006.253.08:38:13.30:sy=cp /usr2/log/k06253ts.log /usr2/log_backup/ 2006.253.08:38:13.40:*end of schedule