2006.251.08:09:48.42;Log Opened: Mark IV Field System Version 9.7.7 2006.251.08:09:48.42;location,TSUKUB32,-140.09,36.10,61.0 2006.251.08:09:48.42;horizon1,0.,5.,360. 2006.251.08:09:48.42;antenna,32.0,180.0,180.0,10.0,710.0,5.0,88.0,azel 2006.251.08:09:48.42;equip,k42c/mk4,vlbab,vlbab,mk4,500.10,3,a/d,101,60,20,none,41,1,in,8bit,cdp,3 2006.251.08:09:48.42;drivev11,330,270,no 2006.251.08:09:48.42;drivev12,mvme117,0,11.400,2548.000,152.780,-6.655,0.014,152,10.000,54500 2006.251.08:09:48.42;drivev13,15.000,268,10.000,10.000,10.000 2006.251.08:09:48.42;drivev21,330,270,no 2006.251.08:09:48.42;drivev22,mvme117,0,11.500,2821.000,127.500,-8.640,0.015,152,14.000,54500 2006.251.08:09:48.42;drivev23,15.000,268,10.000,10.000,10.000 2006.251.08:09:48.42;head10,all,all,all,odd,adaptive,no,5.0000,1 2006.251.08:09:48.42;head11,131.5,16.4,-291.0,131.5,16.4,0.8,168.30,168.30 2006.251.08:09:48.42;head12,122.8,13.9,-150.8,122.8,14.7,2.5,167.61,167.61 2006.251.08:09:48.42;head20,all,all,all,odd,adaptive,no,5.0000,1 2006.251.08:09:48.42;head21,145.3,16.1,-209.3,137.2,16.1,58.9,165.28,165.28 2006.251.08:09:48.42;head22,157.5,17.4,-203.7,149.2,16.6,56.5,169.73,169.73 2006.251.08:09:48.42;time,-0.364,101.533,rate 2006.251.08:09:48.42;flagr,200 2006.251.08:09:48.42:" K06252 2006 TSUKUB32 T Ts 2006.251.08:09:48.42:" T TSUKUB32 AZEL .0000 180.0 14 10.0 710.0 180.0 14 5.0 88.0 32.0 Ts 108 2006.251.08:09:48.42:" Ts TSUKUB32 -3957408.75120 3310229.34660 3737494.83600 73452301 2006.251.08:09:48.42:" 108 TSUKUB32 14 17400 2006.251.08:09:48.42:" drudg version 050216 compiled under FS 9.7.07 2006.251.08:09:48.42:" Rack=K4-2/M4 Recorder 1=K5 Recorder 2=none 2006.251.08:09:48.42:exper_initi 2006.251.08:09:48.42&exper_initi/proc_library 2006.251.08:09:48.42&exper_initi/sched_initi 2006.251.08:09:48.43:!2006.252.06:29:50 2006.251.08:09:48.43&proc_library/" k06252 tsukub32 ts 2006.251.08:09:48.43&proc_library/" drudg version 050216 compiled under fs 9.7.7 2006.251.08:09:48.43&proc_library/"< k4-2/m4 rack >< k5 recorder 1> 2006.251.08:09:48.43&sched_initi/startcheck 2006.251.08:09:48.43&startcheck/sy=check_fsrun.pl & 2006.251.08:09:48.43&startcheck/" sy=/usr2/oper/temp/chmem.sh >& /dev/null & 2006.251.08:09:58.38;cable 2006.251.08:09:58.47/cable/+6.4189E-03 2006.251.08:10:53.00;cablelong 2006.251.08:10:53.08/cablelong/+6.9806E-03 2006.251.08:10:55.75;cablediff 2006.251.08:10:55.75/cablediff/561.7e-6,+ 2006.251.08:11:45.52;cable 2006.251.08:11:45.64/cable/+6.4189E-03 2006.251.08:11:50.47;wx 2006.251.08:11:50.48/wx/27.17,1011.8,89 2006.251.08:12:02.18;"Sky is cloudy. 2006.251.08:12:07.44;xfe 2006.251.08:12:07.53/xfe/off,on,15.5 2006.251.08:12:10.38;clockoff 2006.251.08:12:10.38&clockoff/"gps-fmout=1p 2006.251.08:12:10.38&clockoff/fmout-gps=1p 2006.251.08:12:11.07/fmout-gps/S +4.68E-07 2006.251.09:45:13.19?ERROR st -97 Trouble decoding pressure data 2006.251.09:45:13.19#wxget#05 1.9 3.0 25.85 961012.6 2006.252.06:29:50.00:sy=/usr2/oper/k5/bin/freeze_chk.pl & 2006.252.06:29:50.03:!2006.252.07:19:50 2006.252.07:19:50.00:unstow 2006.252.07:19:50.00&unstow/antenna=e 2006.252.07:19:50.00&unstow/!+10s 2006.252.07:19:50.00&unstow/antenna=m2 2006.252.07:20:02.01:scan_name=252-0730,k06252,60 2006.252.07:20:02.01:source=1128+385,113053.28,381518.5,2000.0,ccw 2006.252.07:20:02.01#antcn#PM 1 00019 2005 228 00 22 31 00 2006.252.07:20:02.01#antcn#PM 2 90.0000 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 2006.252.07:20:02.01#antcn#PM 2 -0.0279715 0.0000000 -0.0282214 -0.0241630 -0.0014011 2006.252.07:20:02.01#antcn#PM 3 -0.0059899 0.0042895 -0.0643783 0.0000000 0.0000000 2006.252.07:20:02.01#antcn#PM 4 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.252.07:20:02.01#antcn#PM 5 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.252.07:20:03.13:ready_k5 2006.252.07:20:03.13&ready_k5/obsinfo=st 2006.252.07:20:03.13&ready_k5/autoobs=1 2006.252.07:20:03.13&ready_k5/autoobs=2 2006.252.07:20:03.13&ready_k5/autoobs=3 2006.252.07:20:03.13&ready_k5/autoobs=4 2006.252.07:20:03.13&ready_k5/obsinfo 2006.252.07:20:03.13/obsinfo=st/error_log.tmp was not found (or not removed). 2006.252.07:20:03.13#flagr#flagr/antenna,new-source 2006.252.07:20:06.39/autoobs//k5ts1/ autoobs started! 2006.252.07:20:09.58/autoobs//k5ts2/ autoobs started! 2006.252.07:20:12.70/autoobs//k5ts3/ autoobs started! 2006.252.07:20:15.84/autoobs//k5ts4/ autoobs started! 2006.252.07:20:15.87/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.252.07:20:15.87:4f8m12a=1 2006.252.07:20:15.87&4f8m12a/xlog=on 2006.252.07:20:15.87&4f8m12a/echo=on 2006.252.07:20:15.87&4f8m12a/pcalon 2006.252.07:20:15.87&4f8m12a/"tpicd=stop 2006.252.07:20:15.87&4f8m12a/vc4f8 2006.252.07:20:15.87&4f8m12a/ifd4f 2006.252.07:20:15.87&4f8m12a/"form=m,16.000,1:2 2006.252.07:20:15.87&4f8m12a/"tpicd 2006.252.07:20:15.87&4f8m12a/echo=off 2006.252.07:20:15.87&4f8m12a/xlog=off 2006.252.07:20:15.87$4f8m12a/echo=on 2006.252.07:20:15.87$4f8m12a/pcalon 2006.252.07:20:15.87&pcalon/"no phase cal control is implemented here 2006.252.07:20:15.87$pcalon/"no phase cal control is implemented here 2006.252.07:20:15.87$4f8m12a/"tpicd=stop 2006.252.07:20:15.87$4f8m12a/vc4f8 2006.252.07:20:15.87&vc4f8/valo=1,532.99 2006.252.07:20:15.87&vc4f8/va=1,8 2006.252.07:20:15.87&vc4f8/valo=2,572.99 2006.252.07:20:15.87&vc4f8/va=2,7 2006.252.07:20:15.87&vc4f8/valo=3,672.99 2006.252.07:20:15.87&vc4f8/va=3,6 2006.252.07:20:15.87&vc4f8/valo=4,832.99 2006.252.07:20:15.87&vc4f8/va=4,7 2006.252.07:20:15.87&vc4f8/valo=5,652.99 2006.252.07:20:15.87&vc4f8/va=5,7 2006.252.07:20:15.87&vc4f8/valo=6,772.99 2006.252.07:20:15.87&vc4f8/va=6,7 2006.252.07:20:15.87&vc4f8/valo=7,832.99 2006.252.07:20:15.87&vc4f8/va=7,7 2006.252.07:20:15.87&vc4f8/valo=8,852.99 2006.252.07:20:15.87&vc4f8/va=8,7 2006.252.07:20:15.87&vc4f8/vblo=1,632.99 2006.252.07:20:15.87&vc4f8/vb=1,4 2006.252.07:20:15.87&vc4f8/vblo=2,640.99 2006.252.07:20:15.87&vc4f8/vb=2,5 2006.252.07:20:15.87&vc4f8/vblo=3,656.99 2006.252.07:20:15.87&vc4f8/vb=3,4 2006.252.07:20:15.87&vc4f8/vblo=4,712.99 2006.252.07:20:15.87&vc4f8/vb=4,4 2006.252.07:20:15.87&vc4f8/vblo=5,744.99 2006.252.07:20:15.87&vc4f8/vb=5,4 2006.252.07:20:15.87&vc4f8/vblo=6,752.99 2006.252.07:20:15.87&vc4f8/vb=6,4 2006.252.07:20:15.87&vc4f8/vabw=wide 2006.252.07:20:15.87&vc4f8/vbbw=wide 2006.252.07:20:15.87$vc4f8/valo=1,532.99 2006.252.07:20:15.88#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.252.07:20:15.88#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.252.07:20:15.88#ibcon#ireg 17 cls_cnt 0 2006.252.07:20:15.88#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.252.07:20:15.88#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.252.07:20:15.88#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.252.07:20:15.88#ibcon#enter wrdev, iclass 23, count 0 2006.252.07:20:15.88#ibcon#first serial, iclass 23, count 0 2006.252.07:20:15.88#ibcon#enter sib2, iclass 23, count 0 2006.252.07:20:15.88#ibcon#flushed, iclass 23, count 0 2006.252.07:20:15.88#ibcon#about to write, iclass 23, count 0 2006.252.07:20:15.88#ibcon#wrote, iclass 23, count 0 2006.252.07:20:15.88#ibcon#about to read 3, iclass 23, count 0 2006.252.07:20:15.91#ibcon#read 3, iclass 23, count 0 2006.252.07:20:15.91#ibcon#about to read 4, iclass 23, count 0 2006.252.07:20:15.91#ibcon#read 4, iclass 23, count 0 2006.252.07:20:15.91#ibcon#about to read 5, iclass 23, count 0 2006.252.07:20:15.91#ibcon#read 5, iclass 23, count 0 2006.252.07:20:15.91#ibcon#about to read 6, iclass 23, count 0 2006.252.07:20:15.91#ibcon#read 6, iclass 23, count 0 2006.252.07:20:15.91#ibcon#end of sib2, iclass 23, count 0 2006.252.07:20:15.91#ibcon#*mode == 0, iclass 23, count 0 2006.252.07:20:15.91#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.252.07:20:15.91#ibcon#[26=FRQ=01,532.99\r\n] 2006.252.07:20:15.91#ibcon#*before write, iclass 23, count 0 2006.252.07:20:15.91#ibcon#enter sib2, iclass 23, count 0 2006.252.07:20:15.91#ibcon#flushed, iclass 23, count 0 2006.252.07:20:15.91#ibcon#about to write, iclass 23, count 0 2006.252.07:20:15.91#ibcon#wrote, iclass 23, count 0 2006.252.07:20:15.91#ibcon#about to read 3, iclass 23, count 0 2006.252.07:20:15.98#ibcon#read 3, iclass 23, count 0 2006.252.07:20:15.98#ibcon#about to read 4, iclass 23, count 0 2006.252.07:20:15.98#ibcon#read 4, iclass 23, count 0 2006.252.07:20:15.98#ibcon#about to read 5, iclass 23, count 0 2006.252.07:20:15.98#ibcon#read 5, iclass 23, count 0 2006.252.07:20:15.98#ibcon#about to read 6, iclass 23, count 0 2006.252.07:20:15.98#ibcon#read 6, iclass 23, count 0 2006.252.07:20:15.98#ibcon#end of sib2, iclass 23, count 0 2006.252.07:20:15.98#ibcon#*after write, iclass 23, count 0 2006.252.07:20:15.98#ibcon#*before return 0, iclass 23, count 0 2006.252.07:20:15.98#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.252.07:20:15.98#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.252.07:20:15.98#ibcon#about to clear, iclass 23 cls_cnt 0 2006.252.07:20:15.98#ibcon#cleared, iclass 23 cls_cnt 0 2006.252.07:20:15.98$vc4f8/va=1,8 2006.252.07:20:15.98#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.252.07:20:15.98#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.252.07:20:15.98#ibcon#ireg 11 cls_cnt 2 2006.252.07:20:15.98#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.252.07:20:15.98#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.252.07:20:15.98#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.252.07:20:15.98#ibcon#enter wrdev, iclass 25, count 2 2006.252.07:20:15.98#ibcon#first serial, iclass 25, count 2 2006.252.07:20:15.98#ibcon#enter sib2, iclass 25, count 2 2006.252.07:20:15.98#ibcon#flushed, iclass 25, count 2 2006.252.07:20:15.98#ibcon#about to write, iclass 25, count 2 2006.252.07:20:15.98#ibcon#wrote, iclass 25, count 2 2006.252.07:20:15.98#ibcon#about to read 3, iclass 25, count 2 2006.252.07:20:16.00#ibcon#read 3, iclass 25, count 2 2006.252.07:20:16.00#ibcon#about to read 4, iclass 25, count 2 2006.252.07:20:16.00#ibcon#read 4, iclass 25, count 2 2006.252.07:20:16.00#ibcon#about to read 5, iclass 25, count 2 2006.252.07:20:16.00#ibcon#read 5, iclass 25, count 2 2006.252.07:20:16.00#ibcon#about to read 6, iclass 25, count 2 2006.252.07:20:16.00#ibcon#read 6, iclass 25, count 2 2006.252.07:20:16.00#ibcon#end of sib2, iclass 25, count 2 2006.252.07:20:16.00#ibcon#*mode == 0, iclass 25, count 2 2006.252.07:20:16.00#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.252.07:20:16.00#ibcon#[25=AT01-08\r\n] 2006.252.07:20:16.00#ibcon#*before write, iclass 25, count 2 2006.252.07:20:16.00#ibcon#enter sib2, iclass 25, count 2 2006.252.07:20:16.00#ibcon#flushed, iclass 25, count 2 2006.252.07:20:16.00#ibcon#about to write, iclass 25, count 2 2006.252.07:20:16.00#ibcon#wrote, iclass 25, count 2 2006.252.07:20:16.00#ibcon#about to read 3, iclass 25, count 2 2006.252.07:20:16.04#ibcon#read 3, iclass 25, count 2 2006.252.07:20:16.04#ibcon#about to read 4, iclass 25, count 2 2006.252.07:20:16.04#ibcon#read 4, iclass 25, count 2 2006.252.07:20:16.04#ibcon#about to read 5, iclass 25, count 2 2006.252.07:20:16.04#ibcon#read 5, iclass 25, count 2 2006.252.07:20:16.04#ibcon#about to read 6, iclass 25, count 2 2006.252.07:20:16.04#ibcon#read 6, iclass 25, count 2 2006.252.07:20:16.04#ibcon#end of sib2, iclass 25, count 2 2006.252.07:20:16.04#ibcon#*after write, iclass 25, count 2 2006.252.07:20:16.04#ibcon#*before return 0, iclass 25, count 2 2006.252.07:20:16.04#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.252.07:20:16.04#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.252.07:20:16.04#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.252.07:20:16.04#ibcon#ireg 7 cls_cnt 0 2006.252.07:20:16.04#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.252.07:20:16.16#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.252.07:20:16.16#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.252.07:20:16.16#ibcon#enter wrdev, iclass 25, count 0 2006.252.07:20:16.16#ibcon#first serial, iclass 25, count 0 2006.252.07:20:16.16#ibcon#enter sib2, iclass 25, count 0 2006.252.07:20:16.16#ibcon#flushed, iclass 25, count 0 2006.252.07:20:16.16#ibcon#about to write, iclass 25, count 0 2006.252.07:20:16.16#ibcon#wrote, iclass 25, count 0 2006.252.07:20:16.16#ibcon#about to read 3, iclass 25, count 0 2006.252.07:20:16.18#ibcon#read 3, iclass 25, count 0 2006.252.07:20:16.18#ibcon#about to read 4, iclass 25, count 0 2006.252.07:20:16.18#ibcon#read 4, iclass 25, count 0 2006.252.07:20:16.18#ibcon#about to read 5, iclass 25, count 0 2006.252.07:20:16.18#ibcon#read 5, iclass 25, count 0 2006.252.07:20:16.18#ibcon#about to read 6, iclass 25, count 0 2006.252.07:20:16.18#ibcon#read 6, iclass 25, count 0 2006.252.07:20:16.18#ibcon#end of sib2, iclass 25, count 0 2006.252.07:20:16.18#ibcon#*mode == 0, iclass 25, count 0 2006.252.07:20:16.18#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.252.07:20:16.18#ibcon#[25=USB\r\n] 2006.252.07:20:16.18#ibcon#*before write, iclass 25, count 0 2006.252.07:20:16.18#ibcon#enter sib2, iclass 25, count 0 2006.252.07:20:16.18#ibcon#flushed, iclass 25, count 0 2006.252.07:20:16.18#ibcon#about to write, iclass 25, count 0 2006.252.07:20:16.18#ibcon#wrote, iclass 25, count 0 2006.252.07:20:16.18#ibcon#about to read 3, iclass 25, count 0 2006.252.07:20:16.21#ibcon#read 3, iclass 25, count 0 2006.252.07:20:16.21#ibcon#about to read 4, iclass 25, count 0 2006.252.07:20:16.21#ibcon#read 4, iclass 25, count 0 2006.252.07:20:16.21#ibcon#about to read 5, iclass 25, count 0 2006.252.07:20:16.21#ibcon#read 5, iclass 25, count 0 2006.252.07:20:16.21#ibcon#about to read 6, iclass 25, count 0 2006.252.07:20:16.21#ibcon#read 6, iclass 25, count 0 2006.252.07:20:16.21#ibcon#end of sib2, iclass 25, count 0 2006.252.07:20:16.21#ibcon#*after write, iclass 25, count 0 2006.252.07:20:16.21#ibcon#*before return 0, iclass 25, count 0 2006.252.07:20:16.21#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.252.07:20:16.21#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.252.07:20:16.21#ibcon#about to clear, iclass 25 cls_cnt 0 2006.252.07:20:16.21#ibcon#cleared, iclass 25 cls_cnt 0 2006.252.07:20:16.21$vc4f8/valo=2,572.99 2006.252.07:20:16.21#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.252.07:20:16.21#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.252.07:20:16.21#ibcon#ireg 17 cls_cnt 0 2006.252.07:20:16.21#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.252.07:20:16.21#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.252.07:20:16.21#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.252.07:20:16.21#ibcon#enter wrdev, iclass 27, count 0 2006.252.07:20:16.21#ibcon#first serial, iclass 27, count 0 2006.252.07:20:16.21#ibcon#enter sib2, iclass 27, count 0 2006.252.07:20:16.21#ibcon#flushed, iclass 27, count 0 2006.252.07:20:16.21#ibcon#about to write, iclass 27, count 0 2006.252.07:20:16.21#ibcon#wrote, iclass 27, count 0 2006.252.07:20:16.21#ibcon#about to read 3, iclass 27, count 0 2006.252.07:20:16.23#ibcon#read 3, iclass 27, count 0 2006.252.07:20:16.23#ibcon#about to read 4, iclass 27, count 0 2006.252.07:20:16.23#ibcon#read 4, iclass 27, count 0 2006.252.07:20:16.23#ibcon#about to read 5, iclass 27, count 0 2006.252.07:20:16.23#ibcon#read 5, iclass 27, count 0 2006.252.07:20:16.23#ibcon#about to read 6, iclass 27, count 0 2006.252.07:20:16.23#ibcon#read 6, iclass 27, count 0 2006.252.07:20:16.23#ibcon#end of sib2, iclass 27, count 0 2006.252.07:20:16.23#ibcon#*mode == 0, iclass 27, count 0 2006.252.07:20:16.23#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.252.07:20:16.23#ibcon#[26=FRQ=02,572.99\r\n] 2006.252.07:20:16.23#ibcon#*before write, iclass 27, count 0 2006.252.07:20:16.23#ibcon#enter sib2, iclass 27, count 0 2006.252.07:20:16.23#ibcon#flushed, iclass 27, count 0 2006.252.07:20:16.23#ibcon#about to write, iclass 27, count 0 2006.252.07:20:16.23#ibcon#wrote, iclass 27, count 0 2006.252.07:20:16.23#ibcon#about to read 3, iclass 27, count 0 2006.252.07:20:16.27#ibcon#read 3, iclass 27, count 0 2006.252.07:20:16.27#ibcon#about to read 4, iclass 27, count 0 2006.252.07:20:16.27#ibcon#read 4, iclass 27, count 0 2006.252.07:20:16.27#ibcon#about to read 5, iclass 27, count 0 2006.252.07:20:16.27#ibcon#read 5, iclass 27, count 0 2006.252.07:20:16.27#ibcon#about to read 6, iclass 27, count 0 2006.252.07:20:16.27#ibcon#read 6, iclass 27, count 0 2006.252.07:20:16.27#ibcon#end of sib2, iclass 27, count 0 2006.252.07:20:16.27#ibcon#*after write, iclass 27, count 0 2006.252.07:20:16.27#ibcon#*before return 0, iclass 27, count 0 2006.252.07:20:16.27#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.252.07:20:16.27#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.252.07:20:16.27#ibcon#about to clear, iclass 27 cls_cnt 0 2006.252.07:20:16.27#ibcon#cleared, iclass 27 cls_cnt 0 2006.252.07:20:16.27$vc4f8/va=2,7 2006.252.07:20:16.27#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.252.07:20:16.27#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.252.07:20:16.27#ibcon#ireg 11 cls_cnt 2 2006.252.07:20:16.27#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.252.07:20:16.33#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.252.07:20:16.33#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.252.07:20:16.33#ibcon#enter wrdev, iclass 29, count 2 2006.252.07:20:16.33#ibcon#first serial, iclass 29, count 2 2006.252.07:20:16.33#ibcon#enter sib2, iclass 29, count 2 2006.252.07:20:16.33#ibcon#flushed, iclass 29, count 2 2006.252.07:20:16.33#ibcon#about to write, iclass 29, count 2 2006.252.07:20:16.33#ibcon#wrote, iclass 29, count 2 2006.252.07:20:16.33#ibcon#about to read 3, iclass 29, count 2 2006.252.07:20:16.35#ibcon#read 3, iclass 29, count 2 2006.252.07:20:16.35#ibcon#about to read 4, iclass 29, count 2 2006.252.07:20:16.35#ibcon#read 4, iclass 29, count 2 2006.252.07:20:16.35#ibcon#about to read 5, iclass 29, count 2 2006.252.07:20:16.35#ibcon#read 5, iclass 29, count 2 2006.252.07:20:16.35#ibcon#about to read 6, iclass 29, count 2 2006.252.07:20:16.35#ibcon#read 6, iclass 29, count 2 2006.252.07:20:16.35#ibcon#end of sib2, iclass 29, count 2 2006.252.07:20:16.35#ibcon#*mode == 0, iclass 29, count 2 2006.252.07:20:16.35#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.252.07:20:16.35#ibcon#[25=AT02-07\r\n] 2006.252.07:20:16.35#ibcon#*before write, iclass 29, count 2 2006.252.07:20:16.35#ibcon#enter sib2, iclass 29, count 2 2006.252.07:20:16.35#ibcon#flushed, iclass 29, count 2 2006.252.07:20:16.35#ibcon#about to write, iclass 29, count 2 2006.252.07:20:16.35#ibcon#wrote, iclass 29, count 2 2006.252.07:20:16.35#ibcon#about to read 3, iclass 29, count 2 2006.252.07:20:16.38#ibcon#read 3, iclass 29, count 2 2006.252.07:20:16.38#ibcon#about to read 4, iclass 29, count 2 2006.252.07:20:16.38#ibcon#read 4, iclass 29, count 2 2006.252.07:20:16.38#ibcon#about to read 5, iclass 29, count 2 2006.252.07:20:16.38#ibcon#read 5, iclass 29, count 2 2006.252.07:20:16.38#ibcon#about to read 6, iclass 29, count 2 2006.252.07:20:16.38#ibcon#read 6, iclass 29, count 2 2006.252.07:20:16.38#ibcon#end of sib2, iclass 29, count 2 2006.252.07:20:16.38#ibcon#*after write, iclass 29, count 2 2006.252.07:20:16.38#ibcon#*before return 0, iclass 29, count 2 2006.252.07:20:16.38#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.252.07:20:16.38#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.252.07:20:16.38#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.252.07:20:16.38#ibcon#ireg 7 cls_cnt 0 2006.252.07:20:16.38#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.252.07:20:16.50#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.252.07:20:16.50#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.252.07:20:16.50#ibcon#enter wrdev, iclass 29, count 0 2006.252.07:20:16.50#ibcon#first serial, iclass 29, count 0 2006.252.07:20:16.50#ibcon#enter sib2, iclass 29, count 0 2006.252.07:20:16.50#ibcon#flushed, iclass 29, count 0 2006.252.07:20:16.50#ibcon#about to write, iclass 29, count 0 2006.252.07:20:16.50#ibcon#wrote, iclass 29, count 0 2006.252.07:20:16.50#ibcon#about to read 3, iclass 29, count 0 2006.252.07:20:16.52#ibcon#read 3, iclass 29, count 0 2006.252.07:20:16.52#ibcon#about to read 4, iclass 29, count 0 2006.252.07:20:16.52#ibcon#read 4, iclass 29, count 0 2006.252.07:20:16.52#ibcon#about to read 5, iclass 29, count 0 2006.252.07:20:16.52#ibcon#read 5, iclass 29, count 0 2006.252.07:20:16.52#ibcon#about to read 6, iclass 29, count 0 2006.252.07:20:16.52#ibcon#read 6, iclass 29, count 0 2006.252.07:20:16.52#ibcon#end of sib2, iclass 29, count 0 2006.252.07:20:16.52#ibcon#*mode == 0, iclass 29, count 0 2006.252.07:20:16.52#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.252.07:20:16.52#ibcon#[25=USB\r\n] 2006.252.07:20:16.52#ibcon#*before write, iclass 29, count 0 2006.252.07:20:16.52#ibcon#enter sib2, iclass 29, count 0 2006.252.07:20:16.52#ibcon#flushed, iclass 29, count 0 2006.252.07:20:16.52#ibcon#about to write, iclass 29, count 0 2006.252.07:20:16.52#ibcon#wrote, iclass 29, count 0 2006.252.07:20:16.52#ibcon#about to read 3, iclass 29, count 0 2006.252.07:20:16.55#ibcon#read 3, iclass 29, count 0 2006.252.07:20:16.55#ibcon#about to read 4, iclass 29, count 0 2006.252.07:20:16.55#ibcon#read 4, iclass 29, count 0 2006.252.07:20:16.55#ibcon#about to read 5, iclass 29, count 0 2006.252.07:20:16.55#ibcon#read 5, iclass 29, count 0 2006.252.07:20:16.55#ibcon#about to read 6, iclass 29, count 0 2006.252.07:20:16.55#ibcon#read 6, iclass 29, count 0 2006.252.07:20:16.55#ibcon#end of sib2, iclass 29, count 0 2006.252.07:20:16.55#ibcon#*after write, iclass 29, count 0 2006.252.07:20:16.55#ibcon#*before return 0, iclass 29, count 0 2006.252.07:20:16.55#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.252.07:20:16.55#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.252.07:20:16.55#ibcon#about to clear, iclass 29 cls_cnt 0 2006.252.07:20:16.55#ibcon#cleared, iclass 29 cls_cnt 0 2006.252.07:20:16.55$vc4f8/valo=3,672.99 2006.252.07:20:16.55#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.252.07:20:16.55#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.252.07:20:16.55#ibcon#ireg 17 cls_cnt 0 2006.252.07:20:16.55#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.252.07:20:16.55#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.252.07:20:16.55#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.252.07:20:16.55#ibcon#enter wrdev, iclass 31, count 0 2006.252.07:20:16.55#ibcon#first serial, iclass 31, count 0 2006.252.07:20:16.55#ibcon#enter sib2, iclass 31, count 0 2006.252.07:20:16.55#ibcon#flushed, iclass 31, count 0 2006.252.07:20:16.55#ibcon#about to write, iclass 31, count 0 2006.252.07:20:16.55#ibcon#wrote, iclass 31, count 0 2006.252.07:20:16.55#ibcon#about to read 3, iclass 31, count 0 2006.252.07:20:16.58#ibcon#read 3, iclass 31, count 0 2006.252.07:20:16.58#ibcon#about to read 4, iclass 31, count 0 2006.252.07:20:16.58#ibcon#read 4, iclass 31, count 0 2006.252.07:20:16.58#ibcon#about to read 5, iclass 31, count 0 2006.252.07:20:16.58#ibcon#read 5, iclass 31, count 0 2006.252.07:20:16.58#ibcon#about to read 6, iclass 31, count 0 2006.252.07:20:16.58#ibcon#read 6, iclass 31, count 0 2006.252.07:20:16.58#ibcon#end of sib2, iclass 31, count 0 2006.252.07:20:16.58#ibcon#*mode == 0, iclass 31, count 0 2006.252.07:20:16.58#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.252.07:20:16.58#ibcon#[26=FRQ=03,672.99\r\n] 2006.252.07:20:16.58#ibcon#*before write, iclass 31, count 0 2006.252.07:20:16.58#ibcon#enter sib2, iclass 31, count 0 2006.252.07:20:16.58#ibcon#flushed, iclass 31, count 0 2006.252.07:20:16.58#ibcon#about to write, iclass 31, count 0 2006.252.07:20:16.58#ibcon#wrote, iclass 31, count 0 2006.252.07:20:16.58#ibcon#about to read 3, iclass 31, count 0 2006.252.07:20:16.62#ibcon#read 3, iclass 31, count 0 2006.252.07:20:16.62#ibcon#about to read 4, iclass 31, count 0 2006.252.07:20:16.62#ibcon#read 4, iclass 31, count 0 2006.252.07:20:16.62#ibcon#about to read 5, iclass 31, count 0 2006.252.07:20:16.62#ibcon#read 5, iclass 31, count 0 2006.252.07:20:16.62#ibcon#about to read 6, iclass 31, count 0 2006.252.07:20:16.62#ibcon#read 6, iclass 31, count 0 2006.252.07:20:16.62#ibcon#end of sib2, iclass 31, count 0 2006.252.07:20:16.62#ibcon#*after write, iclass 31, count 0 2006.252.07:20:16.62#ibcon#*before return 0, iclass 31, count 0 2006.252.07:20:16.62#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.252.07:20:16.62#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.252.07:20:16.62#ibcon#about to clear, iclass 31 cls_cnt 0 2006.252.07:20:16.62#ibcon#cleared, iclass 31 cls_cnt 0 2006.252.07:20:16.62$vc4f8/va=3,6 2006.252.07:20:16.62#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.252.07:20:16.62#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.252.07:20:16.62#ibcon#ireg 11 cls_cnt 2 2006.252.07:20:16.62#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.252.07:20:16.67#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.252.07:20:16.67#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.252.07:20:16.67#ibcon#enter wrdev, iclass 33, count 2 2006.252.07:20:16.67#ibcon#first serial, iclass 33, count 2 2006.252.07:20:16.67#ibcon#enter sib2, iclass 33, count 2 2006.252.07:20:16.67#ibcon#flushed, iclass 33, count 2 2006.252.07:20:16.67#ibcon#about to write, iclass 33, count 2 2006.252.07:20:16.67#ibcon#wrote, iclass 33, count 2 2006.252.07:20:16.67#ibcon#about to read 3, iclass 33, count 2 2006.252.07:20:16.69#ibcon#read 3, iclass 33, count 2 2006.252.07:20:16.69#ibcon#about to read 4, iclass 33, count 2 2006.252.07:20:16.69#ibcon#read 4, iclass 33, count 2 2006.252.07:20:16.69#ibcon#about to read 5, iclass 33, count 2 2006.252.07:20:16.69#ibcon#read 5, iclass 33, count 2 2006.252.07:20:16.69#ibcon#about to read 6, iclass 33, count 2 2006.252.07:20:16.69#ibcon#read 6, iclass 33, count 2 2006.252.07:20:16.69#ibcon#end of sib2, iclass 33, count 2 2006.252.07:20:16.69#ibcon#*mode == 0, iclass 33, count 2 2006.252.07:20:16.69#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.252.07:20:16.69#ibcon#[25=AT03-06\r\n] 2006.252.07:20:16.69#ibcon#*before write, iclass 33, count 2 2006.252.07:20:16.69#ibcon#enter sib2, iclass 33, count 2 2006.252.07:20:16.69#ibcon#flushed, iclass 33, count 2 2006.252.07:20:16.69#ibcon#about to write, iclass 33, count 2 2006.252.07:20:16.69#ibcon#wrote, iclass 33, count 2 2006.252.07:20:16.69#ibcon#about to read 3, iclass 33, count 2 2006.252.07:20:16.72#ibcon#read 3, iclass 33, count 2 2006.252.07:20:16.72#ibcon#about to read 4, iclass 33, count 2 2006.252.07:20:16.72#ibcon#read 4, iclass 33, count 2 2006.252.07:20:16.72#ibcon#about to read 5, iclass 33, count 2 2006.252.07:20:16.72#ibcon#read 5, iclass 33, count 2 2006.252.07:20:16.72#ibcon#about to read 6, iclass 33, count 2 2006.252.07:20:16.72#ibcon#read 6, iclass 33, count 2 2006.252.07:20:16.72#ibcon#end of sib2, iclass 33, count 2 2006.252.07:20:16.72#ibcon#*after write, iclass 33, count 2 2006.252.07:20:16.72#ibcon#*before return 0, iclass 33, count 2 2006.252.07:20:16.72#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.252.07:20:16.72#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.252.07:20:16.72#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.252.07:20:16.72#ibcon#ireg 7 cls_cnt 0 2006.252.07:20:16.72#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.252.07:20:16.84#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.252.07:20:16.84#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.252.07:20:16.84#ibcon#enter wrdev, iclass 33, count 0 2006.252.07:20:16.84#ibcon#first serial, iclass 33, count 0 2006.252.07:20:16.84#ibcon#enter sib2, iclass 33, count 0 2006.252.07:20:16.84#ibcon#flushed, iclass 33, count 0 2006.252.07:20:16.84#ibcon#about to write, iclass 33, count 0 2006.252.07:20:16.84#ibcon#wrote, iclass 33, count 0 2006.252.07:20:16.84#ibcon#about to read 3, iclass 33, count 0 2006.252.07:20:16.86#ibcon#read 3, iclass 33, count 0 2006.252.07:20:16.86#ibcon#about to read 4, iclass 33, count 0 2006.252.07:20:16.86#ibcon#read 4, iclass 33, count 0 2006.252.07:20:16.86#ibcon#about to read 5, iclass 33, count 0 2006.252.07:20:16.86#ibcon#read 5, iclass 33, count 0 2006.252.07:20:16.86#ibcon#about to read 6, iclass 33, count 0 2006.252.07:20:16.86#ibcon#read 6, iclass 33, count 0 2006.252.07:20:16.86#ibcon#end of sib2, iclass 33, count 0 2006.252.07:20:16.86#ibcon#*mode == 0, iclass 33, count 0 2006.252.07:20:16.86#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.252.07:20:16.86#ibcon#[25=USB\r\n] 2006.252.07:20:16.86#ibcon#*before write, iclass 33, count 0 2006.252.07:20:16.86#ibcon#enter sib2, iclass 33, count 0 2006.252.07:20:16.86#ibcon#flushed, iclass 33, count 0 2006.252.07:20:16.86#ibcon#about to write, iclass 33, count 0 2006.252.07:20:16.86#ibcon#wrote, iclass 33, count 0 2006.252.07:20:16.86#ibcon#about to read 3, iclass 33, count 0 2006.252.07:20:16.89#ibcon#read 3, iclass 33, count 0 2006.252.07:20:16.89#ibcon#about to read 4, iclass 33, count 0 2006.252.07:20:16.89#ibcon#read 4, iclass 33, count 0 2006.252.07:20:16.89#ibcon#about to read 5, iclass 33, count 0 2006.252.07:20:16.89#ibcon#read 5, iclass 33, count 0 2006.252.07:20:16.89#ibcon#about to read 6, iclass 33, count 0 2006.252.07:20:16.89#ibcon#read 6, iclass 33, count 0 2006.252.07:20:16.89#ibcon#end of sib2, iclass 33, count 0 2006.252.07:20:16.89#ibcon#*after write, iclass 33, count 0 2006.252.07:20:16.89#ibcon#*before return 0, iclass 33, count 0 2006.252.07:20:16.89#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.252.07:20:16.89#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.252.07:20:16.89#ibcon#about to clear, iclass 33 cls_cnt 0 2006.252.07:20:16.89#ibcon#cleared, iclass 33 cls_cnt 0 2006.252.07:20:16.89$vc4f8/valo=4,832.99 2006.252.07:20:16.89#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.252.07:20:16.89#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.252.07:20:16.89#ibcon#ireg 17 cls_cnt 0 2006.252.07:20:16.89#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.252.07:20:16.89#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.252.07:20:16.89#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.252.07:20:16.89#ibcon#enter wrdev, iclass 35, count 0 2006.252.07:20:16.89#ibcon#first serial, iclass 35, count 0 2006.252.07:20:16.89#ibcon#enter sib2, iclass 35, count 0 2006.252.07:20:16.89#ibcon#flushed, iclass 35, count 0 2006.252.07:20:16.89#ibcon#about to write, iclass 35, count 0 2006.252.07:20:16.89#ibcon#wrote, iclass 35, count 0 2006.252.07:20:16.89#ibcon#about to read 3, iclass 35, count 0 2006.252.07:20:16.91#ibcon#read 3, iclass 35, count 0 2006.252.07:20:16.91#ibcon#about to read 4, iclass 35, count 0 2006.252.07:20:16.91#ibcon#read 4, iclass 35, count 0 2006.252.07:20:16.91#ibcon#about to read 5, iclass 35, count 0 2006.252.07:20:16.91#ibcon#read 5, iclass 35, count 0 2006.252.07:20:16.91#ibcon#about to read 6, iclass 35, count 0 2006.252.07:20:16.91#ibcon#read 6, iclass 35, count 0 2006.252.07:20:16.91#ibcon#end of sib2, iclass 35, count 0 2006.252.07:20:16.91#ibcon#*mode == 0, iclass 35, count 0 2006.252.07:20:16.91#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.252.07:20:16.91#ibcon#[26=FRQ=04,832.99\r\n] 2006.252.07:20:16.91#ibcon#*before write, iclass 35, count 0 2006.252.07:20:16.91#ibcon#enter sib2, iclass 35, count 0 2006.252.07:20:16.91#ibcon#flushed, iclass 35, count 0 2006.252.07:20:16.91#ibcon#about to write, iclass 35, count 0 2006.252.07:20:16.91#ibcon#wrote, iclass 35, count 0 2006.252.07:20:16.91#ibcon#about to read 3, iclass 35, count 0 2006.252.07:20:16.95#ibcon#read 3, iclass 35, count 0 2006.252.07:20:16.95#ibcon#about to read 4, iclass 35, count 0 2006.252.07:20:16.95#ibcon#read 4, iclass 35, count 0 2006.252.07:20:16.95#ibcon#about to read 5, iclass 35, count 0 2006.252.07:20:16.95#ibcon#read 5, iclass 35, count 0 2006.252.07:20:16.95#ibcon#about to read 6, iclass 35, count 0 2006.252.07:20:16.95#ibcon#read 6, iclass 35, count 0 2006.252.07:20:16.95#ibcon#end of sib2, iclass 35, count 0 2006.252.07:20:16.95#ibcon#*after write, iclass 35, count 0 2006.252.07:20:16.95#ibcon#*before return 0, iclass 35, count 0 2006.252.07:20:16.95#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.252.07:20:16.95#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.252.07:20:16.95#ibcon#about to clear, iclass 35 cls_cnt 0 2006.252.07:20:16.95#ibcon#cleared, iclass 35 cls_cnt 0 2006.252.07:20:16.95$vc4f8/va=4,7 2006.252.07:20:16.95#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.252.07:20:16.95#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.252.07:20:16.95#ibcon#ireg 11 cls_cnt 2 2006.252.07:20:16.95#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.252.07:20:17.01#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.252.07:20:17.01#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.252.07:20:17.01#ibcon#enter wrdev, iclass 37, count 2 2006.252.07:20:17.01#ibcon#first serial, iclass 37, count 2 2006.252.07:20:17.01#ibcon#enter sib2, iclass 37, count 2 2006.252.07:20:17.01#ibcon#flushed, iclass 37, count 2 2006.252.07:20:17.01#ibcon#about to write, iclass 37, count 2 2006.252.07:20:17.01#ibcon#wrote, iclass 37, count 2 2006.252.07:20:17.01#ibcon#about to read 3, iclass 37, count 2 2006.252.07:20:17.03#ibcon#read 3, iclass 37, count 2 2006.252.07:20:17.03#ibcon#about to read 4, iclass 37, count 2 2006.252.07:20:17.03#ibcon#read 4, iclass 37, count 2 2006.252.07:20:17.03#ibcon#about to read 5, iclass 37, count 2 2006.252.07:20:17.03#ibcon#read 5, iclass 37, count 2 2006.252.07:20:17.03#ibcon#about to read 6, iclass 37, count 2 2006.252.07:20:17.03#ibcon#read 6, iclass 37, count 2 2006.252.07:20:17.03#ibcon#end of sib2, iclass 37, count 2 2006.252.07:20:17.03#ibcon#*mode == 0, iclass 37, count 2 2006.252.07:20:17.03#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.252.07:20:17.03#ibcon#[25=AT04-07\r\n] 2006.252.07:20:17.03#ibcon#*before write, iclass 37, count 2 2006.252.07:20:17.03#ibcon#enter sib2, iclass 37, count 2 2006.252.07:20:17.03#ibcon#flushed, iclass 37, count 2 2006.252.07:20:17.03#ibcon#about to write, iclass 37, count 2 2006.252.07:20:17.03#ibcon#wrote, iclass 37, count 2 2006.252.07:20:17.03#ibcon#about to read 3, iclass 37, count 2 2006.252.07:20:17.06#ibcon#read 3, iclass 37, count 2 2006.252.07:20:17.06#ibcon#about to read 4, iclass 37, count 2 2006.252.07:20:17.06#ibcon#read 4, iclass 37, count 2 2006.252.07:20:17.06#ibcon#about to read 5, iclass 37, count 2 2006.252.07:20:17.06#ibcon#read 5, iclass 37, count 2 2006.252.07:20:17.06#ibcon#about to read 6, iclass 37, count 2 2006.252.07:20:17.06#ibcon#read 6, iclass 37, count 2 2006.252.07:20:17.06#ibcon#end of sib2, iclass 37, count 2 2006.252.07:20:17.06#ibcon#*after write, iclass 37, count 2 2006.252.07:20:17.06#ibcon#*before return 0, iclass 37, count 2 2006.252.07:20:17.06#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.252.07:20:17.06#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.252.07:20:17.06#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.252.07:20:17.06#ibcon#ireg 7 cls_cnt 0 2006.252.07:20:17.06#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.252.07:20:17.18#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.252.07:20:17.18#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.252.07:20:17.18#ibcon#enter wrdev, iclass 37, count 0 2006.252.07:20:17.18#ibcon#first serial, iclass 37, count 0 2006.252.07:20:17.18#ibcon#enter sib2, iclass 37, count 0 2006.252.07:20:17.18#ibcon#flushed, iclass 37, count 0 2006.252.07:20:17.18#ibcon#about to write, iclass 37, count 0 2006.252.07:20:17.18#ibcon#wrote, iclass 37, count 0 2006.252.07:20:17.18#ibcon#about to read 3, iclass 37, count 0 2006.252.07:20:17.20#ibcon#read 3, iclass 37, count 0 2006.252.07:20:17.20#ibcon#about to read 4, iclass 37, count 0 2006.252.07:20:17.20#ibcon#read 4, iclass 37, count 0 2006.252.07:20:17.20#ibcon#about to read 5, iclass 37, count 0 2006.252.07:20:17.20#ibcon#read 5, iclass 37, count 0 2006.252.07:20:17.20#ibcon#about to read 6, iclass 37, count 0 2006.252.07:20:17.20#ibcon#read 6, iclass 37, count 0 2006.252.07:20:17.20#ibcon#end of sib2, iclass 37, count 0 2006.252.07:20:17.20#ibcon#*mode == 0, iclass 37, count 0 2006.252.07:20:17.20#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.252.07:20:17.20#ibcon#[25=USB\r\n] 2006.252.07:20:17.20#ibcon#*before write, iclass 37, count 0 2006.252.07:20:17.20#ibcon#enter sib2, iclass 37, count 0 2006.252.07:20:17.20#ibcon#flushed, iclass 37, count 0 2006.252.07:20:17.20#ibcon#about to write, iclass 37, count 0 2006.252.07:20:17.20#ibcon#wrote, iclass 37, count 0 2006.252.07:20:17.20#ibcon#about to read 3, iclass 37, count 0 2006.252.07:20:17.23#ibcon#read 3, iclass 37, count 0 2006.252.07:20:17.23#ibcon#about to read 4, iclass 37, count 0 2006.252.07:20:17.23#ibcon#read 4, iclass 37, count 0 2006.252.07:20:17.23#ibcon#about to read 5, iclass 37, count 0 2006.252.07:20:17.23#ibcon#read 5, iclass 37, count 0 2006.252.07:20:17.23#ibcon#about to read 6, iclass 37, count 0 2006.252.07:20:17.23#ibcon#read 6, iclass 37, count 0 2006.252.07:20:17.23#ibcon#end of sib2, iclass 37, count 0 2006.252.07:20:17.23#ibcon#*after write, iclass 37, count 0 2006.252.07:20:17.23#ibcon#*before return 0, iclass 37, count 0 2006.252.07:20:17.23#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.252.07:20:17.23#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.252.07:20:17.23#ibcon#about to clear, iclass 37 cls_cnt 0 2006.252.07:20:17.23#ibcon#cleared, iclass 37 cls_cnt 0 2006.252.07:20:17.23$vc4f8/valo=5,652.99 2006.252.07:20:17.23#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.252.07:20:17.23#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.252.07:20:17.23#ibcon#ireg 17 cls_cnt 0 2006.252.07:20:17.23#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.252.07:20:17.23#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.252.07:20:17.23#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.252.07:20:17.23#ibcon#enter wrdev, iclass 39, count 0 2006.252.07:20:17.23#ibcon#first serial, iclass 39, count 0 2006.252.07:20:17.23#ibcon#enter sib2, iclass 39, count 0 2006.252.07:20:17.23#ibcon#flushed, iclass 39, count 0 2006.252.07:20:17.23#ibcon#about to write, iclass 39, count 0 2006.252.07:20:17.23#ibcon#wrote, iclass 39, count 0 2006.252.07:20:17.23#ibcon#about to read 3, iclass 39, count 0 2006.252.07:20:17.25#ibcon#read 3, iclass 39, count 0 2006.252.07:20:17.25#ibcon#about to read 4, iclass 39, count 0 2006.252.07:20:17.25#ibcon#read 4, iclass 39, count 0 2006.252.07:20:17.25#ibcon#about to read 5, iclass 39, count 0 2006.252.07:20:17.25#ibcon#read 5, iclass 39, count 0 2006.252.07:20:17.25#ibcon#about to read 6, iclass 39, count 0 2006.252.07:20:17.25#ibcon#read 6, iclass 39, count 0 2006.252.07:20:17.25#ibcon#end of sib2, iclass 39, count 0 2006.252.07:20:17.25#ibcon#*mode == 0, iclass 39, count 0 2006.252.07:20:17.25#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.252.07:20:17.25#ibcon#[26=FRQ=05,652.99\r\n] 2006.252.07:20:17.25#ibcon#*before write, iclass 39, count 0 2006.252.07:20:17.25#ibcon#enter sib2, iclass 39, count 0 2006.252.07:20:17.25#ibcon#flushed, iclass 39, count 0 2006.252.07:20:17.25#ibcon#about to write, iclass 39, count 0 2006.252.07:20:17.25#ibcon#wrote, iclass 39, count 0 2006.252.07:20:17.25#ibcon#about to read 3, iclass 39, count 0 2006.252.07:20:17.29#ibcon#read 3, iclass 39, count 0 2006.252.07:20:17.29#ibcon#about to read 4, iclass 39, count 0 2006.252.07:20:17.29#ibcon#read 4, iclass 39, count 0 2006.252.07:20:17.29#ibcon#about to read 5, iclass 39, count 0 2006.252.07:20:17.29#ibcon#read 5, iclass 39, count 0 2006.252.07:20:17.29#ibcon#about to read 6, iclass 39, count 0 2006.252.07:20:17.29#ibcon#read 6, iclass 39, count 0 2006.252.07:20:17.29#ibcon#end of sib2, iclass 39, count 0 2006.252.07:20:17.29#ibcon#*after write, iclass 39, count 0 2006.252.07:20:17.29#ibcon#*before return 0, iclass 39, count 0 2006.252.07:20:17.29#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.252.07:20:17.29#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.252.07:20:17.29#ibcon#about to clear, iclass 39 cls_cnt 0 2006.252.07:20:17.29#ibcon#cleared, iclass 39 cls_cnt 0 2006.252.07:20:17.29$vc4f8/va=5,7 2006.252.07:20:17.29#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.252.07:20:17.29#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.252.07:20:17.29#ibcon#ireg 11 cls_cnt 2 2006.252.07:20:17.29#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.252.07:20:17.35#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.252.07:20:17.35#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.252.07:20:17.35#ibcon#enter wrdev, iclass 3, count 2 2006.252.07:20:17.35#ibcon#first serial, iclass 3, count 2 2006.252.07:20:17.35#ibcon#enter sib2, iclass 3, count 2 2006.252.07:20:17.35#ibcon#flushed, iclass 3, count 2 2006.252.07:20:17.35#ibcon#about to write, iclass 3, count 2 2006.252.07:20:17.35#ibcon#wrote, iclass 3, count 2 2006.252.07:20:17.35#ibcon#about to read 3, iclass 3, count 2 2006.252.07:20:17.37#ibcon#read 3, iclass 3, count 2 2006.252.07:20:17.37#ibcon#about to read 4, iclass 3, count 2 2006.252.07:20:17.37#ibcon#read 4, iclass 3, count 2 2006.252.07:20:17.37#ibcon#about to read 5, iclass 3, count 2 2006.252.07:20:17.37#ibcon#read 5, iclass 3, count 2 2006.252.07:20:17.37#ibcon#about to read 6, iclass 3, count 2 2006.252.07:20:17.37#ibcon#read 6, iclass 3, count 2 2006.252.07:20:17.37#ibcon#end of sib2, iclass 3, count 2 2006.252.07:20:17.37#ibcon#*mode == 0, iclass 3, count 2 2006.252.07:20:17.37#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.252.07:20:17.37#ibcon#[25=AT05-07\r\n] 2006.252.07:20:17.37#ibcon#*before write, iclass 3, count 2 2006.252.07:20:17.37#ibcon#enter sib2, iclass 3, count 2 2006.252.07:20:17.37#ibcon#flushed, iclass 3, count 2 2006.252.07:20:17.37#ibcon#about to write, iclass 3, count 2 2006.252.07:20:17.37#ibcon#wrote, iclass 3, count 2 2006.252.07:20:17.37#ibcon#about to read 3, iclass 3, count 2 2006.252.07:20:17.40#ibcon#read 3, iclass 3, count 2 2006.252.07:20:17.40#ibcon#about to read 4, iclass 3, count 2 2006.252.07:20:17.40#ibcon#read 4, iclass 3, count 2 2006.252.07:20:17.40#ibcon#about to read 5, iclass 3, count 2 2006.252.07:20:17.40#ibcon#read 5, iclass 3, count 2 2006.252.07:20:17.40#ibcon#about to read 6, iclass 3, count 2 2006.252.07:20:17.40#ibcon#read 6, iclass 3, count 2 2006.252.07:20:17.40#ibcon#end of sib2, iclass 3, count 2 2006.252.07:20:17.40#ibcon#*after write, iclass 3, count 2 2006.252.07:20:17.40#ibcon#*before return 0, iclass 3, count 2 2006.252.07:20:17.40#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.252.07:20:17.40#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.252.07:20:17.40#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.252.07:20:17.40#ibcon#ireg 7 cls_cnt 0 2006.252.07:20:17.40#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.252.07:20:17.52#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.252.07:20:17.52#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.252.07:20:17.52#ibcon#enter wrdev, iclass 3, count 0 2006.252.07:20:17.52#ibcon#first serial, iclass 3, count 0 2006.252.07:20:17.52#ibcon#enter sib2, iclass 3, count 0 2006.252.07:20:17.52#ibcon#flushed, iclass 3, count 0 2006.252.07:20:17.52#ibcon#about to write, iclass 3, count 0 2006.252.07:20:17.52#ibcon#wrote, iclass 3, count 0 2006.252.07:20:17.52#ibcon#about to read 3, iclass 3, count 0 2006.252.07:20:17.54#ibcon#read 3, iclass 3, count 0 2006.252.07:20:17.54#ibcon#about to read 4, iclass 3, count 0 2006.252.07:20:17.54#ibcon#read 4, iclass 3, count 0 2006.252.07:20:17.54#ibcon#about to read 5, iclass 3, count 0 2006.252.07:20:17.54#ibcon#read 5, iclass 3, count 0 2006.252.07:20:17.54#ibcon#about to read 6, iclass 3, count 0 2006.252.07:20:17.54#ibcon#read 6, iclass 3, count 0 2006.252.07:20:17.54#ibcon#end of sib2, iclass 3, count 0 2006.252.07:20:17.54#ibcon#*mode == 0, iclass 3, count 0 2006.252.07:20:17.54#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.252.07:20:17.54#ibcon#[25=USB\r\n] 2006.252.07:20:17.54#ibcon#*before write, iclass 3, count 0 2006.252.07:20:17.54#ibcon#enter sib2, iclass 3, count 0 2006.252.07:20:17.54#ibcon#flushed, iclass 3, count 0 2006.252.07:20:17.54#ibcon#about to write, iclass 3, count 0 2006.252.07:20:17.54#ibcon#wrote, iclass 3, count 0 2006.252.07:20:17.54#ibcon#about to read 3, iclass 3, count 0 2006.252.07:20:17.57#ibcon#read 3, iclass 3, count 0 2006.252.07:20:17.57#ibcon#about to read 4, iclass 3, count 0 2006.252.07:20:17.57#ibcon#read 4, iclass 3, count 0 2006.252.07:20:17.57#ibcon#about to read 5, iclass 3, count 0 2006.252.07:20:17.57#ibcon#read 5, iclass 3, count 0 2006.252.07:20:17.57#ibcon#about to read 6, iclass 3, count 0 2006.252.07:20:17.57#ibcon#read 6, iclass 3, count 0 2006.252.07:20:17.57#ibcon#end of sib2, iclass 3, count 0 2006.252.07:20:17.57#ibcon#*after write, iclass 3, count 0 2006.252.07:20:17.57#ibcon#*before return 0, iclass 3, count 0 2006.252.07:20:17.57#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.252.07:20:17.57#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.252.07:20:17.57#ibcon#about to clear, iclass 3 cls_cnt 0 2006.252.07:20:17.57#ibcon#cleared, iclass 3 cls_cnt 0 2006.252.07:20:17.57$vc4f8/valo=6,772.99 2006.252.07:20:17.57#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.252.07:20:17.57#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.252.07:20:17.57#ibcon#ireg 17 cls_cnt 0 2006.252.07:20:17.57#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.252.07:20:17.57#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.252.07:20:17.57#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.252.07:20:17.57#ibcon#enter wrdev, iclass 5, count 0 2006.252.07:20:17.57#ibcon#first serial, iclass 5, count 0 2006.252.07:20:17.57#ibcon#enter sib2, iclass 5, count 0 2006.252.07:20:17.57#ibcon#flushed, iclass 5, count 0 2006.252.07:20:17.57#ibcon#about to write, iclass 5, count 0 2006.252.07:20:17.57#ibcon#wrote, iclass 5, count 0 2006.252.07:20:17.57#ibcon#about to read 3, iclass 5, count 0 2006.252.07:20:17.59#ibcon#read 3, iclass 5, count 0 2006.252.07:20:17.59#ibcon#about to read 4, iclass 5, count 0 2006.252.07:20:17.59#ibcon#read 4, iclass 5, count 0 2006.252.07:20:17.59#ibcon#about to read 5, iclass 5, count 0 2006.252.07:20:17.59#ibcon#read 5, iclass 5, count 0 2006.252.07:20:17.59#ibcon#about to read 6, iclass 5, count 0 2006.252.07:20:17.59#ibcon#read 6, iclass 5, count 0 2006.252.07:20:17.59#ibcon#end of sib2, iclass 5, count 0 2006.252.07:20:17.59#ibcon#*mode == 0, iclass 5, count 0 2006.252.07:20:17.59#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.252.07:20:17.59#ibcon#[26=FRQ=06,772.99\r\n] 2006.252.07:20:17.59#ibcon#*before write, iclass 5, count 0 2006.252.07:20:17.59#ibcon#enter sib2, iclass 5, count 0 2006.252.07:20:17.59#ibcon#flushed, iclass 5, count 0 2006.252.07:20:17.59#ibcon#about to write, iclass 5, count 0 2006.252.07:20:17.59#ibcon#wrote, iclass 5, count 0 2006.252.07:20:17.59#ibcon#about to read 3, iclass 5, count 0 2006.252.07:20:17.63#ibcon#read 3, iclass 5, count 0 2006.252.07:20:17.63#ibcon#about to read 4, iclass 5, count 0 2006.252.07:20:17.63#ibcon#read 4, iclass 5, count 0 2006.252.07:20:17.63#ibcon#about to read 5, iclass 5, count 0 2006.252.07:20:17.63#ibcon#read 5, iclass 5, count 0 2006.252.07:20:17.63#ibcon#about to read 6, iclass 5, count 0 2006.252.07:20:17.63#ibcon#read 6, iclass 5, count 0 2006.252.07:20:17.63#ibcon#end of sib2, iclass 5, count 0 2006.252.07:20:17.63#ibcon#*after write, iclass 5, count 0 2006.252.07:20:17.63#ibcon#*before return 0, iclass 5, count 0 2006.252.07:20:17.63#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.252.07:20:17.63#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.252.07:20:17.63#ibcon#about to clear, iclass 5 cls_cnt 0 2006.252.07:20:17.63#ibcon#cleared, iclass 5 cls_cnt 0 2006.252.07:20:17.63$vc4f8/va=6,7 2006.252.07:20:17.63#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.252.07:20:17.63#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.252.07:20:17.63#ibcon#ireg 11 cls_cnt 2 2006.252.07:20:17.63#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.252.07:20:17.69#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.252.07:20:17.69#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.252.07:20:17.69#ibcon#enter wrdev, iclass 7, count 2 2006.252.07:20:17.69#ibcon#first serial, iclass 7, count 2 2006.252.07:20:17.69#ibcon#enter sib2, iclass 7, count 2 2006.252.07:20:17.69#ibcon#flushed, iclass 7, count 2 2006.252.07:20:17.69#ibcon#about to write, iclass 7, count 2 2006.252.07:20:17.69#ibcon#wrote, iclass 7, count 2 2006.252.07:20:17.69#ibcon#about to read 3, iclass 7, count 2 2006.252.07:20:17.71#ibcon#read 3, iclass 7, count 2 2006.252.07:20:17.71#ibcon#about to read 4, iclass 7, count 2 2006.252.07:20:17.71#ibcon#read 4, iclass 7, count 2 2006.252.07:20:17.71#ibcon#about to read 5, iclass 7, count 2 2006.252.07:20:17.71#ibcon#read 5, iclass 7, count 2 2006.252.07:20:17.71#ibcon#about to read 6, iclass 7, count 2 2006.252.07:20:17.71#ibcon#read 6, iclass 7, count 2 2006.252.07:20:17.71#ibcon#end of sib2, iclass 7, count 2 2006.252.07:20:17.71#ibcon#*mode == 0, iclass 7, count 2 2006.252.07:20:17.71#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.252.07:20:17.71#ibcon#[25=AT06-07\r\n] 2006.252.07:20:17.71#ibcon#*before write, iclass 7, count 2 2006.252.07:20:17.71#ibcon#enter sib2, iclass 7, count 2 2006.252.07:20:17.71#ibcon#flushed, iclass 7, count 2 2006.252.07:20:17.71#ibcon#about to write, iclass 7, count 2 2006.252.07:20:17.71#ibcon#wrote, iclass 7, count 2 2006.252.07:20:17.71#ibcon#about to read 3, iclass 7, count 2 2006.252.07:20:17.74#ibcon#read 3, iclass 7, count 2 2006.252.07:20:17.74#ibcon#about to read 4, iclass 7, count 2 2006.252.07:20:17.74#ibcon#read 4, iclass 7, count 2 2006.252.07:20:17.74#ibcon#about to read 5, iclass 7, count 2 2006.252.07:20:17.74#ibcon#read 5, iclass 7, count 2 2006.252.07:20:17.74#ibcon#about to read 6, iclass 7, count 2 2006.252.07:20:17.74#ibcon#read 6, iclass 7, count 2 2006.252.07:20:17.74#ibcon#end of sib2, iclass 7, count 2 2006.252.07:20:17.74#ibcon#*after write, iclass 7, count 2 2006.252.07:20:17.74#ibcon#*before return 0, iclass 7, count 2 2006.252.07:20:17.74#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.252.07:20:17.74#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.252.07:20:17.74#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.252.07:20:17.74#ibcon#ireg 7 cls_cnt 0 2006.252.07:20:17.74#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.252.07:20:17.86#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.252.07:20:17.86#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.252.07:20:17.86#ibcon#enter wrdev, iclass 7, count 0 2006.252.07:20:17.86#ibcon#first serial, iclass 7, count 0 2006.252.07:20:17.86#ibcon#enter sib2, iclass 7, count 0 2006.252.07:20:17.86#ibcon#flushed, iclass 7, count 0 2006.252.07:20:17.86#ibcon#about to write, iclass 7, count 0 2006.252.07:20:17.86#ibcon#wrote, iclass 7, count 0 2006.252.07:20:17.86#ibcon#about to read 3, iclass 7, count 0 2006.252.07:20:17.88#ibcon#read 3, iclass 7, count 0 2006.252.07:20:17.88#ibcon#about to read 4, iclass 7, count 0 2006.252.07:20:17.88#ibcon#read 4, iclass 7, count 0 2006.252.07:20:17.88#ibcon#about to read 5, iclass 7, count 0 2006.252.07:20:17.88#ibcon#read 5, iclass 7, count 0 2006.252.07:20:17.88#ibcon#about to read 6, iclass 7, count 0 2006.252.07:20:17.88#ibcon#read 6, iclass 7, count 0 2006.252.07:20:17.88#ibcon#end of sib2, iclass 7, count 0 2006.252.07:20:17.88#ibcon#*mode == 0, iclass 7, count 0 2006.252.07:20:17.88#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.252.07:20:17.88#ibcon#[25=USB\r\n] 2006.252.07:20:17.88#ibcon#*before write, iclass 7, count 0 2006.252.07:20:17.88#ibcon#enter sib2, iclass 7, count 0 2006.252.07:20:17.88#ibcon#flushed, iclass 7, count 0 2006.252.07:20:17.88#ibcon#about to write, iclass 7, count 0 2006.252.07:20:17.88#ibcon#wrote, iclass 7, count 0 2006.252.07:20:17.88#ibcon#about to read 3, iclass 7, count 0 2006.252.07:20:17.91#ibcon#read 3, iclass 7, count 0 2006.252.07:20:17.91#ibcon#about to read 4, iclass 7, count 0 2006.252.07:20:17.91#ibcon#read 4, iclass 7, count 0 2006.252.07:20:17.91#ibcon#about to read 5, iclass 7, count 0 2006.252.07:20:17.91#ibcon#read 5, iclass 7, count 0 2006.252.07:20:17.91#ibcon#about to read 6, iclass 7, count 0 2006.252.07:20:17.91#ibcon#read 6, iclass 7, count 0 2006.252.07:20:17.91#ibcon#end of sib2, iclass 7, count 0 2006.252.07:20:17.91#ibcon#*after write, iclass 7, count 0 2006.252.07:20:17.91#ibcon#*before return 0, iclass 7, count 0 2006.252.07:20:17.91#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.252.07:20:17.91#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.252.07:20:17.91#ibcon#about to clear, iclass 7 cls_cnt 0 2006.252.07:20:17.91#ibcon#cleared, iclass 7 cls_cnt 0 2006.252.07:20:17.91$vc4f8/valo=7,832.99 2006.252.07:20:17.91#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.252.07:20:17.91#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.252.07:20:17.91#ibcon#ireg 17 cls_cnt 0 2006.252.07:20:17.91#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.252.07:20:17.91#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.252.07:20:17.91#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.252.07:20:17.91#ibcon#enter wrdev, iclass 11, count 0 2006.252.07:20:17.91#ibcon#first serial, iclass 11, count 0 2006.252.07:20:17.91#ibcon#enter sib2, iclass 11, count 0 2006.252.07:20:17.91#ibcon#flushed, iclass 11, count 0 2006.252.07:20:17.91#ibcon#about to write, iclass 11, count 0 2006.252.07:20:17.91#ibcon#wrote, iclass 11, count 0 2006.252.07:20:17.91#ibcon#about to read 3, iclass 11, count 0 2006.252.07:20:17.93#ibcon#read 3, iclass 11, count 0 2006.252.07:20:17.93#ibcon#about to read 4, iclass 11, count 0 2006.252.07:20:17.93#ibcon#read 4, iclass 11, count 0 2006.252.07:20:17.93#ibcon#about to read 5, iclass 11, count 0 2006.252.07:20:17.93#ibcon#read 5, iclass 11, count 0 2006.252.07:20:17.93#ibcon#about to read 6, iclass 11, count 0 2006.252.07:20:17.93#ibcon#read 6, iclass 11, count 0 2006.252.07:20:17.93#ibcon#end of sib2, iclass 11, count 0 2006.252.07:20:17.93#ibcon#*mode == 0, iclass 11, count 0 2006.252.07:20:17.93#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.252.07:20:17.93#ibcon#[26=FRQ=07,832.99\r\n] 2006.252.07:20:17.93#ibcon#*before write, iclass 11, count 0 2006.252.07:20:17.93#ibcon#enter sib2, iclass 11, count 0 2006.252.07:20:17.93#ibcon#flushed, iclass 11, count 0 2006.252.07:20:17.93#ibcon#about to write, iclass 11, count 0 2006.252.07:20:17.93#ibcon#wrote, iclass 11, count 0 2006.252.07:20:17.93#ibcon#about to read 3, iclass 11, count 0 2006.252.07:20:17.97#ibcon#read 3, iclass 11, count 0 2006.252.07:20:17.97#ibcon#about to read 4, iclass 11, count 0 2006.252.07:20:17.97#ibcon#read 4, iclass 11, count 0 2006.252.07:20:17.97#ibcon#about to read 5, iclass 11, count 0 2006.252.07:20:17.97#ibcon#read 5, iclass 11, count 0 2006.252.07:20:17.97#ibcon#about to read 6, iclass 11, count 0 2006.252.07:20:17.97#ibcon#read 6, iclass 11, count 0 2006.252.07:20:17.97#ibcon#end of sib2, iclass 11, count 0 2006.252.07:20:17.97#ibcon#*after write, iclass 11, count 0 2006.252.07:20:17.97#ibcon#*before return 0, iclass 11, count 0 2006.252.07:20:17.97#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.252.07:20:17.97#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.252.07:20:17.97#ibcon#about to clear, iclass 11 cls_cnt 0 2006.252.07:20:17.97#ibcon#cleared, iclass 11 cls_cnt 0 2006.252.07:20:17.97$vc4f8/va=7,7 2006.252.07:20:17.97#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.252.07:20:17.97#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.252.07:20:17.97#ibcon#ireg 11 cls_cnt 2 2006.252.07:20:17.97#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.252.07:20:18.03#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.252.07:20:18.03#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.252.07:20:18.03#ibcon#enter wrdev, iclass 13, count 2 2006.252.07:20:18.03#ibcon#first serial, iclass 13, count 2 2006.252.07:20:18.03#ibcon#enter sib2, iclass 13, count 2 2006.252.07:20:18.03#ibcon#flushed, iclass 13, count 2 2006.252.07:20:18.03#ibcon#about to write, iclass 13, count 2 2006.252.07:20:18.03#ibcon#wrote, iclass 13, count 2 2006.252.07:20:18.03#ibcon#about to read 3, iclass 13, count 2 2006.252.07:20:18.05#ibcon#read 3, iclass 13, count 2 2006.252.07:20:18.05#ibcon#about to read 4, iclass 13, count 2 2006.252.07:20:18.05#ibcon#read 4, iclass 13, count 2 2006.252.07:20:18.05#ibcon#about to read 5, iclass 13, count 2 2006.252.07:20:18.05#ibcon#read 5, iclass 13, count 2 2006.252.07:20:18.05#ibcon#about to read 6, iclass 13, count 2 2006.252.07:20:18.05#ibcon#read 6, iclass 13, count 2 2006.252.07:20:18.05#ibcon#end of sib2, iclass 13, count 2 2006.252.07:20:18.05#ibcon#*mode == 0, iclass 13, count 2 2006.252.07:20:18.05#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.252.07:20:18.05#ibcon#[25=AT07-07\r\n] 2006.252.07:20:18.05#ibcon#*before write, iclass 13, count 2 2006.252.07:20:18.05#ibcon#enter sib2, iclass 13, count 2 2006.252.07:20:18.05#ibcon#flushed, iclass 13, count 2 2006.252.07:20:18.05#ibcon#about to write, iclass 13, count 2 2006.252.07:20:18.05#ibcon#wrote, iclass 13, count 2 2006.252.07:20:18.05#ibcon#about to read 3, iclass 13, count 2 2006.252.07:20:18.08#ibcon#read 3, iclass 13, count 2 2006.252.07:20:18.08#ibcon#about to read 4, iclass 13, count 2 2006.252.07:20:18.08#ibcon#read 4, iclass 13, count 2 2006.252.07:20:18.08#ibcon#about to read 5, iclass 13, count 2 2006.252.07:20:18.08#ibcon#read 5, iclass 13, count 2 2006.252.07:20:18.08#ibcon#about to read 6, iclass 13, count 2 2006.252.07:20:18.08#ibcon#read 6, iclass 13, count 2 2006.252.07:20:18.08#ibcon#end of sib2, iclass 13, count 2 2006.252.07:20:18.08#ibcon#*after write, iclass 13, count 2 2006.252.07:20:18.08#ibcon#*before return 0, iclass 13, count 2 2006.252.07:20:18.08#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.252.07:20:18.08#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.252.07:20:18.08#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.252.07:20:18.08#ibcon#ireg 7 cls_cnt 0 2006.252.07:20:18.08#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.252.07:20:18.20#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.252.07:20:18.20#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.252.07:20:18.20#ibcon#enter wrdev, iclass 13, count 0 2006.252.07:20:18.20#ibcon#first serial, iclass 13, count 0 2006.252.07:20:18.20#ibcon#enter sib2, iclass 13, count 0 2006.252.07:20:18.20#ibcon#flushed, iclass 13, count 0 2006.252.07:20:18.20#ibcon#about to write, iclass 13, count 0 2006.252.07:20:18.20#ibcon#wrote, iclass 13, count 0 2006.252.07:20:18.20#ibcon#about to read 3, iclass 13, count 0 2006.252.07:20:18.24#ibcon#read 3, iclass 13, count 0 2006.252.07:20:18.24#ibcon#about to read 4, iclass 13, count 0 2006.252.07:20:18.24#ibcon#read 4, iclass 13, count 0 2006.252.07:20:18.24#ibcon#about to read 5, iclass 13, count 0 2006.252.07:20:18.24#ibcon#read 5, iclass 13, count 0 2006.252.07:20:18.24#ibcon#about to read 6, iclass 13, count 0 2006.252.07:20:18.24#ibcon#read 6, iclass 13, count 0 2006.252.07:20:18.24#ibcon#end of sib2, iclass 13, count 0 2006.252.07:20:18.24#ibcon#*mode == 0, iclass 13, count 0 2006.252.07:20:18.24#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.252.07:20:18.24#ibcon#[25=USB\r\n] 2006.252.07:20:18.24#ibcon#*before write, iclass 13, count 0 2006.252.07:20:18.24#ibcon#enter sib2, iclass 13, count 0 2006.252.07:20:18.24#ibcon#flushed, iclass 13, count 0 2006.252.07:20:18.24#ibcon#about to write, iclass 13, count 0 2006.252.07:20:18.24#ibcon#wrote, iclass 13, count 0 2006.252.07:20:18.24#ibcon#about to read 3, iclass 13, count 0 2006.252.07:20:18.27#ibcon#read 3, iclass 13, count 0 2006.252.07:20:18.27#ibcon#about to read 4, iclass 13, count 0 2006.252.07:20:18.27#ibcon#read 4, iclass 13, count 0 2006.252.07:20:18.27#ibcon#about to read 5, iclass 13, count 0 2006.252.07:20:18.27#ibcon#read 5, iclass 13, count 0 2006.252.07:20:18.27#ibcon#about to read 6, iclass 13, count 0 2006.252.07:20:18.27#ibcon#read 6, iclass 13, count 0 2006.252.07:20:18.27#ibcon#end of sib2, iclass 13, count 0 2006.252.07:20:18.27#ibcon#*after write, iclass 13, count 0 2006.252.07:20:18.27#ibcon#*before return 0, iclass 13, count 0 2006.252.07:20:18.27#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.252.07:20:18.27#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.252.07:20:18.27#ibcon#about to clear, iclass 13 cls_cnt 0 2006.252.07:20:18.27#ibcon#cleared, iclass 13 cls_cnt 0 2006.252.07:20:18.27$vc4f8/valo=8,852.99 2006.252.07:20:18.27#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.252.07:20:18.27#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.252.07:20:18.27#ibcon#ireg 17 cls_cnt 0 2006.252.07:20:18.27#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.252.07:20:18.27#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.252.07:20:18.27#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.252.07:20:18.27#ibcon#enter wrdev, iclass 15, count 0 2006.252.07:20:18.27#ibcon#first serial, iclass 15, count 0 2006.252.07:20:18.27#ibcon#enter sib2, iclass 15, count 0 2006.252.07:20:18.27#ibcon#flushed, iclass 15, count 0 2006.252.07:20:18.27#ibcon#about to write, iclass 15, count 0 2006.252.07:20:18.27#ibcon#wrote, iclass 15, count 0 2006.252.07:20:18.27#ibcon#about to read 3, iclass 15, count 0 2006.252.07:20:18.29#ibcon#read 3, iclass 15, count 0 2006.252.07:20:18.29#ibcon#about to read 4, iclass 15, count 0 2006.252.07:20:18.29#ibcon#read 4, iclass 15, count 0 2006.252.07:20:18.29#ibcon#about to read 5, iclass 15, count 0 2006.252.07:20:18.29#ibcon#read 5, iclass 15, count 0 2006.252.07:20:18.29#ibcon#about to read 6, iclass 15, count 0 2006.252.07:20:18.29#ibcon#read 6, iclass 15, count 0 2006.252.07:20:18.29#ibcon#end of sib2, iclass 15, count 0 2006.252.07:20:18.29#ibcon#*mode == 0, iclass 15, count 0 2006.252.07:20:18.29#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.252.07:20:18.29#ibcon#[26=FRQ=08,852.99\r\n] 2006.252.07:20:18.29#ibcon#*before write, iclass 15, count 0 2006.252.07:20:18.29#ibcon#enter sib2, iclass 15, count 0 2006.252.07:20:18.29#ibcon#flushed, iclass 15, count 0 2006.252.07:20:18.29#ibcon#about to write, iclass 15, count 0 2006.252.07:20:18.29#ibcon#wrote, iclass 15, count 0 2006.252.07:20:18.29#ibcon#about to read 3, iclass 15, count 0 2006.252.07:20:18.33#ibcon#read 3, iclass 15, count 0 2006.252.07:20:18.33#ibcon#about to read 4, iclass 15, count 0 2006.252.07:20:18.33#ibcon#read 4, iclass 15, count 0 2006.252.07:20:18.33#ibcon#about to read 5, iclass 15, count 0 2006.252.07:20:18.33#ibcon#read 5, iclass 15, count 0 2006.252.07:20:18.33#ibcon#about to read 6, iclass 15, count 0 2006.252.07:20:18.33#ibcon#read 6, iclass 15, count 0 2006.252.07:20:18.33#ibcon#end of sib2, iclass 15, count 0 2006.252.07:20:18.33#ibcon#*after write, iclass 15, count 0 2006.252.07:20:18.33#ibcon#*before return 0, iclass 15, count 0 2006.252.07:20:18.33#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.252.07:20:18.33#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.252.07:20:18.33#ibcon#about to clear, iclass 15 cls_cnt 0 2006.252.07:20:18.33#ibcon#cleared, iclass 15 cls_cnt 0 2006.252.07:20:18.33$vc4f8/va=8,7 2006.252.07:20:18.33#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.252.07:20:18.33#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.252.07:20:18.33#ibcon#ireg 11 cls_cnt 2 2006.252.07:20:18.33#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.252.07:20:18.39#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.252.07:20:18.39#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.252.07:20:18.39#ibcon#enter wrdev, iclass 17, count 2 2006.252.07:20:18.39#ibcon#first serial, iclass 17, count 2 2006.252.07:20:18.39#ibcon#enter sib2, iclass 17, count 2 2006.252.07:20:18.39#ibcon#flushed, iclass 17, count 2 2006.252.07:20:18.39#ibcon#about to write, iclass 17, count 2 2006.252.07:20:18.39#ibcon#wrote, iclass 17, count 2 2006.252.07:20:18.39#ibcon#about to read 3, iclass 17, count 2 2006.252.07:20:18.41#ibcon#read 3, iclass 17, count 2 2006.252.07:20:18.41#ibcon#about to read 4, iclass 17, count 2 2006.252.07:20:18.41#ibcon#read 4, iclass 17, count 2 2006.252.07:20:18.41#ibcon#about to read 5, iclass 17, count 2 2006.252.07:20:18.41#ibcon#read 5, iclass 17, count 2 2006.252.07:20:18.41#ibcon#about to read 6, iclass 17, count 2 2006.252.07:20:18.41#ibcon#read 6, iclass 17, count 2 2006.252.07:20:18.41#ibcon#end of sib2, iclass 17, count 2 2006.252.07:20:18.41#ibcon#*mode == 0, iclass 17, count 2 2006.252.07:20:18.41#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.252.07:20:18.41#ibcon#[25=AT08-07\r\n] 2006.252.07:20:18.41#ibcon#*before write, iclass 17, count 2 2006.252.07:20:18.41#ibcon#enter sib2, iclass 17, count 2 2006.252.07:20:18.41#ibcon#flushed, iclass 17, count 2 2006.252.07:20:18.41#ibcon#about to write, iclass 17, count 2 2006.252.07:20:18.41#ibcon#wrote, iclass 17, count 2 2006.252.07:20:18.41#ibcon#about to read 3, iclass 17, count 2 2006.252.07:20:18.44#ibcon#read 3, iclass 17, count 2 2006.252.07:20:18.44#ibcon#about to read 4, iclass 17, count 2 2006.252.07:20:18.44#ibcon#read 4, iclass 17, count 2 2006.252.07:20:18.44#ibcon#about to read 5, iclass 17, count 2 2006.252.07:20:18.44#ibcon#read 5, iclass 17, count 2 2006.252.07:20:18.44#ibcon#about to read 6, iclass 17, count 2 2006.252.07:20:18.44#ibcon#read 6, iclass 17, count 2 2006.252.07:20:18.44#ibcon#end of sib2, iclass 17, count 2 2006.252.07:20:18.44#ibcon#*after write, iclass 17, count 2 2006.252.07:20:18.44#ibcon#*before return 0, iclass 17, count 2 2006.252.07:20:18.44#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.252.07:20:18.44#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.252.07:20:18.44#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.252.07:20:18.44#ibcon#ireg 7 cls_cnt 0 2006.252.07:20:18.44#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.252.07:20:18.56#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.252.07:20:18.56#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.252.07:20:18.56#ibcon#enter wrdev, iclass 17, count 0 2006.252.07:20:18.56#ibcon#first serial, iclass 17, count 0 2006.252.07:20:18.56#ibcon#enter sib2, iclass 17, count 0 2006.252.07:20:18.56#ibcon#flushed, iclass 17, count 0 2006.252.07:20:18.56#ibcon#about to write, iclass 17, count 0 2006.252.07:20:18.56#ibcon#wrote, iclass 17, count 0 2006.252.07:20:18.56#ibcon#about to read 3, iclass 17, count 0 2006.252.07:20:18.58#ibcon#read 3, iclass 17, count 0 2006.252.07:20:18.58#ibcon#about to read 4, iclass 17, count 0 2006.252.07:20:18.58#ibcon#read 4, iclass 17, count 0 2006.252.07:20:18.58#ibcon#about to read 5, iclass 17, count 0 2006.252.07:20:18.58#ibcon#read 5, iclass 17, count 0 2006.252.07:20:18.58#ibcon#about to read 6, iclass 17, count 0 2006.252.07:20:18.58#ibcon#read 6, iclass 17, count 0 2006.252.07:20:18.58#ibcon#end of sib2, iclass 17, count 0 2006.252.07:20:18.58#ibcon#*mode == 0, iclass 17, count 0 2006.252.07:20:18.58#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.252.07:20:18.58#ibcon#[25=USB\r\n] 2006.252.07:20:18.58#ibcon#*before write, iclass 17, count 0 2006.252.07:20:18.58#ibcon#enter sib2, iclass 17, count 0 2006.252.07:20:18.58#ibcon#flushed, iclass 17, count 0 2006.252.07:20:18.58#ibcon#about to write, iclass 17, count 0 2006.252.07:20:18.58#ibcon#wrote, iclass 17, count 0 2006.252.07:20:18.58#ibcon#about to read 3, iclass 17, count 0 2006.252.07:20:18.61#ibcon#read 3, iclass 17, count 0 2006.252.07:20:18.61#ibcon#about to read 4, iclass 17, count 0 2006.252.07:20:18.61#ibcon#read 4, iclass 17, count 0 2006.252.07:20:18.61#ibcon#about to read 5, iclass 17, count 0 2006.252.07:20:18.61#ibcon#read 5, iclass 17, count 0 2006.252.07:20:18.61#ibcon#about to read 6, iclass 17, count 0 2006.252.07:20:18.61#ibcon#read 6, iclass 17, count 0 2006.252.07:20:18.61#ibcon#end of sib2, iclass 17, count 0 2006.252.07:20:18.61#ibcon#*after write, iclass 17, count 0 2006.252.07:20:18.61#ibcon#*before return 0, iclass 17, count 0 2006.252.07:20:18.61#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.252.07:20:18.61#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.252.07:20:18.61#ibcon#about to clear, iclass 17 cls_cnt 0 2006.252.07:20:18.61#ibcon#cleared, iclass 17 cls_cnt 0 2006.252.07:20:18.61$vc4f8/vblo=1,632.99 2006.252.07:20:18.61#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.252.07:20:18.61#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.252.07:20:18.61#ibcon#ireg 17 cls_cnt 0 2006.252.07:20:18.61#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.252.07:20:18.61#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.252.07:20:18.61#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.252.07:20:18.61#ibcon#enter wrdev, iclass 19, count 0 2006.252.07:20:18.61#ibcon#first serial, iclass 19, count 0 2006.252.07:20:18.61#ibcon#enter sib2, iclass 19, count 0 2006.252.07:20:18.61#ibcon#flushed, iclass 19, count 0 2006.252.07:20:18.61#ibcon#about to write, iclass 19, count 0 2006.252.07:20:18.61#ibcon#wrote, iclass 19, count 0 2006.252.07:20:18.61#ibcon#about to read 3, iclass 19, count 0 2006.252.07:20:18.63#ibcon#read 3, iclass 19, count 0 2006.252.07:20:18.63#ibcon#about to read 4, iclass 19, count 0 2006.252.07:20:18.63#ibcon#read 4, iclass 19, count 0 2006.252.07:20:18.63#ibcon#about to read 5, iclass 19, count 0 2006.252.07:20:18.63#ibcon#read 5, iclass 19, count 0 2006.252.07:20:18.63#ibcon#about to read 6, iclass 19, count 0 2006.252.07:20:18.63#ibcon#read 6, iclass 19, count 0 2006.252.07:20:18.63#ibcon#end of sib2, iclass 19, count 0 2006.252.07:20:18.63#ibcon#*mode == 0, iclass 19, count 0 2006.252.07:20:18.63#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.252.07:20:18.63#ibcon#[28=FRQ=01,632.99\r\n] 2006.252.07:20:18.63#ibcon#*before write, iclass 19, count 0 2006.252.07:20:18.63#ibcon#enter sib2, iclass 19, count 0 2006.252.07:20:18.63#ibcon#flushed, iclass 19, count 0 2006.252.07:20:18.63#ibcon#about to write, iclass 19, count 0 2006.252.07:20:18.63#ibcon#wrote, iclass 19, count 0 2006.252.07:20:18.63#ibcon#about to read 3, iclass 19, count 0 2006.252.07:20:18.69#ibcon#read 3, iclass 19, count 0 2006.252.07:20:18.69#ibcon#about to read 4, iclass 19, count 0 2006.252.07:20:18.69#ibcon#read 4, iclass 19, count 0 2006.252.07:20:18.69#ibcon#about to read 5, iclass 19, count 0 2006.252.07:20:18.69#ibcon#read 5, iclass 19, count 0 2006.252.07:20:18.69#ibcon#about to read 6, iclass 19, count 0 2006.252.07:20:18.69#ibcon#read 6, iclass 19, count 0 2006.252.07:20:18.69#ibcon#end of sib2, iclass 19, count 0 2006.252.07:20:18.69#ibcon#*after write, iclass 19, count 0 2006.252.07:20:18.69#ibcon#*before return 0, iclass 19, count 0 2006.252.07:20:18.69#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.252.07:20:18.69#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.252.07:20:18.69#ibcon#about to clear, iclass 19 cls_cnt 0 2006.252.07:20:18.69#ibcon#cleared, iclass 19 cls_cnt 0 2006.252.07:20:18.69$vc4f8/vb=1,4 2006.252.07:20:18.69#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.252.07:20:18.69#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.252.07:20:18.69#ibcon#ireg 11 cls_cnt 2 2006.252.07:20:18.69#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.252.07:20:18.69#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.252.07:20:18.69#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.252.07:20:18.69#ibcon#enter wrdev, iclass 21, count 2 2006.252.07:20:18.69#ibcon#first serial, iclass 21, count 2 2006.252.07:20:18.69#ibcon#enter sib2, iclass 21, count 2 2006.252.07:20:18.69#ibcon#flushed, iclass 21, count 2 2006.252.07:20:18.69#ibcon#about to write, iclass 21, count 2 2006.252.07:20:18.69#ibcon#wrote, iclass 21, count 2 2006.252.07:20:18.69#ibcon#about to read 3, iclass 21, count 2 2006.252.07:20:18.71#ibcon#read 3, iclass 21, count 2 2006.252.07:20:18.71#ibcon#about to read 4, iclass 21, count 2 2006.252.07:20:18.71#ibcon#read 4, iclass 21, count 2 2006.252.07:20:18.71#ibcon#about to read 5, iclass 21, count 2 2006.252.07:20:18.71#ibcon#read 5, iclass 21, count 2 2006.252.07:20:18.71#ibcon#about to read 6, iclass 21, count 2 2006.252.07:20:18.71#ibcon#read 6, iclass 21, count 2 2006.252.07:20:18.71#ibcon#end of sib2, iclass 21, count 2 2006.252.07:20:18.71#ibcon#*mode == 0, iclass 21, count 2 2006.252.07:20:18.71#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.252.07:20:18.71#ibcon#[27=AT01-04\r\n] 2006.252.07:20:18.71#ibcon#*before write, iclass 21, count 2 2006.252.07:20:18.71#ibcon#enter sib2, iclass 21, count 2 2006.252.07:20:18.71#ibcon#flushed, iclass 21, count 2 2006.252.07:20:18.71#ibcon#about to write, iclass 21, count 2 2006.252.07:20:18.71#ibcon#wrote, iclass 21, count 2 2006.252.07:20:18.71#ibcon#about to read 3, iclass 21, count 2 2006.252.07:20:18.75#ibcon#read 3, iclass 21, count 2 2006.252.07:20:18.75#ibcon#about to read 4, iclass 21, count 2 2006.252.07:20:18.75#ibcon#read 4, iclass 21, count 2 2006.252.07:20:18.75#ibcon#about to read 5, iclass 21, count 2 2006.252.07:20:18.75#ibcon#read 5, iclass 21, count 2 2006.252.07:20:18.75#ibcon#about to read 6, iclass 21, count 2 2006.252.07:20:18.75#ibcon#read 6, iclass 21, count 2 2006.252.07:20:18.75#ibcon#end of sib2, iclass 21, count 2 2006.252.07:20:18.75#ibcon#*after write, iclass 21, count 2 2006.252.07:20:18.75#ibcon#*before return 0, iclass 21, count 2 2006.252.07:20:18.75#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.252.07:20:18.75#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.252.07:20:18.75#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.252.07:20:18.75#ibcon#ireg 7 cls_cnt 0 2006.252.07:20:18.75#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.252.07:20:18.87#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.252.07:20:18.87#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.252.07:20:18.87#ibcon#enter wrdev, iclass 21, count 0 2006.252.07:20:18.87#ibcon#first serial, iclass 21, count 0 2006.252.07:20:18.87#ibcon#enter sib2, iclass 21, count 0 2006.252.07:20:18.87#ibcon#flushed, iclass 21, count 0 2006.252.07:20:18.87#ibcon#about to write, iclass 21, count 0 2006.252.07:20:18.87#ibcon#wrote, iclass 21, count 0 2006.252.07:20:18.87#ibcon#about to read 3, iclass 21, count 0 2006.252.07:20:18.89#ibcon#read 3, iclass 21, count 0 2006.252.07:20:18.89#ibcon#about to read 4, iclass 21, count 0 2006.252.07:20:18.89#ibcon#read 4, iclass 21, count 0 2006.252.07:20:18.89#ibcon#about to read 5, iclass 21, count 0 2006.252.07:20:18.89#ibcon#read 5, iclass 21, count 0 2006.252.07:20:18.89#ibcon#about to read 6, iclass 21, count 0 2006.252.07:20:18.89#ibcon#read 6, iclass 21, count 0 2006.252.07:20:18.89#ibcon#end of sib2, iclass 21, count 0 2006.252.07:20:18.89#ibcon#*mode == 0, iclass 21, count 0 2006.252.07:20:18.89#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.252.07:20:18.89#ibcon#[27=USB\r\n] 2006.252.07:20:18.89#ibcon#*before write, iclass 21, count 0 2006.252.07:20:18.89#ibcon#enter sib2, iclass 21, count 0 2006.252.07:20:18.89#ibcon#flushed, iclass 21, count 0 2006.252.07:20:18.89#ibcon#about to write, iclass 21, count 0 2006.252.07:20:18.89#ibcon#wrote, iclass 21, count 0 2006.252.07:20:18.89#ibcon#about to read 3, iclass 21, count 0 2006.252.07:20:18.92#ibcon#read 3, iclass 21, count 0 2006.252.07:20:18.92#ibcon#about to read 4, iclass 21, count 0 2006.252.07:20:18.92#ibcon#read 4, iclass 21, count 0 2006.252.07:20:18.92#ibcon#about to read 5, iclass 21, count 0 2006.252.07:20:18.92#ibcon#read 5, iclass 21, count 0 2006.252.07:20:18.92#ibcon#about to read 6, iclass 21, count 0 2006.252.07:20:18.92#ibcon#read 6, iclass 21, count 0 2006.252.07:20:18.92#ibcon#end of sib2, iclass 21, count 0 2006.252.07:20:18.92#ibcon#*after write, iclass 21, count 0 2006.252.07:20:18.92#ibcon#*before return 0, iclass 21, count 0 2006.252.07:20:18.92#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.252.07:20:18.92#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.252.07:20:18.92#ibcon#about to clear, iclass 21 cls_cnt 0 2006.252.07:20:18.92#ibcon#cleared, iclass 21 cls_cnt 0 2006.252.07:20:18.92$vc4f8/vblo=2,640.99 2006.252.07:20:18.92#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.252.07:20:18.92#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.252.07:20:18.92#ibcon#ireg 17 cls_cnt 0 2006.252.07:20:18.92#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.252.07:20:18.92#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.252.07:20:18.92#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.252.07:20:18.92#ibcon#enter wrdev, iclass 23, count 0 2006.252.07:20:18.92#ibcon#first serial, iclass 23, count 0 2006.252.07:20:18.92#ibcon#enter sib2, iclass 23, count 0 2006.252.07:20:18.92#ibcon#flushed, iclass 23, count 0 2006.252.07:20:18.92#ibcon#about to write, iclass 23, count 0 2006.252.07:20:18.92#ibcon#wrote, iclass 23, count 0 2006.252.07:20:18.92#ibcon#about to read 3, iclass 23, count 0 2006.252.07:20:18.94#ibcon#read 3, iclass 23, count 0 2006.252.07:20:18.94#ibcon#about to read 4, iclass 23, count 0 2006.252.07:20:18.94#ibcon#read 4, iclass 23, count 0 2006.252.07:20:18.94#ibcon#about to read 5, iclass 23, count 0 2006.252.07:20:18.94#ibcon#read 5, iclass 23, count 0 2006.252.07:20:18.94#ibcon#about to read 6, iclass 23, count 0 2006.252.07:20:18.94#ibcon#read 6, iclass 23, count 0 2006.252.07:20:18.94#ibcon#end of sib2, iclass 23, count 0 2006.252.07:20:18.94#ibcon#*mode == 0, iclass 23, count 0 2006.252.07:20:18.94#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.252.07:20:18.94#ibcon#[28=FRQ=02,640.99\r\n] 2006.252.07:20:18.94#ibcon#*before write, iclass 23, count 0 2006.252.07:20:18.94#ibcon#enter sib2, iclass 23, count 0 2006.252.07:20:18.94#ibcon#flushed, iclass 23, count 0 2006.252.07:20:18.94#ibcon#about to write, iclass 23, count 0 2006.252.07:20:18.94#ibcon#wrote, iclass 23, count 0 2006.252.07:20:18.94#ibcon#about to read 3, iclass 23, count 0 2006.252.07:20:18.98#ibcon#read 3, iclass 23, count 0 2006.252.07:20:18.98#ibcon#about to read 4, iclass 23, count 0 2006.252.07:20:18.98#ibcon#read 4, iclass 23, count 0 2006.252.07:20:18.98#ibcon#about to read 5, iclass 23, count 0 2006.252.07:20:18.98#ibcon#read 5, iclass 23, count 0 2006.252.07:20:18.98#ibcon#about to read 6, iclass 23, count 0 2006.252.07:20:18.98#ibcon#read 6, iclass 23, count 0 2006.252.07:20:18.98#ibcon#end of sib2, iclass 23, count 0 2006.252.07:20:18.98#ibcon#*after write, iclass 23, count 0 2006.252.07:20:18.98#ibcon#*before return 0, iclass 23, count 0 2006.252.07:20:18.98#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.252.07:20:18.98#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.252.07:20:18.98#ibcon#about to clear, iclass 23 cls_cnt 0 2006.252.07:20:18.98#ibcon#cleared, iclass 23 cls_cnt 0 2006.252.07:20:18.98$vc4f8/vb=2,5 2006.252.07:20:18.98#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.252.07:20:18.98#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.252.07:20:18.98#ibcon#ireg 11 cls_cnt 2 2006.252.07:20:18.98#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.252.07:20:19.04#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.252.07:20:19.04#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.252.07:20:19.04#ibcon#enter wrdev, iclass 25, count 2 2006.252.07:20:19.04#ibcon#first serial, iclass 25, count 2 2006.252.07:20:19.04#ibcon#enter sib2, iclass 25, count 2 2006.252.07:20:19.04#ibcon#flushed, iclass 25, count 2 2006.252.07:20:19.04#ibcon#about to write, iclass 25, count 2 2006.252.07:20:19.04#ibcon#wrote, iclass 25, count 2 2006.252.07:20:19.04#ibcon#about to read 3, iclass 25, count 2 2006.252.07:20:19.06#ibcon#read 3, iclass 25, count 2 2006.252.07:20:19.06#ibcon#about to read 4, iclass 25, count 2 2006.252.07:20:19.06#ibcon#read 4, iclass 25, count 2 2006.252.07:20:19.06#ibcon#about to read 5, iclass 25, count 2 2006.252.07:20:19.06#ibcon#read 5, iclass 25, count 2 2006.252.07:20:19.06#ibcon#about to read 6, iclass 25, count 2 2006.252.07:20:19.06#ibcon#read 6, iclass 25, count 2 2006.252.07:20:19.06#ibcon#end of sib2, iclass 25, count 2 2006.252.07:20:19.06#ibcon#*mode == 0, iclass 25, count 2 2006.252.07:20:19.06#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.252.07:20:19.06#ibcon#[27=AT02-05\r\n] 2006.252.07:20:19.06#ibcon#*before write, iclass 25, count 2 2006.252.07:20:19.06#ibcon#enter sib2, iclass 25, count 2 2006.252.07:20:19.06#ibcon#flushed, iclass 25, count 2 2006.252.07:20:19.06#ibcon#about to write, iclass 25, count 2 2006.252.07:20:19.06#ibcon#wrote, iclass 25, count 2 2006.252.07:20:19.06#ibcon#about to read 3, iclass 25, count 2 2006.252.07:20:19.09#ibcon#read 3, iclass 25, count 2 2006.252.07:20:19.09#ibcon#about to read 4, iclass 25, count 2 2006.252.07:20:19.09#ibcon#read 4, iclass 25, count 2 2006.252.07:20:19.09#ibcon#about to read 5, iclass 25, count 2 2006.252.07:20:19.09#ibcon#read 5, iclass 25, count 2 2006.252.07:20:19.09#ibcon#about to read 6, iclass 25, count 2 2006.252.07:20:19.09#ibcon#read 6, iclass 25, count 2 2006.252.07:20:19.09#ibcon#end of sib2, iclass 25, count 2 2006.252.07:20:19.09#ibcon#*after write, iclass 25, count 2 2006.252.07:20:19.09#ibcon#*before return 0, iclass 25, count 2 2006.252.07:20:19.09#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.252.07:20:19.09#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.252.07:20:19.09#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.252.07:20:19.09#ibcon#ireg 7 cls_cnt 0 2006.252.07:20:19.09#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.252.07:20:19.21#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.252.07:20:19.21#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.252.07:20:19.21#ibcon#enter wrdev, iclass 25, count 0 2006.252.07:20:19.21#ibcon#first serial, iclass 25, count 0 2006.252.07:20:19.21#ibcon#enter sib2, iclass 25, count 0 2006.252.07:20:19.21#ibcon#flushed, iclass 25, count 0 2006.252.07:20:19.21#ibcon#about to write, iclass 25, count 0 2006.252.07:20:19.21#ibcon#wrote, iclass 25, count 0 2006.252.07:20:19.21#ibcon#about to read 3, iclass 25, count 0 2006.252.07:20:19.23#ibcon#read 3, iclass 25, count 0 2006.252.07:20:19.23#ibcon#about to read 4, iclass 25, count 0 2006.252.07:20:19.23#ibcon#read 4, iclass 25, count 0 2006.252.07:20:19.23#ibcon#about to read 5, iclass 25, count 0 2006.252.07:20:19.23#ibcon#read 5, iclass 25, count 0 2006.252.07:20:19.23#ibcon#about to read 6, iclass 25, count 0 2006.252.07:20:19.23#ibcon#read 6, iclass 25, count 0 2006.252.07:20:19.23#ibcon#end of sib2, iclass 25, count 0 2006.252.07:20:19.23#ibcon#*mode == 0, iclass 25, count 0 2006.252.07:20:19.23#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.252.07:20:19.23#ibcon#[27=USB\r\n] 2006.252.07:20:19.23#ibcon#*before write, iclass 25, count 0 2006.252.07:20:19.23#ibcon#enter sib2, iclass 25, count 0 2006.252.07:20:19.23#ibcon#flushed, iclass 25, count 0 2006.252.07:20:19.23#ibcon#about to write, iclass 25, count 0 2006.252.07:20:19.23#ibcon#wrote, iclass 25, count 0 2006.252.07:20:19.23#ibcon#about to read 3, iclass 25, count 0 2006.252.07:20:19.26#ibcon#read 3, iclass 25, count 0 2006.252.07:20:19.26#ibcon#about to read 4, iclass 25, count 0 2006.252.07:20:19.26#ibcon#read 4, iclass 25, count 0 2006.252.07:20:19.26#ibcon#about to read 5, iclass 25, count 0 2006.252.07:20:19.26#ibcon#read 5, iclass 25, count 0 2006.252.07:20:19.26#ibcon#about to read 6, iclass 25, count 0 2006.252.07:20:19.26#ibcon#read 6, iclass 25, count 0 2006.252.07:20:19.26#ibcon#end of sib2, iclass 25, count 0 2006.252.07:20:19.26#ibcon#*after write, iclass 25, count 0 2006.252.07:20:19.26#ibcon#*before return 0, iclass 25, count 0 2006.252.07:20:19.26#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.252.07:20:19.26#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.252.07:20:19.26#ibcon#about to clear, iclass 25 cls_cnt 0 2006.252.07:20:19.26#ibcon#cleared, iclass 25 cls_cnt 0 2006.252.07:20:19.26$vc4f8/vblo=3,656.99 2006.252.07:20:19.26#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.252.07:20:19.26#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.252.07:20:19.26#ibcon#ireg 17 cls_cnt 0 2006.252.07:20:19.26#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.252.07:20:19.26#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.252.07:20:19.26#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.252.07:20:19.26#ibcon#enter wrdev, iclass 27, count 0 2006.252.07:20:19.26#ibcon#first serial, iclass 27, count 0 2006.252.07:20:19.26#ibcon#enter sib2, iclass 27, count 0 2006.252.07:20:19.26#ibcon#flushed, iclass 27, count 0 2006.252.07:20:19.26#ibcon#about to write, iclass 27, count 0 2006.252.07:20:19.26#ibcon#wrote, iclass 27, count 0 2006.252.07:20:19.26#ibcon#about to read 3, iclass 27, count 0 2006.252.07:20:19.28#ibcon#read 3, iclass 27, count 0 2006.252.07:20:19.28#ibcon#about to read 4, iclass 27, count 0 2006.252.07:20:19.28#ibcon#read 4, iclass 27, count 0 2006.252.07:20:19.28#ibcon#about to read 5, iclass 27, count 0 2006.252.07:20:19.28#ibcon#read 5, iclass 27, count 0 2006.252.07:20:19.28#ibcon#about to read 6, iclass 27, count 0 2006.252.07:20:19.28#ibcon#read 6, iclass 27, count 0 2006.252.07:20:19.28#ibcon#end of sib2, iclass 27, count 0 2006.252.07:20:19.28#ibcon#*mode == 0, iclass 27, count 0 2006.252.07:20:19.28#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.252.07:20:19.28#ibcon#[28=FRQ=03,656.99\r\n] 2006.252.07:20:19.28#ibcon#*before write, iclass 27, count 0 2006.252.07:20:19.28#ibcon#enter sib2, iclass 27, count 0 2006.252.07:20:19.28#ibcon#flushed, iclass 27, count 0 2006.252.07:20:19.28#ibcon#about to write, iclass 27, count 0 2006.252.07:20:19.28#ibcon#wrote, iclass 27, count 0 2006.252.07:20:19.28#ibcon#about to read 3, iclass 27, count 0 2006.252.07:20:19.32#ibcon#read 3, iclass 27, count 0 2006.252.07:20:19.32#ibcon#about to read 4, iclass 27, count 0 2006.252.07:20:19.32#ibcon#read 4, iclass 27, count 0 2006.252.07:20:19.32#ibcon#about to read 5, iclass 27, count 0 2006.252.07:20:19.32#ibcon#read 5, iclass 27, count 0 2006.252.07:20:19.32#ibcon#about to read 6, iclass 27, count 0 2006.252.07:20:19.32#ibcon#read 6, iclass 27, count 0 2006.252.07:20:19.32#ibcon#end of sib2, iclass 27, count 0 2006.252.07:20:19.32#ibcon#*after write, iclass 27, count 0 2006.252.07:20:19.32#ibcon#*before return 0, iclass 27, count 0 2006.252.07:20:19.32#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.252.07:20:19.32#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.252.07:20:19.32#ibcon#about to clear, iclass 27 cls_cnt 0 2006.252.07:20:19.32#ibcon#cleared, iclass 27 cls_cnt 0 2006.252.07:20:19.32$vc4f8/vb=3,4 2006.252.07:20:19.32#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.252.07:20:19.32#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.252.07:20:19.32#ibcon#ireg 11 cls_cnt 2 2006.252.07:20:19.32#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.252.07:20:19.38#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.252.07:20:19.38#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.252.07:20:19.38#ibcon#enter wrdev, iclass 29, count 2 2006.252.07:20:19.38#ibcon#first serial, iclass 29, count 2 2006.252.07:20:19.38#ibcon#enter sib2, iclass 29, count 2 2006.252.07:20:19.38#ibcon#flushed, iclass 29, count 2 2006.252.07:20:19.38#ibcon#about to write, iclass 29, count 2 2006.252.07:20:19.38#ibcon#wrote, iclass 29, count 2 2006.252.07:20:19.38#ibcon#about to read 3, iclass 29, count 2 2006.252.07:20:19.40#ibcon#read 3, iclass 29, count 2 2006.252.07:20:19.40#ibcon#about to read 4, iclass 29, count 2 2006.252.07:20:19.40#ibcon#read 4, iclass 29, count 2 2006.252.07:20:19.40#ibcon#about to read 5, iclass 29, count 2 2006.252.07:20:19.40#ibcon#read 5, iclass 29, count 2 2006.252.07:20:19.40#ibcon#about to read 6, iclass 29, count 2 2006.252.07:20:19.40#ibcon#read 6, iclass 29, count 2 2006.252.07:20:19.40#ibcon#end of sib2, iclass 29, count 2 2006.252.07:20:19.40#ibcon#*mode == 0, iclass 29, count 2 2006.252.07:20:19.40#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.252.07:20:19.40#ibcon#[27=AT03-04\r\n] 2006.252.07:20:19.40#ibcon#*before write, iclass 29, count 2 2006.252.07:20:19.40#ibcon#enter sib2, iclass 29, count 2 2006.252.07:20:19.40#ibcon#flushed, iclass 29, count 2 2006.252.07:20:19.40#ibcon#about to write, iclass 29, count 2 2006.252.07:20:19.40#ibcon#wrote, iclass 29, count 2 2006.252.07:20:19.40#ibcon#about to read 3, iclass 29, count 2 2006.252.07:20:19.43#ibcon#read 3, iclass 29, count 2 2006.252.07:20:19.43#ibcon#about to read 4, iclass 29, count 2 2006.252.07:20:19.43#ibcon#read 4, iclass 29, count 2 2006.252.07:20:19.43#ibcon#about to read 5, iclass 29, count 2 2006.252.07:20:19.43#ibcon#read 5, iclass 29, count 2 2006.252.07:20:19.43#ibcon#about to read 6, iclass 29, count 2 2006.252.07:20:19.43#ibcon#read 6, iclass 29, count 2 2006.252.07:20:19.43#ibcon#end of sib2, iclass 29, count 2 2006.252.07:20:19.43#ibcon#*after write, iclass 29, count 2 2006.252.07:20:19.43#ibcon#*before return 0, iclass 29, count 2 2006.252.07:20:19.43#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.252.07:20:19.43#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.252.07:20:19.43#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.252.07:20:19.43#ibcon#ireg 7 cls_cnt 0 2006.252.07:20:19.43#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.252.07:20:19.55#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.252.07:20:19.55#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.252.07:20:19.55#ibcon#enter wrdev, iclass 29, count 0 2006.252.07:20:19.55#ibcon#first serial, iclass 29, count 0 2006.252.07:20:19.55#ibcon#enter sib2, iclass 29, count 0 2006.252.07:20:19.55#ibcon#flushed, iclass 29, count 0 2006.252.07:20:19.55#ibcon#about to write, iclass 29, count 0 2006.252.07:20:19.55#ibcon#wrote, iclass 29, count 0 2006.252.07:20:19.55#ibcon#about to read 3, iclass 29, count 0 2006.252.07:20:19.57#ibcon#read 3, iclass 29, count 0 2006.252.07:20:19.57#ibcon#about to read 4, iclass 29, count 0 2006.252.07:20:19.57#ibcon#read 4, iclass 29, count 0 2006.252.07:20:19.57#ibcon#about to read 5, iclass 29, count 0 2006.252.07:20:19.57#ibcon#read 5, iclass 29, count 0 2006.252.07:20:19.57#ibcon#about to read 6, iclass 29, count 0 2006.252.07:20:19.57#ibcon#read 6, iclass 29, count 0 2006.252.07:20:19.57#ibcon#end of sib2, iclass 29, count 0 2006.252.07:20:19.57#ibcon#*mode == 0, iclass 29, count 0 2006.252.07:20:19.57#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.252.07:20:19.57#ibcon#[27=USB\r\n] 2006.252.07:20:19.57#ibcon#*before write, iclass 29, count 0 2006.252.07:20:19.57#ibcon#enter sib2, iclass 29, count 0 2006.252.07:20:19.57#ibcon#flushed, iclass 29, count 0 2006.252.07:20:19.57#ibcon#about to write, iclass 29, count 0 2006.252.07:20:19.57#ibcon#wrote, iclass 29, count 0 2006.252.07:20:19.57#ibcon#about to read 3, iclass 29, count 0 2006.252.07:20:19.60#ibcon#read 3, iclass 29, count 0 2006.252.07:20:19.60#ibcon#about to read 4, iclass 29, count 0 2006.252.07:20:19.60#ibcon#read 4, iclass 29, count 0 2006.252.07:20:19.60#ibcon#about to read 5, iclass 29, count 0 2006.252.07:20:19.60#ibcon#read 5, iclass 29, count 0 2006.252.07:20:19.60#ibcon#about to read 6, iclass 29, count 0 2006.252.07:20:19.60#ibcon#read 6, iclass 29, count 0 2006.252.07:20:19.60#ibcon#end of sib2, iclass 29, count 0 2006.252.07:20:19.60#ibcon#*after write, iclass 29, count 0 2006.252.07:20:19.60#ibcon#*before return 0, iclass 29, count 0 2006.252.07:20:19.60#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.252.07:20:19.60#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.252.07:20:19.60#ibcon#about to clear, iclass 29 cls_cnt 0 2006.252.07:20:19.60#ibcon#cleared, iclass 29 cls_cnt 0 2006.252.07:20:19.60$vc4f8/vblo=4,712.99 2006.252.07:20:19.60#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.252.07:20:19.60#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.252.07:20:19.60#ibcon#ireg 17 cls_cnt 0 2006.252.07:20:19.60#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.252.07:20:19.60#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.252.07:20:19.60#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.252.07:20:19.60#ibcon#enter wrdev, iclass 31, count 0 2006.252.07:20:19.60#ibcon#first serial, iclass 31, count 0 2006.252.07:20:19.60#ibcon#enter sib2, iclass 31, count 0 2006.252.07:20:19.60#ibcon#flushed, iclass 31, count 0 2006.252.07:20:19.60#ibcon#about to write, iclass 31, count 0 2006.252.07:20:19.60#ibcon#wrote, iclass 31, count 0 2006.252.07:20:19.60#ibcon#about to read 3, iclass 31, count 0 2006.252.07:20:19.62#ibcon#read 3, iclass 31, count 0 2006.252.07:20:19.62#ibcon#about to read 4, iclass 31, count 0 2006.252.07:20:19.62#ibcon#read 4, iclass 31, count 0 2006.252.07:20:19.62#ibcon#about to read 5, iclass 31, count 0 2006.252.07:20:19.62#ibcon#read 5, iclass 31, count 0 2006.252.07:20:19.62#ibcon#about to read 6, iclass 31, count 0 2006.252.07:20:19.62#ibcon#read 6, iclass 31, count 0 2006.252.07:20:19.62#ibcon#end of sib2, iclass 31, count 0 2006.252.07:20:19.62#ibcon#*mode == 0, iclass 31, count 0 2006.252.07:20:19.62#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.252.07:20:19.62#ibcon#[28=FRQ=04,712.99\r\n] 2006.252.07:20:19.62#ibcon#*before write, iclass 31, count 0 2006.252.07:20:19.62#ibcon#enter sib2, iclass 31, count 0 2006.252.07:20:19.62#ibcon#flushed, iclass 31, count 0 2006.252.07:20:19.62#ibcon#about to write, iclass 31, count 0 2006.252.07:20:19.62#ibcon#wrote, iclass 31, count 0 2006.252.07:20:19.62#ibcon#about to read 3, iclass 31, count 0 2006.252.07:20:19.66#ibcon#read 3, iclass 31, count 0 2006.252.07:20:19.66#ibcon#about to read 4, iclass 31, count 0 2006.252.07:20:19.66#ibcon#read 4, iclass 31, count 0 2006.252.07:20:19.66#ibcon#about to read 5, iclass 31, count 0 2006.252.07:20:19.66#ibcon#read 5, iclass 31, count 0 2006.252.07:20:19.66#ibcon#about to read 6, iclass 31, count 0 2006.252.07:20:19.66#ibcon#read 6, iclass 31, count 0 2006.252.07:20:19.66#ibcon#end of sib2, iclass 31, count 0 2006.252.07:20:19.66#ibcon#*after write, iclass 31, count 0 2006.252.07:20:19.66#ibcon#*before return 0, iclass 31, count 0 2006.252.07:20:19.66#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.252.07:20:19.66#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.252.07:20:19.66#ibcon#about to clear, iclass 31 cls_cnt 0 2006.252.07:20:19.66#ibcon#cleared, iclass 31 cls_cnt 0 2006.252.07:20:19.66$vc4f8/vb=4,4 2006.252.07:20:19.66#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.252.07:20:19.66#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.252.07:20:19.66#ibcon#ireg 11 cls_cnt 2 2006.252.07:20:19.66#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.252.07:20:19.72#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.252.07:20:19.72#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.252.07:20:19.72#ibcon#enter wrdev, iclass 33, count 2 2006.252.07:20:19.72#ibcon#first serial, iclass 33, count 2 2006.252.07:20:19.72#ibcon#enter sib2, iclass 33, count 2 2006.252.07:20:19.72#ibcon#flushed, iclass 33, count 2 2006.252.07:20:19.72#ibcon#about to write, iclass 33, count 2 2006.252.07:20:19.72#ibcon#wrote, iclass 33, count 2 2006.252.07:20:19.72#ibcon#about to read 3, iclass 33, count 2 2006.252.07:20:19.74#ibcon#read 3, iclass 33, count 2 2006.252.07:20:19.74#ibcon#about to read 4, iclass 33, count 2 2006.252.07:20:19.74#ibcon#read 4, iclass 33, count 2 2006.252.07:20:19.74#ibcon#about to read 5, iclass 33, count 2 2006.252.07:20:19.74#ibcon#read 5, iclass 33, count 2 2006.252.07:20:19.74#ibcon#about to read 6, iclass 33, count 2 2006.252.07:20:19.74#ibcon#read 6, iclass 33, count 2 2006.252.07:20:19.74#ibcon#end of sib2, iclass 33, count 2 2006.252.07:20:19.74#ibcon#*mode == 0, iclass 33, count 2 2006.252.07:20:19.74#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.252.07:20:19.74#ibcon#[27=AT04-04\r\n] 2006.252.07:20:19.74#ibcon#*before write, iclass 33, count 2 2006.252.07:20:19.74#ibcon#enter sib2, iclass 33, count 2 2006.252.07:20:19.74#ibcon#flushed, iclass 33, count 2 2006.252.07:20:19.74#ibcon#about to write, iclass 33, count 2 2006.252.07:20:19.74#ibcon#wrote, iclass 33, count 2 2006.252.07:20:19.74#ibcon#about to read 3, iclass 33, count 2 2006.252.07:20:19.77#ibcon#read 3, iclass 33, count 2 2006.252.07:20:19.77#ibcon#about to read 4, iclass 33, count 2 2006.252.07:20:19.77#ibcon#read 4, iclass 33, count 2 2006.252.07:20:19.77#ibcon#about to read 5, iclass 33, count 2 2006.252.07:20:19.77#ibcon#read 5, iclass 33, count 2 2006.252.07:20:19.77#ibcon#about to read 6, iclass 33, count 2 2006.252.07:20:19.77#ibcon#read 6, iclass 33, count 2 2006.252.07:20:19.77#ibcon#end of sib2, iclass 33, count 2 2006.252.07:20:19.77#ibcon#*after write, iclass 33, count 2 2006.252.07:20:19.77#ibcon#*before return 0, iclass 33, count 2 2006.252.07:20:19.77#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.252.07:20:19.77#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.252.07:20:19.77#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.252.07:20:19.77#ibcon#ireg 7 cls_cnt 0 2006.252.07:20:19.77#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.252.07:20:19.89#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.252.07:20:19.89#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.252.07:20:19.89#ibcon#enter wrdev, iclass 33, count 0 2006.252.07:20:19.89#ibcon#first serial, iclass 33, count 0 2006.252.07:20:19.89#ibcon#enter sib2, iclass 33, count 0 2006.252.07:20:19.89#ibcon#flushed, iclass 33, count 0 2006.252.07:20:19.89#ibcon#about to write, iclass 33, count 0 2006.252.07:20:19.89#ibcon#wrote, iclass 33, count 0 2006.252.07:20:19.89#ibcon#about to read 3, iclass 33, count 0 2006.252.07:20:19.91#ibcon#read 3, iclass 33, count 0 2006.252.07:20:19.91#ibcon#about to read 4, iclass 33, count 0 2006.252.07:20:19.91#ibcon#read 4, iclass 33, count 0 2006.252.07:20:19.91#ibcon#about to read 5, iclass 33, count 0 2006.252.07:20:19.91#ibcon#read 5, iclass 33, count 0 2006.252.07:20:19.91#ibcon#about to read 6, iclass 33, count 0 2006.252.07:20:19.91#ibcon#read 6, iclass 33, count 0 2006.252.07:20:19.91#ibcon#end of sib2, iclass 33, count 0 2006.252.07:20:19.91#ibcon#*mode == 0, iclass 33, count 0 2006.252.07:20:19.91#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.252.07:20:19.91#ibcon#[27=USB\r\n] 2006.252.07:20:19.91#ibcon#*before write, iclass 33, count 0 2006.252.07:20:19.91#ibcon#enter sib2, iclass 33, count 0 2006.252.07:20:19.91#ibcon#flushed, iclass 33, count 0 2006.252.07:20:19.91#ibcon#about to write, iclass 33, count 0 2006.252.07:20:19.91#ibcon#wrote, iclass 33, count 0 2006.252.07:20:19.91#ibcon#about to read 3, iclass 33, count 0 2006.252.07:20:19.94#ibcon#read 3, iclass 33, count 0 2006.252.07:20:19.94#ibcon#about to read 4, iclass 33, count 0 2006.252.07:20:19.94#ibcon#read 4, iclass 33, count 0 2006.252.07:20:19.94#ibcon#about to read 5, iclass 33, count 0 2006.252.07:20:19.94#ibcon#read 5, iclass 33, count 0 2006.252.07:20:19.94#ibcon#about to read 6, iclass 33, count 0 2006.252.07:20:19.94#ibcon#read 6, iclass 33, count 0 2006.252.07:20:19.94#ibcon#end of sib2, iclass 33, count 0 2006.252.07:20:19.94#ibcon#*after write, iclass 33, count 0 2006.252.07:20:19.94#ibcon#*before return 0, iclass 33, count 0 2006.252.07:20:19.94#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.252.07:20:19.94#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.252.07:20:19.94#ibcon#about to clear, iclass 33 cls_cnt 0 2006.252.07:20:19.94#ibcon#cleared, iclass 33 cls_cnt 0 2006.252.07:20:19.94$vc4f8/vblo=5,744.99 2006.252.07:20:19.94#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.252.07:20:19.94#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.252.07:20:19.94#ibcon#ireg 17 cls_cnt 0 2006.252.07:20:19.94#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.252.07:20:19.94#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.252.07:20:19.94#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.252.07:20:19.94#ibcon#enter wrdev, iclass 35, count 0 2006.252.07:20:19.94#ibcon#first serial, iclass 35, count 0 2006.252.07:20:19.94#ibcon#enter sib2, iclass 35, count 0 2006.252.07:20:19.94#ibcon#flushed, iclass 35, count 0 2006.252.07:20:19.94#ibcon#about to write, iclass 35, count 0 2006.252.07:20:19.94#ibcon#wrote, iclass 35, count 0 2006.252.07:20:19.94#ibcon#about to read 3, iclass 35, count 0 2006.252.07:20:19.97#ibcon#read 3, iclass 35, count 0 2006.252.07:20:19.97#ibcon#about to read 4, iclass 35, count 0 2006.252.07:20:19.97#ibcon#read 4, iclass 35, count 0 2006.252.07:20:19.97#ibcon#about to read 5, iclass 35, count 0 2006.252.07:20:19.97#ibcon#read 5, iclass 35, count 0 2006.252.07:20:19.97#ibcon#about to read 6, iclass 35, count 0 2006.252.07:20:19.97#ibcon#read 6, iclass 35, count 0 2006.252.07:20:19.97#ibcon#end of sib2, iclass 35, count 0 2006.252.07:20:19.97#ibcon#*mode == 0, iclass 35, count 0 2006.252.07:20:19.97#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.252.07:20:19.97#ibcon#[28=FRQ=05,744.99\r\n] 2006.252.07:20:19.97#ibcon#*before write, iclass 35, count 0 2006.252.07:20:19.97#ibcon#enter sib2, iclass 35, count 0 2006.252.07:20:19.97#ibcon#flushed, iclass 35, count 0 2006.252.07:20:19.97#ibcon#about to write, iclass 35, count 0 2006.252.07:20:19.97#ibcon#wrote, iclass 35, count 0 2006.252.07:20:19.97#ibcon#about to read 3, iclass 35, count 0 2006.252.07:20:20.01#ibcon#read 3, iclass 35, count 0 2006.252.07:20:20.01#ibcon#about to read 4, iclass 35, count 0 2006.252.07:20:20.01#ibcon#read 4, iclass 35, count 0 2006.252.07:20:20.01#ibcon#about to read 5, iclass 35, count 0 2006.252.07:20:20.01#ibcon#read 5, iclass 35, count 0 2006.252.07:20:20.01#ibcon#about to read 6, iclass 35, count 0 2006.252.07:20:20.01#ibcon#read 6, iclass 35, count 0 2006.252.07:20:20.01#ibcon#end of sib2, iclass 35, count 0 2006.252.07:20:20.01#ibcon#*after write, iclass 35, count 0 2006.252.07:20:20.01#ibcon#*before return 0, iclass 35, count 0 2006.252.07:20:20.01#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.252.07:20:20.01#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.252.07:20:20.01#ibcon#about to clear, iclass 35 cls_cnt 0 2006.252.07:20:20.01#ibcon#cleared, iclass 35 cls_cnt 0 2006.252.07:20:20.01$vc4f8/vb=5,4 2006.252.07:20:20.01#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.252.07:20:20.01#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.252.07:20:20.01#ibcon#ireg 11 cls_cnt 2 2006.252.07:20:20.01#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.252.07:20:20.06#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.252.07:20:20.06#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.252.07:20:20.06#ibcon#enter wrdev, iclass 37, count 2 2006.252.07:20:20.06#ibcon#first serial, iclass 37, count 2 2006.252.07:20:20.06#ibcon#enter sib2, iclass 37, count 2 2006.252.07:20:20.06#ibcon#flushed, iclass 37, count 2 2006.252.07:20:20.06#ibcon#about to write, iclass 37, count 2 2006.252.07:20:20.06#ibcon#wrote, iclass 37, count 2 2006.252.07:20:20.06#ibcon#about to read 3, iclass 37, count 2 2006.252.07:20:20.08#ibcon#read 3, iclass 37, count 2 2006.252.07:20:20.08#ibcon#about to read 4, iclass 37, count 2 2006.252.07:20:20.08#ibcon#read 4, iclass 37, count 2 2006.252.07:20:20.08#ibcon#about to read 5, iclass 37, count 2 2006.252.07:20:20.08#ibcon#read 5, iclass 37, count 2 2006.252.07:20:20.08#ibcon#about to read 6, iclass 37, count 2 2006.252.07:20:20.08#ibcon#read 6, iclass 37, count 2 2006.252.07:20:20.08#ibcon#end of sib2, iclass 37, count 2 2006.252.07:20:20.08#ibcon#*mode == 0, iclass 37, count 2 2006.252.07:20:20.08#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.252.07:20:20.08#ibcon#[27=AT05-04\r\n] 2006.252.07:20:20.08#ibcon#*before write, iclass 37, count 2 2006.252.07:20:20.08#ibcon#enter sib2, iclass 37, count 2 2006.252.07:20:20.08#ibcon#flushed, iclass 37, count 2 2006.252.07:20:20.08#ibcon#about to write, iclass 37, count 2 2006.252.07:20:20.08#ibcon#wrote, iclass 37, count 2 2006.252.07:20:20.08#ibcon#about to read 3, iclass 37, count 2 2006.252.07:20:20.11#ibcon#read 3, iclass 37, count 2 2006.252.07:20:20.11#ibcon#about to read 4, iclass 37, count 2 2006.252.07:20:20.11#ibcon#read 4, iclass 37, count 2 2006.252.07:20:20.11#ibcon#about to read 5, iclass 37, count 2 2006.252.07:20:20.11#ibcon#read 5, iclass 37, count 2 2006.252.07:20:20.11#ibcon#about to read 6, iclass 37, count 2 2006.252.07:20:20.11#ibcon#read 6, iclass 37, count 2 2006.252.07:20:20.11#ibcon#end of sib2, iclass 37, count 2 2006.252.07:20:20.11#ibcon#*after write, iclass 37, count 2 2006.252.07:20:20.11#ibcon#*before return 0, iclass 37, count 2 2006.252.07:20:20.11#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.252.07:20:20.11#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.252.07:20:20.11#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.252.07:20:20.11#ibcon#ireg 7 cls_cnt 0 2006.252.07:20:20.11#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.252.07:20:20.23#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.252.07:20:20.23#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.252.07:20:20.23#ibcon#enter wrdev, iclass 37, count 0 2006.252.07:20:20.23#ibcon#first serial, iclass 37, count 0 2006.252.07:20:20.23#ibcon#enter sib2, iclass 37, count 0 2006.252.07:20:20.23#ibcon#flushed, iclass 37, count 0 2006.252.07:20:20.23#ibcon#about to write, iclass 37, count 0 2006.252.07:20:20.23#ibcon#wrote, iclass 37, count 0 2006.252.07:20:20.23#ibcon#about to read 3, iclass 37, count 0 2006.252.07:20:20.25#ibcon#read 3, iclass 37, count 0 2006.252.07:20:20.25#ibcon#about to read 4, iclass 37, count 0 2006.252.07:20:20.25#ibcon#read 4, iclass 37, count 0 2006.252.07:20:20.25#ibcon#about to read 5, iclass 37, count 0 2006.252.07:20:20.25#ibcon#read 5, iclass 37, count 0 2006.252.07:20:20.25#ibcon#about to read 6, iclass 37, count 0 2006.252.07:20:20.25#ibcon#read 6, iclass 37, count 0 2006.252.07:20:20.25#ibcon#end of sib2, iclass 37, count 0 2006.252.07:20:20.25#ibcon#*mode == 0, iclass 37, count 0 2006.252.07:20:20.25#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.252.07:20:20.25#ibcon#[27=USB\r\n] 2006.252.07:20:20.25#ibcon#*before write, iclass 37, count 0 2006.252.07:20:20.25#ibcon#enter sib2, iclass 37, count 0 2006.252.07:20:20.25#ibcon#flushed, iclass 37, count 0 2006.252.07:20:20.25#ibcon#about to write, iclass 37, count 0 2006.252.07:20:20.25#ibcon#wrote, iclass 37, count 0 2006.252.07:20:20.25#ibcon#about to read 3, iclass 37, count 0 2006.252.07:20:20.28#ibcon#read 3, iclass 37, count 0 2006.252.07:20:20.28#ibcon#about to read 4, iclass 37, count 0 2006.252.07:20:20.28#ibcon#read 4, iclass 37, count 0 2006.252.07:20:20.28#ibcon#about to read 5, iclass 37, count 0 2006.252.07:20:20.28#ibcon#read 5, iclass 37, count 0 2006.252.07:20:20.28#ibcon#about to read 6, iclass 37, count 0 2006.252.07:20:20.28#ibcon#read 6, iclass 37, count 0 2006.252.07:20:20.28#ibcon#end of sib2, iclass 37, count 0 2006.252.07:20:20.28#ibcon#*after write, iclass 37, count 0 2006.252.07:20:20.28#ibcon#*before return 0, iclass 37, count 0 2006.252.07:20:20.28#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.252.07:20:20.28#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.252.07:20:20.28#ibcon#about to clear, iclass 37 cls_cnt 0 2006.252.07:20:20.28#ibcon#cleared, iclass 37 cls_cnt 0 2006.252.07:20:20.28$vc4f8/vblo=6,752.99 2006.252.07:20:20.28#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.252.07:20:20.28#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.252.07:20:20.28#ibcon#ireg 17 cls_cnt 0 2006.252.07:20:20.28#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.252.07:20:20.28#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.252.07:20:20.28#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.252.07:20:20.28#ibcon#enter wrdev, iclass 39, count 0 2006.252.07:20:20.28#ibcon#first serial, iclass 39, count 0 2006.252.07:20:20.28#ibcon#enter sib2, iclass 39, count 0 2006.252.07:20:20.28#ibcon#flushed, iclass 39, count 0 2006.252.07:20:20.28#ibcon#about to write, iclass 39, count 0 2006.252.07:20:20.28#ibcon#wrote, iclass 39, count 0 2006.252.07:20:20.28#ibcon#about to read 3, iclass 39, count 0 2006.252.07:20:20.30#ibcon#read 3, iclass 39, count 0 2006.252.07:20:20.30#ibcon#about to read 4, iclass 39, count 0 2006.252.07:20:20.30#ibcon#read 4, iclass 39, count 0 2006.252.07:20:20.30#ibcon#about to read 5, iclass 39, count 0 2006.252.07:20:20.30#ibcon#read 5, iclass 39, count 0 2006.252.07:20:20.30#ibcon#about to read 6, iclass 39, count 0 2006.252.07:20:20.30#ibcon#read 6, iclass 39, count 0 2006.252.07:20:20.30#ibcon#end of sib2, iclass 39, count 0 2006.252.07:20:20.30#ibcon#*mode == 0, iclass 39, count 0 2006.252.07:20:20.30#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.252.07:20:20.30#ibcon#[28=FRQ=06,752.99\r\n] 2006.252.07:20:20.30#ibcon#*before write, iclass 39, count 0 2006.252.07:20:20.30#ibcon#enter sib2, iclass 39, count 0 2006.252.07:20:20.30#ibcon#flushed, iclass 39, count 0 2006.252.07:20:20.30#ibcon#about to write, iclass 39, count 0 2006.252.07:20:20.30#ibcon#wrote, iclass 39, count 0 2006.252.07:20:20.30#ibcon#about to read 3, iclass 39, count 0 2006.252.07:20:20.34#ibcon#read 3, iclass 39, count 0 2006.252.07:20:20.34#ibcon#about to read 4, iclass 39, count 0 2006.252.07:20:20.34#ibcon#read 4, iclass 39, count 0 2006.252.07:20:20.34#ibcon#about to read 5, iclass 39, count 0 2006.252.07:20:20.34#ibcon#read 5, iclass 39, count 0 2006.252.07:20:20.34#ibcon#about to read 6, iclass 39, count 0 2006.252.07:20:20.34#ibcon#read 6, iclass 39, count 0 2006.252.07:20:20.34#ibcon#end of sib2, iclass 39, count 0 2006.252.07:20:20.34#ibcon#*after write, iclass 39, count 0 2006.252.07:20:20.34#ibcon#*before return 0, iclass 39, count 0 2006.252.07:20:20.34#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.252.07:20:20.34#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.252.07:20:20.34#ibcon#about to clear, iclass 39 cls_cnt 0 2006.252.07:20:20.34#ibcon#cleared, iclass 39 cls_cnt 0 2006.252.07:20:20.34$vc4f8/vb=6,4 2006.252.07:20:20.34#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.252.07:20:20.34#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.252.07:20:20.34#ibcon#ireg 11 cls_cnt 2 2006.252.07:20:20.34#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.252.07:20:20.40#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.252.07:20:20.40#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.252.07:20:20.40#ibcon#enter wrdev, iclass 3, count 2 2006.252.07:20:20.40#ibcon#first serial, iclass 3, count 2 2006.252.07:20:20.40#ibcon#enter sib2, iclass 3, count 2 2006.252.07:20:20.40#ibcon#flushed, iclass 3, count 2 2006.252.07:20:20.40#ibcon#about to write, iclass 3, count 2 2006.252.07:20:20.40#ibcon#wrote, iclass 3, count 2 2006.252.07:20:20.40#ibcon#about to read 3, iclass 3, count 2 2006.252.07:20:20.42#ibcon#read 3, iclass 3, count 2 2006.252.07:20:20.42#ibcon#about to read 4, iclass 3, count 2 2006.252.07:20:20.42#ibcon#read 4, iclass 3, count 2 2006.252.07:20:20.42#ibcon#about to read 5, iclass 3, count 2 2006.252.07:20:20.42#ibcon#read 5, iclass 3, count 2 2006.252.07:20:20.42#ibcon#about to read 6, iclass 3, count 2 2006.252.07:20:20.42#ibcon#read 6, iclass 3, count 2 2006.252.07:20:20.42#ibcon#end of sib2, iclass 3, count 2 2006.252.07:20:20.42#ibcon#*mode == 0, iclass 3, count 2 2006.252.07:20:20.42#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.252.07:20:20.42#ibcon#[27=AT06-04\r\n] 2006.252.07:20:20.42#ibcon#*before write, iclass 3, count 2 2006.252.07:20:20.42#ibcon#enter sib2, iclass 3, count 2 2006.252.07:20:20.42#ibcon#flushed, iclass 3, count 2 2006.252.07:20:20.42#ibcon#about to write, iclass 3, count 2 2006.252.07:20:20.42#ibcon#wrote, iclass 3, count 2 2006.252.07:20:20.42#ibcon#about to read 3, iclass 3, count 2 2006.252.07:20:20.45#ibcon#read 3, iclass 3, count 2 2006.252.07:20:20.45#ibcon#about to read 4, iclass 3, count 2 2006.252.07:20:20.45#ibcon#read 4, iclass 3, count 2 2006.252.07:20:20.45#ibcon#about to read 5, iclass 3, count 2 2006.252.07:20:20.45#ibcon#read 5, iclass 3, count 2 2006.252.07:20:20.45#ibcon#about to read 6, iclass 3, count 2 2006.252.07:20:20.45#ibcon#read 6, iclass 3, count 2 2006.252.07:20:20.45#ibcon#end of sib2, iclass 3, count 2 2006.252.07:20:20.45#ibcon#*after write, iclass 3, count 2 2006.252.07:20:20.45#ibcon#*before return 0, iclass 3, count 2 2006.252.07:20:20.45#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.252.07:20:20.45#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.252.07:20:20.45#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.252.07:20:20.45#ibcon#ireg 7 cls_cnt 0 2006.252.07:20:20.45#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.252.07:20:20.47#abcon#<5=/05 3.5 5.9 27.70 901011.1\r\n> 2006.252.07:20:20.49#abcon#{5=INTERFACE CLEAR} 2006.252.07:20:20.55#abcon#[5=S1D000X0/0*\r\n] 2006.252.07:20:20.57#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.252.07:20:20.57#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.252.07:20:20.57#ibcon#enter wrdev, iclass 3, count 0 2006.252.07:20:20.57#ibcon#first serial, iclass 3, count 0 2006.252.07:20:20.57#ibcon#enter sib2, iclass 3, count 0 2006.252.07:20:20.57#ibcon#flushed, iclass 3, count 0 2006.252.07:20:20.57#ibcon#about to write, iclass 3, count 0 2006.252.07:20:20.57#ibcon#wrote, iclass 3, count 0 2006.252.07:20:20.57#ibcon#about to read 3, iclass 3, count 0 2006.252.07:20:20.59#ibcon#read 3, iclass 3, count 0 2006.252.07:20:20.59#ibcon#about to read 4, iclass 3, count 0 2006.252.07:20:20.59#ibcon#read 4, iclass 3, count 0 2006.252.07:20:20.59#ibcon#about to read 5, iclass 3, count 0 2006.252.07:20:20.59#ibcon#read 5, iclass 3, count 0 2006.252.07:20:20.59#ibcon#about to read 6, iclass 3, count 0 2006.252.07:20:20.59#ibcon#read 6, iclass 3, count 0 2006.252.07:20:20.59#ibcon#end of sib2, iclass 3, count 0 2006.252.07:20:20.59#ibcon#*mode == 0, iclass 3, count 0 2006.252.07:20:20.59#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.252.07:20:20.59#ibcon#[27=USB\r\n] 2006.252.07:20:20.59#ibcon#*before write, iclass 3, count 0 2006.252.07:20:20.59#ibcon#enter sib2, iclass 3, count 0 2006.252.07:20:20.59#ibcon#flushed, iclass 3, count 0 2006.252.07:20:20.59#ibcon#about to write, iclass 3, count 0 2006.252.07:20:20.59#ibcon#wrote, iclass 3, count 0 2006.252.07:20:20.59#ibcon#about to read 3, iclass 3, count 0 2006.252.07:20:20.62#ibcon#read 3, iclass 3, count 0 2006.252.07:20:20.62#ibcon#about to read 4, iclass 3, count 0 2006.252.07:20:20.62#ibcon#read 4, iclass 3, count 0 2006.252.07:20:20.62#ibcon#about to read 5, iclass 3, count 0 2006.252.07:20:20.62#ibcon#read 5, iclass 3, count 0 2006.252.07:20:20.62#ibcon#about to read 6, iclass 3, count 0 2006.252.07:20:20.62#ibcon#read 6, iclass 3, count 0 2006.252.07:20:20.62#ibcon#end of sib2, iclass 3, count 0 2006.252.07:20:20.62#ibcon#*after write, iclass 3, count 0 2006.252.07:20:20.62#ibcon#*before return 0, iclass 3, count 0 2006.252.07:20:20.62#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.252.07:20:20.62#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.252.07:20:20.62#ibcon#about to clear, iclass 3 cls_cnt 0 2006.252.07:20:20.62#ibcon#cleared, iclass 3 cls_cnt 0 2006.252.07:20:20.62$vc4f8/vabw=wide 2006.252.07:20:20.62#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.252.07:20:20.62#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.252.07:20:20.62#ibcon#ireg 8 cls_cnt 0 2006.252.07:20:20.62#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.252.07:20:20.62#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.252.07:20:20.62#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.252.07:20:20.62#ibcon#enter wrdev, iclass 11, count 0 2006.252.07:20:20.62#ibcon#first serial, iclass 11, count 0 2006.252.07:20:20.62#ibcon#enter sib2, iclass 11, count 0 2006.252.07:20:20.62#ibcon#flushed, iclass 11, count 0 2006.252.07:20:20.62#ibcon#about to write, iclass 11, count 0 2006.252.07:20:20.62#ibcon#wrote, iclass 11, count 0 2006.252.07:20:20.62#ibcon#about to read 3, iclass 11, count 0 2006.252.07:20:20.64#ibcon#read 3, iclass 11, count 0 2006.252.07:20:20.64#ibcon#about to read 4, iclass 11, count 0 2006.252.07:20:20.64#ibcon#read 4, iclass 11, count 0 2006.252.07:20:20.64#ibcon#about to read 5, iclass 11, count 0 2006.252.07:20:20.64#ibcon#read 5, iclass 11, count 0 2006.252.07:20:20.64#ibcon#about to read 6, iclass 11, count 0 2006.252.07:20:20.64#ibcon#read 6, iclass 11, count 0 2006.252.07:20:20.64#ibcon#end of sib2, iclass 11, count 0 2006.252.07:20:20.64#ibcon#*mode == 0, iclass 11, count 0 2006.252.07:20:20.64#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.252.07:20:20.64#ibcon#[25=BW32\r\n] 2006.252.07:20:20.64#ibcon#*before write, iclass 11, count 0 2006.252.07:20:20.64#ibcon#enter sib2, iclass 11, count 0 2006.252.07:20:20.64#ibcon#flushed, iclass 11, count 0 2006.252.07:20:20.64#ibcon#about to write, iclass 11, count 0 2006.252.07:20:20.64#ibcon#wrote, iclass 11, count 0 2006.252.07:20:20.64#ibcon#about to read 3, iclass 11, count 0 2006.252.07:20:20.67#ibcon#read 3, iclass 11, count 0 2006.252.07:20:20.67#ibcon#about to read 4, iclass 11, count 0 2006.252.07:20:20.67#ibcon#read 4, iclass 11, count 0 2006.252.07:20:20.67#ibcon#about to read 5, iclass 11, count 0 2006.252.07:20:20.67#ibcon#read 5, iclass 11, count 0 2006.252.07:20:20.67#ibcon#about to read 6, iclass 11, count 0 2006.252.07:20:20.67#ibcon#read 6, iclass 11, count 0 2006.252.07:20:20.67#ibcon#end of sib2, iclass 11, count 0 2006.252.07:20:20.67#ibcon#*after write, iclass 11, count 0 2006.252.07:20:20.67#ibcon#*before return 0, iclass 11, count 0 2006.252.07:20:20.67#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.252.07:20:20.67#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.252.07:20:20.67#ibcon#about to clear, iclass 11 cls_cnt 0 2006.252.07:20:20.67#ibcon#cleared, iclass 11 cls_cnt 0 2006.252.07:20:20.67$vc4f8/vbbw=wide 2006.252.07:20:20.67#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.252.07:20:20.67#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.252.07:20:20.67#ibcon#ireg 8 cls_cnt 0 2006.252.07:20:20.67#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.252.07:20:20.74#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.252.07:20:20.74#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.252.07:20:20.74#ibcon#enter wrdev, iclass 13, count 0 2006.252.07:20:20.74#ibcon#first serial, iclass 13, count 0 2006.252.07:20:20.74#ibcon#enter sib2, iclass 13, count 0 2006.252.07:20:20.74#ibcon#flushed, iclass 13, count 0 2006.252.07:20:20.74#ibcon#about to write, iclass 13, count 0 2006.252.07:20:20.74#ibcon#wrote, iclass 13, count 0 2006.252.07:20:20.74#ibcon#about to read 3, iclass 13, count 0 2006.252.07:20:20.76#ibcon#read 3, iclass 13, count 0 2006.252.07:20:20.76#ibcon#about to read 4, iclass 13, count 0 2006.252.07:20:20.76#ibcon#read 4, iclass 13, count 0 2006.252.07:20:20.76#ibcon#about to read 5, iclass 13, count 0 2006.252.07:20:20.76#ibcon#read 5, iclass 13, count 0 2006.252.07:20:20.76#ibcon#about to read 6, iclass 13, count 0 2006.252.07:20:20.76#ibcon#read 6, iclass 13, count 0 2006.252.07:20:20.76#ibcon#end of sib2, iclass 13, count 0 2006.252.07:20:20.76#ibcon#*mode == 0, iclass 13, count 0 2006.252.07:20:20.76#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.252.07:20:20.76#ibcon#[27=BW32\r\n] 2006.252.07:20:20.76#ibcon#*before write, iclass 13, count 0 2006.252.07:20:20.76#ibcon#enter sib2, iclass 13, count 0 2006.252.07:20:20.76#ibcon#flushed, iclass 13, count 0 2006.252.07:20:20.76#ibcon#about to write, iclass 13, count 0 2006.252.07:20:20.76#ibcon#wrote, iclass 13, count 0 2006.252.07:20:20.76#ibcon#about to read 3, iclass 13, count 0 2006.252.07:20:20.79#ibcon#read 3, iclass 13, count 0 2006.252.07:20:20.79#ibcon#about to read 4, iclass 13, count 0 2006.252.07:20:20.79#ibcon#read 4, iclass 13, count 0 2006.252.07:20:20.79#ibcon#about to read 5, iclass 13, count 0 2006.252.07:20:20.79#ibcon#read 5, iclass 13, count 0 2006.252.07:20:20.79#ibcon#about to read 6, iclass 13, count 0 2006.252.07:20:20.79#ibcon#read 6, iclass 13, count 0 2006.252.07:20:20.79#ibcon#end of sib2, iclass 13, count 0 2006.252.07:20:20.79#ibcon#*after write, iclass 13, count 0 2006.252.07:20:20.79#ibcon#*before return 0, iclass 13, count 0 2006.252.07:20:20.79#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.252.07:20:20.79#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.252.07:20:20.79#ibcon#about to clear, iclass 13 cls_cnt 0 2006.252.07:20:20.79#ibcon#cleared, iclass 13 cls_cnt 0 2006.252.07:20:20.79$4f8m12a/ifd4f 2006.252.07:20:20.79&ifd4f/lo= 2006.252.07:20:20.79&ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.252.07:20:20.79&ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.252.07:20:20.79&ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.252.07:20:20.79&ifd4f/patch= 2006.252.07:20:20.79&ifd4f/patch=lo1,a1,a2,a3,a4 2006.252.07:20:20.79&ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.252.07:20:20.79&ifd4f/patch=lo3,a5,a6,a7,a8 2006.252.07:20:20.79$ifd4f/lo= 2006.252.07:20:20.79$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.252.07:20:20.79$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.252.07:20:20.79$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.252.07:20:20.79$ifd4f/patch= 2006.252.07:20:20.79$ifd4f/patch=lo1,a1,a2,a3,a4 2006.252.07:20:20.79$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.252.07:20:20.79$ifd4f/patch=lo3,a5,a6,a7,a8 2006.252.07:20:20.79$4f8m12a/"form=m,16.000,1:2 2006.252.07:20:20.79$4f8m12a/"tpicd 2006.252.07:20:20.79$4f8m12a/echo=off 2006.252.07:20:20.79$4f8m12a/xlog=off 2006.252.07:20:20.79:!2006.252.07:29:50 2006.252.07:20:35.13#trakl#Source acquired 2006.252.07:20:35.13#flagr#flagr/antenna,acquired 2006.252.07:29:50.00:preob 2006.252.07:29:50.00&preob/onsource 2006.252.07:29:51.14/onsource/TRACKING 2006.252.07:29:51.14:!2006.252.07:30:00 2006.252.07:30:00.00:data_valid=on 2006.252.07:30:00.00:midob 2006.252.07:30:00.00&midob/onsource 2006.252.07:30:00.00&midob/wx 2006.252.07:30:00.00&midob/cable 2006.252.07:30:00.00&midob/va 2006.252.07:30:00.00&midob/valo 2006.252.07:30:00.00&midob/vb 2006.252.07:30:00.00&midob/vblo 2006.252.07:30:00.00&midob/vabw 2006.252.07:30:00.00&midob/vbbw 2006.252.07:30:00.00&midob/"form 2006.252.07:30:00.00&midob/xfe 2006.252.07:30:00.00&midob/ifatt 2006.252.07:30:00.00&midob/clockoff 2006.252.07:30:00.00&midob/sy=logmail 2006.252.07:30:00.00&midob/"sy=run setcl adapt & 2006.252.07:30:00.14/onsource/TRACKING 2006.252.07:30:00.14/wx/27.55,1011.2,90 2006.252.07:30:00.19/cable/+6.4068E-03 2006.252.07:30:01.29/va/01,08,usb,yes,33,34 2006.252.07:30:01.29/va/02,07,usb,yes,32,34 2006.252.07:30:01.29/va/03,06,usb,yes,34,35 2006.252.07:30:01.29/va/04,07,usb,yes,33,36 2006.252.07:30:01.29/va/05,07,usb,yes,36,38 2006.252.07:30:01.29/va/06,07,usb,yes,31,31 2006.252.07:30:01.29/va/07,07,usb,yes,31,31 2006.252.07:30:01.29/va/08,07,usb,yes,33,33 2006.252.07:30:01.52/valo/01,532.99,yes,locked 2006.252.07:30:01.52/valo/02,572.99,yes,locked 2006.252.07:30:01.52/valo/03,672.99,yes,locked 2006.252.07:30:01.52/valo/04,832.99,yes,locked 2006.252.07:30:01.52/valo/05,652.99,yes,locked 2006.252.07:30:01.52/valo/06,772.99,yes,locked 2006.252.07:30:01.52/valo/07,832.99,yes,locked 2006.252.07:30:01.52/valo/08,852.99,yes,locked 2006.252.07:30:02.61/vb/01,04,usb,yes,31,29 2006.252.07:30:02.61/vb/02,05,usb,yes,29,30 2006.252.07:30:02.61/vb/03,04,usb,yes,29,33 2006.252.07:30:02.61/vb/04,04,usb,yes,30,30 2006.252.07:30:02.61/vb/05,04,usb,yes,28,32 2006.252.07:30:02.61/vb/06,04,usb,yes,29,32 2006.252.07:30:02.61/vb/07,04,usb,yes,31,31 2006.252.07:30:02.61/vb/08,04,usb,yes,29,32 2006.252.07:30:02.85/vblo/01,632.99,yes,locked 2006.252.07:30:02.85/vblo/02,640.99,yes,locked 2006.252.07:30:02.85/vblo/03,656.99,yes,locked 2006.252.07:30:02.85/vblo/04,712.99,yes,locked 2006.252.07:30:02.85/vblo/05,744.99,yes,locked 2006.252.07:30:02.85/vblo/06,752.99,yes,locked 2006.252.07:30:02.85/vblo/07,734.99,yes,locked 2006.252.07:30:02.85/vblo/08,744.99,yes,locked 2006.252.07:30:03.00/vabw/8 2006.252.07:30:03.15/vbbw/8 2006.252.07:30:03.24/xfe/off,on,14.2 2006.252.07:30:03.62/ifatt/23,28,28,28 2006.252.07:30:04.08/fmout-gps/S +4.64E-07 2006.252.07:30:04.15:!2006.252.07:31:00 2006.252.07:31:00.00:data_valid=off 2006.252.07:31:00.00:postob 2006.252.07:31:00.00&postob/cable 2006.252.07:31:00.01&postob/wx 2006.252.07:31:00.01&postob/clockoff 2006.252.07:31:00.20/cable/+6.4089E-03 2006.252.07:31:00.20/wx/27.54,1011.2,90 2006.252.07:31:01.08/fmout-gps/S +4.66E-07 2006.252.07:31:01.08:scan_name=252-0733,k06252,80 2006.252.07:31:01.08:source=1219+044,122222.55,041315.8,2000.0,ccw 2006.252.07:31:01.14#flagr#flagr/antenna,new-source 2006.252.07:31:02.14:checkk5 2006.252.07:31:02.14&checkk5/chk_autoobs=1 2006.252.07:31:02.14&checkk5/chk_autoobs=2 2006.252.07:31:02.15&checkk5/chk_autoobs=3 2006.252.07:31:02.15&checkk5/chk_autoobs=4 2006.252.07:31:02.15&checkk5/chk_obsdata=1 2006.252.07:31:02.16&checkk5/chk_obsdata=2 2006.252.07:31:02.16&checkk5/chk_obsdata=3 2006.252.07:31:02.16&checkk5/chk_obsdata=4 2006.252.07:31:02.16&checkk5/k5log=1 2006.252.07:31:02.16&checkk5/k5log=2 2006.252.07:31:02.16&checkk5/k5log=3 2006.252.07:31:02.16&checkk5/k5log=4 2006.252.07:31:02.16&checkk5/obsinfo 2006.252.07:31:02.56/chk_autoobs//k5ts1/ autoobs is running! 2006.252.07:31:02.94/chk_autoobs//k5ts2/ autoobs is running! 2006.252.07:31:03.33/chk_autoobs//k5ts3/ autoobs is running! 2006.252.07:31:03.73/chk_autoobs//k5ts4/ autoobs is running! 2006.252.07:31:04.11/chk_obsdata//k5ts1/T2520730??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.07:31:04.48/chk_obsdata//k5ts2/T2520730??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.07:31:04.85/chk_obsdata//k5ts3/T2520730??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.07:31:05.22/chk_obsdata//k5ts4/T2520730??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.07:31:05.93/k5log//k5ts1_log_newline 2006.252.07:31:06.63/k5log//k5ts2_log_newline 2006.252.07:31:07.31/k5log//k5ts3_log_newline 2006.252.07:31:08.00/k5log//k5ts4_log_newline 2006.252.07:31:08.02/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.252.07:31:08.02:4f8m12a=1 2006.252.07:31:08.02$4f8m12a/echo=on 2006.252.07:31:08.02$4f8m12a/pcalon 2006.252.07:31:08.02$pcalon/"no phase cal control is implemented here 2006.252.07:31:08.02$4f8m12a/"tpicd=stop 2006.252.07:31:08.02$4f8m12a/vc4f8 2006.252.07:31:08.02$vc4f8/valo=1,532.99 2006.252.07:31:08.03#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.252.07:31:08.03#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.252.07:31:08.03#ibcon#ireg 17 cls_cnt 0 2006.252.07:31:08.03#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.252.07:31:08.03#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.252.07:31:08.03#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.252.07:31:08.03#ibcon#enter wrdev, iclass 16, count 0 2006.252.07:31:08.03#ibcon#first serial, iclass 16, count 0 2006.252.07:31:08.03#ibcon#enter sib2, iclass 16, count 0 2006.252.07:31:08.03#ibcon#flushed, iclass 16, count 0 2006.252.07:31:08.03#ibcon#about to write, iclass 16, count 0 2006.252.07:31:08.03#ibcon#wrote, iclass 16, count 0 2006.252.07:31:08.03#ibcon#about to read 3, iclass 16, count 0 2006.252.07:31:08.07#ibcon#read 3, iclass 16, count 0 2006.252.07:31:08.07#ibcon#about to read 4, iclass 16, count 0 2006.252.07:31:08.07#ibcon#read 4, iclass 16, count 0 2006.252.07:31:08.07#ibcon#about to read 5, iclass 16, count 0 2006.252.07:31:08.07#ibcon#read 5, iclass 16, count 0 2006.252.07:31:08.07#ibcon#about to read 6, iclass 16, count 0 2006.252.07:31:08.07#ibcon#read 6, iclass 16, count 0 2006.252.07:31:08.07#ibcon#end of sib2, iclass 16, count 0 2006.252.07:31:08.07#ibcon#*mode == 0, iclass 16, count 0 2006.252.07:31:08.07#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.252.07:31:08.07#ibcon#[26=FRQ=01,532.99\r\n] 2006.252.07:31:08.07#ibcon#*before write, iclass 16, count 0 2006.252.07:31:08.07#ibcon#enter sib2, iclass 16, count 0 2006.252.07:31:08.07#ibcon#flushed, iclass 16, count 0 2006.252.07:31:08.07#ibcon#about to write, iclass 16, count 0 2006.252.07:31:08.07#ibcon#wrote, iclass 16, count 0 2006.252.07:31:08.07#ibcon#about to read 3, iclass 16, count 0 2006.252.07:31:08.12#ibcon#read 3, iclass 16, count 0 2006.252.07:31:08.12#ibcon#about to read 4, iclass 16, count 0 2006.252.07:31:08.12#ibcon#read 4, iclass 16, count 0 2006.252.07:31:08.12#ibcon#about to read 5, iclass 16, count 0 2006.252.07:31:08.12#ibcon#read 5, iclass 16, count 0 2006.252.07:31:08.12#ibcon#about to read 6, iclass 16, count 0 2006.252.07:31:08.12#ibcon#read 6, iclass 16, count 0 2006.252.07:31:08.12#ibcon#end of sib2, iclass 16, count 0 2006.252.07:31:08.12#ibcon#*after write, iclass 16, count 0 2006.252.07:31:08.12#ibcon#*before return 0, iclass 16, count 0 2006.252.07:31:08.12#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.252.07:31:08.12#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.252.07:31:08.12#ibcon#about to clear, iclass 16 cls_cnt 0 2006.252.07:31:08.12#ibcon#cleared, iclass 16 cls_cnt 0 2006.252.07:31:08.12$vc4f8/va=1,8 2006.252.07:31:08.12#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.252.07:31:08.12#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.252.07:31:08.12#ibcon#ireg 11 cls_cnt 2 2006.252.07:31:08.12#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.252.07:31:08.12#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.252.07:31:08.12#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.252.07:31:08.12#ibcon#enter wrdev, iclass 18, count 2 2006.252.07:31:08.12#ibcon#first serial, iclass 18, count 2 2006.252.07:31:08.12#ibcon#enter sib2, iclass 18, count 2 2006.252.07:31:08.12#ibcon#flushed, iclass 18, count 2 2006.252.07:31:08.12#ibcon#about to write, iclass 18, count 2 2006.252.07:31:08.12#ibcon#wrote, iclass 18, count 2 2006.252.07:31:08.12#ibcon#about to read 3, iclass 18, count 2 2006.252.07:31:08.14#ibcon#read 3, iclass 18, count 2 2006.252.07:31:08.14#ibcon#about to read 4, iclass 18, count 2 2006.252.07:31:08.14#ibcon#read 4, iclass 18, count 2 2006.252.07:31:08.14#ibcon#about to read 5, iclass 18, count 2 2006.252.07:31:08.14#ibcon#read 5, iclass 18, count 2 2006.252.07:31:08.14#ibcon#about to read 6, iclass 18, count 2 2006.252.07:31:08.14#ibcon#read 6, iclass 18, count 2 2006.252.07:31:08.14#ibcon#end of sib2, iclass 18, count 2 2006.252.07:31:08.14#ibcon#*mode == 0, iclass 18, count 2 2006.252.07:31:08.14#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.252.07:31:08.14#ibcon#[25=AT01-08\r\n] 2006.252.07:31:08.14#ibcon#*before write, iclass 18, count 2 2006.252.07:31:08.14#ibcon#enter sib2, iclass 18, count 2 2006.252.07:31:08.14#ibcon#flushed, iclass 18, count 2 2006.252.07:31:08.14#ibcon#about to write, iclass 18, count 2 2006.252.07:31:08.14#ibcon#wrote, iclass 18, count 2 2006.252.07:31:08.14#ibcon#about to read 3, iclass 18, count 2 2006.252.07:31:08.18#ibcon#read 3, iclass 18, count 2 2006.252.07:31:08.18#ibcon#about to read 4, iclass 18, count 2 2006.252.07:31:08.18#ibcon#read 4, iclass 18, count 2 2006.252.07:31:08.18#ibcon#about to read 5, iclass 18, count 2 2006.252.07:31:08.18#ibcon#read 5, iclass 18, count 2 2006.252.07:31:08.18#ibcon#about to read 6, iclass 18, count 2 2006.252.07:31:08.18#ibcon#read 6, iclass 18, count 2 2006.252.07:31:08.18#ibcon#end of sib2, iclass 18, count 2 2006.252.07:31:08.18#ibcon#*after write, iclass 18, count 2 2006.252.07:31:08.18#ibcon#*before return 0, iclass 18, count 2 2006.252.07:31:08.18#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.252.07:31:08.18#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.252.07:31:08.18#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.252.07:31:08.18#ibcon#ireg 7 cls_cnt 0 2006.252.07:31:08.18#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.252.07:31:08.30#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.252.07:31:08.30#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.252.07:31:08.30#ibcon#enter wrdev, iclass 18, count 0 2006.252.07:31:08.30#ibcon#first serial, iclass 18, count 0 2006.252.07:31:08.30#ibcon#enter sib2, iclass 18, count 0 2006.252.07:31:08.30#ibcon#flushed, iclass 18, count 0 2006.252.07:31:08.30#ibcon#about to write, iclass 18, count 0 2006.252.07:31:08.30#ibcon#wrote, iclass 18, count 0 2006.252.07:31:08.30#ibcon#about to read 3, iclass 18, count 0 2006.252.07:31:08.32#ibcon#read 3, iclass 18, count 0 2006.252.07:31:08.32#ibcon#about to read 4, iclass 18, count 0 2006.252.07:31:08.32#ibcon#read 4, iclass 18, count 0 2006.252.07:31:08.32#ibcon#about to read 5, iclass 18, count 0 2006.252.07:31:08.32#ibcon#read 5, iclass 18, count 0 2006.252.07:31:08.32#ibcon#about to read 6, iclass 18, count 0 2006.252.07:31:08.32#ibcon#read 6, iclass 18, count 0 2006.252.07:31:08.32#ibcon#end of sib2, iclass 18, count 0 2006.252.07:31:08.32#ibcon#*mode == 0, iclass 18, count 0 2006.252.07:31:08.32#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.252.07:31:08.32#ibcon#[25=USB\r\n] 2006.252.07:31:08.32#ibcon#*before write, iclass 18, count 0 2006.252.07:31:08.32#ibcon#enter sib2, iclass 18, count 0 2006.252.07:31:08.32#ibcon#flushed, iclass 18, count 0 2006.252.07:31:08.32#ibcon#about to write, iclass 18, count 0 2006.252.07:31:08.32#ibcon#wrote, iclass 18, count 0 2006.252.07:31:08.32#ibcon#about to read 3, iclass 18, count 0 2006.252.07:31:08.35#ibcon#read 3, iclass 18, count 0 2006.252.07:31:08.35#ibcon#about to read 4, iclass 18, count 0 2006.252.07:31:08.35#ibcon#read 4, iclass 18, count 0 2006.252.07:31:08.35#ibcon#about to read 5, iclass 18, count 0 2006.252.07:31:08.35#ibcon#read 5, iclass 18, count 0 2006.252.07:31:08.35#ibcon#about to read 6, iclass 18, count 0 2006.252.07:31:08.35#ibcon#read 6, iclass 18, count 0 2006.252.07:31:08.35#ibcon#end of sib2, iclass 18, count 0 2006.252.07:31:08.35#ibcon#*after write, iclass 18, count 0 2006.252.07:31:08.35#ibcon#*before return 0, iclass 18, count 0 2006.252.07:31:08.35#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.252.07:31:08.35#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.252.07:31:08.35#ibcon#about to clear, iclass 18 cls_cnt 0 2006.252.07:31:08.35#ibcon#cleared, iclass 18 cls_cnt 0 2006.252.07:31:08.35$vc4f8/valo=2,572.99 2006.252.07:31:08.35#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.252.07:31:08.35#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.252.07:31:08.35#ibcon#ireg 17 cls_cnt 0 2006.252.07:31:08.35#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.252.07:31:08.35#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.252.07:31:08.35#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.252.07:31:08.35#ibcon#enter wrdev, iclass 20, count 0 2006.252.07:31:08.35#ibcon#first serial, iclass 20, count 0 2006.252.07:31:08.35#ibcon#enter sib2, iclass 20, count 0 2006.252.07:31:08.35#ibcon#flushed, iclass 20, count 0 2006.252.07:31:08.35#ibcon#about to write, iclass 20, count 0 2006.252.07:31:08.35#ibcon#wrote, iclass 20, count 0 2006.252.07:31:08.35#ibcon#about to read 3, iclass 20, count 0 2006.252.07:31:08.37#ibcon#read 3, iclass 20, count 0 2006.252.07:31:08.37#ibcon#about to read 4, iclass 20, count 0 2006.252.07:31:08.37#ibcon#read 4, iclass 20, count 0 2006.252.07:31:08.37#ibcon#about to read 5, iclass 20, count 0 2006.252.07:31:08.37#ibcon#read 5, iclass 20, count 0 2006.252.07:31:08.37#ibcon#about to read 6, iclass 20, count 0 2006.252.07:31:08.37#ibcon#read 6, iclass 20, count 0 2006.252.07:31:08.37#ibcon#end of sib2, iclass 20, count 0 2006.252.07:31:08.37#ibcon#*mode == 0, iclass 20, count 0 2006.252.07:31:08.37#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.252.07:31:08.37#ibcon#[26=FRQ=02,572.99\r\n] 2006.252.07:31:08.37#ibcon#*before write, iclass 20, count 0 2006.252.07:31:08.37#ibcon#enter sib2, iclass 20, count 0 2006.252.07:31:08.37#ibcon#flushed, iclass 20, count 0 2006.252.07:31:08.37#ibcon#about to write, iclass 20, count 0 2006.252.07:31:08.37#ibcon#wrote, iclass 20, count 0 2006.252.07:31:08.37#ibcon#about to read 3, iclass 20, count 0 2006.252.07:31:08.42#ibcon#read 3, iclass 20, count 0 2006.252.07:31:08.42#ibcon#about to read 4, iclass 20, count 0 2006.252.07:31:08.42#ibcon#read 4, iclass 20, count 0 2006.252.07:31:08.42#ibcon#about to read 5, iclass 20, count 0 2006.252.07:31:08.42#ibcon#read 5, iclass 20, count 0 2006.252.07:31:08.42#ibcon#about to read 6, iclass 20, count 0 2006.252.07:31:08.42#ibcon#read 6, iclass 20, count 0 2006.252.07:31:08.42#ibcon#end of sib2, iclass 20, count 0 2006.252.07:31:08.42#ibcon#*after write, iclass 20, count 0 2006.252.07:31:08.42#ibcon#*before return 0, iclass 20, count 0 2006.252.07:31:08.42#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.252.07:31:08.42#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.252.07:31:08.42#ibcon#about to clear, iclass 20 cls_cnt 0 2006.252.07:31:08.42#ibcon#cleared, iclass 20 cls_cnt 0 2006.252.07:31:08.42$vc4f8/va=2,7 2006.252.07:31:08.42#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.252.07:31:08.42#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.252.07:31:08.42#ibcon#ireg 11 cls_cnt 2 2006.252.07:31:08.42#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.252.07:31:08.47#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.252.07:31:08.47#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.252.07:31:08.47#ibcon#enter wrdev, iclass 22, count 2 2006.252.07:31:08.47#ibcon#first serial, iclass 22, count 2 2006.252.07:31:08.47#ibcon#enter sib2, iclass 22, count 2 2006.252.07:31:08.47#ibcon#flushed, iclass 22, count 2 2006.252.07:31:08.47#ibcon#about to write, iclass 22, count 2 2006.252.07:31:08.47#ibcon#wrote, iclass 22, count 2 2006.252.07:31:08.47#ibcon#about to read 3, iclass 22, count 2 2006.252.07:31:08.49#ibcon#read 3, iclass 22, count 2 2006.252.07:31:08.49#ibcon#about to read 4, iclass 22, count 2 2006.252.07:31:08.49#ibcon#read 4, iclass 22, count 2 2006.252.07:31:08.49#ibcon#about to read 5, iclass 22, count 2 2006.252.07:31:08.49#ibcon#read 5, iclass 22, count 2 2006.252.07:31:08.49#ibcon#about to read 6, iclass 22, count 2 2006.252.07:31:08.49#ibcon#read 6, iclass 22, count 2 2006.252.07:31:08.49#ibcon#end of sib2, iclass 22, count 2 2006.252.07:31:08.49#ibcon#*mode == 0, iclass 22, count 2 2006.252.07:31:08.49#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.252.07:31:08.49#ibcon#[25=AT02-07\r\n] 2006.252.07:31:08.49#ibcon#*before write, iclass 22, count 2 2006.252.07:31:08.49#ibcon#enter sib2, iclass 22, count 2 2006.252.07:31:08.49#ibcon#flushed, iclass 22, count 2 2006.252.07:31:08.49#ibcon#about to write, iclass 22, count 2 2006.252.07:31:08.49#ibcon#wrote, iclass 22, count 2 2006.252.07:31:08.49#ibcon#about to read 3, iclass 22, count 2 2006.252.07:31:08.52#ibcon#read 3, iclass 22, count 2 2006.252.07:31:08.52#ibcon#about to read 4, iclass 22, count 2 2006.252.07:31:08.52#ibcon#read 4, iclass 22, count 2 2006.252.07:31:08.52#ibcon#about to read 5, iclass 22, count 2 2006.252.07:31:08.52#ibcon#read 5, iclass 22, count 2 2006.252.07:31:08.52#ibcon#about to read 6, iclass 22, count 2 2006.252.07:31:08.52#ibcon#read 6, iclass 22, count 2 2006.252.07:31:08.52#ibcon#end of sib2, iclass 22, count 2 2006.252.07:31:08.52#ibcon#*after write, iclass 22, count 2 2006.252.07:31:08.52#ibcon#*before return 0, iclass 22, count 2 2006.252.07:31:08.52#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.252.07:31:08.52#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.252.07:31:08.52#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.252.07:31:08.52#ibcon#ireg 7 cls_cnt 0 2006.252.07:31:08.52#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.252.07:31:08.64#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.252.07:31:08.64#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.252.07:31:08.64#ibcon#enter wrdev, iclass 22, count 0 2006.252.07:31:08.64#ibcon#first serial, iclass 22, count 0 2006.252.07:31:08.64#ibcon#enter sib2, iclass 22, count 0 2006.252.07:31:08.64#ibcon#flushed, iclass 22, count 0 2006.252.07:31:08.64#ibcon#about to write, iclass 22, count 0 2006.252.07:31:08.64#ibcon#wrote, iclass 22, count 0 2006.252.07:31:08.64#ibcon#about to read 3, iclass 22, count 0 2006.252.07:31:08.66#ibcon#read 3, iclass 22, count 0 2006.252.07:31:08.66#ibcon#about to read 4, iclass 22, count 0 2006.252.07:31:08.66#ibcon#read 4, iclass 22, count 0 2006.252.07:31:08.66#ibcon#about to read 5, iclass 22, count 0 2006.252.07:31:08.66#ibcon#read 5, iclass 22, count 0 2006.252.07:31:08.66#ibcon#about to read 6, iclass 22, count 0 2006.252.07:31:08.66#ibcon#read 6, iclass 22, count 0 2006.252.07:31:08.66#ibcon#end of sib2, iclass 22, count 0 2006.252.07:31:08.66#ibcon#*mode == 0, iclass 22, count 0 2006.252.07:31:08.66#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.252.07:31:08.66#ibcon#[25=USB\r\n] 2006.252.07:31:08.66#ibcon#*before write, iclass 22, count 0 2006.252.07:31:08.66#ibcon#enter sib2, iclass 22, count 0 2006.252.07:31:08.66#ibcon#flushed, iclass 22, count 0 2006.252.07:31:08.66#ibcon#about to write, iclass 22, count 0 2006.252.07:31:08.66#ibcon#wrote, iclass 22, count 0 2006.252.07:31:08.66#ibcon#about to read 3, iclass 22, count 0 2006.252.07:31:08.69#ibcon#read 3, iclass 22, count 0 2006.252.07:31:08.69#ibcon#about to read 4, iclass 22, count 0 2006.252.07:31:08.69#ibcon#read 4, iclass 22, count 0 2006.252.07:31:08.69#ibcon#about to read 5, iclass 22, count 0 2006.252.07:31:08.69#ibcon#read 5, iclass 22, count 0 2006.252.07:31:08.69#ibcon#about to read 6, iclass 22, count 0 2006.252.07:31:08.69#ibcon#read 6, iclass 22, count 0 2006.252.07:31:08.69#ibcon#end of sib2, iclass 22, count 0 2006.252.07:31:08.69#ibcon#*after write, iclass 22, count 0 2006.252.07:31:08.69#ibcon#*before return 0, iclass 22, count 0 2006.252.07:31:08.69#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.252.07:31:08.69#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.252.07:31:08.69#ibcon#about to clear, iclass 22 cls_cnt 0 2006.252.07:31:08.69#ibcon#cleared, iclass 22 cls_cnt 0 2006.252.07:31:08.69$vc4f8/valo=3,672.99 2006.252.07:31:08.69#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.252.07:31:08.69#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.252.07:31:08.69#ibcon#ireg 17 cls_cnt 0 2006.252.07:31:08.69#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.252.07:31:08.69#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.252.07:31:08.69#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.252.07:31:08.69#ibcon#enter wrdev, iclass 24, count 0 2006.252.07:31:08.69#ibcon#first serial, iclass 24, count 0 2006.252.07:31:08.69#ibcon#enter sib2, iclass 24, count 0 2006.252.07:31:08.69#ibcon#flushed, iclass 24, count 0 2006.252.07:31:08.69#ibcon#about to write, iclass 24, count 0 2006.252.07:31:08.69#ibcon#wrote, iclass 24, count 0 2006.252.07:31:08.69#ibcon#about to read 3, iclass 24, count 0 2006.252.07:31:08.71#ibcon#read 3, iclass 24, count 0 2006.252.07:31:08.71#ibcon#about to read 4, iclass 24, count 0 2006.252.07:31:08.71#ibcon#read 4, iclass 24, count 0 2006.252.07:31:08.71#ibcon#about to read 5, iclass 24, count 0 2006.252.07:31:08.71#ibcon#read 5, iclass 24, count 0 2006.252.07:31:08.71#ibcon#about to read 6, iclass 24, count 0 2006.252.07:31:08.71#ibcon#read 6, iclass 24, count 0 2006.252.07:31:08.71#ibcon#end of sib2, iclass 24, count 0 2006.252.07:31:08.71#ibcon#*mode == 0, iclass 24, count 0 2006.252.07:31:08.71#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.252.07:31:08.71#ibcon#[26=FRQ=03,672.99\r\n] 2006.252.07:31:08.71#ibcon#*before write, iclass 24, count 0 2006.252.07:31:08.71#ibcon#enter sib2, iclass 24, count 0 2006.252.07:31:08.71#ibcon#flushed, iclass 24, count 0 2006.252.07:31:08.71#ibcon#about to write, iclass 24, count 0 2006.252.07:31:08.71#ibcon#wrote, iclass 24, count 0 2006.252.07:31:08.71#ibcon#about to read 3, iclass 24, count 0 2006.252.07:31:08.76#ibcon#read 3, iclass 24, count 0 2006.252.07:31:08.76#ibcon#about to read 4, iclass 24, count 0 2006.252.07:31:08.76#ibcon#read 4, iclass 24, count 0 2006.252.07:31:08.76#ibcon#about to read 5, iclass 24, count 0 2006.252.07:31:08.76#ibcon#read 5, iclass 24, count 0 2006.252.07:31:08.76#ibcon#about to read 6, iclass 24, count 0 2006.252.07:31:08.76#ibcon#read 6, iclass 24, count 0 2006.252.07:31:08.76#ibcon#end of sib2, iclass 24, count 0 2006.252.07:31:08.76#ibcon#*after write, iclass 24, count 0 2006.252.07:31:08.76#ibcon#*before return 0, iclass 24, count 0 2006.252.07:31:08.76#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.252.07:31:08.76#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.252.07:31:08.76#ibcon#about to clear, iclass 24 cls_cnt 0 2006.252.07:31:08.76#ibcon#cleared, iclass 24 cls_cnt 0 2006.252.07:31:08.76$vc4f8/va=3,6 2006.252.07:31:08.76#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.252.07:31:08.76#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.252.07:31:08.76#ibcon#ireg 11 cls_cnt 2 2006.252.07:31:08.76#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.252.07:31:08.81#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.252.07:31:08.81#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.252.07:31:08.81#ibcon#enter wrdev, iclass 26, count 2 2006.252.07:31:08.81#ibcon#first serial, iclass 26, count 2 2006.252.07:31:08.81#ibcon#enter sib2, iclass 26, count 2 2006.252.07:31:08.81#ibcon#flushed, iclass 26, count 2 2006.252.07:31:08.81#ibcon#about to write, iclass 26, count 2 2006.252.07:31:08.81#ibcon#wrote, iclass 26, count 2 2006.252.07:31:08.81#ibcon#about to read 3, iclass 26, count 2 2006.252.07:31:08.83#ibcon#read 3, iclass 26, count 2 2006.252.07:31:08.83#ibcon#about to read 4, iclass 26, count 2 2006.252.07:31:08.83#ibcon#read 4, iclass 26, count 2 2006.252.07:31:08.83#ibcon#about to read 5, iclass 26, count 2 2006.252.07:31:08.83#ibcon#read 5, iclass 26, count 2 2006.252.07:31:08.83#ibcon#about to read 6, iclass 26, count 2 2006.252.07:31:08.83#ibcon#read 6, iclass 26, count 2 2006.252.07:31:08.83#ibcon#end of sib2, iclass 26, count 2 2006.252.07:31:08.83#ibcon#*mode == 0, iclass 26, count 2 2006.252.07:31:08.83#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.252.07:31:08.83#ibcon#[25=AT03-06\r\n] 2006.252.07:31:08.83#ibcon#*before write, iclass 26, count 2 2006.252.07:31:08.83#ibcon#enter sib2, iclass 26, count 2 2006.252.07:31:08.83#ibcon#flushed, iclass 26, count 2 2006.252.07:31:08.83#ibcon#about to write, iclass 26, count 2 2006.252.07:31:08.83#ibcon#wrote, iclass 26, count 2 2006.252.07:31:08.83#ibcon#about to read 3, iclass 26, count 2 2006.252.07:31:08.86#ibcon#read 3, iclass 26, count 2 2006.252.07:31:08.86#ibcon#about to read 4, iclass 26, count 2 2006.252.07:31:08.86#ibcon#read 4, iclass 26, count 2 2006.252.07:31:08.86#ibcon#about to read 5, iclass 26, count 2 2006.252.07:31:08.86#ibcon#read 5, iclass 26, count 2 2006.252.07:31:08.86#ibcon#about to read 6, iclass 26, count 2 2006.252.07:31:08.86#ibcon#read 6, iclass 26, count 2 2006.252.07:31:08.86#ibcon#end of sib2, iclass 26, count 2 2006.252.07:31:08.86#ibcon#*after write, iclass 26, count 2 2006.252.07:31:08.86#ibcon#*before return 0, iclass 26, count 2 2006.252.07:31:08.86#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.252.07:31:08.86#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.252.07:31:08.86#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.252.07:31:08.86#ibcon#ireg 7 cls_cnt 0 2006.252.07:31:08.86#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.252.07:31:08.98#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.252.07:31:08.98#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.252.07:31:08.98#ibcon#enter wrdev, iclass 26, count 0 2006.252.07:31:08.98#ibcon#first serial, iclass 26, count 0 2006.252.07:31:08.98#ibcon#enter sib2, iclass 26, count 0 2006.252.07:31:08.98#ibcon#flushed, iclass 26, count 0 2006.252.07:31:08.98#ibcon#about to write, iclass 26, count 0 2006.252.07:31:08.98#ibcon#wrote, iclass 26, count 0 2006.252.07:31:08.98#ibcon#about to read 3, iclass 26, count 0 2006.252.07:31:09.00#ibcon#read 3, iclass 26, count 0 2006.252.07:31:09.00#ibcon#about to read 4, iclass 26, count 0 2006.252.07:31:09.00#ibcon#read 4, iclass 26, count 0 2006.252.07:31:09.00#ibcon#about to read 5, iclass 26, count 0 2006.252.07:31:09.00#ibcon#read 5, iclass 26, count 0 2006.252.07:31:09.00#ibcon#about to read 6, iclass 26, count 0 2006.252.07:31:09.00#ibcon#read 6, iclass 26, count 0 2006.252.07:31:09.00#ibcon#end of sib2, iclass 26, count 0 2006.252.07:31:09.00#ibcon#*mode == 0, iclass 26, count 0 2006.252.07:31:09.00#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.252.07:31:09.00#ibcon#[25=USB\r\n] 2006.252.07:31:09.00#ibcon#*before write, iclass 26, count 0 2006.252.07:31:09.00#ibcon#enter sib2, iclass 26, count 0 2006.252.07:31:09.00#ibcon#flushed, iclass 26, count 0 2006.252.07:31:09.00#ibcon#about to write, iclass 26, count 0 2006.252.07:31:09.00#ibcon#wrote, iclass 26, count 0 2006.252.07:31:09.00#ibcon#about to read 3, iclass 26, count 0 2006.252.07:31:09.03#ibcon#read 3, iclass 26, count 0 2006.252.07:31:09.03#ibcon#about to read 4, iclass 26, count 0 2006.252.07:31:09.03#ibcon#read 4, iclass 26, count 0 2006.252.07:31:09.03#ibcon#about to read 5, iclass 26, count 0 2006.252.07:31:09.03#ibcon#read 5, iclass 26, count 0 2006.252.07:31:09.03#ibcon#about to read 6, iclass 26, count 0 2006.252.07:31:09.03#ibcon#read 6, iclass 26, count 0 2006.252.07:31:09.03#ibcon#end of sib2, iclass 26, count 0 2006.252.07:31:09.03#ibcon#*after write, iclass 26, count 0 2006.252.07:31:09.03#ibcon#*before return 0, iclass 26, count 0 2006.252.07:31:09.03#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.252.07:31:09.03#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.252.07:31:09.03#ibcon#about to clear, iclass 26 cls_cnt 0 2006.252.07:31:09.03#ibcon#cleared, iclass 26 cls_cnt 0 2006.252.07:31:09.03$vc4f8/valo=4,832.99 2006.252.07:31:09.03#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.252.07:31:09.03#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.252.07:31:09.03#ibcon#ireg 17 cls_cnt 0 2006.252.07:31:09.03#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.252.07:31:09.03#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.252.07:31:09.03#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.252.07:31:09.03#ibcon#enter wrdev, iclass 28, count 0 2006.252.07:31:09.03#ibcon#first serial, iclass 28, count 0 2006.252.07:31:09.03#ibcon#enter sib2, iclass 28, count 0 2006.252.07:31:09.03#ibcon#flushed, iclass 28, count 0 2006.252.07:31:09.03#ibcon#about to write, iclass 28, count 0 2006.252.07:31:09.03#ibcon#wrote, iclass 28, count 0 2006.252.07:31:09.03#ibcon#about to read 3, iclass 28, count 0 2006.252.07:31:09.05#ibcon#read 3, iclass 28, count 0 2006.252.07:31:09.05#ibcon#about to read 4, iclass 28, count 0 2006.252.07:31:09.05#ibcon#read 4, iclass 28, count 0 2006.252.07:31:09.05#ibcon#about to read 5, iclass 28, count 0 2006.252.07:31:09.05#ibcon#read 5, iclass 28, count 0 2006.252.07:31:09.05#ibcon#about to read 6, iclass 28, count 0 2006.252.07:31:09.05#ibcon#read 6, iclass 28, count 0 2006.252.07:31:09.05#ibcon#end of sib2, iclass 28, count 0 2006.252.07:31:09.05#ibcon#*mode == 0, iclass 28, count 0 2006.252.07:31:09.05#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.252.07:31:09.05#ibcon#[26=FRQ=04,832.99\r\n] 2006.252.07:31:09.05#ibcon#*before write, iclass 28, count 0 2006.252.07:31:09.05#ibcon#enter sib2, iclass 28, count 0 2006.252.07:31:09.05#ibcon#flushed, iclass 28, count 0 2006.252.07:31:09.05#ibcon#about to write, iclass 28, count 0 2006.252.07:31:09.05#ibcon#wrote, iclass 28, count 0 2006.252.07:31:09.05#ibcon#about to read 3, iclass 28, count 0 2006.252.07:31:09.10#ibcon#read 3, iclass 28, count 0 2006.252.07:31:09.10#ibcon#about to read 4, iclass 28, count 0 2006.252.07:31:09.10#ibcon#read 4, iclass 28, count 0 2006.252.07:31:09.10#ibcon#about to read 5, iclass 28, count 0 2006.252.07:31:09.10#ibcon#read 5, iclass 28, count 0 2006.252.07:31:09.10#ibcon#about to read 6, iclass 28, count 0 2006.252.07:31:09.10#ibcon#read 6, iclass 28, count 0 2006.252.07:31:09.10#ibcon#end of sib2, iclass 28, count 0 2006.252.07:31:09.10#ibcon#*after write, iclass 28, count 0 2006.252.07:31:09.10#ibcon#*before return 0, iclass 28, count 0 2006.252.07:31:09.10#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.252.07:31:09.10#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.252.07:31:09.10#ibcon#about to clear, iclass 28 cls_cnt 0 2006.252.07:31:09.10#ibcon#cleared, iclass 28 cls_cnt 0 2006.252.07:31:09.10$vc4f8/va=4,7 2006.252.07:31:09.10#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.252.07:31:09.10#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.252.07:31:09.10#ibcon#ireg 11 cls_cnt 2 2006.252.07:31:09.10#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.252.07:31:09.15#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.252.07:31:09.15#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.252.07:31:09.15#ibcon#enter wrdev, iclass 30, count 2 2006.252.07:31:09.15#ibcon#first serial, iclass 30, count 2 2006.252.07:31:09.15#ibcon#enter sib2, iclass 30, count 2 2006.252.07:31:09.15#ibcon#flushed, iclass 30, count 2 2006.252.07:31:09.15#ibcon#about to write, iclass 30, count 2 2006.252.07:31:09.15#ibcon#wrote, iclass 30, count 2 2006.252.07:31:09.15#ibcon#about to read 3, iclass 30, count 2 2006.252.07:31:09.17#ibcon#read 3, iclass 30, count 2 2006.252.07:31:09.17#ibcon#about to read 4, iclass 30, count 2 2006.252.07:31:09.17#ibcon#read 4, iclass 30, count 2 2006.252.07:31:09.17#ibcon#about to read 5, iclass 30, count 2 2006.252.07:31:09.17#ibcon#read 5, iclass 30, count 2 2006.252.07:31:09.17#ibcon#about to read 6, iclass 30, count 2 2006.252.07:31:09.17#ibcon#read 6, iclass 30, count 2 2006.252.07:31:09.17#ibcon#end of sib2, iclass 30, count 2 2006.252.07:31:09.17#ibcon#*mode == 0, iclass 30, count 2 2006.252.07:31:09.17#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.252.07:31:09.17#ibcon#[25=AT04-07\r\n] 2006.252.07:31:09.17#ibcon#*before write, iclass 30, count 2 2006.252.07:31:09.17#ibcon#enter sib2, iclass 30, count 2 2006.252.07:31:09.17#ibcon#flushed, iclass 30, count 2 2006.252.07:31:09.17#ibcon#about to write, iclass 30, count 2 2006.252.07:31:09.17#ibcon#wrote, iclass 30, count 2 2006.252.07:31:09.17#ibcon#about to read 3, iclass 30, count 2 2006.252.07:31:09.20#ibcon#read 3, iclass 30, count 2 2006.252.07:31:09.20#ibcon#about to read 4, iclass 30, count 2 2006.252.07:31:09.20#ibcon#read 4, iclass 30, count 2 2006.252.07:31:09.20#ibcon#about to read 5, iclass 30, count 2 2006.252.07:31:09.20#ibcon#read 5, iclass 30, count 2 2006.252.07:31:09.20#ibcon#about to read 6, iclass 30, count 2 2006.252.07:31:09.20#ibcon#read 6, iclass 30, count 2 2006.252.07:31:09.20#ibcon#end of sib2, iclass 30, count 2 2006.252.07:31:09.20#ibcon#*after write, iclass 30, count 2 2006.252.07:31:09.20#ibcon#*before return 0, iclass 30, count 2 2006.252.07:31:09.20#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.252.07:31:09.20#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.252.07:31:09.20#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.252.07:31:09.20#ibcon#ireg 7 cls_cnt 0 2006.252.07:31:09.20#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.252.07:31:09.32#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.252.07:31:09.32#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.252.07:31:09.32#ibcon#enter wrdev, iclass 30, count 0 2006.252.07:31:09.32#ibcon#first serial, iclass 30, count 0 2006.252.07:31:09.32#ibcon#enter sib2, iclass 30, count 0 2006.252.07:31:09.32#ibcon#flushed, iclass 30, count 0 2006.252.07:31:09.32#ibcon#about to write, iclass 30, count 0 2006.252.07:31:09.32#ibcon#wrote, iclass 30, count 0 2006.252.07:31:09.32#ibcon#about to read 3, iclass 30, count 0 2006.252.07:31:09.34#ibcon#read 3, iclass 30, count 0 2006.252.07:31:09.34#ibcon#about to read 4, iclass 30, count 0 2006.252.07:31:09.34#ibcon#read 4, iclass 30, count 0 2006.252.07:31:09.34#ibcon#about to read 5, iclass 30, count 0 2006.252.07:31:09.34#ibcon#read 5, iclass 30, count 0 2006.252.07:31:09.34#ibcon#about to read 6, iclass 30, count 0 2006.252.07:31:09.34#ibcon#read 6, iclass 30, count 0 2006.252.07:31:09.34#ibcon#end of sib2, iclass 30, count 0 2006.252.07:31:09.34#ibcon#*mode == 0, iclass 30, count 0 2006.252.07:31:09.34#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.252.07:31:09.34#ibcon#[25=USB\r\n] 2006.252.07:31:09.34#ibcon#*before write, iclass 30, count 0 2006.252.07:31:09.34#ibcon#enter sib2, iclass 30, count 0 2006.252.07:31:09.34#ibcon#flushed, iclass 30, count 0 2006.252.07:31:09.34#ibcon#about to write, iclass 30, count 0 2006.252.07:31:09.34#ibcon#wrote, iclass 30, count 0 2006.252.07:31:09.34#ibcon#about to read 3, iclass 30, count 0 2006.252.07:31:09.37#ibcon#read 3, iclass 30, count 0 2006.252.07:31:09.37#ibcon#about to read 4, iclass 30, count 0 2006.252.07:31:09.37#ibcon#read 4, iclass 30, count 0 2006.252.07:31:09.37#ibcon#about to read 5, iclass 30, count 0 2006.252.07:31:09.37#ibcon#read 5, iclass 30, count 0 2006.252.07:31:09.37#ibcon#about to read 6, iclass 30, count 0 2006.252.07:31:09.37#ibcon#read 6, iclass 30, count 0 2006.252.07:31:09.37#ibcon#end of sib2, iclass 30, count 0 2006.252.07:31:09.37#ibcon#*after write, iclass 30, count 0 2006.252.07:31:09.37#ibcon#*before return 0, iclass 30, count 0 2006.252.07:31:09.37#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.252.07:31:09.37#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.252.07:31:09.37#ibcon#about to clear, iclass 30 cls_cnt 0 2006.252.07:31:09.37#ibcon#cleared, iclass 30 cls_cnt 0 2006.252.07:31:09.37$vc4f8/valo=5,652.99 2006.252.07:31:09.37#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.252.07:31:09.37#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.252.07:31:09.37#ibcon#ireg 17 cls_cnt 0 2006.252.07:31:09.37#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.252.07:31:09.37#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.252.07:31:09.37#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.252.07:31:09.37#ibcon#enter wrdev, iclass 32, count 0 2006.252.07:31:09.37#ibcon#first serial, iclass 32, count 0 2006.252.07:31:09.37#ibcon#enter sib2, iclass 32, count 0 2006.252.07:31:09.37#ibcon#flushed, iclass 32, count 0 2006.252.07:31:09.37#ibcon#about to write, iclass 32, count 0 2006.252.07:31:09.37#ibcon#wrote, iclass 32, count 0 2006.252.07:31:09.37#ibcon#about to read 3, iclass 32, count 0 2006.252.07:31:09.39#ibcon#read 3, iclass 32, count 0 2006.252.07:31:09.39#ibcon#about to read 4, iclass 32, count 0 2006.252.07:31:09.39#ibcon#read 4, iclass 32, count 0 2006.252.07:31:09.39#ibcon#about to read 5, iclass 32, count 0 2006.252.07:31:09.39#ibcon#read 5, iclass 32, count 0 2006.252.07:31:09.39#ibcon#about to read 6, iclass 32, count 0 2006.252.07:31:09.39#ibcon#read 6, iclass 32, count 0 2006.252.07:31:09.39#ibcon#end of sib2, iclass 32, count 0 2006.252.07:31:09.39#ibcon#*mode == 0, iclass 32, count 0 2006.252.07:31:09.39#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.252.07:31:09.39#ibcon#[26=FRQ=05,652.99\r\n] 2006.252.07:31:09.39#ibcon#*before write, iclass 32, count 0 2006.252.07:31:09.39#ibcon#enter sib2, iclass 32, count 0 2006.252.07:31:09.39#ibcon#flushed, iclass 32, count 0 2006.252.07:31:09.39#ibcon#about to write, iclass 32, count 0 2006.252.07:31:09.39#ibcon#wrote, iclass 32, count 0 2006.252.07:31:09.39#ibcon#about to read 3, iclass 32, count 0 2006.252.07:31:09.43#ibcon#read 3, iclass 32, count 0 2006.252.07:31:09.43#ibcon#about to read 4, iclass 32, count 0 2006.252.07:31:09.43#ibcon#read 4, iclass 32, count 0 2006.252.07:31:09.43#ibcon#about to read 5, iclass 32, count 0 2006.252.07:31:09.43#ibcon#read 5, iclass 32, count 0 2006.252.07:31:09.43#ibcon#about to read 6, iclass 32, count 0 2006.252.07:31:09.43#ibcon#read 6, iclass 32, count 0 2006.252.07:31:09.43#ibcon#end of sib2, iclass 32, count 0 2006.252.07:31:09.43#ibcon#*after write, iclass 32, count 0 2006.252.07:31:09.43#ibcon#*before return 0, iclass 32, count 0 2006.252.07:31:09.43#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.252.07:31:09.43#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.252.07:31:09.43#ibcon#about to clear, iclass 32 cls_cnt 0 2006.252.07:31:09.43#ibcon#cleared, iclass 32 cls_cnt 0 2006.252.07:31:09.43$vc4f8/va=5,7 2006.252.07:31:09.43#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.252.07:31:09.43#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.252.07:31:09.43#ibcon#ireg 11 cls_cnt 2 2006.252.07:31:09.43#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.252.07:31:09.49#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.252.07:31:09.49#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.252.07:31:09.49#ibcon#enter wrdev, iclass 34, count 2 2006.252.07:31:09.49#ibcon#first serial, iclass 34, count 2 2006.252.07:31:09.49#ibcon#enter sib2, iclass 34, count 2 2006.252.07:31:09.49#ibcon#flushed, iclass 34, count 2 2006.252.07:31:09.49#ibcon#about to write, iclass 34, count 2 2006.252.07:31:09.49#ibcon#wrote, iclass 34, count 2 2006.252.07:31:09.49#ibcon#about to read 3, iclass 34, count 2 2006.252.07:31:09.51#ibcon#read 3, iclass 34, count 2 2006.252.07:31:09.51#ibcon#about to read 4, iclass 34, count 2 2006.252.07:31:09.51#ibcon#read 4, iclass 34, count 2 2006.252.07:31:09.51#ibcon#about to read 5, iclass 34, count 2 2006.252.07:31:09.51#ibcon#read 5, iclass 34, count 2 2006.252.07:31:09.51#ibcon#about to read 6, iclass 34, count 2 2006.252.07:31:09.51#ibcon#read 6, iclass 34, count 2 2006.252.07:31:09.51#ibcon#end of sib2, iclass 34, count 2 2006.252.07:31:09.51#ibcon#*mode == 0, iclass 34, count 2 2006.252.07:31:09.51#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.252.07:31:09.51#ibcon#[25=AT05-07\r\n] 2006.252.07:31:09.51#ibcon#*before write, iclass 34, count 2 2006.252.07:31:09.51#ibcon#enter sib2, iclass 34, count 2 2006.252.07:31:09.51#ibcon#flushed, iclass 34, count 2 2006.252.07:31:09.51#ibcon#about to write, iclass 34, count 2 2006.252.07:31:09.51#ibcon#wrote, iclass 34, count 2 2006.252.07:31:09.51#ibcon#about to read 3, iclass 34, count 2 2006.252.07:31:09.54#ibcon#read 3, iclass 34, count 2 2006.252.07:31:09.54#ibcon#about to read 4, iclass 34, count 2 2006.252.07:31:09.54#ibcon#read 4, iclass 34, count 2 2006.252.07:31:09.54#ibcon#about to read 5, iclass 34, count 2 2006.252.07:31:09.54#ibcon#read 5, iclass 34, count 2 2006.252.07:31:09.54#ibcon#about to read 6, iclass 34, count 2 2006.252.07:31:09.54#ibcon#read 6, iclass 34, count 2 2006.252.07:31:09.54#ibcon#end of sib2, iclass 34, count 2 2006.252.07:31:09.54#ibcon#*after write, iclass 34, count 2 2006.252.07:31:09.54#ibcon#*before return 0, iclass 34, count 2 2006.252.07:31:09.54#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.252.07:31:09.54#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.252.07:31:09.54#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.252.07:31:09.54#ibcon#ireg 7 cls_cnt 0 2006.252.07:31:09.54#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.252.07:31:09.66#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.252.07:31:09.66#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.252.07:31:09.66#ibcon#enter wrdev, iclass 34, count 0 2006.252.07:31:09.66#ibcon#first serial, iclass 34, count 0 2006.252.07:31:09.66#ibcon#enter sib2, iclass 34, count 0 2006.252.07:31:09.66#ibcon#flushed, iclass 34, count 0 2006.252.07:31:09.66#ibcon#about to write, iclass 34, count 0 2006.252.07:31:09.66#ibcon#wrote, iclass 34, count 0 2006.252.07:31:09.66#ibcon#about to read 3, iclass 34, count 0 2006.252.07:31:09.68#ibcon#read 3, iclass 34, count 0 2006.252.07:31:09.68#ibcon#about to read 4, iclass 34, count 0 2006.252.07:31:09.68#ibcon#read 4, iclass 34, count 0 2006.252.07:31:09.68#ibcon#about to read 5, iclass 34, count 0 2006.252.07:31:09.68#ibcon#read 5, iclass 34, count 0 2006.252.07:31:09.68#ibcon#about to read 6, iclass 34, count 0 2006.252.07:31:09.68#ibcon#read 6, iclass 34, count 0 2006.252.07:31:09.68#ibcon#end of sib2, iclass 34, count 0 2006.252.07:31:09.68#ibcon#*mode == 0, iclass 34, count 0 2006.252.07:31:09.68#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.252.07:31:09.68#ibcon#[25=USB\r\n] 2006.252.07:31:09.68#ibcon#*before write, iclass 34, count 0 2006.252.07:31:09.68#ibcon#enter sib2, iclass 34, count 0 2006.252.07:31:09.68#ibcon#flushed, iclass 34, count 0 2006.252.07:31:09.68#ibcon#about to write, iclass 34, count 0 2006.252.07:31:09.68#ibcon#wrote, iclass 34, count 0 2006.252.07:31:09.68#ibcon#about to read 3, iclass 34, count 0 2006.252.07:31:09.71#ibcon#read 3, iclass 34, count 0 2006.252.07:31:09.71#ibcon#about to read 4, iclass 34, count 0 2006.252.07:31:09.71#ibcon#read 4, iclass 34, count 0 2006.252.07:31:09.71#ibcon#about to read 5, iclass 34, count 0 2006.252.07:31:09.71#ibcon#read 5, iclass 34, count 0 2006.252.07:31:09.71#ibcon#about to read 6, iclass 34, count 0 2006.252.07:31:09.71#ibcon#read 6, iclass 34, count 0 2006.252.07:31:09.71#ibcon#end of sib2, iclass 34, count 0 2006.252.07:31:09.71#ibcon#*after write, iclass 34, count 0 2006.252.07:31:09.71#ibcon#*before return 0, iclass 34, count 0 2006.252.07:31:09.71#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.252.07:31:09.71#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.252.07:31:09.71#ibcon#about to clear, iclass 34 cls_cnt 0 2006.252.07:31:09.71#ibcon#cleared, iclass 34 cls_cnt 0 2006.252.07:31:09.71$vc4f8/valo=6,772.99 2006.252.07:31:09.71#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.252.07:31:09.71#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.252.07:31:09.71#ibcon#ireg 17 cls_cnt 0 2006.252.07:31:09.71#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.252.07:31:09.71#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.252.07:31:09.71#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.252.07:31:09.71#ibcon#enter wrdev, iclass 36, count 0 2006.252.07:31:09.71#ibcon#first serial, iclass 36, count 0 2006.252.07:31:09.71#ibcon#enter sib2, iclass 36, count 0 2006.252.07:31:09.71#ibcon#flushed, iclass 36, count 0 2006.252.07:31:09.71#ibcon#about to write, iclass 36, count 0 2006.252.07:31:09.71#ibcon#wrote, iclass 36, count 0 2006.252.07:31:09.71#ibcon#about to read 3, iclass 36, count 0 2006.252.07:31:09.73#ibcon#read 3, iclass 36, count 0 2006.252.07:31:09.73#ibcon#about to read 4, iclass 36, count 0 2006.252.07:31:09.73#ibcon#read 4, iclass 36, count 0 2006.252.07:31:09.73#ibcon#about to read 5, iclass 36, count 0 2006.252.07:31:09.73#ibcon#read 5, iclass 36, count 0 2006.252.07:31:09.73#ibcon#about to read 6, iclass 36, count 0 2006.252.07:31:09.73#ibcon#read 6, iclass 36, count 0 2006.252.07:31:09.73#ibcon#end of sib2, iclass 36, count 0 2006.252.07:31:09.73#ibcon#*mode == 0, iclass 36, count 0 2006.252.07:31:09.73#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.252.07:31:09.73#ibcon#[26=FRQ=06,772.99\r\n] 2006.252.07:31:09.73#ibcon#*before write, iclass 36, count 0 2006.252.07:31:09.73#ibcon#enter sib2, iclass 36, count 0 2006.252.07:31:09.73#ibcon#flushed, iclass 36, count 0 2006.252.07:31:09.73#ibcon#about to write, iclass 36, count 0 2006.252.07:31:09.73#ibcon#wrote, iclass 36, count 0 2006.252.07:31:09.73#ibcon#about to read 3, iclass 36, count 0 2006.252.07:31:09.78#ibcon#read 3, iclass 36, count 0 2006.252.07:31:09.78#ibcon#about to read 4, iclass 36, count 0 2006.252.07:31:09.78#ibcon#read 4, iclass 36, count 0 2006.252.07:31:09.78#ibcon#about to read 5, iclass 36, count 0 2006.252.07:31:09.78#ibcon#read 5, iclass 36, count 0 2006.252.07:31:09.78#ibcon#about to read 6, iclass 36, count 0 2006.252.07:31:09.78#ibcon#read 6, iclass 36, count 0 2006.252.07:31:09.78#ibcon#end of sib2, iclass 36, count 0 2006.252.07:31:09.78#ibcon#*after write, iclass 36, count 0 2006.252.07:31:09.78#ibcon#*before return 0, iclass 36, count 0 2006.252.07:31:09.78#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.252.07:31:09.78#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.252.07:31:09.78#ibcon#about to clear, iclass 36 cls_cnt 0 2006.252.07:31:09.78#ibcon#cleared, iclass 36 cls_cnt 0 2006.252.07:31:09.78$vc4f8/va=6,7 2006.252.07:31:09.78#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.252.07:31:09.78#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.252.07:31:09.78#ibcon#ireg 11 cls_cnt 2 2006.252.07:31:09.78#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.252.07:31:09.83#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.252.07:31:09.83#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.252.07:31:09.83#ibcon#enter wrdev, iclass 38, count 2 2006.252.07:31:09.83#ibcon#first serial, iclass 38, count 2 2006.252.07:31:09.83#ibcon#enter sib2, iclass 38, count 2 2006.252.07:31:09.83#ibcon#flushed, iclass 38, count 2 2006.252.07:31:09.83#ibcon#about to write, iclass 38, count 2 2006.252.07:31:09.83#ibcon#wrote, iclass 38, count 2 2006.252.07:31:09.83#ibcon#about to read 3, iclass 38, count 2 2006.252.07:31:09.85#ibcon#read 3, iclass 38, count 2 2006.252.07:31:09.85#ibcon#about to read 4, iclass 38, count 2 2006.252.07:31:09.85#ibcon#read 4, iclass 38, count 2 2006.252.07:31:09.85#ibcon#about to read 5, iclass 38, count 2 2006.252.07:31:09.85#ibcon#read 5, iclass 38, count 2 2006.252.07:31:09.85#ibcon#about to read 6, iclass 38, count 2 2006.252.07:31:09.85#ibcon#read 6, iclass 38, count 2 2006.252.07:31:09.85#ibcon#end of sib2, iclass 38, count 2 2006.252.07:31:09.85#ibcon#*mode == 0, iclass 38, count 2 2006.252.07:31:09.85#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.252.07:31:09.85#ibcon#[25=AT06-07\r\n] 2006.252.07:31:09.85#ibcon#*before write, iclass 38, count 2 2006.252.07:31:09.85#ibcon#enter sib2, iclass 38, count 2 2006.252.07:31:09.85#ibcon#flushed, iclass 38, count 2 2006.252.07:31:09.85#ibcon#about to write, iclass 38, count 2 2006.252.07:31:09.85#ibcon#wrote, iclass 38, count 2 2006.252.07:31:09.85#ibcon#about to read 3, iclass 38, count 2 2006.252.07:31:09.88#ibcon#read 3, iclass 38, count 2 2006.252.07:31:09.88#ibcon#about to read 4, iclass 38, count 2 2006.252.07:31:09.88#ibcon#read 4, iclass 38, count 2 2006.252.07:31:09.88#ibcon#about to read 5, iclass 38, count 2 2006.252.07:31:09.88#ibcon#read 5, iclass 38, count 2 2006.252.07:31:09.88#ibcon#about to read 6, iclass 38, count 2 2006.252.07:31:09.88#ibcon#read 6, iclass 38, count 2 2006.252.07:31:09.88#ibcon#end of sib2, iclass 38, count 2 2006.252.07:31:09.88#ibcon#*after write, iclass 38, count 2 2006.252.07:31:09.88#ibcon#*before return 0, iclass 38, count 2 2006.252.07:31:09.88#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.252.07:31:09.88#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.252.07:31:09.88#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.252.07:31:09.88#ibcon#ireg 7 cls_cnt 0 2006.252.07:31:09.88#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.252.07:31:10.00#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.252.07:31:10.00#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.252.07:31:10.00#ibcon#enter wrdev, iclass 38, count 0 2006.252.07:31:10.00#ibcon#first serial, iclass 38, count 0 2006.252.07:31:10.00#ibcon#enter sib2, iclass 38, count 0 2006.252.07:31:10.00#ibcon#flushed, iclass 38, count 0 2006.252.07:31:10.00#ibcon#about to write, iclass 38, count 0 2006.252.07:31:10.00#ibcon#wrote, iclass 38, count 0 2006.252.07:31:10.00#ibcon#about to read 3, iclass 38, count 0 2006.252.07:31:10.02#ibcon#read 3, iclass 38, count 0 2006.252.07:31:10.02#ibcon#about to read 4, iclass 38, count 0 2006.252.07:31:10.02#ibcon#read 4, iclass 38, count 0 2006.252.07:31:10.02#ibcon#about to read 5, iclass 38, count 0 2006.252.07:31:10.02#ibcon#read 5, iclass 38, count 0 2006.252.07:31:10.02#ibcon#about to read 6, iclass 38, count 0 2006.252.07:31:10.02#ibcon#read 6, iclass 38, count 0 2006.252.07:31:10.02#ibcon#end of sib2, iclass 38, count 0 2006.252.07:31:10.02#ibcon#*mode == 0, iclass 38, count 0 2006.252.07:31:10.02#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.252.07:31:10.02#ibcon#[25=USB\r\n] 2006.252.07:31:10.02#ibcon#*before write, iclass 38, count 0 2006.252.07:31:10.02#ibcon#enter sib2, iclass 38, count 0 2006.252.07:31:10.02#ibcon#flushed, iclass 38, count 0 2006.252.07:31:10.02#ibcon#about to write, iclass 38, count 0 2006.252.07:31:10.02#ibcon#wrote, iclass 38, count 0 2006.252.07:31:10.02#ibcon#about to read 3, iclass 38, count 0 2006.252.07:31:10.05#ibcon#read 3, iclass 38, count 0 2006.252.07:31:10.05#ibcon#about to read 4, iclass 38, count 0 2006.252.07:31:10.05#ibcon#read 4, iclass 38, count 0 2006.252.07:31:10.05#ibcon#about to read 5, iclass 38, count 0 2006.252.07:31:10.05#ibcon#read 5, iclass 38, count 0 2006.252.07:31:10.05#ibcon#about to read 6, iclass 38, count 0 2006.252.07:31:10.05#ibcon#read 6, iclass 38, count 0 2006.252.07:31:10.05#ibcon#end of sib2, iclass 38, count 0 2006.252.07:31:10.05#ibcon#*after write, iclass 38, count 0 2006.252.07:31:10.05#ibcon#*before return 0, iclass 38, count 0 2006.252.07:31:10.05#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.252.07:31:10.05#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.252.07:31:10.05#ibcon#about to clear, iclass 38 cls_cnt 0 2006.252.07:31:10.05#ibcon#cleared, iclass 38 cls_cnt 0 2006.252.07:31:10.05$vc4f8/valo=7,832.99 2006.252.07:31:10.05#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.252.07:31:10.05#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.252.07:31:10.05#ibcon#ireg 17 cls_cnt 0 2006.252.07:31:10.05#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.252.07:31:10.05#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.252.07:31:10.05#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.252.07:31:10.05#ibcon#enter wrdev, iclass 40, count 0 2006.252.07:31:10.05#ibcon#first serial, iclass 40, count 0 2006.252.07:31:10.05#ibcon#enter sib2, iclass 40, count 0 2006.252.07:31:10.05#ibcon#flushed, iclass 40, count 0 2006.252.07:31:10.05#ibcon#about to write, iclass 40, count 0 2006.252.07:31:10.05#ibcon#wrote, iclass 40, count 0 2006.252.07:31:10.05#ibcon#about to read 3, iclass 40, count 0 2006.252.07:31:10.07#ibcon#read 3, iclass 40, count 0 2006.252.07:31:10.07#ibcon#about to read 4, iclass 40, count 0 2006.252.07:31:10.07#ibcon#read 4, iclass 40, count 0 2006.252.07:31:10.07#ibcon#about to read 5, iclass 40, count 0 2006.252.07:31:10.07#ibcon#read 5, iclass 40, count 0 2006.252.07:31:10.07#ibcon#about to read 6, iclass 40, count 0 2006.252.07:31:10.07#ibcon#read 6, iclass 40, count 0 2006.252.07:31:10.07#ibcon#end of sib2, iclass 40, count 0 2006.252.07:31:10.07#ibcon#*mode == 0, iclass 40, count 0 2006.252.07:31:10.07#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.252.07:31:10.07#ibcon#[26=FRQ=07,832.99\r\n] 2006.252.07:31:10.07#ibcon#*before write, iclass 40, count 0 2006.252.07:31:10.07#ibcon#enter sib2, iclass 40, count 0 2006.252.07:31:10.07#ibcon#flushed, iclass 40, count 0 2006.252.07:31:10.07#ibcon#about to write, iclass 40, count 0 2006.252.07:31:10.07#ibcon#wrote, iclass 40, count 0 2006.252.07:31:10.07#ibcon#about to read 3, iclass 40, count 0 2006.252.07:31:10.11#ibcon#read 3, iclass 40, count 0 2006.252.07:31:10.11#ibcon#about to read 4, iclass 40, count 0 2006.252.07:31:10.11#ibcon#read 4, iclass 40, count 0 2006.252.07:31:10.11#ibcon#about to read 5, iclass 40, count 0 2006.252.07:31:10.11#ibcon#read 5, iclass 40, count 0 2006.252.07:31:10.11#ibcon#about to read 6, iclass 40, count 0 2006.252.07:31:10.11#ibcon#read 6, iclass 40, count 0 2006.252.07:31:10.11#ibcon#end of sib2, iclass 40, count 0 2006.252.07:31:10.11#ibcon#*after write, iclass 40, count 0 2006.252.07:31:10.11#ibcon#*before return 0, iclass 40, count 0 2006.252.07:31:10.11#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.252.07:31:10.11#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.252.07:31:10.11#ibcon#about to clear, iclass 40 cls_cnt 0 2006.252.07:31:10.11#ibcon#cleared, iclass 40 cls_cnt 0 2006.252.07:31:10.11$vc4f8/va=7,7 2006.252.07:31:10.11#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.252.07:31:10.11#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.252.07:31:10.11#ibcon#ireg 11 cls_cnt 2 2006.252.07:31:10.11#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.252.07:31:10.17#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.252.07:31:10.17#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.252.07:31:10.17#ibcon#enter wrdev, iclass 4, count 2 2006.252.07:31:10.17#ibcon#first serial, iclass 4, count 2 2006.252.07:31:10.17#ibcon#enter sib2, iclass 4, count 2 2006.252.07:31:10.17#ibcon#flushed, iclass 4, count 2 2006.252.07:31:10.17#ibcon#about to write, iclass 4, count 2 2006.252.07:31:10.17#ibcon#wrote, iclass 4, count 2 2006.252.07:31:10.17#ibcon#about to read 3, iclass 4, count 2 2006.252.07:31:10.19#ibcon#read 3, iclass 4, count 2 2006.252.07:31:10.19#ibcon#about to read 4, iclass 4, count 2 2006.252.07:31:10.19#ibcon#read 4, iclass 4, count 2 2006.252.07:31:10.19#ibcon#about to read 5, iclass 4, count 2 2006.252.07:31:10.19#ibcon#read 5, iclass 4, count 2 2006.252.07:31:10.19#ibcon#about to read 6, iclass 4, count 2 2006.252.07:31:10.19#ibcon#read 6, iclass 4, count 2 2006.252.07:31:10.19#ibcon#end of sib2, iclass 4, count 2 2006.252.07:31:10.19#ibcon#*mode == 0, iclass 4, count 2 2006.252.07:31:10.19#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.252.07:31:10.19#ibcon#[25=AT07-07\r\n] 2006.252.07:31:10.19#ibcon#*before write, iclass 4, count 2 2006.252.07:31:10.19#ibcon#enter sib2, iclass 4, count 2 2006.252.07:31:10.19#ibcon#flushed, iclass 4, count 2 2006.252.07:31:10.19#ibcon#about to write, iclass 4, count 2 2006.252.07:31:10.19#ibcon#wrote, iclass 4, count 2 2006.252.07:31:10.19#ibcon#about to read 3, iclass 4, count 2 2006.252.07:31:10.22#ibcon#read 3, iclass 4, count 2 2006.252.07:31:10.22#ibcon#about to read 4, iclass 4, count 2 2006.252.07:31:10.22#ibcon#read 4, iclass 4, count 2 2006.252.07:31:10.22#ibcon#about to read 5, iclass 4, count 2 2006.252.07:31:10.22#ibcon#read 5, iclass 4, count 2 2006.252.07:31:10.22#ibcon#about to read 6, iclass 4, count 2 2006.252.07:31:10.22#ibcon#read 6, iclass 4, count 2 2006.252.07:31:10.22#ibcon#end of sib2, iclass 4, count 2 2006.252.07:31:10.22#ibcon#*after write, iclass 4, count 2 2006.252.07:31:10.22#ibcon#*before return 0, iclass 4, count 2 2006.252.07:31:10.22#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.252.07:31:10.22#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.252.07:31:10.22#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.252.07:31:10.22#ibcon#ireg 7 cls_cnt 0 2006.252.07:31:10.22#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.252.07:31:10.34#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.252.07:31:10.34#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.252.07:31:10.34#ibcon#enter wrdev, iclass 4, count 0 2006.252.07:31:10.34#ibcon#first serial, iclass 4, count 0 2006.252.07:31:10.34#ibcon#enter sib2, iclass 4, count 0 2006.252.07:31:10.34#ibcon#flushed, iclass 4, count 0 2006.252.07:31:10.34#ibcon#about to write, iclass 4, count 0 2006.252.07:31:10.34#ibcon#wrote, iclass 4, count 0 2006.252.07:31:10.34#ibcon#about to read 3, iclass 4, count 0 2006.252.07:31:10.36#ibcon#read 3, iclass 4, count 0 2006.252.07:31:10.36#ibcon#about to read 4, iclass 4, count 0 2006.252.07:31:10.36#ibcon#read 4, iclass 4, count 0 2006.252.07:31:10.36#ibcon#about to read 5, iclass 4, count 0 2006.252.07:31:10.36#ibcon#read 5, iclass 4, count 0 2006.252.07:31:10.36#ibcon#about to read 6, iclass 4, count 0 2006.252.07:31:10.36#ibcon#read 6, iclass 4, count 0 2006.252.07:31:10.36#ibcon#end of sib2, iclass 4, count 0 2006.252.07:31:10.36#ibcon#*mode == 0, iclass 4, count 0 2006.252.07:31:10.36#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.252.07:31:10.36#ibcon#[25=USB\r\n] 2006.252.07:31:10.36#ibcon#*before write, iclass 4, count 0 2006.252.07:31:10.36#ibcon#enter sib2, iclass 4, count 0 2006.252.07:31:10.36#ibcon#flushed, iclass 4, count 0 2006.252.07:31:10.36#ibcon#about to write, iclass 4, count 0 2006.252.07:31:10.36#ibcon#wrote, iclass 4, count 0 2006.252.07:31:10.36#ibcon#about to read 3, iclass 4, count 0 2006.252.07:31:10.39#ibcon#read 3, iclass 4, count 0 2006.252.07:31:10.39#ibcon#about to read 4, iclass 4, count 0 2006.252.07:31:10.39#ibcon#read 4, iclass 4, count 0 2006.252.07:31:10.39#ibcon#about to read 5, iclass 4, count 0 2006.252.07:31:10.39#ibcon#read 5, iclass 4, count 0 2006.252.07:31:10.39#ibcon#about to read 6, iclass 4, count 0 2006.252.07:31:10.39#ibcon#read 6, iclass 4, count 0 2006.252.07:31:10.39#ibcon#end of sib2, iclass 4, count 0 2006.252.07:31:10.39#ibcon#*after write, iclass 4, count 0 2006.252.07:31:10.39#ibcon#*before return 0, iclass 4, count 0 2006.252.07:31:10.39#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.252.07:31:10.39#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.252.07:31:10.39#ibcon#about to clear, iclass 4 cls_cnt 0 2006.252.07:31:10.39#ibcon#cleared, iclass 4 cls_cnt 0 2006.252.07:31:10.39$vc4f8/valo=8,852.99 2006.252.07:31:10.39#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.252.07:31:10.39#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.252.07:31:10.39#ibcon#ireg 17 cls_cnt 0 2006.252.07:31:10.39#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.252.07:31:10.39#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.252.07:31:10.39#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.252.07:31:10.39#ibcon#enter wrdev, iclass 6, count 0 2006.252.07:31:10.39#ibcon#first serial, iclass 6, count 0 2006.252.07:31:10.39#ibcon#enter sib2, iclass 6, count 0 2006.252.07:31:10.39#ibcon#flushed, iclass 6, count 0 2006.252.07:31:10.39#ibcon#about to write, iclass 6, count 0 2006.252.07:31:10.39#ibcon#wrote, iclass 6, count 0 2006.252.07:31:10.39#ibcon#about to read 3, iclass 6, count 0 2006.252.07:31:10.41#ibcon#read 3, iclass 6, count 0 2006.252.07:31:10.41#ibcon#about to read 4, iclass 6, count 0 2006.252.07:31:10.41#ibcon#read 4, iclass 6, count 0 2006.252.07:31:10.41#ibcon#about to read 5, iclass 6, count 0 2006.252.07:31:10.41#ibcon#read 5, iclass 6, count 0 2006.252.07:31:10.41#ibcon#about to read 6, iclass 6, count 0 2006.252.07:31:10.41#ibcon#read 6, iclass 6, count 0 2006.252.07:31:10.41#ibcon#end of sib2, iclass 6, count 0 2006.252.07:31:10.41#ibcon#*mode == 0, iclass 6, count 0 2006.252.07:31:10.41#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.252.07:31:10.41#ibcon#[26=FRQ=08,852.99\r\n] 2006.252.07:31:10.41#ibcon#*before write, iclass 6, count 0 2006.252.07:31:10.41#ibcon#enter sib2, iclass 6, count 0 2006.252.07:31:10.41#ibcon#flushed, iclass 6, count 0 2006.252.07:31:10.41#ibcon#about to write, iclass 6, count 0 2006.252.07:31:10.41#ibcon#wrote, iclass 6, count 0 2006.252.07:31:10.41#ibcon#about to read 3, iclass 6, count 0 2006.252.07:31:10.45#ibcon#read 3, iclass 6, count 0 2006.252.07:31:10.45#ibcon#about to read 4, iclass 6, count 0 2006.252.07:31:10.45#ibcon#read 4, iclass 6, count 0 2006.252.07:31:10.45#ibcon#about to read 5, iclass 6, count 0 2006.252.07:31:10.45#ibcon#read 5, iclass 6, count 0 2006.252.07:31:10.45#ibcon#about to read 6, iclass 6, count 0 2006.252.07:31:10.45#ibcon#read 6, iclass 6, count 0 2006.252.07:31:10.45#ibcon#end of sib2, iclass 6, count 0 2006.252.07:31:10.45#ibcon#*after write, iclass 6, count 0 2006.252.07:31:10.45#ibcon#*before return 0, iclass 6, count 0 2006.252.07:31:10.45#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.252.07:31:10.45#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.252.07:31:10.45#ibcon#about to clear, iclass 6 cls_cnt 0 2006.252.07:31:10.45#ibcon#cleared, iclass 6 cls_cnt 0 2006.252.07:31:10.45$vc4f8/va=8,7 2006.252.07:31:10.45#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.252.07:31:10.45#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.252.07:31:10.45#ibcon#ireg 11 cls_cnt 2 2006.252.07:31:10.45#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.252.07:31:10.51#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.252.07:31:10.51#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.252.07:31:10.51#ibcon#enter wrdev, iclass 10, count 2 2006.252.07:31:10.51#ibcon#first serial, iclass 10, count 2 2006.252.07:31:10.51#ibcon#enter sib2, iclass 10, count 2 2006.252.07:31:10.51#ibcon#flushed, iclass 10, count 2 2006.252.07:31:10.51#ibcon#about to write, iclass 10, count 2 2006.252.07:31:10.51#ibcon#wrote, iclass 10, count 2 2006.252.07:31:10.51#ibcon#about to read 3, iclass 10, count 2 2006.252.07:31:10.53#ibcon#read 3, iclass 10, count 2 2006.252.07:31:10.53#ibcon#about to read 4, iclass 10, count 2 2006.252.07:31:10.53#ibcon#read 4, iclass 10, count 2 2006.252.07:31:10.53#ibcon#about to read 5, iclass 10, count 2 2006.252.07:31:10.53#ibcon#read 5, iclass 10, count 2 2006.252.07:31:10.53#ibcon#about to read 6, iclass 10, count 2 2006.252.07:31:10.53#ibcon#read 6, iclass 10, count 2 2006.252.07:31:10.53#ibcon#end of sib2, iclass 10, count 2 2006.252.07:31:10.53#ibcon#*mode == 0, iclass 10, count 2 2006.252.07:31:10.53#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.252.07:31:10.53#ibcon#[25=AT08-07\r\n] 2006.252.07:31:10.53#ibcon#*before write, iclass 10, count 2 2006.252.07:31:10.53#ibcon#enter sib2, iclass 10, count 2 2006.252.07:31:10.53#ibcon#flushed, iclass 10, count 2 2006.252.07:31:10.53#ibcon#about to write, iclass 10, count 2 2006.252.07:31:10.53#ibcon#wrote, iclass 10, count 2 2006.252.07:31:10.53#ibcon#about to read 3, iclass 10, count 2 2006.252.07:31:10.56#ibcon#read 3, iclass 10, count 2 2006.252.07:31:10.56#ibcon#about to read 4, iclass 10, count 2 2006.252.07:31:10.56#ibcon#read 4, iclass 10, count 2 2006.252.07:31:10.56#ibcon#about to read 5, iclass 10, count 2 2006.252.07:31:10.56#ibcon#read 5, iclass 10, count 2 2006.252.07:31:10.56#ibcon#about to read 6, iclass 10, count 2 2006.252.07:31:10.56#ibcon#read 6, iclass 10, count 2 2006.252.07:31:10.56#ibcon#end of sib2, iclass 10, count 2 2006.252.07:31:10.56#ibcon#*after write, iclass 10, count 2 2006.252.07:31:10.56#ibcon#*before return 0, iclass 10, count 2 2006.252.07:31:10.56#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.252.07:31:10.56#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.252.07:31:10.56#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.252.07:31:10.56#ibcon#ireg 7 cls_cnt 0 2006.252.07:31:10.56#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.252.07:31:10.68#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.252.07:31:10.68#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.252.07:31:10.68#ibcon#enter wrdev, iclass 10, count 0 2006.252.07:31:10.68#ibcon#first serial, iclass 10, count 0 2006.252.07:31:10.68#ibcon#enter sib2, iclass 10, count 0 2006.252.07:31:10.68#ibcon#flushed, iclass 10, count 0 2006.252.07:31:10.68#ibcon#about to write, iclass 10, count 0 2006.252.07:31:10.68#ibcon#wrote, iclass 10, count 0 2006.252.07:31:10.68#ibcon#about to read 3, iclass 10, count 0 2006.252.07:31:10.70#ibcon#read 3, iclass 10, count 0 2006.252.07:31:10.70#ibcon#about to read 4, iclass 10, count 0 2006.252.07:31:10.70#ibcon#read 4, iclass 10, count 0 2006.252.07:31:10.70#ibcon#about to read 5, iclass 10, count 0 2006.252.07:31:10.70#ibcon#read 5, iclass 10, count 0 2006.252.07:31:10.70#ibcon#about to read 6, iclass 10, count 0 2006.252.07:31:10.70#ibcon#read 6, iclass 10, count 0 2006.252.07:31:10.70#ibcon#end of sib2, iclass 10, count 0 2006.252.07:31:10.70#ibcon#*mode == 0, iclass 10, count 0 2006.252.07:31:10.70#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.252.07:31:10.70#ibcon#[25=USB\r\n] 2006.252.07:31:10.70#ibcon#*before write, iclass 10, count 0 2006.252.07:31:10.70#ibcon#enter sib2, iclass 10, count 0 2006.252.07:31:10.70#ibcon#flushed, iclass 10, count 0 2006.252.07:31:10.70#ibcon#about to write, iclass 10, count 0 2006.252.07:31:10.70#ibcon#wrote, iclass 10, count 0 2006.252.07:31:10.70#ibcon#about to read 3, iclass 10, count 0 2006.252.07:31:10.73#ibcon#read 3, iclass 10, count 0 2006.252.07:31:10.73#ibcon#about to read 4, iclass 10, count 0 2006.252.07:31:10.73#ibcon#read 4, iclass 10, count 0 2006.252.07:31:10.73#ibcon#about to read 5, iclass 10, count 0 2006.252.07:31:10.73#ibcon#read 5, iclass 10, count 0 2006.252.07:31:10.73#ibcon#about to read 6, iclass 10, count 0 2006.252.07:31:10.73#ibcon#read 6, iclass 10, count 0 2006.252.07:31:10.73#ibcon#end of sib2, iclass 10, count 0 2006.252.07:31:10.73#ibcon#*after write, iclass 10, count 0 2006.252.07:31:10.73#ibcon#*before return 0, iclass 10, count 0 2006.252.07:31:10.73#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.252.07:31:10.73#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.252.07:31:10.73#ibcon#about to clear, iclass 10 cls_cnt 0 2006.252.07:31:10.73#ibcon#cleared, iclass 10 cls_cnt 0 2006.252.07:31:10.73$vc4f8/vblo=1,632.99 2006.252.07:31:10.73#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.252.07:31:10.73#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.252.07:31:10.73#ibcon#ireg 17 cls_cnt 0 2006.252.07:31:10.73#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.252.07:31:10.73#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.252.07:31:10.73#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.252.07:31:10.73#ibcon#enter wrdev, iclass 12, count 0 2006.252.07:31:10.73#ibcon#first serial, iclass 12, count 0 2006.252.07:31:10.73#ibcon#enter sib2, iclass 12, count 0 2006.252.07:31:10.73#ibcon#flushed, iclass 12, count 0 2006.252.07:31:10.73#ibcon#about to write, iclass 12, count 0 2006.252.07:31:10.73#ibcon#wrote, iclass 12, count 0 2006.252.07:31:10.73#ibcon#about to read 3, iclass 12, count 0 2006.252.07:31:10.75#ibcon#read 3, iclass 12, count 0 2006.252.07:31:10.75#ibcon#about to read 4, iclass 12, count 0 2006.252.07:31:10.75#ibcon#read 4, iclass 12, count 0 2006.252.07:31:10.75#ibcon#about to read 5, iclass 12, count 0 2006.252.07:31:10.75#ibcon#read 5, iclass 12, count 0 2006.252.07:31:10.75#ibcon#about to read 6, iclass 12, count 0 2006.252.07:31:10.75#ibcon#read 6, iclass 12, count 0 2006.252.07:31:10.75#ibcon#end of sib2, iclass 12, count 0 2006.252.07:31:10.75#ibcon#*mode == 0, iclass 12, count 0 2006.252.07:31:10.75#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.252.07:31:10.75#ibcon#[28=FRQ=01,632.99\r\n] 2006.252.07:31:10.75#ibcon#*before write, iclass 12, count 0 2006.252.07:31:10.75#ibcon#enter sib2, iclass 12, count 0 2006.252.07:31:10.75#ibcon#flushed, iclass 12, count 0 2006.252.07:31:10.75#ibcon#about to write, iclass 12, count 0 2006.252.07:31:10.75#ibcon#wrote, iclass 12, count 0 2006.252.07:31:10.75#ibcon#about to read 3, iclass 12, count 0 2006.252.07:31:10.79#ibcon#read 3, iclass 12, count 0 2006.252.07:31:10.79#ibcon#about to read 4, iclass 12, count 0 2006.252.07:31:10.79#ibcon#read 4, iclass 12, count 0 2006.252.07:31:10.79#ibcon#about to read 5, iclass 12, count 0 2006.252.07:31:10.79#ibcon#read 5, iclass 12, count 0 2006.252.07:31:10.79#ibcon#about to read 6, iclass 12, count 0 2006.252.07:31:10.79#ibcon#read 6, iclass 12, count 0 2006.252.07:31:10.79#ibcon#end of sib2, iclass 12, count 0 2006.252.07:31:10.79#ibcon#*after write, iclass 12, count 0 2006.252.07:31:10.79#ibcon#*before return 0, iclass 12, count 0 2006.252.07:31:10.79#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.252.07:31:10.79#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.252.07:31:10.79#ibcon#about to clear, iclass 12 cls_cnt 0 2006.252.07:31:10.79#ibcon#cleared, iclass 12 cls_cnt 0 2006.252.07:31:10.79$vc4f8/vb=1,4 2006.252.07:31:10.79#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.252.07:31:10.79#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.252.07:31:10.79#ibcon#ireg 11 cls_cnt 2 2006.252.07:31:10.79#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.252.07:31:10.79#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.252.07:31:10.79#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.252.07:31:10.79#ibcon#enter wrdev, iclass 14, count 2 2006.252.07:31:10.79#ibcon#first serial, iclass 14, count 2 2006.252.07:31:10.79#ibcon#enter sib2, iclass 14, count 2 2006.252.07:31:10.79#ibcon#flushed, iclass 14, count 2 2006.252.07:31:10.79#ibcon#about to write, iclass 14, count 2 2006.252.07:31:10.79#ibcon#wrote, iclass 14, count 2 2006.252.07:31:10.79#ibcon#about to read 3, iclass 14, count 2 2006.252.07:31:10.81#ibcon#read 3, iclass 14, count 2 2006.252.07:31:10.81#ibcon#about to read 4, iclass 14, count 2 2006.252.07:31:10.81#ibcon#read 4, iclass 14, count 2 2006.252.07:31:10.81#ibcon#about to read 5, iclass 14, count 2 2006.252.07:31:10.81#ibcon#read 5, iclass 14, count 2 2006.252.07:31:10.81#ibcon#about to read 6, iclass 14, count 2 2006.252.07:31:10.81#ibcon#read 6, iclass 14, count 2 2006.252.07:31:10.81#ibcon#end of sib2, iclass 14, count 2 2006.252.07:31:10.81#ibcon#*mode == 0, iclass 14, count 2 2006.252.07:31:10.81#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.252.07:31:10.81#ibcon#[27=AT01-04\r\n] 2006.252.07:31:10.81#ibcon#*before write, iclass 14, count 2 2006.252.07:31:10.81#ibcon#enter sib2, iclass 14, count 2 2006.252.07:31:10.81#ibcon#flushed, iclass 14, count 2 2006.252.07:31:10.81#ibcon#about to write, iclass 14, count 2 2006.252.07:31:10.81#ibcon#wrote, iclass 14, count 2 2006.252.07:31:10.81#ibcon#about to read 3, iclass 14, count 2 2006.252.07:31:10.84#ibcon#read 3, iclass 14, count 2 2006.252.07:31:10.84#ibcon#about to read 4, iclass 14, count 2 2006.252.07:31:10.84#ibcon#read 4, iclass 14, count 2 2006.252.07:31:10.84#ibcon#about to read 5, iclass 14, count 2 2006.252.07:31:10.84#ibcon#read 5, iclass 14, count 2 2006.252.07:31:10.84#ibcon#about to read 6, iclass 14, count 2 2006.252.07:31:10.84#ibcon#read 6, iclass 14, count 2 2006.252.07:31:10.84#ibcon#end of sib2, iclass 14, count 2 2006.252.07:31:10.84#ibcon#*after write, iclass 14, count 2 2006.252.07:31:10.84#ibcon#*before return 0, iclass 14, count 2 2006.252.07:31:10.84#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.252.07:31:10.84#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.252.07:31:10.84#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.252.07:31:10.84#ibcon#ireg 7 cls_cnt 0 2006.252.07:31:10.84#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.252.07:31:10.96#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.252.07:31:10.96#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.252.07:31:10.96#ibcon#enter wrdev, iclass 14, count 0 2006.252.07:31:10.96#ibcon#first serial, iclass 14, count 0 2006.252.07:31:10.96#ibcon#enter sib2, iclass 14, count 0 2006.252.07:31:10.96#ibcon#flushed, iclass 14, count 0 2006.252.07:31:10.96#ibcon#about to write, iclass 14, count 0 2006.252.07:31:10.96#ibcon#wrote, iclass 14, count 0 2006.252.07:31:10.96#ibcon#about to read 3, iclass 14, count 0 2006.252.07:31:10.98#ibcon#read 3, iclass 14, count 0 2006.252.07:31:10.98#ibcon#about to read 4, iclass 14, count 0 2006.252.07:31:10.98#ibcon#read 4, iclass 14, count 0 2006.252.07:31:10.98#ibcon#about to read 5, iclass 14, count 0 2006.252.07:31:10.98#ibcon#read 5, iclass 14, count 0 2006.252.07:31:10.98#ibcon#about to read 6, iclass 14, count 0 2006.252.07:31:10.98#ibcon#read 6, iclass 14, count 0 2006.252.07:31:10.98#ibcon#end of sib2, iclass 14, count 0 2006.252.07:31:10.98#ibcon#*mode == 0, iclass 14, count 0 2006.252.07:31:10.98#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.252.07:31:10.98#ibcon#[27=USB\r\n] 2006.252.07:31:10.98#ibcon#*before write, iclass 14, count 0 2006.252.07:31:10.98#ibcon#enter sib2, iclass 14, count 0 2006.252.07:31:10.98#ibcon#flushed, iclass 14, count 0 2006.252.07:31:10.98#ibcon#about to write, iclass 14, count 0 2006.252.07:31:10.98#ibcon#wrote, iclass 14, count 0 2006.252.07:31:10.98#ibcon#about to read 3, iclass 14, count 0 2006.252.07:31:11.01#ibcon#read 3, iclass 14, count 0 2006.252.07:31:11.01#ibcon#about to read 4, iclass 14, count 0 2006.252.07:31:11.01#ibcon#read 4, iclass 14, count 0 2006.252.07:31:11.01#ibcon#about to read 5, iclass 14, count 0 2006.252.07:31:11.01#ibcon#read 5, iclass 14, count 0 2006.252.07:31:11.01#ibcon#about to read 6, iclass 14, count 0 2006.252.07:31:11.01#ibcon#read 6, iclass 14, count 0 2006.252.07:31:11.01#ibcon#end of sib2, iclass 14, count 0 2006.252.07:31:11.01#ibcon#*after write, iclass 14, count 0 2006.252.07:31:11.01#ibcon#*before return 0, iclass 14, count 0 2006.252.07:31:11.01#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.252.07:31:11.01#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.252.07:31:11.01#ibcon#about to clear, iclass 14 cls_cnt 0 2006.252.07:31:11.01#ibcon#cleared, iclass 14 cls_cnt 0 2006.252.07:31:11.01$vc4f8/vblo=2,640.99 2006.252.07:31:11.01#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.252.07:31:11.01#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.252.07:31:11.01#ibcon#ireg 17 cls_cnt 0 2006.252.07:31:11.01#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.252.07:31:11.01#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.252.07:31:11.01#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.252.07:31:11.01#ibcon#enter wrdev, iclass 16, count 0 2006.252.07:31:11.01#ibcon#first serial, iclass 16, count 0 2006.252.07:31:11.01#ibcon#enter sib2, iclass 16, count 0 2006.252.07:31:11.01#ibcon#flushed, iclass 16, count 0 2006.252.07:31:11.01#ibcon#about to write, iclass 16, count 0 2006.252.07:31:11.01#ibcon#wrote, iclass 16, count 0 2006.252.07:31:11.01#ibcon#about to read 3, iclass 16, count 0 2006.252.07:31:11.03#ibcon#read 3, iclass 16, count 0 2006.252.07:31:11.03#ibcon#about to read 4, iclass 16, count 0 2006.252.07:31:11.03#ibcon#read 4, iclass 16, count 0 2006.252.07:31:11.03#ibcon#about to read 5, iclass 16, count 0 2006.252.07:31:11.03#ibcon#read 5, iclass 16, count 0 2006.252.07:31:11.03#ibcon#about to read 6, iclass 16, count 0 2006.252.07:31:11.03#ibcon#read 6, iclass 16, count 0 2006.252.07:31:11.03#ibcon#end of sib2, iclass 16, count 0 2006.252.07:31:11.03#ibcon#*mode == 0, iclass 16, count 0 2006.252.07:31:11.03#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.252.07:31:11.03#ibcon#[28=FRQ=02,640.99\r\n] 2006.252.07:31:11.03#ibcon#*before write, iclass 16, count 0 2006.252.07:31:11.03#ibcon#enter sib2, iclass 16, count 0 2006.252.07:31:11.03#ibcon#flushed, iclass 16, count 0 2006.252.07:31:11.03#ibcon#about to write, iclass 16, count 0 2006.252.07:31:11.03#ibcon#wrote, iclass 16, count 0 2006.252.07:31:11.03#ibcon#about to read 3, iclass 16, count 0 2006.252.07:31:11.07#ibcon#read 3, iclass 16, count 0 2006.252.07:31:11.07#ibcon#about to read 4, iclass 16, count 0 2006.252.07:31:11.07#ibcon#read 4, iclass 16, count 0 2006.252.07:31:11.07#ibcon#about to read 5, iclass 16, count 0 2006.252.07:31:11.07#ibcon#read 5, iclass 16, count 0 2006.252.07:31:11.07#ibcon#about to read 6, iclass 16, count 0 2006.252.07:31:11.07#ibcon#read 6, iclass 16, count 0 2006.252.07:31:11.07#ibcon#end of sib2, iclass 16, count 0 2006.252.07:31:11.07#ibcon#*after write, iclass 16, count 0 2006.252.07:31:11.07#ibcon#*before return 0, iclass 16, count 0 2006.252.07:31:11.07#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.252.07:31:11.07#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.252.07:31:11.07#ibcon#about to clear, iclass 16 cls_cnt 0 2006.252.07:31:11.07#ibcon#cleared, iclass 16 cls_cnt 0 2006.252.07:31:11.07$vc4f8/vb=2,5 2006.252.07:31:11.07#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.252.07:31:11.07#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.252.07:31:11.07#ibcon#ireg 11 cls_cnt 2 2006.252.07:31:11.07#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.252.07:31:11.13#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.252.07:31:11.13#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.252.07:31:11.13#ibcon#enter wrdev, iclass 18, count 2 2006.252.07:31:11.13#ibcon#first serial, iclass 18, count 2 2006.252.07:31:11.13#ibcon#enter sib2, iclass 18, count 2 2006.252.07:31:11.13#ibcon#flushed, iclass 18, count 2 2006.252.07:31:11.13#ibcon#about to write, iclass 18, count 2 2006.252.07:31:11.13#ibcon#wrote, iclass 18, count 2 2006.252.07:31:11.13#ibcon#about to read 3, iclass 18, count 2 2006.252.07:31:11.15#ibcon#read 3, iclass 18, count 2 2006.252.07:31:11.15#ibcon#about to read 4, iclass 18, count 2 2006.252.07:31:11.15#ibcon#read 4, iclass 18, count 2 2006.252.07:31:11.15#ibcon#about to read 5, iclass 18, count 2 2006.252.07:31:11.15#ibcon#read 5, iclass 18, count 2 2006.252.07:31:11.15#ibcon#about to read 6, iclass 18, count 2 2006.252.07:31:11.15#ibcon#read 6, iclass 18, count 2 2006.252.07:31:11.15#ibcon#end of sib2, iclass 18, count 2 2006.252.07:31:11.15#ibcon#*mode == 0, iclass 18, count 2 2006.252.07:31:11.15#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.252.07:31:11.15#ibcon#[27=AT02-05\r\n] 2006.252.07:31:11.15#ibcon#*before write, iclass 18, count 2 2006.252.07:31:11.15#ibcon#enter sib2, iclass 18, count 2 2006.252.07:31:11.15#ibcon#flushed, iclass 18, count 2 2006.252.07:31:11.15#ibcon#about to write, iclass 18, count 2 2006.252.07:31:11.15#ibcon#wrote, iclass 18, count 2 2006.252.07:31:11.15#ibcon#about to read 3, iclass 18, count 2 2006.252.07:31:11.18#ibcon#read 3, iclass 18, count 2 2006.252.07:31:11.18#ibcon#about to read 4, iclass 18, count 2 2006.252.07:31:11.18#ibcon#read 4, iclass 18, count 2 2006.252.07:31:11.18#ibcon#about to read 5, iclass 18, count 2 2006.252.07:31:11.18#ibcon#read 5, iclass 18, count 2 2006.252.07:31:11.18#ibcon#about to read 6, iclass 18, count 2 2006.252.07:31:11.18#ibcon#read 6, iclass 18, count 2 2006.252.07:31:11.18#ibcon#end of sib2, iclass 18, count 2 2006.252.07:31:11.18#ibcon#*after write, iclass 18, count 2 2006.252.07:31:11.18#ibcon#*before return 0, iclass 18, count 2 2006.252.07:31:11.18#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.252.07:31:11.18#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.252.07:31:11.18#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.252.07:31:11.18#ibcon#ireg 7 cls_cnt 0 2006.252.07:31:11.18#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.252.07:31:11.30#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.252.07:31:11.30#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.252.07:31:11.30#ibcon#enter wrdev, iclass 18, count 0 2006.252.07:31:11.30#ibcon#first serial, iclass 18, count 0 2006.252.07:31:11.30#ibcon#enter sib2, iclass 18, count 0 2006.252.07:31:11.30#ibcon#flushed, iclass 18, count 0 2006.252.07:31:11.30#ibcon#about to write, iclass 18, count 0 2006.252.07:31:11.30#ibcon#wrote, iclass 18, count 0 2006.252.07:31:11.30#ibcon#about to read 3, iclass 18, count 0 2006.252.07:31:11.32#ibcon#read 3, iclass 18, count 0 2006.252.07:31:11.32#ibcon#about to read 4, iclass 18, count 0 2006.252.07:31:11.32#ibcon#read 4, iclass 18, count 0 2006.252.07:31:11.32#ibcon#about to read 5, iclass 18, count 0 2006.252.07:31:11.32#ibcon#read 5, iclass 18, count 0 2006.252.07:31:11.32#ibcon#about to read 6, iclass 18, count 0 2006.252.07:31:11.32#ibcon#read 6, iclass 18, count 0 2006.252.07:31:11.32#ibcon#end of sib2, iclass 18, count 0 2006.252.07:31:11.32#ibcon#*mode == 0, iclass 18, count 0 2006.252.07:31:11.32#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.252.07:31:11.32#ibcon#[27=USB\r\n] 2006.252.07:31:11.32#ibcon#*before write, iclass 18, count 0 2006.252.07:31:11.32#ibcon#enter sib2, iclass 18, count 0 2006.252.07:31:11.32#ibcon#flushed, iclass 18, count 0 2006.252.07:31:11.32#ibcon#about to write, iclass 18, count 0 2006.252.07:31:11.32#ibcon#wrote, iclass 18, count 0 2006.252.07:31:11.32#ibcon#about to read 3, iclass 18, count 0 2006.252.07:31:11.35#ibcon#read 3, iclass 18, count 0 2006.252.07:31:11.35#ibcon#about to read 4, iclass 18, count 0 2006.252.07:31:11.35#ibcon#read 4, iclass 18, count 0 2006.252.07:31:11.35#ibcon#about to read 5, iclass 18, count 0 2006.252.07:31:11.35#ibcon#read 5, iclass 18, count 0 2006.252.07:31:11.35#ibcon#about to read 6, iclass 18, count 0 2006.252.07:31:11.35#ibcon#read 6, iclass 18, count 0 2006.252.07:31:11.35#ibcon#end of sib2, iclass 18, count 0 2006.252.07:31:11.35#ibcon#*after write, iclass 18, count 0 2006.252.07:31:11.35#ibcon#*before return 0, iclass 18, count 0 2006.252.07:31:11.35#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.252.07:31:11.35#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.252.07:31:11.35#ibcon#about to clear, iclass 18 cls_cnt 0 2006.252.07:31:11.35#ibcon#cleared, iclass 18 cls_cnt 0 2006.252.07:31:11.35$vc4f8/vblo=3,656.99 2006.252.07:31:11.35#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.252.07:31:11.35#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.252.07:31:11.35#ibcon#ireg 17 cls_cnt 0 2006.252.07:31:11.35#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.252.07:31:11.35#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.252.07:31:11.35#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.252.07:31:11.35#ibcon#enter wrdev, iclass 20, count 0 2006.252.07:31:11.35#ibcon#first serial, iclass 20, count 0 2006.252.07:31:11.35#ibcon#enter sib2, iclass 20, count 0 2006.252.07:31:11.35#ibcon#flushed, iclass 20, count 0 2006.252.07:31:11.35#ibcon#about to write, iclass 20, count 0 2006.252.07:31:11.35#ibcon#wrote, iclass 20, count 0 2006.252.07:31:11.35#ibcon#about to read 3, iclass 20, count 0 2006.252.07:31:11.37#ibcon#read 3, iclass 20, count 0 2006.252.07:31:11.37#ibcon#about to read 4, iclass 20, count 0 2006.252.07:31:11.37#ibcon#read 4, iclass 20, count 0 2006.252.07:31:11.37#ibcon#about to read 5, iclass 20, count 0 2006.252.07:31:11.37#ibcon#read 5, iclass 20, count 0 2006.252.07:31:11.37#ibcon#about to read 6, iclass 20, count 0 2006.252.07:31:11.37#ibcon#read 6, iclass 20, count 0 2006.252.07:31:11.37#ibcon#end of sib2, iclass 20, count 0 2006.252.07:31:11.37#ibcon#*mode == 0, iclass 20, count 0 2006.252.07:31:11.37#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.252.07:31:11.37#ibcon#[28=FRQ=03,656.99\r\n] 2006.252.07:31:11.37#ibcon#*before write, iclass 20, count 0 2006.252.07:31:11.37#ibcon#enter sib2, iclass 20, count 0 2006.252.07:31:11.37#ibcon#flushed, iclass 20, count 0 2006.252.07:31:11.37#ibcon#about to write, iclass 20, count 0 2006.252.07:31:11.37#ibcon#wrote, iclass 20, count 0 2006.252.07:31:11.37#ibcon#about to read 3, iclass 20, count 0 2006.252.07:31:11.41#ibcon#read 3, iclass 20, count 0 2006.252.07:31:11.41#ibcon#about to read 4, iclass 20, count 0 2006.252.07:31:11.41#ibcon#read 4, iclass 20, count 0 2006.252.07:31:11.41#ibcon#about to read 5, iclass 20, count 0 2006.252.07:31:11.41#ibcon#read 5, iclass 20, count 0 2006.252.07:31:11.41#ibcon#about to read 6, iclass 20, count 0 2006.252.07:31:11.41#ibcon#read 6, iclass 20, count 0 2006.252.07:31:11.41#ibcon#end of sib2, iclass 20, count 0 2006.252.07:31:11.41#ibcon#*after write, iclass 20, count 0 2006.252.07:31:11.41#ibcon#*before return 0, iclass 20, count 0 2006.252.07:31:11.41#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.252.07:31:11.41#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.252.07:31:11.41#ibcon#about to clear, iclass 20 cls_cnt 0 2006.252.07:31:11.41#ibcon#cleared, iclass 20 cls_cnt 0 2006.252.07:31:11.41$vc4f8/vb=3,4 2006.252.07:31:11.41#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.252.07:31:11.41#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.252.07:31:11.41#ibcon#ireg 11 cls_cnt 2 2006.252.07:31:11.41#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.252.07:31:11.47#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.252.07:31:11.47#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.252.07:31:11.47#ibcon#enter wrdev, iclass 22, count 2 2006.252.07:31:11.47#ibcon#first serial, iclass 22, count 2 2006.252.07:31:11.47#ibcon#enter sib2, iclass 22, count 2 2006.252.07:31:11.47#ibcon#flushed, iclass 22, count 2 2006.252.07:31:11.47#ibcon#about to write, iclass 22, count 2 2006.252.07:31:11.47#ibcon#wrote, iclass 22, count 2 2006.252.07:31:11.47#ibcon#about to read 3, iclass 22, count 2 2006.252.07:31:11.49#abcon#<5=/04 3.1 5.5 27.53 901011.3\r\n> 2006.252.07:31:11.49#ibcon#read 3, iclass 22, count 2 2006.252.07:31:11.49#ibcon#about to read 4, iclass 22, count 2 2006.252.07:31:11.49#ibcon#read 4, iclass 22, count 2 2006.252.07:31:11.49#ibcon#about to read 5, iclass 22, count 2 2006.252.07:31:11.49#ibcon#read 5, iclass 22, count 2 2006.252.07:31:11.49#ibcon#about to read 6, iclass 22, count 2 2006.252.07:31:11.49#ibcon#read 6, iclass 22, count 2 2006.252.07:31:11.49#ibcon#end of sib2, iclass 22, count 2 2006.252.07:31:11.49#ibcon#*mode == 0, iclass 22, count 2 2006.252.07:31:11.49#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.252.07:31:11.49#ibcon#[27=AT03-04\r\n] 2006.252.07:31:11.49#ibcon#*before write, iclass 22, count 2 2006.252.07:31:11.49#ibcon#enter sib2, iclass 22, count 2 2006.252.07:31:11.49#ibcon#flushed, iclass 22, count 2 2006.252.07:31:11.49#ibcon#about to write, iclass 22, count 2 2006.252.07:31:11.49#ibcon#wrote, iclass 22, count 2 2006.252.07:31:11.49#ibcon#about to read 3, iclass 22, count 2 2006.252.07:31:11.51#abcon#{5=INTERFACE CLEAR} 2006.252.07:31:11.52#ibcon#read 3, iclass 22, count 2 2006.252.07:31:11.52#ibcon#about to read 4, iclass 22, count 2 2006.252.07:31:11.52#ibcon#read 4, iclass 22, count 2 2006.252.07:31:11.52#ibcon#about to read 5, iclass 22, count 2 2006.252.07:31:11.52#ibcon#read 5, iclass 22, count 2 2006.252.07:31:11.52#ibcon#about to read 6, iclass 22, count 2 2006.252.07:31:11.52#ibcon#read 6, iclass 22, count 2 2006.252.07:31:11.52#ibcon#end of sib2, iclass 22, count 2 2006.252.07:31:11.52#ibcon#*after write, iclass 22, count 2 2006.252.07:31:11.52#ibcon#*before return 0, iclass 22, count 2 2006.252.07:31:11.52#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.252.07:31:11.52#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.252.07:31:11.52#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.252.07:31:11.52#ibcon#ireg 7 cls_cnt 0 2006.252.07:31:11.52#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.252.07:31:11.57#abcon#[5=S1D000X0/0*\r\n] 2006.252.07:31:11.64#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.252.07:31:11.64#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.252.07:31:11.64#ibcon#enter wrdev, iclass 22, count 0 2006.252.07:31:11.64#ibcon#first serial, iclass 22, count 0 2006.252.07:31:11.64#ibcon#enter sib2, iclass 22, count 0 2006.252.07:31:11.64#ibcon#flushed, iclass 22, count 0 2006.252.07:31:11.64#ibcon#about to write, iclass 22, count 0 2006.252.07:31:11.64#ibcon#wrote, iclass 22, count 0 2006.252.07:31:11.64#ibcon#about to read 3, iclass 22, count 0 2006.252.07:31:11.66#ibcon#read 3, iclass 22, count 0 2006.252.07:31:11.66#ibcon#about to read 4, iclass 22, count 0 2006.252.07:31:11.66#ibcon#read 4, iclass 22, count 0 2006.252.07:31:11.66#ibcon#about to read 5, iclass 22, count 0 2006.252.07:31:11.66#ibcon#read 5, iclass 22, count 0 2006.252.07:31:11.66#ibcon#about to read 6, iclass 22, count 0 2006.252.07:31:11.66#ibcon#read 6, iclass 22, count 0 2006.252.07:31:11.66#ibcon#end of sib2, iclass 22, count 0 2006.252.07:31:11.66#ibcon#*mode == 0, iclass 22, count 0 2006.252.07:31:11.66#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.252.07:31:11.66#ibcon#[27=USB\r\n] 2006.252.07:31:11.66#ibcon#*before write, iclass 22, count 0 2006.252.07:31:11.66#ibcon#enter sib2, iclass 22, count 0 2006.252.07:31:11.66#ibcon#flushed, iclass 22, count 0 2006.252.07:31:11.66#ibcon#about to write, iclass 22, count 0 2006.252.07:31:11.66#ibcon#wrote, iclass 22, count 0 2006.252.07:31:11.66#ibcon#about to read 3, iclass 22, count 0 2006.252.07:31:11.69#ibcon#read 3, iclass 22, count 0 2006.252.07:31:11.69#ibcon#about to read 4, iclass 22, count 0 2006.252.07:31:11.69#ibcon#read 4, iclass 22, count 0 2006.252.07:31:11.69#ibcon#about to read 5, iclass 22, count 0 2006.252.07:31:11.69#ibcon#read 5, iclass 22, count 0 2006.252.07:31:11.69#ibcon#about to read 6, iclass 22, count 0 2006.252.07:31:11.69#ibcon#read 6, iclass 22, count 0 2006.252.07:31:11.69#ibcon#end of sib2, iclass 22, count 0 2006.252.07:31:11.69#ibcon#*after write, iclass 22, count 0 2006.252.07:31:11.69#ibcon#*before return 0, iclass 22, count 0 2006.252.07:31:11.69#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.252.07:31:11.69#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.252.07:31:11.69#ibcon#about to clear, iclass 22 cls_cnt 0 2006.252.07:31:11.69#ibcon#cleared, iclass 22 cls_cnt 0 2006.252.07:31:11.69$vc4f8/vblo=4,712.99 2006.252.07:31:11.69#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.252.07:31:11.69#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.252.07:31:11.69#ibcon#ireg 17 cls_cnt 0 2006.252.07:31:11.69#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.252.07:31:11.69#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.252.07:31:11.69#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.252.07:31:11.69#ibcon#enter wrdev, iclass 28, count 0 2006.252.07:31:11.69#ibcon#first serial, iclass 28, count 0 2006.252.07:31:11.69#ibcon#enter sib2, iclass 28, count 0 2006.252.07:31:11.69#ibcon#flushed, iclass 28, count 0 2006.252.07:31:11.69#ibcon#about to write, iclass 28, count 0 2006.252.07:31:11.69#ibcon#wrote, iclass 28, count 0 2006.252.07:31:11.69#ibcon#about to read 3, iclass 28, count 0 2006.252.07:31:11.71#ibcon#read 3, iclass 28, count 0 2006.252.07:31:11.71#ibcon#about to read 4, iclass 28, count 0 2006.252.07:31:11.71#ibcon#read 4, iclass 28, count 0 2006.252.07:31:11.71#ibcon#about to read 5, iclass 28, count 0 2006.252.07:31:11.71#ibcon#read 5, iclass 28, count 0 2006.252.07:31:11.71#ibcon#about to read 6, iclass 28, count 0 2006.252.07:31:11.71#ibcon#read 6, iclass 28, count 0 2006.252.07:31:11.71#ibcon#end of sib2, iclass 28, count 0 2006.252.07:31:11.71#ibcon#*mode == 0, iclass 28, count 0 2006.252.07:31:11.71#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.252.07:31:11.71#ibcon#[28=FRQ=04,712.99\r\n] 2006.252.07:31:11.71#ibcon#*before write, iclass 28, count 0 2006.252.07:31:11.71#ibcon#enter sib2, iclass 28, count 0 2006.252.07:31:11.71#ibcon#flushed, iclass 28, count 0 2006.252.07:31:11.71#ibcon#about to write, iclass 28, count 0 2006.252.07:31:11.71#ibcon#wrote, iclass 28, count 0 2006.252.07:31:11.71#ibcon#about to read 3, iclass 28, count 0 2006.252.07:31:11.75#ibcon#read 3, iclass 28, count 0 2006.252.07:31:11.75#ibcon#about to read 4, iclass 28, count 0 2006.252.07:31:11.75#ibcon#read 4, iclass 28, count 0 2006.252.07:31:11.75#ibcon#about to read 5, iclass 28, count 0 2006.252.07:31:11.75#ibcon#read 5, iclass 28, count 0 2006.252.07:31:11.75#ibcon#about to read 6, iclass 28, count 0 2006.252.07:31:11.75#ibcon#read 6, iclass 28, count 0 2006.252.07:31:11.75#ibcon#end of sib2, iclass 28, count 0 2006.252.07:31:11.75#ibcon#*after write, iclass 28, count 0 2006.252.07:31:11.75#ibcon#*before return 0, iclass 28, count 0 2006.252.07:31:11.75#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.252.07:31:11.75#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.252.07:31:11.75#ibcon#about to clear, iclass 28 cls_cnt 0 2006.252.07:31:11.75#ibcon#cleared, iclass 28 cls_cnt 0 2006.252.07:31:11.75$vc4f8/vb=4,4 2006.252.07:31:11.75#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.252.07:31:11.75#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.252.07:31:11.75#ibcon#ireg 11 cls_cnt 2 2006.252.07:31:11.75#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.252.07:31:11.81#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.252.07:31:11.81#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.252.07:31:11.81#ibcon#enter wrdev, iclass 30, count 2 2006.252.07:31:11.81#ibcon#first serial, iclass 30, count 2 2006.252.07:31:11.81#ibcon#enter sib2, iclass 30, count 2 2006.252.07:31:11.81#ibcon#flushed, iclass 30, count 2 2006.252.07:31:11.81#ibcon#about to write, iclass 30, count 2 2006.252.07:31:11.81#ibcon#wrote, iclass 30, count 2 2006.252.07:31:11.81#ibcon#about to read 3, iclass 30, count 2 2006.252.07:31:11.83#ibcon#read 3, iclass 30, count 2 2006.252.07:31:11.83#ibcon#about to read 4, iclass 30, count 2 2006.252.07:31:11.83#ibcon#read 4, iclass 30, count 2 2006.252.07:31:11.83#ibcon#about to read 5, iclass 30, count 2 2006.252.07:31:11.83#ibcon#read 5, iclass 30, count 2 2006.252.07:31:11.83#ibcon#about to read 6, iclass 30, count 2 2006.252.07:31:11.83#ibcon#read 6, iclass 30, count 2 2006.252.07:31:11.83#ibcon#end of sib2, iclass 30, count 2 2006.252.07:31:11.83#ibcon#*mode == 0, iclass 30, count 2 2006.252.07:31:11.83#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.252.07:31:11.83#ibcon#[27=AT04-04\r\n] 2006.252.07:31:11.83#ibcon#*before write, iclass 30, count 2 2006.252.07:31:11.83#ibcon#enter sib2, iclass 30, count 2 2006.252.07:31:11.83#ibcon#flushed, iclass 30, count 2 2006.252.07:31:11.83#ibcon#about to write, iclass 30, count 2 2006.252.07:31:11.83#ibcon#wrote, iclass 30, count 2 2006.252.07:31:11.83#ibcon#about to read 3, iclass 30, count 2 2006.252.07:31:11.86#ibcon#read 3, iclass 30, count 2 2006.252.07:31:11.86#ibcon#about to read 4, iclass 30, count 2 2006.252.07:31:11.86#ibcon#read 4, iclass 30, count 2 2006.252.07:31:11.86#ibcon#about to read 5, iclass 30, count 2 2006.252.07:31:11.86#ibcon#read 5, iclass 30, count 2 2006.252.07:31:11.86#ibcon#about to read 6, iclass 30, count 2 2006.252.07:31:11.86#ibcon#read 6, iclass 30, count 2 2006.252.07:31:11.86#ibcon#end of sib2, iclass 30, count 2 2006.252.07:31:11.86#ibcon#*after write, iclass 30, count 2 2006.252.07:31:11.86#ibcon#*before return 0, iclass 30, count 2 2006.252.07:31:11.86#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.252.07:31:11.86#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.252.07:31:11.86#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.252.07:31:11.86#ibcon#ireg 7 cls_cnt 0 2006.252.07:31:11.86#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.252.07:31:11.98#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.252.07:31:11.98#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.252.07:31:11.98#ibcon#enter wrdev, iclass 30, count 0 2006.252.07:31:11.98#ibcon#first serial, iclass 30, count 0 2006.252.07:31:11.98#ibcon#enter sib2, iclass 30, count 0 2006.252.07:31:11.98#ibcon#flushed, iclass 30, count 0 2006.252.07:31:11.98#ibcon#about to write, iclass 30, count 0 2006.252.07:31:11.98#ibcon#wrote, iclass 30, count 0 2006.252.07:31:11.98#ibcon#about to read 3, iclass 30, count 0 2006.252.07:31:12.00#ibcon#read 3, iclass 30, count 0 2006.252.07:31:12.00#ibcon#about to read 4, iclass 30, count 0 2006.252.07:31:12.00#ibcon#read 4, iclass 30, count 0 2006.252.07:31:12.00#ibcon#about to read 5, iclass 30, count 0 2006.252.07:31:12.00#ibcon#read 5, iclass 30, count 0 2006.252.07:31:12.00#ibcon#about to read 6, iclass 30, count 0 2006.252.07:31:12.00#ibcon#read 6, iclass 30, count 0 2006.252.07:31:12.00#ibcon#end of sib2, iclass 30, count 0 2006.252.07:31:12.00#ibcon#*mode == 0, iclass 30, count 0 2006.252.07:31:12.00#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.252.07:31:12.00#ibcon#[27=USB\r\n] 2006.252.07:31:12.00#ibcon#*before write, iclass 30, count 0 2006.252.07:31:12.00#ibcon#enter sib2, iclass 30, count 0 2006.252.07:31:12.00#ibcon#flushed, iclass 30, count 0 2006.252.07:31:12.00#ibcon#about to write, iclass 30, count 0 2006.252.07:31:12.00#ibcon#wrote, iclass 30, count 0 2006.252.07:31:12.00#ibcon#about to read 3, iclass 30, count 0 2006.252.07:31:12.03#ibcon#read 3, iclass 30, count 0 2006.252.07:31:12.03#ibcon#about to read 4, iclass 30, count 0 2006.252.07:31:12.03#ibcon#read 4, iclass 30, count 0 2006.252.07:31:12.03#ibcon#about to read 5, iclass 30, count 0 2006.252.07:31:12.03#ibcon#read 5, iclass 30, count 0 2006.252.07:31:12.03#ibcon#about to read 6, iclass 30, count 0 2006.252.07:31:12.03#ibcon#read 6, iclass 30, count 0 2006.252.07:31:12.03#ibcon#end of sib2, iclass 30, count 0 2006.252.07:31:12.03#ibcon#*after write, iclass 30, count 0 2006.252.07:31:12.03#ibcon#*before return 0, iclass 30, count 0 2006.252.07:31:12.03#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.252.07:31:12.03#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.252.07:31:12.03#ibcon#about to clear, iclass 30 cls_cnt 0 2006.252.07:31:12.03#ibcon#cleared, iclass 30 cls_cnt 0 2006.252.07:31:12.03$vc4f8/vblo=5,744.99 2006.252.07:31:12.03#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.252.07:31:12.03#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.252.07:31:12.03#ibcon#ireg 17 cls_cnt 0 2006.252.07:31:12.03#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.252.07:31:12.03#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.252.07:31:12.03#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.252.07:31:12.03#ibcon#enter wrdev, iclass 32, count 0 2006.252.07:31:12.03#ibcon#first serial, iclass 32, count 0 2006.252.07:31:12.03#ibcon#enter sib2, iclass 32, count 0 2006.252.07:31:12.03#ibcon#flushed, iclass 32, count 0 2006.252.07:31:12.03#ibcon#about to write, iclass 32, count 0 2006.252.07:31:12.03#ibcon#wrote, iclass 32, count 0 2006.252.07:31:12.03#ibcon#about to read 3, iclass 32, count 0 2006.252.07:31:12.05#ibcon#read 3, iclass 32, count 0 2006.252.07:31:12.05#ibcon#about to read 4, iclass 32, count 0 2006.252.07:31:12.05#ibcon#read 4, iclass 32, count 0 2006.252.07:31:12.05#ibcon#about to read 5, iclass 32, count 0 2006.252.07:31:12.05#ibcon#read 5, iclass 32, count 0 2006.252.07:31:12.05#ibcon#about to read 6, iclass 32, count 0 2006.252.07:31:12.05#ibcon#read 6, iclass 32, count 0 2006.252.07:31:12.05#ibcon#end of sib2, iclass 32, count 0 2006.252.07:31:12.05#ibcon#*mode == 0, iclass 32, count 0 2006.252.07:31:12.05#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.252.07:31:12.05#ibcon#[28=FRQ=05,744.99\r\n] 2006.252.07:31:12.05#ibcon#*before write, iclass 32, count 0 2006.252.07:31:12.05#ibcon#enter sib2, iclass 32, count 0 2006.252.07:31:12.05#ibcon#flushed, iclass 32, count 0 2006.252.07:31:12.05#ibcon#about to write, iclass 32, count 0 2006.252.07:31:12.05#ibcon#wrote, iclass 32, count 0 2006.252.07:31:12.05#ibcon#about to read 3, iclass 32, count 0 2006.252.07:31:12.09#ibcon#read 3, iclass 32, count 0 2006.252.07:31:12.09#ibcon#about to read 4, iclass 32, count 0 2006.252.07:31:12.09#ibcon#read 4, iclass 32, count 0 2006.252.07:31:12.09#ibcon#about to read 5, iclass 32, count 0 2006.252.07:31:12.09#ibcon#read 5, iclass 32, count 0 2006.252.07:31:12.09#ibcon#about to read 6, iclass 32, count 0 2006.252.07:31:12.09#ibcon#read 6, iclass 32, count 0 2006.252.07:31:12.09#ibcon#end of sib2, iclass 32, count 0 2006.252.07:31:12.09#ibcon#*after write, iclass 32, count 0 2006.252.07:31:12.09#ibcon#*before return 0, iclass 32, count 0 2006.252.07:31:12.09#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.252.07:31:12.09#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.252.07:31:12.09#ibcon#about to clear, iclass 32 cls_cnt 0 2006.252.07:31:12.09#ibcon#cleared, iclass 32 cls_cnt 0 2006.252.07:31:12.09$vc4f8/vb=5,4 2006.252.07:31:12.09#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.252.07:31:12.09#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.252.07:31:12.09#ibcon#ireg 11 cls_cnt 2 2006.252.07:31:12.09#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.252.07:31:12.15#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.252.07:31:12.15#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.252.07:31:12.15#ibcon#enter wrdev, iclass 34, count 2 2006.252.07:31:12.15#ibcon#first serial, iclass 34, count 2 2006.252.07:31:12.15#ibcon#enter sib2, iclass 34, count 2 2006.252.07:31:12.15#ibcon#flushed, iclass 34, count 2 2006.252.07:31:12.15#ibcon#about to write, iclass 34, count 2 2006.252.07:31:12.15#ibcon#wrote, iclass 34, count 2 2006.252.07:31:12.15#ibcon#about to read 3, iclass 34, count 2 2006.252.07:31:12.17#ibcon#read 3, iclass 34, count 2 2006.252.07:31:12.17#ibcon#about to read 4, iclass 34, count 2 2006.252.07:31:12.17#ibcon#read 4, iclass 34, count 2 2006.252.07:31:12.17#ibcon#about to read 5, iclass 34, count 2 2006.252.07:31:12.17#ibcon#read 5, iclass 34, count 2 2006.252.07:31:12.17#ibcon#about to read 6, iclass 34, count 2 2006.252.07:31:12.17#ibcon#read 6, iclass 34, count 2 2006.252.07:31:12.17#ibcon#end of sib2, iclass 34, count 2 2006.252.07:31:12.17#ibcon#*mode == 0, iclass 34, count 2 2006.252.07:31:12.17#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.252.07:31:12.17#ibcon#[27=AT05-04\r\n] 2006.252.07:31:12.17#ibcon#*before write, iclass 34, count 2 2006.252.07:31:12.17#ibcon#enter sib2, iclass 34, count 2 2006.252.07:31:12.17#ibcon#flushed, iclass 34, count 2 2006.252.07:31:12.17#ibcon#about to write, iclass 34, count 2 2006.252.07:31:12.17#ibcon#wrote, iclass 34, count 2 2006.252.07:31:12.17#ibcon#about to read 3, iclass 34, count 2 2006.252.07:31:12.20#ibcon#read 3, iclass 34, count 2 2006.252.07:31:12.20#ibcon#about to read 4, iclass 34, count 2 2006.252.07:31:12.20#ibcon#read 4, iclass 34, count 2 2006.252.07:31:12.20#ibcon#about to read 5, iclass 34, count 2 2006.252.07:31:12.20#ibcon#read 5, iclass 34, count 2 2006.252.07:31:12.20#ibcon#about to read 6, iclass 34, count 2 2006.252.07:31:12.20#ibcon#read 6, iclass 34, count 2 2006.252.07:31:12.20#ibcon#end of sib2, iclass 34, count 2 2006.252.07:31:12.20#ibcon#*after write, iclass 34, count 2 2006.252.07:31:12.20#ibcon#*before return 0, iclass 34, count 2 2006.252.07:31:12.20#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.252.07:31:12.20#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.252.07:31:12.20#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.252.07:31:12.20#ibcon#ireg 7 cls_cnt 0 2006.252.07:31:12.20#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.252.07:31:12.32#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.252.07:31:12.32#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.252.07:31:12.32#ibcon#enter wrdev, iclass 34, count 0 2006.252.07:31:12.32#ibcon#first serial, iclass 34, count 0 2006.252.07:31:12.32#ibcon#enter sib2, iclass 34, count 0 2006.252.07:31:12.32#ibcon#flushed, iclass 34, count 0 2006.252.07:31:12.32#ibcon#about to write, iclass 34, count 0 2006.252.07:31:12.32#ibcon#wrote, iclass 34, count 0 2006.252.07:31:12.32#ibcon#about to read 3, iclass 34, count 0 2006.252.07:31:12.34#ibcon#read 3, iclass 34, count 0 2006.252.07:31:12.34#ibcon#about to read 4, iclass 34, count 0 2006.252.07:31:12.34#ibcon#read 4, iclass 34, count 0 2006.252.07:31:12.34#ibcon#about to read 5, iclass 34, count 0 2006.252.07:31:12.34#ibcon#read 5, iclass 34, count 0 2006.252.07:31:12.34#ibcon#about to read 6, iclass 34, count 0 2006.252.07:31:12.34#ibcon#read 6, iclass 34, count 0 2006.252.07:31:12.34#ibcon#end of sib2, iclass 34, count 0 2006.252.07:31:12.34#ibcon#*mode == 0, iclass 34, count 0 2006.252.07:31:12.34#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.252.07:31:12.34#ibcon#[27=USB\r\n] 2006.252.07:31:12.34#ibcon#*before write, iclass 34, count 0 2006.252.07:31:12.34#ibcon#enter sib2, iclass 34, count 0 2006.252.07:31:12.34#ibcon#flushed, iclass 34, count 0 2006.252.07:31:12.34#ibcon#about to write, iclass 34, count 0 2006.252.07:31:12.34#ibcon#wrote, iclass 34, count 0 2006.252.07:31:12.34#ibcon#about to read 3, iclass 34, count 0 2006.252.07:31:12.37#ibcon#read 3, iclass 34, count 0 2006.252.07:31:12.37#ibcon#about to read 4, iclass 34, count 0 2006.252.07:31:12.37#ibcon#read 4, iclass 34, count 0 2006.252.07:31:12.37#ibcon#about to read 5, iclass 34, count 0 2006.252.07:31:12.37#ibcon#read 5, iclass 34, count 0 2006.252.07:31:12.37#ibcon#about to read 6, iclass 34, count 0 2006.252.07:31:12.37#ibcon#read 6, iclass 34, count 0 2006.252.07:31:12.37#ibcon#end of sib2, iclass 34, count 0 2006.252.07:31:12.37#ibcon#*after write, iclass 34, count 0 2006.252.07:31:12.37#ibcon#*before return 0, iclass 34, count 0 2006.252.07:31:12.37#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.252.07:31:12.37#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.252.07:31:12.37#ibcon#about to clear, iclass 34 cls_cnt 0 2006.252.07:31:12.37#ibcon#cleared, iclass 34 cls_cnt 0 2006.252.07:31:12.37$vc4f8/vblo=6,752.99 2006.252.07:31:12.37#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.252.07:31:12.37#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.252.07:31:12.37#ibcon#ireg 17 cls_cnt 0 2006.252.07:31:12.37#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.252.07:31:12.37#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.252.07:31:12.37#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.252.07:31:12.37#ibcon#enter wrdev, iclass 36, count 0 2006.252.07:31:12.37#ibcon#first serial, iclass 36, count 0 2006.252.07:31:12.37#ibcon#enter sib2, iclass 36, count 0 2006.252.07:31:12.37#ibcon#flushed, iclass 36, count 0 2006.252.07:31:12.37#ibcon#about to write, iclass 36, count 0 2006.252.07:31:12.37#ibcon#wrote, iclass 36, count 0 2006.252.07:31:12.37#ibcon#about to read 3, iclass 36, count 0 2006.252.07:31:12.39#ibcon#read 3, iclass 36, count 0 2006.252.07:31:12.39#ibcon#about to read 4, iclass 36, count 0 2006.252.07:31:12.39#ibcon#read 4, iclass 36, count 0 2006.252.07:31:12.39#ibcon#about to read 5, iclass 36, count 0 2006.252.07:31:12.39#ibcon#read 5, iclass 36, count 0 2006.252.07:31:12.39#ibcon#about to read 6, iclass 36, count 0 2006.252.07:31:12.39#ibcon#read 6, iclass 36, count 0 2006.252.07:31:12.39#ibcon#end of sib2, iclass 36, count 0 2006.252.07:31:12.39#ibcon#*mode == 0, iclass 36, count 0 2006.252.07:31:12.39#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.252.07:31:12.39#ibcon#[28=FRQ=06,752.99\r\n] 2006.252.07:31:12.39#ibcon#*before write, iclass 36, count 0 2006.252.07:31:12.39#ibcon#enter sib2, iclass 36, count 0 2006.252.07:31:12.39#ibcon#flushed, iclass 36, count 0 2006.252.07:31:12.39#ibcon#about to write, iclass 36, count 0 2006.252.07:31:12.39#ibcon#wrote, iclass 36, count 0 2006.252.07:31:12.39#ibcon#about to read 3, iclass 36, count 0 2006.252.07:31:12.43#ibcon#read 3, iclass 36, count 0 2006.252.07:31:12.43#ibcon#about to read 4, iclass 36, count 0 2006.252.07:31:12.43#ibcon#read 4, iclass 36, count 0 2006.252.07:31:12.43#ibcon#about to read 5, iclass 36, count 0 2006.252.07:31:12.43#ibcon#read 5, iclass 36, count 0 2006.252.07:31:12.43#ibcon#about to read 6, iclass 36, count 0 2006.252.07:31:12.43#ibcon#read 6, iclass 36, count 0 2006.252.07:31:12.43#ibcon#end of sib2, iclass 36, count 0 2006.252.07:31:12.43#ibcon#*after write, iclass 36, count 0 2006.252.07:31:12.43#ibcon#*before return 0, iclass 36, count 0 2006.252.07:31:12.43#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.252.07:31:12.43#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.252.07:31:12.43#ibcon#about to clear, iclass 36 cls_cnt 0 2006.252.07:31:12.43#ibcon#cleared, iclass 36 cls_cnt 0 2006.252.07:31:12.43$vc4f8/vb=6,4 2006.252.07:31:12.43#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.252.07:31:12.43#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.252.07:31:12.43#ibcon#ireg 11 cls_cnt 2 2006.252.07:31:12.43#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.252.07:31:12.49#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.252.07:31:12.49#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.252.07:31:12.49#ibcon#enter wrdev, iclass 38, count 2 2006.252.07:31:12.49#ibcon#first serial, iclass 38, count 2 2006.252.07:31:12.49#ibcon#enter sib2, iclass 38, count 2 2006.252.07:31:12.49#ibcon#flushed, iclass 38, count 2 2006.252.07:31:12.49#ibcon#about to write, iclass 38, count 2 2006.252.07:31:12.49#ibcon#wrote, iclass 38, count 2 2006.252.07:31:12.49#ibcon#about to read 3, iclass 38, count 2 2006.252.07:31:12.51#ibcon#read 3, iclass 38, count 2 2006.252.07:31:12.51#ibcon#about to read 4, iclass 38, count 2 2006.252.07:31:12.51#ibcon#read 4, iclass 38, count 2 2006.252.07:31:12.51#ibcon#about to read 5, iclass 38, count 2 2006.252.07:31:12.51#ibcon#read 5, iclass 38, count 2 2006.252.07:31:12.51#ibcon#about to read 6, iclass 38, count 2 2006.252.07:31:12.51#ibcon#read 6, iclass 38, count 2 2006.252.07:31:12.51#ibcon#end of sib2, iclass 38, count 2 2006.252.07:31:12.51#ibcon#*mode == 0, iclass 38, count 2 2006.252.07:31:12.51#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.252.07:31:12.51#ibcon#[27=AT06-04\r\n] 2006.252.07:31:12.51#ibcon#*before write, iclass 38, count 2 2006.252.07:31:12.51#ibcon#enter sib2, iclass 38, count 2 2006.252.07:31:12.51#ibcon#flushed, iclass 38, count 2 2006.252.07:31:12.51#ibcon#about to write, iclass 38, count 2 2006.252.07:31:12.51#ibcon#wrote, iclass 38, count 2 2006.252.07:31:12.51#ibcon#about to read 3, iclass 38, count 2 2006.252.07:31:12.54#ibcon#read 3, iclass 38, count 2 2006.252.07:31:12.54#ibcon#about to read 4, iclass 38, count 2 2006.252.07:31:12.54#ibcon#read 4, iclass 38, count 2 2006.252.07:31:12.54#ibcon#about to read 5, iclass 38, count 2 2006.252.07:31:12.54#ibcon#read 5, iclass 38, count 2 2006.252.07:31:12.54#ibcon#about to read 6, iclass 38, count 2 2006.252.07:31:12.54#ibcon#read 6, iclass 38, count 2 2006.252.07:31:12.54#ibcon#end of sib2, iclass 38, count 2 2006.252.07:31:12.54#ibcon#*after write, iclass 38, count 2 2006.252.07:31:12.54#ibcon#*before return 0, iclass 38, count 2 2006.252.07:31:12.54#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.252.07:31:12.54#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.252.07:31:12.54#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.252.07:31:12.54#ibcon#ireg 7 cls_cnt 0 2006.252.07:31:12.54#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.252.07:31:12.66#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.252.07:31:12.66#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.252.07:31:12.66#ibcon#enter wrdev, iclass 38, count 0 2006.252.07:31:12.66#ibcon#first serial, iclass 38, count 0 2006.252.07:31:12.66#ibcon#enter sib2, iclass 38, count 0 2006.252.07:31:12.66#ibcon#flushed, iclass 38, count 0 2006.252.07:31:12.66#ibcon#about to write, iclass 38, count 0 2006.252.07:31:12.66#ibcon#wrote, iclass 38, count 0 2006.252.07:31:12.66#ibcon#about to read 3, iclass 38, count 0 2006.252.07:31:12.68#ibcon#read 3, iclass 38, count 0 2006.252.07:31:12.68#ibcon#about to read 4, iclass 38, count 0 2006.252.07:31:12.68#ibcon#read 4, iclass 38, count 0 2006.252.07:31:12.68#ibcon#about to read 5, iclass 38, count 0 2006.252.07:31:12.68#ibcon#read 5, iclass 38, count 0 2006.252.07:31:12.68#ibcon#about to read 6, iclass 38, count 0 2006.252.07:31:12.68#ibcon#read 6, iclass 38, count 0 2006.252.07:31:12.68#ibcon#end of sib2, iclass 38, count 0 2006.252.07:31:12.68#ibcon#*mode == 0, iclass 38, count 0 2006.252.07:31:12.68#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.252.07:31:12.68#ibcon#[27=USB\r\n] 2006.252.07:31:12.68#ibcon#*before write, iclass 38, count 0 2006.252.07:31:12.68#ibcon#enter sib2, iclass 38, count 0 2006.252.07:31:12.68#ibcon#flushed, iclass 38, count 0 2006.252.07:31:12.68#ibcon#about to write, iclass 38, count 0 2006.252.07:31:12.68#ibcon#wrote, iclass 38, count 0 2006.252.07:31:12.68#ibcon#about to read 3, iclass 38, count 0 2006.252.07:31:12.71#ibcon#read 3, iclass 38, count 0 2006.252.07:31:12.71#ibcon#about to read 4, iclass 38, count 0 2006.252.07:31:12.71#ibcon#read 4, iclass 38, count 0 2006.252.07:31:12.71#ibcon#about to read 5, iclass 38, count 0 2006.252.07:31:12.71#ibcon#read 5, iclass 38, count 0 2006.252.07:31:12.71#ibcon#about to read 6, iclass 38, count 0 2006.252.07:31:12.71#ibcon#read 6, iclass 38, count 0 2006.252.07:31:12.71#ibcon#end of sib2, iclass 38, count 0 2006.252.07:31:12.71#ibcon#*after write, iclass 38, count 0 2006.252.07:31:12.71#ibcon#*before return 0, iclass 38, count 0 2006.252.07:31:12.71#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.252.07:31:12.71#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.252.07:31:12.71#ibcon#about to clear, iclass 38 cls_cnt 0 2006.252.07:31:12.71#ibcon#cleared, iclass 38 cls_cnt 0 2006.252.07:31:12.71$vc4f8/vabw=wide 2006.252.07:31:12.71#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.252.07:31:12.71#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.252.07:31:12.71#ibcon#ireg 8 cls_cnt 0 2006.252.07:31:12.71#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.252.07:31:12.71#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.252.07:31:12.71#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.252.07:31:12.71#ibcon#enter wrdev, iclass 40, count 0 2006.252.07:31:12.71#ibcon#first serial, iclass 40, count 0 2006.252.07:31:12.71#ibcon#enter sib2, iclass 40, count 0 2006.252.07:31:12.71#ibcon#flushed, iclass 40, count 0 2006.252.07:31:12.71#ibcon#about to write, iclass 40, count 0 2006.252.07:31:12.71#ibcon#wrote, iclass 40, count 0 2006.252.07:31:12.71#ibcon#about to read 3, iclass 40, count 0 2006.252.07:31:12.73#ibcon#read 3, iclass 40, count 0 2006.252.07:31:12.73#ibcon#about to read 4, iclass 40, count 0 2006.252.07:31:12.73#ibcon#read 4, iclass 40, count 0 2006.252.07:31:12.73#ibcon#about to read 5, iclass 40, count 0 2006.252.07:31:12.73#ibcon#read 5, iclass 40, count 0 2006.252.07:31:12.73#ibcon#about to read 6, iclass 40, count 0 2006.252.07:31:12.73#ibcon#read 6, iclass 40, count 0 2006.252.07:31:12.73#ibcon#end of sib2, iclass 40, count 0 2006.252.07:31:12.73#ibcon#*mode == 0, iclass 40, count 0 2006.252.07:31:12.73#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.252.07:31:12.73#ibcon#[25=BW32\r\n] 2006.252.07:31:12.73#ibcon#*before write, iclass 40, count 0 2006.252.07:31:12.73#ibcon#enter sib2, iclass 40, count 0 2006.252.07:31:12.73#ibcon#flushed, iclass 40, count 0 2006.252.07:31:12.73#ibcon#about to write, iclass 40, count 0 2006.252.07:31:12.73#ibcon#wrote, iclass 40, count 0 2006.252.07:31:12.73#ibcon#about to read 3, iclass 40, count 0 2006.252.07:31:12.76#ibcon#read 3, iclass 40, count 0 2006.252.07:31:12.76#ibcon#about to read 4, iclass 40, count 0 2006.252.07:31:12.76#ibcon#read 4, iclass 40, count 0 2006.252.07:31:12.76#ibcon#about to read 5, iclass 40, count 0 2006.252.07:31:12.76#ibcon#read 5, iclass 40, count 0 2006.252.07:31:12.76#ibcon#about to read 6, iclass 40, count 0 2006.252.07:31:12.76#ibcon#read 6, iclass 40, count 0 2006.252.07:31:12.76#ibcon#end of sib2, iclass 40, count 0 2006.252.07:31:12.76#ibcon#*after write, iclass 40, count 0 2006.252.07:31:12.76#ibcon#*before return 0, iclass 40, count 0 2006.252.07:31:12.76#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.252.07:31:12.76#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.252.07:31:12.76#ibcon#about to clear, iclass 40 cls_cnt 0 2006.252.07:31:12.76#ibcon#cleared, iclass 40 cls_cnt 0 2006.252.07:31:12.76$vc4f8/vbbw=wide 2006.252.07:31:12.76#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.252.07:31:12.76#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.252.07:31:12.76#ibcon#ireg 8 cls_cnt 0 2006.252.07:31:12.76#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.252.07:31:12.83#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.252.07:31:12.83#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.252.07:31:12.83#ibcon#enter wrdev, iclass 4, count 0 2006.252.07:31:12.83#ibcon#first serial, iclass 4, count 0 2006.252.07:31:12.83#ibcon#enter sib2, iclass 4, count 0 2006.252.07:31:12.83#ibcon#flushed, iclass 4, count 0 2006.252.07:31:12.83#ibcon#about to write, iclass 4, count 0 2006.252.07:31:12.83#ibcon#wrote, iclass 4, count 0 2006.252.07:31:12.83#ibcon#about to read 3, iclass 4, count 0 2006.252.07:31:12.85#ibcon#read 3, iclass 4, count 0 2006.252.07:31:12.85#ibcon#about to read 4, iclass 4, count 0 2006.252.07:31:12.85#ibcon#read 4, iclass 4, count 0 2006.252.07:31:12.85#ibcon#about to read 5, iclass 4, count 0 2006.252.07:31:12.85#ibcon#read 5, iclass 4, count 0 2006.252.07:31:12.85#ibcon#about to read 6, iclass 4, count 0 2006.252.07:31:12.85#ibcon#read 6, iclass 4, count 0 2006.252.07:31:12.85#ibcon#end of sib2, iclass 4, count 0 2006.252.07:31:12.85#ibcon#*mode == 0, iclass 4, count 0 2006.252.07:31:12.85#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.252.07:31:12.85#ibcon#[27=BW32\r\n] 2006.252.07:31:12.85#ibcon#*before write, iclass 4, count 0 2006.252.07:31:12.85#ibcon#enter sib2, iclass 4, count 0 2006.252.07:31:12.85#ibcon#flushed, iclass 4, count 0 2006.252.07:31:12.85#ibcon#about to write, iclass 4, count 0 2006.252.07:31:12.85#ibcon#wrote, iclass 4, count 0 2006.252.07:31:12.85#ibcon#about to read 3, iclass 4, count 0 2006.252.07:31:12.88#ibcon#read 3, iclass 4, count 0 2006.252.07:31:12.88#ibcon#about to read 4, iclass 4, count 0 2006.252.07:31:12.88#ibcon#read 4, iclass 4, count 0 2006.252.07:31:12.88#ibcon#about to read 5, iclass 4, count 0 2006.252.07:31:12.88#ibcon#read 5, iclass 4, count 0 2006.252.07:31:12.88#ibcon#about to read 6, iclass 4, count 0 2006.252.07:31:12.88#ibcon#read 6, iclass 4, count 0 2006.252.07:31:12.88#ibcon#end of sib2, iclass 4, count 0 2006.252.07:31:12.88#ibcon#*after write, iclass 4, count 0 2006.252.07:31:12.88#ibcon#*before return 0, iclass 4, count 0 2006.252.07:31:12.88#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.252.07:31:12.88#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.252.07:31:12.88#ibcon#about to clear, iclass 4 cls_cnt 0 2006.252.07:31:12.88#ibcon#cleared, iclass 4 cls_cnt 0 2006.252.07:31:12.88$4f8m12a/ifd4f 2006.252.07:31:12.88$ifd4f/lo= 2006.252.07:31:12.88$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.252.07:31:12.88$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.252.07:31:12.88$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.252.07:31:12.88$ifd4f/patch= 2006.252.07:31:12.88$ifd4f/patch=lo1,a1,a2,a3,a4 2006.252.07:31:12.88$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.252.07:31:12.88$ifd4f/patch=lo3,a5,a6,a7,a8 2006.252.07:31:12.88$4f8m12a/"form=m,16.000,1:2 2006.252.07:31:12.88$4f8m12a/"tpicd 2006.252.07:31:12.88$4f8m12a/echo=off 2006.252.07:31:12.88$4f8m12a/xlog=off 2006.252.07:31:12.88:!2006.252.07:33:20 2006.252.07:31:25.14#trakl#Source acquired 2006.252.07:31:25.14#flagr#flagr/antenna,acquired 2006.252.07:33:20.00:preob 2006.252.07:33:20.14/onsource/TRACKING 2006.252.07:33:20.14:!2006.252.07:33:30 2006.252.07:33:30.00:data_valid=on 2006.252.07:33:30.00:midob 2006.252.07:33:31.14/onsource/TRACKING 2006.252.07:33:31.14/wx/27.50,1011.3,90 2006.252.07:33:31.23/cable/+6.4092E-03 2006.252.07:33:32.32/va/01,08,usb,yes,33,35 2006.252.07:33:32.32/va/02,07,usb,yes,33,35 2006.252.07:33:32.32/va/03,06,usb,yes,35,35 2006.252.07:33:32.32/va/04,07,usb,yes,34,36 2006.252.07:33:32.32/va/05,07,usb,yes,36,38 2006.252.07:33:32.32/va/06,07,usb,yes,32,32 2006.252.07:33:32.32/va/07,07,usb,yes,31,31 2006.252.07:33:32.32/va/08,07,usb,yes,34,33 2006.252.07:33:32.55/valo/01,532.99,yes,locked 2006.252.07:33:32.55/valo/02,572.99,yes,locked 2006.252.07:33:32.55/valo/03,672.99,yes,locked 2006.252.07:33:32.55/valo/04,832.99,yes,locked 2006.252.07:33:32.55/valo/05,652.99,yes,locked 2006.252.07:33:32.55/valo/06,772.99,yes,locked 2006.252.07:33:32.55/valo/07,832.99,yes,locked 2006.252.07:33:32.55/valo/08,852.99,yes,locked 2006.252.07:33:33.64/vb/01,04,usb,yes,31,30 2006.252.07:33:33.64/vb/02,05,usb,yes,29,30 2006.252.07:33:33.64/vb/03,04,usb,yes,29,33 2006.252.07:33:33.64/vb/04,04,usb,yes,30,30 2006.252.07:33:33.64/vb/05,04,usb,yes,28,32 2006.252.07:33:33.64/vb/06,04,usb,yes,29,32 2006.252.07:33:33.64/vb/07,04,usb,yes,32,31 2006.252.07:33:33.64/vb/08,04,usb,yes,29,32 2006.252.07:33:33.87/vblo/01,632.99,yes,locked 2006.252.07:33:33.87/vblo/02,640.99,yes,locked 2006.252.07:33:33.87/vblo/03,656.99,yes,locked 2006.252.07:33:33.87/vblo/04,712.99,yes,locked 2006.252.07:33:33.87/vblo/05,744.99,yes,locked 2006.252.07:33:33.87/vblo/06,752.99,yes,locked 2006.252.07:33:33.87/vblo/07,734.99,yes,locked 2006.252.07:33:33.87/vblo/08,744.99,yes,locked 2006.252.07:33:34.02/vabw/8 2006.252.07:33:34.17/vbbw/8 2006.252.07:33:34.26/xfe/off,on,14.0 2006.252.07:33:34.65/ifatt/23,28,28,28 2006.252.07:33:35.08/fmout-gps/S +4.69E-07 2006.252.07:33:35.12:!2006.252.07:34:50 2006.252.07:34:50.00:data_valid=off 2006.252.07:34:50.00:postob 2006.252.07:34:50.11/cable/+6.4088E-03 2006.252.07:34:50.11/wx/27.48,1011.2,91 2006.252.07:34:51.08/fmout-gps/S +4.70E-07 2006.252.07:34:51.08:scan_name=252-0736,k06252,60 2006.252.07:34:51.08:source=1357+769,135755.37,764321.1,2000.0,ccw 2006.252.07:34:52.14#flagr#flagr/antenna,new-source 2006.252.07:34:52.14:checkk5 2006.252.07:34:52.52/chk_autoobs//k5ts1/ autoobs is running! 2006.252.07:34:52.90/chk_autoobs//k5ts2/ autoobs is running! 2006.252.07:34:53.27/chk_autoobs//k5ts3/ autoobs is running! 2006.252.07:34:53.64/chk_autoobs//k5ts4/ autoobs is running! 2006.252.07:34:54.01/chk_obsdata//k5ts1/T2520733??a.dat file size is correct (nominal:640MB, actual:632MB). 2006.252.07:34:54.38/chk_obsdata//k5ts2/T2520733??b.dat file size is correct (nominal:640MB, actual:632MB). 2006.252.07:34:54.75/chk_obsdata//k5ts3/T2520733??c.dat file size is correct (nominal:640MB, actual:632MB). 2006.252.07:34:55.12/chk_obsdata//k5ts4/T2520733??d.dat file size is correct (nominal:640MB, actual:632MB). 2006.252.07:34:55.81/k5log//k5ts1_log_newline 2006.252.07:34:56.50/k5log//k5ts2_log_newline 2006.252.07:34:57.18/k5log//k5ts3_log_newline 2006.252.07:34:57.88/k5log//k5ts4_log_newline 2006.252.07:34:57.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.252.07:34:57.90:4f8m12a=1 2006.252.07:34:57.90$4f8m12a/echo=on 2006.252.07:34:57.90$4f8m12a/pcalon 2006.252.07:34:57.90$pcalon/"no phase cal control is implemented here 2006.252.07:34:57.90$4f8m12a/"tpicd=stop 2006.252.07:34:57.90$4f8m12a/vc4f8 2006.252.07:34:57.90$vc4f8/valo=1,532.99 2006.252.07:34:57.90#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.252.07:34:57.90#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.252.07:34:57.90#ibcon#ireg 17 cls_cnt 0 2006.252.07:34:57.90#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.252.07:34:57.90#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.252.07:34:57.90#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.252.07:34:57.90#ibcon#enter wrdev, iclass 25, count 0 2006.252.07:34:57.90#ibcon#first serial, iclass 25, count 0 2006.252.07:34:57.90#ibcon#enter sib2, iclass 25, count 0 2006.252.07:34:57.90#ibcon#flushed, iclass 25, count 0 2006.252.07:34:57.90#ibcon#about to write, iclass 25, count 0 2006.252.07:34:57.90#ibcon#wrote, iclass 25, count 0 2006.252.07:34:57.90#ibcon#about to read 3, iclass 25, count 0 2006.252.07:34:57.94#ibcon#read 3, iclass 25, count 0 2006.252.07:34:57.94#ibcon#about to read 4, iclass 25, count 0 2006.252.07:34:57.94#ibcon#read 4, iclass 25, count 0 2006.252.07:34:57.94#ibcon#about to read 5, iclass 25, count 0 2006.252.07:34:57.94#ibcon#read 5, iclass 25, count 0 2006.252.07:34:57.94#ibcon#about to read 6, iclass 25, count 0 2006.252.07:34:57.94#ibcon#read 6, iclass 25, count 0 2006.252.07:34:57.94#ibcon#end of sib2, iclass 25, count 0 2006.252.07:34:57.94#ibcon#*mode == 0, iclass 25, count 0 2006.252.07:34:57.94#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.252.07:34:57.94#ibcon#[26=FRQ=01,532.99\r\n] 2006.252.07:34:57.94#ibcon#*before write, iclass 25, count 0 2006.252.07:34:57.94#ibcon#enter sib2, iclass 25, count 0 2006.252.07:34:57.94#ibcon#flushed, iclass 25, count 0 2006.252.07:34:57.94#ibcon#about to write, iclass 25, count 0 2006.252.07:34:57.94#ibcon#wrote, iclass 25, count 0 2006.252.07:34:57.94#ibcon#about to read 3, iclass 25, count 0 2006.252.07:34:58.00#ibcon#read 3, iclass 25, count 0 2006.252.07:34:58.00#ibcon#about to read 4, iclass 25, count 0 2006.252.07:34:58.00#ibcon#read 4, iclass 25, count 0 2006.252.07:34:58.00#ibcon#about to read 5, iclass 25, count 0 2006.252.07:34:58.00#ibcon#read 5, iclass 25, count 0 2006.252.07:34:58.00#ibcon#about to read 6, iclass 25, count 0 2006.252.07:34:58.00#ibcon#read 6, iclass 25, count 0 2006.252.07:34:58.00#ibcon#end of sib2, iclass 25, count 0 2006.252.07:34:58.00#ibcon#*after write, iclass 25, count 0 2006.252.07:34:58.00#ibcon#*before return 0, iclass 25, count 0 2006.252.07:34:58.00#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.252.07:34:58.00#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.252.07:34:58.00#ibcon#about to clear, iclass 25 cls_cnt 0 2006.252.07:34:58.00#ibcon#cleared, iclass 25 cls_cnt 0 2006.252.07:34:58.00$vc4f8/va=1,8 2006.252.07:34:58.00#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.252.07:34:58.00#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.252.07:34:58.00#ibcon#ireg 11 cls_cnt 2 2006.252.07:34:58.00#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.252.07:34:58.00#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.252.07:34:58.00#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.252.07:34:58.00#ibcon#enter wrdev, iclass 27, count 2 2006.252.07:34:58.00#ibcon#first serial, iclass 27, count 2 2006.252.07:34:58.00#ibcon#enter sib2, iclass 27, count 2 2006.252.07:34:58.00#ibcon#flushed, iclass 27, count 2 2006.252.07:34:58.00#ibcon#about to write, iclass 27, count 2 2006.252.07:34:58.00#ibcon#wrote, iclass 27, count 2 2006.252.07:34:58.00#ibcon#about to read 3, iclass 27, count 2 2006.252.07:34:58.02#ibcon#read 3, iclass 27, count 2 2006.252.07:34:58.02#ibcon#about to read 4, iclass 27, count 2 2006.252.07:34:58.02#ibcon#read 4, iclass 27, count 2 2006.252.07:34:58.02#ibcon#about to read 5, iclass 27, count 2 2006.252.07:34:58.02#ibcon#read 5, iclass 27, count 2 2006.252.07:34:58.02#ibcon#about to read 6, iclass 27, count 2 2006.252.07:34:58.02#ibcon#read 6, iclass 27, count 2 2006.252.07:34:58.02#ibcon#end of sib2, iclass 27, count 2 2006.252.07:34:58.02#ibcon#*mode == 0, iclass 27, count 2 2006.252.07:34:58.02#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.252.07:34:58.02#ibcon#[25=AT01-08\r\n] 2006.252.07:34:58.02#ibcon#*before write, iclass 27, count 2 2006.252.07:34:58.02#ibcon#enter sib2, iclass 27, count 2 2006.252.07:34:58.02#ibcon#flushed, iclass 27, count 2 2006.252.07:34:58.02#ibcon#about to write, iclass 27, count 2 2006.252.07:34:58.02#ibcon#wrote, iclass 27, count 2 2006.252.07:34:58.02#ibcon#about to read 3, iclass 27, count 2 2006.252.07:34:58.06#ibcon#read 3, iclass 27, count 2 2006.252.07:34:58.06#ibcon#about to read 4, iclass 27, count 2 2006.252.07:34:58.06#ibcon#read 4, iclass 27, count 2 2006.252.07:34:58.06#ibcon#about to read 5, iclass 27, count 2 2006.252.07:34:58.06#ibcon#read 5, iclass 27, count 2 2006.252.07:34:58.06#ibcon#about to read 6, iclass 27, count 2 2006.252.07:34:58.06#ibcon#read 6, iclass 27, count 2 2006.252.07:34:58.06#ibcon#end of sib2, iclass 27, count 2 2006.252.07:34:58.06#ibcon#*after write, iclass 27, count 2 2006.252.07:34:58.06#ibcon#*before return 0, iclass 27, count 2 2006.252.07:34:58.06#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.252.07:34:58.06#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.252.07:34:58.06#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.252.07:34:58.06#ibcon#ireg 7 cls_cnt 0 2006.252.07:34:58.06#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.252.07:34:58.18#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.252.07:34:58.18#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.252.07:34:58.18#ibcon#enter wrdev, iclass 27, count 0 2006.252.07:34:58.18#ibcon#first serial, iclass 27, count 0 2006.252.07:34:58.18#ibcon#enter sib2, iclass 27, count 0 2006.252.07:34:58.18#ibcon#flushed, iclass 27, count 0 2006.252.07:34:58.18#ibcon#about to write, iclass 27, count 0 2006.252.07:34:58.18#ibcon#wrote, iclass 27, count 0 2006.252.07:34:58.18#ibcon#about to read 3, iclass 27, count 0 2006.252.07:34:58.20#ibcon#read 3, iclass 27, count 0 2006.252.07:34:58.20#ibcon#about to read 4, iclass 27, count 0 2006.252.07:34:58.20#ibcon#read 4, iclass 27, count 0 2006.252.07:34:58.20#ibcon#about to read 5, iclass 27, count 0 2006.252.07:34:58.20#ibcon#read 5, iclass 27, count 0 2006.252.07:34:58.20#ibcon#about to read 6, iclass 27, count 0 2006.252.07:34:58.20#ibcon#read 6, iclass 27, count 0 2006.252.07:34:58.20#ibcon#end of sib2, iclass 27, count 0 2006.252.07:34:58.20#ibcon#*mode == 0, iclass 27, count 0 2006.252.07:34:58.20#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.252.07:34:58.20#ibcon#[25=USB\r\n] 2006.252.07:34:58.20#ibcon#*before write, iclass 27, count 0 2006.252.07:34:58.20#ibcon#enter sib2, iclass 27, count 0 2006.252.07:34:58.20#ibcon#flushed, iclass 27, count 0 2006.252.07:34:58.20#ibcon#about to write, iclass 27, count 0 2006.252.07:34:58.20#ibcon#wrote, iclass 27, count 0 2006.252.07:34:58.20#ibcon#about to read 3, iclass 27, count 0 2006.252.07:34:58.23#ibcon#read 3, iclass 27, count 0 2006.252.07:34:58.23#ibcon#about to read 4, iclass 27, count 0 2006.252.07:34:58.23#ibcon#read 4, iclass 27, count 0 2006.252.07:34:58.23#ibcon#about to read 5, iclass 27, count 0 2006.252.07:34:58.23#ibcon#read 5, iclass 27, count 0 2006.252.07:34:58.23#ibcon#about to read 6, iclass 27, count 0 2006.252.07:34:58.23#ibcon#read 6, iclass 27, count 0 2006.252.07:34:58.23#ibcon#end of sib2, iclass 27, count 0 2006.252.07:34:58.23#ibcon#*after write, iclass 27, count 0 2006.252.07:34:58.23#ibcon#*before return 0, iclass 27, count 0 2006.252.07:34:58.23#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.252.07:34:58.23#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.252.07:34:58.23#ibcon#about to clear, iclass 27 cls_cnt 0 2006.252.07:34:58.23#ibcon#cleared, iclass 27 cls_cnt 0 2006.252.07:34:58.23$vc4f8/valo=2,572.99 2006.252.07:34:58.23#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.252.07:34:58.23#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.252.07:34:58.23#ibcon#ireg 17 cls_cnt 0 2006.252.07:34:58.23#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.252.07:34:58.23#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.252.07:34:58.23#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.252.07:34:58.23#ibcon#enter wrdev, iclass 29, count 0 2006.252.07:34:58.23#ibcon#first serial, iclass 29, count 0 2006.252.07:34:58.23#ibcon#enter sib2, iclass 29, count 0 2006.252.07:34:58.23#ibcon#flushed, iclass 29, count 0 2006.252.07:34:58.23#ibcon#about to write, iclass 29, count 0 2006.252.07:34:58.23#ibcon#wrote, iclass 29, count 0 2006.252.07:34:58.23#ibcon#about to read 3, iclass 29, count 0 2006.252.07:34:58.25#ibcon#read 3, iclass 29, count 0 2006.252.07:34:58.25#ibcon#about to read 4, iclass 29, count 0 2006.252.07:34:58.25#ibcon#read 4, iclass 29, count 0 2006.252.07:34:58.25#ibcon#about to read 5, iclass 29, count 0 2006.252.07:34:58.25#ibcon#read 5, iclass 29, count 0 2006.252.07:34:58.25#ibcon#about to read 6, iclass 29, count 0 2006.252.07:34:58.25#ibcon#read 6, iclass 29, count 0 2006.252.07:34:58.25#ibcon#end of sib2, iclass 29, count 0 2006.252.07:34:58.25#ibcon#*mode == 0, iclass 29, count 0 2006.252.07:34:58.25#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.252.07:34:58.25#ibcon#[26=FRQ=02,572.99\r\n] 2006.252.07:34:58.25#ibcon#*before write, iclass 29, count 0 2006.252.07:34:58.25#ibcon#enter sib2, iclass 29, count 0 2006.252.07:34:58.25#ibcon#flushed, iclass 29, count 0 2006.252.07:34:58.25#ibcon#about to write, iclass 29, count 0 2006.252.07:34:58.25#ibcon#wrote, iclass 29, count 0 2006.252.07:34:58.25#ibcon#about to read 3, iclass 29, count 0 2006.252.07:34:58.29#ibcon#read 3, iclass 29, count 0 2006.252.07:34:58.29#ibcon#about to read 4, iclass 29, count 0 2006.252.07:34:58.29#ibcon#read 4, iclass 29, count 0 2006.252.07:34:58.29#ibcon#about to read 5, iclass 29, count 0 2006.252.07:34:58.29#ibcon#read 5, iclass 29, count 0 2006.252.07:34:58.29#ibcon#about to read 6, iclass 29, count 0 2006.252.07:34:58.29#ibcon#read 6, iclass 29, count 0 2006.252.07:34:58.29#ibcon#end of sib2, iclass 29, count 0 2006.252.07:34:58.29#ibcon#*after write, iclass 29, count 0 2006.252.07:34:58.29#ibcon#*before return 0, iclass 29, count 0 2006.252.07:34:58.29#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.252.07:34:58.29#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.252.07:34:58.29#ibcon#about to clear, iclass 29 cls_cnt 0 2006.252.07:34:58.29#ibcon#cleared, iclass 29 cls_cnt 0 2006.252.07:34:58.29$vc4f8/va=2,7 2006.252.07:34:58.29#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.252.07:34:58.29#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.252.07:34:58.29#ibcon#ireg 11 cls_cnt 2 2006.252.07:34:58.29#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.252.07:34:58.35#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.252.07:34:58.35#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.252.07:34:58.35#ibcon#enter wrdev, iclass 31, count 2 2006.252.07:34:58.35#ibcon#first serial, iclass 31, count 2 2006.252.07:34:58.35#ibcon#enter sib2, iclass 31, count 2 2006.252.07:34:58.35#ibcon#flushed, iclass 31, count 2 2006.252.07:34:58.35#ibcon#about to write, iclass 31, count 2 2006.252.07:34:58.35#ibcon#wrote, iclass 31, count 2 2006.252.07:34:58.35#ibcon#about to read 3, iclass 31, count 2 2006.252.07:34:58.37#ibcon#read 3, iclass 31, count 2 2006.252.07:34:58.37#ibcon#about to read 4, iclass 31, count 2 2006.252.07:34:58.37#ibcon#read 4, iclass 31, count 2 2006.252.07:34:58.37#ibcon#about to read 5, iclass 31, count 2 2006.252.07:34:58.37#ibcon#read 5, iclass 31, count 2 2006.252.07:34:58.37#ibcon#about to read 6, iclass 31, count 2 2006.252.07:34:58.37#ibcon#read 6, iclass 31, count 2 2006.252.07:34:58.37#ibcon#end of sib2, iclass 31, count 2 2006.252.07:34:58.37#ibcon#*mode == 0, iclass 31, count 2 2006.252.07:34:58.37#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.252.07:34:58.37#ibcon#[25=AT02-07\r\n] 2006.252.07:34:58.37#ibcon#*before write, iclass 31, count 2 2006.252.07:34:58.37#ibcon#enter sib2, iclass 31, count 2 2006.252.07:34:58.37#ibcon#flushed, iclass 31, count 2 2006.252.07:34:58.37#ibcon#about to write, iclass 31, count 2 2006.252.07:34:58.37#ibcon#wrote, iclass 31, count 2 2006.252.07:34:58.37#ibcon#about to read 3, iclass 31, count 2 2006.252.07:34:58.40#ibcon#read 3, iclass 31, count 2 2006.252.07:34:58.40#ibcon#about to read 4, iclass 31, count 2 2006.252.07:34:58.40#ibcon#read 4, iclass 31, count 2 2006.252.07:34:58.40#ibcon#about to read 5, iclass 31, count 2 2006.252.07:34:58.40#ibcon#read 5, iclass 31, count 2 2006.252.07:34:58.40#ibcon#about to read 6, iclass 31, count 2 2006.252.07:34:58.40#ibcon#read 6, iclass 31, count 2 2006.252.07:34:58.40#ibcon#end of sib2, iclass 31, count 2 2006.252.07:34:58.40#ibcon#*after write, iclass 31, count 2 2006.252.07:34:58.40#ibcon#*before return 0, iclass 31, count 2 2006.252.07:34:58.40#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.252.07:34:58.40#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.252.07:34:58.40#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.252.07:34:58.40#ibcon#ireg 7 cls_cnt 0 2006.252.07:34:58.40#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.252.07:34:58.52#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.252.07:34:58.52#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.252.07:34:58.52#ibcon#enter wrdev, iclass 31, count 0 2006.252.07:34:58.52#ibcon#first serial, iclass 31, count 0 2006.252.07:34:58.52#ibcon#enter sib2, iclass 31, count 0 2006.252.07:34:58.52#ibcon#flushed, iclass 31, count 0 2006.252.07:34:58.52#ibcon#about to write, iclass 31, count 0 2006.252.07:34:58.52#ibcon#wrote, iclass 31, count 0 2006.252.07:34:58.52#ibcon#about to read 3, iclass 31, count 0 2006.252.07:34:58.54#ibcon#read 3, iclass 31, count 0 2006.252.07:34:58.54#ibcon#about to read 4, iclass 31, count 0 2006.252.07:34:58.54#ibcon#read 4, iclass 31, count 0 2006.252.07:34:58.54#ibcon#about to read 5, iclass 31, count 0 2006.252.07:34:58.54#ibcon#read 5, iclass 31, count 0 2006.252.07:34:58.54#ibcon#about to read 6, iclass 31, count 0 2006.252.07:34:58.54#ibcon#read 6, iclass 31, count 0 2006.252.07:34:58.54#ibcon#end of sib2, iclass 31, count 0 2006.252.07:34:58.54#ibcon#*mode == 0, iclass 31, count 0 2006.252.07:34:58.54#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.252.07:34:58.54#ibcon#[25=USB\r\n] 2006.252.07:34:58.54#ibcon#*before write, iclass 31, count 0 2006.252.07:34:58.54#ibcon#enter sib2, iclass 31, count 0 2006.252.07:34:58.54#ibcon#flushed, iclass 31, count 0 2006.252.07:34:58.54#ibcon#about to write, iclass 31, count 0 2006.252.07:34:58.54#ibcon#wrote, iclass 31, count 0 2006.252.07:34:58.54#ibcon#about to read 3, iclass 31, count 0 2006.252.07:34:58.57#ibcon#read 3, iclass 31, count 0 2006.252.07:34:58.57#ibcon#about to read 4, iclass 31, count 0 2006.252.07:34:58.57#ibcon#read 4, iclass 31, count 0 2006.252.07:34:58.57#ibcon#about to read 5, iclass 31, count 0 2006.252.07:34:58.57#ibcon#read 5, iclass 31, count 0 2006.252.07:34:58.57#ibcon#about to read 6, iclass 31, count 0 2006.252.07:34:58.57#ibcon#read 6, iclass 31, count 0 2006.252.07:34:58.57#ibcon#end of sib2, iclass 31, count 0 2006.252.07:34:58.57#ibcon#*after write, iclass 31, count 0 2006.252.07:34:58.57#ibcon#*before return 0, iclass 31, count 0 2006.252.07:34:58.57#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.252.07:34:58.57#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.252.07:34:58.57#ibcon#about to clear, iclass 31 cls_cnt 0 2006.252.07:34:58.57#ibcon#cleared, iclass 31 cls_cnt 0 2006.252.07:34:58.57$vc4f8/valo=3,672.99 2006.252.07:34:58.57#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.252.07:34:58.57#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.252.07:34:58.57#ibcon#ireg 17 cls_cnt 0 2006.252.07:34:58.57#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.252.07:34:58.57#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.252.07:34:58.57#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.252.07:34:58.57#ibcon#enter wrdev, iclass 33, count 0 2006.252.07:34:58.57#ibcon#first serial, iclass 33, count 0 2006.252.07:34:58.57#ibcon#enter sib2, iclass 33, count 0 2006.252.07:34:58.57#ibcon#flushed, iclass 33, count 0 2006.252.07:34:58.57#ibcon#about to write, iclass 33, count 0 2006.252.07:34:58.57#ibcon#wrote, iclass 33, count 0 2006.252.07:34:58.57#ibcon#about to read 3, iclass 33, count 0 2006.252.07:34:58.59#ibcon#read 3, iclass 33, count 0 2006.252.07:34:58.59#ibcon#about to read 4, iclass 33, count 0 2006.252.07:34:58.59#ibcon#read 4, iclass 33, count 0 2006.252.07:34:58.59#ibcon#about to read 5, iclass 33, count 0 2006.252.07:34:58.59#ibcon#read 5, iclass 33, count 0 2006.252.07:34:58.59#ibcon#about to read 6, iclass 33, count 0 2006.252.07:34:58.59#ibcon#read 6, iclass 33, count 0 2006.252.07:34:58.59#ibcon#end of sib2, iclass 33, count 0 2006.252.07:34:58.59#ibcon#*mode == 0, iclass 33, count 0 2006.252.07:34:58.59#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.252.07:34:58.59#ibcon#[26=FRQ=03,672.99\r\n] 2006.252.07:34:58.59#ibcon#*before write, iclass 33, count 0 2006.252.07:34:58.59#ibcon#enter sib2, iclass 33, count 0 2006.252.07:34:58.59#ibcon#flushed, iclass 33, count 0 2006.252.07:34:58.59#ibcon#about to write, iclass 33, count 0 2006.252.07:34:58.59#ibcon#wrote, iclass 33, count 0 2006.252.07:34:58.59#ibcon#about to read 3, iclass 33, count 0 2006.252.07:34:58.64#ibcon#read 3, iclass 33, count 0 2006.252.07:34:58.64#ibcon#about to read 4, iclass 33, count 0 2006.252.07:34:58.64#ibcon#read 4, iclass 33, count 0 2006.252.07:34:58.64#ibcon#about to read 5, iclass 33, count 0 2006.252.07:34:58.64#ibcon#read 5, iclass 33, count 0 2006.252.07:34:58.64#ibcon#about to read 6, iclass 33, count 0 2006.252.07:34:58.64#ibcon#read 6, iclass 33, count 0 2006.252.07:34:58.64#ibcon#end of sib2, iclass 33, count 0 2006.252.07:34:58.64#ibcon#*after write, iclass 33, count 0 2006.252.07:34:58.64#ibcon#*before return 0, iclass 33, count 0 2006.252.07:34:58.64#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.252.07:34:58.64#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.252.07:34:58.64#ibcon#about to clear, iclass 33 cls_cnt 0 2006.252.07:34:58.64#ibcon#cleared, iclass 33 cls_cnt 0 2006.252.07:34:58.64$vc4f8/va=3,6 2006.252.07:34:58.64#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.252.07:34:58.64#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.252.07:34:58.64#ibcon#ireg 11 cls_cnt 2 2006.252.07:34:58.64#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.252.07:34:58.69#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.252.07:34:58.69#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.252.07:34:58.69#ibcon#enter wrdev, iclass 35, count 2 2006.252.07:34:58.69#ibcon#first serial, iclass 35, count 2 2006.252.07:34:58.69#ibcon#enter sib2, iclass 35, count 2 2006.252.07:34:58.69#ibcon#flushed, iclass 35, count 2 2006.252.07:34:58.69#ibcon#about to write, iclass 35, count 2 2006.252.07:34:58.69#ibcon#wrote, iclass 35, count 2 2006.252.07:34:58.69#ibcon#about to read 3, iclass 35, count 2 2006.252.07:34:58.71#ibcon#read 3, iclass 35, count 2 2006.252.07:34:58.71#ibcon#about to read 4, iclass 35, count 2 2006.252.07:34:58.71#ibcon#read 4, iclass 35, count 2 2006.252.07:34:58.71#ibcon#about to read 5, iclass 35, count 2 2006.252.07:34:58.71#ibcon#read 5, iclass 35, count 2 2006.252.07:34:58.71#ibcon#about to read 6, iclass 35, count 2 2006.252.07:34:58.71#ibcon#read 6, iclass 35, count 2 2006.252.07:34:58.71#ibcon#end of sib2, iclass 35, count 2 2006.252.07:34:58.71#ibcon#*mode == 0, iclass 35, count 2 2006.252.07:34:58.71#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.252.07:34:58.71#ibcon#[25=AT03-06\r\n] 2006.252.07:34:58.71#ibcon#*before write, iclass 35, count 2 2006.252.07:34:58.71#ibcon#enter sib2, iclass 35, count 2 2006.252.07:34:58.71#ibcon#flushed, iclass 35, count 2 2006.252.07:34:58.71#ibcon#about to write, iclass 35, count 2 2006.252.07:34:58.71#ibcon#wrote, iclass 35, count 2 2006.252.07:34:58.71#ibcon#about to read 3, iclass 35, count 2 2006.252.07:34:58.74#ibcon#read 3, iclass 35, count 2 2006.252.07:34:58.74#ibcon#about to read 4, iclass 35, count 2 2006.252.07:34:58.74#ibcon#read 4, iclass 35, count 2 2006.252.07:34:58.74#ibcon#about to read 5, iclass 35, count 2 2006.252.07:34:58.74#ibcon#read 5, iclass 35, count 2 2006.252.07:34:58.74#ibcon#about to read 6, iclass 35, count 2 2006.252.07:34:58.74#ibcon#read 6, iclass 35, count 2 2006.252.07:34:58.74#ibcon#end of sib2, iclass 35, count 2 2006.252.07:34:58.74#ibcon#*after write, iclass 35, count 2 2006.252.07:34:58.74#ibcon#*before return 0, iclass 35, count 2 2006.252.07:34:58.74#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.252.07:34:58.74#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.252.07:34:58.74#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.252.07:34:58.74#ibcon#ireg 7 cls_cnt 0 2006.252.07:34:58.74#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.252.07:34:58.86#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.252.07:34:58.86#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.252.07:34:58.86#ibcon#enter wrdev, iclass 35, count 0 2006.252.07:34:58.86#ibcon#first serial, iclass 35, count 0 2006.252.07:34:58.86#ibcon#enter sib2, iclass 35, count 0 2006.252.07:34:58.86#ibcon#flushed, iclass 35, count 0 2006.252.07:34:58.86#ibcon#about to write, iclass 35, count 0 2006.252.07:34:58.86#ibcon#wrote, iclass 35, count 0 2006.252.07:34:58.86#ibcon#about to read 3, iclass 35, count 0 2006.252.07:34:58.88#ibcon#read 3, iclass 35, count 0 2006.252.07:34:58.88#ibcon#about to read 4, iclass 35, count 0 2006.252.07:34:58.88#ibcon#read 4, iclass 35, count 0 2006.252.07:34:58.88#ibcon#about to read 5, iclass 35, count 0 2006.252.07:34:58.88#ibcon#read 5, iclass 35, count 0 2006.252.07:34:58.88#ibcon#about to read 6, iclass 35, count 0 2006.252.07:34:58.88#ibcon#read 6, iclass 35, count 0 2006.252.07:34:58.88#ibcon#end of sib2, iclass 35, count 0 2006.252.07:34:58.88#ibcon#*mode == 0, iclass 35, count 0 2006.252.07:34:58.88#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.252.07:34:58.88#ibcon#[25=USB\r\n] 2006.252.07:34:58.88#ibcon#*before write, iclass 35, count 0 2006.252.07:34:58.88#ibcon#enter sib2, iclass 35, count 0 2006.252.07:34:58.88#ibcon#flushed, iclass 35, count 0 2006.252.07:34:58.88#ibcon#about to write, iclass 35, count 0 2006.252.07:34:58.88#ibcon#wrote, iclass 35, count 0 2006.252.07:34:58.88#ibcon#about to read 3, iclass 35, count 0 2006.252.07:34:58.91#ibcon#read 3, iclass 35, count 0 2006.252.07:34:58.91#ibcon#about to read 4, iclass 35, count 0 2006.252.07:34:58.91#ibcon#read 4, iclass 35, count 0 2006.252.07:34:58.91#ibcon#about to read 5, iclass 35, count 0 2006.252.07:34:58.91#ibcon#read 5, iclass 35, count 0 2006.252.07:34:58.91#ibcon#about to read 6, iclass 35, count 0 2006.252.07:34:58.91#ibcon#read 6, iclass 35, count 0 2006.252.07:34:58.91#ibcon#end of sib2, iclass 35, count 0 2006.252.07:34:58.91#ibcon#*after write, iclass 35, count 0 2006.252.07:34:58.91#ibcon#*before return 0, iclass 35, count 0 2006.252.07:34:58.91#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.252.07:34:58.91#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.252.07:34:58.91#ibcon#about to clear, iclass 35 cls_cnt 0 2006.252.07:34:58.91#ibcon#cleared, iclass 35 cls_cnt 0 2006.252.07:34:58.91$vc4f8/valo=4,832.99 2006.252.07:34:58.91#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.252.07:34:58.91#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.252.07:34:58.91#ibcon#ireg 17 cls_cnt 0 2006.252.07:34:58.91#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.252.07:34:58.91#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.252.07:34:58.91#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.252.07:34:58.91#ibcon#enter wrdev, iclass 37, count 0 2006.252.07:34:58.91#ibcon#first serial, iclass 37, count 0 2006.252.07:34:58.91#ibcon#enter sib2, iclass 37, count 0 2006.252.07:34:58.91#ibcon#flushed, iclass 37, count 0 2006.252.07:34:58.91#ibcon#about to write, iclass 37, count 0 2006.252.07:34:58.91#ibcon#wrote, iclass 37, count 0 2006.252.07:34:58.91#ibcon#about to read 3, iclass 37, count 0 2006.252.07:34:58.93#ibcon#read 3, iclass 37, count 0 2006.252.07:34:58.93#ibcon#about to read 4, iclass 37, count 0 2006.252.07:34:58.93#ibcon#read 4, iclass 37, count 0 2006.252.07:34:58.93#ibcon#about to read 5, iclass 37, count 0 2006.252.07:34:58.93#ibcon#read 5, iclass 37, count 0 2006.252.07:34:58.93#ibcon#about to read 6, iclass 37, count 0 2006.252.07:34:58.93#ibcon#read 6, iclass 37, count 0 2006.252.07:34:58.93#ibcon#end of sib2, iclass 37, count 0 2006.252.07:34:58.93#ibcon#*mode == 0, iclass 37, count 0 2006.252.07:34:58.93#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.252.07:34:58.93#ibcon#[26=FRQ=04,832.99\r\n] 2006.252.07:34:58.93#ibcon#*before write, iclass 37, count 0 2006.252.07:34:58.93#ibcon#enter sib2, iclass 37, count 0 2006.252.07:34:58.93#ibcon#flushed, iclass 37, count 0 2006.252.07:34:58.93#ibcon#about to write, iclass 37, count 0 2006.252.07:34:58.93#ibcon#wrote, iclass 37, count 0 2006.252.07:34:58.93#ibcon#about to read 3, iclass 37, count 0 2006.252.07:34:58.97#ibcon#read 3, iclass 37, count 0 2006.252.07:34:58.97#ibcon#about to read 4, iclass 37, count 0 2006.252.07:34:58.97#ibcon#read 4, iclass 37, count 0 2006.252.07:34:58.97#ibcon#about to read 5, iclass 37, count 0 2006.252.07:34:58.97#ibcon#read 5, iclass 37, count 0 2006.252.07:34:58.97#ibcon#about to read 6, iclass 37, count 0 2006.252.07:34:58.97#ibcon#read 6, iclass 37, count 0 2006.252.07:34:58.97#ibcon#end of sib2, iclass 37, count 0 2006.252.07:34:58.97#ibcon#*after write, iclass 37, count 0 2006.252.07:34:58.97#ibcon#*before return 0, iclass 37, count 0 2006.252.07:34:58.97#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.252.07:34:58.97#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.252.07:34:58.97#ibcon#about to clear, iclass 37 cls_cnt 0 2006.252.07:34:58.97#ibcon#cleared, iclass 37 cls_cnt 0 2006.252.07:34:58.97$vc4f8/va=4,7 2006.252.07:34:58.97#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.252.07:34:58.97#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.252.07:34:58.97#ibcon#ireg 11 cls_cnt 2 2006.252.07:34:58.97#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.252.07:34:59.03#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.252.07:34:59.03#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.252.07:34:59.03#ibcon#enter wrdev, iclass 39, count 2 2006.252.07:34:59.03#ibcon#first serial, iclass 39, count 2 2006.252.07:34:59.03#ibcon#enter sib2, iclass 39, count 2 2006.252.07:34:59.03#ibcon#flushed, iclass 39, count 2 2006.252.07:34:59.03#ibcon#about to write, iclass 39, count 2 2006.252.07:34:59.03#ibcon#wrote, iclass 39, count 2 2006.252.07:34:59.03#ibcon#about to read 3, iclass 39, count 2 2006.252.07:34:59.05#ibcon#read 3, iclass 39, count 2 2006.252.07:34:59.05#ibcon#about to read 4, iclass 39, count 2 2006.252.07:34:59.05#ibcon#read 4, iclass 39, count 2 2006.252.07:34:59.05#ibcon#about to read 5, iclass 39, count 2 2006.252.07:34:59.05#ibcon#read 5, iclass 39, count 2 2006.252.07:34:59.05#ibcon#about to read 6, iclass 39, count 2 2006.252.07:34:59.05#ibcon#read 6, iclass 39, count 2 2006.252.07:34:59.05#ibcon#end of sib2, iclass 39, count 2 2006.252.07:34:59.05#ibcon#*mode == 0, iclass 39, count 2 2006.252.07:34:59.05#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.252.07:34:59.05#ibcon#[25=AT04-07\r\n] 2006.252.07:34:59.05#ibcon#*before write, iclass 39, count 2 2006.252.07:34:59.05#ibcon#enter sib2, iclass 39, count 2 2006.252.07:34:59.05#ibcon#flushed, iclass 39, count 2 2006.252.07:34:59.05#ibcon#about to write, iclass 39, count 2 2006.252.07:34:59.05#ibcon#wrote, iclass 39, count 2 2006.252.07:34:59.05#ibcon#about to read 3, iclass 39, count 2 2006.252.07:34:59.08#ibcon#read 3, iclass 39, count 2 2006.252.07:34:59.08#ibcon#about to read 4, iclass 39, count 2 2006.252.07:34:59.08#ibcon#read 4, iclass 39, count 2 2006.252.07:34:59.08#ibcon#about to read 5, iclass 39, count 2 2006.252.07:34:59.08#ibcon#read 5, iclass 39, count 2 2006.252.07:34:59.08#ibcon#about to read 6, iclass 39, count 2 2006.252.07:34:59.08#ibcon#read 6, iclass 39, count 2 2006.252.07:34:59.08#ibcon#end of sib2, iclass 39, count 2 2006.252.07:34:59.08#ibcon#*after write, iclass 39, count 2 2006.252.07:34:59.08#ibcon#*before return 0, iclass 39, count 2 2006.252.07:34:59.08#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.252.07:34:59.08#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.252.07:34:59.08#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.252.07:34:59.08#ibcon#ireg 7 cls_cnt 0 2006.252.07:34:59.08#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.252.07:34:59.20#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.252.07:34:59.20#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.252.07:34:59.20#ibcon#enter wrdev, iclass 39, count 0 2006.252.07:34:59.20#ibcon#first serial, iclass 39, count 0 2006.252.07:34:59.20#ibcon#enter sib2, iclass 39, count 0 2006.252.07:34:59.20#ibcon#flushed, iclass 39, count 0 2006.252.07:34:59.20#ibcon#about to write, iclass 39, count 0 2006.252.07:34:59.20#ibcon#wrote, iclass 39, count 0 2006.252.07:34:59.20#ibcon#about to read 3, iclass 39, count 0 2006.252.07:34:59.22#ibcon#read 3, iclass 39, count 0 2006.252.07:34:59.22#ibcon#about to read 4, iclass 39, count 0 2006.252.07:34:59.22#ibcon#read 4, iclass 39, count 0 2006.252.07:34:59.22#ibcon#about to read 5, iclass 39, count 0 2006.252.07:34:59.22#ibcon#read 5, iclass 39, count 0 2006.252.07:34:59.22#ibcon#about to read 6, iclass 39, count 0 2006.252.07:34:59.22#ibcon#read 6, iclass 39, count 0 2006.252.07:34:59.22#ibcon#end of sib2, iclass 39, count 0 2006.252.07:34:59.22#ibcon#*mode == 0, iclass 39, count 0 2006.252.07:34:59.22#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.252.07:34:59.22#ibcon#[25=USB\r\n] 2006.252.07:34:59.22#ibcon#*before write, iclass 39, count 0 2006.252.07:34:59.22#ibcon#enter sib2, iclass 39, count 0 2006.252.07:34:59.22#ibcon#flushed, iclass 39, count 0 2006.252.07:34:59.22#ibcon#about to write, iclass 39, count 0 2006.252.07:34:59.22#ibcon#wrote, iclass 39, count 0 2006.252.07:34:59.22#ibcon#about to read 3, iclass 39, count 0 2006.252.07:34:59.25#ibcon#read 3, iclass 39, count 0 2006.252.07:34:59.25#ibcon#about to read 4, iclass 39, count 0 2006.252.07:34:59.25#ibcon#read 4, iclass 39, count 0 2006.252.07:34:59.25#ibcon#about to read 5, iclass 39, count 0 2006.252.07:34:59.25#ibcon#read 5, iclass 39, count 0 2006.252.07:34:59.25#ibcon#about to read 6, iclass 39, count 0 2006.252.07:34:59.25#ibcon#read 6, iclass 39, count 0 2006.252.07:34:59.25#ibcon#end of sib2, iclass 39, count 0 2006.252.07:34:59.25#ibcon#*after write, iclass 39, count 0 2006.252.07:34:59.25#ibcon#*before return 0, iclass 39, count 0 2006.252.07:34:59.25#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.252.07:34:59.25#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.252.07:34:59.25#ibcon#about to clear, iclass 39 cls_cnt 0 2006.252.07:34:59.25#ibcon#cleared, iclass 39 cls_cnt 0 2006.252.07:34:59.25$vc4f8/valo=5,652.99 2006.252.07:34:59.25#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.252.07:34:59.25#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.252.07:34:59.25#ibcon#ireg 17 cls_cnt 0 2006.252.07:34:59.25#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.252.07:34:59.25#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.252.07:34:59.25#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.252.07:34:59.25#ibcon#enter wrdev, iclass 3, count 0 2006.252.07:34:59.25#ibcon#first serial, iclass 3, count 0 2006.252.07:34:59.25#ibcon#enter sib2, iclass 3, count 0 2006.252.07:34:59.25#ibcon#flushed, iclass 3, count 0 2006.252.07:34:59.25#ibcon#about to write, iclass 3, count 0 2006.252.07:34:59.25#ibcon#wrote, iclass 3, count 0 2006.252.07:34:59.25#ibcon#about to read 3, iclass 3, count 0 2006.252.07:34:59.27#ibcon#read 3, iclass 3, count 0 2006.252.07:34:59.27#ibcon#about to read 4, iclass 3, count 0 2006.252.07:34:59.27#ibcon#read 4, iclass 3, count 0 2006.252.07:34:59.27#ibcon#about to read 5, iclass 3, count 0 2006.252.07:34:59.27#ibcon#read 5, iclass 3, count 0 2006.252.07:34:59.27#ibcon#about to read 6, iclass 3, count 0 2006.252.07:34:59.27#ibcon#read 6, iclass 3, count 0 2006.252.07:34:59.27#ibcon#end of sib2, iclass 3, count 0 2006.252.07:34:59.27#ibcon#*mode == 0, iclass 3, count 0 2006.252.07:34:59.27#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.252.07:34:59.27#ibcon#[26=FRQ=05,652.99\r\n] 2006.252.07:34:59.27#ibcon#*before write, iclass 3, count 0 2006.252.07:34:59.27#ibcon#enter sib2, iclass 3, count 0 2006.252.07:34:59.27#ibcon#flushed, iclass 3, count 0 2006.252.07:34:59.27#ibcon#about to write, iclass 3, count 0 2006.252.07:34:59.27#ibcon#wrote, iclass 3, count 0 2006.252.07:34:59.27#ibcon#about to read 3, iclass 3, count 0 2006.252.07:34:59.31#ibcon#read 3, iclass 3, count 0 2006.252.07:34:59.31#ibcon#about to read 4, iclass 3, count 0 2006.252.07:34:59.31#ibcon#read 4, iclass 3, count 0 2006.252.07:34:59.31#ibcon#about to read 5, iclass 3, count 0 2006.252.07:34:59.31#ibcon#read 5, iclass 3, count 0 2006.252.07:34:59.31#ibcon#about to read 6, iclass 3, count 0 2006.252.07:34:59.31#ibcon#read 6, iclass 3, count 0 2006.252.07:34:59.31#ibcon#end of sib2, iclass 3, count 0 2006.252.07:34:59.31#ibcon#*after write, iclass 3, count 0 2006.252.07:34:59.31#ibcon#*before return 0, iclass 3, count 0 2006.252.07:34:59.31#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.252.07:34:59.31#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.252.07:34:59.31#ibcon#about to clear, iclass 3 cls_cnt 0 2006.252.07:34:59.31#ibcon#cleared, iclass 3 cls_cnt 0 2006.252.07:34:59.31$vc4f8/va=5,7 2006.252.07:34:59.31#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.252.07:34:59.31#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.252.07:34:59.31#ibcon#ireg 11 cls_cnt 2 2006.252.07:34:59.31#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.252.07:34:59.37#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.252.07:34:59.37#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.252.07:34:59.37#ibcon#enter wrdev, iclass 5, count 2 2006.252.07:34:59.37#ibcon#first serial, iclass 5, count 2 2006.252.07:34:59.37#ibcon#enter sib2, iclass 5, count 2 2006.252.07:34:59.37#ibcon#flushed, iclass 5, count 2 2006.252.07:34:59.37#ibcon#about to write, iclass 5, count 2 2006.252.07:34:59.37#ibcon#wrote, iclass 5, count 2 2006.252.07:34:59.37#ibcon#about to read 3, iclass 5, count 2 2006.252.07:34:59.39#ibcon#read 3, iclass 5, count 2 2006.252.07:34:59.39#ibcon#about to read 4, iclass 5, count 2 2006.252.07:34:59.39#ibcon#read 4, iclass 5, count 2 2006.252.07:34:59.39#ibcon#about to read 5, iclass 5, count 2 2006.252.07:34:59.39#ibcon#read 5, iclass 5, count 2 2006.252.07:34:59.39#ibcon#about to read 6, iclass 5, count 2 2006.252.07:34:59.39#ibcon#read 6, iclass 5, count 2 2006.252.07:34:59.39#ibcon#end of sib2, iclass 5, count 2 2006.252.07:34:59.39#ibcon#*mode == 0, iclass 5, count 2 2006.252.07:34:59.39#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.252.07:34:59.39#ibcon#[25=AT05-07\r\n] 2006.252.07:34:59.39#ibcon#*before write, iclass 5, count 2 2006.252.07:34:59.39#ibcon#enter sib2, iclass 5, count 2 2006.252.07:34:59.39#ibcon#flushed, iclass 5, count 2 2006.252.07:34:59.39#ibcon#about to write, iclass 5, count 2 2006.252.07:34:59.39#ibcon#wrote, iclass 5, count 2 2006.252.07:34:59.39#ibcon#about to read 3, iclass 5, count 2 2006.252.07:34:59.42#ibcon#read 3, iclass 5, count 2 2006.252.07:34:59.42#ibcon#about to read 4, iclass 5, count 2 2006.252.07:34:59.42#ibcon#read 4, iclass 5, count 2 2006.252.07:34:59.42#ibcon#about to read 5, iclass 5, count 2 2006.252.07:34:59.42#ibcon#read 5, iclass 5, count 2 2006.252.07:34:59.42#ibcon#about to read 6, iclass 5, count 2 2006.252.07:34:59.42#ibcon#read 6, iclass 5, count 2 2006.252.07:34:59.42#ibcon#end of sib2, iclass 5, count 2 2006.252.07:34:59.42#ibcon#*after write, iclass 5, count 2 2006.252.07:34:59.42#ibcon#*before return 0, iclass 5, count 2 2006.252.07:34:59.42#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.252.07:34:59.42#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.252.07:34:59.42#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.252.07:34:59.42#ibcon#ireg 7 cls_cnt 0 2006.252.07:34:59.42#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.252.07:34:59.54#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.252.07:34:59.54#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.252.07:34:59.54#ibcon#enter wrdev, iclass 5, count 0 2006.252.07:34:59.54#ibcon#first serial, iclass 5, count 0 2006.252.07:34:59.54#ibcon#enter sib2, iclass 5, count 0 2006.252.07:34:59.54#ibcon#flushed, iclass 5, count 0 2006.252.07:34:59.54#ibcon#about to write, iclass 5, count 0 2006.252.07:34:59.54#ibcon#wrote, iclass 5, count 0 2006.252.07:34:59.54#ibcon#about to read 3, iclass 5, count 0 2006.252.07:34:59.56#ibcon#read 3, iclass 5, count 0 2006.252.07:34:59.56#ibcon#about to read 4, iclass 5, count 0 2006.252.07:34:59.56#ibcon#read 4, iclass 5, count 0 2006.252.07:34:59.56#ibcon#about to read 5, iclass 5, count 0 2006.252.07:34:59.56#ibcon#read 5, iclass 5, count 0 2006.252.07:34:59.56#ibcon#about to read 6, iclass 5, count 0 2006.252.07:34:59.56#ibcon#read 6, iclass 5, count 0 2006.252.07:34:59.56#ibcon#end of sib2, iclass 5, count 0 2006.252.07:34:59.56#ibcon#*mode == 0, iclass 5, count 0 2006.252.07:34:59.56#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.252.07:34:59.56#ibcon#[25=USB\r\n] 2006.252.07:34:59.56#ibcon#*before write, iclass 5, count 0 2006.252.07:34:59.56#ibcon#enter sib2, iclass 5, count 0 2006.252.07:34:59.56#ibcon#flushed, iclass 5, count 0 2006.252.07:34:59.56#ibcon#about to write, iclass 5, count 0 2006.252.07:34:59.56#ibcon#wrote, iclass 5, count 0 2006.252.07:34:59.56#ibcon#about to read 3, iclass 5, count 0 2006.252.07:34:59.59#ibcon#read 3, iclass 5, count 0 2006.252.07:34:59.59#ibcon#about to read 4, iclass 5, count 0 2006.252.07:34:59.59#ibcon#read 4, iclass 5, count 0 2006.252.07:34:59.59#ibcon#about to read 5, iclass 5, count 0 2006.252.07:34:59.59#ibcon#read 5, iclass 5, count 0 2006.252.07:34:59.59#ibcon#about to read 6, iclass 5, count 0 2006.252.07:34:59.59#ibcon#read 6, iclass 5, count 0 2006.252.07:34:59.59#ibcon#end of sib2, iclass 5, count 0 2006.252.07:34:59.59#ibcon#*after write, iclass 5, count 0 2006.252.07:34:59.59#ibcon#*before return 0, iclass 5, count 0 2006.252.07:34:59.59#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.252.07:34:59.59#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.252.07:34:59.59#ibcon#about to clear, iclass 5 cls_cnt 0 2006.252.07:34:59.59#ibcon#cleared, iclass 5 cls_cnt 0 2006.252.07:34:59.59$vc4f8/valo=6,772.99 2006.252.07:34:59.59#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.252.07:34:59.59#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.252.07:34:59.59#ibcon#ireg 17 cls_cnt 0 2006.252.07:34:59.59#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.252.07:34:59.59#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.252.07:34:59.59#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.252.07:34:59.59#ibcon#enter wrdev, iclass 7, count 0 2006.252.07:34:59.59#ibcon#first serial, iclass 7, count 0 2006.252.07:34:59.59#ibcon#enter sib2, iclass 7, count 0 2006.252.07:34:59.59#ibcon#flushed, iclass 7, count 0 2006.252.07:34:59.59#ibcon#about to write, iclass 7, count 0 2006.252.07:34:59.59#ibcon#wrote, iclass 7, count 0 2006.252.07:34:59.59#ibcon#about to read 3, iclass 7, count 0 2006.252.07:34:59.61#ibcon#read 3, iclass 7, count 0 2006.252.07:34:59.61#ibcon#about to read 4, iclass 7, count 0 2006.252.07:34:59.61#ibcon#read 4, iclass 7, count 0 2006.252.07:34:59.61#ibcon#about to read 5, iclass 7, count 0 2006.252.07:34:59.61#ibcon#read 5, iclass 7, count 0 2006.252.07:34:59.61#ibcon#about to read 6, iclass 7, count 0 2006.252.07:34:59.61#ibcon#read 6, iclass 7, count 0 2006.252.07:34:59.61#ibcon#end of sib2, iclass 7, count 0 2006.252.07:34:59.61#ibcon#*mode == 0, iclass 7, count 0 2006.252.07:34:59.61#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.252.07:34:59.61#ibcon#[26=FRQ=06,772.99\r\n] 2006.252.07:34:59.61#ibcon#*before write, iclass 7, count 0 2006.252.07:34:59.61#ibcon#enter sib2, iclass 7, count 0 2006.252.07:34:59.61#ibcon#flushed, iclass 7, count 0 2006.252.07:34:59.61#ibcon#about to write, iclass 7, count 0 2006.252.07:34:59.61#ibcon#wrote, iclass 7, count 0 2006.252.07:34:59.61#ibcon#about to read 3, iclass 7, count 0 2006.252.07:34:59.65#ibcon#read 3, iclass 7, count 0 2006.252.07:34:59.65#ibcon#about to read 4, iclass 7, count 0 2006.252.07:34:59.65#ibcon#read 4, iclass 7, count 0 2006.252.07:34:59.65#ibcon#about to read 5, iclass 7, count 0 2006.252.07:34:59.65#ibcon#read 5, iclass 7, count 0 2006.252.07:34:59.65#ibcon#about to read 6, iclass 7, count 0 2006.252.07:34:59.65#ibcon#read 6, iclass 7, count 0 2006.252.07:34:59.65#ibcon#end of sib2, iclass 7, count 0 2006.252.07:34:59.65#ibcon#*after write, iclass 7, count 0 2006.252.07:34:59.65#ibcon#*before return 0, iclass 7, count 0 2006.252.07:34:59.65#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.252.07:34:59.65#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.252.07:34:59.65#ibcon#about to clear, iclass 7 cls_cnt 0 2006.252.07:34:59.65#ibcon#cleared, iclass 7 cls_cnt 0 2006.252.07:34:59.65$vc4f8/va=6,7 2006.252.07:34:59.65#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.252.07:34:59.65#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.252.07:34:59.65#ibcon#ireg 11 cls_cnt 2 2006.252.07:34:59.65#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.252.07:34:59.71#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.252.07:34:59.71#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.252.07:34:59.71#ibcon#enter wrdev, iclass 11, count 2 2006.252.07:34:59.71#ibcon#first serial, iclass 11, count 2 2006.252.07:34:59.71#ibcon#enter sib2, iclass 11, count 2 2006.252.07:34:59.71#ibcon#flushed, iclass 11, count 2 2006.252.07:34:59.71#ibcon#about to write, iclass 11, count 2 2006.252.07:34:59.71#ibcon#wrote, iclass 11, count 2 2006.252.07:34:59.71#ibcon#about to read 3, iclass 11, count 2 2006.252.07:34:59.73#ibcon#read 3, iclass 11, count 2 2006.252.07:34:59.73#ibcon#about to read 4, iclass 11, count 2 2006.252.07:34:59.73#ibcon#read 4, iclass 11, count 2 2006.252.07:34:59.73#ibcon#about to read 5, iclass 11, count 2 2006.252.07:34:59.73#ibcon#read 5, iclass 11, count 2 2006.252.07:34:59.73#ibcon#about to read 6, iclass 11, count 2 2006.252.07:34:59.73#ibcon#read 6, iclass 11, count 2 2006.252.07:34:59.73#ibcon#end of sib2, iclass 11, count 2 2006.252.07:34:59.73#ibcon#*mode == 0, iclass 11, count 2 2006.252.07:34:59.73#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.252.07:34:59.73#ibcon#[25=AT06-07\r\n] 2006.252.07:34:59.73#ibcon#*before write, iclass 11, count 2 2006.252.07:34:59.73#ibcon#enter sib2, iclass 11, count 2 2006.252.07:34:59.73#ibcon#flushed, iclass 11, count 2 2006.252.07:34:59.73#ibcon#about to write, iclass 11, count 2 2006.252.07:34:59.73#ibcon#wrote, iclass 11, count 2 2006.252.07:34:59.73#ibcon#about to read 3, iclass 11, count 2 2006.252.07:34:59.76#ibcon#read 3, iclass 11, count 2 2006.252.07:34:59.76#ibcon#about to read 4, iclass 11, count 2 2006.252.07:34:59.76#ibcon#read 4, iclass 11, count 2 2006.252.07:34:59.76#ibcon#about to read 5, iclass 11, count 2 2006.252.07:34:59.76#ibcon#read 5, iclass 11, count 2 2006.252.07:34:59.76#ibcon#about to read 6, iclass 11, count 2 2006.252.07:34:59.76#ibcon#read 6, iclass 11, count 2 2006.252.07:34:59.76#ibcon#end of sib2, iclass 11, count 2 2006.252.07:34:59.76#ibcon#*after write, iclass 11, count 2 2006.252.07:34:59.76#ibcon#*before return 0, iclass 11, count 2 2006.252.07:34:59.76#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.252.07:34:59.76#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.252.07:34:59.76#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.252.07:34:59.76#ibcon#ireg 7 cls_cnt 0 2006.252.07:34:59.76#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.252.07:34:59.88#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.252.07:34:59.88#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.252.07:34:59.88#ibcon#enter wrdev, iclass 11, count 0 2006.252.07:34:59.88#ibcon#first serial, iclass 11, count 0 2006.252.07:34:59.88#ibcon#enter sib2, iclass 11, count 0 2006.252.07:34:59.88#ibcon#flushed, iclass 11, count 0 2006.252.07:34:59.88#ibcon#about to write, iclass 11, count 0 2006.252.07:34:59.88#ibcon#wrote, iclass 11, count 0 2006.252.07:34:59.88#ibcon#about to read 3, iclass 11, count 0 2006.252.07:34:59.90#ibcon#read 3, iclass 11, count 0 2006.252.07:34:59.90#ibcon#about to read 4, iclass 11, count 0 2006.252.07:34:59.90#ibcon#read 4, iclass 11, count 0 2006.252.07:34:59.90#ibcon#about to read 5, iclass 11, count 0 2006.252.07:34:59.90#ibcon#read 5, iclass 11, count 0 2006.252.07:34:59.90#ibcon#about to read 6, iclass 11, count 0 2006.252.07:34:59.90#ibcon#read 6, iclass 11, count 0 2006.252.07:34:59.90#ibcon#end of sib2, iclass 11, count 0 2006.252.07:34:59.90#ibcon#*mode == 0, iclass 11, count 0 2006.252.07:34:59.90#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.252.07:34:59.90#ibcon#[25=USB\r\n] 2006.252.07:34:59.90#ibcon#*before write, iclass 11, count 0 2006.252.07:34:59.90#ibcon#enter sib2, iclass 11, count 0 2006.252.07:34:59.90#ibcon#flushed, iclass 11, count 0 2006.252.07:34:59.90#ibcon#about to write, iclass 11, count 0 2006.252.07:34:59.90#ibcon#wrote, iclass 11, count 0 2006.252.07:34:59.90#ibcon#about to read 3, iclass 11, count 0 2006.252.07:34:59.93#ibcon#read 3, iclass 11, count 0 2006.252.07:34:59.93#ibcon#about to read 4, iclass 11, count 0 2006.252.07:34:59.93#ibcon#read 4, iclass 11, count 0 2006.252.07:34:59.93#ibcon#about to read 5, iclass 11, count 0 2006.252.07:34:59.93#ibcon#read 5, iclass 11, count 0 2006.252.07:34:59.93#ibcon#about to read 6, iclass 11, count 0 2006.252.07:34:59.93#ibcon#read 6, iclass 11, count 0 2006.252.07:34:59.93#ibcon#end of sib2, iclass 11, count 0 2006.252.07:34:59.93#ibcon#*after write, iclass 11, count 0 2006.252.07:34:59.93#ibcon#*before return 0, iclass 11, count 0 2006.252.07:34:59.93#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.252.07:34:59.93#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.252.07:34:59.93#ibcon#about to clear, iclass 11 cls_cnt 0 2006.252.07:34:59.93#ibcon#cleared, iclass 11 cls_cnt 0 2006.252.07:34:59.93$vc4f8/valo=7,832.99 2006.252.07:34:59.93#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.252.07:34:59.93#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.252.07:34:59.93#ibcon#ireg 17 cls_cnt 0 2006.252.07:34:59.93#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.252.07:34:59.93#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.252.07:34:59.93#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.252.07:34:59.93#ibcon#enter wrdev, iclass 13, count 0 2006.252.07:34:59.93#ibcon#first serial, iclass 13, count 0 2006.252.07:34:59.93#ibcon#enter sib2, iclass 13, count 0 2006.252.07:34:59.93#ibcon#flushed, iclass 13, count 0 2006.252.07:34:59.93#ibcon#about to write, iclass 13, count 0 2006.252.07:34:59.93#ibcon#wrote, iclass 13, count 0 2006.252.07:34:59.93#ibcon#about to read 3, iclass 13, count 0 2006.252.07:34:59.95#ibcon#read 3, iclass 13, count 0 2006.252.07:34:59.95#ibcon#about to read 4, iclass 13, count 0 2006.252.07:34:59.95#ibcon#read 4, iclass 13, count 0 2006.252.07:34:59.95#ibcon#about to read 5, iclass 13, count 0 2006.252.07:34:59.95#ibcon#read 5, iclass 13, count 0 2006.252.07:34:59.95#ibcon#about to read 6, iclass 13, count 0 2006.252.07:34:59.95#ibcon#read 6, iclass 13, count 0 2006.252.07:34:59.95#ibcon#end of sib2, iclass 13, count 0 2006.252.07:34:59.95#ibcon#*mode == 0, iclass 13, count 0 2006.252.07:34:59.95#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.252.07:34:59.95#ibcon#[26=FRQ=07,832.99\r\n] 2006.252.07:34:59.95#ibcon#*before write, iclass 13, count 0 2006.252.07:34:59.95#ibcon#enter sib2, iclass 13, count 0 2006.252.07:34:59.95#ibcon#flushed, iclass 13, count 0 2006.252.07:34:59.95#ibcon#about to write, iclass 13, count 0 2006.252.07:34:59.95#ibcon#wrote, iclass 13, count 0 2006.252.07:34:59.95#ibcon#about to read 3, iclass 13, count 0 2006.252.07:34:59.99#ibcon#read 3, iclass 13, count 0 2006.252.07:34:59.99#ibcon#about to read 4, iclass 13, count 0 2006.252.07:34:59.99#ibcon#read 4, iclass 13, count 0 2006.252.07:34:59.99#ibcon#about to read 5, iclass 13, count 0 2006.252.07:34:59.99#ibcon#read 5, iclass 13, count 0 2006.252.07:34:59.99#ibcon#about to read 6, iclass 13, count 0 2006.252.07:34:59.99#ibcon#read 6, iclass 13, count 0 2006.252.07:34:59.99#ibcon#end of sib2, iclass 13, count 0 2006.252.07:34:59.99#ibcon#*after write, iclass 13, count 0 2006.252.07:34:59.99#ibcon#*before return 0, iclass 13, count 0 2006.252.07:34:59.99#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.252.07:34:59.99#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.252.07:34:59.99#ibcon#about to clear, iclass 13 cls_cnt 0 2006.252.07:34:59.99#ibcon#cleared, iclass 13 cls_cnt 0 2006.252.07:34:59.99$vc4f8/va=7,7 2006.252.07:34:59.99#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.252.07:34:59.99#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.252.07:34:59.99#ibcon#ireg 11 cls_cnt 2 2006.252.07:34:59.99#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.252.07:35:00.05#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.252.07:35:00.05#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.252.07:35:00.05#ibcon#enter wrdev, iclass 15, count 2 2006.252.07:35:00.05#ibcon#first serial, iclass 15, count 2 2006.252.07:35:00.05#ibcon#enter sib2, iclass 15, count 2 2006.252.07:35:00.05#ibcon#flushed, iclass 15, count 2 2006.252.07:35:00.05#ibcon#about to write, iclass 15, count 2 2006.252.07:35:00.05#ibcon#wrote, iclass 15, count 2 2006.252.07:35:00.05#ibcon#about to read 3, iclass 15, count 2 2006.252.07:35:00.07#ibcon#read 3, iclass 15, count 2 2006.252.07:35:00.07#ibcon#about to read 4, iclass 15, count 2 2006.252.07:35:00.07#ibcon#read 4, iclass 15, count 2 2006.252.07:35:00.07#ibcon#about to read 5, iclass 15, count 2 2006.252.07:35:00.07#ibcon#read 5, iclass 15, count 2 2006.252.07:35:00.07#ibcon#about to read 6, iclass 15, count 2 2006.252.07:35:00.07#ibcon#read 6, iclass 15, count 2 2006.252.07:35:00.07#ibcon#end of sib2, iclass 15, count 2 2006.252.07:35:00.07#ibcon#*mode == 0, iclass 15, count 2 2006.252.07:35:00.07#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.252.07:35:00.07#ibcon#[25=AT07-07\r\n] 2006.252.07:35:00.07#ibcon#*before write, iclass 15, count 2 2006.252.07:35:00.07#ibcon#enter sib2, iclass 15, count 2 2006.252.07:35:00.07#ibcon#flushed, iclass 15, count 2 2006.252.07:35:00.07#ibcon#about to write, iclass 15, count 2 2006.252.07:35:00.07#ibcon#wrote, iclass 15, count 2 2006.252.07:35:00.07#ibcon#about to read 3, iclass 15, count 2 2006.252.07:35:00.10#ibcon#read 3, iclass 15, count 2 2006.252.07:35:00.10#ibcon#about to read 4, iclass 15, count 2 2006.252.07:35:00.10#ibcon#read 4, iclass 15, count 2 2006.252.07:35:00.10#ibcon#about to read 5, iclass 15, count 2 2006.252.07:35:00.10#ibcon#read 5, iclass 15, count 2 2006.252.07:35:00.10#ibcon#about to read 6, iclass 15, count 2 2006.252.07:35:00.10#ibcon#read 6, iclass 15, count 2 2006.252.07:35:00.10#ibcon#end of sib2, iclass 15, count 2 2006.252.07:35:00.10#ibcon#*after write, iclass 15, count 2 2006.252.07:35:00.10#ibcon#*before return 0, iclass 15, count 2 2006.252.07:35:00.10#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.252.07:35:00.10#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.252.07:35:00.10#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.252.07:35:00.10#ibcon#ireg 7 cls_cnt 0 2006.252.07:35:00.10#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.252.07:35:00.22#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.252.07:35:00.22#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.252.07:35:00.22#ibcon#enter wrdev, iclass 15, count 0 2006.252.07:35:00.22#ibcon#first serial, iclass 15, count 0 2006.252.07:35:00.22#ibcon#enter sib2, iclass 15, count 0 2006.252.07:35:00.22#ibcon#flushed, iclass 15, count 0 2006.252.07:35:00.22#ibcon#about to write, iclass 15, count 0 2006.252.07:35:00.22#ibcon#wrote, iclass 15, count 0 2006.252.07:35:00.22#ibcon#about to read 3, iclass 15, count 0 2006.252.07:35:00.24#ibcon#read 3, iclass 15, count 0 2006.252.07:35:00.24#ibcon#about to read 4, iclass 15, count 0 2006.252.07:35:00.24#ibcon#read 4, iclass 15, count 0 2006.252.07:35:00.24#ibcon#about to read 5, iclass 15, count 0 2006.252.07:35:00.24#ibcon#read 5, iclass 15, count 0 2006.252.07:35:00.24#ibcon#about to read 6, iclass 15, count 0 2006.252.07:35:00.24#ibcon#read 6, iclass 15, count 0 2006.252.07:35:00.24#ibcon#end of sib2, iclass 15, count 0 2006.252.07:35:00.24#ibcon#*mode == 0, iclass 15, count 0 2006.252.07:35:00.24#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.252.07:35:00.24#ibcon#[25=USB\r\n] 2006.252.07:35:00.24#ibcon#*before write, iclass 15, count 0 2006.252.07:35:00.24#ibcon#enter sib2, iclass 15, count 0 2006.252.07:35:00.24#ibcon#flushed, iclass 15, count 0 2006.252.07:35:00.24#ibcon#about to write, iclass 15, count 0 2006.252.07:35:00.24#ibcon#wrote, iclass 15, count 0 2006.252.07:35:00.24#ibcon#about to read 3, iclass 15, count 0 2006.252.07:35:00.27#ibcon#read 3, iclass 15, count 0 2006.252.07:35:00.27#ibcon#about to read 4, iclass 15, count 0 2006.252.07:35:00.27#ibcon#read 4, iclass 15, count 0 2006.252.07:35:00.27#ibcon#about to read 5, iclass 15, count 0 2006.252.07:35:00.27#ibcon#read 5, iclass 15, count 0 2006.252.07:35:00.27#ibcon#about to read 6, iclass 15, count 0 2006.252.07:35:00.27#ibcon#read 6, iclass 15, count 0 2006.252.07:35:00.27#ibcon#end of sib2, iclass 15, count 0 2006.252.07:35:00.27#ibcon#*after write, iclass 15, count 0 2006.252.07:35:00.27#ibcon#*before return 0, iclass 15, count 0 2006.252.07:35:00.27#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.252.07:35:00.27#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.252.07:35:00.27#ibcon#about to clear, iclass 15 cls_cnt 0 2006.252.07:35:00.27#ibcon#cleared, iclass 15 cls_cnt 0 2006.252.07:35:00.27$vc4f8/valo=8,852.99 2006.252.07:35:00.27#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.252.07:35:00.27#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.252.07:35:00.27#ibcon#ireg 17 cls_cnt 0 2006.252.07:35:00.27#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.252.07:35:00.27#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.252.07:35:00.27#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.252.07:35:00.27#ibcon#enter wrdev, iclass 17, count 0 2006.252.07:35:00.27#ibcon#first serial, iclass 17, count 0 2006.252.07:35:00.27#ibcon#enter sib2, iclass 17, count 0 2006.252.07:35:00.27#ibcon#flushed, iclass 17, count 0 2006.252.07:35:00.27#ibcon#about to write, iclass 17, count 0 2006.252.07:35:00.27#ibcon#wrote, iclass 17, count 0 2006.252.07:35:00.27#ibcon#about to read 3, iclass 17, count 0 2006.252.07:35:00.29#ibcon#read 3, iclass 17, count 0 2006.252.07:35:00.29#ibcon#about to read 4, iclass 17, count 0 2006.252.07:35:00.29#ibcon#read 4, iclass 17, count 0 2006.252.07:35:00.29#ibcon#about to read 5, iclass 17, count 0 2006.252.07:35:00.29#ibcon#read 5, iclass 17, count 0 2006.252.07:35:00.29#ibcon#about to read 6, iclass 17, count 0 2006.252.07:35:00.29#ibcon#read 6, iclass 17, count 0 2006.252.07:35:00.29#ibcon#end of sib2, iclass 17, count 0 2006.252.07:35:00.29#ibcon#*mode == 0, iclass 17, count 0 2006.252.07:35:00.29#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.252.07:35:00.29#ibcon#[26=FRQ=08,852.99\r\n] 2006.252.07:35:00.29#ibcon#*before write, iclass 17, count 0 2006.252.07:35:00.29#ibcon#enter sib2, iclass 17, count 0 2006.252.07:35:00.29#ibcon#flushed, iclass 17, count 0 2006.252.07:35:00.29#ibcon#about to write, iclass 17, count 0 2006.252.07:35:00.29#ibcon#wrote, iclass 17, count 0 2006.252.07:35:00.29#ibcon#about to read 3, iclass 17, count 0 2006.252.07:35:00.33#ibcon#read 3, iclass 17, count 0 2006.252.07:35:00.33#ibcon#about to read 4, iclass 17, count 0 2006.252.07:35:00.33#ibcon#read 4, iclass 17, count 0 2006.252.07:35:00.33#ibcon#about to read 5, iclass 17, count 0 2006.252.07:35:00.33#ibcon#read 5, iclass 17, count 0 2006.252.07:35:00.33#ibcon#about to read 6, iclass 17, count 0 2006.252.07:35:00.33#ibcon#read 6, iclass 17, count 0 2006.252.07:35:00.33#ibcon#end of sib2, iclass 17, count 0 2006.252.07:35:00.33#ibcon#*after write, iclass 17, count 0 2006.252.07:35:00.33#ibcon#*before return 0, iclass 17, count 0 2006.252.07:35:00.33#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.252.07:35:00.33#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.252.07:35:00.33#ibcon#about to clear, iclass 17 cls_cnt 0 2006.252.07:35:00.33#ibcon#cleared, iclass 17 cls_cnt 0 2006.252.07:35:00.33$vc4f8/va=8,7 2006.252.07:35:00.33#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.252.07:35:00.33#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.252.07:35:00.33#ibcon#ireg 11 cls_cnt 2 2006.252.07:35:00.33#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.252.07:35:00.39#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.252.07:35:00.39#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.252.07:35:00.39#ibcon#enter wrdev, iclass 19, count 2 2006.252.07:35:00.39#ibcon#first serial, iclass 19, count 2 2006.252.07:35:00.39#ibcon#enter sib2, iclass 19, count 2 2006.252.07:35:00.39#ibcon#flushed, iclass 19, count 2 2006.252.07:35:00.39#ibcon#about to write, iclass 19, count 2 2006.252.07:35:00.39#ibcon#wrote, iclass 19, count 2 2006.252.07:35:00.39#ibcon#about to read 3, iclass 19, count 2 2006.252.07:35:00.41#ibcon#read 3, iclass 19, count 2 2006.252.07:35:00.41#ibcon#about to read 4, iclass 19, count 2 2006.252.07:35:00.41#ibcon#read 4, iclass 19, count 2 2006.252.07:35:00.41#ibcon#about to read 5, iclass 19, count 2 2006.252.07:35:00.41#ibcon#read 5, iclass 19, count 2 2006.252.07:35:00.41#ibcon#about to read 6, iclass 19, count 2 2006.252.07:35:00.41#ibcon#read 6, iclass 19, count 2 2006.252.07:35:00.41#ibcon#end of sib2, iclass 19, count 2 2006.252.07:35:00.41#ibcon#*mode == 0, iclass 19, count 2 2006.252.07:35:00.41#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.252.07:35:00.41#ibcon#[25=AT08-07\r\n] 2006.252.07:35:00.41#ibcon#*before write, iclass 19, count 2 2006.252.07:35:00.41#ibcon#enter sib2, iclass 19, count 2 2006.252.07:35:00.41#ibcon#flushed, iclass 19, count 2 2006.252.07:35:00.41#ibcon#about to write, iclass 19, count 2 2006.252.07:35:00.41#ibcon#wrote, iclass 19, count 2 2006.252.07:35:00.41#ibcon#about to read 3, iclass 19, count 2 2006.252.07:35:00.44#ibcon#read 3, iclass 19, count 2 2006.252.07:35:00.44#ibcon#about to read 4, iclass 19, count 2 2006.252.07:35:00.44#ibcon#read 4, iclass 19, count 2 2006.252.07:35:00.44#ibcon#about to read 5, iclass 19, count 2 2006.252.07:35:00.44#ibcon#read 5, iclass 19, count 2 2006.252.07:35:00.44#ibcon#about to read 6, iclass 19, count 2 2006.252.07:35:00.44#ibcon#read 6, iclass 19, count 2 2006.252.07:35:00.44#ibcon#end of sib2, iclass 19, count 2 2006.252.07:35:00.44#ibcon#*after write, iclass 19, count 2 2006.252.07:35:00.44#ibcon#*before return 0, iclass 19, count 2 2006.252.07:35:00.44#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.252.07:35:00.44#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.252.07:35:00.44#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.252.07:35:00.44#ibcon#ireg 7 cls_cnt 0 2006.252.07:35:00.44#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.252.07:35:00.56#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.252.07:35:00.56#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.252.07:35:00.56#ibcon#enter wrdev, iclass 19, count 0 2006.252.07:35:00.56#ibcon#first serial, iclass 19, count 0 2006.252.07:35:00.56#ibcon#enter sib2, iclass 19, count 0 2006.252.07:35:00.56#ibcon#flushed, iclass 19, count 0 2006.252.07:35:00.56#ibcon#about to write, iclass 19, count 0 2006.252.07:35:00.56#ibcon#wrote, iclass 19, count 0 2006.252.07:35:00.56#ibcon#about to read 3, iclass 19, count 0 2006.252.07:35:00.58#ibcon#read 3, iclass 19, count 0 2006.252.07:35:00.58#ibcon#about to read 4, iclass 19, count 0 2006.252.07:35:00.58#ibcon#read 4, iclass 19, count 0 2006.252.07:35:00.58#ibcon#about to read 5, iclass 19, count 0 2006.252.07:35:00.58#ibcon#read 5, iclass 19, count 0 2006.252.07:35:00.58#ibcon#about to read 6, iclass 19, count 0 2006.252.07:35:00.58#ibcon#read 6, iclass 19, count 0 2006.252.07:35:00.58#ibcon#end of sib2, iclass 19, count 0 2006.252.07:35:00.58#ibcon#*mode == 0, iclass 19, count 0 2006.252.07:35:00.58#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.252.07:35:00.58#ibcon#[25=USB\r\n] 2006.252.07:35:00.58#ibcon#*before write, iclass 19, count 0 2006.252.07:35:00.58#ibcon#enter sib2, iclass 19, count 0 2006.252.07:35:00.58#ibcon#flushed, iclass 19, count 0 2006.252.07:35:00.58#ibcon#about to write, iclass 19, count 0 2006.252.07:35:00.58#ibcon#wrote, iclass 19, count 0 2006.252.07:35:00.58#ibcon#about to read 3, iclass 19, count 0 2006.252.07:35:00.61#ibcon#read 3, iclass 19, count 0 2006.252.07:35:00.61#ibcon#about to read 4, iclass 19, count 0 2006.252.07:35:00.61#ibcon#read 4, iclass 19, count 0 2006.252.07:35:00.61#ibcon#about to read 5, iclass 19, count 0 2006.252.07:35:00.61#ibcon#read 5, iclass 19, count 0 2006.252.07:35:00.61#ibcon#about to read 6, iclass 19, count 0 2006.252.07:35:00.61#ibcon#read 6, iclass 19, count 0 2006.252.07:35:00.61#ibcon#end of sib2, iclass 19, count 0 2006.252.07:35:00.61#ibcon#*after write, iclass 19, count 0 2006.252.07:35:00.61#ibcon#*before return 0, iclass 19, count 0 2006.252.07:35:00.61#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.252.07:35:00.61#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.252.07:35:00.61#ibcon#about to clear, iclass 19 cls_cnt 0 2006.252.07:35:00.61#ibcon#cleared, iclass 19 cls_cnt 0 2006.252.07:35:00.61$vc4f8/vblo=1,632.99 2006.252.07:35:00.61#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.252.07:35:00.61#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.252.07:35:00.61#ibcon#ireg 17 cls_cnt 0 2006.252.07:35:00.61#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.252.07:35:00.61#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.252.07:35:00.61#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.252.07:35:00.61#ibcon#enter wrdev, iclass 21, count 0 2006.252.07:35:00.61#ibcon#first serial, iclass 21, count 0 2006.252.07:35:00.61#ibcon#enter sib2, iclass 21, count 0 2006.252.07:35:00.61#ibcon#flushed, iclass 21, count 0 2006.252.07:35:00.61#ibcon#about to write, iclass 21, count 0 2006.252.07:35:00.61#ibcon#wrote, iclass 21, count 0 2006.252.07:35:00.61#ibcon#about to read 3, iclass 21, count 0 2006.252.07:35:00.63#ibcon#read 3, iclass 21, count 0 2006.252.07:35:00.63#ibcon#about to read 4, iclass 21, count 0 2006.252.07:35:00.63#ibcon#read 4, iclass 21, count 0 2006.252.07:35:00.63#ibcon#about to read 5, iclass 21, count 0 2006.252.07:35:00.63#ibcon#read 5, iclass 21, count 0 2006.252.07:35:00.63#ibcon#about to read 6, iclass 21, count 0 2006.252.07:35:00.63#ibcon#read 6, iclass 21, count 0 2006.252.07:35:00.63#ibcon#end of sib2, iclass 21, count 0 2006.252.07:35:00.63#ibcon#*mode == 0, iclass 21, count 0 2006.252.07:35:00.63#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.252.07:35:00.63#ibcon#[28=FRQ=01,632.99\r\n] 2006.252.07:35:00.63#ibcon#*before write, iclass 21, count 0 2006.252.07:35:00.63#ibcon#enter sib2, iclass 21, count 0 2006.252.07:35:00.63#ibcon#flushed, iclass 21, count 0 2006.252.07:35:00.63#ibcon#about to write, iclass 21, count 0 2006.252.07:35:00.63#ibcon#wrote, iclass 21, count 0 2006.252.07:35:00.63#ibcon#about to read 3, iclass 21, count 0 2006.252.07:35:00.67#ibcon#read 3, iclass 21, count 0 2006.252.07:35:00.67#ibcon#about to read 4, iclass 21, count 0 2006.252.07:35:00.67#ibcon#read 4, iclass 21, count 0 2006.252.07:35:00.67#ibcon#about to read 5, iclass 21, count 0 2006.252.07:35:00.67#ibcon#read 5, iclass 21, count 0 2006.252.07:35:00.67#ibcon#about to read 6, iclass 21, count 0 2006.252.07:35:00.67#ibcon#read 6, iclass 21, count 0 2006.252.07:35:00.67#ibcon#end of sib2, iclass 21, count 0 2006.252.07:35:00.67#ibcon#*after write, iclass 21, count 0 2006.252.07:35:00.67#ibcon#*before return 0, iclass 21, count 0 2006.252.07:35:00.67#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.252.07:35:00.67#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.252.07:35:00.67#ibcon#about to clear, iclass 21 cls_cnt 0 2006.252.07:35:00.67#ibcon#cleared, iclass 21 cls_cnt 0 2006.252.07:35:00.67$vc4f8/vb=1,4 2006.252.07:35:00.67#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.252.07:35:00.67#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.252.07:35:00.67#ibcon#ireg 11 cls_cnt 2 2006.252.07:35:00.67#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.252.07:35:00.67#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.252.07:35:00.67#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.252.07:35:00.67#ibcon#enter wrdev, iclass 23, count 2 2006.252.07:35:00.67#ibcon#first serial, iclass 23, count 2 2006.252.07:35:00.67#ibcon#enter sib2, iclass 23, count 2 2006.252.07:35:00.67#ibcon#flushed, iclass 23, count 2 2006.252.07:35:00.67#ibcon#about to write, iclass 23, count 2 2006.252.07:35:00.67#ibcon#wrote, iclass 23, count 2 2006.252.07:35:00.67#ibcon#about to read 3, iclass 23, count 2 2006.252.07:35:00.69#ibcon#read 3, iclass 23, count 2 2006.252.07:35:00.69#ibcon#about to read 4, iclass 23, count 2 2006.252.07:35:00.69#ibcon#read 4, iclass 23, count 2 2006.252.07:35:00.69#ibcon#about to read 5, iclass 23, count 2 2006.252.07:35:00.69#ibcon#read 5, iclass 23, count 2 2006.252.07:35:00.69#ibcon#about to read 6, iclass 23, count 2 2006.252.07:35:00.69#ibcon#read 6, iclass 23, count 2 2006.252.07:35:00.69#ibcon#end of sib2, iclass 23, count 2 2006.252.07:35:00.69#ibcon#*mode == 0, iclass 23, count 2 2006.252.07:35:00.69#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.252.07:35:00.69#ibcon#[27=AT01-04\r\n] 2006.252.07:35:00.69#ibcon#*before write, iclass 23, count 2 2006.252.07:35:00.69#ibcon#enter sib2, iclass 23, count 2 2006.252.07:35:00.69#ibcon#flushed, iclass 23, count 2 2006.252.07:35:00.69#ibcon#about to write, iclass 23, count 2 2006.252.07:35:00.69#ibcon#wrote, iclass 23, count 2 2006.252.07:35:00.69#ibcon#about to read 3, iclass 23, count 2 2006.252.07:35:00.72#ibcon#read 3, iclass 23, count 2 2006.252.07:35:00.72#ibcon#about to read 4, iclass 23, count 2 2006.252.07:35:00.72#ibcon#read 4, iclass 23, count 2 2006.252.07:35:00.72#ibcon#about to read 5, iclass 23, count 2 2006.252.07:35:00.72#ibcon#read 5, iclass 23, count 2 2006.252.07:35:00.72#ibcon#about to read 6, iclass 23, count 2 2006.252.07:35:00.72#ibcon#read 6, iclass 23, count 2 2006.252.07:35:00.72#ibcon#end of sib2, iclass 23, count 2 2006.252.07:35:00.72#ibcon#*after write, iclass 23, count 2 2006.252.07:35:00.72#ibcon#*before return 0, iclass 23, count 2 2006.252.07:35:00.72#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.252.07:35:00.72#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.252.07:35:00.72#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.252.07:35:00.72#ibcon#ireg 7 cls_cnt 0 2006.252.07:35:00.72#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.252.07:35:00.84#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.252.07:35:00.84#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.252.07:35:00.84#ibcon#enter wrdev, iclass 23, count 0 2006.252.07:35:00.84#ibcon#first serial, iclass 23, count 0 2006.252.07:35:00.84#ibcon#enter sib2, iclass 23, count 0 2006.252.07:35:00.84#ibcon#flushed, iclass 23, count 0 2006.252.07:35:00.84#ibcon#about to write, iclass 23, count 0 2006.252.07:35:00.84#ibcon#wrote, iclass 23, count 0 2006.252.07:35:00.84#ibcon#about to read 3, iclass 23, count 0 2006.252.07:35:00.86#ibcon#read 3, iclass 23, count 0 2006.252.07:35:00.86#ibcon#about to read 4, iclass 23, count 0 2006.252.07:35:00.86#ibcon#read 4, iclass 23, count 0 2006.252.07:35:00.86#ibcon#about to read 5, iclass 23, count 0 2006.252.07:35:00.86#ibcon#read 5, iclass 23, count 0 2006.252.07:35:00.86#ibcon#about to read 6, iclass 23, count 0 2006.252.07:35:00.86#ibcon#read 6, iclass 23, count 0 2006.252.07:35:00.86#ibcon#end of sib2, iclass 23, count 0 2006.252.07:35:00.86#ibcon#*mode == 0, iclass 23, count 0 2006.252.07:35:00.86#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.252.07:35:00.86#ibcon#[27=USB\r\n] 2006.252.07:35:00.86#ibcon#*before write, iclass 23, count 0 2006.252.07:35:00.86#ibcon#enter sib2, iclass 23, count 0 2006.252.07:35:00.86#ibcon#flushed, iclass 23, count 0 2006.252.07:35:00.86#ibcon#about to write, iclass 23, count 0 2006.252.07:35:00.86#ibcon#wrote, iclass 23, count 0 2006.252.07:35:00.86#ibcon#about to read 3, iclass 23, count 0 2006.252.07:35:00.89#ibcon#read 3, iclass 23, count 0 2006.252.07:35:00.89#ibcon#about to read 4, iclass 23, count 0 2006.252.07:35:00.89#ibcon#read 4, iclass 23, count 0 2006.252.07:35:00.89#ibcon#about to read 5, iclass 23, count 0 2006.252.07:35:00.89#ibcon#read 5, iclass 23, count 0 2006.252.07:35:00.89#ibcon#about to read 6, iclass 23, count 0 2006.252.07:35:00.89#ibcon#read 6, iclass 23, count 0 2006.252.07:35:00.89#ibcon#end of sib2, iclass 23, count 0 2006.252.07:35:00.89#ibcon#*after write, iclass 23, count 0 2006.252.07:35:00.89#ibcon#*before return 0, iclass 23, count 0 2006.252.07:35:00.89#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.252.07:35:00.89#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.252.07:35:00.89#ibcon#about to clear, iclass 23 cls_cnt 0 2006.252.07:35:00.89#ibcon#cleared, iclass 23 cls_cnt 0 2006.252.07:35:00.89$vc4f8/vblo=2,640.99 2006.252.07:35:00.89#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.252.07:35:00.89#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.252.07:35:00.89#ibcon#ireg 17 cls_cnt 0 2006.252.07:35:00.89#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.252.07:35:00.89#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.252.07:35:00.89#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.252.07:35:00.89#ibcon#enter wrdev, iclass 25, count 0 2006.252.07:35:00.89#ibcon#first serial, iclass 25, count 0 2006.252.07:35:00.89#ibcon#enter sib2, iclass 25, count 0 2006.252.07:35:00.89#ibcon#flushed, iclass 25, count 0 2006.252.07:35:00.89#ibcon#about to write, iclass 25, count 0 2006.252.07:35:00.89#ibcon#wrote, iclass 25, count 0 2006.252.07:35:00.89#ibcon#about to read 3, iclass 25, count 0 2006.252.07:35:00.91#ibcon#read 3, iclass 25, count 0 2006.252.07:35:00.91#ibcon#about to read 4, iclass 25, count 0 2006.252.07:35:00.91#ibcon#read 4, iclass 25, count 0 2006.252.07:35:00.91#ibcon#about to read 5, iclass 25, count 0 2006.252.07:35:00.91#ibcon#read 5, iclass 25, count 0 2006.252.07:35:00.91#ibcon#about to read 6, iclass 25, count 0 2006.252.07:35:00.91#ibcon#read 6, iclass 25, count 0 2006.252.07:35:00.91#ibcon#end of sib2, iclass 25, count 0 2006.252.07:35:00.91#ibcon#*mode == 0, iclass 25, count 0 2006.252.07:35:00.91#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.252.07:35:00.91#ibcon#[28=FRQ=02,640.99\r\n] 2006.252.07:35:00.91#ibcon#*before write, iclass 25, count 0 2006.252.07:35:00.91#ibcon#enter sib2, iclass 25, count 0 2006.252.07:35:00.91#ibcon#flushed, iclass 25, count 0 2006.252.07:35:00.91#ibcon#about to write, iclass 25, count 0 2006.252.07:35:00.91#ibcon#wrote, iclass 25, count 0 2006.252.07:35:00.91#ibcon#about to read 3, iclass 25, count 0 2006.252.07:35:00.95#ibcon#read 3, iclass 25, count 0 2006.252.07:35:00.95#ibcon#about to read 4, iclass 25, count 0 2006.252.07:35:00.95#ibcon#read 4, iclass 25, count 0 2006.252.07:35:00.95#ibcon#about to read 5, iclass 25, count 0 2006.252.07:35:00.95#ibcon#read 5, iclass 25, count 0 2006.252.07:35:00.95#ibcon#about to read 6, iclass 25, count 0 2006.252.07:35:00.95#ibcon#read 6, iclass 25, count 0 2006.252.07:35:00.95#ibcon#end of sib2, iclass 25, count 0 2006.252.07:35:00.95#ibcon#*after write, iclass 25, count 0 2006.252.07:35:00.95#ibcon#*before return 0, iclass 25, count 0 2006.252.07:35:00.95#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.252.07:35:00.95#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.252.07:35:00.95#ibcon#about to clear, iclass 25 cls_cnt 0 2006.252.07:35:00.95#ibcon#cleared, iclass 25 cls_cnt 0 2006.252.07:35:00.95$vc4f8/vb=2,5 2006.252.07:35:00.95#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.252.07:35:00.95#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.252.07:35:00.95#ibcon#ireg 11 cls_cnt 2 2006.252.07:35:00.95#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.252.07:35:01.01#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.252.07:35:01.01#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.252.07:35:01.01#ibcon#enter wrdev, iclass 27, count 2 2006.252.07:35:01.01#ibcon#first serial, iclass 27, count 2 2006.252.07:35:01.01#ibcon#enter sib2, iclass 27, count 2 2006.252.07:35:01.01#ibcon#flushed, iclass 27, count 2 2006.252.07:35:01.01#ibcon#about to write, iclass 27, count 2 2006.252.07:35:01.01#ibcon#wrote, iclass 27, count 2 2006.252.07:35:01.01#ibcon#about to read 3, iclass 27, count 2 2006.252.07:35:01.03#ibcon#read 3, iclass 27, count 2 2006.252.07:35:01.03#ibcon#about to read 4, iclass 27, count 2 2006.252.07:35:01.03#ibcon#read 4, iclass 27, count 2 2006.252.07:35:01.03#ibcon#about to read 5, iclass 27, count 2 2006.252.07:35:01.03#ibcon#read 5, iclass 27, count 2 2006.252.07:35:01.03#ibcon#about to read 6, iclass 27, count 2 2006.252.07:35:01.03#ibcon#read 6, iclass 27, count 2 2006.252.07:35:01.03#ibcon#end of sib2, iclass 27, count 2 2006.252.07:35:01.03#ibcon#*mode == 0, iclass 27, count 2 2006.252.07:35:01.03#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.252.07:35:01.03#ibcon#[27=AT02-05\r\n] 2006.252.07:35:01.03#ibcon#*before write, iclass 27, count 2 2006.252.07:35:01.03#ibcon#enter sib2, iclass 27, count 2 2006.252.07:35:01.03#ibcon#flushed, iclass 27, count 2 2006.252.07:35:01.03#ibcon#about to write, iclass 27, count 2 2006.252.07:35:01.03#ibcon#wrote, iclass 27, count 2 2006.252.07:35:01.03#ibcon#about to read 3, iclass 27, count 2 2006.252.07:35:01.06#ibcon#read 3, iclass 27, count 2 2006.252.07:35:01.06#ibcon#about to read 4, iclass 27, count 2 2006.252.07:35:01.06#ibcon#read 4, iclass 27, count 2 2006.252.07:35:01.06#ibcon#about to read 5, iclass 27, count 2 2006.252.07:35:01.06#ibcon#read 5, iclass 27, count 2 2006.252.07:35:01.06#ibcon#about to read 6, iclass 27, count 2 2006.252.07:35:01.06#ibcon#read 6, iclass 27, count 2 2006.252.07:35:01.06#ibcon#end of sib2, iclass 27, count 2 2006.252.07:35:01.06#ibcon#*after write, iclass 27, count 2 2006.252.07:35:01.06#ibcon#*before return 0, iclass 27, count 2 2006.252.07:35:01.06#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.252.07:35:01.06#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.252.07:35:01.06#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.252.07:35:01.06#ibcon#ireg 7 cls_cnt 0 2006.252.07:35:01.06#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.252.07:35:01.18#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.252.07:35:01.18#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.252.07:35:01.18#ibcon#enter wrdev, iclass 27, count 0 2006.252.07:35:01.18#ibcon#first serial, iclass 27, count 0 2006.252.07:35:01.18#ibcon#enter sib2, iclass 27, count 0 2006.252.07:35:01.18#ibcon#flushed, iclass 27, count 0 2006.252.07:35:01.18#ibcon#about to write, iclass 27, count 0 2006.252.07:35:01.18#ibcon#wrote, iclass 27, count 0 2006.252.07:35:01.18#ibcon#about to read 3, iclass 27, count 0 2006.252.07:35:01.20#ibcon#read 3, iclass 27, count 0 2006.252.07:35:01.20#ibcon#about to read 4, iclass 27, count 0 2006.252.07:35:01.20#ibcon#read 4, iclass 27, count 0 2006.252.07:35:01.20#ibcon#about to read 5, iclass 27, count 0 2006.252.07:35:01.20#ibcon#read 5, iclass 27, count 0 2006.252.07:35:01.20#ibcon#about to read 6, iclass 27, count 0 2006.252.07:35:01.20#ibcon#read 6, iclass 27, count 0 2006.252.07:35:01.20#ibcon#end of sib2, iclass 27, count 0 2006.252.07:35:01.20#ibcon#*mode == 0, iclass 27, count 0 2006.252.07:35:01.20#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.252.07:35:01.20#ibcon#[27=USB\r\n] 2006.252.07:35:01.20#ibcon#*before write, iclass 27, count 0 2006.252.07:35:01.20#ibcon#enter sib2, iclass 27, count 0 2006.252.07:35:01.20#ibcon#flushed, iclass 27, count 0 2006.252.07:35:01.20#ibcon#about to write, iclass 27, count 0 2006.252.07:35:01.20#ibcon#wrote, iclass 27, count 0 2006.252.07:35:01.20#ibcon#about to read 3, iclass 27, count 0 2006.252.07:35:01.23#ibcon#read 3, iclass 27, count 0 2006.252.07:35:01.23#ibcon#about to read 4, iclass 27, count 0 2006.252.07:35:01.23#ibcon#read 4, iclass 27, count 0 2006.252.07:35:01.23#ibcon#about to read 5, iclass 27, count 0 2006.252.07:35:01.23#ibcon#read 5, iclass 27, count 0 2006.252.07:35:01.23#ibcon#about to read 6, iclass 27, count 0 2006.252.07:35:01.23#ibcon#read 6, iclass 27, count 0 2006.252.07:35:01.23#ibcon#end of sib2, iclass 27, count 0 2006.252.07:35:01.23#ibcon#*after write, iclass 27, count 0 2006.252.07:35:01.23#ibcon#*before return 0, iclass 27, count 0 2006.252.07:35:01.23#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.252.07:35:01.23#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.252.07:35:01.23#ibcon#about to clear, iclass 27 cls_cnt 0 2006.252.07:35:01.23#ibcon#cleared, iclass 27 cls_cnt 0 2006.252.07:35:01.23$vc4f8/vblo=3,656.99 2006.252.07:35:01.23#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.252.07:35:01.23#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.252.07:35:01.23#ibcon#ireg 17 cls_cnt 0 2006.252.07:35:01.23#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.252.07:35:01.23#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.252.07:35:01.23#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.252.07:35:01.23#ibcon#enter wrdev, iclass 29, count 0 2006.252.07:35:01.23#ibcon#first serial, iclass 29, count 0 2006.252.07:35:01.23#ibcon#enter sib2, iclass 29, count 0 2006.252.07:35:01.23#ibcon#flushed, iclass 29, count 0 2006.252.07:35:01.23#ibcon#about to write, iclass 29, count 0 2006.252.07:35:01.23#ibcon#wrote, iclass 29, count 0 2006.252.07:35:01.23#ibcon#about to read 3, iclass 29, count 0 2006.252.07:35:01.25#ibcon#read 3, iclass 29, count 0 2006.252.07:35:01.25#ibcon#about to read 4, iclass 29, count 0 2006.252.07:35:01.25#ibcon#read 4, iclass 29, count 0 2006.252.07:35:01.25#ibcon#about to read 5, iclass 29, count 0 2006.252.07:35:01.25#ibcon#read 5, iclass 29, count 0 2006.252.07:35:01.25#ibcon#about to read 6, iclass 29, count 0 2006.252.07:35:01.25#ibcon#read 6, iclass 29, count 0 2006.252.07:35:01.25#ibcon#end of sib2, iclass 29, count 0 2006.252.07:35:01.25#ibcon#*mode == 0, iclass 29, count 0 2006.252.07:35:01.25#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.252.07:35:01.25#ibcon#[28=FRQ=03,656.99\r\n] 2006.252.07:35:01.25#ibcon#*before write, iclass 29, count 0 2006.252.07:35:01.25#ibcon#enter sib2, iclass 29, count 0 2006.252.07:35:01.25#ibcon#flushed, iclass 29, count 0 2006.252.07:35:01.25#ibcon#about to write, iclass 29, count 0 2006.252.07:35:01.25#ibcon#wrote, iclass 29, count 0 2006.252.07:35:01.25#ibcon#about to read 3, iclass 29, count 0 2006.252.07:35:01.29#ibcon#read 3, iclass 29, count 0 2006.252.07:35:01.29#ibcon#about to read 4, iclass 29, count 0 2006.252.07:35:01.29#ibcon#read 4, iclass 29, count 0 2006.252.07:35:01.29#ibcon#about to read 5, iclass 29, count 0 2006.252.07:35:01.29#ibcon#read 5, iclass 29, count 0 2006.252.07:35:01.29#ibcon#about to read 6, iclass 29, count 0 2006.252.07:35:01.29#ibcon#read 6, iclass 29, count 0 2006.252.07:35:01.29#ibcon#end of sib2, iclass 29, count 0 2006.252.07:35:01.29#ibcon#*after write, iclass 29, count 0 2006.252.07:35:01.29#ibcon#*before return 0, iclass 29, count 0 2006.252.07:35:01.29#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.252.07:35:01.29#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.252.07:35:01.29#ibcon#about to clear, iclass 29 cls_cnt 0 2006.252.07:35:01.29#ibcon#cleared, iclass 29 cls_cnt 0 2006.252.07:35:01.29$vc4f8/vb=3,4 2006.252.07:35:01.29#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.252.07:35:01.29#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.252.07:35:01.29#ibcon#ireg 11 cls_cnt 2 2006.252.07:35:01.29#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.252.07:35:01.35#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.252.07:35:01.35#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.252.07:35:01.35#ibcon#enter wrdev, iclass 31, count 2 2006.252.07:35:01.35#ibcon#first serial, iclass 31, count 2 2006.252.07:35:01.35#ibcon#enter sib2, iclass 31, count 2 2006.252.07:35:01.35#ibcon#flushed, iclass 31, count 2 2006.252.07:35:01.35#ibcon#about to write, iclass 31, count 2 2006.252.07:35:01.35#ibcon#wrote, iclass 31, count 2 2006.252.07:35:01.35#ibcon#about to read 3, iclass 31, count 2 2006.252.07:35:01.37#ibcon#read 3, iclass 31, count 2 2006.252.07:35:01.37#ibcon#about to read 4, iclass 31, count 2 2006.252.07:35:01.37#ibcon#read 4, iclass 31, count 2 2006.252.07:35:01.37#ibcon#about to read 5, iclass 31, count 2 2006.252.07:35:01.37#ibcon#read 5, iclass 31, count 2 2006.252.07:35:01.37#ibcon#about to read 6, iclass 31, count 2 2006.252.07:35:01.37#ibcon#read 6, iclass 31, count 2 2006.252.07:35:01.37#ibcon#end of sib2, iclass 31, count 2 2006.252.07:35:01.37#ibcon#*mode == 0, iclass 31, count 2 2006.252.07:35:01.37#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.252.07:35:01.37#ibcon#[27=AT03-04\r\n] 2006.252.07:35:01.37#ibcon#*before write, iclass 31, count 2 2006.252.07:35:01.37#ibcon#enter sib2, iclass 31, count 2 2006.252.07:35:01.37#ibcon#flushed, iclass 31, count 2 2006.252.07:35:01.37#ibcon#about to write, iclass 31, count 2 2006.252.07:35:01.37#ibcon#wrote, iclass 31, count 2 2006.252.07:35:01.37#ibcon#about to read 3, iclass 31, count 2 2006.252.07:35:01.40#ibcon#read 3, iclass 31, count 2 2006.252.07:35:01.40#ibcon#about to read 4, iclass 31, count 2 2006.252.07:35:01.40#ibcon#read 4, iclass 31, count 2 2006.252.07:35:01.40#ibcon#about to read 5, iclass 31, count 2 2006.252.07:35:01.40#ibcon#read 5, iclass 31, count 2 2006.252.07:35:01.40#ibcon#about to read 6, iclass 31, count 2 2006.252.07:35:01.40#ibcon#read 6, iclass 31, count 2 2006.252.07:35:01.40#ibcon#end of sib2, iclass 31, count 2 2006.252.07:35:01.40#ibcon#*after write, iclass 31, count 2 2006.252.07:35:01.40#ibcon#*before return 0, iclass 31, count 2 2006.252.07:35:01.40#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.252.07:35:01.40#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.252.07:35:01.40#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.252.07:35:01.40#ibcon#ireg 7 cls_cnt 0 2006.252.07:35:01.40#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.252.07:35:01.52#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.252.07:35:01.52#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.252.07:35:01.52#ibcon#enter wrdev, iclass 31, count 0 2006.252.07:35:01.52#ibcon#first serial, iclass 31, count 0 2006.252.07:35:01.52#ibcon#enter sib2, iclass 31, count 0 2006.252.07:35:01.52#ibcon#flushed, iclass 31, count 0 2006.252.07:35:01.52#ibcon#about to write, iclass 31, count 0 2006.252.07:35:01.52#ibcon#wrote, iclass 31, count 0 2006.252.07:35:01.52#ibcon#about to read 3, iclass 31, count 0 2006.252.07:35:01.54#ibcon#read 3, iclass 31, count 0 2006.252.07:35:01.54#ibcon#about to read 4, iclass 31, count 0 2006.252.07:35:01.54#ibcon#read 4, iclass 31, count 0 2006.252.07:35:01.54#ibcon#about to read 5, iclass 31, count 0 2006.252.07:35:01.54#ibcon#read 5, iclass 31, count 0 2006.252.07:35:01.54#ibcon#about to read 6, iclass 31, count 0 2006.252.07:35:01.54#ibcon#read 6, iclass 31, count 0 2006.252.07:35:01.54#ibcon#end of sib2, iclass 31, count 0 2006.252.07:35:01.54#ibcon#*mode == 0, iclass 31, count 0 2006.252.07:35:01.54#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.252.07:35:01.54#ibcon#[27=USB\r\n] 2006.252.07:35:01.54#ibcon#*before write, iclass 31, count 0 2006.252.07:35:01.54#ibcon#enter sib2, iclass 31, count 0 2006.252.07:35:01.54#ibcon#flushed, iclass 31, count 0 2006.252.07:35:01.54#ibcon#about to write, iclass 31, count 0 2006.252.07:35:01.54#ibcon#wrote, iclass 31, count 0 2006.252.07:35:01.54#ibcon#about to read 3, iclass 31, count 0 2006.252.07:35:01.57#ibcon#read 3, iclass 31, count 0 2006.252.07:35:01.57#ibcon#about to read 4, iclass 31, count 0 2006.252.07:35:01.57#ibcon#read 4, iclass 31, count 0 2006.252.07:35:01.57#ibcon#about to read 5, iclass 31, count 0 2006.252.07:35:01.57#ibcon#read 5, iclass 31, count 0 2006.252.07:35:01.57#ibcon#about to read 6, iclass 31, count 0 2006.252.07:35:01.57#ibcon#read 6, iclass 31, count 0 2006.252.07:35:01.57#ibcon#end of sib2, iclass 31, count 0 2006.252.07:35:01.57#ibcon#*after write, iclass 31, count 0 2006.252.07:35:01.57#ibcon#*before return 0, iclass 31, count 0 2006.252.07:35:01.57#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.252.07:35:01.57#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.252.07:35:01.57#ibcon#about to clear, iclass 31 cls_cnt 0 2006.252.07:35:01.57#ibcon#cleared, iclass 31 cls_cnt 0 2006.252.07:35:01.57$vc4f8/vblo=4,712.99 2006.252.07:35:01.57#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.252.07:35:01.57#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.252.07:35:01.57#ibcon#ireg 17 cls_cnt 0 2006.252.07:35:01.57#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.252.07:35:01.57#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.252.07:35:01.57#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.252.07:35:01.57#ibcon#enter wrdev, iclass 33, count 0 2006.252.07:35:01.57#ibcon#first serial, iclass 33, count 0 2006.252.07:35:01.57#ibcon#enter sib2, iclass 33, count 0 2006.252.07:35:01.57#ibcon#flushed, iclass 33, count 0 2006.252.07:35:01.57#ibcon#about to write, iclass 33, count 0 2006.252.07:35:01.57#ibcon#wrote, iclass 33, count 0 2006.252.07:35:01.57#ibcon#about to read 3, iclass 33, count 0 2006.252.07:35:01.59#ibcon#read 3, iclass 33, count 0 2006.252.07:35:01.59#ibcon#about to read 4, iclass 33, count 0 2006.252.07:35:01.59#ibcon#read 4, iclass 33, count 0 2006.252.07:35:01.59#ibcon#about to read 5, iclass 33, count 0 2006.252.07:35:01.59#ibcon#read 5, iclass 33, count 0 2006.252.07:35:01.59#ibcon#about to read 6, iclass 33, count 0 2006.252.07:35:01.59#ibcon#read 6, iclass 33, count 0 2006.252.07:35:01.59#ibcon#end of sib2, iclass 33, count 0 2006.252.07:35:01.59#ibcon#*mode == 0, iclass 33, count 0 2006.252.07:35:01.59#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.252.07:35:01.59#ibcon#[28=FRQ=04,712.99\r\n] 2006.252.07:35:01.59#ibcon#*before write, iclass 33, count 0 2006.252.07:35:01.59#ibcon#enter sib2, iclass 33, count 0 2006.252.07:35:01.59#ibcon#flushed, iclass 33, count 0 2006.252.07:35:01.59#ibcon#about to write, iclass 33, count 0 2006.252.07:35:01.59#ibcon#wrote, iclass 33, count 0 2006.252.07:35:01.59#ibcon#about to read 3, iclass 33, count 0 2006.252.07:35:01.63#ibcon#read 3, iclass 33, count 0 2006.252.07:35:01.63#ibcon#about to read 4, iclass 33, count 0 2006.252.07:35:01.63#ibcon#read 4, iclass 33, count 0 2006.252.07:35:01.63#ibcon#about to read 5, iclass 33, count 0 2006.252.07:35:01.63#ibcon#read 5, iclass 33, count 0 2006.252.07:35:01.63#ibcon#about to read 6, iclass 33, count 0 2006.252.07:35:01.63#ibcon#read 6, iclass 33, count 0 2006.252.07:35:01.63#ibcon#end of sib2, iclass 33, count 0 2006.252.07:35:01.63#ibcon#*after write, iclass 33, count 0 2006.252.07:35:01.63#ibcon#*before return 0, iclass 33, count 0 2006.252.07:35:01.63#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.252.07:35:01.63#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.252.07:35:01.63#ibcon#about to clear, iclass 33 cls_cnt 0 2006.252.07:35:01.63#ibcon#cleared, iclass 33 cls_cnt 0 2006.252.07:35:01.63$vc4f8/vb=4,4 2006.252.07:35:01.63#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.252.07:35:01.63#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.252.07:35:01.63#ibcon#ireg 11 cls_cnt 2 2006.252.07:35:01.63#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.252.07:35:01.69#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.252.07:35:01.69#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.252.07:35:01.69#ibcon#enter wrdev, iclass 35, count 2 2006.252.07:35:01.69#ibcon#first serial, iclass 35, count 2 2006.252.07:35:01.69#ibcon#enter sib2, iclass 35, count 2 2006.252.07:35:01.69#ibcon#flushed, iclass 35, count 2 2006.252.07:35:01.69#ibcon#about to write, iclass 35, count 2 2006.252.07:35:01.69#ibcon#wrote, iclass 35, count 2 2006.252.07:35:01.69#ibcon#about to read 3, iclass 35, count 2 2006.252.07:35:01.71#ibcon#read 3, iclass 35, count 2 2006.252.07:35:01.71#ibcon#about to read 4, iclass 35, count 2 2006.252.07:35:01.71#ibcon#read 4, iclass 35, count 2 2006.252.07:35:01.71#ibcon#about to read 5, iclass 35, count 2 2006.252.07:35:01.71#ibcon#read 5, iclass 35, count 2 2006.252.07:35:01.71#ibcon#about to read 6, iclass 35, count 2 2006.252.07:35:01.71#ibcon#read 6, iclass 35, count 2 2006.252.07:35:01.71#ibcon#end of sib2, iclass 35, count 2 2006.252.07:35:01.71#ibcon#*mode == 0, iclass 35, count 2 2006.252.07:35:01.71#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.252.07:35:01.71#ibcon#[27=AT04-04\r\n] 2006.252.07:35:01.71#ibcon#*before write, iclass 35, count 2 2006.252.07:35:01.71#ibcon#enter sib2, iclass 35, count 2 2006.252.07:35:01.71#ibcon#flushed, iclass 35, count 2 2006.252.07:35:01.71#ibcon#about to write, iclass 35, count 2 2006.252.07:35:01.71#ibcon#wrote, iclass 35, count 2 2006.252.07:35:01.71#ibcon#about to read 3, iclass 35, count 2 2006.252.07:35:01.74#ibcon#read 3, iclass 35, count 2 2006.252.07:35:01.74#ibcon#about to read 4, iclass 35, count 2 2006.252.07:35:01.74#ibcon#read 4, iclass 35, count 2 2006.252.07:35:01.74#ibcon#about to read 5, iclass 35, count 2 2006.252.07:35:01.74#ibcon#read 5, iclass 35, count 2 2006.252.07:35:01.74#ibcon#about to read 6, iclass 35, count 2 2006.252.07:35:01.74#ibcon#read 6, iclass 35, count 2 2006.252.07:35:01.74#ibcon#end of sib2, iclass 35, count 2 2006.252.07:35:01.74#ibcon#*after write, iclass 35, count 2 2006.252.07:35:01.74#ibcon#*before return 0, iclass 35, count 2 2006.252.07:35:01.74#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.252.07:35:01.74#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.252.07:35:01.74#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.252.07:35:01.74#ibcon#ireg 7 cls_cnt 0 2006.252.07:35:01.74#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.252.07:35:01.86#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.252.07:35:01.86#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.252.07:35:01.86#ibcon#enter wrdev, iclass 35, count 0 2006.252.07:35:01.86#ibcon#first serial, iclass 35, count 0 2006.252.07:35:01.86#ibcon#enter sib2, iclass 35, count 0 2006.252.07:35:01.86#ibcon#flushed, iclass 35, count 0 2006.252.07:35:01.86#ibcon#about to write, iclass 35, count 0 2006.252.07:35:01.86#ibcon#wrote, iclass 35, count 0 2006.252.07:35:01.86#ibcon#about to read 3, iclass 35, count 0 2006.252.07:35:01.88#ibcon#read 3, iclass 35, count 0 2006.252.07:35:01.88#ibcon#about to read 4, iclass 35, count 0 2006.252.07:35:01.88#ibcon#read 4, iclass 35, count 0 2006.252.07:35:01.88#ibcon#about to read 5, iclass 35, count 0 2006.252.07:35:01.88#ibcon#read 5, iclass 35, count 0 2006.252.07:35:01.88#ibcon#about to read 6, iclass 35, count 0 2006.252.07:35:01.88#ibcon#read 6, iclass 35, count 0 2006.252.07:35:01.88#ibcon#end of sib2, iclass 35, count 0 2006.252.07:35:01.88#ibcon#*mode == 0, iclass 35, count 0 2006.252.07:35:01.88#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.252.07:35:01.88#ibcon#[27=USB\r\n] 2006.252.07:35:01.88#ibcon#*before write, iclass 35, count 0 2006.252.07:35:01.88#ibcon#enter sib2, iclass 35, count 0 2006.252.07:35:01.88#ibcon#flushed, iclass 35, count 0 2006.252.07:35:01.88#ibcon#about to write, iclass 35, count 0 2006.252.07:35:01.88#ibcon#wrote, iclass 35, count 0 2006.252.07:35:01.88#ibcon#about to read 3, iclass 35, count 0 2006.252.07:35:01.91#ibcon#read 3, iclass 35, count 0 2006.252.07:35:01.91#ibcon#about to read 4, iclass 35, count 0 2006.252.07:35:01.91#ibcon#read 4, iclass 35, count 0 2006.252.07:35:01.91#ibcon#about to read 5, iclass 35, count 0 2006.252.07:35:01.91#ibcon#read 5, iclass 35, count 0 2006.252.07:35:01.91#ibcon#about to read 6, iclass 35, count 0 2006.252.07:35:01.91#ibcon#read 6, iclass 35, count 0 2006.252.07:35:01.91#ibcon#end of sib2, iclass 35, count 0 2006.252.07:35:01.91#ibcon#*after write, iclass 35, count 0 2006.252.07:35:01.91#ibcon#*before return 0, iclass 35, count 0 2006.252.07:35:01.91#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.252.07:35:01.91#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.252.07:35:01.91#ibcon#about to clear, iclass 35 cls_cnt 0 2006.252.07:35:01.91#ibcon#cleared, iclass 35 cls_cnt 0 2006.252.07:35:01.91$vc4f8/vblo=5,744.99 2006.252.07:35:01.91#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.252.07:35:01.91#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.252.07:35:01.91#ibcon#ireg 17 cls_cnt 0 2006.252.07:35:01.91#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.252.07:35:01.91#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.252.07:35:01.91#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.252.07:35:01.91#ibcon#enter wrdev, iclass 37, count 0 2006.252.07:35:01.91#ibcon#first serial, iclass 37, count 0 2006.252.07:35:01.91#ibcon#enter sib2, iclass 37, count 0 2006.252.07:35:01.91#ibcon#flushed, iclass 37, count 0 2006.252.07:35:01.91#ibcon#about to write, iclass 37, count 0 2006.252.07:35:01.91#ibcon#wrote, iclass 37, count 0 2006.252.07:35:01.91#ibcon#about to read 3, iclass 37, count 0 2006.252.07:35:01.93#ibcon#read 3, iclass 37, count 0 2006.252.07:35:01.93#ibcon#about to read 4, iclass 37, count 0 2006.252.07:35:01.93#ibcon#read 4, iclass 37, count 0 2006.252.07:35:01.93#ibcon#about to read 5, iclass 37, count 0 2006.252.07:35:01.93#ibcon#read 5, iclass 37, count 0 2006.252.07:35:01.93#ibcon#about to read 6, iclass 37, count 0 2006.252.07:35:01.93#ibcon#read 6, iclass 37, count 0 2006.252.07:35:01.93#ibcon#end of sib2, iclass 37, count 0 2006.252.07:35:01.93#ibcon#*mode == 0, iclass 37, count 0 2006.252.07:35:01.93#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.252.07:35:01.93#ibcon#[28=FRQ=05,744.99\r\n] 2006.252.07:35:01.93#ibcon#*before write, iclass 37, count 0 2006.252.07:35:01.93#ibcon#enter sib2, iclass 37, count 0 2006.252.07:35:01.93#ibcon#flushed, iclass 37, count 0 2006.252.07:35:01.93#ibcon#about to write, iclass 37, count 0 2006.252.07:35:01.93#ibcon#wrote, iclass 37, count 0 2006.252.07:35:01.93#ibcon#about to read 3, iclass 37, count 0 2006.252.07:35:01.97#ibcon#read 3, iclass 37, count 0 2006.252.07:35:01.97#ibcon#about to read 4, iclass 37, count 0 2006.252.07:35:01.97#ibcon#read 4, iclass 37, count 0 2006.252.07:35:01.97#ibcon#about to read 5, iclass 37, count 0 2006.252.07:35:01.97#ibcon#read 5, iclass 37, count 0 2006.252.07:35:01.97#ibcon#about to read 6, iclass 37, count 0 2006.252.07:35:01.97#ibcon#read 6, iclass 37, count 0 2006.252.07:35:01.97#ibcon#end of sib2, iclass 37, count 0 2006.252.07:35:01.97#ibcon#*after write, iclass 37, count 0 2006.252.07:35:01.97#ibcon#*before return 0, iclass 37, count 0 2006.252.07:35:01.97#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.252.07:35:01.97#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.252.07:35:01.97#ibcon#about to clear, iclass 37 cls_cnt 0 2006.252.07:35:01.97#ibcon#cleared, iclass 37 cls_cnt 0 2006.252.07:35:01.97$vc4f8/vb=5,4 2006.252.07:35:01.97#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.252.07:35:01.97#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.252.07:35:01.97#ibcon#ireg 11 cls_cnt 2 2006.252.07:35:01.97#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.252.07:35:02.03#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.252.07:35:02.03#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.252.07:35:02.03#ibcon#enter wrdev, iclass 39, count 2 2006.252.07:35:02.03#ibcon#first serial, iclass 39, count 2 2006.252.07:35:02.03#ibcon#enter sib2, iclass 39, count 2 2006.252.07:35:02.03#ibcon#flushed, iclass 39, count 2 2006.252.07:35:02.03#ibcon#about to write, iclass 39, count 2 2006.252.07:35:02.03#ibcon#wrote, iclass 39, count 2 2006.252.07:35:02.03#ibcon#about to read 3, iclass 39, count 2 2006.252.07:35:02.05#ibcon#read 3, iclass 39, count 2 2006.252.07:35:02.05#ibcon#about to read 4, iclass 39, count 2 2006.252.07:35:02.05#ibcon#read 4, iclass 39, count 2 2006.252.07:35:02.05#ibcon#about to read 5, iclass 39, count 2 2006.252.07:35:02.05#ibcon#read 5, iclass 39, count 2 2006.252.07:35:02.05#ibcon#about to read 6, iclass 39, count 2 2006.252.07:35:02.05#ibcon#read 6, iclass 39, count 2 2006.252.07:35:02.05#ibcon#end of sib2, iclass 39, count 2 2006.252.07:35:02.05#ibcon#*mode == 0, iclass 39, count 2 2006.252.07:35:02.05#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.252.07:35:02.05#ibcon#[27=AT05-04\r\n] 2006.252.07:35:02.05#ibcon#*before write, iclass 39, count 2 2006.252.07:35:02.05#ibcon#enter sib2, iclass 39, count 2 2006.252.07:35:02.05#ibcon#flushed, iclass 39, count 2 2006.252.07:35:02.05#ibcon#about to write, iclass 39, count 2 2006.252.07:35:02.05#ibcon#wrote, iclass 39, count 2 2006.252.07:35:02.05#ibcon#about to read 3, iclass 39, count 2 2006.252.07:35:02.08#ibcon#read 3, iclass 39, count 2 2006.252.07:35:02.08#ibcon#about to read 4, iclass 39, count 2 2006.252.07:35:02.08#ibcon#read 4, iclass 39, count 2 2006.252.07:35:02.08#ibcon#about to read 5, iclass 39, count 2 2006.252.07:35:02.08#ibcon#read 5, iclass 39, count 2 2006.252.07:35:02.08#ibcon#about to read 6, iclass 39, count 2 2006.252.07:35:02.08#ibcon#read 6, iclass 39, count 2 2006.252.07:35:02.08#ibcon#end of sib2, iclass 39, count 2 2006.252.07:35:02.08#ibcon#*after write, iclass 39, count 2 2006.252.07:35:02.08#ibcon#*before return 0, iclass 39, count 2 2006.252.07:35:02.08#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.252.07:35:02.08#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.252.07:35:02.08#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.252.07:35:02.08#ibcon#ireg 7 cls_cnt 0 2006.252.07:35:02.08#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.252.07:35:02.20#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.252.07:35:02.20#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.252.07:35:02.20#ibcon#enter wrdev, iclass 39, count 0 2006.252.07:35:02.20#ibcon#first serial, iclass 39, count 0 2006.252.07:35:02.20#ibcon#enter sib2, iclass 39, count 0 2006.252.07:35:02.20#ibcon#flushed, iclass 39, count 0 2006.252.07:35:02.20#ibcon#about to write, iclass 39, count 0 2006.252.07:35:02.20#ibcon#wrote, iclass 39, count 0 2006.252.07:35:02.20#ibcon#about to read 3, iclass 39, count 0 2006.252.07:35:02.22#ibcon#read 3, iclass 39, count 0 2006.252.07:35:02.22#ibcon#about to read 4, iclass 39, count 0 2006.252.07:35:02.22#ibcon#read 4, iclass 39, count 0 2006.252.07:35:02.22#ibcon#about to read 5, iclass 39, count 0 2006.252.07:35:02.22#ibcon#read 5, iclass 39, count 0 2006.252.07:35:02.22#ibcon#about to read 6, iclass 39, count 0 2006.252.07:35:02.22#ibcon#read 6, iclass 39, count 0 2006.252.07:35:02.22#ibcon#end of sib2, iclass 39, count 0 2006.252.07:35:02.22#ibcon#*mode == 0, iclass 39, count 0 2006.252.07:35:02.22#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.252.07:35:02.22#ibcon#[27=USB\r\n] 2006.252.07:35:02.22#ibcon#*before write, iclass 39, count 0 2006.252.07:35:02.22#ibcon#enter sib2, iclass 39, count 0 2006.252.07:35:02.22#ibcon#flushed, iclass 39, count 0 2006.252.07:35:02.22#ibcon#about to write, iclass 39, count 0 2006.252.07:35:02.22#ibcon#wrote, iclass 39, count 0 2006.252.07:35:02.22#ibcon#about to read 3, iclass 39, count 0 2006.252.07:35:02.25#ibcon#read 3, iclass 39, count 0 2006.252.07:35:02.25#ibcon#about to read 4, iclass 39, count 0 2006.252.07:35:02.25#ibcon#read 4, iclass 39, count 0 2006.252.07:35:02.25#ibcon#about to read 5, iclass 39, count 0 2006.252.07:35:02.25#ibcon#read 5, iclass 39, count 0 2006.252.07:35:02.25#ibcon#about to read 6, iclass 39, count 0 2006.252.07:35:02.25#ibcon#read 6, iclass 39, count 0 2006.252.07:35:02.25#ibcon#end of sib2, iclass 39, count 0 2006.252.07:35:02.25#ibcon#*after write, iclass 39, count 0 2006.252.07:35:02.25#ibcon#*before return 0, iclass 39, count 0 2006.252.07:35:02.25#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.252.07:35:02.25#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.252.07:35:02.25#ibcon#about to clear, iclass 39 cls_cnt 0 2006.252.07:35:02.25#ibcon#cleared, iclass 39 cls_cnt 0 2006.252.07:35:02.25$vc4f8/vblo=6,752.99 2006.252.07:35:02.25#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.252.07:35:02.25#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.252.07:35:02.25#ibcon#ireg 17 cls_cnt 0 2006.252.07:35:02.25#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.252.07:35:02.25#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.252.07:35:02.25#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.252.07:35:02.25#ibcon#enter wrdev, iclass 3, count 0 2006.252.07:35:02.25#ibcon#first serial, iclass 3, count 0 2006.252.07:35:02.25#ibcon#enter sib2, iclass 3, count 0 2006.252.07:35:02.25#ibcon#flushed, iclass 3, count 0 2006.252.07:35:02.25#ibcon#about to write, iclass 3, count 0 2006.252.07:35:02.25#ibcon#wrote, iclass 3, count 0 2006.252.07:35:02.25#ibcon#about to read 3, iclass 3, count 0 2006.252.07:35:02.27#ibcon#read 3, iclass 3, count 0 2006.252.07:35:02.27#ibcon#about to read 4, iclass 3, count 0 2006.252.07:35:02.27#ibcon#read 4, iclass 3, count 0 2006.252.07:35:02.27#ibcon#about to read 5, iclass 3, count 0 2006.252.07:35:02.27#ibcon#read 5, iclass 3, count 0 2006.252.07:35:02.27#ibcon#about to read 6, iclass 3, count 0 2006.252.07:35:02.27#ibcon#read 6, iclass 3, count 0 2006.252.07:35:02.27#ibcon#end of sib2, iclass 3, count 0 2006.252.07:35:02.27#ibcon#*mode == 0, iclass 3, count 0 2006.252.07:35:02.27#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.252.07:35:02.27#ibcon#[28=FRQ=06,752.99\r\n] 2006.252.07:35:02.27#ibcon#*before write, iclass 3, count 0 2006.252.07:35:02.27#ibcon#enter sib2, iclass 3, count 0 2006.252.07:35:02.27#ibcon#flushed, iclass 3, count 0 2006.252.07:35:02.27#ibcon#about to write, iclass 3, count 0 2006.252.07:35:02.27#ibcon#wrote, iclass 3, count 0 2006.252.07:35:02.27#ibcon#about to read 3, iclass 3, count 0 2006.252.07:35:02.31#ibcon#read 3, iclass 3, count 0 2006.252.07:35:02.31#ibcon#about to read 4, iclass 3, count 0 2006.252.07:35:02.31#ibcon#read 4, iclass 3, count 0 2006.252.07:35:02.31#ibcon#about to read 5, iclass 3, count 0 2006.252.07:35:02.31#ibcon#read 5, iclass 3, count 0 2006.252.07:35:02.31#ibcon#about to read 6, iclass 3, count 0 2006.252.07:35:02.31#ibcon#read 6, iclass 3, count 0 2006.252.07:35:02.31#ibcon#end of sib2, iclass 3, count 0 2006.252.07:35:02.31#ibcon#*after write, iclass 3, count 0 2006.252.07:35:02.31#ibcon#*before return 0, iclass 3, count 0 2006.252.07:35:02.31#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.252.07:35:02.31#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.252.07:35:02.31#ibcon#about to clear, iclass 3 cls_cnt 0 2006.252.07:35:02.31#ibcon#cleared, iclass 3 cls_cnt 0 2006.252.07:35:02.31$vc4f8/vb=6,4 2006.252.07:35:02.31#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.252.07:35:02.31#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.252.07:35:02.31#ibcon#ireg 11 cls_cnt 2 2006.252.07:35:02.31#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.252.07:35:02.37#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.252.07:35:02.37#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.252.07:35:02.37#ibcon#enter wrdev, iclass 5, count 2 2006.252.07:35:02.37#ibcon#first serial, iclass 5, count 2 2006.252.07:35:02.37#ibcon#enter sib2, iclass 5, count 2 2006.252.07:35:02.37#ibcon#flushed, iclass 5, count 2 2006.252.07:35:02.37#ibcon#about to write, iclass 5, count 2 2006.252.07:35:02.37#ibcon#wrote, iclass 5, count 2 2006.252.07:35:02.37#ibcon#about to read 3, iclass 5, count 2 2006.252.07:35:02.39#ibcon#read 3, iclass 5, count 2 2006.252.07:35:02.39#ibcon#about to read 4, iclass 5, count 2 2006.252.07:35:02.39#ibcon#read 4, iclass 5, count 2 2006.252.07:35:02.39#ibcon#about to read 5, iclass 5, count 2 2006.252.07:35:02.39#ibcon#read 5, iclass 5, count 2 2006.252.07:35:02.39#ibcon#about to read 6, iclass 5, count 2 2006.252.07:35:02.39#ibcon#read 6, iclass 5, count 2 2006.252.07:35:02.39#ibcon#end of sib2, iclass 5, count 2 2006.252.07:35:02.39#ibcon#*mode == 0, iclass 5, count 2 2006.252.07:35:02.39#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.252.07:35:02.39#ibcon#[27=AT06-04\r\n] 2006.252.07:35:02.39#ibcon#*before write, iclass 5, count 2 2006.252.07:35:02.39#ibcon#enter sib2, iclass 5, count 2 2006.252.07:35:02.39#ibcon#flushed, iclass 5, count 2 2006.252.07:35:02.39#ibcon#about to write, iclass 5, count 2 2006.252.07:35:02.39#ibcon#wrote, iclass 5, count 2 2006.252.07:35:02.39#ibcon#about to read 3, iclass 5, count 2 2006.252.07:35:02.42#ibcon#read 3, iclass 5, count 2 2006.252.07:35:02.42#ibcon#about to read 4, iclass 5, count 2 2006.252.07:35:02.42#ibcon#read 4, iclass 5, count 2 2006.252.07:35:02.42#ibcon#about to read 5, iclass 5, count 2 2006.252.07:35:02.42#ibcon#read 5, iclass 5, count 2 2006.252.07:35:02.42#ibcon#about to read 6, iclass 5, count 2 2006.252.07:35:02.42#ibcon#read 6, iclass 5, count 2 2006.252.07:35:02.42#ibcon#end of sib2, iclass 5, count 2 2006.252.07:35:02.42#ibcon#*after write, iclass 5, count 2 2006.252.07:35:02.42#ibcon#*before return 0, iclass 5, count 2 2006.252.07:35:02.42#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.252.07:35:02.42#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.252.07:35:02.42#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.252.07:35:02.42#ibcon#ireg 7 cls_cnt 0 2006.252.07:35:02.42#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.252.07:35:02.54#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.252.07:35:02.54#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.252.07:35:02.54#ibcon#enter wrdev, iclass 5, count 0 2006.252.07:35:02.54#ibcon#first serial, iclass 5, count 0 2006.252.07:35:02.54#ibcon#enter sib2, iclass 5, count 0 2006.252.07:35:02.54#ibcon#flushed, iclass 5, count 0 2006.252.07:35:02.54#ibcon#about to write, iclass 5, count 0 2006.252.07:35:02.54#ibcon#wrote, iclass 5, count 0 2006.252.07:35:02.54#ibcon#about to read 3, iclass 5, count 0 2006.252.07:35:02.56#ibcon#read 3, iclass 5, count 0 2006.252.07:35:02.56#ibcon#about to read 4, iclass 5, count 0 2006.252.07:35:02.56#ibcon#read 4, iclass 5, count 0 2006.252.07:35:02.56#ibcon#about to read 5, iclass 5, count 0 2006.252.07:35:02.56#ibcon#read 5, iclass 5, count 0 2006.252.07:35:02.56#ibcon#about to read 6, iclass 5, count 0 2006.252.07:35:02.56#ibcon#read 6, iclass 5, count 0 2006.252.07:35:02.56#ibcon#end of sib2, iclass 5, count 0 2006.252.07:35:02.56#ibcon#*mode == 0, iclass 5, count 0 2006.252.07:35:02.56#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.252.07:35:02.56#ibcon#[27=USB\r\n] 2006.252.07:35:02.56#ibcon#*before write, iclass 5, count 0 2006.252.07:35:02.56#ibcon#enter sib2, iclass 5, count 0 2006.252.07:35:02.56#ibcon#flushed, iclass 5, count 0 2006.252.07:35:02.56#ibcon#about to write, iclass 5, count 0 2006.252.07:35:02.56#ibcon#wrote, iclass 5, count 0 2006.252.07:35:02.56#ibcon#about to read 3, iclass 5, count 0 2006.252.07:35:02.59#ibcon#read 3, iclass 5, count 0 2006.252.07:35:02.59#ibcon#about to read 4, iclass 5, count 0 2006.252.07:35:02.59#ibcon#read 4, iclass 5, count 0 2006.252.07:35:02.59#ibcon#about to read 5, iclass 5, count 0 2006.252.07:35:02.59#ibcon#read 5, iclass 5, count 0 2006.252.07:35:02.59#ibcon#about to read 6, iclass 5, count 0 2006.252.07:35:02.59#ibcon#read 6, iclass 5, count 0 2006.252.07:35:02.59#ibcon#end of sib2, iclass 5, count 0 2006.252.07:35:02.59#ibcon#*after write, iclass 5, count 0 2006.252.07:35:02.59#ibcon#*before return 0, iclass 5, count 0 2006.252.07:35:02.59#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.252.07:35:02.59#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.252.07:35:02.59#ibcon#about to clear, iclass 5 cls_cnt 0 2006.252.07:35:02.59#ibcon#cleared, iclass 5 cls_cnt 0 2006.252.07:35:02.59$vc4f8/vabw=wide 2006.252.07:35:02.59#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.252.07:35:02.59#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.252.07:35:02.59#ibcon#ireg 8 cls_cnt 0 2006.252.07:35:02.59#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.252.07:35:02.59#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.252.07:35:02.59#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.252.07:35:02.59#ibcon#enter wrdev, iclass 7, count 0 2006.252.07:35:02.59#ibcon#first serial, iclass 7, count 0 2006.252.07:35:02.59#ibcon#enter sib2, iclass 7, count 0 2006.252.07:35:02.59#ibcon#flushed, iclass 7, count 0 2006.252.07:35:02.59#ibcon#about to write, iclass 7, count 0 2006.252.07:35:02.59#ibcon#wrote, iclass 7, count 0 2006.252.07:35:02.59#ibcon#about to read 3, iclass 7, count 0 2006.252.07:35:02.61#ibcon#read 3, iclass 7, count 0 2006.252.07:35:02.61#ibcon#about to read 4, iclass 7, count 0 2006.252.07:35:02.61#ibcon#read 4, iclass 7, count 0 2006.252.07:35:02.61#ibcon#about to read 5, iclass 7, count 0 2006.252.07:35:02.61#ibcon#read 5, iclass 7, count 0 2006.252.07:35:02.61#ibcon#about to read 6, iclass 7, count 0 2006.252.07:35:02.61#ibcon#read 6, iclass 7, count 0 2006.252.07:35:02.61#ibcon#end of sib2, iclass 7, count 0 2006.252.07:35:02.61#ibcon#*mode == 0, iclass 7, count 0 2006.252.07:35:02.61#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.252.07:35:02.61#ibcon#[25=BW32\r\n] 2006.252.07:35:02.61#ibcon#*before write, iclass 7, count 0 2006.252.07:35:02.61#ibcon#enter sib2, iclass 7, count 0 2006.252.07:35:02.61#ibcon#flushed, iclass 7, count 0 2006.252.07:35:02.61#ibcon#about to write, iclass 7, count 0 2006.252.07:35:02.61#ibcon#wrote, iclass 7, count 0 2006.252.07:35:02.61#ibcon#about to read 3, iclass 7, count 0 2006.252.07:35:02.64#ibcon#read 3, iclass 7, count 0 2006.252.07:35:02.64#ibcon#about to read 4, iclass 7, count 0 2006.252.07:35:02.64#ibcon#read 4, iclass 7, count 0 2006.252.07:35:02.64#ibcon#about to read 5, iclass 7, count 0 2006.252.07:35:02.64#ibcon#read 5, iclass 7, count 0 2006.252.07:35:02.64#ibcon#about to read 6, iclass 7, count 0 2006.252.07:35:02.64#ibcon#read 6, iclass 7, count 0 2006.252.07:35:02.64#ibcon#end of sib2, iclass 7, count 0 2006.252.07:35:02.64#ibcon#*after write, iclass 7, count 0 2006.252.07:35:02.64#ibcon#*before return 0, iclass 7, count 0 2006.252.07:35:02.64#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.252.07:35:02.64#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.252.07:35:02.64#ibcon#about to clear, iclass 7 cls_cnt 0 2006.252.07:35:02.64#ibcon#cleared, iclass 7 cls_cnt 0 2006.252.07:35:02.64$vc4f8/vbbw=wide 2006.252.07:35:02.64#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.252.07:35:02.64#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.252.07:35:02.64#ibcon#ireg 8 cls_cnt 0 2006.252.07:35:02.64#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.252.07:35:02.71#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.252.07:35:02.71#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.252.07:35:02.71#ibcon#enter wrdev, iclass 11, count 0 2006.252.07:35:02.71#ibcon#first serial, iclass 11, count 0 2006.252.07:35:02.71#ibcon#enter sib2, iclass 11, count 0 2006.252.07:35:02.71#ibcon#flushed, iclass 11, count 0 2006.252.07:35:02.71#ibcon#about to write, iclass 11, count 0 2006.252.07:35:02.71#ibcon#wrote, iclass 11, count 0 2006.252.07:35:02.71#ibcon#about to read 3, iclass 11, count 0 2006.252.07:35:02.73#ibcon#read 3, iclass 11, count 0 2006.252.07:35:02.73#ibcon#about to read 4, iclass 11, count 0 2006.252.07:35:02.73#ibcon#read 4, iclass 11, count 0 2006.252.07:35:02.73#ibcon#about to read 5, iclass 11, count 0 2006.252.07:35:02.73#ibcon#read 5, iclass 11, count 0 2006.252.07:35:02.73#ibcon#about to read 6, iclass 11, count 0 2006.252.07:35:02.73#ibcon#read 6, iclass 11, count 0 2006.252.07:35:02.73#ibcon#end of sib2, iclass 11, count 0 2006.252.07:35:02.73#ibcon#*mode == 0, iclass 11, count 0 2006.252.07:35:02.73#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.252.07:35:02.73#ibcon#[27=BW32\r\n] 2006.252.07:35:02.73#ibcon#*before write, iclass 11, count 0 2006.252.07:35:02.73#ibcon#enter sib2, iclass 11, count 0 2006.252.07:35:02.73#ibcon#flushed, iclass 11, count 0 2006.252.07:35:02.73#ibcon#about to write, iclass 11, count 0 2006.252.07:35:02.73#ibcon#wrote, iclass 11, count 0 2006.252.07:35:02.73#ibcon#about to read 3, iclass 11, count 0 2006.252.07:35:02.76#ibcon#read 3, iclass 11, count 0 2006.252.07:35:02.76#ibcon#about to read 4, iclass 11, count 0 2006.252.07:35:02.76#ibcon#read 4, iclass 11, count 0 2006.252.07:35:02.76#ibcon#about to read 5, iclass 11, count 0 2006.252.07:35:02.76#ibcon#read 5, iclass 11, count 0 2006.252.07:35:02.76#ibcon#about to read 6, iclass 11, count 0 2006.252.07:35:02.76#ibcon#read 6, iclass 11, count 0 2006.252.07:35:02.76#ibcon#end of sib2, iclass 11, count 0 2006.252.07:35:02.76#ibcon#*after write, iclass 11, count 0 2006.252.07:35:02.76#ibcon#*before return 0, iclass 11, count 0 2006.252.07:35:02.76#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.252.07:35:02.76#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.252.07:35:02.76#ibcon#about to clear, iclass 11 cls_cnt 0 2006.252.07:35:02.76#ibcon#cleared, iclass 11 cls_cnt 0 2006.252.07:35:02.76$4f8m12a/ifd4f 2006.252.07:35:02.76$ifd4f/lo= 2006.252.07:35:02.76$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.252.07:35:02.76$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.252.07:35:02.76$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.252.07:35:02.76$ifd4f/patch= 2006.252.07:35:02.76$ifd4f/patch=lo1,a1,a2,a3,a4 2006.252.07:35:02.76$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.252.07:35:02.76$ifd4f/patch=lo3,a5,a6,a7,a8 2006.252.07:35:02.76$4f8m12a/"form=m,16.000,1:2 2006.252.07:35:02.76$4f8m12a/"tpicd 2006.252.07:35:02.76$4f8m12a/echo=off 2006.252.07:35:02.76$4f8m12a/xlog=off 2006.252.07:35:02.76:!2006.252.07:35:50 2006.252.07:35:32.14#trakl#Source acquired 2006.252.07:35:33.13#flagr#flagr/antenna,acquired 2006.252.07:35:50.00:preob 2006.252.07:35:50.13/onsource/TRACKING 2006.252.07:35:50.13:!2006.252.07:36:00 2006.252.07:36:00.00:data_valid=on 2006.252.07:36:00.00:midob 2006.252.07:36:00.13/onsource/TRACKING 2006.252.07:36:00.13/wx/27.47,1011.3,90 2006.252.07:36:00.32/cable/+6.4071E-03 2006.252.07:36:01.41/va/01,08,usb,yes,32,34 2006.252.07:36:01.41/va/02,07,usb,yes,32,34 2006.252.07:36:01.41/va/03,06,usb,yes,34,34 2006.252.07:36:01.41/va/04,07,usb,yes,33,36 2006.252.07:36:01.41/va/05,07,usb,yes,35,38 2006.252.07:36:01.41/va/06,07,usb,yes,31,31 2006.252.07:36:01.41/va/07,07,usb,yes,30,30 2006.252.07:36:01.41/va/08,07,usb,yes,33,32 2006.252.07:36:01.64/valo/01,532.99,yes,locked 2006.252.07:36:01.64/valo/02,572.99,yes,locked 2006.252.07:36:01.64/valo/03,672.99,yes,locked 2006.252.07:36:01.64/valo/04,832.99,yes,locked 2006.252.07:36:01.64/valo/05,652.99,yes,locked 2006.252.07:36:01.64/valo/06,772.99,yes,locked 2006.252.07:36:01.64/valo/07,832.99,yes,locked 2006.252.07:36:01.64/valo/08,852.99,yes,locked 2006.252.07:36:02.73/vb/01,04,usb,yes,30,29 2006.252.07:36:02.73/vb/02,05,usb,yes,28,29 2006.252.07:36:02.73/vb/03,04,usb,yes,28,32 2006.252.07:36:02.73/vb/04,04,usb,yes,29,29 2006.252.07:36:02.73/vb/05,04,usb,yes,28,32 2006.252.07:36:02.73/vb/06,04,usb,yes,29,32 2006.252.07:36:02.73/vb/07,04,usb,yes,31,31 2006.252.07:36:02.73/vb/08,04,usb,yes,28,32 2006.252.07:36:02.96/vblo/01,632.99,yes,locked 2006.252.07:36:02.96/vblo/02,640.99,yes,locked 2006.252.07:36:02.96/vblo/03,656.99,yes,locked 2006.252.07:36:02.96/vblo/04,712.99,yes,locked 2006.252.07:36:02.96/vblo/05,744.99,yes,locked 2006.252.07:36:02.96/vblo/06,752.99,yes,locked 2006.252.07:36:02.96/vblo/07,734.99,yes,locked 2006.252.07:36:02.96/vblo/08,744.99,yes,locked 2006.252.07:36:03.11/vabw/8 2006.252.07:36:03.26/vbbw/8 2006.252.07:36:03.35/xfe/off,on,14.0 2006.252.07:36:03.73/ifatt/23,28,28,28 2006.252.07:36:04.08/fmout-gps/S +4.72E-07 2006.252.07:36:04.12:!2006.252.07:37:00 2006.252.07:37:00.02:data_valid=off 2006.252.07:37:00.02:postob 2006.252.07:37:00.12/cable/+6.4085E-03 2006.252.07:37:00.12/wx/27.46,1011.3,90 2006.252.07:37:01.08/fmout-gps/S +4.73E-07 2006.252.07:37:01.08:scan_name=252-0737,k06252,60 2006.252.07:37:01.08:source=0804+499,080839.67,495036.5,2000.0,ccw 2006.252.07:37:01.16#flagr#flagr/antenna,new-source 2006.252.07:37:02.14:checkk5 2006.252.07:37:02.51/chk_autoobs//k5ts1/ autoobs is running! 2006.252.07:37:02.89/chk_autoobs//k5ts2/ autoobs is running! 2006.252.07:37:03.27/chk_autoobs//k5ts3/ autoobs is running! 2006.252.07:37:03.64/chk_autoobs//k5ts4/ autoobs is running! 2006.252.07:37:04.01/chk_obsdata//k5ts1/T2520736??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.07:37:04.38/chk_obsdata//k5ts2/T2520736??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.07:37:04.76/chk_obsdata//k5ts3/T2520736??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.07:37:05.13/chk_obsdata//k5ts4/T2520736??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.07:37:05.83/k5log//k5ts1_log_newline 2006.252.07:37:06.52/k5log//k5ts2_log_newline 2006.252.07:37:07.22/k5log//k5ts3_log_newline 2006.252.07:37:07.91/k5log//k5ts4_log_newline 2006.252.07:37:07.93/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.252.07:37:07.93:4f8m12a=1 2006.252.07:37:07.93$4f8m12a/echo=on 2006.252.07:37:07.93$4f8m12a/pcalon 2006.252.07:37:07.93$pcalon/"no phase cal control is implemented here 2006.252.07:37:07.93$4f8m12a/"tpicd=stop 2006.252.07:37:07.93$4f8m12a/vc4f8 2006.252.07:37:07.93$vc4f8/valo=1,532.99 2006.252.07:37:07.94#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.252.07:37:07.94#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.252.07:37:07.94#ibcon#ireg 17 cls_cnt 0 2006.252.07:37:07.94#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.252.07:37:07.94#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.252.07:37:07.94#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.252.07:37:07.94#ibcon#enter wrdev, iclass 30, count 0 2006.252.07:37:07.94#ibcon#first serial, iclass 30, count 0 2006.252.07:37:07.94#ibcon#enter sib2, iclass 30, count 0 2006.252.07:37:07.94#ibcon#flushed, iclass 30, count 0 2006.252.07:37:07.94#ibcon#about to write, iclass 30, count 0 2006.252.07:37:07.94#ibcon#wrote, iclass 30, count 0 2006.252.07:37:07.94#ibcon#about to read 3, iclass 30, count 0 2006.252.07:37:07.98#ibcon#read 3, iclass 30, count 0 2006.252.07:37:07.98#ibcon#about to read 4, iclass 30, count 0 2006.252.07:37:07.98#ibcon#read 4, iclass 30, count 0 2006.252.07:37:07.98#ibcon#about to read 5, iclass 30, count 0 2006.252.07:37:07.98#ibcon#read 5, iclass 30, count 0 2006.252.07:37:07.98#ibcon#about to read 6, iclass 30, count 0 2006.252.07:37:07.98#ibcon#read 6, iclass 30, count 0 2006.252.07:37:07.98#ibcon#end of sib2, iclass 30, count 0 2006.252.07:37:07.98#ibcon#*mode == 0, iclass 30, count 0 2006.252.07:37:07.98#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.252.07:37:07.98#ibcon#[26=FRQ=01,532.99\r\n] 2006.252.07:37:07.98#ibcon#*before write, iclass 30, count 0 2006.252.07:37:07.98#ibcon#enter sib2, iclass 30, count 0 2006.252.07:37:07.98#ibcon#flushed, iclass 30, count 0 2006.252.07:37:07.98#ibcon#about to write, iclass 30, count 0 2006.252.07:37:07.98#ibcon#wrote, iclass 30, count 0 2006.252.07:37:07.98#ibcon#about to read 3, iclass 30, count 0 2006.252.07:37:08.02#ibcon#read 3, iclass 30, count 0 2006.252.07:37:08.02#ibcon#about to read 4, iclass 30, count 0 2006.252.07:37:08.02#ibcon#read 4, iclass 30, count 0 2006.252.07:37:08.02#ibcon#about to read 5, iclass 30, count 0 2006.252.07:37:08.02#ibcon#read 5, iclass 30, count 0 2006.252.07:37:08.02#ibcon#about to read 6, iclass 30, count 0 2006.252.07:37:08.02#ibcon#read 6, iclass 30, count 0 2006.252.07:37:08.02#ibcon#end of sib2, iclass 30, count 0 2006.252.07:37:08.02#ibcon#*after write, iclass 30, count 0 2006.252.07:37:08.02#ibcon#*before return 0, iclass 30, count 0 2006.252.07:37:08.02#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.252.07:37:08.02#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.252.07:37:08.02#ibcon#about to clear, iclass 30 cls_cnt 0 2006.252.07:37:08.02#ibcon#cleared, iclass 30 cls_cnt 0 2006.252.07:37:08.03$vc4f8/va=1,8 2006.252.07:37:08.03#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.252.07:37:08.03#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.252.07:37:08.03#ibcon#ireg 11 cls_cnt 2 2006.252.07:37:08.03#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.252.07:37:08.03#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.252.07:37:08.03#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.252.07:37:08.03#ibcon#enter wrdev, iclass 32, count 2 2006.252.07:37:08.03#ibcon#first serial, iclass 32, count 2 2006.252.07:37:08.03#ibcon#enter sib2, iclass 32, count 2 2006.252.07:37:08.03#ibcon#flushed, iclass 32, count 2 2006.252.07:37:08.03#ibcon#about to write, iclass 32, count 2 2006.252.07:37:08.03#ibcon#wrote, iclass 32, count 2 2006.252.07:37:08.03#ibcon#about to read 3, iclass 32, count 2 2006.252.07:37:08.04#ibcon#read 3, iclass 32, count 2 2006.252.07:37:08.04#ibcon#about to read 4, iclass 32, count 2 2006.252.07:37:08.04#ibcon#read 4, iclass 32, count 2 2006.252.07:37:08.04#ibcon#about to read 5, iclass 32, count 2 2006.252.07:37:08.04#ibcon#read 5, iclass 32, count 2 2006.252.07:37:08.04#ibcon#about to read 6, iclass 32, count 2 2006.252.07:37:08.04#ibcon#read 6, iclass 32, count 2 2006.252.07:37:08.04#ibcon#end of sib2, iclass 32, count 2 2006.252.07:37:08.04#ibcon#*mode == 0, iclass 32, count 2 2006.252.07:37:08.05#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.252.07:37:08.05#ibcon#[25=AT01-08\r\n] 2006.252.07:37:08.05#ibcon#*before write, iclass 32, count 2 2006.252.07:37:08.05#ibcon#enter sib2, iclass 32, count 2 2006.252.07:37:08.05#ibcon#flushed, iclass 32, count 2 2006.252.07:37:08.05#ibcon#about to write, iclass 32, count 2 2006.252.07:37:08.05#ibcon#wrote, iclass 32, count 2 2006.252.07:37:08.05#ibcon#about to read 3, iclass 32, count 2 2006.252.07:37:08.07#ibcon#read 3, iclass 32, count 2 2006.252.07:37:08.07#ibcon#about to read 4, iclass 32, count 2 2006.252.07:37:08.07#ibcon#read 4, iclass 32, count 2 2006.252.07:37:08.07#ibcon#about to read 5, iclass 32, count 2 2006.252.07:37:08.07#ibcon#read 5, iclass 32, count 2 2006.252.07:37:08.07#ibcon#about to read 6, iclass 32, count 2 2006.252.07:37:08.07#ibcon#read 6, iclass 32, count 2 2006.252.07:37:08.07#ibcon#end of sib2, iclass 32, count 2 2006.252.07:37:08.07#ibcon#*after write, iclass 32, count 2 2006.252.07:37:08.07#ibcon#*before return 0, iclass 32, count 2 2006.252.07:37:08.08#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.252.07:37:08.08#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.252.07:37:08.08#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.252.07:37:08.08#ibcon#ireg 7 cls_cnt 0 2006.252.07:37:08.08#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.252.07:37:08.19#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.252.07:37:08.19#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.252.07:37:08.19#ibcon#enter wrdev, iclass 32, count 0 2006.252.07:37:08.19#ibcon#first serial, iclass 32, count 0 2006.252.07:37:08.19#ibcon#enter sib2, iclass 32, count 0 2006.252.07:37:08.19#ibcon#flushed, iclass 32, count 0 2006.252.07:37:08.19#ibcon#about to write, iclass 32, count 0 2006.252.07:37:08.19#ibcon#wrote, iclass 32, count 0 2006.252.07:37:08.19#ibcon#about to read 3, iclass 32, count 0 2006.252.07:37:08.21#ibcon#read 3, iclass 32, count 0 2006.252.07:37:08.21#ibcon#about to read 4, iclass 32, count 0 2006.252.07:37:08.21#ibcon#read 4, iclass 32, count 0 2006.252.07:37:08.21#ibcon#about to read 5, iclass 32, count 0 2006.252.07:37:08.21#ibcon#read 5, iclass 32, count 0 2006.252.07:37:08.21#ibcon#about to read 6, iclass 32, count 0 2006.252.07:37:08.21#ibcon#read 6, iclass 32, count 0 2006.252.07:37:08.21#ibcon#end of sib2, iclass 32, count 0 2006.252.07:37:08.21#ibcon#*mode == 0, iclass 32, count 0 2006.252.07:37:08.21#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.252.07:37:08.21#ibcon#[25=USB\r\n] 2006.252.07:37:08.21#ibcon#*before write, iclass 32, count 0 2006.252.07:37:08.21#ibcon#enter sib2, iclass 32, count 0 2006.252.07:37:08.21#ibcon#flushed, iclass 32, count 0 2006.252.07:37:08.22#ibcon#about to write, iclass 32, count 0 2006.252.07:37:08.22#ibcon#wrote, iclass 32, count 0 2006.252.07:37:08.22#ibcon#about to read 3, iclass 32, count 0 2006.252.07:37:08.24#ibcon#read 3, iclass 32, count 0 2006.252.07:37:08.24#ibcon#about to read 4, iclass 32, count 0 2006.252.07:37:08.24#ibcon#read 4, iclass 32, count 0 2006.252.07:37:08.24#ibcon#about to read 5, iclass 32, count 0 2006.252.07:37:08.24#ibcon#read 5, iclass 32, count 0 2006.252.07:37:08.24#ibcon#about to read 6, iclass 32, count 0 2006.252.07:37:08.24#ibcon#read 6, iclass 32, count 0 2006.252.07:37:08.24#ibcon#end of sib2, iclass 32, count 0 2006.252.07:37:08.24#ibcon#*after write, iclass 32, count 0 2006.252.07:37:08.24#ibcon#*before return 0, iclass 32, count 0 2006.252.07:37:08.24#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.252.07:37:08.24#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.252.07:37:08.24#ibcon#about to clear, iclass 32 cls_cnt 0 2006.252.07:37:08.25#ibcon#cleared, iclass 32 cls_cnt 0 2006.252.07:37:08.25$vc4f8/valo=2,572.99 2006.252.07:37:08.25#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.252.07:37:08.25#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.252.07:37:08.25#ibcon#ireg 17 cls_cnt 0 2006.252.07:37:08.25#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.252.07:37:08.25#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.252.07:37:08.25#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.252.07:37:08.25#ibcon#enter wrdev, iclass 34, count 0 2006.252.07:37:08.25#ibcon#first serial, iclass 34, count 0 2006.252.07:37:08.25#ibcon#enter sib2, iclass 34, count 0 2006.252.07:37:08.25#ibcon#flushed, iclass 34, count 0 2006.252.07:37:08.25#ibcon#about to write, iclass 34, count 0 2006.252.07:37:08.25#ibcon#wrote, iclass 34, count 0 2006.252.07:37:08.25#ibcon#about to read 3, iclass 34, count 0 2006.252.07:37:08.27#ibcon#read 3, iclass 34, count 0 2006.252.07:37:08.27#ibcon#about to read 4, iclass 34, count 0 2006.252.07:37:08.27#ibcon#read 4, iclass 34, count 0 2006.252.07:37:08.27#ibcon#about to read 5, iclass 34, count 0 2006.252.07:37:08.27#ibcon#read 5, iclass 34, count 0 2006.252.07:37:08.27#ibcon#about to read 6, iclass 34, count 0 2006.252.07:37:08.27#ibcon#read 6, iclass 34, count 0 2006.252.07:37:08.27#ibcon#end of sib2, iclass 34, count 0 2006.252.07:37:08.27#ibcon#*mode == 0, iclass 34, count 0 2006.252.07:37:08.27#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.252.07:37:08.27#ibcon#[26=FRQ=02,572.99\r\n] 2006.252.07:37:08.27#ibcon#*before write, iclass 34, count 0 2006.252.07:37:08.27#ibcon#enter sib2, iclass 34, count 0 2006.252.07:37:08.27#ibcon#flushed, iclass 34, count 0 2006.252.07:37:08.27#ibcon#about to write, iclass 34, count 0 2006.252.07:37:08.27#ibcon#wrote, iclass 34, count 0 2006.252.07:37:08.27#ibcon#about to read 3, iclass 34, count 0 2006.252.07:37:08.31#ibcon#read 3, iclass 34, count 0 2006.252.07:37:08.31#ibcon#about to read 4, iclass 34, count 0 2006.252.07:37:08.31#ibcon#read 4, iclass 34, count 0 2006.252.07:37:08.31#ibcon#about to read 5, iclass 34, count 0 2006.252.07:37:08.31#ibcon#read 5, iclass 34, count 0 2006.252.07:37:08.31#ibcon#about to read 6, iclass 34, count 0 2006.252.07:37:08.31#ibcon#read 6, iclass 34, count 0 2006.252.07:37:08.31#ibcon#end of sib2, iclass 34, count 0 2006.252.07:37:08.31#ibcon#*after write, iclass 34, count 0 2006.252.07:37:08.31#ibcon#*before return 0, iclass 34, count 0 2006.252.07:37:08.32#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.252.07:37:08.32#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.252.07:37:08.32#ibcon#about to clear, iclass 34 cls_cnt 0 2006.252.07:37:08.32#ibcon#cleared, iclass 34 cls_cnt 0 2006.252.07:37:08.32$vc4f8/va=2,7 2006.252.07:37:08.32#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.252.07:37:08.32#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.252.07:37:08.32#ibcon#ireg 11 cls_cnt 2 2006.252.07:37:08.32#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.252.07:37:08.35#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.252.07:37:08.35#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.252.07:37:08.35#ibcon#enter wrdev, iclass 36, count 2 2006.252.07:37:08.35#ibcon#first serial, iclass 36, count 2 2006.252.07:37:08.35#ibcon#enter sib2, iclass 36, count 2 2006.252.07:37:08.35#ibcon#flushed, iclass 36, count 2 2006.252.07:37:08.35#ibcon#about to write, iclass 36, count 2 2006.252.07:37:08.35#ibcon#wrote, iclass 36, count 2 2006.252.07:37:08.35#ibcon#about to read 3, iclass 36, count 2 2006.252.07:37:08.38#ibcon#read 3, iclass 36, count 2 2006.252.07:37:08.38#ibcon#about to read 4, iclass 36, count 2 2006.252.07:37:08.38#ibcon#read 4, iclass 36, count 2 2006.252.07:37:08.38#ibcon#about to read 5, iclass 36, count 2 2006.252.07:37:08.38#ibcon#read 5, iclass 36, count 2 2006.252.07:37:08.38#ibcon#about to read 6, iclass 36, count 2 2006.252.07:37:08.38#ibcon#read 6, iclass 36, count 2 2006.252.07:37:08.38#ibcon#end of sib2, iclass 36, count 2 2006.252.07:37:08.38#ibcon#*mode == 0, iclass 36, count 2 2006.252.07:37:08.38#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.252.07:37:08.38#ibcon#[25=AT02-07\r\n] 2006.252.07:37:08.38#ibcon#*before write, iclass 36, count 2 2006.252.07:37:08.38#ibcon#enter sib2, iclass 36, count 2 2006.252.07:37:08.38#ibcon#flushed, iclass 36, count 2 2006.252.07:37:08.38#ibcon#about to write, iclass 36, count 2 2006.252.07:37:08.38#ibcon#wrote, iclass 36, count 2 2006.252.07:37:08.38#ibcon#about to read 3, iclass 36, count 2 2006.252.07:37:08.41#ibcon#read 3, iclass 36, count 2 2006.252.07:37:08.41#ibcon#about to read 4, iclass 36, count 2 2006.252.07:37:08.41#ibcon#read 4, iclass 36, count 2 2006.252.07:37:08.41#ibcon#about to read 5, iclass 36, count 2 2006.252.07:37:08.41#ibcon#read 5, iclass 36, count 2 2006.252.07:37:08.41#ibcon#about to read 6, iclass 36, count 2 2006.252.07:37:08.41#ibcon#read 6, iclass 36, count 2 2006.252.07:37:08.41#ibcon#end of sib2, iclass 36, count 2 2006.252.07:37:08.41#ibcon#*after write, iclass 36, count 2 2006.252.07:37:08.41#ibcon#*before return 0, iclass 36, count 2 2006.252.07:37:08.42#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.252.07:37:08.42#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.252.07:37:08.42#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.252.07:37:08.42#ibcon#ireg 7 cls_cnt 0 2006.252.07:37:08.42#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.252.07:37:08.53#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.252.07:37:08.53#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.252.07:37:08.53#ibcon#enter wrdev, iclass 36, count 0 2006.252.07:37:08.53#ibcon#first serial, iclass 36, count 0 2006.252.07:37:08.53#ibcon#enter sib2, iclass 36, count 0 2006.252.07:37:08.53#ibcon#flushed, iclass 36, count 0 2006.252.07:37:08.53#ibcon#about to write, iclass 36, count 0 2006.252.07:37:08.53#ibcon#wrote, iclass 36, count 0 2006.252.07:37:08.53#ibcon#about to read 3, iclass 36, count 0 2006.252.07:37:08.55#ibcon#read 3, iclass 36, count 0 2006.252.07:37:08.55#ibcon#about to read 4, iclass 36, count 0 2006.252.07:37:08.55#ibcon#read 4, iclass 36, count 0 2006.252.07:37:08.55#ibcon#about to read 5, iclass 36, count 0 2006.252.07:37:08.55#ibcon#read 5, iclass 36, count 0 2006.252.07:37:08.55#ibcon#about to read 6, iclass 36, count 0 2006.252.07:37:08.55#ibcon#read 6, iclass 36, count 0 2006.252.07:37:08.55#ibcon#end of sib2, iclass 36, count 0 2006.252.07:37:08.55#ibcon#*mode == 0, iclass 36, count 0 2006.252.07:37:08.55#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.252.07:37:08.55#ibcon#[25=USB\r\n] 2006.252.07:37:08.55#ibcon#*before write, iclass 36, count 0 2006.252.07:37:08.55#ibcon#enter sib2, iclass 36, count 0 2006.252.07:37:08.55#ibcon#flushed, iclass 36, count 0 2006.252.07:37:08.56#ibcon#about to write, iclass 36, count 0 2006.252.07:37:08.56#ibcon#wrote, iclass 36, count 0 2006.252.07:37:08.56#ibcon#about to read 3, iclass 36, count 0 2006.252.07:37:08.58#ibcon#read 3, iclass 36, count 0 2006.252.07:37:08.58#ibcon#about to read 4, iclass 36, count 0 2006.252.07:37:08.58#ibcon#read 4, iclass 36, count 0 2006.252.07:37:08.58#ibcon#about to read 5, iclass 36, count 0 2006.252.07:37:08.58#ibcon#read 5, iclass 36, count 0 2006.252.07:37:08.58#ibcon#about to read 6, iclass 36, count 0 2006.252.07:37:08.58#ibcon#read 6, iclass 36, count 0 2006.252.07:37:08.58#ibcon#end of sib2, iclass 36, count 0 2006.252.07:37:08.58#ibcon#*after write, iclass 36, count 0 2006.252.07:37:08.58#ibcon#*before return 0, iclass 36, count 0 2006.252.07:37:08.58#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.252.07:37:08.58#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.252.07:37:08.59#ibcon#about to clear, iclass 36 cls_cnt 0 2006.252.07:37:08.59#ibcon#cleared, iclass 36 cls_cnt 0 2006.252.07:37:08.59$vc4f8/valo=3,672.99 2006.252.07:37:08.59#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.252.07:37:08.59#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.252.07:37:08.59#ibcon#ireg 17 cls_cnt 0 2006.252.07:37:08.59#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.252.07:37:08.59#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.252.07:37:08.59#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.252.07:37:08.59#ibcon#enter wrdev, iclass 38, count 0 2006.252.07:37:08.59#ibcon#first serial, iclass 38, count 0 2006.252.07:37:08.59#ibcon#enter sib2, iclass 38, count 0 2006.252.07:37:08.59#ibcon#flushed, iclass 38, count 0 2006.252.07:37:08.59#ibcon#about to write, iclass 38, count 0 2006.252.07:37:08.59#ibcon#wrote, iclass 38, count 0 2006.252.07:37:08.59#ibcon#about to read 3, iclass 38, count 0 2006.252.07:37:08.61#ibcon#read 3, iclass 38, count 0 2006.252.07:37:08.61#ibcon#about to read 4, iclass 38, count 0 2006.252.07:37:08.61#ibcon#read 4, iclass 38, count 0 2006.252.07:37:08.61#ibcon#about to read 5, iclass 38, count 0 2006.252.07:37:08.61#ibcon#read 5, iclass 38, count 0 2006.252.07:37:08.61#ibcon#about to read 6, iclass 38, count 0 2006.252.07:37:08.61#ibcon#read 6, iclass 38, count 0 2006.252.07:37:08.61#ibcon#end of sib2, iclass 38, count 0 2006.252.07:37:08.61#ibcon#*mode == 0, iclass 38, count 0 2006.252.07:37:08.61#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.252.07:37:08.61#ibcon#[26=FRQ=03,672.99\r\n] 2006.252.07:37:08.61#ibcon#*before write, iclass 38, count 0 2006.252.07:37:08.61#ibcon#enter sib2, iclass 38, count 0 2006.252.07:37:08.61#ibcon#flushed, iclass 38, count 0 2006.252.07:37:08.61#ibcon#about to write, iclass 38, count 0 2006.252.07:37:08.61#ibcon#wrote, iclass 38, count 0 2006.252.07:37:08.61#ibcon#about to read 3, iclass 38, count 0 2006.252.07:37:08.65#ibcon#read 3, iclass 38, count 0 2006.252.07:37:08.65#ibcon#about to read 4, iclass 38, count 0 2006.252.07:37:08.65#ibcon#read 4, iclass 38, count 0 2006.252.07:37:08.65#ibcon#about to read 5, iclass 38, count 0 2006.252.07:37:08.65#ibcon#read 5, iclass 38, count 0 2006.252.07:37:08.65#ibcon#about to read 6, iclass 38, count 0 2006.252.07:37:08.65#ibcon#read 6, iclass 38, count 0 2006.252.07:37:08.65#ibcon#end of sib2, iclass 38, count 0 2006.252.07:37:08.65#ibcon#*after write, iclass 38, count 0 2006.252.07:37:08.65#ibcon#*before return 0, iclass 38, count 0 2006.252.07:37:08.66#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.252.07:37:08.66#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.252.07:37:08.66#ibcon#about to clear, iclass 38 cls_cnt 0 2006.252.07:37:08.66#ibcon#cleared, iclass 38 cls_cnt 0 2006.252.07:37:08.66$vc4f8/va=3,6 2006.252.07:37:08.66#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.252.07:37:08.66#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.252.07:37:08.66#ibcon#ireg 11 cls_cnt 2 2006.252.07:37:08.66#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.252.07:37:08.69#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.252.07:37:08.69#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.252.07:37:08.69#ibcon#enter wrdev, iclass 40, count 2 2006.252.07:37:08.69#ibcon#first serial, iclass 40, count 2 2006.252.07:37:08.69#ibcon#enter sib2, iclass 40, count 2 2006.252.07:37:08.69#ibcon#flushed, iclass 40, count 2 2006.252.07:37:08.69#ibcon#about to write, iclass 40, count 2 2006.252.07:37:08.69#ibcon#wrote, iclass 40, count 2 2006.252.07:37:08.69#ibcon#about to read 3, iclass 40, count 2 2006.252.07:37:08.72#ibcon#read 3, iclass 40, count 2 2006.252.07:37:08.72#ibcon#about to read 4, iclass 40, count 2 2006.252.07:37:08.72#ibcon#read 4, iclass 40, count 2 2006.252.07:37:08.72#ibcon#about to read 5, iclass 40, count 2 2006.252.07:37:08.72#ibcon#read 5, iclass 40, count 2 2006.252.07:37:08.72#ibcon#about to read 6, iclass 40, count 2 2006.252.07:37:08.72#ibcon#read 6, iclass 40, count 2 2006.252.07:37:08.72#ibcon#end of sib2, iclass 40, count 2 2006.252.07:37:08.72#ibcon#*mode == 0, iclass 40, count 2 2006.252.07:37:08.72#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.252.07:37:08.72#ibcon#[25=AT03-06\r\n] 2006.252.07:37:08.72#ibcon#*before write, iclass 40, count 2 2006.252.07:37:08.72#ibcon#enter sib2, iclass 40, count 2 2006.252.07:37:08.72#ibcon#flushed, iclass 40, count 2 2006.252.07:37:08.72#ibcon#about to write, iclass 40, count 2 2006.252.07:37:08.72#ibcon#wrote, iclass 40, count 2 2006.252.07:37:08.72#ibcon#about to read 3, iclass 40, count 2 2006.252.07:37:08.75#ibcon#read 3, iclass 40, count 2 2006.252.07:37:08.75#ibcon#about to read 4, iclass 40, count 2 2006.252.07:37:08.75#ibcon#read 4, iclass 40, count 2 2006.252.07:37:08.75#ibcon#about to read 5, iclass 40, count 2 2006.252.07:37:08.75#ibcon#read 5, iclass 40, count 2 2006.252.07:37:08.75#ibcon#about to read 6, iclass 40, count 2 2006.252.07:37:08.75#ibcon#read 6, iclass 40, count 2 2006.252.07:37:08.75#ibcon#end of sib2, iclass 40, count 2 2006.252.07:37:08.75#ibcon#*after write, iclass 40, count 2 2006.252.07:37:08.75#ibcon#*before return 0, iclass 40, count 2 2006.252.07:37:08.76#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.252.07:37:08.76#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.252.07:37:08.76#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.252.07:37:08.76#ibcon#ireg 7 cls_cnt 0 2006.252.07:37:08.76#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.252.07:37:08.87#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.252.07:37:08.87#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.252.07:37:08.87#ibcon#enter wrdev, iclass 40, count 0 2006.252.07:37:08.87#ibcon#first serial, iclass 40, count 0 2006.252.07:37:08.87#ibcon#enter sib2, iclass 40, count 0 2006.252.07:37:08.87#ibcon#flushed, iclass 40, count 0 2006.252.07:37:08.87#ibcon#about to write, iclass 40, count 0 2006.252.07:37:08.87#ibcon#wrote, iclass 40, count 0 2006.252.07:37:08.87#ibcon#about to read 3, iclass 40, count 0 2006.252.07:37:08.89#ibcon#read 3, iclass 40, count 0 2006.252.07:37:08.89#ibcon#about to read 4, iclass 40, count 0 2006.252.07:37:08.89#ibcon#read 4, iclass 40, count 0 2006.252.07:37:08.89#ibcon#about to read 5, iclass 40, count 0 2006.252.07:37:08.89#ibcon#read 5, iclass 40, count 0 2006.252.07:37:08.89#ibcon#about to read 6, iclass 40, count 0 2006.252.07:37:08.89#ibcon#read 6, iclass 40, count 0 2006.252.07:37:08.89#ibcon#end of sib2, iclass 40, count 0 2006.252.07:37:08.89#ibcon#*mode == 0, iclass 40, count 0 2006.252.07:37:08.89#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.252.07:37:08.89#ibcon#[25=USB\r\n] 2006.252.07:37:08.89#ibcon#*before write, iclass 40, count 0 2006.252.07:37:08.89#ibcon#enter sib2, iclass 40, count 0 2006.252.07:37:08.89#ibcon#flushed, iclass 40, count 0 2006.252.07:37:08.90#ibcon#about to write, iclass 40, count 0 2006.252.07:37:08.90#ibcon#wrote, iclass 40, count 0 2006.252.07:37:08.90#ibcon#about to read 3, iclass 40, count 0 2006.252.07:37:08.92#ibcon#read 3, iclass 40, count 0 2006.252.07:37:08.92#ibcon#about to read 4, iclass 40, count 0 2006.252.07:37:08.92#ibcon#read 4, iclass 40, count 0 2006.252.07:37:08.92#ibcon#about to read 5, iclass 40, count 0 2006.252.07:37:08.92#ibcon#read 5, iclass 40, count 0 2006.252.07:37:08.92#ibcon#about to read 6, iclass 40, count 0 2006.252.07:37:08.92#ibcon#read 6, iclass 40, count 0 2006.252.07:37:08.92#ibcon#end of sib2, iclass 40, count 0 2006.252.07:37:08.92#ibcon#*after write, iclass 40, count 0 2006.252.07:37:08.92#ibcon#*before return 0, iclass 40, count 0 2006.252.07:37:08.92#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.252.07:37:08.92#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.252.07:37:08.92#ibcon#about to clear, iclass 40 cls_cnt 0 2006.252.07:37:08.93#ibcon#cleared, iclass 40 cls_cnt 0 2006.252.07:37:08.93$vc4f8/valo=4,832.99 2006.252.07:37:08.93#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.252.07:37:08.93#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.252.07:37:08.93#ibcon#ireg 17 cls_cnt 0 2006.252.07:37:08.93#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.252.07:37:08.93#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.252.07:37:08.93#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.252.07:37:08.93#ibcon#enter wrdev, iclass 4, count 0 2006.252.07:37:08.93#ibcon#first serial, iclass 4, count 0 2006.252.07:37:08.93#ibcon#enter sib2, iclass 4, count 0 2006.252.07:37:08.93#ibcon#flushed, iclass 4, count 0 2006.252.07:37:08.93#ibcon#about to write, iclass 4, count 0 2006.252.07:37:08.93#ibcon#wrote, iclass 4, count 0 2006.252.07:37:08.93#ibcon#about to read 3, iclass 4, count 0 2006.252.07:37:08.94#ibcon#read 3, iclass 4, count 0 2006.252.07:37:08.94#ibcon#about to read 4, iclass 4, count 0 2006.252.07:37:08.94#ibcon#read 4, iclass 4, count 0 2006.252.07:37:08.94#ibcon#about to read 5, iclass 4, count 0 2006.252.07:37:08.94#ibcon#read 5, iclass 4, count 0 2006.252.07:37:08.94#ibcon#about to read 6, iclass 4, count 0 2006.252.07:37:08.94#ibcon#read 6, iclass 4, count 0 2006.252.07:37:08.94#ibcon#end of sib2, iclass 4, count 0 2006.252.07:37:08.94#ibcon#*mode == 0, iclass 4, count 0 2006.252.07:37:08.94#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.252.07:37:08.94#ibcon#[26=FRQ=04,832.99\r\n] 2006.252.07:37:08.94#ibcon#*before write, iclass 4, count 0 2006.252.07:37:08.94#ibcon#enter sib2, iclass 4, count 0 2006.252.07:37:08.94#ibcon#flushed, iclass 4, count 0 2006.252.07:37:08.95#ibcon#about to write, iclass 4, count 0 2006.252.07:37:08.95#ibcon#wrote, iclass 4, count 0 2006.252.07:37:08.95#ibcon#about to read 3, iclass 4, count 0 2006.252.07:37:08.99#ibcon#read 3, iclass 4, count 0 2006.252.07:37:08.99#ibcon#about to read 4, iclass 4, count 0 2006.252.07:37:08.99#ibcon#read 4, iclass 4, count 0 2006.252.07:37:08.99#ibcon#about to read 5, iclass 4, count 0 2006.252.07:37:08.99#ibcon#read 5, iclass 4, count 0 2006.252.07:37:08.99#ibcon#about to read 6, iclass 4, count 0 2006.252.07:37:08.99#ibcon#read 6, iclass 4, count 0 2006.252.07:37:08.99#ibcon#end of sib2, iclass 4, count 0 2006.252.07:37:08.99#ibcon#*after write, iclass 4, count 0 2006.252.07:37:08.99#ibcon#*before return 0, iclass 4, count 0 2006.252.07:37:08.99#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.252.07:37:08.99#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.252.07:37:08.99#ibcon#about to clear, iclass 4 cls_cnt 0 2006.252.07:37:08.99#ibcon#cleared, iclass 4 cls_cnt 0 2006.252.07:37:08.99$vc4f8/va=4,7 2006.252.07:37:08.99#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.252.07:37:08.99#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.252.07:37:08.99#ibcon#ireg 11 cls_cnt 2 2006.252.07:37:08.99#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.252.07:37:09.03#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.252.07:37:09.03#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.252.07:37:09.03#ibcon#enter wrdev, iclass 6, count 2 2006.252.07:37:09.03#ibcon#first serial, iclass 6, count 2 2006.252.07:37:09.03#ibcon#enter sib2, iclass 6, count 2 2006.252.07:37:09.03#ibcon#flushed, iclass 6, count 2 2006.252.07:37:09.03#ibcon#about to write, iclass 6, count 2 2006.252.07:37:09.03#ibcon#wrote, iclass 6, count 2 2006.252.07:37:09.03#ibcon#about to read 3, iclass 6, count 2 2006.252.07:37:09.05#ibcon#read 3, iclass 6, count 2 2006.252.07:37:09.05#ibcon#about to read 4, iclass 6, count 2 2006.252.07:37:09.05#ibcon#read 4, iclass 6, count 2 2006.252.07:37:09.05#ibcon#about to read 5, iclass 6, count 2 2006.252.07:37:09.05#ibcon#read 5, iclass 6, count 2 2006.252.07:37:09.05#ibcon#about to read 6, iclass 6, count 2 2006.252.07:37:09.05#ibcon#read 6, iclass 6, count 2 2006.252.07:37:09.05#ibcon#end of sib2, iclass 6, count 2 2006.252.07:37:09.05#ibcon#*mode == 0, iclass 6, count 2 2006.252.07:37:09.05#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.252.07:37:09.05#ibcon#[25=AT04-07\r\n] 2006.252.07:37:09.06#ibcon#*before write, iclass 6, count 2 2006.252.07:37:09.06#ibcon#enter sib2, iclass 6, count 2 2006.252.07:37:09.06#ibcon#flushed, iclass 6, count 2 2006.252.07:37:09.06#ibcon#about to write, iclass 6, count 2 2006.252.07:37:09.06#ibcon#wrote, iclass 6, count 2 2006.252.07:37:09.06#ibcon#about to read 3, iclass 6, count 2 2006.252.07:37:09.08#ibcon#read 3, iclass 6, count 2 2006.252.07:37:09.08#ibcon#about to read 4, iclass 6, count 2 2006.252.07:37:09.08#ibcon#read 4, iclass 6, count 2 2006.252.07:37:09.08#ibcon#about to read 5, iclass 6, count 2 2006.252.07:37:09.08#ibcon#read 5, iclass 6, count 2 2006.252.07:37:09.08#ibcon#about to read 6, iclass 6, count 2 2006.252.07:37:09.08#ibcon#read 6, iclass 6, count 2 2006.252.07:37:09.08#ibcon#end of sib2, iclass 6, count 2 2006.252.07:37:09.08#ibcon#*after write, iclass 6, count 2 2006.252.07:37:09.08#ibcon#*before return 0, iclass 6, count 2 2006.252.07:37:09.08#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.252.07:37:09.09#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.252.07:37:09.09#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.252.07:37:09.09#ibcon#ireg 7 cls_cnt 0 2006.252.07:37:09.09#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.252.07:37:09.19#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.252.07:37:09.19#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.252.07:37:09.19#ibcon#enter wrdev, iclass 6, count 0 2006.252.07:37:09.19#ibcon#first serial, iclass 6, count 0 2006.252.07:37:09.19#ibcon#enter sib2, iclass 6, count 0 2006.252.07:37:09.19#ibcon#flushed, iclass 6, count 0 2006.252.07:37:09.19#ibcon#about to write, iclass 6, count 0 2006.252.07:37:09.19#ibcon#wrote, iclass 6, count 0 2006.252.07:37:09.19#ibcon#about to read 3, iclass 6, count 0 2006.252.07:37:09.21#ibcon#read 3, iclass 6, count 0 2006.252.07:37:09.21#ibcon#about to read 4, iclass 6, count 0 2006.252.07:37:09.21#ibcon#read 4, iclass 6, count 0 2006.252.07:37:09.21#ibcon#about to read 5, iclass 6, count 0 2006.252.07:37:09.21#ibcon#read 5, iclass 6, count 0 2006.252.07:37:09.21#ibcon#about to read 6, iclass 6, count 0 2006.252.07:37:09.21#ibcon#read 6, iclass 6, count 0 2006.252.07:37:09.21#ibcon#end of sib2, iclass 6, count 0 2006.252.07:37:09.21#ibcon#*mode == 0, iclass 6, count 0 2006.252.07:37:09.21#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.252.07:37:09.21#ibcon#[25=USB\r\n] 2006.252.07:37:09.21#ibcon#*before write, iclass 6, count 0 2006.252.07:37:09.21#ibcon#enter sib2, iclass 6, count 0 2006.252.07:37:09.21#ibcon#flushed, iclass 6, count 0 2006.252.07:37:09.22#ibcon#about to write, iclass 6, count 0 2006.252.07:37:09.22#ibcon#wrote, iclass 6, count 0 2006.252.07:37:09.22#ibcon#about to read 3, iclass 6, count 0 2006.252.07:37:09.24#ibcon#read 3, iclass 6, count 0 2006.252.07:37:09.24#ibcon#about to read 4, iclass 6, count 0 2006.252.07:37:09.24#ibcon#read 4, iclass 6, count 0 2006.252.07:37:09.24#ibcon#about to read 5, iclass 6, count 0 2006.252.07:37:09.24#ibcon#read 5, iclass 6, count 0 2006.252.07:37:09.24#ibcon#about to read 6, iclass 6, count 0 2006.252.07:37:09.24#ibcon#read 6, iclass 6, count 0 2006.252.07:37:09.24#ibcon#end of sib2, iclass 6, count 0 2006.252.07:37:09.24#ibcon#*after write, iclass 6, count 0 2006.252.07:37:09.24#ibcon#*before return 0, iclass 6, count 0 2006.252.07:37:09.24#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.252.07:37:09.24#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.252.07:37:09.24#ibcon#about to clear, iclass 6 cls_cnt 0 2006.252.07:37:09.25#ibcon#cleared, iclass 6 cls_cnt 0 2006.252.07:37:09.25$vc4f8/valo=5,652.99 2006.252.07:37:09.25#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.252.07:37:09.25#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.252.07:37:09.25#ibcon#ireg 17 cls_cnt 0 2006.252.07:37:09.25#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.252.07:37:09.25#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.252.07:37:09.25#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.252.07:37:09.25#ibcon#enter wrdev, iclass 10, count 0 2006.252.07:37:09.25#ibcon#first serial, iclass 10, count 0 2006.252.07:37:09.25#ibcon#enter sib2, iclass 10, count 0 2006.252.07:37:09.25#ibcon#flushed, iclass 10, count 0 2006.252.07:37:09.25#ibcon#about to write, iclass 10, count 0 2006.252.07:37:09.25#ibcon#wrote, iclass 10, count 0 2006.252.07:37:09.25#ibcon#about to read 3, iclass 10, count 0 2006.252.07:37:09.26#ibcon#read 3, iclass 10, count 0 2006.252.07:37:09.26#ibcon#about to read 4, iclass 10, count 0 2006.252.07:37:09.26#ibcon#read 4, iclass 10, count 0 2006.252.07:37:09.26#ibcon#about to read 5, iclass 10, count 0 2006.252.07:37:09.26#ibcon#read 5, iclass 10, count 0 2006.252.07:37:09.26#ibcon#about to read 6, iclass 10, count 0 2006.252.07:37:09.26#ibcon#read 6, iclass 10, count 0 2006.252.07:37:09.26#ibcon#end of sib2, iclass 10, count 0 2006.252.07:37:09.26#ibcon#*mode == 0, iclass 10, count 0 2006.252.07:37:09.26#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.252.07:37:09.26#ibcon#[26=FRQ=05,652.99\r\n] 2006.252.07:37:09.26#ibcon#*before write, iclass 10, count 0 2006.252.07:37:09.26#ibcon#enter sib2, iclass 10, count 0 2006.252.07:37:09.27#ibcon#flushed, iclass 10, count 0 2006.252.07:37:09.27#ibcon#about to write, iclass 10, count 0 2006.252.07:37:09.27#ibcon#wrote, iclass 10, count 0 2006.252.07:37:09.27#ibcon#about to read 3, iclass 10, count 0 2006.252.07:37:09.30#ibcon#read 3, iclass 10, count 0 2006.252.07:37:09.30#ibcon#about to read 4, iclass 10, count 0 2006.252.07:37:09.30#ibcon#read 4, iclass 10, count 0 2006.252.07:37:09.30#ibcon#about to read 5, iclass 10, count 0 2006.252.07:37:09.30#ibcon#read 5, iclass 10, count 0 2006.252.07:37:09.30#ibcon#about to read 6, iclass 10, count 0 2006.252.07:37:09.30#ibcon#read 6, iclass 10, count 0 2006.252.07:37:09.30#ibcon#end of sib2, iclass 10, count 0 2006.252.07:37:09.30#ibcon#*after write, iclass 10, count 0 2006.252.07:37:09.30#ibcon#*before return 0, iclass 10, count 0 2006.252.07:37:09.30#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.252.07:37:09.30#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.252.07:37:09.30#ibcon#about to clear, iclass 10 cls_cnt 0 2006.252.07:37:09.31#ibcon#cleared, iclass 10 cls_cnt 0 2006.252.07:37:09.31$vc4f8/va=5,7 2006.252.07:37:09.31#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.252.07:37:09.31#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.252.07:37:09.31#ibcon#ireg 11 cls_cnt 2 2006.252.07:37:09.31#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.252.07:37:09.35#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.252.07:37:09.35#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.252.07:37:09.35#ibcon#enter wrdev, iclass 12, count 2 2006.252.07:37:09.35#ibcon#first serial, iclass 12, count 2 2006.252.07:37:09.35#ibcon#enter sib2, iclass 12, count 2 2006.252.07:37:09.35#ibcon#flushed, iclass 12, count 2 2006.252.07:37:09.35#ibcon#about to write, iclass 12, count 2 2006.252.07:37:09.35#ibcon#wrote, iclass 12, count 2 2006.252.07:37:09.35#ibcon#about to read 3, iclass 12, count 2 2006.252.07:37:09.37#ibcon#read 3, iclass 12, count 2 2006.252.07:37:09.37#ibcon#about to read 4, iclass 12, count 2 2006.252.07:37:09.37#ibcon#read 4, iclass 12, count 2 2006.252.07:37:09.37#ibcon#about to read 5, iclass 12, count 2 2006.252.07:37:09.37#ibcon#read 5, iclass 12, count 2 2006.252.07:37:09.37#ibcon#about to read 6, iclass 12, count 2 2006.252.07:37:09.37#ibcon#read 6, iclass 12, count 2 2006.252.07:37:09.37#ibcon#end of sib2, iclass 12, count 2 2006.252.07:37:09.37#ibcon#*mode == 0, iclass 12, count 2 2006.252.07:37:09.37#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.252.07:37:09.37#ibcon#[25=AT05-07\r\n] 2006.252.07:37:09.38#ibcon#*before write, iclass 12, count 2 2006.252.07:37:09.38#ibcon#enter sib2, iclass 12, count 2 2006.252.07:37:09.38#ibcon#flushed, iclass 12, count 2 2006.252.07:37:09.38#ibcon#about to write, iclass 12, count 2 2006.252.07:37:09.38#ibcon#wrote, iclass 12, count 2 2006.252.07:37:09.38#ibcon#about to read 3, iclass 12, count 2 2006.252.07:37:09.40#ibcon#read 3, iclass 12, count 2 2006.252.07:37:09.40#ibcon#about to read 4, iclass 12, count 2 2006.252.07:37:09.40#ibcon#read 4, iclass 12, count 2 2006.252.07:37:09.40#ibcon#about to read 5, iclass 12, count 2 2006.252.07:37:09.40#ibcon#read 5, iclass 12, count 2 2006.252.07:37:09.40#ibcon#about to read 6, iclass 12, count 2 2006.252.07:37:09.40#ibcon#read 6, iclass 12, count 2 2006.252.07:37:09.40#ibcon#end of sib2, iclass 12, count 2 2006.252.07:37:09.40#ibcon#*after write, iclass 12, count 2 2006.252.07:37:09.40#ibcon#*before return 0, iclass 12, count 2 2006.252.07:37:09.40#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.252.07:37:09.40#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.252.07:37:09.40#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.252.07:37:09.41#ibcon#ireg 7 cls_cnt 0 2006.252.07:37:09.41#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.252.07:37:09.52#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.252.07:37:09.52#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.252.07:37:09.52#ibcon#enter wrdev, iclass 12, count 0 2006.252.07:37:09.52#ibcon#first serial, iclass 12, count 0 2006.252.07:37:09.52#ibcon#enter sib2, iclass 12, count 0 2006.252.07:37:09.52#ibcon#flushed, iclass 12, count 0 2006.252.07:37:09.52#ibcon#about to write, iclass 12, count 0 2006.252.07:37:09.52#ibcon#wrote, iclass 12, count 0 2006.252.07:37:09.52#ibcon#about to read 3, iclass 12, count 0 2006.252.07:37:09.54#ibcon#read 3, iclass 12, count 0 2006.252.07:37:09.54#ibcon#about to read 4, iclass 12, count 0 2006.252.07:37:09.54#ibcon#read 4, iclass 12, count 0 2006.252.07:37:09.54#ibcon#about to read 5, iclass 12, count 0 2006.252.07:37:09.54#ibcon#read 5, iclass 12, count 0 2006.252.07:37:09.54#ibcon#about to read 6, iclass 12, count 0 2006.252.07:37:09.54#ibcon#read 6, iclass 12, count 0 2006.252.07:37:09.54#ibcon#end of sib2, iclass 12, count 0 2006.252.07:37:09.54#ibcon#*mode == 0, iclass 12, count 0 2006.252.07:37:09.54#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.252.07:37:09.54#ibcon#[25=USB\r\n] 2006.252.07:37:09.54#ibcon#*before write, iclass 12, count 0 2006.252.07:37:09.54#ibcon#enter sib2, iclass 12, count 0 2006.252.07:37:09.54#ibcon#flushed, iclass 12, count 0 2006.252.07:37:09.54#ibcon#about to write, iclass 12, count 0 2006.252.07:37:09.54#ibcon#wrote, iclass 12, count 0 2006.252.07:37:09.54#ibcon#about to read 3, iclass 12, count 0 2006.252.07:37:09.56#ibcon#read 3, iclass 12, count 0 2006.252.07:37:09.56#ibcon#about to read 4, iclass 12, count 0 2006.252.07:37:09.56#ibcon#read 4, iclass 12, count 0 2006.252.07:37:09.56#ibcon#about to read 5, iclass 12, count 0 2006.252.07:37:09.56#ibcon#read 5, iclass 12, count 0 2006.252.07:37:09.56#ibcon#about to read 6, iclass 12, count 0 2006.252.07:37:09.56#ibcon#read 6, iclass 12, count 0 2006.252.07:37:09.56#ibcon#end of sib2, iclass 12, count 0 2006.252.07:37:09.56#ibcon#*after write, iclass 12, count 0 2006.252.07:37:09.56#ibcon#*before return 0, iclass 12, count 0 2006.252.07:37:09.57#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.252.07:37:09.57#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.252.07:37:09.57#ibcon#about to clear, iclass 12 cls_cnt 0 2006.252.07:37:09.57#ibcon#cleared, iclass 12 cls_cnt 0 2006.252.07:37:09.57$vc4f8/valo=6,772.99 2006.252.07:37:09.57#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.252.07:37:09.57#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.252.07:37:09.57#ibcon#ireg 17 cls_cnt 0 2006.252.07:37:09.57#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.252.07:37:09.57#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.252.07:37:09.57#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.252.07:37:09.57#ibcon#enter wrdev, iclass 14, count 0 2006.252.07:37:09.57#ibcon#first serial, iclass 14, count 0 2006.252.07:37:09.57#ibcon#enter sib2, iclass 14, count 0 2006.252.07:37:09.57#ibcon#flushed, iclass 14, count 0 2006.252.07:37:09.57#ibcon#about to write, iclass 14, count 0 2006.252.07:37:09.57#ibcon#wrote, iclass 14, count 0 2006.252.07:37:09.57#ibcon#about to read 3, iclass 14, count 0 2006.252.07:37:09.58#ibcon#read 3, iclass 14, count 0 2006.252.07:37:09.58#ibcon#about to read 4, iclass 14, count 0 2006.252.07:37:09.58#ibcon#read 4, iclass 14, count 0 2006.252.07:37:09.58#ibcon#about to read 5, iclass 14, count 0 2006.252.07:37:09.58#ibcon#read 5, iclass 14, count 0 2006.252.07:37:09.58#ibcon#about to read 6, iclass 14, count 0 2006.252.07:37:09.58#ibcon#read 6, iclass 14, count 0 2006.252.07:37:09.58#ibcon#end of sib2, iclass 14, count 0 2006.252.07:37:09.58#ibcon#*mode == 0, iclass 14, count 0 2006.252.07:37:09.58#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.252.07:37:09.58#ibcon#[26=FRQ=06,772.99\r\n] 2006.252.07:37:09.58#ibcon#*before write, iclass 14, count 0 2006.252.07:37:09.58#ibcon#enter sib2, iclass 14, count 0 2006.252.07:37:09.59#ibcon#flushed, iclass 14, count 0 2006.252.07:37:09.59#ibcon#about to write, iclass 14, count 0 2006.252.07:37:09.59#ibcon#wrote, iclass 14, count 0 2006.252.07:37:09.59#ibcon#about to read 3, iclass 14, count 0 2006.252.07:37:09.62#ibcon#read 3, iclass 14, count 0 2006.252.07:37:09.62#ibcon#about to read 4, iclass 14, count 0 2006.252.07:37:09.62#ibcon#read 4, iclass 14, count 0 2006.252.07:37:09.62#ibcon#about to read 5, iclass 14, count 0 2006.252.07:37:09.62#ibcon#read 5, iclass 14, count 0 2006.252.07:37:09.62#ibcon#about to read 6, iclass 14, count 0 2006.252.07:37:09.62#ibcon#read 6, iclass 14, count 0 2006.252.07:37:09.62#ibcon#end of sib2, iclass 14, count 0 2006.252.07:37:09.62#ibcon#*after write, iclass 14, count 0 2006.252.07:37:09.62#ibcon#*before return 0, iclass 14, count 0 2006.252.07:37:09.62#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.252.07:37:09.62#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.252.07:37:09.62#ibcon#about to clear, iclass 14 cls_cnt 0 2006.252.07:37:09.63#ibcon#cleared, iclass 14 cls_cnt 0 2006.252.07:37:09.63$vc4f8/va=6,7 2006.252.07:37:09.63#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.252.07:37:09.63#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.252.07:37:09.63#ibcon#ireg 11 cls_cnt 2 2006.252.07:37:09.63#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.252.07:37:09.68#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.252.07:37:09.68#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.252.07:37:09.68#ibcon#enter wrdev, iclass 16, count 2 2006.252.07:37:09.68#ibcon#first serial, iclass 16, count 2 2006.252.07:37:09.68#ibcon#enter sib2, iclass 16, count 2 2006.252.07:37:09.68#ibcon#flushed, iclass 16, count 2 2006.252.07:37:09.68#ibcon#about to write, iclass 16, count 2 2006.252.07:37:09.68#ibcon#wrote, iclass 16, count 2 2006.252.07:37:09.68#ibcon#about to read 3, iclass 16, count 2 2006.252.07:37:09.70#ibcon#read 3, iclass 16, count 2 2006.252.07:37:09.70#ibcon#about to read 4, iclass 16, count 2 2006.252.07:37:09.70#ibcon#read 4, iclass 16, count 2 2006.252.07:37:09.70#ibcon#about to read 5, iclass 16, count 2 2006.252.07:37:09.70#ibcon#read 5, iclass 16, count 2 2006.252.07:37:09.70#ibcon#about to read 6, iclass 16, count 2 2006.252.07:37:09.70#ibcon#read 6, iclass 16, count 2 2006.252.07:37:09.70#ibcon#end of sib2, iclass 16, count 2 2006.252.07:37:09.70#ibcon#*mode == 0, iclass 16, count 2 2006.252.07:37:09.70#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.252.07:37:09.70#ibcon#[25=AT06-07\r\n] 2006.252.07:37:09.70#ibcon#*before write, iclass 16, count 2 2006.252.07:37:09.70#ibcon#enter sib2, iclass 16, count 2 2006.252.07:37:09.70#ibcon#flushed, iclass 16, count 2 2006.252.07:37:09.71#ibcon#about to write, iclass 16, count 2 2006.252.07:37:09.71#ibcon#wrote, iclass 16, count 2 2006.252.07:37:09.71#ibcon#about to read 3, iclass 16, count 2 2006.252.07:37:09.73#ibcon#read 3, iclass 16, count 2 2006.252.07:37:09.73#ibcon#about to read 4, iclass 16, count 2 2006.252.07:37:09.73#ibcon#read 4, iclass 16, count 2 2006.252.07:37:09.73#ibcon#about to read 5, iclass 16, count 2 2006.252.07:37:09.73#ibcon#read 5, iclass 16, count 2 2006.252.07:37:09.73#ibcon#about to read 6, iclass 16, count 2 2006.252.07:37:09.73#ibcon#read 6, iclass 16, count 2 2006.252.07:37:09.73#ibcon#end of sib2, iclass 16, count 2 2006.252.07:37:09.73#ibcon#*after write, iclass 16, count 2 2006.252.07:37:09.73#ibcon#*before return 0, iclass 16, count 2 2006.252.07:37:09.73#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.252.07:37:09.73#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.252.07:37:09.73#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.252.07:37:09.74#ibcon#ireg 7 cls_cnt 0 2006.252.07:37:09.74#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.252.07:37:09.84#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.252.07:37:09.84#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.252.07:37:09.84#ibcon#enter wrdev, iclass 16, count 0 2006.252.07:37:09.84#ibcon#first serial, iclass 16, count 0 2006.252.07:37:09.84#ibcon#enter sib2, iclass 16, count 0 2006.252.07:37:09.84#ibcon#flushed, iclass 16, count 0 2006.252.07:37:09.84#ibcon#about to write, iclass 16, count 0 2006.252.07:37:09.84#ibcon#wrote, iclass 16, count 0 2006.252.07:37:09.84#ibcon#about to read 3, iclass 16, count 0 2006.252.07:37:09.86#ibcon#read 3, iclass 16, count 0 2006.252.07:37:09.86#ibcon#about to read 4, iclass 16, count 0 2006.252.07:37:09.86#ibcon#read 4, iclass 16, count 0 2006.252.07:37:09.86#ibcon#about to read 5, iclass 16, count 0 2006.252.07:37:09.86#ibcon#read 5, iclass 16, count 0 2006.252.07:37:09.86#ibcon#about to read 6, iclass 16, count 0 2006.252.07:37:09.86#ibcon#read 6, iclass 16, count 0 2006.252.07:37:09.86#ibcon#end of sib2, iclass 16, count 0 2006.252.07:37:09.86#ibcon#*mode == 0, iclass 16, count 0 2006.252.07:37:09.86#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.252.07:37:09.86#ibcon#[25=USB\r\n] 2006.252.07:37:09.86#ibcon#*before write, iclass 16, count 0 2006.252.07:37:09.86#ibcon#enter sib2, iclass 16, count 0 2006.252.07:37:09.86#ibcon#flushed, iclass 16, count 0 2006.252.07:37:09.87#ibcon#about to write, iclass 16, count 0 2006.252.07:37:09.87#ibcon#wrote, iclass 16, count 0 2006.252.07:37:09.87#ibcon#about to read 3, iclass 16, count 0 2006.252.07:37:09.89#ibcon#read 3, iclass 16, count 0 2006.252.07:37:09.89#ibcon#about to read 4, iclass 16, count 0 2006.252.07:37:09.89#ibcon#read 4, iclass 16, count 0 2006.252.07:37:09.89#ibcon#about to read 5, iclass 16, count 0 2006.252.07:37:09.89#ibcon#read 5, iclass 16, count 0 2006.252.07:37:09.89#ibcon#about to read 6, iclass 16, count 0 2006.252.07:37:09.89#ibcon#read 6, iclass 16, count 0 2006.252.07:37:09.89#ibcon#end of sib2, iclass 16, count 0 2006.252.07:37:09.89#ibcon#*after write, iclass 16, count 0 2006.252.07:37:09.89#ibcon#*before return 0, iclass 16, count 0 2006.252.07:37:09.89#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.252.07:37:09.89#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.252.07:37:09.89#ibcon#about to clear, iclass 16 cls_cnt 0 2006.252.07:37:09.90#ibcon#cleared, iclass 16 cls_cnt 0 2006.252.07:37:09.90$vc4f8/valo=7,832.99 2006.252.07:37:09.90#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.252.07:37:09.90#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.252.07:37:09.90#ibcon#ireg 17 cls_cnt 0 2006.252.07:37:09.90#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.252.07:37:09.90#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.252.07:37:09.90#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.252.07:37:09.90#ibcon#enter wrdev, iclass 18, count 0 2006.252.07:37:09.90#ibcon#first serial, iclass 18, count 0 2006.252.07:37:09.90#ibcon#enter sib2, iclass 18, count 0 2006.252.07:37:09.90#ibcon#flushed, iclass 18, count 0 2006.252.07:37:09.90#ibcon#about to write, iclass 18, count 0 2006.252.07:37:09.90#ibcon#wrote, iclass 18, count 0 2006.252.07:37:09.90#ibcon#about to read 3, iclass 18, count 0 2006.252.07:37:09.91#ibcon#read 3, iclass 18, count 0 2006.252.07:37:09.91#ibcon#about to read 4, iclass 18, count 0 2006.252.07:37:09.91#ibcon#read 4, iclass 18, count 0 2006.252.07:37:09.91#ibcon#about to read 5, iclass 18, count 0 2006.252.07:37:09.91#ibcon#read 5, iclass 18, count 0 2006.252.07:37:09.91#ibcon#about to read 6, iclass 18, count 0 2006.252.07:37:09.91#ibcon#read 6, iclass 18, count 0 2006.252.07:37:09.91#ibcon#end of sib2, iclass 18, count 0 2006.252.07:37:09.91#ibcon#*mode == 0, iclass 18, count 0 2006.252.07:37:09.91#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.252.07:37:09.91#ibcon#[26=FRQ=07,832.99\r\n] 2006.252.07:37:09.91#ibcon#*before write, iclass 18, count 0 2006.252.07:37:09.91#ibcon#enter sib2, iclass 18, count 0 2006.252.07:37:09.91#ibcon#flushed, iclass 18, count 0 2006.252.07:37:09.92#ibcon#about to write, iclass 18, count 0 2006.252.07:37:09.92#ibcon#wrote, iclass 18, count 0 2006.252.07:37:09.92#ibcon#about to read 3, iclass 18, count 0 2006.252.07:37:09.95#ibcon#read 3, iclass 18, count 0 2006.252.07:37:09.95#ibcon#about to read 4, iclass 18, count 0 2006.252.07:37:09.95#ibcon#read 4, iclass 18, count 0 2006.252.07:37:09.95#ibcon#about to read 5, iclass 18, count 0 2006.252.07:37:09.95#ibcon#read 5, iclass 18, count 0 2006.252.07:37:09.95#ibcon#about to read 6, iclass 18, count 0 2006.252.07:37:09.95#ibcon#read 6, iclass 18, count 0 2006.252.07:37:09.95#ibcon#end of sib2, iclass 18, count 0 2006.252.07:37:09.95#ibcon#*after write, iclass 18, count 0 2006.252.07:37:09.95#ibcon#*before return 0, iclass 18, count 0 2006.252.07:37:09.95#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.252.07:37:09.95#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.252.07:37:09.96#ibcon#about to clear, iclass 18 cls_cnt 0 2006.252.07:37:09.96#ibcon#cleared, iclass 18 cls_cnt 0 2006.252.07:37:09.96$vc4f8/va=7,7 2006.252.07:37:09.96#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.252.07:37:09.96#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.252.07:37:09.96#ibcon#ireg 11 cls_cnt 2 2006.252.07:37:09.96#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.252.07:37:10.00#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.252.07:37:10.00#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.252.07:37:10.00#ibcon#enter wrdev, iclass 20, count 2 2006.252.07:37:10.00#ibcon#first serial, iclass 20, count 2 2006.252.07:37:10.00#ibcon#enter sib2, iclass 20, count 2 2006.252.07:37:10.00#ibcon#flushed, iclass 20, count 2 2006.252.07:37:10.00#ibcon#about to write, iclass 20, count 2 2006.252.07:37:10.00#ibcon#wrote, iclass 20, count 2 2006.252.07:37:10.00#ibcon#about to read 3, iclass 20, count 2 2006.252.07:37:10.02#ibcon#read 3, iclass 20, count 2 2006.252.07:37:10.02#ibcon#about to read 4, iclass 20, count 2 2006.252.07:37:10.02#ibcon#read 4, iclass 20, count 2 2006.252.07:37:10.02#ibcon#about to read 5, iclass 20, count 2 2006.252.07:37:10.02#ibcon#read 5, iclass 20, count 2 2006.252.07:37:10.02#ibcon#about to read 6, iclass 20, count 2 2006.252.07:37:10.02#ibcon#read 6, iclass 20, count 2 2006.252.07:37:10.02#ibcon#end of sib2, iclass 20, count 2 2006.252.07:37:10.02#ibcon#*mode == 0, iclass 20, count 2 2006.252.07:37:10.02#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.252.07:37:10.02#ibcon#[25=AT07-07\r\n] 2006.252.07:37:10.02#ibcon#*before write, iclass 20, count 2 2006.252.07:37:10.02#ibcon#enter sib2, iclass 20, count 2 2006.252.07:37:10.03#ibcon#flushed, iclass 20, count 2 2006.252.07:37:10.03#ibcon#about to write, iclass 20, count 2 2006.252.07:37:10.03#ibcon#wrote, iclass 20, count 2 2006.252.07:37:10.03#ibcon#about to read 3, iclass 20, count 2 2006.252.07:37:10.05#ibcon#read 3, iclass 20, count 2 2006.252.07:37:10.05#ibcon#about to read 4, iclass 20, count 2 2006.252.07:37:10.05#ibcon#read 4, iclass 20, count 2 2006.252.07:37:10.05#ibcon#about to read 5, iclass 20, count 2 2006.252.07:37:10.05#ibcon#read 5, iclass 20, count 2 2006.252.07:37:10.05#ibcon#about to read 6, iclass 20, count 2 2006.252.07:37:10.05#ibcon#read 6, iclass 20, count 2 2006.252.07:37:10.05#ibcon#end of sib2, iclass 20, count 2 2006.252.07:37:10.05#ibcon#*after write, iclass 20, count 2 2006.252.07:37:10.05#ibcon#*before return 0, iclass 20, count 2 2006.252.07:37:10.05#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.252.07:37:10.05#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.252.07:37:10.05#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.252.07:37:10.06#ibcon#ireg 7 cls_cnt 0 2006.252.07:37:10.06#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.252.07:37:10.16#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.252.07:37:10.16#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.252.07:37:10.16#ibcon#enter wrdev, iclass 20, count 0 2006.252.07:37:10.16#ibcon#first serial, iclass 20, count 0 2006.252.07:37:10.16#ibcon#enter sib2, iclass 20, count 0 2006.252.07:37:10.16#ibcon#flushed, iclass 20, count 0 2006.252.07:37:10.16#ibcon#about to write, iclass 20, count 0 2006.252.07:37:10.16#ibcon#wrote, iclass 20, count 0 2006.252.07:37:10.16#ibcon#about to read 3, iclass 20, count 0 2006.252.07:37:10.18#ibcon#read 3, iclass 20, count 0 2006.252.07:37:10.18#ibcon#about to read 4, iclass 20, count 0 2006.252.07:37:10.18#ibcon#read 4, iclass 20, count 0 2006.252.07:37:10.18#ibcon#about to read 5, iclass 20, count 0 2006.252.07:37:10.18#ibcon#read 5, iclass 20, count 0 2006.252.07:37:10.18#ibcon#about to read 6, iclass 20, count 0 2006.252.07:37:10.18#ibcon#read 6, iclass 20, count 0 2006.252.07:37:10.18#ibcon#end of sib2, iclass 20, count 0 2006.252.07:37:10.18#ibcon#*mode == 0, iclass 20, count 0 2006.252.07:37:10.18#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.252.07:37:10.18#ibcon#[25=USB\r\n] 2006.252.07:37:10.18#ibcon#*before write, iclass 20, count 0 2006.252.07:37:10.18#ibcon#enter sib2, iclass 20, count 0 2006.252.07:37:10.18#ibcon#flushed, iclass 20, count 0 2006.252.07:37:10.19#ibcon#about to write, iclass 20, count 0 2006.252.07:37:10.19#ibcon#wrote, iclass 20, count 0 2006.252.07:37:10.19#ibcon#about to read 3, iclass 20, count 0 2006.252.07:37:10.21#ibcon#read 3, iclass 20, count 0 2006.252.07:37:10.21#ibcon#about to read 4, iclass 20, count 0 2006.252.07:37:10.21#ibcon#read 4, iclass 20, count 0 2006.252.07:37:10.21#ibcon#about to read 5, iclass 20, count 0 2006.252.07:37:10.21#ibcon#read 5, iclass 20, count 0 2006.252.07:37:10.21#ibcon#about to read 6, iclass 20, count 0 2006.252.07:37:10.21#ibcon#read 6, iclass 20, count 0 2006.252.07:37:10.21#ibcon#end of sib2, iclass 20, count 0 2006.252.07:37:10.21#ibcon#*after write, iclass 20, count 0 2006.252.07:37:10.21#ibcon#*before return 0, iclass 20, count 0 2006.252.07:37:10.21#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.252.07:37:10.21#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.252.07:37:10.21#ibcon#about to clear, iclass 20 cls_cnt 0 2006.252.07:37:10.22#ibcon#cleared, iclass 20 cls_cnt 0 2006.252.07:37:10.22$vc4f8/valo=8,852.99 2006.252.07:37:10.22#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.252.07:37:10.22#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.252.07:37:10.22#ibcon#ireg 17 cls_cnt 0 2006.252.07:37:10.22#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.252.07:37:10.22#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.252.07:37:10.22#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.252.07:37:10.22#ibcon#enter wrdev, iclass 22, count 0 2006.252.07:37:10.22#ibcon#first serial, iclass 22, count 0 2006.252.07:37:10.22#ibcon#enter sib2, iclass 22, count 0 2006.252.07:37:10.22#ibcon#flushed, iclass 22, count 0 2006.252.07:37:10.22#ibcon#about to write, iclass 22, count 0 2006.252.07:37:10.22#ibcon#wrote, iclass 22, count 0 2006.252.07:37:10.22#ibcon#about to read 3, iclass 22, count 0 2006.252.07:37:10.23#ibcon#read 3, iclass 22, count 0 2006.252.07:37:10.23#ibcon#about to read 4, iclass 22, count 0 2006.252.07:37:10.23#ibcon#read 4, iclass 22, count 0 2006.252.07:37:10.23#ibcon#about to read 5, iclass 22, count 0 2006.252.07:37:10.23#ibcon#read 5, iclass 22, count 0 2006.252.07:37:10.23#ibcon#about to read 6, iclass 22, count 0 2006.252.07:37:10.23#ibcon#read 6, iclass 22, count 0 2006.252.07:37:10.23#ibcon#end of sib2, iclass 22, count 0 2006.252.07:37:10.23#ibcon#*mode == 0, iclass 22, count 0 2006.252.07:37:10.23#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.252.07:37:10.23#ibcon#[26=FRQ=08,852.99\r\n] 2006.252.07:37:10.23#ibcon#*before write, iclass 22, count 0 2006.252.07:37:10.23#ibcon#enter sib2, iclass 22, count 0 2006.252.07:37:10.24#ibcon#flushed, iclass 22, count 0 2006.252.07:37:10.24#ibcon#about to write, iclass 22, count 0 2006.252.07:37:10.24#ibcon#wrote, iclass 22, count 0 2006.252.07:37:10.24#ibcon#about to read 3, iclass 22, count 0 2006.252.07:37:10.27#ibcon#read 3, iclass 22, count 0 2006.252.07:37:10.27#ibcon#about to read 4, iclass 22, count 0 2006.252.07:37:10.27#ibcon#read 4, iclass 22, count 0 2006.252.07:37:10.27#ibcon#about to read 5, iclass 22, count 0 2006.252.07:37:10.27#ibcon#read 5, iclass 22, count 0 2006.252.07:37:10.27#ibcon#about to read 6, iclass 22, count 0 2006.252.07:37:10.27#ibcon#read 6, iclass 22, count 0 2006.252.07:37:10.27#ibcon#end of sib2, iclass 22, count 0 2006.252.07:37:10.27#ibcon#*after write, iclass 22, count 0 2006.252.07:37:10.27#ibcon#*before return 0, iclass 22, count 0 2006.252.07:37:10.27#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.252.07:37:10.27#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.252.07:37:10.27#ibcon#about to clear, iclass 22 cls_cnt 0 2006.252.07:37:10.28#ibcon#cleared, iclass 22 cls_cnt 0 2006.252.07:37:10.28$vc4f8/va=8,7 2006.252.07:37:10.28#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.252.07:37:10.28#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.252.07:37:10.28#ibcon#ireg 11 cls_cnt 2 2006.252.07:37:10.28#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.252.07:37:10.33#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.252.07:37:10.33#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.252.07:37:10.33#ibcon#enter wrdev, iclass 24, count 2 2006.252.07:37:10.33#ibcon#first serial, iclass 24, count 2 2006.252.07:37:10.33#ibcon#enter sib2, iclass 24, count 2 2006.252.07:37:10.33#ibcon#flushed, iclass 24, count 2 2006.252.07:37:10.33#ibcon#about to write, iclass 24, count 2 2006.252.07:37:10.33#ibcon#wrote, iclass 24, count 2 2006.252.07:37:10.33#ibcon#about to read 3, iclass 24, count 2 2006.252.07:37:10.34#ibcon#read 3, iclass 24, count 2 2006.252.07:37:10.34#ibcon#about to read 4, iclass 24, count 2 2006.252.07:37:10.34#ibcon#read 4, iclass 24, count 2 2006.252.07:37:10.34#ibcon#about to read 5, iclass 24, count 2 2006.252.07:37:10.34#ibcon#read 5, iclass 24, count 2 2006.252.07:37:10.34#ibcon#about to read 6, iclass 24, count 2 2006.252.07:37:10.34#ibcon#read 6, iclass 24, count 2 2006.252.07:37:10.34#ibcon#end of sib2, iclass 24, count 2 2006.252.07:37:10.34#ibcon#*mode == 0, iclass 24, count 2 2006.252.07:37:10.34#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.252.07:37:10.34#ibcon#[25=AT08-07\r\n] 2006.252.07:37:10.35#ibcon#*before write, iclass 24, count 2 2006.252.07:37:10.35#ibcon#enter sib2, iclass 24, count 2 2006.252.07:37:10.35#ibcon#flushed, iclass 24, count 2 2006.252.07:37:10.35#ibcon#about to write, iclass 24, count 2 2006.252.07:37:10.35#ibcon#wrote, iclass 24, count 2 2006.252.07:37:10.35#ibcon#about to read 3, iclass 24, count 2 2006.252.07:37:10.37#ibcon#read 3, iclass 24, count 2 2006.252.07:37:10.37#ibcon#about to read 4, iclass 24, count 2 2006.252.07:37:10.37#ibcon#read 4, iclass 24, count 2 2006.252.07:37:10.37#ibcon#about to read 5, iclass 24, count 2 2006.252.07:37:10.37#ibcon#read 5, iclass 24, count 2 2006.252.07:37:10.37#ibcon#about to read 6, iclass 24, count 2 2006.252.07:37:10.37#ibcon#read 6, iclass 24, count 2 2006.252.07:37:10.37#ibcon#end of sib2, iclass 24, count 2 2006.252.07:37:10.37#ibcon#*after write, iclass 24, count 2 2006.252.07:37:10.37#ibcon#*before return 0, iclass 24, count 2 2006.252.07:37:10.37#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.252.07:37:10.37#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.252.07:37:10.37#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.252.07:37:10.38#ibcon#ireg 7 cls_cnt 0 2006.252.07:37:10.38#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.252.07:37:10.48#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.252.07:37:10.48#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.252.07:37:10.48#ibcon#enter wrdev, iclass 24, count 0 2006.252.07:37:10.48#ibcon#first serial, iclass 24, count 0 2006.252.07:37:10.48#ibcon#enter sib2, iclass 24, count 0 2006.252.07:37:10.48#ibcon#flushed, iclass 24, count 0 2006.252.07:37:10.48#ibcon#about to write, iclass 24, count 0 2006.252.07:37:10.48#ibcon#wrote, iclass 24, count 0 2006.252.07:37:10.48#ibcon#about to read 3, iclass 24, count 0 2006.252.07:37:10.50#ibcon#read 3, iclass 24, count 0 2006.252.07:37:10.50#ibcon#about to read 4, iclass 24, count 0 2006.252.07:37:10.50#ibcon#read 4, iclass 24, count 0 2006.252.07:37:10.50#ibcon#about to read 5, iclass 24, count 0 2006.252.07:37:10.50#ibcon#read 5, iclass 24, count 0 2006.252.07:37:10.50#ibcon#about to read 6, iclass 24, count 0 2006.252.07:37:10.50#ibcon#read 6, iclass 24, count 0 2006.252.07:37:10.50#ibcon#end of sib2, iclass 24, count 0 2006.252.07:37:10.50#ibcon#*mode == 0, iclass 24, count 0 2006.252.07:37:10.50#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.252.07:37:10.50#ibcon#[25=USB\r\n] 2006.252.07:37:10.50#ibcon#*before write, iclass 24, count 0 2006.252.07:37:10.50#ibcon#enter sib2, iclass 24, count 0 2006.252.07:37:10.50#ibcon#flushed, iclass 24, count 0 2006.252.07:37:10.50#ibcon#about to write, iclass 24, count 0 2006.252.07:37:10.51#ibcon#wrote, iclass 24, count 0 2006.252.07:37:10.51#ibcon#about to read 3, iclass 24, count 0 2006.252.07:37:10.53#ibcon#read 3, iclass 24, count 0 2006.252.07:37:10.53#ibcon#about to read 4, iclass 24, count 0 2006.252.07:37:10.53#ibcon#read 4, iclass 24, count 0 2006.252.07:37:10.53#ibcon#about to read 5, iclass 24, count 0 2006.252.07:37:10.53#ibcon#read 5, iclass 24, count 0 2006.252.07:37:10.53#ibcon#about to read 6, iclass 24, count 0 2006.252.07:37:10.53#ibcon#read 6, iclass 24, count 0 2006.252.07:37:10.53#ibcon#end of sib2, iclass 24, count 0 2006.252.07:37:10.53#ibcon#*after write, iclass 24, count 0 2006.252.07:37:10.53#ibcon#*before return 0, iclass 24, count 0 2006.252.07:37:10.53#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.252.07:37:10.54#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.252.07:37:10.54#ibcon#about to clear, iclass 24 cls_cnt 0 2006.252.07:37:10.54#ibcon#cleared, iclass 24 cls_cnt 0 2006.252.07:37:10.54$vc4f8/vblo=1,632.99 2006.252.07:37:10.54#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.252.07:37:10.54#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.252.07:37:10.54#ibcon#ireg 17 cls_cnt 0 2006.252.07:37:10.54#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.252.07:37:10.54#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.252.07:37:10.54#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.252.07:37:10.54#ibcon#enter wrdev, iclass 26, count 0 2006.252.07:37:10.54#ibcon#first serial, iclass 26, count 0 2006.252.07:37:10.54#ibcon#enter sib2, iclass 26, count 0 2006.252.07:37:10.54#ibcon#flushed, iclass 26, count 0 2006.252.07:37:10.54#ibcon#about to write, iclass 26, count 0 2006.252.07:37:10.54#ibcon#wrote, iclass 26, count 0 2006.252.07:37:10.54#ibcon#about to read 3, iclass 26, count 0 2006.252.07:37:10.55#ibcon#read 3, iclass 26, count 0 2006.252.07:37:10.55#ibcon#about to read 4, iclass 26, count 0 2006.252.07:37:10.55#ibcon#read 4, iclass 26, count 0 2006.252.07:37:10.55#ibcon#about to read 5, iclass 26, count 0 2006.252.07:37:10.55#ibcon#read 5, iclass 26, count 0 2006.252.07:37:10.55#ibcon#about to read 6, iclass 26, count 0 2006.252.07:37:10.55#ibcon#read 6, iclass 26, count 0 2006.252.07:37:10.55#ibcon#end of sib2, iclass 26, count 0 2006.252.07:37:10.55#ibcon#*mode == 0, iclass 26, count 0 2006.252.07:37:10.55#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.252.07:37:10.55#ibcon#[28=FRQ=01,632.99\r\n] 2006.252.07:37:10.55#ibcon#*before write, iclass 26, count 0 2006.252.07:37:10.55#ibcon#enter sib2, iclass 26, count 0 2006.252.07:37:10.55#ibcon#flushed, iclass 26, count 0 2006.252.07:37:10.56#ibcon#about to write, iclass 26, count 0 2006.252.07:37:10.56#ibcon#wrote, iclass 26, count 0 2006.252.07:37:10.56#ibcon#about to read 3, iclass 26, count 0 2006.252.07:37:10.59#ibcon#read 3, iclass 26, count 0 2006.252.07:37:10.59#ibcon#about to read 4, iclass 26, count 0 2006.252.07:37:10.59#ibcon#read 4, iclass 26, count 0 2006.252.07:37:10.59#ibcon#about to read 5, iclass 26, count 0 2006.252.07:37:10.59#ibcon#read 5, iclass 26, count 0 2006.252.07:37:10.59#ibcon#about to read 6, iclass 26, count 0 2006.252.07:37:10.59#ibcon#read 6, iclass 26, count 0 2006.252.07:37:10.59#ibcon#end of sib2, iclass 26, count 0 2006.252.07:37:10.59#ibcon#*after write, iclass 26, count 0 2006.252.07:37:10.59#ibcon#*before return 0, iclass 26, count 0 2006.252.07:37:10.59#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.252.07:37:10.59#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.252.07:37:10.59#ibcon#about to clear, iclass 26 cls_cnt 0 2006.252.07:37:10.59#ibcon#cleared, iclass 26 cls_cnt 0 2006.252.07:37:10.60$vc4f8/vb=1,4 2006.252.07:37:10.60#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.252.07:37:10.60#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.252.07:37:10.60#ibcon#ireg 11 cls_cnt 2 2006.252.07:37:10.60#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.252.07:37:10.60#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.252.07:37:10.60#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.252.07:37:10.60#ibcon#enter wrdev, iclass 28, count 2 2006.252.07:37:10.60#ibcon#first serial, iclass 28, count 2 2006.252.07:37:10.60#ibcon#enter sib2, iclass 28, count 2 2006.252.07:37:10.60#ibcon#flushed, iclass 28, count 2 2006.252.07:37:10.60#ibcon#about to write, iclass 28, count 2 2006.252.07:37:10.60#ibcon#wrote, iclass 28, count 2 2006.252.07:37:10.60#ibcon#about to read 3, iclass 28, count 2 2006.252.07:37:10.61#ibcon#read 3, iclass 28, count 2 2006.252.07:37:10.61#ibcon#about to read 4, iclass 28, count 2 2006.252.07:37:10.61#ibcon#read 4, iclass 28, count 2 2006.252.07:37:10.61#ibcon#about to read 5, iclass 28, count 2 2006.252.07:37:10.61#ibcon#read 5, iclass 28, count 2 2006.252.07:37:10.61#ibcon#about to read 6, iclass 28, count 2 2006.252.07:37:10.61#ibcon#read 6, iclass 28, count 2 2006.252.07:37:10.61#ibcon#end of sib2, iclass 28, count 2 2006.252.07:37:10.61#ibcon#*mode == 0, iclass 28, count 2 2006.252.07:37:10.61#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.252.07:37:10.61#ibcon#[27=AT01-04\r\n] 2006.252.07:37:10.61#ibcon#*before write, iclass 28, count 2 2006.252.07:37:10.61#ibcon#enter sib2, iclass 28, count 2 2006.252.07:37:10.61#ibcon#flushed, iclass 28, count 2 2006.252.07:37:10.62#ibcon#about to write, iclass 28, count 2 2006.252.07:37:10.62#ibcon#wrote, iclass 28, count 2 2006.252.07:37:10.62#ibcon#about to read 3, iclass 28, count 2 2006.252.07:37:10.64#ibcon#read 3, iclass 28, count 2 2006.252.07:37:10.64#ibcon#about to read 4, iclass 28, count 2 2006.252.07:37:10.64#ibcon#read 4, iclass 28, count 2 2006.252.07:37:10.64#ibcon#about to read 5, iclass 28, count 2 2006.252.07:37:10.64#ibcon#read 5, iclass 28, count 2 2006.252.07:37:10.64#ibcon#about to read 6, iclass 28, count 2 2006.252.07:37:10.64#ibcon#read 6, iclass 28, count 2 2006.252.07:37:10.64#ibcon#end of sib2, iclass 28, count 2 2006.252.07:37:10.64#ibcon#*after write, iclass 28, count 2 2006.252.07:37:10.64#ibcon#*before return 0, iclass 28, count 2 2006.252.07:37:10.64#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.252.07:37:10.64#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.252.07:37:10.64#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.252.07:37:10.65#ibcon#ireg 7 cls_cnt 0 2006.252.07:37:10.65#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.252.07:37:10.75#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.252.07:37:10.75#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.252.07:37:10.75#ibcon#enter wrdev, iclass 28, count 0 2006.252.07:37:10.75#ibcon#first serial, iclass 28, count 0 2006.252.07:37:10.75#ibcon#enter sib2, iclass 28, count 0 2006.252.07:37:10.75#ibcon#flushed, iclass 28, count 0 2006.252.07:37:10.75#ibcon#about to write, iclass 28, count 0 2006.252.07:37:10.75#ibcon#wrote, iclass 28, count 0 2006.252.07:37:10.75#ibcon#about to read 3, iclass 28, count 0 2006.252.07:37:10.77#ibcon#read 3, iclass 28, count 0 2006.252.07:37:10.77#ibcon#about to read 4, iclass 28, count 0 2006.252.07:37:10.77#ibcon#read 4, iclass 28, count 0 2006.252.07:37:10.77#ibcon#about to read 5, iclass 28, count 0 2006.252.07:37:10.77#ibcon#read 5, iclass 28, count 0 2006.252.07:37:10.77#ibcon#about to read 6, iclass 28, count 0 2006.252.07:37:10.77#ibcon#read 6, iclass 28, count 0 2006.252.07:37:10.77#ibcon#end of sib2, iclass 28, count 0 2006.252.07:37:10.77#ibcon#*mode == 0, iclass 28, count 0 2006.252.07:37:10.77#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.252.07:37:10.77#ibcon#[27=USB\r\n] 2006.252.07:37:10.77#ibcon#*before write, iclass 28, count 0 2006.252.07:37:10.77#ibcon#enter sib2, iclass 28, count 0 2006.252.07:37:10.77#ibcon#flushed, iclass 28, count 0 2006.252.07:37:10.77#ibcon#about to write, iclass 28, count 0 2006.252.07:37:10.78#ibcon#wrote, iclass 28, count 0 2006.252.07:37:10.78#ibcon#about to read 3, iclass 28, count 0 2006.252.07:37:10.80#ibcon#read 3, iclass 28, count 0 2006.252.07:37:10.80#ibcon#about to read 4, iclass 28, count 0 2006.252.07:37:10.80#ibcon#read 4, iclass 28, count 0 2006.252.07:37:10.80#ibcon#about to read 5, iclass 28, count 0 2006.252.07:37:10.80#ibcon#read 5, iclass 28, count 0 2006.252.07:37:10.80#ibcon#about to read 6, iclass 28, count 0 2006.252.07:37:10.80#ibcon#read 6, iclass 28, count 0 2006.252.07:37:10.80#ibcon#end of sib2, iclass 28, count 0 2006.252.07:37:10.80#ibcon#*after write, iclass 28, count 0 2006.252.07:37:10.80#ibcon#*before return 0, iclass 28, count 0 2006.252.07:37:10.81#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.252.07:37:10.81#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.252.07:37:10.81#ibcon#about to clear, iclass 28 cls_cnt 0 2006.252.07:37:10.81#ibcon#cleared, iclass 28 cls_cnt 0 2006.252.07:37:10.81$vc4f8/vblo=2,640.99 2006.252.07:37:10.81#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.252.07:37:10.81#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.252.07:37:10.81#ibcon#ireg 17 cls_cnt 0 2006.252.07:37:10.81#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.252.07:37:10.81#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.252.07:37:10.81#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.252.07:37:10.81#ibcon#enter wrdev, iclass 30, count 0 2006.252.07:37:10.81#ibcon#first serial, iclass 30, count 0 2006.252.07:37:10.81#ibcon#enter sib2, iclass 30, count 0 2006.252.07:37:10.81#ibcon#flushed, iclass 30, count 0 2006.252.07:37:10.81#ibcon#about to write, iclass 30, count 0 2006.252.07:37:10.81#ibcon#wrote, iclass 30, count 0 2006.252.07:37:10.81#ibcon#about to read 3, iclass 30, count 0 2006.252.07:37:10.82#ibcon#read 3, iclass 30, count 0 2006.252.07:37:10.82#ibcon#about to read 4, iclass 30, count 0 2006.252.07:37:10.82#ibcon#read 4, iclass 30, count 0 2006.252.07:37:10.82#ibcon#about to read 5, iclass 30, count 0 2006.252.07:37:10.82#ibcon#read 5, iclass 30, count 0 2006.252.07:37:10.82#ibcon#about to read 6, iclass 30, count 0 2006.252.07:37:10.82#ibcon#read 6, iclass 30, count 0 2006.252.07:37:10.82#ibcon#end of sib2, iclass 30, count 0 2006.252.07:37:10.82#ibcon#*mode == 0, iclass 30, count 0 2006.252.07:37:10.82#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.252.07:37:10.82#ibcon#[28=FRQ=02,640.99\r\n] 2006.252.07:37:10.82#ibcon#*before write, iclass 30, count 0 2006.252.07:37:10.82#ibcon#enter sib2, iclass 30, count 0 2006.252.07:37:10.82#ibcon#flushed, iclass 30, count 0 2006.252.07:37:10.83#ibcon#about to write, iclass 30, count 0 2006.252.07:37:10.83#ibcon#wrote, iclass 30, count 0 2006.252.07:37:10.83#ibcon#about to read 3, iclass 30, count 0 2006.252.07:37:10.86#ibcon#read 3, iclass 30, count 0 2006.252.07:37:10.86#ibcon#about to read 4, iclass 30, count 0 2006.252.07:37:10.86#ibcon#read 4, iclass 30, count 0 2006.252.07:37:10.86#ibcon#about to read 5, iclass 30, count 0 2006.252.07:37:10.86#ibcon#read 5, iclass 30, count 0 2006.252.07:37:10.86#ibcon#about to read 6, iclass 30, count 0 2006.252.07:37:10.86#ibcon#read 6, iclass 30, count 0 2006.252.07:37:10.86#ibcon#end of sib2, iclass 30, count 0 2006.252.07:37:10.86#ibcon#*after write, iclass 30, count 0 2006.252.07:37:10.86#ibcon#*before return 0, iclass 30, count 0 2006.252.07:37:10.86#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.252.07:37:10.87#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.252.07:37:10.87#ibcon#about to clear, iclass 30 cls_cnt 0 2006.252.07:37:10.87#ibcon#cleared, iclass 30 cls_cnt 0 2006.252.07:37:10.87$vc4f8/vb=2,5 2006.252.07:37:10.87#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.252.07:37:10.87#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.252.07:37:10.87#ibcon#ireg 11 cls_cnt 2 2006.252.07:37:10.87#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.252.07:37:10.92#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.252.07:37:10.92#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.252.07:37:10.92#ibcon#enter wrdev, iclass 32, count 2 2006.252.07:37:10.92#ibcon#first serial, iclass 32, count 2 2006.252.07:37:10.92#ibcon#enter sib2, iclass 32, count 2 2006.252.07:37:10.92#ibcon#flushed, iclass 32, count 2 2006.252.07:37:10.92#ibcon#about to write, iclass 32, count 2 2006.252.07:37:10.92#ibcon#wrote, iclass 32, count 2 2006.252.07:37:10.92#ibcon#about to read 3, iclass 32, count 2 2006.252.07:37:10.94#ibcon#read 3, iclass 32, count 2 2006.252.07:37:10.94#ibcon#about to read 4, iclass 32, count 2 2006.252.07:37:10.94#ibcon#read 4, iclass 32, count 2 2006.252.07:37:10.94#ibcon#about to read 5, iclass 32, count 2 2006.252.07:37:10.94#ibcon#read 5, iclass 32, count 2 2006.252.07:37:10.94#ibcon#about to read 6, iclass 32, count 2 2006.252.07:37:10.94#ibcon#read 6, iclass 32, count 2 2006.252.07:37:10.94#ibcon#end of sib2, iclass 32, count 2 2006.252.07:37:10.94#ibcon#*mode == 0, iclass 32, count 2 2006.252.07:37:10.94#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.252.07:37:10.94#ibcon#[27=AT02-05\r\n] 2006.252.07:37:10.94#ibcon#*before write, iclass 32, count 2 2006.252.07:37:10.94#ibcon#enter sib2, iclass 32, count 2 2006.252.07:37:10.94#ibcon#flushed, iclass 32, count 2 2006.252.07:37:10.94#ibcon#about to write, iclass 32, count 2 2006.252.07:37:10.95#ibcon#wrote, iclass 32, count 2 2006.252.07:37:10.95#ibcon#about to read 3, iclass 32, count 2 2006.252.07:37:10.97#ibcon#read 3, iclass 32, count 2 2006.252.07:37:10.97#ibcon#about to read 4, iclass 32, count 2 2006.252.07:37:10.97#ibcon#read 4, iclass 32, count 2 2006.252.07:37:10.97#ibcon#about to read 5, iclass 32, count 2 2006.252.07:37:10.97#ibcon#read 5, iclass 32, count 2 2006.252.07:37:10.97#ibcon#about to read 6, iclass 32, count 2 2006.252.07:37:10.97#ibcon#read 6, iclass 32, count 2 2006.252.07:37:10.97#ibcon#end of sib2, iclass 32, count 2 2006.252.07:37:10.97#ibcon#*after write, iclass 32, count 2 2006.252.07:37:10.97#ibcon#*before return 0, iclass 32, count 2 2006.252.07:37:10.97#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.252.07:37:10.97#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.252.07:37:10.97#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.252.07:37:10.97#ibcon#ireg 7 cls_cnt 0 2006.252.07:37:10.98#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.252.07:37:11.08#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.252.07:37:11.08#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.252.07:37:11.08#ibcon#enter wrdev, iclass 32, count 0 2006.252.07:37:11.08#ibcon#first serial, iclass 32, count 0 2006.252.07:37:11.08#ibcon#enter sib2, iclass 32, count 0 2006.252.07:37:11.08#ibcon#flushed, iclass 32, count 0 2006.252.07:37:11.08#ibcon#about to write, iclass 32, count 0 2006.252.07:37:11.08#ibcon#wrote, iclass 32, count 0 2006.252.07:37:11.08#ibcon#about to read 3, iclass 32, count 0 2006.252.07:37:11.10#ibcon#read 3, iclass 32, count 0 2006.252.07:37:11.10#ibcon#about to read 4, iclass 32, count 0 2006.252.07:37:11.10#ibcon#read 4, iclass 32, count 0 2006.252.07:37:11.10#ibcon#about to read 5, iclass 32, count 0 2006.252.07:37:11.10#ibcon#read 5, iclass 32, count 0 2006.252.07:37:11.10#ibcon#about to read 6, iclass 32, count 0 2006.252.07:37:11.10#ibcon#read 6, iclass 32, count 0 2006.252.07:37:11.10#ibcon#end of sib2, iclass 32, count 0 2006.252.07:37:11.10#ibcon#*mode == 0, iclass 32, count 0 2006.252.07:37:11.10#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.252.07:37:11.10#ibcon#[27=USB\r\n] 2006.252.07:37:11.10#ibcon#*before write, iclass 32, count 0 2006.252.07:37:11.10#ibcon#enter sib2, iclass 32, count 0 2006.252.07:37:11.10#ibcon#flushed, iclass 32, count 0 2006.252.07:37:11.10#ibcon#about to write, iclass 32, count 0 2006.252.07:37:11.11#ibcon#wrote, iclass 32, count 0 2006.252.07:37:11.11#ibcon#about to read 3, iclass 32, count 0 2006.252.07:37:11.13#ibcon#read 3, iclass 32, count 0 2006.252.07:37:11.13#ibcon#about to read 4, iclass 32, count 0 2006.252.07:37:11.13#ibcon#read 4, iclass 32, count 0 2006.252.07:37:11.13#ibcon#about to read 5, iclass 32, count 0 2006.252.07:37:11.13#ibcon#read 5, iclass 32, count 0 2006.252.07:37:11.13#ibcon#about to read 6, iclass 32, count 0 2006.252.07:37:11.13#ibcon#read 6, iclass 32, count 0 2006.252.07:37:11.13#ibcon#end of sib2, iclass 32, count 0 2006.252.07:37:11.13#ibcon#*after write, iclass 32, count 0 2006.252.07:37:11.13#ibcon#*before return 0, iclass 32, count 0 2006.252.07:37:11.13#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.252.07:37:11.13#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.252.07:37:11.13#ibcon#about to clear, iclass 32 cls_cnt 0 2006.252.07:37:11.14#ibcon#cleared, iclass 32 cls_cnt 0 2006.252.07:37:11.14$vc4f8/vblo=3,656.99 2006.252.07:37:11.14#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.252.07:37:11.14#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.252.07:37:11.14#ibcon#ireg 17 cls_cnt 0 2006.252.07:37:11.14#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.252.07:37:11.14#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.252.07:37:11.14#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.252.07:37:11.14#ibcon#enter wrdev, iclass 34, count 0 2006.252.07:37:11.14#ibcon#first serial, iclass 34, count 0 2006.252.07:37:11.14#ibcon#enter sib2, iclass 34, count 0 2006.252.07:37:11.14#ibcon#flushed, iclass 34, count 0 2006.252.07:37:11.14#ibcon#about to write, iclass 34, count 0 2006.252.07:37:11.14#ibcon#wrote, iclass 34, count 0 2006.252.07:37:11.14#ibcon#about to read 3, iclass 34, count 0 2006.252.07:37:11.15#ibcon#read 3, iclass 34, count 0 2006.252.07:37:11.15#ibcon#about to read 4, iclass 34, count 0 2006.252.07:37:11.15#ibcon#read 4, iclass 34, count 0 2006.252.07:37:11.15#ibcon#about to read 5, iclass 34, count 0 2006.252.07:37:11.15#ibcon#read 5, iclass 34, count 0 2006.252.07:37:11.15#ibcon#about to read 6, iclass 34, count 0 2006.252.07:37:11.15#ibcon#read 6, iclass 34, count 0 2006.252.07:37:11.15#ibcon#end of sib2, iclass 34, count 0 2006.252.07:37:11.15#ibcon#*mode == 0, iclass 34, count 0 2006.252.07:37:11.15#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.252.07:37:11.15#ibcon#[28=FRQ=03,656.99\r\n] 2006.252.07:37:11.15#ibcon#*before write, iclass 34, count 0 2006.252.07:37:11.15#ibcon#enter sib2, iclass 34, count 0 2006.252.07:37:11.15#ibcon#flushed, iclass 34, count 0 2006.252.07:37:11.16#ibcon#about to write, iclass 34, count 0 2006.252.07:37:11.16#ibcon#wrote, iclass 34, count 0 2006.252.07:37:11.16#ibcon#about to read 3, iclass 34, count 0 2006.252.07:37:11.19#ibcon#read 3, iclass 34, count 0 2006.252.07:37:11.19#ibcon#about to read 4, iclass 34, count 0 2006.252.07:37:11.19#ibcon#read 4, iclass 34, count 0 2006.252.07:37:11.19#ibcon#about to read 5, iclass 34, count 0 2006.252.07:37:11.19#ibcon#read 5, iclass 34, count 0 2006.252.07:37:11.19#ibcon#about to read 6, iclass 34, count 0 2006.252.07:37:11.19#ibcon#read 6, iclass 34, count 0 2006.252.07:37:11.19#ibcon#end of sib2, iclass 34, count 0 2006.252.07:37:11.19#ibcon#*after write, iclass 34, count 0 2006.252.07:37:11.19#ibcon#*before return 0, iclass 34, count 0 2006.252.07:37:11.19#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.252.07:37:11.19#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.252.07:37:11.19#ibcon#about to clear, iclass 34 cls_cnt 0 2006.252.07:37:11.19#ibcon#cleared, iclass 34 cls_cnt 0 2006.252.07:37:11.20$vc4f8/vb=3,4 2006.252.07:37:11.20#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.252.07:37:11.20#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.252.07:37:11.20#ibcon#ireg 11 cls_cnt 2 2006.252.07:37:11.20#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.252.07:37:11.24#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.252.07:37:11.24#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.252.07:37:11.24#ibcon#enter wrdev, iclass 36, count 2 2006.252.07:37:11.24#ibcon#first serial, iclass 36, count 2 2006.252.07:37:11.24#ibcon#enter sib2, iclass 36, count 2 2006.252.07:37:11.24#ibcon#flushed, iclass 36, count 2 2006.252.07:37:11.24#ibcon#about to write, iclass 36, count 2 2006.252.07:37:11.24#ibcon#wrote, iclass 36, count 2 2006.252.07:37:11.24#ibcon#about to read 3, iclass 36, count 2 2006.252.07:37:11.26#ibcon#read 3, iclass 36, count 2 2006.252.07:37:11.26#ibcon#about to read 4, iclass 36, count 2 2006.252.07:37:11.26#ibcon#read 4, iclass 36, count 2 2006.252.07:37:11.26#ibcon#about to read 5, iclass 36, count 2 2006.252.07:37:11.26#ibcon#read 5, iclass 36, count 2 2006.252.07:37:11.26#ibcon#about to read 6, iclass 36, count 2 2006.252.07:37:11.26#ibcon#read 6, iclass 36, count 2 2006.252.07:37:11.26#ibcon#end of sib2, iclass 36, count 2 2006.252.07:37:11.26#ibcon#*mode == 0, iclass 36, count 2 2006.252.07:37:11.26#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.252.07:37:11.26#ibcon#[27=AT03-04\r\n] 2006.252.07:37:11.26#ibcon#*before write, iclass 36, count 2 2006.252.07:37:11.26#ibcon#enter sib2, iclass 36, count 2 2006.252.07:37:11.26#ibcon#flushed, iclass 36, count 2 2006.252.07:37:11.27#ibcon#about to write, iclass 36, count 2 2006.252.07:37:11.27#ibcon#wrote, iclass 36, count 2 2006.252.07:37:11.27#ibcon#about to read 3, iclass 36, count 2 2006.252.07:37:11.29#ibcon#read 3, iclass 36, count 2 2006.252.07:37:11.29#ibcon#about to read 4, iclass 36, count 2 2006.252.07:37:11.29#ibcon#read 4, iclass 36, count 2 2006.252.07:37:11.29#ibcon#about to read 5, iclass 36, count 2 2006.252.07:37:11.29#ibcon#read 5, iclass 36, count 2 2006.252.07:37:11.29#ibcon#about to read 6, iclass 36, count 2 2006.252.07:37:11.29#ibcon#read 6, iclass 36, count 2 2006.252.07:37:11.29#ibcon#end of sib2, iclass 36, count 2 2006.252.07:37:11.29#ibcon#*after write, iclass 36, count 2 2006.252.07:37:11.29#ibcon#*before return 0, iclass 36, count 2 2006.252.07:37:11.29#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.252.07:37:11.29#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.252.07:37:11.30#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.252.07:37:11.30#ibcon#ireg 7 cls_cnt 0 2006.252.07:37:11.30#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.252.07:37:11.40#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.252.07:37:11.40#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.252.07:37:11.40#ibcon#enter wrdev, iclass 36, count 0 2006.252.07:37:11.40#ibcon#first serial, iclass 36, count 0 2006.252.07:37:11.40#ibcon#enter sib2, iclass 36, count 0 2006.252.07:37:11.40#ibcon#flushed, iclass 36, count 0 2006.252.07:37:11.40#ibcon#about to write, iclass 36, count 0 2006.252.07:37:11.40#ibcon#wrote, iclass 36, count 0 2006.252.07:37:11.40#ibcon#about to read 3, iclass 36, count 0 2006.252.07:37:11.42#ibcon#read 3, iclass 36, count 0 2006.252.07:37:11.42#ibcon#about to read 4, iclass 36, count 0 2006.252.07:37:11.42#ibcon#read 4, iclass 36, count 0 2006.252.07:37:11.42#ibcon#about to read 5, iclass 36, count 0 2006.252.07:37:11.42#ibcon#read 5, iclass 36, count 0 2006.252.07:37:11.42#ibcon#about to read 6, iclass 36, count 0 2006.252.07:37:11.42#ibcon#read 6, iclass 36, count 0 2006.252.07:37:11.42#ibcon#end of sib2, iclass 36, count 0 2006.252.07:37:11.42#ibcon#*mode == 0, iclass 36, count 0 2006.252.07:37:11.42#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.252.07:37:11.42#ibcon#[27=USB\r\n] 2006.252.07:37:11.42#ibcon#*before write, iclass 36, count 0 2006.252.07:37:11.42#ibcon#enter sib2, iclass 36, count 0 2006.252.07:37:11.42#ibcon#flushed, iclass 36, count 0 2006.252.07:37:11.42#ibcon#about to write, iclass 36, count 0 2006.252.07:37:11.43#ibcon#wrote, iclass 36, count 0 2006.252.07:37:11.43#ibcon#about to read 3, iclass 36, count 0 2006.252.07:37:11.45#ibcon#read 3, iclass 36, count 0 2006.252.07:37:11.45#ibcon#about to read 4, iclass 36, count 0 2006.252.07:37:11.45#ibcon#read 4, iclass 36, count 0 2006.252.07:37:11.45#ibcon#about to read 5, iclass 36, count 0 2006.252.07:37:11.45#ibcon#read 5, iclass 36, count 0 2006.252.07:37:11.45#ibcon#about to read 6, iclass 36, count 0 2006.252.07:37:11.45#ibcon#read 6, iclass 36, count 0 2006.252.07:37:11.45#ibcon#end of sib2, iclass 36, count 0 2006.252.07:37:11.45#ibcon#*after write, iclass 36, count 0 2006.252.07:37:11.45#ibcon#*before return 0, iclass 36, count 0 2006.252.07:37:11.45#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.252.07:37:11.45#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.252.07:37:11.45#ibcon#about to clear, iclass 36 cls_cnt 0 2006.252.07:37:11.46#ibcon#cleared, iclass 36 cls_cnt 0 2006.252.07:37:11.46$vc4f8/vblo=4,712.99 2006.252.07:37:11.46#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.252.07:37:11.46#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.252.07:37:11.46#ibcon#ireg 17 cls_cnt 0 2006.252.07:37:11.46#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.252.07:37:11.46#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.252.07:37:11.46#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.252.07:37:11.46#ibcon#enter wrdev, iclass 38, count 0 2006.252.07:37:11.46#ibcon#first serial, iclass 38, count 0 2006.252.07:37:11.46#ibcon#enter sib2, iclass 38, count 0 2006.252.07:37:11.46#ibcon#flushed, iclass 38, count 0 2006.252.07:37:11.46#ibcon#about to write, iclass 38, count 0 2006.252.07:37:11.46#ibcon#wrote, iclass 38, count 0 2006.252.07:37:11.46#ibcon#about to read 3, iclass 38, count 0 2006.252.07:37:11.47#ibcon#read 3, iclass 38, count 0 2006.252.07:37:11.47#ibcon#about to read 4, iclass 38, count 0 2006.252.07:37:11.47#ibcon#read 4, iclass 38, count 0 2006.252.07:37:11.47#ibcon#about to read 5, iclass 38, count 0 2006.252.07:37:11.47#ibcon#read 5, iclass 38, count 0 2006.252.07:37:11.47#ibcon#about to read 6, iclass 38, count 0 2006.252.07:37:11.47#ibcon#read 6, iclass 38, count 0 2006.252.07:37:11.47#ibcon#end of sib2, iclass 38, count 0 2006.252.07:37:11.47#ibcon#*mode == 0, iclass 38, count 0 2006.252.07:37:11.47#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.252.07:37:11.47#ibcon#[28=FRQ=04,712.99\r\n] 2006.252.07:37:11.47#ibcon#*before write, iclass 38, count 0 2006.252.07:37:11.47#ibcon#enter sib2, iclass 38, count 0 2006.252.07:37:11.47#ibcon#flushed, iclass 38, count 0 2006.252.07:37:11.47#ibcon#about to write, iclass 38, count 0 2006.252.07:37:11.48#ibcon#wrote, iclass 38, count 0 2006.252.07:37:11.48#ibcon#about to read 3, iclass 38, count 0 2006.252.07:37:11.51#ibcon#read 3, iclass 38, count 0 2006.252.07:37:11.51#ibcon#about to read 4, iclass 38, count 0 2006.252.07:37:11.51#ibcon#read 4, iclass 38, count 0 2006.252.07:37:11.51#ibcon#about to read 5, iclass 38, count 0 2006.252.07:37:11.51#ibcon#read 5, iclass 38, count 0 2006.252.07:37:11.51#ibcon#about to read 6, iclass 38, count 0 2006.252.07:37:11.51#ibcon#read 6, iclass 38, count 0 2006.252.07:37:11.51#ibcon#end of sib2, iclass 38, count 0 2006.252.07:37:11.51#ibcon#*after write, iclass 38, count 0 2006.252.07:37:11.51#ibcon#*before return 0, iclass 38, count 0 2006.252.07:37:11.51#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.252.07:37:11.51#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.252.07:37:11.52#ibcon#about to clear, iclass 38 cls_cnt 0 2006.252.07:37:11.52#ibcon#cleared, iclass 38 cls_cnt 0 2006.252.07:37:11.52$vc4f8/vb=4,4 2006.252.07:37:11.52#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.252.07:37:11.52#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.252.07:37:11.52#ibcon#ireg 11 cls_cnt 2 2006.252.07:37:11.52#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.252.07:37:11.56#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.252.07:37:11.56#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.252.07:37:11.56#ibcon#enter wrdev, iclass 40, count 2 2006.252.07:37:11.56#ibcon#first serial, iclass 40, count 2 2006.252.07:37:11.56#ibcon#enter sib2, iclass 40, count 2 2006.252.07:37:11.56#ibcon#flushed, iclass 40, count 2 2006.252.07:37:11.56#ibcon#about to write, iclass 40, count 2 2006.252.07:37:11.56#ibcon#wrote, iclass 40, count 2 2006.252.07:37:11.56#ibcon#about to read 3, iclass 40, count 2 2006.252.07:37:11.58#ibcon#read 3, iclass 40, count 2 2006.252.07:37:11.58#ibcon#about to read 4, iclass 40, count 2 2006.252.07:37:11.58#ibcon#read 4, iclass 40, count 2 2006.252.07:37:11.58#ibcon#about to read 5, iclass 40, count 2 2006.252.07:37:11.58#ibcon#read 5, iclass 40, count 2 2006.252.07:37:11.58#ibcon#about to read 6, iclass 40, count 2 2006.252.07:37:11.58#ibcon#read 6, iclass 40, count 2 2006.252.07:37:11.58#ibcon#end of sib2, iclass 40, count 2 2006.252.07:37:11.58#ibcon#*mode == 0, iclass 40, count 2 2006.252.07:37:11.58#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.252.07:37:11.59#ibcon#[27=AT04-04\r\n] 2006.252.07:37:11.59#ibcon#*before write, iclass 40, count 2 2006.252.07:37:11.59#ibcon#enter sib2, iclass 40, count 2 2006.252.07:37:11.59#ibcon#flushed, iclass 40, count 2 2006.252.07:37:11.59#ibcon#about to write, iclass 40, count 2 2006.252.07:37:11.59#ibcon#wrote, iclass 40, count 2 2006.252.07:37:11.59#ibcon#about to read 3, iclass 40, count 2 2006.252.07:37:11.61#ibcon#read 3, iclass 40, count 2 2006.252.07:37:11.61#ibcon#about to read 4, iclass 40, count 2 2006.252.07:37:11.61#ibcon#read 4, iclass 40, count 2 2006.252.07:37:11.61#ibcon#about to read 5, iclass 40, count 2 2006.252.07:37:11.61#ibcon#read 5, iclass 40, count 2 2006.252.07:37:11.61#ibcon#about to read 6, iclass 40, count 2 2006.252.07:37:11.61#ibcon#read 6, iclass 40, count 2 2006.252.07:37:11.61#ibcon#end of sib2, iclass 40, count 2 2006.252.07:37:11.61#ibcon#*after write, iclass 40, count 2 2006.252.07:37:11.61#ibcon#*before return 0, iclass 40, count 2 2006.252.07:37:11.61#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.252.07:37:11.61#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.252.07:37:11.62#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.252.07:37:11.62#ibcon#ireg 7 cls_cnt 0 2006.252.07:37:11.62#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.252.07:37:11.72#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.252.07:37:11.72#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.252.07:37:11.72#ibcon#enter wrdev, iclass 40, count 0 2006.252.07:37:11.72#ibcon#first serial, iclass 40, count 0 2006.252.07:37:11.72#ibcon#enter sib2, iclass 40, count 0 2006.252.07:37:11.72#ibcon#flushed, iclass 40, count 0 2006.252.07:37:11.72#ibcon#about to write, iclass 40, count 0 2006.252.07:37:11.72#ibcon#wrote, iclass 40, count 0 2006.252.07:37:11.72#ibcon#about to read 3, iclass 40, count 0 2006.252.07:37:11.74#ibcon#read 3, iclass 40, count 0 2006.252.07:37:11.74#ibcon#about to read 4, iclass 40, count 0 2006.252.07:37:11.74#ibcon#read 4, iclass 40, count 0 2006.252.07:37:11.74#ibcon#about to read 5, iclass 40, count 0 2006.252.07:37:11.74#ibcon#read 5, iclass 40, count 0 2006.252.07:37:11.74#ibcon#about to read 6, iclass 40, count 0 2006.252.07:37:11.74#ibcon#read 6, iclass 40, count 0 2006.252.07:37:11.74#ibcon#end of sib2, iclass 40, count 0 2006.252.07:37:11.74#ibcon#*mode == 0, iclass 40, count 0 2006.252.07:37:11.74#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.252.07:37:11.74#ibcon#[27=USB\r\n] 2006.252.07:37:11.74#ibcon#*before write, iclass 40, count 0 2006.252.07:37:11.74#ibcon#enter sib2, iclass 40, count 0 2006.252.07:37:11.74#ibcon#flushed, iclass 40, count 0 2006.252.07:37:11.74#ibcon#about to write, iclass 40, count 0 2006.252.07:37:11.75#ibcon#wrote, iclass 40, count 0 2006.252.07:37:11.75#ibcon#about to read 3, iclass 40, count 0 2006.252.07:37:11.77#ibcon#read 3, iclass 40, count 0 2006.252.07:37:11.77#ibcon#about to read 4, iclass 40, count 0 2006.252.07:37:11.77#ibcon#read 4, iclass 40, count 0 2006.252.07:37:11.77#ibcon#about to read 5, iclass 40, count 0 2006.252.07:37:11.77#ibcon#read 5, iclass 40, count 0 2006.252.07:37:11.77#ibcon#about to read 6, iclass 40, count 0 2006.252.07:37:11.77#ibcon#read 6, iclass 40, count 0 2006.252.07:37:11.77#ibcon#end of sib2, iclass 40, count 0 2006.252.07:37:11.77#ibcon#*after write, iclass 40, count 0 2006.252.07:37:11.77#ibcon#*before return 0, iclass 40, count 0 2006.252.07:37:11.77#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.252.07:37:11.77#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.252.07:37:11.77#ibcon#about to clear, iclass 40 cls_cnt 0 2006.252.07:37:11.78#ibcon#cleared, iclass 40 cls_cnt 0 2006.252.07:37:11.78$vc4f8/vblo=5,744.99 2006.252.07:37:11.78#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.252.07:37:11.78#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.252.07:37:11.78#ibcon#ireg 17 cls_cnt 0 2006.252.07:37:11.78#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.252.07:37:11.78#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.252.07:37:11.78#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.252.07:37:11.78#ibcon#enter wrdev, iclass 4, count 0 2006.252.07:37:11.78#ibcon#first serial, iclass 4, count 0 2006.252.07:37:11.78#ibcon#enter sib2, iclass 4, count 0 2006.252.07:37:11.78#ibcon#flushed, iclass 4, count 0 2006.252.07:37:11.78#ibcon#about to write, iclass 4, count 0 2006.252.07:37:11.78#ibcon#wrote, iclass 4, count 0 2006.252.07:37:11.78#ibcon#about to read 3, iclass 4, count 0 2006.252.07:37:11.79#ibcon#read 3, iclass 4, count 0 2006.252.07:37:11.79#ibcon#about to read 4, iclass 4, count 0 2006.252.07:37:11.79#ibcon#read 4, iclass 4, count 0 2006.252.07:37:11.79#ibcon#about to read 5, iclass 4, count 0 2006.252.07:37:11.79#ibcon#read 5, iclass 4, count 0 2006.252.07:37:11.79#ibcon#about to read 6, iclass 4, count 0 2006.252.07:37:11.79#ibcon#read 6, iclass 4, count 0 2006.252.07:37:11.79#ibcon#end of sib2, iclass 4, count 0 2006.252.07:37:11.79#ibcon#*mode == 0, iclass 4, count 0 2006.252.07:37:11.79#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.252.07:37:11.79#ibcon#[28=FRQ=05,744.99\r\n] 2006.252.07:37:11.79#ibcon#*before write, iclass 4, count 0 2006.252.07:37:11.79#ibcon#enter sib2, iclass 4, count 0 2006.252.07:37:11.79#ibcon#flushed, iclass 4, count 0 2006.252.07:37:11.79#ibcon#about to write, iclass 4, count 0 2006.252.07:37:11.80#ibcon#wrote, iclass 4, count 0 2006.252.07:37:11.80#ibcon#about to read 3, iclass 4, count 0 2006.252.07:37:11.84#ibcon#read 3, iclass 4, count 0 2006.252.07:37:11.84#ibcon#about to read 4, iclass 4, count 0 2006.252.07:37:11.84#ibcon#read 4, iclass 4, count 0 2006.252.07:37:11.84#ibcon#about to read 5, iclass 4, count 0 2006.252.07:37:11.84#ibcon#read 5, iclass 4, count 0 2006.252.07:37:11.84#ibcon#about to read 6, iclass 4, count 0 2006.252.07:37:11.84#ibcon#read 6, iclass 4, count 0 2006.252.07:37:11.84#ibcon#end of sib2, iclass 4, count 0 2006.252.07:37:11.84#ibcon#*after write, iclass 4, count 0 2006.252.07:37:11.84#ibcon#*before return 0, iclass 4, count 0 2006.252.07:37:11.84#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.252.07:37:11.84#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.252.07:37:11.84#ibcon#about to clear, iclass 4 cls_cnt 0 2006.252.07:37:11.84#ibcon#cleared, iclass 4 cls_cnt 0 2006.252.07:37:11.84$vc4f8/vb=5,4 2006.252.07:37:11.84#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.252.07:37:11.84#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.252.07:37:11.84#ibcon#ireg 11 cls_cnt 2 2006.252.07:37:11.84#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.252.07:37:11.88#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.252.07:37:11.88#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.252.07:37:11.88#ibcon#enter wrdev, iclass 6, count 2 2006.252.07:37:11.88#ibcon#first serial, iclass 6, count 2 2006.252.07:37:11.88#ibcon#enter sib2, iclass 6, count 2 2006.252.07:37:11.88#ibcon#flushed, iclass 6, count 2 2006.252.07:37:11.88#ibcon#about to write, iclass 6, count 2 2006.252.07:37:11.88#ibcon#wrote, iclass 6, count 2 2006.252.07:37:11.88#ibcon#about to read 3, iclass 6, count 2 2006.252.07:37:11.90#ibcon#read 3, iclass 6, count 2 2006.252.07:37:11.90#ibcon#about to read 4, iclass 6, count 2 2006.252.07:37:11.90#ibcon#read 4, iclass 6, count 2 2006.252.07:37:11.90#ibcon#about to read 5, iclass 6, count 2 2006.252.07:37:11.90#ibcon#read 5, iclass 6, count 2 2006.252.07:37:11.90#ibcon#about to read 6, iclass 6, count 2 2006.252.07:37:11.90#ibcon#read 6, iclass 6, count 2 2006.252.07:37:11.90#ibcon#end of sib2, iclass 6, count 2 2006.252.07:37:11.90#ibcon#*mode == 0, iclass 6, count 2 2006.252.07:37:11.90#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.252.07:37:11.90#ibcon#[27=AT05-04\r\n] 2006.252.07:37:11.90#ibcon#*before write, iclass 6, count 2 2006.252.07:37:11.90#ibcon#enter sib2, iclass 6, count 2 2006.252.07:37:11.90#ibcon#flushed, iclass 6, count 2 2006.252.07:37:11.91#ibcon#about to write, iclass 6, count 2 2006.252.07:37:11.91#ibcon#wrote, iclass 6, count 2 2006.252.07:37:11.91#ibcon#about to read 3, iclass 6, count 2 2006.252.07:37:11.93#ibcon#read 3, iclass 6, count 2 2006.252.07:37:11.93#ibcon#about to read 4, iclass 6, count 2 2006.252.07:37:11.93#ibcon#read 4, iclass 6, count 2 2006.252.07:37:11.93#ibcon#about to read 5, iclass 6, count 2 2006.252.07:37:11.93#ibcon#read 5, iclass 6, count 2 2006.252.07:37:11.93#ibcon#about to read 6, iclass 6, count 2 2006.252.07:37:11.93#ibcon#read 6, iclass 6, count 2 2006.252.07:37:11.93#ibcon#end of sib2, iclass 6, count 2 2006.252.07:37:11.93#ibcon#*after write, iclass 6, count 2 2006.252.07:37:11.93#ibcon#*before return 0, iclass 6, count 2 2006.252.07:37:11.93#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.252.07:37:11.93#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.252.07:37:11.93#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.252.07:37:11.94#ibcon#ireg 7 cls_cnt 0 2006.252.07:37:11.94#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.252.07:37:12.04#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.252.07:37:12.04#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.252.07:37:12.04#ibcon#enter wrdev, iclass 6, count 0 2006.252.07:37:12.04#ibcon#first serial, iclass 6, count 0 2006.252.07:37:12.04#ibcon#enter sib2, iclass 6, count 0 2006.252.07:37:12.04#ibcon#flushed, iclass 6, count 0 2006.252.07:37:12.04#ibcon#about to write, iclass 6, count 0 2006.252.07:37:12.04#ibcon#wrote, iclass 6, count 0 2006.252.07:37:12.04#ibcon#about to read 3, iclass 6, count 0 2006.252.07:37:12.06#ibcon#read 3, iclass 6, count 0 2006.252.07:37:12.06#ibcon#about to read 4, iclass 6, count 0 2006.252.07:37:12.06#ibcon#read 4, iclass 6, count 0 2006.252.07:37:12.06#ibcon#about to read 5, iclass 6, count 0 2006.252.07:37:12.06#ibcon#read 5, iclass 6, count 0 2006.252.07:37:12.06#ibcon#about to read 6, iclass 6, count 0 2006.252.07:37:12.06#ibcon#read 6, iclass 6, count 0 2006.252.07:37:12.06#ibcon#end of sib2, iclass 6, count 0 2006.252.07:37:12.06#ibcon#*mode == 0, iclass 6, count 0 2006.252.07:37:12.06#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.252.07:37:12.06#ibcon#[27=USB\r\n] 2006.252.07:37:12.06#ibcon#*before write, iclass 6, count 0 2006.252.07:37:12.06#ibcon#enter sib2, iclass 6, count 0 2006.252.07:37:12.06#ibcon#flushed, iclass 6, count 0 2006.252.07:37:12.06#ibcon#about to write, iclass 6, count 0 2006.252.07:37:12.07#ibcon#wrote, iclass 6, count 0 2006.252.07:37:12.07#ibcon#about to read 3, iclass 6, count 0 2006.252.07:37:12.09#ibcon#read 3, iclass 6, count 0 2006.252.07:37:12.09#ibcon#about to read 4, iclass 6, count 0 2006.252.07:37:12.09#ibcon#read 4, iclass 6, count 0 2006.252.07:37:12.09#ibcon#about to read 5, iclass 6, count 0 2006.252.07:37:12.09#ibcon#read 5, iclass 6, count 0 2006.252.07:37:12.09#ibcon#about to read 6, iclass 6, count 0 2006.252.07:37:12.09#ibcon#read 6, iclass 6, count 0 2006.252.07:37:12.09#ibcon#end of sib2, iclass 6, count 0 2006.252.07:37:12.09#ibcon#*after write, iclass 6, count 0 2006.252.07:37:12.09#ibcon#*before return 0, iclass 6, count 0 2006.252.07:37:12.09#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.252.07:37:12.09#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.252.07:37:12.09#ibcon#about to clear, iclass 6 cls_cnt 0 2006.252.07:37:12.10#ibcon#cleared, iclass 6 cls_cnt 0 2006.252.07:37:12.10$vc4f8/vblo=6,752.99 2006.252.07:37:12.10#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.252.07:37:12.10#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.252.07:37:12.10#ibcon#ireg 17 cls_cnt 0 2006.252.07:37:12.10#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.252.07:37:12.10#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.252.07:37:12.10#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.252.07:37:12.10#ibcon#enter wrdev, iclass 10, count 0 2006.252.07:37:12.10#ibcon#first serial, iclass 10, count 0 2006.252.07:37:12.10#ibcon#enter sib2, iclass 10, count 0 2006.252.07:37:12.10#ibcon#flushed, iclass 10, count 0 2006.252.07:37:12.10#ibcon#about to write, iclass 10, count 0 2006.252.07:37:12.10#ibcon#wrote, iclass 10, count 0 2006.252.07:37:12.10#ibcon#about to read 3, iclass 10, count 0 2006.252.07:37:12.11#ibcon#read 3, iclass 10, count 0 2006.252.07:37:12.11#ibcon#about to read 4, iclass 10, count 0 2006.252.07:37:12.11#ibcon#read 4, iclass 10, count 0 2006.252.07:37:12.11#ibcon#about to read 5, iclass 10, count 0 2006.252.07:37:12.11#ibcon#read 5, iclass 10, count 0 2006.252.07:37:12.11#ibcon#about to read 6, iclass 10, count 0 2006.252.07:37:12.11#ibcon#read 6, iclass 10, count 0 2006.252.07:37:12.11#ibcon#end of sib2, iclass 10, count 0 2006.252.07:37:12.11#ibcon#*mode == 0, iclass 10, count 0 2006.252.07:37:12.11#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.252.07:37:12.11#ibcon#[28=FRQ=06,752.99\r\n] 2006.252.07:37:12.11#ibcon#*before write, iclass 10, count 0 2006.252.07:37:12.11#ibcon#enter sib2, iclass 10, count 0 2006.252.07:37:12.11#ibcon#flushed, iclass 10, count 0 2006.252.07:37:12.12#ibcon#about to write, iclass 10, count 0 2006.252.07:37:12.12#ibcon#wrote, iclass 10, count 0 2006.252.07:37:12.12#ibcon#about to read 3, iclass 10, count 0 2006.252.07:37:12.15#ibcon#read 3, iclass 10, count 0 2006.252.07:37:12.15#ibcon#about to read 4, iclass 10, count 0 2006.252.07:37:12.15#ibcon#read 4, iclass 10, count 0 2006.252.07:37:12.15#ibcon#about to read 5, iclass 10, count 0 2006.252.07:37:12.15#ibcon#read 5, iclass 10, count 0 2006.252.07:37:12.15#ibcon#about to read 6, iclass 10, count 0 2006.252.07:37:12.15#ibcon#read 6, iclass 10, count 0 2006.252.07:37:12.15#ibcon#end of sib2, iclass 10, count 0 2006.252.07:37:12.15#ibcon#*after write, iclass 10, count 0 2006.252.07:37:12.15#ibcon#*before return 0, iclass 10, count 0 2006.252.07:37:12.15#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.252.07:37:12.15#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.252.07:37:12.15#ibcon#about to clear, iclass 10 cls_cnt 0 2006.252.07:37:12.15#ibcon#cleared, iclass 10 cls_cnt 0 2006.252.07:37:12.16$vc4f8/vb=6,4 2006.252.07:37:12.16#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.252.07:37:12.16#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.252.07:37:12.16#ibcon#ireg 11 cls_cnt 2 2006.252.07:37:12.16#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.252.07:37:12.20#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.252.07:37:12.20#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.252.07:37:12.20#ibcon#enter wrdev, iclass 12, count 2 2006.252.07:37:12.20#ibcon#first serial, iclass 12, count 2 2006.252.07:37:12.20#ibcon#enter sib2, iclass 12, count 2 2006.252.07:37:12.20#ibcon#flushed, iclass 12, count 2 2006.252.07:37:12.20#ibcon#about to write, iclass 12, count 2 2006.252.07:37:12.20#ibcon#wrote, iclass 12, count 2 2006.252.07:37:12.20#ibcon#about to read 3, iclass 12, count 2 2006.252.07:37:12.22#ibcon#read 3, iclass 12, count 2 2006.252.07:37:12.22#ibcon#about to read 4, iclass 12, count 2 2006.252.07:37:12.22#ibcon#read 4, iclass 12, count 2 2006.252.07:37:12.22#ibcon#about to read 5, iclass 12, count 2 2006.252.07:37:12.22#ibcon#read 5, iclass 12, count 2 2006.252.07:37:12.22#ibcon#about to read 6, iclass 12, count 2 2006.252.07:37:12.22#ibcon#read 6, iclass 12, count 2 2006.252.07:37:12.22#ibcon#end of sib2, iclass 12, count 2 2006.252.07:37:12.22#ibcon#*mode == 0, iclass 12, count 2 2006.252.07:37:12.22#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.252.07:37:12.22#ibcon#[27=AT06-04\r\n] 2006.252.07:37:12.22#ibcon#*before write, iclass 12, count 2 2006.252.07:37:12.23#ibcon#enter sib2, iclass 12, count 2 2006.252.07:37:12.23#ibcon#flushed, iclass 12, count 2 2006.252.07:37:12.23#ibcon#about to write, iclass 12, count 2 2006.252.07:37:12.23#ibcon#wrote, iclass 12, count 2 2006.252.07:37:12.23#ibcon#about to read 3, iclass 12, count 2 2006.252.07:37:12.25#ibcon#read 3, iclass 12, count 2 2006.252.07:37:12.25#ibcon#about to read 4, iclass 12, count 2 2006.252.07:37:12.25#ibcon#read 4, iclass 12, count 2 2006.252.07:37:12.25#ibcon#about to read 5, iclass 12, count 2 2006.252.07:37:12.25#ibcon#read 5, iclass 12, count 2 2006.252.07:37:12.25#ibcon#about to read 6, iclass 12, count 2 2006.252.07:37:12.25#ibcon#read 6, iclass 12, count 2 2006.252.07:37:12.25#ibcon#end of sib2, iclass 12, count 2 2006.252.07:37:12.25#ibcon#*after write, iclass 12, count 2 2006.252.07:37:12.25#ibcon#*before return 0, iclass 12, count 2 2006.252.07:37:12.25#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.252.07:37:12.25#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.252.07:37:12.25#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.252.07:37:12.25#ibcon#ireg 7 cls_cnt 0 2006.252.07:37:12.26#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.252.07:37:12.36#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.252.07:37:12.36#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.252.07:37:12.36#ibcon#enter wrdev, iclass 12, count 0 2006.252.07:37:12.36#ibcon#first serial, iclass 12, count 0 2006.252.07:37:12.36#ibcon#enter sib2, iclass 12, count 0 2006.252.07:37:12.36#ibcon#flushed, iclass 12, count 0 2006.252.07:37:12.36#ibcon#about to write, iclass 12, count 0 2006.252.07:37:12.36#ibcon#wrote, iclass 12, count 0 2006.252.07:37:12.36#ibcon#about to read 3, iclass 12, count 0 2006.252.07:37:12.38#ibcon#read 3, iclass 12, count 0 2006.252.07:37:12.38#ibcon#about to read 4, iclass 12, count 0 2006.252.07:37:12.38#ibcon#read 4, iclass 12, count 0 2006.252.07:37:12.38#ibcon#about to read 5, iclass 12, count 0 2006.252.07:37:12.38#ibcon#read 5, iclass 12, count 0 2006.252.07:37:12.38#ibcon#about to read 6, iclass 12, count 0 2006.252.07:37:12.38#ibcon#read 6, iclass 12, count 0 2006.252.07:37:12.38#ibcon#end of sib2, iclass 12, count 0 2006.252.07:37:12.38#ibcon#*mode == 0, iclass 12, count 0 2006.252.07:37:12.38#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.252.07:37:12.38#ibcon#[27=USB\r\n] 2006.252.07:37:12.38#ibcon#*before write, iclass 12, count 0 2006.252.07:37:12.38#ibcon#enter sib2, iclass 12, count 0 2006.252.07:37:12.38#ibcon#flushed, iclass 12, count 0 2006.252.07:37:12.38#ibcon#about to write, iclass 12, count 0 2006.252.07:37:12.39#ibcon#wrote, iclass 12, count 0 2006.252.07:37:12.39#ibcon#about to read 3, iclass 12, count 0 2006.252.07:37:12.41#ibcon#read 3, iclass 12, count 0 2006.252.07:37:12.41#ibcon#about to read 4, iclass 12, count 0 2006.252.07:37:12.41#ibcon#read 4, iclass 12, count 0 2006.252.07:37:12.41#ibcon#about to read 5, iclass 12, count 0 2006.252.07:37:12.41#ibcon#read 5, iclass 12, count 0 2006.252.07:37:12.41#ibcon#about to read 6, iclass 12, count 0 2006.252.07:37:12.41#ibcon#read 6, iclass 12, count 0 2006.252.07:37:12.41#ibcon#end of sib2, iclass 12, count 0 2006.252.07:37:12.41#ibcon#*after write, iclass 12, count 0 2006.252.07:37:12.41#ibcon#*before return 0, iclass 12, count 0 2006.252.07:37:12.41#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.252.07:37:12.42#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.252.07:37:12.42#ibcon#about to clear, iclass 12 cls_cnt 0 2006.252.07:37:12.42#ibcon#cleared, iclass 12 cls_cnt 0 2006.252.07:37:12.42$vc4f8/vabw=wide 2006.252.07:37:12.42#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.252.07:37:12.42#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.252.07:37:12.42#ibcon#ireg 8 cls_cnt 0 2006.252.07:37:12.42#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.252.07:37:12.42#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.252.07:37:12.42#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.252.07:37:12.42#ibcon#enter wrdev, iclass 14, count 0 2006.252.07:37:12.42#ibcon#first serial, iclass 14, count 0 2006.252.07:37:12.42#ibcon#enter sib2, iclass 14, count 0 2006.252.07:37:12.42#ibcon#flushed, iclass 14, count 0 2006.252.07:37:12.42#ibcon#about to write, iclass 14, count 0 2006.252.07:37:12.42#ibcon#wrote, iclass 14, count 0 2006.252.07:37:12.42#ibcon#about to read 3, iclass 14, count 0 2006.252.07:37:12.43#ibcon#read 3, iclass 14, count 0 2006.252.07:37:12.43#ibcon#about to read 4, iclass 14, count 0 2006.252.07:37:12.43#ibcon#read 4, iclass 14, count 0 2006.252.07:37:12.43#ibcon#about to read 5, iclass 14, count 0 2006.252.07:37:12.43#ibcon#read 5, iclass 14, count 0 2006.252.07:37:12.43#ibcon#about to read 6, iclass 14, count 0 2006.252.07:37:12.43#ibcon#read 6, iclass 14, count 0 2006.252.07:37:12.43#ibcon#end of sib2, iclass 14, count 0 2006.252.07:37:12.43#ibcon#*mode == 0, iclass 14, count 0 2006.252.07:37:12.43#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.252.07:37:12.43#ibcon#[25=BW32\r\n] 2006.252.07:37:12.43#ibcon#*before write, iclass 14, count 0 2006.252.07:37:12.43#ibcon#enter sib2, iclass 14, count 0 2006.252.07:37:12.43#ibcon#flushed, iclass 14, count 0 2006.252.07:37:12.44#ibcon#about to write, iclass 14, count 0 2006.252.07:37:12.44#ibcon#wrote, iclass 14, count 0 2006.252.07:37:12.44#ibcon#about to read 3, iclass 14, count 0 2006.252.07:37:12.46#ibcon#read 3, iclass 14, count 0 2006.252.07:37:12.46#ibcon#about to read 4, iclass 14, count 0 2006.252.07:37:12.46#ibcon#read 4, iclass 14, count 0 2006.252.07:37:12.46#ibcon#about to read 5, iclass 14, count 0 2006.252.07:37:12.46#ibcon#read 5, iclass 14, count 0 2006.252.07:37:12.46#ibcon#about to read 6, iclass 14, count 0 2006.252.07:37:12.46#ibcon#read 6, iclass 14, count 0 2006.252.07:37:12.46#ibcon#end of sib2, iclass 14, count 0 2006.252.07:37:12.46#ibcon#*after write, iclass 14, count 0 2006.252.07:37:12.46#ibcon#*before return 0, iclass 14, count 0 2006.252.07:37:12.46#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.252.07:37:12.47#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.252.07:37:12.47#ibcon#about to clear, iclass 14 cls_cnt 0 2006.252.07:37:12.47#ibcon#cleared, iclass 14 cls_cnt 0 2006.252.07:37:12.47$vc4f8/vbbw=wide 2006.252.07:37:12.47#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.252.07:37:12.47#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.252.07:37:12.47#ibcon#ireg 8 cls_cnt 0 2006.252.07:37:12.47#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.252.07:37:12.53#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.252.07:37:12.53#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.252.07:37:12.53#ibcon#enter wrdev, iclass 16, count 0 2006.252.07:37:12.53#ibcon#first serial, iclass 16, count 0 2006.252.07:37:12.53#ibcon#enter sib2, iclass 16, count 0 2006.252.07:37:12.53#ibcon#flushed, iclass 16, count 0 2006.252.07:37:12.53#ibcon#about to write, iclass 16, count 0 2006.252.07:37:12.53#ibcon#wrote, iclass 16, count 0 2006.252.07:37:12.53#ibcon#about to read 3, iclass 16, count 0 2006.252.07:37:12.55#ibcon#read 3, iclass 16, count 0 2006.252.07:37:12.55#ibcon#about to read 4, iclass 16, count 0 2006.252.07:37:12.55#ibcon#read 4, iclass 16, count 0 2006.252.07:37:12.55#ibcon#about to read 5, iclass 16, count 0 2006.252.07:37:12.55#ibcon#read 5, iclass 16, count 0 2006.252.07:37:12.55#ibcon#about to read 6, iclass 16, count 0 2006.252.07:37:12.55#ibcon#read 6, iclass 16, count 0 2006.252.07:37:12.55#ibcon#end of sib2, iclass 16, count 0 2006.252.07:37:12.55#ibcon#*mode == 0, iclass 16, count 0 2006.252.07:37:12.55#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.252.07:37:12.55#ibcon#[27=BW32\r\n] 2006.252.07:37:12.55#ibcon#*before write, iclass 16, count 0 2006.252.07:37:12.55#ibcon#enter sib2, iclass 16, count 0 2006.252.07:37:12.55#ibcon#flushed, iclass 16, count 0 2006.252.07:37:12.55#ibcon#about to write, iclass 16, count 0 2006.252.07:37:12.56#ibcon#wrote, iclass 16, count 0 2006.252.07:37:12.56#ibcon#about to read 3, iclass 16, count 0 2006.252.07:37:12.58#ibcon#read 3, iclass 16, count 0 2006.252.07:37:12.58#ibcon#about to read 4, iclass 16, count 0 2006.252.07:37:12.58#ibcon#read 4, iclass 16, count 0 2006.252.07:37:12.58#ibcon#about to read 5, iclass 16, count 0 2006.252.07:37:12.58#ibcon#read 5, iclass 16, count 0 2006.252.07:37:12.58#ibcon#about to read 6, iclass 16, count 0 2006.252.07:37:12.58#ibcon#read 6, iclass 16, count 0 2006.252.07:37:12.58#ibcon#end of sib2, iclass 16, count 0 2006.252.07:37:12.58#ibcon#*after write, iclass 16, count 0 2006.252.07:37:12.58#ibcon#*before return 0, iclass 16, count 0 2006.252.07:37:12.58#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.252.07:37:12.58#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.252.07:37:12.58#ibcon#about to clear, iclass 16 cls_cnt 0 2006.252.07:37:12.58#ibcon#cleared, iclass 16 cls_cnt 0 2006.252.07:37:12.59$4f8m12a/ifd4f 2006.252.07:37:12.59$ifd4f/lo= 2006.252.07:37:12.59$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.252.07:37:12.59$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.252.07:37:12.59$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.252.07:37:12.59$ifd4f/patch= 2006.252.07:37:12.59$ifd4f/patch=lo1,a1,a2,a3,a4 2006.252.07:37:12.59$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.252.07:37:12.59$ifd4f/patch=lo3,a5,a6,a7,a8 2006.252.07:37:12.59$4f8m12a/"form=m,16.000,1:2 2006.252.07:37:12.59$4f8m12a/"tpicd 2006.252.07:37:12.59$4f8m12a/echo=off 2006.252.07:37:12.59$4f8m12a/xlog=off 2006.252.07:37:12.59:!2006.252.07:37:40 2006.252.07:37:26.13#trakl#Source acquired 2006.252.07:37:28.14#flagr#flagr/antenna,acquired 2006.252.07:37:40.02:preob 2006.252.07:37:41.14/onsource/TRACKING 2006.252.07:37:41.14:!2006.252.07:37:50 2006.252.07:37:50.02:data_valid=on 2006.252.07:37:50.02:midob 2006.252.07:37:51.15/onsource/TRACKING 2006.252.07:37:51.15/wx/27.46,1011.3,90 2006.252.07:37:51.35/cable/+6.4093E-03 2006.252.07:37:52.44/va/01,08,usb,yes,37,39 2006.252.07:37:52.44/va/02,07,usb,yes,37,39 2006.252.07:37:52.44/va/03,06,usb,yes,40,40 2006.252.07:37:52.44/va/04,07,usb,yes,38,41 2006.252.07:37:52.44/va/05,07,usb,yes,42,44 2006.252.07:37:52.44/va/06,07,usb,yes,37,37 2006.252.07:37:52.44/va/07,07,usb,yes,36,36 2006.252.07:37:52.44/va/08,07,usb,yes,39,38 2006.252.07:37:52.67/valo/01,532.99,yes,locked 2006.252.07:37:52.67/valo/02,572.99,yes,locked 2006.252.07:37:52.67/valo/03,672.99,yes,locked 2006.252.07:37:52.67/valo/04,832.99,yes,locked 2006.252.07:37:52.67/valo/05,652.99,yes,locked 2006.252.07:37:52.67/valo/06,772.99,yes,locked 2006.252.07:37:52.67/valo/07,832.99,yes,locked 2006.252.07:37:52.67/valo/08,852.99,yes,locked 2006.252.07:37:53.76/vb/01,04,usb,yes,33,32 2006.252.07:37:53.76/vb/02,05,usb,yes,31,32 2006.252.07:37:53.76/vb/03,04,usb,yes,31,36 2006.252.07:37:53.76/vb/04,04,usb,yes,33,33 2006.252.07:37:53.76/vb/05,04,usb,yes,31,35 2006.252.07:37:53.76/vb/06,04,usb,yes,32,35 2006.252.07:37:53.76/vb/07,04,usb,yes,34,34 2006.252.07:37:53.76/vb/08,04,usb,yes,31,35 2006.252.07:37:54.00/vblo/01,632.99,yes,locked 2006.252.07:37:54.00/vblo/02,640.99,yes,locked 2006.252.07:37:54.00/vblo/03,656.99,yes,locked 2006.252.07:37:54.00/vblo/04,712.99,yes,locked 2006.252.07:37:54.00/vblo/05,744.99,yes,locked 2006.252.07:37:54.00/vblo/06,752.99,yes,locked 2006.252.07:37:54.00/vblo/07,734.99,yes,locked 2006.252.07:37:54.00/vblo/08,744.99,yes,locked 2006.252.07:37:54.15/vabw/8 2006.252.07:37:54.30/vbbw/8 2006.252.07:37:54.39/xfe/off,on,14.0 2006.252.07:37:54.77/ifatt/23,28,28,28 2006.252.07:37:55.07/fmout-gps/S +4.73E-07 2006.252.07:37:55.12:!2006.252.07:38:50 2006.252.07:38:50.02:data_valid=off 2006.252.07:38:50.02:postob 2006.252.07:38:50.15/cable/+6.4089E-03 2006.252.07:38:50.16/wx/27.45,1011.3,90 2006.252.07:38:51.07/fmout-gps/S +4.74E-07 2006.252.07:38:51.08:scan_name=252-0739,k06252,60 2006.252.07:38:51.08:source=1300+580,130252.47,574837.6,2000.0,ccw 2006.252.07:38:52.15#flagr#flagr/antenna,new-source 2006.252.07:38:52.15:checkk5 2006.252.07:38:52.52/chk_autoobs//k5ts1/ autoobs is running! 2006.252.07:38:52.90/chk_autoobs//k5ts2/ autoobs is running! 2006.252.07:38:53.31/chk_autoobs//k5ts3/ autoobs is running! 2006.252.07:38:53.69/chk_autoobs//k5ts4/ autoobs is running! 2006.252.07:38:54.06/chk_obsdata//k5ts1/T2520737??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.07:38:54.43/chk_obsdata//k5ts2/T2520737??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.07:38:54.80/chk_obsdata//k5ts3/T2520737??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.07:38:55.17/chk_obsdata//k5ts4/T2520737??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.07:38:55.85/k5log//k5ts1_log_newline 2006.252.07:38:56.55/k5log//k5ts2_log_newline 2006.252.07:38:57.24/k5log//k5ts3_log_newline 2006.252.07:38:57.93/k5log//k5ts4_log_newline 2006.252.07:38:57.95/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.252.07:38:57.95:4f8m12a=1 2006.252.07:38:57.95$4f8m12a/echo=on 2006.252.07:38:57.95$4f8m12a/pcalon 2006.252.07:38:57.95$pcalon/"no phase cal control is implemented here 2006.252.07:38:57.95$4f8m12a/"tpicd=stop 2006.252.07:38:57.95$4f8m12a/vc4f8 2006.252.07:38:57.95$vc4f8/valo=1,532.99 2006.252.07:38:57.96#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.252.07:38:57.96#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.252.07:38:57.96#ibcon#ireg 17 cls_cnt 0 2006.252.07:38:57.96#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.252.07:38:57.96#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.252.07:38:57.96#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.252.07:38:57.96#ibcon#enter wrdev, iclass 23, count 0 2006.252.07:38:57.96#ibcon#first serial, iclass 23, count 0 2006.252.07:38:57.96#ibcon#enter sib2, iclass 23, count 0 2006.252.07:38:57.96#ibcon#flushed, iclass 23, count 0 2006.252.07:38:57.96#ibcon#about to write, iclass 23, count 0 2006.252.07:38:57.96#ibcon#wrote, iclass 23, count 0 2006.252.07:38:57.96#ibcon#about to read 3, iclass 23, count 0 2006.252.07:38:58.00#ibcon#read 3, iclass 23, count 0 2006.252.07:38:58.00#ibcon#about to read 4, iclass 23, count 0 2006.252.07:38:58.00#ibcon#read 4, iclass 23, count 0 2006.252.07:38:58.00#ibcon#about to read 5, iclass 23, count 0 2006.252.07:38:58.00#ibcon#read 5, iclass 23, count 0 2006.252.07:38:58.00#ibcon#about to read 6, iclass 23, count 0 2006.252.07:38:58.00#ibcon#read 6, iclass 23, count 0 2006.252.07:38:58.00#ibcon#end of sib2, iclass 23, count 0 2006.252.07:38:58.00#ibcon#*mode == 0, iclass 23, count 0 2006.252.07:38:58.00#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.252.07:38:58.00#ibcon#[26=FRQ=01,532.99\r\n] 2006.252.07:38:58.00#ibcon#*before write, iclass 23, count 0 2006.252.07:38:58.00#ibcon#enter sib2, iclass 23, count 0 2006.252.07:38:58.00#ibcon#flushed, iclass 23, count 0 2006.252.07:38:58.00#ibcon#about to write, iclass 23, count 0 2006.252.07:38:58.00#ibcon#wrote, iclass 23, count 0 2006.252.07:38:58.00#ibcon#about to read 3, iclass 23, count 0 2006.252.07:38:58.04#ibcon#read 3, iclass 23, count 0 2006.252.07:38:58.04#ibcon#about to read 4, iclass 23, count 0 2006.252.07:38:58.04#ibcon#read 4, iclass 23, count 0 2006.252.07:38:58.04#ibcon#about to read 5, iclass 23, count 0 2006.252.07:38:58.04#ibcon#read 5, iclass 23, count 0 2006.252.07:38:58.04#ibcon#about to read 6, iclass 23, count 0 2006.252.07:38:58.04#ibcon#read 6, iclass 23, count 0 2006.252.07:38:58.04#ibcon#end of sib2, iclass 23, count 0 2006.252.07:38:58.04#ibcon#*after write, iclass 23, count 0 2006.252.07:38:58.04#ibcon#*before return 0, iclass 23, count 0 2006.252.07:38:58.04#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.252.07:38:58.04#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.252.07:38:58.04#ibcon#about to clear, iclass 23 cls_cnt 0 2006.252.07:38:58.04#ibcon#cleared, iclass 23 cls_cnt 0 2006.252.07:38:58.04$vc4f8/va=1,8 2006.252.07:38:58.04#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.252.07:38:58.04#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.252.07:38:58.04#ibcon#ireg 11 cls_cnt 2 2006.252.07:38:58.04#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.252.07:38:58.04#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.252.07:38:58.04#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.252.07:38:58.04#ibcon#enter wrdev, iclass 25, count 2 2006.252.07:38:58.04#ibcon#first serial, iclass 25, count 2 2006.252.07:38:58.05#ibcon#enter sib2, iclass 25, count 2 2006.252.07:38:58.05#ibcon#flushed, iclass 25, count 2 2006.252.07:38:58.05#ibcon#about to write, iclass 25, count 2 2006.252.07:38:58.05#ibcon#wrote, iclass 25, count 2 2006.252.07:38:58.05#ibcon#about to read 3, iclass 25, count 2 2006.252.07:38:58.06#ibcon#read 3, iclass 25, count 2 2006.252.07:38:58.06#ibcon#about to read 4, iclass 25, count 2 2006.252.07:38:58.06#ibcon#read 4, iclass 25, count 2 2006.252.07:38:58.06#ibcon#about to read 5, iclass 25, count 2 2006.252.07:38:58.06#ibcon#read 5, iclass 25, count 2 2006.252.07:38:58.06#ibcon#about to read 6, iclass 25, count 2 2006.252.07:38:58.06#ibcon#read 6, iclass 25, count 2 2006.252.07:38:58.06#ibcon#end of sib2, iclass 25, count 2 2006.252.07:38:58.06#ibcon#*mode == 0, iclass 25, count 2 2006.252.07:38:58.06#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.252.07:38:58.06#ibcon#[25=AT01-08\r\n] 2006.252.07:38:58.06#ibcon#*before write, iclass 25, count 2 2006.252.07:38:58.06#ibcon#enter sib2, iclass 25, count 2 2006.252.07:38:58.06#ibcon#flushed, iclass 25, count 2 2006.252.07:38:58.06#ibcon#about to write, iclass 25, count 2 2006.252.07:38:58.06#ibcon#wrote, iclass 25, count 2 2006.252.07:38:58.06#ibcon#about to read 3, iclass 25, count 2 2006.252.07:38:58.09#ibcon#read 3, iclass 25, count 2 2006.252.07:38:58.09#ibcon#about to read 4, iclass 25, count 2 2006.252.07:38:58.09#ibcon#read 4, iclass 25, count 2 2006.252.07:38:58.09#ibcon#about to read 5, iclass 25, count 2 2006.252.07:38:58.09#ibcon#read 5, iclass 25, count 2 2006.252.07:38:58.09#ibcon#about to read 6, iclass 25, count 2 2006.252.07:38:58.09#ibcon#read 6, iclass 25, count 2 2006.252.07:38:58.09#ibcon#end of sib2, iclass 25, count 2 2006.252.07:38:58.09#ibcon#*after write, iclass 25, count 2 2006.252.07:38:58.09#ibcon#*before return 0, iclass 25, count 2 2006.252.07:38:58.09#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.252.07:38:58.09#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.252.07:38:58.09#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.252.07:38:58.09#ibcon#ireg 7 cls_cnt 0 2006.252.07:38:58.09#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.252.07:38:58.21#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.252.07:38:58.21#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.252.07:38:58.21#ibcon#enter wrdev, iclass 25, count 0 2006.252.07:38:58.21#ibcon#first serial, iclass 25, count 0 2006.252.07:38:58.21#ibcon#enter sib2, iclass 25, count 0 2006.252.07:38:58.21#ibcon#flushed, iclass 25, count 0 2006.252.07:38:58.21#ibcon#about to write, iclass 25, count 0 2006.252.07:38:58.21#ibcon#wrote, iclass 25, count 0 2006.252.07:38:58.21#ibcon#about to read 3, iclass 25, count 0 2006.252.07:38:58.23#ibcon#read 3, iclass 25, count 0 2006.252.07:38:58.23#ibcon#about to read 4, iclass 25, count 0 2006.252.07:38:58.23#ibcon#read 4, iclass 25, count 0 2006.252.07:38:58.23#ibcon#about to read 5, iclass 25, count 0 2006.252.07:38:58.23#ibcon#read 5, iclass 25, count 0 2006.252.07:38:58.23#ibcon#about to read 6, iclass 25, count 0 2006.252.07:38:58.23#ibcon#read 6, iclass 25, count 0 2006.252.07:38:58.23#ibcon#end of sib2, iclass 25, count 0 2006.252.07:38:58.23#ibcon#*mode == 0, iclass 25, count 0 2006.252.07:38:58.23#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.252.07:38:58.23#ibcon#[25=USB\r\n] 2006.252.07:38:58.23#ibcon#*before write, iclass 25, count 0 2006.252.07:38:58.23#ibcon#enter sib2, iclass 25, count 0 2006.252.07:38:58.23#ibcon#flushed, iclass 25, count 0 2006.252.07:38:58.23#ibcon#about to write, iclass 25, count 0 2006.252.07:38:58.23#ibcon#wrote, iclass 25, count 0 2006.252.07:38:58.23#ibcon#about to read 3, iclass 25, count 0 2006.252.07:38:58.26#ibcon#read 3, iclass 25, count 0 2006.252.07:38:58.26#ibcon#about to read 4, iclass 25, count 0 2006.252.07:38:58.26#ibcon#read 4, iclass 25, count 0 2006.252.07:38:58.26#ibcon#about to read 5, iclass 25, count 0 2006.252.07:38:58.26#ibcon#read 5, iclass 25, count 0 2006.252.07:38:58.26#ibcon#about to read 6, iclass 25, count 0 2006.252.07:38:58.26#ibcon#read 6, iclass 25, count 0 2006.252.07:38:58.26#ibcon#end of sib2, iclass 25, count 0 2006.252.07:38:58.26#ibcon#*after write, iclass 25, count 0 2006.252.07:38:58.26#ibcon#*before return 0, iclass 25, count 0 2006.252.07:38:58.26#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.252.07:38:58.26#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.252.07:38:58.26#ibcon#about to clear, iclass 25 cls_cnt 0 2006.252.07:38:58.26#ibcon#cleared, iclass 25 cls_cnt 0 2006.252.07:38:58.26$vc4f8/valo=2,572.99 2006.252.07:38:58.26#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.252.07:38:58.26#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.252.07:38:58.26#ibcon#ireg 17 cls_cnt 0 2006.252.07:38:58.26#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.252.07:38:58.26#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.252.07:38:58.26#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.252.07:38:58.26#ibcon#enter wrdev, iclass 27, count 0 2006.252.07:38:58.26#ibcon#first serial, iclass 27, count 0 2006.252.07:38:58.27#ibcon#enter sib2, iclass 27, count 0 2006.252.07:38:58.27#ibcon#flushed, iclass 27, count 0 2006.252.07:38:58.27#ibcon#about to write, iclass 27, count 0 2006.252.07:38:58.27#ibcon#wrote, iclass 27, count 0 2006.252.07:38:58.27#ibcon#about to read 3, iclass 27, count 0 2006.252.07:38:58.28#ibcon#read 3, iclass 27, count 0 2006.252.07:38:58.28#ibcon#about to read 4, iclass 27, count 0 2006.252.07:38:58.28#ibcon#read 4, iclass 27, count 0 2006.252.07:38:58.28#ibcon#about to read 5, iclass 27, count 0 2006.252.07:38:58.28#ibcon#read 5, iclass 27, count 0 2006.252.07:38:58.28#ibcon#about to read 6, iclass 27, count 0 2006.252.07:38:58.28#ibcon#read 6, iclass 27, count 0 2006.252.07:38:58.28#ibcon#end of sib2, iclass 27, count 0 2006.252.07:38:58.28#ibcon#*mode == 0, iclass 27, count 0 2006.252.07:38:58.28#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.252.07:38:58.28#ibcon#[26=FRQ=02,572.99\r\n] 2006.252.07:38:58.28#ibcon#*before write, iclass 27, count 0 2006.252.07:38:58.28#ibcon#enter sib2, iclass 27, count 0 2006.252.07:38:58.28#ibcon#flushed, iclass 27, count 0 2006.252.07:38:58.28#ibcon#about to write, iclass 27, count 0 2006.252.07:38:58.28#ibcon#wrote, iclass 27, count 0 2006.252.07:38:58.28#ibcon#about to read 3, iclass 27, count 0 2006.252.07:38:58.32#ibcon#read 3, iclass 27, count 0 2006.252.07:38:58.32#ibcon#about to read 4, iclass 27, count 0 2006.252.07:38:58.32#ibcon#read 4, iclass 27, count 0 2006.252.07:38:58.32#ibcon#about to read 5, iclass 27, count 0 2006.252.07:38:58.32#ibcon#read 5, iclass 27, count 0 2006.252.07:38:58.32#ibcon#about to read 6, iclass 27, count 0 2006.252.07:38:58.32#ibcon#read 6, iclass 27, count 0 2006.252.07:38:58.32#ibcon#end of sib2, iclass 27, count 0 2006.252.07:38:58.32#ibcon#*after write, iclass 27, count 0 2006.252.07:38:58.32#ibcon#*before return 0, iclass 27, count 0 2006.252.07:38:58.32#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.252.07:38:58.32#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.252.07:38:58.32#ibcon#about to clear, iclass 27 cls_cnt 0 2006.252.07:38:58.32#ibcon#cleared, iclass 27 cls_cnt 0 2006.252.07:38:58.32$vc4f8/va=2,7 2006.252.07:38:58.32#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.252.07:38:58.32#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.252.07:38:58.32#ibcon#ireg 11 cls_cnt 2 2006.252.07:38:58.32#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.252.07:38:58.39#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.252.07:38:58.39#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.252.07:38:58.39#ibcon#enter wrdev, iclass 29, count 2 2006.252.07:38:58.39#ibcon#first serial, iclass 29, count 2 2006.252.07:38:58.39#ibcon#enter sib2, iclass 29, count 2 2006.252.07:38:58.39#ibcon#flushed, iclass 29, count 2 2006.252.07:38:58.39#ibcon#about to write, iclass 29, count 2 2006.252.07:38:58.39#ibcon#wrote, iclass 29, count 2 2006.252.07:38:58.39#ibcon#about to read 3, iclass 29, count 2 2006.252.07:38:58.40#ibcon#read 3, iclass 29, count 2 2006.252.07:38:58.40#ibcon#about to read 4, iclass 29, count 2 2006.252.07:38:58.40#ibcon#read 4, iclass 29, count 2 2006.252.07:38:58.40#ibcon#about to read 5, iclass 29, count 2 2006.252.07:38:58.40#ibcon#read 5, iclass 29, count 2 2006.252.07:38:58.40#ibcon#about to read 6, iclass 29, count 2 2006.252.07:38:58.40#ibcon#read 6, iclass 29, count 2 2006.252.07:38:58.40#ibcon#end of sib2, iclass 29, count 2 2006.252.07:38:58.40#ibcon#*mode == 0, iclass 29, count 2 2006.252.07:38:58.40#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.252.07:38:58.40#ibcon#[25=AT02-07\r\n] 2006.252.07:38:58.40#ibcon#*before write, iclass 29, count 2 2006.252.07:38:58.40#ibcon#enter sib2, iclass 29, count 2 2006.252.07:38:58.40#ibcon#flushed, iclass 29, count 2 2006.252.07:38:58.40#ibcon#about to write, iclass 29, count 2 2006.252.07:38:58.40#ibcon#wrote, iclass 29, count 2 2006.252.07:38:58.40#ibcon#about to read 3, iclass 29, count 2 2006.252.07:38:58.43#ibcon#read 3, iclass 29, count 2 2006.252.07:38:58.43#ibcon#about to read 4, iclass 29, count 2 2006.252.07:38:58.43#ibcon#read 4, iclass 29, count 2 2006.252.07:38:58.43#ibcon#about to read 5, iclass 29, count 2 2006.252.07:38:58.43#ibcon#read 5, iclass 29, count 2 2006.252.07:38:58.43#ibcon#about to read 6, iclass 29, count 2 2006.252.07:38:58.43#ibcon#read 6, iclass 29, count 2 2006.252.07:38:58.43#ibcon#end of sib2, iclass 29, count 2 2006.252.07:38:58.43#ibcon#*after write, iclass 29, count 2 2006.252.07:38:58.43#ibcon#*before return 0, iclass 29, count 2 2006.252.07:38:58.43#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.252.07:38:58.43#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.252.07:38:58.43#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.252.07:38:58.43#ibcon#ireg 7 cls_cnt 0 2006.252.07:38:58.43#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.252.07:38:58.55#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.252.07:38:58.55#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.252.07:38:58.55#ibcon#enter wrdev, iclass 29, count 0 2006.252.07:38:58.55#ibcon#first serial, iclass 29, count 0 2006.252.07:38:58.55#ibcon#enter sib2, iclass 29, count 0 2006.252.07:38:58.55#ibcon#flushed, iclass 29, count 0 2006.252.07:38:58.55#ibcon#about to write, iclass 29, count 0 2006.252.07:38:58.55#ibcon#wrote, iclass 29, count 0 2006.252.07:38:58.55#ibcon#about to read 3, iclass 29, count 0 2006.252.07:38:58.57#ibcon#read 3, iclass 29, count 0 2006.252.07:38:58.57#ibcon#about to read 4, iclass 29, count 0 2006.252.07:38:58.57#ibcon#read 4, iclass 29, count 0 2006.252.07:38:58.57#ibcon#about to read 5, iclass 29, count 0 2006.252.07:38:58.57#ibcon#read 5, iclass 29, count 0 2006.252.07:38:58.57#ibcon#about to read 6, iclass 29, count 0 2006.252.07:38:58.57#ibcon#read 6, iclass 29, count 0 2006.252.07:38:58.57#ibcon#end of sib2, iclass 29, count 0 2006.252.07:38:58.57#ibcon#*mode == 0, iclass 29, count 0 2006.252.07:38:58.57#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.252.07:38:58.57#ibcon#[25=USB\r\n] 2006.252.07:38:58.57#ibcon#*before write, iclass 29, count 0 2006.252.07:38:58.57#ibcon#enter sib2, iclass 29, count 0 2006.252.07:38:58.57#ibcon#flushed, iclass 29, count 0 2006.252.07:38:58.57#ibcon#about to write, iclass 29, count 0 2006.252.07:38:58.57#ibcon#wrote, iclass 29, count 0 2006.252.07:38:58.57#ibcon#about to read 3, iclass 29, count 0 2006.252.07:38:58.60#ibcon#read 3, iclass 29, count 0 2006.252.07:38:58.60#ibcon#about to read 4, iclass 29, count 0 2006.252.07:38:58.60#ibcon#read 4, iclass 29, count 0 2006.252.07:38:58.60#ibcon#about to read 5, iclass 29, count 0 2006.252.07:38:58.60#ibcon#read 5, iclass 29, count 0 2006.252.07:38:58.60#ibcon#about to read 6, iclass 29, count 0 2006.252.07:38:58.60#ibcon#read 6, iclass 29, count 0 2006.252.07:38:58.60#ibcon#end of sib2, iclass 29, count 0 2006.252.07:38:58.60#ibcon#*after write, iclass 29, count 0 2006.252.07:38:58.60#ibcon#*before return 0, iclass 29, count 0 2006.252.07:38:58.60#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.252.07:38:58.60#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.252.07:38:58.60#ibcon#about to clear, iclass 29 cls_cnt 0 2006.252.07:38:58.60#ibcon#cleared, iclass 29 cls_cnt 0 2006.252.07:38:58.60$vc4f8/valo=3,672.99 2006.252.07:38:58.60#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.252.07:38:58.60#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.252.07:38:58.60#ibcon#ireg 17 cls_cnt 0 2006.252.07:38:58.60#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.252.07:38:58.60#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.252.07:38:58.60#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.252.07:38:58.60#ibcon#enter wrdev, iclass 31, count 0 2006.252.07:38:58.60#ibcon#first serial, iclass 31, count 0 2006.252.07:38:58.61#ibcon#enter sib2, iclass 31, count 0 2006.252.07:38:58.61#ibcon#flushed, iclass 31, count 0 2006.252.07:38:58.61#ibcon#about to write, iclass 31, count 0 2006.252.07:38:58.61#ibcon#wrote, iclass 31, count 0 2006.252.07:38:58.61#ibcon#about to read 3, iclass 31, count 0 2006.252.07:38:58.62#ibcon#read 3, iclass 31, count 0 2006.252.07:38:58.62#ibcon#about to read 4, iclass 31, count 0 2006.252.07:38:58.62#ibcon#read 4, iclass 31, count 0 2006.252.07:38:58.62#ibcon#about to read 5, iclass 31, count 0 2006.252.07:38:58.62#ibcon#read 5, iclass 31, count 0 2006.252.07:38:58.62#ibcon#about to read 6, iclass 31, count 0 2006.252.07:38:58.62#ibcon#read 6, iclass 31, count 0 2006.252.07:38:58.62#ibcon#end of sib2, iclass 31, count 0 2006.252.07:38:58.62#ibcon#*mode == 0, iclass 31, count 0 2006.252.07:38:58.62#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.252.07:38:58.62#ibcon#[26=FRQ=03,672.99\r\n] 2006.252.07:38:58.62#ibcon#*before write, iclass 31, count 0 2006.252.07:38:58.62#ibcon#enter sib2, iclass 31, count 0 2006.252.07:38:58.62#ibcon#flushed, iclass 31, count 0 2006.252.07:38:58.62#ibcon#about to write, iclass 31, count 0 2006.252.07:38:58.62#ibcon#wrote, iclass 31, count 0 2006.252.07:38:58.62#ibcon#about to read 3, iclass 31, count 0 2006.252.07:38:58.66#ibcon#read 3, iclass 31, count 0 2006.252.07:38:58.66#ibcon#about to read 4, iclass 31, count 0 2006.252.07:38:58.66#ibcon#read 4, iclass 31, count 0 2006.252.07:38:58.66#ibcon#about to read 5, iclass 31, count 0 2006.252.07:38:58.66#ibcon#read 5, iclass 31, count 0 2006.252.07:38:58.66#ibcon#about to read 6, iclass 31, count 0 2006.252.07:38:58.66#ibcon#read 6, iclass 31, count 0 2006.252.07:38:58.66#ibcon#end of sib2, iclass 31, count 0 2006.252.07:38:58.66#ibcon#*after write, iclass 31, count 0 2006.252.07:38:58.66#ibcon#*before return 0, iclass 31, count 0 2006.252.07:38:58.66#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.252.07:38:58.66#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.252.07:38:58.66#ibcon#about to clear, iclass 31 cls_cnt 0 2006.252.07:38:58.66#ibcon#cleared, iclass 31 cls_cnt 0 2006.252.07:38:58.66$vc4f8/va=3,6 2006.252.07:38:58.66#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.252.07:38:58.66#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.252.07:38:58.66#ibcon#ireg 11 cls_cnt 2 2006.252.07:38:58.66#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.252.07:38:58.73#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.252.07:38:58.73#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.252.07:38:58.73#ibcon#enter wrdev, iclass 33, count 2 2006.252.07:38:58.73#ibcon#first serial, iclass 33, count 2 2006.252.07:38:58.73#ibcon#enter sib2, iclass 33, count 2 2006.252.07:38:58.73#ibcon#flushed, iclass 33, count 2 2006.252.07:38:58.73#ibcon#about to write, iclass 33, count 2 2006.252.07:38:58.73#ibcon#wrote, iclass 33, count 2 2006.252.07:38:58.73#ibcon#about to read 3, iclass 33, count 2 2006.252.07:38:58.74#ibcon#read 3, iclass 33, count 2 2006.252.07:38:58.74#ibcon#about to read 4, iclass 33, count 2 2006.252.07:38:58.74#ibcon#read 4, iclass 33, count 2 2006.252.07:38:58.74#ibcon#about to read 5, iclass 33, count 2 2006.252.07:38:58.74#ibcon#read 5, iclass 33, count 2 2006.252.07:38:58.74#ibcon#about to read 6, iclass 33, count 2 2006.252.07:38:58.74#ibcon#read 6, iclass 33, count 2 2006.252.07:38:58.74#ibcon#end of sib2, iclass 33, count 2 2006.252.07:38:58.74#ibcon#*mode == 0, iclass 33, count 2 2006.252.07:38:58.74#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.252.07:38:58.74#ibcon#[25=AT03-06\r\n] 2006.252.07:38:58.74#ibcon#*before write, iclass 33, count 2 2006.252.07:38:58.74#ibcon#enter sib2, iclass 33, count 2 2006.252.07:38:58.74#ibcon#flushed, iclass 33, count 2 2006.252.07:38:58.74#ibcon#about to write, iclass 33, count 2 2006.252.07:38:58.74#ibcon#wrote, iclass 33, count 2 2006.252.07:38:58.74#ibcon#about to read 3, iclass 33, count 2 2006.252.07:38:58.77#ibcon#read 3, iclass 33, count 2 2006.252.07:38:58.77#ibcon#about to read 4, iclass 33, count 2 2006.252.07:38:58.77#ibcon#read 4, iclass 33, count 2 2006.252.07:38:58.77#ibcon#about to read 5, iclass 33, count 2 2006.252.07:38:58.77#ibcon#read 5, iclass 33, count 2 2006.252.07:38:58.77#ibcon#about to read 6, iclass 33, count 2 2006.252.07:38:58.77#ibcon#read 6, iclass 33, count 2 2006.252.07:38:58.77#ibcon#end of sib2, iclass 33, count 2 2006.252.07:38:58.77#ibcon#*after write, iclass 33, count 2 2006.252.07:38:58.77#ibcon#*before return 0, iclass 33, count 2 2006.252.07:38:58.77#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.252.07:38:58.77#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.252.07:38:58.77#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.252.07:38:58.77#ibcon#ireg 7 cls_cnt 0 2006.252.07:38:58.77#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.252.07:38:58.89#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.252.07:38:58.89#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.252.07:38:58.89#ibcon#enter wrdev, iclass 33, count 0 2006.252.07:38:58.89#ibcon#first serial, iclass 33, count 0 2006.252.07:38:58.89#ibcon#enter sib2, iclass 33, count 0 2006.252.07:38:58.89#ibcon#flushed, iclass 33, count 0 2006.252.07:38:58.89#ibcon#about to write, iclass 33, count 0 2006.252.07:38:58.89#ibcon#wrote, iclass 33, count 0 2006.252.07:38:58.89#ibcon#about to read 3, iclass 33, count 0 2006.252.07:38:58.91#ibcon#read 3, iclass 33, count 0 2006.252.07:38:58.91#ibcon#about to read 4, iclass 33, count 0 2006.252.07:38:58.91#ibcon#read 4, iclass 33, count 0 2006.252.07:38:58.91#ibcon#about to read 5, iclass 33, count 0 2006.252.07:38:58.91#ibcon#read 5, iclass 33, count 0 2006.252.07:38:58.91#ibcon#about to read 6, iclass 33, count 0 2006.252.07:38:58.91#ibcon#read 6, iclass 33, count 0 2006.252.07:38:58.91#ibcon#end of sib2, iclass 33, count 0 2006.252.07:38:58.91#ibcon#*mode == 0, iclass 33, count 0 2006.252.07:38:58.91#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.252.07:38:58.91#ibcon#[25=USB\r\n] 2006.252.07:38:58.91#ibcon#*before write, iclass 33, count 0 2006.252.07:38:58.91#ibcon#enter sib2, iclass 33, count 0 2006.252.07:38:58.91#ibcon#flushed, iclass 33, count 0 2006.252.07:38:58.91#ibcon#about to write, iclass 33, count 0 2006.252.07:38:58.91#ibcon#wrote, iclass 33, count 0 2006.252.07:38:58.91#ibcon#about to read 3, iclass 33, count 0 2006.252.07:38:58.94#ibcon#read 3, iclass 33, count 0 2006.252.07:38:58.94#ibcon#about to read 4, iclass 33, count 0 2006.252.07:38:58.94#ibcon#read 4, iclass 33, count 0 2006.252.07:38:58.94#ibcon#about to read 5, iclass 33, count 0 2006.252.07:38:58.94#ibcon#read 5, iclass 33, count 0 2006.252.07:38:58.94#ibcon#about to read 6, iclass 33, count 0 2006.252.07:38:58.94#ibcon#read 6, iclass 33, count 0 2006.252.07:38:58.94#ibcon#end of sib2, iclass 33, count 0 2006.252.07:38:58.94#ibcon#*after write, iclass 33, count 0 2006.252.07:38:58.94#ibcon#*before return 0, iclass 33, count 0 2006.252.07:38:58.94#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.252.07:38:58.94#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.252.07:38:58.94#ibcon#about to clear, iclass 33 cls_cnt 0 2006.252.07:38:58.94#ibcon#cleared, iclass 33 cls_cnt 0 2006.252.07:38:58.94$vc4f8/valo=4,832.99 2006.252.07:38:58.94#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.252.07:38:58.94#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.252.07:38:58.94#ibcon#ireg 17 cls_cnt 0 2006.252.07:38:58.94#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.252.07:38:58.94#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.252.07:38:58.94#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.252.07:38:58.94#ibcon#enter wrdev, iclass 35, count 0 2006.252.07:38:58.94#ibcon#first serial, iclass 35, count 0 2006.252.07:38:58.95#ibcon#enter sib2, iclass 35, count 0 2006.252.07:38:58.95#ibcon#flushed, iclass 35, count 0 2006.252.07:38:58.95#ibcon#about to write, iclass 35, count 0 2006.252.07:38:58.95#ibcon#wrote, iclass 35, count 0 2006.252.07:38:58.95#ibcon#about to read 3, iclass 35, count 0 2006.252.07:38:58.96#ibcon#read 3, iclass 35, count 0 2006.252.07:38:58.96#ibcon#about to read 4, iclass 35, count 0 2006.252.07:38:58.96#ibcon#read 4, iclass 35, count 0 2006.252.07:38:58.96#ibcon#about to read 5, iclass 35, count 0 2006.252.07:38:58.96#ibcon#read 5, iclass 35, count 0 2006.252.07:38:58.96#ibcon#about to read 6, iclass 35, count 0 2006.252.07:38:58.96#ibcon#read 6, iclass 35, count 0 2006.252.07:38:58.96#ibcon#end of sib2, iclass 35, count 0 2006.252.07:38:58.96#ibcon#*mode == 0, iclass 35, count 0 2006.252.07:38:58.96#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.252.07:38:58.96#ibcon#[26=FRQ=04,832.99\r\n] 2006.252.07:38:58.96#ibcon#*before write, iclass 35, count 0 2006.252.07:38:58.96#ibcon#enter sib2, iclass 35, count 0 2006.252.07:38:58.96#ibcon#flushed, iclass 35, count 0 2006.252.07:38:58.96#ibcon#about to write, iclass 35, count 0 2006.252.07:38:58.96#ibcon#wrote, iclass 35, count 0 2006.252.07:38:58.96#ibcon#about to read 3, iclass 35, count 0 2006.252.07:38:59.00#ibcon#read 3, iclass 35, count 0 2006.252.07:38:59.00#ibcon#about to read 4, iclass 35, count 0 2006.252.07:38:59.00#ibcon#read 4, iclass 35, count 0 2006.252.07:38:59.00#ibcon#about to read 5, iclass 35, count 0 2006.252.07:38:59.00#ibcon#read 5, iclass 35, count 0 2006.252.07:38:59.00#ibcon#about to read 6, iclass 35, count 0 2006.252.07:38:59.00#ibcon#read 6, iclass 35, count 0 2006.252.07:38:59.00#ibcon#end of sib2, iclass 35, count 0 2006.252.07:38:59.00#ibcon#*after write, iclass 35, count 0 2006.252.07:38:59.00#ibcon#*before return 0, iclass 35, count 0 2006.252.07:38:59.00#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.252.07:38:59.00#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.252.07:38:59.00#ibcon#about to clear, iclass 35 cls_cnt 0 2006.252.07:38:59.00#ibcon#cleared, iclass 35 cls_cnt 0 2006.252.07:38:59.00$vc4f8/va=4,7 2006.252.07:38:59.00#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.252.07:38:59.00#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.252.07:38:59.00#ibcon#ireg 11 cls_cnt 2 2006.252.07:38:59.00#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.252.07:38:59.07#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.252.07:38:59.07#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.252.07:38:59.07#ibcon#enter wrdev, iclass 37, count 2 2006.252.07:38:59.07#ibcon#first serial, iclass 37, count 2 2006.252.07:38:59.07#ibcon#enter sib2, iclass 37, count 2 2006.252.07:38:59.07#ibcon#flushed, iclass 37, count 2 2006.252.07:38:59.07#ibcon#about to write, iclass 37, count 2 2006.252.07:38:59.07#ibcon#wrote, iclass 37, count 2 2006.252.07:38:59.07#ibcon#about to read 3, iclass 37, count 2 2006.252.07:38:59.08#ibcon#read 3, iclass 37, count 2 2006.252.07:38:59.08#ibcon#about to read 4, iclass 37, count 2 2006.252.07:38:59.08#ibcon#read 4, iclass 37, count 2 2006.252.07:38:59.08#ibcon#about to read 5, iclass 37, count 2 2006.252.07:38:59.08#ibcon#read 5, iclass 37, count 2 2006.252.07:38:59.08#ibcon#about to read 6, iclass 37, count 2 2006.252.07:38:59.08#ibcon#read 6, iclass 37, count 2 2006.252.07:38:59.08#ibcon#end of sib2, iclass 37, count 2 2006.252.07:38:59.08#ibcon#*mode == 0, iclass 37, count 2 2006.252.07:38:59.09#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.252.07:38:59.09#ibcon#[25=AT04-07\r\n] 2006.252.07:38:59.09#ibcon#*before write, iclass 37, count 2 2006.252.07:38:59.09#ibcon#enter sib2, iclass 37, count 2 2006.252.07:38:59.09#ibcon#flushed, iclass 37, count 2 2006.252.07:38:59.09#ibcon#about to write, iclass 37, count 2 2006.252.07:38:59.09#ibcon#wrote, iclass 37, count 2 2006.252.07:38:59.09#ibcon#about to read 3, iclass 37, count 2 2006.252.07:38:59.11#ibcon#read 3, iclass 37, count 2 2006.252.07:38:59.11#ibcon#about to read 4, iclass 37, count 2 2006.252.07:38:59.11#ibcon#read 4, iclass 37, count 2 2006.252.07:38:59.11#ibcon#about to read 5, iclass 37, count 2 2006.252.07:38:59.11#ibcon#read 5, iclass 37, count 2 2006.252.07:38:59.11#ibcon#about to read 6, iclass 37, count 2 2006.252.07:38:59.11#ibcon#read 6, iclass 37, count 2 2006.252.07:38:59.11#ibcon#end of sib2, iclass 37, count 2 2006.252.07:38:59.11#ibcon#*after write, iclass 37, count 2 2006.252.07:38:59.11#ibcon#*before return 0, iclass 37, count 2 2006.252.07:38:59.11#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.252.07:38:59.11#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.252.07:38:59.11#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.252.07:38:59.11#ibcon#ireg 7 cls_cnt 0 2006.252.07:38:59.11#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.252.07:38:59.23#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.252.07:38:59.23#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.252.07:38:59.23#ibcon#enter wrdev, iclass 37, count 0 2006.252.07:38:59.23#ibcon#first serial, iclass 37, count 0 2006.252.07:38:59.23#ibcon#enter sib2, iclass 37, count 0 2006.252.07:38:59.23#ibcon#flushed, iclass 37, count 0 2006.252.07:38:59.23#ibcon#about to write, iclass 37, count 0 2006.252.07:38:59.23#ibcon#wrote, iclass 37, count 0 2006.252.07:38:59.23#ibcon#about to read 3, iclass 37, count 0 2006.252.07:38:59.25#ibcon#read 3, iclass 37, count 0 2006.252.07:38:59.25#ibcon#about to read 4, iclass 37, count 0 2006.252.07:38:59.25#ibcon#read 4, iclass 37, count 0 2006.252.07:38:59.25#ibcon#about to read 5, iclass 37, count 0 2006.252.07:38:59.25#ibcon#read 5, iclass 37, count 0 2006.252.07:38:59.25#ibcon#about to read 6, iclass 37, count 0 2006.252.07:38:59.25#ibcon#read 6, iclass 37, count 0 2006.252.07:38:59.25#ibcon#end of sib2, iclass 37, count 0 2006.252.07:38:59.25#ibcon#*mode == 0, iclass 37, count 0 2006.252.07:38:59.25#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.252.07:38:59.25#ibcon#[25=USB\r\n] 2006.252.07:38:59.25#ibcon#*before write, iclass 37, count 0 2006.252.07:38:59.25#ibcon#enter sib2, iclass 37, count 0 2006.252.07:38:59.25#ibcon#flushed, iclass 37, count 0 2006.252.07:38:59.25#ibcon#about to write, iclass 37, count 0 2006.252.07:38:59.25#ibcon#wrote, iclass 37, count 0 2006.252.07:38:59.25#ibcon#about to read 3, iclass 37, count 0 2006.252.07:38:59.28#ibcon#read 3, iclass 37, count 0 2006.252.07:38:59.28#ibcon#about to read 4, iclass 37, count 0 2006.252.07:38:59.28#ibcon#read 4, iclass 37, count 0 2006.252.07:38:59.28#ibcon#about to read 5, iclass 37, count 0 2006.252.07:38:59.28#ibcon#read 5, iclass 37, count 0 2006.252.07:38:59.28#ibcon#about to read 6, iclass 37, count 0 2006.252.07:38:59.28#ibcon#read 6, iclass 37, count 0 2006.252.07:38:59.28#ibcon#end of sib2, iclass 37, count 0 2006.252.07:38:59.28#ibcon#*after write, iclass 37, count 0 2006.252.07:38:59.28#ibcon#*before return 0, iclass 37, count 0 2006.252.07:38:59.28#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.252.07:38:59.28#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.252.07:38:59.28#ibcon#about to clear, iclass 37 cls_cnt 0 2006.252.07:38:59.28#ibcon#cleared, iclass 37 cls_cnt 0 2006.252.07:38:59.28$vc4f8/valo=5,652.99 2006.252.07:38:59.28#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.252.07:38:59.28#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.252.07:38:59.28#ibcon#ireg 17 cls_cnt 0 2006.252.07:38:59.28#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.252.07:38:59.28#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.252.07:38:59.28#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.252.07:38:59.29#ibcon#enter wrdev, iclass 39, count 0 2006.252.07:38:59.29#ibcon#first serial, iclass 39, count 0 2006.252.07:38:59.29#ibcon#enter sib2, iclass 39, count 0 2006.252.07:38:59.29#ibcon#flushed, iclass 39, count 0 2006.252.07:38:59.29#ibcon#about to write, iclass 39, count 0 2006.252.07:38:59.29#ibcon#wrote, iclass 39, count 0 2006.252.07:38:59.29#ibcon#about to read 3, iclass 39, count 0 2006.252.07:38:59.30#ibcon#read 3, iclass 39, count 0 2006.252.07:38:59.30#ibcon#about to read 4, iclass 39, count 0 2006.252.07:38:59.30#ibcon#read 4, iclass 39, count 0 2006.252.07:38:59.30#ibcon#about to read 5, iclass 39, count 0 2006.252.07:38:59.30#ibcon#read 5, iclass 39, count 0 2006.252.07:38:59.30#ibcon#about to read 6, iclass 39, count 0 2006.252.07:38:59.30#ibcon#read 6, iclass 39, count 0 2006.252.07:38:59.30#ibcon#end of sib2, iclass 39, count 0 2006.252.07:38:59.30#ibcon#*mode == 0, iclass 39, count 0 2006.252.07:38:59.30#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.252.07:38:59.30#ibcon#[26=FRQ=05,652.99\r\n] 2006.252.07:38:59.30#ibcon#*before write, iclass 39, count 0 2006.252.07:38:59.30#ibcon#enter sib2, iclass 39, count 0 2006.252.07:38:59.30#ibcon#flushed, iclass 39, count 0 2006.252.07:38:59.30#ibcon#about to write, iclass 39, count 0 2006.252.07:38:59.30#ibcon#wrote, iclass 39, count 0 2006.252.07:38:59.30#ibcon#about to read 3, iclass 39, count 0 2006.252.07:38:59.34#ibcon#read 3, iclass 39, count 0 2006.252.07:38:59.34#ibcon#about to read 4, iclass 39, count 0 2006.252.07:38:59.34#ibcon#read 4, iclass 39, count 0 2006.252.07:38:59.34#ibcon#about to read 5, iclass 39, count 0 2006.252.07:38:59.34#ibcon#read 5, iclass 39, count 0 2006.252.07:38:59.34#ibcon#about to read 6, iclass 39, count 0 2006.252.07:38:59.34#ibcon#read 6, iclass 39, count 0 2006.252.07:38:59.34#ibcon#end of sib2, iclass 39, count 0 2006.252.07:38:59.34#ibcon#*after write, iclass 39, count 0 2006.252.07:38:59.34#ibcon#*before return 0, iclass 39, count 0 2006.252.07:38:59.34#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.252.07:38:59.34#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.252.07:38:59.34#ibcon#about to clear, iclass 39 cls_cnt 0 2006.252.07:38:59.34#ibcon#cleared, iclass 39 cls_cnt 0 2006.252.07:38:59.34$vc4f8/va=5,7 2006.252.07:38:59.34#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.252.07:38:59.34#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.252.07:38:59.34#ibcon#ireg 11 cls_cnt 2 2006.252.07:38:59.34#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.252.07:38:59.40#abcon#<5=/05 3.2 5.4 27.45 911011.3\r\n> 2006.252.07:38:59.40#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.252.07:38:59.40#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.252.07:38:59.40#ibcon#enter wrdev, iclass 3, count 2 2006.252.07:38:59.40#ibcon#first serial, iclass 3, count 2 2006.252.07:38:59.40#ibcon#enter sib2, iclass 3, count 2 2006.252.07:38:59.40#ibcon#flushed, iclass 3, count 2 2006.252.07:38:59.40#ibcon#about to write, iclass 3, count 2 2006.252.07:38:59.40#ibcon#wrote, iclass 3, count 2 2006.252.07:38:59.40#ibcon#about to read 3, iclass 3, count 2 2006.252.07:38:59.42#ibcon#read 3, iclass 3, count 2 2006.252.07:38:59.42#ibcon#about to read 4, iclass 3, count 2 2006.252.07:38:59.42#ibcon#read 4, iclass 3, count 2 2006.252.07:38:59.42#ibcon#about to read 5, iclass 3, count 2 2006.252.07:38:59.42#ibcon#read 5, iclass 3, count 2 2006.252.07:38:59.42#ibcon#about to read 6, iclass 3, count 2 2006.252.07:38:59.42#ibcon#read 6, iclass 3, count 2 2006.252.07:38:59.42#ibcon#end of sib2, iclass 3, count 2 2006.252.07:38:59.42#ibcon#*mode == 0, iclass 3, count 2 2006.252.07:38:59.42#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.252.07:38:59.42#ibcon#[25=AT05-07\r\n] 2006.252.07:38:59.42#ibcon#*before write, iclass 3, count 2 2006.252.07:38:59.42#ibcon#enter sib2, iclass 3, count 2 2006.252.07:38:59.42#ibcon#flushed, iclass 3, count 2 2006.252.07:38:59.42#ibcon#about to write, iclass 3, count 2 2006.252.07:38:59.42#ibcon#wrote, iclass 3, count 2 2006.252.07:38:59.42#ibcon#about to read 3, iclass 3, count 2 2006.252.07:38:59.42#abcon#{5=INTERFACE CLEAR} 2006.252.07:38:59.45#ibcon#read 3, iclass 3, count 2 2006.252.07:38:59.45#ibcon#about to read 4, iclass 3, count 2 2006.252.07:38:59.45#ibcon#read 4, iclass 3, count 2 2006.252.07:38:59.45#ibcon#about to read 5, iclass 3, count 2 2006.252.07:38:59.45#ibcon#read 5, iclass 3, count 2 2006.252.07:38:59.45#ibcon#about to read 6, iclass 3, count 2 2006.252.07:38:59.45#ibcon#read 6, iclass 3, count 2 2006.252.07:38:59.45#ibcon#end of sib2, iclass 3, count 2 2006.252.07:38:59.45#ibcon#*after write, iclass 3, count 2 2006.252.07:38:59.45#ibcon#*before return 0, iclass 3, count 2 2006.252.07:38:59.45#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.252.07:38:59.45#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.252.07:38:59.45#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.252.07:38:59.45#ibcon#ireg 7 cls_cnt 0 2006.252.07:38:59.45#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.252.07:38:59.48#abcon#[5=S1D000X0/0*\r\n] 2006.252.07:38:59.57#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.252.07:38:59.57#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.252.07:38:59.57#ibcon#enter wrdev, iclass 3, count 0 2006.252.07:38:59.57#ibcon#first serial, iclass 3, count 0 2006.252.07:38:59.57#ibcon#enter sib2, iclass 3, count 0 2006.252.07:38:59.57#ibcon#flushed, iclass 3, count 0 2006.252.07:38:59.57#ibcon#about to write, iclass 3, count 0 2006.252.07:38:59.57#ibcon#wrote, iclass 3, count 0 2006.252.07:38:59.57#ibcon#about to read 3, iclass 3, count 0 2006.252.07:38:59.59#ibcon#read 3, iclass 3, count 0 2006.252.07:38:59.59#ibcon#about to read 4, iclass 3, count 0 2006.252.07:38:59.59#ibcon#read 4, iclass 3, count 0 2006.252.07:38:59.59#ibcon#about to read 5, iclass 3, count 0 2006.252.07:38:59.59#ibcon#read 5, iclass 3, count 0 2006.252.07:38:59.59#ibcon#about to read 6, iclass 3, count 0 2006.252.07:38:59.59#ibcon#read 6, iclass 3, count 0 2006.252.07:38:59.59#ibcon#end of sib2, iclass 3, count 0 2006.252.07:38:59.59#ibcon#*mode == 0, iclass 3, count 0 2006.252.07:38:59.59#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.252.07:38:59.59#ibcon#[25=USB\r\n] 2006.252.07:38:59.59#ibcon#*before write, iclass 3, count 0 2006.252.07:38:59.59#ibcon#enter sib2, iclass 3, count 0 2006.252.07:38:59.59#ibcon#flushed, iclass 3, count 0 2006.252.07:38:59.59#ibcon#about to write, iclass 3, count 0 2006.252.07:38:59.59#ibcon#wrote, iclass 3, count 0 2006.252.07:38:59.59#ibcon#about to read 3, iclass 3, count 0 2006.252.07:38:59.62#ibcon#read 3, iclass 3, count 0 2006.252.07:38:59.62#ibcon#about to read 4, iclass 3, count 0 2006.252.07:38:59.62#ibcon#read 4, iclass 3, count 0 2006.252.07:38:59.62#ibcon#about to read 5, iclass 3, count 0 2006.252.07:38:59.62#ibcon#read 5, iclass 3, count 0 2006.252.07:38:59.62#ibcon#about to read 6, iclass 3, count 0 2006.252.07:38:59.62#ibcon#read 6, iclass 3, count 0 2006.252.07:38:59.62#ibcon#end of sib2, iclass 3, count 0 2006.252.07:38:59.62#ibcon#*after write, iclass 3, count 0 2006.252.07:38:59.62#ibcon#*before return 0, iclass 3, count 0 2006.252.07:38:59.62#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.252.07:38:59.62#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.252.07:38:59.62#ibcon#about to clear, iclass 3 cls_cnt 0 2006.252.07:38:59.62#ibcon#cleared, iclass 3 cls_cnt 0 2006.252.07:38:59.62$vc4f8/valo=6,772.99 2006.252.07:38:59.62#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.252.07:38:59.62#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.252.07:38:59.62#ibcon#ireg 17 cls_cnt 0 2006.252.07:38:59.62#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.252.07:38:59.62#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.252.07:38:59.62#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.252.07:38:59.62#ibcon#enter wrdev, iclass 11, count 0 2006.252.07:38:59.62#ibcon#first serial, iclass 11, count 0 2006.252.07:38:59.63#ibcon#enter sib2, iclass 11, count 0 2006.252.07:38:59.63#ibcon#flushed, iclass 11, count 0 2006.252.07:38:59.63#ibcon#about to write, iclass 11, count 0 2006.252.07:38:59.63#ibcon#wrote, iclass 11, count 0 2006.252.07:38:59.63#ibcon#about to read 3, iclass 11, count 0 2006.252.07:38:59.64#ibcon#read 3, iclass 11, count 0 2006.252.07:38:59.64#ibcon#about to read 4, iclass 11, count 0 2006.252.07:38:59.64#ibcon#read 4, iclass 11, count 0 2006.252.07:38:59.64#ibcon#about to read 5, iclass 11, count 0 2006.252.07:38:59.64#ibcon#read 5, iclass 11, count 0 2006.252.07:38:59.64#ibcon#about to read 6, iclass 11, count 0 2006.252.07:38:59.64#ibcon#read 6, iclass 11, count 0 2006.252.07:38:59.64#ibcon#end of sib2, iclass 11, count 0 2006.252.07:38:59.64#ibcon#*mode == 0, iclass 11, count 0 2006.252.07:38:59.64#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.252.07:38:59.64#ibcon#[26=FRQ=06,772.99\r\n] 2006.252.07:38:59.64#ibcon#*before write, iclass 11, count 0 2006.252.07:38:59.64#ibcon#enter sib2, iclass 11, count 0 2006.252.07:38:59.64#ibcon#flushed, iclass 11, count 0 2006.252.07:38:59.64#ibcon#about to write, iclass 11, count 0 2006.252.07:38:59.64#ibcon#wrote, iclass 11, count 0 2006.252.07:38:59.64#ibcon#about to read 3, iclass 11, count 0 2006.252.07:38:59.68#ibcon#read 3, iclass 11, count 0 2006.252.07:38:59.68#ibcon#about to read 4, iclass 11, count 0 2006.252.07:38:59.68#ibcon#read 4, iclass 11, count 0 2006.252.07:38:59.68#ibcon#about to read 5, iclass 11, count 0 2006.252.07:38:59.68#ibcon#read 5, iclass 11, count 0 2006.252.07:38:59.68#ibcon#about to read 6, iclass 11, count 0 2006.252.07:38:59.68#ibcon#read 6, iclass 11, count 0 2006.252.07:38:59.68#ibcon#end of sib2, iclass 11, count 0 2006.252.07:38:59.68#ibcon#*after write, iclass 11, count 0 2006.252.07:38:59.68#ibcon#*before return 0, iclass 11, count 0 2006.252.07:38:59.68#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.252.07:38:59.68#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.252.07:38:59.68#ibcon#about to clear, iclass 11 cls_cnt 0 2006.252.07:38:59.68#ibcon#cleared, iclass 11 cls_cnt 0 2006.252.07:38:59.68$vc4f8/va=6,7 2006.252.07:38:59.68#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.252.07:38:59.68#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.252.07:38:59.68#ibcon#ireg 11 cls_cnt 2 2006.252.07:38:59.68#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.252.07:38:59.75#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.252.07:38:59.75#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.252.07:38:59.75#ibcon#enter wrdev, iclass 13, count 2 2006.252.07:38:59.75#ibcon#first serial, iclass 13, count 2 2006.252.07:38:59.75#ibcon#enter sib2, iclass 13, count 2 2006.252.07:38:59.75#ibcon#flushed, iclass 13, count 2 2006.252.07:38:59.75#ibcon#about to write, iclass 13, count 2 2006.252.07:38:59.75#ibcon#wrote, iclass 13, count 2 2006.252.07:38:59.75#ibcon#about to read 3, iclass 13, count 2 2006.252.07:38:59.76#ibcon#read 3, iclass 13, count 2 2006.252.07:38:59.76#ibcon#about to read 4, iclass 13, count 2 2006.252.07:38:59.76#ibcon#read 4, iclass 13, count 2 2006.252.07:38:59.76#ibcon#about to read 5, iclass 13, count 2 2006.252.07:38:59.76#ibcon#read 5, iclass 13, count 2 2006.252.07:38:59.76#ibcon#about to read 6, iclass 13, count 2 2006.252.07:38:59.76#ibcon#read 6, iclass 13, count 2 2006.252.07:38:59.76#ibcon#end of sib2, iclass 13, count 2 2006.252.07:38:59.76#ibcon#*mode == 0, iclass 13, count 2 2006.252.07:38:59.76#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.252.07:38:59.76#ibcon#[25=AT06-07\r\n] 2006.252.07:38:59.76#ibcon#*before write, iclass 13, count 2 2006.252.07:38:59.76#ibcon#enter sib2, iclass 13, count 2 2006.252.07:38:59.76#ibcon#flushed, iclass 13, count 2 2006.252.07:38:59.76#ibcon#about to write, iclass 13, count 2 2006.252.07:38:59.77#ibcon#wrote, iclass 13, count 2 2006.252.07:38:59.77#ibcon#about to read 3, iclass 13, count 2 2006.252.07:38:59.79#ibcon#read 3, iclass 13, count 2 2006.252.07:38:59.79#ibcon#about to read 4, iclass 13, count 2 2006.252.07:38:59.79#ibcon#read 4, iclass 13, count 2 2006.252.07:38:59.79#ibcon#about to read 5, iclass 13, count 2 2006.252.07:38:59.79#ibcon#read 5, iclass 13, count 2 2006.252.07:38:59.79#ibcon#about to read 6, iclass 13, count 2 2006.252.07:38:59.79#ibcon#read 6, iclass 13, count 2 2006.252.07:38:59.79#ibcon#end of sib2, iclass 13, count 2 2006.252.07:38:59.79#ibcon#*after write, iclass 13, count 2 2006.252.07:38:59.79#ibcon#*before return 0, iclass 13, count 2 2006.252.07:38:59.79#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.252.07:38:59.79#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.252.07:38:59.79#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.252.07:38:59.79#ibcon#ireg 7 cls_cnt 0 2006.252.07:38:59.79#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.252.07:38:59.91#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.252.07:38:59.91#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.252.07:38:59.91#ibcon#enter wrdev, iclass 13, count 0 2006.252.07:38:59.91#ibcon#first serial, iclass 13, count 0 2006.252.07:38:59.91#ibcon#enter sib2, iclass 13, count 0 2006.252.07:38:59.91#ibcon#flushed, iclass 13, count 0 2006.252.07:38:59.91#ibcon#about to write, iclass 13, count 0 2006.252.07:38:59.91#ibcon#wrote, iclass 13, count 0 2006.252.07:38:59.91#ibcon#about to read 3, iclass 13, count 0 2006.252.07:38:59.93#ibcon#read 3, iclass 13, count 0 2006.252.07:38:59.93#ibcon#about to read 4, iclass 13, count 0 2006.252.07:38:59.93#ibcon#read 4, iclass 13, count 0 2006.252.07:38:59.93#ibcon#about to read 5, iclass 13, count 0 2006.252.07:38:59.93#ibcon#read 5, iclass 13, count 0 2006.252.07:38:59.93#ibcon#about to read 6, iclass 13, count 0 2006.252.07:38:59.93#ibcon#read 6, iclass 13, count 0 2006.252.07:38:59.93#ibcon#end of sib2, iclass 13, count 0 2006.252.07:38:59.93#ibcon#*mode == 0, iclass 13, count 0 2006.252.07:38:59.93#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.252.07:38:59.93#ibcon#[25=USB\r\n] 2006.252.07:38:59.93#ibcon#*before write, iclass 13, count 0 2006.252.07:38:59.93#ibcon#enter sib2, iclass 13, count 0 2006.252.07:38:59.93#ibcon#flushed, iclass 13, count 0 2006.252.07:38:59.93#ibcon#about to write, iclass 13, count 0 2006.252.07:38:59.93#ibcon#wrote, iclass 13, count 0 2006.252.07:38:59.93#ibcon#about to read 3, iclass 13, count 0 2006.252.07:38:59.96#ibcon#read 3, iclass 13, count 0 2006.252.07:38:59.96#ibcon#about to read 4, iclass 13, count 0 2006.252.07:38:59.96#ibcon#read 4, iclass 13, count 0 2006.252.07:38:59.96#ibcon#about to read 5, iclass 13, count 0 2006.252.07:38:59.96#ibcon#read 5, iclass 13, count 0 2006.252.07:38:59.96#ibcon#about to read 6, iclass 13, count 0 2006.252.07:38:59.96#ibcon#read 6, iclass 13, count 0 2006.252.07:38:59.96#ibcon#end of sib2, iclass 13, count 0 2006.252.07:38:59.96#ibcon#*after write, iclass 13, count 0 2006.252.07:38:59.96#ibcon#*before return 0, iclass 13, count 0 2006.252.07:38:59.96#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.252.07:38:59.96#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.252.07:38:59.96#ibcon#about to clear, iclass 13 cls_cnt 0 2006.252.07:38:59.96#ibcon#cleared, iclass 13 cls_cnt 0 2006.252.07:38:59.96$vc4f8/valo=7,832.99 2006.252.07:38:59.96#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.252.07:38:59.96#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.252.07:38:59.96#ibcon#ireg 17 cls_cnt 0 2006.252.07:38:59.96#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.252.07:38:59.96#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.252.07:38:59.96#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.252.07:38:59.96#ibcon#enter wrdev, iclass 15, count 0 2006.252.07:38:59.96#ibcon#first serial, iclass 15, count 0 2006.252.07:38:59.97#ibcon#enter sib2, iclass 15, count 0 2006.252.07:38:59.97#ibcon#flushed, iclass 15, count 0 2006.252.07:38:59.97#ibcon#about to write, iclass 15, count 0 2006.252.07:38:59.97#ibcon#wrote, iclass 15, count 0 2006.252.07:38:59.97#ibcon#about to read 3, iclass 15, count 0 2006.252.07:38:59.98#ibcon#read 3, iclass 15, count 0 2006.252.07:38:59.98#ibcon#about to read 4, iclass 15, count 0 2006.252.07:38:59.98#ibcon#read 4, iclass 15, count 0 2006.252.07:38:59.98#ibcon#about to read 5, iclass 15, count 0 2006.252.07:38:59.98#ibcon#read 5, iclass 15, count 0 2006.252.07:38:59.98#ibcon#about to read 6, iclass 15, count 0 2006.252.07:38:59.98#ibcon#read 6, iclass 15, count 0 2006.252.07:38:59.98#ibcon#end of sib2, iclass 15, count 0 2006.252.07:38:59.98#ibcon#*mode == 0, iclass 15, count 0 2006.252.07:38:59.98#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.252.07:38:59.98#ibcon#[26=FRQ=07,832.99\r\n] 2006.252.07:38:59.98#ibcon#*before write, iclass 15, count 0 2006.252.07:38:59.98#ibcon#enter sib2, iclass 15, count 0 2006.252.07:38:59.98#ibcon#flushed, iclass 15, count 0 2006.252.07:38:59.98#ibcon#about to write, iclass 15, count 0 2006.252.07:38:59.98#ibcon#wrote, iclass 15, count 0 2006.252.07:38:59.98#ibcon#about to read 3, iclass 15, count 0 2006.252.07:39:00.02#ibcon#read 3, iclass 15, count 0 2006.252.07:39:00.02#ibcon#about to read 4, iclass 15, count 0 2006.252.07:39:00.02#ibcon#read 4, iclass 15, count 0 2006.252.07:39:00.02#ibcon#about to read 5, iclass 15, count 0 2006.252.07:39:00.02#ibcon#read 5, iclass 15, count 0 2006.252.07:39:00.02#ibcon#about to read 6, iclass 15, count 0 2006.252.07:39:00.02#ibcon#read 6, iclass 15, count 0 2006.252.07:39:00.02#ibcon#end of sib2, iclass 15, count 0 2006.252.07:39:00.02#ibcon#*after write, iclass 15, count 0 2006.252.07:39:00.02#ibcon#*before return 0, iclass 15, count 0 2006.252.07:39:00.02#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.252.07:39:00.02#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.252.07:39:00.02#ibcon#about to clear, iclass 15 cls_cnt 0 2006.252.07:39:00.02#ibcon#cleared, iclass 15 cls_cnt 0 2006.252.07:39:00.02$vc4f8/va=7,7 2006.252.07:39:00.02#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.252.07:39:00.02#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.252.07:39:00.02#ibcon#ireg 11 cls_cnt 2 2006.252.07:39:00.02#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.252.07:39:00.08#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.252.07:39:00.08#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.252.07:39:00.08#ibcon#enter wrdev, iclass 17, count 2 2006.252.07:39:00.08#ibcon#first serial, iclass 17, count 2 2006.252.07:39:00.08#ibcon#enter sib2, iclass 17, count 2 2006.252.07:39:00.08#ibcon#flushed, iclass 17, count 2 2006.252.07:39:00.08#ibcon#about to write, iclass 17, count 2 2006.252.07:39:00.08#ibcon#wrote, iclass 17, count 2 2006.252.07:39:00.08#ibcon#about to read 3, iclass 17, count 2 2006.252.07:39:00.10#ibcon#read 3, iclass 17, count 2 2006.252.07:39:00.10#ibcon#about to read 4, iclass 17, count 2 2006.252.07:39:00.10#ibcon#read 4, iclass 17, count 2 2006.252.07:39:00.10#ibcon#about to read 5, iclass 17, count 2 2006.252.07:39:00.10#ibcon#read 5, iclass 17, count 2 2006.252.07:39:00.10#ibcon#about to read 6, iclass 17, count 2 2006.252.07:39:00.10#ibcon#read 6, iclass 17, count 2 2006.252.07:39:00.10#ibcon#end of sib2, iclass 17, count 2 2006.252.07:39:00.10#ibcon#*mode == 0, iclass 17, count 2 2006.252.07:39:00.10#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.252.07:39:00.10#ibcon#[25=AT07-07\r\n] 2006.252.07:39:00.10#ibcon#*before write, iclass 17, count 2 2006.252.07:39:00.10#ibcon#enter sib2, iclass 17, count 2 2006.252.07:39:00.10#ibcon#flushed, iclass 17, count 2 2006.252.07:39:00.10#ibcon#about to write, iclass 17, count 2 2006.252.07:39:00.10#ibcon#wrote, iclass 17, count 2 2006.252.07:39:00.10#ibcon#about to read 3, iclass 17, count 2 2006.252.07:39:00.13#ibcon#read 3, iclass 17, count 2 2006.252.07:39:00.13#ibcon#about to read 4, iclass 17, count 2 2006.252.07:39:00.13#ibcon#read 4, iclass 17, count 2 2006.252.07:39:00.13#ibcon#about to read 5, iclass 17, count 2 2006.252.07:39:00.13#ibcon#read 5, iclass 17, count 2 2006.252.07:39:00.13#ibcon#about to read 6, iclass 17, count 2 2006.252.07:39:00.13#ibcon#read 6, iclass 17, count 2 2006.252.07:39:00.13#ibcon#end of sib2, iclass 17, count 2 2006.252.07:39:00.13#ibcon#*after write, iclass 17, count 2 2006.252.07:39:00.13#ibcon#*before return 0, iclass 17, count 2 2006.252.07:39:00.13#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.252.07:39:00.13#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.252.07:39:00.13#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.252.07:39:00.13#ibcon#ireg 7 cls_cnt 0 2006.252.07:39:00.13#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.252.07:39:00.25#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.252.07:39:00.25#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.252.07:39:00.25#ibcon#enter wrdev, iclass 17, count 0 2006.252.07:39:00.25#ibcon#first serial, iclass 17, count 0 2006.252.07:39:00.25#ibcon#enter sib2, iclass 17, count 0 2006.252.07:39:00.25#ibcon#flushed, iclass 17, count 0 2006.252.07:39:00.25#ibcon#about to write, iclass 17, count 0 2006.252.07:39:00.25#ibcon#wrote, iclass 17, count 0 2006.252.07:39:00.25#ibcon#about to read 3, iclass 17, count 0 2006.252.07:39:00.27#ibcon#read 3, iclass 17, count 0 2006.252.07:39:00.27#ibcon#about to read 4, iclass 17, count 0 2006.252.07:39:00.27#ibcon#read 4, iclass 17, count 0 2006.252.07:39:00.27#ibcon#about to read 5, iclass 17, count 0 2006.252.07:39:00.27#ibcon#read 5, iclass 17, count 0 2006.252.07:39:00.27#ibcon#about to read 6, iclass 17, count 0 2006.252.07:39:00.27#ibcon#read 6, iclass 17, count 0 2006.252.07:39:00.27#ibcon#end of sib2, iclass 17, count 0 2006.252.07:39:00.27#ibcon#*mode == 0, iclass 17, count 0 2006.252.07:39:00.27#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.252.07:39:00.27#ibcon#[25=USB\r\n] 2006.252.07:39:00.27#ibcon#*before write, iclass 17, count 0 2006.252.07:39:00.27#ibcon#enter sib2, iclass 17, count 0 2006.252.07:39:00.27#ibcon#flushed, iclass 17, count 0 2006.252.07:39:00.27#ibcon#about to write, iclass 17, count 0 2006.252.07:39:00.27#ibcon#wrote, iclass 17, count 0 2006.252.07:39:00.27#ibcon#about to read 3, iclass 17, count 0 2006.252.07:39:00.30#ibcon#read 3, iclass 17, count 0 2006.252.07:39:00.30#ibcon#about to read 4, iclass 17, count 0 2006.252.07:39:00.30#ibcon#read 4, iclass 17, count 0 2006.252.07:39:00.30#ibcon#about to read 5, iclass 17, count 0 2006.252.07:39:00.30#ibcon#read 5, iclass 17, count 0 2006.252.07:39:00.30#ibcon#about to read 6, iclass 17, count 0 2006.252.07:39:00.30#ibcon#read 6, iclass 17, count 0 2006.252.07:39:00.30#ibcon#end of sib2, iclass 17, count 0 2006.252.07:39:00.30#ibcon#*after write, iclass 17, count 0 2006.252.07:39:00.30#ibcon#*before return 0, iclass 17, count 0 2006.252.07:39:00.30#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.252.07:39:00.30#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.252.07:39:00.30#ibcon#about to clear, iclass 17 cls_cnt 0 2006.252.07:39:00.30#ibcon#cleared, iclass 17 cls_cnt 0 2006.252.07:39:00.30$vc4f8/valo=8,852.99 2006.252.07:39:00.30#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.252.07:39:00.30#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.252.07:39:00.30#ibcon#ireg 17 cls_cnt 0 2006.252.07:39:00.30#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.252.07:39:00.30#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.252.07:39:00.30#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.252.07:39:00.30#ibcon#enter wrdev, iclass 19, count 0 2006.252.07:39:00.30#ibcon#first serial, iclass 19, count 0 2006.252.07:39:00.31#ibcon#enter sib2, iclass 19, count 0 2006.252.07:39:00.31#ibcon#flushed, iclass 19, count 0 2006.252.07:39:00.31#ibcon#about to write, iclass 19, count 0 2006.252.07:39:00.31#ibcon#wrote, iclass 19, count 0 2006.252.07:39:00.31#ibcon#about to read 3, iclass 19, count 0 2006.252.07:39:00.32#ibcon#read 3, iclass 19, count 0 2006.252.07:39:00.32#ibcon#about to read 4, iclass 19, count 0 2006.252.07:39:00.32#ibcon#read 4, iclass 19, count 0 2006.252.07:39:00.32#ibcon#about to read 5, iclass 19, count 0 2006.252.07:39:00.32#ibcon#read 5, iclass 19, count 0 2006.252.07:39:00.32#ibcon#about to read 6, iclass 19, count 0 2006.252.07:39:00.32#ibcon#read 6, iclass 19, count 0 2006.252.07:39:00.32#ibcon#end of sib2, iclass 19, count 0 2006.252.07:39:00.32#ibcon#*mode == 0, iclass 19, count 0 2006.252.07:39:00.32#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.252.07:39:00.32#ibcon#[26=FRQ=08,852.99\r\n] 2006.252.07:39:00.32#ibcon#*before write, iclass 19, count 0 2006.252.07:39:00.32#ibcon#enter sib2, iclass 19, count 0 2006.252.07:39:00.32#ibcon#flushed, iclass 19, count 0 2006.252.07:39:00.32#ibcon#about to write, iclass 19, count 0 2006.252.07:39:00.32#ibcon#wrote, iclass 19, count 0 2006.252.07:39:00.32#ibcon#about to read 3, iclass 19, count 0 2006.252.07:39:00.36#ibcon#read 3, iclass 19, count 0 2006.252.07:39:00.36#ibcon#about to read 4, iclass 19, count 0 2006.252.07:39:00.36#ibcon#read 4, iclass 19, count 0 2006.252.07:39:00.36#ibcon#about to read 5, iclass 19, count 0 2006.252.07:39:00.36#ibcon#read 5, iclass 19, count 0 2006.252.07:39:00.36#ibcon#about to read 6, iclass 19, count 0 2006.252.07:39:00.36#ibcon#read 6, iclass 19, count 0 2006.252.07:39:00.36#ibcon#end of sib2, iclass 19, count 0 2006.252.07:39:00.36#ibcon#*after write, iclass 19, count 0 2006.252.07:39:00.36#ibcon#*before return 0, iclass 19, count 0 2006.252.07:39:00.36#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.252.07:39:00.36#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.252.07:39:00.36#ibcon#about to clear, iclass 19 cls_cnt 0 2006.252.07:39:00.36#ibcon#cleared, iclass 19 cls_cnt 0 2006.252.07:39:00.36$vc4f8/va=8,7 2006.252.07:39:00.36#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.252.07:39:00.36#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.252.07:39:00.36#ibcon#ireg 11 cls_cnt 2 2006.252.07:39:00.36#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.252.07:39:00.42#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.252.07:39:00.42#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.252.07:39:00.42#ibcon#enter wrdev, iclass 21, count 2 2006.252.07:39:00.42#ibcon#first serial, iclass 21, count 2 2006.252.07:39:00.42#ibcon#enter sib2, iclass 21, count 2 2006.252.07:39:00.42#ibcon#flushed, iclass 21, count 2 2006.252.07:39:00.42#ibcon#about to write, iclass 21, count 2 2006.252.07:39:00.42#ibcon#wrote, iclass 21, count 2 2006.252.07:39:00.42#ibcon#about to read 3, iclass 21, count 2 2006.252.07:39:00.44#ibcon#read 3, iclass 21, count 2 2006.252.07:39:00.44#ibcon#about to read 4, iclass 21, count 2 2006.252.07:39:00.44#ibcon#read 4, iclass 21, count 2 2006.252.07:39:00.44#ibcon#about to read 5, iclass 21, count 2 2006.252.07:39:00.44#ibcon#read 5, iclass 21, count 2 2006.252.07:39:00.44#ibcon#about to read 6, iclass 21, count 2 2006.252.07:39:00.44#ibcon#read 6, iclass 21, count 2 2006.252.07:39:00.44#ibcon#end of sib2, iclass 21, count 2 2006.252.07:39:00.44#ibcon#*mode == 0, iclass 21, count 2 2006.252.07:39:00.44#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.252.07:39:00.44#ibcon#[25=AT08-07\r\n] 2006.252.07:39:00.44#ibcon#*before write, iclass 21, count 2 2006.252.07:39:00.44#ibcon#enter sib2, iclass 21, count 2 2006.252.07:39:00.44#ibcon#flushed, iclass 21, count 2 2006.252.07:39:00.44#ibcon#about to write, iclass 21, count 2 2006.252.07:39:00.44#ibcon#wrote, iclass 21, count 2 2006.252.07:39:00.44#ibcon#about to read 3, iclass 21, count 2 2006.252.07:39:00.47#ibcon#read 3, iclass 21, count 2 2006.252.07:39:00.47#ibcon#about to read 4, iclass 21, count 2 2006.252.07:39:00.47#ibcon#read 4, iclass 21, count 2 2006.252.07:39:00.47#ibcon#about to read 5, iclass 21, count 2 2006.252.07:39:00.47#ibcon#read 5, iclass 21, count 2 2006.252.07:39:00.47#ibcon#about to read 6, iclass 21, count 2 2006.252.07:39:00.47#ibcon#read 6, iclass 21, count 2 2006.252.07:39:00.47#ibcon#end of sib2, iclass 21, count 2 2006.252.07:39:00.47#ibcon#*after write, iclass 21, count 2 2006.252.07:39:00.47#ibcon#*before return 0, iclass 21, count 2 2006.252.07:39:00.47#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.252.07:39:00.47#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.252.07:39:00.47#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.252.07:39:00.47#ibcon#ireg 7 cls_cnt 0 2006.252.07:39:00.47#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.252.07:39:00.59#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.252.07:39:00.59#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.252.07:39:00.59#ibcon#enter wrdev, iclass 21, count 0 2006.252.07:39:00.59#ibcon#first serial, iclass 21, count 0 2006.252.07:39:00.59#ibcon#enter sib2, iclass 21, count 0 2006.252.07:39:00.59#ibcon#flushed, iclass 21, count 0 2006.252.07:39:00.59#ibcon#about to write, iclass 21, count 0 2006.252.07:39:00.59#ibcon#wrote, iclass 21, count 0 2006.252.07:39:00.59#ibcon#about to read 3, iclass 21, count 0 2006.252.07:39:00.61#ibcon#read 3, iclass 21, count 0 2006.252.07:39:00.61#ibcon#about to read 4, iclass 21, count 0 2006.252.07:39:00.61#ibcon#read 4, iclass 21, count 0 2006.252.07:39:00.61#ibcon#about to read 5, iclass 21, count 0 2006.252.07:39:00.61#ibcon#read 5, iclass 21, count 0 2006.252.07:39:00.61#ibcon#about to read 6, iclass 21, count 0 2006.252.07:39:00.61#ibcon#read 6, iclass 21, count 0 2006.252.07:39:00.61#ibcon#end of sib2, iclass 21, count 0 2006.252.07:39:00.61#ibcon#*mode == 0, iclass 21, count 0 2006.252.07:39:00.61#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.252.07:39:00.61#ibcon#[25=USB\r\n] 2006.252.07:39:00.61#ibcon#*before write, iclass 21, count 0 2006.252.07:39:00.61#ibcon#enter sib2, iclass 21, count 0 2006.252.07:39:00.61#ibcon#flushed, iclass 21, count 0 2006.252.07:39:00.61#ibcon#about to write, iclass 21, count 0 2006.252.07:39:00.61#ibcon#wrote, iclass 21, count 0 2006.252.07:39:00.61#ibcon#about to read 3, iclass 21, count 0 2006.252.07:39:00.64#ibcon#read 3, iclass 21, count 0 2006.252.07:39:00.64#ibcon#about to read 4, iclass 21, count 0 2006.252.07:39:00.64#ibcon#read 4, iclass 21, count 0 2006.252.07:39:00.64#ibcon#about to read 5, iclass 21, count 0 2006.252.07:39:00.64#ibcon#read 5, iclass 21, count 0 2006.252.07:39:00.64#ibcon#about to read 6, iclass 21, count 0 2006.252.07:39:00.64#ibcon#read 6, iclass 21, count 0 2006.252.07:39:00.64#ibcon#end of sib2, iclass 21, count 0 2006.252.07:39:00.64#ibcon#*after write, iclass 21, count 0 2006.252.07:39:00.64#ibcon#*before return 0, iclass 21, count 0 2006.252.07:39:00.64#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.252.07:39:00.64#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.252.07:39:00.64#ibcon#about to clear, iclass 21 cls_cnt 0 2006.252.07:39:00.64#ibcon#cleared, iclass 21 cls_cnt 0 2006.252.07:39:00.64$vc4f8/vblo=1,632.99 2006.252.07:39:00.64#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.252.07:39:00.64#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.252.07:39:00.64#ibcon#ireg 17 cls_cnt 0 2006.252.07:39:00.64#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.252.07:39:00.64#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.252.07:39:00.64#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.252.07:39:00.64#ibcon#enter wrdev, iclass 23, count 0 2006.252.07:39:00.64#ibcon#first serial, iclass 23, count 0 2006.252.07:39:00.65#ibcon#enter sib2, iclass 23, count 0 2006.252.07:39:00.65#ibcon#flushed, iclass 23, count 0 2006.252.07:39:00.65#ibcon#about to write, iclass 23, count 0 2006.252.07:39:00.65#ibcon#wrote, iclass 23, count 0 2006.252.07:39:00.65#ibcon#about to read 3, iclass 23, count 0 2006.252.07:39:00.66#ibcon#read 3, iclass 23, count 0 2006.252.07:39:00.66#ibcon#about to read 4, iclass 23, count 0 2006.252.07:39:00.66#ibcon#read 4, iclass 23, count 0 2006.252.07:39:00.66#ibcon#about to read 5, iclass 23, count 0 2006.252.07:39:00.66#ibcon#read 5, iclass 23, count 0 2006.252.07:39:00.66#ibcon#about to read 6, iclass 23, count 0 2006.252.07:39:00.66#ibcon#read 6, iclass 23, count 0 2006.252.07:39:00.66#ibcon#end of sib2, iclass 23, count 0 2006.252.07:39:00.66#ibcon#*mode == 0, iclass 23, count 0 2006.252.07:39:00.66#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.252.07:39:00.66#ibcon#[28=FRQ=01,632.99\r\n] 2006.252.07:39:00.66#ibcon#*before write, iclass 23, count 0 2006.252.07:39:00.66#ibcon#enter sib2, iclass 23, count 0 2006.252.07:39:00.66#ibcon#flushed, iclass 23, count 0 2006.252.07:39:00.66#ibcon#about to write, iclass 23, count 0 2006.252.07:39:00.66#ibcon#wrote, iclass 23, count 0 2006.252.07:39:00.66#ibcon#about to read 3, iclass 23, count 0 2006.252.07:39:00.70#ibcon#read 3, iclass 23, count 0 2006.252.07:39:00.70#ibcon#about to read 4, iclass 23, count 0 2006.252.07:39:00.70#ibcon#read 4, iclass 23, count 0 2006.252.07:39:00.70#ibcon#about to read 5, iclass 23, count 0 2006.252.07:39:00.70#ibcon#read 5, iclass 23, count 0 2006.252.07:39:00.70#ibcon#about to read 6, iclass 23, count 0 2006.252.07:39:00.70#ibcon#read 6, iclass 23, count 0 2006.252.07:39:00.70#ibcon#end of sib2, iclass 23, count 0 2006.252.07:39:00.70#ibcon#*after write, iclass 23, count 0 2006.252.07:39:00.70#ibcon#*before return 0, iclass 23, count 0 2006.252.07:39:00.70#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.252.07:39:00.70#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.252.07:39:00.70#ibcon#about to clear, iclass 23 cls_cnt 0 2006.252.07:39:00.70#ibcon#cleared, iclass 23 cls_cnt 0 2006.252.07:39:00.70$vc4f8/vb=1,4 2006.252.07:39:00.70#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.252.07:39:00.70#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.252.07:39:00.70#ibcon#ireg 11 cls_cnt 2 2006.252.07:39:00.70#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.252.07:39:00.70#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.252.07:39:00.71#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.252.07:39:00.71#ibcon#enter wrdev, iclass 25, count 2 2006.252.07:39:00.71#ibcon#first serial, iclass 25, count 2 2006.252.07:39:00.71#ibcon#enter sib2, iclass 25, count 2 2006.252.07:39:00.71#ibcon#flushed, iclass 25, count 2 2006.252.07:39:00.71#ibcon#about to write, iclass 25, count 2 2006.252.07:39:00.71#ibcon#wrote, iclass 25, count 2 2006.252.07:39:00.71#ibcon#about to read 3, iclass 25, count 2 2006.252.07:39:00.72#ibcon#read 3, iclass 25, count 2 2006.252.07:39:00.72#ibcon#about to read 4, iclass 25, count 2 2006.252.07:39:00.72#ibcon#read 4, iclass 25, count 2 2006.252.07:39:00.72#ibcon#about to read 5, iclass 25, count 2 2006.252.07:39:00.72#ibcon#read 5, iclass 25, count 2 2006.252.07:39:00.72#ibcon#about to read 6, iclass 25, count 2 2006.252.07:39:00.72#ibcon#read 6, iclass 25, count 2 2006.252.07:39:00.72#ibcon#end of sib2, iclass 25, count 2 2006.252.07:39:00.72#ibcon#*mode == 0, iclass 25, count 2 2006.252.07:39:00.72#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.252.07:39:00.72#ibcon#[27=AT01-04\r\n] 2006.252.07:39:00.72#ibcon#*before write, iclass 25, count 2 2006.252.07:39:00.72#ibcon#enter sib2, iclass 25, count 2 2006.252.07:39:00.72#ibcon#flushed, iclass 25, count 2 2006.252.07:39:00.72#ibcon#about to write, iclass 25, count 2 2006.252.07:39:00.72#ibcon#wrote, iclass 25, count 2 2006.252.07:39:00.72#ibcon#about to read 3, iclass 25, count 2 2006.252.07:39:00.75#ibcon#read 3, iclass 25, count 2 2006.252.07:39:00.75#ibcon#about to read 4, iclass 25, count 2 2006.252.07:39:00.75#ibcon#read 4, iclass 25, count 2 2006.252.07:39:00.75#ibcon#about to read 5, iclass 25, count 2 2006.252.07:39:00.75#ibcon#read 5, iclass 25, count 2 2006.252.07:39:00.75#ibcon#about to read 6, iclass 25, count 2 2006.252.07:39:00.75#ibcon#read 6, iclass 25, count 2 2006.252.07:39:00.75#ibcon#end of sib2, iclass 25, count 2 2006.252.07:39:00.75#ibcon#*after write, iclass 25, count 2 2006.252.07:39:00.75#ibcon#*before return 0, iclass 25, count 2 2006.252.07:39:00.75#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.252.07:39:00.75#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.252.07:39:00.75#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.252.07:39:00.75#ibcon#ireg 7 cls_cnt 0 2006.252.07:39:00.75#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.252.07:39:00.87#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.252.07:39:00.87#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.252.07:39:00.87#ibcon#enter wrdev, iclass 25, count 0 2006.252.07:39:00.87#ibcon#first serial, iclass 25, count 0 2006.252.07:39:00.87#ibcon#enter sib2, iclass 25, count 0 2006.252.07:39:00.87#ibcon#flushed, iclass 25, count 0 2006.252.07:39:00.87#ibcon#about to write, iclass 25, count 0 2006.252.07:39:00.87#ibcon#wrote, iclass 25, count 0 2006.252.07:39:00.87#ibcon#about to read 3, iclass 25, count 0 2006.252.07:39:00.89#ibcon#read 3, iclass 25, count 0 2006.252.07:39:00.89#ibcon#about to read 4, iclass 25, count 0 2006.252.07:39:00.89#ibcon#read 4, iclass 25, count 0 2006.252.07:39:00.89#ibcon#about to read 5, iclass 25, count 0 2006.252.07:39:00.89#ibcon#read 5, iclass 25, count 0 2006.252.07:39:00.89#ibcon#about to read 6, iclass 25, count 0 2006.252.07:39:00.89#ibcon#read 6, iclass 25, count 0 2006.252.07:39:00.89#ibcon#end of sib2, iclass 25, count 0 2006.252.07:39:00.89#ibcon#*mode == 0, iclass 25, count 0 2006.252.07:39:00.89#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.252.07:39:00.89#ibcon#[27=USB\r\n] 2006.252.07:39:00.89#ibcon#*before write, iclass 25, count 0 2006.252.07:39:00.89#ibcon#enter sib2, iclass 25, count 0 2006.252.07:39:00.89#ibcon#flushed, iclass 25, count 0 2006.252.07:39:00.89#ibcon#about to write, iclass 25, count 0 2006.252.07:39:00.89#ibcon#wrote, iclass 25, count 0 2006.252.07:39:00.89#ibcon#about to read 3, iclass 25, count 0 2006.252.07:39:00.92#ibcon#read 3, iclass 25, count 0 2006.252.07:39:00.92#ibcon#about to read 4, iclass 25, count 0 2006.252.07:39:00.92#ibcon#read 4, iclass 25, count 0 2006.252.07:39:00.92#ibcon#about to read 5, iclass 25, count 0 2006.252.07:39:00.92#ibcon#read 5, iclass 25, count 0 2006.252.07:39:00.92#ibcon#about to read 6, iclass 25, count 0 2006.252.07:39:00.92#ibcon#read 6, iclass 25, count 0 2006.252.07:39:00.92#ibcon#end of sib2, iclass 25, count 0 2006.252.07:39:00.92#ibcon#*after write, iclass 25, count 0 2006.252.07:39:00.92#ibcon#*before return 0, iclass 25, count 0 2006.252.07:39:00.92#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.252.07:39:00.92#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.252.07:39:00.92#ibcon#about to clear, iclass 25 cls_cnt 0 2006.252.07:39:00.92#ibcon#cleared, iclass 25 cls_cnt 0 2006.252.07:39:00.92$vc4f8/vblo=2,640.99 2006.252.07:39:00.92#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.252.07:39:00.92#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.252.07:39:00.92#ibcon#ireg 17 cls_cnt 0 2006.252.07:39:00.92#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.252.07:39:00.92#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.252.07:39:00.92#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.252.07:39:00.92#ibcon#enter wrdev, iclass 27, count 0 2006.252.07:39:00.93#ibcon#first serial, iclass 27, count 0 2006.252.07:39:00.93#ibcon#enter sib2, iclass 27, count 0 2006.252.07:39:00.93#ibcon#flushed, iclass 27, count 0 2006.252.07:39:00.93#ibcon#about to write, iclass 27, count 0 2006.252.07:39:00.93#ibcon#wrote, iclass 27, count 0 2006.252.07:39:00.93#ibcon#about to read 3, iclass 27, count 0 2006.252.07:39:00.94#ibcon#read 3, iclass 27, count 0 2006.252.07:39:00.94#ibcon#about to read 4, iclass 27, count 0 2006.252.07:39:00.94#ibcon#read 4, iclass 27, count 0 2006.252.07:39:00.94#ibcon#about to read 5, iclass 27, count 0 2006.252.07:39:00.94#ibcon#read 5, iclass 27, count 0 2006.252.07:39:00.94#ibcon#about to read 6, iclass 27, count 0 2006.252.07:39:00.94#ibcon#read 6, iclass 27, count 0 2006.252.07:39:00.94#ibcon#end of sib2, iclass 27, count 0 2006.252.07:39:00.94#ibcon#*mode == 0, iclass 27, count 0 2006.252.07:39:00.94#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.252.07:39:00.94#ibcon#[28=FRQ=02,640.99\r\n] 2006.252.07:39:00.94#ibcon#*before write, iclass 27, count 0 2006.252.07:39:00.94#ibcon#enter sib2, iclass 27, count 0 2006.252.07:39:00.94#ibcon#flushed, iclass 27, count 0 2006.252.07:39:00.94#ibcon#about to write, iclass 27, count 0 2006.252.07:39:00.94#ibcon#wrote, iclass 27, count 0 2006.252.07:39:00.94#ibcon#about to read 3, iclass 27, count 0 2006.252.07:39:00.98#ibcon#read 3, iclass 27, count 0 2006.252.07:39:00.98#ibcon#about to read 4, iclass 27, count 0 2006.252.07:39:00.98#ibcon#read 4, iclass 27, count 0 2006.252.07:39:00.98#ibcon#about to read 5, iclass 27, count 0 2006.252.07:39:00.98#ibcon#read 5, iclass 27, count 0 2006.252.07:39:00.98#ibcon#about to read 6, iclass 27, count 0 2006.252.07:39:00.98#ibcon#read 6, iclass 27, count 0 2006.252.07:39:00.98#ibcon#end of sib2, iclass 27, count 0 2006.252.07:39:00.98#ibcon#*after write, iclass 27, count 0 2006.252.07:39:00.98#ibcon#*before return 0, iclass 27, count 0 2006.252.07:39:00.98#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.252.07:39:00.98#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.252.07:39:00.98#ibcon#about to clear, iclass 27 cls_cnt 0 2006.252.07:39:00.98#ibcon#cleared, iclass 27 cls_cnt 0 2006.252.07:39:00.98$vc4f8/vb=2,5 2006.252.07:39:00.98#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.252.07:39:00.98#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.252.07:39:00.98#ibcon#ireg 11 cls_cnt 2 2006.252.07:39:00.98#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.252.07:39:01.04#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.252.07:39:01.04#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.252.07:39:01.04#ibcon#enter wrdev, iclass 29, count 2 2006.252.07:39:01.04#ibcon#first serial, iclass 29, count 2 2006.252.07:39:01.04#ibcon#enter sib2, iclass 29, count 2 2006.252.07:39:01.04#ibcon#flushed, iclass 29, count 2 2006.252.07:39:01.04#ibcon#about to write, iclass 29, count 2 2006.252.07:39:01.04#ibcon#wrote, iclass 29, count 2 2006.252.07:39:01.04#ibcon#about to read 3, iclass 29, count 2 2006.252.07:39:01.06#ibcon#read 3, iclass 29, count 2 2006.252.07:39:01.06#ibcon#about to read 4, iclass 29, count 2 2006.252.07:39:01.06#ibcon#read 4, iclass 29, count 2 2006.252.07:39:01.06#ibcon#about to read 5, iclass 29, count 2 2006.252.07:39:01.06#ibcon#read 5, iclass 29, count 2 2006.252.07:39:01.06#ibcon#about to read 6, iclass 29, count 2 2006.252.07:39:01.06#ibcon#read 6, iclass 29, count 2 2006.252.07:39:01.06#ibcon#end of sib2, iclass 29, count 2 2006.252.07:39:01.06#ibcon#*mode == 0, iclass 29, count 2 2006.252.07:39:01.06#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.252.07:39:01.06#ibcon#[27=AT02-05\r\n] 2006.252.07:39:01.06#ibcon#*before write, iclass 29, count 2 2006.252.07:39:01.06#ibcon#enter sib2, iclass 29, count 2 2006.252.07:39:01.06#ibcon#flushed, iclass 29, count 2 2006.252.07:39:01.06#ibcon#about to write, iclass 29, count 2 2006.252.07:39:01.06#ibcon#wrote, iclass 29, count 2 2006.252.07:39:01.06#ibcon#about to read 3, iclass 29, count 2 2006.252.07:39:01.09#ibcon#read 3, iclass 29, count 2 2006.252.07:39:01.09#ibcon#about to read 4, iclass 29, count 2 2006.252.07:39:01.09#ibcon#read 4, iclass 29, count 2 2006.252.07:39:01.09#ibcon#about to read 5, iclass 29, count 2 2006.252.07:39:01.09#ibcon#read 5, iclass 29, count 2 2006.252.07:39:01.09#ibcon#about to read 6, iclass 29, count 2 2006.252.07:39:01.09#ibcon#read 6, iclass 29, count 2 2006.252.07:39:01.09#ibcon#end of sib2, iclass 29, count 2 2006.252.07:39:01.09#ibcon#*after write, iclass 29, count 2 2006.252.07:39:01.09#ibcon#*before return 0, iclass 29, count 2 2006.252.07:39:01.09#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.252.07:39:01.09#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.252.07:39:01.09#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.252.07:39:01.09#ibcon#ireg 7 cls_cnt 0 2006.252.07:39:01.09#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.252.07:39:01.21#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.252.07:39:01.21#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.252.07:39:01.21#ibcon#enter wrdev, iclass 29, count 0 2006.252.07:39:01.21#ibcon#first serial, iclass 29, count 0 2006.252.07:39:01.21#ibcon#enter sib2, iclass 29, count 0 2006.252.07:39:01.21#ibcon#flushed, iclass 29, count 0 2006.252.07:39:01.21#ibcon#about to write, iclass 29, count 0 2006.252.07:39:01.21#ibcon#wrote, iclass 29, count 0 2006.252.07:39:01.21#ibcon#about to read 3, iclass 29, count 0 2006.252.07:39:01.23#ibcon#read 3, iclass 29, count 0 2006.252.07:39:01.23#ibcon#about to read 4, iclass 29, count 0 2006.252.07:39:01.23#ibcon#read 4, iclass 29, count 0 2006.252.07:39:01.23#ibcon#about to read 5, iclass 29, count 0 2006.252.07:39:01.23#ibcon#read 5, iclass 29, count 0 2006.252.07:39:01.23#ibcon#about to read 6, iclass 29, count 0 2006.252.07:39:01.23#ibcon#read 6, iclass 29, count 0 2006.252.07:39:01.23#ibcon#end of sib2, iclass 29, count 0 2006.252.07:39:01.23#ibcon#*mode == 0, iclass 29, count 0 2006.252.07:39:01.23#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.252.07:39:01.23#ibcon#[27=USB\r\n] 2006.252.07:39:01.23#ibcon#*before write, iclass 29, count 0 2006.252.07:39:01.23#ibcon#enter sib2, iclass 29, count 0 2006.252.07:39:01.23#ibcon#flushed, iclass 29, count 0 2006.252.07:39:01.23#ibcon#about to write, iclass 29, count 0 2006.252.07:39:01.23#ibcon#wrote, iclass 29, count 0 2006.252.07:39:01.23#ibcon#about to read 3, iclass 29, count 0 2006.252.07:39:01.26#ibcon#read 3, iclass 29, count 0 2006.252.07:39:01.26#ibcon#about to read 4, iclass 29, count 0 2006.252.07:39:01.26#ibcon#read 4, iclass 29, count 0 2006.252.07:39:01.26#ibcon#about to read 5, iclass 29, count 0 2006.252.07:39:01.26#ibcon#read 5, iclass 29, count 0 2006.252.07:39:01.26#ibcon#about to read 6, iclass 29, count 0 2006.252.07:39:01.26#ibcon#read 6, iclass 29, count 0 2006.252.07:39:01.26#ibcon#end of sib2, iclass 29, count 0 2006.252.07:39:01.26#ibcon#*after write, iclass 29, count 0 2006.252.07:39:01.26#ibcon#*before return 0, iclass 29, count 0 2006.252.07:39:01.26#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.252.07:39:01.26#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.252.07:39:01.26#ibcon#about to clear, iclass 29 cls_cnt 0 2006.252.07:39:01.26#ibcon#cleared, iclass 29 cls_cnt 0 2006.252.07:39:01.26$vc4f8/vblo=3,656.99 2006.252.07:39:01.26#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.252.07:39:01.26#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.252.07:39:01.26#ibcon#ireg 17 cls_cnt 0 2006.252.07:39:01.27#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.252.07:39:01.27#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.252.07:39:01.27#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.252.07:39:01.27#ibcon#enter wrdev, iclass 31, count 0 2006.252.07:39:01.27#ibcon#first serial, iclass 31, count 0 2006.252.07:39:01.27#ibcon#enter sib2, iclass 31, count 0 2006.252.07:39:01.27#ibcon#flushed, iclass 31, count 0 2006.252.07:39:01.27#ibcon#about to write, iclass 31, count 0 2006.252.07:39:01.27#ibcon#wrote, iclass 31, count 0 2006.252.07:39:01.27#ibcon#about to read 3, iclass 31, count 0 2006.252.07:39:01.28#ibcon#read 3, iclass 31, count 0 2006.252.07:39:01.28#ibcon#about to read 4, iclass 31, count 0 2006.252.07:39:01.28#ibcon#read 4, iclass 31, count 0 2006.252.07:39:01.28#ibcon#about to read 5, iclass 31, count 0 2006.252.07:39:01.28#ibcon#read 5, iclass 31, count 0 2006.252.07:39:01.28#ibcon#about to read 6, iclass 31, count 0 2006.252.07:39:01.28#ibcon#read 6, iclass 31, count 0 2006.252.07:39:01.28#ibcon#end of sib2, iclass 31, count 0 2006.252.07:39:01.28#ibcon#*mode == 0, iclass 31, count 0 2006.252.07:39:01.28#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.252.07:39:01.28#ibcon#[28=FRQ=03,656.99\r\n] 2006.252.07:39:01.28#ibcon#*before write, iclass 31, count 0 2006.252.07:39:01.28#ibcon#enter sib2, iclass 31, count 0 2006.252.07:39:01.28#ibcon#flushed, iclass 31, count 0 2006.252.07:39:01.28#ibcon#about to write, iclass 31, count 0 2006.252.07:39:01.28#ibcon#wrote, iclass 31, count 0 2006.252.07:39:01.28#ibcon#about to read 3, iclass 31, count 0 2006.252.07:39:01.32#ibcon#read 3, iclass 31, count 0 2006.252.07:39:01.32#ibcon#about to read 4, iclass 31, count 0 2006.252.07:39:01.32#ibcon#read 4, iclass 31, count 0 2006.252.07:39:01.32#ibcon#about to read 5, iclass 31, count 0 2006.252.07:39:01.32#ibcon#read 5, iclass 31, count 0 2006.252.07:39:01.32#ibcon#about to read 6, iclass 31, count 0 2006.252.07:39:01.32#ibcon#read 6, iclass 31, count 0 2006.252.07:39:01.32#ibcon#end of sib2, iclass 31, count 0 2006.252.07:39:01.32#ibcon#*after write, iclass 31, count 0 2006.252.07:39:01.32#ibcon#*before return 0, iclass 31, count 0 2006.252.07:39:01.32#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.252.07:39:01.32#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.252.07:39:01.32#ibcon#about to clear, iclass 31 cls_cnt 0 2006.252.07:39:01.32#ibcon#cleared, iclass 31 cls_cnt 0 2006.252.07:39:01.32$vc4f8/vb=3,4 2006.252.07:39:01.32#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.252.07:39:01.32#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.252.07:39:01.32#ibcon#ireg 11 cls_cnt 2 2006.252.07:39:01.32#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.252.07:39:01.38#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.252.07:39:01.38#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.252.07:39:01.38#ibcon#enter wrdev, iclass 33, count 2 2006.252.07:39:01.38#ibcon#first serial, iclass 33, count 2 2006.252.07:39:01.38#ibcon#enter sib2, iclass 33, count 2 2006.252.07:39:01.38#ibcon#flushed, iclass 33, count 2 2006.252.07:39:01.38#ibcon#about to write, iclass 33, count 2 2006.252.07:39:01.38#ibcon#wrote, iclass 33, count 2 2006.252.07:39:01.38#ibcon#about to read 3, iclass 33, count 2 2006.252.07:39:01.40#ibcon#read 3, iclass 33, count 2 2006.252.07:39:01.40#ibcon#about to read 4, iclass 33, count 2 2006.252.07:39:01.40#ibcon#read 4, iclass 33, count 2 2006.252.07:39:01.40#ibcon#about to read 5, iclass 33, count 2 2006.252.07:39:01.40#ibcon#read 5, iclass 33, count 2 2006.252.07:39:01.40#ibcon#about to read 6, iclass 33, count 2 2006.252.07:39:01.40#ibcon#read 6, iclass 33, count 2 2006.252.07:39:01.40#ibcon#end of sib2, iclass 33, count 2 2006.252.07:39:01.40#ibcon#*mode == 0, iclass 33, count 2 2006.252.07:39:01.40#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.252.07:39:01.40#ibcon#[27=AT03-04\r\n] 2006.252.07:39:01.40#ibcon#*before write, iclass 33, count 2 2006.252.07:39:01.40#ibcon#enter sib2, iclass 33, count 2 2006.252.07:39:01.40#ibcon#flushed, iclass 33, count 2 2006.252.07:39:01.40#ibcon#about to write, iclass 33, count 2 2006.252.07:39:01.40#ibcon#wrote, iclass 33, count 2 2006.252.07:39:01.40#ibcon#about to read 3, iclass 33, count 2 2006.252.07:39:01.43#ibcon#read 3, iclass 33, count 2 2006.252.07:39:01.43#ibcon#about to read 4, iclass 33, count 2 2006.252.07:39:01.43#ibcon#read 4, iclass 33, count 2 2006.252.07:39:01.43#ibcon#about to read 5, iclass 33, count 2 2006.252.07:39:01.43#ibcon#read 5, iclass 33, count 2 2006.252.07:39:01.43#ibcon#about to read 6, iclass 33, count 2 2006.252.07:39:01.43#ibcon#read 6, iclass 33, count 2 2006.252.07:39:01.43#ibcon#end of sib2, iclass 33, count 2 2006.252.07:39:01.43#ibcon#*after write, iclass 33, count 2 2006.252.07:39:01.43#ibcon#*before return 0, iclass 33, count 2 2006.252.07:39:01.43#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.252.07:39:01.43#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.252.07:39:01.43#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.252.07:39:01.43#ibcon#ireg 7 cls_cnt 0 2006.252.07:39:01.43#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.252.07:39:01.55#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.252.07:39:01.55#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.252.07:39:01.55#ibcon#enter wrdev, iclass 33, count 0 2006.252.07:39:01.55#ibcon#first serial, iclass 33, count 0 2006.252.07:39:01.55#ibcon#enter sib2, iclass 33, count 0 2006.252.07:39:01.55#ibcon#flushed, iclass 33, count 0 2006.252.07:39:01.55#ibcon#about to write, iclass 33, count 0 2006.252.07:39:01.55#ibcon#wrote, iclass 33, count 0 2006.252.07:39:01.55#ibcon#about to read 3, iclass 33, count 0 2006.252.07:39:01.57#ibcon#read 3, iclass 33, count 0 2006.252.07:39:01.57#ibcon#about to read 4, iclass 33, count 0 2006.252.07:39:01.57#ibcon#read 4, iclass 33, count 0 2006.252.07:39:01.57#ibcon#about to read 5, iclass 33, count 0 2006.252.07:39:01.57#ibcon#read 5, iclass 33, count 0 2006.252.07:39:01.57#ibcon#about to read 6, iclass 33, count 0 2006.252.07:39:01.57#ibcon#read 6, iclass 33, count 0 2006.252.07:39:01.57#ibcon#end of sib2, iclass 33, count 0 2006.252.07:39:01.57#ibcon#*mode == 0, iclass 33, count 0 2006.252.07:39:01.57#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.252.07:39:01.57#ibcon#[27=USB\r\n] 2006.252.07:39:01.57#ibcon#*before write, iclass 33, count 0 2006.252.07:39:01.57#ibcon#enter sib2, iclass 33, count 0 2006.252.07:39:01.57#ibcon#flushed, iclass 33, count 0 2006.252.07:39:01.57#ibcon#about to write, iclass 33, count 0 2006.252.07:39:01.57#ibcon#wrote, iclass 33, count 0 2006.252.07:39:01.57#ibcon#about to read 3, iclass 33, count 0 2006.252.07:39:01.60#ibcon#read 3, iclass 33, count 0 2006.252.07:39:01.60#ibcon#about to read 4, iclass 33, count 0 2006.252.07:39:01.60#ibcon#read 4, iclass 33, count 0 2006.252.07:39:01.60#ibcon#about to read 5, iclass 33, count 0 2006.252.07:39:01.60#ibcon#read 5, iclass 33, count 0 2006.252.07:39:01.60#ibcon#about to read 6, iclass 33, count 0 2006.252.07:39:01.60#ibcon#read 6, iclass 33, count 0 2006.252.07:39:01.60#ibcon#end of sib2, iclass 33, count 0 2006.252.07:39:01.60#ibcon#*after write, iclass 33, count 0 2006.252.07:39:01.60#ibcon#*before return 0, iclass 33, count 0 2006.252.07:39:01.60#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.252.07:39:01.60#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.252.07:39:01.60#ibcon#about to clear, iclass 33 cls_cnt 0 2006.252.07:39:01.60#ibcon#cleared, iclass 33 cls_cnt 0 2006.252.07:39:01.60$vc4f8/vblo=4,712.99 2006.252.07:39:01.60#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.252.07:39:01.60#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.252.07:39:01.60#ibcon#ireg 17 cls_cnt 0 2006.252.07:39:01.60#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.252.07:39:01.60#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.252.07:39:01.60#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.252.07:39:01.60#ibcon#enter wrdev, iclass 35, count 0 2006.252.07:39:01.60#ibcon#first serial, iclass 35, count 0 2006.252.07:39:01.60#ibcon#enter sib2, iclass 35, count 0 2006.252.07:39:01.61#ibcon#flushed, iclass 35, count 0 2006.252.07:39:01.61#ibcon#about to write, iclass 35, count 0 2006.252.07:39:01.61#ibcon#wrote, iclass 35, count 0 2006.252.07:39:01.61#ibcon#about to read 3, iclass 35, count 0 2006.252.07:39:01.62#ibcon#read 3, iclass 35, count 0 2006.252.07:39:01.62#ibcon#about to read 4, iclass 35, count 0 2006.252.07:39:01.62#ibcon#read 4, iclass 35, count 0 2006.252.07:39:01.62#ibcon#about to read 5, iclass 35, count 0 2006.252.07:39:01.62#ibcon#read 5, iclass 35, count 0 2006.252.07:39:01.62#ibcon#about to read 6, iclass 35, count 0 2006.252.07:39:01.62#ibcon#read 6, iclass 35, count 0 2006.252.07:39:01.62#ibcon#end of sib2, iclass 35, count 0 2006.252.07:39:01.62#ibcon#*mode == 0, iclass 35, count 0 2006.252.07:39:01.62#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.252.07:39:01.62#ibcon#[28=FRQ=04,712.99\r\n] 2006.252.07:39:01.62#ibcon#*before write, iclass 35, count 0 2006.252.07:39:01.62#ibcon#enter sib2, iclass 35, count 0 2006.252.07:39:01.62#ibcon#flushed, iclass 35, count 0 2006.252.07:39:01.62#ibcon#about to write, iclass 35, count 0 2006.252.07:39:01.62#ibcon#wrote, iclass 35, count 0 2006.252.07:39:01.62#ibcon#about to read 3, iclass 35, count 0 2006.252.07:39:01.66#ibcon#read 3, iclass 35, count 0 2006.252.07:39:01.66#ibcon#about to read 4, iclass 35, count 0 2006.252.07:39:01.66#ibcon#read 4, iclass 35, count 0 2006.252.07:39:01.66#ibcon#about to read 5, iclass 35, count 0 2006.252.07:39:01.66#ibcon#read 5, iclass 35, count 0 2006.252.07:39:01.66#ibcon#about to read 6, iclass 35, count 0 2006.252.07:39:01.66#ibcon#read 6, iclass 35, count 0 2006.252.07:39:01.66#ibcon#end of sib2, iclass 35, count 0 2006.252.07:39:01.66#ibcon#*after write, iclass 35, count 0 2006.252.07:39:01.66#ibcon#*before return 0, iclass 35, count 0 2006.252.07:39:01.66#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.252.07:39:01.66#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.252.07:39:01.66#ibcon#about to clear, iclass 35 cls_cnt 0 2006.252.07:39:01.66#ibcon#cleared, iclass 35 cls_cnt 0 2006.252.07:39:01.66$vc4f8/vb=4,4 2006.252.07:39:01.66#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.252.07:39:01.66#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.252.07:39:01.66#ibcon#ireg 11 cls_cnt 2 2006.252.07:39:01.66#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.252.07:39:01.72#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.252.07:39:01.72#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.252.07:39:01.72#ibcon#enter wrdev, iclass 37, count 2 2006.252.07:39:01.72#ibcon#first serial, iclass 37, count 2 2006.252.07:39:01.72#ibcon#enter sib2, iclass 37, count 2 2006.252.07:39:01.72#ibcon#flushed, iclass 37, count 2 2006.252.07:39:01.72#ibcon#about to write, iclass 37, count 2 2006.252.07:39:01.72#ibcon#wrote, iclass 37, count 2 2006.252.07:39:01.72#ibcon#about to read 3, iclass 37, count 2 2006.252.07:39:01.74#ibcon#read 3, iclass 37, count 2 2006.252.07:39:01.74#ibcon#about to read 4, iclass 37, count 2 2006.252.07:39:01.74#ibcon#read 4, iclass 37, count 2 2006.252.07:39:01.74#ibcon#about to read 5, iclass 37, count 2 2006.252.07:39:01.74#ibcon#read 5, iclass 37, count 2 2006.252.07:39:01.74#ibcon#about to read 6, iclass 37, count 2 2006.252.07:39:01.74#ibcon#read 6, iclass 37, count 2 2006.252.07:39:01.74#ibcon#end of sib2, iclass 37, count 2 2006.252.07:39:01.74#ibcon#*mode == 0, iclass 37, count 2 2006.252.07:39:01.74#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.252.07:39:01.74#ibcon#[27=AT04-04\r\n] 2006.252.07:39:01.74#ibcon#*before write, iclass 37, count 2 2006.252.07:39:01.74#ibcon#enter sib2, iclass 37, count 2 2006.252.07:39:01.74#ibcon#flushed, iclass 37, count 2 2006.252.07:39:01.74#ibcon#about to write, iclass 37, count 2 2006.252.07:39:01.74#ibcon#wrote, iclass 37, count 2 2006.252.07:39:01.74#ibcon#about to read 3, iclass 37, count 2 2006.252.07:39:01.77#ibcon#read 3, iclass 37, count 2 2006.252.07:39:01.77#ibcon#about to read 4, iclass 37, count 2 2006.252.07:39:01.77#ibcon#read 4, iclass 37, count 2 2006.252.07:39:01.77#ibcon#about to read 5, iclass 37, count 2 2006.252.07:39:01.77#ibcon#read 5, iclass 37, count 2 2006.252.07:39:01.77#ibcon#about to read 6, iclass 37, count 2 2006.252.07:39:01.77#ibcon#read 6, iclass 37, count 2 2006.252.07:39:01.77#ibcon#end of sib2, iclass 37, count 2 2006.252.07:39:01.77#ibcon#*after write, iclass 37, count 2 2006.252.07:39:01.77#ibcon#*before return 0, iclass 37, count 2 2006.252.07:39:01.77#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.252.07:39:01.77#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.252.07:39:01.77#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.252.07:39:01.77#ibcon#ireg 7 cls_cnt 0 2006.252.07:39:01.77#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.252.07:39:01.89#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.252.07:39:01.89#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.252.07:39:01.89#ibcon#enter wrdev, iclass 37, count 0 2006.252.07:39:01.89#ibcon#first serial, iclass 37, count 0 2006.252.07:39:01.89#ibcon#enter sib2, iclass 37, count 0 2006.252.07:39:01.89#ibcon#flushed, iclass 37, count 0 2006.252.07:39:01.89#ibcon#about to write, iclass 37, count 0 2006.252.07:39:01.89#ibcon#wrote, iclass 37, count 0 2006.252.07:39:01.89#ibcon#about to read 3, iclass 37, count 0 2006.252.07:39:01.91#ibcon#read 3, iclass 37, count 0 2006.252.07:39:01.91#ibcon#about to read 4, iclass 37, count 0 2006.252.07:39:01.91#ibcon#read 4, iclass 37, count 0 2006.252.07:39:01.91#ibcon#about to read 5, iclass 37, count 0 2006.252.07:39:01.91#ibcon#read 5, iclass 37, count 0 2006.252.07:39:01.91#ibcon#about to read 6, iclass 37, count 0 2006.252.07:39:01.91#ibcon#read 6, iclass 37, count 0 2006.252.07:39:01.91#ibcon#end of sib2, iclass 37, count 0 2006.252.07:39:01.91#ibcon#*mode == 0, iclass 37, count 0 2006.252.07:39:01.91#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.252.07:39:01.91#ibcon#[27=USB\r\n] 2006.252.07:39:01.91#ibcon#*before write, iclass 37, count 0 2006.252.07:39:01.91#ibcon#enter sib2, iclass 37, count 0 2006.252.07:39:01.91#ibcon#flushed, iclass 37, count 0 2006.252.07:39:01.91#ibcon#about to write, iclass 37, count 0 2006.252.07:39:01.91#ibcon#wrote, iclass 37, count 0 2006.252.07:39:01.91#ibcon#about to read 3, iclass 37, count 0 2006.252.07:39:01.94#ibcon#read 3, iclass 37, count 0 2006.252.07:39:01.94#ibcon#about to read 4, iclass 37, count 0 2006.252.07:39:01.94#ibcon#read 4, iclass 37, count 0 2006.252.07:39:01.94#ibcon#about to read 5, iclass 37, count 0 2006.252.07:39:01.94#ibcon#read 5, iclass 37, count 0 2006.252.07:39:01.94#ibcon#about to read 6, iclass 37, count 0 2006.252.07:39:01.94#ibcon#read 6, iclass 37, count 0 2006.252.07:39:01.94#ibcon#end of sib2, iclass 37, count 0 2006.252.07:39:01.94#ibcon#*after write, iclass 37, count 0 2006.252.07:39:01.94#ibcon#*before return 0, iclass 37, count 0 2006.252.07:39:01.94#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.252.07:39:01.94#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.252.07:39:01.94#ibcon#about to clear, iclass 37 cls_cnt 0 2006.252.07:39:01.94#ibcon#cleared, iclass 37 cls_cnt 0 2006.252.07:39:01.94$vc4f8/vblo=5,744.99 2006.252.07:39:01.94#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.252.07:39:01.94#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.252.07:39:01.94#ibcon#ireg 17 cls_cnt 0 2006.252.07:39:01.94#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.252.07:39:01.94#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.252.07:39:01.94#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.252.07:39:01.94#ibcon#enter wrdev, iclass 39, count 0 2006.252.07:39:01.94#ibcon#first serial, iclass 39, count 0 2006.252.07:39:01.94#ibcon#enter sib2, iclass 39, count 0 2006.252.07:39:01.95#ibcon#flushed, iclass 39, count 0 2006.252.07:39:01.95#ibcon#about to write, iclass 39, count 0 2006.252.07:39:01.95#ibcon#wrote, iclass 39, count 0 2006.252.07:39:01.95#ibcon#about to read 3, iclass 39, count 0 2006.252.07:39:01.96#ibcon#read 3, iclass 39, count 0 2006.252.07:39:01.96#ibcon#about to read 4, iclass 39, count 0 2006.252.07:39:01.96#ibcon#read 4, iclass 39, count 0 2006.252.07:39:01.96#ibcon#about to read 5, iclass 39, count 0 2006.252.07:39:01.96#ibcon#read 5, iclass 39, count 0 2006.252.07:39:01.96#ibcon#about to read 6, iclass 39, count 0 2006.252.07:39:01.96#ibcon#read 6, iclass 39, count 0 2006.252.07:39:01.96#ibcon#end of sib2, iclass 39, count 0 2006.252.07:39:01.96#ibcon#*mode == 0, iclass 39, count 0 2006.252.07:39:01.96#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.252.07:39:01.96#ibcon#[28=FRQ=05,744.99\r\n] 2006.252.07:39:01.96#ibcon#*before write, iclass 39, count 0 2006.252.07:39:01.96#ibcon#enter sib2, iclass 39, count 0 2006.252.07:39:01.96#ibcon#flushed, iclass 39, count 0 2006.252.07:39:01.96#ibcon#about to write, iclass 39, count 0 2006.252.07:39:01.96#ibcon#wrote, iclass 39, count 0 2006.252.07:39:01.96#ibcon#about to read 3, iclass 39, count 0 2006.252.07:39:02.00#ibcon#read 3, iclass 39, count 0 2006.252.07:39:02.00#ibcon#about to read 4, iclass 39, count 0 2006.252.07:39:02.00#ibcon#read 4, iclass 39, count 0 2006.252.07:39:02.00#ibcon#about to read 5, iclass 39, count 0 2006.252.07:39:02.00#ibcon#read 5, iclass 39, count 0 2006.252.07:39:02.00#ibcon#about to read 6, iclass 39, count 0 2006.252.07:39:02.00#ibcon#read 6, iclass 39, count 0 2006.252.07:39:02.00#ibcon#end of sib2, iclass 39, count 0 2006.252.07:39:02.00#ibcon#*after write, iclass 39, count 0 2006.252.07:39:02.00#ibcon#*before return 0, iclass 39, count 0 2006.252.07:39:02.00#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.252.07:39:02.00#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.252.07:39:02.00#ibcon#about to clear, iclass 39 cls_cnt 0 2006.252.07:39:02.00#ibcon#cleared, iclass 39 cls_cnt 0 2006.252.07:39:02.00$vc4f8/vb=5,4 2006.252.07:39:02.00#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.252.07:39:02.00#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.252.07:39:02.00#ibcon#ireg 11 cls_cnt 2 2006.252.07:39:02.00#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.252.07:39:02.06#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.252.07:39:02.06#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.252.07:39:02.06#ibcon#enter wrdev, iclass 3, count 2 2006.252.07:39:02.06#ibcon#first serial, iclass 3, count 2 2006.252.07:39:02.06#ibcon#enter sib2, iclass 3, count 2 2006.252.07:39:02.06#ibcon#flushed, iclass 3, count 2 2006.252.07:39:02.06#ibcon#about to write, iclass 3, count 2 2006.252.07:39:02.06#ibcon#wrote, iclass 3, count 2 2006.252.07:39:02.06#ibcon#about to read 3, iclass 3, count 2 2006.252.07:39:02.08#ibcon#read 3, iclass 3, count 2 2006.252.07:39:02.08#ibcon#about to read 4, iclass 3, count 2 2006.252.07:39:02.08#ibcon#read 4, iclass 3, count 2 2006.252.07:39:02.08#ibcon#about to read 5, iclass 3, count 2 2006.252.07:39:02.08#ibcon#read 5, iclass 3, count 2 2006.252.07:39:02.08#ibcon#about to read 6, iclass 3, count 2 2006.252.07:39:02.08#ibcon#read 6, iclass 3, count 2 2006.252.07:39:02.08#ibcon#end of sib2, iclass 3, count 2 2006.252.07:39:02.08#ibcon#*mode == 0, iclass 3, count 2 2006.252.07:39:02.08#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.252.07:39:02.08#ibcon#[27=AT05-04\r\n] 2006.252.07:39:02.08#ibcon#*before write, iclass 3, count 2 2006.252.07:39:02.08#ibcon#enter sib2, iclass 3, count 2 2006.252.07:39:02.08#ibcon#flushed, iclass 3, count 2 2006.252.07:39:02.08#ibcon#about to write, iclass 3, count 2 2006.252.07:39:02.08#ibcon#wrote, iclass 3, count 2 2006.252.07:39:02.08#ibcon#about to read 3, iclass 3, count 2 2006.252.07:39:02.11#ibcon#read 3, iclass 3, count 2 2006.252.07:39:02.11#ibcon#about to read 4, iclass 3, count 2 2006.252.07:39:02.11#ibcon#read 4, iclass 3, count 2 2006.252.07:39:02.11#ibcon#about to read 5, iclass 3, count 2 2006.252.07:39:02.11#ibcon#read 5, iclass 3, count 2 2006.252.07:39:02.11#ibcon#about to read 6, iclass 3, count 2 2006.252.07:39:02.11#ibcon#read 6, iclass 3, count 2 2006.252.07:39:02.11#ibcon#end of sib2, iclass 3, count 2 2006.252.07:39:02.11#ibcon#*after write, iclass 3, count 2 2006.252.07:39:02.11#ibcon#*before return 0, iclass 3, count 2 2006.252.07:39:02.11#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.252.07:39:02.11#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.252.07:39:02.11#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.252.07:39:02.11#ibcon#ireg 7 cls_cnt 0 2006.252.07:39:02.11#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.252.07:39:02.23#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.252.07:39:02.23#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.252.07:39:02.23#ibcon#enter wrdev, iclass 3, count 0 2006.252.07:39:02.23#ibcon#first serial, iclass 3, count 0 2006.252.07:39:02.23#ibcon#enter sib2, iclass 3, count 0 2006.252.07:39:02.23#ibcon#flushed, iclass 3, count 0 2006.252.07:39:02.23#ibcon#about to write, iclass 3, count 0 2006.252.07:39:02.23#ibcon#wrote, iclass 3, count 0 2006.252.07:39:02.23#ibcon#about to read 3, iclass 3, count 0 2006.252.07:39:02.25#ibcon#read 3, iclass 3, count 0 2006.252.07:39:02.25#ibcon#about to read 4, iclass 3, count 0 2006.252.07:39:02.25#ibcon#read 4, iclass 3, count 0 2006.252.07:39:02.25#ibcon#about to read 5, iclass 3, count 0 2006.252.07:39:02.25#ibcon#read 5, iclass 3, count 0 2006.252.07:39:02.25#ibcon#about to read 6, iclass 3, count 0 2006.252.07:39:02.25#ibcon#read 6, iclass 3, count 0 2006.252.07:39:02.25#ibcon#end of sib2, iclass 3, count 0 2006.252.07:39:02.25#ibcon#*mode == 0, iclass 3, count 0 2006.252.07:39:02.25#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.252.07:39:02.25#ibcon#[27=USB\r\n] 2006.252.07:39:02.25#ibcon#*before write, iclass 3, count 0 2006.252.07:39:02.25#ibcon#enter sib2, iclass 3, count 0 2006.252.07:39:02.25#ibcon#flushed, iclass 3, count 0 2006.252.07:39:02.25#ibcon#about to write, iclass 3, count 0 2006.252.07:39:02.25#ibcon#wrote, iclass 3, count 0 2006.252.07:39:02.25#ibcon#about to read 3, iclass 3, count 0 2006.252.07:39:02.28#ibcon#read 3, iclass 3, count 0 2006.252.07:39:02.28#ibcon#about to read 4, iclass 3, count 0 2006.252.07:39:02.28#ibcon#read 4, iclass 3, count 0 2006.252.07:39:02.28#ibcon#about to read 5, iclass 3, count 0 2006.252.07:39:02.28#ibcon#read 5, iclass 3, count 0 2006.252.07:39:02.28#ibcon#about to read 6, iclass 3, count 0 2006.252.07:39:02.28#ibcon#read 6, iclass 3, count 0 2006.252.07:39:02.28#ibcon#end of sib2, iclass 3, count 0 2006.252.07:39:02.28#ibcon#*after write, iclass 3, count 0 2006.252.07:39:02.28#ibcon#*before return 0, iclass 3, count 0 2006.252.07:39:02.28#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.252.07:39:02.28#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.252.07:39:02.28#ibcon#about to clear, iclass 3 cls_cnt 0 2006.252.07:39:02.28#ibcon#cleared, iclass 3 cls_cnt 0 2006.252.07:39:02.28$vc4f8/vblo=6,752.99 2006.252.07:39:02.28#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.252.07:39:02.28#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.252.07:39:02.29#ibcon#ireg 17 cls_cnt 0 2006.252.07:39:02.29#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.252.07:39:02.29#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.252.07:39:02.29#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.252.07:39:02.29#ibcon#enter wrdev, iclass 5, count 0 2006.252.07:39:02.29#ibcon#first serial, iclass 5, count 0 2006.252.07:39:02.29#ibcon#enter sib2, iclass 5, count 0 2006.252.07:39:02.29#ibcon#flushed, iclass 5, count 0 2006.252.07:39:02.29#ibcon#about to write, iclass 5, count 0 2006.252.07:39:02.29#ibcon#wrote, iclass 5, count 0 2006.252.07:39:02.29#ibcon#about to read 3, iclass 5, count 0 2006.252.07:39:02.30#ibcon#read 3, iclass 5, count 0 2006.252.07:39:02.30#ibcon#about to read 4, iclass 5, count 0 2006.252.07:39:02.30#ibcon#read 4, iclass 5, count 0 2006.252.07:39:02.30#ibcon#about to read 5, iclass 5, count 0 2006.252.07:39:02.30#ibcon#read 5, iclass 5, count 0 2006.252.07:39:02.30#ibcon#about to read 6, iclass 5, count 0 2006.252.07:39:02.30#ibcon#read 6, iclass 5, count 0 2006.252.07:39:02.30#ibcon#end of sib2, iclass 5, count 0 2006.252.07:39:02.30#ibcon#*mode == 0, iclass 5, count 0 2006.252.07:39:02.30#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.252.07:39:02.30#ibcon#[28=FRQ=06,752.99\r\n] 2006.252.07:39:02.30#ibcon#*before write, iclass 5, count 0 2006.252.07:39:02.30#ibcon#enter sib2, iclass 5, count 0 2006.252.07:39:02.30#ibcon#flushed, iclass 5, count 0 2006.252.07:39:02.30#ibcon#about to write, iclass 5, count 0 2006.252.07:39:02.30#ibcon#wrote, iclass 5, count 0 2006.252.07:39:02.30#ibcon#about to read 3, iclass 5, count 0 2006.252.07:39:02.34#ibcon#read 3, iclass 5, count 0 2006.252.07:39:02.34#ibcon#about to read 4, iclass 5, count 0 2006.252.07:39:02.34#ibcon#read 4, iclass 5, count 0 2006.252.07:39:02.34#ibcon#about to read 5, iclass 5, count 0 2006.252.07:39:02.34#ibcon#read 5, iclass 5, count 0 2006.252.07:39:02.34#ibcon#about to read 6, iclass 5, count 0 2006.252.07:39:02.34#ibcon#read 6, iclass 5, count 0 2006.252.07:39:02.34#ibcon#end of sib2, iclass 5, count 0 2006.252.07:39:02.34#ibcon#*after write, iclass 5, count 0 2006.252.07:39:02.34#ibcon#*before return 0, iclass 5, count 0 2006.252.07:39:02.34#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.252.07:39:02.34#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.252.07:39:02.34#ibcon#about to clear, iclass 5 cls_cnt 0 2006.252.07:39:02.34#ibcon#cleared, iclass 5 cls_cnt 0 2006.252.07:39:02.34$vc4f8/vb=6,4 2006.252.07:39:02.35#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.252.07:39:02.35#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.252.07:39:02.35#ibcon#ireg 11 cls_cnt 2 2006.252.07:39:02.35#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.252.07:39:02.39#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.252.07:39:02.39#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.252.07:39:02.39#ibcon#enter wrdev, iclass 7, count 2 2006.252.07:39:02.39#ibcon#first serial, iclass 7, count 2 2006.252.07:39:02.39#ibcon#enter sib2, iclass 7, count 2 2006.252.07:39:02.39#ibcon#flushed, iclass 7, count 2 2006.252.07:39:02.39#ibcon#about to write, iclass 7, count 2 2006.252.07:39:02.39#ibcon#wrote, iclass 7, count 2 2006.252.07:39:02.39#ibcon#about to read 3, iclass 7, count 2 2006.252.07:39:02.41#ibcon#read 3, iclass 7, count 2 2006.252.07:39:02.41#ibcon#about to read 4, iclass 7, count 2 2006.252.07:39:02.41#ibcon#read 4, iclass 7, count 2 2006.252.07:39:02.41#ibcon#about to read 5, iclass 7, count 2 2006.252.07:39:02.41#ibcon#read 5, iclass 7, count 2 2006.252.07:39:02.41#ibcon#about to read 6, iclass 7, count 2 2006.252.07:39:02.41#ibcon#read 6, iclass 7, count 2 2006.252.07:39:02.41#ibcon#end of sib2, iclass 7, count 2 2006.252.07:39:02.41#ibcon#*mode == 0, iclass 7, count 2 2006.252.07:39:02.41#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.252.07:39:02.41#ibcon#[27=AT06-04\r\n] 2006.252.07:39:02.41#ibcon#*before write, iclass 7, count 2 2006.252.07:39:02.41#ibcon#enter sib2, iclass 7, count 2 2006.252.07:39:02.41#ibcon#flushed, iclass 7, count 2 2006.252.07:39:02.41#ibcon#about to write, iclass 7, count 2 2006.252.07:39:02.41#ibcon#wrote, iclass 7, count 2 2006.252.07:39:02.41#ibcon#about to read 3, iclass 7, count 2 2006.252.07:39:02.44#ibcon#read 3, iclass 7, count 2 2006.252.07:39:02.44#ibcon#about to read 4, iclass 7, count 2 2006.252.07:39:02.44#ibcon#read 4, iclass 7, count 2 2006.252.07:39:02.44#ibcon#about to read 5, iclass 7, count 2 2006.252.07:39:02.44#ibcon#read 5, iclass 7, count 2 2006.252.07:39:02.44#ibcon#about to read 6, iclass 7, count 2 2006.252.07:39:02.44#ibcon#read 6, iclass 7, count 2 2006.252.07:39:02.44#ibcon#end of sib2, iclass 7, count 2 2006.252.07:39:02.44#ibcon#*after write, iclass 7, count 2 2006.252.07:39:02.44#ibcon#*before return 0, iclass 7, count 2 2006.252.07:39:02.44#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.252.07:39:02.44#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.252.07:39:02.44#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.252.07:39:02.44#ibcon#ireg 7 cls_cnt 0 2006.252.07:39:02.44#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.252.07:39:02.56#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.252.07:39:02.56#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.252.07:39:02.56#ibcon#enter wrdev, iclass 7, count 0 2006.252.07:39:02.56#ibcon#first serial, iclass 7, count 0 2006.252.07:39:02.56#ibcon#enter sib2, iclass 7, count 0 2006.252.07:39:02.56#ibcon#flushed, iclass 7, count 0 2006.252.07:39:02.56#ibcon#about to write, iclass 7, count 0 2006.252.07:39:02.56#ibcon#wrote, iclass 7, count 0 2006.252.07:39:02.56#ibcon#about to read 3, iclass 7, count 0 2006.252.07:39:02.58#ibcon#read 3, iclass 7, count 0 2006.252.07:39:02.58#ibcon#about to read 4, iclass 7, count 0 2006.252.07:39:02.58#ibcon#read 4, iclass 7, count 0 2006.252.07:39:02.58#ibcon#about to read 5, iclass 7, count 0 2006.252.07:39:02.58#ibcon#read 5, iclass 7, count 0 2006.252.07:39:02.58#ibcon#about to read 6, iclass 7, count 0 2006.252.07:39:02.58#ibcon#read 6, iclass 7, count 0 2006.252.07:39:02.58#ibcon#end of sib2, iclass 7, count 0 2006.252.07:39:02.58#ibcon#*mode == 0, iclass 7, count 0 2006.252.07:39:02.58#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.252.07:39:02.58#ibcon#[27=USB\r\n] 2006.252.07:39:02.58#ibcon#*before write, iclass 7, count 0 2006.252.07:39:02.58#ibcon#enter sib2, iclass 7, count 0 2006.252.07:39:02.58#ibcon#flushed, iclass 7, count 0 2006.252.07:39:02.58#ibcon#about to write, iclass 7, count 0 2006.252.07:39:02.58#ibcon#wrote, iclass 7, count 0 2006.252.07:39:02.58#ibcon#about to read 3, iclass 7, count 0 2006.252.07:39:02.61#ibcon#read 3, iclass 7, count 0 2006.252.07:39:02.61#ibcon#about to read 4, iclass 7, count 0 2006.252.07:39:02.61#ibcon#read 4, iclass 7, count 0 2006.252.07:39:02.61#ibcon#about to read 5, iclass 7, count 0 2006.252.07:39:02.61#ibcon#read 5, iclass 7, count 0 2006.252.07:39:02.61#ibcon#about to read 6, iclass 7, count 0 2006.252.07:39:02.61#ibcon#read 6, iclass 7, count 0 2006.252.07:39:02.61#ibcon#end of sib2, iclass 7, count 0 2006.252.07:39:02.61#ibcon#*after write, iclass 7, count 0 2006.252.07:39:02.61#ibcon#*before return 0, iclass 7, count 0 2006.252.07:39:02.61#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.252.07:39:02.61#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.252.07:39:02.61#ibcon#about to clear, iclass 7 cls_cnt 0 2006.252.07:39:02.61#ibcon#cleared, iclass 7 cls_cnt 0 2006.252.07:39:02.61$vc4f8/vabw=wide 2006.252.07:39:02.61#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.252.07:39:02.61#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.252.07:39:02.61#ibcon#ireg 8 cls_cnt 0 2006.252.07:39:02.61#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.252.07:39:02.61#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.252.07:39:02.61#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.252.07:39:02.61#ibcon#enter wrdev, iclass 11, count 0 2006.252.07:39:02.61#ibcon#first serial, iclass 11, count 0 2006.252.07:39:02.61#ibcon#enter sib2, iclass 11, count 0 2006.252.07:39:02.62#ibcon#flushed, iclass 11, count 0 2006.252.07:39:02.62#ibcon#about to write, iclass 11, count 0 2006.252.07:39:02.62#ibcon#wrote, iclass 11, count 0 2006.252.07:39:02.62#ibcon#about to read 3, iclass 11, count 0 2006.252.07:39:02.63#ibcon#read 3, iclass 11, count 0 2006.252.07:39:02.63#ibcon#about to read 4, iclass 11, count 0 2006.252.07:39:02.63#ibcon#read 4, iclass 11, count 0 2006.252.07:39:02.63#ibcon#about to read 5, iclass 11, count 0 2006.252.07:39:02.63#ibcon#read 5, iclass 11, count 0 2006.252.07:39:02.63#ibcon#about to read 6, iclass 11, count 0 2006.252.07:39:02.63#ibcon#read 6, iclass 11, count 0 2006.252.07:39:02.63#ibcon#end of sib2, iclass 11, count 0 2006.252.07:39:02.63#ibcon#*mode == 0, iclass 11, count 0 2006.252.07:39:02.63#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.252.07:39:02.63#ibcon#[25=BW32\r\n] 2006.252.07:39:02.63#ibcon#*before write, iclass 11, count 0 2006.252.07:39:02.63#ibcon#enter sib2, iclass 11, count 0 2006.252.07:39:02.63#ibcon#flushed, iclass 11, count 0 2006.252.07:39:02.63#ibcon#about to write, iclass 11, count 0 2006.252.07:39:02.63#ibcon#wrote, iclass 11, count 0 2006.252.07:39:02.63#ibcon#about to read 3, iclass 11, count 0 2006.252.07:39:02.66#ibcon#read 3, iclass 11, count 0 2006.252.07:39:02.66#ibcon#about to read 4, iclass 11, count 0 2006.252.07:39:02.66#ibcon#read 4, iclass 11, count 0 2006.252.07:39:02.66#ibcon#about to read 5, iclass 11, count 0 2006.252.07:39:02.66#ibcon#read 5, iclass 11, count 0 2006.252.07:39:02.66#ibcon#about to read 6, iclass 11, count 0 2006.252.07:39:02.66#ibcon#read 6, iclass 11, count 0 2006.252.07:39:02.66#ibcon#end of sib2, iclass 11, count 0 2006.252.07:39:02.66#ibcon#*after write, iclass 11, count 0 2006.252.07:39:02.66#ibcon#*before return 0, iclass 11, count 0 2006.252.07:39:02.66#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.252.07:39:02.66#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.252.07:39:02.66#ibcon#about to clear, iclass 11 cls_cnt 0 2006.252.07:39:02.66#ibcon#cleared, iclass 11 cls_cnt 0 2006.252.07:39:02.66$vc4f8/vbbw=wide 2006.252.07:39:02.66#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.252.07:39:02.66#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.252.07:39:02.66#ibcon#ireg 8 cls_cnt 0 2006.252.07:39:02.66#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.252.07:39:02.73#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.252.07:39:02.73#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.252.07:39:02.73#ibcon#enter wrdev, iclass 13, count 0 2006.252.07:39:02.73#ibcon#first serial, iclass 13, count 0 2006.252.07:39:02.73#ibcon#enter sib2, iclass 13, count 0 2006.252.07:39:02.73#ibcon#flushed, iclass 13, count 0 2006.252.07:39:02.73#ibcon#about to write, iclass 13, count 0 2006.252.07:39:02.73#ibcon#wrote, iclass 13, count 0 2006.252.07:39:02.73#ibcon#about to read 3, iclass 13, count 0 2006.252.07:39:02.75#ibcon#read 3, iclass 13, count 0 2006.252.07:39:02.75#ibcon#about to read 4, iclass 13, count 0 2006.252.07:39:02.75#ibcon#read 4, iclass 13, count 0 2006.252.07:39:02.75#ibcon#about to read 5, iclass 13, count 0 2006.252.07:39:02.75#ibcon#read 5, iclass 13, count 0 2006.252.07:39:02.75#ibcon#about to read 6, iclass 13, count 0 2006.252.07:39:02.75#ibcon#read 6, iclass 13, count 0 2006.252.07:39:02.75#ibcon#end of sib2, iclass 13, count 0 2006.252.07:39:02.75#ibcon#*mode == 0, iclass 13, count 0 2006.252.07:39:02.75#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.252.07:39:02.75#ibcon#[27=BW32\r\n] 2006.252.07:39:02.75#ibcon#*before write, iclass 13, count 0 2006.252.07:39:02.75#ibcon#enter sib2, iclass 13, count 0 2006.252.07:39:02.75#ibcon#flushed, iclass 13, count 0 2006.252.07:39:02.75#ibcon#about to write, iclass 13, count 0 2006.252.07:39:02.75#ibcon#wrote, iclass 13, count 0 2006.252.07:39:02.75#ibcon#about to read 3, iclass 13, count 0 2006.252.07:39:02.78#ibcon#read 3, iclass 13, count 0 2006.252.07:39:02.78#ibcon#about to read 4, iclass 13, count 0 2006.252.07:39:02.78#ibcon#read 4, iclass 13, count 0 2006.252.07:39:02.78#ibcon#about to read 5, iclass 13, count 0 2006.252.07:39:02.78#ibcon#read 5, iclass 13, count 0 2006.252.07:39:02.78#ibcon#about to read 6, iclass 13, count 0 2006.252.07:39:02.78#ibcon#read 6, iclass 13, count 0 2006.252.07:39:02.78#ibcon#end of sib2, iclass 13, count 0 2006.252.07:39:02.78#ibcon#*after write, iclass 13, count 0 2006.252.07:39:02.78#ibcon#*before return 0, iclass 13, count 0 2006.252.07:39:02.78#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.252.07:39:02.78#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.252.07:39:02.78#ibcon#about to clear, iclass 13 cls_cnt 0 2006.252.07:39:02.78#ibcon#cleared, iclass 13 cls_cnt 0 2006.252.07:39:02.78$4f8m12a/ifd4f 2006.252.07:39:02.79$ifd4f/lo= 2006.252.07:39:02.79$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.252.07:39:02.79$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.252.07:39:02.79$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.252.07:39:02.79$ifd4f/patch= 2006.252.07:39:02.79$ifd4f/patch=lo1,a1,a2,a3,a4 2006.252.07:39:02.79$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.252.07:39:02.79$ifd4f/patch=lo3,a5,a6,a7,a8 2006.252.07:39:02.79$4f8m12a/"form=m,16.000,1:2 2006.252.07:39:02.79$4f8m12a/"tpicd 2006.252.07:39:02.79$4f8m12a/echo=off 2006.252.07:39:02.79$4f8m12a/xlog=off 2006.252.07:39:02.79:!2006.252.07:39:30 2006.252.07:39:16.14#trakl#Source acquired 2006.252.07:39:18.14#flagr#flagr/antenna,acquired 2006.252.07:39:30.01:preob 2006.252.07:39:31.14/onsource/TRACKING 2006.252.07:39:31.14:!2006.252.07:39:40 2006.252.07:39:40.01:data_valid=on 2006.252.07:39:40.02:midob 2006.252.07:39:41.14/onsource/TRACKING 2006.252.07:39:41.15/wx/27.44,1011.3,90 2006.252.07:39:41.19/cable/+6.4097E-03 2006.252.07:39:42.29/va/01,08,usb,yes,32,34 2006.252.07:39:42.29/va/02,07,usb,yes,32,34 2006.252.07:39:42.29/va/03,06,usb,yes,34,34 2006.252.07:39:42.29/va/04,07,usb,yes,33,35 2006.252.07:39:42.29/va/05,07,usb,yes,35,38 2006.252.07:39:42.29/va/06,07,usb,yes,31,31 2006.252.07:39:42.29/va/07,07,usb,yes,30,30 2006.252.07:39:42.29/va/08,07,usb,yes,33,33 2006.252.07:39:42.52/valo/01,532.99,yes,locked 2006.252.07:39:42.52/valo/02,572.99,yes,locked 2006.252.07:39:42.52/valo/03,672.99,yes,locked 2006.252.07:39:42.52/valo/04,832.99,yes,locked 2006.252.07:39:42.52/valo/05,652.99,yes,locked 2006.252.07:39:42.52/valo/06,772.99,yes,locked 2006.252.07:39:42.52/valo/07,832.99,yes,locked 2006.252.07:39:42.52/valo/08,852.99,yes,locked 2006.252.07:39:43.61/vb/01,04,usb,yes,30,29 2006.252.07:39:43.61/vb/02,05,usb,yes,28,29 2006.252.07:39:43.61/vb/03,04,usb,yes,28,32 2006.252.07:39:43.61/vb/04,04,usb,yes,29,29 2006.252.07:39:43.61/vb/05,04,usb,yes,28,32 2006.252.07:39:43.61/vb/06,04,usb,yes,28,31 2006.252.07:39:43.61/vb/07,04,usb,yes,31,31 2006.252.07:39:43.61/vb/08,04,usb,yes,28,32 2006.252.07:39:43.85/vblo/01,632.99,yes,locked 2006.252.07:39:43.85/vblo/02,640.99,yes,locked 2006.252.07:39:43.85/vblo/03,656.99,yes,locked 2006.252.07:39:43.85/vblo/04,712.99,yes,locked 2006.252.07:39:43.85/vblo/05,744.99,yes,locked 2006.252.07:39:43.85/vblo/06,752.99,yes,locked 2006.252.07:39:43.85/vblo/07,734.99,yes,locked 2006.252.07:39:43.85/vblo/08,744.99,yes,locked 2006.252.07:39:44.00/vabw/8 2006.252.07:39:44.15/vbbw/8 2006.252.07:39:44.24/xfe/off,on,14.0 2006.252.07:39:44.62/ifatt/23,28,28,28 2006.252.07:39:45.07/fmout-gps/S +4.74E-07 2006.252.07:39:45.15:!2006.252.07:40:40 2006.252.07:40:40.01:data_valid=off 2006.252.07:40:40.02:postob 2006.252.07:40:40.10/cable/+6.4085E-03 2006.252.07:40:40.10/wx/27.44,1011.2,90 2006.252.07:40:41.07/fmout-gps/S +4.75E-07 2006.252.07:40:41.08:scan_name=252-0741,k06252,60 2006.252.07:40:41.08:source=1417+385,141946.61,382148.5,2000.0,ccw 2006.252.07:40:42.14#flagr#flagr/antenna,new-source 2006.252.07:40:42.15:checkk5 2006.252.07:40:42.53/chk_autoobs//k5ts1/ autoobs is running! 2006.252.07:40:42.91/chk_autoobs//k5ts2/ autoobs is running! 2006.252.07:40:43.29/chk_autoobs//k5ts3/ autoobs is running! 2006.252.07:40:43.67/chk_autoobs//k5ts4/ autoobs is running! 2006.252.07:40:44.04/chk_obsdata//k5ts1/T2520739??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.252.07:40:44.40/chk_obsdata//k5ts2/T2520739??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.252.07:40:44.78/chk_obsdata//k5ts3/T2520739??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.252.07:40:45.15/chk_obsdata//k5ts4/T2520739??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.252.07:40:45.84/k5log//k5ts1_log_newline 2006.252.07:40:46.53/k5log//k5ts2_log_newline 2006.252.07:40:47.22/k5log//k5ts3_log_newline 2006.252.07:40:47.91/k5log//k5ts4_log_newline 2006.252.07:40:47.93/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.252.07:40:47.93:4f8m12a=1 2006.252.07:40:47.93$4f8m12a/echo=on 2006.252.07:40:47.93$4f8m12a/pcalon 2006.252.07:40:47.93$pcalon/"no phase cal control is implemented here 2006.252.07:40:47.93$4f8m12a/"tpicd=stop 2006.252.07:40:47.93$4f8m12a/vc4f8 2006.252.07:40:47.93$vc4f8/valo=1,532.99 2006.252.07:40:47.94#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.252.07:40:47.94#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.252.07:40:47.94#ibcon#ireg 17 cls_cnt 0 2006.252.07:40:47.94#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.252.07:40:47.94#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.252.07:40:47.94#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.252.07:40:47.94#ibcon#enter wrdev, iclass 20, count 0 2006.252.07:40:47.94#ibcon#first serial, iclass 20, count 0 2006.252.07:40:47.94#ibcon#enter sib2, iclass 20, count 0 2006.252.07:40:47.94#ibcon#flushed, iclass 20, count 0 2006.252.07:40:47.94#ibcon#about to write, iclass 20, count 0 2006.252.07:40:47.94#ibcon#wrote, iclass 20, count 0 2006.252.07:40:47.94#ibcon#about to read 3, iclass 20, count 0 2006.252.07:40:47.98#ibcon#read 3, iclass 20, count 0 2006.252.07:40:47.98#ibcon#about to read 4, iclass 20, count 0 2006.252.07:40:47.98#ibcon#read 4, iclass 20, count 0 2006.252.07:40:47.98#ibcon#about to read 5, iclass 20, count 0 2006.252.07:40:47.98#ibcon#read 5, iclass 20, count 0 2006.252.07:40:47.98#ibcon#about to read 6, iclass 20, count 0 2006.252.07:40:47.98#ibcon#read 6, iclass 20, count 0 2006.252.07:40:47.98#ibcon#end of sib2, iclass 20, count 0 2006.252.07:40:47.98#ibcon#*mode == 0, iclass 20, count 0 2006.252.07:40:47.98#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.252.07:40:47.98#ibcon#[26=FRQ=01,532.99\r\n] 2006.252.07:40:47.98#ibcon#*before write, iclass 20, count 0 2006.252.07:40:47.98#ibcon#enter sib2, iclass 20, count 0 2006.252.07:40:47.98#ibcon#flushed, iclass 20, count 0 2006.252.07:40:47.98#ibcon#about to write, iclass 20, count 0 2006.252.07:40:47.98#ibcon#wrote, iclass 20, count 0 2006.252.07:40:47.98#ibcon#about to read 3, iclass 20, count 0 2006.252.07:40:48.02#ibcon#read 3, iclass 20, count 0 2006.252.07:40:48.02#ibcon#about to read 4, iclass 20, count 0 2006.252.07:40:48.02#ibcon#read 4, iclass 20, count 0 2006.252.07:40:48.02#ibcon#about to read 5, iclass 20, count 0 2006.252.07:40:48.02#ibcon#read 5, iclass 20, count 0 2006.252.07:40:48.02#ibcon#about to read 6, iclass 20, count 0 2006.252.07:40:48.02#ibcon#read 6, iclass 20, count 0 2006.252.07:40:48.02#ibcon#end of sib2, iclass 20, count 0 2006.252.07:40:48.02#ibcon#*after write, iclass 20, count 0 2006.252.07:40:48.02#ibcon#*before return 0, iclass 20, count 0 2006.252.07:40:48.02#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.252.07:40:48.02#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.252.07:40:48.02#ibcon#about to clear, iclass 20 cls_cnt 0 2006.252.07:40:48.02#ibcon#cleared, iclass 20 cls_cnt 0 2006.252.07:40:48.02$vc4f8/va=1,8 2006.252.07:40:48.02#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.252.07:40:48.02#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.252.07:40:48.02#ibcon#ireg 11 cls_cnt 2 2006.252.07:40:48.02#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.252.07:40:48.02#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.252.07:40:48.02#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.252.07:40:48.02#ibcon#enter wrdev, iclass 22, count 2 2006.252.07:40:48.02#ibcon#first serial, iclass 22, count 2 2006.252.07:40:48.02#ibcon#enter sib2, iclass 22, count 2 2006.252.07:40:48.02#ibcon#flushed, iclass 22, count 2 2006.252.07:40:48.02#ibcon#about to write, iclass 22, count 2 2006.252.07:40:48.02#ibcon#wrote, iclass 22, count 2 2006.252.07:40:48.02#ibcon#about to read 3, iclass 22, count 2 2006.252.07:40:48.05#ibcon#read 3, iclass 22, count 2 2006.252.07:40:48.05#ibcon#about to read 4, iclass 22, count 2 2006.252.07:40:48.05#ibcon#read 4, iclass 22, count 2 2006.252.07:40:48.05#ibcon#about to read 5, iclass 22, count 2 2006.252.07:40:48.05#ibcon#read 5, iclass 22, count 2 2006.252.07:40:48.05#ibcon#about to read 6, iclass 22, count 2 2006.252.07:40:48.05#ibcon#read 6, iclass 22, count 2 2006.252.07:40:48.05#ibcon#end of sib2, iclass 22, count 2 2006.252.07:40:48.05#ibcon#*mode == 0, iclass 22, count 2 2006.252.07:40:48.05#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.252.07:40:48.05#ibcon#[25=AT01-08\r\n] 2006.252.07:40:48.05#ibcon#*before write, iclass 22, count 2 2006.252.07:40:48.05#ibcon#enter sib2, iclass 22, count 2 2006.252.07:40:48.05#ibcon#flushed, iclass 22, count 2 2006.252.07:40:48.05#ibcon#about to write, iclass 22, count 2 2006.252.07:40:48.05#ibcon#wrote, iclass 22, count 2 2006.252.07:40:48.05#ibcon#about to read 3, iclass 22, count 2 2006.252.07:40:48.08#ibcon#read 3, iclass 22, count 2 2006.252.07:40:48.08#ibcon#about to read 4, iclass 22, count 2 2006.252.07:40:48.08#ibcon#read 4, iclass 22, count 2 2006.252.07:40:48.08#ibcon#about to read 5, iclass 22, count 2 2006.252.07:40:48.08#ibcon#read 5, iclass 22, count 2 2006.252.07:40:48.08#ibcon#about to read 6, iclass 22, count 2 2006.252.07:40:48.08#ibcon#read 6, iclass 22, count 2 2006.252.07:40:48.08#ibcon#end of sib2, iclass 22, count 2 2006.252.07:40:48.08#ibcon#*after write, iclass 22, count 2 2006.252.07:40:48.08#ibcon#*before return 0, iclass 22, count 2 2006.252.07:40:48.08#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.252.07:40:48.08#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.252.07:40:48.08#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.252.07:40:48.08#ibcon#ireg 7 cls_cnt 0 2006.252.07:40:48.08#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.252.07:40:48.20#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.252.07:40:48.20#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.252.07:40:48.20#ibcon#enter wrdev, iclass 22, count 0 2006.252.07:40:48.20#ibcon#first serial, iclass 22, count 0 2006.252.07:40:48.20#ibcon#enter sib2, iclass 22, count 0 2006.252.07:40:48.20#ibcon#flushed, iclass 22, count 0 2006.252.07:40:48.20#ibcon#about to write, iclass 22, count 0 2006.252.07:40:48.20#ibcon#wrote, iclass 22, count 0 2006.252.07:40:48.20#ibcon#about to read 3, iclass 22, count 0 2006.252.07:40:48.22#ibcon#read 3, iclass 22, count 0 2006.252.07:40:48.22#ibcon#about to read 4, iclass 22, count 0 2006.252.07:40:48.22#ibcon#read 4, iclass 22, count 0 2006.252.07:40:48.22#ibcon#about to read 5, iclass 22, count 0 2006.252.07:40:48.22#ibcon#read 5, iclass 22, count 0 2006.252.07:40:48.22#ibcon#about to read 6, iclass 22, count 0 2006.252.07:40:48.22#ibcon#read 6, iclass 22, count 0 2006.252.07:40:48.22#ibcon#end of sib2, iclass 22, count 0 2006.252.07:40:48.22#ibcon#*mode == 0, iclass 22, count 0 2006.252.07:40:48.22#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.252.07:40:48.22#ibcon#[25=USB\r\n] 2006.252.07:40:48.22#ibcon#*before write, iclass 22, count 0 2006.252.07:40:48.22#ibcon#enter sib2, iclass 22, count 0 2006.252.07:40:48.22#ibcon#flushed, iclass 22, count 0 2006.252.07:40:48.22#ibcon#about to write, iclass 22, count 0 2006.252.07:40:48.22#ibcon#wrote, iclass 22, count 0 2006.252.07:40:48.22#ibcon#about to read 3, iclass 22, count 0 2006.252.07:40:48.25#ibcon#read 3, iclass 22, count 0 2006.252.07:40:48.25#ibcon#about to read 4, iclass 22, count 0 2006.252.07:40:48.25#ibcon#read 4, iclass 22, count 0 2006.252.07:40:48.25#ibcon#about to read 5, iclass 22, count 0 2006.252.07:40:48.25#ibcon#read 5, iclass 22, count 0 2006.252.07:40:48.25#ibcon#about to read 6, iclass 22, count 0 2006.252.07:40:48.25#ibcon#read 6, iclass 22, count 0 2006.252.07:40:48.25#ibcon#end of sib2, iclass 22, count 0 2006.252.07:40:48.25#ibcon#*after write, iclass 22, count 0 2006.252.07:40:48.25#ibcon#*before return 0, iclass 22, count 0 2006.252.07:40:48.25#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.252.07:40:48.25#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.252.07:40:48.25#ibcon#about to clear, iclass 22 cls_cnt 0 2006.252.07:40:48.25#ibcon#cleared, iclass 22 cls_cnt 0 2006.252.07:40:48.25$vc4f8/valo=2,572.99 2006.252.07:40:48.25#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.252.07:40:48.25#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.252.07:40:48.25#ibcon#ireg 17 cls_cnt 0 2006.252.07:40:48.25#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.252.07:40:48.25#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.252.07:40:48.25#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.252.07:40:48.25#ibcon#enter wrdev, iclass 24, count 0 2006.252.07:40:48.25#ibcon#first serial, iclass 24, count 0 2006.252.07:40:48.25#ibcon#enter sib2, iclass 24, count 0 2006.252.07:40:48.25#ibcon#flushed, iclass 24, count 0 2006.252.07:40:48.25#ibcon#about to write, iclass 24, count 0 2006.252.07:40:48.25#ibcon#wrote, iclass 24, count 0 2006.252.07:40:48.25#ibcon#about to read 3, iclass 24, count 0 2006.252.07:40:48.27#ibcon#read 3, iclass 24, count 0 2006.252.07:40:48.27#ibcon#about to read 4, iclass 24, count 0 2006.252.07:40:48.27#ibcon#read 4, iclass 24, count 0 2006.252.07:40:48.27#ibcon#about to read 5, iclass 24, count 0 2006.252.07:40:48.27#ibcon#read 5, iclass 24, count 0 2006.252.07:40:48.27#ibcon#about to read 6, iclass 24, count 0 2006.252.07:40:48.27#ibcon#read 6, iclass 24, count 0 2006.252.07:40:48.27#ibcon#end of sib2, iclass 24, count 0 2006.252.07:40:48.27#ibcon#*mode == 0, iclass 24, count 0 2006.252.07:40:48.27#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.252.07:40:48.27#ibcon#[26=FRQ=02,572.99\r\n] 2006.252.07:40:48.27#ibcon#*before write, iclass 24, count 0 2006.252.07:40:48.27#ibcon#enter sib2, iclass 24, count 0 2006.252.07:40:48.27#ibcon#flushed, iclass 24, count 0 2006.252.07:40:48.27#ibcon#about to write, iclass 24, count 0 2006.252.07:40:48.27#ibcon#wrote, iclass 24, count 0 2006.252.07:40:48.27#ibcon#about to read 3, iclass 24, count 0 2006.252.07:40:48.31#ibcon#read 3, iclass 24, count 0 2006.252.07:40:48.31#ibcon#about to read 4, iclass 24, count 0 2006.252.07:40:48.31#ibcon#read 4, iclass 24, count 0 2006.252.07:40:48.31#ibcon#about to read 5, iclass 24, count 0 2006.252.07:40:48.31#ibcon#read 5, iclass 24, count 0 2006.252.07:40:48.31#ibcon#about to read 6, iclass 24, count 0 2006.252.07:40:48.31#ibcon#read 6, iclass 24, count 0 2006.252.07:40:48.31#ibcon#end of sib2, iclass 24, count 0 2006.252.07:40:48.31#ibcon#*after write, iclass 24, count 0 2006.252.07:40:48.31#ibcon#*before return 0, iclass 24, count 0 2006.252.07:40:48.31#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.252.07:40:48.31#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.252.07:40:48.31#ibcon#about to clear, iclass 24 cls_cnt 0 2006.252.07:40:48.31#ibcon#cleared, iclass 24 cls_cnt 0 2006.252.07:40:48.31$vc4f8/va=2,7 2006.252.07:40:48.31#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.252.07:40:48.31#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.252.07:40:48.31#ibcon#ireg 11 cls_cnt 2 2006.252.07:40:48.31#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.252.07:40:48.37#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.252.07:40:48.37#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.252.07:40:48.37#ibcon#enter wrdev, iclass 26, count 2 2006.252.07:40:48.37#ibcon#first serial, iclass 26, count 2 2006.252.07:40:48.37#ibcon#enter sib2, iclass 26, count 2 2006.252.07:40:48.37#ibcon#flushed, iclass 26, count 2 2006.252.07:40:48.37#ibcon#about to write, iclass 26, count 2 2006.252.07:40:48.37#ibcon#wrote, iclass 26, count 2 2006.252.07:40:48.37#ibcon#about to read 3, iclass 26, count 2 2006.252.07:40:48.39#ibcon#read 3, iclass 26, count 2 2006.252.07:40:48.39#ibcon#about to read 4, iclass 26, count 2 2006.252.07:40:48.39#ibcon#read 4, iclass 26, count 2 2006.252.07:40:48.39#ibcon#about to read 5, iclass 26, count 2 2006.252.07:40:48.39#ibcon#read 5, iclass 26, count 2 2006.252.07:40:48.39#ibcon#about to read 6, iclass 26, count 2 2006.252.07:40:48.39#ibcon#read 6, iclass 26, count 2 2006.252.07:40:48.39#ibcon#end of sib2, iclass 26, count 2 2006.252.07:40:48.39#ibcon#*mode == 0, iclass 26, count 2 2006.252.07:40:48.39#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.252.07:40:48.39#ibcon#[25=AT02-07\r\n] 2006.252.07:40:48.39#ibcon#*before write, iclass 26, count 2 2006.252.07:40:48.39#ibcon#enter sib2, iclass 26, count 2 2006.252.07:40:48.39#ibcon#flushed, iclass 26, count 2 2006.252.07:40:48.39#ibcon#about to write, iclass 26, count 2 2006.252.07:40:48.39#ibcon#wrote, iclass 26, count 2 2006.252.07:40:48.39#ibcon#about to read 3, iclass 26, count 2 2006.252.07:40:48.42#ibcon#read 3, iclass 26, count 2 2006.252.07:40:48.42#ibcon#about to read 4, iclass 26, count 2 2006.252.07:40:48.42#ibcon#read 4, iclass 26, count 2 2006.252.07:40:48.42#ibcon#about to read 5, iclass 26, count 2 2006.252.07:40:48.42#ibcon#read 5, iclass 26, count 2 2006.252.07:40:48.42#ibcon#about to read 6, iclass 26, count 2 2006.252.07:40:48.42#ibcon#read 6, iclass 26, count 2 2006.252.07:40:48.42#ibcon#end of sib2, iclass 26, count 2 2006.252.07:40:48.42#ibcon#*after write, iclass 26, count 2 2006.252.07:40:48.42#ibcon#*before return 0, iclass 26, count 2 2006.252.07:40:48.42#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.252.07:40:48.42#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.252.07:40:48.42#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.252.07:40:48.42#ibcon#ireg 7 cls_cnt 0 2006.252.07:40:48.42#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.252.07:40:48.55#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.252.07:40:48.55#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.252.07:40:48.55#ibcon#enter wrdev, iclass 26, count 0 2006.252.07:40:48.55#ibcon#first serial, iclass 26, count 0 2006.252.07:40:48.55#ibcon#enter sib2, iclass 26, count 0 2006.252.07:40:48.55#ibcon#flushed, iclass 26, count 0 2006.252.07:40:48.55#ibcon#about to write, iclass 26, count 0 2006.252.07:40:48.55#ibcon#wrote, iclass 26, count 0 2006.252.07:40:48.55#ibcon#about to read 3, iclass 26, count 0 2006.252.07:40:48.56#ibcon#read 3, iclass 26, count 0 2006.252.07:40:48.56#ibcon#about to read 4, iclass 26, count 0 2006.252.07:40:48.56#ibcon#read 4, iclass 26, count 0 2006.252.07:40:48.56#ibcon#about to read 5, iclass 26, count 0 2006.252.07:40:48.56#ibcon#read 5, iclass 26, count 0 2006.252.07:40:48.56#ibcon#about to read 6, iclass 26, count 0 2006.252.07:40:48.56#ibcon#read 6, iclass 26, count 0 2006.252.07:40:48.56#ibcon#end of sib2, iclass 26, count 0 2006.252.07:40:48.56#ibcon#*mode == 0, iclass 26, count 0 2006.252.07:40:48.56#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.252.07:40:48.56#ibcon#[25=USB\r\n] 2006.252.07:40:48.56#ibcon#*before write, iclass 26, count 0 2006.252.07:40:48.56#ibcon#enter sib2, iclass 26, count 0 2006.252.07:40:48.56#ibcon#flushed, iclass 26, count 0 2006.252.07:40:48.56#ibcon#about to write, iclass 26, count 0 2006.252.07:40:48.56#ibcon#wrote, iclass 26, count 0 2006.252.07:40:48.56#ibcon#about to read 3, iclass 26, count 0 2006.252.07:40:48.59#ibcon#read 3, iclass 26, count 0 2006.252.07:40:48.59#ibcon#about to read 4, iclass 26, count 0 2006.252.07:40:48.59#ibcon#read 4, iclass 26, count 0 2006.252.07:40:48.59#ibcon#about to read 5, iclass 26, count 0 2006.252.07:40:48.59#ibcon#read 5, iclass 26, count 0 2006.252.07:40:48.59#ibcon#about to read 6, iclass 26, count 0 2006.252.07:40:48.59#ibcon#read 6, iclass 26, count 0 2006.252.07:40:48.59#ibcon#end of sib2, iclass 26, count 0 2006.252.07:40:48.59#ibcon#*after write, iclass 26, count 0 2006.252.07:40:48.59#ibcon#*before return 0, iclass 26, count 0 2006.252.07:40:48.59#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.252.07:40:48.59#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.252.07:40:48.59#ibcon#about to clear, iclass 26 cls_cnt 0 2006.252.07:40:48.59#ibcon#cleared, iclass 26 cls_cnt 0 2006.252.07:40:48.59$vc4f8/valo=3,672.99 2006.252.07:40:48.59#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.252.07:40:48.59#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.252.07:40:48.59#ibcon#ireg 17 cls_cnt 0 2006.252.07:40:48.59#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.252.07:40:48.59#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.252.07:40:48.59#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.252.07:40:48.59#ibcon#enter wrdev, iclass 28, count 0 2006.252.07:40:48.59#ibcon#first serial, iclass 28, count 0 2006.252.07:40:48.59#ibcon#enter sib2, iclass 28, count 0 2006.252.07:40:48.59#ibcon#flushed, iclass 28, count 0 2006.252.07:40:48.59#ibcon#about to write, iclass 28, count 0 2006.252.07:40:48.59#ibcon#wrote, iclass 28, count 0 2006.252.07:40:48.59#ibcon#about to read 3, iclass 28, count 0 2006.252.07:40:48.62#ibcon#read 3, iclass 28, count 0 2006.252.07:40:48.62#ibcon#about to read 4, iclass 28, count 0 2006.252.07:40:48.62#ibcon#read 4, iclass 28, count 0 2006.252.07:40:48.62#ibcon#about to read 5, iclass 28, count 0 2006.252.07:40:48.62#ibcon#read 5, iclass 28, count 0 2006.252.07:40:48.62#ibcon#about to read 6, iclass 28, count 0 2006.252.07:40:48.62#ibcon#read 6, iclass 28, count 0 2006.252.07:40:48.62#ibcon#end of sib2, iclass 28, count 0 2006.252.07:40:48.62#ibcon#*mode == 0, iclass 28, count 0 2006.252.07:40:48.62#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.252.07:40:48.62#ibcon#[26=FRQ=03,672.99\r\n] 2006.252.07:40:48.62#ibcon#*before write, iclass 28, count 0 2006.252.07:40:48.62#ibcon#enter sib2, iclass 28, count 0 2006.252.07:40:48.62#ibcon#flushed, iclass 28, count 0 2006.252.07:40:48.62#ibcon#about to write, iclass 28, count 0 2006.252.07:40:48.62#ibcon#wrote, iclass 28, count 0 2006.252.07:40:48.62#ibcon#about to read 3, iclass 28, count 0 2006.252.07:40:48.66#ibcon#read 3, iclass 28, count 0 2006.252.07:40:48.66#ibcon#about to read 4, iclass 28, count 0 2006.252.07:40:48.66#ibcon#read 4, iclass 28, count 0 2006.252.07:40:48.66#ibcon#about to read 5, iclass 28, count 0 2006.252.07:40:48.66#ibcon#read 5, iclass 28, count 0 2006.252.07:40:48.66#ibcon#about to read 6, iclass 28, count 0 2006.252.07:40:48.66#ibcon#read 6, iclass 28, count 0 2006.252.07:40:48.66#ibcon#end of sib2, iclass 28, count 0 2006.252.07:40:48.66#ibcon#*after write, iclass 28, count 0 2006.252.07:40:48.66#ibcon#*before return 0, iclass 28, count 0 2006.252.07:40:48.66#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.252.07:40:48.66#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.252.07:40:48.66#ibcon#about to clear, iclass 28 cls_cnt 0 2006.252.07:40:48.66#ibcon#cleared, iclass 28 cls_cnt 0 2006.252.07:40:48.66$vc4f8/va=3,6 2006.252.07:40:48.66#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.252.07:40:48.66#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.252.07:40:48.66#ibcon#ireg 11 cls_cnt 2 2006.252.07:40:48.66#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.252.07:40:48.72#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.252.07:40:48.72#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.252.07:40:48.72#ibcon#enter wrdev, iclass 30, count 2 2006.252.07:40:48.72#ibcon#first serial, iclass 30, count 2 2006.252.07:40:48.72#ibcon#enter sib2, iclass 30, count 2 2006.252.07:40:48.72#ibcon#flushed, iclass 30, count 2 2006.252.07:40:48.72#ibcon#about to write, iclass 30, count 2 2006.252.07:40:48.72#ibcon#wrote, iclass 30, count 2 2006.252.07:40:48.72#ibcon#about to read 3, iclass 30, count 2 2006.252.07:40:48.73#ibcon#read 3, iclass 30, count 2 2006.252.07:40:48.73#ibcon#about to read 4, iclass 30, count 2 2006.252.07:40:48.73#ibcon#read 4, iclass 30, count 2 2006.252.07:40:48.73#ibcon#about to read 5, iclass 30, count 2 2006.252.07:40:48.73#ibcon#read 5, iclass 30, count 2 2006.252.07:40:48.73#ibcon#about to read 6, iclass 30, count 2 2006.252.07:40:48.73#ibcon#read 6, iclass 30, count 2 2006.252.07:40:48.73#ibcon#end of sib2, iclass 30, count 2 2006.252.07:40:48.73#ibcon#*mode == 0, iclass 30, count 2 2006.252.07:40:48.73#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.252.07:40:48.73#ibcon#[25=AT03-06\r\n] 2006.252.07:40:48.73#ibcon#*before write, iclass 30, count 2 2006.252.07:40:48.73#ibcon#enter sib2, iclass 30, count 2 2006.252.07:40:48.73#ibcon#flushed, iclass 30, count 2 2006.252.07:40:48.73#ibcon#about to write, iclass 30, count 2 2006.252.07:40:48.73#ibcon#wrote, iclass 30, count 2 2006.252.07:40:48.73#ibcon#about to read 3, iclass 30, count 2 2006.252.07:40:48.76#ibcon#read 3, iclass 30, count 2 2006.252.07:40:48.76#ibcon#about to read 4, iclass 30, count 2 2006.252.07:40:48.76#ibcon#read 4, iclass 30, count 2 2006.252.07:40:48.76#ibcon#about to read 5, iclass 30, count 2 2006.252.07:40:48.76#ibcon#read 5, iclass 30, count 2 2006.252.07:40:48.76#ibcon#about to read 6, iclass 30, count 2 2006.252.07:40:48.76#ibcon#read 6, iclass 30, count 2 2006.252.07:40:48.76#ibcon#end of sib2, iclass 30, count 2 2006.252.07:40:48.76#ibcon#*after write, iclass 30, count 2 2006.252.07:40:48.76#ibcon#*before return 0, iclass 30, count 2 2006.252.07:40:48.76#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.252.07:40:48.76#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.252.07:40:48.76#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.252.07:40:48.76#ibcon#ireg 7 cls_cnt 0 2006.252.07:40:48.76#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.252.07:40:48.88#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.252.07:40:48.88#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.252.07:40:48.88#ibcon#enter wrdev, iclass 30, count 0 2006.252.07:40:48.88#ibcon#first serial, iclass 30, count 0 2006.252.07:40:48.88#ibcon#enter sib2, iclass 30, count 0 2006.252.07:40:48.88#ibcon#flushed, iclass 30, count 0 2006.252.07:40:48.88#ibcon#about to write, iclass 30, count 0 2006.252.07:40:48.88#ibcon#wrote, iclass 30, count 0 2006.252.07:40:48.88#ibcon#about to read 3, iclass 30, count 0 2006.252.07:40:48.90#ibcon#read 3, iclass 30, count 0 2006.252.07:40:48.90#ibcon#about to read 4, iclass 30, count 0 2006.252.07:40:48.90#ibcon#read 4, iclass 30, count 0 2006.252.07:40:48.90#ibcon#about to read 5, iclass 30, count 0 2006.252.07:40:48.90#ibcon#read 5, iclass 30, count 0 2006.252.07:40:48.90#ibcon#about to read 6, iclass 30, count 0 2006.252.07:40:48.90#ibcon#read 6, iclass 30, count 0 2006.252.07:40:48.90#ibcon#end of sib2, iclass 30, count 0 2006.252.07:40:48.90#ibcon#*mode == 0, iclass 30, count 0 2006.252.07:40:48.90#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.252.07:40:48.90#ibcon#[25=USB\r\n] 2006.252.07:40:48.90#ibcon#*before write, iclass 30, count 0 2006.252.07:40:48.90#ibcon#enter sib2, iclass 30, count 0 2006.252.07:40:48.90#ibcon#flushed, iclass 30, count 0 2006.252.07:40:48.90#ibcon#about to write, iclass 30, count 0 2006.252.07:40:48.90#ibcon#wrote, iclass 30, count 0 2006.252.07:40:48.90#ibcon#about to read 3, iclass 30, count 0 2006.252.07:40:48.93#ibcon#read 3, iclass 30, count 0 2006.252.07:40:48.93#ibcon#about to read 4, iclass 30, count 0 2006.252.07:40:48.93#ibcon#read 4, iclass 30, count 0 2006.252.07:40:48.93#ibcon#about to read 5, iclass 30, count 0 2006.252.07:40:48.93#ibcon#read 5, iclass 30, count 0 2006.252.07:40:48.93#ibcon#about to read 6, iclass 30, count 0 2006.252.07:40:48.93#ibcon#read 6, iclass 30, count 0 2006.252.07:40:48.93#ibcon#end of sib2, iclass 30, count 0 2006.252.07:40:48.93#ibcon#*after write, iclass 30, count 0 2006.252.07:40:48.93#ibcon#*before return 0, iclass 30, count 0 2006.252.07:40:48.93#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.252.07:40:48.93#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.252.07:40:48.93#ibcon#about to clear, iclass 30 cls_cnt 0 2006.252.07:40:48.93#ibcon#cleared, iclass 30 cls_cnt 0 2006.252.07:40:48.93$vc4f8/valo=4,832.99 2006.252.07:40:48.93#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.252.07:40:48.93#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.252.07:40:48.93#ibcon#ireg 17 cls_cnt 0 2006.252.07:40:48.93#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.252.07:40:48.93#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.252.07:40:48.93#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.252.07:40:48.93#ibcon#enter wrdev, iclass 32, count 0 2006.252.07:40:48.93#ibcon#first serial, iclass 32, count 0 2006.252.07:40:48.93#ibcon#enter sib2, iclass 32, count 0 2006.252.07:40:48.93#ibcon#flushed, iclass 32, count 0 2006.252.07:40:48.93#ibcon#about to write, iclass 32, count 0 2006.252.07:40:48.93#ibcon#wrote, iclass 32, count 0 2006.252.07:40:48.93#ibcon#about to read 3, iclass 32, count 0 2006.252.07:40:48.95#ibcon#read 3, iclass 32, count 0 2006.252.07:40:48.95#ibcon#about to read 4, iclass 32, count 0 2006.252.07:40:48.95#ibcon#read 4, iclass 32, count 0 2006.252.07:40:48.95#ibcon#about to read 5, iclass 32, count 0 2006.252.07:40:48.95#ibcon#read 5, iclass 32, count 0 2006.252.07:40:48.95#ibcon#about to read 6, iclass 32, count 0 2006.252.07:40:48.95#ibcon#read 6, iclass 32, count 0 2006.252.07:40:48.95#ibcon#end of sib2, iclass 32, count 0 2006.252.07:40:48.95#ibcon#*mode == 0, iclass 32, count 0 2006.252.07:40:48.95#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.252.07:40:48.95#ibcon#[26=FRQ=04,832.99\r\n] 2006.252.07:40:48.95#ibcon#*before write, iclass 32, count 0 2006.252.07:40:48.95#ibcon#enter sib2, iclass 32, count 0 2006.252.07:40:48.95#ibcon#flushed, iclass 32, count 0 2006.252.07:40:48.95#ibcon#about to write, iclass 32, count 0 2006.252.07:40:48.95#ibcon#wrote, iclass 32, count 0 2006.252.07:40:48.95#ibcon#about to read 3, iclass 32, count 0 2006.252.07:40:48.99#ibcon#read 3, iclass 32, count 0 2006.252.07:40:48.99#ibcon#about to read 4, iclass 32, count 0 2006.252.07:40:48.99#ibcon#read 4, iclass 32, count 0 2006.252.07:40:48.99#ibcon#about to read 5, iclass 32, count 0 2006.252.07:40:48.99#ibcon#read 5, iclass 32, count 0 2006.252.07:40:48.99#ibcon#about to read 6, iclass 32, count 0 2006.252.07:40:48.99#ibcon#read 6, iclass 32, count 0 2006.252.07:40:48.99#ibcon#end of sib2, iclass 32, count 0 2006.252.07:40:48.99#ibcon#*after write, iclass 32, count 0 2006.252.07:40:48.99#ibcon#*before return 0, iclass 32, count 0 2006.252.07:40:48.99#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.252.07:40:48.99#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.252.07:40:48.99#ibcon#about to clear, iclass 32 cls_cnt 0 2006.252.07:40:48.99#ibcon#cleared, iclass 32 cls_cnt 0 2006.252.07:40:48.99$vc4f8/va=4,7 2006.252.07:40:48.99#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.252.07:40:48.99#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.252.07:40:48.99#ibcon#ireg 11 cls_cnt 2 2006.252.07:40:49.00#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.252.07:40:49.04#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.252.07:40:49.04#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.252.07:40:49.04#ibcon#enter wrdev, iclass 34, count 2 2006.252.07:40:49.04#ibcon#first serial, iclass 34, count 2 2006.252.07:40:49.04#ibcon#enter sib2, iclass 34, count 2 2006.252.07:40:49.04#ibcon#flushed, iclass 34, count 2 2006.252.07:40:49.04#ibcon#about to write, iclass 34, count 2 2006.252.07:40:49.04#ibcon#wrote, iclass 34, count 2 2006.252.07:40:49.04#ibcon#about to read 3, iclass 34, count 2 2006.252.07:40:49.06#ibcon#read 3, iclass 34, count 2 2006.252.07:40:49.06#ibcon#about to read 4, iclass 34, count 2 2006.252.07:40:49.06#ibcon#read 4, iclass 34, count 2 2006.252.07:40:49.06#ibcon#about to read 5, iclass 34, count 2 2006.252.07:40:49.06#ibcon#read 5, iclass 34, count 2 2006.252.07:40:49.06#ibcon#about to read 6, iclass 34, count 2 2006.252.07:40:49.06#ibcon#read 6, iclass 34, count 2 2006.252.07:40:49.06#ibcon#end of sib2, iclass 34, count 2 2006.252.07:40:49.06#ibcon#*mode == 0, iclass 34, count 2 2006.252.07:40:49.06#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.252.07:40:49.06#ibcon#[25=AT04-07\r\n] 2006.252.07:40:49.06#ibcon#*before write, iclass 34, count 2 2006.252.07:40:49.06#ibcon#enter sib2, iclass 34, count 2 2006.252.07:40:49.06#ibcon#flushed, iclass 34, count 2 2006.252.07:40:49.06#ibcon#about to write, iclass 34, count 2 2006.252.07:40:49.06#ibcon#wrote, iclass 34, count 2 2006.252.07:40:49.06#ibcon#about to read 3, iclass 34, count 2 2006.252.07:40:49.09#ibcon#read 3, iclass 34, count 2 2006.252.07:40:49.09#ibcon#about to read 4, iclass 34, count 2 2006.252.07:40:49.09#ibcon#read 4, iclass 34, count 2 2006.252.07:40:49.09#ibcon#about to read 5, iclass 34, count 2 2006.252.07:40:49.09#ibcon#read 5, iclass 34, count 2 2006.252.07:40:49.09#ibcon#about to read 6, iclass 34, count 2 2006.252.07:40:49.09#ibcon#read 6, iclass 34, count 2 2006.252.07:40:49.09#ibcon#end of sib2, iclass 34, count 2 2006.252.07:40:49.09#ibcon#*after write, iclass 34, count 2 2006.252.07:40:49.09#ibcon#*before return 0, iclass 34, count 2 2006.252.07:40:49.09#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.252.07:40:49.09#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.252.07:40:49.09#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.252.07:40:49.09#ibcon#ireg 7 cls_cnt 0 2006.252.07:40:49.09#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.252.07:40:49.21#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.252.07:40:49.21#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.252.07:40:49.21#ibcon#enter wrdev, iclass 34, count 0 2006.252.07:40:49.21#ibcon#first serial, iclass 34, count 0 2006.252.07:40:49.21#ibcon#enter sib2, iclass 34, count 0 2006.252.07:40:49.21#ibcon#flushed, iclass 34, count 0 2006.252.07:40:49.21#ibcon#about to write, iclass 34, count 0 2006.252.07:40:49.21#ibcon#wrote, iclass 34, count 0 2006.252.07:40:49.21#ibcon#about to read 3, iclass 34, count 0 2006.252.07:40:49.23#ibcon#read 3, iclass 34, count 0 2006.252.07:40:49.23#ibcon#about to read 4, iclass 34, count 0 2006.252.07:40:49.23#ibcon#read 4, iclass 34, count 0 2006.252.07:40:49.23#ibcon#about to read 5, iclass 34, count 0 2006.252.07:40:49.23#ibcon#read 5, iclass 34, count 0 2006.252.07:40:49.23#ibcon#about to read 6, iclass 34, count 0 2006.252.07:40:49.23#ibcon#read 6, iclass 34, count 0 2006.252.07:40:49.23#ibcon#end of sib2, iclass 34, count 0 2006.252.07:40:49.23#ibcon#*mode == 0, iclass 34, count 0 2006.252.07:40:49.23#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.252.07:40:49.23#ibcon#[25=USB\r\n] 2006.252.07:40:49.23#ibcon#*before write, iclass 34, count 0 2006.252.07:40:49.23#ibcon#enter sib2, iclass 34, count 0 2006.252.07:40:49.23#ibcon#flushed, iclass 34, count 0 2006.252.07:40:49.23#ibcon#about to write, iclass 34, count 0 2006.252.07:40:49.23#ibcon#wrote, iclass 34, count 0 2006.252.07:40:49.23#ibcon#about to read 3, iclass 34, count 0 2006.252.07:40:49.26#ibcon#read 3, iclass 34, count 0 2006.252.07:40:49.26#ibcon#about to read 4, iclass 34, count 0 2006.252.07:40:49.26#ibcon#read 4, iclass 34, count 0 2006.252.07:40:49.26#ibcon#about to read 5, iclass 34, count 0 2006.252.07:40:49.26#ibcon#read 5, iclass 34, count 0 2006.252.07:40:49.26#ibcon#about to read 6, iclass 34, count 0 2006.252.07:40:49.26#ibcon#read 6, iclass 34, count 0 2006.252.07:40:49.26#ibcon#end of sib2, iclass 34, count 0 2006.252.07:40:49.26#ibcon#*after write, iclass 34, count 0 2006.252.07:40:49.26#ibcon#*before return 0, iclass 34, count 0 2006.252.07:40:49.26#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.252.07:40:49.26#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.252.07:40:49.26#ibcon#about to clear, iclass 34 cls_cnt 0 2006.252.07:40:49.26#ibcon#cleared, iclass 34 cls_cnt 0 2006.252.07:40:49.26$vc4f8/valo=5,652.99 2006.252.07:40:49.26#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.252.07:40:49.26#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.252.07:40:49.26#ibcon#ireg 17 cls_cnt 0 2006.252.07:40:49.26#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.252.07:40:49.26#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.252.07:40:49.26#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.252.07:40:49.26#ibcon#enter wrdev, iclass 36, count 0 2006.252.07:40:49.26#ibcon#first serial, iclass 36, count 0 2006.252.07:40:49.26#ibcon#enter sib2, iclass 36, count 0 2006.252.07:40:49.26#ibcon#flushed, iclass 36, count 0 2006.252.07:40:49.26#ibcon#about to write, iclass 36, count 0 2006.252.07:40:49.26#ibcon#wrote, iclass 36, count 0 2006.252.07:40:49.26#ibcon#about to read 3, iclass 36, count 0 2006.252.07:40:49.28#ibcon#read 3, iclass 36, count 0 2006.252.07:40:49.28#ibcon#about to read 4, iclass 36, count 0 2006.252.07:40:49.28#ibcon#read 4, iclass 36, count 0 2006.252.07:40:49.28#ibcon#about to read 5, iclass 36, count 0 2006.252.07:40:49.28#ibcon#read 5, iclass 36, count 0 2006.252.07:40:49.28#ibcon#about to read 6, iclass 36, count 0 2006.252.07:40:49.28#ibcon#read 6, iclass 36, count 0 2006.252.07:40:49.28#ibcon#end of sib2, iclass 36, count 0 2006.252.07:40:49.28#ibcon#*mode == 0, iclass 36, count 0 2006.252.07:40:49.28#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.252.07:40:49.28#ibcon#[26=FRQ=05,652.99\r\n] 2006.252.07:40:49.28#ibcon#*before write, iclass 36, count 0 2006.252.07:40:49.28#ibcon#enter sib2, iclass 36, count 0 2006.252.07:40:49.28#ibcon#flushed, iclass 36, count 0 2006.252.07:40:49.28#ibcon#about to write, iclass 36, count 0 2006.252.07:40:49.28#ibcon#wrote, iclass 36, count 0 2006.252.07:40:49.28#ibcon#about to read 3, iclass 36, count 0 2006.252.07:40:49.32#ibcon#read 3, iclass 36, count 0 2006.252.07:40:49.32#ibcon#about to read 4, iclass 36, count 0 2006.252.07:40:49.32#ibcon#read 4, iclass 36, count 0 2006.252.07:40:49.32#ibcon#about to read 5, iclass 36, count 0 2006.252.07:40:49.32#ibcon#read 5, iclass 36, count 0 2006.252.07:40:49.32#ibcon#about to read 6, iclass 36, count 0 2006.252.07:40:49.32#ibcon#read 6, iclass 36, count 0 2006.252.07:40:49.32#ibcon#end of sib2, iclass 36, count 0 2006.252.07:40:49.32#ibcon#*after write, iclass 36, count 0 2006.252.07:40:49.32#ibcon#*before return 0, iclass 36, count 0 2006.252.07:40:49.32#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.252.07:40:49.32#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.252.07:40:49.32#ibcon#about to clear, iclass 36 cls_cnt 0 2006.252.07:40:49.32#ibcon#cleared, iclass 36 cls_cnt 0 2006.252.07:40:49.32$vc4f8/va=5,7 2006.252.07:40:49.32#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.252.07:40:49.32#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.252.07:40:49.32#ibcon#ireg 11 cls_cnt 2 2006.252.07:40:49.32#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.252.07:40:49.38#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.252.07:40:49.38#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.252.07:40:49.38#ibcon#enter wrdev, iclass 38, count 2 2006.252.07:40:49.38#ibcon#first serial, iclass 38, count 2 2006.252.07:40:49.38#ibcon#enter sib2, iclass 38, count 2 2006.252.07:40:49.38#ibcon#flushed, iclass 38, count 2 2006.252.07:40:49.38#ibcon#about to write, iclass 38, count 2 2006.252.07:40:49.38#ibcon#wrote, iclass 38, count 2 2006.252.07:40:49.38#ibcon#about to read 3, iclass 38, count 2 2006.252.07:40:49.40#ibcon#read 3, iclass 38, count 2 2006.252.07:40:49.40#ibcon#about to read 4, iclass 38, count 2 2006.252.07:40:49.40#ibcon#read 4, iclass 38, count 2 2006.252.07:40:49.40#ibcon#about to read 5, iclass 38, count 2 2006.252.07:40:49.40#ibcon#read 5, iclass 38, count 2 2006.252.07:40:49.40#ibcon#about to read 6, iclass 38, count 2 2006.252.07:40:49.40#ibcon#read 6, iclass 38, count 2 2006.252.07:40:49.40#ibcon#end of sib2, iclass 38, count 2 2006.252.07:40:49.40#ibcon#*mode == 0, iclass 38, count 2 2006.252.07:40:49.40#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.252.07:40:49.40#ibcon#[25=AT05-07\r\n] 2006.252.07:40:49.40#ibcon#*before write, iclass 38, count 2 2006.252.07:40:49.40#ibcon#enter sib2, iclass 38, count 2 2006.252.07:40:49.40#ibcon#flushed, iclass 38, count 2 2006.252.07:40:49.40#ibcon#about to write, iclass 38, count 2 2006.252.07:40:49.40#ibcon#wrote, iclass 38, count 2 2006.252.07:40:49.40#ibcon#about to read 3, iclass 38, count 2 2006.252.07:40:49.43#ibcon#read 3, iclass 38, count 2 2006.252.07:40:49.43#ibcon#about to read 4, iclass 38, count 2 2006.252.07:40:49.43#ibcon#read 4, iclass 38, count 2 2006.252.07:40:49.43#ibcon#about to read 5, iclass 38, count 2 2006.252.07:40:49.43#ibcon#read 5, iclass 38, count 2 2006.252.07:40:49.43#ibcon#about to read 6, iclass 38, count 2 2006.252.07:40:49.43#ibcon#read 6, iclass 38, count 2 2006.252.07:40:49.43#ibcon#end of sib2, iclass 38, count 2 2006.252.07:40:49.43#ibcon#*after write, iclass 38, count 2 2006.252.07:40:49.43#ibcon#*before return 0, iclass 38, count 2 2006.252.07:40:49.43#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.252.07:40:49.43#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.252.07:40:49.43#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.252.07:40:49.43#ibcon#ireg 7 cls_cnt 0 2006.252.07:40:49.43#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.252.07:40:49.56#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.252.07:40:49.56#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.252.07:40:49.56#ibcon#enter wrdev, iclass 38, count 0 2006.252.07:40:49.56#ibcon#first serial, iclass 38, count 0 2006.252.07:40:49.56#ibcon#enter sib2, iclass 38, count 0 2006.252.07:40:49.56#ibcon#flushed, iclass 38, count 0 2006.252.07:40:49.56#ibcon#about to write, iclass 38, count 0 2006.252.07:40:49.56#ibcon#wrote, iclass 38, count 0 2006.252.07:40:49.56#ibcon#about to read 3, iclass 38, count 0 2006.252.07:40:49.57#ibcon#read 3, iclass 38, count 0 2006.252.07:40:49.57#ibcon#about to read 4, iclass 38, count 0 2006.252.07:40:49.57#ibcon#read 4, iclass 38, count 0 2006.252.07:40:49.57#ibcon#about to read 5, iclass 38, count 0 2006.252.07:40:49.57#ibcon#read 5, iclass 38, count 0 2006.252.07:40:49.57#ibcon#about to read 6, iclass 38, count 0 2006.252.07:40:49.57#ibcon#read 6, iclass 38, count 0 2006.252.07:40:49.57#ibcon#end of sib2, iclass 38, count 0 2006.252.07:40:49.57#ibcon#*mode == 0, iclass 38, count 0 2006.252.07:40:49.57#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.252.07:40:49.57#ibcon#[25=USB\r\n] 2006.252.07:40:49.57#ibcon#*before write, iclass 38, count 0 2006.252.07:40:49.57#ibcon#enter sib2, iclass 38, count 0 2006.252.07:40:49.57#ibcon#flushed, iclass 38, count 0 2006.252.07:40:49.57#ibcon#about to write, iclass 38, count 0 2006.252.07:40:49.57#ibcon#wrote, iclass 38, count 0 2006.252.07:40:49.57#ibcon#about to read 3, iclass 38, count 0 2006.252.07:40:49.60#ibcon#read 3, iclass 38, count 0 2006.252.07:40:49.60#ibcon#about to read 4, iclass 38, count 0 2006.252.07:40:49.60#ibcon#read 4, iclass 38, count 0 2006.252.07:40:49.60#ibcon#about to read 5, iclass 38, count 0 2006.252.07:40:49.60#ibcon#read 5, iclass 38, count 0 2006.252.07:40:49.60#ibcon#about to read 6, iclass 38, count 0 2006.252.07:40:49.60#ibcon#read 6, iclass 38, count 0 2006.252.07:40:49.60#ibcon#end of sib2, iclass 38, count 0 2006.252.07:40:49.60#ibcon#*after write, iclass 38, count 0 2006.252.07:40:49.60#ibcon#*before return 0, iclass 38, count 0 2006.252.07:40:49.60#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.252.07:40:49.60#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.252.07:40:49.60#ibcon#about to clear, iclass 38 cls_cnt 0 2006.252.07:40:49.60#ibcon#cleared, iclass 38 cls_cnt 0 2006.252.07:40:49.60$vc4f8/valo=6,772.99 2006.252.07:40:49.60#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.252.07:40:49.60#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.252.07:40:49.60#ibcon#ireg 17 cls_cnt 0 2006.252.07:40:49.60#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.252.07:40:49.60#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.252.07:40:49.60#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.252.07:40:49.60#ibcon#enter wrdev, iclass 40, count 0 2006.252.07:40:49.60#ibcon#first serial, iclass 40, count 0 2006.252.07:40:49.60#ibcon#enter sib2, iclass 40, count 0 2006.252.07:40:49.60#ibcon#flushed, iclass 40, count 0 2006.252.07:40:49.60#ibcon#about to write, iclass 40, count 0 2006.252.07:40:49.60#ibcon#wrote, iclass 40, count 0 2006.252.07:40:49.60#ibcon#about to read 3, iclass 40, count 0 2006.252.07:40:49.62#ibcon#read 3, iclass 40, count 0 2006.252.07:40:49.62#ibcon#about to read 4, iclass 40, count 0 2006.252.07:40:49.62#ibcon#read 4, iclass 40, count 0 2006.252.07:40:49.62#ibcon#about to read 5, iclass 40, count 0 2006.252.07:40:49.62#ibcon#read 5, iclass 40, count 0 2006.252.07:40:49.62#ibcon#about to read 6, iclass 40, count 0 2006.252.07:40:49.62#ibcon#read 6, iclass 40, count 0 2006.252.07:40:49.62#ibcon#end of sib2, iclass 40, count 0 2006.252.07:40:49.62#ibcon#*mode == 0, iclass 40, count 0 2006.252.07:40:49.62#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.252.07:40:49.62#ibcon#[26=FRQ=06,772.99\r\n] 2006.252.07:40:49.62#ibcon#*before write, iclass 40, count 0 2006.252.07:40:49.62#ibcon#enter sib2, iclass 40, count 0 2006.252.07:40:49.62#ibcon#flushed, iclass 40, count 0 2006.252.07:40:49.62#ibcon#about to write, iclass 40, count 0 2006.252.07:40:49.62#ibcon#wrote, iclass 40, count 0 2006.252.07:40:49.62#ibcon#about to read 3, iclass 40, count 0 2006.252.07:40:49.66#ibcon#read 3, iclass 40, count 0 2006.252.07:40:49.66#ibcon#about to read 4, iclass 40, count 0 2006.252.07:40:49.66#ibcon#read 4, iclass 40, count 0 2006.252.07:40:49.66#ibcon#about to read 5, iclass 40, count 0 2006.252.07:40:49.66#ibcon#read 5, iclass 40, count 0 2006.252.07:40:49.66#ibcon#about to read 6, iclass 40, count 0 2006.252.07:40:49.66#ibcon#read 6, iclass 40, count 0 2006.252.07:40:49.66#ibcon#end of sib2, iclass 40, count 0 2006.252.07:40:49.66#ibcon#*after write, iclass 40, count 0 2006.252.07:40:49.66#ibcon#*before return 0, iclass 40, count 0 2006.252.07:40:49.66#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.252.07:40:49.66#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.252.07:40:49.66#ibcon#about to clear, iclass 40 cls_cnt 0 2006.252.07:40:49.66#ibcon#cleared, iclass 40 cls_cnt 0 2006.252.07:40:49.66$vc4f8/va=6,7 2006.252.07:40:49.66#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.252.07:40:49.66#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.252.07:40:49.66#ibcon#ireg 11 cls_cnt 2 2006.252.07:40:49.66#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.252.07:40:49.72#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.252.07:40:49.72#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.252.07:40:49.72#ibcon#enter wrdev, iclass 4, count 2 2006.252.07:40:49.72#ibcon#first serial, iclass 4, count 2 2006.252.07:40:49.72#ibcon#enter sib2, iclass 4, count 2 2006.252.07:40:49.72#ibcon#flushed, iclass 4, count 2 2006.252.07:40:49.72#ibcon#about to write, iclass 4, count 2 2006.252.07:40:49.72#ibcon#wrote, iclass 4, count 2 2006.252.07:40:49.72#ibcon#about to read 3, iclass 4, count 2 2006.252.07:40:49.74#ibcon#read 3, iclass 4, count 2 2006.252.07:40:49.74#ibcon#about to read 4, iclass 4, count 2 2006.252.07:40:49.74#ibcon#read 4, iclass 4, count 2 2006.252.07:40:49.74#ibcon#about to read 5, iclass 4, count 2 2006.252.07:40:49.74#ibcon#read 5, iclass 4, count 2 2006.252.07:40:49.74#ibcon#about to read 6, iclass 4, count 2 2006.252.07:40:49.74#ibcon#read 6, iclass 4, count 2 2006.252.07:40:49.74#ibcon#end of sib2, iclass 4, count 2 2006.252.07:40:49.74#ibcon#*mode == 0, iclass 4, count 2 2006.252.07:40:49.74#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.252.07:40:49.74#ibcon#[25=AT06-07\r\n] 2006.252.07:40:49.74#ibcon#*before write, iclass 4, count 2 2006.252.07:40:49.74#ibcon#enter sib2, iclass 4, count 2 2006.252.07:40:49.74#ibcon#flushed, iclass 4, count 2 2006.252.07:40:49.74#ibcon#about to write, iclass 4, count 2 2006.252.07:40:49.74#ibcon#wrote, iclass 4, count 2 2006.252.07:40:49.74#ibcon#about to read 3, iclass 4, count 2 2006.252.07:40:49.77#ibcon#read 3, iclass 4, count 2 2006.252.07:40:49.77#ibcon#about to read 4, iclass 4, count 2 2006.252.07:40:49.77#ibcon#read 4, iclass 4, count 2 2006.252.07:40:49.77#ibcon#about to read 5, iclass 4, count 2 2006.252.07:40:49.77#ibcon#read 5, iclass 4, count 2 2006.252.07:40:49.77#ibcon#about to read 6, iclass 4, count 2 2006.252.07:40:49.77#ibcon#read 6, iclass 4, count 2 2006.252.07:40:49.77#ibcon#end of sib2, iclass 4, count 2 2006.252.07:40:49.77#ibcon#*after write, iclass 4, count 2 2006.252.07:40:49.77#ibcon#*before return 0, iclass 4, count 2 2006.252.07:40:49.77#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.252.07:40:49.77#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.252.07:40:49.77#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.252.07:40:49.77#ibcon#ireg 7 cls_cnt 0 2006.252.07:40:49.77#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.252.07:40:49.89#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.252.07:40:49.89#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.252.07:40:49.89#ibcon#enter wrdev, iclass 4, count 0 2006.252.07:40:49.89#ibcon#first serial, iclass 4, count 0 2006.252.07:40:49.89#ibcon#enter sib2, iclass 4, count 0 2006.252.07:40:49.89#ibcon#flushed, iclass 4, count 0 2006.252.07:40:49.89#ibcon#about to write, iclass 4, count 0 2006.252.07:40:49.89#ibcon#wrote, iclass 4, count 0 2006.252.07:40:49.89#ibcon#about to read 3, iclass 4, count 0 2006.252.07:40:49.91#ibcon#read 3, iclass 4, count 0 2006.252.07:40:49.91#ibcon#about to read 4, iclass 4, count 0 2006.252.07:40:49.91#ibcon#read 4, iclass 4, count 0 2006.252.07:40:49.91#ibcon#about to read 5, iclass 4, count 0 2006.252.07:40:49.91#ibcon#read 5, iclass 4, count 0 2006.252.07:40:49.91#ibcon#about to read 6, iclass 4, count 0 2006.252.07:40:49.91#ibcon#read 6, iclass 4, count 0 2006.252.07:40:49.91#ibcon#end of sib2, iclass 4, count 0 2006.252.07:40:49.91#ibcon#*mode == 0, iclass 4, count 0 2006.252.07:40:49.91#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.252.07:40:49.91#ibcon#[25=USB\r\n] 2006.252.07:40:49.91#ibcon#*before write, iclass 4, count 0 2006.252.07:40:49.91#ibcon#enter sib2, iclass 4, count 0 2006.252.07:40:49.91#ibcon#flushed, iclass 4, count 0 2006.252.07:40:49.91#ibcon#about to write, iclass 4, count 0 2006.252.07:40:49.91#ibcon#wrote, iclass 4, count 0 2006.252.07:40:49.91#ibcon#about to read 3, iclass 4, count 0 2006.252.07:40:49.94#ibcon#read 3, iclass 4, count 0 2006.252.07:40:49.94#ibcon#about to read 4, iclass 4, count 0 2006.252.07:40:49.94#ibcon#read 4, iclass 4, count 0 2006.252.07:40:49.94#ibcon#about to read 5, iclass 4, count 0 2006.252.07:40:49.94#ibcon#read 5, iclass 4, count 0 2006.252.07:40:49.94#ibcon#about to read 6, iclass 4, count 0 2006.252.07:40:49.94#ibcon#read 6, iclass 4, count 0 2006.252.07:40:49.94#ibcon#end of sib2, iclass 4, count 0 2006.252.07:40:49.94#ibcon#*after write, iclass 4, count 0 2006.252.07:40:49.94#ibcon#*before return 0, iclass 4, count 0 2006.252.07:40:49.94#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.252.07:40:49.94#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.252.07:40:49.94#ibcon#about to clear, iclass 4 cls_cnt 0 2006.252.07:40:49.94#ibcon#cleared, iclass 4 cls_cnt 0 2006.252.07:40:49.94$vc4f8/valo=7,832.99 2006.252.07:40:49.94#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.252.07:40:49.94#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.252.07:40:49.94#ibcon#ireg 17 cls_cnt 0 2006.252.07:40:49.94#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.252.07:40:49.94#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.252.07:40:49.94#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.252.07:40:49.94#ibcon#enter wrdev, iclass 6, count 0 2006.252.07:40:49.94#ibcon#first serial, iclass 6, count 0 2006.252.07:40:49.94#ibcon#enter sib2, iclass 6, count 0 2006.252.07:40:49.94#ibcon#flushed, iclass 6, count 0 2006.252.07:40:49.94#ibcon#about to write, iclass 6, count 0 2006.252.07:40:49.94#ibcon#wrote, iclass 6, count 0 2006.252.07:40:49.94#ibcon#about to read 3, iclass 6, count 0 2006.252.07:40:49.96#ibcon#read 3, iclass 6, count 0 2006.252.07:40:49.96#ibcon#about to read 4, iclass 6, count 0 2006.252.07:40:49.96#ibcon#read 4, iclass 6, count 0 2006.252.07:40:49.96#ibcon#about to read 5, iclass 6, count 0 2006.252.07:40:49.96#ibcon#read 5, iclass 6, count 0 2006.252.07:40:49.96#ibcon#about to read 6, iclass 6, count 0 2006.252.07:40:49.96#ibcon#read 6, iclass 6, count 0 2006.252.07:40:49.96#ibcon#end of sib2, iclass 6, count 0 2006.252.07:40:49.96#ibcon#*mode == 0, iclass 6, count 0 2006.252.07:40:49.96#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.252.07:40:49.96#ibcon#[26=FRQ=07,832.99\r\n] 2006.252.07:40:49.96#ibcon#*before write, iclass 6, count 0 2006.252.07:40:49.96#ibcon#enter sib2, iclass 6, count 0 2006.252.07:40:49.96#ibcon#flushed, iclass 6, count 0 2006.252.07:40:49.96#ibcon#about to write, iclass 6, count 0 2006.252.07:40:49.96#ibcon#wrote, iclass 6, count 0 2006.252.07:40:49.96#ibcon#about to read 3, iclass 6, count 0 2006.252.07:40:50.00#ibcon#read 3, iclass 6, count 0 2006.252.07:40:50.00#ibcon#about to read 4, iclass 6, count 0 2006.252.07:40:50.00#ibcon#read 4, iclass 6, count 0 2006.252.07:40:50.00#ibcon#about to read 5, iclass 6, count 0 2006.252.07:40:50.00#ibcon#read 5, iclass 6, count 0 2006.252.07:40:50.00#ibcon#about to read 6, iclass 6, count 0 2006.252.07:40:50.00#ibcon#read 6, iclass 6, count 0 2006.252.07:40:50.00#ibcon#end of sib2, iclass 6, count 0 2006.252.07:40:50.00#ibcon#*after write, iclass 6, count 0 2006.252.07:40:50.00#ibcon#*before return 0, iclass 6, count 0 2006.252.07:40:50.00#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.252.07:40:50.00#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.252.07:40:50.00#ibcon#about to clear, iclass 6 cls_cnt 0 2006.252.07:40:50.00#ibcon#cleared, iclass 6 cls_cnt 0 2006.252.07:40:50.00$vc4f8/va=7,7 2006.252.07:40:50.00#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.252.07:40:50.00#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.252.07:40:50.00#ibcon#ireg 11 cls_cnt 2 2006.252.07:40:50.00#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.252.07:40:50.06#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.252.07:40:50.06#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.252.07:40:50.06#ibcon#enter wrdev, iclass 10, count 2 2006.252.07:40:50.06#ibcon#first serial, iclass 10, count 2 2006.252.07:40:50.06#ibcon#enter sib2, iclass 10, count 2 2006.252.07:40:50.06#ibcon#flushed, iclass 10, count 2 2006.252.07:40:50.06#ibcon#about to write, iclass 10, count 2 2006.252.07:40:50.06#ibcon#wrote, iclass 10, count 2 2006.252.07:40:50.06#ibcon#about to read 3, iclass 10, count 2 2006.252.07:40:50.08#ibcon#read 3, iclass 10, count 2 2006.252.07:40:50.08#ibcon#about to read 4, iclass 10, count 2 2006.252.07:40:50.08#ibcon#read 4, iclass 10, count 2 2006.252.07:40:50.08#ibcon#about to read 5, iclass 10, count 2 2006.252.07:40:50.08#ibcon#read 5, iclass 10, count 2 2006.252.07:40:50.08#ibcon#about to read 6, iclass 10, count 2 2006.252.07:40:50.08#ibcon#read 6, iclass 10, count 2 2006.252.07:40:50.08#ibcon#end of sib2, iclass 10, count 2 2006.252.07:40:50.08#ibcon#*mode == 0, iclass 10, count 2 2006.252.07:40:50.08#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.252.07:40:50.08#ibcon#[25=AT07-07\r\n] 2006.252.07:40:50.08#ibcon#*before write, iclass 10, count 2 2006.252.07:40:50.08#ibcon#enter sib2, iclass 10, count 2 2006.252.07:40:50.08#ibcon#flushed, iclass 10, count 2 2006.252.07:40:50.08#ibcon#about to write, iclass 10, count 2 2006.252.07:40:50.08#ibcon#wrote, iclass 10, count 2 2006.252.07:40:50.08#ibcon#about to read 3, iclass 10, count 2 2006.252.07:40:50.11#ibcon#read 3, iclass 10, count 2 2006.252.07:40:50.11#ibcon#about to read 4, iclass 10, count 2 2006.252.07:40:50.11#ibcon#read 4, iclass 10, count 2 2006.252.07:40:50.11#ibcon#about to read 5, iclass 10, count 2 2006.252.07:40:50.11#ibcon#read 5, iclass 10, count 2 2006.252.07:40:50.11#ibcon#about to read 6, iclass 10, count 2 2006.252.07:40:50.11#ibcon#read 6, iclass 10, count 2 2006.252.07:40:50.11#ibcon#end of sib2, iclass 10, count 2 2006.252.07:40:50.11#ibcon#*after write, iclass 10, count 2 2006.252.07:40:50.11#ibcon#*before return 0, iclass 10, count 2 2006.252.07:40:50.11#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.252.07:40:50.11#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.252.07:40:50.11#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.252.07:40:50.11#ibcon#ireg 7 cls_cnt 0 2006.252.07:40:50.11#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.252.07:40:50.23#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.252.07:40:50.23#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.252.07:40:50.23#ibcon#enter wrdev, iclass 10, count 0 2006.252.07:40:50.23#ibcon#first serial, iclass 10, count 0 2006.252.07:40:50.23#ibcon#enter sib2, iclass 10, count 0 2006.252.07:40:50.23#ibcon#flushed, iclass 10, count 0 2006.252.07:40:50.23#ibcon#about to write, iclass 10, count 0 2006.252.07:40:50.23#ibcon#wrote, iclass 10, count 0 2006.252.07:40:50.23#ibcon#about to read 3, iclass 10, count 0 2006.252.07:40:50.25#ibcon#read 3, iclass 10, count 0 2006.252.07:40:50.25#ibcon#about to read 4, iclass 10, count 0 2006.252.07:40:50.25#ibcon#read 4, iclass 10, count 0 2006.252.07:40:50.25#ibcon#about to read 5, iclass 10, count 0 2006.252.07:40:50.25#ibcon#read 5, iclass 10, count 0 2006.252.07:40:50.25#ibcon#about to read 6, iclass 10, count 0 2006.252.07:40:50.25#ibcon#read 6, iclass 10, count 0 2006.252.07:40:50.25#ibcon#end of sib2, iclass 10, count 0 2006.252.07:40:50.25#ibcon#*mode == 0, iclass 10, count 0 2006.252.07:40:50.25#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.252.07:40:50.25#ibcon#[25=USB\r\n] 2006.252.07:40:50.25#ibcon#*before write, iclass 10, count 0 2006.252.07:40:50.25#ibcon#enter sib2, iclass 10, count 0 2006.252.07:40:50.25#ibcon#flushed, iclass 10, count 0 2006.252.07:40:50.25#ibcon#about to write, iclass 10, count 0 2006.252.07:40:50.25#ibcon#wrote, iclass 10, count 0 2006.252.07:40:50.25#ibcon#about to read 3, iclass 10, count 0 2006.252.07:40:50.28#ibcon#read 3, iclass 10, count 0 2006.252.07:40:50.28#ibcon#about to read 4, iclass 10, count 0 2006.252.07:40:50.28#ibcon#read 4, iclass 10, count 0 2006.252.07:40:50.28#ibcon#about to read 5, iclass 10, count 0 2006.252.07:40:50.28#ibcon#read 5, iclass 10, count 0 2006.252.07:40:50.28#ibcon#about to read 6, iclass 10, count 0 2006.252.07:40:50.28#ibcon#read 6, iclass 10, count 0 2006.252.07:40:50.28#ibcon#end of sib2, iclass 10, count 0 2006.252.07:40:50.28#ibcon#*after write, iclass 10, count 0 2006.252.07:40:50.28#ibcon#*before return 0, iclass 10, count 0 2006.252.07:40:50.28#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.252.07:40:50.28#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.252.07:40:50.28#ibcon#about to clear, iclass 10 cls_cnt 0 2006.252.07:40:50.28#ibcon#cleared, iclass 10 cls_cnt 0 2006.252.07:40:50.28$vc4f8/valo=8,852.99 2006.252.07:40:50.28#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.252.07:40:50.28#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.252.07:40:50.28#ibcon#ireg 17 cls_cnt 0 2006.252.07:40:50.28#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.252.07:40:50.28#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.252.07:40:50.28#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.252.07:40:50.28#ibcon#enter wrdev, iclass 12, count 0 2006.252.07:40:50.28#ibcon#first serial, iclass 12, count 0 2006.252.07:40:50.28#ibcon#enter sib2, iclass 12, count 0 2006.252.07:40:50.28#ibcon#flushed, iclass 12, count 0 2006.252.07:40:50.28#ibcon#about to write, iclass 12, count 0 2006.252.07:40:50.28#ibcon#wrote, iclass 12, count 0 2006.252.07:40:50.28#ibcon#about to read 3, iclass 12, count 0 2006.252.07:40:50.31#ibcon#read 3, iclass 12, count 0 2006.252.07:40:50.31#ibcon#about to read 4, iclass 12, count 0 2006.252.07:40:50.31#ibcon#read 4, iclass 12, count 0 2006.252.07:40:50.31#ibcon#about to read 5, iclass 12, count 0 2006.252.07:40:50.31#ibcon#read 5, iclass 12, count 0 2006.252.07:40:50.31#ibcon#about to read 6, iclass 12, count 0 2006.252.07:40:50.31#ibcon#read 6, iclass 12, count 0 2006.252.07:40:50.31#ibcon#end of sib2, iclass 12, count 0 2006.252.07:40:50.31#ibcon#*mode == 0, iclass 12, count 0 2006.252.07:40:50.31#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.252.07:40:50.31#ibcon#[26=FRQ=08,852.99\r\n] 2006.252.07:40:50.31#ibcon#*before write, iclass 12, count 0 2006.252.07:40:50.31#ibcon#enter sib2, iclass 12, count 0 2006.252.07:40:50.31#ibcon#flushed, iclass 12, count 0 2006.252.07:40:50.31#ibcon#about to write, iclass 12, count 0 2006.252.07:40:50.31#ibcon#wrote, iclass 12, count 0 2006.252.07:40:50.31#ibcon#about to read 3, iclass 12, count 0 2006.252.07:40:50.35#ibcon#read 3, iclass 12, count 0 2006.252.07:40:50.35#ibcon#about to read 4, iclass 12, count 0 2006.252.07:40:50.35#ibcon#read 4, iclass 12, count 0 2006.252.07:40:50.35#ibcon#about to read 5, iclass 12, count 0 2006.252.07:40:50.35#ibcon#read 5, iclass 12, count 0 2006.252.07:40:50.35#ibcon#about to read 6, iclass 12, count 0 2006.252.07:40:50.35#ibcon#read 6, iclass 12, count 0 2006.252.07:40:50.35#ibcon#end of sib2, iclass 12, count 0 2006.252.07:40:50.35#ibcon#*after write, iclass 12, count 0 2006.252.07:40:50.35#ibcon#*before return 0, iclass 12, count 0 2006.252.07:40:50.35#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.252.07:40:50.35#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.252.07:40:50.35#ibcon#about to clear, iclass 12 cls_cnt 0 2006.252.07:40:50.35#ibcon#cleared, iclass 12 cls_cnt 0 2006.252.07:40:50.35$vc4f8/va=8,7 2006.252.07:40:50.35#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.252.07:40:50.35#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.252.07:40:50.35#ibcon#ireg 11 cls_cnt 2 2006.252.07:40:50.35#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.252.07:40:50.41#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.252.07:40:50.41#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.252.07:40:50.41#ibcon#enter wrdev, iclass 14, count 2 2006.252.07:40:50.41#ibcon#first serial, iclass 14, count 2 2006.252.07:40:50.41#ibcon#enter sib2, iclass 14, count 2 2006.252.07:40:50.41#ibcon#flushed, iclass 14, count 2 2006.252.07:40:50.41#ibcon#about to write, iclass 14, count 2 2006.252.07:40:50.41#ibcon#wrote, iclass 14, count 2 2006.252.07:40:50.41#ibcon#about to read 3, iclass 14, count 2 2006.252.07:40:50.42#ibcon#read 3, iclass 14, count 2 2006.252.07:40:50.42#ibcon#about to read 4, iclass 14, count 2 2006.252.07:40:50.42#ibcon#read 4, iclass 14, count 2 2006.252.07:40:50.42#ibcon#about to read 5, iclass 14, count 2 2006.252.07:40:50.42#ibcon#read 5, iclass 14, count 2 2006.252.07:40:50.42#ibcon#about to read 6, iclass 14, count 2 2006.252.07:40:50.42#ibcon#read 6, iclass 14, count 2 2006.252.07:40:50.42#ibcon#end of sib2, iclass 14, count 2 2006.252.07:40:50.42#ibcon#*mode == 0, iclass 14, count 2 2006.252.07:40:50.42#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.252.07:40:50.42#ibcon#[25=AT08-07\r\n] 2006.252.07:40:50.42#ibcon#*before write, iclass 14, count 2 2006.252.07:40:50.42#ibcon#enter sib2, iclass 14, count 2 2006.252.07:40:50.42#ibcon#flushed, iclass 14, count 2 2006.252.07:40:50.42#ibcon#about to write, iclass 14, count 2 2006.252.07:40:50.42#ibcon#wrote, iclass 14, count 2 2006.252.07:40:50.42#ibcon#about to read 3, iclass 14, count 2 2006.252.07:40:50.45#ibcon#read 3, iclass 14, count 2 2006.252.07:40:50.45#ibcon#about to read 4, iclass 14, count 2 2006.252.07:40:50.45#ibcon#read 4, iclass 14, count 2 2006.252.07:40:50.45#ibcon#about to read 5, iclass 14, count 2 2006.252.07:40:50.45#ibcon#read 5, iclass 14, count 2 2006.252.07:40:50.45#ibcon#about to read 6, iclass 14, count 2 2006.252.07:40:50.45#ibcon#read 6, iclass 14, count 2 2006.252.07:40:50.45#ibcon#end of sib2, iclass 14, count 2 2006.252.07:40:50.45#ibcon#*after write, iclass 14, count 2 2006.252.07:40:50.45#ibcon#*before return 0, iclass 14, count 2 2006.252.07:40:50.45#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.252.07:40:50.45#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.252.07:40:50.45#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.252.07:40:50.45#ibcon#ireg 7 cls_cnt 0 2006.252.07:40:50.45#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.252.07:40:50.57#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.252.07:40:50.57#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.252.07:40:50.57#ibcon#enter wrdev, iclass 14, count 0 2006.252.07:40:50.57#ibcon#first serial, iclass 14, count 0 2006.252.07:40:50.57#ibcon#enter sib2, iclass 14, count 0 2006.252.07:40:50.57#ibcon#flushed, iclass 14, count 0 2006.252.07:40:50.57#ibcon#about to write, iclass 14, count 0 2006.252.07:40:50.57#ibcon#wrote, iclass 14, count 0 2006.252.07:40:50.57#ibcon#about to read 3, iclass 14, count 0 2006.252.07:40:50.59#ibcon#read 3, iclass 14, count 0 2006.252.07:40:50.59#ibcon#about to read 4, iclass 14, count 0 2006.252.07:40:50.59#ibcon#read 4, iclass 14, count 0 2006.252.07:40:50.59#ibcon#about to read 5, iclass 14, count 0 2006.252.07:40:50.59#ibcon#read 5, iclass 14, count 0 2006.252.07:40:50.59#ibcon#about to read 6, iclass 14, count 0 2006.252.07:40:50.59#ibcon#read 6, iclass 14, count 0 2006.252.07:40:50.59#ibcon#end of sib2, iclass 14, count 0 2006.252.07:40:50.59#ibcon#*mode == 0, iclass 14, count 0 2006.252.07:40:50.59#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.252.07:40:50.59#ibcon#[25=USB\r\n] 2006.252.07:40:50.59#ibcon#*before write, iclass 14, count 0 2006.252.07:40:50.59#ibcon#enter sib2, iclass 14, count 0 2006.252.07:40:50.59#ibcon#flushed, iclass 14, count 0 2006.252.07:40:50.59#ibcon#about to write, iclass 14, count 0 2006.252.07:40:50.59#ibcon#wrote, iclass 14, count 0 2006.252.07:40:50.59#ibcon#about to read 3, iclass 14, count 0 2006.252.07:40:50.62#ibcon#read 3, iclass 14, count 0 2006.252.07:40:50.62#ibcon#about to read 4, iclass 14, count 0 2006.252.07:40:50.62#ibcon#read 4, iclass 14, count 0 2006.252.07:40:50.62#ibcon#about to read 5, iclass 14, count 0 2006.252.07:40:50.62#ibcon#read 5, iclass 14, count 0 2006.252.07:40:50.62#ibcon#about to read 6, iclass 14, count 0 2006.252.07:40:50.62#ibcon#read 6, iclass 14, count 0 2006.252.07:40:50.62#ibcon#end of sib2, iclass 14, count 0 2006.252.07:40:50.62#ibcon#*after write, iclass 14, count 0 2006.252.07:40:50.62#ibcon#*before return 0, iclass 14, count 0 2006.252.07:40:50.62#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.252.07:40:50.62#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.252.07:40:50.62#ibcon#about to clear, iclass 14 cls_cnt 0 2006.252.07:40:50.62#ibcon#cleared, iclass 14 cls_cnt 0 2006.252.07:40:50.62$vc4f8/vblo=1,632.99 2006.252.07:40:50.62#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.252.07:40:50.62#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.252.07:40:50.62#ibcon#ireg 17 cls_cnt 0 2006.252.07:40:50.62#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.252.07:40:50.62#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.252.07:40:50.62#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.252.07:40:50.62#ibcon#enter wrdev, iclass 16, count 0 2006.252.07:40:50.62#ibcon#first serial, iclass 16, count 0 2006.252.07:40:50.62#ibcon#enter sib2, iclass 16, count 0 2006.252.07:40:50.62#ibcon#flushed, iclass 16, count 0 2006.252.07:40:50.62#ibcon#about to write, iclass 16, count 0 2006.252.07:40:50.62#ibcon#wrote, iclass 16, count 0 2006.252.07:40:50.62#ibcon#about to read 3, iclass 16, count 0 2006.252.07:40:50.64#ibcon#read 3, iclass 16, count 0 2006.252.07:40:50.64#ibcon#about to read 4, iclass 16, count 0 2006.252.07:40:50.64#ibcon#read 4, iclass 16, count 0 2006.252.07:40:50.64#ibcon#about to read 5, iclass 16, count 0 2006.252.07:40:50.64#ibcon#read 5, iclass 16, count 0 2006.252.07:40:50.64#ibcon#about to read 6, iclass 16, count 0 2006.252.07:40:50.64#ibcon#read 6, iclass 16, count 0 2006.252.07:40:50.64#ibcon#end of sib2, iclass 16, count 0 2006.252.07:40:50.64#ibcon#*mode == 0, iclass 16, count 0 2006.252.07:40:50.64#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.252.07:40:50.64#ibcon#[28=FRQ=01,632.99\r\n] 2006.252.07:40:50.64#ibcon#*before write, iclass 16, count 0 2006.252.07:40:50.64#ibcon#enter sib2, iclass 16, count 0 2006.252.07:40:50.64#ibcon#flushed, iclass 16, count 0 2006.252.07:40:50.64#ibcon#about to write, iclass 16, count 0 2006.252.07:40:50.64#ibcon#wrote, iclass 16, count 0 2006.252.07:40:50.64#ibcon#about to read 3, iclass 16, count 0 2006.252.07:40:50.68#ibcon#read 3, iclass 16, count 0 2006.252.07:40:50.68#ibcon#about to read 4, iclass 16, count 0 2006.252.07:40:50.68#ibcon#read 4, iclass 16, count 0 2006.252.07:40:50.68#ibcon#about to read 5, iclass 16, count 0 2006.252.07:40:50.68#ibcon#read 5, iclass 16, count 0 2006.252.07:40:50.68#ibcon#about to read 6, iclass 16, count 0 2006.252.07:40:50.68#ibcon#read 6, iclass 16, count 0 2006.252.07:40:50.68#ibcon#end of sib2, iclass 16, count 0 2006.252.07:40:50.68#ibcon#*after write, iclass 16, count 0 2006.252.07:40:50.68#ibcon#*before return 0, iclass 16, count 0 2006.252.07:40:50.68#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.252.07:40:50.68#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.252.07:40:50.68#ibcon#about to clear, iclass 16 cls_cnt 0 2006.252.07:40:50.68#ibcon#cleared, iclass 16 cls_cnt 0 2006.252.07:40:50.68$vc4f8/vb=1,4 2006.252.07:40:50.68#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.252.07:40:50.68#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.252.07:40:50.68#ibcon#ireg 11 cls_cnt 2 2006.252.07:40:50.68#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.252.07:40:50.68#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.252.07:40:50.68#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.252.07:40:50.68#ibcon#enter wrdev, iclass 18, count 2 2006.252.07:40:50.68#ibcon#first serial, iclass 18, count 2 2006.252.07:40:50.68#ibcon#enter sib2, iclass 18, count 2 2006.252.07:40:50.68#ibcon#flushed, iclass 18, count 2 2006.252.07:40:50.68#ibcon#about to write, iclass 18, count 2 2006.252.07:40:50.68#ibcon#wrote, iclass 18, count 2 2006.252.07:40:50.68#ibcon#about to read 3, iclass 18, count 2 2006.252.07:40:50.70#ibcon#read 3, iclass 18, count 2 2006.252.07:40:50.70#ibcon#about to read 4, iclass 18, count 2 2006.252.07:40:50.70#ibcon#read 4, iclass 18, count 2 2006.252.07:40:50.70#ibcon#about to read 5, iclass 18, count 2 2006.252.07:40:50.70#ibcon#read 5, iclass 18, count 2 2006.252.07:40:50.70#ibcon#about to read 6, iclass 18, count 2 2006.252.07:40:50.70#ibcon#read 6, iclass 18, count 2 2006.252.07:40:50.70#ibcon#end of sib2, iclass 18, count 2 2006.252.07:40:50.70#ibcon#*mode == 0, iclass 18, count 2 2006.252.07:40:50.70#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.252.07:40:50.70#ibcon#[27=AT01-04\r\n] 2006.252.07:40:50.70#ibcon#*before write, iclass 18, count 2 2006.252.07:40:50.70#ibcon#enter sib2, iclass 18, count 2 2006.252.07:40:50.70#ibcon#flushed, iclass 18, count 2 2006.252.07:40:50.70#ibcon#about to write, iclass 18, count 2 2006.252.07:40:50.70#ibcon#wrote, iclass 18, count 2 2006.252.07:40:50.70#ibcon#about to read 3, iclass 18, count 2 2006.252.07:40:50.73#ibcon#read 3, iclass 18, count 2 2006.252.07:40:50.73#ibcon#about to read 4, iclass 18, count 2 2006.252.07:40:50.73#ibcon#read 4, iclass 18, count 2 2006.252.07:40:50.73#ibcon#about to read 5, iclass 18, count 2 2006.252.07:40:50.73#ibcon#read 5, iclass 18, count 2 2006.252.07:40:50.73#ibcon#about to read 6, iclass 18, count 2 2006.252.07:40:50.73#ibcon#read 6, iclass 18, count 2 2006.252.07:40:50.73#ibcon#end of sib2, iclass 18, count 2 2006.252.07:40:50.73#ibcon#*after write, iclass 18, count 2 2006.252.07:40:50.73#ibcon#*before return 0, iclass 18, count 2 2006.252.07:40:50.73#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.252.07:40:50.73#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.252.07:40:50.73#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.252.07:40:50.73#ibcon#ireg 7 cls_cnt 0 2006.252.07:40:50.73#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.252.07:40:50.86#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.252.07:40:50.86#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.252.07:40:50.86#ibcon#enter wrdev, iclass 18, count 0 2006.252.07:40:50.86#ibcon#first serial, iclass 18, count 0 2006.252.07:40:50.86#ibcon#enter sib2, iclass 18, count 0 2006.252.07:40:50.86#ibcon#flushed, iclass 18, count 0 2006.252.07:40:50.86#ibcon#about to write, iclass 18, count 0 2006.252.07:40:50.86#ibcon#wrote, iclass 18, count 0 2006.252.07:40:50.86#ibcon#about to read 3, iclass 18, count 0 2006.252.07:40:50.87#ibcon#read 3, iclass 18, count 0 2006.252.07:40:50.87#ibcon#about to read 4, iclass 18, count 0 2006.252.07:40:50.87#ibcon#read 4, iclass 18, count 0 2006.252.07:40:50.87#ibcon#about to read 5, iclass 18, count 0 2006.252.07:40:50.87#ibcon#read 5, iclass 18, count 0 2006.252.07:40:50.87#ibcon#about to read 6, iclass 18, count 0 2006.252.07:40:50.87#ibcon#read 6, iclass 18, count 0 2006.252.07:40:50.87#ibcon#end of sib2, iclass 18, count 0 2006.252.07:40:50.87#ibcon#*mode == 0, iclass 18, count 0 2006.252.07:40:50.87#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.252.07:40:50.87#ibcon#[27=USB\r\n] 2006.252.07:40:50.87#ibcon#*before write, iclass 18, count 0 2006.252.07:40:50.87#ibcon#enter sib2, iclass 18, count 0 2006.252.07:40:50.87#ibcon#flushed, iclass 18, count 0 2006.252.07:40:50.87#ibcon#about to write, iclass 18, count 0 2006.252.07:40:50.87#ibcon#wrote, iclass 18, count 0 2006.252.07:40:50.87#ibcon#about to read 3, iclass 18, count 0 2006.252.07:40:50.90#ibcon#read 3, iclass 18, count 0 2006.252.07:40:50.90#ibcon#about to read 4, iclass 18, count 0 2006.252.07:40:50.90#ibcon#read 4, iclass 18, count 0 2006.252.07:40:50.90#ibcon#about to read 5, iclass 18, count 0 2006.252.07:40:50.90#ibcon#read 5, iclass 18, count 0 2006.252.07:40:50.90#ibcon#about to read 6, iclass 18, count 0 2006.252.07:40:50.90#ibcon#read 6, iclass 18, count 0 2006.252.07:40:50.90#ibcon#end of sib2, iclass 18, count 0 2006.252.07:40:50.90#ibcon#*after write, iclass 18, count 0 2006.252.07:40:50.90#ibcon#*before return 0, iclass 18, count 0 2006.252.07:40:50.90#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.252.07:40:50.90#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.252.07:40:50.90#ibcon#about to clear, iclass 18 cls_cnt 0 2006.252.07:40:50.90#ibcon#cleared, iclass 18 cls_cnt 0 2006.252.07:40:50.90$vc4f8/vblo=2,640.99 2006.252.07:40:50.90#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.252.07:40:50.90#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.252.07:40:50.90#ibcon#ireg 17 cls_cnt 0 2006.252.07:40:50.90#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.252.07:40:50.90#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.252.07:40:50.90#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.252.07:40:50.90#ibcon#enter wrdev, iclass 20, count 0 2006.252.07:40:50.90#ibcon#first serial, iclass 20, count 0 2006.252.07:40:50.90#ibcon#enter sib2, iclass 20, count 0 2006.252.07:40:50.90#ibcon#flushed, iclass 20, count 0 2006.252.07:40:50.90#ibcon#about to write, iclass 20, count 0 2006.252.07:40:50.90#ibcon#wrote, iclass 20, count 0 2006.252.07:40:50.90#ibcon#about to read 3, iclass 20, count 0 2006.252.07:40:50.93#ibcon#read 3, iclass 20, count 0 2006.252.07:40:50.93#ibcon#about to read 4, iclass 20, count 0 2006.252.07:40:50.93#ibcon#read 4, iclass 20, count 0 2006.252.07:40:50.93#ibcon#about to read 5, iclass 20, count 0 2006.252.07:40:50.93#ibcon#read 5, iclass 20, count 0 2006.252.07:40:50.93#ibcon#about to read 6, iclass 20, count 0 2006.252.07:40:50.93#ibcon#read 6, iclass 20, count 0 2006.252.07:40:50.93#ibcon#end of sib2, iclass 20, count 0 2006.252.07:40:50.93#ibcon#*mode == 0, iclass 20, count 0 2006.252.07:40:50.93#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.252.07:40:50.93#ibcon#[28=FRQ=02,640.99\r\n] 2006.252.07:40:50.93#ibcon#*before write, iclass 20, count 0 2006.252.07:40:50.93#ibcon#enter sib2, iclass 20, count 0 2006.252.07:40:50.93#ibcon#flushed, iclass 20, count 0 2006.252.07:40:50.93#ibcon#about to write, iclass 20, count 0 2006.252.07:40:50.93#ibcon#wrote, iclass 20, count 0 2006.252.07:40:50.93#ibcon#about to read 3, iclass 20, count 0 2006.252.07:40:50.97#ibcon#read 3, iclass 20, count 0 2006.252.07:40:50.97#ibcon#about to read 4, iclass 20, count 0 2006.252.07:40:50.97#ibcon#read 4, iclass 20, count 0 2006.252.07:40:50.97#ibcon#about to read 5, iclass 20, count 0 2006.252.07:40:50.97#ibcon#read 5, iclass 20, count 0 2006.252.07:40:50.97#ibcon#about to read 6, iclass 20, count 0 2006.252.07:40:50.97#ibcon#read 6, iclass 20, count 0 2006.252.07:40:50.97#ibcon#end of sib2, iclass 20, count 0 2006.252.07:40:50.97#ibcon#*after write, iclass 20, count 0 2006.252.07:40:50.97#ibcon#*before return 0, iclass 20, count 0 2006.252.07:40:50.97#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.252.07:40:50.97#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.252.07:40:50.97#ibcon#about to clear, iclass 20 cls_cnt 0 2006.252.07:40:50.97#ibcon#cleared, iclass 20 cls_cnt 0 2006.252.07:40:50.97$vc4f8/vb=2,5 2006.252.07:40:50.97#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.252.07:40:50.97#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.252.07:40:50.97#ibcon#ireg 11 cls_cnt 2 2006.252.07:40:50.97#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.252.07:40:51.03#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.252.07:40:51.03#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.252.07:40:51.03#ibcon#enter wrdev, iclass 22, count 2 2006.252.07:40:51.03#ibcon#first serial, iclass 22, count 2 2006.252.07:40:51.03#ibcon#enter sib2, iclass 22, count 2 2006.252.07:40:51.03#ibcon#flushed, iclass 22, count 2 2006.252.07:40:51.03#ibcon#about to write, iclass 22, count 2 2006.252.07:40:51.03#ibcon#wrote, iclass 22, count 2 2006.252.07:40:51.03#ibcon#about to read 3, iclass 22, count 2 2006.252.07:40:51.04#ibcon#read 3, iclass 22, count 2 2006.252.07:40:51.04#ibcon#about to read 4, iclass 22, count 2 2006.252.07:40:51.04#ibcon#read 4, iclass 22, count 2 2006.252.07:40:51.04#ibcon#about to read 5, iclass 22, count 2 2006.252.07:40:51.04#ibcon#read 5, iclass 22, count 2 2006.252.07:40:51.04#ibcon#about to read 6, iclass 22, count 2 2006.252.07:40:51.04#ibcon#read 6, iclass 22, count 2 2006.252.07:40:51.04#ibcon#end of sib2, iclass 22, count 2 2006.252.07:40:51.04#ibcon#*mode == 0, iclass 22, count 2 2006.252.07:40:51.04#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.252.07:40:51.04#ibcon#[27=AT02-05\r\n] 2006.252.07:40:51.04#ibcon#*before write, iclass 22, count 2 2006.252.07:40:51.04#ibcon#enter sib2, iclass 22, count 2 2006.252.07:40:51.04#ibcon#flushed, iclass 22, count 2 2006.252.07:40:51.04#ibcon#about to write, iclass 22, count 2 2006.252.07:40:51.04#ibcon#wrote, iclass 22, count 2 2006.252.07:40:51.04#ibcon#about to read 3, iclass 22, count 2 2006.252.07:40:51.07#ibcon#read 3, iclass 22, count 2 2006.252.07:40:51.07#ibcon#about to read 4, iclass 22, count 2 2006.252.07:40:51.07#ibcon#read 4, iclass 22, count 2 2006.252.07:40:51.07#ibcon#about to read 5, iclass 22, count 2 2006.252.07:40:51.07#ibcon#read 5, iclass 22, count 2 2006.252.07:40:51.07#ibcon#about to read 6, iclass 22, count 2 2006.252.07:40:51.07#ibcon#read 6, iclass 22, count 2 2006.252.07:40:51.07#ibcon#end of sib2, iclass 22, count 2 2006.252.07:40:51.07#ibcon#*after write, iclass 22, count 2 2006.252.07:40:51.07#ibcon#*before return 0, iclass 22, count 2 2006.252.07:40:51.07#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.252.07:40:51.07#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.252.07:40:51.07#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.252.07:40:51.07#ibcon#ireg 7 cls_cnt 0 2006.252.07:40:51.07#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.252.07:40:51.19#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.252.07:40:51.19#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.252.07:40:51.19#ibcon#enter wrdev, iclass 22, count 0 2006.252.07:40:51.19#ibcon#first serial, iclass 22, count 0 2006.252.07:40:51.19#ibcon#enter sib2, iclass 22, count 0 2006.252.07:40:51.19#ibcon#flushed, iclass 22, count 0 2006.252.07:40:51.19#ibcon#about to write, iclass 22, count 0 2006.252.07:40:51.19#ibcon#wrote, iclass 22, count 0 2006.252.07:40:51.19#ibcon#about to read 3, iclass 22, count 0 2006.252.07:40:51.21#ibcon#read 3, iclass 22, count 0 2006.252.07:40:51.21#ibcon#about to read 4, iclass 22, count 0 2006.252.07:40:51.21#ibcon#read 4, iclass 22, count 0 2006.252.07:40:51.21#ibcon#about to read 5, iclass 22, count 0 2006.252.07:40:51.21#ibcon#read 5, iclass 22, count 0 2006.252.07:40:51.21#ibcon#about to read 6, iclass 22, count 0 2006.252.07:40:51.21#ibcon#read 6, iclass 22, count 0 2006.252.07:40:51.21#ibcon#end of sib2, iclass 22, count 0 2006.252.07:40:51.21#ibcon#*mode == 0, iclass 22, count 0 2006.252.07:40:51.21#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.252.07:40:51.21#ibcon#[27=USB\r\n] 2006.252.07:40:51.21#ibcon#*before write, iclass 22, count 0 2006.252.07:40:51.21#ibcon#enter sib2, iclass 22, count 0 2006.252.07:40:51.21#ibcon#flushed, iclass 22, count 0 2006.252.07:40:51.21#ibcon#about to write, iclass 22, count 0 2006.252.07:40:51.21#ibcon#wrote, iclass 22, count 0 2006.252.07:40:51.21#ibcon#about to read 3, iclass 22, count 0 2006.252.07:40:51.24#ibcon#read 3, iclass 22, count 0 2006.252.07:40:51.24#ibcon#about to read 4, iclass 22, count 0 2006.252.07:40:51.24#ibcon#read 4, iclass 22, count 0 2006.252.07:40:51.24#ibcon#about to read 5, iclass 22, count 0 2006.252.07:40:51.24#ibcon#read 5, iclass 22, count 0 2006.252.07:40:51.24#ibcon#about to read 6, iclass 22, count 0 2006.252.07:40:51.24#ibcon#read 6, iclass 22, count 0 2006.252.07:40:51.24#ibcon#end of sib2, iclass 22, count 0 2006.252.07:40:51.24#ibcon#*after write, iclass 22, count 0 2006.252.07:40:51.24#ibcon#*before return 0, iclass 22, count 0 2006.252.07:40:51.24#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.252.07:40:51.24#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.252.07:40:51.24#ibcon#about to clear, iclass 22 cls_cnt 0 2006.252.07:40:51.24#ibcon#cleared, iclass 22 cls_cnt 0 2006.252.07:40:51.24$vc4f8/vblo=3,656.99 2006.252.07:40:51.24#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.252.07:40:51.24#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.252.07:40:51.24#ibcon#ireg 17 cls_cnt 0 2006.252.07:40:51.24#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.252.07:40:51.24#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.252.07:40:51.24#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.252.07:40:51.24#ibcon#enter wrdev, iclass 24, count 0 2006.252.07:40:51.24#ibcon#first serial, iclass 24, count 0 2006.252.07:40:51.24#ibcon#enter sib2, iclass 24, count 0 2006.252.07:40:51.24#ibcon#flushed, iclass 24, count 0 2006.252.07:40:51.24#ibcon#about to write, iclass 24, count 0 2006.252.07:40:51.24#ibcon#wrote, iclass 24, count 0 2006.252.07:40:51.24#ibcon#about to read 3, iclass 24, count 0 2006.252.07:40:51.26#ibcon#read 3, iclass 24, count 0 2006.252.07:40:51.26#ibcon#about to read 4, iclass 24, count 0 2006.252.07:40:51.26#ibcon#read 4, iclass 24, count 0 2006.252.07:40:51.26#ibcon#about to read 5, iclass 24, count 0 2006.252.07:40:51.26#ibcon#read 5, iclass 24, count 0 2006.252.07:40:51.26#ibcon#about to read 6, iclass 24, count 0 2006.252.07:40:51.26#ibcon#read 6, iclass 24, count 0 2006.252.07:40:51.26#ibcon#end of sib2, iclass 24, count 0 2006.252.07:40:51.26#ibcon#*mode == 0, iclass 24, count 0 2006.252.07:40:51.26#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.252.07:40:51.26#ibcon#[28=FRQ=03,656.99\r\n] 2006.252.07:40:51.26#ibcon#*before write, iclass 24, count 0 2006.252.07:40:51.26#ibcon#enter sib2, iclass 24, count 0 2006.252.07:40:51.26#ibcon#flushed, iclass 24, count 0 2006.252.07:40:51.26#ibcon#about to write, iclass 24, count 0 2006.252.07:40:51.26#ibcon#wrote, iclass 24, count 0 2006.252.07:40:51.26#ibcon#about to read 3, iclass 24, count 0 2006.252.07:40:51.30#ibcon#read 3, iclass 24, count 0 2006.252.07:40:51.30#ibcon#about to read 4, iclass 24, count 0 2006.252.07:40:51.30#ibcon#read 4, iclass 24, count 0 2006.252.07:40:51.30#ibcon#about to read 5, iclass 24, count 0 2006.252.07:40:51.30#ibcon#read 5, iclass 24, count 0 2006.252.07:40:51.30#ibcon#about to read 6, iclass 24, count 0 2006.252.07:40:51.30#ibcon#read 6, iclass 24, count 0 2006.252.07:40:51.30#ibcon#end of sib2, iclass 24, count 0 2006.252.07:40:51.30#ibcon#*after write, iclass 24, count 0 2006.252.07:40:51.30#ibcon#*before return 0, iclass 24, count 0 2006.252.07:40:51.30#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.252.07:40:51.30#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.252.07:40:51.30#ibcon#about to clear, iclass 24 cls_cnt 0 2006.252.07:40:51.30#ibcon#cleared, iclass 24 cls_cnt 0 2006.252.07:40:51.30$vc4f8/vb=3,4 2006.252.07:40:51.30#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.252.07:40:51.30#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.252.07:40:51.30#ibcon#ireg 11 cls_cnt 2 2006.252.07:40:51.30#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.252.07:40:51.36#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.252.07:40:51.36#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.252.07:40:51.36#ibcon#enter wrdev, iclass 26, count 2 2006.252.07:40:51.36#ibcon#first serial, iclass 26, count 2 2006.252.07:40:51.36#ibcon#enter sib2, iclass 26, count 2 2006.252.07:40:51.36#ibcon#flushed, iclass 26, count 2 2006.252.07:40:51.36#ibcon#about to write, iclass 26, count 2 2006.252.07:40:51.36#ibcon#wrote, iclass 26, count 2 2006.252.07:40:51.36#ibcon#about to read 3, iclass 26, count 2 2006.252.07:40:51.38#ibcon#read 3, iclass 26, count 2 2006.252.07:40:51.38#ibcon#about to read 4, iclass 26, count 2 2006.252.07:40:51.38#ibcon#read 4, iclass 26, count 2 2006.252.07:40:51.38#ibcon#about to read 5, iclass 26, count 2 2006.252.07:40:51.38#ibcon#read 5, iclass 26, count 2 2006.252.07:40:51.38#ibcon#about to read 6, iclass 26, count 2 2006.252.07:40:51.38#ibcon#read 6, iclass 26, count 2 2006.252.07:40:51.38#ibcon#end of sib2, iclass 26, count 2 2006.252.07:40:51.38#ibcon#*mode == 0, iclass 26, count 2 2006.252.07:40:51.38#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.252.07:40:51.38#ibcon#[27=AT03-04\r\n] 2006.252.07:40:51.38#ibcon#*before write, iclass 26, count 2 2006.252.07:40:51.38#ibcon#enter sib2, iclass 26, count 2 2006.252.07:40:51.38#ibcon#flushed, iclass 26, count 2 2006.252.07:40:51.38#ibcon#about to write, iclass 26, count 2 2006.252.07:40:51.38#ibcon#wrote, iclass 26, count 2 2006.252.07:40:51.38#ibcon#about to read 3, iclass 26, count 2 2006.252.07:40:51.41#ibcon#read 3, iclass 26, count 2 2006.252.07:40:51.41#ibcon#about to read 4, iclass 26, count 2 2006.252.07:40:51.41#ibcon#read 4, iclass 26, count 2 2006.252.07:40:51.41#ibcon#about to read 5, iclass 26, count 2 2006.252.07:40:51.41#ibcon#read 5, iclass 26, count 2 2006.252.07:40:51.41#ibcon#about to read 6, iclass 26, count 2 2006.252.07:40:51.41#ibcon#read 6, iclass 26, count 2 2006.252.07:40:51.41#ibcon#end of sib2, iclass 26, count 2 2006.252.07:40:51.41#ibcon#*after write, iclass 26, count 2 2006.252.07:40:51.41#ibcon#*before return 0, iclass 26, count 2 2006.252.07:40:51.41#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.252.07:40:51.41#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.252.07:40:51.41#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.252.07:40:51.41#ibcon#ireg 7 cls_cnt 0 2006.252.07:40:51.41#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.252.07:40:51.47#abcon#<5=/05 3.5 6.8 27.43 901011.3\r\n> 2006.252.07:40:51.49#abcon#{5=INTERFACE CLEAR} 2006.252.07:40:51.53#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.252.07:40:51.53#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.252.07:40:51.53#ibcon#enter wrdev, iclass 26, count 0 2006.252.07:40:51.53#ibcon#first serial, iclass 26, count 0 2006.252.07:40:51.53#ibcon#enter sib2, iclass 26, count 0 2006.252.07:40:51.53#ibcon#flushed, iclass 26, count 0 2006.252.07:40:51.53#ibcon#about to write, iclass 26, count 0 2006.252.07:40:51.53#ibcon#wrote, iclass 26, count 0 2006.252.07:40:51.53#ibcon#about to read 3, iclass 26, count 0 2006.252.07:40:51.55#ibcon#read 3, iclass 26, count 0 2006.252.07:40:51.55#ibcon#about to read 4, iclass 26, count 0 2006.252.07:40:51.55#ibcon#read 4, iclass 26, count 0 2006.252.07:40:51.55#ibcon#about to read 5, iclass 26, count 0 2006.252.07:40:51.55#ibcon#read 5, iclass 26, count 0 2006.252.07:40:51.55#ibcon#about to read 6, iclass 26, count 0 2006.252.07:40:51.55#ibcon#read 6, iclass 26, count 0 2006.252.07:40:51.55#ibcon#end of sib2, iclass 26, count 0 2006.252.07:40:51.55#ibcon#*mode == 0, iclass 26, count 0 2006.252.07:40:51.55#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.252.07:40:51.55#ibcon#[27=USB\r\n] 2006.252.07:40:51.55#ibcon#*before write, iclass 26, count 0 2006.252.07:40:51.55#ibcon#enter sib2, iclass 26, count 0 2006.252.07:40:51.55#ibcon#flushed, iclass 26, count 0 2006.252.07:40:51.55#ibcon#about to write, iclass 26, count 0 2006.252.07:40:51.55#ibcon#wrote, iclass 26, count 0 2006.252.07:40:51.55#ibcon#about to read 3, iclass 26, count 0 2006.252.07:40:51.55#abcon#[5=S1D000X0/0*\r\n] 2006.252.07:40:51.58#ibcon#read 3, iclass 26, count 0 2006.252.07:40:51.58#ibcon#about to read 4, iclass 26, count 0 2006.252.07:40:51.58#ibcon#read 4, iclass 26, count 0 2006.252.07:40:51.58#ibcon#about to read 5, iclass 26, count 0 2006.252.07:40:51.58#ibcon#read 5, iclass 26, count 0 2006.252.07:40:51.58#ibcon#about to read 6, iclass 26, count 0 2006.252.07:40:51.58#ibcon#read 6, iclass 26, count 0 2006.252.07:40:51.58#ibcon#end of sib2, iclass 26, count 0 2006.252.07:40:51.58#ibcon#*after write, iclass 26, count 0 2006.252.07:40:51.58#ibcon#*before return 0, iclass 26, count 0 2006.252.07:40:51.58#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.252.07:40:51.58#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.252.07:40:51.58#ibcon#about to clear, iclass 26 cls_cnt 0 2006.252.07:40:51.58#ibcon#cleared, iclass 26 cls_cnt 0 2006.252.07:40:51.58$vc4f8/vblo=4,712.99 2006.252.07:40:51.58#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.252.07:40:51.58#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.252.07:40:51.58#ibcon#ireg 17 cls_cnt 0 2006.252.07:40:51.58#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.252.07:40:51.58#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.252.07:40:51.58#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.252.07:40:51.58#ibcon#enter wrdev, iclass 32, count 0 2006.252.07:40:51.58#ibcon#first serial, iclass 32, count 0 2006.252.07:40:51.58#ibcon#enter sib2, iclass 32, count 0 2006.252.07:40:51.58#ibcon#flushed, iclass 32, count 0 2006.252.07:40:51.58#ibcon#about to write, iclass 32, count 0 2006.252.07:40:51.58#ibcon#wrote, iclass 32, count 0 2006.252.07:40:51.58#ibcon#about to read 3, iclass 32, count 0 2006.252.07:40:51.60#ibcon#read 3, iclass 32, count 0 2006.252.07:40:51.60#ibcon#about to read 4, iclass 32, count 0 2006.252.07:40:51.60#ibcon#read 4, iclass 32, count 0 2006.252.07:40:51.60#ibcon#about to read 5, iclass 32, count 0 2006.252.07:40:51.60#ibcon#read 5, iclass 32, count 0 2006.252.07:40:51.60#ibcon#about to read 6, iclass 32, count 0 2006.252.07:40:51.60#ibcon#read 6, iclass 32, count 0 2006.252.07:40:51.60#ibcon#end of sib2, iclass 32, count 0 2006.252.07:40:51.60#ibcon#*mode == 0, iclass 32, count 0 2006.252.07:40:51.60#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.252.07:40:51.60#ibcon#[28=FRQ=04,712.99\r\n] 2006.252.07:40:51.60#ibcon#*before write, iclass 32, count 0 2006.252.07:40:51.60#ibcon#enter sib2, iclass 32, count 0 2006.252.07:40:51.60#ibcon#flushed, iclass 32, count 0 2006.252.07:40:51.60#ibcon#about to write, iclass 32, count 0 2006.252.07:40:51.60#ibcon#wrote, iclass 32, count 0 2006.252.07:40:51.60#ibcon#about to read 3, iclass 32, count 0 2006.252.07:40:51.64#ibcon#read 3, iclass 32, count 0 2006.252.07:40:51.64#ibcon#about to read 4, iclass 32, count 0 2006.252.07:40:51.64#ibcon#read 4, iclass 32, count 0 2006.252.07:40:51.64#ibcon#about to read 5, iclass 32, count 0 2006.252.07:40:51.64#ibcon#read 5, iclass 32, count 0 2006.252.07:40:51.64#ibcon#about to read 6, iclass 32, count 0 2006.252.07:40:51.64#ibcon#read 6, iclass 32, count 0 2006.252.07:40:51.64#ibcon#end of sib2, iclass 32, count 0 2006.252.07:40:51.64#ibcon#*after write, iclass 32, count 0 2006.252.07:40:51.64#ibcon#*before return 0, iclass 32, count 0 2006.252.07:40:51.64#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.252.07:40:51.64#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.252.07:40:51.64#ibcon#about to clear, iclass 32 cls_cnt 0 2006.252.07:40:51.64#ibcon#cleared, iclass 32 cls_cnt 0 2006.252.07:40:51.64$vc4f8/vb=4,4 2006.252.07:40:51.64#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.252.07:40:51.64#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.252.07:40:51.64#ibcon#ireg 11 cls_cnt 2 2006.252.07:40:51.64#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.252.07:40:51.70#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.252.07:40:51.70#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.252.07:40:51.70#ibcon#enter wrdev, iclass 34, count 2 2006.252.07:40:51.70#ibcon#first serial, iclass 34, count 2 2006.252.07:40:51.70#ibcon#enter sib2, iclass 34, count 2 2006.252.07:40:51.70#ibcon#flushed, iclass 34, count 2 2006.252.07:40:51.70#ibcon#about to write, iclass 34, count 2 2006.252.07:40:51.70#ibcon#wrote, iclass 34, count 2 2006.252.07:40:51.70#ibcon#about to read 3, iclass 34, count 2 2006.252.07:40:51.72#ibcon#read 3, iclass 34, count 2 2006.252.07:40:51.72#ibcon#about to read 4, iclass 34, count 2 2006.252.07:40:51.72#ibcon#read 4, iclass 34, count 2 2006.252.07:40:51.72#ibcon#about to read 5, iclass 34, count 2 2006.252.07:40:51.72#ibcon#read 5, iclass 34, count 2 2006.252.07:40:51.72#ibcon#about to read 6, iclass 34, count 2 2006.252.07:40:51.72#ibcon#read 6, iclass 34, count 2 2006.252.07:40:51.72#ibcon#end of sib2, iclass 34, count 2 2006.252.07:40:51.72#ibcon#*mode == 0, iclass 34, count 2 2006.252.07:40:51.72#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.252.07:40:51.72#ibcon#[27=AT04-04\r\n] 2006.252.07:40:51.72#ibcon#*before write, iclass 34, count 2 2006.252.07:40:51.72#ibcon#enter sib2, iclass 34, count 2 2006.252.07:40:51.72#ibcon#flushed, iclass 34, count 2 2006.252.07:40:51.72#ibcon#about to write, iclass 34, count 2 2006.252.07:40:51.72#ibcon#wrote, iclass 34, count 2 2006.252.07:40:51.72#ibcon#about to read 3, iclass 34, count 2 2006.252.07:40:51.75#ibcon#read 3, iclass 34, count 2 2006.252.07:40:51.75#ibcon#about to read 4, iclass 34, count 2 2006.252.07:40:51.75#ibcon#read 4, iclass 34, count 2 2006.252.07:40:51.75#ibcon#about to read 5, iclass 34, count 2 2006.252.07:40:51.75#ibcon#read 5, iclass 34, count 2 2006.252.07:40:51.75#ibcon#about to read 6, iclass 34, count 2 2006.252.07:40:51.75#ibcon#read 6, iclass 34, count 2 2006.252.07:40:51.75#ibcon#end of sib2, iclass 34, count 2 2006.252.07:40:51.75#ibcon#*after write, iclass 34, count 2 2006.252.07:40:51.75#ibcon#*before return 0, iclass 34, count 2 2006.252.07:40:51.75#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.252.07:40:51.75#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.252.07:40:51.75#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.252.07:40:51.75#ibcon#ireg 7 cls_cnt 0 2006.252.07:40:51.75#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.252.07:40:51.87#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.252.07:40:51.87#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.252.07:40:51.87#ibcon#enter wrdev, iclass 34, count 0 2006.252.07:40:51.87#ibcon#first serial, iclass 34, count 0 2006.252.07:40:51.87#ibcon#enter sib2, iclass 34, count 0 2006.252.07:40:51.87#ibcon#flushed, iclass 34, count 0 2006.252.07:40:51.87#ibcon#about to write, iclass 34, count 0 2006.252.07:40:51.87#ibcon#wrote, iclass 34, count 0 2006.252.07:40:51.87#ibcon#about to read 3, iclass 34, count 0 2006.252.07:40:51.89#ibcon#read 3, iclass 34, count 0 2006.252.07:40:51.89#ibcon#about to read 4, iclass 34, count 0 2006.252.07:40:51.89#ibcon#read 4, iclass 34, count 0 2006.252.07:40:51.89#ibcon#about to read 5, iclass 34, count 0 2006.252.07:40:51.89#ibcon#read 5, iclass 34, count 0 2006.252.07:40:51.89#ibcon#about to read 6, iclass 34, count 0 2006.252.07:40:51.89#ibcon#read 6, iclass 34, count 0 2006.252.07:40:51.89#ibcon#end of sib2, iclass 34, count 0 2006.252.07:40:51.89#ibcon#*mode == 0, iclass 34, count 0 2006.252.07:40:51.89#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.252.07:40:51.89#ibcon#[27=USB\r\n] 2006.252.07:40:51.89#ibcon#*before write, iclass 34, count 0 2006.252.07:40:51.89#ibcon#enter sib2, iclass 34, count 0 2006.252.07:40:51.89#ibcon#flushed, iclass 34, count 0 2006.252.07:40:51.89#ibcon#about to write, iclass 34, count 0 2006.252.07:40:51.89#ibcon#wrote, iclass 34, count 0 2006.252.07:40:51.89#ibcon#about to read 3, iclass 34, count 0 2006.252.07:40:51.92#ibcon#read 3, iclass 34, count 0 2006.252.07:40:51.92#ibcon#about to read 4, iclass 34, count 0 2006.252.07:40:51.92#ibcon#read 4, iclass 34, count 0 2006.252.07:40:51.92#ibcon#about to read 5, iclass 34, count 0 2006.252.07:40:51.92#ibcon#read 5, iclass 34, count 0 2006.252.07:40:51.92#ibcon#about to read 6, iclass 34, count 0 2006.252.07:40:51.92#ibcon#read 6, iclass 34, count 0 2006.252.07:40:51.92#ibcon#end of sib2, iclass 34, count 0 2006.252.07:40:51.92#ibcon#*after write, iclass 34, count 0 2006.252.07:40:51.92#ibcon#*before return 0, iclass 34, count 0 2006.252.07:40:51.92#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.252.07:40:51.92#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.252.07:40:51.92#ibcon#about to clear, iclass 34 cls_cnt 0 2006.252.07:40:51.92#ibcon#cleared, iclass 34 cls_cnt 0 2006.252.07:40:51.92$vc4f8/vblo=5,744.99 2006.252.07:40:51.92#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.252.07:40:51.92#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.252.07:40:51.92#ibcon#ireg 17 cls_cnt 0 2006.252.07:40:51.92#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.252.07:40:51.92#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.252.07:40:51.92#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.252.07:40:51.92#ibcon#enter wrdev, iclass 36, count 0 2006.252.07:40:51.92#ibcon#first serial, iclass 36, count 0 2006.252.07:40:51.92#ibcon#enter sib2, iclass 36, count 0 2006.252.07:40:51.92#ibcon#flushed, iclass 36, count 0 2006.252.07:40:51.92#ibcon#about to write, iclass 36, count 0 2006.252.07:40:51.92#ibcon#wrote, iclass 36, count 0 2006.252.07:40:51.92#ibcon#about to read 3, iclass 36, count 0 2006.252.07:40:51.94#ibcon#read 3, iclass 36, count 0 2006.252.07:40:51.94#ibcon#about to read 4, iclass 36, count 0 2006.252.07:40:51.94#ibcon#read 4, iclass 36, count 0 2006.252.07:40:51.94#ibcon#about to read 5, iclass 36, count 0 2006.252.07:40:51.94#ibcon#read 5, iclass 36, count 0 2006.252.07:40:51.94#ibcon#about to read 6, iclass 36, count 0 2006.252.07:40:51.94#ibcon#read 6, iclass 36, count 0 2006.252.07:40:51.94#ibcon#end of sib2, iclass 36, count 0 2006.252.07:40:51.94#ibcon#*mode == 0, iclass 36, count 0 2006.252.07:40:51.94#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.252.07:40:51.94#ibcon#[28=FRQ=05,744.99\r\n] 2006.252.07:40:51.94#ibcon#*before write, iclass 36, count 0 2006.252.07:40:51.94#ibcon#enter sib2, iclass 36, count 0 2006.252.07:40:51.94#ibcon#flushed, iclass 36, count 0 2006.252.07:40:51.94#ibcon#about to write, iclass 36, count 0 2006.252.07:40:51.94#ibcon#wrote, iclass 36, count 0 2006.252.07:40:51.94#ibcon#about to read 3, iclass 36, count 0 2006.252.07:40:51.98#ibcon#read 3, iclass 36, count 0 2006.252.07:40:51.98#ibcon#about to read 4, iclass 36, count 0 2006.252.07:40:51.98#ibcon#read 4, iclass 36, count 0 2006.252.07:40:51.98#ibcon#about to read 5, iclass 36, count 0 2006.252.07:40:51.98#ibcon#read 5, iclass 36, count 0 2006.252.07:40:51.98#ibcon#about to read 6, iclass 36, count 0 2006.252.07:40:51.98#ibcon#read 6, iclass 36, count 0 2006.252.07:40:51.98#ibcon#end of sib2, iclass 36, count 0 2006.252.07:40:51.98#ibcon#*after write, iclass 36, count 0 2006.252.07:40:51.98#ibcon#*before return 0, iclass 36, count 0 2006.252.07:40:51.98#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.252.07:40:51.98#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.252.07:40:51.98#ibcon#about to clear, iclass 36 cls_cnt 0 2006.252.07:40:51.98#ibcon#cleared, iclass 36 cls_cnt 0 2006.252.07:40:51.98$vc4f8/vb=5,4 2006.252.07:40:51.98#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.252.07:40:51.98#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.252.07:40:51.98#ibcon#ireg 11 cls_cnt 2 2006.252.07:40:51.98#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.252.07:40:52.04#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.252.07:40:52.04#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.252.07:40:52.04#ibcon#enter wrdev, iclass 38, count 2 2006.252.07:40:52.04#ibcon#first serial, iclass 38, count 2 2006.252.07:40:52.04#ibcon#enter sib2, iclass 38, count 2 2006.252.07:40:52.04#ibcon#flushed, iclass 38, count 2 2006.252.07:40:52.04#ibcon#about to write, iclass 38, count 2 2006.252.07:40:52.04#ibcon#wrote, iclass 38, count 2 2006.252.07:40:52.04#ibcon#about to read 3, iclass 38, count 2 2006.252.07:40:52.06#ibcon#read 3, iclass 38, count 2 2006.252.07:40:52.06#ibcon#about to read 4, iclass 38, count 2 2006.252.07:40:52.06#ibcon#read 4, iclass 38, count 2 2006.252.07:40:52.06#ibcon#about to read 5, iclass 38, count 2 2006.252.07:40:52.06#ibcon#read 5, iclass 38, count 2 2006.252.07:40:52.06#ibcon#about to read 6, iclass 38, count 2 2006.252.07:40:52.06#ibcon#read 6, iclass 38, count 2 2006.252.07:40:52.06#ibcon#end of sib2, iclass 38, count 2 2006.252.07:40:52.06#ibcon#*mode == 0, iclass 38, count 2 2006.252.07:40:52.06#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.252.07:40:52.06#ibcon#[27=AT05-04\r\n] 2006.252.07:40:52.06#ibcon#*before write, iclass 38, count 2 2006.252.07:40:52.06#ibcon#enter sib2, iclass 38, count 2 2006.252.07:40:52.06#ibcon#flushed, iclass 38, count 2 2006.252.07:40:52.06#ibcon#about to write, iclass 38, count 2 2006.252.07:40:52.06#ibcon#wrote, iclass 38, count 2 2006.252.07:40:52.06#ibcon#about to read 3, iclass 38, count 2 2006.252.07:40:52.09#ibcon#read 3, iclass 38, count 2 2006.252.07:40:52.09#ibcon#about to read 4, iclass 38, count 2 2006.252.07:40:52.09#ibcon#read 4, iclass 38, count 2 2006.252.07:40:52.09#ibcon#about to read 5, iclass 38, count 2 2006.252.07:40:52.09#ibcon#read 5, iclass 38, count 2 2006.252.07:40:52.09#ibcon#about to read 6, iclass 38, count 2 2006.252.07:40:52.09#ibcon#read 6, iclass 38, count 2 2006.252.07:40:52.09#ibcon#end of sib2, iclass 38, count 2 2006.252.07:40:52.09#ibcon#*after write, iclass 38, count 2 2006.252.07:40:52.09#ibcon#*before return 0, iclass 38, count 2 2006.252.07:40:52.09#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.252.07:40:52.09#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.252.07:40:52.09#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.252.07:40:52.09#ibcon#ireg 7 cls_cnt 0 2006.252.07:40:52.09#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.252.07:40:52.21#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.252.07:40:52.21#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.252.07:40:52.21#ibcon#enter wrdev, iclass 38, count 0 2006.252.07:40:52.21#ibcon#first serial, iclass 38, count 0 2006.252.07:40:52.21#ibcon#enter sib2, iclass 38, count 0 2006.252.07:40:52.21#ibcon#flushed, iclass 38, count 0 2006.252.07:40:52.21#ibcon#about to write, iclass 38, count 0 2006.252.07:40:52.21#ibcon#wrote, iclass 38, count 0 2006.252.07:40:52.21#ibcon#about to read 3, iclass 38, count 0 2006.252.07:40:52.23#ibcon#read 3, iclass 38, count 0 2006.252.07:40:52.23#ibcon#about to read 4, iclass 38, count 0 2006.252.07:40:52.23#ibcon#read 4, iclass 38, count 0 2006.252.07:40:52.23#ibcon#about to read 5, iclass 38, count 0 2006.252.07:40:52.23#ibcon#read 5, iclass 38, count 0 2006.252.07:40:52.23#ibcon#about to read 6, iclass 38, count 0 2006.252.07:40:52.23#ibcon#read 6, iclass 38, count 0 2006.252.07:40:52.23#ibcon#end of sib2, iclass 38, count 0 2006.252.07:40:52.23#ibcon#*mode == 0, iclass 38, count 0 2006.252.07:40:52.23#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.252.07:40:52.23#ibcon#[27=USB\r\n] 2006.252.07:40:52.23#ibcon#*before write, iclass 38, count 0 2006.252.07:40:52.23#ibcon#enter sib2, iclass 38, count 0 2006.252.07:40:52.23#ibcon#flushed, iclass 38, count 0 2006.252.07:40:52.23#ibcon#about to write, iclass 38, count 0 2006.252.07:40:52.23#ibcon#wrote, iclass 38, count 0 2006.252.07:40:52.23#ibcon#about to read 3, iclass 38, count 0 2006.252.07:40:52.26#ibcon#read 3, iclass 38, count 0 2006.252.07:40:52.26#ibcon#about to read 4, iclass 38, count 0 2006.252.07:40:52.26#ibcon#read 4, iclass 38, count 0 2006.252.07:40:52.26#ibcon#about to read 5, iclass 38, count 0 2006.252.07:40:52.26#ibcon#read 5, iclass 38, count 0 2006.252.07:40:52.26#ibcon#about to read 6, iclass 38, count 0 2006.252.07:40:52.26#ibcon#read 6, iclass 38, count 0 2006.252.07:40:52.26#ibcon#end of sib2, iclass 38, count 0 2006.252.07:40:52.26#ibcon#*after write, iclass 38, count 0 2006.252.07:40:52.26#ibcon#*before return 0, iclass 38, count 0 2006.252.07:40:52.26#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.252.07:40:52.26#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.252.07:40:52.26#ibcon#about to clear, iclass 38 cls_cnt 0 2006.252.07:40:52.26#ibcon#cleared, iclass 38 cls_cnt 0 2006.252.07:40:52.26$vc4f8/vblo=6,752.99 2006.252.07:40:52.26#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.252.07:40:52.26#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.252.07:40:52.26#ibcon#ireg 17 cls_cnt 0 2006.252.07:40:52.26#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.252.07:40:52.26#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.252.07:40:52.26#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.252.07:40:52.26#ibcon#enter wrdev, iclass 40, count 0 2006.252.07:40:52.26#ibcon#first serial, iclass 40, count 0 2006.252.07:40:52.26#ibcon#enter sib2, iclass 40, count 0 2006.252.07:40:52.26#ibcon#flushed, iclass 40, count 0 2006.252.07:40:52.26#ibcon#about to write, iclass 40, count 0 2006.252.07:40:52.26#ibcon#wrote, iclass 40, count 0 2006.252.07:40:52.26#ibcon#about to read 3, iclass 40, count 0 2006.252.07:40:52.28#ibcon#read 3, iclass 40, count 0 2006.252.07:40:52.28#ibcon#about to read 4, iclass 40, count 0 2006.252.07:40:52.28#ibcon#read 4, iclass 40, count 0 2006.252.07:40:52.28#ibcon#about to read 5, iclass 40, count 0 2006.252.07:40:52.28#ibcon#read 5, iclass 40, count 0 2006.252.07:40:52.28#ibcon#about to read 6, iclass 40, count 0 2006.252.07:40:52.28#ibcon#read 6, iclass 40, count 0 2006.252.07:40:52.28#ibcon#end of sib2, iclass 40, count 0 2006.252.07:40:52.28#ibcon#*mode == 0, iclass 40, count 0 2006.252.07:40:52.28#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.252.07:40:52.28#ibcon#[28=FRQ=06,752.99\r\n] 2006.252.07:40:52.28#ibcon#*before write, iclass 40, count 0 2006.252.07:40:52.28#ibcon#enter sib2, iclass 40, count 0 2006.252.07:40:52.28#ibcon#flushed, iclass 40, count 0 2006.252.07:40:52.28#ibcon#about to write, iclass 40, count 0 2006.252.07:40:52.28#ibcon#wrote, iclass 40, count 0 2006.252.07:40:52.28#ibcon#about to read 3, iclass 40, count 0 2006.252.07:40:52.32#ibcon#read 3, iclass 40, count 0 2006.252.07:40:52.32#ibcon#about to read 4, iclass 40, count 0 2006.252.07:40:52.32#ibcon#read 4, iclass 40, count 0 2006.252.07:40:52.32#ibcon#about to read 5, iclass 40, count 0 2006.252.07:40:52.32#ibcon#read 5, iclass 40, count 0 2006.252.07:40:52.32#ibcon#about to read 6, iclass 40, count 0 2006.252.07:40:52.32#ibcon#read 6, iclass 40, count 0 2006.252.07:40:52.32#ibcon#end of sib2, iclass 40, count 0 2006.252.07:40:52.32#ibcon#*after write, iclass 40, count 0 2006.252.07:40:52.32#ibcon#*before return 0, iclass 40, count 0 2006.252.07:40:52.32#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.252.07:40:52.32#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.252.07:40:52.32#ibcon#about to clear, iclass 40 cls_cnt 0 2006.252.07:40:52.32#ibcon#cleared, iclass 40 cls_cnt 0 2006.252.07:40:52.32$vc4f8/vb=6,4 2006.252.07:40:52.32#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.252.07:40:52.32#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.252.07:40:52.32#ibcon#ireg 11 cls_cnt 2 2006.252.07:40:52.32#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.252.07:40:52.38#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.252.07:40:52.38#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.252.07:40:52.38#ibcon#enter wrdev, iclass 4, count 2 2006.252.07:40:52.38#ibcon#first serial, iclass 4, count 2 2006.252.07:40:52.38#ibcon#enter sib2, iclass 4, count 2 2006.252.07:40:52.38#ibcon#flushed, iclass 4, count 2 2006.252.07:40:52.38#ibcon#about to write, iclass 4, count 2 2006.252.07:40:52.38#ibcon#wrote, iclass 4, count 2 2006.252.07:40:52.38#ibcon#about to read 3, iclass 4, count 2 2006.252.07:40:52.40#ibcon#read 3, iclass 4, count 2 2006.252.07:40:52.40#ibcon#about to read 4, iclass 4, count 2 2006.252.07:40:52.40#ibcon#read 4, iclass 4, count 2 2006.252.07:40:52.40#ibcon#about to read 5, iclass 4, count 2 2006.252.07:40:52.40#ibcon#read 5, iclass 4, count 2 2006.252.07:40:52.40#ibcon#about to read 6, iclass 4, count 2 2006.252.07:40:52.40#ibcon#read 6, iclass 4, count 2 2006.252.07:40:52.40#ibcon#end of sib2, iclass 4, count 2 2006.252.07:40:52.40#ibcon#*mode == 0, iclass 4, count 2 2006.252.07:40:52.40#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.252.07:40:52.40#ibcon#[27=AT06-04\r\n] 2006.252.07:40:52.40#ibcon#*before write, iclass 4, count 2 2006.252.07:40:52.40#ibcon#enter sib2, iclass 4, count 2 2006.252.07:40:52.40#ibcon#flushed, iclass 4, count 2 2006.252.07:40:52.40#ibcon#about to write, iclass 4, count 2 2006.252.07:40:52.40#ibcon#wrote, iclass 4, count 2 2006.252.07:40:52.40#ibcon#about to read 3, iclass 4, count 2 2006.252.07:40:52.43#ibcon#read 3, iclass 4, count 2 2006.252.07:40:52.43#ibcon#about to read 4, iclass 4, count 2 2006.252.07:40:52.43#ibcon#read 4, iclass 4, count 2 2006.252.07:40:52.43#ibcon#about to read 5, iclass 4, count 2 2006.252.07:40:52.43#ibcon#read 5, iclass 4, count 2 2006.252.07:40:52.43#ibcon#about to read 6, iclass 4, count 2 2006.252.07:40:52.43#ibcon#read 6, iclass 4, count 2 2006.252.07:40:52.43#ibcon#end of sib2, iclass 4, count 2 2006.252.07:40:52.43#ibcon#*after write, iclass 4, count 2 2006.252.07:40:52.43#ibcon#*before return 0, iclass 4, count 2 2006.252.07:40:52.43#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.252.07:40:52.43#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.252.07:40:52.43#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.252.07:40:52.43#ibcon#ireg 7 cls_cnt 0 2006.252.07:40:52.43#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.252.07:40:52.55#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.252.07:40:52.55#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.252.07:40:52.55#ibcon#enter wrdev, iclass 4, count 0 2006.252.07:40:52.55#ibcon#first serial, iclass 4, count 0 2006.252.07:40:52.55#ibcon#enter sib2, iclass 4, count 0 2006.252.07:40:52.55#ibcon#flushed, iclass 4, count 0 2006.252.07:40:52.55#ibcon#about to write, iclass 4, count 0 2006.252.07:40:52.55#ibcon#wrote, iclass 4, count 0 2006.252.07:40:52.55#ibcon#about to read 3, iclass 4, count 0 2006.252.07:40:52.57#ibcon#read 3, iclass 4, count 0 2006.252.07:40:52.57#ibcon#about to read 4, iclass 4, count 0 2006.252.07:40:52.57#ibcon#read 4, iclass 4, count 0 2006.252.07:40:52.57#ibcon#about to read 5, iclass 4, count 0 2006.252.07:40:52.57#ibcon#read 5, iclass 4, count 0 2006.252.07:40:52.57#ibcon#about to read 6, iclass 4, count 0 2006.252.07:40:52.57#ibcon#read 6, iclass 4, count 0 2006.252.07:40:52.57#ibcon#end of sib2, iclass 4, count 0 2006.252.07:40:52.57#ibcon#*mode == 0, iclass 4, count 0 2006.252.07:40:52.57#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.252.07:40:52.57#ibcon#[27=USB\r\n] 2006.252.07:40:52.57#ibcon#*before write, iclass 4, count 0 2006.252.07:40:52.57#ibcon#enter sib2, iclass 4, count 0 2006.252.07:40:52.57#ibcon#flushed, iclass 4, count 0 2006.252.07:40:52.57#ibcon#about to write, iclass 4, count 0 2006.252.07:40:52.57#ibcon#wrote, iclass 4, count 0 2006.252.07:40:52.57#ibcon#about to read 3, iclass 4, count 0 2006.252.07:40:52.60#ibcon#read 3, iclass 4, count 0 2006.252.07:40:52.60#ibcon#about to read 4, iclass 4, count 0 2006.252.07:40:52.60#ibcon#read 4, iclass 4, count 0 2006.252.07:40:52.60#ibcon#about to read 5, iclass 4, count 0 2006.252.07:40:52.60#ibcon#read 5, iclass 4, count 0 2006.252.07:40:52.60#ibcon#about to read 6, iclass 4, count 0 2006.252.07:40:52.60#ibcon#read 6, iclass 4, count 0 2006.252.07:40:52.60#ibcon#end of sib2, iclass 4, count 0 2006.252.07:40:52.60#ibcon#*after write, iclass 4, count 0 2006.252.07:40:52.60#ibcon#*before return 0, iclass 4, count 0 2006.252.07:40:52.60#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.252.07:40:52.60#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.252.07:40:52.60#ibcon#about to clear, iclass 4 cls_cnt 0 2006.252.07:40:52.60#ibcon#cleared, iclass 4 cls_cnt 0 2006.252.07:40:52.60$vc4f8/vabw=wide 2006.252.07:40:52.60#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.252.07:40:52.60#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.252.07:40:52.60#ibcon#ireg 8 cls_cnt 0 2006.252.07:40:52.60#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.252.07:40:52.60#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.252.07:40:52.60#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.252.07:40:52.60#ibcon#enter wrdev, iclass 6, count 0 2006.252.07:40:52.60#ibcon#first serial, iclass 6, count 0 2006.252.07:40:52.60#ibcon#enter sib2, iclass 6, count 0 2006.252.07:40:52.60#ibcon#flushed, iclass 6, count 0 2006.252.07:40:52.60#ibcon#about to write, iclass 6, count 0 2006.252.07:40:52.60#ibcon#wrote, iclass 6, count 0 2006.252.07:40:52.60#ibcon#about to read 3, iclass 6, count 0 2006.252.07:40:52.63#ibcon#read 3, iclass 6, count 0 2006.252.07:40:52.63#ibcon#about to read 4, iclass 6, count 0 2006.252.07:40:52.63#ibcon#read 4, iclass 6, count 0 2006.252.07:40:52.63#ibcon#about to read 5, iclass 6, count 0 2006.252.07:40:52.63#ibcon#read 5, iclass 6, count 0 2006.252.07:40:52.63#ibcon#about to read 6, iclass 6, count 0 2006.252.07:40:52.63#ibcon#read 6, iclass 6, count 0 2006.252.07:40:52.63#ibcon#end of sib2, iclass 6, count 0 2006.252.07:40:52.63#ibcon#*mode == 0, iclass 6, count 0 2006.252.07:40:52.63#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.252.07:40:52.63#ibcon#[25=BW32\r\n] 2006.252.07:40:52.63#ibcon#*before write, iclass 6, count 0 2006.252.07:40:52.63#ibcon#enter sib2, iclass 6, count 0 2006.252.07:40:52.63#ibcon#flushed, iclass 6, count 0 2006.252.07:40:52.63#ibcon#about to write, iclass 6, count 0 2006.252.07:40:52.63#ibcon#wrote, iclass 6, count 0 2006.252.07:40:52.63#ibcon#about to read 3, iclass 6, count 0 2006.252.07:40:52.66#ibcon#read 3, iclass 6, count 0 2006.252.07:40:52.66#ibcon#about to read 4, iclass 6, count 0 2006.252.07:40:52.66#ibcon#read 4, iclass 6, count 0 2006.252.07:40:52.66#ibcon#about to read 5, iclass 6, count 0 2006.252.07:40:52.66#ibcon#read 5, iclass 6, count 0 2006.252.07:40:52.66#ibcon#about to read 6, iclass 6, count 0 2006.252.07:40:52.66#ibcon#read 6, iclass 6, count 0 2006.252.07:40:52.66#ibcon#end of sib2, iclass 6, count 0 2006.252.07:40:52.66#ibcon#*after write, iclass 6, count 0 2006.252.07:40:52.66#ibcon#*before return 0, iclass 6, count 0 2006.252.07:40:52.66#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.252.07:40:52.66#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.252.07:40:52.66#ibcon#about to clear, iclass 6 cls_cnt 0 2006.252.07:40:52.66#ibcon#cleared, iclass 6 cls_cnt 0 2006.252.07:40:52.66$vc4f8/vbbw=wide 2006.252.07:40:52.66#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.252.07:40:52.66#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.252.07:40:52.66#ibcon#ireg 8 cls_cnt 0 2006.252.07:40:52.66#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.252.07:40:52.72#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.252.07:40:52.72#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.252.07:40:52.72#ibcon#enter wrdev, iclass 10, count 0 2006.252.07:40:52.72#ibcon#first serial, iclass 10, count 0 2006.252.07:40:52.72#ibcon#enter sib2, iclass 10, count 0 2006.252.07:40:52.72#ibcon#flushed, iclass 10, count 0 2006.252.07:40:52.72#ibcon#about to write, iclass 10, count 0 2006.252.07:40:52.72#ibcon#wrote, iclass 10, count 0 2006.252.07:40:52.72#ibcon#about to read 3, iclass 10, count 0 2006.252.07:40:52.74#ibcon#read 3, iclass 10, count 0 2006.252.07:40:52.74#ibcon#about to read 4, iclass 10, count 0 2006.252.07:40:52.74#ibcon#read 4, iclass 10, count 0 2006.252.07:40:52.74#ibcon#about to read 5, iclass 10, count 0 2006.252.07:40:52.74#ibcon#read 5, iclass 10, count 0 2006.252.07:40:52.74#ibcon#about to read 6, iclass 10, count 0 2006.252.07:40:52.74#ibcon#read 6, iclass 10, count 0 2006.252.07:40:52.74#ibcon#end of sib2, iclass 10, count 0 2006.252.07:40:52.74#ibcon#*mode == 0, iclass 10, count 0 2006.252.07:40:52.74#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.252.07:40:52.74#ibcon#[27=BW32\r\n] 2006.252.07:40:52.74#ibcon#*before write, iclass 10, count 0 2006.252.07:40:52.74#ibcon#enter sib2, iclass 10, count 0 2006.252.07:40:52.74#ibcon#flushed, iclass 10, count 0 2006.252.07:40:52.74#ibcon#about to write, iclass 10, count 0 2006.252.07:40:52.74#ibcon#wrote, iclass 10, count 0 2006.252.07:40:52.74#ibcon#about to read 3, iclass 10, count 0 2006.252.07:40:52.77#ibcon#read 3, iclass 10, count 0 2006.252.07:40:52.77#ibcon#about to read 4, iclass 10, count 0 2006.252.07:40:52.77#ibcon#read 4, iclass 10, count 0 2006.252.07:40:52.77#ibcon#about to read 5, iclass 10, count 0 2006.252.07:40:52.77#ibcon#read 5, iclass 10, count 0 2006.252.07:40:52.77#ibcon#about to read 6, iclass 10, count 0 2006.252.07:40:52.77#ibcon#read 6, iclass 10, count 0 2006.252.07:40:52.77#ibcon#end of sib2, iclass 10, count 0 2006.252.07:40:52.77#ibcon#*after write, iclass 10, count 0 2006.252.07:40:52.77#ibcon#*before return 0, iclass 10, count 0 2006.252.07:40:52.77#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.252.07:40:52.77#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.252.07:40:52.77#ibcon#about to clear, iclass 10 cls_cnt 0 2006.252.07:40:52.77#ibcon#cleared, iclass 10 cls_cnt 0 2006.252.07:40:52.77$4f8m12a/ifd4f 2006.252.07:40:52.77$ifd4f/lo= 2006.252.07:40:52.77$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.252.07:40:52.77$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.252.07:40:52.78$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.252.07:40:52.78$ifd4f/patch= 2006.252.07:40:52.78$ifd4f/patch=lo1,a1,a2,a3,a4 2006.252.07:40:52.78$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.252.07:40:52.78$ifd4f/patch=lo3,a5,a6,a7,a8 2006.252.07:40:52.78$4f8m12a/"form=m,16.000,1:2 2006.252.07:40:52.78$4f8m12a/"tpicd 2006.252.07:40:52.78$4f8m12a/echo=off 2006.252.07:40:52.78$4f8m12a/xlog=off 2006.252.07:40:52.78:!2006.252.07:41:20 2006.252.07:41:03.14#trakl#Source acquired 2006.252.07:41:05.14#flagr#flagr/antenna,acquired 2006.252.07:41:20.01:preob 2006.252.07:41:21.14/onsource/TRACKING 2006.252.07:41:21.14:!2006.252.07:41:30 2006.252.07:41:30.00:data_valid=on 2006.252.07:41:30.00:midob 2006.252.07:41:30.14/onsource/TRACKING 2006.252.07:41:30.14/wx/27.43,1011.2,90 2006.252.07:41:30.27/cable/+6.4096E-03 2006.252.07:41:31.36/va/01,08,usb,yes,32,34 2006.252.07:41:31.36/va/02,07,usb,yes,32,33 2006.252.07:41:31.36/va/03,06,usb,yes,34,34 2006.252.07:41:31.36/va/04,07,usb,yes,32,35 2006.252.07:41:31.36/va/05,07,usb,yes,35,37 2006.252.07:41:31.36/va/06,07,usb,yes,31,31 2006.252.07:41:31.36/va/07,07,usb,yes,30,30 2006.252.07:41:31.36/va/08,07,usb,yes,33,32 2006.252.07:41:31.59/valo/01,532.99,yes,locked 2006.252.07:41:31.59/valo/02,572.99,yes,locked 2006.252.07:41:31.59/valo/03,672.99,yes,locked 2006.252.07:41:31.59/valo/04,832.99,yes,locked 2006.252.07:41:31.59/valo/05,652.99,yes,locked 2006.252.07:41:31.59/valo/06,772.99,yes,locked 2006.252.07:41:31.59/valo/07,832.99,yes,locked 2006.252.07:41:31.59/valo/08,852.99,yes,locked 2006.252.07:41:32.68/vb/01,04,usb,yes,30,29 2006.252.07:41:32.68/vb/02,05,usb,yes,28,29 2006.252.07:41:32.68/vb/03,04,usb,yes,28,32 2006.252.07:41:32.68/vb/04,04,usb,yes,29,29 2006.252.07:41:32.68/vb/05,04,usb,yes,28,32 2006.252.07:41:32.68/vb/06,04,usb,yes,28,31 2006.252.07:41:32.68/vb/07,04,usb,yes,31,31 2006.252.07:41:32.68/vb/08,04,usb,yes,28,32 2006.252.07:41:32.91/vblo/01,632.99,yes,locked 2006.252.07:41:32.91/vblo/02,640.99,yes,locked 2006.252.07:41:32.91/vblo/03,656.99,yes,locked 2006.252.07:41:32.91/vblo/04,712.99,yes,locked 2006.252.07:41:32.91/vblo/05,744.99,yes,locked 2006.252.07:41:32.91/vblo/06,752.99,yes,locked 2006.252.07:41:32.91/vblo/07,734.99,yes,locked 2006.252.07:41:32.91/vblo/08,744.99,yes,locked 2006.252.07:41:33.06/vabw/8 2006.252.07:41:33.21/vbbw/8 2006.252.07:41:33.30/xfe/off,on,14.0 2006.252.07:41:33.67/ifatt/23,28,28,28 2006.252.07:41:34.07/fmout-gps/S +4.77E-07 2006.252.07:41:34.12:!2006.252.07:42:30 2006.252.07:42:30.01:data_valid=off 2006.252.07:42:30.02:postob 2006.252.07:42:30.12/cable/+6.4102E-03 2006.252.07:42:30.13/wx/27.42,1011.2,90 2006.252.07:42:31.07/fmout-gps/S +4.79E-07 2006.252.07:42:31.08:scan_name=252-0743,k06252,60 2006.252.07:42:31.08:source=1418+546,141946.60,542314.8,2000.0,ccw 2006.252.07:42:31.14#flagr#flagr/antenna,new-source 2006.252.07:42:32.14:checkk5 2006.252.07:42:32.52/chk_autoobs//k5ts1/ autoobs is running! 2006.252.07:42:32.89/chk_autoobs//k5ts2/ autoobs is running! 2006.252.07:42:33.27/chk_autoobs//k5ts3/ autoobs is running! 2006.252.07:42:33.64/chk_autoobs//k5ts4/ autoobs is running! 2006.252.07:42:34.02/chk_obsdata//k5ts1/T2520741??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.07:42:34.39/chk_obsdata//k5ts2/T2520741??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.07:42:34.76/chk_obsdata//k5ts3/T2520741??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.07:42:35.14/chk_obsdata//k5ts4/T2520741??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.07:42:35.83/k5log//k5ts1_log_newline 2006.252.07:42:36.53/k5log//k5ts2_log_newline 2006.252.07:42:37.22/k5log//k5ts3_log_newline 2006.252.07:42:37.91/k5log//k5ts4_log_newline 2006.252.07:42:37.93/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.252.07:42:37.93:4f8m12a=1 2006.252.07:42:37.93$4f8m12a/echo=on 2006.252.07:42:37.93$4f8m12a/pcalon 2006.252.07:42:37.93$pcalon/"no phase cal control is implemented here 2006.252.07:42:37.93$4f8m12a/"tpicd=stop 2006.252.07:42:37.93$4f8m12a/vc4f8 2006.252.07:42:37.93$vc4f8/valo=1,532.99 2006.252.07:42:37.94#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.252.07:42:37.94#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.252.07:42:37.94#ibcon#ireg 17 cls_cnt 0 2006.252.07:42:37.94#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.252.07:42:37.94#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.252.07:42:37.94#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.252.07:42:37.94#ibcon#enter wrdev, iclass 17, count 0 2006.252.07:42:37.94#ibcon#first serial, iclass 17, count 0 2006.252.07:42:37.94#ibcon#enter sib2, iclass 17, count 0 2006.252.07:42:37.94#ibcon#flushed, iclass 17, count 0 2006.252.07:42:37.94#ibcon#about to write, iclass 17, count 0 2006.252.07:42:37.94#ibcon#wrote, iclass 17, count 0 2006.252.07:42:37.94#ibcon#about to read 3, iclass 17, count 0 2006.252.07:42:37.98#ibcon#read 3, iclass 17, count 0 2006.252.07:42:37.98#ibcon#about to read 4, iclass 17, count 0 2006.252.07:42:37.98#ibcon#read 4, iclass 17, count 0 2006.252.07:42:37.98#ibcon#about to read 5, iclass 17, count 0 2006.252.07:42:37.98#ibcon#read 5, iclass 17, count 0 2006.252.07:42:37.98#ibcon#about to read 6, iclass 17, count 0 2006.252.07:42:37.98#ibcon#read 6, iclass 17, count 0 2006.252.07:42:37.98#ibcon#end of sib2, iclass 17, count 0 2006.252.07:42:37.98#ibcon#*mode == 0, iclass 17, count 0 2006.252.07:42:37.98#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.252.07:42:37.98#ibcon#[26=FRQ=01,532.99\r\n] 2006.252.07:42:37.98#ibcon#*before write, iclass 17, count 0 2006.252.07:42:37.98#ibcon#enter sib2, iclass 17, count 0 2006.252.07:42:37.98#ibcon#flushed, iclass 17, count 0 2006.252.07:42:37.98#ibcon#about to write, iclass 17, count 0 2006.252.07:42:37.98#ibcon#wrote, iclass 17, count 0 2006.252.07:42:37.98#ibcon#about to read 3, iclass 17, count 0 2006.252.07:42:38.02#ibcon#read 3, iclass 17, count 0 2006.252.07:42:38.02#ibcon#about to read 4, iclass 17, count 0 2006.252.07:42:38.02#ibcon#read 4, iclass 17, count 0 2006.252.07:42:38.02#ibcon#about to read 5, iclass 17, count 0 2006.252.07:42:38.02#ibcon#read 5, iclass 17, count 0 2006.252.07:42:38.02#ibcon#about to read 6, iclass 17, count 0 2006.252.07:42:38.02#ibcon#read 6, iclass 17, count 0 2006.252.07:42:38.02#ibcon#end of sib2, iclass 17, count 0 2006.252.07:42:38.02#ibcon#*after write, iclass 17, count 0 2006.252.07:42:38.02#ibcon#*before return 0, iclass 17, count 0 2006.252.07:42:38.02#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.252.07:42:38.02#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.252.07:42:38.02#ibcon#about to clear, iclass 17 cls_cnt 0 2006.252.07:42:38.02#ibcon#cleared, iclass 17 cls_cnt 0 2006.252.07:42:38.02$vc4f8/va=1,8 2006.252.07:42:38.02#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.252.07:42:38.02#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.252.07:42:38.02#ibcon#ireg 11 cls_cnt 2 2006.252.07:42:38.02#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.252.07:42:38.02#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.252.07:42:38.02#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.252.07:42:38.02#ibcon#enter wrdev, iclass 19, count 2 2006.252.07:42:38.02#ibcon#first serial, iclass 19, count 2 2006.252.07:42:38.02#ibcon#enter sib2, iclass 19, count 2 2006.252.07:42:38.02#ibcon#flushed, iclass 19, count 2 2006.252.07:42:38.02#ibcon#about to write, iclass 19, count 2 2006.252.07:42:38.02#ibcon#wrote, iclass 19, count 2 2006.252.07:42:38.02#ibcon#about to read 3, iclass 19, count 2 2006.252.07:42:38.05#ibcon#read 3, iclass 19, count 2 2006.252.07:42:38.05#ibcon#about to read 4, iclass 19, count 2 2006.252.07:42:38.05#ibcon#read 4, iclass 19, count 2 2006.252.07:42:38.05#ibcon#about to read 5, iclass 19, count 2 2006.252.07:42:38.05#ibcon#read 5, iclass 19, count 2 2006.252.07:42:38.05#ibcon#about to read 6, iclass 19, count 2 2006.252.07:42:38.05#ibcon#read 6, iclass 19, count 2 2006.252.07:42:38.05#ibcon#end of sib2, iclass 19, count 2 2006.252.07:42:38.05#ibcon#*mode == 0, iclass 19, count 2 2006.252.07:42:38.05#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.252.07:42:38.05#ibcon#[25=AT01-08\r\n] 2006.252.07:42:38.05#ibcon#*before write, iclass 19, count 2 2006.252.07:42:38.05#ibcon#enter sib2, iclass 19, count 2 2006.252.07:42:38.05#ibcon#flushed, iclass 19, count 2 2006.252.07:42:38.05#ibcon#about to write, iclass 19, count 2 2006.252.07:42:38.05#ibcon#wrote, iclass 19, count 2 2006.252.07:42:38.05#ibcon#about to read 3, iclass 19, count 2 2006.252.07:42:38.08#ibcon#read 3, iclass 19, count 2 2006.252.07:42:38.08#ibcon#about to read 4, iclass 19, count 2 2006.252.07:42:38.08#ibcon#read 4, iclass 19, count 2 2006.252.07:42:38.08#ibcon#about to read 5, iclass 19, count 2 2006.252.07:42:38.08#ibcon#read 5, iclass 19, count 2 2006.252.07:42:38.08#ibcon#about to read 6, iclass 19, count 2 2006.252.07:42:38.08#ibcon#read 6, iclass 19, count 2 2006.252.07:42:38.08#ibcon#end of sib2, iclass 19, count 2 2006.252.07:42:38.08#ibcon#*after write, iclass 19, count 2 2006.252.07:42:38.08#ibcon#*before return 0, iclass 19, count 2 2006.252.07:42:38.08#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.252.07:42:38.08#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.252.07:42:38.08#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.252.07:42:38.08#ibcon#ireg 7 cls_cnt 0 2006.252.07:42:38.08#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.252.07:42:38.19#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.252.07:42:38.19#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.252.07:42:38.19#ibcon#enter wrdev, iclass 19, count 0 2006.252.07:42:38.19#ibcon#first serial, iclass 19, count 0 2006.252.07:42:38.19#ibcon#enter sib2, iclass 19, count 0 2006.252.07:42:38.19#ibcon#flushed, iclass 19, count 0 2006.252.07:42:38.19#ibcon#about to write, iclass 19, count 0 2006.252.07:42:38.19#ibcon#wrote, iclass 19, count 0 2006.252.07:42:38.19#ibcon#about to read 3, iclass 19, count 0 2006.252.07:42:38.21#ibcon#read 3, iclass 19, count 0 2006.252.07:42:38.21#ibcon#about to read 4, iclass 19, count 0 2006.252.07:42:38.21#ibcon#read 4, iclass 19, count 0 2006.252.07:42:38.21#ibcon#about to read 5, iclass 19, count 0 2006.252.07:42:38.21#ibcon#read 5, iclass 19, count 0 2006.252.07:42:38.21#ibcon#about to read 6, iclass 19, count 0 2006.252.07:42:38.21#ibcon#read 6, iclass 19, count 0 2006.252.07:42:38.21#ibcon#end of sib2, iclass 19, count 0 2006.252.07:42:38.21#ibcon#*mode == 0, iclass 19, count 0 2006.252.07:42:38.21#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.252.07:42:38.21#ibcon#[25=USB\r\n] 2006.252.07:42:38.21#ibcon#*before write, iclass 19, count 0 2006.252.07:42:38.21#ibcon#enter sib2, iclass 19, count 0 2006.252.07:42:38.21#ibcon#flushed, iclass 19, count 0 2006.252.07:42:38.21#ibcon#about to write, iclass 19, count 0 2006.252.07:42:38.21#ibcon#wrote, iclass 19, count 0 2006.252.07:42:38.21#ibcon#about to read 3, iclass 19, count 0 2006.252.07:42:38.24#ibcon#read 3, iclass 19, count 0 2006.252.07:42:38.24#ibcon#about to read 4, iclass 19, count 0 2006.252.07:42:38.24#ibcon#read 4, iclass 19, count 0 2006.252.07:42:38.24#ibcon#about to read 5, iclass 19, count 0 2006.252.07:42:38.24#ibcon#read 5, iclass 19, count 0 2006.252.07:42:38.24#ibcon#about to read 6, iclass 19, count 0 2006.252.07:42:38.24#ibcon#read 6, iclass 19, count 0 2006.252.07:42:38.24#ibcon#end of sib2, iclass 19, count 0 2006.252.07:42:38.24#ibcon#*after write, iclass 19, count 0 2006.252.07:42:38.24#ibcon#*before return 0, iclass 19, count 0 2006.252.07:42:38.24#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.252.07:42:38.24#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.252.07:42:38.24#ibcon#about to clear, iclass 19 cls_cnt 0 2006.252.07:42:38.24#ibcon#cleared, iclass 19 cls_cnt 0 2006.252.07:42:38.24$vc4f8/valo=2,572.99 2006.252.07:42:38.24#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.252.07:42:38.24#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.252.07:42:38.24#ibcon#ireg 17 cls_cnt 0 2006.252.07:42:38.24#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.252.07:42:38.24#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.252.07:42:38.24#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.252.07:42:38.24#ibcon#enter wrdev, iclass 21, count 0 2006.252.07:42:38.24#ibcon#first serial, iclass 21, count 0 2006.252.07:42:38.24#ibcon#enter sib2, iclass 21, count 0 2006.252.07:42:38.24#ibcon#flushed, iclass 21, count 0 2006.252.07:42:38.24#ibcon#about to write, iclass 21, count 0 2006.252.07:42:38.24#ibcon#wrote, iclass 21, count 0 2006.252.07:42:38.24#ibcon#about to read 3, iclass 21, count 0 2006.252.07:42:38.26#ibcon#read 3, iclass 21, count 0 2006.252.07:42:38.26#ibcon#about to read 4, iclass 21, count 0 2006.252.07:42:38.26#ibcon#read 4, iclass 21, count 0 2006.252.07:42:38.26#ibcon#about to read 5, iclass 21, count 0 2006.252.07:42:38.26#ibcon#read 5, iclass 21, count 0 2006.252.07:42:38.26#ibcon#about to read 6, iclass 21, count 0 2006.252.07:42:38.26#ibcon#read 6, iclass 21, count 0 2006.252.07:42:38.26#ibcon#end of sib2, iclass 21, count 0 2006.252.07:42:38.26#ibcon#*mode == 0, iclass 21, count 0 2006.252.07:42:38.26#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.252.07:42:38.26#ibcon#[26=FRQ=02,572.99\r\n] 2006.252.07:42:38.26#ibcon#*before write, iclass 21, count 0 2006.252.07:42:38.26#ibcon#enter sib2, iclass 21, count 0 2006.252.07:42:38.26#ibcon#flushed, iclass 21, count 0 2006.252.07:42:38.26#ibcon#about to write, iclass 21, count 0 2006.252.07:42:38.26#ibcon#wrote, iclass 21, count 0 2006.252.07:42:38.26#ibcon#about to read 3, iclass 21, count 0 2006.252.07:42:38.30#ibcon#read 3, iclass 21, count 0 2006.252.07:42:38.30#ibcon#about to read 4, iclass 21, count 0 2006.252.07:42:38.30#ibcon#read 4, iclass 21, count 0 2006.252.07:42:38.30#ibcon#about to read 5, iclass 21, count 0 2006.252.07:42:38.30#ibcon#read 5, iclass 21, count 0 2006.252.07:42:38.30#ibcon#about to read 6, iclass 21, count 0 2006.252.07:42:38.30#ibcon#read 6, iclass 21, count 0 2006.252.07:42:38.30#ibcon#end of sib2, iclass 21, count 0 2006.252.07:42:38.30#ibcon#*after write, iclass 21, count 0 2006.252.07:42:38.30#ibcon#*before return 0, iclass 21, count 0 2006.252.07:42:38.30#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.252.07:42:38.30#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.252.07:42:38.30#ibcon#about to clear, iclass 21 cls_cnt 0 2006.252.07:42:38.30#ibcon#cleared, iclass 21 cls_cnt 0 2006.252.07:42:38.30$vc4f8/va=2,7 2006.252.07:42:38.30#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.252.07:42:38.30#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.252.07:42:38.30#ibcon#ireg 11 cls_cnt 2 2006.252.07:42:38.30#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.252.07:42:38.37#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.252.07:42:38.37#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.252.07:42:38.37#ibcon#enter wrdev, iclass 23, count 2 2006.252.07:42:38.37#ibcon#first serial, iclass 23, count 2 2006.252.07:42:38.37#ibcon#enter sib2, iclass 23, count 2 2006.252.07:42:38.37#ibcon#flushed, iclass 23, count 2 2006.252.07:42:38.37#ibcon#about to write, iclass 23, count 2 2006.252.07:42:38.37#ibcon#wrote, iclass 23, count 2 2006.252.07:42:38.37#ibcon#about to read 3, iclass 23, count 2 2006.252.07:42:38.38#ibcon#read 3, iclass 23, count 2 2006.252.07:42:38.38#ibcon#about to read 4, iclass 23, count 2 2006.252.07:42:38.38#ibcon#read 4, iclass 23, count 2 2006.252.07:42:38.38#ibcon#about to read 5, iclass 23, count 2 2006.252.07:42:38.38#ibcon#read 5, iclass 23, count 2 2006.252.07:42:38.38#ibcon#about to read 6, iclass 23, count 2 2006.252.07:42:38.38#ibcon#read 6, iclass 23, count 2 2006.252.07:42:38.38#ibcon#end of sib2, iclass 23, count 2 2006.252.07:42:38.38#ibcon#*mode == 0, iclass 23, count 2 2006.252.07:42:38.38#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.252.07:42:38.38#ibcon#[25=AT02-07\r\n] 2006.252.07:42:38.38#ibcon#*before write, iclass 23, count 2 2006.252.07:42:38.38#ibcon#enter sib2, iclass 23, count 2 2006.252.07:42:38.38#ibcon#flushed, iclass 23, count 2 2006.252.07:42:38.38#ibcon#about to write, iclass 23, count 2 2006.252.07:42:38.38#ibcon#wrote, iclass 23, count 2 2006.252.07:42:38.38#ibcon#about to read 3, iclass 23, count 2 2006.252.07:42:38.41#ibcon#read 3, iclass 23, count 2 2006.252.07:42:38.41#ibcon#about to read 4, iclass 23, count 2 2006.252.07:42:38.41#ibcon#read 4, iclass 23, count 2 2006.252.07:42:38.41#ibcon#about to read 5, iclass 23, count 2 2006.252.07:42:38.41#ibcon#read 5, iclass 23, count 2 2006.252.07:42:38.41#ibcon#about to read 6, iclass 23, count 2 2006.252.07:42:38.41#ibcon#read 6, iclass 23, count 2 2006.252.07:42:38.41#ibcon#end of sib2, iclass 23, count 2 2006.252.07:42:38.41#ibcon#*after write, iclass 23, count 2 2006.252.07:42:38.41#ibcon#*before return 0, iclass 23, count 2 2006.252.07:42:38.41#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.252.07:42:38.41#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.252.07:42:38.41#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.252.07:42:38.41#ibcon#ireg 7 cls_cnt 0 2006.252.07:42:38.41#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.252.07:42:38.53#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.252.07:42:38.53#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.252.07:42:38.53#ibcon#enter wrdev, iclass 23, count 0 2006.252.07:42:38.53#ibcon#first serial, iclass 23, count 0 2006.252.07:42:38.53#ibcon#enter sib2, iclass 23, count 0 2006.252.07:42:38.53#ibcon#flushed, iclass 23, count 0 2006.252.07:42:38.53#ibcon#about to write, iclass 23, count 0 2006.252.07:42:38.53#ibcon#wrote, iclass 23, count 0 2006.252.07:42:38.53#ibcon#about to read 3, iclass 23, count 0 2006.252.07:42:38.55#ibcon#read 3, iclass 23, count 0 2006.252.07:42:38.55#ibcon#about to read 4, iclass 23, count 0 2006.252.07:42:38.55#ibcon#read 4, iclass 23, count 0 2006.252.07:42:38.55#ibcon#about to read 5, iclass 23, count 0 2006.252.07:42:38.55#ibcon#read 5, iclass 23, count 0 2006.252.07:42:38.55#ibcon#about to read 6, iclass 23, count 0 2006.252.07:42:38.55#ibcon#read 6, iclass 23, count 0 2006.252.07:42:38.55#ibcon#end of sib2, iclass 23, count 0 2006.252.07:42:38.55#ibcon#*mode == 0, iclass 23, count 0 2006.252.07:42:38.55#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.252.07:42:38.55#ibcon#[25=USB\r\n] 2006.252.07:42:38.55#ibcon#*before write, iclass 23, count 0 2006.252.07:42:38.55#ibcon#enter sib2, iclass 23, count 0 2006.252.07:42:38.55#ibcon#flushed, iclass 23, count 0 2006.252.07:42:38.55#ibcon#about to write, iclass 23, count 0 2006.252.07:42:38.55#ibcon#wrote, iclass 23, count 0 2006.252.07:42:38.55#ibcon#about to read 3, iclass 23, count 0 2006.252.07:42:38.58#ibcon#read 3, iclass 23, count 0 2006.252.07:42:38.58#ibcon#about to read 4, iclass 23, count 0 2006.252.07:42:38.58#ibcon#read 4, iclass 23, count 0 2006.252.07:42:38.58#ibcon#about to read 5, iclass 23, count 0 2006.252.07:42:38.58#ibcon#read 5, iclass 23, count 0 2006.252.07:42:38.58#ibcon#about to read 6, iclass 23, count 0 2006.252.07:42:38.58#ibcon#read 6, iclass 23, count 0 2006.252.07:42:38.58#ibcon#end of sib2, iclass 23, count 0 2006.252.07:42:38.58#ibcon#*after write, iclass 23, count 0 2006.252.07:42:38.58#ibcon#*before return 0, iclass 23, count 0 2006.252.07:42:38.58#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.252.07:42:38.58#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.252.07:42:38.58#ibcon#about to clear, iclass 23 cls_cnt 0 2006.252.07:42:38.58#ibcon#cleared, iclass 23 cls_cnt 0 2006.252.07:42:38.58$vc4f8/valo=3,672.99 2006.252.07:42:38.58#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.252.07:42:38.58#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.252.07:42:38.58#ibcon#ireg 17 cls_cnt 0 2006.252.07:42:38.58#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.252.07:42:38.58#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.252.07:42:38.58#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.252.07:42:38.58#ibcon#enter wrdev, iclass 25, count 0 2006.252.07:42:38.58#ibcon#first serial, iclass 25, count 0 2006.252.07:42:38.58#ibcon#enter sib2, iclass 25, count 0 2006.252.07:42:38.58#ibcon#flushed, iclass 25, count 0 2006.252.07:42:38.58#ibcon#about to write, iclass 25, count 0 2006.252.07:42:38.58#ibcon#wrote, iclass 25, count 0 2006.252.07:42:38.58#ibcon#about to read 3, iclass 25, count 0 2006.252.07:42:38.60#ibcon#read 3, iclass 25, count 0 2006.252.07:42:38.60#ibcon#about to read 4, iclass 25, count 0 2006.252.07:42:38.60#ibcon#read 4, iclass 25, count 0 2006.252.07:42:38.60#ibcon#about to read 5, iclass 25, count 0 2006.252.07:42:38.60#ibcon#read 5, iclass 25, count 0 2006.252.07:42:38.60#ibcon#about to read 6, iclass 25, count 0 2006.252.07:42:38.60#ibcon#read 6, iclass 25, count 0 2006.252.07:42:38.60#ibcon#end of sib2, iclass 25, count 0 2006.252.07:42:38.60#ibcon#*mode == 0, iclass 25, count 0 2006.252.07:42:38.60#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.252.07:42:38.60#ibcon#[26=FRQ=03,672.99\r\n] 2006.252.07:42:38.60#ibcon#*before write, iclass 25, count 0 2006.252.07:42:38.60#ibcon#enter sib2, iclass 25, count 0 2006.252.07:42:38.60#ibcon#flushed, iclass 25, count 0 2006.252.07:42:38.60#ibcon#about to write, iclass 25, count 0 2006.252.07:42:38.60#ibcon#wrote, iclass 25, count 0 2006.252.07:42:38.60#ibcon#about to read 3, iclass 25, count 0 2006.252.07:42:38.64#ibcon#read 3, iclass 25, count 0 2006.252.07:42:38.64#ibcon#about to read 4, iclass 25, count 0 2006.252.07:42:38.64#ibcon#read 4, iclass 25, count 0 2006.252.07:42:38.64#ibcon#about to read 5, iclass 25, count 0 2006.252.07:42:38.64#ibcon#read 5, iclass 25, count 0 2006.252.07:42:38.64#ibcon#about to read 6, iclass 25, count 0 2006.252.07:42:38.64#ibcon#read 6, iclass 25, count 0 2006.252.07:42:38.64#ibcon#end of sib2, iclass 25, count 0 2006.252.07:42:38.64#ibcon#*after write, iclass 25, count 0 2006.252.07:42:38.64#ibcon#*before return 0, iclass 25, count 0 2006.252.07:42:38.64#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.252.07:42:38.64#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.252.07:42:38.64#ibcon#about to clear, iclass 25 cls_cnt 0 2006.252.07:42:38.64#ibcon#cleared, iclass 25 cls_cnt 0 2006.252.07:42:38.64$vc4f8/va=3,6 2006.252.07:42:38.64#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.252.07:42:38.64#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.252.07:42:38.64#ibcon#ireg 11 cls_cnt 2 2006.252.07:42:38.64#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.252.07:42:38.71#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.252.07:42:38.71#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.252.07:42:38.71#ibcon#enter wrdev, iclass 27, count 2 2006.252.07:42:38.71#ibcon#first serial, iclass 27, count 2 2006.252.07:42:38.71#ibcon#enter sib2, iclass 27, count 2 2006.252.07:42:38.71#ibcon#flushed, iclass 27, count 2 2006.252.07:42:38.71#ibcon#about to write, iclass 27, count 2 2006.252.07:42:38.71#ibcon#wrote, iclass 27, count 2 2006.252.07:42:38.71#ibcon#about to read 3, iclass 27, count 2 2006.252.07:42:38.72#ibcon#read 3, iclass 27, count 2 2006.252.07:42:38.72#ibcon#about to read 4, iclass 27, count 2 2006.252.07:42:38.72#ibcon#read 4, iclass 27, count 2 2006.252.07:42:38.72#ibcon#about to read 5, iclass 27, count 2 2006.252.07:42:38.72#ibcon#read 5, iclass 27, count 2 2006.252.07:42:38.72#ibcon#about to read 6, iclass 27, count 2 2006.252.07:42:38.72#ibcon#read 6, iclass 27, count 2 2006.252.07:42:38.72#ibcon#end of sib2, iclass 27, count 2 2006.252.07:42:38.72#ibcon#*mode == 0, iclass 27, count 2 2006.252.07:42:38.72#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.252.07:42:38.72#ibcon#[25=AT03-06\r\n] 2006.252.07:42:38.72#ibcon#*before write, iclass 27, count 2 2006.252.07:42:38.72#ibcon#enter sib2, iclass 27, count 2 2006.252.07:42:38.72#ibcon#flushed, iclass 27, count 2 2006.252.07:42:38.72#ibcon#about to write, iclass 27, count 2 2006.252.07:42:38.72#ibcon#wrote, iclass 27, count 2 2006.252.07:42:38.72#ibcon#about to read 3, iclass 27, count 2 2006.252.07:42:38.75#ibcon#read 3, iclass 27, count 2 2006.252.07:42:38.75#ibcon#about to read 4, iclass 27, count 2 2006.252.07:42:38.75#ibcon#read 4, iclass 27, count 2 2006.252.07:42:38.75#ibcon#about to read 5, iclass 27, count 2 2006.252.07:42:38.75#ibcon#read 5, iclass 27, count 2 2006.252.07:42:38.75#ibcon#about to read 6, iclass 27, count 2 2006.252.07:42:38.75#ibcon#read 6, iclass 27, count 2 2006.252.07:42:38.75#ibcon#end of sib2, iclass 27, count 2 2006.252.07:42:38.75#ibcon#*after write, iclass 27, count 2 2006.252.07:42:38.75#ibcon#*before return 0, iclass 27, count 2 2006.252.07:42:38.75#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.252.07:42:38.75#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.252.07:42:38.75#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.252.07:42:38.75#ibcon#ireg 7 cls_cnt 0 2006.252.07:42:38.75#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.252.07:42:38.87#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.252.07:42:38.87#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.252.07:42:38.87#ibcon#enter wrdev, iclass 27, count 0 2006.252.07:42:38.87#ibcon#first serial, iclass 27, count 0 2006.252.07:42:38.87#ibcon#enter sib2, iclass 27, count 0 2006.252.07:42:38.87#ibcon#flushed, iclass 27, count 0 2006.252.07:42:38.87#ibcon#about to write, iclass 27, count 0 2006.252.07:42:38.87#ibcon#wrote, iclass 27, count 0 2006.252.07:42:38.87#ibcon#about to read 3, iclass 27, count 0 2006.252.07:42:38.89#ibcon#read 3, iclass 27, count 0 2006.252.07:42:38.89#ibcon#about to read 4, iclass 27, count 0 2006.252.07:42:38.89#ibcon#read 4, iclass 27, count 0 2006.252.07:42:38.89#ibcon#about to read 5, iclass 27, count 0 2006.252.07:42:38.89#ibcon#read 5, iclass 27, count 0 2006.252.07:42:38.89#ibcon#about to read 6, iclass 27, count 0 2006.252.07:42:38.89#ibcon#read 6, iclass 27, count 0 2006.252.07:42:38.89#ibcon#end of sib2, iclass 27, count 0 2006.252.07:42:38.89#ibcon#*mode == 0, iclass 27, count 0 2006.252.07:42:38.89#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.252.07:42:38.89#ibcon#[25=USB\r\n] 2006.252.07:42:38.89#ibcon#*before write, iclass 27, count 0 2006.252.07:42:38.89#ibcon#enter sib2, iclass 27, count 0 2006.252.07:42:38.89#ibcon#flushed, iclass 27, count 0 2006.252.07:42:38.89#ibcon#about to write, iclass 27, count 0 2006.252.07:42:38.89#ibcon#wrote, iclass 27, count 0 2006.252.07:42:38.89#ibcon#about to read 3, iclass 27, count 0 2006.252.07:42:38.92#ibcon#read 3, iclass 27, count 0 2006.252.07:42:38.92#ibcon#about to read 4, iclass 27, count 0 2006.252.07:42:38.92#ibcon#read 4, iclass 27, count 0 2006.252.07:42:38.92#ibcon#about to read 5, iclass 27, count 0 2006.252.07:42:38.92#ibcon#read 5, iclass 27, count 0 2006.252.07:42:38.92#ibcon#about to read 6, iclass 27, count 0 2006.252.07:42:38.92#ibcon#read 6, iclass 27, count 0 2006.252.07:42:38.92#ibcon#end of sib2, iclass 27, count 0 2006.252.07:42:38.92#ibcon#*after write, iclass 27, count 0 2006.252.07:42:38.92#ibcon#*before return 0, iclass 27, count 0 2006.252.07:42:38.92#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.252.07:42:38.92#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.252.07:42:38.92#ibcon#about to clear, iclass 27 cls_cnt 0 2006.252.07:42:38.92#ibcon#cleared, iclass 27 cls_cnt 0 2006.252.07:42:38.92$vc4f8/valo=4,832.99 2006.252.07:42:38.92#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.252.07:42:38.92#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.252.07:42:38.92#ibcon#ireg 17 cls_cnt 0 2006.252.07:42:38.92#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.252.07:42:38.92#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.252.07:42:38.92#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.252.07:42:38.92#ibcon#enter wrdev, iclass 29, count 0 2006.252.07:42:38.92#ibcon#first serial, iclass 29, count 0 2006.252.07:42:38.92#ibcon#enter sib2, iclass 29, count 0 2006.252.07:42:38.92#ibcon#flushed, iclass 29, count 0 2006.252.07:42:38.92#ibcon#about to write, iclass 29, count 0 2006.252.07:42:38.92#ibcon#wrote, iclass 29, count 0 2006.252.07:42:38.92#ibcon#about to read 3, iclass 29, count 0 2006.252.07:42:38.94#ibcon#read 3, iclass 29, count 0 2006.252.07:42:38.94#ibcon#about to read 4, iclass 29, count 0 2006.252.07:42:38.94#ibcon#read 4, iclass 29, count 0 2006.252.07:42:38.94#ibcon#about to read 5, iclass 29, count 0 2006.252.07:42:38.94#ibcon#read 5, iclass 29, count 0 2006.252.07:42:38.94#ibcon#about to read 6, iclass 29, count 0 2006.252.07:42:38.94#ibcon#read 6, iclass 29, count 0 2006.252.07:42:38.94#ibcon#end of sib2, iclass 29, count 0 2006.252.07:42:38.94#ibcon#*mode == 0, iclass 29, count 0 2006.252.07:42:38.94#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.252.07:42:38.94#ibcon#[26=FRQ=04,832.99\r\n] 2006.252.07:42:38.94#ibcon#*before write, iclass 29, count 0 2006.252.07:42:38.94#ibcon#enter sib2, iclass 29, count 0 2006.252.07:42:38.94#ibcon#flushed, iclass 29, count 0 2006.252.07:42:38.94#ibcon#about to write, iclass 29, count 0 2006.252.07:42:38.94#ibcon#wrote, iclass 29, count 0 2006.252.07:42:38.94#ibcon#about to read 3, iclass 29, count 0 2006.252.07:42:38.98#ibcon#read 3, iclass 29, count 0 2006.252.07:42:38.98#ibcon#about to read 4, iclass 29, count 0 2006.252.07:42:38.98#ibcon#read 4, iclass 29, count 0 2006.252.07:42:38.98#ibcon#about to read 5, iclass 29, count 0 2006.252.07:42:38.98#ibcon#read 5, iclass 29, count 0 2006.252.07:42:38.98#ibcon#about to read 6, iclass 29, count 0 2006.252.07:42:38.98#ibcon#read 6, iclass 29, count 0 2006.252.07:42:38.98#ibcon#end of sib2, iclass 29, count 0 2006.252.07:42:38.98#ibcon#*after write, iclass 29, count 0 2006.252.07:42:38.98#ibcon#*before return 0, iclass 29, count 0 2006.252.07:42:38.98#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.252.07:42:38.98#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.252.07:42:38.98#ibcon#about to clear, iclass 29 cls_cnt 0 2006.252.07:42:38.98#ibcon#cleared, iclass 29 cls_cnt 0 2006.252.07:42:38.98$vc4f8/va=4,7 2006.252.07:42:38.98#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.252.07:42:38.98#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.252.07:42:38.98#ibcon#ireg 11 cls_cnt 2 2006.252.07:42:38.98#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.252.07:42:39.04#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.252.07:42:39.04#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.252.07:42:39.04#ibcon#enter wrdev, iclass 31, count 2 2006.252.07:42:39.04#ibcon#first serial, iclass 31, count 2 2006.252.07:42:39.04#ibcon#enter sib2, iclass 31, count 2 2006.252.07:42:39.04#ibcon#flushed, iclass 31, count 2 2006.252.07:42:39.04#ibcon#about to write, iclass 31, count 2 2006.252.07:42:39.04#ibcon#wrote, iclass 31, count 2 2006.252.07:42:39.04#ibcon#about to read 3, iclass 31, count 2 2006.252.07:42:39.06#ibcon#read 3, iclass 31, count 2 2006.252.07:42:39.06#ibcon#about to read 4, iclass 31, count 2 2006.252.07:42:39.06#ibcon#read 4, iclass 31, count 2 2006.252.07:42:39.06#ibcon#about to read 5, iclass 31, count 2 2006.252.07:42:39.06#ibcon#read 5, iclass 31, count 2 2006.252.07:42:39.06#ibcon#about to read 6, iclass 31, count 2 2006.252.07:42:39.06#ibcon#read 6, iclass 31, count 2 2006.252.07:42:39.06#ibcon#end of sib2, iclass 31, count 2 2006.252.07:42:39.06#ibcon#*mode == 0, iclass 31, count 2 2006.252.07:42:39.06#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.252.07:42:39.06#ibcon#[25=AT04-07\r\n] 2006.252.07:42:39.06#ibcon#*before write, iclass 31, count 2 2006.252.07:42:39.06#ibcon#enter sib2, iclass 31, count 2 2006.252.07:42:39.06#ibcon#flushed, iclass 31, count 2 2006.252.07:42:39.06#ibcon#about to write, iclass 31, count 2 2006.252.07:42:39.06#ibcon#wrote, iclass 31, count 2 2006.252.07:42:39.06#ibcon#about to read 3, iclass 31, count 2 2006.252.07:42:39.09#ibcon#read 3, iclass 31, count 2 2006.252.07:42:39.09#ibcon#about to read 4, iclass 31, count 2 2006.252.07:42:39.09#ibcon#read 4, iclass 31, count 2 2006.252.07:42:39.09#ibcon#about to read 5, iclass 31, count 2 2006.252.07:42:39.09#ibcon#read 5, iclass 31, count 2 2006.252.07:42:39.09#ibcon#about to read 6, iclass 31, count 2 2006.252.07:42:39.09#ibcon#read 6, iclass 31, count 2 2006.252.07:42:39.09#ibcon#end of sib2, iclass 31, count 2 2006.252.07:42:39.09#ibcon#*after write, iclass 31, count 2 2006.252.07:42:39.09#ibcon#*before return 0, iclass 31, count 2 2006.252.07:42:39.09#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.252.07:42:39.09#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.252.07:42:39.09#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.252.07:42:39.09#ibcon#ireg 7 cls_cnt 0 2006.252.07:42:39.09#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.252.07:42:39.21#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.252.07:42:39.21#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.252.07:42:39.21#ibcon#enter wrdev, iclass 31, count 0 2006.252.07:42:39.21#ibcon#first serial, iclass 31, count 0 2006.252.07:42:39.21#ibcon#enter sib2, iclass 31, count 0 2006.252.07:42:39.21#ibcon#flushed, iclass 31, count 0 2006.252.07:42:39.21#ibcon#about to write, iclass 31, count 0 2006.252.07:42:39.21#ibcon#wrote, iclass 31, count 0 2006.252.07:42:39.21#ibcon#about to read 3, iclass 31, count 0 2006.252.07:42:39.23#ibcon#read 3, iclass 31, count 0 2006.252.07:42:39.23#ibcon#about to read 4, iclass 31, count 0 2006.252.07:42:39.23#ibcon#read 4, iclass 31, count 0 2006.252.07:42:39.23#ibcon#about to read 5, iclass 31, count 0 2006.252.07:42:39.23#ibcon#read 5, iclass 31, count 0 2006.252.07:42:39.23#ibcon#about to read 6, iclass 31, count 0 2006.252.07:42:39.23#ibcon#read 6, iclass 31, count 0 2006.252.07:42:39.23#ibcon#end of sib2, iclass 31, count 0 2006.252.07:42:39.23#ibcon#*mode == 0, iclass 31, count 0 2006.252.07:42:39.23#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.252.07:42:39.23#ibcon#[25=USB\r\n] 2006.252.07:42:39.23#ibcon#*before write, iclass 31, count 0 2006.252.07:42:39.23#ibcon#enter sib2, iclass 31, count 0 2006.252.07:42:39.23#ibcon#flushed, iclass 31, count 0 2006.252.07:42:39.23#ibcon#about to write, iclass 31, count 0 2006.252.07:42:39.23#ibcon#wrote, iclass 31, count 0 2006.252.07:42:39.23#ibcon#about to read 3, iclass 31, count 0 2006.252.07:42:39.26#ibcon#read 3, iclass 31, count 0 2006.252.07:42:39.26#ibcon#about to read 4, iclass 31, count 0 2006.252.07:42:39.26#ibcon#read 4, iclass 31, count 0 2006.252.07:42:39.26#ibcon#about to read 5, iclass 31, count 0 2006.252.07:42:39.26#ibcon#read 5, iclass 31, count 0 2006.252.07:42:39.26#ibcon#about to read 6, iclass 31, count 0 2006.252.07:42:39.26#ibcon#read 6, iclass 31, count 0 2006.252.07:42:39.26#ibcon#end of sib2, iclass 31, count 0 2006.252.07:42:39.26#ibcon#*after write, iclass 31, count 0 2006.252.07:42:39.26#ibcon#*before return 0, iclass 31, count 0 2006.252.07:42:39.26#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.252.07:42:39.26#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.252.07:42:39.26#ibcon#about to clear, iclass 31 cls_cnt 0 2006.252.07:42:39.26#ibcon#cleared, iclass 31 cls_cnt 0 2006.252.07:42:39.26$vc4f8/valo=5,652.99 2006.252.07:42:39.26#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.252.07:42:39.26#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.252.07:42:39.26#ibcon#ireg 17 cls_cnt 0 2006.252.07:42:39.26#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.252.07:42:39.26#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.252.07:42:39.26#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.252.07:42:39.26#ibcon#enter wrdev, iclass 33, count 0 2006.252.07:42:39.26#ibcon#first serial, iclass 33, count 0 2006.252.07:42:39.26#ibcon#enter sib2, iclass 33, count 0 2006.252.07:42:39.26#ibcon#flushed, iclass 33, count 0 2006.252.07:42:39.26#ibcon#about to write, iclass 33, count 0 2006.252.07:42:39.26#ibcon#wrote, iclass 33, count 0 2006.252.07:42:39.26#ibcon#about to read 3, iclass 33, count 0 2006.252.07:42:39.28#ibcon#read 3, iclass 33, count 0 2006.252.07:42:39.28#ibcon#about to read 4, iclass 33, count 0 2006.252.07:42:39.28#ibcon#read 4, iclass 33, count 0 2006.252.07:42:39.28#ibcon#about to read 5, iclass 33, count 0 2006.252.07:42:39.28#ibcon#read 5, iclass 33, count 0 2006.252.07:42:39.28#ibcon#about to read 6, iclass 33, count 0 2006.252.07:42:39.28#ibcon#read 6, iclass 33, count 0 2006.252.07:42:39.28#ibcon#end of sib2, iclass 33, count 0 2006.252.07:42:39.28#ibcon#*mode == 0, iclass 33, count 0 2006.252.07:42:39.28#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.252.07:42:39.28#ibcon#[26=FRQ=05,652.99\r\n] 2006.252.07:42:39.28#ibcon#*before write, iclass 33, count 0 2006.252.07:42:39.28#ibcon#enter sib2, iclass 33, count 0 2006.252.07:42:39.28#ibcon#flushed, iclass 33, count 0 2006.252.07:42:39.28#ibcon#about to write, iclass 33, count 0 2006.252.07:42:39.28#ibcon#wrote, iclass 33, count 0 2006.252.07:42:39.28#ibcon#about to read 3, iclass 33, count 0 2006.252.07:42:39.32#ibcon#read 3, iclass 33, count 0 2006.252.07:42:39.32#ibcon#about to read 4, iclass 33, count 0 2006.252.07:42:39.32#ibcon#read 4, iclass 33, count 0 2006.252.07:42:39.32#ibcon#about to read 5, iclass 33, count 0 2006.252.07:42:39.32#ibcon#read 5, iclass 33, count 0 2006.252.07:42:39.32#ibcon#about to read 6, iclass 33, count 0 2006.252.07:42:39.32#ibcon#read 6, iclass 33, count 0 2006.252.07:42:39.32#ibcon#end of sib2, iclass 33, count 0 2006.252.07:42:39.32#ibcon#*after write, iclass 33, count 0 2006.252.07:42:39.32#ibcon#*before return 0, iclass 33, count 0 2006.252.07:42:39.32#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.252.07:42:39.32#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.252.07:42:39.32#ibcon#about to clear, iclass 33 cls_cnt 0 2006.252.07:42:39.32#ibcon#cleared, iclass 33 cls_cnt 0 2006.252.07:42:39.32$vc4f8/va=5,7 2006.252.07:42:39.32#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.252.07:42:39.32#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.252.07:42:39.32#ibcon#ireg 11 cls_cnt 2 2006.252.07:42:39.32#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.252.07:42:39.38#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.252.07:42:39.38#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.252.07:42:39.38#ibcon#enter wrdev, iclass 35, count 2 2006.252.07:42:39.38#ibcon#first serial, iclass 35, count 2 2006.252.07:42:39.38#ibcon#enter sib2, iclass 35, count 2 2006.252.07:42:39.38#ibcon#flushed, iclass 35, count 2 2006.252.07:42:39.38#ibcon#about to write, iclass 35, count 2 2006.252.07:42:39.38#ibcon#wrote, iclass 35, count 2 2006.252.07:42:39.38#ibcon#about to read 3, iclass 35, count 2 2006.252.07:42:39.40#ibcon#read 3, iclass 35, count 2 2006.252.07:42:39.40#ibcon#about to read 4, iclass 35, count 2 2006.252.07:42:39.40#ibcon#read 4, iclass 35, count 2 2006.252.07:42:39.40#ibcon#about to read 5, iclass 35, count 2 2006.252.07:42:39.40#ibcon#read 5, iclass 35, count 2 2006.252.07:42:39.40#ibcon#about to read 6, iclass 35, count 2 2006.252.07:42:39.40#ibcon#read 6, iclass 35, count 2 2006.252.07:42:39.40#ibcon#end of sib2, iclass 35, count 2 2006.252.07:42:39.40#ibcon#*mode == 0, iclass 35, count 2 2006.252.07:42:39.40#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.252.07:42:39.40#ibcon#[25=AT05-07\r\n] 2006.252.07:42:39.40#ibcon#*before write, iclass 35, count 2 2006.252.07:42:39.40#ibcon#enter sib2, iclass 35, count 2 2006.252.07:42:39.40#ibcon#flushed, iclass 35, count 2 2006.252.07:42:39.40#ibcon#about to write, iclass 35, count 2 2006.252.07:42:39.40#ibcon#wrote, iclass 35, count 2 2006.252.07:42:39.40#ibcon#about to read 3, iclass 35, count 2 2006.252.07:42:39.44#ibcon#read 3, iclass 35, count 2 2006.252.07:42:39.44#ibcon#about to read 4, iclass 35, count 2 2006.252.07:42:39.44#ibcon#read 4, iclass 35, count 2 2006.252.07:42:39.44#ibcon#about to read 5, iclass 35, count 2 2006.252.07:42:39.44#ibcon#read 5, iclass 35, count 2 2006.252.07:42:39.44#ibcon#about to read 6, iclass 35, count 2 2006.252.07:42:39.44#ibcon#read 6, iclass 35, count 2 2006.252.07:42:39.44#ibcon#end of sib2, iclass 35, count 2 2006.252.07:42:39.44#ibcon#*after write, iclass 35, count 2 2006.252.07:42:39.44#ibcon#*before return 0, iclass 35, count 2 2006.252.07:42:39.44#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.252.07:42:39.44#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.252.07:42:39.44#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.252.07:42:39.44#ibcon#ireg 7 cls_cnt 0 2006.252.07:42:39.44#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.252.07:42:39.55#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.252.07:42:39.55#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.252.07:42:39.55#ibcon#enter wrdev, iclass 35, count 0 2006.252.07:42:39.55#ibcon#first serial, iclass 35, count 0 2006.252.07:42:39.55#ibcon#enter sib2, iclass 35, count 0 2006.252.07:42:39.55#ibcon#flushed, iclass 35, count 0 2006.252.07:42:39.55#ibcon#about to write, iclass 35, count 0 2006.252.07:42:39.55#ibcon#wrote, iclass 35, count 0 2006.252.07:42:39.55#ibcon#about to read 3, iclass 35, count 0 2006.252.07:42:39.57#ibcon#read 3, iclass 35, count 0 2006.252.07:42:39.57#ibcon#about to read 4, iclass 35, count 0 2006.252.07:42:39.57#ibcon#read 4, iclass 35, count 0 2006.252.07:42:39.57#ibcon#about to read 5, iclass 35, count 0 2006.252.07:42:39.57#ibcon#read 5, iclass 35, count 0 2006.252.07:42:39.57#ibcon#about to read 6, iclass 35, count 0 2006.252.07:42:39.57#ibcon#read 6, iclass 35, count 0 2006.252.07:42:39.57#ibcon#end of sib2, iclass 35, count 0 2006.252.07:42:39.57#ibcon#*mode == 0, iclass 35, count 0 2006.252.07:42:39.57#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.252.07:42:39.57#ibcon#[25=USB\r\n] 2006.252.07:42:39.57#ibcon#*before write, iclass 35, count 0 2006.252.07:42:39.57#ibcon#enter sib2, iclass 35, count 0 2006.252.07:42:39.57#ibcon#flushed, iclass 35, count 0 2006.252.07:42:39.57#ibcon#about to write, iclass 35, count 0 2006.252.07:42:39.57#ibcon#wrote, iclass 35, count 0 2006.252.07:42:39.57#ibcon#about to read 3, iclass 35, count 0 2006.252.07:42:39.60#ibcon#read 3, iclass 35, count 0 2006.252.07:42:39.60#ibcon#about to read 4, iclass 35, count 0 2006.252.07:42:39.60#ibcon#read 4, iclass 35, count 0 2006.252.07:42:39.60#ibcon#about to read 5, iclass 35, count 0 2006.252.07:42:39.60#ibcon#read 5, iclass 35, count 0 2006.252.07:42:39.60#ibcon#about to read 6, iclass 35, count 0 2006.252.07:42:39.60#ibcon#read 6, iclass 35, count 0 2006.252.07:42:39.60#ibcon#end of sib2, iclass 35, count 0 2006.252.07:42:39.60#ibcon#*after write, iclass 35, count 0 2006.252.07:42:39.60#ibcon#*before return 0, iclass 35, count 0 2006.252.07:42:39.60#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.252.07:42:39.60#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.252.07:42:39.60#ibcon#about to clear, iclass 35 cls_cnt 0 2006.252.07:42:39.60#ibcon#cleared, iclass 35 cls_cnt 0 2006.252.07:42:39.60$vc4f8/valo=6,772.99 2006.252.07:42:39.60#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.252.07:42:39.60#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.252.07:42:39.60#ibcon#ireg 17 cls_cnt 0 2006.252.07:42:39.60#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.252.07:42:39.60#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.252.07:42:39.60#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.252.07:42:39.60#ibcon#enter wrdev, iclass 37, count 0 2006.252.07:42:39.60#ibcon#first serial, iclass 37, count 0 2006.252.07:42:39.60#ibcon#enter sib2, iclass 37, count 0 2006.252.07:42:39.60#ibcon#flushed, iclass 37, count 0 2006.252.07:42:39.60#ibcon#about to write, iclass 37, count 0 2006.252.07:42:39.60#ibcon#wrote, iclass 37, count 0 2006.252.07:42:39.60#ibcon#about to read 3, iclass 37, count 0 2006.252.07:42:39.62#ibcon#read 3, iclass 37, count 0 2006.252.07:42:39.62#ibcon#about to read 4, iclass 37, count 0 2006.252.07:42:39.62#ibcon#read 4, iclass 37, count 0 2006.252.07:42:39.62#ibcon#about to read 5, iclass 37, count 0 2006.252.07:42:39.62#ibcon#read 5, iclass 37, count 0 2006.252.07:42:39.62#ibcon#about to read 6, iclass 37, count 0 2006.252.07:42:39.62#ibcon#read 6, iclass 37, count 0 2006.252.07:42:39.62#ibcon#end of sib2, iclass 37, count 0 2006.252.07:42:39.62#ibcon#*mode == 0, iclass 37, count 0 2006.252.07:42:39.62#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.252.07:42:39.62#ibcon#[26=FRQ=06,772.99\r\n] 2006.252.07:42:39.62#ibcon#*before write, iclass 37, count 0 2006.252.07:42:39.62#ibcon#enter sib2, iclass 37, count 0 2006.252.07:42:39.62#ibcon#flushed, iclass 37, count 0 2006.252.07:42:39.62#ibcon#about to write, iclass 37, count 0 2006.252.07:42:39.62#ibcon#wrote, iclass 37, count 0 2006.252.07:42:39.62#ibcon#about to read 3, iclass 37, count 0 2006.252.07:42:39.66#ibcon#read 3, iclass 37, count 0 2006.252.07:42:39.66#ibcon#about to read 4, iclass 37, count 0 2006.252.07:42:39.66#ibcon#read 4, iclass 37, count 0 2006.252.07:42:39.66#ibcon#about to read 5, iclass 37, count 0 2006.252.07:42:39.66#ibcon#read 5, iclass 37, count 0 2006.252.07:42:39.66#ibcon#about to read 6, iclass 37, count 0 2006.252.07:42:39.66#ibcon#read 6, iclass 37, count 0 2006.252.07:42:39.66#ibcon#end of sib2, iclass 37, count 0 2006.252.07:42:39.66#ibcon#*after write, iclass 37, count 0 2006.252.07:42:39.66#ibcon#*before return 0, iclass 37, count 0 2006.252.07:42:39.66#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.252.07:42:39.66#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.252.07:42:39.66#ibcon#about to clear, iclass 37 cls_cnt 0 2006.252.07:42:39.66#ibcon#cleared, iclass 37 cls_cnt 0 2006.252.07:42:39.66$vc4f8/va=6,7 2006.252.07:42:39.66#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.252.07:42:39.66#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.252.07:42:39.66#ibcon#ireg 11 cls_cnt 2 2006.252.07:42:39.66#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.252.07:42:39.72#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.252.07:42:39.72#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.252.07:42:39.72#ibcon#enter wrdev, iclass 39, count 2 2006.252.07:42:39.72#ibcon#first serial, iclass 39, count 2 2006.252.07:42:39.72#ibcon#enter sib2, iclass 39, count 2 2006.252.07:42:39.72#ibcon#flushed, iclass 39, count 2 2006.252.07:42:39.72#ibcon#about to write, iclass 39, count 2 2006.252.07:42:39.72#ibcon#wrote, iclass 39, count 2 2006.252.07:42:39.72#ibcon#about to read 3, iclass 39, count 2 2006.252.07:42:39.74#ibcon#read 3, iclass 39, count 2 2006.252.07:42:39.74#ibcon#about to read 4, iclass 39, count 2 2006.252.07:42:39.74#ibcon#read 4, iclass 39, count 2 2006.252.07:42:39.74#ibcon#about to read 5, iclass 39, count 2 2006.252.07:42:39.74#ibcon#read 5, iclass 39, count 2 2006.252.07:42:39.74#ibcon#about to read 6, iclass 39, count 2 2006.252.07:42:39.74#ibcon#read 6, iclass 39, count 2 2006.252.07:42:39.74#ibcon#end of sib2, iclass 39, count 2 2006.252.07:42:39.74#ibcon#*mode == 0, iclass 39, count 2 2006.252.07:42:39.74#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.252.07:42:39.74#ibcon#[25=AT06-07\r\n] 2006.252.07:42:39.74#ibcon#*before write, iclass 39, count 2 2006.252.07:42:39.74#ibcon#enter sib2, iclass 39, count 2 2006.252.07:42:39.74#ibcon#flushed, iclass 39, count 2 2006.252.07:42:39.74#ibcon#about to write, iclass 39, count 2 2006.252.07:42:39.74#ibcon#wrote, iclass 39, count 2 2006.252.07:42:39.74#ibcon#about to read 3, iclass 39, count 2 2006.252.07:42:39.77#ibcon#read 3, iclass 39, count 2 2006.252.07:42:39.77#ibcon#about to read 4, iclass 39, count 2 2006.252.07:42:39.77#ibcon#read 4, iclass 39, count 2 2006.252.07:42:39.77#ibcon#about to read 5, iclass 39, count 2 2006.252.07:42:39.77#ibcon#read 5, iclass 39, count 2 2006.252.07:42:39.77#ibcon#about to read 6, iclass 39, count 2 2006.252.07:42:39.77#ibcon#read 6, iclass 39, count 2 2006.252.07:42:39.77#ibcon#end of sib2, iclass 39, count 2 2006.252.07:42:39.77#ibcon#*after write, iclass 39, count 2 2006.252.07:42:39.77#ibcon#*before return 0, iclass 39, count 2 2006.252.07:42:39.77#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.252.07:42:39.77#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.252.07:42:39.77#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.252.07:42:39.77#ibcon#ireg 7 cls_cnt 0 2006.252.07:42:39.77#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.252.07:42:39.89#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.252.07:42:39.89#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.252.07:42:39.89#ibcon#enter wrdev, iclass 39, count 0 2006.252.07:42:39.89#ibcon#first serial, iclass 39, count 0 2006.252.07:42:39.89#ibcon#enter sib2, iclass 39, count 0 2006.252.07:42:39.89#ibcon#flushed, iclass 39, count 0 2006.252.07:42:39.89#ibcon#about to write, iclass 39, count 0 2006.252.07:42:39.89#ibcon#wrote, iclass 39, count 0 2006.252.07:42:39.89#ibcon#about to read 3, iclass 39, count 0 2006.252.07:42:39.91#ibcon#read 3, iclass 39, count 0 2006.252.07:42:39.91#ibcon#about to read 4, iclass 39, count 0 2006.252.07:42:39.91#ibcon#read 4, iclass 39, count 0 2006.252.07:42:39.91#ibcon#about to read 5, iclass 39, count 0 2006.252.07:42:39.91#ibcon#read 5, iclass 39, count 0 2006.252.07:42:39.91#ibcon#about to read 6, iclass 39, count 0 2006.252.07:42:39.91#ibcon#read 6, iclass 39, count 0 2006.252.07:42:39.91#ibcon#end of sib2, iclass 39, count 0 2006.252.07:42:39.91#ibcon#*mode == 0, iclass 39, count 0 2006.252.07:42:39.91#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.252.07:42:39.91#ibcon#[25=USB\r\n] 2006.252.07:42:39.91#ibcon#*before write, iclass 39, count 0 2006.252.07:42:39.91#ibcon#enter sib2, iclass 39, count 0 2006.252.07:42:39.91#ibcon#flushed, iclass 39, count 0 2006.252.07:42:39.91#ibcon#about to write, iclass 39, count 0 2006.252.07:42:39.91#ibcon#wrote, iclass 39, count 0 2006.252.07:42:39.91#ibcon#about to read 3, iclass 39, count 0 2006.252.07:42:39.94#ibcon#read 3, iclass 39, count 0 2006.252.07:42:39.94#ibcon#about to read 4, iclass 39, count 0 2006.252.07:42:39.94#ibcon#read 4, iclass 39, count 0 2006.252.07:42:39.94#ibcon#about to read 5, iclass 39, count 0 2006.252.07:42:39.94#ibcon#read 5, iclass 39, count 0 2006.252.07:42:39.94#ibcon#about to read 6, iclass 39, count 0 2006.252.07:42:39.94#ibcon#read 6, iclass 39, count 0 2006.252.07:42:39.94#ibcon#end of sib2, iclass 39, count 0 2006.252.07:42:39.94#ibcon#*after write, iclass 39, count 0 2006.252.07:42:39.94#ibcon#*before return 0, iclass 39, count 0 2006.252.07:42:39.94#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.252.07:42:39.94#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.252.07:42:39.94#ibcon#about to clear, iclass 39 cls_cnt 0 2006.252.07:42:39.94#ibcon#cleared, iclass 39 cls_cnt 0 2006.252.07:42:39.94$vc4f8/valo=7,832.99 2006.252.07:42:39.94#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.252.07:42:39.94#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.252.07:42:39.94#ibcon#ireg 17 cls_cnt 0 2006.252.07:42:39.94#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.252.07:42:39.94#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.252.07:42:39.94#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.252.07:42:39.94#ibcon#enter wrdev, iclass 3, count 0 2006.252.07:42:39.94#ibcon#first serial, iclass 3, count 0 2006.252.07:42:39.94#ibcon#enter sib2, iclass 3, count 0 2006.252.07:42:39.94#ibcon#flushed, iclass 3, count 0 2006.252.07:42:39.94#ibcon#about to write, iclass 3, count 0 2006.252.07:42:39.94#ibcon#wrote, iclass 3, count 0 2006.252.07:42:39.94#ibcon#about to read 3, iclass 3, count 0 2006.252.07:42:39.96#ibcon#read 3, iclass 3, count 0 2006.252.07:42:39.96#ibcon#about to read 4, iclass 3, count 0 2006.252.07:42:39.96#ibcon#read 4, iclass 3, count 0 2006.252.07:42:39.96#ibcon#about to read 5, iclass 3, count 0 2006.252.07:42:39.96#ibcon#read 5, iclass 3, count 0 2006.252.07:42:39.96#ibcon#about to read 6, iclass 3, count 0 2006.252.07:42:39.96#ibcon#read 6, iclass 3, count 0 2006.252.07:42:39.96#ibcon#end of sib2, iclass 3, count 0 2006.252.07:42:39.96#ibcon#*mode == 0, iclass 3, count 0 2006.252.07:42:39.96#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.252.07:42:39.96#ibcon#[26=FRQ=07,832.99\r\n] 2006.252.07:42:39.96#ibcon#*before write, iclass 3, count 0 2006.252.07:42:39.96#ibcon#enter sib2, iclass 3, count 0 2006.252.07:42:39.96#ibcon#flushed, iclass 3, count 0 2006.252.07:42:39.96#ibcon#about to write, iclass 3, count 0 2006.252.07:42:39.96#ibcon#wrote, iclass 3, count 0 2006.252.07:42:39.96#ibcon#about to read 3, iclass 3, count 0 2006.252.07:42:40.00#ibcon#read 3, iclass 3, count 0 2006.252.07:42:40.00#ibcon#about to read 4, iclass 3, count 0 2006.252.07:42:40.00#ibcon#read 4, iclass 3, count 0 2006.252.07:42:40.00#ibcon#about to read 5, iclass 3, count 0 2006.252.07:42:40.00#ibcon#read 5, iclass 3, count 0 2006.252.07:42:40.00#ibcon#about to read 6, iclass 3, count 0 2006.252.07:42:40.00#ibcon#read 6, iclass 3, count 0 2006.252.07:42:40.00#ibcon#end of sib2, iclass 3, count 0 2006.252.07:42:40.00#ibcon#*after write, iclass 3, count 0 2006.252.07:42:40.00#ibcon#*before return 0, iclass 3, count 0 2006.252.07:42:40.00#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.252.07:42:40.00#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.252.07:42:40.00#ibcon#about to clear, iclass 3 cls_cnt 0 2006.252.07:42:40.00#ibcon#cleared, iclass 3 cls_cnt 0 2006.252.07:42:40.00$vc4f8/va=7,7 2006.252.07:42:40.00#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.252.07:42:40.00#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.252.07:42:40.00#ibcon#ireg 11 cls_cnt 2 2006.252.07:42:40.00#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.252.07:42:40.06#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.252.07:42:40.06#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.252.07:42:40.06#ibcon#enter wrdev, iclass 5, count 2 2006.252.07:42:40.06#ibcon#first serial, iclass 5, count 2 2006.252.07:42:40.06#ibcon#enter sib2, iclass 5, count 2 2006.252.07:42:40.06#ibcon#flushed, iclass 5, count 2 2006.252.07:42:40.06#ibcon#about to write, iclass 5, count 2 2006.252.07:42:40.06#ibcon#wrote, iclass 5, count 2 2006.252.07:42:40.06#ibcon#about to read 3, iclass 5, count 2 2006.252.07:42:40.08#ibcon#read 3, iclass 5, count 2 2006.252.07:42:40.08#ibcon#about to read 4, iclass 5, count 2 2006.252.07:42:40.08#ibcon#read 4, iclass 5, count 2 2006.252.07:42:40.08#ibcon#about to read 5, iclass 5, count 2 2006.252.07:42:40.08#ibcon#read 5, iclass 5, count 2 2006.252.07:42:40.08#ibcon#about to read 6, iclass 5, count 2 2006.252.07:42:40.08#ibcon#read 6, iclass 5, count 2 2006.252.07:42:40.08#ibcon#end of sib2, iclass 5, count 2 2006.252.07:42:40.08#ibcon#*mode == 0, iclass 5, count 2 2006.252.07:42:40.08#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.252.07:42:40.08#ibcon#[25=AT07-07\r\n] 2006.252.07:42:40.08#ibcon#*before write, iclass 5, count 2 2006.252.07:42:40.08#ibcon#enter sib2, iclass 5, count 2 2006.252.07:42:40.08#ibcon#flushed, iclass 5, count 2 2006.252.07:42:40.08#ibcon#about to write, iclass 5, count 2 2006.252.07:42:40.08#ibcon#wrote, iclass 5, count 2 2006.252.07:42:40.08#ibcon#about to read 3, iclass 5, count 2 2006.252.07:42:40.11#ibcon#read 3, iclass 5, count 2 2006.252.07:42:40.11#ibcon#about to read 4, iclass 5, count 2 2006.252.07:42:40.11#ibcon#read 4, iclass 5, count 2 2006.252.07:42:40.11#ibcon#about to read 5, iclass 5, count 2 2006.252.07:42:40.11#ibcon#read 5, iclass 5, count 2 2006.252.07:42:40.11#ibcon#about to read 6, iclass 5, count 2 2006.252.07:42:40.11#ibcon#read 6, iclass 5, count 2 2006.252.07:42:40.11#ibcon#end of sib2, iclass 5, count 2 2006.252.07:42:40.11#ibcon#*after write, iclass 5, count 2 2006.252.07:42:40.11#ibcon#*before return 0, iclass 5, count 2 2006.252.07:42:40.11#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.252.07:42:40.11#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.252.07:42:40.11#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.252.07:42:40.11#ibcon#ireg 7 cls_cnt 0 2006.252.07:42:40.11#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.252.07:42:40.23#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.252.07:42:40.23#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.252.07:42:40.23#ibcon#enter wrdev, iclass 5, count 0 2006.252.07:42:40.23#ibcon#first serial, iclass 5, count 0 2006.252.07:42:40.23#ibcon#enter sib2, iclass 5, count 0 2006.252.07:42:40.23#ibcon#flushed, iclass 5, count 0 2006.252.07:42:40.23#ibcon#about to write, iclass 5, count 0 2006.252.07:42:40.23#ibcon#wrote, iclass 5, count 0 2006.252.07:42:40.23#ibcon#about to read 3, iclass 5, count 0 2006.252.07:42:40.25#ibcon#read 3, iclass 5, count 0 2006.252.07:42:40.25#ibcon#about to read 4, iclass 5, count 0 2006.252.07:42:40.25#ibcon#read 4, iclass 5, count 0 2006.252.07:42:40.25#ibcon#about to read 5, iclass 5, count 0 2006.252.07:42:40.25#ibcon#read 5, iclass 5, count 0 2006.252.07:42:40.25#ibcon#about to read 6, iclass 5, count 0 2006.252.07:42:40.25#ibcon#read 6, iclass 5, count 0 2006.252.07:42:40.25#ibcon#end of sib2, iclass 5, count 0 2006.252.07:42:40.25#ibcon#*mode == 0, iclass 5, count 0 2006.252.07:42:40.25#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.252.07:42:40.25#ibcon#[25=USB\r\n] 2006.252.07:42:40.25#ibcon#*before write, iclass 5, count 0 2006.252.07:42:40.25#ibcon#enter sib2, iclass 5, count 0 2006.252.07:42:40.25#ibcon#flushed, iclass 5, count 0 2006.252.07:42:40.25#ibcon#about to write, iclass 5, count 0 2006.252.07:42:40.25#ibcon#wrote, iclass 5, count 0 2006.252.07:42:40.25#ibcon#about to read 3, iclass 5, count 0 2006.252.07:42:40.28#ibcon#read 3, iclass 5, count 0 2006.252.07:42:40.28#ibcon#about to read 4, iclass 5, count 0 2006.252.07:42:40.28#ibcon#read 4, iclass 5, count 0 2006.252.07:42:40.28#ibcon#about to read 5, iclass 5, count 0 2006.252.07:42:40.28#ibcon#read 5, iclass 5, count 0 2006.252.07:42:40.28#ibcon#about to read 6, iclass 5, count 0 2006.252.07:42:40.28#ibcon#read 6, iclass 5, count 0 2006.252.07:42:40.28#ibcon#end of sib2, iclass 5, count 0 2006.252.07:42:40.28#ibcon#*after write, iclass 5, count 0 2006.252.07:42:40.28#ibcon#*before return 0, iclass 5, count 0 2006.252.07:42:40.28#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.252.07:42:40.28#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.252.07:42:40.28#ibcon#about to clear, iclass 5 cls_cnt 0 2006.252.07:42:40.28#ibcon#cleared, iclass 5 cls_cnt 0 2006.252.07:42:40.28$vc4f8/valo=8,852.99 2006.252.07:42:40.28#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.252.07:42:40.28#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.252.07:42:40.28#ibcon#ireg 17 cls_cnt 0 2006.252.07:42:40.28#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.252.07:42:40.28#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.252.07:42:40.28#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.252.07:42:40.28#ibcon#enter wrdev, iclass 7, count 0 2006.252.07:42:40.28#ibcon#first serial, iclass 7, count 0 2006.252.07:42:40.28#ibcon#enter sib2, iclass 7, count 0 2006.252.07:42:40.28#ibcon#flushed, iclass 7, count 0 2006.252.07:42:40.28#ibcon#about to write, iclass 7, count 0 2006.252.07:42:40.28#ibcon#wrote, iclass 7, count 0 2006.252.07:42:40.28#ibcon#about to read 3, iclass 7, count 0 2006.252.07:42:40.30#ibcon#read 3, iclass 7, count 0 2006.252.07:42:40.30#ibcon#about to read 4, iclass 7, count 0 2006.252.07:42:40.30#ibcon#read 4, iclass 7, count 0 2006.252.07:42:40.30#ibcon#about to read 5, iclass 7, count 0 2006.252.07:42:40.30#ibcon#read 5, iclass 7, count 0 2006.252.07:42:40.30#ibcon#about to read 6, iclass 7, count 0 2006.252.07:42:40.30#ibcon#read 6, iclass 7, count 0 2006.252.07:42:40.30#ibcon#end of sib2, iclass 7, count 0 2006.252.07:42:40.30#ibcon#*mode == 0, iclass 7, count 0 2006.252.07:42:40.30#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.252.07:42:40.30#ibcon#[26=FRQ=08,852.99\r\n] 2006.252.07:42:40.30#ibcon#*before write, iclass 7, count 0 2006.252.07:42:40.30#ibcon#enter sib2, iclass 7, count 0 2006.252.07:42:40.30#ibcon#flushed, iclass 7, count 0 2006.252.07:42:40.30#ibcon#about to write, iclass 7, count 0 2006.252.07:42:40.30#ibcon#wrote, iclass 7, count 0 2006.252.07:42:40.30#ibcon#about to read 3, iclass 7, count 0 2006.252.07:42:40.34#ibcon#read 3, iclass 7, count 0 2006.252.07:42:40.34#ibcon#about to read 4, iclass 7, count 0 2006.252.07:42:40.34#ibcon#read 4, iclass 7, count 0 2006.252.07:42:40.34#ibcon#about to read 5, iclass 7, count 0 2006.252.07:42:40.34#ibcon#read 5, iclass 7, count 0 2006.252.07:42:40.34#ibcon#about to read 6, iclass 7, count 0 2006.252.07:42:40.34#ibcon#read 6, iclass 7, count 0 2006.252.07:42:40.34#ibcon#end of sib2, iclass 7, count 0 2006.252.07:42:40.34#ibcon#*after write, iclass 7, count 0 2006.252.07:42:40.34#ibcon#*before return 0, iclass 7, count 0 2006.252.07:42:40.34#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.252.07:42:40.34#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.252.07:42:40.34#ibcon#about to clear, iclass 7 cls_cnt 0 2006.252.07:42:40.34#ibcon#cleared, iclass 7 cls_cnt 0 2006.252.07:42:40.34$vc4f8/va=8,7 2006.252.07:42:40.34#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.252.07:42:40.34#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.252.07:42:40.34#ibcon#ireg 11 cls_cnt 2 2006.252.07:42:40.34#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.252.07:42:40.40#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.252.07:42:40.40#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.252.07:42:40.40#ibcon#enter wrdev, iclass 11, count 2 2006.252.07:42:40.40#ibcon#first serial, iclass 11, count 2 2006.252.07:42:40.40#ibcon#enter sib2, iclass 11, count 2 2006.252.07:42:40.40#ibcon#flushed, iclass 11, count 2 2006.252.07:42:40.40#ibcon#about to write, iclass 11, count 2 2006.252.07:42:40.40#ibcon#wrote, iclass 11, count 2 2006.252.07:42:40.40#ibcon#about to read 3, iclass 11, count 2 2006.252.07:42:40.42#ibcon#read 3, iclass 11, count 2 2006.252.07:42:40.42#ibcon#about to read 4, iclass 11, count 2 2006.252.07:42:40.42#ibcon#read 4, iclass 11, count 2 2006.252.07:42:40.42#ibcon#about to read 5, iclass 11, count 2 2006.252.07:42:40.42#ibcon#read 5, iclass 11, count 2 2006.252.07:42:40.42#ibcon#about to read 6, iclass 11, count 2 2006.252.07:42:40.42#ibcon#read 6, iclass 11, count 2 2006.252.07:42:40.42#ibcon#end of sib2, iclass 11, count 2 2006.252.07:42:40.42#ibcon#*mode == 0, iclass 11, count 2 2006.252.07:42:40.42#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.252.07:42:40.42#ibcon#[25=AT08-07\r\n] 2006.252.07:42:40.42#ibcon#*before write, iclass 11, count 2 2006.252.07:42:40.42#ibcon#enter sib2, iclass 11, count 2 2006.252.07:42:40.42#ibcon#flushed, iclass 11, count 2 2006.252.07:42:40.42#ibcon#about to write, iclass 11, count 2 2006.252.07:42:40.42#ibcon#wrote, iclass 11, count 2 2006.252.07:42:40.42#ibcon#about to read 3, iclass 11, count 2 2006.252.07:42:40.45#ibcon#read 3, iclass 11, count 2 2006.252.07:42:40.45#ibcon#about to read 4, iclass 11, count 2 2006.252.07:42:40.45#ibcon#read 4, iclass 11, count 2 2006.252.07:42:40.45#ibcon#about to read 5, iclass 11, count 2 2006.252.07:42:40.45#ibcon#read 5, iclass 11, count 2 2006.252.07:42:40.45#ibcon#about to read 6, iclass 11, count 2 2006.252.07:42:40.45#ibcon#read 6, iclass 11, count 2 2006.252.07:42:40.45#ibcon#end of sib2, iclass 11, count 2 2006.252.07:42:40.45#ibcon#*after write, iclass 11, count 2 2006.252.07:42:40.45#ibcon#*before return 0, iclass 11, count 2 2006.252.07:42:40.45#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.252.07:42:40.45#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.252.07:42:40.45#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.252.07:42:40.45#ibcon#ireg 7 cls_cnt 0 2006.252.07:42:40.45#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.252.07:42:40.57#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.252.07:42:40.57#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.252.07:42:40.57#ibcon#enter wrdev, iclass 11, count 0 2006.252.07:42:40.57#ibcon#first serial, iclass 11, count 0 2006.252.07:42:40.57#ibcon#enter sib2, iclass 11, count 0 2006.252.07:42:40.57#ibcon#flushed, iclass 11, count 0 2006.252.07:42:40.57#ibcon#about to write, iclass 11, count 0 2006.252.07:42:40.57#ibcon#wrote, iclass 11, count 0 2006.252.07:42:40.57#ibcon#about to read 3, iclass 11, count 0 2006.252.07:42:40.59#ibcon#read 3, iclass 11, count 0 2006.252.07:42:40.59#ibcon#about to read 4, iclass 11, count 0 2006.252.07:42:40.59#ibcon#read 4, iclass 11, count 0 2006.252.07:42:40.59#ibcon#about to read 5, iclass 11, count 0 2006.252.07:42:40.59#ibcon#read 5, iclass 11, count 0 2006.252.07:42:40.59#ibcon#about to read 6, iclass 11, count 0 2006.252.07:42:40.59#ibcon#read 6, iclass 11, count 0 2006.252.07:42:40.59#ibcon#end of sib2, iclass 11, count 0 2006.252.07:42:40.59#ibcon#*mode == 0, iclass 11, count 0 2006.252.07:42:40.59#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.252.07:42:40.59#ibcon#[25=USB\r\n] 2006.252.07:42:40.59#ibcon#*before write, iclass 11, count 0 2006.252.07:42:40.59#ibcon#enter sib2, iclass 11, count 0 2006.252.07:42:40.59#ibcon#flushed, iclass 11, count 0 2006.252.07:42:40.59#ibcon#about to write, iclass 11, count 0 2006.252.07:42:40.59#ibcon#wrote, iclass 11, count 0 2006.252.07:42:40.59#ibcon#about to read 3, iclass 11, count 0 2006.252.07:42:40.62#ibcon#read 3, iclass 11, count 0 2006.252.07:42:40.62#ibcon#about to read 4, iclass 11, count 0 2006.252.07:42:40.62#ibcon#read 4, iclass 11, count 0 2006.252.07:42:40.62#ibcon#about to read 5, iclass 11, count 0 2006.252.07:42:40.62#ibcon#read 5, iclass 11, count 0 2006.252.07:42:40.62#ibcon#about to read 6, iclass 11, count 0 2006.252.07:42:40.62#ibcon#read 6, iclass 11, count 0 2006.252.07:42:40.62#ibcon#end of sib2, iclass 11, count 0 2006.252.07:42:40.62#ibcon#*after write, iclass 11, count 0 2006.252.07:42:40.62#ibcon#*before return 0, iclass 11, count 0 2006.252.07:42:40.62#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.252.07:42:40.62#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.252.07:42:40.62#ibcon#about to clear, iclass 11 cls_cnt 0 2006.252.07:42:40.62#ibcon#cleared, iclass 11 cls_cnt 0 2006.252.07:42:40.62$vc4f8/vblo=1,632.99 2006.252.07:42:40.62#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.252.07:42:40.62#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.252.07:42:40.62#ibcon#ireg 17 cls_cnt 0 2006.252.07:42:40.62#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.252.07:42:40.62#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.252.07:42:40.62#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.252.07:42:40.62#ibcon#enter wrdev, iclass 13, count 0 2006.252.07:42:40.62#ibcon#first serial, iclass 13, count 0 2006.252.07:42:40.62#ibcon#enter sib2, iclass 13, count 0 2006.252.07:42:40.62#ibcon#flushed, iclass 13, count 0 2006.252.07:42:40.62#ibcon#about to write, iclass 13, count 0 2006.252.07:42:40.62#ibcon#wrote, iclass 13, count 0 2006.252.07:42:40.62#ibcon#about to read 3, iclass 13, count 0 2006.252.07:42:40.64#ibcon#read 3, iclass 13, count 0 2006.252.07:42:40.64#ibcon#about to read 4, iclass 13, count 0 2006.252.07:42:40.64#ibcon#read 4, iclass 13, count 0 2006.252.07:42:40.64#ibcon#about to read 5, iclass 13, count 0 2006.252.07:42:40.64#ibcon#read 5, iclass 13, count 0 2006.252.07:42:40.64#ibcon#about to read 6, iclass 13, count 0 2006.252.07:42:40.64#ibcon#read 6, iclass 13, count 0 2006.252.07:42:40.64#ibcon#end of sib2, iclass 13, count 0 2006.252.07:42:40.64#ibcon#*mode == 0, iclass 13, count 0 2006.252.07:42:40.64#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.252.07:42:40.64#ibcon#[28=FRQ=01,632.99\r\n] 2006.252.07:42:40.64#ibcon#*before write, iclass 13, count 0 2006.252.07:42:40.64#ibcon#enter sib2, iclass 13, count 0 2006.252.07:42:40.64#ibcon#flushed, iclass 13, count 0 2006.252.07:42:40.64#ibcon#about to write, iclass 13, count 0 2006.252.07:42:40.64#ibcon#wrote, iclass 13, count 0 2006.252.07:42:40.64#ibcon#about to read 3, iclass 13, count 0 2006.252.07:42:40.68#ibcon#read 3, iclass 13, count 0 2006.252.07:42:40.68#ibcon#about to read 4, iclass 13, count 0 2006.252.07:42:40.68#ibcon#read 4, iclass 13, count 0 2006.252.07:42:40.68#ibcon#about to read 5, iclass 13, count 0 2006.252.07:42:40.68#ibcon#read 5, iclass 13, count 0 2006.252.07:42:40.68#ibcon#about to read 6, iclass 13, count 0 2006.252.07:42:40.68#ibcon#read 6, iclass 13, count 0 2006.252.07:42:40.68#ibcon#end of sib2, iclass 13, count 0 2006.252.07:42:40.68#ibcon#*after write, iclass 13, count 0 2006.252.07:42:40.68#ibcon#*before return 0, iclass 13, count 0 2006.252.07:42:40.68#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.252.07:42:40.68#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.252.07:42:40.68#ibcon#about to clear, iclass 13 cls_cnt 0 2006.252.07:42:40.68#ibcon#cleared, iclass 13 cls_cnt 0 2006.252.07:42:40.68$vc4f8/vb=1,4 2006.252.07:42:40.68#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.252.07:42:40.68#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.252.07:42:40.68#ibcon#ireg 11 cls_cnt 2 2006.252.07:42:40.68#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.252.07:42:40.68#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.252.07:42:40.68#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.252.07:42:40.68#ibcon#enter wrdev, iclass 15, count 2 2006.252.07:42:40.68#ibcon#first serial, iclass 15, count 2 2006.252.07:42:40.68#ibcon#enter sib2, iclass 15, count 2 2006.252.07:42:40.68#ibcon#flushed, iclass 15, count 2 2006.252.07:42:40.68#ibcon#about to write, iclass 15, count 2 2006.252.07:42:40.68#ibcon#wrote, iclass 15, count 2 2006.252.07:42:40.68#ibcon#about to read 3, iclass 15, count 2 2006.252.07:42:40.70#ibcon#read 3, iclass 15, count 2 2006.252.07:42:40.70#ibcon#about to read 4, iclass 15, count 2 2006.252.07:42:40.70#ibcon#read 4, iclass 15, count 2 2006.252.07:42:40.70#ibcon#about to read 5, iclass 15, count 2 2006.252.07:42:40.70#ibcon#read 5, iclass 15, count 2 2006.252.07:42:40.70#ibcon#about to read 6, iclass 15, count 2 2006.252.07:42:40.70#ibcon#read 6, iclass 15, count 2 2006.252.07:42:40.70#ibcon#end of sib2, iclass 15, count 2 2006.252.07:42:40.70#ibcon#*mode == 0, iclass 15, count 2 2006.252.07:42:40.70#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.252.07:42:40.70#ibcon#[27=AT01-04\r\n] 2006.252.07:42:40.70#ibcon#*before write, iclass 15, count 2 2006.252.07:42:40.70#ibcon#enter sib2, iclass 15, count 2 2006.252.07:42:40.70#ibcon#flushed, iclass 15, count 2 2006.252.07:42:40.70#ibcon#about to write, iclass 15, count 2 2006.252.07:42:40.70#ibcon#wrote, iclass 15, count 2 2006.252.07:42:40.70#ibcon#about to read 3, iclass 15, count 2 2006.252.07:42:40.73#ibcon#read 3, iclass 15, count 2 2006.252.07:42:40.73#ibcon#about to read 4, iclass 15, count 2 2006.252.07:42:40.73#ibcon#read 4, iclass 15, count 2 2006.252.07:42:40.73#ibcon#about to read 5, iclass 15, count 2 2006.252.07:42:40.73#ibcon#read 5, iclass 15, count 2 2006.252.07:42:40.73#ibcon#about to read 6, iclass 15, count 2 2006.252.07:42:40.73#ibcon#read 6, iclass 15, count 2 2006.252.07:42:40.73#ibcon#end of sib2, iclass 15, count 2 2006.252.07:42:40.73#ibcon#*after write, iclass 15, count 2 2006.252.07:42:40.73#ibcon#*before return 0, iclass 15, count 2 2006.252.07:42:40.73#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.252.07:42:40.73#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.252.07:42:40.73#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.252.07:42:40.73#ibcon#ireg 7 cls_cnt 0 2006.252.07:42:40.73#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.252.07:42:40.85#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.252.07:42:40.85#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.252.07:42:40.85#ibcon#enter wrdev, iclass 15, count 0 2006.252.07:42:40.85#ibcon#first serial, iclass 15, count 0 2006.252.07:42:40.85#ibcon#enter sib2, iclass 15, count 0 2006.252.07:42:40.85#ibcon#flushed, iclass 15, count 0 2006.252.07:42:40.85#ibcon#about to write, iclass 15, count 0 2006.252.07:42:40.85#ibcon#wrote, iclass 15, count 0 2006.252.07:42:40.85#ibcon#about to read 3, iclass 15, count 0 2006.252.07:42:40.87#ibcon#read 3, iclass 15, count 0 2006.252.07:42:40.87#ibcon#about to read 4, iclass 15, count 0 2006.252.07:42:40.87#ibcon#read 4, iclass 15, count 0 2006.252.07:42:40.87#ibcon#about to read 5, iclass 15, count 0 2006.252.07:42:40.87#ibcon#read 5, iclass 15, count 0 2006.252.07:42:40.87#ibcon#about to read 6, iclass 15, count 0 2006.252.07:42:40.87#ibcon#read 6, iclass 15, count 0 2006.252.07:42:40.87#ibcon#end of sib2, iclass 15, count 0 2006.252.07:42:40.87#ibcon#*mode == 0, iclass 15, count 0 2006.252.07:42:40.87#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.252.07:42:40.87#ibcon#[27=USB\r\n] 2006.252.07:42:40.87#ibcon#*before write, iclass 15, count 0 2006.252.07:42:40.87#ibcon#enter sib2, iclass 15, count 0 2006.252.07:42:40.87#ibcon#flushed, iclass 15, count 0 2006.252.07:42:40.87#ibcon#about to write, iclass 15, count 0 2006.252.07:42:40.87#ibcon#wrote, iclass 15, count 0 2006.252.07:42:40.87#ibcon#about to read 3, iclass 15, count 0 2006.252.07:42:40.90#ibcon#read 3, iclass 15, count 0 2006.252.07:42:40.90#ibcon#about to read 4, iclass 15, count 0 2006.252.07:42:40.90#ibcon#read 4, iclass 15, count 0 2006.252.07:42:40.90#ibcon#about to read 5, iclass 15, count 0 2006.252.07:42:40.90#ibcon#read 5, iclass 15, count 0 2006.252.07:42:40.90#ibcon#about to read 6, iclass 15, count 0 2006.252.07:42:40.90#ibcon#read 6, iclass 15, count 0 2006.252.07:42:40.90#ibcon#end of sib2, iclass 15, count 0 2006.252.07:42:40.90#ibcon#*after write, iclass 15, count 0 2006.252.07:42:40.90#ibcon#*before return 0, iclass 15, count 0 2006.252.07:42:40.90#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.252.07:42:40.90#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.252.07:42:40.90#ibcon#about to clear, iclass 15 cls_cnt 0 2006.252.07:42:40.90#ibcon#cleared, iclass 15 cls_cnt 0 2006.252.07:42:40.90$vc4f8/vblo=2,640.99 2006.252.07:42:40.90#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.252.07:42:40.90#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.252.07:42:40.90#ibcon#ireg 17 cls_cnt 0 2006.252.07:42:40.90#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.252.07:42:40.90#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.252.07:42:40.90#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.252.07:42:40.90#ibcon#enter wrdev, iclass 17, count 0 2006.252.07:42:40.90#ibcon#first serial, iclass 17, count 0 2006.252.07:42:40.90#ibcon#enter sib2, iclass 17, count 0 2006.252.07:42:40.90#ibcon#flushed, iclass 17, count 0 2006.252.07:42:40.90#ibcon#about to write, iclass 17, count 0 2006.252.07:42:40.90#ibcon#wrote, iclass 17, count 0 2006.252.07:42:40.90#ibcon#about to read 3, iclass 17, count 0 2006.252.07:42:40.92#ibcon#read 3, iclass 17, count 0 2006.252.07:42:40.92#ibcon#about to read 4, iclass 17, count 0 2006.252.07:42:40.92#ibcon#read 4, iclass 17, count 0 2006.252.07:42:40.92#ibcon#about to read 5, iclass 17, count 0 2006.252.07:42:40.92#ibcon#read 5, iclass 17, count 0 2006.252.07:42:40.92#ibcon#about to read 6, iclass 17, count 0 2006.252.07:42:40.92#ibcon#read 6, iclass 17, count 0 2006.252.07:42:40.92#ibcon#end of sib2, iclass 17, count 0 2006.252.07:42:40.92#ibcon#*mode == 0, iclass 17, count 0 2006.252.07:42:40.92#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.252.07:42:40.92#ibcon#[28=FRQ=02,640.99\r\n] 2006.252.07:42:40.92#ibcon#*before write, iclass 17, count 0 2006.252.07:42:40.92#ibcon#enter sib2, iclass 17, count 0 2006.252.07:42:40.92#ibcon#flushed, iclass 17, count 0 2006.252.07:42:40.92#ibcon#about to write, iclass 17, count 0 2006.252.07:42:40.92#ibcon#wrote, iclass 17, count 0 2006.252.07:42:40.92#ibcon#about to read 3, iclass 17, count 0 2006.252.07:42:40.96#ibcon#read 3, iclass 17, count 0 2006.252.07:42:40.96#ibcon#about to read 4, iclass 17, count 0 2006.252.07:42:40.96#ibcon#read 4, iclass 17, count 0 2006.252.07:42:40.96#ibcon#about to read 5, iclass 17, count 0 2006.252.07:42:40.96#ibcon#read 5, iclass 17, count 0 2006.252.07:42:40.96#ibcon#about to read 6, iclass 17, count 0 2006.252.07:42:40.96#ibcon#read 6, iclass 17, count 0 2006.252.07:42:40.96#ibcon#end of sib2, iclass 17, count 0 2006.252.07:42:40.96#ibcon#*after write, iclass 17, count 0 2006.252.07:42:40.96#ibcon#*before return 0, iclass 17, count 0 2006.252.07:42:40.96#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.252.07:42:40.96#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.252.07:42:40.96#ibcon#about to clear, iclass 17 cls_cnt 0 2006.252.07:42:40.96#ibcon#cleared, iclass 17 cls_cnt 0 2006.252.07:42:40.96$vc4f8/vb=2,5 2006.252.07:42:40.96#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.252.07:42:40.96#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.252.07:42:40.96#ibcon#ireg 11 cls_cnt 2 2006.252.07:42:40.96#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.252.07:42:41.02#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.252.07:42:41.02#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.252.07:42:41.02#ibcon#enter wrdev, iclass 19, count 2 2006.252.07:42:41.02#ibcon#first serial, iclass 19, count 2 2006.252.07:42:41.02#ibcon#enter sib2, iclass 19, count 2 2006.252.07:42:41.02#ibcon#flushed, iclass 19, count 2 2006.252.07:42:41.02#ibcon#about to write, iclass 19, count 2 2006.252.07:42:41.02#ibcon#wrote, iclass 19, count 2 2006.252.07:42:41.02#ibcon#about to read 3, iclass 19, count 2 2006.252.07:42:41.04#ibcon#read 3, iclass 19, count 2 2006.252.07:42:41.04#ibcon#about to read 4, iclass 19, count 2 2006.252.07:42:41.04#ibcon#read 4, iclass 19, count 2 2006.252.07:42:41.04#ibcon#about to read 5, iclass 19, count 2 2006.252.07:42:41.04#ibcon#read 5, iclass 19, count 2 2006.252.07:42:41.04#ibcon#about to read 6, iclass 19, count 2 2006.252.07:42:41.04#ibcon#read 6, iclass 19, count 2 2006.252.07:42:41.04#ibcon#end of sib2, iclass 19, count 2 2006.252.07:42:41.04#ibcon#*mode == 0, iclass 19, count 2 2006.252.07:42:41.04#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.252.07:42:41.04#ibcon#[27=AT02-05\r\n] 2006.252.07:42:41.04#ibcon#*before write, iclass 19, count 2 2006.252.07:42:41.04#ibcon#enter sib2, iclass 19, count 2 2006.252.07:42:41.04#ibcon#flushed, iclass 19, count 2 2006.252.07:42:41.04#ibcon#about to write, iclass 19, count 2 2006.252.07:42:41.04#ibcon#wrote, iclass 19, count 2 2006.252.07:42:41.04#ibcon#about to read 3, iclass 19, count 2 2006.252.07:42:41.07#ibcon#read 3, iclass 19, count 2 2006.252.07:42:41.07#ibcon#about to read 4, iclass 19, count 2 2006.252.07:42:41.07#ibcon#read 4, iclass 19, count 2 2006.252.07:42:41.07#ibcon#about to read 5, iclass 19, count 2 2006.252.07:42:41.07#ibcon#read 5, iclass 19, count 2 2006.252.07:42:41.07#ibcon#about to read 6, iclass 19, count 2 2006.252.07:42:41.07#ibcon#read 6, iclass 19, count 2 2006.252.07:42:41.07#ibcon#end of sib2, iclass 19, count 2 2006.252.07:42:41.07#ibcon#*after write, iclass 19, count 2 2006.252.07:42:41.07#ibcon#*before return 0, iclass 19, count 2 2006.252.07:42:41.07#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.252.07:42:41.07#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.252.07:42:41.07#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.252.07:42:41.07#ibcon#ireg 7 cls_cnt 0 2006.252.07:42:41.07#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.252.07:42:41.19#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.252.07:42:41.19#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.252.07:42:41.19#ibcon#enter wrdev, iclass 19, count 0 2006.252.07:42:41.19#ibcon#first serial, iclass 19, count 0 2006.252.07:42:41.19#ibcon#enter sib2, iclass 19, count 0 2006.252.07:42:41.19#ibcon#flushed, iclass 19, count 0 2006.252.07:42:41.19#ibcon#about to write, iclass 19, count 0 2006.252.07:42:41.19#ibcon#wrote, iclass 19, count 0 2006.252.07:42:41.19#ibcon#about to read 3, iclass 19, count 0 2006.252.07:42:41.21#ibcon#read 3, iclass 19, count 0 2006.252.07:42:41.21#ibcon#about to read 4, iclass 19, count 0 2006.252.07:42:41.21#ibcon#read 4, iclass 19, count 0 2006.252.07:42:41.21#ibcon#about to read 5, iclass 19, count 0 2006.252.07:42:41.21#ibcon#read 5, iclass 19, count 0 2006.252.07:42:41.21#ibcon#about to read 6, iclass 19, count 0 2006.252.07:42:41.21#ibcon#read 6, iclass 19, count 0 2006.252.07:42:41.21#ibcon#end of sib2, iclass 19, count 0 2006.252.07:42:41.21#ibcon#*mode == 0, iclass 19, count 0 2006.252.07:42:41.21#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.252.07:42:41.21#ibcon#[27=USB\r\n] 2006.252.07:42:41.21#ibcon#*before write, iclass 19, count 0 2006.252.07:42:41.21#ibcon#enter sib2, iclass 19, count 0 2006.252.07:42:41.21#ibcon#flushed, iclass 19, count 0 2006.252.07:42:41.21#ibcon#about to write, iclass 19, count 0 2006.252.07:42:41.21#ibcon#wrote, iclass 19, count 0 2006.252.07:42:41.21#ibcon#about to read 3, iclass 19, count 0 2006.252.07:42:41.24#ibcon#read 3, iclass 19, count 0 2006.252.07:42:41.24#ibcon#about to read 4, iclass 19, count 0 2006.252.07:42:41.24#ibcon#read 4, iclass 19, count 0 2006.252.07:42:41.24#ibcon#about to read 5, iclass 19, count 0 2006.252.07:42:41.24#ibcon#read 5, iclass 19, count 0 2006.252.07:42:41.24#ibcon#about to read 6, iclass 19, count 0 2006.252.07:42:41.24#ibcon#read 6, iclass 19, count 0 2006.252.07:42:41.24#ibcon#end of sib2, iclass 19, count 0 2006.252.07:42:41.24#ibcon#*after write, iclass 19, count 0 2006.252.07:42:41.24#ibcon#*before return 0, iclass 19, count 0 2006.252.07:42:41.24#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.252.07:42:41.24#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.252.07:42:41.24#ibcon#about to clear, iclass 19 cls_cnt 0 2006.252.07:42:41.24#ibcon#cleared, iclass 19 cls_cnt 0 2006.252.07:42:41.24$vc4f8/vblo=3,656.99 2006.252.07:42:41.24#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.252.07:42:41.24#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.252.07:42:41.24#ibcon#ireg 17 cls_cnt 0 2006.252.07:42:41.24#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.252.07:42:41.24#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.252.07:42:41.24#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.252.07:42:41.24#ibcon#enter wrdev, iclass 21, count 0 2006.252.07:42:41.24#ibcon#first serial, iclass 21, count 0 2006.252.07:42:41.24#ibcon#enter sib2, iclass 21, count 0 2006.252.07:42:41.24#ibcon#flushed, iclass 21, count 0 2006.252.07:42:41.24#ibcon#about to write, iclass 21, count 0 2006.252.07:42:41.24#ibcon#wrote, iclass 21, count 0 2006.252.07:42:41.24#ibcon#about to read 3, iclass 21, count 0 2006.252.07:42:41.26#ibcon#read 3, iclass 21, count 0 2006.252.07:42:41.26#ibcon#about to read 4, iclass 21, count 0 2006.252.07:42:41.26#ibcon#read 4, iclass 21, count 0 2006.252.07:42:41.26#ibcon#about to read 5, iclass 21, count 0 2006.252.07:42:41.26#ibcon#read 5, iclass 21, count 0 2006.252.07:42:41.26#ibcon#about to read 6, iclass 21, count 0 2006.252.07:42:41.26#ibcon#read 6, iclass 21, count 0 2006.252.07:42:41.26#ibcon#end of sib2, iclass 21, count 0 2006.252.07:42:41.26#ibcon#*mode == 0, iclass 21, count 0 2006.252.07:42:41.26#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.252.07:42:41.26#ibcon#[28=FRQ=03,656.99\r\n] 2006.252.07:42:41.26#ibcon#*before write, iclass 21, count 0 2006.252.07:42:41.26#ibcon#enter sib2, iclass 21, count 0 2006.252.07:42:41.26#ibcon#flushed, iclass 21, count 0 2006.252.07:42:41.26#ibcon#about to write, iclass 21, count 0 2006.252.07:42:41.26#ibcon#wrote, iclass 21, count 0 2006.252.07:42:41.26#ibcon#about to read 3, iclass 21, count 0 2006.252.07:42:41.30#ibcon#read 3, iclass 21, count 0 2006.252.07:42:41.30#ibcon#about to read 4, iclass 21, count 0 2006.252.07:42:41.30#ibcon#read 4, iclass 21, count 0 2006.252.07:42:41.30#ibcon#about to read 5, iclass 21, count 0 2006.252.07:42:41.30#ibcon#read 5, iclass 21, count 0 2006.252.07:42:41.30#ibcon#about to read 6, iclass 21, count 0 2006.252.07:42:41.30#ibcon#read 6, iclass 21, count 0 2006.252.07:42:41.30#ibcon#end of sib2, iclass 21, count 0 2006.252.07:42:41.30#ibcon#*after write, iclass 21, count 0 2006.252.07:42:41.30#ibcon#*before return 0, iclass 21, count 0 2006.252.07:42:41.30#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.252.07:42:41.30#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.252.07:42:41.30#ibcon#about to clear, iclass 21 cls_cnt 0 2006.252.07:42:41.30#ibcon#cleared, iclass 21 cls_cnt 0 2006.252.07:42:41.30$vc4f8/vb=3,4 2006.252.07:42:41.30#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.252.07:42:41.30#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.252.07:42:41.30#ibcon#ireg 11 cls_cnt 2 2006.252.07:42:41.30#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.252.07:42:41.36#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.252.07:42:41.36#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.252.07:42:41.36#ibcon#enter wrdev, iclass 23, count 2 2006.252.07:42:41.36#ibcon#first serial, iclass 23, count 2 2006.252.07:42:41.36#ibcon#enter sib2, iclass 23, count 2 2006.252.07:42:41.36#ibcon#flushed, iclass 23, count 2 2006.252.07:42:41.36#ibcon#about to write, iclass 23, count 2 2006.252.07:42:41.36#ibcon#wrote, iclass 23, count 2 2006.252.07:42:41.36#ibcon#about to read 3, iclass 23, count 2 2006.252.07:42:41.38#ibcon#read 3, iclass 23, count 2 2006.252.07:42:41.38#ibcon#about to read 4, iclass 23, count 2 2006.252.07:42:41.38#ibcon#read 4, iclass 23, count 2 2006.252.07:42:41.38#ibcon#about to read 5, iclass 23, count 2 2006.252.07:42:41.38#ibcon#read 5, iclass 23, count 2 2006.252.07:42:41.38#ibcon#about to read 6, iclass 23, count 2 2006.252.07:42:41.38#ibcon#read 6, iclass 23, count 2 2006.252.07:42:41.38#ibcon#end of sib2, iclass 23, count 2 2006.252.07:42:41.38#ibcon#*mode == 0, iclass 23, count 2 2006.252.07:42:41.38#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.252.07:42:41.38#ibcon#[27=AT03-04\r\n] 2006.252.07:42:41.38#ibcon#*before write, iclass 23, count 2 2006.252.07:42:41.38#ibcon#enter sib2, iclass 23, count 2 2006.252.07:42:41.38#ibcon#flushed, iclass 23, count 2 2006.252.07:42:41.38#ibcon#about to write, iclass 23, count 2 2006.252.07:42:41.38#ibcon#wrote, iclass 23, count 2 2006.252.07:42:41.38#ibcon#about to read 3, iclass 23, count 2 2006.252.07:42:41.41#ibcon#read 3, iclass 23, count 2 2006.252.07:42:41.41#ibcon#about to read 4, iclass 23, count 2 2006.252.07:42:41.41#ibcon#read 4, iclass 23, count 2 2006.252.07:42:41.41#ibcon#about to read 5, iclass 23, count 2 2006.252.07:42:41.41#ibcon#read 5, iclass 23, count 2 2006.252.07:42:41.41#ibcon#about to read 6, iclass 23, count 2 2006.252.07:42:41.41#ibcon#read 6, iclass 23, count 2 2006.252.07:42:41.41#ibcon#end of sib2, iclass 23, count 2 2006.252.07:42:41.41#ibcon#*after write, iclass 23, count 2 2006.252.07:42:41.41#ibcon#*before return 0, iclass 23, count 2 2006.252.07:42:41.41#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.252.07:42:41.41#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.252.07:42:41.41#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.252.07:42:41.41#ibcon#ireg 7 cls_cnt 0 2006.252.07:42:41.41#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.252.07:42:41.53#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.252.07:42:41.53#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.252.07:42:41.53#ibcon#enter wrdev, iclass 23, count 0 2006.252.07:42:41.53#ibcon#first serial, iclass 23, count 0 2006.252.07:42:41.53#ibcon#enter sib2, iclass 23, count 0 2006.252.07:42:41.53#ibcon#flushed, iclass 23, count 0 2006.252.07:42:41.53#ibcon#about to write, iclass 23, count 0 2006.252.07:42:41.53#ibcon#wrote, iclass 23, count 0 2006.252.07:42:41.53#ibcon#about to read 3, iclass 23, count 0 2006.252.07:42:41.55#ibcon#read 3, iclass 23, count 0 2006.252.07:42:41.55#ibcon#about to read 4, iclass 23, count 0 2006.252.07:42:41.55#ibcon#read 4, iclass 23, count 0 2006.252.07:42:41.55#ibcon#about to read 5, iclass 23, count 0 2006.252.07:42:41.55#ibcon#read 5, iclass 23, count 0 2006.252.07:42:41.55#ibcon#about to read 6, iclass 23, count 0 2006.252.07:42:41.55#ibcon#read 6, iclass 23, count 0 2006.252.07:42:41.55#ibcon#end of sib2, iclass 23, count 0 2006.252.07:42:41.55#ibcon#*mode == 0, iclass 23, count 0 2006.252.07:42:41.55#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.252.07:42:41.55#ibcon#[27=USB\r\n] 2006.252.07:42:41.55#ibcon#*before write, iclass 23, count 0 2006.252.07:42:41.55#ibcon#enter sib2, iclass 23, count 0 2006.252.07:42:41.55#ibcon#flushed, iclass 23, count 0 2006.252.07:42:41.55#ibcon#about to write, iclass 23, count 0 2006.252.07:42:41.55#ibcon#wrote, iclass 23, count 0 2006.252.07:42:41.55#ibcon#about to read 3, iclass 23, count 0 2006.252.07:42:41.58#ibcon#read 3, iclass 23, count 0 2006.252.07:42:41.58#ibcon#about to read 4, iclass 23, count 0 2006.252.07:42:41.58#ibcon#read 4, iclass 23, count 0 2006.252.07:42:41.58#ibcon#about to read 5, iclass 23, count 0 2006.252.07:42:41.58#ibcon#read 5, iclass 23, count 0 2006.252.07:42:41.58#ibcon#about to read 6, iclass 23, count 0 2006.252.07:42:41.58#ibcon#read 6, iclass 23, count 0 2006.252.07:42:41.58#ibcon#end of sib2, iclass 23, count 0 2006.252.07:42:41.58#ibcon#*after write, iclass 23, count 0 2006.252.07:42:41.58#ibcon#*before return 0, iclass 23, count 0 2006.252.07:42:41.58#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.252.07:42:41.58#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.252.07:42:41.58#ibcon#about to clear, iclass 23 cls_cnt 0 2006.252.07:42:41.58#ibcon#cleared, iclass 23 cls_cnt 0 2006.252.07:42:41.58$vc4f8/vblo=4,712.99 2006.252.07:42:41.58#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.252.07:42:41.58#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.252.07:42:41.58#ibcon#ireg 17 cls_cnt 0 2006.252.07:42:41.58#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.252.07:42:41.58#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.252.07:42:41.58#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.252.07:42:41.58#ibcon#enter wrdev, iclass 25, count 0 2006.252.07:42:41.58#ibcon#first serial, iclass 25, count 0 2006.252.07:42:41.58#ibcon#enter sib2, iclass 25, count 0 2006.252.07:42:41.58#ibcon#flushed, iclass 25, count 0 2006.252.07:42:41.58#ibcon#about to write, iclass 25, count 0 2006.252.07:42:41.58#ibcon#wrote, iclass 25, count 0 2006.252.07:42:41.58#ibcon#about to read 3, iclass 25, count 0 2006.252.07:42:41.60#ibcon#read 3, iclass 25, count 0 2006.252.07:42:41.60#ibcon#about to read 4, iclass 25, count 0 2006.252.07:42:41.60#ibcon#read 4, iclass 25, count 0 2006.252.07:42:41.60#ibcon#about to read 5, iclass 25, count 0 2006.252.07:42:41.60#ibcon#read 5, iclass 25, count 0 2006.252.07:42:41.60#ibcon#about to read 6, iclass 25, count 0 2006.252.07:42:41.60#ibcon#read 6, iclass 25, count 0 2006.252.07:42:41.60#ibcon#end of sib2, iclass 25, count 0 2006.252.07:42:41.60#ibcon#*mode == 0, iclass 25, count 0 2006.252.07:42:41.60#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.252.07:42:41.60#ibcon#[28=FRQ=04,712.99\r\n] 2006.252.07:42:41.60#ibcon#*before write, iclass 25, count 0 2006.252.07:42:41.60#ibcon#enter sib2, iclass 25, count 0 2006.252.07:42:41.60#ibcon#flushed, iclass 25, count 0 2006.252.07:42:41.60#ibcon#about to write, iclass 25, count 0 2006.252.07:42:41.60#ibcon#wrote, iclass 25, count 0 2006.252.07:42:41.60#ibcon#about to read 3, iclass 25, count 0 2006.252.07:42:41.64#ibcon#read 3, iclass 25, count 0 2006.252.07:42:41.64#ibcon#about to read 4, iclass 25, count 0 2006.252.07:42:41.64#ibcon#read 4, iclass 25, count 0 2006.252.07:42:41.64#ibcon#about to read 5, iclass 25, count 0 2006.252.07:42:41.64#ibcon#read 5, iclass 25, count 0 2006.252.07:42:41.64#ibcon#about to read 6, iclass 25, count 0 2006.252.07:42:41.64#ibcon#read 6, iclass 25, count 0 2006.252.07:42:41.64#ibcon#end of sib2, iclass 25, count 0 2006.252.07:42:41.64#ibcon#*after write, iclass 25, count 0 2006.252.07:42:41.64#ibcon#*before return 0, iclass 25, count 0 2006.252.07:42:41.64#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.252.07:42:41.64#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.252.07:42:41.64#ibcon#about to clear, iclass 25 cls_cnt 0 2006.252.07:42:41.64#ibcon#cleared, iclass 25 cls_cnt 0 2006.252.07:42:41.64$vc4f8/vb=4,4 2006.252.07:42:41.64#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.252.07:42:41.64#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.252.07:42:41.64#ibcon#ireg 11 cls_cnt 2 2006.252.07:42:41.64#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.252.07:42:41.70#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.252.07:42:41.70#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.252.07:42:41.70#ibcon#enter wrdev, iclass 27, count 2 2006.252.07:42:41.70#ibcon#first serial, iclass 27, count 2 2006.252.07:42:41.70#ibcon#enter sib2, iclass 27, count 2 2006.252.07:42:41.70#ibcon#flushed, iclass 27, count 2 2006.252.07:42:41.70#ibcon#about to write, iclass 27, count 2 2006.252.07:42:41.70#ibcon#wrote, iclass 27, count 2 2006.252.07:42:41.70#ibcon#about to read 3, iclass 27, count 2 2006.252.07:42:41.72#ibcon#read 3, iclass 27, count 2 2006.252.07:42:41.72#ibcon#about to read 4, iclass 27, count 2 2006.252.07:42:41.72#ibcon#read 4, iclass 27, count 2 2006.252.07:42:41.72#ibcon#about to read 5, iclass 27, count 2 2006.252.07:42:41.72#ibcon#read 5, iclass 27, count 2 2006.252.07:42:41.72#ibcon#about to read 6, iclass 27, count 2 2006.252.07:42:41.72#ibcon#read 6, iclass 27, count 2 2006.252.07:42:41.72#ibcon#end of sib2, iclass 27, count 2 2006.252.07:42:41.72#ibcon#*mode == 0, iclass 27, count 2 2006.252.07:42:41.72#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.252.07:42:41.72#ibcon#[27=AT04-04\r\n] 2006.252.07:42:41.72#ibcon#*before write, iclass 27, count 2 2006.252.07:42:41.72#ibcon#enter sib2, iclass 27, count 2 2006.252.07:42:41.72#ibcon#flushed, iclass 27, count 2 2006.252.07:42:41.72#ibcon#about to write, iclass 27, count 2 2006.252.07:42:41.72#ibcon#wrote, iclass 27, count 2 2006.252.07:42:41.72#ibcon#about to read 3, iclass 27, count 2 2006.252.07:42:41.75#ibcon#read 3, iclass 27, count 2 2006.252.07:42:41.75#ibcon#about to read 4, iclass 27, count 2 2006.252.07:42:41.75#ibcon#read 4, iclass 27, count 2 2006.252.07:42:41.75#ibcon#about to read 5, iclass 27, count 2 2006.252.07:42:41.75#ibcon#read 5, iclass 27, count 2 2006.252.07:42:41.75#ibcon#about to read 6, iclass 27, count 2 2006.252.07:42:41.75#ibcon#read 6, iclass 27, count 2 2006.252.07:42:41.75#ibcon#end of sib2, iclass 27, count 2 2006.252.07:42:41.75#ibcon#*after write, iclass 27, count 2 2006.252.07:42:41.75#ibcon#*before return 0, iclass 27, count 2 2006.252.07:42:41.75#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.252.07:42:41.75#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.252.07:42:41.75#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.252.07:42:41.75#ibcon#ireg 7 cls_cnt 0 2006.252.07:42:41.75#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.252.07:42:41.87#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.252.07:42:41.87#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.252.07:42:41.87#ibcon#enter wrdev, iclass 27, count 0 2006.252.07:42:41.87#ibcon#first serial, iclass 27, count 0 2006.252.07:42:41.87#ibcon#enter sib2, iclass 27, count 0 2006.252.07:42:41.87#ibcon#flushed, iclass 27, count 0 2006.252.07:42:41.87#ibcon#about to write, iclass 27, count 0 2006.252.07:42:41.87#ibcon#wrote, iclass 27, count 0 2006.252.07:42:41.87#ibcon#about to read 3, iclass 27, count 0 2006.252.07:42:41.89#ibcon#read 3, iclass 27, count 0 2006.252.07:42:41.89#ibcon#about to read 4, iclass 27, count 0 2006.252.07:42:41.89#ibcon#read 4, iclass 27, count 0 2006.252.07:42:41.89#ibcon#about to read 5, iclass 27, count 0 2006.252.07:42:41.89#ibcon#read 5, iclass 27, count 0 2006.252.07:42:41.89#ibcon#about to read 6, iclass 27, count 0 2006.252.07:42:41.89#ibcon#read 6, iclass 27, count 0 2006.252.07:42:41.89#ibcon#end of sib2, iclass 27, count 0 2006.252.07:42:41.89#ibcon#*mode == 0, iclass 27, count 0 2006.252.07:42:41.89#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.252.07:42:41.89#ibcon#[27=USB\r\n] 2006.252.07:42:41.89#ibcon#*before write, iclass 27, count 0 2006.252.07:42:41.89#ibcon#enter sib2, iclass 27, count 0 2006.252.07:42:41.89#ibcon#flushed, iclass 27, count 0 2006.252.07:42:41.89#ibcon#about to write, iclass 27, count 0 2006.252.07:42:41.89#ibcon#wrote, iclass 27, count 0 2006.252.07:42:41.89#ibcon#about to read 3, iclass 27, count 0 2006.252.07:42:41.92#ibcon#read 3, iclass 27, count 0 2006.252.07:42:41.92#ibcon#about to read 4, iclass 27, count 0 2006.252.07:42:41.92#ibcon#read 4, iclass 27, count 0 2006.252.07:42:41.92#ibcon#about to read 5, iclass 27, count 0 2006.252.07:42:41.92#ibcon#read 5, iclass 27, count 0 2006.252.07:42:41.92#ibcon#about to read 6, iclass 27, count 0 2006.252.07:42:41.92#ibcon#read 6, iclass 27, count 0 2006.252.07:42:41.92#ibcon#end of sib2, iclass 27, count 0 2006.252.07:42:41.92#ibcon#*after write, iclass 27, count 0 2006.252.07:42:41.92#ibcon#*before return 0, iclass 27, count 0 2006.252.07:42:41.92#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.252.07:42:41.92#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.252.07:42:41.92#ibcon#about to clear, iclass 27 cls_cnt 0 2006.252.07:42:41.92#ibcon#cleared, iclass 27 cls_cnt 0 2006.252.07:42:41.92$vc4f8/vblo=5,744.99 2006.252.07:42:41.92#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.252.07:42:41.92#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.252.07:42:41.92#ibcon#ireg 17 cls_cnt 0 2006.252.07:42:41.92#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.252.07:42:41.92#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.252.07:42:41.92#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.252.07:42:41.92#ibcon#enter wrdev, iclass 29, count 0 2006.252.07:42:41.92#ibcon#first serial, iclass 29, count 0 2006.252.07:42:41.92#ibcon#enter sib2, iclass 29, count 0 2006.252.07:42:41.92#ibcon#flushed, iclass 29, count 0 2006.252.07:42:41.92#ibcon#about to write, iclass 29, count 0 2006.252.07:42:41.92#ibcon#wrote, iclass 29, count 0 2006.252.07:42:41.92#ibcon#about to read 3, iclass 29, count 0 2006.252.07:42:41.94#ibcon#read 3, iclass 29, count 0 2006.252.07:42:41.94#ibcon#about to read 4, iclass 29, count 0 2006.252.07:42:41.94#ibcon#read 4, iclass 29, count 0 2006.252.07:42:41.94#ibcon#about to read 5, iclass 29, count 0 2006.252.07:42:41.94#ibcon#read 5, iclass 29, count 0 2006.252.07:42:41.94#ibcon#about to read 6, iclass 29, count 0 2006.252.07:42:41.94#ibcon#read 6, iclass 29, count 0 2006.252.07:42:41.94#ibcon#end of sib2, iclass 29, count 0 2006.252.07:42:41.94#ibcon#*mode == 0, iclass 29, count 0 2006.252.07:42:41.94#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.252.07:42:41.94#ibcon#[28=FRQ=05,744.99\r\n] 2006.252.07:42:41.94#ibcon#*before write, iclass 29, count 0 2006.252.07:42:41.94#ibcon#enter sib2, iclass 29, count 0 2006.252.07:42:41.94#ibcon#flushed, iclass 29, count 0 2006.252.07:42:41.94#ibcon#about to write, iclass 29, count 0 2006.252.07:42:41.94#ibcon#wrote, iclass 29, count 0 2006.252.07:42:41.94#ibcon#about to read 3, iclass 29, count 0 2006.252.07:42:41.98#ibcon#read 3, iclass 29, count 0 2006.252.07:42:41.98#ibcon#about to read 4, iclass 29, count 0 2006.252.07:42:41.98#ibcon#read 4, iclass 29, count 0 2006.252.07:42:41.98#ibcon#about to read 5, iclass 29, count 0 2006.252.07:42:41.98#ibcon#read 5, iclass 29, count 0 2006.252.07:42:41.98#ibcon#about to read 6, iclass 29, count 0 2006.252.07:42:41.98#ibcon#read 6, iclass 29, count 0 2006.252.07:42:41.98#ibcon#end of sib2, iclass 29, count 0 2006.252.07:42:41.98#ibcon#*after write, iclass 29, count 0 2006.252.07:42:41.98#ibcon#*before return 0, iclass 29, count 0 2006.252.07:42:41.98#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.252.07:42:41.98#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.252.07:42:41.98#ibcon#about to clear, iclass 29 cls_cnt 0 2006.252.07:42:41.98#ibcon#cleared, iclass 29 cls_cnt 0 2006.252.07:42:41.98$vc4f8/vb=5,4 2006.252.07:42:41.98#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.252.07:42:41.98#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.252.07:42:41.98#ibcon#ireg 11 cls_cnt 2 2006.252.07:42:41.98#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.252.07:42:42.05#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.252.07:42:42.05#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.252.07:42:42.05#ibcon#enter wrdev, iclass 31, count 2 2006.252.07:42:42.05#ibcon#first serial, iclass 31, count 2 2006.252.07:42:42.05#ibcon#enter sib2, iclass 31, count 2 2006.252.07:42:42.05#ibcon#flushed, iclass 31, count 2 2006.252.07:42:42.05#ibcon#about to write, iclass 31, count 2 2006.252.07:42:42.05#ibcon#wrote, iclass 31, count 2 2006.252.07:42:42.05#ibcon#about to read 3, iclass 31, count 2 2006.252.07:42:42.06#ibcon#read 3, iclass 31, count 2 2006.252.07:42:42.06#ibcon#about to read 4, iclass 31, count 2 2006.252.07:42:42.06#ibcon#read 4, iclass 31, count 2 2006.252.07:42:42.06#ibcon#about to read 5, iclass 31, count 2 2006.252.07:42:42.06#ibcon#read 5, iclass 31, count 2 2006.252.07:42:42.06#ibcon#about to read 6, iclass 31, count 2 2006.252.07:42:42.06#ibcon#read 6, iclass 31, count 2 2006.252.07:42:42.06#ibcon#end of sib2, iclass 31, count 2 2006.252.07:42:42.06#ibcon#*mode == 0, iclass 31, count 2 2006.252.07:42:42.06#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.252.07:42:42.06#ibcon#[27=AT05-04\r\n] 2006.252.07:42:42.06#ibcon#*before write, iclass 31, count 2 2006.252.07:42:42.06#ibcon#enter sib2, iclass 31, count 2 2006.252.07:42:42.06#ibcon#flushed, iclass 31, count 2 2006.252.07:42:42.06#ibcon#about to write, iclass 31, count 2 2006.252.07:42:42.06#ibcon#wrote, iclass 31, count 2 2006.252.07:42:42.06#ibcon#about to read 3, iclass 31, count 2 2006.252.07:42:42.09#ibcon#read 3, iclass 31, count 2 2006.252.07:42:42.09#ibcon#about to read 4, iclass 31, count 2 2006.252.07:42:42.09#ibcon#read 4, iclass 31, count 2 2006.252.07:42:42.09#ibcon#about to read 5, iclass 31, count 2 2006.252.07:42:42.09#ibcon#read 5, iclass 31, count 2 2006.252.07:42:42.09#ibcon#about to read 6, iclass 31, count 2 2006.252.07:42:42.09#ibcon#read 6, iclass 31, count 2 2006.252.07:42:42.09#ibcon#end of sib2, iclass 31, count 2 2006.252.07:42:42.09#ibcon#*after write, iclass 31, count 2 2006.252.07:42:42.09#ibcon#*before return 0, iclass 31, count 2 2006.252.07:42:42.09#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.252.07:42:42.09#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.252.07:42:42.09#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.252.07:42:42.09#ibcon#ireg 7 cls_cnt 0 2006.252.07:42:42.09#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.252.07:42:42.21#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.252.07:42:42.21#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.252.07:42:42.21#ibcon#enter wrdev, iclass 31, count 0 2006.252.07:42:42.21#ibcon#first serial, iclass 31, count 0 2006.252.07:42:42.21#ibcon#enter sib2, iclass 31, count 0 2006.252.07:42:42.21#ibcon#flushed, iclass 31, count 0 2006.252.07:42:42.21#ibcon#about to write, iclass 31, count 0 2006.252.07:42:42.21#ibcon#wrote, iclass 31, count 0 2006.252.07:42:42.21#ibcon#about to read 3, iclass 31, count 0 2006.252.07:42:42.23#ibcon#read 3, iclass 31, count 0 2006.252.07:42:42.23#ibcon#about to read 4, iclass 31, count 0 2006.252.07:42:42.23#ibcon#read 4, iclass 31, count 0 2006.252.07:42:42.23#ibcon#about to read 5, iclass 31, count 0 2006.252.07:42:42.23#ibcon#read 5, iclass 31, count 0 2006.252.07:42:42.23#ibcon#about to read 6, iclass 31, count 0 2006.252.07:42:42.23#ibcon#read 6, iclass 31, count 0 2006.252.07:42:42.23#ibcon#end of sib2, iclass 31, count 0 2006.252.07:42:42.23#ibcon#*mode == 0, iclass 31, count 0 2006.252.07:42:42.23#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.252.07:42:42.23#ibcon#[27=USB\r\n] 2006.252.07:42:42.23#ibcon#*before write, iclass 31, count 0 2006.252.07:42:42.23#ibcon#enter sib2, iclass 31, count 0 2006.252.07:42:42.23#ibcon#flushed, iclass 31, count 0 2006.252.07:42:42.23#ibcon#about to write, iclass 31, count 0 2006.252.07:42:42.23#ibcon#wrote, iclass 31, count 0 2006.252.07:42:42.23#ibcon#about to read 3, iclass 31, count 0 2006.252.07:42:42.26#ibcon#read 3, iclass 31, count 0 2006.252.07:42:42.26#ibcon#about to read 4, iclass 31, count 0 2006.252.07:42:42.26#ibcon#read 4, iclass 31, count 0 2006.252.07:42:42.26#ibcon#about to read 5, iclass 31, count 0 2006.252.07:42:42.26#ibcon#read 5, iclass 31, count 0 2006.252.07:42:42.26#ibcon#about to read 6, iclass 31, count 0 2006.252.07:42:42.26#ibcon#read 6, iclass 31, count 0 2006.252.07:42:42.26#ibcon#end of sib2, iclass 31, count 0 2006.252.07:42:42.26#ibcon#*after write, iclass 31, count 0 2006.252.07:42:42.26#ibcon#*before return 0, iclass 31, count 0 2006.252.07:42:42.26#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.252.07:42:42.26#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.252.07:42:42.26#ibcon#about to clear, iclass 31 cls_cnt 0 2006.252.07:42:42.26#ibcon#cleared, iclass 31 cls_cnt 0 2006.252.07:42:42.26$vc4f8/vblo=6,752.99 2006.252.07:42:42.26#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.252.07:42:42.26#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.252.07:42:42.26#ibcon#ireg 17 cls_cnt 0 2006.252.07:42:42.26#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.252.07:42:42.26#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.252.07:42:42.26#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.252.07:42:42.26#ibcon#enter wrdev, iclass 33, count 0 2006.252.07:42:42.26#ibcon#first serial, iclass 33, count 0 2006.252.07:42:42.26#ibcon#enter sib2, iclass 33, count 0 2006.252.07:42:42.26#ibcon#flushed, iclass 33, count 0 2006.252.07:42:42.26#ibcon#about to write, iclass 33, count 0 2006.252.07:42:42.26#ibcon#wrote, iclass 33, count 0 2006.252.07:42:42.26#ibcon#about to read 3, iclass 33, count 0 2006.252.07:42:42.28#ibcon#read 3, iclass 33, count 0 2006.252.07:42:42.28#ibcon#about to read 4, iclass 33, count 0 2006.252.07:42:42.28#ibcon#read 4, iclass 33, count 0 2006.252.07:42:42.28#ibcon#about to read 5, iclass 33, count 0 2006.252.07:42:42.28#ibcon#read 5, iclass 33, count 0 2006.252.07:42:42.28#ibcon#about to read 6, iclass 33, count 0 2006.252.07:42:42.28#ibcon#read 6, iclass 33, count 0 2006.252.07:42:42.28#ibcon#end of sib2, iclass 33, count 0 2006.252.07:42:42.28#ibcon#*mode == 0, iclass 33, count 0 2006.252.07:42:42.28#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.252.07:42:42.28#ibcon#[28=FRQ=06,752.99\r\n] 2006.252.07:42:42.28#ibcon#*before write, iclass 33, count 0 2006.252.07:42:42.28#ibcon#enter sib2, iclass 33, count 0 2006.252.07:42:42.28#ibcon#flushed, iclass 33, count 0 2006.252.07:42:42.28#ibcon#about to write, iclass 33, count 0 2006.252.07:42:42.28#ibcon#wrote, iclass 33, count 0 2006.252.07:42:42.28#ibcon#about to read 3, iclass 33, count 0 2006.252.07:42:42.32#ibcon#read 3, iclass 33, count 0 2006.252.07:42:42.32#ibcon#about to read 4, iclass 33, count 0 2006.252.07:42:42.32#ibcon#read 4, iclass 33, count 0 2006.252.07:42:42.32#ibcon#about to read 5, iclass 33, count 0 2006.252.07:42:42.32#ibcon#read 5, iclass 33, count 0 2006.252.07:42:42.32#ibcon#about to read 6, iclass 33, count 0 2006.252.07:42:42.32#ibcon#read 6, iclass 33, count 0 2006.252.07:42:42.32#ibcon#end of sib2, iclass 33, count 0 2006.252.07:42:42.32#ibcon#*after write, iclass 33, count 0 2006.252.07:42:42.32#ibcon#*before return 0, iclass 33, count 0 2006.252.07:42:42.32#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.252.07:42:42.32#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.252.07:42:42.32#ibcon#about to clear, iclass 33 cls_cnt 0 2006.252.07:42:42.32#ibcon#cleared, iclass 33 cls_cnt 0 2006.252.07:42:42.32$vc4f8/vb=6,4 2006.252.07:42:42.32#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.252.07:42:42.32#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.252.07:42:42.32#ibcon#ireg 11 cls_cnt 2 2006.252.07:42:42.32#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.252.07:42:42.38#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.252.07:42:42.38#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.252.07:42:42.38#ibcon#enter wrdev, iclass 35, count 2 2006.252.07:42:42.38#ibcon#first serial, iclass 35, count 2 2006.252.07:42:42.38#ibcon#enter sib2, iclass 35, count 2 2006.252.07:42:42.38#ibcon#flushed, iclass 35, count 2 2006.252.07:42:42.38#ibcon#about to write, iclass 35, count 2 2006.252.07:42:42.38#ibcon#wrote, iclass 35, count 2 2006.252.07:42:42.38#ibcon#about to read 3, iclass 35, count 2 2006.252.07:42:42.40#ibcon#read 3, iclass 35, count 2 2006.252.07:42:42.40#ibcon#about to read 4, iclass 35, count 2 2006.252.07:42:42.40#ibcon#read 4, iclass 35, count 2 2006.252.07:42:42.40#ibcon#about to read 5, iclass 35, count 2 2006.252.07:42:42.40#ibcon#read 5, iclass 35, count 2 2006.252.07:42:42.40#ibcon#about to read 6, iclass 35, count 2 2006.252.07:42:42.40#ibcon#read 6, iclass 35, count 2 2006.252.07:42:42.40#ibcon#end of sib2, iclass 35, count 2 2006.252.07:42:42.40#ibcon#*mode == 0, iclass 35, count 2 2006.252.07:42:42.40#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.252.07:42:42.40#ibcon#[27=AT06-04\r\n] 2006.252.07:42:42.40#ibcon#*before write, iclass 35, count 2 2006.252.07:42:42.40#ibcon#enter sib2, iclass 35, count 2 2006.252.07:42:42.40#ibcon#flushed, iclass 35, count 2 2006.252.07:42:42.40#ibcon#about to write, iclass 35, count 2 2006.252.07:42:42.40#ibcon#wrote, iclass 35, count 2 2006.252.07:42:42.40#ibcon#about to read 3, iclass 35, count 2 2006.252.07:42:42.43#ibcon#read 3, iclass 35, count 2 2006.252.07:42:42.43#ibcon#about to read 4, iclass 35, count 2 2006.252.07:42:42.43#ibcon#read 4, iclass 35, count 2 2006.252.07:42:42.43#ibcon#about to read 5, iclass 35, count 2 2006.252.07:42:42.43#ibcon#read 5, iclass 35, count 2 2006.252.07:42:42.43#ibcon#about to read 6, iclass 35, count 2 2006.252.07:42:42.43#ibcon#read 6, iclass 35, count 2 2006.252.07:42:42.43#ibcon#end of sib2, iclass 35, count 2 2006.252.07:42:42.43#ibcon#*after write, iclass 35, count 2 2006.252.07:42:42.43#ibcon#*before return 0, iclass 35, count 2 2006.252.07:42:42.43#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.252.07:42:42.43#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.252.07:42:42.43#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.252.07:42:42.43#ibcon#ireg 7 cls_cnt 0 2006.252.07:42:42.43#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.252.07:42:42.55#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.252.07:42:42.55#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.252.07:42:42.55#ibcon#enter wrdev, iclass 35, count 0 2006.252.07:42:42.55#ibcon#first serial, iclass 35, count 0 2006.252.07:42:42.55#ibcon#enter sib2, iclass 35, count 0 2006.252.07:42:42.55#ibcon#flushed, iclass 35, count 0 2006.252.07:42:42.55#ibcon#about to write, iclass 35, count 0 2006.252.07:42:42.55#ibcon#wrote, iclass 35, count 0 2006.252.07:42:42.55#ibcon#about to read 3, iclass 35, count 0 2006.252.07:42:42.57#ibcon#read 3, iclass 35, count 0 2006.252.07:42:42.57#ibcon#about to read 4, iclass 35, count 0 2006.252.07:42:42.57#ibcon#read 4, iclass 35, count 0 2006.252.07:42:42.57#ibcon#about to read 5, iclass 35, count 0 2006.252.07:42:42.57#ibcon#read 5, iclass 35, count 0 2006.252.07:42:42.57#ibcon#about to read 6, iclass 35, count 0 2006.252.07:42:42.57#ibcon#read 6, iclass 35, count 0 2006.252.07:42:42.57#ibcon#end of sib2, iclass 35, count 0 2006.252.07:42:42.57#ibcon#*mode == 0, iclass 35, count 0 2006.252.07:42:42.57#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.252.07:42:42.57#ibcon#[27=USB\r\n] 2006.252.07:42:42.57#ibcon#*before write, iclass 35, count 0 2006.252.07:42:42.57#ibcon#enter sib2, iclass 35, count 0 2006.252.07:42:42.57#ibcon#flushed, iclass 35, count 0 2006.252.07:42:42.57#ibcon#about to write, iclass 35, count 0 2006.252.07:42:42.57#ibcon#wrote, iclass 35, count 0 2006.252.07:42:42.57#ibcon#about to read 3, iclass 35, count 0 2006.252.07:42:42.60#ibcon#read 3, iclass 35, count 0 2006.252.07:42:42.60#ibcon#about to read 4, iclass 35, count 0 2006.252.07:42:42.60#ibcon#read 4, iclass 35, count 0 2006.252.07:42:42.60#ibcon#about to read 5, iclass 35, count 0 2006.252.07:42:42.60#ibcon#read 5, iclass 35, count 0 2006.252.07:42:42.60#ibcon#about to read 6, iclass 35, count 0 2006.252.07:42:42.60#ibcon#read 6, iclass 35, count 0 2006.252.07:42:42.60#ibcon#end of sib2, iclass 35, count 0 2006.252.07:42:42.60#ibcon#*after write, iclass 35, count 0 2006.252.07:42:42.60#ibcon#*before return 0, iclass 35, count 0 2006.252.07:42:42.60#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.252.07:42:42.60#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.252.07:42:42.60#ibcon#about to clear, iclass 35 cls_cnt 0 2006.252.07:42:42.60#ibcon#cleared, iclass 35 cls_cnt 0 2006.252.07:42:42.60$vc4f8/vabw=wide 2006.252.07:42:42.60#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.252.07:42:42.60#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.252.07:42:42.60#ibcon#ireg 8 cls_cnt 0 2006.252.07:42:42.60#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.252.07:42:42.60#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.252.07:42:42.60#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.252.07:42:42.60#ibcon#enter wrdev, iclass 37, count 0 2006.252.07:42:42.60#ibcon#first serial, iclass 37, count 0 2006.252.07:42:42.60#ibcon#enter sib2, iclass 37, count 0 2006.252.07:42:42.60#ibcon#flushed, iclass 37, count 0 2006.252.07:42:42.60#ibcon#about to write, iclass 37, count 0 2006.252.07:42:42.60#ibcon#wrote, iclass 37, count 0 2006.252.07:42:42.60#ibcon#about to read 3, iclass 37, count 0 2006.252.07:42:42.62#ibcon#read 3, iclass 37, count 0 2006.252.07:42:42.62#ibcon#about to read 4, iclass 37, count 0 2006.252.07:42:42.62#ibcon#read 4, iclass 37, count 0 2006.252.07:42:42.62#ibcon#about to read 5, iclass 37, count 0 2006.252.07:42:42.62#ibcon#read 5, iclass 37, count 0 2006.252.07:42:42.62#ibcon#about to read 6, iclass 37, count 0 2006.252.07:42:42.62#ibcon#read 6, iclass 37, count 0 2006.252.07:42:42.62#ibcon#end of sib2, iclass 37, count 0 2006.252.07:42:42.62#ibcon#*mode == 0, iclass 37, count 0 2006.252.07:42:42.62#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.252.07:42:42.62#ibcon#[25=BW32\r\n] 2006.252.07:42:42.62#ibcon#*before write, iclass 37, count 0 2006.252.07:42:42.62#ibcon#enter sib2, iclass 37, count 0 2006.252.07:42:42.62#ibcon#flushed, iclass 37, count 0 2006.252.07:42:42.62#ibcon#about to write, iclass 37, count 0 2006.252.07:42:42.62#ibcon#wrote, iclass 37, count 0 2006.252.07:42:42.62#ibcon#about to read 3, iclass 37, count 0 2006.252.07:42:42.65#ibcon#read 3, iclass 37, count 0 2006.252.07:42:42.65#ibcon#about to read 4, iclass 37, count 0 2006.252.07:42:42.65#ibcon#read 4, iclass 37, count 0 2006.252.07:42:42.65#ibcon#about to read 5, iclass 37, count 0 2006.252.07:42:42.65#ibcon#read 5, iclass 37, count 0 2006.252.07:42:42.65#ibcon#about to read 6, iclass 37, count 0 2006.252.07:42:42.65#ibcon#read 6, iclass 37, count 0 2006.252.07:42:42.65#ibcon#end of sib2, iclass 37, count 0 2006.252.07:42:42.65#ibcon#*after write, iclass 37, count 0 2006.252.07:42:42.65#ibcon#*before return 0, iclass 37, count 0 2006.252.07:42:42.65#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.252.07:42:42.65#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.252.07:42:42.65#ibcon#about to clear, iclass 37 cls_cnt 0 2006.252.07:42:42.65#ibcon#cleared, iclass 37 cls_cnt 0 2006.252.07:42:42.65$vc4f8/vbbw=wide 2006.252.07:42:42.65#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.252.07:42:42.65#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.252.07:42:42.65#ibcon#ireg 8 cls_cnt 0 2006.252.07:42:42.65#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.252.07:42:42.72#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.252.07:42:42.72#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.252.07:42:42.72#ibcon#enter wrdev, iclass 39, count 0 2006.252.07:42:42.72#ibcon#first serial, iclass 39, count 0 2006.252.07:42:42.72#ibcon#enter sib2, iclass 39, count 0 2006.252.07:42:42.72#ibcon#flushed, iclass 39, count 0 2006.252.07:42:42.72#ibcon#about to write, iclass 39, count 0 2006.252.07:42:42.72#ibcon#wrote, iclass 39, count 0 2006.252.07:42:42.72#ibcon#about to read 3, iclass 39, count 0 2006.252.07:42:42.74#ibcon#read 3, iclass 39, count 0 2006.252.07:42:42.74#ibcon#about to read 4, iclass 39, count 0 2006.252.07:42:42.74#ibcon#read 4, iclass 39, count 0 2006.252.07:42:42.74#ibcon#about to read 5, iclass 39, count 0 2006.252.07:42:42.74#ibcon#read 5, iclass 39, count 0 2006.252.07:42:42.74#ibcon#about to read 6, iclass 39, count 0 2006.252.07:42:42.74#ibcon#read 6, iclass 39, count 0 2006.252.07:42:42.74#ibcon#end of sib2, iclass 39, count 0 2006.252.07:42:42.74#ibcon#*mode == 0, iclass 39, count 0 2006.252.07:42:42.74#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.252.07:42:42.74#ibcon#[27=BW32\r\n] 2006.252.07:42:42.74#ibcon#*before write, iclass 39, count 0 2006.252.07:42:42.74#ibcon#enter sib2, iclass 39, count 0 2006.252.07:42:42.74#ibcon#flushed, iclass 39, count 0 2006.252.07:42:42.74#ibcon#about to write, iclass 39, count 0 2006.252.07:42:42.74#ibcon#wrote, iclass 39, count 0 2006.252.07:42:42.74#ibcon#about to read 3, iclass 39, count 0 2006.252.07:42:42.77#ibcon#read 3, iclass 39, count 0 2006.252.07:42:42.77#ibcon#about to read 4, iclass 39, count 0 2006.252.07:42:42.77#ibcon#read 4, iclass 39, count 0 2006.252.07:42:42.77#ibcon#about to read 5, iclass 39, count 0 2006.252.07:42:42.77#ibcon#read 5, iclass 39, count 0 2006.252.07:42:42.77#ibcon#about to read 6, iclass 39, count 0 2006.252.07:42:42.77#ibcon#read 6, iclass 39, count 0 2006.252.07:42:42.77#ibcon#end of sib2, iclass 39, count 0 2006.252.07:42:42.77#ibcon#*after write, iclass 39, count 0 2006.252.07:42:42.77#ibcon#*before return 0, iclass 39, count 0 2006.252.07:42:42.77#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.252.07:42:42.77#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.252.07:42:42.77#ibcon#about to clear, iclass 39 cls_cnt 0 2006.252.07:42:42.77#ibcon#cleared, iclass 39 cls_cnt 0 2006.252.07:42:42.77$4f8m12a/ifd4f 2006.252.07:42:42.77$ifd4f/lo= 2006.252.07:42:42.77$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.252.07:42:42.77$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.252.07:42:42.77$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.252.07:42:42.77$ifd4f/patch= 2006.252.07:42:42.77$ifd4f/patch=lo1,a1,a2,a3,a4 2006.252.07:42:42.78$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.252.07:42:42.78$ifd4f/patch=lo3,a5,a6,a7,a8 2006.252.07:42:42.78$4f8m12a/"form=m,16.000,1:2 2006.252.07:42:42.78$4f8m12a/"tpicd 2006.252.07:42:42.78$4f8m12a/echo=off 2006.252.07:42:42.78$4f8m12a/xlog=off 2006.252.07:42:42.78:!2006.252.07:43:10 2006.252.07:42:53.14#trakl#Source acquired 2006.252.07:42:55.14#flagr#flagr/antenna,acquired 2006.252.07:43:10.01:preob 2006.252.07:43:11.14/onsource/TRACKING 2006.252.07:43:11.14:!2006.252.07:43:20 2006.252.07:43:20.00:data_valid=on 2006.252.07:43:20.00:midob 2006.252.07:43:20.14/onsource/TRACKING 2006.252.07:43:20.14/wx/27.41,1011.2,90 2006.252.07:43:20.36/cable/+6.4084E-03 2006.252.07:43:21.45/va/01,08,usb,yes,32,34 2006.252.07:43:21.45/va/02,07,usb,yes,32,34 2006.252.07:43:21.45/va/03,06,usb,yes,34,34 2006.252.07:43:21.45/va/04,07,usb,yes,33,35 2006.252.07:43:21.45/va/05,07,usb,yes,36,38 2006.252.07:43:21.45/va/06,07,usb,yes,31,31 2006.252.07:43:21.45/va/07,07,usb,yes,31,30 2006.252.07:43:21.45/va/08,07,usb,yes,33,33 2006.252.07:43:21.68/valo/01,532.99,yes,locked 2006.252.07:43:21.68/valo/02,572.99,yes,locked 2006.252.07:43:21.68/valo/03,672.99,yes,locked 2006.252.07:43:21.68/valo/04,832.99,yes,locked 2006.252.07:43:21.68/valo/05,652.99,yes,locked 2006.252.07:43:21.68/valo/06,772.99,yes,locked 2006.252.07:43:21.68/valo/07,832.99,yes,locked 2006.252.07:43:21.68/valo/08,852.99,yes,locked 2006.252.07:43:22.77/vb/01,04,usb,yes,30,29 2006.252.07:43:22.77/vb/02,05,usb,yes,28,29 2006.252.07:43:22.77/vb/03,04,usb,yes,28,32 2006.252.07:43:22.77/vb/04,04,usb,yes,29,29 2006.252.07:43:22.77/vb/05,04,usb,yes,27,31 2006.252.07:43:22.77/vb/06,04,usb,yes,28,31 2006.252.07:43:22.77/vb/07,04,usb,yes,31,30 2006.252.07:43:22.77/vb/08,04,usb,yes,28,31 2006.252.07:43:23.00/vblo/01,632.99,yes,locked 2006.252.07:43:23.00/vblo/02,640.99,yes,locked 2006.252.07:43:23.00/vblo/03,656.99,yes,locked 2006.252.07:43:23.00/vblo/04,712.99,yes,locked 2006.252.07:43:23.00/vblo/05,744.99,yes,locked 2006.252.07:43:23.00/vblo/06,752.99,yes,locked 2006.252.07:43:23.00/vblo/07,734.99,yes,locked 2006.252.07:43:23.00/vblo/08,744.99,yes,locked 2006.252.07:43:23.15/vabw/8 2006.252.07:43:23.30/vbbw/8 2006.252.07:43:23.39/xfe/off,on,14.0 2006.252.07:43:23.76/ifatt/23,28,28,28 2006.252.07:43:24.07/fmout-gps/S +4.79E-07 2006.252.07:43:24.15:!2006.252.07:44:20 2006.252.07:44:20.00:data_valid=off 2006.252.07:44:20.01:postob 2006.252.07:44:20.12/cable/+6.4105E-03 2006.252.07:44:20.13/wx/27.40,1011.2,90 2006.252.07:44:21.07/fmout-gps/S +4.78E-07 2006.252.07:44:21.08:scan_name=252-0745,k06252,60 2006.252.07:44:21.08:source=0718+793,072611.74,791131.0,2000.0,neutral 2006.252.07:44:21.13#flagr#flagr/antenna,new-source 2006.252.07:44:22.13:checkk5 2006.252.07:44:22.51/chk_autoobs//k5ts1/ autoobs is running! 2006.252.07:44:22.88/chk_autoobs//k5ts2/ autoobs is running! 2006.252.07:44:23.26/chk_autoobs//k5ts3/ autoobs is running! 2006.252.07:44:23.63/chk_autoobs//k5ts4/ autoobs is running! 2006.252.07:44:24.00/chk_obsdata//k5ts1/T2520743??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.07:44:24.38/chk_obsdata//k5ts2/T2520743??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.07:44:24.74/chk_obsdata//k5ts3/T2520743??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.07:44:25.11/chk_obsdata//k5ts4/T2520743??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.07:44:25.81/k5log//k5ts1_log_newline 2006.252.07:44:26.50/k5log//k5ts2_log_newline 2006.252.07:44:27.19/k5log//k5ts3_log_newline 2006.252.07:44:27.88/k5log//k5ts4_log_newline 2006.252.07:44:27.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.252.07:44:27.90:4f8m12a=1 2006.252.07:44:27.90$4f8m12a/echo=on 2006.252.07:44:27.90$4f8m12a/pcalon 2006.252.07:44:27.90$pcalon/"no phase cal control is implemented here 2006.252.07:44:27.90$4f8m12a/"tpicd=stop 2006.252.07:44:27.90$4f8m12a/vc4f8 2006.252.07:44:27.90$vc4f8/valo=1,532.99 2006.252.07:44:27.91#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.252.07:44:27.91#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.252.07:44:27.91#ibcon#ireg 17 cls_cnt 0 2006.252.07:44:27.91#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.252.07:44:27.91#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.252.07:44:27.91#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.252.07:44:27.91#ibcon#enter wrdev, iclass 14, count 0 2006.252.07:44:27.91#ibcon#first serial, iclass 14, count 0 2006.252.07:44:27.91#ibcon#enter sib2, iclass 14, count 0 2006.252.07:44:27.91#ibcon#flushed, iclass 14, count 0 2006.252.07:44:27.91#ibcon#about to write, iclass 14, count 0 2006.252.07:44:27.91#ibcon#wrote, iclass 14, count 0 2006.252.07:44:27.91#ibcon#about to read 3, iclass 14, count 0 2006.252.07:44:27.95#ibcon#read 3, iclass 14, count 0 2006.252.07:44:27.95#ibcon#about to read 4, iclass 14, count 0 2006.252.07:44:27.95#ibcon#read 4, iclass 14, count 0 2006.252.07:44:27.95#ibcon#about to read 5, iclass 14, count 0 2006.252.07:44:27.95#ibcon#read 5, iclass 14, count 0 2006.252.07:44:27.95#ibcon#about to read 6, iclass 14, count 0 2006.252.07:44:27.95#ibcon#read 6, iclass 14, count 0 2006.252.07:44:27.95#ibcon#end of sib2, iclass 14, count 0 2006.252.07:44:27.95#ibcon#*mode == 0, iclass 14, count 0 2006.252.07:44:27.95#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.252.07:44:27.95#ibcon#[26=FRQ=01,532.99\r\n] 2006.252.07:44:27.95#ibcon#*before write, iclass 14, count 0 2006.252.07:44:27.95#ibcon#enter sib2, iclass 14, count 0 2006.252.07:44:27.95#ibcon#flushed, iclass 14, count 0 2006.252.07:44:27.95#ibcon#about to write, iclass 14, count 0 2006.252.07:44:27.95#ibcon#wrote, iclass 14, count 0 2006.252.07:44:27.95#ibcon#about to read 3, iclass 14, count 0 2006.252.07:44:27.99#ibcon#read 3, iclass 14, count 0 2006.252.07:44:27.99#ibcon#about to read 4, iclass 14, count 0 2006.252.07:44:27.99#ibcon#read 4, iclass 14, count 0 2006.252.07:44:27.99#ibcon#about to read 5, iclass 14, count 0 2006.252.07:44:27.99#ibcon#read 5, iclass 14, count 0 2006.252.07:44:27.99#ibcon#about to read 6, iclass 14, count 0 2006.252.07:44:27.99#ibcon#read 6, iclass 14, count 0 2006.252.07:44:27.99#ibcon#end of sib2, iclass 14, count 0 2006.252.07:44:27.99#ibcon#*after write, iclass 14, count 0 2006.252.07:44:27.99#ibcon#*before return 0, iclass 14, count 0 2006.252.07:44:27.99#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.252.07:44:27.99#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.252.07:44:27.99#ibcon#about to clear, iclass 14 cls_cnt 0 2006.252.07:44:27.99#ibcon#cleared, iclass 14 cls_cnt 0 2006.252.07:44:27.99$vc4f8/va=1,8 2006.252.07:44:27.99#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.252.07:44:27.99#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.252.07:44:27.99#ibcon#ireg 11 cls_cnt 2 2006.252.07:44:27.99#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.252.07:44:27.99#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.252.07:44:27.99#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.252.07:44:27.99#ibcon#enter wrdev, iclass 16, count 2 2006.252.07:44:27.99#ibcon#first serial, iclass 16, count 2 2006.252.07:44:27.99#ibcon#enter sib2, iclass 16, count 2 2006.252.07:44:27.99#ibcon#flushed, iclass 16, count 2 2006.252.07:44:27.99#ibcon#about to write, iclass 16, count 2 2006.252.07:44:27.99#ibcon#wrote, iclass 16, count 2 2006.252.07:44:27.99#ibcon#about to read 3, iclass 16, count 2 2006.252.07:44:28.02#ibcon#read 3, iclass 16, count 2 2006.252.07:44:28.02#ibcon#about to read 4, iclass 16, count 2 2006.252.07:44:28.02#ibcon#read 4, iclass 16, count 2 2006.252.07:44:28.02#ibcon#about to read 5, iclass 16, count 2 2006.252.07:44:28.02#ibcon#read 5, iclass 16, count 2 2006.252.07:44:28.02#ibcon#about to read 6, iclass 16, count 2 2006.252.07:44:28.02#ibcon#read 6, iclass 16, count 2 2006.252.07:44:28.02#ibcon#end of sib2, iclass 16, count 2 2006.252.07:44:28.02#ibcon#*mode == 0, iclass 16, count 2 2006.252.07:44:28.02#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.252.07:44:28.02#ibcon#[25=AT01-08\r\n] 2006.252.07:44:28.02#ibcon#*before write, iclass 16, count 2 2006.252.07:44:28.02#ibcon#enter sib2, iclass 16, count 2 2006.252.07:44:28.02#ibcon#flushed, iclass 16, count 2 2006.252.07:44:28.02#ibcon#about to write, iclass 16, count 2 2006.252.07:44:28.02#ibcon#wrote, iclass 16, count 2 2006.252.07:44:28.02#ibcon#about to read 3, iclass 16, count 2 2006.252.07:44:28.05#ibcon#read 3, iclass 16, count 2 2006.252.07:44:28.05#ibcon#about to read 4, iclass 16, count 2 2006.252.07:44:28.05#ibcon#read 4, iclass 16, count 2 2006.252.07:44:28.05#ibcon#about to read 5, iclass 16, count 2 2006.252.07:44:28.05#ibcon#read 5, iclass 16, count 2 2006.252.07:44:28.05#ibcon#about to read 6, iclass 16, count 2 2006.252.07:44:28.05#ibcon#read 6, iclass 16, count 2 2006.252.07:44:28.05#ibcon#end of sib2, iclass 16, count 2 2006.252.07:44:28.05#ibcon#*after write, iclass 16, count 2 2006.252.07:44:28.05#ibcon#*before return 0, iclass 16, count 2 2006.252.07:44:28.05#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.252.07:44:28.05#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.252.07:44:28.05#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.252.07:44:28.05#ibcon#ireg 7 cls_cnt 0 2006.252.07:44:28.05#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.252.07:44:28.16#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.252.07:44:28.16#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.252.07:44:28.16#ibcon#enter wrdev, iclass 16, count 0 2006.252.07:44:28.16#ibcon#first serial, iclass 16, count 0 2006.252.07:44:28.16#ibcon#enter sib2, iclass 16, count 0 2006.252.07:44:28.16#ibcon#flushed, iclass 16, count 0 2006.252.07:44:28.16#ibcon#about to write, iclass 16, count 0 2006.252.07:44:28.16#ibcon#wrote, iclass 16, count 0 2006.252.07:44:28.16#ibcon#about to read 3, iclass 16, count 0 2006.252.07:44:28.18#ibcon#read 3, iclass 16, count 0 2006.252.07:44:28.18#ibcon#about to read 4, iclass 16, count 0 2006.252.07:44:28.18#ibcon#read 4, iclass 16, count 0 2006.252.07:44:28.18#ibcon#about to read 5, iclass 16, count 0 2006.252.07:44:28.18#ibcon#read 5, iclass 16, count 0 2006.252.07:44:28.18#ibcon#about to read 6, iclass 16, count 0 2006.252.07:44:28.18#ibcon#read 6, iclass 16, count 0 2006.252.07:44:28.18#ibcon#end of sib2, iclass 16, count 0 2006.252.07:44:28.18#ibcon#*mode == 0, iclass 16, count 0 2006.252.07:44:28.18#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.252.07:44:28.18#ibcon#[25=USB\r\n] 2006.252.07:44:28.18#ibcon#*before write, iclass 16, count 0 2006.252.07:44:28.18#ibcon#enter sib2, iclass 16, count 0 2006.252.07:44:28.18#ibcon#flushed, iclass 16, count 0 2006.252.07:44:28.18#ibcon#about to write, iclass 16, count 0 2006.252.07:44:28.18#ibcon#wrote, iclass 16, count 0 2006.252.07:44:28.18#ibcon#about to read 3, iclass 16, count 0 2006.252.07:44:28.21#ibcon#read 3, iclass 16, count 0 2006.252.07:44:28.21#ibcon#about to read 4, iclass 16, count 0 2006.252.07:44:28.21#ibcon#read 4, iclass 16, count 0 2006.252.07:44:28.21#ibcon#about to read 5, iclass 16, count 0 2006.252.07:44:28.21#ibcon#read 5, iclass 16, count 0 2006.252.07:44:28.21#ibcon#about to read 6, iclass 16, count 0 2006.252.07:44:28.21#ibcon#read 6, iclass 16, count 0 2006.252.07:44:28.21#ibcon#end of sib2, iclass 16, count 0 2006.252.07:44:28.21#ibcon#*after write, iclass 16, count 0 2006.252.07:44:28.21#ibcon#*before return 0, iclass 16, count 0 2006.252.07:44:28.21#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.252.07:44:28.21#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.252.07:44:28.21#ibcon#about to clear, iclass 16 cls_cnt 0 2006.252.07:44:28.21#ibcon#cleared, iclass 16 cls_cnt 0 2006.252.07:44:28.21$vc4f8/valo=2,572.99 2006.252.07:44:28.21#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.252.07:44:28.21#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.252.07:44:28.21#ibcon#ireg 17 cls_cnt 0 2006.252.07:44:28.21#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.252.07:44:28.21#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.252.07:44:28.21#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.252.07:44:28.21#ibcon#enter wrdev, iclass 18, count 0 2006.252.07:44:28.21#ibcon#first serial, iclass 18, count 0 2006.252.07:44:28.21#ibcon#enter sib2, iclass 18, count 0 2006.252.07:44:28.21#ibcon#flushed, iclass 18, count 0 2006.252.07:44:28.21#ibcon#about to write, iclass 18, count 0 2006.252.07:44:28.21#ibcon#wrote, iclass 18, count 0 2006.252.07:44:28.21#ibcon#about to read 3, iclass 18, count 0 2006.252.07:44:28.23#ibcon#read 3, iclass 18, count 0 2006.252.07:44:28.23#ibcon#about to read 4, iclass 18, count 0 2006.252.07:44:28.23#ibcon#read 4, iclass 18, count 0 2006.252.07:44:28.23#ibcon#about to read 5, iclass 18, count 0 2006.252.07:44:28.23#ibcon#read 5, iclass 18, count 0 2006.252.07:44:28.23#ibcon#about to read 6, iclass 18, count 0 2006.252.07:44:28.23#ibcon#read 6, iclass 18, count 0 2006.252.07:44:28.23#ibcon#end of sib2, iclass 18, count 0 2006.252.07:44:28.23#ibcon#*mode == 0, iclass 18, count 0 2006.252.07:44:28.23#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.252.07:44:28.23#ibcon#[26=FRQ=02,572.99\r\n] 2006.252.07:44:28.23#ibcon#*before write, iclass 18, count 0 2006.252.07:44:28.23#ibcon#enter sib2, iclass 18, count 0 2006.252.07:44:28.23#ibcon#flushed, iclass 18, count 0 2006.252.07:44:28.23#ibcon#about to write, iclass 18, count 0 2006.252.07:44:28.23#ibcon#wrote, iclass 18, count 0 2006.252.07:44:28.23#ibcon#about to read 3, iclass 18, count 0 2006.252.07:44:28.27#ibcon#read 3, iclass 18, count 0 2006.252.07:44:28.27#ibcon#about to read 4, iclass 18, count 0 2006.252.07:44:28.27#ibcon#read 4, iclass 18, count 0 2006.252.07:44:28.27#ibcon#about to read 5, iclass 18, count 0 2006.252.07:44:28.27#ibcon#read 5, iclass 18, count 0 2006.252.07:44:28.27#ibcon#about to read 6, iclass 18, count 0 2006.252.07:44:28.27#ibcon#read 6, iclass 18, count 0 2006.252.07:44:28.27#ibcon#end of sib2, iclass 18, count 0 2006.252.07:44:28.27#ibcon#*after write, iclass 18, count 0 2006.252.07:44:28.27#ibcon#*before return 0, iclass 18, count 0 2006.252.07:44:28.27#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.252.07:44:28.27#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.252.07:44:28.27#ibcon#about to clear, iclass 18 cls_cnt 0 2006.252.07:44:28.27#ibcon#cleared, iclass 18 cls_cnt 0 2006.252.07:44:28.27$vc4f8/va=2,7 2006.252.07:44:28.27#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.252.07:44:28.27#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.252.07:44:28.27#ibcon#ireg 11 cls_cnt 2 2006.252.07:44:28.27#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.252.07:44:28.34#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.252.07:44:28.34#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.252.07:44:28.34#ibcon#enter wrdev, iclass 20, count 2 2006.252.07:44:28.34#ibcon#first serial, iclass 20, count 2 2006.252.07:44:28.34#ibcon#enter sib2, iclass 20, count 2 2006.252.07:44:28.34#ibcon#flushed, iclass 20, count 2 2006.252.07:44:28.34#ibcon#about to write, iclass 20, count 2 2006.252.07:44:28.34#ibcon#wrote, iclass 20, count 2 2006.252.07:44:28.34#ibcon#about to read 3, iclass 20, count 2 2006.252.07:44:28.35#ibcon#read 3, iclass 20, count 2 2006.252.07:44:28.35#ibcon#about to read 4, iclass 20, count 2 2006.252.07:44:28.35#ibcon#read 4, iclass 20, count 2 2006.252.07:44:28.35#ibcon#about to read 5, iclass 20, count 2 2006.252.07:44:28.35#ibcon#read 5, iclass 20, count 2 2006.252.07:44:28.35#ibcon#about to read 6, iclass 20, count 2 2006.252.07:44:28.35#ibcon#read 6, iclass 20, count 2 2006.252.07:44:28.35#ibcon#end of sib2, iclass 20, count 2 2006.252.07:44:28.35#ibcon#*mode == 0, iclass 20, count 2 2006.252.07:44:28.35#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.252.07:44:28.35#ibcon#[25=AT02-07\r\n] 2006.252.07:44:28.35#ibcon#*before write, iclass 20, count 2 2006.252.07:44:28.35#ibcon#enter sib2, iclass 20, count 2 2006.252.07:44:28.35#ibcon#flushed, iclass 20, count 2 2006.252.07:44:28.35#ibcon#about to write, iclass 20, count 2 2006.252.07:44:28.35#ibcon#wrote, iclass 20, count 2 2006.252.07:44:28.35#ibcon#about to read 3, iclass 20, count 2 2006.252.07:44:28.38#ibcon#read 3, iclass 20, count 2 2006.252.07:44:28.38#ibcon#about to read 4, iclass 20, count 2 2006.252.07:44:28.38#ibcon#read 4, iclass 20, count 2 2006.252.07:44:28.38#ibcon#about to read 5, iclass 20, count 2 2006.252.07:44:28.38#ibcon#read 5, iclass 20, count 2 2006.252.07:44:28.38#ibcon#about to read 6, iclass 20, count 2 2006.252.07:44:28.38#ibcon#read 6, iclass 20, count 2 2006.252.07:44:28.38#ibcon#end of sib2, iclass 20, count 2 2006.252.07:44:28.38#ibcon#*after write, iclass 20, count 2 2006.252.07:44:28.38#ibcon#*before return 0, iclass 20, count 2 2006.252.07:44:28.38#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.252.07:44:28.38#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.252.07:44:28.38#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.252.07:44:28.38#ibcon#ireg 7 cls_cnt 0 2006.252.07:44:28.38#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.252.07:44:28.50#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.252.07:44:28.50#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.252.07:44:28.50#ibcon#enter wrdev, iclass 20, count 0 2006.252.07:44:28.50#ibcon#first serial, iclass 20, count 0 2006.252.07:44:28.50#ibcon#enter sib2, iclass 20, count 0 2006.252.07:44:28.50#ibcon#flushed, iclass 20, count 0 2006.252.07:44:28.50#ibcon#about to write, iclass 20, count 0 2006.252.07:44:28.50#ibcon#wrote, iclass 20, count 0 2006.252.07:44:28.50#ibcon#about to read 3, iclass 20, count 0 2006.252.07:44:28.52#ibcon#read 3, iclass 20, count 0 2006.252.07:44:28.52#ibcon#about to read 4, iclass 20, count 0 2006.252.07:44:28.52#ibcon#read 4, iclass 20, count 0 2006.252.07:44:28.52#ibcon#about to read 5, iclass 20, count 0 2006.252.07:44:28.52#ibcon#read 5, iclass 20, count 0 2006.252.07:44:28.52#ibcon#about to read 6, iclass 20, count 0 2006.252.07:44:28.52#ibcon#read 6, iclass 20, count 0 2006.252.07:44:28.52#ibcon#end of sib2, iclass 20, count 0 2006.252.07:44:28.52#ibcon#*mode == 0, iclass 20, count 0 2006.252.07:44:28.52#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.252.07:44:28.52#ibcon#[25=USB\r\n] 2006.252.07:44:28.52#ibcon#*before write, iclass 20, count 0 2006.252.07:44:28.52#ibcon#enter sib2, iclass 20, count 0 2006.252.07:44:28.52#ibcon#flushed, iclass 20, count 0 2006.252.07:44:28.52#ibcon#about to write, iclass 20, count 0 2006.252.07:44:28.52#ibcon#wrote, iclass 20, count 0 2006.252.07:44:28.52#ibcon#about to read 3, iclass 20, count 0 2006.252.07:44:28.55#ibcon#read 3, iclass 20, count 0 2006.252.07:44:28.55#ibcon#about to read 4, iclass 20, count 0 2006.252.07:44:28.55#ibcon#read 4, iclass 20, count 0 2006.252.07:44:28.55#ibcon#about to read 5, iclass 20, count 0 2006.252.07:44:28.55#ibcon#read 5, iclass 20, count 0 2006.252.07:44:28.55#ibcon#about to read 6, iclass 20, count 0 2006.252.07:44:28.55#ibcon#read 6, iclass 20, count 0 2006.252.07:44:28.55#ibcon#end of sib2, iclass 20, count 0 2006.252.07:44:28.55#ibcon#*after write, iclass 20, count 0 2006.252.07:44:28.55#ibcon#*before return 0, iclass 20, count 0 2006.252.07:44:28.55#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.252.07:44:28.55#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.252.07:44:28.55#ibcon#about to clear, iclass 20 cls_cnt 0 2006.252.07:44:28.55#ibcon#cleared, iclass 20 cls_cnt 0 2006.252.07:44:28.55$vc4f8/valo=3,672.99 2006.252.07:44:28.55#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.252.07:44:28.55#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.252.07:44:28.55#ibcon#ireg 17 cls_cnt 0 2006.252.07:44:28.55#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.252.07:44:28.55#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.252.07:44:28.55#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.252.07:44:28.55#ibcon#enter wrdev, iclass 22, count 0 2006.252.07:44:28.55#ibcon#first serial, iclass 22, count 0 2006.252.07:44:28.55#ibcon#enter sib2, iclass 22, count 0 2006.252.07:44:28.55#ibcon#flushed, iclass 22, count 0 2006.252.07:44:28.55#ibcon#about to write, iclass 22, count 0 2006.252.07:44:28.55#ibcon#wrote, iclass 22, count 0 2006.252.07:44:28.55#ibcon#about to read 3, iclass 22, count 0 2006.252.07:44:28.58#ibcon#read 3, iclass 22, count 0 2006.252.07:44:28.58#ibcon#about to read 4, iclass 22, count 0 2006.252.07:44:28.58#ibcon#read 4, iclass 22, count 0 2006.252.07:44:28.58#ibcon#about to read 5, iclass 22, count 0 2006.252.07:44:28.58#ibcon#read 5, iclass 22, count 0 2006.252.07:44:28.58#ibcon#about to read 6, iclass 22, count 0 2006.252.07:44:28.58#ibcon#read 6, iclass 22, count 0 2006.252.07:44:28.58#ibcon#end of sib2, iclass 22, count 0 2006.252.07:44:28.58#ibcon#*mode == 0, iclass 22, count 0 2006.252.07:44:28.58#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.252.07:44:28.58#ibcon#[26=FRQ=03,672.99\r\n] 2006.252.07:44:28.58#ibcon#*before write, iclass 22, count 0 2006.252.07:44:28.58#ibcon#enter sib2, iclass 22, count 0 2006.252.07:44:28.58#ibcon#flushed, iclass 22, count 0 2006.252.07:44:28.58#ibcon#about to write, iclass 22, count 0 2006.252.07:44:28.58#ibcon#wrote, iclass 22, count 0 2006.252.07:44:28.58#ibcon#about to read 3, iclass 22, count 0 2006.252.07:44:28.62#ibcon#read 3, iclass 22, count 0 2006.252.07:44:28.62#ibcon#about to read 4, iclass 22, count 0 2006.252.07:44:28.62#ibcon#read 4, iclass 22, count 0 2006.252.07:44:28.62#ibcon#about to read 5, iclass 22, count 0 2006.252.07:44:28.62#ibcon#read 5, iclass 22, count 0 2006.252.07:44:28.62#ibcon#about to read 6, iclass 22, count 0 2006.252.07:44:28.62#ibcon#read 6, iclass 22, count 0 2006.252.07:44:28.62#ibcon#end of sib2, iclass 22, count 0 2006.252.07:44:28.62#ibcon#*after write, iclass 22, count 0 2006.252.07:44:28.62#ibcon#*before return 0, iclass 22, count 0 2006.252.07:44:28.62#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.252.07:44:28.62#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.252.07:44:28.62#ibcon#about to clear, iclass 22 cls_cnt 0 2006.252.07:44:28.62#ibcon#cleared, iclass 22 cls_cnt 0 2006.252.07:44:28.62$vc4f8/va=3,6 2006.252.07:44:28.62#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.252.07:44:28.62#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.252.07:44:28.62#ibcon#ireg 11 cls_cnt 2 2006.252.07:44:28.62#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.252.07:44:28.67#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.252.07:44:28.68#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.252.07:44:28.68#ibcon#enter wrdev, iclass 24, count 2 2006.252.07:44:28.68#ibcon#first serial, iclass 24, count 2 2006.252.07:44:28.68#ibcon#enter sib2, iclass 24, count 2 2006.252.07:44:28.68#ibcon#flushed, iclass 24, count 2 2006.252.07:44:28.68#ibcon#about to write, iclass 24, count 2 2006.252.07:44:28.68#ibcon#wrote, iclass 24, count 2 2006.252.07:44:28.68#ibcon#about to read 3, iclass 24, count 2 2006.252.07:44:28.69#ibcon#read 3, iclass 24, count 2 2006.252.07:44:28.69#ibcon#about to read 4, iclass 24, count 2 2006.252.07:44:28.69#ibcon#read 4, iclass 24, count 2 2006.252.07:44:28.69#ibcon#about to read 5, iclass 24, count 2 2006.252.07:44:28.69#ibcon#read 5, iclass 24, count 2 2006.252.07:44:28.69#ibcon#about to read 6, iclass 24, count 2 2006.252.07:44:28.69#ibcon#read 6, iclass 24, count 2 2006.252.07:44:28.69#ibcon#end of sib2, iclass 24, count 2 2006.252.07:44:28.69#ibcon#*mode == 0, iclass 24, count 2 2006.252.07:44:28.69#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.252.07:44:28.69#ibcon#[25=AT03-06\r\n] 2006.252.07:44:28.69#ibcon#*before write, iclass 24, count 2 2006.252.07:44:28.69#ibcon#enter sib2, iclass 24, count 2 2006.252.07:44:28.69#ibcon#flushed, iclass 24, count 2 2006.252.07:44:28.69#ibcon#about to write, iclass 24, count 2 2006.252.07:44:28.69#ibcon#wrote, iclass 24, count 2 2006.252.07:44:28.69#ibcon#about to read 3, iclass 24, count 2 2006.252.07:44:28.72#ibcon#read 3, iclass 24, count 2 2006.252.07:44:28.72#ibcon#about to read 4, iclass 24, count 2 2006.252.07:44:28.72#ibcon#read 4, iclass 24, count 2 2006.252.07:44:28.72#ibcon#about to read 5, iclass 24, count 2 2006.252.07:44:28.72#ibcon#read 5, iclass 24, count 2 2006.252.07:44:28.72#ibcon#about to read 6, iclass 24, count 2 2006.252.07:44:28.72#ibcon#read 6, iclass 24, count 2 2006.252.07:44:28.72#ibcon#end of sib2, iclass 24, count 2 2006.252.07:44:28.72#ibcon#*after write, iclass 24, count 2 2006.252.07:44:28.72#ibcon#*before return 0, iclass 24, count 2 2006.252.07:44:28.72#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.252.07:44:28.72#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.252.07:44:28.72#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.252.07:44:28.72#ibcon#ireg 7 cls_cnt 0 2006.252.07:44:28.72#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.252.07:44:28.84#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.252.07:44:28.84#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.252.07:44:28.84#ibcon#enter wrdev, iclass 24, count 0 2006.252.07:44:28.84#ibcon#first serial, iclass 24, count 0 2006.252.07:44:28.84#ibcon#enter sib2, iclass 24, count 0 2006.252.07:44:28.84#ibcon#flushed, iclass 24, count 0 2006.252.07:44:28.84#ibcon#about to write, iclass 24, count 0 2006.252.07:44:28.84#ibcon#wrote, iclass 24, count 0 2006.252.07:44:28.84#ibcon#about to read 3, iclass 24, count 0 2006.252.07:44:28.86#ibcon#read 3, iclass 24, count 0 2006.252.07:44:28.86#ibcon#about to read 4, iclass 24, count 0 2006.252.07:44:28.86#ibcon#read 4, iclass 24, count 0 2006.252.07:44:28.86#ibcon#about to read 5, iclass 24, count 0 2006.252.07:44:28.86#ibcon#read 5, iclass 24, count 0 2006.252.07:44:28.86#ibcon#about to read 6, iclass 24, count 0 2006.252.07:44:28.86#ibcon#read 6, iclass 24, count 0 2006.252.07:44:28.86#ibcon#end of sib2, iclass 24, count 0 2006.252.07:44:28.86#ibcon#*mode == 0, iclass 24, count 0 2006.252.07:44:28.86#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.252.07:44:28.86#ibcon#[25=USB\r\n] 2006.252.07:44:28.86#ibcon#*before write, iclass 24, count 0 2006.252.07:44:28.86#ibcon#enter sib2, iclass 24, count 0 2006.252.07:44:28.86#ibcon#flushed, iclass 24, count 0 2006.252.07:44:28.86#ibcon#about to write, iclass 24, count 0 2006.252.07:44:28.86#ibcon#wrote, iclass 24, count 0 2006.252.07:44:28.86#ibcon#about to read 3, iclass 24, count 0 2006.252.07:44:28.89#ibcon#read 3, iclass 24, count 0 2006.252.07:44:28.89#ibcon#about to read 4, iclass 24, count 0 2006.252.07:44:28.89#ibcon#read 4, iclass 24, count 0 2006.252.07:44:28.89#ibcon#about to read 5, iclass 24, count 0 2006.252.07:44:28.89#ibcon#read 5, iclass 24, count 0 2006.252.07:44:28.89#ibcon#about to read 6, iclass 24, count 0 2006.252.07:44:28.89#ibcon#read 6, iclass 24, count 0 2006.252.07:44:28.89#ibcon#end of sib2, iclass 24, count 0 2006.252.07:44:28.89#ibcon#*after write, iclass 24, count 0 2006.252.07:44:28.89#ibcon#*before return 0, iclass 24, count 0 2006.252.07:44:28.89#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.252.07:44:28.89#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.252.07:44:28.89#ibcon#about to clear, iclass 24 cls_cnt 0 2006.252.07:44:28.89#ibcon#cleared, iclass 24 cls_cnt 0 2006.252.07:44:28.89$vc4f8/valo=4,832.99 2006.252.07:44:28.89#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.252.07:44:28.89#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.252.07:44:28.89#ibcon#ireg 17 cls_cnt 0 2006.252.07:44:28.89#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.252.07:44:28.89#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.252.07:44:28.89#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.252.07:44:28.89#ibcon#enter wrdev, iclass 26, count 0 2006.252.07:44:28.89#ibcon#first serial, iclass 26, count 0 2006.252.07:44:28.89#ibcon#enter sib2, iclass 26, count 0 2006.252.07:44:28.89#ibcon#flushed, iclass 26, count 0 2006.252.07:44:28.89#ibcon#about to write, iclass 26, count 0 2006.252.07:44:28.89#ibcon#wrote, iclass 26, count 0 2006.252.07:44:28.89#ibcon#about to read 3, iclass 26, count 0 2006.252.07:44:28.92#ibcon#read 3, iclass 26, count 0 2006.252.07:44:28.92#ibcon#about to read 4, iclass 26, count 0 2006.252.07:44:28.92#ibcon#read 4, iclass 26, count 0 2006.252.07:44:28.92#ibcon#about to read 5, iclass 26, count 0 2006.252.07:44:28.92#ibcon#read 5, iclass 26, count 0 2006.252.07:44:28.92#ibcon#about to read 6, iclass 26, count 0 2006.252.07:44:28.92#ibcon#read 6, iclass 26, count 0 2006.252.07:44:28.92#ibcon#end of sib2, iclass 26, count 0 2006.252.07:44:28.92#ibcon#*mode == 0, iclass 26, count 0 2006.252.07:44:28.92#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.252.07:44:28.92#ibcon#[26=FRQ=04,832.99\r\n] 2006.252.07:44:28.92#ibcon#*before write, iclass 26, count 0 2006.252.07:44:28.92#ibcon#enter sib2, iclass 26, count 0 2006.252.07:44:28.92#ibcon#flushed, iclass 26, count 0 2006.252.07:44:28.92#ibcon#about to write, iclass 26, count 0 2006.252.07:44:28.92#ibcon#wrote, iclass 26, count 0 2006.252.07:44:28.92#ibcon#about to read 3, iclass 26, count 0 2006.252.07:44:28.96#ibcon#read 3, iclass 26, count 0 2006.252.07:44:28.96#ibcon#about to read 4, iclass 26, count 0 2006.252.07:44:28.96#ibcon#read 4, iclass 26, count 0 2006.252.07:44:28.96#ibcon#about to read 5, iclass 26, count 0 2006.252.07:44:28.96#ibcon#read 5, iclass 26, count 0 2006.252.07:44:28.96#ibcon#about to read 6, iclass 26, count 0 2006.252.07:44:28.96#ibcon#read 6, iclass 26, count 0 2006.252.07:44:28.96#ibcon#end of sib2, iclass 26, count 0 2006.252.07:44:28.96#ibcon#*after write, iclass 26, count 0 2006.252.07:44:28.96#ibcon#*before return 0, iclass 26, count 0 2006.252.07:44:28.96#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.252.07:44:28.96#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.252.07:44:28.96#ibcon#about to clear, iclass 26 cls_cnt 0 2006.252.07:44:28.96#ibcon#cleared, iclass 26 cls_cnt 0 2006.252.07:44:28.96$vc4f8/va=4,7 2006.252.07:44:28.96#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.252.07:44:28.96#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.252.07:44:28.96#ibcon#ireg 11 cls_cnt 2 2006.252.07:44:28.96#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.252.07:44:29.01#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.252.07:44:29.01#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.252.07:44:29.01#ibcon#enter wrdev, iclass 28, count 2 2006.252.07:44:29.01#ibcon#first serial, iclass 28, count 2 2006.252.07:44:29.01#ibcon#enter sib2, iclass 28, count 2 2006.252.07:44:29.01#ibcon#flushed, iclass 28, count 2 2006.252.07:44:29.01#ibcon#about to write, iclass 28, count 2 2006.252.07:44:29.01#ibcon#wrote, iclass 28, count 2 2006.252.07:44:29.01#ibcon#about to read 3, iclass 28, count 2 2006.252.07:44:29.03#ibcon#read 3, iclass 28, count 2 2006.252.07:44:29.03#ibcon#about to read 4, iclass 28, count 2 2006.252.07:44:29.03#ibcon#read 4, iclass 28, count 2 2006.252.07:44:29.03#ibcon#about to read 5, iclass 28, count 2 2006.252.07:44:29.03#ibcon#read 5, iclass 28, count 2 2006.252.07:44:29.03#ibcon#about to read 6, iclass 28, count 2 2006.252.07:44:29.03#ibcon#read 6, iclass 28, count 2 2006.252.07:44:29.03#ibcon#end of sib2, iclass 28, count 2 2006.252.07:44:29.03#ibcon#*mode == 0, iclass 28, count 2 2006.252.07:44:29.03#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.252.07:44:29.03#ibcon#[25=AT04-07\r\n] 2006.252.07:44:29.03#ibcon#*before write, iclass 28, count 2 2006.252.07:44:29.03#ibcon#enter sib2, iclass 28, count 2 2006.252.07:44:29.03#ibcon#flushed, iclass 28, count 2 2006.252.07:44:29.03#ibcon#about to write, iclass 28, count 2 2006.252.07:44:29.03#ibcon#wrote, iclass 28, count 2 2006.252.07:44:29.03#ibcon#about to read 3, iclass 28, count 2 2006.252.07:44:29.06#ibcon#read 3, iclass 28, count 2 2006.252.07:44:29.06#ibcon#about to read 4, iclass 28, count 2 2006.252.07:44:29.06#ibcon#read 4, iclass 28, count 2 2006.252.07:44:29.06#ibcon#about to read 5, iclass 28, count 2 2006.252.07:44:29.06#ibcon#read 5, iclass 28, count 2 2006.252.07:44:29.06#ibcon#about to read 6, iclass 28, count 2 2006.252.07:44:29.06#ibcon#read 6, iclass 28, count 2 2006.252.07:44:29.06#ibcon#end of sib2, iclass 28, count 2 2006.252.07:44:29.06#ibcon#*after write, iclass 28, count 2 2006.252.07:44:29.06#ibcon#*before return 0, iclass 28, count 2 2006.252.07:44:29.06#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.252.07:44:29.06#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.252.07:44:29.06#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.252.07:44:29.06#ibcon#ireg 7 cls_cnt 0 2006.252.07:44:29.06#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.252.07:44:29.18#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.252.07:44:29.18#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.252.07:44:29.18#ibcon#enter wrdev, iclass 28, count 0 2006.252.07:44:29.18#ibcon#first serial, iclass 28, count 0 2006.252.07:44:29.18#ibcon#enter sib2, iclass 28, count 0 2006.252.07:44:29.18#ibcon#flushed, iclass 28, count 0 2006.252.07:44:29.18#ibcon#about to write, iclass 28, count 0 2006.252.07:44:29.18#ibcon#wrote, iclass 28, count 0 2006.252.07:44:29.18#ibcon#about to read 3, iclass 28, count 0 2006.252.07:44:29.20#ibcon#read 3, iclass 28, count 0 2006.252.07:44:29.20#ibcon#about to read 4, iclass 28, count 0 2006.252.07:44:29.20#ibcon#read 4, iclass 28, count 0 2006.252.07:44:29.20#ibcon#about to read 5, iclass 28, count 0 2006.252.07:44:29.20#ibcon#read 5, iclass 28, count 0 2006.252.07:44:29.20#ibcon#about to read 6, iclass 28, count 0 2006.252.07:44:29.20#ibcon#read 6, iclass 28, count 0 2006.252.07:44:29.20#ibcon#end of sib2, iclass 28, count 0 2006.252.07:44:29.20#ibcon#*mode == 0, iclass 28, count 0 2006.252.07:44:29.20#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.252.07:44:29.20#ibcon#[25=USB\r\n] 2006.252.07:44:29.20#ibcon#*before write, iclass 28, count 0 2006.252.07:44:29.20#ibcon#enter sib2, iclass 28, count 0 2006.252.07:44:29.20#ibcon#flushed, iclass 28, count 0 2006.252.07:44:29.20#ibcon#about to write, iclass 28, count 0 2006.252.07:44:29.20#ibcon#wrote, iclass 28, count 0 2006.252.07:44:29.20#ibcon#about to read 3, iclass 28, count 0 2006.252.07:44:29.23#ibcon#read 3, iclass 28, count 0 2006.252.07:44:29.23#ibcon#about to read 4, iclass 28, count 0 2006.252.07:44:29.23#ibcon#read 4, iclass 28, count 0 2006.252.07:44:29.23#ibcon#about to read 5, iclass 28, count 0 2006.252.07:44:29.23#ibcon#read 5, iclass 28, count 0 2006.252.07:44:29.23#ibcon#about to read 6, iclass 28, count 0 2006.252.07:44:29.23#ibcon#read 6, iclass 28, count 0 2006.252.07:44:29.23#ibcon#end of sib2, iclass 28, count 0 2006.252.07:44:29.23#ibcon#*after write, iclass 28, count 0 2006.252.07:44:29.23#ibcon#*before return 0, iclass 28, count 0 2006.252.07:44:29.23#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.252.07:44:29.23#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.252.07:44:29.23#ibcon#about to clear, iclass 28 cls_cnt 0 2006.252.07:44:29.23#ibcon#cleared, iclass 28 cls_cnt 0 2006.252.07:44:29.23$vc4f8/valo=5,652.99 2006.252.07:44:29.23#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.252.07:44:29.23#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.252.07:44:29.23#ibcon#ireg 17 cls_cnt 0 2006.252.07:44:29.23#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.252.07:44:29.23#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.252.07:44:29.23#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.252.07:44:29.23#ibcon#enter wrdev, iclass 30, count 0 2006.252.07:44:29.23#ibcon#first serial, iclass 30, count 0 2006.252.07:44:29.23#ibcon#enter sib2, iclass 30, count 0 2006.252.07:44:29.23#ibcon#flushed, iclass 30, count 0 2006.252.07:44:29.23#ibcon#about to write, iclass 30, count 0 2006.252.07:44:29.23#ibcon#wrote, iclass 30, count 0 2006.252.07:44:29.23#ibcon#about to read 3, iclass 30, count 0 2006.252.07:44:29.25#ibcon#read 3, iclass 30, count 0 2006.252.07:44:29.25#ibcon#about to read 4, iclass 30, count 0 2006.252.07:44:29.25#ibcon#read 4, iclass 30, count 0 2006.252.07:44:29.25#ibcon#about to read 5, iclass 30, count 0 2006.252.07:44:29.25#ibcon#read 5, iclass 30, count 0 2006.252.07:44:29.25#ibcon#about to read 6, iclass 30, count 0 2006.252.07:44:29.25#ibcon#read 6, iclass 30, count 0 2006.252.07:44:29.25#ibcon#end of sib2, iclass 30, count 0 2006.252.07:44:29.25#ibcon#*mode == 0, iclass 30, count 0 2006.252.07:44:29.25#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.252.07:44:29.25#ibcon#[26=FRQ=05,652.99\r\n] 2006.252.07:44:29.25#ibcon#*before write, iclass 30, count 0 2006.252.07:44:29.25#ibcon#enter sib2, iclass 30, count 0 2006.252.07:44:29.25#ibcon#flushed, iclass 30, count 0 2006.252.07:44:29.25#ibcon#about to write, iclass 30, count 0 2006.252.07:44:29.25#ibcon#wrote, iclass 30, count 0 2006.252.07:44:29.25#ibcon#about to read 3, iclass 30, count 0 2006.252.07:44:29.29#ibcon#read 3, iclass 30, count 0 2006.252.07:44:29.29#ibcon#about to read 4, iclass 30, count 0 2006.252.07:44:29.29#ibcon#read 4, iclass 30, count 0 2006.252.07:44:29.29#ibcon#about to read 5, iclass 30, count 0 2006.252.07:44:29.29#ibcon#read 5, iclass 30, count 0 2006.252.07:44:29.29#ibcon#about to read 6, iclass 30, count 0 2006.252.07:44:29.29#ibcon#read 6, iclass 30, count 0 2006.252.07:44:29.29#ibcon#end of sib2, iclass 30, count 0 2006.252.07:44:29.29#ibcon#*after write, iclass 30, count 0 2006.252.07:44:29.29#ibcon#*before return 0, iclass 30, count 0 2006.252.07:44:29.29#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.252.07:44:29.29#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.252.07:44:29.29#ibcon#about to clear, iclass 30 cls_cnt 0 2006.252.07:44:29.29#ibcon#cleared, iclass 30 cls_cnt 0 2006.252.07:44:29.29$vc4f8/va=5,7 2006.252.07:44:29.29#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.252.07:44:29.29#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.252.07:44:29.29#ibcon#ireg 11 cls_cnt 2 2006.252.07:44:29.29#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.252.07:44:29.35#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.252.07:44:29.35#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.252.07:44:29.35#ibcon#enter wrdev, iclass 32, count 2 2006.252.07:44:29.35#ibcon#first serial, iclass 32, count 2 2006.252.07:44:29.35#ibcon#enter sib2, iclass 32, count 2 2006.252.07:44:29.35#ibcon#flushed, iclass 32, count 2 2006.252.07:44:29.35#ibcon#about to write, iclass 32, count 2 2006.252.07:44:29.35#ibcon#wrote, iclass 32, count 2 2006.252.07:44:29.35#ibcon#about to read 3, iclass 32, count 2 2006.252.07:44:29.37#ibcon#read 3, iclass 32, count 2 2006.252.07:44:29.37#ibcon#about to read 4, iclass 32, count 2 2006.252.07:44:29.37#ibcon#read 4, iclass 32, count 2 2006.252.07:44:29.37#ibcon#about to read 5, iclass 32, count 2 2006.252.07:44:29.37#ibcon#read 5, iclass 32, count 2 2006.252.07:44:29.37#ibcon#about to read 6, iclass 32, count 2 2006.252.07:44:29.37#ibcon#read 6, iclass 32, count 2 2006.252.07:44:29.37#ibcon#end of sib2, iclass 32, count 2 2006.252.07:44:29.37#ibcon#*mode == 0, iclass 32, count 2 2006.252.07:44:29.37#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.252.07:44:29.37#ibcon#[25=AT05-07\r\n] 2006.252.07:44:29.37#ibcon#*before write, iclass 32, count 2 2006.252.07:44:29.37#ibcon#enter sib2, iclass 32, count 2 2006.252.07:44:29.37#ibcon#flushed, iclass 32, count 2 2006.252.07:44:29.37#ibcon#about to write, iclass 32, count 2 2006.252.07:44:29.37#ibcon#wrote, iclass 32, count 2 2006.252.07:44:29.37#ibcon#about to read 3, iclass 32, count 2 2006.252.07:44:29.40#ibcon#read 3, iclass 32, count 2 2006.252.07:44:29.40#ibcon#about to read 4, iclass 32, count 2 2006.252.07:44:29.40#ibcon#read 4, iclass 32, count 2 2006.252.07:44:29.40#ibcon#about to read 5, iclass 32, count 2 2006.252.07:44:29.40#ibcon#read 5, iclass 32, count 2 2006.252.07:44:29.40#ibcon#about to read 6, iclass 32, count 2 2006.252.07:44:29.40#ibcon#read 6, iclass 32, count 2 2006.252.07:44:29.40#ibcon#end of sib2, iclass 32, count 2 2006.252.07:44:29.40#ibcon#*after write, iclass 32, count 2 2006.252.07:44:29.40#ibcon#*before return 0, iclass 32, count 2 2006.252.07:44:29.40#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.252.07:44:29.40#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.252.07:44:29.40#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.252.07:44:29.40#ibcon#ireg 7 cls_cnt 0 2006.252.07:44:29.40#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.252.07:44:29.52#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.252.07:44:29.52#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.252.07:44:29.52#ibcon#enter wrdev, iclass 32, count 0 2006.252.07:44:29.52#ibcon#first serial, iclass 32, count 0 2006.252.07:44:29.52#ibcon#enter sib2, iclass 32, count 0 2006.252.07:44:29.52#ibcon#flushed, iclass 32, count 0 2006.252.07:44:29.52#ibcon#about to write, iclass 32, count 0 2006.252.07:44:29.52#ibcon#wrote, iclass 32, count 0 2006.252.07:44:29.52#ibcon#about to read 3, iclass 32, count 0 2006.252.07:44:29.54#ibcon#read 3, iclass 32, count 0 2006.252.07:44:29.54#ibcon#about to read 4, iclass 32, count 0 2006.252.07:44:29.54#ibcon#read 4, iclass 32, count 0 2006.252.07:44:29.54#ibcon#about to read 5, iclass 32, count 0 2006.252.07:44:29.54#ibcon#read 5, iclass 32, count 0 2006.252.07:44:29.54#ibcon#about to read 6, iclass 32, count 0 2006.252.07:44:29.54#ibcon#read 6, iclass 32, count 0 2006.252.07:44:29.54#ibcon#end of sib2, iclass 32, count 0 2006.252.07:44:29.54#ibcon#*mode == 0, iclass 32, count 0 2006.252.07:44:29.54#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.252.07:44:29.54#ibcon#[25=USB\r\n] 2006.252.07:44:29.54#ibcon#*before write, iclass 32, count 0 2006.252.07:44:29.54#ibcon#enter sib2, iclass 32, count 0 2006.252.07:44:29.54#ibcon#flushed, iclass 32, count 0 2006.252.07:44:29.54#ibcon#about to write, iclass 32, count 0 2006.252.07:44:29.54#ibcon#wrote, iclass 32, count 0 2006.252.07:44:29.54#ibcon#about to read 3, iclass 32, count 0 2006.252.07:44:29.57#ibcon#read 3, iclass 32, count 0 2006.252.07:44:29.57#ibcon#about to read 4, iclass 32, count 0 2006.252.07:44:29.57#ibcon#read 4, iclass 32, count 0 2006.252.07:44:29.57#ibcon#about to read 5, iclass 32, count 0 2006.252.07:44:29.57#ibcon#read 5, iclass 32, count 0 2006.252.07:44:29.57#ibcon#about to read 6, iclass 32, count 0 2006.252.07:44:29.57#ibcon#read 6, iclass 32, count 0 2006.252.07:44:29.57#ibcon#end of sib2, iclass 32, count 0 2006.252.07:44:29.57#ibcon#*after write, iclass 32, count 0 2006.252.07:44:29.57#ibcon#*before return 0, iclass 32, count 0 2006.252.07:44:29.57#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.252.07:44:29.57#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.252.07:44:29.57#ibcon#about to clear, iclass 32 cls_cnt 0 2006.252.07:44:29.57#ibcon#cleared, iclass 32 cls_cnt 0 2006.252.07:44:29.57$vc4f8/valo=6,772.99 2006.252.07:44:29.57#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.252.07:44:29.57#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.252.07:44:29.57#ibcon#ireg 17 cls_cnt 0 2006.252.07:44:29.57#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.252.07:44:29.57#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.252.07:44:29.57#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.252.07:44:29.57#ibcon#enter wrdev, iclass 34, count 0 2006.252.07:44:29.57#ibcon#first serial, iclass 34, count 0 2006.252.07:44:29.57#ibcon#enter sib2, iclass 34, count 0 2006.252.07:44:29.57#ibcon#flushed, iclass 34, count 0 2006.252.07:44:29.57#ibcon#about to write, iclass 34, count 0 2006.252.07:44:29.57#ibcon#wrote, iclass 34, count 0 2006.252.07:44:29.57#ibcon#about to read 3, iclass 34, count 0 2006.252.07:44:29.59#ibcon#read 3, iclass 34, count 0 2006.252.07:44:29.59#ibcon#about to read 4, iclass 34, count 0 2006.252.07:44:29.59#ibcon#read 4, iclass 34, count 0 2006.252.07:44:29.59#ibcon#about to read 5, iclass 34, count 0 2006.252.07:44:29.59#ibcon#read 5, iclass 34, count 0 2006.252.07:44:29.59#ibcon#about to read 6, iclass 34, count 0 2006.252.07:44:29.59#ibcon#read 6, iclass 34, count 0 2006.252.07:44:29.59#ibcon#end of sib2, iclass 34, count 0 2006.252.07:44:29.59#ibcon#*mode == 0, iclass 34, count 0 2006.252.07:44:29.59#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.252.07:44:29.59#ibcon#[26=FRQ=06,772.99\r\n] 2006.252.07:44:29.59#ibcon#*before write, iclass 34, count 0 2006.252.07:44:29.59#ibcon#enter sib2, iclass 34, count 0 2006.252.07:44:29.59#ibcon#flushed, iclass 34, count 0 2006.252.07:44:29.59#ibcon#about to write, iclass 34, count 0 2006.252.07:44:29.59#ibcon#wrote, iclass 34, count 0 2006.252.07:44:29.59#ibcon#about to read 3, iclass 34, count 0 2006.252.07:44:29.63#ibcon#read 3, iclass 34, count 0 2006.252.07:44:29.63#ibcon#about to read 4, iclass 34, count 0 2006.252.07:44:29.63#ibcon#read 4, iclass 34, count 0 2006.252.07:44:29.63#ibcon#about to read 5, iclass 34, count 0 2006.252.07:44:29.63#ibcon#read 5, iclass 34, count 0 2006.252.07:44:29.63#ibcon#about to read 6, iclass 34, count 0 2006.252.07:44:29.63#ibcon#read 6, iclass 34, count 0 2006.252.07:44:29.63#ibcon#end of sib2, iclass 34, count 0 2006.252.07:44:29.63#ibcon#*after write, iclass 34, count 0 2006.252.07:44:29.63#ibcon#*before return 0, iclass 34, count 0 2006.252.07:44:29.63#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.252.07:44:29.63#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.252.07:44:29.63#ibcon#about to clear, iclass 34 cls_cnt 0 2006.252.07:44:29.63#ibcon#cleared, iclass 34 cls_cnt 0 2006.252.07:44:29.63$vc4f8/va=6,7 2006.252.07:44:29.63#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.252.07:44:29.63#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.252.07:44:29.63#ibcon#ireg 11 cls_cnt 2 2006.252.07:44:29.63#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.252.07:44:29.69#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.252.07:44:29.69#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.252.07:44:29.69#ibcon#enter wrdev, iclass 36, count 2 2006.252.07:44:29.69#ibcon#first serial, iclass 36, count 2 2006.252.07:44:29.69#ibcon#enter sib2, iclass 36, count 2 2006.252.07:44:29.69#ibcon#flushed, iclass 36, count 2 2006.252.07:44:29.69#ibcon#about to write, iclass 36, count 2 2006.252.07:44:29.69#ibcon#wrote, iclass 36, count 2 2006.252.07:44:29.69#ibcon#about to read 3, iclass 36, count 2 2006.252.07:44:29.71#ibcon#read 3, iclass 36, count 2 2006.252.07:44:29.71#ibcon#about to read 4, iclass 36, count 2 2006.252.07:44:29.71#ibcon#read 4, iclass 36, count 2 2006.252.07:44:29.71#ibcon#about to read 5, iclass 36, count 2 2006.252.07:44:29.71#ibcon#read 5, iclass 36, count 2 2006.252.07:44:29.71#ibcon#about to read 6, iclass 36, count 2 2006.252.07:44:29.71#ibcon#read 6, iclass 36, count 2 2006.252.07:44:29.71#ibcon#end of sib2, iclass 36, count 2 2006.252.07:44:29.71#ibcon#*mode == 0, iclass 36, count 2 2006.252.07:44:29.71#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.252.07:44:29.71#ibcon#[25=AT06-07\r\n] 2006.252.07:44:29.71#ibcon#*before write, iclass 36, count 2 2006.252.07:44:29.71#ibcon#enter sib2, iclass 36, count 2 2006.252.07:44:29.71#ibcon#flushed, iclass 36, count 2 2006.252.07:44:29.71#ibcon#about to write, iclass 36, count 2 2006.252.07:44:29.71#ibcon#wrote, iclass 36, count 2 2006.252.07:44:29.71#ibcon#about to read 3, iclass 36, count 2 2006.252.07:44:29.74#ibcon#read 3, iclass 36, count 2 2006.252.07:44:29.74#ibcon#about to read 4, iclass 36, count 2 2006.252.07:44:29.74#ibcon#read 4, iclass 36, count 2 2006.252.07:44:29.74#ibcon#about to read 5, iclass 36, count 2 2006.252.07:44:29.74#ibcon#read 5, iclass 36, count 2 2006.252.07:44:29.74#ibcon#about to read 6, iclass 36, count 2 2006.252.07:44:29.74#ibcon#read 6, iclass 36, count 2 2006.252.07:44:29.74#ibcon#end of sib2, iclass 36, count 2 2006.252.07:44:29.74#ibcon#*after write, iclass 36, count 2 2006.252.07:44:29.74#ibcon#*before return 0, iclass 36, count 2 2006.252.07:44:29.74#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.252.07:44:29.74#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.252.07:44:29.74#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.252.07:44:29.74#ibcon#ireg 7 cls_cnt 0 2006.252.07:44:29.74#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.252.07:44:29.86#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.252.07:44:29.86#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.252.07:44:29.86#ibcon#enter wrdev, iclass 36, count 0 2006.252.07:44:29.86#ibcon#first serial, iclass 36, count 0 2006.252.07:44:29.86#ibcon#enter sib2, iclass 36, count 0 2006.252.07:44:29.86#ibcon#flushed, iclass 36, count 0 2006.252.07:44:29.86#ibcon#about to write, iclass 36, count 0 2006.252.07:44:29.86#ibcon#wrote, iclass 36, count 0 2006.252.07:44:29.86#ibcon#about to read 3, iclass 36, count 0 2006.252.07:44:29.88#ibcon#read 3, iclass 36, count 0 2006.252.07:44:29.88#ibcon#about to read 4, iclass 36, count 0 2006.252.07:44:29.88#ibcon#read 4, iclass 36, count 0 2006.252.07:44:29.88#ibcon#about to read 5, iclass 36, count 0 2006.252.07:44:29.88#ibcon#read 5, iclass 36, count 0 2006.252.07:44:29.88#ibcon#about to read 6, iclass 36, count 0 2006.252.07:44:29.88#ibcon#read 6, iclass 36, count 0 2006.252.07:44:29.88#ibcon#end of sib2, iclass 36, count 0 2006.252.07:44:29.88#ibcon#*mode == 0, iclass 36, count 0 2006.252.07:44:29.88#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.252.07:44:29.88#ibcon#[25=USB\r\n] 2006.252.07:44:29.88#ibcon#*before write, iclass 36, count 0 2006.252.07:44:29.88#ibcon#enter sib2, iclass 36, count 0 2006.252.07:44:29.88#ibcon#flushed, iclass 36, count 0 2006.252.07:44:29.88#ibcon#about to write, iclass 36, count 0 2006.252.07:44:29.88#ibcon#wrote, iclass 36, count 0 2006.252.07:44:29.88#ibcon#about to read 3, iclass 36, count 0 2006.252.07:44:29.91#ibcon#read 3, iclass 36, count 0 2006.252.07:44:29.91#ibcon#about to read 4, iclass 36, count 0 2006.252.07:44:29.91#ibcon#read 4, iclass 36, count 0 2006.252.07:44:29.91#ibcon#about to read 5, iclass 36, count 0 2006.252.07:44:29.91#ibcon#read 5, iclass 36, count 0 2006.252.07:44:29.91#ibcon#about to read 6, iclass 36, count 0 2006.252.07:44:29.91#ibcon#read 6, iclass 36, count 0 2006.252.07:44:29.91#ibcon#end of sib2, iclass 36, count 0 2006.252.07:44:29.91#ibcon#*after write, iclass 36, count 0 2006.252.07:44:29.91#ibcon#*before return 0, iclass 36, count 0 2006.252.07:44:29.91#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.252.07:44:29.91#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.252.07:44:29.91#ibcon#about to clear, iclass 36 cls_cnt 0 2006.252.07:44:29.91#ibcon#cleared, iclass 36 cls_cnt 0 2006.252.07:44:29.91$vc4f8/valo=7,832.99 2006.252.07:44:29.91#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.252.07:44:29.91#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.252.07:44:29.91#ibcon#ireg 17 cls_cnt 0 2006.252.07:44:29.91#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.252.07:44:29.91#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.252.07:44:29.91#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.252.07:44:29.91#ibcon#enter wrdev, iclass 38, count 0 2006.252.07:44:29.91#ibcon#first serial, iclass 38, count 0 2006.252.07:44:29.91#ibcon#enter sib2, iclass 38, count 0 2006.252.07:44:29.91#ibcon#flushed, iclass 38, count 0 2006.252.07:44:29.91#ibcon#about to write, iclass 38, count 0 2006.252.07:44:29.91#ibcon#wrote, iclass 38, count 0 2006.252.07:44:29.91#ibcon#about to read 3, iclass 38, count 0 2006.252.07:44:29.93#ibcon#read 3, iclass 38, count 0 2006.252.07:44:29.93#ibcon#about to read 4, iclass 38, count 0 2006.252.07:44:29.93#ibcon#read 4, iclass 38, count 0 2006.252.07:44:29.93#ibcon#about to read 5, iclass 38, count 0 2006.252.07:44:29.93#ibcon#read 5, iclass 38, count 0 2006.252.07:44:29.93#ibcon#about to read 6, iclass 38, count 0 2006.252.07:44:29.93#ibcon#read 6, iclass 38, count 0 2006.252.07:44:29.93#ibcon#end of sib2, iclass 38, count 0 2006.252.07:44:29.93#ibcon#*mode == 0, iclass 38, count 0 2006.252.07:44:29.93#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.252.07:44:29.93#ibcon#[26=FRQ=07,832.99\r\n] 2006.252.07:44:29.93#ibcon#*before write, iclass 38, count 0 2006.252.07:44:29.93#ibcon#enter sib2, iclass 38, count 0 2006.252.07:44:29.93#ibcon#flushed, iclass 38, count 0 2006.252.07:44:29.93#ibcon#about to write, iclass 38, count 0 2006.252.07:44:29.93#ibcon#wrote, iclass 38, count 0 2006.252.07:44:29.93#ibcon#about to read 3, iclass 38, count 0 2006.252.07:44:29.97#ibcon#read 3, iclass 38, count 0 2006.252.07:44:29.97#ibcon#about to read 4, iclass 38, count 0 2006.252.07:44:29.97#ibcon#read 4, iclass 38, count 0 2006.252.07:44:29.97#ibcon#about to read 5, iclass 38, count 0 2006.252.07:44:29.97#ibcon#read 5, iclass 38, count 0 2006.252.07:44:29.97#ibcon#about to read 6, iclass 38, count 0 2006.252.07:44:29.97#ibcon#read 6, iclass 38, count 0 2006.252.07:44:29.97#ibcon#end of sib2, iclass 38, count 0 2006.252.07:44:29.97#ibcon#*after write, iclass 38, count 0 2006.252.07:44:29.97#ibcon#*before return 0, iclass 38, count 0 2006.252.07:44:29.97#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.252.07:44:29.97#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.252.07:44:29.97#ibcon#about to clear, iclass 38 cls_cnt 0 2006.252.07:44:29.97#ibcon#cleared, iclass 38 cls_cnt 0 2006.252.07:44:29.97$vc4f8/va=7,7 2006.252.07:44:29.97#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.252.07:44:29.97#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.252.07:44:29.97#ibcon#ireg 11 cls_cnt 2 2006.252.07:44:29.97#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.252.07:44:30.04#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.252.07:44:30.04#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.252.07:44:30.04#ibcon#enter wrdev, iclass 40, count 2 2006.252.07:44:30.04#ibcon#first serial, iclass 40, count 2 2006.252.07:44:30.04#ibcon#enter sib2, iclass 40, count 2 2006.252.07:44:30.04#ibcon#flushed, iclass 40, count 2 2006.252.07:44:30.04#ibcon#about to write, iclass 40, count 2 2006.252.07:44:30.04#ibcon#wrote, iclass 40, count 2 2006.252.07:44:30.04#ibcon#about to read 3, iclass 40, count 2 2006.252.07:44:30.05#ibcon#read 3, iclass 40, count 2 2006.252.07:44:30.05#ibcon#about to read 4, iclass 40, count 2 2006.252.07:44:30.05#ibcon#read 4, iclass 40, count 2 2006.252.07:44:30.05#ibcon#about to read 5, iclass 40, count 2 2006.252.07:44:30.05#ibcon#read 5, iclass 40, count 2 2006.252.07:44:30.05#ibcon#about to read 6, iclass 40, count 2 2006.252.07:44:30.05#ibcon#read 6, iclass 40, count 2 2006.252.07:44:30.05#ibcon#end of sib2, iclass 40, count 2 2006.252.07:44:30.05#ibcon#*mode == 0, iclass 40, count 2 2006.252.07:44:30.05#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.252.07:44:30.05#ibcon#[25=AT07-07\r\n] 2006.252.07:44:30.05#ibcon#*before write, iclass 40, count 2 2006.252.07:44:30.05#ibcon#enter sib2, iclass 40, count 2 2006.252.07:44:30.05#ibcon#flushed, iclass 40, count 2 2006.252.07:44:30.05#ibcon#about to write, iclass 40, count 2 2006.252.07:44:30.05#ibcon#wrote, iclass 40, count 2 2006.252.07:44:30.05#ibcon#about to read 3, iclass 40, count 2 2006.252.07:44:30.08#ibcon#read 3, iclass 40, count 2 2006.252.07:44:30.08#ibcon#about to read 4, iclass 40, count 2 2006.252.07:44:30.08#ibcon#read 4, iclass 40, count 2 2006.252.07:44:30.08#ibcon#about to read 5, iclass 40, count 2 2006.252.07:44:30.08#ibcon#read 5, iclass 40, count 2 2006.252.07:44:30.08#ibcon#about to read 6, iclass 40, count 2 2006.252.07:44:30.08#ibcon#read 6, iclass 40, count 2 2006.252.07:44:30.08#ibcon#end of sib2, iclass 40, count 2 2006.252.07:44:30.08#ibcon#*after write, iclass 40, count 2 2006.252.07:44:30.08#ibcon#*before return 0, iclass 40, count 2 2006.252.07:44:30.08#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.252.07:44:30.08#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.252.07:44:30.08#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.252.07:44:30.08#ibcon#ireg 7 cls_cnt 0 2006.252.07:44:30.08#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.252.07:44:30.20#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.252.07:44:30.20#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.252.07:44:30.20#ibcon#enter wrdev, iclass 40, count 0 2006.252.07:44:30.20#ibcon#first serial, iclass 40, count 0 2006.252.07:44:30.20#ibcon#enter sib2, iclass 40, count 0 2006.252.07:44:30.20#ibcon#flushed, iclass 40, count 0 2006.252.07:44:30.20#ibcon#about to write, iclass 40, count 0 2006.252.07:44:30.20#ibcon#wrote, iclass 40, count 0 2006.252.07:44:30.20#ibcon#about to read 3, iclass 40, count 0 2006.252.07:44:30.24#ibcon#read 3, iclass 40, count 0 2006.252.07:44:30.24#ibcon#about to read 4, iclass 40, count 0 2006.252.07:44:30.24#ibcon#read 4, iclass 40, count 0 2006.252.07:44:30.24#ibcon#about to read 5, iclass 40, count 0 2006.252.07:44:30.24#ibcon#read 5, iclass 40, count 0 2006.252.07:44:30.24#ibcon#about to read 6, iclass 40, count 0 2006.252.07:44:30.24#ibcon#read 6, iclass 40, count 0 2006.252.07:44:30.24#ibcon#end of sib2, iclass 40, count 0 2006.252.07:44:30.24#ibcon#*mode == 0, iclass 40, count 0 2006.252.07:44:30.24#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.252.07:44:30.24#ibcon#[25=USB\r\n] 2006.252.07:44:30.24#ibcon#*before write, iclass 40, count 0 2006.252.07:44:30.24#ibcon#enter sib2, iclass 40, count 0 2006.252.07:44:30.24#ibcon#flushed, iclass 40, count 0 2006.252.07:44:30.24#ibcon#about to write, iclass 40, count 0 2006.252.07:44:30.24#ibcon#wrote, iclass 40, count 0 2006.252.07:44:30.24#ibcon#about to read 3, iclass 40, count 0 2006.252.07:44:30.26#ibcon#read 3, iclass 40, count 0 2006.252.07:44:30.26#ibcon#about to read 4, iclass 40, count 0 2006.252.07:44:30.26#ibcon#read 4, iclass 40, count 0 2006.252.07:44:30.26#ibcon#about to read 5, iclass 40, count 0 2006.252.07:44:30.26#ibcon#read 5, iclass 40, count 0 2006.252.07:44:30.26#ibcon#about to read 6, iclass 40, count 0 2006.252.07:44:30.26#ibcon#read 6, iclass 40, count 0 2006.252.07:44:30.26#ibcon#end of sib2, iclass 40, count 0 2006.252.07:44:30.26#ibcon#*after write, iclass 40, count 0 2006.252.07:44:30.26#ibcon#*before return 0, iclass 40, count 0 2006.252.07:44:30.26#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.252.07:44:30.26#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.252.07:44:30.26#ibcon#about to clear, iclass 40 cls_cnt 0 2006.252.07:44:30.26#ibcon#cleared, iclass 40 cls_cnt 0 2006.252.07:44:30.26$vc4f8/valo=8,852.99 2006.252.07:44:30.26#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.252.07:44:30.26#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.252.07:44:30.26#ibcon#ireg 17 cls_cnt 0 2006.252.07:44:30.26#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.252.07:44:30.26#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.252.07:44:30.26#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.252.07:44:30.26#ibcon#enter wrdev, iclass 4, count 0 2006.252.07:44:30.26#ibcon#first serial, iclass 4, count 0 2006.252.07:44:30.26#ibcon#enter sib2, iclass 4, count 0 2006.252.07:44:30.26#ibcon#flushed, iclass 4, count 0 2006.252.07:44:30.26#ibcon#about to write, iclass 4, count 0 2006.252.07:44:30.26#ibcon#wrote, iclass 4, count 0 2006.252.07:44:30.26#ibcon#about to read 3, iclass 4, count 0 2006.252.07:44:30.28#ibcon#read 3, iclass 4, count 0 2006.252.07:44:30.28#ibcon#about to read 4, iclass 4, count 0 2006.252.07:44:30.28#ibcon#read 4, iclass 4, count 0 2006.252.07:44:30.28#ibcon#about to read 5, iclass 4, count 0 2006.252.07:44:30.28#ibcon#read 5, iclass 4, count 0 2006.252.07:44:30.28#ibcon#about to read 6, iclass 4, count 0 2006.252.07:44:30.28#ibcon#read 6, iclass 4, count 0 2006.252.07:44:30.28#ibcon#end of sib2, iclass 4, count 0 2006.252.07:44:30.28#ibcon#*mode == 0, iclass 4, count 0 2006.252.07:44:30.28#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.252.07:44:30.28#ibcon#[26=FRQ=08,852.99\r\n] 2006.252.07:44:30.28#ibcon#*before write, iclass 4, count 0 2006.252.07:44:30.28#ibcon#enter sib2, iclass 4, count 0 2006.252.07:44:30.28#ibcon#flushed, iclass 4, count 0 2006.252.07:44:30.28#ibcon#about to write, iclass 4, count 0 2006.252.07:44:30.28#ibcon#wrote, iclass 4, count 0 2006.252.07:44:30.28#ibcon#about to read 3, iclass 4, count 0 2006.252.07:44:30.32#ibcon#read 3, iclass 4, count 0 2006.252.07:44:30.32#ibcon#about to read 4, iclass 4, count 0 2006.252.07:44:30.32#ibcon#read 4, iclass 4, count 0 2006.252.07:44:30.32#ibcon#about to read 5, iclass 4, count 0 2006.252.07:44:30.32#ibcon#read 5, iclass 4, count 0 2006.252.07:44:30.32#ibcon#about to read 6, iclass 4, count 0 2006.252.07:44:30.32#ibcon#read 6, iclass 4, count 0 2006.252.07:44:30.32#ibcon#end of sib2, iclass 4, count 0 2006.252.07:44:30.32#ibcon#*after write, iclass 4, count 0 2006.252.07:44:30.32#ibcon#*before return 0, iclass 4, count 0 2006.252.07:44:30.32#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.252.07:44:30.32#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.252.07:44:30.32#ibcon#about to clear, iclass 4 cls_cnt 0 2006.252.07:44:30.32#ibcon#cleared, iclass 4 cls_cnt 0 2006.252.07:44:30.32$vc4f8/va=8,7 2006.252.07:44:30.32#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.252.07:44:30.32#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.252.07:44:30.32#ibcon#ireg 11 cls_cnt 2 2006.252.07:44:30.32#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.252.07:44:30.38#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.252.07:44:30.38#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.252.07:44:30.38#ibcon#enter wrdev, iclass 6, count 2 2006.252.07:44:30.38#ibcon#first serial, iclass 6, count 2 2006.252.07:44:30.38#ibcon#enter sib2, iclass 6, count 2 2006.252.07:44:30.38#ibcon#flushed, iclass 6, count 2 2006.252.07:44:30.38#ibcon#about to write, iclass 6, count 2 2006.252.07:44:30.38#ibcon#wrote, iclass 6, count 2 2006.252.07:44:30.38#ibcon#about to read 3, iclass 6, count 2 2006.252.07:44:30.40#ibcon#read 3, iclass 6, count 2 2006.252.07:44:30.40#ibcon#about to read 4, iclass 6, count 2 2006.252.07:44:30.40#ibcon#read 4, iclass 6, count 2 2006.252.07:44:30.40#ibcon#about to read 5, iclass 6, count 2 2006.252.07:44:30.40#ibcon#read 5, iclass 6, count 2 2006.252.07:44:30.40#ibcon#about to read 6, iclass 6, count 2 2006.252.07:44:30.40#ibcon#read 6, iclass 6, count 2 2006.252.07:44:30.40#ibcon#end of sib2, iclass 6, count 2 2006.252.07:44:30.40#ibcon#*mode == 0, iclass 6, count 2 2006.252.07:44:30.40#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.252.07:44:30.40#ibcon#[25=AT08-07\r\n] 2006.252.07:44:30.40#ibcon#*before write, iclass 6, count 2 2006.252.07:44:30.40#ibcon#enter sib2, iclass 6, count 2 2006.252.07:44:30.40#ibcon#flushed, iclass 6, count 2 2006.252.07:44:30.40#ibcon#about to write, iclass 6, count 2 2006.252.07:44:30.40#ibcon#wrote, iclass 6, count 2 2006.252.07:44:30.40#ibcon#about to read 3, iclass 6, count 2 2006.252.07:44:30.43#ibcon#read 3, iclass 6, count 2 2006.252.07:44:30.43#ibcon#about to read 4, iclass 6, count 2 2006.252.07:44:30.43#ibcon#read 4, iclass 6, count 2 2006.252.07:44:30.43#ibcon#about to read 5, iclass 6, count 2 2006.252.07:44:30.43#ibcon#read 5, iclass 6, count 2 2006.252.07:44:30.43#ibcon#about to read 6, iclass 6, count 2 2006.252.07:44:30.43#ibcon#read 6, iclass 6, count 2 2006.252.07:44:30.43#ibcon#end of sib2, iclass 6, count 2 2006.252.07:44:30.43#ibcon#*after write, iclass 6, count 2 2006.252.07:44:30.43#ibcon#*before return 0, iclass 6, count 2 2006.252.07:44:30.43#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.252.07:44:30.43#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.252.07:44:30.43#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.252.07:44:30.43#ibcon#ireg 7 cls_cnt 0 2006.252.07:44:30.43#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.252.07:44:30.55#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.252.07:44:30.55#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.252.07:44:30.55#ibcon#enter wrdev, iclass 6, count 0 2006.252.07:44:30.55#ibcon#first serial, iclass 6, count 0 2006.252.07:44:30.55#ibcon#enter sib2, iclass 6, count 0 2006.252.07:44:30.55#ibcon#flushed, iclass 6, count 0 2006.252.07:44:30.55#ibcon#about to write, iclass 6, count 0 2006.252.07:44:30.55#ibcon#wrote, iclass 6, count 0 2006.252.07:44:30.55#ibcon#about to read 3, iclass 6, count 0 2006.252.07:44:30.57#ibcon#read 3, iclass 6, count 0 2006.252.07:44:30.57#ibcon#about to read 4, iclass 6, count 0 2006.252.07:44:30.57#ibcon#read 4, iclass 6, count 0 2006.252.07:44:30.57#ibcon#about to read 5, iclass 6, count 0 2006.252.07:44:30.57#ibcon#read 5, iclass 6, count 0 2006.252.07:44:30.57#ibcon#about to read 6, iclass 6, count 0 2006.252.07:44:30.57#ibcon#read 6, iclass 6, count 0 2006.252.07:44:30.57#ibcon#end of sib2, iclass 6, count 0 2006.252.07:44:30.57#ibcon#*mode == 0, iclass 6, count 0 2006.252.07:44:30.57#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.252.07:44:30.57#ibcon#[25=USB\r\n] 2006.252.07:44:30.57#ibcon#*before write, iclass 6, count 0 2006.252.07:44:30.57#ibcon#enter sib2, iclass 6, count 0 2006.252.07:44:30.57#ibcon#flushed, iclass 6, count 0 2006.252.07:44:30.57#ibcon#about to write, iclass 6, count 0 2006.252.07:44:30.57#ibcon#wrote, iclass 6, count 0 2006.252.07:44:30.57#ibcon#about to read 3, iclass 6, count 0 2006.252.07:44:30.60#ibcon#read 3, iclass 6, count 0 2006.252.07:44:30.60#ibcon#about to read 4, iclass 6, count 0 2006.252.07:44:30.60#ibcon#read 4, iclass 6, count 0 2006.252.07:44:30.60#ibcon#about to read 5, iclass 6, count 0 2006.252.07:44:30.60#ibcon#read 5, iclass 6, count 0 2006.252.07:44:30.60#ibcon#about to read 6, iclass 6, count 0 2006.252.07:44:30.60#ibcon#read 6, iclass 6, count 0 2006.252.07:44:30.60#ibcon#end of sib2, iclass 6, count 0 2006.252.07:44:30.60#ibcon#*after write, iclass 6, count 0 2006.252.07:44:30.60#ibcon#*before return 0, iclass 6, count 0 2006.252.07:44:30.60#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.252.07:44:30.60#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.252.07:44:30.60#ibcon#about to clear, iclass 6 cls_cnt 0 2006.252.07:44:30.60#ibcon#cleared, iclass 6 cls_cnt 0 2006.252.07:44:30.60$vc4f8/vblo=1,632.99 2006.252.07:44:30.60#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.252.07:44:30.60#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.252.07:44:30.60#ibcon#ireg 17 cls_cnt 0 2006.252.07:44:30.60#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.252.07:44:30.60#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.252.07:44:30.60#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.252.07:44:30.60#ibcon#enter wrdev, iclass 10, count 0 2006.252.07:44:30.60#ibcon#first serial, iclass 10, count 0 2006.252.07:44:30.60#ibcon#enter sib2, iclass 10, count 0 2006.252.07:44:30.60#ibcon#flushed, iclass 10, count 0 2006.252.07:44:30.60#ibcon#about to write, iclass 10, count 0 2006.252.07:44:30.60#ibcon#wrote, iclass 10, count 0 2006.252.07:44:30.60#ibcon#about to read 3, iclass 10, count 0 2006.252.07:44:30.62#ibcon#read 3, iclass 10, count 0 2006.252.07:44:30.62#ibcon#about to read 4, iclass 10, count 0 2006.252.07:44:30.62#ibcon#read 4, iclass 10, count 0 2006.252.07:44:30.62#ibcon#about to read 5, iclass 10, count 0 2006.252.07:44:30.62#ibcon#read 5, iclass 10, count 0 2006.252.07:44:30.62#ibcon#about to read 6, iclass 10, count 0 2006.252.07:44:30.62#ibcon#read 6, iclass 10, count 0 2006.252.07:44:30.62#ibcon#end of sib2, iclass 10, count 0 2006.252.07:44:30.62#ibcon#*mode == 0, iclass 10, count 0 2006.252.07:44:30.62#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.252.07:44:30.62#ibcon#[28=FRQ=01,632.99\r\n] 2006.252.07:44:30.62#ibcon#*before write, iclass 10, count 0 2006.252.07:44:30.62#ibcon#enter sib2, iclass 10, count 0 2006.252.07:44:30.62#ibcon#flushed, iclass 10, count 0 2006.252.07:44:30.62#ibcon#about to write, iclass 10, count 0 2006.252.07:44:30.62#ibcon#wrote, iclass 10, count 0 2006.252.07:44:30.62#ibcon#about to read 3, iclass 10, count 0 2006.252.07:44:30.66#ibcon#read 3, iclass 10, count 0 2006.252.07:44:30.66#ibcon#about to read 4, iclass 10, count 0 2006.252.07:44:30.66#ibcon#read 4, iclass 10, count 0 2006.252.07:44:30.66#ibcon#about to read 5, iclass 10, count 0 2006.252.07:44:30.66#ibcon#read 5, iclass 10, count 0 2006.252.07:44:30.66#ibcon#about to read 6, iclass 10, count 0 2006.252.07:44:30.66#ibcon#read 6, iclass 10, count 0 2006.252.07:44:30.66#ibcon#end of sib2, iclass 10, count 0 2006.252.07:44:30.66#ibcon#*after write, iclass 10, count 0 2006.252.07:44:30.66#ibcon#*before return 0, iclass 10, count 0 2006.252.07:44:30.66#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.252.07:44:30.66#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.252.07:44:30.66#ibcon#about to clear, iclass 10 cls_cnt 0 2006.252.07:44:30.66#ibcon#cleared, iclass 10 cls_cnt 0 2006.252.07:44:30.66$vc4f8/vb=1,4 2006.252.07:44:30.66#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.252.07:44:30.66#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.252.07:44:30.66#ibcon#ireg 11 cls_cnt 2 2006.252.07:44:30.66#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.252.07:44:30.66#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.252.07:44:30.66#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.252.07:44:30.66#ibcon#enter wrdev, iclass 12, count 2 2006.252.07:44:30.66#ibcon#first serial, iclass 12, count 2 2006.252.07:44:30.66#ibcon#enter sib2, iclass 12, count 2 2006.252.07:44:30.66#ibcon#flushed, iclass 12, count 2 2006.252.07:44:30.66#ibcon#about to write, iclass 12, count 2 2006.252.07:44:30.66#ibcon#wrote, iclass 12, count 2 2006.252.07:44:30.66#ibcon#about to read 3, iclass 12, count 2 2006.252.07:44:30.68#ibcon#read 3, iclass 12, count 2 2006.252.07:44:30.68#ibcon#about to read 4, iclass 12, count 2 2006.252.07:44:30.68#ibcon#read 4, iclass 12, count 2 2006.252.07:44:30.68#ibcon#about to read 5, iclass 12, count 2 2006.252.07:44:30.68#ibcon#read 5, iclass 12, count 2 2006.252.07:44:30.68#ibcon#about to read 6, iclass 12, count 2 2006.252.07:44:30.68#ibcon#read 6, iclass 12, count 2 2006.252.07:44:30.68#ibcon#end of sib2, iclass 12, count 2 2006.252.07:44:30.68#ibcon#*mode == 0, iclass 12, count 2 2006.252.07:44:30.68#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.252.07:44:30.68#ibcon#[27=AT01-04\r\n] 2006.252.07:44:30.68#ibcon#*before write, iclass 12, count 2 2006.252.07:44:30.68#ibcon#enter sib2, iclass 12, count 2 2006.252.07:44:30.68#ibcon#flushed, iclass 12, count 2 2006.252.07:44:30.68#ibcon#about to write, iclass 12, count 2 2006.252.07:44:30.68#ibcon#wrote, iclass 12, count 2 2006.252.07:44:30.68#ibcon#about to read 3, iclass 12, count 2 2006.252.07:44:30.71#ibcon#read 3, iclass 12, count 2 2006.252.07:44:30.71#ibcon#about to read 4, iclass 12, count 2 2006.252.07:44:30.71#ibcon#read 4, iclass 12, count 2 2006.252.07:44:30.71#ibcon#about to read 5, iclass 12, count 2 2006.252.07:44:30.71#ibcon#read 5, iclass 12, count 2 2006.252.07:44:30.71#ibcon#about to read 6, iclass 12, count 2 2006.252.07:44:30.71#ibcon#read 6, iclass 12, count 2 2006.252.07:44:30.71#ibcon#end of sib2, iclass 12, count 2 2006.252.07:44:30.71#ibcon#*after write, iclass 12, count 2 2006.252.07:44:30.71#ibcon#*before return 0, iclass 12, count 2 2006.252.07:44:30.71#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.252.07:44:30.71#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.252.07:44:30.71#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.252.07:44:30.71#ibcon#ireg 7 cls_cnt 0 2006.252.07:44:30.71#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.252.07:44:30.83#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.252.07:44:30.83#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.252.07:44:30.83#ibcon#enter wrdev, iclass 12, count 0 2006.252.07:44:30.83#ibcon#first serial, iclass 12, count 0 2006.252.07:44:30.83#ibcon#enter sib2, iclass 12, count 0 2006.252.07:44:30.83#ibcon#flushed, iclass 12, count 0 2006.252.07:44:30.83#ibcon#about to write, iclass 12, count 0 2006.252.07:44:30.83#ibcon#wrote, iclass 12, count 0 2006.252.07:44:30.83#ibcon#about to read 3, iclass 12, count 0 2006.252.07:44:30.85#ibcon#read 3, iclass 12, count 0 2006.252.07:44:30.85#ibcon#about to read 4, iclass 12, count 0 2006.252.07:44:30.85#ibcon#read 4, iclass 12, count 0 2006.252.07:44:30.85#ibcon#about to read 5, iclass 12, count 0 2006.252.07:44:30.85#ibcon#read 5, iclass 12, count 0 2006.252.07:44:30.85#ibcon#about to read 6, iclass 12, count 0 2006.252.07:44:30.85#ibcon#read 6, iclass 12, count 0 2006.252.07:44:30.85#ibcon#end of sib2, iclass 12, count 0 2006.252.07:44:30.85#ibcon#*mode == 0, iclass 12, count 0 2006.252.07:44:30.85#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.252.07:44:30.85#ibcon#[27=USB\r\n] 2006.252.07:44:30.85#ibcon#*before write, iclass 12, count 0 2006.252.07:44:30.85#ibcon#enter sib2, iclass 12, count 0 2006.252.07:44:30.85#ibcon#flushed, iclass 12, count 0 2006.252.07:44:30.85#ibcon#about to write, iclass 12, count 0 2006.252.07:44:30.85#ibcon#wrote, iclass 12, count 0 2006.252.07:44:30.85#ibcon#about to read 3, iclass 12, count 0 2006.252.07:44:30.88#ibcon#read 3, iclass 12, count 0 2006.252.07:44:30.88#ibcon#about to read 4, iclass 12, count 0 2006.252.07:44:30.88#ibcon#read 4, iclass 12, count 0 2006.252.07:44:30.88#ibcon#about to read 5, iclass 12, count 0 2006.252.07:44:30.88#ibcon#read 5, iclass 12, count 0 2006.252.07:44:30.88#ibcon#about to read 6, iclass 12, count 0 2006.252.07:44:30.88#ibcon#read 6, iclass 12, count 0 2006.252.07:44:30.88#ibcon#end of sib2, iclass 12, count 0 2006.252.07:44:30.88#ibcon#*after write, iclass 12, count 0 2006.252.07:44:30.88#ibcon#*before return 0, iclass 12, count 0 2006.252.07:44:30.88#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.252.07:44:30.88#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.252.07:44:30.88#ibcon#about to clear, iclass 12 cls_cnt 0 2006.252.07:44:30.88#ibcon#cleared, iclass 12 cls_cnt 0 2006.252.07:44:30.88$vc4f8/vblo=2,640.99 2006.252.07:44:30.88#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.252.07:44:30.88#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.252.07:44:30.88#ibcon#ireg 17 cls_cnt 0 2006.252.07:44:30.88#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.252.07:44:30.88#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.252.07:44:30.88#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.252.07:44:30.88#ibcon#enter wrdev, iclass 14, count 0 2006.252.07:44:30.88#ibcon#first serial, iclass 14, count 0 2006.252.07:44:30.88#ibcon#enter sib2, iclass 14, count 0 2006.252.07:44:30.88#ibcon#flushed, iclass 14, count 0 2006.252.07:44:30.88#ibcon#about to write, iclass 14, count 0 2006.252.07:44:30.88#ibcon#wrote, iclass 14, count 0 2006.252.07:44:30.88#ibcon#about to read 3, iclass 14, count 0 2006.252.07:44:30.91#ibcon#read 3, iclass 14, count 0 2006.252.07:44:30.91#ibcon#about to read 4, iclass 14, count 0 2006.252.07:44:30.91#ibcon#read 4, iclass 14, count 0 2006.252.07:44:30.91#ibcon#about to read 5, iclass 14, count 0 2006.252.07:44:30.91#ibcon#read 5, iclass 14, count 0 2006.252.07:44:30.91#ibcon#about to read 6, iclass 14, count 0 2006.252.07:44:30.91#ibcon#read 6, iclass 14, count 0 2006.252.07:44:30.91#ibcon#end of sib2, iclass 14, count 0 2006.252.07:44:30.91#ibcon#*mode == 0, iclass 14, count 0 2006.252.07:44:30.91#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.252.07:44:30.91#ibcon#[28=FRQ=02,640.99\r\n] 2006.252.07:44:30.91#ibcon#*before write, iclass 14, count 0 2006.252.07:44:30.91#ibcon#enter sib2, iclass 14, count 0 2006.252.07:44:30.91#ibcon#flushed, iclass 14, count 0 2006.252.07:44:30.91#ibcon#about to write, iclass 14, count 0 2006.252.07:44:30.91#ibcon#wrote, iclass 14, count 0 2006.252.07:44:30.91#ibcon#about to read 3, iclass 14, count 0 2006.252.07:44:30.95#ibcon#read 3, iclass 14, count 0 2006.252.07:44:30.95#ibcon#about to read 4, iclass 14, count 0 2006.252.07:44:30.95#ibcon#read 4, iclass 14, count 0 2006.252.07:44:30.95#ibcon#about to read 5, iclass 14, count 0 2006.252.07:44:30.95#ibcon#read 5, iclass 14, count 0 2006.252.07:44:30.95#ibcon#about to read 6, iclass 14, count 0 2006.252.07:44:30.95#ibcon#read 6, iclass 14, count 0 2006.252.07:44:30.95#ibcon#end of sib2, iclass 14, count 0 2006.252.07:44:30.95#ibcon#*after write, iclass 14, count 0 2006.252.07:44:30.95#ibcon#*before return 0, iclass 14, count 0 2006.252.07:44:30.95#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.252.07:44:30.95#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.252.07:44:30.95#ibcon#about to clear, iclass 14 cls_cnt 0 2006.252.07:44:30.95#ibcon#cleared, iclass 14 cls_cnt 0 2006.252.07:44:30.95$vc4f8/vb=2,5 2006.252.07:44:30.95#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.252.07:44:30.95#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.252.07:44:30.95#ibcon#ireg 11 cls_cnt 2 2006.252.07:44:30.95#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.252.07:44:31.00#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.252.07:44:31.00#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.252.07:44:31.00#ibcon#enter wrdev, iclass 16, count 2 2006.252.07:44:31.00#ibcon#first serial, iclass 16, count 2 2006.252.07:44:31.00#ibcon#enter sib2, iclass 16, count 2 2006.252.07:44:31.00#ibcon#flushed, iclass 16, count 2 2006.252.07:44:31.01#ibcon#about to write, iclass 16, count 2 2006.252.07:44:31.01#ibcon#wrote, iclass 16, count 2 2006.252.07:44:31.01#ibcon#about to read 3, iclass 16, count 2 2006.252.07:44:31.02#ibcon#read 3, iclass 16, count 2 2006.252.07:44:31.02#ibcon#about to read 4, iclass 16, count 2 2006.252.07:44:31.02#ibcon#read 4, iclass 16, count 2 2006.252.07:44:31.02#ibcon#about to read 5, iclass 16, count 2 2006.252.07:44:31.02#ibcon#read 5, iclass 16, count 2 2006.252.07:44:31.02#ibcon#about to read 6, iclass 16, count 2 2006.252.07:44:31.02#ibcon#read 6, iclass 16, count 2 2006.252.07:44:31.02#ibcon#end of sib2, iclass 16, count 2 2006.252.07:44:31.02#ibcon#*mode == 0, iclass 16, count 2 2006.252.07:44:31.02#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.252.07:44:31.02#ibcon#[27=AT02-05\r\n] 2006.252.07:44:31.02#ibcon#*before write, iclass 16, count 2 2006.252.07:44:31.02#ibcon#enter sib2, iclass 16, count 2 2006.252.07:44:31.02#ibcon#flushed, iclass 16, count 2 2006.252.07:44:31.02#ibcon#about to write, iclass 16, count 2 2006.252.07:44:31.02#ibcon#wrote, iclass 16, count 2 2006.252.07:44:31.02#ibcon#about to read 3, iclass 16, count 2 2006.252.07:44:31.05#ibcon#read 3, iclass 16, count 2 2006.252.07:44:31.05#ibcon#about to read 4, iclass 16, count 2 2006.252.07:44:31.05#ibcon#read 4, iclass 16, count 2 2006.252.07:44:31.05#ibcon#about to read 5, iclass 16, count 2 2006.252.07:44:31.05#ibcon#read 5, iclass 16, count 2 2006.252.07:44:31.05#ibcon#about to read 6, iclass 16, count 2 2006.252.07:44:31.05#ibcon#read 6, iclass 16, count 2 2006.252.07:44:31.05#ibcon#end of sib2, iclass 16, count 2 2006.252.07:44:31.05#ibcon#*after write, iclass 16, count 2 2006.252.07:44:31.05#ibcon#*before return 0, iclass 16, count 2 2006.252.07:44:31.05#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.252.07:44:31.05#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.252.07:44:31.05#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.252.07:44:31.05#ibcon#ireg 7 cls_cnt 0 2006.252.07:44:31.05#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.252.07:44:31.17#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.252.07:44:31.17#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.252.07:44:31.17#ibcon#enter wrdev, iclass 16, count 0 2006.252.07:44:31.17#ibcon#first serial, iclass 16, count 0 2006.252.07:44:31.17#ibcon#enter sib2, iclass 16, count 0 2006.252.07:44:31.17#ibcon#flushed, iclass 16, count 0 2006.252.07:44:31.17#ibcon#about to write, iclass 16, count 0 2006.252.07:44:31.17#ibcon#wrote, iclass 16, count 0 2006.252.07:44:31.17#ibcon#about to read 3, iclass 16, count 0 2006.252.07:44:31.19#ibcon#read 3, iclass 16, count 0 2006.252.07:44:31.19#ibcon#about to read 4, iclass 16, count 0 2006.252.07:44:31.19#ibcon#read 4, iclass 16, count 0 2006.252.07:44:31.19#ibcon#about to read 5, iclass 16, count 0 2006.252.07:44:31.19#ibcon#read 5, iclass 16, count 0 2006.252.07:44:31.19#ibcon#about to read 6, iclass 16, count 0 2006.252.07:44:31.19#ibcon#read 6, iclass 16, count 0 2006.252.07:44:31.19#ibcon#end of sib2, iclass 16, count 0 2006.252.07:44:31.19#ibcon#*mode == 0, iclass 16, count 0 2006.252.07:44:31.19#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.252.07:44:31.19#ibcon#[27=USB\r\n] 2006.252.07:44:31.19#ibcon#*before write, iclass 16, count 0 2006.252.07:44:31.19#ibcon#enter sib2, iclass 16, count 0 2006.252.07:44:31.19#ibcon#flushed, iclass 16, count 0 2006.252.07:44:31.19#ibcon#about to write, iclass 16, count 0 2006.252.07:44:31.19#ibcon#wrote, iclass 16, count 0 2006.252.07:44:31.19#ibcon#about to read 3, iclass 16, count 0 2006.252.07:44:31.22#ibcon#read 3, iclass 16, count 0 2006.252.07:44:31.22#ibcon#about to read 4, iclass 16, count 0 2006.252.07:44:31.22#ibcon#read 4, iclass 16, count 0 2006.252.07:44:31.22#ibcon#about to read 5, iclass 16, count 0 2006.252.07:44:31.22#ibcon#read 5, iclass 16, count 0 2006.252.07:44:31.22#ibcon#about to read 6, iclass 16, count 0 2006.252.07:44:31.22#ibcon#read 6, iclass 16, count 0 2006.252.07:44:31.22#ibcon#end of sib2, iclass 16, count 0 2006.252.07:44:31.22#ibcon#*after write, iclass 16, count 0 2006.252.07:44:31.22#ibcon#*before return 0, iclass 16, count 0 2006.252.07:44:31.22#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.252.07:44:31.22#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.252.07:44:31.22#ibcon#about to clear, iclass 16 cls_cnt 0 2006.252.07:44:31.22#ibcon#cleared, iclass 16 cls_cnt 0 2006.252.07:44:31.22$vc4f8/vblo=3,656.99 2006.252.07:44:31.22#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.252.07:44:31.22#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.252.07:44:31.22#ibcon#ireg 17 cls_cnt 0 2006.252.07:44:31.22#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.252.07:44:31.22#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.252.07:44:31.22#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.252.07:44:31.22#ibcon#enter wrdev, iclass 18, count 0 2006.252.07:44:31.22#ibcon#first serial, iclass 18, count 0 2006.252.07:44:31.22#ibcon#enter sib2, iclass 18, count 0 2006.252.07:44:31.22#ibcon#flushed, iclass 18, count 0 2006.252.07:44:31.22#ibcon#about to write, iclass 18, count 0 2006.252.07:44:31.22#ibcon#wrote, iclass 18, count 0 2006.252.07:44:31.22#ibcon#about to read 3, iclass 18, count 0 2006.252.07:44:31.24#ibcon#read 3, iclass 18, count 0 2006.252.07:44:31.24#ibcon#about to read 4, iclass 18, count 0 2006.252.07:44:31.24#ibcon#read 4, iclass 18, count 0 2006.252.07:44:31.24#ibcon#about to read 5, iclass 18, count 0 2006.252.07:44:31.24#ibcon#read 5, iclass 18, count 0 2006.252.07:44:31.24#ibcon#about to read 6, iclass 18, count 0 2006.252.07:44:31.24#ibcon#read 6, iclass 18, count 0 2006.252.07:44:31.24#ibcon#end of sib2, iclass 18, count 0 2006.252.07:44:31.24#ibcon#*mode == 0, iclass 18, count 0 2006.252.07:44:31.24#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.252.07:44:31.24#ibcon#[28=FRQ=03,656.99\r\n] 2006.252.07:44:31.24#ibcon#*before write, iclass 18, count 0 2006.252.07:44:31.24#ibcon#enter sib2, iclass 18, count 0 2006.252.07:44:31.24#ibcon#flushed, iclass 18, count 0 2006.252.07:44:31.24#ibcon#about to write, iclass 18, count 0 2006.252.07:44:31.24#ibcon#wrote, iclass 18, count 0 2006.252.07:44:31.24#ibcon#about to read 3, iclass 18, count 0 2006.252.07:44:31.28#ibcon#read 3, iclass 18, count 0 2006.252.07:44:31.28#ibcon#about to read 4, iclass 18, count 0 2006.252.07:44:31.28#ibcon#read 4, iclass 18, count 0 2006.252.07:44:31.28#ibcon#about to read 5, iclass 18, count 0 2006.252.07:44:31.28#ibcon#read 5, iclass 18, count 0 2006.252.07:44:31.28#ibcon#about to read 6, iclass 18, count 0 2006.252.07:44:31.28#ibcon#read 6, iclass 18, count 0 2006.252.07:44:31.28#ibcon#end of sib2, iclass 18, count 0 2006.252.07:44:31.28#ibcon#*after write, iclass 18, count 0 2006.252.07:44:31.28#ibcon#*before return 0, iclass 18, count 0 2006.252.07:44:31.28#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.252.07:44:31.28#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.252.07:44:31.28#ibcon#about to clear, iclass 18 cls_cnt 0 2006.252.07:44:31.28#ibcon#cleared, iclass 18 cls_cnt 0 2006.252.07:44:31.28$vc4f8/vb=3,4 2006.252.07:44:31.28#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.252.07:44:31.28#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.252.07:44:31.28#ibcon#ireg 11 cls_cnt 2 2006.252.07:44:31.28#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.252.07:44:31.34#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.252.07:44:31.34#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.252.07:44:31.34#ibcon#enter wrdev, iclass 20, count 2 2006.252.07:44:31.34#ibcon#first serial, iclass 20, count 2 2006.252.07:44:31.34#ibcon#enter sib2, iclass 20, count 2 2006.252.07:44:31.34#ibcon#flushed, iclass 20, count 2 2006.252.07:44:31.34#ibcon#about to write, iclass 20, count 2 2006.252.07:44:31.34#ibcon#wrote, iclass 20, count 2 2006.252.07:44:31.34#ibcon#about to read 3, iclass 20, count 2 2006.252.07:44:31.36#ibcon#read 3, iclass 20, count 2 2006.252.07:44:31.36#ibcon#about to read 4, iclass 20, count 2 2006.252.07:44:31.36#ibcon#read 4, iclass 20, count 2 2006.252.07:44:31.36#ibcon#about to read 5, iclass 20, count 2 2006.252.07:44:31.36#ibcon#read 5, iclass 20, count 2 2006.252.07:44:31.36#ibcon#about to read 6, iclass 20, count 2 2006.252.07:44:31.36#ibcon#read 6, iclass 20, count 2 2006.252.07:44:31.36#ibcon#end of sib2, iclass 20, count 2 2006.252.07:44:31.36#ibcon#*mode == 0, iclass 20, count 2 2006.252.07:44:31.36#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.252.07:44:31.36#ibcon#[27=AT03-04\r\n] 2006.252.07:44:31.36#ibcon#*before write, iclass 20, count 2 2006.252.07:44:31.36#ibcon#enter sib2, iclass 20, count 2 2006.252.07:44:31.36#ibcon#flushed, iclass 20, count 2 2006.252.07:44:31.36#ibcon#about to write, iclass 20, count 2 2006.252.07:44:31.36#ibcon#wrote, iclass 20, count 2 2006.252.07:44:31.36#ibcon#about to read 3, iclass 20, count 2 2006.252.07:44:31.39#ibcon#read 3, iclass 20, count 2 2006.252.07:44:31.39#ibcon#about to read 4, iclass 20, count 2 2006.252.07:44:31.39#ibcon#read 4, iclass 20, count 2 2006.252.07:44:31.39#ibcon#about to read 5, iclass 20, count 2 2006.252.07:44:31.39#ibcon#read 5, iclass 20, count 2 2006.252.07:44:31.39#ibcon#about to read 6, iclass 20, count 2 2006.252.07:44:31.39#ibcon#read 6, iclass 20, count 2 2006.252.07:44:31.39#ibcon#end of sib2, iclass 20, count 2 2006.252.07:44:31.39#ibcon#*after write, iclass 20, count 2 2006.252.07:44:31.39#ibcon#*before return 0, iclass 20, count 2 2006.252.07:44:31.39#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.252.07:44:31.39#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.252.07:44:31.39#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.252.07:44:31.39#ibcon#ireg 7 cls_cnt 0 2006.252.07:44:31.39#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.252.07:44:31.51#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.252.07:44:31.51#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.252.07:44:31.51#ibcon#enter wrdev, iclass 20, count 0 2006.252.07:44:31.51#ibcon#first serial, iclass 20, count 0 2006.252.07:44:31.51#ibcon#enter sib2, iclass 20, count 0 2006.252.07:44:31.51#ibcon#flushed, iclass 20, count 0 2006.252.07:44:31.51#ibcon#about to write, iclass 20, count 0 2006.252.07:44:31.51#ibcon#wrote, iclass 20, count 0 2006.252.07:44:31.51#ibcon#about to read 3, iclass 20, count 0 2006.252.07:44:31.53#ibcon#read 3, iclass 20, count 0 2006.252.07:44:31.53#ibcon#about to read 4, iclass 20, count 0 2006.252.07:44:31.53#ibcon#read 4, iclass 20, count 0 2006.252.07:44:31.53#ibcon#about to read 5, iclass 20, count 0 2006.252.07:44:31.53#ibcon#read 5, iclass 20, count 0 2006.252.07:44:31.53#ibcon#about to read 6, iclass 20, count 0 2006.252.07:44:31.53#ibcon#read 6, iclass 20, count 0 2006.252.07:44:31.53#ibcon#end of sib2, iclass 20, count 0 2006.252.07:44:31.53#ibcon#*mode == 0, iclass 20, count 0 2006.252.07:44:31.53#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.252.07:44:31.53#ibcon#[27=USB\r\n] 2006.252.07:44:31.53#ibcon#*before write, iclass 20, count 0 2006.252.07:44:31.53#ibcon#enter sib2, iclass 20, count 0 2006.252.07:44:31.53#ibcon#flushed, iclass 20, count 0 2006.252.07:44:31.53#ibcon#about to write, iclass 20, count 0 2006.252.07:44:31.53#ibcon#wrote, iclass 20, count 0 2006.252.07:44:31.53#ibcon#about to read 3, iclass 20, count 0 2006.252.07:44:31.56#ibcon#read 3, iclass 20, count 0 2006.252.07:44:31.56#ibcon#about to read 4, iclass 20, count 0 2006.252.07:44:31.56#ibcon#read 4, iclass 20, count 0 2006.252.07:44:31.56#ibcon#about to read 5, iclass 20, count 0 2006.252.07:44:31.56#ibcon#read 5, iclass 20, count 0 2006.252.07:44:31.56#ibcon#about to read 6, iclass 20, count 0 2006.252.07:44:31.56#ibcon#read 6, iclass 20, count 0 2006.252.07:44:31.56#ibcon#end of sib2, iclass 20, count 0 2006.252.07:44:31.56#ibcon#*after write, iclass 20, count 0 2006.252.07:44:31.56#ibcon#*before return 0, iclass 20, count 0 2006.252.07:44:31.56#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.252.07:44:31.56#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.252.07:44:31.56#ibcon#about to clear, iclass 20 cls_cnt 0 2006.252.07:44:31.56#ibcon#cleared, iclass 20 cls_cnt 0 2006.252.07:44:31.56$vc4f8/vblo=4,712.99 2006.252.07:44:31.56#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.252.07:44:31.56#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.252.07:44:31.56#ibcon#ireg 17 cls_cnt 0 2006.252.07:44:31.56#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.252.07:44:31.56#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.252.07:44:31.56#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.252.07:44:31.56#ibcon#enter wrdev, iclass 22, count 0 2006.252.07:44:31.56#ibcon#first serial, iclass 22, count 0 2006.252.07:44:31.56#ibcon#enter sib2, iclass 22, count 0 2006.252.07:44:31.56#ibcon#flushed, iclass 22, count 0 2006.252.07:44:31.56#ibcon#about to write, iclass 22, count 0 2006.252.07:44:31.56#ibcon#wrote, iclass 22, count 0 2006.252.07:44:31.56#ibcon#about to read 3, iclass 22, count 0 2006.252.07:44:31.58#ibcon#read 3, iclass 22, count 0 2006.252.07:44:31.58#ibcon#about to read 4, iclass 22, count 0 2006.252.07:44:31.58#ibcon#read 4, iclass 22, count 0 2006.252.07:44:31.58#ibcon#about to read 5, iclass 22, count 0 2006.252.07:44:31.58#ibcon#read 5, iclass 22, count 0 2006.252.07:44:31.58#ibcon#about to read 6, iclass 22, count 0 2006.252.07:44:31.58#ibcon#read 6, iclass 22, count 0 2006.252.07:44:31.58#ibcon#end of sib2, iclass 22, count 0 2006.252.07:44:31.58#ibcon#*mode == 0, iclass 22, count 0 2006.252.07:44:31.58#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.252.07:44:31.58#ibcon#[28=FRQ=04,712.99\r\n] 2006.252.07:44:31.58#ibcon#*before write, iclass 22, count 0 2006.252.07:44:31.58#ibcon#enter sib2, iclass 22, count 0 2006.252.07:44:31.58#ibcon#flushed, iclass 22, count 0 2006.252.07:44:31.58#ibcon#about to write, iclass 22, count 0 2006.252.07:44:31.58#ibcon#wrote, iclass 22, count 0 2006.252.07:44:31.58#ibcon#about to read 3, iclass 22, count 0 2006.252.07:44:31.62#ibcon#read 3, iclass 22, count 0 2006.252.07:44:31.62#ibcon#about to read 4, iclass 22, count 0 2006.252.07:44:31.62#ibcon#read 4, iclass 22, count 0 2006.252.07:44:31.62#ibcon#about to read 5, iclass 22, count 0 2006.252.07:44:31.62#ibcon#read 5, iclass 22, count 0 2006.252.07:44:31.62#ibcon#about to read 6, iclass 22, count 0 2006.252.07:44:31.62#ibcon#read 6, iclass 22, count 0 2006.252.07:44:31.62#ibcon#end of sib2, iclass 22, count 0 2006.252.07:44:31.62#ibcon#*after write, iclass 22, count 0 2006.252.07:44:31.62#ibcon#*before return 0, iclass 22, count 0 2006.252.07:44:31.62#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.252.07:44:31.62#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.252.07:44:31.62#ibcon#about to clear, iclass 22 cls_cnt 0 2006.252.07:44:31.62#ibcon#cleared, iclass 22 cls_cnt 0 2006.252.07:44:31.62$vc4f8/vb=4,4 2006.252.07:44:31.62#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.252.07:44:31.62#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.252.07:44:31.62#ibcon#ireg 11 cls_cnt 2 2006.252.07:44:31.62#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.252.07:44:31.68#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.252.07:44:31.68#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.252.07:44:31.68#ibcon#enter wrdev, iclass 24, count 2 2006.252.07:44:31.68#ibcon#first serial, iclass 24, count 2 2006.252.07:44:31.68#ibcon#enter sib2, iclass 24, count 2 2006.252.07:44:31.68#ibcon#flushed, iclass 24, count 2 2006.252.07:44:31.68#ibcon#about to write, iclass 24, count 2 2006.252.07:44:31.68#ibcon#wrote, iclass 24, count 2 2006.252.07:44:31.68#ibcon#about to read 3, iclass 24, count 2 2006.252.07:44:31.70#ibcon#read 3, iclass 24, count 2 2006.252.07:44:31.70#ibcon#about to read 4, iclass 24, count 2 2006.252.07:44:31.70#ibcon#read 4, iclass 24, count 2 2006.252.07:44:31.70#ibcon#about to read 5, iclass 24, count 2 2006.252.07:44:31.70#ibcon#read 5, iclass 24, count 2 2006.252.07:44:31.70#ibcon#about to read 6, iclass 24, count 2 2006.252.07:44:31.70#ibcon#read 6, iclass 24, count 2 2006.252.07:44:31.70#ibcon#end of sib2, iclass 24, count 2 2006.252.07:44:31.70#ibcon#*mode == 0, iclass 24, count 2 2006.252.07:44:31.70#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.252.07:44:31.70#ibcon#[27=AT04-04\r\n] 2006.252.07:44:31.70#ibcon#*before write, iclass 24, count 2 2006.252.07:44:31.70#ibcon#enter sib2, iclass 24, count 2 2006.252.07:44:31.70#ibcon#flushed, iclass 24, count 2 2006.252.07:44:31.70#ibcon#about to write, iclass 24, count 2 2006.252.07:44:31.70#ibcon#wrote, iclass 24, count 2 2006.252.07:44:31.70#ibcon#about to read 3, iclass 24, count 2 2006.252.07:44:31.73#ibcon#read 3, iclass 24, count 2 2006.252.07:44:31.73#ibcon#about to read 4, iclass 24, count 2 2006.252.07:44:31.73#ibcon#read 4, iclass 24, count 2 2006.252.07:44:31.73#ibcon#about to read 5, iclass 24, count 2 2006.252.07:44:31.73#ibcon#read 5, iclass 24, count 2 2006.252.07:44:31.73#ibcon#about to read 6, iclass 24, count 2 2006.252.07:44:31.73#ibcon#read 6, iclass 24, count 2 2006.252.07:44:31.73#ibcon#end of sib2, iclass 24, count 2 2006.252.07:44:31.73#ibcon#*after write, iclass 24, count 2 2006.252.07:44:31.73#ibcon#*before return 0, iclass 24, count 2 2006.252.07:44:31.73#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.252.07:44:31.73#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.252.07:44:31.73#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.252.07:44:31.73#ibcon#ireg 7 cls_cnt 0 2006.252.07:44:31.73#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.252.07:44:31.85#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.252.07:44:31.85#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.252.07:44:31.85#ibcon#enter wrdev, iclass 24, count 0 2006.252.07:44:31.85#ibcon#first serial, iclass 24, count 0 2006.252.07:44:31.85#ibcon#enter sib2, iclass 24, count 0 2006.252.07:44:31.85#ibcon#flushed, iclass 24, count 0 2006.252.07:44:31.85#ibcon#about to write, iclass 24, count 0 2006.252.07:44:31.85#ibcon#wrote, iclass 24, count 0 2006.252.07:44:31.85#ibcon#about to read 3, iclass 24, count 0 2006.252.07:44:31.87#ibcon#read 3, iclass 24, count 0 2006.252.07:44:31.87#ibcon#about to read 4, iclass 24, count 0 2006.252.07:44:31.87#ibcon#read 4, iclass 24, count 0 2006.252.07:44:31.87#ibcon#about to read 5, iclass 24, count 0 2006.252.07:44:31.87#ibcon#read 5, iclass 24, count 0 2006.252.07:44:31.87#ibcon#about to read 6, iclass 24, count 0 2006.252.07:44:31.87#ibcon#read 6, iclass 24, count 0 2006.252.07:44:31.87#ibcon#end of sib2, iclass 24, count 0 2006.252.07:44:31.87#ibcon#*mode == 0, iclass 24, count 0 2006.252.07:44:31.87#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.252.07:44:31.87#ibcon#[27=USB\r\n] 2006.252.07:44:31.87#ibcon#*before write, iclass 24, count 0 2006.252.07:44:31.87#ibcon#enter sib2, iclass 24, count 0 2006.252.07:44:31.87#ibcon#flushed, iclass 24, count 0 2006.252.07:44:31.87#ibcon#about to write, iclass 24, count 0 2006.252.07:44:31.87#ibcon#wrote, iclass 24, count 0 2006.252.07:44:31.87#ibcon#about to read 3, iclass 24, count 0 2006.252.07:44:31.90#ibcon#read 3, iclass 24, count 0 2006.252.07:44:31.90#ibcon#about to read 4, iclass 24, count 0 2006.252.07:44:31.90#ibcon#read 4, iclass 24, count 0 2006.252.07:44:31.90#ibcon#about to read 5, iclass 24, count 0 2006.252.07:44:31.90#ibcon#read 5, iclass 24, count 0 2006.252.07:44:31.90#ibcon#about to read 6, iclass 24, count 0 2006.252.07:44:31.90#ibcon#read 6, iclass 24, count 0 2006.252.07:44:31.90#ibcon#end of sib2, iclass 24, count 0 2006.252.07:44:31.90#ibcon#*after write, iclass 24, count 0 2006.252.07:44:31.90#ibcon#*before return 0, iclass 24, count 0 2006.252.07:44:31.90#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.252.07:44:31.90#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.252.07:44:31.90#ibcon#about to clear, iclass 24 cls_cnt 0 2006.252.07:44:31.90#ibcon#cleared, iclass 24 cls_cnt 0 2006.252.07:44:31.90$vc4f8/vblo=5,744.99 2006.252.07:44:31.90#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.252.07:44:31.90#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.252.07:44:31.90#ibcon#ireg 17 cls_cnt 0 2006.252.07:44:31.90#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.252.07:44:31.90#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.252.07:44:31.90#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.252.07:44:31.90#ibcon#enter wrdev, iclass 26, count 0 2006.252.07:44:31.90#ibcon#first serial, iclass 26, count 0 2006.252.07:44:31.90#ibcon#enter sib2, iclass 26, count 0 2006.252.07:44:31.90#ibcon#flushed, iclass 26, count 0 2006.252.07:44:31.90#ibcon#about to write, iclass 26, count 0 2006.252.07:44:31.90#ibcon#wrote, iclass 26, count 0 2006.252.07:44:31.90#ibcon#about to read 3, iclass 26, count 0 2006.252.07:44:31.92#ibcon#read 3, iclass 26, count 0 2006.252.07:44:31.92#ibcon#about to read 4, iclass 26, count 0 2006.252.07:44:31.92#ibcon#read 4, iclass 26, count 0 2006.252.07:44:31.92#ibcon#about to read 5, iclass 26, count 0 2006.252.07:44:31.92#ibcon#read 5, iclass 26, count 0 2006.252.07:44:31.92#ibcon#about to read 6, iclass 26, count 0 2006.252.07:44:31.92#ibcon#read 6, iclass 26, count 0 2006.252.07:44:31.92#ibcon#end of sib2, iclass 26, count 0 2006.252.07:44:31.92#ibcon#*mode == 0, iclass 26, count 0 2006.252.07:44:31.92#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.252.07:44:31.92#ibcon#[28=FRQ=05,744.99\r\n] 2006.252.07:44:31.92#ibcon#*before write, iclass 26, count 0 2006.252.07:44:31.92#ibcon#enter sib2, iclass 26, count 0 2006.252.07:44:31.92#ibcon#flushed, iclass 26, count 0 2006.252.07:44:31.92#ibcon#about to write, iclass 26, count 0 2006.252.07:44:31.92#ibcon#wrote, iclass 26, count 0 2006.252.07:44:31.92#ibcon#about to read 3, iclass 26, count 0 2006.252.07:44:31.96#ibcon#read 3, iclass 26, count 0 2006.252.07:44:31.96#ibcon#about to read 4, iclass 26, count 0 2006.252.07:44:31.96#ibcon#read 4, iclass 26, count 0 2006.252.07:44:31.96#ibcon#about to read 5, iclass 26, count 0 2006.252.07:44:31.96#ibcon#read 5, iclass 26, count 0 2006.252.07:44:31.96#ibcon#about to read 6, iclass 26, count 0 2006.252.07:44:31.96#ibcon#read 6, iclass 26, count 0 2006.252.07:44:31.96#ibcon#end of sib2, iclass 26, count 0 2006.252.07:44:31.96#ibcon#*after write, iclass 26, count 0 2006.252.07:44:31.96#ibcon#*before return 0, iclass 26, count 0 2006.252.07:44:31.96#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.252.07:44:31.96#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.252.07:44:31.96#ibcon#about to clear, iclass 26 cls_cnt 0 2006.252.07:44:31.96#ibcon#cleared, iclass 26 cls_cnt 0 2006.252.07:44:31.96$vc4f8/vb=5,4 2006.252.07:44:31.96#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.252.07:44:31.96#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.252.07:44:31.96#ibcon#ireg 11 cls_cnt 2 2006.252.07:44:31.96#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.252.07:44:32.02#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.252.07:44:32.02#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.252.07:44:32.02#ibcon#enter wrdev, iclass 28, count 2 2006.252.07:44:32.02#ibcon#first serial, iclass 28, count 2 2006.252.07:44:32.02#ibcon#enter sib2, iclass 28, count 2 2006.252.07:44:32.02#ibcon#flushed, iclass 28, count 2 2006.252.07:44:32.02#ibcon#about to write, iclass 28, count 2 2006.252.07:44:32.02#ibcon#wrote, iclass 28, count 2 2006.252.07:44:32.02#ibcon#about to read 3, iclass 28, count 2 2006.252.07:44:32.04#ibcon#read 3, iclass 28, count 2 2006.252.07:44:32.04#ibcon#about to read 4, iclass 28, count 2 2006.252.07:44:32.04#ibcon#read 4, iclass 28, count 2 2006.252.07:44:32.04#ibcon#about to read 5, iclass 28, count 2 2006.252.07:44:32.04#ibcon#read 5, iclass 28, count 2 2006.252.07:44:32.04#ibcon#about to read 6, iclass 28, count 2 2006.252.07:44:32.04#ibcon#read 6, iclass 28, count 2 2006.252.07:44:32.04#ibcon#end of sib2, iclass 28, count 2 2006.252.07:44:32.04#ibcon#*mode == 0, iclass 28, count 2 2006.252.07:44:32.04#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.252.07:44:32.04#ibcon#[27=AT05-04\r\n] 2006.252.07:44:32.04#ibcon#*before write, iclass 28, count 2 2006.252.07:44:32.04#ibcon#enter sib2, iclass 28, count 2 2006.252.07:44:32.04#ibcon#flushed, iclass 28, count 2 2006.252.07:44:32.04#ibcon#about to write, iclass 28, count 2 2006.252.07:44:32.04#ibcon#wrote, iclass 28, count 2 2006.252.07:44:32.04#ibcon#about to read 3, iclass 28, count 2 2006.252.07:44:32.07#ibcon#read 3, iclass 28, count 2 2006.252.07:44:32.07#ibcon#about to read 4, iclass 28, count 2 2006.252.07:44:32.07#ibcon#read 4, iclass 28, count 2 2006.252.07:44:32.07#ibcon#about to read 5, iclass 28, count 2 2006.252.07:44:32.07#ibcon#read 5, iclass 28, count 2 2006.252.07:44:32.07#ibcon#about to read 6, iclass 28, count 2 2006.252.07:44:32.07#ibcon#read 6, iclass 28, count 2 2006.252.07:44:32.07#ibcon#end of sib2, iclass 28, count 2 2006.252.07:44:32.07#ibcon#*after write, iclass 28, count 2 2006.252.07:44:32.07#ibcon#*before return 0, iclass 28, count 2 2006.252.07:44:32.07#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.252.07:44:32.07#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.252.07:44:32.07#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.252.07:44:32.07#ibcon#ireg 7 cls_cnt 0 2006.252.07:44:32.07#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.252.07:44:32.19#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.252.07:44:32.19#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.252.07:44:32.19#ibcon#enter wrdev, iclass 28, count 0 2006.252.07:44:32.19#ibcon#first serial, iclass 28, count 0 2006.252.07:44:32.19#ibcon#enter sib2, iclass 28, count 0 2006.252.07:44:32.19#ibcon#flushed, iclass 28, count 0 2006.252.07:44:32.19#ibcon#about to write, iclass 28, count 0 2006.252.07:44:32.19#ibcon#wrote, iclass 28, count 0 2006.252.07:44:32.19#ibcon#about to read 3, iclass 28, count 0 2006.252.07:44:32.21#ibcon#read 3, iclass 28, count 0 2006.252.07:44:32.21#ibcon#about to read 4, iclass 28, count 0 2006.252.07:44:32.21#ibcon#read 4, iclass 28, count 0 2006.252.07:44:32.21#ibcon#about to read 5, iclass 28, count 0 2006.252.07:44:32.21#ibcon#read 5, iclass 28, count 0 2006.252.07:44:32.21#ibcon#about to read 6, iclass 28, count 0 2006.252.07:44:32.21#ibcon#read 6, iclass 28, count 0 2006.252.07:44:32.21#ibcon#end of sib2, iclass 28, count 0 2006.252.07:44:32.21#ibcon#*mode == 0, iclass 28, count 0 2006.252.07:44:32.21#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.252.07:44:32.21#ibcon#[27=USB\r\n] 2006.252.07:44:32.21#ibcon#*before write, iclass 28, count 0 2006.252.07:44:32.21#ibcon#enter sib2, iclass 28, count 0 2006.252.07:44:32.21#ibcon#flushed, iclass 28, count 0 2006.252.07:44:32.21#ibcon#about to write, iclass 28, count 0 2006.252.07:44:32.21#ibcon#wrote, iclass 28, count 0 2006.252.07:44:32.21#ibcon#about to read 3, iclass 28, count 0 2006.252.07:44:32.24#ibcon#read 3, iclass 28, count 0 2006.252.07:44:32.24#ibcon#about to read 4, iclass 28, count 0 2006.252.07:44:32.24#ibcon#read 4, iclass 28, count 0 2006.252.07:44:32.24#ibcon#about to read 5, iclass 28, count 0 2006.252.07:44:32.24#ibcon#read 5, iclass 28, count 0 2006.252.07:44:32.24#ibcon#about to read 6, iclass 28, count 0 2006.252.07:44:32.24#ibcon#read 6, iclass 28, count 0 2006.252.07:44:32.24#ibcon#end of sib2, iclass 28, count 0 2006.252.07:44:32.24#ibcon#*after write, iclass 28, count 0 2006.252.07:44:32.24#ibcon#*before return 0, iclass 28, count 0 2006.252.07:44:32.24#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.252.07:44:32.24#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.252.07:44:32.24#ibcon#about to clear, iclass 28 cls_cnt 0 2006.252.07:44:32.24#ibcon#cleared, iclass 28 cls_cnt 0 2006.252.07:44:32.24$vc4f8/vblo=6,752.99 2006.252.07:44:32.24#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.252.07:44:32.24#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.252.07:44:32.24#ibcon#ireg 17 cls_cnt 0 2006.252.07:44:32.24#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.252.07:44:32.24#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.252.07:44:32.24#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.252.07:44:32.24#ibcon#enter wrdev, iclass 30, count 0 2006.252.07:44:32.24#ibcon#first serial, iclass 30, count 0 2006.252.07:44:32.24#ibcon#enter sib2, iclass 30, count 0 2006.252.07:44:32.24#ibcon#flushed, iclass 30, count 0 2006.252.07:44:32.24#ibcon#about to write, iclass 30, count 0 2006.252.07:44:32.24#ibcon#wrote, iclass 30, count 0 2006.252.07:44:32.24#ibcon#about to read 3, iclass 30, count 0 2006.252.07:44:32.26#ibcon#read 3, iclass 30, count 0 2006.252.07:44:32.26#ibcon#about to read 4, iclass 30, count 0 2006.252.07:44:32.26#ibcon#read 4, iclass 30, count 0 2006.252.07:44:32.26#ibcon#about to read 5, iclass 30, count 0 2006.252.07:44:32.26#ibcon#read 5, iclass 30, count 0 2006.252.07:44:32.26#ibcon#about to read 6, iclass 30, count 0 2006.252.07:44:32.26#ibcon#read 6, iclass 30, count 0 2006.252.07:44:32.26#ibcon#end of sib2, iclass 30, count 0 2006.252.07:44:32.26#ibcon#*mode == 0, iclass 30, count 0 2006.252.07:44:32.26#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.252.07:44:32.26#ibcon#[28=FRQ=06,752.99\r\n] 2006.252.07:44:32.26#ibcon#*before write, iclass 30, count 0 2006.252.07:44:32.26#ibcon#enter sib2, iclass 30, count 0 2006.252.07:44:32.26#ibcon#flushed, iclass 30, count 0 2006.252.07:44:32.26#ibcon#about to write, iclass 30, count 0 2006.252.07:44:32.26#ibcon#wrote, iclass 30, count 0 2006.252.07:44:32.26#ibcon#about to read 3, iclass 30, count 0 2006.252.07:44:32.30#ibcon#read 3, iclass 30, count 0 2006.252.07:44:32.30#ibcon#about to read 4, iclass 30, count 0 2006.252.07:44:32.30#ibcon#read 4, iclass 30, count 0 2006.252.07:44:32.30#ibcon#about to read 5, iclass 30, count 0 2006.252.07:44:32.30#ibcon#read 5, iclass 30, count 0 2006.252.07:44:32.30#ibcon#about to read 6, iclass 30, count 0 2006.252.07:44:32.30#ibcon#read 6, iclass 30, count 0 2006.252.07:44:32.30#ibcon#end of sib2, iclass 30, count 0 2006.252.07:44:32.30#ibcon#*after write, iclass 30, count 0 2006.252.07:44:32.30#ibcon#*before return 0, iclass 30, count 0 2006.252.07:44:32.30#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.252.07:44:32.30#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.252.07:44:32.30#ibcon#about to clear, iclass 30 cls_cnt 0 2006.252.07:44:32.30#ibcon#cleared, iclass 30 cls_cnt 0 2006.252.07:44:32.30$vc4f8/vb=6,4 2006.252.07:44:32.30#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.252.07:44:32.30#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.252.07:44:32.30#ibcon#ireg 11 cls_cnt 2 2006.252.07:44:32.30#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.252.07:44:32.36#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.252.07:44:32.36#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.252.07:44:32.36#ibcon#enter wrdev, iclass 32, count 2 2006.252.07:44:32.36#ibcon#first serial, iclass 32, count 2 2006.252.07:44:32.36#ibcon#enter sib2, iclass 32, count 2 2006.252.07:44:32.36#ibcon#flushed, iclass 32, count 2 2006.252.07:44:32.36#ibcon#about to write, iclass 32, count 2 2006.252.07:44:32.36#ibcon#wrote, iclass 32, count 2 2006.252.07:44:32.36#ibcon#about to read 3, iclass 32, count 2 2006.252.07:44:32.38#ibcon#read 3, iclass 32, count 2 2006.252.07:44:32.38#ibcon#about to read 4, iclass 32, count 2 2006.252.07:44:32.38#ibcon#read 4, iclass 32, count 2 2006.252.07:44:32.38#ibcon#about to read 5, iclass 32, count 2 2006.252.07:44:32.38#ibcon#read 5, iclass 32, count 2 2006.252.07:44:32.38#ibcon#about to read 6, iclass 32, count 2 2006.252.07:44:32.38#ibcon#read 6, iclass 32, count 2 2006.252.07:44:32.38#ibcon#end of sib2, iclass 32, count 2 2006.252.07:44:32.38#ibcon#*mode == 0, iclass 32, count 2 2006.252.07:44:32.38#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.252.07:44:32.38#ibcon#[27=AT06-04\r\n] 2006.252.07:44:32.38#ibcon#*before write, iclass 32, count 2 2006.252.07:44:32.38#ibcon#enter sib2, iclass 32, count 2 2006.252.07:44:32.38#ibcon#flushed, iclass 32, count 2 2006.252.07:44:32.38#ibcon#about to write, iclass 32, count 2 2006.252.07:44:32.38#ibcon#wrote, iclass 32, count 2 2006.252.07:44:32.38#ibcon#about to read 3, iclass 32, count 2 2006.252.07:44:32.41#ibcon#read 3, iclass 32, count 2 2006.252.07:44:32.41#ibcon#about to read 4, iclass 32, count 2 2006.252.07:44:32.41#ibcon#read 4, iclass 32, count 2 2006.252.07:44:32.41#ibcon#about to read 5, iclass 32, count 2 2006.252.07:44:32.41#ibcon#read 5, iclass 32, count 2 2006.252.07:44:32.41#ibcon#about to read 6, iclass 32, count 2 2006.252.07:44:32.41#ibcon#read 6, iclass 32, count 2 2006.252.07:44:32.41#ibcon#end of sib2, iclass 32, count 2 2006.252.07:44:32.41#ibcon#*after write, iclass 32, count 2 2006.252.07:44:32.41#ibcon#*before return 0, iclass 32, count 2 2006.252.07:44:32.41#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.252.07:44:32.41#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.252.07:44:32.41#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.252.07:44:32.41#ibcon#ireg 7 cls_cnt 0 2006.252.07:44:32.41#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.252.07:44:32.53#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.252.07:44:32.53#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.252.07:44:32.53#ibcon#enter wrdev, iclass 32, count 0 2006.252.07:44:32.53#ibcon#first serial, iclass 32, count 0 2006.252.07:44:32.53#ibcon#enter sib2, iclass 32, count 0 2006.252.07:44:32.53#ibcon#flushed, iclass 32, count 0 2006.252.07:44:32.53#ibcon#about to write, iclass 32, count 0 2006.252.07:44:32.53#ibcon#wrote, iclass 32, count 0 2006.252.07:44:32.53#ibcon#about to read 3, iclass 32, count 0 2006.252.07:44:32.55#ibcon#read 3, iclass 32, count 0 2006.252.07:44:32.55#ibcon#about to read 4, iclass 32, count 0 2006.252.07:44:32.55#ibcon#read 4, iclass 32, count 0 2006.252.07:44:32.55#ibcon#about to read 5, iclass 32, count 0 2006.252.07:44:32.55#ibcon#read 5, iclass 32, count 0 2006.252.07:44:32.55#ibcon#about to read 6, iclass 32, count 0 2006.252.07:44:32.55#ibcon#read 6, iclass 32, count 0 2006.252.07:44:32.55#ibcon#end of sib2, iclass 32, count 0 2006.252.07:44:32.55#ibcon#*mode == 0, iclass 32, count 0 2006.252.07:44:32.55#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.252.07:44:32.55#ibcon#[27=USB\r\n] 2006.252.07:44:32.55#ibcon#*before write, iclass 32, count 0 2006.252.07:44:32.55#ibcon#enter sib2, iclass 32, count 0 2006.252.07:44:32.55#ibcon#flushed, iclass 32, count 0 2006.252.07:44:32.55#ibcon#about to write, iclass 32, count 0 2006.252.07:44:32.55#ibcon#wrote, iclass 32, count 0 2006.252.07:44:32.55#ibcon#about to read 3, iclass 32, count 0 2006.252.07:44:32.58#ibcon#read 3, iclass 32, count 0 2006.252.07:44:32.58#ibcon#about to read 4, iclass 32, count 0 2006.252.07:44:32.58#ibcon#read 4, iclass 32, count 0 2006.252.07:44:32.58#ibcon#about to read 5, iclass 32, count 0 2006.252.07:44:32.58#ibcon#read 5, iclass 32, count 0 2006.252.07:44:32.58#ibcon#about to read 6, iclass 32, count 0 2006.252.07:44:32.58#ibcon#read 6, iclass 32, count 0 2006.252.07:44:32.58#ibcon#end of sib2, iclass 32, count 0 2006.252.07:44:32.58#ibcon#*after write, iclass 32, count 0 2006.252.07:44:32.58#ibcon#*before return 0, iclass 32, count 0 2006.252.07:44:32.58#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.252.07:44:32.58#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.252.07:44:32.58#ibcon#about to clear, iclass 32 cls_cnt 0 2006.252.07:44:32.58#ibcon#cleared, iclass 32 cls_cnt 0 2006.252.07:44:32.58$vc4f8/vabw=wide 2006.252.07:44:32.58#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.252.07:44:32.58#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.252.07:44:32.58#ibcon#ireg 8 cls_cnt 0 2006.252.07:44:32.58#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.252.07:44:32.58#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.252.07:44:32.58#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.252.07:44:32.58#ibcon#enter wrdev, iclass 34, count 0 2006.252.07:44:32.58#ibcon#first serial, iclass 34, count 0 2006.252.07:44:32.58#ibcon#enter sib2, iclass 34, count 0 2006.252.07:44:32.58#ibcon#flushed, iclass 34, count 0 2006.252.07:44:32.58#ibcon#about to write, iclass 34, count 0 2006.252.07:44:32.58#ibcon#wrote, iclass 34, count 0 2006.252.07:44:32.58#ibcon#about to read 3, iclass 34, count 0 2006.252.07:44:32.61#ibcon#read 3, iclass 34, count 0 2006.252.07:44:32.61#ibcon#about to read 4, iclass 34, count 0 2006.252.07:44:32.61#ibcon#read 4, iclass 34, count 0 2006.252.07:44:32.61#ibcon#about to read 5, iclass 34, count 0 2006.252.07:44:32.61#ibcon#read 5, iclass 34, count 0 2006.252.07:44:32.61#ibcon#about to read 6, iclass 34, count 0 2006.252.07:44:32.61#ibcon#read 6, iclass 34, count 0 2006.252.07:44:32.61#ibcon#end of sib2, iclass 34, count 0 2006.252.07:44:32.61#ibcon#*mode == 0, iclass 34, count 0 2006.252.07:44:32.61#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.252.07:44:32.61#ibcon#[25=BW32\r\n] 2006.252.07:44:32.61#ibcon#*before write, iclass 34, count 0 2006.252.07:44:32.61#ibcon#enter sib2, iclass 34, count 0 2006.252.07:44:32.61#ibcon#flushed, iclass 34, count 0 2006.252.07:44:32.61#ibcon#about to write, iclass 34, count 0 2006.252.07:44:32.61#ibcon#wrote, iclass 34, count 0 2006.252.07:44:32.61#ibcon#about to read 3, iclass 34, count 0 2006.252.07:44:32.64#ibcon#read 3, iclass 34, count 0 2006.252.07:44:32.64#ibcon#about to read 4, iclass 34, count 0 2006.252.07:44:32.64#ibcon#read 4, iclass 34, count 0 2006.252.07:44:32.64#ibcon#about to read 5, iclass 34, count 0 2006.252.07:44:32.64#ibcon#read 5, iclass 34, count 0 2006.252.07:44:32.64#ibcon#about to read 6, iclass 34, count 0 2006.252.07:44:32.64#ibcon#read 6, iclass 34, count 0 2006.252.07:44:32.64#ibcon#end of sib2, iclass 34, count 0 2006.252.07:44:32.64#ibcon#*after write, iclass 34, count 0 2006.252.07:44:32.64#ibcon#*before return 0, iclass 34, count 0 2006.252.07:44:32.64#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.252.07:44:32.64#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.252.07:44:32.64#ibcon#about to clear, iclass 34 cls_cnt 0 2006.252.07:44:32.64#ibcon#cleared, iclass 34 cls_cnt 0 2006.252.07:44:32.64$vc4f8/vbbw=wide 2006.252.07:44:32.64#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.252.07:44:32.64#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.252.07:44:32.64#ibcon#ireg 8 cls_cnt 0 2006.252.07:44:32.64#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.252.07:44:32.70#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.252.07:44:32.70#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.252.07:44:32.70#ibcon#enter wrdev, iclass 36, count 0 2006.252.07:44:32.70#ibcon#first serial, iclass 36, count 0 2006.252.07:44:32.70#ibcon#enter sib2, iclass 36, count 0 2006.252.07:44:32.70#ibcon#flushed, iclass 36, count 0 2006.252.07:44:32.70#ibcon#about to write, iclass 36, count 0 2006.252.07:44:32.70#ibcon#wrote, iclass 36, count 0 2006.252.07:44:32.70#ibcon#about to read 3, iclass 36, count 0 2006.252.07:44:32.72#ibcon#read 3, iclass 36, count 0 2006.252.07:44:32.72#ibcon#about to read 4, iclass 36, count 0 2006.252.07:44:32.72#ibcon#read 4, iclass 36, count 0 2006.252.07:44:32.72#ibcon#about to read 5, iclass 36, count 0 2006.252.07:44:32.72#ibcon#read 5, iclass 36, count 0 2006.252.07:44:32.72#ibcon#about to read 6, iclass 36, count 0 2006.252.07:44:32.72#ibcon#read 6, iclass 36, count 0 2006.252.07:44:32.72#ibcon#end of sib2, iclass 36, count 0 2006.252.07:44:32.72#ibcon#*mode == 0, iclass 36, count 0 2006.252.07:44:32.72#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.252.07:44:32.72#ibcon#[27=BW32\r\n] 2006.252.07:44:32.72#ibcon#*before write, iclass 36, count 0 2006.252.07:44:32.72#ibcon#enter sib2, iclass 36, count 0 2006.252.07:44:32.72#ibcon#flushed, iclass 36, count 0 2006.252.07:44:32.72#ibcon#about to write, iclass 36, count 0 2006.252.07:44:32.72#ibcon#wrote, iclass 36, count 0 2006.252.07:44:32.72#ibcon#about to read 3, iclass 36, count 0 2006.252.07:44:32.75#ibcon#read 3, iclass 36, count 0 2006.252.07:44:32.75#ibcon#about to read 4, iclass 36, count 0 2006.252.07:44:32.75#ibcon#read 4, iclass 36, count 0 2006.252.07:44:32.75#ibcon#about to read 5, iclass 36, count 0 2006.252.07:44:32.75#ibcon#read 5, iclass 36, count 0 2006.252.07:44:32.75#ibcon#about to read 6, iclass 36, count 0 2006.252.07:44:32.75#ibcon#read 6, iclass 36, count 0 2006.252.07:44:32.75#ibcon#end of sib2, iclass 36, count 0 2006.252.07:44:32.75#ibcon#*after write, iclass 36, count 0 2006.252.07:44:32.75#ibcon#*before return 0, iclass 36, count 0 2006.252.07:44:32.75#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.252.07:44:32.75#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.252.07:44:32.75#ibcon#about to clear, iclass 36 cls_cnt 0 2006.252.07:44:32.75#ibcon#cleared, iclass 36 cls_cnt 0 2006.252.07:44:32.75$4f8m12a/ifd4f 2006.252.07:44:32.75$ifd4f/lo= 2006.252.07:44:32.75$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.252.07:44:32.75$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.252.07:44:32.75$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.252.07:44:32.75$ifd4f/patch= 2006.252.07:44:32.75$ifd4f/patch=lo1,a1,a2,a3,a4 2006.252.07:44:32.75$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.252.07:44:32.75$ifd4f/patch=lo3,a5,a6,a7,a8 2006.252.07:44:32.75$4f8m12a/"form=m,16.000,1:2 2006.252.07:44:32.75$4f8m12a/"tpicd 2006.252.07:44:32.76$4f8m12a/echo=off 2006.252.07:44:32.76$4f8m12a/xlog=off 2006.252.07:44:32.76:!2006.252.07:45:00 2006.252.07:44:45.13#trakl#Source acquired 2006.252.07:44:45.13#flagr#flagr/antenna,acquired 2006.252.07:45:00.01:preob 2006.252.07:45:01.13/onsource/TRACKING 2006.252.07:45:01.13:!2006.252.07:45:10 2006.252.07:45:10.00:data_valid=on 2006.252.07:45:10.00:midob 2006.252.07:45:10.13/onsource/TRACKING 2006.252.07:45:10.13/wx/27.39,1011.2,90 2006.252.07:45:10.35/cable/+6.4102E-03 2006.252.07:45:11.44/va/01,08,usb,yes,33,35 2006.252.07:45:11.44/va/02,07,usb,yes,33,35 2006.252.07:45:11.44/va/03,06,usb,yes,35,36 2006.252.07:45:11.44/va/04,07,usb,yes,34,37 2006.252.07:45:11.44/va/05,07,usb,yes,37,39 2006.252.07:45:11.44/va/06,07,usb,yes,32,32 2006.252.07:45:11.44/va/07,07,usb,yes,32,32 2006.252.07:45:11.44/va/08,07,usb,yes,35,34 2006.252.07:45:11.67/valo/01,532.99,yes,locked 2006.252.07:45:11.67/valo/02,572.99,yes,locked 2006.252.07:45:11.67/valo/03,672.99,yes,locked 2006.252.07:45:11.67/valo/04,832.99,yes,locked 2006.252.07:45:11.67/valo/05,652.99,yes,locked 2006.252.07:45:11.67/valo/06,772.99,yes,locked 2006.252.07:45:11.67/valo/07,832.99,yes,locked 2006.252.07:45:11.67/valo/08,852.99,yes,locked 2006.252.07:45:12.76/vb/01,04,usb,yes,31,29 2006.252.07:45:12.76/vb/02,05,usb,yes,29,30 2006.252.07:45:12.76/vb/03,04,usb,yes,29,33 2006.252.07:45:12.76/vb/04,04,usb,yes,30,30 2006.252.07:45:12.76/vb/05,04,usb,yes,28,32 2006.252.07:45:12.76/vb/06,04,usb,yes,29,32 2006.252.07:45:12.76/vb/07,04,usb,yes,31,31 2006.252.07:45:12.76/vb/08,04,usb,yes,29,32 2006.252.07:45:12.99/vblo/01,632.99,yes,locked 2006.252.07:45:12.99/vblo/02,640.99,yes,locked 2006.252.07:45:12.99/vblo/03,656.99,yes,locked 2006.252.07:45:12.99/vblo/04,712.99,yes,locked 2006.252.07:45:12.99/vblo/05,744.99,yes,locked 2006.252.07:45:12.99/vblo/06,752.99,yes,locked 2006.252.07:45:12.99/vblo/07,734.99,yes,locked 2006.252.07:45:12.99/vblo/08,744.99,yes,locked 2006.252.07:45:13.14/vabw/8 2006.252.07:45:13.29/vbbw/8 2006.252.07:45:13.40/xfe/off,on,14.2 2006.252.07:45:13.78/ifatt/23,28,28,28 2006.252.07:45:14.08/fmout-gps/S +4.80E-07 2006.252.07:45:14.12:!2006.252.07:46:10 2006.252.07:46:10.01:data_valid=off 2006.252.07:46:10.02:postob 2006.252.07:46:10.19/cable/+6.4077E-03 2006.252.07:46:10.20/wx/27.39,1011.2,90 2006.252.07:46:11.07/fmout-gps/S +4.81E-07 2006.252.07:46:11.08:scan_name=252-0747,k06252,60 2006.252.07:46:11.08:source=3c371,180650.68,694928.1,2000.0,cw 2006.252.07:46:11.13#flagr#flagr/antenna,new-source 2006.252.07:46:12.14:checkk5 2006.252.07:46:12.52/chk_autoobs//k5ts1/ autoobs is running! 2006.252.07:46:12.89/chk_autoobs//k5ts2/ autoobs is running! 2006.252.07:46:13.27/chk_autoobs//k5ts3/ autoobs is running! 2006.252.07:46:13.65/chk_autoobs//k5ts4/ autoobs is running! 2006.252.07:46:14.01/chk_obsdata//k5ts1/T2520745??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.252.07:46:14.39/chk_obsdata//k5ts2/T2520745??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.252.07:46:14.76/chk_obsdata//k5ts3/T2520745??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.252.07:46:15.14/chk_obsdata//k5ts4/T2520745??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.252.07:46:15.85/k5log//k5ts1_log_newline 2006.252.07:46:16.54/k5log//k5ts2_log_newline 2006.252.07:46:17.24/k5log//k5ts3_log_newline 2006.252.07:46:17.93/k5log//k5ts4_log_newline 2006.252.07:46:17.95/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.252.07:46:17.95:4f8m12a=1 2006.252.07:46:17.95$4f8m12a/echo=on 2006.252.07:46:17.95$4f8m12a/pcalon 2006.252.07:46:17.95$pcalon/"no phase cal control is implemented here 2006.252.07:46:17.95$4f8m12a/"tpicd=stop 2006.252.07:46:17.95$4f8m12a/vc4f8 2006.252.07:46:17.95$vc4f8/valo=1,532.99 2006.252.07:46:17.96#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.252.07:46:17.96#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.252.07:46:17.96#ibcon#ireg 17 cls_cnt 0 2006.252.07:46:17.96#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.252.07:46:17.96#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.252.07:46:17.96#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.252.07:46:17.96#ibcon#enter wrdev, iclass 11, count 0 2006.252.07:46:17.96#ibcon#first serial, iclass 11, count 0 2006.252.07:46:17.96#ibcon#enter sib2, iclass 11, count 0 2006.252.07:46:17.96#ibcon#flushed, iclass 11, count 0 2006.252.07:46:17.96#ibcon#about to write, iclass 11, count 0 2006.252.07:46:17.96#ibcon#wrote, iclass 11, count 0 2006.252.07:46:17.96#ibcon#about to read 3, iclass 11, count 0 2006.252.07:46:18.00#ibcon#read 3, iclass 11, count 0 2006.252.07:46:18.00#ibcon#about to read 4, iclass 11, count 0 2006.252.07:46:18.00#ibcon#read 4, iclass 11, count 0 2006.252.07:46:18.00#ibcon#about to read 5, iclass 11, count 0 2006.252.07:46:18.00#ibcon#read 5, iclass 11, count 0 2006.252.07:46:18.00#ibcon#about to read 6, iclass 11, count 0 2006.252.07:46:18.00#ibcon#read 6, iclass 11, count 0 2006.252.07:46:18.00#ibcon#end of sib2, iclass 11, count 0 2006.252.07:46:18.00#ibcon#*mode == 0, iclass 11, count 0 2006.252.07:46:18.00#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.252.07:46:18.00#ibcon#[26=FRQ=01,532.99\r\n] 2006.252.07:46:18.00#ibcon#*before write, iclass 11, count 0 2006.252.07:46:18.00#ibcon#enter sib2, iclass 11, count 0 2006.252.07:46:18.00#ibcon#flushed, iclass 11, count 0 2006.252.07:46:18.00#ibcon#about to write, iclass 11, count 0 2006.252.07:46:18.00#ibcon#wrote, iclass 11, count 0 2006.252.07:46:18.00#ibcon#about to read 3, iclass 11, count 0 2006.252.07:46:18.04#ibcon#read 3, iclass 11, count 0 2006.252.07:46:18.04#ibcon#about to read 4, iclass 11, count 0 2006.252.07:46:18.04#ibcon#read 4, iclass 11, count 0 2006.252.07:46:18.04#ibcon#about to read 5, iclass 11, count 0 2006.252.07:46:18.04#ibcon#read 5, iclass 11, count 0 2006.252.07:46:18.04#ibcon#about to read 6, iclass 11, count 0 2006.252.07:46:18.04#ibcon#read 6, iclass 11, count 0 2006.252.07:46:18.04#ibcon#end of sib2, iclass 11, count 0 2006.252.07:46:18.04#ibcon#*after write, iclass 11, count 0 2006.252.07:46:18.04#ibcon#*before return 0, iclass 11, count 0 2006.252.07:46:18.04#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.252.07:46:18.04#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.252.07:46:18.04#ibcon#about to clear, iclass 11 cls_cnt 0 2006.252.07:46:18.04#ibcon#cleared, iclass 11 cls_cnt 0 2006.252.07:46:18.04$vc4f8/va=1,8 2006.252.07:46:18.04#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.252.07:46:18.04#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.252.07:46:18.04#ibcon#ireg 11 cls_cnt 2 2006.252.07:46:18.04#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.252.07:46:18.04#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.252.07:46:18.04#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.252.07:46:18.04#ibcon#enter wrdev, iclass 13, count 2 2006.252.07:46:18.04#ibcon#first serial, iclass 13, count 2 2006.252.07:46:18.04#ibcon#enter sib2, iclass 13, count 2 2006.252.07:46:18.04#ibcon#flushed, iclass 13, count 2 2006.252.07:46:18.04#ibcon#about to write, iclass 13, count 2 2006.252.07:46:18.04#ibcon#wrote, iclass 13, count 2 2006.252.07:46:18.04#ibcon#about to read 3, iclass 13, count 2 2006.252.07:46:18.06#ibcon#read 3, iclass 13, count 2 2006.252.07:46:18.06#ibcon#about to read 4, iclass 13, count 2 2006.252.07:46:18.06#ibcon#read 4, iclass 13, count 2 2006.252.07:46:18.06#ibcon#about to read 5, iclass 13, count 2 2006.252.07:46:18.06#ibcon#read 5, iclass 13, count 2 2006.252.07:46:18.06#ibcon#about to read 6, iclass 13, count 2 2006.252.07:46:18.06#ibcon#read 6, iclass 13, count 2 2006.252.07:46:18.06#ibcon#end of sib2, iclass 13, count 2 2006.252.07:46:18.06#ibcon#*mode == 0, iclass 13, count 2 2006.252.07:46:18.06#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.252.07:46:18.06#ibcon#[25=AT01-08\r\n] 2006.252.07:46:18.06#ibcon#*before write, iclass 13, count 2 2006.252.07:46:18.06#ibcon#enter sib2, iclass 13, count 2 2006.252.07:46:18.06#ibcon#flushed, iclass 13, count 2 2006.252.07:46:18.06#ibcon#about to write, iclass 13, count 2 2006.252.07:46:18.06#ibcon#wrote, iclass 13, count 2 2006.252.07:46:18.06#ibcon#about to read 3, iclass 13, count 2 2006.252.07:46:18.09#ibcon#read 3, iclass 13, count 2 2006.252.07:46:18.09#ibcon#about to read 4, iclass 13, count 2 2006.252.07:46:18.09#ibcon#read 4, iclass 13, count 2 2006.252.07:46:18.09#ibcon#about to read 5, iclass 13, count 2 2006.252.07:46:18.09#ibcon#read 5, iclass 13, count 2 2006.252.07:46:18.09#ibcon#about to read 6, iclass 13, count 2 2006.252.07:46:18.09#ibcon#read 6, iclass 13, count 2 2006.252.07:46:18.09#ibcon#end of sib2, iclass 13, count 2 2006.252.07:46:18.09#ibcon#*after write, iclass 13, count 2 2006.252.07:46:18.09#ibcon#*before return 0, iclass 13, count 2 2006.252.07:46:18.09#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.252.07:46:18.09#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.252.07:46:18.09#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.252.07:46:18.09#ibcon#ireg 7 cls_cnt 0 2006.252.07:46:18.09#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.252.07:46:18.21#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.252.07:46:18.21#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.252.07:46:18.21#ibcon#enter wrdev, iclass 13, count 0 2006.252.07:46:18.21#ibcon#first serial, iclass 13, count 0 2006.252.07:46:18.21#ibcon#enter sib2, iclass 13, count 0 2006.252.07:46:18.21#ibcon#flushed, iclass 13, count 0 2006.252.07:46:18.21#ibcon#about to write, iclass 13, count 0 2006.252.07:46:18.21#ibcon#wrote, iclass 13, count 0 2006.252.07:46:18.21#ibcon#about to read 3, iclass 13, count 0 2006.252.07:46:18.23#ibcon#read 3, iclass 13, count 0 2006.252.07:46:18.23#ibcon#about to read 4, iclass 13, count 0 2006.252.07:46:18.23#ibcon#read 4, iclass 13, count 0 2006.252.07:46:18.23#ibcon#about to read 5, iclass 13, count 0 2006.252.07:46:18.23#ibcon#read 5, iclass 13, count 0 2006.252.07:46:18.23#ibcon#about to read 6, iclass 13, count 0 2006.252.07:46:18.23#ibcon#read 6, iclass 13, count 0 2006.252.07:46:18.23#ibcon#end of sib2, iclass 13, count 0 2006.252.07:46:18.23#ibcon#*mode == 0, iclass 13, count 0 2006.252.07:46:18.23#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.252.07:46:18.23#ibcon#[25=USB\r\n] 2006.252.07:46:18.23#ibcon#*before write, iclass 13, count 0 2006.252.07:46:18.23#ibcon#enter sib2, iclass 13, count 0 2006.252.07:46:18.23#ibcon#flushed, iclass 13, count 0 2006.252.07:46:18.23#ibcon#about to write, iclass 13, count 0 2006.252.07:46:18.23#ibcon#wrote, iclass 13, count 0 2006.252.07:46:18.23#ibcon#about to read 3, iclass 13, count 0 2006.252.07:46:18.26#ibcon#read 3, iclass 13, count 0 2006.252.07:46:18.26#ibcon#about to read 4, iclass 13, count 0 2006.252.07:46:18.26#ibcon#read 4, iclass 13, count 0 2006.252.07:46:18.26#ibcon#about to read 5, iclass 13, count 0 2006.252.07:46:18.26#ibcon#read 5, iclass 13, count 0 2006.252.07:46:18.26#ibcon#about to read 6, iclass 13, count 0 2006.252.07:46:18.26#ibcon#read 6, iclass 13, count 0 2006.252.07:46:18.26#ibcon#end of sib2, iclass 13, count 0 2006.252.07:46:18.26#ibcon#*after write, iclass 13, count 0 2006.252.07:46:18.26#ibcon#*before return 0, iclass 13, count 0 2006.252.07:46:18.26#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.252.07:46:18.26#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.252.07:46:18.26#ibcon#about to clear, iclass 13 cls_cnt 0 2006.252.07:46:18.26#ibcon#cleared, iclass 13 cls_cnt 0 2006.252.07:46:18.26$vc4f8/valo=2,572.99 2006.252.07:46:18.26#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.252.07:46:18.26#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.252.07:46:18.26#ibcon#ireg 17 cls_cnt 0 2006.252.07:46:18.26#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.252.07:46:18.26#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.252.07:46:18.26#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.252.07:46:18.26#ibcon#enter wrdev, iclass 15, count 0 2006.252.07:46:18.26#ibcon#first serial, iclass 15, count 0 2006.252.07:46:18.26#ibcon#enter sib2, iclass 15, count 0 2006.252.07:46:18.26#ibcon#flushed, iclass 15, count 0 2006.252.07:46:18.26#ibcon#about to write, iclass 15, count 0 2006.252.07:46:18.26#ibcon#wrote, iclass 15, count 0 2006.252.07:46:18.26#ibcon#about to read 3, iclass 15, count 0 2006.252.07:46:18.29#ibcon#read 3, iclass 15, count 0 2006.252.07:46:18.29#ibcon#about to read 4, iclass 15, count 0 2006.252.07:46:18.29#ibcon#read 4, iclass 15, count 0 2006.252.07:46:18.29#ibcon#about to read 5, iclass 15, count 0 2006.252.07:46:18.29#ibcon#read 5, iclass 15, count 0 2006.252.07:46:18.29#ibcon#about to read 6, iclass 15, count 0 2006.252.07:46:18.29#ibcon#read 6, iclass 15, count 0 2006.252.07:46:18.29#ibcon#end of sib2, iclass 15, count 0 2006.252.07:46:18.29#ibcon#*mode == 0, iclass 15, count 0 2006.252.07:46:18.29#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.252.07:46:18.29#ibcon#[26=FRQ=02,572.99\r\n] 2006.252.07:46:18.29#ibcon#*before write, iclass 15, count 0 2006.252.07:46:18.29#ibcon#enter sib2, iclass 15, count 0 2006.252.07:46:18.29#ibcon#flushed, iclass 15, count 0 2006.252.07:46:18.29#ibcon#about to write, iclass 15, count 0 2006.252.07:46:18.29#ibcon#wrote, iclass 15, count 0 2006.252.07:46:18.29#ibcon#about to read 3, iclass 15, count 0 2006.252.07:46:18.33#ibcon#read 3, iclass 15, count 0 2006.252.07:46:18.33#ibcon#about to read 4, iclass 15, count 0 2006.252.07:46:18.33#ibcon#read 4, iclass 15, count 0 2006.252.07:46:18.33#ibcon#about to read 5, iclass 15, count 0 2006.252.07:46:18.33#ibcon#read 5, iclass 15, count 0 2006.252.07:46:18.33#ibcon#about to read 6, iclass 15, count 0 2006.252.07:46:18.33#ibcon#read 6, iclass 15, count 0 2006.252.07:46:18.33#ibcon#end of sib2, iclass 15, count 0 2006.252.07:46:18.33#ibcon#*after write, iclass 15, count 0 2006.252.07:46:18.33#ibcon#*before return 0, iclass 15, count 0 2006.252.07:46:18.33#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.252.07:46:18.33#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.252.07:46:18.33#ibcon#about to clear, iclass 15 cls_cnt 0 2006.252.07:46:18.33#ibcon#cleared, iclass 15 cls_cnt 0 2006.252.07:46:18.33$vc4f8/va=2,7 2006.252.07:46:18.33#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.252.07:46:18.33#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.252.07:46:18.33#ibcon#ireg 11 cls_cnt 2 2006.252.07:46:18.33#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.252.07:46:18.38#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.252.07:46:18.38#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.252.07:46:18.38#ibcon#enter wrdev, iclass 17, count 2 2006.252.07:46:18.38#ibcon#first serial, iclass 17, count 2 2006.252.07:46:18.38#ibcon#enter sib2, iclass 17, count 2 2006.252.07:46:18.38#ibcon#flushed, iclass 17, count 2 2006.252.07:46:18.38#ibcon#about to write, iclass 17, count 2 2006.252.07:46:18.38#ibcon#wrote, iclass 17, count 2 2006.252.07:46:18.38#ibcon#about to read 3, iclass 17, count 2 2006.252.07:46:18.40#ibcon#read 3, iclass 17, count 2 2006.252.07:46:18.40#ibcon#about to read 4, iclass 17, count 2 2006.252.07:46:18.40#ibcon#read 4, iclass 17, count 2 2006.252.07:46:18.40#ibcon#about to read 5, iclass 17, count 2 2006.252.07:46:18.40#ibcon#read 5, iclass 17, count 2 2006.252.07:46:18.40#ibcon#about to read 6, iclass 17, count 2 2006.252.07:46:18.40#ibcon#read 6, iclass 17, count 2 2006.252.07:46:18.40#ibcon#end of sib2, iclass 17, count 2 2006.252.07:46:18.40#ibcon#*mode == 0, iclass 17, count 2 2006.252.07:46:18.40#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.252.07:46:18.40#ibcon#[25=AT02-07\r\n] 2006.252.07:46:18.40#ibcon#*before write, iclass 17, count 2 2006.252.07:46:18.40#ibcon#enter sib2, iclass 17, count 2 2006.252.07:46:18.40#ibcon#flushed, iclass 17, count 2 2006.252.07:46:18.40#ibcon#about to write, iclass 17, count 2 2006.252.07:46:18.40#ibcon#wrote, iclass 17, count 2 2006.252.07:46:18.40#ibcon#about to read 3, iclass 17, count 2 2006.252.07:46:18.43#ibcon#read 3, iclass 17, count 2 2006.252.07:46:18.43#ibcon#about to read 4, iclass 17, count 2 2006.252.07:46:18.43#ibcon#read 4, iclass 17, count 2 2006.252.07:46:18.43#ibcon#about to read 5, iclass 17, count 2 2006.252.07:46:18.43#ibcon#read 5, iclass 17, count 2 2006.252.07:46:18.43#ibcon#about to read 6, iclass 17, count 2 2006.252.07:46:18.43#ibcon#read 6, iclass 17, count 2 2006.252.07:46:18.43#ibcon#end of sib2, iclass 17, count 2 2006.252.07:46:18.43#ibcon#*after write, iclass 17, count 2 2006.252.07:46:18.43#ibcon#*before return 0, iclass 17, count 2 2006.252.07:46:18.43#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.252.07:46:18.43#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.252.07:46:18.43#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.252.07:46:18.43#ibcon#ireg 7 cls_cnt 0 2006.252.07:46:18.43#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.252.07:46:18.55#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.252.07:46:18.55#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.252.07:46:18.55#ibcon#enter wrdev, iclass 17, count 0 2006.252.07:46:18.55#ibcon#first serial, iclass 17, count 0 2006.252.07:46:18.55#ibcon#enter sib2, iclass 17, count 0 2006.252.07:46:18.55#ibcon#flushed, iclass 17, count 0 2006.252.07:46:18.55#ibcon#about to write, iclass 17, count 0 2006.252.07:46:18.55#ibcon#wrote, iclass 17, count 0 2006.252.07:46:18.55#ibcon#about to read 3, iclass 17, count 0 2006.252.07:46:18.57#ibcon#read 3, iclass 17, count 0 2006.252.07:46:18.57#ibcon#about to read 4, iclass 17, count 0 2006.252.07:46:18.57#ibcon#read 4, iclass 17, count 0 2006.252.07:46:18.57#ibcon#about to read 5, iclass 17, count 0 2006.252.07:46:18.57#ibcon#read 5, iclass 17, count 0 2006.252.07:46:18.57#ibcon#about to read 6, iclass 17, count 0 2006.252.07:46:18.57#ibcon#read 6, iclass 17, count 0 2006.252.07:46:18.57#ibcon#end of sib2, iclass 17, count 0 2006.252.07:46:18.57#ibcon#*mode == 0, iclass 17, count 0 2006.252.07:46:18.57#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.252.07:46:18.57#ibcon#[25=USB\r\n] 2006.252.07:46:18.57#ibcon#*before write, iclass 17, count 0 2006.252.07:46:18.57#ibcon#enter sib2, iclass 17, count 0 2006.252.07:46:18.57#ibcon#flushed, iclass 17, count 0 2006.252.07:46:18.57#ibcon#about to write, iclass 17, count 0 2006.252.07:46:18.57#ibcon#wrote, iclass 17, count 0 2006.252.07:46:18.57#ibcon#about to read 3, iclass 17, count 0 2006.252.07:46:18.60#ibcon#read 3, iclass 17, count 0 2006.252.07:46:18.60#ibcon#about to read 4, iclass 17, count 0 2006.252.07:46:18.60#ibcon#read 4, iclass 17, count 0 2006.252.07:46:18.60#ibcon#about to read 5, iclass 17, count 0 2006.252.07:46:18.60#ibcon#read 5, iclass 17, count 0 2006.252.07:46:18.60#ibcon#about to read 6, iclass 17, count 0 2006.252.07:46:18.60#ibcon#read 6, iclass 17, count 0 2006.252.07:46:18.60#ibcon#end of sib2, iclass 17, count 0 2006.252.07:46:18.60#ibcon#*after write, iclass 17, count 0 2006.252.07:46:18.60#ibcon#*before return 0, iclass 17, count 0 2006.252.07:46:18.60#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.252.07:46:18.60#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.252.07:46:18.60#ibcon#about to clear, iclass 17 cls_cnt 0 2006.252.07:46:18.60#ibcon#cleared, iclass 17 cls_cnt 0 2006.252.07:46:18.60$vc4f8/valo=3,672.99 2006.252.07:46:18.60#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.252.07:46:18.60#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.252.07:46:18.60#ibcon#ireg 17 cls_cnt 0 2006.252.07:46:18.60#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.252.07:46:18.60#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.252.07:46:18.60#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.252.07:46:18.60#ibcon#enter wrdev, iclass 19, count 0 2006.252.07:46:18.60#ibcon#first serial, iclass 19, count 0 2006.252.07:46:18.60#ibcon#enter sib2, iclass 19, count 0 2006.252.07:46:18.60#ibcon#flushed, iclass 19, count 0 2006.252.07:46:18.60#ibcon#about to write, iclass 19, count 0 2006.252.07:46:18.60#ibcon#wrote, iclass 19, count 0 2006.252.07:46:18.60#ibcon#about to read 3, iclass 19, count 0 2006.252.07:46:18.62#ibcon#read 3, iclass 19, count 0 2006.252.07:46:18.62#ibcon#about to read 4, iclass 19, count 0 2006.252.07:46:18.62#ibcon#read 4, iclass 19, count 0 2006.252.07:46:18.62#ibcon#about to read 5, iclass 19, count 0 2006.252.07:46:18.62#ibcon#read 5, iclass 19, count 0 2006.252.07:46:18.62#ibcon#about to read 6, iclass 19, count 0 2006.252.07:46:18.62#ibcon#read 6, iclass 19, count 0 2006.252.07:46:18.62#ibcon#end of sib2, iclass 19, count 0 2006.252.07:46:18.62#ibcon#*mode == 0, iclass 19, count 0 2006.252.07:46:18.62#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.252.07:46:18.62#ibcon#[26=FRQ=03,672.99\r\n] 2006.252.07:46:18.62#ibcon#*before write, iclass 19, count 0 2006.252.07:46:18.62#ibcon#enter sib2, iclass 19, count 0 2006.252.07:46:18.62#ibcon#flushed, iclass 19, count 0 2006.252.07:46:18.62#ibcon#about to write, iclass 19, count 0 2006.252.07:46:18.62#ibcon#wrote, iclass 19, count 0 2006.252.07:46:18.62#ibcon#about to read 3, iclass 19, count 0 2006.252.07:46:18.66#ibcon#read 3, iclass 19, count 0 2006.252.07:46:18.66#ibcon#about to read 4, iclass 19, count 0 2006.252.07:46:18.66#ibcon#read 4, iclass 19, count 0 2006.252.07:46:18.66#ibcon#about to read 5, iclass 19, count 0 2006.252.07:46:18.66#ibcon#read 5, iclass 19, count 0 2006.252.07:46:18.66#ibcon#about to read 6, iclass 19, count 0 2006.252.07:46:18.66#ibcon#read 6, iclass 19, count 0 2006.252.07:46:18.66#ibcon#end of sib2, iclass 19, count 0 2006.252.07:46:18.66#ibcon#*after write, iclass 19, count 0 2006.252.07:46:18.66#ibcon#*before return 0, iclass 19, count 0 2006.252.07:46:18.66#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.252.07:46:18.66#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.252.07:46:18.66#ibcon#about to clear, iclass 19 cls_cnt 0 2006.252.07:46:18.66#ibcon#cleared, iclass 19 cls_cnt 0 2006.252.07:46:18.66$vc4f8/va=3,6 2006.252.07:46:18.66#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.252.07:46:18.66#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.252.07:46:18.66#ibcon#ireg 11 cls_cnt 2 2006.252.07:46:18.66#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.252.07:46:18.73#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.252.07:46:18.73#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.252.07:46:18.73#ibcon#enter wrdev, iclass 21, count 2 2006.252.07:46:18.73#ibcon#first serial, iclass 21, count 2 2006.252.07:46:18.73#ibcon#enter sib2, iclass 21, count 2 2006.252.07:46:18.73#ibcon#flushed, iclass 21, count 2 2006.252.07:46:18.73#ibcon#about to write, iclass 21, count 2 2006.252.07:46:18.73#ibcon#wrote, iclass 21, count 2 2006.252.07:46:18.73#ibcon#about to read 3, iclass 21, count 2 2006.252.07:46:18.74#ibcon#read 3, iclass 21, count 2 2006.252.07:46:18.74#ibcon#about to read 4, iclass 21, count 2 2006.252.07:46:18.74#ibcon#read 4, iclass 21, count 2 2006.252.07:46:18.74#ibcon#about to read 5, iclass 21, count 2 2006.252.07:46:18.74#ibcon#read 5, iclass 21, count 2 2006.252.07:46:18.74#ibcon#about to read 6, iclass 21, count 2 2006.252.07:46:18.74#ibcon#read 6, iclass 21, count 2 2006.252.07:46:18.74#ibcon#end of sib2, iclass 21, count 2 2006.252.07:46:18.74#ibcon#*mode == 0, iclass 21, count 2 2006.252.07:46:18.74#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.252.07:46:18.74#ibcon#[25=AT03-06\r\n] 2006.252.07:46:18.74#ibcon#*before write, iclass 21, count 2 2006.252.07:46:18.74#ibcon#enter sib2, iclass 21, count 2 2006.252.07:46:18.74#ibcon#flushed, iclass 21, count 2 2006.252.07:46:18.74#ibcon#about to write, iclass 21, count 2 2006.252.07:46:18.74#ibcon#wrote, iclass 21, count 2 2006.252.07:46:18.74#ibcon#about to read 3, iclass 21, count 2 2006.252.07:46:18.77#ibcon#read 3, iclass 21, count 2 2006.252.07:46:18.77#ibcon#about to read 4, iclass 21, count 2 2006.252.07:46:18.77#ibcon#read 4, iclass 21, count 2 2006.252.07:46:18.77#ibcon#about to read 5, iclass 21, count 2 2006.252.07:46:18.77#ibcon#read 5, iclass 21, count 2 2006.252.07:46:18.77#ibcon#about to read 6, iclass 21, count 2 2006.252.07:46:18.77#ibcon#read 6, iclass 21, count 2 2006.252.07:46:18.77#ibcon#end of sib2, iclass 21, count 2 2006.252.07:46:18.77#ibcon#*after write, iclass 21, count 2 2006.252.07:46:18.77#ibcon#*before return 0, iclass 21, count 2 2006.252.07:46:18.77#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.252.07:46:18.77#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.252.07:46:18.77#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.252.07:46:18.77#ibcon#ireg 7 cls_cnt 0 2006.252.07:46:18.77#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.252.07:46:18.89#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.252.07:46:18.89#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.252.07:46:18.89#ibcon#enter wrdev, iclass 21, count 0 2006.252.07:46:18.89#ibcon#first serial, iclass 21, count 0 2006.252.07:46:18.89#ibcon#enter sib2, iclass 21, count 0 2006.252.07:46:18.89#ibcon#flushed, iclass 21, count 0 2006.252.07:46:18.89#ibcon#about to write, iclass 21, count 0 2006.252.07:46:18.89#ibcon#wrote, iclass 21, count 0 2006.252.07:46:18.89#ibcon#about to read 3, iclass 21, count 0 2006.252.07:46:18.91#ibcon#read 3, iclass 21, count 0 2006.252.07:46:18.91#ibcon#about to read 4, iclass 21, count 0 2006.252.07:46:18.91#ibcon#read 4, iclass 21, count 0 2006.252.07:46:18.91#ibcon#about to read 5, iclass 21, count 0 2006.252.07:46:18.91#ibcon#read 5, iclass 21, count 0 2006.252.07:46:18.91#ibcon#about to read 6, iclass 21, count 0 2006.252.07:46:18.91#ibcon#read 6, iclass 21, count 0 2006.252.07:46:18.91#ibcon#end of sib2, iclass 21, count 0 2006.252.07:46:18.91#ibcon#*mode == 0, iclass 21, count 0 2006.252.07:46:18.91#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.252.07:46:18.91#ibcon#[25=USB\r\n] 2006.252.07:46:18.91#ibcon#*before write, iclass 21, count 0 2006.252.07:46:18.91#ibcon#enter sib2, iclass 21, count 0 2006.252.07:46:18.91#ibcon#flushed, iclass 21, count 0 2006.252.07:46:18.91#ibcon#about to write, iclass 21, count 0 2006.252.07:46:18.91#ibcon#wrote, iclass 21, count 0 2006.252.07:46:18.91#ibcon#about to read 3, iclass 21, count 0 2006.252.07:46:18.94#ibcon#read 3, iclass 21, count 0 2006.252.07:46:18.94#ibcon#about to read 4, iclass 21, count 0 2006.252.07:46:18.94#ibcon#read 4, iclass 21, count 0 2006.252.07:46:18.94#ibcon#about to read 5, iclass 21, count 0 2006.252.07:46:18.94#ibcon#read 5, iclass 21, count 0 2006.252.07:46:18.94#ibcon#about to read 6, iclass 21, count 0 2006.252.07:46:18.94#ibcon#read 6, iclass 21, count 0 2006.252.07:46:18.94#ibcon#end of sib2, iclass 21, count 0 2006.252.07:46:18.94#ibcon#*after write, iclass 21, count 0 2006.252.07:46:18.94#ibcon#*before return 0, iclass 21, count 0 2006.252.07:46:18.94#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.252.07:46:18.94#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.252.07:46:18.94#ibcon#about to clear, iclass 21 cls_cnt 0 2006.252.07:46:18.94#ibcon#cleared, iclass 21 cls_cnt 0 2006.252.07:46:18.94$vc4f8/valo=4,832.99 2006.252.07:46:18.94#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.252.07:46:18.94#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.252.07:46:18.94#ibcon#ireg 17 cls_cnt 0 2006.252.07:46:18.94#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.252.07:46:18.94#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.252.07:46:18.94#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.252.07:46:18.94#ibcon#enter wrdev, iclass 23, count 0 2006.252.07:46:18.94#ibcon#first serial, iclass 23, count 0 2006.252.07:46:18.94#ibcon#enter sib2, iclass 23, count 0 2006.252.07:46:18.94#ibcon#flushed, iclass 23, count 0 2006.252.07:46:18.94#ibcon#about to write, iclass 23, count 0 2006.252.07:46:18.94#ibcon#wrote, iclass 23, count 0 2006.252.07:46:18.94#ibcon#about to read 3, iclass 23, count 0 2006.252.07:46:18.96#ibcon#read 3, iclass 23, count 0 2006.252.07:46:18.96#ibcon#about to read 4, iclass 23, count 0 2006.252.07:46:18.96#ibcon#read 4, iclass 23, count 0 2006.252.07:46:18.96#ibcon#about to read 5, iclass 23, count 0 2006.252.07:46:18.96#ibcon#read 5, iclass 23, count 0 2006.252.07:46:18.96#ibcon#about to read 6, iclass 23, count 0 2006.252.07:46:18.96#ibcon#read 6, iclass 23, count 0 2006.252.07:46:18.96#ibcon#end of sib2, iclass 23, count 0 2006.252.07:46:18.96#ibcon#*mode == 0, iclass 23, count 0 2006.252.07:46:18.96#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.252.07:46:18.96#ibcon#[26=FRQ=04,832.99\r\n] 2006.252.07:46:18.96#ibcon#*before write, iclass 23, count 0 2006.252.07:46:18.96#ibcon#enter sib2, iclass 23, count 0 2006.252.07:46:18.96#ibcon#flushed, iclass 23, count 0 2006.252.07:46:18.96#ibcon#about to write, iclass 23, count 0 2006.252.07:46:18.96#ibcon#wrote, iclass 23, count 0 2006.252.07:46:18.96#ibcon#about to read 3, iclass 23, count 0 2006.252.07:46:19.00#ibcon#read 3, iclass 23, count 0 2006.252.07:46:19.00#ibcon#about to read 4, iclass 23, count 0 2006.252.07:46:19.00#ibcon#read 4, iclass 23, count 0 2006.252.07:46:19.00#ibcon#about to read 5, iclass 23, count 0 2006.252.07:46:19.00#ibcon#read 5, iclass 23, count 0 2006.252.07:46:19.00#ibcon#about to read 6, iclass 23, count 0 2006.252.07:46:19.00#ibcon#read 6, iclass 23, count 0 2006.252.07:46:19.00#ibcon#end of sib2, iclass 23, count 0 2006.252.07:46:19.00#ibcon#*after write, iclass 23, count 0 2006.252.07:46:19.00#ibcon#*before return 0, iclass 23, count 0 2006.252.07:46:19.00#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.252.07:46:19.00#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.252.07:46:19.00#ibcon#about to clear, iclass 23 cls_cnt 0 2006.252.07:46:19.00#ibcon#cleared, iclass 23 cls_cnt 0 2006.252.07:46:19.00$vc4f8/va=4,7 2006.252.07:46:19.00#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.252.07:46:19.00#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.252.07:46:19.00#ibcon#ireg 11 cls_cnt 2 2006.252.07:46:19.00#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.252.07:46:19.06#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.252.07:46:19.06#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.252.07:46:19.06#ibcon#enter wrdev, iclass 25, count 2 2006.252.07:46:19.06#ibcon#first serial, iclass 25, count 2 2006.252.07:46:19.06#ibcon#enter sib2, iclass 25, count 2 2006.252.07:46:19.06#ibcon#flushed, iclass 25, count 2 2006.252.07:46:19.06#ibcon#about to write, iclass 25, count 2 2006.252.07:46:19.06#ibcon#wrote, iclass 25, count 2 2006.252.07:46:19.06#ibcon#about to read 3, iclass 25, count 2 2006.252.07:46:19.08#ibcon#read 3, iclass 25, count 2 2006.252.07:46:19.08#ibcon#about to read 4, iclass 25, count 2 2006.252.07:46:19.08#ibcon#read 4, iclass 25, count 2 2006.252.07:46:19.08#ibcon#about to read 5, iclass 25, count 2 2006.252.07:46:19.08#ibcon#read 5, iclass 25, count 2 2006.252.07:46:19.08#ibcon#about to read 6, iclass 25, count 2 2006.252.07:46:19.08#ibcon#read 6, iclass 25, count 2 2006.252.07:46:19.08#ibcon#end of sib2, iclass 25, count 2 2006.252.07:46:19.08#ibcon#*mode == 0, iclass 25, count 2 2006.252.07:46:19.08#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.252.07:46:19.08#ibcon#[25=AT04-07\r\n] 2006.252.07:46:19.08#ibcon#*before write, iclass 25, count 2 2006.252.07:46:19.08#ibcon#enter sib2, iclass 25, count 2 2006.252.07:46:19.08#ibcon#flushed, iclass 25, count 2 2006.252.07:46:19.08#ibcon#about to write, iclass 25, count 2 2006.252.07:46:19.08#ibcon#wrote, iclass 25, count 2 2006.252.07:46:19.08#ibcon#about to read 3, iclass 25, count 2 2006.252.07:46:19.11#ibcon#read 3, iclass 25, count 2 2006.252.07:46:19.11#ibcon#about to read 4, iclass 25, count 2 2006.252.07:46:19.11#ibcon#read 4, iclass 25, count 2 2006.252.07:46:19.11#ibcon#about to read 5, iclass 25, count 2 2006.252.07:46:19.11#ibcon#read 5, iclass 25, count 2 2006.252.07:46:19.11#ibcon#about to read 6, iclass 25, count 2 2006.252.07:46:19.11#ibcon#read 6, iclass 25, count 2 2006.252.07:46:19.11#ibcon#end of sib2, iclass 25, count 2 2006.252.07:46:19.11#ibcon#*after write, iclass 25, count 2 2006.252.07:46:19.11#ibcon#*before return 0, iclass 25, count 2 2006.252.07:46:19.11#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.252.07:46:19.11#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.252.07:46:19.11#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.252.07:46:19.11#ibcon#ireg 7 cls_cnt 0 2006.252.07:46:19.11#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.252.07:46:19.23#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.252.07:46:19.23#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.252.07:46:19.23#ibcon#enter wrdev, iclass 25, count 0 2006.252.07:46:19.23#ibcon#first serial, iclass 25, count 0 2006.252.07:46:19.23#ibcon#enter sib2, iclass 25, count 0 2006.252.07:46:19.23#ibcon#flushed, iclass 25, count 0 2006.252.07:46:19.23#ibcon#about to write, iclass 25, count 0 2006.252.07:46:19.23#ibcon#wrote, iclass 25, count 0 2006.252.07:46:19.23#ibcon#about to read 3, iclass 25, count 0 2006.252.07:46:19.25#ibcon#read 3, iclass 25, count 0 2006.252.07:46:19.25#ibcon#about to read 4, iclass 25, count 0 2006.252.07:46:19.25#ibcon#read 4, iclass 25, count 0 2006.252.07:46:19.25#ibcon#about to read 5, iclass 25, count 0 2006.252.07:46:19.25#ibcon#read 5, iclass 25, count 0 2006.252.07:46:19.25#ibcon#about to read 6, iclass 25, count 0 2006.252.07:46:19.25#ibcon#read 6, iclass 25, count 0 2006.252.07:46:19.25#ibcon#end of sib2, iclass 25, count 0 2006.252.07:46:19.25#ibcon#*mode == 0, iclass 25, count 0 2006.252.07:46:19.25#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.252.07:46:19.25#ibcon#[25=USB\r\n] 2006.252.07:46:19.25#ibcon#*before write, iclass 25, count 0 2006.252.07:46:19.25#ibcon#enter sib2, iclass 25, count 0 2006.252.07:46:19.25#ibcon#flushed, iclass 25, count 0 2006.252.07:46:19.25#ibcon#about to write, iclass 25, count 0 2006.252.07:46:19.25#ibcon#wrote, iclass 25, count 0 2006.252.07:46:19.25#ibcon#about to read 3, iclass 25, count 0 2006.252.07:46:19.28#ibcon#read 3, iclass 25, count 0 2006.252.07:46:19.28#ibcon#about to read 4, iclass 25, count 0 2006.252.07:46:19.28#ibcon#read 4, iclass 25, count 0 2006.252.07:46:19.28#ibcon#about to read 5, iclass 25, count 0 2006.252.07:46:19.28#ibcon#read 5, iclass 25, count 0 2006.252.07:46:19.28#ibcon#about to read 6, iclass 25, count 0 2006.252.07:46:19.28#ibcon#read 6, iclass 25, count 0 2006.252.07:46:19.28#ibcon#end of sib2, iclass 25, count 0 2006.252.07:46:19.28#ibcon#*after write, iclass 25, count 0 2006.252.07:46:19.28#ibcon#*before return 0, iclass 25, count 0 2006.252.07:46:19.28#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.252.07:46:19.28#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.252.07:46:19.28#ibcon#about to clear, iclass 25 cls_cnt 0 2006.252.07:46:19.28#ibcon#cleared, iclass 25 cls_cnt 0 2006.252.07:46:19.28$vc4f8/valo=5,652.99 2006.252.07:46:19.28#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.252.07:46:19.28#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.252.07:46:19.28#ibcon#ireg 17 cls_cnt 0 2006.252.07:46:19.28#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.252.07:46:19.28#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.252.07:46:19.28#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.252.07:46:19.28#ibcon#enter wrdev, iclass 27, count 0 2006.252.07:46:19.28#ibcon#first serial, iclass 27, count 0 2006.252.07:46:19.28#ibcon#enter sib2, iclass 27, count 0 2006.252.07:46:19.28#ibcon#flushed, iclass 27, count 0 2006.252.07:46:19.28#ibcon#about to write, iclass 27, count 0 2006.252.07:46:19.28#ibcon#wrote, iclass 27, count 0 2006.252.07:46:19.28#ibcon#about to read 3, iclass 27, count 0 2006.252.07:46:19.30#ibcon#read 3, iclass 27, count 0 2006.252.07:46:19.30#ibcon#about to read 4, iclass 27, count 0 2006.252.07:46:19.30#ibcon#read 4, iclass 27, count 0 2006.252.07:46:19.30#ibcon#about to read 5, iclass 27, count 0 2006.252.07:46:19.30#ibcon#read 5, iclass 27, count 0 2006.252.07:46:19.30#ibcon#about to read 6, iclass 27, count 0 2006.252.07:46:19.30#ibcon#read 6, iclass 27, count 0 2006.252.07:46:19.30#ibcon#end of sib2, iclass 27, count 0 2006.252.07:46:19.30#ibcon#*mode == 0, iclass 27, count 0 2006.252.07:46:19.30#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.252.07:46:19.30#ibcon#[26=FRQ=05,652.99\r\n] 2006.252.07:46:19.30#ibcon#*before write, iclass 27, count 0 2006.252.07:46:19.30#ibcon#enter sib2, iclass 27, count 0 2006.252.07:46:19.30#ibcon#flushed, iclass 27, count 0 2006.252.07:46:19.30#ibcon#about to write, iclass 27, count 0 2006.252.07:46:19.30#ibcon#wrote, iclass 27, count 0 2006.252.07:46:19.30#ibcon#about to read 3, iclass 27, count 0 2006.252.07:46:19.34#ibcon#read 3, iclass 27, count 0 2006.252.07:46:19.34#ibcon#about to read 4, iclass 27, count 0 2006.252.07:46:19.34#ibcon#read 4, iclass 27, count 0 2006.252.07:46:19.34#ibcon#about to read 5, iclass 27, count 0 2006.252.07:46:19.34#ibcon#read 5, iclass 27, count 0 2006.252.07:46:19.34#ibcon#about to read 6, iclass 27, count 0 2006.252.07:46:19.34#ibcon#read 6, iclass 27, count 0 2006.252.07:46:19.34#ibcon#end of sib2, iclass 27, count 0 2006.252.07:46:19.34#ibcon#*after write, iclass 27, count 0 2006.252.07:46:19.34#ibcon#*before return 0, iclass 27, count 0 2006.252.07:46:19.34#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.252.07:46:19.34#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.252.07:46:19.34#ibcon#about to clear, iclass 27 cls_cnt 0 2006.252.07:46:19.34#ibcon#cleared, iclass 27 cls_cnt 0 2006.252.07:46:19.34$vc4f8/va=5,7 2006.252.07:46:19.34#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.252.07:46:19.34#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.252.07:46:19.34#ibcon#ireg 11 cls_cnt 2 2006.252.07:46:19.34#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.252.07:46:19.40#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.252.07:46:19.40#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.252.07:46:19.40#ibcon#enter wrdev, iclass 29, count 2 2006.252.07:46:19.40#ibcon#first serial, iclass 29, count 2 2006.252.07:46:19.40#ibcon#enter sib2, iclass 29, count 2 2006.252.07:46:19.40#ibcon#flushed, iclass 29, count 2 2006.252.07:46:19.40#ibcon#about to write, iclass 29, count 2 2006.252.07:46:19.40#ibcon#wrote, iclass 29, count 2 2006.252.07:46:19.40#ibcon#about to read 3, iclass 29, count 2 2006.252.07:46:19.42#ibcon#read 3, iclass 29, count 2 2006.252.07:46:19.42#ibcon#about to read 4, iclass 29, count 2 2006.252.07:46:19.42#ibcon#read 4, iclass 29, count 2 2006.252.07:46:19.42#ibcon#about to read 5, iclass 29, count 2 2006.252.07:46:19.42#ibcon#read 5, iclass 29, count 2 2006.252.07:46:19.42#ibcon#about to read 6, iclass 29, count 2 2006.252.07:46:19.42#ibcon#read 6, iclass 29, count 2 2006.252.07:46:19.42#ibcon#end of sib2, iclass 29, count 2 2006.252.07:46:19.42#ibcon#*mode == 0, iclass 29, count 2 2006.252.07:46:19.42#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.252.07:46:19.42#ibcon#[25=AT05-07\r\n] 2006.252.07:46:19.42#ibcon#*before write, iclass 29, count 2 2006.252.07:46:19.42#ibcon#enter sib2, iclass 29, count 2 2006.252.07:46:19.42#ibcon#flushed, iclass 29, count 2 2006.252.07:46:19.42#ibcon#about to write, iclass 29, count 2 2006.252.07:46:19.42#ibcon#wrote, iclass 29, count 2 2006.252.07:46:19.42#ibcon#about to read 3, iclass 29, count 2 2006.252.07:46:19.45#ibcon#read 3, iclass 29, count 2 2006.252.07:46:19.45#ibcon#about to read 4, iclass 29, count 2 2006.252.07:46:19.45#ibcon#read 4, iclass 29, count 2 2006.252.07:46:19.45#ibcon#about to read 5, iclass 29, count 2 2006.252.07:46:19.45#ibcon#read 5, iclass 29, count 2 2006.252.07:46:19.45#ibcon#about to read 6, iclass 29, count 2 2006.252.07:46:19.45#ibcon#read 6, iclass 29, count 2 2006.252.07:46:19.45#ibcon#end of sib2, iclass 29, count 2 2006.252.07:46:19.45#ibcon#*after write, iclass 29, count 2 2006.252.07:46:19.45#ibcon#*before return 0, iclass 29, count 2 2006.252.07:46:19.45#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.252.07:46:19.45#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.252.07:46:19.45#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.252.07:46:19.45#ibcon#ireg 7 cls_cnt 0 2006.252.07:46:19.45#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.252.07:46:19.57#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.252.07:46:19.57#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.252.07:46:19.57#ibcon#enter wrdev, iclass 29, count 0 2006.252.07:46:19.57#ibcon#first serial, iclass 29, count 0 2006.252.07:46:19.57#ibcon#enter sib2, iclass 29, count 0 2006.252.07:46:19.57#ibcon#flushed, iclass 29, count 0 2006.252.07:46:19.57#ibcon#about to write, iclass 29, count 0 2006.252.07:46:19.57#ibcon#wrote, iclass 29, count 0 2006.252.07:46:19.57#ibcon#about to read 3, iclass 29, count 0 2006.252.07:46:19.59#ibcon#read 3, iclass 29, count 0 2006.252.07:46:19.59#ibcon#about to read 4, iclass 29, count 0 2006.252.07:46:19.59#ibcon#read 4, iclass 29, count 0 2006.252.07:46:19.59#ibcon#about to read 5, iclass 29, count 0 2006.252.07:46:19.59#ibcon#read 5, iclass 29, count 0 2006.252.07:46:19.59#ibcon#about to read 6, iclass 29, count 0 2006.252.07:46:19.59#ibcon#read 6, iclass 29, count 0 2006.252.07:46:19.59#ibcon#end of sib2, iclass 29, count 0 2006.252.07:46:19.59#ibcon#*mode == 0, iclass 29, count 0 2006.252.07:46:19.59#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.252.07:46:19.59#ibcon#[25=USB\r\n] 2006.252.07:46:19.59#ibcon#*before write, iclass 29, count 0 2006.252.07:46:19.59#ibcon#enter sib2, iclass 29, count 0 2006.252.07:46:19.59#ibcon#flushed, iclass 29, count 0 2006.252.07:46:19.59#ibcon#about to write, iclass 29, count 0 2006.252.07:46:19.59#ibcon#wrote, iclass 29, count 0 2006.252.07:46:19.59#ibcon#about to read 3, iclass 29, count 0 2006.252.07:46:19.62#ibcon#read 3, iclass 29, count 0 2006.252.07:46:19.62#ibcon#about to read 4, iclass 29, count 0 2006.252.07:46:19.62#ibcon#read 4, iclass 29, count 0 2006.252.07:46:19.62#ibcon#about to read 5, iclass 29, count 0 2006.252.07:46:19.62#ibcon#read 5, iclass 29, count 0 2006.252.07:46:19.62#ibcon#about to read 6, iclass 29, count 0 2006.252.07:46:19.62#ibcon#read 6, iclass 29, count 0 2006.252.07:46:19.62#ibcon#end of sib2, iclass 29, count 0 2006.252.07:46:19.62#ibcon#*after write, iclass 29, count 0 2006.252.07:46:19.62#ibcon#*before return 0, iclass 29, count 0 2006.252.07:46:19.62#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.252.07:46:19.62#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.252.07:46:19.62#ibcon#about to clear, iclass 29 cls_cnt 0 2006.252.07:46:19.62#ibcon#cleared, iclass 29 cls_cnt 0 2006.252.07:46:19.62$vc4f8/valo=6,772.99 2006.252.07:46:19.62#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.252.07:46:19.62#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.252.07:46:19.62#ibcon#ireg 17 cls_cnt 0 2006.252.07:46:19.62#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.252.07:46:19.62#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.252.07:46:19.62#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.252.07:46:19.62#ibcon#enter wrdev, iclass 31, count 0 2006.252.07:46:19.62#ibcon#first serial, iclass 31, count 0 2006.252.07:46:19.62#ibcon#enter sib2, iclass 31, count 0 2006.252.07:46:19.62#ibcon#flushed, iclass 31, count 0 2006.252.07:46:19.62#ibcon#about to write, iclass 31, count 0 2006.252.07:46:19.62#ibcon#wrote, iclass 31, count 0 2006.252.07:46:19.62#ibcon#about to read 3, iclass 31, count 0 2006.252.07:46:19.64#ibcon#read 3, iclass 31, count 0 2006.252.07:46:19.64#ibcon#about to read 4, iclass 31, count 0 2006.252.07:46:19.64#ibcon#read 4, iclass 31, count 0 2006.252.07:46:19.64#ibcon#about to read 5, iclass 31, count 0 2006.252.07:46:19.64#ibcon#read 5, iclass 31, count 0 2006.252.07:46:19.64#ibcon#about to read 6, iclass 31, count 0 2006.252.07:46:19.64#ibcon#read 6, iclass 31, count 0 2006.252.07:46:19.64#ibcon#end of sib2, iclass 31, count 0 2006.252.07:46:19.64#ibcon#*mode == 0, iclass 31, count 0 2006.252.07:46:19.64#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.252.07:46:19.64#ibcon#[26=FRQ=06,772.99\r\n] 2006.252.07:46:19.64#ibcon#*before write, iclass 31, count 0 2006.252.07:46:19.64#ibcon#enter sib2, iclass 31, count 0 2006.252.07:46:19.64#ibcon#flushed, iclass 31, count 0 2006.252.07:46:19.64#ibcon#about to write, iclass 31, count 0 2006.252.07:46:19.64#ibcon#wrote, iclass 31, count 0 2006.252.07:46:19.64#ibcon#about to read 3, iclass 31, count 0 2006.252.07:46:19.68#ibcon#read 3, iclass 31, count 0 2006.252.07:46:19.68#ibcon#about to read 4, iclass 31, count 0 2006.252.07:46:19.68#ibcon#read 4, iclass 31, count 0 2006.252.07:46:19.68#ibcon#about to read 5, iclass 31, count 0 2006.252.07:46:19.68#ibcon#read 5, iclass 31, count 0 2006.252.07:46:19.68#ibcon#about to read 6, iclass 31, count 0 2006.252.07:46:19.68#ibcon#read 6, iclass 31, count 0 2006.252.07:46:19.68#ibcon#end of sib2, iclass 31, count 0 2006.252.07:46:19.68#ibcon#*after write, iclass 31, count 0 2006.252.07:46:19.68#ibcon#*before return 0, iclass 31, count 0 2006.252.07:46:19.68#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.252.07:46:19.68#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.252.07:46:19.68#ibcon#about to clear, iclass 31 cls_cnt 0 2006.252.07:46:19.68#ibcon#cleared, iclass 31 cls_cnt 0 2006.252.07:46:19.68$vc4f8/va=6,7 2006.252.07:46:19.68#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.252.07:46:19.68#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.252.07:46:19.68#ibcon#ireg 11 cls_cnt 2 2006.252.07:46:19.68#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.252.07:46:19.75#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.252.07:46:19.75#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.252.07:46:19.75#ibcon#enter wrdev, iclass 33, count 2 2006.252.07:46:19.75#ibcon#first serial, iclass 33, count 2 2006.252.07:46:19.75#ibcon#enter sib2, iclass 33, count 2 2006.252.07:46:19.75#ibcon#flushed, iclass 33, count 2 2006.252.07:46:19.75#ibcon#about to write, iclass 33, count 2 2006.252.07:46:19.75#ibcon#wrote, iclass 33, count 2 2006.252.07:46:19.75#ibcon#about to read 3, iclass 33, count 2 2006.252.07:46:19.76#ibcon#read 3, iclass 33, count 2 2006.252.07:46:19.76#ibcon#about to read 4, iclass 33, count 2 2006.252.07:46:19.76#ibcon#read 4, iclass 33, count 2 2006.252.07:46:19.76#ibcon#about to read 5, iclass 33, count 2 2006.252.07:46:19.76#ibcon#read 5, iclass 33, count 2 2006.252.07:46:19.76#ibcon#about to read 6, iclass 33, count 2 2006.252.07:46:19.76#ibcon#read 6, iclass 33, count 2 2006.252.07:46:19.76#ibcon#end of sib2, iclass 33, count 2 2006.252.07:46:19.76#ibcon#*mode == 0, iclass 33, count 2 2006.252.07:46:19.76#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.252.07:46:19.76#ibcon#[25=AT06-07\r\n] 2006.252.07:46:19.76#ibcon#*before write, iclass 33, count 2 2006.252.07:46:19.76#ibcon#enter sib2, iclass 33, count 2 2006.252.07:46:19.76#ibcon#flushed, iclass 33, count 2 2006.252.07:46:19.76#ibcon#about to write, iclass 33, count 2 2006.252.07:46:19.76#ibcon#wrote, iclass 33, count 2 2006.252.07:46:19.76#ibcon#about to read 3, iclass 33, count 2 2006.252.07:46:19.79#ibcon#read 3, iclass 33, count 2 2006.252.07:46:19.79#ibcon#about to read 4, iclass 33, count 2 2006.252.07:46:19.79#ibcon#read 4, iclass 33, count 2 2006.252.07:46:19.79#ibcon#about to read 5, iclass 33, count 2 2006.252.07:46:19.79#ibcon#read 5, iclass 33, count 2 2006.252.07:46:19.79#ibcon#about to read 6, iclass 33, count 2 2006.252.07:46:19.79#ibcon#read 6, iclass 33, count 2 2006.252.07:46:19.79#ibcon#end of sib2, iclass 33, count 2 2006.252.07:46:19.79#ibcon#*after write, iclass 33, count 2 2006.252.07:46:19.79#ibcon#*before return 0, iclass 33, count 2 2006.252.07:46:19.79#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.252.07:46:19.79#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.252.07:46:19.79#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.252.07:46:19.79#ibcon#ireg 7 cls_cnt 0 2006.252.07:46:19.79#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.252.07:46:19.91#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.252.07:46:19.91#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.252.07:46:19.91#ibcon#enter wrdev, iclass 33, count 0 2006.252.07:46:19.91#ibcon#first serial, iclass 33, count 0 2006.252.07:46:19.91#ibcon#enter sib2, iclass 33, count 0 2006.252.07:46:19.91#ibcon#flushed, iclass 33, count 0 2006.252.07:46:19.91#ibcon#about to write, iclass 33, count 0 2006.252.07:46:19.91#ibcon#wrote, iclass 33, count 0 2006.252.07:46:19.91#ibcon#about to read 3, iclass 33, count 0 2006.252.07:46:19.93#ibcon#read 3, iclass 33, count 0 2006.252.07:46:19.93#ibcon#about to read 4, iclass 33, count 0 2006.252.07:46:19.93#ibcon#read 4, iclass 33, count 0 2006.252.07:46:19.93#ibcon#about to read 5, iclass 33, count 0 2006.252.07:46:19.93#ibcon#read 5, iclass 33, count 0 2006.252.07:46:19.93#ibcon#about to read 6, iclass 33, count 0 2006.252.07:46:19.93#ibcon#read 6, iclass 33, count 0 2006.252.07:46:19.93#ibcon#end of sib2, iclass 33, count 0 2006.252.07:46:19.93#ibcon#*mode == 0, iclass 33, count 0 2006.252.07:46:19.93#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.252.07:46:19.93#ibcon#[25=USB\r\n] 2006.252.07:46:19.93#ibcon#*before write, iclass 33, count 0 2006.252.07:46:19.93#ibcon#enter sib2, iclass 33, count 0 2006.252.07:46:19.93#ibcon#flushed, iclass 33, count 0 2006.252.07:46:19.93#ibcon#about to write, iclass 33, count 0 2006.252.07:46:19.93#ibcon#wrote, iclass 33, count 0 2006.252.07:46:19.93#ibcon#about to read 3, iclass 33, count 0 2006.252.07:46:19.96#ibcon#read 3, iclass 33, count 0 2006.252.07:46:19.96#ibcon#about to read 4, iclass 33, count 0 2006.252.07:46:19.96#ibcon#read 4, iclass 33, count 0 2006.252.07:46:19.96#ibcon#about to read 5, iclass 33, count 0 2006.252.07:46:19.96#ibcon#read 5, iclass 33, count 0 2006.252.07:46:19.96#ibcon#about to read 6, iclass 33, count 0 2006.252.07:46:19.96#ibcon#read 6, iclass 33, count 0 2006.252.07:46:19.96#ibcon#end of sib2, iclass 33, count 0 2006.252.07:46:19.96#ibcon#*after write, iclass 33, count 0 2006.252.07:46:19.96#ibcon#*before return 0, iclass 33, count 0 2006.252.07:46:19.96#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.252.07:46:19.96#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.252.07:46:19.96#ibcon#about to clear, iclass 33 cls_cnt 0 2006.252.07:46:19.96#ibcon#cleared, iclass 33 cls_cnt 0 2006.252.07:46:19.96$vc4f8/valo=7,832.99 2006.252.07:46:19.96#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.252.07:46:19.96#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.252.07:46:19.96#ibcon#ireg 17 cls_cnt 0 2006.252.07:46:19.96#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.252.07:46:19.96#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.252.07:46:19.96#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.252.07:46:19.96#ibcon#enter wrdev, iclass 35, count 0 2006.252.07:46:19.96#ibcon#first serial, iclass 35, count 0 2006.252.07:46:19.96#ibcon#enter sib2, iclass 35, count 0 2006.252.07:46:19.96#ibcon#flushed, iclass 35, count 0 2006.252.07:46:19.96#ibcon#about to write, iclass 35, count 0 2006.252.07:46:19.96#ibcon#wrote, iclass 35, count 0 2006.252.07:46:19.96#ibcon#about to read 3, iclass 35, count 0 2006.252.07:46:19.98#ibcon#read 3, iclass 35, count 0 2006.252.07:46:19.98#ibcon#about to read 4, iclass 35, count 0 2006.252.07:46:19.98#ibcon#read 4, iclass 35, count 0 2006.252.07:46:19.98#ibcon#about to read 5, iclass 35, count 0 2006.252.07:46:19.98#ibcon#read 5, iclass 35, count 0 2006.252.07:46:19.98#ibcon#about to read 6, iclass 35, count 0 2006.252.07:46:19.98#ibcon#read 6, iclass 35, count 0 2006.252.07:46:19.98#ibcon#end of sib2, iclass 35, count 0 2006.252.07:46:19.98#ibcon#*mode == 0, iclass 35, count 0 2006.252.07:46:19.98#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.252.07:46:19.98#ibcon#[26=FRQ=07,832.99\r\n] 2006.252.07:46:19.98#ibcon#*before write, iclass 35, count 0 2006.252.07:46:19.98#ibcon#enter sib2, iclass 35, count 0 2006.252.07:46:19.98#ibcon#flushed, iclass 35, count 0 2006.252.07:46:19.98#ibcon#about to write, iclass 35, count 0 2006.252.07:46:19.98#ibcon#wrote, iclass 35, count 0 2006.252.07:46:19.98#ibcon#about to read 3, iclass 35, count 0 2006.252.07:46:20.02#ibcon#read 3, iclass 35, count 0 2006.252.07:46:20.02#ibcon#about to read 4, iclass 35, count 0 2006.252.07:46:20.02#ibcon#read 4, iclass 35, count 0 2006.252.07:46:20.02#ibcon#about to read 5, iclass 35, count 0 2006.252.07:46:20.02#ibcon#read 5, iclass 35, count 0 2006.252.07:46:20.02#ibcon#about to read 6, iclass 35, count 0 2006.252.07:46:20.02#ibcon#read 6, iclass 35, count 0 2006.252.07:46:20.02#ibcon#end of sib2, iclass 35, count 0 2006.252.07:46:20.02#ibcon#*after write, iclass 35, count 0 2006.252.07:46:20.02#ibcon#*before return 0, iclass 35, count 0 2006.252.07:46:20.02#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.252.07:46:20.02#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.252.07:46:20.02#ibcon#about to clear, iclass 35 cls_cnt 0 2006.252.07:46:20.02#ibcon#cleared, iclass 35 cls_cnt 0 2006.252.07:46:20.02$vc4f8/va=7,7 2006.252.07:46:20.02#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.252.07:46:20.02#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.252.07:46:20.02#ibcon#ireg 11 cls_cnt 2 2006.252.07:46:20.02#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.252.07:46:20.08#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.252.07:46:20.08#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.252.07:46:20.08#ibcon#enter wrdev, iclass 37, count 2 2006.252.07:46:20.08#ibcon#first serial, iclass 37, count 2 2006.252.07:46:20.08#ibcon#enter sib2, iclass 37, count 2 2006.252.07:46:20.08#ibcon#flushed, iclass 37, count 2 2006.252.07:46:20.08#ibcon#about to write, iclass 37, count 2 2006.252.07:46:20.08#ibcon#wrote, iclass 37, count 2 2006.252.07:46:20.08#ibcon#about to read 3, iclass 37, count 2 2006.252.07:46:20.10#ibcon#read 3, iclass 37, count 2 2006.252.07:46:20.10#ibcon#about to read 4, iclass 37, count 2 2006.252.07:46:20.10#ibcon#read 4, iclass 37, count 2 2006.252.07:46:20.10#ibcon#about to read 5, iclass 37, count 2 2006.252.07:46:20.10#ibcon#read 5, iclass 37, count 2 2006.252.07:46:20.10#ibcon#about to read 6, iclass 37, count 2 2006.252.07:46:20.10#ibcon#read 6, iclass 37, count 2 2006.252.07:46:20.10#ibcon#end of sib2, iclass 37, count 2 2006.252.07:46:20.10#ibcon#*mode == 0, iclass 37, count 2 2006.252.07:46:20.10#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.252.07:46:20.10#ibcon#[25=AT07-07\r\n] 2006.252.07:46:20.10#ibcon#*before write, iclass 37, count 2 2006.252.07:46:20.10#ibcon#enter sib2, iclass 37, count 2 2006.252.07:46:20.10#ibcon#flushed, iclass 37, count 2 2006.252.07:46:20.10#ibcon#about to write, iclass 37, count 2 2006.252.07:46:20.10#ibcon#wrote, iclass 37, count 2 2006.252.07:46:20.10#ibcon#about to read 3, iclass 37, count 2 2006.252.07:46:20.13#ibcon#read 3, iclass 37, count 2 2006.252.07:46:20.13#ibcon#about to read 4, iclass 37, count 2 2006.252.07:46:20.13#ibcon#read 4, iclass 37, count 2 2006.252.07:46:20.13#ibcon#about to read 5, iclass 37, count 2 2006.252.07:46:20.13#ibcon#read 5, iclass 37, count 2 2006.252.07:46:20.13#ibcon#about to read 6, iclass 37, count 2 2006.252.07:46:20.13#ibcon#read 6, iclass 37, count 2 2006.252.07:46:20.13#ibcon#end of sib2, iclass 37, count 2 2006.252.07:46:20.13#ibcon#*after write, iclass 37, count 2 2006.252.07:46:20.13#ibcon#*before return 0, iclass 37, count 2 2006.252.07:46:20.13#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.252.07:46:20.13#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.252.07:46:20.13#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.252.07:46:20.13#ibcon#ireg 7 cls_cnt 0 2006.252.07:46:20.13#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.252.07:46:20.25#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.252.07:46:20.25#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.252.07:46:20.25#ibcon#enter wrdev, iclass 37, count 0 2006.252.07:46:20.25#ibcon#first serial, iclass 37, count 0 2006.252.07:46:20.25#ibcon#enter sib2, iclass 37, count 0 2006.252.07:46:20.25#ibcon#flushed, iclass 37, count 0 2006.252.07:46:20.25#ibcon#about to write, iclass 37, count 0 2006.252.07:46:20.25#ibcon#wrote, iclass 37, count 0 2006.252.07:46:20.25#ibcon#about to read 3, iclass 37, count 0 2006.252.07:46:20.27#ibcon#read 3, iclass 37, count 0 2006.252.07:46:20.27#ibcon#about to read 4, iclass 37, count 0 2006.252.07:46:20.27#ibcon#read 4, iclass 37, count 0 2006.252.07:46:20.27#ibcon#about to read 5, iclass 37, count 0 2006.252.07:46:20.27#ibcon#read 5, iclass 37, count 0 2006.252.07:46:20.27#ibcon#about to read 6, iclass 37, count 0 2006.252.07:46:20.27#ibcon#read 6, iclass 37, count 0 2006.252.07:46:20.27#ibcon#end of sib2, iclass 37, count 0 2006.252.07:46:20.27#ibcon#*mode == 0, iclass 37, count 0 2006.252.07:46:20.27#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.252.07:46:20.27#ibcon#[25=USB\r\n] 2006.252.07:46:20.27#ibcon#*before write, iclass 37, count 0 2006.252.07:46:20.27#ibcon#enter sib2, iclass 37, count 0 2006.252.07:46:20.27#ibcon#flushed, iclass 37, count 0 2006.252.07:46:20.27#ibcon#about to write, iclass 37, count 0 2006.252.07:46:20.27#ibcon#wrote, iclass 37, count 0 2006.252.07:46:20.27#ibcon#about to read 3, iclass 37, count 0 2006.252.07:46:20.30#ibcon#read 3, iclass 37, count 0 2006.252.07:46:20.30#ibcon#about to read 4, iclass 37, count 0 2006.252.07:46:20.30#ibcon#read 4, iclass 37, count 0 2006.252.07:46:20.30#ibcon#about to read 5, iclass 37, count 0 2006.252.07:46:20.30#ibcon#read 5, iclass 37, count 0 2006.252.07:46:20.30#ibcon#about to read 6, iclass 37, count 0 2006.252.07:46:20.30#ibcon#read 6, iclass 37, count 0 2006.252.07:46:20.30#ibcon#end of sib2, iclass 37, count 0 2006.252.07:46:20.30#ibcon#*after write, iclass 37, count 0 2006.252.07:46:20.30#ibcon#*before return 0, iclass 37, count 0 2006.252.07:46:20.30#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.252.07:46:20.30#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.252.07:46:20.30#ibcon#about to clear, iclass 37 cls_cnt 0 2006.252.07:46:20.30#ibcon#cleared, iclass 37 cls_cnt 0 2006.252.07:46:20.30$vc4f8/valo=8,852.99 2006.252.07:46:20.30#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.252.07:46:20.30#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.252.07:46:20.30#ibcon#ireg 17 cls_cnt 0 2006.252.07:46:20.30#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.252.07:46:20.30#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.252.07:46:20.30#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.252.07:46:20.30#ibcon#enter wrdev, iclass 39, count 0 2006.252.07:46:20.30#ibcon#first serial, iclass 39, count 0 2006.252.07:46:20.30#ibcon#enter sib2, iclass 39, count 0 2006.252.07:46:20.30#ibcon#flushed, iclass 39, count 0 2006.252.07:46:20.30#ibcon#about to write, iclass 39, count 0 2006.252.07:46:20.30#ibcon#wrote, iclass 39, count 0 2006.252.07:46:20.30#ibcon#about to read 3, iclass 39, count 0 2006.252.07:46:20.32#ibcon#read 3, iclass 39, count 0 2006.252.07:46:20.32#ibcon#about to read 4, iclass 39, count 0 2006.252.07:46:20.32#ibcon#read 4, iclass 39, count 0 2006.252.07:46:20.32#ibcon#about to read 5, iclass 39, count 0 2006.252.07:46:20.32#ibcon#read 5, iclass 39, count 0 2006.252.07:46:20.32#ibcon#about to read 6, iclass 39, count 0 2006.252.07:46:20.32#ibcon#read 6, iclass 39, count 0 2006.252.07:46:20.32#ibcon#end of sib2, iclass 39, count 0 2006.252.07:46:20.32#ibcon#*mode == 0, iclass 39, count 0 2006.252.07:46:20.32#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.252.07:46:20.32#ibcon#[26=FRQ=08,852.99\r\n] 2006.252.07:46:20.32#ibcon#*before write, iclass 39, count 0 2006.252.07:46:20.32#ibcon#enter sib2, iclass 39, count 0 2006.252.07:46:20.32#ibcon#flushed, iclass 39, count 0 2006.252.07:46:20.32#ibcon#about to write, iclass 39, count 0 2006.252.07:46:20.32#ibcon#wrote, iclass 39, count 0 2006.252.07:46:20.32#ibcon#about to read 3, iclass 39, count 0 2006.252.07:46:20.36#ibcon#read 3, iclass 39, count 0 2006.252.07:46:20.36#ibcon#about to read 4, iclass 39, count 0 2006.252.07:46:20.36#ibcon#read 4, iclass 39, count 0 2006.252.07:46:20.36#ibcon#about to read 5, iclass 39, count 0 2006.252.07:46:20.36#ibcon#read 5, iclass 39, count 0 2006.252.07:46:20.36#ibcon#about to read 6, iclass 39, count 0 2006.252.07:46:20.36#ibcon#read 6, iclass 39, count 0 2006.252.07:46:20.36#ibcon#end of sib2, iclass 39, count 0 2006.252.07:46:20.36#ibcon#*after write, iclass 39, count 0 2006.252.07:46:20.36#ibcon#*before return 0, iclass 39, count 0 2006.252.07:46:20.36#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.252.07:46:20.36#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.252.07:46:20.36#ibcon#about to clear, iclass 39 cls_cnt 0 2006.252.07:46:20.36#ibcon#cleared, iclass 39 cls_cnt 0 2006.252.07:46:20.36$vc4f8/va=8,7 2006.252.07:46:20.36#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.252.07:46:20.36#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.252.07:46:20.36#ibcon#ireg 11 cls_cnt 2 2006.252.07:46:20.36#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.252.07:46:20.43#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.252.07:46:20.43#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.252.07:46:20.43#ibcon#enter wrdev, iclass 3, count 2 2006.252.07:46:20.43#ibcon#first serial, iclass 3, count 2 2006.252.07:46:20.43#ibcon#enter sib2, iclass 3, count 2 2006.252.07:46:20.43#ibcon#flushed, iclass 3, count 2 2006.252.07:46:20.43#ibcon#about to write, iclass 3, count 2 2006.252.07:46:20.43#ibcon#wrote, iclass 3, count 2 2006.252.07:46:20.43#ibcon#about to read 3, iclass 3, count 2 2006.252.07:46:20.44#ibcon#read 3, iclass 3, count 2 2006.252.07:46:20.44#ibcon#about to read 4, iclass 3, count 2 2006.252.07:46:20.44#ibcon#read 4, iclass 3, count 2 2006.252.07:46:20.44#ibcon#about to read 5, iclass 3, count 2 2006.252.07:46:20.44#ibcon#read 5, iclass 3, count 2 2006.252.07:46:20.44#ibcon#about to read 6, iclass 3, count 2 2006.252.07:46:20.44#ibcon#read 6, iclass 3, count 2 2006.252.07:46:20.44#ibcon#end of sib2, iclass 3, count 2 2006.252.07:46:20.44#ibcon#*mode == 0, iclass 3, count 2 2006.252.07:46:20.44#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.252.07:46:20.44#ibcon#[25=AT08-07\r\n] 2006.252.07:46:20.44#ibcon#*before write, iclass 3, count 2 2006.252.07:46:20.44#ibcon#enter sib2, iclass 3, count 2 2006.252.07:46:20.44#ibcon#flushed, iclass 3, count 2 2006.252.07:46:20.44#ibcon#about to write, iclass 3, count 2 2006.252.07:46:20.44#ibcon#wrote, iclass 3, count 2 2006.252.07:46:20.44#ibcon#about to read 3, iclass 3, count 2 2006.252.07:46:20.47#ibcon#read 3, iclass 3, count 2 2006.252.07:46:20.47#ibcon#about to read 4, iclass 3, count 2 2006.252.07:46:20.47#ibcon#read 4, iclass 3, count 2 2006.252.07:46:20.47#ibcon#about to read 5, iclass 3, count 2 2006.252.07:46:20.47#ibcon#read 5, iclass 3, count 2 2006.252.07:46:20.47#ibcon#about to read 6, iclass 3, count 2 2006.252.07:46:20.47#ibcon#read 6, iclass 3, count 2 2006.252.07:46:20.47#ibcon#end of sib2, iclass 3, count 2 2006.252.07:46:20.47#ibcon#*after write, iclass 3, count 2 2006.252.07:46:20.47#ibcon#*before return 0, iclass 3, count 2 2006.252.07:46:20.47#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.252.07:46:20.47#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.252.07:46:20.47#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.252.07:46:20.47#ibcon#ireg 7 cls_cnt 0 2006.252.07:46:20.47#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.252.07:46:20.59#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.252.07:46:20.59#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.252.07:46:20.59#ibcon#enter wrdev, iclass 3, count 0 2006.252.07:46:20.59#ibcon#first serial, iclass 3, count 0 2006.252.07:46:20.59#ibcon#enter sib2, iclass 3, count 0 2006.252.07:46:20.59#ibcon#flushed, iclass 3, count 0 2006.252.07:46:20.59#ibcon#about to write, iclass 3, count 0 2006.252.07:46:20.59#ibcon#wrote, iclass 3, count 0 2006.252.07:46:20.59#ibcon#about to read 3, iclass 3, count 0 2006.252.07:46:20.61#ibcon#read 3, iclass 3, count 0 2006.252.07:46:20.61#ibcon#about to read 4, iclass 3, count 0 2006.252.07:46:20.61#ibcon#read 4, iclass 3, count 0 2006.252.07:46:20.61#ibcon#about to read 5, iclass 3, count 0 2006.252.07:46:20.61#ibcon#read 5, iclass 3, count 0 2006.252.07:46:20.61#ibcon#about to read 6, iclass 3, count 0 2006.252.07:46:20.61#ibcon#read 6, iclass 3, count 0 2006.252.07:46:20.61#ibcon#end of sib2, iclass 3, count 0 2006.252.07:46:20.61#ibcon#*mode == 0, iclass 3, count 0 2006.252.07:46:20.61#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.252.07:46:20.61#ibcon#[25=USB\r\n] 2006.252.07:46:20.61#ibcon#*before write, iclass 3, count 0 2006.252.07:46:20.61#ibcon#enter sib2, iclass 3, count 0 2006.252.07:46:20.61#ibcon#flushed, iclass 3, count 0 2006.252.07:46:20.61#ibcon#about to write, iclass 3, count 0 2006.252.07:46:20.61#ibcon#wrote, iclass 3, count 0 2006.252.07:46:20.61#ibcon#about to read 3, iclass 3, count 0 2006.252.07:46:20.64#ibcon#read 3, iclass 3, count 0 2006.252.07:46:20.64#ibcon#about to read 4, iclass 3, count 0 2006.252.07:46:20.64#ibcon#read 4, iclass 3, count 0 2006.252.07:46:20.64#ibcon#about to read 5, iclass 3, count 0 2006.252.07:46:20.64#ibcon#read 5, iclass 3, count 0 2006.252.07:46:20.64#ibcon#about to read 6, iclass 3, count 0 2006.252.07:46:20.64#ibcon#read 6, iclass 3, count 0 2006.252.07:46:20.64#ibcon#end of sib2, iclass 3, count 0 2006.252.07:46:20.64#ibcon#*after write, iclass 3, count 0 2006.252.07:46:20.64#ibcon#*before return 0, iclass 3, count 0 2006.252.07:46:20.64#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.252.07:46:20.64#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.252.07:46:20.64#ibcon#about to clear, iclass 3 cls_cnt 0 2006.252.07:46:20.64#ibcon#cleared, iclass 3 cls_cnt 0 2006.252.07:46:20.64$vc4f8/vblo=1,632.99 2006.252.07:46:20.64#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.252.07:46:20.64#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.252.07:46:20.64#ibcon#ireg 17 cls_cnt 0 2006.252.07:46:20.64#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.252.07:46:20.64#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.252.07:46:20.64#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.252.07:46:20.64#ibcon#enter wrdev, iclass 5, count 0 2006.252.07:46:20.64#ibcon#first serial, iclass 5, count 0 2006.252.07:46:20.64#ibcon#enter sib2, iclass 5, count 0 2006.252.07:46:20.64#ibcon#flushed, iclass 5, count 0 2006.252.07:46:20.64#ibcon#about to write, iclass 5, count 0 2006.252.07:46:20.64#ibcon#wrote, iclass 5, count 0 2006.252.07:46:20.64#ibcon#about to read 3, iclass 5, count 0 2006.252.07:46:20.66#ibcon#read 3, iclass 5, count 0 2006.252.07:46:20.66#ibcon#about to read 4, iclass 5, count 0 2006.252.07:46:20.66#ibcon#read 4, iclass 5, count 0 2006.252.07:46:20.66#ibcon#about to read 5, iclass 5, count 0 2006.252.07:46:20.66#ibcon#read 5, iclass 5, count 0 2006.252.07:46:20.66#ibcon#about to read 6, iclass 5, count 0 2006.252.07:46:20.66#ibcon#read 6, iclass 5, count 0 2006.252.07:46:20.66#ibcon#end of sib2, iclass 5, count 0 2006.252.07:46:20.66#ibcon#*mode == 0, iclass 5, count 0 2006.252.07:46:20.66#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.252.07:46:20.66#ibcon#[28=FRQ=01,632.99\r\n] 2006.252.07:46:20.66#ibcon#*before write, iclass 5, count 0 2006.252.07:46:20.66#ibcon#enter sib2, iclass 5, count 0 2006.252.07:46:20.66#ibcon#flushed, iclass 5, count 0 2006.252.07:46:20.66#ibcon#about to write, iclass 5, count 0 2006.252.07:46:20.66#ibcon#wrote, iclass 5, count 0 2006.252.07:46:20.66#ibcon#about to read 3, iclass 5, count 0 2006.252.07:46:20.70#ibcon#read 3, iclass 5, count 0 2006.252.07:46:20.70#ibcon#about to read 4, iclass 5, count 0 2006.252.07:46:20.70#ibcon#read 4, iclass 5, count 0 2006.252.07:46:20.70#ibcon#about to read 5, iclass 5, count 0 2006.252.07:46:20.70#ibcon#read 5, iclass 5, count 0 2006.252.07:46:20.70#ibcon#about to read 6, iclass 5, count 0 2006.252.07:46:20.70#ibcon#read 6, iclass 5, count 0 2006.252.07:46:20.70#ibcon#end of sib2, iclass 5, count 0 2006.252.07:46:20.70#ibcon#*after write, iclass 5, count 0 2006.252.07:46:20.70#ibcon#*before return 0, iclass 5, count 0 2006.252.07:46:20.70#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.252.07:46:20.70#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.252.07:46:20.70#ibcon#about to clear, iclass 5 cls_cnt 0 2006.252.07:46:20.70#ibcon#cleared, iclass 5 cls_cnt 0 2006.252.07:46:20.70$vc4f8/vb=1,4 2006.252.07:46:20.70#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.252.07:46:20.70#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.252.07:46:20.70#ibcon#ireg 11 cls_cnt 2 2006.252.07:46:20.70#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.252.07:46:20.70#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.252.07:46:20.70#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.252.07:46:20.70#ibcon#enter wrdev, iclass 7, count 2 2006.252.07:46:20.70#ibcon#first serial, iclass 7, count 2 2006.252.07:46:20.70#ibcon#enter sib2, iclass 7, count 2 2006.252.07:46:20.70#ibcon#flushed, iclass 7, count 2 2006.252.07:46:20.70#ibcon#about to write, iclass 7, count 2 2006.252.07:46:20.70#ibcon#wrote, iclass 7, count 2 2006.252.07:46:20.70#ibcon#about to read 3, iclass 7, count 2 2006.252.07:46:20.72#ibcon#read 3, iclass 7, count 2 2006.252.07:46:20.72#ibcon#about to read 4, iclass 7, count 2 2006.252.07:46:20.72#ibcon#read 4, iclass 7, count 2 2006.252.07:46:20.72#ibcon#about to read 5, iclass 7, count 2 2006.252.07:46:20.72#ibcon#read 5, iclass 7, count 2 2006.252.07:46:20.72#ibcon#about to read 6, iclass 7, count 2 2006.252.07:46:20.72#ibcon#read 6, iclass 7, count 2 2006.252.07:46:20.72#ibcon#end of sib2, iclass 7, count 2 2006.252.07:46:20.72#ibcon#*mode == 0, iclass 7, count 2 2006.252.07:46:20.72#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.252.07:46:20.72#ibcon#[27=AT01-04\r\n] 2006.252.07:46:20.72#ibcon#*before write, iclass 7, count 2 2006.252.07:46:20.72#ibcon#enter sib2, iclass 7, count 2 2006.252.07:46:20.72#ibcon#flushed, iclass 7, count 2 2006.252.07:46:20.72#ibcon#about to write, iclass 7, count 2 2006.252.07:46:20.72#ibcon#wrote, iclass 7, count 2 2006.252.07:46:20.72#ibcon#about to read 3, iclass 7, count 2 2006.252.07:46:20.75#ibcon#read 3, iclass 7, count 2 2006.252.07:46:20.75#ibcon#about to read 4, iclass 7, count 2 2006.252.07:46:20.75#ibcon#read 4, iclass 7, count 2 2006.252.07:46:20.75#ibcon#about to read 5, iclass 7, count 2 2006.252.07:46:20.75#ibcon#read 5, iclass 7, count 2 2006.252.07:46:20.75#ibcon#about to read 6, iclass 7, count 2 2006.252.07:46:20.75#ibcon#read 6, iclass 7, count 2 2006.252.07:46:20.75#ibcon#end of sib2, iclass 7, count 2 2006.252.07:46:20.75#ibcon#*after write, iclass 7, count 2 2006.252.07:46:20.75#ibcon#*before return 0, iclass 7, count 2 2006.252.07:46:20.75#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.252.07:46:20.75#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.252.07:46:20.75#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.252.07:46:20.75#ibcon#ireg 7 cls_cnt 0 2006.252.07:46:20.75#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.252.07:46:20.87#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.252.07:46:20.87#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.252.07:46:20.87#ibcon#enter wrdev, iclass 7, count 0 2006.252.07:46:20.87#ibcon#first serial, iclass 7, count 0 2006.252.07:46:20.87#ibcon#enter sib2, iclass 7, count 0 2006.252.07:46:20.87#ibcon#flushed, iclass 7, count 0 2006.252.07:46:20.87#ibcon#about to write, iclass 7, count 0 2006.252.07:46:20.87#ibcon#wrote, iclass 7, count 0 2006.252.07:46:20.87#ibcon#about to read 3, iclass 7, count 0 2006.252.07:46:20.89#ibcon#read 3, iclass 7, count 0 2006.252.07:46:20.89#ibcon#about to read 4, iclass 7, count 0 2006.252.07:46:20.89#ibcon#read 4, iclass 7, count 0 2006.252.07:46:20.89#ibcon#about to read 5, iclass 7, count 0 2006.252.07:46:20.89#ibcon#read 5, iclass 7, count 0 2006.252.07:46:20.89#ibcon#about to read 6, iclass 7, count 0 2006.252.07:46:20.89#ibcon#read 6, iclass 7, count 0 2006.252.07:46:20.89#ibcon#end of sib2, iclass 7, count 0 2006.252.07:46:20.89#ibcon#*mode == 0, iclass 7, count 0 2006.252.07:46:20.89#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.252.07:46:20.89#ibcon#[27=USB\r\n] 2006.252.07:46:20.89#ibcon#*before write, iclass 7, count 0 2006.252.07:46:20.89#ibcon#enter sib2, iclass 7, count 0 2006.252.07:46:20.89#ibcon#flushed, iclass 7, count 0 2006.252.07:46:20.89#ibcon#about to write, iclass 7, count 0 2006.252.07:46:20.89#ibcon#wrote, iclass 7, count 0 2006.252.07:46:20.89#ibcon#about to read 3, iclass 7, count 0 2006.252.07:46:20.92#ibcon#read 3, iclass 7, count 0 2006.252.07:46:20.92#ibcon#about to read 4, iclass 7, count 0 2006.252.07:46:20.92#ibcon#read 4, iclass 7, count 0 2006.252.07:46:20.92#ibcon#about to read 5, iclass 7, count 0 2006.252.07:46:20.92#ibcon#read 5, iclass 7, count 0 2006.252.07:46:20.92#ibcon#about to read 6, iclass 7, count 0 2006.252.07:46:20.92#ibcon#read 6, iclass 7, count 0 2006.252.07:46:20.92#ibcon#end of sib2, iclass 7, count 0 2006.252.07:46:20.92#ibcon#*after write, iclass 7, count 0 2006.252.07:46:20.92#ibcon#*before return 0, iclass 7, count 0 2006.252.07:46:20.92#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.252.07:46:20.92#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.252.07:46:20.92#ibcon#about to clear, iclass 7 cls_cnt 0 2006.252.07:46:20.92#ibcon#cleared, iclass 7 cls_cnt 0 2006.252.07:46:20.92$vc4f8/vblo=2,640.99 2006.252.07:46:20.92#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.252.07:46:20.92#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.252.07:46:20.92#ibcon#ireg 17 cls_cnt 0 2006.252.07:46:20.92#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.252.07:46:20.92#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.252.07:46:20.92#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.252.07:46:20.92#ibcon#enter wrdev, iclass 11, count 0 2006.252.07:46:20.92#ibcon#first serial, iclass 11, count 0 2006.252.07:46:20.92#ibcon#enter sib2, iclass 11, count 0 2006.252.07:46:20.92#ibcon#flushed, iclass 11, count 0 2006.252.07:46:20.92#ibcon#about to write, iclass 11, count 0 2006.252.07:46:20.92#ibcon#wrote, iclass 11, count 0 2006.252.07:46:20.92#ibcon#about to read 3, iclass 11, count 0 2006.252.07:46:20.94#ibcon#read 3, iclass 11, count 0 2006.252.07:46:20.94#ibcon#about to read 4, iclass 11, count 0 2006.252.07:46:20.94#ibcon#read 4, iclass 11, count 0 2006.252.07:46:20.94#ibcon#about to read 5, iclass 11, count 0 2006.252.07:46:20.94#ibcon#read 5, iclass 11, count 0 2006.252.07:46:20.94#ibcon#about to read 6, iclass 11, count 0 2006.252.07:46:20.94#ibcon#read 6, iclass 11, count 0 2006.252.07:46:20.94#ibcon#end of sib2, iclass 11, count 0 2006.252.07:46:20.94#ibcon#*mode == 0, iclass 11, count 0 2006.252.07:46:20.94#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.252.07:46:20.94#ibcon#[28=FRQ=02,640.99\r\n] 2006.252.07:46:20.94#ibcon#*before write, iclass 11, count 0 2006.252.07:46:20.94#ibcon#enter sib2, iclass 11, count 0 2006.252.07:46:20.94#ibcon#flushed, iclass 11, count 0 2006.252.07:46:20.94#ibcon#about to write, iclass 11, count 0 2006.252.07:46:20.94#ibcon#wrote, iclass 11, count 0 2006.252.07:46:20.94#ibcon#about to read 3, iclass 11, count 0 2006.252.07:46:20.98#ibcon#read 3, iclass 11, count 0 2006.252.07:46:20.98#ibcon#about to read 4, iclass 11, count 0 2006.252.07:46:20.98#ibcon#read 4, iclass 11, count 0 2006.252.07:46:20.98#ibcon#about to read 5, iclass 11, count 0 2006.252.07:46:20.98#ibcon#read 5, iclass 11, count 0 2006.252.07:46:20.98#ibcon#about to read 6, iclass 11, count 0 2006.252.07:46:20.98#ibcon#read 6, iclass 11, count 0 2006.252.07:46:20.98#ibcon#end of sib2, iclass 11, count 0 2006.252.07:46:20.98#ibcon#*after write, iclass 11, count 0 2006.252.07:46:20.98#ibcon#*before return 0, iclass 11, count 0 2006.252.07:46:20.98#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.252.07:46:20.98#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.252.07:46:20.98#ibcon#about to clear, iclass 11 cls_cnt 0 2006.252.07:46:20.98#ibcon#cleared, iclass 11 cls_cnt 0 2006.252.07:46:20.98$vc4f8/vb=2,5 2006.252.07:46:20.98#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.252.07:46:20.98#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.252.07:46:20.98#ibcon#ireg 11 cls_cnt 2 2006.252.07:46:20.98#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.252.07:46:21.04#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.252.07:46:21.04#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.252.07:46:21.04#ibcon#enter wrdev, iclass 13, count 2 2006.252.07:46:21.04#ibcon#first serial, iclass 13, count 2 2006.252.07:46:21.04#ibcon#enter sib2, iclass 13, count 2 2006.252.07:46:21.04#ibcon#flushed, iclass 13, count 2 2006.252.07:46:21.04#ibcon#about to write, iclass 13, count 2 2006.252.07:46:21.04#ibcon#wrote, iclass 13, count 2 2006.252.07:46:21.04#ibcon#about to read 3, iclass 13, count 2 2006.252.07:46:21.06#ibcon#read 3, iclass 13, count 2 2006.252.07:46:21.06#ibcon#about to read 4, iclass 13, count 2 2006.252.07:46:21.06#ibcon#read 4, iclass 13, count 2 2006.252.07:46:21.06#ibcon#about to read 5, iclass 13, count 2 2006.252.07:46:21.06#ibcon#read 5, iclass 13, count 2 2006.252.07:46:21.06#ibcon#about to read 6, iclass 13, count 2 2006.252.07:46:21.06#ibcon#read 6, iclass 13, count 2 2006.252.07:46:21.06#ibcon#end of sib2, iclass 13, count 2 2006.252.07:46:21.06#ibcon#*mode == 0, iclass 13, count 2 2006.252.07:46:21.06#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.252.07:46:21.06#ibcon#[27=AT02-05\r\n] 2006.252.07:46:21.06#ibcon#*before write, iclass 13, count 2 2006.252.07:46:21.06#ibcon#enter sib2, iclass 13, count 2 2006.252.07:46:21.06#ibcon#flushed, iclass 13, count 2 2006.252.07:46:21.06#ibcon#about to write, iclass 13, count 2 2006.252.07:46:21.06#ibcon#wrote, iclass 13, count 2 2006.252.07:46:21.06#ibcon#about to read 3, iclass 13, count 2 2006.252.07:46:21.09#ibcon#read 3, iclass 13, count 2 2006.252.07:46:21.09#ibcon#about to read 4, iclass 13, count 2 2006.252.07:46:21.09#ibcon#read 4, iclass 13, count 2 2006.252.07:46:21.09#ibcon#about to read 5, iclass 13, count 2 2006.252.07:46:21.09#ibcon#read 5, iclass 13, count 2 2006.252.07:46:21.09#ibcon#about to read 6, iclass 13, count 2 2006.252.07:46:21.09#ibcon#read 6, iclass 13, count 2 2006.252.07:46:21.09#ibcon#end of sib2, iclass 13, count 2 2006.252.07:46:21.09#ibcon#*after write, iclass 13, count 2 2006.252.07:46:21.09#ibcon#*before return 0, iclass 13, count 2 2006.252.07:46:21.09#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.252.07:46:21.09#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.252.07:46:21.09#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.252.07:46:21.09#ibcon#ireg 7 cls_cnt 0 2006.252.07:46:21.09#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.252.07:46:21.21#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.252.07:46:21.21#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.252.07:46:21.21#ibcon#enter wrdev, iclass 13, count 0 2006.252.07:46:21.21#ibcon#first serial, iclass 13, count 0 2006.252.07:46:21.21#ibcon#enter sib2, iclass 13, count 0 2006.252.07:46:21.21#ibcon#flushed, iclass 13, count 0 2006.252.07:46:21.21#ibcon#about to write, iclass 13, count 0 2006.252.07:46:21.21#ibcon#wrote, iclass 13, count 0 2006.252.07:46:21.21#ibcon#about to read 3, iclass 13, count 0 2006.252.07:46:21.23#ibcon#read 3, iclass 13, count 0 2006.252.07:46:21.23#ibcon#about to read 4, iclass 13, count 0 2006.252.07:46:21.23#ibcon#read 4, iclass 13, count 0 2006.252.07:46:21.23#ibcon#about to read 5, iclass 13, count 0 2006.252.07:46:21.23#ibcon#read 5, iclass 13, count 0 2006.252.07:46:21.23#ibcon#about to read 6, iclass 13, count 0 2006.252.07:46:21.23#ibcon#read 6, iclass 13, count 0 2006.252.07:46:21.23#ibcon#end of sib2, iclass 13, count 0 2006.252.07:46:21.23#ibcon#*mode == 0, iclass 13, count 0 2006.252.07:46:21.23#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.252.07:46:21.23#ibcon#[27=USB\r\n] 2006.252.07:46:21.23#ibcon#*before write, iclass 13, count 0 2006.252.07:46:21.23#ibcon#enter sib2, iclass 13, count 0 2006.252.07:46:21.23#ibcon#flushed, iclass 13, count 0 2006.252.07:46:21.23#ibcon#about to write, iclass 13, count 0 2006.252.07:46:21.23#ibcon#wrote, iclass 13, count 0 2006.252.07:46:21.23#ibcon#about to read 3, iclass 13, count 0 2006.252.07:46:21.26#ibcon#read 3, iclass 13, count 0 2006.252.07:46:21.26#ibcon#about to read 4, iclass 13, count 0 2006.252.07:46:21.26#ibcon#read 4, iclass 13, count 0 2006.252.07:46:21.26#ibcon#about to read 5, iclass 13, count 0 2006.252.07:46:21.26#ibcon#read 5, iclass 13, count 0 2006.252.07:46:21.26#ibcon#about to read 6, iclass 13, count 0 2006.252.07:46:21.26#ibcon#read 6, iclass 13, count 0 2006.252.07:46:21.26#ibcon#end of sib2, iclass 13, count 0 2006.252.07:46:21.26#ibcon#*after write, iclass 13, count 0 2006.252.07:46:21.26#ibcon#*before return 0, iclass 13, count 0 2006.252.07:46:21.26#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.252.07:46:21.26#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.252.07:46:21.26#ibcon#about to clear, iclass 13 cls_cnt 0 2006.252.07:46:21.26#ibcon#cleared, iclass 13 cls_cnt 0 2006.252.07:46:21.26$vc4f8/vblo=3,656.99 2006.252.07:46:21.26#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.252.07:46:21.26#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.252.07:46:21.26#ibcon#ireg 17 cls_cnt 0 2006.252.07:46:21.26#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.252.07:46:21.26#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.252.07:46:21.26#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.252.07:46:21.26#ibcon#enter wrdev, iclass 15, count 0 2006.252.07:46:21.26#ibcon#first serial, iclass 15, count 0 2006.252.07:46:21.26#ibcon#enter sib2, iclass 15, count 0 2006.252.07:46:21.26#ibcon#flushed, iclass 15, count 0 2006.252.07:46:21.26#ibcon#about to write, iclass 15, count 0 2006.252.07:46:21.26#ibcon#wrote, iclass 15, count 0 2006.252.07:46:21.26#ibcon#about to read 3, iclass 15, count 0 2006.252.07:46:21.28#ibcon#read 3, iclass 15, count 0 2006.252.07:46:21.28#ibcon#about to read 4, iclass 15, count 0 2006.252.07:46:21.28#ibcon#read 4, iclass 15, count 0 2006.252.07:46:21.28#ibcon#about to read 5, iclass 15, count 0 2006.252.07:46:21.28#ibcon#read 5, iclass 15, count 0 2006.252.07:46:21.28#ibcon#about to read 6, iclass 15, count 0 2006.252.07:46:21.28#ibcon#read 6, iclass 15, count 0 2006.252.07:46:21.28#ibcon#end of sib2, iclass 15, count 0 2006.252.07:46:21.28#ibcon#*mode == 0, iclass 15, count 0 2006.252.07:46:21.28#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.252.07:46:21.28#ibcon#[28=FRQ=03,656.99\r\n] 2006.252.07:46:21.28#ibcon#*before write, iclass 15, count 0 2006.252.07:46:21.28#ibcon#enter sib2, iclass 15, count 0 2006.252.07:46:21.28#ibcon#flushed, iclass 15, count 0 2006.252.07:46:21.28#ibcon#about to write, iclass 15, count 0 2006.252.07:46:21.28#ibcon#wrote, iclass 15, count 0 2006.252.07:46:21.28#ibcon#about to read 3, iclass 15, count 0 2006.252.07:46:21.32#ibcon#read 3, iclass 15, count 0 2006.252.07:46:21.32#ibcon#about to read 4, iclass 15, count 0 2006.252.07:46:21.32#ibcon#read 4, iclass 15, count 0 2006.252.07:46:21.32#ibcon#about to read 5, iclass 15, count 0 2006.252.07:46:21.32#ibcon#read 5, iclass 15, count 0 2006.252.07:46:21.32#ibcon#about to read 6, iclass 15, count 0 2006.252.07:46:21.32#ibcon#read 6, iclass 15, count 0 2006.252.07:46:21.32#ibcon#end of sib2, iclass 15, count 0 2006.252.07:46:21.32#ibcon#*after write, iclass 15, count 0 2006.252.07:46:21.32#ibcon#*before return 0, iclass 15, count 0 2006.252.07:46:21.32#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.252.07:46:21.32#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.252.07:46:21.32#ibcon#about to clear, iclass 15 cls_cnt 0 2006.252.07:46:21.32#ibcon#cleared, iclass 15 cls_cnt 0 2006.252.07:46:21.32$vc4f8/vb=3,4 2006.252.07:46:21.32#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.252.07:46:21.32#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.252.07:46:21.32#ibcon#ireg 11 cls_cnt 2 2006.252.07:46:21.32#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.252.07:46:21.38#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.252.07:46:21.38#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.252.07:46:21.38#ibcon#enter wrdev, iclass 17, count 2 2006.252.07:46:21.38#ibcon#first serial, iclass 17, count 2 2006.252.07:46:21.38#ibcon#enter sib2, iclass 17, count 2 2006.252.07:46:21.38#ibcon#flushed, iclass 17, count 2 2006.252.07:46:21.38#ibcon#about to write, iclass 17, count 2 2006.252.07:46:21.38#ibcon#wrote, iclass 17, count 2 2006.252.07:46:21.38#ibcon#about to read 3, iclass 17, count 2 2006.252.07:46:21.40#ibcon#read 3, iclass 17, count 2 2006.252.07:46:21.40#ibcon#about to read 4, iclass 17, count 2 2006.252.07:46:21.40#ibcon#read 4, iclass 17, count 2 2006.252.07:46:21.40#ibcon#about to read 5, iclass 17, count 2 2006.252.07:46:21.40#ibcon#read 5, iclass 17, count 2 2006.252.07:46:21.40#ibcon#about to read 6, iclass 17, count 2 2006.252.07:46:21.40#ibcon#read 6, iclass 17, count 2 2006.252.07:46:21.40#ibcon#end of sib2, iclass 17, count 2 2006.252.07:46:21.40#ibcon#*mode == 0, iclass 17, count 2 2006.252.07:46:21.40#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.252.07:46:21.40#ibcon#[27=AT03-04\r\n] 2006.252.07:46:21.40#ibcon#*before write, iclass 17, count 2 2006.252.07:46:21.40#ibcon#enter sib2, iclass 17, count 2 2006.252.07:46:21.40#ibcon#flushed, iclass 17, count 2 2006.252.07:46:21.40#ibcon#about to write, iclass 17, count 2 2006.252.07:46:21.40#ibcon#wrote, iclass 17, count 2 2006.252.07:46:21.40#ibcon#about to read 3, iclass 17, count 2 2006.252.07:46:21.43#ibcon#read 3, iclass 17, count 2 2006.252.07:46:21.43#ibcon#about to read 4, iclass 17, count 2 2006.252.07:46:21.43#ibcon#read 4, iclass 17, count 2 2006.252.07:46:21.43#ibcon#about to read 5, iclass 17, count 2 2006.252.07:46:21.43#ibcon#read 5, iclass 17, count 2 2006.252.07:46:21.43#ibcon#about to read 6, iclass 17, count 2 2006.252.07:46:21.43#ibcon#read 6, iclass 17, count 2 2006.252.07:46:21.43#ibcon#end of sib2, iclass 17, count 2 2006.252.07:46:21.43#ibcon#*after write, iclass 17, count 2 2006.252.07:46:21.43#ibcon#*before return 0, iclass 17, count 2 2006.252.07:46:21.43#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.252.07:46:21.43#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.252.07:46:21.43#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.252.07:46:21.43#ibcon#ireg 7 cls_cnt 0 2006.252.07:46:21.43#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.252.07:46:21.55#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.252.07:46:21.55#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.252.07:46:21.55#ibcon#enter wrdev, iclass 17, count 0 2006.252.07:46:21.55#ibcon#first serial, iclass 17, count 0 2006.252.07:46:21.55#ibcon#enter sib2, iclass 17, count 0 2006.252.07:46:21.55#ibcon#flushed, iclass 17, count 0 2006.252.07:46:21.55#ibcon#about to write, iclass 17, count 0 2006.252.07:46:21.55#ibcon#wrote, iclass 17, count 0 2006.252.07:46:21.55#ibcon#about to read 3, iclass 17, count 0 2006.252.07:46:21.57#ibcon#read 3, iclass 17, count 0 2006.252.07:46:21.57#ibcon#about to read 4, iclass 17, count 0 2006.252.07:46:21.57#ibcon#read 4, iclass 17, count 0 2006.252.07:46:21.57#ibcon#about to read 5, iclass 17, count 0 2006.252.07:46:21.57#ibcon#read 5, iclass 17, count 0 2006.252.07:46:21.57#ibcon#about to read 6, iclass 17, count 0 2006.252.07:46:21.57#ibcon#read 6, iclass 17, count 0 2006.252.07:46:21.57#ibcon#end of sib2, iclass 17, count 0 2006.252.07:46:21.57#ibcon#*mode == 0, iclass 17, count 0 2006.252.07:46:21.57#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.252.07:46:21.57#ibcon#[27=USB\r\n] 2006.252.07:46:21.57#ibcon#*before write, iclass 17, count 0 2006.252.07:46:21.57#ibcon#enter sib2, iclass 17, count 0 2006.252.07:46:21.57#ibcon#flushed, iclass 17, count 0 2006.252.07:46:21.57#ibcon#about to write, iclass 17, count 0 2006.252.07:46:21.57#ibcon#wrote, iclass 17, count 0 2006.252.07:46:21.57#ibcon#about to read 3, iclass 17, count 0 2006.252.07:46:21.60#ibcon#read 3, iclass 17, count 0 2006.252.07:46:21.60#ibcon#about to read 4, iclass 17, count 0 2006.252.07:46:21.60#ibcon#read 4, iclass 17, count 0 2006.252.07:46:21.60#ibcon#about to read 5, iclass 17, count 0 2006.252.07:46:21.60#ibcon#read 5, iclass 17, count 0 2006.252.07:46:21.60#ibcon#about to read 6, iclass 17, count 0 2006.252.07:46:21.60#ibcon#read 6, iclass 17, count 0 2006.252.07:46:21.60#ibcon#end of sib2, iclass 17, count 0 2006.252.07:46:21.60#ibcon#*after write, iclass 17, count 0 2006.252.07:46:21.60#ibcon#*before return 0, iclass 17, count 0 2006.252.07:46:21.60#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.252.07:46:21.60#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.252.07:46:21.60#ibcon#about to clear, iclass 17 cls_cnt 0 2006.252.07:46:21.60#ibcon#cleared, iclass 17 cls_cnt 0 2006.252.07:46:21.60$vc4f8/vblo=4,712.99 2006.252.07:46:21.60#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.252.07:46:21.60#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.252.07:46:21.60#ibcon#ireg 17 cls_cnt 0 2006.252.07:46:21.60#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.252.07:46:21.60#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.252.07:46:21.60#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.252.07:46:21.60#ibcon#enter wrdev, iclass 19, count 0 2006.252.07:46:21.60#ibcon#first serial, iclass 19, count 0 2006.252.07:46:21.60#ibcon#enter sib2, iclass 19, count 0 2006.252.07:46:21.60#ibcon#flushed, iclass 19, count 0 2006.252.07:46:21.60#ibcon#about to write, iclass 19, count 0 2006.252.07:46:21.60#ibcon#wrote, iclass 19, count 0 2006.252.07:46:21.60#ibcon#about to read 3, iclass 19, count 0 2006.252.07:46:21.62#ibcon#read 3, iclass 19, count 0 2006.252.07:46:21.62#ibcon#about to read 4, iclass 19, count 0 2006.252.07:46:21.62#ibcon#read 4, iclass 19, count 0 2006.252.07:46:21.62#ibcon#about to read 5, iclass 19, count 0 2006.252.07:46:21.62#ibcon#read 5, iclass 19, count 0 2006.252.07:46:21.62#ibcon#about to read 6, iclass 19, count 0 2006.252.07:46:21.62#ibcon#read 6, iclass 19, count 0 2006.252.07:46:21.62#ibcon#end of sib2, iclass 19, count 0 2006.252.07:46:21.62#ibcon#*mode == 0, iclass 19, count 0 2006.252.07:46:21.62#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.252.07:46:21.62#ibcon#[28=FRQ=04,712.99\r\n] 2006.252.07:46:21.62#ibcon#*before write, iclass 19, count 0 2006.252.07:46:21.62#ibcon#enter sib2, iclass 19, count 0 2006.252.07:46:21.62#ibcon#flushed, iclass 19, count 0 2006.252.07:46:21.62#ibcon#about to write, iclass 19, count 0 2006.252.07:46:21.62#ibcon#wrote, iclass 19, count 0 2006.252.07:46:21.62#ibcon#about to read 3, iclass 19, count 0 2006.252.07:46:21.66#ibcon#read 3, iclass 19, count 0 2006.252.07:46:21.66#ibcon#about to read 4, iclass 19, count 0 2006.252.07:46:21.66#ibcon#read 4, iclass 19, count 0 2006.252.07:46:21.66#ibcon#about to read 5, iclass 19, count 0 2006.252.07:46:21.66#ibcon#read 5, iclass 19, count 0 2006.252.07:46:21.66#ibcon#about to read 6, iclass 19, count 0 2006.252.07:46:21.66#ibcon#read 6, iclass 19, count 0 2006.252.07:46:21.66#ibcon#end of sib2, iclass 19, count 0 2006.252.07:46:21.66#ibcon#*after write, iclass 19, count 0 2006.252.07:46:21.66#ibcon#*before return 0, iclass 19, count 0 2006.252.07:46:21.66#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.252.07:46:21.66#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.252.07:46:21.66#ibcon#about to clear, iclass 19 cls_cnt 0 2006.252.07:46:21.66#ibcon#cleared, iclass 19 cls_cnt 0 2006.252.07:46:21.66$vc4f8/vb=4,4 2006.252.07:46:21.66#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.252.07:46:21.66#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.252.07:46:21.66#ibcon#ireg 11 cls_cnt 2 2006.252.07:46:21.66#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.252.07:46:21.72#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.252.07:46:21.72#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.252.07:46:21.72#ibcon#enter wrdev, iclass 21, count 2 2006.252.07:46:21.72#ibcon#first serial, iclass 21, count 2 2006.252.07:46:21.72#ibcon#enter sib2, iclass 21, count 2 2006.252.07:46:21.72#ibcon#flushed, iclass 21, count 2 2006.252.07:46:21.72#ibcon#about to write, iclass 21, count 2 2006.252.07:46:21.72#ibcon#wrote, iclass 21, count 2 2006.252.07:46:21.72#ibcon#about to read 3, iclass 21, count 2 2006.252.07:46:21.74#ibcon#read 3, iclass 21, count 2 2006.252.07:46:21.74#ibcon#about to read 4, iclass 21, count 2 2006.252.07:46:21.74#ibcon#read 4, iclass 21, count 2 2006.252.07:46:21.74#ibcon#about to read 5, iclass 21, count 2 2006.252.07:46:21.74#ibcon#read 5, iclass 21, count 2 2006.252.07:46:21.74#ibcon#about to read 6, iclass 21, count 2 2006.252.07:46:21.74#ibcon#read 6, iclass 21, count 2 2006.252.07:46:21.74#ibcon#end of sib2, iclass 21, count 2 2006.252.07:46:21.74#ibcon#*mode == 0, iclass 21, count 2 2006.252.07:46:21.74#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.252.07:46:21.74#ibcon#[27=AT04-04\r\n] 2006.252.07:46:21.74#ibcon#*before write, iclass 21, count 2 2006.252.07:46:21.74#ibcon#enter sib2, iclass 21, count 2 2006.252.07:46:21.74#ibcon#flushed, iclass 21, count 2 2006.252.07:46:21.74#ibcon#about to write, iclass 21, count 2 2006.252.07:46:21.74#ibcon#wrote, iclass 21, count 2 2006.252.07:46:21.74#ibcon#about to read 3, iclass 21, count 2 2006.252.07:46:21.77#ibcon#read 3, iclass 21, count 2 2006.252.07:46:21.77#ibcon#about to read 4, iclass 21, count 2 2006.252.07:46:21.77#ibcon#read 4, iclass 21, count 2 2006.252.07:46:21.77#ibcon#about to read 5, iclass 21, count 2 2006.252.07:46:21.77#ibcon#read 5, iclass 21, count 2 2006.252.07:46:21.77#ibcon#about to read 6, iclass 21, count 2 2006.252.07:46:21.77#ibcon#read 6, iclass 21, count 2 2006.252.07:46:21.77#ibcon#end of sib2, iclass 21, count 2 2006.252.07:46:21.77#ibcon#*after write, iclass 21, count 2 2006.252.07:46:21.77#ibcon#*before return 0, iclass 21, count 2 2006.252.07:46:21.77#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.252.07:46:21.77#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.252.07:46:21.77#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.252.07:46:21.77#ibcon#ireg 7 cls_cnt 0 2006.252.07:46:21.77#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.252.07:46:21.89#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.252.07:46:21.89#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.252.07:46:21.89#ibcon#enter wrdev, iclass 21, count 0 2006.252.07:46:21.89#ibcon#first serial, iclass 21, count 0 2006.252.07:46:21.89#ibcon#enter sib2, iclass 21, count 0 2006.252.07:46:21.89#ibcon#flushed, iclass 21, count 0 2006.252.07:46:21.89#ibcon#about to write, iclass 21, count 0 2006.252.07:46:21.89#ibcon#wrote, iclass 21, count 0 2006.252.07:46:21.89#ibcon#about to read 3, iclass 21, count 0 2006.252.07:46:21.91#ibcon#read 3, iclass 21, count 0 2006.252.07:46:21.91#ibcon#about to read 4, iclass 21, count 0 2006.252.07:46:21.91#ibcon#read 4, iclass 21, count 0 2006.252.07:46:21.91#ibcon#about to read 5, iclass 21, count 0 2006.252.07:46:21.91#ibcon#read 5, iclass 21, count 0 2006.252.07:46:21.91#ibcon#about to read 6, iclass 21, count 0 2006.252.07:46:21.91#ibcon#read 6, iclass 21, count 0 2006.252.07:46:21.91#ibcon#end of sib2, iclass 21, count 0 2006.252.07:46:21.91#ibcon#*mode == 0, iclass 21, count 0 2006.252.07:46:21.91#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.252.07:46:21.91#ibcon#[27=USB\r\n] 2006.252.07:46:21.91#ibcon#*before write, iclass 21, count 0 2006.252.07:46:21.91#ibcon#enter sib2, iclass 21, count 0 2006.252.07:46:21.91#ibcon#flushed, iclass 21, count 0 2006.252.07:46:21.91#ibcon#about to write, iclass 21, count 0 2006.252.07:46:21.91#ibcon#wrote, iclass 21, count 0 2006.252.07:46:21.91#ibcon#about to read 3, iclass 21, count 0 2006.252.07:46:21.94#ibcon#read 3, iclass 21, count 0 2006.252.07:46:21.94#ibcon#about to read 4, iclass 21, count 0 2006.252.07:46:21.94#ibcon#read 4, iclass 21, count 0 2006.252.07:46:21.94#ibcon#about to read 5, iclass 21, count 0 2006.252.07:46:21.94#ibcon#read 5, iclass 21, count 0 2006.252.07:46:21.94#ibcon#about to read 6, iclass 21, count 0 2006.252.07:46:21.94#ibcon#read 6, iclass 21, count 0 2006.252.07:46:21.94#ibcon#end of sib2, iclass 21, count 0 2006.252.07:46:21.94#ibcon#*after write, iclass 21, count 0 2006.252.07:46:21.94#ibcon#*before return 0, iclass 21, count 0 2006.252.07:46:21.94#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.252.07:46:21.94#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.252.07:46:21.94#ibcon#about to clear, iclass 21 cls_cnt 0 2006.252.07:46:21.94#ibcon#cleared, iclass 21 cls_cnt 0 2006.252.07:46:21.94$vc4f8/vblo=5,744.99 2006.252.07:46:21.94#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.252.07:46:21.94#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.252.07:46:21.94#ibcon#ireg 17 cls_cnt 0 2006.252.07:46:21.94#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.252.07:46:21.94#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.252.07:46:21.94#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.252.07:46:21.94#ibcon#enter wrdev, iclass 23, count 0 2006.252.07:46:21.94#ibcon#first serial, iclass 23, count 0 2006.252.07:46:21.94#ibcon#enter sib2, iclass 23, count 0 2006.252.07:46:21.94#ibcon#flushed, iclass 23, count 0 2006.252.07:46:21.94#ibcon#about to write, iclass 23, count 0 2006.252.07:46:21.94#ibcon#wrote, iclass 23, count 0 2006.252.07:46:21.94#ibcon#about to read 3, iclass 23, count 0 2006.252.07:46:21.96#ibcon#read 3, iclass 23, count 0 2006.252.07:46:21.96#ibcon#about to read 4, iclass 23, count 0 2006.252.07:46:21.96#ibcon#read 4, iclass 23, count 0 2006.252.07:46:21.96#ibcon#about to read 5, iclass 23, count 0 2006.252.07:46:21.96#ibcon#read 5, iclass 23, count 0 2006.252.07:46:21.96#ibcon#about to read 6, iclass 23, count 0 2006.252.07:46:21.96#ibcon#read 6, iclass 23, count 0 2006.252.07:46:21.96#ibcon#end of sib2, iclass 23, count 0 2006.252.07:46:21.96#ibcon#*mode == 0, iclass 23, count 0 2006.252.07:46:21.96#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.252.07:46:21.96#ibcon#[28=FRQ=05,744.99\r\n] 2006.252.07:46:21.96#ibcon#*before write, iclass 23, count 0 2006.252.07:46:21.96#ibcon#enter sib2, iclass 23, count 0 2006.252.07:46:21.96#ibcon#flushed, iclass 23, count 0 2006.252.07:46:21.96#ibcon#about to write, iclass 23, count 0 2006.252.07:46:21.96#ibcon#wrote, iclass 23, count 0 2006.252.07:46:21.96#ibcon#about to read 3, iclass 23, count 0 2006.252.07:46:22.00#ibcon#read 3, iclass 23, count 0 2006.252.07:46:22.00#ibcon#about to read 4, iclass 23, count 0 2006.252.07:46:22.00#ibcon#read 4, iclass 23, count 0 2006.252.07:46:22.00#ibcon#about to read 5, iclass 23, count 0 2006.252.07:46:22.00#ibcon#read 5, iclass 23, count 0 2006.252.07:46:22.00#ibcon#about to read 6, iclass 23, count 0 2006.252.07:46:22.00#ibcon#read 6, iclass 23, count 0 2006.252.07:46:22.00#ibcon#end of sib2, iclass 23, count 0 2006.252.07:46:22.00#ibcon#*after write, iclass 23, count 0 2006.252.07:46:22.00#ibcon#*before return 0, iclass 23, count 0 2006.252.07:46:22.00#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.252.07:46:22.00#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.252.07:46:22.00#ibcon#about to clear, iclass 23 cls_cnt 0 2006.252.07:46:22.00#ibcon#cleared, iclass 23 cls_cnt 0 2006.252.07:46:22.00$vc4f8/vb=5,4 2006.252.07:46:22.00#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.252.07:46:22.00#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.252.07:46:22.00#ibcon#ireg 11 cls_cnt 2 2006.252.07:46:22.00#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.252.07:46:22.06#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.252.07:46:22.06#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.252.07:46:22.06#ibcon#enter wrdev, iclass 25, count 2 2006.252.07:46:22.06#ibcon#first serial, iclass 25, count 2 2006.252.07:46:22.06#ibcon#enter sib2, iclass 25, count 2 2006.252.07:46:22.06#ibcon#flushed, iclass 25, count 2 2006.252.07:46:22.06#ibcon#about to write, iclass 25, count 2 2006.252.07:46:22.06#ibcon#wrote, iclass 25, count 2 2006.252.07:46:22.06#ibcon#about to read 3, iclass 25, count 2 2006.252.07:46:22.08#ibcon#read 3, iclass 25, count 2 2006.252.07:46:22.08#ibcon#about to read 4, iclass 25, count 2 2006.252.07:46:22.08#ibcon#read 4, iclass 25, count 2 2006.252.07:46:22.08#ibcon#about to read 5, iclass 25, count 2 2006.252.07:46:22.08#ibcon#read 5, iclass 25, count 2 2006.252.07:46:22.08#ibcon#about to read 6, iclass 25, count 2 2006.252.07:46:22.08#ibcon#read 6, iclass 25, count 2 2006.252.07:46:22.08#ibcon#end of sib2, iclass 25, count 2 2006.252.07:46:22.08#ibcon#*mode == 0, iclass 25, count 2 2006.252.07:46:22.08#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.252.07:46:22.08#ibcon#[27=AT05-04\r\n] 2006.252.07:46:22.08#ibcon#*before write, iclass 25, count 2 2006.252.07:46:22.08#ibcon#enter sib2, iclass 25, count 2 2006.252.07:46:22.08#ibcon#flushed, iclass 25, count 2 2006.252.07:46:22.08#ibcon#about to write, iclass 25, count 2 2006.252.07:46:22.08#ibcon#wrote, iclass 25, count 2 2006.252.07:46:22.08#ibcon#about to read 3, iclass 25, count 2 2006.252.07:46:22.11#ibcon#read 3, iclass 25, count 2 2006.252.07:46:22.11#ibcon#about to read 4, iclass 25, count 2 2006.252.07:46:22.11#ibcon#read 4, iclass 25, count 2 2006.252.07:46:22.11#ibcon#about to read 5, iclass 25, count 2 2006.252.07:46:22.11#ibcon#read 5, iclass 25, count 2 2006.252.07:46:22.11#ibcon#about to read 6, iclass 25, count 2 2006.252.07:46:22.11#ibcon#read 6, iclass 25, count 2 2006.252.07:46:22.11#ibcon#end of sib2, iclass 25, count 2 2006.252.07:46:22.11#ibcon#*after write, iclass 25, count 2 2006.252.07:46:22.11#ibcon#*before return 0, iclass 25, count 2 2006.252.07:46:22.11#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.252.07:46:22.11#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.252.07:46:22.11#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.252.07:46:22.11#ibcon#ireg 7 cls_cnt 0 2006.252.07:46:22.11#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.252.07:46:22.23#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.252.07:46:22.23#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.252.07:46:22.23#ibcon#enter wrdev, iclass 25, count 0 2006.252.07:46:22.23#ibcon#first serial, iclass 25, count 0 2006.252.07:46:22.23#ibcon#enter sib2, iclass 25, count 0 2006.252.07:46:22.23#ibcon#flushed, iclass 25, count 0 2006.252.07:46:22.23#ibcon#about to write, iclass 25, count 0 2006.252.07:46:22.23#ibcon#wrote, iclass 25, count 0 2006.252.07:46:22.23#ibcon#about to read 3, iclass 25, count 0 2006.252.07:46:22.27#ibcon#read 3, iclass 25, count 0 2006.252.07:46:22.27#ibcon#about to read 4, iclass 25, count 0 2006.252.07:46:22.27#ibcon#read 4, iclass 25, count 0 2006.252.07:46:22.27#ibcon#about to read 5, iclass 25, count 0 2006.252.07:46:22.27#ibcon#read 5, iclass 25, count 0 2006.252.07:46:22.27#ibcon#about to read 6, iclass 25, count 0 2006.252.07:46:22.27#ibcon#read 6, iclass 25, count 0 2006.252.07:46:22.27#ibcon#end of sib2, iclass 25, count 0 2006.252.07:46:22.27#ibcon#*mode == 0, iclass 25, count 0 2006.252.07:46:22.27#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.252.07:46:22.27#ibcon#[27=USB\r\n] 2006.252.07:46:22.27#ibcon#*before write, iclass 25, count 0 2006.252.07:46:22.27#ibcon#enter sib2, iclass 25, count 0 2006.252.07:46:22.27#ibcon#flushed, iclass 25, count 0 2006.252.07:46:22.27#ibcon#about to write, iclass 25, count 0 2006.252.07:46:22.27#ibcon#wrote, iclass 25, count 0 2006.252.07:46:22.27#ibcon#about to read 3, iclass 25, count 0 2006.252.07:46:22.29#ibcon#read 3, iclass 25, count 0 2006.252.07:46:22.29#ibcon#about to read 4, iclass 25, count 0 2006.252.07:46:22.29#ibcon#read 4, iclass 25, count 0 2006.252.07:46:22.29#ibcon#about to read 5, iclass 25, count 0 2006.252.07:46:22.29#ibcon#read 5, iclass 25, count 0 2006.252.07:46:22.29#ibcon#about to read 6, iclass 25, count 0 2006.252.07:46:22.29#ibcon#read 6, iclass 25, count 0 2006.252.07:46:22.29#ibcon#end of sib2, iclass 25, count 0 2006.252.07:46:22.29#ibcon#*after write, iclass 25, count 0 2006.252.07:46:22.29#ibcon#*before return 0, iclass 25, count 0 2006.252.07:46:22.29#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.252.07:46:22.29#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.252.07:46:22.29#ibcon#about to clear, iclass 25 cls_cnt 0 2006.252.07:46:22.29#ibcon#cleared, iclass 25 cls_cnt 0 2006.252.07:46:22.29$vc4f8/vblo=6,752.99 2006.252.07:46:22.29#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.252.07:46:22.29#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.252.07:46:22.29#ibcon#ireg 17 cls_cnt 0 2006.252.07:46:22.29#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.252.07:46:22.29#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.252.07:46:22.29#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.252.07:46:22.29#ibcon#enter wrdev, iclass 27, count 0 2006.252.07:46:22.29#ibcon#first serial, iclass 27, count 0 2006.252.07:46:22.29#ibcon#enter sib2, iclass 27, count 0 2006.252.07:46:22.29#ibcon#flushed, iclass 27, count 0 2006.252.07:46:22.29#ibcon#about to write, iclass 27, count 0 2006.252.07:46:22.29#ibcon#wrote, iclass 27, count 0 2006.252.07:46:22.29#ibcon#about to read 3, iclass 27, count 0 2006.252.07:46:22.31#ibcon#read 3, iclass 27, count 0 2006.252.07:46:22.31#ibcon#about to read 4, iclass 27, count 0 2006.252.07:46:22.31#ibcon#read 4, iclass 27, count 0 2006.252.07:46:22.31#ibcon#about to read 5, iclass 27, count 0 2006.252.07:46:22.31#ibcon#read 5, iclass 27, count 0 2006.252.07:46:22.31#ibcon#about to read 6, iclass 27, count 0 2006.252.07:46:22.31#ibcon#read 6, iclass 27, count 0 2006.252.07:46:22.31#ibcon#end of sib2, iclass 27, count 0 2006.252.07:46:22.31#ibcon#*mode == 0, iclass 27, count 0 2006.252.07:46:22.31#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.252.07:46:22.31#ibcon#[28=FRQ=06,752.99\r\n] 2006.252.07:46:22.31#ibcon#*before write, iclass 27, count 0 2006.252.07:46:22.31#ibcon#enter sib2, iclass 27, count 0 2006.252.07:46:22.31#ibcon#flushed, iclass 27, count 0 2006.252.07:46:22.31#ibcon#about to write, iclass 27, count 0 2006.252.07:46:22.31#ibcon#wrote, iclass 27, count 0 2006.252.07:46:22.31#ibcon#about to read 3, iclass 27, count 0 2006.252.07:46:22.35#ibcon#read 3, iclass 27, count 0 2006.252.07:46:22.35#ibcon#about to read 4, iclass 27, count 0 2006.252.07:46:22.35#ibcon#read 4, iclass 27, count 0 2006.252.07:46:22.35#ibcon#about to read 5, iclass 27, count 0 2006.252.07:46:22.35#ibcon#read 5, iclass 27, count 0 2006.252.07:46:22.35#ibcon#about to read 6, iclass 27, count 0 2006.252.07:46:22.35#ibcon#read 6, iclass 27, count 0 2006.252.07:46:22.35#ibcon#end of sib2, iclass 27, count 0 2006.252.07:46:22.35#ibcon#*after write, iclass 27, count 0 2006.252.07:46:22.35#ibcon#*before return 0, iclass 27, count 0 2006.252.07:46:22.35#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.252.07:46:22.35#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.252.07:46:22.35#ibcon#about to clear, iclass 27 cls_cnt 0 2006.252.07:46:22.35#ibcon#cleared, iclass 27 cls_cnt 0 2006.252.07:46:22.35$vc4f8/vb=6,4 2006.252.07:46:22.35#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.252.07:46:22.35#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.252.07:46:22.35#ibcon#ireg 11 cls_cnt 2 2006.252.07:46:22.35#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.252.07:46:22.41#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.252.07:46:22.41#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.252.07:46:22.41#ibcon#enter wrdev, iclass 29, count 2 2006.252.07:46:22.41#ibcon#first serial, iclass 29, count 2 2006.252.07:46:22.41#ibcon#enter sib2, iclass 29, count 2 2006.252.07:46:22.41#ibcon#flushed, iclass 29, count 2 2006.252.07:46:22.41#ibcon#about to write, iclass 29, count 2 2006.252.07:46:22.41#ibcon#wrote, iclass 29, count 2 2006.252.07:46:22.41#ibcon#about to read 3, iclass 29, count 2 2006.252.07:46:22.43#ibcon#read 3, iclass 29, count 2 2006.252.07:46:22.43#ibcon#about to read 4, iclass 29, count 2 2006.252.07:46:22.43#ibcon#read 4, iclass 29, count 2 2006.252.07:46:22.43#ibcon#about to read 5, iclass 29, count 2 2006.252.07:46:22.43#ibcon#read 5, iclass 29, count 2 2006.252.07:46:22.43#ibcon#about to read 6, iclass 29, count 2 2006.252.07:46:22.43#ibcon#read 6, iclass 29, count 2 2006.252.07:46:22.43#ibcon#end of sib2, iclass 29, count 2 2006.252.07:46:22.43#ibcon#*mode == 0, iclass 29, count 2 2006.252.07:46:22.43#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.252.07:46:22.43#ibcon#[27=AT06-04\r\n] 2006.252.07:46:22.43#ibcon#*before write, iclass 29, count 2 2006.252.07:46:22.43#ibcon#enter sib2, iclass 29, count 2 2006.252.07:46:22.43#ibcon#flushed, iclass 29, count 2 2006.252.07:46:22.43#ibcon#about to write, iclass 29, count 2 2006.252.07:46:22.43#ibcon#wrote, iclass 29, count 2 2006.252.07:46:22.43#ibcon#about to read 3, iclass 29, count 2 2006.252.07:46:22.46#ibcon#read 3, iclass 29, count 2 2006.252.07:46:22.46#ibcon#about to read 4, iclass 29, count 2 2006.252.07:46:22.46#ibcon#read 4, iclass 29, count 2 2006.252.07:46:22.46#ibcon#about to read 5, iclass 29, count 2 2006.252.07:46:22.46#ibcon#read 5, iclass 29, count 2 2006.252.07:46:22.46#ibcon#about to read 6, iclass 29, count 2 2006.252.07:46:22.46#ibcon#read 6, iclass 29, count 2 2006.252.07:46:22.46#ibcon#end of sib2, iclass 29, count 2 2006.252.07:46:22.46#ibcon#*after write, iclass 29, count 2 2006.252.07:46:22.46#ibcon#*before return 0, iclass 29, count 2 2006.252.07:46:22.46#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.252.07:46:22.46#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.252.07:46:22.46#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.252.07:46:22.46#ibcon#ireg 7 cls_cnt 0 2006.252.07:46:22.46#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.252.07:46:22.58#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.252.07:46:22.58#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.252.07:46:22.58#ibcon#enter wrdev, iclass 29, count 0 2006.252.07:46:22.58#ibcon#first serial, iclass 29, count 0 2006.252.07:46:22.58#ibcon#enter sib2, iclass 29, count 0 2006.252.07:46:22.58#ibcon#flushed, iclass 29, count 0 2006.252.07:46:22.58#ibcon#about to write, iclass 29, count 0 2006.252.07:46:22.58#ibcon#wrote, iclass 29, count 0 2006.252.07:46:22.58#ibcon#about to read 3, iclass 29, count 0 2006.252.07:46:22.60#ibcon#read 3, iclass 29, count 0 2006.252.07:46:22.60#ibcon#about to read 4, iclass 29, count 0 2006.252.07:46:22.60#ibcon#read 4, iclass 29, count 0 2006.252.07:46:22.60#ibcon#about to read 5, iclass 29, count 0 2006.252.07:46:22.60#ibcon#read 5, iclass 29, count 0 2006.252.07:46:22.60#ibcon#about to read 6, iclass 29, count 0 2006.252.07:46:22.60#ibcon#read 6, iclass 29, count 0 2006.252.07:46:22.60#ibcon#end of sib2, iclass 29, count 0 2006.252.07:46:22.60#ibcon#*mode == 0, iclass 29, count 0 2006.252.07:46:22.60#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.252.07:46:22.60#ibcon#[27=USB\r\n] 2006.252.07:46:22.60#ibcon#*before write, iclass 29, count 0 2006.252.07:46:22.60#ibcon#enter sib2, iclass 29, count 0 2006.252.07:46:22.60#ibcon#flushed, iclass 29, count 0 2006.252.07:46:22.60#ibcon#about to write, iclass 29, count 0 2006.252.07:46:22.60#ibcon#wrote, iclass 29, count 0 2006.252.07:46:22.60#ibcon#about to read 3, iclass 29, count 0 2006.252.07:46:22.63#ibcon#read 3, iclass 29, count 0 2006.252.07:46:22.63#ibcon#about to read 4, iclass 29, count 0 2006.252.07:46:22.63#ibcon#read 4, iclass 29, count 0 2006.252.07:46:22.63#ibcon#about to read 5, iclass 29, count 0 2006.252.07:46:22.63#ibcon#read 5, iclass 29, count 0 2006.252.07:46:22.63#ibcon#about to read 6, iclass 29, count 0 2006.252.07:46:22.63#ibcon#read 6, iclass 29, count 0 2006.252.07:46:22.63#ibcon#end of sib2, iclass 29, count 0 2006.252.07:46:22.63#ibcon#*after write, iclass 29, count 0 2006.252.07:46:22.63#ibcon#*before return 0, iclass 29, count 0 2006.252.07:46:22.63#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.252.07:46:22.63#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.252.07:46:22.63#ibcon#about to clear, iclass 29 cls_cnt 0 2006.252.07:46:22.63#ibcon#cleared, iclass 29 cls_cnt 0 2006.252.07:46:22.63$vc4f8/vabw=wide 2006.252.07:46:22.63#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.252.07:46:22.63#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.252.07:46:22.63#ibcon#ireg 8 cls_cnt 0 2006.252.07:46:22.63#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.252.07:46:22.63#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.252.07:46:22.63#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.252.07:46:22.63#ibcon#enter wrdev, iclass 31, count 0 2006.252.07:46:22.63#ibcon#first serial, iclass 31, count 0 2006.252.07:46:22.63#ibcon#enter sib2, iclass 31, count 0 2006.252.07:46:22.63#ibcon#flushed, iclass 31, count 0 2006.252.07:46:22.63#ibcon#about to write, iclass 31, count 0 2006.252.07:46:22.63#ibcon#wrote, iclass 31, count 0 2006.252.07:46:22.63#ibcon#about to read 3, iclass 31, count 0 2006.252.07:46:22.65#ibcon#read 3, iclass 31, count 0 2006.252.07:46:22.65#ibcon#about to read 4, iclass 31, count 0 2006.252.07:46:22.65#ibcon#read 4, iclass 31, count 0 2006.252.07:46:22.65#ibcon#about to read 5, iclass 31, count 0 2006.252.07:46:22.65#ibcon#read 5, iclass 31, count 0 2006.252.07:46:22.65#ibcon#about to read 6, iclass 31, count 0 2006.252.07:46:22.65#ibcon#read 6, iclass 31, count 0 2006.252.07:46:22.65#ibcon#end of sib2, iclass 31, count 0 2006.252.07:46:22.65#ibcon#*mode == 0, iclass 31, count 0 2006.252.07:46:22.65#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.252.07:46:22.65#ibcon#[25=BW32\r\n] 2006.252.07:46:22.65#ibcon#*before write, iclass 31, count 0 2006.252.07:46:22.65#ibcon#enter sib2, iclass 31, count 0 2006.252.07:46:22.65#ibcon#flushed, iclass 31, count 0 2006.252.07:46:22.65#ibcon#about to write, iclass 31, count 0 2006.252.07:46:22.65#ibcon#wrote, iclass 31, count 0 2006.252.07:46:22.65#ibcon#about to read 3, iclass 31, count 0 2006.252.07:46:22.68#ibcon#read 3, iclass 31, count 0 2006.252.07:46:22.68#ibcon#about to read 4, iclass 31, count 0 2006.252.07:46:22.68#ibcon#read 4, iclass 31, count 0 2006.252.07:46:22.68#ibcon#about to read 5, iclass 31, count 0 2006.252.07:46:22.68#ibcon#read 5, iclass 31, count 0 2006.252.07:46:22.68#ibcon#about to read 6, iclass 31, count 0 2006.252.07:46:22.68#ibcon#read 6, iclass 31, count 0 2006.252.07:46:22.68#ibcon#end of sib2, iclass 31, count 0 2006.252.07:46:22.68#ibcon#*after write, iclass 31, count 0 2006.252.07:46:22.68#ibcon#*before return 0, iclass 31, count 0 2006.252.07:46:22.68#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.252.07:46:22.68#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.252.07:46:22.68#ibcon#about to clear, iclass 31 cls_cnt 0 2006.252.07:46:22.68#ibcon#cleared, iclass 31 cls_cnt 0 2006.252.07:46:22.68$vc4f8/vbbw=wide 2006.252.07:46:22.68#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.252.07:46:22.68#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.252.07:46:22.68#ibcon#ireg 8 cls_cnt 0 2006.252.07:46:22.68#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.252.07:46:22.75#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.252.07:46:22.75#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.252.07:46:22.75#ibcon#enter wrdev, iclass 33, count 0 2006.252.07:46:22.75#ibcon#first serial, iclass 33, count 0 2006.252.07:46:22.75#ibcon#enter sib2, iclass 33, count 0 2006.252.07:46:22.75#ibcon#flushed, iclass 33, count 0 2006.252.07:46:22.75#ibcon#about to write, iclass 33, count 0 2006.252.07:46:22.75#ibcon#wrote, iclass 33, count 0 2006.252.07:46:22.75#ibcon#about to read 3, iclass 33, count 0 2006.252.07:46:22.77#ibcon#read 3, iclass 33, count 0 2006.252.07:46:22.77#ibcon#about to read 4, iclass 33, count 0 2006.252.07:46:22.77#ibcon#read 4, iclass 33, count 0 2006.252.07:46:22.77#ibcon#about to read 5, iclass 33, count 0 2006.252.07:46:22.77#ibcon#read 5, iclass 33, count 0 2006.252.07:46:22.77#ibcon#about to read 6, iclass 33, count 0 2006.252.07:46:22.77#ibcon#read 6, iclass 33, count 0 2006.252.07:46:22.77#ibcon#end of sib2, iclass 33, count 0 2006.252.07:46:22.77#ibcon#*mode == 0, iclass 33, count 0 2006.252.07:46:22.77#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.252.07:46:22.77#ibcon#[27=BW32\r\n] 2006.252.07:46:22.77#ibcon#*before write, iclass 33, count 0 2006.252.07:46:22.77#ibcon#enter sib2, iclass 33, count 0 2006.252.07:46:22.77#ibcon#flushed, iclass 33, count 0 2006.252.07:46:22.77#ibcon#about to write, iclass 33, count 0 2006.252.07:46:22.77#ibcon#wrote, iclass 33, count 0 2006.252.07:46:22.77#ibcon#about to read 3, iclass 33, count 0 2006.252.07:46:22.80#ibcon#read 3, iclass 33, count 0 2006.252.07:46:22.80#ibcon#about to read 4, iclass 33, count 0 2006.252.07:46:22.80#ibcon#read 4, iclass 33, count 0 2006.252.07:46:22.80#ibcon#about to read 5, iclass 33, count 0 2006.252.07:46:22.80#ibcon#read 5, iclass 33, count 0 2006.252.07:46:22.80#ibcon#about to read 6, iclass 33, count 0 2006.252.07:46:22.80#ibcon#read 6, iclass 33, count 0 2006.252.07:46:22.80#ibcon#end of sib2, iclass 33, count 0 2006.252.07:46:22.80#ibcon#*after write, iclass 33, count 0 2006.252.07:46:22.80#ibcon#*before return 0, iclass 33, count 0 2006.252.07:46:22.80#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.252.07:46:22.80#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.252.07:46:22.80#ibcon#about to clear, iclass 33 cls_cnt 0 2006.252.07:46:22.80#ibcon#cleared, iclass 33 cls_cnt 0 2006.252.07:46:22.80$4f8m12a/ifd4f 2006.252.07:46:22.80$ifd4f/lo= 2006.252.07:46:22.80$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.252.07:46:22.80$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.252.07:46:22.80$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.252.07:46:22.80$ifd4f/patch= 2006.252.07:46:22.80$ifd4f/patch=lo1,a1,a2,a3,a4 2006.252.07:46:22.80$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.252.07:46:22.80$ifd4f/patch=lo3,a5,a6,a7,a8 2006.252.07:46:22.80$4f8m12a/"form=m,16.000,1:2 2006.252.07:46:22.80$4f8m12a/"tpicd 2006.252.07:46:22.80$4f8m12a/echo=off 2006.252.07:46:22.80$4f8m12a/xlog=off 2006.252.07:46:22.80:!2006.252.07:46:50 2006.252.07:46:31.14#trakl#Source acquired 2006.252.07:46:32.14#flagr#flagr/antenna,acquired 2006.252.07:46:50.00:preob 2006.252.07:46:51.14/onsource/TRACKING 2006.252.07:46:51.14:!2006.252.07:47:00 2006.252.07:47:00.00:data_valid=on 2006.252.07:47:00.00:midob 2006.252.07:47:00.14/onsource/TRACKING 2006.252.07:47:00.14/wx/27.39,1011.2,90 2006.252.07:47:00.30/cable/+6.4086E-03 2006.252.07:47:01.39/va/01,08,usb,yes,32,34 2006.252.07:47:01.39/va/02,07,usb,yes,32,34 2006.252.07:47:01.39/va/03,06,usb,yes,34,34 2006.252.07:47:01.39/va/04,07,usb,yes,33,36 2006.252.07:47:01.39/va/05,07,usb,yes,36,38 2006.252.07:47:01.39/va/06,07,usb,yes,31,31 2006.252.07:47:01.39/va/07,07,usb,yes,31,31 2006.252.07:47:01.39/va/08,07,usb,yes,33,33 2006.252.07:47:01.62/valo/01,532.99,yes,locked 2006.252.07:47:01.62/valo/02,572.99,yes,locked 2006.252.07:47:01.62/valo/03,672.99,yes,locked 2006.252.07:47:01.62/valo/04,832.99,yes,locked 2006.252.07:47:01.62/valo/05,652.99,yes,locked 2006.252.07:47:01.62/valo/06,772.99,yes,locked 2006.252.07:47:01.62/valo/07,832.99,yes,locked 2006.252.07:47:01.62/valo/08,852.99,yes,locked 2006.252.07:47:02.71/vb/01,04,usb,yes,30,29 2006.252.07:47:02.71/vb/02,05,usb,yes,28,29 2006.252.07:47:02.71/vb/03,04,usb,yes,28,32 2006.252.07:47:02.71/vb/04,04,usb,yes,29,29 2006.252.07:47:02.71/vb/05,04,usb,yes,28,32 2006.252.07:47:02.71/vb/06,04,usb,yes,28,31 2006.252.07:47:02.71/vb/07,04,usb,yes,31,31 2006.252.07:47:02.71/vb/08,04,usb,yes,28,31 2006.252.07:47:02.94/vblo/01,632.99,yes,locked 2006.252.07:47:02.94/vblo/02,640.99,yes,locked 2006.252.07:47:02.94/vblo/03,656.99,yes,locked 2006.252.07:47:02.94/vblo/04,712.99,yes,locked 2006.252.07:47:02.94/vblo/05,744.99,yes,locked 2006.252.07:47:02.94/vblo/06,752.99,yes,locked 2006.252.07:47:02.94/vblo/07,734.99,yes,locked 2006.252.07:47:02.94/vblo/08,744.99,yes,locked 2006.252.07:47:03.09/vabw/8 2006.252.07:47:03.24/vbbw/8 2006.252.07:47:03.35/xfe/off,on,14.2 2006.252.07:47:03.72/ifatt/23,28,28,28 2006.252.07:47:04.07/fmout-gps/S +4.80E-07 2006.252.07:47:04.15:!2006.252.07:48:00 2006.252.07:48:00.00:data_valid=off 2006.252.07:48:00.01:postob 2006.252.07:48:00.09/cable/+6.4084E-03 2006.252.07:48:00.09/wx/27.39,1011.2,90 2006.252.07:48:01.07/fmout-gps/S +4.80E-07 2006.252.07:48:01.08:scan_name=252-0748,k06252,60 2006.252.07:48:01.08:source=nrao512,164029.63,394646.0,2000.0,cw 2006.252.07:48:01.14#flagr#flagr/antenna,new-source 2006.252.07:48:02.14:checkk5 2006.252.07:48:02.51/chk_autoobs//k5ts1/ autoobs is running! 2006.252.07:48:02.89/chk_autoobs//k5ts2/ autoobs is running! 2006.252.07:48:03.27/chk_autoobs//k5ts3/ autoobs is running! 2006.252.07:48:03.65/chk_autoobs//k5ts4/ autoobs is running! 2006.252.07:48:04.02/chk_obsdata//k5ts1/T2520747??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.07:48:04.39/chk_obsdata//k5ts2/T2520747??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.07:48:04.75/chk_obsdata//k5ts3/T2520747??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.07:48:05.12/chk_obsdata//k5ts4/T2520747??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.07:48:05.82/k5log//k5ts1_log_newline 2006.252.07:48:06.50/k5log//k5ts2_log_newline 2006.252.07:48:07.19/k5log//k5ts3_log_newline 2006.252.07:48:07.88/k5log//k5ts4_log_newline 2006.252.07:48:07.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.252.07:48:07.90:4f8m12a=1 2006.252.07:48:07.90$4f8m12a/echo=on 2006.252.07:48:07.90$4f8m12a/pcalon 2006.252.07:48:07.90$pcalon/"no phase cal control is implemented here 2006.252.07:48:07.90$4f8m12a/"tpicd=stop 2006.252.07:48:07.90$4f8m12a/vc4f8 2006.252.07:48:07.90$vc4f8/valo=1,532.99 2006.252.07:48:07.91#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.252.07:48:07.91#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.252.07:48:07.91#ibcon#ireg 17 cls_cnt 0 2006.252.07:48:07.91#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.252.07:48:07.91#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.252.07:48:07.91#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.252.07:48:07.91#ibcon#enter wrdev, iclass 40, count 0 2006.252.07:48:07.91#ibcon#first serial, iclass 40, count 0 2006.252.07:48:07.91#ibcon#enter sib2, iclass 40, count 0 2006.252.07:48:07.91#ibcon#flushed, iclass 40, count 0 2006.252.07:48:07.91#ibcon#about to write, iclass 40, count 0 2006.252.07:48:07.91#ibcon#wrote, iclass 40, count 0 2006.252.07:48:07.91#ibcon#about to read 3, iclass 40, count 0 2006.252.07:48:07.95#ibcon#read 3, iclass 40, count 0 2006.252.07:48:07.95#ibcon#about to read 4, iclass 40, count 0 2006.252.07:48:07.95#ibcon#read 4, iclass 40, count 0 2006.252.07:48:07.95#ibcon#about to read 5, iclass 40, count 0 2006.252.07:48:07.95#ibcon#read 5, iclass 40, count 0 2006.252.07:48:07.95#ibcon#about to read 6, iclass 40, count 0 2006.252.07:48:07.95#ibcon#read 6, iclass 40, count 0 2006.252.07:48:07.95#ibcon#end of sib2, iclass 40, count 0 2006.252.07:48:07.95#ibcon#*mode == 0, iclass 40, count 0 2006.252.07:48:07.95#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.252.07:48:07.95#ibcon#[26=FRQ=01,532.99\r\n] 2006.252.07:48:07.95#ibcon#*before write, iclass 40, count 0 2006.252.07:48:07.95#ibcon#enter sib2, iclass 40, count 0 2006.252.07:48:07.95#ibcon#flushed, iclass 40, count 0 2006.252.07:48:07.95#ibcon#about to write, iclass 40, count 0 2006.252.07:48:07.95#ibcon#wrote, iclass 40, count 0 2006.252.07:48:07.95#ibcon#about to read 3, iclass 40, count 0 2006.252.07:48:07.99#ibcon#read 3, iclass 40, count 0 2006.252.07:48:07.99#ibcon#about to read 4, iclass 40, count 0 2006.252.07:48:07.99#ibcon#read 4, iclass 40, count 0 2006.252.07:48:07.99#ibcon#about to read 5, iclass 40, count 0 2006.252.07:48:07.99#ibcon#read 5, iclass 40, count 0 2006.252.07:48:07.99#ibcon#about to read 6, iclass 40, count 0 2006.252.07:48:07.99#ibcon#read 6, iclass 40, count 0 2006.252.07:48:07.99#ibcon#end of sib2, iclass 40, count 0 2006.252.07:48:07.99#ibcon#*after write, iclass 40, count 0 2006.252.07:48:07.99#ibcon#*before return 0, iclass 40, count 0 2006.252.07:48:07.99#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.252.07:48:07.99#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.252.07:48:07.99#ibcon#about to clear, iclass 40 cls_cnt 0 2006.252.07:48:07.99#ibcon#cleared, iclass 40 cls_cnt 0 2006.252.07:48:07.99$vc4f8/va=1,8 2006.252.07:48:07.99#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.252.07:48:07.99#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.252.07:48:07.99#ibcon#ireg 11 cls_cnt 2 2006.252.07:48:07.99#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.252.07:48:07.99#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.252.07:48:07.99#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.252.07:48:07.99#ibcon#enter wrdev, iclass 4, count 2 2006.252.07:48:07.99#ibcon#first serial, iclass 4, count 2 2006.252.07:48:07.99#ibcon#enter sib2, iclass 4, count 2 2006.252.07:48:07.99#ibcon#flushed, iclass 4, count 2 2006.252.07:48:07.99#ibcon#about to write, iclass 4, count 2 2006.252.07:48:07.99#ibcon#wrote, iclass 4, count 2 2006.252.07:48:07.99#ibcon#about to read 3, iclass 4, count 2 2006.252.07:48:08.01#ibcon#read 3, iclass 4, count 2 2006.252.07:48:08.01#ibcon#about to read 4, iclass 4, count 2 2006.252.07:48:08.01#ibcon#read 4, iclass 4, count 2 2006.252.07:48:08.01#ibcon#about to read 5, iclass 4, count 2 2006.252.07:48:08.01#ibcon#read 5, iclass 4, count 2 2006.252.07:48:08.01#ibcon#about to read 6, iclass 4, count 2 2006.252.07:48:08.01#ibcon#read 6, iclass 4, count 2 2006.252.07:48:08.01#ibcon#end of sib2, iclass 4, count 2 2006.252.07:48:08.01#ibcon#*mode == 0, iclass 4, count 2 2006.252.07:48:08.01#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.252.07:48:08.01#ibcon#[25=AT01-08\r\n] 2006.252.07:48:08.01#ibcon#*before write, iclass 4, count 2 2006.252.07:48:08.01#ibcon#enter sib2, iclass 4, count 2 2006.252.07:48:08.01#ibcon#flushed, iclass 4, count 2 2006.252.07:48:08.01#ibcon#about to write, iclass 4, count 2 2006.252.07:48:08.01#ibcon#wrote, iclass 4, count 2 2006.252.07:48:08.01#ibcon#about to read 3, iclass 4, count 2 2006.252.07:48:08.04#ibcon#read 3, iclass 4, count 2 2006.252.07:48:08.04#ibcon#about to read 4, iclass 4, count 2 2006.252.07:48:08.04#ibcon#read 4, iclass 4, count 2 2006.252.07:48:08.04#ibcon#about to read 5, iclass 4, count 2 2006.252.07:48:08.04#ibcon#read 5, iclass 4, count 2 2006.252.07:48:08.04#ibcon#about to read 6, iclass 4, count 2 2006.252.07:48:08.04#ibcon#read 6, iclass 4, count 2 2006.252.07:48:08.04#ibcon#end of sib2, iclass 4, count 2 2006.252.07:48:08.04#ibcon#*after write, iclass 4, count 2 2006.252.07:48:08.04#ibcon#*before return 0, iclass 4, count 2 2006.252.07:48:08.04#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.252.07:48:08.04#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.252.07:48:08.04#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.252.07:48:08.04#ibcon#ireg 7 cls_cnt 0 2006.252.07:48:08.04#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.252.07:48:08.16#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.252.07:48:08.16#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.252.07:48:08.16#ibcon#enter wrdev, iclass 4, count 0 2006.252.07:48:08.16#ibcon#first serial, iclass 4, count 0 2006.252.07:48:08.16#ibcon#enter sib2, iclass 4, count 0 2006.252.07:48:08.16#ibcon#flushed, iclass 4, count 0 2006.252.07:48:08.16#ibcon#about to write, iclass 4, count 0 2006.252.07:48:08.16#ibcon#wrote, iclass 4, count 0 2006.252.07:48:08.16#ibcon#about to read 3, iclass 4, count 0 2006.252.07:48:08.18#ibcon#read 3, iclass 4, count 0 2006.252.07:48:08.18#ibcon#about to read 4, iclass 4, count 0 2006.252.07:48:08.18#ibcon#read 4, iclass 4, count 0 2006.252.07:48:08.18#ibcon#about to read 5, iclass 4, count 0 2006.252.07:48:08.18#ibcon#read 5, iclass 4, count 0 2006.252.07:48:08.18#ibcon#about to read 6, iclass 4, count 0 2006.252.07:48:08.18#ibcon#read 6, iclass 4, count 0 2006.252.07:48:08.18#ibcon#end of sib2, iclass 4, count 0 2006.252.07:48:08.18#ibcon#*mode == 0, iclass 4, count 0 2006.252.07:48:08.18#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.252.07:48:08.18#ibcon#[25=USB\r\n] 2006.252.07:48:08.18#ibcon#*before write, iclass 4, count 0 2006.252.07:48:08.18#ibcon#enter sib2, iclass 4, count 0 2006.252.07:48:08.18#ibcon#flushed, iclass 4, count 0 2006.252.07:48:08.18#ibcon#about to write, iclass 4, count 0 2006.252.07:48:08.18#ibcon#wrote, iclass 4, count 0 2006.252.07:48:08.18#ibcon#about to read 3, iclass 4, count 0 2006.252.07:48:08.21#ibcon#read 3, iclass 4, count 0 2006.252.07:48:08.21#ibcon#about to read 4, iclass 4, count 0 2006.252.07:48:08.21#ibcon#read 4, iclass 4, count 0 2006.252.07:48:08.21#ibcon#about to read 5, iclass 4, count 0 2006.252.07:48:08.21#ibcon#read 5, iclass 4, count 0 2006.252.07:48:08.21#ibcon#about to read 6, iclass 4, count 0 2006.252.07:48:08.21#ibcon#read 6, iclass 4, count 0 2006.252.07:48:08.21#ibcon#end of sib2, iclass 4, count 0 2006.252.07:48:08.21#ibcon#*after write, iclass 4, count 0 2006.252.07:48:08.21#ibcon#*before return 0, iclass 4, count 0 2006.252.07:48:08.21#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.252.07:48:08.21#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.252.07:48:08.21#ibcon#about to clear, iclass 4 cls_cnt 0 2006.252.07:48:08.21#ibcon#cleared, iclass 4 cls_cnt 0 2006.252.07:48:08.21$vc4f8/valo=2,572.99 2006.252.07:48:08.21#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.252.07:48:08.21#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.252.07:48:08.21#ibcon#ireg 17 cls_cnt 0 2006.252.07:48:08.21#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.252.07:48:08.21#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.252.07:48:08.21#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.252.07:48:08.21#ibcon#enter wrdev, iclass 6, count 0 2006.252.07:48:08.21#ibcon#first serial, iclass 6, count 0 2006.252.07:48:08.21#ibcon#enter sib2, iclass 6, count 0 2006.252.07:48:08.21#ibcon#flushed, iclass 6, count 0 2006.252.07:48:08.21#ibcon#about to write, iclass 6, count 0 2006.252.07:48:08.21#ibcon#wrote, iclass 6, count 0 2006.252.07:48:08.21#ibcon#about to read 3, iclass 6, count 0 2006.252.07:48:08.24#ibcon#read 3, iclass 6, count 0 2006.252.07:48:08.24#ibcon#about to read 4, iclass 6, count 0 2006.252.07:48:08.24#ibcon#read 4, iclass 6, count 0 2006.252.07:48:08.24#ibcon#about to read 5, iclass 6, count 0 2006.252.07:48:08.24#ibcon#read 5, iclass 6, count 0 2006.252.07:48:08.24#ibcon#about to read 6, iclass 6, count 0 2006.252.07:48:08.24#ibcon#read 6, iclass 6, count 0 2006.252.07:48:08.24#ibcon#end of sib2, iclass 6, count 0 2006.252.07:48:08.24#ibcon#*mode == 0, iclass 6, count 0 2006.252.07:48:08.24#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.252.07:48:08.24#ibcon#[26=FRQ=02,572.99\r\n] 2006.252.07:48:08.24#ibcon#*before write, iclass 6, count 0 2006.252.07:48:08.24#ibcon#enter sib2, iclass 6, count 0 2006.252.07:48:08.24#ibcon#flushed, iclass 6, count 0 2006.252.07:48:08.24#ibcon#about to write, iclass 6, count 0 2006.252.07:48:08.24#ibcon#wrote, iclass 6, count 0 2006.252.07:48:08.24#ibcon#about to read 3, iclass 6, count 0 2006.252.07:48:08.28#ibcon#read 3, iclass 6, count 0 2006.252.07:48:08.28#ibcon#about to read 4, iclass 6, count 0 2006.252.07:48:08.28#ibcon#read 4, iclass 6, count 0 2006.252.07:48:08.28#ibcon#about to read 5, iclass 6, count 0 2006.252.07:48:08.28#ibcon#read 5, iclass 6, count 0 2006.252.07:48:08.28#ibcon#about to read 6, iclass 6, count 0 2006.252.07:48:08.28#ibcon#read 6, iclass 6, count 0 2006.252.07:48:08.28#ibcon#end of sib2, iclass 6, count 0 2006.252.07:48:08.28#ibcon#*after write, iclass 6, count 0 2006.252.07:48:08.28#ibcon#*before return 0, iclass 6, count 0 2006.252.07:48:08.28#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.252.07:48:08.28#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.252.07:48:08.28#ibcon#about to clear, iclass 6 cls_cnt 0 2006.252.07:48:08.28#ibcon#cleared, iclass 6 cls_cnt 0 2006.252.07:48:08.28$vc4f8/va=2,7 2006.252.07:48:08.28#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.252.07:48:08.28#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.252.07:48:08.28#ibcon#ireg 11 cls_cnt 2 2006.252.07:48:08.28#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.252.07:48:08.33#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.252.07:48:08.33#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.252.07:48:08.33#ibcon#enter wrdev, iclass 10, count 2 2006.252.07:48:08.33#ibcon#first serial, iclass 10, count 2 2006.252.07:48:08.33#ibcon#enter sib2, iclass 10, count 2 2006.252.07:48:08.33#ibcon#flushed, iclass 10, count 2 2006.252.07:48:08.33#ibcon#about to write, iclass 10, count 2 2006.252.07:48:08.33#ibcon#wrote, iclass 10, count 2 2006.252.07:48:08.33#ibcon#about to read 3, iclass 10, count 2 2006.252.07:48:08.35#ibcon#read 3, iclass 10, count 2 2006.252.07:48:08.35#ibcon#about to read 4, iclass 10, count 2 2006.252.07:48:08.35#ibcon#read 4, iclass 10, count 2 2006.252.07:48:08.35#ibcon#about to read 5, iclass 10, count 2 2006.252.07:48:08.35#ibcon#read 5, iclass 10, count 2 2006.252.07:48:08.35#ibcon#about to read 6, iclass 10, count 2 2006.252.07:48:08.35#ibcon#read 6, iclass 10, count 2 2006.252.07:48:08.35#ibcon#end of sib2, iclass 10, count 2 2006.252.07:48:08.35#ibcon#*mode == 0, iclass 10, count 2 2006.252.07:48:08.35#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.252.07:48:08.35#ibcon#[25=AT02-07\r\n] 2006.252.07:48:08.35#ibcon#*before write, iclass 10, count 2 2006.252.07:48:08.35#ibcon#enter sib2, iclass 10, count 2 2006.252.07:48:08.35#ibcon#flushed, iclass 10, count 2 2006.252.07:48:08.35#ibcon#about to write, iclass 10, count 2 2006.252.07:48:08.35#ibcon#wrote, iclass 10, count 2 2006.252.07:48:08.35#ibcon#about to read 3, iclass 10, count 2 2006.252.07:48:08.38#ibcon#read 3, iclass 10, count 2 2006.252.07:48:08.38#ibcon#about to read 4, iclass 10, count 2 2006.252.07:48:08.38#ibcon#read 4, iclass 10, count 2 2006.252.07:48:08.38#ibcon#about to read 5, iclass 10, count 2 2006.252.07:48:08.38#ibcon#read 5, iclass 10, count 2 2006.252.07:48:08.38#ibcon#about to read 6, iclass 10, count 2 2006.252.07:48:08.38#ibcon#read 6, iclass 10, count 2 2006.252.07:48:08.38#ibcon#end of sib2, iclass 10, count 2 2006.252.07:48:08.38#ibcon#*after write, iclass 10, count 2 2006.252.07:48:08.38#ibcon#*before return 0, iclass 10, count 2 2006.252.07:48:08.38#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.252.07:48:08.38#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.252.07:48:08.38#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.252.07:48:08.38#ibcon#ireg 7 cls_cnt 0 2006.252.07:48:08.38#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.252.07:48:08.50#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.252.07:48:08.50#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.252.07:48:08.50#ibcon#enter wrdev, iclass 10, count 0 2006.252.07:48:08.50#ibcon#first serial, iclass 10, count 0 2006.252.07:48:08.50#ibcon#enter sib2, iclass 10, count 0 2006.252.07:48:08.50#ibcon#flushed, iclass 10, count 0 2006.252.07:48:08.50#ibcon#about to write, iclass 10, count 0 2006.252.07:48:08.50#ibcon#wrote, iclass 10, count 0 2006.252.07:48:08.50#ibcon#about to read 3, iclass 10, count 0 2006.252.07:48:08.52#ibcon#read 3, iclass 10, count 0 2006.252.07:48:08.52#ibcon#about to read 4, iclass 10, count 0 2006.252.07:48:08.52#ibcon#read 4, iclass 10, count 0 2006.252.07:48:08.52#ibcon#about to read 5, iclass 10, count 0 2006.252.07:48:08.52#ibcon#read 5, iclass 10, count 0 2006.252.07:48:08.52#ibcon#about to read 6, iclass 10, count 0 2006.252.07:48:08.52#ibcon#read 6, iclass 10, count 0 2006.252.07:48:08.52#ibcon#end of sib2, iclass 10, count 0 2006.252.07:48:08.52#ibcon#*mode == 0, iclass 10, count 0 2006.252.07:48:08.52#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.252.07:48:08.52#ibcon#[25=USB\r\n] 2006.252.07:48:08.52#ibcon#*before write, iclass 10, count 0 2006.252.07:48:08.52#ibcon#enter sib2, iclass 10, count 0 2006.252.07:48:08.52#ibcon#flushed, iclass 10, count 0 2006.252.07:48:08.52#ibcon#about to write, iclass 10, count 0 2006.252.07:48:08.52#ibcon#wrote, iclass 10, count 0 2006.252.07:48:08.52#ibcon#about to read 3, iclass 10, count 0 2006.252.07:48:08.55#ibcon#read 3, iclass 10, count 0 2006.252.07:48:08.55#ibcon#about to read 4, iclass 10, count 0 2006.252.07:48:08.55#ibcon#read 4, iclass 10, count 0 2006.252.07:48:08.55#ibcon#about to read 5, iclass 10, count 0 2006.252.07:48:08.55#ibcon#read 5, iclass 10, count 0 2006.252.07:48:08.55#ibcon#about to read 6, iclass 10, count 0 2006.252.07:48:08.55#ibcon#read 6, iclass 10, count 0 2006.252.07:48:08.55#ibcon#end of sib2, iclass 10, count 0 2006.252.07:48:08.55#ibcon#*after write, iclass 10, count 0 2006.252.07:48:08.55#ibcon#*before return 0, iclass 10, count 0 2006.252.07:48:08.55#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.252.07:48:08.55#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.252.07:48:08.55#ibcon#about to clear, iclass 10 cls_cnt 0 2006.252.07:48:08.55#ibcon#cleared, iclass 10 cls_cnt 0 2006.252.07:48:08.55$vc4f8/valo=3,672.99 2006.252.07:48:08.55#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.252.07:48:08.55#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.252.07:48:08.55#ibcon#ireg 17 cls_cnt 0 2006.252.07:48:08.55#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.252.07:48:08.55#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.252.07:48:08.55#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.252.07:48:08.55#ibcon#enter wrdev, iclass 12, count 0 2006.252.07:48:08.55#ibcon#first serial, iclass 12, count 0 2006.252.07:48:08.55#ibcon#enter sib2, iclass 12, count 0 2006.252.07:48:08.55#ibcon#flushed, iclass 12, count 0 2006.252.07:48:08.55#ibcon#about to write, iclass 12, count 0 2006.252.07:48:08.55#ibcon#wrote, iclass 12, count 0 2006.252.07:48:08.55#ibcon#about to read 3, iclass 12, count 0 2006.252.07:48:08.58#ibcon#read 3, iclass 12, count 0 2006.252.07:48:08.58#ibcon#about to read 4, iclass 12, count 0 2006.252.07:48:08.58#ibcon#read 4, iclass 12, count 0 2006.252.07:48:08.58#ibcon#about to read 5, iclass 12, count 0 2006.252.07:48:08.58#ibcon#read 5, iclass 12, count 0 2006.252.07:48:08.58#ibcon#about to read 6, iclass 12, count 0 2006.252.07:48:08.58#ibcon#read 6, iclass 12, count 0 2006.252.07:48:08.58#ibcon#end of sib2, iclass 12, count 0 2006.252.07:48:08.58#ibcon#*mode == 0, iclass 12, count 0 2006.252.07:48:08.58#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.252.07:48:08.58#ibcon#[26=FRQ=03,672.99\r\n] 2006.252.07:48:08.58#ibcon#*before write, iclass 12, count 0 2006.252.07:48:08.58#ibcon#enter sib2, iclass 12, count 0 2006.252.07:48:08.58#ibcon#flushed, iclass 12, count 0 2006.252.07:48:08.58#ibcon#about to write, iclass 12, count 0 2006.252.07:48:08.58#ibcon#wrote, iclass 12, count 0 2006.252.07:48:08.58#ibcon#about to read 3, iclass 12, count 0 2006.252.07:48:08.62#ibcon#read 3, iclass 12, count 0 2006.252.07:48:08.62#ibcon#about to read 4, iclass 12, count 0 2006.252.07:48:08.62#ibcon#read 4, iclass 12, count 0 2006.252.07:48:08.62#ibcon#about to read 5, iclass 12, count 0 2006.252.07:48:08.62#ibcon#read 5, iclass 12, count 0 2006.252.07:48:08.62#ibcon#about to read 6, iclass 12, count 0 2006.252.07:48:08.62#ibcon#read 6, iclass 12, count 0 2006.252.07:48:08.62#ibcon#end of sib2, iclass 12, count 0 2006.252.07:48:08.62#ibcon#*after write, iclass 12, count 0 2006.252.07:48:08.62#ibcon#*before return 0, iclass 12, count 0 2006.252.07:48:08.62#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.252.07:48:08.62#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.252.07:48:08.62#ibcon#about to clear, iclass 12 cls_cnt 0 2006.252.07:48:08.62#ibcon#cleared, iclass 12 cls_cnt 0 2006.252.07:48:08.62$vc4f8/va=3,6 2006.252.07:48:08.62#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.252.07:48:08.62#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.252.07:48:08.62#ibcon#ireg 11 cls_cnt 2 2006.252.07:48:08.62#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.252.07:48:08.67#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.252.07:48:08.67#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.252.07:48:08.67#ibcon#enter wrdev, iclass 14, count 2 2006.252.07:48:08.67#ibcon#first serial, iclass 14, count 2 2006.252.07:48:08.67#ibcon#enter sib2, iclass 14, count 2 2006.252.07:48:08.67#ibcon#flushed, iclass 14, count 2 2006.252.07:48:08.67#ibcon#about to write, iclass 14, count 2 2006.252.07:48:08.67#ibcon#wrote, iclass 14, count 2 2006.252.07:48:08.67#ibcon#about to read 3, iclass 14, count 2 2006.252.07:48:08.69#ibcon#read 3, iclass 14, count 2 2006.252.07:48:08.69#ibcon#about to read 4, iclass 14, count 2 2006.252.07:48:08.69#ibcon#read 4, iclass 14, count 2 2006.252.07:48:08.69#ibcon#about to read 5, iclass 14, count 2 2006.252.07:48:08.69#ibcon#read 5, iclass 14, count 2 2006.252.07:48:08.69#ibcon#about to read 6, iclass 14, count 2 2006.252.07:48:08.69#ibcon#read 6, iclass 14, count 2 2006.252.07:48:08.69#ibcon#end of sib2, iclass 14, count 2 2006.252.07:48:08.69#ibcon#*mode == 0, iclass 14, count 2 2006.252.07:48:08.69#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.252.07:48:08.69#ibcon#[25=AT03-06\r\n] 2006.252.07:48:08.69#ibcon#*before write, iclass 14, count 2 2006.252.07:48:08.69#ibcon#enter sib2, iclass 14, count 2 2006.252.07:48:08.69#ibcon#flushed, iclass 14, count 2 2006.252.07:48:08.69#ibcon#about to write, iclass 14, count 2 2006.252.07:48:08.69#ibcon#wrote, iclass 14, count 2 2006.252.07:48:08.69#ibcon#about to read 3, iclass 14, count 2 2006.252.07:48:08.72#ibcon#read 3, iclass 14, count 2 2006.252.07:48:08.72#ibcon#about to read 4, iclass 14, count 2 2006.252.07:48:08.72#ibcon#read 4, iclass 14, count 2 2006.252.07:48:08.72#ibcon#about to read 5, iclass 14, count 2 2006.252.07:48:08.72#ibcon#read 5, iclass 14, count 2 2006.252.07:48:08.72#ibcon#about to read 6, iclass 14, count 2 2006.252.07:48:08.72#ibcon#read 6, iclass 14, count 2 2006.252.07:48:08.72#ibcon#end of sib2, iclass 14, count 2 2006.252.07:48:08.72#ibcon#*after write, iclass 14, count 2 2006.252.07:48:08.72#ibcon#*before return 0, iclass 14, count 2 2006.252.07:48:08.72#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.252.07:48:08.72#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.252.07:48:08.72#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.252.07:48:08.72#ibcon#ireg 7 cls_cnt 0 2006.252.07:48:08.72#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.252.07:48:08.79#abcon#<5=/05 3.5 6.8 27.39 901011.2\r\n> 2006.252.07:48:08.81#abcon#{5=INTERFACE CLEAR} 2006.252.07:48:08.84#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.252.07:48:08.84#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.252.07:48:08.84#ibcon#enter wrdev, iclass 14, count 0 2006.252.07:48:08.84#ibcon#first serial, iclass 14, count 0 2006.252.07:48:08.84#ibcon#enter sib2, iclass 14, count 0 2006.252.07:48:08.84#ibcon#flushed, iclass 14, count 0 2006.252.07:48:08.84#ibcon#about to write, iclass 14, count 0 2006.252.07:48:08.84#ibcon#wrote, iclass 14, count 0 2006.252.07:48:08.84#ibcon#about to read 3, iclass 14, count 0 2006.252.07:48:08.88#ibcon#read 3, iclass 14, count 0 2006.252.07:48:08.88#ibcon#about to read 4, iclass 14, count 0 2006.252.07:48:08.88#ibcon#read 4, iclass 14, count 0 2006.252.07:48:08.88#ibcon#about to read 5, iclass 14, count 0 2006.252.07:48:08.88#ibcon#read 5, iclass 14, count 0 2006.252.07:48:08.88#ibcon#about to read 6, iclass 14, count 0 2006.252.07:48:08.88#ibcon#read 6, iclass 14, count 0 2006.252.07:48:08.88#ibcon#end of sib2, iclass 14, count 0 2006.252.07:48:08.88#ibcon#*mode == 0, iclass 14, count 0 2006.252.07:48:08.88#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.252.07:48:08.88#ibcon#[25=USB\r\n] 2006.252.07:48:08.88#ibcon#*before write, iclass 14, count 0 2006.252.07:48:08.88#ibcon#enter sib2, iclass 14, count 0 2006.252.07:48:08.88#ibcon#flushed, iclass 14, count 0 2006.252.07:48:08.88#ibcon#about to write, iclass 14, count 0 2006.252.07:48:08.88#ibcon#wrote, iclass 14, count 0 2006.252.07:48:08.88#ibcon#about to read 3, iclass 14, count 0 2006.252.07:48:08.89#abcon#[5=S1D000X0/0*\r\n] 2006.252.07:48:08.90#ibcon#read 3, iclass 14, count 0 2006.252.07:48:08.90#ibcon#about to read 4, iclass 14, count 0 2006.252.07:48:08.90#ibcon#read 4, iclass 14, count 0 2006.252.07:48:08.90#ibcon#about to read 5, iclass 14, count 0 2006.252.07:48:08.90#ibcon#read 5, iclass 14, count 0 2006.252.07:48:08.90#ibcon#about to read 6, iclass 14, count 0 2006.252.07:48:08.90#ibcon#read 6, iclass 14, count 0 2006.252.07:48:08.90#ibcon#end of sib2, iclass 14, count 0 2006.252.07:48:08.90#ibcon#*after write, iclass 14, count 0 2006.252.07:48:08.90#ibcon#*before return 0, iclass 14, count 0 2006.252.07:48:08.90#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.252.07:48:08.90#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.252.07:48:08.90#ibcon#about to clear, iclass 14 cls_cnt 0 2006.252.07:48:08.90#ibcon#cleared, iclass 14 cls_cnt 0 2006.252.07:48:08.90$vc4f8/valo=4,832.99 2006.252.07:48:08.90#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.252.07:48:08.90#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.252.07:48:08.90#ibcon#ireg 17 cls_cnt 0 2006.252.07:48:08.90#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.252.07:48:08.90#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.252.07:48:08.90#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.252.07:48:08.90#ibcon#enter wrdev, iclass 20, count 0 2006.252.07:48:08.90#ibcon#first serial, iclass 20, count 0 2006.252.07:48:08.90#ibcon#enter sib2, iclass 20, count 0 2006.252.07:48:08.90#ibcon#flushed, iclass 20, count 0 2006.252.07:48:08.90#ibcon#about to write, iclass 20, count 0 2006.252.07:48:08.90#ibcon#wrote, iclass 20, count 0 2006.252.07:48:08.90#ibcon#about to read 3, iclass 20, count 0 2006.252.07:48:08.92#ibcon#read 3, iclass 20, count 0 2006.252.07:48:08.92#ibcon#about to read 4, iclass 20, count 0 2006.252.07:48:08.92#ibcon#read 4, iclass 20, count 0 2006.252.07:48:08.92#ibcon#about to read 5, iclass 20, count 0 2006.252.07:48:08.92#ibcon#read 5, iclass 20, count 0 2006.252.07:48:08.92#ibcon#about to read 6, iclass 20, count 0 2006.252.07:48:08.92#ibcon#read 6, iclass 20, count 0 2006.252.07:48:08.92#ibcon#end of sib2, iclass 20, count 0 2006.252.07:48:08.92#ibcon#*mode == 0, iclass 20, count 0 2006.252.07:48:08.92#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.252.07:48:08.92#ibcon#[26=FRQ=04,832.99\r\n] 2006.252.07:48:08.92#ibcon#*before write, iclass 20, count 0 2006.252.07:48:08.92#ibcon#enter sib2, iclass 20, count 0 2006.252.07:48:08.92#ibcon#flushed, iclass 20, count 0 2006.252.07:48:08.92#ibcon#about to write, iclass 20, count 0 2006.252.07:48:08.92#ibcon#wrote, iclass 20, count 0 2006.252.07:48:08.92#ibcon#about to read 3, iclass 20, count 0 2006.252.07:48:08.96#ibcon#read 3, iclass 20, count 0 2006.252.07:48:08.96#ibcon#about to read 4, iclass 20, count 0 2006.252.07:48:08.96#ibcon#read 4, iclass 20, count 0 2006.252.07:48:08.96#ibcon#about to read 5, iclass 20, count 0 2006.252.07:48:08.96#ibcon#read 5, iclass 20, count 0 2006.252.07:48:08.96#ibcon#about to read 6, iclass 20, count 0 2006.252.07:48:08.96#ibcon#read 6, iclass 20, count 0 2006.252.07:48:08.96#ibcon#end of sib2, iclass 20, count 0 2006.252.07:48:08.96#ibcon#*after write, iclass 20, count 0 2006.252.07:48:08.96#ibcon#*before return 0, iclass 20, count 0 2006.252.07:48:08.96#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.252.07:48:08.96#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.252.07:48:08.96#ibcon#about to clear, iclass 20 cls_cnt 0 2006.252.07:48:08.96#ibcon#cleared, iclass 20 cls_cnt 0 2006.252.07:48:08.96$vc4f8/va=4,7 2006.252.07:48:08.96#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.252.07:48:08.96#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.252.07:48:08.96#ibcon#ireg 11 cls_cnt 2 2006.252.07:48:08.96#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.252.07:48:09.02#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.252.07:48:09.02#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.252.07:48:09.02#ibcon#enter wrdev, iclass 22, count 2 2006.252.07:48:09.02#ibcon#first serial, iclass 22, count 2 2006.252.07:48:09.02#ibcon#enter sib2, iclass 22, count 2 2006.252.07:48:09.02#ibcon#flushed, iclass 22, count 2 2006.252.07:48:09.02#ibcon#about to write, iclass 22, count 2 2006.252.07:48:09.02#ibcon#wrote, iclass 22, count 2 2006.252.07:48:09.02#ibcon#about to read 3, iclass 22, count 2 2006.252.07:48:09.04#ibcon#read 3, iclass 22, count 2 2006.252.07:48:09.04#ibcon#about to read 4, iclass 22, count 2 2006.252.07:48:09.04#ibcon#read 4, iclass 22, count 2 2006.252.07:48:09.04#ibcon#about to read 5, iclass 22, count 2 2006.252.07:48:09.04#ibcon#read 5, iclass 22, count 2 2006.252.07:48:09.04#ibcon#about to read 6, iclass 22, count 2 2006.252.07:48:09.04#ibcon#read 6, iclass 22, count 2 2006.252.07:48:09.04#ibcon#end of sib2, iclass 22, count 2 2006.252.07:48:09.04#ibcon#*mode == 0, iclass 22, count 2 2006.252.07:48:09.04#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.252.07:48:09.04#ibcon#[25=AT04-07\r\n] 2006.252.07:48:09.04#ibcon#*before write, iclass 22, count 2 2006.252.07:48:09.04#ibcon#enter sib2, iclass 22, count 2 2006.252.07:48:09.04#ibcon#flushed, iclass 22, count 2 2006.252.07:48:09.04#ibcon#about to write, iclass 22, count 2 2006.252.07:48:09.04#ibcon#wrote, iclass 22, count 2 2006.252.07:48:09.04#ibcon#about to read 3, iclass 22, count 2 2006.252.07:48:09.07#ibcon#read 3, iclass 22, count 2 2006.252.07:48:09.07#ibcon#about to read 4, iclass 22, count 2 2006.252.07:48:09.07#ibcon#read 4, iclass 22, count 2 2006.252.07:48:09.07#ibcon#about to read 5, iclass 22, count 2 2006.252.07:48:09.07#ibcon#read 5, iclass 22, count 2 2006.252.07:48:09.07#ibcon#about to read 6, iclass 22, count 2 2006.252.07:48:09.07#ibcon#read 6, iclass 22, count 2 2006.252.07:48:09.07#ibcon#end of sib2, iclass 22, count 2 2006.252.07:48:09.07#ibcon#*after write, iclass 22, count 2 2006.252.07:48:09.07#ibcon#*before return 0, iclass 22, count 2 2006.252.07:48:09.07#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.252.07:48:09.07#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.252.07:48:09.07#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.252.07:48:09.07#ibcon#ireg 7 cls_cnt 0 2006.252.07:48:09.07#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.252.07:48:09.19#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.252.07:48:09.19#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.252.07:48:09.19#ibcon#enter wrdev, iclass 22, count 0 2006.252.07:48:09.19#ibcon#first serial, iclass 22, count 0 2006.252.07:48:09.19#ibcon#enter sib2, iclass 22, count 0 2006.252.07:48:09.19#ibcon#flushed, iclass 22, count 0 2006.252.07:48:09.19#ibcon#about to write, iclass 22, count 0 2006.252.07:48:09.19#ibcon#wrote, iclass 22, count 0 2006.252.07:48:09.19#ibcon#about to read 3, iclass 22, count 0 2006.252.07:48:09.21#ibcon#read 3, iclass 22, count 0 2006.252.07:48:09.21#ibcon#about to read 4, iclass 22, count 0 2006.252.07:48:09.21#ibcon#read 4, iclass 22, count 0 2006.252.07:48:09.21#ibcon#about to read 5, iclass 22, count 0 2006.252.07:48:09.21#ibcon#read 5, iclass 22, count 0 2006.252.07:48:09.21#ibcon#about to read 6, iclass 22, count 0 2006.252.07:48:09.21#ibcon#read 6, iclass 22, count 0 2006.252.07:48:09.21#ibcon#end of sib2, iclass 22, count 0 2006.252.07:48:09.21#ibcon#*mode == 0, iclass 22, count 0 2006.252.07:48:09.21#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.252.07:48:09.21#ibcon#[25=USB\r\n] 2006.252.07:48:09.21#ibcon#*before write, iclass 22, count 0 2006.252.07:48:09.21#ibcon#enter sib2, iclass 22, count 0 2006.252.07:48:09.21#ibcon#flushed, iclass 22, count 0 2006.252.07:48:09.21#ibcon#about to write, iclass 22, count 0 2006.252.07:48:09.21#ibcon#wrote, iclass 22, count 0 2006.252.07:48:09.21#ibcon#about to read 3, iclass 22, count 0 2006.252.07:48:09.24#ibcon#read 3, iclass 22, count 0 2006.252.07:48:09.24#ibcon#about to read 4, iclass 22, count 0 2006.252.07:48:09.24#ibcon#read 4, iclass 22, count 0 2006.252.07:48:09.24#ibcon#about to read 5, iclass 22, count 0 2006.252.07:48:09.24#ibcon#read 5, iclass 22, count 0 2006.252.07:48:09.24#ibcon#about to read 6, iclass 22, count 0 2006.252.07:48:09.24#ibcon#read 6, iclass 22, count 0 2006.252.07:48:09.24#ibcon#end of sib2, iclass 22, count 0 2006.252.07:48:09.24#ibcon#*after write, iclass 22, count 0 2006.252.07:48:09.24#ibcon#*before return 0, iclass 22, count 0 2006.252.07:48:09.24#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.252.07:48:09.24#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.252.07:48:09.24#ibcon#about to clear, iclass 22 cls_cnt 0 2006.252.07:48:09.24#ibcon#cleared, iclass 22 cls_cnt 0 2006.252.07:48:09.24$vc4f8/valo=5,652.99 2006.252.07:48:09.24#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.252.07:48:09.24#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.252.07:48:09.24#ibcon#ireg 17 cls_cnt 0 2006.252.07:48:09.24#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.252.07:48:09.24#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.252.07:48:09.24#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.252.07:48:09.24#ibcon#enter wrdev, iclass 24, count 0 2006.252.07:48:09.24#ibcon#first serial, iclass 24, count 0 2006.252.07:48:09.24#ibcon#enter sib2, iclass 24, count 0 2006.252.07:48:09.24#ibcon#flushed, iclass 24, count 0 2006.252.07:48:09.24#ibcon#about to write, iclass 24, count 0 2006.252.07:48:09.24#ibcon#wrote, iclass 24, count 0 2006.252.07:48:09.24#ibcon#about to read 3, iclass 24, count 0 2006.252.07:48:09.26#ibcon#read 3, iclass 24, count 0 2006.252.07:48:09.26#ibcon#about to read 4, iclass 24, count 0 2006.252.07:48:09.26#ibcon#read 4, iclass 24, count 0 2006.252.07:48:09.26#ibcon#about to read 5, iclass 24, count 0 2006.252.07:48:09.26#ibcon#read 5, iclass 24, count 0 2006.252.07:48:09.26#ibcon#about to read 6, iclass 24, count 0 2006.252.07:48:09.26#ibcon#read 6, iclass 24, count 0 2006.252.07:48:09.26#ibcon#end of sib2, iclass 24, count 0 2006.252.07:48:09.26#ibcon#*mode == 0, iclass 24, count 0 2006.252.07:48:09.26#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.252.07:48:09.26#ibcon#[26=FRQ=05,652.99\r\n] 2006.252.07:48:09.26#ibcon#*before write, iclass 24, count 0 2006.252.07:48:09.26#ibcon#enter sib2, iclass 24, count 0 2006.252.07:48:09.26#ibcon#flushed, iclass 24, count 0 2006.252.07:48:09.26#ibcon#about to write, iclass 24, count 0 2006.252.07:48:09.26#ibcon#wrote, iclass 24, count 0 2006.252.07:48:09.26#ibcon#about to read 3, iclass 24, count 0 2006.252.07:48:09.30#ibcon#read 3, iclass 24, count 0 2006.252.07:48:09.30#ibcon#about to read 4, iclass 24, count 0 2006.252.07:48:09.30#ibcon#read 4, iclass 24, count 0 2006.252.07:48:09.30#ibcon#about to read 5, iclass 24, count 0 2006.252.07:48:09.30#ibcon#read 5, iclass 24, count 0 2006.252.07:48:09.30#ibcon#about to read 6, iclass 24, count 0 2006.252.07:48:09.30#ibcon#read 6, iclass 24, count 0 2006.252.07:48:09.30#ibcon#end of sib2, iclass 24, count 0 2006.252.07:48:09.30#ibcon#*after write, iclass 24, count 0 2006.252.07:48:09.30#ibcon#*before return 0, iclass 24, count 0 2006.252.07:48:09.30#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.252.07:48:09.30#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.252.07:48:09.30#ibcon#about to clear, iclass 24 cls_cnt 0 2006.252.07:48:09.30#ibcon#cleared, iclass 24 cls_cnt 0 2006.252.07:48:09.30$vc4f8/va=5,7 2006.252.07:48:09.30#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.252.07:48:09.30#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.252.07:48:09.30#ibcon#ireg 11 cls_cnt 2 2006.252.07:48:09.30#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.252.07:48:09.36#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.252.07:48:09.36#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.252.07:48:09.36#ibcon#enter wrdev, iclass 26, count 2 2006.252.07:48:09.36#ibcon#first serial, iclass 26, count 2 2006.252.07:48:09.36#ibcon#enter sib2, iclass 26, count 2 2006.252.07:48:09.36#ibcon#flushed, iclass 26, count 2 2006.252.07:48:09.36#ibcon#about to write, iclass 26, count 2 2006.252.07:48:09.36#ibcon#wrote, iclass 26, count 2 2006.252.07:48:09.36#ibcon#about to read 3, iclass 26, count 2 2006.252.07:48:09.38#ibcon#read 3, iclass 26, count 2 2006.252.07:48:09.38#ibcon#about to read 4, iclass 26, count 2 2006.252.07:48:09.38#ibcon#read 4, iclass 26, count 2 2006.252.07:48:09.38#ibcon#about to read 5, iclass 26, count 2 2006.252.07:48:09.38#ibcon#read 5, iclass 26, count 2 2006.252.07:48:09.38#ibcon#about to read 6, iclass 26, count 2 2006.252.07:48:09.38#ibcon#read 6, iclass 26, count 2 2006.252.07:48:09.38#ibcon#end of sib2, iclass 26, count 2 2006.252.07:48:09.38#ibcon#*mode == 0, iclass 26, count 2 2006.252.07:48:09.38#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.252.07:48:09.38#ibcon#[25=AT05-07\r\n] 2006.252.07:48:09.38#ibcon#*before write, iclass 26, count 2 2006.252.07:48:09.38#ibcon#enter sib2, iclass 26, count 2 2006.252.07:48:09.38#ibcon#flushed, iclass 26, count 2 2006.252.07:48:09.38#ibcon#about to write, iclass 26, count 2 2006.252.07:48:09.38#ibcon#wrote, iclass 26, count 2 2006.252.07:48:09.38#ibcon#about to read 3, iclass 26, count 2 2006.252.07:48:09.41#ibcon#read 3, iclass 26, count 2 2006.252.07:48:09.41#ibcon#about to read 4, iclass 26, count 2 2006.252.07:48:09.41#ibcon#read 4, iclass 26, count 2 2006.252.07:48:09.41#ibcon#about to read 5, iclass 26, count 2 2006.252.07:48:09.41#ibcon#read 5, iclass 26, count 2 2006.252.07:48:09.41#ibcon#about to read 6, iclass 26, count 2 2006.252.07:48:09.41#ibcon#read 6, iclass 26, count 2 2006.252.07:48:09.41#ibcon#end of sib2, iclass 26, count 2 2006.252.07:48:09.41#ibcon#*after write, iclass 26, count 2 2006.252.07:48:09.41#ibcon#*before return 0, iclass 26, count 2 2006.252.07:48:09.41#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.252.07:48:09.41#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.252.07:48:09.41#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.252.07:48:09.41#ibcon#ireg 7 cls_cnt 0 2006.252.07:48:09.41#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.252.07:48:09.54#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.252.07:48:09.54#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.252.07:48:09.54#ibcon#enter wrdev, iclass 26, count 0 2006.252.07:48:09.54#ibcon#first serial, iclass 26, count 0 2006.252.07:48:09.54#ibcon#enter sib2, iclass 26, count 0 2006.252.07:48:09.54#ibcon#flushed, iclass 26, count 0 2006.252.07:48:09.54#ibcon#about to write, iclass 26, count 0 2006.252.07:48:09.54#ibcon#wrote, iclass 26, count 0 2006.252.07:48:09.54#ibcon#about to read 3, iclass 26, count 0 2006.252.07:48:09.55#ibcon#read 3, iclass 26, count 0 2006.252.07:48:09.55#ibcon#about to read 4, iclass 26, count 0 2006.252.07:48:09.55#ibcon#read 4, iclass 26, count 0 2006.252.07:48:09.55#ibcon#about to read 5, iclass 26, count 0 2006.252.07:48:09.55#ibcon#read 5, iclass 26, count 0 2006.252.07:48:09.55#ibcon#about to read 6, iclass 26, count 0 2006.252.07:48:09.55#ibcon#read 6, iclass 26, count 0 2006.252.07:48:09.55#ibcon#end of sib2, iclass 26, count 0 2006.252.07:48:09.55#ibcon#*mode == 0, iclass 26, count 0 2006.252.07:48:09.55#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.252.07:48:09.55#ibcon#[25=USB\r\n] 2006.252.07:48:09.55#ibcon#*before write, iclass 26, count 0 2006.252.07:48:09.55#ibcon#enter sib2, iclass 26, count 0 2006.252.07:48:09.55#ibcon#flushed, iclass 26, count 0 2006.252.07:48:09.55#ibcon#about to write, iclass 26, count 0 2006.252.07:48:09.55#ibcon#wrote, iclass 26, count 0 2006.252.07:48:09.55#ibcon#about to read 3, iclass 26, count 0 2006.252.07:48:09.58#ibcon#read 3, iclass 26, count 0 2006.252.07:48:09.58#ibcon#about to read 4, iclass 26, count 0 2006.252.07:48:09.58#ibcon#read 4, iclass 26, count 0 2006.252.07:48:09.58#ibcon#about to read 5, iclass 26, count 0 2006.252.07:48:09.58#ibcon#read 5, iclass 26, count 0 2006.252.07:48:09.58#ibcon#about to read 6, iclass 26, count 0 2006.252.07:48:09.58#ibcon#read 6, iclass 26, count 0 2006.252.07:48:09.58#ibcon#end of sib2, iclass 26, count 0 2006.252.07:48:09.58#ibcon#*after write, iclass 26, count 0 2006.252.07:48:09.58#ibcon#*before return 0, iclass 26, count 0 2006.252.07:48:09.58#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.252.07:48:09.58#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.252.07:48:09.58#ibcon#about to clear, iclass 26 cls_cnt 0 2006.252.07:48:09.58#ibcon#cleared, iclass 26 cls_cnt 0 2006.252.07:48:09.58$vc4f8/valo=6,772.99 2006.252.07:48:09.58#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.252.07:48:09.58#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.252.07:48:09.58#ibcon#ireg 17 cls_cnt 0 2006.252.07:48:09.58#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.252.07:48:09.58#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.252.07:48:09.58#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.252.07:48:09.58#ibcon#enter wrdev, iclass 28, count 0 2006.252.07:48:09.58#ibcon#first serial, iclass 28, count 0 2006.252.07:48:09.58#ibcon#enter sib2, iclass 28, count 0 2006.252.07:48:09.58#ibcon#flushed, iclass 28, count 0 2006.252.07:48:09.58#ibcon#about to write, iclass 28, count 0 2006.252.07:48:09.58#ibcon#wrote, iclass 28, count 0 2006.252.07:48:09.58#ibcon#about to read 3, iclass 28, count 0 2006.252.07:48:09.60#ibcon#read 3, iclass 28, count 0 2006.252.07:48:09.60#ibcon#about to read 4, iclass 28, count 0 2006.252.07:48:09.60#ibcon#read 4, iclass 28, count 0 2006.252.07:48:09.60#ibcon#about to read 5, iclass 28, count 0 2006.252.07:48:09.60#ibcon#read 5, iclass 28, count 0 2006.252.07:48:09.60#ibcon#about to read 6, iclass 28, count 0 2006.252.07:48:09.60#ibcon#read 6, iclass 28, count 0 2006.252.07:48:09.60#ibcon#end of sib2, iclass 28, count 0 2006.252.07:48:09.60#ibcon#*mode == 0, iclass 28, count 0 2006.252.07:48:09.60#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.252.07:48:09.60#ibcon#[26=FRQ=06,772.99\r\n] 2006.252.07:48:09.60#ibcon#*before write, iclass 28, count 0 2006.252.07:48:09.60#ibcon#enter sib2, iclass 28, count 0 2006.252.07:48:09.60#ibcon#flushed, iclass 28, count 0 2006.252.07:48:09.60#ibcon#about to write, iclass 28, count 0 2006.252.07:48:09.60#ibcon#wrote, iclass 28, count 0 2006.252.07:48:09.60#ibcon#about to read 3, iclass 28, count 0 2006.252.07:48:09.64#ibcon#read 3, iclass 28, count 0 2006.252.07:48:09.64#ibcon#about to read 4, iclass 28, count 0 2006.252.07:48:09.64#ibcon#read 4, iclass 28, count 0 2006.252.07:48:09.64#ibcon#about to read 5, iclass 28, count 0 2006.252.07:48:09.64#ibcon#read 5, iclass 28, count 0 2006.252.07:48:09.64#ibcon#about to read 6, iclass 28, count 0 2006.252.07:48:09.64#ibcon#read 6, iclass 28, count 0 2006.252.07:48:09.64#ibcon#end of sib2, iclass 28, count 0 2006.252.07:48:09.64#ibcon#*after write, iclass 28, count 0 2006.252.07:48:09.64#ibcon#*before return 0, iclass 28, count 0 2006.252.07:48:09.64#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.252.07:48:09.64#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.252.07:48:09.64#ibcon#about to clear, iclass 28 cls_cnt 0 2006.252.07:48:09.64#ibcon#cleared, iclass 28 cls_cnt 0 2006.252.07:48:09.64$vc4f8/va=6,7 2006.252.07:48:09.64#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.252.07:48:09.64#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.252.07:48:09.64#ibcon#ireg 11 cls_cnt 2 2006.252.07:48:09.64#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.252.07:48:09.70#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.252.07:48:09.70#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.252.07:48:09.70#ibcon#enter wrdev, iclass 30, count 2 2006.252.07:48:09.70#ibcon#first serial, iclass 30, count 2 2006.252.07:48:09.70#ibcon#enter sib2, iclass 30, count 2 2006.252.07:48:09.70#ibcon#flushed, iclass 30, count 2 2006.252.07:48:09.70#ibcon#about to write, iclass 30, count 2 2006.252.07:48:09.70#ibcon#wrote, iclass 30, count 2 2006.252.07:48:09.70#ibcon#about to read 3, iclass 30, count 2 2006.252.07:48:09.72#ibcon#read 3, iclass 30, count 2 2006.252.07:48:09.72#ibcon#about to read 4, iclass 30, count 2 2006.252.07:48:09.72#ibcon#read 4, iclass 30, count 2 2006.252.07:48:09.72#ibcon#about to read 5, iclass 30, count 2 2006.252.07:48:09.72#ibcon#read 5, iclass 30, count 2 2006.252.07:48:09.72#ibcon#about to read 6, iclass 30, count 2 2006.252.07:48:09.72#ibcon#read 6, iclass 30, count 2 2006.252.07:48:09.72#ibcon#end of sib2, iclass 30, count 2 2006.252.07:48:09.72#ibcon#*mode == 0, iclass 30, count 2 2006.252.07:48:09.72#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.252.07:48:09.72#ibcon#[25=AT06-07\r\n] 2006.252.07:48:09.72#ibcon#*before write, iclass 30, count 2 2006.252.07:48:09.72#ibcon#enter sib2, iclass 30, count 2 2006.252.07:48:09.72#ibcon#flushed, iclass 30, count 2 2006.252.07:48:09.72#ibcon#about to write, iclass 30, count 2 2006.252.07:48:09.72#ibcon#wrote, iclass 30, count 2 2006.252.07:48:09.72#ibcon#about to read 3, iclass 30, count 2 2006.252.07:48:09.75#ibcon#read 3, iclass 30, count 2 2006.252.07:48:09.75#ibcon#about to read 4, iclass 30, count 2 2006.252.07:48:09.75#ibcon#read 4, iclass 30, count 2 2006.252.07:48:09.75#ibcon#about to read 5, iclass 30, count 2 2006.252.07:48:09.75#ibcon#read 5, iclass 30, count 2 2006.252.07:48:09.75#ibcon#about to read 6, iclass 30, count 2 2006.252.07:48:09.75#ibcon#read 6, iclass 30, count 2 2006.252.07:48:09.75#ibcon#end of sib2, iclass 30, count 2 2006.252.07:48:09.75#ibcon#*after write, iclass 30, count 2 2006.252.07:48:09.75#ibcon#*before return 0, iclass 30, count 2 2006.252.07:48:09.75#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.252.07:48:09.75#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.252.07:48:09.75#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.252.07:48:09.75#ibcon#ireg 7 cls_cnt 0 2006.252.07:48:09.75#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.252.07:48:09.87#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.252.07:48:09.87#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.252.07:48:09.87#ibcon#enter wrdev, iclass 30, count 0 2006.252.07:48:09.87#ibcon#first serial, iclass 30, count 0 2006.252.07:48:09.87#ibcon#enter sib2, iclass 30, count 0 2006.252.07:48:09.87#ibcon#flushed, iclass 30, count 0 2006.252.07:48:09.87#ibcon#about to write, iclass 30, count 0 2006.252.07:48:09.87#ibcon#wrote, iclass 30, count 0 2006.252.07:48:09.87#ibcon#about to read 3, iclass 30, count 0 2006.252.07:48:09.89#ibcon#read 3, iclass 30, count 0 2006.252.07:48:09.89#ibcon#about to read 4, iclass 30, count 0 2006.252.07:48:09.89#ibcon#read 4, iclass 30, count 0 2006.252.07:48:09.89#ibcon#about to read 5, iclass 30, count 0 2006.252.07:48:09.89#ibcon#read 5, iclass 30, count 0 2006.252.07:48:09.89#ibcon#about to read 6, iclass 30, count 0 2006.252.07:48:09.89#ibcon#read 6, iclass 30, count 0 2006.252.07:48:09.89#ibcon#end of sib2, iclass 30, count 0 2006.252.07:48:09.89#ibcon#*mode == 0, iclass 30, count 0 2006.252.07:48:09.89#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.252.07:48:09.89#ibcon#[25=USB\r\n] 2006.252.07:48:09.89#ibcon#*before write, iclass 30, count 0 2006.252.07:48:09.89#ibcon#enter sib2, iclass 30, count 0 2006.252.07:48:09.89#ibcon#flushed, iclass 30, count 0 2006.252.07:48:09.89#ibcon#about to write, iclass 30, count 0 2006.252.07:48:09.89#ibcon#wrote, iclass 30, count 0 2006.252.07:48:09.89#ibcon#about to read 3, iclass 30, count 0 2006.252.07:48:09.92#ibcon#read 3, iclass 30, count 0 2006.252.07:48:09.92#ibcon#about to read 4, iclass 30, count 0 2006.252.07:48:09.92#ibcon#read 4, iclass 30, count 0 2006.252.07:48:09.92#ibcon#about to read 5, iclass 30, count 0 2006.252.07:48:09.92#ibcon#read 5, iclass 30, count 0 2006.252.07:48:09.92#ibcon#about to read 6, iclass 30, count 0 2006.252.07:48:09.92#ibcon#read 6, iclass 30, count 0 2006.252.07:48:09.92#ibcon#end of sib2, iclass 30, count 0 2006.252.07:48:09.92#ibcon#*after write, iclass 30, count 0 2006.252.07:48:09.92#ibcon#*before return 0, iclass 30, count 0 2006.252.07:48:09.92#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.252.07:48:09.92#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.252.07:48:09.92#ibcon#about to clear, iclass 30 cls_cnt 0 2006.252.07:48:09.92#ibcon#cleared, iclass 30 cls_cnt 0 2006.252.07:48:09.92$vc4f8/valo=7,832.99 2006.252.07:48:09.92#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.252.07:48:09.92#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.252.07:48:09.92#ibcon#ireg 17 cls_cnt 0 2006.252.07:48:09.92#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.252.07:48:09.92#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.252.07:48:09.92#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.252.07:48:09.92#ibcon#enter wrdev, iclass 32, count 0 2006.252.07:48:09.92#ibcon#first serial, iclass 32, count 0 2006.252.07:48:09.92#ibcon#enter sib2, iclass 32, count 0 2006.252.07:48:09.92#ibcon#flushed, iclass 32, count 0 2006.252.07:48:09.92#ibcon#about to write, iclass 32, count 0 2006.252.07:48:09.92#ibcon#wrote, iclass 32, count 0 2006.252.07:48:09.92#ibcon#about to read 3, iclass 32, count 0 2006.252.07:48:09.94#ibcon#read 3, iclass 32, count 0 2006.252.07:48:09.94#ibcon#about to read 4, iclass 32, count 0 2006.252.07:48:09.94#ibcon#read 4, iclass 32, count 0 2006.252.07:48:09.94#ibcon#about to read 5, iclass 32, count 0 2006.252.07:48:09.94#ibcon#read 5, iclass 32, count 0 2006.252.07:48:09.94#ibcon#about to read 6, iclass 32, count 0 2006.252.07:48:09.94#ibcon#read 6, iclass 32, count 0 2006.252.07:48:09.94#ibcon#end of sib2, iclass 32, count 0 2006.252.07:48:09.94#ibcon#*mode == 0, iclass 32, count 0 2006.252.07:48:09.94#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.252.07:48:09.94#ibcon#[26=FRQ=07,832.99\r\n] 2006.252.07:48:09.94#ibcon#*before write, iclass 32, count 0 2006.252.07:48:09.94#ibcon#enter sib2, iclass 32, count 0 2006.252.07:48:09.94#ibcon#flushed, iclass 32, count 0 2006.252.07:48:09.94#ibcon#about to write, iclass 32, count 0 2006.252.07:48:09.94#ibcon#wrote, iclass 32, count 0 2006.252.07:48:09.94#ibcon#about to read 3, iclass 32, count 0 2006.252.07:48:09.98#ibcon#read 3, iclass 32, count 0 2006.252.07:48:09.98#ibcon#about to read 4, iclass 32, count 0 2006.252.07:48:09.98#ibcon#read 4, iclass 32, count 0 2006.252.07:48:09.98#ibcon#about to read 5, iclass 32, count 0 2006.252.07:48:09.98#ibcon#read 5, iclass 32, count 0 2006.252.07:48:09.98#ibcon#about to read 6, iclass 32, count 0 2006.252.07:48:09.98#ibcon#read 6, iclass 32, count 0 2006.252.07:48:09.98#ibcon#end of sib2, iclass 32, count 0 2006.252.07:48:09.98#ibcon#*after write, iclass 32, count 0 2006.252.07:48:09.98#ibcon#*before return 0, iclass 32, count 0 2006.252.07:48:09.98#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.252.07:48:09.98#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.252.07:48:09.98#ibcon#about to clear, iclass 32 cls_cnt 0 2006.252.07:48:09.98#ibcon#cleared, iclass 32 cls_cnt 0 2006.252.07:48:09.98$vc4f8/va=7,7 2006.252.07:48:09.98#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.252.07:48:09.98#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.252.07:48:09.98#ibcon#ireg 11 cls_cnt 2 2006.252.07:48:09.98#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.252.07:48:10.04#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.252.07:48:10.04#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.252.07:48:10.04#ibcon#enter wrdev, iclass 34, count 2 2006.252.07:48:10.04#ibcon#first serial, iclass 34, count 2 2006.252.07:48:10.04#ibcon#enter sib2, iclass 34, count 2 2006.252.07:48:10.04#ibcon#flushed, iclass 34, count 2 2006.252.07:48:10.04#ibcon#about to write, iclass 34, count 2 2006.252.07:48:10.04#ibcon#wrote, iclass 34, count 2 2006.252.07:48:10.04#ibcon#about to read 3, iclass 34, count 2 2006.252.07:48:10.06#ibcon#read 3, iclass 34, count 2 2006.252.07:48:10.06#ibcon#about to read 4, iclass 34, count 2 2006.252.07:48:10.06#ibcon#read 4, iclass 34, count 2 2006.252.07:48:10.06#ibcon#about to read 5, iclass 34, count 2 2006.252.07:48:10.06#ibcon#read 5, iclass 34, count 2 2006.252.07:48:10.06#ibcon#about to read 6, iclass 34, count 2 2006.252.07:48:10.06#ibcon#read 6, iclass 34, count 2 2006.252.07:48:10.06#ibcon#end of sib2, iclass 34, count 2 2006.252.07:48:10.06#ibcon#*mode == 0, iclass 34, count 2 2006.252.07:48:10.06#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.252.07:48:10.06#ibcon#[25=AT07-07\r\n] 2006.252.07:48:10.06#ibcon#*before write, iclass 34, count 2 2006.252.07:48:10.06#ibcon#enter sib2, iclass 34, count 2 2006.252.07:48:10.06#ibcon#flushed, iclass 34, count 2 2006.252.07:48:10.06#ibcon#about to write, iclass 34, count 2 2006.252.07:48:10.06#ibcon#wrote, iclass 34, count 2 2006.252.07:48:10.06#ibcon#about to read 3, iclass 34, count 2 2006.252.07:48:10.09#ibcon#read 3, iclass 34, count 2 2006.252.07:48:10.09#ibcon#about to read 4, iclass 34, count 2 2006.252.07:48:10.09#ibcon#read 4, iclass 34, count 2 2006.252.07:48:10.09#ibcon#about to read 5, iclass 34, count 2 2006.252.07:48:10.09#ibcon#read 5, iclass 34, count 2 2006.252.07:48:10.09#ibcon#about to read 6, iclass 34, count 2 2006.252.07:48:10.09#ibcon#read 6, iclass 34, count 2 2006.252.07:48:10.09#ibcon#end of sib2, iclass 34, count 2 2006.252.07:48:10.09#ibcon#*after write, iclass 34, count 2 2006.252.07:48:10.09#ibcon#*before return 0, iclass 34, count 2 2006.252.07:48:10.09#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.252.07:48:10.09#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.252.07:48:10.09#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.252.07:48:10.09#ibcon#ireg 7 cls_cnt 0 2006.252.07:48:10.09#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.252.07:48:10.21#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.252.07:48:10.21#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.252.07:48:10.21#ibcon#enter wrdev, iclass 34, count 0 2006.252.07:48:10.21#ibcon#first serial, iclass 34, count 0 2006.252.07:48:10.21#ibcon#enter sib2, iclass 34, count 0 2006.252.07:48:10.21#ibcon#flushed, iclass 34, count 0 2006.252.07:48:10.21#ibcon#about to write, iclass 34, count 0 2006.252.07:48:10.21#ibcon#wrote, iclass 34, count 0 2006.252.07:48:10.21#ibcon#about to read 3, iclass 34, count 0 2006.252.07:48:10.23#ibcon#read 3, iclass 34, count 0 2006.252.07:48:10.23#ibcon#about to read 4, iclass 34, count 0 2006.252.07:48:10.23#ibcon#read 4, iclass 34, count 0 2006.252.07:48:10.23#ibcon#about to read 5, iclass 34, count 0 2006.252.07:48:10.23#ibcon#read 5, iclass 34, count 0 2006.252.07:48:10.23#ibcon#about to read 6, iclass 34, count 0 2006.252.07:48:10.23#ibcon#read 6, iclass 34, count 0 2006.252.07:48:10.23#ibcon#end of sib2, iclass 34, count 0 2006.252.07:48:10.23#ibcon#*mode == 0, iclass 34, count 0 2006.252.07:48:10.23#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.252.07:48:10.23#ibcon#[25=USB\r\n] 2006.252.07:48:10.23#ibcon#*before write, iclass 34, count 0 2006.252.07:48:10.23#ibcon#enter sib2, iclass 34, count 0 2006.252.07:48:10.23#ibcon#flushed, iclass 34, count 0 2006.252.07:48:10.23#ibcon#about to write, iclass 34, count 0 2006.252.07:48:10.23#ibcon#wrote, iclass 34, count 0 2006.252.07:48:10.23#ibcon#about to read 3, iclass 34, count 0 2006.252.07:48:10.26#ibcon#read 3, iclass 34, count 0 2006.252.07:48:10.26#ibcon#about to read 4, iclass 34, count 0 2006.252.07:48:10.26#ibcon#read 4, iclass 34, count 0 2006.252.07:48:10.26#ibcon#about to read 5, iclass 34, count 0 2006.252.07:48:10.26#ibcon#read 5, iclass 34, count 0 2006.252.07:48:10.26#ibcon#about to read 6, iclass 34, count 0 2006.252.07:48:10.26#ibcon#read 6, iclass 34, count 0 2006.252.07:48:10.26#ibcon#end of sib2, iclass 34, count 0 2006.252.07:48:10.26#ibcon#*after write, iclass 34, count 0 2006.252.07:48:10.26#ibcon#*before return 0, iclass 34, count 0 2006.252.07:48:10.26#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.252.07:48:10.26#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.252.07:48:10.26#ibcon#about to clear, iclass 34 cls_cnt 0 2006.252.07:48:10.26#ibcon#cleared, iclass 34 cls_cnt 0 2006.252.07:48:10.26$vc4f8/valo=8,852.99 2006.252.07:48:10.26#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.252.07:48:10.26#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.252.07:48:10.26#ibcon#ireg 17 cls_cnt 0 2006.252.07:48:10.26#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.252.07:48:10.26#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.252.07:48:10.26#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.252.07:48:10.26#ibcon#enter wrdev, iclass 36, count 0 2006.252.07:48:10.26#ibcon#first serial, iclass 36, count 0 2006.252.07:48:10.26#ibcon#enter sib2, iclass 36, count 0 2006.252.07:48:10.26#ibcon#flushed, iclass 36, count 0 2006.252.07:48:10.26#ibcon#about to write, iclass 36, count 0 2006.252.07:48:10.26#ibcon#wrote, iclass 36, count 0 2006.252.07:48:10.26#ibcon#about to read 3, iclass 36, count 0 2006.252.07:48:10.28#ibcon#read 3, iclass 36, count 0 2006.252.07:48:10.28#ibcon#about to read 4, iclass 36, count 0 2006.252.07:48:10.28#ibcon#read 4, iclass 36, count 0 2006.252.07:48:10.28#ibcon#about to read 5, iclass 36, count 0 2006.252.07:48:10.28#ibcon#read 5, iclass 36, count 0 2006.252.07:48:10.28#ibcon#about to read 6, iclass 36, count 0 2006.252.07:48:10.28#ibcon#read 6, iclass 36, count 0 2006.252.07:48:10.28#ibcon#end of sib2, iclass 36, count 0 2006.252.07:48:10.28#ibcon#*mode == 0, iclass 36, count 0 2006.252.07:48:10.28#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.252.07:48:10.28#ibcon#[26=FRQ=08,852.99\r\n] 2006.252.07:48:10.28#ibcon#*before write, iclass 36, count 0 2006.252.07:48:10.28#ibcon#enter sib2, iclass 36, count 0 2006.252.07:48:10.28#ibcon#flushed, iclass 36, count 0 2006.252.07:48:10.28#ibcon#about to write, iclass 36, count 0 2006.252.07:48:10.28#ibcon#wrote, iclass 36, count 0 2006.252.07:48:10.28#ibcon#about to read 3, iclass 36, count 0 2006.252.07:48:10.32#ibcon#read 3, iclass 36, count 0 2006.252.07:48:10.32#ibcon#about to read 4, iclass 36, count 0 2006.252.07:48:10.32#ibcon#read 4, iclass 36, count 0 2006.252.07:48:10.32#ibcon#about to read 5, iclass 36, count 0 2006.252.07:48:10.32#ibcon#read 5, iclass 36, count 0 2006.252.07:48:10.32#ibcon#about to read 6, iclass 36, count 0 2006.252.07:48:10.32#ibcon#read 6, iclass 36, count 0 2006.252.07:48:10.32#ibcon#end of sib2, iclass 36, count 0 2006.252.07:48:10.32#ibcon#*after write, iclass 36, count 0 2006.252.07:48:10.32#ibcon#*before return 0, iclass 36, count 0 2006.252.07:48:10.32#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.252.07:48:10.32#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.252.07:48:10.32#ibcon#about to clear, iclass 36 cls_cnt 0 2006.252.07:48:10.32#ibcon#cleared, iclass 36 cls_cnt 0 2006.252.07:48:10.32$vc4f8/va=8,7 2006.252.07:48:10.32#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.252.07:48:10.32#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.252.07:48:10.32#ibcon#ireg 11 cls_cnt 2 2006.252.07:48:10.32#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.252.07:48:10.38#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.252.07:48:10.38#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.252.07:48:10.38#ibcon#enter wrdev, iclass 38, count 2 2006.252.07:48:10.38#ibcon#first serial, iclass 38, count 2 2006.252.07:48:10.38#ibcon#enter sib2, iclass 38, count 2 2006.252.07:48:10.38#ibcon#flushed, iclass 38, count 2 2006.252.07:48:10.38#ibcon#about to write, iclass 38, count 2 2006.252.07:48:10.38#ibcon#wrote, iclass 38, count 2 2006.252.07:48:10.38#ibcon#about to read 3, iclass 38, count 2 2006.252.07:48:10.40#ibcon#read 3, iclass 38, count 2 2006.252.07:48:10.40#ibcon#about to read 4, iclass 38, count 2 2006.252.07:48:10.40#ibcon#read 4, iclass 38, count 2 2006.252.07:48:10.40#ibcon#about to read 5, iclass 38, count 2 2006.252.07:48:10.40#ibcon#read 5, iclass 38, count 2 2006.252.07:48:10.40#ibcon#about to read 6, iclass 38, count 2 2006.252.07:48:10.40#ibcon#read 6, iclass 38, count 2 2006.252.07:48:10.40#ibcon#end of sib2, iclass 38, count 2 2006.252.07:48:10.40#ibcon#*mode == 0, iclass 38, count 2 2006.252.07:48:10.40#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.252.07:48:10.40#ibcon#[25=AT08-07\r\n] 2006.252.07:48:10.40#ibcon#*before write, iclass 38, count 2 2006.252.07:48:10.40#ibcon#enter sib2, iclass 38, count 2 2006.252.07:48:10.40#ibcon#flushed, iclass 38, count 2 2006.252.07:48:10.40#ibcon#about to write, iclass 38, count 2 2006.252.07:48:10.40#ibcon#wrote, iclass 38, count 2 2006.252.07:48:10.40#ibcon#about to read 3, iclass 38, count 2 2006.252.07:48:10.43#ibcon#read 3, iclass 38, count 2 2006.252.07:48:10.43#ibcon#about to read 4, iclass 38, count 2 2006.252.07:48:10.43#ibcon#read 4, iclass 38, count 2 2006.252.07:48:10.43#ibcon#about to read 5, iclass 38, count 2 2006.252.07:48:10.43#ibcon#read 5, iclass 38, count 2 2006.252.07:48:10.43#ibcon#about to read 6, iclass 38, count 2 2006.252.07:48:10.43#ibcon#read 6, iclass 38, count 2 2006.252.07:48:10.43#ibcon#end of sib2, iclass 38, count 2 2006.252.07:48:10.43#ibcon#*after write, iclass 38, count 2 2006.252.07:48:10.43#ibcon#*before return 0, iclass 38, count 2 2006.252.07:48:10.43#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.252.07:48:10.43#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.252.07:48:10.43#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.252.07:48:10.43#ibcon#ireg 7 cls_cnt 0 2006.252.07:48:10.43#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.252.07:48:10.55#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.252.07:48:10.55#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.252.07:48:10.55#ibcon#enter wrdev, iclass 38, count 0 2006.252.07:48:10.55#ibcon#first serial, iclass 38, count 0 2006.252.07:48:10.55#ibcon#enter sib2, iclass 38, count 0 2006.252.07:48:10.55#ibcon#flushed, iclass 38, count 0 2006.252.07:48:10.55#ibcon#about to write, iclass 38, count 0 2006.252.07:48:10.55#ibcon#wrote, iclass 38, count 0 2006.252.07:48:10.55#ibcon#about to read 3, iclass 38, count 0 2006.252.07:48:10.57#ibcon#read 3, iclass 38, count 0 2006.252.07:48:10.57#ibcon#about to read 4, iclass 38, count 0 2006.252.07:48:10.57#ibcon#read 4, iclass 38, count 0 2006.252.07:48:10.57#ibcon#about to read 5, iclass 38, count 0 2006.252.07:48:10.57#ibcon#read 5, iclass 38, count 0 2006.252.07:48:10.57#ibcon#about to read 6, iclass 38, count 0 2006.252.07:48:10.57#ibcon#read 6, iclass 38, count 0 2006.252.07:48:10.57#ibcon#end of sib2, iclass 38, count 0 2006.252.07:48:10.57#ibcon#*mode == 0, iclass 38, count 0 2006.252.07:48:10.57#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.252.07:48:10.57#ibcon#[25=USB\r\n] 2006.252.07:48:10.57#ibcon#*before write, iclass 38, count 0 2006.252.07:48:10.57#ibcon#enter sib2, iclass 38, count 0 2006.252.07:48:10.57#ibcon#flushed, iclass 38, count 0 2006.252.07:48:10.57#ibcon#about to write, iclass 38, count 0 2006.252.07:48:10.57#ibcon#wrote, iclass 38, count 0 2006.252.07:48:10.57#ibcon#about to read 3, iclass 38, count 0 2006.252.07:48:10.60#ibcon#read 3, iclass 38, count 0 2006.252.07:48:10.60#ibcon#about to read 4, iclass 38, count 0 2006.252.07:48:10.60#ibcon#read 4, iclass 38, count 0 2006.252.07:48:10.60#ibcon#about to read 5, iclass 38, count 0 2006.252.07:48:10.60#ibcon#read 5, iclass 38, count 0 2006.252.07:48:10.60#ibcon#about to read 6, iclass 38, count 0 2006.252.07:48:10.60#ibcon#read 6, iclass 38, count 0 2006.252.07:48:10.60#ibcon#end of sib2, iclass 38, count 0 2006.252.07:48:10.60#ibcon#*after write, iclass 38, count 0 2006.252.07:48:10.60#ibcon#*before return 0, iclass 38, count 0 2006.252.07:48:10.60#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.252.07:48:10.60#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.252.07:48:10.60#ibcon#about to clear, iclass 38 cls_cnt 0 2006.252.07:48:10.60#ibcon#cleared, iclass 38 cls_cnt 0 2006.252.07:48:10.60$vc4f8/vblo=1,632.99 2006.252.07:48:10.60#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.252.07:48:10.60#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.252.07:48:10.60#ibcon#ireg 17 cls_cnt 0 2006.252.07:48:10.60#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.252.07:48:10.60#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.252.07:48:10.60#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.252.07:48:10.60#ibcon#enter wrdev, iclass 40, count 0 2006.252.07:48:10.60#ibcon#first serial, iclass 40, count 0 2006.252.07:48:10.60#ibcon#enter sib2, iclass 40, count 0 2006.252.07:48:10.60#ibcon#flushed, iclass 40, count 0 2006.252.07:48:10.60#ibcon#about to write, iclass 40, count 0 2006.252.07:48:10.60#ibcon#wrote, iclass 40, count 0 2006.252.07:48:10.60#ibcon#about to read 3, iclass 40, count 0 2006.252.07:48:10.62#ibcon#read 3, iclass 40, count 0 2006.252.07:48:10.62#ibcon#about to read 4, iclass 40, count 0 2006.252.07:48:10.62#ibcon#read 4, iclass 40, count 0 2006.252.07:48:10.62#ibcon#about to read 5, iclass 40, count 0 2006.252.07:48:10.62#ibcon#read 5, iclass 40, count 0 2006.252.07:48:10.62#ibcon#about to read 6, iclass 40, count 0 2006.252.07:48:10.62#ibcon#read 6, iclass 40, count 0 2006.252.07:48:10.62#ibcon#end of sib2, iclass 40, count 0 2006.252.07:48:10.62#ibcon#*mode == 0, iclass 40, count 0 2006.252.07:48:10.62#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.252.07:48:10.62#ibcon#[28=FRQ=01,632.99\r\n] 2006.252.07:48:10.62#ibcon#*before write, iclass 40, count 0 2006.252.07:48:10.62#ibcon#enter sib2, iclass 40, count 0 2006.252.07:48:10.62#ibcon#flushed, iclass 40, count 0 2006.252.07:48:10.62#ibcon#about to write, iclass 40, count 0 2006.252.07:48:10.62#ibcon#wrote, iclass 40, count 0 2006.252.07:48:10.62#ibcon#about to read 3, iclass 40, count 0 2006.252.07:48:10.66#ibcon#read 3, iclass 40, count 0 2006.252.07:48:10.66#ibcon#about to read 4, iclass 40, count 0 2006.252.07:48:10.66#ibcon#read 4, iclass 40, count 0 2006.252.07:48:10.66#ibcon#about to read 5, iclass 40, count 0 2006.252.07:48:10.66#ibcon#read 5, iclass 40, count 0 2006.252.07:48:10.66#ibcon#about to read 6, iclass 40, count 0 2006.252.07:48:10.66#ibcon#read 6, iclass 40, count 0 2006.252.07:48:10.66#ibcon#end of sib2, iclass 40, count 0 2006.252.07:48:10.66#ibcon#*after write, iclass 40, count 0 2006.252.07:48:10.66#ibcon#*before return 0, iclass 40, count 0 2006.252.07:48:10.66#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.252.07:48:10.66#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.252.07:48:10.66#ibcon#about to clear, iclass 40 cls_cnt 0 2006.252.07:48:10.66#ibcon#cleared, iclass 40 cls_cnt 0 2006.252.07:48:10.66$vc4f8/vb=1,4 2006.252.07:48:10.66#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.252.07:48:10.66#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.252.07:48:10.66#ibcon#ireg 11 cls_cnt 2 2006.252.07:48:10.66#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.252.07:48:10.66#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.252.07:48:10.66#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.252.07:48:10.66#ibcon#enter wrdev, iclass 4, count 2 2006.252.07:48:10.66#ibcon#first serial, iclass 4, count 2 2006.252.07:48:10.66#ibcon#enter sib2, iclass 4, count 2 2006.252.07:48:10.66#ibcon#flushed, iclass 4, count 2 2006.252.07:48:10.66#ibcon#about to write, iclass 4, count 2 2006.252.07:48:10.66#ibcon#wrote, iclass 4, count 2 2006.252.07:48:10.66#ibcon#about to read 3, iclass 4, count 2 2006.252.07:48:10.68#ibcon#read 3, iclass 4, count 2 2006.252.07:48:10.68#ibcon#about to read 4, iclass 4, count 2 2006.252.07:48:10.68#ibcon#read 4, iclass 4, count 2 2006.252.07:48:10.68#ibcon#about to read 5, iclass 4, count 2 2006.252.07:48:10.68#ibcon#read 5, iclass 4, count 2 2006.252.07:48:10.68#ibcon#about to read 6, iclass 4, count 2 2006.252.07:48:10.68#ibcon#read 6, iclass 4, count 2 2006.252.07:48:10.68#ibcon#end of sib2, iclass 4, count 2 2006.252.07:48:10.68#ibcon#*mode == 0, iclass 4, count 2 2006.252.07:48:10.68#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.252.07:48:10.68#ibcon#[27=AT01-04\r\n] 2006.252.07:48:10.68#ibcon#*before write, iclass 4, count 2 2006.252.07:48:10.68#ibcon#enter sib2, iclass 4, count 2 2006.252.07:48:10.68#ibcon#flushed, iclass 4, count 2 2006.252.07:48:10.68#ibcon#about to write, iclass 4, count 2 2006.252.07:48:10.68#ibcon#wrote, iclass 4, count 2 2006.252.07:48:10.68#ibcon#about to read 3, iclass 4, count 2 2006.252.07:48:10.71#ibcon#read 3, iclass 4, count 2 2006.252.07:48:10.71#ibcon#about to read 4, iclass 4, count 2 2006.252.07:48:10.71#ibcon#read 4, iclass 4, count 2 2006.252.07:48:10.71#ibcon#about to read 5, iclass 4, count 2 2006.252.07:48:10.71#ibcon#read 5, iclass 4, count 2 2006.252.07:48:10.71#ibcon#about to read 6, iclass 4, count 2 2006.252.07:48:10.71#ibcon#read 6, iclass 4, count 2 2006.252.07:48:10.71#ibcon#end of sib2, iclass 4, count 2 2006.252.07:48:10.71#ibcon#*after write, iclass 4, count 2 2006.252.07:48:10.71#ibcon#*before return 0, iclass 4, count 2 2006.252.07:48:10.71#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.252.07:48:10.71#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.252.07:48:10.71#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.252.07:48:10.71#ibcon#ireg 7 cls_cnt 0 2006.252.07:48:10.71#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.252.07:48:10.83#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.252.07:48:10.83#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.252.07:48:10.83#ibcon#enter wrdev, iclass 4, count 0 2006.252.07:48:10.83#ibcon#first serial, iclass 4, count 0 2006.252.07:48:10.83#ibcon#enter sib2, iclass 4, count 0 2006.252.07:48:10.83#ibcon#flushed, iclass 4, count 0 2006.252.07:48:10.83#ibcon#about to write, iclass 4, count 0 2006.252.07:48:10.83#ibcon#wrote, iclass 4, count 0 2006.252.07:48:10.83#ibcon#about to read 3, iclass 4, count 0 2006.252.07:48:10.85#ibcon#read 3, iclass 4, count 0 2006.252.07:48:10.85#ibcon#about to read 4, iclass 4, count 0 2006.252.07:48:10.85#ibcon#read 4, iclass 4, count 0 2006.252.07:48:10.85#ibcon#about to read 5, iclass 4, count 0 2006.252.07:48:10.85#ibcon#read 5, iclass 4, count 0 2006.252.07:48:10.85#ibcon#about to read 6, iclass 4, count 0 2006.252.07:48:10.85#ibcon#read 6, iclass 4, count 0 2006.252.07:48:10.85#ibcon#end of sib2, iclass 4, count 0 2006.252.07:48:10.85#ibcon#*mode == 0, iclass 4, count 0 2006.252.07:48:10.85#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.252.07:48:10.85#ibcon#[27=USB\r\n] 2006.252.07:48:10.85#ibcon#*before write, iclass 4, count 0 2006.252.07:48:10.85#ibcon#enter sib2, iclass 4, count 0 2006.252.07:48:10.85#ibcon#flushed, iclass 4, count 0 2006.252.07:48:10.85#ibcon#about to write, iclass 4, count 0 2006.252.07:48:10.85#ibcon#wrote, iclass 4, count 0 2006.252.07:48:10.85#ibcon#about to read 3, iclass 4, count 0 2006.252.07:48:10.88#ibcon#read 3, iclass 4, count 0 2006.252.07:48:10.88#ibcon#about to read 4, iclass 4, count 0 2006.252.07:48:10.88#ibcon#read 4, iclass 4, count 0 2006.252.07:48:10.88#ibcon#about to read 5, iclass 4, count 0 2006.252.07:48:10.88#ibcon#read 5, iclass 4, count 0 2006.252.07:48:10.88#ibcon#about to read 6, iclass 4, count 0 2006.252.07:48:10.88#ibcon#read 6, iclass 4, count 0 2006.252.07:48:10.88#ibcon#end of sib2, iclass 4, count 0 2006.252.07:48:10.88#ibcon#*after write, iclass 4, count 0 2006.252.07:48:10.88#ibcon#*before return 0, iclass 4, count 0 2006.252.07:48:10.88#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.252.07:48:10.88#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.252.07:48:10.88#ibcon#about to clear, iclass 4 cls_cnt 0 2006.252.07:48:10.88#ibcon#cleared, iclass 4 cls_cnt 0 2006.252.07:48:10.88$vc4f8/vblo=2,640.99 2006.252.07:48:10.88#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.252.07:48:10.88#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.252.07:48:10.88#ibcon#ireg 17 cls_cnt 0 2006.252.07:48:10.88#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.252.07:48:10.88#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.252.07:48:10.88#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.252.07:48:10.88#ibcon#enter wrdev, iclass 6, count 0 2006.252.07:48:10.88#ibcon#first serial, iclass 6, count 0 2006.252.07:48:10.88#ibcon#enter sib2, iclass 6, count 0 2006.252.07:48:10.88#ibcon#flushed, iclass 6, count 0 2006.252.07:48:10.88#ibcon#about to write, iclass 6, count 0 2006.252.07:48:10.88#ibcon#wrote, iclass 6, count 0 2006.252.07:48:10.88#ibcon#about to read 3, iclass 6, count 0 2006.252.07:48:10.90#ibcon#read 3, iclass 6, count 0 2006.252.07:48:10.90#ibcon#about to read 4, iclass 6, count 0 2006.252.07:48:10.90#ibcon#read 4, iclass 6, count 0 2006.252.07:48:10.90#ibcon#about to read 5, iclass 6, count 0 2006.252.07:48:10.90#ibcon#read 5, iclass 6, count 0 2006.252.07:48:10.90#ibcon#about to read 6, iclass 6, count 0 2006.252.07:48:10.90#ibcon#read 6, iclass 6, count 0 2006.252.07:48:10.90#ibcon#end of sib2, iclass 6, count 0 2006.252.07:48:10.90#ibcon#*mode == 0, iclass 6, count 0 2006.252.07:48:10.90#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.252.07:48:10.90#ibcon#[28=FRQ=02,640.99\r\n] 2006.252.07:48:10.90#ibcon#*before write, iclass 6, count 0 2006.252.07:48:10.90#ibcon#enter sib2, iclass 6, count 0 2006.252.07:48:10.90#ibcon#flushed, iclass 6, count 0 2006.252.07:48:10.90#ibcon#about to write, iclass 6, count 0 2006.252.07:48:10.90#ibcon#wrote, iclass 6, count 0 2006.252.07:48:10.90#ibcon#about to read 3, iclass 6, count 0 2006.252.07:48:10.94#ibcon#read 3, iclass 6, count 0 2006.252.07:48:10.94#ibcon#about to read 4, iclass 6, count 0 2006.252.07:48:10.94#ibcon#read 4, iclass 6, count 0 2006.252.07:48:10.94#ibcon#about to read 5, iclass 6, count 0 2006.252.07:48:10.94#ibcon#read 5, iclass 6, count 0 2006.252.07:48:10.94#ibcon#about to read 6, iclass 6, count 0 2006.252.07:48:10.94#ibcon#read 6, iclass 6, count 0 2006.252.07:48:10.94#ibcon#end of sib2, iclass 6, count 0 2006.252.07:48:10.94#ibcon#*after write, iclass 6, count 0 2006.252.07:48:10.94#ibcon#*before return 0, iclass 6, count 0 2006.252.07:48:10.94#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.252.07:48:10.94#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.252.07:48:10.94#ibcon#about to clear, iclass 6 cls_cnt 0 2006.252.07:48:10.94#ibcon#cleared, iclass 6 cls_cnt 0 2006.252.07:48:10.94$vc4f8/vb=2,5 2006.252.07:48:10.94#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.252.07:48:10.94#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.252.07:48:10.94#ibcon#ireg 11 cls_cnt 2 2006.252.07:48:10.94#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.252.07:48:11.00#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.252.07:48:11.00#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.252.07:48:11.00#ibcon#enter wrdev, iclass 10, count 2 2006.252.07:48:11.00#ibcon#first serial, iclass 10, count 2 2006.252.07:48:11.00#ibcon#enter sib2, iclass 10, count 2 2006.252.07:48:11.00#ibcon#flushed, iclass 10, count 2 2006.252.07:48:11.00#ibcon#about to write, iclass 10, count 2 2006.252.07:48:11.00#ibcon#wrote, iclass 10, count 2 2006.252.07:48:11.00#ibcon#about to read 3, iclass 10, count 2 2006.252.07:48:11.02#ibcon#read 3, iclass 10, count 2 2006.252.07:48:11.02#ibcon#about to read 4, iclass 10, count 2 2006.252.07:48:11.02#ibcon#read 4, iclass 10, count 2 2006.252.07:48:11.02#ibcon#about to read 5, iclass 10, count 2 2006.252.07:48:11.02#ibcon#read 5, iclass 10, count 2 2006.252.07:48:11.02#ibcon#about to read 6, iclass 10, count 2 2006.252.07:48:11.02#ibcon#read 6, iclass 10, count 2 2006.252.07:48:11.02#ibcon#end of sib2, iclass 10, count 2 2006.252.07:48:11.02#ibcon#*mode == 0, iclass 10, count 2 2006.252.07:48:11.02#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.252.07:48:11.02#ibcon#[27=AT02-05\r\n] 2006.252.07:48:11.02#ibcon#*before write, iclass 10, count 2 2006.252.07:48:11.02#ibcon#enter sib2, iclass 10, count 2 2006.252.07:48:11.02#ibcon#flushed, iclass 10, count 2 2006.252.07:48:11.02#ibcon#about to write, iclass 10, count 2 2006.252.07:48:11.02#ibcon#wrote, iclass 10, count 2 2006.252.07:48:11.02#ibcon#about to read 3, iclass 10, count 2 2006.252.07:48:11.05#ibcon#read 3, iclass 10, count 2 2006.252.07:48:11.05#ibcon#about to read 4, iclass 10, count 2 2006.252.07:48:11.05#ibcon#read 4, iclass 10, count 2 2006.252.07:48:11.05#ibcon#about to read 5, iclass 10, count 2 2006.252.07:48:11.05#ibcon#read 5, iclass 10, count 2 2006.252.07:48:11.05#ibcon#about to read 6, iclass 10, count 2 2006.252.07:48:11.05#ibcon#read 6, iclass 10, count 2 2006.252.07:48:11.05#ibcon#end of sib2, iclass 10, count 2 2006.252.07:48:11.05#ibcon#*after write, iclass 10, count 2 2006.252.07:48:11.05#ibcon#*before return 0, iclass 10, count 2 2006.252.07:48:11.05#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.252.07:48:11.05#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.252.07:48:11.05#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.252.07:48:11.05#ibcon#ireg 7 cls_cnt 0 2006.252.07:48:11.05#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.252.07:48:11.17#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.252.07:48:11.17#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.252.07:48:11.17#ibcon#enter wrdev, iclass 10, count 0 2006.252.07:48:11.17#ibcon#first serial, iclass 10, count 0 2006.252.07:48:11.17#ibcon#enter sib2, iclass 10, count 0 2006.252.07:48:11.17#ibcon#flushed, iclass 10, count 0 2006.252.07:48:11.17#ibcon#about to write, iclass 10, count 0 2006.252.07:48:11.17#ibcon#wrote, iclass 10, count 0 2006.252.07:48:11.17#ibcon#about to read 3, iclass 10, count 0 2006.252.07:48:11.21#ibcon#read 3, iclass 10, count 0 2006.252.07:48:11.21#ibcon#about to read 4, iclass 10, count 0 2006.252.07:48:11.21#ibcon#read 4, iclass 10, count 0 2006.252.07:48:11.21#ibcon#about to read 5, iclass 10, count 0 2006.252.07:48:11.21#ibcon#read 5, iclass 10, count 0 2006.252.07:48:11.21#ibcon#about to read 6, iclass 10, count 0 2006.252.07:48:11.21#ibcon#read 6, iclass 10, count 0 2006.252.07:48:11.21#ibcon#end of sib2, iclass 10, count 0 2006.252.07:48:11.21#ibcon#*mode == 0, iclass 10, count 0 2006.252.07:48:11.21#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.252.07:48:11.21#ibcon#[27=USB\r\n] 2006.252.07:48:11.21#ibcon#*before write, iclass 10, count 0 2006.252.07:48:11.21#ibcon#enter sib2, iclass 10, count 0 2006.252.07:48:11.21#ibcon#flushed, iclass 10, count 0 2006.252.07:48:11.21#ibcon#about to write, iclass 10, count 0 2006.252.07:48:11.21#ibcon#wrote, iclass 10, count 0 2006.252.07:48:11.21#ibcon#about to read 3, iclass 10, count 0 2006.252.07:48:11.23#ibcon#read 3, iclass 10, count 0 2006.252.07:48:11.23#ibcon#about to read 4, iclass 10, count 0 2006.252.07:48:11.23#ibcon#read 4, iclass 10, count 0 2006.252.07:48:11.23#ibcon#about to read 5, iclass 10, count 0 2006.252.07:48:11.23#ibcon#read 5, iclass 10, count 0 2006.252.07:48:11.23#ibcon#about to read 6, iclass 10, count 0 2006.252.07:48:11.23#ibcon#read 6, iclass 10, count 0 2006.252.07:48:11.23#ibcon#end of sib2, iclass 10, count 0 2006.252.07:48:11.23#ibcon#*after write, iclass 10, count 0 2006.252.07:48:11.23#ibcon#*before return 0, iclass 10, count 0 2006.252.07:48:11.23#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.252.07:48:11.23#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.252.07:48:11.23#ibcon#about to clear, iclass 10 cls_cnt 0 2006.252.07:48:11.23#ibcon#cleared, iclass 10 cls_cnt 0 2006.252.07:48:11.23$vc4f8/vblo=3,656.99 2006.252.07:48:11.23#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.252.07:48:11.23#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.252.07:48:11.23#ibcon#ireg 17 cls_cnt 0 2006.252.07:48:11.23#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.252.07:48:11.23#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.252.07:48:11.23#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.252.07:48:11.23#ibcon#enter wrdev, iclass 12, count 0 2006.252.07:48:11.23#ibcon#first serial, iclass 12, count 0 2006.252.07:48:11.23#ibcon#enter sib2, iclass 12, count 0 2006.252.07:48:11.23#ibcon#flushed, iclass 12, count 0 2006.252.07:48:11.23#ibcon#about to write, iclass 12, count 0 2006.252.07:48:11.23#ibcon#wrote, iclass 12, count 0 2006.252.07:48:11.23#ibcon#about to read 3, iclass 12, count 0 2006.252.07:48:11.25#ibcon#read 3, iclass 12, count 0 2006.252.07:48:11.25#ibcon#about to read 4, iclass 12, count 0 2006.252.07:48:11.25#ibcon#read 4, iclass 12, count 0 2006.252.07:48:11.25#ibcon#about to read 5, iclass 12, count 0 2006.252.07:48:11.25#ibcon#read 5, iclass 12, count 0 2006.252.07:48:11.25#ibcon#about to read 6, iclass 12, count 0 2006.252.07:48:11.25#ibcon#read 6, iclass 12, count 0 2006.252.07:48:11.25#ibcon#end of sib2, iclass 12, count 0 2006.252.07:48:11.25#ibcon#*mode == 0, iclass 12, count 0 2006.252.07:48:11.25#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.252.07:48:11.25#ibcon#[28=FRQ=03,656.99\r\n] 2006.252.07:48:11.25#ibcon#*before write, iclass 12, count 0 2006.252.07:48:11.25#ibcon#enter sib2, iclass 12, count 0 2006.252.07:48:11.25#ibcon#flushed, iclass 12, count 0 2006.252.07:48:11.25#ibcon#about to write, iclass 12, count 0 2006.252.07:48:11.25#ibcon#wrote, iclass 12, count 0 2006.252.07:48:11.25#ibcon#about to read 3, iclass 12, count 0 2006.252.07:48:11.29#ibcon#read 3, iclass 12, count 0 2006.252.07:48:11.29#ibcon#about to read 4, iclass 12, count 0 2006.252.07:48:11.29#ibcon#read 4, iclass 12, count 0 2006.252.07:48:11.29#ibcon#about to read 5, iclass 12, count 0 2006.252.07:48:11.29#ibcon#read 5, iclass 12, count 0 2006.252.07:48:11.29#ibcon#about to read 6, iclass 12, count 0 2006.252.07:48:11.29#ibcon#read 6, iclass 12, count 0 2006.252.07:48:11.29#ibcon#end of sib2, iclass 12, count 0 2006.252.07:48:11.29#ibcon#*after write, iclass 12, count 0 2006.252.07:48:11.29#ibcon#*before return 0, iclass 12, count 0 2006.252.07:48:11.29#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.252.07:48:11.29#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.252.07:48:11.29#ibcon#about to clear, iclass 12 cls_cnt 0 2006.252.07:48:11.29#ibcon#cleared, iclass 12 cls_cnt 0 2006.252.07:48:11.29$vc4f8/vb=3,4 2006.252.07:48:11.29#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.252.07:48:11.29#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.252.07:48:11.29#ibcon#ireg 11 cls_cnt 2 2006.252.07:48:11.29#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.252.07:48:11.35#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.252.07:48:11.35#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.252.07:48:11.35#ibcon#enter wrdev, iclass 14, count 2 2006.252.07:48:11.35#ibcon#first serial, iclass 14, count 2 2006.252.07:48:11.35#ibcon#enter sib2, iclass 14, count 2 2006.252.07:48:11.35#ibcon#flushed, iclass 14, count 2 2006.252.07:48:11.35#ibcon#about to write, iclass 14, count 2 2006.252.07:48:11.35#ibcon#wrote, iclass 14, count 2 2006.252.07:48:11.35#ibcon#about to read 3, iclass 14, count 2 2006.252.07:48:11.37#ibcon#read 3, iclass 14, count 2 2006.252.07:48:11.37#ibcon#about to read 4, iclass 14, count 2 2006.252.07:48:11.37#ibcon#read 4, iclass 14, count 2 2006.252.07:48:11.37#ibcon#about to read 5, iclass 14, count 2 2006.252.07:48:11.37#ibcon#read 5, iclass 14, count 2 2006.252.07:48:11.37#ibcon#about to read 6, iclass 14, count 2 2006.252.07:48:11.37#ibcon#read 6, iclass 14, count 2 2006.252.07:48:11.37#ibcon#end of sib2, iclass 14, count 2 2006.252.07:48:11.37#ibcon#*mode == 0, iclass 14, count 2 2006.252.07:48:11.37#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.252.07:48:11.37#ibcon#[27=AT03-04\r\n] 2006.252.07:48:11.37#ibcon#*before write, iclass 14, count 2 2006.252.07:48:11.37#ibcon#enter sib2, iclass 14, count 2 2006.252.07:48:11.37#ibcon#flushed, iclass 14, count 2 2006.252.07:48:11.37#ibcon#about to write, iclass 14, count 2 2006.252.07:48:11.37#ibcon#wrote, iclass 14, count 2 2006.252.07:48:11.37#ibcon#about to read 3, iclass 14, count 2 2006.252.07:48:11.40#ibcon#read 3, iclass 14, count 2 2006.252.07:48:11.40#ibcon#about to read 4, iclass 14, count 2 2006.252.07:48:11.40#ibcon#read 4, iclass 14, count 2 2006.252.07:48:11.40#ibcon#about to read 5, iclass 14, count 2 2006.252.07:48:11.40#ibcon#read 5, iclass 14, count 2 2006.252.07:48:11.40#ibcon#about to read 6, iclass 14, count 2 2006.252.07:48:11.40#ibcon#read 6, iclass 14, count 2 2006.252.07:48:11.40#ibcon#end of sib2, iclass 14, count 2 2006.252.07:48:11.40#ibcon#*after write, iclass 14, count 2 2006.252.07:48:11.40#ibcon#*before return 0, iclass 14, count 2 2006.252.07:48:11.40#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.252.07:48:11.40#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.252.07:48:11.40#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.252.07:48:11.40#ibcon#ireg 7 cls_cnt 0 2006.252.07:48:11.40#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.252.07:48:11.52#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.252.07:48:11.52#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.252.07:48:11.52#ibcon#enter wrdev, iclass 14, count 0 2006.252.07:48:11.52#ibcon#first serial, iclass 14, count 0 2006.252.07:48:11.52#ibcon#enter sib2, iclass 14, count 0 2006.252.07:48:11.52#ibcon#flushed, iclass 14, count 0 2006.252.07:48:11.52#ibcon#about to write, iclass 14, count 0 2006.252.07:48:11.52#ibcon#wrote, iclass 14, count 0 2006.252.07:48:11.52#ibcon#about to read 3, iclass 14, count 0 2006.252.07:48:11.54#ibcon#read 3, iclass 14, count 0 2006.252.07:48:11.54#ibcon#about to read 4, iclass 14, count 0 2006.252.07:48:11.54#ibcon#read 4, iclass 14, count 0 2006.252.07:48:11.54#ibcon#about to read 5, iclass 14, count 0 2006.252.07:48:11.54#ibcon#read 5, iclass 14, count 0 2006.252.07:48:11.54#ibcon#about to read 6, iclass 14, count 0 2006.252.07:48:11.54#ibcon#read 6, iclass 14, count 0 2006.252.07:48:11.54#ibcon#end of sib2, iclass 14, count 0 2006.252.07:48:11.54#ibcon#*mode == 0, iclass 14, count 0 2006.252.07:48:11.54#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.252.07:48:11.54#ibcon#[27=USB\r\n] 2006.252.07:48:11.54#ibcon#*before write, iclass 14, count 0 2006.252.07:48:11.54#ibcon#enter sib2, iclass 14, count 0 2006.252.07:48:11.54#ibcon#flushed, iclass 14, count 0 2006.252.07:48:11.54#ibcon#about to write, iclass 14, count 0 2006.252.07:48:11.54#ibcon#wrote, iclass 14, count 0 2006.252.07:48:11.54#ibcon#about to read 3, iclass 14, count 0 2006.252.07:48:11.57#ibcon#read 3, iclass 14, count 0 2006.252.07:48:11.57#ibcon#about to read 4, iclass 14, count 0 2006.252.07:48:11.57#ibcon#read 4, iclass 14, count 0 2006.252.07:48:11.57#ibcon#about to read 5, iclass 14, count 0 2006.252.07:48:11.57#ibcon#read 5, iclass 14, count 0 2006.252.07:48:11.57#ibcon#about to read 6, iclass 14, count 0 2006.252.07:48:11.57#ibcon#read 6, iclass 14, count 0 2006.252.07:48:11.57#ibcon#end of sib2, iclass 14, count 0 2006.252.07:48:11.57#ibcon#*after write, iclass 14, count 0 2006.252.07:48:11.57#ibcon#*before return 0, iclass 14, count 0 2006.252.07:48:11.57#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.252.07:48:11.57#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.252.07:48:11.57#ibcon#about to clear, iclass 14 cls_cnt 0 2006.252.07:48:11.57#ibcon#cleared, iclass 14 cls_cnt 0 2006.252.07:48:11.57$vc4f8/vblo=4,712.99 2006.252.07:48:11.57#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.252.07:48:11.57#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.252.07:48:11.57#ibcon#ireg 17 cls_cnt 0 2006.252.07:48:11.57#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.252.07:48:11.57#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.252.07:48:11.57#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.252.07:48:11.57#ibcon#enter wrdev, iclass 16, count 0 2006.252.07:48:11.57#ibcon#first serial, iclass 16, count 0 2006.252.07:48:11.57#ibcon#enter sib2, iclass 16, count 0 2006.252.07:48:11.57#ibcon#flushed, iclass 16, count 0 2006.252.07:48:11.57#ibcon#about to write, iclass 16, count 0 2006.252.07:48:11.57#ibcon#wrote, iclass 16, count 0 2006.252.07:48:11.57#ibcon#about to read 3, iclass 16, count 0 2006.252.07:48:11.59#ibcon#read 3, iclass 16, count 0 2006.252.07:48:11.59#ibcon#about to read 4, iclass 16, count 0 2006.252.07:48:11.59#ibcon#read 4, iclass 16, count 0 2006.252.07:48:11.59#ibcon#about to read 5, iclass 16, count 0 2006.252.07:48:11.59#ibcon#read 5, iclass 16, count 0 2006.252.07:48:11.59#ibcon#about to read 6, iclass 16, count 0 2006.252.07:48:11.59#ibcon#read 6, iclass 16, count 0 2006.252.07:48:11.59#ibcon#end of sib2, iclass 16, count 0 2006.252.07:48:11.59#ibcon#*mode == 0, iclass 16, count 0 2006.252.07:48:11.59#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.252.07:48:11.59#ibcon#[28=FRQ=04,712.99\r\n] 2006.252.07:48:11.59#ibcon#*before write, iclass 16, count 0 2006.252.07:48:11.59#ibcon#enter sib2, iclass 16, count 0 2006.252.07:48:11.59#ibcon#flushed, iclass 16, count 0 2006.252.07:48:11.59#ibcon#about to write, iclass 16, count 0 2006.252.07:48:11.59#ibcon#wrote, iclass 16, count 0 2006.252.07:48:11.59#ibcon#about to read 3, iclass 16, count 0 2006.252.07:48:11.63#ibcon#read 3, iclass 16, count 0 2006.252.07:48:11.63#ibcon#about to read 4, iclass 16, count 0 2006.252.07:48:11.63#ibcon#read 4, iclass 16, count 0 2006.252.07:48:11.63#ibcon#about to read 5, iclass 16, count 0 2006.252.07:48:11.63#ibcon#read 5, iclass 16, count 0 2006.252.07:48:11.63#ibcon#about to read 6, iclass 16, count 0 2006.252.07:48:11.63#ibcon#read 6, iclass 16, count 0 2006.252.07:48:11.63#ibcon#end of sib2, iclass 16, count 0 2006.252.07:48:11.63#ibcon#*after write, iclass 16, count 0 2006.252.07:48:11.63#ibcon#*before return 0, iclass 16, count 0 2006.252.07:48:11.63#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.252.07:48:11.63#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.252.07:48:11.63#ibcon#about to clear, iclass 16 cls_cnt 0 2006.252.07:48:11.63#ibcon#cleared, iclass 16 cls_cnt 0 2006.252.07:48:11.63$vc4f8/vb=4,4 2006.252.07:48:11.63#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.252.07:48:11.63#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.252.07:48:11.63#ibcon#ireg 11 cls_cnt 2 2006.252.07:48:11.63#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.252.07:48:11.69#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.252.07:48:11.69#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.252.07:48:11.69#ibcon#enter wrdev, iclass 18, count 2 2006.252.07:48:11.69#ibcon#first serial, iclass 18, count 2 2006.252.07:48:11.69#ibcon#enter sib2, iclass 18, count 2 2006.252.07:48:11.69#ibcon#flushed, iclass 18, count 2 2006.252.07:48:11.69#ibcon#about to write, iclass 18, count 2 2006.252.07:48:11.69#ibcon#wrote, iclass 18, count 2 2006.252.07:48:11.69#ibcon#about to read 3, iclass 18, count 2 2006.252.07:48:11.71#ibcon#read 3, iclass 18, count 2 2006.252.07:48:11.71#ibcon#about to read 4, iclass 18, count 2 2006.252.07:48:11.71#ibcon#read 4, iclass 18, count 2 2006.252.07:48:11.71#ibcon#about to read 5, iclass 18, count 2 2006.252.07:48:11.71#ibcon#read 5, iclass 18, count 2 2006.252.07:48:11.71#ibcon#about to read 6, iclass 18, count 2 2006.252.07:48:11.71#ibcon#read 6, iclass 18, count 2 2006.252.07:48:11.71#ibcon#end of sib2, iclass 18, count 2 2006.252.07:48:11.71#ibcon#*mode == 0, iclass 18, count 2 2006.252.07:48:11.71#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.252.07:48:11.71#ibcon#[27=AT04-04\r\n] 2006.252.07:48:11.71#ibcon#*before write, iclass 18, count 2 2006.252.07:48:11.71#ibcon#enter sib2, iclass 18, count 2 2006.252.07:48:11.71#ibcon#flushed, iclass 18, count 2 2006.252.07:48:11.71#ibcon#about to write, iclass 18, count 2 2006.252.07:48:11.71#ibcon#wrote, iclass 18, count 2 2006.252.07:48:11.71#ibcon#about to read 3, iclass 18, count 2 2006.252.07:48:11.74#ibcon#read 3, iclass 18, count 2 2006.252.07:48:11.74#ibcon#about to read 4, iclass 18, count 2 2006.252.07:48:11.74#ibcon#read 4, iclass 18, count 2 2006.252.07:48:11.74#ibcon#about to read 5, iclass 18, count 2 2006.252.07:48:11.74#ibcon#read 5, iclass 18, count 2 2006.252.07:48:11.74#ibcon#about to read 6, iclass 18, count 2 2006.252.07:48:11.74#ibcon#read 6, iclass 18, count 2 2006.252.07:48:11.74#ibcon#end of sib2, iclass 18, count 2 2006.252.07:48:11.74#ibcon#*after write, iclass 18, count 2 2006.252.07:48:11.74#ibcon#*before return 0, iclass 18, count 2 2006.252.07:48:11.74#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.252.07:48:11.74#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.252.07:48:11.74#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.252.07:48:11.74#ibcon#ireg 7 cls_cnt 0 2006.252.07:48:11.74#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.252.07:48:11.86#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.252.07:48:11.86#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.252.07:48:11.86#ibcon#enter wrdev, iclass 18, count 0 2006.252.07:48:11.86#ibcon#first serial, iclass 18, count 0 2006.252.07:48:11.86#ibcon#enter sib2, iclass 18, count 0 2006.252.07:48:11.86#ibcon#flushed, iclass 18, count 0 2006.252.07:48:11.86#ibcon#about to write, iclass 18, count 0 2006.252.07:48:11.86#ibcon#wrote, iclass 18, count 0 2006.252.07:48:11.86#ibcon#about to read 3, iclass 18, count 0 2006.252.07:48:11.88#ibcon#read 3, iclass 18, count 0 2006.252.07:48:11.88#ibcon#about to read 4, iclass 18, count 0 2006.252.07:48:11.88#ibcon#read 4, iclass 18, count 0 2006.252.07:48:11.88#ibcon#about to read 5, iclass 18, count 0 2006.252.07:48:11.88#ibcon#read 5, iclass 18, count 0 2006.252.07:48:11.88#ibcon#about to read 6, iclass 18, count 0 2006.252.07:48:11.88#ibcon#read 6, iclass 18, count 0 2006.252.07:48:11.88#ibcon#end of sib2, iclass 18, count 0 2006.252.07:48:11.88#ibcon#*mode == 0, iclass 18, count 0 2006.252.07:48:11.88#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.252.07:48:11.88#ibcon#[27=USB\r\n] 2006.252.07:48:11.88#ibcon#*before write, iclass 18, count 0 2006.252.07:48:11.88#ibcon#enter sib2, iclass 18, count 0 2006.252.07:48:11.88#ibcon#flushed, iclass 18, count 0 2006.252.07:48:11.88#ibcon#about to write, iclass 18, count 0 2006.252.07:48:11.88#ibcon#wrote, iclass 18, count 0 2006.252.07:48:11.88#ibcon#about to read 3, iclass 18, count 0 2006.252.07:48:11.91#ibcon#read 3, iclass 18, count 0 2006.252.07:48:11.91#ibcon#about to read 4, iclass 18, count 0 2006.252.07:48:11.91#ibcon#read 4, iclass 18, count 0 2006.252.07:48:11.91#ibcon#about to read 5, iclass 18, count 0 2006.252.07:48:11.91#ibcon#read 5, iclass 18, count 0 2006.252.07:48:11.91#ibcon#about to read 6, iclass 18, count 0 2006.252.07:48:11.91#ibcon#read 6, iclass 18, count 0 2006.252.07:48:11.91#ibcon#end of sib2, iclass 18, count 0 2006.252.07:48:11.91#ibcon#*after write, iclass 18, count 0 2006.252.07:48:11.91#ibcon#*before return 0, iclass 18, count 0 2006.252.07:48:11.91#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.252.07:48:11.91#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.252.07:48:11.91#ibcon#about to clear, iclass 18 cls_cnt 0 2006.252.07:48:11.91#ibcon#cleared, iclass 18 cls_cnt 0 2006.252.07:48:11.91$vc4f8/vblo=5,744.99 2006.252.07:48:11.91#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.252.07:48:11.91#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.252.07:48:11.91#ibcon#ireg 17 cls_cnt 0 2006.252.07:48:11.91#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.252.07:48:11.91#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.252.07:48:11.91#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.252.07:48:11.91#ibcon#enter wrdev, iclass 20, count 0 2006.252.07:48:11.91#ibcon#first serial, iclass 20, count 0 2006.252.07:48:11.91#ibcon#enter sib2, iclass 20, count 0 2006.252.07:48:11.91#ibcon#flushed, iclass 20, count 0 2006.252.07:48:11.91#ibcon#about to write, iclass 20, count 0 2006.252.07:48:11.91#ibcon#wrote, iclass 20, count 0 2006.252.07:48:11.91#ibcon#about to read 3, iclass 20, count 0 2006.252.07:48:11.94#ibcon#read 3, iclass 20, count 0 2006.252.07:48:11.94#ibcon#about to read 4, iclass 20, count 0 2006.252.07:48:11.94#ibcon#read 4, iclass 20, count 0 2006.252.07:48:11.94#ibcon#about to read 5, iclass 20, count 0 2006.252.07:48:11.94#ibcon#read 5, iclass 20, count 0 2006.252.07:48:11.94#ibcon#about to read 6, iclass 20, count 0 2006.252.07:48:11.94#ibcon#read 6, iclass 20, count 0 2006.252.07:48:11.94#ibcon#end of sib2, iclass 20, count 0 2006.252.07:48:11.94#ibcon#*mode == 0, iclass 20, count 0 2006.252.07:48:11.94#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.252.07:48:11.94#ibcon#[28=FRQ=05,744.99\r\n] 2006.252.07:48:11.94#ibcon#*before write, iclass 20, count 0 2006.252.07:48:11.94#ibcon#enter sib2, iclass 20, count 0 2006.252.07:48:11.94#ibcon#flushed, iclass 20, count 0 2006.252.07:48:11.94#ibcon#about to write, iclass 20, count 0 2006.252.07:48:11.94#ibcon#wrote, iclass 20, count 0 2006.252.07:48:11.94#ibcon#about to read 3, iclass 20, count 0 2006.252.07:48:11.98#ibcon#read 3, iclass 20, count 0 2006.252.07:48:11.98#ibcon#about to read 4, iclass 20, count 0 2006.252.07:48:11.98#ibcon#read 4, iclass 20, count 0 2006.252.07:48:11.98#ibcon#about to read 5, iclass 20, count 0 2006.252.07:48:11.98#ibcon#read 5, iclass 20, count 0 2006.252.07:48:11.98#ibcon#about to read 6, iclass 20, count 0 2006.252.07:48:11.98#ibcon#read 6, iclass 20, count 0 2006.252.07:48:11.98#ibcon#end of sib2, iclass 20, count 0 2006.252.07:48:11.98#ibcon#*after write, iclass 20, count 0 2006.252.07:48:11.98#ibcon#*before return 0, iclass 20, count 0 2006.252.07:48:11.98#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.252.07:48:11.98#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.252.07:48:11.98#ibcon#about to clear, iclass 20 cls_cnt 0 2006.252.07:48:11.98#ibcon#cleared, iclass 20 cls_cnt 0 2006.252.07:48:11.98$vc4f8/vb=5,4 2006.252.07:48:11.98#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.252.07:48:11.98#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.252.07:48:11.98#ibcon#ireg 11 cls_cnt 2 2006.252.07:48:11.98#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.252.07:48:12.03#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.252.07:48:12.03#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.252.07:48:12.03#ibcon#enter wrdev, iclass 22, count 2 2006.252.07:48:12.03#ibcon#first serial, iclass 22, count 2 2006.252.07:48:12.03#ibcon#enter sib2, iclass 22, count 2 2006.252.07:48:12.03#ibcon#flushed, iclass 22, count 2 2006.252.07:48:12.03#ibcon#about to write, iclass 22, count 2 2006.252.07:48:12.03#ibcon#wrote, iclass 22, count 2 2006.252.07:48:12.03#ibcon#about to read 3, iclass 22, count 2 2006.252.07:48:12.05#ibcon#read 3, iclass 22, count 2 2006.252.07:48:12.05#ibcon#about to read 4, iclass 22, count 2 2006.252.07:48:12.05#ibcon#read 4, iclass 22, count 2 2006.252.07:48:12.05#ibcon#about to read 5, iclass 22, count 2 2006.252.07:48:12.05#ibcon#read 5, iclass 22, count 2 2006.252.07:48:12.05#ibcon#about to read 6, iclass 22, count 2 2006.252.07:48:12.05#ibcon#read 6, iclass 22, count 2 2006.252.07:48:12.05#ibcon#end of sib2, iclass 22, count 2 2006.252.07:48:12.05#ibcon#*mode == 0, iclass 22, count 2 2006.252.07:48:12.05#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.252.07:48:12.05#ibcon#[27=AT05-04\r\n] 2006.252.07:48:12.05#ibcon#*before write, iclass 22, count 2 2006.252.07:48:12.05#ibcon#enter sib2, iclass 22, count 2 2006.252.07:48:12.05#ibcon#flushed, iclass 22, count 2 2006.252.07:48:12.05#ibcon#about to write, iclass 22, count 2 2006.252.07:48:12.05#ibcon#wrote, iclass 22, count 2 2006.252.07:48:12.05#ibcon#about to read 3, iclass 22, count 2 2006.252.07:48:12.08#ibcon#read 3, iclass 22, count 2 2006.252.07:48:12.08#ibcon#about to read 4, iclass 22, count 2 2006.252.07:48:12.08#ibcon#read 4, iclass 22, count 2 2006.252.07:48:12.08#ibcon#about to read 5, iclass 22, count 2 2006.252.07:48:12.08#ibcon#read 5, iclass 22, count 2 2006.252.07:48:12.08#ibcon#about to read 6, iclass 22, count 2 2006.252.07:48:12.08#ibcon#read 6, iclass 22, count 2 2006.252.07:48:12.08#ibcon#end of sib2, iclass 22, count 2 2006.252.07:48:12.08#ibcon#*after write, iclass 22, count 2 2006.252.07:48:12.08#ibcon#*before return 0, iclass 22, count 2 2006.252.07:48:12.08#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.252.07:48:12.08#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.252.07:48:12.08#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.252.07:48:12.08#ibcon#ireg 7 cls_cnt 0 2006.252.07:48:12.08#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.252.07:48:12.20#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.252.07:48:12.20#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.252.07:48:12.20#ibcon#enter wrdev, iclass 22, count 0 2006.252.07:48:12.20#ibcon#first serial, iclass 22, count 0 2006.252.07:48:12.20#ibcon#enter sib2, iclass 22, count 0 2006.252.07:48:12.20#ibcon#flushed, iclass 22, count 0 2006.252.07:48:12.20#ibcon#about to write, iclass 22, count 0 2006.252.07:48:12.20#ibcon#wrote, iclass 22, count 0 2006.252.07:48:12.20#ibcon#about to read 3, iclass 22, count 0 2006.252.07:48:12.22#ibcon#read 3, iclass 22, count 0 2006.252.07:48:12.22#ibcon#about to read 4, iclass 22, count 0 2006.252.07:48:12.22#ibcon#read 4, iclass 22, count 0 2006.252.07:48:12.22#ibcon#about to read 5, iclass 22, count 0 2006.252.07:48:12.22#ibcon#read 5, iclass 22, count 0 2006.252.07:48:12.22#ibcon#about to read 6, iclass 22, count 0 2006.252.07:48:12.22#ibcon#read 6, iclass 22, count 0 2006.252.07:48:12.22#ibcon#end of sib2, iclass 22, count 0 2006.252.07:48:12.22#ibcon#*mode == 0, iclass 22, count 0 2006.252.07:48:12.22#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.252.07:48:12.22#ibcon#[27=USB\r\n] 2006.252.07:48:12.22#ibcon#*before write, iclass 22, count 0 2006.252.07:48:12.22#ibcon#enter sib2, iclass 22, count 0 2006.252.07:48:12.22#ibcon#flushed, iclass 22, count 0 2006.252.07:48:12.22#ibcon#about to write, iclass 22, count 0 2006.252.07:48:12.22#ibcon#wrote, iclass 22, count 0 2006.252.07:48:12.22#ibcon#about to read 3, iclass 22, count 0 2006.252.07:48:12.25#ibcon#read 3, iclass 22, count 0 2006.252.07:48:12.25#ibcon#about to read 4, iclass 22, count 0 2006.252.07:48:12.25#ibcon#read 4, iclass 22, count 0 2006.252.07:48:12.25#ibcon#about to read 5, iclass 22, count 0 2006.252.07:48:12.25#ibcon#read 5, iclass 22, count 0 2006.252.07:48:12.25#ibcon#about to read 6, iclass 22, count 0 2006.252.07:48:12.25#ibcon#read 6, iclass 22, count 0 2006.252.07:48:12.25#ibcon#end of sib2, iclass 22, count 0 2006.252.07:48:12.25#ibcon#*after write, iclass 22, count 0 2006.252.07:48:12.25#ibcon#*before return 0, iclass 22, count 0 2006.252.07:48:12.25#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.252.07:48:12.25#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.252.07:48:12.25#ibcon#about to clear, iclass 22 cls_cnt 0 2006.252.07:48:12.25#ibcon#cleared, iclass 22 cls_cnt 0 2006.252.07:48:12.25$vc4f8/vblo=6,752.99 2006.252.07:48:12.25#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.252.07:48:12.25#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.252.07:48:12.25#ibcon#ireg 17 cls_cnt 0 2006.252.07:48:12.25#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.252.07:48:12.25#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.252.07:48:12.25#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.252.07:48:12.25#ibcon#enter wrdev, iclass 24, count 0 2006.252.07:48:12.25#ibcon#first serial, iclass 24, count 0 2006.252.07:48:12.25#ibcon#enter sib2, iclass 24, count 0 2006.252.07:48:12.25#ibcon#flushed, iclass 24, count 0 2006.252.07:48:12.25#ibcon#about to write, iclass 24, count 0 2006.252.07:48:12.25#ibcon#wrote, iclass 24, count 0 2006.252.07:48:12.25#ibcon#about to read 3, iclass 24, count 0 2006.252.07:48:12.27#ibcon#read 3, iclass 24, count 0 2006.252.07:48:12.27#ibcon#about to read 4, iclass 24, count 0 2006.252.07:48:12.27#ibcon#read 4, iclass 24, count 0 2006.252.07:48:12.27#ibcon#about to read 5, iclass 24, count 0 2006.252.07:48:12.27#ibcon#read 5, iclass 24, count 0 2006.252.07:48:12.27#ibcon#about to read 6, iclass 24, count 0 2006.252.07:48:12.27#ibcon#read 6, iclass 24, count 0 2006.252.07:48:12.27#ibcon#end of sib2, iclass 24, count 0 2006.252.07:48:12.27#ibcon#*mode == 0, iclass 24, count 0 2006.252.07:48:12.27#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.252.07:48:12.27#ibcon#[28=FRQ=06,752.99\r\n] 2006.252.07:48:12.27#ibcon#*before write, iclass 24, count 0 2006.252.07:48:12.27#ibcon#enter sib2, iclass 24, count 0 2006.252.07:48:12.27#ibcon#flushed, iclass 24, count 0 2006.252.07:48:12.27#ibcon#about to write, iclass 24, count 0 2006.252.07:48:12.27#ibcon#wrote, iclass 24, count 0 2006.252.07:48:12.27#ibcon#about to read 3, iclass 24, count 0 2006.252.07:48:12.31#ibcon#read 3, iclass 24, count 0 2006.252.07:48:12.31#ibcon#about to read 4, iclass 24, count 0 2006.252.07:48:12.31#ibcon#read 4, iclass 24, count 0 2006.252.07:48:12.31#ibcon#about to read 5, iclass 24, count 0 2006.252.07:48:12.31#ibcon#read 5, iclass 24, count 0 2006.252.07:48:12.31#ibcon#about to read 6, iclass 24, count 0 2006.252.07:48:12.31#ibcon#read 6, iclass 24, count 0 2006.252.07:48:12.31#ibcon#end of sib2, iclass 24, count 0 2006.252.07:48:12.31#ibcon#*after write, iclass 24, count 0 2006.252.07:48:12.31#ibcon#*before return 0, iclass 24, count 0 2006.252.07:48:12.31#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.252.07:48:12.31#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.252.07:48:12.31#ibcon#about to clear, iclass 24 cls_cnt 0 2006.252.07:48:12.31#ibcon#cleared, iclass 24 cls_cnt 0 2006.252.07:48:12.31$vc4f8/vb=6,4 2006.252.07:48:12.31#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.252.07:48:12.31#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.252.07:48:12.31#ibcon#ireg 11 cls_cnt 2 2006.252.07:48:12.31#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.252.07:48:12.37#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.252.07:48:12.37#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.252.07:48:12.37#ibcon#enter wrdev, iclass 26, count 2 2006.252.07:48:12.37#ibcon#first serial, iclass 26, count 2 2006.252.07:48:12.37#ibcon#enter sib2, iclass 26, count 2 2006.252.07:48:12.37#ibcon#flushed, iclass 26, count 2 2006.252.07:48:12.37#ibcon#about to write, iclass 26, count 2 2006.252.07:48:12.37#ibcon#wrote, iclass 26, count 2 2006.252.07:48:12.37#ibcon#about to read 3, iclass 26, count 2 2006.252.07:48:12.39#ibcon#read 3, iclass 26, count 2 2006.252.07:48:12.39#ibcon#about to read 4, iclass 26, count 2 2006.252.07:48:12.39#ibcon#read 4, iclass 26, count 2 2006.252.07:48:12.39#ibcon#about to read 5, iclass 26, count 2 2006.252.07:48:12.39#ibcon#read 5, iclass 26, count 2 2006.252.07:48:12.39#ibcon#about to read 6, iclass 26, count 2 2006.252.07:48:12.39#ibcon#read 6, iclass 26, count 2 2006.252.07:48:12.39#ibcon#end of sib2, iclass 26, count 2 2006.252.07:48:12.39#ibcon#*mode == 0, iclass 26, count 2 2006.252.07:48:12.39#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.252.07:48:12.39#ibcon#[27=AT06-04\r\n] 2006.252.07:48:12.39#ibcon#*before write, iclass 26, count 2 2006.252.07:48:12.39#ibcon#enter sib2, iclass 26, count 2 2006.252.07:48:12.39#ibcon#flushed, iclass 26, count 2 2006.252.07:48:12.39#ibcon#about to write, iclass 26, count 2 2006.252.07:48:12.39#ibcon#wrote, iclass 26, count 2 2006.252.07:48:12.39#ibcon#about to read 3, iclass 26, count 2 2006.252.07:48:12.42#ibcon#read 3, iclass 26, count 2 2006.252.07:48:12.42#ibcon#about to read 4, iclass 26, count 2 2006.252.07:48:12.42#ibcon#read 4, iclass 26, count 2 2006.252.07:48:12.42#ibcon#about to read 5, iclass 26, count 2 2006.252.07:48:12.42#ibcon#read 5, iclass 26, count 2 2006.252.07:48:12.42#ibcon#about to read 6, iclass 26, count 2 2006.252.07:48:12.42#ibcon#read 6, iclass 26, count 2 2006.252.07:48:12.42#ibcon#end of sib2, iclass 26, count 2 2006.252.07:48:12.42#ibcon#*after write, iclass 26, count 2 2006.252.07:48:12.42#ibcon#*before return 0, iclass 26, count 2 2006.252.07:48:12.42#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.252.07:48:12.42#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.252.07:48:12.42#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.252.07:48:12.42#ibcon#ireg 7 cls_cnt 0 2006.252.07:48:12.42#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.252.07:48:12.54#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.252.07:48:12.54#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.252.07:48:12.54#ibcon#enter wrdev, iclass 26, count 0 2006.252.07:48:12.54#ibcon#first serial, iclass 26, count 0 2006.252.07:48:12.54#ibcon#enter sib2, iclass 26, count 0 2006.252.07:48:12.54#ibcon#flushed, iclass 26, count 0 2006.252.07:48:12.54#ibcon#about to write, iclass 26, count 0 2006.252.07:48:12.54#ibcon#wrote, iclass 26, count 0 2006.252.07:48:12.54#ibcon#about to read 3, iclass 26, count 0 2006.252.07:48:12.56#ibcon#read 3, iclass 26, count 0 2006.252.07:48:12.56#ibcon#about to read 4, iclass 26, count 0 2006.252.07:48:12.56#ibcon#read 4, iclass 26, count 0 2006.252.07:48:12.56#ibcon#about to read 5, iclass 26, count 0 2006.252.07:48:12.56#ibcon#read 5, iclass 26, count 0 2006.252.07:48:12.56#ibcon#about to read 6, iclass 26, count 0 2006.252.07:48:12.56#ibcon#read 6, iclass 26, count 0 2006.252.07:48:12.56#ibcon#end of sib2, iclass 26, count 0 2006.252.07:48:12.56#ibcon#*mode == 0, iclass 26, count 0 2006.252.07:48:12.56#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.252.07:48:12.56#ibcon#[27=USB\r\n] 2006.252.07:48:12.56#ibcon#*before write, iclass 26, count 0 2006.252.07:48:12.56#ibcon#enter sib2, iclass 26, count 0 2006.252.07:48:12.56#ibcon#flushed, iclass 26, count 0 2006.252.07:48:12.56#ibcon#about to write, iclass 26, count 0 2006.252.07:48:12.56#ibcon#wrote, iclass 26, count 0 2006.252.07:48:12.56#ibcon#about to read 3, iclass 26, count 0 2006.252.07:48:12.59#ibcon#read 3, iclass 26, count 0 2006.252.07:48:12.59#ibcon#about to read 4, iclass 26, count 0 2006.252.07:48:12.59#ibcon#read 4, iclass 26, count 0 2006.252.07:48:12.59#ibcon#about to read 5, iclass 26, count 0 2006.252.07:48:12.59#ibcon#read 5, iclass 26, count 0 2006.252.07:48:12.59#ibcon#about to read 6, iclass 26, count 0 2006.252.07:48:12.59#ibcon#read 6, iclass 26, count 0 2006.252.07:48:12.59#ibcon#end of sib2, iclass 26, count 0 2006.252.07:48:12.59#ibcon#*after write, iclass 26, count 0 2006.252.07:48:12.59#ibcon#*before return 0, iclass 26, count 0 2006.252.07:48:12.59#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.252.07:48:12.59#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.252.07:48:12.59#ibcon#about to clear, iclass 26 cls_cnt 0 2006.252.07:48:12.59#ibcon#cleared, iclass 26 cls_cnt 0 2006.252.07:48:12.59$vc4f8/vabw=wide 2006.252.07:48:12.59#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.252.07:48:12.59#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.252.07:48:12.59#ibcon#ireg 8 cls_cnt 0 2006.252.07:48:12.59#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.252.07:48:12.59#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.252.07:48:12.59#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.252.07:48:12.59#ibcon#enter wrdev, iclass 28, count 0 2006.252.07:48:12.59#ibcon#first serial, iclass 28, count 0 2006.252.07:48:12.59#ibcon#enter sib2, iclass 28, count 0 2006.252.07:48:12.59#ibcon#flushed, iclass 28, count 0 2006.252.07:48:12.59#ibcon#about to write, iclass 28, count 0 2006.252.07:48:12.59#ibcon#wrote, iclass 28, count 0 2006.252.07:48:12.59#ibcon#about to read 3, iclass 28, count 0 2006.252.07:48:12.62#ibcon#read 3, iclass 28, count 0 2006.252.07:48:12.62#ibcon#about to read 4, iclass 28, count 0 2006.252.07:48:12.62#ibcon#read 4, iclass 28, count 0 2006.252.07:48:12.62#ibcon#about to read 5, iclass 28, count 0 2006.252.07:48:12.62#ibcon#read 5, iclass 28, count 0 2006.252.07:48:12.62#ibcon#about to read 6, iclass 28, count 0 2006.252.07:48:12.62#ibcon#read 6, iclass 28, count 0 2006.252.07:48:12.62#ibcon#end of sib2, iclass 28, count 0 2006.252.07:48:12.62#ibcon#*mode == 0, iclass 28, count 0 2006.252.07:48:12.62#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.252.07:48:12.62#ibcon#[25=BW32\r\n] 2006.252.07:48:12.62#ibcon#*before write, iclass 28, count 0 2006.252.07:48:12.62#ibcon#enter sib2, iclass 28, count 0 2006.252.07:48:12.62#ibcon#flushed, iclass 28, count 0 2006.252.07:48:12.62#ibcon#about to write, iclass 28, count 0 2006.252.07:48:12.62#ibcon#wrote, iclass 28, count 0 2006.252.07:48:12.62#ibcon#about to read 3, iclass 28, count 0 2006.252.07:48:12.65#ibcon#read 3, iclass 28, count 0 2006.252.07:48:12.65#ibcon#about to read 4, iclass 28, count 0 2006.252.07:48:12.65#ibcon#read 4, iclass 28, count 0 2006.252.07:48:12.65#ibcon#about to read 5, iclass 28, count 0 2006.252.07:48:12.65#ibcon#read 5, iclass 28, count 0 2006.252.07:48:12.65#ibcon#about to read 6, iclass 28, count 0 2006.252.07:48:12.65#ibcon#read 6, iclass 28, count 0 2006.252.07:48:12.65#ibcon#end of sib2, iclass 28, count 0 2006.252.07:48:12.65#ibcon#*after write, iclass 28, count 0 2006.252.07:48:12.65#ibcon#*before return 0, iclass 28, count 0 2006.252.07:48:12.65#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.252.07:48:12.65#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.252.07:48:12.65#ibcon#about to clear, iclass 28 cls_cnt 0 2006.252.07:48:12.65#ibcon#cleared, iclass 28 cls_cnt 0 2006.252.07:48:12.65$vc4f8/vbbw=wide 2006.252.07:48:12.65#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.252.07:48:12.65#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.252.07:48:12.65#ibcon#ireg 8 cls_cnt 0 2006.252.07:48:12.65#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.252.07:48:12.71#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.252.07:48:12.71#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.252.07:48:12.71#ibcon#enter wrdev, iclass 30, count 0 2006.252.07:48:12.71#ibcon#first serial, iclass 30, count 0 2006.252.07:48:12.71#ibcon#enter sib2, iclass 30, count 0 2006.252.07:48:12.71#ibcon#flushed, iclass 30, count 0 2006.252.07:48:12.71#ibcon#about to write, iclass 30, count 0 2006.252.07:48:12.71#ibcon#wrote, iclass 30, count 0 2006.252.07:48:12.71#ibcon#about to read 3, iclass 30, count 0 2006.252.07:48:12.73#ibcon#read 3, iclass 30, count 0 2006.252.07:48:12.73#ibcon#about to read 4, iclass 30, count 0 2006.252.07:48:12.73#ibcon#read 4, iclass 30, count 0 2006.252.07:48:12.73#ibcon#about to read 5, iclass 30, count 0 2006.252.07:48:12.73#ibcon#read 5, iclass 30, count 0 2006.252.07:48:12.73#ibcon#about to read 6, iclass 30, count 0 2006.252.07:48:12.73#ibcon#read 6, iclass 30, count 0 2006.252.07:48:12.73#ibcon#end of sib2, iclass 30, count 0 2006.252.07:48:12.73#ibcon#*mode == 0, iclass 30, count 0 2006.252.07:48:12.73#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.252.07:48:12.73#ibcon#[27=BW32\r\n] 2006.252.07:48:12.73#ibcon#*before write, iclass 30, count 0 2006.252.07:48:12.73#ibcon#enter sib2, iclass 30, count 0 2006.252.07:48:12.73#ibcon#flushed, iclass 30, count 0 2006.252.07:48:12.73#ibcon#about to write, iclass 30, count 0 2006.252.07:48:12.73#ibcon#wrote, iclass 30, count 0 2006.252.07:48:12.73#ibcon#about to read 3, iclass 30, count 0 2006.252.07:48:12.76#ibcon#read 3, iclass 30, count 0 2006.252.07:48:12.76#ibcon#about to read 4, iclass 30, count 0 2006.252.07:48:12.76#ibcon#read 4, iclass 30, count 0 2006.252.07:48:12.76#ibcon#about to read 5, iclass 30, count 0 2006.252.07:48:12.76#ibcon#read 5, iclass 30, count 0 2006.252.07:48:12.76#ibcon#about to read 6, iclass 30, count 0 2006.252.07:48:12.76#ibcon#read 6, iclass 30, count 0 2006.252.07:48:12.76#ibcon#end of sib2, iclass 30, count 0 2006.252.07:48:12.76#ibcon#*after write, iclass 30, count 0 2006.252.07:48:12.76#ibcon#*before return 0, iclass 30, count 0 2006.252.07:48:12.76#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.252.07:48:12.76#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.252.07:48:12.76#ibcon#about to clear, iclass 30 cls_cnt 0 2006.252.07:48:12.76#ibcon#cleared, iclass 30 cls_cnt 0 2006.252.07:48:12.76$4f8m12a/ifd4f 2006.252.07:48:12.76$ifd4f/lo= 2006.252.07:48:12.76$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.252.07:48:12.76$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.252.07:48:12.76$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.252.07:48:12.76$ifd4f/patch= 2006.252.07:48:12.76$ifd4f/patch=lo1,a1,a2,a3,a4 2006.252.07:48:12.76$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.252.07:48:12.76$ifd4f/patch=lo3,a5,a6,a7,a8 2006.252.07:48:12.76$4f8m12a/"form=m,16.000,1:2 2006.252.07:48:12.76$4f8m12a/"tpicd 2006.252.07:48:12.76$4f8m12a/echo=off 2006.252.07:48:12.76$4f8m12a/xlog=off 2006.252.07:48:12.76:!2006.252.07:48:40 2006.252.07:48:21.14#trakl#Source acquired 2006.252.07:48:22.14#flagr#flagr/antenna,acquired 2006.252.07:48:40.00:preob 2006.252.07:48:41.14/onsource/TRACKING 2006.252.07:48:41.14:!2006.252.07:48:50 2006.252.07:48:50.00:data_valid=on 2006.252.07:48:50.00:midob 2006.252.07:48:50.14/onsource/TRACKING 2006.252.07:48:50.14/wx/27.39,1011.2,90 2006.252.07:48:50.31/cable/+6.4097E-03 2006.252.07:48:51.40/va/01,08,usb,yes,32,34 2006.252.07:48:51.40/va/02,07,usb,yes,32,34 2006.252.07:48:51.40/va/03,06,usb,yes,34,34 2006.252.07:48:51.40/va/04,07,usb,yes,33,35 2006.252.07:48:51.40/va/05,07,usb,yes,36,38 2006.252.07:48:51.40/va/06,07,usb,yes,31,31 2006.252.07:48:51.40/va/07,07,usb,yes,31,31 2006.252.07:48:51.40/va/08,07,usb,yes,33,33 2006.252.07:48:51.63/valo/01,532.99,yes,locked 2006.252.07:48:51.63/valo/02,572.99,yes,locked 2006.252.07:48:51.63/valo/03,672.99,yes,locked 2006.252.07:48:51.63/valo/04,832.99,yes,locked 2006.252.07:48:51.63/valo/05,652.99,yes,locked 2006.252.07:48:51.63/valo/06,772.99,yes,locked 2006.252.07:48:51.63/valo/07,832.99,yes,locked 2006.252.07:48:51.63/valo/08,852.99,yes,locked 2006.252.07:48:52.72/vb/01,04,usb,yes,30,29 2006.252.07:48:52.72/vb/02,05,usb,yes,28,30 2006.252.07:48:52.72/vb/03,04,usb,yes,28,32 2006.252.07:48:52.72/vb/04,04,usb,yes,29,29 2006.252.07:48:52.72/vb/05,04,usb,yes,28,32 2006.252.07:48:52.72/vb/06,04,usb,yes,29,32 2006.252.07:48:52.72/vb/07,04,usb,yes,31,31 2006.252.07:48:52.72/vb/08,04,usb,yes,28,32 2006.252.07:48:52.95/vblo/01,632.99,yes,locked 2006.252.07:48:52.95/vblo/02,640.99,yes,locked 2006.252.07:48:52.95/vblo/03,656.99,yes,locked 2006.252.07:48:52.95/vblo/04,712.99,yes,locked 2006.252.07:48:52.95/vblo/05,744.99,yes,locked 2006.252.07:48:52.95/vblo/06,752.99,yes,locked 2006.252.07:48:52.95/vblo/07,734.99,yes,locked 2006.252.07:48:52.95/vblo/08,744.99,yes,locked 2006.252.07:48:53.10/vabw/8 2006.252.07:48:53.25/vbbw/8 2006.252.07:48:53.34/xfe/off,on,14.2 2006.252.07:48:53.71/ifatt/23,28,28,28 2006.252.07:48:54.07/fmout-gps/S +4.80E-07 2006.252.07:48:54.11:!2006.252.07:49:50 2006.252.07:49:50.01:data_valid=off 2006.252.07:49:50.02:postob 2006.252.07:49:50.07/cable/+6.4078E-03 2006.252.07:49:50.08/wx/27.39,1011.2,90 2006.252.07:49:51.07/fmout-gps/S +4.81E-07 2006.252.07:49:51.08:scan_name=252-0750,k06252,70 2006.252.07:49:51.08:source=3c418,203837.03,511912.7,2000.0,cw 2006.252.07:49:51.14#flagr#flagr/antenna,new-source 2006.252.07:49:52.14:checkk5 2006.252.07:49:52.51/chk_autoobs//k5ts1/ autoobs is running! 2006.252.07:49:52.89/chk_autoobs//k5ts2/ autoobs is running! 2006.252.07:49:53.28/chk_autoobs//k5ts3/ autoobs is running! 2006.252.07:49:53.65/chk_autoobs//k5ts4/ autoobs is running! 2006.252.07:49:54.02/chk_obsdata//k5ts1/T2520748??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.07:49:54.39/chk_obsdata//k5ts2/T2520748??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.07:49:54.75/chk_obsdata//k5ts3/T2520748??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.07:49:55.13/chk_obsdata//k5ts4/T2520748??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.07:49:55.83/k5log//k5ts1_log_newline 2006.252.07:49:56.53/k5log//k5ts2_log_newline 2006.252.07:49:57.22/k5log//k5ts3_log_newline 2006.252.07:49:57.91/k5log//k5ts4_log_newline 2006.252.07:49:57.93/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.252.07:49:57.93:4f8m12a=1 2006.252.07:49:57.93$4f8m12a/echo=on 2006.252.07:49:57.93$4f8m12a/pcalon 2006.252.07:49:57.93$pcalon/"no phase cal control is implemented here 2006.252.07:49:57.93$4f8m12a/"tpicd=stop 2006.252.07:49:57.93$4f8m12a/vc4f8 2006.252.07:49:57.93$vc4f8/valo=1,532.99 2006.252.07:49:57.93#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.252.07:49:57.93#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.252.07:49:57.93#ibcon#ireg 17 cls_cnt 0 2006.252.07:49:57.93#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.252.07:49:57.93#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.252.07:49:57.93#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.252.07:49:57.93#ibcon#enter wrdev, iclass 32, count 0 2006.252.07:49:57.93#ibcon#first serial, iclass 32, count 0 2006.252.07:49:57.93#ibcon#enter sib2, iclass 32, count 0 2006.252.07:49:57.93#ibcon#flushed, iclass 32, count 0 2006.252.07:49:57.93#ibcon#about to write, iclass 32, count 0 2006.252.07:49:57.93#ibcon#wrote, iclass 32, count 0 2006.252.07:49:57.93#ibcon#about to read 3, iclass 32, count 0 2006.252.07:49:57.98#ibcon#read 3, iclass 32, count 0 2006.252.07:49:57.98#ibcon#about to read 4, iclass 32, count 0 2006.252.07:49:57.98#ibcon#read 4, iclass 32, count 0 2006.252.07:49:57.98#ibcon#about to read 5, iclass 32, count 0 2006.252.07:49:57.98#ibcon#read 5, iclass 32, count 0 2006.252.07:49:57.98#ibcon#about to read 6, iclass 32, count 0 2006.252.07:49:57.98#ibcon#read 6, iclass 32, count 0 2006.252.07:49:57.98#ibcon#end of sib2, iclass 32, count 0 2006.252.07:49:57.98#ibcon#*mode == 0, iclass 32, count 0 2006.252.07:49:57.98#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.252.07:49:57.98#ibcon#[26=FRQ=01,532.99\r\n] 2006.252.07:49:57.98#ibcon#*before write, iclass 32, count 0 2006.252.07:49:57.98#ibcon#enter sib2, iclass 32, count 0 2006.252.07:49:57.98#ibcon#flushed, iclass 32, count 0 2006.252.07:49:57.98#ibcon#about to write, iclass 32, count 0 2006.252.07:49:57.98#ibcon#wrote, iclass 32, count 0 2006.252.07:49:57.98#ibcon#about to read 3, iclass 32, count 0 2006.252.07:49:58.02#ibcon#read 3, iclass 32, count 0 2006.252.07:49:58.02#ibcon#about to read 4, iclass 32, count 0 2006.252.07:49:58.02#ibcon#read 4, iclass 32, count 0 2006.252.07:49:58.02#ibcon#about to read 5, iclass 32, count 0 2006.252.07:49:58.02#ibcon#read 5, iclass 32, count 0 2006.252.07:49:58.02#ibcon#about to read 6, iclass 32, count 0 2006.252.07:49:58.02#ibcon#read 6, iclass 32, count 0 2006.252.07:49:58.02#ibcon#end of sib2, iclass 32, count 0 2006.252.07:49:58.02#ibcon#*after write, iclass 32, count 0 2006.252.07:49:58.02#ibcon#*before return 0, iclass 32, count 0 2006.252.07:49:58.02#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.252.07:49:58.02#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.252.07:49:58.02#ibcon#about to clear, iclass 32 cls_cnt 0 2006.252.07:49:58.02#ibcon#cleared, iclass 32 cls_cnt 0 2006.252.07:49:58.02$vc4f8/va=1,8 2006.252.07:49:58.02#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.252.07:49:58.02#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.252.07:49:58.02#ibcon#ireg 11 cls_cnt 2 2006.252.07:49:58.02#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.252.07:49:58.02#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.252.07:49:58.02#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.252.07:49:58.02#ibcon#enter wrdev, iclass 34, count 2 2006.252.07:49:58.02#ibcon#first serial, iclass 34, count 2 2006.252.07:49:58.02#ibcon#enter sib2, iclass 34, count 2 2006.252.07:49:58.02#ibcon#flushed, iclass 34, count 2 2006.252.07:49:58.02#ibcon#about to write, iclass 34, count 2 2006.252.07:49:58.02#ibcon#wrote, iclass 34, count 2 2006.252.07:49:58.02#ibcon#about to read 3, iclass 34, count 2 2006.252.07:49:58.04#ibcon#read 3, iclass 34, count 2 2006.252.07:49:58.04#ibcon#about to read 4, iclass 34, count 2 2006.252.07:49:58.04#ibcon#read 4, iclass 34, count 2 2006.252.07:49:58.04#ibcon#about to read 5, iclass 34, count 2 2006.252.07:49:58.04#ibcon#read 5, iclass 34, count 2 2006.252.07:49:58.04#ibcon#about to read 6, iclass 34, count 2 2006.252.07:49:58.04#ibcon#read 6, iclass 34, count 2 2006.252.07:49:58.04#ibcon#end of sib2, iclass 34, count 2 2006.252.07:49:58.04#ibcon#*mode == 0, iclass 34, count 2 2006.252.07:49:58.04#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.252.07:49:58.04#ibcon#[25=AT01-08\r\n] 2006.252.07:49:58.04#ibcon#*before write, iclass 34, count 2 2006.252.07:49:58.04#ibcon#enter sib2, iclass 34, count 2 2006.252.07:49:58.04#ibcon#flushed, iclass 34, count 2 2006.252.07:49:58.04#ibcon#about to write, iclass 34, count 2 2006.252.07:49:58.04#ibcon#wrote, iclass 34, count 2 2006.252.07:49:58.04#ibcon#about to read 3, iclass 34, count 2 2006.252.07:49:58.07#ibcon#read 3, iclass 34, count 2 2006.252.07:49:58.07#ibcon#about to read 4, iclass 34, count 2 2006.252.07:49:58.07#ibcon#read 4, iclass 34, count 2 2006.252.07:49:58.07#ibcon#about to read 5, iclass 34, count 2 2006.252.07:49:58.07#ibcon#read 5, iclass 34, count 2 2006.252.07:49:58.07#ibcon#about to read 6, iclass 34, count 2 2006.252.07:49:58.07#ibcon#read 6, iclass 34, count 2 2006.252.07:49:58.07#ibcon#end of sib2, iclass 34, count 2 2006.252.07:49:58.07#ibcon#*after write, iclass 34, count 2 2006.252.07:49:58.07#ibcon#*before return 0, iclass 34, count 2 2006.252.07:49:58.07#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.252.07:49:58.07#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.252.07:49:58.07#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.252.07:49:58.07#ibcon#ireg 7 cls_cnt 0 2006.252.07:49:58.07#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.252.07:49:58.19#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.252.07:49:58.19#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.252.07:49:58.19#ibcon#enter wrdev, iclass 34, count 0 2006.252.07:49:58.19#ibcon#first serial, iclass 34, count 0 2006.252.07:49:58.19#ibcon#enter sib2, iclass 34, count 0 2006.252.07:49:58.19#ibcon#flushed, iclass 34, count 0 2006.252.07:49:58.19#ibcon#about to write, iclass 34, count 0 2006.252.07:49:58.19#ibcon#wrote, iclass 34, count 0 2006.252.07:49:58.19#ibcon#about to read 3, iclass 34, count 0 2006.252.07:49:58.21#ibcon#read 3, iclass 34, count 0 2006.252.07:49:58.21#ibcon#about to read 4, iclass 34, count 0 2006.252.07:49:58.21#ibcon#read 4, iclass 34, count 0 2006.252.07:49:58.21#ibcon#about to read 5, iclass 34, count 0 2006.252.07:49:58.21#ibcon#read 5, iclass 34, count 0 2006.252.07:49:58.21#ibcon#about to read 6, iclass 34, count 0 2006.252.07:49:58.21#ibcon#read 6, iclass 34, count 0 2006.252.07:49:58.21#ibcon#end of sib2, iclass 34, count 0 2006.252.07:49:58.21#ibcon#*mode == 0, iclass 34, count 0 2006.252.07:49:58.21#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.252.07:49:58.21#ibcon#[25=USB\r\n] 2006.252.07:49:58.21#ibcon#*before write, iclass 34, count 0 2006.252.07:49:58.21#ibcon#enter sib2, iclass 34, count 0 2006.252.07:49:58.21#ibcon#flushed, iclass 34, count 0 2006.252.07:49:58.21#ibcon#about to write, iclass 34, count 0 2006.252.07:49:58.21#ibcon#wrote, iclass 34, count 0 2006.252.07:49:58.21#ibcon#about to read 3, iclass 34, count 0 2006.252.07:49:58.24#ibcon#read 3, iclass 34, count 0 2006.252.07:49:58.24#ibcon#about to read 4, iclass 34, count 0 2006.252.07:49:58.24#ibcon#read 4, iclass 34, count 0 2006.252.07:49:58.24#ibcon#about to read 5, iclass 34, count 0 2006.252.07:49:58.24#ibcon#read 5, iclass 34, count 0 2006.252.07:49:58.24#ibcon#about to read 6, iclass 34, count 0 2006.252.07:49:58.24#ibcon#read 6, iclass 34, count 0 2006.252.07:49:58.24#ibcon#end of sib2, iclass 34, count 0 2006.252.07:49:58.24#ibcon#*after write, iclass 34, count 0 2006.252.07:49:58.24#ibcon#*before return 0, iclass 34, count 0 2006.252.07:49:58.24#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.252.07:49:58.24#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.252.07:49:58.24#ibcon#about to clear, iclass 34 cls_cnt 0 2006.252.07:49:58.24#ibcon#cleared, iclass 34 cls_cnt 0 2006.252.07:49:58.24$vc4f8/valo=2,572.99 2006.252.07:49:58.24#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.252.07:49:58.24#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.252.07:49:58.24#ibcon#ireg 17 cls_cnt 0 2006.252.07:49:58.24#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.252.07:49:58.24#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.252.07:49:58.24#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.252.07:49:58.24#ibcon#enter wrdev, iclass 36, count 0 2006.252.07:49:58.24#ibcon#first serial, iclass 36, count 0 2006.252.07:49:58.24#ibcon#enter sib2, iclass 36, count 0 2006.252.07:49:58.24#ibcon#flushed, iclass 36, count 0 2006.252.07:49:58.24#ibcon#about to write, iclass 36, count 0 2006.252.07:49:58.24#ibcon#wrote, iclass 36, count 0 2006.252.07:49:58.24#ibcon#about to read 3, iclass 36, count 0 2006.252.07:49:58.26#ibcon#read 3, iclass 36, count 0 2006.252.07:49:58.26#ibcon#about to read 4, iclass 36, count 0 2006.252.07:49:58.26#ibcon#read 4, iclass 36, count 0 2006.252.07:49:58.26#ibcon#about to read 5, iclass 36, count 0 2006.252.07:49:58.26#ibcon#read 5, iclass 36, count 0 2006.252.07:49:58.26#ibcon#about to read 6, iclass 36, count 0 2006.252.07:49:58.26#ibcon#read 6, iclass 36, count 0 2006.252.07:49:58.26#ibcon#end of sib2, iclass 36, count 0 2006.252.07:49:58.26#ibcon#*mode == 0, iclass 36, count 0 2006.252.07:49:58.26#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.252.07:49:58.26#ibcon#[26=FRQ=02,572.99\r\n] 2006.252.07:49:58.26#ibcon#*before write, iclass 36, count 0 2006.252.07:49:58.26#ibcon#enter sib2, iclass 36, count 0 2006.252.07:49:58.26#ibcon#flushed, iclass 36, count 0 2006.252.07:49:58.26#ibcon#about to write, iclass 36, count 0 2006.252.07:49:58.26#ibcon#wrote, iclass 36, count 0 2006.252.07:49:58.26#ibcon#about to read 3, iclass 36, count 0 2006.252.07:49:58.30#ibcon#read 3, iclass 36, count 0 2006.252.07:49:58.30#ibcon#about to read 4, iclass 36, count 0 2006.252.07:49:58.30#ibcon#read 4, iclass 36, count 0 2006.252.07:49:58.30#ibcon#about to read 5, iclass 36, count 0 2006.252.07:49:58.30#ibcon#read 5, iclass 36, count 0 2006.252.07:49:58.30#ibcon#about to read 6, iclass 36, count 0 2006.252.07:49:58.30#ibcon#read 6, iclass 36, count 0 2006.252.07:49:58.30#ibcon#end of sib2, iclass 36, count 0 2006.252.07:49:58.30#ibcon#*after write, iclass 36, count 0 2006.252.07:49:58.30#ibcon#*before return 0, iclass 36, count 0 2006.252.07:49:58.30#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.252.07:49:58.30#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.252.07:49:58.30#ibcon#about to clear, iclass 36 cls_cnt 0 2006.252.07:49:58.30#ibcon#cleared, iclass 36 cls_cnt 0 2006.252.07:49:58.30$vc4f8/va=2,7 2006.252.07:49:58.30#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.252.07:49:58.30#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.252.07:49:58.30#ibcon#ireg 11 cls_cnt 2 2006.252.07:49:58.30#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.252.07:49:58.37#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.252.07:49:58.37#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.252.07:49:58.37#ibcon#enter wrdev, iclass 38, count 2 2006.252.07:49:58.37#ibcon#first serial, iclass 38, count 2 2006.252.07:49:58.37#ibcon#enter sib2, iclass 38, count 2 2006.252.07:49:58.37#ibcon#flushed, iclass 38, count 2 2006.252.07:49:58.37#ibcon#about to write, iclass 38, count 2 2006.252.07:49:58.37#ibcon#wrote, iclass 38, count 2 2006.252.07:49:58.37#ibcon#about to read 3, iclass 38, count 2 2006.252.07:49:58.38#ibcon#read 3, iclass 38, count 2 2006.252.07:49:58.38#ibcon#about to read 4, iclass 38, count 2 2006.252.07:49:58.38#ibcon#read 4, iclass 38, count 2 2006.252.07:49:58.38#ibcon#about to read 5, iclass 38, count 2 2006.252.07:49:58.38#ibcon#read 5, iclass 38, count 2 2006.252.07:49:58.38#ibcon#about to read 6, iclass 38, count 2 2006.252.07:49:58.38#ibcon#read 6, iclass 38, count 2 2006.252.07:49:58.38#ibcon#end of sib2, iclass 38, count 2 2006.252.07:49:58.38#ibcon#*mode == 0, iclass 38, count 2 2006.252.07:49:58.38#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.252.07:49:58.38#ibcon#[25=AT02-07\r\n] 2006.252.07:49:58.38#ibcon#*before write, iclass 38, count 2 2006.252.07:49:58.38#ibcon#enter sib2, iclass 38, count 2 2006.252.07:49:58.38#ibcon#flushed, iclass 38, count 2 2006.252.07:49:58.38#ibcon#about to write, iclass 38, count 2 2006.252.07:49:58.38#ibcon#wrote, iclass 38, count 2 2006.252.07:49:58.38#ibcon#about to read 3, iclass 38, count 2 2006.252.07:49:58.41#ibcon#read 3, iclass 38, count 2 2006.252.07:49:58.41#ibcon#about to read 4, iclass 38, count 2 2006.252.07:49:58.41#ibcon#read 4, iclass 38, count 2 2006.252.07:49:58.41#ibcon#about to read 5, iclass 38, count 2 2006.252.07:49:58.41#ibcon#read 5, iclass 38, count 2 2006.252.07:49:58.41#ibcon#about to read 6, iclass 38, count 2 2006.252.07:49:58.41#ibcon#read 6, iclass 38, count 2 2006.252.07:49:58.41#ibcon#end of sib2, iclass 38, count 2 2006.252.07:49:58.41#ibcon#*after write, iclass 38, count 2 2006.252.07:49:58.41#ibcon#*before return 0, iclass 38, count 2 2006.252.07:49:58.41#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.252.07:49:58.41#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.252.07:49:58.41#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.252.07:49:58.41#ibcon#ireg 7 cls_cnt 0 2006.252.07:49:58.41#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.252.07:49:58.53#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.252.07:49:58.53#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.252.07:49:58.53#ibcon#enter wrdev, iclass 38, count 0 2006.252.07:49:58.53#ibcon#first serial, iclass 38, count 0 2006.252.07:49:58.53#ibcon#enter sib2, iclass 38, count 0 2006.252.07:49:58.53#ibcon#flushed, iclass 38, count 0 2006.252.07:49:58.53#ibcon#about to write, iclass 38, count 0 2006.252.07:49:58.53#ibcon#wrote, iclass 38, count 0 2006.252.07:49:58.53#ibcon#about to read 3, iclass 38, count 0 2006.252.07:49:58.55#ibcon#read 3, iclass 38, count 0 2006.252.07:49:58.55#ibcon#about to read 4, iclass 38, count 0 2006.252.07:49:58.55#ibcon#read 4, iclass 38, count 0 2006.252.07:49:58.55#ibcon#about to read 5, iclass 38, count 0 2006.252.07:49:58.55#ibcon#read 5, iclass 38, count 0 2006.252.07:49:58.55#ibcon#about to read 6, iclass 38, count 0 2006.252.07:49:58.55#ibcon#read 6, iclass 38, count 0 2006.252.07:49:58.55#ibcon#end of sib2, iclass 38, count 0 2006.252.07:49:58.55#ibcon#*mode == 0, iclass 38, count 0 2006.252.07:49:58.55#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.252.07:49:58.55#ibcon#[25=USB\r\n] 2006.252.07:49:58.55#ibcon#*before write, iclass 38, count 0 2006.252.07:49:58.55#ibcon#enter sib2, iclass 38, count 0 2006.252.07:49:58.55#ibcon#flushed, iclass 38, count 0 2006.252.07:49:58.55#ibcon#about to write, iclass 38, count 0 2006.252.07:49:58.55#ibcon#wrote, iclass 38, count 0 2006.252.07:49:58.55#ibcon#about to read 3, iclass 38, count 0 2006.252.07:49:58.58#ibcon#read 3, iclass 38, count 0 2006.252.07:49:58.58#ibcon#about to read 4, iclass 38, count 0 2006.252.07:49:58.58#ibcon#read 4, iclass 38, count 0 2006.252.07:49:58.58#ibcon#about to read 5, iclass 38, count 0 2006.252.07:49:58.58#ibcon#read 5, iclass 38, count 0 2006.252.07:49:58.58#ibcon#about to read 6, iclass 38, count 0 2006.252.07:49:58.58#ibcon#read 6, iclass 38, count 0 2006.252.07:49:58.58#ibcon#end of sib2, iclass 38, count 0 2006.252.07:49:58.58#ibcon#*after write, iclass 38, count 0 2006.252.07:49:58.58#ibcon#*before return 0, iclass 38, count 0 2006.252.07:49:58.58#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.252.07:49:58.58#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.252.07:49:58.58#ibcon#about to clear, iclass 38 cls_cnt 0 2006.252.07:49:58.58#ibcon#cleared, iclass 38 cls_cnt 0 2006.252.07:49:58.58$vc4f8/valo=3,672.99 2006.252.07:49:58.58#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.252.07:49:58.58#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.252.07:49:58.58#ibcon#ireg 17 cls_cnt 0 2006.252.07:49:58.58#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.252.07:49:58.58#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.252.07:49:58.58#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.252.07:49:58.58#ibcon#enter wrdev, iclass 40, count 0 2006.252.07:49:58.58#ibcon#first serial, iclass 40, count 0 2006.252.07:49:58.58#ibcon#enter sib2, iclass 40, count 0 2006.252.07:49:58.58#ibcon#flushed, iclass 40, count 0 2006.252.07:49:58.58#ibcon#about to write, iclass 40, count 0 2006.252.07:49:58.58#ibcon#wrote, iclass 40, count 0 2006.252.07:49:58.58#ibcon#about to read 3, iclass 40, count 0 2006.252.07:49:58.60#ibcon#read 3, iclass 40, count 0 2006.252.07:49:58.60#ibcon#about to read 4, iclass 40, count 0 2006.252.07:49:58.60#ibcon#read 4, iclass 40, count 0 2006.252.07:49:58.60#ibcon#about to read 5, iclass 40, count 0 2006.252.07:49:58.60#ibcon#read 5, iclass 40, count 0 2006.252.07:49:58.60#ibcon#about to read 6, iclass 40, count 0 2006.252.07:49:58.60#ibcon#read 6, iclass 40, count 0 2006.252.07:49:58.60#ibcon#end of sib2, iclass 40, count 0 2006.252.07:49:58.60#ibcon#*mode == 0, iclass 40, count 0 2006.252.07:49:58.60#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.252.07:49:58.60#ibcon#[26=FRQ=03,672.99\r\n] 2006.252.07:49:58.60#ibcon#*before write, iclass 40, count 0 2006.252.07:49:58.60#ibcon#enter sib2, iclass 40, count 0 2006.252.07:49:58.60#ibcon#flushed, iclass 40, count 0 2006.252.07:49:58.60#ibcon#about to write, iclass 40, count 0 2006.252.07:49:58.60#ibcon#wrote, iclass 40, count 0 2006.252.07:49:58.60#ibcon#about to read 3, iclass 40, count 0 2006.252.07:49:58.64#ibcon#read 3, iclass 40, count 0 2006.252.07:49:58.64#ibcon#about to read 4, iclass 40, count 0 2006.252.07:49:58.64#ibcon#read 4, iclass 40, count 0 2006.252.07:49:58.64#ibcon#about to read 5, iclass 40, count 0 2006.252.07:49:58.64#ibcon#read 5, iclass 40, count 0 2006.252.07:49:58.64#ibcon#about to read 6, iclass 40, count 0 2006.252.07:49:58.64#ibcon#read 6, iclass 40, count 0 2006.252.07:49:58.64#ibcon#end of sib2, iclass 40, count 0 2006.252.07:49:58.64#ibcon#*after write, iclass 40, count 0 2006.252.07:49:58.64#ibcon#*before return 0, iclass 40, count 0 2006.252.07:49:58.64#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.252.07:49:58.64#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.252.07:49:58.64#ibcon#about to clear, iclass 40 cls_cnt 0 2006.252.07:49:58.64#ibcon#cleared, iclass 40 cls_cnt 0 2006.252.07:49:58.64$vc4f8/va=3,6 2006.252.07:49:58.64#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.252.07:49:58.64#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.252.07:49:58.64#ibcon#ireg 11 cls_cnt 2 2006.252.07:49:58.64#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.252.07:49:58.71#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.252.07:49:58.71#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.252.07:49:58.71#ibcon#enter wrdev, iclass 4, count 2 2006.252.07:49:58.71#ibcon#first serial, iclass 4, count 2 2006.252.07:49:58.71#ibcon#enter sib2, iclass 4, count 2 2006.252.07:49:58.71#ibcon#flushed, iclass 4, count 2 2006.252.07:49:58.71#ibcon#about to write, iclass 4, count 2 2006.252.07:49:58.71#ibcon#wrote, iclass 4, count 2 2006.252.07:49:58.71#ibcon#about to read 3, iclass 4, count 2 2006.252.07:49:58.72#ibcon#read 3, iclass 4, count 2 2006.252.07:49:58.72#ibcon#about to read 4, iclass 4, count 2 2006.252.07:49:58.72#ibcon#read 4, iclass 4, count 2 2006.252.07:49:58.72#ibcon#about to read 5, iclass 4, count 2 2006.252.07:49:58.72#ibcon#read 5, iclass 4, count 2 2006.252.07:49:58.72#ibcon#about to read 6, iclass 4, count 2 2006.252.07:49:58.72#ibcon#read 6, iclass 4, count 2 2006.252.07:49:58.72#ibcon#end of sib2, iclass 4, count 2 2006.252.07:49:58.72#ibcon#*mode == 0, iclass 4, count 2 2006.252.07:49:58.72#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.252.07:49:58.72#ibcon#[25=AT03-06\r\n] 2006.252.07:49:58.72#ibcon#*before write, iclass 4, count 2 2006.252.07:49:58.72#ibcon#enter sib2, iclass 4, count 2 2006.252.07:49:58.72#ibcon#flushed, iclass 4, count 2 2006.252.07:49:58.72#ibcon#about to write, iclass 4, count 2 2006.252.07:49:58.72#ibcon#wrote, iclass 4, count 2 2006.252.07:49:58.72#ibcon#about to read 3, iclass 4, count 2 2006.252.07:49:58.75#ibcon#read 3, iclass 4, count 2 2006.252.07:49:58.75#ibcon#about to read 4, iclass 4, count 2 2006.252.07:49:58.75#ibcon#read 4, iclass 4, count 2 2006.252.07:49:58.75#ibcon#about to read 5, iclass 4, count 2 2006.252.07:49:58.75#ibcon#read 5, iclass 4, count 2 2006.252.07:49:58.75#ibcon#about to read 6, iclass 4, count 2 2006.252.07:49:58.75#ibcon#read 6, iclass 4, count 2 2006.252.07:49:58.75#ibcon#end of sib2, iclass 4, count 2 2006.252.07:49:58.75#ibcon#*after write, iclass 4, count 2 2006.252.07:49:58.75#ibcon#*before return 0, iclass 4, count 2 2006.252.07:49:58.75#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.252.07:49:58.75#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.252.07:49:58.75#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.252.07:49:58.75#ibcon#ireg 7 cls_cnt 0 2006.252.07:49:58.75#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.252.07:49:58.87#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.252.07:49:58.87#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.252.07:49:58.87#ibcon#enter wrdev, iclass 4, count 0 2006.252.07:49:58.87#ibcon#first serial, iclass 4, count 0 2006.252.07:49:58.87#ibcon#enter sib2, iclass 4, count 0 2006.252.07:49:58.87#ibcon#flushed, iclass 4, count 0 2006.252.07:49:58.87#ibcon#about to write, iclass 4, count 0 2006.252.07:49:58.87#ibcon#wrote, iclass 4, count 0 2006.252.07:49:58.87#ibcon#about to read 3, iclass 4, count 0 2006.252.07:49:58.89#ibcon#read 3, iclass 4, count 0 2006.252.07:49:58.89#ibcon#about to read 4, iclass 4, count 0 2006.252.07:49:58.89#ibcon#read 4, iclass 4, count 0 2006.252.07:49:58.89#ibcon#about to read 5, iclass 4, count 0 2006.252.07:49:58.89#ibcon#read 5, iclass 4, count 0 2006.252.07:49:58.89#ibcon#about to read 6, iclass 4, count 0 2006.252.07:49:58.89#ibcon#read 6, iclass 4, count 0 2006.252.07:49:58.89#ibcon#end of sib2, iclass 4, count 0 2006.252.07:49:58.89#ibcon#*mode == 0, iclass 4, count 0 2006.252.07:49:58.89#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.252.07:49:58.89#ibcon#[25=USB\r\n] 2006.252.07:49:58.89#ibcon#*before write, iclass 4, count 0 2006.252.07:49:58.89#ibcon#enter sib2, iclass 4, count 0 2006.252.07:49:58.89#ibcon#flushed, iclass 4, count 0 2006.252.07:49:58.89#ibcon#about to write, iclass 4, count 0 2006.252.07:49:58.89#ibcon#wrote, iclass 4, count 0 2006.252.07:49:58.89#ibcon#about to read 3, iclass 4, count 0 2006.252.07:49:58.92#ibcon#read 3, iclass 4, count 0 2006.252.07:49:58.92#ibcon#about to read 4, iclass 4, count 0 2006.252.07:49:58.92#ibcon#read 4, iclass 4, count 0 2006.252.07:49:58.92#ibcon#about to read 5, iclass 4, count 0 2006.252.07:49:58.92#ibcon#read 5, iclass 4, count 0 2006.252.07:49:58.92#ibcon#about to read 6, iclass 4, count 0 2006.252.07:49:58.92#ibcon#read 6, iclass 4, count 0 2006.252.07:49:58.92#ibcon#end of sib2, iclass 4, count 0 2006.252.07:49:58.92#ibcon#*after write, iclass 4, count 0 2006.252.07:49:58.92#ibcon#*before return 0, iclass 4, count 0 2006.252.07:49:58.92#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.252.07:49:58.92#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.252.07:49:58.92#ibcon#about to clear, iclass 4 cls_cnt 0 2006.252.07:49:58.92#ibcon#cleared, iclass 4 cls_cnt 0 2006.252.07:49:58.92$vc4f8/valo=4,832.99 2006.252.07:49:58.92#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.252.07:49:58.92#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.252.07:49:58.92#ibcon#ireg 17 cls_cnt 0 2006.252.07:49:58.92#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.252.07:49:58.92#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.252.07:49:58.92#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.252.07:49:58.92#ibcon#enter wrdev, iclass 6, count 0 2006.252.07:49:58.92#ibcon#first serial, iclass 6, count 0 2006.252.07:49:58.92#ibcon#enter sib2, iclass 6, count 0 2006.252.07:49:58.92#ibcon#flushed, iclass 6, count 0 2006.252.07:49:58.92#ibcon#about to write, iclass 6, count 0 2006.252.07:49:58.92#ibcon#wrote, iclass 6, count 0 2006.252.07:49:58.92#ibcon#about to read 3, iclass 6, count 0 2006.252.07:49:58.94#ibcon#read 3, iclass 6, count 0 2006.252.07:49:58.94#ibcon#about to read 4, iclass 6, count 0 2006.252.07:49:58.94#ibcon#read 4, iclass 6, count 0 2006.252.07:49:58.94#ibcon#about to read 5, iclass 6, count 0 2006.252.07:49:58.94#ibcon#read 5, iclass 6, count 0 2006.252.07:49:58.94#ibcon#about to read 6, iclass 6, count 0 2006.252.07:49:58.94#ibcon#read 6, iclass 6, count 0 2006.252.07:49:58.94#ibcon#end of sib2, iclass 6, count 0 2006.252.07:49:58.94#ibcon#*mode == 0, iclass 6, count 0 2006.252.07:49:58.94#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.252.07:49:58.94#ibcon#[26=FRQ=04,832.99\r\n] 2006.252.07:49:58.94#ibcon#*before write, iclass 6, count 0 2006.252.07:49:58.94#ibcon#enter sib2, iclass 6, count 0 2006.252.07:49:58.94#ibcon#flushed, iclass 6, count 0 2006.252.07:49:58.94#ibcon#about to write, iclass 6, count 0 2006.252.07:49:58.94#ibcon#wrote, iclass 6, count 0 2006.252.07:49:58.94#ibcon#about to read 3, iclass 6, count 0 2006.252.07:49:58.98#ibcon#read 3, iclass 6, count 0 2006.252.07:49:58.98#ibcon#about to read 4, iclass 6, count 0 2006.252.07:49:58.98#ibcon#read 4, iclass 6, count 0 2006.252.07:49:58.98#ibcon#about to read 5, iclass 6, count 0 2006.252.07:49:58.98#ibcon#read 5, iclass 6, count 0 2006.252.07:49:58.98#ibcon#about to read 6, iclass 6, count 0 2006.252.07:49:58.98#ibcon#read 6, iclass 6, count 0 2006.252.07:49:58.98#ibcon#end of sib2, iclass 6, count 0 2006.252.07:49:58.98#ibcon#*after write, iclass 6, count 0 2006.252.07:49:58.98#ibcon#*before return 0, iclass 6, count 0 2006.252.07:49:58.98#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.252.07:49:58.98#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.252.07:49:58.98#ibcon#about to clear, iclass 6 cls_cnt 0 2006.252.07:49:58.98#ibcon#cleared, iclass 6 cls_cnt 0 2006.252.07:49:58.98$vc4f8/va=4,7 2006.252.07:49:58.98#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.252.07:49:58.98#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.252.07:49:58.98#ibcon#ireg 11 cls_cnt 2 2006.252.07:49:58.98#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.252.07:49:59.05#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.252.07:49:59.05#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.252.07:49:59.05#ibcon#enter wrdev, iclass 10, count 2 2006.252.07:49:59.05#ibcon#first serial, iclass 10, count 2 2006.252.07:49:59.05#ibcon#enter sib2, iclass 10, count 2 2006.252.07:49:59.05#ibcon#flushed, iclass 10, count 2 2006.252.07:49:59.05#ibcon#about to write, iclass 10, count 2 2006.252.07:49:59.05#ibcon#wrote, iclass 10, count 2 2006.252.07:49:59.05#ibcon#about to read 3, iclass 10, count 2 2006.252.07:49:59.06#ibcon#read 3, iclass 10, count 2 2006.252.07:49:59.06#ibcon#about to read 4, iclass 10, count 2 2006.252.07:49:59.06#ibcon#read 4, iclass 10, count 2 2006.252.07:49:59.06#ibcon#about to read 5, iclass 10, count 2 2006.252.07:49:59.06#ibcon#read 5, iclass 10, count 2 2006.252.07:49:59.06#ibcon#about to read 6, iclass 10, count 2 2006.252.07:49:59.06#ibcon#read 6, iclass 10, count 2 2006.252.07:49:59.06#ibcon#end of sib2, iclass 10, count 2 2006.252.07:49:59.06#ibcon#*mode == 0, iclass 10, count 2 2006.252.07:49:59.06#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.252.07:49:59.06#ibcon#[25=AT04-07\r\n] 2006.252.07:49:59.06#ibcon#*before write, iclass 10, count 2 2006.252.07:49:59.06#ibcon#enter sib2, iclass 10, count 2 2006.252.07:49:59.06#ibcon#flushed, iclass 10, count 2 2006.252.07:49:59.06#ibcon#about to write, iclass 10, count 2 2006.252.07:49:59.06#ibcon#wrote, iclass 10, count 2 2006.252.07:49:59.06#ibcon#about to read 3, iclass 10, count 2 2006.252.07:49:59.09#ibcon#read 3, iclass 10, count 2 2006.252.07:49:59.09#ibcon#about to read 4, iclass 10, count 2 2006.252.07:49:59.09#ibcon#read 4, iclass 10, count 2 2006.252.07:49:59.09#ibcon#about to read 5, iclass 10, count 2 2006.252.07:49:59.09#ibcon#read 5, iclass 10, count 2 2006.252.07:49:59.09#ibcon#about to read 6, iclass 10, count 2 2006.252.07:49:59.09#ibcon#read 6, iclass 10, count 2 2006.252.07:49:59.09#ibcon#end of sib2, iclass 10, count 2 2006.252.07:49:59.09#ibcon#*after write, iclass 10, count 2 2006.252.07:49:59.09#ibcon#*before return 0, iclass 10, count 2 2006.252.07:49:59.09#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.252.07:49:59.09#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.252.07:49:59.09#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.252.07:49:59.09#ibcon#ireg 7 cls_cnt 0 2006.252.07:49:59.09#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.252.07:49:59.21#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.252.07:49:59.21#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.252.07:49:59.21#ibcon#enter wrdev, iclass 10, count 0 2006.252.07:49:59.21#ibcon#first serial, iclass 10, count 0 2006.252.07:49:59.21#ibcon#enter sib2, iclass 10, count 0 2006.252.07:49:59.21#ibcon#flushed, iclass 10, count 0 2006.252.07:49:59.21#ibcon#about to write, iclass 10, count 0 2006.252.07:49:59.21#ibcon#wrote, iclass 10, count 0 2006.252.07:49:59.21#ibcon#about to read 3, iclass 10, count 0 2006.252.07:49:59.23#ibcon#read 3, iclass 10, count 0 2006.252.07:49:59.23#ibcon#about to read 4, iclass 10, count 0 2006.252.07:49:59.23#ibcon#read 4, iclass 10, count 0 2006.252.07:49:59.23#ibcon#about to read 5, iclass 10, count 0 2006.252.07:49:59.23#ibcon#read 5, iclass 10, count 0 2006.252.07:49:59.23#ibcon#about to read 6, iclass 10, count 0 2006.252.07:49:59.23#ibcon#read 6, iclass 10, count 0 2006.252.07:49:59.23#ibcon#end of sib2, iclass 10, count 0 2006.252.07:49:59.23#ibcon#*mode == 0, iclass 10, count 0 2006.252.07:49:59.23#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.252.07:49:59.23#ibcon#[25=USB\r\n] 2006.252.07:49:59.23#ibcon#*before write, iclass 10, count 0 2006.252.07:49:59.23#ibcon#enter sib2, iclass 10, count 0 2006.252.07:49:59.23#ibcon#flushed, iclass 10, count 0 2006.252.07:49:59.23#ibcon#about to write, iclass 10, count 0 2006.252.07:49:59.23#ibcon#wrote, iclass 10, count 0 2006.252.07:49:59.23#ibcon#about to read 3, iclass 10, count 0 2006.252.07:49:59.26#ibcon#read 3, iclass 10, count 0 2006.252.07:49:59.26#ibcon#about to read 4, iclass 10, count 0 2006.252.07:49:59.26#ibcon#read 4, iclass 10, count 0 2006.252.07:49:59.26#ibcon#about to read 5, iclass 10, count 0 2006.252.07:49:59.26#ibcon#read 5, iclass 10, count 0 2006.252.07:49:59.26#ibcon#about to read 6, iclass 10, count 0 2006.252.07:49:59.26#ibcon#read 6, iclass 10, count 0 2006.252.07:49:59.26#ibcon#end of sib2, iclass 10, count 0 2006.252.07:49:59.26#ibcon#*after write, iclass 10, count 0 2006.252.07:49:59.26#ibcon#*before return 0, iclass 10, count 0 2006.252.07:49:59.26#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.252.07:49:59.26#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.252.07:49:59.26#ibcon#about to clear, iclass 10 cls_cnt 0 2006.252.07:49:59.26#ibcon#cleared, iclass 10 cls_cnt 0 2006.252.07:49:59.26$vc4f8/valo=5,652.99 2006.252.07:49:59.26#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.252.07:49:59.26#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.252.07:49:59.26#ibcon#ireg 17 cls_cnt 0 2006.252.07:49:59.26#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.252.07:49:59.26#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.252.07:49:59.26#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.252.07:49:59.26#ibcon#enter wrdev, iclass 12, count 0 2006.252.07:49:59.26#ibcon#first serial, iclass 12, count 0 2006.252.07:49:59.26#ibcon#enter sib2, iclass 12, count 0 2006.252.07:49:59.26#ibcon#flushed, iclass 12, count 0 2006.252.07:49:59.26#ibcon#about to write, iclass 12, count 0 2006.252.07:49:59.26#ibcon#wrote, iclass 12, count 0 2006.252.07:49:59.26#ibcon#about to read 3, iclass 12, count 0 2006.252.07:49:59.28#ibcon#read 3, iclass 12, count 0 2006.252.07:49:59.28#ibcon#about to read 4, iclass 12, count 0 2006.252.07:49:59.28#ibcon#read 4, iclass 12, count 0 2006.252.07:49:59.28#ibcon#about to read 5, iclass 12, count 0 2006.252.07:49:59.28#ibcon#read 5, iclass 12, count 0 2006.252.07:49:59.28#ibcon#about to read 6, iclass 12, count 0 2006.252.07:49:59.28#ibcon#read 6, iclass 12, count 0 2006.252.07:49:59.28#ibcon#end of sib2, iclass 12, count 0 2006.252.07:49:59.28#ibcon#*mode == 0, iclass 12, count 0 2006.252.07:49:59.28#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.252.07:49:59.28#ibcon#[26=FRQ=05,652.99\r\n] 2006.252.07:49:59.28#ibcon#*before write, iclass 12, count 0 2006.252.07:49:59.28#ibcon#enter sib2, iclass 12, count 0 2006.252.07:49:59.28#ibcon#flushed, iclass 12, count 0 2006.252.07:49:59.28#ibcon#about to write, iclass 12, count 0 2006.252.07:49:59.28#ibcon#wrote, iclass 12, count 0 2006.252.07:49:59.28#ibcon#about to read 3, iclass 12, count 0 2006.252.07:49:59.32#ibcon#read 3, iclass 12, count 0 2006.252.07:49:59.32#ibcon#about to read 4, iclass 12, count 0 2006.252.07:49:59.32#ibcon#read 4, iclass 12, count 0 2006.252.07:49:59.32#ibcon#about to read 5, iclass 12, count 0 2006.252.07:49:59.32#ibcon#read 5, iclass 12, count 0 2006.252.07:49:59.32#ibcon#about to read 6, iclass 12, count 0 2006.252.07:49:59.32#ibcon#read 6, iclass 12, count 0 2006.252.07:49:59.32#ibcon#end of sib2, iclass 12, count 0 2006.252.07:49:59.32#ibcon#*after write, iclass 12, count 0 2006.252.07:49:59.32#ibcon#*before return 0, iclass 12, count 0 2006.252.07:49:59.32#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.252.07:49:59.32#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.252.07:49:59.32#ibcon#about to clear, iclass 12 cls_cnt 0 2006.252.07:49:59.32#ibcon#cleared, iclass 12 cls_cnt 0 2006.252.07:49:59.32$vc4f8/va=5,7 2006.252.07:49:59.32#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.252.07:49:59.32#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.252.07:49:59.32#ibcon#ireg 11 cls_cnt 2 2006.252.07:49:59.32#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.252.07:49:59.38#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.252.07:49:59.38#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.252.07:49:59.38#ibcon#enter wrdev, iclass 14, count 2 2006.252.07:49:59.38#ibcon#first serial, iclass 14, count 2 2006.252.07:49:59.38#ibcon#enter sib2, iclass 14, count 2 2006.252.07:49:59.38#ibcon#flushed, iclass 14, count 2 2006.252.07:49:59.38#ibcon#about to write, iclass 14, count 2 2006.252.07:49:59.38#ibcon#wrote, iclass 14, count 2 2006.252.07:49:59.38#ibcon#about to read 3, iclass 14, count 2 2006.252.07:49:59.40#ibcon#read 3, iclass 14, count 2 2006.252.07:49:59.40#ibcon#about to read 4, iclass 14, count 2 2006.252.07:49:59.40#ibcon#read 4, iclass 14, count 2 2006.252.07:49:59.40#ibcon#about to read 5, iclass 14, count 2 2006.252.07:49:59.40#ibcon#read 5, iclass 14, count 2 2006.252.07:49:59.40#ibcon#about to read 6, iclass 14, count 2 2006.252.07:49:59.40#ibcon#read 6, iclass 14, count 2 2006.252.07:49:59.40#ibcon#end of sib2, iclass 14, count 2 2006.252.07:49:59.40#ibcon#*mode == 0, iclass 14, count 2 2006.252.07:49:59.40#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.252.07:49:59.40#ibcon#[25=AT05-07\r\n] 2006.252.07:49:59.40#ibcon#*before write, iclass 14, count 2 2006.252.07:49:59.40#ibcon#enter sib2, iclass 14, count 2 2006.252.07:49:59.40#ibcon#flushed, iclass 14, count 2 2006.252.07:49:59.40#ibcon#about to write, iclass 14, count 2 2006.252.07:49:59.40#ibcon#wrote, iclass 14, count 2 2006.252.07:49:59.40#ibcon#about to read 3, iclass 14, count 2 2006.252.07:49:59.43#ibcon#read 3, iclass 14, count 2 2006.252.07:49:59.43#ibcon#about to read 4, iclass 14, count 2 2006.252.07:49:59.43#ibcon#read 4, iclass 14, count 2 2006.252.07:49:59.43#ibcon#about to read 5, iclass 14, count 2 2006.252.07:49:59.43#ibcon#read 5, iclass 14, count 2 2006.252.07:49:59.43#ibcon#about to read 6, iclass 14, count 2 2006.252.07:49:59.43#ibcon#read 6, iclass 14, count 2 2006.252.07:49:59.43#ibcon#end of sib2, iclass 14, count 2 2006.252.07:49:59.43#ibcon#*after write, iclass 14, count 2 2006.252.07:49:59.43#ibcon#*before return 0, iclass 14, count 2 2006.252.07:49:59.43#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.252.07:49:59.43#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.252.07:49:59.43#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.252.07:49:59.43#ibcon#ireg 7 cls_cnt 0 2006.252.07:49:59.43#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.252.07:49:59.55#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.252.07:49:59.55#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.252.07:49:59.55#ibcon#enter wrdev, iclass 14, count 0 2006.252.07:49:59.55#ibcon#first serial, iclass 14, count 0 2006.252.07:49:59.55#ibcon#enter sib2, iclass 14, count 0 2006.252.07:49:59.55#ibcon#flushed, iclass 14, count 0 2006.252.07:49:59.55#ibcon#about to write, iclass 14, count 0 2006.252.07:49:59.55#ibcon#wrote, iclass 14, count 0 2006.252.07:49:59.55#ibcon#about to read 3, iclass 14, count 0 2006.252.07:49:59.57#ibcon#read 3, iclass 14, count 0 2006.252.07:49:59.57#ibcon#about to read 4, iclass 14, count 0 2006.252.07:49:59.57#ibcon#read 4, iclass 14, count 0 2006.252.07:49:59.57#ibcon#about to read 5, iclass 14, count 0 2006.252.07:49:59.57#ibcon#read 5, iclass 14, count 0 2006.252.07:49:59.57#ibcon#about to read 6, iclass 14, count 0 2006.252.07:49:59.57#ibcon#read 6, iclass 14, count 0 2006.252.07:49:59.57#ibcon#end of sib2, iclass 14, count 0 2006.252.07:49:59.57#ibcon#*mode == 0, iclass 14, count 0 2006.252.07:49:59.57#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.252.07:49:59.57#ibcon#[25=USB\r\n] 2006.252.07:49:59.57#ibcon#*before write, iclass 14, count 0 2006.252.07:49:59.57#ibcon#enter sib2, iclass 14, count 0 2006.252.07:49:59.57#ibcon#flushed, iclass 14, count 0 2006.252.07:49:59.57#ibcon#about to write, iclass 14, count 0 2006.252.07:49:59.57#ibcon#wrote, iclass 14, count 0 2006.252.07:49:59.57#ibcon#about to read 3, iclass 14, count 0 2006.252.07:49:59.60#ibcon#read 3, iclass 14, count 0 2006.252.07:49:59.60#ibcon#about to read 4, iclass 14, count 0 2006.252.07:49:59.60#ibcon#read 4, iclass 14, count 0 2006.252.07:49:59.60#ibcon#about to read 5, iclass 14, count 0 2006.252.07:49:59.60#ibcon#read 5, iclass 14, count 0 2006.252.07:49:59.60#ibcon#about to read 6, iclass 14, count 0 2006.252.07:49:59.60#ibcon#read 6, iclass 14, count 0 2006.252.07:49:59.60#ibcon#end of sib2, iclass 14, count 0 2006.252.07:49:59.60#ibcon#*after write, iclass 14, count 0 2006.252.07:49:59.60#ibcon#*before return 0, iclass 14, count 0 2006.252.07:49:59.60#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.252.07:49:59.60#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.252.07:49:59.60#ibcon#about to clear, iclass 14 cls_cnt 0 2006.252.07:49:59.60#ibcon#cleared, iclass 14 cls_cnt 0 2006.252.07:49:59.60$vc4f8/valo=6,772.99 2006.252.07:49:59.60#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.252.07:49:59.60#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.252.07:49:59.60#ibcon#ireg 17 cls_cnt 0 2006.252.07:49:59.60#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.252.07:49:59.60#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.252.07:49:59.60#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.252.07:49:59.60#ibcon#enter wrdev, iclass 16, count 0 2006.252.07:49:59.60#ibcon#first serial, iclass 16, count 0 2006.252.07:49:59.60#ibcon#enter sib2, iclass 16, count 0 2006.252.07:49:59.60#ibcon#flushed, iclass 16, count 0 2006.252.07:49:59.60#ibcon#about to write, iclass 16, count 0 2006.252.07:49:59.60#ibcon#wrote, iclass 16, count 0 2006.252.07:49:59.60#ibcon#about to read 3, iclass 16, count 0 2006.252.07:49:59.62#ibcon#read 3, iclass 16, count 0 2006.252.07:49:59.62#ibcon#about to read 4, iclass 16, count 0 2006.252.07:49:59.62#ibcon#read 4, iclass 16, count 0 2006.252.07:49:59.62#ibcon#about to read 5, iclass 16, count 0 2006.252.07:49:59.62#ibcon#read 5, iclass 16, count 0 2006.252.07:49:59.62#ibcon#about to read 6, iclass 16, count 0 2006.252.07:49:59.62#ibcon#read 6, iclass 16, count 0 2006.252.07:49:59.62#ibcon#end of sib2, iclass 16, count 0 2006.252.07:49:59.62#ibcon#*mode == 0, iclass 16, count 0 2006.252.07:49:59.62#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.252.07:49:59.62#ibcon#[26=FRQ=06,772.99\r\n] 2006.252.07:49:59.62#ibcon#*before write, iclass 16, count 0 2006.252.07:49:59.62#ibcon#enter sib2, iclass 16, count 0 2006.252.07:49:59.62#ibcon#flushed, iclass 16, count 0 2006.252.07:49:59.62#ibcon#about to write, iclass 16, count 0 2006.252.07:49:59.62#ibcon#wrote, iclass 16, count 0 2006.252.07:49:59.62#ibcon#about to read 3, iclass 16, count 0 2006.252.07:49:59.66#ibcon#read 3, iclass 16, count 0 2006.252.07:49:59.66#ibcon#about to read 4, iclass 16, count 0 2006.252.07:49:59.66#ibcon#read 4, iclass 16, count 0 2006.252.07:49:59.66#ibcon#about to read 5, iclass 16, count 0 2006.252.07:49:59.66#ibcon#read 5, iclass 16, count 0 2006.252.07:49:59.66#ibcon#about to read 6, iclass 16, count 0 2006.252.07:49:59.66#ibcon#read 6, iclass 16, count 0 2006.252.07:49:59.66#ibcon#end of sib2, iclass 16, count 0 2006.252.07:49:59.66#ibcon#*after write, iclass 16, count 0 2006.252.07:49:59.66#ibcon#*before return 0, iclass 16, count 0 2006.252.07:49:59.66#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.252.07:49:59.66#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.252.07:49:59.66#ibcon#about to clear, iclass 16 cls_cnt 0 2006.252.07:49:59.66#ibcon#cleared, iclass 16 cls_cnt 0 2006.252.07:49:59.66$vc4f8/va=6,7 2006.252.07:49:59.66#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.252.07:49:59.66#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.252.07:49:59.66#ibcon#ireg 11 cls_cnt 2 2006.252.07:49:59.66#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.252.07:49:59.73#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.252.07:49:59.73#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.252.07:49:59.73#ibcon#enter wrdev, iclass 18, count 2 2006.252.07:49:59.73#ibcon#first serial, iclass 18, count 2 2006.252.07:49:59.73#ibcon#enter sib2, iclass 18, count 2 2006.252.07:49:59.73#ibcon#flushed, iclass 18, count 2 2006.252.07:49:59.73#ibcon#about to write, iclass 18, count 2 2006.252.07:49:59.73#ibcon#wrote, iclass 18, count 2 2006.252.07:49:59.73#ibcon#about to read 3, iclass 18, count 2 2006.252.07:49:59.74#ibcon#read 3, iclass 18, count 2 2006.252.07:49:59.74#ibcon#about to read 4, iclass 18, count 2 2006.252.07:49:59.74#ibcon#read 4, iclass 18, count 2 2006.252.07:49:59.74#ibcon#about to read 5, iclass 18, count 2 2006.252.07:49:59.74#ibcon#read 5, iclass 18, count 2 2006.252.07:49:59.74#ibcon#about to read 6, iclass 18, count 2 2006.252.07:49:59.74#ibcon#read 6, iclass 18, count 2 2006.252.07:49:59.74#ibcon#end of sib2, iclass 18, count 2 2006.252.07:49:59.74#ibcon#*mode == 0, iclass 18, count 2 2006.252.07:49:59.74#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.252.07:49:59.74#ibcon#[25=AT06-07\r\n] 2006.252.07:49:59.74#ibcon#*before write, iclass 18, count 2 2006.252.07:49:59.74#ibcon#enter sib2, iclass 18, count 2 2006.252.07:49:59.74#ibcon#flushed, iclass 18, count 2 2006.252.07:49:59.74#ibcon#about to write, iclass 18, count 2 2006.252.07:49:59.74#ibcon#wrote, iclass 18, count 2 2006.252.07:49:59.74#ibcon#about to read 3, iclass 18, count 2 2006.252.07:49:59.77#ibcon#read 3, iclass 18, count 2 2006.252.07:49:59.77#ibcon#about to read 4, iclass 18, count 2 2006.252.07:49:59.77#ibcon#read 4, iclass 18, count 2 2006.252.07:49:59.77#ibcon#about to read 5, iclass 18, count 2 2006.252.07:49:59.77#ibcon#read 5, iclass 18, count 2 2006.252.07:49:59.77#ibcon#about to read 6, iclass 18, count 2 2006.252.07:49:59.77#ibcon#read 6, iclass 18, count 2 2006.252.07:49:59.77#ibcon#end of sib2, iclass 18, count 2 2006.252.07:49:59.77#ibcon#*after write, iclass 18, count 2 2006.252.07:49:59.77#ibcon#*before return 0, iclass 18, count 2 2006.252.07:49:59.77#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.252.07:49:59.77#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.252.07:49:59.77#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.252.07:49:59.77#ibcon#ireg 7 cls_cnt 0 2006.252.07:49:59.77#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.252.07:49:59.89#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.252.07:49:59.89#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.252.07:49:59.89#ibcon#enter wrdev, iclass 18, count 0 2006.252.07:49:59.89#ibcon#first serial, iclass 18, count 0 2006.252.07:49:59.89#ibcon#enter sib2, iclass 18, count 0 2006.252.07:49:59.89#ibcon#flushed, iclass 18, count 0 2006.252.07:49:59.89#ibcon#about to write, iclass 18, count 0 2006.252.07:49:59.89#ibcon#wrote, iclass 18, count 0 2006.252.07:49:59.89#ibcon#about to read 3, iclass 18, count 0 2006.252.07:49:59.91#ibcon#read 3, iclass 18, count 0 2006.252.07:49:59.91#ibcon#about to read 4, iclass 18, count 0 2006.252.07:49:59.91#ibcon#read 4, iclass 18, count 0 2006.252.07:49:59.91#ibcon#about to read 5, iclass 18, count 0 2006.252.07:49:59.91#ibcon#read 5, iclass 18, count 0 2006.252.07:49:59.91#ibcon#about to read 6, iclass 18, count 0 2006.252.07:49:59.91#ibcon#read 6, iclass 18, count 0 2006.252.07:49:59.91#ibcon#end of sib2, iclass 18, count 0 2006.252.07:49:59.91#ibcon#*mode == 0, iclass 18, count 0 2006.252.07:49:59.91#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.252.07:49:59.91#ibcon#[25=USB\r\n] 2006.252.07:49:59.91#ibcon#*before write, iclass 18, count 0 2006.252.07:49:59.91#ibcon#enter sib2, iclass 18, count 0 2006.252.07:49:59.91#ibcon#flushed, iclass 18, count 0 2006.252.07:49:59.91#ibcon#about to write, iclass 18, count 0 2006.252.07:49:59.91#ibcon#wrote, iclass 18, count 0 2006.252.07:49:59.91#ibcon#about to read 3, iclass 18, count 0 2006.252.07:49:59.94#ibcon#read 3, iclass 18, count 0 2006.252.07:49:59.94#ibcon#about to read 4, iclass 18, count 0 2006.252.07:49:59.94#ibcon#read 4, iclass 18, count 0 2006.252.07:49:59.94#ibcon#about to read 5, iclass 18, count 0 2006.252.07:49:59.94#ibcon#read 5, iclass 18, count 0 2006.252.07:49:59.94#ibcon#about to read 6, iclass 18, count 0 2006.252.07:49:59.94#ibcon#read 6, iclass 18, count 0 2006.252.07:49:59.94#ibcon#end of sib2, iclass 18, count 0 2006.252.07:49:59.94#ibcon#*after write, iclass 18, count 0 2006.252.07:49:59.94#ibcon#*before return 0, iclass 18, count 0 2006.252.07:49:59.94#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.252.07:49:59.94#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.252.07:49:59.94#ibcon#about to clear, iclass 18 cls_cnt 0 2006.252.07:49:59.94#ibcon#cleared, iclass 18 cls_cnt 0 2006.252.07:49:59.94$vc4f8/valo=7,832.99 2006.252.07:49:59.94#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.252.07:49:59.94#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.252.07:49:59.94#ibcon#ireg 17 cls_cnt 0 2006.252.07:49:59.94#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.252.07:49:59.94#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.252.07:49:59.94#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.252.07:49:59.94#ibcon#enter wrdev, iclass 20, count 0 2006.252.07:49:59.94#ibcon#first serial, iclass 20, count 0 2006.252.07:49:59.94#ibcon#enter sib2, iclass 20, count 0 2006.252.07:49:59.94#ibcon#flushed, iclass 20, count 0 2006.252.07:49:59.94#ibcon#about to write, iclass 20, count 0 2006.252.07:49:59.94#ibcon#wrote, iclass 20, count 0 2006.252.07:49:59.94#ibcon#about to read 3, iclass 20, count 0 2006.252.07:49:59.96#ibcon#read 3, iclass 20, count 0 2006.252.07:49:59.96#ibcon#about to read 4, iclass 20, count 0 2006.252.07:49:59.96#ibcon#read 4, iclass 20, count 0 2006.252.07:49:59.96#ibcon#about to read 5, iclass 20, count 0 2006.252.07:49:59.96#ibcon#read 5, iclass 20, count 0 2006.252.07:49:59.96#ibcon#about to read 6, iclass 20, count 0 2006.252.07:49:59.96#ibcon#read 6, iclass 20, count 0 2006.252.07:49:59.96#ibcon#end of sib2, iclass 20, count 0 2006.252.07:49:59.96#ibcon#*mode == 0, iclass 20, count 0 2006.252.07:49:59.96#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.252.07:49:59.96#ibcon#[26=FRQ=07,832.99\r\n] 2006.252.07:49:59.96#ibcon#*before write, iclass 20, count 0 2006.252.07:49:59.96#ibcon#enter sib2, iclass 20, count 0 2006.252.07:49:59.96#ibcon#flushed, iclass 20, count 0 2006.252.07:49:59.96#ibcon#about to write, iclass 20, count 0 2006.252.07:49:59.96#ibcon#wrote, iclass 20, count 0 2006.252.07:49:59.96#ibcon#about to read 3, iclass 20, count 0 2006.252.07:50:00.00#ibcon#read 3, iclass 20, count 0 2006.252.07:50:00.00#ibcon#about to read 4, iclass 20, count 0 2006.252.07:50:00.00#ibcon#read 4, iclass 20, count 0 2006.252.07:50:00.00#ibcon#about to read 5, iclass 20, count 0 2006.252.07:50:00.00#ibcon#read 5, iclass 20, count 0 2006.252.07:50:00.00#ibcon#about to read 6, iclass 20, count 0 2006.252.07:50:00.00#ibcon#read 6, iclass 20, count 0 2006.252.07:50:00.00#ibcon#end of sib2, iclass 20, count 0 2006.252.07:50:00.00#ibcon#*after write, iclass 20, count 0 2006.252.07:50:00.00#ibcon#*before return 0, iclass 20, count 0 2006.252.07:50:00.00#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.252.07:50:00.00#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.252.07:50:00.00#ibcon#about to clear, iclass 20 cls_cnt 0 2006.252.07:50:00.00#ibcon#cleared, iclass 20 cls_cnt 0 2006.252.07:50:00.00$vc4f8/va=7,7 2006.252.07:50:00.00#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.252.07:50:00.00#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.252.07:50:00.00#ibcon#ireg 11 cls_cnt 2 2006.252.07:50:00.00#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.252.07:50:00.06#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.252.07:50:00.06#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.252.07:50:00.06#ibcon#enter wrdev, iclass 22, count 2 2006.252.07:50:00.06#ibcon#first serial, iclass 22, count 2 2006.252.07:50:00.06#ibcon#enter sib2, iclass 22, count 2 2006.252.07:50:00.06#ibcon#flushed, iclass 22, count 2 2006.252.07:50:00.06#ibcon#about to write, iclass 22, count 2 2006.252.07:50:00.06#ibcon#wrote, iclass 22, count 2 2006.252.07:50:00.06#ibcon#about to read 3, iclass 22, count 2 2006.252.07:50:00.08#ibcon#read 3, iclass 22, count 2 2006.252.07:50:00.08#ibcon#about to read 4, iclass 22, count 2 2006.252.07:50:00.08#ibcon#read 4, iclass 22, count 2 2006.252.07:50:00.08#ibcon#about to read 5, iclass 22, count 2 2006.252.07:50:00.08#ibcon#read 5, iclass 22, count 2 2006.252.07:50:00.08#ibcon#about to read 6, iclass 22, count 2 2006.252.07:50:00.08#ibcon#read 6, iclass 22, count 2 2006.252.07:50:00.08#ibcon#end of sib2, iclass 22, count 2 2006.252.07:50:00.08#ibcon#*mode == 0, iclass 22, count 2 2006.252.07:50:00.08#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.252.07:50:00.08#ibcon#[25=AT07-07\r\n] 2006.252.07:50:00.08#ibcon#*before write, iclass 22, count 2 2006.252.07:50:00.08#ibcon#enter sib2, iclass 22, count 2 2006.252.07:50:00.08#ibcon#flushed, iclass 22, count 2 2006.252.07:50:00.08#ibcon#about to write, iclass 22, count 2 2006.252.07:50:00.08#ibcon#wrote, iclass 22, count 2 2006.252.07:50:00.08#ibcon#about to read 3, iclass 22, count 2 2006.252.07:50:00.11#ibcon#read 3, iclass 22, count 2 2006.252.07:50:00.11#ibcon#about to read 4, iclass 22, count 2 2006.252.07:50:00.11#ibcon#read 4, iclass 22, count 2 2006.252.07:50:00.11#ibcon#about to read 5, iclass 22, count 2 2006.252.07:50:00.11#ibcon#read 5, iclass 22, count 2 2006.252.07:50:00.11#ibcon#about to read 6, iclass 22, count 2 2006.252.07:50:00.11#ibcon#read 6, iclass 22, count 2 2006.252.07:50:00.11#ibcon#end of sib2, iclass 22, count 2 2006.252.07:50:00.11#ibcon#*after write, iclass 22, count 2 2006.252.07:50:00.11#ibcon#*before return 0, iclass 22, count 2 2006.252.07:50:00.11#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.252.07:50:00.11#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.252.07:50:00.11#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.252.07:50:00.11#ibcon#ireg 7 cls_cnt 0 2006.252.07:50:00.11#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.252.07:50:00.23#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.252.07:50:00.23#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.252.07:50:00.23#ibcon#enter wrdev, iclass 22, count 0 2006.252.07:50:00.23#ibcon#first serial, iclass 22, count 0 2006.252.07:50:00.23#ibcon#enter sib2, iclass 22, count 0 2006.252.07:50:00.23#ibcon#flushed, iclass 22, count 0 2006.252.07:50:00.23#ibcon#about to write, iclass 22, count 0 2006.252.07:50:00.23#ibcon#wrote, iclass 22, count 0 2006.252.07:50:00.23#ibcon#about to read 3, iclass 22, count 0 2006.252.07:50:00.25#ibcon#read 3, iclass 22, count 0 2006.252.07:50:00.25#ibcon#about to read 4, iclass 22, count 0 2006.252.07:50:00.25#ibcon#read 4, iclass 22, count 0 2006.252.07:50:00.25#ibcon#about to read 5, iclass 22, count 0 2006.252.07:50:00.25#ibcon#read 5, iclass 22, count 0 2006.252.07:50:00.25#ibcon#about to read 6, iclass 22, count 0 2006.252.07:50:00.25#ibcon#read 6, iclass 22, count 0 2006.252.07:50:00.25#ibcon#end of sib2, iclass 22, count 0 2006.252.07:50:00.25#ibcon#*mode == 0, iclass 22, count 0 2006.252.07:50:00.25#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.252.07:50:00.25#ibcon#[25=USB\r\n] 2006.252.07:50:00.25#ibcon#*before write, iclass 22, count 0 2006.252.07:50:00.25#ibcon#enter sib2, iclass 22, count 0 2006.252.07:50:00.25#ibcon#flushed, iclass 22, count 0 2006.252.07:50:00.25#ibcon#about to write, iclass 22, count 0 2006.252.07:50:00.25#ibcon#wrote, iclass 22, count 0 2006.252.07:50:00.25#ibcon#about to read 3, iclass 22, count 0 2006.252.07:50:00.28#ibcon#read 3, iclass 22, count 0 2006.252.07:50:00.28#ibcon#about to read 4, iclass 22, count 0 2006.252.07:50:00.28#ibcon#read 4, iclass 22, count 0 2006.252.07:50:00.28#ibcon#about to read 5, iclass 22, count 0 2006.252.07:50:00.28#ibcon#read 5, iclass 22, count 0 2006.252.07:50:00.28#ibcon#about to read 6, iclass 22, count 0 2006.252.07:50:00.28#ibcon#read 6, iclass 22, count 0 2006.252.07:50:00.28#ibcon#end of sib2, iclass 22, count 0 2006.252.07:50:00.28#ibcon#*after write, iclass 22, count 0 2006.252.07:50:00.28#ibcon#*before return 0, iclass 22, count 0 2006.252.07:50:00.28#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.252.07:50:00.28#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.252.07:50:00.28#ibcon#about to clear, iclass 22 cls_cnt 0 2006.252.07:50:00.28#ibcon#cleared, iclass 22 cls_cnt 0 2006.252.07:50:00.28$vc4f8/valo=8,852.99 2006.252.07:50:00.28#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.252.07:50:00.28#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.252.07:50:00.28#ibcon#ireg 17 cls_cnt 0 2006.252.07:50:00.28#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.252.07:50:00.28#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.252.07:50:00.28#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.252.07:50:00.28#ibcon#enter wrdev, iclass 24, count 0 2006.252.07:50:00.28#ibcon#first serial, iclass 24, count 0 2006.252.07:50:00.28#ibcon#enter sib2, iclass 24, count 0 2006.252.07:50:00.28#ibcon#flushed, iclass 24, count 0 2006.252.07:50:00.28#ibcon#about to write, iclass 24, count 0 2006.252.07:50:00.28#ibcon#wrote, iclass 24, count 0 2006.252.07:50:00.28#ibcon#about to read 3, iclass 24, count 0 2006.252.07:50:00.30#ibcon#read 3, iclass 24, count 0 2006.252.07:50:00.30#ibcon#about to read 4, iclass 24, count 0 2006.252.07:50:00.30#ibcon#read 4, iclass 24, count 0 2006.252.07:50:00.30#ibcon#about to read 5, iclass 24, count 0 2006.252.07:50:00.30#ibcon#read 5, iclass 24, count 0 2006.252.07:50:00.30#ibcon#about to read 6, iclass 24, count 0 2006.252.07:50:00.30#ibcon#read 6, iclass 24, count 0 2006.252.07:50:00.30#ibcon#end of sib2, iclass 24, count 0 2006.252.07:50:00.30#ibcon#*mode == 0, iclass 24, count 0 2006.252.07:50:00.30#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.252.07:50:00.30#ibcon#[26=FRQ=08,852.99\r\n] 2006.252.07:50:00.30#ibcon#*before write, iclass 24, count 0 2006.252.07:50:00.30#ibcon#enter sib2, iclass 24, count 0 2006.252.07:50:00.30#ibcon#flushed, iclass 24, count 0 2006.252.07:50:00.30#ibcon#about to write, iclass 24, count 0 2006.252.07:50:00.30#ibcon#wrote, iclass 24, count 0 2006.252.07:50:00.30#ibcon#about to read 3, iclass 24, count 0 2006.252.07:50:00.34#ibcon#read 3, iclass 24, count 0 2006.252.07:50:00.34#ibcon#about to read 4, iclass 24, count 0 2006.252.07:50:00.34#ibcon#read 4, iclass 24, count 0 2006.252.07:50:00.34#ibcon#about to read 5, iclass 24, count 0 2006.252.07:50:00.34#ibcon#read 5, iclass 24, count 0 2006.252.07:50:00.34#ibcon#about to read 6, iclass 24, count 0 2006.252.07:50:00.34#ibcon#read 6, iclass 24, count 0 2006.252.07:50:00.34#ibcon#end of sib2, iclass 24, count 0 2006.252.07:50:00.34#ibcon#*after write, iclass 24, count 0 2006.252.07:50:00.34#ibcon#*before return 0, iclass 24, count 0 2006.252.07:50:00.34#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.252.07:50:00.34#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.252.07:50:00.34#ibcon#about to clear, iclass 24 cls_cnt 0 2006.252.07:50:00.34#ibcon#cleared, iclass 24 cls_cnt 0 2006.252.07:50:00.34$vc4f8/va=8,7 2006.252.07:50:00.34#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.252.07:50:00.34#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.252.07:50:00.34#ibcon#ireg 11 cls_cnt 2 2006.252.07:50:00.34#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.252.07:50:00.40#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.252.07:50:00.40#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.252.07:50:00.40#ibcon#enter wrdev, iclass 26, count 2 2006.252.07:50:00.40#ibcon#first serial, iclass 26, count 2 2006.252.07:50:00.40#ibcon#enter sib2, iclass 26, count 2 2006.252.07:50:00.40#ibcon#flushed, iclass 26, count 2 2006.252.07:50:00.40#ibcon#about to write, iclass 26, count 2 2006.252.07:50:00.40#ibcon#wrote, iclass 26, count 2 2006.252.07:50:00.40#ibcon#about to read 3, iclass 26, count 2 2006.252.07:50:00.42#ibcon#read 3, iclass 26, count 2 2006.252.07:50:00.42#ibcon#about to read 4, iclass 26, count 2 2006.252.07:50:00.42#ibcon#read 4, iclass 26, count 2 2006.252.07:50:00.42#ibcon#about to read 5, iclass 26, count 2 2006.252.07:50:00.42#ibcon#read 5, iclass 26, count 2 2006.252.07:50:00.42#ibcon#about to read 6, iclass 26, count 2 2006.252.07:50:00.42#ibcon#read 6, iclass 26, count 2 2006.252.07:50:00.42#ibcon#end of sib2, iclass 26, count 2 2006.252.07:50:00.42#ibcon#*mode == 0, iclass 26, count 2 2006.252.07:50:00.42#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.252.07:50:00.42#ibcon#[25=AT08-07\r\n] 2006.252.07:50:00.42#ibcon#*before write, iclass 26, count 2 2006.252.07:50:00.42#ibcon#enter sib2, iclass 26, count 2 2006.252.07:50:00.42#ibcon#flushed, iclass 26, count 2 2006.252.07:50:00.42#ibcon#about to write, iclass 26, count 2 2006.252.07:50:00.42#ibcon#wrote, iclass 26, count 2 2006.252.07:50:00.42#ibcon#about to read 3, iclass 26, count 2 2006.252.07:50:00.45#ibcon#read 3, iclass 26, count 2 2006.252.07:50:00.45#ibcon#about to read 4, iclass 26, count 2 2006.252.07:50:00.45#ibcon#read 4, iclass 26, count 2 2006.252.07:50:00.45#ibcon#about to read 5, iclass 26, count 2 2006.252.07:50:00.45#ibcon#read 5, iclass 26, count 2 2006.252.07:50:00.45#ibcon#about to read 6, iclass 26, count 2 2006.252.07:50:00.45#ibcon#read 6, iclass 26, count 2 2006.252.07:50:00.45#ibcon#end of sib2, iclass 26, count 2 2006.252.07:50:00.45#ibcon#*after write, iclass 26, count 2 2006.252.07:50:00.45#ibcon#*before return 0, iclass 26, count 2 2006.252.07:50:00.45#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.252.07:50:00.45#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.252.07:50:00.45#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.252.07:50:00.45#ibcon#ireg 7 cls_cnt 0 2006.252.07:50:00.45#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.252.07:50:00.57#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.252.07:50:00.57#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.252.07:50:00.57#ibcon#enter wrdev, iclass 26, count 0 2006.252.07:50:00.57#ibcon#first serial, iclass 26, count 0 2006.252.07:50:00.57#ibcon#enter sib2, iclass 26, count 0 2006.252.07:50:00.57#ibcon#flushed, iclass 26, count 0 2006.252.07:50:00.57#ibcon#about to write, iclass 26, count 0 2006.252.07:50:00.57#ibcon#wrote, iclass 26, count 0 2006.252.07:50:00.57#ibcon#about to read 3, iclass 26, count 0 2006.252.07:50:00.59#ibcon#read 3, iclass 26, count 0 2006.252.07:50:00.59#ibcon#about to read 4, iclass 26, count 0 2006.252.07:50:00.59#ibcon#read 4, iclass 26, count 0 2006.252.07:50:00.59#ibcon#about to read 5, iclass 26, count 0 2006.252.07:50:00.59#ibcon#read 5, iclass 26, count 0 2006.252.07:50:00.59#ibcon#about to read 6, iclass 26, count 0 2006.252.07:50:00.59#ibcon#read 6, iclass 26, count 0 2006.252.07:50:00.59#ibcon#end of sib2, iclass 26, count 0 2006.252.07:50:00.59#ibcon#*mode == 0, iclass 26, count 0 2006.252.07:50:00.59#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.252.07:50:00.59#ibcon#[25=USB\r\n] 2006.252.07:50:00.59#ibcon#*before write, iclass 26, count 0 2006.252.07:50:00.59#ibcon#enter sib2, iclass 26, count 0 2006.252.07:50:00.59#ibcon#flushed, iclass 26, count 0 2006.252.07:50:00.59#ibcon#about to write, iclass 26, count 0 2006.252.07:50:00.59#ibcon#wrote, iclass 26, count 0 2006.252.07:50:00.59#ibcon#about to read 3, iclass 26, count 0 2006.252.07:50:00.62#ibcon#read 3, iclass 26, count 0 2006.252.07:50:00.62#ibcon#about to read 4, iclass 26, count 0 2006.252.07:50:00.62#ibcon#read 4, iclass 26, count 0 2006.252.07:50:00.62#ibcon#about to read 5, iclass 26, count 0 2006.252.07:50:00.62#ibcon#read 5, iclass 26, count 0 2006.252.07:50:00.62#ibcon#about to read 6, iclass 26, count 0 2006.252.07:50:00.62#ibcon#read 6, iclass 26, count 0 2006.252.07:50:00.62#ibcon#end of sib2, iclass 26, count 0 2006.252.07:50:00.62#ibcon#*after write, iclass 26, count 0 2006.252.07:50:00.62#ibcon#*before return 0, iclass 26, count 0 2006.252.07:50:00.62#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.252.07:50:00.62#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.252.07:50:00.62#ibcon#about to clear, iclass 26 cls_cnt 0 2006.252.07:50:00.62#ibcon#cleared, iclass 26 cls_cnt 0 2006.252.07:50:00.62$vc4f8/vblo=1,632.99 2006.252.07:50:00.62#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.252.07:50:00.62#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.252.07:50:00.62#ibcon#ireg 17 cls_cnt 0 2006.252.07:50:00.62#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.252.07:50:00.62#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.252.07:50:00.62#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.252.07:50:00.62#ibcon#enter wrdev, iclass 28, count 0 2006.252.07:50:00.62#ibcon#first serial, iclass 28, count 0 2006.252.07:50:00.62#ibcon#enter sib2, iclass 28, count 0 2006.252.07:50:00.62#ibcon#flushed, iclass 28, count 0 2006.252.07:50:00.62#ibcon#about to write, iclass 28, count 0 2006.252.07:50:00.62#ibcon#wrote, iclass 28, count 0 2006.252.07:50:00.62#ibcon#about to read 3, iclass 28, count 0 2006.252.07:50:00.64#ibcon#read 3, iclass 28, count 0 2006.252.07:50:00.64#ibcon#about to read 4, iclass 28, count 0 2006.252.07:50:00.64#ibcon#read 4, iclass 28, count 0 2006.252.07:50:00.64#ibcon#about to read 5, iclass 28, count 0 2006.252.07:50:00.64#ibcon#read 5, iclass 28, count 0 2006.252.07:50:00.64#ibcon#about to read 6, iclass 28, count 0 2006.252.07:50:00.64#ibcon#read 6, iclass 28, count 0 2006.252.07:50:00.64#ibcon#end of sib2, iclass 28, count 0 2006.252.07:50:00.64#ibcon#*mode == 0, iclass 28, count 0 2006.252.07:50:00.64#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.252.07:50:00.64#ibcon#[28=FRQ=01,632.99\r\n] 2006.252.07:50:00.64#ibcon#*before write, iclass 28, count 0 2006.252.07:50:00.64#ibcon#enter sib2, iclass 28, count 0 2006.252.07:50:00.64#ibcon#flushed, iclass 28, count 0 2006.252.07:50:00.64#ibcon#about to write, iclass 28, count 0 2006.252.07:50:00.64#ibcon#wrote, iclass 28, count 0 2006.252.07:50:00.64#ibcon#about to read 3, iclass 28, count 0 2006.252.07:50:00.68#ibcon#read 3, iclass 28, count 0 2006.252.07:50:00.68#ibcon#about to read 4, iclass 28, count 0 2006.252.07:50:00.68#ibcon#read 4, iclass 28, count 0 2006.252.07:50:00.68#ibcon#about to read 5, iclass 28, count 0 2006.252.07:50:00.68#ibcon#read 5, iclass 28, count 0 2006.252.07:50:00.68#ibcon#about to read 6, iclass 28, count 0 2006.252.07:50:00.68#ibcon#read 6, iclass 28, count 0 2006.252.07:50:00.68#ibcon#end of sib2, iclass 28, count 0 2006.252.07:50:00.68#ibcon#*after write, iclass 28, count 0 2006.252.07:50:00.68#ibcon#*before return 0, iclass 28, count 0 2006.252.07:50:00.68#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.252.07:50:00.68#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.252.07:50:00.68#ibcon#about to clear, iclass 28 cls_cnt 0 2006.252.07:50:00.68#ibcon#cleared, iclass 28 cls_cnt 0 2006.252.07:50:00.68$vc4f8/vb=1,4 2006.252.07:50:00.68#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.252.07:50:00.68#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.252.07:50:00.68#ibcon#ireg 11 cls_cnt 2 2006.252.07:50:00.68#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.252.07:50:00.68#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.252.07:50:00.68#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.252.07:50:00.68#ibcon#enter wrdev, iclass 30, count 2 2006.252.07:50:00.68#ibcon#first serial, iclass 30, count 2 2006.252.07:50:00.68#ibcon#enter sib2, iclass 30, count 2 2006.252.07:50:00.68#ibcon#flushed, iclass 30, count 2 2006.252.07:50:00.68#ibcon#about to write, iclass 30, count 2 2006.252.07:50:00.68#ibcon#wrote, iclass 30, count 2 2006.252.07:50:00.68#ibcon#about to read 3, iclass 30, count 2 2006.252.07:50:00.70#ibcon#read 3, iclass 30, count 2 2006.252.07:50:00.70#ibcon#about to read 4, iclass 30, count 2 2006.252.07:50:00.70#ibcon#read 4, iclass 30, count 2 2006.252.07:50:00.70#ibcon#about to read 5, iclass 30, count 2 2006.252.07:50:00.70#ibcon#read 5, iclass 30, count 2 2006.252.07:50:00.70#ibcon#about to read 6, iclass 30, count 2 2006.252.07:50:00.70#ibcon#read 6, iclass 30, count 2 2006.252.07:50:00.70#ibcon#end of sib2, iclass 30, count 2 2006.252.07:50:00.70#ibcon#*mode == 0, iclass 30, count 2 2006.252.07:50:00.70#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.252.07:50:00.70#ibcon#[27=AT01-04\r\n] 2006.252.07:50:00.70#ibcon#*before write, iclass 30, count 2 2006.252.07:50:00.70#ibcon#enter sib2, iclass 30, count 2 2006.252.07:50:00.70#ibcon#flushed, iclass 30, count 2 2006.252.07:50:00.70#ibcon#about to write, iclass 30, count 2 2006.252.07:50:00.70#ibcon#wrote, iclass 30, count 2 2006.252.07:50:00.70#ibcon#about to read 3, iclass 30, count 2 2006.252.07:50:00.73#ibcon#read 3, iclass 30, count 2 2006.252.07:50:00.73#ibcon#about to read 4, iclass 30, count 2 2006.252.07:50:00.73#ibcon#read 4, iclass 30, count 2 2006.252.07:50:00.73#ibcon#about to read 5, iclass 30, count 2 2006.252.07:50:00.73#ibcon#read 5, iclass 30, count 2 2006.252.07:50:00.73#ibcon#about to read 6, iclass 30, count 2 2006.252.07:50:00.73#ibcon#read 6, iclass 30, count 2 2006.252.07:50:00.73#ibcon#end of sib2, iclass 30, count 2 2006.252.07:50:00.73#ibcon#*after write, iclass 30, count 2 2006.252.07:50:00.73#ibcon#*before return 0, iclass 30, count 2 2006.252.07:50:00.73#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.252.07:50:00.73#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.252.07:50:00.73#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.252.07:50:00.73#ibcon#ireg 7 cls_cnt 0 2006.252.07:50:00.73#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.252.07:50:00.85#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.252.07:50:00.85#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.252.07:50:00.85#ibcon#enter wrdev, iclass 30, count 0 2006.252.07:50:00.85#ibcon#first serial, iclass 30, count 0 2006.252.07:50:00.85#ibcon#enter sib2, iclass 30, count 0 2006.252.07:50:00.85#ibcon#flushed, iclass 30, count 0 2006.252.07:50:00.85#ibcon#about to write, iclass 30, count 0 2006.252.07:50:00.85#ibcon#wrote, iclass 30, count 0 2006.252.07:50:00.85#ibcon#about to read 3, iclass 30, count 0 2006.252.07:50:00.87#ibcon#read 3, iclass 30, count 0 2006.252.07:50:00.87#ibcon#about to read 4, iclass 30, count 0 2006.252.07:50:00.87#ibcon#read 4, iclass 30, count 0 2006.252.07:50:00.87#ibcon#about to read 5, iclass 30, count 0 2006.252.07:50:00.87#ibcon#read 5, iclass 30, count 0 2006.252.07:50:00.87#ibcon#about to read 6, iclass 30, count 0 2006.252.07:50:00.87#ibcon#read 6, iclass 30, count 0 2006.252.07:50:00.87#ibcon#end of sib2, iclass 30, count 0 2006.252.07:50:00.87#ibcon#*mode == 0, iclass 30, count 0 2006.252.07:50:00.87#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.252.07:50:00.87#ibcon#[27=USB\r\n] 2006.252.07:50:00.87#ibcon#*before write, iclass 30, count 0 2006.252.07:50:00.87#ibcon#enter sib2, iclass 30, count 0 2006.252.07:50:00.87#ibcon#flushed, iclass 30, count 0 2006.252.07:50:00.87#ibcon#about to write, iclass 30, count 0 2006.252.07:50:00.87#ibcon#wrote, iclass 30, count 0 2006.252.07:50:00.87#ibcon#about to read 3, iclass 30, count 0 2006.252.07:50:00.90#ibcon#read 3, iclass 30, count 0 2006.252.07:50:00.90#ibcon#about to read 4, iclass 30, count 0 2006.252.07:50:00.90#ibcon#read 4, iclass 30, count 0 2006.252.07:50:00.90#ibcon#about to read 5, iclass 30, count 0 2006.252.07:50:00.90#ibcon#read 5, iclass 30, count 0 2006.252.07:50:00.90#ibcon#about to read 6, iclass 30, count 0 2006.252.07:50:00.90#ibcon#read 6, iclass 30, count 0 2006.252.07:50:00.90#ibcon#end of sib2, iclass 30, count 0 2006.252.07:50:00.90#ibcon#*after write, iclass 30, count 0 2006.252.07:50:00.90#ibcon#*before return 0, iclass 30, count 0 2006.252.07:50:00.90#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.252.07:50:00.90#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.252.07:50:00.90#ibcon#about to clear, iclass 30 cls_cnt 0 2006.252.07:50:00.90#ibcon#cleared, iclass 30 cls_cnt 0 2006.252.07:50:00.90$vc4f8/vblo=2,640.99 2006.252.07:50:00.90#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.252.07:50:00.90#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.252.07:50:00.90#ibcon#ireg 17 cls_cnt 0 2006.252.07:50:00.90#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.252.07:50:00.90#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.252.07:50:00.90#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.252.07:50:00.90#ibcon#enter wrdev, iclass 32, count 0 2006.252.07:50:00.90#ibcon#first serial, iclass 32, count 0 2006.252.07:50:00.90#ibcon#enter sib2, iclass 32, count 0 2006.252.07:50:00.90#ibcon#flushed, iclass 32, count 0 2006.252.07:50:00.90#ibcon#about to write, iclass 32, count 0 2006.252.07:50:00.90#ibcon#wrote, iclass 32, count 0 2006.252.07:50:00.90#ibcon#about to read 3, iclass 32, count 0 2006.252.07:50:00.92#ibcon#read 3, iclass 32, count 0 2006.252.07:50:00.92#ibcon#about to read 4, iclass 32, count 0 2006.252.07:50:00.92#ibcon#read 4, iclass 32, count 0 2006.252.07:50:00.92#ibcon#about to read 5, iclass 32, count 0 2006.252.07:50:00.92#ibcon#read 5, iclass 32, count 0 2006.252.07:50:00.92#ibcon#about to read 6, iclass 32, count 0 2006.252.07:50:00.92#ibcon#read 6, iclass 32, count 0 2006.252.07:50:00.92#ibcon#end of sib2, iclass 32, count 0 2006.252.07:50:00.92#ibcon#*mode == 0, iclass 32, count 0 2006.252.07:50:00.92#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.252.07:50:00.92#ibcon#[28=FRQ=02,640.99\r\n] 2006.252.07:50:00.92#ibcon#*before write, iclass 32, count 0 2006.252.07:50:00.92#ibcon#enter sib2, iclass 32, count 0 2006.252.07:50:00.92#ibcon#flushed, iclass 32, count 0 2006.252.07:50:00.92#ibcon#about to write, iclass 32, count 0 2006.252.07:50:00.92#ibcon#wrote, iclass 32, count 0 2006.252.07:50:00.92#ibcon#about to read 3, iclass 32, count 0 2006.252.07:50:00.96#ibcon#read 3, iclass 32, count 0 2006.252.07:50:00.96#ibcon#about to read 4, iclass 32, count 0 2006.252.07:50:00.96#ibcon#read 4, iclass 32, count 0 2006.252.07:50:00.96#ibcon#about to read 5, iclass 32, count 0 2006.252.07:50:00.96#ibcon#read 5, iclass 32, count 0 2006.252.07:50:00.96#ibcon#about to read 6, iclass 32, count 0 2006.252.07:50:00.96#ibcon#read 6, iclass 32, count 0 2006.252.07:50:00.96#ibcon#end of sib2, iclass 32, count 0 2006.252.07:50:00.96#ibcon#*after write, iclass 32, count 0 2006.252.07:50:00.96#ibcon#*before return 0, iclass 32, count 0 2006.252.07:50:00.96#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.252.07:50:00.96#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.252.07:50:00.96#ibcon#about to clear, iclass 32 cls_cnt 0 2006.252.07:50:00.96#ibcon#cleared, iclass 32 cls_cnt 0 2006.252.07:50:00.96$vc4f8/vb=2,5 2006.252.07:50:00.96#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.252.07:50:00.96#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.252.07:50:00.96#ibcon#ireg 11 cls_cnt 2 2006.252.07:50:00.96#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.252.07:50:01.02#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.252.07:50:01.02#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.252.07:50:01.02#ibcon#enter wrdev, iclass 34, count 2 2006.252.07:50:01.02#ibcon#first serial, iclass 34, count 2 2006.252.07:50:01.02#ibcon#enter sib2, iclass 34, count 2 2006.252.07:50:01.02#ibcon#flushed, iclass 34, count 2 2006.252.07:50:01.02#ibcon#about to write, iclass 34, count 2 2006.252.07:50:01.02#ibcon#wrote, iclass 34, count 2 2006.252.07:50:01.02#ibcon#about to read 3, iclass 34, count 2 2006.252.07:50:01.04#ibcon#read 3, iclass 34, count 2 2006.252.07:50:01.04#ibcon#about to read 4, iclass 34, count 2 2006.252.07:50:01.04#ibcon#read 4, iclass 34, count 2 2006.252.07:50:01.04#ibcon#about to read 5, iclass 34, count 2 2006.252.07:50:01.04#ibcon#read 5, iclass 34, count 2 2006.252.07:50:01.04#ibcon#about to read 6, iclass 34, count 2 2006.252.07:50:01.04#ibcon#read 6, iclass 34, count 2 2006.252.07:50:01.04#ibcon#end of sib2, iclass 34, count 2 2006.252.07:50:01.04#ibcon#*mode == 0, iclass 34, count 2 2006.252.07:50:01.04#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.252.07:50:01.04#ibcon#[27=AT02-05\r\n] 2006.252.07:50:01.04#ibcon#*before write, iclass 34, count 2 2006.252.07:50:01.04#ibcon#enter sib2, iclass 34, count 2 2006.252.07:50:01.04#ibcon#flushed, iclass 34, count 2 2006.252.07:50:01.04#ibcon#about to write, iclass 34, count 2 2006.252.07:50:01.04#ibcon#wrote, iclass 34, count 2 2006.252.07:50:01.04#ibcon#about to read 3, iclass 34, count 2 2006.252.07:50:01.07#ibcon#read 3, iclass 34, count 2 2006.252.07:50:01.07#ibcon#about to read 4, iclass 34, count 2 2006.252.07:50:01.07#ibcon#read 4, iclass 34, count 2 2006.252.07:50:01.07#ibcon#about to read 5, iclass 34, count 2 2006.252.07:50:01.07#ibcon#read 5, iclass 34, count 2 2006.252.07:50:01.07#ibcon#about to read 6, iclass 34, count 2 2006.252.07:50:01.07#ibcon#read 6, iclass 34, count 2 2006.252.07:50:01.07#ibcon#end of sib2, iclass 34, count 2 2006.252.07:50:01.07#ibcon#*after write, iclass 34, count 2 2006.252.07:50:01.07#ibcon#*before return 0, iclass 34, count 2 2006.252.07:50:01.07#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.252.07:50:01.07#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.252.07:50:01.07#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.252.07:50:01.07#ibcon#ireg 7 cls_cnt 0 2006.252.07:50:01.07#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.252.07:50:01.19#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.252.07:50:01.19#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.252.07:50:01.19#ibcon#enter wrdev, iclass 34, count 0 2006.252.07:50:01.19#ibcon#first serial, iclass 34, count 0 2006.252.07:50:01.19#ibcon#enter sib2, iclass 34, count 0 2006.252.07:50:01.19#ibcon#flushed, iclass 34, count 0 2006.252.07:50:01.19#ibcon#about to write, iclass 34, count 0 2006.252.07:50:01.19#ibcon#wrote, iclass 34, count 0 2006.252.07:50:01.19#ibcon#about to read 3, iclass 34, count 0 2006.252.07:50:01.23#ibcon#read 3, iclass 34, count 0 2006.252.07:50:01.23#ibcon#about to read 4, iclass 34, count 0 2006.252.07:50:01.23#ibcon#read 4, iclass 34, count 0 2006.252.07:50:01.23#ibcon#about to read 5, iclass 34, count 0 2006.252.07:50:01.23#ibcon#read 5, iclass 34, count 0 2006.252.07:50:01.23#ibcon#about to read 6, iclass 34, count 0 2006.252.07:50:01.23#ibcon#read 6, iclass 34, count 0 2006.252.07:50:01.23#ibcon#end of sib2, iclass 34, count 0 2006.252.07:50:01.23#ibcon#*mode == 0, iclass 34, count 0 2006.252.07:50:01.23#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.252.07:50:01.23#ibcon#[27=USB\r\n] 2006.252.07:50:01.23#ibcon#*before write, iclass 34, count 0 2006.252.07:50:01.23#ibcon#enter sib2, iclass 34, count 0 2006.252.07:50:01.23#ibcon#flushed, iclass 34, count 0 2006.252.07:50:01.23#ibcon#about to write, iclass 34, count 0 2006.252.07:50:01.23#ibcon#wrote, iclass 34, count 0 2006.252.07:50:01.23#ibcon#about to read 3, iclass 34, count 0 2006.252.07:50:01.25#ibcon#read 3, iclass 34, count 0 2006.252.07:50:01.25#ibcon#about to read 4, iclass 34, count 0 2006.252.07:50:01.25#ibcon#read 4, iclass 34, count 0 2006.252.07:50:01.25#ibcon#about to read 5, iclass 34, count 0 2006.252.07:50:01.25#ibcon#read 5, iclass 34, count 0 2006.252.07:50:01.25#ibcon#about to read 6, iclass 34, count 0 2006.252.07:50:01.25#ibcon#read 6, iclass 34, count 0 2006.252.07:50:01.25#ibcon#end of sib2, iclass 34, count 0 2006.252.07:50:01.25#ibcon#*after write, iclass 34, count 0 2006.252.07:50:01.25#ibcon#*before return 0, iclass 34, count 0 2006.252.07:50:01.25#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.252.07:50:01.25#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.252.07:50:01.25#ibcon#about to clear, iclass 34 cls_cnt 0 2006.252.07:50:01.25#ibcon#cleared, iclass 34 cls_cnt 0 2006.252.07:50:01.25$vc4f8/vblo=3,656.99 2006.252.07:50:01.25#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.252.07:50:01.25#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.252.07:50:01.25#ibcon#ireg 17 cls_cnt 0 2006.252.07:50:01.25#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.252.07:50:01.25#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.252.07:50:01.25#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.252.07:50:01.25#ibcon#enter wrdev, iclass 36, count 0 2006.252.07:50:01.25#ibcon#first serial, iclass 36, count 0 2006.252.07:50:01.25#ibcon#enter sib2, iclass 36, count 0 2006.252.07:50:01.25#ibcon#flushed, iclass 36, count 0 2006.252.07:50:01.25#ibcon#about to write, iclass 36, count 0 2006.252.07:50:01.25#ibcon#wrote, iclass 36, count 0 2006.252.07:50:01.25#ibcon#about to read 3, iclass 36, count 0 2006.252.07:50:01.27#ibcon#read 3, iclass 36, count 0 2006.252.07:50:01.27#ibcon#about to read 4, iclass 36, count 0 2006.252.07:50:01.27#ibcon#read 4, iclass 36, count 0 2006.252.07:50:01.27#ibcon#about to read 5, iclass 36, count 0 2006.252.07:50:01.27#ibcon#read 5, iclass 36, count 0 2006.252.07:50:01.27#ibcon#about to read 6, iclass 36, count 0 2006.252.07:50:01.27#ibcon#read 6, iclass 36, count 0 2006.252.07:50:01.27#ibcon#end of sib2, iclass 36, count 0 2006.252.07:50:01.27#ibcon#*mode == 0, iclass 36, count 0 2006.252.07:50:01.27#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.252.07:50:01.27#ibcon#[28=FRQ=03,656.99\r\n] 2006.252.07:50:01.27#ibcon#*before write, iclass 36, count 0 2006.252.07:50:01.27#ibcon#enter sib2, iclass 36, count 0 2006.252.07:50:01.27#ibcon#flushed, iclass 36, count 0 2006.252.07:50:01.27#ibcon#about to write, iclass 36, count 0 2006.252.07:50:01.27#ibcon#wrote, iclass 36, count 0 2006.252.07:50:01.27#ibcon#about to read 3, iclass 36, count 0 2006.252.07:50:01.31#ibcon#read 3, iclass 36, count 0 2006.252.07:50:01.31#ibcon#about to read 4, iclass 36, count 0 2006.252.07:50:01.31#ibcon#read 4, iclass 36, count 0 2006.252.07:50:01.31#ibcon#about to read 5, iclass 36, count 0 2006.252.07:50:01.31#ibcon#read 5, iclass 36, count 0 2006.252.07:50:01.31#ibcon#about to read 6, iclass 36, count 0 2006.252.07:50:01.31#ibcon#read 6, iclass 36, count 0 2006.252.07:50:01.31#ibcon#end of sib2, iclass 36, count 0 2006.252.07:50:01.31#ibcon#*after write, iclass 36, count 0 2006.252.07:50:01.31#ibcon#*before return 0, iclass 36, count 0 2006.252.07:50:01.31#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.252.07:50:01.31#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.252.07:50:01.31#ibcon#about to clear, iclass 36 cls_cnt 0 2006.252.07:50:01.31#ibcon#cleared, iclass 36 cls_cnt 0 2006.252.07:50:01.31$vc4f8/vb=3,4 2006.252.07:50:01.31#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.252.07:50:01.31#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.252.07:50:01.31#ibcon#ireg 11 cls_cnt 2 2006.252.07:50:01.31#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.252.07:50:01.37#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.252.07:50:01.37#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.252.07:50:01.37#ibcon#enter wrdev, iclass 38, count 2 2006.252.07:50:01.37#ibcon#first serial, iclass 38, count 2 2006.252.07:50:01.37#ibcon#enter sib2, iclass 38, count 2 2006.252.07:50:01.37#ibcon#flushed, iclass 38, count 2 2006.252.07:50:01.37#ibcon#about to write, iclass 38, count 2 2006.252.07:50:01.37#ibcon#wrote, iclass 38, count 2 2006.252.07:50:01.37#ibcon#about to read 3, iclass 38, count 2 2006.252.07:50:01.39#ibcon#read 3, iclass 38, count 2 2006.252.07:50:01.39#ibcon#about to read 4, iclass 38, count 2 2006.252.07:50:01.39#ibcon#read 4, iclass 38, count 2 2006.252.07:50:01.39#ibcon#about to read 5, iclass 38, count 2 2006.252.07:50:01.39#ibcon#read 5, iclass 38, count 2 2006.252.07:50:01.39#ibcon#about to read 6, iclass 38, count 2 2006.252.07:50:01.39#ibcon#read 6, iclass 38, count 2 2006.252.07:50:01.39#ibcon#end of sib2, iclass 38, count 2 2006.252.07:50:01.39#ibcon#*mode == 0, iclass 38, count 2 2006.252.07:50:01.39#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.252.07:50:01.39#ibcon#[27=AT03-04\r\n] 2006.252.07:50:01.39#ibcon#*before write, iclass 38, count 2 2006.252.07:50:01.39#ibcon#enter sib2, iclass 38, count 2 2006.252.07:50:01.39#ibcon#flushed, iclass 38, count 2 2006.252.07:50:01.39#ibcon#about to write, iclass 38, count 2 2006.252.07:50:01.39#ibcon#wrote, iclass 38, count 2 2006.252.07:50:01.39#ibcon#about to read 3, iclass 38, count 2 2006.252.07:50:01.42#ibcon#read 3, iclass 38, count 2 2006.252.07:50:01.42#ibcon#about to read 4, iclass 38, count 2 2006.252.07:50:01.42#ibcon#read 4, iclass 38, count 2 2006.252.07:50:01.42#ibcon#about to read 5, iclass 38, count 2 2006.252.07:50:01.42#ibcon#read 5, iclass 38, count 2 2006.252.07:50:01.42#ibcon#about to read 6, iclass 38, count 2 2006.252.07:50:01.42#ibcon#read 6, iclass 38, count 2 2006.252.07:50:01.42#ibcon#end of sib2, iclass 38, count 2 2006.252.07:50:01.42#ibcon#*after write, iclass 38, count 2 2006.252.07:50:01.42#ibcon#*before return 0, iclass 38, count 2 2006.252.07:50:01.42#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.252.07:50:01.42#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.252.07:50:01.42#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.252.07:50:01.42#ibcon#ireg 7 cls_cnt 0 2006.252.07:50:01.42#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.252.07:50:01.54#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.252.07:50:01.54#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.252.07:50:01.54#ibcon#enter wrdev, iclass 38, count 0 2006.252.07:50:01.54#ibcon#first serial, iclass 38, count 0 2006.252.07:50:01.54#ibcon#enter sib2, iclass 38, count 0 2006.252.07:50:01.54#ibcon#flushed, iclass 38, count 0 2006.252.07:50:01.54#ibcon#about to write, iclass 38, count 0 2006.252.07:50:01.54#ibcon#wrote, iclass 38, count 0 2006.252.07:50:01.54#ibcon#about to read 3, iclass 38, count 0 2006.252.07:50:01.56#ibcon#read 3, iclass 38, count 0 2006.252.07:50:01.56#ibcon#about to read 4, iclass 38, count 0 2006.252.07:50:01.56#ibcon#read 4, iclass 38, count 0 2006.252.07:50:01.56#ibcon#about to read 5, iclass 38, count 0 2006.252.07:50:01.56#ibcon#read 5, iclass 38, count 0 2006.252.07:50:01.56#ibcon#about to read 6, iclass 38, count 0 2006.252.07:50:01.56#ibcon#read 6, iclass 38, count 0 2006.252.07:50:01.56#ibcon#end of sib2, iclass 38, count 0 2006.252.07:50:01.56#ibcon#*mode == 0, iclass 38, count 0 2006.252.07:50:01.56#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.252.07:50:01.56#ibcon#[27=USB\r\n] 2006.252.07:50:01.56#ibcon#*before write, iclass 38, count 0 2006.252.07:50:01.56#ibcon#enter sib2, iclass 38, count 0 2006.252.07:50:01.56#ibcon#flushed, iclass 38, count 0 2006.252.07:50:01.56#ibcon#about to write, iclass 38, count 0 2006.252.07:50:01.56#ibcon#wrote, iclass 38, count 0 2006.252.07:50:01.56#ibcon#about to read 3, iclass 38, count 0 2006.252.07:50:01.59#ibcon#read 3, iclass 38, count 0 2006.252.07:50:01.59#ibcon#about to read 4, iclass 38, count 0 2006.252.07:50:01.59#ibcon#read 4, iclass 38, count 0 2006.252.07:50:01.59#ibcon#about to read 5, iclass 38, count 0 2006.252.07:50:01.59#ibcon#read 5, iclass 38, count 0 2006.252.07:50:01.59#ibcon#about to read 6, iclass 38, count 0 2006.252.07:50:01.59#ibcon#read 6, iclass 38, count 0 2006.252.07:50:01.59#ibcon#end of sib2, iclass 38, count 0 2006.252.07:50:01.59#ibcon#*after write, iclass 38, count 0 2006.252.07:50:01.59#ibcon#*before return 0, iclass 38, count 0 2006.252.07:50:01.59#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.252.07:50:01.59#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.252.07:50:01.59#ibcon#about to clear, iclass 38 cls_cnt 0 2006.252.07:50:01.59#ibcon#cleared, iclass 38 cls_cnt 0 2006.252.07:50:01.59$vc4f8/vblo=4,712.99 2006.252.07:50:01.59#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.252.07:50:01.59#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.252.07:50:01.59#ibcon#ireg 17 cls_cnt 0 2006.252.07:50:01.59#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.252.07:50:01.59#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.252.07:50:01.59#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.252.07:50:01.59#ibcon#enter wrdev, iclass 40, count 0 2006.252.07:50:01.59#ibcon#first serial, iclass 40, count 0 2006.252.07:50:01.59#ibcon#enter sib2, iclass 40, count 0 2006.252.07:50:01.59#ibcon#flushed, iclass 40, count 0 2006.252.07:50:01.59#ibcon#about to write, iclass 40, count 0 2006.252.07:50:01.59#ibcon#wrote, iclass 40, count 0 2006.252.07:50:01.59#ibcon#about to read 3, iclass 40, count 0 2006.252.07:50:01.61#ibcon#read 3, iclass 40, count 0 2006.252.07:50:01.61#ibcon#about to read 4, iclass 40, count 0 2006.252.07:50:01.61#ibcon#read 4, iclass 40, count 0 2006.252.07:50:01.61#ibcon#about to read 5, iclass 40, count 0 2006.252.07:50:01.61#ibcon#read 5, iclass 40, count 0 2006.252.07:50:01.61#ibcon#about to read 6, iclass 40, count 0 2006.252.07:50:01.61#ibcon#read 6, iclass 40, count 0 2006.252.07:50:01.61#ibcon#end of sib2, iclass 40, count 0 2006.252.07:50:01.61#ibcon#*mode == 0, iclass 40, count 0 2006.252.07:50:01.61#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.252.07:50:01.61#ibcon#[28=FRQ=04,712.99\r\n] 2006.252.07:50:01.61#ibcon#*before write, iclass 40, count 0 2006.252.07:50:01.61#ibcon#enter sib2, iclass 40, count 0 2006.252.07:50:01.61#ibcon#flushed, iclass 40, count 0 2006.252.07:50:01.61#ibcon#about to write, iclass 40, count 0 2006.252.07:50:01.61#ibcon#wrote, iclass 40, count 0 2006.252.07:50:01.61#ibcon#about to read 3, iclass 40, count 0 2006.252.07:50:01.65#ibcon#read 3, iclass 40, count 0 2006.252.07:50:01.65#ibcon#about to read 4, iclass 40, count 0 2006.252.07:50:01.65#ibcon#read 4, iclass 40, count 0 2006.252.07:50:01.65#ibcon#about to read 5, iclass 40, count 0 2006.252.07:50:01.65#ibcon#read 5, iclass 40, count 0 2006.252.07:50:01.65#ibcon#about to read 6, iclass 40, count 0 2006.252.07:50:01.65#ibcon#read 6, iclass 40, count 0 2006.252.07:50:01.65#ibcon#end of sib2, iclass 40, count 0 2006.252.07:50:01.65#ibcon#*after write, iclass 40, count 0 2006.252.07:50:01.65#ibcon#*before return 0, iclass 40, count 0 2006.252.07:50:01.65#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.252.07:50:01.65#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.252.07:50:01.65#ibcon#about to clear, iclass 40 cls_cnt 0 2006.252.07:50:01.65#ibcon#cleared, iclass 40 cls_cnt 0 2006.252.07:50:01.65$vc4f8/vb=4,4 2006.252.07:50:01.65#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.252.07:50:01.65#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.252.07:50:01.65#ibcon#ireg 11 cls_cnt 2 2006.252.07:50:01.65#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.252.07:50:01.71#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.252.07:50:01.71#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.252.07:50:01.71#ibcon#enter wrdev, iclass 4, count 2 2006.252.07:50:01.71#ibcon#first serial, iclass 4, count 2 2006.252.07:50:01.71#ibcon#enter sib2, iclass 4, count 2 2006.252.07:50:01.71#ibcon#flushed, iclass 4, count 2 2006.252.07:50:01.71#ibcon#about to write, iclass 4, count 2 2006.252.07:50:01.71#ibcon#wrote, iclass 4, count 2 2006.252.07:50:01.71#ibcon#about to read 3, iclass 4, count 2 2006.252.07:50:01.73#ibcon#read 3, iclass 4, count 2 2006.252.07:50:01.73#ibcon#about to read 4, iclass 4, count 2 2006.252.07:50:01.73#ibcon#read 4, iclass 4, count 2 2006.252.07:50:01.73#ibcon#about to read 5, iclass 4, count 2 2006.252.07:50:01.73#ibcon#read 5, iclass 4, count 2 2006.252.07:50:01.73#ibcon#about to read 6, iclass 4, count 2 2006.252.07:50:01.73#ibcon#read 6, iclass 4, count 2 2006.252.07:50:01.73#ibcon#end of sib2, iclass 4, count 2 2006.252.07:50:01.73#ibcon#*mode == 0, iclass 4, count 2 2006.252.07:50:01.73#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.252.07:50:01.73#ibcon#[27=AT04-04\r\n] 2006.252.07:50:01.73#ibcon#*before write, iclass 4, count 2 2006.252.07:50:01.73#ibcon#enter sib2, iclass 4, count 2 2006.252.07:50:01.73#ibcon#flushed, iclass 4, count 2 2006.252.07:50:01.73#ibcon#about to write, iclass 4, count 2 2006.252.07:50:01.73#ibcon#wrote, iclass 4, count 2 2006.252.07:50:01.73#ibcon#about to read 3, iclass 4, count 2 2006.252.07:50:01.76#ibcon#read 3, iclass 4, count 2 2006.252.07:50:01.76#ibcon#about to read 4, iclass 4, count 2 2006.252.07:50:01.76#ibcon#read 4, iclass 4, count 2 2006.252.07:50:01.76#ibcon#about to read 5, iclass 4, count 2 2006.252.07:50:01.76#ibcon#read 5, iclass 4, count 2 2006.252.07:50:01.76#ibcon#about to read 6, iclass 4, count 2 2006.252.07:50:01.76#ibcon#read 6, iclass 4, count 2 2006.252.07:50:01.76#ibcon#end of sib2, iclass 4, count 2 2006.252.07:50:01.76#ibcon#*after write, iclass 4, count 2 2006.252.07:50:01.76#ibcon#*before return 0, iclass 4, count 2 2006.252.07:50:01.76#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.252.07:50:01.76#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.252.07:50:01.76#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.252.07:50:01.76#ibcon#ireg 7 cls_cnt 0 2006.252.07:50:01.76#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.252.07:50:01.88#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.252.07:50:01.88#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.252.07:50:01.88#ibcon#enter wrdev, iclass 4, count 0 2006.252.07:50:01.88#ibcon#first serial, iclass 4, count 0 2006.252.07:50:01.88#ibcon#enter sib2, iclass 4, count 0 2006.252.07:50:01.88#ibcon#flushed, iclass 4, count 0 2006.252.07:50:01.88#ibcon#about to write, iclass 4, count 0 2006.252.07:50:01.88#ibcon#wrote, iclass 4, count 0 2006.252.07:50:01.88#ibcon#about to read 3, iclass 4, count 0 2006.252.07:50:01.90#ibcon#read 3, iclass 4, count 0 2006.252.07:50:01.90#ibcon#about to read 4, iclass 4, count 0 2006.252.07:50:01.90#ibcon#read 4, iclass 4, count 0 2006.252.07:50:01.90#ibcon#about to read 5, iclass 4, count 0 2006.252.07:50:01.90#ibcon#read 5, iclass 4, count 0 2006.252.07:50:01.90#ibcon#about to read 6, iclass 4, count 0 2006.252.07:50:01.90#ibcon#read 6, iclass 4, count 0 2006.252.07:50:01.90#ibcon#end of sib2, iclass 4, count 0 2006.252.07:50:01.90#ibcon#*mode == 0, iclass 4, count 0 2006.252.07:50:01.90#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.252.07:50:01.90#ibcon#[27=USB\r\n] 2006.252.07:50:01.90#ibcon#*before write, iclass 4, count 0 2006.252.07:50:01.90#ibcon#enter sib2, iclass 4, count 0 2006.252.07:50:01.90#ibcon#flushed, iclass 4, count 0 2006.252.07:50:01.90#ibcon#about to write, iclass 4, count 0 2006.252.07:50:01.90#ibcon#wrote, iclass 4, count 0 2006.252.07:50:01.90#ibcon#about to read 3, iclass 4, count 0 2006.252.07:50:01.93#ibcon#read 3, iclass 4, count 0 2006.252.07:50:01.93#ibcon#about to read 4, iclass 4, count 0 2006.252.07:50:01.93#ibcon#read 4, iclass 4, count 0 2006.252.07:50:01.93#ibcon#about to read 5, iclass 4, count 0 2006.252.07:50:01.93#ibcon#read 5, iclass 4, count 0 2006.252.07:50:01.93#ibcon#about to read 6, iclass 4, count 0 2006.252.07:50:01.93#ibcon#read 6, iclass 4, count 0 2006.252.07:50:01.93#ibcon#end of sib2, iclass 4, count 0 2006.252.07:50:01.93#ibcon#*after write, iclass 4, count 0 2006.252.07:50:01.93#ibcon#*before return 0, iclass 4, count 0 2006.252.07:50:01.93#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.252.07:50:01.93#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.252.07:50:01.93#ibcon#about to clear, iclass 4 cls_cnt 0 2006.252.07:50:01.93#ibcon#cleared, iclass 4 cls_cnt 0 2006.252.07:50:01.93$vc4f8/vblo=5,744.99 2006.252.07:50:01.93#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.252.07:50:01.93#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.252.07:50:01.93#ibcon#ireg 17 cls_cnt 0 2006.252.07:50:01.93#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.252.07:50:01.93#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.252.07:50:01.93#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.252.07:50:01.93#ibcon#enter wrdev, iclass 6, count 0 2006.252.07:50:01.93#ibcon#first serial, iclass 6, count 0 2006.252.07:50:01.93#ibcon#enter sib2, iclass 6, count 0 2006.252.07:50:01.93#ibcon#flushed, iclass 6, count 0 2006.252.07:50:01.93#ibcon#about to write, iclass 6, count 0 2006.252.07:50:01.93#ibcon#wrote, iclass 6, count 0 2006.252.07:50:01.93#ibcon#about to read 3, iclass 6, count 0 2006.252.07:50:01.95#ibcon#read 3, iclass 6, count 0 2006.252.07:50:01.95#ibcon#about to read 4, iclass 6, count 0 2006.252.07:50:01.95#ibcon#read 4, iclass 6, count 0 2006.252.07:50:01.95#ibcon#about to read 5, iclass 6, count 0 2006.252.07:50:01.95#ibcon#read 5, iclass 6, count 0 2006.252.07:50:01.95#ibcon#about to read 6, iclass 6, count 0 2006.252.07:50:01.95#ibcon#read 6, iclass 6, count 0 2006.252.07:50:01.95#ibcon#end of sib2, iclass 6, count 0 2006.252.07:50:01.95#ibcon#*mode == 0, iclass 6, count 0 2006.252.07:50:01.95#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.252.07:50:01.95#ibcon#[28=FRQ=05,744.99\r\n] 2006.252.07:50:01.95#ibcon#*before write, iclass 6, count 0 2006.252.07:50:01.95#ibcon#enter sib2, iclass 6, count 0 2006.252.07:50:01.95#ibcon#flushed, iclass 6, count 0 2006.252.07:50:01.95#ibcon#about to write, iclass 6, count 0 2006.252.07:50:01.95#ibcon#wrote, iclass 6, count 0 2006.252.07:50:01.95#ibcon#about to read 3, iclass 6, count 0 2006.252.07:50:01.99#ibcon#read 3, iclass 6, count 0 2006.252.07:50:01.99#ibcon#about to read 4, iclass 6, count 0 2006.252.07:50:01.99#ibcon#read 4, iclass 6, count 0 2006.252.07:50:01.99#ibcon#about to read 5, iclass 6, count 0 2006.252.07:50:01.99#ibcon#read 5, iclass 6, count 0 2006.252.07:50:01.99#ibcon#about to read 6, iclass 6, count 0 2006.252.07:50:01.99#ibcon#read 6, iclass 6, count 0 2006.252.07:50:01.99#ibcon#end of sib2, iclass 6, count 0 2006.252.07:50:01.99#ibcon#*after write, iclass 6, count 0 2006.252.07:50:01.99#ibcon#*before return 0, iclass 6, count 0 2006.252.07:50:01.99#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.252.07:50:01.99#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.252.07:50:01.99#ibcon#about to clear, iclass 6 cls_cnt 0 2006.252.07:50:01.99#ibcon#cleared, iclass 6 cls_cnt 0 2006.252.07:50:01.99$vc4f8/vb=5,4 2006.252.07:50:01.99#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.252.07:50:01.99#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.252.07:50:01.99#ibcon#ireg 11 cls_cnt 2 2006.252.07:50:01.99#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.252.07:50:02.06#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.252.07:50:02.06#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.252.07:50:02.06#ibcon#enter wrdev, iclass 10, count 2 2006.252.07:50:02.06#ibcon#first serial, iclass 10, count 2 2006.252.07:50:02.06#ibcon#enter sib2, iclass 10, count 2 2006.252.07:50:02.06#ibcon#flushed, iclass 10, count 2 2006.252.07:50:02.06#ibcon#about to write, iclass 10, count 2 2006.252.07:50:02.06#ibcon#wrote, iclass 10, count 2 2006.252.07:50:02.06#ibcon#about to read 3, iclass 10, count 2 2006.252.07:50:02.07#ibcon#read 3, iclass 10, count 2 2006.252.07:50:02.07#ibcon#about to read 4, iclass 10, count 2 2006.252.07:50:02.07#ibcon#read 4, iclass 10, count 2 2006.252.07:50:02.07#ibcon#about to read 5, iclass 10, count 2 2006.252.07:50:02.07#ibcon#read 5, iclass 10, count 2 2006.252.07:50:02.07#ibcon#about to read 6, iclass 10, count 2 2006.252.07:50:02.07#ibcon#read 6, iclass 10, count 2 2006.252.07:50:02.07#ibcon#end of sib2, iclass 10, count 2 2006.252.07:50:02.07#ibcon#*mode == 0, iclass 10, count 2 2006.252.07:50:02.07#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.252.07:50:02.07#ibcon#[27=AT05-04\r\n] 2006.252.07:50:02.07#ibcon#*before write, iclass 10, count 2 2006.252.07:50:02.07#ibcon#enter sib2, iclass 10, count 2 2006.252.07:50:02.07#ibcon#flushed, iclass 10, count 2 2006.252.07:50:02.07#ibcon#about to write, iclass 10, count 2 2006.252.07:50:02.07#ibcon#wrote, iclass 10, count 2 2006.252.07:50:02.07#ibcon#about to read 3, iclass 10, count 2 2006.252.07:50:02.10#ibcon#read 3, iclass 10, count 2 2006.252.07:50:02.10#ibcon#about to read 4, iclass 10, count 2 2006.252.07:50:02.10#ibcon#read 4, iclass 10, count 2 2006.252.07:50:02.10#ibcon#about to read 5, iclass 10, count 2 2006.252.07:50:02.10#ibcon#read 5, iclass 10, count 2 2006.252.07:50:02.10#ibcon#about to read 6, iclass 10, count 2 2006.252.07:50:02.10#ibcon#read 6, iclass 10, count 2 2006.252.07:50:02.10#ibcon#end of sib2, iclass 10, count 2 2006.252.07:50:02.10#ibcon#*after write, iclass 10, count 2 2006.252.07:50:02.10#ibcon#*before return 0, iclass 10, count 2 2006.252.07:50:02.10#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.252.07:50:02.10#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.252.07:50:02.10#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.252.07:50:02.10#ibcon#ireg 7 cls_cnt 0 2006.252.07:50:02.10#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.252.07:50:02.22#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.252.07:50:02.22#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.252.07:50:02.22#ibcon#enter wrdev, iclass 10, count 0 2006.252.07:50:02.22#ibcon#first serial, iclass 10, count 0 2006.252.07:50:02.22#ibcon#enter sib2, iclass 10, count 0 2006.252.07:50:02.22#ibcon#flushed, iclass 10, count 0 2006.252.07:50:02.22#ibcon#about to write, iclass 10, count 0 2006.252.07:50:02.22#ibcon#wrote, iclass 10, count 0 2006.252.07:50:02.22#ibcon#about to read 3, iclass 10, count 0 2006.252.07:50:02.24#ibcon#read 3, iclass 10, count 0 2006.252.07:50:02.24#ibcon#about to read 4, iclass 10, count 0 2006.252.07:50:02.24#ibcon#read 4, iclass 10, count 0 2006.252.07:50:02.24#ibcon#about to read 5, iclass 10, count 0 2006.252.07:50:02.24#ibcon#read 5, iclass 10, count 0 2006.252.07:50:02.24#ibcon#about to read 6, iclass 10, count 0 2006.252.07:50:02.24#ibcon#read 6, iclass 10, count 0 2006.252.07:50:02.24#ibcon#end of sib2, iclass 10, count 0 2006.252.07:50:02.24#ibcon#*mode == 0, iclass 10, count 0 2006.252.07:50:02.24#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.252.07:50:02.24#ibcon#[27=USB\r\n] 2006.252.07:50:02.24#ibcon#*before write, iclass 10, count 0 2006.252.07:50:02.24#ibcon#enter sib2, iclass 10, count 0 2006.252.07:50:02.24#ibcon#flushed, iclass 10, count 0 2006.252.07:50:02.24#ibcon#about to write, iclass 10, count 0 2006.252.07:50:02.24#ibcon#wrote, iclass 10, count 0 2006.252.07:50:02.24#ibcon#about to read 3, iclass 10, count 0 2006.252.07:50:02.27#ibcon#read 3, iclass 10, count 0 2006.252.07:50:02.27#ibcon#about to read 4, iclass 10, count 0 2006.252.07:50:02.27#ibcon#read 4, iclass 10, count 0 2006.252.07:50:02.27#ibcon#about to read 5, iclass 10, count 0 2006.252.07:50:02.27#ibcon#read 5, iclass 10, count 0 2006.252.07:50:02.27#ibcon#about to read 6, iclass 10, count 0 2006.252.07:50:02.27#ibcon#read 6, iclass 10, count 0 2006.252.07:50:02.27#ibcon#end of sib2, iclass 10, count 0 2006.252.07:50:02.27#ibcon#*after write, iclass 10, count 0 2006.252.07:50:02.27#ibcon#*before return 0, iclass 10, count 0 2006.252.07:50:02.27#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.252.07:50:02.27#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.252.07:50:02.27#ibcon#about to clear, iclass 10 cls_cnt 0 2006.252.07:50:02.27#ibcon#cleared, iclass 10 cls_cnt 0 2006.252.07:50:02.27$vc4f8/vblo=6,752.99 2006.252.07:50:02.27#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.252.07:50:02.27#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.252.07:50:02.27#ibcon#ireg 17 cls_cnt 0 2006.252.07:50:02.27#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.252.07:50:02.27#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.252.07:50:02.27#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.252.07:50:02.27#ibcon#enter wrdev, iclass 12, count 0 2006.252.07:50:02.27#ibcon#first serial, iclass 12, count 0 2006.252.07:50:02.27#ibcon#enter sib2, iclass 12, count 0 2006.252.07:50:02.27#ibcon#flushed, iclass 12, count 0 2006.252.07:50:02.27#ibcon#about to write, iclass 12, count 0 2006.252.07:50:02.27#ibcon#wrote, iclass 12, count 0 2006.252.07:50:02.27#ibcon#about to read 3, iclass 12, count 0 2006.252.07:50:02.29#ibcon#read 3, iclass 12, count 0 2006.252.07:50:02.29#ibcon#about to read 4, iclass 12, count 0 2006.252.07:50:02.29#ibcon#read 4, iclass 12, count 0 2006.252.07:50:02.29#ibcon#about to read 5, iclass 12, count 0 2006.252.07:50:02.29#ibcon#read 5, iclass 12, count 0 2006.252.07:50:02.29#ibcon#about to read 6, iclass 12, count 0 2006.252.07:50:02.29#ibcon#read 6, iclass 12, count 0 2006.252.07:50:02.29#ibcon#end of sib2, iclass 12, count 0 2006.252.07:50:02.29#ibcon#*mode == 0, iclass 12, count 0 2006.252.07:50:02.29#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.252.07:50:02.29#ibcon#[28=FRQ=06,752.99\r\n] 2006.252.07:50:02.29#ibcon#*before write, iclass 12, count 0 2006.252.07:50:02.29#ibcon#enter sib2, iclass 12, count 0 2006.252.07:50:02.29#ibcon#flushed, iclass 12, count 0 2006.252.07:50:02.29#ibcon#about to write, iclass 12, count 0 2006.252.07:50:02.29#ibcon#wrote, iclass 12, count 0 2006.252.07:50:02.29#ibcon#about to read 3, iclass 12, count 0 2006.252.07:50:02.33#ibcon#read 3, iclass 12, count 0 2006.252.07:50:02.33#ibcon#about to read 4, iclass 12, count 0 2006.252.07:50:02.33#ibcon#read 4, iclass 12, count 0 2006.252.07:50:02.33#ibcon#about to read 5, iclass 12, count 0 2006.252.07:50:02.33#ibcon#read 5, iclass 12, count 0 2006.252.07:50:02.33#ibcon#about to read 6, iclass 12, count 0 2006.252.07:50:02.33#ibcon#read 6, iclass 12, count 0 2006.252.07:50:02.33#ibcon#end of sib2, iclass 12, count 0 2006.252.07:50:02.33#ibcon#*after write, iclass 12, count 0 2006.252.07:50:02.33#ibcon#*before return 0, iclass 12, count 0 2006.252.07:50:02.33#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.252.07:50:02.33#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.252.07:50:02.33#ibcon#about to clear, iclass 12 cls_cnt 0 2006.252.07:50:02.33#ibcon#cleared, iclass 12 cls_cnt 0 2006.252.07:50:02.33$vc4f8/vb=6,4 2006.252.07:50:02.33#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.252.07:50:02.33#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.252.07:50:02.33#ibcon#ireg 11 cls_cnt 2 2006.252.07:50:02.33#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.252.07:50:02.39#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.252.07:50:02.39#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.252.07:50:02.39#ibcon#enter wrdev, iclass 14, count 2 2006.252.07:50:02.39#ibcon#first serial, iclass 14, count 2 2006.252.07:50:02.39#ibcon#enter sib2, iclass 14, count 2 2006.252.07:50:02.39#ibcon#flushed, iclass 14, count 2 2006.252.07:50:02.39#ibcon#about to write, iclass 14, count 2 2006.252.07:50:02.39#ibcon#wrote, iclass 14, count 2 2006.252.07:50:02.39#ibcon#about to read 3, iclass 14, count 2 2006.252.07:50:02.41#ibcon#read 3, iclass 14, count 2 2006.252.07:50:02.41#ibcon#about to read 4, iclass 14, count 2 2006.252.07:50:02.41#ibcon#read 4, iclass 14, count 2 2006.252.07:50:02.41#ibcon#about to read 5, iclass 14, count 2 2006.252.07:50:02.41#ibcon#read 5, iclass 14, count 2 2006.252.07:50:02.41#ibcon#about to read 6, iclass 14, count 2 2006.252.07:50:02.41#ibcon#read 6, iclass 14, count 2 2006.252.07:50:02.41#ibcon#end of sib2, iclass 14, count 2 2006.252.07:50:02.41#ibcon#*mode == 0, iclass 14, count 2 2006.252.07:50:02.41#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.252.07:50:02.41#ibcon#[27=AT06-04\r\n] 2006.252.07:50:02.41#ibcon#*before write, iclass 14, count 2 2006.252.07:50:02.41#ibcon#enter sib2, iclass 14, count 2 2006.252.07:50:02.41#ibcon#flushed, iclass 14, count 2 2006.252.07:50:02.41#ibcon#about to write, iclass 14, count 2 2006.252.07:50:02.41#ibcon#wrote, iclass 14, count 2 2006.252.07:50:02.41#ibcon#about to read 3, iclass 14, count 2 2006.252.07:50:02.44#ibcon#read 3, iclass 14, count 2 2006.252.07:50:02.44#ibcon#about to read 4, iclass 14, count 2 2006.252.07:50:02.44#ibcon#read 4, iclass 14, count 2 2006.252.07:50:02.44#ibcon#about to read 5, iclass 14, count 2 2006.252.07:50:02.44#ibcon#read 5, iclass 14, count 2 2006.252.07:50:02.44#ibcon#about to read 6, iclass 14, count 2 2006.252.07:50:02.44#ibcon#read 6, iclass 14, count 2 2006.252.07:50:02.44#ibcon#end of sib2, iclass 14, count 2 2006.252.07:50:02.44#ibcon#*after write, iclass 14, count 2 2006.252.07:50:02.44#ibcon#*before return 0, iclass 14, count 2 2006.252.07:50:02.44#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.252.07:50:02.44#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.252.07:50:02.44#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.252.07:50:02.44#ibcon#ireg 7 cls_cnt 0 2006.252.07:50:02.44#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.252.07:50:02.56#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.252.07:50:02.56#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.252.07:50:02.56#ibcon#enter wrdev, iclass 14, count 0 2006.252.07:50:02.56#ibcon#first serial, iclass 14, count 0 2006.252.07:50:02.56#ibcon#enter sib2, iclass 14, count 0 2006.252.07:50:02.56#ibcon#flushed, iclass 14, count 0 2006.252.07:50:02.56#ibcon#about to write, iclass 14, count 0 2006.252.07:50:02.56#ibcon#wrote, iclass 14, count 0 2006.252.07:50:02.56#ibcon#about to read 3, iclass 14, count 0 2006.252.07:50:02.58#ibcon#read 3, iclass 14, count 0 2006.252.07:50:02.58#ibcon#about to read 4, iclass 14, count 0 2006.252.07:50:02.58#ibcon#read 4, iclass 14, count 0 2006.252.07:50:02.58#ibcon#about to read 5, iclass 14, count 0 2006.252.07:50:02.58#ibcon#read 5, iclass 14, count 0 2006.252.07:50:02.58#ibcon#about to read 6, iclass 14, count 0 2006.252.07:50:02.58#ibcon#read 6, iclass 14, count 0 2006.252.07:50:02.58#ibcon#end of sib2, iclass 14, count 0 2006.252.07:50:02.58#ibcon#*mode == 0, iclass 14, count 0 2006.252.07:50:02.58#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.252.07:50:02.58#ibcon#[27=USB\r\n] 2006.252.07:50:02.58#ibcon#*before write, iclass 14, count 0 2006.252.07:50:02.58#ibcon#enter sib2, iclass 14, count 0 2006.252.07:50:02.58#ibcon#flushed, iclass 14, count 0 2006.252.07:50:02.58#ibcon#about to write, iclass 14, count 0 2006.252.07:50:02.58#ibcon#wrote, iclass 14, count 0 2006.252.07:50:02.58#ibcon#about to read 3, iclass 14, count 0 2006.252.07:50:02.61#ibcon#read 3, iclass 14, count 0 2006.252.07:50:02.61#ibcon#about to read 4, iclass 14, count 0 2006.252.07:50:02.61#ibcon#read 4, iclass 14, count 0 2006.252.07:50:02.61#ibcon#about to read 5, iclass 14, count 0 2006.252.07:50:02.61#ibcon#read 5, iclass 14, count 0 2006.252.07:50:02.61#ibcon#about to read 6, iclass 14, count 0 2006.252.07:50:02.61#ibcon#read 6, iclass 14, count 0 2006.252.07:50:02.61#ibcon#end of sib2, iclass 14, count 0 2006.252.07:50:02.61#ibcon#*after write, iclass 14, count 0 2006.252.07:50:02.61#ibcon#*before return 0, iclass 14, count 0 2006.252.07:50:02.61#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.252.07:50:02.61#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.252.07:50:02.61#ibcon#about to clear, iclass 14 cls_cnt 0 2006.252.07:50:02.61#ibcon#cleared, iclass 14 cls_cnt 0 2006.252.07:50:02.61$vc4f8/vabw=wide 2006.252.07:50:02.61#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.252.07:50:02.61#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.252.07:50:02.61#ibcon#ireg 8 cls_cnt 0 2006.252.07:50:02.61#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.252.07:50:02.61#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.252.07:50:02.61#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.252.07:50:02.61#ibcon#enter wrdev, iclass 16, count 0 2006.252.07:50:02.61#ibcon#first serial, iclass 16, count 0 2006.252.07:50:02.61#ibcon#enter sib2, iclass 16, count 0 2006.252.07:50:02.61#ibcon#flushed, iclass 16, count 0 2006.252.07:50:02.61#ibcon#about to write, iclass 16, count 0 2006.252.07:50:02.61#ibcon#wrote, iclass 16, count 0 2006.252.07:50:02.61#ibcon#about to read 3, iclass 16, count 0 2006.252.07:50:02.63#ibcon#read 3, iclass 16, count 0 2006.252.07:50:02.63#ibcon#about to read 4, iclass 16, count 0 2006.252.07:50:02.63#ibcon#read 4, iclass 16, count 0 2006.252.07:50:02.63#ibcon#about to read 5, iclass 16, count 0 2006.252.07:50:02.63#ibcon#read 5, iclass 16, count 0 2006.252.07:50:02.63#ibcon#about to read 6, iclass 16, count 0 2006.252.07:50:02.63#ibcon#read 6, iclass 16, count 0 2006.252.07:50:02.63#ibcon#end of sib2, iclass 16, count 0 2006.252.07:50:02.63#ibcon#*mode == 0, iclass 16, count 0 2006.252.07:50:02.63#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.252.07:50:02.63#ibcon#[25=BW32\r\n] 2006.252.07:50:02.63#ibcon#*before write, iclass 16, count 0 2006.252.07:50:02.63#ibcon#enter sib2, iclass 16, count 0 2006.252.07:50:02.63#ibcon#flushed, iclass 16, count 0 2006.252.07:50:02.63#ibcon#about to write, iclass 16, count 0 2006.252.07:50:02.63#ibcon#wrote, iclass 16, count 0 2006.252.07:50:02.63#ibcon#about to read 3, iclass 16, count 0 2006.252.07:50:02.66#ibcon#read 3, iclass 16, count 0 2006.252.07:50:02.66#ibcon#about to read 4, iclass 16, count 0 2006.252.07:50:02.66#ibcon#read 4, iclass 16, count 0 2006.252.07:50:02.66#ibcon#about to read 5, iclass 16, count 0 2006.252.07:50:02.66#ibcon#read 5, iclass 16, count 0 2006.252.07:50:02.66#ibcon#about to read 6, iclass 16, count 0 2006.252.07:50:02.66#ibcon#read 6, iclass 16, count 0 2006.252.07:50:02.66#ibcon#end of sib2, iclass 16, count 0 2006.252.07:50:02.66#ibcon#*after write, iclass 16, count 0 2006.252.07:50:02.66#ibcon#*before return 0, iclass 16, count 0 2006.252.07:50:02.66#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.252.07:50:02.66#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.252.07:50:02.66#ibcon#about to clear, iclass 16 cls_cnt 0 2006.252.07:50:02.66#ibcon#cleared, iclass 16 cls_cnt 0 2006.252.07:50:02.66$vc4f8/vbbw=wide 2006.252.07:50:02.66#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.252.07:50:02.66#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.252.07:50:02.66#ibcon#ireg 8 cls_cnt 0 2006.252.07:50:02.66#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.252.07:50:02.73#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.252.07:50:02.73#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.252.07:50:02.73#ibcon#enter wrdev, iclass 18, count 0 2006.252.07:50:02.73#ibcon#first serial, iclass 18, count 0 2006.252.07:50:02.73#ibcon#enter sib2, iclass 18, count 0 2006.252.07:50:02.73#ibcon#flushed, iclass 18, count 0 2006.252.07:50:02.73#ibcon#about to write, iclass 18, count 0 2006.252.07:50:02.73#ibcon#wrote, iclass 18, count 0 2006.252.07:50:02.73#ibcon#about to read 3, iclass 18, count 0 2006.252.07:50:02.75#ibcon#read 3, iclass 18, count 0 2006.252.07:50:02.75#ibcon#about to read 4, iclass 18, count 0 2006.252.07:50:02.75#ibcon#read 4, iclass 18, count 0 2006.252.07:50:02.75#ibcon#about to read 5, iclass 18, count 0 2006.252.07:50:02.75#ibcon#read 5, iclass 18, count 0 2006.252.07:50:02.75#ibcon#about to read 6, iclass 18, count 0 2006.252.07:50:02.75#ibcon#read 6, iclass 18, count 0 2006.252.07:50:02.75#ibcon#end of sib2, iclass 18, count 0 2006.252.07:50:02.75#ibcon#*mode == 0, iclass 18, count 0 2006.252.07:50:02.75#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.252.07:50:02.75#ibcon#[27=BW32\r\n] 2006.252.07:50:02.75#ibcon#*before write, iclass 18, count 0 2006.252.07:50:02.75#ibcon#enter sib2, iclass 18, count 0 2006.252.07:50:02.75#ibcon#flushed, iclass 18, count 0 2006.252.07:50:02.75#ibcon#about to write, iclass 18, count 0 2006.252.07:50:02.75#ibcon#wrote, iclass 18, count 0 2006.252.07:50:02.75#ibcon#about to read 3, iclass 18, count 0 2006.252.07:50:02.78#ibcon#read 3, iclass 18, count 0 2006.252.07:50:02.78#ibcon#about to read 4, iclass 18, count 0 2006.252.07:50:02.78#ibcon#read 4, iclass 18, count 0 2006.252.07:50:02.78#ibcon#about to read 5, iclass 18, count 0 2006.252.07:50:02.78#ibcon#read 5, iclass 18, count 0 2006.252.07:50:02.78#ibcon#about to read 6, iclass 18, count 0 2006.252.07:50:02.78#ibcon#read 6, iclass 18, count 0 2006.252.07:50:02.78#ibcon#end of sib2, iclass 18, count 0 2006.252.07:50:02.78#ibcon#*after write, iclass 18, count 0 2006.252.07:50:02.78#ibcon#*before return 0, iclass 18, count 0 2006.252.07:50:02.78#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.252.07:50:02.78#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.252.07:50:02.78#ibcon#about to clear, iclass 18 cls_cnt 0 2006.252.07:50:02.78#ibcon#cleared, iclass 18 cls_cnt 0 2006.252.07:50:02.78$4f8m12a/ifd4f 2006.252.07:50:02.78$ifd4f/lo= 2006.252.07:50:02.78$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.252.07:50:02.78$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.252.07:50:02.78$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.252.07:50:02.78$ifd4f/patch= 2006.252.07:50:02.78$ifd4f/patch=lo1,a1,a2,a3,a4 2006.252.07:50:02.78$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.252.07:50:02.78$ifd4f/patch=lo3,a5,a6,a7,a8 2006.252.07:50:02.78$4f8m12a/"form=m,16.000,1:2 2006.252.07:50:02.78$4f8m12a/"tpicd 2006.252.07:50:02.78$4f8m12a/echo=off 2006.252.07:50:02.78$4f8m12a/xlog=off 2006.252.07:50:02.78:!2006.252.07:50:30 2006.252.07:50:17.14#trakl#Source acquired 2006.252.07:50:18.14#flagr#flagr/antenna,acquired 2006.252.07:50:30.00:preob 2006.252.07:50:31.14/onsource/TRACKING 2006.252.07:50:31.14:!2006.252.07:50:40 2006.252.07:50:40.00:data_valid=on 2006.252.07:50:40.00:midob 2006.252.07:50:40.14/onsource/TRACKING 2006.252.07:50:40.14/wx/27.39,1011.2,90 2006.252.07:50:40.35/cable/+6.4080E-03 2006.252.07:50:41.44/va/01,08,usb,yes,33,34 2006.252.07:50:41.44/va/02,07,usb,yes,33,34 2006.252.07:50:41.44/va/03,06,usb,yes,35,35 2006.252.07:50:41.44/va/04,07,usb,yes,33,36 2006.252.07:50:41.44/va/05,07,usb,yes,36,39 2006.252.07:50:41.44/va/06,07,usb,yes,32,32 2006.252.07:50:41.44/va/07,07,usb,yes,31,31 2006.252.07:50:41.44/va/08,07,usb,yes,34,34 2006.252.07:50:41.67/valo/01,532.99,yes,locked 2006.252.07:50:41.67/valo/02,572.99,yes,locked 2006.252.07:50:41.67/valo/03,672.99,yes,locked 2006.252.07:50:41.67/valo/04,832.99,yes,locked 2006.252.07:50:41.67/valo/05,652.99,yes,locked 2006.252.07:50:41.67/valo/06,772.99,yes,locked 2006.252.07:50:41.67/valo/07,832.99,yes,locked 2006.252.07:50:41.67/valo/08,852.99,yes,locked 2006.252.07:50:42.76/vb/01,04,usb,yes,31,30 2006.252.07:50:42.76/vb/02,05,usb,yes,29,30 2006.252.07:50:42.76/vb/03,04,usb,yes,29,33 2006.252.07:50:42.76/vb/04,04,usb,yes,30,30 2006.252.07:50:42.76/vb/05,04,usb,yes,28,32 2006.252.07:50:42.76/vb/06,04,usb,yes,29,32 2006.252.07:50:42.76/vb/07,04,usb,yes,31,31 2006.252.07:50:42.76/vb/08,04,usb,yes,29,32 2006.252.07:50:42.99/vblo/01,632.99,yes,locked 2006.252.07:50:42.99/vblo/02,640.99,yes,locked 2006.252.07:50:42.99/vblo/03,656.99,yes,locked 2006.252.07:50:42.99/vblo/04,712.99,yes,locked 2006.252.07:50:42.99/vblo/05,744.99,yes,locked 2006.252.07:50:42.99/vblo/06,752.99,yes,locked 2006.252.07:50:42.99/vblo/07,734.99,yes,locked 2006.252.07:50:42.99/vblo/08,744.99,yes,locked 2006.252.07:50:43.14/vabw/8 2006.252.07:50:43.29/vbbw/8 2006.252.07:50:43.38/xfe/off,on,14.2 2006.252.07:50:43.75/ifatt/23,28,28,28 2006.252.07:50:44.08/fmout-gps/S +4.82E-07 2006.252.07:50:44.16:!2006.252.07:51:50 2006.252.07:51:50.00:data_valid=off 2006.252.07:51:50.00:postob 2006.252.07:51:50.14/cable/+6.4101E-03 2006.252.07:51:50.15/wx/27.39,1011.2,90 2006.252.07:51:51.07/fmout-gps/S +4.82E-07 2006.252.07:51:51.07:scan_name=252-0752,k06252,60 2006.252.07:51:51.08:source=1357+769,135755.37,764321.1,2000.0,ccw 2006.252.07:51:52.14#flagr#flagr/antenna,new-source 2006.252.07:51:52.15:checkk5 2006.252.07:51:52.52/chk_autoobs//k5ts1/ autoobs is running! 2006.252.07:51:52.89/chk_autoobs//k5ts2/ autoobs is running! 2006.252.07:51:53.28/chk_autoobs//k5ts3/ autoobs is running! 2006.252.07:51:53.65/chk_autoobs//k5ts4/ autoobs is running! 2006.252.07:51:54.02/chk_obsdata//k5ts1/T2520750??a.dat file size is correct (nominal:560MB, actual:560MB). 2006.252.07:51:54.39/chk_obsdata//k5ts2/T2520750??b.dat file size is correct (nominal:560MB, actual:560MB). 2006.252.07:51:54.75/chk_obsdata//k5ts3/T2520750??c.dat file size is correct (nominal:560MB, actual:560MB). 2006.252.07:51:55.12/chk_obsdata//k5ts4/T2520750??d.dat file size is correct (nominal:560MB, actual:560MB). 2006.252.07:51:55.82/k5log//k5ts1_log_newline 2006.252.07:51:56.53/k5log//k5ts2_log_newline 2006.252.07:51:57.22/k5log//k5ts3_log_newline 2006.252.07:51:57.91/k5log//k5ts4_log_newline 2006.252.07:51:57.93/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.252.07:51:57.93:4f8m12a=1 2006.252.07:51:57.93$4f8m12a/echo=on 2006.252.07:51:57.93$4f8m12a/pcalon 2006.252.07:51:57.93$pcalon/"no phase cal control is implemented here 2006.252.07:51:57.93$4f8m12a/"tpicd=stop 2006.252.07:51:57.93$4f8m12a/vc4f8 2006.252.07:51:57.93$vc4f8/valo=1,532.99 2006.252.07:51:57.94#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.252.07:51:57.94#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.252.07:51:57.94#ibcon#ireg 17 cls_cnt 0 2006.252.07:51:57.94#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.252.07:51:57.94#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.252.07:51:57.94#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.252.07:51:57.94#ibcon#enter wrdev, iclass 33, count 0 2006.252.07:51:57.94#ibcon#first serial, iclass 33, count 0 2006.252.07:51:57.94#ibcon#enter sib2, iclass 33, count 0 2006.252.07:51:57.94#ibcon#flushed, iclass 33, count 0 2006.252.07:51:57.94#ibcon#about to write, iclass 33, count 0 2006.252.07:51:57.94#ibcon#wrote, iclass 33, count 0 2006.252.07:51:57.94#ibcon#about to read 3, iclass 33, count 0 2006.252.07:51:57.95#ibcon#read 3, iclass 33, count 0 2006.252.07:51:57.95#ibcon#about to read 4, iclass 33, count 0 2006.252.07:51:57.95#ibcon#read 4, iclass 33, count 0 2006.252.07:51:57.95#ibcon#about to read 5, iclass 33, count 0 2006.252.07:51:57.95#ibcon#read 5, iclass 33, count 0 2006.252.07:51:57.95#ibcon#about to read 6, iclass 33, count 0 2006.252.07:51:57.95#ibcon#read 6, iclass 33, count 0 2006.252.07:51:57.95#ibcon#end of sib2, iclass 33, count 0 2006.252.07:51:57.95#ibcon#*mode == 0, iclass 33, count 0 2006.252.07:51:57.95#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.252.07:51:57.95#ibcon#[26=FRQ=01,532.99\r\n] 2006.252.07:51:57.95#ibcon#*before write, iclass 33, count 0 2006.252.07:51:57.95#ibcon#enter sib2, iclass 33, count 0 2006.252.07:51:57.95#ibcon#flushed, iclass 33, count 0 2006.252.07:51:57.95#ibcon#about to write, iclass 33, count 0 2006.252.07:51:57.95#ibcon#wrote, iclass 33, count 0 2006.252.07:51:57.95#ibcon#about to read 3, iclass 33, count 0 2006.252.07:51:58.00#ibcon#read 3, iclass 33, count 0 2006.252.07:51:58.00#ibcon#about to read 4, iclass 33, count 0 2006.252.07:51:58.00#ibcon#read 4, iclass 33, count 0 2006.252.07:51:58.00#ibcon#about to read 5, iclass 33, count 0 2006.252.07:51:58.00#ibcon#read 5, iclass 33, count 0 2006.252.07:51:58.00#ibcon#about to read 6, iclass 33, count 0 2006.252.07:51:58.00#ibcon#read 6, iclass 33, count 0 2006.252.07:51:58.00#ibcon#end of sib2, iclass 33, count 0 2006.252.07:51:58.00#ibcon#*after write, iclass 33, count 0 2006.252.07:51:58.00#ibcon#*before return 0, iclass 33, count 0 2006.252.07:51:58.00#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.252.07:51:58.00#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.252.07:51:58.00#ibcon#about to clear, iclass 33 cls_cnt 0 2006.252.07:51:58.00#ibcon#cleared, iclass 33 cls_cnt 0 2006.252.07:51:58.00$vc4f8/va=1,8 2006.252.07:51:58.00#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.252.07:51:58.00#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.252.07:51:58.00#ibcon#ireg 11 cls_cnt 2 2006.252.07:51:58.00#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.252.07:51:58.00#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.252.07:51:58.00#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.252.07:51:58.00#ibcon#enter wrdev, iclass 35, count 2 2006.252.07:51:58.00#ibcon#first serial, iclass 35, count 2 2006.252.07:51:58.00#ibcon#enter sib2, iclass 35, count 2 2006.252.07:51:58.00#ibcon#flushed, iclass 35, count 2 2006.252.07:51:58.00#ibcon#about to write, iclass 35, count 2 2006.252.07:51:58.00#ibcon#wrote, iclass 35, count 2 2006.252.07:51:58.00#ibcon#about to read 3, iclass 35, count 2 2006.252.07:51:58.02#ibcon#read 3, iclass 35, count 2 2006.252.07:51:58.02#ibcon#about to read 4, iclass 35, count 2 2006.252.07:51:58.02#ibcon#read 4, iclass 35, count 2 2006.252.07:51:58.02#ibcon#about to read 5, iclass 35, count 2 2006.252.07:51:58.02#ibcon#read 5, iclass 35, count 2 2006.252.07:51:58.02#ibcon#about to read 6, iclass 35, count 2 2006.252.07:51:58.02#ibcon#read 6, iclass 35, count 2 2006.252.07:51:58.02#ibcon#end of sib2, iclass 35, count 2 2006.252.07:51:58.02#ibcon#*mode == 0, iclass 35, count 2 2006.252.07:51:58.02#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.252.07:51:58.02#ibcon#[25=AT01-08\r\n] 2006.252.07:51:58.02#ibcon#*before write, iclass 35, count 2 2006.252.07:51:58.02#ibcon#enter sib2, iclass 35, count 2 2006.252.07:51:58.02#ibcon#flushed, iclass 35, count 2 2006.252.07:51:58.02#ibcon#about to write, iclass 35, count 2 2006.252.07:51:58.02#ibcon#wrote, iclass 35, count 2 2006.252.07:51:58.02#ibcon#about to read 3, iclass 35, count 2 2006.252.07:51:58.05#ibcon#read 3, iclass 35, count 2 2006.252.07:51:58.05#ibcon#about to read 4, iclass 35, count 2 2006.252.07:51:58.05#ibcon#read 4, iclass 35, count 2 2006.252.07:51:58.05#ibcon#about to read 5, iclass 35, count 2 2006.252.07:51:58.05#ibcon#read 5, iclass 35, count 2 2006.252.07:51:58.05#ibcon#about to read 6, iclass 35, count 2 2006.252.07:51:58.05#ibcon#read 6, iclass 35, count 2 2006.252.07:51:58.05#ibcon#end of sib2, iclass 35, count 2 2006.252.07:51:58.05#ibcon#*after write, iclass 35, count 2 2006.252.07:51:58.05#ibcon#*before return 0, iclass 35, count 2 2006.252.07:51:58.05#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.252.07:51:58.05#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.252.07:51:58.05#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.252.07:51:58.05#ibcon#ireg 7 cls_cnt 0 2006.252.07:51:58.05#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.252.07:51:58.17#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.252.07:51:58.17#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.252.07:51:58.17#ibcon#enter wrdev, iclass 35, count 0 2006.252.07:51:58.17#ibcon#first serial, iclass 35, count 0 2006.252.07:51:58.17#ibcon#enter sib2, iclass 35, count 0 2006.252.07:51:58.17#ibcon#flushed, iclass 35, count 0 2006.252.07:51:58.17#ibcon#about to write, iclass 35, count 0 2006.252.07:51:58.17#ibcon#wrote, iclass 35, count 0 2006.252.07:51:58.17#ibcon#about to read 3, iclass 35, count 0 2006.252.07:51:58.19#ibcon#read 3, iclass 35, count 0 2006.252.07:51:58.19#ibcon#about to read 4, iclass 35, count 0 2006.252.07:51:58.19#ibcon#read 4, iclass 35, count 0 2006.252.07:51:58.19#ibcon#about to read 5, iclass 35, count 0 2006.252.07:51:58.19#ibcon#read 5, iclass 35, count 0 2006.252.07:51:58.19#ibcon#about to read 6, iclass 35, count 0 2006.252.07:51:58.19#ibcon#read 6, iclass 35, count 0 2006.252.07:51:58.19#ibcon#end of sib2, iclass 35, count 0 2006.252.07:51:58.19#ibcon#*mode == 0, iclass 35, count 0 2006.252.07:51:58.19#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.252.07:51:58.19#ibcon#[25=USB\r\n] 2006.252.07:51:58.19#ibcon#*before write, iclass 35, count 0 2006.252.07:51:58.19#ibcon#enter sib2, iclass 35, count 0 2006.252.07:51:58.19#ibcon#flushed, iclass 35, count 0 2006.252.07:51:58.19#ibcon#about to write, iclass 35, count 0 2006.252.07:51:58.19#ibcon#wrote, iclass 35, count 0 2006.252.07:51:58.19#ibcon#about to read 3, iclass 35, count 0 2006.252.07:51:58.22#ibcon#read 3, iclass 35, count 0 2006.252.07:51:58.22#ibcon#about to read 4, iclass 35, count 0 2006.252.07:51:58.22#ibcon#read 4, iclass 35, count 0 2006.252.07:51:58.22#ibcon#about to read 5, iclass 35, count 0 2006.252.07:51:58.22#ibcon#read 5, iclass 35, count 0 2006.252.07:51:58.22#ibcon#about to read 6, iclass 35, count 0 2006.252.07:51:58.22#ibcon#read 6, iclass 35, count 0 2006.252.07:51:58.22#ibcon#end of sib2, iclass 35, count 0 2006.252.07:51:58.22#ibcon#*after write, iclass 35, count 0 2006.252.07:51:58.22#ibcon#*before return 0, iclass 35, count 0 2006.252.07:51:58.22#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.252.07:51:58.22#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.252.07:51:58.22#ibcon#about to clear, iclass 35 cls_cnt 0 2006.252.07:51:58.22#ibcon#cleared, iclass 35 cls_cnt 0 2006.252.07:51:58.22$vc4f8/valo=2,572.99 2006.252.07:51:58.22#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.252.07:51:58.22#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.252.07:51:58.22#ibcon#ireg 17 cls_cnt 0 2006.252.07:51:58.22#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.252.07:51:58.22#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.252.07:51:58.22#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.252.07:51:58.22#ibcon#enter wrdev, iclass 37, count 0 2006.252.07:51:58.22#ibcon#first serial, iclass 37, count 0 2006.252.07:51:58.22#ibcon#enter sib2, iclass 37, count 0 2006.252.07:51:58.22#ibcon#flushed, iclass 37, count 0 2006.252.07:51:58.22#ibcon#about to write, iclass 37, count 0 2006.252.07:51:58.22#ibcon#wrote, iclass 37, count 0 2006.252.07:51:58.22#ibcon#about to read 3, iclass 37, count 0 2006.252.07:51:58.24#ibcon#read 3, iclass 37, count 0 2006.252.07:51:58.24#ibcon#about to read 4, iclass 37, count 0 2006.252.07:51:58.24#ibcon#read 4, iclass 37, count 0 2006.252.07:51:58.24#ibcon#about to read 5, iclass 37, count 0 2006.252.07:51:58.24#ibcon#read 5, iclass 37, count 0 2006.252.07:51:58.24#ibcon#about to read 6, iclass 37, count 0 2006.252.07:51:58.24#ibcon#read 6, iclass 37, count 0 2006.252.07:51:58.24#ibcon#end of sib2, iclass 37, count 0 2006.252.07:51:58.24#ibcon#*mode == 0, iclass 37, count 0 2006.252.07:51:58.24#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.252.07:51:58.24#ibcon#[26=FRQ=02,572.99\r\n] 2006.252.07:51:58.24#ibcon#*before write, iclass 37, count 0 2006.252.07:51:58.24#ibcon#enter sib2, iclass 37, count 0 2006.252.07:51:58.24#ibcon#flushed, iclass 37, count 0 2006.252.07:51:58.24#ibcon#about to write, iclass 37, count 0 2006.252.07:51:58.24#ibcon#wrote, iclass 37, count 0 2006.252.07:51:58.24#ibcon#about to read 3, iclass 37, count 0 2006.252.07:51:58.28#ibcon#read 3, iclass 37, count 0 2006.252.07:51:58.28#ibcon#about to read 4, iclass 37, count 0 2006.252.07:51:58.28#ibcon#read 4, iclass 37, count 0 2006.252.07:51:58.28#ibcon#about to read 5, iclass 37, count 0 2006.252.07:51:58.28#ibcon#read 5, iclass 37, count 0 2006.252.07:51:58.28#ibcon#about to read 6, iclass 37, count 0 2006.252.07:51:58.28#ibcon#read 6, iclass 37, count 0 2006.252.07:51:58.28#ibcon#end of sib2, iclass 37, count 0 2006.252.07:51:58.28#ibcon#*after write, iclass 37, count 0 2006.252.07:51:58.28#ibcon#*before return 0, iclass 37, count 0 2006.252.07:51:58.28#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.252.07:51:58.28#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.252.07:51:58.28#ibcon#about to clear, iclass 37 cls_cnt 0 2006.252.07:51:58.28#ibcon#cleared, iclass 37 cls_cnt 0 2006.252.07:51:58.28$vc4f8/va=2,7 2006.252.07:51:58.28#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.252.07:51:58.28#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.252.07:51:58.28#ibcon#ireg 11 cls_cnt 2 2006.252.07:51:58.28#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.252.07:51:58.34#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.252.07:51:58.34#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.252.07:51:58.34#ibcon#enter wrdev, iclass 39, count 2 2006.252.07:51:58.34#ibcon#first serial, iclass 39, count 2 2006.252.07:51:58.34#ibcon#enter sib2, iclass 39, count 2 2006.252.07:51:58.34#ibcon#flushed, iclass 39, count 2 2006.252.07:51:58.34#ibcon#about to write, iclass 39, count 2 2006.252.07:51:58.34#ibcon#wrote, iclass 39, count 2 2006.252.07:51:58.34#ibcon#about to read 3, iclass 39, count 2 2006.252.07:51:58.37#ibcon#read 3, iclass 39, count 2 2006.252.07:51:58.37#ibcon#about to read 4, iclass 39, count 2 2006.252.07:51:58.37#ibcon#read 4, iclass 39, count 2 2006.252.07:51:58.37#ibcon#about to read 5, iclass 39, count 2 2006.252.07:51:58.37#ibcon#read 5, iclass 39, count 2 2006.252.07:51:58.37#ibcon#about to read 6, iclass 39, count 2 2006.252.07:51:58.37#ibcon#read 6, iclass 39, count 2 2006.252.07:51:58.37#ibcon#end of sib2, iclass 39, count 2 2006.252.07:51:58.37#ibcon#*mode == 0, iclass 39, count 2 2006.252.07:51:58.37#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.252.07:51:58.37#ibcon#[25=AT02-07\r\n] 2006.252.07:51:58.37#ibcon#*before write, iclass 39, count 2 2006.252.07:51:58.37#ibcon#enter sib2, iclass 39, count 2 2006.252.07:51:58.37#ibcon#flushed, iclass 39, count 2 2006.252.07:51:58.37#ibcon#about to write, iclass 39, count 2 2006.252.07:51:58.37#ibcon#wrote, iclass 39, count 2 2006.252.07:51:58.37#ibcon#about to read 3, iclass 39, count 2 2006.252.07:51:58.40#ibcon#read 3, iclass 39, count 2 2006.252.07:51:58.40#ibcon#about to read 4, iclass 39, count 2 2006.252.07:51:58.40#ibcon#read 4, iclass 39, count 2 2006.252.07:51:58.40#ibcon#about to read 5, iclass 39, count 2 2006.252.07:51:58.40#ibcon#read 5, iclass 39, count 2 2006.252.07:51:58.40#ibcon#about to read 6, iclass 39, count 2 2006.252.07:51:58.40#ibcon#read 6, iclass 39, count 2 2006.252.07:51:58.40#ibcon#end of sib2, iclass 39, count 2 2006.252.07:51:58.40#ibcon#*after write, iclass 39, count 2 2006.252.07:51:58.40#ibcon#*before return 0, iclass 39, count 2 2006.252.07:51:58.40#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.252.07:51:58.40#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.252.07:51:58.40#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.252.07:51:58.40#ibcon#ireg 7 cls_cnt 0 2006.252.07:51:58.40#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.252.07:51:58.52#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.252.07:51:58.52#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.252.07:51:58.52#ibcon#enter wrdev, iclass 39, count 0 2006.252.07:51:58.52#ibcon#first serial, iclass 39, count 0 2006.252.07:51:58.52#ibcon#enter sib2, iclass 39, count 0 2006.252.07:51:58.52#ibcon#flushed, iclass 39, count 0 2006.252.07:51:58.52#ibcon#about to write, iclass 39, count 0 2006.252.07:51:58.52#ibcon#wrote, iclass 39, count 0 2006.252.07:51:58.52#ibcon#about to read 3, iclass 39, count 0 2006.252.07:51:58.54#ibcon#read 3, iclass 39, count 0 2006.252.07:51:58.54#ibcon#about to read 4, iclass 39, count 0 2006.252.07:51:58.54#ibcon#read 4, iclass 39, count 0 2006.252.07:51:58.54#ibcon#about to read 5, iclass 39, count 0 2006.252.07:51:58.54#ibcon#read 5, iclass 39, count 0 2006.252.07:51:58.54#ibcon#about to read 6, iclass 39, count 0 2006.252.07:51:58.54#ibcon#read 6, iclass 39, count 0 2006.252.07:51:58.54#ibcon#end of sib2, iclass 39, count 0 2006.252.07:51:58.54#ibcon#*mode == 0, iclass 39, count 0 2006.252.07:51:58.54#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.252.07:51:58.54#ibcon#[25=USB\r\n] 2006.252.07:51:58.54#ibcon#*before write, iclass 39, count 0 2006.252.07:51:58.54#ibcon#enter sib2, iclass 39, count 0 2006.252.07:51:58.54#ibcon#flushed, iclass 39, count 0 2006.252.07:51:58.54#ibcon#about to write, iclass 39, count 0 2006.252.07:51:58.54#ibcon#wrote, iclass 39, count 0 2006.252.07:51:58.54#ibcon#about to read 3, iclass 39, count 0 2006.252.07:51:58.57#ibcon#read 3, iclass 39, count 0 2006.252.07:51:58.57#ibcon#about to read 4, iclass 39, count 0 2006.252.07:51:58.57#ibcon#read 4, iclass 39, count 0 2006.252.07:51:58.57#ibcon#about to read 5, iclass 39, count 0 2006.252.07:51:58.57#ibcon#read 5, iclass 39, count 0 2006.252.07:51:58.57#ibcon#about to read 6, iclass 39, count 0 2006.252.07:51:58.57#ibcon#read 6, iclass 39, count 0 2006.252.07:51:58.57#ibcon#end of sib2, iclass 39, count 0 2006.252.07:51:58.57#ibcon#*after write, iclass 39, count 0 2006.252.07:51:58.57#ibcon#*before return 0, iclass 39, count 0 2006.252.07:51:58.57#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.252.07:51:58.57#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.252.07:51:58.57#ibcon#about to clear, iclass 39 cls_cnt 0 2006.252.07:51:58.57#ibcon#cleared, iclass 39 cls_cnt 0 2006.252.07:51:58.57$vc4f8/valo=3,672.99 2006.252.07:51:58.57#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.252.07:51:58.57#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.252.07:51:58.57#ibcon#ireg 17 cls_cnt 0 2006.252.07:51:58.57#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.252.07:51:58.57#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.252.07:51:58.57#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.252.07:51:58.57#ibcon#enter wrdev, iclass 3, count 0 2006.252.07:51:58.57#ibcon#first serial, iclass 3, count 0 2006.252.07:51:58.57#ibcon#enter sib2, iclass 3, count 0 2006.252.07:51:58.57#ibcon#flushed, iclass 3, count 0 2006.252.07:51:58.57#ibcon#about to write, iclass 3, count 0 2006.252.07:51:58.57#ibcon#wrote, iclass 3, count 0 2006.252.07:51:58.57#ibcon#about to read 3, iclass 3, count 0 2006.252.07:51:58.60#ibcon#read 3, iclass 3, count 0 2006.252.07:51:58.60#ibcon#about to read 4, iclass 3, count 0 2006.252.07:51:58.60#ibcon#read 4, iclass 3, count 0 2006.252.07:51:58.60#ibcon#about to read 5, iclass 3, count 0 2006.252.07:51:58.60#ibcon#read 5, iclass 3, count 0 2006.252.07:51:58.60#ibcon#about to read 6, iclass 3, count 0 2006.252.07:51:58.60#ibcon#read 6, iclass 3, count 0 2006.252.07:51:58.60#ibcon#end of sib2, iclass 3, count 0 2006.252.07:51:58.60#ibcon#*mode == 0, iclass 3, count 0 2006.252.07:51:58.60#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.252.07:51:58.60#ibcon#[26=FRQ=03,672.99\r\n] 2006.252.07:51:58.60#ibcon#*before write, iclass 3, count 0 2006.252.07:51:58.60#ibcon#enter sib2, iclass 3, count 0 2006.252.07:51:58.60#ibcon#flushed, iclass 3, count 0 2006.252.07:51:58.60#ibcon#about to write, iclass 3, count 0 2006.252.07:51:58.60#ibcon#wrote, iclass 3, count 0 2006.252.07:51:58.60#ibcon#about to read 3, iclass 3, count 0 2006.252.07:51:58.64#ibcon#read 3, iclass 3, count 0 2006.252.07:51:58.64#ibcon#about to read 4, iclass 3, count 0 2006.252.07:51:58.64#ibcon#read 4, iclass 3, count 0 2006.252.07:51:58.64#ibcon#about to read 5, iclass 3, count 0 2006.252.07:51:58.64#ibcon#read 5, iclass 3, count 0 2006.252.07:51:58.64#ibcon#about to read 6, iclass 3, count 0 2006.252.07:51:58.64#ibcon#read 6, iclass 3, count 0 2006.252.07:51:58.64#ibcon#end of sib2, iclass 3, count 0 2006.252.07:51:58.64#ibcon#*after write, iclass 3, count 0 2006.252.07:51:58.64#ibcon#*before return 0, iclass 3, count 0 2006.252.07:51:58.64#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.252.07:51:58.64#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.252.07:51:58.64#ibcon#about to clear, iclass 3 cls_cnt 0 2006.252.07:51:58.64#ibcon#cleared, iclass 3 cls_cnt 0 2006.252.07:51:58.64$vc4f8/va=3,6 2006.252.07:51:58.64#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.252.07:51:58.64#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.252.07:51:58.64#ibcon#ireg 11 cls_cnt 2 2006.252.07:51:58.64#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.252.07:51:58.69#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.252.07:51:58.69#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.252.07:51:58.69#ibcon#enter wrdev, iclass 5, count 2 2006.252.07:51:58.69#ibcon#first serial, iclass 5, count 2 2006.252.07:51:58.69#ibcon#enter sib2, iclass 5, count 2 2006.252.07:51:58.69#ibcon#flushed, iclass 5, count 2 2006.252.07:51:58.69#ibcon#about to write, iclass 5, count 2 2006.252.07:51:58.69#ibcon#wrote, iclass 5, count 2 2006.252.07:51:58.69#ibcon#about to read 3, iclass 5, count 2 2006.252.07:51:58.71#ibcon#read 3, iclass 5, count 2 2006.252.07:51:58.71#ibcon#about to read 4, iclass 5, count 2 2006.252.07:51:58.71#ibcon#read 4, iclass 5, count 2 2006.252.07:51:58.71#ibcon#about to read 5, iclass 5, count 2 2006.252.07:51:58.71#ibcon#read 5, iclass 5, count 2 2006.252.07:51:58.71#ibcon#about to read 6, iclass 5, count 2 2006.252.07:51:58.71#ibcon#read 6, iclass 5, count 2 2006.252.07:51:58.71#ibcon#end of sib2, iclass 5, count 2 2006.252.07:51:58.71#ibcon#*mode == 0, iclass 5, count 2 2006.252.07:51:58.71#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.252.07:51:58.71#ibcon#[25=AT03-06\r\n] 2006.252.07:51:58.71#ibcon#*before write, iclass 5, count 2 2006.252.07:51:58.71#ibcon#enter sib2, iclass 5, count 2 2006.252.07:51:58.71#ibcon#flushed, iclass 5, count 2 2006.252.07:51:58.71#ibcon#about to write, iclass 5, count 2 2006.252.07:51:58.71#ibcon#wrote, iclass 5, count 2 2006.252.07:51:58.71#ibcon#about to read 3, iclass 5, count 2 2006.252.07:51:58.74#ibcon#read 3, iclass 5, count 2 2006.252.07:51:58.74#ibcon#about to read 4, iclass 5, count 2 2006.252.07:51:58.74#ibcon#read 4, iclass 5, count 2 2006.252.07:51:58.74#ibcon#about to read 5, iclass 5, count 2 2006.252.07:51:58.74#ibcon#read 5, iclass 5, count 2 2006.252.07:51:58.74#ibcon#about to read 6, iclass 5, count 2 2006.252.07:51:58.74#ibcon#read 6, iclass 5, count 2 2006.252.07:51:58.74#ibcon#end of sib2, iclass 5, count 2 2006.252.07:51:58.74#ibcon#*after write, iclass 5, count 2 2006.252.07:51:58.74#ibcon#*before return 0, iclass 5, count 2 2006.252.07:51:58.74#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.252.07:51:58.74#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.252.07:51:58.74#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.252.07:51:58.74#ibcon#ireg 7 cls_cnt 0 2006.252.07:51:58.74#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.252.07:51:58.86#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.252.07:51:58.86#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.252.07:51:58.86#ibcon#enter wrdev, iclass 5, count 0 2006.252.07:51:58.86#ibcon#first serial, iclass 5, count 0 2006.252.07:51:58.86#ibcon#enter sib2, iclass 5, count 0 2006.252.07:51:58.86#ibcon#flushed, iclass 5, count 0 2006.252.07:51:58.86#ibcon#about to write, iclass 5, count 0 2006.252.07:51:58.86#ibcon#wrote, iclass 5, count 0 2006.252.07:51:58.86#ibcon#about to read 3, iclass 5, count 0 2006.252.07:51:58.88#ibcon#read 3, iclass 5, count 0 2006.252.07:51:58.88#ibcon#about to read 4, iclass 5, count 0 2006.252.07:51:58.88#ibcon#read 4, iclass 5, count 0 2006.252.07:51:58.88#ibcon#about to read 5, iclass 5, count 0 2006.252.07:51:58.88#ibcon#read 5, iclass 5, count 0 2006.252.07:51:58.88#ibcon#about to read 6, iclass 5, count 0 2006.252.07:51:58.88#ibcon#read 6, iclass 5, count 0 2006.252.07:51:58.88#ibcon#end of sib2, iclass 5, count 0 2006.252.07:51:58.88#ibcon#*mode == 0, iclass 5, count 0 2006.252.07:51:58.88#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.252.07:51:58.88#ibcon#[25=USB\r\n] 2006.252.07:51:58.88#ibcon#*before write, iclass 5, count 0 2006.252.07:51:58.88#ibcon#enter sib2, iclass 5, count 0 2006.252.07:51:58.88#ibcon#flushed, iclass 5, count 0 2006.252.07:51:58.88#ibcon#about to write, iclass 5, count 0 2006.252.07:51:58.88#ibcon#wrote, iclass 5, count 0 2006.252.07:51:58.88#ibcon#about to read 3, iclass 5, count 0 2006.252.07:51:58.91#ibcon#read 3, iclass 5, count 0 2006.252.07:51:58.91#ibcon#about to read 4, iclass 5, count 0 2006.252.07:51:58.91#ibcon#read 4, iclass 5, count 0 2006.252.07:51:58.91#ibcon#about to read 5, iclass 5, count 0 2006.252.07:51:58.91#ibcon#read 5, iclass 5, count 0 2006.252.07:51:58.91#ibcon#about to read 6, iclass 5, count 0 2006.252.07:51:58.91#ibcon#read 6, iclass 5, count 0 2006.252.07:51:58.91#ibcon#end of sib2, iclass 5, count 0 2006.252.07:51:58.91#ibcon#*after write, iclass 5, count 0 2006.252.07:51:58.91#ibcon#*before return 0, iclass 5, count 0 2006.252.07:51:58.91#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.252.07:51:58.91#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.252.07:51:58.91#ibcon#about to clear, iclass 5 cls_cnt 0 2006.252.07:51:58.91#ibcon#cleared, iclass 5 cls_cnt 0 2006.252.07:51:58.91$vc4f8/valo=4,832.99 2006.252.07:51:58.91#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.252.07:51:58.91#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.252.07:51:58.91#ibcon#ireg 17 cls_cnt 0 2006.252.07:51:58.91#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.252.07:51:58.91#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.252.07:51:58.91#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.252.07:51:58.91#ibcon#enter wrdev, iclass 7, count 0 2006.252.07:51:58.91#ibcon#first serial, iclass 7, count 0 2006.252.07:51:58.91#ibcon#enter sib2, iclass 7, count 0 2006.252.07:51:58.91#ibcon#flushed, iclass 7, count 0 2006.252.07:51:58.91#ibcon#about to write, iclass 7, count 0 2006.252.07:51:58.91#ibcon#wrote, iclass 7, count 0 2006.252.07:51:58.91#ibcon#about to read 3, iclass 7, count 0 2006.252.07:51:58.93#ibcon#read 3, iclass 7, count 0 2006.252.07:51:58.93#ibcon#about to read 4, iclass 7, count 0 2006.252.07:51:58.93#ibcon#read 4, iclass 7, count 0 2006.252.07:51:58.93#ibcon#about to read 5, iclass 7, count 0 2006.252.07:51:58.93#ibcon#read 5, iclass 7, count 0 2006.252.07:51:58.93#ibcon#about to read 6, iclass 7, count 0 2006.252.07:51:58.93#ibcon#read 6, iclass 7, count 0 2006.252.07:51:58.93#ibcon#end of sib2, iclass 7, count 0 2006.252.07:51:58.93#ibcon#*mode == 0, iclass 7, count 0 2006.252.07:51:58.93#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.252.07:51:58.93#ibcon#[26=FRQ=04,832.99\r\n] 2006.252.07:51:58.93#ibcon#*before write, iclass 7, count 0 2006.252.07:51:58.93#ibcon#enter sib2, iclass 7, count 0 2006.252.07:51:58.93#ibcon#flushed, iclass 7, count 0 2006.252.07:51:58.93#ibcon#about to write, iclass 7, count 0 2006.252.07:51:58.93#ibcon#wrote, iclass 7, count 0 2006.252.07:51:58.93#ibcon#about to read 3, iclass 7, count 0 2006.252.07:51:58.97#ibcon#read 3, iclass 7, count 0 2006.252.07:51:58.97#ibcon#about to read 4, iclass 7, count 0 2006.252.07:51:58.97#ibcon#read 4, iclass 7, count 0 2006.252.07:51:58.97#ibcon#about to read 5, iclass 7, count 0 2006.252.07:51:58.97#ibcon#read 5, iclass 7, count 0 2006.252.07:51:58.97#ibcon#about to read 6, iclass 7, count 0 2006.252.07:51:58.97#ibcon#read 6, iclass 7, count 0 2006.252.07:51:58.97#ibcon#end of sib2, iclass 7, count 0 2006.252.07:51:58.97#ibcon#*after write, iclass 7, count 0 2006.252.07:51:58.97#ibcon#*before return 0, iclass 7, count 0 2006.252.07:51:58.97#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.252.07:51:58.97#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.252.07:51:58.97#ibcon#about to clear, iclass 7 cls_cnt 0 2006.252.07:51:58.97#ibcon#cleared, iclass 7 cls_cnt 0 2006.252.07:51:58.97$vc4f8/va=4,7 2006.252.07:51:58.97#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.252.07:51:58.97#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.252.07:51:58.97#ibcon#ireg 11 cls_cnt 2 2006.252.07:51:58.97#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.252.07:51:59.03#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.252.07:51:59.03#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.252.07:51:59.03#ibcon#enter wrdev, iclass 11, count 2 2006.252.07:51:59.03#ibcon#first serial, iclass 11, count 2 2006.252.07:51:59.03#ibcon#enter sib2, iclass 11, count 2 2006.252.07:51:59.03#ibcon#flushed, iclass 11, count 2 2006.252.07:51:59.03#ibcon#about to write, iclass 11, count 2 2006.252.07:51:59.03#ibcon#wrote, iclass 11, count 2 2006.252.07:51:59.03#ibcon#about to read 3, iclass 11, count 2 2006.252.07:51:59.05#ibcon#read 3, iclass 11, count 2 2006.252.07:51:59.05#ibcon#about to read 4, iclass 11, count 2 2006.252.07:51:59.05#ibcon#read 4, iclass 11, count 2 2006.252.07:51:59.05#ibcon#about to read 5, iclass 11, count 2 2006.252.07:51:59.05#ibcon#read 5, iclass 11, count 2 2006.252.07:51:59.05#ibcon#about to read 6, iclass 11, count 2 2006.252.07:51:59.05#ibcon#read 6, iclass 11, count 2 2006.252.07:51:59.05#ibcon#end of sib2, iclass 11, count 2 2006.252.07:51:59.05#ibcon#*mode == 0, iclass 11, count 2 2006.252.07:51:59.05#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.252.07:51:59.05#ibcon#[25=AT04-07\r\n] 2006.252.07:51:59.05#ibcon#*before write, iclass 11, count 2 2006.252.07:51:59.05#ibcon#enter sib2, iclass 11, count 2 2006.252.07:51:59.05#ibcon#flushed, iclass 11, count 2 2006.252.07:51:59.05#ibcon#about to write, iclass 11, count 2 2006.252.07:51:59.05#ibcon#wrote, iclass 11, count 2 2006.252.07:51:59.05#ibcon#about to read 3, iclass 11, count 2 2006.252.07:51:59.08#ibcon#read 3, iclass 11, count 2 2006.252.07:51:59.08#ibcon#about to read 4, iclass 11, count 2 2006.252.07:51:59.08#ibcon#read 4, iclass 11, count 2 2006.252.07:51:59.08#ibcon#about to read 5, iclass 11, count 2 2006.252.07:51:59.08#ibcon#read 5, iclass 11, count 2 2006.252.07:51:59.08#ibcon#about to read 6, iclass 11, count 2 2006.252.07:51:59.08#ibcon#read 6, iclass 11, count 2 2006.252.07:51:59.08#ibcon#end of sib2, iclass 11, count 2 2006.252.07:51:59.08#ibcon#*after write, iclass 11, count 2 2006.252.07:51:59.08#ibcon#*before return 0, iclass 11, count 2 2006.252.07:51:59.08#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.252.07:51:59.08#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.252.07:51:59.08#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.252.07:51:59.08#ibcon#ireg 7 cls_cnt 0 2006.252.07:51:59.08#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.252.07:51:59.20#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.252.07:51:59.20#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.252.07:51:59.20#ibcon#enter wrdev, iclass 11, count 0 2006.252.07:51:59.20#ibcon#first serial, iclass 11, count 0 2006.252.07:51:59.20#ibcon#enter sib2, iclass 11, count 0 2006.252.07:51:59.20#ibcon#flushed, iclass 11, count 0 2006.252.07:51:59.20#ibcon#about to write, iclass 11, count 0 2006.252.07:51:59.20#ibcon#wrote, iclass 11, count 0 2006.252.07:51:59.20#ibcon#about to read 3, iclass 11, count 0 2006.252.07:51:59.22#ibcon#read 3, iclass 11, count 0 2006.252.07:51:59.22#ibcon#about to read 4, iclass 11, count 0 2006.252.07:51:59.22#ibcon#read 4, iclass 11, count 0 2006.252.07:51:59.22#ibcon#about to read 5, iclass 11, count 0 2006.252.07:51:59.22#ibcon#read 5, iclass 11, count 0 2006.252.07:51:59.22#ibcon#about to read 6, iclass 11, count 0 2006.252.07:51:59.22#ibcon#read 6, iclass 11, count 0 2006.252.07:51:59.22#ibcon#end of sib2, iclass 11, count 0 2006.252.07:51:59.22#ibcon#*mode == 0, iclass 11, count 0 2006.252.07:51:59.22#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.252.07:51:59.22#ibcon#[25=USB\r\n] 2006.252.07:51:59.22#ibcon#*before write, iclass 11, count 0 2006.252.07:51:59.22#ibcon#enter sib2, iclass 11, count 0 2006.252.07:51:59.22#ibcon#flushed, iclass 11, count 0 2006.252.07:51:59.22#ibcon#about to write, iclass 11, count 0 2006.252.07:51:59.22#ibcon#wrote, iclass 11, count 0 2006.252.07:51:59.22#ibcon#about to read 3, iclass 11, count 0 2006.252.07:51:59.25#ibcon#read 3, iclass 11, count 0 2006.252.07:51:59.25#ibcon#about to read 4, iclass 11, count 0 2006.252.07:51:59.25#ibcon#read 4, iclass 11, count 0 2006.252.07:51:59.25#ibcon#about to read 5, iclass 11, count 0 2006.252.07:51:59.25#ibcon#read 5, iclass 11, count 0 2006.252.07:51:59.25#ibcon#about to read 6, iclass 11, count 0 2006.252.07:51:59.25#ibcon#read 6, iclass 11, count 0 2006.252.07:51:59.25#ibcon#end of sib2, iclass 11, count 0 2006.252.07:51:59.25#ibcon#*after write, iclass 11, count 0 2006.252.07:51:59.25#ibcon#*before return 0, iclass 11, count 0 2006.252.07:51:59.25#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.252.07:51:59.25#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.252.07:51:59.25#ibcon#about to clear, iclass 11 cls_cnt 0 2006.252.07:51:59.25#ibcon#cleared, iclass 11 cls_cnt 0 2006.252.07:51:59.25$vc4f8/valo=5,652.99 2006.252.07:51:59.25#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.252.07:51:59.25#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.252.07:51:59.25#ibcon#ireg 17 cls_cnt 0 2006.252.07:51:59.25#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.252.07:51:59.25#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.252.07:51:59.25#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.252.07:51:59.25#ibcon#enter wrdev, iclass 13, count 0 2006.252.07:51:59.25#ibcon#first serial, iclass 13, count 0 2006.252.07:51:59.25#ibcon#enter sib2, iclass 13, count 0 2006.252.07:51:59.25#ibcon#flushed, iclass 13, count 0 2006.252.07:51:59.25#ibcon#about to write, iclass 13, count 0 2006.252.07:51:59.25#ibcon#wrote, iclass 13, count 0 2006.252.07:51:59.25#ibcon#about to read 3, iclass 13, count 0 2006.252.07:51:59.27#ibcon#read 3, iclass 13, count 0 2006.252.07:51:59.27#ibcon#about to read 4, iclass 13, count 0 2006.252.07:51:59.27#ibcon#read 4, iclass 13, count 0 2006.252.07:51:59.27#ibcon#about to read 5, iclass 13, count 0 2006.252.07:51:59.27#ibcon#read 5, iclass 13, count 0 2006.252.07:51:59.27#ibcon#about to read 6, iclass 13, count 0 2006.252.07:51:59.27#ibcon#read 6, iclass 13, count 0 2006.252.07:51:59.27#ibcon#end of sib2, iclass 13, count 0 2006.252.07:51:59.27#ibcon#*mode == 0, iclass 13, count 0 2006.252.07:51:59.27#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.252.07:51:59.27#ibcon#[26=FRQ=05,652.99\r\n] 2006.252.07:51:59.27#ibcon#*before write, iclass 13, count 0 2006.252.07:51:59.27#ibcon#enter sib2, iclass 13, count 0 2006.252.07:51:59.27#ibcon#flushed, iclass 13, count 0 2006.252.07:51:59.27#ibcon#about to write, iclass 13, count 0 2006.252.07:51:59.27#ibcon#wrote, iclass 13, count 0 2006.252.07:51:59.27#ibcon#about to read 3, iclass 13, count 0 2006.252.07:51:59.31#ibcon#read 3, iclass 13, count 0 2006.252.07:51:59.31#ibcon#about to read 4, iclass 13, count 0 2006.252.07:51:59.31#ibcon#read 4, iclass 13, count 0 2006.252.07:51:59.31#ibcon#about to read 5, iclass 13, count 0 2006.252.07:51:59.31#ibcon#read 5, iclass 13, count 0 2006.252.07:51:59.31#ibcon#about to read 6, iclass 13, count 0 2006.252.07:51:59.31#ibcon#read 6, iclass 13, count 0 2006.252.07:51:59.31#ibcon#end of sib2, iclass 13, count 0 2006.252.07:51:59.31#ibcon#*after write, iclass 13, count 0 2006.252.07:51:59.31#ibcon#*before return 0, iclass 13, count 0 2006.252.07:51:59.31#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.252.07:51:59.31#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.252.07:51:59.31#ibcon#about to clear, iclass 13 cls_cnt 0 2006.252.07:51:59.31#ibcon#cleared, iclass 13 cls_cnt 0 2006.252.07:51:59.31$vc4f8/va=5,7 2006.252.07:51:59.31#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.252.07:51:59.31#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.252.07:51:59.31#ibcon#ireg 11 cls_cnt 2 2006.252.07:51:59.31#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.252.07:51:59.37#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.252.07:51:59.37#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.252.07:51:59.37#ibcon#enter wrdev, iclass 15, count 2 2006.252.07:51:59.37#ibcon#first serial, iclass 15, count 2 2006.252.07:51:59.37#ibcon#enter sib2, iclass 15, count 2 2006.252.07:51:59.37#ibcon#flushed, iclass 15, count 2 2006.252.07:51:59.37#ibcon#about to write, iclass 15, count 2 2006.252.07:51:59.37#ibcon#wrote, iclass 15, count 2 2006.252.07:51:59.37#ibcon#about to read 3, iclass 15, count 2 2006.252.07:51:59.39#ibcon#read 3, iclass 15, count 2 2006.252.07:51:59.39#ibcon#about to read 4, iclass 15, count 2 2006.252.07:51:59.39#ibcon#read 4, iclass 15, count 2 2006.252.07:51:59.39#ibcon#about to read 5, iclass 15, count 2 2006.252.07:51:59.39#ibcon#read 5, iclass 15, count 2 2006.252.07:51:59.39#ibcon#about to read 6, iclass 15, count 2 2006.252.07:51:59.39#ibcon#read 6, iclass 15, count 2 2006.252.07:51:59.39#ibcon#end of sib2, iclass 15, count 2 2006.252.07:51:59.39#ibcon#*mode == 0, iclass 15, count 2 2006.252.07:51:59.39#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.252.07:51:59.39#ibcon#[25=AT05-07\r\n] 2006.252.07:51:59.39#ibcon#*before write, iclass 15, count 2 2006.252.07:51:59.39#ibcon#enter sib2, iclass 15, count 2 2006.252.07:51:59.39#ibcon#flushed, iclass 15, count 2 2006.252.07:51:59.39#ibcon#about to write, iclass 15, count 2 2006.252.07:51:59.39#ibcon#wrote, iclass 15, count 2 2006.252.07:51:59.39#ibcon#about to read 3, iclass 15, count 2 2006.252.07:51:59.42#ibcon#read 3, iclass 15, count 2 2006.252.07:51:59.42#ibcon#about to read 4, iclass 15, count 2 2006.252.07:51:59.42#ibcon#read 4, iclass 15, count 2 2006.252.07:51:59.42#ibcon#about to read 5, iclass 15, count 2 2006.252.07:51:59.42#ibcon#read 5, iclass 15, count 2 2006.252.07:51:59.42#ibcon#about to read 6, iclass 15, count 2 2006.252.07:51:59.42#ibcon#read 6, iclass 15, count 2 2006.252.07:51:59.42#ibcon#end of sib2, iclass 15, count 2 2006.252.07:51:59.42#ibcon#*after write, iclass 15, count 2 2006.252.07:51:59.42#ibcon#*before return 0, iclass 15, count 2 2006.252.07:51:59.42#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.252.07:51:59.42#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.252.07:51:59.42#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.252.07:51:59.42#ibcon#ireg 7 cls_cnt 0 2006.252.07:51:59.42#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.252.07:51:59.54#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.252.07:51:59.54#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.252.07:51:59.54#ibcon#enter wrdev, iclass 15, count 0 2006.252.07:51:59.54#ibcon#first serial, iclass 15, count 0 2006.252.07:51:59.54#ibcon#enter sib2, iclass 15, count 0 2006.252.07:51:59.54#ibcon#flushed, iclass 15, count 0 2006.252.07:51:59.54#ibcon#about to write, iclass 15, count 0 2006.252.07:51:59.54#ibcon#wrote, iclass 15, count 0 2006.252.07:51:59.54#ibcon#about to read 3, iclass 15, count 0 2006.252.07:51:59.56#ibcon#read 3, iclass 15, count 0 2006.252.07:51:59.56#ibcon#about to read 4, iclass 15, count 0 2006.252.07:51:59.56#ibcon#read 4, iclass 15, count 0 2006.252.07:51:59.56#ibcon#about to read 5, iclass 15, count 0 2006.252.07:51:59.56#ibcon#read 5, iclass 15, count 0 2006.252.07:51:59.56#ibcon#about to read 6, iclass 15, count 0 2006.252.07:51:59.56#ibcon#read 6, iclass 15, count 0 2006.252.07:51:59.56#ibcon#end of sib2, iclass 15, count 0 2006.252.07:51:59.56#ibcon#*mode == 0, iclass 15, count 0 2006.252.07:51:59.56#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.252.07:51:59.56#ibcon#[25=USB\r\n] 2006.252.07:51:59.56#ibcon#*before write, iclass 15, count 0 2006.252.07:51:59.56#ibcon#enter sib2, iclass 15, count 0 2006.252.07:51:59.56#ibcon#flushed, iclass 15, count 0 2006.252.07:51:59.56#ibcon#about to write, iclass 15, count 0 2006.252.07:51:59.56#ibcon#wrote, iclass 15, count 0 2006.252.07:51:59.56#ibcon#about to read 3, iclass 15, count 0 2006.252.07:51:59.59#ibcon#read 3, iclass 15, count 0 2006.252.07:51:59.59#ibcon#about to read 4, iclass 15, count 0 2006.252.07:51:59.59#ibcon#read 4, iclass 15, count 0 2006.252.07:51:59.59#ibcon#about to read 5, iclass 15, count 0 2006.252.07:51:59.59#ibcon#read 5, iclass 15, count 0 2006.252.07:51:59.59#ibcon#about to read 6, iclass 15, count 0 2006.252.07:51:59.59#ibcon#read 6, iclass 15, count 0 2006.252.07:51:59.59#ibcon#end of sib2, iclass 15, count 0 2006.252.07:51:59.59#ibcon#*after write, iclass 15, count 0 2006.252.07:51:59.59#ibcon#*before return 0, iclass 15, count 0 2006.252.07:51:59.59#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.252.07:51:59.59#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.252.07:51:59.59#ibcon#about to clear, iclass 15 cls_cnt 0 2006.252.07:51:59.59#ibcon#cleared, iclass 15 cls_cnt 0 2006.252.07:51:59.59$vc4f8/valo=6,772.99 2006.252.07:51:59.59#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.252.07:51:59.59#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.252.07:51:59.59#ibcon#ireg 17 cls_cnt 0 2006.252.07:51:59.59#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.252.07:51:59.59#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.252.07:51:59.59#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.252.07:51:59.59#ibcon#enter wrdev, iclass 17, count 0 2006.252.07:51:59.59#ibcon#first serial, iclass 17, count 0 2006.252.07:51:59.59#ibcon#enter sib2, iclass 17, count 0 2006.252.07:51:59.59#ibcon#flushed, iclass 17, count 0 2006.252.07:51:59.59#ibcon#about to write, iclass 17, count 0 2006.252.07:51:59.59#ibcon#wrote, iclass 17, count 0 2006.252.07:51:59.59#ibcon#about to read 3, iclass 17, count 0 2006.252.07:51:59.62#ibcon#read 3, iclass 17, count 0 2006.252.07:51:59.62#ibcon#about to read 4, iclass 17, count 0 2006.252.07:51:59.62#ibcon#read 4, iclass 17, count 0 2006.252.07:51:59.62#ibcon#about to read 5, iclass 17, count 0 2006.252.07:51:59.62#ibcon#read 5, iclass 17, count 0 2006.252.07:51:59.62#ibcon#about to read 6, iclass 17, count 0 2006.252.07:51:59.62#ibcon#read 6, iclass 17, count 0 2006.252.07:51:59.62#ibcon#end of sib2, iclass 17, count 0 2006.252.07:51:59.62#ibcon#*mode == 0, iclass 17, count 0 2006.252.07:51:59.62#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.252.07:51:59.62#ibcon#[26=FRQ=06,772.99\r\n] 2006.252.07:51:59.62#ibcon#*before write, iclass 17, count 0 2006.252.07:51:59.62#ibcon#enter sib2, iclass 17, count 0 2006.252.07:51:59.62#ibcon#flushed, iclass 17, count 0 2006.252.07:51:59.62#ibcon#about to write, iclass 17, count 0 2006.252.07:51:59.62#ibcon#wrote, iclass 17, count 0 2006.252.07:51:59.62#ibcon#about to read 3, iclass 17, count 0 2006.252.07:51:59.66#ibcon#read 3, iclass 17, count 0 2006.252.07:51:59.66#ibcon#about to read 4, iclass 17, count 0 2006.252.07:51:59.66#ibcon#read 4, iclass 17, count 0 2006.252.07:51:59.66#ibcon#about to read 5, iclass 17, count 0 2006.252.07:51:59.66#ibcon#read 5, iclass 17, count 0 2006.252.07:51:59.66#ibcon#about to read 6, iclass 17, count 0 2006.252.07:51:59.66#ibcon#read 6, iclass 17, count 0 2006.252.07:51:59.66#ibcon#end of sib2, iclass 17, count 0 2006.252.07:51:59.66#ibcon#*after write, iclass 17, count 0 2006.252.07:51:59.66#ibcon#*before return 0, iclass 17, count 0 2006.252.07:51:59.66#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.252.07:51:59.66#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.252.07:51:59.66#ibcon#about to clear, iclass 17 cls_cnt 0 2006.252.07:51:59.66#ibcon#cleared, iclass 17 cls_cnt 0 2006.252.07:51:59.66$vc4f8/va=6,7 2006.252.07:51:59.66#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.252.07:51:59.66#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.252.07:51:59.66#ibcon#ireg 11 cls_cnt 2 2006.252.07:51:59.66#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.252.07:51:59.71#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.252.07:51:59.71#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.252.07:51:59.71#ibcon#enter wrdev, iclass 19, count 2 2006.252.07:51:59.71#ibcon#first serial, iclass 19, count 2 2006.252.07:51:59.71#ibcon#enter sib2, iclass 19, count 2 2006.252.07:51:59.71#ibcon#flushed, iclass 19, count 2 2006.252.07:51:59.71#ibcon#about to write, iclass 19, count 2 2006.252.07:51:59.71#ibcon#wrote, iclass 19, count 2 2006.252.07:51:59.71#ibcon#about to read 3, iclass 19, count 2 2006.252.07:51:59.73#ibcon#read 3, iclass 19, count 2 2006.252.07:51:59.73#ibcon#about to read 4, iclass 19, count 2 2006.252.07:51:59.73#ibcon#read 4, iclass 19, count 2 2006.252.07:51:59.73#ibcon#about to read 5, iclass 19, count 2 2006.252.07:51:59.73#ibcon#read 5, iclass 19, count 2 2006.252.07:51:59.73#ibcon#about to read 6, iclass 19, count 2 2006.252.07:51:59.73#ibcon#read 6, iclass 19, count 2 2006.252.07:51:59.73#ibcon#end of sib2, iclass 19, count 2 2006.252.07:51:59.73#ibcon#*mode == 0, iclass 19, count 2 2006.252.07:51:59.73#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.252.07:51:59.73#ibcon#[25=AT06-07\r\n] 2006.252.07:51:59.73#ibcon#*before write, iclass 19, count 2 2006.252.07:51:59.73#ibcon#enter sib2, iclass 19, count 2 2006.252.07:51:59.73#ibcon#flushed, iclass 19, count 2 2006.252.07:51:59.73#ibcon#about to write, iclass 19, count 2 2006.252.07:51:59.73#ibcon#wrote, iclass 19, count 2 2006.252.07:51:59.73#ibcon#about to read 3, iclass 19, count 2 2006.252.07:51:59.76#ibcon#read 3, iclass 19, count 2 2006.252.07:51:59.76#ibcon#about to read 4, iclass 19, count 2 2006.252.07:51:59.76#ibcon#read 4, iclass 19, count 2 2006.252.07:51:59.76#ibcon#about to read 5, iclass 19, count 2 2006.252.07:51:59.76#ibcon#read 5, iclass 19, count 2 2006.252.07:51:59.76#ibcon#about to read 6, iclass 19, count 2 2006.252.07:51:59.76#ibcon#read 6, iclass 19, count 2 2006.252.07:51:59.76#ibcon#end of sib2, iclass 19, count 2 2006.252.07:51:59.76#ibcon#*after write, iclass 19, count 2 2006.252.07:51:59.76#ibcon#*before return 0, iclass 19, count 2 2006.252.07:51:59.76#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.252.07:51:59.76#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.252.07:51:59.76#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.252.07:51:59.76#ibcon#ireg 7 cls_cnt 0 2006.252.07:51:59.76#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.252.07:51:59.88#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.252.07:51:59.88#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.252.07:51:59.88#ibcon#enter wrdev, iclass 19, count 0 2006.252.07:51:59.88#ibcon#first serial, iclass 19, count 0 2006.252.07:51:59.88#ibcon#enter sib2, iclass 19, count 0 2006.252.07:51:59.88#ibcon#flushed, iclass 19, count 0 2006.252.07:51:59.88#ibcon#about to write, iclass 19, count 0 2006.252.07:51:59.88#ibcon#wrote, iclass 19, count 0 2006.252.07:51:59.88#ibcon#about to read 3, iclass 19, count 0 2006.252.07:51:59.90#ibcon#read 3, iclass 19, count 0 2006.252.07:51:59.90#ibcon#about to read 4, iclass 19, count 0 2006.252.07:51:59.90#ibcon#read 4, iclass 19, count 0 2006.252.07:51:59.90#ibcon#about to read 5, iclass 19, count 0 2006.252.07:51:59.90#ibcon#read 5, iclass 19, count 0 2006.252.07:51:59.90#ibcon#about to read 6, iclass 19, count 0 2006.252.07:51:59.90#ibcon#read 6, iclass 19, count 0 2006.252.07:51:59.90#ibcon#end of sib2, iclass 19, count 0 2006.252.07:51:59.90#ibcon#*mode == 0, iclass 19, count 0 2006.252.07:51:59.90#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.252.07:51:59.90#ibcon#[25=USB\r\n] 2006.252.07:51:59.90#ibcon#*before write, iclass 19, count 0 2006.252.07:51:59.90#ibcon#enter sib2, iclass 19, count 0 2006.252.07:51:59.90#ibcon#flushed, iclass 19, count 0 2006.252.07:51:59.90#ibcon#about to write, iclass 19, count 0 2006.252.07:51:59.90#ibcon#wrote, iclass 19, count 0 2006.252.07:51:59.90#ibcon#about to read 3, iclass 19, count 0 2006.252.07:51:59.93#ibcon#read 3, iclass 19, count 0 2006.252.07:51:59.93#ibcon#about to read 4, iclass 19, count 0 2006.252.07:51:59.93#ibcon#read 4, iclass 19, count 0 2006.252.07:51:59.93#ibcon#about to read 5, iclass 19, count 0 2006.252.07:51:59.93#ibcon#read 5, iclass 19, count 0 2006.252.07:51:59.93#ibcon#about to read 6, iclass 19, count 0 2006.252.07:51:59.93#ibcon#read 6, iclass 19, count 0 2006.252.07:51:59.93#ibcon#end of sib2, iclass 19, count 0 2006.252.07:51:59.93#ibcon#*after write, iclass 19, count 0 2006.252.07:51:59.93#ibcon#*before return 0, iclass 19, count 0 2006.252.07:51:59.93#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.252.07:51:59.93#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.252.07:51:59.93#ibcon#about to clear, iclass 19 cls_cnt 0 2006.252.07:51:59.93#ibcon#cleared, iclass 19 cls_cnt 0 2006.252.07:51:59.93$vc4f8/valo=7,832.99 2006.252.07:51:59.93#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.252.07:51:59.93#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.252.07:51:59.93#ibcon#ireg 17 cls_cnt 0 2006.252.07:51:59.93#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.252.07:51:59.93#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.252.07:51:59.93#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.252.07:51:59.93#ibcon#enter wrdev, iclass 21, count 0 2006.252.07:51:59.93#ibcon#first serial, iclass 21, count 0 2006.252.07:51:59.93#ibcon#enter sib2, iclass 21, count 0 2006.252.07:51:59.93#ibcon#flushed, iclass 21, count 0 2006.252.07:51:59.93#ibcon#about to write, iclass 21, count 0 2006.252.07:51:59.93#ibcon#wrote, iclass 21, count 0 2006.252.07:51:59.93#ibcon#about to read 3, iclass 21, count 0 2006.252.07:51:59.95#ibcon#read 3, iclass 21, count 0 2006.252.07:51:59.95#ibcon#about to read 4, iclass 21, count 0 2006.252.07:51:59.95#ibcon#read 4, iclass 21, count 0 2006.252.07:51:59.95#ibcon#about to read 5, iclass 21, count 0 2006.252.07:51:59.95#ibcon#read 5, iclass 21, count 0 2006.252.07:51:59.95#ibcon#about to read 6, iclass 21, count 0 2006.252.07:51:59.95#ibcon#read 6, iclass 21, count 0 2006.252.07:51:59.95#ibcon#end of sib2, iclass 21, count 0 2006.252.07:51:59.95#ibcon#*mode == 0, iclass 21, count 0 2006.252.07:51:59.95#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.252.07:51:59.95#ibcon#[26=FRQ=07,832.99\r\n] 2006.252.07:51:59.95#ibcon#*before write, iclass 21, count 0 2006.252.07:51:59.95#ibcon#enter sib2, iclass 21, count 0 2006.252.07:51:59.95#ibcon#flushed, iclass 21, count 0 2006.252.07:51:59.95#ibcon#about to write, iclass 21, count 0 2006.252.07:51:59.95#ibcon#wrote, iclass 21, count 0 2006.252.07:51:59.95#ibcon#about to read 3, iclass 21, count 0 2006.252.07:51:59.99#ibcon#read 3, iclass 21, count 0 2006.252.07:51:59.99#ibcon#about to read 4, iclass 21, count 0 2006.252.07:51:59.99#ibcon#read 4, iclass 21, count 0 2006.252.07:51:59.99#ibcon#about to read 5, iclass 21, count 0 2006.252.07:51:59.99#ibcon#read 5, iclass 21, count 0 2006.252.07:51:59.99#ibcon#about to read 6, iclass 21, count 0 2006.252.07:51:59.99#ibcon#read 6, iclass 21, count 0 2006.252.07:51:59.99#ibcon#end of sib2, iclass 21, count 0 2006.252.07:51:59.99#ibcon#*after write, iclass 21, count 0 2006.252.07:51:59.99#ibcon#*before return 0, iclass 21, count 0 2006.252.07:51:59.99#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.252.07:51:59.99#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.252.07:51:59.99#ibcon#about to clear, iclass 21 cls_cnt 0 2006.252.07:51:59.99#ibcon#cleared, iclass 21 cls_cnt 0 2006.252.07:51:59.99$vc4f8/va=7,7 2006.252.07:51:59.99#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.252.07:51:59.99#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.252.07:51:59.99#ibcon#ireg 11 cls_cnt 2 2006.252.07:51:59.99#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.252.07:52:00.05#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.252.07:52:00.05#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.252.07:52:00.05#ibcon#enter wrdev, iclass 23, count 2 2006.252.07:52:00.05#ibcon#first serial, iclass 23, count 2 2006.252.07:52:00.05#ibcon#enter sib2, iclass 23, count 2 2006.252.07:52:00.05#ibcon#flushed, iclass 23, count 2 2006.252.07:52:00.05#ibcon#about to write, iclass 23, count 2 2006.252.07:52:00.05#ibcon#wrote, iclass 23, count 2 2006.252.07:52:00.05#ibcon#about to read 3, iclass 23, count 2 2006.252.07:52:00.07#ibcon#read 3, iclass 23, count 2 2006.252.07:52:00.07#ibcon#about to read 4, iclass 23, count 2 2006.252.07:52:00.07#ibcon#read 4, iclass 23, count 2 2006.252.07:52:00.07#ibcon#about to read 5, iclass 23, count 2 2006.252.07:52:00.07#ibcon#read 5, iclass 23, count 2 2006.252.07:52:00.07#ibcon#about to read 6, iclass 23, count 2 2006.252.07:52:00.07#ibcon#read 6, iclass 23, count 2 2006.252.07:52:00.07#ibcon#end of sib2, iclass 23, count 2 2006.252.07:52:00.07#ibcon#*mode == 0, iclass 23, count 2 2006.252.07:52:00.07#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.252.07:52:00.07#ibcon#[25=AT07-07\r\n] 2006.252.07:52:00.07#ibcon#*before write, iclass 23, count 2 2006.252.07:52:00.07#ibcon#enter sib2, iclass 23, count 2 2006.252.07:52:00.07#ibcon#flushed, iclass 23, count 2 2006.252.07:52:00.07#ibcon#about to write, iclass 23, count 2 2006.252.07:52:00.07#ibcon#wrote, iclass 23, count 2 2006.252.07:52:00.07#ibcon#about to read 3, iclass 23, count 2 2006.252.07:52:00.10#ibcon#read 3, iclass 23, count 2 2006.252.07:52:00.10#ibcon#about to read 4, iclass 23, count 2 2006.252.07:52:00.10#ibcon#read 4, iclass 23, count 2 2006.252.07:52:00.10#ibcon#about to read 5, iclass 23, count 2 2006.252.07:52:00.10#ibcon#read 5, iclass 23, count 2 2006.252.07:52:00.10#ibcon#about to read 6, iclass 23, count 2 2006.252.07:52:00.10#ibcon#read 6, iclass 23, count 2 2006.252.07:52:00.10#ibcon#end of sib2, iclass 23, count 2 2006.252.07:52:00.10#ibcon#*after write, iclass 23, count 2 2006.252.07:52:00.10#ibcon#*before return 0, iclass 23, count 2 2006.252.07:52:00.10#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.252.07:52:00.10#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.252.07:52:00.10#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.252.07:52:00.10#ibcon#ireg 7 cls_cnt 0 2006.252.07:52:00.10#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.252.07:52:00.22#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.252.07:52:00.22#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.252.07:52:00.22#ibcon#enter wrdev, iclass 23, count 0 2006.252.07:52:00.22#ibcon#first serial, iclass 23, count 0 2006.252.07:52:00.22#ibcon#enter sib2, iclass 23, count 0 2006.252.07:52:00.22#ibcon#flushed, iclass 23, count 0 2006.252.07:52:00.22#ibcon#about to write, iclass 23, count 0 2006.252.07:52:00.22#ibcon#wrote, iclass 23, count 0 2006.252.07:52:00.22#ibcon#about to read 3, iclass 23, count 0 2006.252.07:52:00.24#ibcon#read 3, iclass 23, count 0 2006.252.07:52:00.24#ibcon#about to read 4, iclass 23, count 0 2006.252.07:52:00.24#ibcon#read 4, iclass 23, count 0 2006.252.07:52:00.24#ibcon#about to read 5, iclass 23, count 0 2006.252.07:52:00.24#ibcon#read 5, iclass 23, count 0 2006.252.07:52:00.24#ibcon#about to read 6, iclass 23, count 0 2006.252.07:52:00.24#ibcon#read 6, iclass 23, count 0 2006.252.07:52:00.24#ibcon#end of sib2, iclass 23, count 0 2006.252.07:52:00.24#ibcon#*mode == 0, iclass 23, count 0 2006.252.07:52:00.24#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.252.07:52:00.24#ibcon#[25=USB\r\n] 2006.252.07:52:00.24#ibcon#*before write, iclass 23, count 0 2006.252.07:52:00.24#ibcon#enter sib2, iclass 23, count 0 2006.252.07:52:00.24#ibcon#flushed, iclass 23, count 0 2006.252.07:52:00.24#ibcon#about to write, iclass 23, count 0 2006.252.07:52:00.24#ibcon#wrote, iclass 23, count 0 2006.252.07:52:00.24#ibcon#about to read 3, iclass 23, count 0 2006.252.07:52:00.27#ibcon#read 3, iclass 23, count 0 2006.252.07:52:00.27#ibcon#about to read 4, iclass 23, count 0 2006.252.07:52:00.27#ibcon#read 4, iclass 23, count 0 2006.252.07:52:00.27#ibcon#about to read 5, iclass 23, count 0 2006.252.07:52:00.27#ibcon#read 5, iclass 23, count 0 2006.252.07:52:00.27#ibcon#about to read 6, iclass 23, count 0 2006.252.07:52:00.27#ibcon#read 6, iclass 23, count 0 2006.252.07:52:00.27#ibcon#end of sib2, iclass 23, count 0 2006.252.07:52:00.27#ibcon#*after write, iclass 23, count 0 2006.252.07:52:00.27#ibcon#*before return 0, iclass 23, count 0 2006.252.07:52:00.27#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.252.07:52:00.27#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.252.07:52:00.27#ibcon#about to clear, iclass 23 cls_cnt 0 2006.252.07:52:00.27#ibcon#cleared, iclass 23 cls_cnt 0 2006.252.07:52:00.27$vc4f8/valo=8,852.99 2006.252.07:52:00.27#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.252.07:52:00.27#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.252.07:52:00.27#ibcon#ireg 17 cls_cnt 0 2006.252.07:52:00.27#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.252.07:52:00.27#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.252.07:52:00.27#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.252.07:52:00.27#ibcon#enter wrdev, iclass 25, count 0 2006.252.07:52:00.27#ibcon#first serial, iclass 25, count 0 2006.252.07:52:00.27#ibcon#enter sib2, iclass 25, count 0 2006.252.07:52:00.27#ibcon#flushed, iclass 25, count 0 2006.252.07:52:00.27#ibcon#about to write, iclass 25, count 0 2006.252.07:52:00.27#ibcon#wrote, iclass 25, count 0 2006.252.07:52:00.27#ibcon#about to read 3, iclass 25, count 0 2006.252.07:52:00.29#ibcon#read 3, iclass 25, count 0 2006.252.07:52:00.29#ibcon#about to read 4, iclass 25, count 0 2006.252.07:52:00.29#ibcon#read 4, iclass 25, count 0 2006.252.07:52:00.29#ibcon#about to read 5, iclass 25, count 0 2006.252.07:52:00.29#ibcon#read 5, iclass 25, count 0 2006.252.07:52:00.29#ibcon#about to read 6, iclass 25, count 0 2006.252.07:52:00.29#ibcon#read 6, iclass 25, count 0 2006.252.07:52:00.29#ibcon#end of sib2, iclass 25, count 0 2006.252.07:52:00.29#ibcon#*mode == 0, iclass 25, count 0 2006.252.07:52:00.29#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.252.07:52:00.29#ibcon#[26=FRQ=08,852.99\r\n] 2006.252.07:52:00.29#ibcon#*before write, iclass 25, count 0 2006.252.07:52:00.29#ibcon#enter sib2, iclass 25, count 0 2006.252.07:52:00.29#ibcon#flushed, iclass 25, count 0 2006.252.07:52:00.29#ibcon#about to write, iclass 25, count 0 2006.252.07:52:00.29#ibcon#wrote, iclass 25, count 0 2006.252.07:52:00.29#ibcon#about to read 3, iclass 25, count 0 2006.252.07:52:00.33#ibcon#read 3, iclass 25, count 0 2006.252.07:52:00.33#ibcon#about to read 4, iclass 25, count 0 2006.252.07:52:00.33#ibcon#read 4, iclass 25, count 0 2006.252.07:52:00.33#ibcon#about to read 5, iclass 25, count 0 2006.252.07:52:00.33#ibcon#read 5, iclass 25, count 0 2006.252.07:52:00.33#ibcon#about to read 6, iclass 25, count 0 2006.252.07:52:00.33#ibcon#read 6, iclass 25, count 0 2006.252.07:52:00.33#ibcon#end of sib2, iclass 25, count 0 2006.252.07:52:00.33#ibcon#*after write, iclass 25, count 0 2006.252.07:52:00.33#ibcon#*before return 0, iclass 25, count 0 2006.252.07:52:00.33#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.252.07:52:00.33#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.252.07:52:00.33#ibcon#about to clear, iclass 25 cls_cnt 0 2006.252.07:52:00.33#ibcon#cleared, iclass 25 cls_cnt 0 2006.252.07:52:00.33$vc4f8/va=8,7 2006.252.07:52:00.33#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.252.07:52:00.33#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.252.07:52:00.33#ibcon#ireg 11 cls_cnt 2 2006.252.07:52:00.33#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.252.07:52:00.39#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.252.07:52:00.39#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.252.07:52:00.39#ibcon#enter wrdev, iclass 27, count 2 2006.252.07:52:00.39#ibcon#first serial, iclass 27, count 2 2006.252.07:52:00.39#ibcon#enter sib2, iclass 27, count 2 2006.252.07:52:00.39#ibcon#flushed, iclass 27, count 2 2006.252.07:52:00.39#ibcon#about to write, iclass 27, count 2 2006.252.07:52:00.39#ibcon#wrote, iclass 27, count 2 2006.252.07:52:00.39#ibcon#about to read 3, iclass 27, count 2 2006.252.07:52:00.41#ibcon#read 3, iclass 27, count 2 2006.252.07:52:00.41#ibcon#about to read 4, iclass 27, count 2 2006.252.07:52:00.41#ibcon#read 4, iclass 27, count 2 2006.252.07:52:00.41#ibcon#about to read 5, iclass 27, count 2 2006.252.07:52:00.41#ibcon#read 5, iclass 27, count 2 2006.252.07:52:00.41#ibcon#about to read 6, iclass 27, count 2 2006.252.07:52:00.41#ibcon#read 6, iclass 27, count 2 2006.252.07:52:00.41#ibcon#end of sib2, iclass 27, count 2 2006.252.07:52:00.41#ibcon#*mode == 0, iclass 27, count 2 2006.252.07:52:00.41#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.252.07:52:00.41#ibcon#[25=AT08-07\r\n] 2006.252.07:52:00.41#ibcon#*before write, iclass 27, count 2 2006.252.07:52:00.41#ibcon#enter sib2, iclass 27, count 2 2006.252.07:52:00.41#ibcon#flushed, iclass 27, count 2 2006.252.07:52:00.41#ibcon#about to write, iclass 27, count 2 2006.252.07:52:00.41#ibcon#wrote, iclass 27, count 2 2006.252.07:52:00.41#ibcon#about to read 3, iclass 27, count 2 2006.252.07:52:00.44#ibcon#read 3, iclass 27, count 2 2006.252.07:52:00.44#ibcon#about to read 4, iclass 27, count 2 2006.252.07:52:00.44#ibcon#read 4, iclass 27, count 2 2006.252.07:52:00.44#ibcon#about to read 5, iclass 27, count 2 2006.252.07:52:00.44#ibcon#read 5, iclass 27, count 2 2006.252.07:52:00.44#ibcon#about to read 6, iclass 27, count 2 2006.252.07:52:00.44#ibcon#read 6, iclass 27, count 2 2006.252.07:52:00.44#ibcon#end of sib2, iclass 27, count 2 2006.252.07:52:00.44#ibcon#*after write, iclass 27, count 2 2006.252.07:52:00.44#ibcon#*before return 0, iclass 27, count 2 2006.252.07:52:00.44#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.252.07:52:00.44#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.252.07:52:00.44#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.252.07:52:00.44#ibcon#ireg 7 cls_cnt 0 2006.252.07:52:00.44#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.252.07:52:00.56#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.252.07:52:00.56#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.252.07:52:00.56#ibcon#enter wrdev, iclass 27, count 0 2006.252.07:52:00.56#ibcon#first serial, iclass 27, count 0 2006.252.07:52:00.56#ibcon#enter sib2, iclass 27, count 0 2006.252.07:52:00.56#ibcon#flushed, iclass 27, count 0 2006.252.07:52:00.56#ibcon#about to write, iclass 27, count 0 2006.252.07:52:00.56#ibcon#wrote, iclass 27, count 0 2006.252.07:52:00.56#ibcon#about to read 3, iclass 27, count 0 2006.252.07:52:00.58#ibcon#read 3, iclass 27, count 0 2006.252.07:52:00.58#ibcon#about to read 4, iclass 27, count 0 2006.252.07:52:00.58#ibcon#read 4, iclass 27, count 0 2006.252.07:52:00.58#ibcon#about to read 5, iclass 27, count 0 2006.252.07:52:00.58#ibcon#read 5, iclass 27, count 0 2006.252.07:52:00.58#ibcon#about to read 6, iclass 27, count 0 2006.252.07:52:00.58#ibcon#read 6, iclass 27, count 0 2006.252.07:52:00.58#ibcon#end of sib2, iclass 27, count 0 2006.252.07:52:00.58#ibcon#*mode == 0, iclass 27, count 0 2006.252.07:52:00.58#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.252.07:52:00.58#ibcon#[25=USB\r\n] 2006.252.07:52:00.58#ibcon#*before write, iclass 27, count 0 2006.252.07:52:00.58#ibcon#enter sib2, iclass 27, count 0 2006.252.07:52:00.58#ibcon#flushed, iclass 27, count 0 2006.252.07:52:00.58#ibcon#about to write, iclass 27, count 0 2006.252.07:52:00.58#ibcon#wrote, iclass 27, count 0 2006.252.07:52:00.58#ibcon#about to read 3, iclass 27, count 0 2006.252.07:52:00.61#ibcon#read 3, iclass 27, count 0 2006.252.07:52:00.61#ibcon#about to read 4, iclass 27, count 0 2006.252.07:52:00.61#ibcon#read 4, iclass 27, count 0 2006.252.07:52:00.61#ibcon#about to read 5, iclass 27, count 0 2006.252.07:52:00.61#ibcon#read 5, iclass 27, count 0 2006.252.07:52:00.61#ibcon#about to read 6, iclass 27, count 0 2006.252.07:52:00.61#ibcon#read 6, iclass 27, count 0 2006.252.07:52:00.61#ibcon#end of sib2, iclass 27, count 0 2006.252.07:52:00.61#ibcon#*after write, iclass 27, count 0 2006.252.07:52:00.61#ibcon#*before return 0, iclass 27, count 0 2006.252.07:52:00.61#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.252.07:52:00.61#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.252.07:52:00.61#ibcon#about to clear, iclass 27 cls_cnt 0 2006.252.07:52:00.61#ibcon#cleared, iclass 27 cls_cnt 0 2006.252.07:52:00.61$vc4f8/vblo=1,632.99 2006.252.07:52:00.61#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.252.07:52:00.61#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.252.07:52:00.61#ibcon#ireg 17 cls_cnt 0 2006.252.07:52:00.61#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.252.07:52:00.61#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.252.07:52:00.61#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.252.07:52:00.61#ibcon#enter wrdev, iclass 29, count 0 2006.252.07:52:00.61#ibcon#first serial, iclass 29, count 0 2006.252.07:52:00.61#ibcon#enter sib2, iclass 29, count 0 2006.252.07:52:00.61#ibcon#flushed, iclass 29, count 0 2006.252.07:52:00.61#ibcon#about to write, iclass 29, count 0 2006.252.07:52:00.61#ibcon#wrote, iclass 29, count 0 2006.252.07:52:00.61#ibcon#about to read 3, iclass 29, count 0 2006.252.07:52:00.63#ibcon#read 3, iclass 29, count 0 2006.252.07:52:00.63#ibcon#about to read 4, iclass 29, count 0 2006.252.07:52:00.63#ibcon#read 4, iclass 29, count 0 2006.252.07:52:00.63#ibcon#about to read 5, iclass 29, count 0 2006.252.07:52:00.63#ibcon#read 5, iclass 29, count 0 2006.252.07:52:00.63#ibcon#about to read 6, iclass 29, count 0 2006.252.07:52:00.63#ibcon#read 6, iclass 29, count 0 2006.252.07:52:00.63#ibcon#end of sib2, iclass 29, count 0 2006.252.07:52:00.63#ibcon#*mode == 0, iclass 29, count 0 2006.252.07:52:00.63#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.252.07:52:00.63#ibcon#[28=FRQ=01,632.99\r\n] 2006.252.07:52:00.63#ibcon#*before write, iclass 29, count 0 2006.252.07:52:00.63#ibcon#enter sib2, iclass 29, count 0 2006.252.07:52:00.63#ibcon#flushed, iclass 29, count 0 2006.252.07:52:00.63#ibcon#about to write, iclass 29, count 0 2006.252.07:52:00.63#ibcon#wrote, iclass 29, count 0 2006.252.07:52:00.63#ibcon#about to read 3, iclass 29, count 0 2006.252.07:52:00.67#ibcon#read 3, iclass 29, count 0 2006.252.07:52:00.67#ibcon#about to read 4, iclass 29, count 0 2006.252.07:52:00.67#ibcon#read 4, iclass 29, count 0 2006.252.07:52:00.67#ibcon#about to read 5, iclass 29, count 0 2006.252.07:52:00.67#ibcon#read 5, iclass 29, count 0 2006.252.07:52:00.67#ibcon#about to read 6, iclass 29, count 0 2006.252.07:52:00.67#ibcon#read 6, iclass 29, count 0 2006.252.07:52:00.67#ibcon#end of sib2, iclass 29, count 0 2006.252.07:52:00.67#ibcon#*after write, iclass 29, count 0 2006.252.07:52:00.67#ibcon#*before return 0, iclass 29, count 0 2006.252.07:52:00.67#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.252.07:52:00.67#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.252.07:52:00.67#ibcon#about to clear, iclass 29 cls_cnt 0 2006.252.07:52:00.67#ibcon#cleared, iclass 29 cls_cnt 0 2006.252.07:52:00.67$vc4f8/vb=1,4 2006.252.07:52:00.67#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.252.07:52:00.67#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.252.07:52:00.67#ibcon#ireg 11 cls_cnt 2 2006.252.07:52:00.67#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.252.07:52:00.67#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.252.07:52:00.67#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.252.07:52:00.67#ibcon#enter wrdev, iclass 31, count 2 2006.252.07:52:00.67#ibcon#first serial, iclass 31, count 2 2006.252.07:52:00.67#ibcon#enter sib2, iclass 31, count 2 2006.252.07:52:00.67#ibcon#flushed, iclass 31, count 2 2006.252.07:52:00.67#ibcon#about to write, iclass 31, count 2 2006.252.07:52:00.67#ibcon#wrote, iclass 31, count 2 2006.252.07:52:00.67#ibcon#about to read 3, iclass 31, count 2 2006.252.07:52:00.69#ibcon#read 3, iclass 31, count 2 2006.252.07:52:00.69#ibcon#about to read 4, iclass 31, count 2 2006.252.07:52:00.69#ibcon#read 4, iclass 31, count 2 2006.252.07:52:00.69#ibcon#about to read 5, iclass 31, count 2 2006.252.07:52:00.69#ibcon#read 5, iclass 31, count 2 2006.252.07:52:00.69#ibcon#about to read 6, iclass 31, count 2 2006.252.07:52:00.69#ibcon#read 6, iclass 31, count 2 2006.252.07:52:00.69#ibcon#end of sib2, iclass 31, count 2 2006.252.07:52:00.69#ibcon#*mode == 0, iclass 31, count 2 2006.252.07:52:00.69#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.252.07:52:00.69#ibcon#[27=AT01-04\r\n] 2006.252.07:52:00.69#ibcon#*before write, iclass 31, count 2 2006.252.07:52:00.69#ibcon#enter sib2, iclass 31, count 2 2006.252.07:52:00.69#ibcon#flushed, iclass 31, count 2 2006.252.07:52:00.69#ibcon#about to write, iclass 31, count 2 2006.252.07:52:00.69#ibcon#wrote, iclass 31, count 2 2006.252.07:52:00.69#ibcon#about to read 3, iclass 31, count 2 2006.252.07:52:00.72#ibcon#read 3, iclass 31, count 2 2006.252.07:52:00.72#ibcon#about to read 4, iclass 31, count 2 2006.252.07:52:00.72#ibcon#read 4, iclass 31, count 2 2006.252.07:52:00.72#ibcon#about to read 5, iclass 31, count 2 2006.252.07:52:00.72#ibcon#read 5, iclass 31, count 2 2006.252.07:52:00.72#ibcon#about to read 6, iclass 31, count 2 2006.252.07:52:00.72#ibcon#read 6, iclass 31, count 2 2006.252.07:52:00.72#ibcon#end of sib2, iclass 31, count 2 2006.252.07:52:00.72#ibcon#*after write, iclass 31, count 2 2006.252.07:52:00.72#ibcon#*before return 0, iclass 31, count 2 2006.252.07:52:00.72#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.252.07:52:00.72#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.252.07:52:00.72#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.252.07:52:00.72#ibcon#ireg 7 cls_cnt 0 2006.252.07:52:00.72#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.252.07:52:00.84#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.252.07:52:00.84#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.252.07:52:00.84#ibcon#enter wrdev, iclass 31, count 0 2006.252.07:52:00.84#ibcon#first serial, iclass 31, count 0 2006.252.07:52:00.84#ibcon#enter sib2, iclass 31, count 0 2006.252.07:52:00.84#ibcon#flushed, iclass 31, count 0 2006.252.07:52:00.84#ibcon#about to write, iclass 31, count 0 2006.252.07:52:00.84#ibcon#wrote, iclass 31, count 0 2006.252.07:52:00.84#ibcon#about to read 3, iclass 31, count 0 2006.252.07:52:00.86#ibcon#read 3, iclass 31, count 0 2006.252.07:52:00.86#ibcon#about to read 4, iclass 31, count 0 2006.252.07:52:00.86#ibcon#read 4, iclass 31, count 0 2006.252.07:52:00.86#ibcon#about to read 5, iclass 31, count 0 2006.252.07:52:00.86#ibcon#read 5, iclass 31, count 0 2006.252.07:52:00.86#ibcon#about to read 6, iclass 31, count 0 2006.252.07:52:00.86#ibcon#read 6, iclass 31, count 0 2006.252.07:52:00.86#ibcon#end of sib2, iclass 31, count 0 2006.252.07:52:00.86#ibcon#*mode == 0, iclass 31, count 0 2006.252.07:52:00.86#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.252.07:52:00.86#ibcon#[27=USB\r\n] 2006.252.07:52:00.86#ibcon#*before write, iclass 31, count 0 2006.252.07:52:00.86#ibcon#enter sib2, iclass 31, count 0 2006.252.07:52:00.86#ibcon#flushed, iclass 31, count 0 2006.252.07:52:00.86#ibcon#about to write, iclass 31, count 0 2006.252.07:52:00.86#ibcon#wrote, iclass 31, count 0 2006.252.07:52:00.86#ibcon#about to read 3, iclass 31, count 0 2006.252.07:52:00.89#ibcon#read 3, iclass 31, count 0 2006.252.07:52:00.89#ibcon#about to read 4, iclass 31, count 0 2006.252.07:52:00.89#ibcon#read 4, iclass 31, count 0 2006.252.07:52:00.89#ibcon#about to read 5, iclass 31, count 0 2006.252.07:52:00.89#ibcon#read 5, iclass 31, count 0 2006.252.07:52:00.89#ibcon#about to read 6, iclass 31, count 0 2006.252.07:52:00.89#ibcon#read 6, iclass 31, count 0 2006.252.07:52:00.89#ibcon#end of sib2, iclass 31, count 0 2006.252.07:52:00.89#ibcon#*after write, iclass 31, count 0 2006.252.07:52:00.89#ibcon#*before return 0, iclass 31, count 0 2006.252.07:52:00.89#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.252.07:52:00.89#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.252.07:52:00.89#ibcon#about to clear, iclass 31 cls_cnt 0 2006.252.07:52:00.89#ibcon#cleared, iclass 31 cls_cnt 0 2006.252.07:52:00.89$vc4f8/vblo=2,640.99 2006.252.07:52:00.89#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.252.07:52:00.89#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.252.07:52:00.89#ibcon#ireg 17 cls_cnt 0 2006.252.07:52:00.89#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.252.07:52:00.89#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.252.07:52:00.89#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.252.07:52:00.89#ibcon#enter wrdev, iclass 33, count 0 2006.252.07:52:00.89#ibcon#first serial, iclass 33, count 0 2006.252.07:52:00.89#ibcon#enter sib2, iclass 33, count 0 2006.252.07:52:00.89#ibcon#flushed, iclass 33, count 0 2006.252.07:52:00.89#ibcon#about to write, iclass 33, count 0 2006.252.07:52:00.89#ibcon#wrote, iclass 33, count 0 2006.252.07:52:00.89#ibcon#about to read 3, iclass 33, count 0 2006.252.07:52:00.91#ibcon#read 3, iclass 33, count 0 2006.252.07:52:00.91#ibcon#about to read 4, iclass 33, count 0 2006.252.07:52:00.91#ibcon#read 4, iclass 33, count 0 2006.252.07:52:00.91#ibcon#about to read 5, iclass 33, count 0 2006.252.07:52:00.91#ibcon#read 5, iclass 33, count 0 2006.252.07:52:00.91#ibcon#about to read 6, iclass 33, count 0 2006.252.07:52:00.91#ibcon#read 6, iclass 33, count 0 2006.252.07:52:00.91#ibcon#end of sib2, iclass 33, count 0 2006.252.07:52:00.91#ibcon#*mode == 0, iclass 33, count 0 2006.252.07:52:00.91#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.252.07:52:00.91#ibcon#[28=FRQ=02,640.99\r\n] 2006.252.07:52:00.91#ibcon#*before write, iclass 33, count 0 2006.252.07:52:00.91#ibcon#enter sib2, iclass 33, count 0 2006.252.07:52:00.91#ibcon#flushed, iclass 33, count 0 2006.252.07:52:00.91#ibcon#about to write, iclass 33, count 0 2006.252.07:52:00.91#ibcon#wrote, iclass 33, count 0 2006.252.07:52:00.91#ibcon#about to read 3, iclass 33, count 0 2006.252.07:52:00.95#ibcon#read 3, iclass 33, count 0 2006.252.07:52:00.95#ibcon#about to read 4, iclass 33, count 0 2006.252.07:52:00.95#ibcon#read 4, iclass 33, count 0 2006.252.07:52:00.95#ibcon#about to read 5, iclass 33, count 0 2006.252.07:52:00.95#ibcon#read 5, iclass 33, count 0 2006.252.07:52:00.95#ibcon#about to read 6, iclass 33, count 0 2006.252.07:52:00.95#ibcon#read 6, iclass 33, count 0 2006.252.07:52:00.95#ibcon#end of sib2, iclass 33, count 0 2006.252.07:52:00.95#ibcon#*after write, iclass 33, count 0 2006.252.07:52:00.95#ibcon#*before return 0, iclass 33, count 0 2006.252.07:52:00.95#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.252.07:52:00.95#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.252.07:52:00.95#ibcon#about to clear, iclass 33 cls_cnt 0 2006.252.07:52:00.95#ibcon#cleared, iclass 33 cls_cnt 0 2006.252.07:52:00.95$vc4f8/vb=2,5 2006.252.07:52:00.95#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.252.07:52:00.95#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.252.07:52:00.95#ibcon#ireg 11 cls_cnt 2 2006.252.07:52:00.95#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.252.07:52:01.01#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.252.07:52:01.01#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.252.07:52:01.01#ibcon#enter wrdev, iclass 35, count 2 2006.252.07:52:01.01#ibcon#first serial, iclass 35, count 2 2006.252.07:52:01.01#ibcon#enter sib2, iclass 35, count 2 2006.252.07:52:01.01#ibcon#flushed, iclass 35, count 2 2006.252.07:52:01.01#ibcon#about to write, iclass 35, count 2 2006.252.07:52:01.01#ibcon#wrote, iclass 35, count 2 2006.252.07:52:01.01#ibcon#about to read 3, iclass 35, count 2 2006.252.07:52:01.03#ibcon#read 3, iclass 35, count 2 2006.252.07:52:01.03#ibcon#about to read 4, iclass 35, count 2 2006.252.07:52:01.03#ibcon#read 4, iclass 35, count 2 2006.252.07:52:01.03#ibcon#about to read 5, iclass 35, count 2 2006.252.07:52:01.03#ibcon#read 5, iclass 35, count 2 2006.252.07:52:01.03#ibcon#about to read 6, iclass 35, count 2 2006.252.07:52:01.03#ibcon#read 6, iclass 35, count 2 2006.252.07:52:01.03#ibcon#end of sib2, iclass 35, count 2 2006.252.07:52:01.03#ibcon#*mode == 0, iclass 35, count 2 2006.252.07:52:01.03#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.252.07:52:01.03#ibcon#[27=AT02-05\r\n] 2006.252.07:52:01.03#ibcon#*before write, iclass 35, count 2 2006.252.07:52:01.03#ibcon#enter sib2, iclass 35, count 2 2006.252.07:52:01.03#ibcon#flushed, iclass 35, count 2 2006.252.07:52:01.03#ibcon#about to write, iclass 35, count 2 2006.252.07:52:01.03#ibcon#wrote, iclass 35, count 2 2006.252.07:52:01.03#ibcon#about to read 3, iclass 35, count 2 2006.252.07:52:01.06#ibcon#read 3, iclass 35, count 2 2006.252.07:52:01.06#ibcon#about to read 4, iclass 35, count 2 2006.252.07:52:01.06#ibcon#read 4, iclass 35, count 2 2006.252.07:52:01.06#ibcon#about to read 5, iclass 35, count 2 2006.252.07:52:01.06#ibcon#read 5, iclass 35, count 2 2006.252.07:52:01.06#ibcon#about to read 6, iclass 35, count 2 2006.252.07:52:01.06#ibcon#read 6, iclass 35, count 2 2006.252.07:52:01.06#ibcon#end of sib2, iclass 35, count 2 2006.252.07:52:01.06#ibcon#*after write, iclass 35, count 2 2006.252.07:52:01.06#ibcon#*before return 0, iclass 35, count 2 2006.252.07:52:01.06#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.252.07:52:01.06#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.252.07:52:01.06#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.252.07:52:01.06#ibcon#ireg 7 cls_cnt 0 2006.252.07:52:01.06#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.252.07:52:01.18#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.252.07:52:01.18#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.252.07:52:01.18#ibcon#enter wrdev, iclass 35, count 0 2006.252.07:52:01.18#ibcon#first serial, iclass 35, count 0 2006.252.07:52:01.18#ibcon#enter sib2, iclass 35, count 0 2006.252.07:52:01.18#ibcon#flushed, iclass 35, count 0 2006.252.07:52:01.18#ibcon#about to write, iclass 35, count 0 2006.252.07:52:01.18#ibcon#wrote, iclass 35, count 0 2006.252.07:52:01.18#ibcon#about to read 3, iclass 35, count 0 2006.252.07:52:01.22#ibcon#read 3, iclass 35, count 0 2006.252.07:52:01.22#ibcon#about to read 4, iclass 35, count 0 2006.252.07:52:01.22#ibcon#read 4, iclass 35, count 0 2006.252.07:52:01.22#ibcon#about to read 5, iclass 35, count 0 2006.252.07:52:01.22#ibcon#read 5, iclass 35, count 0 2006.252.07:52:01.22#ibcon#about to read 6, iclass 35, count 0 2006.252.07:52:01.22#ibcon#read 6, iclass 35, count 0 2006.252.07:52:01.22#ibcon#end of sib2, iclass 35, count 0 2006.252.07:52:01.22#ibcon#*mode == 0, iclass 35, count 0 2006.252.07:52:01.22#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.252.07:52:01.22#ibcon#[27=USB\r\n] 2006.252.07:52:01.22#ibcon#*before write, iclass 35, count 0 2006.252.07:52:01.22#ibcon#enter sib2, iclass 35, count 0 2006.252.07:52:01.22#ibcon#flushed, iclass 35, count 0 2006.252.07:52:01.22#ibcon#about to write, iclass 35, count 0 2006.252.07:52:01.22#ibcon#wrote, iclass 35, count 0 2006.252.07:52:01.22#ibcon#about to read 3, iclass 35, count 0 2006.252.07:52:01.24#ibcon#read 3, iclass 35, count 0 2006.252.07:52:01.24#ibcon#about to read 4, iclass 35, count 0 2006.252.07:52:01.24#ibcon#read 4, iclass 35, count 0 2006.252.07:52:01.24#ibcon#about to read 5, iclass 35, count 0 2006.252.07:52:01.24#ibcon#read 5, iclass 35, count 0 2006.252.07:52:01.24#ibcon#about to read 6, iclass 35, count 0 2006.252.07:52:01.24#ibcon#read 6, iclass 35, count 0 2006.252.07:52:01.24#ibcon#end of sib2, iclass 35, count 0 2006.252.07:52:01.24#ibcon#*after write, iclass 35, count 0 2006.252.07:52:01.24#ibcon#*before return 0, iclass 35, count 0 2006.252.07:52:01.24#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.252.07:52:01.24#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.252.07:52:01.24#ibcon#about to clear, iclass 35 cls_cnt 0 2006.252.07:52:01.24#ibcon#cleared, iclass 35 cls_cnt 0 2006.252.07:52:01.24$vc4f8/vblo=3,656.99 2006.252.07:52:01.24#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.252.07:52:01.24#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.252.07:52:01.24#ibcon#ireg 17 cls_cnt 0 2006.252.07:52:01.24#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.252.07:52:01.24#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.252.07:52:01.24#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.252.07:52:01.24#ibcon#enter wrdev, iclass 37, count 0 2006.252.07:52:01.24#ibcon#first serial, iclass 37, count 0 2006.252.07:52:01.24#ibcon#enter sib2, iclass 37, count 0 2006.252.07:52:01.24#ibcon#flushed, iclass 37, count 0 2006.252.07:52:01.24#ibcon#about to write, iclass 37, count 0 2006.252.07:52:01.24#ibcon#wrote, iclass 37, count 0 2006.252.07:52:01.24#ibcon#about to read 3, iclass 37, count 0 2006.252.07:52:01.26#ibcon#read 3, iclass 37, count 0 2006.252.07:52:01.26#ibcon#about to read 4, iclass 37, count 0 2006.252.07:52:01.26#ibcon#read 4, iclass 37, count 0 2006.252.07:52:01.26#ibcon#about to read 5, iclass 37, count 0 2006.252.07:52:01.26#ibcon#read 5, iclass 37, count 0 2006.252.07:52:01.26#ibcon#about to read 6, iclass 37, count 0 2006.252.07:52:01.26#ibcon#read 6, iclass 37, count 0 2006.252.07:52:01.26#ibcon#end of sib2, iclass 37, count 0 2006.252.07:52:01.26#ibcon#*mode == 0, iclass 37, count 0 2006.252.07:52:01.26#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.252.07:52:01.26#ibcon#[28=FRQ=03,656.99\r\n] 2006.252.07:52:01.26#ibcon#*before write, iclass 37, count 0 2006.252.07:52:01.26#ibcon#enter sib2, iclass 37, count 0 2006.252.07:52:01.26#ibcon#flushed, iclass 37, count 0 2006.252.07:52:01.26#ibcon#about to write, iclass 37, count 0 2006.252.07:52:01.26#ibcon#wrote, iclass 37, count 0 2006.252.07:52:01.26#ibcon#about to read 3, iclass 37, count 0 2006.252.07:52:01.30#ibcon#read 3, iclass 37, count 0 2006.252.07:52:01.30#ibcon#about to read 4, iclass 37, count 0 2006.252.07:52:01.30#ibcon#read 4, iclass 37, count 0 2006.252.07:52:01.30#ibcon#about to read 5, iclass 37, count 0 2006.252.07:52:01.30#ibcon#read 5, iclass 37, count 0 2006.252.07:52:01.30#ibcon#about to read 6, iclass 37, count 0 2006.252.07:52:01.30#ibcon#read 6, iclass 37, count 0 2006.252.07:52:01.30#ibcon#end of sib2, iclass 37, count 0 2006.252.07:52:01.30#ibcon#*after write, iclass 37, count 0 2006.252.07:52:01.30#ibcon#*before return 0, iclass 37, count 0 2006.252.07:52:01.30#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.252.07:52:01.30#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.252.07:52:01.30#ibcon#about to clear, iclass 37 cls_cnt 0 2006.252.07:52:01.30#ibcon#cleared, iclass 37 cls_cnt 0 2006.252.07:52:01.30$vc4f8/vb=3,4 2006.252.07:52:01.30#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.252.07:52:01.30#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.252.07:52:01.30#ibcon#ireg 11 cls_cnt 2 2006.252.07:52:01.30#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.252.07:52:01.36#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.252.07:52:01.36#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.252.07:52:01.36#ibcon#enter wrdev, iclass 39, count 2 2006.252.07:52:01.36#ibcon#first serial, iclass 39, count 2 2006.252.07:52:01.36#ibcon#enter sib2, iclass 39, count 2 2006.252.07:52:01.36#ibcon#flushed, iclass 39, count 2 2006.252.07:52:01.36#ibcon#about to write, iclass 39, count 2 2006.252.07:52:01.36#ibcon#wrote, iclass 39, count 2 2006.252.07:52:01.36#ibcon#about to read 3, iclass 39, count 2 2006.252.07:52:01.38#ibcon#read 3, iclass 39, count 2 2006.252.07:52:01.38#ibcon#about to read 4, iclass 39, count 2 2006.252.07:52:01.38#ibcon#read 4, iclass 39, count 2 2006.252.07:52:01.38#ibcon#about to read 5, iclass 39, count 2 2006.252.07:52:01.38#ibcon#read 5, iclass 39, count 2 2006.252.07:52:01.38#ibcon#about to read 6, iclass 39, count 2 2006.252.07:52:01.38#ibcon#read 6, iclass 39, count 2 2006.252.07:52:01.38#ibcon#end of sib2, iclass 39, count 2 2006.252.07:52:01.38#ibcon#*mode == 0, iclass 39, count 2 2006.252.07:52:01.38#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.252.07:52:01.38#ibcon#[27=AT03-04\r\n] 2006.252.07:52:01.38#ibcon#*before write, iclass 39, count 2 2006.252.07:52:01.38#ibcon#enter sib2, iclass 39, count 2 2006.252.07:52:01.38#ibcon#flushed, iclass 39, count 2 2006.252.07:52:01.38#ibcon#about to write, iclass 39, count 2 2006.252.07:52:01.38#ibcon#wrote, iclass 39, count 2 2006.252.07:52:01.38#ibcon#about to read 3, iclass 39, count 2 2006.252.07:52:01.41#ibcon#read 3, iclass 39, count 2 2006.252.07:52:01.41#ibcon#about to read 4, iclass 39, count 2 2006.252.07:52:01.41#ibcon#read 4, iclass 39, count 2 2006.252.07:52:01.41#ibcon#about to read 5, iclass 39, count 2 2006.252.07:52:01.41#ibcon#read 5, iclass 39, count 2 2006.252.07:52:01.41#ibcon#about to read 6, iclass 39, count 2 2006.252.07:52:01.41#ibcon#read 6, iclass 39, count 2 2006.252.07:52:01.41#ibcon#end of sib2, iclass 39, count 2 2006.252.07:52:01.41#ibcon#*after write, iclass 39, count 2 2006.252.07:52:01.41#ibcon#*before return 0, iclass 39, count 2 2006.252.07:52:01.41#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.252.07:52:01.41#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.252.07:52:01.41#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.252.07:52:01.41#ibcon#ireg 7 cls_cnt 0 2006.252.07:52:01.41#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.252.07:52:01.53#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.252.07:52:01.53#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.252.07:52:01.53#ibcon#enter wrdev, iclass 39, count 0 2006.252.07:52:01.53#ibcon#first serial, iclass 39, count 0 2006.252.07:52:01.53#ibcon#enter sib2, iclass 39, count 0 2006.252.07:52:01.53#ibcon#flushed, iclass 39, count 0 2006.252.07:52:01.53#ibcon#about to write, iclass 39, count 0 2006.252.07:52:01.53#ibcon#wrote, iclass 39, count 0 2006.252.07:52:01.53#ibcon#about to read 3, iclass 39, count 0 2006.252.07:52:01.55#ibcon#read 3, iclass 39, count 0 2006.252.07:52:01.55#ibcon#about to read 4, iclass 39, count 0 2006.252.07:52:01.55#ibcon#read 4, iclass 39, count 0 2006.252.07:52:01.55#ibcon#about to read 5, iclass 39, count 0 2006.252.07:52:01.55#ibcon#read 5, iclass 39, count 0 2006.252.07:52:01.55#ibcon#about to read 6, iclass 39, count 0 2006.252.07:52:01.55#ibcon#read 6, iclass 39, count 0 2006.252.07:52:01.55#ibcon#end of sib2, iclass 39, count 0 2006.252.07:52:01.55#ibcon#*mode == 0, iclass 39, count 0 2006.252.07:52:01.55#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.252.07:52:01.55#ibcon#[27=USB\r\n] 2006.252.07:52:01.55#ibcon#*before write, iclass 39, count 0 2006.252.07:52:01.55#ibcon#enter sib2, iclass 39, count 0 2006.252.07:52:01.55#ibcon#flushed, iclass 39, count 0 2006.252.07:52:01.55#ibcon#about to write, iclass 39, count 0 2006.252.07:52:01.55#ibcon#wrote, iclass 39, count 0 2006.252.07:52:01.55#ibcon#about to read 3, iclass 39, count 0 2006.252.07:52:01.58#ibcon#read 3, iclass 39, count 0 2006.252.07:52:01.58#ibcon#about to read 4, iclass 39, count 0 2006.252.07:52:01.58#ibcon#read 4, iclass 39, count 0 2006.252.07:52:01.58#ibcon#about to read 5, iclass 39, count 0 2006.252.07:52:01.58#ibcon#read 5, iclass 39, count 0 2006.252.07:52:01.58#ibcon#about to read 6, iclass 39, count 0 2006.252.07:52:01.58#ibcon#read 6, iclass 39, count 0 2006.252.07:52:01.58#ibcon#end of sib2, iclass 39, count 0 2006.252.07:52:01.58#ibcon#*after write, iclass 39, count 0 2006.252.07:52:01.58#ibcon#*before return 0, iclass 39, count 0 2006.252.07:52:01.58#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.252.07:52:01.58#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.252.07:52:01.58#ibcon#about to clear, iclass 39 cls_cnt 0 2006.252.07:52:01.58#ibcon#cleared, iclass 39 cls_cnt 0 2006.252.07:52:01.58$vc4f8/vblo=4,712.99 2006.252.07:52:01.58#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.252.07:52:01.58#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.252.07:52:01.58#ibcon#ireg 17 cls_cnt 0 2006.252.07:52:01.58#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.252.07:52:01.58#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.252.07:52:01.58#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.252.07:52:01.58#ibcon#enter wrdev, iclass 3, count 0 2006.252.07:52:01.58#ibcon#first serial, iclass 3, count 0 2006.252.07:52:01.58#ibcon#enter sib2, iclass 3, count 0 2006.252.07:52:01.58#ibcon#flushed, iclass 3, count 0 2006.252.07:52:01.58#ibcon#about to write, iclass 3, count 0 2006.252.07:52:01.58#ibcon#wrote, iclass 3, count 0 2006.252.07:52:01.58#ibcon#about to read 3, iclass 3, count 0 2006.252.07:52:01.60#ibcon#read 3, iclass 3, count 0 2006.252.07:52:01.60#ibcon#about to read 4, iclass 3, count 0 2006.252.07:52:01.60#ibcon#read 4, iclass 3, count 0 2006.252.07:52:01.60#ibcon#about to read 5, iclass 3, count 0 2006.252.07:52:01.60#ibcon#read 5, iclass 3, count 0 2006.252.07:52:01.60#ibcon#about to read 6, iclass 3, count 0 2006.252.07:52:01.60#ibcon#read 6, iclass 3, count 0 2006.252.07:52:01.60#ibcon#end of sib2, iclass 3, count 0 2006.252.07:52:01.60#ibcon#*mode == 0, iclass 3, count 0 2006.252.07:52:01.60#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.252.07:52:01.60#ibcon#[28=FRQ=04,712.99\r\n] 2006.252.07:52:01.60#ibcon#*before write, iclass 3, count 0 2006.252.07:52:01.60#ibcon#enter sib2, iclass 3, count 0 2006.252.07:52:01.60#ibcon#flushed, iclass 3, count 0 2006.252.07:52:01.60#ibcon#about to write, iclass 3, count 0 2006.252.07:52:01.60#ibcon#wrote, iclass 3, count 0 2006.252.07:52:01.60#ibcon#about to read 3, iclass 3, count 0 2006.252.07:52:01.64#ibcon#read 3, iclass 3, count 0 2006.252.07:52:01.64#ibcon#about to read 4, iclass 3, count 0 2006.252.07:52:01.64#ibcon#read 4, iclass 3, count 0 2006.252.07:52:01.64#ibcon#about to read 5, iclass 3, count 0 2006.252.07:52:01.64#ibcon#read 5, iclass 3, count 0 2006.252.07:52:01.64#ibcon#about to read 6, iclass 3, count 0 2006.252.07:52:01.64#ibcon#read 6, iclass 3, count 0 2006.252.07:52:01.64#ibcon#end of sib2, iclass 3, count 0 2006.252.07:52:01.64#ibcon#*after write, iclass 3, count 0 2006.252.07:52:01.64#ibcon#*before return 0, iclass 3, count 0 2006.252.07:52:01.64#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.252.07:52:01.64#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.252.07:52:01.64#ibcon#about to clear, iclass 3 cls_cnt 0 2006.252.07:52:01.64#ibcon#cleared, iclass 3 cls_cnt 0 2006.252.07:52:01.64$vc4f8/vb=4,4 2006.252.07:52:01.64#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.252.07:52:01.64#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.252.07:52:01.64#ibcon#ireg 11 cls_cnt 2 2006.252.07:52:01.64#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.252.07:52:01.70#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.252.07:52:01.70#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.252.07:52:01.70#ibcon#enter wrdev, iclass 5, count 2 2006.252.07:52:01.70#ibcon#first serial, iclass 5, count 2 2006.252.07:52:01.70#ibcon#enter sib2, iclass 5, count 2 2006.252.07:52:01.70#ibcon#flushed, iclass 5, count 2 2006.252.07:52:01.70#ibcon#about to write, iclass 5, count 2 2006.252.07:52:01.70#ibcon#wrote, iclass 5, count 2 2006.252.07:52:01.70#ibcon#about to read 3, iclass 5, count 2 2006.252.07:52:01.72#ibcon#read 3, iclass 5, count 2 2006.252.07:52:01.72#ibcon#about to read 4, iclass 5, count 2 2006.252.07:52:01.72#ibcon#read 4, iclass 5, count 2 2006.252.07:52:01.72#ibcon#about to read 5, iclass 5, count 2 2006.252.07:52:01.72#ibcon#read 5, iclass 5, count 2 2006.252.07:52:01.72#ibcon#about to read 6, iclass 5, count 2 2006.252.07:52:01.72#ibcon#read 6, iclass 5, count 2 2006.252.07:52:01.72#ibcon#end of sib2, iclass 5, count 2 2006.252.07:52:01.72#ibcon#*mode == 0, iclass 5, count 2 2006.252.07:52:01.72#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.252.07:52:01.72#ibcon#[27=AT04-04\r\n] 2006.252.07:52:01.72#ibcon#*before write, iclass 5, count 2 2006.252.07:52:01.72#ibcon#enter sib2, iclass 5, count 2 2006.252.07:52:01.72#ibcon#flushed, iclass 5, count 2 2006.252.07:52:01.72#ibcon#about to write, iclass 5, count 2 2006.252.07:52:01.72#ibcon#wrote, iclass 5, count 2 2006.252.07:52:01.72#ibcon#about to read 3, iclass 5, count 2 2006.252.07:52:01.75#ibcon#read 3, iclass 5, count 2 2006.252.07:52:01.75#ibcon#about to read 4, iclass 5, count 2 2006.252.07:52:01.75#ibcon#read 4, iclass 5, count 2 2006.252.07:52:01.75#ibcon#about to read 5, iclass 5, count 2 2006.252.07:52:01.75#ibcon#read 5, iclass 5, count 2 2006.252.07:52:01.75#ibcon#about to read 6, iclass 5, count 2 2006.252.07:52:01.75#ibcon#read 6, iclass 5, count 2 2006.252.07:52:01.75#ibcon#end of sib2, iclass 5, count 2 2006.252.07:52:01.75#ibcon#*after write, iclass 5, count 2 2006.252.07:52:01.75#ibcon#*before return 0, iclass 5, count 2 2006.252.07:52:01.75#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.252.07:52:01.75#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.252.07:52:01.75#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.252.07:52:01.75#ibcon#ireg 7 cls_cnt 0 2006.252.07:52:01.75#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.252.07:52:01.87#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.252.07:52:01.87#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.252.07:52:01.87#ibcon#enter wrdev, iclass 5, count 0 2006.252.07:52:01.87#ibcon#first serial, iclass 5, count 0 2006.252.07:52:01.87#ibcon#enter sib2, iclass 5, count 0 2006.252.07:52:01.87#ibcon#flushed, iclass 5, count 0 2006.252.07:52:01.87#ibcon#about to write, iclass 5, count 0 2006.252.07:52:01.87#ibcon#wrote, iclass 5, count 0 2006.252.07:52:01.87#ibcon#about to read 3, iclass 5, count 0 2006.252.07:52:01.89#ibcon#read 3, iclass 5, count 0 2006.252.07:52:01.89#ibcon#about to read 4, iclass 5, count 0 2006.252.07:52:01.89#ibcon#read 4, iclass 5, count 0 2006.252.07:52:01.89#ibcon#about to read 5, iclass 5, count 0 2006.252.07:52:01.89#ibcon#read 5, iclass 5, count 0 2006.252.07:52:01.89#ibcon#about to read 6, iclass 5, count 0 2006.252.07:52:01.89#ibcon#read 6, iclass 5, count 0 2006.252.07:52:01.89#ibcon#end of sib2, iclass 5, count 0 2006.252.07:52:01.89#ibcon#*mode == 0, iclass 5, count 0 2006.252.07:52:01.89#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.252.07:52:01.89#ibcon#[27=USB\r\n] 2006.252.07:52:01.89#ibcon#*before write, iclass 5, count 0 2006.252.07:52:01.89#ibcon#enter sib2, iclass 5, count 0 2006.252.07:52:01.89#ibcon#flushed, iclass 5, count 0 2006.252.07:52:01.89#ibcon#about to write, iclass 5, count 0 2006.252.07:52:01.89#ibcon#wrote, iclass 5, count 0 2006.252.07:52:01.89#ibcon#about to read 3, iclass 5, count 0 2006.252.07:52:01.92#ibcon#read 3, iclass 5, count 0 2006.252.07:52:01.92#ibcon#about to read 4, iclass 5, count 0 2006.252.07:52:01.92#ibcon#read 4, iclass 5, count 0 2006.252.07:52:01.92#ibcon#about to read 5, iclass 5, count 0 2006.252.07:52:01.92#ibcon#read 5, iclass 5, count 0 2006.252.07:52:01.92#ibcon#about to read 6, iclass 5, count 0 2006.252.07:52:01.92#ibcon#read 6, iclass 5, count 0 2006.252.07:52:01.92#ibcon#end of sib2, iclass 5, count 0 2006.252.07:52:01.92#ibcon#*after write, iclass 5, count 0 2006.252.07:52:01.92#ibcon#*before return 0, iclass 5, count 0 2006.252.07:52:01.92#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.252.07:52:01.92#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.252.07:52:01.92#ibcon#about to clear, iclass 5 cls_cnt 0 2006.252.07:52:01.92#ibcon#cleared, iclass 5 cls_cnt 0 2006.252.07:52:01.92$vc4f8/vblo=5,744.99 2006.252.07:52:01.92#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.252.07:52:01.92#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.252.07:52:01.92#ibcon#ireg 17 cls_cnt 0 2006.252.07:52:01.92#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.252.07:52:01.92#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.252.07:52:01.92#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.252.07:52:01.92#ibcon#enter wrdev, iclass 7, count 0 2006.252.07:52:01.92#ibcon#first serial, iclass 7, count 0 2006.252.07:52:01.92#ibcon#enter sib2, iclass 7, count 0 2006.252.07:52:01.92#ibcon#flushed, iclass 7, count 0 2006.252.07:52:01.92#ibcon#about to write, iclass 7, count 0 2006.252.07:52:01.92#ibcon#wrote, iclass 7, count 0 2006.252.07:52:01.92#ibcon#about to read 3, iclass 7, count 0 2006.252.07:52:01.95#ibcon#read 3, iclass 7, count 0 2006.252.07:52:01.95#ibcon#about to read 4, iclass 7, count 0 2006.252.07:52:01.95#ibcon#read 4, iclass 7, count 0 2006.252.07:52:01.95#ibcon#about to read 5, iclass 7, count 0 2006.252.07:52:01.95#ibcon#read 5, iclass 7, count 0 2006.252.07:52:01.95#ibcon#about to read 6, iclass 7, count 0 2006.252.07:52:01.95#ibcon#read 6, iclass 7, count 0 2006.252.07:52:01.95#ibcon#end of sib2, iclass 7, count 0 2006.252.07:52:01.95#ibcon#*mode == 0, iclass 7, count 0 2006.252.07:52:01.95#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.252.07:52:01.95#ibcon#[28=FRQ=05,744.99\r\n] 2006.252.07:52:01.95#ibcon#*before write, iclass 7, count 0 2006.252.07:52:01.95#ibcon#enter sib2, iclass 7, count 0 2006.252.07:52:01.95#ibcon#flushed, iclass 7, count 0 2006.252.07:52:01.95#ibcon#about to write, iclass 7, count 0 2006.252.07:52:01.95#ibcon#wrote, iclass 7, count 0 2006.252.07:52:01.95#ibcon#about to read 3, iclass 7, count 0 2006.252.07:52:01.99#ibcon#read 3, iclass 7, count 0 2006.252.07:52:01.99#ibcon#about to read 4, iclass 7, count 0 2006.252.07:52:01.99#ibcon#read 4, iclass 7, count 0 2006.252.07:52:01.99#ibcon#about to read 5, iclass 7, count 0 2006.252.07:52:01.99#ibcon#read 5, iclass 7, count 0 2006.252.07:52:01.99#ibcon#about to read 6, iclass 7, count 0 2006.252.07:52:01.99#ibcon#read 6, iclass 7, count 0 2006.252.07:52:01.99#ibcon#end of sib2, iclass 7, count 0 2006.252.07:52:01.99#ibcon#*after write, iclass 7, count 0 2006.252.07:52:01.99#ibcon#*before return 0, iclass 7, count 0 2006.252.07:52:01.99#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.252.07:52:01.99#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.252.07:52:01.99#ibcon#about to clear, iclass 7 cls_cnt 0 2006.252.07:52:01.99#ibcon#cleared, iclass 7 cls_cnt 0 2006.252.07:52:01.99$vc4f8/vb=5,4 2006.252.07:52:01.99#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.252.07:52:01.99#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.252.07:52:01.99#ibcon#ireg 11 cls_cnt 2 2006.252.07:52:01.99#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.252.07:52:02.04#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.252.07:52:02.04#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.252.07:52:02.04#ibcon#enter wrdev, iclass 11, count 2 2006.252.07:52:02.04#ibcon#first serial, iclass 11, count 2 2006.252.07:52:02.04#ibcon#enter sib2, iclass 11, count 2 2006.252.07:52:02.04#ibcon#flushed, iclass 11, count 2 2006.252.07:52:02.04#ibcon#about to write, iclass 11, count 2 2006.252.07:52:02.04#ibcon#wrote, iclass 11, count 2 2006.252.07:52:02.04#ibcon#about to read 3, iclass 11, count 2 2006.252.07:52:02.06#ibcon#read 3, iclass 11, count 2 2006.252.07:52:02.06#ibcon#about to read 4, iclass 11, count 2 2006.252.07:52:02.06#ibcon#read 4, iclass 11, count 2 2006.252.07:52:02.06#ibcon#about to read 5, iclass 11, count 2 2006.252.07:52:02.06#ibcon#read 5, iclass 11, count 2 2006.252.07:52:02.06#ibcon#about to read 6, iclass 11, count 2 2006.252.07:52:02.06#ibcon#read 6, iclass 11, count 2 2006.252.07:52:02.06#ibcon#end of sib2, iclass 11, count 2 2006.252.07:52:02.06#ibcon#*mode == 0, iclass 11, count 2 2006.252.07:52:02.06#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.252.07:52:02.06#ibcon#[27=AT05-04\r\n] 2006.252.07:52:02.06#ibcon#*before write, iclass 11, count 2 2006.252.07:52:02.06#ibcon#enter sib2, iclass 11, count 2 2006.252.07:52:02.06#ibcon#flushed, iclass 11, count 2 2006.252.07:52:02.06#ibcon#about to write, iclass 11, count 2 2006.252.07:52:02.06#ibcon#wrote, iclass 11, count 2 2006.252.07:52:02.06#ibcon#about to read 3, iclass 11, count 2 2006.252.07:52:02.09#ibcon#read 3, iclass 11, count 2 2006.252.07:52:02.09#ibcon#about to read 4, iclass 11, count 2 2006.252.07:52:02.09#ibcon#read 4, iclass 11, count 2 2006.252.07:52:02.09#ibcon#about to read 5, iclass 11, count 2 2006.252.07:52:02.09#ibcon#read 5, iclass 11, count 2 2006.252.07:52:02.09#ibcon#about to read 6, iclass 11, count 2 2006.252.07:52:02.09#ibcon#read 6, iclass 11, count 2 2006.252.07:52:02.09#ibcon#end of sib2, iclass 11, count 2 2006.252.07:52:02.09#ibcon#*after write, iclass 11, count 2 2006.252.07:52:02.09#ibcon#*before return 0, iclass 11, count 2 2006.252.07:52:02.09#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.252.07:52:02.09#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.252.07:52:02.09#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.252.07:52:02.09#ibcon#ireg 7 cls_cnt 0 2006.252.07:52:02.09#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.252.07:52:02.21#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.252.07:52:02.21#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.252.07:52:02.21#ibcon#enter wrdev, iclass 11, count 0 2006.252.07:52:02.21#ibcon#first serial, iclass 11, count 0 2006.252.07:52:02.21#ibcon#enter sib2, iclass 11, count 0 2006.252.07:52:02.21#ibcon#flushed, iclass 11, count 0 2006.252.07:52:02.21#ibcon#about to write, iclass 11, count 0 2006.252.07:52:02.21#ibcon#wrote, iclass 11, count 0 2006.252.07:52:02.21#ibcon#about to read 3, iclass 11, count 0 2006.252.07:52:02.23#ibcon#read 3, iclass 11, count 0 2006.252.07:52:02.23#ibcon#about to read 4, iclass 11, count 0 2006.252.07:52:02.23#ibcon#read 4, iclass 11, count 0 2006.252.07:52:02.23#ibcon#about to read 5, iclass 11, count 0 2006.252.07:52:02.23#ibcon#read 5, iclass 11, count 0 2006.252.07:52:02.23#ibcon#about to read 6, iclass 11, count 0 2006.252.07:52:02.23#ibcon#read 6, iclass 11, count 0 2006.252.07:52:02.23#ibcon#end of sib2, iclass 11, count 0 2006.252.07:52:02.23#ibcon#*mode == 0, iclass 11, count 0 2006.252.07:52:02.23#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.252.07:52:02.23#ibcon#[27=USB\r\n] 2006.252.07:52:02.23#ibcon#*before write, iclass 11, count 0 2006.252.07:52:02.23#ibcon#enter sib2, iclass 11, count 0 2006.252.07:52:02.23#ibcon#flushed, iclass 11, count 0 2006.252.07:52:02.23#ibcon#about to write, iclass 11, count 0 2006.252.07:52:02.23#ibcon#wrote, iclass 11, count 0 2006.252.07:52:02.23#ibcon#about to read 3, iclass 11, count 0 2006.252.07:52:02.26#ibcon#read 3, iclass 11, count 0 2006.252.07:52:02.26#ibcon#about to read 4, iclass 11, count 0 2006.252.07:52:02.26#ibcon#read 4, iclass 11, count 0 2006.252.07:52:02.26#ibcon#about to read 5, iclass 11, count 0 2006.252.07:52:02.26#ibcon#read 5, iclass 11, count 0 2006.252.07:52:02.26#ibcon#about to read 6, iclass 11, count 0 2006.252.07:52:02.26#ibcon#read 6, iclass 11, count 0 2006.252.07:52:02.26#ibcon#end of sib2, iclass 11, count 0 2006.252.07:52:02.26#ibcon#*after write, iclass 11, count 0 2006.252.07:52:02.26#ibcon#*before return 0, iclass 11, count 0 2006.252.07:52:02.26#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.252.07:52:02.26#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.252.07:52:02.26#ibcon#about to clear, iclass 11 cls_cnt 0 2006.252.07:52:02.26#ibcon#cleared, iclass 11 cls_cnt 0 2006.252.07:52:02.26$vc4f8/vblo=6,752.99 2006.252.07:52:02.26#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.252.07:52:02.26#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.252.07:52:02.26#ibcon#ireg 17 cls_cnt 0 2006.252.07:52:02.26#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.252.07:52:02.26#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.252.07:52:02.26#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.252.07:52:02.26#ibcon#enter wrdev, iclass 13, count 0 2006.252.07:52:02.26#ibcon#first serial, iclass 13, count 0 2006.252.07:52:02.26#ibcon#enter sib2, iclass 13, count 0 2006.252.07:52:02.26#ibcon#flushed, iclass 13, count 0 2006.252.07:52:02.26#ibcon#about to write, iclass 13, count 0 2006.252.07:52:02.26#ibcon#wrote, iclass 13, count 0 2006.252.07:52:02.26#ibcon#about to read 3, iclass 13, count 0 2006.252.07:52:02.28#ibcon#read 3, iclass 13, count 0 2006.252.07:52:02.28#ibcon#about to read 4, iclass 13, count 0 2006.252.07:52:02.28#ibcon#read 4, iclass 13, count 0 2006.252.07:52:02.28#ibcon#about to read 5, iclass 13, count 0 2006.252.07:52:02.28#ibcon#read 5, iclass 13, count 0 2006.252.07:52:02.28#ibcon#about to read 6, iclass 13, count 0 2006.252.07:52:02.28#ibcon#read 6, iclass 13, count 0 2006.252.07:52:02.28#ibcon#end of sib2, iclass 13, count 0 2006.252.07:52:02.28#ibcon#*mode == 0, iclass 13, count 0 2006.252.07:52:02.28#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.252.07:52:02.28#ibcon#[28=FRQ=06,752.99\r\n] 2006.252.07:52:02.28#ibcon#*before write, iclass 13, count 0 2006.252.07:52:02.28#ibcon#enter sib2, iclass 13, count 0 2006.252.07:52:02.28#ibcon#flushed, iclass 13, count 0 2006.252.07:52:02.28#ibcon#about to write, iclass 13, count 0 2006.252.07:52:02.28#ibcon#wrote, iclass 13, count 0 2006.252.07:52:02.28#ibcon#about to read 3, iclass 13, count 0 2006.252.07:52:02.32#ibcon#read 3, iclass 13, count 0 2006.252.07:52:02.32#ibcon#about to read 4, iclass 13, count 0 2006.252.07:52:02.32#ibcon#read 4, iclass 13, count 0 2006.252.07:52:02.32#ibcon#about to read 5, iclass 13, count 0 2006.252.07:52:02.32#ibcon#read 5, iclass 13, count 0 2006.252.07:52:02.32#ibcon#about to read 6, iclass 13, count 0 2006.252.07:52:02.32#ibcon#read 6, iclass 13, count 0 2006.252.07:52:02.32#ibcon#end of sib2, iclass 13, count 0 2006.252.07:52:02.32#ibcon#*after write, iclass 13, count 0 2006.252.07:52:02.32#ibcon#*before return 0, iclass 13, count 0 2006.252.07:52:02.32#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.252.07:52:02.32#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.252.07:52:02.32#ibcon#about to clear, iclass 13 cls_cnt 0 2006.252.07:52:02.32#ibcon#cleared, iclass 13 cls_cnt 0 2006.252.07:52:02.32$vc4f8/vb=6,4 2006.252.07:52:02.32#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.252.07:52:02.32#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.252.07:52:02.32#ibcon#ireg 11 cls_cnt 2 2006.252.07:52:02.32#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.252.07:52:02.38#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.252.07:52:02.38#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.252.07:52:02.38#ibcon#enter wrdev, iclass 15, count 2 2006.252.07:52:02.38#ibcon#first serial, iclass 15, count 2 2006.252.07:52:02.38#ibcon#enter sib2, iclass 15, count 2 2006.252.07:52:02.38#ibcon#flushed, iclass 15, count 2 2006.252.07:52:02.38#ibcon#about to write, iclass 15, count 2 2006.252.07:52:02.38#ibcon#wrote, iclass 15, count 2 2006.252.07:52:02.38#ibcon#about to read 3, iclass 15, count 2 2006.252.07:52:02.40#ibcon#read 3, iclass 15, count 2 2006.252.07:52:02.40#ibcon#about to read 4, iclass 15, count 2 2006.252.07:52:02.40#ibcon#read 4, iclass 15, count 2 2006.252.07:52:02.40#ibcon#about to read 5, iclass 15, count 2 2006.252.07:52:02.40#ibcon#read 5, iclass 15, count 2 2006.252.07:52:02.40#ibcon#about to read 6, iclass 15, count 2 2006.252.07:52:02.40#ibcon#read 6, iclass 15, count 2 2006.252.07:52:02.40#ibcon#end of sib2, iclass 15, count 2 2006.252.07:52:02.40#ibcon#*mode == 0, iclass 15, count 2 2006.252.07:52:02.40#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.252.07:52:02.40#ibcon#[27=AT06-04\r\n] 2006.252.07:52:02.40#ibcon#*before write, iclass 15, count 2 2006.252.07:52:02.40#ibcon#enter sib2, iclass 15, count 2 2006.252.07:52:02.40#ibcon#flushed, iclass 15, count 2 2006.252.07:52:02.40#ibcon#about to write, iclass 15, count 2 2006.252.07:52:02.40#ibcon#wrote, iclass 15, count 2 2006.252.07:52:02.40#ibcon#about to read 3, iclass 15, count 2 2006.252.07:52:02.43#ibcon#read 3, iclass 15, count 2 2006.252.07:52:02.43#ibcon#about to read 4, iclass 15, count 2 2006.252.07:52:02.43#ibcon#read 4, iclass 15, count 2 2006.252.07:52:02.43#ibcon#about to read 5, iclass 15, count 2 2006.252.07:52:02.43#ibcon#read 5, iclass 15, count 2 2006.252.07:52:02.43#ibcon#about to read 6, iclass 15, count 2 2006.252.07:52:02.43#ibcon#read 6, iclass 15, count 2 2006.252.07:52:02.43#ibcon#end of sib2, iclass 15, count 2 2006.252.07:52:02.43#ibcon#*after write, iclass 15, count 2 2006.252.07:52:02.43#ibcon#*before return 0, iclass 15, count 2 2006.252.07:52:02.43#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.252.07:52:02.43#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.252.07:52:02.43#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.252.07:52:02.43#ibcon#ireg 7 cls_cnt 0 2006.252.07:52:02.43#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.252.07:52:02.55#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.252.07:52:02.55#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.252.07:52:02.55#ibcon#enter wrdev, iclass 15, count 0 2006.252.07:52:02.55#ibcon#first serial, iclass 15, count 0 2006.252.07:52:02.55#ibcon#enter sib2, iclass 15, count 0 2006.252.07:52:02.55#ibcon#flushed, iclass 15, count 0 2006.252.07:52:02.55#ibcon#about to write, iclass 15, count 0 2006.252.07:52:02.55#ibcon#wrote, iclass 15, count 0 2006.252.07:52:02.55#ibcon#about to read 3, iclass 15, count 0 2006.252.07:52:02.57#ibcon#read 3, iclass 15, count 0 2006.252.07:52:02.57#ibcon#about to read 4, iclass 15, count 0 2006.252.07:52:02.57#ibcon#read 4, iclass 15, count 0 2006.252.07:52:02.57#ibcon#about to read 5, iclass 15, count 0 2006.252.07:52:02.57#ibcon#read 5, iclass 15, count 0 2006.252.07:52:02.57#ibcon#about to read 6, iclass 15, count 0 2006.252.07:52:02.57#ibcon#read 6, iclass 15, count 0 2006.252.07:52:02.57#ibcon#end of sib2, iclass 15, count 0 2006.252.07:52:02.57#ibcon#*mode == 0, iclass 15, count 0 2006.252.07:52:02.57#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.252.07:52:02.57#ibcon#[27=USB\r\n] 2006.252.07:52:02.57#ibcon#*before write, iclass 15, count 0 2006.252.07:52:02.57#ibcon#enter sib2, iclass 15, count 0 2006.252.07:52:02.57#ibcon#flushed, iclass 15, count 0 2006.252.07:52:02.57#ibcon#about to write, iclass 15, count 0 2006.252.07:52:02.57#ibcon#wrote, iclass 15, count 0 2006.252.07:52:02.57#ibcon#about to read 3, iclass 15, count 0 2006.252.07:52:02.60#ibcon#read 3, iclass 15, count 0 2006.252.07:52:02.60#ibcon#about to read 4, iclass 15, count 0 2006.252.07:52:02.60#ibcon#read 4, iclass 15, count 0 2006.252.07:52:02.60#ibcon#about to read 5, iclass 15, count 0 2006.252.07:52:02.60#ibcon#read 5, iclass 15, count 0 2006.252.07:52:02.60#ibcon#about to read 6, iclass 15, count 0 2006.252.07:52:02.60#ibcon#read 6, iclass 15, count 0 2006.252.07:52:02.60#ibcon#end of sib2, iclass 15, count 0 2006.252.07:52:02.60#ibcon#*after write, iclass 15, count 0 2006.252.07:52:02.60#ibcon#*before return 0, iclass 15, count 0 2006.252.07:52:02.60#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.252.07:52:02.60#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.252.07:52:02.60#ibcon#about to clear, iclass 15 cls_cnt 0 2006.252.07:52:02.60#ibcon#cleared, iclass 15 cls_cnt 0 2006.252.07:52:02.60$vc4f8/vabw=wide 2006.252.07:52:02.60#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.252.07:52:02.60#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.252.07:52:02.60#ibcon#ireg 8 cls_cnt 0 2006.252.07:52:02.60#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.252.07:52:02.60#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.252.07:52:02.60#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.252.07:52:02.60#ibcon#enter wrdev, iclass 17, count 0 2006.252.07:52:02.60#ibcon#first serial, iclass 17, count 0 2006.252.07:52:02.60#ibcon#enter sib2, iclass 17, count 0 2006.252.07:52:02.60#ibcon#flushed, iclass 17, count 0 2006.252.07:52:02.60#ibcon#about to write, iclass 17, count 0 2006.252.07:52:02.60#ibcon#wrote, iclass 17, count 0 2006.252.07:52:02.60#ibcon#about to read 3, iclass 17, count 0 2006.252.07:52:02.63#ibcon#read 3, iclass 17, count 0 2006.252.07:52:02.63#ibcon#about to read 4, iclass 17, count 0 2006.252.07:52:02.63#ibcon#read 4, iclass 17, count 0 2006.252.07:52:02.63#ibcon#about to read 5, iclass 17, count 0 2006.252.07:52:02.63#ibcon#read 5, iclass 17, count 0 2006.252.07:52:02.63#ibcon#about to read 6, iclass 17, count 0 2006.252.07:52:02.63#ibcon#read 6, iclass 17, count 0 2006.252.07:52:02.63#ibcon#end of sib2, iclass 17, count 0 2006.252.07:52:02.63#ibcon#*mode == 0, iclass 17, count 0 2006.252.07:52:02.63#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.252.07:52:02.63#ibcon#[25=BW32\r\n] 2006.252.07:52:02.63#ibcon#*before write, iclass 17, count 0 2006.252.07:52:02.63#ibcon#enter sib2, iclass 17, count 0 2006.252.07:52:02.63#ibcon#flushed, iclass 17, count 0 2006.252.07:52:02.63#ibcon#about to write, iclass 17, count 0 2006.252.07:52:02.63#ibcon#wrote, iclass 17, count 0 2006.252.07:52:02.63#ibcon#about to read 3, iclass 17, count 0 2006.252.07:52:02.66#ibcon#read 3, iclass 17, count 0 2006.252.07:52:02.66#ibcon#about to read 4, iclass 17, count 0 2006.252.07:52:02.66#ibcon#read 4, iclass 17, count 0 2006.252.07:52:02.66#ibcon#about to read 5, iclass 17, count 0 2006.252.07:52:02.66#ibcon#read 5, iclass 17, count 0 2006.252.07:52:02.66#ibcon#about to read 6, iclass 17, count 0 2006.252.07:52:02.66#ibcon#read 6, iclass 17, count 0 2006.252.07:52:02.66#ibcon#end of sib2, iclass 17, count 0 2006.252.07:52:02.66#ibcon#*after write, iclass 17, count 0 2006.252.07:52:02.66#ibcon#*before return 0, iclass 17, count 0 2006.252.07:52:02.66#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.252.07:52:02.66#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.252.07:52:02.66#ibcon#about to clear, iclass 17 cls_cnt 0 2006.252.07:52:02.66#ibcon#cleared, iclass 17 cls_cnt 0 2006.252.07:52:02.66$vc4f8/vbbw=wide 2006.252.07:52:02.66#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.252.07:52:02.66#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.252.07:52:02.66#ibcon#ireg 8 cls_cnt 0 2006.252.07:52:02.66#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.252.07:52:02.72#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.252.07:52:02.72#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.252.07:52:02.72#ibcon#enter wrdev, iclass 19, count 0 2006.252.07:52:02.72#ibcon#first serial, iclass 19, count 0 2006.252.07:52:02.72#ibcon#enter sib2, iclass 19, count 0 2006.252.07:52:02.72#ibcon#flushed, iclass 19, count 0 2006.252.07:52:02.72#ibcon#about to write, iclass 19, count 0 2006.252.07:52:02.72#ibcon#wrote, iclass 19, count 0 2006.252.07:52:02.72#ibcon#about to read 3, iclass 19, count 0 2006.252.07:52:02.74#ibcon#read 3, iclass 19, count 0 2006.252.07:52:02.74#ibcon#about to read 4, iclass 19, count 0 2006.252.07:52:02.74#ibcon#read 4, iclass 19, count 0 2006.252.07:52:02.74#ibcon#about to read 5, iclass 19, count 0 2006.252.07:52:02.74#ibcon#read 5, iclass 19, count 0 2006.252.07:52:02.74#ibcon#about to read 6, iclass 19, count 0 2006.252.07:52:02.74#ibcon#read 6, iclass 19, count 0 2006.252.07:52:02.74#ibcon#end of sib2, iclass 19, count 0 2006.252.07:52:02.74#ibcon#*mode == 0, iclass 19, count 0 2006.252.07:52:02.74#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.252.07:52:02.74#ibcon#[27=BW32\r\n] 2006.252.07:52:02.74#ibcon#*before write, iclass 19, count 0 2006.252.07:52:02.74#ibcon#enter sib2, iclass 19, count 0 2006.252.07:52:02.74#ibcon#flushed, iclass 19, count 0 2006.252.07:52:02.74#ibcon#about to write, iclass 19, count 0 2006.252.07:52:02.74#ibcon#wrote, iclass 19, count 0 2006.252.07:52:02.74#ibcon#about to read 3, iclass 19, count 0 2006.252.07:52:02.77#ibcon#read 3, iclass 19, count 0 2006.252.07:52:02.77#ibcon#about to read 4, iclass 19, count 0 2006.252.07:52:02.77#ibcon#read 4, iclass 19, count 0 2006.252.07:52:02.77#ibcon#about to read 5, iclass 19, count 0 2006.252.07:52:02.77#ibcon#read 5, iclass 19, count 0 2006.252.07:52:02.77#ibcon#about to read 6, iclass 19, count 0 2006.252.07:52:02.77#ibcon#read 6, iclass 19, count 0 2006.252.07:52:02.77#ibcon#end of sib2, iclass 19, count 0 2006.252.07:52:02.77#ibcon#*after write, iclass 19, count 0 2006.252.07:52:02.77#ibcon#*before return 0, iclass 19, count 0 2006.252.07:52:02.77#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.252.07:52:02.77#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.252.07:52:02.77#ibcon#about to clear, iclass 19 cls_cnt 0 2006.252.07:52:02.77#ibcon#cleared, iclass 19 cls_cnt 0 2006.252.07:52:02.77$4f8m12a/ifd4f 2006.252.07:52:02.77$ifd4f/lo= 2006.252.07:52:02.77$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.252.07:52:02.77$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.252.07:52:02.77$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.252.07:52:02.77$ifd4f/patch= 2006.252.07:52:02.77$ifd4f/patch=lo1,a1,a2,a3,a4 2006.252.07:52:02.77$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.252.07:52:02.77$ifd4f/patch=lo3,a5,a6,a7,a8 2006.252.07:52:02.77$4f8m12a/"form=m,16.000,1:2 2006.252.07:52:02.77$4f8m12a/"tpicd 2006.252.07:52:02.77$4f8m12a/echo=off 2006.252.07:52:02.77$4f8m12a/xlog=off 2006.252.07:52:02.77:!2006.252.07:52:40 2006.252.07:52:21.14#trakl#Source acquired 2006.252.07:52:23.14#flagr#flagr/antenna,acquired 2006.252.07:52:40.00:preob 2006.252.07:52:40.13/onsource/TRACKING 2006.252.07:52:40.13:!2006.252.07:52:50 2006.252.07:52:50.00:data_valid=on 2006.252.07:52:50.00:midob 2006.252.07:52:50.13/onsource/TRACKING 2006.252.07:52:50.13/wx/27.39,1011.2,90 2006.252.07:52:50.32/cable/+6.4122E-03 2006.252.07:52:51.41/va/01,08,usb,yes,33,34 2006.252.07:52:51.41/va/02,07,usb,yes,32,34 2006.252.07:52:51.41/va/03,06,usb,yes,35,35 2006.252.07:52:51.41/va/04,07,usb,yes,33,36 2006.252.07:52:51.41/va/05,07,usb,yes,36,38 2006.252.07:52:51.41/va/06,07,usb,yes,31,31 2006.252.07:52:51.41/va/07,07,usb,yes,31,31 2006.252.07:52:51.41/va/08,07,usb,yes,34,33 2006.252.07:52:51.64/valo/01,532.99,yes,locked 2006.252.07:52:51.64/valo/02,572.99,yes,locked 2006.252.07:52:51.64/valo/03,672.99,yes,locked 2006.252.07:52:51.64/valo/04,832.99,yes,locked 2006.252.07:52:51.64/valo/05,652.99,yes,locked 2006.252.07:52:51.64/valo/06,772.99,yes,locked 2006.252.07:52:51.64/valo/07,832.99,yes,locked 2006.252.07:52:51.64/valo/08,852.99,yes,locked 2006.252.07:52:52.73/vb/01,04,usb,yes,30,29 2006.252.07:52:52.73/vb/02,05,usb,yes,28,29 2006.252.07:52:52.73/vb/03,04,usb,yes,28,32 2006.252.07:52:52.73/vb/04,04,usb,yes,29,29 2006.252.07:52:52.73/vb/05,04,usb,yes,28,32 2006.252.07:52:52.73/vb/06,04,usb,yes,29,32 2006.252.07:52:52.73/vb/07,04,usb,yes,31,31 2006.252.07:52:52.73/vb/08,04,usb,yes,28,32 2006.252.07:52:52.96/vblo/01,632.99,yes,locked 2006.252.07:52:52.96/vblo/02,640.99,yes,locked 2006.252.07:52:52.96/vblo/03,656.99,yes,locked 2006.252.07:52:52.96/vblo/04,712.99,yes,locked 2006.252.07:52:52.96/vblo/05,744.99,yes,locked 2006.252.07:52:52.96/vblo/06,752.99,yes,locked 2006.252.07:52:52.96/vblo/07,734.99,yes,locked 2006.252.07:52:52.96/vblo/08,744.99,yes,locked 2006.252.07:52:53.11/vabw/8 2006.252.07:52:53.26/vbbw/8 2006.252.07:52:53.35/xfe/off,on,14.2 2006.252.07:52:53.73/ifatt/23,28,28,28 2006.252.07:52:54.07/fmout-gps/S +4.80E-07 2006.252.07:52:54.11:!2006.252.07:53:50 2006.252.07:53:50.00:data_valid=off 2006.252.07:53:50.00:postob 2006.252.07:53:50.15/cable/+6.4128E-03 2006.252.07:53:50.15/wx/27.38,1011.2,90 2006.252.07:53:51.07/fmout-gps/S +4.80E-07 2006.252.07:53:51.07:scan_name=252-0755,k06252,60 2006.252.07:53:51.08:source=4c39.25,092703.01,390220.9,2000.0,ccw 2006.252.07:53:51.13#flagr#flagr/antenna,new-source 2006.252.07:53:52.13:checkk5 2006.252.07:53:52.50/chk_autoobs//k5ts1/ autoobs is running! 2006.252.07:53:52.88/chk_autoobs//k5ts2/ autoobs is running! 2006.252.07:53:53.26/chk_autoobs//k5ts3/ autoobs is running! 2006.252.07:53:53.64/chk_autoobs//k5ts4/ autoobs is running! 2006.252.07:53:54.01/chk_obsdata//k5ts1/T2520752??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.07:53:54.38/chk_obsdata//k5ts2/T2520752??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.07:53:54.75/chk_obsdata//k5ts3/T2520752??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.07:53:55.11/chk_obsdata//k5ts4/T2520752??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.07:53:55.80/k5log//k5ts1_log_newline 2006.252.07:53:56.50/k5log//k5ts2_log_newline 2006.252.07:53:57.19/k5log//k5ts3_log_newline 2006.252.07:53:57.88/k5log//k5ts4_log_newline 2006.252.07:53:57.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.252.07:53:57.90:4f8m12a=2 2006.252.07:53:57.90$4f8m12a/echo=on 2006.252.07:53:57.90$4f8m12a/pcalon 2006.252.07:53:57.90$pcalon/"no phase cal control is implemented here 2006.252.07:53:57.90$4f8m12a/"tpicd=stop 2006.252.07:53:57.90$4f8m12a/vc4f8 2006.252.07:53:57.90$vc4f8/valo=1,532.99 2006.252.07:53:57.91#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.252.07:53:57.91#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.252.07:53:57.91#ibcon#ireg 17 cls_cnt 0 2006.252.07:53:57.91#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.252.07:53:57.91#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.252.07:53:57.91#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.252.07:53:57.91#ibcon#enter wrdev, iclass 34, count 0 2006.252.07:53:57.91#ibcon#first serial, iclass 34, count 0 2006.252.07:53:57.91#ibcon#enter sib2, iclass 34, count 0 2006.252.07:53:57.91#ibcon#flushed, iclass 34, count 0 2006.252.07:53:57.91#ibcon#about to write, iclass 34, count 0 2006.252.07:53:57.91#ibcon#wrote, iclass 34, count 0 2006.252.07:53:57.91#ibcon#about to read 3, iclass 34, count 0 2006.252.07:53:57.95#ibcon#read 3, iclass 34, count 0 2006.252.07:53:57.95#ibcon#about to read 4, iclass 34, count 0 2006.252.07:53:57.95#ibcon#read 4, iclass 34, count 0 2006.252.07:53:57.95#ibcon#about to read 5, iclass 34, count 0 2006.252.07:53:57.95#ibcon#read 5, iclass 34, count 0 2006.252.07:53:57.95#ibcon#about to read 6, iclass 34, count 0 2006.252.07:53:57.95#ibcon#read 6, iclass 34, count 0 2006.252.07:53:57.95#ibcon#end of sib2, iclass 34, count 0 2006.252.07:53:57.95#ibcon#*mode == 0, iclass 34, count 0 2006.252.07:53:57.95#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.252.07:53:57.95#ibcon#[26=FRQ=01,532.99\r\n] 2006.252.07:53:57.95#ibcon#*before write, iclass 34, count 0 2006.252.07:53:57.95#ibcon#enter sib2, iclass 34, count 0 2006.252.07:53:57.95#ibcon#flushed, iclass 34, count 0 2006.252.07:53:57.95#ibcon#about to write, iclass 34, count 0 2006.252.07:53:57.95#ibcon#wrote, iclass 34, count 0 2006.252.07:53:57.95#ibcon#about to read 3, iclass 34, count 0 2006.252.07:53:57.99#ibcon#read 3, iclass 34, count 0 2006.252.07:53:57.99#ibcon#about to read 4, iclass 34, count 0 2006.252.07:53:57.99#ibcon#read 4, iclass 34, count 0 2006.252.07:53:57.99#ibcon#about to read 5, iclass 34, count 0 2006.252.07:53:57.99#ibcon#read 5, iclass 34, count 0 2006.252.07:53:57.99#ibcon#about to read 6, iclass 34, count 0 2006.252.07:53:57.99#ibcon#read 6, iclass 34, count 0 2006.252.07:53:57.99#ibcon#end of sib2, iclass 34, count 0 2006.252.07:53:57.99#ibcon#*after write, iclass 34, count 0 2006.252.07:53:57.99#ibcon#*before return 0, iclass 34, count 0 2006.252.07:53:57.99#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.252.07:53:57.99#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.252.07:53:57.99#ibcon#about to clear, iclass 34 cls_cnt 0 2006.252.07:53:57.99#ibcon#cleared, iclass 34 cls_cnt 0 2006.252.07:53:57.99$vc4f8/va=1,8 2006.252.07:53:57.99#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.252.07:53:57.99#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.252.07:53:57.99#ibcon#ireg 11 cls_cnt 2 2006.252.07:53:57.99#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.252.07:53:57.99#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.252.07:53:57.99#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.252.07:53:57.99#ibcon#enter wrdev, iclass 36, count 2 2006.252.07:53:57.99#ibcon#first serial, iclass 36, count 2 2006.252.07:53:57.99#ibcon#enter sib2, iclass 36, count 2 2006.252.07:53:57.99#ibcon#flushed, iclass 36, count 2 2006.252.07:53:57.99#ibcon#about to write, iclass 36, count 2 2006.252.07:53:57.99#ibcon#wrote, iclass 36, count 2 2006.252.07:53:57.99#ibcon#about to read 3, iclass 36, count 2 2006.252.07:53:58.01#ibcon#read 3, iclass 36, count 2 2006.252.07:53:58.01#ibcon#about to read 4, iclass 36, count 2 2006.252.07:53:58.01#ibcon#read 4, iclass 36, count 2 2006.252.07:53:58.01#ibcon#about to read 5, iclass 36, count 2 2006.252.07:53:58.01#ibcon#read 5, iclass 36, count 2 2006.252.07:53:58.01#ibcon#about to read 6, iclass 36, count 2 2006.252.07:53:58.01#ibcon#read 6, iclass 36, count 2 2006.252.07:53:58.01#ibcon#end of sib2, iclass 36, count 2 2006.252.07:53:58.01#ibcon#*mode == 0, iclass 36, count 2 2006.252.07:53:58.01#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.252.07:53:58.01#ibcon#[25=AT01-08\r\n] 2006.252.07:53:58.01#ibcon#*before write, iclass 36, count 2 2006.252.07:53:58.01#ibcon#enter sib2, iclass 36, count 2 2006.252.07:53:58.01#ibcon#flushed, iclass 36, count 2 2006.252.07:53:58.01#ibcon#about to write, iclass 36, count 2 2006.252.07:53:58.01#ibcon#wrote, iclass 36, count 2 2006.252.07:53:58.01#ibcon#about to read 3, iclass 36, count 2 2006.252.07:53:58.04#ibcon#read 3, iclass 36, count 2 2006.252.07:53:58.04#ibcon#about to read 4, iclass 36, count 2 2006.252.07:53:58.04#ibcon#read 4, iclass 36, count 2 2006.252.07:53:58.04#ibcon#about to read 5, iclass 36, count 2 2006.252.07:53:58.04#ibcon#read 5, iclass 36, count 2 2006.252.07:53:58.04#ibcon#about to read 6, iclass 36, count 2 2006.252.07:53:58.04#ibcon#read 6, iclass 36, count 2 2006.252.07:53:58.04#ibcon#end of sib2, iclass 36, count 2 2006.252.07:53:58.04#ibcon#*after write, iclass 36, count 2 2006.252.07:53:58.04#ibcon#*before return 0, iclass 36, count 2 2006.252.07:53:58.04#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.252.07:53:58.04#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.252.07:53:58.04#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.252.07:53:58.04#ibcon#ireg 7 cls_cnt 0 2006.252.07:53:58.04#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.252.07:53:58.16#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.252.07:53:58.16#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.252.07:53:58.16#ibcon#enter wrdev, iclass 36, count 0 2006.252.07:53:58.16#ibcon#first serial, iclass 36, count 0 2006.252.07:53:58.16#ibcon#enter sib2, iclass 36, count 0 2006.252.07:53:58.16#ibcon#flushed, iclass 36, count 0 2006.252.07:53:58.16#ibcon#about to write, iclass 36, count 0 2006.252.07:53:58.16#ibcon#wrote, iclass 36, count 0 2006.252.07:53:58.16#ibcon#about to read 3, iclass 36, count 0 2006.252.07:53:58.18#ibcon#read 3, iclass 36, count 0 2006.252.07:53:58.18#ibcon#about to read 4, iclass 36, count 0 2006.252.07:53:58.18#ibcon#read 4, iclass 36, count 0 2006.252.07:53:58.18#ibcon#about to read 5, iclass 36, count 0 2006.252.07:53:58.18#ibcon#read 5, iclass 36, count 0 2006.252.07:53:58.18#ibcon#about to read 6, iclass 36, count 0 2006.252.07:53:58.18#ibcon#read 6, iclass 36, count 0 2006.252.07:53:58.18#ibcon#end of sib2, iclass 36, count 0 2006.252.07:53:58.18#ibcon#*mode == 0, iclass 36, count 0 2006.252.07:53:58.18#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.252.07:53:58.18#ibcon#[25=USB\r\n] 2006.252.07:53:58.18#ibcon#*before write, iclass 36, count 0 2006.252.07:53:58.18#ibcon#enter sib2, iclass 36, count 0 2006.252.07:53:58.18#ibcon#flushed, iclass 36, count 0 2006.252.07:53:58.18#ibcon#about to write, iclass 36, count 0 2006.252.07:53:58.18#ibcon#wrote, iclass 36, count 0 2006.252.07:53:58.18#ibcon#about to read 3, iclass 36, count 0 2006.252.07:53:58.21#ibcon#read 3, iclass 36, count 0 2006.252.07:53:58.21#ibcon#about to read 4, iclass 36, count 0 2006.252.07:53:58.21#ibcon#read 4, iclass 36, count 0 2006.252.07:53:58.21#ibcon#about to read 5, iclass 36, count 0 2006.252.07:53:58.21#ibcon#read 5, iclass 36, count 0 2006.252.07:53:58.21#ibcon#about to read 6, iclass 36, count 0 2006.252.07:53:58.21#ibcon#read 6, iclass 36, count 0 2006.252.07:53:58.21#ibcon#end of sib2, iclass 36, count 0 2006.252.07:53:58.21#ibcon#*after write, iclass 36, count 0 2006.252.07:53:58.21#ibcon#*before return 0, iclass 36, count 0 2006.252.07:53:58.21#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.252.07:53:58.21#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.252.07:53:58.21#ibcon#about to clear, iclass 36 cls_cnt 0 2006.252.07:53:58.21#ibcon#cleared, iclass 36 cls_cnt 0 2006.252.07:53:58.21$vc4f8/valo=2,572.99 2006.252.07:53:58.21#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.252.07:53:58.21#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.252.07:53:58.21#ibcon#ireg 17 cls_cnt 0 2006.252.07:53:58.21#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.252.07:53:58.21#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.252.07:53:58.21#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.252.07:53:58.21#ibcon#enter wrdev, iclass 38, count 0 2006.252.07:53:58.21#ibcon#first serial, iclass 38, count 0 2006.252.07:53:58.21#ibcon#enter sib2, iclass 38, count 0 2006.252.07:53:58.21#ibcon#flushed, iclass 38, count 0 2006.252.07:53:58.21#ibcon#about to write, iclass 38, count 0 2006.252.07:53:58.21#ibcon#wrote, iclass 38, count 0 2006.252.07:53:58.21#ibcon#about to read 3, iclass 38, count 0 2006.252.07:53:58.23#ibcon#read 3, iclass 38, count 0 2006.252.07:53:58.23#ibcon#about to read 4, iclass 38, count 0 2006.252.07:53:58.23#ibcon#read 4, iclass 38, count 0 2006.252.07:53:58.23#ibcon#about to read 5, iclass 38, count 0 2006.252.07:53:58.23#ibcon#read 5, iclass 38, count 0 2006.252.07:53:58.23#ibcon#about to read 6, iclass 38, count 0 2006.252.07:53:58.23#ibcon#read 6, iclass 38, count 0 2006.252.07:53:58.23#ibcon#end of sib2, iclass 38, count 0 2006.252.07:53:58.23#ibcon#*mode == 0, iclass 38, count 0 2006.252.07:53:58.23#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.252.07:53:58.23#ibcon#[26=FRQ=02,572.99\r\n] 2006.252.07:53:58.23#ibcon#*before write, iclass 38, count 0 2006.252.07:53:58.23#ibcon#enter sib2, iclass 38, count 0 2006.252.07:53:58.23#ibcon#flushed, iclass 38, count 0 2006.252.07:53:58.23#ibcon#about to write, iclass 38, count 0 2006.252.07:53:58.23#ibcon#wrote, iclass 38, count 0 2006.252.07:53:58.23#ibcon#about to read 3, iclass 38, count 0 2006.252.07:53:58.27#ibcon#read 3, iclass 38, count 0 2006.252.07:53:58.27#ibcon#about to read 4, iclass 38, count 0 2006.252.07:53:58.27#ibcon#read 4, iclass 38, count 0 2006.252.07:53:58.27#ibcon#about to read 5, iclass 38, count 0 2006.252.07:53:58.27#ibcon#read 5, iclass 38, count 0 2006.252.07:53:58.27#ibcon#about to read 6, iclass 38, count 0 2006.252.07:53:58.27#ibcon#read 6, iclass 38, count 0 2006.252.07:53:58.27#ibcon#end of sib2, iclass 38, count 0 2006.252.07:53:58.27#ibcon#*after write, iclass 38, count 0 2006.252.07:53:58.27#ibcon#*before return 0, iclass 38, count 0 2006.252.07:53:58.27#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.252.07:53:58.27#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.252.07:53:58.27#ibcon#about to clear, iclass 38 cls_cnt 0 2006.252.07:53:58.27#ibcon#cleared, iclass 38 cls_cnt 0 2006.252.07:53:58.27$vc4f8/va=2,7 2006.252.07:53:58.27#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.252.07:53:58.27#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.252.07:53:58.27#ibcon#ireg 11 cls_cnt 2 2006.252.07:53:58.27#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.252.07:53:58.34#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.252.07:53:58.34#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.252.07:53:58.34#ibcon#enter wrdev, iclass 40, count 2 2006.252.07:53:58.34#ibcon#first serial, iclass 40, count 2 2006.252.07:53:58.34#ibcon#enter sib2, iclass 40, count 2 2006.252.07:53:58.34#ibcon#flushed, iclass 40, count 2 2006.252.07:53:58.34#ibcon#about to write, iclass 40, count 2 2006.252.07:53:58.34#ibcon#wrote, iclass 40, count 2 2006.252.07:53:58.34#ibcon#about to read 3, iclass 40, count 2 2006.252.07:53:58.35#ibcon#read 3, iclass 40, count 2 2006.252.07:53:58.35#ibcon#about to read 4, iclass 40, count 2 2006.252.07:53:58.35#ibcon#read 4, iclass 40, count 2 2006.252.07:53:58.35#ibcon#about to read 5, iclass 40, count 2 2006.252.07:53:58.35#ibcon#read 5, iclass 40, count 2 2006.252.07:53:58.35#ibcon#about to read 6, iclass 40, count 2 2006.252.07:53:58.35#ibcon#read 6, iclass 40, count 2 2006.252.07:53:58.35#ibcon#end of sib2, iclass 40, count 2 2006.252.07:53:58.35#ibcon#*mode == 0, iclass 40, count 2 2006.252.07:53:58.35#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.252.07:53:58.35#ibcon#[25=AT02-07\r\n] 2006.252.07:53:58.35#ibcon#*before write, iclass 40, count 2 2006.252.07:53:58.35#ibcon#enter sib2, iclass 40, count 2 2006.252.07:53:58.35#ibcon#flushed, iclass 40, count 2 2006.252.07:53:58.35#ibcon#about to write, iclass 40, count 2 2006.252.07:53:58.35#ibcon#wrote, iclass 40, count 2 2006.252.07:53:58.35#ibcon#about to read 3, iclass 40, count 2 2006.252.07:53:58.38#ibcon#read 3, iclass 40, count 2 2006.252.07:53:58.38#ibcon#about to read 4, iclass 40, count 2 2006.252.07:53:58.38#ibcon#read 4, iclass 40, count 2 2006.252.07:53:58.38#ibcon#about to read 5, iclass 40, count 2 2006.252.07:53:58.38#ibcon#read 5, iclass 40, count 2 2006.252.07:53:58.38#ibcon#about to read 6, iclass 40, count 2 2006.252.07:53:58.38#ibcon#read 6, iclass 40, count 2 2006.252.07:53:58.38#ibcon#end of sib2, iclass 40, count 2 2006.252.07:53:58.38#ibcon#*after write, iclass 40, count 2 2006.252.07:53:58.38#ibcon#*before return 0, iclass 40, count 2 2006.252.07:53:58.38#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.252.07:53:58.38#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.252.07:53:58.38#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.252.07:53:58.38#ibcon#ireg 7 cls_cnt 0 2006.252.07:53:58.38#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.252.07:53:58.50#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.252.07:53:58.50#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.252.07:53:58.50#ibcon#enter wrdev, iclass 40, count 0 2006.252.07:53:58.50#ibcon#first serial, iclass 40, count 0 2006.252.07:53:58.50#ibcon#enter sib2, iclass 40, count 0 2006.252.07:53:58.50#ibcon#flushed, iclass 40, count 0 2006.252.07:53:58.50#ibcon#about to write, iclass 40, count 0 2006.252.07:53:58.50#ibcon#wrote, iclass 40, count 0 2006.252.07:53:58.50#ibcon#about to read 3, iclass 40, count 0 2006.252.07:53:58.52#ibcon#read 3, iclass 40, count 0 2006.252.07:53:58.52#ibcon#about to read 4, iclass 40, count 0 2006.252.07:53:58.52#ibcon#read 4, iclass 40, count 0 2006.252.07:53:58.52#ibcon#about to read 5, iclass 40, count 0 2006.252.07:53:58.52#ibcon#read 5, iclass 40, count 0 2006.252.07:53:58.52#ibcon#about to read 6, iclass 40, count 0 2006.252.07:53:58.52#ibcon#read 6, iclass 40, count 0 2006.252.07:53:58.52#ibcon#end of sib2, iclass 40, count 0 2006.252.07:53:58.52#ibcon#*mode == 0, iclass 40, count 0 2006.252.07:53:58.52#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.252.07:53:58.52#ibcon#[25=USB\r\n] 2006.252.07:53:58.52#ibcon#*before write, iclass 40, count 0 2006.252.07:53:58.52#ibcon#enter sib2, iclass 40, count 0 2006.252.07:53:58.52#ibcon#flushed, iclass 40, count 0 2006.252.07:53:58.52#ibcon#about to write, iclass 40, count 0 2006.252.07:53:58.52#ibcon#wrote, iclass 40, count 0 2006.252.07:53:58.52#ibcon#about to read 3, iclass 40, count 0 2006.252.07:53:58.55#ibcon#read 3, iclass 40, count 0 2006.252.07:53:58.55#ibcon#about to read 4, iclass 40, count 0 2006.252.07:53:58.55#ibcon#read 4, iclass 40, count 0 2006.252.07:53:58.55#ibcon#about to read 5, iclass 40, count 0 2006.252.07:53:58.55#ibcon#read 5, iclass 40, count 0 2006.252.07:53:58.55#ibcon#about to read 6, iclass 40, count 0 2006.252.07:53:58.55#ibcon#read 6, iclass 40, count 0 2006.252.07:53:58.55#ibcon#end of sib2, iclass 40, count 0 2006.252.07:53:58.55#ibcon#*after write, iclass 40, count 0 2006.252.07:53:58.55#ibcon#*before return 0, iclass 40, count 0 2006.252.07:53:58.55#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.252.07:53:58.55#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.252.07:53:58.55#ibcon#about to clear, iclass 40 cls_cnt 0 2006.252.07:53:58.55#ibcon#cleared, iclass 40 cls_cnt 0 2006.252.07:53:58.55$vc4f8/valo=3,672.99 2006.252.07:53:58.55#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.252.07:53:58.55#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.252.07:53:58.55#ibcon#ireg 17 cls_cnt 0 2006.252.07:53:58.55#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.252.07:53:58.55#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.252.07:53:58.55#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.252.07:53:58.55#ibcon#enter wrdev, iclass 4, count 0 2006.252.07:53:58.55#ibcon#first serial, iclass 4, count 0 2006.252.07:53:58.55#ibcon#enter sib2, iclass 4, count 0 2006.252.07:53:58.55#ibcon#flushed, iclass 4, count 0 2006.252.07:53:58.55#ibcon#about to write, iclass 4, count 0 2006.252.07:53:58.55#ibcon#wrote, iclass 4, count 0 2006.252.07:53:58.55#ibcon#about to read 3, iclass 4, count 0 2006.252.07:53:58.57#ibcon#read 3, iclass 4, count 0 2006.252.07:53:58.57#ibcon#about to read 4, iclass 4, count 0 2006.252.07:53:58.57#ibcon#read 4, iclass 4, count 0 2006.252.07:53:58.57#ibcon#about to read 5, iclass 4, count 0 2006.252.07:53:58.57#ibcon#read 5, iclass 4, count 0 2006.252.07:53:58.57#ibcon#about to read 6, iclass 4, count 0 2006.252.07:53:58.57#ibcon#read 6, iclass 4, count 0 2006.252.07:53:58.57#ibcon#end of sib2, iclass 4, count 0 2006.252.07:53:58.57#ibcon#*mode == 0, iclass 4, count 0 2006.252.07:53:58.57#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.252.07:53:58.57#ibcon#[26=FRQ=03,672.99\r\n] 2006.252.07:53:58.57#ibcon#*before write, iclass 4, count 0 2006.252.07:53:58.57#ibcon#enter sib2, iclass 4, count 0 2006.252.07:53:58.57#ibcon#flushed, iclass 4, count 0 2006.252.07:53:58.57#ibcon#about to write, iclass 4, count 0 2006.252.07:53:58.57#ibcon#wrote, iclass 4, count 0 2006.252.07:53:58.57#ibcon#about to read 3, iclass 4, count 0 2006.252.07:53:58.61#ibcon#read 3, iclass 4, count 0 2006.252.07:53:58.61#ibcon#about to read 4, iclass 4, count 0 2006.252.07:53:58.61#ibcon#read 4, iclass 4, count 0 2006.252.07:53:58.61#ibcon#about to read 5, iclass 4, count 0 2006.252.07:53:58.61#ibcon#read 5, iclass 4, count 0 2006.252.07:53:58.61#ibcon#about to read 6, iclass 4, count 0 2006.252.07:53:58.61#ibcon#read 6, iclass 4, count 0 2006.252.07:53:58.61#ibcon#end of sib2, iclass 4, count 0 2006.252.07:53:58.61#ibcon#*after write, iclass 4, count 0 2006.252.07:53:58.61#ibcon#*before return 0, iclass 4, count 0 2006.252.07:53:58.61#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.252.07:53:58.61#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.252.07:53:58.61#ibcon#about to clear, iclass 4 cls_cnt 0 2006.252.07:53:58.61#ibcon#cleared, iclass 4 cls_cnt 0 2006.252.07:53:58.61$vc4f8/va=3,6 2006.252.07:53:58.61#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.252.07:53:58.61#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.252.07:53:58.61#ibcon#ireg 11 cls_cnt 2 2006.252.07:53:58.61#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.252.07:53:58.68#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.252.07:53:58.68#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.252.07:53:58.68#ibcon#enter wrdev, iclass 6, count 2 2006.252.07:53:58.68#ibcon#first serial, iclass 6, count 2 2006.252.07:53:58.68#ibcon#enter sib2, iclass 6, count 2 2006.252.07:53:58.68#ibcon#flushed, iclass 6, count 2 2006.252.07:53:58.68#ibcon#about to write, iclass 6, count 2 2006.252.07:53:58.68#ibcon#wrote, iclass 6, count 2 2006.252.07:53:58.68#ibcon#about to read 3, iclass 6, count 2 2006.252.07:53:58.69#ibcon#read 3, iclass 6, count 2 2006.252.07:53:58.69#ibcon#about to read 4, iclass 6, count 2 2006.252.07:53:58.69#ibcon#read 4, iclass 6, count 2 2006.252.07:53:58.69#ibcon#about to read 5, iclass 6, count 2 2006.252.07:53:58.69#ibcon#read 5, iclass 6, count 2 2006.252.07:53:58.69#ibcon#about to read 6, iclass 6, count 2 2006.252.07:53:58.69#ibcon#read 6, iclass 6, count 2 2006.252.07:53:58.69#ibcon#end of sib2, iclass 6, count 2 2006.252.07:53:58.69#ibcon#*mode == 0, iclass 6, count 2 2006.252.07:53:58.69#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.252.07:53:58.69#ibcon#[25=AT03-06\r\n] 2006.252.07:53:58.69#ibcon#*before write, iclass 6, count 2 2006.252.07:53:58.69#ibcon#enter sib2, iclass 6, count 2 2006.252.07:53:58.69#ibcon#flushed, iclass 6, count 2 2006.252.07:53:58.69#ibcon#about to write, iclass 6, count 2 2006.252.07:53:58.69#ibcon#wrote, iclass 6, count 2 2006.252.07:53:58.69#ibcon#about to read 3, iclass 6, count 2 2006.252.07:53:58.72#ibcon#read 3, iclass 6, count 2 2006.252.07:53:58.72#ibcon#about to read 4, iclass 6, count 2 2006.252.07:53:58.72#ibcon#read 4, iclass 6, count 2 2006.252.07:53:58.72#ibcon#about to read 5, iclass 6, count 2 2006.252.07:53:58.72#ibcon#read 5, iclass 6, count 2 2006.252.07:53:58.72#ibcon#about to read 6, iclass 6, count 2 2006.252.07:53:58.72#ibcon#read 6, iclass 6, count 2 2006.252.07:53:58.72#ibcon#end of sib2, iclass 6, count 2 2006.252.07:53:58.72#ibcon#*after write, iclass 6, count 2 2006.252.07:53:58.72#ibcon#*before return 0, iclass 6, count 2 2006.252.07:53:58.72#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.252.07:53:58.72#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.252.07:53:58.72#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.252.07:53:58.72#ibcon#ireg 7 cls_cnt 0 2006.252.07:53:58.72#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.252.07:53:58.84#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.252.07:53:58.84#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.252.07:53:58.84#ibcon#enter wrdev, iclass 6, count 0 2006.252.07:53:58.84#ibcon#first serial, iclass 6, count 0 2006.252.07:53:58.84#ibcon#enter sib2, iclass 6, count 0 2006.252.07:53:58.84#ibcon#flushed, iclass 6, count 0 2006.252.07:53:58.84#ibcon#about to write, iclass 6, count 0 2006.252.07:53:58.84#ibcon#wrote, iclass 6, count 0 2006.252.07:53:58.84#ibcon#about to read 3, iclass 6, count 0 2006.252.07:53:58.86#ibcon#read 3, iclass 6, count 0 2006.252.07:53:58.86#ibcon#about to read 4, iclass 6, count 0 2006.252.07:53:58.86#ibcon#read 4, iclass 6, count 0 2006.252.07:53:58.86#ibcon#about to read 5, iclass 6, count 0 2006.252.07:53:58.86#ibcon#read 5, iclass 6, count 0 2006.252.07:53:58.86#ibcon#about to read 6, iclass 6, count 0 2006.252.07:53:58.86#ibcon#read 6, iclass 6, count 0 2006.252.07:53:58.86#ibcon#end of sib2, iclass 6, count 0 2006.252.07:53:58.86#ibcon#*mode == 0, iclass 6, count 0 2006.252.07:53:58.86#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.252.07:53:58.86#ibcon#[25=USB\r\n] 2006.252.07:53:58.86#ibcon#*before write, iclass 6, count 0 2006.252.07:53:58.86#ibcon#enter sib2, iclass 6, count 0 2006.252.07:53:58.86#ibcon#flushed, iclass 6, count 0 2006.252.07:53:58.86#ibcon#about to write, iclass 6, count 0 2006.252.07:53:58.86#ibcon#wrote, iclass 6, count 0 2006.252.07:53:58.86#ibcon#about to read 3, iclass 6, count 0 2006.252.07:53:58.89#ibcon#read 3, iclass 6, count 0 2006.252.07:53:58.89#ibcon#about to read 4, iclass 6, count 0 2006.252.07:53:58.89#ibcon#read 4, iclass 6, count 0 2006.252.07:53:58.89#ibcon#about to read 5, iclass 6, count 0 2006.252.07:53:58.89#ibcon#read 5, iclass 6, count 0 2006.252.07:53:58.89#ibcon#about to read 6, iclass 6, count 0 2006.252.07:53:58.89#ibcon#read 6, iclass 6, count 0 2006.252.07:53:58.89#ibcon#end of sib2, iclass 6, count 0 2006.252.07:53:58.89#ibcon#*after write, iclass 6, count 0 2006.252.07:53:58.89#ibcon#*before return 0, iclass 6, count 0 2006.252.07:53:58.89#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.252.07:53:58.89#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.252.07:53:58.89#ibcon#about to clear, iclass 6 cls_cnt 0 2006.252.07:53:58.89#ibcon#cleared, iclass 6 cls_cnt 0 2006.252.07:53:58.89$vc4f8/valo=4,832.99 2006.252.07:53:58.89#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.252.07:53:58.89#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.252.07:53:58.89#ibcon#ireg 17 cls_cnt 0 2006.252.07:53:58.89#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.252.07:53:58.89#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.252.07:53:58.89#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.252.07:53:58.89#ibcon#enter wrdev, iclass 10, count 0 2006.252.07:53:58.89#ibcon#first serial, iclass 10, count 0 2006.252.07:53:58.89#ibcon#enter sib2, iclass 10, count 0 2006.252.07:53:58.89#ibcon#flushed, iclass 10, count 0 2006.252.07:53:58.89#ibcon#about to write, iclass 10, count 0 2006.252.07:53:58.89#ibcon#wrote, iclass 10, count 0 2006.252.07:53:58.89#ibcon#about to read 3, iclass 10, count 0 2006.252.07:53:58.91#ibcon#read 3, iclass 10, count 0 2006.252.07:53:58.91#ibcon#about to read 4, iclass 10, count 0 2006.252.07:53:58.91#ibcon#read 4, iclass 10, count 0 2006.252.07:53:58.91#ibcon#about to read 5, iclass 10, count 0 2006.252.07:53:58.91#ibcon#read 5, iclass 10, count 0 2006.252.07:53:58.91#ibcon#about to read 6, iclass 10, count 0 2006.252.07:53:58.91#ibcon#read 6, iclass 10, count 0 2006.252.07:53:58.91#ibcon#end of sib2, iclass 10, count 0 2006.252.07:53:58.91#ibcon#*mode == 0, iclass 10, count 0 2006.252.07:53:58.91#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.252.07:53:58.91#ibcon#[26=FRQ=04,832.99\r\n] 2006.252.07:53:58.91#ibcon#*before write, iclass 10, count 0 2006.252.07:53:58.91#ibcon#enter sib2, iclass 10, count 0 2006.252.07:53:58.91#ibcon#flushed, iclass 10, count 0 2006.252.07:53:58.91#ibcon#about to write, iclass 10, count 0 2006.252.07:53:58.91#ibcon#wrote, iclass 10, count 0 2006.252.07:53:58.91#ibcon#about to read 3, iclass 10, count 0 2006.252.07:53:58.95#ibcon#read 3, iclass 10, count 0 2006.252.07:53:58.95#ibcon#about to read 4, iclass 10, count 0 2006.252.07:53:58.95#ibcon#read 4, iclass 10, count 0 2006.252.07:53:58.95#ibcon#about to read 5, iclass 10, count 0 2006.252.07:53:58.95#ibcon#read 5, iclass 10, count 0 2006.252.07:53:58.95#ibcon#about to read 6, iclass 10, count 0 2006.252.07:53:58.95#ibcon#read 6, iclass 10, count 0 2006.252.07:53:58.95#ibcon#end of sib2, iclass 10, count 0 2006.252.07:53:58.95#ibcon#*after write, iclass 10, count 0 2006.252.07:53:58.95#ibcon#*before return 0, iclass 10, count 0 2006.252.07:53:58.95#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.252.07:53:58.95#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.252.07:53:58.95#ibcon#about to clear, iclass 10 cls_cnt 0 2006.252.07:53:58.95#ibcon#cleared, iclass 10 cls_cnt 0 2006.252.07:53:58.95$vc4f8/va=4,7 2006.252.07:53:58.95#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.252.07:53:58.95#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.252.07:53:58.95#ibcon#ireg 11 cls_cnt 2 2006.252.07:53:58.95#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.252.07:53:59.01#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.252.07:53:59.01#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.252.07:53:59.01#ibcon#enter wrdev, iclass 12, count 2 2006.252.07:53:59.01#ibcon#first serial, iclass 12, count 2 2006.252.07:53:59.01#ibcon#enter sib2, iclass 12, count 2 2006.252.07:53:59.01#ibcon#flushed, iclass 12, count 2 2006.252.07:53:59.01#ibcon#about to write, iclass 12, count 2 2006.252.07:53:59.01#ibcon#wrote, iclass 12, count 2 2006.252.07:53:59.01#ibcon#about to read 3, iclass 12, count 2 2006.252.07:53:59.03#ibcon#read 3, iclass 12, count 2 2006.252.07:53:59.03#ibcon#about to read 4, iclass 12, count 2 2006.252.07:53:59.03#ibcon#read 4, iclass 12, count 2 2006.252.07:53:59.03#ibcon#about to read 5, iclass 12, count 2 2006.252.07:53:59.03#ibcon#read 5, iclass 12, count 2 2006.252.07:53:59.03#ibcon#about to read 6, iclass 12, count 2 2006.252.07:53:59.03#ibcon#read 6, iclass 12, count 2 2006.252.07:53:59.03#ibcon#end of sib2, iclass 12, count 2 2006.252.07:53:59.03#ibcon#*mode == 0, iclass 12, count 2 2006.252.07:53:59.03#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.252.07:53:59.03#ibcon#[25=AT04-07\r\n] 2006.252.07:53:59.03#ibcon#*before write, iclass 12, count 2 2006.252.07:53:59.03#ibcon#enter sib2, iclass 12, count 2 2006.252.07:53:59.03#ibcon#flushed, iclass 12, count 2 2006.252.07:53:59.03#ibcon#about to write, iclass 12, count 2 2006.252.07:53:59.03#ibcon#wrote, iclass 12, count 2 2006.252.07:53:59.03#ibcon#about to read 3, iclass 12, count 2 2006.252.07:53:59.06#ibcon#read 3, iclass 12, count 2 2006.252.07:53:59.06#ibcon#about to read 4, iclass 12, count 2 2006.252.07:53:59.06#ibcon#read 4, iclass 12, count 2 2006.252.07:53:59.06#ibcon#about to read 5, iclass 12, count 2 2006.252.07:53:59.06#ibcon#read 5, iclass 12, count 2 2006.252.07:53:59.06#ibcon#about to read 6, iclass 12, count 2 2006.252.07:53:59.06#ibcon#read 6, iclass 12, count 2 2006.252.07:53:59.06#ibcon#end of sib2, iclass 12, count 2 2006.252.07:53:59.06#ibcon#*after write, iclass 12, count 2 2006.252.07:53:59.06#ibcon#*before return 0, iclass 12, count 2 2006.252.07:53:59.06#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.252.07:53:59.06#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.252.07:53:59.06#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.252.07:53:59.06#ibcon#ireg 7 cls_cnt 0 2006.252.07:53:59.06#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.252.07:53:59.18#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.252.07:53:59.18#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.252.07:53:59.18#ibcon#enter wrdev, iclass 12, count 0 2006.252.07:53:59.18#ibcon#first serial, iclass 12, count 0 2006.252.07:53:59.18#ibcon#enter sib2, iclass 12, count 0 2006.252.07:53:59.18#ibcon#flushed, iclass 12, count 0 2006.252.07:53:59.18#ibcon#about to write, iclass 12, count 0 2006.252.07:53:59.18#ibcon#wrote, iclass 12, count 0 2006.252.07:53:59.18#ibcon#about to read 3, iclass 12, count 0 2006.252.07:53:59.20#ibcon#read 3, iclass 12, count 0 2006.252.07:53:59.20#ibcon#about to read 4, iclass 12, count 0 2006.252.07:53:59.20#ibcon#read 4, iclass 12, count 0 2006.252.07:53:59.20#ibcon#about to read 5, iclass 12, count 0 2006.252.07:53:59.20#ibcon#read 5, iclass 12, count 0 2006.252.07:53:59.20#ibcon#about to read 6, iclass 12, count 0 2006.252.07:53:59.20#ibcon#read 6, iclass 12, count 0 2006.252.07:53:59.20#ibcon#end of sib2, iclass 12, count 0 2006.252.07:53:59.20#ibcon#*mode == 0, iclass 12, count 0 2006.252.07:53:59.20#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.252.07:53:59.20#ibcon#[25=USB\r\n] 2006.252.07:53:59.20#ibcon#*before write, iclass 12, count 0 2006.252.07:53:59.20#ibcon#enter sib2, iclass 12, count 0 2006.252.07:53:59.20#ibcon#flushed, iclass 12, count 0 2006.252.07:53:59.20#ibcon#about to write, iclass 12, count 0 2006.252.07:53:59.20#ibcon#wrote, iclass 12, count 0 2006.252.07:53:59.20#ibcon#about to read 3, iclass 12, count 0 2006.252.07:53:59.23#ibcon#read 3, iclass 12, count 0 2006.252.07:53:59.23#ibcon#about to read 4, iclass 12, count 0 2006.252.07:53:59.23#ibcon#read 4, iclass 12, count 0 2006.252.07:53:59.23#ibcon#about to read 5, iclass 12, count 0 2006.252.07:53:59.23#ibcon#read 5, iclass 12, count 0 2006.252.07:53:59.23#ibcon#about to read 6, iclass 12, count 0 2006.252.07:53:59.23#ibcon#read 6, iclass 12, count 0 2006.252.07:53:59.23#ibcon#end of sib2, iclass 12, count 0 2006.252.07:53:59.23#ibcon#*after write, iclass 12, count 0 2006.252.07:53:59.23#ibcon#*before return 0, iclass 12, count 0 2006.252.07:53:59.23#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.252.07:53:59.23#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.252.07:53:59.23#ibcon#about to clear, iclass 12 cls_cnt 0 2006.252.07:53:59.23#ibcon#cleared, iclass 12 cls_cnt 0 2006.252.07:53:59.23$vc4f8/valo=5,652.99 2006.252.07:53:59.23#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.252.07:53:59.23#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.252.07:53:59.23#ibcon#ireg 17 cls_cnt 0 2006.252.07:53:59.23#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.252.07:53:59.23#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.252.07:53:59.23#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.252.07:53:59.23#ibcon#enter wrdev, iclass 14, count 0 2006.252.07:53:59.23#ibcon#first serial, iclass 14, count 0 2006.252.07:53:59.23#ibcon#enter sib2, iclass 14, count 0 2006.252.07:53:59.23#ibcon#flushed, iclass 14, count 0 2006.252.07:53:59.23#ibcon#about to write, iclass 14, count 0 2006.252.07:53:59.23#ibcon#wrote, iclass 14, count 0 2006.252.07:53:59.23#ibcon#about to read 3, iclass 14, count 0 2006.252.07:53:59.25#ibcon#read 3, iclass 14, count 0 2006.252.07:53:59.25#ibcon#about to read 4, iclass 14, count 0 2006.252.07:53:59.25#ibcon#read 4, iclass 14, count 0 2006.252.07:53:59.25#ibcon#about to read 5, iclass 14, count 0 2006.252.07:53:59.25#ibcon#read 5, iclass 14, count 0 2006.252.07:53:59.25#ibcon#about to read 6, iclass 14, count 0 2006.252.07:53:59.25#ibcon#read 6, iclass 14, count 0 2006.252.07:53:59.25#ibcon#end of sib2, iclass 14, count 0 2006.252.07:53:59.25#ibcon#*mode == 0, iclass 14, count 0 2006.252.07:53:59.25#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.252.07:53:59.25#ibcon#[26=FRQ=05,652.99\r\n] 2006.252.07:53:59.25#ibcon#*before write, iclass 14, count 0 2006.252.07:53:59.25#ibcon#enter sib2, iclass 14, count 0 2006.252.07:53:59.25#ibcon#flushed, iclass 14, count 0 2006.252.07:53:59.25#ibcon#about to write, iclass 14, count 0 2006.252.07:53:59.25#ibcon#wrote, iclass 14, count 0 2006.252.07:53:59.25#ibcon#about to read 3, iclass 14, count 0 2006.252.07:53:59.29#ibcon#read 3, iclass 14, count 0 2006.252.07:53:59.29#ibcon#about to read 4, iclass 14, count 0 2006.252.07:53:59.29#ibcon#read 4, iclass 14, count 0 2006.252.07:53:59.29#ibcon#about to read 5, iclass 14, count 0 2006.252.07:53:59.29#ibcon#read 5, iclass 14, count 0 2006.252.07:53:59.29#ibcon#about to read 6, iclass 14, count 0 2006.252.07:53:59.29#ibcon#read 6, iclass 14, count 0 2006.252.07:53:59.29#ibcon#end of sib2, iclass 14, count 0 2006.252.07:53:59.29#ibcon#*after write, iclass 14, count 0 2006.252.07:53:59.29#ibcon#*before return 0, iclass 14, count 0 2006.252.07:53:59.29#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.252.07:53:59.29#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.252.07:53:59.29#ibcon#about to clear, iclass 14 cls_cnt 0 2006.252.07:53:59.29#ibcon#cleared, iclass 14 cls_cnt 0 2006.252.07:53:59.29$vc4f8/va=5,7 2006.252.07:53:59.29#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.252.07:53:59.29#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.252.07:53:59.29#ibcon#ireg 11 cls_cnt 2 2006.252.07:53:59.29#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.252.07:53:59.35#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.252.07:53:59.35#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.252.07:53:59.35#ibcon#enter wrdev, iclass 16, count 2 2006.252.07:53:59.35#ibcon#first serial, iclass 16, count 2 2006.252.07:53:59.35#ibcon#enter sib2, iclass 16, count 2 2006.252.07:53:59.35#ibcon#flushed, iclass 16, count 2 2006.252.07:53:59.35#ibcon#about to write, iclass 16, count 2 2006.252.07:53:59.35#ibcon#wrote, iclass 16, count 2 2006.252.07:53:59.35#ibcon#about to read 3, iclass 16, count 2 2006.252.07:53:59.37#ibcon#read 3, iclass 16, count 2 2006.252.07:53:59.37#ibcon#about to read 4, iclass 16, count 2 2006.252.07:53:59.37#ibcon#read 4, iclass 16, count 2 2006.252.07:53:59.37#ibcon#about to read 5, iclass 16, count 2 2006.252.07:53:59.37#ibcon#read 5, iclass 16, count 2 2006.252.07:53:59.37#ibcon#about to read 6, iclass 16, count 2 2006.252.07:53:59.37#ibcon#read 6, iclass 16, count 2 2006.252.07:53:59.37#ibcon#end of sib2, iclass 16, count 2 2006.252.07:53:59.37#ibcon#*mode == 0, iclass 16, count 2 2006.252.07:53:59.37#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.252.07:53:59.37#ibcon#[25=AT05-07\r\n] 2006.252.07:53:59.37#ibcon#*before write, iclass 16, count 2 2006.252.07:53:59.37#ibcon#enter sib2, iclass 16, count 2 2006.252.07:53:59.37#ibcon#flushed, iclass 16, count 2 2006.252.07:53:59.37#ibcon#about to write, iclass 16, count 2 2006.252.07:53:59.37#ibcon#wrote, iclass 16, count 2 2006.252.07:53:59.37#ibcon#about to read 3, iclass 16, count 2 2006.252.07:53:59.40#ibcon#read 3, iclass 16, count 2 2006.252.07:53:59.40#ibcon#about to read 4, iclass 16, count 2 2006.252.07:53:59.40#ibcon#read 4, iclass 16, count 2 2006.252.07:53:59.40#ibcon#about to read 5, iclass 16, count 2 2006.252.07:53:59.40#ibcon#read 5, iclass 16, count 2 2006.252.07:53:59.40#ibcon#about to read 6, iclass 16, count 2 2006.252.07:53:59.40#ibcon#read 6, iclass 16, count 2 2006.252.07:53:59.40#ibcon#end of sib2, iclass 16, count 2 2006.252.07:53:59.40#ibcon#*after write, iclass 16, count 2 2006.252.07:53:59.40#ibcon#*before return 0, iclass 16, count 2 2006.252.07:53:59.40#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.252.07:53:59.40#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.252.07:53:59.40#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.252.07:53:59.40#ibcon#ireg 7 cls_cnt 0 2006.252.07:53:59.40#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.252.07:53:59.52#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.252.07:53:59.52#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.252.07:53:59.52#ibcon#enter wrdev, iclass 16, count 0 2006.252.07:53:59.52#ibcon#first serial, iclass 16, count 0 2006.252.07:53:59.52#ibcon#enter sib2, iclass 16, count 0 2006.252.07:53:59.52#ibcon#flushed, iclass 16, count 0 2006.252.07:53:59.52#ibcon#about to write, iclass 16, count 0 2006.252.07:53:59.52#ibcon#wrote, iclass 16, count 0 2006.252.07:53:59.52#ibcon#about to read 3, iclass 16, count 0 2006.252.07:53:59.54#ibcon#read 3, iclass 16, count 0 2006.252.07:53:59.54#ibcon#about to read 4, iclass 16, count 0 2006.252.07:53:59.54#ibcon#read 4, iclass 16, count 0 2006.252.07:53:59.54#ibcon#about to read 5, iclass 16, count 0 2006.252.07:53:59.54#ibcon#read 5, iclass 16, count 0 2006.252.07:53:59.54#ibcon#about to read 6, iclass 16, count 0 2006.252.07:53:59.54#ibcon#read 6, iclass 16, count 0 2006.252.07:53:59.54#ibcon#end of sib2, iclass 16, count 0 2006.252.07:53:59.54#ibcon#*mode == 0, iclass 16, count 0 2006.252.07:53:59.54#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.252.07:53:59.54#ibcon#[25=USB\r\n] 2006.252.07:53:59.54#ibcon#*before write, iclass 16, count 0 2006.252.07:53:59.54#ibcon#enter sib2, iclass 16, count 0 2006.252.07:53:59.54#ibcon#flushed, iclass 16, count 0 2006.252.07:53:59.54#ibcon#about to write, iclass 16, count 0 2006.252.07:53:59.54#ibcon#wrote, iclass 16, count 0 2006.252.07:53:59.54#ibcon#about to read 3, iclass 16, count 0 2006.252.07:53:59.57#ibcon#read 3, iclass 16, count 0 2006.252.07:53:59.57#ibcon#about to read 4, iclass 16, count 0 2006.252.07:53:59.57#ibcon#read 4, iclass 16, count 0 2006.252.07:53:59.57#ibcon#about to read 5, iclass 16, count 0 2006.252.07:53:59.57#ibcon#read 5, iclass 16, count 0 2006.252.07:53:59.57#ibcon#about to read 6, iclass 16, count 0 2006.252.07:53:59.57#ibcon#read 6, iclass 16, count 0 2006.252.07:53:59.57#ibcon#end of sib2, iclass 16, count 0 2006.252.07:53:59.57#ibcon#*after write, iclass 16, count 0 2006.252.07:53:59.57#ibcon#*before return 0, iclass 16, count 0 2006.252.07:53:59.57#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.252.07:53:59.57#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.252.07:53:59.57#ibcon#about to clear, iclass 16 cls_cnt 0 2006.252.07:53:59.57#ibcon#cleared, iclass 16 cls_cnt 0 2006.252.07:53:59.57$vc4f8/valo=6,772.99 2006.252.07:53:59.57#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.252.07:53:59.57#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.252.07:53:59.57#ibcon#ireg 17 cls_cnt 0 2006.252.07:53:59.57#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.252.07:53:59.57#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.252.07:53:59.57#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.252.07:53:59.57#ibcon#enter wrdev, iclass 18, count 0 2006.252.07:53:59.57#ibcon#first serial, iclass 18, count 0 2006.252.07:53:59.57#ibcon#enter sib2, iclass 18, count 0 2006.252.07:53:59.57#ibcon#flushed, iclass 18, count 0 2006.252.07:53:59.57#ibcon#about to write, iclass 18, count 0 2006.252.07:53:59.57#ibcon#wrote, iclass 18, count 0 2006.252.07:53:59.57#ibcon#about to read 3, iclass 18, count 0 2006.252.07:53:59.59#ibcon#read 3, iclass 18, count 0 2006.252.07:53:59.59#ibcon#about to read 4, iclass 18, count 0 2006.252.07:53:59.59#ibcon#read 4, iclass 18, count 0 2006.252.07:53:59.59#ibcon#about to read 5, iclass 18, count 0 2006.252.07:53:59.59#ibcon#read 5, iclass 18, count 0 2006.252.07:53:59.59#ibcon#about to read 6, iclass 18, count 0 2006.252.07:53:59.59#ibcon#read 6, iclass 18, count 0 2006.252.07:53:59.59#ibcon#end of sib2, iclass 18, count 0 2006.252.07:53:59.59#ibcon#*mode == 0, iclass 18, count 0 2006.252.07:53:59.59#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.252.07:53:59.59#ibcon#[26=FRQ=06,772.99\r\n] 2006.252.07:53:59.59#ibcon#*before write, iclass 18, count 0 2006.252.07:53:59.59#ibcon#enter sib2, iclass 18, count 0 2006.252.07:53:59.59#ibcon#flushed, iclass 18, count 0 2006.252.07:53:59.59#ibcon#about to write, iclass 18, count 0 2006.252.07:53:59.59#ibcon#wrote, iclass 18, count 0 2006.252.07:53:59.59#ibcon#about to read 3, iclass 18, count 0 2006.252.07:53:59.63#ibcon#read 3, iclass 18, count 0 2006.252.07:53:59.63#ibcon#about to read 4, iclass 18, count 0 2006.252.07:53:59.63#ibcon#read 4, iclass 18, count 0 2006.252.07:53:59.63#ibcon#about to read 5, iclass 18, count 0 2006.252.07:53:59.63#ibcon#read 5, iclass 18, count 0 2006.252.07:53:59.63#ibcon#about to read 6, iclass 18, count 0 2006.252.07:53:59.63#ibcon#read 6, iclass 18, count 0 2006.252.07:53:59.63#ibcon#end of sib2, iclass 18, count 0 2006.252.07:53:59.63#ibcon#*after write, iclass 18, count 0 2006.252.07:53:59.63#ibcon#*before return 0, iclass 18, count 0 2006.252.07:53:59.63#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.252.07:53:59.63#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.252.07:53:59.63#ibcon#about to clear, iclass 18 cls_cnt 0 2006.252.07:53:59.63#ibcon#cleared, iclass 18 cls_cnt 0 2006.252.07:53:59.63$vc4f8/va=6,7 2006.252.07:53:59.63#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.252.07:53:59.63#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.252.07:53:59.63#ibcon#ireg 11 cls_cnt 2 2006.252.07:53:59.63#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.252.07:53:59.69#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.252.07:53:59.69#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.252.07:53:59.69#ibcon#enter wrdev, iclass 20, count 2 2006.252.07:53:59.69#ibcon#first serial, iclass 20, count 2 2006.252.07:53:59.69#ibcon#enter sib2, iclass 20, count 2 2006.252.07:53:59.69#ibcon#flushed, iclass 20, count 2 2006.252.07:53:59.69#ibcon#about to write, iclass 20, count 2 2006.252.07:53:59.69#ibcon#wrote, iclass 20, count 2 2006.252.07:53:59.69#ibcon#about to read 3, iclass 20, count 2 2006.252.07:53:59.71#ibcon#read 3, iclass 20, count 2 2006.252.07:53:59.71#ibcon#about to read 4, iclass 20, count 2 2006.252.07:53:59.71#ibcon#read 4, iclass 20, count 2 2006.252.07:53:59.71#ibcon#about to read 5, iclass 20, count 2 2006.252.07:53:59.71#ibcon#read 5, iclass 20, count 2 2006.252.07:53:59.71#ibcon#about to read 6, iclass 20, count 2 2006.252.07:53:59.71#ibcon#read 6, iclass 20, count 2 2006.252.07:53:59.71#ibcon#end of sib2, iclass 20, count 2 2006.252.07:53:59.71#ibcon#*mode == 0, iclass 20, count 2 2006.252.07:53:59.71#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.252.07:53:59.71#ibcon#[25=AT06-07\r\n] 2006.252.07:53:59.71#ibcon#*before write, iclass 20, count 2 2006.252.07:53:59.71#ibcon#enter sib2, iclass 20, count 2 2006.252.07:53:59.71#ibcon#flushed, iclass 20, count 2 2006.252.07:53:59.71#ibcon#about to write, iclass 20, count 2 2006.252.07:53:59.71#ibcon#wrote, iclass 20, count 2 2006.252.07:53:59.71#ibcon#about to read 3, iclass 20, count 2 2006.252.07:53:59.74#ibcon#read 3, iclass 20, count 2 2006.252.07:53:59.74#ibcon#about to read 4, iclass 20, count 2 2006.252.07:53:59.74#ibcon#read 4, iclass 20, count 2 2006.252.07:53:59.74#ibcon#about to read 5, iclass 20, count 2 2006.252.07:53:59.74#ibcon#read 5, iclass 20, count 2 2006.252.07:53:59.74#ibcon#about to read 6, iclass 20, count 2 2006.252.07:53:59.74#ibcon#read 6, iclass 20, count 2 2006.252.07:53:59.74#ibcon#end of sib2, iclass 20, count 2 2006.252.07:53:59.74#ibcon#*after write, iclass 20, count 2 2006.252.07:53:59.74#ibcon#*before return 0, iclass 20, count 2 2006.252.07:53:59.74#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.252.07:53:59.74#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.252.07:53:59.74#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.252.07:53:59.74#ibcon#ireg 7 cls_cnt 0 2006.252.07:53:59.74#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.252.07:53:59.86#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.252.07:53:59.86#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.252.07:53:59.86#ibcon#enter wrdev, iclass 20, count 0 2006.252.07:53:59.86#ibcon#first serial, iclass 20, count 0 2006.252.07:53:59.86#ibcon#enter sib2, iclass 20, count 0 2006.252.07:53:59.86#ibcon#flushed, iclass 20, count 0 2006.252.07:53:59.86#ibcon#about to write, iclass 20, count 0 2006.252.07:53:59.86#ibcon#wrote, iclass 20, count 0 2006.252.07:53:59.86#ibcon#about to read 3, iclass 20, count 0 2006.252.07:53:59.88#ibcon#read 3, iclass 20, count 0 2006.252.07:53:59.88#ibcon#about to read 4, iclass 20, count 0 2006.252.07:53:59.88#ibcon#read 4, iclass 20, count 0 2006.252.07:53:59.88#ibcon#about to read 5, iclass 20, count 0 2006.252.07:53:59.88#ibcon#read 5, iclass 20, count 0 2006.252.07:53:59.88#ibcon#about to read 6, iclass 20, count 0 2006.252.07:53:59.88#ibcon#read 6, iclass 20, count 0 2006.252.07:53:59.88#ibcon#end of sib2, iclass 20, count 0 2006.252.07:53:59.88#ibcon#*mode == 0, iclass 20, count 0 2006.252.07:53:59.88#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.252.07:53:59.88#ibcon#[25=USB\r\n] 2006.252.07:53:59.88#ibcon#*before write, iclass 20, count 0 2006.252.07:53:59.88#ibcon#enter sib2, iclass 20, count 0 2006.252.07:53:59.88#ibcon#flushed, iclass 20, count 0 2006.252.07:53:59.88#ibcon#about to write, iclass 20, count 0 2006.252.07:53:59.88#ibcon#wrote, iclass 20, count 0 2006.252.07:53:59.88#ibcon#about to read 3, iclass 20, count 0 2006.252.07:53:59.91#ibcon#read 3, iclass 20, count 0 2006.252.07:53:59.91#ibcon#about to read 4, iclass 20, count 0 2006.252.07:53:59.91#ibcon#read 4, iclass 20, count 0 2006.252.07:53:59.91#ibcon#about to read 5, iclass 20, count 0 2006.252.07:53:59.91#ibcon#read 5, iclass 20, count 0 2006.252.07:53:59.91#ibcon#about to read 6, iclass 20, count 0 2006.252.07:53:59.91#ibcon#read 6, iclass 20, count 0 2006.252.07:53:59.91#ibcon#end of sib2, iclass 20, count 0 2006.252.07:53:59.91#ibcon#*after write, iclass 20, count 0 2006.252.07:53:59.91#ibcon#*before return 0, iclass 20, count 0 2006.252.07:53:59.91#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.252.07:53:59.91#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.252.07:53:59.91#ibcon#about to clear, iclass 20 cls_cnt 0 2006.252.07:53:59.91#ibcon#cleared, iclass 20 cls_cnt 0 2006.252.07:53:59.91$vc4f8/valo=7,832.99 2006.252.07:53:59.91#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.252.07:53:59.91#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.252.07:53:59.91#ibcon#ireg 17 cls_cnt 0 2006.252.07:53:59.91#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.252.07:53:59.91#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.252.07:53:59.91#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.252.07:53:59.91#ibcon#enter wrdev, iclass 22, count 0 2006.252.07:53:59.91#ibcon#first serial, iclass 22, count 0 2006.252.07:53:59.91#ibcon#enter sib2, iclass 22, count 0 2006.252.07:53:59.91#ibcon#flushed, iclass 22, count 0 2006.252.07:53:59.91#ibcon#about to write, iclass 22, count 0 2006.252.07:53:59.91#ibcon#wrote, iclass 22, count 0 2006.252.07:53:59.91#ibcon#about to read 3, iclass 22, count 0 2006.252.07:53:59.93#ibcon#read 3, iclass 22, count 0 2006.252.07:53:59.93#ibcon#about to read 4, iclass 22, count 0 2006.252.07:53:59.93#ibcon#read 4, iclass 22, count 0 2006.252.07:53:59.93#ibcon#about to read 5, iclass 22, count 0 2006.252.07:53:59.93#ibcon#read 5, iclass 22, count 0 2006.252.07:53:59.93#ibcon#about to read 6, iclass 22, count 0 2006.252.07:53:59.93#ibcon#read 6, iclass 22, count 0 2006.252.07:53:59.93#ibcon#end of sib2, iclass 22, count 0 2006.252.07:53:59.93#ibcon#*mode == 0, iclass 22, count 0 2006.252.07:53:59.93#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.252.07:53:59.93#ibcon#[26=FRQ=07,832.99\r\n] 2006.252.07:53:59.93#ibcon#*before write, iclass 22, count 0 2006.252.07:53:59.93#ibcon#enter sib2, iclass 22, count 0 2006.252.07:53:59.93#ibcon#flushed, iclass 22, count 0 2006.252.07:53:59.93#ibcon#about to write, iclass 22, count 0 2006.252.07:53:59.93#ibcon#wrote, iclass 22, count 0 2006.252.07:53:59.93#ibcon#about to read 3, iclass 22, count 0 2006.252.07:53:59.97#ibcon#read 3, iclass 22, count 0 2006.252.07:53:59.97#ibcon#about to read 4, iclass 22, count 0 2006.252.07:53:59.97#ibcon#read 4, iclass 22, count 0 2006.252.07:53:59.97#ibcon#about to read 5, iclass 22, count 0 2006.252.07:53:59.97#ibcon#read 5, iclass 22, count 0 2006.252.07:53:59.97#ibcon#about to read 6, iclass 22, count 0 2006.252.07:53:59.97#ibcon#read 6, iclass 22, count 0 2006.252.07:53:59.97#ibcon#end of sib2, iclass 22, count 0 2006.252.07:53:59.97#ibcon#*after write, iclass 22, count 0 2006.252.07:53:59.97#ibcon#*before return 0, iclass 22, count 0 2006.252.07:53:59.97#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.252.07:53:59.97#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.252.07:53:59.97#ibcon#about to clear, iclass 22 cls_cnt 0 2006.252.07:53:59.97#ibcon#cleared, iclass 22 cls_cnt 0 2006.252.07:53:59.97$vc4f8/va=7,7 2006.252.07:53:59.97#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.252.07:53:59.97#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.252.07:53:59.97#ibcon#ireg 11 cls_cnt 2 2006.252.07:53:59.97#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.252.07:54:00.03#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.252.07:54:00.03#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.252.07:54:00.03#ibcon#enter wrdev, iclass 24, count 2 2006.252.07:54:00.03#ibcon#first serial, iclass 24, count 2 2006.252.07:54:00.03#ibcon#enter sib2, iclass 24, count 2 2006.252.07:54:00.03#ibcon#flushed, iclass 24, count 2 2006.252.07:54:00.03#ibcon#about to write, iclass 24, count 2 2006.252.07:54:00.03#ibcon#wrote, iclass 24, count 2 2006.252.07:54:00.03#ibcon#about to read 3, iclass 24, count 2 2006.252.07:54:00.05#ibcon#read 3, iclass 24, count 2 2006.252.07:54:00.05#ibcon#about to read 4, iclass 24, count 2 2006.252.07:54:00.05#ibcon#read 4, iclass 24, count 2 2006.252.07:54:00.05#ibcon#about to read 5, iclass 24, count 2 2006.252.07:54:00.05#ibcon#read 5, iclass 24, count 2 2006.252.07:54:00.05#ibcon#about to read 6, iclass 24, count 2 2006.252.07:54:00.05#ibcon#read 6, iclass 24, count 2 2006.252.07:54:00.05#ibcon#end of sib2, iclass 24, count 2 2006.252.07:54:00.05#ibcon#*mode == 0, iclass 24, count 2 2006.252.07:54:00.05#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.252.07:54:00.05#ibcon#[25=AT07-07\r\n] 2006.252.07:54:00.05#ibcon#*before write, iclass 24, count 2 2006.252.07:54:00.05#ibcon#enter sib2, iclass 24, count 2 2006.252.07:54:00.05#ibcon#flushed, iclass 24, count 2 2006.252.07:54:00.05#ibcon#about to write, iclass 24, count 2 2006.252.07:54:00.05#ibcon#wrote, iclass 24, count 2 2006.252.07:54:00.05#ibcon#about to read 3, iclass 24, count 2 2006.252.07:54:00.08#ibcon#read 3, iclass 24, count 2 2006.252.07:54:00.08#ibcon#about to read 4, iclass 24, count 2 2006.252.07:54:00.08#ibcon#read 4, iclass 24, count 2 2006.252.07:54:00.08#ibcon#about to read 5, iclass 24, count 2 2006.252.07:54:00.08#ibcon#read 5, iclass 24, count 2 2006.252.07:54:00.08#ibcon#about to read 6, iclass 24, count 2 2006.252.07:54:00.08#ibcon#read 6, iclass 24, count 2 2006.252.07:54:00.08#ibcon#end of sib2, iclass 24, count 2 2006.252.07:54:00.08#ibcon#*after write, iclass 24, count 2 2006.252.07:54:00.08#ibcon#*before return 0, iclass 24, count 2 2006.252.07:54:00.08#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.252.07:54:00.08#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.252.07:54:00.08#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.252.07:54:00.08#ibcon#ireg 7 cls_cnt 0 2006.252.07:54:00.08#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.252.07:54:00.20#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.252.07:54:00.20#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.252.07:54:00.20#ibcon#enter wrdev, iclass 24, count 0 2006.252.07:54:00.20#ibcon#first serial, iclass 24, count 0 2006.252.07:54:00.20#ibcon#enter sib2, iclass 24, count 0 2006.252.07:54:00.20#ibcon#flushed, iclass 24, count 0 2006.252.07:54:00.20#ibcon#about to write, iclass 24, count 0 2006.252.07:54:00.20#ibcon#wrote, iclass 24, count 0 2006.252.07:54:00.20#ibcon#about to read 3, iclass 24, count 0 2006.252.07:54:00.22#ibcon#read 3, iclass 24, count 0 2006.252.07:54:00.22#ibcon#about to read 4, iclass 24, count 0 2006.252.07:54:00.22#ibcon#read 4, iclass 24, count 0 2006.252.07:54:00.22#ibcon#about to read 5, iclass 24, count 0 2006.252.07:54:00.22#ibcon#read 5, iclass 24, count 0 2006.252.07:54:00.22#ibcon#about to read 6, iclass 24, count 0 2006.252.07:54:00.22#ibcon#read 6, iclass 24, count 0 2006.252.07:54:00.22#ibcon#end of sib2, iclass 24, count 0 2006.252.07:54:00.22#ibcon#*mode == 0, iclass 24, count 0 2006.252.07:54:00.22#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.252.07:54:00.22#ibcon#[25=USB\r\n] 2006.252.07:54:00.22#ibcon#*before write, iclass 24, count 0 2006.252.07:54:00.22#ibcon#enter sib2, iclass 24, count 0 2006.252.07:54:00.22#ibcon#flushed, iclass 24, count 0 2006.252.07:54:00.22#ibcon#about to write, iclass 24, count 0 2006.252.07:54:00.22#ibcon#wrote, iclass 24, count 0 2006.252.07:54:00.22#ibcon#about to read 3, iclass 24, count 0 2006.252.07:54:00.25#ibcon#read 3, iclass 24, count 0 2006.252.07:54:00.25#ibcon#about to read 4, iclass 24, count 0 2006.252.07:54:00.25#ibcon#read 4, iclass 24, count 0 2006.252.07:54:00.25#ibcon#about to read 5, iclass 24, count 0 2006.252.07:54:00.25#ibcon#read 5, iclass 24, count 0 2006.252.07:54:00.25#ibcon#about to read 6, iclass 24, count 0 2006.252.07:54:00.25#ibcon#read 6, iclass 24, count 0 2006.252.07:54:00.25#ibcon#end of sib2, iclass 24, count 0 2006.252.07:54:00.25#ibcon#*after write, iclass 24, count 0 2006.252.07:54:00.25#ibcon#*before return 0, iclass 24, count 0 2006.252.07:54:00.25#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.252.07:54:00.25#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.252.07:54:00.25#ibcon#about to clear, iclass 24 cls_cnt 0 2006.252.07:54:00.25#ibcon#cleared, iclass 24 cls_cnt 0 2006.252.07:54:00.25$vc4f8/valo=8,852.99 2006.252.07:54:00.25#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.252.07:54:00.25#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.252.07:54:00.25#ibcon#ireg 17 cls_cnt 0 2006.252.07:54:00.25#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.252.07:54:00.25#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.252.07:54:00.25#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.252.07:54:00.25#ibcon#enter wrdev, iclass 26, count 0 2006.252.07:54:00.25#ibcon#first serial, iclass 26, count 0 2006.252.07:54:00.25#ibcon#enter sib2, iclass 26, count 0 2006.252.07:54:00.25#ibcon#flushed, iclass 26, count 0 2006.252.07:54:00.25#ibcon#about to write, iclass 26, count 0 2006.252.07:54:00.25#ibcon#wrote, iclass 26, count 0 2006.252.07:54:00.25#ibcon#about to read 3, iclass 26, count 0 2006.252.07:54:00.27#ibcon#read 3, iclass 26, count 0 2006.252.07:54:00.27#ibcon#about to read 4, iclass 26, count 0 2006.252.07:54:00.27#ibcon#read 4, iclass 26, count 0 2006.252.07:54:00.27#ibcon#about to read 5, iclass 26, count 0 2006.252.07:54:00.27#ibcon#read 5, iclass 26, count 0 2006.252.07:54:00.27#ibcon#about to read 6, iclass 26, count 0 2006.252.07:54:00.27#ibcon#read 6, iclass 26, count 0 2006.252.07:54:00.27#ibcon#end of sib2, iclass 26, count 0 2006.252.07:54:00.27#ibcon#*mode == 0, iclass 26, count 0 2006.252.07:54:00.27#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.252.07:54:00.27#ibcon#[26=FRQ=08,852.99\r\n] 2006.252.07:54:00.27#ibcon#*before write, iclass 26, count 0 2006.252.07:54:00.27#ibcon#enter sib2, iclass 26, count 0 2006.252.07:54:00.27#ibcon#flushed, iclass 26, count 0 2006.252.07:54:00.27#ibcon#about to write, iclass 26, count 0 2006.252.07:54:00.27#ibcon#wrote, iclass 26, count 0 2006.252.07:54:00.27#ibcon#about to read 3, iclass 26, count 0 2006.252.07:54:00.31#ibcon#read 3, iclass 26, count 0 2006.252.07:54:00.31#ibcon#about to read 4, iclass 26, count 0 2006.252.07:54:00.31#ibcon#read 4, iclass 26, count 0 2006.252.07:54:00.31#ibcon#about to read 5, iclass 26, count 0 2006.252.07:54:00.31#ibcon#read 5, iclass 26, count 0 2006.252.07:54:00.31#ibcon#about to read 6, iclass 26, count 0 2006.252.07:54:00.31#ibcon#read 6, iclass 26, count 0 2006.252.07:54:00.31#ibcon#end of sib2, iclass 26, count 0 2006.252.07:54:00.31#ibcon#*after write, iclass 26, count 0 2006.252.07:54:00.31#ibcon#*before return 0, iclass 26, count 0 2006.252.07:54:00.31#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.252.07:54:00.31#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.252.07:54:00.31#ibcon#about to clear, iclass 26 cls_cnt 0 2006.252.07:54:00.31#ibcon#cleared, iclass 26 cls_cnt 0 2006.252.07:54:00.31$vc4f8/va=8,7 2006.252.07:54:00.31#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.252.07:54:00.31#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.252.07:54:00.31#ibcon#ireg 11 cls_cnt 2 2006.252.07:54:00.31#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.252.07:54:00.37#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.252.07:54:00.37#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.252.07:54:00.37#ibcon#enter wrdev, iclass 28, count 2 2006.252.07:54:00.37#ibcon#first serial, iclass 28, count 2 2006.252.07:54:00.37#ibcon#enter sib2, iclass 28, count 2 2006.252.07:54:00.37#ibcon#flushed, iclass 28, count 2 2006.252.07:54:00.37#ibcon#about to write, iclass 28, count 2 2006.252.07:54:00.37#ibcon#wrote, iclass 28, count 2 2006.252.07:54:00.37#ibcon#about to read 3, iclass 28, count 2 2006.252.07:54:00.39#ibcon#read 3, iclass 28, count 2 2006.252.07:54:00.39#ibcon#about to read 4, iclass 28, count 2 2006.252.07:54:00.39#ibcon#read 4, iclass 28, count 2 2006.252.07:54:00.39#ibcon#about to read 5, iclass 28, count 2 2006.252.07:54:00.39#ibcon#read 5, iclass 28, count 2 2006.252.07:54:00.39#ibcon#about to read 6, iclass 28, count 2 2006.252.07:54:00.39#ibcon#read 6, iclass 28, count 2 2006.252.07:54:00.39#ibcon#end of sib2, iclass 28, count 2 2006.252.07:54:00.39#ibcon#*mode == 0, iclass 28, count 2 2006.252.07:54:00.39#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.252.07:54:00.39#ibcon#[25=AT08-07\r\n] 2006.252.07:54:00.39#ibcon#*before write, iclass 28, count 2 2006.252.07:54:00.39#ibcon#enter sib2, iclass 28, count 2 2006.252.07:54:00.39#ibcon#flushed, iclass 28, count 2 2006.252.07:54:00.39#ibcon#about to write, iclass 28, count 2 2006.252.07:54:00.39#ibcon#wrote, iclass 28, count 2 2006.252.07:54:00.39#ibcon#about to read 3, iclass 28, count 2 2006.252.07:54:00.42#ibcon#read 3, iclass 28, count 2 2006.252.07:54:00.42#ibcon#about to read 4, iclass 28, count 2 2006.252.07:54:00.42#ibcon#read 4, iclass 28, count 2 2006.252.07:54:00.42#ibcon#about to read 5, iclass 28, count 2 2006.252.07:54:00.42#ibcon#read 5, iclass 28, count 2 2006.252.07:54:00.42#ibcon#about to read 6, iclass 28, count 2 2006.252.07:54:00.42#ibcon#read 6, iclass 28, count 2 2006.252.07:54:00.42#ibcon#end of sib2, iclass 28, count 2 2006.252.07:54:00.42#ibcon#*after write, iclass 28, count 2 2006.252.07:54:00.42#ibcon#*before return 0, iclass 28, count 2 2006.252.07:54:00.42#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.252.07:54:00.42#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.252.07:54:00.42#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.252.07:54:00.42#ibcon#ireg 7 cls_cnt 0 2006.252.07:54:00.42#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.252.07:54:00.54#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.252.07:54:00.54#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.252.07:54:00.54#ibcon#enter wrdev, iclass 28, count 0 2006.252.07:54:00.54#ibcon#first serial, iclass 28, count 0 2006.252.07:54:00.54#ibcon#enter sib2, iclass 28, count 0 2006.252.07:54:00.54#ibcon#flushed, iclass 28, count 0 2006.252.07:54:00.54#ibcon#about to write, iclass 28, count 0 2006.252.07:54:00.54#ibcon#wrote, iclass 28, count 0 2006.252.07:54:00.54#ibcon#about to read 3, iclass 28, count 0 2006.252.07:54:00.56#ibcon#read 3, iclass 28, count 0 2006.252.07:54:00.56#ibcon#about to read 4, iclass 28, count 0 2006.252.07:54:00.56#ibcon#read 4, iclass 28, count 0 2006.252.07:54:00.56#ibcon#about to read 5, iclass 28, count 0 2006.252.07:54:00.56#ibcon#read 5, iclass 28, count 0 2006.252.07:54:00.56#ibcon#about to read 6, iclass 28, count 0 2006.252.07:54:00.56#ibcon#read 6, iclass 28, count 0 2006.252.07:54:00.56#ibcon#end of sib2, iclass 28, count 0 2006.252.07:54:00.56#ibcon#*mode == 0, iclass 28, count 0 2006.252.07:54:00.56#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.252.07:54:00.56#ibcon#[25=USB\r\n] 2006.252.07:54:00.56#ibcon#*before write, iclass 28, count 0 2006.252.07:54:00.56#ibcon#enter sib2, iclass 28, count 0 2006.252.07:54:00.56#ibcon#flushed, iclass 28, count 0 2006.252.07:54:00.56#ibcon#about to write, iclass 28, count 0 2006.252.07:54:00.56#ibcon#wrote, iclass 28, count 0 2006.252.07:54:00.56#ibcon#about to read 3, iclass 28, count 0 2006.252.07:54:00.59#ibcon#read 3, iclass 28, count 0 2006.252.07:54:00.59#ibcon#about to read 4, iclass 28, count 0 2006.252.07:54:00.59#ibcon#read 4, iclass 28, count 0 2006.252.07:54:00.59#ibcon#about to read 5, iclass 28, count 0 2006.252.07:54:00.59#ibcon#read 5, iclass 28, count 0 2006.252.07:54:00.59#ibcon#about to read 6, iclass 28, count 0 2006.252.07:54:00.59#ibcon#read 6, iclass 28, count 0 2006.252.07:54:00.59#ibcon#end of sib2, iclass 28, count 0 2006.252.07:54:00.59#ibcon#*after write, iclass 28, count 0 2006.252.07:54:00.59#ibcon#*before return 0, iclass 28, count 0 2006.252.07:54:00.59#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.252.07:54:00.59#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.252.07:54:00.59#ibcon#about to clear, iclass 28 cls_cnt 0 2006.252.07:54:00.59#ibcon#cleared, iclass 28 cls_cnt 0 2006.252.07:54:00.59$vc4f8/vblo=1,632.99 2006.252.07:54:00.59#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.252.07:54:00.59#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.252.07:54:00.59#ibcon#ireg 17 cls_cnt 0 2006.252.07:54:00.59#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.252.07:54:00.59#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.252.07:54:00.59#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.252.07:54:00.59#ibcon#enter wrdev, iclass 30, count 0 2006.252.07:54:00.59#ibcon#first serial, iclass 30, count 0 2006.252.07:54:00.59#ibcon#enter sib2, iclass 30, count 0 2006.252.07:54:00.59#ibcon#flushed, iclass 30, count 0 2006.252.07:54:00.59#ibcon#about to write, iclass 30, count 0 2006.252.07:54:00.59#ibcon#wrote, iclass 30, count 0 2006.252.07:54:00.59#ibcon#about to read 3, iclass 30, count 0 2006.252.07:54:00.61#ibcon#read 3, iclass 30, count 0 2006.252.07:54:00.61#ibcon#about to read 4, iclass 30, count 0 2006.252.07:54:00.61#ibcon#read 4, iclass 30, count 0 2006.252.07:54:00.61#ibcon#about to read 5, iclass 30, count 0 2006.252.07:54:00.61#ibcon#read 5, iclass 30, count 0 2006.252.07:54:00.61#ibcon#about to read 6, iclass 30, count 0 2006.252.07:54:00.61#ibcon#read 6, iclass 30, count 0 2006.252.07:54:00.61#ibcon#end of sib2, iclass 30, count 0 2006.252.07:54:00.61#ibcon#*mode == 0, iclass 30, count 0 2006.252.07:54:00.61#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.252.07:54:00.61#ibcon#[28=FRQ=01,632.99\r\n] 2006.252.07:54:00.61#ibcon#*before write, iclass 30, count 0 2006.252.07:54:00.61#ibcon#enter sib2, iclass 30, count 0 2006.252.07:54:00.61#ibcon#flushed, iclass 30, count 0 2006.252.07:54:00.61#ibcon#about to write, iclass 30, count 0 2006.252.07:54:00.61#ibcon#wrote, iclass 30, count 0 2006.252.07:54:00.61#ibcon#about to read 3, iclass 30, count 0 2006.252.07:54:00.65#ibcon#read 3, iclass 30, count 0 2006.252.07:54:00.65#ibcon#about to read 4, iclass 30, count 0 2006.252.07:54:00.65#ibcon#read 4, iclass 30, count 0 2006.252.07:54:00.65#ibcon#about to read 5, iclass 30, count 0 2006.252.07:54:00.65#ibcon#read 5, iclass 30, count 0 2006.252.07:54:00.65#ibcon#about to read 6, iclass 30, count 0 2006.252.07:54:00.65#ibcon#read 6, iclass 30, count 0 2006.252.07:54:00.65#ibcon#end of sib2, iclass 30, count 0 2006.252.07:54:00.65#ibcon#*after write, iclass 30, count 0 2006.252.07:54:00.65#ibcon#*before return 0, iclass 30, count 0 2006.252.07:54:00.65#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.252.07:54:00.65#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.252.07:54:00.65#ibcon#about to clear, iclass 30 cls_cnt 0 2006.252.07:54:00.65#ibcon#cleared, iclass 30 cls_cnt 0 2006.252.07:54:00.65$vc4f8/vb=1,4 2006.252.07:54:00.65#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.252.07:54:00.65#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.252.07:54:00.65#ibcon#ireg 11 cls_cnt 2 2006.252.07:54:00.65#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.252.07:54:00.65#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.252.07:54:00.65#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.252.07:54:00.65#ibcon#enter wrdev, iclass 32, count 2 2006.252.07:54:00.65#ibcon#first serial, iclass 32, count 2 2006.252.07:54:00.65#ibcon#enter sib2, iclass 32, count 2 2006.252.07:54:00.65#ibcon#flushed, iclass 32, count 2 2006.252.07:54:00.65#ibcon#about to write, iclass 32, count 2 2006.252.07:54:00.65#ibcon#wrote, iclass 32, count 2 2006.252.07:54:00.65#ibcon#about to read 3, iclass 32, count 2 2006.252.07:54:00.67#ibcon#read 3, iclass 32, count 2 2006.252.07:54:00.67#ibcon#about to read 4, iclass 32, count 2 2006.252.07:54:00.67#ibcon#read 4, iclass 32, count 2 2006.252.07:54:00.67#ibcon#about to read 5, iclass 32, count 2 2006.252.07:54:00.67#ibcon#read 5, iclass 32, count 2 2006.252.07:54:00.67#ibcon#about to read 6, iclass 32, count 2 2006.252.07:54:00.67#ibcon#read 6, iclass 32, count 2 2006.252.07:54:00.67#ibcon#end of sib2, iclass 32, count 2 2006.252.07:54:00.67#ibcon#*mode == 0, iclass 32, count 2 2006.252.07:54:00.67#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.252.07:54:00.67#ibcon#[27=AT01-04\r\n] 2006.252.07:54:00.67#ibcon#*before write, iclass 32, count 2 2006.252.07:54:00.67#ibcon#enter sib2, iclass 32, count 2 2006.252.07:54:00.67#ibcon#flushed, iclass 32, count 2 2006.252.07:54:00.67#ibcon#about to write, iclass 32, count 2 2006.252.07:54:00.67#ibcon#wrote, iclass 32, count 2 2006.252.07:54:00.67#ibcon#about to read 3, iclass 32, count 2 2006.252.07:54:00.70#ibcon#read 3, iclass 32, count 2 2006.252.07:54:00.70#ibcon#about to read 4, iclass 32, count 2 2006.252.07:54:00.70#ibcon#read 4, iclass 32, count 2 2006.252.07:54:00.70#ibcon#about to read 5, iclass 32, count 2 2006.252.07:54:00.70#ibcon#read 5, iclass 32, count 2 2006.252.07:54:00.70#ibcon#about to read 6, iclass 32, count 2 2006.252.07:54:00.70#ibcon#read 6, iclass 32, count 2 2006.252.07:54:00.70#ibcon#end of sib2, iclass 32, count 2 2006.252.07:54:00.70#ibcon#*after write, iclass 32, count 2 2006.252.07:54:00.70#ibcon#*before return 0, iclass 32, count 2 2006.252.07:54:00.70#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.252.07:54:00.70#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.252.07:54:00.70#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.252.07:54:00.70#ibcon#ireg 7 cls_cnt 0 2006.252.07:54:00.70#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.252.07:54:00.82#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.252.07:54:00.82#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.252.07:54:00.82#ibcon#enter wrdev, iclass 32, count 0 2006.252.07:54:00.82#ibcon#first serial, iclass 32, count 0 2006.252.07:54:00.82#ibcon#enter sib2, iclass 32, count 0 2006.252.07:54:00.82#ibcon#flushed, iclass 32, count 0 2006.252.07:54:00.82#ibcon#about to write, iclass 32, count 0 2006.252.07:54:00.82#ibcon#wrote, iclass 32, count 0 2006.252.07:54:00.82#ibcon#about to read 3, iclass 32, count 0 2006.252.07:54:00.84#ibcon#read 3, iclass 32, count 0 2006.252.07:54:00.84#ibcon#about to read 4, iclass 32, count 0 2006.252.07:54:00.84#ibcon#read 4, iclass 32, count 0 2006.252.07:54:00.84#ibcon#about to read 5, iclass 32, count 0 2006.252.07:54:00.84#ibcon#read 5, iclass 32, count 0 2006.252.07:54:00.84#ibcon#about to read 6, iclass 32, count 0 2006.252.07:54:00.84#ibcon#read 6, iclass 32, count 0 2006.252.07:54:00.84#ibcon#end of sib2, iclass 32, count 0 2006.252.07:54:00.84#ibcon#*mode == 0, iclass 32, count 0 2006.252.07:54:00.84#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.252.07:54:00.84#ibcon#[27=USB\r\n] 2006.252.07:54:00.84#ibcon#*before write, iclass 32, count 0 2006.252.07:54:00.84#ibcon#enter sib2, iclass 32, count 0 2006.252.07:54:00.84#ibcon#flushed, iclass 32, count 0 2006.252.07:54:00.84#ibcon#about to write, iclass 32, count 0 2006.252.07:54:00.84#ibcon#wrote, iclass 32, count 0 2006.252.07:54:00.84#ibcon#about to read 3, iclass 32, count 0 2006.252.07:54:00.87#ibcon#read 3, iclass 32, count 0 2006.252.07:54:00.87#ibcon#about to read 4, iclass 32, count 0 2006.252.07:54:00.87#ibcon#read 4, iclass 32, count 0 2006.252.07:54:00.87#ibcon#about to read 5, iclass 32, count 0 2006.252.07:54:00.87#ibcon#read 5, iclass 32, count 0 2006.252.07:54:00.87#ibcon#about to read 6, iclass 32, count 0 2006.252.07:54:00.87#ibcon#read 6, iclass 32, count 0 2006.252.07:54:00.87#ibcon#end of sib2, iclass 32, count 0 2006.252.07:54:00.87#ibcon#*after write, iclass 32, count 0 2006.252.07:54:00.87#ibcon#*before return 0, iclass 32, count 0 2006.252.07:54:00.87#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.252.07:54:00.87#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.252.07:54:00.87#ibcon#about to clear, iclass 32 cls_cnt 0 2006.252.07:54:00.87#ibcon#cleared, iclass 32 cls_cnt 0 2006.252.07:54:00.87$vc4f8/vblo=2,640.99 2006.252.07:54:00.87#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.252.07:54:00.87#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.252.07:54:00.87#ibcon#ireg 17 cls_cnt 0 2006.252.07:54:00.87#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.252.07:54:00.87#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.252.07:54:00.87#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.252.07:54:00.87#ibcon#enter wrdev, iclass 34, count 0 2006.252.07:54:00.87#ibcon#first serial, iclass 34, count 0 2006.252.07:54:00.87#ibcon#enter sib2, iclass 34, count 0 2006.252.07:54:00.87#ibcon#flushed, iclass 34, count 0 2006.252.07:54:00.87#ibcon#about to write, iclass 34, count 0 2006.252.07:54:00.87#ibcon#wrote, iclass 34, count 0 2006.252.07:54:00.87#ibcon#about to read 3, iclass 34, count 0 2006.252.07:54:00.89#ibcon#read 3, iclass 34, count 0 2006.252.07:54:00.89#ibcon#about to read 4, iclass 34, count 0 2006.252.07:54:00.89#ibcon#read 4, iclass 34, count 0 2006.252.07:54:00.89#ibcon#about to read 5, iclass 34, count 0 2006.252.07:54:00.89#ibcon#read 5, iclass 34, count 0 2006.252.07:54:00.89#ibcon#about to read 6, iclass 34, count 0 2006.252.07:54:00.89#ibcon#read 6, iclass 34, count 0 2006.252.07:54:00.89#ibcon#end of sib2, iclass 34, count 0 2006.252.07:54:00.89#ibcon#*mode == 0, iclass 34, count 0 2006.252.07:54:00.89#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.252.07:54:00.89#ibcon#[28=FRQ=02,640.99\r\n] 2006.252.07:54:00.89#ibcon#*before write, iclass 34, count 0 2006.252.07:54:00.89#ibcon#enter sib2, iclass 34, count 0 2006.252.07:54:00.89#ibcon#flushed, iclass 34, count 0 2006.252.07:54:00.89#ibcon#about to write, iclass 34, count 0 2006.252.07:54:00.89#ibcon#wrote, iclass 34, count 0 2006.252.07:54:00.89#ibcon#about to read 3, iclass 34, count 0 2006.252.07:54:00.93#ibcon#read 3, iclass 34, count 0 2006.252.07:54:00.93#ibcon#about to read 4, iclass 34, count 0 2006.252.07:54:00.93#ibcon#read 4, iclass 34, count 0 2006.252.07:54:00.93#ibcon#about to read 5, iclass 34, count 0 2006.252.07:54:00.93#ibcon#read 5, iclass 34, count 0 2006.252.07:54:00.93#ibcon#about to read 6, iclass 34, count 0 2006.252.07:54:00.93#ibcon#read 6, iclass 34, count 0 2006.252.07:54:00.93#ibcon#end of sib2, iclass 34, count 0 2006.252.07:54:00.93#ibcon#*after write, iclass 34, count 0 2006.252.07:54:00.93#ibcon#*before return 0, iclass 34, count 0 2006.252.07:54:00.93#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.252.07:54:00.93#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.252.07:54:00.93#ibcon#about to clear, iclass 34 cls_cnt 0 2006.252.07:54:00.93#ibcon#cleared, iclass 34 cls_cnt 0 2006.252.07:54:00.93$vc4f8/vb=2,5 2006.252.07:54:00.93#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.252.07:54:00.93#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.252.07:54:00.93#ibcon#ireg 11 cls_cnt 2 2006.252.07:54:00.93#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.252.07:54:00.99#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.252.07:54:00.99#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.252.07:54:00.99#ibcon#enter wrdev, iclass 36, count 2 2006.252.07:54:00.99#ibcon#first serial, iclass 36, count 2 2006.252.07:54:00.99#ibcon#enter sib2, iclass 36, count 2 2006.252.07:54:00.99#ibcon#flushed, iclass 36, count 2 2006.252.07:54:00.99#ibcon#about to write, iclass 36, count 2 2006.252.07:54:00.99#ibcon#wrote, iclass 36, count 2 2006.252.07:54:00.99#ibcon#about to read 3, iclass 36, count 2 2006.252.07:54:01.01#ibcon#read 3, iclass 36, count 2 2006.252.07:54:01.01#ibcon#about to read 4, iclass 36, count 2 2006.252.07:54:01.01#ibcon#read 4, iclass 36, count 2 2006.252.07:54:01.01#ibcon#about to read 5, iclass 36, count 2 2006.252.07:54:01.01#ibcon#read 5, iclass 36, count 2 2006.252.07:54:01.01#ibcon#about to read 6, iclass 36, count 2 2006.252.07:54:01.01#ibcon#read 6, iclass 36, count 2 2006.252.07:54:01.01#ibcon#end of sib2, iclass 36, count 2 2006.252.07:54:01.01#ibcon#*mode == 0, iclass 36, count 2 2006.252.07:54:01.01#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.252.07:54:01.01#ibcon#[27=AT02-05\r\n] 2006.252.07:54:01.01#ibcon#*before write, iclass 36, count 2 2006.252.07:54:01.01#ibcon#enter sib2, iclass 36, count 2 2006.252.07:54:01.01#ibcon#flushed, iclass 36, count 2 2006.252.07:54:01.01#ibcon#about to write, iclass 36, count 2 2006.252.07:54:01.01#ibcon#wrote, iclass 36, count 2 2006.252.07:54:01.01#ibcon#about to read 3, iclass 36, count 2 2006.252.07:54:01.04#ibcon#read 3, iclass 36, count 2 2006.252.07:54:01.04#ibcon#about to read 4, iclass 36, count 2 2006.252.07:54:01.04#ibcon#read 4, iclass 36, count 2 2006.252.07:54:01.04#ibcon#about to read 5, iclass 36, count 2 2006.252.07:54:01.04#ibcon#read 5, iclass 36, count 2 2006.252.07:54:01.04#ibcon#about to read 6, iclass 36, count 2 2006.252.07:54:01.04#ibcon#read 6, iclass 36, count 2 2006.252.07:54:01.04#ibcon#end of sib2, iclass 36, count 2 2006.252.07:54:01.04#ibcon#*after write, iclass 36, count 2 2006.252.07:54:01.04#ibcon#*before return 0, iclass 36, count 2 2006.252.07:54:01.04#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.252.07:54:01.04#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.252.07:54:01.04#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.252.07:54:01.04#ibcon#ireg 7 cls_cnt 0 2006.252.07:54:01.04#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.252.07:54:01.16#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.252.07:54:01.16#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.252.07:54:01.16#ibcon#enter wrdev, iclass 36, count 0 2006.252.07:54:01.16#ibcon#first serial, iclass 36, count 0 2006.252.07:54:01.16#ibcon#enter sib2, iclass 36, count 0 2006.252.07:54:01.16#ibcon#flushed, iclass 36, count 0 2006.252.07:54:01.16#ibcon#about to write, iclass 36, count 0 2006.252.07:54:01.16#ibcon#wrote, iclass 36, count 0 2006.252.07:54:01.16#ibcon#about to read 3, iclass 36, count 0 2006.252.07:54:01.18#ibcon#read 3, iclass 36, count 0 2006.252.07:54:01.18#ibcon#about to read 4, iclass 36, count 0 2006.252.07:54:01.18#ibcon#read 4, iclass 36, count 0 2006.252.07:54:01.18#ibcon#about to read 5, iclass 36, count 0 2006.252.07:54:01.18#ibcon#read 5, iclass 36, count 0 2006.252.07:54:01.18#ibcon#about to read 6, iclass 36, count 0 2006.252.07:54:01.18#ibcon#read 6, iclass 36, count 0 2006.252.07:54:01.18#ibcon#end of sib2, iclass 36, count 0 2006.252.07:54:01.18#ibcon#*mode == 0, iclass 36, count 0 2006.252.07:54:01.18#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.252.07:54:01.18#ibcon#[27=USB\r\n] 2006.252.07:54:01.18#ibcon#*before write, iclass 36, count 0 2006.252.07:54:01.18#ibcon#enter sib2, iclass 36, count 0 2006.252.07:54:01.18#ibcon#flushed, iclass 36, count 0 2006.252.07:54:01.18#ibcon#about to write, iclass 36, count 0 2006.252.07:54:01.18#ibcon#wrote, iclass 36, count 0 2006.252.07:54:01.18#ibcon#about to read 3, iclass 36, count 0 2006.252.07:54:01.21#ibcon#read 3, iclass 36, count 0 2006.252.07:54:01.21#ibcon#about to read 4, iclass 36, count 0 2006.252.07:54:01.21#ibcon#read 4, iclass 36, count 0 2006.252.07:54:01.21#ibcon#about to read 5, iclass 36, count 0 2006.252.07:54:01.21#ibcon#read 5, iclass 36, count 0 2006.252.07:54:01.21#ibcon#about to read 6, iclass 36, count 0 2006.252.07:54:01.21#ibcon#read 6, iclass 36, count 0 2006.252.07:54:01.21#ibcon#end of sib2, iclass 36, count 0 2006.252.07:54:01.21#ibcon#*after write, iclass 36, count 0 2006.252.07:54:01.21#ibcon#*before return 0, iclass 36, count 0 2006.252.07:54:01.21#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.252.07:54:01.21#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.252.07:54:01.21#ibcon#about to clear, iclass 36 cls_cnt 0 2006.252.07:54:01.21#ibcon#cleared, iclass 36 cls_cnt 0 2006.252.07:54:01.21$vc4f8/vblo=3,656.99 2006.252.07:54:01.21#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.252.07:54:01.21#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.252.07:54:01.21#ibcon#ireg 17 cls_cnt 0 2006.252.07:54:01.21#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.252.07:54:01.21#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.252.07:54:01.21#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.252.07:54:01.21#ibcon#enter wrdev, iclass 38, count 0 2006.252.07:54:01.21#ibcon#first serial, iclass 38, count 0 2006.252.07:54:01.21#ibcon#enter sib2, iclass 38, count 0 2006.252.07:54:01.21#ibcon#flushed, iclass 38, count 0 2006.252.07:54:01.21#ibcon#about to write, iclass 38, count 0 2006.252.07:54:01.21#ibcon#wrote, iclass 38, count 0 2006.252.07:54:01.21#ibcon#about to read 3, iclass 38, count 0 2006.252.07:54:01.23#ibcon#read 3, iclass 38, count 0 2006.252.07:54:01.23#ibcon#about to read 4, iclass 38, count 0 2006.252.07:54:01.23#ibcon#read 4, iclass 38, count 0 2006.252.07:54:01.23#ibcon#about to read 5, iclass 38, count 0 2006.252.07:54:01.23#ibcon#read 5, iclass 38, count 0 2006.252.07:54:01.23#ibcon#about to read 6, iclass 38, count 0 2006.252.07:54:01.23#ibcon#read 6, iclass 38, count 0 2006.252.07:54:01.23#ibcon#end of sib2, iclass 38, count 0 2006.252.07:54:01.23#ibcon#*mode == 0, iclass 38, count 0 2006.252.07:54:01.23#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.252.07:54:01.23#ibcon#[28=FRQ=03,656.99\r\n] 2006.252.07:54:01.23#ibcon#*before write, iclass 38, count 0 2006.252.07:54:01.23#ibcon#enter sib2, iclass 38, count 0 2006.252.07:54:01.23#ibcon#flushed, iclass 38, count 0 2006.252.07:54:01.23#ibcon#about to write, iclass 38, count 0 2006.252.07:54:01.23#ibcon#wrote, iclass 38, count 0 2006.252.07:54:01.23#ibcon#about to read 3, iclass 38, count 0 2006.252.07:54:01.27#ibcon#read 3, iclass 38, count 0 2006.252.07:54:01.27#ibcon#about to read 4, iclass 38, count 0 2006.252.07:54:01.27#ibcon#read 4, iclass 38, count 0 2006.252.07:54:01.27#ibcon#about to read 5, iclass 38, count 0 2006.252.07:54:01.27#ibcon#read 5, iclass 38, count 0 2006.252.07:54:01.27#ibcon#about to read 6, iclass 38, count 0 2006.252.07:54:01.27#ibcon#read 6, iclass 38, count 0 2006.252.07:54:01.27#ibcon#end of sib2, iclass 38, count 0 2006.252.07:54:01.27#ibcon#*after write, iclass 38, count 0 2006.252.07:54:01.27#ibcon#*before return 0, iclass 38, count 0 2006.252.07:54:01.27#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.252.07:54:01.27#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.252.07:54:01.27#ibcon#about to clear, iclass 38 cls_cnt 0 2006.252.07:54:01.27#ibcon#cleared, iclass 38 cls_cnt 0 2006.252.07:54:01.27$vc4f8/vb=3,4 2006.252.07:54:01.27#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.252.07:54:01.27#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.252.07:54:01.27#ibcon#ireg 11 cls_cnt 2 2006.252.07:54:01.27#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.252.07:54:01.33#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.252.07:54:01.33#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.252.07:54:01.33#ibcon#enter wrdev, iclass 40, count 2 2006.252.07:54:01.33#ibcon#first serial, iclass 40, count 2 2006.252.07:54:01.33#ibcon#enter sib2, iclass 40, count 2 2006.252.07:54:01.33#ibcon#flushed, iclass 40, count 2 2006.252.07:54:01.33#ibcon#about to write, iclass 40, count 2 2006.252.07:54:01.33#ibcon#wrote, iclass 40, count 2 2006.252.07:54:01.33#ibcon#about to read 3, iclass 40, count 2 2006.252.07:54:01.35#ibcon#read 3, iclass 40, count 2 2006.252.07:54:01.35#ibcon#about to read 4, iclass 40, count 2 2006.252.07:54:01.35#ibcon#read 4, iclass 40, count 2 2006.252.07:54:01.35#ibcon#about to read 5, iclass 40, count 2 2006.252.07:54:01.35#ibcon#read 5, iclass 40, count 2 2006.252.07:54:01.35#ibcon#about to read 6, iclass 40, count 2 2006.252.07:54:01.35#ibcon#read 6, iclass 40, count 2 2006.252.07:54:01.35#ibcon#end of sib2, iclass 40, count 2 2006.252.07:54:01.35#ibcon#*mode == 0, iclass 40, count 2 2006.252.07:54:01.35#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.252.07:54:01.35#ibcon#[27=AT03-04\r\n] 2006.252.07:54:01.35#ibcon#*before write, iclass 40, count 2 2006.252.07:54:01.35#ibcon#enter sib2, iclass 40, count 2 2006.252.07:54:01.35#ibcon#flushed, iclass 40, count 2 2006.252.07:54:01.35#ibcon#about to write, iclass 40, count 2 2006.252.07:54:01.35#ibcon#wrote, iclass 40, count 2 2006.252.07:54:01.35#ibcon#about to read 3, iclass 40, count 2 2006.252.07:54:01.38#ibcon#read 3, iclass 40, count 2 2006.252.07:54:01.38#ibcon#about to read 4, iclass 40, count 2 2006.252.07:54:01.38#ibcon#read 4, iclass 40, count 2 2006.252.07:54:01.38#ibcon#about to read 5, iclass 40, count 2 2006.252.07:54:01.38#ibcon#read 5, iclass 40, count 2 2006.252.07:54:01.38#ibcon#about to read 6, iclass 40, count 2 2006.252.07:54:01.38#ibcon#read 6, iclass 40, count 2 2006.252.07:54:01.38#ibcon#end of sib2, iclass 40, count 2 2006.252.07:54:01.38#ibcon#*after write, iclass 40, count 2 2006.252.07:54:01.38#ibcon#*before return 0, iclass 40, count 2 2006.252.07:54:01.38#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.252.07:54:01.38#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.252.07:54:01.38#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.252.07:54:01.38#ibcon#ireg 7 cls_cnt 0 2006.252.07:54:01.38#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.252.07:54:01.50#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.252.07:54:01.50#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.252.07:54:01.50#ibcon#enter wrdev, iclass 40, count 0 2006.252.07:54:01.50#ibcon#first serial, iclass 40, count 0 2006.252.07:54:01.50#ibcon#enter sib2, iclass 40, count 0 2006.252.07:54:01.50#ibcon#flushed, iclass 40, count 0 2006.252.07:54:01.50#ibcon#about to write, iclass 40, count 0 2006.252.07:54:01.50#ibcon#wrote, iclass 40, count 0 2006.252.07:54:01.50#ibcon#about to read 3, iclass 40, count 0 2006.252.07:54:01.52#ibcon#read 3, iclass 40, count 0 2006.252.07:54:01.52#ibcon#about to read 4, iclass 40, count 0 2006.252.07:54:01.52#ibcon#read 4, iclass 40, count 0 2006.252.07:54:01.52#ibcon#about to read 5, iclass 40, count 0 2006.252.07:54:01.52#ibcon#read 5, iclass 40, count 0 2006.252.07:54:01.52#ibcon#about to read 6, iclass 40, count 0 2006.252.07:54:01.52#ibcon#read 6, iclass 40, count 0 2006.252.07:54:01.52#ibcon#end of sib2, iclass 40, count 0 2006.252.07:54:01.52#ibcon#*mode == 0, iclass 40, count 0 2006.252.07:54:01.52#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.252.07:54:01.52#ibcon#[27=USB\r\n] 2006.252.07:54:01.52#ibcon#*before write, iclass 40, count 0 2006.252.07:54:01.52#ibcon#enter sib2, iclass 40, count 0 2006.252.07:54:01.52#ibcon#flushed, iclass 40, count 0 2006.252.07:54:01.52#ibcon#about to write, iclass 40, count 0 2006.252.07:54:01.52#ibcon#wrote, iclass 40, count 0 2006.252.07:54:01.52#ibcon#about to read 3, iclass 40, count 0 2006.252.07:54:01.55#ibcon#read 3, iclass 40, count 0 2006.252.07:54:01.55#ibcon#about to read 4, iclass 40, count 0 2006.252.07:54:01.55#ibcon#read 4, iclass 40, count 0 2006.252.07:54:01.55#ibcon#about to read 5, iclass 40, count 0 2006.252.07:54:01.55#ibcon#read 5, iclass 40, count 0 2006.252.07:54:01.55#ibcon#about to read 6, iclass 40, count 0 2006.252.07:54:01.55#ibcon#read 6, iclass 40, count 0 2006.252.07:54:01.55#ibcon#end of sib2, iclass 40, count 0 2006.252.07:54:01.55#ibcon#*after write, iclass 40, count 0 2006.252.07:54:01.55#ibcon#*before return 0, iclass 40, count 0 2006.252.07:54:01.55#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.252.07:54:01.55#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.252.07:54:01.55#ibcon#about to clear, iclass 40 cls_cnt 0 2006.252.07:54:01.55#ibcon#cleared, iclass 40 cls_cnt 0 2006.252.07:54:01.55$vc4f8/vblo=4,712.99 2006.252.07:54:01.55#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.252.07:54:01.55#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.252.07:54:01.55#ibcon#ireg 17 cls_cnt 0 2006.252.07:54:01.55#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.252.07:54:01.55#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.252.07:54:01.55#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.252.07:54:01.55#ibcon#enter wrdev, iclass 4, count 0 2006.252.07:54:01.55#ibcon#first serial, iclass 4, count 0 2006.252.07:54:01.55#ibcon#enter sib2, iclass 4, count 0 2006.252.07:54:01.55#ibcon#flushed, iclass 4, count 0 2006.252.07:54:01.55#ibcon#about to write, iclass 4, count 0 2006.252.07:54:01.55#ibcon#wrote, iclass 4, count 0 2006.252.07:54:01.55#ibcon#about to read 3, iclass 4, count 0 2006.252.07:54:01.57#ibcon#read 3, iclass 4, count 0 2006.252.07:54:01.57#ibcon#about to read 4, iclass 4, count 0 2006.252.07:54:01.57#ibcon#read 4, iclass 4, count 0 2006.252.07:54:01.57#ibcon#about to read 5, iclass 4, count 0 2006.252.07:54:01.57#ibcon#read 5, iclass 4, count 0 2006.252.07:54:01.57#ibcon#about to read 6, iclass 4, count 0 2006.252.07:54:01.57#ibcon#read 6, iclass 4, count 0 2006.252.07:54:01.57#ibcon#end of sib2, iclass 4, count 0 2006.252.07:54:01.57#ibcon#*mode == 0, iclass 4, count 0 2006.252.07:54:01.57#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.252.07:54:01.57#ibcon#[28=FRQ=04,712.99\r\n] 2006.252.07:54:01.57#ibcon#*before write, iclass 4, count 0 2006.252.07:54:01.57#ibcon#enter sib2, iclass 4, count 0 2006.252.07:54:01.57#ibcon#flushed, iclass 4, count 0 2006.252.07:54:01.57#ibcon#about to write, iclass 4, count 0 2006.252.07:54:01.57#ibcon#wrote, iclass 4, count 0 2006.252.07:54:01.57#ibcon#about to read 3, iclass 4, count 0 2006.252.07:54:01.61#ibcon#read 3, iclass 4, count 0 2006.252.07:54:01.61#ibcon#about to read 4, iclass 4, count 0 2006.252.07:54:01.61#ibcon#read 4, iclass 4, count 0 2006.252.07:54:01.61#ibcon#about to read 5, iclass 4, count 0 2006.252.07:54:01.61#ibcon#read 5, iclass 4, count 0 2006.252.07:54:01.61#ibcon#about to read 6, iclass 4, count 0 2006.252.07:54:01.61#ibcon#read 6, iclass 4, count 0 2006.252.07:54:01.61#ibcon#end of sib2, iclass 4, count 0 2006.252.07:54:01.61#ibcon#*after write, iclass 4, count 0 2006.252.07:54:01.61#ibcon#*before return 0, iclass 4, count 0 2006.252.07:54:01.61#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.252.07:54:01.61#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.252.07:54:01.61#ibcon#about to clear, iclass 4 cls_cnt 0 2006.252.07:54:01.61#ibcon#cleared, iclass 4 cls_cnt 0 2006.252.07:54:01.61$vc4f8/vb=4,4 2006.252.07:54:01.61#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.252.07:54:01.61#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.252.07:54:01.61#ibcon#ireg 11 cls_cnt 2 2006.252.07:54:01.61#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.252.07:54:01.67#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.252.07:54:01.67#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.252.07:54:01.67#ibcon#enter wrdev, iclass 6, count 2 2006.252.07:54:01.67#ibcon#first serial, iclass 6, count 2 2006.252.07:54:01.67#ibcon#enter sib2, iclass 6, count 2 2006.252.07:54:01.67#ibcon#flushed, iclass 6, count 2 2006.252.07:54:01.67#ibcon#about to write, iclass 6, count 2 2006.252.07:54:01.67#ibcon#wrote, iclass 6, count 2 2006.252.07:54:01.67#ibcon#about to read 3, iclass 6, count 2 2006.252.07:54:01.70#ibcon#read 3, iclass 6, count 2 2006.252.07:54:01.70#ibcon#about to read 4, iclass 6, count 2 2006.252.07:54:01.70#ibcon#read 4, iclass 6, count 2 2006.252.07:54:01.70#ibcon#about to read 5, iclass 6, count 2 2006.252.07:54:01.70#ibcon#read 5, iclass 6, count 2 2006.252.07:54:01.70#ibcon#about to read 6, iclass 6, count 2 2006.252.07:54:01.70#ibcon#read 6, iclass 6, count 2 2006.252.07:54:01.70#ibcon#end of sib2, iclass 6, count 2 2006.252.07:54:01.70#ibcon#*mode == 0, iclass 6, count 2 2006.252.07:54:01.70#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.252.07:54:01.70#ibcon#[27=AT04-04\r\n] 2006.252.07:54:01.70#ibcon#*before write, iclass 6, count 2 2006.252.07:54:01.70#ibcon#enter sib2, iclass 6, count 2 2006.252.07:54:01.70#ibcon#flushed, iclass 6, count 2 2006.252.07:54:01.70#ibcon#about to write, iclass 6, count 2 2006.252.07:54:01.70#ibcon#wrote, iclass 6, count 2 2006.252.07:54:01.70#ibcon#about to read 3, iclass 6, count 2 2006.252.07:54:01.73#ibcon#read 3, iclass 6, count 2 2006.252.07:54:01.73#ibcon#about to read 4, iclass 6, count 2 2006.252.07:54:01.73#ibcon#read 4, iclass 6, count 2 2006.252.07:54:01.73#ibcon#about to read 5, iclass 6, count 2 2006.252.07:54:01.73#ibcon#read 5, iclass 6, count 2 2006.252.07:54:01.73#ibcon#about to read 6, iclass 6, count 2 2006.252.07:54:01.73#ibcon#read 6, iclass 6, count 2 2006.252.07:54:01.73#ibcon#end of sib2, iclass 6, count 2 2006.252.07:54:01.73#ibcon#*after write, iclass 6, count 2 2006.252.07:54:01.73#ibcon#*before return 0, iclass 6, count 2 2006.252.07:54:01.73#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.252.07:54:01.73#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.252.07:54:01.73#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.252.07:54:01.73#ibcon#ireg 7 cls_cnt 0 2006.252.07:54:01.73#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.252.07:54:01.85#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.252.07:54:01.85#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.252.07:54:01.85#ibcon#enter wrdev, iclass 6, count 0 2006.252.07:54:01.85#ibcon#first serial, iclass 6, count 0 2006.252.07:54:01.85#ibcon#enter sib2, iclass 6, count 0 2006.252.07:54:01.85#ibcon#flushed, iclass 6, count 0 2006.252.07:54:01.85#ibcon#about to write, iclass 6, count 0 2006.252.07:54:01.85#ibcon#wrote, iclass 6, count 0 2006.252.07:54:01.85#ibcon#about to read 3, iclass 6, count 0 2006.252.07:54:01.87#ibcon#read 3, iclass 6, count 0 2006.252.07:54:01.87#ibcon#about to read 4, iclass 6, count 0 2006.252.07:54:01.87#ibcon#read 4, iclass 6, count 0 2006.252.07:54:01.87#ibcon#about to read 5, iclass 6, count 0 2006.252.07:54:01.87#ibcon#read 5, iclass 6, count 0 2006.252.07:54:01.87#ibcon#about to read 6, iclass 6, count 0 2006.252.07:54:01.87#ibcon#read 6, iclass 6, count 0 2006.252.07:54:01.87#ibcon#end of sib2, iclass 6, count 0 2006.252.07:54:01.87#ibcon#*mode == 0, iclass 6, count 0 2006.252.07:54:01.87#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.252.07:54:01.87#ibcon#[27=USB\r\n] 2006.252.07:54:01.87#ibcon#*before write, iclass 6, count 0 2006.252.07:54:01.87#ibcon#enter sib2, iclass 6, count 0 2006.252.07:54:01.87#ibcon#flushed, iclass 6, count 0 2006.252.07:54:01.87#ibcon#about to write, iclass 6, count 0 2006.252.07:54:01.87#ibcon#wrote, iclass 6, count 0 2006.252.07:54:01.87#ibcon#about to read 3, iclass 6, count 0 2006.252.07:54:01.90#ibcon#read 3, iclass 6, count 0 2006.252.07:54:01.90#ibcon#about to read 4, iclass 6, count 0 2006.252.07:54:01.90#ibcon#read 4, iclass 6, count 0 2006.252.07:54:01.90#ibcon#about to read 5, iclass 6, count 0 2006.252.07:54:01.90#ibcon#read 5, iclass 6, count 0 2006.252.07:54:01.90#ibcon#about to read 6, iclass 6, count 0 2006.252.07:54:01.90#ibcon#read 6, iclass 6, count 0 2006.252.07:54:01.90#ibcon#end of sib2, iclass 6, count 0 2006.252.07:54:01.90#ibcon#*after write, iclass 6, count 0 2006.252.07:54:01.90#ibcon#*before return 0, iclass 6, count 0 2006.252.07:54:01.90#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.252.07:54:01.90#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.252.07:54:01.90#ibcon#about to clear, iclass 6 cls_cnt 0 2006.252.07:54:01.90#ibcon#cleared, iclass 6 cls_cnt 0 2006.252.07:54:01.90$vc4f8/vblo=5,744.99 2006.252.07:54:01.90#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.252.07:54:01.90#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.252.07:54:01.90#ibcon#ireg 17 cls_cnt 0 2006.252.07:54:01.90#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.252.07:54:01.90#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.252.07:54:01.90#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.252.07:54:01.90#ibcon#enter wrdev, iclass 10, count 0 2006.252.07:54:01.90#ibcon#first serial, iclass 10, count 0 2006.252.07:54:01.90#ibcon#enter sib2, iclass 10, count 0 2006.252.07:54:01.90#ibcon#flushed, iclass 10, count 0 2006.252.07:54:01.90#ibcon#about to write, iclass 10, count 0 2006.252.07:54:01.90#ibcon#wrote, iclass 10, count 0 2006.252.07:54:01.90#ibcon#about to read 3, iclass 10, count 0 2006.252.07:54:01.92#ibcon#read 3, iclass 10, count 0 2006.252.07:54:01.92#ibcon#about to read 4, iclass 10, count 0 2006.252.07:54:01.92#ibcon#read 4, iclass 10, count 0 2006.252.07:54:01.92#ibcon#about to read 5, iclass 10, count 0 2006.252.07:54:01.92#ibcon#read 5, iclass 10, count 0 2006.252.07:54:01.92#ibcon#about to read 6, iclass 10, count 0 2006.252.07:54:01.92#ibcon#read 6, iclass 10, count 0 2006.252.07:54:01.92#ibcon#end of sib2, iclass 10, count 0 2006.252.07:54:01.92#ibcon#*mode == 0, iclass 10, count 0 2006.252.07:54:01.92#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.252.07:54:01.92#ibcon#[28=FRQ=05,744.99\r\n] 2006.252.07:54:01.92#ibcon#*before write, iclass 10, count 0 2006.252.07:54:01.92#ibcon#enter sib2, iclass 10, count 0 2006.252.07:54:01.92#ibcon#flushed, iclass 10, count 0 2006.252.07:54:01.92#ibcon#about to write, iclass 10, count 0 2006.252.07:54:01.92#ibcon#wrote, iclass 10, count 0 2006.252.07:54:01.92#ibcon#about to read 3, iclass 10, count 0 2006.252.07:54:01.96#ibcon#read 3, iclass 10, count 0 2006.252.07:54:01.96#ibcon#about to read 4, iclass 10, count 0 2006.252.07:54:01.96#ibcon#read 4, iclass 10, count 0 2006.252.07:54:01.96#ibcon#about to read 5, iclass 10, count 0 2006.252.07:54:01.96#ibcon#read 5, iclass 10, count 0 2006.252.07:54:01.96#ibcon#about to read 6, iclass 10, count 0 2006.252.07:54:01.96#ibcon#read 6, iclass 10, count 0 2006.252.07:54:01.96#ibcon#end of sib2, iclass 10, count 0 2006.252.07:54:01.96#ibcon#*after write, iclass 10, count 0 2006.252.07:54:01.96#ibcon#*before return 0, iclass 10, count 0 2006.252.07:54:01.96#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.252.07:54:01.96#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.252.07:54:01.96#ibcon#about to clear, iclass 10 cls_cnt 0 2006.252.07:54:01.96#ibcon#cleared, iclass 10 cls_cnt 0 2006.252.07:54:01.96$vc4f8/vb=5,4 2006.252.07:54:01.96#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.252.07:54:01.96#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.252.07:54:01.96#ibcon#ireg 11 cls_cnt 2 2006.252.07:54:01.96#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.252.07:54:02.02#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.252.07:54:02.02#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.252.07:54:02.02#ibcon#enter wrdev, iclass 12, count 2 2006.252.07:54:02.02#ibcon#first serial, iclass 12, count 2 2006.252.07:54:02.02#ibcon#enter sib2, iclass 12, count 2 2006.252.07:54:02.02#ibcon#flushed, iclass 12, count 2 2006.252.07:54:02.02#ibcon#about to write, iclass 12, count 2 2006.252.07:54:02.02#ibcon#wrote, iclass 12, count 2 2006.252.07:54:02.02#ibcon#about to read 3, iclass 12, count 2 2006.252.07:54:02.04#ibcon#read 3, iclass 12, count 2 2006.252.07:54:02.04#ibcon#about to read 4, iclass 12, count 2 2006.252.07:54:02.04#ibcon#read 4, iclass 12, count 2 2006.252.07:54:02.04#ibcon#about to read 5, iclass 12, count 2 2006.252.07:54:02.04#ibcon#read 5, iclass 12, count 2 2006.252.07:54:02.04#ibcon#about to read 6, iclass 12, count 2 2006.252.07:54:02.04#ibcon#read 6, iclass 12, count 2 2006.252.07:54:02.04#ibcon#end of sib2, iclass 12, count 2 2006.252.07:54:02.04#ibcon#*mode == 0, iclass 12, count 2 2006.252.07:54:02.04#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.252.07:54:02.04#ibcon#[27=AT05-04\r\n] 2006.252.07:54:02.04#ibcon#*before write, iclass 12, count 2 2006.252.07:54:02.04#ibcon#enter sib2, iclass 12, count 2 2006.252.07:54:02.04#ibcon#flushed, iclass 12, count 2 2006.252.07:54:02.04#ibcon#about to write, iclass 12, count 2 2006.252.07:54:02.04#ibcon#wrote, iclass 12, count 2 2006.252.07:54:02.04#ibcon#about to read 3, iclass 12, count 2 2006.252.07:54:02.07#ibcon#read 3, iclass 12, count 2 2006.252.07:54:02.07#ibcon#about to read 4, iclass 12, count 2 2006.252.07:54:02.07#ibcon#read 4, iclass 12, count 2 2006.252.07:54:02.07#ibcon#about to read 5, iclass 12, count 2 2006.252.07:54:02.07#ibcon#read 5, iclass 12, count 2 2006.252.07:54:02.07#ibcon#about to read 6, iclass 12, count 2 2006.252.07:54:02.07#ibcon#read 6, iclass 12, count 2 2006.252.07:54:02.07#ibcon#end of sib2, iclass 12, count 2 2006.252.07:54:02.07#ibcon#*after write, iclass 12, count 2 2006.252.07:54:02.07#ibcon#*before return 0, iclass 12, count 2 2006.252.07:54:02.07#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.252.07:54:02.07#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.252.07:54:02.07#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.252.07:54:02.07#ibcon#ireg 7 cls_cnt 0 2006.252.07:54:02.07#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.252.07:54:02.19#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.252.07:54:02.19#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.252.07:54:02.19#ibcon#enter wrdev, iclass 12, count 0 2006.252.07:54:02.19#ibcon#first serial, iclass 12, count 0 2006.252.07:54:02.19#ibcon#enter sib2, iclass 12, count 0 2006.252.07:54:02.19#ibcon#flushed, iclass 12, count 0 2006.252.07:54:02.19#ibcon#about to write, iclass 12, count 0 2006.252.07:54:02.19#ibcon#wrote, iclass 12, count 0 2006.252.07:54:02.19#ibcon#about to read 3, iclass 12, count 0 2006.252.07:54:02.21#ibcon#read 3, iclass 12, count 0 2006.252.07:54:02.21#ibcon#about to read 4, iclass 12, count 0 2006.252.07:54:02.21#ibcon#read 4, iclass 12, count 0 2006.252.07:54:02.21#ibcon#about to read 5, iclass 12, count 0 2006.252.07:54:02.21#ibcon#read 5, iclass 12, count 0 2006.252.07:54:02.21#ibcon#about to read 6, iclass 12, count 0 2006.252.07:54:02.21#ibcon#read 6, iclass 12, count 0 2006.252.07:54:02.21#ibcon#end of sib2, iclass 12, count 0 2006.252.07:54:02.21#ibcon#*mode == 0, iclass 12, count 0 2006.252.07:54:02.21#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.252.07:54:02.21#ibcon#[27=USB\r\n] 2006.252.07:54:02.21#ibcon#*before write, iclass 12, count 0 2006.252.07:54:02.21#ibcon#enter sib2, iclass 12, count 0 2006.252.07:54:02.21#ibcon#flushed, iclass 12, count 0 2006.252.07:54:02.21#ibcon#about to write, iclass 12, count 0 2006.252.07:54:02.21#ibcon#wrote, iclass 12, count 0 2006.252.07:54:02.21#ibcon#about to read 3, iclass 12, count 0 2006.252.07:54:02.24#ibcon#read 3, iclass 12, count 0 2006.252.07:54:02.24#ibcon#about to read 4, iclass 12, count 0 2006.252.07:54:02.24#ibcon#read 4, iclass 12, count 0 2006.252.07:54:02.24#ibcon#about to read 5, iclass 12, count 0 2006.252.07:54:02.24#ibcon#read 5, iclass 12, count 0 2006.252.07:54:02.24#ibcon#about to read 6, iclass 12, count 0 2006.252.07:54:02.24#ibcon#read 6, iclass 12, count 0 2006.252.07:54:02.24#ibcon#end of sib2, iclass 12, count 0 2006.252.07:54:02.24#ibcon#*after write, iclass 12, count 0 2006.252.07:54:02.24#ibcon#*before return 0, iclass 12, count 0 2006.252.07:54:02.24#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.252.07:54:02.24#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.252.07:54:02.24#ibcon#about to clear, iclass 12 cls_cnt 0 2006.252.07:54:02.24#ibcon#cleared, iclass 12 cls_cnt 0 2006.252.07:54:02.24$vc4f8/vblo=6,752.99 2006.252.07:54:02.24#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.252.07:54:02.24#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.252.07:54:02.24#ibcon#ireg 17 cls_cnt 0 2006.252.07:54:02.24#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.252.07:54:02.24#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.252.07:54:02.24#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.252.07:54:02.24#ibcon#enter wrdev, iclass 14, count 0 2006.252.07:54:02.24#ibcon#first serial, iclass 14, count 0 2006.252.07:54:02.24#ibcon#enter sib2, iclass 14, count 0 2006.252.07:54:02.24#ibcon#flushed, iclass 14, count 0 2006.252.07:54:02.24#ibcon#about to write, iclass 14, count 0 2006.252.07:54:02.24#ibcon#wrote, iclass 14, count 0 2006.252.07:54:02.24#ibcon#about to read 3, iclass 14, count 0 2006.252.07:54:02.26#ibcon#read 3, iclass 14, count 0 2006.252.07:54:02.26#ibcon#about to read 4, iclass 14, count 0 2006.252.07:54:02.26#ibcon#read 4, iclass 14, count 0 2006.252.07:54:02.26#ibcon#about to read 5, iclass 14, count 0 2006.252.07:54:02.26#ibcon#read 5, iclass 14, count 0 2006.252.07:54:02.26#ibcon#about to read 6, iclass 14, count 0 2006.252.07:54:02.26#ibcon#read 6, iclass 14, count 0 2006.252.07:54:02.26#ibcon#end of sib2, iclass 14, count 0 2006.252.07:54:02.26#ibcon#*mode == 0, iclass 14, count 0 2006.252.07:54:02.26#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.252.07:54:02.26#ibcon#[28=FRQ=06,752.99\r\n] 2006.252.07:54:02.26#ibcon#*before write, iclass 14, count 0 2006.252.07:54:02.26#ibcon#enter sib2, iclass 14, count 0 2006.252.07:54:02.26#ibcon#flushed, iclass 14, count 0 2006.252.07:54:02.26#ibcon#about to write, iclass 14, count 0 2006.252.07:54:02.26#ibcon#wrote, iclass 14, count 0 2006.252.07:54:02.26#ibcon#about to read 3, iclass 14, count 0 2006.252.07:54:02.30#ibcon#read 3, iclass 14, count 0 2006.252.07:54:02.30#ibcon#about to read 4, iclass 14, count 0 2006.252.07:54:02.30#ibcon#read 4, iclass 14, count 0 2006.252.07:54:02.30#ibcon#about to read 5, iclass 14, count 0 2006.252.07:54:02.30#ibcon#read 5, iclass 14, count 0 2006.252.07:54:02.30#ibcon#about to read 6, iclass 14, count 0 2006.252.07:54:02.30#ibcon#read 6, iclass 14, count 0 2006.252.07:54:02.30#ibcon#end of sib2, iclass 14, count 0 2006.252.07:54:02.30#ibcon#*after write, iclass 14, count 0 2006.252.07:54:02.30#ibcon#*before return 0, iclass 14, count 0 2006.252.07:54:02.30#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.252.07:54:02.30#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.252.07:54:02.30#ibcon#about to clear, iclass 14 cls_cnt 0 2006.252.07:54:02.30#ibcon#cleared, iclass 14 cls_cnt 0 2006.252.07:54:02.30$vc4f8/vb=6,4 2006.252.07:54:02.30#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.252.07:54:02.30#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.252.07:54:02.30#ibcon#ireg 11 cls_cnt 2 2006.252.07:54:02.30#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.252.07:54:02.36#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.252.07:54:02.36#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.252.07:54:02.36#ibcon#enter wrdev, iclass 16, count 2 2006.252.07:54:02.36#ibcon#first serial, iclass 16, count 2 2006.252.07:54:02.36#ibcon#enter sib2, iclass 16, count 2 2006.252.07:54:02.36#ibcon#flushed, iclass 16, count 2 2006.252.07:54:02.36#ibcon#about to write, iclass 16, count 2 2006.252.07:54:02.36#ibcon#wrote, iclass 16, count 2 2006.252.07:54:02.36#ibcon#about to read 3, iclass 16, count 2 2006.252.07:54:02.38#ibcon#read 3, iclass 16, count 2 2006.252.07:54:02.38#ibcon#about to read 4, iclass 16, count 2 2006.252.07:54:02.38#ibcon#read 4, iclass 16, count 2 2006.252.07:54:02.38#ibcon#about to read 5, iclass 16, count 2 2006.252.07:54:02.38#ibcon#read 5, iclass 16, count 2 2006.252.07:54:02.38#ibcon#about to read 6, iclass 16, count 2 2006.252.07:54:02.38#ibcon#read 6, iclass 16, count 2 2006.252.07:54:02.38#ibcon#end of sib2, iclass 16, count 2 2006.252.07:54:02.38#ibcon#*mode == 0, iclass 16, count 2 2006.252.07:54:02.38#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.252.07:54:02.38#ibcon#[27=AT06-04\r\n] 2006.252.07:54:02.38#ibcon#*before write, iclass 16, count 2 2006.252.07:54:02.38#ibcon#enter sib2, iclass 16, count 2 2006.252.07:54:02.38#ibcon#flushed, iclass 16, count 2 2006.252.07:54:02.38#ibcon#about to write, iclass 16, count 2 2006.252.07:54:02.38#ibcon#wrote, iclass 16, count 2 2006.252.07:54:02.38#ibcon#about to read 3, iclass 16, count 2 2006.252.07:54:02.41#ibcon#read 3, iclass 16, count 2 2006.252.07:54:02.41#ibcon#about to read 4, iclass 16, count 2 2006.252.07:54:02.41#ibcon#read 4, iclass 16, count 2 2006.252.07:54:02.41#ibcon#about to read 5, iclass 16, count 2 2006.252.07:54:02.41#ibcon#read 5, iclass 16, count 2 2006.252.07:54:02.41#ibcon#about to read 6, iclass 16, count 2 2006.252.07:54:02.41#ibcon#read 6, iclass 16, count 2 2006.252.07:54:02.41#ibcon#end of sib2, iclass 16, count 2 2006.252.07:54:02.41#ibcon#*after write, iclass 16, count 2 2006.252.07:54:02.41#ibcon#*before return 0, iclass 16, count 2 2006.252.07:54:02.41#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.252.07:54:02.41#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.252.07:54:02.41#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.252.07:54:02.41#ibcon#ireg 7 cls_cnt 0 2006.252.07:54:02.41#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.252.07:54:02.53#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.252.07:54:02.53#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.252.07:54:02.53#ibcon#enter wrdev, iclass 16, count 0 2006.252.07:54:02.53#ibcon#first serial, iclass 16, count 0 2006.252.07:54:02.53#ibcon#enter sib2, iclass 16, count 0 2006.252.07:54:02.53#ibcon#flushed, iclass 16, count 0 2006.252.07:54:02.53#ibcon#about to write, iclass 16, count 0 2006.252.07:54:02.53#ibcon#wrote, iclass 16, count 0 2006.252.07:54:02.53#ibcon#about to read 3, iclass 16, count 0 2006.252.07:54:02.55#ibcon#read 3, iclass 16, count 0 2006.252.07:54:02.55#ibcon#about to read 4, iclass 16, count 0 2006.252.07:54:02.55#ibcon#read 4, iclass 16, count 0 2006.252.07:54:02.55#ibcon#about to read 5, iclass 16, count 0 2006.252.07:54:02.55#ibcon#read 5, iclass 16, count 0 2006.252.07:54:02.55#ibcon#about to read 6, iclass 16, count 0 2006.252.07:54:02.55#ibcon#read 6, iclass 16, count 0 2006.252.07:54:02.55#ibcon#end of sib2, iclass 16, count 0 2006.252.07:54:02.55#ibcon#*mode == 0, iclass 16, count 0 2006.252.07:54:02.55#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.252.07:54:02.55#ibcon#[27=USB\r\n] 2006.252.07:54:02.55#ibcon#*before write, iclass 16, count 0 2006.252.07:54:02.55#ibcon#enter sib2, iclass 16, count 0 2006.252.07:54:02.55#ibcon#flushed, iclass 16, count 0 2006.252.07:54:02.55#ibcon#about to write, iclass 16, count 0 2006.252.07:54:02.55#ibcon#wrote, iclass 16, count 0 2006.252.07:54:02.55#ibcon#about to read 3, iclass 16, count 0 2006.252.07:54:02.58#ibcon#read 3, iclass 16, count 0 2006.252.07:54:02.58#ibcon#about to read 4, iclass 16, count 0 2006.252.07:54:02.58#ibcon#read 4, iclass 16, count 0 2006.252.07:54:02.58#ibcon#about to read 5, iclass 16, count 0 2006.252.07:54:02.58#ibcon#read 5, iclass 16, count 0 2006.252.07:54:02.58#ibcon#about to read 6, iclass 16, count 0 2006.252.07:54:02.58#ibcon#read 6, iclass 16, count 0 2006.252.07:54:02.58#ibcon#end of sib2, iclass 16, count 0 2006.252.07:54:02.58#ibcon#*after write, iclass 16, count 0 2006.252.07:54:02.58#ibcon#*before return 0, iclass 16, count 0 2006.252.07:54:02.58#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.252.07:54:02.58#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.252.07:54:02.58#ibcon#about to clear, iclass 16 cls_cnt 0 2006.252.07:54:02.58#ibcon#cleared, iclass 16 cls_cnt 0 2006.252.07:54:02.58$vc4f8/vabw=wide 2006.252.07:54:02.58#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.252.07:54:02.58#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.252.07:54:02.58#ibcon#ireg 8 cls_cnt 0 2006.252.07:54:02.58#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.252.07:54:02.58#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.252.07:54:02.58#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.252.07:54:02.58#ibcon#enter wrdev, iclass 18, count 0 2006.252.07:54:02.58#ibcon#first serial, iclass 18, count 0 2006.252.07:54:02.58#ibcon#enter sib2, iclass 18, count 0 2006.252.07:54:02.58#ibcon#flushed, iclass 18, count 0 2006.252.07:54:02.58#ibcon#about to write, iclass 18, count 0 2006.252.07:54:02.58#ibcon#wrote, iclass 18, count 0 2006.252.07:54:02.58#ibcon#about to read 3, iclass 18, count 0 2006.252.07:54:02.60#ibcon#read 3, iclass 18, count 0 2006.252.07:54:02.60#ibcon#about to read 4, iclass 18, count 0 2006.252.07:54:02.60#ibcon#read 4, iclass 18, count 0 2006.252.07:54:02.60#ibcon#about to read 5, iclass 18, count 0 2006.252.07:54:02.60#ibcon#read 5, iclass 18, count 0 2006.252.07:54:02.60#ibcon#about to read 6, iclass 18, count 0 2006.252.07:54:02.60#ibcon#read 6, iclass 18, count 0 2006.252.07:54:02.60#ibcon#end of sib2, iclass 18, count 0 2006.252.07:54:02.60#ibcon#*mode == 0, iclass 18, count 0 2006.252.07:54:02.60#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.252.07:54:02.60#ibcon#[25=BW32\r\n] 2006.252.07:54:02.60#ibcon#*before write, iclass 18, count 0 2006.252.07:54:02.60#ibcon#enter sib2, iclass 18, count 0 2006.252.07:54:02.60#ibcon#flushed, iclass 18, count 0 2006.252.07:54:02.60#ibcon#about to write, iclass 18, count 0 2006.252.07:54:02.60#ibcon#wrote, iclass 18, count 0 2006.252.07:54:02.60#ibcon#about to read 3, iclass 18, count 0 2006.252.07:54:02.63#ibcon#read 3, iclass 18, count 0 2006.252.07:54:02.63#ibcon#about to read 4, iclass 18, count 0 2006.252.07:54:02.63#ibcon#read 4, iclass 18, count 0 2006.252.07:54:02.63#ibcon#about to read 5, iclass 18, count 0 2006.252.07:54:02.63#ibcon#read 5, iclass 18, count 0 2006.252.07:54:02.63#ibcon#about to read 6, iclass 18, count 0 2006.252.07:54:02.63#ibcon#read 6, iclass 18, count 0 2006.252.07:54:02.63#ibcon#end of sib2, iclass 18, count 0 2006.252.07:54:02.63#ibcon#*after write, iclass 18, count 0 2006.252.07:54:02.63#ibcon#*before return 0, iclass 18, count 0 2006.252.07:54:02.63#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.252.07:54:02.63#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.252.07:54:02.63#ibcon#about to clear, iclass 18 cls_cnt 0 2006.252.07:54:02.63#ibcon#cleared, iclass 18 cls_cnt 0 2006.252.07:54:02.63$vc4f8/vbbw=wide 2006.252.07:54:02.63#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.252.07:54:02.63#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.252.07:54:02.63#ibcon#ireg 8 cls_cnt 0 2006.252.07:54:02.63#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.252.07:54:02.70#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.252.07:54:02.70#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.252.07:54:02.70#ibcon#enter wrdev, iclass 20, count 0 2006.252.07:54:02.70#ibcon#first serial, iclass 20, count 0 2006.252.07:54:02.70#ibcon#enter sib2, iclass 20, count 0 2006.252.07:54:02.70#ibcon#flushed, iclass 20, count 0 2006.252.07:54:02.70#ibcon#about to write, iclass 20, count 0 2006.252.07:54:02.70#ibcon#wrote, iclass 20, count 0 2006.252.07:54:02.70#ibcon#about to read 3, iclass 20, count 0 2006.252.07:54:02.72#ibcon#read 3, iclass 20, count 0 2006.252.07:54:02.72#ibcon#about to read 4, iclass 20, count 0 2006.252.07:54:02.72#ibcon#read 4, iclass 20, count 0 2006.252.07:54:02.72#ibcon#about to read 5, iclass 20, count 0 2006.252.07:54:02.72#ibcon#read 5, iclass 20, count 0 2006.252.07:54:02.72#ibcon#about to read 6, iclass 20, count 0 2006.252.07:54:02.72#ibcon#read 6, iclass 20, count 0 2006.252.07:54:02.72#ibcon#end of sib2, iclass 20, count 0 2006.252.07:54:02.72#ibcon#*mode == 0, iclass 20, count 0 2006.252.07:54:02.72#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.252.07:54:02.72#ibcon#[27=BW32\r\n] 2006.252.07:54:02.72#ibcon#*before write, iclass 20, count 0 2006.252.07:54:02.72#ibcon#enter sib2, iclass 20, count 0 2006.252.07:54:02.72#ibcon#flushed, iclass 20, count 0 2006.252.07:54:02.72#ibcon#about to write, iclass 20, count 0 2006.252.07:54:02.72#ibcon#wrote, iclass 20, count 0 2006.252.07:54:02.72#ibcon#about to read 3, iclass 20, count 0 2006.252.07:54:02.75#ibcon#read 3, iclass 20, count 0 2006.252.07:54:02.75#ibcon#about to read 4, iclass 20, count 0 2006.252.07:54:02.75#ibcon#read 4, iclass 20, count 0 2006.252.07:54:02.75#ibcon#about to read 5, iclass 20, count 0 2006.252.07:54:02.75#ibcon#read 5, iclass 20, count 0 2006.252.07:54:02.75#ibcon#about to read 6, iclass 20, count 0 2006.252.07:54:02.75#ibcon#read 6, iclass 20, count 0 2006.252.07:54:02.75#ibcon#end of sib2, iclass 20, count 0 2006.252.07:54:02.75#ibcon#*after write, iclass 20, count 0 2006.252.07:54:02.75#ibcon#*before return 0, iclass 20, count 0 2006.252.07:54:02.75#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.252.07:54:02.75#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.252.07:54:02.75#ibcon#about to clear, iclass 20 cls_cnt 0 2006.252.07:54:02.75#ibcon#cleared, iclass 20 cls_cnt 0 2006.252.07:54:02.75$4f8m12a/ifd4f 2006.252.07:54:02.75$ifd4f/lo= 2006.252.07:54:02.75$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.252.07:54:02.75$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.252.07:54:02.75$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.252.07:54:02.75$ifd4f/patch= 2006.252.07:54:02.75$ifd4f/patch=lo1,a1,a2,a3,a4 2006.252.07:54:02.75$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.252.07:54:02.75$ifd4f/patch=lo3,a5,a6,a7,a8 2006.252.07:54:02.75$4f8m12a/"form=m,16.000,1:2 2006.252.07:54:02.75$4f8m12a/"tpicd 2006.252.07:54:02.75$4f8m12a/echo=off 2006.252.07:54:02.75$4f8m12a/xlog=off 2006.252.07:54:02.75:!2006.252.07:55:10 2006.252.07:54:15.13#trakl#Source acquired 2006.252.07:54:15.13#flagr#flagr/antenna,acquired 2006.252.07:55:10.00:preob 2006.252.07:55:10.14/onsource/TRACKING 2006.252.07:55:10.14:!2006.252.07:55:20 2006.252.07:55:20.00:data_valid=on 2006.252.07:55:20.00:midob 2006.252.07:55:21.14/onsource/TRACKING 2006.252.07:55:21.14/wx/27.38,1011.2,89 2006.252.07:55:21.20/cable/+6.4117E-03 2006.252.07:55:22.29/va/01,08,usb,yes,46,48 2006.252.07:55:22.29/va/02,07,usb,yes,46,48 2006.252.07:55:22.29/va/03,06,usb,yes,48,48 2006.252.07:55:22.29/va/04,07,usb,yes,46,50 2006.252.07:55:22.29/va/05,07,usb,yes,51,54 2006.252.07:55:22.29/va/06,07,usb,yes,45,45 2006.252.07:55:22.29/va/07,07,usb,yes,44,44 2006.252.07:55:22.29/va/08,07,usb,yes,48,47 2006.252.07:55:22.52/valo/01,532.99,yes,locked 2006.252.07:55:22.52/valo/02,572.99,yes,locked 2006.252.07:55:22.52/valo/03,672.99,yes,locked 2006.252.07:55:22.52/valo/04,832.99,yes,locked 2006.252.07:55:22.52/valo/05,652.99,yes,locked 2006.252.07:55:22.52/valo/06,772.99,yes,locked 2006.252.07:55:22.52/valo/07,832.99,yes,locked 2006.252.07:55:22.52/valo/08,852.99,yes,locked 2006.252.07:55:23.61/vb/01,04,usb,yes,41,39 2006.252.07:55:23.61/vb/02,05,usb,yes,38,39 2006.252.07:55:23.61/vb/03,04,usb,yes,38,43 2006.252.07:55:23.61/vb/04,04,usb,yes,40,40 2006.252.07:55:23.61/vb/05,04,usb,yes,37,43 2006.252.07:55:23.61/vb/06,04,usb,yes,38,42 2006.252.07:55:23.61/vb/07,04,usb,yes,41,42 2006.252.07:55:23.61/vb/08,04,usb,yes,38,42 2006.252.07:55:23.84/vblo/01,632.99,yes,locked 2006.252.07:55:23.84/vblo/02,640.99,yes,locked 2006.252.07:55:23.84/vblo/03,656.99,yes,locked 2006.252.07:55:23.84/vblo/04,712.99,yes,locked 2006.252.07:55:23.84/vblo/05,744.99,yes,locked 2006.252.07:55:23.84/vblo/06,752.99,yes,locked 2006.252.07:55:23.84/vblo/07,734.99,yes,locked 2006.252.07:55:23.84/vblo/08,744.99,yes,locked 2006.252.07:55:23.99/vabw/8 2006.252.07:55:24.14/vbbw/8 2006.252.07:55:24.23/xfe/off,on,14.0 2006.252.07:55:24.60/ifatt/23,28,28,28 2006.252.07:55:25.07/fmout-gps/S +4.80E-07 2006.252.07:55:25.11:!2006.252.07:56:20 2006.252.07:56:20.01:data_valid=off 2006.252.07:56:20.01:postob 2006.252.07:56:20.20/cable/+6.4107E-03 2006.252.07:56:20.20/wx/27.37,1011.2,89 2006.252.07:56:21.07/fmout-gps/S +4.81E-07 2006.252.07:56:21.07:scan_name=252-0758,k06252,60 2006.252.07:56:21.08:source=0059+581,010245.76,582411.1,2000.0,cw 2006.252.07:56:21.14#flagr#flagr/antenna,new-source 2006.252.07:56:22.14:checkk5 2006.252.07:56:22.52/chk_autoobs//k5ts1/ autoobs is running! 2006.252.07:56:22.89/chk_autoobs//k5ts2/ autoobs is running! 2006.252.07:56:23.27/chk_autoobs//k5ts3/ autoobs is running! 2006.252.07:56:23.64/chk_autoobs//k5ts4/ autoobs is running! 2006.252.07:56:24.00/chk_obsdata//k5ts1/T2520755??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.07:56:24.37/chk_obsdata//k5ts2/T2520755??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.07:56:24.74/chk_obsdata//k5ts3/T2520755??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.07:56:25.11/chk_obsdata//k5ts4/T2520755??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.07:56:25.81/k5log//k5ts1_log_newline 2006.252.07:56:26.50/k5log//k5ts2_log_newline 2006.252.07:56:27.19/k5log//k5ts3_log_newline 2006.252.07:56:27.88/k5log//k5ts4_log_newline 2006.252.07:56:27.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.252.07:56:27.90:4f8m12a=2 2006.252.07:56:27.90$4f8m12a/echo=on 2006.252.07:56:27.91$4f8m12a/pcalon 2006.252.07:56:27.91$pcalon/"no phase cal control is implemented here 2006.252.07:56:27.91$4f8m12a/"tpicd=stop 2006.252.07:56:27.91$4f8m12a/vc4f8 2006.252.07:56:27.91$vc4f8/valo=1,532.99 2006.252.07:56:27.91#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.252.07:56:27.91#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.252.07:56:27.91#ibcon#ireg 17 cls_cnt 0 2006.252.07:56:27.91#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.252.07:56:27.91#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.252.07:56:27.91#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.252.07:56:27.91#ibcon#enter wrdev, iclass 38, count 0 2006.252.07:56:27.91#ibcon#first serial, iclass 38, count 0 2006.252.07:56:27.91#ibcon#enter sib2, iclass 38, count 0 2006.252.07:56:27.91#ibcon#flushed, iclass 38, count 0 2006.252.07:56:27.91#ibcon#about to write, iclass 38, count 0 2006.252.07:56:27.91#ibcon#wrote, iclass 38, count 0 2006.252.07:56:27.91#ibcon#about to read 3, iclass 38, count 0 2006.252.07:56:27.95#ibcon#read 3, iclass 38, count 0 2006.252.07:56:27.95#ibcon#about to read 4, iclass 38, count 0 2006.252.07:56:27.95#ibcon#read 4, iclass 38, count 0 2006.252.07:56:27.95#ibcon#about to read 5, iclass 38, count 0 2006.252.07:56:27.95#ibcon#read 5, iclass 38, count 0 2006.252.07:56:27.95#ibcon#about to read 6, iclass 38, count 0 2006.252.07:56:27.95#ibcon#read 6, iclass 38, count 0 2006.252.07:56:27.95#ibcon#end of sib2, iclass 38, count 0 2006.252.07:56:27.95#ibcon#*mode == 0, iclass 38, count 0 2006.252.07:56:27.95#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.252.07:56:27.95#ibcon#[26=FRQ=01,532.99\r\n] 2006.252.07:56:27.95#ibcon#*before write, iclass 38, count 0 2006.252.07:56:27.95#ibcon#enter sib2, iclass 38, count 0 2006.252.07:56:27.95#ibcon#flushed, iclass 38, count 0 2006.252.07:56:27.95#ibcon#about to write, iclass 38, count 0 2006.252.07:56:27.95#ibcon#wrote, iclass 38, count 0 2006.252.07:56:27.95#ibcon#about to read 3, iclass 38, count 0 2006.252.07:56:28.00#ibcon#read 3, iclass 38, count 0 2006.252.07:56:28.00#ibcon#about to read 4, iclass 38, count 0 2006.252.07:56:28.00#ibcon#read 4, iclass 38, count 0 2006.252.07:56:28.00#ibcon#about to read 5, iclass 38, count 0 2006.252.07:56:28.00#ibcon#read 5, iclass 38, count 0 2006.252.07:56:28.00#ibcon#about to read 6, iclass 38, count 0 2006.252.07:56:28.00#ibcon#read 6, iclass 38, count 0 2006.252.07:56:28.00#ibcon#end of sib2, iclass 38, count 0 2006.252.07:56:28.00#ibcon#*after write, iclass 38, count 0 2006.252.07:56:28.00#ibcon#*before return 0, iclass 38, count 0 2006.252.07:56:28.00#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.252.07:56:28.00#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.252.07:56:28.00#ibcon#about to clear, iclass 38 cls_cnt 0 2006.252.07:56:28.00#ibcon#cleared, iclass 38 cls_cnt 0 2006.252.07:56:28.00$vc4f8/va=1,8 2006.252.07:56:28.00#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.252.07:56:28.00#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.252.07:56:28.00#ibcon#ireg 11 cls_cnt 2 2006.252.07:56:28.00#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.252.07:56:28.00#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.252.07:56:28.00#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.252.07:56:28.00#ibcon#enter wrdev, iclass 40, count 2 2006.252.07:56:28.00#ibcon#first serial, iclass 40, count 2 2006.252.07:56:28.00#ibcon#enter sib2, iclass 40, count 2 2006.252.07:56:28.00#ibcon#flushed, iclass 40, count 2 2006.252.07:56:28.00#ibcon#about to write, iclass 40, count 2 2006.252.07:56:28.00#ibcon#wrote, iclass 40, count 2 2006.252.07:56:28.00#ibcon#about to read 3, iclass 40, count 2 2006.252.07:56:28.03#ibcon#read 3, iclass 40, count 2 2006.252.07:56:28.03#ibcon#about to read 4, iclass 40, count 2 2006.252.07:56:28.03#ibcon#read 4, iclass 40, count 2 2006.252.07:56:28.03#ibcon#about to read 5, iclass 40, count 2 2006.252.07:56:28.03#ibcon#read 5, iclass 40, count 2 2006.252.07:56:28.03#ibcon#about to read 6, iclass 40, count 2 2006.252.07:56:28.03#ibcon#read 6, iclass 40, count 2 2006.252.07:56:28.03#ibcon#end of sib2, iclass 40, count 2 2006.252.07:56:28.03#ibcon#*mode == 0, iclass 40, count 2 2006.252.07:56:28.03#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.252.07:56:28.03#ibcon#[25=AT01-08\r\n] 2006.252.07:56:28.03#ibcon#*before write, iclass 40, count 2 2006.252.07:56:28.03#ibcon#enter sib2, iclass 40, count 2 2006.252.07:56:28.03#ibcon#flushed, iclass 40, count 2 2006.252.07:56:28.03#ibcon#about to write, iclass 40, count 2 2006.252.07:56:28.03#ibcon#wrote, iclass 40, count 2 2006.252.07:56:28.03#ibcon#about to read 3, iclass 40, count 2 2006.252.07:56:28.06#ibcon#read 3, iclass 40, count 2 2006.252.07:56:28.06#ibcon#about to read 4, iclass 40, count 2 2006.252.07:56:28.06#ibcon#read 4, iclass 40, count 2 2006.252.07:56:28.06#ibcon#about to read 5, iclass 40, count 2 2006.252.07:56:28.06#ibcon#read 5, iclass 40, count 2 2006.252.07:56:28.06#ibcon#about to read 6, iclass 40, count 2 2006.252.07:56:28.06#ibcon#read 6, iclass 40, count 2 2006.252.07:56:28.06#ibcon#end of sib2, iclass 40, count 2 2006.252.07:56:28.06#ibcon#*after write, iclass 40, count 2 2006.252.07:56:28.06#ibcon#*before return 0, iclass 40, count 2 2006.252.07:56:28.06#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.252.07:56:28.06#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.252.07:56:28.06#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.252.07:56:28.06#ibcon#ireg 7 cls_cnt 0 2006.252.07:56:28.06#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.252.07:56:28.18#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.252.07:56:28.18#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.252.07:56:28.18#ibcon#enter wrdev, iclass 40, count 0 2006.252.07:56:28.18#ibcon#first serial, iclass 40, count 0 2006.252.07:56:28.18#ibcon#enter sib2, iclass 40, count 0 2006.252.07:56:28.18#ibcon#flushed, iclass 40, count 0 2006.252.07:56:28.18#ibcon#about to write, iclass 40, count 0 2006.252.07:56:28.18#ibcon#wrote, iclass 40, count 0 2006.252.07:56:28.18#ibcon#about to read 3, iclass 40, count 0 2006.252.07:56:28.20#ibcon#read 3, iclass 40, count 0 2006.252.07:56:28.20#ibcon#about to read 4, iclass 40, count 0 2006.252.07:56:28.20#ibcon#read 4, iclass 40, count 0 2006.252.07:56:28.20#ibcon#about to read 5, iclass 40, count 0 2006.252.07:56:28.20#ibcon#read 5, iclass 40, count 0 2006.252.07:56:28.20#ibcon#about to read 6, iclass 40, count 0 2006.252.07:56:28.20#ibcon#read 6, iclass 40, count 0 2006.252.07:56:28.20#ibcon#end of sib2, iclass 40, count 0 2006.252.07:56:28.20#ibcon#*mode == 0, iclass 40, count 0 2006.252.07:56:28.20#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.252.07:56:28.20#ibcon#[25=USB\r\n] 2006.252.07:56:28.20#ibcon#*before write, iclass 40, count 0 2006.252.07:56:28.20#ibcon#enter sib2, iclass 40, count 0 2006.252.07:56:28.20#ibcon#flushed, iclass 40, count 0 2006.252.07:56:28.20#ibcon#about to write, iclass 40, count 0 2006.252.07:56:28.20#ibcon#wrote, iclass 40, count 0 2006.252.07:56:28.20#ibcon#about to read 3, iclass 40, count 0 2006.252.07:56:28.23#ibcon#read 3, iclass 40, count 0 2006.252.07:56:28.23#ibcon#about to read 4, iclass 40, count 0 2006.252.07:56:28.23#ibcon#read 4, iclass 40, count 0 2006.252.07:56:28.23#ibcon#about to read 5, iclass 40, count 0 2006.252.07:56:28.23#ibcon#read 5, iclass 40, count 0 2006.252.07:56:28.23#ibcon#about to read 6, iclass 40, count 0 2006.252.07:56:28.23#ibcon#read 6, iclass 40, count 0 2006.252.07:56:28.23#ibcon#end of sib2, iclass 40, count 0 2006.252.07:56:28.23#ibcon#*after write, iclass 40, count 0 2006.252.07:56:28.23#ibcon#*before return 0, iclass 40, count 0 2006.252.07:56:28.23#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.252.07:56:28.23#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.252.07:56:28.23#ibcon#about to clear, iclass 40 cls_cnt 0 2006.252.07:56:28.23#ibcon#cleared, iclass 40 cls_cnt 0 2006.252.07:56:28.23$vc4f8/valo=2,572.99 2006.252.07:56:28.23#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.252.07:56:28.23#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.252.07:56:28.23#ibcon#ireg 17 cls_cnt 0 2006.252.07:56:28.23#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.252.07:56:28.23#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.252.07:56:28.23#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.252.07:56:28.23#ibcon#enter wrdev, iclass 4, count 0 2006.252.07:56:28.23#ibcon#first serial, iclass 4, count 0 2006.252.07:56:28.23#ibcon#enter sib2, iclass 4, count 0 2006.252.07:56:28.23#ibcon#flushed, iclass 4, count 0 2006.252.07:56:28.23#ibcon#about to write, iclass 4, count 0 2006.252.07:56:28.23#ibcon#wrote, iclass 4, count 0 2006.252.07:56:28.23#ibcon#about to read 3, iclass 4, count 0 2006.252.07:56:28.25#ibcon#read 3, iclass 4, count 0 2006.252.07:56:28.25#ibcon#about to read 4, iclass 4, count 0 2006.252.07:56:28.25#ibcon#read 4, iclass 4, count 0 2006.252.07:56:28.25#ibcon#about to read 5, iclass 4, count 0 2006.252.07:56:28.25#ibcon#read 5, iclass 4, count 0 2006.252.07:56:28.25#ibcon#about to read 6, iclass 4, count 0 2006.252.07:56:28.25#ibcon#read 6, iclass 4, count 0 2006.252.07:56:28.25#ibcon#end of sib2, iclass 4, count 0 2006.252.07:56:28.25#ibcon#*mode == 0, iclass 4, count 0 2006.252.07:56:28.25#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.252.07:56:28.25#ibcon#[26=FRQ=02,572.99\r\n] 2006.252.07:56:28.25#ibcon#*before write, iclass 4, count 0 2006.252.07:56:28.25#ibcon#enter sib2, iclass 4, count 0 2006.252.07:56:28.25#ibcon#flushed, iclass 4, count 0 2006.252.07:56:28.25#ibcon#about to write, iclass 4, count 0 2006.252.07:56:28.25#ibcon#wrote, iclass 4, count 0 2006.252.07:56:28.25#ibcon#about to read 3, iclass 4, count 0 2006.252.07:56:28.29#ibcon#read 3, iclass 4, count 0 2006.252.07:56:28.29#ibcon#about to read 4, iclass 4, count 0 2006.252.07:56:28.29#ibcon#read 4, iclass 4, count 0 2006.252.07:56:28.29#ibcon#about to read 5, iclass 4, count 0 2006.252.07:56:28.29#ibcon#read 5, iclass 4, count 0 2006.252.07:56:28.29#ibcon#about to read 6, iclass 4, count 0 2006.252.07:56:28.29#ibcon#read 6, iclass 4, count 0 2006.252.07:56:28.29#ibcon#end of sib2, iclass 4, count 0 2006.252.07:56:28.29#ibcon#*after write, iclass 4, count 0 2006.252.07:56:28.29#ibcon#*before return 0, iclass 4, count 0 2006.252.07:56:28.29#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.252.07:56:28.29#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.252.07:56:28.29#ibcon#about to clear, iclass 4 cls_cnt 0 2006.252.07:56:28.29#ibcon#cleared, iclass 4 cls_cnt 0 2006.252.07:56:28.29$vc4f8/va=2,7 2006.252.07:56:28.29#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.252.07:56:28.29#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.252.07:56:28.29#ibcon#ireg 11 cls_cnt 2 2006.252.07:56:28.29#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.252.07:56:28.35#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.252.07:56:28.35#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.252.07:56:28.35#ibcon#enter wrdev, iclass 6, count 2 2006.252.07:56:28.35#ibcon#first serial, iclass 6, count 2 2006.252.07:56:28.35#ibcon#enter sib2, iclass 6, count 2 2006.252.07:56:28.35#ibcon#flushed, iclass 6, count 2 2006.252.07:56:28.35#ibcon#about to write, iclass 6, count 2 2006.252.07:56:28.35#ibcon#wrote, iclass 6, count 2 2006.252.07:56:28.35#ibcon#about to read 3, iclass 6, count 2 2006.252.07:56:28.37#ibcon#read 3, iclass 6, count 2 2006.252.07:56:28.37#ibcon#about to read 4, iclass 6, count 2 2006.252.07:56:28.37#ibcon#read 4, iclass 6, count 2 2006.252.07:56:28.37#ibcon#about to read 5, iclass 6, count 2 2006.252.07:56:28.37#ibcon#read 5, iclass 6, count 2 2006.252.07:56:28.37#ibcon#about to read 6, iclass 6, count 2 2006.252.07:56:28.37#ibcon#read 6, iclass 6, count 2 2006.252.07:56:28.37#ibcon#end of sib2, iclass 6, count 2 2006.252.07:56:28.37#ibcon#*mode == 0, iclass 6, count 2 2006.252.07:56:28.37#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.252.07:56:28.37#ibcon#[25=AT02-07\r\n] 2006.252.07:56:28.37#ibcon#*before write, iclass 6, count 2 2006.252.07:56:28.37#ibcon#enter sib2, iclass 6, count 2 2006.252.07:56:28.37#ibcon#flushed, iclass 6, count 2 2006.252.07:56:28.37#ibcon#about to write, iclass 6, count 2 2006.252.07:56:28.37#ibcon#wrote, iclass 6, count 2 2006.252.07:56:28.37#ibcon#about to read 3, iclass 6, count 2 2006.252.07:56:28.40#ibcon#read 3, iclass 6, count 2 2006.252.07:56:28.40#ibcon#about to read 4, iclass 6, count 2 2006.252.07:56:28.40#ibcon#read 4, iclass 6, count 2 2006.252.07:56:28.40#ibcon#about to read 5, iclass 6, count 2 2006.252.07:56:28.40#ibcon#read 5, iclass 6, count 2 2006.252.07:56:28.40#ibcon#about to read 6, iclass 6, count 2 2006.252.07:56:28.40#ibcon#read 6, iclass 6, count 2 2006.252.07:56:28.40#ibcon#end of sib2, iclass 6, count 2 2006.252.07:56:28.40#ibcon#*after write, iclass 6, count 2 2006.252.07:56:28.40#ibcon#*before return 0, iclass 6, count 2 2006.252.07:56:28.40#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.252.07:56:28.40#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.252.07:56:28.40#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.252.07:56:28.40#ibcon#ireg 7 cls_cnt 0 2006.252.07:56:28.40#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.252.07:56:28.52#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.252.07:56:28.52#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.252.07:56:28.52#ibcon#enter wrdev, iclass 6, count 0 2006.252.07:56:28.52#ibcon#first serial, iclass 6, count 0 2006.252.07:56:28.52#ibcon#enter sib2, iclass 6, count 0 2006.252.07:56:28.52#ibcon#flushed, iclass 6, count 0 2006.252.07:56:28.52#ibcon#about to write, iclass 6, count 0 2006.252.07:56:28.52#ibcon#wrote, iclass 6, count 0 2006.252.07:56:28.52#ibcon#about to read 3, iclass 6, count 0 2006.252.07:56:28.54#ibcon#read 3, iclass 6, count 0 2006.252.07:56:28.54#ibcon#about to read 4, iclass 6, count 0 2006.252.07:56:28.54#ibcon#read 4, iclass 6, count 0 2006.252.07:56:28.54#ibcon#about to read 5, iclass 6, count 0 2006.252.07:56:28.54#ibcon#read 5, iclass 6, count 0 2006.252.07:56:28.54#ibcon#about to read 6, iclass 6, count 0 2006.252.07:56:28.54#ibcon#read 6, iclass 6, count 0 2006.252.07:56:28.54#ibcon#end of sib2, iclass 6, count 0 2006.252.07:56:28.54#ibcon#*mode == 0, iclass 6, count 0 2006.252.07:56:28.54#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.252.07:56:28.54#ibcon#[25=USB\r\n] 2006.252.07:56:28.54#ibcon#*before write, iclass 6, count 0 2006.252.07:56:28.54#ibcon#enter sib2, iclass 6, count 0 2006.252.07:56:28.54#ibcon#flushed, iclass 6, count 0 2006.252.07:56:28.54#ibcon#about to write, iclass 6, count 0 2006.252.07:56:28.54#ibcon#wrote, iclass 6, count 0 2006.252.07:56:28.54#ibcon#about to read 3, iclass 6, count 0 2006.252.07:56:28.57#ibcon#read 3, iclass 6, count 0 2006.252.07:56:28.57#ibcon#about to read 4, iclass 6, count 0 2006.252.07:56:28.57#ibcon#read 4, iclass 6, count 0 2006.252.07:56:28.57#ibcon#about to read 5, iclass 6, count 0 2006.252.07:56:28.57#ibcon#read 5, iclass 6, count 0 2006.252.07:56:28.57#ibcon#about to read 6, iclass 6, count 0 2006.252.07:56:28.57#ibcon#read 6, iclass 6, count 0 2006.252.07:56:28.57#ibcon#end of sib2, iclass 6, count 0 2006.252.07:56:28.57#ibcon#*after write, iclass 6, count 0 2006.252.07:56:28.57#ibcon#*before return 0, iclass 6, count 0 2006.252.07:56:28.57#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.252.07:56:28.57#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.252.07:56:28.57#ibcon#about to clear, iclass 6 cls_cnt 0 2006.252.07:56:28.57#ibcon#cleared, iclass 6 cls_cnt 0 2006.252.07:56:28.57$vc4f8/valo=3,672.99 2006.252.07:56:28.57#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.252.07:56:28.57#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.252.07:56:28.57#ibcon#ireg 17 cls_cnt 0 2006.252.07:56:28.57#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.252.07:56:28.57#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.252.07:56:28.57#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.252.07:56:28.57#ibcon#enter wrdev, iclass 10, count 0 2006.252.07:56:28.57#ibcon#first serial, iclass 10, count 0 2006.252.07:56:28.57#ibcon#enter sib2, iclass 10, count 0 2006.252.07:56:28.57#ibcon#flushed, iclass 10, count 0 2006.252.07:56:28.57#ibcon#about to write, iclass 10, count 0 2006.252.07:56:28.57#ibcon#wrote, iclass 10, count 0 2006.252.07:56:28.57#ibcon#about to read 3, iclass 10, count 0 2006.252.07:56:28.60#ibcon#read 3, iclass 10, count 0 2006.252.07:56:28.60#ibcon#about to read 4, iclass 10, count 0 2006.252.07:56:28.60#ibcon#read 4, iclass 10, count 0 2006.252.07:56:28.60#ibcon#about to read 5, iclass 10, count 0 2006.252.07:56:28.60#ibcon#read 5, iclass 10, count 0 2006.252.07:56:28.60#ibcon#about to read 6, iclass 10, count 0 2006.252.07:56:28.60#ibcon#read 6, iclass 10, count 0 2006.252.07:56:28.60#ibcon#end of sib2, iclass 10, count 0 2006.252.07:56:28.60#ibcon#*mode == 0, iclass 10, count 0 2006.252.07:56:28.60#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.252.07:56:28.60#ibcon#[26=FRQ=03,672.99\r\n] 2006.252.07:56:28.60#ibcon#*before write, iclass 10, count 0 2006.252.07:56:28.60#ibcon#enter sib2, iclass 10, count 0 2006.252.07:56:28.60#ibcon#flushed, iclass 10, count 0 2006.252.07:56:28.60#ibcon#about to write, iclass 10, count 0 2006.252.07:56:28.60#ibcon#wrote, iclass 10, count 0 2006.252.07:56:28.60#ibcon#about to read 3, iclass 10, count 0 2006.252.07:56:28.64#ibcon#read 3, iclass 10, count 0 2006.252.07:56:28.64#ibcon#about to read 4, iclass 10, count 0 2006.252.07:56:28.64#ibcon#read 4, iclass 10, count 0 2006.252.07:56:28.64#ibcon#about to read 5, iclass 10, count 0 2006.252.07:56:28.64#ibcon#read 5, iclass 10, count 0 2006.252.07:56:28.64#ibcon#about to read 6, iclass 10, count 0 2006.252.07:56:28.64#ibcon#read 6, iclass 10, count 0 2006.252.07:56:28.64#ibcon#end of sib2, iclass 10, count 0 2006.252.07:56:28.64#ibcon#*after write, iclass 10, count 0 2006.252.07:56:28.64#ibcon#*before return 0, iclass 10, count 0 2006.252.07:56:28.64#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.252.07:56:28.64#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.252.07:56:28.64#ibcon#about to clear, iclass 10 cls_cnt 0 2006.252.07:56:28.64#ibcon#cleared, iclass 10 cls_cnt 0 2006.252.07:56:28.64$vc4f8/va=3,6 2006.252.07:56:28.64#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.252.07:56:28.64#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.252.07:56:28.64#ibcon#ireg 11 cls_cnt 2 2006.252.07:56:28.64#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.252.07:56:28.69#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.252.07:56:28.69#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.252.07:56:28.69#ibcon#enter wrdev, iclass 12, count 2 2006.252.07:56:28.69#ibcon#first serial, iclass 12, count 2 2006.252.07:56:28.69#ibcon#enter sib2, iclass 12, count 2 2006.252.07:56:28.69#ibcon#flushed, iclass 12, count 2 2006.252.07:56:28.69#ibcon#about to write, iclass 12, count 2 2006.252.07:56:28.69#ibcon#wrote, iclass 12, count 2 2006.252.07:56:28.69#ibcon#about to read 3, iclass 12, count 2 2006.252.07:56:28.71#ibcon#read 3, iclass 12, count 2 2006.252.07:56:28.71#ibcon#about to read 4, iclass 12, count 2 2006.252.07:56:28.71#ibcon#read 4, iclass 12, count 2 2006.252.07:56:28.71#ibcon#about to read 5, iclass 12, count 2 2006.252.07:56:28.71#ibcon#read 5, iclass 12, count 2 2006.252.07:56:28.71#ibcon#about to read 6, iclass 12, count 2 2006.252.07:56:28.71#ibcon#read 6, iclass 12, count 2 2006.252.07:56:28.71#ibcon#end of sib2, iclass 12, count 2 2006.252.07:56:28.71#ibcon#*mode == 0, iclass 12, count 2 2006.252.07:56:28.71#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.252.07:56:28.71#ibcon#[25=AT03-06\r\n] 2006.252.07:56:28.71#ibcon#*before write, iclass 12, count 2 2006.252.07:56:28.71#ibcon#enter sib2, iclass 12, count 2 2006.252.07:56:28.71#ibcon#flushed, iclass 12, count 2 2006.252.07:56:28.71#ibcon#about to write, iclass 12, count 2 2006.252.07:56:28.71#ibcon#wrote, iclass 12, count 2 2006.252.07:56:28.71#ibcon#about to read 3, iclass 12, count 2 2006.252.07:56:28.74#ibcon#read 3, iclass 12, count 2 2006.252.07:56:28.74#ibcon#about to read 4, iclass 12, count 2 2006.252.07:56:28.74#ibcon#read 4, iclass 12, count 2 2006.252.07:56:28.74#ibcon#about to read 5, iclass 12, count 2 2006.252.07:56:28.74#ibcon#read 5, iclass 12, count 2 2006.252.07:56:28.74#ibcon#about to read 6, iclass 12, count 2 2006.252.07:56:28.74#ibcon#read 6, iclass 12, count 2 2006.252.07:56:28.74#ibcon#end of sib2, iclass 12, count 2 2006.252.07:56:28.74#ibcon#*after write, iclass 12, count 2 2006.252.07:56:28.74#ibcon#*before return 0, iclass 12, count 2 2006.252.07:56:28.74#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.252.07:56:28.74#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.252.07:56:28.74#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.252.07:56:28.74#ibcon#ireg 7 cls_cnt 0 2006.252.07:56:28.74#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.252.07:56:28.86#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.252.07:56:28.86#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.252.07:56:28.86#ibcon#enter wrdev, iclass 12, count 0 2006.252.07:56:28.86#ibcon#first serial, iclass 12, count 0 2006.252.07:56:28.86#ibcon#enter sib2, iclass 12, count 0 2006.252.07:56:28.86#ibcon#flushed, iclass 12, count 0 2006.252.07:56:28.86#ibcon#about to write, iclass 12, count 0 2006.252.07:56:28.86#ibcon#wrote, iclass 12, count 0 2006.252.07:56:28.86#ibcon#about to read 3, iclass 12, count 0 2006.252.07:56:28.88#ibcon#read 3, iclass 12, count 0 2006.252.07:56:28.88#ibcon#about to read 4, iclass 12, count 0 2006.252.07:56:28.88#ibcon#read 4, iclass 12, count 0 2006.252.07:56:28.88#ibcon#about to read 5, iclass 12, count 0 2006.252.07:56:28.88#ibcon#read 5, iclass 12, count 0 2006.252.07:56:28.88#ibcon#about to read 6, iclass 12, count 0 2006.252.07:56:28.88#ibcon#read 6, iclass 12, count 0 2006.252.07:56:28.88#ibcon#end of sib2, iclass 12, count 0 2006.252.07:56:28.88#ibcon#*mode == 0, iclass 12, count 0 2006.252.07:56:28.88#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.252.07:56:28.88#ibcon#[25=USB\r\n] 2006.252.07:56:28.88#ibcon#*before write, iclass 12, count 0 2006.252.07:56:28.88#ibcon#enter sib2, iclass 12, count 0 2006.252.07:56:28.88#ibcon#flushed, iclass 12, count 0 2006.252.07:56:28.88#ibcon#about to write, iclass 12, count 0 2006.252.07:56:28.88#ibcon#wrote, iclass 12, count 0 2006.252.07:56:28.88#ibcon#about to read 3, iclass 12, count 0 2006.252.07:56:28.91#ibcon#read 3, iclass 12, count 0 2006.252.07:56:28.91#ibcon#about to read 4, iclass 12, count 0 2006.252.07:56:28.91#ibcon#read 4, iclass 12, count 0 2006.252.07:56:28.91#ibcon#about to read 5, iclass 12, count 0 2006.252.07:56:28.91#ibcon#read 5, iclass 12, count 0 2006.252.07:56:28.91#ibcon#about to read 6, iclass 12, count 0 2006.252.07:56:28.91#ibcon#read 6, iclass 12, count 0 2006.252.07:56:28.91#ibcon#end of sib2, iclass 12, count 0 2006.252.07:56:28.91#ibcon#*after write, iclass 12, count 0 2006.252.07:56:28.91#ibcon#*before return 0, iclass 12, count 0 2006.252.07:56:28.91#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.252.07:56:28.91#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.252.07:56:28.91#ibcon#about to clear, iclass 12 cls_cnt 0 2006.252.07:56:28.91#ibcon#cleared, iclass 12 cls_cnt 0 2006.252.07:56:28.91$vc4f8/valo=4,832.99 2006.252.07:56:28.91#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.252.07:56:28.91#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.252.07:56:28.91#ibcon#ireg 17 cls_cnt 0 2006.252.07:56:28.91#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.252.07:56:28.91#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.252.07:56:28.91#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.252.07:56:28.91#ibcon#enter wrdev, iclass 14, count 0 2006.252.07:56:28.91#ibcon#first serial, iclass 14, count 0 2006.252.07:56:28.91#ibcon#enter sib2, iclass 14, count 0 2006.252.07:56:28.91#ibcon#flushed, iclass 14, count 0 2006.252.07:56:28.91#ibcon#about to write, iclass 14, count 0 2006.252.07:56:28.91#ibcon#wrote, iclass 14, count 0 2006.252.07:56:28.91#ibcon#about to read 3, iclass 14, count 0 2006.252.07:56:28.93#ibcon#read 3, iclass 14, count 0 2006.252.07:56:28.93#ibcon#about to read 4, iclass 14, count 0 2006.252.07:56:28.93#ibcon#read 4, iclass 14, count 0 2006.252.07:56:28.93#ibcon#about to read 5, iclass 14, count 0 2006.252.07:56:28.93#ibcon#read 5, iclass 14, count 0 2006.252.07:56:28.93#ibcon#about to read 6, iclass 14, count 0 2006.252.07:56:28.93#ibcon#read 6, iclass 14, count 0 2006.252.07:56:28.93#ibcon#end of sib2, iclass 14, count 0 2006.252.07:56:28.93#ibcon#*mode == 0, iclass 14, count 0 2006.252.07:56:28.93#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.252.07:56:28.93#ibcon#[26=FRQ=04,832.99\r\n] 2006.252.07:56:28.93#ibcon#*before write, iclass 14, count 0 2006.252.07:56:28.93#ibcon#enter sib2, iclass 14, count 0 2006.252.07:56:28.93#ibcon#flushed, iclass 14, count 0 2006.252.07:56:28.93#ibcon#about to write, iclass 14, count 0 2006.252.07:56:28.93#ibcon#wrote, iclass 14, count 0 2006.252.07:56:28.93#ibcon#about to read 3, iclass 14, count 0 2006.252.07:56:28.97#ibcon#read 3, iclass 14, count 0 2006.252.07:56:28.97#ibcon#about to read 4, iclass 14, count 0 2006.252.07:56:28.97#ibcon#read 4, iclass 14, count 0 2006.252.07:56:28.97#ibcon#about to read 5, iclass 14, count 0 2006.252.07:56:28.97#ibcon#read 5, iclass 14, count 0 2006.252.07:56:28.97#ibcon#about to read 6, iclass 14, count 0 2006.252.07:56:28.97#ibcon#read 6, iclass 14, count 0 2006.252.07:56:28.97#ibcon#end of sib2, iclass 14, count 0 2006.252.07:56:28.97#ibcon#*after write, iclass 14, count 0 2006.252.07:56:28.97#ibcon#*before return 0, iclass 14, count 0 2006.252.07:56:28.97#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.252.07:56:28.97#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.252.07:56:28.97#ibcon#about to clear, iclass 14 cls_cnt 0 2006.252.07:56:28.97#ibcon#cleared, iclass 14 cls_cnt 0 2006.252.07:56:28.97$vc4f8/va=4,7 2006.252.07:56:28.97#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.252.07:56:28.97#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.252.07:56:28.97#ibcon#ireg 11 cls_cnt 2 2006.252.07:56:28.97#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.252.07:56:29.03#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.252.07:56:29.03#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.252.07:56:29.03#ibcon#enter wrdev, iclass 16, count 2 2006.252.07:56:29.03#ibcon#first serial, iclass 16, count 2 2006.252.07:56:29.03#ibcon#enter sib2, iclass 16, count 2 2006.252.07:56:29.03#ibcon#flushed, iclass 16, count 2 2006.252.07:56:29.03#ibcon#about to write, iclass 16, count 2 2006.252.07:56:29.03#ibcon#wrote, iclass 16, count 2 2006.252.07:56:29.03#ibcon#about to read 3, iclass 16, count 2 2006.252.07:56:29.05#ibcon#read 3, iclass 16, count 2 2006.252.07:56:29.05#ibcon#about to read 4, iclass 16, count 2 2006.252.07:56:29.05#ibcon#read 4, iclass 16, count 2 2006.252.07:56:29.05#ibcon#about to read 5, iclass 16, count 2 2006.252.07:56:29.05#ibcon#read 5, iclass 16, count 2 2006.252.07:56:29.05#ibcon#about to read 6, iclass 16, count 2 2006.252.07:56:29.05#ibcon#read 6, iclass 16, count 2 2006.252.07:56:29.05#ibcon#end of sib2, iclass 16, count 2 2006.252.07:56:29.05#ibcon#*mode == 0, iclass 16, count 2 2006.252.07:56:29.05#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.252.07:56:29.05#ibcon#[25=AT04-07\r\n] 2006.252.07:56:29.05#ibcon#*before write, iclass 16, count 2 2006.252.07:56:29.05#ibcon#enter sib2, iclass 16, count 2 2006.252.07:56:29.05#ibcon#flushed, iclass 16, count 2 2006.252.07:56:29.05#ibcon#about to write, iclass 16, count 2 2006.252.07:56:29.05#ibcon#wrote, iclass 16, count 2 2006.252.07:56:29.05#ibcon#about to read 3, iclass 16, count 2 2006.252.07:56:29.08#ibcon#read 3, iclass 16, count 2 2006.252.07:56:29.08#ibcon#about to read 4, iclass 16, count 2 2006.252.07:56:29.08#ibcon#read 4, iclass 16, count 2 2006.252.07:56:29.08#ibcon#about to read 5, iclass 16, count 2 2006.252.07:56:29.08#ibcon#read 5, iclass 16, count 2 2006.252.07:56:29.08#ibcon#about to read 6, iclass 16, count 2 2006.252.07:56:29.08#ibcon#read 6, iclass 16, count 2 2006.252.07:56:29.08#ibcon#end of sib2, iclass 16, count 2 2006.252.07:56:29.08#ibcon#*after write, iclass 16, count 2 2006.252.07:56:29.08#ibcon#*before return 0, iclass 16, count 2 2006.252.07:56:29.08#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.252.07:56:29.08#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.252.07:56:29.08#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.252.07:56:29.08#ibcon#ireg 7 cls_cnt 0 2006.252.07:56:29.08#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.252.07:56:29.20#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.252.07:56:29.20#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.252.07:56:29.20#ibcon#enter wrdev, iclass 16, count 0 2006.252.07:56:29.20#ibcon#first serial, iclass 16, count 0 2006.252.07:56:29.20#ibcon#enter sib2, iclass 16, count 0 2006.252.07:56:29.20#ibcon#flushed, iclass 16, count 0 2006.252.07:56:29.20#ibcon#about to write, iclass 16, count 0 2006.252.07:56:29.20#ibcon#wrote, iclass 16, count 0 2006.252.07:56:29.20#ibcon#about to read 3, iclass 16, count 0 2006.252.07:56:29.22#ibcon#read 3, iclass 16, count 0 2006.252.07:56:29.22#ibcon#about to read 4, iclass 16, count 0 2006.252.07:56:29.22#ibcon#read 4, iclass 16, count 0 2006.252.07:56:29.22#ibcon#about to read 5, iclass 16, count 0 2006.252.07:56:29.22#ibcon#read 5, iclass 16, count 0 2006.252.07:56:29.22#ibcon#about to read 6, iclass 16, count 0 2006.252.07:56:29.22#ibcon#read 6, iclass 16, count 0 2006.252.07:56:29.22#ibcon#end of sib2, iclass 16, count 0 2006.252.07:56:29.22#ibcon#*mode == 0, iclass 16, count 0 2006.252.07:56:29.22#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.252.07:56:29.22#ibcon#[25=USB\r\n] 2006.252.07:56:29.22#ibcon#*before write, iclass 16, count 0 2006.252.07:56:29.22#ibcon#enter sib2, iclass 16, count 0 2006.252.07:56:29.22#ibcon#flushed, iclass 16, count 0 2006.252.07:56:29.22#ibcon#about to write, iclass 16, count 0 2006.252.07:56:29.22#ibcon#wrote, iclass 16, count 0 2006.252.07:56:29.22#ibcon#about to read 3, iclass 16, count 0 2006.252.07:56:29.25#ibcon#read 3, iclass 16, count 0 2006.252.07:56:29.25#ibcon#about to read 4, iclass 16, count 0 2006.252.07:56:29.25#ibcon#read 4, iclass 16, count 0 2006.252.07:56:29.25#ibcon#about to read 5, iclass 16, count 0 2006.252.07:56:29.25#ibcon#read 5, iclass 16, count 0 2006.252.07:56:29.25#ibcon#about to read 6, iclass 16, count 0 2006.252.07:56:29.25#ibcon#read 6, iclass 16, count 0 2006.252.07:56:29.25#ibcon#end of sib2, iclass 16, count 0 2006.252.07:56:29.25#ibcon#*after write, iclass 16, count 0 2006.252.07:56:29.25#ibcon#*before return 0, iclass 16, count 0 2006.252.07:56:29.25#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.252.07:56:29.25#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.252.07:56:29.25#ibcon#about to clear, iclass 16 cls_cnt 0 2006.252.07:56:29.25#ibcon#cleared, iclass 16 cls_cnt 0 2006.252.07:56:29.25$vc4f8/valo=5,652.99 2006.252.07:56:29.25#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.252.07:56:29.25#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.252.07:56:29.25#ibcon#ireg 17 cls_cnt 0 2006.252.07:56:29.25#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.252.07:56:29.25#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.252.07:56:29.25#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.252.07:56:29.25#ibcon#enter wrdev, iclass 18, count 0 2006.252.07:56:29.25#ibcon#first serial, iclass 18, count 0 2006.252.07:56:29.25#ibcon#enter sib2, iclass 18, count 0 2006.252.07:56:29.25#ibcon#flushed, iclass 18, count 0 2006.252.07:56:29.25#ibcon#about to write, iclass 18, count 0 2006.252.07:56:29.25#ibcon#wrote, iclass 18, count 0 2006.252.07:56:29.25#ibcon#about to read 3, iclass 18, count 0 2006.252.07:56:29.27#ibcon#read 3, iclass 18, count 0 2006.252.07:56:29.27#ibcon#about to read 4, iclass 18, count 0 2006.252.07:56:29.27#ibcon#read 4, iclass 18, count 0 2006.252.07:56:29.27#ibcon#about to read 5, iclass 18, count 0 2006.252.07:56:29.27#ibcon#read 5, iclass 18, count 0 2006.252.07:56:29.27#ibcon#about to read 6, iclass 18, count 0 2006.252.07:56:29.27#ibcon#read 6, iclass 18, count 0 2006.252.07:56:29.27#ibcon#end of sib2, iclass 18, count 0 2006.252.07:56:29.27#ibcon#*mode == 0, iclass 18, count 0 2006.252.07:56:29.27#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.252.07:56:29.27#ibcon#[26=FRQ=05,652.99\r\n] 2006.252.07:56:29.27#ibcon#*before write, iclass 18, count 0 2006.252.07:56:29.27#ibcon#enter sib2, iclass 18, count 0 2006.252.07:56:29.27#ibcon#flushed, iclass 18, count 0 2006.252.07:56:29.27#ibcon#about to write, iclass 18, count 0 2006.252.07:56:29.27#ibcon#wrote, iclass 18, count 0 2006.252.07:56:29.27#ibcon#about to read 3, iclass 18, count 0 2006.252.07:56:29.31#ibcon#read 3, iclass 18, count 0 2006.252.07:56:29.31#ibcon#about to read 4, iclass 18, count 0 2006.252.07:56:29.31#ibcon#read 4, iclass 18, count 0 2006.252.07:56:29.31#ibcon#about to read 5, iclass 18, count 0 2006.252.07:56:29.31#ibcon#read 5, iclass 18, count 0 2006.252.07:56:29.31#ibcon#about to read 6, iclass 18, count 0 2006.252.07:56:29.31#ibcon#read 6, iclass 18, count 0 2006.252.07:56:29.31#ibcon#end of sib2, iclass 18, count 0 2006.252.07:56:29.31#ibcon#*after write, iclass 18, count 0 2006.252.07:56:29.31#ibcon#*before return 0, iclass 18, count 0 2006.252.07:56:29.31#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.252.07:56:29.31#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.252.07:56:29.31#ibcon#about to clear, iclass 18 cls_cnt 0 2006.252.07:56:29.31#ibcon#cleared, iclass 18 cls_cnt 0 2006.252.07:56:29.31$vc4f8/va=5,7 2006.252.07:56:29.31#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.252.07:56:29.31#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.252.07:56:29.31#ibcon#ireg 11 cls_cnt 2 2006.252.07:56:29.31#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.252.07:56:29.37#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.252.07:56:29.37#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.252.07:56:29.37#ibcon#enter wrdev, iclass 20, count 2 2006.252.07:56:29.37#ibcon#first serial, iclass 20, count 2 2006.252.07:56:29.37#ibcon#enter sib2, iclass 20, count 2 2006.252.07:56:29.37#ibcon#flushed, iclass 20, count 2 2006.252.07:56:29.37#ibcon#about to write, iclass 20, count 2 2006.252.07:56:29.37#ibcon#wrote, iclass 20, count 2 2006.252.07:56:29.37#ibcon#about to read 3, iclass 20, count 2 2006.252.07:56:29.39#ibcon#read 3, iclass 20, count 2 2006.252.07:56:29.39#ibcon#about to read 4, iclass 20, count 2 2006.252.07:56:29.39#ibcon#read 4, iclass 20, count 2 2006.252.07:56:29.39#ibcon#about to read 5, iclass 20, count 2 2006.252.07:56:29.39#ibcon#read 5, iclass 20, count 2 2006.252.07:56:29.39#ibcon#about to read 6, iclass 20, count 2 2006.252.07:56:29.39#ibcon#read 6, iclass 20, count 2 2006.252.07:56:29.39#ibcon#end of sib2, iclass 20, count 2 2006.252.07:56:29.39#ibcon#*mode == 0, iclass 20, count 2 2006.252.07:56:29.39#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.252.07:56:29.39#ibcon#[25=AT05-07\r\n] 2006.252.07:56:29.39#ibcon#*before write, iclass 20, count 2 2006.252.07:56:29.39#ibcon#enter sib2, iclass 20, count 2 2006.252.07:56:29.39#ibcon#flushed, iclass 20, count 2 2006.252.07:56:29.39#ibcon#about to write, iclass 20, count 2 2006.252.07:56:29.39#ibcon#wrote, iclass 20, count 2 2006.252.07:56:29.39#ibcon#about to read 3, iclass 20, count 2 2006.252.07:56:29.42#ibcon#read 3, iclass 20, count 2 2006.252.07:56:29.42#ibcon#about to read 4, iclass 20, count 2 2006.252.07:56:29.42#ibcon#read 4, iclass 20, count 2 2006.252.07:56:29.42#ibcon#about to read 5, iclass 20, count 2 2006.252.07:56:29.42#ibcon#read 5, iclass 20, count 2 2006.252.07:56:29.42#ibcon#about to read 6, iclass 20, count 2 2006.252.07:56:29.42#ibcon#read 6, iclass 20, count 2 2006.252.07:56:29.42#ibcon#end of sib2, iclass 20, count 2 2006.252.07:56:29.42#ibcon#*after write, iclass 20, count 2 2006.252.07:56:29.42#ibcon#*before return 0, iclass 20, count 2 2006.252.07:56:29.42#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.252.07:56:29.42#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.252.07:56:29.42#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.252.07:56:29.42#ibcon#ireg 7 cls_cnt 0 2006.252.07:56:29.42#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.252.07:56:29.54#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.252.07:56:29.54#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.252.07:56:29.54#ibcon#enter wrdev, iclass 20, count 0 2006.252.07:56:29.54#ibcon#first serial, iclass 20, count 0 2006.252.07:56:29.54#ibcon#enter sib2, iclass 20, count 0 2006.252.07:56:29.54#ibcon#flushed, iclass 20, count 0 2006.252.07:56:29.54#ibcon#about to write, iclass 20, count 0 2006.252.07:56:29.54#ibcon#wrote, iclass 20, count 0 2006.252.07:56:29.54#ibcon#about to read 3, iclass 20, count 0 2006.252.07:56:29.56#ibcon#read 3, iclass 20, count 0 2006.252.07:56:29.56#ibcon#about to read 4, iclass 20, count 0 2006.252.07:56:29.56#ibcon#read 4, iclass 20, count 0 2006.252.07:56:29.56#ibcon#about to read 5, iclass 20, count 0 2006.252.07:56:29.56#ibcon#read 5, iclass 20, count 0 2006.252.07:56:29.56#ibcon#about to read 6, iclass 20, count 0 2006.252.07:56:29.56#ibcon#read 6, iclass 20, count 0 2006.252.07:56:29.56#ibcon#end of sib2, iclass 20, count 0 2006.252.07:56:29.56#ibcon#*mode == 0, iclass 20, count 0 2006.252.07:56:29.56#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.252.07:56:29.56#ibcon#[25=USB\r\n] 2006.252.07:56:29.56#ibcon#*before write, iclass 20, count 0 2006.252.07:56:29.56#ibcon#enter sib2, iclass 20, count 0 2006.252.07:56:29.56#ibcon#flushed, iclass 20, count 0 2006.252.07:56:29.56#ibcon#about to write, iclass 20, count 0 2006.252.07:56:29.56#ibcon#wrote, iclass 20, count 0 2006.252.07:56:29.56#ibcon#about to read 3, iclass 20, count 0 2006.252.07:56:29.59#ibcon#read 3, iclass 20, count 0 2006.252.07:56:29.59#ibcon#about to read 4, iclass 20, count 0 2006.252.07:56:29.59#ibcon#read 4, iclass 20, count 0 2006.252.07:56:29.59#ibcon#about to read 5, iclass 20, count 0 2006.252.07:56:29.59#ibcon#read 5, iclass 20, count 0 2006.252.07:56:29.59#ibcon#about to read 6, iclass 20, count 0 2006.252.07:56:29.59#ibcon#read 6, iclass 20, count 0 2006.252.07:56:29.59#ibcon#end of sib2, iclass 20, count 0 2006.252.07:56:29.59#ibcon#*after write, iclass 20, count 0 2006.252.07:56:29.59#ibcon#*before return 0, iclass 20, count 0 2006.252.07:56:29.59#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.252.07:56:29.59#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.252.07:56:29.59#ibcon#about to clear, iclass 20 cls_cnt 0 2006.252.07:56:29.59#ibcon#cleared, iclass 20 cls_cnt 0 2006.252.07:56:29.59$vc4f8/valo=6,772.99 2006.252.07:56:29.59#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.252.07:56:29.59#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.252.07:56:29.59#ibcon#ireg 17 cls_cnt 0 2006.252.07:56:29.59#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.252.07:56:29.59#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.252.07:56:29.59#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.252.07:56:29.59#ibcon#enter wrdev, iclass 22, count 0 2006.252.07:56:29.59#ibcon#first serial, iclass 22, count 0 2006.252.07:56:29.59#ibcon#enter sib2, iclass 22, count 0 2006.252.07:56:29.59#ibcon#flushed, iclass 22, count 0 2006.252.07:56:29.59#ibcon#about to write, iclass 22, count 0 2006.252.07:56:29.59#ibcon#wrote, iclass 22, count 0 2006.252.07:56:29.59#ibcon#about to read 3, iclass 22, count 0 2006.252.07:56:29.61#ibcon#read 3, iclass 22, count 0 2006.252.07:56:29.61#ibcon#about to read 4, iclass 22, count 0 2006.252.07:56:29.61#ibcon#read 4, iclass 22, count 0 2006.252.07:56:29.61#ibcon#about to read 5, iclass 22, count 0 2006.252.07:56:29.61#ibcon#read 5, iclass 22, count 0 2006.252.07:56:29.61#ibcon#about to read 6, iclass 22, count 0 2006.252.07:56:29.61#ibcon#read 6, iclass 22, count 0 2006.252.07:56:29.61#ibcon#end of sib2, iclass 22, count 0 2006.252.07:56:29.61#ibcon#*mode == 0, iclass 22, count 0 2006.252.07:56:29.61#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.252.07:56:29.61#ibcon#[26=FRQ=06,772.99\r\n] 2006.252.07:56:29.61#ibcon#*before write, iclass 22, count 0 2006.252.07:56:29.61#ibcon#enter sib2, iclass 22, count 0 2006.252.07:56:29.61#ibcon#flushed, iclass 22, count 0 2006.252.07:56:29.61#ibcon#about to write, iclass 22, count 0 2006.252.07:56:29.61#ibcon#wrote, iclass 22, count 0 2006.252.07:56:29.61#ibcon#about to read 3, iclass 22, count 0 2006.252.07:56:29.65#ibcon#read 3, iclass 22, count 0 2006.252.07:56:29.65#ibcon#about to read 4, iclass 22, count 0 2006.252.07:56:29.65#ibcon#read 4, iclass 22, count 0 2006.252.07:56:29.65#ibcon#about to read 5, iclass 22, count 0 2006.252.07:56:29.65#ibcon#read 5, iclass 22, count 0 2006.252.07:56:29.65#ibcon#about to read 6, iclass 22, count 0 2006.252.07:56:29.65#ibcon#read 6, iclass 22, count 0 2006.252.07:56:29.65#ibcon#end of sib2, iclass 22, count 0 2006.252.07:56:29.65#ibcon#*after write, iclass 22, count 0 2006.252.07:56:29.65#ibcon#*before return 0, iclass 22, count 0 2006.252.07:56:29.65#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.252.07:56:29.65#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.252.07:56:29.65#ibcon#about to clear, iclass 22 cls_cnt 0 2006.252.07:56:29.65#ibcon#cleared, iclass 22 cls_cnt 0 2006.252.07:56:29.65$vc4f8/va=6,7 2006.252.07:56:29.65#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.252.07:56:29.65#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.252.07:56:29.65#ibcon#ireg 11 cls_cnt 2 2006.252.07:56:29.65#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.252.07:56:29.71#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.252.07:56:29.71#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.252.07:56:29.71#ibcon#enter wrdev, iclass 24, count 2 2006.252.07:56:29.71#ibcon#first serial, iclass 24, count 2 2006.252.07:56:29.71#ibcon#enter sib2, iclass 24, count 2 2006.252.07:56:29.71#ibcon#flushed, iclass 24, count 2 2006.252.07:56:29.71#ibcon#about to write, iclass 24, count 2 2006.252.07:56:29.71#ibcon#wrote, iclass 24, count 2 2006.252.07:56:29.71#ibcon#about to read 3, iclass 24, count 2 2006.252.07:56:29.73#ibcon#read 3, iclass 24, count 2 2006.252.07:56:29.73#ibcon#about to read 4, iclass 24, count 2 2006.252.07:56:29.73#ibcon#read 4, iclass 24, count 2 2006.252.07:56:29.73#ibcon#about to read 5, iclass 24, count 2 2006.252.07:56:29.73#ibcon#read 5, iclass 24, count 2 2006.252.07:56:29.73#ibcon#about to read 6, iclass 24, count 2 2006.252.07:56:29.73#ibcon#read 6, iclass 24, count 2 2006.252.07:56:29.73#ibcon#end of sib2, iclass 24, count 2 2006.252.07:56:29.73#ibcon#*mode == 0, iclass 24, count 2 2006.252.07:56:29.73#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.252.07:56:29.73#ibcon#[25=AT06-07\r\n] 2006.252.07:56:29.73#ibcon#*before write, iclass 24, count 2 2006.252.07:56:29.73#ibcon#enter sib2, iclass 24, count 2 2006.252.07:56:29.73#ibcon#flushed, iclass 24, count 2 2006.252.07:56:29.73#ibcon#about to write, iclass 24, count 2 2006.252.07:56:29.73#ibcon#wrote, iclass 24, count 2 2006.252.07:56:29.73#ibcon#about to read 3, iclass 24, count 2 2006.252.07:56:29.76#ibcon#read 3, iclass 24, count 2 2006.252.07:56:29.76#ibcon#about to read 4, iclass 24, count 2 2006.252.07:56:29.76#ibcon#read 4, iclass 24, count 2 2006.252.07:56:29.76#ibcon#about to read 5, iclass 24, count 2 2006.252.07:56:29.76#ibcon#read 5, iclass 24, count 2 2006.252.07:56:29.76#ibcon#about to read 6, iclass 24, count 2 2006.252.07:56:29.76#ibcon#read 6, iclass 24, count 2 2006.252.07:56:29.76#ibcon#end of sib2, iclass 24, count 2 2006.252.07:56:29.76#ibcon#*after write, iclass 24, count 2 2006.252.07:56:29.76#ibcon#*before return 0, iclass 24, count 2 2006.252.07:56:29.76#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.252.07:56:29.76#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.252.07:56:29.76#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.252.07:56:29.76#ibcon#ireg 7 cls_cnt 0 2006.252.07:56:29.76#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.252.07:56:29.88#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.252.07:56:29.88#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.252.07:56:29.88#ibcon#enter wrdev, iclass 24, count 0 2006.252.07:56:29.88#ibcon#first serial, iclass 24, count 0 2006.252.07:56:29.88#ibcon#enter sib2, iclass 24, count 0 2006.252.07:56:29.88#ibcon#flushed, iclass 24, count 0 2006.252.07:56:29.88#ibcon#about to write, iclass 24, count 0 2006.252.07:56:29.88#ibcon#wrote, iclass 24, count 0 2006.252.07:56:29.88#ibcon#about to read 3, iclass 24, count 0 2006.252.07:56:29.90#ibcon#read 3, iclass 24, count 0 2006.252.07:56:29.90#ibcon#about to read 4, iclass 24, count 0 2006.252.07:56:29.90#ibcon#read 4, iclass 24, count 0 2006.252.07:56:29.90#ibcon#about to read 5, iclass 24, count 0 2006.252.07:56:29.90#ibcon#read 5, iclass 24, count 0 2006.252.07:56:29.90#ibcon#about to read 6, iclass 24, count 0 2006.252.07:56:29.90#ibcon#read 6, iclass 24, count 0 2006.252.07:56:29.90#ibcon#end of sib2, iclass 24, count 0 2006.252.07:56:29.90#ibcon#*mode == 0, iclass 24, count 0 2006.252.07:56:29.90#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.252.07:56:29.90#ibcon#[25=USB\r\n] 2006.252.07:56:29.90#ibcon#*before write, iclass 24, count 0 2006.252.07:56:29.90#ibcon#enter sib2, iclass 24, count 0 2006.252.07:56:29.90#ibcon#flushed, iclass 24, count 0 2006.252.07:56:29.90#ibcon#about to write, iclass 24, count 0 2006.252.07:56:29.90#ibcon#wrote, iclass 24, count 0 2006.252.07:56:29.90#ibcon#about to read 3, iclass 24, count 0 2006.252.07:56:29.93#ibcon#read 3, iclass 24, count 0 2006.252.07:56:29.93#ibcon#about to read 4, iclass 24, count 0 2006.252.07:56:29.93#ibcon#read 4, iclass 24, count 0 2006.252.07:56:29.93#ibcon#about to read 5, iclass 24, count 0 2006.252.07:56:29.93#ibcon#read 5, iclass 24, count 0 2006.252.07:56:29.93#ibcon#about to read 6, iclass 24, count 0 2006.252.07:56:29.93#ibcon#read 6, iclass 24, count 0 2006.252.07:56:29.93#ibcon#end of sib2, iclass 24, count 0 2006.252.07:56:29.93#ibcon#*after write, iclass 24, count 0 2006.252.07:56:29.93#ibcon#*before return 0, iclass 24, count 0 2006.252.07:56:29.93#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.252.07:56:29.93#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.252.07:56:29.93#ibcon#about to clear, iclass 24 cls_cnt 0 2006.252.07:56:29.93#ibcon#cleared, iclass 24 cls_cnt 0 2006.252.07:56:29.93$vc4f8/valo=7,832.99 2006.252.07:56:29.93#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.252.07:56:29.93#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.252.07:56:29.93#ibcon#ireg 17 cls_cnt 0 2006.252.07:56:29.93#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.252.07:56:29.93#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.252.07:56:29.93#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.252.07:56:29.93#ibcon#enter wrdev, iclass 26, count 0 2006.252.07:56:29.93#ibcon#first serial, iclass 26, count 0 2006.252.07:56:29.93#ibcon#enter sib2, iclass 26, count 0 2006.252.07:56:29.93#ibcon#flushed, iclass 26, count 0 2006.252.07:56:29.93#ibcon#about to write, iclass 26, count 0 2006.252.07:56:29.93#ibcon#wrote, iclass 26, count 0 2006.252.07:56:29.93#ibcon#about to read 3, iclass 26, count 0 2006.252.07:56:29.95#ibcon#read 3, iclass 26, count 0 2006.252.07:56:29.95#ibcon#about to read 4, iclass 26, count 0 2006.252.07:56:29.95#ibcon#read 4, iclass 26, count 0 2006.252.07:56:29.95#ibcon#about to read 5, iclass 26, count 0 2006.252.07:56:29.95#ibcon#read 5, iclass 26, count 0 2006.252.07:56:29.95#ibcon#about to read 6, iclass 26, count 0 2006.252.07:56:29.95#ibcon#read 6, iclass 26, count 0 2006.252.07:56:29.95#ibcon#end of sib2, iclass 26, count 0 2006.252.07:56:29.95#ibcon#*mode == 0, iclass 26, count 0 2006.252.07:56:29.95#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.252.07:56:29.95#ibcon#[26=FRQ=07,832.99\r\n] 2006.252.07:56:29.95#ibcon#*before write, iclass 26, count 0 2006.252.07:56:29.95#ibcon#enter sib2, iclass 26, count 0 2006.252.07:56:29.95#ibcon#flushed, iclass 26, count 0 2006.252.07:56:29.95#ibcon#about to write, iclass 26, count 0 2006.252.07:56:29.95#ibcon#wrote, iclass 26, count 0 2006.252.07:56:29.95#ibcon#about to read 3, iclass 26, count 0 2006.252.07:56:29.99#ibcon#read 3, iclass 26, count 0 2006.252.07:56:29.99#ibcon#about to read 4, iclass 26, count 0 2006.252.07:56:29.99#ibcon#read 4, iclass 26, count 0 2006.252.07:56:29.99#ibcon#about to read 5, iclass 26, count 0 2006.252.07:56:29.99#ibcon#read 5, iclass 26, count 0 2006.252.07:56:29.99#ibcon#about to read 6, iclass 26, count 0 2006.252.07:56:29.99#ibcon#read 6, iclass 26, count 0 2006.252.07:56:29.99#ibcon#end of sib2, iclass 26, count 0 2006.252.07:56:29.99#ibcon#*after write, iclass 26, count 0 2006.252.07:56:29.99#ibcon#*before return 0, iclass 26, count 0 2006.252.07:56:29.99#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.252.07:56:29.99#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.252.07:56:29.99#ibcon#about to clear, iclass 26 cls_cnt 0 2006.252.07:56:29.99#ibcon#cleared, iclass 26 cls_cnt 0 2006.252.07:56:29.99$vc4f8/va=7,7 2006.252.07:56:29.99#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.252.07:56:29.99#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.252.07:56:29.99#ibcon#ireg 11 cls_cnt 2 2006.252.07:56:29.99#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.252.07:56:30.05#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.252.07:56:30.05#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.252.07:56:30.05#ibcon#enter wrdev, iclass 28, count 2 2006.252.07:56:30.05#ibcon#first serial, iclass 28, count 2 2006.252.07:56:30.05#ibcon#enter sib2, iclass 28, count 2 2006.252.07:56:30.05#ibcon#flushed, iclass 28, count 2 2006.252.07:56:30.05#ibcon#about to write, iclass 28, count 2 2006.252.07:56:30.05#ibcon#wrote, iclass 28, count 2 2006.252.07:56:30.05#ibcon#about to read 3, iclass 28, count 2 2006.252.07:56:30.07#ibcon#read 3, iclass 28, count 2 2006.252.07:56:30.07#ibcon#about to read 4, iclass 28, count 2 2006.252.07:56:30.07#ibcon#read 4, iclass 28, count 2 2006.252.07:56:30.07#ibcon#about to read 5, iclass 28, count 2 2006.252.07:56:30.07#ibcon#read 5, iclass 28, count 2 2006.252.07:56:30.07#ibcon#about to read 6, iclass 28, count 2 2006.252.07:56:30.07#ibcon#read 6, iclass 28, count 2 2006.252.07:56:30.07#ibcon#end of sib2, iclass 28, count 2 2006.252.07:56:30.07#ibcon#*mode == 0, iclass 28, count 2 2006.252.07:56:30.07#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.252.07:56:30.07#ibcon#[25=AT07-07\r\n] 2006.252.07:56:30.07#ibcon#*before write, iclass 28, count 2 2006.252.07:56:30.07#ibcon#enter sib2, iclass 28, count 2 2006.252.07:56:30.07#ibcon#flushed, iclass 28, count 2 2006.252.07:56:30.07#ibcon#about to write, iclass 28, count 2 2006.252.07:56:30.07#ibcon#wrote, iclass 28, count 2 2006.252.07:56:30.07#ibcon#about to read 3, iclass 28, count 2 2006.252.07:56:30.10#ibcon#read 3, iclass 28, count 2 2006.252.07:56:30.10#ibcon#about to read 4, iclass 28, count 2 2006.252.07:56:30.10#ibcon#read 4, iclass 28, count 2 2006.252.07:56:30.10#ibcon#about to read 5, iclass 28, count 2 2006.252.07:56:30.10#ibcon#read 5, iclass 28, count 2 2006.252.07:56:30.10#ibcon#about to read 6, iclass 28, count 2 2006.252.07:56:30.10#ibcon#read 6, iclass 28, count 2 2006.252.07:56:30.10#ibcon#end of sib2, iclass 28, count 2 2006.252.07:56:30.10#ibcon#*after write, iclass 28, count 2 2006.252.07:56:30.10#ibcon#*before return 0, iclass 28, count 2 2006.252.07:56:30.10#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.252.07:56:30.10#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.252.07:56:30.10#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.252.07:56:30.10#ibcon#ireg 7 cls_cnt 0 2006.252.07:56:30.10#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.252.07:56:30.22#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.252.07:56:30.22#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.252.07:56:30.22#ibcon#enter wrdev, iclass 28, count 0 2006.252.07:56:30.22#ibcon#first serial, iclass 28, count 0 2006.252.07:56:30.22#ibcon#enter sib2, iclass 28, count 0 2006.252.07:56:30.22#ibcon#flushed, iclass 28, count 0 2006.252.07:56:30.22#ibcon#about to write, iclass 28, count 0 2006.252.07:56:30.22#ibcon#wrote, iclass 28, count 0 2006.252.07:56:30.22#ibcon#about to read 3, iclass 28, count 0 2006.252.07:56:30.24#ibcon#read 3, iclass 28, count 0 2006.252.07:56:30.24#ibcon#about to read 4, iclass 28, count 0 2006.252.07:56:30.24#ibcon#read 4, iclass 28, count 0 2006.252.07:56:30.24#ibcon#about to read 5, iclass 28, count 0 2006.252.07:56:30.24#ibcon#read 5, iclass 28, count 0 2006.252.07:56:30.24#ibcon#about to read 6, iclass 28, count 0 2006.252.07:56:30.24#ibcon#read 6, iclass 28, count 0 2006.252.07:56:30.24#ibcon#end of sib2, iclass 28, count 0 2006.252.07:56:30.24#ibcon#*mode == 0, iclass 28, count 0 2006.252.07:56:30.24#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.252.07:56:30.24#ibcon#[25=USB\r\n] 2006.252.07:56:30.24#ibcon#*before write, iclass 28, count 0 2006.252.07:56:30.24#ibcon#enter sib2, iclass 28, count 0 2006.252.07:56:30.24#ibcon#flushed, iclass 28, count 0 2006.252.07:56:30.24#ibcon#about to write, iclass 28, count 0 2006.252.07:56:30.24#ibcon#wrote, iclass 28, count 0 2006.252.07:56:30.24#ibcon#about to read 3, iclass 28, count 0 2006.252.07:56:30.27#ibcon#read 3, iclass 28, count 0 2006.252.07:56:30.27#ibcon#about to read 4, iclass 28, count 0 2006.252.07:56:30.27#ibcon#read 4, iclass 28, count 0 2006.252.07:56:30.27#ibcon#about to read 5, iclass 28, count 0 2006.252.07:56:30.27#ibcon#read 5, iclass 28, count 0 2006.252.07:56:30.27#ibcon#about to read 6, iclass 28, count 0 2006.252.07:56:30.27#ibcon#read 6, iclass 28, count 0 2006.252.07:56:30.27#ibcon#end of sib2, iclass 28, count 0 2006.252.07:56:30.27#ibcon#*after write, iclass 28, count 0 2006.252.07:56:30.27#ibcon#*before return 0, iclass 28, count 0 2006.252.07:56:30.27#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.252.07:56:30.27#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.252.07:56:30.27#ibcon#about to clear, iclass 28 cls_cnt 0 2006.252.07:56:30.27#ibcon#cleared, iclass 28 cls_cnt 0 2006.252.07:56:30.27$vc4f8/valo=8,852.99 2006.252.07:56:30.27#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.252.07:56:30.27#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.252.07:56:30.27#ibcon#ireg 17 cls_cnt 0 2006.252.07:56:30.27#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.252.07:56:30.27#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.252.07:56:30.27#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.252.07:56:30.27#ibcon#enter wrdev, iclass 30, count 0 2006.252.07:56:30.27#ibcon#first serial, iclass 30, count 0 2006.252.07:56:30.27#ibcon#enter sib2, iclass 30, count 0 2006.252.07:56:30.27#ibcon#flushed, iclass 30, count 0 2006.252.07:56:30.27#ibcon#about to write, iclass 30, count 0 2006.252.07:56:30.27#ibcon#wrote, iclass 30, count 0 2006.252.07:56:30.27#ibcon#about to read 3, iclass 30, count 0 2006.252.07:56:30.29#ibcon#read 3, iclass 30, count 0 2006.252.07:56:30.29#ibcon#about to read 4, iclass 30, count 0 2006.252.07:56:30.29#ibcon#read 4, iclass 30, count 0 2006.252.07:56:30.29#ibcon#about to read 5, iclass 30, count 0 2006.252.07:56:30.29#ibcon#read 5, iclass 30, count 0 2006.252.07:56:30.29#ibcon#about to read 6, iclass 30, count 0 2006.252.07:56:30.29#ibcon#read 6, iclass 30, count 0 2006.252.07:56:30.29#ibcon#end of sib2, iclass 30, count 0 2006.252.07:56:30.29#ibcon#*mode == 0, iclass 30, count 0 2006.252.07:56:30.29#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.252.07:56:30.29#ibcon#[26=FRQ=08,852.99\r\n] 2006.252.07:56:30.29#ibcon#*before write, iclass 30, count 0 2006.252.07:56:30.29#ibcon#enter sib2, iclass 30, count 0 2006.252.07:56:30.29#ibcon#flushed, iclass 30, count 0 2006.252.07:56:30.29#ibcon#about to write, iclass 30, count 0 2006.252.07:56:30.29#ibcon#wrote, iclass 30, count 0 2006.252.07:56:30.29#ibcon#about to read 3, iclass 30, count 0 2006.252.07:56:30.33#ibcon#read 3, iclass 30, count 0 2006.252.07:56:30.33#ibcon#about to read 4, iclass 30, count 0 2006.252.07:56:30.33#ibcon#read 4, iclass 30, count 0 2006.252.07:56:30.33#ibcon#about to read 5, iclass 30, count 0 2006.252.07:56:30.33#ibcon#read 5, iclass 30, count 0 2006.252.07:56:30.33#ibcon#about to read 6, iclass 30, count 0 2006.252.07:56:30.33#ibcon#read 6, iclass 30, count 0 2006.252.07:56:30.33#ibcon#end of sib2, iclass 30, count 0 2006.252.07:56:30.33#ibcon#*after write, iclass 30, count 0 2006.252.07:56:30.33#ibcon#*before return 0, iclass 30, count 0 2006.252.07:56:30.33#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.252.07:56:30.33#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.252.07:56:30.33#ibcon#about to clear, iclass 30 cls_cnt 0 2006.252.07:56:30.33#ibcon#cleared, iclass 30 cls_cnt 0 2006.252.07:56:30.33$vc4f8/va=8,7 2006.252.07:56:30.33#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.252.07:56:30.33#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.252.07:56:30.33#ibcon#ireg 11 cls_cnt 2 2006.252.07:56:30.33#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.252.07:56:30.39#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.252.07:56:30.39#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.252.07:56:30.39#ibcon#enter wrdev, iclass 32, count 2 2006.252.07:56:30.39#ibcon#first serial, iclass 32, count 2 2006.252.07:56:30.39#ibcon#enter sib2, iclass 32, count 2 2006.252.07:56:30.39#ibcon#flushed, iclass 32, count 2 2006.252.07:56:30.39#ibcon#about to write, iclass 32, count 2 2006.252.07:56:30.39#ibcon#wrote, iclass 32, count 2 2006.252.07:56:30.39#ibcon#about to read 3, iclass 32, count 2 2006.252.07:56:30.41#ibcon#read 3, iclass 32, count 2 2006.252.07:56:30.41#ibcon#about to read 4, iclass 32, count 2 2006.252.07:56:30.41#ibcon#read 4, iclass 32, count 2 2006.252.07:56:30.41#ibcon#about to read 5, iclass 32, count 2 2006.252.07:56:30.41#ibcon#read 5, iclass 32, count 2 2006.252.07:56:30.41#ibcon#about to read 6, iclass 32, count 2 2006.252.07:56:30.41#ibcon#read 6, iclass 32, count 2 2006.252.07:56:30.41#ibcon#end of sib2, iclass 32, count 2 2006.252.07:56:30.41#ibcon#*mode == 0, iclass 32, count 2 2006.252.07:56:30.41#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.252.07:56:30.41#ibcon#[25=AT08-07\r\n] 2006.252.07:56:30.41#ibcon#*before write, iclass 32, count 2 2006.252.07:56:30.41#ibcon#enter sib2, iclass 32, count 2 2006.252.07:56:30.41#ibcon#flushed, iclass 32, count 2 2006.252.07:56:30.41#ibcon#about to write, iclass 32, count 2 2006.252.07:56:30.41#ibcon#wrote, iclass 32, count 2 2006.252.07:56:30.41#ibcon#about to read 3, iclass 32, count 2 2006.252.07:56:30.44#ibcon#read 3, iclass 32, count 2 2006.252.07:56:30.44#ibcon#about to read 4, iclass 32, count 2 2006.252.07:56:30.44#ibcon#read 4, iclass 32, count 2 2006.252.07:56:30.44#ibcon#about to read 5, iclass 32, count 2 2006.252.07:56:30.44#ibcon#read 5, iclass 32, count 2 2006.252.07:56:30.44#ibcon#about to read 6, iclass 32, count 2 2006.252.07:56:30.44#ibcon#read 6, iclass 32, count 2 2006.252.07:56:30.44#ibcon#end of sib2, iclass 32, count 2 2006.252.07:56:30.44#ibcon#*after write, iclass 32, count 2 2006.252.07:56:30.44#ibcon#*before return 0, iclass 32, count 2 2006.252.07:56:30.44#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.252.07:56:30.44#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.252.07:56:30.44#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.252.07:56:30.44#ibcon#ireg 7 cls_cnt 0 2006.252.07:56:30.44#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.252.07:56:30.56#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.252.07:56:30.56#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.252.07:56:30.56#ibcon#enter wrdev, iclass 32, count 0 2006.252.07:56:30.56#ibcon#first serial, iclass 32, count 0 2006.252.07:56:30.56#ibcon#enter sib2, iclass 32, count 0 2006.252.07:56:30.56#ibcon#flushed, iclass 32, count 0 2006.252.07:56:30.56#ibcon#about to write, iclass 32, count 0 2006.252.07:56:30.56#ibcon#wrote, iclass 32, count 0 2006.252.07:56:30.56#ibcon#about to read 3, iclass 32, count 0 2006.252.07:56:30.58#ibcon#read 3, iclass 32, count 0 2006.252.07:56:30.58#ibcon#about to read 4, iclass 32, count 0 2006.252.07:56:30.58#ibcon#read 4, iclass 32, count 0 2006.252.07:56:30.58#ibcon#about to read 5, iclass 32, count 0 2006.252.07:56:30.58#ibcon#read 5, iclass 32, count 0 2006.252.07:56:30.58#ibcon#about to read 6, iclass 32, count 0 2006.252.07:56:30.58#ibcon#read 6, iclass 32, count 0 2006.252.07:56:30.58#ibcon#end of sib2, iclass 32, count 0 2006.252.07:56:30.58#ibcon#*mode == 0, iclass 32, count 0 2006.252.07:56:30.58#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.252.07:56:30.58#ibcon#[25=USB\r\n] 2006.252.07:56:30.58#ibcon#*before write, iclass 32, count 0 2006.252.07:56:30.58#ibcon#enter sib2, iclass 32, count 0 2006.252.07:56:30.58#ibcon#flushed, iclass 32, count 0 2006.252.07:56:30.58#ibcon#about to write, iclass 32, count 0 2006.252.07:56:30.58#ibcon#wrote, iclass 32, count 0 2006.252.07:56:30.58#ibcon#about to read 3, iclass 32, count 0 2006.252.07:56:30.61#ibcon#read 3, iclass 32, count 0 2006.252.07:56:30.61#ibcon#about to read 4, iclass 32, count 0 2006.252.07:56:30.61#ibcon#read 4, iclass 32, count 0 2006.252.07:56:30.61#ibcon#about to read 5, iclass 32, count 0 2006.252.07:56:30.61#ibcon#read 5, iclass 32, count 0 2006.252.07:56:30.61#ibcon#about to read 6, iclass 32, count 0 2006.252.07:56:30.61#ibcon#read 6, iclass 32, count 0 2006.252.07:56:30.61#ibcon#end of sib2, iclass 32, count 0 2006.252.07:56:30.61#ibcon#*after write, iclass 32, count 0 2006.252.07:56:30.61#ibcon#*before return 0, iclass 32, count 0 2006.252.07:56:30.61#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.252.07:56:30.61#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.252.07:56:30.61#ibcon#about to clear, iclass 32 cls_cnt 0 2006.252.07:56:30.61#ibcon#cleared, iclass 32 cls_cnt 0 2006.252.07:56:30.61$vc4f8/vblo=1,632.99 2006.252.07:56:30.61#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.252.07:56:30.61#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.252.07:56:30.61#ibcon#ireg 17 cls_cnt 0 2006.252.07:56:30.61#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.252.07:56:30.61#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.252.07:56:30.61#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.252.07:56:30.61#ibcon#enter wrdev, iclass 34, count 0 2006.252.07:56:30.61#ibcon#first serial, iclass 34, count 0 2006.252.07:56:30.61#ibcon#enter sib2, iclass 34, count 0 2006.252.07:56:30.61#ibcon#flushed, iclass 34, count 0 2006.252.07:56:30.61#ibcon#about to write, iclass 34, count 0 2006.252.07:56:30.61#ibcon#wrote, iclass 34, count 0 2006.252.07:56:30.61#ibcon#about to read 3, iclass 34, count 0 2006.252.07:56:30.63#ibcon#read 3, iclass 34, count 0 2006.252.07:56:30.63#ibcon#about to read 4, iclass 34, count 0 2006.252.07:56:30.63#ibcon#read 4, iclass 34, count 0 2006.252.07:56:30.63#ibcon#about to read 5, iclass 34, count 0 2006.252.07:56:30.63#ibcon#read 5, iclass 34, count 0 2006.252.07:56:30.63#ibcon#about to read 6, iclass 34, count 0 2006.252.07:56:30.63#ibcon#read 6, iclass 34, count 0 2006.252.07:56:30.63#ibcon#end of sib2, iclass 34, count 0 2006.252.07:56:30.63#ibcon#*mode == 0, iclass 34, count 0 2006.252.07:56:30.63#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.252.07:56:30.63#ibcon#[28=FRQ=01,632.99\r\n] 2006.252.07:56:30.63#ibcon#*before write, iclass 34, count 0 2006.252.07:56:30.63#ibcon#enter sib2, iclass 34, count 0 2006.252.07:56:30.63#ibcon#flushed, iclass 34, count 0 2006.252.07:56:30.63#ibcon#about to write, iclass 34, count 0 2006.252.07:56:30.63#ibcon#wrote, iclass 34, count 0 2006.252.07:56:30.63#ibcon#about to read 3, iclass 34, count 0 2006.252.07:56:30.67#ibcon#read 3, iclass 34, count 0 2006.252.07:56:30.67#ibcon#about to read 4, iclass 34, count 0 2006.252.07:56:30.67#ibcon#read 4, iclass 34, count 0 2006.252.07:56:30.67#ibcon#about to read 5, iclass 34, count 0 2006.252.07:56:30.67#ibcon#read 5, iclass 34, count 0 2006.252.07:56:30.67#ibcon#about to read 6, iclass 34, count 0 2006.252.07:56:30.67#ibcon#read 6, iclass 34, count 0 2006.252.07:56:30.67#ibcon#end of sib2, iclass 34, count 0 2006.252.07:56:30.67#ibcon#*after write, iclass 34, count 0 2006.252.07:56:30.67#ibcon#*before return 0, iclass 34, count 0 2006.252.07:56:30.67#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.252.07:56:30.67#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.252.07:56:30.67#ibcon#about to clear, iclass 34 cls_cnt 0 2006.252.07:56:30.67#ibcon#cleared, iclass 34 cls_cnt 0 2006.252.07:56:30.67$vc4f8/vb=1,4 2006.252.07:56:30.67#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.252.07:56:30.67#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.252.07:56:30.67#ibcon#ireg 11 cls_cnt 2 2006.252.07:56:30.67#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.252.07:56:30.67#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.252.07:56:30.67#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.252.07:56:30.67#ibcon#enter wrdev, iclass 36, count 2 2006.252.07:56:30.67#ibcon#first serial, iclass 36, count 2 2006.252.07:56:30.67#ibcon#enter sib2, iclass 36, count 2 2006.252.07:56:30.67#ibcon#flushed, iclass 36, count 2 2006.252.07:56:30.67#ibcon#about to write, iclass 36, count 2 2006.252.07:56:30.67#ibcon#wrote, iclass 36, count 2 2006.252.07:56:30.67#ibcon#about to read 3, iclass 36, count 2 2006.252.07:56:30.69#ibcon#read 3, iclass 36, count 2 2006.252.07:56:30.69#ibcon#about to read 4, iclass 36, count 2 2006.252.07:56:30.69#ibcon#read 4, iclass 36, count 2 2006.252.07:56:30.69#ibcon#about to read 5, iclass 36, count 2 2006.252.07:56:30.69#ibcon#read 5, iclass 36, count 2 2006.252.07:56:30.69#ibcon#about to read 6, iclass 36, count 2 2006.252.07:56:30.69#ibcon#read 6, iclass 36, count 2 2006.252.07:56:30.69#ibcon#end of sib2, iclass 36, count 2 2006.252.07:56:30.69#ibcon#*mode == 0, iclass 36, count 2 2006.252.07:56:30.69#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.252.07:56:30.69#ibcon#[27=AT01-04\r\n] 2006.252.07:56:30.69#ibcon#*before write, iclass 36, count 2 2006.252.07:56:30.69#ibcon#enter sib2, iclass 36, count 2 2006.252.07:56:30.69#ibcon#flushed, iclass 36, count 2 2006.252.07:56:30.69#ibcon#about to write, iclass 36, count 2 2006.252.07:56:30.69#ibcon#wrote, iclass 36, count 2 2006.252.07:56:30.69#ibcon#about to read 3, iclass 36, count 2 2006.252.07:56:30.72#ibcon#read 3, iclass 36, count 2 2006.252.07:56:30.72#ibcon#about to read 4, iclass 36, count 2 2006.252.07:56:30.72#ibcon#read 4, iclass 36, count 2 2006.252.07:56:30.72#ibcon#about to read 5, iclass 36, count 2 2006.252.07:56:30.72#ibcon#read 5, iclass 36, count 2 2006.252.07:56:30.72#ibcon#about to read 6, iclass 36, count 2 2006.252.07:56:30.72#ibcon#read 6, iclass 36, count 2 2006.252.07:56:30.72#ibcon#end of sib2, iclass 36, count 2 2006.252.07:56:30.72#ibcon#*after write, iclass 36, count 2 2006.252.07:56:30.72#ibcon#*before return 0, iclass 36, count 2 2006.252.07:56:30.72#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.252.07:56:30.72#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.252.07:56:30.72#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.252.07:56:30.72#ibcon#ireg 7 cls_cnt 0 2006.252.07:56:30.72#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.252.07:56:30.84#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.252.07:56:30.84#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.252.07:56:30.84#ibcon#enter wrdev, iclass 36, count 0 2006.252.07:56:30.84#ibcon#first serial, iclass 36, count 0 2006.252.07:56:30.84#ibcon#enter sib2, iclass 36, count 0 2006.252.07:56:30.84#ibcon#flushed, iclass 36, count 0 2006.252.07:56:30.84#ibcon#about to write, iclass 36, count 0 2006.252.07:56:30.84#ibcon#wrote, iclass 36, count 0 2006.252.07:56:30.84#ibcon#about to read 3, iclass 36, count 0 2006.252.07:56:30.86#ibcon#read 3, iclass 36, count 0 2006.252.07:56:30.86#ibcon#about to read 4, iclass 36, count 0 2006.252.07:56:30.86#ibcon#read 4, iclass 36, count 0 2006.252.07:56:30.86#ibcon#about to read 5, iclass 36, count 0 2006.252.07:56:30.86#ibcon#read 5, iclass 36, count 0 2006.252.07:56:30.86#ibcon#about to read 6, iclass 36, count 0 2006.252.07:56:30.86#ibcon#read 6, iclass 36, count 0 2006.252.07:56:30.86#ibcon#end of sib2, iclass 36, count 0 2006.252.07:56:30.86#ibcon#*mode == 0, iclass 36, count 0 2006.252.07:56:30.86#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.252.07:56:30.86#ibcon#[27=USB\r\n] 2006.252.07:56:30.86#ibcon#*before write, iclass 36, count 0 2006.252.07:56:30.86#ibcon#enter sib2, iclass 36, count 0 2006.252.07:56:30.86#ibcon#flushed, iclass 36, count 0 2006.252.07:56:30.86#ibcon#about to write, iclass 36, count 0 2006.252.07:56:30.86#ibcon#wrote, iclass 36, count 0 2006.252.07:56:30.86#ibcon#about to read 3, iclass 36, count 0 2006.252.07:56:30.89#ibcon#read 3, iclass 36, count 0 2006.252.07:56:30.89#ibcon#about to read 4, iclass 36, count 0 2006.252.07:56:30.89#ibcon#read 4, iclass 36, count 0 2006.252.07:56:30.89#ibcon#about to read 5, iclass 36, count 0 2006.252.07:56:30.89#ibcon#read 5, iclass 36, count 0 2006.252.07:56:30.89#ibcon#about to read 6, iclass 36, count 0 2006.252.07:56:30.89#ibcon#read 6, iclass 36, count 0 2006.252.07:56:30.89#ibcon#end of sib2, iclass 36, count 0 2006.252.07:56:30.89#ibcon#*after write, iclass 36, count 0 2006.252.07:56:30.89#ibcon#*before return 0, iclass 36, count 0 2006.252.07:56:30.89#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.252.07:56:30.89#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.252.07:56:30.89#ibcon#about to clear, iclass 36 cls_cnt 0 2006.252.07:56:30.89#ibcon#cleared, iclass 36 cls_cnt 0 2006.252.07:56:30.89$vc4f8/vblo=2,640.99 2006.252.07:56:30.89#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.252.07:56:30.89#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.252.07:56:30.89#ibcon#ireg 17 cls_cnt 0 2006.252.07:56:30.89#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.252.07:56:30.89#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.252.07:56:30.89#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.252.07:56:30.89#ibcon#enter wrdev, iclass 38, count 0 2006.252.07:56:30.89#ibcon#first serial, iclass 38, count 0 2006.252.07:56:30.89#ibcon#enter sib2, iclass 38, count 0 2006.252.07:56:30.89#ibcon#flushed, iclass 38, count 0 2006.252.07:56:30.89#ibcon#about to write, iclass 38, count 0 2006.252.07:56:30.89#ibcon#wrote, iclass 38, count 0 2006.252.07:56:30.89#ibcon#about to read 3, iclass 38, count 0 2006.252.07:56:30.91#ibcon#read 3, iclass 38, count 0 2006.252.07:56:30.91#ibcon#about to read 4, iclass 38, count 0 2006.252.07:56:30.91#ibcon#read 4, iclass 38, count 0 2006.252.07:56:30.91#ibcon#about to read 5, iclass 38, count 0 2006.252.07:56:30.91#ibcon#read 5, iclass 38, count 0 2006.252.07:56:30.91#ibcon#about to read 6, iclass 38, count 0 2006.252.07:56:30.91#ibcon#read 6, iclass 38, count 0 2006.252.07:56:30.91#ibcon#end of sib2, iclass 38, count 0 2006.252.07:56:30.91#ibcon#*mode == 0, iclass 38, count 0 2006.252.07:56:30.91#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.252.07:56:30.91#ibcon#[28=FRQ=02,640.99\r\n] 2006.252.07:56:30.91#ibcon#*before write, iclass 38, count 0 2006.252.07:56:30.91#ibcon#enter sib2, iclass 38, count 0 2006.252.07:56:30.91#ibcon#flushed, iclass 38, count 0 2006.252.07:56:30.91#ibcon#about to write, iclass 38, count 0 2006.252.07:56:30.91#ibcon#wrote, iclass 38, count 0 2006.252.07:56:30.91#ibcon#about to read 3, iclass 38, count 0 2006.252.07:56:30.95#ibcon#read 3, iclass 38, count 0 2006.252.07:56:30.95#ibcon#about to read 4, iclass 38, count 0 2006.252.07:56:30.95#ibcon#read 4, iclass 38, count 0 2006.252.07:56:30.95#ibcon#about to read 5, iclass 38, count 0 2006.252.07:56:30.95#ibcon#read 5, iclass 38, count 0 2006.252.07:56:30.95#ibcon#about to read 6, iclass 38, count 0 2006.252.07:56:30.95#ibcon#read 6, iclass 38, count 0 2006.252.07:56:30.95#ibcon#end of sib2, iclass 38, count 0 2006.252.07:56:30.95#ibcon#*after write, iclass 38, count 0 2006.252.07:56:30.95#ibcon#*before return 0, iclass 38, count 0 2006.252.07:56:30.95#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.252.07:56:30.95#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.252.07:56:30.95#ibcon#about to clear, iclass 38 cls_cnt 0 2006.252.07:56:30.95#ibcon#cleared, iclass 38 cls_cnt 0 2006.252.07:56:30.95$vc4f8/vb=2,5 2006.252.07:56:30.95#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.252.07:56:30.95#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.252.07:56:30.95#ibcon#ireg 11 cls_cnt 2 2006.252.07:56:30.95#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.252.07:56:31.01#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.252.07:56:31.01#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.252.07:56:31.01#ibcon#enter wrdev, iclass 40, count 2 2006.252.07:56:31.01#ibcon#first serial, iclass 40, count 2 2006.252.07:56:31.01#ibcon#enter sib2, iclass 40, count 2 2006.252.07:56:31.01#ibcon#flushed, iclass 40, count 2 2006.252.07:56:31.01#ibcon#about to write, iclass 40, count 2 2006.252.07:56:31.01#ibcon#wrote, iclass 40, count 2 2006.252.07:56:31.01#ibcon#about to read 3, iclass 40, count 2 2006.252.07:56:31.03#ibcon#read 3, iclass 40, count 2 2006.252.07:56:31.03#ibcon#about to read 4, iclass 40, count 2 2006.252.07:56:31.03#ibcon#read 4, iclass 40, count 2 2006.252.07:56:31.03#ibcon#about to read 5, iclass 40, count 2 2006.252.07:56:31.03#ibcon#read 5, iclass 40, count 2 2006.252.07:56:31.03#ibcon#about to read 6, iclass 40, count 2 2006.252.07:56:31.03#ibcon#read 6, iclass 40, count 2 2006.252.07:56:31.03#ibcon#end of sib2, iclass 40, count 2 2006.252.07:56:31.03#ibcon#*mode == 0, iclass 40, count 2 2006.252.07:56:31.03#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.252.07:56:31.03#ibcon#[27=AT02-05\r\n] 2006.252.07:56:31.03#ibcon#*before write, iclass 40, count 2 2006.252.07:56:31.03#ibcon#enter sib2, iclass 40, count 2 2006.252.07:56:31.03#ibcon#flushed, iclass 40, count 2 2006.252.07:56:31.03#ibcon#about to write, iclass 40, count 2 2006.252.07:56:31.03#ibcon#wrote, iclass 40, count 2 2006.252.07:56:31.03#ibcon#about to read 3, iclass 40, count 2 2006.252.07:56:31.06#ibcon#read 3, iclass 40, count 2 2006.252.07:56:31.06#ibcon#about to read 4, iclass 40, count 2 2006.252.07:56:31.06#ibcon#read 4, iclass 40, count 2 2006.252.07:56:31.06#ibcon#about to read 5, iclass 40, count 2 2006.252.07:56:31.06#ibcon#read 5, iclass 40, count 2 2006.252.07:56:31.06#ibcon#about to read 6, iclass 40, count 2 2006.252.07:56:31.06#ibcon#read 6, iclass 40, count 2 2006.252.07:56:31.06#ibcon#end of sib2, iclass 40, count 2 2006.252.07:56:31.06#ibcon#*after write, iclass 40, count 2 2006.252.07:56:31.06#ibcon#*before return 0, iclass 40, count 2 2006.252.07:56:31.06#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.252.07:56:31.06#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.252.07:56:31.06#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.252.07:56:31.06#ibcon#ireg 7 cls_cnt 0 2006.252.07:56:31.06#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.252.07:56:31.18#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.252.07:56:31.18#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.252.07:56:31.18#ibcon#enter wrdev, iclass 40, count 0 2006.252.07:56:31.18#ibcon#first serial, iclass 40, count 0 2006.252.07:56:31.18#ibcon#enter sib2, iclass 40, count 0 2006.252.07:56:31.18#ibcon#flushed, iclass 40, count 0 2006.252.07:56:31.18#ibcon#about to write, iclass 40, count 0 2006.252.07:56:31.18#ibcon#wrote, iclass 40, count 0 2006.252.07:56:31.18#ibcon#about to read 3, iclass 40, count 0 2006.252.07:56:31.22#ibcon#read 3, iclass 40, count 0 2006.252.07:56:31.22#ibcon#about to read 4, iclass 40, count 0 2006.252.07:56:31.22#ibcon#read 4, iclass 40, count 0 2006.252.07:56:31.22#ibcon#about to read 5, iclass 40, count 0 2006.252.07:56:31.22#ibcon#read 5, iclass 40, count 0 2006.252.07:56:31.22#ibcon#about to read 6, iclass 40, count 0 2006.252.07:56:31.22#ibcon#read 6, iclass 40, count 0 2006.252.07:56:31.22#ibcon#end of sib2, iclass 40, count 0 2006.252.07:56:31.22#ibcon#*mode == 0, iclass 40, count 0 2006.252.07:56:31.22#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.252.07:56:31.22#ibcon#[27=USB\r\n] 2006.252.07:56:31.22#ibcon#*before write, iclass 40, count 0 2006.252.07:56:31.22#ibcon#enter sib2, iclass 40, count 0 2006.252.07:56:31.22#ibcon#flushed, iclass 40, count 0 2006.252.07:56:31.22#ibcon#about to write, iclass 40, count 0 2006.252.07:56:31.22#ibcon#wrote, iclass 40, count 0 2006.252.07:56:31.22#ibcon#about to read 3, iclass 40, count 0 2006.252.07:56:31.24#ibcon#read 3, iclass 40, count 0 2006.252.07:56:31.24#ibcon#about to read 4, iclass 40, count 0 2006.252.07:56:31.24#ibcon#read 4, iclass 40, count 0 2006.252.07:56:31.24#ibcon#about to read 5, iclass 40, count 0 2006.252.07:56:31.24#ibcon#read 5, iclass 40, count 0 2006.252.07:56:31.24#ibcon#about to read 6, iclass 40, count 0 2006.252.07:56:31.24#ibcon#read 6, iclass 40, count 0 2006.252.07:56:31.24#ibcon#end of sib2, iclass 40, count 0 2006.252.07:56:31.24#ibcon#*after write, iclass 40, count 0 2006.252.07:56:31.24#ibcon#*before return 0, iclass 40, count 0 2006.252.07:56:31.24#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.252.07:56:31.24#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.252.07:56:31.24#ibcon#about to clear, iclass 40 cls_cnt 0 2006.252.07:56:31.24#ibcon#cleared, iclass 40 cls_cnt 0 2006.252.07:56:31.24$vc4f8/vblo=3,656.99 2006.252.07:56:31.24#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.252.07:56:31.24#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.252.07:56:31.24#ibcon#ireg 17 cls_cnt 0 2006.252.07:56:31.24#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.252.07:56:31.24#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.252.07:56:31.24#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.252.07:56:31.24#ibcon#enter wrdev, iclass 4, count 0 2006.252.07:56:31.24#ibcon#first serial, iclass 4, count 0 2006.252.07:56:31.24#ibcon#enter sib2, iclass 4, count 0 2006.252.07:56:31.24#ibcon#flushed, iclass 4, count 0 2006.252.07:56:31.24#ibcon#about to write, iclass 4, count 0 2006.252.07:56:31.24#ibcon#wrote, iclass 4, count 0 2006.252.07:56:31.24#ibcon#about to read 3, iclass 4, count 0 2006.252.07:56:31.26#ibcon#read 3, iclass 4, count 0 2006.252.07:56:31.26#ibcon#about to read 4, iclass 4, count 0 2006.252.07:56:31.26#ibcon#read 4, iclass 4, count 0 2006.252.07:56:31.26#ibcon#about to read 5, iclass 4, count 0 2006.252.07:56:31.26#ibcon#read 5, iclass 4, count 0 2006.252.07:56:31.26#ibcon#about to read 6, iclass 4, count 0 2006.252.07:56:31.26#ibcon#read 6, iclass 4, count 0 2006.252.07:56:31.26#ibcon#end of sib2, iclass 4, count 0 2006.252.07:56:31.26#ibcon#*mode == 0, iclass 4, count 0 2006.252.07:56:31.26#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.252.07:56:31.26#ibcon#[28=FRQ=03,656.99\r\n] 2006.252.07:56:31.26#ibcon#*before write, iclass 4, count 0 2006.252.07:56:31.26#ibcon#enter sib2, iclass 4, count 0 2006.252.07:56:31.26#ibcon#flushed, iclass 4, count 0 2006.252.07:56:31.26#ibcon#about to write, iclass 4, count 0 2006.252.07:56:31.26#ibcon#wrote, iclass 4, count 0 2006.252.07:56:31.26#ibcon#about to read 3, iclass 4, count 0 2006.252.07:56:31.30#ibcon#read 3, iclass 4, count 0 2006.252.07:56:31.30#ibcon#about to read 4, iclass 4, count 0 2006.252.07:56:31.30#ibcon#read 4, iclass 4, count 0 2006.252.07:56:31.30#ibcon#about to read 5, iclass 4, count 0 2006.252.07:56:31.30#ibcon#read 5, iclass 4, count 0 2006.252.07:56:31.30#ibcon#about to read 6, iclass 4, count 0 2006.252.07:56:31.30#ibcon#read 6, iclass 4, count 0 2006.252.07:56:31.30#ibcon#end of sib2, iclass 4, count 0 2006.252.07:56:31.30#ibcon#*after write, iclass 4, count 0 2006.252.07:56:31.30#ibcon#*before return 0, iclass 4, count 0 2006.252.07:56:31.30#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.252.07:56:31.30#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.252.07:56:31.30#ibcon#about to clear, iclass 4 cls_cnt 0 2006.252.07:56:31.30#ibcon#cleared, iclass 4 cls_cnt 0 2006.252.07:56:31.30$vc4f8/vb=3,4 2006.252.07:56:31.30#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.252.07:56:31.30#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.252.07:56:31.30#ibcon#ireg 11 cls_cnt 2 2006.252.07:56:31.30#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.252.07:56:31.36#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.252.07:56:31.36#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.252.07:56:31.36#ibcon#enter wrdev, iclass 6, count 2 2006.252.07:56:31.36#ibcon#first serial, iclass 6, count 2 2006.252.07:56:31.36#ibcon#enter sib2, iclass 6, count 2 2006.252.07:56:31.36#ibcon#flushed, iclass 6, count 2 2006.252.07:56:31.36#ibcon#about to write, iclass 6, count 2 2006.252.07:56:31.36#ibcon#wrote, iclass 6, count 2 2006.252.07:56:31.36#ibcon#about to read 3, iclass 6, count 2 2006.252.07:56:31.38#ibcon#read 3, iclass 6, count 2 2006.252.07:56:31.38#ibcon#about to read 4, iclass 6, count 2 2006.252.07:56:31.38#ibcon#read 4, iclass 6, count 2 2006.252.07:56:31.38#ibcon#about to read 5, iclass 6, count 2 2006.252.07:56:31.38#ibcon#read 5, iclass 6, count 2 2006.252.07:56:31.38#ibcon#about to read 6, iclass 6, count 2 2006.252.07:56:31.38#ibcon#read 6, iclass 6, count 2 2006.252.07:56:31.38#ibcon#end of sib2, iclass 6, count 2 2006.252.07:56:31.38#ibcon#*mode == 0, iclass 6, count 2 2006.252.07:56:31.38#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.252.07:56:31.38#ibcon#[27=AT03-04\r\n] 2006.252.07:56:31.38#ibcon#*before write, iclass 6, count 2 2006.252.07:56:31.38#ibcon#enter sib2, iclass 6, count 2 2006.252.07:56:31.38#ibcon#flushed, iclass 6, count 2 2006.252.07:56:31.38#ibcon#about to write, iclass 6, count 2 2006.252.07:56:31.38#ibcon#wrote, iclass 6, count 2 2006.252.07:56:31.38#ibcon#about to read 3, iclass 6, count 2 2006.252.07:56:31.41#ibcon#read 3, iclass 6, count 2 2006.252.07:56:31.41#ibcon#about to read 4, iclass 6, count 2 2006.252.07:56:31.41#ibcon#read 4, iclass 6, count 2 2006.252.07:56:31.41#ibcon#about to read 5, iclass 6, count 2 2006.252.07:56:31.41#ibcon#read 5, iclass 6, count 2 2006.252.07:56:31.41#ibcon#about to read 6, iclass 6, count 2 2006.252.07:56:31.41#ibcon#read 6, iclass 6, count 2 2006.252.07:56:31.41#ibcon#end of sib2, iclass 6, count 2 2006.252.07:56:31.41#ibcon#*after write, iclass 6, count 2 2006.252.07:56:31.41#ibcon#*before return 0, iclass 6, count 2 2006.252.07:56:31.41#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.252.07:56:31.41#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.252.07:56:31.41#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.252.07:56:31.41#ibcon#ireg 7 cls_cnt 0 2006.252.07:56:31.41#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.252.07:56:31.53#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.252.07:56:31.53#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.252.07:56:31.53#ibcon#enter wrdev, iclass 6, count 0 2006.252.07:56:31.53#ibcon#first serial, iclass 6, count 0 2006.252.07:56:31.53#ibcon#enter sib2, iclass 6, count 0 2006.252.07:56:31.53#ibcon#flushed, iclass 6, count 0 2006.252.07:56:31.53#ibcon#about to write, iclass 6, count 0 2006.252.07:56:31.53#ibcon#wrote, iclass 6, count 0 2006.252.07:56:31.53#ibcon#about to read 3, iclass 6, count 0 2006.252.07:56:31.55#ibcon#read 3, iclass 6, count 0 2006.252.07:56:31.55#ibcon#about to read 4, iclass 6, count 0 2006.252.07:56:31.55#ibcon#read 4, iclass 6, count 0 2006.252.07:56:31.55#ibcon#about to read 5, iclass 6, count 0 2006.252.07:56:31.55#ibcon#read 5, iclass 6, count 0 2006.252.07:56:31.55#ibcon#about to read 6, iclass 6, count 0 2006.252.07:56:31.55#ibcon#read 6, iclass 6, count 0 2006.252.07:56:31.55#ibcon#end of sib2, iclass 6, count 0 2006.252.07:56:31.55#ibcon#*mode == 0, iclass 6, count 0 2006.252.07:56:31.55#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.252.07:56:31.55#ibcon#[27=USB\r\n] 2006.252.07:56:31.55#ibcon#*before write, iclass 6, count 0 2006.252.07:56:31.55#ibcon#enter sib2, iclass 6, count 0 2006.252.07:56:31.55#ibcon#flushed, iclass 6, count 0 2006.252.07:56:31.55#ibcon#about to write, iclass 6, count 0 2006.252.07:56:31.55#ibcon#wrote, iclass 6, count 0 2006.252.07:56:31.55#ibcon#about to read 3, iclass 6, count 0 2006.252.07:56:31.58#ibcon#read 3, iclass 6, count 0 2006.252.07:56:31.58#ibcon#about to read 4, iclass 6, count 0 2006.252.07:56:31.58#ibcon#read 4, iclass 6, count 0 2006.252.07:56:31.58#ibcon#about to read 5, iclass 6, count 0 2006.252.07:56:31.58#ibcon#read 5, iclass 6, count 0 2006.252.07:56:31.58#ibcon#about to read 6, iclass 6, count 0 2006.252.07:56:31.58#ibcon#read 6, iclass 6, count 0 2006.252.07:56:31.58#ibcon#end of sib2, iclass 6, count 0 2006.252.07:56:31.58#ibcon#*after write, iclass 6, count 0 2006.252.07:56:31.58#ibcon#*before return 0, iclass 6, count 0 2006.252.07:56:31.58#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.252.07:56:31.58#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.252.07:56:31.58#ibcon#about to clear, iclass 6 cls_cnt 0 2006.252.07:56:31.58#ibcon#cleared, iclass 6 cls_cnt 0 2006.252.07:56:31.58$vc4f8/vblo=4,712.99 2006.252.07:56:31.58#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.252.07:56:31.58#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.252.07:56:31.58#ibcon#ireg 17 cls_cnt 0 2006.252.07:56:31.58#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.252.07:56:31.58#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.252.07:56:31.58#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.252.07:56:31.58#ibcon#enter wrdev, iclass 10, count 0 2006.252.07:56:31.58#ibcon#first serial, iclass 10, count 0 2006.252.07:56:31.58#ibcon#enter sib2, iclass 10, count 0 2006.252.07:56:31.58#ibcon#flushed, iclass 10, count 0 2006.252.07:56:31.58#ibcon#about to write, iclass 10, count 0 2006.252.07:56:31.58#ibcon#wrote, iclass 10, count 0 2006.252.07:56:31.58#ibcon#about to read 3, iclass 10, count 0 2006.252.07:56:31.60#ibcon#read 3, iclass 10, count 0 2006.252.07:56:31.60#ibcon#about to read 4, iclass 10, count 0 2006.252.07:56:31.60#ibcon#read 4, iclass 10, count 0 2006.252.07:56:31.60#ibcon#about to read 5, iclass 10, count 0 2006.252.07:56:31.60#ibcon#read 5, iclass 10, count 0 2006.252.07:56:31.60#ibcon#about to read 6, iclass 10, count 0 2006.252.07:56:31.60#ibcon#read 6, iclass 10, count 0 2006.252.07:56:31.60#ibcon#end of sib2, iclass 10, count 0 2006.252.07:56:31.60#ibcon#*mode == 0, iclass 10, count 0 2006.252.07:56:31.60#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.252.07:56:31.60#ibcon#[28=FRQ=04,712.99\r\n] 2006.252.07:56:31.60#ibcon#*before write, iclass 10, count 0 2006.252.07:56:31.60#ibcon#enter sib2, iclass 10, count 0 2006.252.07:56:31.60#ibcon#flushed, iclass 10, count 0 2006.252.07:56:31.60#ibcon#about to write, iclass 10, count 0 2006.252.07:56:31.60#ibcon#wrote, iclass 10, count 0 2006.252.07:56:31.60#ibcon#about to read 3, iclass 10, count 0 2006.252.07:56:31.64#ibcon#read 3, iclass 10, count 0 2006.252.07:56:31.64#ibcon#about to read 4, iclass 10, count 0 2006.252.07:56:31.64#ibcon#read 4, iclass 10, count 0 2006.252.07:56:31.64#ibcon#about to read 5, iclass 10, count 0 2006.252.07:56:31.64#ibcon#read 5, iclass 10, count 0 2006.252.07:56:31.64#ibcon#about to read 6, iclass 10, count 0 2006.252.07:56:31.64#ibcon#read 6, iclass 10, count 0 2006.252.07:56:31.64#ibcon#end of sib2, iclass 10, count 0 2006.252.07:56:31.64#ibcon#*after write, iclass 10, count 0 2006.252.07:56:31.64#ibcon#*before return 0, iclass 10, count 0 2006.252.07:56:31.64#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.252.07:56:31.64#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.252.07:56:31.64#ibcon#about to clear, iclass 10 cls_cnt 0 2006.252.07:56:31.64#ibcon#cleared, iclass 10 cls_cnt 0 2006.252.07:56:31.64$vc4f8/vb=4,4 2006.252.07:56:31.64#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.252.07:56:31.64#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.252.07:56:31.64#ibcon#ireg 11 cls_cnt 2 2006.252.07:56:31.64#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.252.07:56:31.70#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.252.07:56:31.70#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.252.07:56:31.70#ibcon#enter wrdev, iclass 12, count 2 2006.252.07:56:31.70#ibcon#first serial, iclass 12, count 2 2006.252.07:56:31.70#ibcon#enter sib2, iclass 12, count 2 2006.252.07:56:31.70#ibcon#flushed, iclass 12, count 2 2006.252.07:56:31.70#ibcon#about to write, iclass 12, count 2 2006.252.07:56:31.70#ibcon#wrote, iclass 12, count 2 2006.252.07:56:31.70#ibcon#about to read 3, iclass 12, count 2 2006.252.07:56:31.72#ibcon#read 3, iclass 12, count 2 2006.252.07:56:31.72#ibcon#about to read 4, iclass 12, count 2 2006.252.07:56:31.72#ibcon#read 4, iclass 12, count 2 2006.252.07:56:31.72#ibcon#about to read 5, iclass 12, count 2 2006.252.07:56:31.72#ibcon#read 5, iclass 12, count 2 2006.252.07:56:31.72#ibcon#about to read 6, iclass 12, count 2 2006.252.07:56:31.72#ibcon#read 6, iclass 12, count 2 2006.252.07:56:31.72#ibcon#end of sib2, iclass 12, count 2 2006.252.07:56:31.72#ibcon#*mode == 0, iclass 12, count 2 2006.252.07:56:31.72#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.252.07:56:31.72#ibcon#[27=AT04-04\r\n] 2006.252.07:56:31.72#ibcon#*before write, iclass 12, count 2 2006.252.07:56:31.72#ibcon#enter sib2, iclass 12, count 2 2006.252.07:56:31.72#ibcon#flushed, iclass 12, count 2 2006.252.07:56:31.72#ibcon#about to write, iclass 12, count 2 2006.252.07:56:31.72#ibcon#wrote, iclass 12, count 2 2006.252.07:56:31.72#ibcon#about to read 3, iclass 12, count 2 2006.252.07:56:31.75#ibcon#read 3, iclass 12, count 2 2006.252.07:56:31.75#ibcon#about to read 4, iclass 12, count 2 2006.252.07:56:31.75#ibcon#read 4, iclass 12, count 2 2006.252.07:56:31.75#ibcon#about to read 5, iclass 12, count 2 2006.252.07:56:31.75#ibcon#read 5, iclass 12, count 2 2006.252.07:56:31.75#ibcon#about to read 6, iclass 12, count 2 2006.252.07:56:31.75#ibcon#read 6, iclass 12, count 2 2006.252.07:56:31.75#ibcon#end of sib2, iclass 12, count 2 2006.252.07:56:31.75#ibcon#*after write, iclass 12, count 2 2006.252.07:56:31.75#ibcon#*before return 0, iclass 12, count 2 2006.252.07:56:31.75#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.252.07:56:31.75#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.252.07:56:31.75#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.252.07:56:31.75#ibcon#ireg 7 cls_cnt 0 2006.252.07:56:31.75#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.252.07:56:31.87#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.252.07:56:31.87#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.252.07:56:31.87#ibcon#enter wrdev, iclass 12, count 0 2006.252.07:56:31.87#ibcon#first serial, iclass 12, count 0 2006.252.07:56:31.87#ibcon#enter sib2, iclass 12, count 0 2006.252.07:56:31.87#ibcon#flushed, iclass 12, count 0 2006.252.07:56:31.87#ibcon#about to write, iclass 12, count 0 2006.252.07:56:31.87#ibcon#wrote, iclass 12, count 0 2006.252.07:56:31.87#ibcon#about to read 3, iclass 12, count 0 2006.252.07:56:31.89#ibcon#read 3, iclass 12, count 0 2006.252.07:56:31.89#ibcon#about to read 4, iclass 12, count 0 2006.252.07:56:31.89#ibcon#read 4, iclass 12, count 0 2006.252.07:56:31.89#ibcon#about to read 5, iclass 12, count 0 2006.252.07:56:31.89#ibcon#read 5, iclass 12, count 0 2006.252.07:56:31.89#ibcon#about to read 6, iclass 12, count 0 2006.252.07:56:31.89#ibcon#read 6, iclass 12, count 0 2006.252.07:56:31.89#ibcon#end of sib2, iclass 12, count 0 2006.252.07:56:31.89#ibcon#*mode == 0, iclass 12, count 0 2006.252.07:56:31.89#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.252.07:56:31.89#ibcon#[27=USB\r\n] 2006.252.07:56:31.89#ibcon#*before write, iclass 12, count 0 2006.252.07:56:31.89#ibcon#enter sib2, iclass 12, count 0 2006.252.07:56:31.89#ibcon#flushed, iclass 12, count 0 2006.252.07:56:31.89#ibcon#about to write, iclass 12, count 0 2006.252.07:56:31.89#ibcon#wrote, iclass 12, count 0 2006.252.07:56:31.89#ibcon#about to read 3, iclass 12, count 0 2006.252.07:56:31.92#ibcon#read 3, iclass 12, count 0 2006.252.07:56:31.92#ibcon#about to read 4, iclass 12, count 0 2006.252.07:56:31.92#ibcon#read 4, iclass 12, count 0 2006.252.07:56:31.92#ibcon#about to read 5, iclass 12, count 0 2006.252.07:56:31.92#ibcon#read 5, iclass 12, count 0 2006.252.07:56:31.92#ibcon#about to read 6, iclass 12, count 0 2006.252.07:56:31.92#ibcon#read 6, iclass 12, count 0 2006.252.07:56:31.92#ibcon#end of sib2, iclass 12, count 0 2006.252.07:56:31.92#ibcon#*after write, iclass 12, count 0 2006.252.07:56:31.92#ibcon#*before return 0, iclass 12, count 0 2006.252.07:56:31.92#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.252.07:56:31.92#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.252.07:56:31.92#ibcon#about to clear, iclass 12 cls_cnt 0 2006.252.07:56:31.92#ibcon#cleared, iclass 12 cls_cnt 0 2006.252.07:56:31.92$vc4f8/vblo=5,744.99 2006.252.07:56:31.92#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.252.07:56:31.92#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.252.07:56:31.92#ibcon#ireg 17 cls_cnt 0 2006.252.07:56:31.92#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.252.07:56:31.92#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.252.07:56:31.92#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.252.07:56:31.92#ibcon#enter wrdev, iclass 14, count 0 2006.252.07:56:31.92#ibcon#first serial, iclass 14, count 0 2006.252.07:56:31.92#ibcon#enter sib2, iclass 14, count 0 2006.252.07:56:31.92#ibcon#flushed, iclass 14, count 0 2006.252.07:56:31.92#ibcon#about to write, iclass 14, count 0 2006.252.07:56:31.92#ibcon#wrote, iclass 14, count 0 2006.252.07:56:31.92#ibcon#about to read 3, iclass 14, count 0 2006.252.07:56:31.95#ibcon#read 3, iclass 14, count 0 2006.252.07:56:31.95#ibcon#about to read 4, iclass 14, count 0 2006.252.07:56:31.95#ibcon#read 4, iclass 14, count 0 2006.252.07:56:31.95#ibcon#about to read 5, iclass 14, count 0 2006.252.07:56:31.95#ibcon#read 5, iclass 14, count 0 2006.252.07:56:31.95#ibcon#about to read 6, iclass 14, count 0 2006.252.07:56:31.95#ibcon#read 6, iclass 14, count 0 2006.252.07:56:31.95#ibcon#end of sib2, iclass 14, count 0 2006.252.07:56:31.95#ibcon#*mode == 0, iclass 14, count 0 2006.252.07:56:31.95#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.252.07:56:31.95#ibcon#[28=FRQ=05,744.99\r\n] 2006.252.07:56:31.95#ibcon#*before write, iclass 14, count 0 2006.252.07:56:31.95#ibcon#enter sib2, iclass 14, count 0 2006.252.07:56:31.95#ibcon#flushed, iclass 14, count 0 2006.252.07:56:31.95#ibcon#about to write, iclass 14, count 0 2006.252.07:56:31.95#ibcon#wrote, iclass 14, count 0 2006.252.07:56:31.95#ibcon#about to read 3, iclass 14, count 0 2006.252.07:56:31.99#ibcon#read 3, iclass 14, count 0 2006.252.07:56:31.99#ibcon#about to read 4, iclass 14, count 0 2006.252.07:56:31.99#ibcon#read 4, iclass 14, count 0 2006.252.07:56:31.99#ibcon#about to read 5, iclass 14, count 0 2006.252.07:56:31.99#ibcon#read 5, iclass 14, count 0 2006.252.07:56:31.99#ibcon#about to read 6, iclass 14, count 0 2006.252.07:56:31.99#ibcon#read 6, iclass 14, count 0 2006.252.07:56:31.99#ibcon#end of sib2, iclass 14, count 0 2006.252.07:56:31.99#ibcon#*after write, iclass 14, count 0 2006.252.07:56:31.99#ibcon#*before return 0, iclass 14, count 0 2006.252.07:56:31.99#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.252.07:56:31.99#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.252.07:56:31.99#ibcon#about to clear, iclass 14 cls_cnt 0 2006.252.07:56:31.99#ibcon#cleared, iclass 14 cls_cnt 0 2006.252.07:56:31.99$vc4f8/vb=5,4 2006.252.07:56:31.99#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.252.07:56:31.99#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.252.07:56:31.99#ibcon#ireg 11 cls_cnt 2 2006.252.07:56:31.99#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.252.07:56:32.04#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.252.07:56:32.04#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.252.07:56:32.04#ibcon#enter wrdev, iclass 16, count 2 2006.252.07:56:32.04#ibcon#first serial, iclass 16, count 2 2006.252.07:56:32.04#ibcon#enter sib2, iclass 16, count 2 2006.252.07:56:32.04#ibcon#flushed, iclass 16, count 2 2006.252.07:56:32.04#ibcon#about to write, iclass 16, count 2 2006.252.07:56:32.04#ibcon#wrote, iclass 16, count 2 2006.252.07:56:32.04#ibcon#about to read 3, iclass 16, count 2 2006.252.07:56:32.06#ibcon#read 3, iclass 16, count 2 2006.252.07:56:32.06#ibcon#about to read 4, iclass 16, count 2 2006.252.07:56:32.06#ibcon#read 4, iclass 16, count 2 2006.252.07:56:32.06#ibcon#about to read 5, iclass 16, count 2 2006.252.07:56:32.06#ibcon#read 5, iclass 16, count 2 2006.252.07:56:32.06#ibcon#about to read 6, iclass 16, count 2 2006.252.07:56:32.06#ibcon#read 6, iclass 16, count 2 2006.252.07:56:32.06#ibcon#end of sib2, iclass 16, count 2 2006.252.07:56:32.06#ibcon#*mode == 0, iclass 16, count 2 2006.252.07:56:32.06#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.252.07:56:32.06#ibcon#[27=AT05-04\r\n] 2006.252.07:56:32.06#ibcon#*before write, iclass 16, count 2 2006.252.07:56:32.06#ibcon#enter sib2, iclass 16, count 2 2006.252.07:56:32.06#ibcon#flushed, iclass 16, count 2 2006.252.07:56:32.06#ibcon#about to write, iclass 16, count 2 2006.252.07:56:32.06#ibcon#wrote, iclass 16, count 2 2006.252.07:56:32.06#ibcon#about to read 3, iclass 16, count 2 2006.252.07:56:32.09#ibcon#read 3, iclass 16, count 2 2006.252.07:56:32.09#ibcon#about to read 4, iclass 16, count 2 2006.252.07:56:32.09#ibcon#read 4, iclass 16, count 2 2006.252.07:56:32.09#ibcon#about to read 5, iclass 16, count 2 2006.252.07:56:32.09#ibcon#read 5, iclass 16, count 2 2006.252.07:56:32.09#ibcon#about to read 6, iclass 16, count 2 2006.252.07:56:32.09#ibcon#read 6, iclass 16, count 2 2006.252.07:56:32.09#ibcon#end of sib2, iclass 16, count 2 2006.252.07:56:32.09#ibcon#*after write, iclass 16, count 2 2006.252.07:56:32.09#ibcon#*before return 0, iclass 16, count 2 2006.252.07:56:32.09#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.252.07:56:32.09#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.252.07:56:32.09#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.252.07:56:32.09#ibcon#ireg 7 cls_cnt 0 2006.252.07:56:32.09#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.252.07:56:32.21#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.252.07:56:32.21#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.252.07:56:32.21#ibcon#enter wrdev, iclass 16, count 0 2006.252.07:56:32.21#ibcon#first serial, iclass 16, count 0 2006.252.07:56:32.21#ibcon#enter sib2, iclass 16, count 0 2006.252.07:56:32.21#ibcon#flushed, iclass 16, count 0 2006.252.07:56:32.21#ibcon#about to write, iclass 16, count 0 2006.252.07:56:32.21#ibcon#wrote, iclass 16, count 0 2006.252.07:56:32.21#ibcon#about to read 3, iclass 16, count 0 2006.252.07:56:32.23#ibcon#read 3, iclass 16, count 0 2006.252.07:56:32.23#ibcon#about to read 4, iclass 16, count 0 2006.252.07:56:32.23#ibcon#read 4, iclass 16, count 0 2006.252.07:56:32.23#ibcon#about to read 5, iclass 16, count 0 2006.252.07:56:32.23#ibcon#read 5, iclass 16, count 0 2006.252.07:56:32.23#ibcon#about to read 6, iclass 16, count 0 2006.252.07:56:32.23#ibcon#read 6, iclass 16, count 0 2006.252.07:56:32.23#ibcon#end of sib2, iclass 16, count 0 2006.252.07:56:32.23#ibcon#*mode == 0, iclass 16, count 0 2006.252.07:56:32.23#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.252.07:56:32.23#ibcon#[27=USB\r\n] 2006.252.07:56:32.23#ibcon#*before write, iclass 16, count 0 2006.252.07:56:32.23#ibcon#enter sib2, iclass 16, count 0 2006.252.07:56:32.23#ibcon#flushed, iclass 16, count 0 2006.252.07:56:32.23#ibcon#about to write, iclass 16, count 0 2006.252.07:56:32.23#ibcon#wrote, iclass 16, count 0 2006.252.07:56:32.23#ibcon#about to read 3, iclass 16, count 0 2006.252.07:56:32.26#ibcon#read 3, iclass 16, count 0 2006.252.07:56:32.26#ibcon#about to read 4, iclass 16, count 0 2006.252.07:56:32.26#ibcon#read 4, iclass 16, count 0 2006.252.07:56:32.26#ibcon#about to read 5, iclass 16, count 0 2006.252.07:56:32.26#ibcon#read 5, iclass 16, count 0 2006.252.07:56:32.26#ibcon#about to read 6, iclass 16, count 0 2006.252.07:56:32.26#ibcon#read 6, iclass 16, count 0 2006.252.07:56:32.26#ibcon#end of sib2, iclass 16, count 0 2006.252.07:56:32.26#ibcon#*after write, iclass 16, count 0 2006.252.07:56:32.26#ibcon#*before return 0, iclass 16, count 0 2006.252.07:56:32.26#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.252.07:56:32.26#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.252.07:56:32.26#ibcon#about to clear, iclass 16 cls_cnt 0 2006.252.07:56:32.26#ibcon#cleared, iclass 16 cls_cnt 0 2006.252.07:56:32.26$vc4f8/vblo=6,752.99 2006.252.07:56:32.26#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.252.07:56:32.26#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.252.07:56:32.26#ibcon#ireg 17 cls_cnt 0 2006.252.07:56:32.26#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.252.07:56:32.26#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.252.07:56:32.26#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.252.07:56:32.26#ibcon#enter wrdev, iclass 18, count 0 2006.252.07:56:32.26#ibcon#first serial, iclass 18, count 0 2006.252.07:56:32.26#ibcon#enter sib2, iclass 18, count 0 2006.252.07:56:32.26#ibcon#flushed, iclass 18, count 0 2006.252.07:56:32.26#ibcon#about to write, iclass 18, count 0 2006.252.07:56:32.26#ibcon#wrote, iclass 18, count 0 2006.252.07:56:32.26#ibcon#about to read 3, iclass 18, count 0 2006.252.07:56:32.28#ibcon#read 3, iclass 18, count 0 2006.252.07:56:32.28#ibcon#about to read 4, iclass 18, count 0 2006.252.07:56:32.28#ibcon#read 4, iclass 18, count 0 2006.252.07:56:32.28#ibcon#about to read 5, iclass 18, count 0 2006.252.07:56:32.28#ibcon#read 5, iclass 18, count 0 2006.252.07:56:32.28#ibcon#about to read 6, iclass 18, count 0 2006.252.07:56:32.28#ibcon#read 6, iclass 18, count 0 2006.252.07:56:32.28#ibcon#end of sib2, iclass 18, count 0 2006.252.07:56:32.28#ibcon#*mode == 0, iclass 18, count 0 2006.252.07:56:32.28#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.252.07:56:32.28#ibcon#[28=FRQ=06,752.99\r\n] 2006.252.07:56:32.28#ibcon#*before write, iclass 18, count 0 2006.252.07:56:32.28#ibcon#enter sib2, iclass 18, count 0 2006.252.07:56:32.28#ibcon#flushed, iclass 18, count 0 2006.252.07:56:32.28#ibcon#about to write, iclass 18, count 0 2006.252.07:56:32.28#ibcon#wrote, iclass 18, count 0 2006.252.07:56:32.28#ibcon#about to read 3, iclass 18, count 0 2006.252.07:56:32.32#ibcon#read 3, iclass 18, count 0 2006.252.07:56:32.32#ibcon#about to read 4, iclass 18, count 0 2006.252.07:56:32.32#ibcon#read 4, iclass 18, count 0 2006.252.07:56:32.32#ibcon#about to read 5, iclass 18, count 0 2006.252.07:56:32.32#ibcon#read 5, iclass 18, count 0 2006.252.07:56:32.32#ibcon#about to read 6, iclass 18, count 0 2006.252.07:56:32.32#ibcon#read 6, iclass 18, count 0 2006.252.07:56:32.32#ibcon#end of sib2, iclass 18, count 0 2006.252.07:56:32.32#ibcon#*after write, iclass 18, count 0 2006.252.07:56:32.32#ibcon#*before return 0, iclass 18, count 0 2006.252.07:56:32.32#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.252.07:56:32.32#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.252.07:56:32.32#ibcon#about to clear, iclass 18 cls_cnt 0 2006.252.07:56:32.32#ibcon#cleared, iclass 18 cls_cnt 0 2006.252.07:56:32.32$vc4f8/vb=6,4 2006.252.07:56:32.32#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.252.07:56:32.32#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.252.07:56:32.32#ibcon#ireg 11 cls_cnt 2 2006.252.07:56:32.32#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.252.07:56:32.38#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.252.07:56:32.38#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.252.07:56:32.38#ibcon#enter wrdev, iclass 20, count 2 2006.252.07:56:32.38#ibcon#first serial, iclass 20, count 2 2006.252.07:56:32.38#ibcon#enter sib2, iclass 20, count 2 2006.252.07:56:32.38#ibcon#flushed, iclass 20, count 2 2006.252.07:56:32.38#ibcon#about to write, iclass 20, count 2 2006.252.07:56:32.38#ibcon#wrote, iclass 20, count 2 2006.252.07:56:32.38#ibcon#about to read 3, iclass 20, count 2 2006.252.07:56:32.40#ibcon#read 3, iclass 20, count 2 2006.252.07:56:32.40#ibcon#about to read 4, iclass 20, count 2 2006.252.07:56:32.40#ibcon#read 4, iclass 20, count 2 2006.252.07:56:32.40#ibcon#about to read 5, iclass 20, count 2 2006.252.07:56:32.40#ibcon#read 5, iclass 20, count 2 2006.252.07:56:32.40#ibcon#about to read 6, iclass 20, count 2 2006.252.07:56:32.40#ibcon#read 6, iclass 20, count 2 2006.252.07:56:32.40#ibcon#end of sib2, iclass 20, count 2 2006.252.07:56:32.40#ibcon#*mode == 0, iclass 20, count 2 2006.252.07:56:32.40#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.252.07:56:32.40#ibcon#[27=AT06-04\r\n] 2006.252.07:56:32.40#ibcon#*before write, iclass 20, count 2 2006.252.07:56:32.40#ibcon#enter sib2, iclass 20, count 2 2006.252.07:56:32.40#ibcon#flushed, iclass 20, count 2 2006.252.07:56:32.40#ibcon#about to write, iclass 20, count 2 2006.252.07:56:32.40#ibcon#wrote, iclass 20, count 2 2006.252.07:56:32.40#ibcon#about to read 3, iclass 20, count 2 2006.252.07:56:32.43#ibcon#read 3, iclass 20, count 2 2006.252.07:56:32.43#ibcon#about to read 4, iclass 20, count 2 2006.252.07:56:32.43#ibcon#read 4, iclass 20, count 2 2006.252.07:56:32.43#ibcon#about to read 5, iclass 20, count 2 2006.252.07:56:32.43#ibcon#read 5, iclass 20, count 2 2006.252.07:56:32.43#ibcon#about to read 6, iclass 20, count 2 2006.252.07:56:32.43#ibcon#read 6, iclass 20, count 2 2006.252.07:56:32.43#ibcon#end of sib2, iclass 20, count 2 2006.252.07:56:32.43#ibcon#*after write, iclass 20, count 2 2006.252.07:56:32.43#ibcon#*before return 0, iclass 20, count 2 2006.252.07:56:32.43#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.252.07:56:32.43#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.252.07:56:32.43#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.252.07:56:32.43#ibcon#ireg 7 cls_cnt 0 2006.252.07:56:32.43#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.252.07:56:32.55#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.252.07:56:32.55#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.252.07:56:32.55#ibcon#enter wrdev, iclass 20, count 0 2006.252.07:56:32.55#ibcon#first serial, iclass 20, count 0 2006.252.07:56:32.55#ibcon#enter sib2, iclass 20, count 0 2006.252.07:56:32.55#ibcon#flushed, iclass 20, count 0 2006.252.07:56:32.55#ibcon#about to write, iclass 20, count 0 2006.252.07:56:32.55#ibcon#wrote, iclass 20, count 0 2006.252.07:56:32.55#ibcon#about to read 3, iclass 20, count 0 2006.252.07:56:32.57#ibcon#read 3, iclass 20, count 0 2006.252.07:56:32.57#ibcon#about to read 4, iclass 20, count 0 2006.252.07:56:32.57#ibcon#read 4, iclass 20, count 0 2006.252.07:56:32.57#ibcon#about to read 5, iclass 20, count 0 2006.252.07:56:32.57#ibcon#read 5, iclass 20, count 0 2006.252.07:56:32.57#ibcon#about to read 6, iclass 20, count 0 2006.252.07:56:32.57#ibcon#read 6, iclass 20, count 0 2006.252.07:56:32.57#ibcon#end of sib2, iclass 20, count 0 2006.252.07:56:32.57#ibcon#*mode == 0, iclass 20, count 0 2006.252.07:56:32.57#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.252.07:56:32.57#ibcon#[27=USB\r\n] 2006.252.07:56:32.57#ibcon#*before write, iclass 20, count 0 2006.252.07:56:32.57#ibcon#enter sib2, iclass 20, count 0 2006.252.07:56:32.57#ibcon#flushed, iclass 20, count 0 2006.252.07:56:32.57#ibcon#about to write, iclass 20, count 0 2006.252.07:56:32.57#ibcon#wrote, iclass 20, count 0 2006.252.07:56:32.57#ibcon#about to read 3, iclass 20, count 0 2006.252.07:56:32.60#ibcon#read 3, iclass 20, count 0 2006.252.07:56:32.60#ibcon#about to read 4, iclass 20, count 0 2006.252.07:56:32.60#ibcon#read 4, iclass 20, count 0 2006.252.07:56:32.60#ibcon#about to read 5, iclass 20, count 0 2006.252.07:56:32.60#ibcon#read 5, iclass 20, count 0 2006.252.07:56:32.60#ibcon#about to read 6, iclass 20, count 0 2006.252.07:56:32.60#ibcon#read 6, iclass 20, count 0 2006.252.07:56:32.60#ibcon#end of sib2, iclass 20, count 0 2006.252.07:56:32.60#ibcon#*after write, iclass 20, count 0 2006.252.07:56:32.60#ibcon#*before return 0, iclass 20, count 0 2006.252.07:56:32.60#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.252.07:56:32.60#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.252.07:56:32.60#ibcon#about to clear, iclass 20 cls_cnt 0 2006.252.07:56:32.60#ibcon#cleared, iclass 20 cls_cnt 0 2006.252.07:56:32.60$vc4f8/vabw=wide 2006.252.07:56:32.60#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.252.07:56:32.60#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.252.07:56:32.60#ibcon#ireg 8 cls_cnt 0 2006.252.07:56:32.60#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.252.07:56:32.60#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.252.07:56:32.60#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.252.07:56:32.60#ibcon#enter wrdev, iclass 22, count 0 2006.252.07:56:32.60#ibcon#first serial, iclass 22, count 0 2006.252.07:56:32.60#ibcon#enter sib2, iclass 22, count 0 2006.252.07:56:32.60#ibcon#flushed, iclass 22, count 0 2006.252.07:56:32.60#ibcon#about to write, iclass 22, count 0 2006.252.07:56:32.60#ibcon#wrote, iclass 22, count 0 2006.252.07:56:32.60#ibcon#about to read 3, iclass 22, count 0 2006.252.07:56:32.62#ibcon#read 3, iclass 22, count 0 2006.252.07:56:32.62#ibcon#about to read 4, iclass 22, count 0 2006.252.07:56:32.62#ibcon#read 4, iclass 22, count 0 2006.252.07:56:32.62#ibcon#about to read 5, iclass 22, count 0 2006.252.07:56:32.62#ibcon#read 5, iclass 22, count 0 2006.252.07:56:32.62#ibcon#about to read 6, iclass 22, count 0 2006.252.07:56:32.62#ibcon#read 6, iclass 22, count 0 2006.252.07:56:32.62#ibcon#end of sib2, iclass 22, count 0 2006.252.07:56:32.62#ibcon#*mode == 0, iclass 22, count 0 2006.252.07:56:32.62#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.252.07:56:32.62#ibcon#[25=BW32\r\n] 2006.252.07:56:32.62#ibcon#*before write, iclass 22, count 0 2006.252.07:56:32.62#ibcon#enter sib2, iclass 22, count 0 2006.252.07:56:32.62#ibcon#flushed, iclass 22, count 0 2006.252.07:56:32.62#ibcon#about to write, iclass 22, count 0 2006.252.07:56:32.62#ibcon#wrote, iclass 22, count 0 2006.252.07:56:32.62#ibcon#about to read 3, iclass 22, count 0 2006.252.07:56:32.65#ibcon#read 3, iclass 22, count 0 2006.252.07:56:32.65#ibcon#about to read 4, iclass 22, count 0 2006.252.07:56:32.65#ibcon#read 4, iclass 22, count 0 2006.252.07:56:32.65#ibcon#about to read 5, iclass 22, count 0 2006.252.07:56:32.65#ibcon#read 5, iclass 22, count 0 2006.252.07:56:32.65#ibcon#about to read 6, iclass 22, count 0 2006.252.07:56:32.65#ibcon#read 6, iclass 22, count 0 2006.252.07:56:32.65#ibcon#end of sib2, iclass 22, count 0 2006.252.07:56:32.65#ibcon#*after write, iclass 22, count 0 2006.252.07:56:32.65#ibcon#*before return 0, iclass 22, count 0 2006.252.07:56:32.65#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.252.07:56:32.65#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.252.07:56:32.65#ibcon#about to clear, iclass 22 cls_cnt 0 2006.252.07:56:32.65#ibcon#cleared, iclass 22 cls_cnt 0 2006.252.07:56:32.65$vc4f8/vbbw=wide 2006.252.07:56:32.65#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.252.07:56:32.65#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.252.07:56:32.65#ibcon#ireg 8 cls_cnt 0 2006.252.07:56:32.65#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.252.07:56:32.72#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.252.07:56:32.72#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.252.07:56:32.72#ibcon#enter wrdev, iclass 24, count 0 2006.252.07:56:32.72#ibcon#first serial, iclass 24, count 0 2006.252.07:56:32.72#ibcon#enter sib2, iclass 24, count 0 2006.252.07:56:32.72#ibcon#flushed, iclass 24, count 0 2006.252.07:56:32.72#ibcon#about to write, iclass 24, count 0 2006.252.07:56:32.72#ibcon#wrote, iclass 24, count 0 2006.252.07:56:32.72#ibcon#about to read 3, iclass 24, count 0 2006.252.07:56:32.74#ibcon#read 3, iclass 24, count 0 2006.252.07:56:32.74#ibcon#about to read 4, iclass 24, count 0 2006.252.07:56:32.74#ibcon#read 4, iclass 24, count 0 2006.252.07:56:32.74#ibcon#about to read 5, iclass 24, count 0 2006.252.07:56:32.74#ibcon#read 5, iclass 24, count 0 2006.252.07:56:32.74#ibcon#about to read 6, iclass 24, count 0 2006.252.07:56:32.74#ibcon#read 6, iclass 24, count 0 2006.252.07:56:32.74#ibcon#end of sib2, iclass 24, count 0 2006.252.07:56:32.74#ibcon#*mode == 0, iclass 24, count 0 2006.252.07:56:32.74#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.252.07:56:32.74#ibcon#[27=BW32\r\n] 2006.252.07:56:32.74#ibcon#*before write, iclass 24, count 0 2006.252.07:56:32.74#ibcon#enter sib2, iclass 24, count 0 2006.252.07:56:32.74#ibcon#flushed, iclass 24, count 0 2006.252.07:56:32.74#ibcon#about to write, iclass 24, count 0 2006.252.07:56:32.74#ibcon#wrote, iclass 24, count 0 2006.252.07:56:32.74#ibcon#about to read 3, iclass 24, count 0 2006.252.07:56:32.77#ibcon#read 3, iclass 24, count 0 2006.252.07:56:32.77#ibcon#about to read 4, iclass 24, count 0 2006.252.07:56:32.77#ibcon#read 4, iclass 24, count 0 2006.252.07:56:32.77#ibcon#about to read 5, iclass 24, count 0 2006.252.07:56:32.77#ibcon#read 5, iclass 24, count 0 2006.252.07:56:32.77#ibcon#about to read 6, iclass 24, count 0 2006.252.07:56:32.77#ibcon#read 6, iclass 24, count 0 2006.252.07:56:32.77#ibcon#end of sib2, iclass 24, count 0 2006.252.07:56:32.77#ibcon#*after write, iclass 24, count 0 2006.252.07:56:32.77#ibcon#*before return 0, iclass 24, count 0 2006.252.07:56:32.77#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.252.07:56:32.77#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.252.07:56:32.77#ibcon#about to clear, iclass 24 cls_cnt 0 2006.252.07:56:32.77#ibcon#cleared, iclass 24 cls_cnt 0 2006.252.07:56:32.77$4f8m12a/ifd4f 2006.252.07:56:32.77$ifd4f/lo= 2006.252.07:56:32.77$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.252.07:56:32.77$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.252.07:56:32.77$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.252.07:56:32.77$ifd4f/patch= 2006.252.07:56:32.77$ifd4f/patch=lo1,a1,a2,a3,a4 2006.252.07:56:32.77$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.252.07:56:32.77$ifd4f/patch=lo3,a5,a6,a7,a8 2006.252.07:56:32.77$4f8m12a/"form=m,16.000,1:2 2006.252.07:56:32.77$4f8m12a/"tpicd 2006.252.07:56:32.77$4f8m12a/echo=off 2006.252.07:56:32.77$4f8m12a/xlog=off 2006.252.07:56:32.77:!2006.252.07:58:40 2006.252.07:56:32.81#abcon#<5=/05 3.8 7.2 27.37 891011.2\r\n> 2006.252.07:56:55.14#trakl#Source acquired 2006.252.07:56:57.14#flagr#flagr/antenna,acquired 2006.252.07:58:40.00:preob 2006.252.07:58:40.14/onsource/TRACKING 2006.252.07:58:40.14:!2006.252.07:58:50 2006.252.07:58:50.00:data_valid=on 2006.252.07:58:50.00:midob 2006.252.07:58:51.14/onsource/TRACKING 2006.252.07:58:51.14/wx/27.35,1011.2,90 2006.252.07:58:51.19/cable/+6.4109E-03 2006.252.07:58:52.28/va/01,08,usb,yes,36,38 2006.252.07:58:52.28/va/02,07,usb,yes,36,38 2006.252.07:58:52.28/va/03,06,usb,yes,38,38 2006.252.07:58:52.28/va/04,07,usb,yes,37,40 2006.252.07:58:52.28/va/05,07,usb,yes,41,43 2006.252.07:58:52.28/va/06,07,usb,yes,36,36 2006.252.07:58:52.28/va/07,07,usb,yes,35,35 2006.252.07:58:52.28/va/08,07,usb,yes,38,38 2006.252.07:58:52.51/valo/01,532.99,yes,locked 2006.252.07:58:52.51/valo/02,572.99,yes,locked 2006.252.07:58:52.51/valo/03,672.99,yes,locked 2006.252.07:58:52.51/valo/04,832.99,yes,locked 2006.252.07:58:52.51/valo/05,652.99,yes,locked 2006.252.07:58:52.51/valo/06,772.99,yes,locked 2006.252.07:58:52.51/valo/07,832.99,yes,locked 2006.252.07:58:52.51/valo/08,852.99,yes,locked 2006.252.07:58:53.60/vb/01,04,usb,yes,32,31 2006.252.07:58:53.60/vb/02,05,usb,yes,30,32 2006.252.07:58:53.60/vb/03,04,usb,yes,31,35 2006.252.07:58:53.60/vb/04,04,usb,yes,32,32 2006.252.07:58:53.60/vb/05,04,usb,yes,30,35 2006.252.07:58:53.60/vb/06,04,usb,yes,31,34 2006.252.07:58:53.60/vb/07,04,usb,yes,33,34 2006.252.07:58:53.60/vb/08,04,usb,yes,31,35 2006.252.07:58:53.83/vblo/01,632.99,yes,locked 2006.252.07:58:53.83/vblo/02,640.99,yes,locked 2006.252.07:58:53.83/vblo/03,656.99,yes,locked 2006.252.07:58:53.83/vblo/04,712.99,yes,locked 2006.252.07:58:53.83/vblo/05,744.99,yes,locked 2006.252.07:58:53.83/vblo/06,752.99,yes,locked 2006.252.07:58:53.83/vblo/07,734.99,yes,locked 2006.252.07:58:53.83/vblo/08,744.99,yes,locked 2006.252.07:58:53.98/vabw/8 2006.252.07:58:54.13/vbbw/8 2006.252.07:58:54.22/xfe/off,on,14.2 2006.252.07:58:54.59/ifatt/23,28,28,28 2006.252.07:58:55.07/fmout-gps/S +4.80E-07 2006.252.07:58:55.11:!2006.252.07:59:50 2006.252.07:59:50.00:data_valid=off 2006.252.07:59:50.00:postob 2006.252.07:59:50.11/cable/+6.4098E-03 2006.252.07:59:50.11/wx/27.35,1011.2,90 2006.252.07:59:51.08/fmout-gps/S +4.79E-07 2006.252.07:59:51.08:scan_name=252-0800,k06252,60 2006.252.07:59:51.09:source=nrao512,164029.63,394646.0,2000.0,cw 2006.252.07:59:51.14#flagr#flagr/antenna,new-source 2006.252.07:59:52.14:checkk5 2006.252.07:59:52.52/chk_autoobs//k5ts1/ autoobs is running! 2006.252.07:59:52.89/chk_autoobs//k5ts2/ autoobs is running! 2006.252.07:59:53.27/chk_autoobs//k5ts3/ autoobs is running! 2006.252.07:59:53.65/chk_autoobs//k5ts4/ autoobs is running! 2006.252.07:59:54.01/chk_obsdata//k5ts1/T2520758??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.07:59:54.38/chk_obsdata//k5ts2/T2520758??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.07:59:54.75/chk_obsdata//k5ts3/T2520758??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.07:59:55.12/chk_obsdata//k5ts4/T2520758??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.07:59:55.83/k5log//k5ts1_log_newline 2006.252.07:59:56.54/k5log//k5ts2_log_newline 2006.252.07:59:57.23/k5log//k5ts3_log_newline 2006.252.07:59:57.92/k5log//k5ts4_log_newline 2006.252.07:59:57.94/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.252.07:59:57.94:4f8m12a=2 2006.252.07:59:57.94$4f8m12a/echo=on 2006.252.07:59:57.94$4f8m12a/pcalon 2006.252.07:59:57.94$pcalon/"no phase cal control is implemented here 2006.252.07:59:57.94$4f8m12a/"tpicd=stop 2006.252.07:59:57.94$4f8m12a/vc4f8 2006.252.07:59:57.95$vc4f8/valo=1,532.99 2006.252.07:59:57.95#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.252.07:59:57.95#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.252.07:59:57.95#ibcon#ireg 17 cls_cnt 0 2006.252.07:59:57.95#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.252.07:59:57.95#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.252.07:59:57.95#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.252.07:59:57.95#ibcon#enter wrdev, iclass 39, count 0 2006.252.07:59:57.95#ibcon#first serial, iclass 39, count 0 2006.252.07:59:57.95#ibcon#enter sib2, iclass 39, count 0 2006.252.07:59:57.95#ibcon#flushed, iclass 39, count 0 2006.252.07:59:57.95#ibcon#about to write, iclass 39, count 0 2006.252.07:59:57.95#ibcon#wrote, iclass 39, count 0 2006.252.07:59:57.95#ibcon#about to read 3, iclass 39, count 0 2006.252.07:59:57.99#ibcon#read 3, iclass 39, count 0 2006.252.07:59:57.99#ibcon#about to read 4, iclass 39, count 0 2006.252.07:59:57.99#ibcon#read 4, iclass 39, count 0 2006.252.07:59:57.99#ibcon#about to read 5, iclass 39, count 0 2006.252.07:59:57.99#ibcon#read 5, iclass 39, count 0 2006.252.07:59:57.99#ibcon#about to read 6, iclass 39, count 0 2006.252.07:59:57.99#ibcon#read 6, iclass 39, count 0 2006.252.07:59:57.99#ibcon#end of sib2, iclass 39, count 0 2006.252.07:59:57.99#ibcon#*mode == 0, iclass 39, count 0 2006.252.07:59:57.99#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.252.07:59:57.99#ibcon#[26=FRQ=01,532.99\r\n] 2006.252.07:59:57.99#ibcon#*before write, iclass 39, count 0 2006.252.07:59:57.99#ibcon#enter sib2, iclass 39, count 0 2006.252.07:59:57.99#ibcon#flushed, iclass 39, count 0 2006.252.07:59:57.99#ibcon#about to write, iclass 39, count 0 2006.252.07:59:57.99#ibcon#wrote, iclass 39, count 0 2006.252.07:59:57.99#ibcon#about to read 3, iclass 39, count 0 2006.252.07:59:58.04#ibcon#read 3, iclass 39, count 0 2006.252.07:59:58.04#ibcon#about to read 4, iclass 39, count 0 2006.252.07:59:58.04#ibcon#read 4, iclass 39, count 0 2006.252.07:59:58.04#ibcon#about to read 5, iclass 39, count 0 2006.252.07:59:58.04#ibcon#read 5, iclass 39, count 0 2006.252.07:59:58.04#ibcon#about to read 6, iclass 39, count 0 2006.252.07:59:58.04#ibcon#read 6, iclass 39, count 0 2006.252.07:59:58.04#ibcon#end of sib2, iclass 39, count 0 2006.252.07:59:58.04#ibcon#*after write, iclass 39, count 0 2006.252.07:59:58.04#ibcon#*before return 0, iclass 39, count 0 2006.252.07:59:58.04#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.252.07:59:58.04#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.252.07:59:58.04#ibcon#about to clear, iclass 39 cls_cnt 0 2006.252.07:59:58.04#ibcon#cleared, iclass 39 cls_cnt 0 2006.252.07:59:58.04$vc4f8/va=1,8 2006.252.07:59:58.04#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.252.07:59:58.04#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.252.07:59:58.04#ibcon#ireg 11 cls_cnt 2 2006.252.07:59:58.04#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.252.07:59:58.04#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.252.07:59:58.04#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.252.07:59:58.04#ibcon#enter wrdev, iclass 3, count 2 2006.252.07:59:58.04#ibcon#first serial, iclass 3, count 2 2006.252.07:59:58.04#ibcon#enter sib2, iclass 3, count 2 2006.252.07:59:58.04#ibcon#flushed, iclass 3, count 2 2006.252.07:59:58.04#ibcon#about to write, iclass 3, count 2 2006.252.07:59:58.04#ibcon#wrote, iclass 3, count 2 2006.252.07:59:58.04#ibcon#about to read 3, iclass 3, count 2 2006.252.07:59:58.07#ibcon#read 3, iclass 3, count 2 2006.252.07:59:58.07#ibcon#about to read 4, iclass 3, count 2 2006.252.07:59:58.07#ibcon#read 4, iclass 3, count 2 2006.252.07:59:58.07#ibcon#about to read 5, iclass 3, count 2 2006.252.07:59:58.07#ibcon#read 5, iclass 3, count 2 2006.252.07:59:58.07#ibcon#about to read 6, iclass 3, count 2 2006.252.07:59:58.07#ibcon#read 6, iclass 3, count 2 2006.252.07:59:58.07#ibcon#end of sib2, iclass 3, count 2 2006.252.07:59:58.07#ibcon#*mode == 0, iclass 3, count 2 2006.252.07:59:58.07#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.252.07:59:58.07#ibcon#[25=AT01-08\r\n] 2006.252.07:59:58.07#ibcon#*before write, iclass 3, count 2 2006.252.07:59:58.07#ibcon#enter sib2, iclass 3, count 2 2006.252.07:59:58.07#ibcon#flushed, iclass 3, count 2 2006.252.07:59:58.07#ibcon#about to write, iclass 3, count 2 2006.252.07:59:58.07#ibcon#wrote, iclass 3, count 2 2006.252.07:59:58.07#ibcon#about to read 3, iclass 3, count 2 2006.252.07:59:58.10#ibcon#read 3, iclass 3, count 2 2006.252.07:59:58.10#ibcon#about to read 4, iclass 3, count 2 2006.252.07:59:58.10#ibcon#read 4, iclass 3, count 2 2006.252.07:59:58.10#ibcon#about to read 5, iclass 3, count 2 2006.252.07:59:58.10#ibcon#read 5, iclass 3, count 2 2006.252.07:59:58.10#ibcon#about to read 6, iclass 3, count 2 2006.252.07:59:58.10#ibcon#read 6, iclass 3, count 2 2006.252.07:59:58.10#ibcon#end of sib2, iclass 3, count 2 2006.252.07:59:58.10#ibcon#*after write, iclass 3, count 2 2006.252.07:59:58.10#ibcon#*before return 0, iclass 3, count 2 2006.252.07:59:58.10#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.252.07:59:58.10#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.252.07:59:58.10#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.252.07:59:58.10#ibcon#ireg 7 cls_cnt 0 2006.252.07:59:58.10#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.252.07:59:58.22#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.252.07:59:58.22#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.252.07:59:58.22#ibcon#enter wrdev, iclass 3, count 0 2006.252.07:59:58.22#ibcon#first serial, iclass 3, count 0 2006.252.07:59:58.22#ibcon#enter sib2, iclass 3, count 0 2006.252.07:59:58.22#ibcon#flushed, iclass 3, count 0 2006.252.07:59:58.22#ibcon#about to write, iclass 3, count 0 2006.252.07:59:58.22#ibcon#wrote, iclass 3, count 0 2006.252.07:59:58.22#ibcon#about to read 3, iclass 3, count 0 2006.252.07:59:58.24#ibcon#read 3, iclass 3, count 0 2006.252.07:59:58.24#ibcon#about to read 4, iclass 3, count 0 2006.252.07:59:58.24#ibcon#read 4, iclass 3, count 0 2006.252.07:59:58.24#ibcon#about to read 5, iclass 3, count 0 2006.252.07:59:58.24#ibcon#read 5, iclass 3, count 0 2006.252.07:59:58.24#ibcon#about to read 6, iclass 3, count 0 2006.252.07:59:58.24#ibcon#read 6, iclass 3, count 0 2006.252.07:59:58.24#ibcon#end of sib2, iclass 3, count 0 2006.252.07:59:58.24#ibcon#*mode == 0, iclass 3, count 0 2006.252.07:59:58.24#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.252.07:59:58.24#ibcon#[25=USB\r\n] 2006.252.07:59:58.24#ibcon#*before write, iclass 3, count 0 2006.252.07:59:58.24#ibcon#enter sib2, iclass 3, count 0 2006.252.07:59:58.24#ibcon#flushed, iclass 3, count 0 2006.252.07:59:58.24#ibcon#about to write, iclass 3, count 0 2006.252.07:59:58.24#ibcon#wrote, iclass 3, count 0 2006.252.07:59:58.24#ibcon#about to read 3, iclass 3, count 0 2006.252.07:59:58.27#ibcon#read 3, iclass 3, count 0 2006.252.07:59:58.27#ibcon#about to read 4, iclass 3, count 0 2006.252.07:59:58.27#ibcon#read 4, iclass 3, count 0 2006.252.07:59:58.27#ibcon#about to read 5, iclass 3, count 0 2006.252.07:59:58.27#ibcon#read 5, iclass 3, count 0 2006.252.07:59:58.27#ibcon#about to read 6, iclass 3, count 0 2006.252.07:59:58.27#ibcon#read 6, iclass 3, count 0 2006.252.07:59:58.27#ibcon#end of sib2, iclass 3, count 0 2006.252.07:59:58.27#ibcon#*after write, iclass 3, count 0 2006.252.07:59:58.27#ibcon#*before return 0, iclass 3, count 0 2006.252.07:59:58.27#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.252.07:59:58.27#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.252.07:59:58.27#ibcon#about to clear, iclass 3 cls_cnt 0 2006.252.07:59:58.27#ibcon#cleared, iclass 3 cls_cnt 0 2006.252.07:59:58.27$vc4f8/valo=2,572.99 2006.252.07:59:58.27#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.252.07:59:58.27#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.252.07:59:58.27#ibcon#ireg 17 cls_cnt 0 2006.252.07:59:58.27#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.252.07:59:58.27#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.252.07:59:58.27#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.252.07:59:58.27#ibcon#enter wrdev, iclass 5, count 0 2006.252.07:59:58.27#ibcon#first serial, iclass 5, count 0 2006.252.07:59:58.27#ibcon#enter sib2, iclass 5, count 0 2006.252.07:59:58.27#ibcon#flushed, iclass 5, count 0 2006.252.07:59:58.27#ibcon#about to write, iclass 5, count 0 2006.252.07:59:58.27#ibcon#wrote, iclass 5, count 0 2006.252.07:59:58.27#ibcon#about to read 3, iclass 5, count 0 2006.252.07:59:58.29#ibcon#read 3, iclass 5, count 0 2006.252.07:59:58.29#ibcon#about to read 4, iclass 5, count 0 2006.252.07:59:58.29#ibcon#read 4, iclass 5, count 0 2006.252.07:59:58.29#ibcon#about to read 5, iclass 5, count 0 2006.252.07:59:58.29#ibcon#read 5, iclass 5, count 0 2006.252.07:59:58.29#ibcon#about to read 6, iclass 5, count 0 2006.252.07:59:58.29#ibcon#read 6, iclass 5, count 0 2006.252.07:59:58.29#ibcon#end of sib2, iclass 5, count 0 2006.252.07:59:58.29#ibcon#*mode == 0, iclass 5, count 0 2006.252.07:59:58.29#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.252.07:59:58.30#ibcon#[26=FRQ=02,572.99\r\n] 2006.252.07:59:58.30#ibcon#*before write, iclass 5, count 0 2006.252.07:59:58.30#ibcon#enter sib2, iclass 5, count 0 2006.252.07:59:58.30#ibcon#flushed, iclass 5, count 0 2006.252.07:59:58.30#ibcon#about to write, iclass 5, count 0 2006.252.07:59:58.30#ibcon#wrote, iclass 5, count 0 2006.252.07:59:58.30#ibcon#about to read 3, iclass 5, count 0 2006.252.07:59:58.34#ibcon#read 3, iclass 5, count 0 2006.252.07:59:58.34#ibcon#about to read 4, iclass 5, count 0 2006.252.07:59:58.34#ibcon#read 4, iclass 5, count 0 2006.252.07:59:58.34#ibcon#about to read 5, iclass 5, count 0 2006.252.07:59:58.34#ibcon#read 5, iclass 5, count 0 2006.252.07:59:58.34#ibcon#about to read 6, iclass 5, count 0 2006.252.07:59:58.34#ibcon#read 6, iclass 5, count 0 2006.252.07:59:58.34#ibcon#end of sib2, iclass 5, count 0 2006.252.07:59:58.34#ibcon#*after write, iclass 5, count 0 2006.252.07:59:58.34#ibcon#*before return 0, iclass 5, count 0 2006.252.07:59:58.34#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.252.07:59:58.34#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.252.07:59:58.34#ibcon#about to clear, iclass 5 cls_cnt 0 2006.252.07:59:58.34#ibcon#cleared, iclass 5 cls_cnt 0 2006.252.07:59:58.34$vc4f8/va=2,7 2006.252.07:59:58.34#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.252.07:59:58.34#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.252.07:59:58.34#ibcon#ireg 11 cls_cnt 2 2006.252.07:59:58.34#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.252.07:59:58.39#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.252.07:59:58.39#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.252.07:59:58.39#ibcon#enter wrdev, iclass 7, count 2 2006.252.07:59:58.39#ibcon#first serial, iclass 7, count 2 2006.252.07:59:58.39#ibcon#enter sib2, iclass 7, count 2 2006.252.07:59:58.39#ibcon#flushed, iclass 7, count 2 2006.252.07:59:58.39#ibcon#about to write, iclass 7, count 2 2006.252.07:59:58.39#ibcon#wrote, iclass 7, count 2 2006.252.07:59:58.39#ibcon#about to read 3, iclass 7, count 2 2006.252.07:59:58.41#ibcon#read 3, iclass 7, count 2 2006.252.07:59:58.41#ibcon#about to read 4, iclass 7, count 2 2006.252.07:59:58.41#ibcon#read 4, iclass 7, count 2 2006.252.07:59:58.41#ibcon#about to read 5, iclass 7, count 2 2006.252.07:59:58.41#ibcon#read 5, iclass 7, count 2 2006.252.07:59:58.41#ibcon#about to read 6, iclass 7, count 2 2006.252.07:59:58.41#ibcon#read 6, iclass 7, count 2 2006.252.07:59:58.41#ibcon#end of sib2, iclass 7, count 2 2006.252.07:59:58.41#ibcon#*mode == 0, iclass 7, count 2 2006.252.07:59:58.41#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.252.07:59:58.41#ibcon#[25=AT02-07\r\n] 2006.252.07:59:58.41#ibcon#*before write, iclass 7, count 2 2006.252.07:59:58.41#ibcon#enter sib2, iclass 7, count 2 2006.252.07:59:58.41#ibcon#flushed, iclass 7, count 2 2006.252.07:59:58.41#ibcon#about to write, iclass 7, count 2 2006.252.07:59:58.41#ibcon#wrote, iclass 7, count 2 2006.252.07:59:58.41#ibcon#about to read 3, iclass 7, count 2 2006.252.07:59:58.44#ibcon#read 3, iclass 7, count 2 2006.252.07:59:58.44#ibcon#about to read 4, iclass 7, count 2 2006.252.07:59:58.44#ibcon#read 4, iclass 7, count 2 2006.252.07:59:58.44#ibcon#about to read 5, iclass 7, count 2 2006.252.07:59:58.44#ibcon#read 5, iclass 7, count 2 2006.252.07:59:58.44#ibcon#about to read 6, iclass 7, count 2 2006.252.07:59:58.44#ibcon#read 6, iclass 7, count 2 2006.252.07:59:58.44#ibcon#end of sib2, iclass 7, count 2 2006.252.07:59:58.44#ibcon#*after write, iclass 7, count 2 2006.252.07:59:58.44#ibcon#*before return 0, iclass 7, count 2 2006.252.07:59:58.44#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.252.07:59:58.44#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.252.07:59:58.44#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.252.07:59:58.44#ibcon#ireg 7 cls_cnt 0 2006.252.07:59:58.44#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.252.07:59:58.56#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.252.07:59:58.56#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.252.07:59:58.56#ibcon#enter wrdev, iclass 7, count 0 2006.252.07:59:58.56#ibcon#first serial, iclass 7, count 0 2006.252.07:59:58.56#ibcon#enter sib2, iclass 7, count 0 2006.252.07:59:58.56#ibcon#flushed, iclass 7, count 0 2006.252.07:59:58.56#ibcon#about to write, iclass 7, count 0 2006.252.07:59:58.56#ibcon#wrote, iclass 7, count 0 2006.252.07:59:58.56#ibcon#about to read 3, iclass 7, count 0 2006.252.07:59:58.58#ibcon#read 3, iclass 7, count 0 2006.252.07:59:58.58#ibcon#about to read 4, iclass 7, count 0 2006.252.07:59:58.58#ibcon#read 4, iclass 7, count 0 2006.252.07:59:58.58#ibcon#about to read 5, iclass 7, count 0 2006.252.07:59:58.58#ibcon#read 5, iclass 7, count 0 2006.252.07:59:58.58#ibcon#about to read 6, iclass 7, count 0 2006.252.07:59:58.58#ibcon#read 6, iclass 7, count 0 2006.252.07:59:58.58#ibcon#end of sib2, iclass 7, count 0 2006.252.07:59:58.58#ibcon#*mode == 0, iclass 7, count 0 2006.252.07:59:58.58#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.252.07:59:58.58#ibcon#[25=USB\r\n] 2006.252.07:59:58.58#ibcon#*before write, iclass 7, count 0 2006.252.07:59:58.58#ibcon#enter sib2, iclass 7, count 0 2006.252.07:59:58.58#ibcon#flushed, iclass 7, count 0 2006.252.07:59:58.58#ibcon#about to write, iclass 7, count 0 2006.252.07:59:58.58#ibcon#wrote, iclass 7, count 0 2006.252.07:59:58.58#ibcon#about to read 3, iclass 7, count 0 2006.252.07:59:58.61#ibcon#read 3, iclass 7, count 0 2006.252.07:59:58.61#ibcon#about to read 4, iclass 7, count 0 2006.252.07:59:58.61#ibcon#read 4, iclass 7, count 0 2006.252.07:59:58.61#ibcon#about to read 5, iclass 7, count 0 2006.252.07:59:58.61#ibcon#read 5, iclass 7, count 0 2006.252.07:59:58.61#ibcon#about to read 6, iclass 7, count 0 2006.252.07:59:58.61#ibcon#read 6, iclass 7, count 0 2006.252.07:59:58.61#ibcon#end of sib2, iclass 7, count 0 2006.252.07:59:58.61#ibcon#*after write, iclass 7, count 0 2006.252.07:59:58.61#ibcon#*before return 0, iclass 7, count 0 2006.252.07:59:58.61#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.252.07:59:58.61#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.252.07:59:58.61#ibcon#about to clear, iclass 7 cls_cnt 0 2006.252.07:59:58.61#ibcon#cleared, iclass 7 cls_cnt 0 2006.252.07:59:58.61$vc4f8/valo=3,672.99 2006.252.07:59:58.61#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.252.07:59:58.61#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.252.07:59:58.61#ibcon#ireg 17 cls_cnt 0 2006.252.07:59:58.61#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.252.07:59:58.61#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.252.07:59:58.61#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.252.07:59:58.61#ibcon#enter wrdev, iclass 11, count 0 2006.252.07:59:58.61#ibcon#first serial, iclass 11, count 0 2006.252.07:59:58.61#ibcon#enter sib2, iclass 11, count 0 2006.252.07:59:58.61#ibcon#flushed, iclass 11, count 0 2006.252.07:59:58.61#ibcon#about to write, iclass 11, count 0 2006.252.07:59:58.61#ibcon#wrote, iclass 11, count 0 2006.252.07:59:58.61#ibcon#about to read 3, iclass 11, count 0 2006.252.07:59:58.63#ibcon#read 3, iclass 11, count 0 2006.252.07:59:58.63#ibcon#about to read 4, iclass 11, count 0 2006.252.07:59:58.63#ibcon#read 4, iclass 11, count 0 2006.252.07:59:58.63#ibcon#about to read 5, iclass 11, count 0 2006.252.07:59:58.63#ibcon#read 5, iclass 11, count 0 2006.252.07:59:58.64#ibcon#about to read 6, iclass 11, count 0 2006.252.07:59:58.64#ibcon#read 6, iclass 11, count 0 2006.252.07:59:58.64#ibcon#end of sib2, iclass 11, count 0 2006.252.07:59:58.64#ibcon#*mode == 0, iclass 11, count 0 2006.252.07:59:58.64#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.252.07:59:58.64#ibcon#[26=FRQ=03,672.99\r\n] 2006.252.07:59:58.64#ibcon#*before write, iclass 11, count 0 2006.252.07:59:58.64#ibcon#enter sib2, iclass 11, count 0 2006.252.07:59:58.64#ibcon#flushed, iclass 11, count 0 2006.252.07:59:58.64#ibcon#about to write, iclass 11, count 0 2006.252.07:59:58.64#ibcon#wrote, iclass 11, count 0 2006.252.07:59:58.64#ibcon#about to read 3, iclass 11, count 0 2006.252.07:59:58.68#ibcon#read 3, iclass 11, count 0 2006.252.07:59:58.68#ibcon#about to read 4, iclass 11, count 0 2006.252.07:59:58.68#ibcon#read 4, iclass 11, count 0 2006.252.07:59:58.68#ibcon#about to read 5, iclass 11, count 0 2006.252.07:59:58.68#ibcon#read 5, iclass 11, count 0 2006.252.07:59:58.68#ibcon#about to read 6, iclass 11, count 0 2006.252.07:59:58.68#ibcon#read 6, iclass 11, count 0 2006.252.07:59:58.68#ibcon#end of sib2, iclass 11, count 0 2006.252.07:59:58.68#ibcon#*after write, iclass 11, count 0 2006.252.07:59:58.68#ibcon#*before return 0, iclass 11, count 0 2006.252.07:59:58.68#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.252.07:59:58.68#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.252.07:59:58.68#ibcon#about to clear, iclass 11 cls_cnt 0 2006.252.07:59:58.68#ibcon#cleared, iclass 11 cls_cnt 0 2006.252.07:59:58.68$vc4f8/va=3,6 2006.252.07:59:58.68#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.252.07:59:58.68#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.252.07:59:58.68#ibcon#ireg 11 cls_cnt 2 2006.252.07:59:58.68#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.252.07:59:58.73#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.252.07:59:58.73#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.252.07:59:58.73#ibcon#enter wrdev, iclass 13, count 2 2006.252.07:59:58.73#ibcon#first serial, iclass 13, count 2 2006.252.07:59:58.73#ibcon#enter sib2, iclass 13, count 2 2006.252.07:59:58.73#ibcon#flushed, iclass 13, count 2 2006.252.07:59:58.73#ibcon#about to write, iclass 13, count 2 2006.252.07:59:58.73#ibcon#wrote, iclass 13, count 2 2006.252.07:59:58.73#ibcon#about to read 3, iclass 13, count 2 2006.252.07:59:58.75#ibcon#read 3, iclass 13, count 2 2006.252.07:59:58.75#ibcon#about to read 4, iclass 13, count 2 2006.252.07:59:58.75#ibcon#read 4, iclass 13, count 2 2006.252.07:59:58.75#ibcon#about to read 5, iclass 13, count 2 2006.252.07:59:58.75#ibcon#read 5, iclass 13, count 2 2006.252.07:59:58.75#ibcon#about to read 6, iclass 13, count 2 2006.252.07:59:58.75#ibcon#read 6, iclass 13, count 2 2006.252.07:59:58.75#ibcon#end of sib2, iclass 13, count 2 2006.252.07:59:58.75#ibcon#*mode == 0, iclass 13, count 2 2006.252.07:59:58.75#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.252.07:59:58.75#ibcon#[25=AT03-06\r\n] 2006.252.07:59:58.75#ibcon#*before write, iclass 13, count 2 2006.252.07:59:58.75#ibcon#enter sib2, iclass 13, count 2 2006.252.07:59:58.75#ibcon#flushed, iclass 13, count 2 2006.252.07:59:58.75#ibcon#about to write, iclass 13, count 2 2006.252.07:59:58.75#ibcon#wrote, iclass 13, count 2 2006.252.07:59:58.75#ibcon#about to read 3, iclass 13, count 2 2006.252.07:59:58.78#ibcon#read 3, iclass 13, count 2 2006.252.07:59:58.78#ibcon#about to read 4, iclass 13, count 2 2006.252.07:59:58.78#ibcon#read 4, iclass 13, count 2 2006.252.07:59:58.78#ibcon#about to read 5, iclass 13, count 2 2006.252.07:59:58.78#ibcon#read 5, iclass 13, count 2 2006.252.07:59:58.78#ibcon#about to read 6, iclass 13, count 2 2006.252.07:59:58.78#ibcon#read 6, iclass 13, count 2 2006.252.07:59:58.78#ibcon#end of sib2, iclass 13, count 2 2006.252.07:59:58.78#ibcon#*after write, iclass 13, count 2 2006.252.07:59:58.78#ibcon#*before return 0, iclass 13, count 2 2006.252.07:59:58.78#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.252.07:59:58.78#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.252.07:59:58.78#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.252.07:59:58.78#ibcon#ireg 7 cls_cnt 0 2006.252.07:59:58.78#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.252.07:59:58.90#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.252.07:59:58.90#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.252.07:59:58.90#ibcon#enter wrdev, iclass 13, count 0 2006.252.07:59:58.90#ibcon#first serial, iclass 13, count 0 2006.252.07:59:58.90#ibcon#enter sib2, iclass 13, count 0 2006.252.07:59:58.90#ibcon#flushed, iclass 13, count 0 2006.252.07:59:58.90#ibcon#about to write, iclass 13, count 0 2006.252.07:59:58.90#ibcon#wrote, iclass 13, count 0 2006.252.07:59:58.90#ibcon#about to read 3, iclass 13, count 0 2006.252.07:59:58.92#ibcon#read 3, iclass 13, count 0 2006.252.07:59:58.92#ibcon#about to read 4, iclass 13, count 0 2006.252.07:59:58.92#ibcon#read 4, iclass 13, count 0 2006.252.07:59:58.92#ibcon#about to read 5, iclass 13, count 0 2006.252.07:59:58.92#ibcon#read 5, iclass 13, count 0 2006.252.07:59:58.92#ibcon#about to read 6, iclass 13, count 0 2006.252.07:59:58.92#ibcon#read 6, iclass 13, count 0 2006.252.07:59:58.92#ibcon#end of sib2, iclass 13, count 0 2006.252.07:59:58.92#ibcon#*mode == 0, iclass 13, count 0 2006.252.07:59:58.92#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.252.07:59:58.92#ibcon#[25=USB\r\n] 2006.252.07:59:58.92#ibcon#*before write, iclass 13, count 0 2006.252.07:59:58.92#ibcon#enter sib2, iclass 13, count 0 2006.252.07:59:58.92#ibcon#flushed, iclass 13, count 0 2006.252.07:59:58.92#ibcon#about to write, iclass 13, count 0 2006.252.07:59:58.92#ibcon#wrote, iclass 13, count 0 2006.252.07:59:58.92#ibcon#about to read 3, iclass 13, count 0 2006.252.07:59:58.95#ibcon#read 3, iclass 13, count 0 2006.252.07:59:58.95#ibcon#about to read 4, iclass 13, count 0 2006.252.07:59:58.95#ibcon#read 4, iclass 13, count 0 2006.252.07:59:58.95#ibcon#about to read 5, iclass 13, count 0 2006.252.07:59:58.95#ibcon#read 5, iclass 13, count 0 2006.252.07:59:58.95#ibcon#about to read 6, iclass 13, count 0 2006.252.07:59:58.95#ibcon#read 6, iclass 13, count 0 2006.252.07:59:58.95#ibcon#end of sib2, iclass 13, count 0 2006.252.07:59:58.95#ibcon#*after write, iclass 13, count 0 2006.252.07:59:58.95#ibcon#*before return 0, iclass 13, count 0 2006.252.07:59:58.95#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.252.07:59:58.95#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.252.07:59:58.95#ibcon#about to clear, iclass 13 cls_cnt 0 2006.252.07:59:58.95#ibcon#cleared, iclass 13 cls_cnt 0 2006.252.07:59:58.95$vc4f8/valo=4,832.99 2006.252.07:59:58.95#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.252.07:59:58.95#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.252.07:59:58.95#ibcon#ireg 17 cls_cnt 0 2006.252.07:59:58.95#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.252.07:59:58.95#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.252.07:59:58.95#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.252.07:59:58.95#ibcon#enter wrdev, iclass 15, count 0 2006.252.07:59:58.95#ibcon#first serial, iclass 15, count 0 2006.252.07:59:58.95#ibcon#enter sib2, iclass 15, count 0 2006.252.07:59:58.95#ibcon#flushed, iclass 15, count 0 2006.252.07:59:58.95#ibcon#about to write, iclass 15, count 0 2006.252.07:59:58.95#ibcon#wrote, iclass 15, count 0 2006.252.07:59:58.95#ibcon#about to read 3, iclass 15, count 0 2006.252.07:59:58.97#ibcon#read 3, iclass 15, count 0 2006.252.07:59:58.97#ibcon#about to read 4, iclass 15, count 0 2006.252.07:59:58.97#ibcon#read 4, iclass 15, count 0 2006.252.07:59:58.97#ibcon#about to read 5, iclass 15, count 0 2006.252.07:59:58.98#ibcon#read 5, iclass 15, count 0 2006.252.07:59:58.98#ibcon#about to read 6, iclass 15, count 0 2006.252.07:59:58.98#ibcon#read 6, iclass 15, count 0 2006.252.07:59:58.98#ibcon#end of sib2, iclass 15, count 0 2006.252.07:59:58.98#ibcon#*mode == 0, iclass 15, count 0 2006.252.07:59:58.98#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.252.07:59:58.98#ibcon#[26=FRQ=04,832.99\r\n] 2006.252.07:59:58.98#ibcon#*before write, iclass 15, count 0 2006.252.07:59:58.98#ibcon#enter sib2, iclass 15, count 0 2006.252.07:59:58.98#ibcon#flushed, iclass 15, count 0 2006.252.07:59:58.98#ibcon#about to write, iclass 15, count 0 2006.252.07:59:58.98#ibcon#wrote, iclass 15, count 0 2006.252.07:59:58.98#ibcon#about to read 3, iclass 15, count 0 2006.252.07:59:59.02#ibcon#read 3, iclass 15, count 0 2006.252.07:59:59.02#ibcon#about to read 4, iclass 15, count 0 2006.252.07:59:59.02#ibcon#read 4, iclass 15, count 0 2006.252.07:59:59.02#ibcon#about to read 5, iclass 15, count 0 2006.252.07:59:59.02#ibcon#read 5, iclass 15, count 0 2006.252.07:59:59.02#ibcon#about to read 6, iclass 15, count 0 2006.252.07:59:59.02#ibcon#read 6, iclass 15, count 0 2006.252.07:59:59.02#ibcon#end of sib2, iclass 15, count 0 2006.252.07:59:59.02#ibcon#*after write, iclass 15, count 0 2006.252.07:59:59.02#ibcon#*before return 0, iclass 15, count 0 2006.252.07:59:59.02#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.252.07:59:59.02#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.252.07:59:59.02#ibcon#about to clear, iclass 15 cls_cnt 0 2006.252.07:59:59.02#ibcon#cleared, iclass 15 cls_cnt 0 2006.252.07:59:59.02$vc4f8/va=4,7 2006.252.07:59:59.02#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.252.07:59:59.02#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.252.07:59:59.02#ibcon#ireg 11 cls_cnt 2 2006.252.07:59:59.02#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.252.07:59:59.07#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.252.07:59:59.07#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.252.07:59:59.07#ibcon#enter wrdev, iclass 17, count 2 2006.252.07:59:59.07#ibcon#first serial, iclass 17, count 2 2006.252.07:59:59.07#ibcon#enter sib2, iclass 17, count 2 2006.252.07:59:59.07#ibcon#flushed, iclass 17, count 2 2006.252.07:59:59.07#ibcon#about to write, iclass 17, count 2 2006.252.07:59:59.07#ibcon#wrote, iclass 17, count 2 2006.252.07:59:59.07#ibcon#about to read 3, iclass 17, count 2 2006.252.07:59:59.09#ibcon#read 3, iclass 17, count 2 2006.252.07:59:59.09#ibcon#about to read 4, iclass 17, count 2 2006.252.07:59:59.09#ibcon#read 4, iclass 17, count 2 2006.252.07:59:59.09#ibcon#about to read 5, iclass 17, count 2 2006.252.07:59:59.09#ibcon#read 5, iclass 17, count 2 2006.252.07:59:59.09#ibcon#about to read 6, iclass 17, count 2 2006.252.07:59:59.09#ibcon#read 6, iclass 17, count 2 2006.252.07:59:59.09#ibcon#end of sib2, iclass 17, count 2 2006.252.07:59:59.09#ibcon#*mode == 0, iclass 17, count 2 2006.252.07:59:59.09#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.252.07:59:59.09#ibcon#[25=AT04-07\r\n] 2006.252.07:59:59.09#ibcon#*before write, iclass 17, count 2 2006.252.07:59:59.09#ibcon#enter sib2, iclass 17, count 2 2006.252.07:59:59.09#ibcon#flushed, iclass 17, count 2 2006.252.07:59:59.09#ibcon#about to write, iclass 17, count 2 2006.252.07:59:59.09#ibcon#wrote, iclass 17, count 2 2006.252.07:59:59.09#ibcon#about to read 3, iclass 17, count 2 2006.252.07:59:59.12#ibcon#read 3, iclass 17, count 2 2006.252.07:59:59.12#ibcon#about to read 4, iclass 17, count 2 2006.252.07:59:59.12#ibcon#read 4, iclass 17, count 2 2006.252.07:59:59.12#ibcon#about to read 5, iclass 17, count 2 2006.252.07:59:59.12#ibcon#read 5, iclass 17, count 2 2006.252.07:59:59.12#ibcon#about to read 6, iclass 17, count 2 2006.252.07:59:59.12#ibcon#read 6, iclass 17, count 2 2006.252.07:59:59.12#ibcon#end of sib2, iclass 17, count 2 2006.252.07:59:59.12#ibcon#*after write, iclass 17, count 2 2006.252.07:59:59.12#ibcon#*before return 0, iclass 17, count 2 2006.252.07:59:59.12#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.252.07:59:59.12#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.252.07:59:59.12#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.252.07:59:59.12#ibcon#ireg 7 cls_cnt 0 2006.252.07:59:59.12#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.252.07:59:59.24#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.252.07:59:59.24#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.252.07:59:59.24#ibcon#enter wrdev, iclass 17, count 0 2006.252.07:59:59.24#ibcon#first serial, iclass 17, count 0 2006.252.07:59:59.24#ibcon#enter sib2, iclass 17, count 0 2006.252.07:59:59.24#ibcon#flushed, iclass 17, count 0 2006.252.07:59:59.24#ibcon#about to write, iclass 17, count 0 2006.252.07:59:59.24#ibcon#wrote, iclass 17, count 0 2006.252.07:59:59.24#ibcon#about to read 3, iclass 17, count 0 2006.252.07:59:59.26#ibcon#read 3, iclass 17, count 0 2006.252.07:59:59.26#ibcon#about to read 4, iclass 17, count 0 2006.252.07:59:59.26#ibcon#read 4, iclass 17, count 0 2006.252.07:59:59.26#ibcon#about to read 5, iclass 17, count 0 2006.252.07:59:59.26#ibcon#read 5, iclass 17, count 0 2006.252.07:59:59.26#ibcon#about to read 6, iclass 17, count 0 2006.252.07:59:59.26#ibcon#read 6, iclass 17, count 0 2006.252.07:59:59.26#ibcon#end of sib2, iclass 17, count 0 2006.252.07:59:59.26#ibcon#*mode == 0, iclass 17, count 0 2006.252.07:59:59.26#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.252.07:59:59.26#ibcon#[25=USB\r\n] 2006.252.07:59:59.26#ibcon#*before write, iclass 17, count 0 2006.252.07:59:59.26#ibcon#enter sib2, iclass 17, count 0 2006.252.07:59:59.26#ibcon#flushed, iclass 17, count 0 2006.252.07:59:59.26#ibcon#about to write, iclass 17, count 0 2006.252.07:59:59.26#ibcon#wrote, iclass 17, count 0 2006.252.07:59:59.26#ibcon#about to read 3, iclass 17, count 0 2006.252.07:59:59.29#ibcon#read 3, iclass 17, count 0 2006.252.07:59:59.29#ibcon#about to read 4, iclass 17, count 0 2006.252.07:59:59.29#ibcon#read 4, iclass 17, count 0 2006.252.07:59:59.29#ibcon#about to read 5, iclass 17, count 0 2006.252.07:59:59.29#ibcon#read 5, iclass 17, count 0 2006.252.07:59:59.29#ibcon#about to read 6, iclass 17, count 0 2006.252.07:59:59.29#ibcon#read 6, iclass 17, count 0 2006.252.07:59:59.29#ibcon#end of sib2, iclass 17, count 0 2006.252.07:59:59.29#ibcon#*after write, iclass 17, count 0 2006.252.07:59:59.29#ibcon#*before return 0, iclass 17, count 0 2006.252.07:59:59.29#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.252.07:59:59.29#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.252.07:59:59.29#ibcon#about to clear, iclass 17 cls_cnt 0 2006.252.07:59:59.29#ibcon#cleared, iclass 17 cls_cnt 0 2006.252.07:59:59.29$vc4f8/valo=5,652.99 2006.252.07:59:59.29#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.252.07:59:59.29#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.252.07:59:59.29#ibcon#ireg 17 cls_cnt 0 2006.252.07:59:59.29#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.252.07:59:59.29#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.252.07:59:59.29#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.252.07:59:59.29#ibcon#enter wrdev, iclass 19, count 0 2006.252.07:59:59.29#ibcon#first serial, iclass 19, count 0 2006.252.07:59:59.29#ibcon#enter sib2, iclass 19, count 0 2006.252.07:59:59.29#ibcon#flushed, iclass 19, count 0 2006.252.07:59:59.29#ibcon#about to write, iclass 19, count 0 2006.252.07:59:59.29#ibcon#wrote, iclass 19, count 0 2006.252.07:59:59.29#ibcon#about to read 3, iclass 19, count 0 2006.252.07:59:59.31#ibcon#read 3, iclass 19, count 0 2006.252.07:59:59.31#ibcon#about to read 4, iclass 19, count 0 2006.252.07:59:59.31#ibcon#read 4, iclass 19, count 0 2006.252.07:59:59.31#ibcon#about to read 5, iclass 19, count 0 2006.252.07:59:59.31#ibcon#read 5, iclass 19, count 0 2006.252.07:59:59.31#ibcon#about to read 6, iclass 19, count 0 2006.252.07:59:59.31#ibcon#read 6, iclass 19, count 0 2006.252.07:59:59.31#ibcon#end of sib2, iclass 19, count 0 2006.252.07:59:59.31#ibcon#*mode == 0, iclass 19, count 0 2006.252.07:59:59.31#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.252.07:59:59.31#ibcon#[26=FRQ=05,652.99\r\n] 2006.252.07:59:59.31#ibcon#*before write, iclass 19, count 0 2006.252.07:59:59.31#ibcon#enter sib2, iclass 19, count 0 2006.252.07:59:59.31#ibcon#flushed, iclass 19, count 0 2006.252.07:59:59.31#ibcon#about to write, iclass 19, count 0 2006.252.07:59:59.31#ibcon#wrote, iclass 19, count 0 2006.252.07:59:59.31#ibcon#about to read 3, iclass 19, count 0 2006.252.07:59:59.35#ibcon#read 3, iclass 19, count 0 2006.252.07:59:59.35#ibcon#about to read 4, iclass 19, count 0 2006.252.07:59:59.35#ibcon#read 4, iclass 19, count 0 2006.252.07:59:59.35#ibcon#about to read 5, iclass 19, count 0 2006.252.07:59:59.35#ibcon#read 5, iclass 19, count 0 2006.252.07:59:59.35#ibcon#about to read 6, iclass 19, count 0 2006.252.07:59:59.35#ibcon#read 6, iclass 19, count 0 2006.252.07:59:59.35#ibcon#end of sib2, iclass 19, count 0 2006.252.07:59:59.35#ibcon#*after write, iclass 19, count 0 2006.252.07:59:59.35#ibcon#*before return 0, iclass 19, count 0 2006.252.07:59:59.35#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.252.07:59:59.35#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.252.07:59:59.35#ibcon#about to clear, iclass 19 cls_cnt 0 2006.252.07:59:59.35#ibcon#cleared, iclass 19 cls_cnt 0 2006.252.07:59:59.35$vc4f8/va=5,7 2006.252.07:59:59.35#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.252.07:59:59.35#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.252.07:59:59.35#ibcon#ireg 11 cls_cnt 2 2006.252.07:59:59.35#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.252.07:59:59.41#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.252.07:59:59.41#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.252.07:59:59.41#ibcon#enter wrdev, iclass 21, count 2 2006.252.07:59:59.41#ibcon#first serial, iclass 21, count 2 2006.252.07:59:59.41#ibcon#enter sib2, iclass 21, count 2 2006.252.07:59:59.41#ibcon#flushed, iclass 21, count 2 2006.252.07:59:59.41#ibcon#about to write, iclass 21, count 2 2006.252.07:59:59.41#ibcon#wrote, iclass 21, count 2 2006.252.07:59:59.41#ibcon#about to read 3, iclass 21, count 2 2006.252.07:59:59.43#ibcon#read 3, iclass 21, count 2 2006.252.07:59:59.43#ibcon#about to read 4, iclass 21, count 2 2006.252.07:59:59.43#ibcon#read 4, iclass 21, count 2 2006.252.07:59:59.43#ibcon#about to read 5, iclass 21, count 2 2006.252.07:59:59.43#ibcon#read 5, iclass 21, count 2 2006.252.07:59:59.43#ibcon#about to read 6, iclass 21, count 2 2006.252.07:59:59.43#ibcon#read 6, iclass 21, count 2 2006.252.07:59:59.43#ibcon#end of sib2, iclass 21, count 2 2006.252.07:59:59.43#ibcon#*mode == 0, iclass 21, count 2 2006.252.07:59:59.43#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.252.07:59:59.43#ibcon#[25=AT05-07\r\n] 2006.252.07:59:59.43#ibcon#*before write, iclass 21, count 2 2006.252.07:59:59.43#ibcon#enter sib2, iclass 21, count 2 2006.252.07:59:59.43#ibcon#flushed, iclass 21, count 2 2006.252.07:59:59.43#ibcon#about to write, iclass 21, count 2 2006.252.07:59:59.43#ibcon#wrote, iclass 21, count 2 2006.252.07:59:59.43#ibcon#about to read 3, iclass 21, count 2 2006.252.07:59:59.46#ibcon#read 3, iclass 21, count 2 2006.252.07:59:59.46#ibcon#about to read 4, iclass 21, count 2 2006.252.07:59:59.46#ibcon#read 4, iclass 21, count 2 2006.252.07:59:59.46#ibcon#about to read 5, iclass 21, count 2 2006.252.07:59:59.46#ibcon#read 5, iclass 21, count 2 2006.252.07:59:59.46#ibcon#about to read 6, iclass 21, count 2 2006.252.07:59:59.46#ibcon#read 6, iclass 21, count 2 2006.252.07:59:59.46#ibcon#end of sib2, iclass 21, count 2 2006.252.07:59:59.46#ibcon#*after write, iclass 21, count 2 2006.252.07:59:59.46#ibcon#*before return 0, iclass 21, count 2 2006.252.07:59:59.46#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.252.07:59:59.46#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.252.07:59:59.46#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.252.07:59:59.46#ibcon#ireg 7 cls_cnt 0 2006.252.07:59:59.46#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.252.07:59:59.58#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.252.07:59:59.58#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.252.07:59:59.58#ibcon#enter wrdev, iclass 21, count 0 2006.252.07:59:59.58#ibcon#first serial, iclass 21, count 0 2006.252.07:59:59.58#ibcon#enter sib2, iclass 21, count 0 2006.252.07:59:59.58#ibcon#flushed, iclass 21, count 0 2006.252.07:59:59.58#ibcon#about to write, iclass 21, count 0 2006.252.07:59:59.58#ibcon#wrote, iclass 21, count 0 2006.252.07:59:59.58#ibcon#about to read 3, iclass 21, count 0 2006.252.07:59:59.60#ibcon#read 3, iclass 21, count 0 2006.252.07:59:59.60#ibcon#about to read 4, iclass 21, count 0 2006.252.07:59:59.60#ibcon#read 4, iclass 21, count 0 2006.252.07:59:59.60#ibcon#about to read 5, iclass 21, count 0 2006.252.07:59:59.60#ibcon#read 5, iclass 21, count 0 2006.252.07:59:59.60#ibcon#about to read 6, iclass 21, count 0 2006.252.07:59:59.60#ibcon#read 6, iclass 21, count 0 2006.252.07:59:59.60#ibcon#end of sib2, iclass 21, count 0 2006.252.07:59:59.60#ibcon#*mode == 0, iclass 21, count 0 2006.252.07:59:59.60#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.252.07:59:59.60#ibcon#[25=USB\r\n] 2006.252.07:59:59.60#ibcon#*before write, iclass 21, count 0 2006.252.07:59:59.60#ibcon#enter sib2, iclass 21, count 0 2006.252.07:59:59.60#ibcon#flushed, iclass 21, count 0 2006.252.07:59:59.60#ibcon#about to write, iclass 21, count 0 2006.252.07:59:59.60#ibcon#wrote, iclass 21, count 0 2006.252.07:59:59.60#ibcon#about to read 3, iclass 21, count 0 2006.252.07:59:59.63#ibcon#read 3, iclass 21, count 0 2006.252.07:59:59.63#ibcon#about to read 4, iclass 21, count 0 2006.252.07:59:59.63#ibcon#read 4, iclass 21, count 0 2006.252.07:59:59.63#ibcon#about to read 5, iclass 21, count 0 2006.252.07:59:59.63#ibcon#read 5, iclass 21, count 0 2006.252.07:59:59.63#ibcon#about to read 6, iclass 21, count 0 2006.252.07:59:59.63#ibcon#read 6, iclass 21, count 0 2006.252.07:59:59.63#ibcon#end of sib2, iclass 21, count 0 2006.252.07:59:59.63#ibcon#*after write, iclass 21, count 0 2006.252.07:59:59.63#ibcon#*before return 0, iclass 21, count 0 2006.252.07:59:59.63#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.252.07:59:59.63#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.252.07:59:59.63#ibcon#about to clear, iclass 21 cls_cnt 0 2006.252.07:59:59.63#ibcon#cleared, iclass 21 cls_cnt 0 2006.252.07:59:59.63$vc4f8/valo=6,772.99 2006.252.07:59:59.63#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.252.07:59:59.63#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.252.07:59:59.63#ibcon#ireg 17 cls_cnt 0 2006.252.07:59:59.63#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.252.07:59:59.63#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.252.07:59:59.63#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.252.07:59:59.63#ibcon#enter wrdev, iclass 23, count 0 2006.252.07:59:59.63#ibcon#first serial, iclass 23, count 0 2006.252.07:59:59.63#ibcon#enter sib2, iclass 23, count 0 2006.252.07:59:59.63#ibcon#flushed, iclass 23, count 0 2006.252.07:59:59.63#ibcon#about to write, iclass 23, count 0 2006.252.07:59:59.63#ibcon#wrote, iclass 23, count 0 2006.252.07:59:59.63#ibcon#about to read 3, iclass 23, count 0 2006.252.07:59:59.65#ibcon#read 3, iclass 23, count 0 2006.252.07:59:59.65#ibcon#about to read 4, iclass 23, count 0 2006.252.07:59:59.65#ibcon#read 4, iclass 23, count 0 2006.252.07:59:59.65#ibcon#about to read 5, iclass 23, count 0 2006.252.07:59:59.65#ibcon#read 5, iclass 23, count 0 2006.252.07:59:59.65#ibcon#about to read 6, iclass 23, count 0 2006.252.07:59:59.65#ibcon#read 6, iclass 23, count 0 2006.252.07:59:59.65#ibcon#end of sib2, iclass 23, count 0 2006.252.07:59:59.65#ibcon#*mode == 0, iclass 23, count 0 2006.252.07:59:59.65#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.252.07:59:59.66#ibcon#[26=FRQ=06,772.99\r\n] 2006.252.07:59:59.66#ibcon#*before write, iclass 23, count 0 2006.252.07:59:59.66#ibcon#enter sib2, iclass 23, count 0 2006.252.07:59:59.66#ibcon#flushed, iclass 23, count 0 2006.252.07:59:59.66#ibcon#about to write, iclass 23, count 0 2006.252.07:59:59.66#ibcon#wrote, iclass 23, count 0 2006.252.07:59:59.66#ibcon#about to read 3, iclass 23, count 0 2006.252.07:59:59.70#ibcon#read 3, iclass 23, count 0 2006.252.07:59:59.70#ibcon#about to read 4, iclass 23, count 0 2006.252.07:59:59.70#ibcon#read 4, iclass 23, count 0 2006.252.07:59:59.70#ibcon#about to read 5, iclass 23, count 0 2006.252.07:59:59.70#ibcon#read 5, iclass 23, count 0 2006.252.07:59:59.70#ibcon#about to read 6, iclass 23, count 0 2006.252.07:59:59.70#ibcon#read 6, iclass 23, count 0 2006.252.07:59:59.70#ibcon#end of sib2, iclass 23, count 0 2006.252.07:59:59.70#ibcon#*after write, iclass 23, count 0 2006.252.07:59:59.70#ibcon#*before return 0, iclass 23, count 0 2006.252.07:59:59.70#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.252.07:59:59.70#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.252.07:59:59.70#ibcon#about to clear, iclass 23 cls_cnt 0 2006.252.07:59:59.70#ibcon#cleared, iclass 23 cls_cnt 0 2006.252.07:59:59.70$vc4f8/va=6,7 2006.252.07:59:59.70#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.252.07:59:59.70#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.252.07:59:59.70#ibcon#ireg 11 cls_cnt 2 2006.252.07:59:59.70#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.252.07:59:59.75#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.252.07:59:59.75#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.252.07:59:59.75#ibcon#enter wrdev, iclass 25, count 2 2006.252.07:59:59.75#ibcon#first serial, iclass 25, count 2 2006.252.07:59:59.75#ibcon#enter sib2, iclass 25, count 2 2006.252.07:59:59.75#ibcon#flushed, iclass 25, count 2 2006.252.07:59:59.75#ibcon#about to write, iclass 25, count 2 2006.252.07:59:59.75#ibcon#wrote, iclass 25, count 2 2006.252.07:59:59.75#ibcon#about to read 3, iclass 25, count 2 2006.252.07:59:59.77#ibcon#read 3, iclass 25, count 2 2006.252.07:59:59.77#ibcon#about to read 4, iclass 25, count 2 2006.252.07:59:59.77#ibcon#read 4, iclass 25, count 2 2006.252.07:59:59.77#ibcon#about to read 5, iclass 25, count 2 2006.252.07:59:59.77#ibcon#read 5, iclass 25, count 2 2006.252.07:59:59.77#ibcon#about to read 6, iclass 25, count 2 2006.252.07:59:59.77#ibcon#read 6, iclass 25, count 2 2006.252.07:59:59.77#ibcon#end of sib2, iclass 25, count 2 2006.252.07:59:59.77#ibcon#*mode == 0, iclass 25, count 2 2006.252.07:59:59.77#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.252.07:59:59.77#ibcon#[25=AT06-07\r\n] 2006.252.07:59:59.77#ibcon#*before write, iclass 25, count 2 2006.252.07:59:59.77#ibcon#enter sib2, iclass 25, count 2 2006.252.07:59:59.77#ibcon#flushed, iclass 25, count 2 2006.252.07:59:59.77#ibcon#about to write, iclass 25, count 2 2006.252.07:59:59.77#ibcon#wrote, iclass 25, count 2 2006.252.07:59:59.77#ibcon#about to read 3, iclass 25, count 2 2006.252.07:59:59.80#ibcon#read 3, iclass 25, count 2 2006.252.07:59:59.80#ibcon#about to read 4, iclass 25, count 2 2006.252.07:59:59.80#ibcon#read 4, iclass 25, count 2 2006.252.07:59:59.80#ibcon#about to read 5, iclass 25, count 2 2006.252.07:59:59.80#ibcon#read 5, iclass 25, count 2 2006.252.07:59:59.80#ibcon#about to read 6, iclass 25, count 2 2006.252.07:59:59.80#ibcon#read 6, iclass 25, count 2 2006.252.07:59:59.80#ibcon#end of sib2, iclass 25, count 2 2006.252.07:59:59.80#ibcon#*after write, iclass 25, count 2 2006.252.07:59:59.80#ibcon#*before return 0, iclass 25, count 2 2006.252.07:59:59.80#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.252.07:59:59.80#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.252.07:59:59.80#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.252.07:59:59.80#ibcon#ireg 7 cls_cnt 0 2006.252.07:59:59.80#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.252.07:59:59.92#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.252.07:59:59.92#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.252.07:59:59.92#ibcon#enter wrdev, iclass 25, count 0 2006.252.07:59:59.92#ibcon#first serial, iclass 25, count 0 2006.252.07:59:59.92#ibcon#enter sib2, iclass 25, count 0 2006.252.07:59:59.92#ibcon#flushed, iclass 25, count 0 2006.252.07:59:59.92#ibcon#about to write, iclass 25, count 0 2006.252.07:59:59.92#ibcon#wrote, iclass 25, count 0 2006.252.07:59:59.92#ibcon#about to read 3, iclass 25, count 0 2006.252.07:59:59.94#ibcon#read 3, iclass 25, count 0 2006.252.07:59:59.94#ibcon#about to read 4, iclass 25, count 0 2006.252.07:59:59.94#ibcon#read 4, iclass 25, count 0 2006.252.07:59:59.94#ibcon#about to read 5, iclass 25, count 0 2006.252.07:59:59.94#ibcon#read 5, iclass 25, count 0 2006.252.07:59:59.94#ibcon#about to read 6, iclass 25, count 0 2006.252.07:59:59.94#ibcon#read 6, iclass 25, count 0 2006.252.07:59:59.94#ibcon#end of sib2, iclass 25, count 0 2006.252.07:59:59.94#ibcon#*mode == 0, iclass 25, count 0 2006.252.07:59:59.94#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.252.07:59:59.94#ibcon#[25=USB\r\n] 2006.252.07:59:59.94#ibcon#*before write, iclass 25, count 0 2006.252.07:59:59.94#ibcon#enter sib2, iclass 25, count 0 2006.252.07:59:59.94#ibcon#flushed, iclass 25, count 0 2006.252.07:59:59.94#ibcon#about to write, iclass 25, count 0 2006.252.07:59:59.94#ibcon#wrote, iclass 25, count 0 2006.252.07:59:59.94#ibcon#about to read 3, iclass 25, count 0 2006.252.07:59:59.97#ibcon#read 3, iclass 25, count 0 2006.252.07:59:59.97#ibcon#about to read 4, iclass 25, count 0 2006.252.07:59:59.97#ibcon#read 4, iclass 25, count 0 2006.252.07:59:59.97#ibcon#about to read 5, iclass 25, count 0 2006.252.07:59:59.97#ibcon#read 5, iclass 25, count 0 2006.252.07:59:59.97#ibcon#about to read 6, iclass 25, count 0 2006.252.07:59:59.97#ibcon#read 6, iclass 25, count 0 2006.252.07:59:59.97#ibcon#end of sib2, iclass 25, count 0 2006.252.07:59:59.97#ibcon#*after write, iclass 25, count 0 2006.252.07:59:59.97#ibcon#*before return 0, iclass 25, count 0 2006.252.07:59:59.97#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.252.07:59:59.97#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.252.07:59:59.97#ibcon#about to clear, iclass 25 cls_cnt 0 2006.252.07:59:59.97#ibcon#cleared, iclass 25 cls_cnt 0 2006.252.07:59:59.97$vc4f8/valo=7,832.99 2006.252.07:59:59.97#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.252.07:59:59.97#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.252.07:59:59.97#ibcon#ireg 17 cls_cnt 0 2006.252.07:59:59.97#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.252.07:59:59.97#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.252.07:59:59.97#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.252.07:59:59.97#ibcon#enter wrdev, iclass 27, count 0 2006.252.07:59:59.97#ibcon#first serial, iclass 27, count 0 2006.252.07:59:59.97#ibcon#enter sib2, iclass 27, count 0 2006.252.07:59:59.97#ibcon#flushed, iclass 27, count 0 2006.252.07:59:59.97#ibcon#about to write, iclass 27, count 0 2006.252.07:59:59.97#ibcon#wrote, iclass 27, count 0 2006.252.07:59:59.97#ibcon#about to read 3, iclass 27, count 0 2006.252.07:59:59.99#ibcon#read 3, iclass 27, count 0 2006.252.07:59:59.99#ibcon#about to read 4, iclass 27, count 0 2006.252.07:59:59.99#ibcon#read 4, iclass 27, count 0 2006.252.07:59:59.99#ibcon#about to read 5, iclass 27, count 0 2006.252.07:59:59.99#ibcon#read 5, iclass 27, count 0 2006.252.07:59:59.99#ibcon#about to read 6, iclass 27, count 0 2006.252.07:59:59.99#ibcon#read 6, iclass 27, count 0 2006.252.07:59:59.99#ibcon#end of sib2, iclass 27, count 0 2006.252.07:59:59.99#ibcon#*mode == 0, iclass 27, count 0 2006.252.07:59:59.99#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.252.07:59:59.99#ibcon#[26=FRQ=07,832.99\r\n] 2006.252.07:59:59.99#ibcon#*before write, iclass 27, count 0 2006.252.07:59:59.99#ibcon#enter sib2, iclass 27, count 0 2006.252.07:59:59.99#ibcon#flushed, iclass 27, count 0 2006.252.07:59:59.99#ibcon#about to write, iclass 27, count 0 2006.252.07:59:59.99#ibcon#wrote, iclass 27, count 0 2006.252.07:59:59.99#ibcon#about to read 3, iclass 27, count 0 2006.252.08:00:00.03#ibcon#read 3, iclass 27, count 0 2006.252.08:00:00.03#ibcon#about to read 4, iclass 27, count 0 2006.252.08:00:00.03#ibcon#read 4, iclass 27, count 0 2006.252.08:00:00.03#ibcon#about to read 5, iclass 27, count 0 2006.252.08:00:00.03#ibcon#read 5, iclass 27, count 0 2006.252.08:00:00.03#ibcon#about to read 6, iclass 27, count 0 2006.252.08:00:00.03#ibcon#read 6, iclass 27, count 0 2006.252.08:00:00.03#ibcon#end of sib2, iclass 27, count 0 2006.252.08:00:00.03#ibcon#*after write, iclass 27, count 0 2006.252.08:00:00.03#ibcon#*before return 0, iclass 27, count 0 2006.252.08:00:00.03#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.252.08:00:00.03#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.252.08:00:00.03#ibcon#about to clear, iclass 27 cls_cnt 0 2006.252.08:00:00.03#ibcon#cleared, iclass 27 cls_cnt 0 2006.252.08:00:00.03$vc4f8/va=7,7 2006.252.08:00:00.03#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.252.08:00:00.03#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.252.08:00:00.03#ibcon#ireg 11 cls_cnt 2 2006.252.08:00:00.03#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.252.08:00:00.09#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.252.08:00:00.09#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.252.08:00:00.09#ibcon#enter wrdev, iclass 29, count 2 2006.252.08:00:00.09#ibcon#first serial, iclass 29, count 2 2006.252.08:00:00.09#ibcon#enter sib2, iclass 29, count 2 2006.252.08:00:00.09#ibcon#flushed, iclass 29, count 2 2006.252.08:00:00.09#ibcon#about to write, iclass 29, count 2 2006.252.08:00:00.09#ibcon#wrote, iclass 29, count 2 2006.252.08:00:00.09#ibcon#about to read 3, iclass 29, count 2 2006.252.08:00:00.11#ibcon#read 3, iclass 29, count 2 2006.252.08:00:00.11#ibcon#about to read 4, iclass 29, count 2 2006.252.08:00:00.11#ibcon#read 4, iclass 29, count 2 2006.252.08:00:00.11#ibcon#about to read 5, iclass 29, count 2 2006.252.08:00:00.11#ibcon#read 5, iclass 29, count 2 2006.252.08:00:00.11#ibcon#about to read 6, iclass 29, count 2 2006.252.08:00:00.11#ibcon#read 6, iclass 29, count 2 2006.252.08:00:00.11#ibcon#end of sib2, iclass 29, count 2 2006.252.08:00:00.11#ibcon#*mode == 0, iclass 29, count 2 2006.252.08:00:00.11#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.252.08:00:00.11#ibcon#[25=AT07-07\r\n] 2006.252.08:00:00.11#ibcon#*before write, iclass 29, count 2 2006.252.08:00:00.11#ibcon#enter sib2, iclass 29, count 2 2006.252.08:00:00.11#ibcon#flushed, iclass 29, count 2 2006.252.08:00:00.11#ibcon#about to write, iclass 29, count 2 2006.252.08:00:00.11#ibcon#wrote, iclass 29, count 2 2006.252.08:00:00.11#ibcon#about to read 3, iclass 29, count 2 2006.252.08:00:00.14#ibcon#read 3, iclass 29, count 2 2006.252.08:00:00.14#ibcon#about to read 4, iclass 29, count 2 2006.252.08:00:00.14#ibcon#read 4, iclass 29, count 2 2006.252.08:00:00.14#ibcon#about to read 5, iclass 29, count 2 2006.252.08:00:00.14#ibcon#read 5, iclass 29, count 2 2006.252.08:00:00.14#ibcon#about to read 6, iclass 29, count 2 2006.252.08:00:00.14#ibcon#read 6, iclass 29, count 2 2006.252.08:00:00.14#ibcon#end of sib2, iclass 29, count 2 2006.252.08:00:00.14#ibcon#*after write, iclass 29, count 2 2006.252.08:00:00.14#ibcon#*before return 0, iclass 29, count 2 2006.252.08:00:00.14#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.252.08:00:00.14#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.252.08:00:00.14#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.252.08:00:00.14#ibcon#ireg 7 cls_cnt 0 2006.252.08:00:00.14#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.252.08:00:00.26#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.252.08:00:00.26#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.252.08:00:00.26#ibcon#enter wrdev, iclass 29, count 0 2006.252.08:00:00.26#ibcon#first serial, iclass 29, count 0 2006.252.08:00:00.26#ibcon#enter sib2, iclass 29, count 0 2006.252.08:00:00.26#ibcon#flushed, iclass 29, count 0 2006.252.08:00:00.26#ibcon#about to write, iclass 29, count 0 2006.252.08:00:00.26#ibcon#wrote, iclass 29, count 0 2006.252.08:00:00.26#ibcon#about to read 3, iclass 29, count 0 2006.252.08:00:00.28#ibcon#read 3, iclass 29, count 0 2006.252.08:00:00.28#ibcon#about to read 4, iclass 29, count 0 2006.252.08:00:00.28#ibcon#read 4, iclass 29, count 0 2006.252.08:00:00.28#ibcon#about to read 5, iclass 29, count 0 2006.252.08:00:00.28#ibcon#read 5, iclass 29, count 0 2006.252.08:00:00.28#ibcon#about to read 6, iclass 29, count 0 2006.252.08:00:00.28#ibcon#read 6, iclass 29, count 0 2006.252.08:00:00.28#ibcon#end of sib2, iclass 29, count 0 2006.252.08:00:00.28#ibcon#*mode == 0, iclass 29, count 0 2006.252.08:00:00.28#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.252.08:00:00.28#ibcon#[25=USB\r\n] 2006.252.08:00:00.28#ibcon#*before write, iclass 29, count 0 2006.252.08:00:00.28#ibcon#enter sib2, iclass 29, count 0 2006.252.08:00:00.28#ibcon#flushed, iclass 29, count 0 2006.252.08:00:00.28#ibcon#about to write, iclass 29, count 0 2006.252.08:00:00.28#ibcon#wrote, iclass 29, count 0 2006.252.08:00:00.28#ibcon#about to read 3, iclass 29, count 0 2006.252.08:00:00.31#ibcon#read 3, iclass 29, count 0 2006.252.08:00:00.31#ibcon#about to read 4, iclass 29, count 0 2006.252.08:00:00.31#ibcon#read 4, iclass 29, count 0 2006.252.08:00:00.31#ibcon#about to read 5, iclass 29, count 0 2006.252.08:00:00.31#ibcon#read 5, iclass 29, count 0 2006.252.08:00:00.31#ibcon#about to read 6, iclass 29, count 0 2006.252.08:00:00.31#ibcon#read 6, iclass 29, count 0 2006.252.08:00:00.31#ibcon#end of sib2, iclass 29, count 0 2006.252.08:00:00.31#ibcon#*after write, iclass 29, count 0 2006.252.08:00:00.31#ibcon#*before return 0, iclass 29, count 0 2006.252.08:00:00.31#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.252.08:00:00.31#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.252.08:00:00.31#ibcon#about to clear, iclass 29 cls_cnt 0 2006.252.08:00:00.31#ibcon#cleared, iclass 29 cls_cnt 0 2006.252.08:00:00.31$vc4f8/valo=8,852.99 2006.252.08:00:00.31#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.252.08:00:00.31#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.252.08:00:00.31#ibcon#ireg 17 cls_cnt 0 2006.252.08:00:00.31#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.252.08:00:00.31#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.252.08:00:00.31#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.252.08:00:00.31#ibcon#enter wrdev, iclass 31, count 0 2006.252.08:00:00.31#ibcon#first serial, iclass 31, count 0 2006.252.08:00:00.31#ibcon#enter sib2, iclass 31, count 0 2006.252.08:00:00.31#ibcon#flushed, iclass 31, count 0 2006.252.08:00:00.31#ibcon#about to write, iclass 31, count 0 2006.252.08:00:00.31#ibcon#wrote, iclass 31, count 0 2006.252.08:00:00.31#ibcon#about to read 3, iclass 31, count 0 2006.252.08:00:00.33#ibcon#read 3, iclass 31, count 0 2006.252.08:00:00.33#ibcon#about to read 4, iclass 31, count 0 2006.252.08:00:00.33#ibcon#read 4, iclass 31, count 0 2006.252.08:00:00.33#ibcon#about to read 5, iclass 31, count 0 2006.252.08:00:00.33#ibcon#read 5, iclass 31, count 0 2006.252.08:00:00.33#ibcon#about to read 6, iclass 31, count 0 2006.252.08:00:00.33#ibcon#read 6, iclass 31, count 0 2006.252.08:00:00.33#ibcon#end of sib2, iclass 31, count 0 2006.252.08:00:00.33#ibcon#*mode == 0, iclass 31, count 0 2006.252.08:00:00.33#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.252.08:00:00.33#ibcon#[26=FRQ=08,852.99\r\n] 2006.252.08:00:00.33#ibcon#*before write, iclass 31, count 0 2006.252.08:00:00.33#ibcon#enter sib2, iclass 31, count 0 2006.252.08:00:00.33#ibcon#flushed, iclass 31, count 0 2006.252.08:00:00.33#ibcon#about to write, iclass 31, count 0 2006.252.08:00:00.33#ibcon#wrote, iclass 31, count 0 2006.252.08:00:00.33#ibcon#about to read 3, iclass 31, count 0 2006.252.08:00:00.37#ibcon#read 3, iclass 31, count 0 2006.252.08:00:00.37#ibcon#about to read 4, iclass 31, count 0 2006.252.08:00:00.37#ibcon#read 4, iclass 31, count 0 2006.252.08:00:00.37#ibcon#about to read 5, iclass 31, count 0 2006.252.08:00:00.37#ibcon#read 5, iclass 31, count 0 2006.252.08:00:00.37#ibcon#about to read 6, iclass 31, count 0 2006.252.08:00:00.37#ibcon#read 6, iclass 31, count 0 2006.252.08:00:00.37#ibcon#end of sib2, iclass 31, count 0 2006.252.08:00:00.37#ibcon#*after write, iclass 31, count 0 2006.252.08:00:00.37#ibcon#*before return 0, iclass 31, count 0 2006.252.08:00:00.37#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.252.08:00:00.37#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.252.08:00:00.37#ibcon#about to clear, iclass 31 cls_cnt 0 2006.252.08:00:00.37#ibcon#cleared, iclass 31 cls_cnt 0 2006.252.08:00:00.37$vc4f8/va=8,7 2006.252.08:00:00.37#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.252.08:00:00.37#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.252.08:00:00.37#ibcon#ireg 11 cls_cnt 2 2006.252.08:00:00.37#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.252.08:00:00.43#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.252.08:00:00.43#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.252.08:00:00.43#ibcon#enter wrdev, iclass 33, count 2 2006.252.08:00:00.43#ibcon#first serial, iclass 33, count 2 2006.252.08:00:00.43#ibcon#enter sib2, iclass 33, count 2 2006.252.08:00:00.43#ibcon#flushed, iclass 33, count 2 2006.252.08:00:00.43#ibcon#about to write, iclass 33, count 2 2006.252.08:00:00.43#ibcon#wrote, iclass 33, count 2 2006.252.08:00:00.43#ibcon#about to read 3, iclass 33, count 2 2006.252.08:00:00.45#ibcon#read 3, iclass 33, count 2 2006.252.08:00:00.45#ibcon#about to read 4, iclass 33, count 2 2006.252.08:00:00.45#ibcon#read 4, iclass 33, count 2 2006.252.08:00:00.45#ibcon#about to read 5, iclass 33, count 2 2006.252.08:00:00.45#ibcon#read 5, iclass 33, count 2 2006.252.08:00:00.45#ibcon#about to read 6, iclass 33, count 2 2006.252.08:00:00.45#ibcon#read 6, iclass 33, count 2 2006.252.08:00:00.45#ibcon#end of sib2, iclass 33, count 2 2006.252.08:00:00.45#ibcon#*mode == 0, iclass 33, count 2 2006.252.08:00:00.45#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.252.08:00:00.45#ibcon#[25=AT08-07\r\n] 2006.252.08:00:00.45#ibcon#*before write, iclass 33, count 2 2006.252.08:00:00.45#ibcon#enter sib2, iclass 33, count 2 2006.252.08:00:00.45#ibcon#flushed, iclass 33, count 2 2006.252.08:00:00.45#ibcon#about to write, iclass 33, count 2 2006.252.08:00:00.45#ibcon#wrote, iclass 33, count 2 2006.252.08:00:00.45#ibcon#about to read 3, iclass 33, count 2 2006.252.08:00:00.48#ibcon#read 3, iclass 33, count 2 2006.252.08:00:00.48#ibcon#about to read 4, iclass 33, count 2 2006.252.08:00:00.48#ibcon#read 4, iclass 33, count 2 2006.252.08:00:00.48#ibcon#about to read 5, iclass 33, count 2 2006.252.08:00:00.48#ibcon#read 5, iclass 33, count 2 2006.252.08:00:00.48#ibcon#about to read 6, iclass 33, count 2 2006.252.08:00:00.48#ibcon#read 6, iclass 33, count 2 2006.252.08:00:00.48#ibcon#end of sib2, iclass 33, count 2 2006.252.08:00:00.48#ibcon#*after write, iclass 33, count 2 2006.252.08:00:00.48#ibcon#*before return 0, iclass 33, count 2 2006.252.08:00:00.48#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.252.08:00:00.48#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.252.08:00:00.48#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.252.08:00:00.48#ibcon#ireg 7 cls_cnt 0 2006.252.08:00:00.48#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.252.08:00:00.60#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.252.08:00:00.60#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.252.08:00:00.60#ibcon#enter wrdev, iclass 33, count 0 2006.252.08:00:00.60#ibcon#first serial, iclass 33, count 0 2006.252.08:00:00.60#ibcon#enter sib2, iclass 33, count 0 2006.252.08:00:00.60#ibcon#flushed, iclass 33, count 0 2006.252.08:00:00.60#ibcon#about to write, iclass 33, count 0 2006.252.08:00:00.60#ibcon#wrote, iclass 33, count 0 2006.252.08:00:00.60#ibcon#about to read 3, iclass 33, count 0 2006.252.08:00:00.62#ibcon#read 3, iclass 33, count 0 2006.252.08:00:00.62#ibcon#about to read 4, iclass 33, count 0 2006.252.08:00:00.62#ibcon#read 4, iclass 33, count 0 2006.252.08:00:00.62#ibcon#about to read 5, iclass 33, count 0 2006.252.08:00:00.62#ibcon#read 5, iclass 33, count 0 2006.252.08:00:00.62#ibcon#about to read 6, iclass 33, count 0 2006.252.08:00:00.62#ibcon#read 6, iclass 33, count 0 2006.252.08:00:00.62#ibcon#end of sib2, iclass 33, count 0 2006.252.08:00:00.62#ibcon#*mode == 0, iclass 33, count 0 2006.252.08:00:00.62#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.252.08:00:00.62#ibcon#[25=USB\r\n] 2006.252.08:00:00.62#ibcon#*before write, iclass 33, count 0 2006.252.08:00:00.62#ibcon#enter sib2, iclass 33, count 0 2006.252.08:00:00.62#ibcon#flushed, iclass 33, count 0 2006.252.08:00:00.62#ibcon#about to write, iclass 33, count 0 2006.252.08:00:00.62#ibcon#wrote, iclass 33, count 0 2006.252.08:00:00.62#ibcon#about to read 3, iclass 33, count 0 2006.252.08:00:00.65#ibcon#read 3, iclass 33, count 0 2006.252.08:00:00.65#ibcon#about to read 4, iclass 33, count 0 2006.252.08:00:00.65#ibcon#read 4, iclass 33, count 0 2006.252.08:00:00.65#ibcon#about to read 5, iclass 33, count 0 2006.252.08:00:00.65#ibcon#read 5, iclass 33, count 0 2006.252.08:00:00.65#ibcon#about to read 6, iclass 33, count 0 2006.252.08:00:00.65#ibcon#read 6, iclass 33, count 0 2006.252.08:00:00.65#ibcon#end of sib2, iclass 33, count 0 2006.252.08:00:00.65#ibcon#*after write, iclass 33, count 0 2006.252.08:00:00.65#ibcon#*before return 0, iclass 33, count 0 2006.252.08:00:00.65#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.252.08:00:00.65#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.252.08:00:00.65#ibcon#about to clear, iclass 33 cls_cnt 0 2006.252.08:00:00.65#ibcon#cleared, iclass 33 cls_cnt 0 2006.252.08:00:00.65$vc4f8/vblo=1,632.99 2006.252.08:00:00.65#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.252.08:00:00.65#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.252.08:00:00.65#ibcon#ireg 17 cls_cnt 0 2006.252.08:00:00.65#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.252.08:00:00.65#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.252.08:00:00.65#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.252.08:00:00.65#ibcon#enter wrdev, iclass 35, count 0 2006.252.08:00:00.65#ibcon#first serial, iclass 35, count 0 2006.252.08:00:00.65#ibcon#enter sib2, iclass 35, count 0 2006.252.08:00:00.65#ibcon#flushed, iclass 35, count 0 2006.252.08:00:00.65#ibcon#about to write, iclass 35, count 0 2006.252.08:00:00.65#ibcon#wrote, iclass 35, count 0 2006.252.08:00:00.65#ibcon#about to read 3, iclass 35, count 0 2006.252.08:00:00.67#ibcon#read 3, iclass 35, count 0 2006.252.08:00:00.67#ibcon#about to read 4, iclass 35, count 0 2006.252.08:00:00.67#ibcon#read 4, iclass 35, count 0 2006.252.08:00:00.67#ibcon#about to read 5, iclass 35, count 0 2006.252.08:00:00.67#ibcon#read 5, iclass 35, count 0 2006.252.08:00:00.67#ibcon#about to read 6, iclass 35, count 0 2006.252.08:00:00.67#ibcon#read 6, iclass 35, count 0 2006.252.08:00:00.67#ibcon#end of sib2, iclass 35, count 0 2006.252.08:00:00.67#ibcon#*mode == 0, iclass 35, count 0 2006.252.08:00:00.67#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.252.08:00:00.67#ibcon#[28=FRQ=01,632.99\r\n] 2006.252.08:00:00.67#ibcon#*before write, iclass 35, count 0 2006.252.08:00:00.67#ibcon#enter sib2, iclass 35, count 0 2006.252.08:00:00.67#ibcon#flushed, iclass 35, count 0 2006.252.08:00:00.67#ibcon#about to write, iclass 35, count 0 2006.252.08:00:00.67#ibcon#wrote, iclass 35, count 0 2006.252.08:00:00.67#ibcon#about to read 3, iclass 35, count 0 2006.252.08:00:00.71#ibcon#read 3, iclass 35, count 0 2006.252.08:00:00.71#ibcon#about to read 4, iclass 35, count 0 2006.252.08:00:00.71#ibcon#read 4, iclass 35, count 0 2006.252.08:00:00.71#ibcon#about to read 5, iclass 35, count 0 2006.252.08:00:00.71#ibcon#read 5, iclass 35, count 0 2006.252.08:00:00.71#ibcon#about to read 6, iclass 35, count 0 2006.252.08:00:00.71#ibcon#read 6, iclass 35, count 0 2006.252.08:00:00.71#ibcon#end of sib2, iclass 35, count 0 2006.252.08:00:00.71#ibcon#*after write, iclass 35, count 0 2006.252.08:00:00.71#ibcon#*before return 0, iclass 35, count 0 2006.252.08:00:00.71#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.252.08:00:00.71#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.252.08:00:00.71#ibcon#about to clear, iclass 35 cls_cnt 0 2006.252.08:00:00.71#ibcon#cleared, iclass 35 cls_cnt 0 2006.252.08:00:00.71$vc4f8/vb=1,4 2006.252.08:00:00.71#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.252.08:00:00.71#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.252.08:00:00.71#ibcon#ireg 11 cls_cnt 2 2006.252.08:00:00.71#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.252.08:00:00.71#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.252.08:00:00.71#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.252.08:00:00.71#ibcon#enter wrdev, iclass 37, count 2 2006.252.08:00:00.71#ibcon#first serial, iclass 37, count 2 2006.252.08:00:00.71#ibcon#enter sib2, iclass 37, count 2 2006.252.08:00:00.71#ibcon#flushed, iclass 37, count 2 2006.252.08:00:00.71#ibcon#about to write, iclass 37, count 2 2006.252.08:00:00.71#ibcon#wrote, iclass 37, count 2 2006.252.08:00:00.71#ibcon#about to read 3, iclass 37, count 2 2006.252.08:00:00.73#ibcon#read 3, iclass 37, count 2 2006.252.08:00:00.73#ibcon#about to read 4, iclass 37, count 2 2006.252.08:00:00.73#ibcon#read 4, iclass 37, count 2 2006.252.08:00:00.73#ibcon#about to read 5, iclass 37, count 2 2006.252.08:00:00.73#ibcon#read 5, iclass 37, count 2 2006.252.08:00:00.73#ibcon#about to read 6, iclass 37, count 2 2006.252.08:00:00.73#ibcon#read 6, iclass 37, count 2 2006.252.08:00:00.73#ibcon#end of sib2, iclass 37, count 2 2006.252.08:00:00.73#ibcon#*mode == 0, iclass 37, count 2 2006.252.08:00:00.73#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.252.08:00:00.73#ibcon#[27=AT01-04\r\n] 2006.252.08:00:00.73#ibcon#*before write, iclass 37, count 2 2006.252.08:00:00.73#ibcon#enter sib2, iclass 37, count 2 2006.252.08:00:00.73#ibcon#flushed, iclass 37, count 2 2006.252.08:00:00.73#ibcon#about to write, iclass 37, count 2 2006.252.08:00:00.73#ibcon#wrote, iclass 37, count 2 2006.252.08:00:00.73#ibcon#about to read 3, iclass 37, count 2 2006.252.08:00:00.76#ibcon#read 3, iclass 37, count 2 2006.252.08:00:00.76#ibcon#about to read 4, iclass 37, count 2 2006.252.08:00:00.76#ibcon#read 4, iclass 37, count 2 2006.252.08:00:00.76#ibcon#about to read 5, iclass 37, count 2 2006.252.08:00:00.76#ibcon#read 5, iclass 37, count 2 2006.252.08:00:00.76#ibcon#about to read 6, iclass 37, count 2 2006.252.08:00:00.76#ibcon#read 6, iclass 37, count 2 2006.252.08:00:00.76#ibcon#end of sib2, iclass 37, count 2 2006.252.08:00:00.76#ibcon#*after write, iclass 37, count 2 2006.252.08:00:00.76#ibcon#*before return 0, iclass 37, count 2 2006.252.08:00:00.76#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.252.08:00:00.76#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.252.08:00:00.76#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.252.08:00:00.76#ibcon#ireg 7 cls_cnt 0 2006.252.08:00:00.76#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.252.08:00:00.88#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.252.08:00:00.88#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.252.08:00:00.88#ibcon#enter wrdev, iclass 37, count 0 2006.252.08:00:00.88#ibcon#first serial, iclass 37, count 0 2006.252.08:00:00.88#ibcon#enter sib2, iclass 37, count 0 2006.252.08:00:00.88#ibcon#flushed, iclass 37, count 0 2006.252.08:00:00.88#ibcon#about to write, iclass 37, count 0 2006.252.08:00:00.88#ibcon#wrote, iclass 37, count 0 2006.252.08:00:00.88#ibcon#about to read 3, iclass 37, count 0 2006.252.08:00:00.90#ibcon#read 3, iclass 37, count 0 2006.252.08:00:00.90#ibcon#about to read 4, iclass 37, count 0 2006.252.08:00:00.90#ibcon#read 4, iclass 37, count 0 2006.252.08:00:00.90#ibcon#about to read 5, iclass 37, count 0 2006.252.08:00:00.90#ibcon#read 5, iclass 37, count 0 2006.252.08:00:00.90#ibcon#about to read 6, iclass 37, count 0 2006.252.08:00:00.90#ibcon#read 6, iclass 37, count 0 2006.252.08:00:00.90#ibcon#end of sib2, iclass 37, count 0 2006.252.08:00:00.90#ibcon#*mode == 0, iclass 37, count 0 2006.252.08:00:00.90#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.252.08:00:00.90#ibcon#[27=USB\r\n] 2006.252.08:00:00.90#ibcon#*before write, iclass 37, count 0 2006.252.08:00:00.90#ibcon#enter sib2, iclass 37, count 0 2006.252.08:00:00.90#ibcon#flushed, iclass 37, count 0 2006.252.08:00:00.90#ibcon#about to write, iclass 37, count 0 2006.252.08:00:00.90#ibcon#wrote, iclass 37, count 0 2006.252.08:00:00.90#ibcon#about to read 3, iclass 37, count 0 2006.252.08:00:00.93#ibcon#read 3, iclass 37, count 0 2006.252.08:00:00.93#ibcon#about to read 4, iclass 37, count 0 2006.252.08:00:00.93#ibcon#read 4, iclass 37, count 0 2006.252.08:00:00.93#ibcon#about to read 5, iclass 37, count 0 2006.252.08:00:00.93#ibcon#read 5, iclass 37, count 0 2006.252.08:00:00.93#ibcon#about to read 6, iclass 37, count 0 2006.252.08:00:00.93#ibcon#read 6, iclass 37, count 0 2006.252.08:00:00.93#ibcon#end of sib2, iclass 37, count 0 2006.252.08:00:00.93#ibcon#*after write, iclass 37, count 0 2006.252.08:00:00.93#ibcon#*before return 0, iclass 37, count 0 2006.252.08:00:00.93#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.252.08:00:00.93#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.252.08:00:00.93#ibcon#about to clear, iclass 37 cls_cnt 0 2006.252.08:00:00.93#ibcon#cleared, iclass 37 cls_cnt 0 2006.252.08:00:00.93$vc4f8/vblo=2,640.99 2006.252.08:00:00.93#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.252.08:00:00.93#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.252.08:00:00.93#ibcon#ireg 17 cls_cnt 0 2006.252.08:00:00.93#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.252.08:00:00.93#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.252.08:00:00.93#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.252.08:00:00.93#ibcon#enter wrdev, iclass 39, count 0 2006.252.08:00:00.93#ibcon#first serial, iclass 39, count 0 2006.252.08:00:00.93#ibcon#enter sib2, iclass 39, count 0 2006.252.08:00:00.93#ibcon#flushed, iclass 39, count 0 2006.252.08:00:00.93#ibcon#about to write, iclass 39, count 0 2006.252.08:00:00.93#ibcon#wrote, iclass 39, count 0 2006.252.08:00:00.93#ibcon#about to read 3, iclass 39, count 0 2006.252.08:00:00.95#ibcon#read 3, iclass 39, count 0 2006.252.08:00:00.95#ibcon#about to read 4, iclass 39, count 0 2006.252.08:00:00.95#ibcon#read 4, iclass 39, count 0 2006.252.08:00:00.95#ibcon#about to read 5, iclass 39, count 0 2006.252.08:00:00.95#ibcon#read 5, iclass 39, count 0 2006.252.08:00:00.95#ibcon#about to read 6, iclass 39, count 0 2006.252.08:00:00.95#ibcon#read 6, iclass 39, count 0 2006.252.08:00:00.95#ibcon#end of sib2, iclass 39, count 0 2006.252.08:00:00.95#ibcon#*mode == 0, iclass 39, count 0 2006.252.08:00:00.95#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.252.08:00:00.95#ibcon#[28=FRQ=02,640.99\r\n] 2006.252.08:00:00.95#ibcon#*before write, iclass 39, count 0 2006.252.08:00:00.95#ibcon#enter sib2, iclass 39, count 0 2006.252.08:00:00.95#ibcon#flushed, iclass 39, count 0 2006.252.08:00:00.95#ibcon#about to write, iclass 39, count 0 2006.252.08:00:00.95#ibcon#wrote, iclass 39, count 0 2006.252.08:00:00.95#ibcon#about to read 3, iclass 39, count 0 2006.252.08:00:00.99#ibcon#read 3, iclass 39, count 0 2006.252.08:00:00.99#ibcon#about to read 4, iclass 39, count 0 2006.252.08:00:00.99#ibcon#read 4, iclass 39, count 0 2006.252.08:00:00.99#ibcon#about to read 5, iclass 39, count 0 2006.252.08:00:00.99#ibcon#read 5, iclass 39, count 0 2006.252.08:00:00.99#ibcon#about to read 6, iclass 39, count 0 2006.252.08:00:00.99#ibcon#read 6, iclass 39, count 0 2006.252.08:00:00.99#ibcon#end of sib2, iclass 39, count 0 2006.252.08:00:00.99#ibcon#*after write, iclass 39, count 0 2006.252.08:00:00.99#ibcon#*before return 0, iclass 39, count 0 2006.252.08:00:00.99#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.252.08:00:00.99#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.252.08:00:00.99#ibcon#about to clear, iclass 39 cls_cnt 0 2006.252.08:00:00.99#ibcon#cleared, iclass 39 cls_cnt 0 2006.252.08:00:00.99$vc4f8/vb=2,5 2006.252.08:00:00.99#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.252.08:00:00.99#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.252.08:00:00.99#ibcon#ireg 11 cls_cnt 2 2006.252.08:00:00.99#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.252.08:00:01.05#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.252.08:00:01.05#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.252.08:00:01.05#ibcon#enter wrdev, iclass 3, count 2 2006.252.08:00:01.05#ibcon#first serial, iclass 3, count 2 2006.252.08:00:01.05#ibcon#enter sib2, iclass 3, count 2 2006.252.08:00:01.05#ibcon#flushed, iclass 3, count 2 2006.252.08:00:01.05#ibcon#about to write, iclass 3, count 2 2006.252.08:00:01.05#ibcon#wrote, iclass 3, count 2 2006.252.08:00:01.05#ibcon#about to read 3, iclass 3, count 2 2006.252.08:00:01.07#ibcon#read 3, iclass 3, count 2 2006.252.08:00:01.07#ibcon#about to read 4, iclass 3, count 2 2006.252.08:00:01.07#ibcon#read 4, iclass 3, count 2 2006.252.08:00:01.07#ibcon#about to read 5, iclass 3, count 2 2006.252.08:00:01.07#ibcon#read 5, iclass 3, count 2 2006.252.08:00:01.07#ibcon#about to read 6, iclass 3, count 2 2006.252.08:00:01.07#ibcon#read 6, iclass 3, count 2 2006.252.08:00:01.07#ibcon#end of sib2, iclass 3, count 2 2006.252.08:00:01.07#ibcon#*mode == 0, iclass 3, count 2 2006.252.08:00:01.07#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.252.08:00:01.07#ibcon#[27=AT02-05\r\n] 2006.252.08:00:01.07#ibcon#*before write, iclass 3, count 2 2006.252.08:00:01.07#ibcon#enter sib2, iclass 3, count 2 2006.252.08:00:01.07#ibcon#flushed, iclass 3, count 2 2006.252.08:00:01.07#ibcon#about to write, iclass 3, count 2 2006.252.08:00:01.07#ibcon#wrote, iclass 3, count 2 2006.252.08:00:01.07#ibcon#about to read 3, iclass 3, count 2 2006.252.08:00:01.10#ibcon#read 3, iclass 3, count 2 2006.252.08:00:01.10#ibcon#about to read 4, iclass 3, count 2 2006.252.08:00:01.10#ibcon#read 4, iclass 3, count 2 2006.252.08:00:01.10#ibcon#about to read 5, iclass 3, count 2 2006.252.08:00:01.10#ibcon#read 5, iclass 3, count 2 2006.252.08:00:01.10#ibcon#about to read 6, iclass 3, count 2 2006.252.08:00:01.10#ibcon#read 6, iclass 3, count 2 2006.252.08:00:01.10#ibcon#end of sib2, iclass 3, count 2 2006.252.08:00:01.10#ibcon#*after write, iclass 3, count 2 2006.252.08:00:01.10#ibcon#*before return 0, iclass 3, count 2 2006.252.08:00:01.10#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.252.08:00:01.10#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.252.08:00:01.10#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.252.08:00:01.10#ibcon#ireg 7 cls_cnt 0 2006.252.08:00:01.10#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.252.08:00:01.22#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.252.08:00:01.22#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.252.08:00:01.22#ibcon#enter wrdev, iclass 3, count 0 2006.252.08:00:01.22#ibcon#first serial, iclass 3, count 0 2006.252.08:00:01.22#ibcon#enter sib2, iclass 3, count 0 2006.252.08:00:01.22#ibcon#flushed, iclass 3, count 0 2006.252.08:00:01.22#ibcon#about to write, iclass 3, count 0 2006.252.08:00:01.22#ibcon#wrote, iclass 3, count 0 2006.252.08:00:01.22#ibcon#about to read 3, iclass 3, count 0 2006.252.08:00:01.25#ibcon#read 3, iclass 3, count 0 2006.252.08:00:01.25#ibcon#about to read 4, iclass 3, count 0 2006.252.08:00:01.25#ibcon#read 4, iclass 3, count 0 2006.252.08:00:01.25#ibcon#about to read 5, iclass 3, count 0 2006.252.08:00:01.25#ibcon#read 5, iclass 3, count 0 2006.252.08:00:01.25#ibcon#about to read 6, iclass 3, count 0 2006.252.08:00:01.25#ibcon#read 6, iclass 3, count 0 2006.252.08:00:01.25#ibcon#end of sib2, iclass 3, count 0 2006.252.08:00:01.25#ibcon#*mode == 0, iclass 3, count 0 2006.252.08:00:01.25#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.252.08:00:01.25#ibcon#[27=USB\r\n] 2006.252.08:00:01.25#ibcon#*before write, iclass 3, count 0 2006.252.08:00:01.25#ibcon#enter sib2, iclass 3, count 0 2006.252.08:00:01.25#ibcon#flushed, iclass 3, count 0 2006.252.08:00:01.25#ibcon#about to write, iclass 3, count 0 2006.252.08:00:01.25#ibcon#wrote, iclass 3, count 0 2006.252.08:00:01.25#ibcon#about to read 3, iclass 3, count 0 2006.252.08:00:01.28#ibcon#read 3, iclass 3, count 0 2006.252.08:00:01.28#ibcon#about to read 4, iclass 3, count 0 2006.252.08:00:01.28#ibcon#read 4, iclass 3, count 0 2006.252.08:00:01.28#ibcon#about to read 5, iclass 3, count 0 2006.252.08:00:01.28#ibcon#read 5, iclass 3, count 0 2006.252.08:00:01.28#ibcon#about to read 6, iclass 3, count 0 2006.252.08:00:01.28#ibcon#read 6, iclass 3, count 0 2006.252.08:00:01.28#ibcon#end of sib2, iclass 3, count 0 2006.252.08:00:01.28#ibcon#*after write, iclass 3, count 0 2006.252.08:00:01.28#ibcon#*before return 0, iclass 3, count 0 2006.252.08:00:01.28#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.252.08:00:01.28#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.252.08:00:01.28#ibcon#about to clear, iclass 3 cls_cnt 0 2006.252.08:00:01.28#ibcon#cleared, iclass 3 cls_cnt 0 2006.252.08:00:01.28$vc4f8/vblo=3,656.99 2006.252.08:00:01.28#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.252.08:00:01.28#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.252.08:00:01.28#ibcon#ireg 17 cls_cnt 0 2006.252.08:00:01.28#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.252.08:00:01.28#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.252.08:00:01.28#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.252.08:00:01.28#ibcon#enter wrdev, iclass 5, count 0 2006.252.08:00:01.28#ibcon#first serial, iclass 5, count 0 2006.252.08:00:01.28#ibcon#enter sib2, iclass 5, count 0 2006.252.08:00:01.28#ibcon#flushed, iclass 5, count 0 2006.252.08:00:01.28#ibcon#about to write, iclass 5, count 0 2006.252.08:00:01.28#ibcon#wrote, iclass 5, count 0 2006.252.08:00:01.28#ibcon#about to read 3, iclass 5, count 0 2006.252.08:00:01.30#ibcon#read 3, iclass 5, count 0 2006.252.08:00:01.30#ibcon#about to read 4, iclass 5, count 0 2006.252.08:00:01.30#ibcon#read 4, iclass 5, count 0 2006.252.08:00:01.30#ibcon#about to read 5, iclass 5, count 0 2006.252.08:00:01.30#ibcon#read 5, iclass 5, count 0 2006.252.08:00:01.30#ibcon#about to read 6, iclass 5, count 0 2006.252.08:00:01.30#ibcon#read 6, iclass 5, count 0 2006.252.08:00:01.30#ibcon#end of sib2, iclass 5, count 0 2006.252.08:00:01.30#ibcon#*mode == 0, iclass 5, count 0 2006.252.08:00:01.30#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.252.08:00:01.30#ibcon#[28=FRQ=03,656.99\r\n] 2006.252.08:00:01.30#ibcon#*before write, iclass 5, count 0 2006.252.08:00:01.30#ibcon#enter sib2, iclass 5, count 0 2006.252.08:00:01.30#ibcon#flushed, iclass 5, count 0 2006.252.08:00:01.30#ibcon#about to write, iclass 5, count 0 2006.252.08:00:01.30#ibcon#wrote, iclass 5, count 0 2006.252.08:00:01.30#ibcon#about to read 3, iclass 5, count 0 2006.252.08:00:01.34#ibcon#read 3, iclass 5, count 0 2006.252.08:00:01.34#ibcon#about to read 4, iclass 5, count 0 2006.252.08:00:01.34#ibcon#read 4, iclass 5, count 0 2006.252.08:00:01.34#ibcon#about to read 5, iclass 5, count 0 2006.252.08:00:01.34#ibcon#read 5, iclass 5, count 0 2006.252.08:00:01.34#ibcon#about to read 6, iclass 5, count 0 2006.252.08:00:01.34#ibcon#read 6, iclass 5, count 0 2006.252.08:00:01.34#ibcon#end of sib2, iclass 5, count 0 2006.252.08:00:01.34#ibcon#*after write, iclass 5, count 0 2006.252.08:00:01.34#ibcon#*before return 0, iclass 5, count 0 2006.252.08:00:01.34#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.252.08:00:01.34#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.252.08:00:01.34#ibcon#about to clear, iclass 5 cls_cnt 0 2006.252.08:00:01.34#ibcon#cleared, iclass 5 cls_cnt 0 2006.252.08:00:01.34$vc4f8/vb=3,4 2006.252.08:00:01.34#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.252.08:00:01.34#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.252.08:00:01.34#ibcon#ireg 11 cls_cnt 2 2006.252.08:00:01.34#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.252.08:00:01.40#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.252.08:00:01.40#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.252.08:00:01.40#ibcon#enter wrdev, iclass 7, count 2 2006.252.08:00:01.40#ibcon#first serial, iclass 7, count 2 2006.252.08:00:01.40#ibcon#enter sib2, iclass 7, count 2 2006.252.08:00:01.40#ibcon#flushed, iclass 7, count 2 2006.252.08:00:01.40#ibcon#about to write, iclass 7, count 2 2006.252.08:00:01.40#ibcon#wrote, iclass 7, count 2 2006.252.08:00:01.40#ibcon#about to read 3, iclass 7, count 2 2006.252.08:00:01.42#ibcon#read 3, iclass 7, count 2 2006.252.08:00:01.42#ibcon#about to read 4, iclass 7, count 2 2006.252.08:00:01.42#ibcon#read 4, iclass 7, count 2 2006.252.08:00:01.42#ibcon#about to read 5, iclass 7, count 2 2006.252.08:00:01.42#ibcon#read 5, iclass 7, count 2 2006.252.08:00:01.42#ibcon#about to read 6, iclass 7, count 2 2006.252.08:00:01.42#ibcon#read 6, iclass 7, count 2 2006.252.08:00:01.42#ibcon#end of sib2, iclass 7, count 2 2006.252.08:00:01.42#ibcon#*mode == 0, iclass 7, count 2 2006.252.08:00:01.42#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.252.08:00:01.42#ibcon#[27=AT03-04\r\n] 2006.252.08:00:01.42#ibcon#*before write, iclass 7, count 2 2006.252.08:00:01.42#ibcon#enter sib2, iclass 7, count 2 2006.252.08:00:01.42#ibcon#flushed, iclass 7, count 2 2006.252.08:00:01.42#ibcon#about to write, iclass 7, count 2 2006.252.08:00:01.42#ibcon#wrote, iclass 7, count 2 2006.252.08:00:01.42#ibcon#about to read 3, iclass 7, count 2 2006.252.08:00:01.45#ibcon#read 3, iclass 7, count 2 2006.252.08:00:01.45#ibcon#about to read 4, iclass 7, count 2 2006.252.08:00:01.45#ibcon#read 4, iclass 7, count 2 2006.252.08:00:01.45#ibcon#about to read 5, iclass 7, count 2 2006.252.08:00:01.45#ibcon#read 5, iclass 7, count 2 2006.252.08:00:01.45#ibcon#about to read 6, iclass 7, count 2 2006.252.08:00:01.45#ibcon#read 6, iclass 7, count 2 2006.252.08:00:01.45#ibcon#end of sib2, iclass 7, count 2 2006.252.08:00:01.45#ibcon#*after write, iclass 7, count 2 2006.252.08:00:01.45#ibcon#*before return 0, iclass 7, count 2 2006.252.08:00:01.45#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.252.08:00:01.45#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.252.08:00:01.45#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.252.08:00:01.45#ibcon#ireg 7 cls_cnt 0 2006.252.08:00:01.45#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.252.08:00:01.57#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.252.08:00:01.57#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.252.08:00:01.57#ibcon#enter wrdev, iclass 7, count 0 2006.252.08:00:01.57#ibcon#first serial, iclass 7, count 0 2006.252.08:00:01.57#ibcon#enter sib2, iclass 7, count 0 2006.252.08:00:01.57#ibcon#flushed, iclass 7, count 0 2006.252.08:00:01.57#ibcon#about to write, iclass 7, count 0 2006.252.08:00:01.57#ibcon#wrote, iclass 7, count 0 2006.252.08:00:01.57#ibcon#about to read 3, iclass 7, count 0 2006.252.08:00:01.59#ibcon#read 3, iclass 7, count 0 2006.252.08:00:01.59#ibcon#about to read 4, iclass 7, count 0 2006.252.08:00:01.59#ibcon#read 4, iclass 7, count 0 2006.252.08:00:01.59#ibcon#about to read 5, iclass 7, count 0 2006.252.08:00:01.59#ibcon#read 5, iclass 7, count 0 2006.252.08:00:01.59#ibcon#about to read 6, iclass 7, count 0 2006.252.08:00:01.59#ibcon#read 6, iclass 7, count 0 2006.252.08:00:01.59#ibcon#end of sib2, iclass 7, count 0 2006.252.08:00:01.59#ibcon#*mode == 0, iclass 7, count 0 2006.252.08:00:01.59#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.252.08:00:01.59#ibcon#[27=USB\r\n] 2006.252.08:00:01.59#ibcon#*before write, iclass 7, count 0 2006.252.08:00:01.59#ibcon#enter sib2, iclass 7, count 0 2006.252.08:00:01.59#ibcon#flushed, iclass 7, count 0 2006.252.08:00:01.59#ibcon#about to write, iclass 7, count 0 2006.252.08:00:01.59#ibcon#wrote, iclass 7, count 0 2006.252.08:00:01.59#ibcon#about to read 3, iclass 7, count 0 2006.252.08:00:01.62#ibcon#read 3, iclass 7, count 0 2006.252.08:00:01.62#ibcon#about to read 4, iclass 7, count 0 2006.252.08:00:01.62#ibcon#read 4, iclass 7, count 0 2006.252.08:00:01.62#ibcon#about to read 5, iclass 7, count 0 2006.252.08:00:01.62#ibcon#read 5, iclass 7, count 0 2006.252.08:00:01.62#ibcon#about to read 6, iclass 7, count 0 2006.252.08:00:01.62#ibcon#read 6, iclass 7, count 0 2006.252.08:00:01.62#ibcon#end of sib2, iclass 7, count 0 2006.252.08:00:01.62#ibcon#*after write, iclass 7, count 0 2006.252.08:00:01.62#ibcon#*before return 0, iclass 7, count 0 2006.252.08:00:01.62#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.252.08:00:01.62#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.252.08:00:01.62#ibcon#about to clear, iclass 7 cls_cnt 0 2006.252.08:00:01.62#ibcon#cleared, iclass 7 cls_cnt 0 2006.252.08:00:01.62$vc4f8/vblo=4,712.99 2006.252.08:00:01.62#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.252.08:00:01.62#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.252.08:00:01.62#ibcon#ireg 17 cls_cnt 0 2006.252.08:00:01.62#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.252.08:00:01.62#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.252.08:00:01.62#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.252.08:00:01.62#ibcon#enter wrdev, iclass 11, count 0 2006.252.08:00:01.62#ibcon#first serial, iclass 11, count 0 2006.252.08:00:01.62#ibcon#enter sib2, iclass 11, count 0 2006.252.08:00:01.62#ibcon#flushed, iclass 11, count 0 2006.252.08:00:01.62#ibcon#about to write, iclass 11, count 0 2006.252.08:00:01.62#ibcon#wrote, iclass 11, count 0 2006.252.08:00:01.62#ibcon#about to read 3, iclass 11, count 0 2006.252.08:00:01.64#ibcon#read 3, iclass 11, count 0 2006.252.08:00:01.64#ibcon#about to read 4, iclass 11, count 0 2006.252.08:00:01.64#ibcon#read 4, iclass 11, count 0 2006.252.08:00:01.64#ibcon#about to read 5, iclass 11, count 0 2006.252.08:00:01.64#ibcon#read 5, iclass 11, count 0 2006.252.08:00:01.64#ibcon#about to read 6, iclass 11, count 0 2006.252.08:00:01.64#ibcon#read 6, iclass 11, count 0 2006.252.08:00:01.64#ibcon#end of sib2, iclass 11, count 0 2006.252.08:00:01.64#ibcon#*mode == 0, iclass 11, count 0 2006.252.08:00:01.64#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.252.08:00:01.64#ibcon#[28=FRQ=04,712.99\r\n] 2006.252.08:00:01.64#ibcon#*before write, iclass 11, count 0 2006.252.08:00:01.64#ibcon#enter sib2, iclass 11, count 0 2006.252.08:00:01.64#ibcon#flushed, iclass 11, count 0 2006.252.08:00:01.64#ibcon#about to write, iclass 11, count 0 2006.252.08:00:01.64#ibcon#wrote, iclass 11, count 0 2006.252.08:00:01.64#ibcon#about to read 3, iclass 11, count 0 2006.252.08:00:01.68#ibcon#read 3, iclass 11, count 0 2006.252.08:00:01.68#ibcon#about to read 4, iclass 11, count 0 2006.252.08:00:01.68#ibcon#read 4, iclass 11, count 0 2006.252.08:00:01.68#ibcon#about to read 5, iclass 11, count 0 2006.252.08:00:01.68#ibcon#read 5, iclass 11, count 0 2006.252.08:00:01.68#ibcon#about to read 6, iclass 11, count 0 2006.252.08:00:01.68#ibcon#read 6, iclass 11, count 0 2006.252.08:00:01.68#ibcon#end of sib2, iclass 11, count 0 2006.252.08:00:01.68#ibcon#*after write, iclass 11, count 0 2006.252.08:00:01.68#ibcon#*before return 0, iclass 11, count 0 2006.252.08:00:01.68#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.252.08:00:01.68#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.252.08:00:01.68#ibcon#about to clear, iclass 11 cls_cnt 0 2006.252.08:00:01.68#ibcon#cleared, iclass 11 cls_cnt 0 2006.252.08:00:01.68$vc4f8/vb=4,4 2006.252.08:00:01.68#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.252.08:00:01.68#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.252.08:00:01.68#ibcon#ireg 11 cls_cnt 2 2006.252.08:00:01.68#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.252.08:00:01.74#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.252.08:00:01.74#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.252.08:00:01.74#ibcon#enter wrdev, iclass 13, count 2 2006.252.08:00:01.74#ibcon#first serial, iclass 13, count 2 2006.252.08:00:01.74#ibcon#enter sib2, iclass 13, count 2 2006.252.08:00:01.74#ibcon#flushed, iclass 13, count 2 2006.252.08:00:01.74#ibcon#about to write, iclass 13, count 2 2006.252.08:00:01.74#ibcon#wrote, iclass 13, count 2 2006.252.08:00:01.74#ibcon#about to read 3, iclass 13, count 2 2006.252.08:00:01.76#ibcon#read 3, iclass 13, count 2 2006.252.08:00:01.76#ibcon#about to read 4, iclass 13, count 2 2006.252.08:00:01.76#ibcon#read 4, iclass 13, count 2 2006.252.08:00:01.76#ibcon#about to read 5, iclass 13, count 2 2006.252.08:00:01.76#ibcon#read 5, iclass 13, count 2 2006.252.08:00:01.76#ibcon#about to read 6, iclass 13, count 2 2006.252.08:00:01.76#ibcon#read 6, iclass 13, count 2 2006.252.08:00:01.76#ibcon#end of sib2, iclass 13, count 2 2006.252.08:00:01.76#ibcon#*mode == 0, iclass 13, count 2 2006.252.08:00:01.76#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.252.08:00:01.76#ibcon#[27=AT04-04\r\n] 2006.252.08:00:01.76#ibcon#*before write, iclass 13, count 2 2006.252.08:00:01.76#ibcon#enter sib2, iclass 13, count 2 2006.252.08:00:01.76#ibcon#flushed, iclass 13, count 2 2006.252.08:00:01.76#ibcon#about to write, iclass 13, count 2 2006.252.08:00:01.76#ibcon#wrote, iclass 13, count 2 2006.252.08:00:01.76#ibcon#about to read 3, iclass 13, count 2 2006.252.08:00:01.79#ibcon#read 3, iclass 13, count 2 2006.252.08:00:01.79#ibcon#about to read 4, iclass 13, count 2 2006.252.08:00:01.79#ibcon#read 4, iclass 13, count 2 2006.252.08:00:01.79#ibcon#about to read 5, iclass 13, count 2 2006.252.08:00:01.79#ibcon#read 5, iclass 13, count 2 2006.252.08:00:01.79#ibcon#about to read 6, iclass 13, count 2 2006.252.08:00:01.79#ibcon#read 6, iclass 13, count 2 2006.252.08:00:01.79#ibcon#end of sib2, iclass 13, count 2 2006.252.08:00:01.79#ibcon#*after write, iclass 13, count 2 2006.252.08:00:01.79#ibcon#*before return 0, iclass 13, count 2 2006.252.08:00:01.79#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.252.08:00:01.79#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.252.08:00:01.79#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.252.08:00:01.79#ibcon#ireg 7 cls_cnt 0 2006.252.08:00:01.79#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.252.08:00:01.91#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.252.08:00:01.91#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.252.08:00:01.91#ibcon#enter wrdev, iclass 13, count 0 2006.252.08:00:01.91#ibcon#first serial, iclass 13, count 0 2006.252.08:00:01.91#ibcon#enter sib2, iclass 13, count 0 2006.252.08:00:01.91#ibcon#flushed, iclass 13, count 0 2006.252.08:00:01.91#ibcon#about to write, iclass 13, count 0 2006.252.08:00:01.91#ibcon#wrote, iclass 13, count 0 2006.252.08:00:01.91#ibcon#about to read 3, iclass 13, count 0 2006.252.08:00:01.93#ibcon#read 3, iclass 13, count 0 2006.252.08:00:01.93#ibcon#about to read 4, iclass 13, count 0 2006.252.08:00:01.93#ibcon#read 4, iclass 13, count 0 2006.252.08:00:01.93#ibcon#about to read 5, iclass 13, count 0 2006.252.08:00:01.93#ibcon#read 5, iclass 13, count 0 2006.252.08:00:01.93#ibcon#about to read 6, iclass 13, count 0 2006.252.08:00:01.93#ibcon#read 6, iclass 13, count 0 2006.252.08:00:01.93#ibcon#end of sib2, iclass 13, count 0 2006.252.08:00:01.93#ibcon#*mode == 0, iclass 13, count 0 2006.252.08:00:01.93#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.252.08:00:01.93#ibcon#[27=USB\r\n] 2006.252.08:00:01.93#ibcon#*before write, iclass 13, count 0 2006.252.08:00:01.93#ibcon#enter sib2, iclass 13, count 0 2006.252.08:00:01.93#ibcon#flushed, iclass 13, count 0 2006.252.08:00:01.93#ibcon#about to write, iclass 13, count 0 2006.252.08:00:01.93#ibcon#wrote, iclass 13, count 0 2006.252.08:00:01.93#ibcon#about to read 3, iclass 13, count 0 2006.252.08:00:01.96#ibcon#read 3, iclass 13, count 0 2006.252.08:00:01.96#ibcon#about to read 4, iclass 13, count 0 2006.252.08:00:01.96#ibcon#read 4, iclass 13, count 0 2006.252.08:00:01.96#ibcon#about to read 5, iclass 13, count 0 2006.252.08:00:01.96#ibcon#read 5, iclass 13, count 0 2006.252.08:00:01.96#ibcon#about to read 6, iclass 13, count 0 2006.252.08:00:01.96#ibcon#read 6, iclass 13, count 0 2006.252.08:00:01.96#ibcon#end of sib2, iclass 13, count 0 2006.252.08:00:01.96#ibcon#*after write, iclass 13, count 0 2006.252.08:00:01.96#ibcon#*before return 0, iclass 13, count 0 2006.252.08:00:01.96#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.252.08:00:01.96#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.252.08:00:01.96#ibcon#about to clear, iclass 13 cls_cnt 0 2006.252.08:00:01.96#ibcon#cleared, iclass 13 cls_cnt 0 2006.252.08:00:01.96$vc4f8/vblo=5,744.99 2006.252.08:00:01.96#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.252.08:00:01.96#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.252.08:00:01.96#ibcon#ireg 17 cls_cnt 0 2006.252.08:00:01.96#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.252.08:00:01.96#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.252.08:00:01.96#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.252.08:00:01.96#ibcon#enter wrdev, iclass 15, count 0 2006.252.08:00:01.96#ibcon#first serial, iclass 15, count 0 2006.252.08:00:01.96#ibcon#enter sib2, iclass 15, count 0 2006.252.08:00:01.96#ibcon#flushed, iclass 15, count 0 2006.252.08:00:01.96#ibcon#about to write, iclass 15, count 0 2006.252.08:00:01.96#ibcon#wrote, iclass 15, count 0 2006.252.08:00:01.96#ibcon#about to read 3, iclass 15, count 0 2006.252.08:00:01.98#ibcon#read 3, iclass 15, count 0 2006.252.08:00:01.98#ibcon#about to read 4, iclass 15, count 0 2006.252.08:00:01.98#ibcon#read 4, iclass 15, count 0 2006.252.08:00:01.98#ibcon#about to read 5, iclass 15, count 0 2006.252.08:00:01.98#ibcon#read 5, iclass 15, count 0 2006.252.08:00:01.98#ibcon#about to read 6, iclass 15, count 0 2006.252.08:00:01.98#ibcon#read 6, iclass 15, count 0 2006.252.08:00:01.98#ibcon#end of sib2, iclass 15, count 0 2006.252.08:00:01.98#ibcon#*mode == 0, iclass 15, count 0 2006.252.08:00:01.98#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.252.08:00:01.98#ibcon#[28=FRQ=05,744.99\r\n] 2006.252.08:00:01.98#ibcon#*before write, iclass 15, count 0 2006.252.08:00:01.98#ibcon#enter sib2, iclass 15, count 0 2006.252.08:00:01.98#ibcon#flushed, iclass 15, count 0 2006.252.08:00:01.98#ibcon#about to write, iclass 15, count 0 2006.252.08:00:01.98#ibcon#wrote, iclass 15, count 0 2006.252.08:00:01.98#ibcon#about to read 3, iclass 15, count 0 2006.252.08:00:02.02#ibcon#read 3, iclass 15, count 0 2006.252.08:00:02.02#ibcon#about to read 4, iclass 15, count 0 2006.252.08:00:02.02#ibcon#read 4, iclass 15, count 0 2006.252.08:00:02.02#ibcon#about to read 5, iclass 15, count 0 2006.252.08:00:02.02#ibcon#read 5, iclass 15, count 0 2006.252.08:00:02.02#ibcon#about to read 6, iclass 15, count 0 2006.252.08:00:02.02#ibcon#read 6, iclass 15, count 0 2006.252.08:00:02.02#ibcon#end of sib2, iclass 15, count 0 2006.252.08:00:02.02#ibcon#*after write, iclass 15, count 0 2006.252.08:00:02.02#ibcon#*before return 0, iclass 15, count 0 2006.252.08:00:02.02#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.252.08:00:02.02#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.252.08:00:02.02#ibcon#about to clear, iclass 15 cls_cnt 0 2006.252.08:00:02.02#ibcon#cleared, iclass 15 cls_cnt 0 2006.252.08:00:02.02$vc4f8/vb=5,4 2006.252.08:00:02.02#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.252.08:00:02.02#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.252.08:00:02.02#ibcon#ireg 11 cls_cnt 2 2006.252.08:00:02.02#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.252.08:00:02.08#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.252.08:00:02.08#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.252.08:00:02.08#ibcon#enter wrdev, iclass 17, count 2 2006.252.08:00:02.08#ibcon#first serial, iclass 17, count 2 2006.252.08:00:02.08#ibcon#enter sib2, iclass 17, count 2 2006.252.08:00:02.08#ibcon#flushed, iclass 17, count 2 2006.252.08:00:02.08#ibcon#about to write, iclass 17, count 2 2006.252.08:00:02.08#ibcon#wrote, iclass 17, count 2 2006.252.08:00:02.08#ibcon#about to read 3, iclass 17, count 2 2006.252.08:00:02.10#ibcon#read 3, iclass 17, count 2 2006.252.08:00:02.10#ibcon#about to read 4, iclass 17, count 2 2006.252.08:00:02.10#ibcon#read 4, iclass 17, count 2 2006.252.08:00:02.10#ibcon#about to read 5, iclass 17, count 2 2006.252.08:00:02.10#ibcon#read 5, iclass 17, count 2 2006.252.08:00:02.10#ibcon#about to read 6, iclass 17, count 2 2006.252.08:00:02.10#ibcon#read 6, iclass 17, count 2 2006.252.08:00:02.10#ibcon#end of sib2, iclass 17, count 2 2006.252.08:00:02.10#ibcon#*mode == 0, iclass 17, count 2 2006.252.08:00:02.10#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.252.08:00:02.10#ibcon#[27=AT05-04\r\n] 2006.252.08:00:02.10#ibcon#*before write, iclass 17, count 2 2006.252.08:00:02.10#ibcon#enter sib2, iclass 17, count 2 2006.252.08:00:02.10#ibcon#flushed, iclass 17, count 2 2006.252.08:00:02.10#ibcon#about to write, iclass 17, count 2 2006.252.08:00:02.10#ibcon#wrote, iclass 17, count 2 2006.252.08:00:02.10#ibcon#about to read 3, iclass 17, count 2 2006.252.08:00:02.13#ibcon#read 3, iclass 17, count 2 2006.252.08:00:02.13#ibcon#about to read 4, iclass 17, count 2 2006.252.08:00:02.13#ibcon#read 4, iclass 17, count 2 2006.252.08:00:02.13#ibcon#about to read 5, iclass 17, count 2 2006.252.08:00:02.13#ibcon#read 5, iclass 17, count 2 2006.252.08:00:02.13#ibcon#about to read 6, iclass 17, count 2 2006.252.08:00:02.13#ibcon#read 6, iclass 17, count 2 2006.252.08:00:02.13#ibcon#end of sib2, iclass 17, count 2 2006.252.08:00:02.13#ibcon#*after write, iclass 17, count 2 2006.252.08:00:02.13#ibcon#*before return 0, iclass 17, count 2 2006.252.08:00:02.13#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.252.08:00:02.13#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.252.08:00:02.13#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.252.08:00:02.13#ibcon#ireg 7 cls_cnt 0 2006.252.08:00:02.13#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.252.08:00:02.25#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.252.08:00:02.25#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.252.08:00:02.25#ibcon#enter wrdev, iclass 17, count 0 2006.252.08:00:02.25#ibcon#first serial, iclass 17, count 0 2006.252.08:00:02.25#ibcon#enter sib2, iclass 17, count 0 2006.252.08:00:02.25#ibcon#flushed, iclass 17, count 0 2006.252.08:00:02.25#ibcon#about to write, iclass 17, count 0 2006.252.08:00:02.25#ibcon#wrote, iclass 17, count 0 2006.252.08:00:02.25#ibcon#about to read 3, iclass 17, count 0 2006.252.08:00:02.27#ibcon#read 3, iclass 17, count 0 2006.252.08:00:02.27#ibcon#about to read 4, iclass 17, count 0 2006.252.08:00:02.27#ibcon#read 4, iclass 17, count 0 2006.252.08:00:02.27#ibcon#about to read 5, iclass 17, count 0 2006.252.08:00:02.27#ibcon#read 5, iclass 17, count 0 2006.252.08:00:02.27#ibcon#about to read 6, iclass 17, count 0 2006.252.08:00:02.27#ibcon#read 6, iclass 17, count 0 2006.252.08:00:02.27#ibcon#end of sib2, iclass 17, count 0 2006.252.08:00:02.27#ibcon#*mode == 0, iclass 17, count 0 2006.252.08:00:02.27#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.252.08:00:02.27#ibcon#[27=USB\r\n] 2006.252.08:00:02.27#ibcon#*before write, iclass 17, count 0 2006.252.08:00:02.27#ibcon#enter sib2, iclass 17, count 0 2006.252.08:00:02.27#ibcon#flushed, iclass 17, count 0 2006.252.08:00:02.27#ibcon#about to write, iclass 17, count 0 2006.252.08:00:02.27#ibcon#wrote, iclass 17, count 0 2006.252.08:00:02.27#ibcon#about to read 3, iclass 17, count 0 2006.252.08:00:02.30#ibcon#read 3, iclass 17, count 0 2006.252.08:00:02.30#ibcon#about to read 4, iclass 17, count 0 2006.252.08:00:02.30#ibcon#read 4, iclass 17, count 0 2006.252.08:00:02.30#ibcon#about to read 5, iclass 17, count 0 2006.252.08:00:02.30#ibcon#read 5, iclass 17, count 0 2006.252.08:00:02.30#ibcon#about to read 6, iclass 17, count 0 2006.252.08:00:02.30#ibcon#read 6, iclass 17, count 0 2006.252.08:00:02.30#ibcon#end of sib2, iclass 17, count 0 2006.252.08:00:02.30#ibcon#*after write, iclass 17, count 0 2006.252.08:00:02.30#ibcon#*before return 0, iclass 17, count 0 2006.252.08:00:02.30#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.252.08:00:02.30#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.252.08:00:02.30#ibcon#about to clear, iclass 17 cls_cnt 0 2006.252.08:00:02.30#ibcon#cleared, iclass 17 cls_cnt 0 2006.252.08:00:02.30$vc4f8/vblo=6,752.99 2006.252.08:00:02.30#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.252.08:00:02.30#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.252.08:00:02.30#ibcon#ireg 17 cls_cnt 0 2006.252.08:00:02.30#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.252.08:00:02.30#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.252.08:00:02.30#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.252.08:00:02.30#ibcon#enter wrdev, iclass 19, count 0 2006.252.08:00:02.30#ibcon#first serial, iclass 19, count 0 2006.252.08:00:02.30#ibcon#enter sib2, iclass 19, count 0 2006.252.08:00:02.30#ibcon#flushed, iclass 19, count 0 2006.252.08:00:02.30#ibcon#about to write, iclass 19, count 0 2006.252.08:00:02.30#ibcon#wrote, iclass 19, count 0 2006.252.08:00:02.30#ibcon#about to read 3, iclass 19, count 0 2006.252.08:00:02.33#ibcon#read 3, iclass 19, count 0 2006.252.08:00:02.33#ibcon#about to read 4, iclass 19, count 0 2006.252.08:00:02.33#ibcon#read 4, iclass 19, count 0 2006.252.08:00:02.33#ibcon#about to read 5, iclass 19, count 0 2006.252.08:00:02.33#ibcon#read 5, iclass 19, count 0 2006.252.08:00:02.33#ibcon#about to read 6, iclass 19, count 0 2006.252.08:00:02.33#ibcon#read 6, iclass 19, count 0 2006.252.08:00:02.33#ibcon#end of sib2, iclass 19, count 0 2006.252.08:00:02.33#ibcon#*mode == 0, iclass 19, count 0 2006.252.08:00:02.33#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.252.08:00:02.33#ibcon#[28=FRQ=06,752.99\r\n] 2006.252.08:00:02.33#ibcon#*before write, iclass 19, count 0 2006.252.08:00:02.33#ibcon#enter sib2, iclass 19, count 0 2006.252.08:00:02.33#ibcon#flushed, iclass 19, count 0 2006.252.08:00:02.33#ibcon#about to write, iclass 19, count 0 2006.252.08:00:02.33#ibcon#wrote, iclass 19, count 0 2006.252.08:00:02.33#ibcon#about to read 3, iclass 19, count 0 2006.252.08:00:02.37#ibcon#read 3, iclass 19, count 0 2006.252.08:00:02.37#ibcon#about to read 4, iclass 19, count 0 2006.252.08:00:02.37#ibcon#read 4, iclass 19, count 0 2006.252.08:00:02.37#ibcon#about to read 5, iclass 19, count 0 2006.252.08:00:02.37#ibcon#read 5, iclass 19, count 0 2006.252.08:00:02.37#ibcon#about to read 6, iclass 19, count 0 2006.252.08:00:02.37#ibcon#read 6, iclass 19, count 0 2006.252.08:00:02.37#ibcon#end of sib2, iclass 19, count 0 2006.252.08:00:02.37#ibcon#*after write, iclass 19, count 0 2006.252.08:00:02.37#ibcon#*before return 0, iclass 19, count 0 2006.252.08:00:02.37#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.252.08:00:02.37#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.252.08:00:02.37#ibcon#about to clear, iclass 19 cls_cnt 0 2006.252.08:00:02.37#ibcon#cleared, iclass 19 cls_cnt 0 2006.252.08:00:02.37$vc4f8/vb=6,4 2006.252.08:00:02.37#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.252.08:00:02.37#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.252.08:00:02.37#ibcon#ireg 11 cls_cnt 2 2006.252.08:00:02.37#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.252.08:00:02.42#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.252.08:00:02.42#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.252.08:00:02.42#ibcon#enter wrdev, iclass 21, count 2 2006.252.08:00:02.42#ibcon#first serial, iclass 21, count 2 2006.252.08:00:02.42#ibcon#enter sib2, iclass 21, count 2 2006.252.08:00:02.42#ibcon#flushed, iclass 21, count 2 2006.252.08:00:02.42#ibcon#about to write, iclass 21, count 2 2006.252.08:00:02.42#ibcon#wrote, iclass 21, count 2 2006.252.08:00:02.42#ibcon#about to read 3, iclass 21, count 2 2006.252.08:00:02.44#ibcon#read 3, iclass 21, count 2 2006.252.08:00:02.44#ibcon#about to read 4, iclass 21, count 2 2006.252.08:00:02.44#ibcon#read 4, iclass 21, count 2 2006.252.08:00:02.44#ibcon#about to read 5, iclass 21, count 2 2006.252.08:00:02.44#ibcon#read 5, iclass 21, count 2 2006.252.08:00:02.44#ibcon#about to read 6, iclass 21, count 2 2006.252.08:00:02.44#ibcon#read 6, iclass 21, count 2 2006.252.08:00:02.44#ibcon#end of sib2, iclass 21, count 2 2006.252.08:00:02.44#ibcon#*mode == 0, iclass 21, count 2 2006.252.08:00:02.44#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.252.08:00:02.44#ibcon#[27=AT06-04\r\n] 2006.252.08:00:02.44#ibcon#*before write, iclass 21, count 2 2006.252.08:00:02.44#ibcon#enter sib2, iclass 21, count 2 2006.252.08:00:02.44#ibcon#flushed, iclass 21, count 2 2006.252.08:00:02.44#ibcon#about to write, iclass 21, count 2 2006.252.08:00:02.44#ibcon#wrote, iclass 21, count 2 2006.252.08:00:02.44#ibcon#about to read 3, iclass 21, count 2 2006.252.08:00:02.47#ibcon#read 3, iclass 21, count 2 2006.252.08:00:02.47#ibcon#about to read 4, iclass 21, count 2 2006.252.08:00:02.47#ibcon#read 4, iclass 21, count 2 2006.252.08:00:02.47#ibcon#about to read 5, iclass 21, count 2 2006.252.08:00:02.47#ibcon#read 5, iclass 21, count 2 2006.252.08:00:02.47#ibcon#about to read 6, iclass 21, count 2 2006.252.08:00:02.47#ibcon#read 6, iclass 21, count 2 2006.252.08:00:02.47#ibcon#end of sib2, iclass 21, count 2 2006.252.08:00:02.47#ibcon#*after write, iclass 21, count 2 2006.252.08:00:02.47#ibcon#*before return 0, iclass 21, count 2 2006.252.08:00:02.47#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.252.08:00:02.47#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.252.08:00:02.47#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.252.08:00:02.47#ibcon#ireg 7 cls_cnt 0 2006.252.08:00:02.47#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.252.08:00:02.59#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.252.08:00:02.59#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.252.08:00:02.59#ibcon#enter wrdev, iclass 21, count 0 2006.252.08:00:02.59#ibcon#first serial, iclass 21, count 0 2006.252.08:00:02.59#ibcon#enter sib2, iclass 21, count 0 2006.252.08:00:02.59#ibcon#flushed, iclass 21, count 0 2006.252.08:00:02.59#ibcon#about to write, iclass 21, count 0 2006.252.08:00:02.59#ibcon#wrote, iclass 21, count 0 2006.252.08:00:02.59#ibcon#about to read 3, iclass 21, count 0 2006.252.08:00:02.61#ibcon#read 3, iclass 21, count 0 2006.252.08:00:02.61#ibcon#about to read 4, iclass 21, count 0 2006.252.08:00:02.61#ibcon#read 4, iclass 21, count 0 2006.252.08:00:02.61#ibcon#about to read 5, iclass 21, count 0 2006.252.08:00:02.61#ibcon#read 5, iclass 21, count 0 2006.252.08:00:02.61#ibcon#about to read 6, iclass 21, count 0 2006.252.08:00:02.61#ibcon#read 6, iclass 21, count 0 2006.252.08:00:02.61#ibcon#end of sib2, iclass 21, count 0 2006.252.08:00:02.61#ibcon#*mode == 0, iclass 21, count 0 2006.252.08:00:02.61#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.252.08:00:02.61#ibcon#[27=USB\r\n] 2006.252.08:00:02.61#ibcon#*before write, iclass 21, count 0 2006.252.08:00:02.61#ibcon#enter sib2, iclass 21, count 0 2006.252.08:00:02.61#ibcon#flushed, iclass 21, count 0 2006.252.08:00:02.61#ibcon#about to write, iclass 21, count 0 2006.252.08:00:02.61#ibcon#wrote, iclass 21, count 0 2006.252.08:00:02.61#ibcon#about to read 3, iclass 21, count 0 2006.252.08:00:02.64#ibcon#read 3, iclass 21, count 0 2006.252.08:00:02.64#ibcon#about to read 4, iclass 21, count 0 2006.252.08:00:02.64#ibcon#read 4, iclass 21, count 0 2006.252.08:00:02.64#ibcon#about to read 5, iclass 21, count 0 2006.252.08:00:02.64#ibcon#read 5, iclass 21, count 0 2006.252.08:00:02.64#ibcon#about to read 6, iclass 21, count 0 2006.252.08:00:02.64#ibcon#read 6, iclass 21, count 0 2006.252.08:00:02.64#ibcon#end of sib2, iclass 21, count 0 2006.252.08:00:02.64#ibcon#*after write, iclass 21, count 0 2006.252.08:00:02.64#ibcon#*before return 0, iclass 21, count 0 2006.252.08:00:02.64#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.252.08:00:02.64#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.252.08:00:02.64#ibcon#about to clear, iclass 21 cls_cnt 0 2006.252.08:00:02.64#ibcon#cleared, iclass 21 cls_cnt 0 2006.252.08:00:02.64$vc4f8/vabw=wide 2006.252.08:00:02.64#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.252.08:00:02.64#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.252.08:00:02.64#ibcon#ireg 8 cls_cnt 0 2006.252.08:00:02.64#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.252.08:00:02.64#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.252.08:00:02.64#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.252.08:00:02.64#ibcon#enter wrdev, iclass 23, count 0 2006.252.08:00:02.64#ibcon#first serial, iclass 23, count 0 2006.252.08:00:02.64#ibcon#enter sib2, iclass 23, count 0 2006.252.08:00:02.64#ibcon#flushed, iclass 23, count 0 2006.252.08:00:02.64#ibcon#about to write, iclass 23, count 0 2006.252.08:00:02.64#ibcon#wrote, iclass 23, count 0 2006.252.08:00:02.64#ibcon#about to read 3, iclass 23, count 0 2006.252.08:00:02.66#ibcon#read 3, iclass 23, count 0 2006.252.08:00:02.66#ibcon#about to read 4, iclass 23, count 0 2006.252.08:00:02.66#ibcon#read 4, iclass 23, count 0 2006.252.08:00:02.66#ibcon#about to read 5, iclass 23, count 0 2006.252.08:00:02.66#ibcon#read 5, iclass 23, count 0 2006.252.08:00:02.66#ibcon#about to read 6, iclass 23, count 0 2006.252.08:00:02.66#ibcon#read 6, iclass 23, count 0 2006.252.08:00:02.66#ibcon#end of sib2, iclass 23, count 0 2006.252.08:00:02.66#ibcon#*mode == 0, iclass 23, count 0 2006.252.08:00:02.66#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.252.08:00:02.66#ibcon#[25=BW32\r\n] 2006.252.08:00:02.66#ibcon#*before write, iclass 23, count 0 2006.252.08:00:02.66#ibcon#enter sib2, iclass 23, count 0 2006.252.08:00:02.66#ibcon#flushed, iclass 23, count 0 2006.252.08:00:02.66#ibcon#about to write, iclass 23, count 0 2006.252.08:00:02.66#ibcon#wrote, iclass 23, count 0 2006.252.08:00:02.66#ibcon#about to read 3, iclass 23, count 0 2006.252.08:00:02.69#ibcon#read 3, iclass 23, count 0 2006.252.08:00:02.69#ibcon#about to read 4, iclass 23, count 0 2006.252.08:00:02.69#ibcon#read 4, iclass 23, count 0 2006.252.08:00:02.69#ibcon#about to read 5, iclass 23, count 0 2006.252.08:00:02.69#ibcon#read 5, iclass 23, count 0 2006.252.08:00:02.69#ibcon#about to read 6, iclass 23, count 0 2006.252.08:00:02.69#ibcon#read 6, iclass 23, count 0 2006.252.08:00:02.69#ibcon#end of sib2, iclass 23, count 0 2006.252.08:00:02.69#ibcon#*after write, iclass 23, count 0 2006.252.08:00:02.69#ibcon#*before return 0, iclass 23, count 0 2006.252.08:00:02.69#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.252.08:00:02.69#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.252.08:00:02.69#ibcon#about to clear, iclass 23 cls_cnt 0 2006.252.08:00:02.69#ibcon#cleared, iclass 23 cls_cnt 0 2006.252.08:00:02.69$vc4f8/vbbw=wide 2006.252.08:00:02.69#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.252.08:00:02.69#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.252.08:00:02.69#ibcon#ireg 8 cls_cnt 0 2006.252.08:00:02.69#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.252.08:00:02.76#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.252.08:00:02.76#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.252.08:00:02.76#ibcon#enter wrdev, iclass 25, count 0 2006.252.08:00:02.76#ibcon#first serial, iclass 25, count 0 2006.252.08:00:02.76#ibcon#enter sib2, iclass 25, count 0 2006.252.08:00:02.76#ibcon#flushed, iclass 25, count 0 2006.252.08:00:02.76#ibcon#about to write, iclass 25, count 0 2006.252.08:00:02.76#ibcon#wrote, iclass 25, count 0 2006.252.08:00:02.76#ibcon#about to read 3, iclass 25, count 0 2006.252.08:00:02.78#ibcon#read 3, iclass 25, count 0 2006.252.08:00:02.78#ibcon#about to read 4, iclass 25, count 0 2006.252.08:00:02.78#ibcon#read 4, iclass 25, count 0 2006.252.08:00:02.78#ibcon#about to read 5, iclass 25, count 0 2006.252.08:00:02.78#ibcon#read 5, iclass 25, count 0 2006.252.08:00:02.78#ibcon#about to read 6, iclass 25, count 0 2006.252.08:00:02.78#ibcon#read 6, iclass 25, count 0 2006.252.08:00:02.78#ibcon#end of sib2, iclass 25, count 0 2006.252.08:00:02.78#ibcon#*mode == 0, iclass 25, count 0 2006.252.08:00:02.78#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.252.08:00:02.78#ibcon#[27=BW32\r\n] 2006.252.08:00:02.78#ibcon#*before write, iclass 25, count 0 2006.252.08:00:02.78#ibcon#enter sib2, iclass 25, count 0 2006.252.08:00:02.78#ibcon#flushed, iclass 25, count 0 2006.252.08:00:02.78#ibcon#about to write, iclass 25, count 0 2006.252.08:00:02.78#ibcon#wrote, iclass 25, count 0 2006.252.08:00:02.78#ibcon#about to read 3, iclass 25, count 0 2006.252.08:00:02.81#ibcon#read 3, iclass 25, count 0 2006.252.08:00:02.81#ibcon#about to read 4, iclass 25, count 0 2006.252.08:00:02.81#ibcon#read 4, iclass 25, count 0 2006.252.08:00:02.81#ibcon#about to read 5, iclass 25, count 0 2006.252.08:00:02.81#ibcon#read 5, iclass 25, count 0 2006.252.08:00:02.81#ibcon#about to read 6, iclass 25, count 0 2006.252.08:00:02.81#ibcon#read 6, iclass 25, count 0 2006.252.08:00:02.81#ibcon#end of sib2, iclass 25, count 0 2006.252.08:00:02.81#ibcon#*after write, iclass 25, count 0 2006.252.08:00:02.81#ibcon#*before return 0, iclass 25, count 0 2006.252.08:00:02.81#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.252.08:00:02.81#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.252.08:00:02.81#ibcon#about to clear, iclass 25 cls_cnt 0 2006.252.08:00:02.81#ibcon#cleared, iclass 25 cls_cnt 0 2006.252.08:00:02.81$4f8m12a/ifd4f 2006.252.08:00:02.81$ifd4f/lo= 2006.252.08:00:02.81$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.252.08:00:02.81$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.252.08:00:02.81$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.252.08:00:02.81$ifd4f/patch= 2006.252.08:00:02.81$ifd4f/patch=lo1,a1,a2,a3,a4 2006.252.08:00:02.81$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.252.08:00:02.81$ifd4f/patch=lo3,a5,a6,a7,a8 2006.252.08:00:02.81$4f8m12a/"form=m,16.000,1:2 2006.252.08:00:02.81$4f8m12a/"tpicd 2006.252.08:00:02.81$4f8m12a/echo=off 2006.252.08:00:02.81$4f8m12a/xlog=off 2006.252.08:00:02.81:!2006.252.08:00:40 2006.252.08:00:25.14#trakl#Source acquired 2006.252.08:00:27.14#flagr#flagr/antenna,acquired 2006.252.08:00:40.00:preob 2006.252.08:00:40.14/onsource/TRACKING 2006.252.08:00:40.14:!2006.252.08:00:50 2006.252.08:00:50.00:data_valid=on 2006.252.08:00:50.00:midob 2006.252.08:00:51.14/onsource/TRACKING 2006.252.08:00:51.14/wx/27.34,1011.2,90 2006.252.08:00:51.27/cable/+6.4112E-03 2006.252.08:00:52.36/va/01,08,usb,yes,32,34 2006.252.08:00:52.36/va/02,07,usb,yes,32,34 2006.252.08:00:52.36/va/03,06,usb,yes,34,34 2006.252.08:00:52.36/va/04,07,usb,yes,33,36 2006.252.08:00:52.36/va/05,07,usb,yes,36,38 2006.252.08:00:52.36/va/06,07,usb,yes,31,31 2006.252.08:00:52.36/va/07,07,usb,yes,31,31 2006.252.08:00:52.36/va/08,07,usb,yes,34,33 2006.252.08:00:52.59/valo/01,532.99,yes,locked 2006.252.08:00:52.59/valo/02,572.99,yes,locked 2006.252.08:00:52.59/valo/03,672.99,yes,locked 2006.252.08:00:52.59/valo/04,832.99,yes,locked 2006.252.08:00:52.59/valo/05,652.99,yes,locked 2006.252.08:00:52.59/valo/06,772.99,yes,locked 2006.252.08:00:52.59/valo/07,832.99,yes,locked 2006.252.08:00:52.59/valo/08,852.99,yes,locked 2006.252.08:00:53.68/vb/01,04,usb,yes,30,29 2006.252.08:00:53.68/vb/02,05,usb,yes,28,30 2006.252.08:00:53.68/vb/03,04,usb,yes,28,32 2006.252.08:00:53.68/vb/04,04,usb,yes,29,29 2006.252.08:00:53.68/vb/05,04,usb,yes,28,32 2006.252.08:00:53.68/vb/06,04,usb,yes,29,31 2006.252.08:00:53.68/vb/07,04,usb,yes,31,31 2006.252.08:00:53.68/vb/08,04,usb,yes,28,32 2006.252.08:00:53.92/vblo/01,632.99,yes,locked 2006.252.08:00:53.92/vblo/02,640.99,yes,locked 2006.252.08:00:53.92/vblo/03,656.99,yes,locked 2006.252.08:00:53.92/vblo/04,712.99,yes,locked 2006.252.08:00:53.92/vblo/05,744.99,yes,locked 2006.252.08:00:53.92/vblo/06,752.99,yes,locked 2006.252.08:00:53.92/vblo/07,734.99,yes,locked 2006.252.08:00:53.92/vblo/08,744.99,yes,locked 2006.252.08:00:54.07/vabw/8 2006.252.08:00:54.22/vbbw/8 2006.252.08:00:54.31/xfe/off,on,14.2 2006.252.08:00:54.68/ifatt/23,28,28,28 2006.252.08:00:55.07/fmout-gps/S +4.79E-07 2006.252.08:00:55.11:!2006.252.08:01:50 2006.252.08:01:50.00:data_valid=off 2006.252.08:01:50.00:postob 2006.252.08:01:50.12/cable/+6.4089E-03 2006.252.08:01:50.12/wx/27.33,1011.2,90 2006.252.08:01:51.08/fmout-gps/S +4.79E-07 2006.252.08:01:51.08:scan_name=252-0802,k06252,60 2006.252.08:01:51.09:source=1803+784,180045.68,782804.0,2000.0,neutral 2006.252.08:01:51.13#flagr#flagr/antenna,new-source 2006.252.08:01:52.13:checkk5 2006.252.08:01:52.50/chk_autoobs//k5ts1/ autoobs is running! 2006.252.08:01:52.88/chk_autoobs//k5ts2/ autoobs is running! 2006.252.08:01:53.27/chk_autoobs//k5ts3/ autoobs is running! 2006.252.08:01:53.65/chk_autoobs//k5ts4/ autoobs is running! 2006.252.08:01:54.02/chk_obsdata//k5ts1/T2520800??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.08:01:54.39/chk_obsdata//k5ts2/T2520800??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.08:01:54.76/chk_obsdata//k5ts3/T2520800??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.08:01:55.13/chk_obsdata//k5ts4/T2520800??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.08:01:55.83/k5log//k5ts1_log_newline 2006.252.08:01:56.52/k5log//k5ts2_log_newline 2006.252.08:01:57.21/k5log//k5ts3_log_newline 2006.252.08:01:57.90/k5log//k5ts4_log_newline 2006.252.08:01:57.92/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.252.08:01:57.92:4f8m12a=2 2006.252.08:01:57.93$4f8m12a/echo=on 2006.252.08:01:57.93$4f8m12a/pcalon 2006.252.08:01:57.93$pcalon/"no phase cal control is implemented here 2006.252.08:01:57.93$4f8m12a/"tpicd=stop 2006.252.08:01:57.93$4f8m12a/vc4f8 2006.252.08:01:57.93$vc4f8/valo=1,532.99 2006.252.08:01:57.93#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.252.08:01:57.93#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.252.08:01:57.93#ibcon#ireg 17 cls_cnt 0 2006.252.08:01:57.93#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.252.08:01:57.93#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.252.08:01:57.93#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.252.08:01:57.93#ibcon#enter wrdev, iclass 36, count 0 2006.252.08:01:57.93#ibcon#first serial, iclass 36, count 0 2006.252.08:01:57.93#ibcon#enter sib2, iclass 36, count 0 2006.252.08:01:57.93#ibcon#flushed, iclass 36, count 0 2006.252.08:01:57.93#ibcon#about to write, iclass 36, count 0 2006.252.08:01:57.93#ibcon#wrote, iclass 36, count 0 2006.252.08:01:57.93#ibcon#about to read 3, iclass 36, count 0 2006.252.08:01:57.97#ibcon#read 3, iclass 36, count 0 2006.252.08:01:57.97#ibcon#about to read 4, iclass 36, count 0 2006.252.08:01:57.97#ibcon#read 4, iclass 36, count 0 2006.252.08:01:57.97#ibcon#about to read 5, iclass 36, count 0 2006.252.08:01:57.97#ibcon#read 5, iclass 36, count 0 2006.252.08:01:57.97#ibcon#about to read 6, iclass 36, count 0 2006.252.08:01:57.97#ibcon#read 6, iclass 36, count 0 2006.252.08:01:57.97#ibcon#end of sib2, iclass 36, count 0 2006.252.08:01:57.97#ibcon#*mode == 0, iclass 36, count 0 2006.252.08:01:57.97#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.252.08:01:57.97#ibcon#[26=FRQ=01,532.99\r\n] 2006.252.08:01:57.97#ibcon#*before write, iclass 36, count 0 2006.252.08:01:57.97#ibcon#enter sib2, iclass 36, count 0 2006.252.08:01:57.97#ibcon#flushed, iclass 36, count 0 2006.252.08:01:57.97#ibcon#about to write, iclass 36, count 0 2006.252.08:01:57.97#ibcon#wrote, iclass 36, count 0 2006.252.08:01:57.97#ibcon#about to read 3, iclass 36, count 0 2006.252.08:01:58.02#ibcon#read 3, iclass 36, count 0 2006.252.08:01:58.02#ibcon#about to read 4, iclass 36, count 0 2006.252.08:01:58.02#ibcon#read 4, iclass 36, count 0 2006.252.08:01:58.02#ibcon#about to read 5, iclass 36, count 0 2006.252.08:01:58.02#ibcon#read 5, iclass 36, count 0 2006.252.08:01:58.02#ibcon#about to read 6, iclass 36, count 0 2006.252.08:01:58.02#ibcon#read 6, iclass 36, count 0 2006.252.08:01:58.02#ibcon#end of sib2, iclass 36, count 0 2006.252.08:01:58.02#ibcon#*after write, iclass 36, count 0 2006.252.08:01:58.02#ibcon#*before return 0, iclass 36, count 0 2006.252.08:01:58.02#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.252.08:01:58.02#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.252.08:01:58.02#ibcon#about to clear, iclass 36 cls_cnt 0 2006.252.08:01:58.02#ibcon#cleared, iclass 36 cls_cnt 0 2006.252.08:01:58.02$vc4f8/va=1,8 2006.252.08:01:58.02#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.252.08:01:58.02#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.252.08:01:58.02#ibcon#ireg 11 cls_cnt 2 2006.252.08:01:58.02#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.252.08:01:58.02#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.252.08:01:58.02#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.252.08:01:58.02#ibcon#enter wrdev, iclass 38, count 2 2006.252.08:01:58.02#ibcon#first serial, iclass 38, count 2 2006.252.08:01:58.02#ibcon#enter sib2, iclass 38, count 2 2006.252.08:01:58.02#ibcon#flushed, iclass 38, count 2 2006.252.08:01:58.02#ibcon#about to write, iclass 38, count 2 2006.252.08:01:58.02#ibcon#wrote, iclass 38, count 2 2006.252.08:01:58.02#ibcon#about to read 3, iclass 38, count 2 2006.252.08:01:58.04#ibcon#read 3, iclass 38, count 2 2006.252.08:01:58.04#ibcon#about to read 4, iclass 38, count 2 2006.252.08:01:58.04#ibcon#read 4, iclass 38, count 2 2006.252.08:01:58.04#ibcon#about to read 5, iclass 38, count 2 2006.252.08:01:58.04#ibcon#read 5, iclass 38, count 2 2006.252.08:01:58.04#ibcon#about to read 6, iclass 38, count 2 2006.252.08:01:58.04#ibcon#read 6, iclass 38, count 2 2006.252.08:01:58.04#ibcon#end of sib2, iclass 38, count 2 2006.252.08:01:58.04#ibcon#*mode == 0, iclass 38, count 2 2006.252.08:01:58.04#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.252.08:01:58.04#ibcon#[25=AT01-08\r\n] 2006.252.08:01:58.04#ibcon#*before write, iclass 38, count 2 2006.252.08:01:58.04#ibcon#enter sib2, iclass 38, count 2 2006.252.08:01:58.04#ibcon#flushed, iclass 38, count 2 2006.252.08:01:58.04#ibcon#about to write, iclass 38, count 2 2006.252.08:01:58.04#ibcon#wrote, iclass 38, count 2 2006.252.08:01:58.04#ibcon#about to read 3, iclass 38, count 2 2006.252.08:01:58.07#ibcon#read 3, iclass 38, count 2 2006.252.08:01:58.07#ibcon#about to read 4, iclass 38, count 2 2006.252.08:01:58.07#ibcon#read 4, iclass 38, count 2 2006.252.08:01:58.07#ibcon#about to read 5, iclass 38, count 2 2006.252.08:01:58.07#ibcon#read 5, iclass 38, count 2 2006.252.08:01:58.07#ibcon#about to read 6, iclass 38, count 2 2006.252.08:01:58.07#ibcon#read 6, iclass 38, count 2 2006.252.08:01:58.07#ibcon#end of sib2, iclass 38, count 2 2006.252.08:01:58.07#ibcon#*after write, iclass 38, count 2 2006.252.08:01:58.07#ibcon#*before return 0, iclass 38, count 2 2006.252.08:01:58.07#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.252.08:01:58.07#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.252.08:01:58.07#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.252.08:01:58.07#ibcon#ireg 7 cls_cnt 0 2006.252.08:01:58.07#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.252.08:01:58.19#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.252.08:01:58.19#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.252.08:01:58.19#ibcon#enter wrdev, iclass 38, count 0 2006.252.08:01:58.19#ibcon#first serial, iclass 38, count 0 2006.252.08:01:58.19#ibcon#enter sib2, iclass 38, count 0 2006.252.08:01:58.19#ibcon#flushed, iclass 38, count 0 2006.252.08:01:58.19#ibcon#about to write, iclass 38, count 0 2006.252.08:01:58.19#ibcon#wrote, iclass 38, count 0 2006.252.08:01:58.19#ibcon#about to read 3, iclass 38, count 0 2006.252.08:01:58.21#ibcon#read 3, iclass 38, count 0 2006.252.08:01:58.21#ibcon#about to read 4, iclass 38, count 0 2006.252.08:01:58.21#ibcon#read 4, iclass 38, count 0 2006.252.08:01:58.21#ibcon#about to read 5, iclass 38, count 0 2006.252.08:01:58.21#ibcon#read 5, iclass 38, count 0 2006.252.08:01:58.21#ibcon#about to read 6, iclass 38, count 0 2006.252.08:01:58.21#ibcon#read 6, iclass 38, count 0 2006.252.08:01:58.21#ibcon#end of sib2, iclass 38, count 0 2006.252.08:01:58.21#ibcon#*mode == 0, iclass 38, count 0 2006.252.08:01:58.21#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.252.08:01:58.21#ibcon#[25=USB\r\n] 2006.252.08:01:58.21#ibcon#*before write, iclass 38, count 0 2006.252.08:01:58.21#ibcon#enter sib2, iclass 38, count 0 2006.252.08:01:58.21#ibcon#flushed, iclass 38, count 0 2006.252.08:01:58.21#ibcon#about to write, iclass 38, count 0 2006.252.08:01:58.21#ibcon#wrote, iclass 38, count 0 2006.252.08:01:58.21#ibcon#about to read 3, iclass 38, count 0 2006.252.08:01:58.24#ibcon#read 3, iclass 38, count 0 2006.252.08:01:58.24#ibcon#about to read 4, iclass 38, count 0 2006.252.08:01:58.24#ibcon#read 4, iclass 38, count 0 2006.252.08:01:58.24#ibcon#about to read 5, iclass 38, count 0 2006.252.08:01:58.24#ibcon#read 5, iclass 38, count 0 2006.252.08:01:58.24#ibcon#about to read 6, iclass 38, count 0 2006.252.08:01:58.24#ibcon#read 6, iclass 38, count 0 2006.252.08:01:58.24#ibcon#end of sib2, iclass 38, count 0 2006.252.08:01:58.24#ibcon#*after write, iclass 38, count 0 2006.252.08:01:58.24#ibcon#*before return 0, iclass 38, count 0 2006.252.08:01:58.24#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.252.08:01:58.24#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.252.08:01:58.24#ibcon#about to clear, iclass 38 cls_cnt 0 2006.252.08:01:58.24#ibcon#cleared, iclass 38 cls_cnt 0 2006.252.08:01:58.24$vc4f8/valo=2,572.99 2006.252.08:01:58.24#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.252.08:01:58.24#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.252.08:01:58.24#ibcon#ireg 17 cls_cnt 0 2006.252.08:01:58.24#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.252.08:01:58.24#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.252.08:01:58.24#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.252.08:01:58.24#ibcon#enter wrdev, iclass 3, count 0 2006.252.08:01:58.24#ibcon#first serial, iclass 3, count 0 2006.252.08:01:58.24#ibcon#enter sib2, iclass 3, count 0 2006.252.08:01:58.24#ibcon#flushed, iclass 3, count 0 2006.252.08:01:58.24#ibcon#about to write, iclass 3, count 0 2006.252.08:01:58.24#ibcon#wrote, iclass 3, count 0 2006.252.08:01:58.24#ibcon#about to read 3, iclass 3, count 0 2006.252.08:01:58.25#abcon#<5=/05 3.7 6.6 27.34 901011.2\r\n> 2006.252.08:01:58.26#ibcon#read 3, iclass 3, count 0 2006.252.08:01:58.26#ibcon#about to read 4, iclass 3, count 0 2006.252.08:01:58.26#ibcon#read 4, iclass 3, count 0 2006.252.08:01:58.26#ibcon#about to read 5, iclass 3, count 0 2006.252.08:01:58.27#ibcon#read 5, iclass 3, count 0 2006.252.08:01:58.27#ibcon#about to read 6, iclass 3, count 0 2006.252.08:01:58.27#ibcon#read 6, iclass 3, count 0 2006.252.08:01:58.27#ibcon#end of sib2, iclass 3, count 0 2006.252.08:01:58.27#ibcon#*mode == 0, iclass 3, count 0 2006.252.08:01:58.27#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.252.08:01:58.27#ibcon#[26=FRQ=02,572.99\r\n] 2006.252.08:01:58.27#ibcon#*before write, iclass 3, count 0 2006.252.08:01:58.27#ibcon#enter sib2, iclass 3, count 0 2006.252.08:01:58.27#ibcon#flushed, iclass 3, count 0 2006.252.08:01:58.27#ibcon#about to write, iclass 3, count 0 2006.252.08:01:58.27#ibcon#wrote, iclass 3, count 0 2006.252.08:01:58.27#ibcon#about to read 3, iclass 3, count 0 2006.252.08:01:58.27#abcon#{5=INTERFACE CLEAR} 2006.252.08:01:58.31#ibcon#read 3, iclass 3, count 0 2006.252.08:01:58.31#ibcon#about to read 4, iclass 3, count 0 2006.252.08:01:58.31#ibcon#read 4, iclass 3, count 0 2006.252.08:01:58.31#ibcon#about to read 5, iclass 3, count 0 2006.252.08:01:58.31#ibcon#read 5, iclass 3, count 0 2006.252.08:01:58.31#ibcon#about to read 6, iclass 3, count 0 2006.252.08:01:58.31#ibcon#read 6, iclass 3, count 0 2006.252.08:01:58.31#ibcon#end of sib2, iclass 3, count 0 2006.252.08:01:58.31#ibcon#*after write, iclass 3, count 0 2006.252.08:01:58.31#ibcon#*before return 0, iclass 3, count 0 2006.252.08:01:58.31#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.252.08:01:58.31#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.252.08:01:58.31#ibcon#about to clear, iclass 3 cls_cnt 0 2006.252.08:01:58.31#ibcon#cleared, iclass 3 cls_cnt 0 2006.252.08:01:58.31$vc4f8/va=2,7 2006.252.08:01:58.31#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.252.08:01:58.31#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.252.08:01:58.31#ibcon#ireg 11 cls_cnt 2 2006.252.08:01:58.31#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.252.08:01:58.33#abcon#[5=S1D000X0/0*\r\n] 2006.252.08:01:58.36#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.252.08:01:58.36#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.252.08:01:58.36#ibcon#enter wrdev, iclass 7, count 2 2006.252.08:01:58.36#ibcon#first serial, iclass 7, count 2 2006.252.08:01:58.36#ibcon#enter sib2, iclass 7, count 2 2006.252.08:01:58.36#ibcon#flushed, iclass 7, count 2 2006.252.08:01:58.36#ibcon#about to write, iclass 7, count 2 2006.252.08:01:58.36#ibcon#wrote, iclass 7, count 2 2006.252.08:01:58.36#ibcon#about to read 3, iclass 7, count 2 2006.252.08:01:58.38#ibcon#read 3, iclass 7, count 2 2006.252.08:01:58.38#ibcon#about to read 4, iclass 7, count 2 2006.252.08:01:58.38#ibcon#read 4, iclass 7, count 2 2006.252.08:01:58.38#ibcon#about to read 5, iclass 7, count 2 2006.252.08:01:58.38#ibcon#read 5, iclass 7, count 2 2006.252.08:01:58.38#ibcon#about to read 6, iclass 7, count 2 2006.252.08:01:58.38#ibcon#read 6, iclass 7, count 2 2006.252.08:01:58.38#ibcon#end of sib2, iclass 7, count 2 2006.252.08:01:58.38#ibcon#*mode == 0, iclass 7, count 2 2006.252.08:01:58.38#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.252.08:01:58.38#ibcon#[25=AT02-07\r\n] 2006.252.08:01:58.38#ibcon#*before write, iclass 7, count 2 2006.252.08:01:58.38#ibcon#enter sib2, iclass 7, count 2 2006.252.08:01:58.38#ibcon#flushed, iclass 7, count 2 2006.252.08:01:58.38#ibcon#about to write, iclass 7, count 2 2006.252.08:01:58.38#ibcon#wrote, iclass 7, count 2 2006.252.08:01:58.38#ibcon#about to read 3, iclass 7, count 2 2006.252.08:01:58.41#ibcon#read 3, iclass 7, count 2 2006.252.08:01:58.41#ibcon#about to read 4, iclass 7, count 2 2006.252.08:01:58.41#ibcon#read 4, iclass 7, count 2 2006.252.08:01:58.41#ibcon#about to read 5, iclass 7, count 2 2006.252.08:01:58.41#ibcon#read 5, iclass 7, count 2 2006.252.08:01:58.41#ibcon#about to read 6, iclass 7, count 2 2006.252.08:01:58.41#ibcon#read 6, iclass 7, count 2 2006.252.08:01:58.41#ibcon#end of sib2, iclass 7, count 2 2006.252.08:01:58.41#ibcon#*after write, iclass 7, count 2 2006.252.08:01:58.41#ibcon#*before return 0, iclass 7, count 2 2006.252.08:01:58.41#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.252.08:01:58.41#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.252.08:01:58.41#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.252.08:01:58.41#ibcon#ireg 7 cls_cnt 0 2006.252.08:01:58.41#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.252.08:01:58.53#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.252.08:01:58.53#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.252.08:01:58.53#ibcon#enter wrdev, iclass 7, count 0 2006.252.08:01:58.53#ibcon#first serial, iclass 7, count 0 2006.252.08:01:58.53#ibcon#enter sib2, iclass 7, count 0 2006.252.08:01:58.53#ibcon#flushed, iclass 7, count 0 2006.252.08:01:58.53#ibcon#about to write, iclass 7, count 0 2006.252.08:01:58.53#ibcon#wrote, iclass 7, count 0 2006.252.08:01:58.53#ibcon#about to read 3, iclass 7, count 0 2006.252.08:01:58.55#ibcon#read 3, iclass 7, count 0 2006.252.08:01:58.55#ibcon#about to read 4, iclass 7, count 0 2006.252.08:01:58.55#ibcon#read 4, iclass 7, count 0 2006.252.08:01:58.55#ibcon#about to read 5, iclass 7, count 0 2006.252.08:01:58.55#ibcon#read 5, iclass 7, count 0 2006.252.08:01:58.55#ibcon#about to read 6, iclass 7, count 0 2006.252.08:01:58.55#ibcon#read 6, iclass 7, count 0 2006.252.08:01:58.55#ibcon#end of sib2, iclass 7, count 0 2006.252.08:01:58.55#ibcon#*mode == 0, iclass 7, count 0 2006.252.08:01:58.55#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.252.08:01:58.55#ibcon#[25=USB\r\n] 2006.252.08:01:58.55#ibcon#*before write, iclass 7, count 0 2006.252.08:01:58.55#ibcon#enter sib2, iclass 7, count 0 2006.252.08:01:58.55#ibcon#flushed, iclass 7, count 0 2006.252.08:01:58.55#ibcon#about to write, iclass 7, count 0 2006.252.08:01:58.55#ibcon#wrote, iclass 7, count 0 2006.252.08:01:58.55#ibcon#about to read 3, iclass 7, count 0 2006.252.08:01:58.58#ibcon#read 3, iclass 7, count 0 2006.252.08:01:58.58#ibcon#about to read 4, iclass 7, count 0 2006.252.08:01:58.58#ibcon#read 4, iclass 7, count 0 2006.252.08:01:58.58#ibcon#about to read 5, iclass 7, count 0 2006.252.08:01:58.58#ibcon#read 5, iclass 7, count 0 2006.252.08:01:58.58#ibcon#about to read 6, iclass 7, count 0 2006.252.08:01:58.58#ibcon#read 6, iclass 7, count 0 2006.252.08:01:58.58#ibcon#end of sib2, iclass 7, count 0 2006.252.08:01:58.58#ibcon#*after write, iclass 7, count 0 2006.252.08:01:58.58#ibcon#*before return 0, iclass 7, count 0 2006.252.08:01:58.58#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.252.08:01:58.58#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.252.08:01:58.58#ibcon#about to clear, iclass 7 cls_cnt 0 2006.252.08:01:58.58#ibcon#cleared, iclass 7 cls_cnt 0 2006.252.08:01:58.58$vc4f8/valo=3,672.99 2006.252.08:01:58.58#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.252.08:01:58.58#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.252.08:01:58.58#ibcon#ireg 17 cls_cnt 0 2006.252.08:01:58.58#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.252.08:01:58.58#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.252.08:01:58.58#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.252.08:01:58.58#ibcon#enter wrdev, iclass 12, count 0 2006.252.08:01:58.58#ibcon#first serial, iclass 12, count 0 2006.252.08:01:58.58#ibcon#enter sib2, iclass 12, count 0 2006.252.08:01:58.58#ibcon#flushed, iclass 12, count 0 2006.252.08:01:58.58#ibcon#about to write, iclass 12, count 0 2006.252.08:01:58.58#ibcon#wrote, iclass 12, count 0 2006.252.08:01:58.58#ibcon#about to read 3, iclass 12, count 0 2006.252.08:01:58.60#ibcon#read 3, iclass 12, count 0 2006.252.08:01:58.60#ibcon#about to read 4, iclass 12, count 0 2006.252.08:01:58.60#ibcon#read 4, iclass 12, count 0 2006.252.08:01:58.60#ibcon#about to read 5, iclass 12, count 0 2006.252.08:01:58.60#ibcon#read 5, iclass 12, count 0 2006.252.08:01:58.60#ibcon#about to read 6, iclass 12, count 0 2006.252.08:01:58.60#ibcon#read 6, iclass 12, count 0 2006.252.08:01:58.60#ibcon#end of sib2, iclass 12, count 0 2006.252.08:01:58.60#ibcon#*mode == 0, iclass 12, count 0 2006.252.08:01:58.60#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.252.08:01:58.60#ibcon#[26=FRQ=03,672.99\r\n] 2006.252.08:01:58.60#ibcon#*before write, iclass 12, count 0 2006.252.08:01:58.60#ibcon#enter sib2, iclass 12, count 0 2006.252.08:01:58.60#ibcon#flushed, iclass 12, count 0 2006.252.08:01:58.60#ibcon#about to write, iclass 12, count 0 2006.252.08:01:58.60#ibcon#wrote, iclass 12, count 0 2006.252.08:01:58.60#ibcon#about to read 3, iclass 12, count 0 2006.252.08:01:58.65#ibcon#read 3, iclass 12, count 0 2006.252.08:01:58.65#ibcon#about to read 4, iclass 12, count 0 2006.252.08:01:58.65#ibcon#read 4, iclass 12, count 0 2006.252.08:01:58.65#ibcon#about to read 5, iclass 12, count 0 2006.252.08:01:58.65#ibcon#read 5, iclass 12, count 0 2006.252.08:01:58.65#ibcon#about to read 6, iclass 12, count 0 2006.252.08:01:58.65#ibcon#read 6, iclass 12, count 0 2006.252.08:01:58.65#ibcon#end of sib2, iclass 12, count 0 2006.252.08:01:58.65#ibcon#*after write, iclass 12, count 0 2006.252.08:01:58.65#ibcon#*before return 0, iclass 12, count 0 2006.252.08:01:58.65#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.252.08:01:58.65#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.252.08:01:58.65#ibcon#about to clear, iclass 12 cls_cnt 0 2006.252.08:01:58.65#ibcon#cleared, iclass 12 cls_cnt 0 2006.252.08:01:58.65$vc4f8/va=3,6 2006.252.08:01:58.65#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.252.08:01:58.65#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.252.08:01:58.65#ibcon#ireg 11 cls_cnt 2 2006.252.08:01:58.65#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.252.08:01:58.70#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.252.08:01:58.70#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.252.08:01:58.70#ibcon#enter wrdev, iclass 14, count 2 2006.252.08:01:58.70#ibcon#first serial, iclass 14, count 2 2006.252.08:01:58.70#ibcon#enter sib2, iclass 14, count 2 2006.252.08:01:58.70#ibcon#flushed, iclass 14, count 2 2006.252.08:01:58.70#ibcon#about to write, iclass 14, count 2 2006.252.08:01:58.70#ibcon#wrote, iclass 14, count 2 2006.252.08:01:58.70#ibcon#about to read 3, iclass 14, count 2 2006.252.08:01:58.72#ibcon#read 3, iclass 14, count 2 2006.252.08:01:58.72#ibcon#about to read 4, iclass 14, count 2 2006.252.08:01:58.72#ibcon#read 4, iclass 14, count 2 2006.252.08:01:58.72#ibcon#about to read 5, iclass 14, count 2 2006.252.08:01:58.72#ibcon#read 5, iclass 14, count 2 2006.252.08:01:58.72#ibcon#about to read 6, iclass 14, count 2 2006.252.08:01:58.72#ibcon#read 6, iclass 14, count 2 2006.252.08:01:58.72#ibcon#end of sib2, iclass 14, count 2 2006.252.08:01:58.72#ibcon#*mode == 0, iclass 14, count 2 2006.252.08:01:58.72#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.252.08:01:58.72#ibcon#[25=AT03-06\r\n] 2006.252.08:01:58.72#ibcon#*before write, iclass 14, count 2 2006.252.08:01:58.72#ibcon#enter sib2, iclass 14, count 2 2006.252.08:01:58.72#ibcon#flushed, iclass 14, count 2 2006.252.08:01:58.72#ibcon#about to write, iclass 14, count 2 2006.252.08:01:58.72#ibcon#wrote, iclass 14, count 2 2006.252.08:01:58.72#ibcon#about to read 3, iclass 14, count 2 2006.252.08:01:58.75#ibcon#read 3, iclass 14, count 2 2006.252.08:01:58.75#ibcon#about to read 4, iclass 14, count 2 2006.252.08:01:58.75#ibcon#read 4, iclass 14, count 2 2006.252.08:01:58.75#ibcon#about to read 5, iclass 14, count 2 2006.252.08:01:58.75#ibcon#read 5, iclass 14, count 2 2006.252.08:01:58.75#ibcon#about to read 6, iclass 14, count 2 2006.252.08:01:58.75#ibcon#read 6, iclass 14, count 2 2006.252.08:01:58.75#ibcon#end of sib2, iclass 14, count 2 2006.252.08:01:58.75#ibcon#*after write, iclass 14, count 2 2006.252.08:01:58.75#ibcon#*before return 0, iclass 14, count 2 2006.252.08:01:58.75#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.252.08:01:58.75#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.252.08:01:58.75#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.252.08:01:58.75#ibcon#ireg 7 cls_cnt 0 2006.252.08:01:58.75#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.252.08:01:58.87#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.252.08:01:58.87#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.252.08:01:58.87#ibcon#enter wrdev, iclass 14, count 0 2006.252.08:01:58.87#ibcon#first serial, iclass 14, count 0 2006.252.08:01:58.87#ibcon#enter sib2, iclass 14, count 0 2006.252.08:01:58.87#ibcon#flushed, iclass 14, count 0 2006.252.08:01:58.87#ibcon#about to write, iclass 14, count 0 2006.252.08:01:58.87#ibcon#wrote, iclass 14, count 0 2006.252.08:01:58.87#ibcon#about to read 3, iclass 14, count 0 2006.252.08:01:58.89#ibcon#read 3, iclass 14, count 0 2006.252.08:01:58.89#ibcon#about to read 4, iclass 14, count 0 2006.252.08:01:58.89#ibcon#read 4, iclass 14, count 0 2006.252.08:01:58.89#ibcon#about to read 5, iclass 14, count 0 2006.252.08:01:58.89#ibcon#read 5, iclass 14, count 0 2006.252.08:01:58.89#ibcon#about to read 6, iclass 14, count 0 2006.252.08:01:58.89#ibcon#read 6, iclass 14, count 0 2006.252.08:01:58.89#ibcon#end of sib2, iclass 14, count 0 2006.252.08:01:58.89#ibcon#*mode == 0, iclass 14, count 0 2006.252.08:01:58.89#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.252.08:01:58.89#ibcon#[25=USB\r\n] 2006.252.08:01:58.89#ibcon#*before write, iclass 14, count 0 2006.252.08:01:58.89#ibcon#enter sib2, iclass 14, count 0 2006.252.08:01:58.89#ibcon#flushed, iclass 14, count 0 2006.252.08:01:58.89#ibcon#about to write, iclass 14, count 0 2006.252.08:01:58.89#ibcon#wrote, iclass 14, count 0 2006.252.08:01:58.89#ibcon#about to read 3, iclass 14, count 0 2006.252.08:01:58.92#ibcon#read 3, iclass 14, count 0 2006.252.08:01:58.92#ibcon#about to read 4, iclass 14, count 0 2006.252.08:01:58.92#ibcon#read 4, iclass 14, count 0 2006.252.08:01:58.92#ibcon#about to read 5, iclass 14, count 0 2006.252.08:01:58.92#ibcon#read 5, iclass 14, count 0 2006.252.08:01:58.92#ibcon#about to read 6, iclass 14, count 0 2006.252.08:01:58.92#ibcon#read 6, iclass 14, count 0 2006.252.08:01:58.92#ibcon#end of sib2, iclass 14, count 0 2006.252.08:01:58.92#ibcon#*after write, iclass 14, count 0 2006.252.08:01:58.92#ibcon#*before return 0, iclass 14, count 0 2006.252.08:01:58.92#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.252.08:01:58.92#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.252.08:01:58.92#ibcon#about to clear, iclass 14 cls_cnt 0 2006.252.08:01:58.92#ibcon#cleared, iclass 14 cls_cnt 0 2006.252.08:01:58.92$vc4f8/valo=4,832.99 2006.252.08:01:58.92#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.252.08:01:58.92#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.252.08:01:58.92#ibcon#ireg 17 cls_cnt 0 2006.252.08:01:58.92#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.252.08:01:58.92#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.252.08:01:58.92#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.252.08:01:58.92#ibcon#enter wrdev, iclass 16, count 0 2006.252.08:01:58.92#ibcon#first serial, iclass 16, count 0 2006.252.08:01:58.92#ibcon#enter sib2, iclass 16, count 0 2006.252.08:01:58.92#ibcon#flushed, iclass 16, count 0 2006.252.08:01:58.92#ibcon#about to write, iclass 16, count 0 2006.252.08:01:58.92#ibcon#wrote, iclass 16, count 0 2006.252.08:01:58.92#ibcon#about to read 3, iclass 16, count 0 2006.252.08:01:58.94#ibcon#read 3, iclass 16, count 0 2006.252.08:01:58.94#ibcon#about to read 4, iclass 16, count 0 2006.252.08:01:58.94#ibcon#read 4, iclass 16, count 0 2006.252.08:01:58.94#ibcon#about to read 5, iclass 16, count 0 2006.252.08:01:58.94#ibcon#read 5, iclass 16, count 0 2006.252.08:01:58.94#ibcon#about to read 6, iclass 16, count 0 2006.252.08:01:58.94#ibcon#read 6, iclass 16, count 0 2006.252.08:01:58.94#ibcon#end of sib2, iclass 16, count 0 2006.252.08:01:58.94#ibcon#*mode == 0, iclass 16, count 0 2006.252.08:01:58.94#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.252.08:01:58.94#ibcon#[26=FRQ=04,832.99\r\n] 2006.252.08:01:58.94#ibcon#*before write, iclass 16, count 0 2006.252.08:01:58.94#ibcon#enter sib2, iclass 16, count 0 2006.252.08:01:58.94#ibcon#flushed, iclass 16, count 0 2006.252.08:01:58.94#ibcon#about to write, iclass 16, count 0 2006.252.08:01:58.94#ibcon#wrote, iclass 16, count 0 2006.252.08:01:58.94#ibcon#about to read 3, iclass 16, count 0 2006.252.08:01:58.99#ibcon#read 3, iclass 16, count 0 2006.252.08:01:58.99#ibcon#about to read 4, iclass 16, count 0 2006.252.08:01:58.99#ibcon#read 4, iclass 16, count 0 2006.252.08:01:58.99#ibcon#about to read 5, iclass 16, count 0 2006.252.08:01:58.99#ibcon#read 5, iclass 16, count 0 2006.252.08:01:58.99#ibcon#about to read 6, iclass 16, count 0 2006.252.08:01:58.99#ibcon#read 6, iclass 16, count 0 2006.252.08:01:58.99#ibcon#end of sib2, iclass 16, count 0 2006.252.08:01:58.99#ibcon#*after write, iclass 16, count 0 2006.252.08:01:58.99#ibcon#*before return 0, iclass 16, count 0 2006.252.08:01:58.99#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.252.08:01:58.99#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.252.08:01:58.99#ibcon#about to clear, iclass 16 cls_cnt 0 2006.252.08:01:58.99#ibcon#cleared, iclass 16 cls_cnt 0 2006.252.08:01:58.99$vc4f8/va=4,7 2006.252.08:01:58.99#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.252.08:01:58.99#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.252.08:01:58.99#ibcon#ireg 11 cls_cnt 2 2006.252.08:01:58.99#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.252.08:01:59.04#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.252.08:01:59.04#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.252.08:01:59.04#ibcon#enter wrdev, iclass 18, count 2 2006.252.08:01:59.04#ibcon#first serial, iclass 18, count 2 2006.252.08:01:59.04#ibcon#enter sib2, iclass 18, count 2 2006.252.08:01:59.04#ibcon#flushed, iclass 18, count 2 2006.252.08:01:59.04#ibcon#about to write, iclass 18, count 2 2006.252.08:01:59.04#ibcon#wrote, iclass 18, count 2 2006.252.08:01:59.04#ibcon#about to read 3, iclass 18, count 2 2006.252.08:01:59.06#ibcon#read 3, iclass 18, count 2 2006.252.08:01:59.06#ibcon#about to read 4, iclass 18, count 2 2006.252.08:01:59.06#ibcon#read 4, iclass 18, count 2 2006.252.08:01:59.06#ibcon#about to read 5, iclass 18, count 2 2006.252.08:01:59.06#ibcon#read 5, iclass 18, count 2 2006.252.08:01:59.06#ibcon#about to read 6, iclass 18, count 2 2006.252.08:01:59.06#ibcon#read 6, iclass 18, count 2 2006.252.08:01:59.06#ibcon#end of sib2, iclass 18, count 2 2006.252.08:01:59.06#ibcon#*mode == 0, iclass 18, count 2 2006.252.08:01:59.06#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.252.08:01:59.06#ibcon#[25=AT04-07\r\n] 2006.252.08:01:59.06#ibcon#*before write, iclass 18, count 2 2006.252.08:01:59.06#ibcon#enter sib2, iclass 18, count 2 2006.252.08:01:59.06#ibcon#flushed, iclass 18, count 2 2006.252.08:01:59.06#ibcon#about to write, iclass 18, count 2 2006.252.08:01:59.06#ibcon#wrote, iclass 18, count 2 2006.252.08:01:59.06#ibcon#about to read 3, iclass 18, count 2 2006.252.08:01:59.09#ibcon#read 3, iclass 18, count 2 2006.252.08:01:59.09#ibcon#about to read 4, iclass 18, count 2 2006.252.08:01:59.09#ibcon#read 4, iclass 18, count 2 2006.252.08:01:59.09#ibcon#about to read 5, iclass 18, count 2 2006.252.08:01:59.09#ibcon#read 5, iclass 18, count 2 2006.252.08:01:59.09#ibcon#about to read 6, iclass 18, count 2 2006.252.08:01:59.09#ibcon#read 6, iclass 18, count 2 2006.252.08:01:59.09#ibcon#end of sib2, iclass 18, count 2 2006.252.08:01:59.09#ibcon#*after write, iclass 18, count 2 2006.252.08:01:59.09#ibcon#*before return 0, iclass 18, count 2 2006.252.08:01:59.09#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.252.08:01:59.09#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.252.08:01:59.09#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.252.08:01:59.09#ibcon#ireg 7 cls_cnt 0 2006.252.08:01:59.09#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.252.08:01:59.21#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.252.08:01:59.21#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.252.08:01:59.21#ibcon#enter wrdev, iclass 18, count 0 2006.252.08:01:59.21#ibcon#first serial, iclass 18, count 0 2006.252.08:01:59.21#ibcon#enter sib2, iclass 18, count 0 2006.252.08:01:59.21#ibcon#flushed, iclass 18, count 0 2006.252.08:01:59.21#ibcon#about to write, iclass 18, count 0 2006.252.08:01:59.21#ibcon#wrote, iclass 18, count 0 2006.252.08:01:59.21#ibcon#about to read 3, iclass 18, count 0 2006.252.08:01:59.23#ibcon#read 3, iclass 18, count 0 2006.252.08:01:59.23#ibcon#about to read 4, iclass 18, count 0 2006.252.08:01:59.23#ibcon#read 4, iclass 18, count 0 2006.252.08:01:59.23#ibcon#about to read 5, iclass 18, count 0 2006.252.08:01:59.23#ibcon#read 5, iclass 18, count 0 2006.252.08:01:59.23#ibcon#about to read 6, iclass 18, count 0 2006.252.08:01:59.23#ibcon#read 6, iclass 18, count 0 2006.252.08:01:59.23#ibcon#end of sib2, iclass 18, count 0 2006.252.08:01:59.23#ibcon#*mode == 0, iclass 18, count 0 2006.252.08:01:59.23#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.252.08:01:59.23#ibcon#[25=USB\r\n] 2006.252.08:01:59.23#ibcon#*before write, iclass 18, count 0 2006.252.08:01:59.23#ibcon#enter sib2, iclass 18, count 0 2006.252.08:01:59.23#ibcon#flushed, iclass 18, count 0 2006.252.08:01:59.23#ibcon#about to write, iclass 18, count 0 2006.252.08:01:59.23#ibcon#wrote, iclass 18, count 0 2006.252.08:01:59.23#ibcon#about to read 3, iclass 18, count 0 2006.252.08:01:59.26#ibcon#read 3, iclass 18, count 0 2006.252.08:01:59.26#ibcon#about to read 4, iclass 18, count 0 2006.252.08:01:59.26#ibcon#read 4, iclass 18, count 0 2006.252.08:01:59.26#ibcon#about to read 5, iclass 18, count 0 2006.252.08:01:59.26#ibcon#read 5, iclass 18, count 0 2006.252.08:01:59.26#ibcon#about to read 6, iclass 18, count 0 2006.252.08:01:59.26#ibcon#read 6, iclass 18, count 0 2006.252.08:01:59.26#ibcon#end of sib2, iclass 18, count 0 2006.252.08:01:59.26#ibcon#*after write, iclass 18, count 0 2006.252.08:01:59.26#ibcon#*before return 0, iclass 18, count 0 2006.252.08:01:59.26#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.252.08:01:59.26#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.252.08:01:59.26#ibcon#about to clear, iclass 18 cls_cnt 0 2006.252.08:01:59.26#ibcon#cleared, iclass 18 cls_cnt 0 2006.252.08:01:59.26$vc4f8/valo=5,652.99 2006.252.08:01:59.26#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.252.08:01:59.26#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.252.08:01:59.26#ibcon#ireg 17 cls_cnt 0 2006.252.08:01:59.26#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.252.08:01:59.26#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.252.08:01:59.26#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.252.08:01:59.26#ibcon#enter wrdev, iclass 20, count 0 2006.252.08:01:59.26#ibcon#first serial, iclass 20, count 0 2006.252.08:01:59.26#ibcon#enter sib2, iclass 20, count 0 2006.252.08:01:59.26#ibcon#flushed, iclass 20, count 0 2006.252.08:01:59.26#ibcon#about to write, iclass 20, count 0 2006.252.08:01:59.26#ibcon#wrote, iclass 20, count 0 2006.252.08:01:59.26#ibcon#about to read 3, iclass 20, count 0 2006.252.08:01:59.28#ibcon#read 3, iclass 20, count 0 2006.252.08:01:59.28#ibcon#about to read 4, iclass 20, count 0 2006.252.08:01:59.28#ibcon#read 4, iclass 20, count 0 2006.252.08:01:59.28#ibcon#about to read 5, iclass 20, count 0 2006.252.08:01:59.28#ibcon#read 5, iclass 20, count 0 2006.252.08:01:59.28#ibcon#about to read 6, iclass 20, count 0 2006.252.08:01:59.28#ibcon#read 6, iclass 20, count 0 2006.252.08:01:59.28#ibcon#end of sib2, iclass 20, count 0 2006.252.08:01:59.28#ibcon#*mode == 0, iclass 20, count 0 2006.252.08:01:59.28#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.252.08:01:59.28#ibcon#[26=FRQ=05,652.99\r\n] 2006.252.08:01:59.28#ibcon#*before write, iclass 20, count 0 2006.252.08:01:59.28#ibcon#enter sib2, iclass 20, count 0 2006.252.08:01:59.28#ibcon#flushed, iclass 20, count 0 2006.252.08:01:59.28#ibcon#about to write, iclass 20, count 0 2006.252.08:01:59.28#ibcon#wrote, iclass 20, count 0 2006.252.08:01:59.28#ibcon#about to read 3, iclass 20, count 0 2006.252.08:01:59.32#ibcon#read 3, iclass 20, count 0 2006.252.08:01:59.32#ibcon#about to read 4, iclass 20, count 0 2006.252.08:01:59.32#ibcon#read 4, iclass 20, count 0 2006.252.08:01:59.32#ibcon#about to read 5, iclass 20, count 0 2006.252.08:01:59.32#ibcon#read 5, iclass 20, count 0 2006.252.08:01:59.32#ibcon#about to read 6, iclass 20, count 0 2006.252.08:01:59.32#ibcon#read 6, iclass 20, count 0 2006.252.08:01:59.32#ibcon#end of sib2, iclass 20, count 0 2006.252.08:01:59.32#ibcon#*after write, iclass 20, count 0 2006.252.08:01:59.32#ibcon#*before return 0, iclass 20, count 0 2006.252.08:01:59.32#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.252.08:01:59.32#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.252.08:01:59.32#ibcon#about to clear, iclass 20 cls_cnt 0 2006.252.08:01:59.32#ibcon#cleared, iclass 20 cls_cnt 0 2006.252.08:01:59.32$vc4f8/va=5,7 2006.252.08:01:59.32#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.252.08:01:59.32#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.252.08:01:59.32#ibcon#ireg 11 cls_cnt 2 2006.252.08:01:59.32#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.252.08:01:59.38#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.252.08:01:59.38#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.252.08:01:59.38#ibcon#enter wrdev, iclass 22, count 2 2006.252.08:01:59.38#ibcon#first serial, iclass 22, count 2 2006.252.08:01:59.38#ibcon#enter sib2, iclass 22, count 2 2006.252.08:01:59.38#ibcon#flushed, iclass 22, count 2 2006.252.08:01:59.38#ibcon#about to write, iclass 22, count 2 2006.252.08:01:59.38#ibcon#wrote, iclass 22, count 2 2006.252.08:01:59.38#ibcon#about to read 3, iclass 22, count 2 2006.252.08:01:59.40#ibcon#read 3, iclass 22, count 2 2006.252.08:01:59.40#ibcon#about to read 4, iclass 22, count 2 2006.252.08:01:59.40#ibcon#read 4, iclass 22, count 2 2006.252.08:01:59.40#ibcon#about to read 5, iclass 22, count 2 2006.252.08:01:59.40#ibcon#read 5, iclass 22, count 2 2006.252.08:01:59.40#ibcon#about to read 6, iclass 22, count 2 2006.252.08:01:59.40#ibcon#read 6, iclass 22, count 2 2006.252.08:01:59.40#ibcon#end of sib2, iclass 22, count 2 2006.252.08:01:59.40#ibcon#*mode == 0, iclass 22, count 2 2006.252.08:01:59.40#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.252.08:01:59.40#ibcon#[25=AT05-07\r\n] 2006.252.08:01:59.40#ibcon#*before write, iclass 22, count 2 2006.252.08:01:59.40#ibcon#enter sib2, iclass 22, count 2 2006.252.08:01:59.40#ibcon#flushed, iclass 22, count 2 2006.252.08:01:59.40#ibcon#about to write, iclass 22, count 2 2006.252.08:01:59.40#ibcon#wrote, iclass 22, count 2 2006.252.08:01:59.40#ibcon#about to read 3, iclass 22, count 2 2006.252.08:01:59.43#ibcon#read 3, iclass 22, count 2 2006.252.08:01:59.43#ibcon#about to read 4, iclass 22, count 2 2006.252.08:01:59.43#ibcon#read 4, iclass 22, count 2 2006.252.08:01:59.43#ibcon#about to read 5, iclass 22, count 2 2006.252.08:01:59.43#ibcon#read 5, iclass 22, count 2 2006.252.08:01:59.43#ibcon#about to read 6, iclass 22, count 2 2006.252.08:01:59.43#ibcon#read 6, iclass 22, count 2 2006.252.08:01:59.43#ibcon#end of sib2, iclass 22, count 2 2006.252.08:01:59.43#ibcon#*after write, iclass 22, count 2 2006.252.08:01:59.43#ibcon#*before return 0, iclass 22, count 2 2006.252.08:01:59.43#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.252.08:01:59.43#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.252.08:01:59.43#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.252.08:01:59.43#ibcon#ireg 7 cls_cnt 0 2006.252.08:01:59.43#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.252.08:01:59.55#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.252.08:01:59.55#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.252.08:01:59.55#ibcon#enter wrdev, iclass 22, count 0 2006.252.08:01:59.55#ibcon#first serial, iclass 22, count 0 2006.252.08:01:59.55#ibcon#enter sib2, iclass 22, count 0 2006.252.08:01:59.55#ibcon#flushed, iclass 22, count 0 2006.252.08:01:59.55#ibcon#about to write, iclass 22, count 0 2006.252.08:01:59.55#ibcon#wrote, iclass 22, count 0 2006.252.08:01:59.55#ibcon#about to read 3, iclass 22, count 0 2006.252.08:01:59.57#ibcon#read 3, iclass 22, count 0 2006.252.08:01:59.57#ibcon#about to read 4, iclass 22, count 0 2006.252.08:01:59.57#ibcon#read 4, iclass 22, count 0 2006.252.08:01:59.57#ibcon#about to read 5, iclass 22, count 0 2006.252.08:01:59.57#ibcon#read 5, iclass 22, count 0 2006.252.08:01:59.57#ibcon#about to read 6, iclass 22, count 0 2006.252.08:01:59.57#ibcon#read 6, iclass 22, count 0 2006.252.08:01:59.57#ibcon#end of sib2, iclass 22, count 0 2006.252.08:01:59.57#ibcon#*mode == 0, iclass 22, count 0 2006.252.08:01:59.57#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.252.08:01:59.57#ibcon#[25=USB\r\n] 2006.252.08:01:59.57#ibcon#*before write, iclass 22, count 0 2006.252.08:01:59.57#ibcon#enter sib2, iclass 22, count 0 2006.252.08:01:59.57#ibcon#flushed, iclass 22, count 0 2006.252.08:01:59.57#ibcon#about to write, iclass 22, count 0 2006.252.08:01:59.57#ibcon#wrote, iclass 22, count 0 2006.252.08:01:59.57#ibcon#about to read 3, iclass 22, count 0 2006.252.08:01:59.60#ibcon#read 3, iclass 22, count 0 2006.252.08:01:59.60#ibcon#about to read 4, iclass 22, count 0 2006.252.08:01:59.60#ibcon#read 4, iclass 22, count 0 2006.252.08:01:59.60#ibcon#about to read 5, iclass 22, count 0 2006.252.08:01:59.60#ibcon#read 5, iclass 22, count 0 2006.252.08:01:59.60#ibcon#about to read 6, iclass 22, count 0 2006.252.08:01:59.60#ibcon#read 6, iclass 22, count 0 2006.252.08:01:59.60#ibcon#end of sib2, iclass 22, count 0 2006.252.08:01:59.60#ibcon#*after write, iclass 22, count 0 2006.252.08:01:59.60#ibcon#*before return 0, iclass 22, count 0 2006.252.08:01:59.60#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.252.08:01:59.60#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.252.08:01:59.60#ibcon#about to clear, iclass 22 cls_cnt 0 2006.252.08:01:59.60#ibcon#cleared, iclass 22 cls_cnt 0 2006.252.08:01:59.60$vc4f8/valo=6,772.99 2006.252.08:01:59.60#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.252.08:01:59.60#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.252.08:01:59.60#ibcon#ireg 17 cls_cnt 0 2006.252.08:01:59.60#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.252.08:01:59.60#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.252.08:01:59.60#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.252.08:01:59.60#ibcon#enter wrdev, iclass 24, count 0 2006.252.08:01:59.60#ibcon#first serial, iclass 24, count 0 2006.252.08:01:59.60#ibcon#enter sib2, iclass 24, count 0 2006.252.08:01:59.60#ibcon#flushed, iclass 24, count 0 2006.252.08:01:59.60#ibcon#about to write, iclass 24, count 0 2006.252.08:01:59.60#ibcon#wrote, iclass 24, count 0 2006.252.08:01:59.60#ibcon#about to read 3, iclass 24, count 0 2006.252.08:01:59.62#ibcon#read 3, iclass 24, count 0 2006.252.08:01:59.62#ibcon#about to read 4, iclass 24, count 0 2006.252.08:01:59.62#ibcon#read 4, iclass 24, count 0 2006.252.08:01:59.62#ibcon#about to read 5, iclass 24, count 0 2006.252.08:01:59.62#ibcon#read 5, iclass 24, count 0 2006.252.08:01:59.62#ibcon#about to read 6, iclass 24, count 0 2006.252.08:01:59.62#ibcon#read 6, iclass 24, count 0 2006.252.08:01:59.62#ibcon#end of sib2, iclass 24, count 0 2006.252.08:01:59.62#ibcon#*mode == 0, iclass 24, count 0 2006.252.08:01:59.62#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.252.08:01:59.62#ibcon#[26=FRQ=06,772.99\r\n] 2006.252.08:01:59.62#ibcon#*before write, iclass 24, count 0 2006.252.08:01:59.62#ibcon#enter sib2, iclass 24, count 0 2006.252.08:01:59.62#ibcon#flushed, iclass 24, count 0 2006.252.08:01:59.62#ibcon#about to write, iclass 24, count 0 2006.252.08:01:59.62#ibcon#wrote, iclass 24, count 0 2006.252.08:01:59.62#ibcon#about to read 3, iclass 24, count 0 2006.252.08:01:59.67#ibcon#read 3, iclass 24, count 0 2006.252.08:01:59.67#ibcon#about to read 4, iclass 24, count 0 2006.252.08:01:59.67#ibcon#read 4, iclass 24, count 0 2006.252.08:01:59.67#ibcon#about to read 5, iclass 24, count 0 2006.252.08:01:59.67#ibcon#read 5, iclass 24, count 0 2006.252.08:01:59.67#ibcon#about to read 6, iclass 24, count 0 2006.252.08:01:59.67#ibcon#read 6, iclass 24, count 0 2006.252.08:01:59.67#ibcon#end of sib2, iclass 24, count 0 2006.252.08:01:59.67#ibcon#*after write, iclass 24, count 0 2006.252.08:01:59.67#ibcon#*before return 0, iclass 24, count 0 2006.252.08:01:59.67#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.252.08:01:59.67#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.252.08:01:59.67#ibcon#about to clear, iclass 24 cls_cnt 0 2006.252.08:01:59.67#ibcon#cleared, iclass 24 cls_cnt 0 2006.252.08:01:59.67$vc4f8/va=6,7 2006.252.08:01:59.67#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.252.08:01:59.67#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.252.08:01:59.67#ibcon#ireg 11 cls_cnt 2 2006.252.08:01:59.67#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.252.08:01:59.72#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.252.08:01:59.72#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.252.08:01:59.72#ibcon#enter wrdev, iclass 26, count 2 2006.252.08:01:59.72#ibcon#first serial, iclass 26, count 2 2006.252.08:01:59.72#ibcon#enter sib2, iclass 26, count 2 2006.252.08:01:59.72#ibcon#flushed, iclass 26, count 2 2006.252.08:01:59.72#ibcon#about to write, iclass 26, count 2 2006.252.08:01:59.72#ibcon#wrote, iclass 26, count 2 2006.252.08:01:59.72#ibcon#about to read 3, iclass 26, count 2 2006.252.08:01:59.74#ibcon#read 3, iclass 26, count 2 2006.252.08:01:59.74#ibcon#about to read 4, iclass 26, count 2 2006.252.08:01:59.74#ibcon#read 4, iclass 26, count 2 2006.252.08:01:59.74#ibcon#about to read 5, iclass 26, count 2 2006.252.08:01:59.74#ibcon#read 5, iclass 26, count 2 2006.252.08:01:59.74#ibcon#about to read 6, iclass 26, count 2 2006.252.08:01:59.74#ibcon#read 6, iclass 26, count 2 2006.252.08:01:59.74#ibcon#end of sib2, iclass 26, count 2 2006.252.08:01:59.74#ibcon#*mode == 0, iclass 26, count 2 2006.252.08:01:59.74#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.252.08:01:59.74#ibcon#[25=AT06-07\r\n] 2006.252.08:01:59.74#ibcon#*before write, iclass 26, count 2 2006.252.08:01:59.74#ibcon#enter sib2, iclass 26, count 2 2006.252.08:01:59.74#ibcon#flushed, iclass 26, count 2 2006.252.08:01:59.74#ibcon#about to write, iclass 26, count 2 2006.252.08:01:59.74#ibcon#wrote, iclass 26, count 2 2006.252.08:01:59.74#ibcon#about to read 3, iclass 26, count 2 2006.252.08:01:59.77#ibcon#read 3, iclass 26, count 2 2006.252.08:01:59.77#ibcon#about to read 4, iclass 26, count 2 2006.252.08:01:59.77#ibcon#read 4, iclass 26, count 2 2006.252.08:01:59.77#ibcon#about to read 5, iclass 26, count 2 2006.252.08:01:59.77#ibcon#read 5, iclass 26, count 2 2006.252.08:01:59.77#ibcon#about to read 6, iclass 26, count 2 2006.252.08:01:59.77#ibcon#read 6, iclass 26, count 2 2006.252.08:01:59.77#ibcon#end of sib2, iclass 26, count 2 2006.252.08:01:59.77#ibcon#*after write, iclass 26, count 2 2006.252.08:01:59.77#ibcon#*before return 0, iclass 26, count 2 2006.252.08:01:59.77#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.252.08:01:59.77#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.252.08:01:59.77#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.252.08:01:59.77#ibcon#ireg 7 cls_cnt 0 2006.252.08:01:59.77#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.252.08:01:59.89#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.252.08:01:59.89#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.252.08:01:59.89#ibcon#enter wrdev, iclass 26, count 0 2006.252.08:01:59.89#ibcon#first serial, iclass 26, count 0 2006.252.08:01:59.89#ibcon#enter sib2, iclass 26, count 0 2006.252.08:01:59.89#ibcon#flushed, iclass 26, count 0 2006.252.08:01:59.89#ibcon#about to write, iclass 26, count 0 2006.252.08:01:59.89#ibcon#wrote, iclass 26, count 0 2006.252.08:01:59.89#ibcon#about to read 3, iclass 26, count 0 2006.252.08:01:59.91#ibcon#read 3, iclass 26, count 0 2006.252.08:01:59.91#ibcon#about to read 4, iclass 26, count 0 2006.252.08:01:59.91#ibcon#read 4, iclass 26, count 0 2006.252.08:01:59.91#ibcon#about to read 5, iclass 26, count 0 2006.252.08:01:59.91#ibcon#read 5, iclass 26, count 0 2006.252.08:01:59.91#ibcon#about to read 6, iclass 26, count 0 2006.252.08:01:59.91#ibcon#read 6, iclass 26, count 0 2006.252.08:01:59.91#ibcon#end of sib2, iclass 26, count 0 2006.252.08:01:59.91#ibcon#*mode == 0, iclass 26, count 0 2006.252.08:01:59.91#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.252.08:01:59.91#ibcon#[25=USB\r\n] 2006.252.08:01:59.91#ibcon#*before write, iclass 26, count 0 2006.252.08:01:59.91#ibcon#enter sib2, iclass 26, count 0 2006.252.08:01:59.91#ibcon#flushed, iclass 26, count 0 2006.252.08:01:59.91#ibcon#about to write, iclass 26, count 0 2006.252.08:01:59.91#ibcon#wrote, iclass 26, count 0 2006.252.08:01:59.91#ibcon#about to read 3, iclass 26, count 0 2006.252.08:01:59.94#ibcon#read 3, iclass 26, count 0 2006.252.08:01:59.94#ibcon#about to read 4, iclass 26, count 0 2006.252.08:01:59.94#ibcon#read 4, iclass 26, count 0 2006.252.08:01:59.94#ibcon#about to read 5, iclass 26, count 0 2006.252.08:01:59.94#ibcon#read 5, iclass 26, count 0 2006.252.08:01:59.94#ibcon#about to read 6, iclass 26, count 0 2006.252.08:01:59.94#ibcon#read 6, iclass 26, count 0 2006.252.08:01:59.94#ibcon#end of sib2, iclass 26, count 0 2006.252.08:01:59.94#ibcon#*after write, iclass 26, count 0 2006.252.08:01:59.94#ibcon#*before return 0, iclass 26, count 0 2006.252.08:01:59.94#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.252.08:01:59.94#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.252.08:01:59.94#ibcon#about to clear, iclass 26 cls_cnt 0 2006.252.08:01:59.94#ibcon#cleared, iclass 26 cls_cnt 0 2006.252.08:01:59.94$vc4f8/valo=7,832.99 2006.252.08:01:59.94#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.252.08:01:59.94#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.252.08:01:59.94#ibcon#ireg 17 cls_cnt 0 2006.252.08:01:59.94#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.252.08:01:59.94#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.252.08:01:59.94#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.252.08:01:59.94#ibcon#enter wrdev, iclass 28, count 0 2006.252.08:01:59.94#ibcon#first serial, iclass 28, count 0 2006.252.08:01:59.94#ibcon#enter sib2, iclass 28, count 0 2006.252.08:01:59.94#ibcon#flushed, iclass 28, count 0 2006.252.08:01:59.94#ibcon#about to write, iclass 28, count 0 2006.252.08:01:59.94#ibcon#wrote, iclass 28, count 0 2006.252.08:01:59.94#ibcon#about to read 3, iclass 28, count 0 2006.252.08:01:59.96#ibcon#read 3, iclass 28, count 0 2006.252.08:01:59.96#ibcon#about to read 4, iclass 28, count 0 2006.252.08:01:59.96#ibcon#read 4, iclass 28, count 0 2006.252.08:01:59.96#ibcon#about to read 5, iclass 28, count 0 2006.252.08:01:59.96#ibcon#read 5, iclass 28, count 0 2006.252.08:01:59.96#ibcon#about to read 6, iclass 28, count 0 2006.252.08:01:59.96#ibcon#read 6, iclass 28, count 0 2006.252.08:01:59.96#ibcon#end of sib2, iclass 28, count 0 2006.252.08:01:59.96#ibcon#*mode == 0, iclass 28, count 0 2006.252.08:01:59.96#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.252.08:01:59.96#ibcon#[26=FRQ=07,832.99\r\n] 2006.252.08:01:59.96#ibcon#*before write, iclass 28, count 0 2006.252.08:01:59.96#ibcon#enter sib2, iclass 28, count 0 2006.252.08:01:59.96#ibcon#flushed, iclass 28, count 0 2006.252.08:01:59.96#ibcon#about to write, iclass 28, count 0 2006.252.08:01:59.96#ibcon#wrote, iclass 28, count 0 2006.252.08:01:59.96#ibcon#about to read 3, iclass 28, count 0 2006.252.08:02:00.00#ibcon#read 3, iclass 28, count 0 2006.252.08:02:00.00#ibcon#about to read 4, iclass 28, count 0 2006.252.08:02:00.00#ibcon#read 4, iclass 28, count 0 2006.252.08:02:00.00#ibcon#about to read 5, iclass 28, count 0 2006.252.08:02:00.00#ibcon#read 5, iclass 28, count 0 2006.252.08:02:00.00#ibcon#about to read 6, iclass 28, count 0 2006.252.08:02:00.00#ibcon#read 6, iclass 28, count 0 2006.252.08:02:00.00#ibcon#end of sib2, iclass 28, count 0 2006.252.08:02:00.00#ibcon#*after write, iclass 28, count 0 2006.252.08:02:00.00#ibcon#*before return 0, iclass 28, count 0 2006.252.08:02:00.00#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.252.08:02:00.00#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.252.08:02:00.00#ibcon#about to clear, iclass 28 cls_cnt 0 2006.252.08:02:00.00#ibcon#cleared, iclass 28 cls_cnt 0 2006.252.08:02:00.00$vc4f8/va=7,7 2006.252.08:02:00.00#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.252.08:02:00.00#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.252.08:02:00.00#ibcon#ireg 11 cls_cnt 2 2006.252.08:02:00.00#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.252.08:02:00.06#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.252.08:02:00.06#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.252.08:02:00.06#ibcon#enter wrdev, iclass 30, count 2 2006.252.08:02:00.06#ibcon#first serial, iclass 30, count 2 2006.252.08:02:00.06#ibcon#enter sib2, iclass 30, count 2 2006.252.08:02:00.06#ibcon#flushed, iclass 30, count 2 2006.252.08:02:00.06#ibcon#about to write, iclass 30, count 2 2006.252.08:02:00.06#ibcon#wrote, iclass 30, count 2 2006.252.08:02:00.06#ibcon#about to read 3, iclass 30, count 2 2006.252.08:02:00.08#ibcon#read 3, iclass 30, count 2 2006.252.08:02:00.08#ibcon#about to read 4, iclass 30, count 2 2006.252.08:02:00.08#ibcon#read 4, iclass 30, count 2 2006.252.08:02:00.08#ibcon#about to read 5, iclass 30, count 2 2006.252.08:02:00.08#ibcon#read 5, iclass 30, count 2 2006.252.08:02:00.08#ibcon#about to read 6, iclass 30, count 2 2006.252.08:02:00.08#ibcon#read 6, iclass 30, count 2 2006.252.08:02:00.08#ibcon#end of sib2, iclass 30, count 2 2006.252.08:02:00.08#ibcon#*mode == 0, iclass 30, count 2 2006.252.08:02:00.08#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.252.08:02:00.08#ibcon#[25=AT07-07\r\n] 2006.252.08:02:00.08#ibcon#*before write, iclass 30, count 2 2006.252.08:02:00.08#ibcon#enter sib2, iclass 30, count 2 2006.252.08:02:00.08#ibcon#flushed, iclass 30, count 2 2006.252.08:02:00.08#ibcon#about to write, iclass 30, count 2 2006.252.08:02:00.08#ibcon#wrote, iclass 30, count 2 2006.252.08:02:00.08#ibcon#about to read 3, iclass 30, count 2 2006.252.08:02:00.11#ibcon#read 3, iclass 30, count 2 2006.252.08:02:00.11#ibcon#about to read 4, iclass 30, count 2 2006.252.08:02:00.11#ibcon#read 4, iclass 30, count 2 2006.252.08:02:00.11#ibcon#about to read 5, iclass 30, count 2 2006.252.08:02:00.11#ibcon#read 5, iclass 30, count 2 2006.252.08:02:00.11#ibcon#about to read 6, iclass 30, count 2 2006.252.08:02:00.11#ibcon#read 6, iclass 30, count 2 2006.252.08:02:00.11#ibcon#end of sib2, iclass 30, count 2 2006.252.08:02:00.11#ibcon#*after write, iclass 30, count 2 2006.252.08:02:00.11#ibcon#*before return 0, iclass 30, count 2 2006.252.08:02:00.11#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.252.08:02:00.11#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.252.08:02:00.11#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.252.08:02:00.11#ibcon#ireg 7 cls_cnt 0 2006.252.08:02:00.11#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.252.08:02:00.23#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.252.08:02:00.23#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.252.08:02:00.23#ibcon#enter wrdev, iclass 30, count 0 2006.252.08:02:00.23#ibcon#first serial, iclass 30, count 0 2006.252.08:02:00.23#ibcon#enter sib2, iclass 30, count 0 2006.252.08:02:00.23#ibcon#flushed, iclass 30, count 0 2006.252.08:02:00.23#ibcon#about to write, iclass 30, count 0 2006.252.08:02:00.23#ibcon#wrote, iclass 30, count 0 2006.252.08:02:00.23#ibcon#about to read 3, iclass 30, count 0 2006.252.08:02:00.25#ibcon#read 3, iclass 30, count 0 2006.252.08:02:00.25#ibcon#about to read 4, iclass 30, count 0 2006.252.08:02:00.25#ibcon#read 4, iclass 30, count 0 2006.252.08:02:00.25#ibcon#about to read 5, iclass 30, count 0 2006.252.08:02:00.25#ibcon#read 5, iclass 30, count 0 2006.252.08:02:00.25#ibcon#about to read 6, iclass 30, count 0 2006.252.08:02:00.25#ibcon#read 6, iclass 30, count 0 2006.252.08:02:00.25#ibcon#end of sib2, iclass 30, count 0 2006.252.08:02:00.25#ibcon#*mode == 0, iclass 30, count 0 2006.252.08:02:00.25#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.252.08:02:00.25#ibcon#[25=USB\r\n] 2006.252.08:02:00.25#ibcon#*before write, iclass 30, count 0 2006.252.08:02:00.25#ibcon#enter sib2, iclass 30, count 0 2006.252.08:02:00.25#ibcon#flushed, iclass 30, count 0 2006.252.08:02:00.25#ibcon#about to write, iclass 30, count 0 2006.252.08:02:00.25#ibcon#wrote, iclass 30, count 0 2006.252.08:02:00.25#ibcon#about to read 3, iclass 30, count 0 2006.252.08:02:00.28#ibcon#read 3, iclass 30, count 0 2006.252.08:02:00.28#ibcon#about to read 4, iclass 30, count 0 2006.252.08:02:00.28#ibcon#read 4, iclass 30, count 0 2006.252.08:02:00.28#ibcon#about to read 5, iclass 30, count 0 2006.252.08:02:00.28#ibcon#read 5, iclass 30, count 0 2006.252.08:02:00.28#ibcon#about to read 6, iclass 30, count 0 2006.252.08:02:00.28#ibcon#read 6, iclass 30, count 0 2006.252.08:02:00.28#ibcon#end of sib2, iclass 30, count 0 2006.252.08:02:00.28#ibcon#*after write, iclass 30, count 0 2006.252.08:02:00.28#ibcon#*before return 0, iclass 30, count 0 2006.252.08:02:00.28#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.252.08:02:00.28#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.252.08:02:00.28#ibcon#about to clear, iclass 30 cls_cnt 0 2006.252.08:02:00.28#ibcon#cleared, iclass 30 cls_cnt 0 2006.252.08:02:00.28$vc4f8/valo=8,852.99 2006.252.08:02:00.28#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.252.08:02:00.28#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.252.08:02:00.28#ibcon#ireg 17 cls_cnt 0 2006.252.08:02:00.28#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.252.08:02:00.28#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.252.08:02:00.28#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.252.08:02:00.28#ibcon#enter wrdev, iclass 32, count 0 2006.252.08:02:00.28#ibcon#first serial, iclass 32, count 0 2006.252.08:02:00.28#ibcon#enter sib2, iclass 32, count 0 2006.252.08:02:00.28#ibcon#flushed, iclass 32, count 0 2006.252.08:02:00.28#ibcon#about to write, iclass 32, count 0 2006.252.08:02:00.28#ibcon#wrote, iclass 32, count 0 2006.252.08:02:00.28#ibcon#about to read 3, iclass 32, count 0 2006.252.08:02:00.30#ibcon#read 3, iclass 32, count 0 2006.252.08:02:00.30#ibcon#about to read 4, iclass 32, count 0 2006.252.08:02:00.30#ibcon#read 4, iclass 32, count 0 2006.252.08:02:00.30#ibcon#about to read 5, iclass 32, count 0 2006.252.08:02:00.30#ibcon#read 5, iclass 32, count 0 2006.252.08:02:00.30#ibcon#about to read 6, iclass 32, count 0 2006.252.08:02:00.30#ibcon#read 6, iclass 32, count 0 2006.252.08:02:00.30#ibcon#end of sib2, iclass 32, count 0 2006.252.08:02:00.30#ibcon#*mode == 0, iclass 32, count 0 2006.252.08:02:00.30#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.252.08:02:00.30#ibcon#[26=FRQ=08,852.99\r\n] 2006.252.08:02:00.30#ibcon#*before write, iclass 32, count 0 2006.252.08:02:00.30#ibcon#enter sib2, iclass 32, count 0 2006.252.08:02:00.30#ibcon#flushed, iclass 32, count 0 2006.252.08:02:00.30#ibcon#about to write, iclass 32, count 0 2006.252.08:02:00.30#ibcon#wrote, iclass 32, count 0 2006.252.08:02:00.30#ibcon#about to read 3, iclass 32, count 0 2006.252.08:02:00.34#ibcon#read 3, iclass 32, count 0 2006.252.08:02:00.34#ibcon#about to read 4, iclass 32, count 0 2006.252.08:02:00.34#ibcon#read 4, iclass 32, count 0 2006.252.08:02:00.34#ibcon#about to read 5, iclass 32, count 0 2006.252.08:02:00.34#ibcon#read 5, iclass 32, count 0 2006.252.08:02:00.34#ibcon#about to read 6, iclass 32, count 0 2006.252.08:02:00.34#ibcon#read 6, iclass 32, count 0 2006.252.08:02:00.34#ibcon#end of sib2, iclass 32, count 0 2006.252.08:02:00.34#ibcon#*after write, iclass 32, count 0 2006.252.08:02:00.34#ibcon#*before return 0, iclass 32, count 0 2006.252.08:02:00.34#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.252.08:02:00.34#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.252.08:02:00.34#ibcon#about to clear, iclass 32 cls_cnt 0 2006.252.08:02:00.34#ibcon#cleared, iclass 32 cls_cnt 0 2006.252.08:02:00.34$vc4f8/va=8,7 2006.252.08:02:00.34#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.252.08:02:00.34#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.252.08:02:00.34#ibcon#ireg 11 cls_cnt 2 2006.252.08:02:00.34#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.252.08:02:00.40#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.252.08:02:00.40#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.252.08:02:00.40#ibcon#enter wrdev, iclass 34, count 2 2006.252.08:02:00.40#ibcon#first serial, iclass 34, count 2 2006.252.08:02:00.40#ibcon#enter sib2, iclass 34, count 2 2006.252.08:02:00.40#ibcon#flushed, iclass 34, count 2 2006.252.08:02:00.40#ibcon#about to write, iclass 34, count 2 2006.252.08:02:00.40#ibcon#wrote, iclass 34, count 2 2006.252.08:02:00.40#ibcon#about to read 3, iclass 34, count 2 2006.252.08:02:00.42#ibcon#read 3, iclass 34, count 2 2006.252.08:02:00.42#ibcon#about to read 4, iclass 34, count 2 2006.252.08:02:00.42#ibcon#read 4, iclass 34, count 2 2006.252.08:02:00.42#ibcon#about to read 5, iclass 34, count 2 2006.252.08:02:00.42#ibcon#read 5, iclass 34, count 2 2006.252.08:02:00.42#ibcon#about to read 6, iclass 34, count 2 2006.252.08:02:00.42#ibcon#read 6, iclass 34, count 2 2006.252.08:02:00.42#ibcon#end of sib2, iclass 34, count 2 2006.252.08:02:00.42#ibcon#*mode == 0, iclass 34, count 2 2006.252.08:02:00.42#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.252.08:02:00.42#ibcon#[25=AT08-07\r\n] 2006.252.08:02:00.42#ibcon#*before write, iclass 34, count 2 2006.252.08:02:00.42#ibcon#enter sib2, iclass 34, count 2 2006.252.08:02:00.42#ibcon#flushed, iclass 34, count 2 2006.252.08:02:00.42#ibcon#about to write, iclass 34, count 2 2006.252.08:02:00.42#ibcon#wrote, iclass 34, count 2 2006.252.08:02:00.42#ibcon#about to read 3, iclass 34, count 2 2006.252.08:02:00.45#ibcon#read 3, iclass 34, count 2 2006.252.08:02:00.45#ibcon#about to read 4, iclass 34, count 2 2006.252.08:02:00.45#ibcon#read 4, iclass 34, count 2 2006.252.08:02:00.45#ibcon#about to read 5, iclass 34, count 2 2006.252.08:02:00.45#ibcon#read 5, iclass 34, count 2 2006.252.08:02:00.45#ibcon#about to read 6, iclass 34, count 2 2006.252.08:02:00.45#ibcon#read 6, iclass 34, count 2 2006.252.08:02:00.45#ibcon#end of sib2, iclass 34, count 2 2006.252.08:02:00.45#ibcon#*after write, iclass 34, count 2 2006.252.08:02:00.45#ibcon#*before return 0, iclass 34, count 2 2006.252.08:02:00.45#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.252.08:02:00.45#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.252.08:02:00.45#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.252.08:02:00.45#ibcon#ireg 7 cls_cnt 0 2006.252.08:02:00.45#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.252.08:02:00.57#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.252.08:02:00.57#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.252.08:02:00.57#ibcon#enter wrdev, iclass 34, count 0 2006.252.08:02:00.57#ibcon#first serial, iclass 34, count 0 2006.252.08:02:00.57#ibcon#enter sib2, iclass 34, count 0 2006.252.08:02:00.57#ibcon#flushed, iclass 34, count 0 2006.252.08:02:00.57#ibcon#about to write, iclass 34, count 0 2006.252.08:02:00.57#ibcon#wrote, iclass 34, count 0 2006.252.08:02:00.57#ibcon#about to read 3, iclass 34, count 0 2006.252.08:02:00.59#ibcon#read 3, iclass 34, count 0 2006.252.08:02:00.59#ibcon#about to read 4, iclass 34, count 0 2006.252.08:02:00.59#ibcon#read 4, iclass 34, count 0 2006.252.08:02:00.59#ibcon#about to read 5, iclass 34, count 0 2006.252.08:02:00.59#ibcon#read 5, iclass 34, count 0 2006.252.08:02:00.59#ibcon#about to read 6, iclass 34, count 0 2006.252.08:02:00.59#ibcon#read 6, iclass 34, count 0 2006.252.08:02:00.59#ibcon#end of sib2, iclass 34, count 0 2006.252.08:02:00.59#ibcon#*mode == 0, iclass 34, count 0 2006.252.08:02:00.59#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.252.08:02:00.59#ibcon#[25=USB\r\n] 2006.252.08:02:00.59#ibcon#*before write, iclass 34, count 0 2006.252.08:02:00.59#ibcon#enter sib2, iclass 34, count 0 2006.252.08:02:00.59#ibcon#flushed, iclass 34, count 0 2006.252.08:02:00.59#ibcon#about to write, iclass 34, count 0 2006.252.08:02:00.59#ibcon#wrote, iclass 34, count 0 2006.252.08:02:00.59#ibcon#about to read 3, iclass 34, count 0 2006.252.08:02:00.62#ibcon#read 3, iclass 34, count 0 2006.252.08:02:00.62#ibcon#about to read 4, iclass 34, count 0 2006.252.08:02:00.62#ibcon#read 4, iclass 34, count 0 2006.252.08:02:00.62#ibcon#about to read 5, iclass 34, count 0 2006.252.08:02:00.62#ibcon#read 5, iclass 34, count 0 2006.252.08:02:00.62#ibcon#about to read 6, iclass 34, count 0 2006.252.08:02:00.62#ibcon#read 6, iclass 34, count 0 2006.252.08:02:00.62#ibcon#end of sib2, iclass 34, count 0 2006.252.08:02:00.62#ibcon#*after write, iclass 34, count 0 2006.252.08:02:00.62#ibcon#*before return 0, iclass 34, count 0 2006.252.08:02:00.62#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.252.08:02:00.62#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.252.08:02:00.62#ibcon#about to clear, iclass 34 cls_cnt 0 2006.252.08:02:00.62#ibcon#cleared, iclass 34 cls_cnt 0 2006.252.08:02:00.62$vc4f8/vblo=1,632.99 2006.252.08:02:00.62#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.252.08:02:00.62#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.252.08:02:00.62#ibcon#ireg 17 cls_cnt 0 2006.252.08:02:00.62#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.252.08:02:00.62#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.252.08:02:00.62#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.252.08:02:00.62#ibcon#enter wrdev, iclass 36, count 0 2006.252.08:02:00.62#ibcon#first serial, iclass 36, count 0 2006.252.08:02:00.62#ibcon#enter sib2, iclass 36, count 0 2006.252.08:02:00.62#ibcon#flushed, iclass 36, count 0 2006.252.08:02:00.62#ibcon#about to write, iclass 36, count 0 2006.252.08:02:00.62#ibcon#wrote, iclass 36, count 0 2006.252.08:02:00.62#ibcon#about to read 3, iclass 36, count 0 2006.252.08:02:00.64#ibcon#read 3, iclass 36, count 0 2006.252.08:02:00.64#ibcon#about to read 4, iclass 36, count 0 2006.252.08:02:00.64#ibcon#read 4, iclass 36, count 0 2006.252.08:02:00.64#ibcon#about to read 5, iclass 36, count 0 2006.252.08:02:00.64#ibcon#read 5, iclass 36, count 0 2006.252.08:02:00.64#ibcon#about to read 6, iclass 36, count 0 2006.252.08:02:00.64#ibcon#read 6, iclass 36, count 0 2006.252.08:02:00.64#ibcon#end of sib2, iclass 36, count 0 2006.252.08:02:00.64#ibcon#*mode == 0, iclass 36, count 0 2006.252.08:02:00.64#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.252.08:02:00.64#ibcon#[28=FRQ=01,632.99\r\n] 2006.252.08:02:00.64#ibcon#*before write, iclass 36, count 0 2006.252.08:02:00.64#ibcon#enter sib2, iclass 36, count 0 2006.252.08:02:00.64#ibcon#flushed, iclass 36, count 0 2006.252.08:02:00.64#ibcon#about to write, iclass 36, count 0 2006.252.08:02:00.64#ibcon#wrote, iclass 36, count 0 2006.252.08:02:00.64#ibcon#about to read 3, iclass 36, count 0 2006.252.08:02:00.69#ibcon#read 3, iclass 36, count 0 2006.252.08:02:00.69#ibcon#about to read 4, iclass 36, count 0 2006.252.08:02:00.69#ibcon#read 4, iclass 36, count 0 2006.252.08:02:00.69#ibcon#about to read 5, iclass 36, count 0 2006.252.08:02:00.69#ibcon#read 5, iclass 36, count 0 2006.252.08:02:00.69#ibcon#about to read 6, iclass 36, count 0 2006.252.08:02:00.69#ibcon#read 6, iclass 36, count 0 2006.252.08:02:00.69#ibcon#end of sib2, iclass 36, count 0 2006.252.08:02:00.69#ibcon#*after write, iclass 36, count 0 2006.252.08:02:00.69#ibcon#*before return 0, iclass 36, count 0 2006.252.08:02:00.69#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.252.08:02:00.69#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.252.08:02:00.69#ibcon#about to clear, iclass 36 cls_cnt 0 2006.252.08:02:00.69#ibcon#cleared, iclass 36 cls_cnt 0 2006.252.08:02:00.69$vc4f8/vb=1,4 2006.252.08:02:00.69#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.252.08:02:00.69#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.252.08:02:00.69#ibcon#ireg 11 cls_cnt 2 2006.252.08:02:00.69#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.252.08:02:00.69#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.252.08:02:00.69#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.252.08:02:00.69#ibcon#enter wrdev, iclass 38, count 2 2006.252.08:02:00.69#ibcon#first serial, iclass 38, count 2 2006.252.08:02:00.69#ibcon#enter sib2, iclass 38, count 2 2006.252.08:02:00.69#ibcon#flushed, iclass 38, count 2 2006.252.08:02:00.69#ibcon#about to write, iclass 38, count 2 2006.252.08:02:00.69#ibcon#wrote, iclass 38, count 2 2006.252.08:02:00.69#ibcon#about to read 3, iclass 38, count 2 2006.252.08:02:00.71#ibcon#read 3, iclass 38, count 2 2006.252.08:02:00.71#ibcon#about to read 4, iclass 38, count 2 2006.252.08:02:00.71#ibcon#read 4, iclass 38, count 2 2006.252.08:02:00.71#ibcon#about to read 5, iclass 38, count 2 2006.252.08:02:00.71#ibcon#read 5, iclass 38, count 2 2006.252.08:02:00.71#ibcon#about to read 6, iclass 38, count 2 2006.252.08:02:00.71#ibcon#read 6, iclass 38, count 2 2006.252.08:02:00.71#ibcon#end of sib2, iclass 38, count 2 2006.252.08:02:00.71#ibcon#*mode == 0, iclass 38, count 2 2006.252.08:02:00.71#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.252.08:02:00.71#ibcon#[27=AT01-04\r\n] 2006.252.08:02:00.71#ibcon#*before write, iclass 38, count 2 2006.252.08:02:00.71#ibcon#enter sib2, iclass 38, count 2 2006.252.08:02:00.71#ibcon#flushed, iclass 38, count 2 2006.252.08:02:00.71#ibcon#about to write, iclass 38, count 2 2006.252.08:02:00.71#ibcon#wrote, iclass 38, count 2 2006.252.08:02:00.71#ibcon#about to read 3, iclass 38, count 2 2006.252.08:02:00.74#ibcon#read 3, iclass 38, count 2 2006.252.08:02:00.74#ibcon#about to read 4, iclass 38, count 2 2006.252.08:02:00.74#ibcon#read 4, iclass 38, count 2 2006.252.08:02:00.74#ibcon#about to read 5, iclass 38, count 2 2006.252.08:02:00.74#ibcon#read 5, iclass 38, count 2 2006.252.08:02:00.74#ibcon#about to read 6, iclass 38, count 2 2006.252.08:02:00.74#ibcon#read 6, iclass 38, count 2 2006.252.08:02:00.74#ibcon#end of sib2, iclass 38, count 2 2006.252.08:02:00.74#ibcon#*after write, iclass 38, count 2 2006.252.08:02:00.74#ibcon#*before return 0, iclass 38, count 2 2006.252.08:02:00.74#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.252.08:02:00.74#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.252.08:02:00.74#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.252.08:02:00.74#ibcon#ireg 7 cls_cnt 0 2006.252.08:02:00.74#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.252.08:02:00.86#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.252.08:02:00.86#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.252.08:02:00.86#ibcon#enter wrdev, iclass 38, count 0 2006.252.08:02:00.86#ibcon#first serial, iclass 38, count 0 2006.252.08:02:00.86#ibcon#enter sib2, iclass 38, count 0 2006.252.08:02:00.86#ibcon#flushed, iclass 38, count 0 2006.252.08:02:00.86#ibcon#about to write, iclass 38, count 0 2006.252.08:02:00.86#ibcon#wrote, iclass 38, count 0 2006.252.08:02:00.86#ibcon#about to read 3, iclass 38, count 0 2006.252.08:02:00.88#ibcon#read 3, iclass 38, count 0 2006.252.08:02:00.88#ibcon#about to read 4, iclass 38, count 0 2006.252.08:02:00.88#ibcon#read 4, iclass 38, count 0 2006.252.08:02:00.88#ibcon#about to read 5, iclass 38, count 0 2006.252.08:02:00.88#ibcon#read 5, iclass 38, count 0 2006.252.08:02:00.88#ibcon#about to read 6, iclass 38, count 0 2006.252.08:02:00.88#ibcon#read 6, iclass 38, count 0 2006.252.08:02:00.88#ibcon#end of sib2, iclass 38, count 0 2006.252.08:02:00.88#ibcon#*mode == 0, iclass 38, count 0 2006.252.08:02:00.88#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.252.08:02:00.88#ibcon#[27=USB\r\n] 2006.252.08:02:00.88#ibcon#*before write, iclass 38, count 0 2006.252.08:02:00.88#ibcon#enter sib2, iclass 38, count 0 2006.252.08:02:00.88#ibcon#flushed, iclass 38, count 0 2006.252.08:02:00.88#ibcon#about to write, iclass 38, count 0 2006.252.08:02:00.88#ibcon#wrote, iclass 38, count 0 2006.252.08:02:00.88#ibcon#about to read 3, iclass 38, count 0 2006.252.08:02:00.91#ibcon#read 3, iclass 38, count 0 2006.252.08:02:00.91#ibcon#about to read 4, iclass 38, count 0 2006.252.08:02:00.91#ibcon#read 4, iclass 38, count 0 2006.252.08:02:00.91#ibcon#about to read 5, iclass 38, count 0 2006.252.08:02:00.91#ibcon#read 5, iclass 38, count 0 2006.252.08:02:00.91#ibcon#about to read 6, iclass 38, count 0 2006.252.08:02:00.91#ibcon#read 6, iclass 38, count 0 2006.252.08:02:00.91#ibcon#end of sib2, iclass 38, count 0 2006.252.08:02:00.91#ibcon#*after write, iclass 38, count 0 2006.252.08:02:00.91#ibcon#*before return 0, iclass 38, count 0 2006.252.08:02:00.91#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.252.08:02:00.91#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.252.08:02:00.91#ibcon#about to clear, iclass 38 cls_cnt 0 2006.252.08:02:00.91#ibcon#cleared, iclass 38 cls_cnt 0 2006.252.08:02:00.91$vc4f8/vblo=2,640.99 2006.252.08:02:00.91#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.252.08:02:00.91#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.252.08:02:00.91#ibcon#ireg 17 cls_cnt 0 2006.252.08:02:00.91#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.252.08:02:00.91#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.252.08:02:00.91#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.252.08:02:00.91#ibcon#enter wrdev, iclass 40, count 0 2006.252.08:02:00.91#ibcon#first serial, iclass 40, count 0 2006.252.08:02:00.91#ibcon#enter sib2, iclass 40, count 0 2006.252.08:02:00.91#ibcon#flushed, iclass 40, count 0 2006.252.08:02:00.91#ibcon#about to write, iclass 40, count 0 2006.252.08:02:00.91#ibcon#wrote, iclass 40, count 0 2006.252.08:02:00.91#ibcon#about to read 3, iclass 40, count 0 2006.252.08:02:00.93#ibcon#read 3, iclass 40, count 0 2006.252.08:02:00.93#ibcon#about to read 4, iclass 40, count 0 2006.252.08:02:00.93#ibcon#read 4, iclass 40, count 0 2006.252.08:02:00.93#ibcon#about to read 5, iclass 40, count 0 2006.252.08:02:00.93#ibcon#read 5, iclass 40, count 0 2006.252.08:02:00.93#ibcon#about to read 6, iclass 40, count 0 2006.252.08:02:00.93#ibcon#read 6, iclass 40, count 0 2006.252.08:02:00.93#ibcon#end of sib2, iclass 40, count 0 2006.252.08:02:00.93#ibcon#*mode == 0, iclass 40, count 0 2006.252.08:02:00.93#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.252.08:02:00.93#ibcon#[28=FRQ=02,640.99\r\n] 2006.252.08:02:00.93#ibcon#*before write, iclass 40, count 0 2006.252.08:02:00.93#ibcon#enter sib2, iclass 40, count 0 2006.252.08:02:00.93#ibcon#flushed, iclass 40, count 0 2006.252.08:02:00.93#ibcon#about to write, iclass 40, count 0 2006.252.08:02:00.93#ibcon#wrote, iclass 40, count 0 2006.252.08:02:00.93#ibcon#about to read 3, iclass 40, count 0 2006.252.08:02:00.97#ibcon#read 3, iclass 40, count 0 2006.252.08:02:00.97#ibcon#about to read 4, iclass 40, count 0 2006.252.08:02:00.97#ibcon#read 4, iclass 40, count 0 2006.252.08:02:00.97#ibcon#about to read 5, iclass 40, count 0 2006.252.08:02:00.97#ibcon#read 5, iclass 40, count 0 2006.252.08:02:00.97#ibcon#about to read 6, iclass 40, count 0 2006.252.08:02:00.97#ibcon#read 6, iclass 40, count 0 2006.252.08:02:00.97#ibcon#end of sib2, iclass 40, count 0 2006.252.08:02:00.97#ibcon#*after write, iclass 40, count 0 2006.252.08:02:00.97#ibcon#*before return 0, iclass 40, count 0 2006.252.08:02:00.97#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.252.08:02:00.97#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.252.08:02:00.97#ibcon#about to clear, iclass 40 cls_cnt 0 2006.252.08:02:00.97#ibcon#cleared, iclass 40 cls_cnt 0 2006.252.08:02:00.97$vc4f8/vb=2,5 2006.252.08:02:00.97#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.252.08:02:00.97#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.252.08:02:00.97#ibcon#ireg 11 cls_cnt 2 2006.252.08:02:00.97#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.252.08:02:01.03#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.252.08:02:01.03#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.252.08:02:01.03#ibcon#enter wrdev, iclass 4, count 2 2006.252.08:02:01.03#ibcon#first serial, iclass 4, count 2 2006.252.08:02:01.03#ibcon#enter sib2, iclass 4, count 2 2006.252.08:02:01.03#ibcon#flushed, iclass 4, count 2 2006.252.08:02:01.03#ibcon#about to write, iclass 4, count 2 2006.252.08:02:01.03#ibcon#wrote, iclass 4, count 2 2006.252.08:02:01.03#ibcon#about to read 3, iclass 4, count 2 2006.252.08:02:01.05#ibcon#read 3, iclass 4, count 2 2006.252.08:02:01.05#ibcon#about to read 4, iclass 4, count 2 2006.252.08:02:01.05#ibcon#read 4, iclass 4, count 2 2006.252.08:02:01.05#ibcon#about to read 5, iclass 4, count 2 2006.252.08:02:01.05#ibcon#read 5, iclass 4, count 2 2006.252.08:02:01.05#ibcon#about to read 6, iclass 4, count 2 2006.252.08:02:01.05#ibcon#read 6, iclass 4, count 2 2006.252.08:02:01.05#ibcon#end of sib2, iclass 4, count 2 2006.252.08:02:01.05#ibcon#*mode == 0, iclass 4, count 2 2006.252.08:02:01.05#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.252.08:02:01.05#ibcon#[27=AT02-05\r\n] 2006.252.08:02:01.05#ibcon#*before write, iclass 4, count 2 2006.252.08:02:01.05#ibcon#enter sib2, iclass 4, count 2 2006.252.08:02:01.05#ibcon#flushed, iclass 4, count 2 2006.252.08:02:01.05#ibcon#about to write, iclass 4, count 2 2006.252.08:02:01.05#ibcon#wrote, iclass 4, count 2 2006.252.08:02:01.05#ibcon#about to read 3, iclass 4, count 2 2006.252.08:02:01.08#ibcon#read 3, iclass 4, count 2 2006.252.08:02:01.08#ibcon#about to read 4, iclass 4, count 2 2006.252.08:02:01.08#ibcon#read 4, iclass 4, count 2 2006.252.08:02:01.08#ibcon#about to read 5, iclass 4, count 2 2006.252.08:02:01.08#ibcon#read 5, iclass 4, count 2 2006.252.08:02:01.08#ibcon#about to read 6, iclass 4, count 2 2006.252.08:02:01.08#ibcon#read 6, iclass 4, count 2 2006.252.08:02:01.08#ibcon#end of sib2, iclass 4, count 2 2006.252.08:02:01.08#ibcon#*after write, iclass 4, count 2 2006.252.08:02:01.08#ibcon#*before return 0, iclass 4, count 2 2006.252.08:02:01.08#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.252.08:02:01.08#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.252.08:02:01.08#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.252.08:02:01.08#ibcon#ireg 7 cls_cnt 0 2006.252.08:02:01.08#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.252.08:02:01.20#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.252.08:02:01.20#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.252.08:02:01.20#ibcon#enter wrdev, iclass 4, count 0 2006.252.08:02:01.20#ibcon#first serial, iclass 4, count 0 2006.252.08:02:01.20#ibcon#enter sib2, iclass 4, count 0 2006.252.08:02:01.20#ibcon#flushed, iclass 4, count 0 2006.252.08:02:01.20#ibcon#about to write, iclass 4, count 0 2006.252.08:02:01.20#ibcon#wrote, iclass 4, count 0 2006.252.08:02:01.20#ibcon#about to read 3, iclass 4, count 0 2006.252.08:02:01.22#ibcon#read 3, iclass 4, count 0 2006.252.08:02:01.22#ibcon#about to read 4, iclass 4, count 0 2006.252.08:02:01.22#ibcon#read 4, iclass 4, count 0 2006.252.08:02:01.22#ibcon#about to read 5, iclass 4, count 0 2006.252.08:02:01.22#ibcon#read 5, iclass 4, count 0 2006.252.08:02:01.22#ibcon#about to read 6, iclass 4, count 0 2006.252.08:02:01.22#ibcon#read 6, iclass 4, count 0 2006.252.08:02:01.22#ibcon#end of sib2, iclass 4, count 0 2006.252.08:02:01.22#ibcon#*mode == 0, iclass 4, count 0 2006.252.08:02:01.22#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.252.08:02:01.22#ibcon#[27=USB\r\n] 2006.252.08:02:01.22#ibcon#*before write, iclass 4, count 0 2006.252.08:02:01.22#ibcon#enter sib2, iclass 4, count 0 2006.252.08:02:01.22#ibcon#flushed, iclass 4, count 0 2006.252.08:02:01.22#ibcon#about to write, iclass 4, count 0 2006.252.08:02:01.22#ibcon#wrote, iclass 4, count 0 2006.252.08:02:01.22#ibcon#about to read 3, iclass 4, count 0 2006.252.08:02:01.25#ibcon#read 3, iclass 4, count 0 2006.252.08:02:01.25#ibcon#about to read 4, iclass 4, count 0 2006.252.08:02:01.25#ibcon#read 4, iclass 4, count 0 2006.252.08:02:01.25#ibcon#about to read 5, iclass 4, count 0 2006.252.08:02:01.25#ibcon#read 5, iclass 4, count 0 2006.252.08:02:01.25#ibcon#about to read 6, iclass 4, count 0 2006.252.08:02:01.25#ibcon#read 6, iclass 4, count 0 2006.252.08:02:01.25#ibcon#end of sib2, iclass 4, count 0 2006.252.08:02:01.25#ibcon#*after write, iclass 4, count 0 2006.252.08:02:01.25#ibcon#*before return 0, iclass 4, count 0 2006.252.08:02:01.25#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.252.08:02:01.25#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.252.08:02:01.25#ibcon#about to clear, iclass 4 cls_cnt 0 2006.252.08:02:01.25#ibcon#cleared, iclass 4 cls_cnt 0 2006.252.08:02:01.25$vc4f8/vblo=3,656.99 2006.252.08:02:01.25#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.252.08:02:01.25#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.252.08:02:01.25#ibcon#ireg 17 cls_cnt 0 2006.252.08:02:01.25#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.252.08:02:01.25#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.252.08:02:01.25#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.252.08:02:01.25#ibcon#enter wrdev, iclass 6, count 0 2006.252.08:02:01.25#ibcon#first serial, iclass 6, count 0 2006.252.08:02:01.25#ibcon#enter sib2, iclass 6, count 0 2006.252.08:02:01.25#ibcon#flushed, iclass 6, count 0 2006.252.08:02:01.25#ibcon#about to write, iclass 6, count 0 2006.252.08:02:01.25#ibcon#wrote, iclass 6, count 0 2006.252.08:02:01.25#ibcon#about to read 3, iclass 6, count 0 2006.252.08:02:01.27#ibcon#read 3, iclass 6, count 0 2006.252.08:02:01.27#ibcon#about to read 4, iclass 6, count 0 2006.252.08:02:01.27#ibcon#read 4, iclass 6, count 0 2006.252.08:02:01.27#ibcon#about to read 5, iclass 6, count 0 2006.252.08:02:01.27#ibcon#read 5, iclass 6, count 0 2006.252.08:02:01.27#ibcon#about to read 6, iclass 6, count 0 2006.252.08:02:01.27#ibcon#read 6, iclass 6, count 0 2006.252.08:02:01.27#ibcon#end of sib2, iclass 6, count 0 2006.252.08:02:01.27#ibcon#*mode == 0, iclass 6, count 0 2006.252.08:02:01.27#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.252.08:02:01.27#ibcon#[28=FRQ=03,656.99\r\n] 2006.252.08:02:01.27#ibcon#*before write, iclass 6, count 0 2006.252.08:02:01.27#ibcon#enter sib2, iclass 6, count 0 2006.252.08:02:01.27#ibcon#flushed, iclass 6, count 0 2006.252.08:02:01.27#ibcon#about to write, iclass 6, count 0 2006.252.08:02:01.27#ibcon#wrote, iclass 6, count 0 2006.252.08:02:01.27#ibcon#about to read 3, iclass 6, count 0 2006.252.08:02:01.31#ibcon#read 3, iclass 6, count 0 2006.252.08:02:01.31#ibcon#about to read 4, iclass 6, count 0 2006.252.08:02:01.31#ibcon#read 4, iclass 6, count 0 2006.252.08:02:01.31#ibcon#about to read 5, iclass 6, count 0 2006.252.08:02:01.31#ibcon#read 5, iclass 6, count 0 2006.252.08:02:01.31#ibcon#about to read 6, iclass 6, count 0 2006.252.08:02:01.31#ibcon#read 6, iclass 6, count 0 2006.252.08:02:01.31#ibcon#end of sib2, iclass 6, count 0 2006.252.08:02:01.31#ibcon#*after write, iclass 6, count 0 2006.252.08:02:01.31#ibcon#*before return 0, iclass 6, count 0 2006.252.08:02:01.31#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.252.08:02:01.31#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.252.08:02:01.31#ibcon#about to clear, iclass 6 cls_cnt 0 2006.252.08:02:01.31#ibcon#cleared, iclass 6 cls_cnt 0 2006.252.08:02:01.31$vc4f8/vb=3,4 2006.252.08:02:01.31#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.252.08:02:01.31#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.252.08:02:01.31#ibcon#ireg 11 cls_cnt 2 2006.252.08:02:01.31#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.252.08:02:01.37#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.252.08:02:01.37#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.252.08:02:01.37#ibcon#enter wrdev, iclass 10, count 2 2006.252.08:02:01.37#ibcon#first serial, iclass 10, count 2 2006.252.08:02:01.37#ibcon#enter sib2, iclass 10, count 2 2006.252.08:02:01.37#ibcon#flushed, iclass 10, count 2 2006.252.08:02:01.37#ibcon#about to write, iclass 10, count 2 2006.252.08:02:01.37#ibcon#wrote, iclass 10, count 2 2006.252.08:02:01.37#ibcon#about to read 3, iclass 10, count 2 2006.252.08:02:01.39#ibcon#read 3, iclass 10, count 2 2006.252.08:02:01.39#ibcon#about to read 4, iclass 10, count 2 2006.252.08:02:01.39#ibcon#read 4, iclass 10, count 2 2006.252.08:02:01.39#ibcon#about to read 5, iclass 10, count 2 2006.252.08:02:01.39#ibcon#read 5, iclass 10, count 2 2006.252.08:02:01.39#ibcon#about to read 6, iclass 10, count 2 2006.252.08:02:01.39#ibcon#read 6, iclass 10, count 2 2006.252.08:02:01.39#ibcon#end of sib2, iclass 10, count 2 2006.252.08:02:01.39#ibcon#*mode == 0, iclass 10, count 2 2006.252.08:02:01.39#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.252.08:02:01.39#ibcon#[27=AT03-04\r\n] 2006.252.08:02:01.39#ibcon#*before write, iclass 10, count 2 2006.252.08:02:01.39#ibcon#enter sib2, iclass 10, count 2 2006.252.08:02:01.39#ibcon#flushed, iclass 10, count 2 2006.252.08:02:01.39#ibcon#about to write, iclass 10, count 2 2006.252.08:02:01.39#ibcon#wrote, iclass 10, count 2 2006.252.08:02:01.39#ibcon#about to read 3, iclass 10, count 2 2006.252.08:02:01.42#ibcon#read 3, iclass 10, count 2 2006.252.08:02:01.42#ibcon#about to read 4, iclass 10, count 2 2006.252.08:02:01.42#ibcon#read 4, iclass 10, count 2 2006.252.08:02:01.42#ibcon#about to read 5, iclass 10, count 2 2006.252.08:02:01.42#ibcon#read 5, iclass 10, count 2 2006.252.08:02:01.42#ibcon#about to read 6, iclass 10, count 2 2006.252.08:02:01.42#ibcon#read 6, iclass 10, count 2 2006.252.08:02:01.42#ibcon#end of sib2, iclass 10, count 2 2006.252.08:02:01.42#ibcon#*after write, iclass 10, count 2 2006.252.08:02:01.42#ibcon#*before return 0, iclass 10, count 2 2006.252.08:02:01.42#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.252.08:02:01.42#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.252.08:02:01.42#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.252.08:02:01.42#ibcon#ireg 7 cls_cnt 0 2006.252.08:02:01.42#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.252.08:02:01.54#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.252.08:02:01.54#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.252.08:02:01.54#ibcon#enter wrdev, iclass 10, count 0 2006.252.08:02:01.54#ibcon#first serial, iclass 10, count 0 2006.252.08:02:01.54#ibcon#enter sib2, iclass 10, count 0 2006.252.08:02:01.54#ibcon#flushed, iclass 10, count 0 2006.252.08:02:01.54#ibcon#about to write, iclass 10, count 0 2006.252.08:02:01.54#ibcon#wrote, iclass 10, count 0 2006.252.08:02:01.54#ibcon#about to read 3, iclass 10, count 0 2006.252.08:02:01.56#ibcon#read 3, iclass 10, count 0 2006.252.08:02:01.56#ibcon#about to read 4, iclass 10, count 0 2006.252.08:02:01.56#ibcon#read 4, iclass 10, count 0 2006.252.08:02:01.56#ibcon#about to read 5, iclass 10, count 0 2006.252.08:02:01.56#ibcon#read 5, iclass 10, count 0 2006.252.08:02:01.56#ibcon#about to read 6, iclass 10, count 0 2006.252.08:02:01.56#ibcon#read 6, iclass 10, count 0 2006.252.08:02:01.56#ibcon#end of sib2, iclass 10, count 0 2006.252.08:02:01.56#ibcon#*mode == 0, iclass 10, count 0 2006.252.08:02:01.56#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.252.08:02:01.56#ibcon#[27=USB\r\n] 2006.252.08:02:01.56#ibcon#*before write, iclass 10, count 0 2006.252.08:02:01.56#ibcon#enter sib2, iclass 10, count 0 2006.252.08:02:01.56#ibcon#flushed, iclass 10, count 0 2006.252.08:02:01.56#ibcon#about to write, iclass 10, count 0 2006.252.08:02:01.56#ibcon#wrote, iclass 10, count 0 2006.252.08:02:01.56#ibcon#about to read 3, iclass 10, count 0 2006.252.08:02:01.59#ibcon#read 3, iclass 10, count 0 2006.252.08:02:01.59#ibcon#about to read 4, iclass 10, count 0 2006.252.08:02:01.59#ibcon#read 4, iclass 10, count 0 2006.252.08:02:01.59#ibcon#about to read 5, iclass 10, count 0 2006.252.08:02:01.59#ibcon#read 5, iclass 10, count 0 2006.252.08:02:01.59#ibcon#about to read 6, iclass 10, count 0 2006.252.08:02:01.59#ibcon#read 6, iclass 10, count 0 2006.252.08:02:01.59#ibcon#end of sib2, iclass 10, count 0 2006.252.08:02:01.59#ibcon#*after write, iclass 10, count 0 2006.252.08:02:01.59#ibcon#*before return 0, iclass 10, count 0 2006.252.08:02:01.59#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.252.08:02:01.59#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.252.08:02:01.59#ibcon#about to clear, iclass 10 cls_cnt 0 2006.252.08:02:01.59#ibcon#cleared, iclass 10 cls_cnt 0 2006.252.08:02:01.59$vc4f8/vblo=4,712.99 2006.252.08:02:01.59#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.252.08:02:01.59#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.252.08:02:01.59#ibcon#ireg 17 cls_cnt 0 2006.252.08:02:01.59#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.252.08:02:01.59#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.252.08:02:01.59#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.252.08:02:01.59#ibcon#enter wrdev, iclass 12, count 0 2006.252.08:02:01.59#ibcon#first serial, iclass 12, count 0 2006.252.08:02:01.59#ibcon#enter sib2, iclass 12, count 0 2006.252.08:02:01.59#ibcon#flushed, iclass 12, count 0 2006.252.08:02:01.59#ibcon#about to write, iclass 12, count 0 2006.252.08:02:01.59#ibcon#wrote, iclass 12, count 0 2006.252.08:02:01.59#ibcon#about to read 3, iclass 12, count 0 2006.252.08:02:01.61#ibcon#read 3, iclass 12, count 0 2006.252.08:02:01.61#ibcon#about to read 4, iclass 12, count 0 2006.252.08:02:01.61#ibcon#read 4, iclass 12, count 0 2006.252.08:02:01.61#ibcon#about to read 5, iclass 12, count 0 2006.252.08:02:01.61#ibcon#read 5, iclass 12, count 0 2006.252.08:02:01.61#ibcon#about to read 6, iclass 12, count 0 2006.252.08:02:01.61#ibcon#read 6, iclass 12, count 0 2006.252.08:02:01.61#ibcon#end of sib2, iclass 12, count 0 2006.252.08:02:01.61#ibcon#*mode == 0, iclass 12, count 0 2006.252.08:02:01.61#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.252.08:02:01.61#ibcon#[28=FRQ=04,712.99\r\n] 2006.252.08:02:01.61#ibcon#*before write, iclass 12, count 0 2006.252.08:02:01.61#ibcon#enter sib2, iclass 12, count 0 2006.252.08:02:01.61#ibcon#flushed, iclass 12, count 0 2006.252.08:02:01.61#ibcon#about to write, iclass 12, count 0 2006.252.08:02:01.61#ibcon#wrote, iclass 12, count 0 2006.252.08:02:01.61#ibcon#about to read 3, iclass 12, count 0 2006.252.08:02:01.65#ibcon#read 3, iclass 12, count 0 2006.252.08:02:01.65#ibcon#about to read 4, iclass 12, count 0 2006.252.08:02:01.65#ibcon#read 4, iclass 12, count 0 2006.252.08:02:01.65#ibcon#about to read 5, iclass 12, count 0 2006.252.08:02:01.65#ibcon#read 5, iclass 12, count 0 2006.252.08:02:01.65#ibcon#about to read 6, iclass 12, count 0 2006.252.08:02:01.65#ibcon#read 6, iclass 12, count 0 2006.252.08:02:01.65#ibcon#end of sib2, iclass 12, count 0 2006.252.08:02:01.65#ibcon#*after write, iclass 12, count 0 2006.252.08:02:01.65#ibcon#*before return 0, iclass 12, count 0 2006.252.08:02:01.65#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.252.08:02:01.65#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.252.08:02:01.65#ibcon#about to clear, iclass 12 cls_cnt 0 2006.252.08:02:01.65#ibcon#cleared, iclass 12 cls_cnt 0 2006.252.08:02:01.65$vc4f8/vb=4,4 2006.252.08:02:01.65#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.252.08:02:01.65#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.252.08:02:01.65#ibcon#ireg 11 cls_cnt 2 2006.252.08:02:01.65#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.252.08:02:01.71#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.252.08:02:01.71#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.252.08:02:01.71#ibcon#enter wrdev, iclass 14, count 2 2006.252.08:02:01.71#ibcon#first serial, iclass 14, count 2 2006.252.08:02:01.71#ibcon#enter sib2, iclass 14, count 2 2006.252.08:02:01.71#ibcon#flushed, iclass 14, count 2 2006.252.08:02:01.71#ibcon#about to write, iclass 14, count 2 2006.252.08:02:01.71#ibcon#wrote, iclass 14, count 2 2006.252.08:02:01.71#ibcon#about to read 3, iclass 14, count 2 2006.252.08:02:01.73#ibcon#read 3, iclass 14, count 2 2006.252.08:02:01.73#ibcon#about to read 4, iclass 14, count 2 2006.252.08:02:01.73#ibcon#read 4, iclass 14, count 2 2006.252.08:02:01.73#ibcon#about to read 5, iclass 14, count 2 2006.252.08:02:01.73#ibcon#read 5, iclass 14, count 2 2006.252.08:02:01.73#ibcon#about to read 6, iclass 14, count 2 2006.252.08:02:01.73#ibcon#read 6, iclass 14, count 2 2006.252.08:02:01.73#ibcon#end of sib2, iclass 14, count 2 2006.252.08:02:01.73#ibcon#*mode == 0, iclass 14, count 2 2006.252.08:02:01.73#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.252.08:02:01.73#ibcon#[27=AT04-04\r\n] 2006.252.08:02:01.73#ibcon#*before write, iclass 14, count 2 2006.252.08:02:01.73#ibcon#enter sib2, iclass 14, count 2 2006.252.08:02:01.73#ibcon#flushed, iclass 14, count 2 2006.252.08:02:01.73#ibcon#about to write, iclass 14, count 2 2006.252.08:02:01.73#ibcon#wrote, iclass 14, count 2 2006.252.08:02:01.73#ibcon#about to read 3, iclass 14, count 2 2006.252.08:02:01.76#ibcon#read 3, iclass 14, count 2 2006.252.08:02:01.76#ibcon#about to read 4, iclass 14, count 2 2006.252.08:02:01.76#ibcon#read 4, iclass 14, count 2 2006.252.08:02:01.76#ibcon#about to read 5, iclass 14, count 2 2006.252.08:02:01.76#ibcon#read 5, iclass 14, count 2 2006.252.08:02:01.76#ibcon#about to read 6, iclass 14, count 2 2006.252.08:02:01.76#ibcon#read 6, iclass 14, count 2 2006.252.08:02:01.76#ibcon#end of sib2, iclass 14, count 2 2006.252.08:02:01.76#ibcon#*after write, iclass 14, count 2 2006.252.08:02:01.76#ibcon#*before return 0, iclass 14, count 2 2006.252.08:02:01.76#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.252.08:02:01.76#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.252.08:02:01.76#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.252.08:02:01.76#ibcon#ireg 7 cls_cnt 0 2006.252.08:02:01.76#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.252.08:02:01.88#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.252.08:02:01.88#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.252.08:02:01.88#ibcon#enter wrdev, iclass 14, count 0 2006.252.08:02:01.88#ibcon#first serial, iclass 14, count 0 2006.252.08:02:01.88#ibcon#enter sib2, iclass 14, count 0 2006.252.08:02:01.88#ibcon#flushed, iclass 14, count 0 2006.252.08:02:01.88#ibcon#about to write, iclass 14, count 0 2006.252.08:02:01.88#ibcon#wrote, iclass 14, count 0 2006.252.08:02:01.88#ibcon#about to read 3, iclass 14, count 0 2006.252.08:02:01.90#ibcon#read 3, iclass 14, count 0 2006.252.08:02:01.90#ibcon#about to read 4, iclass 14, count 0 2006.252.08:02:01.90#ibcon#read 4, iclass 14, count 0 2006.252.08:02:01.90#ibcon#about to read 5, iclass 14, count 0 2006.252.08:02:01.90#ibcon#read 5, iclass 14, count 0 2006.252.08:02:01.90#ibcon#about to read 6, iclass 14, count 0 2006.252.08:02:01.90#ibcon#read 6, iclass 14, count 0 2006.252.08:02:01.90#ibcon#end of sib2, iclass 14, count 0 2006.252.08:02:01.90#ibcon#*mode == 0, iclass 14, count 0 2006.252.08:02:01.90#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.252.08:02:01.90#ibcon#[27=USB\r\n] 2006.252.08:02:01.90#ibcon#*before write, iclass 14, count 0 2006.252.08:02:01.90#ibcon#enter sib2, iclass 14, count 0 2006.252.08:02:01.90#ibcon#flushed, iclass 14, count 0 2006.252.08:02:01.90#ibcon#about to write, iclass 14, count 0 2006.252.08:02:01.90#ibcon#wrote, iclass 14, count 0 2006.252.08:02:01.90#ibcon#about to read 3, iclass 14, count 0 2006.252.08:02:01.93#ibcon#read 3, iclass 14, count 0 2006.252.08:02:01.93#ibcon#about to read 4, iclass 14, count 0 2006.252.08:02:01.93#ibcon#read 4, iclass 14, count 0 2006.252.08:02:01.93#ibcon#about to read 5, iclass 14, count 0 2006.252.08:02:01.93#ibcon#read 5, iclass 14, count 0 2006.252.08:02:01.93#ibcon#about to read 6, iclass 14, count 0 2006.252.08:02:01.93#ibcon#read 6, iclass 14, count 0 2006.252.08:02:01.93#ibcon#end of sib2, iclass 14, count 0 2006.252.08:02:01.93#ibcon#*after write, iclass 14, count 0 2006.252.08:02:01.93#ibcon#*before return 0, iclass 14, count 0 2006.252.08:02:01.93#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.252.08:02:01.93#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.252.08:02:01.93#ibcon#about to clear, iclass 14 cls_cnt 0 2006.252.08:02:01.93#ibcon#cleared, iclass 14 cls_cnt 0 2006.252.08:02:01.93$vc4f8/vblo=5,744.99 2006.252.08:02:01.93#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.252.08:02:01.93#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.252.08:02:01.93#ibcon#ireg 17 cls_cnt 0 2006.252.08:02:01.93#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.252.08:02:01.93#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.252.08:02:01.93#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.252.08:02:01.93#ibcon#enter wrdev, iclass 16, count 0 2006.252.08:02:01.93#ibcon#first serial, iclass 16, count 0 2006.252.08:02:01.93#ibcon#enter sib2, iclass 16, count 0 2006.252.08:02:01.93#ibcon#flushed, iclass 16, count 0 2006.252.08:02:01.93#ibcon#about to write, iclass 16, count 0 2006.252.08:02:01.93#ibcon#wrote, iclass 16, count 0 2006.252.08:02:01.93#ibcon#about to read 3, iclass 16, count 0 2006.252.08:02:01.95#ibcon#read 3, iclass 16, count 0 2006.252.08:02:01.95#ibcon#about to read 4, iclass 16, count 0 2006.252.08:02:01.95#ibcon#read 4, iclass 16, count 0 2006.252.08:02:01.95#ibcon#about to read 5, iclass 16, count 0 2006.252.08:02:01.95#ibcon#read 5, iclass 16, count 0 2006.252.08:02:01.95#ibcon#about to read 6, iclass 16, count 0 2006.252.08:02:01.95#ibcon#read 6, iclass 16, count 0 2006.252.08:02:01.95#ibcon#end of sib2, iclass 16, count 0 2006.252.08:02:01.95#ibcon#*mode == 0, iclass 16, count 0 2006.252.08:02:01.95#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.252.08:02:01.95#ibcon#[28=FRQ=05,744.99\r\n] 2006.252.08:02:01.95#ibcon#*before write, iclass 16, count 0 2006.252.08:02:01.95#ibcon#enter sib2, iclass 16, count 0 2006.252.08:02:01.95#ibcon#flushed, iclass 16, count 0 2006.252.08:02:01.95#ibcon#about to write, iclass 16, count 0 2006.252.08:02:01.95#ibcon#wrote, iclass 16, count 0 2006.252.08:02:01.95#ibcon#about to read 3, iclass 16, count 0 2006.252.08:02:01.99#ibcon#read 3, iclass 16, count 0 2006.252.08:02:01.99#ibcon#about to read 4, iclass 16, count 0 2006.252.08:02:01.99#ibcon#read 4, iclass 16, count 0 2006.252.08:02:01.99#ibcon#about to read 5, iclass 16, count 0 2006.252.08:02:01.99#ibcon#read 5, iclass 16, count 0 2006.252.08:02:01.99#ibcon#about to read 6, iclass 16, count 0 2006.252.08:02:01.99#ibcon#read 6, iclass 16, count 0 2006.252.08:02:01.99#ibcon#end of sib2, iclass 16, count 0 2006.252.08:02:01.99#ibcon#*after write, iclass 16, count 0 2006.252.08:02:01.99#ibcon#*before return 0, iclass 16, count 0 2006.252.08:02:01.99#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.252.08:02:01.99#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.252.08:02:01.99#ibcon#about to clear, iclass 16 cls_cnt 0 2006.252.08:02:01.99#ibcon#cleared, iclass 16 cls_cnt 0 2006.252.08:02:01.99$vc4f8/vb=5,4 2006.252.08:02:01.99#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.252.08:02:01.99#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.252.08:02:01.99#ibcon#ireg 11 cls_cnt 2 2006.252.08:02:01.99#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.252.08:02:02.05#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.252.08:02:02.05#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.252.08:02:02.05#ibcon#enter wrdev, iclass 18, count 2 2006.252.08:02:02.05#ibcon#first serial, iclass 18, count 2 2006.252.08:02:02.05#ibcon#enter sib2, iclass 18, count 2 2006.252.08:02:02.05#ibcon#flushed, iclass 18, count 2 2006.252.08:02:02.05#ibcon#about to write, iclass 18, count 2 2006.252.08:02:02.05#ibcon#wrote, iclass 18, count 2 2006.252.08:02:02.05#ibcon#about to read 3, iclass 18, count 2 2006.252.08:02:02.07#ibcon#read 3, iclass 18, count 2 2006.252.08:02:02.07#ibcon#about to read 4, iclass 18, count 2 2006.252.08:02:02.07#ibcon#read 4, iclass 18, count 2 2006.252.08:02:02.07#ibcon#about to read 5, iclass 18, count 2 2006.252.08:02:02.07#ibcon#read 5, iclass 18, count 2 2006.252.08:02:02.07#ibcon#about to read 6, iclass 18, count 2 2006.252.08:02:02.07#ibcon#read 6, iclass 18, count 2 2006.252.08:02:02.07#ibcon#end of sib2, iclass 18, count 2 2006.252.08:02:02.07#ibcon#*mode == 0, iclass 18, count 2 2006.252.08:02:02.07#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.252.08:02:02.07#ibcon#[27=AT05-04\r\n] 2006.252.08:02:02.07#ibcon#*before write, iclass 18, count 2 2006.252.08:02:02.07#ibcon#enter sib2, iclass 18, count 2 2006.252.08:02:02.07#ibcon#flushed, iclass 18, count 2 2006.252.08:02:02.07#ibcon#about to write, iclass 18, count 2 2006.252.08:02:02.07#ibcon#wrote, iclass 18, count 2 2006.252.08:02:02.07#ibcon#about to read 3, iclass 18, count 2 2006.252.08:02:02.10#ibcon#read 3, iclass 18, count 2 2006.252.08:02:02.10#ibcon#about to read 4, iclass 18, count 2 2006.252.08:02:02.10#ibcon#read 4, iclass 18, count 2 2006.252.08:02:02.10#ibcon#about to read 5, iclass 18, count 2 2006.252.08:02:02.10#ibcon#read 5, iclass 18, count 2 2006.252.08:02:02.10#ibcon#about to read 6, iclass 18, count 2 2006.252.08:02:02.10#ibcon#read 6, iclass 18, count 2 2006.252.08:02:02.10#ibcon#end of sib2, iclass 18, count 2 2006.252.08:02:02.10#ibcon#*after write, iclass 18, count 2 2006.252.08:02:02.10#ibcon#*before return 0, iclass 18, count 2 2006.252.08:02:02.10#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.252.08:02:02.10#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.252.08:02:02.10#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.252.08:02:02.10#ibcon#ireg 7 cls_cnt 0 2006.252.08:02:02.10#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.252.08:02:02.22#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.252.08:02:02.22#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.252.08:02:02.22#ibcon#enter wrdev, iclass 18, count 0 2006.252.08:02:02.22#ibcon#first serial, iclass 18, count 0 2006.252.08:02:02.22#ibcon#enter sib2, iclass 18, count 0 2006.252.08:02:02.22#ibcon#flushed, iclass 18, count 0 2006.252.08:02:02.22#ibcon#about to write, iclass 18, count 0 2006.252.08:02:02.22#ibcon#wrote, iclass 18, count 0 2006.252.08:02:02.22#ibcon#about to read 3, iclass 18, count 0 2006.252.08:02:02.24#ibcon#read 3, iclass 18, count 0 2006.252.08:02:02.24#ibcon#about to read 4, iclass 18, count 0 2006.252.08:02:02.24#ibcon#read 4, iclass 18, count 0 2006.252.08:02:02.24#ibcon#about to read 5, iclass 18, count 0 2006.252.08:02:02.24#ibcon#read 5, iclass 18, count 0 2006.252.08:02:02.24#ibcon#about to read 6, iclass 18, count 0 2006.252.08:02:02.24#ibcon#read 6, iclass 18, count 0 2006.252.08:02:02.24#ibcon#end of sib2, iclass 18, count 0 2006.252.08:02:02.24#ibcon#*mode == 0, iclass 18, count 0 2006.252.08:02:02.24#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.252.08:02:02.24#ibcon#[27=USB\r\n] 2006.252.08:02:02.24#ibcon#*before write, iclass 18, count 0 2006.252.08:02:02.24#ibcon#enter sib2, iclass 18, count 0 2006.252.08:02:02.24#ibcon#flushed, iclass 18, count 0 2006.252.08:02:02.24#ibcon#about to write, iclass 18, count 0 2006.252.08:02:02.24#ibcon#wrote, iclass 18, count 0 2006.252.08:02:02.24#ibcon#about to read 3, iclass 18, count 0 2006.252.08:02:02.27#ibcon#read 3, iclass 18, count 0 2006.252.08:02:02.27#ibcon#about to read 4, iclass 18, count 0 2006.252.08:02:02.27#ibcon#read 4, iclass 18, count 0 2006.252.08:02:02.27#ibcon#about to read 5, iclass 18, count 0 2006.252.08:02:02.27#ibcon#read 5, iclass 18, count 0 2006.252.08:02:02.27#ibcon#about to read 6, iclass 18, count 0 2006.252.08:02:02.27#ibcon#read 6, iclass 18, count 0 2006.252.08:02:02.27#ibcon#end of sib2, iclass 18, count 0 2006.252.08:02:02.27#ibcon#*after write, iclass 18, count 0 2006.252.08:02:02.27#ibcon#*before return 0, iclass 18, count 0 2006.252.08:02:02.27#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.252.08:02:02.27#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.252.08:02:02.27#ibcon#about to clear, iclass 18 cls_cnt 0 2006.252.08:02:02.27#ibcon#cleared, iclass 18 cls_cnt 0 2006.252.08:02:02.27$vc4f8/vblo=6,752.99 2006.252.08:02:02.27#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.252.08:02:02.27#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.252.08:02:02.27#ibcon#ireg 17 cls_cnt 0 2006.252.08:02:02.27#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.252.08:02:02.27#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.252.08:02:02.27#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.252.08:02:02.27#ibcon#enter wrdev, iclass 20, count 0 2006.252.08:02:02.27#ibcon#first serial, iclass 20, count 0 2006.252.08:02:02.27#ibcon#enter sib2, iclass 20, count 0 2006.252.08:02:02.27#ibcon#flushed, iclass 20, count 0 2006.252.08:02:02.27#ibcon#about to write, iclass 20, count 0 2006.252.08:02:02.27#ibcon#wrote, iclass 20, count 0 2006.252.08:02:02.27#ibcon#about to read 3, iclass 20, count 0 2006.252.08:02:02.29#ibcon#read 3, iclass 20, count 0 2006.252.08:02:02.29#ibcon#about to read 4, iclass 20, count 0 2006.252.08:02:02.29#ibcon#read 4, iclass 20, count 0 2006.252.08:02:02.29#ibcon#about to read 5, iclass 20, count 0 2006.252.08:02:02.29#ibcon#read 5, iclass 20, count 0 2006.252.08:02:02.29#ibcon#about to read 6, iclass 20, count 0 2006.252.08:02:02.29#ibcon#read 6, iclass 20, count 0 2006.252.08:02:02.29#ibcon#end of sib2, iclass 20, count 0 2006.252.08:02:02.29#ibcon#*mode == 0, iclass 20, count 0 2006.252.08:02:02.29#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.252.08:02:02.29#ibcon#[28=FRQ=06,752.99\r\n] 2006.252.08:02:02.29#ibcon#*before write, iclass 20, count 0 2006.252.08:02:02.29#ibcon#enter sib2, iclass 20, count 0 2006.252.08:02:02.29#ibcon#flushed, iclass 20, count 0 2006.252.08:02:02.29#ibcon#about to write, iclass 20, count 0 2006.252.08:02:02.29#ibcon#wrote, iclass 20, count 0 2006.252.08:02:02.29#ibcon#about to read 3, iclass 20, count 0 2006.252.08:02:02.33#ibcon#read 3, iclass 20, count 0 2006.252.08:02:02.33#ibcon#about to read 4, iclass 20, count 0 2006.252.08:02:02.33#ibcon#read 4, iclass 20, count 0 2006.252.08:02:02.33#ibcon#about to read 5, iclass 20, count 0 2006.252.08:02:02.33#ibcon#read 5, iclass 20, count 0 2006.252.08:02:02.33#ibcon#about to read 6, iclass 20, count 0 2006.252.08:02:02.33#ibcon#read 6, iclass 20, count 0 2006.252.08:02:02.33#ibcon#end of sib2, iclass 20, count 0 2006.252.08:02:02.33#ibcon#*after write, iclass 20, count 0 2006.252.08:02:02.33#ibcon#*before return 0, iclass 20, count 0 2006.252.08:02:02.33#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.252.08:02:02.33#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.252.08:02:02.33#ibcon#about to clear, iclass 20 cls_cnt 0 2006.252.08:02:02.33#ibcon#cleared, iclass 20 cls_cnt 0 2006.252.08:02:02.33$vc4f8/vb=6,4 2006.252.08:02:02.33#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.252.08:02:02.33#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.252.08:02:02.33#ibcon#ireg 11 cls_cnt 2 2006.252.08:02:02.33#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.252.08:02:02.39#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.252.08:02:02.39#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.252.08:02:02.39#ibcon#enter wrdev, iclass 22, count 2 2006.252.08:02:02.39#ibcon#first serial, iclass 22, count 2 2006.252.08:02:02.39#ibcon#enter sib2, iclass 22, count 2 2006.252.08:02:02.39#ibcon#flushed, iclass 22, count 2 2006.252.08:02:02.39#ibcon#about to write, iclass 22, count 2 2006.252.08:02:02.39#ibcon#wrote, iclass 22, count 2 2006.252.08:02:02.39#ibcon#about to read 3, iclass 22, count 2 2006.252.08:02:02.41#ibcon#read 3, iclass 22, count 2 2006.252.08:02:02.41#ibcon#about to read 4, iclass 22, count 2 2006.252.08:02:02.41#ibcon#read 4, iclass 22, count 2 2006.252.08:02:02.41#ibcon#about to read 5, iclass 22, count 2 2006.252.08:02:02.41#ibcon#read 5, iclass 22, count 2 2006.252.08:02:02.41#ibcon#about to read 6, iclass 22, count 2 2006.252.08:02:02.41#ibcon#read 6, iclass 22, count 2 2006.252.08:02:02.41#ibcon#end of sib2, iclass 22, count 2 2006.252.08:02:02.41#ibcon#*mode == 0, iclass 22, count 2 2006.252.08:02:02.41#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.252.08:02:02.41#ibcon#[27=AT06-04\r\n] 2006.252.08:02:02.41#ibcon#*before write, iclass 22, count 2 2006.252.08:02:02.41#ibcon#enter sib2, iclass 22, count 2 2006.252.08:02:02.41#ibcon#flushed, iclass 22, count 2 2006.252.08:02:02.41#ibcon#about to write, iclass 22, count 2 2006.252.08:02:02.41#ibcon#wrote, iclass 22, count 2 2006.252.08:02:02.41#ibcon#about to read 3, iclass 22, count 2 2006.252.08:02:02.44#ibcon#read 3, iclass 22, count 2 2006.252.08:02:02.44#ibcon#about to read 4, iclass 22, count 2 2006.252.08:02:02.44#ibcon#read 4, iclass 22, count 2 2006.252.08:02:02.44#ibcon#about to read 5, iclass 22, count 2 2006.252.08:02:02.44#ibcon#read 5, iclass 22, count 2 2006.252.08:02:02.44#ibcon#about to read 6, iclass 22, count 2 2006.252.08:02:02.44#ibcon#read 6, iclass 22, count 2 2006.252.08:02:02.44#ibcon#end of sib2, iclass 22, count 2 2006.252.08:02:02.44#ibcon#*after write, iclass 22, count 2 2006.252.08:02:02.44#ibcon#*before return 0, iclass 22, count 2 2006.252.08:02:02.44#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.252.08:02:02.44#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.252.08:02:02.44#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.252.08:02:02.44#ibcon#ireg 7 cls_cnt 0 2006.252.08:02:02.44#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.252.08:02:02.56#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.252.08:02:02.56#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.252.08:02:02.56#ibcon#enter wrdev, iclass 22, count 0 2006.252.08:02:02.56#ibcon#first serial, iclass 22, count 0 2006.252.08:02:02.56#ibcon#enter sib2, iclass 22, count 0 2006.252.08:02:02.56#ibcon#flushed, iclass 22, count 0 2006.252.08:02:02.56#ibcon#about to write, iclass 22, count 0 2006.252.08:02:02.56#ibcon#wrote, iclass 22, count 0 2006.252.08:02:02.56#ibcon#about to read 3, iclass 22, count 0 2006.252.08:02:02.58#ibcon#read 3, iclass 22, count 0 2006.252.08:02:02.58#ibcon#about to read 4, iclass 22, count 0 2006.252.08:02:02.58#ibcon#read 4, iclass 22, count 0 2006.252.08:02:02.58#ibcon#about to read 5, iclass 22, count 0 2006.252.08:02:02.58#ibcon#read 5, iclass 22, count 0 2006.252.08:02:02.58#ibcon#about to read 6, iclass 22, count 0 2006.252.08:02:02.58#ibcon#read 6, iclass 22, count 0 2006.252.08:02:02.58#ibcon#end of sib2, iclass 22, count 0 2006.252.08:02:02.58#ibcon#*mode == 0, iclass 22, count 0 2006.252.08:02:02.58#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.252.08:02:02.58#ibcon#[27=USB\r\n] 2006.252.08:02:02.58#ibcon#*before write, iclass 22, count 0 2006.252.08:02:02.58#ibcon#enter sib2, iclass 22, count 0 2006.252.08:02:02.58#ibcon#flushed, iclass 22, count 0 2006.252.08:02:02.58#ibcon#about to write, iclass 22, count 0 2006.252.08:02:02.58#ibcon#wrote, iclass 22, count 0 2006.252.08:02:02.58#ibcon#about to read 3, iclass 22, count 0 2006.252.08:02:02.61#ibcon#read 3, iclass 22, count 0 2006.252.08:02:02.61#ibcon#about to read 4, iclass 22, count 0 2006.252.08:02:02.61#ibcon#read 4, iclass 22, count 0 2006.252.08:02:02.61#ibcon#about to read 5, iclass 22, count 0 2006.252.08:02:02.61#ibcon#read 5, iclass 22, count 0 2006.252.08:02:02.61#ibcon#about to read 6, iclass 22, count 0 2006.252.08:02:02.61#ibcon#read 6, iclass 22, count 0 2006.252.08:02:02.61#ibcon#end of sib2, iclass 22, count 0 2006.252.08:02:02.61#ibcon#*after write, iclass 22, count 0 2006.252.08:02:02.61#ibcon#*before return 0, iclass 22, count 0 2006.252.08:02:02.61#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.252.08:02:02.61#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.252.08:02:02.61#ibcon#about to clear, iclass 22 cls_cnt 0 2006.252.08:02:02.61#ibcon#cleared, iclass 22 cls_cnt 0 2006.252.08:02:02.61$vc4f8/vabw=wide 2006.252.08:02:02.61#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.252.08:02:02.61#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.252.08:02:02.61#ibcon#ireg 8 cls_cnt 0 2006.252.08:02:02.61#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.252.08:02:02.61#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.252.08:02:02.61#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.252.08:02:02.61#ibcon#enter wrdev, iclass 24, count 0 2006.252.08:02:02.61#ibcon#first serial, iclass 24, count 0 2006.252.08:02:02.61#ibcon#enter sib2, iclass 24, count 0 2006.252.08:02:02.61#ibcon#flushed, iclass 24, count 0 2006.252.08:02:02.61#ibcon#about to write, iclass 24, count 0 2006.252.08:02:02.61#ibcon#wrote, iclass 24, count 0 2006.252.08:02:02.61#ibcon#about to read 3, iclass 24, count 0 2006.252.08:02:02.63#ibcon#read 3, iclass 24, count 0 2006.252.08:02:02.63#ibcon#about to read 4, iclass 24, count 0 2006.252.08:02:02.63#ibcon#read 4, iclass 24, count 0 2006.252.08:02:02.63#ibcon#about to read 5, iclass 24, count 0 2006.252.08:02:02.63#ibcon#read 5, iclass 24, count 0 2006.252.08:02:02.63#ibcon#about to read 6, iclass 24, count 0 2006.252.08:02:02.63#ibcon#read 6, iclass 24, count 0 2006.252.08:02:02.63#ibcon#end of sib2, iclass 24, count 0 2006.252.08:02:02.63#ibcon#*mode == 0, iclass 24, count 0 2006.252.08:02:02.63#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.252.08:02:02.63#ibcon#[25=BW32\r\n] 2006.252.08:02:02.63#ibcon#*before write, iclass 24, count 0 2006.252.08:02:02.63#ibcon#enter sib2, iclass 24, count 0 2006.252.08:02:02.63#ibcon#flushed, iclass 24, count 0 2006.252.08:02:02.63#ibcon#about to write, iclass 24, count 0 2006.252.08:02:02.63#ibcon#wrote, iclass 24, count 0 2006.252.08:02:02.63#ibcon#about to read 3, iclass 24, count 0 2006.252.08:02:02.66#ibcon#read 3, iclass 24, count 0 2006.252.08:02:02.66#ibcon#about to read 4, iclass 24, count 0 2006.252.08:02:02.66#ibcon#read 4, iclass 24, count 0 2006.252.08:02:02.66#ibcon#about to read 5, iclass 24, count 0 2006.252.08:02:02.66#ibcon#read 5, iclass 24, count 0 2006.252.08:02:02.66#ibcon#about to read 6, iclass 24, count 0 2006.252.08:02:02.66#ibcon#read 6, iclass 24, count 0 2006.252.08:02:02.66#ibcon#end of sib2, iclass 24, count 0 2006.252.08:02:02.66#ibcon#*after write, iclass 24, count 0 2006.252.08:02:02.66#ibcon#*before return 0, iclass 24, count 0 2006.252.08:02:02.66#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.252.08:02:02.66#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.252.08:02:02.66#ibcon#about to clear, iclass 24 cls_cnt 0 2006.252.08:02:02.66#ibcon#cleared, iclass 24 cls_cnt 0 2006.252.08:02:02.66$vc4f8/vbbw=wide 2006.252.08:02:02.66#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.252.08:02:02.66#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.252.08:02:02.66#ibcon#ireg 8 cls_cnt 0 2006.252.08:02:02.66#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.252.08:02:02.73#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.252.08:02:02.73#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.252.08:02:02.73#ibcon#enter wrdev, iclass 26, count 0 2006.252.08:02:02.73#ibcon#first serial, iclass 26, count 0 2006.252.08:02:02.73#ibcon#enter sib2, iclass 26, count 0 2006.252.08:02:02.73#ibcon#flushed, iclass 26, count 0 2006.252.08:02:02.73#ibcon#about to write, iclass 26, count 0 2006.252.08:02:02.73#ibcon#wrote, iclass 26, count 0 2006.252.08:02:02.73#ibcon#about to read 3, iclass 26, count 0 2006.252.08:02:02.75#ibcon#read 3, iclass 26, count 0 2006.252.08:02:02.75#ibcon#about to read 4, iclass 26, count 0 2006.252.08:02:02.75#ibcon#read 4, iclass 26, count 0 2006.252.08:02:02.75#ibcon#about to read 5, iclass 26, count 0 2006.252.08:02:02.75#ibcon#read 5, iclass 26, count 0 2006.252.08:02:02.75#ibcon#about to read 6, iclass 26, count 0 2006.252.08:02:02.75#ibcon#read 6, iclass 26, count 0 2006.252.08:02:02.75#ibcon#end of sib2, iclass 26, count 0 2006.252.08:02:02.75#ibcon#*mode == 0, iclass 26, count 0 2006.252.08:02:02.75#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.252.08:02:02.75#ibcon#[27=BW32\r\n] 2006.252.08:02:02.75#ibcon#*before write, iclass 26, count 0 2006.252.08:02:02.75#ibcon#enter sib2, iclass 26, count 0 2006.252.08:02:02.75#ibcon#flushed, iclass 26, count 0 2006.252.08:02:02.75#ibcon#about to write, iclass 26, count 0 2006.252.08:02:02.75#ibcon#wrote, iclass 26, count 0 2006.252.08:02:02.75#ibcon#about to read 3, iclass 26, count 0 2006.252.08:02:02.78#ibcon#read 3, iclass 26, count 0 2006.252.08:02:02.78#ibcon#about to read 4, iclass 26, count 0 2006.252.08:02:02.78#ibcon#read 4, iclass 26, count 0 2006.252.08:02:02.78#ibcon#about to read 5, iclass 26, count 0 2006.252.08:02:02.78#ibcon#read 5, iclass 26, count 0 2006.252.08:02:02.78#ibcon#about to read 6, iclass 26, count 0 2006.252.08:02:02.78#ibcon#read 6, iclass 26, count 0 2006.252.08:02:02.78#ibcon#end of sib2, iclass 26, count 0 2006.252.08:02:02.78#ibcon#*after write, iclass 26, count 0 2006.252.08:02:02.78#ibcon#*before return 0, iclass 26, count 0 2006.252.08:02:02.78#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.252.08:02:02.78#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.252.08:02:02.78#ibcon#about to clear, iclass 26 cls_cnt 0 2006.252.08:02:02.78#ibcon#cleared, iclass 26 cls_cnt 0 2006.252.08:02:02.78$4f8m12a/ifd4f 2006.252.08:02:02.78$ifd4f/lo= 2006.252.08:02:02.78$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.252.08:02:02.78$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.252.08:02:02.78$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.252.08:02:02.78$ifd4f/patch= 2006.252.08:02:02.78$ifd4f/patch=lo1,a1,a2,a3,a4 2006.252.08:02:02.78$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.252.08:02:02.78$ifd4f/patch=lo3,a5,a6,a7,a8 2006.252.08:02:02.78$4f8m12a/"form=m,16.000,1:2 2006.252.08:02:02.78$4f8m12a/"tpicd 2006.252.08:02:02.78$4f8m12a/echo=off 2006.252.08:02:02.78$4f8m12a/xlog=off 2006.252.08:02:02.78:!2006.252.08:02:30 2006.252.08:02:16.13#trakl#Source acquired 2006.252.08:02:18.13#flagr#flagr/antenna,acquired 2006.252.08:02:30.00:preob 2006.252.08:02:31.13/onsource/TRACKING 2006.252.08:02:31.13:!2006.252.08:02:40 2006.252.08:02:40.00:data_valid=on 2006.252.08:02:40.00:midob 2006.252.08:02:40.13/onsource/TRACKING 2006.252.08:02:40.13/wx/27.33,1011.2,90 2006.252.08:02:40.32/cable/+6.4100E-03 2006.252.08:02:41.41/va/01,08,usb,yes,33,34 2006.252.08:02:41.41/va/02,07,usb,yes,33,34 2006.252.08:02:41.41/va/03,06,usb,yes,35,35 2006.252.08:02:41.41/va/04,07,usb,yes,33,36 2006.252.08:02:41.41/va/05,07,usb,yes,37,39 2006.252.08:02:41.41/va/06,07,usb,yes,32,32 2006.252.08:02:41.41/va/07,07,usb,yes,32,31 2006.252.08:02:41.41/va/08,07,usb,yes,34,34 2006.252.08:02:41.64/valo/01,532.99,yes,locked 2006.252.08:02:41.64/valo/02,572.99,yes,locked 2006.252.08:02:41.64/valo/03,672.99,yes,locked 2006.252.08:02:41.64/valo/04,832.99,yes,locked 2006.252.08:02:41.64/valo/05,652.99,yes,locked 2006.252.08:02:41.64/valo/06,772.99,yes,locked 2006.252.08:02:41.64/valo/07,832.99,yes,locked 2006.252.08:02:41.64/valo/08,852.99,yes,locked 2006.252.08:02:42.73/vb/01,04,usb,yes,30,29 2006.252.08:02:42.73/vb/02,05,usb,yes,28,30 2006.252.08:02:42.73/vb/03,04,usb,yes,28,32 2006.252.08:02:42.73/vb/04,04,usb,yes,29,29 2006.252.08:02:42.73/vb/05,04,usb,yes,28,32 2006.252.08:02:42.73/vb/06,04,usb,yes,29,32 2006.252.08:02:42.73/vb/07,04,usb,yes,31,31 2006.252.08:02:42.73/vb/08,04,usb,yes,28,32 2006.252.08:02:42.96/vblo/01,632.99,yes,locked 2006.252.08:02:42.96/vblo/02,640.99,yes,locked 2006.252.08:02:42.96/vblo/03,656.99,yes,locked 2006.252.08:02:42.96/vblo/04,712.99,yes,locked 2006.252.08:02:42.96/vblo/05,744.99,yes,locked 2006.252.08:02:42.96/vblo/06,752.99,yes,locked 2006.252.08:02:42.96/vblo/07,734.99,yes,locked 2006.252.08:02:42.96/vblo/08,744.99,yes,locked 2006.252.08:02:43.11/vabw/8 2006.252.08:02:43.26/vbbw/8 2006.252.08:02:43.35/xfe/off,on,14.2 2006.252.08:02:43.72/ifatt/23,28,28,28 2006.252.08:02:44.08/fmout-gps/S +4.79E-07 2006.252.08:02:44.12:!2006.252.08:03:40 2006.252.08:03:40.00:data_valid=off 2006.252.08:03:40.00:postob 2006.252.08:03:40.11/cable/+6.4091E-03 2006.252.08:03:40.11/wx/27.33,1011.1,90 2006.252.08:03:41.08/fmout-gps/S +4.80E-07 2006.252.08:03:41.08:scan_name=252-0804,k06252,60 2006.252.08:03:41.08:source=1044+719,104827.62,714335.9,2000.0,ccw 2006.252.08:03:41.14#flagr#flagr/antenna,new-source 2006.252.08:03:42.14:checkk5 2006.252.08:03:42.51/chk_autoobs//k5ts1/ autoobs is running! 2006.252.08:03:42.89/chk_autoobs//k5ts2/ autoobs is running! 2006.252.08:03:43.26/chk_autoobs//k5ts3/ autoobs is running! 2006.252.08:03:43.64/chk_autoobs//k5ts4/ autoobs is running! 2006.252.08:03:44.01/chk_obsdata//k5ts1/T2520802??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.08:03:44.38/chk_obsdata//k5ts2/T2520802??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.08:03:44.75/chk_obsdata//k5ts3/T2520802??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.08:03:45.12/chk_obsdata//k5ts4/T2520802??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.08:03:45.81/k5log//k5ts1_log_newline 2006.252.08:03:46.51/k5log//k5ts2_log_newline 2006.252.08:03:47.20/k5log//k5ts3_log_newline 2006.252.08:03:47.89/k5log//k5ts4_log_newline 2006.252.08:03:47.91/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.252.08:03:47.91:4f8m12a=2 2006.252.08:03:47.92$4f8m12a/echo=on 2006.252.08:03:47.92$4f8m12a/pcalon 2006.252.08:03:47.92$pcalon/"no phase cal control is implemented here 2006.252.08:03:47.92$4f8m12a/"tpicd=stop 2006.252.08:03:47.92$4f8m12a/vc4f8 2006.252.08:03:47.92$vc4f8/valo=1,532.99 2006.252.08:03:47.92#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.252.08:03:47.92#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.252.08:03:47.92#ibcon#ireg 17 cls_cnt 0 2006.252.08:03:47.92#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.252.08:03:47.92#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.252.08:03:47.92#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.252.08:03:47.92#ibcon#enter wrdev, iclass 33, count 0 2006.252.08:03:47.92#ibcon#first serial, iclass 33, count 0 2006.252.08:03:47.92#ibcon#enter sib2, iclass 33, count 0 2006.252.08:03:47.92#ibcon#flushed, iclass 33, count 0 2006.252.08:03:47.92#ibcon#about to write, iclass 33, count 0 2006.252.08:03:47.92#ibcon#wrote, iclass 33, count 0 2006.252.08:03:47.92#ibcon#about to read 3, iclass 33, count 0 2006.252.08:03:47.96#ibcon#read 3, iclass 33, count 0 2006.252.08:03:47.96#ibcon#about to read 4, iclass 33, count 0 2006.252.08:03:47.96#ibcon#read 4, iclass 33, count 0 2006.252.08:03:47.96#ibcon#about to read 5, iclass 33, count 0 2006.252.08:03:47.96#ibcon#read 5, iclass 33, count 0 2006.252.08:03:47.96#ibcon#about to read 6, iclass 33, count 0 2006.252.08:03:47.96#ibcon#read 6, iclass 33, count 0 2006.252.08:03:47.96#ibcon#end of sib2, iclass 33, count 0 2006.252.08:03:47.96#ibcon#*mode == 0, iclass 33, count 0 2006.252.08:03:47.96#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.252.08:03:47.96#ibcon#[26=FRQ=01,532.99\r\n] 2006.252.08:03:47.96#ibcon#*before write, iclass 33, count 0 2006.252.08:03:47.96#ibcon#enter sib2, iclass 33, count 0 2006.252.08:03:47.96#ibcon#flushed, iclass 33, count 0 2006.252.08:03:47.96#ibcon#about to write, iclass 33, count 0 2006.252.08:03:47.96#ibcon#wrote, iclass 33, count 0 2006.252.08:03:47.96#ibcon#about to read 3, iclass 33, count 0 2006.252.08:03:48.01#ibcon#read 3, iclass 33, count 0 2006.252.08:03:48.01#ibcon#about to read 4, iclass 33, count 0 2006.252.08:03:48.01#ibcon#read 4, iclass 33, count 0 2006.252.08:03:48.01#ibcon#about to read 5, iclass 33, count 0 2006.252.08:03:48.01#ibcon#read 5, iclass 33, count 0 2006.252.08:03:48.01#ibcon#about to read 6, iclass 33, count 0 2006.252.08:03:48.01#ibcon#read 6, iclass 33, count 0 2006.252.08:03:48.01#ibcon#end of sib2, iclass 33, count 0 2006.252.08:03:48.01#ibcon#*after write, iclass 33, count 0 2006.252.08:03:48.01#ibcon#*before return 0, iclass 33, count 0 2006.252.08:03:48.01#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.252.08:03:48.01#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.252.08:03:48.01#ibcon#about to clear, iclass 33 cls_cnt 0 2006.252.08:03:48.01#ibcon#cleared, iclass 33 cls_cnt 0 2006.252.08:03:48.01$vc4f8/va=1,8 2006.252.08:03:48.01#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.252.08:03:48.01#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.252.08:03:48.01#ibcon#ireg 11 cls_cnt 2 2006.252.08:03:48.01#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.252.08:03:48.01#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.252.08:03:48.01#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.252.08:03:48.01#ibcon#enter wrdev, iclass 35, count 2 2006.252.08:03:48.01#ibcon#first serial, iclass 35, count 2 2006.252.08:03:48.01#ibcon#enter sib2, iclass 35, count 2 2006.252.08:03:48.01#ibcon#flushed, iclass 35, count 2 2006.252.08:03:48.01#ibcon#about to write, iclass 35, count 2 2006.252.08:03:48.01#ibcon#wrote, iclass 35, count 2 2006.252.08:03:48.01#ibcon#about to read 3, iclass 35, count 2 2006.252.08:03:48.03#ibcon#read 3, iclass 35, count 2 2006.252.08:03:48.03#ibcon#about to read 4, iclass 35, count 2 2006.252.08:03:48.03#ibcon#read 4, iclass 35, count 2 2006.252.08:03:48.03#ibcon#about to read 5, iclass 35, count 2 2006.252.08:03:48.03#ibcon#read 5, iclass 35, count 2 2006.252.08:03:48.03#ibcon#about to read 6, iclass 35, count 2 2006.252.08:03:48.03#ibcon#read 6, iclass 35, count 2 2006.252.08:03:48.03#ibcon#end of sib2, iclass 35, count 2 2006.252.08:03:48.03#ibcon#*mode == 0, iclass 35, count 2 2006.252.08:03:48.03#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.252.08:03:48.03#ibcon#[25=AT01-08\r\n] 2006.252.08:03:48.03#ibcon#*before write, iclass 35, count 2 2006.252.08:03:48.03#ibcon#enter sib2, iclass 35, count 2 2006.252.08:03:48.03#ibcon#flushed, iclass 35, count 2 2006.252.08:03:48.03#ibcon#about to write, iclass 35, count 2 2006.252.08:03:48.03#ibcon#wrote, iclass 35, count 2 2006.252.08:03:48.03#ibcon#about to read 3, iclass 35, count 2 2006.252.08:03:48.06#ibcon#read 3, iclass 35, count 2 2006.252.08:03:48.06#ibcon#about to read 4, iclass 35, count 2 2006.252.08:03:48.06#ibcon#read 4, iclass 35, count 2 2006.252.08:03:48.06#ibcon#about to read 5, iclass 35, count 2 2006.252.08:03:48.06#ibcon#read 5, iclass 35, count 2 2006.252.08:03:48.06#ibcon#about to read 6, iclass 35, count 2 2006.252.08:03:48.06#ibcon#read 6, iclass 35, count 2 2006.252.08:03:48.06#ibcon#end of sib2, iclass 35, count 2 2006.252.08:03:48.06#ibcon#*after write, iclass 35, count 2 2006.252.08:03:48.06#ibcon#*before return 0, iclass 35, count 2 2006.252.08:03:48.06#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.252.08:03:48.06#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.252.08:03:48.06#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.252.08:03:48.06#ibcon#ireg 7 cls_cnt 0 2006.252.08:03:48.06#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.252.08:03:48.18#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.252.08:03:48.18#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.252.08:03:48.18#ibcon#enter wrdev, iclass 35, count 0 2006.252.08:03:48.18#ibcon#first serial, iclass 35, count 0 2006.252.08:03:48.18#ibcon#enter sib2, iclass 35, count 0 2006.252.08:03:48.18#ibcon#flushed, iclass 35, count 0 2006.252.08:03:48.18#ibcon#about to write, iclass 35, count 0 2006.252.08:03:48.18#ibcon#wrote, iclass 35, count 0 2006.252.08:03:48.18#ibcon#about to read 3, iclass 35, count 0 2006.252.08:03:48.20#ibcon#read 3, iclass 35, count 0 2006.252.08:03:48.20#ibcon#about to read 4, iclass 35, count 0 2006.252.08:03:48.20#ibcon#read 4, iclass 35, count 0 2006.252.08:03:48.20#ibcon#about to read 5, iclass 35, count 0 2006.252.08:03:48.20#ibcon#read 5, iclass 35, count 0 2006.252.08:03:48.20#ibcon#about to read 6, iclass 35, count 0 2006.252.08:03:48.20#ibcon#read 6, iclass 35, count 0 2006.252.08:03:48.20#ibcon#end of sib2, iclass 35, count 0 2006.252.08:03:48.20#ibcon#*mode == 0, iclass 35, count 0 2006.252.08:03:48.20#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.252.08:03:48.20#ibcon#[25=USB\r\n] 2006.252.08:03:48.20#ibcon#*before write, iclass 35, count 0 2006.252.08:03:48.20#ibcon#enter sib2, iclass 35, count 0 2006.252.08:03:48.20#ibcon#flushed, iclass 35, count 0 2006.252.08:03:48.20#ibcon#about to write, iclass 35, count 0 2006.252.08:03:48.20#ibcon#wrote, iclass 35, count 0 2006.252.08:03:48.20#ibcon#about to read 3, iclass 35, count 0 2006.252.08:03:48.23#ibcon#read 3, iclass 35, count 0 2006.252.08:03:48.23#ibcon#about to read 4, iclass 35, count 0 2006.252.08:03:48.23#ibcon#read 4, iclass 35, count 0 2006.252.08:03:48.23#ibcon#about to read 5, iclass 35, count 0 2006.252.08:03:48.23#ibcon#read 5, iclass 35, count 0 2006.252.08:03:48.23#ibcon#about to read 6, iclass 35, count 0 2006.252.08:03:48.23#ibcon#read 6, iclass 35, count 0 2006.252.08:03:48.23#ibcon#end of sib2, iclass 35, count 0 2006.252.08:03:48.23#ibcon#*after write, iclass 35, count 0 2006.252.08:03:48.23#ibcon#*before return 0, iclass 35, count 0 2006.252.08:03:48.23#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.252.08:03:48.23#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.252.08:03:48.23#ibcon#about to clear, iclass 35 cls_cnt 0 2006.252.08:03:48.23#ibcon#cleared, iclass 35 cls_cnt 0 2006.252.08:03:48.23$vc4f8/valo=2,572.99 2006.252.08:03:48.23#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.252.08:03:48.23#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.252.08:03:48.23#ibcon#ireg 17 cls_cnt 0 2006.252.08:03:48.23#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.252.08:03:48.23#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.252.08:03:48.23#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.252.08:03:48.23#ibcon#enter wrdev, iclass 37, count 0 2006.252.08:03:48.23#ibcon#first serial, iclass 37, count 0 2006.252.08:03:48.23#ibcon#enter sib2, iclass 37, count 0 2006.252.08:03:48.23#ibcon#flushed, iclass 37, count 0 2006.252.08:03:48.23#ibcon#about to write, iclass 37, count 0 2006.252.08:03:48.23#ibcon#wrote, iclass 37, count 0 2006.252.08:03:48.23#ibcon#about to read 3, iclass 37, count 0 2006.252.08:03:48.25#ibcon#read 3, iclass 37, count 0 2006.252.08:03:48.25#ibcon#about to read 4, iclass 37, count 0 2006.252.08:03:48.25#ibcon#read 4, iclass 37, count 0 2006.252.08:03:48.25#ibcon#about to read 5, iclass 37, count 0 2006.252.08:03:48.25#ibcon#read 5, iclass 37, count 0 2006.252.08:03:48.25#ibcon#about to read 6, iclass 37, count 0 2006.252.08:03:48.25#ibcon#read 6, iclass 37, count 0 2006.252.08:03:48.25#ibcon#end of sib2, iclass 37, count 0 2006.252.08:03:48.25#ibcon#*mode == 0, iclass 37, count 0 2006.252.08:03:48.25#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.252.08:03:48.25#ibcon#[26=FRQ=02,572.99\r\n] 2006.252.08:03:48.25#ibcon#*before write, iclass 37, count 0 2006.252.08:03:48.25#ibcon#enter sib2, iclass 37, count 0 2006.252.08:03:48.25#ibcon#flushed, iclass 37, count 0 2006.252.08:03:48.25#ibcon#about to write, iclass 37, count 0 2006.252.08:03:48.25#ibcon#wrote, iclass 37, count 0 2006.252.08:03:48.25#ibcon#about to read 3, iclass 37, count 0 2006.252.08:03:48.30#ibcon#read 3, iclass 37, count 0 2006.252.08:03:48.30#ibcon#about to read 4, iclass 37, count 0 2006.252.08:03:48.30#ibcon#read 4, iclass 37, count 0 2006.252.08:03:48.30#ibcon#about to read 5, iclass 37, count 0 2006.252.08:03:48.30#ibcon#read 5, iclass 37, count 0 2006.252.08:03:48.30#ibcon#about to read 6, iclass 37, count 0 2006.252.08:03:48.30#ibcon#read 6, iclass 37, count 0 2006.252.08:03:48.30#ibcon#end of sib2, iclass 37, count 0 2006.252.08:03:48.30#ibcon#*after write, iclass 37, count 0 2006.252.08:03:48.30#ibcon#*before return 0, iclass 37, count 0 2006.252.08:03:48.30#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.252.08:03:48.30#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.252.08:03:48.30#ibcon#about to clear, iclass 37 cls_cnt 0 2006.252.08:03:48.30#ibcon#cleared, iclass 37 cls_cnt 0 2006.252.08:03:48.30$vc4f8/va=2,7 2006.252.08:03:48.30#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.252.08:03:48.30#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.252.08:03:48.30#ibcon#ireg 11 cls_cnt 2 2006.252.08:03:48.30#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.252.08:03:48.35#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.252.08:03:48.35#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.252.08:03:48.35#ibcon#enter wrdev, iclass 39, count 2 2006.252.08:03:48.35#ibcon#first serial, iclass 39, count 2 2006.252.08:03:48.35#ibcon#enter sib2, iclass 39, count 2 2006.252.08:03:48.35#ibcon#flushed, iclass 39, count 2 2006.252.08:03:48.35#ibcon#about to write, iclass 39, count 2 2006.252.08:03:48.35#ibcon#wrote, iclass 39, count 2 2006.252.08:03:48.35#ibcon#about to read 3, iclass 39, count 2 2006.252.08:03:48.37#ibcon#read 3, iclass 39, count 2 2006.252.08:03:48.37#ibcon#about to read 4, iclass 39, count 2 2006.252.08:03:48.37#ibcon#read 4, iclass 39, count 2 2006.252.08:03:48.37#ibcon#about to read 5, iclass 39, count 2 2006.252.08:03:48.37#ibcon#read 5, iclass 39, count 2 2006.252.08:03:48.37#ibcon#about to read 6, iclass 39, count 2 2006.252.08:03:48.37#ibcon#read 6, iclass 39, count 2 2006.252.08:03:48.37#ibcon#end of sib2, iclass 39, count 2 2006.252.08:03:48.37#ibcon#*mode == 0, iclass 39, count 2 2006.252.08:03:48.37#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.252.08:03:48.37#ibcon#[25=AT02-07\r\n] 2006.252.08:03:48.37#ibcon#*before write, iclass 39, count 2 2006.252.08:03:48.37#ibcon#enter sib2, iclass 39, count 2 2006.252.08:03:48.37#ibcon#flushed, iclass 39, count 2 2006.252.08:03:48.37#ibcon#about to write, iclass 39, count 2 2006.252.08:03:48.37#ibcon#wrote, iclass 39, count 2 2006.252.08:03:48.37#ibcon#about to read 3, iclass 39, count 2 2006.252.08:03:48.40#ibcon#read 3, iclass 39, count 2 2006.252.08:03:48.40#ibcon#about to read 4, iclass 39, count 2 2006.252.08:03:48.40#ibcon#read 4, iclass 39, count 2 2006.252.08:03:48.40#ibcon#about to read 5, iclass 39, count 2 2006.252.08:03:48.40#ibcon#read 5, iclass 39, count 2 2006.252.08:03:48.40#ibcon#about to read 6, iclass 39, count 2 2006.252.08:03:48.40#ibcon#read 6, iclass 39, count 2 2006.252.08:03:48.40#ibcon#end of sib2, iclass 39, count 2 2006.252.08:03:48.40#ibcon#*after write, iclass 39, count 2 2006.252.08:03:48.40#ibcon#*before return 0, iclass 39, count 2 2006.252.08:03:48.40#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.252.08:03:48.40#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.252.08:03:48.40#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.252.08:03:48.40#ibcon#ireg 7 cls_cnt 0 2006.252.08:03:48.40#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.252.08:03:48.52#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.252.08:03:48.52#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.252.08:03:48.52#ibcon#enter wrdev, iclass 39, count 0 2006.252.08:03:48.52#ibcon#first serial, iclass 39, count 0 2006.252.08:03:48.52#ibcon#enter sib2, iclass 39, count 0 2006.252.08:03:48.52#ibcon#flushed, iclass 39, count 0 2006.252.08:03:48.52#ibcon#about to write, iclass 39, count 0 2006.252.08:03:48.52#ibcon#wrote, iclass 39, count 0 2006.252.08:03:48.52#ibcon#about to read 3, iclass 39, count 0 2006.252.08:03:48.54#ibcon#read 3, iclass 39, count 0 2006.252.08:03:48.54#ibcon#about to read 4, iclass 39, count 0 2006.252.08:03:48.54#ibcon#read 4, iclass 39, count 0 2006.252.08:03:48.54#ibcon#about to read 5, iclass 39, count 0 2006.252.08:03:48.54#ibcon#read 5, iclass 39, count 0 2006.252.08:03:48.54#ibcon#about to read 6, iclass 39, count 0 2006.252.08:03:48.54#ibcon#read 6, iclass 39, count 0 2006.252.08:03:48.54#ibcon#end of sib2, iclass 39, count 0 2006.252.08:03:48.54#ibcon#*mode == 0, iclass 39, count 0 2006.252.08:03:48.54#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.252.08:03:48.54#ibcon#[25=USB\r\n] 2006.252.08:03:48.54#ibcon#*before write, iclass 39, count 0 2006.252.08:03:48.54#ibcon#enter sib2, iclass 39, count 0 2006.252.08:03:48.54#ibcon#flushed, iclass 39, count 0 2006.252.08:03:48.54#ibcon#about to write, iclass 39, count 0 2006.252.08:03:48.54#ibcon#wrote, iclass 39, count 0 2006.252.08:03:48.54#ibcon#about to read 3, iclass 39, count 0 2006.252.08:03:48.57#ibcon#read 3, iclass 39, count 0 2006.252.08:03:48.57#ibcon#about to read 4, iclass 39, count 0 2006.252.08:03:48.57#ibcon#read 4, iclass 39, count 0 2006.252.08:03:48.57#ibcon#about to read 5, iclass 39, count 0 2006.252.08:03:48.57#ibcon#read 5, iclass 39, count 0 2006.252.08:03:48.57#ibcon#about to read 6, iclass 39, count 0 2006.252.08:03:48.57#ibcon#read 6, iclass 39, count 0 2006.252.08:03:48.57#ibcon#end of sib2, iclass 39, count 0 2006.252.08:03:48.57#ibcon#*after write, iclass 39, count 0 2006.252.08:03:48.57#ibcon#*before return 0, iclass 39, count 0 2006.252.08:03:48.57#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.252.08:03:48.57#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.252.08:03:48.57#ibcon#about to clear, iclass 39 cls_cnt 0 2006.252.08:03:48.57#ibcon#cleared, iclass 39 cls_cnt 0 2006.252.08:03:48.57$vc4f8/valo=3,672.99 2006.252.08:03:48.57#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.252.08:03:48.57#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.252.08:03:48.57#ibcon#ireg 17 cls_cnt 0 2006.252.08:03:48.57#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.252.08:03:48.57#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.252.08:03:48.57#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.252.08:03:48.57#ibcon#enter wrdev, iclass 3, count 0 2006.252.08:03:48.57#ibcon#first serial, iclass 3, count 0 2006.252.08:03:48.57#ibcon#enter sib2, iclass 3, count 0 2006.252.08:03:48.57#ibcon#flushed, iclass 3, count 0 2006.252.08:03:48.57#ibcon#about to write, iclass 3, count 0 2006.252.08:03:48.57#ibcon#wrote, iclass 3, count 0 2006.252.08:03:48.57#ibcon#about to read 3, iclass 3, count 0 2006.252.08:03:48.59#ibcon#read 3, iclass 3, count 0 2006.252.08:03:48.59#ibcon#about to read 4, iclass 3, count 0 2006.252.08:03:48.59#ibcon#read 4, iclass 3, count 0 2006.252.08:03:48.59#ibcon#about to read 5, iclass 3, count 0 2006.252.08:03:48.59#ibcon#read 5, iclass 3, count 0 2006.252.08:03:48.59#ibcon#about to read 6, iclass 3, count 0 2006.252.08:03:48.59#ibcon#read 6, iclass 3, count 0 2006.252.08:03:48.59#ibcon#end of sib2, iclass 3, count 0 2006.252.08:03:48.59#ibcon#*mode == 0, iclass 3, count 0 2006.252.08:03:48.59#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.252.08:03:48.59#ibcon#[26=FRQ=03,672.99\r\n] 2006.252.08:03:48.59#ibcon#*before write, iclass 3, count 0 2006.252.08:03:48.59#ibcon#enter sib2, iclass 3, count 0 2006.252.08:03:48.59#ibcon#flushed, iclass 3, count 0 2006.252.08:03:48.59#ibcon#about to write, iclass 3, count 0 2006.252.08:03:48.59#ibcon#wrote, iclass 3, count 0 2006.252.08:03:48.59#ibcon#about to read 3, iclass 3, count 0 2006.252.08:03:48.64#ibcon#read 3, iclass 3, count 0 2006.252.08:03:48.64#ibcon#about to read 4, iclass 3, count 0 2006.252.08:03:48.64#ibcon#read 4, iclass 3, count 0 2006.252.08:03:48.64#ibcon#about to read 5, iclass 3, count 0 2006.252.08:03:48.64#ibcon#read 5, iclass 3, count 0 2006.252.08:03:48.64#ibcon#about to read 6, iclass 3, count 0 2006.252.08:03:48.64#ibcon#read 6, iclass 3, count 0 2006.252.08:03:48.64#ibcon#end of sib2, iclass 3, count 0 2006.252.08:03:48.64#ibcon#*after write, iclass 3, count 0 2006.252.08:03:48.64#ibcon#*before return 0, iclass 3, count 0 2006.252.08:03:48.64#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.252.08:03:48.64#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.252.08:03:48.64#ibcon#about to clear, iclass 3 cls_cnt 0 2006.252.08:03:48.64#ibcon#cleared, iclass 3 cls_cnt 0 2006.252.08:03:48.64$vc4f8/va=3,6 2006.252.08:03:48.64#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.252.08:03:48.64#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.252.08:03:48.64#ibcon#ireg 11 cls_cnt 2 2006.252.08:03:48.64#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.252.08:03:48.69#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.252.08:03:48.69#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.252.08:03:48.69#ibcon#enter wrdev, iclass 5, count 2 2006.252.08:03:48.69#ibcon#first serial, iclass 5, count 2 2006.252.08:03:48.69#ibcon#enter sib2, iclass 5, count 2 2006.252.08:03:48.69#ibcon#flushed, iclass 5, count 2 2006.252.08:03:48.69#ibcon#about to write, iclass 5, count 2 2006.252.08:03:48.69#ibcon#wrote, iclass 5, count 2 2006.252.08:03:48.69#ibcon#about to read 3, iclass 5, count 2 2006.252.08:03:48.71#ibcon#read 3, iclass 5, count 2 2006.252.08:03:48.71#ibcon#about to read 4, iclass 5, count 2 2006.252.08:03:48.71#ibcon#read 4, iclass 5, count 2 2006.252.08:03:48.71#ibcon#about to read 5, iclass 5, count 2 2006.252.08:03:48.71#ibcon#read 5, iclass 5, count 2 2006.252.08:03:48.71#ibcon#about to read 6, iclass 5, count 2 2006.252.08:03:48.71#ibcon#read 6, iclass 5, count 2 2006.252.08:03:48.71#ibcon#end of sib2, iclass 5, count 2 2006.252.08:03:48.71#ibcon#*mode == 0, iclass 5, count 2 2006.252.08:03:48.71#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.252.08:03:48.71#ibcon#[25=AT03-06\r\n] 2006.252.08:03:48.71#ibcon#*before write, iclass 5, count 2 2006.252.08:03:48.71#ibcon#enter sib2, iclass 5, count 2 2006.252.08:03:48.71#ibcon#flushed, iclass 5, count 2 2006.252.08:03:48.71#ibcon#about to write, iclass 5, count 2 2006.252.08:03:48.71#ibcon#wrote, iclass 5, count 2 2006.252.08:03:48.71#ibcon#about to read 3, iclass 5, count 2 2006.252.08:03:48.74#ibcon#read 3, iclass 5, count 2 2006.252.08:03:48.74#ibcon#about to read 4, iclass 5, count 2 2006.252.08:03:48.74#ibcon#read 4, iclass 5, count 2 2006.252.08:03:48.74#ibcon#about to read 5, iclass 5, count 2 2006.252.08:03:48.74#ibcon#read 5, iclass 5, count 2 2006.252.08:03:48.74#ibcon#about to read 6, iclass 5, count 2 2006.252.08:03:48.74#ibcon#read 6, iclass 5, count 2 2006.252.08:03:48.74#ibcon#end of sib2, iclass 5, count 2 2006.252.08:03:48.74#ibcon#*after write, iclass 5, count 2 2006.252.08:03:48.74#ibcon#*before return 0, iclass 5, count 2 2006.252.08:03:48.74#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.252.08:03:48.74#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.252.08:03:48.74#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.252.08:03:48.74#ibcon#ireg 7 cls_cnt 0 2006.252.08:03:48.74#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.252.08:03:48.86#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.252.08:03:48.86#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.252.08:03:48.86#ibcon#enter wrdev, iclass 5, count 0 2006.252.08:03:48.86#ibcon#first serial, iclass 5, count 0 2006.252.08:03:48.86#ibcon#enter sib2, iclass 5, count 0 2006.252.08:03:48.86#ibcon#flushed, iclass 5, count 0 2006.252.08:03:48.86#ibcon#about to write, iclass 5, count 0 2006.252.08:03:48.86#ibcon#wrote, iclass 5, count 0 2006.252.08:03:48.86#ibcon#about to read 3, iclass 5, count 0 2006.252.08:03:48.88#ibcon#read 3, iclass 5, count 0 2006.252.08:03:48.88#ibcon#about to read 4, iclass 5, count 0 2006.252.08:03:48.88#ibcon#read 4, iclass 5, count 0 2006.252.08:03:48.88#ibcon#about to read 5, iclass 5, count 0 2006.252.08:03:48.88#ibcon#read 5, iclass 5, count 0 2006.252.08:03:48.88#ibcon#about to read 6, iclass 5, count 0 2006.252.08:03:48.88#ibcon#read 6, iclass 5, count 0 2006.252.08:03:48.88#ibcon#end of sib2, iclass 5, count 0 2006.252.08:03:48.88#ibcon#*mode == 0, iclass 5, count 0 2006.252.08:03:48.88#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.252.08:03:48.88#ibcon#[25=USB\r\n] 2006.252.08:03:48.88#ibcon#*before write, iclass 5, count 0 2006.252.08:03:48.88#ibcon#enter sib2, iclass 5, count 0 2006.252.08:03:48.88#ibcon#flushed, iclass 5, count 0 2006.252.08:03:48.88#ibcon#about to write, iclass 5, count 0 2006.252.08:03:48.88#ibcon#wrote, iclass 5, count 0 2006.252.08:03:48.88#ibcon#about to read 3, iclass 5, count 0 2006.252.08:03:48.91#ibcon#read 3, iclass 5, count 0 2006.252.08:03:48.91#ibcon#about to read 4, iclass 5, count 0 2006.252.08:03:48.91#ibcon#read 4, iclass 5, count 0 2006.252.08:03:48.91#ibcon#about to read 5, iclass 5, count 0 2006.252.08:03:48.91#ibcon#read 5, iclass 5, count 0 2006.252.08:03:48.91#ibcon#about to read 6, iclass 5, count 0 2006.252.08:03:48.91#ibcon#read 6, iclass 5, count 0 2006.252.08:03:48.91#ibcon#end of sib2, iclass 5, count 0 2006.252.08:03:48.91#ibcon#*after write, iclass 5, count 0 2006.252.08:03:48.91#ibcon#*before return 0, iclass 5, count 0 2006.252.08:03:48.91#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.252.08:03:48.91#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.252.08:03:48.91#ibcon#about to clear, iclass 5 cls_cnt 0 2006.252.08:03:48.91#ibcon#cleared, iclass 5 cls_cnt 0 2006.252.08:03:48.91$vc4f8/valo=4,832.99 2006.252.08:03:48.91#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.252.08:03:48.91#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.252.08:03:48.91#ibcon#ireg 17 cls_cnt 0 2006.252.08:03:48.91#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.252.08:03:48.91#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.252.08:03:48.91#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.252.08:03:48.91#ibcon#enter wrdev, iclass 7, count 0 2006.252.08:03:48.91#ibcon#first serial, iclass 7, count 0 2006.252.08:03:48.91#ibcon#enter sib2, iclass 7, count 0 2006.252.08:03:48.91#ibcon#flushed, iclass 7, count 0 2006.252.08:03:48.91#ibcon#about to write, iclass 7, count 0 2006.252.08:03:48.91#ibcon#wrote, iclass 7, count 0 2006.252.08:03:48.91#ibcon#about to read 3, iclass 7, count 0 2006.252.08:03:48.93#ibcon#read 3, iclass 7, count 0 2006.252.08:03:48.93#ibcon#about to read 4, iclass 7, count 0 2006.252.08:03:48.93#ibcon#read 4, iclass 7, count 0 2006.252.08:03:48.93#ibcon#about to read 5, iclass 7, count 0 2006.252.08:03:48.93#ibcon#read 5, iclass 7, count 0 2006.252.08:03:48.93#ibcon#about to read 6, iclass 7, count 0 2006.252.08:03:48.93#ibcon#read 6, iclass 7, count 0 2006.252.08:03:48.93#ibcon#end of sib2, iclass 7, count 0 2006.252.08:03:48.93#ibcon#*mode == 0, iclass 7, count 0 2006.252.08:03:48.93#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.252.08:03:48.93#ibcon#[26=FRQ=04,832.99\r\n] 2006.252.08:03:48.93#ibcon#*before write, iclass 7, count 0 2006.252.08:03:48.93#ibcon#enter sib2, iclass 7, count 0 2006.252.08:03:48.93#ibcon#flushed, iclass 7, count 0 2006.252.08:03:48.93#ibcon#about to write, iclass 7, count 0 2006.252.08:03:48.93#ibcon#wrote, iclass 7, count 0 2006.252.08:03:48.93#ibcon#about to read 3, iclass 7, count 0 2006.252.08:03:48.98#ibcon#read 3, iclass 7, count 0 2006.252.08:03:48.98#ibcon#about to read 4, iclass 7, count 0 2006.252.08:03:48.98#ibcon#read 4, iclass 7, count 0 2006.252.08:03:48.98#ibcon#about to read 5, iclass 7, count 0 2006.252.08:03:48.98#ibcon#read 5, iclass 7, count 0 2006.252.08:03:48.98#ibcon#about to read 6, iclass 7, count 0 2006.252.08:03:48.98#ibcon#read 6, iclass 7, count 0 2006.252.08:03:48.98#ibcon#end of sib2, iclass 7, count 0 2006.252.08:03:48.98#ibcon#*after write, iclass 7, count 0 2006.252.08:03:48.98#ibcon#*before return 0, iclass 7, count 0 2006.252.08:03:48.98#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.252.08:03:48.98#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.252.08:03:48.98#ibcon#about to clear, iclass 7 cls_cnt 0 2006.252.08:03:48.98#ibcon#cleared, iclass 7 cls_cnt 0 2006.252.08:03:48.98$vc4f8/va=4,7 2006.252.08:03:48.98#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.252.08:03:48.98#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.252.08:03:48.98#ibcon#ireg 11 cls_cnt 2 2006.252.08:03:48.98#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.252.08:03:49.03#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.252.08:03:49.03#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.252.08:03:49.03#ibcon#enter wrdev, iclass 11, count 2 2006.252.08:03:49.03#ibcon#first serial, iclass 11, count 2 2006.252.08:03:49.03#ibcon#enter sib2, iclass 11, count 2 2006.252.08:03:49.03#ibcon#flushed, iclass 11, count 2 2006.252.08:03:49.03#ibcon#about to write, iclass 11, count 2 2006.252.08:03:49.03#ibcon#wrote, iclass 11, count 2 2006.252.08:03:49.03#ibcon#about to read 3, iclass 11, count 2 2006.252.08:03:49.05#ibcon#read 3, iclass 11, count 2 2006.252.08:03:49.05#ibcon#about to read 4, iclass 11, count 2 2006.252.08:03:49.05#ibcon#read 4, iclass 11, count 2 2006.252.08:03:49.05#ibcon#about to read 5, iclass 11, count 2 2006.252.08:03:49.05#ibcon#read 5, iclass 11, count 2 2006.252.08:03:49.05#ibcon#about to read 6, iclass 11, count 2 2006.252.08:03:49.05#ibcon#read 6, iclass 11, count 2 2006.252.08:03:49.05#ibcon#end of sib2, iclass 11, count 2 2006.252.08:03:49.05#ibcon#*mode == 0, iclass 11, count 2 2006.252.08:03:49.05#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.252.08:03:49.05#ibcon#[25=AT04-07\r\n] 2006.252.08:03:49.05#ibcon#*before write, iclass 11, count 2 2006.252.08:03:49.05#ibcon#enter sib2, iclass 11, count 2 2006.252.08:03:49.05#ibcon#flushed, iclass 11, count 2 2006.252.08:03:49.05#ibcon#about to write, iclass 11, count 2 2006.252.08:03:49.05#ibcon#wrote, iclass 11, count 2 2006.252.08:03:49.05#ibcon#about to read 3, iclass 11, count 2 2006.252.08:03:49.08#ibcon#read 3, iclass 11, count 2 2006.252.08:03:49.08#ibcon#about to read 4, iclass 11, count 2 2006.252.08:03:49.08#ibcon#read 4, iclass 11, count 2 2006.252.08:03:49.08#ibcon#about to read 5, iclass 11, count 2 2006.252.08:03:49.08#ibcon#read 5, iclass 11, count 2 2006.252.08:03:49.08#ibcon#about to read 6, iclass 11, count 2 2006.252.08:03:49.08#ibcon#read 6, iclass 11, count 2 2006.252.08:03:49.08#ibcon#end of sib2, iclass 11, count 2 2006.252.08:03:49.08#ibcon#*after write, iclass 11, count 2 2006.252.08:03:49.08#ibcon#*before return 0, iclass 11, count 2 2006.252.08:03:49.08#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.252.08:03:49.08#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.252.08:03:49.08#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.252.08:03:49.08#ibcon#ireg 7 cls_cnt 0 2006.252.08:03:49.08#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.252.08:03:49.20#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.252.08:03:49.20#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.252.08:03:49.20#ibcon#enter wrdev, iclass 11, count 0 2006.252.08:03:49.20#ibcon#first serial, iclass 11, count 0 2006.252.08:03:49.20#ibcon#enter sib2, iclass 11, count 0 2006.252.08:03:49.20#ibcon#flushed, iclass 11, count 0 2006.252.08:03:49.20#ibcon#about to write, iclass 11, count 0 2006.252.08:03:49.20#ibcon#wrote, iclass 11, count 0 2006.252.08:03:49.20#ibcon#about to read 3, iclass 11, count 0 2006.252.08:03:49.22#ibcon#read 3, iclass 11, count 0 2006.252.08:03:49.22#ibcon#about to read 4, iclass 11, count 0 2006.252.08:03:49.22#ibcon#read 4, iclass 11, count 0 2006.252.08:03:49.22#ibcon#about to read 5, iclass 11, count 0 2006.252.08:03:49.22#ibcon#read 5, iclass 11, count 0 2006.252.08:03:49.22#ibcon#about to read 6, iclass 11, count 0 2006.252.08:03:49.22#ibcon#read 6, iclass 11, count 0 2006.252.08:03:49.22#ibcon#end of sib2, iclass 11, count 0 2006.252.08:03:49.22#ibcon#*mode == 0, iclass 11, count 0 2006.252.08:03:49.22#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.252.08:03:49.22#ibcon#[25=USB\r\n] 2006.252.08:03:49.22#ibcon#*before write, iclass 11, count 0 2006.252.08:03:49.22#ibcon#enter sib2, iclass 11, count 0 2006.252.08:03:49.22#ibcon#flushed, iclass 11, count 0 2006.252.08:03:49.22#ibcon#about to write, iclass 11, count 0 2006.252.08:03:49.22#ibcon#wrote, iclass 11, count 0 2006.252.08:03:49.22#ibcon#about to read 3, iclass 11, count 0 2006.252.08:03:49.25#ibcon#read 3, iclass 11, count 0 2006.252.08:03:49.25#ibcon#about to read 4, iclass 11, count 0 2006.252.08:03:49.25#ibcon#read 4, iclass 11, count 0 2006.252.08:03:49.25#ibcon#about to read 5, iclass 11, count 0 2006.252.08:03:49.25#ibcon#read 5, iclass 11, count 0 2006.252.08:03:49.25#ibcon#about to read 6, iclass 11, count 0 2006.252.08:03:49.25#ibcon#read 6, iclass 11, count 0 2006.252.08:03:49.25#ibcon#end of sib2, iclass 11, count 0 2006.252.08:03:49.25#ibcon#*after write, iclass 11, count 0 2006.252.08:03:49.25#ibcon#*before return 0, iclass 11, count 0 2006.252.08:03:49.25#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.252.08:03:49.25#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.252.08:03:49.25#ibcon#about to clear, iclass 11 cls_cnt 0 2006.252.08:03:49.25#ibcon#cleared, iclass 11 cls_cnt 0 2006.252.08:03:49.25$vc4f8/valo=5,652.99 2006.252.08:03:49.25#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.252.08:03:49.25#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.252.08:03:49.25#ibcon#ireg 17 cls_cnt 0 2006.252.08:03:49.25#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.252.08:03:49.25#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.252.08:03:49.25#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.252.08:03:49.25#ibcon#enter wrdev, iclass 13, count 0 2006.252.08:03:49.25#ibcon#first serial, iclass 13, count 0 2006.252.08:03:49.25#ibcon#enter sib2, iclass 13, count 0 2006.252.08:03:49.25#ibcon#flushed, iclass 13, count 0 2006.252.08:03:49.25#ibcon#about to write, iclass 13, count 0 2006.252.08:03:49.25#ibcon#wrote, iclass 13, count 0 2006.252.08:03:49.25#ibcon#about to read 3, iclass 13, count 0 2006.252.08:03:49.27#ibcon#read 3, iclass 13, count 0 2006.252.08:03:49.27#ibcon#about to read 4, iclass 13, count 0 2006.252.08:03:49.27#ibcon#read 4, iclass 13, count 0 2006.252.08:03:49.27#ibcon#about to read 5, iclass 13, count 0 2006.252.08:03:49.27#ibcon#read 5, iclass 13, count 0 2006.252.08:03:49.27#ibcon#about to read 6, iclass 13, count 0 2006.252.08:03:49.27#ibcon#read 6, iclass 13, count 0 2006.252.08:03:49.27#ibcon#end of sib2, iclass 13, count 0 2006.252.08:03:49.27#ibcon#*mode == 0, iclass 13, count 0 2006.252.08:03:49.27#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.252.08:03:49.27#ibcon#[26=FRQ=05,652.99\r\n] 2006.252.08:03:49.27#ibcon#*before write, iclass 13, count 0 2006.252.08:03:49.27#ibcon#enter sib2, iclass 13, count 0 2006.252.08:03:49.27#ibcon#flushed, iclass 13, count 0 2006.252.08:03:49.27#ibcon#about to write, iclass 13, count 0 2006.252.08:03:49.27#ibcon#wrote, iclass 13, count 0 2006.252.08:03:49.27#ibcon#about to read 3, iclass 13, count 0 2006.252.08:03:49.31#ibcon#read 3, iclass 13, count 0 2006.252.08:03:49.31#ibcon#about to read 4, iclass 13, count 0 2006.252.08:03:49.31#ibcon#read 4, iclass 13, count 0 2006.252.08:03:49.31#ibcon#about to read 5, iclass 13, count 0 2006.252.08:03:49.31#ibcon#read 5, iclass 13, count 0 2006.252.08:03:49.31#ibcon#about to read 6, iclass 13, count 0 2006.252.08:03:49.31#ibcon#read 6, iclass 13, count 0 2006.252.08:03:49.31#ibcon#end of sib2, iclass 13, count 0 2006.252.08:03:49.31#ibcon#*after write, iclass 13, count 0 2006.252.08:03:49.31#ibcon#*before return 0, iclass 13, count 0 2006.252.08:03:49.31#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.252.08:03:49.31#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.252.08:03:49.31#ibcon#about to clear, iclass 13 cls_cnt 0 2006.252.08:03:49.31#ibcon#cleared, iclass 13 cls_cnt 0 2006.252.08:03:49.31$vc4f8/va=5,7 2006.252.08:03:49.31#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.252.08:03:49.31#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.252.08:03:49.31#ibcon#ireg 11 cls_cnt 2 2006.252.08:03:49.31#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.252.08:03:49.37#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.252.08:03:49.37#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.252.08:03:49.37#ibcon#enter wrdev, iclass 15, count 2 2006.252.08:03:49.37#ibcon#first serial, iclass 15, count 2 2006.252.08:03:49.37#ibcon#enter sib2, iclass 15, count 2 2006.252.08:03:49.37#ibcon#flushed, iclass 15, count 2 2006.252.08:03:49.37#ibcon#about to write, iclass 15, count 2 2006.252.08:03:49.37#ibcon#wrote, iclass 15, count 2 2006.252.08:03:49.37#ibcon#about to read 3, iclass 15, count 2 2006.252.08:03:49.39#ibcon#read 3, iclass 15, count 2 2006.252.08:03:49.39#ibcon#about to read 4, iclass 15, count 2 2006.252.08:03:49.39#ibcon#read 4, iclass 15, count 2 2006.252.08:03:49.39#ibcon#about to read 5, iclass 15, count 2 2006.252.08:03:49.39#ibcon#read 5, iclass 15, count 2 2006.252.08:03:49.39#ibcon#about to read 6, iclass 15, count 2 2006.252.08:03:49.39#ibcon#read 6, iclass 15, count 2 2006.252.08:03:49.39#ibcon#end of sib2, iclass 15, count 2 2006.252.08:03:49.39#ibcon#*mode == 0, iclass 15, count 2 2006.252.08:03:49.39#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.252.08:03:49.39#ibcon#[25=AT05-07\r\n] 2006.252.08:03:49.39#ibcon#*before write, iclass 15, count 2 2006.252.08:03:49.39#ibcon#enter sib2, iclass 15, count 2 2006.252.08:03:49.39#ibcon#flushed, iclass 15, count 2 2006.252.08:03:49.39#ibcon#about to write, iclass 15, count 2 2006.252.08:03:49.39#ibcon#wrote, iclass 15, count 2 2006.252.08:03:49.39#ibcon#about to read 3, iclass 15, count 2 2006.252.08:03:49.42#ibcon#read 3, iclass 15, count 2 2006.252.08:03:49.42#ibcon#about to read 4, iclass 15, count 2 2006.252.08:03:49.42#ibcon#read 4, iclass 15, count 2 2006.252.08:03:49.42#ibcon#about to read 5, iclass 15, count 2 2006.252.08:03:49.42#ibcon#read 5, iclass 15, count 2 2006.252.08:03:49.42#ibcon#about to read 6, iclass 15, count 2 2006.252.08:03:49.42#ibcon#read 6, iclass 15, count 2 2006.252.08:03:49.42#ibcon#end of sib2, iclass 15, count 2 2006.252.08:03:49.42#ibcon#*after write, iclass 15, count 2 2006.252.08:03:49.42#ibcon#*before return 0, iclass 15, count 2 2006.252.08:03:49.42#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.252.08:03:49.42#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.252.08:03:49.42#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.252.08:03:49.42#ibcon#ireg 7 cls_cnt 0 2006.252.08:03:49.42#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.252.08:03:49.54#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.252.08:03:49.54#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.252.08:03:49.54#ibcon#enter wrdev, iclass 15, count 0 2006.252.08:03:49.54#ibcon#first serial, iclass 15, count 0 2006.252.08:03:49.54#ibcon#enter sib2, iclass 15, count 0 2006.252.08:03:49.54#ibcon#flushed, iclass 15, count 0 2006.252.08:03:49.54#ibcon#about to write, iclass 15, count 0 2006.252.08:03:49.54#ibcon#wrote, iclass 15, count 0 2006.252.08:03:49.54#ibcon#about to read 3, iclass 15, count 0 2006.252.08:03:49.56#ibcon#read 3, iclass 15, count 0 2006.252.08:03:49.56#ibcon#about to read 4, iclass 15, count 0 2006.252.08:03:49.56#ibcon#read 4, iclass 15, count 0 2006.252.08:03:49.56#ibcon#about to read 5, iclass 15, count 0 2006.252.08:03:49.56#ibcon#read 5, iclass 15, count 0 2006.252.08:03:49.56#ibcon#about to read 6, iclass 15, count 0 2006.252.08:03:49.56#ibcon#read 6, iclass 15, count 0 2006.252.08:03:49.56#ibcon#end of sib2, iclass 15, count 0 2006.252.08:03:49.56#ibcon#*mode == 0, iclass 15, count 0 2006.252.08:03:49.56#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.252.08:03:49.56#ibcon#[25=USB\r\n] 2006.252.08:03:49.56#ibcon#*before write, iclass 15, count 0 2006.252.08:03:49.56#ibcon#enter sib2, iclass 15, count 0 2006.252.08:03:49.56#ibcon#flushed, iclass 15, count 0 2006.252.08:03:49.56#ibcon#about to write, iclass 15, count 0 2006.252.08:03:49.56#ibcon#wrote, iclass 15, count 0 2006.252.08:03:49.56#ibcon#about to read 3, iclass 15, count 0 2006.252.08:03:49.59#ibcon#read 3, iclass 15, count 0 2006.252.08:03:49.59#ibcon#about to read 4, iclass 15, count 0 2006.252.08:03:49.59#ibcon#read 4, iclass 15, count 0 2006.252.08:03:49.59#ibcon#about to read 5, iclass 15, count 0 2006.252.08:03:49.59#ibcon#read 5, iclass 15, count 0 2006.252.08:03:49.59#ibcon#about to read 6, iclass 15, count 0 2006.252.08:03:49.59#ibcon#read 6, iclass 15, count 0 2006.252.08:03:49.59#ibcon#end of sib2, iclass 15, count 0 2006.252.08:03:49.59#ibcon#*after write, iclass 15, count 0 2006.252.08:03:49.59#ibcon#*before return 0, iclass 15, count 0 2006.252.08:03:49.59#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.252.08:03:49.59#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.252.08:03:49.59#ibcon#about to clear, iclass 15 cls_cnt 0 2006.252.08:03:49.59#ibcon#cleared, iclass 15 cls_cnt 0 2006.252.08:03:49.59$vc4f8/valo=6,772.99 2006.252.08:03:49.59#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.252.08:03:49.59#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.252.08:03:49.59#ibcon#ireg 17 cls_cnt 0 2006.252.08:03:49.59#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.252.08:03:49.59#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.252.08:03:49.59#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.252.08:03:49.59#ibcon#enter wrdev, iclass 17, count 0 2006.252.08:03:49.59#ibcon#first serial, iclass 17, count 0 2006.252.08:03:49.59#ibcon#enter sib2, iclass 17, count 0 2006.252.08:03:49.59#ibcon#flushed, iclass 17, count 0 2006.252.08:03:49.59#ibcon#about to write, iclass 17, count 0 2006.252.08:03:49.59#ibcon#wrote, iclass 17, count 0 2006.252.08:03:49.59#ibcon#about to read 3, iclass 17, count 0 2006.252.08:03:49.61#ibcon#read 3, iclass 17, count 0 2006.252.08:03:49.61#ibcon#about to read 4, iclass 17, count 0 2006.252.08:03:49.61#ibcon#read 4, iclass 17, count 0 2006.252.08:03:49.61#ibcon#about to read 5, iclass 17, count 0 2006.252.08:03:49.61#ibcon#read 5, iclass 17, count 0 2006.252.08:03:49.61#ibcon#about to read 6, iclass 17, count 0 2006.252.08:03:49.61#ibcon#read 6, iclass 17, count 0 2006.252.08:03:49.61#ibcon#end of sib2, iclass 17, count 0 2006.252.08:03:49.61#ibcon#*mode == 0, iclass 17, count 0 2006.252.08:03:49.61#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.252.08:03:49.61#ibcon#[26=FRQ=06,772.99\r\n] 2006.252.08:03:49.61#ibcon#*before write, iclass 17, count 0 2006.252.08:03:49.61#ibcon#enter sib2, iclass 17, count 0 2006.252.08:03:49.61#ibcon#flushed, iclass 17, count 0 2006.252.08:03:49.61#ibcon#about to write, iclass 17, count 0 2006.252.08:03:49.61#ibcon#wrote, iclass 17, count 0 2006.252.08:03:49.61#ibcon#about to read 3, iclass 17, count 0 2006.252.08:03:49.65#ibcon#read 3, iclass 17, count 0 2006.252.08:03:49.65#ibcon#about to read 4, iclass 17, count 0 2006.252.08:03:49.65#ibcon#read 4, iclass 17, count 0 2006.252.08:03:49.65#ibcon#about to read 5, iclass 17, count 0 2006.252.08:03:49.65#ibcon#read 5, iclass 17, count 0 2006.252.08:03:49.65#ibcon#about to read 6, iclass 17, count 0 2006.252.08:03:49.65#ibcon#read 6, iclass 17, count 0 2006.252.08:03:49.65#ibcon#end of sib2, iclass 17, count 0 2006.252.08:03:49.65#ibcon#*after write, iclass 17, count 0 2006.252.08:03:49.65#ibcon#*before return 0, iclass 17, count 0 2006.252.08:03:49.65#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.252.08:03:49.65#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.252.08:03:49.65#ibcon#about to clear, iclass 17 cls_cnt 0 2006.252.08:03:49.65#ibcon#cleared, iclass 17 cls_cnt 0 2006.252.08:03:49.65$vc4f8/va=6,7 2006.252.08:03:49.65#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.252.08:03:49.65#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.252.08:03:49.65#ibcon#ireg 11 cls_cnt 2 2006.252.08:03:49.65#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.252.08:03:49.71#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.252.08:03:49.71#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.252.08:03:49.71#ibcon#enter wrdev, iclass 19, count 2 2006.252.08:03:49.71#ibcon#first serial, iclass 19, count 2 2006.252.08:03:49.71#ibcon#enter sib2, iclass 19, count 2 2006.252.08:03:49.71#ibcon#flushed, iclass 19, count 2 2006.252.08:03:49.71#ibcon#about to write, iclass 19, count 2 2006.252.08:03:49.71#ibcon#wrote, iclass 19, count 2 2006.252.08:03:49.71#ibcon#about to read 3, iclass 19, count 2 2006.252.08:03:49.73#ibcon#read 3, iclass 19, count 2 2006.252.08:03:49.73#ibcon#about to read 4, iclass 19, count 2 2006.252.08:03:49.73#ibcon#read 4, iclass 19, count 2 2006.252.08:03:49.73#ibcon#about to read 5, iclass 19, count 2 2006.252.08:03:49.73#ibcon#read 5, iclass 19, count 2 2006.252.08:03:49.73#ibcon#about to read 6, iclass 19, count 2 2006.252.08:03:49.73#ibcon#read 6, iclass 19, count 2 2006.252.08:03:49.73#ibcon#end of sib2, iclass 19, count 2 2006.252.08:03:49.73#ibcon#*mode == 0, iclass 19, count 2 2006.252.08:03:49.73#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.252.08:03:49.73#ibcon#[25=AT06-07\r\n] 2006.252.08:03:49.73#ibcon#*before write, iclass 19, count 2 2006.252.08:03:49.73#ibcon#enter sib2, iclass 19, count 2 2006.252.08:03:49.73#ibcon#flushed, iclass 19, count 2 2006.252.08:03:49.73#ibcon#about to write, iclass 19, count 2 2006.252.08:03:49.73#ibcon#wrote, iclass 19, count 2 2006.252.08:03:49.73#ibcon#about to read 3, iclass 19, count 2 2006.252.08:03:49.76#ibcon#read 3, iclass 19, count 2 2006.252.08:03:49.76#ibcon#about to read 4, iclass 19, count 2 2006.252.08:03:49.76#ibcon#read 4, iclass 19, count 2 2006.252.08:03:49.76#ibcon#about to read 5, iclass 19, count 2 2006.252.08:03:49.76#ibcon#read 5, iclass 19, count 2 2006.252.08:03:49.76#ibcon#about to read 6, iclass 19, count 2 2006.252.08:03:49.76#ibcon#read 6, iclass 19, count 2 2006.252.08:03:49.76#ibcon#end of sib2, iclass 19, count 2 2006.252.08:03:49.76#ibcon#*after write, iclass 19, count 2 2006.252.08:03:49.76#ibcon#*before return 0, iclass 19, count 2 2006.252.08:03:49.76#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.252.08:03:49.76#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.252.08:03:49.76#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.252.08:03:49.76#ibcon#ireg 7 cls_cnt 0 2006.252.08:03:49.76#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.252.08:03:49.88#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.252.08:03:49.88#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.252.08:03:49.88#ibcon#enter wrdev, iclass 19, count 0 2006.252.08:03:49.88#ibcon#first serial, iclass 19, count 0 2006.252.08:03:49.88#ibcon#enter sib2, iclass 19, count 0 2006.252.08:03:49.88#ibcon#flushed, iclass 19, count 0 2006.252.08:03:49.88#ibcon#about to write, iclass 19, count 0 2006.252.08:03:49.88#ibcon#wrote, iclass 19, count 0 2006.252.08:03:49.88#ibcon#about to read 3, iclass 19, count 0 2006.252.08:03:49.90#ibcon#read 3, iclass 19, count 0 2006.252.08:03:49.90#ibcon#about to read 4, iclass 19, count 0 2006.252.08:03:49.90#ibcon#read 4, iclass 19, count 0 2006.252.08:03:49.90#ibcon#about to read 5, iclass 19, count 0 2006.252.08:03:49.90#ibcon#read 5, iclass 19, count 0 2006.252.08:03:49.90#ibcon#about to read 6, iclass 19, count 0 2006.252.08:03:49.90#ibcon#read 6, iclass 19, count 0 2006.252.08:03:49.90#ibcon#end of sib2, iclass 19, count 0 2006.252.08:03:49.90#ibcon#*mode == 0, iclass 19, count 0 2006.252.08:03:49.90#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.252.08:03:49.90#ibcon#[25=USB\r\n] 2006.252.08:03:49.90#ibcon#*before write, iclass 19, count 0 2006.252.08:03:49.90#ibcon#enter sib2, iclass 19, count 0 2006.252.08:03:49.90#ibcon#flushed, iclass 19, count 0 2006.252.08:03:49.90#ibcon#about to write, iclass 19, count 0 2006.252.08:03:49.90#ibcon#wrote, iclass 19, count 0 2006.252.08:03:49.90#ibcon#about to read 3, iclass 19, count 0 2006.252.08:03:49.93#ibcon#read 3, iclass 19, count 0 2006.252.08:03:49.93#ibcon#about to read 4, iclass 19, count 0 2006.252.08:03:49.93#ibcon#read 4, iclass 19, count 0 2006.252.08:03:49.93#ibcon#about to read 5, iclass 19, count 0 2006.252.08:03:49.93#ibcon#read 5, iclass 19, count 0 2006.252.08:03:49.93#ibcon#about to read 6, iclass 19, count 0 2006.252.08:03:49.93#ibcon#read 6, iclass 19, count 0 2006.252.08:03:49.93#ibcon#end of sib2, iclass 19, count 0 2006.252.08:03:49.93#ibcon#*after write, iclass 19, count 0 2006.252.08:03:49.93#ibcon#*before return 0, iclass 19, count 0 2006.252.08:03:49.93#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.252.08:03:49.93#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.252.08:03:49.93#ibcon#about to clear, iclass 19 cls_cnt 0 2006.252.08:03:49.93#ibcon#cleared, iclass 19 cls_cnt 0 2006.252.08:03:49.93$vc4f8/valo=7,832.99 2006.252.08:03:49.93#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.252.08:03:49.93#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.252.08:03:49.93#ibcon#ireg 17 cls_cnt 0 2006.252.08:03:49.93#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.252.08:03:49.93#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.252.08:03:49.93#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.252.08:03:49.93#ibcon#enter wrdev, iclass 21, count 0 2006.252.08:03:49.93#ibcon#first serial, iclass 21, count 0 2006.252.08:03:49.93#ibcon#enter sib2, iclass 21, count 0 2006.252.08:03:49.93#ibcon#flushed, iclass 21, count 0 2006.252.08:03:49.93#ibcon#about to write, iclass 21, count 0 2006.252.08:03:49.93#ibcon#wrote, iclass 21, count 0 2006.252.08:03:49.93#ibcon#about to read 3, iclass 21, count 0 2006.252.08:03:49.95#ibcon#read 3, iclass 21, count 0 2006.252.08:03:49.95#ibcon#about to read 4, iclass 21, count 0 2006.252.08:03:49.95#ibcon#read 4, iclass 21, count 0 2006.252.08:03:49.95#ibcon#about to read 5, iclass 21, count 0 2006.252.08:03:49.95#ibcon#read 5, iclass 21, count 0 2006.252.08:03:49.95#ibcon#about to read 6, iclass 21, count 0 2006.252.08:03:49.95#ibcon#read 6, iclass 21, count 0 2006.252.08:03:49.95#ibcon#end of sib2, iclass 21, count 0 2006.252.08:03:49.95#ibcon#*mode == 0, iclass 21, count 0 2006.252.08:03:49.95#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.252.08:03:49.95#ibcon#[26=FRQ=07,832.99\r\n] 2006.252.08:03:49.95#ibcon#*before write, iclass 21, count 0 2006.252.08:03:49.95#ibcon#enter sib2, iclass 21, count 0 2006.252.08:03:49.95#ibcon#flushed, iclass 21, count 0 2006.252.08:03:49.95#ibcon#about to write, iclass 21, count 0 2006.252.08:03:49.95#ibcon#wrote, iclass 21, count 0 2006.252.08:03:49.95#ibcon#about to read 3, iclass 21, count 0 2006.252.08:03:49.99#ibcon#read 3, iclass 21, count 0 2006.252.08:03:49.99#ibcon#about to read 4, iclass 21, count 0 2006.252.08:03:49.99#ibcon#read 4, iclass 21, count 0 2006.252.08:03:49.99#ibcon#about to read 5, iclass 21, count 0 2006.252.08:03:49.99#ibcon#read 5, iclass 21, count 0 2006.252.08:03:49.99#ibcon#about to read 6, iclass 21, count 0 2006.252.08:03:49.99#ibcon#read 6, iclass 21, count 0 2006.252.08:03:49.99#ibcon#end of sib2, iclass 21, count 0 2006.252.08:03:49.99#ibcon#*after write, iclass 21, count 0 2006.252.08:03:49.99#ibcon#*before return 0, iclass 21, count 0 2006.252.08:03:49.99#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.252.08:03:49.99#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.252.08:03:49.99#ibcon#about to clear, iclass 21 cls_cnt 0 2006.252.08:03:49.99#ibcon#cleared, iclass 21 cls_cnt 0 2006.252.08:03:49.99$vc4f8/va=7,7 2006.252.08:03:49.99#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.252.08:03:49.99#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.252.08:03:49.99#ibcon#ireg 11 cls_cnt 2 2006.252.08:03:49.99#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.252.08:03:50.05#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.252.08:03:50.05#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.252.08:03:50.05#ibcon#enter wrdev, iclass 23, count 2 2006.252.08:03:50.05#ibcon#first serial, iclass 23, count 2 2006.252.08:03:50.05#ibcon#enter sib2, iclass 23, count 2 2006.252.08:03:50.05#ibcon#flushed, iclass 23, count 2 2006.252.08:03:50.05#ibcon#about to write, iclass 23, count 2 2006.252.08:03:50.05#ibcon#wrote, iclass 23, count 2 2006.252.08:03:50.05#ibcon#about to read 3, iclass 23, count 2 2006.252.08:03:50.07#ibcon#read 3, iclass 23, count 2 2006.252.08:03:50.07#ibcon#about to read 4, iclass 23, count 2 2006.252.08:03:50.07#ibcon#read 4, iclass 23, count 2 2006.252.08:03:50.07#ibcon#about to read 5, iclass 23, count 2 2006.252.08:03:50.07#ibcon#read 5, iclass 23, count 2 2006.252.08:03:50.07#ibcon#about to read 6, iclass 23, count 2 2006.252.08:03:50.07#ibcon#read 6, iclass 23, count 2 2006.252.08:03:50.07#ibcon#end of sib2, iclass 23, count 2 2006.252.08:03:50.07#ibcon#*mode == 0, iclass 23, count 2 2006.252.08:03:50.07#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.252.08:03:50.07#ibcon#[25=AT07-07\r\n] 2006.252.08:03:50.07#ibcon#*before write, iclass 23, count 2 2006.252.08:03:50.07#ibcon#enter sib2, iclass 23, count 2 2006.252.08:03:50.07#ibcon#flushed, iclass 23, count 2 2006.252.08:03:50.07#ibcon#about to write, iclass 23, count 2 2006.252.08:03:50.07#ibcon#wrote, iclass 23, count 2 2006.252.08:03:50.07#ibcon#about to read 3, iclass 23, count 2 2006.252.08:03:50.10#ibcon#read 3, iclass 23, count 2 2006.252.08:03:50.10#ibcon#about to read 4, iclass 23, count 2 2006.252.08:03:50.10#ibcon#read 4, iclass 23, count 2 2006.252.08:03:50.10#ibcon#about to read 5, iclass 23, count 2 2006.252.08:03:50.10#ibcon#read 5, iclass 23, count 2 2006.252.08:03:50.10#ibcon#about to read 6, iclass 23, count 2 2006.252.08:03:50.10#ibcon#read 6, iclass 23, count 2 2006.252.08:03:50.10#ibcon#end of sib2, iclass 23, count 2 2006.252.08:03:50.10#ibcon#*after write, iclass 23, count 2 2006.252.08:03:50.10#ibcon#*before return 0, iclass 23, count 2 2006.252.08:03:50.10#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.252.08:03:50.10#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.252.08:03:50.10#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.252.08:03:50.10#ibcon#ireg 7 cls_cnt 0 2006.252.08:03:50.10#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.252.08:03:50.22#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.252.08:03:50.22#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.252.08:03:50.22#ibcon#enter wrdev, iclass 23, count 0 2006.252.08:03:50.22#ibcon#first serial, iclass 23, count 0 2006.252.08:03:50.22#ibcon#enter sib2, iclass 23, count 0 2006.252.08:03:50.22#ibcon#flushed, iclass 23, count 0 2006.252.08:03:50.22#ibcon#about to write, iclass 23, count 0 2006.252.08:03:50.22#ibcon#wrote, iclass 23, count 0 2006.252.08:03:50.22#ibcon#about to read 3, iclass 23, count 0 2006.252.08:03:50.25#ibcon#read 3, iclass 23, count 0 2006.252.08:03:50.25#ibcon#about to read 4, iclass 23, count 0 2006.252.08:03:50.25#ibcon#read 4, iclass 23, count 0 2006.252.08:03:50.25#ibcon#about to read 5, iclass 23, count 0 2006.252.08:03:50.25#ibcon#read 5, iclass 23, count 0 2006.252.08:03:50.25#ibcon#about to read 6, iclass 23, count 0 2006.252.08:03:50.25#ibcon#read 6, iclass 23, count 0 2006.252.08:03:50.25#ibcon#end of sib2, iclass 23, count 0 2006.252.08:03:50.25#ibcon#*mode == 0, iclass 23, count 0 2006.252.08:03:50.25#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.252.08:03:50.25#ibcon#[25=USB\r\n] 2006.252.08:03:50.25#ibcon#*before write, iclass 23, count 0 2006.252.08:03:50.25#ibcon#enter sib2, iclass 23, count 0 2006.252.08:03:50.25#ibcon#flushed, iclass 23, count 0 2006.252.08:03:50.25#ibcon#about to write, iclass 23, count 0 2006.252.08:03:50.25#ibcon#wrote, iclass 23, count 0 2006.252.08:03:50.25#ibcon#about to read 3, iclass 23, count 0 2006.252.08:03:50.29#ibcon#read 3, iclass 23, count 0 2006.252.08:03:50.29#ibcon#about to read 4, iclass 23, count 0 2006.252.08:03:50.29#ibcon#read 4, iclass 23, count 0 2006.252.08:03:50.29#ibcon#about to read 5, iclass 23, count 0 2006.252.08:03:50.29#ibcon#read 5, iclass 23, count 0 2006.252.08:03:50.29#ibcon#about to read 6, iclass 23, count 0 2006.252.08:03:50.29#ibcon#read 6, iclass 23, count 0 2006.252.08:03:50.29#ibcon#end of sib2, iclass 23, count 0 2006.252.08:03:50.29#ibcon#*after write, iclass 23, count 0 2006.252.08:03:50.29#ibcon#*before return 0, iclass 23, count 0 2006.252.08:03:50.29#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.252.08:03:50.29#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.252.08:03:50.29#ibcon#about to clear, iclass 23 cls_cnt 0 2006.252.08:03:50.29#ibcon#cleared, iclass 23 cls_cnt 0 2006.252.08:03:50.29$vc4f8/valo=8,852.99 2006.252.08:03:50.29#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.252.08:03:50.29#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.252.08:03:50.29#ibcon#ireg 17 cls_cnt 0 2006.252.08:03:50.29#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.252.08:03:50.29#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.252.08:03:50.29#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.252.08:03:50.29#ibcon#enter wrdev, iclass 26, count 0 2006.252.08:03:50.29#ibcon#first serial, iclass 26, count 0 2006.252.08:03:50.29#ibcon#enter sib2, iclass 26, count 0 2006.252.08:03:50.29#ibcon#flushed, iclass 26, count 0 2006.252.08:03:50.29#ibcon#about to write, iclass 26, count 0 2006.252.08:03:50.29#ibcon#wrote, iclass 26, count 0 2006.252.08:03:50.29#ibcon#about to read 3, iclass 26, count 0 2006.252.08:03:50.30#abcon#<5=/05 3.8 6.6 27.33 901011.1\r\n> 2006.252.08:03:50.31#ibcon#read 3, iclass 26, count 0 2006.252.08:03:50.31#ibcon#about to read 4, iclass 26, count 0 2006.252.08:03:50.31#ibcon#read 4, iclass 26, count 0 2006.252.08:03:50.31#ibcon#about to read 5, iclass 26, count 0 2006.252.08:03:50.31#ibcon#read 5, iclass 26, count 0 2006.252.08:03:50.31#ibcon#about to read 6, iclass 26, count 0 2006.252.08:03:50.31#ibcon#read 6, iclass 26, count 0 2006.252.08:03:50.31#ibcon#end of sib2, iclass 26, count 0 2006.252.08:03:50.31#ibcon#*mode == 0, iclass 26, count 0 2006.252.08:03:50.31#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.252.08:03:50.31#ibcon#[26=FRQ=08,852.99\r\n] 2006.252.08:03:50.31#ibcon#*before write, iclass 26, count 0 2006.252.08:03:50.31#ibcon#enter sib2, iclass 26, count 0 2006.252.08:03:50.31#ibcon#flushed, iclass 26, count 0 2006.252.08:03:50.31#ibcon#about to write, iclass 26, count 0 2006.252.08:03:50.31#ibcon#wrote, iclass 26, count 0 2006.252.08:03:50.31#ibcon#about to read 3, iclass 26, count 0 2006.252.08:03:50.32#abcon#{5=INTERFACE CLEAR} 2006.252.08:03:50.35#ibcon#read 3, iclass 26, count 0 2006.252.08:03:50.35#ibcon#about to read 4, iclass 26, count 0 2006.252.08:03:50.35#ibcon#read 4, iclass 26, count 0 2006.252.08:03:50.35#ibcon#about to read 5, iclass 26, count 0 2006.252.08:03:50.35#ibcon#read 5, iclass 26, count 0 2006.252.08:03:50.35#ibcon#about to read 6, iclass 26, count 0 2006.252.08:03:50.35#ibcon#read 6, iclass 26, count 0 2006.252.08:03:50.35#ibcon#end of sib2, iclass 26, count 0 2006.252.08:03:50.35#ibcon#*after write, iclass 26, count 0 2006.252.08:03:50.35#ibcon#*before return 0, iclass 26, count 0 2006.252.08:03:50.35#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.252.08:03:50.35#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.252.08:03:50.35#ibcon#about to clear, iclass 26 cls_cnt 0 2006.252.08:03:50.35#ibcon#cleared, iclass 26 cls_cnt 0 2006.252.08:03:50.35$vc4f8/va=8,7 2006.252.08:03:50.35#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.252.08:03:50.35#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.252.08:03:50.35#ibcon#ireg 11 cls_cnt 2 2006.252.08:03:50.35#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.252.08:03:50.38#abcon#[5=S1D000X0/0*\r\n] 2006.252.08:03:50.41#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.252.08:03:50.41#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.252.08:03:50.41#ibcon#enter wrdev, iclass 30, count 2 2006.252.08:03:50.41#ibcon#first serial, iclass 30, count 2 2006.252.08:03:50.41#ibcon#enter sib2, iclass 30, count 2 2006.252.08:03:50.41#ibcon#flushed, iclass 30, count 2 2006.252.08:03:50.41#ibcon#about to write, iclass 30, count 2 2006.252.08:03:50.41#ibcon#wrote, iclass 30, count 2 2006.252.08:03:50.41#ibcon#about to read 3, iclass 30, count 2 2006.252.08:03:50.43#ibcon#read 3, iclass 30, count 2 2006.252.08:03:50.43#ibcon#about to read 4, iclass 30, count 2 2006.252.08:03:50.43#ibcon#read 4, iclass 30, count 2 2006.252.08:03:50.43#ibcon#about to read 5, iclass 30, count 2 2006.252.08:03:50.43#ibcon#read 5, iclass 30, count 2 2006.252.08:03:50.43#ibcon#about to read 6, iclass 30, count 2 2006.252.08:03:50.43#ibcon#read 6, iclass 30, count 2 2006.252.08:03:50.43#ibcon#end of sib2, iclass 30, count 2 2006.252.08:03:50.43#ibcon#*mode == 0, iclass 30, count 2 2006.252.08:03:50.43#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.252.08:03:50.43#ibcon#[25=AT08-07\r\n] 2006.252.08:03:50.43#ibcon#*before write, iclass 30, count 2 2006.252.08:03:50.43#ibcon#enter sib2, iclass 30, count 2 2006.252.08:03:50.43#ibcon#flushed, iclass 30, count 2 2006.252.08:03:50.43#ibcon#about to write, iclass 30, count 2 2006.252.08:03:50.43#ibcon#wrote, iclass 30, count 2 2006.252.08:03:50.43#ibcon#about to read 3, iclass 30, count 2 2006.252.08:03:50.46#ibcon#read 3, iclass 30, count 2 2006.252.08:03:50.46#ibcon#about to read 4, iclass 30, count 2 2006.252.08:03:50.46#ibcon#read 4, iclass 30, count 2 2006.252.08:03:50.46#ibcon#about to read 5, iclass 30, count 2 2006.252.08:03:50.46#ibcon#read 5, iclass 30, count 2 2006.252.08:03:50.46#ibcon#about to read 6, iclass 30, count 2 2006.252.08:03:50.46#ibcon#read 6, iclass 30, count 2 2006.252.08:03:50.46#ibcon#end of sib2, iclass 30, count 2 2006.252.08:03:50.46#ibcon#*after write, iclass 30, count 2 2006.252.08:03:50.46#ibcon#*before return 0, iclass 30, count 2 2006.252.08:03:50.46#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.252.08:03:50.46#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.252.08:03:50.46#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.252.08:03:50.46#ibcon#ireg 7 cls_cnt 0 2006.252.08:03:50.46#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.252.08:03:50.58#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.252.08:03:50.58#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.252.08:03:50.58#ibcon#enter wrdev, iclass 30, count 0 2006.252.08:03:50.58#ibcon#first serial, iclass 30, count 0 2006.252.08:03:50.58#ibcon#enter sib2, iclass 30, count 0 2006.252.08:03:50.58#ibcon#flushed, iclass 30, count 0 2006.252.08:03:50.58#ibcon#about to write, iclass 30, count 0 2006.252.08:03:50.58#ibcon#wrote, iclass 30, count 0 2006.252.08:03:50.58#ibcon#about to read 3, iclass 30, count 0 2006.252.08:03:50.60#ibcon#read 3, iclass 30, count 0 2006.252.08:03:50.60#ibcon#about to read 4, iclass 30, count 0 2006.252.08:03:50.60#ibcon#read 4, iclass 30, count 0 2006.252.08:03:50.60#ibcon#about to read 5, iclass 30, count 0 2006.252.08:03:50.60#ibcon#read 5, iclass 30, count 0 2006.252.08:03:50.60#ibcon#about to read 6, iclass 30, count 0 2006.252.08:03:50.60#ibcon#read 6, iclass 30, count 0 2006.252.08:03:50.60#ibcon#end of sib2, iclass 30, count 0 2006.252.08:03:50.60#ibcon#*mode == 0, iclass 30, count 0 2006.252.08:03:50.60#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.252.08:03:50.60#ibcon#[25=USB\r\n] 2006.252.08:03:50.60#ibcon#*before write, iclass 30, count 0 2006.252.08:03:50.60#ibcon#enter sib2, iclass 30, count 0 2006.252.08:03:50.60#ibcon#flushed, iclass 30, count 0 2006.252.08:03:50.60#ibcon#about to write, iclass 30, count 0 2006.252.08:03:50.60#ibcon#wrote, iclass 30, count 0 2006.252.08:03:50.60#ibcon#about to read 3, iclass 30, count 0 2006.252.08:03:50.63#ibcon#read 3, iclass 30, count 0 2006.252.08:03:50.63#ibcon#about to read 4, iclass 30, count 0 2006.252.08:03:50.63#ibcon#read 4, iclass 30, count 0 2006.252.08:03:50.63#ibcon#about to read 5, iclass 30, count 0 2006.252.08:03:50.63#ibcon#read 5, iclass 30, count 0 2006.252.08:03:50.63#ibcon#about to read 6, iclass 30, count 0 2006.252.08:03:50.63#ibcon#read 6, iclass 30, count 0 2006.252.08:03:50.63#ibcon#end of sib2, iclass 30, count 0 2006.252.08:03:50.63#ibcon#*after write, iclass 30, count 0 2006.252.08:03:50.63#ibcon#*before return 0, iclass 30, count 0 2006.252.08:03:50.63#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.252.08:03:50.63#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.252.08:03:50.63#ibcon#about to clear, iclass 30 cls_cnt 0 2006.252.08:03:50.63#ibcon#cleared, iclass 30 cls_cnt 0 2006.252.08:03:50.63$vc4f8/vblo=1,632.99 2006.252.08:03:50.63#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.252.08:03:50.63#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.252.08:03:50.63#ibcon#ireg 17 cls_cnt 0 2006.252.08:03:50.63#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.252.08:03:50.63#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.252.08:03:50.63#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.252.08:03:50.63#ibcon#enter wrdev, iclass 33, count 0 2006.252.08:03:50.63#ibcon#first serial, iclass 33, count 0 2006.252.08:03:50.63#ibcon#enter sib2, iclass 33, count 0 2006.252.08:03:50.63#ibcon#flushed, iclass 33, count 0 2006.252.08:03:50.63#ibcon#about to write, iclass 33, count 0 2006.252.08:03:50.63#ibcon#wrote, iclass 33, count 0 2006.252.08:03:50.63#ibcon#about to read 3, iclass 33, count 0 2006.252.08:03:50.65#ibcon#read 3, iclass 33, count 0 2006.252.08:03:50.65#ibcon#about to read 4, iclass 33, count 0 2006.252.08:03:50.65#ibcon#read 4, iclass 33, count 0 2006.252.08:03:50.65#ibcon#about to read 5, iclass 33, count 0 2006.252.08:03:50.65#ibcon#read 5, iclass 33, count 0 2006.252.08:03:50.65#ibcon#about to read 6, iclass 33, count 0 2006.252.08:03:50.65#ibcon#read 6, iclass 33, count 0 2006.252.08:03:50.65#ibcon#end of sib2, iclass 33, count 0 2006.252.08:03:50.65#ibcon#*mode == 0, iclass 33, count 0 2006.252.08:03:50.65#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.252.08:03:50.65#ibcon#[28=FRQ=01,632.99\r\n] 2006.252.08:03:50.65#ibcon#*before write, iclass 33, count 0 2006.252.08:03:50.65#ibcon#enter sib2, iclass 33, count 0 2006.252.08:03:50.65#ibcon#flushed, iclass 33, count 0 2006.252.08:03:50.65#ibcon#about to write, iclass 33, count 0 2006.252.08:03:50.65#ibcon#wrote, iclass 33, count 0 2006.252.08:03:50.65#ibcon#about to read 3, iclass 33, count 0 2006.252.08:03:50.69#ibcon#read 3, iclass 33, count 0 2006.252.08:03:50.69#ibcon#about to read 4, iclass 33, count 0 2006.252.08:03:50.69#ibcon#read 4, iclass 33, count 0 2006.252.08:03:50.69#ibcon#about to read 5, iclass 33, count 0 2006.252.08:03:50.69#ibcon#read 5, iclass 33, count 0 2006.252.08:03:50.69#ibcon#about to read 6, iclass 33, count 0 2006.252.08:03:50.69#ibcon#read 6, iclass 33, count 0 2006.252.08:03:50.69#ibcon#end of sib2, iclass 33, count 0 2006.252.08:03:50.69#ibcon#*after write, iclass 33, count 0 2006.252.08:03:50.69#ibcon#*before return 0, iclass 33, count 0 2006.252.08:03:50.69#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.252.08:03:50.69#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.252.08:03:50.69#ibcon#about to clear, iclass 33 cls_cnt 0 2006.252.08:03:50.69#ibcon#cleared, iclass 33 cls_cnt 0 2006.252.08:03:50.69$vc4f8/vb=1,4 2006.252.08:03:50.69#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.252.08:03:50.69#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.252.08:03:50.69#ibcon#ireg 11 cls_cnt 2 2006.252.08:03:50.69#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.252.08:03:50.69#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.252.08:03:50.69#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.252.08:03:50.69#ibcon#enter wrdev, iclass 35, count 2 2006.252.08:03:50.69#ibcon#first serial, iclass 35, count 2 2006.252.08:03:50.69#ibcon#enter sib2, iclass 35, count 2 2006.252.08:03:50.69#ibcon#flushed, iclass 35, count 2 2006.252.08:03:50.69#ibcon#about to write, iclass 35, count 2 2006.252.08:03:50.69#ibcon#wrote, iclass 35, count 2 2006.252.08:03:50.69#ibcon#about to read 3, iclass 35, count 2 2006.252.08:03:50.71#ibcon#read 3, iclass 35, count 2 2006.252.08:03:50.71#ibcon#about to read 4, iclass 35, count 2 2006.252.08:03:50.71#ibcon#read 4, iclass 35, count 2 2006.252.08:03:50.71#ibcon#about to read 5, iclass 35, count 2 2006.252.08:03:50.71#ibcon#read 5, iclass 35, count 2 2006.252.08:03:50.71#ibcon#about to read 6, iclass 35, count 2 2006.252.08:03:50.71#ibcon#read 6, iclass 35, count 2 2006.252.08:03:50.71#ibcon#end of sib2, iclass 35, count 2 2006.252.08:03:50.71#ibcon#*mode == 0, iclass 35, count 2 2006.252.08:03:50.71#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.252.08:03:50.71#ibcon#[27=AT01-04\r\n] 2006.252.08:03:50.71#ibcon#*before write, iclass 35, count 2 2006.252.08:03:50.71#ibcon#enter sib2, iclass 35, count 2 2006.252.08:03:50.71#ibcon#flushed, iclass 35, count 2 2006.252.08:03:50.71#ibcon#about to write, iclass 35, count 2 2006.252.08:03:50.71#ibcon#wrote, iclass 35, count 2 2006.252.08:03:50.71#ibcon#about to read 3, iclass 35, count 2 2006.252.08:03:50.74#ibcon#read 3, iclass 35, count 2 2006.252.08:03:50.74#ibcon#about to read 4, iclass 35, count 2 2006.252.08:03:50.74#ibcon#read 4, iclass 35, count 2 2006.252.08:03:50.74#ibcon#about to read 5, iclass 35, count 2 2006.252.08:03:50.74#ibcon#read 5, iclass 35, count 2 2006.252.08:03:50.74#ibcon#about to read 6, iclass 35, count 2 2006.252.08:03:50.74#ibcon#read 6, iclass 35, count 2 2006.252.08:03:50.74#ibcon#end of sib2, iclass 35, count 2 2006.252.08:03:50.74#ibcon#*after write, iclass 35, count 2 2006.252.08:03:50.74#ibcon#*before return 0, iclass 35, count 2 2006.252.08:03:50.74#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.252.08:03:50.74#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.252.08:03:50.74#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.252.08:03:50.74#ibcon#ireg 7 cls_cnt 0 2006.252.08:03:50.74#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.252.08:03:50.86#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.252.08:03:50.86#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.252.08:03:50.86#ibcon#enter wrdev, iclass 35, count 0 2006.252.08:03:50.86#ibcon#first serial, iclass 35, count 0 2006.252.08:03:50.86#ibcon#enter sib2, iclass 35, count 0 2006.252.08:03:50.86#ibcon#flushed, iclass 35, count 0 2006.252.08:03:50.86#ibcon#about to write, iclass 35, count 0 2006.252.08:03:50.86#ibcon#wrote, iclass 35, count 0 2006.252.08:03:50.86#ibcon#about to read 3, iclass 35, count 0 2006.252.08:03:50.88#ibcon#read 3, iclass 35, count 0 2006.252.08:03:50.88#ibcon#about to read 4, iclass 35, count 0 2006.252.08:03:50.88#ibcon#read 4, iclass 35, count 0 2006.252.08:03:50.88#ibcon#about to read 5, iclass 35, count 0 2006.252.08:03:50.88#ibcon#read 5, iclass 35, count 0 2006.252.08:03:50.88#ibcon#about to read 6, iclass 35, count 0 2006.252.08:03:50.88#ibcon#read 6, iclass 35, count 0 2006.252.08:03:50.88#ibcon#end of sib2, iclass 35, count 0 2006.252.08:03:50.88#ibcon#*mode == 0, iclass 35, count 0 2006.252.08:03:50.88#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.252.08:03:50.88#ibcon#[27=USB\r\n] 2006.252.08:03:50.88#ibcon#*before write, iclass 35, count 0 2006.252.08:03:50.88#ibcon#enter sib2, iclass 35, count 0 2006.252.08:03:50.88#ibcon#flushed, iclass 35, count 0 2006.252.08:03:50.88#ibcon#about to write, iclass 35, count 0 2006.252.08:03:50.88#ibcon#wrote, iclass 35, count 0 2006.252.08:03:50.88#ibcon#about to read 3, iclass 35, count 0 2006.252.08:03:50.91#ibcon#read 3, iclass 35, count 0 2006.252.08:03:50.91#ibcon#about to read 4, iclass 35, count 0 2006.252.08:03:50.91#ibcon#read 4, iclass 35, count 0 2006.252.08:03:50.91#ibcon#about to read 5, iclass 35, count 0 2006.252.08:03:50.91#ibcon#read 5, iclass 35, count 0 2006.252.08:03:50.91#ibcon#about to read 6, iclass 35, count 0 2006.252.08:03:50.91#ibcon#read 6, iclass 35, count 0 2006.252.08:03:50.91#ibcon#end of sib2, iclass 35, count 0 2006.252.08:03:50.91#ibcon#*after write, iclass 35, count 0 2006.252.08:03:50.91#ibcon#*before return 0, iclass 35, count 0 2006.252.08:03:50.91#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.252.08:03:50.91#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.252.08:03:50.91#ibcon#about to clear, iclass 35 cls_cnt 0 2006.252.08:03:50.91#ibcon#cleared, iclass 35 cls_cnt 0 2006.252.08:03:50.91$vc4f8/vblo=2,640.99 2006.252.08:03:50.91#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.252.08:03:50.91#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.252.08:03:50.91#ibcon#ireg 17 cls_cnt 0 2006.252.08:03:50.91#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.252.08:03:50.91#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.252.08:03:50.91#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.252.08:03:50.91#ibcon#enter wrdev, iclass 37, count 0 2006.252.08:03:50.91#ibcon#first serial, iclass 37, count 0 2006.252.08:03:50.91#ibcon#enter sib2, iclass 37, count 0 2006.252.08:03:50.91#ibcon#flushed, iclass 37, count 0 2006.252.08:03:50.91#ibcon#about to write, iclass 37, count 0 2006.252.08:03:50.91#ibcon#wrote, iclass 37, count 0 2006.252.08:03:50.91#ibcon#about to read 3, iclass 37, count 0 2006.252.08:03:50.93#ibcon#read 3, iclass 37, count 0 2006.252.08:03:50.93#ibcon#about to read 4, iclass 37, count 0 2006.252.08:03:50.93#ibcon#read 4, iclass 37, count 0 2006.252.08:03:50.93#ibcon#about to read 5, iclass 37, count 0 2006.252.08:03:50.93#ibcon#read 5, iclass 37, count 0 2006.252.08:03:50.93#ibcon#about to read 6, iclass 37, count 0 2006.252.08:03:50.93#ibcon#read 6, iclass 37, count 0 2006.252.08:03:50.93#ibcon#end of sib2, iclass 37, count 0 2006.252.08:03:50.93#ibcon#*mode == 0, iclass 37, count 0 2006.252.08:03:50.93#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.252.08:03:50.93#ibcon#[28=FRQ=02,640.99\r\n] 2006.252.08:03:50.93#ibcon#*before write, iclass 37, count 0 2006.252.08:03:50.93#ibcon#enter sib2, iclass 37, count 0 2006.252.08:03:50.93#ibcon#flushed, iclass 37, count 0 2006.252.08:03:50.93#ibcon#about to write, iclass 37, count 0 2006.252.08:03:50.93#ibcon#wrote, iclass 37, count 0 2006.252.08:03:50.93#ibcon#about to read 3, iclass 37, count 0 2006.252.08:03:50.97#ibcon#read 3, iclass 37, count 0 2006.252.08:03:50.97#ibcon#about to read 4, iclass 37, count 0 2006.252.08:03:50.97#ibcon#read 4, iclass 37, count 0 2006.252.08:03:50.97#ibcon#about to read 5, iclass 37, count 0 2006.252.08:03:50.97#ibcon#read 5, iclass 37, count 0 2006.252.08:03:50.97#ibcon#about to read 6, iclass 37, count 0 2006.252.08:03:50.97#ibcon#read 6, iclass 37, count 0 2006.252.08:03:50.97#ibcon#end of sib2, iclass 37, count 0 2006.252.08:03:50.97#ibcon#*after write, iclass 37, count 0 2006.252.08:03:50.97#ibcon#*before return 0, iclass 37, count 0 2006.252.08:03:50.97#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.252.08:03:50.97#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.252.08:03:50.97#ibcon#about to clear, iclass 37 cls_cnt 0 2006.252.08:03:50.97#ibcon#cleared, iclass 37 cls_cnt 0 2006.252.08:03:50.97$vc4f8/vb=2,5 2006.252.08:03:50.97#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.252.08:03:50.97#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.252.08:03:50.97#ibcon#ireg 11 cls_cnt 2 2006.252.08:03:50.97#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.252.08:03:51.03#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.252.08:03:51.03#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.252.08:03:51.03#ibcon#enter wrdev, iclass 39, count 2 2006.252.08:03:51.03#ibcon#first serial, iclass 39, count 2 2006.252.08:03:51.03#ibcon#enter sib2, iclass 39, count 2 2006.252.08:03:51.03#ibcon#flushed, iclass 39, count 2 2006.252.08:03:51.03#ibcon#about to write, iclass 39, count 2 2006.252.08:03:51.03#ibcon#wrote, iclass 39, count 2 2006.252.08:03:51.03#ibcon#about to read 3, iclass 39, count 2 2006.252.08:03:51.05#ibcon#read 3, iclass 39, count 2 2006.252.08:03:51.05#ibcon#about to read 4, iclass 39, count 2 2006.252.08:03:51.05#ibcon#read 4, iclass 39, count 2 2006.252.08:03:51.05#ibcon#about to read 5, iclass 39, count 2 2006.252.08:03:51.05#ibcon#read 5, iclass 39, count 2 2006.252.08:03:51.05#ibcon#about to read 6, iclass 39, count 2 2006.252.08:03:51.05#ibcon#read 6, iclass 39, count 2 2006.252.08:03:51.05#ibcon#end of sib2, iclass 39, count 2 2006.252.08:03:51.05#ibcon#*mode == 0, iclass 39, count 2 2006.252.08:03:51.05#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.252.08:03:51.05#ibcon#[27=AT02-05\r\n] 2006.252.08:03:51.05#ibcon#*before write, iclass 39, count 2 2006.252.08:03:51.05#ibcon#enter sib2, iclass 39, count 2 2006.252.08:03:51.05#ibcon#flushed, iclass 39, count 2 2006.252.08:03:51.05#ibcon#about to write, iclass 39, count 2 2006.252.08:03:51.05#ibcon#wrote, iclass 39, count 2 2006.252.08:03:51.05#ibcon#about to read 3, iclass 39, count 2 2006.252.08:03:51.08#ibcon#read 3, iclass 39, count 2 2006.252.08:03:51.08#ibcon#about to read 4, iclass 39, count 2 2006.252.08:03:51.08#ibcon#read 4, iclass 39, count 2 2006.252.08:03:51.08#ibcon#about to read 5, iclass 39, count 2 2006.252.08:03:51.08#ibcon#read 5, iclass 39, count 2 2006.252.08:03:51.08#ibcon#about to read 6, iclass 39, count 2 2006.252.08:03:51.08#ibcon#read 6, iclass 39, count 2 2006.252.08:03:51.08#ibcon#end of sib2, iclass 39, count 2 2006.252.08:03:51.08#ibcon#*after write, iclass 39, count 2 2006.252.08:03:51.08#ibcon#*before return 0, iclass 39, count 2 2006.252.08:03:51.08#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.252.08:03:51.08#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.252.08:03:51.08#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.252.08:03:51.08#ibcon#ireg 7 cls_cnt 0 2006.252.08:03:51.08#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.252.08:03:51.20#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.252.08:03:51.20#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.252.08:03:51.20#ibcon#enter wrdev, iclass 39, count 0 2006.252.08:03:51.20#ibcon#first serial, iclass 39, count 0 2006.252.08:03:51.20#ibcon#enter sib2, iclass 39, count 0 2006.252.08:03:51.20#ibcon#flushed, iclass 39, count 0 2006.252.08:03:51.20#ibcon#about to write, iclass 39, count 0 2006.252.08:03:51.20#ibcon#wrote, iclass 39, count 0 2006.252.08:03:51.20#ibcon#about to read 3, iclass 39, count 0 2006.252.08:03:51.22#ibcon#read 3, iclass 39, count 0 2006.252.08:03:51.22#ibcon#about to read 4, iclass 39, count 0 2006.252.08:03:51.22#ibcon#read 4, iclass 39, count 0 2006.252.08:03:51.22#ibcon#about to read 5, iclass 39, count 0 2006.252.08:03:51.22#ibcon#read 5, iclass 39, count 0 2006.252.08:03:51.22#ibcon#about to read 6, iclass 39, count 0 2006.252.08:03:51.22#ibcon#read 6, iclass 39, count 0 2006.252.08:03:51.22#ibcon#end of sib2, iclass 39, count 0 2006.252.08:03:51.22#ibcon#*mode == 0, iclass 39, count 0 2006.252.08:03:51.22#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.252.08:03:51.22#ibcon#[27=USB\r\n] 2006.252.08:03:51.22#ibcon#*before write, iclass 39, count 0 2006.252.08:03:51.22#ibcon#enter sib2, iclass 39, count 0 2006.252.08:03:51.22#ibcon#flushed, iclass 39, count 0 2006.252.08:03:51.22#ibcon#about to write, iclass 39, count 0 2006.252.08:03:51.22#ibcon#wrote, iclass 39, count 0 2006.252.08:03:51.22#ibcon#about to read 3, iclass 39, count 0 2006.252.08:03:51.25#ibcon#read 3, iclass 39, count 0 2006.252.08:03:51.25#ibcon#about to read 4, iclass 39, count 0 2006.252.08:03:51.25#ibcon#read 4, iclass 39, count 0 2006.252.08:03:51.25#ibcon#about to read 5, iclass 39, count 0 2006.252.08:03:51.25#ibcon#read 5, iclass 39, count 0 2006.252.08:03:51.25#ibcon#about to read 6, iclass 39, count 0 2006.252.08:03:51.25#ibcon#read 6, iclass 39, count 0 2006.252.08:03:51.25#ibcon#end of sib2, iclass 39, count 0 2006.252.08:03:51.25#ibcon#*after write, iclass 39, count 0 2006.252.08:03:51.25#ibcon#*before return 0, iclass 39, count 0 2006.252.08:03:51.25#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.252.08:03:51.25#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.252.08:03:51.25#ibcon#about to clear, iclass 39 cls_cnt 0 2006.252.08:03:51.25#ibcon#cleared, iclass 39 cls_cnt 0 2006.252.08:03:51.25$vc4f8/vblo=3,656.99 2006.252.08:03:51.25#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.252.08:03:51.25#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.252.08:03:51.25#ibcon#ireg 17 cls_cnt 0 2006.252.08:03:51.25#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.252.08:03:51.25#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.252.08:03:51.25#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.252.08:03:51.25#ibcon#enter wrdev, iclass 3, count 0 2006.252.08:03:51.25#ibcon#first serial, iclass 3, count 0 2006.252.08:03:51.25#ibcon#enter sib2, iclass 3, count 0 2006.252.08:03:51.25#ibcon#flushed, iclass 3, count 0 2006.252.08:03:51.25#ibcon#about to write, iclass 3, count 0 2006.252.08:03:51.25#ibcon#wrote, iclass 3, count 0 2006.252.08:03:51.25#ibcon#about to read 3, iclass 3, count 0 2006.252.08:03:51.27#ibcon#read 3, iclass 3, count 0 2006.252.08:03:51.27#ibcon#about to read 4, iclass 3, count 0 2006.252.08:03:51.27#ibcon#read 4, iclass 3, count 0 2006.252.08:03:51.27#ibcon#about to read 5, iclass 3, count 0 2006.252.08:03:51.27#ibcon#read 5, iclass 3, count 0 2006.252.08:03:51.27#ibcon#about to read 6, iclass 3, count 0 2006.252.08:03:51.27#ibcon#read 6, iclass 3, count 0 2006.252.08:03:51.27#ibcon#end of sib2, iclass 3, count 0 2006.252.08:03:51.27#ibcon#*mode == 0, iclass 3, count 0 2006.252.08:03:51.27#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.252.08:03:51.27#ibcon#[28=FRQ=03,656.99\r\n] 2006.252.08:03:51.27#ibcon#*before write, iclass 3, count 0 2006.252.08:03:51.27#ibcon#enter sib2, iclass 3, count 0 2006.252.08:03:51.27#ibcon#flushed, iclass 3, count 0 2006.252.08:03:51.27#ibcon#about to write, iclass 3, count 0 2006.252.08:03:51.27#ibcon#wrote, iclass 3, count 0 2006.252.08:03:51.27#ibcon#about to read 3, iclass 3, count 0 2006.252.08:03:51.31#ibcon#read 3, iclass 3, count 0 2006.252.08:03:51.31#ibcon#about to read 4, iclass 3, count 0 2006.252.08:03:51.31#ibcon#read 4, iclass 3, count 0 2006.252.08:03:51.31#ibcon#about to read 5, iclass 3, count 0 2006.252.08:03:51.31#ibcon#read 5, iclass 3, count 0 2006.252.08:03:51.31#ibcon#about to read 6, iclass 3, count 0 2006.252.08:03:51.31#ibcon#read 6, iclass 3, count 0 2006.252.08:03:51.31#ibcon#end of sib2, iclass 3, count 0 2006.252.08:03:51.31#ibcon#*after write, iclass 3, count 0 2006.252.08:03:51.31#ibcon#*before return 0, iclass 3, count 0 2006.252.08:03:51.31#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.252.08:03:51.31#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.252.08:03:51.31#ibcon#about to clear, iclass 3 cls_cnt 0 2006.252.08:03:51.31#ibcon#cleared, iclass 3 cls_cnt 0 2006.252.08:03:51.31$vc4f8/vb=3,4 2006.252.08:03:51.31#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.252.08:03:51.31#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.252.08:03:51.31#ibcon#ireg 11 cls_cnt 2 2006.252.08:03:51.31#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.252.08:03:51.37#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.252.08:03:51.37#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.252.08:03:51.37#ibcon#enter wrdev, iclass 5, count 2 2006.252.08:03:51.37#ibcon#first serial, iclass 5, count 2 2006.252.08:03:51.37#ibcon#enter sib2, iclass 5, count 2 2006.252.08:03:51.37#ibcon#flushed, iclass 5, count 2 2006.252.08:03:51.37#ibcon#about to write, iclass 5, count 2 2006.252.08:03:51.37#ibcon#wrote, iclass 5, count 2 2006.252.08:03:51.37#ibcon#about to read 3, iclass 5, count 2 2006.252.08:03:51.39#ibcon#read 3, iclass 5, count 2 2006.252.08:03:51.39#ibcon#about to read 4, iclass 5, count 2 2006.252.08:03:51.39#ibcon#read 4, iclass 5, count 2 2006.252.08:03:51.39#ibcon#about to read 5, iclass 5, count 2 2006.252.08:03:51.39#ibcon#read 5, iclass 5, count 2 2006.252.08:03:51.39#ibcon#about to read 6, iclass 5, count 2 2006.252.08:03:51.39#ibcon#read 6, iclass 5, count 2 2006.252.08:03:51.39#ibcon#end of sib2, iclass 5, count 2 2006.252.08:03:51.39#ibcon#*mode == 0, iclass 5, count 2 2006.252.08:03:51.39#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.252.08:03:51.39#ibcon#[27=AT03-04\r\n] 2006.252.08:03:51.39#ibcon#*before write, iclass 5, count 2 2006.252.08:03:51.39#ibcon#enter sib2, iclass 5, count 2 2006.252.08:03:51.39#ibcon#flushed, iclass 5, count 2 2006.252.08:03:51.39#ibcon#about to write, iclass 5, count 2 2006.252.08:03:51.39#ibcon#wrote, iclass 5, count 2 2006.252.08:03:51.39#ibcon#about to read 3, iclass 5, count 2 2006.252.08:03:51.42#ibcon#read 3, iclass 5, count 2 2006.252.08:03:51.42#ibcon#about to read 4, iclass 5, count 2 2006.252.08:03:51.42#ibcon#read 4, iclass 5, count 2 2006.252.08:03:51.42#ibcon#about to read 5, iclass 5, count 2 2006.252.08:03:51.42#ibcon#read 5, iclass 5, count 2 2006.252.08:03:51.42#ibcon#about to read 6, iclass 5, count 2 2006.252.08:03:51.42#ibcon#read 6, iclass 5, count 2 2006.252.08:03:51.42#ibcon#end of sib2, iclass 5, count 2 2006.252.08:03:51.42#ibcon#*after write, iclass 5, count 2 2006.252.08:03:51.42#ibcon#*before return 0, iclass 5, count 2 2006.252.08:03:51.42#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.252.08:03:51.42#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.252.08:03:51.42#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.252.08:03:51.42#ibcon#ireg 7 cls_cnt 0 2006.252.08:03:51.42#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.252.08:03:51.54#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.252.08:03:51.54#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.252.08:03:51.54#ibcon#enter wrdev, iclass 5, count 0 2006.252.08:03:51.54#ibcon#first serial, iclass 5, count 0 2006.252.08:03:51.54#ibcon#enter sib2, iclass 5, count 0 2006.252.08:03:51.54#ibcon#flushed, iclass 5, count 0 2006.252.08:03:51.54#ibcon#about to write, iclass 5, count 0 2006.252.08:03:51.54#ibcon#wrote, iclass 5, count 0 2006.252.08:03:51.54#ibcon#about to read 3, iclass 5, count 0 2006.252.08:03:51.56#ibcon#read 3, iclass 5, count 0 2006.252.08:03:51.56#ibcon#about to read 4, iclass 5, count 0 2006.252.08:03:51.56#ibcon#read 4, iclass 5, count 0 2006.252.08:03:51.56#ibcon#about to read 5, iclass 5, count 0 2006.252.08:03:51.56#ibcon#read 5, iclass 5, count 0 2006.252.08:03:51.56#ibcon#about to read 6, iclass 5, count 0 2006.252.08:03:51.56#ibcon#read 6, iclass 5, count 0 2006.252.08:03:51.56#ibcon#end of sib2, iclass 5, count 0 2006.252.08:03:51.56#ibcon#*mode == 0, iclass 5, count 0 2006.252.08:03:51.56#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.252.08:03:51.56#ibcon#[27=USB\r\n] 2006.252.08:03:51.56#ibcon#*before write, iclass 5, count 0 2006.252.08:03:51.56#ibcon#enter sib2, iclass 5, count 0 2006.252.08:03:51.56#ibcon#flushed, iclass 5, count 0 2006.252.08:03:51.56#ibcon#about to write, iclass 5, count 0 2006.252.08:03:51.56#ibcon#wrote, iclass 5, count 0 2006.252.08:03:51.56#ibcon#about to read 3, iclass 5, count 0 2006.252.08:03:51.59#ibcon#read 3, iclass 5, count 0 2006.252.08:03:51.59#ibcon#about to read 4, iclass 5, count 0 2006.252.08:03:51.59#ibcon#read 4, iclass 5, count 0 2006.252.08:03:51.59#ibcon#about to read 5, iclass 5, count 0 2006.252.08:03:51.59#ibcon#read 5, iclass 5, count 0 2006.252.08:03:51.59#ibcon#about to read 6, iclass 5, count 0 2006.252.08:03:51.59#ibcon#read 6, iclass 5, count 0 2006.252.08:03:51.59#ibcon#end of sib2, iclass 5, count 0 2006.252.08:03:51.59#ibcon#*after write, iclass 5, count 0 2006.252.08:03:51.59#ibcon#*before return 0, iclass 5, count 0 2006.252.08:03:51.59#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.252.08:03:51.59#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.252.08:03:51.59#ibcon#about to clear, iclass 5 cls_cnt 0 2006.252.08:03:51.59#ibcon#cleared, iclass 5 cls_cnt 0 2006.252.08:03:51.59$vc4f8/vblo=4,712.99 2006.252.08:03:51.59#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.252.08:03:51.59#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.252.08:03:51.59#ibcon#ireg 17 cls_cnt 0 2006.252.08:03:51.59#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.252.08:03:51.59#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.252.08:03:51.59#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.252.08:03:51.59#ibcon#enter wrdev, iclass 7, count 0 2006.252.08:03:51.59#ibcon#first serial, iclass 7, count 0 2006.252.08:03:51.59#ibcon#enter sib2, iclass 7, count 0 2006.252.08:03:51.59#ibcon#flushed, iclass 7, count 0 2006.252.08:03:51.59#ibcon#about to write, iclass 7, count 0 2006.252.08:03:51.59#ibcon#wrote, iclass 7, count 0 2006.252.08:03:51.59#ibcon#about to read 3, iclass 7, count 0 2006.252.08:03:51.61#ibcon#read 3, iclass 7, count 0 2006.252.08:03:51.61#ibcon#about to read 4, iclass 7, count 0 2006.252.08:03:51.61#ibcon#read 4, iclass 7, count 0 2006.252.08:03:51.61#ibcon#about to read 5, iclass 7, count 0 2006.252.08:03:51.61#ibcon#read 5, iclass 7, count 0 2006.252.08:03:51.61#ibcon#about to read 6, iclass 7, count 0 2006.252.08:03:51.61#ibcon#read 6, iclass 7, count 0 2006.252.08:03:51.61#ibcon#end of sib2, iclass 7, count 0 2006.252.08:03:51.61#ibcon#*mode == 0, iclass 7, count 0 2006.252.08:03:51.61#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.252.08:03:51.61#ibcon#[28=FRQ=04,712.99\r\n] 2006.252.08:03:51.61#ibcon#*before write, iclass 7, count 0 2006.252.08:03:51.61#ibcon#enter sib2, iclass 7, count 0 2006.252.08:03:51.61#ibcon#flushed, iclass 7, count 0 2006.252.08:03:51.61#ibcon#about to write, iclass 7, count 0 2006.252.08:03:51.61#ibcon#wrote, iclass 7, count 0 2006.252.08:03:51.61#ibcon#about to read 3, iclass 7, count 0 2006.252.08:03:51.65#ibcon#read 3, iclass 7, count 0 2006.252.08:03:51.65#ibcon#about to read 4, iclass 7, count 0 2006.252.08:03:51.65#ibcon#read 4, iclass 7, count 0 2006.252.08:03:51.65#ibcon#about to read 5, iclass 7, count 0 2006.252.08:03:51.65#ibcon#read 5, iclass 7, count 0 2006.252.08:03:51.65#ibcon#about to read 6, iclass 7, count 0 2006.252.08:03:51.65#ibcon#read 6, iclass 7, count 0 2006.252.08:03:51.65#ibcon#end of sib2, iclass 7, count 0 2006.252.08:03:51.65#ibcon#*after write, iclass 7, count 0 2006.252.08:03:51.65#ibcon#*before return 0, iclass 7, count 0 2006.252.08:03:51.65#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.252.08:03:51.65#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.252.08:03:51.65#ibcon#about to clear, iclass 7 cls_cnt 0 2006.252.08:03:51.65#ibcon#cleared, iclass 7 cls_cnt 0 2006.252.08:03:51.65$vc4f8/vb=4,4 2006.252.08:03:51.65#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.252.08:03:51.65#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.252.08:03:51.65#ibcon#ireg 11 cls_cnt 2 2006.252.08:03:51.65#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.252.08:03:51.71#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.252.08:03:51.71#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.252.08:03:51.71#ibcon#enter wrdev, iclass 11, count 2 2006.252.08:03:51.71#ibcon#first serial, iclass 11, count 2 2006.252.08:03:51.71#ibcon#enter sib2, iclass 11, count 2 2006.252.08:03:51.71#ibcon#flushed, iclass 11, count 2 2006.252.08:03:51.71#ibcon#about to write, iclass 11, count 2 2006.252.08:03:51.71#ibcon#wrote, iclass 11, count 2 2006.252.08:03:51.71#ibcon#about to read 3, iclass 11, count 2 2006.252.08:03:51.73#ibcon#read 3, iclass 11, count 2 2006.252.08:03:51.73#ibcon#about to read 4, iclass 11, count 2 2006.252.08:03:51.73#ibcon#read 4, iclass 11, count 2 2006.252.08:03:51.73#ibcon#about to read 5, iclass 11, count 2 2006.252.08:03:51.73#ibcon#read 5, iclass 11, count 2 2006.252.08:03:51.73#ibcon#about to read 6, iclass 11, count 2 2006.252.08:03:51.73#ibcon#read 6, iclass 11, count 2 2006.252.08:03:51.73#ibcon#end of sib2, iclass 11, count 2 2006.252.08:03:51.73#ibcon#*mode == 0, iclass 11, count 2 2006.252.08:03:51.73#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.252.08:03:51.73#ibcon#[27=AT04-04\r\n] 2006.252.08:03:51.73#ibcon#*before write, iclass 11, count 2 2006.252.08:03:51.73#ibcon#enter sib2, iclass 11, count 2 2006.252.08:03:51.73#ibcon#flushed, iclass 11, count 2 2006.252.08:03:51.73#ibcon#about to write, iclass 11, count 2 2006.252.08:03:51.73#ibcon#wrote, iclass 11, count 2 2006.252.08:03:51.73#ibcon#about to read 3, iclass 11, count 2 2006.252.08:03:51.76#ibcon#read 3, iclass 11, count 2 2006.252.08:03:51.76#ibcon#about to read 4, iclass 11, count 2 2006.252.08:03:51.76#ibcon#read 4, iclass 11, count 2 2006.252.08:03:51.76#ibcon#about to read 5, iclass 11, count 2 2006.252.08:03:51.76#ibcon#read 5, iclass 11, count 2 2006.252.08:03:51.76#ibcon#about to read 6, iclass 11, count 2 2006.252.08:03:51.76#ibcon#read 6, iclass 11, count 2 2006.252.08:03:51.76#ibcon#end of sib2, iclass 11, count 2 2006.252.08:03:51.76#ibcon#*after write, iclass 11, count 2 2006.252.08:03:51.76#ibcon#*before return 0, iclass 11, count 2 2006.252.08:03:51.76#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.252.08:03:51.76#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.252.08:03:51.76#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.252.08:03:51.76#ibcon#ireg 7 cls_cnt 0 2006.252.08:03:51.76#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.252.08:03:51.88#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.252.08:03:51.88#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.252.08:03:51.88#ibcon#enter wrdev, iclass 11, count 0 2006.252.08:03:51.88#ibcon#first serial, iclass 11, count 0 2006.252.08:03:51.88#ibcon#enter sib2, iclass 11, count 0 2006.252.08:03:51.88#ibcon#flushed, iclass 11, count 0 2006.252.08:03:51.88#ibcon#about to write, iclass 11, count 0 2006.252.08:03:51.88#ibcon#wrote, iclass 11, count 0 2006.252.08:03:51.88#ibcon#about to read 3, iclass 11, count 0 2006.252.08:03:51.90#ibcon#read 3, iclass 11, count 0 2006.252.08:03:51.90#ibcon#about to read 4, iclass 11, count 0 2006.252.08:03:51.90#ibcon#read 4, iclass 11, count 0 2006.252.08:03:51.90#ibcon#about to read 5, iclass 11, count 0 2006.252.08:03:51.90#ibcon#read 5, iclass 11, count 0 2006.252.08:03:51.90#ibcon#about to read 6, iclass 11, count 0 2006.252.08:03:51.90#ibcon#read 6, iclass 11, count 0 2006.252.08:03:51.90#ibcon#end of sib2, iclass 11, count 0 2006.252.08:03:51.90#ibcon#*mode == 0, iclass 11, count 0 2006.252.08:03:51.90#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.252.08:03:51.90#ibcon#[27=USB\r\n] 2006.252.08:03:51.90#ibcon#*before write, iclass 11, count 0 2006.252.08:03:51.90#ibcon#enter sib2, iclass 11, count 0 2006.252.08:03:51.90#ibcon#flushed, iclass 11, count 0 2006.252.08:03:51.90#ibcon#about to write, iclass 11, count 0 2006.252.08:03:51.90#ibcon#wrote, iclass 11, count 0 2006.252.08:03:51.90#ibcon#about to read 3, iclass 11, count 0 2006.252.08:03:51.93#ibcon#read 3, iclass 11, count 0 2006.252.08:03:51.93#ibcon#about to read 4, iclass 11, count 0 2006.252.08:03:51.93#ibcon#read 4, iclass 11, count 0 2006.252.08:03:51.93#ibcon#about to read 5, iclass 11, count 0 2006.252.08:03:51.93#ibcon#read 5, iclass 11, count 0 2006.252.08:03:51.93#ibcon#about to read 6, iclass 11, count 0 2006.252.08:03:51.93#ibcon#read 6, iclass 11, count 0 2006.252.08:03:51.93#ibcon#end of sib2, iclass 11, count 0 2006.252.08:03:51.93#ibcon#*after write, iclass 11, count 0 2006.252.08:03:51.93#ibcon#*before return 0, iclass 11, count 0 2006.252.08:03:51.93#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.252.08:03:51.93#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.252.08:03:51.93#ibcon#about to clear, iclass 11 cls_cnt 0 2006.252.08:03:51.93#ibcon#cleared, iclass 11 cls_cnt 0 2006.252.08:03:51.93$vc4f8/vblo=5,744.99 2006.252.08:03:51.93#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.252.08:03:51.93#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.252.08:03:51.93#ibcon#ireg 17 cls_cnt 0 2006.252.08:03:51.93#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.252.08:03:51.93#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.252.08:03:51.93#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.252.08:03:51.93#ibcon#enter wrdev, iclass 13, count 0 2006.252.08:03:51.93#ibcon#first serial, iclass 13, count 0 2006.252.08:03:51.93#ibcon#enter sib2, iclass 13, count 0 2006.252.08:03:51.93#ibcon#flushed, iclass 13, count 0 2006.252.08:03:51.93#ibcon#about to write, iclass 13, count 0 2006.252.08:03:51.93#ibcon#wrote, iclass 13, count 0 2006.252.08:03:51.93#ibcon#about to read 3, iclass 13, count 0 2006.252.08:03:51.95#ibcon#read 3, iclass 13, count 0 2006.252.08:03:51.95#ibcon#about to read 4, iclass 13, count 0 2006.252.08:03:51.95#ibcon#read 4, iclass 13, count 0 2006.252.08:03:51.95#ibcon#about to read 5, iclass 13, count 0 2006.252.08:03:51.95#ibcon#read 5, iclass 13, count 0 2006.252.08:03:51.95#ibcon#about to read 6, iclass 13, count 0 2006.252.08:03:51.95#ibcon#read 6, iclass 13, count 0 2006.252.08:03:51.95#ibcon#end of sib2, iclass 13, count 0 2006.252.08:03:51.95#ibcon#*mode == 0, iclass 13, count 0 2006.252.08:03:51.95#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.252.08:03:51.95#ibcon#[28=FRQ=05,744.99\r\n] 2006.252.08:03:51.95#ibcon#*before write, iclass 13, count 0 2006.252.08:03:51.95#ibcon#enter sib2, iclass 13, count 0 2006.252.08:03:51.95#ibcon#flushed, iclass 13, count 0 2006.252.08:03:51.95#ibcon#about to write, iclass 13, count 0 2006.252.08:03:51.95#ibcon#wrote, iclass 13, count 0 2006.252.08:03:51.95#ibcon#about to read 3, iclass 13, count 0 2006.252.08:03:51.99#ibcon#read 3, iclass 13, count 0 2006.252.08:03:51.99#ibcon#about to read 4, iclass 13, count 0 2006.252.08:03:51.99#ibcon#read 4, iclass 13, count 0 2006.252.08:03:51.99#ibcon#about to read 5, iclass 13, count 0 2006.252.08:03:51.99#ibcon#read 5, iclass 13, count 0 2006.252.08:03:51.99#ibcon#about to read 6, iclass 13, count 0 2006.252.08:03:51.99#ibcon#read 6, iclass 13, count 0 2006.252.08:03:51.99#ibcon#end of sib2, iclass 13, count 0 2006.252.08:03:51.99#ibcon#*after write, iclass 13, count 0 2006.252.08:03:51.99#ibcon#*before return 0, iclass 13, count 0 2006.252.08:03:51.99#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.252.08:03:51.99#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.252.08:03:51.99#ibcon#about to clear, iclass 13 cls_cnt 0 2006.252.08:03:51.99#ibcon#cleared, iclass 13 cls_cnt 0 2006.252.08:03:51.99$vc4f8/vb=5,4 2006.252.08:03:51.99#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.252.08:03:51.99#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.252.08:03:51.99#ibcon#ireg 11 cls_cnt 2 2006.252.08:03:51.99#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.252.08:03:52.05#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.252.08:03:52.05#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.252.08:03:52.05#ibcon#enter wrdev, iclass 15, count 2 2006.252.08:03:52.05#ibcon#first serial, iclass 15, count 2 2006.252.08:03:52.05#ibcon#enter sib2, iclass 15, count 2 2006.252.08:03:52.05#ibcon#flushed, iclass 15, count 2 2006.252.08:03:52.05#ibcon#about to write, iclass 15, count 2 2006.252.08:03:52.05#ibcon#wrote, iclass 15, count 2 2006.252.08:03:52.05#ibcon#about to read 3, iclass 15, count 2 2006.252.08:03:52.07#ibcon#read 3, iclass 15, count 2 2006.252.08:03:52.07#ibcon#about to read 4, iclass 15, count 2 2006.252.08:03:52.07#ibcon#read 4, iclass 15, count 2 2006.252.08:03:52.07#ibcon#about to read 5, iclass 15, count 2 2006.252.08:03:52.07#ibcon#read 5, iclass 15, count 2 2006.252.08:03:52.07#ibcon#about to read 6, iclass 15, count 2 2006.252.08:03:52.07#ibcon#read 6, iclass 15, count 2 2006.252.08:03:52.07#ibcon#end of sib2, iclass 15, count 2 2006.252.08:03:52.07#ibcon#*mode == 0, iclass 15, count 2 2006.252.08:03:52.07#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.252.08:03:52.07#ibcon#[27=AT05-04\r\n] 2006.252.08:03:52.07#ibcon#*before write, iclass 15, count 2 2006.252.08:03:52.07#ibcon#enter sib2, iclass 15, count 2 2006.252.08:03:52.07#ibcon#flushed, iclass 15, count 2 2006.252.08:03:52.07#ibcon#about to write, iclass 15, count 2 2006.252.08:03:52.07#ibcon#wrote, iclass 15, count 2 2006.252.08:03:52.07#ibcon#about to read 3, iclass 15, count 2 2006.252.08:03:52.10#ibcon#read 3, iclass 15, count 2 2006.252.08:03:52.10#ibcon#about to read 4, iclass 15, count 2 2006.252.08:03:52.10#ibcon#read 4, iclass 15, count 2 2006.252.08:03:52.10#ibcon#about to read 5, iclass 15, count 2 2006.252.08:03:52.10#ibcon#read 5, iclass 15, count 2 2006.252.08:03:52.10#ibcon#about to read 6, iclass 15, count 2 2006.252.08:03:52.10#ibcon#read 6, iclass 15, count 2 2006.252.08:03:52.10#ibcon#end of sib2, iclass 15, count 2 2006.252.08:03:52.10#ibcon#*after write, iclass 15, count 2 2006.252.08:03:52.10#ibcon#*before return 0, iclass 15, count 2 2006.252.08:03:52.10#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.252.08:03:52.10#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.252.08:03:52.10#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.252.08:03:52.10#ibcon#ireg 7 cls_cnt 0 2006.252.08:03:52.10#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.252.08:03:52.22#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.252.08:03:52.22#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.252.08:03:52.22#ibcon#enter wrdev, iclass 15, count 0 2006.252.08:03:52.22#ibcon#first serial, iclass 15, count 0 2006.252.08:03:52.22#ibcon#enter sib2, iclass 15, count 0 2006.252.08:03:52.22#ibcon#flushed, iclass 15, count 0 2006.252.08:03:52.22#ibcon#about to write, iclass 15, count 0 2006.252.08:03:52.22#ibcon#wrote, iclass 15, count 0 2006.252.08:03:52.22#ibcon#about to read 3, iclass 15, count 0 2006.252.08:03:52.24#ibcon#read 3, iclass 15, count 0 2006.252.08:03:52.24#ibcon#about to read 4, iclass 15, count 0 2006.252.08:03:52.24#ibcon#read 4, iclass 15, count 0 2006.252.08:03:52.24#ibcon#about to read 5, iclass 15, count 0 2006.252.08:03:52.24#ibcon#read 5, iclass 15, count 0 2006.252.08:03:52.24#ibcon#about to read 6, iclass 15, count 0 2006.252.08:03:52.24#ibcon#read 6, iclass 15, count 0 2006.252.08:03:52.24#ibcon#end of sib2, iclass 15, count 0 2006.252.08:03:52.24#ibcon#*mode == 0, iclass 15, count 0 2006.252.08:03:52.24#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.252.08:03:52.24#ibcon#[27=USB\r\n] 2006.252.08:03:52.24#ibcon#*before write, iclass 15, count 0 2006.252.08:03:52.24#ibcon#enter sib2, iclass 15, count 0 2006.252.08:03:52.24#ibcon#flushed, iclass 15, count 0 2006.252.08:03:52.24#ibcon#about to write, iclass 15, count 0 2006.252.08:03:52.24#ibcon#wrote, iclass 15, count 0 2006.252.08:03:52.24#ibcon#about to read 3, iclass 15, count 0 2006.252.08:03:52.27#ibcon#read 3, iclass 15, count 0 2006.252.08:03:52.27#ibcon#about to read 4, iclass 15, count 0 2006.252.08:03:52.27#ibcon#read 4, iclass 15, count 0 2006.252.08:03:52.27#ibcon#about to read 5, iclass 15, count 0 2006.252.08:03:52.27#ibcon#read 5, iclass 15, count 0 2006.252.08:03:52.27#ibcon#about to read 6, iclass 15, count 0 2006.252.08:03:52.27#ibcon#read 6, iclass 15, count 0 2006.252.08:03:52.27#ibcon#end of sib2, iclass 15, count 0 2006.252.08:03:52.27#ibcon#*after write, iclass 15, count 0 2006.252.08:03:52.27#ibcon#*before return 0, iclass 15, count 0 2006.252.08:03:52.27#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.252.08:03:52.27#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.252.08:03:52.27#ibcon#about to clear, iclass 15 cls_cnt 0 2006.252.08:03:52.27#ibcon#cleared, iclass 15 cls_cnt 0 2006.252.08:03:52.27$vc4f8/vblo=6,752.99 2006.252.08:03:52.27#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.252.08:03:52.27#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.252.08:03:52.27#ibcon#ireg 17 cls_cnt 0 2006.252.08:03:52.27#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.252.08:03:52.27#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.252.08:03:52.27#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.252.08:03:52.27#ibcon#enter wrdev, iclass 17, count 0 2006.252.08:03:52.27#ibcon#first serial, iclass 17, count 0 2006.252.08:03:52.27#ibcon#enter sib2, iclass 17, count 0 2006.252.08:03:52.27#ibcon#flushed, iclass 17, count 0 2006.252.08:03:52.27#ibcon#about to write, iclass 17, count 0 2006.252.08:03:52.27#ibcon#wrote, iclass 17, count 0 2006.252.08:03:52.27#ibcon#about to read 3, iclass 17, count 0 2006.252.08:03:52.29#ibcon#read 3, iclass 17, count 0 2006.252.08:03:52.29#ibcon#about to read 4, iclass 17, count 0 2006.252.08:03:52.29#ibcon#read 4, iclass 17, count 0 2006.252.08:03:52.29#ibcon#about to read 5, iclass 17, count 0 2006.252.08:03:52.29#ibcon#read 5, iclass 17, count 0 2006.252.08:03:52.29#ibcon#about to read 6, iclass 17, count 0 2006.252.08:03:52.29#ibcon#read 6, iclass 17, count 0 2006.252.08:03:52.29#ibcon#end of sib2, iclass 17, count 0 2006.252.08:03:52.29#ibcon#*mode == 0, iclass 17, count 0 2006.252.08:03:52.29#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.252.08:03:52.29#ibcon#[28=FRQ=06,752.99\r\n] 2006.252.08:03:52.29#ibcon#*before write, iclass 17, count 0 2006.252.08:03:52.29#ibcon#enter sib2, iclass 17, count 0 2006.252.08:03:52.29#ibcon#flushed, iclass 17, count 0 2006.252.08:03:52.29#ibcon#about to write, iclass 17, count 0 2006.252.08:03:52.29#ibcon#wrote, iclass 17, count 0 2006.252.08:03:52.29#ibcon#about to read 3, iclass 17, count 0 2006.252.08:03:52.33#ibcon#read 3, iclass 17, count 0 2006.252.08:03:52.33#ibcon#about to read 4, iclass 17, count 0 2006.252.08:03:52.33#ibcon#read 4, iclass 17, count 0 2006.252.08:03:52.33#ibcon#about to read 5, iclass 17, count 0 2006.252.08:03:52.33#ibcon#read 5, iclass 17, count 0 2006.252.08:03:52.33#ibcon#about to read 6, iclass 17, count 0 2006.252.08:03:52.33#ibcon#read 6, iclass 17, count 0 2006.252.08:03:52.33#ibcon#end of sib2, iclass 17, count 0 2006.252.08:03:52.33#ibcon#*after write, iclass 17, count 0 2006.252.08:03:52.33#ibcon#*before return 0, iclass 17, count 0 2006.252.08:03:52.33#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.252.08:03:52.33#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.252.08:03:52.33#ibcon#about to clear, iclass 17 cls_cnt 0 2006.252.08:03:52.33#ibcon#cleared, iclass 17 cls_cnt 0 2006.252.08:03:52.33$vc4f8/vb=6,4 2006.252.08:03:52.33#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.252.08:03:52.33#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.252.08:03:52.33#ibcon#ireg 11 cls_cnt 2 2006.252.08:03:52.33#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.252.08:03:52.39#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.252.08:03:52.39#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.252.08:03:52.39#ibcon#enter wrdev, iclass 19, count 2 2006.252.08:03:52.39#ibcon#first serial, iclass 19, count 2 2006.252.08:03:52.39#ibcon#enter sib2, iclass 19, count 2 2006.252.08:03:52.39#ibcon#flushed, iclass 19, count 2 2006.252.08:03:52.39#ibcon#about to write, iclass 19, count 2 2006.252.08:03:52.39#ibcon#wrote, iclass 19, count 2 2006.252.08:03:52.39#ibcon#about to read 3, iclass 19, count 2 2006.252.08:03:52.41#ibcon#read 3, iclass 19, count 2 2006.252.08:03:52.41#ibcon#about to read 4, iclass 19, count 2 2006.252.08:03:52.41#ibcon#read 4, iclass 19, count 2 2006.252.08:03:52.41#ibcon#about to read 5, iclass 19, count 2 2006.252.08:03:52.41#ibcon#read 5, iclass 19, count 2 2006.252.08:03:52.41#ibcon#about to read 6, iclass 19, count 2 2006.252.08:03:52.41#ibcon#read 6, iclass 19, count 2 2006.252.08:03:52.41#ibcon#end of sib2, iclass 19, count 2 2006.252.08:03:52.41#ibcon#*mode == 0, iclass 19, count 2 2006.252.08:03:52.41#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.252.08:03:52.41#ibcon#[27=AT06-04\r\n] 2006.252.08:03:52.41#ibcon#*before write, iclass 19, count 2 2006.252.08:03:52.41#ibcon#enter sib2, iclass 19, count 2 2006.252.08:03:52.41#ibcon#flushed, iclass 19, count 2 2006.252.08:03:52.41#ibcon#about to write, iclass 19, count 2 2006.252.08:03:52.41#ibcon#wrote, iclass 19, count 2 2006.252.08:03:52.41#ibcon#about to read 3, iclass 19, count 2 2006.252.08:03:52.44#ibcon#read 3, iclass 19, count 2 2006.252.08:03:52.44#ibcon#about to read 4, iclass 19, count 2 2006.252.08:03:52.44#ibcon#read 4, iclass 19, count 2 2006.252.08:03:52.44#ibcon#about to read 5, iclass 19, count 2 2006.252.08:03:52.44#ibcon#read 5, iclass 19, count 2 2006.252.08:03:52.44#ibcon#about to read 6, iclass 19, count 2 2006.252.08:03:52.44#ibcon#read 6, iclass 19, count 2 2006.252.08:03:52.44#ibcon#end of sib2, iclass 19, count 2 2006.252.08:03:52.44#ibcon#*after write, iclass 19, count 2 2006.252.08:03:52.44#ibcon#*before return 0, iclass 19, count 2 2006.252.08:03:52.44#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.252.08:03:52.44#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.252.08:03:52.44#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.252.08:03:52.44#ibcon#ireg 7 cls_cnt 0 2006.252.08:03:52.44#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.252.08:03:52.56#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.252.08:03:52.56#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.252.08:03:52.56#ibcon#enter wrdev, iclass 19, count 0 2006.252.08:03:52.56#ibcon#first serial, iclass 19, count 0 2006.252.08:03:52.56#ibcon#enter sib2, iclass 19, count 0 2006.252.08:03:52.56#ibcon#flushed, iclass 19, count 0 2006.252.08:03:52.56#ibcon#about to write, iclass 19, count 0 2006.252.08:03:52.56#ibcon#wrote, iclass 19, count 0 2006.252.08:03:52.56#ibcon#about to read 3, iclass 19, count 0 2006.252.08:03:52.58#ibcon#read 3, iclass 19, count 0 2006.252.08:03:52.58#ibcon#about to read 4, iclass 19, count 0 2006.252.08:03:52.58#ibcon#read 4, iclass 19, count 0 2006.252.08:03:52.58#ibcon#about to read 5, iclass 19, count 0 2006.252.08:03:52.58#ibcon#read 5, iclass 19, count 0 2006.252.08:03:52.58#ibcon#about to read 6, iclass 19, count 0 2006.252.08:03:52.58#ibcon#read 6, iclass 19, count 0 2006.252.08:03:52.58#ibcon#end of sib2, iclass 19, count 0 2006.252.08:03:52.58#ibcon#*mode == 0, iclass 19, count 0 2006.252.08:03:52.58#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.252.08:03:52.58#ibcon#[27=USB\r\n] 2006.252.08:03:52.58#ibcon#*before write, iclass 19, count 0 2006.252.08:03:52.58#ibcon#enter sib2, iclass 19, count 0 2006.252.08:03:52.58#ibcon#flushed, iclass 19, count 0 2006.252.08:03:52.58#ibcon#about to write, iclass 19, count 0 2006.252.08:03:52.58#ibcon#wrote, iclass 19, count 0 2006.252.08:03:52.58#ibcon#about to read 3, iclass 19, count 0 2006.252.08:03:52.61#ibcon#read 3, iclass 19, count 0 2006.252.08:03:52.61#ibcon#about to read 4, iclass 19, count 0 2006.252.08:03:52.61#ibcon#read 4, iclass 19, count 0 2006.252.08:03:52.61#ibcon#about to read 5, iclass 19, count 0 2006.252.08:03:52.61#ibcon#read 5, iclass 19, count 0 2006.252.08:03:52.61#ibcon#about to read 6, iclass 19, count 0 2006.252.08:03:52.61#ibcon#read 6, iclass 19, count 0 2006.252.08:03:52.61#ibcon#end of sib2, iclass 19, count 0 2006.252.08:03:52.61#ibcon#*after write, iclass 19, count 0 2006.252.08:03:52.61#ibcon#*before return 0, iclass 19, count 0 2006.252.08:03:52.61#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.252.08:03:52.61#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.252.08:03:52.61#ibcon#about to clear, iclass 19 cls_cnt 0 2006.252.08:03:52.61#ibcon#cleared, iclass 19 cls_cnt 0 2006.252.08:03:52.61$vc4f8/vabw=wide 2006.252.08:03:52.61#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.252.08:03:52.61#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.252.08:03:52.61#ibcon#ireg 8 cls_cnt 0 2006.252.08:03:52.61#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.252.08:03:52.61#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.252.08:03:52.61#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.252.08:03:52.61#ibcon#enter wrdev, iclass 21, count 0 2006.252.08:03:52.61#ibcon#first serial, iclass 21, count 0 2006.252.08:03:52.61#ibcon#enter sib2, iclass 21, count 0 2006.252.08:03:52.61#ibcon#flushed, iclass 21, count 0 2006.252.08:03:52.61#ibcon#about to write, iclass 21, count 0 2006.252.08:03:52.61#ibcon#wrote, iclass 21, count 0 2006.252.08:03:52.61#ibcon#about to read 3, iclass 21, count 0 2006.252.08:03:52.63#ibcon#read 3, iclass 21, count 0 2006.252.08:03:52.63#ibcon#about to read 4, iclass 21, count 0 2006.252.08:03:52.63#ibcon#read 4, iclass 21, count 0 2006.252.08:03:52.63#ibcon#about to read 5, iclass 21, count 0 2006.252.08:03:52.63#ibcon#read 5, iclass 21, count 0 2006.252.08:03:52.63#ibcon#about to read 6, iclass 21, count 0 2006.252.08:03:52.63#ibcon#read 6, iclass 21, count 0 2006.252.08:03:52.63#ibcon#end of sib2, iclass 21, count 0 2006.252.08:03:52.63#ibcon#*mode == 0, iclass 21, count 0 2006.252.08:03:52.63#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.252.08:03:52.63#ibcon#[25=BW32\r\n] 2006.252.08:03:52.63#ibcon#*before write, iclass 21, count 0 2006.252.08:03:52.63#ibcon#enter sib2, iclass 21, count 0 2006.252.08:03:52.63#ibcon#flushed, iclass 21, count 0 2006.252.08:03:52.63#ibcon#about to write, iclass 21, count 0 2006.252.08:03:52.63#ibcon#wrote, iclass 21, count 0 2006.252.08:03:52.63#ibcon#about to read 3, iclass 21, count 0 2006.252.08:03:52.67#ibcon#read 3, iclass 21, count 0 2006.252.08:03:52.67#ibcon#about to read 4, iclass 21, count 0 2006.252.08:03:52.67#ibcon#read 4, iclass 21, count 0 2006.252.08:03:52.67#ibcon#about to read 5, iclass 21, count 0 2006.252.08:03:52.67#ibcon#read 5, iclass 21, count 0 2006.252.08:03:52.67#ibcon#about to read 6, iclass 21, count 0 2006.252.08:03:52.67#ibcon#read 6, iclass 21, count 0 2006.252.08:03:52.67#ibcon#end of sib2, iclass 21, count 0 2006.252.08:03:52.67#ibcon#*after write, iclass 21, count 0 2006.252.08:03:52.67#ibcon#*before return 0, iclass 21, count 0 2006.252.08:03:52.67#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.252.08:03:52.67#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.252.08:03:52.67#ibcon#about to clear, iclass 21 cls_cnt 0 2006.252.08:03:52.67#ibcon#cleared, iclass 21 cls_cnt 0 2006.252.08:03:52.67$vc4f8/vbbw=wide 2006.252.08:03:52.67#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.252.08:03:52.67#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.252.08:03:52.67#ibcon#ireg 8 cls_cnt 0 2006.252.08:03:52.67#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.252.08:03:52.73#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.252.08:03:52.73#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.252.08:03:52.73#ibcon#enter wrdev, iclass 23, count 0 2006.252.08:03:52.73#ibcon#first serial, iclass 23, count 0 2006.252.08:03:52.73#ibcon#enter sib2, iclass 23, count 0 2006.252.08:03:52.73#ibcon#flushed, iclass 23, count 0 2006.252.08:03:52.73#ibcon#about to write, iclass 23, count 0 2006.252.08:03:52.73#ibcon#wrote, iclass 23, count 0 2006.252.08:03:52.73#ibcon#about to read 3, iclass 23, count 0 2006.252.08:03:52.75#ibcon#read 3, iclass 23, count 0 2006.252.08:03:52.75#ibcon#about to read 4, iclass 23, count 0 2006.252.08:03:52.75#ibcon#read 4, iclass 23, count 0 2006.252.08:03:52.75#ibcon#about to read 5, iclass 23, count 0 2006.252.08:03:52.75#ibcon#read 5, iclass 23, count 0 2006.252.08:03:52.75#ibcon#about to read 6, iclass 23, count 0 2006.252.08:03:52.75#ibcon#read 6, iclass 23, count 0 2006.252.08:03:52.75#ibcon#end of sib2, iclass 23, count 0 2006.252.08:03:52.75#ibcon#*mode == 0, iclass 23, count 0 2006.252.08:03:52.75#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.252.08:03:52.75#ibcon#[27=BW32\r\n] 2006.252.08:03:52.75#ibcon#*before write, iclass 23, count 0 2006.252.08:03:52.75#ibcon#enter sib2, iclass 23, count 0 2006.252.08:03:52.75#ibcon#flushed, iclass 23, count 0 2006.252.08:03:52.75#ibcon#about to write, iclass 23, count 0 2006.252.08:03:52.75#ibcon#wrote, iclass 23, count 0 2006.252.08:03:52.75#ibcon#about to read 3, iclass 23, count 0 2006.252.08:03:52.78#ibcon#read 3, iclass 23, count 0 2006.252.08:03:52.78#ibcon#about to read 4, iclass 23, count 0 2006.252.08:03:52.78#ibcon#read 4, iclass 23, count 0 2006.252.08:03:52.78#ibcon#about to read 5, iclass 23, count 0 2006.252.08:03:52.78#ibcon#read 5, iclass 23, count 0 2006.252.08:03:52.78#ibcon#about to read 6, iclass 23, count 0 2006.252.08:03:52.78#ibcon#read 6, iclass 23, count 0 2006.252.08:03:52.78#ibcon#end of sib2, iclass 23, count 0 2006.252.08:03:52.78#ibcon#*after write, iclass 23, count 0 2006.252.08:03:52.78#ibcon#*before return 0, iclass 23, count 0 2006.252.08:03:52.78#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.252.08:03:52.78#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.252.08:03:52.78#ibcon#about to clear, iclass 23 cls_cnt 0 2006.252.08:03:52.78#ibcon#cleared, iclass 23 cls_cnt 0 2006.252.08:03:52.78$4f8m12a/ifd4f 2006.252.08:03:52.78$ifd4f/lo= 2006.252.08:03:52.78$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.252.08:03:52.78$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.252.08:03:52.78$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.252.08:03:52.78$ifd4f/patch= 2006.252.08:03:52.78$ifd4f/patch=lo1,a1,a2,a3,a4 2006.252.08:03:52.78$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.252.08:03:52.78$ifd4f/patch=lo3,a5,a6,a7,a8 2006.252.08:03:52.78$4f8m12a/"form=m,16.000,1:2 2006.252.08:03:52.78$4f8m12a/"tpicd 2006.252.08:03:52.78$4f8m12a/echo=off 2006.252.08:03:52.78$4f8m12a/xlog=off 2006.252.08:03:52.78:!2006.252.08:04:20 2006.252.08:04:01.14#trakl#Source acquired 2006.252.08:04:02.14#flagr#flagr/antenna,acquired 2006.252.08:04:20.00:preob 2006.252.08:04:21.14/onsource/TRACKING 2006.252.08:04:21.14:!2006.252.08:04:30 2006.252.08:04:30.00:data_valid=on 2006.252.08:04:30.00:midob 2006.252.08:04:30.14/onsource/TRACKING 2006.252.08:04:30.14/wx/27.33,1011.1,90 2006.252.08:04:30.31/cable/+6.4115E-03 2006.252.08:04:31.40/va/01,08,usb,yes,33,35 2006.252.08:04:31.40/va/02,07,usb,yes,33,35 2006.252.08:04:31.40/va/03,06,usb,yes,35,35 2006.252.08:04:31.40/va/04,07,usb,yes,34,37 2006.252.08:04:31.40/va/05,07,usb,yes,37,39 2006.252.08:04:31.40/va/06,07,usb,yes,32,32 2006.252.08:04:31.40/va/07,07,usb,yes,32,32 2006.252.08:04:31.40/va/08,07,usb,yes,35,34 2006.252.08:04:31.63/valo/01,532.99,yes,locked 2006.252.08:04:31.63/valo/02,572.99,yes,locked 2006.252.08:04:31.63/valo/03,672.99,yes,locked 2006.252.08:04:31.63/valo/04,832.99,yes,locked 2006.252.08:04:31.63/valo/05,652.99,yes,locked 2006.252.08:04:31.63/valo/06,772.99,yes,locked 2006.252.08:04:31.63/valo/07,832.99,yes,locked 2006.252.08:04:31.63/valo/08,852.99,yes,locked 2006.252.08:04:32.72/vb/01,04,usb,yes,31,29 2006.252.08:04:32.72/vb/02,05,usb,yes,29,30 2006.252.08:04:32.72/vb/03,04,usb,yes,29,33 2006.252.08:04:32.72/vb/04,04,usb,yes,30,30 2006.252.08:04:32.72/vb/05,04,usb,yes,28,32 2006.252.08:04:32.72/vb/06,04,usb,yes,29,32 2006.252.08:04:32.72/vb/07,04,usb,yes,31,31 2006.252.08:04:32.72/vb/08,04,usb,yes,29,32 2006.252.08:04:32.96/vblo/01,632.99,yes,locked 2006.252.08:04:32.96/vblo/02,640.99,yes,locked 2006.252.08:04:32.96/vblo/03,656.99,yes,locked 2006.252.08:04:32.96/vblo/04,712.99,yes,locked 2006.252.08:04:32.96/vblo/05,744.99,yes,locked 2006.252.08:04:32.96/vblo/06,752.99,yes,locked 2006.252.08:04:32.96/vblo/07,734.99,yes,locked 2006.252.08:04:32.96/vblo/08,744.99,yes,locked 2006.252.08:04:33.11/vabw/8 2006.252.08:04:33.26/vbbw/8 2006.252.08:04:33.35/xfe/off,on,14.2 2006.252.08:04:33.72/ifatt/23,28,28,28 2006.252.08:04:34.08/fmout-gps/S +4.80E-07 2006.252.08:04:34.12:!2006.252.08:05:30 2006.252.08:05:30.00:data_valid=off 2006.252.08:05:30.00:postob 2006.252.08:05:30.16/cable/+6.4097E-03 2006.252.08:05:30.16/wx/27.33,1011.1,90 2006.252.08:05:31.08/fmout-gps/S +4.78E-07 2006.252.08:05:31.08:scan_name=252-0806,k06252,60 2006.252.08:05:31.08:source=1128+385,113053.28,381518.5,2000.0,ccw 2006.252.08:05:31.16#flagr#flagr/antenna,new-source 2006.252.08:05:32.14:checkk5 2006.252.08:05:32.53/chk_autoobs//k5ts1/ autoobs is running! 2006.252.08:05:32.90/chk_autoobs//k5ts2/ autoobs is running! 2006.252.08:05:33.28/chk_autoobs//k5ts3/ autoobs is running! 2006.252.08:05:33.66/chk_autoobs//k5ts4/ autoobs is running! 2006.252.08:05:34.03/chk_obsdata//k5ts1/T2520804??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.08:05:34.39/chk_obsdata//k5ts2/T2520804??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.08:05:34.76/chk_obsdata//k5ts3/T2520804??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.08:05:35.13/chk_obsdata//k5ts4/T2520804??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.08:05:35.82/k5log//k5ts1_log_newline 2006.252.08:05:36.52/k5log//k5ts2_log_newline 2006.252.08:05:37.21/k5log//k5ts3_log_newline 2006.252.08:05:37.90/k5log//k5ts4_log_newline 2006.252.08:05:37.92/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.252.08:05:37.92:4f8m12a=2 2006.252.08:05:37.92$4f8m12a/echo=on 2006.252.08:05:37.92$4f8m12a/pcalon 2006.252.08:05:37.92$pcalon/"no phase cal control is implemented here 2006.252.08:05:37.92$4f8m12a/"tpicd=stop 2006.252.08:05:37.92$4f8m12a/vc4f8 2006.252.08:05:37.92$vc4f8/valo=1,532.99 2006.252.08:05:37.93#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.252.08:05:37.93#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.252.08:05:37.93#ibcon#ireg 17 cls_cnt 0 2006.252.08:05:37.93#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.252.08:05:37.93#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.252.08:05:37.93#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.252.08:05:37.93#ibcon#enter wrdev, iclass 30, count 0 2006.252.08:05:37.93#ibcon#first serial, iclass 30, count 0 2006.252.08:05:37.93#ibcon#enter sib2, iclass 30, count 0 2006.252.08:05:37.93#ibcon#flushed, iclass 30, count 0 2006.252.08:05:37.93#ibcon#about to write, iclass 30, count 0 2006.252.08:05:37.93#ibcon#wrote, iclass 30, count 0 2006.252.08:05:37.93#ibcon#about to read 3, iclass 30, count 0 2006.252.08:05:37.97#ibcon#read 3, iclass 30, count 0 2006.252.08:05:37.97#ibcon#about to read 4, iclass 30, count 0 2006.252.08:05:37.97#ibcon#read 4, iclass 30, count 0 2006.252.08:05:37.97#ibcon#about to read 5, iclass 30, count 0 2006.252.08:05:37.97#ibcon#read 5, iclass 30, count 0 2006.252.08:05:37.97#ibcon#about to read 6, iclass 30, count 0 2006.252.08:05:37.97#ibcon#read 6, iclass 30, count 0 2006.252.08:05:37.97#ibcon#end of sib2, iclass 30, count 0 2006.252.08:05:37.97#ibcon#*mode == 0, iclass 30, count 0 2006.252.08:05:37.97#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.252.08:05:37.97#ibcon#[26=FRQ=01,532.99\r\n] 2006.252.08:05:37.97#ibcon#*before write, iclass 30, count 0 2006.252.08:05:37.97#ibcon#enter sib2, iclass 30, count 0 2006.252.08:05:37.97#ibcon#flushed, iclass 30, count 0 2006.252.08:05:37.97#ibcon#about to write, iclass 30, count 0 2006.252.08:05:37.97#ibcon#wrote, iclass 30, count 0 2006.252.08:05:37.97#ibcon#about to read 3, iclass 30, count 0 2006.252.08:05:38.02#ibcon#read 3, iclass 30, count 0 2006.252.08:05:38.02#ibcon#about to read 4, iclass 30, count 0 2006.252.08:05:38.02#ibcon#read 4, iclass 30, count 0 2006.252.08:05:38.02#ibcon#about to read 5, iclass 30, count 0 2006.252.08:05:38.02#ibcon#read 5, iclass 30, count 0 2006.252.08:05:38.02#ibcon#about to read 6, iclass 30, count 0 2006.252.08:05:38.02#ibcon#read 6, iclass 30, count 0 2006.252.08:05:38.02#ibcon#end of sib2, iclass 30, count 0 2006.252.08:05:38.02#ibcon#*after write, iclass 30, count 0 2006.252.08:05:38.02#ibcon#*before return 0, iclass 30, count 0 2006.252.08:05:38.02#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.252.08:05:38.02#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.252.08:05:38.02#ibcon#about to clear, iclass 30 cls_cnt 0 2006.252.08:05:38.02#ibcon#cleared, iclass 30 cls_cnt 0 2006.252.08:05:38.02$vc4f8/va=1,8 2006.252.08:05:38.02#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.252.08:05:38.02#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.252.08:05:38.02#ibcon#ireg 11 cls_cnt 2 2006.252.08:05:38.02#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.252.08:05:38.02#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.252.08:05:38.02#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.252.08:05:38.02#ibcon#enter wrdev, iclass 32, count 2 2006.252.08:05:38.02#ibcon#first serial, iclass 32, count 2 2006.252.08:05:38.02#ibcon#enter sib2, iclass 32, count 2 2006.252.08:05:38.02#ibcon#flushed, iclass 32, count 2 2006.252.08:05:38.02#ibcon#about to write, iclass 32, count 2 2006.252.08:05:38.02#ibcon#wrote, iclass 32, count 2 2006.252.08:05:38.02#ibcon#about to read 3, iclass 32, count 2 2006.252.08:05:38.04#ibcon#read 3, iclass 32, count 2 2006.252.08:05:38.04#ibcon#about to read 4, iclass 32, count 2 2006.252.08:05:38.04#ibcon#read 4, iclass 32, count 2 2006.252.08:05:38.04#ibcon#about to read 5, iclass 32, count 2 2006.252.08:05:38.04#ibcon#read 5, iclass 32, count 2 2006.252.08:05:38.04#ibcon#about to read 6, iclass 32, count 2 2006.252.08:05:38.04#ibcon#read 6, iclass 32, count 2 2006.252.08:05:38.04#ibcon#end of sib2, iclass 32, count 2 2006.252.08:05:38.04#ibcon#*mode == 0, iclass 32, count 2 2006.252.08:05:38.04#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.252.08:05:38.04#ibcon#[25=AT01-08\r\n] 2006.252.08:05:38.04#ibcon#*before write, iclass 32, count 2 2006.252.08:05:38.04#ibcon#enter sib2, iclass 32, count 2 2006.252.08:05:38.04#ibcon#flushed, iclass 32, count 2 2006.252.08:05:38.04#ibcon#about to write, iclass 32, count 2 2006.252.08:05:38.04#ibcon#wrote, iclass 32, count 2 2006.252.08:05:38.04#ibcon#about to read 3, iclass 32, count 2 2006.252.08:05:38.07#ibcon#read 3, iclass 32, count 2 2006.252.08:05:38.07#ibcon#about to read 4, iclass 32, count 2 2006.252.08:05:38.07#ibcon#read 4, iclass 32, count 2 2006.252.08:05:38.07#ibcon#about to read 5, iclass 32, count 2 2006.252.08:05:38.07#ibcon#read 5, iclass 32, count 2 2006.252.08:05:38.07#ibcon#about to read 6, iclass 32, count 2 2006.252.08:05:38.07#ibcon#read 6, iclass 32, count 2 2006.252.08:05:38.07#ibcon#end of sib2, iclass 32, count 2 2006.252.08:05:38.07#ibcon#*after write, iclass 32, count 2 2006.252.08:05:38.07#ibcon#*before return 0, iclass 32, count 2 2006.252.08:05:38.07#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.252.08:05:38.07#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.252.08:05:38.07#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.252.08:05:38.07#ibcon#ireg 7 cls_cnt 0 2006.252.08:05:38.07#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.252.08:05:38.19#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.252.08:05:38.19#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.252.08:05:38.19#ibcon#enter wrdev, iclass 32, count 0 2006.252.08:05:38.19#ibcon#first serial, iclass 32, count 0 2006.252.08:05:38.19#ibcon#enter sib2, iclass 32, count 0 2006.252.08:05:38.19#ibcon#flushed, iclass 32, count 0 2006.252.08:05:38.19#ibcon#about to write, iclass 32, count 0 2006.252.08:05:38.19#ibcon#wrote, iclass 32, count 0 2006.252.08:05:38.19#ibcon#about to read 3, iclass 32, count 0 2006.252.08:05:38.21#ibcon#read 3, iclass 32, count 0 2006.252.08:05:38.21#ibcon#about to read 4, iclass 32, count 0 2006.252.08:05:38.21#ibcon#read 4, iclass 32, count 0 2006.252.08:05:38.21#ibcon#about to read 5, iclass 32, count 0 2006.252.08:05:38.21#ibcon#read 5, iclass 32, count 0 2006.252.08:05:38.21#ibcon#about to read 6, iclass 32, count 0 2006.252.08:05:38.21#ibcon#read 6, iclass 32, count 0 2006.252.08:05:38.21#ibcon#end of sib2, iclass 32, count 0 2006.252.08:05:38.21#ibcon#*mode == 0, iclass 32, count 0 2006.252.08:05:38.21#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.252.08:05:38.21#ibcon#[25=USB\r\n] 2006.252.08:05:38.21#ibcon#*before write, iclass 32, count 0 2006.252.08:05:38.21#ibcon#enter sib2, iclass 32, count 0 2006.252.08:05:38.21#ibcon#flushed, iclass 32, count 0 2006.252.08:05:38.21#ibcon#about to write, iclass 32, count 0 2006.252.08:05:38.21#ibcon#wrote, iclass 32, count 0 2006.252.08:05:38.21#ibcon#about to read 3, iclass 32, count 0 2006.252.08:05:38.24#ibcon#read 3, iclass 32, count 0 2006.252.08:05:38.24#ibcon#about to read 4, iclass 32, count 0 2006.252.08:05:38.24#ibcon#read 4, iclass 32, count 0 2006.252.08:05:38.24#ibcon#about to read 5, iclass 32, count 0 2006.252.08:05:38.24#ibcon#read 5, iclass 32, count 0 2006.252.08:05:38.24#ibcon#about to read 6, iclass 32, count 0 2006.252.08:05:38.24#ibcon#read 6, iclass 32, count 0 2006.252.08:05:38.24#ibcon#end of sib2, iclass 32, count 0 2006.252.08:05:38.24#ibcon#*after write, iclass 32, count 0 2006.252.08:05:38.24#ibcon#*before return 0, iclass 32, count 0 2006.252.08:05:38.24#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.252.08:05:38.24#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.252.08:05:38.24#ibcon#about to clear, iclass 32 cls_cnt 0 2006.252.08:05:38.24#ibcon#cleared, iclass 32 cls_cnt 0 2006.252.08:05:38.24$vc4f8/valo=2,572.99 2006.252.08:05:38.24#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.252.08:05:38.24#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.252.08:05:38.24#ibcon#ireg 17 cls_cnt 0 2006.252.08:05:38.24#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.252.08:05:38.24#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.252.08:05:38.24#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.252.08:05:38.24#ibcon#enter wrdev, iclass 34, count 0 2006.252.08:05:38.24#ibcon#first serial, iclass 34, count 0 2006.252.08:05:38.24#ibcon#enter sib2, iclass 34, count 0 2006.252.08:05:38.24#ibcon#flushed, iclass 34, count 0 2006.252.08:05:38.24#ibcon#about to write, iclass 34, count 0 2006.252.08:05:38.24#ibcon#wrote, iclass 34, count 0 2006.252.08:05:38.24#ibcon#about to read 3, iclass 34, count 0 2006.252.08:05:38.26#ibcon#read 3, iclass 34, count 0 2006.252.08:05:38.26#ibcon#about to read 4, iclass 34, count 0 2006.252.08:05:38.26#ibcon#read 4, iclass 34, count 0 2006.252.08:05:38.26#ibcon#about to read 5, iclass 34, count 0 2006.252.08:05:38.26#ibcon#read 5, iclass 34, count 0 2006.252.08:05:38.26#ibcon#about to read 6, iclass 34, count 0 2006.252.08:05:38.26#ibcon#read 6, iclass 34, count 0 2006.252.08:05:38.26#ibcon#end of sib2, iclass 34, count 0 2006.252.08:05:38.26#ibcon#*mode == 0, iclass 34, count 0 2006.252.08:05:38.26#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.252.08:05:38.26#ibcon#[26=FRQ=02,572.99\r\n] 2006.252.08:05:38.26#ibcon#*before write, iclass 34, count 0 2006.252.08:05:38.26#ibcon#enter sib2, iclass 34, count 0 2006.252.08:05:38.26#ibcon#flushed, iclass 34, count 0 2006.252.08:05:38.26#ibcon#about to write, iclass 34, count 0 2006.252.08:05:38.26#ibcon#wrote, iclass 34, count 0 2006.252.08:05:38.26#ibcon#about to read 3, iclass 34, count 0 2006.252.08:05:38.30#ibcon#read 3, iclass 34, count 0 2006.252.08:05:38.30#ibcon#about to read 4, iclass 34, count 0 2006.252.08:05:38.30#ibcon#read 4, iclass 34, count 0 2006.252.08:05:38.30#ibcon#about to read 5, iclass 34, count 0 2006.252.08:05:38.30#ibcon#read 5, iclass 34, count 0 2006.252.08:05:38.30#ibcon#about to read 6, iclass 34, count 0 2006.252.08:05:38.30#ibcon#read 6, iclass 34, count 0 2006.252.08:05:38.30#ibcon#end of sib2, iclass 34, count 0 2006.252.08:05:38.30#ibcon#*after write, iclass 34, count 0 2006.252.08:05:38.30#ibcon#*before return 0, iclass 34, count 0 2006.252.08:05:38.30#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.252.08:05:38.30#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.252.08:05:38.30#ibcon#about to clear, iclass 34 cls_cnt 0 2006.252.08:05:38.30#ibcon#cleared, iclass 34 cls_cnt 0 2006.252.08:05:38.30$vc4f8/va=2,7 2006.252.08:05:38.30#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.252.08:05:38.30#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.252.08:05:38.30#ibcon#ireg 11 cls_cnt 2 2006.252.08:05:38.30#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.252.08:05:38.36#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.252.08:05:38.36#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.252.08:05:38.36#ibcon#enter wrdev, iclass 36, count 2 2006.252.08:05:38.36#ibcon#first serial, iclass 36, count 2 2006.252.08:05:38.36#ibcon#enter sib2, iclass 36, count 2 2006.252.08:05:38.36#ibcon#flushed, iclass 36, count 2 2006.252.08:05:38.36#ibcon#about to write, iclass 36, count 2 2006.252.08:05:38.36#ibcon#wrote, iclass 36, count 2 2006.252.08:05:38.36#ibcon#about to read 3, iclass 36, count 2 2006.252.08:05:38.38#ibcon#read 3, iclass 36, count 2 2006.252.08:05:38.38#ibcon#about to read 4, iclass 36, count 2 2006.252.08:05:38.38#ibcon#read 4, iclass 36, count 2 2006.252.08:05:38.38#ibcon#about to read 5, iclass 36, count 2 2006.252.08:05:38.38#ibcon#read 5, iclass 36, count 2 2006.252.08:05:38.38#ibcon#about to read 6, iclass 36, count 2 2006.252.08:05:38.38#ibcon#read 6, iclass 36, count 2 2006.252.08:05:38.38#ibcon#end of sib2, iclass 36, count 2 2006.252.08:05:38.38#ibcon#*mode == 0, iclass 36, count 2 2006.252.08:05:38.38#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.252.08:05:38.38#ibcon#[25=AT02-07\r\n] 2006.252.08:05:38.38#ibcon#*before write, iclass 36, count 2 2006.252.08:05:38.38#ibcon#enter sib2, iclass 36, count 2 2006.252.08:05:38.38#ibcon#flushed, iclass 36, count 2 2006.252.08:05:38.38#ibcon#about to write, iclass 36, count 2 2006.252.08:05:38.38#ibcon#wrote, iclass 36, count 2 2006.252.08:05:38.38#ibcon#about to read 3, iclass 36, count 2 2006.252.08:05:38.41#ibcon#read 3, iclass 36, count 2 2006.252.08:05:38.41#ibcon#about to read 4, iclass 36, count 2 2006.252.08:05:38.41#ibcon#read 4, iclass 36, count 2 2006.252.08:05:38.41#ibcon#about to read 5, iclass 36, count 2 2006.252.08:05:38.41#ibcon#read 5, iclass 36, count 2 2006.252.08:05:38.41#ibcon#about to read 6, iclass 36, count 2 2006.252.08:05:38.41#ibcon#read 6, iclass 36, count 2 2006.252.08:05:38.41#ibcon#end of sib2, iclass 36, count 2 2006.252.08:05:38.41#ibcon#*after write, iclass 36, count 2 2006.252.08:05:38.41#ibcon#*before return 0, iclass 36, count 2 2006.252.08:05:38.41#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.252.08:05:38.41#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.252.08:05:38.41#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.252.08:05:38.41#ibcon#ireg 7 cls_cnt 0 2006.252.08:05:38.41#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.252.08:05:38.53#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.252.08:05:38.53#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.252.08:05:38.53#ibcon#enter wrdev, iclass 36, count 0 2006.252.08:05:38.53#ibcon#first serial, iclass 36, count 0 2006.252.08:05:38.53#ibcon#enter sib2, iclass 36, count 0 2006.252.08:05:38.53#ibcon#flushed, iclass 36, count 0 2006.252.08:05:38.53#ibcon#about to write, iclass 36, count 0 2006.252.08:05:38.53#ibcon#wrote, iclass 36, count 0 2006.252.08:05:38.53#ibcon#about to read 3, iclass 36, count 0 2006.252.08:05:38.55#ibcon#read 3, iclass 36, count 0 2006.252.08:05:38.55#ibcon#about to read 4, iclass 36, count 0 2006.252.08:05:38.55#ibcon#read 4, iclass 36, count 0 2006.252.08:05:38.55#ibcon#about to read 5, iclass 36, count 0 2006.252.08:05:38.55#ibcon#read 5, iclass 36, count 0 2006.252.08:05:38.55#ibcon#about to read 6, iclass 36, count 0 2006.252.08:05:38.55#ibcon#read 6, iclass 36, count 0 2006.252.08:05:38.55#ibcon#end of sib2, iclass 36, count 0 2006.252.08:05:38.55#ibcon#*mode == 0, iclass 36, count 0 2006.252.08:05:38.55#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.252.08:05:38.55#ibcon#[25=USB\r\n] 2006.252.08:05:38.55#ibcon#*before write, iclass 36, count 0 2006.252.08:05:38.55#ibcon#enter sib2, iclass 36, count 0 2006.252.08:05:38.55#ibcon#flushed, iclass 36, count 0 2006.252.08:05:38.55#ibcon#about to write, iclass 36, count 0 2006.252.08:05:38.55#ibcon#wrote, iclass 36, count 0 2006.252.08:05:38.55#ibcon#about to read 3, iclass 36, count 0 2006.252.08:05:38.58#ibcon#read 3, iclass 36, count 0 2006.252.08:05:38.58#ibcon#about to read 4, iclass 36, count 0 2006.252.08:05:38.58#ibcon#read 4, iclass 36, count 0 2006.252.08:05:38.58#ibcon#about to read 5, iclass 36, count 0 2006.252.08:05:38.58#ibcon#read 5, iclass 36, count 0 2006.252.08:05:38.58#ibcon#about to read 6, iclass 36, count 0 2006.252.08:05:38.58#ibcon#read 6, iclass 36, count 0 2006.252.08:05:38.58#ibcon#end of sib2, iclass 36, count 0 2006.252.08:05:38.58#ibcon#*after write, iclass 36, count 0 2006.252.08:05:38.58#ibcon#*before return 0, iclass 36, count 0 2006.252.08:05:38.58#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.252.08:05:38.58#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.252.08:05:38.58#ibcon#about to clear, iclass 36 cls_cnt 0 2006.252.08:05:38.58#ibcon#cleared, iclass 36 cls_cnt 0 2006.252.08:05:38.58$vc4f8/valo=3,672.99 2006.252.08:05:38.58#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.252.08:05:38.58#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.252.08:05:38.58#ibcon#ireg 17 cls_cnt 0 2006.252.08:05:38.58#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.252.08:05:38.58#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.252.08:05:38.58#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.252.08:05:38.58#ibcon#enter wrdev, iclass 38, count 0 2006.252.08:05:38.58#ibcon#first serial, iclass 38, count 0 2006.252.08:05:38.58#ibcon#enter sib2, iclass 38, count 0 2006.252.08:05:38.58#ibcon#flushed, iclass 38, count 0 2006.252.08:05:38.58#ibcon#about to write, iclass 38, count 0 2006.252.08:05:38.58#ibcon#wrote, iclass 38, count 0 2006.252.08:05:38.58#ibcon#about to read 3, iclass 38, count 0 2006.252.08:05:38.60#ibcon#read 3, iclass 38, count 0 2006.252.08:05:38.60#ibcon#about to read 4, iclass 38, count 0 2006.252.08:05:38.60#ibcon#read 4, iclass 38, count 0 2006.252.08:05:38.60#ibcon#about to read 5, iclass 38, count 0 2006.252.08:05:38.60#ibcon#read 5, iclass 38, count 0 2006.252.08:05:38.60#ibcon#about to read 6, iclass 38, count 0 2006.252.08:05:38.60#ibcon#read 6, iclass 38, count 0 2006.252.08:05:38.60#ibcon#end of sib2, iclass 38, count 0 2006.252.08:05:38.60#ibcon#*mode == 0, iclass 38, count 0 2006.252.08:05:38.60#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.252.08:05:38.60#ibcon#[26=FRQ=03,672.99\r\n] 2006.252.08:05:38.60#ibcon#*before write, iclass 38, count 0 2006.252.08:05:38.60#ibcon#enter sib2, iclass 38, count 0 2006.252.08:05:38.60#ibcon#flushed, iclass 38, count 0 2006.252.08:05:38.60#ibcon#about to write, iclass 38, count 0 2006.252.08:05:38.60#ibcon#wrote, iclass 38, count 0 2006.252.08:05:38.60#ibcon#about to read 3, iclass 38, count 0 2006.252.08:05:38.65#ibcon#read 3, iclass 38, count 0 2006.252.08:05:38.65#ibcon#about to read 4, iclass 38, count 0 2006.252.08:05:38.65#ibcon#read 4, iclass 38, count 0 2006.252.08:05:38.65#ibcon#about to read 5, iclass 38, count 0 2006.252.08:05:38.65#ibcon#read 5, iclass 38, count 0 2006.252.08:05:38.65#ibcon#about to read 6, iclass 38, count 0 2006.252.08:05:38.65#ibcon#read 6, iclass 38, count 0 2006.252.08:05:38.65#ibcon#end of sib2, iclass 38, count 0 2006.252.08:05:38.65#ibcon#*after write, iclass 38, count 0 2006.252.08:05:38.65#ibcon#*before return 0, iclass 38, count 0 2006.252.08:05:38.65#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.252.08:05:38.65#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.252.08:05:38.65#ibcon#about to clear, iclass 38 cls_cnt 0 2006.252.08:05:38.65#ibcon#cleared, iclass 38 cls_cnt 0 2006.252.08:05:38.65$vc4f8/va=3,6 2006.252.08:05:38.65#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.252.08:05:38.65#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.252.08:05:38.65#ibcon#ireg 11 cls_cnt 2 2006.252.08:05:38.65#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.252.08:05:38.70#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.252.08:05:38.70#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.252.08:05:38.70#ibcon#enter wrdev, iclass 40, count 2 2006.252.08:05:38.70#ibcon#first serial, iclass 40, count 2 2006.252.08:05:38.70#ibcon#enter sib2, iclass 40, count 2 2006.252.08:05:38.70#ibcon#flushed, iclass 40, count 2 2006.252.08:05:38.70#ibcon#about to write, iclass 40, count 2 2006.252.08:05:38.70#ibcon#wrote, iclass 40, count 2 2006.252.08:05:38.70#ibcon#about to read 3, iclass 40, count 2 2006.252.08:05:38.72#ibcon#read 3, iclass 40, count 2 2006.252.08:05:38.72#ibcon#about to read 4, iclass 40, count 2 2006.252.08:05:38.72#ibcon#read 4, iclass 40, count 2 2006.252.08:05:38.72#ibcon#about to read 5, iclass 40, count 2 2006.252.08:05:38.72#ibcon#read 5, iclass 40, count 2 2006.252.08:05:38.72#ibcon#about to read 6, iclass 40, count 2 2006.252.08:05:38.72#ibcon#read 6, iclass 40, count 2 2006.252.08:05:38.72#ibcon#end of sib2, iclass 40, count 2 2006.252.08:05:38.72#ibcon#*mode == 0, iclass 40, count 2 2006.252.08:05:38.72#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.252.08:05:38.72#ibcon#[25=AT03-06\r\n] 2006.252.08:05:38.72#ibcon#*before write, iclass 40, count 2 2006.252.08:05:38.72#ibcon#enter sib2, iclass 40, count 2 2006.252.08:05:38.72#ibcon#flushed, iclass 40, count 2 2006.252.08:05:38.72#ibcon#about to write, iclass 40, count 2 2006.252.08:05:38.72#ibcon#wrote, iclass 40, count 2 2006.252.08:05:38.72#ibcon#about to read 3, iclass 40, count 2 2006.252.08:05:38.75#ibcon#read 3, iclass 40, count 2 2006.252.08:05:38.75#ibcon#about to read 4, iclass 40, count 2 2006.252.08:05:38.75#ibcon#read 4, iclass 40, count 2 2006.252.08:05:38.75#ibcon#about to read 5, iclass 40, count 2 2006.252.08:05:38.75#ibcon#read 5, iclass 40, count 2 2006.252.08:05:38.75#ibcon#about to read 6, iclass 40, count 2 2006.252.08:05:38.75#ibcon#read 6, iclass 40, count 2 2006.252.08:05:38.75#ibcon#end of sib2, iclass 40, count 2 2006.252.08:05:38.75#ibcon#*after write, iclass 40, count 2 2006.252.08:05:38.75#ibcon#*before return 0, iclass 40, count 2 2006.252.08:05:38.75#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.252.08:05:38.75#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.252.08:05:38.75#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.252.08:05:38.75#ibcon#ireg 7 cls_cnt 0 2006.252.08:05:38.75#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.252.08:05:38.87#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.252.08:05:38.87#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.252.08:05:38.87#ibcon#enter wrdev, iclass 40, count 0 2006.252.08:05:38.87#ibcon#first serial, iclass 40, count 0 2006.252.08:05:38.87#ibcon#enter sib2, iclass 40, count 0 2006.252.08:05:38.87#ibcon#flushed, iclass 40, count 0 2006.252.08:05:38.87#ibcon#about to write, iclass 40, count 0 2006.252.08:05:38.87#ibcon#wrote, iclass 40, count 0 2006.252.08:05:38.87#ibcon#about to read 3, iclass 40, count 0 2006.252.08:05:38.89#ibcon#read 3, iclass 40, count 0 2006.252.08:05:38.89#ibcon#about to read 4, iclass 40, count 0 2006.252.08:05:38.89#ibcon#read 4, iclass 40, count 0 2006.252.08:05:38.89#ibcon#about to read 5, iclass 40, count 0 2006.252.08:05:38.89#ibcon#read 5, iclass 40, count 0 2006.252.08:05:38.89#ibcon#about to read 6, iclass 40, count 0 2006.252.08:05:38.89#ibcon#read 6, iclass 40, count 0 2006.252.08:05:38.89#ibcon#end of sib2, iclass 40, count 0 2006.252.08:05:38.89#ibcon#*mode == 0, iclass 40, count 0 2006.252.08:05:38.89#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.252.08:05:38.89#ibcon#[25=USB\r\n] 2006.252.08:05:38.89#ibcon#*before write, iclass 40, count 0 2006.252.08:05:38.89#ibcon#enter sib2, iclass 40, count 0 2006.252.08:05:38.89#ibcon#flushed, iclass 40, count 0 2006.252.08:05:38.89#ibcon#about to write, iclass 40, count 0 2006.252.08:05:38.89#ibcon#wrote, iclass 40, count 0 2006.252.08:05:38.89#ibcon#about to read 3, iclass 40, count 0 2006.252.08:05:38.92#ibcon#read 3, iclass 40, count 0 2006.252.08:05:38.92#ibcon#about to read 4, iclass 40, count 0 2006.252.08:05:38.92#ibcon#read 4, iclass 40, count 0 2006.252.08:05:38.92#ibcon#about to read 5, iclass 40, count 0 2006.252.08:05:38.92#ibcon#read 5, iclass 40, count 0 2006.252.08:05:38.92#ibcon#about to read 6, iclass 40, count 0 2006.252.08:05:38.92#ibcon#read 6, iclass 40, count 0 2006.252.08:05:38.92#ibcon#end of sib2, iclass 40, count 0 2006.252.08:05:38.92#ibcon#*after write, iclass 40, count 0 2006.252.08:05:38.92#ibcon#*before return 0, iclass 40, count 0 2006.252.08:05:38.92#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.252.08:05:38.92#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.252.08:05:38.92#ibcon#about to clear, iclass 40 cls_cnt 0 2006.252.08:05:38.92#ibcon#cleared, iclass 40 cls_cnt 0 2006.252.08:05:38.92$vc4f8/valo=4,832.99 2006.252.08:05:38.92#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.252.08:05:38.92#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.252.08:05:38.92#ibcon#ireg 17 cls_cnt 0 2006.252.08:05:38.92#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.252.08:05:38.92#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.252.08:05:38.92#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.252.08:05:38.92#ibcon#enter wrdev, iclass 4, count 0 2006.252.08:05:38.92#ibcon#first serial, iclass 4, count 0 2006.252.08:05:38.92#ibcon#enter sib2, iclass 4, count 0 2006.252.08:05:38.92#ibcon#flushed, iclass 4, count 0 2006.252.08:05:38.92#ibcon#about to write, iclass 4, count 0 2006.252.08:05:38.92#ibcon#wrote, iclass 4, count 0 2006.252.08:05:38.92#ibcon#about to read 3, iclass 4, count 0 2006.252.08:05:38.94#ibcon#read 3, iclass 4, count 0 2006.252.08:05:38.94#ibcon#about to read 4, iclass 4, count 0 2006.252.08:05:38.94#ibcon#read 4, iclass 4, count 0 2006.252.08:05:38.94#ibcon#about to read 5, iclass 4, count 0 2006.252.08:05:38.94#ibcon#read 5, iclass 4, count 0 2006.252.08:05:38.94#ibcon#about to read 6, iclass 4, count 0 2006.252.08:05:38.94#ibcon#read 6, iclass 4, count 0 2006.252.08:05:38.94#ibcon#end of sib2, iclass 4, count 0 2006.252.08:05:38.94#ibcon#*mode == 0, iclass 4, count 0 2006.252.08:05:38.94#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.252.08:05:38.94#ibcon#[26=FRQ=04,832.99\r\n] 2006.252.08:05:38.94#ibcon#*before write, iclass 4, count 0 2006.252.08:05:38.94#ibcon#enter sib2, iclass 4, count 0 2006.252.08:05:38.94#ibcon#flushed, iclass 4, count 0 2006.252.08:05:38.94#ibcon#about to write, iclass 4, count 0 2006.252.08:05:38.94#ibcon#wrote, iclass 4, count 0 2006.252.08:05:38.94#ibcon#about to read 3, iclass 4, count 0 2006.252.08:05:38.99#ibcon#read 3, iclass 4, count 0 2006.252.08:05:38.99#ibcon#about to read 4, iclass 4, count 0 2006.252.08:05:38.99#ibcon#read 4, iclass 4, count 0 2006.252.08:05:38.99#ibcon#about to read 5, iclass 4, count 0 2006.252.08:05:38.99#ibcon#read 5, iclass 4, count 0 2006.252.08:05:38.99#ibcon#about to read 6, iclass 4, count 0 2006.252.08:05:38.99#ibcon#read 6, iclass 4, count 0 2006.252.08:05:38.99#ibcon#end of sib2, iclass 4, count 0 2006.252.08:05:38.99#ibcon#*after write, iclass 4, count 0 2006.252.08:05:38.99#ibcon#*before return 0, iclass 4, count 0 2006.252.08:05:38.99#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.252.08:05:38.99#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.252.08:05:38.99#ibcon#about to clear, iclass 4 cls_cnt 0 2006.252.08:05:38.99#ibcon#cleared, iclass 4 cls_cnt 0 2006.252.08:05:38.99$vc4f8/va=4,7 2006.252.08:05:38.99#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.252.08:05:38.99#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.252.08:05:38.99#ibcon#ireg 11 cls_cnt 2 2006.252.08:05:38.99#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.252.08:05:39.04#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.252.08:05:39.04#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.252.08:05:39.04#ibcon#enter wrdev, iclass 6, count 2 2006.252.08:05:39.04#ibcon#first serial, iclass 6, count 2 2006.252.08:05:39.04#ibcon#enter sib2, iclass 6, count 2 2006.252.08:05:39.04#ibcon#flushed, iclass 6, count 2 2006.252.08:05:39.04#ibcon#about to write, iclass 6, count 2 2006.252.08:05:39.04#ibcon#wrote, iclass 6, count 2 2006.252.08:05:39.04#ibcon#about to read 3, iclass 6, count 2 2006.252.08:05:39.06#ibcon#read 3, iclass 6, count 2 2006.252.08:05:39.06#ibcon#about to read 4, iclass 6, count 2 2006.252.08:05:39.06#ibcon#read 4, iclass 6, count 2 2006.252.08:05:39.06#ibcon#about to read 5, iclass 6, count 2 2006.252.08:05:39.06#ibcon#read 5, iclass 6, count 2 2006.252.08:05:39.06#ibcon#about to read 6, iclass 6, count 2 2006.252.08:05:39.06#ibcon#read 6, iclass 6, count 2 2006.252.08:05:39.06#ibcon#end of sib2, iclass 6, count 2 2006.252.08:05:39.06#ibcon#*mode == 0, iclass 6, count 2 2006.252.08:05:39.06#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.252.08:05:39.06#ibcon#[25=AT04-07\r\n] 2006.252.08:05:39.06#ibcon#*before write, iclass 6, count 2 2006.252.08:05:39.06#ibcon#enter sib2, iclass 6, count 2 2006.252.08:05:39.06#ibcon#flushed, iclass 6, count 2 2006.252.08:05:39.06#ibcon#about to write, iclass 6, count 2 2006.252.08:05:39.06#ibcon#wrote, iclass 6, count 2 2006.252.08:05:39.06#ibcon#about to read 3, iclass 6, count 2 2006.252.08:05:39.09#ibcon#read 3, iclass 6, count 2 2006.252.08:05:39.09#ibcon#about to read 4, iclass 6, count 2 2006.252.08:05:39.09#ibcon#read 4, iclass 6, count 2 2006.252.08:05:39.09#ibcon#about to read 5, iclass 6, count 2 2006.252.08:05:39.09#ibcon#read 5, iclass 6, count 2 2006.252.08:05:39.09#ibcon#about to read 6, iclass 6, count 2 2006.252.08:05:39.09#ibcon#read 6, iclass 6, count 2 2006.252.08:05:39.09#ibcon#end of sib2, iclass 6, count 2 2006.252.08:05:39.09#ibcon#*after write, iclass 6, count 2 2006.252.08:05:39.09#ibcon#*before return 0, iclass 6, count 2 2006.252.08:05:39.09#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.252.08:05:39.09#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.252.08:05:39.09#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.252.08:05:39.09#ibcon#ireg 7 cls_cnt 0 2006.252.08:05:39.09#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.252.08:05:39.21#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.252.08:05:39.21#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.252.08:05:39.21#ibcon#enter wrdev, iclass 6, count 0 2006.252.08:05:39.21#ibcon#first serial, iclass 6, count 0 2006.252.08:05:39.21#ibcon#enter sib2, iclass 6, count 0 2006.252.08:05:39.21#ibcon#flushed, iclass 6, count 0 2006.252.08:05:39.21#ibcon#about to write, iclass 6, count 0 2006.252.08:05:39.21#ibcon#wrote, iclass 6, count 0 2006.252.08:05:39.21#ibcon#about to read 3, iclass 6, count 0 2006.252.08:05:39.23#ibcon#read 3, iclass 6, count 0 2006.252.08:05:39.23#ibcon#about to read 4, iclass 6, count 0 2006.252.08:05:39.23#ibcon#read 4, iclass 6, count 0 2006.252.08:05:39.23#ibcon#about to read 5, iclass 6, count 0 2006.252.08:05:39.23#ibcon#read 5, iclass 6, count 0 2006.252.08:05:39.23#ibcon#about to read 6, iclass 6, count 0 2006.252.08:05:39.23#ibcon#read 6, iclass 6, count 0 2006.252.08:05:39.23#ibcon#end of sib2, iclass 6, count 0 2006.252.08:05:39.23#ibcon#*mode == 0, iclass 6, count 0 2006.252.08:05:39.23#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.252.08:05:39.23#ibcon#[25=USB\r\n] 2006.252.08:05:39.23#ibcon#*before write, iclass 6, count 0 2006.252.08:05:39.23#ibcon#enter sib2, iclass 6, count 0 2006.252.08:05:39.23#ibcon#flushed, iclass 6, count 0 2006.252.08:05:39.23#ibcon#about to write, iclass 6, count 0 2006.252.08:05:39.23#ibcon#wrote, iclass 6, count 0 2006.252.08:05:39.23#ibcon#about to read 3, iclass 6, count 0 2006.252.08:05:39.26#ibcon#read 3, iclass 6, count 0 2006.252.08:05:39.26#ibcon#about to read 4, iclass 6, count 0 2006.252.08:05:39.26#ibcon#read 4, iclass 6, count 0 2006.252.08:05:39.26#ibcon#about to read 5, iclass 6, count 0 2006.252.08:05:39.26#ibcon#read 5, iclass 6, count 0 2006.252.08:05:39.26#ibcon#about to read 6, iclass 6, count 0 2006.252.08:05:39.26#ibcon#read 6, iclass 6, count 0 2006.252.08:05:39.26#ibcon#end of sib2, iclass 6, count 0 2006.252.08:05:39.26#ibcon#*after write, iclass 6, count 0 2006.252.08:05:39.26#ibcon#*before return 0, iclass 6, count 0 2006.252.08:05:39.26#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.252.08:05:39.26#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.252.08:05:39.26#ibcon#about to clear, iclass 6 cls_cnt 0 2006.252.08:05:39.26#ibcon#cleared, iclass 6 cls_cnt 0 2006.252.08:05:39.26$vc4f8/valo=5,652.99 2006.252.08:05:39.26#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.252.08:05:39.26#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.252.08:05:39.26#ibcon#ireg 17 cls_cnt 0 2006.252.08:05:39.26#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.252.08:05:39.26#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.252.08:05:39.26#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.252.08:05:39.26#ibcon#enter wrdev, iclass 10, count 0 2006.252.08:05:39.26#ibcon#first serial, iclass 10, count 0 2006.252.08:05:39.26#ibcon#enter sib2, iclass 10, count 0 2006.252.08:05:39.26#ibcon#flushed, iclass 10, count 0 2006.252.08:05:39.26#ibcon#about to write, iclass 10, count 0 2006.252.08:05:39.26#ibcon#wrote, iclass 10, count 0 2006.252.08:05:39.26#ibcon#about to read 3, iclass 10, count 0 2006.252.08:05:39.28#ibcon#read 3, iclass 10, count 0 2006.252.08:05:39.28#ibcon#about to read 4, iclass 10, count 0 2006.252.08:05:39.28#ibcon#read 4, iclass 10, count 0 2006.252.08:05:39.28#ibcon#about to read 5, iclass 10, count 0 2006.252.08:05:39.28#ibcon#read 5, iclass 10, count 0 2006.252.08:05:39.28#ibcon#about to read 6, iclass 10, count 0 2006.252.08:05:39.28#ibcon#read 6, iclass 10, count 0 2006.252.08:05:39.28#ibcon#end of sib2, iclass 10, count 0 2006.252.08:05:39.28#ibcon#*mode == 0, iclass 10, count 0 2006.252.08:05:39.28#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.252.08:05:39.28#ibcon#[26=FRQ=05,652.99\r\n] 2006.252.08:05:39.28#ibcon#*before write, iclass 10, count 0 2006.252.08:05:39.28#ibcon#enter sib2, iclass 10, count 0 2006.252.08:05:39.28#ibcon#flushed, iclass 10, count 0 2006.252.08:05:39.28#ibcon#about to write, iclass 10, count 0 2006.252.08:05:39.28#ibcon#wrote, iclass 10, count 0 2006.252.08:05:39.28#ibcon#about to read 3, iclass 10, count 0 2006.252.08:05:39.32#ibcon#read 3, iclass 10, count 0 2006.252.08:05:39.32#ibcon#about to read 4, iclass 10, count 0 2006.252.08:05:39.32#ibcon#read 4, iclass 10, count 0 2006.252.08:05:39.32#ibcon#about to read 5, iclass 10, count 0 2006.252.08:05:39.32#ibcon#read 5, iclass 10, count 0 2006.252.08:05:39.32#ibcon#about to read 6, iclass 10, count 0 2006.252.08:05:39.32#ibcon#read 6, iclass 10, count 0 2006.252.08:05:39.32#ibcon#end of sib2, iclass 10, count 0 2006.252.08:05:39.32#ibcon#*after write, iclass 10, count 0 2006.252.08:05:39.32#ibcon#*before return 0, iclass 10, count 0 2006.252.08:05:39.32#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.252.08:05:39.32#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.252.08:05:39.32#ibcon#about to clear, iclass 10 cls_cnt 0 2006.252.08:05:39.32#ibcon#cleared, iclass 10 cls_cnt 0 2006.252.08:05:39.32$vc4f8/va=5,7 2006.252.08:05:39.32#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.252.08:05:39.32#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.252.08:05:39.32#ibcon#ireg 11 cls_cnt 2 2006.252.08:05:39.32#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.252.08:05:39.38#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.252.08:05:39.38#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.252.08:05:39.38#ibcon#enter wrdev, iclass 12, count 2 2006.252.08:05:39.38#ibcon#first serial, iclass 12, count 2 2006.252.08:05:39.38#ibcon#enter sib2, iclass 12, count 2 2006.252.08:05:39.38#ibcon#flushed, iclass 12, count 2 2006.252.08:05:39.38#ibcon#about to write, iclass 12, count 2 2006.252.08:05:39.38#ibcon#wrote, iclass 12, count 2 2006.252.08:05:39.38#ibcon#about to read 3, iclass 12, count 2 2006.252.08:05:39.40#ibcon#read 3, iclass 12, count 2 2006.252.08:05:39.40#ibcon#about to read 4, iclass 12, count 2 2006.252.08:05:39.40#ibcon#read 4, iclass 12, count 2 2006.252.08:05:39.40#ibcon#about to read 5, iclass 12, count 2 2006.252.08:05:39.40#ibcon#read 5, iclass 12, count 2 2006.252.08:05:39.40#ibcon#about to read 6, iclass 12, count 2 2006.252.08:05:39.40#ibcon#read 6, iclass 12, count 2 2006.252.08:05:39.40#ibcon#end of sib2, iclass 12, count 2 2006.252.08:05:39.40#ibcon#*mode == 0, iclass 12, count 2 2006.252.08:05:39.40#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.252.08:05:39.40#ibcon#[25=AT05-07\r\n] 2006.252.08:05:39.40#ibcon#*before write, iclass 12, count 2 2006.252.08:05:39.40#ibcon#enter sib2, iclass 12, count 2 2006.252.08:05:39.40#ibcon#flushed, iclass 12, count 2 2006.252.08:05:39.40#ibcon#about to write, iclass 12, count 2 2006.252.08:05:39.40#ibcon#wrote, iclass 12, count 2 2006.252.08:05:39.40#ibcon#about to read 3, iclass 12, count 2 2006.252.08:05:39.43#ibcon#read 3, iclass 12, count 2 2006.252.08:05:39.43#ibcon#about to read 4, iclass 12, count 2 2006.252.08:05:39.43#ibcon#read 4, iclass 12, count 2 2006.252.08:05:39.43#ibcon#about to read 5, iclass 12, count 2 2006.252.08:05:39.43#ibcon#read 5, iclass 12, count 2 2006.252.08:05:39.43#ibcon#about to read 6, iclass 12, count 2 2006.252.08:05:39.43#ibcon#read 6, iclass 12, count 2 2006.252.08:05:39.43#ibcon#end of sib2, iclass 12, count 2 2006.252.08:05:39.43#ibcon#*after write, iclass 12, count 2 2006.252.08:05:39.43#ibcon#*before return 0, iclass 12, count 2 2006.252.08:05:39.43#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.252.08:05:39.43#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.252.08:05:39.43#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.252.08:05:39.43#ibcon#ireg 7 cls_cnt 0 2006.252.08:05:39.43#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.252.08:05:39.55#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.252.08:05:39.55#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.252.08:05:39.55#ibcon#enter wrdev, iclass 12, count 0 2006.252.08:05:39.55#ibcon#first serial, iclass 12, count 0 2006.252.08:05:39.55#ibcon#enter sib2, iclass 12, count 0 2006.252.08:05:39.55#ibcon#flushed, iclass 12, count 0 2006.252.08:05:39.55#ibcon#about to write, iclass 12, count 0 2006.252.08:05:39.55#ibcon#wrote, iclass 12, count 0 2006.252.08:05:39.55#ibcon#about to read 3, iclass 12, count 0 2006.252.08:05:39.57#ibcon#read 3, iclass 12, count 0 2006.252.08:05:39.57#ibcon#about to read 4, iclass 12, count 0 2006.252.08:05:39.57#ibcon#read 4, iclass 12, count 0 2006.252.08:05:39.57#ibcon#about to read 5, iclass 12, count 0 2006.252.08:05:39.57#ibcon#read 5, iclass 12, count 0 2006.252.08:05:39.57#ibcon#about to read 6, iclass 12, count 0 2006.252.08:05:39.57#ibcon#read 6, iclass 12, count 0 2006.252.08:05:39.57#ibcon#end of sib2, iclass 12, count 0 2006.252.08:05:39.57#ibcon#*mode == 0, iclass 12, count 0 2006.252.08:05:39.57#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.252.08:05:39.57#ibcon#[25=USB\r\n] 2006.252.08:05:39.57#ibcon#*before write, iclass 12, count 0 2006.252.08:05:39.57#ibcon#enter sib2, iclass 12, count 0 2006.252.08:05:39.57#ibcon#flushed, iclass 12, count 0 2006.252.08:05:39.57#ibcon#about to write, iclass 12, count 0 2006.252.08:05:39.57#ibcon#wrote, iclass 12, count 0 2006.252.08:05:39.57#ibcon#about to read 3, iclass 12, count 0 2006.252.08:05:39.60#ibcon#read 3, iclass 12, count 0 2006.252.08:05:39.60#ibcon#about to read 4, iclass 12, count 0 2006.252.08:05:39.60#ibcon#read 4, iclass 12, count 0 2006.252.08:05:39.60#ibcon#about to read 5, iclass 12, count 0 2006.252.08:05:39.60#ibcon#read 5, iclass 12, count 0 2006.252.08:05:39.60#ibcon#about to read 6, iclass 12, count 0 2006.252.08:05:39.60#ibcon#read 6, iclass 12, count 0 2006.252.08:05:39.60#ibcon#end of sib2, iclass 12, count 0 2006.252.08:05:39.60#ibcon#*after write, iclass 12, count 0 2006.252.08:05:39.60#ibcon#*before return 0, iclass 12, count 0 2006.252.08:05:39.60#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.252.08:05:39.60#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.252.08:05:39.60#ibcon#about to clear, iclass 12 cls_cnt 0 2006.252.08:05:39.60#ibcon#cleared, iclass 12 cls_cnt 0 2006.252.08:05:39.60$vc4f8/valo=6,772.99 2006.252.08:05:39.60#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.252.08:05:39.60#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.252.08:05:39.60#ibcon#ireg 17 cls_cnt 0 2006.252.08:05:39.60#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.252.08:05:39.60#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.252.08:05:39.60#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.252.08:05:39.60#ibcon#enter wrdev, iclass 14, count 0 2006.252.08:05:39.60#ibcon#first serial, iclass 14, count 0 2006.252.08:05:39.60#ibcon#enter sib2, iclass 14, count 0 2006.252.08:05:39.60#ibcon#flushed, iclass 14, count 0 2006.252.08:05:39.60#ibcon#about to write, iclass 14, count 0 2006.252.08:05:39.60#ibcon#wrote, iclass 14, count 0 2006.252.08:05:39.60#ibcon#about to read 3, iclass 14, count 0 2006.252.08:05:39.62#ibcon#read 3, iclass 14, count 0 2006.252.08:05:39.62#ibcon#about to read 4, iclass 14, count 0 2006.252.08:05:39.62#ibcon#read 4, iclass 14, count 0 2006.252.08:05:39.62#ibcon#about to read 5, iclass 14, count 0 2006.252.08:05:39.62#ibcon#read 5, iclass 14, count 0 2006.252.08:05:39.62#ibcon#about to read 6, iclass 14, count 0 2006.252.08:05:39.62#ibcon#read 6, iclass 14, count 0 2006.252.08:05:39.62#ibcon#end of sib2, iclass 14, count 0 2006.252.08:05:39.62#ibcon#*mode == 0, iclass 14, count 0 2006.252.08:05:39.62#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.252.08:05:39.62#ibcon#[26=FRQ=06,772.99\r\n] 2006.252.08:05:39.62#ibcon#*before write, iclass 14, count 0 2006.252.08:05:39.62#ibcon#enter sib2, iclass 14, count 0 2006.252.08:05:39.62#ibcon#flushed, iclass 14, count 0 2006.252.08:05:39.62#ibcon#about to write, iclass 14, count 0 2006.252.08:05:39.62#ibcon#wrote, iclass 14, count 0 2006.252.08:05:39.62#ibcon#about to read 3, iclass 14, count 0 2006.252.08:05:39.67#ibcon#read 3, iclass 14, count 0 2006.252.08:05:39.67#ibcon#about to read 4, iclass 14, count 0 2006.252.08:05:39.67#ibcon#read 4, iclass 14, count 0 2006.252.08:05:39.67#ibcon#about to read 5, iclass 14, count 0 2006.252.08:05:39.67#ibcon#read 5, iclass 14, count 0 2006.252.08:05:39.67#ibcon#about to read 6, iclass 14, count 0 2006.252.08:05:39.67#ibcon#read 6, iclass 14, count 0 2006.252.08:05:39.67#ibcon#end of sib2, iclass 14, count 0 2006.252.08:05:39.67#ibcon#*after write, iclass 14, count 0 2006.252.08:05:39.67#ibcon#*before return 0, iclass 14, count 0 2006.252.08:05:39.67#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.252.08:05:39.67#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.252.08:05:39.67#ibcon#about to clear, iclass 14 cls_cnt 0 2006.252.08:05:39.67#ibcon#cleared, iclass 14 cls_cnt 0 2006.252.08:05:39.67$vc4f8/va=6,7 2006.252.08:05:39.67#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.252.08:05:39.67#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.252.08:05:39.67#ibcon#ireg 11 cls_cnt 2 2006.252.08:05:39.67#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.252.08:05:39.72#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.252.08:05:39.72#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.252.08:05:39.72#ibcon#enter wrdev, iclass 16, count 2 2006.252.08:05:39.72#ibcon#first serial, iclass 16, count 2 2006.252.08:05:39.72#ibcon#enter sib2, iclass 16, count 2 2006.252.08:05:39.72#ibcon#flushed, iclass 16, count 2 2006.252.08:05:39.72#ibcon#about to write, iclass 16, count 2 2006.252.08:05:39.72#ibcon#wrote, iclass 16, count 2 2006.252.08:05:39.72#ibcon#about to read 3, iclass 16, count 2 2006.252.08:05:39.74#ibcon#read 3, iclass 16, count 2 2006.252.08:05:39.74#ibcon#about to read 4, iclass 16, count 2 2006.252.08:05:39.74#ibcon#read 4, iclass 16, count 2 2006.252.08:05:39.74#ibcon#about to read 5, iclass 16, count 2 2006.252.08:05:39.74#ibcon#read 5, iclass 16, count 2 2006.252.08:05:39.74#ibcon#about to read 6, iclass 16, count 2 2006.252.08:05:39.74#ibcon#read 6, iclass 16, count 2 2006.252.08:05:39.74#ibcon#end of sib2, iclass 16, count 2 2006.252.08:05:39.74#ibcon#*mode == 0, iclass 16, count 2 2006.252.08:05:39.74#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.252.08:05:39.74#ibcon#[25=AT06-07\r\n] 2006.252.08:05:39.74#ibcon#*before write, iclass 16, count 2 2006.252.08:05:39.74#ibcon#enter sib2, iclass 16, count 2 2006.252.08:05:39.74#ibcon#flushed, iclass 16, count 2 2006.252.08:05:39.74#ibcon#about to write, iclass 16, count 2 2006.252.08:05:39.74#ibcon#wrote, iclass 16, count 2 2006.252.08:05:39.74#ibcon#about to read 3, iclass 16, count 2 2006.252.08:05:39.77#ibcon#read 3, iclass 16, count 2 2006.252.08:05:39.77#ibcon#about to read 4, iclass 16, count 2 2006.252.08:05:39.77#ibcon#read 4, iclass 16, count 2 2006.252.08:05:39.77#ibcon#about to read 5, iclass 16, count 2 2006.252.08:05:39.77#ibcon#read 5, iclass 16, count 2 2006.252.08:05:39.77#ibcon#about to read 6, iclass 16, count 2 2006.252.08:05:39.77#ibcon#read 6, iclass 16, count 2 2006.252.08:05:39.77#ibcon#end of sib2, iclass 16, count 2 2006.252.08:05:39.77#ibcon#*after write, iclass 16, count 2 2006.252.08:05:39.77#ibcon#*before return 0, iclass 16, count 2 2006.252.08:05:39.77#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.252.08:05:39.77#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.252.08:05:39.77#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.252.08:05:39.77#ibcon#ireg 7 cls_cnt 0 2006.252.08:05:39.77#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.252.08:05:39.89#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.252.08:05:39.89#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.252.08:05:39.89#ibcon#enter wrdev, iclass 16, count 0 2006.252.08:05:39.89#ibcon#first serial, iclass 16, count 0 2006.252.08:05:39.89#ibcon#enter sib2, iclass 16, count 0 2006.252.08:05:39.89#ibcon#flushed, iclass 16, count 0 2006.252.08:05:39.89#ibcon#about to write, iclass 16, count 0 2006.252.08:05:39.89#ibcon#wrote, iclass 16, count 0 2006.252.08:05:39.89#ibcon#about to read 3, iclass 16, count 0 2006.252.08:05:39.91#ibcon#read 3, iclass 16, count 0 2006.252.08:05:39.91#ibcon#about to read 4, iclass 16, count 0 2006.252.08:05:39.91#ibcon#read 4, iclass 16, count 0 2006.252.08:05:39.91#ibcon#about to read 5, iclass 16, count 0 2006.252.08:05:39.91#ibcon#read 5, iclass 16, count 0 2006.252.08:05:39.91#ibcon#about to read 6, iclass 16, count 0 2006.252.08:05:39.91#ibcon#read 6, iclass 16, count 0 2006.252.08:05:39.91#ibcon#end of sib2, iclass 16, count 0 2006.252.08:05:39.91#ibcon#*mode == 0, iclass 16, count 0 2006.252.08:05:39.91#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.252.08:05:39.91#ibcon#[25=USB\r\n] 2006.252.08:05:39.91#ibcon#*before write, iclass 16, count 0 2006.252.08:05:39.91#ibcon#enter sib2, iclass 16, count 0 2006.252.08:05:39.91#ibcon#flushed, iclass 16, count 0 2006.252.08:05:39.91#ibcon#about to write, iclass 16, count 0 2006.252.08:05:39.91#ibcon#wrote, iclass 16, count 0 2006.252.08:05:39.91#ibcon#about to read 3, iclass 16, count 0 2006.252.08:05:39.94#ibcon#read 3, iclass 16, count 0 2006.252.08:05:39.94#ibcon#about to read 4, iclass 16, count 0 2006.252.08:05:39.94#ibcon#read 4, iclass 16, count 0 2006.252.08:05:39.94#ibcon#about to read 5, iclass 16, count 0 2006.252.08:05:39.94#ibcon#read 5, iclass 16, count 0 2006.252.08:05:39.94#ibcon#about to read 6, iclass 16, count 0 2006.252.08:05:39.94#ibcon#read 6, iclass 16, count 0 2006.252.08:05:39.94#ibcon#end of sib2, iclass 16, count 0 2006.252.08:05:39.94#ibcon#*after write, iclass 16, count 0 2006.252.08:05:39.94#ibcon#*before return 0, iclass 16, count 0 2006.252.08:05:39.94#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.252.08:05:39.94#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.252.08:05:39.94#ibcon#about to clear, iclass 16 cls_cnt 0 2006.252.08:05:39.94#ibcon#cleared, iclass 16 cls_cnt 0 2006.252.08:05:39.94$vc4f8/valo=7,832.99 2006.252.08:05:39.94#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.252.08:05:39.94#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.252.08:05:39.94#ibcon#ireg 17 cls_cnt 0 2006.252.08:05:39.94#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.252.08:05:39.94#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.252.08:05:39.94#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.252.08:05:39.94#ibcon#enter wrdev, iclass 18, count 0 2006.252.08:05:39.94#ibcon#first serial, iclass 18, count 0 2006.252.08:05:39.94#ibcon#enter sib2, iclass 18, count 0 2006.252.08:05:39.94#ibcon#flushed, iclass 18, count 0 2006.252.08:05:39.94#ibcon#about to write, iclass 18, count 0 2006.252.08:05:39.94#ibcon#wrote, iclass 18, count 0 2006.252.08:05:39.94#ibcon#about to read 3, iclass 18, count 0 2006.252.08:05:39.96#ibcon#read 3, iclass 18, count 0 2006.252.08:05:39.96#ibcon#about to read 4, iclass 18, count 0 2006.252.08:05:39.96#ibcon#read 4, iclass 18, count 0 2006.252.08:05:39.96#ibcon#about to read 5, iclass 18, count 0 2006.252.08:05:39.96#ibcon#read 5, iclass 18, count 0 2006.252.08:05:39.96#ibcon#about to read 6, iclass 18, count 0 2006.252.08:05:39.96#ibcon#read 6, iclass 18, count 0 2006.252.08:05:39.96#ibcon#end of sib2, iclass 18, count 0 2006.252.08:05:39.96#ibcon#*mode == 0, iclass 18, count 0 2006.252.08:05:39.96#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.252.08:05:39.96#ibcon#[26=FRQ=07,832.99\r\n] 2006.252.08:05:39.96#ibcon#*before write, iclass 18, count 0 2006.252.08:05:39.96#ibcon#enter sib2, iclass 18, count 0 2006.252.08:05:39.96#ibcon#flushed, iclass 18, count 0 2006.252.08:05:39.96#ibcon#about to write, iclass 18, count 0 2006.252.08:05:39.96#ibcon#wrote, iclass 18, count 0 2006.252.08:05:39.96#ibcon#about to read 3, iclass 18, count 0 2006.252.08:05:40.00#ibcon#read 3, iclass 18, count 0 2006.252.08:05:40.00#ibcon#about to read 4, iclass 18, count 0 2006.252.08:05:40.00#ibcon#read 4, iclass 18, count 0 2006.252.08:05:40.00#ibcon#about to read 5, iclass 18, count 0 2006.252.08:05:40.00#ibcon#read 5, iclass 18, count 0 2006.252.08:05:40.00#ibcon#about to read 6, iclass 18, count 0 2006.252.08:05:40.00#ibcon#read 6, iclass 18, count 0 2006.252.08:05:40.00#ibcon#end of sib2, iclass 18, count 0 2006.252.08:05:40.00#ibcon#*after write, iclass 18, count 0 2006.252.08:05:40.00#ibcon#*before return 0, iclass 18, count 0 2006.252.08:05:40.00#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.252.08:05:40.00#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.252.08:05:40.00#ibcon#about to clear, iclass 18 cls_cnt 0 2006.252.08:05:40.00#ibcon#cleared, iclass 18 cls_cnt 0 2006.252.08:05:40.00$vc4f8/va=7,7 2006.252.08:05:40.00#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.252.08:05:40.00#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.252.08:05:40.00#ibcon#ireg 11 cls_cnt 2 2006.252.08:05:40.00#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.252.08:05:40.06#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.252.08:05:40.06#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.252.08:05:40.06#ibcon#enter wrdev, iclass 20, count 2 2006.252.08:05:40.06#ibcon#first serial, iclass 20, count 2 2006.252.08:05:40.06#ibcon#enter sib2, iclass 20, count 2 2006.252.08:05:40.06#ibcon#flushed, iclass 20, count 2 2006.252.08:05:40.06#ibcon#about to write, iclass 20, count 2 2006.252.08:05:40.06#ibcon#wrote, iclass 20, count 2 2006.252.08:05:40.06#ibcon#about to read 3, iclass 20, count 2 2006.252.08:05:40.08#ibcon#read 3, iclass 20, count 2 2006.252.08:05:40.08#ibcon#about to read 4, iclass 20, count 2 2006.252.08:05:40.08#ibcon#read 4, iclass 20, count 2 2006.252.08:05:40.08#ibcon#about to read 5, iclass 20, count 2 2006.252.08:05:40.08#ibcon#read 5, iclass 20, count 2 2006.252.08:05:40.08#ibcon#about to read 6, iclass 20, count 2 2006.252.08:05:40.08#ibcon#read 6, iclass 20, count 2 2006.252.08:05:40.08#ibcon#end of sib2, iclass 20, count 2 2006.252.08:05:40.08#ibcon#*mode == 0, iclass 20, count 2 2006.252.08:05:40.08#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.252.08:05:40.08#ibcon#[25=AT07-07\r\n] 2006.252.08:05:40.08#ibcon#*before write, iclass 20, count 2 2006.252.08:05:40.08#ibcon#enter sib2, iclass 20, count 2 2006.252.08:05:40.08#ibcon#flushed, iclass 20, count 2 2006.252.08:05:40.08#ibcon#about to write, iclass 20, count 2 2006.252.08:05:40.08#ibcon#wrote, iclass 20, count 2 2006.252.08:05:40.08#ibcon#about to read 3, iclass 20, count 2 2006.252.08:05:40.11#ibcon#read 3, iclass 20, count 2 2006.252.08:05:40.11#ibcon#about to read 4, iclass 20, count 2 2006.252.08:05:40.11#ibcon#read 4, iclass 20, count 2 2006.252.08:05:40.11#ibcon#about to read 5, iclass 20, count 2 2006.252.08:05:40.11#ibcon#read 5, iclass 20, count 2 2006.252.08:05:40.11#ibcon#about to read 6, iclass 20, count 2 2006.252.08:05:40.11#ibcon#read 6, iclass 20, count 2 2006.252.08:05:40.11#ibcon#end of sib2, iclass 20, count 2 2006.252.08:05:40.11#ibcon#*after write, iclass 20, count 2 2006.252.08:05:40.11#ibcon#*before return 0, iclass 20, count 2 2006.252.08:05:40.11#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.252.08:05:40.11#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.252.08:05:40.11#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.252.08:05:40.11#ibcon#ireg 7 cls_cnt 0 2006.252.08:05:40.11#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.252.08:05:40.23#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.252.08:05:40.23#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.252.08:05:40.23#ibcon#enter wrdev, iclass 20, count 0 2006.252.08:05:40.23#ibcon#first serial, iclass 20, count 0 2006.252.08:05:40.23#ibcon#enter sib2, iclass 20, count 0 2006.252.08:05:40.23#ibcon#flushed, iclass 20, count 0 2006.252.08:05:40.23#ibcon#about to write, iclass 20, count 0 2006.252.08:05:40.23#ibcon#wrote, iclass 20, count 0 2006.252.08:05:40.23#ibcon#about to read 3, iclass 20, count 0 2006.252.08:05:40.25#ibcon#read 3, iclass 20, count 0 2006.252.08:05:40.25#ibcon#about to read 4, iclass 20, count 0 2006.252.08:05:40.25#ibcon#read 4, iclass 20, count 0 2006.252.08:05:40.25#ibcon#about to read 5, iclass 20, count 0 2006.252.08:05:40.25#ibcon#read 5, iclass 20, count 0 2006.252.08:05:40.25#ibcon#about to read 6, iclass 20, count 0 2006.252.08:05:40.25#ibcon#read 6, iclass 20, count 0 2006.252.08:05:40.25#ibcon#end of sib2, iclass 20, count 0 2006.252.08:05:40.25#ibcon#*mode == 0, iclass 20, count 0 2006.252.08:05:40.25#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.252.08:05:40.25#ibcon#[25=USB\r\n] 2006.252.08:05:40.25#ibcon#*before write, iclass 20, count 0 2006.252.08:05:40.25#ibcon#enter sib2, iclass 20, count 0 2006.252.08:05:40.25#ibcon#flushed, iclass 20, count 0 2006.252.08:05:40.25#ibcon#about to write, iclass 20, count 0 2006.252.08:05:40.25#ibcon#wrote, iclass 20, count 0 2006.252.08:05:40.25#ibcon#about to read 3, iclass 20, count 0 2006.252.08:05:40.28#ibcon#read 3, iclass 20, count 0 2006.252.08:05:40.28#ibcon#about to read 4, iclass 20, count 0 2006.252.08:05:40.28#ibcon#read 4, iclass 20, count 0 2006.252.08:05:40.28#ibcon#about to read 5, iclass 20, count 0 2006.252.08:05:40.28#ibcon#read 5, iclass 20, count 0 2006.252.08:05:40.28#ibcon#about to read 6, iclass 20, count 0 2006.252.08:05:40.28#ibcon#read 6, iclass 20, count 0 2006.252.08:05:40.28#ibcon#end of sib2, iclass 20, count 0 2006.252.08:05:40.28#ibcon#*after write, iclass 20, count 0 2006.252.08:05:40.28#ibcon#*before return 0, iclass 20, count 0 2006.252.08:05:40.28#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.252.08:05:40.28#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.252.08:05:40.28#ibcon#about to clear, iclass 20 cls_cnt 0 2006.252.08:05:40.28#ibcon#cleared, iclass 20 cls_cnt 0 2006.252.08:05:40.28$vc4f8/valo=8,852.99 2006.252.08:05:40.28#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.252.08:05:40.28#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.252.08:05:40.28#ibcon#ireg 17 cls_cnt 0 2006.252.08:05:40.28#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.252.08:05:40.28#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.252.08:05:40.28#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.252.08:05:40.28#ibcon#enter wrdev, iclass 22, count 0 2006.252.08:05:40.28#ibcon#first serial, iclass 22, count 0 2006.252.08:05:40.28#ibcon#enter sib2, iclass 22, count 0 2006.252.08:05:40.28#ibcon#flushed, iclass 22, count 0 2006.252.08:05:40.28#ibcon#about to write, iclass 22, count 0 2006.252.08:05:40.28#ibcon#wrote, iclass 22, count 0 2006.252.08:05:40.28#ibcon#about to read 3, iclass 22, count 0 2006.252.08:05:40.30#ibcon#read 3, iclass 22, count 0 2006.252.08:05:40.30#ibcon#about to read 4, iclass 22, count 0 2006.252.08:05:40.30#ibcon#read 4, iclass 22, count 0 2006.252.08:05:40.30#ibcon#about to read 5, iclass 22, count 0 2006.252.08:05:40.30#ibcon#read 5, iclass 22, count 0 2006.252.08:05:40.30#ibcon#about to read 6, iclass 22, count 0 2006.252.08:05:40.30#ibcon#read 6, iclass 22, count 0 2006.252.08:05:40.30#ibcon#end of sib2, iclass 22, count 0 2006.252.08:05:40.30#ibcon#*mode == 0, iclass 22, count 0 2006.252.08:05:40.30#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.252.08:05:40.30#ibcon#[26=FRQ=08,852.99\r\n] 2006.252.08:05:40.30#ibcon#*before write, iclass 22, count 0 2006.252.08:05:40.30#ibcon#enter sib2, iclass 22, count 0 2006.252.08:05:40.30#ibcon#flushed, iclass 22, count 0 2006.252.08:05:40.30#ibcon#about to write, iclass 22, count 0 2006.252.08:05:40.30#ibcon#wrote, iclass 22, count 0 2006.252.08:05:40.30#ibcon#about to read 3, iclass 22, count 0 2006.252.08:05:40.35#ibcon#read 3, iclass 22, count 0 2006.252.08:05:40.35#ibcon#about to read 4, iclass 22, count 0 2006.252.08:05:40.35#ibcon#read 4, iclass 22, count 0 2006.252.08:05:40.35#ibcon#about to read 5, iclass 22, count 0 2006.252.08:05:40.35#ibcon#read 5, iclass 22, count 0 2006.252.08:05:40.35#ibcon#about to read 6, iclass 22, count 0 2006.252.08:05:40.35#ibcon#read 6, iclass 22, count 0 2006.252.08:05:40.35#ibcon#end of sib2, iclass 22, count 0 2006.252.08:05:40.35#ibcon#*after write, iclass 22, count 0 2006.252.08:05:40.35#ibcon#*before return 0, iclass 22, count 0 2006.252.08:05:40.35#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.252.08:05:40.35#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.252.08:05:40.35#ibcon#about to clear, iclass 22 cls_cnt 0 2006.252.08:05:40.35#ibcon#cleared, iclass 22 cls_cnt 0 2006.252.08:05:40.35$vc4f8/va=8,7 2006.252.08:05:40.35#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.252.08:05:40.35#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.252.08:05:40.35#ibcon#ireg 11 cls_cnt 2 2006.252.08:05:40.35#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.252.08:05:40.40#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.252.08:05:40.40#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.252.08:05:40.40#ibcon#enter wrdev, iclass 24, count 2 2006.252.08:05:40.40#ibcon#first serial, iclass 24, count 2 2006.252.08:05:40.40#ibcon#enter sib2, iclass 24, count 2 2006.252.08:05:40.40#ibcon#flushed, iclass 24, count 2 2006.252.08:05:40.40#ibcon#about to write, iclass 24, count 2 2006.252.08:05:40.40#ibcon#wrote, iclass 24, count 2 2006.252.08:05:40.40#ibcon#about to read 3, iclass 24, count 2 2006.252.08:05:40.42#ibcon#read 3, iclass 24, count 2 2006.252.08:05:40.42#ibcon#about to read 4, iclass 24, count 2 2006.252.08:05:40.42#ibcon#read 4, iclass 24, count 2 2006.252.08:05:40.42#ibcon#about to read 5, iclass 24, count 2 2006.252.08:05:40.42#ibcon#read 5, iclass 24, count 2 2006.252.08:05:40.42#ibcon#about to read 6, iclass 24, count 2 2006.252.08:05:40.42#ibcon#read 6, iclass 24, count 2 2006.252.08:05:40.42#ibcon#end of sib2, iclass 24, count 2 2006.252.08:05:40.42#ibcon#*mode == 0, iclass 24, count 2 2006.252.08:05:40.42#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.252.08:05:40.42#ibcon#[25=AT08-07\r\n] 2006.252.08:05:40.42#ibcon#*before write, iclass 24, count 2 2006.252.08:05:40.42#ibcon#enter sib2, iclass 24, count 2 2006.252.08:05:40.42#ibcon#flushed, iclass 24, count 2 2006.252.08:05:40.42#ibcon#about to write, iclass 24, count 2 2006.252.08:05:40.42#ibcon#wrote, iclass 24, count 2 2006.252.08:05:40.42#ibcon#about to read 3, iclass 24, count 2 2006.252.08:05:40.45#ibcon#read 3, iclass 24, count 2 2006.252.08:05:40.45#ibcon#about to read 4, iclass 24, count 2 2006.252.08:05:40.45#ibcon#read 4, iclass 24, count 2 2006.252.08:05:40.45#ibcon#about to read 5, iclass 24, count 2 2006.252.08:05:40.45#ibcon#read 5, iclass 24, count 2 2006.252.08:05:40.45#ibcon#about to read 6, iclass 24, count 2 2006.252.08:05:40.45#ibcon#read 6, iclass 24, count 2 2006.252.08:05:40.45#ibcon#end of sib2, iclass 24, count 2 2006.252.08:05:40.45#ibcon#*after write, iclass 24, count 2 2006.252.08:05:40.45#ibcon#*before return 0, iclass 24, count 2 2006.252.08:05:40.45#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.252.08:05:40.45#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.252.08:05:40.45#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.252.08:05:40.45#ibcon#ireg 7 cls_cnt 0 2006.252.08:05:40.45#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.252.08:05:40.57#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.252.08:05:40.57#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.252.08:05:40.57#ibcon#enter wrdev, iclass 24, count 0 2006.252.08:05:40.57#ibcon#first serial, iclass 24, count 0 2006.252.08:05:40.57#ibcon#enter sib2, iclass 24, count 0 2006.252.08:05:40.57#ibcon#flushed, iclass 24, count 0 2006.252.08:05:40.57#ibcon#about to write, iclass 24, count 0 2006.252.08:05:40.57#ibcon#wrote, iclass 24, count 0 2006.252.08:05:40.57#ibcon#about to read 3, iclass 24, count 0 2006.252.08:05:40.59#ibcon#read 3, iclass 24, count 0 2006.252.08:05:40.59#ibcon#about to read 4, iclass 24, count 0 2006.252.08:05:40.59#ibcon#read 4, iclass 24, count 0 2006.252.08:05:40.59#ibcon#about to read 5, iclass 24, count 0 2006.252.08:05:40.59#ibcon#read 5, iclass 24, count 0 2006.252.08:05:40.59#ibcon#about to read 6, iclass 24, count 0 2006.252.08:05:40.59#ibcon#read 6, iclass 24, count 0 2006.252.08:05:40.59#ibcon#end of sib2, iclass 24, count 0 2006.252.08:05:40.59#ibcon#*mode == 0, iclass 24, count 0 2006.252.08:05:40.59#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.252.08:05:40.59#ibcon#[25=USB\r\n] 2006.252.08:05:40.59#ibcon#*before write, iclass 24, count 0 2006.252.08:05:40.59#ibcon#enter sib2, iclass 24, count 0 2006.252.08:05:40.59#ibcon#flushed, iclass 24, count 0 2006.252.08:05:40.59#ibcon#about to write, iclass 24, count 0 2006.252.08:05:40.59#ibcon#wrote, iclass 24, count 0 2006.252.08:05:40.59#ibcon#about to read 3, iclass 24, count 0 2006.252.08:05:40.62#ibcon#read 3, iclass 24, count 0 2006.252.08:05:40.62#ibcon#about to read 4, iclass 24, count 0 2006.252.08:05:40.62#ibcon#read 4, iclass 24, count 0 2006.252.08:05:40.62#ibcon#about to read 5, iclass 24, count 0 2006.252.08:05:40.62#ibcon#read 5, iclass 24, count 0 2006.252.08:05:40.62#ibcon#about to read 6, iclass 24, count 0 2006.252.08:05:40.62#ibcon#read 6, iclass 24, count 0 2006.252.08:05:40.62#ibcon#end of sib2, iclass 24, count 0 2006.252.08:05:40.62#ibcon#*after write, iclass 24, count 0 2006.252.08:05:40.62#ibcon#*before return 0, iclass 24, count 0 2006.252.08:05:40.62#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.252.08:05:40.62#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.252.08:05:40.62#ibcon#about to clear, iclass 24 cls_cnt 0 2006.252.08:05:40.62#ibcon#cleared, iclass 24 cls_cnt 0 2006.252.08:05:40.62$vc4f8/vblo=1,632.99 2006.252.08:05:40.62#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.252.08:05:40.62#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.252.08:05:40.62#ibcon#ireg 17 cls_cnt 0 2006.252.08:05:40.62#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.252.08:05:40.62#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.252.08:05:40.62#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.252.08:05:40.62#ibcon#enter wrdev, iclass 26, count 0 2006.252.08:05:40.62#ibcon#first serial, iclass 26, count 0 2006.252.08:05:40.62#ibcon#enter sib2, iclass 26, count 0 2006.252.08:05:40.62#ibcon#flushed, iclass 26, count 0 2006.252.08:05:40.62#ibcon#about to write, iclass 26, count 0 2006.252.08:05:40.62#ibcon#wrote, iclass 26, count 0 2006.252.08:05:40.62#ibcon#about to read 3, iclass 26, count 0 2006.252.08:05:40.64#ibcon#read 3, iclass 26, count 0 2006.252.08:05:40.64#ibcon#about to read 4, iclass 26, count 0 2006.252.08:05:40.64#ibcon#read 4, iclass 26, count 0 2006.252.08:05:40.64#ibcon#about to read 5, iclass 26, count 0 2006.252.08:05:40.64#ibcon#read 5, iclass 26, count 0 2006.252.08:05:40.64#ibcon#about to read 6, iclass 26, count 0 2006.252.08:05:40.64#ibcon#read 6, iclass 26, count 0 2006.252.08:05:40.64#ibcon#end of sib2, iclass 26, count 0 2006.252.08:05:40.64#ibcon#*mode == 0, iclass 26, count 0 2006.252.08:05:40.64#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.252.08:05:40.64#ibcon#[28=FRQ=01,632.99\r\n] 2006.252.08:05:40.64#ibcon#*before write, iclass 26, count 0 2006.252.08:05:40.64#ibcon#enter sib2, iclass 26, count 0 2006.252.08:05:40.64#ibcon#flushed, iclass 26, count 0 2006.252.08:05:40.64#ibcon#about to write, iclass 26, count 0 2006.252.08:05:40.64#ibcon#wrote, iclass 26, count 0 2006.252.08:05:40.64#ibcon#about to read 3, iclass 26, count 0 2006.252.08:05:40.68#ibcon#read 3, iclass 26, count 0 2006.252.08:05:40.68#ibcon#about to read 4, iclass 26, count 0 2006.252.08:05:40.68#ibcon#read 4, iclass 26, count 0 2006.252.08:05:40.68#ibcon#about to read 5, iclass 26, count 0 2006.252.08:05:40.68#ibcon#read 5, iclass 26, count 0 2006.252.08:05:40.68#ibcon#about to read 6, iclass 26, count 0 2006.252.08:05:40.68#ibcon#read 6, iclass 26, count 0 2006.252.08:05:40.68#ibcon#end of sib2, iclass 26, count 0 2006.252.08:05:40.68#ibcon#*after write, iclass 26, count 0 2006.252.08:05:40.68#ibcon#*before return 0, iclass 26, count 0 2006.252.08:05:40.68#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.252.08:05:40.68#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.252.08:05:40.68#ibcon#about to clear, iclass 26 cls_cnt 0 2006.252.08:05:40.68#ibcon#cleared, iclass 26 cls_cnt 0 2006.252.08:05:40.68$vc4f8/vb=1,4 2006.252.08:05:40.68#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.252.08:05:40.68#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.252.08:05:40.68#ibcon#ireg 11 cls_cnt 2 2006.252.08:05:40.68#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.252.08:05:40.68#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.252.08:05:40.68#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.252.08:05:40.68#ibcon#enter wrdev, iclass 28, count 2 2006.252.08:05:40.68#ibcon#first serial, iclass 28, count 2 2006.252.08:05:40.68#ibcon#enter sib2, iclass 28, count 2 2006.252.08:05:40.68#ibcon#flushed, iclass 28, count 2 2006.252.08:05:40.68#ibcon#about to write, iclass 28, count 2 2006.252.08:05:40.68#ibcon#wrote, iclass 28, count 2 2006.252.08:05:40.68#ibcon#about to read 3, iclass 28, count 2 2006.252.08:05:40.70#ibcon#read 3, iclass 28, count 2 2006.252.08:05:40.70#ibcon#about to read 4, iclass 28, count 2 2006.252.08:05:40.70#ibcon#read 4, iclass 28, count 2 2006.252.08:05:40.70#ibcon#about to read 5, iclass 28, count 2 2006.252.08:05:40.70#ibcon#read 5, iclass 28, count 2 2006.252.08:05:40.70#ibcon#about to read 6, iclass 28, count 2 2006.252.08:05:40.70#ibcon#read 6, iclass 28, count 2 2006.252.08:05:40.70#ibcon#end of sib2, iclass 28, count 2 2006.252.08:05:40.70#ibcon#*mode == 0, iclass 28, count 2 2006.252.08:05:40.70#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.252.08:05:40.70#ibcon#[27=AT01-04\r\n] 2006.252.08:05:40.70#ibcon#*before write, iclass 28, count 2 2006.252.08:05:40.70#ibcon#enter sib2, iclass 28, count 2 2006.252.08:05:40.70#ibcon#flushed, iclass 28, count 2 2006.252.08:05:40.70#ibcon#about to write, iclass 28, count 2 2006.252.08:05:40.70#ibcon#wrote, iclass 28, count 2 2006.252.08:05:40.70#ibcon#about to read 3, iclass 28, count 2 2006.252.08:05:40.73#ibcon#read 3, iclass 28, count 2 2006.252.08:05:40.73#ibcon#about to read 4, iclass 28, count 2 2006.252.08:05:40.73#ibcon#read 4, iclass 28, count 2 2006.252.08:05:40.73#ibcon#about to read 5, iclass 28, count 2 2006.252.08:05:40.73#ibcon#read 5, iclass 28, count 2 2006.252.08:05:40.73#ibcon#about to read 6, iclass 28, count 2 2006.252.08:05:40.73#ibcon#read 6, iclass 28, count 2 2006.252.08:05:40.73#ibcon#end of sib2, iclass 28, count 2 2006.252.08:05:40.73#ibcon#*after write, iclass 28, count 2 2006.252.08:05:40.73#ibcon#*before return 0, iclass 28, count 2 2006.252.08:05:40.73#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.252.08:05:40.73#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.252.08:05:40.73#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.252.08:05:40.73#ibcon#ireg 7 cls_cnt 0 2006.252.08:05:40.73#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.252.08:05:40.85#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.252.08:05:40.85#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.252.08:05:40.85#ibcon#enter wrdev, iclass 28, count 0 2006.252.08:05:40.85#ibcon#first serial, iclass 28, count 0 2006.252.08:05:40.85#ibcon#enter sib2, iclass 28, count 0 2006.252.08:05:40.85#ibcon#flushed, iclass 28, count 0 2006.252.08:05:40.85#ibcon#about to write, iclass 28, count 0 2006.252.08:05:40.85#ibcon#wrote, iclass 28, count 0 2006.252.08:05:40.85#ibcon#about to read 3, iclass 28, count 0 2006.252.08:05:40.87#ibcon#read 3, iclass 28, count 0 2006.252.08:05:40.87#ibcon#about to read 4, iclass 28, count 0 2006.252.08:05:40.87#ibcon#read 4, iclass 28, count 0 2006.252.08:05:40.87#ibcon#about to read 5, iclass 28, count 0 2006.252.08:05:40.87#ibcon#read 5, iclass 28, count 0 2006.252.08:05:40.87#ibcon#about to read 6, iclass 28, count 0 2006.252.08:05:40.87#ibcon#read 6, iclass 28, count 0 2006.252.08:05:40.87#ibcon#end of sib2, iclass 28, count 0 2006.252.08:05:40.87#ibcon#*mode == 0, iclass 28, count 0 2006.252.08:05:40.87#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.252.08:05:40.87#ibcon#[27=USB\r\n] 2006.252.08:05:40.87#ibcon#*before write, iclass 28, count 0 2006.252.08:05:40.87#ibcon#enter sib2, iclass 28, count 0 2006.252.08:05:40.87#ibcon#flushed, iclass 28, count 0 2006.252.08:05:40.87#ibcon#about to write, iclass 28, count 0 2006.252.08:05:40.87#ibcon#wrote, iclass 28, count 0 2006.252.08:05:40.87#ibcon#about to read 3, iclass 28, count 0 2006.252.08:05:40.90#ibcon#read 3, iclass 28, count 0 2006.252.08:05:40.90#ibcon#about to read 4, iclass 28, count 0 2006.252.08:05:40.90#ibcon#read 4, iclass 28, count 0 2006.252.08:05:40.90#ibcon#about to read 5, iclass 28, count 0 2006.252.08:05:40.90#ibcon#read 5, iclass 28, count 0 2006.252.08:05:40.90#ibcon#about to read 6, iclass 28, count 0 2006.252.08:05:40.90#ibcon#read 6, iclass 28, count 0 2006.252.08:05:40.90#ibcon#end of sib2, iclass 28, count 0 2006.252.08:05:40.90#ibcon#*after write, iclass 28, count 0 2006.252.08:05:40.90#ibcon#*before return 0, iclass 28, count 0 2006.252.08:05:40.90#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.252.08:05:40.90#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.252.08:05:40.90#ibcon#about to clear, iclass 28 cls_cnt 0 2006.252.08:05:40.90#ibcon#cleared, iclass 28 cls_cnt 0 2006.252.08:05:40.90$vc4f8/vblo=2,640.99 2006.252.08:05:40.90#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.252.08:05:40.90#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.252.08:05:40.90#ibcon#ireg 17 cls_cnt 0 2006.252.08:05:40.90#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.252.08:05:40.90#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.252.08:05:40.90#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.252.08:05:40.90#ibcon#enter wrdev, iclass 30, count 0 2006.252.08:05:40.90#ibcon#first serial, iclass 30, count 0 2006.252.08:05:40.90#ibcon#enter sib2, iclass 30, count 0 2006.252.08:05:40.90#ibcon#flushed, iclass 30, count 0 2006.252.08:05:40.90#ibcon#about to write, iclass 30, count 0 2006.252.08:05:40.90#ibcon#wrote, iclass 30, count 0 2006.252.08:05:40.90#ibcon#about to read 3, iclass 30, count 0 2006.252.08:05:40.92#ibcon#read 3, iclass 30, count 0 2006.252.08:05:40.92#ibcon#about to read 4, iclass 30, count 0 2006.252.08:05:40.92#ibcon#read 4, iclass 30, count 0 2006.252.08:05:40.92#ibcon#about to read 5, iclass 30, count 0 2006.252.08:05:40.92#ibcon#read 5, iclass 30, count 0 2006.252.08:05:40.92#ibcon#about to read 6, iclass 30, count 0 2006.252.08:05:40.92#ibcon#read 6, iclass 30, count 0 2006.252.08:05:40.92#ibcon#end of sib2, iclass 30, count 0 2006.252.08:05:40.92#ibcon#*mode == 0, iclass 30, count 0 2006.252.08:05:40.92#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.252.08:05:40.92#ibcon#[28=FRQ=02,640.99\r\n] 2006.252.08:05:40.92#ibcon#*before write, iclass 30, count 0 2006.252.08:05:40.92#ibcon#enter sib2, iclass 30, count 0 2006.252.08:05:40.92#ibcon#flushed, iclass 30, count 0 2006.252.08:05:40.92#ibcon#about to write, iclass 30, count 0 2006.252.08:05:40.92#ibcon#wrote, iclass 30, count 0 2006.252.08:05:40.92#ibcon#about to read 3, iclass 30, count 0 2006.252.08:05:40.96#ibcon#read 3, iclass 30, count 0 2006.252.08:05:40.96#ibcon#about to read 4, iclass 30, count 0 2006.252.08:05:40.96#ibcon#read 4, iclass 30, count 0 2006.252.08:05:40.96#ibcon#about to read 5, iclass 30, count 0 2006.252.08:05:40.96#ibcon#read 5, iclass 30, count 0 2006.252.08:05:40.96#ibcon#about to read 6, iclass 30, count 0 2006.252.08:05:40.96#ibcon#read 6, iclass 30, count 0 2006.252.08:05:40.96#ibcon#end of sib2, iclass 30, count 0 2006.252.08:05:40.96#ibcon#*after write, iclass 30, count 0 2006.252.08:05:40.96#ibcon#*before return 0, iclass 30, count 0 2006.252.08:05:40.96#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.252.08:05:40.96#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.252.08:05:40.96#ibcon#about to clear, iclass 30 cls_cnt 0 2006.252.08:05:40.96#ibcon#cleared, iclass 30 cls_cnt 0 2006.252.08:05:40.96$vc4f8/vb=2,5 2006.252.08:05:40.96#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.252.08:05:40.96#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.252.08:05:40.96#ibcon#ireg 11 cls_cnt 2 2006.252.08:05:40.96#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.252.08:05:41.02#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.252.08:05:41.02#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.252.08:05:41.02#ibcon#enter wrdev, iclass 32, count 2 2006.252.08:05:41.02#ibcon#first serial, iclass 32, count 2 2006.252.08:05:41.02#ibcon#enter sib2, iclass 32, count 2 2006.252.08:05:41.02#ibcon#flushed, iclass 32, count 2 2006.252.08:05:41.02#ibcon#about to write, iclass 32, count 2 2006.252.08:05:41.02#ibcon#wrote, iclass 32, count 2 2006.252.08:05:41.02#ibcon#about to read 3, iclass 32, count 2 2006.252.08:05:41.04#ibcon#read 3, iclass 32, count 2 2006.252.08:05:41.04#ibcon#about to read 4, iclass 32, count 2 2006.252.08:05:41.04#ibcon#read 4, iclass 32, count 2 2006.252.08:05:41.04#ibcon#about to read 5, iclass 32, count 2 2006.252.08:05:41.04#ibcon#read 5, iclass 32, count 2 2006.252.08:05:41.04#ibcon#about to read 6, iclass 32, count 2 2006.252.08:05:41.04#ibcon#read 6, iclass 32, count 2 2006.252.08:05:41.04#ibcon#end of sib2, iclass 32, count 2 2006.252.08:05:41.04#ibcon#*mode == 0, iclass 32, count 2 2006.252.08:05:41.04#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.252.08:05:41.04#ibcon#[27=AT02-05\r\n] 2006.252.08:05:41.04#ibcon#*before write, iclass 32, count 2 2006.252.08:05:41.04#ibcon#enter sib2, iclass 32, count 2 2006.252.08:05:41.04#ibcon#flushed, iclass 32, count 2 2006.252.08:05:41.04#ibcon#about to write, iclass 32, count 2 2006.252.08:05:41.04#ibcon#wrote, iclass 32, count 2 2006.252.08:05:41.04#ibcon#about to read 3, iclass 32, count 2 2006.252.08:05:41.07#ibcon#read 3, iclass 32, count 2 2006.252.08:05:41.07#ibcon#about to read 4, iclass 32, count 2 2006.252.08:05:41.07#ibcon#read 4, iclass 32, count 2 2006.252.08:05:41.07#ibcon#about to read 5, iclass 32, count 2 2006.252.08:05:41.07#ibcon#read 5, iclass 32, count 2 2006.252.08:05:41.07#ibcon#about to read 6, iclass 32, count 2 2006.252.08:05:41.07#ibcon#read 6, iclass 32, count 2 2006.252.08:05:41.07#ibcon#end of sib2, iclass 32, count 2 2006.252.08:05:41.07#ibcon#*after write, iclass 32, count 2 2006.252.08:05:41.07#ibcon#*before return 0, iclass 32, count 2 2006.252.08:05:41.07#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.252.08:05:41.07#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.252.08:05:41.07#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.252.08:05:41.07#ibcon#ireg 7 cls_cnt 0 2006.252.08:05:41.07#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.252.08:05:41.19#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.252.08:05:41.19#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.252.08:05:41.19#ibcon#enter wrdev, iclass 32, count 0 2006.252.08:05:41.19#ibcon#first serial, iclass 32, count 0 2006.252.08:05:41.19#ibcon#enter sib2, iclass 32, count 0 2006.252.08:05:41.19#ibcon#flushed, iclass 32, count 0 2006.252.08:05:41.19#ibcon#about to write, iclass 32, count 0 2006.252.08:05:41.19#ibcon#wrote, iclass 32, count 0 2006.252.08:05:41.19#ibcon#about to read 3, iclass 32, count 0 2006.252.08:05:41.22#ibcon#read 3, iclass 32, count 0 2006.252.08:05:41.22#ibcon#about to read 4, iclass 32, count 0 2006.252.08:05:41.22#ibcon#read 4, iclass 32, count 0 2006.252.08:05:41.22#ibcon#about to read 5, iclass 32, count 0 2006.252.08:05:41.22#ibcon#read 5, iclass 32, count 0 2006.252.08:05:41.22#ibcon#about to read 6, iclass 32, count 0 2006.252.08:05:41.22#ibcon#read 6, iclass 32, count 0 2006.252.08:05:41.22#ibcon#end of sib2, iclass 32, count 0 2006.252.08:05:41.22#ibcon#*mode == 0, iclass 32, count 0 2006.252.08:05:41.22#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.252.08:05:41.22#ibcon#[27=USB\r\n] 2006.252.08:05:41.22#ibcon#*before write, iclass 32, count 0 2006.252.08:05:41.22#ibcon#enter sib2, iclass 32, count 0 2006.252.08:05:41.22#ibcon#flushed, iclass 32, count 0 2006.252.08:05:41.22#ibcon#about to write, iclass 32, count 0 2006.252.08:05:41.22#ibcon#wrote, iclass 32, count 0 2006.252.08:05:41.22#ibcon#about to read 3, iclass 32, count 0 2006.252.08:05:41.25#ibcon#read 3, iclass 32, count 0 2006.252.08:05:41.25#ibcon#about to read 4, iclass 32, count 0 2006.252.08:05:41.25#ibcon#read 4, iclass 32, count 0 2006.252.08:05:41.25#ibcon#about to read 5, iclass 32, count 0 2006.252.08:05:41.25#ibcon#read 5, iclass 32, count 0 2006.252.08:05:41.25#ibcon#about to read 6, iclass 32, count 0 2006.252.08:05:41.25#ibcon#read 6, iclass 32, count 0 2006.252.08:05:41.25#ibcon#end of sib2, iclass 32, count 0 2006.252.08:05:41.25#ibcon#*after write, iclass 32, count 0 2006.252.08:05:41.25#ibcon#*before return 0, iclass 32, count 0 2006.252.08:05:41.25#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.252.08:05:41.25#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.252.08:05:41.25#ibcon#about to clear, iclass 32 cls_cnt 0 2006.252.08:05:41.25#ibcon#cleared, iclass 32 cls_cnt 0 2006.252.08:05:41.25$vc4f8/vblo=3,656.99 2006.252.08:05:41.25#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.252.08:05:41.25#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.252.08:05:41.25#ibcon#ireg 17 cls_cnt 0 2006.252.08:05:41.25#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.252.08:05:41.25#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.252.08:05:41.25#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.252.08:05:41.25#ibcon#enter wrdev, iclass 34, count 0 2006.252.08:05:41.25#ibcon#first serial, iclass 34, count 0 2006.252.08:05:41.25#ibcon#enter sib2, iclass 34, count 0 2006.252.08:05:41.25#ibcon#flushed, iclass 34, count 0 2006.252.08:05:41.25#ibcon#about to write, iclass 34, count 0 2006.252.08:05:41.25#ibcon#wrote, iclass 34, count 0 2006.252.08:05:41.25#ibcon#about to read 3, iclass 34, count 0 2006.252.08:05:41.27#ibcon#read 3, iclass 34, count 0 2006.252.08:05:41.27#ibcon#about to read 4, iclass 34, count 0 2006.252.08:05:41.27#ibcon#read 4, iclass 34, count 0 2006.252.08:05:41.27#ibcon#about to read 5, iclass 34, count 0 2006.252.08:05:41.27#ibcon#read 5, iclass 34, count 0 2006.252.08:05:41.27#ibcon#about to read 6, iclass 34, count 0 2006.252.08:05:41.27#ibcon#read 6, iclass 34, count 0 2006.252.08:05:41.27#ibcon#end of sib2, iclass 34, count 0 2006.252.08:05:41.27#ibcon#*mode == 0, iclass 34, count 0 2006.252.08:05:41.27#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.252.08:05:41.27#ibcon#[28=FRQ=03,656.99\r\n] 2006.252.08:05:41.27#ibcon#*before write, iclass 34, count 0 2006.252.08:05:41.27#ibcon#enter sib2, iclass 34, count 0 2006.252.08:05:41.27#ibcon#flushed, iclass 34, count 0 2006.252.08:05:41.27#ibcon#about to write, iclass 34, count 0 2006.252.08:05:41.27#ibcon#wrote, iclass 34, count 0 2006.252.08:05:41.27#ibcon#about to read 3, iclass 34, count 0 2006.252.08:05:41.31#ibcon#read 3, iclass 34, count 0 2006.252.08:05:41.31#ibcon#about to read 4, iclass 34, count 0 2006.252.08:05:41.31#ibcon#read 4, iclass 34, count 0 2006.252.08:05:41.31#ibcon#about to read 5, iclass 34, count 0 2006.252.08:05:41.31#ibcon#read 5, iclass 34, count 0 2006.252.08:05:41.31#ibcon#about to read 6, iclass 34, count 0 2006.252.08:05:41.31#ibcon#read 6, iclass 34, count 0 2006.252.08:05:41.31#ibcon#end of sib2, iclass 34, count 0 2006.252.08:05:41.31#ibcon#*after write, iclass 34, count 0 2006.252.08:05:41.31#ibcon#*before return 0, iclass 34, count 0 2006.252.08:05:41.31#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.252.08:05:41.31#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.252.08:05:41.31#ibcon#about to clear, iclass 34 cls_cnt 0 2006.252.08:05:41.31#ibcon#cleared, iclass 34 cls_cnt 0 2006.252.08:05:41.31$vc4f8/vb=3,4 2006.252.08:05:41.31#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.252.08:05:41.31#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.252.08:05:41.31#ibcon#ireg 11 cls_cnt 2 2006.252.08:05:41.31#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.252.08:05:41.37#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.252.08:05:41.37#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.252.08:05:41.37#ibcon#enter wrdev, iclass 36, count 2 2006.252.08:05:41.37#ibcon#first serial, iclass 36, count 2 2006.252.08:05:41.37#ibcon#enter sib2, iclass 36, count 2 2006.252.08:05:41.37#ibcon#flushed, iclass 36, count 2 2006.252.08:05:41.37#ibcon#about to write, iclass 36, count 2 2006.252.08:05:41.37#ibcon#wrote, iclass 36, count 2 2006.252.08:05:41.37#ibcon#about to read 3, iclass 36, count 2 2006.252.08:05:41.39#ibcon#read 3, iclass 36, count 2 2006.252.08:05:41.39#ibcon#about to read 4, iclass 36, count 2 2006.252.08:05:41.39#ibcon#read 4, iclass 36, count 2 2006.252.08:05:41.39#ibcon#about to read 5, iclass 36, count 2 2006.252.08:05:41.39#ibcon#read 5, iclass 36, count 2 2006.252.08:05:41.39#ibcon#about to read 6, iclass 36, count 2 2006.252.08:05:41.39#ibcon#read 6, iclass 36, count 2 2006.252.08:05:41.39#ibcon#end of sib2, iclass 36, count 2 2006.252.08:05:41.39#ibcon#*mode == 0, iclass 36, count 2 2006.252.08:05:41.39#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.252.08:05:41.39#ibcon#[27=AT03-04\r\n] 2006.252.08:05:41.39#ibcon#*before write, iclass 36, count 2 2006.252.08:05:41.39#ibcon#enter sib2, iclass 36, count 2 2006.252.08:05:41.39#ibcon#flushed, iclass 36, count 2 2006.252.08:05:41.39#ibcon#about to write, iclass 36, count 2 2006.252.08:05:41.39#ibcon#wrote, iclass 36, count 2 2006.252.08:05:41.39#ibcon#about to read 3, iclass 36, count 2 2006.252.08:05:41.42#ibcon#read 3, iclass 36, count 2 2006.252.08:05:41.42#ibcon#about to read 4, iclass 36, count 2 2006.252.08:05:41.42#ibcon#read 4, iclass 36, count 2 2006.252.08:05:41.42#ibcon#about to read 5, iclass 36, count 2 2006.252.08:05:41.42#ibcon#read 5, iclass 36, count 2 2006.252.08:05:41.42#ibcon#about to read 6, iclass 36, count 2 2006.252.08:05:41.42#ibcon#read 6, iclass 36, count 2 2006.252.08:05:41.42#ibcon#end of sib2, iclass 36, count 2 2006.252.08:05:41.42#ibcon#*after write, iclass 36, count 2 2006.252.08:05:41.42#ibcon#*before return 0, iclass 36, count 2 2006.252.08:05:41.42#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.252.08:05:41.42#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.252.08:05:41.42#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.252.08:05:41.42#ibcon#ireg 7 cls_cnt 0 2006.252.08:05:41.42#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.252.08:05:41.54#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.252.08:05:41.54#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.252.08:05:41.54#ibcon#enter wrdev, iclass 36, count 0 2006.252.08:05:41.54#ibcon#first serial, iclass 36, count 0 2006.252.08:05:41.54#ibcon#enter sib2, iclass 36, count 0 2006.252.08:05:41.54#ibcon#flushed, iclass 36, count 0 2006.252.08:05:41.54#ibcon#about to write, iclass 36, count 0 2006.252.08:05:41.54#ibcon#wrote, iclass 36, count 0 2006.252.08:05:41.54#ibcon#about to read 3, iclass 36, count 0 2006.252.08:05:41.56#ibcon#read 3, iclass 36, count 0 2006.252.08:05:41.56#ibcon#about to read 4, iclass 36, count 0 2006.252.08:05:41.56#ibcon#read 4, iclass 36, count 0 2006.252.08:05:41.56#ibcon#about to read 5, iclass 36, count 0 2006.252.08:05:41.56#ibcon#read 5, iclass 36, count 0 2006.252.08:05:41.56#ibcon#about to read 6, iclass 36, count 0 2006.252.08:05:41.56#ibcon#read 6, iclass 36, count 0 2006.252.08:05:41.56#ibcon#end of sib2, iclass 36, count 0 2006.252.08:05:41.56#ibcon#*mode == 0, iclass 36, count 0 2006.252.08:05:41.56#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.252.08:05:41.56#ibcon#[27=USB\r\n] 2006.252.08:05:41.56#ibcon#*before write, iclass 36, count 0 2006.252.08:05:41.56#ibcon#enter sib2, iclass 36, count 0 2006.252.08:05:41.56#ibcon#flushed, iclass 36, count 0 2006.252.08:05:41.56#ibcon#about to write, iclass 36, count 0 2006.252.08:05:41.56#ibcon#wrote, iclass 36, count 0 2006.252.08:05:41.56#ibcon#about to read 3, iclass 36, count 0 2006.252.08:05:41.59#ibcon#read 3, iclass 36, count 0 2006.252.08:05:41.59#ibcon#about to read 4, iclass 36, count 0 2006.252.08:05:41.59#ibcon#read 4, iclass 36, count 0 2006.252.08:05:41.59#ibcon#about to read 5, iclass 36, count 0 2006.252.08:05:41.59#ibcon#read 5, iclass 36, count 0 2006.252.08:05:41.59#ibcon#about to read 6, iclass 36, count 0 2006.252.08:05:41.59#ibcon#read 6, iclass 36, count 0 2006.252.08:05:41.59#ibcon#end of sib2, iclass 36, count 0 2006.252.08:05:41.59#ibcon#*after write, iclass 36, count 0 2006.252.08:05:41.59#ibcon#*before return 0, iclass 36, count 0 2006.252.08:05:41.59#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.252.08:05:41.59#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.252.08:05:41.59#ibcon#about to clear, iclass 36 cls_cnt 0 2006.252.08:05:41.59#ibcon#cleared, iclass 36 cls_cnt 0 2006.252.08:05:41.59$vc4f8/vblo=4,712.99 2006.252.08:05:41.59#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.252.08:05:41.59#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.252.08:05:41.59#ibcon#ireg 17 cls_cnt 0 2006.252.08:05:41.59#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.252.08:05:41.59#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.252.08:05:41.59#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.252.08:05:41.59#ibcon#enter wrdev, iclass 38, count 0 2006.252.08:05:41.59#ibcon#first serial, iclass 38, count 0 2006.252.08:05:41.59#ibcon#enter sib2, iclass 38, count 0 2006.252.08:05:41.59#ibcon#flushed, iclass 38, count 0 2006.252.08:05:41.59#ibcon#about to write, iclass 38, count 0 2006.252.08:05:41.59#ibcon#wrote, iclass 38, count 0 2006.252.08:05:41.59#ibcon#about to read 3, iclass 38, count 0 2006.252.08:05:41.61#ibcon#read 3, iclass 38, count 0 2006.252.08:05:41.61#ibcon#about to read 4, iclass 38, count 0 2006.252.08:05:41.61#ibcon#read 4, iclass 38, count 0 2006.252.08:05:41.61#ibcon#about to read 5, iclass 38, count 0 2006.252.08:05:41.61#ibcon#read 5, iclass 38, count 0 2006.252.08:05:41.61#ibcon#about to read 6, iclass 38, count 0 2006.252.08:05:41.61#ibcon#read 6, iclass 38, count 0 2006.252.08:05:41.61#ibcon#end of sib2, iclass 38, count 0 2006.252.08:05:41.61#ibcon#*mode == 0, iclass 38, count 0 2006.252.08:05:41.61#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.252.08:05:41.61#ibcon#[28=FRQ=04,712.99\r\n] 2006.252.08:05:41.61#ibcon#*before write, iclass 38, count 0 2006.252.08:05:41.61#ibcon#enter sib2, iclass 38, count 0 2006.252.08:05:41.61#ibcon#flushed, iclass 38, count 0 2006.252.08:05:41.61#ibcon#about to write, iclass 38, count 0 2006.252.08:05:41.61#ibcon#wrote, iclass 38, count 0 2006.252.08:05:41.61#ibcon#about to read 3, iclass 38, count 0 2006.252.08:05:41.65#ibcon#read 3, iclass 38, count 0 2006.252.08:05:41.65#ibcon#about to read 4, iclass 38, count 0 2006.252.08:05:41.65#ibcon#read 4, iclass 38, count 0 2006.252.08:05:41.65#ibcon#about to read 5, iclass 38, count 0 2006.252.08:05:41.65#ibcon#read 5, iclass 38, count 0 2006.252.08:05:41.65#ibcon#about to read 6, iclass 38, count 0 2006.252.08:05:41.65#ibcon#read 6, iclass 38, count 0 2006.252.08:05:41.65#ibcon#end of sib2, iclass 38, count 0 2006.252.08:05:41.65#ibcon#*after write, iclass 38, count 0 2006.252.08:05:41.65#ibcon#*before return 0, iclass 38, count 0 2006.252.08:05:41.65#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.252.08:05:41.65#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.252.08:05:41.65#ibcon#about to clear, iclass 38 cls_cnt 0 2006.252.08:05:41.65#ibcon#cleared, iclass 38 cls_cnt 0 2006.252.08:05:41.65$vc4f8/vb=4,4 2006.252.08:05:41.65#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.252.08:05:41.65#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.252.08:05:41.65#ibcon#ireg 11 cls_cnt 2 2006.252.08:05:41.65#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.252.08:05:41.71#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.252.08:05:41.71#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.252.08:05:41.71#ibcon#enter wrdev, iclass 40, count 2 2006.252.08:05:41.71#ibcon#first serial, iclass 40, count 2 2006.252.08:05:41.71#ibcon#enter sib2, iclass 40, count 2 2006.252.08:05:41.71#ibcon#flushed, iclass 40, count 2 2006.252.08:05:41.71#ibcon#about to write, iclass 40, count 2 2006.252.08:05:41.71#ibcon#wrote, iclass 40, count 2 2006.252.08:05:41.71#ibcon#about to read 3, iclass 40, count 2 2006.252.08:05:41.73#ibcon#read 3, iclass 40, count 2 2006.252.08:05:41.73#ibcon#about to read 4, iclass 40, count 2 2006.252.08:05:41.73#ibcon#read 4, iclass 40, count 2 2006.252.08:05:41.73#ibcon#about to read 5, iclass 40, count 2 2006.252.08:05:41.73#ibcon#read 5, iclass 40, count 2 2006.252.08:05:41.73#ibcon#about to read 6, iclass 40, count 2 2006.252.08:05:41.73#ibcon#read 6, iclass 40, count 2 2006.252.08:05:41.73#ibcon#end of sib2, iclass 40, count 2 2006.252.08:05:41.73#ibcon#*mode == 0, iclass 40, count 2 2006.252.08:05:41.73#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.252.08:05:41.73#ibcon#[27=AT04-04\r\n] 2006.252.08:05:41.73#ibcon#*before write, iclass 40, count 2 2006.252.08:05:41.73#ibcon#enter sib2, iclass 40, count 2 2006.252.08:05:41.73#ibcon#flushed, iclass 40, count 2 2006.252.08:05:41.73#ibcon#about to write, iclass 40, count 2 2006.252.08:05:41.73#ibcon#wrote, iclass 40, count 2 2006.252.08:05:41.73#ibcon#about to read 3, iclass 40, count 2 2006.252.08:05:41.76#ibcon#read 3, iclass 40, count 2 2006.252.08:05:41.76#ibcon#about to read 4, iclass 40, count 2 2006.252.08:05:41.76#ibcon#read 4, iclass 40, count 2 2006.252.08:05:41.76#ibcon#about to read 5, iclass 40, count 2 2006.252.08:05:41.76#ibcon#read 5, iclass 40, count 2 2006.252.08:05:41.76#ibcon#about to read 6, iclass 40, count 2 2006.252.08:05:41.76#ibcon#read 6, iclass 40, count 2 2006.252.08:05:41.76#ibcon#end of sib2, iclass 40, count 2 2006.252.08:05:41.76#ibcon#*after write, iclass 40, count 2 2006.252.08:05:41.76#ibcon#*before return 0, iclass 40, count 2 2006.252.08:05:41.76#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.252.08:05:41.76#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.252.08:05:41.76#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.252.08:05:41.76#ibcon#ireg 7 cls_cnt 0 2006.252.08:05:41.76#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.252.08:05:41.88#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.252.08:05:41.88#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.252.08:05:41.88#ibcon#enter wrdev, iclass 40, count 0 2006.252.08:05:41.88#ibcon#first serial, iclass 40, count 0 2006.252.08:05:41.88#ibcon#enter sib2, iclass 40, count 0 2006.252.08:05:41.88#ibcon#flushed, iclass 40, count 0 2006.252.08:05:41.88#ibcon#about to write, iclass 40, count 0 2006.252.08:05:41.88#ibcon#wrote, iclass 40, count 0 2006.252.08:05:41.88#ibcon#about to read 3, iclass 40, count 0 2006.252.08:05:41.90#ibcon#read 3, iclass 40, count 0 2006.252.08:05:41.90#ibcon#about to read 4, iclass 40, count 0 2006.252.08:05:41.90#ibcon#read 4, iclass 40, count 0 2006.252.08:05:41.90#ibcon#about to read 5, iclass 40, count 0 2006.252.08:05:41.90#ibcon#read 5, iclass 40, count 0 2006.252.08:05:41.90#ibcon#about to read 6, iclass 40, count 0 2006.252.08:05:41.90#ibcon#read 6, iclass 40, count 0 2006.252.08:05:41.90#ibcon#end of sib2, iclass 40, count 0 2006.252.08:05:41.90#ibcon#*mode == 0, iclass 40, count 0 2006.252.08:05:41.90#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.252.08:05:41.90#ibcon#[27=USB\r\n] 2006.252.08:05:41.90#ibcon#*before write, iclass 40, count 0 2006.252.08:05:41.90#ibcon#enter sib2, iclass 40, count 0 2006.252.08:05:41.90#ibcon#flushed, iclass 40, count 0 2006.252.08:05:41.90#ibcon#about to write, iclass 40, count 0 2006.252.08:05:41.90#ibcon#wrote, iclass 40, count 0 2006.252.08:05:41.90#ibcon#about to read 3, iclass 40, count 0 2006.252.08:05:41.93#ibcon#read 3, iclass 40, count 0 2006.252.08:05:41.93#ibcon#about to read 4, iclass 40, count 0 2006.252.08:05:41.93#ibcon#read 4, iclass 40, count 0 2006.252.08:05:41.93#ibcon#about to read 5, iclass 40, count 0 2006.252.08:05:41.93#ibcon#read 5, iclass 40, count 0 2006.252.08:05:41.93#ibcon#about to read 6, iclass 40, count 0 2006.252.08:05:41.93#ibcon#read 6, iclass 40, count 0 2006.252.08:05:41.93#ibcon#end of sib2, iclass 40, count 0 2006.252.08:05:41.93#ibcon#*after write, iclass 40, count 0 2006.252.08:05:41.93#ibcon#*before return 0, iclass 40, count 0 2006.252.08:05:41.93#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.252.08:05:41.93#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.252.08:05:41.93#ibcon#about to clear, iclass 40 cls_cnt 0 2006.252.08:05:41.93#ibcon#cleared, iclass 40 cls_cnt 0 2006.252.08:05:41.93$vc4f8/vblo=5,744.99 2006.252.08:05:41.93#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.252.08:05:41.93#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.252.08:05:41.93#ibcon#ireg 17 cls_cnt 0 2006.252.08:05:41.93#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.252.08:05:41.93#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.252.08:05:41.93#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.252.08:05:41.93#ibcon#enter wrdev, iclass 4, count 0 2006.252.08:05:41.93#ibcon#first serial, iclass 4, count 0 2006.252.08:05:41.93#ibcon#enter sib2, iclass 4, count 0 2006.252.08:05:41.93#ibcon#flushed, iclass 4, count 0 2006.252.08:05:41.93#ibcon#about to write, iclass 4, count 0 2006.252.08:05:41.93#ibcon#wrote, iclass 4, count 0 2006.252.08:05:41.93#ibcon#about to read 3, iclass 4, count 0 2006.252.08:05:41.95#ibcon#read 3, iclass 4, count 0 2006.252.08:05:41.95#ibcon#about to read 4, iclass 4, count 0 2006.252.08:05:41.95#ibcon#read 4, iclass 4, count 0 2006.252.08:05:41.95#ibcon#about to read 5, iclass 4, count 0 2006.252.08:05:41.95#ibcon#read 5, iclass 4, count 0 2006.252.08:05:41.95#ibcon#about to read 6, iclass 4, count 0 2006.252.08:05:41.95#ibcon#read 6, iclass 4, count 0 2006.252.08:05:41.95#ibcon#end of sib2, iclass 4, count 0 2006.252.08:05:41.95#ibcon#*mode == 0, iclass 4, count 0 2006.252.08:05:41.95#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.252.08:05:41.95#ibcon#[28=FRQ=05,744.99\r\n] 2006.252.08:05:41.95#ibcon#*before write, iclass 4, count 0 2006.252.08:05:41.95#ibcon#enter sib2, iclass 4, count 0 2006.252.08:05:41.95#ibcon#flushed, iclass 4, count 0 2006.252.08:05:41.95#ibcon#about to write, iclass 4, count 0 2006.252.08:05:41.95#ibcon#wrote, iclass 4, count 0 2006.252.08:05:41.95#ibcon#about to read 3, iclass 4, count 0 2006.252.08:05:41.99#ibcon#read 3, iclass 4, count 0 2006.252.08:05:41.99#ibcon#about to read 4, iclass 4, count 0 2006.252.08:05:41.99#ibcon#read 4, iclass 4, count 0 2006.252.08:05:41.99#ibcon#about to read 5, iclass 4, count 0 2006.252.08:05:41.99#ibcon#read 5, iclass 4, count 0 2006.252.08:05:41.99#ibcon#about to read 6, iclass 4, count 0 2006.252.08:05:41.99#ibcon#read 6, iclass 4, count 0 2006.252.08:05:41.99#ibcon#end of sib2, iclass 4, count 0 2006.252.08:05:41.99#ibcon#*after write, iclass 4, count 0 2006.252.08:05:41.99#ibcon#*before return 0, iclass 4, count 0 2006.252.08:05:41.99#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.252.08:05:41.99#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.252.08:05:41.99#ibcon#about to clear, iclass 4 cls_cnt 0 2006.252.08:05:41.99#ibcon#cleared, iclass 4 cls_cnt 0 2006.252.08:05:41.99$vc4f8/vb=5,4 2006.252.08:05:41.99#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.252.08:05:41.99#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.252.08:05:41.99#ibcon#ireg 11 cls_cnt 2 2006.252.08:05:41.99#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.252.08:05:42.05#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.252.08:05:42.05#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.252.08:05:42.05#ibcon#enter wrdev, iclass 6, count 2 2006.252.08:05:42.05#ibcon#first serial, iclass 6, count 2 2006.252.08:05:42.05#ibcon#enter sib2, iclass 6, count 2 2006.252.08:05:42.05#ibcon#flushed, iclass 6, count 2 2006.252.08:05:42.05#ibcon#about to write, iclass 6, count 2 2006.252.08:05:42.05#ibcon#wrote, iclass 6, count 2 2006.252.08:05:42.05#ibcon#about to read 3, iclass 6, count 2 2006.252.08:05:42.07#ibcon#read 3, iclass 6, count 2 2006.252.08:05:42.07#ibcon#about to read 4, iclass 6, count 2 2006.252.08:05:42.07#ibcon#read 4, iclass 6, count 2 2006.252.08:05:42.07#ibcon#about to read 5, iclass 6, count 2 2006.252.08:05:42.07#ibcon#read 5, iclass 6, count 2 2006.252.08:05:42.07#ibcon#about to read 6, iclass 6, count 2 2006.252.08:05:42.07#ibcon#read 6, iclass 6, count 2 2006.252.08:05:42.07#ibcon#end of sib2, iclass 6, count 2 2006.252.08:05:42.07#ibcon#*mode == 0, iclass 6, count 2 2006.252.08:05:42.07#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.252.08:05:42.07#ibcon#[27=AT05-04\r\n] 2006.252.08:05:42.07#ibcon#*before write, iclass 6, count 2 2006.252.08:05:42.07#ibcon#enter sib2, iclass 6, count 2 2006.252.08:05:42.07#ibcon#flushed, iclass 6, count 2 2006.252.08:05:42.07#ibcon#about to write, iclass 6, count 2 2006.252.08:05:42.07#ibcon#wrote, iclass 6, count 2 2006.252.08:05:42.07#ibcon#about to read 3, iclass 6, count 2 2006.252.08:05:42.10#ibcon#read 3, iclass 6, count 2 2006.252.08:05:42.10#ibcon#about to read 4, iclass 6, count 2 2006.252.08:05:42.10#ibcon#read 4, iclass 6, count 2 2006.252.08:05:42.10#ibcon#about to read 5, iclass 6, count 2 2006.252.08:05:42.10#ibcon#read 5, iclass 6, count 2 2006.252.08:05:42.10#ibcon#about to read 6, iclass 6, count 2 2006.252.08:05:42.10#ibcon#read 6, iclass 6, count 2 2006.252.08:05:42.10#ibcon#end of sib2, iclass 6, count 2 2006.252.08:05:42.10#ibcon#*after write, iclass 6, count 2 2006.252.08:05:42.10#ibcon#*before return 0, iclass 6, count 2 2006.252.08:05:42.10#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.252.08:05:42.10#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.252.08:05:42.10#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.252.08:05:42.10#ibcon#ireg 7 cls_cnt 0 2006.252.08:05:42.10#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.252.08:05:42.17#abcon#<5=/05 3.4 6.0 27.33 901011.1\r\n> 2006.252.08:05:42.19#abcon#{5=INTERFACE CLEAR} 2006.252.08:05:42.22#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.252.08:05:42.22#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.252.08:05:42.22#ibcon#enter wrdev, iclass 6, count 0 2006.252.08:05:42.22#ibcon#first serial, iclass 6, count 0 2006.252.08:05:42.22#ibcon#enter sib2, iclass 6, count 0 2006.252.08:05:42.22#ibcon#flushed, iclass 6, count 0 2006.252.08:05:42.22#ibcon#about to write, iclass 6, count 0 2006.252.08:05:42.22#ibcon#wrote, iclass 6, count 0 2006.252.08:05:42.22#ibcon#about to read 3, iclass 6, count 0 2006.252.08:05:42.24#ibcon#read 3, iclass 6, count 0 2006.252.08:05:42.24#ibcon#about to read 4, iclass 6, count 0 2006.252.08:05:42.24#ibcon#read 4, iclass 6, count 0 2006.252.08:05:42.24#ibcon#about to read 5, iclass 6, count 0 2006.252.08:05:42.24#ibcon#read 5, iclass 6, count 0 2006.252.08:05:42.24#ibcon#about to read 6, iclass 6, count 0 2006.252.08:05:42.24#ibcon#read 6, iclass 6, count 0 2006.252.08:05:42.24#ibcon#end of sib2, iclass 6, count 0 2006.252.08:05:42.24#ibcon#*mode == 0, iclass 6, count 0 2006.252.08:05:42.24#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.252.08:05:42.24#ibcon#[27=USB\r\n] 2006.252.08:05:42.24#ibcon#*before write, iclass 6, count 0 2006.252.08:05:42.24#ibcon#enter sib2, iclass 6, count 0 2006.252.08:05:42.24#ibcon#flushed, iclass 6, count 0 2006.252.08:05:42.24#ibcon#about to write, iclass 6, count 0 2006.252.08:05:42.24#ibcon#wrote, iclass 6, count 0 2006.252.08:05:42.24#ibcon#about to read 3, iclass 6, count 0 2006.252.08:05:42.25#abcon#[5=S1D000X0/0*\r\n] 2006.252.08:05:42.27#ibcon#read 3, iclass 6, count 0 2006.252.08:05:42.27#ibcon#about to read 4, iclass 6, count 0 2006.252.08:05:42.27#ibcon#read 4, iclass 6, count 0 2006.252.08:05:42.27#ibcon#about to read 5, iclass 6, count 0 2006.252.08:05:42.27#ibcon#read 5, iclass 6, count 0 2006.252.08:05:42.27#ibcon#about to read 6, iclass 6, count 0 2006.252.08:05:42.27#ibcon#read 6, iclass 6, count 0 2006.252.08:05:42.27#ibcon#end of sib2, iclass 6, count 0 2006.252.08:05:42.27#ibcon#*after write, iclass 6, count 0 2006.252.08:05:42.27#ibcon#*before return 0, iclass 6, count 0 2006.252.08:05:42.27#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.252.08:05:42.27#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.252.08:05:42.27#ibcon#about to clear, iclass 6 cls_cnt 0 2006.252.08:05:42.27#ibcon#cleared, iclass 6 cls_cnt 0 2006.252.08:05:42.27$vc4f8/vblo=6,752.99 2006.252.08:05:42.27#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.252.08:05:42.27#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.252.08:05:42.27#ibcon#ireg 17 cls_cnt 0 2006.252.08:05:42.27#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.252.08:05:42.27#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.252.08:05:42.27#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.252.08:05:42.27#ibcon#enter wrdev, iclass 14, count 0 2006.252.08:05:42.27#ibcon#first serial, iclass 14, count 0 2006.252.08:05:42.27#ibcon#enter sib2, iclass 14, count 0 2006.252.08:05:42.27#ibcon#flushed, iclass 14, count 0 2006.252.08:05:42.27#ibcon#about to write, iclass 14, count 0 2006.252.08:05:42.27#ibcon#wrote, iclass 14, count 0 2006.252.08:05:42.27#ibcon#about to read 3, iclass 14, count 0 2006.252.08:05:42.29#ibcon#read 3, iclass 14, count 0 2006.252.08:05:42.29#ibcon#about to read 4, iclass 14, count 0 2006.252.08:05:42.29#ibcon#read 4, iclass 14, count 0 2006.252.08:05:42.29#ibcon#about to read 5, iclass 14, count 0 2006.252.08:05:42.29#ibcon#read 5, iclass 14, count 0 2006.252.08:05:42.29#ibcon#about to read 6, iclass 14, count 0 2006.252.08:05:42.29#ibcon#read 6, iclass 14, count 0 2006.252.08:05:42.29#ibcon#end of sib2, iclass 14, count 0 2006.252.08:05:42.29#ibcon#*mode == 0, iclass 14, count 0 2006.252.08:05:42.29#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.252.08:05:42.29#ibcon#[28=FRQ=06,752.99\r\n] 2006.252.08:05:42.29#ibcon#*before write, iclass 14, count 0 2006.252.08:05:42.29#ibcon#enter sib2, iclass 14, count 0 2006.252.08:05:42.29#ibcon#flushed, iclass 14, count 0 2006.252.08:05:42.29#ibcon#about to write, iclass 14, count 0 2006.252.08:05:42.29#ibcon#wrote, iclass 14, count 0 2006.252.08:05:42.29#ibcon#about to read 3, iclass 14, count 0 2006.252.08:05:42.33#ibcon#read 3, iclass 14, count 0 2006.252.08:05:42.33#ibcon#about to read 4, iclass 14, count 0 2006.252.08:05:42.33#ibcon#read 4, iclass 14, count 0 2006.252.08:05:42.33#ibcon#about to read 5, iclass 14, count 0 2006.252.08:05:42.33#ibcon#read 5, iclass 14, count 0 2006.252.08:05:42.33#ibcon#about to read 6, iclass 14, count 0 2006.252.08:05:42.33#ibcon#read 6, iclass 14, count 0 2006.252.08:05:42.33#ibcon#end of sib2, iclass 14, count 0 2006.252.08:05:42.33#ibcon#*after write, iclass 14, count 0 2006.252.08:05:42.33#ibcon#*before return 0, iclass 14, count 0 2006.252.08:05:42.33#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.252.08:05:42.33#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.252.08:05:42.33#ibcon#about to clear, iclass 14 cls_cnt 0 2006.252.08:05:42.33#ibcon#cleared, iclass 14 cls_cnt 0 2006.252.08:05:42.33$vc4f8/vb=6,4 2006.252.08:05:42.33#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.252.08:05:42.33#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.252.08:05:42.33#ibcon#ireg 11 cls_cnt 2 2006.252.08:05:42.33#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.252.08:05:42.39#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.252.08:05:42.39#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.252.08:05:42.39#ibcon#enter wrdev, iclass 16, count 2 2006.252.08:05:42.39#ibcon#first serial, iclass 16, count 2 2006.252.08:05:42.39#ibcon#enter sib2, iclass 16, count 2 2006.252.08:05:42.39#ibcon#flushed, iclass 16, count 2 2006.252.08:05:42.39#ibcon#about to write, iclass 16, count 2 2006.252.08:05:42.39#ibcon#wrote, iclass 16, count 2 2006.252.08:05:42.39#ibcon#about to read 3, iclass 16, count 2 2006.252.08:05:42.41#ibcon#read 3, iclass 16, count 2 2006.252.08:05:42.41#ibcon#about to read 4, iclass 16, count 2 2006.252.08:05:42.41#ibcon#read 4, iclass 16, count 2 2006.252.08:05:42.41#ibcon#about to read 5, iclass 16, count 2 2006.252.08:05:42.41#ibcon#read 5, iclass 16, count 2 2006.252.08:05:42.41#ibcon#about to read 6, iclass 16, count 2 2006.252.08:05:42.41#ibcon#read 6, iclass 16, count 2 2006.252.08:05:42.41#ibcon#end of sib2, iclass 16, count 2 2006.252.08:05:42.41#ibcon#*mode == 0, iclass 16, count 2 2006.252.08:05:42.41#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.252.08:05:42.41#ibcon#[27=AT06-04\r\n] 2006.252.08:05:42.41#ibcon#*before write, iclass 16, count 2 2006.252.08:05:42.41#ibcon#enter sib2, iclass 16, count 2 2006.252.08:05:42.41#ibcon#flushed, iclass 16, count 2 2006.252.08:05:42.41#ibcon#about to write, iclass 16, count 2 2006.252.08:05:42.41#ibcon#wrote, iclass 16, count 2 2006.252.08:05:42.41#ibcon#about to read 3, iclass 16, count 2 2006.252.08:05:42.44#ibcon#read 3, iclass 16, count 2 2006.252.08:05:42.44#ibcon#about to read 4, iclass 16, count 2 2006.252.08:05:42.44#ibcon#read 4, iclass 16, count 2 2006.252.08:05:42.44#ibcon#about to read 5, iclass 16, count 2 2006.252.08:05:42.44#ibcon#read 5, iclass 16, count 2 2006.252.08:05:42.44#ibcon#about to read 6, iclass 16, count 2 2006.252.08:05:42.44#ibcon#read 6, iclass 16, count 2 2006.252.08:05:42.44#ibcon#end of sib2, iclass 16, count 2 2006.252.08:05:42.44#ibcon#*after write, iclass 16, count 2 2006.252.08:05:42.44#ibcon#*before return 0, iclass 16, count 2 2006.252.08:05:42.44#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.252.08:05:42.44#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.252.08:05:42.44#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.252.08:05:42.44#ibcon#ireg 7 cls_cnt 0 2006.252.08:05:42.44#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.252.08:05:42.56#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.252.08:05:42.56#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.252.08:05:42.56#ibcon#enter wrdev, iclass 16, count 0 2006.252.08:05:42.56#ibcon#first serial, iclass 16, count 0 2006.252.08:05:42.56#ibcon#enter sib2, iclass 16, count 0 2006.252.08:05:42.56#ibcon#flushed, iclass 16, count 0 2006.252.08:05:42.56#ibcon#about to write, iclass 16, count 0 2006.252.08:05:42.56#ibcon#wrote, iclass 16, count 0 2006.252.08:05:42.56#ibcon#about to read 3, iclass 16, count 0 2006.252.08:05:42.58#ibcon#read 3, iclass 16, count 0 2006.252.08:05:42.58#ibcon#about to read 4, iclass 16, count 0 2006.252.08:05:42.58#ibcon#read 4, iclass 16, count 0 2006.252.08:05:42.58#ibcon#about to read 5, iclass 16, count 0 2006.252.08:05:42.58#ibcon#read 5, iclass 16, count 0 2006.252.08:05:42.58#ibcon#about to read 6, iclass 16, count 0 2006.252.08:05:42.58#ibcon#read 6, iclass 16, count 0 2006.252.08:05:42.58#ibcon#end of sib2, iclass 16, count 0 2006.252.08:05:42.58#ibcon#*mode == 0, iclass 16, count 0 2006.252.08:05:42.58#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.252.08:05:42.58#ibcon#[27=USB\r\n] 2006.252.08:05:42.58#ibcon#*before write, iclass 16, count 0 2006.252.08:05:42.58#ibcon#enter sib2, iclass 16, count 0 2006.252.08:05:42.58#ibcon#flushed, iclass 16, count 0 2006.252.08:05:42.58#ibcon#about to write, iclass 16, count 0 2006.252.08:05:42.58#ibcon#wrote, iclass 16, count 0 2006.252.08:05:42.58#ibcon#about to read 3, iclass 16, count 0 2006.252.08:05:42.61#ibcon#read 3, iclass 16, count 0 2006.252.08:05:42.61#ibcon#about to read 4, iclass 16, count 0 2006.252.08:05:42.61#ibcon#read 4, iclass 16, count 0 2006.252.08:05:42.61#ibcon#about to read 5, iclass 16, count 0 2006.252.08:05:42.61#ibcon#read 5, iclass 16, count 0 2006.252.08:05:42.61#ibcon#about to read 6, iclass 16, count 0 2006.252.08:05:42.61#ibcon#read 6, iclass 16, count 0 2006.252.08:05:42.61#ibcon#end of sib2, iclass 16, count 0 2006.252.08:05:42.61#ibcon#*after write, iclass 16, count 0 2006.252.08:05:42.61#ibcon#*before return 0, iclass 16, count 0 2006.252.08:05:42.61#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.252.08:05:42.61#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.252.08:05:42.61#ibcon#about to clear, iclass 16 cls_cnt 0 2006.252.08:05:42.61#ibcon#cleared, iclass 16 cls_cnt 0 2006.252.08:05:42.61$vc4f8/vabw=wide 2006.252.08:05:42.61#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.252.08:05:42.61#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.252.08:05:42.61#ibcon#ireg 8 cls_cnt 0 2006.252.08:05:42.61#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.252.08:05:42.61#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.252.08:05:42.61#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.252.08:05:42.61#ibcon#enter wrdev, iclass 18, count 0 2006.252.08:05:42.61#ibcon#first serial, iclass 18, count 0 2006.252.08:05:42.61#ibcon#enter sib2, iclass 18, count 0 2006.252.08:05:42.61#ibcon#flushed, iclass 18, count 0 2006.252.08:05:42.61#ibcon#about to write, iclass 18, count 0 2006.252.08:05:42.61#ibcon#wrote, iclass 18, count 0 2006.252.08:05:42.61#ibcon#about to read 3, iclass 18, count 0 2006.252.08:05:42.63#ibcon#read 3, iclass 18, count 0 2006.252.08:05:42.63#ibcon#about to read 4, iclass 18, count 0 2006.252.08:05:42.63#ibcon#read 4, iclass 18, count 0 2006.252.08:05:42.63#ibcon#about to read 5, iclass 18, count 0 2006.252.08:05:42.63#ibcon#read 5, iclass 18, count 0 2006.252.08:05:42.63#ibcon#about to read 6, iclass 18, count 0 2006.252.08:05:42.63#ibcon#read 6, iclass 18, count 0 2006.252.08:05:42.63#ibcon#end of sib2, iclass 18, count 0 2006.252.08:05:42.63#ibcon#*mode == 0, iclass 18, count 0 2006.252.08:05:42.63#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.252.08:05:42.63#ibcon#[25=BW32\r\n] 2006.252.08:05:42.63#ibcon#*before write, iclass 18, count 0 2006.252.08:05:42.63#ibcon#enter sib2, iclass 18, count 0 2006.252.08:05:42.63#ibcon#flushed, iclass 18, count 0 2006.252.08:05:42.63#ibcon#about to write, iclass 18, count 0 2006.252.08:05:42.63#ibcon#wrote, iclass 18, count 0 2006.252.08:05:42.63#ibcon#about to read 3, iclass 18, count 0 2006.252.08:05:42.66#ibcon#read 3, iclass 18, count 0 2006.252.08:05:42.66#ibcon#about to read 4, iclass 18, count 0 2006.252.08:05:42.66#ibcon#read 4, iclass 18, count 0 2006.252.08:05:42.66#ibcon#about to read 5, iclass 18, count 0 2006.252.08:05:42.66#ibcon#read 5, iclass 18, count 0 2006.252.08:05:42.66#ibcon#about to read 6, iclass 18, count 0 2006.252.08:05:42.66#ibcon#read 6, iclass 18, count 0 2006.252.08:05:42.66#ibcon#end of sib2, iclass 18, count 0 2006.252.08:05:42.66#ibcon#*after write, iclass 18, count 0 2006.252.08:05:42.66#ibcon#*before return 0, iclass 18, count 0 2006.252.08:05:42.66#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.252.08:05:42.66#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.252.08:05:42.66#ibcon#about to clear, iclass 18 cls_cnt 0 2006.252.08:05:42.66#ibcon#cleared, iclass 18 cls_cnt 0 2006.252.08:05:42.66$vc4f8/vbbw=wide 2006.252.08:05:42.66#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.252.08:05:42.66#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.252.08:05:42.66#ibcon#ireg 8 cls_cnt 0 2006.252.08:05:42.66#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.252.08:05:42.73#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.252.08:05:42.73#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.252.08:05:42.73#ibcon#enter wrdev, iclass 20, count 0 2006.252.08:05:42.73#ibcon#first serial, iclass 20, count 0 2006.252.08:05:42.73#ibcon#enter sib2, iclass 20, count 0 2006.252.08:05:42.73#ibcon#flushed, iclass 20, count 0 2006.252.08:05:42.73#ibcon#about to write, iclass 20, count 0 2006.252.08:05:42.73#ibcon#wrote, iclass 20, count 0 2006.252.08:05:42.73#ibcon#about to read 3, iclass 20, count 0 2006.252.08:05:42.75#ibcon#read 3, iclass 20, count 0 2006.252.08:05:42.75#ibcon#about to read 4, iclass 20, count 0 2006.252.08:05:42.75#ibcon#read 4, iclass 20, count 0 2006.252.08:05:42.75#ibcon#about to read 5, iclass 20, count 0 2006.252.08:05:42.75#ibcon#read 5, iclass 20, count 0 2006.252.08:05:42.75#ibcon#about to read 6, iclass 20, count 0 2006.252.08:05:42.75#ibcon#read 6, iclass 20, count 0 2006.252.08:05:42.75#ibcon#end of sib2, iclass 20, count 0 2006.252.08:05:42.75#ibcon#*mode == 0, iclass 20, count 0 2006.252.08:05:42.75#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.252.08:05:42.75#ibcon#[27=BW32\r\n] 2006.252.08:05:42.75#ibcon#*before write, iclass 20, count 0 2006.252.08:05:42.75#ibcon#enter sib2, iclass 20, count 0 2006.252.08:05:42.75#ibcon#flushed, iclass 20, count 0 2006.252.08:05:42.75#ibcon#about to write, iclass 20, count 0 2006.252.08:05:42.75#ibcon#wrote, iclass 20, count 0 2006.252.08:05:42.75#ibcon#about to read 3, iclass 20, count 0 2006.252.08:05:42.78#ibcon#read 3, iclass 20, count 0 2006.252.08:05:42.78#ibcon#about to read 4, iclass 20, count 0 2006.252.08:05:42.78#ibcon#read 4, iclass 20, count 0 2006.252.08:05:42.78#ibcon#about to read 5, iclass 20, count 0 2006.252.08:05:42.78#ibcon#read 5, iclass 20, count 0 2006.252.08:05:42.78#ibcon#about to read 6, iclass 20, count 0 2006.252.08:05:42.78#ibcon#read 6, iclass 20, count 0 2006.252.08:05:42.78#ibcon#end of sib2, iclass 20, count 0 2006.252.08:05:42.78#ibcon#*after write, iclass 20, count 0 2006.252.08:05:42.78#ibcon#*before return 0, iclass 20, count 0 2006.252.08:05:42.78#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.252.08:05:42.78#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.252.08:05:42.78#ibcon#about to clear, iclass 20 cls_cnt 0 2006.252.08:05:42.78#ibcon#cleared, iclass 20 cls_cnt 0 2006.252.08:05:42.78$4f8m12a/ifd4f 2006.252.08:05:42.78$ifd4f/lo= 2006.252.08:05:42.78$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.252.08:05:42.78$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.252.08:05:42.78$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.252.08:05:42.78$ifd4f/patch= 2006.252.08:05:42.78$ifd4f/patch=lo1,a1,a2,a3,a4 2006.252.08:05:42.78$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.252.08:05:42.78$ifd4f/patch=lo3,a5,a6,a7,a8 2006.252.08:05:42.78$4f8m12a/"form=m,16.000,1:2 2006.252.08:05:42.78$4f8m12a/"tpicd 2006.252.08:05:42.78$4f8m12a/echo=off 2006.252.08:05:42.78$4f8m12a/xlog=off 2006.252.08:05:42.78:!2006.252.08:06:10 2006.252.08:05:54.14#trakl#Source acquired 2006.252.08:05:55.14#flagr#flagr/antenna,acquired 2006.252.08:06:10.00:preob 2006.252.08:06:11.14/onsource/TRACKING 2006.252.08:06:11.14:!2006.252.08:06:20 2006.252.08:06:20.00:data_valid=on 2006.252.08:06:20.00:midob 2006.252.08:06:20.14/onsource/TRACKING 2006.252.08:06:20.14/wx/27.33,1011.1,90 2006.252.08:06:20.32/cable/+6.4110E-03 2006.252.08:06:21.41/va/01,08,usb,yes,34,35 2006.252.08:06:21.41/va/02,07,usb,yes,33,35 2006.252.08:06:21.41/va/03,06,usb,yes,36,36 2006.252.08:06:21.41/va/04,07,usb,yes,34,37 2006.252.08:06:21.41/va/05,07,usb,yes,38,40 2006.252.08:06:21.41/va/06,07,usb,yes,33,33 2006.252.08:06:21.41/va/07,07,usb,yes,33,33 2006.252.08:06:21.41/va/08,07,usb,yes,36,35 2006.252.08:06:21.64/valo/01,532.99,yes,locked 2006.252.08:06:21.64/valo/02,572.99,yes,locked 2006.252.08:06:21.64/valo/03,672.99,yes,locked 2006.252.08:06:21.64/valo/04,832.99,yes,locked 2006.252.08:06:21.64/valo/05,652.99,yes,locked 2006.252.08:06:21.64/valo/06,772.99,yes,locked 2006.252.08:06:21.64/valo/07,832.99,yes,locked 2006.252.08:06:21.64/valo/08,852.99,yes,locked 2006.252.08:06:22.73/vb/01,04,usb,yes,31,30 2006.252.08:06:22.73/vb/02,05,usb,yes,29,30 2006.252.08:06:22.73/vb/03,04,usb,yes,29,33 2006.252.08:06:22.73/vb/04,04,usb,yes,30,30 2006.252.08:06:22.73/vb/05,04,usb,yes,28,32 2006.252.08:06:22.73/vb/06,04,usb,yes,29,32 2006.252.08:06:22.73/vb/07,04,usb,yes,31,31 2006.252.08:06:22.73/vb/08,04,usb,yes,29,32 2006.252.08:06:22.97/vblo/01,632.99,yes,locked 2006.252.08:06:22.97/vblo/02,640.99,yes,locked 2006.252.08:06:22.97/vblo/03,656.99,yes,locked 2006.252.08:06:22.97/vblo/04,712.99,yes,locked 2006.252.08:06:22.97/vblo/05,744.99,yes,locked 2006.252.08:06:22.97/vblo/06,752.99,yes,locked 2006.252.08:06:22.97/vblo/07,734.99,yes,locked 2006.252.08:06:22.97/vblo/08,744.99,yes,locked 2006.252.08:06:23.12/vabw/8 2006.252.08:06:23.27/vbbw/8 2006.252.08:06:23.36/xfe/off,on,14.2 2006.252.08:06:23.76/ifatt/23,28,28,28 2006.252.08:06:24.08/fmout-gps/S +4.78E-07 2006.252.08:06:24.12:!2006.252.08:07:20 2006.252.08:07:20.00:data_valid=off 2006.252.08:07:20.00:postob 2006.252.08:07:20.15/cable/+6.4112E-03 2006.252.08:07:20.15/wx/27.33,1011.1,89 2006.252.08:07:21.08/fmout-gps/S +4.77E-07 2006.252.08:07:21.08:scan_name=252-0808,k06252,60 2006.252.08:07:21.08:source=4c39.25,092703.01,390220.9,2000.0,ccw 2006.252.08:07:21.14#flagr#flagr/antenna,new-source 2006.252.08:07:22.14:checkk5 2006.252.08:07:22.51/chk_autoobs//k5ts1/ autoobs is running! 2006.252.08:07:22.88/chk_autoobs//k5ts2/ autoobs is running! 2006.252.08:07:23.27/chk_autoobs//k5ts3/ autoobs is running! 2006.252.08:07:23.64/chk_autoobs//k5ts4/ autoobs is running! 2006.252.08:07:24.00/chk_obsdata//k5ts1/T2520806??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.08:07:24.37/chk_obsdata//k5ts2/T2520806??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.08:07:24.74/chk_obsdata//k5ts3/T2520806??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.08:07:25.11/chk_obsdata//k5ts4/T2520806??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.08:07:25.80/k5log//k5ts1_log_newline 2006.252.08:07:26.49/k5log//k5ts2_log_newline 2006.252.08:07:27.19/k5log//k5ts3_log_newline 2006.252.08:07:27.88/k5log//k5ts4_log_newline 2006.252.08:07:27.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.252.08:07:27.91:4f8m12a=2 2006.252.08:07:27.91$4f8m12a/echo=on 2006.252.08:07:27.91$4f8m12a/pcalon 2006.252.08:07:27.91$pcalon/"no phase cal control is implemented here 2006.252.08:07:27.91$4f8m12a/"tpicd=stop 2006.252.08:07:27.91$4f8m12a/vc4f8 2006.252.08:07:27.91$vc4f8/valo=1,532.99 2006.252.08:07:27.91#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.252.08:07:27.91#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.252.08:07:27.91#ibcon#ireg 17 cls_cnt 0 2006.252.08:07:27.91#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.252.08:07:27.91#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.252.08:07:27.91#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.252.08:07:27.91#ibcon#enter wrdev, iclass 27, count 0 2006.252.08:07:27.91#ibcon#first serial, iclass 27, count 0 2006.252.08:07:27.91#ibcon#enter sib2, iclass 27, count 0 2006.252.08:07:27.91#ibcon#flushed, iclass 27, count 0 2006.252.08:07:27.91#ibcon#about to write, iclass 27, count 0 2006.252.08:07:27.91#ibcon#wrote, iclass 27, count 0 2006.252.08:07:27.91#ibcon#about to read 3, iclass 27, count 0 2006.252.08:07:27.95#ibcon#read 3, iclass 27, count 0 2006.252.08:07:27.95#ibcon#about to read 4, iclass 27, count 0 2006.252.08:07:27.95#ibcon#read 4, iclass 27, count 0 2006.252.08:07:27.95#ibcon#about to read 5, iclass 27, count 0 2006.252.08:07:27.95#ibcon#read 5, iclass 27, count 0 2006.252.08:07:27.95#ibcon#about to read 6, iclass 27, count 0 2006.252.08:07:27.95#ibcon#read 6, iclass 27, count 0 2006.252.08:07:27.95#ibcon#end of sib2, iclass 27, count 0 2006.252.08:07:27.95#ibcon#*mode == 0, iclass 27, count 0 2006.252.08:07:27.95#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.252.08:07:27.95#ibcon#[26=FRQ=01,532.99\r\n] 2006.252.08:07:27.95#ibcon#*before write, iclass 27, count 0 2006.252.08:07:27.95#ibcon#enter sib2, iclass 27, count 0 2006.252.08:07:27.95#ibcon#flushed, iclass 27, count 0 2006.252.08:07:27.95#ibcon#about to write, iclass 27, count 0 2006.252.08:07:27.95#ibcon#wrote, iclass 27, count 0 2006.252.08:07:27.95#ibcon#about to read 3, iclass 27, count 0 2006.252.08:07:28.00#ibcon#read 3, iclass 27, count 0 2006.252.08:07:28.00#ibcon#about to read 4, iclass 27, count 0 2006.252.08:07:28.00#ibcon#read 4, iclass 27, count 0 2006.252.08:07:28.00#ibcon#about to read 5, iclass 27, count 0 2006.252.08:07:28.00#ibcon#read 5, iclass 27, count 0 2006.252.08:07:28.00#ibcon#about to read 6, iclass 27, count 0 2006.252.08:07:28.00#ibcon#read 6, iclass 27, count 0 2006.252.08:07:28.00#ibcon#end of sib2, iclass 27, count 0 2006.252.08:07:28.00#ibcon#*after write, iclass 27, count 0 2006.252.08:07:28.00#ibcon#*before return 0, iclass 27, count 0 2006.252.08:07:28.00#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.252.08:07:28.00#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.252.08:07:28.00#ibcon#about to clear, iclass 27 cls_cnt 0 2006.252.08:07:28.00#ibcon#cleared, iclass 27 cls_cnt 0 2006.252.08:07:28.00$vc4f8/va=1,8 2006.252.08:07:28.00#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.252.08:07:28.00#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.252.08:07:28.00#ibcon#ireg 11 cls_cnt 2 2006.252.08:07:28.00#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.252.08:07:28.00#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.252.08:07:28.00#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.252.08:07:28.00#ibcon#enter wrdev, iclass 29, count 2 2006.252.08:07:28.00#ibcon#first serial, iclass 29, count 2 2006.252.08:07:28.00#ibcon#enter sib2, iclass 29, count 2 2006.252.08:07:28.00#ibcon#flushed, iclass 29, count 2 2006.252.08:07:28.00#ibcon#about to write, iclass 29, count 2 2006.252.08:07:28.00#ibcon#wrote, iclass 29, count 2 2006.252.08:07:28.00#ibcon#about to read 3, iclass 29, count 2 2006.252.08:07:28.02#ibcon#read 3, iclass 29, count 2 2006.252.08:07:28.02#ibcon#about to read 4, iclass 29, count 2 2006.252.08:07:28.02#ibcon#read 4, iclass 29, count 2 2006.252.08:07:28.02#ibcon#about to read 5, iclass 29, count 2 2006.252.08:07:28.02#ibcon#read 5, iclass 29, count 2 2006.252.08:07:28.02#ibcon#about to read 6, iclass 29, count 2 2006.252.08:07:28.02#ibcon#read 6, iclass 29, count 2 2006.252.08:07:28.02#ibcon#end of sib2, iclass 29, count 2 2006.252.08:07:28.02#ibcon#*mode == 0, iclass 29, count 2 2006.252.08:07:28.02#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.252.08:07:28.02#ibcon#[25=AT01-08\r\n] 2006.252.08:07:28.02#ibcon#*before write, iclass 29, count 2 2006.252.08:07:28.02#ibcon#enter sib2, iclass 29, count 2 2006.252.08:07:28.02#ibcon#flushed, iclass 29, count 2 2006.252.08:07:28.02#ibcon#about to write, iclass 29, count 2 2006.252.08:07:28.02#ibcon#wrote, iclass 29, count 2 2006.252.08:07:28.02#ibcon#about to read 3, iclass 29, count 2 2006.252.08:07:28.05#ibcon#read 3, iclass 29, count 2 2006.252.08:07:28.05#ibcon#about to read 4, iclass 29, count 2 2006.252.08:07:28.05#ibcon#read 4, iclass 29, count 2 2006.252.08:07:28.05#ibcon#about to read 5, iclass 29, count 2 2006.252.08:07:28.05#ibcon#read 5, iclass 29, count 2 2006.252.08:07:28.05#ibcon#about to read 6, iclass 29, count 2 2006.252.08:07:28.05#ibcon#read 6, iclass 29, count 2 2006.252.08:07:28.05#ibcon#end of sib2, iclass 29, count 2 2006.252.08:07:28.05#ibcon#*after write, iclass 29, count 2 2006.252.08:07:28.05#ibcon#*before return 0, iclass 29, count 2 2006.252.08:07:28.05#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.252.08:07:28.05#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.252.08:07:28.05#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.252.08:07:28.05#ibcon#ireg 7 cls_cnt 0 2006.252.08:07:28.05#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.252.08:07:28.17#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.252.08:07:28.17#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.252.08:07:28.17#ibcon#enter wrdev, iclass 29, count 0 2006.252.08:07:28.17#ibcon#first serial, iclass 29, count 0 2006.252.08:07:28.17#ibcon#enter sib2, iclass 29, count 0 2006.252.08:07:28.17#ibcon#flushed, iclass 29, count 0 2006.252.08:07:28.17#ibcon#about to write, iclass 29, count 0 2006.252.08:07:28.17#ibcon#wrote, iclass 29, count 0 2006.252.08:07:28.17#ibcon#about to read 3, iclass 29, count 0 2006.252.08:07:28.19#ibcon#read 3, iclass 29, count 0 2006.252.08:07:28.19#ibcon#about to read 4, iclass 29, count 0 2006.252.08:07:28.19#ibcon#read 4, iclass 29, count 0 2006.252.08:07:28.19#ibcon#about to read 5, iclass 29, count 0 2006.252.08:07:28.19#ibcon#read 5, iclass 29, count 0 2006.252.08:07:28.19#ibcon#about to read 6, iclass 29, count 0 2006.252.08:07:28.19#ibcon#read 6, iclass 29, count 0 2006.252.08:07:28.19#ibcon#end of sib2, iclass 29, count 0 2006.252.08:07:28.19#ibcon#*mode == 0, iclass 29, count 0 2006.252.08:07:28.19#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.252.08:07:28.19#ibcon#[25=USB\r\n] 2006.252.08:07:28.19#ibcon#*before write, iclass 29, count 0 2006.252.08:07:28.19#ibcon#enter sib2, iclass 29, count 0 2006.252.08:07:28.19#ibcon#flushed, iclass 29, count 0 2006.252.08:07:28.19#ibcon#about to write, iclass 29, count 0 2006.252.08:07:28.19#ibcon#wrote, iclass 29, count 0 2006.252.08:07:28.19#ibcon#about to read 3, iclass 29, count 0 2006.252.08:07:28.22#ibcon#read 3, iclass 29, count 0 2006.252.08:07:28.22#ibcon#about to read 4, iclass 29, count 0 2006.252.08:07:28.22#ibcon#read 4, iclass 29, count 0 2006.252.08:07:28.22#ibcon#about to read 5, iclass 29, count 0 2006.252.08:07:28.22#ibcon#read 5, iclass 29, count 0 2006.252.08:07:28.22#ibcon#about to read 6, iclass 29, count 0 2006.252.08:07:28.22#ibcon#read 6, iclass 29, count 0 2006.252.08:07:28.22#ibcon#end of sib2, iclass 29, count 0 2006.252.08:07:28.22#ibcon#*after write, iclass 29, count 0 2006.252.08:07:28.22#ibcon#*before return 0, iclass 29, count 0 2006.252.08:07:28.22#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.252.08:07:28.22#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.252.08:07:28.22#ibcon#about to clear, iclass 29 cls_cnt 0 2006.252.08:07:28.22#ibcon#cleared, iclass 29 cls_cnt 0 2006.252.08:07:28.22$vc4f8/valo=2,572.99 2006.252.08:07:28.22#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.252.08:07:28.22#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.252.08:07:28.22#ibcon#ireg 17 cls_cnt 0 2006.252.08:07:28.22#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.252.08:07:28.22#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.252.08:07:28.22#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.252.08:07:28.22#ibcon#enter wrdev, iclass 31, count 0 2006.252.08:07:28.22#ibcon#first serial, iclass 31, count 0 2006.252.08:07:28.22#ibcon#enter sib2, iclass 31, count 0 2006.252.08:07:28.22#ibcon#flushed, iclass 31, count 0 2006.252.08:07:28.22#ibcon#about to write, iclass 31, count 0 2006.252.08:07:28.22#ibcon#wrote, iclass 31, count 0 2006.252.08:07:28.22#ibcon#about to read 3, iclass 31, count 0 2006.252.08:07:28.24#ibcon#read 3, iclass 31, count 0 2006.252.08:07:28.24#ibcon#about to read 4, iclass 31, count 0 2006.252.08:07:28.24#ibcon#read 4, iclass 31, count 0 2006.252.08:07:28.24#ibcon#about to read 5, iclass 31, count 0 2006.252.08:07:28.24#ibcon#read 5, iclass 31, count 0 2006.252.08:07:28.24#ibcon#about to read 6, iclass 31, count 0 2006.252.08:07:28.24#ibcon#read 6, iclass 31, count 0 2006.252.08:07:28.24#ibcon#end of sib2, iclass 31, count 0 2006.252.08:07:28.24#ibcon#*mode == 0, iclass 31, count 0 2006.252.08:07:28.24#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.252.08:07:28.24#ibcon#[26=FRQ=02,572.99\r\n] 2006.252.08:07:28.24#ibcon#*before write, iclass 31, count 0 2006.252.08:07:28.24#ibcon#enter sib2, iclass 31, count 0 2006.252.08:07:28.24#ibcon#flushed, iclass 31, count 0 2006.252.08:07:28.24#ibcon#about to write, iclass 31, count 0 2006.252.08:07:28.24#ibcon#wrote, iclass 31, count 0 2006.252.08:07:28.24#ibcon#about to read 3, iclass 31, count 0 2006.252.08:07:28.28#ibcon#read 3, iclass 31, count 0 2006.252.08:07:28.28#ibcon#about to read 4, iclass 31, count 0 2006.252.08:07:28.28#ibcon#read 4, iclass 31, count 0 2006.252.08:07:28.28#ibcon#about to read 5, iclass 31, count 0 2006.252.08:07:28.28#ibcon#read 5, iclass 31, count 0 2006.252.08:07:28.28#ibcon#about to read 6, iclass 31, count 0 2006.252.08:07:28.28#ibcon#read 6, iclass 31, count 0 2006.252.08:07:28.28#ibcon#end of sib2, iclass 31, count 0 2006.252.08:07:28.28#ibcon#*after write, iclass 31, count 0 2006.252.08:07:28.28#ibcon#*before return 0, iclass 31, count 0 2006.252.08:07:28.28#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.252.08:07:28.28#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.252.08:07:28.28#ibcon#about to clear, iclass 31 cls_cnt 0 2006.252.08:07:28.28#ibcon#cleared, iclass 31 cls_cnt 0 2006.252.08:07:28.28$vc4f8/va=2,7 2006.252.08:07:28.28#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.252.08:07:28.28#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.252.08:07:28.28#ibcon#ireg 11 cls_cnt 2 2006.252.08:07:28.28#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.252.08:07:28.34#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.252.08:07:28.34#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.252.08:07:28.34#ibcon#enter wrdev, iclass 33, count 2 2006.252.08:07:28.34#ibcon#first serial, iclass 33, count 2 2006.252.08:07:28.34#ibcon#enter sib2, iclass 33, count 2 2006.252.08:07:28.34#ibcon#flushed, iclass 33, count 2 2006.252.08:07:28.34#ibcon#about to write, iclass 33, count 2 2006.252.08:07:28.34#ibcon#wrote, iclass 33, count 2 2006.252.08:07:28.34#ibcon#about to read 3, iclass 33, count 2 2006.252.08:07:28.36#ibcon#read 3, iclass 33, count 2 2006.252.08:07:28.36#ibcon#about to read 4, iclass 33, count 2 2006.252.08:07:28.36#ibcon#read 4, iclass 33, count 2 2006.252.08:07:28.36#ibcon#about to read 5, iclass 33, count 2 2006.252.08:07:28.36#ibcon#read 5, iclass 33, count 2 2006.252.08:07:28.36#ibcon#about to read 6, iclass 33, count 2 2006.252.08:07:28.36#ibcon#read 6, iclass 33, count 2 2006.252.08:07:28.36#ibcon#end of sib2, iclass 33, count 2 2006.252.08:07:28.36#ibcon#*mode == 0, iclass 33, count 2 2006.252.08:07:28.36#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.252.08:07:28.36#ibcon#[25=AT02-07\r\n] 2006.252.08:07:28.36#ibcon#*before write, iclass 33, count 2 2006.252.08:07:28.36#ibcon#enter sib2, iclass 33, count 2 2006.252.08:07:28.36#ibcon#flushed, iclass 33, count 2 2006.252.08:07:28.36#ibcon#about to write, iclass 33, count 2 2006.252.08:07:28.36#ibcon#wrote, iclass 33, count 2 2006.252.08:07:28.36#ibcon#about to read 3, iclass 33, count 2 2006.252.08:07:28.39#ibcon#read 3, iclass 33, count 2 2006.252.08:07:28.39#ibcon#about to read 4, iclass 33, count 2 2006.252.08:07:28.39#ibcon#read 4, iclass 33, count 2 2006.252.08:07:28.39#ibcon#about to read 5, iclass 33, count 2 2006.252.08:07:28.39#ibcon#read 5, iclass 33, count 2 2006.252.08:07:28.39#ibcon#about to read 6, iclass 33, count 2 2006.252.08:07:28.39#ibcon#read 6, iclass 33, count 2 2006.252.08:07:28.39#ibcon#end of sib2, iclass 33, count 2 2006.252.08:07:28.39#ibcon#*after write, iclass 33, count 2 2006.252.08:07:28.39#ibcon#*before return 0, iclass 33, count 2 2006.252.08:07:28.39#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.252.08:07:28.39#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.252.08:07:28.39#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.252.08:07:28.39#ibcon#ireg 7 cls_cnt 0 2006.252.08:07:28.39#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.252.08:07:28.51#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.252.08:07:28.51#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.252.08:07:28.51#ibcon#enter wrdev, iclass 33, count 0 2006.252.08:07:28.51#ibcon#first serial, iclass 33, count 0 2006.252.08:07:28.51#ibcon#enter sib2, iclass 33, count 0 2006.252.08:07:28.51#ibcon#flushed, iclass 33, count 0 2006.252.08:07:28.51#ibcon#about to write, iclass 33, count 0 2006.252.08:07:28.51#ibcon#wrote, iclass 33, count 0 2006.252.08:07:28.51#ibcon#about to read 3, iclass 33, count 0 2006.252.08:07:28.53#ibcon#read 3, iclass 33, count 0 2006.252.08:07:28.53#ibcon#about to read 4, iclass 33, count 0 2006.252.08:07:28.53#ibcon#read 4, iclass 33, count 0 2006.252.08:07:28.53#ibcon#about to read 5, iclass 33, count 0 2006.252.08:07:28.53#ibcon#read 5, iclass 33, count 0 2006.252.08:07:28.53#ibcon#about to read 6, iclass 33, count 0 2006.252.08:07:28.53#ibcon#read 6, iclass 33, count 0 2006.252.08:07:28.53#ibcon#end of sib2, iclass 33, count 0 2006.252.08:07:28.53#ibcon#*mode == 0, iclass 33, count 0 2006.252.08:07:28.53#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.252.08:07:28.53#ibcon#[25=USB\r\n] 2006.252.08:07:28.53#ibcon#*before write, iclass 33, count 0 2006.252.08:07:28.53#ibcon#enter sib2, iclass 33, count 0 2006.252.08:07:28.53#ibcon#flushed, iclass 33, count 0 2006.252.08:07:28.53#ibcon#about to write, iclass 33, count 0 2006.252.08:07:28.53#ibcon#wrote, iclass 33, count 0 2006.252.08:07:28.53#ibcon#about to read 3, iclass 33, count 0 2006.252.08:07:28.56#ibcon#read 3, iclass 33, count 0 2006.252.08:07:28.56#ibcon#about to read 4, iclass 33, count 0 2006.252.08:07:28.56#ibcon#read 4, iclass 33, count 0 2006.252.08:07:28.56#ibcon#about to read 5, iclass 33, count 0 2006.252.08:07:28.56#ibcon#read 5, iclass 33, count 0 2006.252.08:07:28.56#ibcon#about to read 6, iclass 33, count 0 2006.252.08:07:28.56#ibcon#read 6, iclass 33, count 0 2006.252.08:07:28.56#ibcon#end of sib2, iclass 33, count 0 2006.252.08:07:28.56#ibcon#*after write, iclass 33, count 0 2006.252.08:07:28.56#ibcon#*before return 0, iclass 33, count 0 2006.252.08:07:28.56#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.252.08:07:28.56#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.252.08:07:28.56#ibcon#about to clear, iclass 33 cls_cnt 0 2006.252.08:07:28.56#ibcon#cleared, iclass 33 cls_cnt 0 2006.252.08:07:28.56$vc4f8/valo=3,672.99 2006.252.08:07:28.56#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.252.08:07:28.56#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.252.08:07:28.56#ibcon#ireg 17 cls_cnt 0 2006.252.08:07:28.56#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.252.08:07:28.56#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.252.08:07:28.56#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.252.08:07:28.56#ibcon#enter wrdev, iclass 35, count 0 2006.252.08:07:28.56#ibcon#first serial, iclass 35, count 0 2006.252.08:07:28.56#ibcon#enter sib2, iclass 35, count 0 2006.252.08:07:28.56#ibcon#flushed, iclass 35, count 0 2006.252.08:07:28.56#ibcon#about to write, iclass 35, count 0 2006.252.08:07:28.56#ibcon#wrote, iclass 35, count 0 2006.252.08:07:28.56#ibcon#about to read 3, iclass 35, count 0 2006.252.08:07:28.58#ibcon#read 3, iclass 35, count 0 2006.252.08:07:28.58#ibcon#about to read 4, iclass 35, count 0 2006.252.08:07:28.58#ibcon#read 4, iclass 35, count 0 2006.252.08:07:28.58#ibcon#about to read 5, iclass 35, count 0 2006.252.08:07:28.58#ibcon#read 5, iclass 35, count 0 2006.252.08:07:28.58#ibcon#about to read 6, iclass 35, count 0 2006.252.08:07:28.58#ibcon#read 6, iclass 35, count 0 2006.252.08:07:28.58#ibcon#end of sib2, iclass 35, count 0 2006.252.08:07:28.58#ibcon#*mode == 0, iclass 35, count 0 2006.252.08:07:28.58#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.252.08:07:28.58#ibcon#[26=FRQ=03,672.99\r\n] 2006.252.08:07:28.58#ibcon#*before write, iclass 35, count 0 2006.252.08:07:28.58#ibcon#enter sib2, iclass 35, count 0 2006.252.08:07:28.58#ibcon#flushed, iclass 35, count 0 2006.252.08:07:28.58#ibcon#about to write, iclass 35, count 0 2006.252.08:07:28.58#ibcon#wrote, iclass 35, count 0 2006.252.08:07:28.58#ibcon#about to read 3, iclass 35, count 0 2006.252.08:07:28.63#ibcon#read 3, iclass 35, count 0 2006.252.08:07:28.63#ibcon#about to read 4, iclass 35, count 0 2006.252.08:07:28.63#ibcon#read 4, iclass 35, count 0 2006.252.08:07:28.63#ibcon#about to read 5, iclass 35, count 0 2006.252.08:07:28.63#ibcon#read 5, iclass 35, count 0 2006.252.08:07:28.63#ibcon#about to read 6, iclass 35, count 0 2006.252.08:07:28.63#ibcon#read 6, iclass 35, count 0 2006.252.08:07:28.63#ibcon#end of sib2, iclass 35, count 0 2006.252.08:07:28.63#ibcon#*after write, iclass 35, count 0 2006.252.08:07:28.63#ibcon#*before return 0, iclass 35, count 0 2006.252.08:07:28.63#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.252.08:07:28.63#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.252.08:07:28.63#ibcon#about to clear, iclass 35 cls_cnt 0 2006.252.08:07:28.63#ibcon#cleared, iclass 35 cls_cnt 0 2006.252.08:07:28.63$vc4f8/va=3,6 2006.252.08:07:28.63#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.252.08:07:28.63#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.252.08:07:28.63#ibcon#ireg 11 cls_cnt 2 2006.252.08:07:28.63#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.252.08:07:28.68#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.252.08:07:28.68#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.252.08:07:28.68#ibcon#enter wrdev, iclass 37, count 2 2006.252.08:07:28.68#ibcon#first serial, iclass 37, count 2 2006.252.08:07:28.68#ibcon#enter sib2, iclass 37, count 2 2006.252.08:07:28.68#ibcon#flushed, iclass 37, count 2 2006.252.08:07:28.68#ibcon#about to write, iclass 37, count 2 2006.252.08:07:28.68#ibcon#wrote, iclass 37, count 2 2006.252.08:07:28.68#ibcon#about to read 3, iclass 37, count 2 2006.252.08:07:28.70#ibcon#read 3, iclass 37, count 2 2006.252.08:07:28.70#ibcon#about to read 4, iclass 37, count 2 2006.252.08:07:28.70#ibcon#read 4, iclass 37, count 2 2006.252.08:07:28.70#ibcon#about to read 5, iclass 37, count 2 2006.252.08:07:28.70#ibcon#read 5, iclass 37, count 2 2006.252.08:07:28.70#ibcon#about to read 6, iclass 37, count 2 2006.252.08:07:28.70#ibcon#read 6, iclass 37, count 2 2006.252.08:07:28.70#ibcon#end of sib2, iclass 37, count 2 2006.252.08:07:28.70#ibcon#*mode == 0, iclass 37, count 2 2006.252.08:07:28.70#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.252.08:07:28.70#ibcon#[25=AT03-06\r\n] 2006.252.08:07:28.70#ibcon#*before write, iclass 37, count 2 2006.252.08:07:28.70#ibcon#enter sib2, iclass 37, count 2 2006.252.08:07:28.70#ibcon#flushed, iclass 37, count 2 2006.252.08:07:28.70#ibcon#about to write, iclass 37, count 2 2006.252.08:07:28.70#ibcon#wrote, iclass 37, count 2 2006.252.08:07:28.70#ibcon#about to read 3, iclass 37, count 2 2006.252.08:07:28.73#ibcon#read 3, iclass 37, count 2 2006.252.08:07:28.73#ibcon#about to read 4, iclass 37, count 2 2006.252.08:07:28.73#ibcon#read 4, iclass 37, count 2 2006.252.08:07:28.73#ibcon#about to read 5, iclass 37, count 2 2006.252.08:07:28.73#ibcon#read 5, iclass 37, count 2 2006.252.08:07:28.73#ibcon#about to read 6, iclass 37, count 2 2006.252.08:07:28.73#ibcon#read 6, iclass 37, count 2 2006.252.08:07:28.73#ibcon#end of sib2, iclass 37, count 2 2006.252.08:07:28.73#ibcon#*after write, iclass 37, count 2 2006.252.08:07:28.73#ibcon#*before return 0, iclass 37, count 2 2006.252.08:07:28.73#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.252.08:07:28.73#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.252.08:07:28.73#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.252.08:07:28.73#ibcon#ireg 7 cls_cnt 0 2006.252.08:07:28.73#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.252.08:07:28.85#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.252.08:07:28.85#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.252.08:07:28.85#ibcon#enter wrdev, iclass 37, count 0 2006.252.08:07:28.85#ibcon#first serial, iclass 37, count 0 2006.252.08:07:28.85#ibcon#enter sib2, iclass 37, count 0 2006.252.08:07:28.85#ibcon#flushed, iclass 37, count 0 2006.252.08:07:28.85#ibcon#about to write, iclass 37, count 0 2006.252.08:07:28.85#ibcon#wrote, iclass 37, count 0 2006.252.08:07:28.85#ibcon#about to read 3, iclass 37, count 0 2006.252.08:07:28.87#ibcon#read 3, iclass 37, count 0 2006.252.08:07:28.87#ibcon#about to read 4, iclass 37, count 0 2006.252.08:07:28.87#ibcon#read 4, iclass 37, count 0 2006.252.08:07:28.87#ibcon#about to read 5, iclass 37, count 0 2006.252.08:07:28.87#ibcon#read 5, iclass 37, count 0 2006.252.08:07:28.87#ibcon#about to read 6, iclass 37, count 0 2006.252.08:07:28.87#ibcon#read 6, iclass 37, count 0 2006.252.08:07:28.87#ibcon#end of sib2, iclass 37, count 0 2006.252.08:07:28.87#ibcon#*mode == 0, iclass 37, count 0 2006.252.08:07:28.87#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.252.08:07:28.87#ibcon#[25=USB\r\n] 2006.252.08:07:28.87#ibcon#*before write, iclass 37, count 0 2006.252.08:07:28.87#ibcon#enter sib2, iclass 37, count 0 2006.252.08:07:28.87#ibcon#flushed, iclass 37, count 0 2006.252.08:07:28.87#ibcon#about to write, iclass 37, count 0 2006.252.08:07:28.87#ibcon#wrote, iclass 37, count 0 2006.252.08:07:28.87#ibcon#about to read 3, iclass 37, count 0 2006.252.08:07:28.90#ibcon#read 3, iclass 37, count 0 2006.252.08:07:28.90#ibcon#about to read 4, iclass 37, count 0 2006.252.08:07:28.90#ibcon#read 4, iclass 37, count 0 2006.252.08:07:28.90#ibcon#about to read 5, iclass 37, count 0 2006.252.08:07:28.90#ibcon#read 5, iclass 37, count 0 2006.252.08:07:28.90#ibcon#about to read 6, iclass 37, count 0 2006.252.08:07:28.90#ibcon#read 6, iclass 37, count 0 2006.252.08:07:28.90#ibcon#end of sib2, iclass 37, count 0 2006.252.08:07:28.90#ibcon#*after write, iclass 37, count 0 2006.252.08:07:28.90#ibcon#*before return 0, iclass 37, count 0 2006.252.08:07:28.90#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.252.08:07:28.90#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.252.08:07:28.90#ibcon#about to clear, iclass 37 cls_cnt 0 2006.252.08:07:28.90#ibcon#cleared, iclass 37 cls_cnt 0 2006.252.08:07:28.90$vc4f8/valo=4,832.99 2006.252.08:07:28.90#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.252.08:07:28.90#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.252.08:07:28.90#ibcon#ireg 17 cls_cnt 0 2006.252.08:07:28.90#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.252.08:07:28.90#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.252.08:07:28.90#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.252.08:07:28.90#ibcon#enter wrdev, iclass 39, count 0 2006.252.08:07:28.90#ibcon#first serial, iclass 39, count 0 2006.252.08:07:28.90#ibcon#enter sib2, iclass 39, count 0 2006.252.08:07:28.90#ibcon#flushed, iclass 39, count 0 2006.252.08:07:28.90#ibcon#about to write, iclass 39, count 0 2006.252.08:07:28.90#ibcon#wrote, iclass 39, count 0 2006.252.08:07:28.90#ibcon#about to read 3, iclass 39, count 0 2006.252.08:07:28.92#ibcon#read 3, iclass 39, count 0 2006.252.08:07:28.92#ibcon#about to read 4, iclass 39, count 0 2006.252.08:07:28.92#ibcon#read 4, iclass 39, count 0 2006.252.08:07:28.92#ibcon#about to read 5, iclass 39, count 0 2006.252.08:07:28.92#ibcon#read 5, iclass 39, count 0 2006.252.08:07:28.92#ibcon#about to read 6, iclass 39, count 0 2006.252.08:07:28.92#ibcon#read 6, iclass 39, count 0 2006.252.08:07:28.92#ibcon#end of sib2, iclass 39, count 0 2006.252.08:07:28.92#ibcon#*mode == 0, iclass 39, count 0 2006.252.08:07:28.92#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.252.08:07:28.92#ibcon#[26=FRQ=04,832.99\r\n] 2006.252.08:07:28.92#ibcon#*before write, iclass 39, count 0 2006.252.08:07:28.92#ibcon#enter sib2, iclass 39, count 0 2006.252.08:07:28.92#ibcon#flushed, iclass 39, count 0 2006.252.08:07:28.92#ibcon#about to write, iclass 39, count 0 2006.252.08:07:28.92#ibcon#wrote, iclass 39, count 0 2006.252.08:07:28.92#ibcon#about to read 3, iclass 39, count 0 2006.252.08:07:28.97#ibcon#read 3, iclass 39, count 0 2006.252.08:07:28.97#ibcon#about to read 4, iclass 39, count 0 2006.252.08:07:28.97#ibcon#read 4, iclass 39, count 0 2006.252.08:07:28.97#ibcon#about to read 5, iclass 39, count 0 2006.252.08:07:28.97#ibcon#read 5, iclass 39, count 0 2006.252.08:07:28.97#ibcon#about to read 6, iclass 39, count 0 2006.252.08:07:28.97#ibcon#read 6, iclass 39, count 0 2006.252.08:07:28.97#ibcon#end of sib2, iclass 39, count 0 2006.252.08:07:28.97#ibcon#*after write, iclass 39, count 0 2006.252.08:07:28.97#ibcon#*before return 0, iclass 39, count 0 2006.252.08:07:28.97#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.252.08:07:28.97#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.252.08:07:28.97#ibcon#about to clear, iclass 39 cls_cnt 0 2006.252.08:07:28.97#ibcon#cleared, iclass 39 cls_cnt 0 2006.252.08:07:28.97$vc4f8/va=4,7 2006.252.08:07:28.97#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.252.08:07:28.97#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.252.08:07:28.97#ibcon#ireg 11 cls_cnt 2 2006.252.08:07:28.97#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.252.08:07:29.02#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.252.08:07:29.02#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.252.08:07:29.02#ibcon#enter wrdev, iclass 3, count 2 2006.252.08:07:29.02#ibcon#first serial, iclass 3, count 2 2006.252.08:07:29.02#ibcon#enter sib2, iclass 3, count 2 2006.252.08:07:29.02#ibcon#flushed, iclass 3, count 2 2006.252.08:07:29.02#ibcon#about to write, iclass 3, count 2 2006.252.08:07:29.02#ibcon#wrote, iclass 3, count 2 2006.252.08:07:29.02#ibcon#about to read 3, iclass 3, count 2 2006.252.08:07:29.04#ibcon#read 3, iclass 3, count 2 2006.252.08:07:29.04#ibcon#about to read 4, iclass 3, count 2 2006.252.08:07:29.04#ibcon#read 4, iclass 3, count 2 2006.252.08:07:29.04#ibcon#about to read 5, iclass 3, count 2 2006.252.08:07:29.04#ibcon#read 5, iclass 3, count 2 2006.252.08:07:29.04#ibcon#about to read 6, iclass 3, count 2 2006.252.08:07:29.04#ibcon#read 6, iclass 3, count 2 2006.252.08:07:29.04#ibcon#end of sib2, iclass 3, count 2 2006.252.08:07:29.04#ibcon#*mode == 0, iclass 3, count 2 2006.252.08:07:29.04#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.252.08:07:29.04#ibcon#[25=AT04-07\r\n] 2006.252.08:07:29.04#ibcon#*before write, iclass 3, count 2 2006.252.08:07:29.04#ibcon#enter sib2, iclass 3, count 2 2006.252.08:07:29.04#ibcon#flushed, iclass 3, count 2 2006.252.08:07:29.04#ibcon#about to write, iclass 3, count 2 2006.252.08:07:29.04#ibcon#wrote, iclass 3, count 2 2006.252.08:07:29.04#ibcon#about to read 3, iclass 3, count 2 2006.252.08:07:29.07#ibcon#read 3, iclass 3, count 2 2006.252.08:07:29.07#ibcon#about to read 4, iclass 3, count 2 2006.252.08:07:29.07#ibcon#read 4, iclass 3, count 2 2006.252.08:07:29.07#ibcon#about to read 5, iclass 3, count 2 2006.252.08:07:29.07#ibcon#read 5, iclass 3, count 2 2006.252.08:07:29.07#ibcon#about to read 6, iclass 3, count 2 2006.252.08:07:29.07#ibcon#read 6, iclass 3, count 2 2006.252.08:07:29.07#ibcon#end of sib2, iclass 3, count 2 2006.252.08:07:29.07#ibcon#*after write, iclass 3, count 2 2006.252.08:07:29.07#ibcon#*before return 0, iclass 3, count 2 2006.252.08:07:29.07#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.252.08:07:29.07#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.252.08:07:29.07#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.252.08:07:29.07#ibcon#ireg 7 cls_cnt 0 2006.252.08:07:29.07#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.252.08:07:29.19#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.252.08:07:29.19#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.252.08:07:29.19#ibcon#enter wrdev, iclass 3, count 0 2006.252.08:07:29.19#ibcon#first serial, iclass 3, count 0 2006.252.08:07:29.19#ibcon#enter sib2, iclass 3, count 0 2006.252.08:07:29.19#ibcon#flushed, iclass 3, count 0 2006.252.08:07:29.19#ibcon#about to write, iclass 3, count 0 2006.252.08:07:29.19#ibcon#wrote, iclass 3, count 0 2006.252.08:07:29.19#ibcon#about to read 3, iclass 3, count 0 2006.252.08:07:29.21#ibcon#read 3, iclass 3, count 0 2006.252.08:07:29.21#ibcon#about to read 4, iclass 3, count 0 2006.252.08:07:29.21#ibcon#read 4, iclass 3, count 0 2006.252.08:07:29.21#ibcon#about to read 5, iclass 3, count 0 2006.252.08:07:29.21#ibcon#read 5, iclass 3, count 0 2006.252.08:07:29.21#ibcon#about to read 6, iclass 3, count 0 2006.252.08:07:29.21#ibcon#read 6, iclass 3, count 0 2006.252.08:07:29.21#ibcon#end of sib2, iclass 3, count 0 2006.252.08:07:29.21#ibcon#*mode == 0, iclass 3, count 0 2006.252.08:07:29.21#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.252.08:07:29.21#ibcon#[25=USB\r\n] 2006.252.08:07:29.21#ibcon#*before write, iclass 3, count 0 2006.252.08:07:29.21#ibcon#enter sib2, iclass 3, count 0 2006.252.08:07:29.21#ibcon#flushed, iclass 3, count 0 2006.252.08:07:29.21#ibcon#about to write, iclass 3, count 0 2006.252.08:07:29.21#ibcon#wrote, iclass 3, count 0 2006.252.08:07:29.21#ibcon#about to read 3, iclass 3, count 0 2006.252.08:07:29.24#ibcon#read 3, iclass 3, count 0 2006.252.08:07:29.24#ibcon#about to read 4, iclass 3, count 0 2006.252.08:07:29.24#ibcon#read 4, iclass 3, count 0 2006.252.08:07:29.24#ibcon#about to read 5, iclass 3, count 0 2006.252.08:07:29.24#ibcon#read 5, iclass 3, count 0 2006.252.08:07:29.24#ibcon#about to read 6, iclass 3, count 0 2006.252.08:07:29.24#ibcon#read 6, iclass 3, count 0 2006.252.08:07:29.24#ibcon#end of sib2, iclass 3, count 0 2006.252.08:07:29.24#ibcon#*after write, iclass 3, count 0 2006.252.08:07:29.24#ibcon#*before return 0, iclass 3, count 0 2006.252.08:07:29.24#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.252.08:07:29.24#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.252.08:07:29.24#ibcon#about to clear, iclass 3 cls_cnt 0 2006.252.08:07:29.24#ibcon#cleared, iclass 3 cls_cnt 0 2006.252.08:07:29.24$vc4f8/valo=5,652.99 2006.252.08:07:29.24#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.252.08:07:29.24#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.252.08:07:29.24#ibcon#ireg 17 cls_cnt 0 2006.252.08:07:29.24#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.252.08:07:29.24#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.252.08:07:29.24#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.252.08:07:29.24#ibcon#enter wrdev, iclass 5, count 0 2006.252.08:07:29.24#ibcon#first serial, iclass 5, count 0 2006.252.08:07:29.24#ibcon#enter sib2, iclass 5, count 0 2006.252.08:07:29.24#ibcon#flushed, iclass 5, count 0 2006.252.08:07:29.24#ibcon#about to write, iclass 5, count 0 2006.252.08:07:29.24#ibcon#wrote, iclass 5, count 0 2006.252.08:07:29.24#ibcon#about to read 3, iclass 5, count 0 2006.252.08:07:29.26#ibcon#read 3, iclass 5, count 0 2006.252.08:07:29.26#ibcon#about to read 4, iclass 5, count 0 2006.252.08:07:29.26#ibcon#read 4, iclass 5, count 0 2006.252.08:07:29.26#ibcon#about to read 5, iclass 5, count 0 2006.252.08:07:29.26#ibcon#read 5, iclass 5, count 0 2006.252.08:07:29.26#ibcon#about to read 6, iclass 5, count 0 2006.252.08:07:29.26#ibcon#read 6, iclass 5, count 0 2006.252.08:07:29.26#ibcon#end of sib2, iclass 5, count 0 2006.252.08:07:29.26#ibcon#*mode == 0, iclass 5, count 0 2006.252.08:07:29.26#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.252.08:07:29.26#ibcon#[26=FRQ=05,652.99\r\n] 2006.252.08:07:29.26#ibcon#*before write, iclass 5, count 0 2006.252.08:07:29.26#ibcon#enter sib2, iclass 5, count 0 2006.252.08:07:29.26#ibcon#flushed, iclass 5, count 0 2006.252.08:07:29.26#ibcon#about to write, iclass 5, count 0 2006.252.08:07:29.26#ibcon#wrote, iclass 5, count 0 2006.252.08:07:29.26#ibcon#about to read 3, iclass 5, count 0 2006.252.08:07:29.30#ibcon#read 3, iclass 5, count 0 2006.252.08:07:29.30#ibcon#about to read 4, iclass 5, count 0 2006.252.08:07:29.30#ibcon#read 4, iclass 5, count 0 2006.252.08:07:29.30#ibcon#about to read 5, iclass 5, count 0 2006.252.08:07:29.30#ibcon#read 5, iclass 5, count 0 2006.252.08:07:29.30#ibcon#about to read 6, iclass 5, count 0 2006.252.08:07:29.30#ibcon#read 6, iclass 5, count 0 2006.252.08:07:29.30#ibcon#end of sib2, iclass 5, count 0 2006.252.08:07:29.30#ibcon#*after write, iclass 5, count 0 2006.252.08:07:29.30#ibcon#*before return 0, iclass 5, count 0 2006.252.08:07:29.30#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.252.08:07:29.30#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.252.08:07:29.30#ibcon#about to clear, iclass 5 cls_cnt 0 2006.252.08:07:29.30#ibcon#cleared, iclass 5 cls_cnt 0 2006.252.08:07:29.30$vc4f8/va=5,7 2006.252.08:07:29.30#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.252.08:07:29.30#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.252.08:07:29.30#ibcon#ireg 11 cls_cnt 2 2006.252.08:07:29.30#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.252.08:07:29.36#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.252.08:07:29.36#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.252.08:07:29.36#ibcon#enter wrdev, iclass 7, count 2 2006.252.08:07:29.36#ibcon#first serial, iclass 7, count 2 2006.252.08:07:29.36#ibcon#enter sib2, iclass 7, count 2 2006.252.08:07:29.36#ibcon#flushed, iclass 7, count 2 2006.252.08:07:29.36#ibcon#about to write, iclass 7, count 2 2006.252.08:07:29.36#ibcon#wrote, iclass 7, count 2 2006.252.08:07:29.36#ibcon#about to read 3, iclass 7, count 2 2006.252.08:07:29.38#ibcon#read 3, iclass 7, count 2 2006.252.08:07:29.38#ibcon#about to read 4, iclass 7, count 2 2006.252.08:07:29.38#ibcon#read 4, iclass 7, count 2 2006.252.08:07:29.38#ibcon#about to read 5, iclass 7, count 2 2006.252.08:07:29.38#ibcon#read 5, iclass 7, count 2 2006.252.08:07:29.38#ibcon#about to read 6, iclass 7, count 2 2006.252.08:07:29.38#ibcon#read 6, iclass 7, count 2 2006.252.08:07:29.38#ibcon#end of sib2, iclass 7, count 2 2006.252.08:07:29.38#ibcon#*mode == 0, iclass 7, count 2 2006.252.08:07:29.38#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.252.08:07:29.38#ibcon#[25=AT05-07\r\n] 2006.252.08:07:29.38#ibcon#*before write, iclass 7, count 2 2006.252.08:07:29.38#ibcon#enter sib2, iclass 7, count 2 2006.252.08:07:29.38#ibcon#flushed, iclass 7, count 2 2006.252.08:07:29.38#ibcon#about to write, iclass 7, count 2 2006.252.08:07:29.38#ibcon#wrote, iclass 7, count 2 2006.252.08:07:29.38#ibcon#about to read 3, iclass 7, count 2 2006.252.08:07:29.41#ibcon#read 3, iclass 7, count 2 2006.252.08:07:29.41#ibcon#about to read 4, iclass 7, count 2 2006.252.08:07:29.41#ibcon#read 4, iclass 7, count 2 2006.252.08:07:29.41#ibcon#about to read 5, iclass 7, count 2 2006.252.08:07:29.41#ibcon#read 5, iclass 7, count 2 2006.252.08:07:29.41#ibcon#about to read 6, iclass 7, count 2 2006.252.08:07:29.41#ibcon#read 6, iclass 7, count 2 2006.252.08:07:29.41#ibcon#end of sib2, iclass 7, count 2 2006.252.08:07:29.41#ibcon#*after write, iclass 7, count 2 2006.252.08:07:29.41#ibcon#*before return 0, iclass 7, count 2 2006.252.08:07:29.41#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.252.08:07:29.41#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.252.08:07:29.41#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.252.08:07:29.41#ibcon#ireg 7 cls_cnt 0 2006.252.08:07:29.41#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.252.08:07:29.53#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.252.08:07:29.53#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.252.08:07:29.53#ibcon#enter wrdev, iclass 7, count 0 2006.252.08:07:29.53#ibcon#first serial, iclass 7, count 0 2006.252.08:07:29.53#ibcon#enter sib2, iclass 7, count 0 2006.252.08:07:29.53#ibcon#flushed, iclass 7, count 0 2006.252.08:07:29.53#ibcon#about to write, iclass 7, count 0 2006.252.08:07:29.53#ibcon#wrote, iclass 7, count 0 2006.252.08:07:29.53#ibcon#about to read 3, iclass 7, count 0 2006.252.08:07:29.55#ibcon#read 3, iclass 7, count 0 2006.252.08:07:29.55#ibcon#about to read 4, iclass 7, count 0 2006.252.08:07:29.55#ibcon#read 4, iclass 7, count 0 2006.252.08:07:29.55#ibcon#about to read 5, iclass 7, count 0 2006.252.08:07:29.55#ibcon#read 5, iclass 7, count 0 2006.252.08:07:29.55#ibcon#about to read 6, iclass 7, count 0 2006.252.08:07:29.55#ibcon#read 6, iclass 7, count 0 2006.252.08:07:29.55#ibcon#end of sib2, iclass 7, count 0 2006.252.08:07:29.55#ibcon#*mode == 0, iclass 7, count 0 2006.252.08:07:29.55#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.252.08:07:29.55#ibcon#[25=USB\r\n] 2006.252.08:07:29.55#ibcon#*before write, iclass 7, count 0 2006.252.08:07:29.55#ibcon#enter sib2, iclass 7, count 0 2006.252.08:07:29.55#ibcon#flushed, iclass 7, count 0 2006.252.08:07:29.55#ibcon#about to write, iclass 7, count 0 2006.252.08:07:29.55#ibcon#wrote, iclass 7, count 0 2006.252.08:07:29.55#ibcon#about to read 3, iclass 7, count 0 2006.252.08:07:29.58#ibcon#read 3, iclass 7, count 0 2006.252.08:07:29.58#ibcon#about to read 4, iclass 7, count 0 2006.252.08:07:29.58#ibcon#read 4, iclass 7, count 0 2006.252.08:07:29.58#ibcon#about to read 5, iclass 7, count 0 2006.252.08:07:29.58#ibcon#read 5, iclass 7, count 0 2006.252.08:07:29.58#ibcon#about to read 6, iclass 7, count 0 2006.252.08:07:29.58#ibcon#read 6, iclass 7, count 0 2006.252.08:07:29.58#ibcon#end of sib2, iclass 7, count 0 2006.252.08:07:29.58#ibcon#*after write, iclass 7, count 0 2006.252.08:07:29.58#ibcon#*before return 0, iclass 7, count 0 2006.252.08:07:29.58#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.252.08:07:29.58#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.252.08:07:29.58#ibcon#about to clear, iclass 7 cls_cnt 0 2006.252.08:07:29.58#ibcon#cleared, iclass 7 cls_cnt 0 2006.252.08:07:29.58$vc4f8/valo=6,772.99 2006.252.08:07:29.58#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.252.08:07:29.58#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.252.08:07:29.58#ibcon#ireg 17 cls_cnt 0 2006.252.08:07:29.58#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.252.08:07:29.58#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.252.08:07:29.58#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.252.08:07:29.58#ibcon#enter wrdev, iclass 11, count 0 2006.252.08:07:29.58#ibcon#first serial, iclass 11, count 0 2006.252.08:07:29.58#ibcon#enter sib2, iclass 11, count 0 2006.252.08:07:29.58#ibcon#flushed, iclass 11, count 0 2006.252.08:07:29.58#ibcon#about to write, iclass 11, count 0 2006.252.08:07:29.58#ibcon#wrote, iclass 11, count 0 2006.252.08:07:29.58#ibcon#about to read 3, iclass 11, count 0 2006.252.08:07:29.60#ibcon#read 3, iclass 11, count 0 2006.252.08:07:29.60#ibcon#about to read 4, iclass 11, count 0 2006.252.08:07:29.60#ibcon#read 4, iclass 11, count 0 2006.252.08:07:29.60#ibcon#about to read 5, iclass 11, count 0 2006.252.08:07:29.60#ibcon#read 5, iclass 11, count 0 2006.252.08:07:29.60#ibcon#about to read 6, iclass 11, count 0 2006.252.08:07:29.60#ibcon#read 6, iclass 11, count 0 2006.252.08:07:29.60#ibcon#end of sib2, iclass 11, count 0 2006.252.08:07:29.60#ibcon#*mode == 0, iclass 11, count 0 2006.252.08:07:29.60#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.252.08:07:29.60#ibcon#[26=FRQ=06,772.99\r\n] 2006.252.08:07:29.60#ibcon#*before write, iclass 11, count 0 2006.252.08:07:29.60#ibcon#enter sib2, iclass 11, count 0 2006.252.08:07:29.60#ibcon#flushed, iclass 11, count 0 2006.252.08:07:29.60#ibcon#about to write, iclass 11, count 0 2006.252.08:07:29.60#ibcon#wrote, iclass 11, count 0 2006.252.08:07:29.60#ibcon#about to read 3, iclass 11, count 0 2006.252.08:07:29.65#ibcon#read 3, iclass 11, count 0 2006.252.08:07:29.65#ibcon#about to read 4, iclass 11, count 0 2006.252.08:07:29.65#ibcon#read 4, iclass 11, count 0 2006.252.08:07:29.65#ibcon#about to read 5, iclass 11, count 0 2006.252.08:07:29.65#ibcon#read 5, iclass 11, count 0 2006.252.08:07:29.65#ibcon#about to read 6, iclass 11, count 0 2006.252.08:07:29.65#ibcon#read 6, iclass 11, count 0 2006.252.08:07:29.65#ibcon#end of sib2, iclass 11, count 0 2006.252.08:07:29.65#ibcon#*after write, iclass 11, count 0 2006.252.08:07:29.65#ibcon#*before return 0, iclass 11, count 0 2006.252.08:07:29.65#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.252.08:07:29.65#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.252.08:07:29.65#ibcon#about to clear, iclass 11 cls_cnt 0 2006.252.08:07:29.65#ibcon#cleared, iclass 11 cls_cnt 0 2006.252.08:07:29.65$vc4f8/va=6,7 2006.252.08:07:29.65#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.252.08:07:29.65#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.252.08:07:29.65#ibcon#ireg 11 cls_cnt 2 2006.252.08:07:29.65#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.252.08:07:29.70#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.252.08:07:29.70#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.252.08:07:29.70#ibcon#enter wrdev, iclass 13, count 2 2006.252.08:07:29.70#ibcon#first serial, iclass 13, count 2 2006.252.08:07:29.70#ibcon#enter sib2, iclass 13, count 2 2006.252.08:07:29.70#ibcon#flushed, iclass 13, count 2 2006.252.08:07:29.70#ibcon#about to write, iclass 13, count 2 2006.252.08:07:29.70#ibcon#wrote, iclass 13, count 2 2006.252.08:07:29.70#ibcon#about to read 3, iclass 13, count 2 2006.252.08:07:29.72#ibcon#read 3, iclass 13, count 2 2006.252.08:07:29.72#ibcon#about to read 4, iclass 13, count 2 2006.252.08:07:29.72#ibcon#read 4, iclass 13, count 2 2006.252.08:07:29.72#ibcon#about to read 5, iclass 13, count 2 2006.252.08:07:29.72#ibcon#read 5, iclass 13, count 2 2006.252.08:07:29.72#ibcon#about to read 6, iclass 13, count 2 2006.252.08:07:29.72#ibcon#read 6, iclass 13, count 2 2006.252.08:07:29.72#ibcon#end of sib2, iclass 13, count 2 2006.252.08:07:29.72#ibcon#*mode == 0, iclass 13, count 2 2006.252.08:07:29.72#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.252.08:07:29.72#ibcon#[25=AT06-07\r\n] 2006.252.08:07:29.72#ibcon#*before write, iclass 13, count 2 2006.252.08:07:29.72#ibcon#enter sib2, iclass 13, count 2 2006.252.08:07:29.72#ibcon#flushed, iclass 13, count 2 2006.252.08:07:29.72#ibcon#about to write, iclass 13, count 2 2006.252.08:07:29.72#ibcon#wrote, iclass 13, count 2 2006.252.08:07:29.72#ibcon#about to read 3, iclass 13, count 2 2006.252.08:07:29.75#ibcon#read 3, iclass 13, count 2 2006.252.08:07:29.75#ibcon#about to read 4, iclass 13, count 2 2006.252.08:07:29.75#ibcon#read 4, iclass 13, count 2 2006.252.08:07:29.75#ibcon#about to read 5, iclass 13, count 2 2006.252.08:07:29.75#ibcon#read 5, iclass 13, count 2 2006.252.08:07:29.75#ibcon#about to read 6, iclass 13, count 2 2006.252.08:07:29.75#ibcon#read 6, iclass 13, count 2 2006.252.08:07:29.75#ibcon#end of sib2, iclass 13, count 2 2006.252.08:07:29.75#ibcon#*after write, iclass 13, count 2 2006.252.08:07:29.75#ibcon#*before return 0, iclass 13, count 2 2006.252.08:07:29.75#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.252.08:07:29.75#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.252.08:07:29.75#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.252.08:07:29.75#ibcon#ireg 7 cls_cnt 0 2006.252.08:07:29.75#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.252.08:07:29.87#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.252.08:07:29.87#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.252.08:07:29.87#ibcon#enter wrdev, iclass 13, count 0 2006.252.08:07:29.87#ibcon#first serial, iclass 13, count 0 2006.252.08:07:29.87#ibcon#enter sib2, iclass 13, count 0 2006.252.08:07:29.87#ibcon#flushed, iclass 13, count 0 2006.252.08:07:29.87#ibcon#about to write, iclass 13, count 0 2006.252.08:07:29.87#ibcon#wrote, iclass 13, count 0 2006.252.08:07:29.87#ibcon#about to read 3, iclass 13, count 0 2006.252.08:07:29.89#ibcon#read 3, iclass 13, count 0 2006.252.08:07:29.89#ibcon#about to read 4, iclass 13, count 0 2006.252.08:07:29.89#ibcon#read 4, iclass 13, count 0 2006.252.08:07:29.89#ibcon#about to read 5, iclass 13, count 0 2006.252.08:07:29.89#ibcon#read 5, iclass 13, count 0 2006.252.08:07:29.89#ibcon#about to read 6, iclass 13, count 0 2006.252.08:07:29.89#ibcon#read 6, iclass 13, count 0 2006.252.08:07:29.89#ibcon#end of sib2, iclass 13, count 0 2006.252.08:07:29.89#ibcon#*mode == 0, iclass 13, count 0 2006.252.08:07:29.89#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.252.08:07:29.89#ibcon#[25=USB\r\n] 2006.252.08:07:29.89#ibcon#*before write, iclass 13, count 0 2006.252.08:07:29.89#ibcon#enter sib2, iclass 13, count 0 2006.252.08:07:29.89#ibcon#flushed, iclass 13, count 0 2006.252.08:07:29.89#ibcon#about to write, iclass 13, count 0 2006.252.08:07:29.89#ibcon#wrote, iclass 13, count 0 2006.252.08:07:29.89#ibcon#about to read 3, iclass 13, count 0 2006.252.08:07:29.92#ibcon#read 3, iclass 13, count 0 2006.252.08:07:29.92#ibcon#about to read 4, iclass 13, count 0 2006.252.08:07:29.92#ibcon#read 4, iclass 13, count 0 2006.252.08:07:29.92#ibcon#about to read 5, iclass 13, count 0 2006.252.08:07:29.92#ibcon#read 5, iclass 13, count 0 2006.252.08:07:29.92#ibcon#about to read 6, iclass 13, count 0 2006.252.08:07:29.92#ibcon#read 6, iclass 13, count 0 2006.252.08:07:29.92#ibcon#end of sib2, iclass 13, count 0 2006.252.08:07:29.92#ibcon#*after write, iclass 13, count 0 2006.252.08:07:29.92#ibcon#*before return 0, iclass 13, count 0 2006.252.08:07:29.92#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.252.08:07:29.92#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.252.08:07:29.92#ibcon#about to clear, iclass 13 cls_cnt 0 2006.252.08:07:29.92#ibcon#cleared, iclass 13 cls_cnt 0 2006.252.08:07:29.92$vc4f8/valo=7,832.99 2006.252.08:07:29.92#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.252.08:07:29.92#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.252.08:07:29.92#ibcon#ireg 17 cls_cnt 0 2006.252.08:07:29.92#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.252.08:07:29.92#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.252.08:07:29.92#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.252.08:07:29.92#ibcon#enter wrdev, iclass 15, count 0 2006.252.08:07:29.92#ibcon#first serial, iclass 15, count 0 2006.252.08:07:29.92#ibcon#enter sib2, iclass 15, count 0 2006.252.08:07:29.92#ibcon#flushed, iclass 15, count 0 2006.252.08:07:29.92#ibcon#about to write, iclass 15, count 0 2006.252.08:07:29.92#ibcon#wrote, iclass 15, count 0 2006.252.08:07:29.92#ibcon#about to read 3, iclass 15, count 0 2006.252.08:07:29.94#ibcon#read 3, iclass 15, count 0 2006.252.08:07:29.94#ibcon#about to read 4, iclass 15, count 0 2006.252.08:07:29.94#ibcon#read 4, iclass 15, count 0 2006.252.08:07:29.94#ibcon#about to read 5, iclass 15, count 0 2006.252.08:07:29.94#ibcon#read 5, iclass 15, count 0 2006.252.08:07:29.94#ibcon#about to read 6, iclass 15, count 0 2006.252.08:07:29.94#ibcon#read 6, iclass 15, count 0 2006.252.08:07:29.94#ibcon#end of sib2, iclass 15, count 0 2006.252.08:07:29.94#ibcon#*mode == 0, iclass 15, count 0 2006.252.08:07:29.94#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.252.08:07:29.94#ibcon#[26=FRQ=07,832.99\r\n] 2006.252.08:07:29.94#ibcon#*before write, iclass 15, count 0 2006.252.08:07:29.94#ibcon#enter sib2, iclass 15, count 0 2006.252.08:07:29.94#ibcon#flushed, iclass 15, count 0 2006.252.08:07:29.94#ibcon#about to write, iclass 15, count 0 2006.252.08:07:29.94#ibcon#wrote, iclass 15, count 0 2006.252.08:07:29.94#ibcon#about to read 3, iclass 15, count 0 2006.252.08:07:29.98#ibcon#read 3, iclass 15, count 0 2006.252.08:07:29.98#ibcon#about to read 4, iclass 15, count 0 2006.252.08:07:29.98#ibcon#read 4, iclass 15, count 0 2006.252.08:07:29.98#ibcon#about to read 5, iclass 15, count 0 2006.252.08:07:29.98#ibcon#read 5, iclass 15, count 0 2006.252.08:07:29.98#ibcon#about to read 6, iclass 15, count 0 2006.252.08:07:29.98#ibcon#read 6, iclass 15, count 0 2006.252.08:07:29.98#ibcon#end of sib2, iclass 15, count 0 2006.252.08:07:29.98#ibcon#*after write, iclass 15, count 0 2006.252.08:07:29.98#ibcon#*before return 0, iclass 15, count 0 2006.252.08:07:29.98#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.252.08:07:29.98#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.252.08:07:29.98#ibcon#about to clear, iclass 15 cls_cnt 0 2006.252.08:07:29.98#ibcon#cleared, iclass 15 cls_cnt 0 2006.252.08:07:29.98$vc4f8/va=7,7 2006.252.08:07:29.98#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.252.08:07:29.98#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.252.08:07:29.98#ibcon#ireg 11 cls_cnt 2 2006.252.08:07:29.98#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.252.08:07:30.04#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.252.08:07:30.04#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.252.08:07:30.04#ibcon#enter wrdev, iclass 17, count 2 2006.252.08:07:30.04#ibcon#first serial, iclass 17, count 2 2006.252.08:07:30.04#ibcon#enter sib2, iclass 17, count 2 2006.252.08:07:30.04#ibcon#flushed, iclass 17, count 2 2006.252.08:07:30.04#ibcon#about to write, iclass 17, count 2 2006.252.08:07:30.04#ibcon#wrote, iclass 17, count 2 2006.252.08:07:30.04#ibcon#about to read 3, iclass 17, count 2 2006.252.08:07:30.06#ibcon#read 3, iclass 17, count 2 2006.252.08:07:30.06#ibcon#about to read 4, iclass 17, count 2 2006.252.08:07:30.06#ibcon#read 4, iclass 17, count 2 2006.252.08:07:30.06#ibcon#about to read 5, iclass 17, count 2 2006.252.08:07:30.06#ibcon#read 5, iclass 17, count 2 2006.252.08:07:30.06#ibcon#about to read 6, iclass 17, count 2 2006.252.08:07:30.06#ibcon#read 6, iclass 17, count 2 2006.252.08:07:30.06#ibcon#end of sib2, iclass 17, count 2 2006.252.08:07:30.06#ibcon#*mode == 0, iclass 17, count 2 2006.252.08:07:30.06#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.252.08:07:30.06#ibcon#[25=AT07-07\r\n] 2006.252.08:07:30.06#ibcon#*before write, iclass 17, count 2 2006.252.08:07:30.06#ibcon#enter sib2, iclass 17, count 2 2006.252.08:07:30.06#ibcon#flushed, iclass 17, count 2 2006.252.08:07:30.06#ibcon#about to write, iclass 17, count 2 2006.252.08:07:30.06#ibcon#wrote, iclass 17, count 2 2006.252.08:07:30.06#ibcon#about to read 3, iclass 17, count 2 2006.252.08:07:30.09#ibcon#read 3, iclass 17, count 2 2006.252.08:07:30.09#ibcon#about to read 4, iclass 17, count 2 2006.252.08:07:30.09#ibcon#read 4, iclass 17, count 2 2006.252.08:07:30.09#ibcon#about to read 5, iclass 17, count 2 2006.252.08:07:30.09#ibcon#read 5, iclass 17, count 2 2006.252.08:07:30.09#ibcon#about to read 6, iclass 17, count 2 2006.252.08:07:30.09#ibcon#read 6, iclass 17, count 2 2006.252.08:07:30.09#ibcon#end of sib2, iclass 17, count 2 2006.252.08:07:30.09#ibcon#*after write, iclass 17, count 2 2006.252.08:07:30.09#ibcon#*before return 0, iclass 17, count 2 2006.252.08:07:30.09#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.252.08:07:30.09#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.252.08:07:30.09#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.252.08:07:30.09#ibcon#ireg 7 cls_cnt 0 2006.252.08:07:30.09#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.252.08:07:30.21#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.252.08:07:30.21#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.252.08:07:30.21#ibcon#enter wrdev, iclass 17, count 0 2006.252.08:07:30.21#ibcon#first serial, iclass 17, count 0 2006.252.08:07:30.21#ibcon#enter sib2, iclass 17, count 0 2006.252.08:07:30.21#ibcon#flushed, iclass 17, count 0 2006.252.08:07:30.21#ibcon#about to write, iclass 17, count 0 2006.252.08:07:30.21#ibcon#wrote, iclass 17, count 0 2006.252.08:07:30.21#ibcon#about to read 3, iclass 17, count 0 2006.252.08:07:30.23#ibcon#read 3, iclass 17, count 0 2006.252.08:07:30.23#ibcon#about to read 4, iclass 17, count 0 2006.252.08:07:30.23#ibcon#read 4, iclass 17, count 0 2006.252.08:07:30.23#ibcon#about to read 5, iclass 17, count 0 2006.252.08:07:30.23#ibcon#read 5, iclass 17, count 0 2006.252.08:07:30.23#ibcon#about to read 6, iclass 17, count 0 2006.252.08:07:30.23#ibcon#read 6, iclass 17, count 0 2006.252.08:07:30.23#ibcon#end of sib2, iclass 17, count 0 2006.252.08:07:30.23#ibcon#*mode == 0, iclass 17, count 0 2006.252.08:07:30.23#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.252.08:07:30.23#ibcon#[25=USB\r\n] 2006.252.08:07:30.23#ibcon#*before write, iclass 17, count 0 2006.252.08:07:30.23#ibcon#enter sib2, iclass 17, count 0 2006.252.08:07:30.23#ibcon#flushed, iclass 17, count 0 2006.252.08:07:30.23#ibcon#about to write, iclass 17, count 0 2006.252.08:07:30.23#ibcon#wrote, iclass 17, count 0 2006.252.08:07:30.23#ibcon#about to read 3, iclass 17, count 0 2006.252.08:07:30.26#ibcon#read 3, iclass 17, count 0 2006.252.08:07:30.26#ibcon#about to read 4, iclass 17, count 0 2006.252.08:07:30.26#ibcon#read 4, iclass 17, count 0 2006.252.08:07:30.26#ibcon#about to read 5, iclass 17, count 0 2006.252.08:07:30.26#ibcon#read 5, iclass 17, count 0 2006.252.08:07:30.26#ibcon#about to read 6, iclass 17, count 0 2006.252.08:07:30.26#ibcon#read 6, iclass 17, count 0 2006.252.08:07:30.26#ibcon#end of sib2, iclass 17, count 0 2006.252.08:07:30.26#ibcon#*after write, iclass 17, count 0 2006.252.08:07:30.26#ibcon#*before return 0, iclass 17, count 0 2006.252.08:07:30.26#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.252.08:07:30.26#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.252.08:07:30.26#ibcon#about to clear, iclass 17 cls_cnt 0 2006.252.08:07:30.26#ibcon#cleared, iclass 17 cls_cnt 0 2006.252.08:07:30.26$vc4f8/valo=8,852.99 2006.252.08:07:30.26#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.252.08:07:30.26#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.252.08:07:30.26#ibcon#ireg 17 cls_cnt 0 2006.252.08:07:30.26#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.252.08:07:30.26#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.252.08:07:30.26#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.252.08:07:30.26#ibcon#enter wrdev, iclass 19, count 0 2006.252.08:07:30.26#ibcon#first serial, iclass 19, count 0 2006.252.08:07:30.26#ibcon#enter sib2, iclass 19, count 0 2006.252.08:07:30.26#ibcon#flushed, iclass 19, count 0 2006.252.08:07:30.26#ibcon#about to write, iclass 19, count 0 2006.252.08:07:30.26#ibcon#wrote, iclass 19, count 0 2006.252.08:07:30.26#ibcon#about to read 3, iclass 19, count 0 2006.252.08:07:30.28#ibcon#read 3, iclass 19, count 0 2006.252.08:07:30.28#ibcon#about to read 4, iclass 19, count 0 2006.252.08:07:30.28#ibcon#read 4, iclass 19, count 0 2006.252.08:07:30.28#ibcon#about to read 5, iclass 19, count 0 2006.252.08:07:30.28#ibcon#read 5, iclass 19, count 0 2006.252.08:07:30.28#ibcon#about to read 6, iclass 19, count 0 2006.252.08:07:30.28#ibcon#read 6, iclass 19, count 0 2006.252.08:07:30.28#ibcon#end of sib2, iclass 19, count 0 2006.252.08:07:30.28#ibcon#*mode == 0, iclass 19, count 0 2006.252.08:07:30.28#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.252.08:07:30.28#ibcon#[26=FRQ=08,852.99\r\n] 2006.252.08:07:30.28#ibcon#*before write, iclass 19, count 0 2006.252.08:07:30.28#ibcon#enter sib2, iclass 19, count 0 2006.252.08:07:30.28#ibcon#flushed, iclass 19, count 0 2006.252.08:07:30.28#ibcon#about to write, iclass 19, count 0 2006.252.08:07:30.28#ibcon#wrote, iclass 19, count 0 2006.252.08:07:30.28#ibcon#about to read 3, iclass 19, count 0 2006.252.08:07:30.32#ibcon#read 3, iclass 19, count 0 2006.252.08:07:30.32#ibcon#about to read 4, iclass 19, count 0 2006.252.08:07:30.32#ibcon#read 4, iclass 19, count 0 2006.252.08:07:30.32#ibcon#about to read 5, iclass 19, count 0 2006.252.08:07:30.32#ibcon#read 5, iclass 19, count 0 2006.252.08:07:30.32#ibcon#about to read 6, iclass 19, count 0 2006.252.08:07:30.32#ibcon#read 6, iclass 19, count 0 2006.252.08:07:30.32#ibcon#end of sib2, iclass 19, count 0 2006.252.08:07:30.32#ibcon#*after write, iclass 19, count 0 2006.252.08:07:30.32#ibcon#*before return 0, iclass 19, count 0 2006.252.08:07:30.32#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.252.08:07:30.32#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.252.08:07:30.32#ibcon#about to clear, iclass 19 cls_cnt 0 2006.252.08:07:30.32#ibcon#cleared, iclass 19 cls_cnt 0 2006.252.08:07:30.32$vc4f8/va=8,7 2006.252.08:07:30.32#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.252.08:07:30.32#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.252.08:07:30.32#ibcon#ireg 11 cls_cnt 2 2006.252.08:07:30.32#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.252.08:07:30.38#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.252.08:07:30.38#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.252.08:07:30.38#ibcon#enter wrdev, iclass 21, count 2 2006.252.08:07:30.38#ibcon#first serial, iclass 21, count 2 2006.252.08:07:30.38#ibcon#enter sib2, iclass 21, count 2 2006.252.08:07:30.38#ibcon#flushed, iclass 21, count 2 2006.252.08:07:30.38#ibcon#about to write, iclass 21, count 2 2006.252.08:07:30.38#ibcon#wrote, iclass 21, count 2 2006.252.08:07:30.38#ibcon#about to read 3, iclass 21, count 2 2006.252.08:07:30.40#ibcon#read 3, iclass 21, count 2 2006.252.08:07:30.40#ibcon#about to read 4, iclass 21, count 2 2006.252.08:07:30.40#ibcon#read 4, iclass 21, count 2 2006.252.08:07:30.40#ibcon#about to read 5, iclass 21, count 2 2006.252.08:07:30.40#ibcon#read 5, iclass 21, count 2 2006.252.08:07:30.40#ibcon#about to read 6, iclass 21, count 2 2006.252.08:07:30.40#ibcon#read 6, iclass 21, count 2 2006.252.08:07:30.40#ibcon#end of sib2, iclass 21, count 2 2006.252.08:07:30.40#ibcon#*mode == 0, iclass 21, count 2 2006.252.08:07:30.40#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.252.08:07:30.40#ibcon#[25=AT08-07\r\n] 2006.252.08:07:30.40#ibcon#*before write, iclass 21, count 2 2006.252.08:07:30.40#ibcon#enter sib2, iclass 21, count 2 2006.252.08:07:30.40#ibcon#flushed, iclass 21, count 2 2006.252.08:07:30.40#ibcon#about to write, iclass 21, count 2 2006.252.08:07:30.40#ibcon#wrote, iclass 21, count 2 2006.252.08:07:30.40#ibcon#about to read 3, iclass 21, count 2 2006.252.08:07:30.43#ibcon#read 3, iclass 21, count 2 2006.252.08:07:30.43#ibcon#about to read 4, iclass 21, count 2 2006.252.08:07:30.43#ibcon#read 4, iclass 21, count 2 2006.252.08:07:30.43#ibcon#about to read 5, iclass 21, count 2 2006.252.08:07:30.43#ibcon#read 5, iclass 21, count 2 2006.252.08:07:30.43#ibcon#about to read 6, iclass 21, count 2 2006.252.08:07:30.43#ibcon#read 6, iclass 21, count 2 2006.252.08:07:30.43#ibcon#end of sib2, iclass 21, count 2 2006.252.08:07:30.43#ibcon#*after write, iclass 21, count 2 2006.252.08:07:30.43#ibcon#*before return 0, iclass 21, count 2 2006.252.08:07:30.43#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.252.08:07:30.43#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.252.08:07:30.43#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.252.08:07:30.43#ibcon#ireg 7 cls_cnt 0 2006.252.08:07:30.43#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.252.08:07:30.55#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.252.08:07:30.55#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.252.08:07:30.55#ibcon#enter wrdev, iclass 21, count 0 2006.252.08:07:30.55#ibcon#first serial, iclass 21, count 0 2006.252.08:07:30.55#ibcon#enter sib2, iclass 21, count 0 2006.252.08:07:30.55#ibcon#flushed, iclass 21, count 0 2006.252.08:07:30.55#ibcon#about to write, iclass 21, count 0 2006.252.08:07:30.55#ibcon#wrote, iclass 21, count 0 2006.252.08:07:30.55#ibcon#about to read 3, iclass 21, count 0 2006.252.08:07:30.57#ibcon#read 3, iclass 21, count 0 2006.252.08:07:30.57#ibcon#about to read 4, iclass 21, count 0 2006.252.08:07:30.57#ibcon#read 4, iclass 21, count 0 2006.252.08:07:30.57#ibcon#about to read 5, iclass 21, count 0 2006.252.08:07:30.57#ibcon#read 5, iclass 21, count 0 2006.252.08:07:30.57#ibcon#about to read 6, iclass 21, count 0 2006.252.08:07:30.57#ibcon#read 6, iclass 21, count 0 2006.252.08:07:30.57#ibcon#end of sib2, iclass 21, count 0 2006.252.08:07:30.57#ibcon#*mode == 0, iclass 21, count 0 2006.252.08:07:30.57#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.252.08:07:30.57#ibcon#[25=USB\r\n] 2006.252.08:07:30.57#ibcon#*before write, iclass 21, count 0 2006.252.08:07:30.57#ibcon#enter sib2, iclass 21, count 0 2006.252.08:07:30.57#ibcon#flushed, iclass 21, count 0 2006.252.08:07:30.57#ibcon#about to write, iclass 21, count 0 2006.252.08:07:30.57#ibcon#wrote, iclass 21, count 0 2006.252.08:07:30.57#ibcon#about to read 3, iclass 21, count 0 2006.252.08:07:30.60#ibcon#read 3, iclass 21, count 0 2006.252.08:07:30.60#ibcon#about to read 4, iclass 21, count 0 2006.252.08:07:30.60#ibcon#read 4, iclass 21, count 0 2006.252.08:07:30.60#ibcon#about to read 5, iclass 21, count 0 2006.252.08:07:30.60#ibcon#read 5, iclass 21, count 0 2006.252.08:07:30.60#ibcon#about to read 6, iclass 21, count 0 2006.252.08:07:30.60#ibcon#read 6, iclass 21, count 0 2006.252.08:07:30.60#ibcon#end of sib2, iclass 21, count 0 2006.252.08:07:30.60#ibcon#*after write, iclass 21, count 0 2006.252.08:07:30.60#ibcon#*before return 0, iclass 21, count 0 2006.252.08:07:30.60#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.252.08:07:30.60#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.252.08:07:30.60#ibcon#about to clear, iclass 21 cls_cnt 0 2006.252.08:07:30.60#ibcon#cleared, iclass 21 cls_cnt 0 2006.252.08:07:30.60$vc4f8/vblo=1,632.99 2006.252.08:07:30.60#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.252.08:07:30.60#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.252.08:07:30.60#ibcon#ireg 17 cls_cnt 0 2006.252.08:07:30.60#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.252.08:07:30.60#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.252.08:07:30.60#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.252.08:07:30.60#ibcon#enter wrdev, iclass 23, count 0 2006.252.08:07:30.60#ibcon#first serial, iclass 23, count 0 2006.252.08:07:30.60#ibcon#enter sib2, iclass 23, count 0 2006.252.08:07:30.60#ibcon#flushed, iclass 23, count 0 2006.252.08:07:30.60#ibcon#about to write, iclass 23, count 0 2006.252.08:07:30.60#ibcon#wrote, iclass 23, count 0 2006.252.08:07:30.60#ibcon#about to read 3, iclass 23, count 0 2006.252.08:07:30.62#ibcon#read 3, iclass 23, count 0 2006.252.08:07:30.62#ibcon#about to read 4, iclass 23, count 0 2006.252.08:07:30.62#ibcon#read 4, iclass 23, count 0 2006.252.08:07:30.62#ibcon#about to read 5, iclass 23, count 0 2006.252.08:07:30.62#ibcon#read 5, iclass 23, count 0 2006.252.08:07:30.62#ibcon#about to read 6, iclass 23, count 0 2006.252.08:07:30.62#ibcon#read 6, iclass 23, count 0 2006.252.08:07:30.62#ibcon#end of sib2, iclass 23, count 0 2006.252.08:07:30.62#ibcon#*mode == 0, iclass 23, count 0 2006.252.08:07:30.62#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.252.08:07:30.62#ibcon#[28=FRQ=01,632.99\r\n] 2006.252.08:07:30.62#ibcon#*before write, iclass 23, count 0 2006.252.08:07:30.62#ibcon#enter sib2, iclass 23, count 0 2006.252.08:07:30.62#ibcon#flushed, iclass 23, count 0 2006.252.08:07:30.62#ibcon#about to write, iclass 23, count 0 2006.252.08:07:30.62#ibcon#wrote, iclass 23, count 0 2006.252.08:07:30.62#ibcon#about to read 3, iclass 23, count 0 2006.252.08:07:30.66#ibcon#read 3, iclass 23, count 0 2006.252.08:07:30.66#ibcon#about to read 4, iclass 23, count 0 2006.252.08:07:30.66#ibcon#read 4, iclass 23, count 0 2006.252.08:07:30.66#ibcon#about to read 5, iclass 23, count 0 2006.252.08:07:30.66#ibcon#read 5, iclass 23, count 0 2006.252.08:07:30.66#ibcon#about to read 6, iclass 23, count 0 2006.252.08:07:30.66#ibcon#read 6, iclass 23, count 0 2006.252.08:07:30.66#ibcon#end of sib2, iclass 23, count 0 2006.252.08:07:30.66#ibcon#*after write, iclass 23, count 0 2006.252.08:07:30.66#ibcon#*before return 0, iclass 23, count 0 2006.252.08:07:30.66#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.252.08:07:30.66#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.252.08:07:30.66#ibcon#about to clear, iclass 23 cls_cnt 0 2006.252.08:07:30.66#ibcon#cleared, iclass 23 cls_cnt 0 2006.252.08:07:30.66$vc4f8/vb=1,4 2006.252.08:07:30.66#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.252.08:07:30.66#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.252.08:07:30.66#ibcon#ireg 11 cls_cnt 2 2006.252.08:07:30.66#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.252.08:07:30.66#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.252.08:07:30.66#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.252.08:07:30.66#ibcon#enter wrdev, iclass 25, count 2 2006.252.08:07:30.66#ibcon#first serial, iclass 25, count 2 2006.252.08:07:30.66#ibcon#enter sib2, iclass 25, count 2 2006.252.08:07:30.66#ibcon#flushed, iclass 25, count 2 2006.252.08:07:30.66#ibcon#about to write, iclass 25, count 2 2006.252.08:07:30.66#ibcon#wrote, iclass 25, count 2 2006.252.08:07:30.66#ibcon#about to read 3, iclass 25, count 2 2006.252.08:07:30.68#ibcon#read 3, iclass 25, count 2 2006.252.08:07:30.68#ibcon#about to read 4, iclass 25, count 2 2006.252.08:07:30.68#ibcon#read 4, iclass 25, count 2 2006.252.08:07:30.68#ibcon#about to read 5, iclass 25, count 2 2006.252.08:07:30.68#ibcon#read 5, iclass 25, count 2 2006.252.08:07:30.68#ibcon#about to read 6, iclass 25, count 2 2006.252.08:07:30.68#ibcon#read 6, iclass 25, count 2 2006.252.08:07:30.68#ibcon#end of sib2, iclass 25, count 2 2006.252.08:07:30.68#ibcon#*mode == 0, iclass 25, count 2 2006.252.08:07:30.68#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.252.08:07:30.68#ibcon#[27=AT01-04\r\n] 2006.252.08:07:30.68#ibcon#*before write, iclass 25, count 2 2006.252.08:07:30.68#ibcon#enter sib2, iclass 25, count 2 2006.252.08:07:30.68#ibcon#flushed, iclass 25, count 2 2006.252.08:07:30.68#ibcon#about to write, iclass 25, count 2 2006.252.08:07:30.68#ibcon#wrote, iclass 25, count 2 2006.252.08:07:30.68#ibcon#about to read 3, iclass 25, count 2 2006.252.08:07:30.71#ibcon#read 3, iclass 25, count 2 2006.252.08:07:30.71#ibcon#about to read 4, iclass 25, count 2 2006.252.08:07:30.71#ibcon#read 4, iclass 25, count 2 2006.252.08:07:30.71#ibcon#about to read 5, iclass 25, count 2 2006.252.08:07:30.71#ibcon#read 5, iclass 25, count 2 2006.252.08:07:30.71#ibcon#about to read 6, iclass 25, count 2 2006.252.08:07:30.71#ibcon#read 6, iclass 25, count 2 2006.252.08:07:30.71#ibcon#end of sib2, iclass 25, count 2 2006.252.08:07:30.71#ibcon#*after write, iclass 25, count 2 2006.252.08:07:30.71#ibcon#*before return 0, iclass 25, count 2 2006.252.08:07:30.71#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.252.08:07:30.71#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.252.08:07:30.71#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.252.08:07:30.71#ibcon#ireg 7 cls_cnt 0 2006.252.08:07:30.71#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.252.08:07:30.83#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.252.08:07:30.83#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.252.08:07:30.83#ibcon#enter wrdev, iclass 25, count 0 2006.252.08:07:30.83#ibcon#first serial, iclass 25, count 0 2006.252.08:07:30.83#ibcon#enter sib2, iclass 25, count 0 2006.252.08:07:30.83#ibcon#flushed, iclass 25, count 0 2006.252.08:07:30.83#ibcon#about to write, iclass 25, count 0 2006.252.08:07:30.83#ibcon#wrote, iclass 25, count 0 2006.252.08:07:30.83#ibcon#about to read 3, iclass 25, count 0 2006.252.08:07:30.85#ibcon#read 3, iclass 25, count 0 2006.252.08:07:30.85#ibcon#about to read 4, iclass 25, count 0 2006.252.08:07:30.85#ibcon#read 4, iclass 25, count 0 2006.252.08:07:30.85#ibcon#about to read 5, iclass 25, count 0 2006.252.08:07:30.85#ibcon#read 5, iclass 25, count 0 2006.252.08:07:30.85#ibcon#about to read 6, iclass 25, count 0 2006.252.08:07:30.85#ibcon#read 6, iclass 25, count 0 2006.252.08:07:30.85#ibcon#end of sib2, iclass 25, count 0 2006.252.08:07:30.85#ibcon#*mode == 0, iclass 25, count 0 2006.252.08:07:30.85#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.252.08:07:30.85#ibcon#[27=USB\r\n] 2006.252.08:07:30.85#ibcon#*before write, iclass 25, count 0 2006.252.08:07:30.85#ibcon#enter sib2, iclass 25, count 0 2006.252.08:07:30.85#ibcon#flushed, iclass 25, count 0 2006.252.08:07:30.85#ibcon#about to write, iclass 25, count 0 2006.252.08:07:30.85#ibcon#wrote, iclass 25, count 0 2006.252.08:07:30.85#ibcon#about to read 3, iclass 25, count 0 2006.252.08:07:30.88#ibcon#read 3, iclass 25, count 0 2006.252.08:07:30.88#ibcon#about to read 4, iclass 25, count 0 2006.252.08:07:30.88#ibcon#read 4, iclass 25, count 0 2006.252.08:07:30.88#ibcon#about to read 5, iclass 25, count 0 2006.252.08:07:30.88#ibcon#read 5, iclass 25, count 0 2006.252.08:07:30.88#ibcon#about to read 6, iclass 25, count 0 2006.252.08:07:30.88#ibcon#read 6, iclass 25, count 0 2006.252.08:07:30.88#ibcon#end of sib2, iclass 25, count 0 2006.252.08:07:30.88#ibcon#*after write, iclass 25, count 0 2006.252.08:07:30.88#ibcon#*before return 0, iclass 25, count 0 2006.252.08:07:30.88#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.252.08:07:30.88#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.252.08:07:30.88#ibcon#about to clear, iclass 25 cls_cnt 0 2006.252.08:07:30.88#ibcon#cleared, iclass 25 cls_cnt 0 2006.252.08:07:30.88$vc4f8/vblo=2,640.99 2006.252.08:07:30.88#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.252.08:07:30.88#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.252.08:07:30.88#ibcon#ireg 17 cls_cnt 0 2006.252.08:07:30.88#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.252.08:07:30.88#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.252.08:07:30.88#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.252.08:07:30.88#ibcon#enter wrdev, iclass 27, count 0 2006.252.08:07:30.88#ibcon#first serial, iclass 27, count 0 2006.252.08:07:30.88#ibcon#enter sib2, iclass 27, count 0 2006.252.08:07:30.88#ibcon#flushed, iclass 27, count 0 2006.252.08:07:30.88#ibcon#about to write, iclass 27, count 0 2006.252.08:07:30.88#ibcon#wrote, iclass 27, count 0 2006.252.08:07:30.88#ibcon#about to read 3, iclass 27, count 0 2006.252.08:07:30.90#ibcon#read 3, iclass 27, count 0 2006.252.08:07:30.90#ibcon#about to read 4, iclass 27, count 0 2006.252.08:07:30.90#ibcon#read 4, iclass 27, count 0 2006.252.08:07:30.90#ibcon#about to read 5, iclass 27, count 0 2006.252.08:07:30.90#ibcon#read 5, iclass 27, count 0 2006.252.08:07:30.90#ibcon#about to read 6, iclass 27, count 0 2006.252.08:07:30.90#ibcon#read 6, iclass 27, count 0 2006.252.08:07:30.90#ibcon#end of sib2, iclass 27, count 0 2006.252.08:07:30.90#ibcon#*mode == 0, iclass 27, count 0 2006.252.08:07:30.90#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.252.08:07:30.90#ibcon#[28=FRQ=02,640.99\r\n] 2006.252.08:07:30.90#ibcon#*before write, iclass 27, count 0 2006.252.08:07:30.90#ibcon#enter sib2, iclass 27, count 0 2006.252.08:07:30.90#ibcon#flushed, iclass 27, count 0 2006.252.08:07:30.90#ibcon#about to write, iclass 27, count 0 2006.252.08:07:30.90#ibcon#wrote, iclass 27, count 0 2006.252.08:07:30.90#ibcon#about to read 3, iclass 27, count 0 2006.252.08:07:30.94#ibcon#read 3, iclass 27, count 0 2006.252.08:07:30.94#ibcon#about to read 4, iclass 27, count 0 2006.252.08:07:30.94#ibcon#read 4, iclass 27, count 0 2006.252.08:07:30.94#ibcon#about to read 5, iclass 27, count 0 2006.252.08:07:30.94#ibcon#read 5, iclass 27, count 0 2006.252.08:07:30.94#ibcon#about to read 6, iclass 27, count 0 2006.252.08:07:30.94#ibcon#read 6, iclass 27, count 0 2006.252.08:07:30.94#ibcon#end of sib2, iclass 27, count 0 2006.252.08:07:30.94#ibcon#*after write, iclass 27, count 0 2006.252.08:07:30.94#ibcon#*before return 0, iclass 27, count 0 2006.252.08:07:30.94#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.252.08:07:30.94#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.252.08:07:30.94#ibcon#about to clear, iclass 27 cls_cnt 0 2006.252.08:07:30.94#ibcon#cleared, iclass 27 cls_cnt 0 2006.252.08:07:30.94$vc4f8/vb=2,5 2006.252.08:07:30.94#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.252.08:07:30.94#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.252.08:07:30.94#ibcon#ireg 11 cls_cnt 2 2006.252.08:07:30.94#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.252.08:07:31.00#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.252.08:07:31.00#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.252.08:07:31.00#ibcon#enter wrdev, iclass 29, count 2 2006.252.08:07:31.00#ibcon#first serial, iclass 29, count 2 2006.252.08:07:31.00#ibcon#enter sib2, iclass 29, count 2 2006.252.08:07:31.00#ibcon#flushed, iclass 29, count 2 2006.252.08:07:31.00#ibcon#about to write, iclass 29, count 2 2006.252.08:07:31.00#ibcon#wrote, iclass 29, count 2 2006.252.08:07:31.00#ibcon#about to read 3, iclass 29, count 2 2006.252.08:07:31.02#ibcon#read 3, iclass 29, count 2 2006.252.08:07:31.02#ibcon#about to read 4, iclass 29, count 2 2006.252.08:07:31.02#ibcon#read 4, iclass 29, count 2 2006.252.08:07:31.02#ibcon#about to read 5, iclass 29, count 2 2006.252.08:07:31.02#ibcon#read 5, iclass 29, count 2 2006.252.08:07:31.02#ibcon#about to read 6, iclass 29, count 2 2006.252.08:07:31.02#ibcon#read 6, iclass 29, count 2 2006.252.08:07:31.02#ibcon#end of sib2, iclass 29, count 2 2006.252.08:07:31.02#ibcon#*mode == 0, iclass 29, count 2 2006.252.08:07:31.02#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.252.08:07:31.02#ibcon#[27=AT02-05\r\n] 2006.252.08:07:31.02#ibcon#*before write, iclass 29, count 2 2006.252.08:07:31.02#ibcon#enter sib2, iclass 29, count 2 2006.252.08:07:31.02#ibcon#flushed, iclass 29, count 2 2006.252.08:07:31.02#ibcon#about to write, iclass 29, count 2 2006.252.08:07:31.02#ibcon#wrote, iclass 29, count 2 2006.252.08:07:31.02#ibcon#about to read 3, iclass 29, count 2 2006.252.08:07:31.05#ibcon#read 3, iclass 29, count 2 2006.252.08:07:31.05#ibcon#about to read 4, iclass 29, count 2 2006.252.08:07:31.05#ibcon#read 4, iclass 29, count 2 2006.252.08:07:31.05#ibcon#about to read 5, iclass 29, count 2 2006.252.08:07:31.05#ibcon#read 5, iclass 29, count 2 2006.252.08:07:31.05#ibcon#about to read 6, iclass 29, count 2 2006.252.08:07:31.05#ibcon#read 6, iclass 29, count 2 2006.252.08:07:31.05#ibcon#end of sib2, iclass 29, count 2 2006.252.08:07:31.05#ibcon#*after write, iclass 29, count 2 2006.252.08:07:31.05#ibcon#*before return 0, iclass 29, count 2 2006.252.08:07:31.05#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.252.08:07:31.05#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.252.08:07:31.05#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.252.08:07:31.05#ibcon#ireg 7 cls_cnt 0 2006.252.08:07:31.05#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.252.08:07:31.17#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.252.08:07:31.17#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.252.08:07:31.17#ibcon#enter wrdev, iclass 29, count 0 2006.252.08:07:31.17#ibcon#first serial, iclass 29, count 0 2006.252.08:07:31.17#ibcon#enter sib2, iclass 29, count 0 2006.252.08:07:31.17#ibcon#flushed, iclass 29, count 0 2006.252.08:07:31.17#ibcon#about to write, iclass 29, count 0 2006.252.08:07:31.17#ibcon#wrote, iclass 29, count 0 2006.252.08:07:31.17#ibcon#about to read 3, iclass 29, count 0 2006.252.08:07:31.20#ibcon#read 3, iclass 29, count 0 2006.252.08:07:31.20#ibcon#about to read 4, iclass 29, count 0 2006.252.08:07:31.20#ibcon#read 4, iclass 29, count 0 2006.252.08:07:31.20#ibcon#about to read 5, iclass 29, count 0 2006.252.08:07:31.20#ibcon#read 5, iclass 29, count 0 2006.252.08:07:31.20#ibcon#about to read 6, iclass 29, count 0 2006.252.08:07:31.20#ibcon#read 6, iclass 29, count 0 2006.252.08:07:31.20#ibcon#end of sib2, iclass 29, count 0 2006.252.08:07:31.20#ibcon#*mode == 0, iclass 29, count 0 2006.252.08:07:31.20#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.252.08:07:31.20#ibcon#[27=USB\r\n] 2006.252.08:07:31.20#ibcon#*before write, iclass 29, count 0 2006.252.08:07:31.20#ibcon#enter sib2, iclass 29, count 0 2006.252.08:07:31.20#ibcon#flushed, iclass 29, count 0 2006.252.08:07:31.20#ibcon#about to write, iclass 29, count 0 2006.252.08:07:31.20#ibcon#wrote, iclass 29, count 0 2006.252.08:07:31.20#ibcon#about to read 3, iclass 29, count 0 2006.252.08:07:31.23#ibcon#read 3, iclass 29, count 0 2006.252.08:07:31.23#ibcon#about to read 4, iclass 29, count 0 2006.252.08:07:31.23#ibcon#read 4, iclass 29, count 0 2006.252.08:07:31.23#ibcon#about to read 5, iclass 29, count 0 2006.252.08:07:31.23#ibcon#read 5, iclass 29, count 0 2006.252.08:07:31.23#ibcon#about to read 6, iclass 29, count 0 2006.252.08:07:31.23#ibcon#read 6, iclass 29, count 0 2006.252.08:07:31.23#ibcon#end of sib2, iclass 29, count 0 2006.252.08:07:31.23#ibcon#*after write, iclass 29, count 0 2006.252.08:07:31.23#ibcon#*before return 0, iclass 29, count 0 2006.252.08:07:31.23#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.252.08:07:31.23#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.252.08:07:31.23#ibcon#about to clear, iclass 29 cls_cnt 0 2006.252.08:07:31.23#ibcon#cleared, iclass 29 cls_cnt 0 2006.252.08:07:31.23$vc4f8/vblo=3,656.99 2006.252.08:07:31.23#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.252.08:07:31.23#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.252.08:07:31.23#ibcon#ireg 17 cls_cnt 0 2006.252.08:07:31.23#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.252.08:07:31.23#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.252.08:07:31.23#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.252.08:07:31.23#ibcon#enter wrdev, iclass 31, count 0 2006.252.08:07:31.23#ibcon#first serial, iclass 31, count 0 2006.252.08:07:31.23#ibcon#enter sib2, iclass 31, count 0 2006.252.08:07:31.23#ibcon#flushed, iclass 31, count 0 2006.252.08:07:31.23#ibcon#about to write, iclass 31, count 0 2006.252.08:07:31.23#ibcon#wrote, iclass 31, count 0 2006.252.08:07:31.23#ibcon#about to read 3, iclass 31, count 0 2006.252.08:07:31.25#ibcon#read 3, iclass 31, count 0 2006.252.08:07:31.25#ibcon#about to read 4, iclass 31, count 0 2006.252.08:07:31.25#ibcon#read 4, iclass 31, count 0 2006.252.08:07:31.25#ibcon#about to read 5, iclass 31, count 0 2006.252.08:07:31.25#ibcon#read 5, iclass 31, count 0 2006.252.08:07:31.25#ibcon#about to read 6, iclass 31, count 0 2006.252.08:07:31.25#ibcon#read 6, iclass 31, count 0 2006.252.08:07:31.25#ibcon#end of sib2, iclass 31, count 0 2006.252.08:07:31.25#ibcon#*mode == 0, iclass 31, count 0 2006.252.08:07:31.25#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.252.08:07:31.25#ibcon#[28=FRQ=03,656.99\r\n] 2006.252.08:07:31.25#ibcon#*before write, iclass 31, count 0 2006.252.08:07:31.25#ibcon#enter sib2, iclass 31, count 0 2006.252.08:07:31.25#ibcon#flushed, iclass 31, count 0 2006.252.08:07:31.25#ibcon#about to write, iclass 31, count 0 2006.252.08:07:31.25#ibcon#wrote, iclass 31, count 0 2006.252.08:07:31.25#ibcon#about to read 3, iclass 31, count 0 2006.252.08:07:31.29#ibcon#read 3, iclass 31, count 0 2006.252.08:07:31.29#ibcon#about to read 4, iclass 31, count 0 2006.252.08:07:31.29#ibcon#read 4, iclass 31, count 0 2006.252.08:07:31.29#ibcon#about to read 5, iclass 31, count 0 2006.252.08:07:31.29#ibcon#read 5, iclass 31, count 0 2006.252.08:07:31.29#ibcon#about to read 6, iclass 31, count 0 2006.252.08:07:31.29#ibcon#read 6, iclass 31, count 0 2006.252.08:07:31.29#ibcon#end of sib2, iclass 31, count 0 2006.252.08:07:31.29#ibcon#*after write, iclass 31, count 0 2006.252.08:07:31.29#ibcon#*before return 0, iclass 31, count 0 2006.252.08:07:31.29#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.252.08:07:31.29#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.252.08:07:31.29#ibcon#about to clear, iclass 31 cls_cnt 0 2006.252.08:07:31.29#ibcon#cleared, iclass 31 cls_cnt 0 2006.252.08:07:31.29$vc4f8/vb=3,4 2006.252.08:07:31.29#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.252.08:07:31.29#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.252.08:07:31.29#ibcon#ireg 11 cls_cnt 2 2006.252.08:07:31.29#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.252.08:07:31.35#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.252.08:07:31.35#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.252.08:07:31.35#ibcon#enter wrdev, iclass 33, count 2 2006.252.08:07:31.35#ibcon#first serial, iclass 33, count 2 2006.252.08:07:31.35#ibcon#enter sib2, iclass 33, count 2 2006.252.08:07:31.35#ibcon#flushed, iclass 33, count 2 2006.252.08:07:31.35#ibcon#about to write, iclass 33, count 2 2006.252.08:07:31.35#ibcon#wrote, iclass 33, count 2 2006.252.08:07:31.35#ibcon#about to read 3, iclass 33, count 2 2006.252.08:07:31.37#ibcon#read 3, iclass 33, count 2 2006.252.08:07:31.37#ibcon#about to read 4, iclass 33, count 2 2006.252.08:07:31.37#ibcon#read 4, iclass 33, count 2 2006.252.08:07:31.37#ibcon#about to read 5, iclass 33, count 2 2006.252.08:07:31.37#ibcon#read 5, iclass 33, count 2 2006.252.08:07:31.37#ibcon#about to read 6, iclass 33, count 2 2006.252.08:07:31.37#ibcon#read 6, iclass 33, count 2 2006.252.08:07:31.37#ibcon#end of sib2, iclass 33, count 2 2006.252.08:07:31.37#ibcon#*mode == 0, iclass 33, count 2 2006.252.08:07:31.37#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.252.08:07:31.37#ibcon#[27=AT03-04\r\n] 2006.252.08:07:31.37#ibcon#*before write, iclass 33, count 2 2006.252.08:07:31.37#ibcon#enter sib2, iclass 33, count 2 2006.252.08:07:31.37#ibcon#flushed, iclass 33, count 2 2006.252.08:07:31.37#ibcon#about to write, iclass 33, count 2 2006.252.08:07:31.37#ibcon#wrote, iclass 33, count 2 2006.252.08:07:31.37#ibcon#about to read 3, iclass 33, count 2 2006.252.08:07:31.40#ibcon#read 3, iclass 33, count 2 2006.252.08:07:31.40#ibcon#about to read 4, iclass 33, count 2 2006.252.08:07:31.40#ibcon#read 4, iclass 33, count 2 2006.252.08:07:31.40#ibcon#about to read 5, iclass 33, count 2 2006.252.08:07:31.40#ibcon#read 5, iclass 33, count 2 2006.252.08:07:31.40#ibcon#about to read 6, iclass 33, count 2 2006.252.08:07:31.40#ibcon#read 6, iclass 33, count 2 2006.252.08:07:31.40#ibcon#end of sib2, iclass 33, count 2 2006.252.08:07:31.40#ibcon#*after write, iclass 33, count 2 2006.252.08:07:31.40#ibcon#*before return 0, iclass 33, count 2 2006.252.08:07:31.40#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.252.08:07:31.40#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.252.08:07:31.40#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.252.08:07:31.40#ibcon#ireg 7 cls_cnt 0 2006.252.08:07:31.40#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.252.08:07:31.52#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.252.08:07:31.52#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.252.08:07:31.52#ibcon#enter wrdev, iclass 33, count 0 2006.252.08:07:31.52#ibcon#first serial, iclass 33, count 0 2006.252.08:07:31.52#ibcon#enter sib2, iclass 33, count 0 2006.252.08:07:31.52#ibcon#flushed, iclass 33, count 0 2006.252.08:07:31.52#ibcon#about to write, iclass 33, count 0 2006.252.08:07:31.52#ibcon#wrote, iclass 33, count 0 2006.252.08:07:31.52#ibcon#about to read 3, iclass 33, count 0 2006.252.08:07:31.54#ibcon#read 3, iclass 33, count 0 2006.252.08:07:31.54#ibcon#about to read 4, iclass 33, count 0 2006.252.08:07:31.54#ibcon#read 4, iclass 33, count 0 2006.252.08:07:31.54#ibcon#about to read 5, iclass 33, count 0 2006.252.08:07:31.54#ibcon#read 5, iclass 33, count 0 2006.252.08:07:31.54#ibcon#about to read 6, iclass 33, count 0 2006.252.08:07:31.54#ibcon#read 6, iclass 33, count 0 2006.252.08:07:31.54#ibcon#end of sib2, iclass 33, count 0 2006.252.08:07:31.54#ibcon#*mode == 0, iclass 33, count 0 2006.252.08:07:31.54#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.252.08:07:31.54#ibcon#[27=USB\r\n] 2006.252.08:07:31.54#ibcon#*before write, iclass 33, count 0 2006.252.08:07:31.54#ibcon#enter sib2, iclass 33, count 0 2006.252.08:07:31.54#ibcon#flushed, iclass 33, count 0 2006.252.08:07:31.54#ibcon#about to write, iclass 33, count 0 2006.252.08:07:31.54#ibcon#wrote, iclass 33, count 0 2006.252.08:07:31.54#ibcon#about to read 3, iclass 33, count 0 2006.252.08:07:31.57#ibcon#read 3, iclass 33, count 0 2006.252.08:07:31.57#ibcon#about to read 4, iclass 33, count 0 2006.252.08:07:31.57#ibcon#read 4, iclass 33, count 0 2006.252.08:07:31.57#ibcon#about to read 5, iclass 33, count 0 2006.252.08:07:31.57#ibcon#read 5, iclass 33, count 0 2006.252.08:07:31.57#ibcon#about to read 6, iclass 33, count 0 2006.252.08:07:31.57#ibcon#read 6, iclass 33, count 0 2006.252.08:07:31.57#ibcon#end of sib2, iclass 33, count 0 2006.252.08:07:31.57#ibcon#*after write, iclass 33, count 0 2006.252.08:07:31.57#ibcon#*before return 0, iclass 33, count 0 2006.252.08:07:31.57#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.252.08:07:31.57#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.252.08:07:31.57#ibcon#about to clear, iclass 33 cls_cnt 0 2006.252.08:07:31.57#ibcon#cleared, iclass 33 cls_cnt 0 2006.252.08:07:31.57$vc4f8/vblo=4,712.99 2006.252.08:07:31.57#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.252.08:07:31.57#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.252.08:07:31.57#ibcon#ireg 17 cls_cnt 0 2006.252.08:07:31.57#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.252.08:07:31.57#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.252.08:07:31.57#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.252.08:07:31.57#ibcon#enter wrdev, iclass 35, count 0 2006.252.08:07:31.57#ibcon#first serial, iclass 35, count 0 2006.252.08:07:31.57#ibcon#enter sib2, iclass 35, count 0 2006.252.08:07:31.57#ibcon#flushed, iclass 35, count 0 2006.252.08:07:31.57#ibcon#about to write, iclass 35, count 0 2006.252.08:07:31.57#ibcon#wrote, iclass 35, count 0 2006.252.08:07:31.57#ibcon#about to read 3, iclass 35, count 0 2006.252.08:07:31.59#ibcon#read 3, iclass 35, count 0 2006.252.08:07:31.59#ibcon#about to read 4, iclass 35, count 0 2006.252.08:07:31.59#ibcon#read 4, iclass 35, count 0 2006.252.08:07:31.59#ibcon#about to read 5, iclass 35, count 0 2006.252.08:07:31.59#ibcon#read 5, iclass 35, count 0 2006.252.08:07:31.59#ibcon#about to read 6, iclass 35, count 0 2006.252.08:07:31.59#ibcon#read 6, iclass 35, count 0 2006.252.08:07:31.59#ibcon#end of sib2, iclass 35, count 0 2006.252.08:07:31.59#ibcon#*mode == 0, iclass 35, count 0 2006.252.08:07:31.59#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.252.08:07:31.59#ibcon#[28=FRQ=04,712.99\r\n] 2006.252.08:07:31.59#ibcon#*before write, iclass 35, count 0 2006.252.08:07:31.59#ibcon#enter sib2, iclass 35, count 0 2006.252.08:07:31.59#ibcon#flushed, iclass 35, count 0 2006.252.08:07:31.59#ibcon#about to write, iclass 35, count 0 2006.252.08:07:31.59#ibcon#wrote, iclass 35, count 0 2006.252.08:07:31.59#ibcon#about to read 3, iclass 35, count 0 2006.252.08:07:31.63#ibcon#read 3, iclass 35, count 0 2006.252.08:07:31.63#ibcon#about to read 4, iclass 35, count 0 2006.252.08:07:31.63#ibcon#read 4, iclass 35, count 0 2006.252.08:07:31.63#ibcon#about to read 5, iclass 35, count 0 2006.252.08:07:31.63#ibcon#read 5, iclass 35, count 0 2006.252.08:07:31.63#ibcon#about to read 6, iclass 35, count 0 2006.252.08:07:31.63#ibcon#read 6, iclass 35, count 0 2006.252.08:07:31.63#ibcon#end of sib2, iclass 35, count 0 2006.252.08:07:31.63#ibcon#*after write, iclass 35, count 0 2006.252.08:07:31.63#ibcon#*before return 0, iclass 35, count 0 2006.252.08:07:31.63#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.252.08:07:31.63#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.252.08:07:31.63#ibcon#about to clear, iclass 35 cls_cnt 0 2006.252.08:07:31.63#ibcon#cleared, iclass 35 cls_cnt 0 2006.252.08:07:31.63$vc4f8/vb=4,4 2006.252.08:07:31.63#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.252.08:07:31.63#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.252.08:07:31.63#ibcon#ireg 11 cls_cnt 2 2006.252.08:07:31.63#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.252.08:07:31.69#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.252.08:07:31.69#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.252.08:07:31.69#ibcon#enter wrdev, iclass 37, count 2 2006.252.08:07:31.69#ibcon#first serial, iclass 37, count 2 2006.252.08:07:31.69#ibcon#enter sib2, iclass 37, count 2 2006.252.08:07:31.69#ibcon#flushed, iclass 37, count 2 2006.252.08:07:31.69#ibcon#about to write, iclass 37, count 2 2006.252.08:07:31.69#ibcon#wrote, iclass 37, count 2 2006.252.08:07:31.69#ibcon#about to read 3, iclass 37, count 2 2006.252.08:07:31.71#ibcon#read 3, iclass 37, count 2 2006.252.08:07:31.71#ibcon#about to read 4, iclass 37, count 2 2006.252.08:07:31.71#ibcon#read 4, iclass 37, count 2 2006.252.08:07:31.71#ibcon#about to read 5, iclass 37, count 2 2006.252.08:07:31.71#ibcon#read 5, iclass 37, count 2 2006.252.08:07:31.71#ibcon#about to read 6, iclass 37, count 2 2006.252.08:07:31.71#ibcon#read 6, iclass 37, count 2 2006.252.08:07:31.71#ibcon#end of sib2, iclass 37, count 2 2006.252.08:07:31.71#ibcon#*mode == 0, iclass 37, count 2 2006.252.08:07:31.71#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.252.08:07:31.71#ibcon#[27=AT04-04\r\n] 2006.252.08:07:31.71#ibcon#*before write, iclass 37, count 2 2006.252.08:07:31.71#ibcon#enter sib2, iclass 37, count 2 2006.252.08:07:31.71#ibcon#flushed, iclass 37, count 2 2006.252.08:07:31.71#ibcon#about to write, iclass 37, count 2 2006.252.08:07:31.71#ibcon#wrote, iclass 37, count 2 2006.252.08:07:31.71#ibcon#about to read 3, iclass 37, count 2 2006.252.08:07:31.74#ibcon#read 3, iclass 37, count 2 2006.252.08:07:31.74#ibcon#about to read 4, iclass 37, count 2 2006.252.08:07:31.74#ibcon#read 4, iclass 37, count 2 2006.252.08:07:31.74#ibcon#about to read 5, iclass 37, count 2 2006.252.08:07:31.74#ibcon#read 5, iclass 37, count 2 2006.252.08:07:31.74#ibcon#about to read 6, iclass 37, count 2 2006.252.08:07:31.74#ibcon#read 6, iclass 37, count 2 2006.252.08:07:31.74#ibcon#end of sib2, iclass 37, count 2 2006.252.08:07:31.74#ibcon#*after write, iclass 37, count 2 2006.252.08:07:31.74#ibcon#*before return 0, iclass 37, count 2 2006.252.08:07:31.74#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.252.08:07:31.74#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.252.08:07:31.74#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.252.08:07:31.74#ibcon#ireg 7 cls_cnt 0 2006.252.08:07:31.74#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.252.08:07:31.86#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.252.08:07:31.86#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.252.08:07:31.86#ibcon#enter wrdev, iclass 37, count 0 2006.252.08:07:31.86#ibcon#first serial, iclass 37, count 0 2006.252.08:07:31.86#ibcon#enter sib2, iclass 37, count 0 2006.252.08:07:31.86#ibcon#flushed, iclass 37, count 0 2006.252.08:07:31.86#ibcon#about to write, iclass 37, count 0 2006.252.08:07:31.86#ibcon#wrote, iclass 37, count 0 2006.252.08:07:31.86#ibcon#about to read 3, iclass 37, count 0 2006.252.08:07:31.88#ibcon#read 3, iclass 37, count 0 2006.252.08:07:31.88#ibcon#about to read 4, iclass 37, count 0 2006.252.08:07:31.88#ibcon#read 4, iclass 37, count 0 2006.252.08:07:31.88#ibcon#about to read 5, iclass 37, count 0 2006.252.08:07:31.88#ibcon#read 5, iclass 37, count 0 2006.252.08:07:31.88#ibcon#about to read 6, iclass 37, count 0 2006.252.08:07:31.88#ibcon#read 6, iclass 37, count 0 2006.252.08:07:31.88#ibcon#end of sib2, iclass 37, count 0 2006.252.08:07:31.88#ibcon#*mode == 0, iclass 37, count 0 2006.252.08:07:31.88#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.252.08:07:31.88#ibcon#[27=USB\r\n] 2006.252.08:07:31.88#ibcon#*before write, iclass 37, count 0 2006.252.08:07:31.88#ibcon#enter sib2, iclass 37, count 0 2006.252.08:07:31.88#ibcon#flushed, iclass 37, count 0 2006.252.08:07:31.88#ibcon#about to write, iclass 37, count 0 2006.252.08:07:31.88#ibcon#wrote, iclass 37, count 0 2006.252.08:07:31.88#ibcon#about to read 3, iclass 37, count 0 2006.252.08:07:31.91#ibcon#read 3, iclass 37, count 0 2006.252.08:07:31.91#ibcon#about to read 4, iclass 37, count 0 2006.252.08:07:31.91#ibcon#read 4, iclass 37, count 0 2006.252.08:07:31.91#ibcon#about to read 5, iclass 37, count 0 2006.252.08:07:31.91#ibcon#read 5, iclass 37, count 0 2006.252.08:07:31.91#ibcon#about to read 6, iclass 37, count 0 2006.252.08:07:31.91#ibcon#read 6, iclass 37, count 0 2006.252.08:07:31.91#ibcon#end of sib2, iclass 37, count 0 2006.252.08:07:31.91#ibcon#*after write, iclass 37, count 0 2006.252.08:07:31.91#ibcon#*before return 0, iclass 37, count 0 2006.252.08:07:31.91#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.252.08:07:31.91#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.252.08:07:31.91#ibcon#about to clear, iclass 37 cls_cnt 0 2006.252.08:07:31.91#ibcon#cleared, iclass 37 cls_cnt 0 2006.252.08:07:31.91$vc4f8/vblo=5,744.99 2006.252.08:07:31.91#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.252.08:07:31.91#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.252.08:07:31.91#ibcon#ireg 17 cls_cnt 0 2006.252.08:07:31.91#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.252.08:07:31.91#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.252.08:07:31.91#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.252.08:07:31.91#ibcon#enter wrdev, iclass 39, count 0 2006.252.08:07:31.91#ibcon#first serial, iclass 39, count 0 2006.252.08:07:31.91#ibcon#enter sib2, iclass 39, count 0 2006.252.08:07:31.91#ibcon#flushed, iclass 39, count 0 2006.252.08:07:31.91#ibcon#about to write, iclass 39, count 0 2006.252.08:07:31.91#ibcon#wrote, iclass 39, count 0 2006.252.08:07:31.91#ibcon#about to read 3, iclass 39, count 0 2006.252.08:07:31.93#ibcon#read 3, iclass 39, count 0 2006.252.08:07:31.93#ibcon#about to read 4, iclass 39, count 0 2006.252.08:07:31.93#ibcon#read 4, iclass 39, count 0 2006.252.08:07:31.93#ibcon#about to read 5, iclass 39, count 0 2006.252.08:07:31.93#ibcon#read 5, iclass 39, count 0 2006.252.08:07:31.93#ibcon#about to read 6, iclass 39, count 0 2006.252.08:07:31.93#ibcon#read 6, iclass 39, count 0 2006.252.08:07:31.93#ibcon#end of sib2, iclass 39, count 0 2006.252.08:07:31.93#ibcon#*mode == 0, iclass 39, count 0 2006.252.08:07:31.93#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.252.08:07:31.93#ibcon#[28=FRQ=05,744.99\r\n] 2006.252.08:07:31.93#ibcon#*before write, iclass 39, count 0 2006.252.08:07:31.93#ibcon#enter sib2, iclass 39, count 0 2006.252.08:07:31.93#ibcon#flushed, iclass 39, count 0 2006.252.08:07:31.93#ibcon#about to write, iclass 39, count 0 2006.252.08:07:31.93#ibcon#wrote, iclass 39, count 0 2006.252.08:07:31.93#ibcon#about to read 3, iclass 39, count 0 2006.252.08:07:31.97#ibcon#read 3, iclass 39, count 0 2006.252.08:07:31.97#ibcon#about to read 4, iclass 39, count 0 2006.252.08:07:31.97#ibcon#read 4, iclass 39, count 0 2006.252.08:07:31.97#ibcon#about to read 5, iclass 39, count 0 2006.252.08:07:31.97#ibcon#read 5, iclass 39, count 0 2006.252.08:07:31.97#ibcon#about to read 6, iclass 39, count 0 2006.252.08:07:31.97#ibcon#read 6, iclass 39, count 0 2006.252.08:07:31.97#ibcon#end of sib2, iclass 39, count 0 2006.252.08:07:31.97#ibcon#*after write, iclass 39, count 0 2006.252.08:07:31.97#ibcon#*before return 0, iclass 39, count 0 2006.252.08:07:31.97#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.252.08:07:31.97#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.252.08:07:31.97#ibcon#about to clear, iclass 39 cls_cnt 0 2006.252.08:07:31.97#ibcon#cleared, iclass 39 cls_cnt 0 2006.252.08:07:31.97$vc4f8/vb=5,4 2006.252.08:07:31.97#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.252.08:07:31.97#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.252.08:07:31.97#ibcon#ireg 11 cls_cnt 2 2006.252.08:07:31.97#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.252.08:07:32.03#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.252.08:07:32.03#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.252.08:07:32.03#ibcon#enter wrdev, iclass 3, count 2 2006.252.08:07:32.03#ibcon#first serial, iclass 3, count 2 2006.252.08:07:32.03#ibcon#enter sib2, iclass 3, count 2 2006.252.08:07:32.03#ibcon#flushed, iclass 3, count 2 2006.252.08:07:32.03#ibcon#about to write, iclass 3, count 2 2006.252.08:07:32.03#ibcon#wrote, iclass 3, count 2 2006.252.08:07:32.03#ibcon#about to read 3, iclass 3, count 2 2006.252.08:07:32.05#ibcon#read 3, iclass 3, count 2 2006.252.08:07:32.05#ibcon#about to read 4, iclass 3, count 2 2006.252.08:07:32.05#ibcon#read 4, iclass 3, count 2 2006.252.08:07:32.05#ibcon#about to read 5, iclass 3, count 2 2006.252.08:07:32.05#ibcon#read 5, iclass 3, count 2 2006.252.08:07:32.05#ibcon#about to read 6, iclass 3, count 2 2006.252.08:07:32.05#ibcon#read 6, iclass 3, count 2 2006.252.08:07:32.05#ibcon#end of sib2, iclass 3, count 2 2006.252.08:07:32.05#ibcon#*mode == 0, iclass 3, count 2 2006.252.08:07:32.05#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.252.08:07:32.05#ibcon#[27=AT05-04\r\n] 2006.252.08:07:32.05#ibcon#*before write, iclass 3, count 2 2006.252.08:07:32.05#ibcon#enter sib2, iclass 3, count 2 2006.252.08:07:32.05#ibcon#flushed, iclass 3, count 2 2006.252.08:07:32.05#ibcon#about to write, iclass 3, count 2 2006.252.08:07:32.05#ibcon#wrote, iclass 3, count 2 2006.252.08:07:32.05#ibcon#about to read 3, iclass 3, count 2 2006.252.08:07:32.08#ibcon#read 3, iclass 3, count 2 2006.252.08:07:32.08#ibcon#about to read 4, iclass 3, count 2 2006.252.08:07:32.08#ibcon#read 4, iclass 3, count 2 2006.252.08:07:32.08#ibcon#about to read 5, iclass 3, count 2 2006.252.08:07:32.08#ibcon#read 5, iclass 3, count 2 2006.252.08:07:32.08#ibcon#about to read 6, iclass 3, count 2 2006.252.08:07:32.08#ibcon#read 6, iclass 3, count 2 2006.252.08:07:32.08#ibcon#end of sib2, iclass 3, count 2 2006.252.08:07:32.08#ibcon#*after write, iclass 3, count 2 2006.252.08:07:32.08#ibcon#*before return 0, iclass 3, count 2 2006.252.08:07:32.08#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.252.08:07:32.08#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.252.08:07:32.08#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.252.08:07:32.08#ibcon#ireg 7 cls_cnt 0 2006.252.08:07:32.08#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.252.08:07:32.20#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.252.08:07:32.20#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.252.08:07:32.20#ibcon#enter wrdev, iclass 3, count 0 2006.252.08:07:32.20#ibcon#first serial, iclass 3, count 0 2006.252.08:07:32.20#ibcon#enter sib2, iclass 3, count 0 2006.252.08:07:32.20#ibcon#flushed, iclass 3, count 0 2006.252.08:07:32.20#ibcon#about to write, iclass 3, count 0 2006.252.08:07:32.20#ibcon#wrote, iclass 3, count 0 2006.252.08:07:32.20#ibcon#about to read 3, iclass 3, count 0 2006.252.08:07:32.22#ibcon#read 3, iclass 3, count 0 2006.252.08:07:32.22#ibcon#about to read 4, iclass 3, count 0 2006.252.08:07:32.22#ibcon#read 4, iclass 3, count 0 2006.252.08:07:32.22#ibcon#about to read 5, iclass 3, count 0 2006.252.08:07:32.22#ibcon#read 5, iclass 3, count 0 2006.252.08:07:32.22#ibcon#about to read 6, iclass 3, count 0 2006.252.08:07:32.22#ibcon#read 6, iclass 3, count 0 2006.252.08:07:32.22#ibcon#end of sib2, iclass 3, count 0 2006.252.08:07:32.22#ibcon#*mode == 0, iclass 3, count 0 2006.252.08:07:32.22#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.252.08:07:32.22#ibcon#[27=USB\r\n] 2006.252.08:07:32.22#ibcon#*before write, iclass 3, count 0 2006.252.08:07:32.22#ibcon#enter sib2, iclass 3, count 0 2006.252.08:07:32.22#ibcon#flushed, iclass 3, count 0 2006.252.08:07:32.22#ibcon#about to write, iclass 3, count 0 2006.252.08:07:32.22#ibcon#wrote, iclass 3, count 0 2006.252.08:07:32.22#ibcon#about to read 3, iclass 3, count 0 2006.252.08:07:32.25#ibcon#read 3, iclass 3, count 0 2006.252.08:07:32.25#ibcon#about to read 4, iclass 3, count 0 2006.252.08:07:32.25#ibcon#read 4, iclass 3, count 0 2006.252.08:07:32.25#ibcon#about to read 5, iclass 3, count 0 2006.252.08:07:32.25#ibcon#read 5, iclass 3, count 0 2006.252.08:07:32.25#ibcon#about to read 6, iclass 3, count 0 2006.252.08:07:32.25#ibcon#read 6, iclass 3, count 0 2006.252.08:07:32.25#ibcon#end of sib2, iclass 3, count 0 2006.252.08:07:32.25#ibcon#*after write, iclass 3, count 0 2006.252.08:07:32.25#ibcon#*before return 0, iclass 3, count 0 2006.252.08:07:32.25#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.252.08:07:32.25#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.252.08:07:32.25#ibcon#about to clear, iclass 3 cls_cnt 0 2006.252.08:07:32.25#ibcon#cleared, iclass 3 cls_cnt 0 2006.252.08:07:32.25$vc4f8/vblo=6,752.99 2006.252.08:07:32.25#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.252.08:07:32.25#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.252.08:07:32.25#ibcon#ireg 17 cls_cnt 0 2006.252.08:07:32.25#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.252.08:07:32.25#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.252.08:07:32.25#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.252.08:07:32.25#ibcon#enter wrdev, iclass 5, count 0 2006.252.08:07:32.25#ibcon#first serial, iclass 5, count 0 2006.252.08:07:32.25#ibcon#enter sib2, iclass 5, count 0 2006.252.08:07:32.25#ibcon#flushed, iclass 5, count 0 2006.252.08:07:32.25#ibcon#about to write, iclass 5, count 0 2006.252.08:07:32.25#ibcon#wrote, iclass 5, count 0 2006.252.08:07:32.25#ibcon#about to read 3, iclass 5, count 0 2006.252.08:07:32.27#ibcon#read 3, iclass 5, count 0 2006.252.08:07:32.27#ibcon#about to read 4, iclass 5, count 0 2006.252.08:07:32.27#ibcon#read 4, iclass 5, count 0 2006.252.08:07:32.27#ibcon#about to read 5, iclass 5, count 0 2006.252.08:07:32.27#ibcon#read 5, iclass 5, count 0 2006.252.08:07:32.27#ibcon#about to read 6, iclass 5, count 0 2006.252.08:07:32.27#ibcon#read 6, iclass 5, count 0 2006.252.08:07:32.27#ibcon#end of sib2, iclass 5, count 0 2006.252.08:07:32.27#ibcon#*mode == 0, iclass 5, count 0 2006.252.08:07:32.27#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.252.08:07:32.27#ibcon#[28=FRQ=06,752.99\r\n] 2006.252.08:07:32.27#ibcon#*before write, iclass 5, count 0 2006.252.08:07:32.27#ibcon#enter sib2, iclass 5, count 0 2006.252.08:07:32.27#ibcon#flushed, iclass 5, count 0 2006.252.08:07:32.27#ibcon#about to write, iclass 5, count 0 2006.252.08:07:32.27#ibcon#wrote, iclass 5, count 0 2006.252.08:07:32.27#ibcon#about to read 3, iclass 5, count 0 2006.252.08:07:32.31#ibcon#read 3, iclass 5, count 0 2006.252.08:07:32.31#ibcon#about to read 4, iclass 5, count 0 2006.252.08:07:32.31#ibcon#read 4, iclass 5, count 0 2006.252.08:07:32.31#ibcon#about to read 5, iclass 5, count 0 2006.252.08:07:32.31#ibcon#read 5, iclass 5, count 0 2006.252.08:07:32.31#ibcon#about to read 6, iclass 5, count 0 2006.252.08:07:32.31#ibcon#read 6, iclass 5, count 0 2006.252.08:07:32.31#ibcon#end of sib2, iclass 5, count 0 2006.252.08:07:32.31#ibcon#*after write, iclass 5, count 0 2006.252.08:07:32.31#ibcon#*before return 0, iclass 5, count 0 2006.252.08:07:32.31#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.252.08:07:32.31#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.252.08:07:32.31#ibcon#about to clear, iclass 5 cls_cnt 0 2006.252.08:07:32.31#ibcon#cleared, iclass 5 cls_cnt 0 2006.252.08:07:32.31$vc4f8/vb=6,4 2006.252.08:07:32.31#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.252.08:07:32.31#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.252.08:07:32.31#ibcon#ireg 11 cls_cnt 2 2006.252.08:07:32.31#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.252.08:07:32.37#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.252.08:07:32.37#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.252.08:07:32.37#ibcon#enter wrdev, iclass 7, count 2 2006.252.08:07:32.37#ibcon#first serial, iclass 7, count 2 2006.252.08:07:32.37#ibcon#enter sib2, iclass 7, count 2 2006.252.08:07:32.37#ibcon#flushed, iclass 7, count 2 2006.252.08:07:32.37#ibcon#about to write, iclass 7, count 2 2006.252.08:07:32.37#ibcon#wrote, iclass 7, count 2 2006.252.08:07:32.37#ibcon#about to read 3, iclass 7, count 2 2006.252.08:07:32.39#ibcon#read 3, iclass 7, count 2 2006.252.08:07:32.39#ibcon#about to read 4, iclass 7, count 2 2006.252.08:07:32.39#ibcon#read 4, iclass 7, count 2 2006.252.08:07:32.39#ibcon#about to read 5, iclass 7, count 2 2006.252.08:07:32.39#ibcon#read 5, iclass 7, count 2 2006.252.08:07:32.39#ibcon#about to read 6, iclass 7, count 2 2006.252.08:07:32.39#ibcon#read 6, iclass 7, count 2 2006.252.08:07:32.39#ibcon#end of sib2, iclass 7, count 2 2006.252.08:07:32.39#ibcon#*mode == 0, iclass 7, count 2 2006.252.08:07:32.39#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.252.08:07:32.39#ibcon#[27=AT06-04\r\n] 2006.252.08:07:32.39#ibcon#*before write, iclass 7, count 2 2006.252.08:07:32.39#ibcon#enter sib2, iclass 7, count 2 2006.252.08:07:32.39#ibcon#flushed, iclass 7, count 2 2006.252.08:07:32.39#ibcon#about to write, iclass 7, count 2 2006.252.08:07:32.39#ibcon#wrote, iclass 7, count 2 2006.252.08:07:32.39#ibcon#about to read 3, iclass 7, count 2 2006.252.08:07:32.42#ibcon#read 3, iclass 7, count 2 2006.252.08:07:32.42#ibcon#about to read 4, iclass 7, count 2 2006.252.08:07:32.42#ibcon#read 4, iclass 7, count 2 2006.252.08:07:32.42#ibcon#about to read 5, iclass 7, count 2 2006.252.08:07:32.42#ibcon#read 5, iclass 7, count 2 2006.252.08:07:32.42#ibcon#about to read 6, iclass 7, count 2 2006.252.08:07:32.42#ibcon#read 6, iclass 7, count 2 2006.252.08:07:32.42#ibcon#end of sib2, iclass 7, count 2 2006.252.08:07:32.42#ibcon#*after write, iclass 7, count 2 2006.252.08:07:32.42#ibcon#*before return 0, iclass 7, count 2 2006.252.08:07:32.42#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.252.08:07:32.42#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.252.08:07:32.42#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.252.08:07:32.42#ibcon#ireg 7 cls_cnt 0 2006.252.08:07:32.42#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.252.08:07:32.54#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.252.08:07:32.54#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.252.08:07:32.54#ibcon#enter wrdev, iclass 7, count 0 2006.252.08:07:32.54#ibcon#first serial, iclass 7, count 0 2006.252.08:07:32.54#ibcon#enter sib2, iclass 7, count 0 2006.252.08:07:32.54#ibcon#flushed, iclass 7, count 0 2006.252.08:07:32.54#ibcon#about to write, iclass 7, count 0 2006.252.08:07:32.54#ibcon#wrote, iclass 7, count 0 2006.252.08:07:32.54#ibcon#about to read 3, iclass 7, count 0 2006.252.08:07:32.56#ibcon#read 3, iclass 7, count 0 2006.252.08:07:32.56#ibcon#about to read 4, iclass 7, count 0 2006.252.08:07:32.56#ibcon#read 4, iclass 7, count 0 2006.252.08:07:32.56#ibcon#about to read 5, iclass 7, count 0 2006.252.08:07:32.56#ibcon#read 5, iclass 7, count 0 2006.252.08:07:32.56#ibcon#about to read 6, iclass 7, count 0 2006.252.08:07:32.56#ibcon#read 6, iclass 7, count 0 2006.252.08:07:32.56#ibcon#end of sib2, iclass 7, count 0 2006.252.08:07:32.56#ibcon#*mode == 0, iclass 7, count 0 2006.252.08:07:32.56#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.252.08:07:32.56#ibcon#[27=USB\r\n] 2006.252.08:07:32.56#ibcon#*before write, iclass 7, count 0 2006.252.08:07:32.56#ibcon#enter sib2, iclass 7, count 0 2006.252.08:07:32.56#ibcon#flushed, iclass 7, count 0 2006.252.08:07:32.56#ibcon#about to write, iclass 7, count 0 2006.252.08:07:32.56#ibcon#wrote, iclass 7, count 0 2006.252.08:07:32.56#ibcon#about to read 3, iclass 7, count 0 2006.252.08:07:32.59#ibcon#read 3, iclass 7, count 0 2006.252.08:07:32.59#ibcon#about to read 4, iclass 7, count 0 2006.252.08:07:32.59#ibcon#read 4, iclass 7, count 0 2006.252.08:07:32.59#ibcon#about to read 5, iclass 7, count 0 2006.252.08:07:32.59#ibcon#read 5, iclass 7, count 0 2006.252.08:07:32.59#ibcon#about to read 6, iclass 7, count 0 2006.252.08:07:32.59#ibcon#read 6, iclass 7, count 0 2006.252.08:07:32.59#ibcon#end of sib2, iclass 7, count 0 2006.252.08:07:32.59#ibcon#*after write, iclass 7, count 0 2006.252.08:07:32.59#ibcon#*before return 0, iclass 7, count 0 2006.252.08:07:32.59#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.252.08:07:32.59#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.252.08:07:32.59#ibcon#about to clear, iclass 7 cls_cnt 0 2006.252.08:07:32.59#ibcon#cleared, iclass 7 cls_cnt 0 2006.252.08:07:32.59$vc4f8/vabw=wide 2006.252.08:07:32.59#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.252.08:07:32.59#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.252.08:07:32.59#ibcon#ireg 8 cls_cnt 0 2006.252.08:07:32.59#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.252.08:07:32.59#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.252.08:07:32.59#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.252.08:07:32.59#ibcon#enter wrdev, iclass 11, count 0 2006.252.08:07:32.59#ibcon#first serial, iclass 11, count 0 2006.252.08:07:32.59#ibcon#enter sib2, iclass 11, count 0 2006.252.08:07:32.59#ibcon#flushed, iclass 11, count 0 2006.252.08:07:32.59#ibcon#about to write, iclass 11, count 0 2006.252.08:07:32.59#ibcon#wrote, iclass 11, count 0 2006.252.08:07:32.59#ibcon#about to read 3, iclass 11, count 0 2006.252.08:07:32.61#ibcon#read 3, iclass 11, count 0 2006.252.08:07:32.61#ibcon#about to read 4, iclass 11, count 0 2006.252.08:07:32.61#ibcon#read 4, iclass 11, count 0 2006.252.08:07:32.61#ibcon#about to read 5, iclass 11, count 0 2006.252.08:07:32.61#ibcon#read 5, iclass 11, count 0 2006.252.08:07:32.61#ibcon#about to read 6, iclass 11, count 0 2006.252.08:07:32.61#ibcon#read 6, iclass 11, count 0 2006.252.08:07:32.61#ibcon#end of sib2, iclass 11, count 0 2006.252.08:07:32.61#ibcon#*mode == 0, iclass 11, count 0 2006.252.08:07:32.61#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.252.08:07:32.61#ibcon#[25=BW32\r\n] 2006.252.08:07:32.61#ibcon#*before write, iclass 11, count 0 2006.252.08:07:32.61#ibcon#enter sib2, iclass 11, count 0 2006.252.08:07:32.61#ibcon#flushed, iclass 11, count 0 2006.252.08:07:32.61#ibcon#about to write, iclass 11, count 0 2006.252.08:07:32.61#ibcon#wrote, iclass 11, count 0 2006.252.08:07:32.61#ibcon#about to read 3, iclass 11, count 0 2006.252.08:07:32.64#ibcon#read 3, iclass 11, count 0 2006.252.08:07:32.64#ibcon#about to read 4, iclass 11, count 0 2006.252.08:07:32.64#ibcon#read 4, iclass 11, count 0 2006.252.08:07:32.64#ibcon#about to read 5, iclass 11, count 0 2006.252.08:07:32.64#ibcon#read 5, iclass 11, count 0 2006.252.08:07:32.64#ibcon#about to read 6, iclass 11, count 0 2006.252.08:07:32.64#ibcon#read 6, iclass 11, count 0 2006.252.08:07:32.64#ibcon#end of sib2, iclass 11, count 0 2006.252.08:07:32.64#ibcon#*after write, iclass 11, count 0 2006.252.08:07:32.64#ibcon#*before return 0, iclass 11, count 0 2006.252.08:07:32.64#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.252.08:07:32.64#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.252.08:07:32.64#ibcon#about to clear, iclass 11 cls_cnt 0 2006.252.08:07:32.64#ibcon#cleared, iclass 11 cls_cnt 0 2006.252.08:07:32.64$vc4f8/vbbw=wide 2006.252.08:07:32.64#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.252.08:07:32.64#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.252.08:07:32.64#ibcon#ireg 8 cls_cnt 0 2006.252.08:07:32.64#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.252.08:07:32.71#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.252.08:07:32.71#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.252.08:07:32.71#ibcon#enter wrdev, iclass 13, count 0 2006.252.08:07:32.71#ibcon#first serial, iclass 13, count 0 2006.252.08:07:32.71#ibcon#enter sib2, iclass 13, count 0 2006.252.08:07:32.71#ibcon#flushed, iclass 13, count 0 2006.252.08:07:32.71#ibcon#about to write, iclass 13, count 0 2006.252.08:07:32.71#ibcon#wrote, iclass 13, count 0 2006.252.08:07:32.71#ibcon#about to read 3, iclass 13, count 0 2006.252.08:07:32.73#ibcon#read 3, iclass 13, count 0 2006.252.08:07:32.73#ibcon#about to read 4, iclass 13, count 0 2006.252.08:07:32.73#ibcon#read 4, iclass 13, count 0 2006.252.08:07:32.73#ibcon#about to read 5, iclass 13, count 0 2006.252.08:07:32.73#ibcon#read 5, iclass 13, count 0 2006.252.08:07:32.73#ibcon#about to read 6, iclass 13, count 0 2006.252.08:07:32.73#ibcon#read 6, iclass 13, count 0 2006.252.08:07:32.73#ibcon#end of sib2, iclass 13, count 0 2006.252.08:07:32.73#ibcon#*mode == 0, iclass 13, count 0 2006.252.08:07:32.73#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.252.08:07:32.73#ibcon#[27=BW32\r\n] 2006.252.08:07:32.73#ibcon#*before write, iclass 13, count 0 2006.252.08:07:32.73#ibcon#enter sib2, iclass 13, count 0 2006.252.08:07:32.73#ibcon#flushed, iclass 13, count 0 2006.252.08:07:32.73#ibcon#about to write, iclass 13, count 0 2006.252.08:07:32.73#ibcon#wrote, iclass 13, count 0 2006.252.08:07:32.73#ibcon#about to read 3, iclass 13, count 0 2006.252.08:07:32.76#ibcon#read 3, iclass 13, count 0 2006.252.08:07:32.76#ibcon#about to read 4, iclass 13, count 0 2006.252.08:07:32.76#ibcon#read 4, iclass 13, count 0 2006.252.08:07:32.76#ibcon#about to read 5, iclass 13, count 0 2006.252.08:07:32.76#ibcon#read 5, iclass 13, count 0 2006.252.08:07:32.76#ibcon#about to read 6, iclass 13, count 0 2006.252.08:07:32.76#ibcon#read 6, iclass 13, count 0 2006.252.08:07:32.76#ibcon#end of sib2, iclass 13, count 0 2006.252.08:07:32.76#ibcon#*after write, iclass 13, count 0 2006.252.08:07:32.76#ibcon#*before return 0, iclass 13, count 0 2006.252.08:07:32.76#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.252.08:07:32.76#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.252.08:07:32.76#ibcon#about to clear, iclass 13 cls_cnt 0 2006.252.08:07:32.76#ibcon#cleared, iclass 13 cls_cnt 0 2006.252.08:07:32.76$4f8m12a/ifd4f 2006.252.08:07:32.76$ifd4f/lo= 2006.252.08:07:32.76$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.252.08:07:32.76$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.252.08:07:32.76$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.252.08:07:32.76$ifd4f/patch= 2006.252.08:07:32.76$ifd4f/patch=lo1,a1,a2,a3,a4 2006.252.08:07:32.76$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.252.08:07:32.76$ifd4f/patch=lo3,a5,a6,a7,a8 2006.252.08:07:32.76$4f8m12a/"form=m,16.000,1:2 2006.252.08:07:32.76$4f8m12a/"tpicd 2006.252.08:07:32.76$4f8m12a/echo=off 2006.252.08:07:32.76$4f8m12a/xlog=off 2006.252.08:07:32.76:!2006.252.08:08:00 2006.252.08:07:41.14#trakl#Source acquired 2006.252.08:07:42.14#flagr#flagr/antenna,acquired 2006.252.08:08:00.00:preob 2006.252.08:08:01.14/onsource/TRACKING 2006.252.08:08:01.14:!2006.252.08:08:10 2006.252.08:08:10.00:data_valid=on 2006.252.08:08:10.00:midob 2006.252.08:08:10.14/onsource/TRACKING 2006.252.08:08:10.14/wx/27.33,1011.1,90 2006.252.08:08:10.27/cable/+6.4110E-03 2006.252.08:08:11.36/va/01,08,usb,yes,47,50 2006.252.08:08:11.36/va/02,07,usb,yes,47,49 2006.252.08:08:11.36/va/03,06,usb,yes,50,50 2006.252.08:08:11.36/va/04,07,usb,yes,48,52 2006.252.08:08:11.36/va/05,07,usb,yes,53,56 2006.252.08:08:11.36/va/06,07,usb,yes,47,47 2006.252.08:08:11.36/va/07,07,usb,yes,47,46 2006.252.08:08:11.36/va/08,07,usb,yes,50,49 2006.252.08:08:11.59/valo/01,532.99,yes,locked 2006.252.08:08:11.59/valo/02,572.99,yes,locked 2006.252.08:08:11.59/valo/03,672.99,yes,locked 2006.252.08:08:11.59/valo/04,832.99,yes,locked 2006.252.08:08:11.59/valo/05,652.99,yes,locked 2006.252.08:08:11.59/valo/06,772.99,yes,locked 2006.252.08:08:11.59/valo/07,832.99,yes,locked 2006.252.08:08:11.59/valo/08,852.99,yes,locked 2006.252.08:08:12.68/vb/01,04,usb,yes,43,41 2006.252.08:08:12.68/vb/02,05,usb,yes,40,42 2006.252.08:08:12.68/vb/03,04,usb,yes,41,46 2006.252.08:08:12.68/vb/04,04,usb,yes,42,42 2006.252.08:08:12.68/vb/05,04,usb,yes,39,45 2006.252.08:08:12.68/vb/06,04,usb,yes,41,45 2006.252.08:08:12.68/vb/07,04,usb,yes,44,44 2006.252.08:08:12.68/vb/08,04,usb,yes,40,45 2006.252.08:08:12.92/vblo/01,632.99,yes,locked 2006.252.08:08:12.92/vblo/02,640.99,yes,locked 2006.252.08:08:12.92/vblo/03,656.99,yes,locked 2006.252.08:08:12.92/vblo/04,712.99,yes,locked 2006.252.08:08:12.92/vblo/05,744.99,yes,locked 2006.252.08:08:12.92/vblo/06,752.99,yes,locked 2006.252.08:08:12.92/vblo/07,734.99,yes,locked 2006.252.08:08:12.92/vblo/08,744.99,yes,locked 2006.252.08:08:13.07/vabw/8 2006.252.08:08:13.22/vbbw/8 2006.252.08:08:13.31/xfe/off,on,14.2 2006.252.08:08:13.69/ifatt/23,28,28,28 2006.252.08:08:14.08/fmout-gps/S +4.78E-07 2006.252.08:08:14.12:!2006.252.08:09:10 2006.252.08:09:10.00:data_valid=off 2006.252.08:09:10.00:postob 2006.252.08:09:10.07/cable/+6.4106E-03 2006.252.08:09:10.07/wx/27.32,1011.1,90 2006.252.08:09:11.08/fmout-gps/S +4.77E-07 2006.252.08:09:11.08:scan_name=252-0810,k06252,60 2006.252.08:09:11.08:source=1300+580,130252.47,574837.6,2000.0,ccw 2006.252.08:09:11.14#flagr#flagr/antenna,new-source 2006.252.08:09:12.14:checkk5 2006.252.08:09:12.51/chk_autoobs//k5ts1/ autoobs is running! 2006.252.08:09:12.88/chk_autoobs//k5ts2/ autoobs is running! 2006.252.08:09:13.26/chk_autoobs//k5ts3/ autoobs is running! 2006.252.08:09:13.63/chk_autoobs//k5ts4/ autoobs is running! 2006.252.08:09:13.99/chk_obsdata//k5ts1/T2520808??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.08:09:14.36/chk_obsdata//k5ts2/T2520808??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.08:09:14.73/chk_obsdata//k5ts3/T2520808??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.08:09:15.10/chk_obsdata//k5ts4/T2520808??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.08:09:15.79/k5log//k5ts1_log_newline 2006.252.08:09:16.48/k5log//k5ts2_log_newline 2006.252.08:09:17.18/k5log//k5ts3_log_newline 2006.252.08:09:17.87/k5log//k5ts4_log_newline 2006.252.08:09:17.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.252.08:09:17.90:4f8m12a=2 2006.252.08:09:17.90$4f8m12a/echo=on 2006.252.08:09:17.90$4f8m12a/pcalon 2006.252.08:09:17.90$pcalon/"no phase cal control is implemented here 2006.252.08:09:17.90$4f8m12a/"tpicd=stop 2006.252.08:09:17.90$4f8m12a/vc4f8 2006.252.08:09:17.90$vc4f8/valo=1,532.99 2006.252.08:09:17.90#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.252.08:09:17.90#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.252.08:09:17.90#ibcon#ireg 17 cls_cnt 0 2006.252.08:09:17.90#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.252.08:09:17.90#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.252.08:09:17.90#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.252.08:09:17.90#ibcon#enter wrdev, iclass 24, count 0 2006.252.08:09:17.90#ibcon#first serial, iclass 24, count 0 2006.252.08:09:17.90#ibcon#enter sib2, iclass 24, count 0 2006.252.08:09:17.90#ibcon#flushed, iclass 24, count 0 2006.252.08:09:17.90#ibcon#about to write, iclass 24, count 0 2006.252.08:09:17.90#ibcon#wrote, iclass 24, count 0 2006.252.08:09:17.90#ibcon#about to read 3, iclass 24, count 0 2006.252.08:09:17.94#ibcon#read 3, iclass 24, count 0 2006.252.08:09:17.94#ibcon#about to read 4, iclass 24, count 0 2006.252.08:09:17.94#ibcon#read 4, iclass 24, count 0 2006.252.08:09:17.94#ibcon#about to read 5, iclass 24, count 0 2006.252.08:09:17.94#ibcon#read 5, iclass 24, count 0 2006.252.08:09:17.94#ibcon#about to read 6, iclass 24, count 0 2006.252.08:09:17.94#ibcon#read 6, iclass 24, count 0 2006.252.08:09:17.94#ibcon#end of sib2, iclass 24, count 0 2006.252.08:09:17.94#ibcon#*mode == 0, iclass 24, count 0 2006.252.08:09:17.94#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.252.08:09:17.94#ibcon#[26=FRQ=01,532.99\r\n] 2006.252.08:09:17.94#ibcon#*before write, iclass 24, count 0 2006.252.08:09:17.94#ibcon#enter sib2, iclass 24, count 0 2006.252.08:09:17.94#ibcon#flushed, iclass 24, count 0 2006.252.08:09:17.94#ibcon#about to write, iclass 24, count 0 2006.252.08:09:17.94#ibcon#wrote, iclass 24, count 0 2006.252.08:09:17.94#ibcon#about to read 3, iclass 24, count 0 2006.252.08:09:17.99#ibcon#read 3, iclass 24, count 0 2006.252.08:09:17.99#ibcon#about to read 4, iclass 24, count 0 2006.252.08:09:17.99#ibcon#read 4, iclass 24, count 0 2006.252.08:09:17.99#ibcon#about to read 5, iclass 24, count 0 2006.252.08:09:17.99#ibcon#read 5, iclass 24, count 0 2006.252.08:09:17.99#ibcon#about to read 6, iclass 24, count 0 2006.252.08:09:17.99#ibcon#read 6, iclass 24, count 0 2006.252.08:09:17.99#ibcon#end of sib2, iclass 24, count 0 2006.252.08:09:17.99#ibcon#*after write, iclass 24, count 0 2006.252.08:09:17.99#ibcon#*before return 0, iclass 24, count 0 2006.252.08:09:17.99#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.252.08:09:17.99#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.252.08:09:17.99#ibcon#about to clear, iclass 24 cls_cnt 0 2006.252.08:09:17.99#ibcon#cleared, iclass 24 cls_cnt 0 2006.252.08:09:17.99$vc4f8/va=1,8 2006.252.08:09:17.99#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.252.08:09:17.99#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.252.08:09:17.99#ibcon#ireg 11 cls_cnt 2 2006.252.08:09:17.99#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.252.08:09:17.99#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.252.08:09:17.99#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.252.08:09:17.99#ibcon#enter wrdev, iclass 26, count 2 2006.252.08:09:17.99#ibcon#first serial, iclass 26, count 2 2006.252.08:09:17.99#ibcon#enter sib2, iclass 26, count 2 2006.252.08:09:17.99#ibcon#flushed, iclass 26, count 2 2006.252.08:09:17.99#ibcon#about to write, iclass 26, count 2 2006.252.08:09:17.99#ibcon#wrote, iclass 26, count 2 2006.252.08:09:17.99#ibcon#about to read 3, iclass 26, count 2 2006.252.08:09:18.01#ibcon#read 3, iclass 26, count 2 2006.252.08:09:18.01#ibcon#about to read 4, iclass 26, count 2 2006.252.08:09:18.01#ibcon#read 4, iclass 26, count 2 2006.252.08:09:18.01#ibcon#about to read 5, iclass 26, count 2 2006.252.08:09:18.01#ibcon#read 5, iclass 26, count 2 2006.252.08:09:18.01#ibcon#about to read 6, iclass 26, count 2 2006.252.08:09:18.01#ibcon#read 6, iclass 26, count 2 2006.252.08:09:18.01#ibcon#end of sib2, iclass 26, count 2 2006.252.08:09:18.01#ibcon#*mode == 0, iclass 26, count 2 2006.252.08:09:18.01#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.252.08:09:18.01#ibcon#[25=AT01-08\r\n] 2006.252.08:09:18.01#ibcon#*before write, iclass 26, count 2 2006.252.08:09:18.01#ibcon#enter sib2, iclass 26, count 2 2006.252.08:09:18.01#ibcon#flushed, iclass 26, count 2 2006.252.08:09:18.01#ibcon#about to write, iclass 26, count 2 2006.252.08:09:18.01#ibcon#wrote, iclass 26, count 2 2006.252.08:09:18.01#ibcon#about to read 3, iclass 26, count 2 2006.252.08:09:18.04#ibcon#read 3, iclass 26, count 2 2006.252.08:09:18.04#ibcon#about to read 4, iclass 26, count 2 2006.252.08:09:18.04#ibcon#read 4, iclass 26, count 2 2006.252.08:09:18.04#ibcon#about to read 5, iclass 26, count 2 2006.252.08:09:18.04#ibcon#read 5, iclass 26, count 2 2006.252.08:09:18.04#ibcon#about to read 6, iclass 26, count 2 2006.252.08:09:18.04#ibcon#read 6, iclass 26, count 2 2006.252.08:09:18.04#ibcon#end of sib2, iclass 26, count 2 2006.252.08:09:18.04#ibcon#*after write, iclass 26, count 2 2006.252.08:09:18.04#ibcon#*before return 0, iclass 26, count 2 2006.252.08:09:18.04#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.252.08:09:18.04#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.252.08:09:18.04#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.252.08:09:18.04#ibcon#ireg 7 cls_cnt 0 2006.252.08:09:18.04#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.252.08:09:18.16#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.252.08:09:18.16#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.252.08:09:18.16#ibcon#enter wrdev, iclass 26, count 0 2006.252.08:09:18.16#ibcon#first serial, iclass 26, count 0 2006.252.08:09:18.16#ibcon#enter sib2, iclass 26, count 0 2006.252.08:09:18.16#ibcon#flushed, iclass 26, count 0 2006.252.08:09:18.16#ibcon#about to write, iclass 26, count 0 2006.252.08:09:18.16#ibcon#wrote, iclass 26, count 0 2006.252.08:09:18.16#ibcon#about to read 3, iclass 26, count 0 2006.252.08:09:18.18#ibcon#read 3, iclass 26, count 0 2006.252.08:09:18.18#ibcon#about to read 4, iclass 26, count 0 2006.252.08:09:18.18#ibcon#read 4, iclass 26, count 0 2006.252.08:09:18.18#ibcon#about to read 5, iclass 26, count 0 2006.252.08:09:18.18#ibcon#read 5, iclass 26, count 0 2006.252.08:09:18.18#ibcon#about to read 6, iclass 26, count 0 2006.252.08:09:18.18#ibcon#read 6, iclass 26, count 0 2006.252.08:09:18.18#ibcon#end of sib2, iclass 26, count 0 2006.252.08:09:18.18#ibcon#*mode == 0, iclass 26, count 0 2006.252.08:09:18.18#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.252.08:09:18.18#ibcon#[25=USB\r\n] 2006.252.08:09:18.18#ibcon#*before write, iclass 26, count 0 2006.252.08:09:18.18#ibcon#enter sib2, iclass 26, count 0 2006.252.08:09:18.18#ibcon#flushed, iclass 26, count 0 2006.252.08:09:18.18#ibcon#about to write, iclass 26, count 0 2006.252.08:09:18.18#ibcon#wrote, iclass 26, count 0 2006.252.08:09:18.18#ibcon#about to read 3, iclass 26, count 0 2006.252.08:09:18.21#ibcon#read 3, iclass 26, count 0 2006.252.08:09:18.21#ibcon#about to read 4, iclass 26, count 0 2006.252.08:09:18.21#ibcon#read 4, iclass 26, count 0 2006.252.08:09:18.21#ibcon#about to read 5, iclass 26, count 0 2006.252.08:09:18.21#ibcon#read 5, iclass 26, count 0 2006.252.08:09:18.21#ibcon#about to read 6, iclass 26, count 0 2006.252.08:09:18.21#ibcon#read 6, iclass 26, count 0 2006.252.08:09:18.21#ibcon#end of sib2, iclass 26, count 0 2006.252.08:09:18.21#ibcon#*after write, iclass 26, count 0 2006.252.08:09:18.21#ibcon#*before return 0, iclass 26, count 0 2006.252.08:09:18.21#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.252.08:09:18.21#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.252.08:09:18.21#ibcon#about to clear, iclass 26 cls_cnt 0 2006.252.08:09:18.21#ibcon#cleared, iclass 26 cls_cnt 0 2006.252.08:09:18.21$vc4f8/valo=2,572.99 2006.252.08:09:18.21#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.252.08:09:18.21#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.252.08:09:18.21#ibcon#ireg 17 cls_cnt 0 2006.252.08:09:18.21#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.252.08:09:18.21#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.252.08:09:18.21#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.252.08:09:18.21#ibcon#enter wrdev, iclass 28, count 0 2006.252.08:09:18.21#ibcon#first serial, iclass 28, count 0 2006.252.08:09:18.21#ibcon#enter sib2, iclass 28, count 0 2006.252.08:09:18.21#ibcon#flushed, iclass 28, count 0 2006.252.08:09:18.21#ibcon#about to write, iclass 28, count 0 2006.252.08:09:18.21#ibcon#wrote, iclass 28, count 0 2006.252.08:09:18.21#ibcon#about to read 3, iclass 28, count 0 2006.252.08:09:18.23#ibcon#read 3, iclass 28, count 0 2006.252.08:09:18.23#ibcon#about to read 4, iclass 28, count 0 2006.252.08:09:18.23#ibcon#read 4, iclass 28, count 0 2006.252.08:09:18.23#ibcon#about to read 5, iclass 28, count 0 2006.252.08:09:18.23#ibcon#read 5, iclass 28, count 0 2006.252.08:09:18.23#ibcon#about to read 6, iclass 28, count 0 2006.252.08:09:18.23#ibcon#read 6, iclass 28, count 0 2006.252.08:09:18.23#ibcon#end of sib2, iclass 28, count 0 2006.252.08:09:18.23#ibcon#*mode == 0, iclass 28, count 0 2006.252.08:09:18.23#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.252.08:09:18.23#ibcon#[26=FRQ=02,572.99\r\n] 2006.252.08:09:18.23#ibcon#*before write, iclass 28, count 0 2006.252.08:09:18.23#ibcon#enter sib2, iclass 28, count 0 2006.252.08:09:18.23#ibcon#flushed, iclass 28, count 0 2006.252.08:09:18.23#ibcon#about to write, iclass 28, count 0 2006.252.08:09:18.23#ibcon#wrote, iclass 28, count 0 2006.252.08:09:18.23#ibcon#about to read 3, iclass 28, count 0 2006.252.08:09:18.27#ibcon#read 3, iclass 28, count 0 2006.252.08:09:18.27#ibcon#about to read 4, iclass 28, count 0 2006.252.08:09:18.27#ibcon#read 4, iclass 28, count 0 2006.252.08:09:18.27#ibcon#about to read 5, iclass 28, count 0 2006.252.08:09:18.27#ibcon#read 5, iclass 28, count 0 2006.252.08:09:18.27#ibcon#about to read 6, iclass 28, count 0 2006.252.08:09:18.27#ibcon#read 6, iclass 28, count 0 2006.252.08:09:18.27#ibcon#end of sib2, iclass 28, count 0 2006.252.08:09:18.27#ibcon#*after write, iclass 28, count 0 2006.252.08:09:18.27#ibcon#*before return 0, iclass 28, count 0 2006.252.08:09:18.27#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.252.08:09:18.27#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.252.08:09:18.27#ibcon#about to clear, iclass 28 cls_cnt 0 2006.252.08:09:18.27#ibcon#cleared, iclass 28 cls_cnt 0 2006.252.08:09:18.27$vc4f8/va=2,7 2006.252.08:09:18.27#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.252.08:09:18.27#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.252.08:09:18.27#ibcon#ireg 11 cls_cnt 2 2006.252.08:09:18.27#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.252.08:09:18.33#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.252.08:09:18.33#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.252.08:09:18.33#ibcon#enter wrdev, iclass 30, count 2 2006.252.08:09:18.33#ibcon#first serial, iclass 30, count 2 2006.252.08:09:18.33#ibcon#enter sib2, iclass 30, count 2 2006.252.08:09:18.33#ibcon#flushed, iclass 30, count 2 2006.252.08:09:18.33#ibcon#about to write, iclass 30, count 2 2006.252.08:09:18.33#ibcon#wrote, iclass 30, count 2 2006.252.08:09:18.33#ibcon#about to read 3, iclass 30, count 2 2006.252.08:09:18.35#ibcon#read 3, iclass 30, count 2 2006.252.08:09:18.35#ibcon#about to read 4, iclass 30, count 2 2006.252.08:09:18.35#ibcon#read 4, iclass 30, count 2 2006.252.08:09:18.35#ibcon#about to read 5, iclass 30, count 2 2006.252.08:09:18.35#ibcon#read 5, iclass 30, count 2 2006.252.08:09:18.35#ibcon#about to read 6, iclass 30, count 2 2006.252.08:09:18.35#ibcon#read 6, iclass 30, count 2 2006.252.08:09:18.35#ibcon#end of sib2, iclass 30, count 2 2006.252.08:09:18.35#ibcon#*mode == 0, iclass 30, count 2 2006.252.08:09:18.35#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.252.08:09:18.35#ibcon#[25=AT02-07\r\n] 2006.252.08:09:18.35#ibcon#*before write, iclass 30, count 2 2006.252.08:09:18.35#ibcon#enter sib2, iclass 30, count 2 2006.252.08:09:18.35#ibcon#flushed, iclass 30, count 2 2006.252.08:09:18.35#ibcon#about to write, iclass 30, count 2 2006.252.08:09:18.35#ibcon#wrote, iclass 30, count 2 2006.252.08:09:18.35#ibcon#about to read 3, iclass 30, count 2 2006.252.08:09:18.38#ibcon#read 3, iclass 30, count 2 2006.252.08:09:18.38#ibcon#about to read 4, iclass 30, count 2 2006.252.08:09:18.38#ibcon#read 4, iclass 30, count 2 2006.252.08:09:18.38#ibcon#about to read 5, iclass 30, count 2 2006.252.08:09:18.38#ibcon#read 5, iclass 30, count 2 2006.252.08:09:18.38#ibcon#about to read 6, iclass 30, count 2 2006.252.08:09:18.38#ibcon#read 6, iclass 30, count 2 2006.252.08:09:18.38#ibcon#end of sib2, iclass 30, count 2 2006.252.08:09:18.38#ibcon#*after write, iclass 30, count 2 2006.252.08:09:18.38#ibcon#*before return 0, iclass 30, count 2 2006.252.08:09:18.38#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.252.08:09:18.38#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.252.08:09:18.38#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.252.08:09:18.38#ibcon#ireg 7 cls_cnt 0 2006.252.08:09:18.38#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.252.08:09:18.50#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.252.08:09:18.50#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.252.08:09:18.50#ibcon#enter wrdev, iclass 30, count 0 2006.252.08:09:18.50#ibcon#first serial, iclass 30, count 0 2006.252.08:09:18.50#ibcon#enter sib2, iclass 30, count 0 2006.252.08:09:18.50#ibcon#flushed, iclass 30, count 0 2006.252.08:09:18.50#ibcon#about to write, iclass 30, count 0 2006.252.08:09:18.50#ibcon#wrote, iclass 30, count 0 2006.252.08:09:18.50#ibcon#about to read 3, iclass 30, count 0 2006.252.08:09:18.52#ibcon#read 3, iclass 30, count 0 2006.252.08:09:18.52#ibcon#about to read 4, iclass 30, count 0 2006.252.08:09:18.52#ibcon#read 4, iclass 30, count 0 2006.252.08:09:18.52#ibcon#about to read 5, iclass 30, count 0 2006.252.08:09:18.52#ibcon#read 5, iclass 30, count 0 2006.252.08:09:18.52#ibcon#about to read 6, iclass 30, count 0 2006.252.08:09:18.52#ibcon#read 6, iclass 30, count 0 2006.252.08:09:18.52#ibcon#end of sib2, iclass 30, count 0 2006.252.08:09:18.52#ibcon#*mode == 0, iclass 30, count 0 2006.252.08:09:18.52#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.252.08:09:18.52#ibcon#[25=USB\r\n] 2006.252.08:09:18.52#ibcon#*before write, iclass 30, count 0 2006.252.08:09:18.52#ibcon#enter sib2, iclass 30, count 0 2006.252.08:09:18.52#ibcon#flushed, iclass 30, count 0 2006.252.08:09:18.52#ibcon#about to write, iclass 30, count 0 2006.252.08:09:18.52#ibcon#wrote, iclass 30, count 0 2006.252.08:09:18.52#ibcon#about to read 3, iclass 30, count 0 2006.252.08:09:18.55#ibcon#read 3, iclass 30, count 0 2006.252.08:09:18.55#ibcon#about to read 4, iclass 30, count 0 2006.252.08:09:18.55#ibcon#read 4, iclass 30, count 0 2006.252.08:09:18.55#ibcon#about to read 5, iclass 30, count 0 2006.252.08:09:18.55#ibcon#read 5, iclass 30, count 0 2006.252.08:09:18.55#ibcon#about to read 6, iclass 30, count 0 2006.252.08:09:18.55#ibcon#read 6, iclass 30, count 0 2006.252.08:09:18.55#ibcon#end of sib2, iclass 30, count 0 2006.252.08:09:18.55#ibcon#*after write, iclass 30, count 0 2006.252.08:09:18.55#ibcon#*before return 0, iclass 30, count 0 2006.252.08:09:18.55#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.252.08:09:18.55#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.252.08:09:18.55#ibcon#about to clear, iclass 30 cls_cnt 0 2006.252.08:09:18.55#ibcon#cleared, iclass 30 cls_cnt 0 2006.252.08:09:18.55$vc4f8/valo=3,672.99 2006.252.08:09:18.55#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.252.08:09:18.55#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.252.08:09:18.55#ibcon#ireg 17 cls_cnt 0 2006.252.08:09:18.55#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.252.08:09:18.55#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.252.08:09:18.55#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.252.08:09:18.55#ibcon#enter wrdev, iclass 32, count 0 2006.252.08:09:18.55#ibcon#first serial, iclass 32, count 0 2006.252.08:09:18.55#ibcon#enter sib2, iclass 32, count 0 2006.252.08:09:18.55#ibcon#flushed, iclass 32, count 0 2006.252.08:09:18.55#ibcon#about to write, iclass 32, count 0 2006.252.08:09:18.55#ibcon#wrote, iclass 32, count 0 2006.252.08:09:18.55#ibcon#about to read 3, iclass 32, count 0 2006.252.08:09:18.57#ibcon#read 3, iclass 32, count 0 2006.252.08:09:18.57#ibcon#about to read 4, iclass 32, count 0 2006.252.08:09:18.57#ibcon#read 4, iclass 32, count 0 2006.252.08:09:18.57#ibcon#about to read 5, iclass 32, count 0 2006.252.08:09:18.57#ibcon#read 5, iclass 32, count 0 2006.252.08:09:18.57#ibcon#about to read 6, iclass 32, count 0 2006.252.08:09:18.57#ibcon#read 6, iclass 32, count 0 2006.252.08:09:18.57#ibcon#end of sib2, iclass 32, count 0 2006.252.08:09:18.57#ibcon#*mode == 0, iclass 32, count 0 2006.252.08:09:18.57#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.252.08:09:18.57#ibcon#[26=FRQ=03,672.99\r\n] 2006.252.08:09:18.57#ibcon#*before write, iclass 32, count 0 2006.252.08:09:18.57#ibcon#enter sib2, iclass 32, count 0 2006.252.08:09:18.57#ibcon#flushed, iclass 32, count 0 2006.252.08:09:18.57#ibcon#about to write, iclass 32, count 0 2006.252.08:09:18.57#ibcon#wrote, iclass 32, count 0 2006.252.08:09:18.57#ibcon#about to read 3, iclass 32, count 0 2006.252.08:09:18.62#ibcon#read 3, iclass 32, count 0 2006.252.08:09:18.62#ibcon#about to read 4, iclass 32, count 0 2006.252.08:09:18.62#ibcon#read 4, iclass 32, count 0 2006.252.08:09:18.62#ibcon#about to read 5, iclass 32, count 0 2006.252.08:09:18.62#ibcon#read 5, iclass 32, count 0 2006.252.08:09:18.62#ibcon#about to read 6, iclass 32, count 0 2006.252.08:09:18.62#ibcon#read 6, iclass 32, count 0 2006.252.08:09:18.62#ibcon#end of sib2, iclass 32, count 0 2006.252.08:09:18.62#ibcon#*after write, iclass 32, count 0 2006.252.08:09:18.62#ibcon#*before return 0, iclass 32, count 0 2006.252.08:09:18.62#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.252.08:09:18.62#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.252.08:09:18.62#ibcon#about to clear, iclass 32 cls_cnt 0 2006.252.08:09:18.62#ibcon#cleared, iclass 32 cls_cnt 0 2006.252.08:09:18.62$vc4f8/va=3,6 2006.252.08:09:18.62#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.252.08:09:18.62#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.252.08:09:18.62#ibcon#ireg 11 cls_cnt 2 2006.252.08:09:18.62#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.252.08:09:18.67#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.252.08:09:18.67#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.252.08:09:18.67#ibcon#enter wrdev, iclass 34, count 2 2006.252.08:09:18.67#ibcon#first serial, iclass 34, count 2 2006.252.08:09:18.67#ibcon#enter sib2, iclass 34, count 2 2006.252.08:09:18.67#ibcon#flushed, iclass 34, count 2 2006.252.08:09:18.67#ibcon#about to write, iclass 34, count 2 2006.252.08:09:18.67#ibcon#wrote, iclass 34, count 2 2006.252.08:09:18.67#ibcon#about to read 3, iclass 34, count 2 2006.252.08:09:18.69#ibcon#read 3, iclass 34, count 2 2006.252.08:09:18.69#ibcon#about to read 4, iclass 34, count 2 2006.252.08:09:18.69#ibcon#read 4, iclass 34, count 2 2006.252.08:09:18.69#ibcon#about to read 5, iclass 34, count 2 2006.252.08:09:18.69#ibcon#read 5, iclass 34, count 2 2006.252.08:09:18.69#ibcon#about to read 6, iclass 34, count 2 2006.252.08:09:18.69#ibcon#read 6, iclass 34, count 2 2006.252.08:09:18.69#ibcon#end of sib2, iclass 34, count 2 2006.252.08:09:18.69#ibcon#*mode == 0, iclass 34, count 2 2006.252.08:09:18.69#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.252.08:09:18.69#ibcon#[25=AT03-06\r\n] 2006.252.08:09:18.69#ibcon#*before write, iclass 34, count 2 2006.252.08:09:18.69#ibcon#enter sib2, iclass 34, count 2 2006.252.08:09:18.69#ibcon#flushed, iclass 34, count 2 2006.252.08:09:18.69#ibcon#about to write, iclass 34, count 2 2006.252.08:09:18.69#ibcon#wrote, iclass 34, count 2 2006.252.08:09:18.69#ibcon#about to read 3, iclass 34, count 2 2006.252.08:09:18.72#ibcon#read 3, iclass 34, count 2 2006.252.08:09:18.72#ibcon#about to read 4, iclass 34, count 2 2006.252.08:09:18.72#ibcon#read 4, iclass 34, count 2 2006.252.08:09:18.72#ibcon#about to read 5, iclass 34, count 2 2006.252.08:09:18.72#ibcon#read 5, iclass 34, count 2 2006.252.08:09:18.72#ibcon#about to read 6, iclass 34, count 2 2006.252.08:09:18.72#ibcon#read 6, iclass 34, count 2 2006.252.08:09:18.72#ibcon#end of sib2, iclass 34, count 2 2006.252.08:09:18.72#ibcon#*after write, iclass 34, count 2 2006.252.08:09:18.72#ibcon#*before return 0, iclass 34, count 2 2006.252.08:09:18.72#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.252.08:09:18.72#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.252.08:09:18.72#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.252.08:09:18.72#ibcon#ireg 7 cls_cnt 0 2006.252.08:09:18.72#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.252.08:09:18.84#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.252.08:09:18.84#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.252.08:09:18.84#ibcon#enter wrdev, iclass 34, count 0 2006.252.08:09:18.84#ibcon#first serial, iclass 34, count 0 2006.252.08:09:18.84#ibcon#enter sib2, iclass 34, count 0 2006.252.08:09:18.84#ibcon#flushed, iclass 34, count 0 2006.252.08:09:18.84#ibcon#about to write, iclass 34, count 0 2006.252.08:09:18.84#ibcon#wrote, iclass 34, count 0 2006.252.08:09:18.84#ibcon#about to read 3, iclass 34, count 0 2006.252.08:09:18.86#ibcon#read 3, iclass 34, count 0 2006.252.08:09:18.86#ibcon#about to read 4, iclass 34, count 0 2006.252.08:09:18.86#ibcon#read 4, iclass 34, count 0 2006.252.08:09:18.86#ibcon#about to read 5, iclass 34, count 0 2006.252.08:09:18.86#ibcon#read 5, iclass 34, count 0 2006.252.08:09:18.86#ibcon#about to read 6, iclass 34, count 0 2006.252.08:09:18.86#ibcon#read 6, iclass 34, count 0 2006.252.08:09:18.86#ibcon#end of sib2, iclass 34, count 0 2006.252.08:09:18.86#ibcon#*mode == 0, iclass 34, count 0 2006.252.08:09:18.86#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.252.08:09:18.86#ibcon#[25=USB\r\n] 2006.252.08:09:18.86#ibcon#*before write, iclass 34, count 0 2006.252.08:09:18.86#ibcon#enter sib2, iclass 34, count 0 2006.252.08:09:18.86#ibcon#flushed, iclass 34, count 0 2006.252.08:09:18.86#ibcon#about to write, iclass 34, count 0 2006.252.08:09:18.86#ibcon#wrote, iclass 34, count 0 2006.252.08:09:18.86#ibcon#about to read 3, iclass 34, count 0 2006.252.08:09:18.89#ibcon#read 3, iclass 34, count 0 2006.252.08:09:18.89#ibcon#about to read 4, iclass 34, count 0 2006.252.08:09:18.89#ibcon#read 4, iclass 34, count 0 2006.252.08:09:18.89#ibcon#about to read 5, iclass 34, count 0 2006.252.08:09:18.89#ibcon#read 5, iclass 34, count 0 2006.252.08:09:18.89#ibcon#about to read 6, iclass 34, count 0 2006.252.08:09:18.89#ibcon#read 6, iclass 34, count 0 2006.252.08:09:18.89#ibcon#end of sib2, iclass 34, count 0 2006.252.08:09:18.89#ibcon#*after write, iclass 34, count 0 2006.252.08:09:18.89#ibcon#*before return 0, iclass 34, count 0 2006.252.08:09:18.89#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.252.08:09:18.89#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.252.08:09:18.89#ibcon#about to clear, iclass 34 cls_cnt 0 2006.252.08:09:18.89#ibcon#cleared, iclass 34 cls_cnt 0 2006.252.08:09:18.89$vc4f8/valo=4,832.99 2006.252.08:09:18.89#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.252.08:09:18.89#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.252.08:09:18.89#ibcon#ireg 17 cls_cnt 0 2006.252.08:09:18.89#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.252.08:09:18.89#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.252.08:09:18.89#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.252.08:09:18.89#ibcon#enter wrdev, iclass 36, count 0 2006.252.08:09:18.89#ibcon#first serial, iclass 36, count 0 2006.252.08:09:18.89#ibcon#enter sib2, iclass 36, count 0 2006.252.08:09:18.89#ibcon#flushed, iclass 36, count 0 2006.252.08:09:18.89#ibcon#about to write, iclass 36, count 0 2006.252.08:09:18.89#ibcon#wrote, iclass 36, count 0 2006.252.08:09:18.89#ibcon#about to read 3, iclass 36, count 0 2006.252.08:09:18.91#ibcon#read 3, iclass 36, count 0 2006.252.08:09:18.91#ibcon#about to read 4, iclass 36, count 0 2006.252.08:09:18.91#ibcon#read 4, iclass 36, count 0 2006.252.08:09:18.91#ibcon#about to read 5, iclass 36, count 0 2006.252.08:09:18.91#ibcon#read 5, iclass 36, count 0 2006.252.08:09:18.91#ibcon#about to read 6, iclass 36, count 0 2006.252.08:09:18.91#ibcon#read 6, iclass 36, count 0 2006.252.08:09:18.91#ibcon#end of sib2, iclass 36, count 0 2006.252.08:09:18.91#ibcon#*mode == 0, iclass 36, count 0 2006.252.08:09:18.91#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.252.08:09:18.91#ibcon#[26=FRQ=04,832.99\r\n] 2006.252.08:09:18.91#ibcon#*before write, iclass 36, count 0 2006.252.08:09:18.91#ibcon#enter sib2, iclass 36, count 0 2006.252.08:09:18.91#ibcon#flushed, iclass 36, count 0 2006.252.08:09:18.91#ibcon#about to write, iclass 36, count 0 2006.252.08:09:18.91#ibcon#wrote, iclass 36, count 0 2006.252.08:09:18.91#ibcon#about to read 3, iclass 36, count 0 2006.252.08:09:18.96#ibcon#read 3, iclass 36, count 0 2006.252.08:09:18.96#ibcon#about to read 4, iclass 36, count 0 2006.252.08:09:18.96#ibcon#read 4, iclass 36, count 0 2006.252.08:09:18.96#ibcon#about to read 5, iclass 36, count 0 2006.252.08:09:18.96#ibcon#read 5, iclass 36, count 0 2006.252.08:09:18.96#ibcon#about to read 6, iclass 36, count 0 2006.252.08:09:18.96#ibcon#read 6, iclass 36, count 0 2006.252.08:09:18.96#ibcon#end of sib2, iclass 36, count 0 2006.252.08:09:18.96#ibcon#*after write, iclass 36, count 0 2006.252.08:09:18.96#ibcon#*before return 0, iclass 36, count 0 2006.252.08:09:18.96#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.252.08:09:18.96#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.252.08:09:18.96#ibcon#about to clear, iclass 36 cls_cnt 0 2006.252.08:09:18.96#ibcon#cleared, iclass 36 cls_cnt 0 2006.252.08:09:18.96$vc4f8/va=4,7 2006.252.08:09:18.96#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.252.08:09:18.96#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.252.08:09:18.96#ibcon#ireg 11 cls_cnt 2 2006.252.08:09:18.96#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.252.08:09:19.01#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.252.08:09:19.01#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.252.08:09:19.01#ibcon#enter wrdev, iclass 38, count 2 2006.252.08:09:19.01#ibcon#first serial, iclass 38, count 2 2006.252.08:09:19.01#ibcon#enter sib2, iclass 38, count 2 2006.252.08:09:19.01#ibcon#flushed, iclass 38, count 2 2006.252.08:09:19.01#ibcon#about to write, iclass 38, count 2 2006.252.08:09:19.01#ibcon#wrote, iclass 38, count 2 2006.252.08:09:19.01#ibcon#about to read 3, iclass 38, count 2 2006.252.08:09:19.03#ibcon#read 3, iclass 38, count 2 2006.252.08:09:19.03#ibcon#about to read 4, iclass 38, count 2 2006.252.08:09:19.03#ibcon#read 4, iclass 38, count 2 2006.252.08:09:19.03#ibcon#about to read 5, iclass 38, count 2 2006.252.08:09:19.03#ibcon#read 5, iclass 38, count 2 2006.252.08:09:19.03#ibcon#about to read 6, iclass 38, count 2 2006.252.08:09:19.03#ibcon#read 6, iclass 38, count 2 2006.252.08:09:19.03#ibcon#end of sib2, iclass 38, count 2 2006.252.08:09:19.03#ibcon#*mode == 0, iclass 38, count 2 2006.252.08:09:19.03#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.252.08:09:19.03#ibcon#[25=AT04-07\r\n] 2006.252.08:09:19.03#ibcon#*before write, iclass 38, count 2 2006.252.08:09:19.03#ibcon#enter sib2, iclass 38, count 2 2006.252.08:09:19.03#ibcon#flushed, iclass 38, count 2 2006.252.08:09:19.03#ibcon#about to write, iclass 38, count 2 2006.252.08:09:19.03#ibcon#wrote, iclass 38, count 2 2006.252.08:09:19.03#ibcon#about to read 3, iclass 38, count 2 2006.252.08:09:19.06#ibcon#read 3, iclass 38, count 2 2006.252.08:09:19.06#ibcon#about to read 4, iclass 38, count 2 2006.252.08:09:19.06#ibcon#read 4, iclass 38, count 2 2006.252.08:09:19.06#ibcon#about to read 5, iclass 38, count 2 2006.252.08:09:19.06#ibcon#read 5, iclass 38, count 2 2006.252.08:09:19.06#ibcon#about to read 6, iclass 38, count 2 2006.252.08:09:19.06#ibcon#read 6, iclass 38, count 2 2006.252.08:09:19.06#ibcon#end of sib2, iclass 38, count 2 2006.252.08:09:19.06#ibcon#*after write, iclass 38, count 2 2006.252.08:09:19.06#ibcon#*before return 0, iclass 38, count 2 2006.252.08:09:19.06#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.252.08:09:19.06#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.252.08:09:19.06#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.252.08:09:19.06#ibcon#ireg 7 cls_cnt 0 2006.252.08:09:19.06#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.252.08:09:19.18#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.252.08:09:19.18#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.252.08:09:19.18#ibcon#enter wrdev, iclass 38, count 0 2006.252.08:09:19.18#ibcon#first serial, iclass 38, count 0 2006.252.08:09:19.18#ibcon#enter sib2, iclass 38, count 0 2006.252.08:09:19.18#ibcon#flushed, iclass 38, count 0 2006.252.08:09:19.18#ibcon#about to write, iclass 38, count 0 2006.252.08:09:19.18#ibcon#wrote, iclass 38, count 0 2006.252.08:09:19.18#ibcon#about to read 3, iclass 38, count 0 2006.252.08:09:19.20#ibcon#read 3, iclass 38, count 0 2006.252.08:09:19.20#ibcon#about to read 4, iclass 38, count 0 2006.252.08:09:19.20#ibcon#read 4, iclass 38, count 0 2006.252.08:09:19.20#ibcon#about to read 5, iclass 38, count 0 2006.252.08:09:19.20#ibcon#read 5, iclass 38, count 0 2006.252.08:09:19.20#ibcon#about to read 6, iclass 38, count 0 2006.252.08:09:19.20#ibcon#read 6, iclass 38, count 0 2006.252.08:09:19.20#ibcon#end of sib2, iclass 38, count 0 2006.252.08:09:19.20#ibcon#*mode == 0, iclass 38, count 0 2006.252.08:09:19.20#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.252.08:09:19.20#ibcon#[25=USB\r\n] 2006.252.08:09:19.20#ibcon#*before write, iclass 38, count 0 2006.252.08:09:19.20#ibcon#enter sib2, iclass 38, count 0 2006.252.08:09:19.20#ibcon#flushed, iclass 38, count 0 2006.252.08:09:19.20#ibcon#about to write, iclass 38, count 0 2006.252.08:09:19.20#ibcon#wrote, iclass 38, count 0 2006.252.08:09:19.20#ibcon#about to read 3, iclass 38, count 0 2006.252.08:09:19.23#ibcon#read 3, iclass 38, count 0 2006.252.08:09:19.23#ibcon#about to read 4, iclass 38, count 0 2006.252.08:09:19.23#ibcon#read 4, iclass 38, count 0 2006.252.08:09:19.23#ibcon#about to read 5, iclass 38, count 0 2006.252.08:09:19.23#ibcon#read 5, iclass 38, count 0 2006.252.08:09:19.23#ibcon#about to read 6, iclass 38, count 0 2006.252.08:09:19.23#ibcon#read 6, iclass 38, count 0 2006.252.08:09:19.23#ibcon#end of sib2, iclass 38, count 0 2006.252.08:09:19.23#ibcon#*after write, iclass 38, count 0 2006.252.08:09:19.23#ibcon#*before return 0, iclass 38, count 0 2006.252.08:09:19.23#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.252.08:09:19.23#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.252.08:09:19.23#ibcon#about to clear, iclass 38 cls_cnt 0 2006.252.08:09:19.23#ibcon#cleared, iclass 38 cls_cnt 0 2006.252.08:09:19.23$vc4f8/valo=5,652.99 2006.252.08:09:19.23#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.252.08:09:19.23#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.252.08:09:19.23#ibcon#ireg 17 cls_cnt 0 2006.252.08:09:19.23#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.252.08:09:19.23#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.252.08:09:19.23#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.252.08:09:19.23#ibcon#enter wrdev, iclass 40, count 0 2006.252.08:09:19.23#ibcon#first serial, iclass 40, count 0 2006.252.08:09:19.23#ibcon#enter sib2, iclass 40, count 0 2006.252.08:09:19.23#ibcon#flushed, iclass 40, count 0 2006.252.08:09:19.23#ibcon#about to write, iclass 40, count 0 2006.252.08:09:19.23#ibcon#wrote, iclass 40, count 0 2006.252.08:09:19.23#ibcon#about to read 3, iclass 40, count 0 2006.252.08:09:19.25#ibcon#read 3, iclass 40, count 0 2006.252.08:09:19.25#ibcon#about to read 4, iclass 40, count 0 2006.252.08:09:19.25#ibcon#read 4, iclass 40, count 0 2006.252.08:09:19.25#ibcon#about to read 5, iclass 40, count 0 2006.252.08:09:19.25#ibcon#read 5, iclass 40, count 0 2006.252.08:09:19.25#ibcon#about to read 6, iclass 40, count 0 2006.252.08:09:19.25#ibcon#read 6, iclass 40, count 0 2006.252.08:09:19.25#ibcon#end of sib2, iclass 40, count 0 2006.252.08:09:19.25#ibcon#*mode == 0, iclass 40, count 0 2006.252.08:09:19.25#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.252.08:09:19.25#ibcon#[26=FRQ=05,652.99\r\n] 2006.252.08:09:19.25#ibcon#*before write, iclass 40, count 0 2006.252.08:09:19.25#ibcon#enter sib2, iclass 40, count 0 2006.252.08:09:19.25#ibcon#flushed, iclass 40, count 0 2006.252.08:09:19.25#ibcon#about to write, iclass 40, count 0 2006.252.08:09:19.25#ibcon#wrote, iclass 40, count 0 2006.252.08:09:19.25#ibcon#about to read 3, iclass 40, count 0 2006.252.08:09:19.29#ibcon#read 3, iclass 40, count 0 2006.252.08:09:19.29#ibcon#about to read 4, iclass 40, count 0 2006.252.08:09:19.29#ibcon#read 4, iclass 40, count 0 2006.252.08:09:19.29#ibcon#about to read 5, iclass 40, count 0 2006.252.08:09:19.29#ibcon#read 5, iclass 40, count 0 2006.252.08:09:19.29#ibcon#about to read 6, iclass 40, count 0 2006.252.08:09:19.29#ibcon#read 6, iclass 40, count 0 2006.252.08:09:19.29#ibcon#end of sib2, iclass 40, count 0 2006.252.08:09:19.29#ibcon#*after write, iclass 40, count 0 2006.252.08:09:19.29#ibcon#*before return 0, iclass 40, count 0 2006.252.08:09:19.29#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.252.08:09:19.29#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.252.08:09:19.29#ibcon#about to clear, iclass 40 cls_cnt 0 2006.252.08:09:19.29#ibcon#cleared, iclass 40 cls_cnt 0 2006.252.08:09:19.29$vc4f8/va=5,7 2006.252.08:09:19.29#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.252.08:09:19.29#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.252.08:09:19.29#ibcon#ireg 11 cls_cnt 2 2006.252.08:09:19.29#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.252.08:09:19.35#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.252.08:09:19.35#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.252.08:09:19.35#ibcon#enter wrdev, iclass 4, count 2 2006.252.08:09:19.35#ibcon#first serial, iclass 4, count 2 2006.252.08:09:19.35#ibcon#enter sib2, iclass 4, count 2 2006.252.08:09:19.35#ibcon#flushed, iclass 4, count 2 2006.252.08:09:19.35#ibcon#about to write, iclass 4, count 2 2006.252.08:09:19.35#ibcon#wrote, iclass 4, count 2 2006.252.08:09:19.35#ibcon#about to read 3, iclass 4, count 2 2006.252.08:09:19.37#ibcon#read 3, iclass 4, count 2 2006.252.08:09:19.37#ibcon#about to read 4, iclass 4, count 2 2006.252.08:09:19.37#ibcon#read 4, iclass 4, count 2 2006.252.08:09:19.37#ibcon#about to read 5, iclass 4, count 2 2006.252.08:09:19.37#ibcon#read 5, iclass 4, count 2 2006.252.08:09:19.37#ibcon#about to read 6, iclass 4, count 2 2006.252.08:09:19.37#ibcon#read 6, iclass 4, count 2 2006.252.08:09:19.37#ibcon#end of sib2, iclass 4, count 2 2006.252.08:09:19.37#ibcon#*mode == 0, iclass 4, count 2 2006.252.08:09:19.37#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.252.08:09:19.37#ibcon#[25=AT05-07\r\n] 2006.252.08:09:19.37#ibcon#*before write, iclass 4, count 2 2006.252.08:09:19.37#ibcon#enter sib2, iclass 4, count 2 2006.252.08:09:19.37#ibcon#flushed, iclass 4, count 2 2006.252.08:09:19.37#ibcon#about to write, iclass 4, count 2 2006.252.08:09:19.37#ibcon#wrote, iclass 4, count 2 2006.252.08:09:19.37#ibcon#about to read 3, iclass 4, count 2 2006.252.08:09:19.40#ibcon#read 3, iclass 4, count 2 2006.252.08:09:19.40#ibcon#about to read 4, iclass 4, count 2 2006.252.08:09:19.40#ibcon#read 4, iclass 4, count 2 2006.252.08:09:19.40#ibcon#about to read 5, iclass 4, count 2 2006.252.08:09:19.40#ibcon#read 5, iclass 4, count 2 2006.252.08:09:19.40#ibcon#about to read 6, iclass 4, count 2 2006.252.08:09:19.40#ibcon#read 6, iclass 4, count 2 2006.252.08:09:19.40#ibcon#end of sib2, iclass 4, count 2 2006.252.08:09:19.40#ibcon#*after write, iclass 4, count 2 2006.252.08:09:19.40#ibcon#*before return 0, iclass 4, count 2 2006.252.08:09:19.40#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.252.08:09:19.40#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.252.08:09:19.40#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.252.08:09:19.40#ibcon#ireg 7 cls_cnt 0 2006.252.08:09:19.40#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.252.08:09:19.52#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.252.08:09:19.52#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.252.08:09:19.52#ibcon#enter wrdev, iclass 4, count 0 2006.252.08:09:19.52#ibcon#first serial, iclass 4, count 0 2006.252.08:09:19.52#ibcon#enter sib2, iclass 4, count 0 2006.252.08:09:19.52#ibcon#flushed, iclass 4, count 0 2006.252.08:09:19.52#ibcon#about to write, iclass 4, count 0 2006.252.08:09:19.52#ibcon#wrote, iclass 4, count 0 2006.252.08:09:19.52#ibcon#about to read 3, iclass 4, count 0 2006.252.08:09:19.54#ibcon#read 3, iclass 4, count 0 2006.252.08:09:19.54#ibcon#about to read 4, iclass 4, count 0 2006.252.08:09:19.54#ibcon#read 4, iclass 4, count 0 2006.252.08:09:19.54#ibcon#about to read 5, iclass 4, count 0 2006.252.08:09:19.54#ibcon#read 5, iclass 4, count 0 2006.252.08:09:19.54#ibcon#about to read 6, iclass 4, count 0 2006.252.08:09:19.54#ibcon#read 6, iclass 4, count 0 2006.252.08:09:19.54#ibcon#end of sib2, iclass 4, count 0 2006.252.08:09:19.54#ibcon#*mode == 0, iclass 4, count 0 2006.252.08:09:19.54#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.252.08:09:19.54#ibcon#[25=USB\r\n] 2006.252.08:09:19.54#ibcon#*before write, iclass 4, count 0 2006.252.08:09:19.54#ibcon#enter sib2, iclass 4, count 0 2006.252.08:09:19.54#ibcon#flushed, iclass 4, count 0 2006.252.08:09:19.54#ibcon#about to write, iclass 4, count 0 2006.252.08:09:19.54#ibcon#wrote, iclass 4, count 0 2006.252.08:09:19.54#ibcon#about to read 3, iclass 4, count 0 2006.252.08:09:19.57#ibcon#read 3, iclass 4, count 0 2006.252.08:09:19.57#ibcon#about to read 4, iclass 4, count 0 2006.252.08:09:19.57#ibcon#read 4, iclass 4, count 0 2006.252.08:09:19.57#ibcon#about to read 5, iclass 4, count 0 2006.252.08:09:19.57#ibcon#read 5, iclass 4, count 0 2006.252.08:09:19.57#ibcon#about to read 6, iclass 4, count 0 2006.252.08:09:19.57#ibcon#read 6, iclass 4, count 0 2006.252.08:09:19.57#ibcon#end of sib2, iclass 4, count 0 2006.252.08:09:19.57#ibcon#*after write, iclass 4, count 0 2006.252.08:09:19.57#ibcon#*before return 0, iclass 4, count 0 2006.252.08:09:19.57#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.252.08:09:19.57#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.252.08:09:19.57#ibcon#about to clear, iclass 4 cls_cnt 0 2006.252.08:09:19.57#ibcon#cleared, iclass 4 cls_cnt 0 2006.252.08:09:19.57$vc4f8/valo=6,772.99 2006.252.08:09:19.57#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.252.08:09:19.57#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.252.08:09:19.57#ibcon#ireg 17 cls_cnt 0 2006.252.08:09:19.57#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.252.08:09:19.57#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.252.08:09:19.57#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.252.08:09:19.57#ibcon#enter wrdev, iclass 6, count 0 2006.252.08:09:19.57#ibcon#first serial, iclass 6, count 0 2006.252.08:09:19.57#ibcon#enter sib2, iclass 6, count 0 2006.252.08:09:19.57#ibcon#flushed, iclass 6, count 0 2006.252.08:09:19.57#ibcon#about to write, iclass 6, count 0 2006.252.08:09:19.57#ibcon#wrote, iclass 6, count 0 2006.252.08:09:19.57#ibcon#about to read 3, iclass 6, count 0 2006.252.08:09:19.59#ibcon#read 3, iclass 6, count 0 2006.252.08:09:19.59#ibcon#about to read 4, iclass 6, count 0 2006.252.08:09:19.59#ibcon#read 4, iclass 6, count 0 2006.252.08:09:19.59#ibcon#about to read 5, iclass 6, count 0 2006.252.08:09:19.59#ibcon#read 5, iclass 6, count 0 2006.252.08:09:19.59#ibcon#about to read 6, iclass 6, count 0 2006.252.08:09:19.59#ibcon#read 6, iclass 6, count 0 2006.252.08:09:19.59#ibcon#end of sib2, iclass 6, count 0 2006.252.08:09:19.59#ibcon#*mode == 0, iclass 6, count 0 2006.252.08:09:19.59#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.252.08:09:19.59#ibcon#[26=FRQ=06,772.99\r\n] 2006.252.08:09:19.59#ibcon#*before write, iclass 6, count 0 2006.252.08:09:19.59#ibcon#enter sib2, iclass 6, count 0 2006.252.08:09:19.59#ibcon#flushed, iclass 6, count 0 2006.252.08:09:19.59#ibcon#about to write, iclass 6, count 0 2006.252.08:09:19.59#ibcon#wrote, iclass 6, count 0 2006.252.08:09:19.59#ibcon#about to read 3, iclass 6, count 0 2006.252.08:09:19.64#ibcon#read 3, iclass 6, count 0 2006.252.08:09:19.64#ibcon#about to read 4, iclass 6, count 0 2006.252.08:09:19.64#ibcon#read 4, iclass 6, count 0 2006.252.08:09:19.64#ibcon#about to read 5, iclass 6, count 0 2006.252.08:09:19.64#ibcon#read 5, iclass 6, count 0 2006.252.08:09:19.64#ibcon#about to read 6, iclass 6, count 0 2006.252.08:09:19.64#ibcon#read 6, iclass 6, count 0 2006.252.08:09:19.64#ibcon#end of sib2, iclass 6, count 0 2006.252.08:09:19.64#ibcon#*after write, iclass 6, count 0 2006.252.08:09:19.64#ibcon#*before return 0, iclass 6, count 0 2006.252.08:09:19.64#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.252.08:09:19.64#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.252.08:09:19.64#ibcon#about to clear, iclass 6 cls_cnt 0 2006.252.08:09:19.64#ibcon#cleared, iclass 6 cls_cnt 0 2006.252.08:09:19.64$vc4f8/va=6,7 2006.252.08:09:19.64#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.252.08:09:19.64#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.252.08:09:19.64#ibcon#ireg 11 cls_cnt 2 2006.252.08:09:19.64#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.252.08:09:19.69#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.252.08:09:19.69#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.252.08:09:19.69#ibcon#enter wrdev, iclass 10, count 2 2006.252.08:09:19.69#ibcon#first serial, iclass 10, count 2 2006.252.08:09:19.69#ibcon#enter sib2, iclass 10, count 2 2006.252.08:09:19.69#ibcon#flushed, iclass 10, count 2 2006.252.08:09:19.69#ibcon#about to write, iclass 10, count 2 2006.252.08:09:19.69#ibcon#wrote, iclass 10, count 2 2006.252.08:09:19.69#ibcon#about to read 3, iclass 10, count 2 2006.252.08:09:19.71#ibcon#read 3, iclass 10, count 2 2006.252.08:09:19.71#ibcon#about to read 4, iclass 10, count 2 2006.252.08:09:19.71#ibcon#read 4, iclass 10, count 2 2006.252.08:09:19.71#ibcon#about to read 5, iclass 10, count 2 2006.252.08:09:19.71#ibcon#read 5, iclass 10, count 2 2006.252.08:09:19.71#ibcon#about to read 6, iclass 10, count 2 2006.252.08:09:19.71#ibcon#read 6, iclass 10, count 2 2006.252.08:09:19.71#ibcon#end of sib2, iclass 10, count 2 2006.252.08:09:19.71#ibcon#*mode == 0, iclass 10, count 2 2006.252.08:09:19.71#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.252.08:09:19.71#ibcon#[25=AT06-07\r\n] 2006.252.08:09:19.71#ibcon#*before write, iclass 10, count 2 2006.252.08:09:19.71#ibcon#enter sib2, iclass 10, count 2 2006.252.08:09:19.71#ibcon#flushed, iclass 10, count 2 2006.252.08:09:19.71#ibcon#about to write, iclass 10, count 2 2006.252.08:09:19.71#ibcon#wrote, iclass 10, count 2 2006.252.08:09:19.71#ibcon#about to read 3, iclass 10, count 2 2006.252.08:09:19.74#ibcon#read 3, iclass 10, count 2 2006.252.08:09:19.74#ibcon#about to read 4, iclass 10, count 2 2006.252.08:09:19.74#ibcon#read 4, iclass 10, count 2 2006.252.08:09:19.74#ibcon#about to read 5, iclass 10, count 2 2006.252.08:09:19.74#ibcon#read 5, iclass 10, count 2 2006.252.08:09:19.74#ibcon#about to read 6, iclass 10, count 2 2006.252.08:09:19.74#ibcon#read 6, iclass 10, count 2 2006.252.08:09:19.74#ibcon#end of sib2, iclass 10, count 2 2006.252.08:09:19.74#ibcon#*after write, iclass 10, count 2 2006.252.08:09:19.74#ibcon#*before return 0, iclass 10, count 2 2006.252.08:09:19.74#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.252.08:09:19.74#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.252.08:09:19.74#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.252.08:09:19.74#ibcon#ireg 7 cls_cnt 0 2006.252.08:09:19.74#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.252.08:09:19.86#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.252.08:09:19.86#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.252.08:09:19.86#ibcon#enter wrdev, iclass 10, count 0 2006.252.08:09:19.86#ibcon#first serial, iclass 10, count 0 2006.252.08:09:19.86#ibcon#enter sib2, iclass 10, count 0 2006.252.08:09:19.86#ibcon#flushed, iclass 10, count 0 2006.252.08:09:19.86#ibcon#about to write, iclass 10, count 0 2006.252.08:09:19.86#ibcon#wrote, iclass 10, count 0 2006.252.08:09:19.86#ibcon#about to read 3, iclass 10, count 0 2006.252.08:09:19.88#ibcon#read 3, iclass 10, count 0 2006.252.08:09:19.88#ibcon#about to read 4, iclass 10, count 0 2006.252.08:09:19.88#ibcon#read 4, iclass 10, count 0 2006.252.08:09:19.88#ibcon#about to read 5, iclass 10, count 0 2006.252.08:09:19.88#ibcon#read 5, iclass 10, count 0 2006.252.08:09:19.88#ibcon#about to read 6, iclass 10, count 0 2006.252.08:09:19.88#ibcon#read 6, iclass 10, count 0 2006.252.08:09:19.88#ibcon#end of sib2, iclass 10, count 0 2006.252.08:09:19.88#ibcon#*mode == 0, iclass 10, count 0 2006.252.08:09:19.88#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.252.08:09:19.88#ibcon#[25=USB\r\n] 2006.252.08:09:19.88#ibcon#*before write, iclass 10, count 0 2006.252.08:09:19.88#ibcon#enter sib2, iclass 10, count 0 2006.252.08:09:19.88#ibcon#flushed, iclass 10, count 0 2006.252.08:09:19.88#ibcon#about to write, iclass 10, count 0 2006.252.08:09:19.88#ibcon#wrote, iclass 10, count 0 2006.252.08:09:19.88#ibcon#about to read 3, iclass 10, count 0 2006.252.08:09:19.91#ibcon#read 3, iclass 10, count 0 2006.252.08:09:19.91#ibcon#about to read 4, iclass 10, count 0 2006.252.08:09:19.91#ibcon#read 4, iclass 10, count 0 2006.252.08:09:19.91#ibcon#about to read 5, iclass 10, count 0 2006.252.08:09:19.91#ibcon#read 5, iclass 10, count 0 2006.252.08:09:19.91#ibcon#about to read 6, iclass 10, count 0 2006.252.08:09:19.91#ibcon#read 6, iclass 10, count 0 2006.252.08:09:19.91#ibcon#end of sib2, iclass 10, count 0 2006.252.08:09:19.91#ibcon#*after write, iclass 10, count 0 2006.252.08:09:19.91#ibcon#*before return 0, iclass 10, count 0 2006.252.08:09:19.91#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.252.08:09:19.91#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.252.08:09:19.91#ibcon#about to clear, iclass 10 cls_cnt 0 2006.252.08:09:19.91#ibcon#cleared, iclass 10 cls_cnt 0 2006.252.08:09:19.91$vc4f8/valo=7,832.99 2006.252.08:09:19.91#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.252.08:09:19.91#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.252.08:09:19.91#ibcon#ireg 17 cls_cnt 0 2006.252.08:09:19.91#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.252.08:09:19.91#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.252.08:09:19.91#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.252.08:09:19.91#ibcon#enter wrdev, iclass 12, count 0 2006.252.08:09:19.91#ibcon#first serial, iclass 12, count 0 2006.252.08:09:19.91#ibcon#enter sib2, iclass 12, count 0 2006.252.08:09:19.91#ibcon#flushed, iclass 12, count 0 2006.252.08:09:19.91#ibcon#about to write, iclass 12, count 0 2006.252.08:09:19.91#ibcon#wrote, iclass 12, count 0 2006.252.08:09:19.91#ibcon#about to read 3, iclass 12, count 0 2006.252.08:09:19.93#ibcon#read 3, iclass 12, count 0 2006.252.08:09:19.93#ibcon#about to read 4, iclass 12, count 0 2006.252.08:09:19.93#ibcon#read 4, iclass 12, count 0 2006.252.08:09:19.93#ibcon#about to read 5, iclass 12, count 0 2006.252.08:09:19.93#ibcon#read 5, iclass 12, count 0 2006.252.08:09:19.93#ibcon#about to read 6, iclass 12, count 0 2006.252.08:09:19.93#ibcon#read 6, iclass 12, count 0 2006.252.08:09:19.93#ibcon#end of sib2, iclass 12, count 0 2006.252.08:09:19.93#ibcon#*mode == 0, iclass 12, count 0 2006.252.08:09:19.93#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.252.08:09:19.93#ibcon#[26=FRQ=07,832.99\r\n] 2006.252.08:09:19.93#ibcon#*before write, iclass 12, count 0 2006.252.08:09:19.93#ibcon#enter sib2, iclass 12, count 0 2006.252.08:09:19.93#ibcon#flushed, iclass 12, count 0 2006.252.08:09:19.93#ibcon#about to write, iclass 12, count 0 2006.252.08:09:19.93#ibcon#wrote, iclass 12, count 0 2006.252.08:09:19.93#ibcon#about to read 3, iclass 12, count 0 2006.252.08:09:19.97#ibcon#read 3, iclass 12, count 0 2006.252.08:09:19.97#ibcon#about to read 4, iclass 12, count 0 2006.252.08:09:19.97#ibcon#read 4, iclass 12, count 0 2006.252.08:09:19.97#ibcon#about to read 5, iclass 12, count 0 2006.252.08:09:19.97#ibcon#read 5, iclass 12, count 0 2006.252.08:09:19.97#ibcon#about to read 6, iclass 12, count 0 2006.252.08:09:19.97#ibcon#read 6, iclass 12, count 0 2006.252.08:09:19.97#ibcon#end of sib2, iclass 12, count 0 2006.252.08:09:19.97#ibcon#*after write, iclass 12, count 0 2006.252.08:09:19.97#ibcon#*before return 0, iclass 12, count 0 2006.252.08:09:19.97#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.252.08:09:19.97#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.252.08:09:19.97#ibcon#about to clear, iclass 12 cls_cnt 0 2006.252.08:09:19.97#ibcon#cleared, iclass 12 cls_cnt 0 2006.252.08:09:19.97$vc4f8/va=7,7 2006.252.08:09:19.97#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.252.08:09:19.97#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.252.08:09:19.97#ibcon#ireg 11 cls_cnt 2 2006.252.08:09:19.97#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.252.08:09:20.03#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.252.08:09:20.03#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.252.08:09:20.03#ibcon#enter wrdev, iclass 14, count 2 2006.252.08:09:20.03#ibcon#first serial, iclass 14, count 2 2006.252.08:09:20.03#ibcon#enter sib2, iclass 14, count 2 2006.252.08:09:20.03#ibcon#flushed, iclass 14, count 2 2006.252.08:09:20.03#ibcon#about to write, iclass 14, count 2 2006.252.08:09:20.03#ibcon#wrote, iclass 14, count 2 2006.252.08:09:20.03#ibcon#about to read 3, iclass 14, count 2 2006.252.08:09:20.05#ibcon#read 3, iclass 14, count 2 2006.252.08:09:20.05#ibcon#about to read 4, iclass 14, count 2 2006.252.08:09:20.05#ibcon#read 4, iclass 14, count 2 2006.252.08:09:20.05#ibcon#about to read 5, iclass 14, count 2 2006.252.08:09:20.05#ibcon#read 5, iclass 14, count 2 2006.252.08:09:20.05#ibcon#about to read 6, iclass 14, count 2 2006.252.08:09:20.05#ibcon#read 6, iclass 14, count 2 2006.252.08:09:20.05#ibcon#end of sib2, iclass 14, count 2 2006.252.08:09:20.05#ibcon#*mode == 0, iclass 14, count 2 2006.252.08:09:20.05#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.252.08:09:20.05#ibcon#[25=AT07-07\r\n] 2006.252.08:09:20.05#ibcon#*before write, iclass 14, count 2 2006.252.08:09:20.05#ibcon#enter sib2, iclass 14, count 2 2006.252.08:09:20.05#ibcon#flushed, iclass 14, count 2 2006.252.08:09:20.05#ibcon#about to write, iclass 14, count 2 2006.252.08:09:20.05#ibcon#wrote, iclass 14, count 2 2006.252.08:09:20.05#ibcon#about to read 3, iclass 14, count 2 2006.252.08:09:20.08#ibcon#read 3, iclass 14, count 2 2006.252.08:09:20.08#ibcon#about to read 4, iclass 14, count 2 2006.252.08:09:20.08#ibcon#read 4, iclass 14, count 2 2006.252.08:09:20.08#ibcon#about to read 5, iclass 14, count 2 2006.252.08:09:20.08#ibcon#read 5, iclass 14, count 2 2006.252.08:09:20.08#ibcon#about to read 6, iclass 14, count 2 2006.252.08:09:20.08#ibcon#read 6, iclass 14, count 2 2006.252.08:09:20.08#ibcon#end of sib2, iclass 14, count 2 2006.252.08:09:20.08#ibcon#*after write, iclass 14, count 2 2006.252.08:09:20.08#ibcon#*before return 0, iclass 14, count 2 2006.252.08:09:20.08#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.252.08:09:20.08#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.252.08:09:20.08#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.252.08:09:20.08#ibcon#ireg 7 cls_cnt 0 2006.252.08:09:20.08#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.252.08:09:20.20#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.252.08:09:20.20#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.252.08:09:20.20#ibcon#enter wrdev, iclass 14, count 0 2006.252.08:09:20.20#ibcon#first serial, iclass 14, count 0 2006.252.08:09:20.20#ibcon#enter sib2, iclass 14, count 0 2006.252.08:09:20.20#ibcon#flushed, iclass 14, count 0 2006.252.08:09:20.20#ibcon#about to write, iclass 14, count 0 2006.252.08:09:20.20#ibcon#wrote, iclass 14, count 0 2006.252.08:09:20.20#ibcon#about to read 3, iclass 14, count 0 2006.252.08:09:20.23#ibcon#read 3, iclass 14, count 0 2006.252.08:09:20.23#ibcon#about to read 4, iclass 14, count 0 2006.252.08:09:20.23#ibcon#read 4, iclass 14, count 0 2006.252.08:09:20.23#ibcon#about to read 5, iclass 14, count 0 2006.252.08:09:20.23#ibcon#read 5, iclass 14, count 0 2006.252.08:09:20.23#ibcon#about to read 6, iclass 14, count 0 2006.252.08:09:20.23#ibcon#read 6, iclass 14, count 0 2006.252.08:09:20.23#ibcon#end of sib2, iclass 14, count 0 2006.252.08:09:20.23#ibcon#*mode == 0, iclass 14, count 0 2006.252.08:09:20.23#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.252.08:09:20.23#ibcon#[25=USB\r\n] 2006.252.08:09:20.23#ibcon#*before write, iclass 14, count 0 2006.252.08:09:20.23#ibcon#enter sib2, iclass 14, count 0 2006.252.08:09:20.23#ibcon#flushed, iclass 14, count 0 2006.252.08:09:20.23#ibcon#about to write, iclass 14, count 0 2006.252.08:09:20.23#ibcon#wrote, iclass 14, count 0 2006.252.08:09:20.23#ibcon#about to read 3, iclass 14, count 0 2006.252.08:09:20.26#ibcon#read 3, iclass 14, count 0 2006.252.08:09:20.26#ibcon#about to read 4, iclass 14, count 0 2006.252.08:09:20.26#ibcon#read 4, iclass 14, count 0 2006.252.08:09:20.26#ibcon#about to read 5, iclass 14, count 0 2006.252.08:09:20.26#ibcon#read 5, iclass 14, count 0 2006.252.08:09:20.26#ibcon#about to read 6, iclass 14, count 0 2006.252.08:09:20.26#ibcon#read 6, iclass 14, count 0 2006.252.08:09:20.26#ibcon#end of sib2, iclass 14, count 0 2006.252.08:09:20.26#ibcon#*after write, iclass 14, count 0 2006.252.08:09:20.26#ibcon#*before return 0, iclass 14, count 0 2006.252.08:09:20.26#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.252.08:09:20.26#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.252.08:09:20.26#ibcon#about to clear, iclass 14 cls_cnt 0 2006.252.08:09:20.26#ibcon#cleared, iclass 14 cls_cnt 0 2006.252.08:09:20.26$vc4f8/valo=8,852.99 2006.252.08:09:20.26#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.252.08:09:20.26#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.252.08:09:20.26#ibcon#ireg 17 cls_cnt 0 2006.252.08:09:20.26#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.252.08:09:20.26#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.252.08:09:20.26#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.252.08:09:20.26#ibcon#enter wrdev, iclass 16, count 0 2006.252.08:09:20.26#ibcon#first serial, iclass 16, count 0 2006.252.08:09:20.26#ibcon#enter sib2, iclass 16, count 0 2006.252.08:09:20.26#ibcon#flushed, iclass 16, count 0 2006.252.08:09:20.26#ibcon#about to write, iclass 16, count 0 2006.252.08:09:20.26#ibcon#wrote, iclass 16, count 0 2006.252.08:09:20.26#ibcon#about to read 3, iclass 16, count 0 2006.252.08:09:20.28#ibcon#read 3, iclass 16, count 0 2006.252.08:09:20.28#ibcon#about to read 4, iclass 16, count 0 2006.252.08:09:20.28#ibcon#read 4, iclass 16, count 0 2006.252.08:09:20.28#ibcon#about to read 5, iclass 16, count 0 2006.252.08:09:20.28#ibcon#read 5, iclass 16, count 0 2006.252.08:09:20.28#ibcon#about to read 6, iclass 16, count 0 2006.252.08:09:20.28#ibcon#read 6, iclass 16, count 0 2006.252.08:09:20.28#ibcon#end of sib2, iclass 16, count 0 2006.252.08:09:20.28#ibcon#*mode == 0, iclass 16, count 0 2006.252.08:09:20.28#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.252.08:09:20.28#ibcon#[26=FRQ=08,852.99\r\n] 2006.252.08:09:20.28#ibcon#*before write, iclass 16, count 0 2006.252.08:09:20.28#ibcon#enter sib2, iclass 16, count 0 2006.252.08:09:20.28#ibcon#flushed, iclass 16, count 0 2006.252.08:09:20.28#ibcon#about to write, iclass 16, count 0 2006.252.08:09:20.28#ibcon#wrote, iclass 16, count 0 2006.252.08:09:20.28#ibcon#about to read 3, iclass 16, count 0 2006.252.08:09:20.32#ibcon#read 3, iclass 16, count 0 2006.252.08:09:20.32#ibcon#about to read 4, iclass 16, count 0 2006.252.08:09:20.32#ibcon#read 4, iclass 16, count 0 2006.252.08:09:20.32#ibcon#about to read 5, iclass 16, count 0 2006.252.08:09:20.32#ibcon#read 5, iclass 16, count 0 2006.252.08:09:20.32#ibcon#about to read 6, iclass 16, count 0 2006.252.08:09:20.32#ibcon#read 6, iclass 16, count 0 2006.252.08:09:20.32#ibcon#end of sib2, iclass 16, count 0 2006.252.08:09:20.32#ibcon#*after write, iclass 16, count 0 2006.252.08:09:20.32#ibcon#*before return 0, iclass 16, count 0 2006.252.08:09:20.32#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.252.08:09:20.32#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.252.08:09:20.32#ibcon#about to clear, iclass 16 cls_cnt 0 2006.252.08:09:20.32#ibcon#cleared, iclass 16 cls_cnt 0 2006.252.08:09:20.32$vc4f8/va=8,7 2006.252.08:09:20.32#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.252.08:09:20.32#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.252.08:09:20.32#ibcon#ireg 11 cls_cnt 2 2006.252.08:09:20.32#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.252.08:09:20.38#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.252.08:09:20.38#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.252.08:09:20.38#ibcon#enter wrdev, iclass 18, count 2 2006.252.08:09:20.38#ibcon#first serial, iclass 18, count 2 2006.252.08:09:20.38#ibcon#enter sib2, iclass 18, count 2 2006.252.08:09:20.38#ibcon#flushed, iclass 18, count 2 2006.252.08:09:20.38#ibcon#about to write, iclass 18, count 2 2006.252.08:09:20.38#ibcon#wrote, iclass 18, count 2 2006.252.08:09:20.38#ibcon#about to read 3, iclass 18, count 2 2006.252.08:09:20.40#ibcon#read 3, iclass 18, count 2 2006.252.08:09:20.40#ibcon#about to read 4, iclass 18, count 2 2006.252.08:09:20.40#ibcon#read 4, iclass 18, count 2 2006.252.08:09:20.40#ibcon#about to read 5, iclass 18, count 2 2006.252.08:09:20.40#ibcon#read 5, iclass 18, count 2 2006.252.08:09:20.40#ibcon#about to read 6, iclass 18, count 2 2006.252.08:09:20.40#ibcon#read 6, iclass 18, count 2 2006.252.08:09:20.40#ibcon#end of sib2, iclass 18, count 2 2006.252.08:09:20.40#ibcon#*mode == 0, iclass 18, count 2 2006.252.08:09:20.40#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.252.08:09:20.40#ibcon#[25=AT08-07\r\n] 2006.252.08:09:20.40#ibcon#*before write, iclass 18, count 2 2006.252.08:09:20.40#ibcon#enter sib2, iclass 18, count 2 2006.252.08:09:20.40#ibcon#flushed, iclass 18, count 2 2006.252.08:09:20.40#ibcon#about to write, iclass 18, count 2 2006.252.08:09:20.40#ibcon#wrote, iclass 18, count 2 2006.252.08:09:20.40#ibcon#about to read 3, iclass 18, count 2 2006.252.08:09:20.43#ibcon#read 3, iclass 18, count 2 2006.252.08:09:20.43#ibcon#about to read 4, iclass 18, count 2 2006.252.08:09:20.43#ibcon#read 4, iclass 18, count 2 2006.252.08:09:20.43#ibcon#about to read 5, iclass 18, count 2 2006.252.08:09:20.43#ibcon#read 5, iclass 18, count 2 2006.252.08:09:20.43#ibcon#about to read 6, iclass 18, count 2 2006.252.08:09:20.43#ibcon#read 6, iclass 18, count 2 2006.252.08:09:20.43#ibcon#end of sib2, iclass 18, count 2 2006.252.08:09:20.43#ibcon#*after write, iclass 18, count 2 2006.252.08:09:20.43#ibcon#*before return 0, iclass 18, count 2 2006.252.08:09:20.43#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.252.08:09:20.43#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.252.08:09:20.43#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.252.08:09:20.43#ibcon#ireg 7 cls_cnt 0 2006.252.08:09:20.43#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.252.08:09:20.55#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.252.08:09:20.55#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.252.08:09:20.55#ibcon#enter wrdev, iclass 18, count 0 2006.252.08:09:20.55#ibcon#first serial, iclass 18, count 0 2006.252.08:09:20.55#ibcon#enter sib2, iclass 18, count 0 2006.252.08:09:20.55#ibcon#flushed, iclass 18, count 0 2006.252.08:09:20.55#ibcon#about to write, iclass 18, count 0 2006.252.08:09:20.55#ibcon#wrote, iclass 18, count 0 2006.252.08:09:20.55#ibcon#about to read 3, iclass 18, count 0 2006.252.08:09:20.57#ibcon#read 3, iclass 18, count 0 2006.252.08:09:20.57#ibcon#about to read 4, iclass 18, count 0 2006.252.08:09:20.57#ibcon#read 4, iclass 18, count 0 2006.252.08:09:20.57#ibcon#about to read 5, iclass 18, count 0 2006.252.08:09:20.57#ibcon#read 5, iclass 18, count 0 2006.252.08:09:20.57#ibcon#about to read 6, iclass 18, count 0 2006.252.08:09:20.57#ibcon#read 6, iclass 18, count 0 2006.252.08:09:20.57#ibcon#end of sib2, iclass 18, count 0 2006.252.08:09:20.57#ibcon#*mode == 0, iclass 18, count 0 2006.252.08:09:20.57#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.252.08:09:20.57#ibcon#[25=USB\r\n] 2006.252.08:09:20.57#ibcon#*before write, iclass 18, count 0 2006.252.08:09:20.57#ibcon#enter sib2, iclass 18, count 0 2006.252.08:09:20.57#ibcon#flushed, iclass 18, count 0 2006.252.08:09:20.57#ibcon#about to write, iclass 18, count 0 2006.252.08:09:20.57#ibcon#wrote, iclass 18, count 0 2006.252.08:09:20.57#ibcon#about to read 3, iclass 18, count 0 2006.252.08:09:20.60#ibcon#read 3, iclass 18, count 0 2006.252.08:09:20.60#ibcon#about to read 4, iclass 18, count 0 2006.252.08:09:20.60#ibcon#read 4, iclass 18, count 0 2006.252.08:09:20.60#ibcon#about to read 5, iclass 18, count 0 2006.252.08:09:20.60#ibcon#read 5, iclass 18, count 0 2006.252.08:09:20.60#ibcon#about to read 6, iclass 18, count 0 2006.252.08:09:20.60#ibcon#read 6, iclass 18, count 0 2006.252.08:09:20.60#ibcon#end of sib2, iclass 18, count 0 2006.252.08:09:20.60#ibcon#*after write, iclass 18, count 0 2006.252.08:09:20.60#ibcon#*before return 0, iclass 18, count 0 2006.252.08:09:20.60#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.252.08:09:20.60#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.252.08:09:20.60#ibcon#about to clear, iclass 18 cls_cnt 0 2006.252.08:09:20.60#ibcon#cleared, iclass 18 cls_cnt 0 2006.252.08:09:20.60$vc4f8/vblo=1,632.99 2006.252.08:09:20.60#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.252.08:09:20.60#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.252.08:09:20.60#ibcon#ireg 17 cls_cnt 0 2006.252.08:09:20.60#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.252.08:09:20.60#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.252.08:09:20.60#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.252.08:09:20.60#ibcon#enter wrdev, iclass 20, count 0 2006.252.08:09:20.60#ibcon#first serial, iclass 20, count 0 2006.252.08:09:20.60#ibcon#enter sib2, iclass 20, count 0 2006.252.08:09:20.60#ibcon#flushed, iclass 20, count 0 2006.252.08:09:20.60#ibcon#about to write, iclass 20, count 0 2006.252.08:09:20.60#ibcon#wrote, iclass 20, count 0 2006.252.08:09:20.60#ibcon#about to read 3, iclass 20, count 0 2006.252.08:09:20.62#ibcon#read 3, iclass 20, count 0 2006.252.08:09:20.62#ibcon#about to read 4, iclass 20, count 0 2006.252.08:09:20.62#ibcon#read 4, iclass 20, count 0 2006.252.08:09:20.62#ibcon#about to read 5, iclass 20, count 0 2006.252.08:09:20.62#ibcon#read 5, iclass 20, count 0 2006.252.08:09:20.62#ibcon#about to read 6, iclass 20, count 0 2006.252.08:09:20.62#ibcon#read 6, iclass 20, count 0 2006.252.08:09:20.62#ibcon#end of sib2, iclass 20, count 0 2006.252.08:09:20.62#ibcon#*mode == 0, iclass 20, count 0 2006.252.08:09:20.62#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.252.08:09:20.62#ibcon#[28=FRQ=01,632.99\r\n] 2006.252.08:09:20.62#ibcon#*before write, iclass 20, count 0 2006.252.08:09:20.62#ibcon#enter sib2, iclass 20, count 0 2006.252.08:09:20.62#ibcon#flushed, iclass 20, count 0 2006.252.08:09:20.62#ibcon#about to write, iclass 20, count 0 2006.252.08:09:20.62#ibcon#wrote, iclass 20, count 0 2006.252.08:09:20.62#ibcon#about to read 3, iclass 20, count 0 2006.252.08:09:20.66#ibcon#read 3, iclass 20, count 0 2006.252.08:09:20.66#ibcon#about to read 4, iclass 20, count 0 2006.252.08:09:20.66#ibcon#read 4, iclass 20, count 0 2006.252.08:09:20.66#ibcon#about to read 5, iclass 20, count 0 2006.252.08:09:20.66#ibcon#read 5, iclass 20, count 0 2006.252.08:09:20.66#ibcon#about to read 6, iclass 20, count 0 2006.252.08:09:20.66#ibcon#read 6, iclass 20, count 0 2006.252.08:09:20.66#ibcon#end of sib2, iclass 20, count 0 2006.252.08:09:20.66#ibcon#*after write, iclass 20, count 0 2006.252.08:09:20.66#ibcon#*before return 0, iclass 20, count 0 2006.252.08:09:20.66#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.252.08:09:20.66#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.252.08:09:20.66#ibcon#about to clear, iclass 20 cls_cnt 0 2006.252.08:09:20.66#ibcon#cleared, iclass 20 cls_cnt 0 2006.252.08:09:20.66$vc4f8/vb=1,4 2006.252.08:09:20.66#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.252.08:09:20.66#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.252.08:09:20.66#ibcon#ireg 11 cls_cnt 2 2006.252.08:09:20.66#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.252.08:09:20.66#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.252.08:09:20.66#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.252.08:09:20.66#ibcon#enter wrdev, iclass 22, count 2 2006.252.08:09:20.66#ibcon#first serial, iclass 22, count 2 2006.252.08:09:20.66#ibcon#enter sib2, iclass 22, count 2 2006.252.08:09:20.66#ibcon#flushed, iclass 22, count 2 2006.252.08:09:20.66#ibcon#about to write, iclass 22, count 2 2006.252.08:09:20.66#ibcon#wrote, iclass 22, count 2 2006.252.08:09:20.66#ibcon#about to read 3, iclass 22, count 2 2006.252.08:09:20.68#ibcon#read 3, iclass 22, count 2 2006.252.08:09:20.68#ibcon#about to read 4, iclass 22, count 2 2006.252.08:09:20.68#ibcon#read 4, iclass 22, count 2 2006.252.08:09:20.68#ibcon#about to read 5, iclass 22, count 2 2006.252.08:09:20.68#ibcon#read 5, iclass 22, count 2 2006.252.08:09:20.68#ibcon#about to read 6, iclass 22, count 2 2006.252.08:09:20.68#ibcon#read 6, iclass 22, count 2 2006.252.08:09:20.68#ibcon#end of sib2, iclass 22, count 2 2006.252.08:09:20.68#ibcon#*mode == 0, iclass 22, count 2 2006.252.08:09:20.68#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.252.08:09:20.68#ibcon#[27=AT01-04\r\n] 2006.252.08:09:20.68#ibcon#*before write, iclass 22, count 2 2006.252.08:09:20.68#ibcon#enter sib2, iclass 22, count 2 2006.252.08:09:20.68#ibcon#flushed, iclass 22, count 2 2006.252.08:09:20.68#ibcon#about to write, iclass 22, count 2 2006.252.08:09:20.68#ibcon#wrote, iclass 22, count 2 2006.252.08:09:20.68#ibcon#about to read 3, iclass 22, count 2 2006.252.08:09:20.71#ibcon#read 3, iclass 22, count 2 2006.252.08:09:20.71#ibcon#about to read 4, iclass 22, count 2 2006.252.08:09:20.71#ibcon#read 4, iclass 22, count 2 2006.252.08:09:20.71#ibcon#about to read 5, iclass 22, count 2 2006.252.08:09:20.71#ibcon#read 5, iclass 22, count 2 2006.252.08:09:20.71#ibcon#about to read 6, iclass 22, count 2 2006.252.08:09:20.71#ibcon#read 6, iclass 22, count 2 2006.252.08:09:20.71#ibcon#end of sib2, iclass 22, count 2 2006.252.08:09:20.71#ibcon#*after write, iclass 22, count 2 2006.252.08:09:20.71#ibcon#*before return 0, iclass 22, count 2 2006.252.08:09:20.71#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.252.08:09:20.71#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.252.08:09:20.71#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.252.08:09:20.71#ibcon#ireg 7 cls_cnt 0 2006.252.08:09:20.71#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.252.08:09:20.83#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.252.08:09:20.83#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.252.08:09:20.83#ibcon#enter wrdev, iclass 22, count 0 2006.252.08:09:20.83#ibcon#first serial, iclass 22, count 0 2006.252.08:09:20.83#ibcon#enter sib2, iclass 22, count 0 2006.252.08:09:20.83#ibcon#flushed, iclass 22, count 0 2006.252.08:09:20.83#ibcon#about to write, iclass 22, count 0 2006.252.08:09:20.83#ibcon#wrote, iclass 22, count 0 2006.252.08:09:20.83#ibcon#about to read 3, iclass 22, count 0 2006.252.08:09:20.85#ibcon#read 3, iclass 22, count 0 2006.252.08:09:20.85#ibcon#about to read 4, iclass 22, count 0 2006.252.08:09:20.85#ibcon#read 4, iclass 22, count 0 2006.252.08:09:20.85#ibcon#about to read 5, iclass 22, count 0 2006.252.08:09:20.85#ibcon#read 5, iclass 22, count 0 2006.252.08:09:20.85#ibcon#about to read 6, iclass 22, count 0 2006.252.08:09:20.85#ibcon#read 6, iclass 22, count 0 2006.252.08:09:20.85#ibcon#end of sib2, iclass 22, count 0 2006.252.08:09:20.85#ibcon#*mode == 0, iclass 22, count 0 2006.252.08:09:20.85#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.252.08:09:20.85#ibcon#[27=USB\r\n] 2006.252.08:09:20.85#ibcon#*before write, iclass 22, count 0 2006.252.08:09:20.85#ibcon#enter sib2, iclass 22, count 0 2006.252.08:09:20.85#ibcon#flushed, iclass 22, count 0 2006.252.08:09:20.85#ibcon#about to write, iclass 22, count 0 2006.252.08:09:20.85#ibcon#wrote, iclass 22, count 0 2006.252.08:09:20.85#ibcon#about to read 3, iclass 22, count 0 2006.252.08:09:20.88#ibcon#read 3, iclass 22, count 0 2006.252.08:09:20.88#ibcon#about to read 4, iclass 22, count 0 2006.252.08:09:20.88#ibcon#read 4, iclass 22, count 0 2006.252.08:09:20.88#ibcon#about to read 5, iclass 22, count 0 2006.252.08:09:20.88#ibcon#read 5, iclass 22, count 0 2006.252.08:09:20.88#ibcon#about to read 6, iclass 22, count 0 2006.252.08:09:20.88#ibcon#read 6, iclass 22, count 0 2006.252.08:09:20.88#ibcon#end of sib2, iclass 22, count 0 2006.252.08:09:20.88#ibcon#*after write, iclass 22, count 0 2006.252.08:09:20.88#ibcon#*before return 0, iclass 22, count 0 2006.252.08:09:20.88#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.252.08:09:20.88#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.252.08:09:20.88#ibcon#about to clear, iclass 22 cls_cnt 0 2006.252.08:09:20.88#ibcon#cleared, iclass 22 cls_cnt 0 2006.252.08:09:20.88$vc4f8/vblo=2,640.99 2006.252.08:09:20.88#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.252.08:09:20.88#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.252.08:09:20.88#ibcon#ireg 17 cls_cnt 0 2006.252.08:09:20.88#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.252.08:09:20.88#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.252.08:09:20.88#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.252.08:09:20.88#ibcon#enter wrdev, iclass 24, count 0 2006.252.08:09:20.88#ibcon#first serial, iclass 24, count 0 2006.252.08:09:20.88#ibcon#enter sib2, iclass 24, count 0 2006.252.08:09:20.88#ibcon#flushed, iclass 24, count 0 2006.252.08:09:20.88#ibcon#about to write, iclass 24, count 0 2006.252.08:09:20.88#ibcon#wrote, iclass 24, count 0 2006.252.08:09:20.88#ibcon#about to read 3, iclass 24, count 0 2006.252.08:09:20.90#ibcon#read 3, iclass 24, count 0 2006.252.08:09:20.90#ibcon#about to read 4, iclass 24, count 0 2006.252.08:09:20.90#ibcon#read 4, iclass 24, count 0 2006.252.08:09:20.90#ibcon#about to read 5, iclass 24, count 0 2006.252.08:09:20.90#ibcon#read 5, iclass 24, count 0 2006.252.08:09:20.90#ibcon#about to read 6, iclass 24, count 0 2006.252.08:09:20.90#ibcon#read 6, iclass 24, count 0 2006.252.08:09:20.90#ibcon#end of sib2, iclass 24, count 0 2006.252.08:09:20.90#ibcon#*mode == 0, iclass 24, count 0 2006.252.08:09:20.90#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.252.08:09:20.90#ibcon#[28=FRQ=02,640.99\r\n] 2006.252.08:09:20.90#ibcon#*before write, iclass 24, count 0 2006.252.08:09:20.90#ibcon#enter sib2, iclass 24, count 0 2006.252.08:09:20.90#ibcon#flushed, iclass 24, count 0 2006.252.08:09:20.90#ibcon#about to write, iclass 24, count 0 2006.252.08:09:20.90#ibcon#wrote, iclass 24, count 0 2006.252.08:09:20.90#ibcon#about to read 3, iclass 24, count 0 2006.252.08:09:20.94#ibcon#read 3, iclass 24, count 0 2006.252.08:09:20.94#ibcon#about to read 4, iclass 24, count 0 2006.252.08:09:20.94#ibcon#read 4, iclass 24, count 0 2006.252.08:09:20.94#ibcon#about to read 5, iclass 24, count 0 2006.252.08:09:20.94#ibcon#read 5, iclass 24, count 0 2006.252.08:09:20.94#ibcon#about to read 6, iclass 24, count 0 2006.252.08:09:20.94#ibcon#read 6, iclass 24, count 0 2006.252.08:09:20.94#ibcon#end of sib2, iclass 24, count 0 2006.252.08:09:20.94#ibcon#*after write, iclass 24, count 0 2006.252.08:09:20.94#ibcon#*before return 0, iclass 24, count 0 2006.252.08:09:20.94#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.252.08:09:20.94#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.252.08:09:20.94#ibcon#about to clear, iclass 24 cls_cnt 0 2006.252.08:09:20.94#ibcon#cleared, iclass 24 cls_cnt 0 2006.252.08:09:20.94$vc4f8/vb=2,5 2006.252.08:09:20.94#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.252.08:09:20.94#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.252.08:09:20.94#ibcon#ireg 11 cls_cnt 2 2006.252.08:09:20.94#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.252.08:09:21.00#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.252.08:09:21.00#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.252.08:09:21.00#ibcon#enter wrdev, iclass 26, count 2 2006.252.08:09:21.00#ibcon#first serial, iclass 26, count 2 2006.252.08:09:21.00#ibcon#enter sib2, iclass 26, count 2 2006.252.08:09:21.00#ibcon#flushed, iclass 26, count 2 2006.252.08:09:21.00#ibcon#about to write, iclass 26, count 2 2006.252.08:09:21.00#ibcon#wrote, iclass 26, count 2 2006.252.08:09:21.00#ibcon#about to read 3, iclass 26, count 2 2006.252.08:09:21.02#ibcon#read 3, iclass 26, count 2 2006.252.08:09:21.02#ibcon#about to read 4, iclass 26, count 2 2006.252.08:09:21.02#ibcon#read 4, iclass 26, count 2 2006.252.08:09:21.02#ibcon#about to read 5, iclass 26, count 2 2006.252.08:09:21.02#ibcon#read 5, iclass 26, count 2 2006.252.08:09:21.02#ibcon#about to read 6, iclass 26, count 2 2006.252.08:09:21.02#ibcon#read 6, iclass 26, count 2 2006.252.08:09:21.02#ibcon#end of sib2, iclass 26, count 2 2006.252.08:09:21.02#ibcon#*mode == 0, iclass 26, count 2 2006.252.08:09:21.02#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.252.08:09:21.02#ibcon#[27=AT02-05\r\n] 2006.252.08:09:21.02#ibcon#*before write, iclass 26, count 2 2006.252.08:09:21.02#ibcon#enter sib2, iclass 26, count 2 2006.252.08:09:21.02#ibcon#flushed, iclass 26, count 2 2006.252.08:09:21.02#ibcon#about to write, iclass 26, count 2 2006.252.08:09:21.02#ibcon#wrote, iclass 26, count 2 2006.252.08:09:21.02#ibcon#about to read 3, iclass 26, count 2 2006.252.08:09:21.05#ibcon#read 3, iclass 26, count 2 2006.252.08:09:21.05#ibcon#about to read 4, iclass 26, count 2 2006.252.08:09:21.05#ibcon#read 4, iclass 26, count 2 2006.252.08:09:21.05#ibcon#about to read 5, iclass 26, count 2 2006.252.08:09:21.05#ibcon#read 5, iclass 26, count 2 2006.252.08:09:21.05#ibcon#about to read 6, iclass 26, count 2 2006.252.08:09:21.05#ibcon#read 6, iclass 26, count 2 2006.252.08:09:21.05#ibcon#end of sib2, iclass 26, count 2 2006.252.08:09:21.05#ibcon#*after write, iclass 26, count 2 2006.252.08:09:21.05#ibcon#*before return 0, iclass 26, count 2 2006.252.08:09:21.05#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.252.08:09:21.05#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.252.08:09:21.05#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.252.08:09:21.05#ibcon#ireg 7 cls_cnt 0 2006.252.08:09:21.05#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.252.08:09:21.17#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.252.08:09:21.17#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.252.08:09:21.17#ibcon#enter wrdev, iclass 26, count 0 2006.252.08:09:21.17#ibcon#first serial, iclass 26, count 0 2006.252.08:09:21.17#ibcon#enter sib2, iclass 26, count 0 2006.252.08:09:21.17#ibcon#flushed, iclass 26, count 0 2006.252.08:09:21.17#ibcon#about to write, iclass 26, count 0 2006.252.08:09:21.17#ibcon#wrote, iclass 26, count 0 2006.252.08:09:21.17#ibcon#about to read 3, iclass 26, count 0 2006.252.08:09:21.19#ibcon#read 3, iclass 26, count 0 2006.252.08:09:21.19#ibcon#about to read 4, iclass 26, count 0 2006.252.08:09:21.19#ibcon#read 4, iclass 26, count 0 2006.252.08:09:21.19#ibcon#about to read 5, iclass 26, count 0 2006.252.08:09:21.19#ibcon#read 5, iclass 26, count 0 2006.252.08:09:21.19#ibcon#about to read 6, iclass 26, count 0 2006.252.08:09:21.19#ibcon#read 6, iclass 26, count 0 2006.252.08:09:21.19#ibcon#end of sib2, iclass 26, count 0 2006.252.08:09:21.19#ibcon#*mode == 0, iclass 26, count 0 2006.252.08:09:21.19#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.252.08:09:21.19#ibcon#[27=USB\r\n] 2006.252.08:09:21.19#ibcon#*before write, iclass 26, count 0 2006.252.08:09:21.19#ibcon#enter sib2, iclass 26, count 0 2006.252.08:09:21.19#ibcon#flushed, iclass 26, count 0 2006.252.08:09:21.19#ibcon#about to write, iclass 26, count 0 2006.252.08:09:21.19#ibcon#wrote, iclass 26, count 0 2006.252.08:09:21.19#ibcon#about to read 3, iclass 26, count 0 2006.252.08:09:21.22#ibcon#read 3, iclass 26, count 0 2006.252.08:09:21.22#ibcon#about to read 4, iclass 26, count 0 2006.252.08:09:21.22#ibcon#read 4, iclass 26, count 0 2006.252.08:09:21.22#ibcon#about to read 5, iclass 26, count 0 2006.252.08:09:21.22#ibcon#read 5, iclass 26, count 0 2006.252.08:09:21.22#ibcon#about to read 6, iclass 26, count 0 2006.252.08:09:21.22#ibcon#read 6, iclass 26, count 0 2006.252.08:09:21.22#ibcon#end of sib2, iclass 26, count 0 2006.252.08:09:21.22#ibcon#*after write, iclass 26, count 0 2006.252.08:09:21.22#ibcon#*before return 0, iclass 26, count 0 2006.252.08:09:21.22#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.252.08:09:21.22#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.252.08:09:21.22#ibcon#about to clear, iclass 26 cls_cnt 0 2006.252.08:09:21.22#ibcon#cleared, iclass 26 cls_cnt 0 2006.252.08:09:21.22$vc4f8/vblo=3,656.99 2006.252.08:09:21.22#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.252.08:09:21.22#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.252.08:09:21.22#ibcon#ireg 17 cls_cnt 0 2006.252.08:09:21.22#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.252.08:09:21.22#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.252.08:09:21.22#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.252.08:09:21.22#ibcon#enter wrdev, iclass 28, count 0 2006.252.08:09:21.22#ibcon#first serial, iclass 28, count 0 2006.252.08:09:21.22#ibcon#enter sib2, iclass 28, count 0 2006.252.08:09:21.22#ibcon#flushed, iclass 28, count 0 2006.252.08:09:21.22#ibcon#about to write, iclass 28, count 0 2006.252.08:09:21.22#ibcon#wrote, iclass 28, count 0 2006.252.08:09:21.22#ibcon#about to read 3, iclass 28, count 0 2006.252.08:09:21.24#ibcon#read 3, iclass 28, count 0 2006.252.08:09:21.24#ibcon#about to read 4, iclass 28, count 0 2006.252.08:09:21.24#ibcon#read 4, iclass 28, count 0 2006.252.08:09:21.24#ibcon#about to read 5, iclass 28, count 0 2006.252.08:09:21.24#ibcon#read 5, iclass 28, count 0 2006.252.08:09:21.24#ibcon#about to read 6, iclass 28, count 0 2006.252.08:09:21.24#ibcon#read 6, iclass 28, count 0 2006.252.08:09:21.24#ibcon#end of sib2, iclass 28, count 0 2006.252.08:09:21.24#ibcon#*mode == 0, iclass 28, count 0 2006.252.08:09:21.24#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.252.08:09:21.24#ibcon#[28=FRQ=03,656.99\r\n] 2006.252.08:09:21.24#ibcon#*before write, iclass 28, count 0 2006.252.08:09:21.24#ibcon#enter sib2, iclass 28, count 0 2006.252.08:09:21.24#ibcon#flushed, iclass 28, count 0 2006.252.08:09:21.24#ibcon#about to write, iclass 28, count 0 2006.252.08:09:21.24#ibcon#wrote, iclass 28, count 0 2006.252.08:09:21.24#ibcon#about to read 3, iclass 28, count 0 2006.252.08:09:21.28#ibcon#read 3, iclass 28, count 0 2006.252.08:09:21.28#ibcon#about to read 4, iclass 28, count 0 2006.252.08:09:21.28#ibcon#read 4, iclass 28, count 0 2006.252.08:09:21.28#ibcon#about to read 5, iclass 28, count 0 2006.252.08:09:21.28#ibcon#read 5, iclass 28, count 0 2006.252.08:09:21.28#ibcon#about to read 6, iclass 28, count 0 2006.252.08:09:21.28#ibcon#read 6, iclass 28, count 0 2006.252.08:09:21.28#ibcon#end of sib2, iclass 28, count 0 2006.252.08:09:21.28#ibcon#*after write, iclass 28, count 0 2006.252.08:09:21.28#ibcon#*before return 0, iclass 28, count 0 2006.252.08:09:21.28#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.252.08:09:21.28#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.252.08:09:21.28#ibcon#about to clear, iclass 28 cls_cnt 0 2006.252.08:09:21.28#ibcon#cleared, iclass 28 cls_cnt 0 2006.252.08:09:21.28$vc4f8/vb=3,4 2006.252.08:09:21.28#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.252.08:09:21.28#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.252.08:09:21.28#ibcon#ireg 11 cls_cnt 2 2006.252.08:09:21.28#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.252.08:09:21.34#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.252.08:09:21.34#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.252.08:09:21.34#ibcon#enter wrdev, iclass 30, count 2 2006.252.08:09:21.34#ibcon#first serial, iclass 30, count 2 2006.252.08:09:21.34#ibcon#enter sib2, iclass 30, count 2 2006.252.08:09:21.34#ibcon#flushed, iclass 30, count 2 2006.252.08:09:21.34#ibcon#about to write, iclass 30, count 2 2006.252.08:09:21.34#ibcon#wrote, iclass 30, count 2 2006.252.08:09:21.34#ibcon#about to read 3, iclass 30, count 2 2006.252.08:09:21.36#ibcon#read 3, iclass 30, count 2 2006.252.08:09:21.36#ibcon#about to read 4, iclass 30, count 2 2006.252.08:09:21.36#ibcon#read 4, iclass 30, count 2 2006.252.08:09:21.36#ibcon#about to read 5, iclass 30, count 2 2006.252.08:09:21.36#ibcon#read 5, iclass 30, count 2 2006.252.08:09:21.36#ibcon#about to read 6, iclass 30, count 2 2006.252.08:09:21.36#ibcon#read 6, iclass 30, count 2 2006.252.08:09:21.36#ibcon#end of sib2, iclass 30, count 2 2006.252.08:09:21.36#ibcon#*mode == 0, iclass 30, count 2 2006.252.08:09:21.36#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.252.08:09:21.36#ibcon#[27=AT03-04\r\n] 2006.252.08:09:21.36#ibcon#*before write, iclass 30, count 2 2006.252.08:09:21.36#ibcon#enter sib2, iclass 30, count 2 2006.252.08:09:21.36#ibcon#flushed, iclass 30, count 2 2006.252.08:09:21.36#ibcon#about to write, iclass 30, count 2 2006.252.08:09:21.36#ibcon#wrote, iclass 30, count 2 2006.252.08:09:21.36#ibcon#about to read 3, iclass 30, count 2 2006.252.08:09:21.39#ibcon#read 3, iclass 30, count 2 2006.252.08:09:21.39#ibcon#about to read 4, iclass 30, count 2 2006.252.08:09:21.39#ibcon#read 4, iclass 30, count 2 2006.252.08:09:21.39#ibcon#about to read 5, iclass 30, count 2 2006.252.08:09:21.39#ibcon#read 5, iclass 30, count 2 2006.252.08:09:21.39#ibcon#about to read 6, iclass 30, count 2 2006.252.08:09:21.39#ibcon#read 6, iclass 30, count 2 2006.252.08:09:21.39#ibcon#end of sib2, iclass 30, count 2 2006.252.08:09:21.39#ibcon#*after write, iclass 30, count 2 2006.252.08:09:21.39#ibcon#*before return 0, iclass 30, count 2 2006.252.08:09:21.39#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.252.08:09:21.39#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.252.08:09:21.39#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.252.08:09:21.39#ibcon#ireg 7 cls_cnt 0 2006.252.08:09:21.39#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.252.08:09:21.51#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.252.08:09:21.51#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.252.08:09:21.51#ibcon#enter wrdev, iclass 30, count 0 2006.252.08:09:21.51#ibcon#first serial, iclass 30, count 0 2006.252.08:09:21.51#ibcon#enter sib2, iclass 30, count 0 2006.252.08:09:21.51#ibcon#flushed, iclass 30, count 0 2006.252.08:09:21.51#ibcon#about to write, iclass 30, count 0 2006.252.08:09:21.51#ibcon#wrote, iclass 30, count 0 2006.252.08:09:21.51#ibcon#about to read 3, iclass 30, count 0 2006.252.08:09:21.53#ibcon#read 3, iclass 30, count 0 2006.252.08:09:21.53#ibcon#about to read 4, iclass 30, count 0 2006.252.08:09:21.53#ibcon#read 4, iclass 30, count 0 2006.252.08:09:21.53#ibcon#about to read 5, iclass 30, count 0 2006.252.08:09:21.53#ibcon#read 5, iclass 30, count 0 2006.252.08:09:21.53#ibcon#about to read 6, iclass 30, count 0 2006.252.08:09:21.53#ibcon#read 6, iclass 30, count 0 2006.252.08:09:21.53#ibcon#end of sib2, iclass 30, count 0 2006.252.08:09:21.53#ibcon#*mode == 0, iclass 30, count 0 2006.252.08:09:21.53#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.252.08:09:21.53#ibcon#[27=USB\r\n] 2006.252.08:09:21.53#ibcon#*before write, iclass 30, count 0 2006.252.08:09:21.53#ibcon#enter sib2, iclass 30, count 0 2006.252.08:09:21.53#ibcon#flushed, iclass 30, count 0 2006.252.08:09:21.53#ibcon#about to write, iclass 30, count 0 2006.252.08:09:21.53#ibcon#wrote, iclass 30, count 0 2006.252.08:09:21.53#ibcon#about to read 3, iclass 30, count 0 2006.252.08:09:21.56#ibcon#read 3, iclass 30, count 0 2006.252.08:09:21.56#ibcon#about to read 4, iclass 30, count 0 2006.252.08:09:21.56#ibcon#read 4, iclass 30, count 0 2006.252.08:09:21.56#ibcon#about to read 5, iclass 30, count 0 2006.252.08:09:21.56#ibcon#read 5, iclass 30, count 0 2006.252.08:09:21.56#ibcon#about to read 6, iclass 30, count 0 2006.252.08:09:21.56#ibcon#read 6, iclass 30, count 0 2006.252.08:09:21.56#ibcon#end of sib2, iclass 30, count 0 2006.252.08:09:21.56#ibcon#*after write, iclass 30, count 0 2006.252.08:09:21.56#ibcon#*before return 0, iclass 30, count 0 2006.252.08:09:21.56#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.252.08:09:21.56#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.252.08:09:21.56#ibcon#about to clear, iclass 30 cls_cnt 0 2006.252.08:09:21.56#ibcon#cleared, iclass 30 cls_cnt 0 2006.252.08:09:21.56$vc4f8/vblo=4,712.99 2006.252.08:09:21.56#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.252.08:09:21.56#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.252.08:09:21.56#ibcon#ireg 17 cls_cnt 0 2006.252.08:09:21.56#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.252.08:09:21.56#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.252.08:09:21.56#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.252.08:09:21.56#ibcon#enter wrdev, iclass 32, count 0 2006.252.08:09:21.56#ibcon#first serial, iclass 32, count 0 2006.252.08:09:21.56#ibcon#enter sib2, iclass 32, count 0 2006.252.08:09:21.56#ibcon#flushed, iclass 32, count 0 2006.252.08:09:21.56#ibcon#about to write, iclass 32, count 0 2006.252.08:09:21.56#ibcon#wrote, iclass 32, count 0 2006.252.08:09:21.56#ibcon#about to read 3, iclass 32, count 0 2006.252.08:09:21.58#ibcon#read 3, iclass 32, count 0 2006.252.08:09:21.58#ibcon#about to read 4, iclass 32, count 0 2006.252.08:09:21.58#ibcon#read 4, iclass 32, count 0 2006.252.08:09:21.58#ibcon#about to read 5, iclass 32, count 0 2006.252.08:09:21.58#ibcon#read 5, iclass 32, count 0 2006.252.08:09:21.58#ibcon#about to read 6, iclass 32, count 0 2006.252.08:09:21.58#ibcon#read 6, iclass 32, count 0 2006.252.08:09:21.58#ibcon#end of sib2, iclass 32, count 0 2006.252.08:09:21.58#ibcon#*mode == 0, iclass 32, count 0 2006.252.08:09:21.58#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.252.08:09:21.58#ibcon#[28=FRQ=04,712.99\r\n] 2006.252.08:09:21.58#ibcon#*before write, iclass 32, count 0 2006.252.08:09:21.58#ibcon#enter sib2, iclass 32, count 0 2006.252.08:09:21.58#ibcon#flushed, iclass 32, count 0 2006.252.08:09:21.58#ibcon#about to write, iclass 32, count 0 2006.252.08:09:21.58#ibcon#wrote, iclass 32, count 0 2006.252.08:09:21.58#ibcon#about to read 3, iclass 32, count 0 2006.252.08:09:21.62#ibcon#read 3, iclass 32, count 0 2006.252.08:09:21.62#ibcon#about to read 4, iclass 32, count 0 2006.252.08:09:21.62#ibcon#read 4, iclass 32, count 0 2006.252.08:09:21.62#ibcon#about to read 5, iclass 32, count 0 2006.252.08:09:21.62#ibcon#read 5, iclass 32, count 0 2006.252.08:09:21.62#ibcon#about to read 6, iclass 32, count 0 2006.252.08:09:21.62#ibcon#read 6, iclass 32, count 0 2006.252.08:09:21.62#ibcon#end of sib2, iclass 32, count 0 2006.252.08:09:21.62#ibcon#*after write, iclass 32, count 0 2006.252.08:09:21.62#ibcon#*before return 0, iclass 32, count 0 2006.252.08:09:21.62#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.252.08:09:21.62#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.252.08:09:21.62#ibcon#about to clear, iclass 32 cls_cnt 0 2006.252.08:09:21.62#ibcon#cleared, iclass 32 cls_cnt 0 2006.252.08:09:21.62$vc4f8/vb=4,4 2006.252.08:09:21.62#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.252.08:09:21.62#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.252.08:09:21.62#ibcon#ireg 11 cls_cnt 2 2006.252.08:09:21.62#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.252.08:09:21.68#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.252.08:09:21.68#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.252.08:09:21.68#ibcon#enter wrdev, iclass 34, count 2 2006.252.08:09:21.68#ibcon#first serial, iclass 34, count 2 2006.252.08:09:21.68#ibcon#enter sib2, iclass 34, count 2 2006.252.08:09:21.68#ibcon#flushed, iclass 34, count 2 2006.252.08:09:21.68#ibcon#about to write, iclass 34, count 2 2006.252.08:09:21.68#ibcon#wrote, iclass 34, count 2 2006.252.08:09:21.68#ibcon#about to read 3, iclass 34, count 2 2006.252.08:09:21.70#ibcon#read 3, iclass 34, count 2 2006.252.08:09:21.70#ibcon#about to read 4, iclass 34, count 2 2006.252.08:09:21.70#ibcon#read 4, iclass 34, count 2 2006.252.08:09:21.70#ibcon#about to read 5, iclass 34, count 2 2006.252.08:09:21.70#ibcon#read 5, iclass 34, count 2 2006.252.08:09:21.70#ibcon#about to read 6, iclass 34, count 2 2006.252.08:09:21.70#ibcon#read 6, iclass 34, count 2 2006.252.08:09:21.70#ibcon#end of sib2, iclass 34, count 2 2006.252.08:09:21.70#ibcon#*mode == 0, iclass 34, count 2 2006.252.08:09:21.70#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.252.08:09:21.70#ibcon#[27=AT04-04\r\n] 2006.252.08:09:21.70#ibcon#*before write, iclass 34, count 2 2006.252.08:09:21.70#ibcon#enter sib2, iclass 34, count 2 2006.252.08:09:21.70#ibcon#flushed, iclass 34, count 2 2006.252.08:09:21.70#ibcon#about to write, iclass 34, count 2 2006.252.08:09:21.70#ibcon#wrote, iclass 34, count 2 2006.252.08:09:21.70#ibcon#about to read 3, iclass 34, count 2 2006.252.08:09:21.73#ibcon#read 3, iclass 34, count 2 2006.252.08:09:21.73#ibcon#about to read 4, iclass 34, count 2 2006.252.08:09:21.73#ibcon#read 4, iclass 34, count 2 2006.252.08:09:21.73#ibcon#about to read 5, iclass 34, count 2 2006.252.08:09:21.73#ibcon#read 5, iclass 34, count 2 2006.252.08:09:21.73#ibcon#about to read 6, iclass 34, count 2 2006.252.08:09:21.73#ibcon#read 6, iclass 34, count 2 2006.252.08:09:21.73#ibcon#end of sib2, iclass 34, count 2 2006.252.08:09:21.73#ibcon#*after write, iclass 34, count 2 2006.252.08:09:21.73#ibcon#*before return 0, iclass 34, count 2 2006.252.08:09:21.73#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.252.08:09:21.73#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.252.08:09:21.73#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.252.08:09:21.73#ibcon#ireg 7 cls_cnt 0 2006.252.08:09:21.73#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.252.08:09:21.85#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.252.08:09:21.85#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.252.08:09:21.85#ibcon#enter wrdev, iclass 34, count 0 2006.252.08:09:21.85#ibcon#first serial, iclass 34, count 0 2006.252.08:09:21.85#ibcon#enter sib2, iclass 34, count 0 2006.252.08:09:21.85#ibcon#flushed, iclass 34, count 0 2006.252.08:09:21.85#ibcon#about to write, iclass 34, count 0 2006.252.08:09:21.85#ibcon#wrote, iclass 34, count 0 2006.252.08:09:21.85#ibcon#about to read 3, iclass 34, count 0 2006.252.08:09:21.87#ibcon#read 3, iclass 34, count 0 2006.252.08:09:21.87#ibcon#about to read 4, iclass 34, count 0 2006.252.08:09:21.87#ibcon#read 4, iclass 34, count 0 2006.252.08:09:21.87#ibcon#about to read 5, iclass 34, count 0 2006.252.08:09:21.87#ibcon#read 5, iclass 34, count 0 2006.252.08:09:21.87#ibcon#about to read 6, iclass 34, count 0 2006.252.08:09:21.87#ibcon#read 6, iclass 34, count 0 2006.252.08:09:21.87#ibcon#end of sib2, iclass 34, count 0 2006.252.08:09:21.87#ibcon#*mode == 0, iclass 34, count 0 2006.252.08:09:21.87#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.252.08:09:21.87#ibcon#[27=USB\r\n] 2006.252.08:09:21.87#ibcon#*before write, iclass 34, count 0 2006.252.08:09:21.87#ibcon#enter sib2, iclass 34, count 0 2006.252.08:09:21.87#ibcon#flushed, iclass 34, count 0 2006.252.08:09:21.87#ibcon#about to write, iclass 34, count 0 2006.252.08:09:21.87#ibcon#wrote, iclass 34, count 0 2006.252.08:09:21.87#ibcon#about to read 3, iclass 34, count 0 2006.252.08:09:21.90#ibcon#read 3, iclass 34, count 0 2006.252.08:09:21.90#ibcon#about to read 4, iclass 34, count 0 2006.252.08:09:21.90#ibcon#read 4, iclass 34, count 0 2006.252.08:09:21.90#ibcon#about to read 5, iclass 34, count 0 2006.252.08:09:21.90#ibcon#read 5, iclass 34, count 0 2006.252.08:09:21.90#ibcon#about to read 6, iclass 34, count 0 2006.252.08:09:21.90#ibcon#read 6, iclass 34, count 0 2006.252.08:09:21.90#ibcon#end of sib2, iclass 34, count 0 2006.252.08:09:21.90#ibcon#*after write, iclass 34, count 0 2006.252.08:09:21.90#ibcon#*before return 0, iclass 34, count 0 2006.252.08:09:21.90#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.252.08:09:21.90#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.252.08:09:21.90#ibcon#about to clear, iclass 34 cls_cnt 0 2006.252.08:09:21.90#ibcon#cleared, iclass 34 cls_cnt 0 2006.252.08:09:21.90$vc4f8/vblo=5,744.99 2006.252.08:09:21.90#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.252.08:09:21.90#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.252.08:09:21.90#ibcon#ireg 17 cls_cnt 0 2006.252.08:09:21.90#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.252.08:09:21.90#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.252.08:09:21.90#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.252.08:09:21.90#ibcon#enter wrdev, iclass 36, count 0 2006.252.08:09:21.90#ibcon#first serial, iclass 36, count 0 2006.252.08:09:21.90#ibcon#enter sib2, iclass 36, count 0 2006.252.08:09:21.90#ibcon#flushed, iclass 36, count 0 2006.252.08:09:21.90#ibcon#about to write, iclass 36, count 0 2006.252.08:09:21.90#ibcon#wrote, iclass 36, count 0 2006.252.08:09:21.90#ibcon#about to read 3, iclass 36, count 0 2006.252.08:09:21.92#ibcon#read 3, iclass 36, count 0 2006.252.08:09:21.92#ibcon#about to read 4, iclass 36, count 0 2006.252.08:09:21.92#ibcon#read 4, iclass 36, count 0 2006.252.08:09:21.92#ibcon#about to read 5, iclass 36, count 0 2006.252.08:09:21.92#ibcon#read 5, iclass 36, count 0 2006.252.08:09:21.92#ibcon#about to read 6, iclass 36, count 0 2006.252.08:09:21.92#ibcon#read 6, iclass 36, count 0 2006.252.08:09:21.92#ibcon#end of sib2, iclass 36, count 0 2006.252.08:09:21.92#ibcon#*mode == 0, iclass 36, count 0 2006.252.08:09:21.92#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.252.08:09:21.92#ibcon#[28=FRQ=05,744.99\r\n] 2006.252.08:09:21.92#ibcon#*before write, iclass 36, count 0 2006.252.08:09:21.92#ibcon#enter sib2, iclass 36, count 0 2006.252.08:09:21.92#ibcon#flushed, iclass 36, count 0 2006.252.08:09:21.92#ibcon#about to write, iclass 36, count 0 2006.252.08:09:21.92#ibcon#wrote, iclass 36, count 0 2006.252.08:09:21.92#ibcon#about to read 3, iclass 36, count 0 2006.252.08:09:21.97#ibcon#read 3, iclass 36, count 0 2006.252.08:09:21.97#ibcon#about to read 4, iclass 36, count 0 2006.252.08:09:21.97#ibcon#read 4, iclass 36, count 0 2006.252.08:09:21.97#ibcon#about to read 5, iclass 36, count 0 2006.252.08:09:21.97#ibcon#read 5, iclass 36, count 0 2006.252.08:09:21.97#ibcon#about to read 6, iclass 36, count 0 2006.252.08:09:21.97#ibcon#read 6, iclass 36, count 0 2006.252.08:09:21.97#ibcon#end of sib2, iclass 36, count 0 2006.252.08:09:21.97#ibcon#*after write, iclass 36, count 0 2006.252.08:09:21.97#ibcon#*before return 0, iclass 36, count 0 2006.252.08:09:21.97#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.252.08:09:21.97#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.252.08:09:21.97#ibcon#about to clear, iclass 36 cls_cnt 0 2006.252.08:09:21.97#ibcon#cleared, iclass 36 cls_cnt 0 2006.252.08:09:21.97$vc4f8/vb=5,4 2006.252.08:09:21.97#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.252.08:09:21.97#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.252.08:09:21.97#ibcon#ireg 11 cls_cnt 2 2006.252.08:09:21.97#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.252.08:09:22.02#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.252.08:09:22.02#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.252.08:09:22.02#ibcon#enter wrdev, iclass 38, count 2 2006.252.08:09:22.02#ibcon#first serial, iclass 38, count 2 2006.252.08:09:22.02#ibcon#enter sib2, iclass 38, count 2 2006.252.08:09:22.02#ibcon#flushed, iclass 38, count 2 2006.252.08:09:22.02#ibcon#about to write, iclass 38, count 2 2006.252.08:09:22.02#ibcon#wrote, iclass 38, count 2 2006.252.08:09:22.02#ibcon#about to read 3, iclass 38, count 2 2006.252.08:09:22.04#ibcon#read 3, iclass 38, count 2 2006.252.08:09:22.04#ibcon#about to read 4, iclass 38, count 2 2006.252.08:09:22.04#ibcon#read 4, iclass 38, count 2 2006.252.08:09:22.04#ibcon#about to read 5, iclass 38, count 2 2006.252.08:09:22.04#ibcon#read 5, iclass 38, count 2 2006.252.08:09:22.04#ibcon#about to read 6, iclass 38, count 2 2006.252.08:09:22.04#ibcon#read 6, iclass 38, count 2 2006.252.08:09:22.04#ibcon#end of sib2, iclass 38, count 2 2006.252.08:09:22.04#ibcon#*mode == 0, iclass 38, count 2 2006.252.08:09:22.04#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.252.08:09:22.04#ibcon#[27=AT05-04\r\n] 2006.252.08:09:22.04#ibcon#*before write, iclass 38, count 2 2006.252.08:09:22.04#ibcon#enter sib2, iclass 38, count 2 2006.252.08:09:22.04#ibcon#flushed, iclass 38, count 2 2006.252.08:09:22.04#ibcon#about to write, iclass 38, count 2 2006.252.08:09:22.04#ibcon#wrote, iclass 38, count 2 2006.252.08:09:22.04#ibcon#about to read 3, iclass 38, count 2 2006.252.08:09:22.07#ibcon#read 3, iclass 38, count 2 2006.252.08:09:22.07#ibcon#about to read 4, iclass 38, count 2 2006.252.08:09:22.07#ibcon#read 4, iclass 38, count 2 2006.252.08:09:22.07#ibcon#about to read 5, iclass 38, count 2 2006.252.08:09:22.07#ibcon#read 5, iclass 38, count 2 2006.252.08:09:22.07#ibcon#about to read 6, iclass 38, count 2 2006.252.08:09:22.07#ibcon#read 6, iclass 38, count 2 2006.252.08:09:22.07#ibcon#end of sib2, iclass 38, count 2 2006.252.08:09:22.07#ibcon#*after write, iclass 38, count 2 2006.252.08:09:22.07#ibcon#*before return 0, iclass 38, count 2 2006.252.08:09:22.07#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.252.08:09:22.07#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.252.08:09:22.07#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.252.08:09:22.07#ibcon#ireg 7 cls_cnt 0 2006.252.08:09:22.07#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.252.08:09:22.19#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.252.08:09:22.19#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.252.08:09:22.19#ibcon#enter wrdev, iclass 38, count 0 2006.252.08:09:22.19#ibcon#first serial, iclass 38, count 0 2006.252.08:09:22.19#ibcon#enter sib2, iclass 38, count 0 2006.252.08:09:22.19#ibcon#flushed, iclass 38, count 0 2006.252.08:09:22.19#ibcon#about to write, iclass 38, count 0 2006.252.08:09:22.19#ibcon#wrote, iclass 38, count 0 2006.252.08:09:22.19#ibcon#about to read 3, iclass 38, count 0 2006.252.08:09:22.21#ibcon#read 3, iclass 38, count 0 2006.252.08:09:22.21#ibcon#about to read 4, iclass 38, count 0 2006.252.08:09:22.21#ibcon#read 4, iclass 38, count 0 2006.252.08:09:22.21#ibcon#about to read 5, iclass 38, count 0 2006.252.08:09:22.21#ibcon#read 5, iclass 38, count 0 2006.252.08:09:22.21#ibcon#about to read 6, iclass 38, count 0 2006.252.08:09:22.21#ibcon#read 6, iclass 38, count 0 2006.252.08:09:22.21#ibcon#end of sib2, iclass 38, count 0 2006.252.08:09:22.21#ibcon#*mode == 0, iclass 38, count 0 2006.252.08:09:22.21#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.252.08:09:22.21#ibcon#[27=USB\r\n] 2006.252.08:09:22.21#ibcon#*before write, iclass 38, count 0 2006.252.08:09:22.21#ibcon#enter sib2, iclass 38, count 0 2006.252.08:09:22.21#ibcon#flushed, iclass 38, count 0 2006.252.08:09:22.21#ibcon#about to write, iclass 38, count 0 2006.252.08:09:22.21#ibcon#wrote, iclass 38, count 0 2006.252.08:09:22.21#ibcon#about to read 3, iclass 38, count 0 2006.252.08:09:22.24#ibcon#read 3, iclass 38, count 0 2006.252.08:09:22.24#ibcon#about to read 4, iclass 38, count 0 2006.252.08:09:22.24#ibcon#read 4, iclass 38, count 0 2006.252.08:09:22.24#ibcon#about to read 5, iclass 38, count 0 2006.252.08:09:22.24#ibcon#read 5, iclass 38, count 0 2006.252.08:09:22.24#ibcon#about to read 6, iclass 38, count 0 2006.252.08:09:22.24#ibcon#read 6, iclass 38, count 0 2006.252.08:09:22.24#ibcon#end of sib2, iclass 38, count 0 2006.252.08:09:22.24#ibcon#*after write, iclass 38, count 0 2006.252.08:09:22.24#ibcon#*before return 0, iclass 38, count 0 2006.252.08:09:22.24#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.252.08:09:22.24#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.252.08:09:22.24#ibcon#about to clear, iclass 38 cls_cnt 0 2006.252.08:09:22.24#ibcon#cleared, iclass 38 cls_cnt 0 2006.252.08:09:22.24$vc4f8/vblo=6,752.99 2006.252.08:09:22.24#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.252.08:09:22.24#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.252.08:09:22.24#ibcon#ireg 17 cls_cnt 0 2006.252.08:09:22.24#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.252.08:09:22.24#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.252.08:09:22.24#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.252.08:09:22.24#ibcon#enter wrdev, iclass 40, count 0 2006.252.08:09:22.24#ibcon#first serial, iclass 40, count 0 2006.252.08:09:22.24#ibcon#enter sib2, iclass 40, count 0 2006.252.08:09:22.24#ibcon#flushed, iclass 40, count 0 2006.252.08:09:22.24#ibcon#about to write, iclass 40, count 0 2006.252.08:09:22.24#ibcon#wrote, iclass 40, count 0 2006.252.08:09:22.24#ibcon#about to read 3, iclass 40, count 0 2006.252.08:09:22.26#ibcon#read 3, iclass 40, count 0 2006.252.08:09:22.26#ibcon#about to read 4, iclass 40, count 0 2006.252.08:09:22.26#ibcon#read 4, iclass 40, count 0 2006.252.08:09:22.26#ibcon#about to read 5, iclass 40, count 0 2006.252.08:09:22.26#ibcon#read 5, iclass 40, count 0 2006.252.08:09:22.26#ibcon#about to read 6, iclass 40, count 0 2006.252.08:09:22.26#ibcon#read 6, iclass 40, count 0 2006.252.08:09:22.26#ibcon#end of sib2, iclass 40, count 0 2006.252.08:09:22.26#ibcon#*mode == 0, iclass 40, count 0 2006.252.08:09:22.26#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.252.08:09:22.26#ibcon#[28=FRQ=06,752.99\r\n] 2006.252.08:09:22.26#ibcon#*before write, iclass 40, count 0 2006.252.08:09:22.26#ibcon#enter sib2, iclass 40, count 0 2006.252.08:09:22.26#ibcon#flushed, iclass 40, count 0 2006.252.08:09:22.26#ibcon#about to write, iclass 40, count 0 2006.252.08:09:22.26#ibcon#wrote, iclass 40, count 0 2006.252.08:09:22.26#ibcon#about to read 3, iclass 40, count 0 2006.252.08:09:22.30#ibcon#read 3, iclass 40, count 0 2006.252.08:09:22.30#ibcon#about to read 4, iclass 40, count 0 2006.252.08:09:22.30#ibcon#read 4, iclass 40, count 0 2006.252.08:09:22.30#ibcon#about to read 5, iclass 40, count 0 2006.252.08:09:22.30#ibcon#read 5, iclass 40, count 0 2006.252.08:09:22.30#ibcon#about to read 6, iclass 40, count 0 2006.252.08:09:22.30#ibcon#read 6, iclass 40, count 0 2006.252.08:09:22.30#ibcon#end of sib2, iclass 40, count 0 2006.252.08:09:22.30#ibcon#*after write, iclass 40, count 0 2006.252.08:09:22.30#ibcon#*before return 0, iclass 40, count 0 2006.252.08:09:22.30#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.252.08:09:22.30#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.252.08:09:22.30#ibcon#about to clear, iclass 40 cls_cnt 0 2006.252.08:09:22.30#ibcon#cleared, iclass 40 cls_cnt 0 2006.252.08:09:22.30$vc4f8/vb=6,4 2006.252.08:09:22.30#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.252.08:09:22.30#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.252.08:09:22.30#ibcon#ireg 11 cls_cnt 2 2006.252.08:09:22.30#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.252.08:09:22.36#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.252.08:09:22.36#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.252.08:09:22.36#ibcon#enter wrdev, iclass 4, count 2 2006.252.08:09:22.36#ibcon#first serial, iclass 4, count 2 2006.252.08:09:22.36#ibcon#enter sib2, iclass 4, count 2 2006.252.08:09:22.36#ibcon#flushed, iclass 4, count 2 2006.252.08:09:22.36#ibcon#about to write, iclass 4, count 2 2006.252.08:09:22.36#ibcon#wrote, iclass 4, count 2 2006.252.08:09:22.36#ibcon#about to read 3, iclass 4, count 2 2006.252.08:09:22.38#ibcon#read 3, iclass 4, count 2 2006.252.08:09:22.38#ibcon#about to read 4, iclass 4, count 2 2006.252.08:09:22.38#ibcon#read 4, iclass 4, count 2 2006.252.08:09:22.38#ibcon#about to read 5, iclass 4, count 2 2006.252.08:09:22.38#ibcon#read 5, iclass 4, count 2 2006.252.08:09:22.38#ibcon#about to read 6, iclass 4, count 2 2006.252.08:09:22.38#ibcon#read 6, iclass 4, count 2 2006.252.08:09:22.38#ibcon#end of sib2, iclass 4, count 2 2006.252.08:09:22.38#ibcon#*mode == 0, iclass 4, count 2 2006.252.08:09:22.38#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.252.08:09:22.38#ibcon#[27=AT06-04\r\n] 2006.252.08:09:22.38#ibcon#*before write, iclass 4, count 2 2006.252.08:09:22.38#ibcon#enter sib2, iclass 4, count 2 2006.252.08:09:22.38#ibcon#flushed, iclass 4, count 2 2006.252.08:09:22.38#ibcon#about to write, iclass 4, count 2 2006.252.08:09:22.38#ibcon#wrote, iclass 4, count 2 2006.252.08:09:22.38#ibcon#about to read 3, iclass 4, count 2 2006.252.08:09:22.41#ibcon#read 3, iclass 4, count 2 2006.252.08:09:22.41#ibcon#about to read 4, iclass 4, count 2 2006.252.08:09:22.41#ibcon#read 4, iclass 4, count 2 2006.252.08:09:22.41#ibcon#about to read 5, iclass 4, count 2 2006.252.08:09:22.41#ibcon#read 5, iclass 4, count 2 2006.252.08:09:22.41#ibcon#about to read 6, iclass 4, count 2 2006.252.08:09:22.41#ibcon#read 6, iclass 4, count 2 2006.252.08:09:22.41#ibcon#end of sib2, iclass 4, count 2 2006.252.08:09:22.41#ibcon#*after write, iclass 4, count 2 2006.252.08:09:22.41#ibcon#*before return 0, iclass 4, count 2 2006.252.08:09:22.41#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.252.08:09:22.41#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.252.08:09:22.41#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.252.08:09:22.41#ibcon#ireg 7 cls_cnt 0 2006.252.08:09:22.41#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.252.08:09:22.53#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.252.08:09:22.53#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.252.08:09:22.53#ibcon#enter wrdev, iclass 4, count 0 2006.252.08:09:22.53#ibcon#first serial, iclass 4, count 0 2006.252.08:09:22.53#ibcon#enter sib2, iclass 4, count 0 2006.252.08:09:22.53#ibcon#flushed, iclass 4, count 0 2006.252.08:09:22.53#ibcon#about to write, iclass 4, count 0 2006.252.08:09:22.53#ibcon#wrote, iclass 4, count 0 2006.252.08:09:22.53#ibcon#about to read 3, iclass 4, count 0 2006.252.08:09:22.55#ibcon#read 3, iclass 4, count 0 2006.252.08:09:22.55#ibcon#about to read 4, iclass 4, count 0 2006.252.08:09:22.55#ibcon#read 4, iclass 4, count 0 2006.252.08:09:22.55#ibcon#about to read 5, iclass 4, count 0 2006.252.08:09:22.55#ibcon#read 5, iclass 4, count 0 2006.252.08:09:22.55#ibcon#about to read 6, iclass 4, count 0 2006.252.08:09:22.55#ibcon#read 6, iclass 4, count 0 2006.252.08:09:22.55#ibcon#end of sib2, iclass 4, count 0 2006.252.08:09:22.55#ibcon#*mode == 0, iclass 4, count 0 2006.252.08:09:22.55#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.252.08:09:22.55#ibcon#[27=USB\r\n] 2006.252.08:09:22.55#ibcon#*before write, iclass 4, count 0 2006.252.08:09:22.55#ibcon#enter sib2, iclass 4, count 0 2006.252.08:09:22.55#ibcon#flushed, iclass 4, count 0 2006.252.08:09:22.55#ibcon#about to write, iclass 4, count 0 2006.252.08:09:22.55#ibcon#wrote, iclass 4, count 0 2006.252.08:09:22.55#ibcon#about to read 3, iclass 4, count 0 2006.252.08:09:22.58#ibcon#read 3, iclass 4, count 0 2006.252.08:09:22.58#ibcon#about to read 4, iclass 4, count 0 2006.252.08:09:22.58#ibcon#read 4, iclass 4, count 0 2006.252.08:09:22.58#ibcon#about to read 5, iclass 4, count 0 2006.252.08:09:22.58#ibcon#read 5, iclass 4, count 0 2006.252.08:09:22.58#ibcon#about to read 6, iclass 4, count 0 2006.252.08:09:22.58#ibcon#read 6, iclass 4, count 0 2006.252.08:09:22.58#ibcon#end of sib2, iclass 4, count 0 2006.252.08:09:22.58#ibcon#*after write, iclass 4, count 0 2006.252.08:09:22.58#ibcon#*before return 0, iclass 4, count 0 2006.252.08:09:22.58#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.252.08:09:22.58#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.252.08:09:22.58#ibcon#about to clear, iclass 4 cls_cnt 0 2006.252.08:09:22.58#ibcon#cleared, iclass 4 cls_cnt 0 2006.252.08:09:22.58$vc4f8/vabw=wide 2006.252.08:09:22.58#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.252.08:09:22.58#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.252.08:09:22.58#ibcon#ireg 8 cls_cnt 0 2006.252.08:09:22.58#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.252.08:09:22.58#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.252.08:09:22.58#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.252.08:09:22.58#ibcon#enter wrdev, iclass 6, count 0 2006.252.08:09:22.58#ibcon#first serial, iclass 6, count 0 2006.252.08:09:22.58#ibcon#enter sib2, iclass 6, count 0 2006.252.08:09:22.58#ibcon#flushed, iclass 6, count 0 2006.252.08:09:22.58#ibcon#about to write, iclass 6, count 0 2006.252.08:09:22.58#ibcon#wrote, iclass 6, count 0 2006.252.08:09:22.58#ibcon#about to read 3, iclass 6, count 0 2006.252.08:09:22.60#ibcon#read 3, iclass 6, count 0 2006.252.08:09:22.60#ibcon#about to read 4, iclass 6, count 0 2006.252.08:09:22.60#ibcon#read 4, iclass 6, count 0 2006.252.08:09:22.60#ibcon#about to read 5, iclass 6, count 0 2006.252.08:09:22.60#ibcon#read 5, iclass 6, count 0 2006.252.08:09:22.60#ibcon#about to read 6, iclass 6, count 0 2006.252.08:09:22.60#ibcon#read 6, iclass 6, count 0 2006.252.08:09:22.60#ibcon#end of sib2, iclass 6, count 0 2006.252.08:09:22.60#ibcon#*mode == 0, iclass 6, count 0 2006.252.08:09:22.60#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.252.08:09:22.60#ibcon#[25=BW32\r\n] 2006.252.08:09:22.60#ibcon#*before write, iclass 6, count 0 2006.252.08:09:22.60#ibcon#enter sib2, iclass 6, count 0 2006.252.08:09:22.60#ibcon#flushed, iclass 6, count 0 2006.252.08:09:22.60#ibcon#about to write, iclass 6, count 0 2006.252.08:09:22.60#ibcon#wrote, iclass 6, count 0 2006.252.08:09:22.60#ibcon#about to read 3, iclass 6, count 0 2006.252.08:09:22.64#ibcon#read 3, iclass 6, count 0 2006.252.08:09:22.64#ibcon#about to read 4, iclass 6, count 0 2006.252.08:09:22.64#ibcon#read 4, iclass 6, count 0 2006.252.08:09:22.64#ibcon#about to read 5, iclass 6, count 0 2006.252.08:09:22.64#ibcon#read 5, iclass 6, count 0 2006.252.08:09:22.64#ibcon#about to read 6, iclass 6, count 0 2006.252.08:09:22.64#ibcon#read 6, iclass 6, count 0 2006.252.08:09:22.64#ibcon#end of sib2, iclass 6, count 0 2006.252.08:09:22.64#ibcon#*after write, iclass 6, count 0 2006.252.08:09:22.64#ibcon#*before return 0, iclass 6, count 0 2006.252.08:09:22.64#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.252.08:09:22.64#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.252.08:09:22.64#ibcon#about to clear, iclass 6 cls_cnt 0 2006.252.08:09:22.64#ibcon#cleared, iclass 6 cls_cnt 0 2006.252.08:09:22.64$vc4f8/vbbw=wide 2006.252.08:09:22.64#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.252.08:09:22.64#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.252.08:09:22.64#ibcon#ireg 8 cls_cnt 0 2006.252.08:09:22.64#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.252.08:09:22.70#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.252.08:09:22.70#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.252.08:09:22.70#ibcon#enter wrdev, iclass 10, count 0 2006.252.08:09:22.70#ibcon#first serial, iclass 10, count 0 2006.252.08:09:22.70#ibcon#enter sib2, iclass 10, count 0 2006.252.08:09:22.70#ibcon#flushed, iclass 10, count 0 2006.252.08:09:22.70#ibcon#about to write, iclass 10, count 0 2006.252.08:09:22.70#ibcon#wrote, iclass 10, count 0 2006.252.08:09:22.70#ibcon#about to read 3, iclass 10, count 0 2006.252.08:09:22.72#ibcon#read 3, iclass 10, count 0 2006.252.08:09:22.72#ibcon#about to read 4, iclass 10, count 0 2006.252.08:09:22.72#ibcon#read 4, iclass 10, count 0 2006.252.08:09:22.72#ibcon#about to read 5, iclass 10, count 0 2006.252.08:09:22.72#ibcon#read 5, iclass 10, count 0 2006.252.08:09:22.72#ibcon#about to read 6, iclass 10, count 0 2006.252.08:09:22.72#ibcon#read 6, iclass 10, count 0 2006.252.08:09:22.72#ibcon#end of sib2, iclass 10, count 0 2006.252.08:09:22.72#ibcon#*mode == 0, iclass 10, count 0 2006.252.08:09:22.72#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.252.08:09:22.72#ibcon#[27=BW32\r\n] 2006.252.08:09:22.72#ibcon#*before write, iclass 10, count 0 2006.252.08:09:22.72#ibcon#enter sib2, iclass 10, count 0 2006.252.08:09:22.72#ibcon#flushed, iclass 10, count 0 2006.252.08:09:22.72#ibcon#about to write, iclass 10, count 0 2006.252.08:09:22.72#ibcon#wrote, iclass 10, count 0 2006.252.08:09:22.72#ibcon#about to read 3, iclass 10, count 0 2006.252.08:09:22.75#ibcon#read 3, iclass 10, count 0 2006.252.08:09:22.75#ibcon#about to read 4, iclass 10, count 0 2006.252.08:09:22.75#ibcon#read 4, iclass 10, count 0 2006.252.08:09:22.75#ibcon#about to read 5, iclass 10, count 0 2006.252.08:09:22.75#ibcon#read 5, iclass 10, count 0 2006.252.08:09:22.75#ibcon#about to read 6, iclass 10, count 0 2006.252.08:09:22.75#ibcon#read 6, iclass 10, count 0 2006.252.08:09:22.75#ibcon#end of sib2, iclass 10, count 0 2006.252.08:09:22.75#ibcon#*after write, iclass 10, count 0 2006.252.08:09:22.75#ibcon#*before return 0, iclass 10, count 0 2006.252.08:09:22.75#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.252.08:09:22.75#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.252.08:09:22.75#ibcon#about to clear, iclass 10 cls_cnt 0 2006.252.08:09:22.75#ibcon#cleared, iclass 10 cls_cnt 0 2006.252.08:09:22.75$4f8m12a/ifd4f 2006.252.08:09:22.75$ifd4f/lo= 2006.252.08:09:22.75$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.252.08:09:22.75$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.252.08:09:22.75$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.252.08:09:22.75$ifd4f/patch= 2006.252.08:09:22.75$ifd4f/patch=lo1,a1,a2,a3,a4 2006.252.08:09:22.75$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.252.08:09:22.75$ifd4f/patch=lo3,a5,a6,a7,a8 2006.252.08:09:22.75$4f8m12a/"form=m,16.000,1:2 2006.252.08:09:22.75$4f8m12a/"tpicd 2006.252.08:09:22.75$4f8m12a/echo=off 2006.252.08:09:22.75$4f8m12a/xlog=off 2006.252.08:09:22.75:!2006.252.08:09:50 2006.252.08:09:35.13#trakl#Source acquired 2006.252.08:09:35.13#flagr#flagr/antenna,acquired 2006.252.08:09:50.00:preob 2006.252.08:09:51.13/onsource/TRACKING 2006.252.08:09:51.13:!2006.252.08:10:00 2006.252.08:10:00.00:data_valid=on 2006.252.08:10:00.00:midob 2006.252.08:10:00.13/onsource/TRACKING 2006.252.08:10:00.13/wx/27.32,1011.1,90 2006.252.08:10:00.19/cable/+6.4102E-03 2006.252.08:10:01.28/va/01,08,usb,yes,33,34 2006.252.08:10:01.28/va/02,07,usb,yes,33,34 2006.252.08:10:01.28/va/03,06,usb,yes,35,35 2006.252.08:10:01.28/va/04,07,usb,yes,33,36 2006.252.08:10:01.28/va/05,07,usb,yes,37,39 2006.252.08:10:01.28/va/06,07,usb,yes,32,32 2006.252.08:10:01.28/va/07,07,usb,yes,32,32 2006.252.08:10:01.28/va/08,07,usb,yes,35,34 2006.252.08:10:01.51/valo/01,532.99,yes,locked 2006.252.08:10:01.51/valo/02,572.99,yes,locked 2006.252.08:10:01.51/valo/03,672.99,yes,locked 2006.252.08:10:01.51/valo/04,832.99,yes,locked 2006.252.08:10:01.51/valo/05,652.99,yes,locked 2006.252.08:10:01.51/valo/06,772.99,yes,locked 2006.252.08:10:01.51/valo/07,832.99,yes,locked 2006.252.08:10:01.51/valo/08,852.99,yes,locked 2006.252.08:10:02.60/vb/01,04,usb,yes,30,29 2006.252.08:10:02.60/vb/02,05,usb,yes,28,29 2006.252.08:10:02.60/vb/03,04,usb,yes,28,32 2006.252.08:10:02.60/vb/04,04,usb,yes,29,29 2006.252.08:10:02.60/vb/05,04,usb,yes,28,32 2006.252.08:10:02.60/vb/06,04,usb,yes,29,31 2006.252.08:10:02.60/vb/07,04,usb,yes,31,31 2006.252.08:10:02.60/vb/08,04,usb,yes,28,32 2006.252.08:10:02.83/vblo/01,632.99,yes,locked 2006.252.08:10:02.83/vblo/02,640.99,yes,locked 2006.252.08:10:02.83/vblo/03,656.99,yes,locked 2006.252.08:10:02.83/vblo/04,712.99,yes,locked 2006.252.08:10:02.83/vblo/05,744.99,yes,locked 2006.252.08:10:02.83/vblo/06,752.99,yes,locked 2006.252.08:10:02.83/vblo/07,734.99,yes,locked 2006.252.08:10:02.83/vblo/08,744.99,yes,locked 2006.252.08:10:02.98/vabw/8 2006.252.08:10:03.13/vbbw/8 2006.252.08:10:03.29/xfe/off,on,14.2 2006.252.08:10:03.67/ifatt/23,28,28,28 2006.252.08:10:04.08/fmout-gps/S +4.77E-07 2006.252.08:10:04.12:!2006.252.08:11:00 2006.252.08:11:00.00:data_valid=off 2006.252.08:11:00.00:postob 2006.252.08:11:00.16/cable/+6.4115E-03 2006.252.08:11:00.16/wx/27.31,1011.1,90 2006.252.08:11:01.08/fmout-gps/S +4.76E-07 2006.252.08:11:01.08:scan_name=252-0812,k06252,70 2006.252.08:11:01.08:source=1219+044,122222.55,041315.8,2000.0,ccw 2006.252.08:11:01.15#flagr#flagr/antenna,new-source 2006.252.08:11:02.13:checkk5 2006.252.08:11:02.49/chk_autoobs//k5ts1/ autoobs is running! 2006.252.08:11:02.87/chk_autoobs//k5ts2/ autoobs is running! 2006.252.08:11:03.25/chk_autoobs//k5ts3/ autoobs is running! 2006.252.08:11:03.62/chk_autoobs//k5ts4/ autoobs is running! 2006.252.08:11:03.99/chk_obsdata//k5ts1/T2520810??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.08:11:04.37/chk_obsdata//k5ts2/T2520810??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.08:11:04.73/chk_obsdata//k5ts3/T2520810??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.08:11:05.10/chk_obsdata//k5ts4/T2520810??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.08:11:05.80/k5log//k5ts1_log_newline 2006.252.08:11:06.48/k5log//k5ts2_log_newline 2006.252.08:11:07.18/k5log//k5ts3_log_newline 2006.252.08:11:07.86/k5log//k5ts4_log_newline 2006.252.08:11:07.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.252.08:11:07.89:4f8m12a=2 2006.252.08:11:07.89$4f8m12a/echo=on 2006.252.08:11:07.89$4f8m12a/pcalon 2006.252.08:11:07.89$pcalon/"no phase cal control is implemented here 2006.252.08:11:07.89$4f8m12a/"tpicd=stop 2006.252.08:11:07.89$4f8m12a/vc4f8 2006.252.08:11:07.89$vc4f8/valo=1,532.99 2006.252.08:11:07.89#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.252.08:11:07.89#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.252.08:11:07.89#ibcon#ireg 17 cls_cnt 0 2006.252.08:11:07.89#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.252.08:11:07.89#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.252.08:11:07.89#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.252.08:11:07.89#ibcon#enter wrdev, iclass 21, count 0 2006.252.08:11:07.89#ibcon#first serial, iclass 21, count 0 2006.252.08:11:07.89#ibcon#enter sib2, iclass 21, count 0 2006.252.08:11:07.89#ibcon#flushed, iclass 21, count 0 2006.252.08:11:07.89#ibcon#about to write, iclass 21, count 0 2006.252.08:11:07.89#ibcon#wrote, iclass 21, count 0 2006.252.08:11:07.89#ibcon#about to read 3, iclass 21, count 0 2006.252.08:11:07.91#ibcon#read 3, iclass 21, count 0 2006.252.08:11:07.91#ibcon#about to read 4, iclass 21, count 0 2006.252.08:11:07.91#ibcon#read 4, iclass 21, count 0 2006.252.08:11:07.91#ibcon#about to read 5, iclass 21, count 0 2006.252.08:11:07.91#ibcon#read 5, iclass 21, count 0 2006.252.08:11:07.91#ibcon#about to read 6, iclass 21, count 0 2006.252.08:11:07.91#ibcon#read 6, iclass 21, count 0 2006.252.08:11:07.91#ibcon#end of sib2, iclass 21, count 0 2006.252.08:11:07.91#ibcon#*mode == 0, iclass 21, count 0 2006.252.08:11:07.91#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.252.08:11:07.91#ibcon#[26=FRQ=01,532.99\r\n] 2006.252.08:11:07.91#ibcon#*before write, iclass 21, count 0 2006.252.08:11:07.91#ibcon#enter sib2, iclass 21, count 0 2006.252.08:11:07.91#ibcon#flushed, iclass 21, count 0 2006.252.08:11:07.91#ibcon#about to write, iclass 21, count 0 2006.252.08:11:07.91#ibcon#wrote, iclass 21, count 0 2006.252.08:11:07.91#ibcon#about to read 3, iclass 21, count 0 2006.252.08:11:07.96#ibcon#read 3, iclass 21, count 0 2006.252.08:11:07.96#ibcon#about to read 4, iclass 21, count 0 2006.252.08:11:07.96#ibcon#read 4, iclass 21, count 0 2006.252.08:11:07.96#ibcon#about to read 5, iclass 21, count 0 2006.252.08:11:07.96#ibcon#read 5, iclass 21, count 0 2006.252.08:11:07.96#ibcon#about to read 6, iclass 21, count 0 2006.252.08:11:07.96#ibcon#read 6, iclass 21, count 0 2006.252.08:11:07.96#ibcon#end of sib2, iclass 21, count 0 2006.252.08:11:07.96#ibcon#*after write, iclass 21, count 0 2006.252.08:11:07.96#ibcon#*before return 0, iclass 21, count 0 2006.252.08:11:07.96#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.252.08:11:07.96#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.252.08:11:07.96#ibcon#about to clear, iclass 21 cls_cnt 0 2006.252.08:11:07.96#ibcon#cleared, iclass 21 cls_cnt 0 2006.252.08:11:07.96$vc4f8/va=1,8 2006.252.08:11:07.96#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.252.08:11:07.96#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.252.08:11:07.96#ibcon#ireg 11 cls_cnt 2 2006.252.08:11:07.96#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.252.08:11:07.96#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.252.08:11:07.96#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.252.08:11:07.96#ibcon#enter wrdev, iclass 23, count 2 2006.252.08:11:07.96#ibcon#first serial, iclass 23, count 2 2006.252.08:11:07.96#ibcon#enter sib2, iclass 23, count 2 2006.252.08:11:07.96#ibcon#flushed, iclass 23, count 2 2006.252.08:11:07.96#ibcon#about to write, iclass 23, count 2 2006.252.08:11:07.96#ibcon#wrote, iclass 23, count 2 2006.252.08:11:07.96#ibcon#about to read 3, iclass 23, count 2 2006.252.08:11:07.98#ibcon#read 3, iclass 23, count 2 2006.252.08:11:07.98#ibcon#about to read 4, iclass 23, count 2 2006.252.08:11:07.98#ibcon#read 4, iclass 23, count 2 2006.252.08:11:07.98#ibcon#about to read 5, iclass 23, count 2 2006.252.08:11:07.98#ibcon#read 5, iclass 23, count 2 2006.252.08:11:07.98#ibcon#about to read 6, iclass 23, count 2 2006.252.08:11:07.98#ibcon#read 6, iclass 23, count 2 2006.252.08:11:07.98#ibcon#end of sib2, iclass 23, count 2 2006.252.08:11:07.98#ibcon#*mode == 0, iclass 23, count 2 2006.252.08:11:07.98#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.252.08:11:07.98#ibcon#[25=AT01-08\r\n] 2006.252.08:11:07.98#ibcon#*before write, iclass 23, count 2 2006.252.08:11:07.98#ibcon#enter sib2, iclass 23, count 2 2006.252.08:11:07.98#ibcon#flushed, iclass 23, count 2 2006.252.08:11:07.98#ibcon#about to write, iclass 23, count 2 2006.252.08:11:07.98#ibcon#wrote, iclass 23, count 2 2006.252.08:11:07.98#ibcon#about to read 3, iclass 23, count 2 2006.252.08:11:08.01#ibcon#read 3, iclass 23, count 2 2006.252.08:11:08.01#ibcon#about to read 4, iclass 23, count 2 2006.252.08:11:08.01#ibcon#read 4, iclass 23, count 2 2006.252.08:11:08.01#ibcon#about to read 5, iclass 23, count 2 2006.252.08:11:08.01#ibcon#read 5, iclass 23, count 2 2006.252.08:11:08.01#ibcon#about to read 6, iclass 23, count 2 2006.252.08:11:08.01#ibcon#read 6, iclass 23, count 2 2006.252.08:11:08.01#ibcon#end of sib2, iclass 23, count 2 2006.252.08:11:08.01#ibcon#*after write, iclass 23, count 2 2006.252.08:11:08.01#ibcon#*before return 0, iclass 23, count 2 2006.252.08:11:08.01#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.252.08:11:08.01#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.252.08:11:08.01#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.252.08:11:08.01#ibcon#ireg 7 cls_cnt 0 2006.252.08:11:08.01#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.252.08:11:08.13#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.252.08:11:08.13#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.252.08:11:08.13#ibcon#enter wrdev, iclass 23, count 0 2006.252.08:11:08.13#ibcon#first serial, iclass 23, count 0 2006.252.08:11:08.13#ibcon#enter sib2, iclass 23, count 0 2006.252.08:11:08.13#ibcon#flushed, iclass 23, count 0 2006.252.08:11:08.13#ibcon#about to write, iclass 23, count 0 2006.252.08:11:08.13#ibcon#wrote, iclass 23, count 0 2006.252.08:11:08.13#ibcon#about to read 3, iclass 23, count 0 2006.252.08:11:08.15#ibcon#read 3, iclass 23, count 0 2006.252.08:11:08.15#ibcon#about to read 4, iclass 23, count 0 2006.252.08:11:08.15#ibcon#read 4, iclass 23, count 0 2006.252.08:11:08.15#ibcon#about to read 5, iclass 23, count 0 2006.252.08:11:08.15#ibcon#read 5, iclass 23, count 0 2006.252.08:11:08.15#ibcon#about to read 6, iclass 23, count 0 2006.252.08:11:08.15#ibcon#read 6, iclass 23, count 0 2006.252.08:11:08.15#ibcon#end of sib2, iclass 23, count 0 2006.252.08:11:08.15#ibcon#*mode == 0, iclass 23, count 0 2006.252.08:11:08.15#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.252.08:11:08.15#ibcon#[25=USB\r\n] 2006.252.08:11:08.15#ibcon#*before write, iclass 23, count 0 2006.252.08:11:08.15#ibcon#enter sib2, iclass 23, count 0 2006.252.08:11:08.15#ibcon#flushed, iclass 23, count 0 2006.252.08:11:08.15#ibcon#about to write, iclass 23, count 0 2006.252.08:11:08.15#ibcon#wrote, iclass 23, count 0 2006.252.08:11:08.15#ibcon#about to read 3, iclass 23, count 0 2006.252.08:11:08.18#ibcon#read 3, iclass 23, count 0 2006.252.08:11:08.18#ibcon#about to read 4, iclass 23, count 0 2006.252.08:11:08.18#ibcon#read 4, iclass 23, count 0 2006.252.08:11:08.18#ibcon#about to read 5, iclass 23, count 0 2006.252.08:11:08.18#ibcon#read 5, iclass 23, count 0 2006.252.08:11:08.18#ibcon#about to read 6, iclass 23, count 0 2006.252.08:11:08.18#ibcon#read 6, iclass 23, count 0 2006.252.08:11:08.18#ibcon#end of sib2, iclass 23, count 0 2006.252.08:11:08.18#ibcon#*after write, iclass 23, count 0 2006.252.08:11:08.18#ibcon#*before return 0, iclass 23, count 0 2006.252.08:11:08.18#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.252.08:11:08.18#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.252.08:11:08.18#ibcon#about to clear, iclass 23 cls_cnt 0 2006.252.08:11:08.18#ibcon#cleared, iclass 23 cls_cnt 0 2006.252.08:11:08.18$vc4f8/valo=2,572.99 2006.252.08:11:08.18#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.252.08:11:08.18#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.252.08:11:08.18#ibcon#ireg 17 cls_cnt 0 2006.252.08:11:08.18#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.252.08:11:08.18#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.252.08:11:08.18#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.252.08:11:08.18#ibcon#enter wrdev, iclass 25, count 0 2006.252.08:11:08.18#ibcon#first serial, iclass 25, count 0 2006.252.08:11:08.18#ibcon#enter sib2, iclass 25, count 0 2006.252.08:11:08.18#ibcon#flushed, iclass 25, count 0 2006.252.08:11:08.18#ibcon#about to write, iclass 25, count 0 2006.252.08:11:08.18#ibcon#wrote, iclass 25, count 0 2006.252.08:11:08.18#ibcon#about to read 3, iclass 25, count 0 2006.252.08:11:08.20#ibcon#read 3, iclass 25, count 0 2006.252.08:11:08.20#ibcon#about to read 4, iclass 25, count 0 2006.252.08:11:08.20#ibcon#read 4, iclass 25, count 0 2006.252.08:11:08.20#ibcon#about to read 5, iclass 25, count 0 2006.252.08:11:08.20#ibcon#read 5, iclass 25, count 0 2006.252.08:11:08.20#ibcon#about to read 6, iclass 25, count 0 2006.252.08:11:08.20#ibcon#read 6, iclass 25, count 0 2006.252.08:11:08.20#ibcon#end of sib2, iclass 25, count 0 2006.252.08:11:08.20#ibcon#*mode == 0, iclass 25, count 0 2006.252.08:11:08.20#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.252.08:11:08.20#ibcon#[26=FRQ=02,572.99\r\n] 2006.252.08:11:08.20#ibcon#*before write, iclass 25, count 0 2006.252.08:11:08.20#ibcon#enter sib2, iclass 25, count 0 2006.252.08:11:08.20#ibcon#flushed, iclass 25, count 0 2006.252.08:11:08.20#ibcon#about to write, iclass 25, count 0 2006.252.08:11:08.20#ibcon#wrote, iclass 25, count 0 2006.252.08:11:08.20#ibcon#about to read 3, iclass 25, count 0 2006.252.08:11:08.25#ibcon#read 3, iclass 25, count 0 2006.252.08:11:08.25#ibcon#about to read 4, iclass 25, count 0 2006.252.08:11:08.25#ibcon#read 4, iclass 25, count 0 2006.252.08:11:08.25#ibcon#about to read 5, iclass 25, count 0 2006.252.08:11:08.25#ibcon#read 5, iclass 25, count 0 2006.252.08:11:08.25#ibcon#about to read 6, iclass 25, count 0 2006.252.08:11:08.25#ibcon#read 6, iclass 25, count 0 2006.252.08:11:08.25#ibcon#end of sib2, iclass 25, count 0 2006.252.08:11:08.25#ibcon#*after write, iclass 25, count 0 2006.252.08:11:08.25#ibcon#*before return 0, iclass 25, count 0 2006.252.08:11:08.25#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.252.08:11:08.25#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.252.08:11:08.25#ibcon#about to clear, iclass 25 cls_cnt 0 2006.252.08:11:08.25#ibcon#cleared, iclass 25 cls_cnt 0 2006.252.08:11:08.25$vc4f8/va=2,7 2006.252.08:11:08.25#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.252.08:11:08.25#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.252.08:11:08.25#ibcon#ireg 11 cls_cnt 2 2006.252.08:11:08.25#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.252.08:11:08.30#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.252.08:11:08.30#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.252.08:11:08.30#ibcon#enter wrdev, iclass 27, count 2 2006.252.08:11:08.30#ibcon#first serial, iclass 27, count 2 2006.252.08:11:08.30#ibcon#enter sib2, iclass 27, count 2 2006.252.08:11:08.30#ibcon#flushed, iclass 27, count 2 2006.252.08:11:08.30#ibcon#about to write, iclass 27, count 2 2006.252.08:11:08.30#ibcon#wrote, iclass 27, count 2 2006.252.08:11:08.30#ibcon#about to read 3, iclass 27, count 2 2006.252.08:11:08.32#ibcon#read 3, iclass 27, count 2 2006.252.08:11:08.32#ibcon#about to read 4, iclass 27, count 2 2006.252.08:11:08.32#ibcon#read 4, iclass 27, count 2 2006.252.08:11:08.32#ibcon#about to read 5, iclass 27, count 2 2006.252.08:11:08.32#ibcon#read 5, iclass 27, count 2 2006.252.08:11:08.32#ibcon#about to read 6, iclass 27, count 2 2006.252.08:11:08.32#ibcon#read 6, iclass 27, count 2 2006.252.08:11:08.32#ibcon#end of sib2, iclass 27, count 2 2006.252.08:11:08.32#ibcon#*mode == 0, iclass 27, count 2 2006.252.08:11:08.32#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.252.08:11:08.32#ibcon#[25=AT02-07\r\n] 2006.252.08:11:08.32#ibcon#*before write, iclass 27, count 2 2006.252.08:11:08.32#ibcon#enter sib2, iclass 27, count 2 2006.252.08:11:08.32#ibcon#flushed, iclass 27, count 2 2006.252.08:11:08.32#ibcon#about to write, iclass 27, count 2 2006.252.08:11:08.32#ibcon#wrote, iclass 27, count 2 2006.252.08:11:08.32#ibcon#about to read 3, iclass 27, count 2 2006.252.08:11:08.35#ibcon#read 3, iclass 27, count 2 2006.252.08:11:08.35#ibcon#about to read 4, iclass 27, count 2 2006.252.08:11:08.35#ibcon#read 4, iclass 27, count 2 2006.252.08:11:08.35#ibcon#about to read 5, iclass 27, count 2 2006.252.08:11:08.35#ibcon#read 5, iclass 27, count 2 2006.252.08:11:08.35#ibcon#about to read 6, iclass 27, count 2 2006.252.08:11:08.35#ibcon#read 6, iclass 27, count 2 2006.252.08:11:08.35#ibcon#end of sib2, iclass 27, count 2 2006.252.08:11:08.35#ibcon#*after write, iclass 27, count 2 2006.252.08:11:08.35#ibcon#*before return 0, iclass 27, count 2 2006.252.08:11:08.35#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.252.08:11:08.35#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.252.08:11:08.35#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.252.08:11:08.35#ibcon#ireg 7 cls_cnt 0 2006.252.08:11:08.35#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.252.08:11:08.47#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.252.08:11:08.47#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.252.08:11:08.47#ibcon#enter wrdev, iclass 27, count 0 2006.252.08:11:08.47#ibcon#first serial, iclass 27, count 0 2006.252.08:11:08.47#ibcon#enter sib2, iclass 27, count 0 2006.252.08:11:08.47#ibcon#flushed, iclass 27, count 0 2006.252.08:11:08.47#ibcon#about to write, iclass 27, count 0 2006.252.08:11:08.47#ibcon#wrote, iclass 27, count 0 2006.252.08:11:08.47#ibcon#about to read 3, iclass 27, count 0 2006.252.08:11:08.49#ibcon#read 3, iclass 27, count 0 2006.252.08:11:08.49#ibcon#about to read 4, iclass 27, count 0 2006.252.08:11:08.49#ibcon#read 4, iclass 27, count 0 2006.252.08:11:08.49#ibcon#about to read 5, iclass 27, count 0 2006.252.08:11:08.49#ibcon#read 5, iclass 27, count 0 2006.252.08:11:08.49#ibcon#about to read 6, iclass 27, count 0 2006.252.08:11:08.49#ibcon#read 6, iclass 27, count 0 2006.252.08:11:08.49#ibcon#end of sib2, iclass 27, count 0 2006.252.08:11:08.49#ibcon#*mode == 0, iclass 27, count 0 2006.252.08:11:08.49#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.252.08:11:08.49#ibcon#[25=USB\r\n] 2006.252.08:11:08.49#ibcon#*before write, iclass 27, count 0 2006.252.08:11:08.49#ibcon#enter sib2, iclass 27, count 0 2006.252.08:11:08.49#ibcon#flushed, iclass 27, count 0 2006.252.08:11:08.49#ibcon#about to write, iclass 27, count 0 2006.252.08:11:08.49#ibcon#wrote, iclass 27, count 0 2006.252.08:11:08.49#ibcon#about to read 3, iclass 27, count 0 2006.252.08:11:08.52#ibcon#read 3, iclass 27, count 0 2006.252.08:11:08.52#ibcon#about to read 4, iclass 27, count 0 2006.252.08:11:08.52#ibcon#read 4, iclass 27, count 0 2006.252.08:11:08.52#ibcon#about to read 5, iclass 27, count 0 2006.252.08:11:08.52#ibcon#read 5, iclass 27, count 0 2006.252.08:11:08.52#ibcon#about to read 6, iclass 27, count 0 2006.252.08:11:08.52#ibcon#read 6, iclass 27, count 0 2006.252.08:11:08.52#ibcon#end of sib2, iclass 27, count 0 2006.252.08:11:08.52#ibcon#*after write, iclass 27, count 0 2006.252.08:11:08.52#ibcon#*before return 0, iclass 27, count 0 2006.252.08:11:08.52#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.252.08:11:08.52#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.252.08:11:08.52#ibcon#about to clear, iclass 27 cls_cnt 0 2006.252.08:11:08.52#ibcon#cleared, iclass 27 cls_cnt 0 2006.252.08:11:08.52$vc4f8/valo=3,672.99 2006.252.08:11:08.52#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.252.08:11:08.52#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.252.08:11:08.52#ibcon#ireg 17 cls_cnt 0 2006.252.08:11:08.52#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.252.08:11:08.52#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.252.08:11:08.52#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.252.08:11:08.52#ibcon#enter wrdev, iclass 29, count 0 2006.252.08:11:08.52#ibcon#first serial, iclass 29, count 0 2006.252.08:11:08.52#ibcon#enter sib2, iclass 29, count 0 2006.252.08:11:08.52#ibcon#flushed, iclass 29, count 0 2006.252.08:11:08.52#ibcon#about to write, iclass 29, count 0 2006.252.08:11:08.52#ibcon#wrote, iclass 29, count 0 2006.252.08:11:08.52#ibcon#about to read 3, iclass 29, count 0 2006.252.08:11:08.54#ibcon#read 3, iclass 29, count 0 2006.252.08:11:08.54#ibcon#about to read 4, iclass 29, count 0 2006.252.08:11:08.54#ibcon#read 4, iclass 29, count 0 2006.252.08:11:08.54#ibcon#about to read 5, iclass 29, count 0 2006.252.08:11:08.54#ibcon#read 5, iclass 29, count 0 2006.252.08:11:08.54#ibcon#about to read 6, iclass 29, count 0 2006.252.08:11:08.54#ibcon#read 6, iclass 29, count 0 2006.252.08:11:08.54#ibcon#end of sib2, iclass 29, count 0 2006.252.08:11:08.54#ibcon#*mode == 0, iclass 29, count 0 2006.252.08:11:08.54#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.252.08:11:08.54#ibcon#[26=FRQ=03,672.99\r\n] 2006.252.08:11:08.54#ibcon#*before write, iclass 29, count 0 2006.252.08:11:08.54#ibcon#enter sib2, iclass 29, count 0 2006.252.08:11:08.54#ibcon#flushed, iclass 29, count 0 2006.252.08:11:08.54#ibcon#about to write, iclass 29, count 0 2006.252.08:11:08.54#ibcon#wrote, iclass 29, count 0 2006.252.08:11:08.54#ibcon#about to read 3, iclass 29, count 0 2006.252.08:11:08.58#ibcon#read 3, iclass 29, count 0 2006.252.08:11:08.58#ibcon#about to read 4, iclass 29, count 0 2006.252.08:11:08.58#ibcon#read 4, iclass 29, count 0 2006.252.08:11:08.58#ibcon#about to read 5, iclass 29, count 0 2006.252.08:11:08.58#ibcon#read 5, iclass 29, count 0 2006.252.08:11:08.58#ibcon#about to read 6, iclass 29, count 0 2006.252.08:11:08.58#ibcon#read 6, iclass 29, count 0 2006.252.08:11:08.58#ibcon#end of sib2, iclass 29, count 0 2006.252.08:11:08.58#ibcon#*after write, iclass 29, count 0 2006.252.08:11:08.58#ibcon#*before return 0, iclass 29, count 0 2006.252.08:11:08.58#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.252.08:11:08.58#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.252.08:11:08.58#ibcon#about to clear, iclass 29 cls_cnt 0 2006.252.08:11:08.58#ibcon#cleared, iclass 29 cls_cnt 0 2006.252.08:11:08.58$vc4f8/va=3,6 2006.252.08:11:08.58#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.252.08:11:08.58#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.252.08:11:08.58#ibcon#ireg 11 cls_cnt 2 2006.252.08:11:08.58#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.252.08:11:08.64#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.252.08:11:08.64#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.252.08:11:08.64#ibcon#enter wrdev, iclass 31, count 2 2006.252.08:11:08.64#ibcon#first serial, iclass 31, count 2 2006.252.08:11:08.64#ibcon#enter sib2, iclass 31, count 2 2006.252.08:11:08.64#ibcon#flushed, iclass 31, count 2 2006.252.08:11:08.64#ibcon#about to write, iclass 31, count 2 2006.252.08:11:08.64#ibcon#wrote, iclass 31, count 2 2006.252.08:11:08.64#ibcon#about to read 3, iclass 31, count 2 2006.252.08:11:08.66#ibcon#read 3, iclass 31, count 2 2006.252.08:11:08.66#ibcon#about to read 4, iclass 31, count 2 2006.252.08:11:08.66#ibcon#read 4, iclass 31, count 2 2006.252.08:11:08.66#ibcon#about to read 5, iclass 31, count 2 2006.252.08:11:08.66#ibcon#read 5, iclass 31, count 2 2006.252.08:11:08.66#ibcon#about to read 6, iclass 31, count 2 2006.252.08:11:08.66#ibcon#read 6, iclass 31, count 2 2006.252.08:11:08.66#ibcon#end of sib2, iclass 31, count 2 2006.252.08:11:08.66#ibcon#*mode == 0, iclass 31, count 2 2006.252.08:11:08.66#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.252.08:11:08.66#ibcon#[25=AT03-06\r\n] 2006.252.08:11:08.66#ibcon#*before write, iclass 31, count 2 2006.252.08:11:08.66#ibcon#enter sib2, iclass 31, count 2 2006.252.08:11:08.66#ibcon#flushed, iclass 31, count 2 2006.252.08:11:08.66#ibcon#about to write, iclass 31, count 2 2006.252.08:11:08.66#ibcon#wrote, iclass 31, count 2 2006.252.08:11:08.66#ibcon#about to read 3, iclass 31, count 2 2006.252.08:11:08.69#ibcon#read 3, iclass 31, count 2 2006.252.08:11:08.69#ibcon#about to read 4, iclass 31, count 2 2006.252.08:11:08.69#ibcon#read 4, iclass 31, count 2 2006.252.08:11:08.69#ibcon#about to read 5, iclass 31, count 2 2006.252.08:11:08.69#ibcon#read 5, iclass 31, count 2 2006.252.08:11:08.69#ibcon#about to read 6, iclass 31, count 2 2006.252.08:11:08.69#ibcon#read 6, iclass 31, count 2 2006.252.08:11:08.69#ibcon#end of sib2, iclass 31, count 2 2006.252.08:11:08.69#ibcon#*after write, iclass 31, count 2 2006.252.08:11:08.69#ibcon#*before return 0, iclass 31, count 2 2006.252.08:11:08.69#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.252.08:11:08.69#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.252.08:11:08.69#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.252.08:11:08.69#ibcon#ireg 7 cls_cnt 0 2006.252.08:11:08.69#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.252.08:11:08.81#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.252.08:11:08.81#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.252.08:11:08.81#ibcon#enter wrdev, iclass 31, count 0 2006.252.08:11:08.81#ibcon#first serial, iclass 31, count 0 2006.252.08:11:08.81#ibcon#enter sib2, iclass 31, count 0 2006.252.08:11:08.81#ibcon#flushed, iclass 31, count 0 2006.252.08:11:08.81#ibcon#about to write, iclass 31, count 0 2006.252.08:11:08.81#ibcon#wrote, iclass 31, count 0 2006.252.08:11:08.81#ibcon#about to read 3, iclass 31, count 0 2006.252.08:11:08.83#ibcon#read 3, iclass 31, count 0 2006.252.08:11:08.83#ibcon#about to read 4, iclass 31, count 0 2006.252.08:11:08.83#ibcon#read 4, iclass 31, count 0 2006.252.08:11:08.83#ibcon#about to read 5, iclass 31, count 0 2006.252.08:11:08.83#ibcon#read 5, iclass 31, count 0 2006.252.08:11:08.83#ibcon#about to read 6, iclass 31, count 0 2006.252.08:11:08.83#ibcon#read 6, iclass 31, count 0 2006.252.08:11:08.83#ibcon#end of sib2, iclass 31, count 0 2006.252.08:11:08.83#ibcon#*mode == 0, iclass 31, count 0 2006.252.08:11:08.83#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.252.08:11:08.83#ibcon#[25=USB\r\n] 2006.252.08:11:08.83#ibcon#*before write, iclass 31, count 0 2006.252.08:11:08.83#ibcon#enter sib2, iclass 31, count 0 2006.252.08:11:08.83#ibcon#flushed, iclass 31, count 0 2006.252.08:11:08.83#ibcon#about to write, iclass 31, count 0 2006.252.08:11:08.83#ibcon#wrote, iclass 31, count 0 2006.252.08:11:08.83#ibcon#about to read 3, iclass 31, count 0 2006.252.08:11:08.86#ibcon#read 3, iclass 31, count 0 2006.252.08:11:08.86#ibcon#about to read 4, iclass 31, count 0 2006.252.08:11:08.86#ibcon#read 4, iclass 31, count 0 2006.252.08:11:08.86#ibcon#about to read 5, iclass 31, count 0 2006.252.08:11:08.86#ibcon#read 5, iclass 31, count 0 2006.252.08:11:08.86#ibcon#about to read 6, iclass 31, count 0 2006.252.08:11:08.86#ibcon#read 6, iclass 31, count 0 2006.252.08:11:08.86#ibcon#end of sib2, iclass 31, count 0 2006.252.08:11:08.86#ibcon#*after write, iclass 31, count 0 2006.252.08:11:08.86#ibcon#*before return 0, iclass 31, count 0 2006.252.08:11:08.86#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.252.08:11:08.86#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.252.08:11:08.86#ibcon#about to clear, iclass 31 cls_cnt 0 2006.252.08:11:08.86#ibcon#cleared, iclass 31 cls_cnt 0 2006.252.08:11:08.86$vc4f8/valo=4,832.99 2006.252.08:11:08.86#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.252.08:11:08.86#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.252.08:11:08.86#ibcon#ireg 17 cls_cnt 0 2006.252.08:11:08.86#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.252.08:11:08.86#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.252.08:11:08.86#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.252.08:11:08.86#ibcon#enter wrdev, iclass 33, count 0 2006.252.08:11:08.86#ibcon#first serial, iclass 33, count 0 2006.252.08:11:08.86#ibcon#enter sib2, iclass 33, count 0 2006.252.08:11:08.86#ibcon#flushed, iclass 33, count 0 2006.252.08:11:08.86#ibcon#about to write, iclass 33, count 0 2006.252.08:11:08.86#ibcon#wrote, iclass 33, count 0 2006.252.08:11:08.86#ibcon#about to read 3, iclass 33, count 0 2006.252.08:11:08.88#ibcon#read 3, iclass 33, count 0 2006.252.08:11:08.88#ibcon#about to read 4, iclass 33, count 0 2006.252.08:11:08.88#ibcon#read 4, iclass 33, count 0 2006.252.08:11:08.88#ibcon#about to read 5, iclass 33, count 0 2006.252.08:11:08.88#ibcon#read 5, iclass 33, count 0 2006.252.08:11:08.88#ibcon#about to read 6, iclass 33, count 0 2006.252.08:11:08.88#ibcon#read 6, iclass 33, count 0 2006.252.08:11:08.88#ibcon#end of sib2, iclass 33, count 0 2006.252.08:11:08.88#ibcon#*mode == 0, iclass 33, count 0 2006.252.08:11:08.88#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.252.08:11:08.88#ibcon#[26=FRQ=04,832.99\r\n] 2006.252.08:11:08.88#ibcon#*before write, iclass 33, count 0 2006.252.08:11:08.88#ibcon#enter sib2, iclass 33, count 0 2006.252.08:11:08.88#ibcon#flushed, iclass 33, count 0 2006.252.08:11:08.88#ibcon#about to write, iclass 33, count 0 2006.252.08:11:08.88#ibcon#wrote, iclass 33, count 0 2006.252.08:11:08.88#ibcon#about to read 3, iclass 33, count 0 2006.252.08:11:08.92#ibcon#read 3, iclass 33, count 0 2006.252.08:11:08.92#ibcon#about to read 4, iclass 33, count 0 2006.252.08:11:08.92#ibcon#read 4, iclass 33, count 0 2006.252.08:11:08.92#ibcon#about to read 5, iclass 33, count 0 2006.252.08:11:08.92#ibcon#read 5, iclass 33, count 0 2006.252.08:11:08.92#ibcon#about to read 6, iclass 33, count 0 2006.252.08:11:08.92#ibcon#read 6, iclass 33, count 0 2006.252.08:11:08.92#ibcon#end of sib2, iclass 33, count 0 2006.252.08:11:08.92#ibcon#*after write, iclass 33, count 0 2006.252.08:11:08.92#ibcon#*before return 0, iclass 33, count 0 2006.252.08:11:08.92#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.252.08:11:08.92#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.252.08:11:08.92#ibcon#about to clear, iclass 33 cls_cnt 0 2006.252.08:11:08.92#ibcon#cleared, iclass 33 cls_cnt 0 2006.252.08:11:08.92$vc4f8/va=4,7 2006.252.08:11:08.92#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.252.08:11:08.92#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.252.08:11:08.92#ibcon#ireg 11 cls_cnt 2 2006.252.08:11:08.92#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.252.08:11:08.98#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.252.08:11:08.98#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.252.08:11:08.98#ibcon#enter wrdev, iclass 35, count 2 2006.252.08:11:08.98#ibcon#first serial, iclass 35, count 2 2006.252.08:11:08.98#ibcon#enter sib2, iclass 35, count 2 2006.252.08:11:08.98#ibcon#flushed, iclass 35, count 2 2006.252.08:11:08.98#ibcon#about to write, iclass 35, count 2 2006.252.08:11:08.98#ibcon#wrote, iclass 35, count 2 2006.252.08:11:08.98#ibcon#about to read 3, iclass 35, count 2 2006.252.08:11:09.00#ibcon#read 3, iclass 35, count 2 2006.252.08:11:09.00#ibcon#about to read 4, iclass 35, count 2 2006.252.08:11:09.00#ibcon#read 4, iclass 35, count 2 2006.252.08:11:09.00#ibcon#about to read 5, iclass 35, count 2 2006.252.08:11:09.00#ibcon#read 5, iclass 35, count 2 2006.252.08:11:09.00#ibcon#about to read 6, iclass 35, count 2 2006.252.08:11:09.00#ibcon#read 6, iclass 35, count 2 2006.252.08:11:09.00#ibcon#end of sib2, iclass 35, count 2 2006.252.08:11:09.00#ibcon#*mode == 0, iclass 35, count 2 2006.252.08:11:09.00#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.252.08:11:09.00#ibcon#[25=AT04-07\r\n] 2006.252.08:11:09.00#ibcon#*before write, iclass 35, count 2 2006.252.08:11:09.00#ibcon#enter sib2, iclass 35, count 2 2006.252.08:11:09.00#ibcon#flushed, iclass 35, count 2 2006.252.08:11:09.00#ibcon#about to write, iclass 35, count 2 2006.252.08:11:09.00#ibcon#wrote, iclass 35, count 2 2006.252.08:11:09.00#ibcon#about to read 3, iclass 35, count 2 2006.252.08:11:09.03#ibcon#read 3, iclass 35, count 2 2006.252.08:11:09.03#ibcon#about to read 4, iclass 35, count 2 2006.252.08:11:09.03#ibcon#read 4, iclass 35, count 2 2006.252.08:11:09.03#ibcon#about to read 5, iclass 35, count 2 2006.252.08:11:09.03#ibcon#read 5, iclass 35, count 2 2006.252.08:11:09.03#ibcon#about to read 6, iclass 35, count 2 2006.252.08:11:09.03#ibcon#read 6, iclass 35, count 2 2006.252.08:11:09.03#ibcon#end of sib2, iclass 35, count 2 2006.252.08:11:09.03#ibcon#*after write, iclass 35, count 2 2006.252.08:11:09.03#ibcon#*before return 0, iclass 35, count 2 2006.252.08:11:09.03#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.252.08:11:09.03#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.252.08:11:09.03#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.252.08:11:09.03#ibcon#ireg 7 cls_cnt 0 2006.252.08:11:09.03#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.252.08:11:09.15#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.252.08:11:09.15#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.252.08:11:09.15#ibcon#enter wrdev, iclass 35, count 0 2006.252.08:11:09.15#ibcon#first serial, iclass 35, count 0 2006.252.08:11:09.15#ibcon#enter sib2, iclass 35, count 0 2006.252.08:11:09.15#ibcon#flushed, iclass 35, count 0 2006.252.08:11:09.15#ibcon#about to write, iclass 35, count 0 2006.252.08:11:09.15#ibcon#wrote, iclass 35, count 0 2006.252.08:11:09.15#ibcon#about to read 3, iclass 35, count 0 2006.252.08:11:09.17#ibcon#read 3, iclass 35, count 0 2006.252.08:11:09.17#ibcon#about to read 4, iclass 35, count 0 2006.252.08:11:09.17#ibcon#read 4, iclass 35, count 0 2006.252.08:11:09.17#ibcon#about to read 5, iclass 35, count 0 2006.252.08:11:09.17#ibcon#read 5, iclass 35, count 0 2006.252.08:11:09.17#ibcon#about to read 6, iclass 35, count 0 2006.252.08:11:09.17#ibcon#read 6, iclass 35, count 0 2006.252.08:11:09.17#ibcon#end of sib2, iclass 35, count 0 2006.252.08:11:09.17#ibcon#*mode == 0, iclass 35, count 0 2006.252.08:11:09.17#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.252.08:11:09.17#ibcon#[25=USB\r\n] 2006.252.08:11:09.17#ibcon#*before write, iclass 35, count 0 2006.252.08:11:09.17#ibcon#enter sib2, iclass 35, count 0 2006.252.08:11:09.17#ibcon#flushed, iclass 35, count 0 2006.252.08:11:09.17#ibcon#about to write, iclass 35, count 0 2006.252.08:11:09.17#ibcon#wrote, iclass 35, count 0 2006.252.08:11:09.17#ibcon#about to read 3, iclass 35, count 0 2006.252.08:11:09.20#ibcon#read 3, iclass 35, count 0 2006.252.08:11:09.20#ibcon#about to read 4, iclass 35, count 0 2006.252.08:11:09.20#ibcon#read 4, iclass 35, count 0 2006.252.08:11:09.20#ibcon#about to read 5, iclass 35, count 0 2006.252.08:11:09.20#ibcon#read 5, iclass 35, count 0 2006.252.08:11:09.20#ibcon#about to read 6, iclass 35, count 0 2006.252.08:11:09.20#ibcon#read 6, iclass 35, count 0 2006.252.08:11:09.20#ibcon#end of sib2, iclass 35, count 0 2006.252.08:11:09.20#ibcon#*after write, iclass 35, count 0 2006.252.08:11:09.20#ibcon#*before return 0, iclass 35, count 0 2006.252.08:11:09.20#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.252.08:11:09.20#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.252.08:11:09.20#ibcon#about to clear, iclass 35 cls_cnt 0 2006.252.08:11:09.20#ibcon#cleared, iclass 35 cls_cnt 0 2006.252.08:11:09.20$vc4f8/valo=5,652.99 2006.252.08:11:09.20#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.252.08:11:09.20#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.252.08:11:09.20#ibcon#ireg 17 cls_cnt 0 2006.252.08:11:09.20#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.252.08:11:09.20#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.252.08:11:09.20#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.252.08:11:09.20#ibcon#enter wrdev, iclass 37, count 0 2006.252.08:11:09.20#ibcon#first serial, iclass 37, count 0 2006.252.08:11:09.20#ibcon#enter sib2, iclass 37, count 0 2006.252.08:11:09.20#ibcon#flushed, iclass 37, count 0 2006.252.08:11:09.20#ibcon#about to write, iclass 37, count 0 2006.252.08:11:09.20#ibcon#wrote, iclass 37, count 0 2006.252.08:11:09.20#ibcon#about to read 3, iclass 37, count 0 2006.252.08:11:09.22#ibcon#read 3, iclass 37, count 0 2006.252.08:11:09.22#ibcon#about to read 4, iclass 37, count 0 2006.252.08:11:09.22#ibcon#read 4, iclass 37, count 0 2006.252.08:11:09.22#ibcon#about to read 5, iclass 37, count 0 2006.252.08:11:09.22#ibcon#read 5, iclass 37, count 0 2006.252.08:11:09.22#ibcon#about to read 6, iclass 37, count 0 2006.252.08:11:09.22#ibcon#read 6, iclass 37, count 0 2006.252.08:11:09.22#ibcon#end of sib2, iclass 37, count 0 2006.252.08:11:09.22#ibcon#*mode == 0, iclass 37, count 0 2006.252.08:11:09.22#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.252.08:11:09.22#ibcon#[26=FRQ=05,652.99\r\n] 2006.252.08:11:09.22#ibcon#*before write, iclass 37, count 0 2006.252.08:11:09.22#ibcon#enter sib2, iclass 37, count 0 2006.252.08:11:09.22#ibcon#flushed, iclass 37, count 0 2006.252.08:11:09.22#ibcon#about to write, iclass 37, count 0 2006.252.08:11:09.22#ibcon#wrote, iclass 37, count 0 2006.252.08:11:09.22#ibcon#about to read 3, iclass 37, count 0 2006.252.08:11:09.26#ibcon#read 3, iclass 37, count 0 2006.252.08:11:09.26#ibcon#about to read 4, iclass 37, count 0 2006.252.08:11:09.26#ibcon#read 4, iclass 37, count 0 2006.252.08:11:09.26#ibcon#about to read 5, iclass 37, count 0 2006.252.08:11:09.26#ibcon#read 5, iclass 37, count 0 2006.252.08:11:09.26#ibcon#about to read 6, iclass 37, count 0 2006.252.08:11:09.26#ibcon#read 6, iclass 37, count 0 2006.252.08:11:09.26#ibcon#end of sib2, iclass 37, count 0 2006.252.08:11:09.26#ibcon#*after write, iclass 37, count 0 2006.252.08:11:09.26#ibcon#*before return 0, iclass 37, count 0 2006.252.08:11:09.26#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.252.08:11:09.26#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.252.08:11:09.26#ibcon#about to clear, iclass 37 cls_cnt 0 2006.252.08:11:09.26#ibcon#cleared, iclass 37 cls_cnt 0 2006.252.08:11:09.26$vc4f8/va=5,7 2006.252.08:11:09.26#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.252.08:11:09.26#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.252.08:11:09.26#ibcon#ireg 11 cls_cnt 2 2006.252.08:11:09.26#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.252.08:11:09.32#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.252.08:11:09.32#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.252.08:11:09.32#ibcon#enter wrdev, iclass 39, count 2 2006.252.08:11:09.32#ibcon#first serial, iclass 39, count 2 2006.252.08:11:09.32#ibcon#enter sib2, iclass 39, count 2 2006.252.08:11:09.32#ibcon#flushed, iclass 39, count 2 2006.252.08:11:09.32#ibcon#about to write, iclass 39, count 2 2006.252.08:11:09.32#ibcon#wrote, iclass 39, count 2 2006.252.08:11:09.32#ibcon#about to read 3, iclass 39, count 2 2006.252.08:11:09.34#ibcon#read 3, iclass 39, count 2 2006.252.08:11:09.34#ibcon#about to read 4, iclass 39, count 2 2006.252.08:11:09.34#ibcon#read 4, iclass 39, count 2 2006.252.08:11:09.34#ibcon#about to read 5, iclass 39, count 2 2006.252.08:11:09.34#ibcon#read 5, iclass 39, count 2 2006.252.08:11:09.34#ibcon#about to read 6, iclass 39, count 2 2006.252.08:11:09.34#ibcon#read 6, iclass 39, count 2 2006.252.08:11:09.34#ibcon#end of sib2, iclass 39, count 2 2006.252.08:11:09.34#ibcon#*mode == 0, iclass 39, count 2 2006.252.08:11:09.34#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.252.08:11:09.34#ibcon#[25=AT05-07\r\n] 2006.252.08:11:09.34#ibcon#*before write, iclass 39, count 2 2006.252.08:11:09.34#ibcon#enter sib2, iclass 39, count 2 2006.252.08:11:09.34#ibcon#flushed, iclass 39, count 2 2006.252.08:11:09.34#ibcon#about to write, iclass 39, count 2 2006.252.08:11:09.34#ibcon#wrote, iclass 39, count 2 2006.252.08:11:09.34#ibcon#about to read 3, iclass 39, count 2 2006.252.08:11:09.37#ibcon#read 3, iclass 39, count 2 2006.252.08:11:09.37#ibcon#about to read 4, iclass 39, count 2 2006.252.08:11:09.37#ibcon#read 4, iclass 39, count 2 2006.252.08:11:09.37#ibcon#about to read 5, iclass 39, count 2 2006.252.08:11:09.37#ibcon#read 5, iclass 39, count 2 2006.252.08:11:09.37#ibcon#about to read 6, iclass 39, count 2 2006.252.08:11:09.37#ibcon#read 6, iclass 39, count 2 2006.252.08:11:09.37#ibcon#end of sib2, iclass 39, count 2 2006.252.08:11:09.37#ibcon#*after write, iclass 39, count 2 2006.252.08:11:09.37#ibcon#*before return 0, iclass 39, count 2 2006.252.08:11:09.37#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.252.08:11:09.37#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.252.08:11:09.37#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.252.08:11:09.37#ibcon#ireg 7 cls_cnt 0 2006.252.08:11:09.37#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.252.08:11:09.49#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.252.08:11:09.49#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.252.08:11:09.49#ibcon#enter wrdev, iclass 39, count 0 2006.252.08:11:09.49#ibcon#first serial, iclass 39, count 0 2006.252.08:11:09.49#ibcon#enter sib2, iclass 39, count 0 2006.252.08:11:09.49#ibcon#flushed, iclass 39, count 0 2006.252.08:11:09.49#ibcon#about to write, iclass 39, count 0 2006.252.08:11:09.49#ibcon#wrote, iclass 39, count 0 2006.252.08:11:09.49#ibcon#about to read 3, iclass 39, count 0 2006.252.08:11:09.51#ibcon#read 3, iclass 39, count 0 2006.252.08:11:09.51#ibcon#about to read 4, iclass 39, count 0 2006.252.08:11:09.51#ibcon#read 4, iclass 39, count 0 2006.252.08:11:09.51#ibcon#about to read 5, iclass 39, count 0 2006.252.08:11:09.51#ibcon#read 5, iclass 39, count 0 2006.252.08:11:09.51#ibcon#about to read 6, iclass 39, count 0 2006.252.08:11:09.51#ibcon#read 6, iclass 39, count 0 2006.252.08:11:09.51#ibcon#end of sib2, iclass 39, count 0 2006.252.08:11:09.51#ibcon#*mode == 0, iclass 39, count 0 2006.252.08:11:09.51#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.252.08:11:09.51#ibcon#[25=USB\r\n] 2006.252.08:11:09.51#ibcon#*before write, iclass 39, count 0 2006.252.08:11:09.51#ibcon#enter sib2, iclass 39, count 0 2006.252.08:11:09.51#ibcon#flushed, iclass 39, count 0 2006.252.08:11:09.51#ibcon#about to write, iclass 39, count 0 2006.252.08:11:09.51#ibcon#wrote, iclass 39, count 0 2006.252.08:11:09.51#ibcon#about to read 3, iclass 39, count 0 2006.252.08:11:09.54#ibcon#read 3, iclass 39, count 0 2006.252.08:11:09.54#ibcon#about to read 4, iclass 39, count 0 2006.252.08:11:09.54#ibcon#read 4, iclass 39, count 0 2006.252.08:11:09.54#ibcon#about to read 5, iclass 39, count 0 2006.252.08:11:09.54#ibcon#read 5, iclass 39, count 0 2006.252.08:11:09.54#ibcon#about to read 6, iclass 39, count 0 2006.252.08:11:09.54#ibcon#read 6, iclass 39, count 0 2006.252.08:11:09.54#ibcon#end of sib2, iclass 39, count 0 2006.252.08:11:09.54#ibcon#*after write, iclass 39, count 0 2006.252.08:11:09.54#ibcon#*before return 0, iclass 39, count 0 2006.252.08:11:09.54#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.252.08:11:09.54#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.252.08:11:09.54#ibcon#about to clear, iclass 39 cls_cnt 0 2006.252.08:11:09.54#ibcon#cleared, iclass 39 cls_cnt 0 2006.252.08:11:09.54$vc4f8/valo=6,772.99 2006.252.08:11:09.54#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.252.08:11:09.54#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.252.08:11:09.54#ibcon#ireg 17 cls_cnt 0 2006.252.08:11:09.54#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.252.08:11:09.54#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.252.08:11:09.54#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.252.08:11:09.54#ibcon#enter wrdev, iclass 3, count 0 2006.252.08:11:09.54#ibcon#first serial, iclass 3, count 0 2006.252.08:11:09.54#ibcon#enter sib2, iclass 3, count 0 2006.252.08:11:09.54#ibcon#flushed, iclass 3, count 0 2006.252.08:11:09.54#ibcon#about to write, iclass 3, count 0 2006.252.08:11:09.54#ibcon#wrote, iclass 3, count 0 2006.252.08:11:09.54#ibcon#about to read 3, iclass 3, count 0 2006.252.08:11:09.56#ibcon#read 3, iclass 3, count 0 2006.252.08:11:09.56#ibcon#about to read 4, iclass 3, count 0 2006.252.08:11:09.56#ibcon#read 4, iclass 3, count 0 2006.252.08:11:09.56#ibcon#about to read 5, iclass 3, count 0 2006.252.08:11:09.56#ibcon#read 5, iclass 3, count 0 2006.252.08:11:09.56#ibcon#about to read 6, iclass 3, count 0 2006.252.08:11:09.56#ibcon#read 6, iclass 3, count 0 2006.252.08:11:09.56#ibcon#end of sib2, iclass 3, count 0 2006.252.08:11:09.56#ibcon#*mode == 0, iclass 3, count 0 2006.252.08:11:09.56#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.252.08:11:09.56#ibcon#[26=FRQ=06,772.99\r\n] 2006.252.08:11:09.56#ibcon#*before write, iclass 3, count 0 2006.252.08:11:09.56#ibcon#enter sib2, iclass 3, count 0 2006.252.08:11:09.56#ibcon#flushed, iclass 3, count 0 2006.252.08:11:09.56#ibcon#about to write, iclass 3, count 0 2006.252.08:11:09.56#ibcon#wrote, iclass 3, count 0 2006.252.08:11:09.56#ibcon#about to read 3, iclass 3, count 0 2006.252.08:11:09.61#ibcon#read 3, iclass 3, count 0 2006.252.08:11:09.61#ibcon#about to read 4, iclass 3, count 0 2006.252.08:11:09.61#ibcon#read 4, iclass 3, count 0 2006.252.08:11:09.61#ibcon#about to read 5, iclass 3, count 0 2006.252.08:11:09.61#ibcon#read 5, iclass 3, count 0 2006.252.08:11:09.61#ibcon#about to read 6, iclass 3, count 0 2006.252.08:11:09.61#ibcon#read 6, iclass 3, count 0 2006.252.08:11:09.61#ibcon#end of sib2, iclass 3, count 0 2006.252.08:11:09.61#ibcon#*after write, iclass 3, count 0 2006.252.08:11:09.61#ibcon#*before return 0, iclass 3, count 0 2006.252.08:11:09.61#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.252.08:11:09.61#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.252.08:11:09.61#ibcon#about to clear, iclass 3 cls_cnt 0 2006.252.08:11:09.61#ibcon#cleared, iclass 3 cls_cnt 0 2006.252.08:11:09.61$vc4f8/va=6,7 2006.252.08:11:09.61#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.252.08:11:09.61#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.252.08:11:09.61#ibcon#ireg 11 cls_cnt 2 2006.252.08:11:09.61#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.252.08:11:09.66#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.252.08:11:09.66#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.252.08:11:09.66#ibcon#enter wrdev, iclass 5, count 2 2006.252.08:11:09.66#ibcon#first serial, iclass 5, count 2 2006.252.08:11:09.66#ibcon#enter sib2, iclass 5, count 2 2006.252.08:11:09.66#ibcon#flushed, iclass 5, count 2 2006.252.08:11:09.66#ibcon#about to write, iclass 5, count 2 2006.252.08:11:09.66#ibcon#wrote, iclass 5, count 2 2006.252.08:11:09.66#ibcon#about to read 3, iclass 5, count 2 2006.252.08:11:09.68#ibcon#read 3, iclass 5, count 2 2006.252.08:11:09.68#ibcon#about to read 4, iclass 5, count 2 2006.252.08:11:09.68#ibcon#read 4, iclass 5, count 2 2006.252.08:11:09.68#ibcon#about to read 5, iclass 5, count 2 2006.252.08:11:09.68#ibcon#read 5, iclass 5, count 2 2006.252.08:11:09.68#ibcon#about to read 6, iclass 5, count 2 2006.252.08:11:09.68#ibcon#read 6, iclass 5, count 2 2006.252.08:11:09.68#ibcon#end of sib2, iclass 5, count 2 2006.252.08:11:09.68#ibcon#*mode == 0, iclass 5, count 2 2006.252.08:11:09.68#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.252.08:11:09.68#ibcon#[25=AT06-07\r\n] 2006.252.08:11:09.68#ibcon#*before write, iclass 5, count 2 2006.252.08:11:09.68#ibcon#enter sib2, iclass 5, count 2 2006.252.08:11:09.68#ibcon#flushed, iclass 5, count 2 2006.252.08:11:09.68#ibcon#about to write, iclass 5, count 2 2006.252.08:11:09.68#ibcon#wrote, iclass 5, count 2 2006.252.08:11:09.68#ibcon#about to read 3, iclass 5, count 2 2006.252.08:11:09.71#ibcon#read 3, iclass 5, count 2 2006.252.08:11:09.71#ibcon#about to read 4, iclass 5, count 2 2006.252.08:11:09.71#ibcon#read 4, iclass 5, count 2 2006.252.08:11:09.71#ibcon#about to read 5, iclass 5, count 2 2006.252.08:11:09.71#ibcon#read 5, iclass 5, count 2 2006.252.08:11:09.71#ibcon#about to read 6, iclass 5, count 2 2006.252.08:11:09.71#ibcon#read 6, iclass 5, count 2 2006.252.08:11:09.71#ibcon#end of sib2, iclass 5, count 2 2006.252.08:11:09.71#ibcon#*after write, iclass 5, count 2 2006.252.08:11:09.71#ibcon#*before return 0, iclass 5, count 2 2006.252.08:11:09.71#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.252.08:11:09.71#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.252.08:11:09.71#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.252.08:11:09.71#ibcon#ireg 7 cls_cnt 0 2006.252.08:11:09.71#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.252.08:11:09.83#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.252.08:11:09.83#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.252.08:11:09.83#ibcon#enter wrdev, iclass 5, count 0 2006.252.08:11:09.83#ibcon#first serial, iclass 5, count 0 2006.252.08:11:09.83#ibcon#enter sib2, iclass 5, count 0 2006.252.08:11:09.83#ibcon#flushed, iclass 5, count 0 2006.252.08:11:09.83#ibcon#about to write, iclass 5, count 0 2006.252.08:11:09.83#ibcon#wrote, iclass 5, count 0 2006.252.08:11:09.83#ibcon#about to read 3, iclass 5, count 0 2006.252.08:11:09.85#ibcon#read 3, iclass 5, count 0 2006.252.08:11:09.85#ibcon#about to read 4, iclass 5, count 0 2006.252.08:11:09.85#ibcon#read 4, iclass 5, count 0 2006.252.08:11:09.85#ibcon#about to read 5, iclass 5, count 0 2006.252.08:11:09.85#ibcon#read 5, iclass 5, count 0 2006.252.08:11:09.85#ibcon#about to read 6, iclass 5, count 0 2006.252.08:11:09.85#ibcon#read 6, iclass 5, count 0 2006.252.08:11:09.85#ibcon#end of sib2, iclass 5, count 0 2006.252.08:11:09.85#ibcon#*mode == 0, iclass 5, count 0 2006.252.08:11:09.85#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.252.08:11:09.85#ibcon#[25=USB\r\n] 2006.252.08:11:09.85#ibcon#*before write, iclass 5, count 0 2006.252.08:11:09.85#ibcon#enter sib2, iclass 5, count 0 2006.252.08:11:09.85#ibcon#flushed, iclass 5, count 0 2006.252.08:11:09.85#ibcon#about to write, iclass 5, count 0 2006.252.08:11:09.85#ibcon#wrote, iclass 5, count 0 2006.252.08:11:09.85#ibcon#about to read 3, iclass 5, count 0 2006.252.08:11:09.88#ibcon#read 3, iclass 5, count 0 2006.252.08:11:09.88#ibcon#about to read 4, iclass 5, count 0 2006.252.08:11:09.88#ibcon#read 4, iclass 5, count 0 2006.252.08:11:09.88#ibcon#about to read 5, iclass 5, count 0 2006.252.08:11:09.88#ibcon#read 5, iclass 5, count 0 2006.252.08:11:09.88#ibcon#about to read 6, iclass 5, count 0 2006.252.08:11:09.88#ibcon#read 6, iclass 5, count 0 2006.252.08:11:09.88#ibcon#end of sib2, iclass 5, count 0 2006.252.08:11:09.88#ibcon#*after write, iclass 5, count 0 2006.252.08:11:09.88#ibcon#*before return 0, iclass 5, count 0 2006.252.08:11:09.88#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.252.08:11:09.88#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.252.08:11:09.88#ibcon#about to clear, iclass 5 cls_cnt 0 2006.252.08:11:09.88#ibcon#cleared, iclass 5 cls_cnt 0 2006.252.08:11:09.88$vc4f8/valo=7,832.99 2006.252.08:11:09.88#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.252.08:11:09.88#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.252.08:11:09.88#ibcon#ireg 17 cls_cnt 0 2006.252.08:11:09.88#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.252.08:11:09.88#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.252.08:11:09.88#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.252.08:11:09.88#ibcon#enter wrdev, iclass 7, count 0 2006.252.08:11:09.88#ibcon#first serial, iclass 7, count 0 2006.252.08:11:09.88#ibcon#enter sib2, iclass 7, count 0 2006.252.08:11:09.88#ibcon#flushed, iclass 7, count 0 2006.252.08:11:09.88#ibcon#about to write, iclass 7, count 0 2006.252.08:11:09.88#ibcon#wrote, iclass 7, count 0 2006.252.08:11:09.88#ibcon#about to read 3, iclass 7, count 0 2006.252.08:11:09.90#ibcon#read 3, iclass 7, count 0 2006.252.08:11:09.90#ibcon#about to read 4, iclass 7, count 0 2006.252.08:11:09.90#ibcon#read 4, iclass 7, count 0 2006.252.08:11:09.90#ibcon#about to read 5, iclass 7, count 0 2006.252.08:11:09.90#ibcon#read 5, iclass 7, count 0 2006.252.08:11:09.90#ibcon#about to read 6, iclass 7, count 0 2006.252.08:11:09.90#ibcon#read 6, iclass 7, count 0 2006.252.08:11:09.90#ibcon#end of sib2, iclass 7, count 0 2006.252.08:11:09.90#ibcon#*mode == 0, iclass 7, count 0 2006.252.08:11:09.90#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.252.08:11:09.90#ibcon#[26=FRQ=07,832.99\r\n] 2006.252.08:11:09.90#ibcon#*before write, iclass 7, count 0 2006.252.08:11:09.90#ibcon#enter sib2, iclass 7, count 0 2006.252.08:11:09.90#ibcon#flushed, iclass 7, count 0 2006.252.08:11:09.90#ibcon#about to write, iclass 7, count 0 2006.252.08:11:09.90#ibcon#wrote, iclass 7, count 0 2006.252.08:11:09.90#ibcon#about to read 3, iclass 7, count 0 2006.252.08:11:09.94#ibcon#read 3, iclass 7, count 0 2006.252.08:11:09.94#ibcon#about to read 4, iclass 7, count 0 2006.252.08:11:09.94#ibcon#read 4, iclass 7, count 0 2006.252.08:11:09.94#ibcon#about to read 5, iclass 7, count 0 2006.252.08:11:09.94#ibcon#read 5, iclass 7, count 0 2006.252.08:11:09.94#ibcon#about to read 6, iclass 7, count 0 2006.252.08:11:09.94#ibcon#read 6, iclass 7, count 0 2006.252.08:11:09.94#ibcon#end of sib2, iclass 7, count 0 2006.252.08:11:09.94#ibcon#*after write, iclass 7, count 0 2006.252.08:11:09.94#ibcon#*before return 0, iclass 7, count 0 2006.252.08:11:09.94#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.252.08:11:09.94#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.252.08:11:09.94#ibcon#about to clear, iclass 7 cls_cnt 0 2006.252.08:11:09.94#ibcon#cleared, iclass 7 cls_cnt 0 2006.252.08:11:09.94$vc4f8/va=7,7 2006.252.08:11:09.94#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.252.08:11:09.94#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.252.08:11:09.94#ibcon#ireg 11 cls_cnt 2 2006.252.08:11:09.94#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.252.08:11:10.00#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.252.08:11:10.00#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.252.08:11:10.00#ibcon#enter wrdev, iclass 11, count 2 2006.252.08:11:10.00#ibcon#first serial, iclass 11, count 2 2006.252.08:11:10.00#ibcon#enter sib2, iclass 11, count 2 2006.252.08:11:10.00#ibcon#flushed, iclass 11, count 2 2006.252.08:11:10.00#ibcon#about to write, iclass 11, count 2 2006.252.08:11:10.00#ibcon#wrote, iclass 11, count 2 2006.252.08:11:10.00#ibcon#about to read 3, iclass 11, count 2 2006.252.08:11:10.02#ibcon#read 3, iclass 11, count 2 2006.252.08:11:10.02#ibcon#about to read 4, iclass 11, count 2 2006.252.08:11:10.02#ibcon#read 4, iclass 11, count 2 2006.252.08:11:10.02#ibcon#about to read 5, iclass 11, count 2 2006.252.08:11:10.02#ibcon#read 5, iclass 11, count 2 2006.252.08:11:10.02#ibcon#about to read 6, iclass 11, count 2 2006.252.08:11:10.02#ibcon#read 6, iclass 11, count 2 2006.252.08:11:10.02#ibcon#end of sib2, iclass 11, count 2 2006.252.08:11:10.02#ibcon#*mode == 0, iclass 11, count 2 2006.252.08:11:10.02#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.252.08:11:10.02#ibcon#[25=AT07-07\r\n] 2006.252.08:11:10.02#ibcon#*before write, iclass 11, count 2 2006.252.08:11:10.02#ibcon#enter sib2, iclass 11, count 2 2006.252.08:11:10.02#ibcon#flushed, iclass 11, count 2 2006.252.08:11:10.02#ibcon#about to write, iclass 11, count 2 2006.252.08:11:10.02#ibcon#wrote, iclass 11, count 2 2006.252.08:11:10.02#ibcon#about to read 3, iclass 11, count 2 2006.252.08:11:10.05#ibcon#read 3, iclass 11, count 2 2006.252.08:11:10.05#ibcon#about to read 4, iclass 11, count 2 2006.252.08:11:10.05#ibcon#read 4, iclass 11, count 2 2006.252.08:11:10.05#ibcon#about to read 5, iclass 11, count 2 2006.252.08:11:10.05#ibcon#read 5, iclass 11, count 2 2006.252.08:11:10.05#ibcon#about to read 6, iclass 11, count 2 2006.252.08:11:10.05#ibcon#read 6, iclass 11, count 2 2006.252.08:11:10.05#ibcon#end of sib2, iclass 11, count 2 2006.252.08:11:10.05#ibcon#*after write, iclass 11, count 2 2006.252.08:11:10.05#ibcon#*before return 0, iclass 11, count 2 2006.252.08:11:10.05#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.252.08:11:10.05#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.252.08:11:10.05#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.252.08:11:10.05#ibcon#ireg 7 cls_cnt 0 2006.252.08:11:10.05#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.252.08:11:10.17#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.252.08:11:10.17#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.252.08:11:10.17#ibcon#enter wrdev, iclass 11, count 0 2006.252.08:11:10.17#ibcon#first serial, iclass 11, count 0 2006.252.08:11:10.17#ibcon#enter sib2, iclass 11, count 0 2006.252.08:11:10.17#ibcon#flushed, iclass 11, count 0 2006.252.08:11:10.17#ibcon#about to write, iclass 11, count 0 2006.252.08:11:10.17#ibcon#wrote, iclass 11, count 0 2006.252.08:11:10.17#ibcon#about to read 3, iclass 11, count 0 2006.252.08:11:10.20#ibcon#read 3, iclass 11, count 0 2006.252.08:11:10.20#ibcon#about to read 4, iclass 11, count 0 2006.252.08:11:10.20#ibcon#read 4, iclass 11, count 0 2006.252.08:11:10.20#ibcon#about to read 5, iclass 11, count 0 2006.252.08:11:10.20#ibcon#read 5, iclass 11, count 0 2006.252.08:11:10.20#ibcon#about to read 6, iclass 11, count 0 2006.252.08:11:10.20#ibcon#read 6, iclass 11, count 0 2006.252.08:11:10.20#ibcon#end of sib2, iclass 11, count 0 2006.252.08:11:10.20#ibcon#*mode == 0, iclass 11, count 0 2006.252.08:11:10.20#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.252.08:11:10.20#ibcon#[25=USB\r\n] 2006.252.08:11:10.20#ibcon#*before write, iclass 11, count 0 2006.252.08:11:10.20#ibcon#enter sib2, iclass 11, count 0 2006.252.08:11:10.20#ibcon#flushed, iclass 11, count 0 2006.252.08:11:10.20#ibcon#about to write, iclass 11, count 0 2006.252.08:11:10.20#ibcon#wrote, iclass 11, count 0 2006.252.08:11:10.20#ibcon#about to read 3, iclass 11, count 0 2006.252.08:11:10.23#ibcon#read 3, iclass 11, count 0 2006.252.08:11:10.23#ibcon#about to read 4, iclass 11, count 0 2006.252.08:11:10.23#ibcon#read 4, iclass 11, count 0 2006.252.08:11:10.23#ibcon#about to read 5, iclass 11, count 0 2006.252.08:11:10.23#ibcon#read 5, iclass 11, count 0 2006.252.08:11:10.23#ibcon#about to read 6, iclass 11, count 0 2006.252.08:11:10.23#ibcon#read 6, iclass 11, count 0 2006.252.08:11:10.23#ibcon#end of sib2, iclass 11, count 0 2006.252.08:11:10.23#ibcon#*after write, iclass 11, count 0 2006.252.08:11:10.23#ibcon#*before return 0, iclass 11, count 0 2006.252.08:11:10.23#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.252.08:11:10.23#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.252.08:11:10.23#ibcon#about to clear, iclass 11 cls_cnt 0 2006.252.08:11:10.23#ibcon#cleared, iclass 11 cls_cnt 0 2006.252.08:11:10.23$vc4f8/valo=8,852.99 2006.252.08:11:10.23#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.252.08:11:10.23#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.252.08:11:10.23#ibcon#ireg 17 cls_cnt 0 2006.252.08:11:10.23#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.252.08:11:10.23#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.252.08:11:10.23#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.252.08:11:10.23#ibcon#enter wrdev, iclass 13, count 0 2006.252.08:11:10.23#ibcon#first serial, iclass 13, count 0 2006.252.08:11:10.23#ibcon#enter sib2, iclass 13, count 0 2006.252.08:11:10.23#ibcon#flushed, iclass 13, count 0 2006.252.08:11:10.23#ibcon#about to write, iclass 13, count 0 2006.252.08:11:10.23#ibcon#wrote, iclass 13, count 0 2006.252.08:11:10.23#ibcon#about to read 3, iclass 13, count 0 2006.252.08:11:10.25#ibcon#read 3, iclass 13, count 0 2006.252.08:11:10.25#ibcon#about to read 4, iclass 13, count 0 2006.252.08:11:10.25#ibcon#read 4, iclass 13, count 0 2006.252.08:11:10.25#ibcon#about to read 5, iclass 13, count 0 2006.252.08:11:10.25#ibcon#read 5, iclass 13, count 0 2006.252.08:11:10.25#ibcon#about to read 6, iclass 13, count 0 2006.252.08:11:10.25#ibcon#read 6, iclass 13, count 0 2006.252.08:11:10.25#ibcon#end of sib2, iclass 13, count 0 2006.252.08:11:10.25#ibcon#*mode == 0, iclass 13, count 0 2006.252.08:11:10.25#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.252.08:11:10.25#ibcon#[26=FRQ=08,852.99\r\n] 2006.252.08:11:10.25#ibcon#*before write, iclass 13, count 0 2006.252.08:11:10.25#ibcon#enter sib2, iclass 13, count 0 2006.252.08:11:10.25#ibcon#flushed, iclass 13, count 0 2006.252.08:11:10.25#ibcon#about to write, iclass 13, count 0 2006.252.08:11:10.25#ibcon#wrote, iclass 13, count 0 2006.252.08:11:10.25#ibcon#about to read 3, iclass 13, count 0 2006.252.08:11:10.29#ibcon#read 3, iclass 13, count 0 2006.252.08:11:10.29#ibcon#about to read 4, iclass 13, count 0 2006.252.08:11:10.29#ibcon#read 4, iclass 13, count 0 2006.252.08:11:10.29#ibcon#about to read 5, iclass 13, count 0 2006.252.08:11:10.29#ibcon#read 5, iclass 13, count 0 2006.252.08:11:10.29#ibcon#about to read 6, iclass 13, count 0 2006.252.08:11:10.29#ibcon#read 6, iclass 13, count 0 2006.252.08:11:10.29#ibcon#end of sib2, iclass 13, count 0 2006.252.08:11:10.29#ibcon#*after write, iclass 13, count 0 2006.252.08:11:10.29#ibcon#*before return 0, iclass 13, count 0 2006.252.08:11:10.29#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.252.08:11:10.29#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.252.08:11:10.29#ibcon#about to clear, iclass 13 cls_cnt 0 2006.252.08:11:10.29#ibcon#cleared, iclass 13 cls_cnt 0 2006.252.08:11:10.29$vc4f8/va=8,7 2006.252.08:11:10.29#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.252.08:11:10.29#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.252.08:11:10.29#ibcon#ireg 11 cls_cnt 2 2006.252.08:11:10.29#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.252.08:11:10.35#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.252.08:11:10.35#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.252.08:11:10.35#ibcon#enter wrdev, iclass 15, count 2 2006.252.08:11:10.35#ibcon#first serial, iclass 15, count 2 2006.252.08:11:10.35#ibcon#enter sib2, iclass 15, count 2 2006.252.08:11:10.35#ibcon#flushed, iclass 15, count 2 2006.252.08:11:10.35#ibcon#about to write, iclass 15, count 2 2006.252.08:11:10.35#ibcon#wrote, iclass 15, count 2 2006.252.08:11:10.35#ibcon#about to read 3, iclass 15, count 2 2006.252.08:11:10.37#ibcon#read 3, iclass 15, count 2 2006.252.08:11:10.37#ibcon#about to read 4, iclass 15, count 2 2006.252.08:11:10.37#ibcon#read 4, iclass 15, count 2 2006.252.08:11:10.37#ibcon#about to read 5, iclass 15, count 2 2006.252.08:11:10.37#ibcon#read 5, iclass 15, count 2 2006.252.08:11:10.37#ibcon#about to read 6, iclass 15, count 2 2006.252.08:11:10.37#ibcon#read 6, iclass 15, count 2 2006.252.08:11:10.37#ibcon#end of sib2, iclass 15, count 2 2006.252.08:11:10.37#ibcon#*mode == 0, iclass 15, count 2 2006.252.08:11:10.37#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.252.08:11:10.37#ibcon#[25=AT08-07\r\n] 2006.252.08:11:10.37#ibcon#*before write, iclass 15, count 2 2006.252.08:11:10.37#ibcon#enter sib2, iclass 15, count 2 2006.252.08:11:10.37#ibcon#flushed, iclass 15, count 2 2006.252.08:11:10.37#ibcon#about to write, iclass 15, count 2 2006.252.08:11:10.37#ibcon#wrote, iclass 15, count 2 2006.252.08:11:10.37#ibcon#about to read 3, iclass 15, count 2 2006.252.08:11:10.40#ibcon#read 3, iclass 15, count 2 2006.252.08:11:10.40#ibcon#about to read 4, iclass 15, count 2 2006.252.08:11:10.40#ibcon#read 4, iclass 15, count 2 2006.252.08:11:10.40#ibcon#about to read 5, iclass 15, count 2 2006.252.08:11:10.40#ibcon#read 5, iclass 15, count 2 2006.252.08:11:10.40#ibcon#about to read 6, iclass 15, count 2 2006.252.08:11:10.40#ibcon#read 6, iclass 15, count 2 2006.252.08:11:10.40#ibcon#end of sib2, iclass 15, count 2 2006.252.08:11:10.40#ibcon#*after write, iclass 15, count 2 2006.252.08:11:10.40#ibcon#*before return 0, iclass 15, count 2 2006.252.08:11:10.40#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.252.08:11:10.40#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.252.08:11:10.40#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.252.08:11:10.40#ibcon#ireg 7 cls_cnt 0 2006.252.08:11:10.40#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.252.08:11:10.52#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.252.08:11:10.52#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.252.08:11:10.52#ibcon#enter wrdev, iclass 15, count 0 2006.252.08:11:10.52#ibcon#first serial, iclass 15, count 0 2006.252.08:11:10.52#ibcon#enter sib2, iclass 15, count 0 2006.252.08:11:10.52#ibcon#flushed, iclass 15, count 0 2006.252.08:11:10.52#ibcon#about to write, iclass 15, count 0 2006.252.08:11:10.52#ibcon#wrote, iclass 15, count 0 2006.252.08:11:10.52#ibcon#about to read 3, iclass 15, count 0 2006.252.08:11:10.54#ibcon#read 3, iclass 15, count 0 2006.252.08:11:10.54#ibcon#about to read 4, iclass 15, count 0 2006.252.08:11:10.54#ibcon#read 4, iclass 15, count 0 2006.252.08:11:10.54#ibcon#about to read 5, iclass 15, count 0 2006.252.08:11:10.54#ibcon#read 5, iclass 15, count 0 2006.252.08:11:10.54#ibcon#about to read 6, iclass 15, count 0 2006.252.08:11:10.54#ibcon#read 6, iclass 15, count 0 2006.252.08:11:10.54#ibcon#end of sib2, iclass 15, count 0 2006.252.08:11:10.54#ibcon#*mode == 0, iclass 15, count 0 2006.252.08:11:10.54#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.252.08:11:10.54#ibcon#[25=USB\r\n] 2006.252.08:11:10.54#ibcon#*before write, iclass 15, count 0 2006.252.08:11:10.54#ibcon#enter sib2, iclass 15, count 0 2006.252.08:11:10.54#ibcon#flushed, iclass 15, count 0 2006.252.08:11:10.54#ibcon#about to write, iclass 15, count 0 2006.252.08:11:10.54#ibcon#wrote, iclass 15, count 0 2006.252.08:11:10.54#ibcon#about to read 3, iclass 15, count 0 2006.252.08:11:10.57#ibcon#read 3, iclass 15, count 0 2006.252.08:11:10.57#ibcon#about to read 4, iclass 15, count 0 2006.252.08:11:10.57#ibcon#read 4, iclass 15, count 0 2006.252.08:11:10.57#ibcon#about to read 5, iclass 15, count 0 2006.252.08:11:10.57#ibcon#read 5, iclass 15, count 0 2006.252.08:11:10.57#ibcon#about to read 6, iclass 15, count 0 2006.252.08:11:10.57#ibcon#read 6, iclass 15, count 0 2006.252.08:11:10.57#ibcon#end of sib2, iclass 15, count 0 2006.252.08:11:10.57#ibcon#*after write, iclass 15, count 0 2006.252.08:11:10.57#ibcon#*before return 0, iclass 15, count 0 2006.252.08:11:10.57#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.252.08:11:10.57#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.252.08:11:10.57#ibcon#about to clear, iclass 15 cls_cnt 0 2006.252.08:11:10.57#ibcon#cleared, iclass 15 cls_cnt 0 2006.252.08:11:10.57$vc4f8/vblo=1,632.99 2006.252.08:11:10.57#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.252.08:11:10.57#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.252.08:11:10.57#ibcon#ireg 17 cls_cnt 0 2006.252.08:11:10.57#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.252.08:11:10.57#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.252.08:11:10.57#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.252.08:11:10.57#ibcon#enter wrdev, iclass 17, count 0 2006.252.08:11:10.57#ibcon#first serial, iclass 17, count 0 2006.252.08:11:10.57#ibcon#enter sib2, iclass 17, count 0 2006.252.08:11:10.57#ibcon#flushed, iclass 17, count 0 2006.252.08:11:10.57#ibcon#about to write, iclass 17, count 0 2006.252.08:11:10.57#ibcon#wrote, iclass 17, count 0 2006.252.08:11:10.57#ibcon#about to read 3, iclass 17, count 0 2006.252.08:11:10.59#ibcon#read 3, iclass 17, count 0 2006.252.08:11:10.59#ibcon#about to read 4, iclass 17, count 0 2006.252.08:11:10.59#ibcon#read 4, iclass 17, count 0 2006.252.08:11:10.59#ibcon#about to read 5, iclass 17, count 0 2006.252.08:11:10.59#ibcon#read 5, iclass 17, count 0 2006.252.08:11:10.59#ibcon#about to read 6, iclass 17, count 0 2006.252.08:11:10.59#ibcon#read 6, iclass 17, count 0 2006.252.08:11:10.59#ibcon#end of sib2, iclass 17, count 0 2006.252.08:11:10.59#ibcon#*mode == 0, iclass 17, count 0 2006.252.08:11:10.59#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.252.08:11:10.59#ibcon#[28=FRQ=01,632.99\r\n] 2006.252.08:11:10.59#ibcon#*before write, iclass 17, count 0 2006.252.08:11:10.59#ibcon#enter sib2, iclass 17, count 0 2006.252.08:11:10.59#ibcon#flushed, iclass 17, count 0 2006.252.08:11:10.59#ibcon#about to write, iclass 17, count 0 2006.252.08:11:10.59#ibcon#wrote, iclass 17, count 0 2006.252.08:11:10.59#ibcon#about to read 3, iclass 17, count 0 2006.252.08:11:10.63#ibcon#read 3, iclass 17, count 0 2006.252.08:11:10.63#ibcon#about to read 4, iclass 17, count 0 2006.252.08:11:10.63#ibcon#read 4, iclass 17, count 0 2006.252.08:11:10.63#ibcon#about to read 5, iclass 17, count 0 2006.252.08:11:10.63#ibcon#read 5, iclass 17, count 0 2006.252.08:11:10.63#ibcon#about to read 6, iclass 17, count 0 2006.252.08:11:10.63#ibcon#read 6, iclass 17, count 0 2006.252.08:11:10.63#ibcon#end of sib2, iclass 17, count 0 2006.252.08:11:10.63#ibcon#*after write, iclass 17, count 0 2006.252.08:11:10.63#ibcon#*before return 0, iclass 17, count 0 2006.252.08:11:10.63#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.252.08:11:10.63#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.252.08:11:10.63#ibcon#about to clear, iclass 17 cls_cnt 0 2006.252.08:11:10.63#ibcon#cleared, iclass 17 cls_cnt 0 2006.252.08:11:10.63$vc4f8/vb=1,4 2006.252.08:11:10.63#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.252.08:11:10.63#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.252.08:11:10.63#ibcon#ireg 11 cls_cnt 2 2006.252.08:11:10.63#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.252.08:11:10.63#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.252.08:11:10.63#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.252.08:11:10.63#ibcon#enter wrdev, iclass 19, count 2 2006.252.08:11:10.63#ibcon#first serial, iclass 19, count 2 2006.252.08:11:10.63#ibcon#enter sib2, iclass 19, count 2 2006.252.08:11:10.63#ibcon#flushed, iclass 19, count 2 2006.252.08:11:10.63#ibcon#about to write, iclass 19, count 2 2006.252.08:11:10.63#ibcon#wrote, iclass 19, count 2 2006.252.08:11:10.63#ibcon#about to read 3, iclass 19, count 2 2006.252.08:11:10.65#ibcon#read 3, iclass 19, count 2 2006.252.08:11:10.65#ibcon#about to read 4, iclass 19, count 2 2006.252.08:11:10.65#ibcon#read 4, iclass 19, count 2 2006.252.08:11:10.65#ibcon#about to read 5, iclass 19, count 2 2006.252.08:11:10.65#ibcon#read 5, iclass 19, count 2 2006.252.08:11:10.65#ibcon#about to read 6, iclass 19, count 2 2006.252.08:11:10.65#ibcon#read 6, iclass 19, count 2 2006.252.08:11:10.65#ibcon#end of sib2, iclass 19, count 2 2006.252.08:11:10.65#ibcon#*mode == 0, iclass 19, count 2 2006.252.08:11:10.65#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.252.08:11:10.65#ibcon#[27=AT01-04\r\n] 2006.252.08:11:10.65#ibcon#*before write, iclass 19, count 2 2006.252.08:11:10.65#ibcon#enter sib2, iclass 19, count 2 2006.252.08:11:10.65#ibcon#flushed, iclass 19, count 2 2006.252.08:11:10.65#ibcon#about to write, iclass 19, count 2 2006.252.08:11:10.65#ibcon#wrote, iclass 19, count 2 2006.252.08:11:10.65#ibcon#about to read 3, iclass 19, count 2 2006.252.08:11:10.68#ibcon#read 3, iclass 19, count 2 2006.252.08:11:10.68#ibcon#about to read 4, iclass 19, count 2 2006.252.08:11:10.68#ibcon#read 4, iclass 19, count 2 2006.252.08:11:10.68#ibcon#about to read 5, iclass 19, count 2 2006.252.08:11:10.68#ibcon#read 5, iclass 19, count 2 2006.252.08:11:10.68#ibcon#about to read 6, iclass 19, count 2 2006.252.08:11:10.68#ibcon#read 6, iclass 19, count 2 2006.252.08:11:10.68#ibcon#end of sib2, iclass 19, count 2 2006.252.08:11:10.68#ibcon#*after write, iclass 19, count 2 2006.252.08:11:10.68#ibcon#*before return 0, iclass 19, count 2 2006.252.08:11:10.68#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.252.08:11:10.68#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.252.08:11:10.68#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.252.08:11:10.68#ibcon#ireg 7 cls_cnt 0 2006.252.08:11:10.68#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.252.08:11:10.80#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.252.08:11:10.80#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.252.08:11:10.80#ibcon#enter wrdev, iclass 19, count 0 2006.252.08:11:10.80#ibcon#first serial, iclass 19, count 0 2006.252.08:11:10.80#ibcon#enter sib2, iclass 19, count 0 2006.252.08:11:10.80#ibcon#flushed, iclass 19, count 0 2006.252.08:11:10.80#ibcon#about to write, iclass 19, count 0 2006.252.08:11:10.80#ibcon#wrote, iclass 19, count 0 2006.252.08:11:10.80#ibcon#about to read 3, iclass 19, count 0 2006.252.08:11:10.82#ibcon#read 3, iclass 19, count 0 2006.252.08:11:10.82#ibcon#about to read 4, iclass 19, count 0 2006.252.08:11:10.82#ibcon#read 4, iclass 19, count 0 2006.252.08:11:10.82#ibcon#about to read 5, iclass 19, count 0 2006.252.08:11:10.82#ibcon#read 5, iclass 19, count 0 2006.252.08:11:10.82#ibcon#about to read 6, iclass 19, count 0 2006.252.08:11:10.82#ibcon#read 6, iclass 19, count 0 2006.252.08:11:10.82#ibcon#end of sib2, iclass 19, count 0 2006.252.08:11:10.82#ibcon#*mode == 0, iclass 19, count 0 2006.252.08:11:10.82#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.252.08:11:10.82#ibcon#[27=USB\r\n] 2006.252.08:11:10.82#ibcon#*before write, iclass 19, count 0 2006.252.08:11:10.82#ibcon#enter sib2, iclass 19, count 0 2006.252.08:11:10.82#ibcon#flushed, iclass 19, count 0 2006.252.08:11:10.82#ibcon#about to write, iclass 19, count 0 2006.252.08:11:10.82#ibcon#wrote, iclass 19, count 0 2006.252.08:11:10.82#ibcon#about to read 3, iclass 19, count 0 2006.252.08:11:10.85#ibcon#read 3, iclass 19, count 0 2006.252.08:11:10.85#ibcon#about to read 4, iclass 19, count 0 2006.252.08:11:10.85#ibcon#read 4, iclass 19, count 0 2006.252.08:11:10.85#ibcon#about to read 5, iclass 19, count 0 2006.252.08:11:10.85#ibcon#read 5, iclass 19, count 0 2006.252.08:11:10.85#ibcon#about to read 6, iclass 19, count 0 2006.252.08:11:10.85#ibcon#read 6, iclass 19, count 0 2006.252.08:11:10.85#ibcon#end of sib2, iclass 19, count 0 2006.252.08:11:10.85#ibcon#*after write, iclass 19, count 0 2006.252.08:11:10.85#ibcon#*before return 0, iclass 19, count 0 2006.252.08:11:10.85#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.252.08:11:10.85#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.252.08:11:10.85#ibcon#about to clear, iclass 19 cls_cnt 0 2006.252.08:11:10.85#ibcon#cleared, iclass 19 cls_cnt 0 2006.252.08:11:10.85$vc4f8/vblo=2,640.99 2006.252.08:11:10.85#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.252.08:11:10.85#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.252.08:11:10.85#ibcon#ireg 17 cls_cnt 0 2006.252.08:11:10.85#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.252.08:11:10.85#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.252.08:11:10.85#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.252.08:11:10.85#ibcon#enter wrdev, iclass 21, count 0 2006.252.08:11:10.85#ibcon#first serial, iclass 21, count 0 2006.252.08:11:10.85#ibcon#enter sib2, iclass 21, count 0 2006.252.08:11:10.85#ibcon#flushed, iclass 21, count 0 2006.252.08:11:10.85#ibcon#about to write, iclass 21, count 0 2006.252.08:11:10.85#ibcon#wrote, iclass 21, count 0 2006.252.08:11:10.85#ibcon#about to read 3, iclass 21, count 0 2006.252.08:11:10.87#ibcon#read 3, iclass 21, count 0 2006.252.08:11:10.87#ibcon#about to read 4, iclass 21, count 0 2006.252.08:11:10.87#ibcon#read 4, iclass 21, count 0 2006.252.08:11:10.87#ibcon#about to read 5, iclass 21, count 0 2006.252.08:11:10.87#ibcon#read 5, iclass 21, count 0 2006.252.08:11:10.87#ibcon#about to read 6, iclass 21, count 0 2006.252.08:11:10.87#ibcon#read 6, iclass 21, count 0 2006.252.08:11:10.87#ibcon#end of sib2, iclass 21, count 0 2006.252.08:11:10.87#ibcon#*mode == 0, iclass 21, count 0 2006.252.08:11:10.87#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.252.08:11:10.87#ibcon#[28=FRQ=02,640.99\r\n] 2006.252.08:11:10.87#ibcon#*before write, iclass 21, count 0 2006.252.08:11:10.87#ibcon#enter sib2, iclass 21, count 0 2006.252.08:11:10.87#ibcon#flushed, iclass 21, count 0 2006.252.08:11:10.87#ibcon#about to write, iclass 21, count 0 2006.252.08:11:10.87#ibcon#wrote, iclass 21, count 0 2006.252.08:11:10.87#ibcon#about to read 3, iclass 21, count 0 2006.252.08:11:10.92#ibcon#read 3, iclass 21, count 0 2006.252.08:11:10.92#ibcon#about to read 4, iclass 21, count 0 2006.252.08:11:10.92#ibcon#read 4, iclass 21, count 0 2006.252.08:11:10.92#ibcon#about to read 5, iclass 21, count 0 2006.252.08:11:10.92#ibcon#read 5, iclass 21, count 0 2006.252.08:11:10.92#ibcon#about to read 6, iclass 21, count 0 2006.252.08:11:10.92#ibcon#read 6, iclass 21, count 0 2006.252.08:11:10.92#ibcon#end of sib2, iclass 21, count 0 2006.252.08:11:10.92#ibcon#*after write, iclass 21, count 0 2006.252.08:11:10.92#ibcon#*before return 0, iclass 21, count 0 2006.252.08:11:10.92#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.252.08:11:10.92#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.252.08:11:10.92#ibcon#about to clear, iclass 21 cls_cnt 0 2006.252.08:11:10.92#ibcon#cleared, iclass 21 cls_cnt 0 2006.252.08:11:10.92$vc4f8/vb=2,5 2006.252.08:11:10.92#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.252.08:11:10.92#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.252.08:11:10.92#ibcon#ireg 11 cls_cnt 2 2006.252.08:11:10.92#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.252.08:11:10.97#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.252.08:11:10.97#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.252.08:11:10.97#ibcon#enter wrdev, iclass 23, count 2 2006.252.08:11:10.97#ibcon#first serial, iclass 23, count 2 2006.252.08:11:10.97#ibcon#enter sib2, iclass 23, count 2 2006.252.08:11:10.97#ibcon#flushed, iclass 23, count 2 2006.252.08:11:10.97#ibcon#about to write, iclass 23, count 2 2006.252.08:11:10.97#ibcon#wrote, iclass 23, count 2 2006.252.08:11:10.97#ibcon#about to read 3, iclass 23, count 2 2006.252.08:11:10.99#ibcon#read 3, iclass 23, count 2 2006.252.08:11:10.99#ibcon#about to read 4, iclass 23, count 2 2006.252.08:11:10.99#ibcon#read 4, iclass 23, count 2 2006.252.08:11:10.99#ibcon#about to read 5, iclass 23, count 2 2006.252.08:11:10.99#ibcon#read 5, iclass 23, count 2 2006.252.08:11:10.99#ibcon#about to read 6, iclass 23, count 2 2006.252.08:11:10.99#ibcon#read 6, iclass 23, count 2 2006.252.08:11:10.99#ibcon#end of sib2, iclass 23, count 2 2006.252.08:11:10.99#ibcon#*mode == 0, iclass 23, count 2 2006.252.08:11:10.99#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.252.08:11:10.99#ibcon#[27=AT02-05\r\n] 2006.252.08:11:10.99#ibcon#*before write, iclass 23, count 2 2006.252.08:11:10.99#ibcon#enter sib2, iclass 23, count 2 2006.252.08:11:10.99#ibcon#flushed, iclass 23, count 2 2006.252.08:11:10.99#ibcon#about to write, iclass 23, count 2 2006.252.08:11:10.99#ibcon#wrote, iclass 23, count 2 2006.252.08:11:10.99#ibcon#about to read 3, iclass 23, count 2 2006.252.08:11:11.02#ibcon#read 3, iclass 23, count 2 2006.252.08:11:11.02#ibcon#about to read 4, iclass 23, count 2 2006.252.08:11:11.02#ibcon#read 4, iclass 23, count 2 2006.252.08:11:11.02#ibcon#about to read 5, iclass 23, count 2 2006.252.08:11:11.02#ibcon#read 5, iclass 23, count 2 2006.252.08:11:11.02#ibcon#about to read 6, iclass 23, count 2 2006.252.08:11:11.02#ibcon#read 6, iclass 23, count 2 2006.252.08:11:11.02#ibcon#end of sib2, iclass 23, count 2 2006.252.08:11:11.02#ibcon#*after write, iclass 23, count 2 2006.252.08:11:11.02#ibcon#*before return 0, iclass 23, count 2 2006.252.08:11:11.02#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.252.08:11:11.02#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.252.08:11:11.02#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.252.08:11:11.02#ibcon#ireg 7 cls_cnt 0 2006.252.08:11:11.02#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.252.08:11:11.14#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.252.08:11:11.14#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.252.08:11:11.14#ibcon#enter wrdev, iclass 23, count 0 2006.252.08:11:11.14#ibcon#first serial, iclass 23, count 0 2006.252.08:11:11.14#ibcon#enter sib2, iclass 23, count 0 2006.252.08:11:11.14#ibcon#flushed, iclass 23, count 0 2006.252.08:11:11.14#ibcon#about to write, iclass 23, count 0 2006.252.08:11:11.14#ibcon#wrote, iclass 23, count 0 2006.252.08:11:11.14#ibcon#about to read 3, iclass 23, count 0 2006.252.08:11:11.16#ibcon#read 3, iclass 23, count 0 2006.252.08:11:11.16#ibcon#about to read 4, iclass 23, count 0 2006.252.08:11:11.16#ibcon#read 4, iclass 23, count 0 2006.252.08:11:11.16#ibcon#about to read 5, iclass 23, count 0 2006.252.08:11:11.16#ibcon#read 5, iclass 23, count 0 2006.252.08:11:11.16#ibcon#about to read 6, iclass 23, count 0 2006.252.08:11:11.16#ibcon#read 6, iclass 23, count 0 2006.252.08:11:11.16#ibcon#end of sib2, iclass 23, count 0 2006.252.08:11:11.16#ibcon#*mode == 0, iclass 23, count 0 2006.252.08:11:11.16#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.252.08:11:11.16#ibcon#[27=USB\r\n] 2006.252.08:11:11.16#ibcon#*before write, iclass 23, count 0 2006.252.08:11:11.16#ibcon#enter sib2, iclass 23, count 0 2006.252.08:11:11.16#ibcon#flushed, iclass 23, count 0 2006.252.08:11:11.16#ibcon#about to write, iclass 23, count 0 2006.252.08:11:11.16#ibcon#wrote, iclass 23, count 0 2006.252.08:11:11.16#ibcon#about to read 3, iclass 23, count 0 2006.252.08:11:11.19#ibcon#read 3, iclass 23, count 0 2006.252.08:11:11.19#ibcon#about to read 4, iclass 23, count 0 2006.252.08:11:11.19#ibcon#read 4, iclass 23, count 0 2006.252.08:11:11.19#ibcon#about to read 5, iclass 23, count 0 2006.252.08:11:11.19#ibcon#read 5, iclass 23, count 0 2006.252.08:11:11.19#ibcon#about to read 6, iclass 23, count 0 2006.252.08:11:11.19#ibcon#read 6, iclass 23, count 0 2006.252.08:11:11.19#ibcon#end of sib2, iclass 23, count 0 2006.252.08:11:11.19#ibcon#*after write, iclass 23, count 0 2006.252.08:11:11.19#ibcon#*before return 0, iclass 23, count 0 2006.252.08:11:11.19#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.252.08:11:11.19#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.252.08:11:11.19#ibcon#about to clear, iclass 23 cls_cnt 0 2006.252.08:11:11.19#ibcon#cleared, iclass 23 cls_cnt 0 2006.252.08:11:11.19$vc4f8/vblo=3,656.99 2006.252.08:11:11.19#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.252.08:11:11.19#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.252.08:11:11.19#ibcon#ireg 17 cls_cnt 0 2006.252.08:11:11.19#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.252.08:11:11.19#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.252.08:11:11.19#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.252.08:11:11.19#ibcon#enter wrdev, iclass 25, count 0 2006.252.08:11:11.19#ibcon#first serial, iclass 25, count 0 2006.252.08:11:11.19#ibcon#enter sib2, iclass 25, count 0 2006.252.08:11:11.19#ibcon#flushed, iclass 25, count 0 2006.252.08:11:11.19#ibcon#about to write, iclass 25, count 0 2006.252.08:11:11.19#ibcon#wrote, iclass 25, count 0 2006.252.08:11:11.19#ibcon#about to read 3, iclass 25, count 0 2006.252.08:11:11.21#ibcon#read 3, iclass 25, count 0 2006.252.08:11:11.21#ibcon#about to read 4, iclass 25, count 0 2006.252.08:11:11.21#ibcon#read 4, iclass 25, count 0 2006.252.08:11:11.21#ibcon#about to read 5, iclass 25, count 0 2006.252.08:11:11.21#ibcon#read 5, iclass 25, count 0 2006.252.08:11:11.21#ibcon#about to read 6, iclass 25, count 0 2006.252.08:11:11.21#ibcon#read 6, iclass 25, count 0 2006.252.08:11:11.21#ibcon#end of sib2, iclass 25, count 0 2006.252.08:11:11.21#ibcon#*mode == 0, iclass 25, count 0 2006.252.08:11:11.21#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.252.08:11:11.21#ibcon#[28=FRQ=03,656.99\r\n] 2006.252.08:11:11.21#ibcon#*before write, iclass 25, count 0 2006.252.08:11:11.21#ibcon#enter sib2, iclass 25, count 0 2006.252.08:11:11.21#ibcon#flushed, iclass 25, count 0 2006.252.08:11:11.21#ibcon#about to write, iclass 25, count 0 2006.252.08:11:11.21#ibcon#wrote, iclass 25, count 0 2006.252.08:11:11.21#ibcon#about to read 3, iclass 25, count 0 2006.252.08:11:11.25#ibcon#read 3, iclass 25, count 0 2006.252.08:11:11.25#ibcon#about to read 4, iclass 25, count 0 2006.252.08:11:11.25#ibcon#read 4, iclass 25, count 0 2006.252.08:11:11.25#ibcon#about to read 5, iclass 25, count 0 2006.252.08:11:11.25#ibcon#read 5, iclass 25, count 0 2006.252.08:11:11.25#ibcon#about to read 6, iclass 25, count 0 2006.252.08:11:11.25#ibcon#read 6, iclass 25, count 0 2006.252.08:11:11.25#ibcon#end of sib2, iclass 25, count 0 2006.252.08:11:11.25#ibcon#*after write, iclass 25, count 0 2006.252.08:11:11.25#ibcon#*before return 0, iclass 25, count 0 2006.252.08:11:11.25#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.252.08:11:11.25#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.252.08:11:11.25#ibcon#about to clear, iclass 25 cls_cnt 0 2006.252.08:11:11.25#ibcon#cleared, iclass 25 cls_cnt 0 2006.252.08:11:11.25$vc4f8/vb=3,4 2006.252.08:11:11.25#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.252.08:11:11.25#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.252.08:11:11.25#ibcon#ireg 11 cls_cnt 2 2006.252.08:11:11.25#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.252.08:11:11.31#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.252.08:11:11.31#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.252.08:11:11.31#ibcon#enter wrdev, iclass 27, count 2 2006.252.08:11:11.31#ibcon#first serial, iclass 27, count 2 2006.252.08:11:11.31#ibcon#enter sib2, iclass 27, count 2 2006.252.08:11:11.31#ibcon#flushed, iclass 27, count 2 2006.252.08:11:11.31#ibcon#about to write, iclass 27, count 2 2006.252.08:11:11.31#ibcon#wrote, iclass 27, count 2 2006.252.08:11:11.31#ibcon#about to read 3, iclass 27, count 2 2006.252.08:11:11.33#ibcon#read 3, iclass 27, count 2 2006.252.08:11:11.33#ibcon#about to read 4, iclass 27, count 2 2006.252.08:11:11.33#ibcon#read 4, iclass 27, count 2 2006.252.08:11:11.33#ibcon#about to read 5, iclass 27, count 2 2006.252.08:11:11.33#ibcon#read 5, iclass 27, count 2 2006.252.08:11:11.33#ibcon#about to read 6, iclass 27, count 2 2006.252.08:11:11.33#ibcon#read 6, iclass 27, count 2 2006.252.08:11:11.33#ibcon#end of sib2, iclass 27, count 2 2006.252.08:11:11.33#ibcon#*mode == 0, iclass 27, count 2 2006.252.08:11:11.33#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.252.08:11:11.33#ibcon#[27=AT03-04\r\n] 2006.252.08:11:11.33#ibcon#*before write, iclass 27, count 2 2006.252.08:11:11.33#ibcon#enter sib2, iclass 27, count 2 2006.252.08:11:11.33#ibcon#flushed, iclass 27, count 2 2006.252.08:11:11.33#ibcon#about to write, iclass 27, count 2 2006.252.08:11:11.33#ibcon#wrote, iclass 27, count 2 2006.252.08:11:11.33#ibcon#about to read 3, iclass 27, count 2 2006.252.08:11:11.36#ibcon#read 3, iclass 27, count 2 2006.252.08:11:11.36#ibcon#about to read 4, iclass 27, count 2 2006.252.08:11:11.36#ibcon#read 4, iclass 27, count 2 2006.252.08:11:11.36#ibcon#about to read 5, iclass 27, count 2 2006.252.08:11:11.36#ibcon#read 5, iclass 27, count 2 2006.252.08:11:11.36#ibcon#about to read 6, iclass 27, count 2 2006.252.08:11:11.36#ibcon#read 6, iclass 27, count 2 2006.252.08:11:11.36#ibcon#end of sib2, iclass 27, count 2 2006.252.08:11:11.36#ibcon#*after write, iclass 27, count 2 2006.252.08:11:11.36#ibcon#*before return 0, iclass 27, count 2 2006.252.08:11:11.36#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.252.08:11:11.36#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.252.08:11:11.36#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.252.08:11:11.36#ibcon#ireg 7 cls_cnt 0 2006.252.08:11:11.36#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.252.08:11:11.48#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.252.08:11:11.48#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.252.08:11:11.48#ibcon#enter wrdev, iclass 27, count 0 2006.252.08:11:11.48#ibcon#first serial, iclass 27, count 0 2006.252.08:11:11.48#ibcon#enter sib2, iclass 27, count 0 2006.252.08:11:11.48#ibcon#flushed, iclass 27, count 0 2006.252.08:11:11.48#ibcon#about to write, iclass 27, count 0 2006.252.08:11:11.48#ibcon#wrote, iclass 27, count 0 2006.252.08:11:11.48#ibcon#about to read 3, iclass 27, count 0 2006.252.08:11:11.50#ibcon#read 3, iclass 27, count 0 2006.252.08:11:11.50#ibcon#about to read 4, iclass 27, count 0 2006.252.08:11:11.50#ibcon#read 4, iclass 27, count 0 2006.252.08:11:11.50#ibcon#about to read 5, iclass 27, count 0 2006.252.08:11:11.50#ibcon#read 5, iclass 27, count 0 2006.252.08:11:11.50#ibcon#about to read 6, iclass 27, count 0 2006.252.08:11:11.50#ibcon#read 6, iclass 27, count 0 2006.252.08:11:11.50#ibcon#end of sib2, iclass 27, count 0 2006.252.08:11:11.50#ibcon#*mode == 0, iclass 27, count 0 2006.252.08:11:11.50#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.252.08:11:11.50#ibcon#[27=USB\r\n] 2006.252.08:11:11.50#ibcon#*before write, iclass 27, count 0 2006.252.08:11:11.50#ibcon#enter sib2, iclass 27, count 0 2006.252.08:11:11.50#ibcon#flushed, iclass 27, count 0 2006.252.08:11:11.50#ibcon#about to write, iclass 27, count 0 2006.252.08:11:11.50#ibcon#wrote, iclass 27, count 0 2006.252.08:11:11.50#ibcon#about to read 3, iclass 27, count 0 2006.252.08:11:11.53#ibcon#read 3, iclass 27, count 0 2006.252.08:11:11.53#ibcon#about to read 4, iclass 27, count 0 2006.252.08:11:11.53#ibcon#read 4, iclass 27, count 0 2006.252.08:11:11.53#ibcon#about to read 5, iclass 27, count 0 2006.252.08:11:11.53#ibcon#read 5, iclass 27, count 0 2006.252.08:11:11.53#ibcon#about to read 6, iclass 27, count 0 2006.252.08:11:11.53#ibcon#read 6, iclass 27, count 0 2006.252.08:11:11.53#ibcon#end of sib2, iclass 27, count 0 2006.252.08:11:11.53#ibcon#*after write, iclass 27, count 0 2006.252.08:11:11.53#ibcon#*before return 0, iclass 27, count 0 2006.252.08:11:11.53#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.252.08:11:11.53#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.252.08:11:11.53#ibcon#about to clear, iclass 27 cls_cnt 0 2006.252.08:11:11.53#ibcon#cleared, iclass 27 cls_cnt 0 2006.252.08:11:11.53$vc4f8/vblo=4,712.99 2006.252.08:11:11.53#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.252.08:11:11.53#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.252.08:11:11.53#ibcon#ireg 17 cls_cnt 0 2006.252.08:11:11.53#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.252.08:11:11.53#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.252.08:11:11.53#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.252.08:11:11.53#ibcon#enter wrdev, iclass 29, count 0 2006.252.08:11:11.53#ibcon#first serial, iclass 29, count 0 2006.252.08:11:11.53#ibcon#enter sib2, iclass 29, count 0 2006.252.08:11:11.53#ibcon#flushed, iclass 29, count 0 2006.252.08:11:11.53#ibcon#about to write, iclass 29, count 0 2006.252.08:11:11.53#ibcon#wrote, iclass 29, count 0 2006.252.08:11:11.53#ibcon#about to read 3, iclass 29, count 0 2006.252.08:11:11.55#ibcon#read 3, iclass 29, count 0 2006.252.08:11:11.55#ibcon#about to read 4, iclass 29, count 0 2006.252.08:11:11.55#ibcon#read 4, iclass 29, count 0 2006.252.08:11:11.55#ibcon#about to read 5, iclass 29, count 0 2006.252.08:11:11.55#ibcon#read 5, iclass 29, count 0 2006.252.08:11:11.55#ibcon#about to read 6, iclass 29, count 0 2006.252.08:11:11.55#ibcon#read 6, iclass 29, count 0 2006.252.08:11:11.55#ibcon#end of sib2, iclass 29, count 0 2006.252.08:11:11.55#ibcon#*mode == 0, iclass 29, count 0 2006.252.08:11:11.55#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.252.08:11:11.55#ibcon#[28=FRQ=04,712.99\r\n] 2006.252.08:11:11.55#ibcon#*before write, iclass 29, count 0 2006.252.08:11:11.55#ibcon#enter sib2, iclass 29, count 0 2006.252.08:11:11.55#ibcon#flushed, iclass 29, count 0 2006.252.08:11:11.55#ibcon#about to write, iclass 29, count 0 2006.252.08:11:11.55#ibcon#wrote, iclass 29, count 0 2006.252.08:11:11.55#ibcon#about to read 3, iclass 29, count 0 2006.252.08:11:11.59#ibcon#read 3, iclass 29, count 0 2006.252.08:11:11.59#ibcon#about to read 4, iclass 29, count 0 2006.252.08:11:11.59#ibcon#read 4, iclass 29, count 0 2006.252.08:11:11.59#ibcon#about to read 5, iclass 29, count 0 2006.252.08:11:11.59#ibcon#read 5, iclass 29, count 0 2006.252.08:11:11.59#ibcon#about to read 6, iclass 29, count 0 2006.252.08:11:11.59#ibcon#read 6, iclass 29, count 0 2006.252.08:11:11.59#ibcon#end of sib2, iclass 29, count 0 2006.252.08:11:11.59#ibcon#*after write, iclass 29, count 0 2006.252.08:11:11.59#ibcon#*before return 0, iclass 29, count 0 2006.252.08:11:11.59#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.252.08:11:11.59#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.252.08:11:11.59#ibcon#about to clear, iclass 29 cls_cnt 0 2006.252.08:11:11.59#ibcon#cleared, iclass 29 cls_cnt 0 2006.252.08:11:11.59$vc4f8/vb=4,4 2006.252.08:11:11.59#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.252.08:11:11.59#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.252.08:11:11.59#ibcon#ireg 11 cls_cnt 2 2006.252.08:11:11.59#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.252.08:11:11.65#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.252.08:11:11.65#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.252.08:11:11.65#ibcon#enter wrdev, iclass 31, count 2 2006.252.08:11:11.65#ibcon#first serial, iclass 31, count 2 2006.252.08:11:11.65#ibcon#enter sib2, iclass 31, count 2 2006.252.08:11:11.65#ibcon#flushed, iclass 31, count 2 2006.252.08:11:11.65#ibcon#about to write, iclass 31, count 2 2006.252.08:11:11.65#ibcon#wrote, iclass 31, count 2 2006.252.08:11:11.65#ibcon#about to read 3, iclass 31, count 2 2006.252.08:11:11.67#ibcon#read 3, iclass 31, count 2 2006.252.08:11:11.67#ibcon#about to read 4, iclass 31, count 2 2006.252.08:11:11.67#ibcon#read 4, iclass 31, count 2 2006.252.08:11:11.67#ibcon#about to read 5, iclass 31, count 2 2006.252.08:11:11.67#ibcon#read 5, iclass 31, count 2 2006.252.08:11:11.67#ibcon#about to read 6, iclass 31, count 2 2006.252.08:11:11.67#ibcon#read 6, iclass 31, count 2 2006.252.08:11:11.67#ibcon#end of sib2, iclass 31, count 2 2006.252.08:11:11.67#ibcon#*mode == 0, iclass 31, count 2 2006.252.08:11:11.67#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.252.08:11:11.67#ibcon#[27=AT04-04\r\n] 2006.252.08:11:11.67#ibcon#*before write, iclass 31, count 2 2006.252.08:11:11.67#ibcon#enter sib2, iclass 31, count 2 2006.252.08:11:11.67#ibcon#flushed, iclass 31, count 2 2006.252.08:11:11.67#ibcon#about to write, iclass 31, count 2 2006.252.08:11:11.67#ibcon#wrote, iclass 31, count 2 2006.252.08:11:11.67#ibcon#about to read 3, iclass 31, count 2 2006.252.08:11:11.71#ibcon#read 3, iclass 31, count 2 2006.252.08:11:11.71#ibcon#about to read 4, iclass 31, count 2 2006.252.08:11:11.71#ibcon#read 4, iclass 31, count 2 2006.252.08:11:11.71#ibcon#about to read 5, iclass 31, count 2 2006.252.08:11:11.71#ibcon#read 5, iclass 31, count 2 2006.252.08:11:11.71#ibcon#about to read 6, iclass 31, count 2 2006.252.08:11:11.71#ibcon#read 6, iclass 31, count 2 2006.252.08:11:11.71#ibcon#end of sib2, iclass 31, count 2 2006.252.08:11:11.71#ibcon#*after write, iclass 31, count 2 2006.252.08:11:11.71#ibcon#*before return 0, iclass 31, count 2 2006.252.08:11:11.71#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.252.08:11:11.71#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.252.08:11:11.71#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.252.08:11:11.71#ibcon#ireg 7 cls_cnt 0 2006.252.08:11:11.71#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.252.08:11:11.83#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.252.08:11:11.83#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.252.08:11:11.83#ibcon#enter wrdev, iclass 31, count 0 2006.252.08:11:11.83#ibcon#first serial, iclass 31, count 0 2006.252.08:11:11.83#ibcon#enter sib2, iclass 31, count 0 2006.252.08:11:11.83#ibcon#flushed, iclass 31, count 0 2006.252.08:11:11.83#ibcon#about to write, iclass 31, count 0 2006.252.08:11:11.83#ibcon#wrote, iclass 31, count 0 2006.252.08:11:11.83#ibcon#about to read 3, iclass 31, count 0 2006.252.08:11:11.85#ibcon#read 3, iclass 31, count 0 2006.252.08:11:11.85#ibcon#about to read 4, iclass 31, count 0 2006.252.08:11:11.85#ibcon#read 4, iclass 31, count 0 2006.252.08:11:11.85#ibcon#about to read 5, iclass 31, count 0 2006.252.08:11:11.85#ibcon#read 5, iclass 31, count 0 2006.252.08:11:11.85#ibcon#about to read 6, iclass 31, count 0 2006.252.08:11:11.85#ibcon#read 6, iclass 31, count 0 2006.252.08:11:11.85#ibcon#end of sib2, iclass 31, count 0 2006.252.08:11:11.85#ibcon#*mode == 0, iclass 31, count 0 2006.252.08:11:11.85#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.252.08:11:11.85#ibcon#[27=USB\r\n] 2006.252.08:11:11.85#ibcon#*before write, iclass 31, count 0 2006.252.08:11:11.85#ibcon#enter sib2, iclass 31, count 0 2006.252.08:11:11.85#ibcon#flushed, iclass 31, count 0 2006.252.08:11:11.85#ibcon#about to write, iclass 31, count 0 2006.252.08:11:11.85#ibcon#wrote, iclass 31, count 0 2006.252.08:11:11.85#ibcon#about to read 3, iclass 31, count 0 2006.252.08:11:11.88#ibcon#read 3, iclass 31, count 0 2006.252.08:11:11.88#ibcon#about to read 4, iclass 31, count 0 2006.252.08:11:11.88#ibcon#read 4, iclass 31, count 0 2006.252.08:11:11.88#ibcon#about to read 5, iclass 31, count 0 2006.252.08:11:11.88#ibcon#read 5, iclass 31, count 0 2006.252.08:11:11.88#ibcon#about to read 6, iclass 31, count 0 2006.252.08:11:11.88#ibcon#read 6, iclass 31, count 0 2006.252.08:11:11.88#ibcon#end of sib2, iclass 31, count 0 2006.252.08:11:11.88#ibcon#*after write, iclass 31, count 0 2006.252.08:11:11.88#ibcon#*before return 0, iclass 31, count 0 2006.252.08:11:11.88#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.252.08:11:11.88#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.252.08:11:11.88#ibcon#about to clear, iclass 31 cls_cnt 0 2006.252.08:11:11.88#ibcon#cleared, iclass 31 cls_cnt 0 2006.252.08:11:11.88$vc4f8/vblo=5,744.99 2006.252.08:11:11.88#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.252.08:11:11.88#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.252.08:11:11.88#ibcon#ireg 17 cls_cnt 0 2006.252.08:11:11.88#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.252.08:11:11.88#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.252.08:11:11.88#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.252.08:11:11.88#ibcon#enter wrdev, iclass 33, count 0 2006.252.08:11:11.88#ibcon#first serial, iclass 33, count 0 2006.252.08:11:11.88#ibcon#enter sib2, iclass 33, count 0 2006.252.08:11:11.88#ibcon#flushed, iclass 33, count 0 2006.252.08:11:11.88#ibcon#about to write, iclass 33, count 0 2006.252.08:11:11.88#ibcon#wrote, iclass 33, count 0 2006.252.08:11:11.88#ibcon#about to read 3, iclass 33, count 0 2006.252.08:11:11.90#ibcon#read 3, iclass 33, count 0 2006.252.08:11:11.90#ibcon#about to read 4, iclass 33, count 0 2006.252.08:11:11.90#ibcon#read 4, iclass 33, count 0 2006.252.08:11:11.90#ibcon#about to read 5, iclass 33, count 0 2006.252.08:11:11.90#ibcon#read 5, iclass 33, count 0 2006.252.08:11:11.90#ibcon#about to read 6, iclass 33, count 0 2006.252.08:11:11.90#ibcon#read 6, iclass 33, count 0 2006.252.08:11:11.90#ibcon#end of sib2, iclass 33, count 0 2006.252.08:11:11.90#ibcon#*mode == 0, iclass 33, count 0 2006.252.08:11:11.90#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.252.08:11:11.90#ibcon#[28=FRQ=05,744.99\r\n] 2006.252.08:11:11.90#ibcon#*before write, iclass 33, count 0 2006.252.08:11:11.90#ibcon#enter sib2, iclass 33, count 0 2006.252.08:11:11.90#ibcon#flushed, iclass 33, count 0 2006.252.08:11:11.90#ibcon#about to write, iclass 33, count 0 2006.252.08:11:11.90#ibcon#wrote, iclass 33, count 0 2006.252.08:11:11.90#ibcon#about to read 3, iclass 33, count 0 2006.252.08:11:11.94#ibcon#read 3, iclass 33, count 0 2006.252.08:11:11.94#ibcon#about to read 4, iclass 33, count 0 2006.252.08:11:11.94#ibcon#read 4, iclass 33, count 0 2006.252.08:11:11.94#ibcon#about to read 5, iclass 33, count 0 2006.252.08:11:11.94#ibcon#read 5, iclass 33, count 0 2006.252.08:11:11.94#ibcon#about to read 6, iclass 33, count 0 2006.252.08:11:11.94#ibcon#read 6, iclass 33, count 0 2006.252.08:11:11.94#ibcon#end of sib2, iclass 33, count 0 2006.252.08:11:11.94#ibcon#*after write, iclass 33, count 0 2006.252.08:11:11.94#ibcon#*before return 0, iclass 33, count 0 2006.252.08:11:11.94#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.252.08:11:11.94#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.252.08:11:11.94#ibcon#about to clear, iclass 33 cls_cnt 0 2006.252.08:11:11.94#ibcon#cleared, iclass 33 cls_cnt 0 2006.252.08:11:11.94$vc4f8/vb=5,4 2006.252.08:11:11.94#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.252.08:11:11.94#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.252.08:11:11.94#ibcon#ireg 11 cls_cnt 2 2006.252.08:11:11.94#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.252.08:11:12.00#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.252.08:11:12.00#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.252.08:11:12.00#ibcon#enter wrdev, iclass 35, count 2 2006.252.08:11:12.00#ibcon#first serial, iclass 35, count 2 2006.252.08:11:12.00#ibcon#enter sib2, iclass 35, count 2 2006.252.08:11:12.00#ibcon#flushed, iclass 35, count 2 2006.252.08:11:12.00#ibcon#about to write, iclass 35, count 2 2006.252.08:11:12.00#ibcon#wrote, iclass 35, count 2 2006.252.08:11:12.00#ibcon#about to read 3, iclass 35, count 2 2006.252.08:11:12.02#ibcon#read 3, iclass 35, count 2 2006.252.08:11:12.02#ibcon#about to read 4, iclass 35, count 2 2006.252.08:11:12.02#ibcon#read 4, iclass 35, count 2 2006.252.08:11:12.02#ibcon#about to read 5, iclass 35, count 2 2006.252.08:11:12.02#ibcon#read 5, iclass 35, count 2 2006.252.08:11:12.02#ibcon#about to read 6, iclass 35, count 2 2006.252.08:11:12.02#ibcon#read 6, iclass 35, count 2 2006.252.08:11:12.02#ibcon#end of sib2, iclass 35, count 2 2006.252.08:11:12.02#ibcon#*mode == 0, iclass 35, count 2 2006.252.08:11:12.02#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.252.08:11:12.02#ibcon#[27=AT05-04\r\n] 2006.252.08:11:12.02#ibcon#*before write, iclass 35, count 2 2006.252.08:11:12.02#ibcon#enter sib2, iclass 35, count 2 2006.252.08:11:12.02#ibcon#flushed, iclass 35, count 2 2006.252.08:11:12.02#ibcon#about to write, iclass 35, count 2 2006.252.08:11:12.02#ibcon#wrote, iclass 35, count 2 2006.252.08:11:12.02#ibcon#about to read 3, iclass 35, count 2 2006.252.08:11:12.05#ibcon#read 3, iclass 35, count 2 2006.252.08:11:12.05#ibcon#about to read 4, iclass 35, count 2 2006.252.08:11:12.05#ibcon#read 4, iclass 35, count 2 2006.252.08:11:12.05#ibcon#about to read 5, iclass 35, count 2 2006.252.08:11:12.05#ibcon#read 5, iclass 35, count 2 2006.252.08:11:12.05#ibcon#about to read 6, iclass 35, count 2 2006.252.08:11:12.05#ibcon#read 6, iclass 35, count 2 2006.252.08:11:12.05#ibcon#end of sib2, iclass 35, count 2 2006.252.08:11:12.05#ibcon#*after write, iclass 35, count 2 2006.252.08:11:12.05#ibcon#*before return 0, iclass 35, count 2 2006.252.08:11:12.05#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.252.08:11:12.05#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.252.08:11:12.05#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.252.08:11:12.05#ibcon#ireg 7 cls_cnt 0 2006.252.08:11:12.05#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.252.08:11:12.17#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.252.08:11:12.17#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.252.08:11:12.17#ibcon#enter wrdev, iclass 35, count 0 2006.252.08:11:12.17#ibcon#first serial, iclass 35, count 0 2006.252.08:11:12.17#ibcon#enter sib2, iclass 35, count 0 2006.252.08:11:12.17#ibcon#flushed, iclass 35, count 0 2006.252.08:11:12.17#ibcon#about to write, iclass 35, count 0 2006.252.08:11:12.17#ibcon#wrote, iclass 35, count 0 2006.252.08:11:12.17#ibcon#about to read 3, iclass 35, count 0 2006.252.08:11:12.19#ibcon#read 3, iclass 35, count 0 2006.252.08:11:12.19#ibcon#about to read 4, iclass 35, count 0 2006.252.08:11:12.19#ibcon#read 4, iclass 35, count 0 2006.252.08:11:12.19#ibcon#about to read 5, iclass 35, count 0 2006.252.08:11:12.19#ibcon#read 5, iclass 35, count 0 2006.252.08:11:12.19#ibcon#about to read 6, iclass 35, count 0 2006.252.08:11:12.19#ibcon#read 6, iclass 35, count 0 2006.252.08:11:12.19#ibcon#end of sib2, iclass 35, count 0 2006.252.08:11:12.19#ibcon#*mode == 0, iclass 35, count 0 2006.252.08:11:12.19#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.252.08:11:12.19#ibcon#[27=USB\r\n] 2006.252.08:11:12.19#ibcon#*before write, iclass 35, count 0 2006.252.08:11:12.19#ibcon#enter sib2, iclass 35, count 0 2006.252.08:11:12.19#ibcon#flushed, iclass 35, count 0 2006.252.08:11:12.19#ibcon#about to write, iclass 35, count 0 2006.252.08:11:12.19#ibcon#wrote, iclass 35, count 0 2006.252.08:11:12.19#ibcon#about to read 3, iclass 35, count 0 2006.252.08:11:12.22#ibcon#read 3, iclass 35, count 0 2006.252.08:11:12.22#ibcon#about to read 4, iclass 35, count 0 2006.252.08:11:12.22#ibcon#read 4, iclass 35, count 0 2006.252.08:11:12.22#ibcon#about to read 5, iclass 35, count 0 2006.252.08:11:12.22#ibcon#read 5, iclass 35, count 0 2006.252.08:11:12.22#ibcon#about to read 6, iclass 35, count 0 2006.252.08:11:12.22#ibcon#read 6, iclass 35, count 0 2006.252.08:11:12.22#ibcon#end of sib2, iclass 35, count 0 2006.252.08:11:12.22#ibcon#*after write, iclass 35, count 0 2006.252.08:11:12.22#ibcon#*before return 0, iclass 35, count 0 2006.252.08:11:12.22#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.252.08:11:12.22#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.252.08:11:12.22#ibcon#about to clear, iclass 35 cls_cnt 0 2006.252.08:11:12.22#ibcon#cleared, iclass 35 cls_cnt 0 2006.252.08:11:12.22$vc4f8/vblo=6,752.99 2006.252.08:11:12.22#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.252.08:11:12.22#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.252.08:11:12.22#ibcon#ireg 17 cls_cnt 0 2006.252.08:11:12.22#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.252.08:11:12.22#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.252.08:11:12.22#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.252.08:11:12.22#ibcon#enter wrdev, iclass 37, count 0 2006.252.08:11:12.22#ibcon#first serial, iclass 37, count 0 2006.252.08:11:12.22#ibcon#enter sib2, iclass 37, count 0 2006.252.08:11:12.22#ibcon#flushed, iclass 37, count 0 2006.252.08:11:12.22#ibcon#about to write, iclass 37, count 0 2006.252.08:11:12.22#ibcon#wrote, iclass 37, count 0 2006.252.08:11:12.22#ibcon#about to read 3, iclass 37, count 0 2006.252.08:11:12.24#ibcon#read 3, iclass 37, count 0 2006.252.08:11:12.24#ibcon#about to read 4, iclass 37, count 0 2006.252.08:11:12.24#ibcon#read 4, iclass 37, count 0 2006.252.08:11:12.24#ibcon#about to read 5, iclass 37, count 0 2006.252.08:11:12.24#ibcon#read 5, iclass 37, count 0 2006.252.08:11:12.24#ibcon#about to read 6, iclass 37, count 0 2006.252.08:11:12.24#ibcon#read 6, iclass 37, count 0 2006.252.08:11:12.24#ibcon#end of sib2, iclass 37, count 0 2006.252.08:11:12.24#ibcon#*mode == 0, iclass 37, count 0 2006.252.08:11:12.24#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.252.08:11:12.24#ibcon#[28=FRQ=06,752.99\r\n] 2006.252.08:11:12.24#ibcon#*before write, iclass 37, count 0 2006.252.08:11:12.24#ibcon#enter sib2, iclass 37, count 0 2006.252.08:11:12.24#ibcon#flushed, iclass 37, count 0 2006.252.08:11:12.24#ibcon#about to write, iclass 37, count 0 2006.252.08:11:12.24#ibcon#wrote, iclass 37, count 0 2006.252.08:11:12.24#ibcon#about to read 3, iclass 37, count 0 2006.252.08:11:12.28#ibcon#read 3, iclass 37, count 0 2006.252.08:11:12.28#ibcon#about to read 4, iclass 37, count 0 2006.252.08:11:12.28#ibcon#read 4, iclass 37, count 0 2006.252.08:11:12.28#ibcon#about to read 5, iclass 37, count 0 2006.252.08:11:12.28#ibcon#read 5, iclass 37, count 0 2006.252.08:11:12.28#ibcon#about to read 6, iclass 37, count 0 2006.252.08:11:12.28#ibcon#read 6, iclass 37, count 0 2006.252.08:11:12.28#ibcon#end of sib2, iclass 37, count 0 2006.252.08:11:12.28#ibcon#*after write, iclass 37, count 0 2006.252.08:11:12.28#ibcon#*before return 0, iclass 37, count 0 2006.252.08:11:12.28#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.252.08:11:12.28#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.252.08:11:12.28#ibcon#about to clear, iclass 37 cls_cnt 0 2006.252.08:11:12.28#ibcon#cleared, iclass 37 cls_cnt 0 2006.252.08:11:12.28$vc4f8/vb=6,4 2006.252.08:11:12.28#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.252.08:11:12.28#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.252.08:11:12.28#ibcon#ireg 11 cls_cnt 2 2006.252.08:11:12.28#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.252.08:11:12.34#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.252.08:11:12.34#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.252.08:11:12.34#ibcon#enter wrdev, iclass 39, count 2 2006.252.08:11:12.34#ibcon#first serial, iclass 39, count 2 2006.252.08:11:12.34#ibcon#enter sib2, iclass 39, count 2 2006.252.08:11:12.34#ibcon#flushed, iclass 39, count 2 2006.252.08:11:12.34#ibcon#about to write, iclass 39, count 2 2006.252.08:11:12.34#ibcon#wrote, iclass 39, count 2 2006.252.08:11:12.34#ibcon#about to read 3, iclass 39, count 2 2006.252.08:11:12.36#ibcon#read 3, iclass 39, count 2 2006.252.08:11:12.36#ibcon#about to read 4, iclass 39, count 2 2006.252.08:11:12.36#ibcon#read 4, iclass 39, count 2 2006.252.08:11:12.36#ibcon#about to read 5, iclass 39, count 2 2006.252.08:11:12.36#ibcon#read 5, iclass 39, count 2 2006.252.08:11:12.36#ibcon#about to read 6, iclass 39, count 2 2006.252.08:11:12.36#ibcon#read 6, iclass 39, count 2 2006.252.08:11:12.36#ibcon#end of sib2, iclass 39, count 2 2006.252.08:11:12.36#ibcon#*mode == 0, iclass 39, count 2 2006.252.08:11:12.36#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.252.08:11:12.36#ibcon#[27=AT06-04\r\n] 2006.252.08:11:12.36#ibcon#*before write, iclass 39, count 2 2006.252.08:11:12.36#ibcon#enter sib2, iclass 39, count 2 2006.252.08:11:12.36#ibcon#flushed, iclass 39, count 2 2006.252.08:11:12.36#ibcon#about to write, iclass 39, count 2 2006.252.08:11:12.36#ibcon#wrote, iclass 39, count 2 2006.252.08:11:12.36#ibcon#about to read 3, iclass 39, count 2 2006.252.08:11:12.39#ibcon#read 3, iclass 39, count 2 2006.252.08:11:12.39#ibcon#about to read 4, iclass 39, count 2 2006.252.08:11:12.39#ibcon#read 4, iclass 39, count 2 2006.252.08:11:12.39#ibcon#about to read 5, iclass 39, count 2 2006.252.08:11:12.39#ibcon#read 5, iclass 39, count 2 2006.252.08:11:12.39#ibcon#about to read 6, iclass 39, count 2 2006.252.08:11:12.39#ibcon#read 6, iclass 39, count 2 2006.252.08:11:12.39#ibcon#end of sib2, iclass 39, count 2 2006.252.08:11:12.39#ibcon#*after write, iclass 39, count 2 2006.252.08:11:12.39#ibcon#*before return 0, iclass 39, count 2 2006.252.08:11:12.39#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.252.08:11:12.39#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.252.08:11:12.39#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.252.08:11:12.39#ibcon#ireg 7 cls_cnt 0 2006.252.08:11:12.39#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.252.08:11:12.51#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.252.08:11:12.51#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.252.08:11:12.51#ibcon#enter wrdev, iclass 39, count 0 2006.252.08:11:12.51#ibcon#first serial, iclass 39, count 0 2006.252.08:11:12.51#ibcon#enter sib2, iclass 39, count 0 2006.252.08:11:12.51#ibcon#flushed, iclass 39, count 0 2006.252.08:11:12.51#ibcon#about to write, iclass 39, count 0 2006.252.08:11:12.51#ibcon#wrote, iclass 39, count 0 2006.252.08:11:12.51#ibcon#about to read 3, iclass 39, count 0 2006.252.08:11:12.53#ibcon#read 3, iclass 39, count 0 2006.252.08:11:12.53#ibcon#about to read 4, iclass 39, count 0 2006.252.08:11:12.53#ibcon#read 4, iclass 39, count 0 2006.252.08:11:12.53#ibcon#about to read 5, iclass 39, count 0 2006.252.08:11:12.53#ibcon#read 5, iclass 39, count 0 2006.252.08:11:12.53#ibcon#about to read 6, iclass 39, count 0 2006.252.08:11:12.53#ibcon#read 6, iclass 39, count 0 2006.252.08:11:12.53#ibcon#end of sib2, iclass 39, count 0 2006.252.08:11:12.53#ibcon#*mode == 0, iclass 39, count 0 2006.252.08:11:12.53#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.252.08:11:12.53#ibcon#[27=USB\r\n] 2006.252.08:11:12.53#ibcon#*before write, iclass 39, count 0 2006.252.08:11:12.53#ibcon#enter sib2, iclass 39, count 0 2006.252.08:11:12.53#ibcon#flushed, iclass 39, count 0 2006.252.08:11:12.53#ibcon#about to write, iclass 39, count 0 2006.252.08:11:12.53#ibcon#wrote, iclass 39, count 0 2006.252.08:11:12.53#ibcon#about to read 3, iclass 39, count 0 2006.252.08:11:12.56#ibcon#read 3, iclass 39, count 0 2006.252.08:11:12.56#ibcon#about to read 4, iclass 39, count 0 2006.252.08:11:12.56#ibcon#read 4, iclass 39, count 0 2006.252.08:11:12.56#ibcon#about to read 5, iclass 39, count 0 2006.252.08:11:12.56#ibcon#read 5, iclass 39, count 0 2006.252.08:11:12.56#ibcon#about to read 6, iclass 39, count 0 2006.252.08:11:12.56#ibcon#read 6, iclass 39, count 0 2006.252.08:11:12.56#ibcon#end of sib2, iclass 39, count 0 2006.252.08:11:12.56#ibcon#*after write, iclass 39, count 0 2006.252.08:11:12.56#ibcon#*before return 0, iclass 39, count 0 2006.252.08:11:12.56#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.252.08:11:12.56#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.252.08:11:12.56#ibcon#about to clear, iclass 39 cls_cnt 0 2006.252.08:11:12.56#ibcon#cleared, iclass 39 cls_cnt 0 2006.252.08:11:12.56$vc4f8/vabw=wide 2006.252.08:11:12.56#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.252.08:11:12.56#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.252.08:11:12.56#ibcon#ireg 8 cls_cnt 0 2006.252.08:11:12.56#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.252.08:11:12.56#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.252.08:11:12.56#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.252.08:11:12.56#ibcon#enter wrdev, iclass 3, count 0 2006.252.08:11:12.56#ibcon#first serial, iclass 3, count 0 2006.252.08:11:12.56#ibcon#enter sib2, iclass 3, count 0 2006.252.08:11:12.56#ibcon#flushed, iclass 3, count 0 2006.252.08:11:12.56#ibcon#about to write, iclass 3, count 0 2006.252.08:11:12.56#ibcon#wrote, iclass 3, count 0 2006.252.08:11:12.56#ibcon#about to read 3, iclass 3, count 0 2006.252.08:11:12.58#ibcon#read 3, iclass 3, count 0 2006.252.08:11:12.58#ibcon#about to read 4, iclass 3, count 0 2006.252.08:11:12.58#ibcon#read 4, iclass 3, count 0 2006.252.08:11:12.58#ibcon#about to read 5, iclass 3, count 0 2006.252.08:11:12.58#ibcon#read 5, iclass 3, count 0 2006.252.08:11:12.58#ibcon#about to read 6, iclass 3, count 0 2006.252.08:11:12.58#ibcon#read 6, iclass 3, count 0 2006.252.08:11:12.58#ibcon#end of sib2, iclass 3, count 0 2006.252.08:11:12.58#ibcon#*mode == 0, iclass 3, count 0 2006.252.08:11:12.58#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.252.08:11:12.58#ibcon#[25=BW32\r\n] 2006.252.08:11:12.58#ibcon#*before write, iclass 3, count 0 2006.252.08:11:12.58#ibcon#enter sib2, iclass 3, count 0 2006.252.08:11:12.58#ibcon#flushed, iclass 3, count 0 2006.252.08:11:12.58#ibcon#about to write, iclass 3, count 0 2006.252.08:11:12.58#ibcon#wrote, iclass 3, count 0 2006.252.08:11:12.58#ibcon#about to read 3, iclass 3, count 0 2006.252.08:11:12.61#ibcon#read 3, iclass 3, count 0 2006.252.08:11:12.61#ibcon#about to read 4, iclass 3, count 0 2006.252.08:11:12.61#ibcon#read 4, iclass 3, count 0 2006.252.08:11:12.61#ibcon#about to read 5, iclass 3, count 0 2006.252.08:11:12.61#ibcon#read 5, iclass 3, count 0 2006.252.08:11:12.61#ibcon#about to read 6, iclass 3, count 0 2006.252.08:11:12.61#ibcon#read 6, iclass 3, count 0 2006.252.08:11:12.61#ibcon#end of sib2, iclass 3, count 0 2006.252.08:11:12.61#ibcon#*after write, iclass 3, count 0 2006.252.08:11:12.61#ibcon#*before return 0, iclass 3, count 0 2006.252.08:11:12.61#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.252.08:11:12.61#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.252.08:11:12.61#ibcon#about to clear, iclass 3 cls_cnt 0 2006.252.08:11:12.61#ibcon#cleared, iclass 3 cls_cnt 0 2006.252.08:11:12.61$vc4f8/vbbw=wide 2006.252.08:11:12.61#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.252.08:11:12.61#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.252.08:11:12.61#ibcon#ireg 8 cls_cnt 0 2006.252.08:11:12.61#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.252.08:11:12.68#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.252.08:11:12.68#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.252.08:11:12.68#ibcon#enter wrdev, iclass 5, count 0 2006.252.08:11:12.68#ibcon#first serial, iclass 5, count 0 2006.252.08:11:12.68#ibcon#enter sib2, iclass 5, count 0 2006.252.08:11:12.68#ibcon#flushed, iclass 5, count 0 2006.252.08:11:12.68#ibcon#about to write, iclass 5, count 0 2006.252.08:11:12.68#ibcon#wrote, iclass 5, count 0 2006.252.08:11:12.68#ibcon#about to read 3, iclass 5, count 0 2006.252.08:11:12.70#ibcon#read 3, iclass 5, count 0 2006.252.08:11:12.70#ibcon#about to read 4, iclass 5, count 0 2006.252.08:11:12.70#ibcon#read 4, iclass 5, count 0 2006.252.08:11:12.70#ibcon#about to read 5, iclass 5, count 0 2006.252.08:11:12.70#ibcon#read 5, iclass 5, count 0 2006.252.08:11:12.70#ibcon#about to read 6, iclass 5, count 0 2006.252.08:11:12.70#ibcon#read 6, iclass 5, count 0 2006.252.08:11:12.70#ibcon#end of sib2, iclass 5, count 0 2006.252.08:11:12.70#ibcon#*mode == 0, iclass 5, count 0 2006.252.08:11:12.70#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.252.08:11:12.70#ibcon#[27=BW32\r\n] 2006.252.08:11:12.70#ibcon#*before write, iclass 5, count 0 2006.252.08:11:12.70#ibcon#enter sib2, iclass 5, count 0 2006.252.08:11:12.70#ibcon#flushed, iclass 5, count 0 2006.252.08:11:12.70#ibcon#about to write, iclass 5, count 0 2006.252.08:11:12.70#ibcon#wrote, iclass 5, count 0 2006.252.08:11:12.70#ibcon#about to read 3, iclass 5, count 0 2006.252.08:11:12.73#ibcon#read 3, iclass 5, count 0 2006.252.08:11:12.73#ibcon#about to read 4, iclass 5, count 0 2006.252.08:11:12.73#ibcon#read 4, iclass 5, count 0 2006.252.08:11:12.73#ibcon#about to read 5, iclass 5, count 0 2006.252.08:11:12.73#ibcon#read 5, iclass 5, count 0 2006.252.08:11:12.73#ibcon#about to read 6, iclass 5, count 0 2006.252.08:11:12.73#ibcon#read 6, iclass 5, count 0 2006.252.08:11:12.73#ibcon#end of sib2, iclass 5, count 0 2006.252.08:11:12.73#ibcon#*after write, iclass 5, count 0 2006.252.08:11:12.73#ibcon#*before return 0, iclass 5, count 0 2006.252.08:11:12.73#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.252.08:11:12.73#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.252.08:11:12.73#ibcon#about to clear, iclass 5 cls_cnt 0 2006.252.08:11:12.73#ibcon#cleared, iclass 5 cls_cnt 0 2006.252.08:11:12.73$4f8m12a/ifd4f 2006.252.08:11:12.73$ifd4f/lo= 2006.252.08:11:12.73$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.252.08:11:12.73$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.252.08:11:12.73$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.252.08:11:12.73$ifd4f/patch= 2006.252.08:11:12.73$ifd4f/patch=lo1,a1,a2,a3,a4 2006.252.08:11:12.73$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.252.08:11:12.73$ifd4f/patch=lo3,a5,a6,a7,a8 2006.252.08:11:12.73$4f8m12a/"form=m,16.000,1:2 2006.252.08:11:12.73$4f8m12a/"tpicd 2006.252.08:11:12.73$4f8m12a/echo=off 2006.252.08:11:12.73$4f8m12a/xlog=off 2006.252.08:11:12.73:!2006.252.08:11:50 2006.252.08:11:30.13#trakl#Source acquired 2006.252.08:11:31.13#flagr#flagr/antenna,acquired 2006.252.08:11:50.00:preob 2006.252.08:11:50.14/onsource/TRACKING 2006.252.08:11:50.14:!2006.252.08:12:00 2006.252.08:12:00.00:data_valid=on 2006.252.08:12:00.00:midob 2006.252.08:12:01.14/onsource/TRACKING 2006.252.08:12:01.14/wx/27.31,1011.1,90 2006.252.08:12:01.33/cable/+6.4122E-03 2006.252.08:12:02.42/va/01,08,usb,yes,34,36 2006.252.08:12:02.42/va/02,07,usb,yes,34,36 2006.252.08:12:02.42/va/03,06,usb,yes,36,37 2006.252.08:12:02.42/va/04,07,usb,yes,35,38 2006.252.08:12:02.42/va/05,07,usb,yes,39,41 2006.252.08:12:02.42/va/06,07,usb,yes,34,34 2006.252.08:12:02.42/va/07,07,usb,yes,34,33 2006.252.08:12:02.42/va/08,07,usb,yes,36,36 2006.252.08:12:02.65/valo/01,532.99,yes,locked 2006.252.08:12:02.65/valo/02,572.99,yes,locked 2006.252.08:12:02.65/valo/03,672.99,yes,locked 2006.252.08:12:02.65/valo/04,832.99,yes,locked 2006.252.08:12:02.65/valo/05,652.99,yes,locked 2006.252.08:12:02.65/valo/06,772.99,yes,locked 2006.252.08:12:02.65/valo/07,832.99,yes,locked 2006.252.08:12:02.65/valo/08,852.99,yes,locked 2006.252.08:12:03.74/vb/01,04,usb,yes,31,30 2006.252.08:12:03.74/vb/02,05,usb,yes,29,30 2006.252.08:12:03.74/vb/03,04,usb,yes,29,33 2006.252.08:12:03.74/vb/04,04,usb,yes,30,30 2006.252.08:12:03.74/vb/05,04,usb,yes,28,33 2006.252.08:12:03.74/vb/06,04,usb,yes,29,32 2006.252.08:12:03.74/vb/07,04,usb,yes,32,31 2006.252.08:12:03.74/vb/08,04,usb,yes,29,32 2006.252.08:12:03.97/vblo/01,632.99,yes,locked 2006.252.08:12:03.97/vblo/02,640.99,yes,locked 2006.252.08:12:03.97/vblo/03,656.99,yes,locked 2006.252.08:12:03.97/vblo/04,712.99,yes,locked 2006.252.08:12:03.97/vblo/05,744.99,yes,locked 2006.252.08:12:03.97/vblo/06,752.99,yes,locked 2006.252.08:12:03.97/vblo/07,734.99,yes,locked 2006.252.08:12:03.97/vblo/08,744.99,yes,locked 2006.252.08:12:04.12/vabw/8 2006.252.08:12:04.27/vbbw/8 2006.252.08:12:04.43/xfe/off,on,14.2 2006.252.08:12:04.80/ifatt/23,28,28,28 2006.252.08:12:05.08/fmout-gps/S +4.76E-07 2006.252.08:12:05.12:!2006.252.08:13:10 2006.252.08:13:10.02:data_valid=off 2006.252.08:13:10.02:postob 2006.252.08:13:10.11/cable/+6.4111E-03 2006.252.08:13:10.11/wx/27.30,1011.1,90 2006.252.08:13:11.08/fmout-gps/S +4.76E-07 2006.252.08:13:11.08:scan_name=252-0814,k06252,60 2006.252.08:13:11.08:source=0059+581,010245.76,582411.1,2000.0,cw 2006.252.08:13:12.15#flagr#flagr/antenna,new-source 2006.252.08:13:12.15:checkk5 2006.252.08:13:12.52/chk_autoobs//k5ts1/ autoobs is running! 2006.252.08:13:12.90/chk_autoobs//k5ts2/ autoobs is running! 2006.252.08:13:13.28/chk_autoobs//k5ts3/ autoobs is running! 2006.252.08:13:13.65/chk_autoobs//k5ts4/ autoobs is running! 2006.252.08:13:14.02/chk_obsdata//k5ts1/T2520812??a.dat file size is correct (nominal:560MB, actual:552MB). 2006.252.08:13:14.39/chk_obsdata//k5ts2/T2520812??b.dat file size is correct (nominal:560MB, actual:552MB). 2006.252.08:13:14.76/chk_obsdata//k5ts3/T2520812??c.dat file size is correct (nominal:560MB, actual:552MB). 2006.252.08:13:15.13/chk_obsdata//k5ts4/T2520812??d.dat file size is correct (nominal:560MB, actual:552MB). 2006.252.08:13:15.83/k5log//k5ts1_log_newline 2006.252.08:13:16.52/k5log//k5ts2_log_newline 2006.252.08:13:17.22/k5log//k5ts3_log_newline 2006.252.08:13:17.88/k5log//k5ts4_log_newline 2006.252.08:13:17.91/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.252.08:13:17.91:4f8m12a=2 2006.252.08:13:17.91$4f8m12a/echo=on 2006.252.08:13:17.91$4f8m12a/pcalon 2006.252.08:13:17.91$pcalon/"no phase cal control is implemented here 2006.252.08:13:17.91$4f8m12a/"tpicd=stop 2006.252.08:13:17.91$4f8m12a/vc4f8 2006.252.08:13:17.91$vc4f8/valo=1,532.99 2006.252.08:13:17.91#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.252.08:13:17.91#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.252.08:13:17.91#ibcon#ireg 17 cls_cnt 0 2006.252.08:13:17.91#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.252.08:13:17.91#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.252.08:13:17.91#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.252.08:13:17.91#ibcon#enter wrdev, iclass 22, count 0 2006.252.08:13:17.91#ibcon#first serial, iclass 22, count 0 2006.252.08:13:17.91#ibcon#enter sib2, iclass 22, count 0 2006.252.08:13:17.91#ibcon#flushed, iclass 22, count 0 2006.252.08:13:17.91#ibcon#about to write, iclass 22, count 0 2006.252.08:13:17.91#ibcon#wrote, iclass 22, count 0 2006.252.08:13:17.91#ibcon#about to read 3, iclass 22, count 0 2006.252.08:13:17.92#ibcon#read 3, iclass 22, count 0 2006.252.08:13:17.92#ibcon#about to read 4, iclass 22, count 0 2006.252.08:13:17.92#ibcon#read 4, iclass 22, count 0 2006.252.08:13:17.92#ibcon#about to read 5, iclass 22, count 0 2006.252.08:13:17.92#ibcon#read 5, iclass 22, count 0 2006.252.08:13:17.92#ibcon#about to read 6, iclass 22, count 0 2006.252.08:13:17.92#ibcon#read 6, iclass 22, count 0 2006.252.08:13:17.92#ibcon#end of sib2, iclass 22, count 0 2006.252.08:13:17.92#ibcon#*mode == 0, iclass 22, count 0 2006.252.08:13:17.92#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.252.08:13:17.93#ibcon#[26=FRQ=01,532.99\r\n] 2006.252.08:13:17.93#ibcon#*before write, iclass 22, count 0 2006.252.08:13:17.93#ibcon#enter sib2, iclass 22, count 0 2006.252.08:13:17.93#ibcon#flushed, iclass 22, count 0 2006.252.08:13:17.93#ibcon#about to write, iclass 22, count 0 2006.252.08:13:17.93#ibcon#wrote, iclass 22, count 0 2006.252.08:13:17.93#ibcon#about to read 3, iclass 22, count 0 2006.252.08:13:17.97#ibcon#read 3, iclass 22, count 0 2006.252.08:13:17.97#ibcon#about to read 4, iclass 22, count 0 2006.252.08:13:17.97#ibcon#read 4, iclass 22, count 0 2006.252.08:13:17.97#ibcon#about to read 5, iclass 22, count 0 2006.252.08:13:17.97#ibcon#read 5, iclass 22, count 0 2006.252.08:13:17.97#ibcon#about to read 6, iclass 22, count 0 2006.252.08:13:17.97#ibcon#read 6, iclass 22, count 0 2006.252.08:13:17.97#ibcon#end of sib2, iclass 22, count 0 2006.252.08:13:17.97#ibcon#*after write, iclass 22, count 0 2006.252.08:13:17.97#ibcon#*before return 0, iclass 22, count 0 2006.252.08:13:17.97#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.252.08:13:17.98#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.252.08:13:17.98#ibcon#about to clear, iclass 22 cls_cnt 0 2006.252.08:13:17.98#ibcon#cleared, iclass 22 cls_cnt 0 2006.252.08:13:17.98$vc4f8/va=1,8 2006.252.08:13:17.98#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.252.08:13:17.98#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.252.08:13:17.98#ibcon#ireg 11 cls_cnt 2 2006.252.08:13:17.98#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.252.08:13:17.98#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.252.08:13:17.98#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.252.08:13:17.98#ibcon#enter wrdev, iclass 24, count 2 2006.252.08:13:17.98#ibcon#first serial, iclass 24, count 2 2006.252.08:13:17.98#ibcon#enter sib2, iclass 24, count 2 2006.252.08:13:17.98#ibcon#flushed, iclass 24, count 2 2006.252.08:13:17.98#ibcon#about to write, iclass 24, count 2 2006.252.08:13:17.98#ibcon#wrote, iclass 24, count 2 2006.252.08:13:17.98#ibcon#about to read 3, iclass 24, count 2 2006.252.08:13:17.99#ibcon#read 3, iclass 24, count 2 2006.252.08:13:17.99#ibcon#about to read 4, iclass 24, count 2 2006.252.08:13:17.99#ibcon#read 4, iclass 24, count 2 2006.252.08:13:17.99#ibcon#about to read 5, iclass 24, count 2 2006.252.08:13:17.99#ibcon#read 5, iclass 24, count 2 2006.252.08:13:17.99#ibcon#about to read 6, iclass 24, count 2 2006.252.08:13:17.99#ibcon#read 6, iclass 24, count 2 2006.252.08:13:17.99#ibcon#end of sib2, iclass 24, count 2 2006.252.08:13:17.99#ibcon#*mode == 0, iclass 24, count 2 2006.252.08:13:17.99#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.252.08:13:17.99#ibcon#[25=AT01-08\r\n] 2006.252.08:13:17.99#ibcon#*before write, iclass 24, count 2 2006.252.08:13:18.00#ibcon#enter sib2, iclass 24, count 2 2006.252.08:13:18.00#ibcon#flushed, iclass 24, count 2 2006.252.08:13:18.00#ibcon#about to write, iclass 24, count 2 2006.252.08:13:18.00#ibcon#wrote, iclass 24, count 2 2006.252.08:13:18.00#ibcon#about to read 3, iclass 24, count 2 2006.252.08:13:18.03#ibcon#read 3, iclass 24, count 2 2006.252.08:13:18.03#ibcon#about to read 4, iclass 24, count 2 2006.252.08:13:18.03#ibcon#read 4, iclass 24, count 2 2006.252.08:13:18.03#ibcon#about to read 5, iclass 24, count 2 2006.252.08:13:18.03#ibcon#read 5, iclass 24, count 2 2006.252.08:13:18.03#ibcon#about to read 6, iclass 24, count 2 2006.252.08:13:18.03#ibcon#read 6, iclass 24, count 2 2006.252.08:13:18.03#ibcon#end of sib2, iclass 24, count 2 2006.252.08:13:18.03#ibcon#*after write, iclass 24, count 2 2006.252.08:13:18.03#ibcon#*before return 0, iclass 24, count 2 2006.252.08:13:18.03#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.252.08:13:18.03#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.252.08:13:18.03#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.252.08:13:18.03#ibcon#ireg 7 cls_cnt 0 2006.252.08:13:18.03#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.252.08:13:18.15#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.252.08:13:18.15#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.252.08:13:18.15#ibcon#enter wrdev, iclass 24, count 0 2006.252.08:13:18.15#ibcon#first serial, iclass 24, count 0 2006.252.08:13:18.15#ibcon#enter sib2, iclass 24, count 0 2006.252.08:13:18.15#ibcon#flushed, iclass 24, count 0 2006.252.08:13:18.15#ibcon#about to write, iclass 24, count 0 2006.252.08:13:18.15#ibcon#wrote, iclass 24, count 0 2006.252.08:13:18.15#ibcon#about to read 3, iclass 24, count 0 2006.252.08:13:18.16#ibcon#read 3, iclass 24, count 0 2006.252.08:13:18.16#ibcon#about to read 4, iclass 24, count 0 2006.252.08:13:18.16#ibcon#read 4, iclass 24, count 0 2006.252.08:13:18.16#ibcon#about to read 5, iclass 24, count 0 2006.252.08:13:18.16#ibcon#read 5, iclass 24, count 0 2006.252.08:13:18.17#ibcon#about to read 6, iclass 24, count 0 2006.252.08:13:18.17#ibcon#read 6, iclass 24, count 0 2006.252.08:13:18.17#ibcon#end of sib2, iclass 24, count 0 2006.252.08:13:18.17#ibcon#*mode == 0, iclass 24, count 0 2006.252.08:13:18.17#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.252.08:13:18.17#ibcon#[25=USB\r\n] 2006.252.08:13:18.17#ibcon#*before write, iclass 24, count 0 2006.252.08:13:18.17#ibcon#enter sib2, iclass 24, count 0 2006.252.08:13:18.17#ibcon#flushed, iclass 24, count 0 2006.252.08:13:18.17#ibcon#about to write, iclass 24, count 0 2006.252.08:13:18.17#ibcon#wrote, iclass 24, count 0 2006.252.08:13:18.17#ibcon#about to read 3, iclass 24, count 0 2006.252.08:13:18.19#ibcon#read 3, iclass 24, count 0 2006.252.08:13:18.19#ibcon#about to read 4, iclass 24, count 0 2006.252.08:13:18.19#ibcon#read 4, iclass 24, count 0 2006.252.08:13:18.19#ibcon#about to read 5, iclass 24, count 0 2006.252.08:13:18.19#ibcon#read 5, iclass 24, count 0 2006.252.08:13:18.19#ibcon#about to read 6, iclass 24, count 0 2006.252.08:13:18.19#ibcon#read 6, iclass 24, count 0 2006.252.08:13:18.19#ibcon#end of sib2, iclass 24, count 0 2006.252.08:13:18.19#ibcon#*after write, iclass 24, count 0 2006.252.08:13:18.19#ibcon#*before return 0, iclass 24, count 0 2006.252.08:13:18.19#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.252.08:13:18.20#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.252.08:13:18.20#ibcon#about to clear, iclass 24 cls_cnt 0 2006.252.08:13:18.20#ibcon#cleared, iclass 24 cls_cnt 0 2006.252.08:13:18.20$vc4f8/valo=2,572.99 2006.252.08:13:18.20#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.252.08:13:18.20#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.252.08:13:18.20#ibcon#ireg 17 cls_cnt 0 2006.252.08:13:18.20#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.252.08:13:18.20#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.252.08:13:18.20#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.252.08:13:18.20#ibcon#enter wrdev, iclass 26, count 0 2006.252.08:13:18.20#ibcon#first serial, iclass 26, count 0 2006.252.08:13:18.20#ibcon#enter sib2, iclass 26, count 0 2006.252.08:13:18.20#ibcon#flushed, iclass 26, count 0 2006.252.08:13:18.20#ibcon#about to write, iclass 26, count 0 2006.252.08:13:18.20#ibcon#wrote, iclass 26, count 0 2006.252.08:13:18.20#ibcon#about to read 3, iclass 26, count 0 2006.252.08:13:18.22#ibcon#read 3, iclass 26, count 0 2006.252.08:13:18.22#ibcon#about to read 4, iclass 26, count 0 2006.252.08:13:18.22#ibcon#read 4, iclass 26, count 0 2006.252.08:13:18.22#ibcon#about to read 5, iclass 26, count 0 2006.252.08:13:18.22#ibcon#read 5, iclass 26, count 0 2006.252.08:13:18.22#ibcon#about to read 6, iclass 26, count 0 2006.252.08:13:18.22#ibcon#read 6, iclass 26, count 0 2006.252.08:13:18.22#ibcon#end of sib2, iclass 26, count 0 2006.252.08:13:18.22#ibcon#*mode == 0, iclass 26, count 0 2006.252.08:13:18.22#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.252.08:13:18.22#ibcon#[26=FRQ=02,572.99\r\n] 2006.252.08:13:18.22#ibcon#*before write, iclass 26, count 0 2006.252.08:13:18.22#ibcon#enter sib2, iclass 26, count 0 2006.252.08:13:18.22#ibcon#flushed, iclass 26, count 0 2006.252.08:13:18.22#ibcon#about to write, iclass 26, count 0 2006.252.08:13:18.22#ibcon#wrote, iclass 26, count 0 2006.252.08:13:18.22#ibcon#about to read 3, iclass 26, count 0 2006.252.08:13:18.26#ibcon#read 3, iclass 26, count 0 2006.252.08:13:18.26#ibcon#about to read 4, iclass 26, count 0 2006.252.08:13:18.26#ibcon#read 4, iclass 26, count 0 2006.252.08:13:18.26#ibcon#about to read 5, iclass 26, count 0 2006.252.08:13:18.26#ibcon#read 5, iclass 26, count 0 2006.252.08:13:18.26#ibcon#about to read 6, iclass 26, count 0 2006.252.08:13:18.26#ibcon#read 6, iclass 26, count 0 2006.252.08:13:18.27#ibcon#end of sib2, iclass 26, count 0 2006.252.08:13:18.27#ibcon#*after write, iclass 26, count 0 2006.252.08:13:18.27#ibcon#*before return 0, iclass 26, count 0 2006.252.08:13:18.27#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.252.08:13:18.27#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.252.08:13:18.27#ibcon#about to clear, iclass 26 cls_cnt 0 2006.252.08:13:18.27#ibcon#cleared, iclass 26 cls_cnt 0 2006.252.08:13:18.27$vc4f8/va=2,7 2006.252.08:13:18.27#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.252.08:13:18.27#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.252.08:13:18.27#ibcon#ireg 11 cls_cnt 2 2006.252.08:13:18.27#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.252.08:13:18.32#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.252.08:13:18.32#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.252.08:13:18.32#ibcon#enter wrdev, iclass 28, count 2 2006.252.08:13:18.32#ibcon#first serial, iclass 28, count 2 2006.252.08:13:18.32#ibcon#enter sib2, iclass 28, count 2 2006.252.08:13:18.32#ibcon#flushed, iclass 28, count 2 2006.252.08:13:18.32#ibcon#about to write, iclass 28, count 2 2006.252.08:13:18.32#ibcon#wrote, iclass 28, count 2 2006.252.08:13:18.32#ibcon#about to read 3, iclass 28, count 2 2006.252.08:13:18.33#ibcon#read 3, iclass 28, count 2 2006.252.08:13:18.33#ibcon#about to read 4, iclass 28, count 2 2006.252.08:13:18.33#ibcon#read 4, iclass 28, count 2 2006.252.08:13:18.33#ibcon#about to read 5, iclass 28, count 2 2006.252.08:13:18.33#ibcon#read 5, iclass 28, count 2 2006.252.08:13:18.33#ibcon#about to read 6, iclass 28, count 2 2006.252.08:13:18.33#ibcon#read 6, iclass 28, count 2 2006.252.08:13:18.33#ibcon#end of sib2, iclass 28, count 2 2006.252.08:13:18.33#ibcon#*mode == 0, iclass 28, count 2 2006.252.08:13:18.33#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.252.08:13:18.34#ibcon#[25=AT02-07\r\n] 2006.252.08:13:18.34#ibcon#*before write, iclass 28, count 2 2006.252.08:13:18.34#ibcon#enter sib2, iclass 28, count 2 2006.252.08:13:18.34#ibcon#flushed, iclass 28, count 2 2006.252.08:13:18.34#ibcon#about to write, iclass 28, count 2 2006.252.08:13:18.34#ibcon#wrote, iclass 28, count 2 2006.252.08:13:18.34#ibcon#about to read 3, iclass 28, count 2 2006.252.08:13:18.36#ibcon#read 3, iclass 28, count 2 2006.252.08:13:18.36#ibcon#about to read 4, iclass 28, count 2 2006.252.08:13:18.36#ibcon#read 4, iclass 28, count 2 2006.252.08:13:18.36#ibcon#about to read 5, iclass 28, count 2 2006.252.08:13:18.36#ibcon#read 5, iclass 28, count 2 2006.252.08:13:18.36#ibcon#about to read 6, iclass 28, count 2 2006.252.08:13:18.36#ibcon#read 6, iclass 28, count 2 2006.252.08:13:18.36#ibcon#end of sib2, iclass 28, count 2 2006.252.08:13:18.36#ibcon#*after write, iclass 28, count 2 2006.252.08:13:18.37#ibcon#*before return 0, iclass 28, count 2 2006.252.08:13:18.37#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.252.08:13:18.37#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.252.08:13:18.37#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.252.08:13:18.37#ibcon#ireg 7 cls_cnt 0 2006.252.08:13:18.37#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.252.08:13:18.48#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.252.08:13:18.48#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.252.08:13:18.48#ibcon#enter wrdev, iclass 28, count 0 2006.252.08:13:18.48#ibcon#first serial, iclass 28, count 0 2006.252.08:13:18.48#ibcon#enter sib2, iclass 28, count 0 2006.252.08:13:18.48#ibcon#flushed, iclass 28, count 0 2006.252.08:13:18.48#ibcon#about to write, iclass 28, count 0 2006.252.08:13:18.48#ibcon#wrote, iclass 28, count 0 2006.252.08:13:18.48#ibcon#about to read 3, iclass 28, count 0 2006.252.08:13:18.50#ibcon#read 3, iclass 28, count 0 2006.252.08:13:18.50#ibcon#about to read 4, iclass 28, count 0 2006.252.08:13:18.50#ibcon#read 4, iclass 28, count 0 2006.252.08:13:18.50#ibcon#about to read 5, iclass 28, count 0 2006.252.08:13:18.50#ibcon#read 5, iclass 28, count 0 2006.252.08:13:18.50#ibcon#about to read 6, iclass 28, count 0 2006.252.08:13:18.50#ibcon#read 6, iclass 28, count 0 2006.252.08:13:18.50#ibcon#end of sib2, iclass 28, count 0 2006.252.08:13:18.50#ibcon#*mode == 0, iclass 28, count 0 2006.252.08:13:18.50#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.252.08:13:18.50#ibcon#[25=USB\r\n] 2006.252.08:13:18.50#ibcon#*before write, iclass 28, count 0 2006.252.08:13:18.51#ibcon#enter sib2, iclass 28, count 0 2006.252.08:13:18.51#ibcon#flushed, iclass 28, count 0 2006.252.08:13:18.51#ibcon#about to write, iclass 28, count 0 2006.252.08:13:18.51#ibcon#wrote, iclass 28, count 0 2006.252.08:13:18.51#ibcon#about to read 3, iclass 28, count 0 2006.252.08:13:18.53#ibcon#read 3, iclass 28, count 0 2006.252.08:13:18.53#ibcon#about to read 4, iclass 28, count 0 2006.252.08:13:18.53#ibcon#read 4, iclass 28, count 0 2006.252.08:13:18.53#ibcon#about to read 5, iclass 28, count 0 2006.252.08:13:18.53#ibcon#read 5, iclass 28, count 0 2006.252.08:13:18.53#ibcon#about to read 6, iclass 28, count 0 2006.252.08:13:18.53#ibcon#read 6, iclass 28, count 0 2006.252.08:13:18.53#ibcon#end of sib2, iclass 28, count 0 2006.252.08:13:18.53#ibcon#*after write, iclass 28, count 0 2006.252.08:13:18.53#ibcon#*before return 0, iclass 28, count 0 2006.252.08:13:18.53#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.252.08:13:18.54#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.252.08:13:18.54#ibcon#about to clear, iclass 28 cls_cnt 0 2006.252.08:13:18.54#ibcon#cleared, iclass 28 cls_cnt 0 2006.252.08:13:18.54$vc4f8/valo=3,672.99 2006.252.08:13:18.54#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.252.08:13:18.54#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.252.08:13:18.54#ibcon#ireg 17 cls_cnt 0 2006.252.08:13:18.54#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.252.08:13:18.54#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.252.08:13:18.54#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.252.08:13:18.54#ibcon#enter wrdev, iclass 30, count 0 2006.252.08:13:18.54#ibcon#first serial, iclass 30, count 0 2006.252.08:13:18.54#ibcon#enter sib2, iclass 30, count 0 2006.252.08:13:18.54#ibcon#flushed, iclass 30, count 0 2006.252.08:13:18.54#ibcon#about to write, iclass 30, count 0 2006.252.08:13:18.54#ibcon#wrote, iclass 30, count 0 2006.252.08:13:18.54#ibcon#about to read 3, iclass 30, count 0 2006.252.08:13:18.56#ibcon#read 3, iclass 30, count 0 2006.252.08:13:18.56#ibcon#about to read 4, iclass 30, count 0 2006.252.08:13:18.56#ibcon#read 4, iclass 30, count 0 2006.252.08:13:18.56#ibcon#about to read 5, iclass 30, count 0 2006.252.08:13:18.56#ibcon#read 5, iclass 30, count 0 2006.252.08:13:18.56#ibcon#about to read 6, iclass 30, count 0 2006.252.08:13:18.56#ibcon#read 6, iclass 30, count 0 2006.252.08:13:18.56#ibcon#end of sib2, iclass 30, count 0 2006.252.08:13:18.56#ibcon#*mode == 0, iclass 30, count 0 2006.252.08:13:18.56#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.252.08:13:18.56#ibcon#[26=FRQ=03,672.99\r\n] 2006.252.08:13:18.56#ibcon#*before write, iclass 30, count 0 2006.252.08:13:18.56#ibcon#enter sib2, iclass 30, count 0 2006.252.08:13:18.56#ibcon#flushed, iclass 30, count 0 2006.252.08:13:18.56#ibcon#about to write, iclass 30, count 0 2006.252.08:13:18.56#ibcon#wrote, iclass 30, count 0 2006.252.08:13:18.56#ibcon#about to read 3, iclass 30, count 0 2006.252.08:13:18.60#ibcon#read 3, iclass 30, count 0 2006.252.08:13:18.60#ibcon#about to read 4, iclass 30, count 0 2006.252.08:13:18.60#ibcon#read 4, iclass 30, count 0 2006.252.08:13:18.60#ibcon#about to read 5, iclass 30, count 0 2006.252.08:13:18.60#ibcon#read 5, iclass 30, count 0 2006.252.08:13:18.60#ibcon#about to read 6, iclass 30, count 0 2006.252.08:13:18.60#ibcon#read 6, iclass 30, count 0 2006.252.08:13:18.60#ibcon#end of sib2, iclass 30, count 0 2006.252.08:13:18.61#ibcon#*after write, iclass 30, count 0 2006.252.08:13:18.61#ibcon#*before return 0, iclass 30, count 0 2006.252.08:13:18.61#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.252.08:13:18.61#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.252.08:13:18.61#ibcon#about to clear, iclass 30 cls_cnt 0 2006.252.08:13:18.61#ibcon#cleared, iclass 30 cls_cnt 0 2006.252.08:13:18.61$vc4f8/va=3,6 2006.252.08:13:18.61#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.252.08:13:18.61#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.252.08:13:18.61#ibcon#ireg 11 cls_cnt 2 2006.252.08:13:18.61#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.252.08:13:18.66#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.252.08:13:18.66#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.252.08:13:18.66#ibcon#enter wrdev, iclass 32, count 2 2006.252.08:13:18.66#ibcon#first serial, iclass 32, count 2 2006.252.08:13:18.66#ibcon#enter sib2, iclass 32, count 2 2006.252.08:13:18.66#ibcon#flushed, iclass 32, count 2 2006.252.08:13:18.66#ibcon#about to write, iclass 32, count 2 2006.252.08:13:18.66#ibcon#wrote, iclass 32, count 2 2006.252.08:13:18.66#ibcon#about to read 3, iclass 32, count 2 2006.252.08:13:18.67#ibcon#read 3, iclass 32, count 2 2006.252.08:13:18.67#ibcon#about to read 4, iclass 32, count 2 2006.252.08:13:18.67#ibcon#read 4, iclass 32, count 2 2006.252.08:13:18.67#ibcon#about to read 5, iclass 32, count 2 2006.252.08:13:18.67#ibcon#read 5, iclass 32, count 2 2006.252.08:13:18.67#ibcon#about to read 6, iclass 32, count 2 2006.252.08:13:18.67#ibcon#read 6, iclass 32, count 2 2006.252.08:13:18.67#ibcon#end of sib2, iclass 32, count 2 2006.252.08:13:18.67#ibcon#*mode == 0, iclass 32, count 2 2006.252.08:13:18.67#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.252.08:13:18.68#ibcon#[25=AT03-06\r\n] 2006.252.08:13:18.68#ibcon#*before write, iclass 32, count 2 2006.252.08:13:18.68#ibcon#enter sib2, iclass 32, count 2 2006.252.08:13:18.68#ibcon#flushed, iclass 32, count 2 2006.252.08:13:18.68#ibcon#about to write, iclass 32, count 2 2006.252.08:13:18.68#ibcon#wrote, iclass 32, count 2 2006.252.08:13:18.68#ibcon#about to read 3, iclass 32, count 2 2006.252.08:13:18.70#ibcon#read 3, iclass 32, count 2 2006.252.08:13:18.70#ibcon#about to read 4, iclass 32, count 2 2006.252.08:13:18.70#ibcon#read 4, iclass 32, count 2 2006.252.08:13:18.70#ibcon#about to read 5, iclass 32, count 2 2006.252.08:13:18.70#ibcon#read 5, iclass 32, count 2 2006.252.08:13:18.70#ibcon#about to read 6, iclass 32, count 2 2006.252.08:13:18.70#ibcon#read 6, iclass 32, count 2 2006.252.08:13:18.70#ibcon#end of sib2, iclass 32, count 2 2006.252.08:13:18.70#ibcon#*after write, iclass 32, count 2 2006.252.08:13:18.71#ibcon#*before return 0, iclass 32, count 2 2006.252.08:13:18.71#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.252.08:13:18.71#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.252.08:13:18.71#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.252.08:13:18.71#ibcon#ireg 7 cls_cnt 0 2006.252.08:13:18.71#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.252.08:13:18.82#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.252.08:13:18.82#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.252.08:13:18.82#ibcon#enter wrdev, iclass 32, count 0 2006.252.08:13:18.82#ibcon#first serial, iclass 32, count 0 2006.252.08:13:18.82#ibcon#enter sib2, iclass 32, count 0 2006.252.08:13:18.82#ibcon#flushed, iclass 32, count 0 2006.252.08:13:18.82#ibcon#about to write, iclass 32, count 0 2006.252.08:13:18.82#ibcon#wrote, iclass 32, count 0 2006.252.08:13:18.82#ibcon#about to read 3, iclass 32, count 0 2006.252.08:13:18.84#ibcon#read 3, iclass 32, count 0 2006.252.08:13:18.84#ibcon#about to read 4, iclass 32, count 0 2006.252.08:13:18.84#ibcon#read 4, iclass 32, count 0 2006.252.08:13:18.84#ibcon#about to read 5, iclass 32, count 0 2006.252.08:13:18.84#ibcon#read 5, iclass 32, count 0 2006.252.08:13:18.84#ibcon#about to read 6, iclass 32, count 0 2006.252.08:13:18.84#ibcon#read 6, iclass 32, count 0 2006.252.08:13:18.84#ibcon#end of sib2, iclass 32, count 0 2006.252.08:13:18.84#ibcon#*mode == 0, iclass 32, count 0 2006.252.08:13:18.84#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.252.08:13:18.84#ibcon#[25=USB\r\n] 2006.252.08:13:18.84#ibcon#*before write, iclass 32, count 0 2006.252.08:13:18.85#ibcon#enter sib2, iclass 32, count 0 2006.252.08:13:18.85#ibcon#flushed, iclass 32, count 0 2006.252.08:13:18.85#ibcon#about to write, iclass 32, count 0 2006.252.08:13:18.85#ibcon#wrote, iclass 32, count 0 2006.252.08:13:18.85#ibcon#about to read 3, iclass 32, count 0 2006.252.08:13:18.87#ibcon#read 3, iclass 32, count 0 2006.252.08:13:18.87#ibcon#about to read 4, iclass 32, count 0 2006.252.08:13:18.87#ibcon#read 4, iclass 32, count 0 2006.252.08:13:18.87#ibcon#about to read 5, iclass 32, count 0 2006.252.08:13:18.87#ibcon#read 5, iclass 32, count 0 2006.252.08:13:18.87#ibcon#about to read 6, iclass 32, count 0 2006.252.08:13:18.87#ibcon#read 6, iclass 32, count 0 2006.252.08:13:18.87#ibcon#end of sib2, iclass 32, count 0 2006.252.08:13:18.87#ibcon#*after write, iclass 32, count 0 2006.252.08:13:18.87#ibcon#*before return 0, iclass 32, count 0 2006.252.08:13:18.87#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.252.08:13:18.88#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.252.08:13:18.88#ibcon#about to clear, iclass 32 cls_cnt 0 2006.252.08:13:18.88#ibcon#cleared, iclass 32 cls_cnt 0 2006.252.08:13:18.88$vc4f8/valo=4,832.99 2006.252.08:13:18.88#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.252.08:13:18.88#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.252.08:13:18.88#ibcon#ireg 17 cls_cnt 0 2006.252.08:13:18.88#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.252.08:13:18.88#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.252.08:13:18.88#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.252.08:13:18.88#ibcon#enter wrdev, iclass 34, count 0 2006.252.08:13:18.88#ibcon#first serial, iclass 34, count 0 2006.252.08:13:18.88#ibcon#enter sib2, iclass 34, count 0 2006.252.08:13:18.88#ibcon#flushed, iclass 34, count 0 2006.252.08:13:18.88#ibcon#about to write, iclass 34, count 0 2006.252.08:13:18.88#ibcon#wrote, iclass 34, count 0 2006.252.08:13:18.88#ibcon#about to read 3, iclass 34, count 0 2006.252.08:13:18.89#ibcon#read 3, iclass 34, count 0 2006.252.08:13:18.89#ibcon#about to read 4, iclass 34, count 0 2006.252.08:13:18.89#ibcon#read 4, iclass 34, count 0 2006.252.08:13:18.89#ibcon#about to read 5, iclass 34, count 0 2006.252.08:13:18.89#ibcon#read 5, iclass 34, count 0 2006.252.08:13:18.89#ibcon#about to read 6, iclass 34, count 0 2006.252.08:13:18.89#ibcon#read 6, iclass 34, count 0 2006.252.08:13:18.89#ibcon#end of sib2, iclass 34, count 0 2006.252.08:13:18.89#ibcon#*mode == 0, iclass 34, count 0 2006.252.08:13:18.89#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.252.08:13:18.89#ibcon#[26=FRQ=04,832.99\r\n] 2006.252.08:13:18.90#ibcon#*before write, iclass 34, count 0 2006.252.08:13:18.90#ibcon#enter sib2, iclass 34, count 0 2006.252.08:13:18.90#ibcon#flushed, iclass 34, count 0 2006.252.08:13:18.90#ibcon#about to write, iclass 34, count 0 2006.252.08:13:18.90#ibcon#wrote, iclass 34, count 0 2006.252.08:13:18.90#ibcon#about to read 3, iclass 34, count 0 2006.252.08:13:18.93#ibcon#read 3, iclass 34, count 0 2006.252.08:13:18.93#ibcon#about to read 4, iclass 34, count 0 2006.252.08:13:18.93#ibcon#read 4, iclass 34, count 0 2006.252.08:13:18.93#ibcon#about to read 5, iclass 34, count 0 2006.252.08:13:18.93#ibcon#read 5, iclass 34, count 0 2006.252.08:13:18.93#ibcon#about to read 6, iclass 34, count 0 2006.252.08:13:18.93#ibcon#read 6, iclass 34, count 0 2006.252.08:13:18.93#ibcon#end of sib2, iclass 34, count 0 2006.252.08:13:18.93#ibcon#*after write, iclass 34, count 0 2006.252.08:13:18.93#ibcon#*before return 0, iclass 34, count 0 2006.252.08:13:18.94#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.252.08:13:18.94#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.252.08:13:18.94#ibcon#about to clear, iclass 34 cls_cnt 0 2006.252.08:13:18.94#ibcon#cleared, iclass 34 cls_cnt 0 2006.252.08:13:18.94$vc4f8/va=4,7 2006.252.08:13:18.94#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.252.08:13:18.94#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.252.08:13:18.94#ibcon#ireg 11 cls_cnt 2 2006.252.08:13:18.94#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.252.08:13:18.99#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.252.08:13:18.99#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.252.08:13:18.99#ibcon#enter wrdev, iclass 36, count 2 2006.252.08:13:18.99#ibcon#first serial, iclass 36, count 2 2006.252.08:13:18.99#ibcon#enter sib2, iclass 36, count 2 2006.252.08:13:18.99#ibcon#flushed, iclass 36, count 2 2006.252.08:13:18.99#ibcon#about to write, iclass 36, count 2 2006.252.08:13:18.99#ibcon#wrote, iclass 36, count 2 2006.252.08:13:18.99#ibcon#about to read 3, iclass 36, count 2 2006.252.08:13:19.01#ibcon#read 3, iclass 36, count 2 2006.252.08:13:19.01#ibcon#about to read 4, iclass 36, count 2 2006.252.08:13:19.01#ibcon#read 4, iclass 36, count 2 2006.252.08:13:19.01#ibcon#about to read 5, iclass 36, count 2 2006.252.08:13:19.01#ibcon#read 5, iclass 36, count 2 2006.252.08:13:19.01#ibcon#about to read 6, iclass 36, count 2 2006.252.08:13:19.01#ibcon#read 6, iclass 36, count 2 2006.252.08:13:19.01#ibcon#end of sib2, iclass 36, count 2 2006.252.08:13:19.01#ibcon#*mode == 0, iclass 36, count 2 2006.252.08:13:19.01#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.252.08:13:19.01#ibcon#[25=AT04-07\r\n] 2006.252.08:13:19.02#ibcon#*before write, iclass 36, count 2 2006.252.08:13:19.02#ibcon#enter sib2, iclass 36, count 2 2006.252.08:13:19.02#ibcon#flushed, iclass 36, count 2 2006.252.08:13:19.02#ibcon#about to write, iclass 36, count 2 2006.252.08:13:19.02#ibcon#wrote, iclass 36, count 2 2006.252.08:13:19.02#ibcon#about to read 3, iclass 36, count 2 2006.252.08:13:19.04#ibcon#read 3, iclass 36, count 2 2006.252.08:13:19.04#ibcon#about to read 4, iclass 36, count 2 2006.252.08:13:19.04#ibcon#read 4, iclass 36, count 2 2006.252.08:13:19.04#ibcon#about to read 5, iclass 36, count 2 2006.252.08:13:19.04#ibcon#read 5, iclass 36, count 2 2006.252.08:13:19.04#ibcon#about to read 6, iclass 36, count 2 2006.252.08:13:19.04#ibcon#read 6, iclass 36, count 2 2006.252.08:13:19.04#ibcon#end of sib2, iclass 36, count 2 2006.252.08:13:19.04#ibcon#*after write, iclass 36, count 2 2006.252.08:13:19.05#ibcon#*before return 0, iclass 36, count 2 2006.252.08:13:19.05#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.252.08:13:19.05#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.252.08:13:19.05#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.252.08:13:19.05#ibcon#ireg 7 cls_cnt 0 2006.252.08:13:19.05#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.252.08:13:19.16#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.252.08:13:19.16#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.252.08:13:19.16#ibcon#enter wrdev, iclass 36, count 0 2006.252.08:13:19.16#ibcon#first serial, iclass 36, count 0 2006.252.08:13:19.16#ibcon#enter sib2, iclass 36, count 0 2006.252.08:13:19.16#ibcon#flushed, iclass 36, count 0 2006.252.08:13:19.16#ibcon#about to write, iclass 36, count 0 2006.252.08:13:19.16#ibcon#wrote, iclass 36, count 0 2006.252.08:13:19.16#ibcon#about to read 3, iclass 36, count 0 2006.252.08:13:19.18#ibcon#read 3, iclass 36, count 0 2006.252.08:13:19.18#ibcon#about to read 4, iclass 36, count 0 2006.252.08:13:19.18#ibcon#read 4, iclass 36, count 0 2006.252.08:13:19.18#ibcon#about to read 5, iclass 36, count 0 2006.252.08:13:19.18#ibcon#read 5, iclass 36, count 0 2006.252.08:13:19.18#ibcon#about to read 6, iclass 36, count 0 2006.252.08:13:19.18#ibcon#read 6, iclass 36, count 0 2006.252.08:13:19.18#ibcon#end of sib2, iclass 36, count 0 2006.252.08:13:19.18#ibcon#*mode == 0, iclass 36, count 0 2006.252.08:13:19.18#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.252.08:13:19.18#ibcon#[25=USB\r\n] 2006.252.08:13:19.18#ibcon#*before write, iclass 36, count 0 2006.252.08:13:19.19#ibcon#enter sib2, iclass 36, count 0 2006.252.08:13:19.19#ibcon#flushed, iclass 36, count 0 2006.252.08:13:19.19#ibcon#about to write, iclass 36, count 0 2006.252.08:13:19.19#ibcon#wrote, iclass 36, count 0 2006.252.08:13:19.19#ibcon#about to read 3, iclass 36, count 0 2006.252.08:13:19.21#ibcon#read 3, iclass 36, count 0 2006.252.08:13:19.21#ibcon#about to read 4, iclass 36, count 0 2006.252.08:13:19.21#ibcon#read 4, iclass 36, count 0 2006.252.08:13:19.21#ibcon#about to read 5, iclass 36, count 0 2006.252.08:13:19.21#ibcon#read 5, iclass 36, count 0 2006.252.08:13:19.21#ibcon#about to read 6, iclass 36, count 0 2006.252.08:13:19.21#ibcon#read 6, iclass 36, count 0 2006.252.08:13:19.21#ibcon#end of sib2, iclass 36, count 0 2006.252.08:13:19.21#ibcon#*after write, iclass 36, count 0 2006.252.08:13:19.21#ibcon#*before return 0, iclass 36, count 0 2006.252.08:13:19.21#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.252.08:13:19.22#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.252.08:13:19.22#ibcon#about to clear, iclass 36 cls_cnt 0 2006.252.08:13:19.22#ibcon#cleared, iclass 36 cls_cnt 0 2006.252.08:13:19.22$vc4f8/valo=5,652.99 2006.252.08:13:19.22#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.252.08:13:19.22#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.252.08:13:19.22#ibcon#ireg 17 cls_cnt 0 2006.252.08:13:19.22#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.252.08:13:19.22#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.252.08:13:19.22#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.252.08:13:19.22#ibcon#enter wrdev, iclass 38, count 0 2006.252.08:13:19.22#ibcon#first serial, iclass 38, count 0 2006.252.08:13:19.22#ibcon#enter sib2, iclass 38, count 0 2006.252.08:13:19.22#ibcon#flushed, iclass 38, count 0 2006.252.08:13:19.22#ibcon#about to write, iclass 38, count 0 2006.252.08:13:19.22#ibcon#wrote, iclass 38, count 0 2006.252.08:13:19.22#ibcon#about to read 3, iclass 38, count 0 2006.252.08:13:19.23#ibcon#read 3, iclass 38, count 0 2006.252.08:13:19.23#ibcon#about to read 4, iclass 38, count 0 2006.252.08:13:19.23#ibcon#read 4, iclass 38, count 0 2006.252.08:13:19.23#ibcon#about to read 5, iclass 38, count 0 2006.252.08:13:19.23#ibcon#read 5, iclass 38, count 0 2006.252.08:13:19.23#ibcon#about to read 6, iclass 38, count 0 2006.252.08:13:19.23#ibcon#read 6, iclass 38, count 0 2006.252.08:13:19.23#ibcon#end of sib2, iclass 38, count 0 2006.252.08:13:19.23#ibcon#*mode == 0, iclass 38, count 0 2006.252.08:13:19.24#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.252.08:13:19.24#ibcon#[26=FRQ=05,652.99\r\n] 2006.252.08:13:19.24#ibcon#*before write, iclass 38, count 0 2006.252.08:13:19.24#ibcon#enter sib2, iclass 38, count 0 2006.252.08:13:19.24#ibcon#flushed, iclass 38, count 0 2006.252.08:13:19.24#ibcon#about to write, iclass 38, count 0 2006.252.08:13:19.24#ibcon#wrote, iclass 38, count 0 2006.252.08:13:19.24#ibcon#about to read 3, iclass 38, count 0 2006.252.08:13:19.27#ibcon#read 3, iclass 38, count 0 2006.252.08:13:19.27#ibcon#about to read 4, iclass 38, count 0 2006.252.08:13:19.27#ibcon#read 4, iclass 38, count 0 2006.252.08:13:19.27#ibcon#about to read 5, iclass 38, count 0 2006.252.08:13:19.27#ibcon#read 5, iclass 38, count 0 2006.252.08:13:19.27#ibcon#about to read 6, iclass 38, count 0 2006.252.08:13:19.27#ibcon#read 6, iclass 38, count 0 2006.252.08:13:19.27#ibcon#end of sib2, iclass 38, count 0 2006.252.08:13:19.27#ibcon#*after write, iclass 38, count 0 2006.252.08:13:19.27#ibcon#*before return 0, iclass 38, count 0 2006.252.08:13:19.28#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.252.08:13:19.28#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.252.08:13:19.28#ibcon#about to clear, iclass 38 cls_cnt 0 2006.252.08:13:19.28#ibcon#cleared, iclass 38 cls_cnt 0 2006.252.08:13:19.28$vc4f8/va=5,7 2006.252.08:13:19.28#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.252.08:13:19.28#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.252.08:13:19.28#ibcon#ireg 11 cls_cnt 2 2006.252.08:13:19.28#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.252.08:13:19.32#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.252.08:13:19.32#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.252.08:13:19.32#ibcon#enter wrdev, iclass 40, count 2 2006.252.08:13:19.32#ibcon#first serial, iclass 40, count 2 2006.252.08:13:19.32#ibcon#enter sib2, iclass 40, count 2 2006.252.08:13:19.32#ibcon#flushed, iclass 40, count 2 2006.252.08:13:19.32#ibcon#about to write, iclass 40, count 2 2006.252.08:13:19.32#ibcon#wrote, iclass 40, count 2 2006.252.08:13:19.32#ibcon#about to read 3, iclass 40, count 2 2006.252.08:13:19.34#ibcon#read 3, iclass 40, count 2 2006.252.08:13:19.34#ibcon#about to read 4, iclass 40, count 2 2006.252.08:13:19.34#ibcon#read 4, iclass 40, count 2 2006.252.08:13:19.34#ibcon#about to read 5, iclass 40, count 2 2006.252.08:13:19.34#ibcon#read 5, iclass 40, count 2 2006.252.08:13:19.34#ibcon#about to read 6, iclass 40, count 2 2006.252.08:13:19.34#ibcon#read 6, iclass 40, count 2 2006.252.08:13:19.34#ibcon#end of sib2, iclass 40, count 2 2006.252.08:13:19.34#ibcon#*mode == 0, iclass 40, count 2 2006.252.08:13:19.34#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.252.08:13:19.34#ibcon#[25=AT05-07\r\n] 2006.252.08:13:19.34#ibcon#*before write, iclass 40, count 2 2006.252.08:13:19.35#ibcon#enter sib2, iclass 40, count 2 2006.252.08:13:19.35#ibcon#flushed, iclass 40, count 2 2006.252.08:13:19.35#ibcon#about to write, iclass 40, count 2 2006.252.08:13:19.35#ibcon#wrote, iclass 40, count 2 2006.252.08:13:19.35#ibcon#about to read 3, iclass 40, count 2 2006.252.08:13:19.37#ibcon#read 3, iclass 40, count 2 2006.252.08:13:19.37#ibcon#about to read 4, iclass 40, count 2 2006.252.08:13:19.37#ibcon#read 4, iclass 40, count 2 2006.252.08:13:19.37#ibcon#about to read 5, iclass 40, count 2 2006.252.08:13:19.37#ibcon#read 5, iclass 40, count 2 2006.252.08:13:19.37#ibcon#about to read 6, iclass 40, count 2 2006.252.08:13:19.37#ibcon#read 6, iclass 40, count 2 2006.252.08:13:19.37#ibcon#end of sib2, iclass 40, count 2 2006.252.08:13:19.37#ibcon#*after write, iclass 40, count 2 2006.252.08:13:19.37#ibcon#*before return 0, iclass 40, count 2 2006.252.08:13:19.37#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.252.08:13:19.38#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.252.08:13:19.38#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.252.08:13:19.38#ibcon#ireg 7 cls_cnt 0 2006.252.08:13:19.38#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.252.08:13:19.50#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.252.08:13:19.50#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.252.08:13:19.50#ibcon#enter wrdev, iclass 40, count 0 2006.252.08:13:19.50#ibcon#first serial, iclass 40, count 0 2006.252.08:13:19.50#ibcon#enter sib2, iclass 40, count 0 2006.252.08:13:19.50#ibcon#flushed, iclass 40, count 0 2006.252.08:13:19.50#ibcon#about to write, iclass 40, count 0 2006.252.08:13:19.50#ibcon#wrote, iclass 40, count 0 2006.252.08:13:19.50#ibcon#about to read 3, iclass 40, count 0 2006.252.08:13:19.51#ibcon#read 3, iclass 40, count 0 2006.252.08:13:19.51#ibcon#about to read 4, iclass 40, count 0 2006.252.08:13:19.51#ibcon#read 4, iclass 40, count 0 2006.252.08:13:19.51#ibcon#about to read 5, iclass 40, count 0 2006.252.08:13:19.51#ibcon#read 5, iclass 40, count 0 2006.252.08:13:19.51#ibcon#about to read 6, iclass 40, count 0 2006.252.08:13:19.51#ibcon#read 6, iclass 40, count 0 2006.252.08:13:19.51#ibcon#end of sib2, iclass 40, count 0 2006.252.08:13:19.51#ibcon#*mode == 0, iclass 40, count 0 2006.252.08:13:19.51#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.252.08:13:19.51#ibcon#[25=USB\r\n] 2006.252.08:13:19.52#ibcon#*before write, iclass 40, count 0 2006.252.08:13:19.52#ibcon#enter sib2, iclass 40, count 0 2006.252.08:13:19.52#ibcon#flushed, iclass 40, count 0 2006.252.08:13:19.52#ibcon#about to write, iclass 40, count 0 2006.252.08:13:19.52#ibcon#wrote, iclass 40, count 0 2006.252.08:13:19.52#ibcon#about to read 3, iclass 40, count 0 2006.252.08:13:19.54#ibcon#read 3, iclass 40, count 0 2006.252.08:13:19.54#ibcon#about to read 4, iclass 40, count 0 2006.252.08:13:19.54#ibcon#read 4, iclass 40, count 0 2006.252.08:13:19.54#ibcon#about to read 5, iclass 40, count 0 2006.252.08:13:19.54#ibcon#read 5, iclass 40, count 0 2006.252.08:13:19.54#ibcon#about to read 6, iclass 40, count 0 2006.252.08:13:19.54#ibcon#read 6, iclass 40, count 0 2006.252.08:13:19.54#ibcon#end of sib2, iclass 40, count 0 2006.252.08:13:19.54#ibcon#*after write, iclass 40, count 0 2006.252.08:13:19.54#ibcon#*before return 0, iclass 40, count 0 2006.252.08:13:19.54#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.252.08:13:19.55#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.252.08:13:19.55#ibcon#about to clear, iclass 40 cls_cnt 0 2006.252.08:13:19.55#ibcon#cleared, iclass 40 cls_cnt 0 2006.252.08:13:19.55$vc4f8/valo=6,772.99 2006.252.08:13:19.55#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.252.08:13:19.55#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.252.08:13:19.55#ibcon#ireg 17 cls_cnt 0 2006.252.08:13:19.55#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.252.08:13:19.55#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.252.08:13:19.55#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.252.08:13:19.55#ibcon#enter wrdev, iclass 4, count 0 2006.252.08:13:19.55#ibcon#first serial, iclass 4, count 0 2006.252.08:13:19.55#ibcon#enter sib2, iclass 4, count 0 2006.252.08:13:19.55#ibcon#flushed, iclass 4, count 0 2006.252.08:13:19.55#ibcon#about to write, iclass 4, count 0 2006.252.08:13:19.55#ibcon#wrote, iclass 4, count 0 2006.252.08:13:19.55#ibcon#about to read 3, iclass 4, count 0 2006.252.08:13:19.57#ibcon#read 3, iclass 4, count 0 2006.252.08:13:19.57#ibcon#about to read 4, iclass 4, count 0 2006.252.08:13:19.57#ibcon#read 4, iclass 4, count 0 2006.252.08:13:19.57#ibcon#about to read 5, iclass 4, count 0 2006.252.08:13:19.57#ibcon#read 5, iclass 4, count 0 2006.252.08:13:19.57#ibcon#about to read 6, iclass 4, count 0 2006.252.08:13:19.57#ibcon#read 6, iclass 4, count 0 2006.252.08:13:19.57#ibcon#end of sib2, iclass 4, count 0 2006.252.08:13:19.57#ibcon#*mode == 0, iclass 4, count 0 2006.252.08:13:19.57#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.252.08:13:19.57#ibcon#[26=FRQ=06,772.99\r\n] 2006.252.08:13:19.57#ibcon#*before write, iclass 4, count 0 2006.252.08:13:19.57#ibcon#enter sib2, iclass 4, count 0 2006.252.08:13:19.57#ibcon#flushed, iclass 4, count 0 2006.252.08:13:19.57#ibcon#about to write, iclass 4, count 0 2006.252.08:13:19.57#ibcon#wrote, iclass 4, count 0 2006.252.08:13:19.57#ibcon#about to read 3, iclass 4, count 0 2006.252.08:13:19.61#ibcon#read 3, iclass 4, count 0 2006.252.08:13:19.61#ibcon#about to read 4, iclass 4, count 0 2006.252.08:13:19.61#ibcon#read 4, iclass 4, count 0 2006.252.08:13:19.61#ibcon#about to read 5, iclass 4, count 0 2006.252.08:13:19.61#ibcon#read 5, iclass 4, count 0 2006.252.08:13:19.61#ibcon#about to read 6, iclass 4, count 0 2006.252.08:13:19.61#ibcon#read 6, iclass 4, count 0 2006.252.08:13:19.61#ibcon#end of sib2, iclass 4, count 0 2006.252.08:13:19.62#ibcon#*after write, iclass 4, count 0 2006.252.08:13:19.62#ibcon#*before return 0, iclass 4, count 0 2006.252.08:13:19.62#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.252.08:13:19.62#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.252.08:13:19.62#ibcon#about to clear, iclass 4 cls_cnt 0 2006.252.08:13:19.62#ibcon#cleared, iclass 4 cls_cnt 0 2006.252.08:13:19.62$vc4f8/va=6,7 2006.252.08:13:19.62#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.252.08:13:19.62#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.252.08:13:19.62#ibcon#ireg 11 cls_cnt 2 2006.252.08:13:19.62#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.252.08:13:19.66#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.252.08:13:19.66#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.252.08:13:19.66#ibcon#enter wrdev, iclass 6, count 2 2006.252.08:13:19.66#ibcon#first serial, iclass 6, count 2 2006.252.08:13:19.66#ibcon#enter sib2, iclass 6, count 2 2006.252.08:13:19.66#ibcon#flushed, iclass 6, count 2 2006.252.08:13:19.66#ibcon#about to write, iclass 6, count 2 2006.252.08:13:19.66#ibcon#wrote, iclass 6, count 2 2006.252.08:13:19.66#ibcon#about to read 3, iclass 6, count 2 2006.252.08:13:19.68#ibcon#read 3, iclass 6, count 2 2006.252.08:13:19.68#ibcon#about to read 4, iclass 6, count 2 2006.252.08:13:19.68#ibcon#read 4, iclass 6, count 2 2006.252.08:13:19.68#ibcon#about to read 5, iclass 6, count 2 2006.252.08:13:19.68#ibcon#read 5, iclass 6, count 2 2006.252.08:13:19.68#ibcon#about to read 6, iclass 6, count 2 2006.252.08:13:19.68#ibcon#read 6, iclass 6, count 2 2006.252.08:13:19.68#ibcon#end of sib2, iclass 6, count 2 2006.252.08:13:19.68#ibcon#*mode == 0, iclass 6, count 2 2006.252.08:13:19.68#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.252.08:13:19.68#ibcon#[25=AT06-07\r\n] 2006.252.08:13:19.68#ibcon#*before write, iclass 6, count 2 2006.252.08:13:19.69#ibcon#enter sib2, iclass 6, count 2 2006.252.08:13:19.69#ibcon#flushed, iclass 6, count 2 2006.252.08:13:19.69#ibcon#about to write, iclass 6, count 2 2006.252.08:13:19.69#ibcon#wrote, iclass 6, count 2 2006.252.08:13:19.69#ibcon#about to read 3, iclass 6, count 2 2006.252.08:13:19.71#ibcon#read 3, iclass 6, count 2 2006.252.08:13:19.71#ibcon#about to read 4, iclass 6, count 2 2006.252.08:13:19.71#ibcon#read 4, iclass 6, count 2 2006.252.08:13:19.71#ibcon#about to read 5, iclass 6, count 2 2006.252.08:13:19.71#ibcon#read 5, iclass 6, count 2 2006.252.08:13:19.71#ibcon#about to read 6, iclass 6, count 2 2006.252.08:13:19.71#ibcon#read 6, iclass 6, count 2 2006.252.08:13:19.71#ibcon#end of sib2, iclass 6, count 2 2006.252.08:13:19.71#ibcon#*after write, iclass 6, count 2 2006.252.08:13:19.72#ibcon#*before return 0, iclass 6, count 2 2006.252.08:13:19.72#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.252.08:13:19.72#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.252.08:13:19.72#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.252.08:13:19.72#ibcon#ireg 7 cls_cnt 0 2006.252.08:13:19.72#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.252.08:13:19.83#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.252.08:13:19.83#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.252.08:13:19.83#ibcon#enter wrdev, iclass 6, count 0 2006.252.08:13:19.83#ibcon#first serial, iclass 6, count 0 2006.252.08:13:19.83#ibcon#enter sib2, iclass 6, count 0 2006.252.08:13:19.83#ibcon#flushed, iclass 6, count 0 2006.252.08:13:19.83#ibcon#about to write, iclass 6, count 0 2006.252.08:13:19.83#ibcon#wrote, iclass 6, count 0 2006.252.08:13:19.83#ibcon#about to read 3, iclass 6, count 0 2006.252.08:13:19.85#ibcon#read 3, iclass 6, count 0 2006.252.08:13:19.85#ibcon#about to read 4, iclass 6, count 0 2006.252.08:13:19.85#ibcon#read 4, iclass 6, count 0 2006.252.08:13:19.85#ibcon#about to read 5, iclass 6, count 0 2006.252.08:13:19.85#ibcon#read 5, iclass 6, count 0 2006.252.08:13:19.85#ibcon#about to read 6, iclass 6, count 0 2006.252.08:13:19.85#ibcon#read 6, iclass 6, count 0 2006.252.08:13:19.85#ibcon#end of sib2, iclass 6, count 0 2006.252.08:13:19.85#ibcon#*mode == 0, iclass 6, count 0 2006.252.08:13:19.85#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.252.08:13:19.85#ibcon#[25=USB\r\n] 2006.252.08:13:19.85#ibcon#*before write, iclass 6, count 0 2006.252.08:13:19.86#ibcon#enter sib2, iclass 6, count 0 2006.252.08:13:19.86#ibcon#flushed, iclass 6, count 0 2006.252.08:13:19.86#ibcon#about to write, iclass 6, count 0 2006.252.08:13:19.86#ibcon#wrote, iclass 6, count 0 2006.252.08:13:19.86#ibcon#about to read 3, iclass 6, count 0 2006.252.08:13:19.88#ibcon#read 3, iclass 6, count 0 2006.252.08:13:19.88#ibcon#about to read 4, iclass 6, count 0 2006.252.08:13:19.88#ibcon#read 4, iclass 6, count 0 2006.252.08:13:19.88#ibcon#about to read 5, iclass 6, count 0 2006.252.08:13:19.88#ibcon#read 5, iclass 6, count 0 2006.252.08:13:19.88#ibcon#about to read 6, iclass 6, count 0 2006.252.08:13:19.88#ibcon#read 6, iclass 6, count 0 2006.252.08:13:19.88#ibcon#end of sib2, iclass 6, count 0 2006.252.08:13:19.88#ibcon#*after write, iclass 6, count 0 2006.252.08:13:19.88#ibcon#*before return 0, iclass 6, count 0 2006.252.08:13:19.88#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.252.08:13:19.89#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.252.08:13:19.89#ibcon#about to clear, iclass 6 cls_cnt 0 2006.252.08:13:19.89#ibcon#cleared, iclass 6 cls_cnt 0 2006.252.08:13:19.89$vc4f8/valo=7,832.99 2006.252.08:13:19.89#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.252.08:13:19.89#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.252.08:13:19.89#ibcon#ireg 17 cls_cnt 0 2006.252.08:13:19.89#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.252.08:13:19.89#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.252.08:13:19.89#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.252.08:13:19.89#ibcon#enter wrdev, iclass 10, count 0 2006.252.08:13:19.89#ibcon#first serial, iclass 10, count 0 2006.252.08:13:19.89#ibcon#enter sib2, iclass 10, count 0 2006.252.08:13:19.89#ibcon#flushed, iclass 10, count 0 2006.252.08:13:19.89#ibcon#about to write, iclass 10, count 0 2006.252.08:13:19.89#ibcon#wrote, iclass 10, count 0 2006.252.08:13:19.89#ibcon#about to read 3, iclass 10, count 0 2006.252.08:13:19.90#ibcon#read 3, iclass 10, count 0 2006.252.08:13:19.90#ibcon#about to read 4, iclass 10, count 0 2006.252.08:13:19.90#ibcon#read 4, iclass 10, count 0 2006.252.08:13:19.90#ibcon#about to read 5, iclass 10, count 0 2006.252.08:13:19.90#ibcon#read 5, iclass 10, count 0 2006.252.08:13:19.90#ibcon#about to read 6, iclass 10, count 0 2006.252.08:13:19.90#ibcon#read 6, iclass 10, count 0 2006.252.08:13:19.90#ibcon#end of sib2, iclass 10, count 0 2006.252.08:13:19.90#ibcon#*mode == 0, iclass 10, count 0 2006.252.08:13:19.90#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.252.08:13:19.90#ibcon#[26=FRQ=07,832.99\r\n] 2006.252.08:13:19.90#ibcon#*before write, iclass 10, count 0 2006.252.08:13:19.91#ibcon#enter sib2, iclass 10, count 0 2006.252.08:13:19.91#ibcon#flushed, iclass 10, count 0 2006.252.08:13:19.91#ibcon#about to write, iclass 10, count 0 2006.252.08:13:19.91#ibcon#wrote, iclass 10, count 0 2006.252.08:13:19.91#ibcon#about to read 3, iclass 10, count 0 2006.252.08:13:19.94#abcon#<5=/05 3.2 6.1 27.30 901011.1\r\n> 2006.252.08:13:19.95#ibcon#read 3, iclass 10, count 0 2006.252.08:13:19.95#ibcon#about to read 4, iclass 10, count 0 2006.252.08:13:19.95#ibcon#read 4, iclass 10, count 0 2006.252.08:13:19.95#ibcon#about to read 5, iclass 10, count 0 2006.252.08:13:19.95#ibcon#read 5, iclass 10, count 0 2006.252.08:13:19.95#ibcon#about to read 6, iclass 10, count 0 2006.252.08:13:19.95#ibcon#read 6, iclass 10, count 0 2006.252.08:13:19.95#ibcon#end of sib2, iclass 10, count 0 2006.252.08:13:19.95#ibcon#*after write, iclass 10, count 0 2006.252.08:13:19.95#ibcon#*before return 0, iclass 10, count 0 2006.252.08:13:19.95#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.252.08:13:19.95#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.252.08:13:19.95#ibcon#about to clear, iclass 10 cls_cnt 0 2006.252.08:13:19.95#ibcon#cleared, iclass 10 cls_cnt 0 2006.252.08:13:19.95$vc4f8/va=7,7 2006.252.08:13:19.95#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.252.08:13:19.95#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.252.08:13:19.95#ibcon#ireg 11 cls_cnt 2 2006.252.08:13:19.95#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.252.08:13:19.96#abcon#{5=INTERFACE CLEAR} 2006.252.08:13:20.01#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.252.08:13:20.01#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.252.08:13:20.01#ibcon#enter wrdev, iclass 15, count 2 2006.252.08:13:20.01#ibcon#first serial, iclass 15, count 2 2006.252.08:13:20.01#ibcon#enter sib2, iclass 15, count 2 2006.252.08:13:20.01#ibcon#flushed, iclass 15, count 2 2006.252.08:13:20.01#ibcon#about to write, iclass 15, count 2 2006.252.08:13:20.01#ibcon#wrote, iclass 15, count 2 2006.252.08:13:20.01#ibcon#about to read 3, iclass 15, count 2 2006.252.08:13:20.02#ibcon#read 3, iclass 15, count 2 2006.252.08:13:20.02#ibcon#about to read 4, iclass 15, count 2 2006.252.08:13:20.02#ibcon#read 4, iclass 15, count 2 2006.252.08:13:20.02#ibcon#about to read 5, iclass 15, count 2 2006.252.08:13:20.02#ibcon#read 5, iclass 15, count 2 2006.252.08:13:20.02#ibcon#about to read 6, iclass 15, count 2 2006.252.08:13:20.02#ibcon#read 6, iclass 15, count 2 2006.252.08:13:20.02#ibcon#end of sib2, iclass 15, count 2 2006.252.08:13:20.02#ibcon#*mode == 0, iclass 15, count 2 2006.252.08:13:20.02#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.252.08:13:20.02#ibcon#[25=AT07-07\r\n] 2006.252.08:13:20.02#ibcon#*before write, iclass 15, count 2 2006.252.08:13:20.02#ibcon#enter sib2, iclass 15, count 2 2006.252.08:13:20.03#ibcon#flushed, iclass 15, count 2 2006.252.08:13:20.03#ibcon#about to write, iclass 15, count 2 2006.252.08:13:20.03#ibcon#wrote, iclass 15, count 2 2006.252.08:13:20.03#ibcon#about to read 3, iclass 15, count 2 2006.252.08:13:20.03#abcon#[5=S1D000X0/0*\r\n] 2006.252.08:13:20.05#ibcon#read 3, iclass 15, count 2 2006.252.08:13:20.05#ibcon#about to read 4, iclass 15, count 2 2006.252.08:13:20.05#ibcon#read 4, iclass 15, count 2 2006.252.08:13:20.05#ibcon#about to read 5, iclass 15, count 2 2006.252.08:13:20.05#ibcon#read 5, iclass 15, count 2 2006.252.08:13:20.05#ibcon#about to read 6, iclass 15, count 2 2006.252.08:13:20.05#ibcon#read 6, iclass 15, count 2 2006.252.08:13:20.05#ibcon#end of sib2, iclass 15, count 2 2006.252.08:13:20.05#ibcon#*after write, iclass 15, count 2 2006.252.08:13:20.06#ibcon#*before return 0, iclass 15, count 2 2006.252.08:13:20.06#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.252.08:13:20.06#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.252.08:13:20.06#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.252.08:13:20.06#ibcon#ireg 7 cls_cnt 0 2006.252.08:13:20.06#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.252.08:13:20.17#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.252.08:13:20.17#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.252.08:13:20.17#ibcon#enter wrdev, iclass 15, count 0 2006.252.08:13:20.17#ibcon#first serial, iclass 15, count 0 2006.252.08:13:20.17#ibcon#enter sib2, iclass 15, count 0 2006.252.08:13:20.17#ibcon#flushed, iclass 15, count 0 2006.252.08:13:20.17#ibcon#about to write, iclass 15, count 0 2006.252.08:13:20.17#ibcon#wrote, iclass 15, count 0 2006.252.08:13:20.17#ibcon#about to read 3, iclass 15, count 0 2006.252.08:13:20.19#ibcon#read 3, iclass 15, count 0 2006.252.08:13:20.19#ibcon#about to read 4, iclass 15, count 0 2006.252.08:13:20.19#ibcon#read 4, iclass 15, count 0 2006.252.08:13:20.19#ibcon#about to read 5, iclass 15, count 0 2006.252.08:13:20.19#ibcon#read 5, iclass 15, count 0 2006.252.08:13:20.19#ibcon#about to read 6, iclass 15, count 0 2006.252.08:13:20.19#ibcon#read 6, iclass 15, count 0 2006.252.08:13:20.19#ibcon#end of sib2, iclass 15, count 0 2006.252.08:13:20.19#ibcon#*mode == 0, iclass 15, count 0 2006.252.08:13:20.19#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.252.08:13:20.19#ibcon#[25=USB\r\n] 2006.252.08:13:20.19#ibcon#*before write, iclass 15, count 0 2006.252.08:13:20.20#ibcon#enter sib2, iclass 15, count 0 2006.252.08:13:20.20#ibcon#flushed, iclass 15, count 0 2006.252.08:13:20.20#ibcon#about to write, iclass 15, count 0 2006.252.08:13:20.20#ibcon#wrote, iclass 15, count 0 2006.252.08:13:20.20#ibcon#about to read 3, iclass 15, count 0 2006.252.08:13:20.22#ibcon#read 3, iclass 15, count 0 2006.252.08:13:20.22#ibcon#about to read 4, iclass 15, count 0 2006.252.08:13:20.22#ibcon#read 4, iclass 15, count 0 2006.252.08:13:20.22#ibcon#about to read 5, iclass 15, count 0 2006.252.08:13:20.22#ibcon#read 5, iclass 15, count 0 2006.252.08:13:20.22#ibcon#about to read 6, iclass 15, count 0 2006.252.08:13:20.22#ibcon#read 6, iclass 15, count 0 2006.252.08:13:20.22#ibcon#end of sib2, iclass 15, count 0 2006.252.08:13:20.22#ibcon#*after write, iclass 15, count 0 2006.252.08:13:20.22#ibcon#*before return 0, iclass 15, count 0 2006.252.08:13:20.22#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.252.08:13:20.22#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.252.08:13:20.23#ibcon#about to clear, iclass 15 cls_cnt 0 2006.252.08:13:20.23#ibcon#cleared, iclass 15 cls_cnt 0 2006.252.08:13:20.23$vc4f8/valo=8,852.99 2006.252.08:13:20.23#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.252.08:13:20.23#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.252.08:13:20.23#ibcon#ireg 17 cls_cnt 0 2006.252.08:13:20.23#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.252.08:13:20.23#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.252.08:13:20.23#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.252.08:13:20.23#ibcon#enter wrdev, iclass 18, count 0 2006.252.08:13:20.23#ibcon#first serial, iclass 18, count 0 2006.252.08:13:20.23#ibcon#enter sib2, iclass 18, count 0 2006.252.08:13:20.23#ibcon#flushed, iclass 18, count 0 2006.252.08:13:20.23#ibcon#about to write, iclass 18, count 0 2006.252.08:13:20.23#ibcon#wrote, iclass 18, count 0 2006.252.08:13:20.23#ibcon#about to read 3, iclass 18, count 0 2006.252.08:13:20.24#ibcon#read 3, iclass 18, count 0 2006.252.08:13:20.24#ibcon#about to read 4, iclass 18, count 0 2006.252.08:13:20.24#ibcon#read 4, iclass 18, count 0 2006.252.08:13:20.24#ibcon#about to read 5, iclass 18, count 0 2006.252.08:13:20.24#ibcon#read 5, iclass 18, count 0 2006.252.08:13:20.24#ibcon#about to read 6, iclass 18, count 0 2006.252.08:13:20.24#ibcon#read 6, iclass 18, count 0 2006.252.08:13:20.24#ibcon#end of sib2, iclass 18, count 0 2006.252.08:13:20.24#ibcon#*mode == 0, iclass 18, count 0 2006.252.08:13:20.25#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.252.08:13:20.25#ibcon#[26=FRQ=08,852.99\r\n] 2006.252.08:13:20.25#ibcon#*before write, iclass 18, count 0 2006.252.08:13:20.25#ibcon#enter sib2, iclass 18, count 0 2006.252.08:13:20.25#ibcon#flushed, iclass 18, count 0 2006.252.08:13:20.25#ibcon#about to write, iclass 18, count 0 2006.252.08:13:20.25#ibcon#wrote, iclass 18, count 0 2006.252.08:13:20.25#ibcon#about to read 3, iclass 18, count 0 2006.252.08:13:20.28#ibcon#read 3, iclass 18, count 0 2006.252.08:13:20.28#ibcon#about to read 4, iclass 18, count 0 2006.252.08:13:20.28#ibcon#read 4, iclass 18, count 0 2006.252.08:13:20.28#ibcon#about to read 5, iclass 18, count 0 2006.252.08:13:20.28#ibcon#read 5, iclass 18, count 0 2006.252.08:13:20.28#ibcon#about to read 6, iclass 18, count 0 2006.252.08:13:20.28#ibcon#read 6, iclass 18, count 0 2006.252.08:13:20.28#ibcon#end of sib2, iclass 18, count 0 2006.252.08:13:20.28#ibcon#*after write, iclass 18, count 0 2006.252.08:13:20.28#ibcon#*before return 0, iclass 18, count 0 2006.252.08:13:20.28#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.252.08:13:20.29#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.252.08:13:20.29#ibcon#about to clear, iclass 18 cls_cnt 0 2006.252.08:13:20.29#ibcon#cleared, iclass 18 cls_cnt 0 2006.252.08:13:20.29$vc4f8/va=8,7 2006.252.08:13:20.29#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.252.08:13:20.29#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.252.08:13:20.29#ibcon#ireg 11 cls_cnt 2 2006.252.08:13:20.29#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.252.08:13:20.33#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.252.08:13:20.33#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.252.08:13:20.33#ibcon#enter wrdev, iclass 20, count 2 2006.252.08:13:20.33#ibcon#first serial, iclass 20, count 2 2006.252.08:13:20.33#ibcon#enter sib2, iclass 20, count 2 2006.252.08:13:20.33#ibcon#flushed, iclass 20, count 2 2006.252.08:13:20.33#ibcon#about to write, iclass 20, count 2 2006.252.08:13:20.34#ibcon#wrote, iclass 20, count 2 2006.252.08:13:20.34#ibcon#about to read 3, iclass 20, count 2 2006.252.08:13:20.35#ibcon#read 3, iclass 20, count 2 2006.252.08:13:20.35#ibcon#about to read 4, iclass 20, count 2 2006.252.08:13:20.35#ibcon#read 4, iclass 20, count 2 2006.252.08:13:20.35#ibcon#about to read 5, iclass 20, count 2 2006.252.08:13:20.35#ibcon#read 5, iclass 20, count 2 2006.252.08:13:20.35#ibcon#about to read 6, iclass 20, count 2 2006.252.08:13:20.35#ibcon#read 6, iclass 20, count 2 2006.252.08:13:20.35#ibcon#end of sib2, iclass 20, count 2 2006.252.08:13:20.35#ibcon#*mode == 0, iclass 20, count 2 2006.252.08:13:20.35#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.252.08:13:20.35#ibcon#[25=AT08-07\r\n] 2006.252.08:13:20.35#ibcon#*before write, iclass 20, count 2 2006.252.08:13:20.36#ibcon#enter sib2, iclass 20, count 2 2006.252.08:13:20.36#ibcon#flushed, iclass 20, count 2 2006.252.08:13:20.36#ibcon#about to write, iclass 20, count 2 2006.252.08:13:20.36#ibcon#wrote, iclass 20, count 2 2006.252.08:13:20.36#ibcon#about to read 3, iclass 20, count 2 2006.252.08:13:20.38#ibcon#read 3, iclass 20, count 2 2006.252.08:13:20.38#ibcon#about to read 4, iclass 20, count 2 2006.252.08:13:20.38#ibcon#read 4, iclass 20, count 2 2006.252.08:13:20.38#ibcon#about to read 5, iclass 20, count 2 2006.252.08:13:20.38#ibcon#read 5, iclass 20, count 2 2006.252.08:13:20.38#ibcon#about to read 6, iclass 20, count 2 2006.252.08:13:20.38#ibcon#read 6, iclass 20, count 2 2006.252.08:13:20.38#ibcon#end of sib2, iclass 20, count 2 2006.252.08:13:20.38#ibcon#*after write, iclass 20, count 2 2006.252.08:13:20.38#ibcon#*before return 0, iclass 20, count 2 2006.252.08:13:20.39#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.252.08:13:20.39#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.252.08:13:20.39#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.252.08:13:20.39#ibcon#ireg 7 cls_cnt 0 2006.252.08:13:20.39#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.252.08:13:20.50#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.252.08:13:20.50#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.252.08:13:20.50#ibcon#enter wrdev, iclass 20, count 0 2006.252.08:13:20.50#ibcon#first serial, iclass 20, count 0 2006.252.08:13:20.50#ibcon#enter sib2, iclass 20, count 0 2006.252.08:13:20.50#ibcon#flushed, iclass 20, count 0 2006.252.08:13:20.50#ibcon#about to write, iclass 20, count 0 2006.252.08:13:20.50#ibcon#wrote, iclass 20, count 0 2006.252.08:13:20.50#ibcon#about to read 3, iclass 20, count 0 2006.252.08:13:20.52#ibcon#read 3, iclass 20, count 0 2006.252.08:13:20.52#ibcon#about to read 4, iclass 20, count 0 2006.252.08:13:20.52#ibcon#read 4, iclass 20, count 0 2006.252.08:13:20.52#ibcon#about to read 5, iclass 20, count 0 2006.252.08:13:20.52#ibcon#read 5, iclass 20, count 0 2006.252.08:13:20.52#ibcon#about to read 6, iclass 20, count 0 2006.252.08:13:20.52#ibcon#read 6, iclass 20, count 0 2006.252.08:13:20.52#ibcon#end of sib2, iclass 20, count 0 2006.252.08:13:20.52#ibcon#*mode == 0, iclass 20, count 0 2006.252.08:13:20.52#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.252.08:13:20.52#ibcon#[25=USB\r\n] 2006.252.08:13:20.53#ibcon#*before write, iclass 20, count 0 2006.252.08:13:20.53#ibcon#enter sib2, iclass 20, count 0 2006.252.08:13:20.53#ibcon#flushed, iclass 20, count 0 2006.252.08:13:20.53#ibcon#about to write, iclass 20, count 0 2006.252.08:13:20.53#ibcon#wrote, iclass 20, count 0 2006.252.08:13:20.53#ibcon#about to read 3, iclass 20, count 0 2006.252.08:13:20.55#ibcon#read 3, iclass 20, count 0 2006.252.08:13:20.55#ibcon#about to read 4, iclass 20, count 0 2006.252.08:13:20.55#ibcon#read 4, iclass 20, count 0 2006.252.08:13:20.55#ibcon#about to read 5, iclass 20, count 0 2006.252.08:13:20.55#ibcon#read 5, iclass 20, count 0 2006.252.08:13:20.55#ibcon#about to read 6, iclass 20, count 0 2006.252.08:13:20.55#ibcon#read 6, iclass 20, count 0 2006.252.08:13:20.55#ibcon#end of sib2, iclass 20, count 0 2006.252.08:13:20.55#ibcon#*after write, iclass 20, count 0 2006.252.08:13:20.55#ibcon#*before return 0, iclass 20, count 0 2006.252.08:13:20.55#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.252.08:13:20.56#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.252.08:13:20.56#ibcon#about to clear, iclass 20 cls_cnt 0 2006.252.08:13:20.56#ibcon#cleared, iclass 20 cls_cnt 0 2006.252.08:13:20.56$vc4f8/vblo=1,632.99 2006.252.08:13:20.56#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.252.08:13:20.56#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.252.08:13:20.56#ibcon#ireg 17 cls_cnt 0 2006.252.08:13:20.56#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.252.08:13:20.56#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.252.08:13:20.56#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.252.08:13:20.56#ibcon#enter wrdev, iclass 22, count 0 2006.252.08:13:20.56#ibcon#first serial, iclass 22, count 0 2006.252.08:13:20.56#ibcon#enter sib2, iclass 22, count 0 2006.252.08:13:20.56#ibcon#flushed, iclass 22, count 0 2006.252.08:13:20.56#ibcon#about to write, iclass 22, count 0 2006.252.08:13:20.56#ibcon#wrote, iclass 22, count 0 2006.252.08:13:20.56#ibcon#about to read 3, iclass 22, count 0 2006.252.08:13:20.57#ibcon#read 3, iclass 22, count 0 2006.252.08:13:20.57#ibcon#about to read 4, iclass 22, count 0 2006.252.08:13:20.57#ibcon#read 4, iclass 22, count 0 2006.252.08:13:20.57#ibcon#about to read 5, iclass 22, count 0 2006.252.08:13:20.57#ibcon#read 5, iclass 22, count 0 2006.252.08:13:20.57#ibcon#about to read 6, iclass 22, count 0 2006.252.08:13:20.57#ibcon#read 6, iclass 22, count 0 2006.252.08:13:20.57#ibcon#end of sib2, iclass 22, count 0 2006.252.08:13:20.57#ibcon#*mode == 0, iclass 22, count 0 2006.252.08:13:20.57#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.252.08:13:20.57#ibcon#[28=FRQ=01,632.99\r\n] 2006.252.08:13:20.57#ibcon#*before write, iclass 22, count 0 2006.252.08:13:20.58#ibcon#enter sib2, iclass 22, count 0 2006.252.08:13:20.58#ibcon#flushed, iclass 22, count 0 2006.252.08:13:20.58#ibcon#about to write, iclass 22, count 0 2006.252.08:13:20.58#ibcon#wrote, iclass 22, count 0 2006.252.08:13:20.58#ibcon#about to read 3, iclass 22, count 0 2006.252.08:13:20.61#ibcon#read 3, iclass 22, count 0 2006.252.08:13:20.61#ibcon#about to read 4, iclass 22, count 0 2006.252.08:13:20.61#ibcon#read 4, iclass 22, count 0 2006.252.08:13:20.61#ibcon#about to read 5, iclass 22, count 0 2006.252.08:13:20.61#ibcon#read 5, iclass 22, count 0 2006.252.08:13:20.61#ibcon#about to read 6, iclass 22, count 0 2006.252.08:13:20.61#ibcon#read 6, iclass 22, count 0 2006.252.08:13:20.61#ibcon#end of sib2, iclass 22, count 0 2006.252.08:13:20.61#ibcon#*after write, iclass 22, count 0 2006.252.08:13:20.61#ibcon#*before return 0, iclass 22, count 0 2006.252.08:13:20.62#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.252.08:13:20.62#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.252.08:13:20.62#ibcon#about to clear, iclass 22 cls_cnt 0 2006.252.08:13:20.62#ibcon#cleared, iclass 22 cls_cnt 0 2006.252.08:13:20.62$vc4f8/vb=1,4 2006.252.08:13:20.62#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.252.08:13:20.62#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.252.08:13:20.62#ibcon#ireg 11 cls_cnt 2 2006.252.08:13:20.62#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.252.08:13:20.62#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.252.08:13:20.62#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.252.08:13:20.62#ibcon#enter wrdev, iclass 24, count 2 2006.252.08:13:20.62#ibcon#first serial, iclass 24, count 2 2006.252.08:13:20.62#ibcon#enter sib2, iclass 24, count 2 2006.252.08:13:20.62#ibcon#flushed, iclass 24, count 2 2006.252.08:13:20.62#ibcon#about to write, iclass 24, count 2 2006.252.08:13:20.62#ibcon#wrote, iclass 24, count 2 2006.252.08:13:20.62#ibcon#about to read 3, iclass 24, count 2 2006.252.08:13:20.63#ibcon#read 3, iclass 24, count 2 2006.252.08:13:20.63#ibcon#about to read 4, iclass 24, count 2 2006.252.08:13:20.63#ibcon#read 4, iclass 24, count 2 2006.252.08:13:20.63#ibcon#about to read 5, iclass 24, count 2 2006.252.08:13:20.63#ibcon#read 5, iclass 24, count 2 2006.252.08:13:20.63#ibcon#about to read 6, iclass 24, count 2 2006.252.08:13:20.63#ibcon#read 6, iclass 24, count 2 2006.252.08:13:20.63#ibcon#end of sib2, iclass 24, count 2 2006.252.08:13:20.63#ibcon#*mode == 0, iclass 24, count 2 2006.252.08:13:20.63#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.252.08:13:20.63#ibcon#[27=AT01-04\r\n] 2006.252.08:13:20.63#ibcon#*before write, iclass 24, count 2 2006.252.08:13:20.64#ibcon#enter sib2, iclass 24, count 2 2006.252.08:13:20.64#ibcon#flushed, iclass 24, count 2 2006.252.08:13:20.64#ibcon#about to write, iclass 24, count 2 2006.252.08:13:20.64#ibcon#wrote, iclass 24, count 2 2006.252.08:13:20.64#ibcon#about to read 3, iclass 24, count 2 2006.252.08:13:20.66#ibcon#read 3, iclass 24, count 2 2006.252.08:13:20.66#ibcon#about to read 4, iclass 24, count 2 2006.252.08:13:20.66#ibcon#read 4, iclass 24, count 2 2006.252.08:13:20.66#ibcon#about to read 5, iclass 24, count 2 2006.252.08:13:20.66#ibcon#read 5, iclass 24, count 2 2006.252.08:13:20.66#ibcon#about to read 6, iclass 24, count 2 2006.252.08:13:20.66#ibcon#read 6, iclass 24, count 2 2006.252.08:13:20.66#ibcon#end of sib2, iclass 24, count 2 2006.252.08:13:20.66#ibcon#*after write, iclass 24, count 2 2006.252.08:13:20.66#ibcon#*before return 0, iclass 24, count 2 2006.252.08:13:20.67#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.252.08:13:20.67#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.252.08:13:20.67#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.252.08:13:20.67#ibcon#ireg 7 cls_cnt 0 2006.252.08:13:20.67#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.252.08:13:20.78#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.252.08:13:20.78#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.252.08:13:20.78#ibcon#enter wrdev, iclass 24, count 0 2006.252.08:13:20.78#ibcon#first serial, iclass 24, count 0 2006.252.08:13:20.78#ibcon#enter sib2, iclass 24, count 0 2006.252.08:13:20.78#ibcon#flushed, iclass 24, count 0 2006.252.08:13:20.78#ibcon#about to write, iclass 24, count 0 2006.252.08:13:20.78#ibcon#wrote, iclass 24, count 0 2006.252.08:13:20.78#ibcon#about to read 3, iclass 24, count 0 2006.252.08:13:20.80#ibcon#read 3, iclass 24, count 0 2006.252.08:13:20.80#ibcon#about to read 4, iclass 24, count 0 2006.252.08:13:20.80#ibcon#read 4, iclass 24, count 0 2006.252.08:13:20.80#ibcon#about to read 5, iclass 24, count 0 2006.252.08:13:20.80#ibcon#read 5, iclass 24, count 0 2006.252.08:13:20.80#ibcon#about to read 6, iclass 24, count 0 2006.252.08:13:20.80#ibcon#read 6, iclass 24, count 0 2006.252.08:13:20.80#ibcon#end of sib2, iclass 24, count 0 2006.252.08:13:20.80#ibcon#*mode == 0, iclass 24, count 0 2006.252.08:13:20.80#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.252.08:13:20.80#ibcon#[27=USB\r\n] 2006.252.08:13:20.81#ibcon#*before write, iclass 24, count 0 2006.252.08:13:20.81#ibcon#enter sib2, iclass 24, count 0 2006.252.08:13:20.81#ibcon#flushed, iclass 24, count 0 2006.252.08:13:20.81#ibcon#about to write, iclass 24, count 0 2006.252.08:13:20.81#ibcon#wrote, iclass 24, count 0 2006.252.08:13:20.81#ibcon#about to read 3, iclass 24, count 0 2006.252.08:13:20.83#ibcon#read 3, iclass 24, count 0 2006.252.08:13:20.83#ibcon#about to read 4, iclass 24, count 0 2006.252.08:13:20.83#ibcon#read 4, iclass 24, count 0 2006.252.08:13:20.83#ibcon#about to read 5, iclass 24, count 0 2006.252.08:13:20.83#ibcon#read 5, iclass 24, count 0 2006.252.08:13:20.83#ibcon#about to read 6, iclass 24, count 0 2006.252.08:13:20.83#ibcon#read 6, iclass 24, count 0 2006.252.08:13:20.83#ibcon#end of sib2, iclass 24, count 0 2006.252.08:13:20.83#ibcon#*after write, iclass 24, count 0 2006.252.08:13:20.83#ibcon#*before return 0, iclass 24, count 0 2006.252.08:13:20.83#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.252.08:13:20.84#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.252.08:13:20.84#ibcon#about to clear, iclass 24 cls_cnt 0 2006.252.08:13:20.84#ibcon#cleared, iclass 24 cls_cnt 0 2006.252.08:13:20.84$vc4f8/vblo=2,640.99 2006.252.08:13:20.84#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.252.08:13:20.84#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.252.08:13:20.84#ibcon#ireg 17 cls_cnt 0 2006.252.08:13:20.84#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.252.08:13:20.84#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.252.08:13:20.84#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.252.08:13:20.84#ibcon#enter wrdev, iclass 26, count 0 2006.252.08:13:20.84#ibcon#first serial, iclass 26, count 0 2006.252.08:13:20.84#ibcon#enter sib2, iclass 26, count 0 2006.252.08:13:20.84#ibcon#flushed, iclass 26, count 0 2006.252.08:13:20.84#ibcon#about to write, iclass 26, count 0 2006.252.08:13:20.84#ibcon#wrote, iclass 26, count 0 2006.252.08:13:20.84#ibcon#about to read 3, iclass 26, count 0 2006.252.08:13:20.85#ibcon#read 3, iclass 26, count 0 2006.252.08:13:20.85#ibcon#about to read 4, iclass 26, count 0 2006.252.08:13:20.85#ibcon#read 4, iclass 26, count 0 2006.252.08:13:20.85#ibcon#about to read 5, iclass 26, count 0 2006.252.08:13:20.85#ibcon#read 5, iclass 26, count 0 2006.252.08:13:20.85#ibcon#about to read 6, iclass 26, count 0 2006.252.08:13:20.85#ibcon#read 6, iclass 26, count 0 2006.252.08:13:20.85#ibcon#end of sib2, iclass 26, count 0 2006.252.08:13:20.85#ibcon#*mode == 0, iclass 26, count 0 2006.252.08:13:20.85#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.252.08:13:20.85#ibcon#[28=FRQ=02,640.99\r\n] 2006.252.08:13:20.85#ibcon#*before write, iclass 26, count 0 2006.252.08:13:20.85#ibcon#enter sib2, iclass 26, count 0 2006.252.08:13:20.86#ibcon#flushed, iclass 26, count 0 2006.252.08:13:20.86#ibcon#about to write, iclass 26, count 0 2006.252.08:13:20.86#ibcon#wrote, iclass 26, count 0 2006.252.08:13:20.86#ibcon#about to read 3, iclass 26, count 0 2006.252.08:13:20.89#ibcon#read 3, iclass 26, count 0 2006.252.08:13:20.89#ibcon#about to read 4, iclass 26, count 0 2006.252.08:13:20.89#ibcon#read 4, iclass 26, count 0 2006.252.08:13:20.89#ibcon#about to read 5, iclass 26, count 0 2006.252.08:13:20.89#ibcon#read 5, iclass 26, count 0 2006.252.08:13:20.89#ibcon#about to read 6, iclass 26, count 0 2006.252.08:13:20.89#ibcon#read 6, iclass 26, count 0 2006.252.08:13:20.89#ibcon#end of sib2, iclass 26, count 0 2006.252.08:13:20.89#ibcon#*after write, iclass 26, count 0 2006.252.08:13:20.89#ibcon#*before return 0, iclass 26, count 0 2006.252.08:13:20.90#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.252.08:13:20.90#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.252.08:13:20.90#ibcon#about to clear, iclass 26 cls_cnt 0 2006.252.08:13:20.90#ibcon#cleared, iclass 26 cls_cnt 0 2006.252.08:13:20.90$vc4f8/vb=2,5 2006.252.08:13:20.90#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.252.08:13:20.90#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.252.08:13:20.90#ibcon#ireg 11 cls_cnt 2 2006.252.08:13:20.90#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.252.08:13:20.94#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.252.08:13:20.94#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.252.08:13:20.94#ibcon#enter wrdev, iclass 28, count 2 2006.252.08:13:20.94#ibcon#first serial, iclass 28, count 2 2006.252.08:13:20.94#ibcon#enter sib2, iclass 28, count 2 2006.252.08:13:20.94#ibcon#flushed, iclass 28, count 2 2006.252.08:13:20.94#ibcon#about to write, iclass 28, count 2 2006.252.08:13:20.94#ibcon#wrote, iclass 28, count 2 2006.252.08:13:20.94#ibcon#about to read 3, iclass 28, count 2 2006.252.08:13:20.97#ibcon#read 3, iclass 28, count 2 2006.252.08:13:20.97#ibcon#about to read 4, iclass 28, count 2 2006.252.08:13:20.97#ibcon#read 4, iclass 28, count 2 2006.252.08:13:20.97#ibcon#about to read 5, iclass 28, count 2 2006.252.08:13:20.97#ibcon#read 5, iclass 28, count 2 2006.252.08:13:20.97#ibcon#about to read 6, iclass 28, count 2 2006.252.08:13:20.97#ibcon#read 6, iclass 28, count 2 2006.252.08:13:20.97#ibcon#end of sib2, iclass 28, count 2 2006.252.08:13:20.97#ibcon#*mode == 0, iclass 28, count 2 2006.252.08:13:20.97#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.252.08:13:20.97#ibcon#[27=AT02-05\r\n] 2006.252.08:13:20.97#ibcon#*before write, iclass 28, count 2 2006.252.08:13:20.97#ibcon#enter sib2, iclass 28, count 2 2006.252.08:13:20.97#ibcon#flushed, iclass 28, count 2 2006.252.08:13:20.97#ibcon#about to write, iclass 28, count 2 2006.252.08:13:20.97#ibcon#wrote, iclass 28, count 2 2006.252.08:13:20.97#ibcon#about to read 3, iclass 28, count 2 2006.252.08:13:21.00#ibcon#read 3, iclass 28, count 2 2006.252.08:13:21.00#ibcon#about to read 4, iclass 28, count 2 2006.252.08:13:21.00#ibcon#read 4, iclass 28, count 2 2006.252.08:13:21.00#ibcon#about to read 5, iclass 28, count 2 2006.252.08:13:21.00#ibcon#read 5, iclass 28, count 2 2006.252.08:13:21.00#ibcon#about to read 6, iclass 28, count 2 2006.252.08:13:21.00#ibcon#read 6, iclass 28, count 2 2006.252.08:13:21.00#ibcon#end of sib2, iclass 28, count 2 2006.252.08:13:21.00#ibcon#*after write, iclass 28, count 2 2006.252.08:13:21.01#ibcon#*before return 0, iclass 28, count 2 2006.252.08:13:21.01#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.252.08:13:21.01#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.252.08:13:21.01#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.252.08:13:21.01#ibcon#ireg 7 cls_cnt 0 2006.252.08:13:21.01#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.252.08:13:21.12#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.252.08:13:21.12#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.252.08:13:21.12#ibcon#enter wrdev, iclass 28, count 0 2006.252.08:13:21.12#ibcon#first serial, iclass 28, count 0 2006.252.08:13:21.12#ibcon#enter sib2, iclass 28, count 0 2006.252.08:13:21.12#ibcon#flushed, iclass 28, count 0 2006.252.08:13:21.12#ibcon#about to write, iclass 28, count 0 2006.252.08:13:21.12#ibcon#wrote, iclass 28, count 0 2006.252.08:13:21.12#ibcon#about to read 3, iclass 28, count 0 2006.252.08:13:21.14#ibcon#read 3, iclass 28, count 0 2006.252.08:13:21.14#ibcon#about to read 4, iclass 28, count 0 2006.252.08:13:21.14#ibcon#read 4, iclass 28, count 0 2006.252.08:13:21.14#ibcon#about to read 5, iclass 28, count 0 2006.252.08:13:21.14#ibcon#read 5, iclass 28, count 0 2006.252.08:13:21.14#ibcon#about to read 6, iclass 28, count 0 2006.252.08:13:21.14#ibcon#read 6, iclass 28, count 0 2006.252.08:13:21.14#ibcon#end of sib2, iclass 28, count 0 2006.252.08:13:21.14#ibcon#*mode == 0, iclass 28, count 0 2006.252.08:13:21.14#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.252.08:13:21.14#ibcon#[27=USB\r\n] 2006.252.08:13:21.14#ibcon#*before write, iclass 28, count 0 2006.252.08:13:21.15#ibcon#enter sib2, iclass 28, count 0 2006.252.08:13:21.15#ibcon#flushed, iclass 28, count 0 2006.252.08:13:21.15#ibcon#about to write, iclass 28, count 0 2006.252.08:13:21.15#ibcon#wrote, iclass 28, count 0 2006.252.08:13:21.15#ibcon#about to read 3, iclass 28, count 0 2006.252.08:13:21.17#ibcon#read 3, iclass 28, count 0 2006.252.08:13:21.17#ibcon#about to read 4, iclass 28, count 0 2006.252.08:13:21.17#ibcon#read 4, iclass 28, count 0 2006.252.08:13:21.17#ibcon#about to read 5, iclass 28, count 0 2006.252.08:13:21.17#ibcon#read 5, iclass 28, count 0 2006.252.08:13:21.17#ibcon#about to read 6, iclass 28, count 0 2006.252.08:13:21.17#ibcon#read 6, iclass 28, count 0 2006.252.08:13:21.17#ibcon#end of sib2, iclass 28, count 0 2006.252.08:13:21.17#ibcon#*after write, iclass 28, count 0 2006.252.08:13:21.17#ibcon#*before return 0, iclass 28, count 0 2006.252.08:13:21.17#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.252.08:13:21.18#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.252.08:13:21.18#ibcon#about to clear, iclass 28 cls_cnt 0 2006.252.08:13:21.18#ibcon#cleared, iclass 28 cls_cnt 0 2006.252.08:13:21.18$vc4f8/vblo=3,656.99 2006.252.08:13:21.18#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.252.08:13:21.18#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.252.08:13:21.18#ibcon#ireg 17 cls_cnt 0 2006.252.08:13:21.18#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.252.08:13:21.18#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.252.08:13:21.18#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.252.08:13:21.18#ibcon#enter wrdev, iclass 30, count 0 2006.252.08:13:21.18#ibcon#first serial, iclass 30, count 0 2006.252.08:13:21.18#ibcon#enter sib2, iclass 30, count 0 2006.252.08:13:21.18#ibcon#flushed, iclass 30, count 0 2006.252.08:13:21.18#ibcon#about to write, iclass 30, count 0 2006.252.08:13:21.18#ibcon#wrote, iclass 30, count 0 2006.252.08:13:21.18#ibcon#about to read 3, iclass 30, count 0 2006.252.08:13:21.19#ibcon#read 3, iclass 30, count 0 2006.252.08:13:21.19#ibcon#about to read 4, iclass 30, count 0 2006.252.08:13:21.19#ibcon#read 4, iclass 30, count 0 2006.252.08:13:21.19#ibcon#about to read 5, iclass 30, count 0 2006.252.08:13:21.19#ibcon#read 5, iclass 30, count 0 2006.252.08:13:21.19#ibcon#about to read 6, iclass 30, count 0 2006.252.08:13:21.19#ibcon#read 6, iclass 30, count 0 2006.252.08:13:21.19#ibcon#end of sib2, iclass 30, count 0 2006.252.08:13:21.19#ibcon#*mode == 0, iclass 30, count 0 2006.252.08:13:21.19#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.252.08:13:21.19#ibcon#[28=FRQ=03,656.99\r\n] 2006.252.08:13:21.19#ibcon#*before write, iclass 30, count 0 2006.252.08:13:21.20#ibcon#enter sib2, iclass 30, count 0 2006.252.08:13:21.20#ibcon#flushed, iclass 30, count 0 2006.252.08:13:21.20#ibcon#about to write, iclass 30, count 0 2006.252.08:13:21.20#ibcon#wrote, iclass 30, count 0 2006.252.08:13:21.20#ibcon#about to read 3, iclass 30, count 0 2006.252.08:13:21.23#ibcon#read 3, iclass 30, count 0 2006.252.08:13:21.23#ibcon#about to read 4, iclass 30, count 0 2006.252.08:13:21.23#ibcon#read 4, iclass 30, count 0 2006.252.08:13:21.23#ibcon#about to read 5, iclass 30, count 0 2006.252.08:13:21.23#ibcon#read 5, iclass 30, count 0 2006.252.08:13:21.23#ibcon#about to read 6, iclass 30, count 0 2006.252.08:13:21.23#ibcon#read 6, iclass 30, count 0 2006.252.08:13:21.23#ibcon#end of sib2, iclass 30, count 0 2006.252.08:13:21.23#ibcon#*after write, iclass 30, count 0 2006.252.08:13:21.23#ibcon#*before return 0, iclass 30, count 0 2006.252.08:13:21.24#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.252.08:13:21.24#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.252.08:13:21.24#ibcon#about to clear, iclass 30 cls_cnt 0 2006.252.08:13:21.24#ibcon#cleared, iclass 30 cls_cnt 0 2006.252.08:13:21.24$vc4f8/vb=3,4 2006.252.08:13:21.24#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.252.08:13:21.24#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.252.08:13:21.24#ibcon#ireg 11 cls_cnt 2 2006.252.08:13:21.24#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.252.08:13:21.29#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.252.08:13:21.29#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.252.08:13:21.29#ibcon#enter wrdev, iclass 32, count 2 2006.252.08:13:21.29#ibcon#first serial, iclass 32, count 2 2006.252.08:13:21.29#ibcon#enter sib2, iclass 32, count 2 2006.252.08:13:21.29#ibcon#flushed, iclass 32, count 2 2006.252.08:13:21.29#ibcon#about to write, iclass 32, count 2 2006.252.08:13:21.29#ibcon#wrote, iclass 32, count 2 2006.252.08:13:21.29#ibcon#about to read 3, iclass 32, count 2 2006.252.08:13:21.31#ibcon#read 3, iclass 32, count 2 2006.252.08:13:21.31#ibcon#about to read 4, iclass 32, count 2 2006.252.08:13:21.31#ibcon#read 4, iclass 32, count 2 2006.252.08:13:21.31#ibcon#about to read 5, iclass 32, count 2 2006.252.08:13:21.31#ibcon#read 5, iclass 32, count 2 2006.252.08:13:21.31#ibcon#about to read 6, iclass 32, count 2 2006.252.08:13:21.31#ibcon#read 6, iclass 32, count 2 2006.252.08:13:21.31#ibcon#end of sib2, iclass 32, count 2 2006.252.08:13:21.31#ibcon#*mode == 0, iclass 32, count 2 2006.252.08:13:21.31#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.252.08:13:21.31#ibcon#[27=AT03-04\r\n] 2006.252.08:13:21.31#ibcon#*before write, iclass 32, count 2 2006.252.08:13:21.32#ibcon#enter sib2, iclass 32, count 2 2006.252.08:13:21.32#ibcon#flushed, iclass 32, count 2 2006.252.08:13:21.32#ibcon#about to write, iclass 32, count 2 2006.252.08:13:21.32#ibcon#wrote, iclass 32, count 2 2006.252.08:13:21.32#ibcon#about to read 3, iclass 32, count 2 2006.252.08:13:21.34#ibcon#read 3, iclass 32, count 2 2006.252.08:13:21.34#ibcon#about to read 4, iclass 32, count 2 2006.252.08:13:21.34#ibcon#read 4, iclass 32, count 2 2006.252.08:13:21.34#ibcon#about to read 5, iclass 32, count 2 2006.252.08:13:21.34#ibcon#read 5, iclass 32, count 2 2006.252.08:13:21.34#ibcon#about to read 6, iclass 32, count 2 2006.252.08:13:21.34#ibcon#read 6, iclass 32, count 2 2006.252.08:13:21.34#ibcon#end of sib2, iclass 32, count 2 2006.252.08:13:21.34#ibcon#*after write, iclass 32, count 2 2006.252.08:13:21.34#ibcon#*before return 0, iclass 32, count 2 2006.252.08:13:21.35#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.252.08:13:21.35#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.252.08:13:21.35#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.252.08:13:21.35#ibcon#ireg 7 cls_cnt 0 2006.252.08:13:21.35#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.252.08:13:21.46#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.252.08:13:21.46#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.252.08:13:21.46#ibcon#enter wrdev, iclass 32, count 0 2006.252.08:13:21.46#ibcon#first serial, iclass 32, count 0 2006.252.08:13:21.46#ibcon#enter sib2, iclass 32, count 0 2006.252.08:13:21.46#ibcon#flushed, iclass 32, count 0 2006.252.08:13:21.46#ibcon#about to write, iclass 32, count 0 2006.252.08:13:21.46#ibcon#wrote, iclass 32, count 0 2006.252.08:13:21.46#ibcon#about to read 3, iclass 32, count 0 2006.252.08:13:21.48#ibcon#read 3, iclass 32, count 0 2006.252.08:13:21.48#ibcon#about to read 4, iclass 32, count 0 2006.252.08:13:21.48#ibcon#read 4, iclass 32, count 0 2006.252.08:13:21.48#ibcon#about to read 5, iclass 32, count 0 2006.252.08:13:21.48#ibcon#read 5, iclass 32, count 0 2006.252.08:13:21.48#ibcon#about to read 6, iclass 32, count 0 2006.252.08:13:21.48#ibcon#read 6, iclass 32, count 0 2006.252.08:13:21.48#ibcon#end of sib2, iclass 32, count 0 2006.252.08:13:21.48#ibcon#*mode == 0, iclass 32, count 0 2006.252.08:13:21.48#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.252.08:13:21.48#ibcon#[27=USB\r\n] 2006.252.08:13:21.48#ibcon#*before write, iclass 32, count 0 2006.252.08:13:21.48#ibcon#enter sib2, iclass 32, count 0 2006.252.08:13:21.49#ibcon#flushed, iclass 32, count 0 2006.252.08:13:21.49#ibcon#about to write, iclass 32, count 0 2006.252.08:13:21.49#ibcon#wrote, iclass 32, count 0 2006.252.08:13:21.49#ibcon#about to read 3, iclass 32, count 0 2006.252.08:13:21.51#ibcon#read 3, iclass 32, count 0 2006.252.08:13:21.51#ibcon#about to read 4, iclass 32, count 0 2006.252.08:13:21.51#ibcon#read 4, iclass 32, count 0 2006.252.08:13:21.51#ibcon#about to read 5, iclass 32, count 0 2006.252.08:13:21.51#ibcon#read 5, iclass 32, count 0 2006.252.08:13:21.51#ibcon#about to read 6, iclass 32, count 0 2006.252.08:13:21.51#ibcon#read 6, iclass 32, count 0 2006.252.08:13:21.51#ibcon#end of sib2, iclass 32, count 0 2006.252.08:13:21.51#ibcon#*after write, iclass 32, count 0 2006.252.08:13:21.51#ibcon#*before return 0, iclass 32, count 0 2006.252.08:13:21.51#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.252.08:13:21.52#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.252.08:13:21.52#ibcon#about to clear, iclass 32 cls_cnt 0 2006.252.08:13:21.52#ibcon#cleared, iclass 32 cls_cnt 0 2006.252.08:13:21.52$vc4f8/vblo=4,712.99 2006.252.08:13:21.52#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.252.08:13:21.52#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.252.08:13:21.52#ibcon#ireg 17 cls_cnt 0 2006.252.08:13:21.52#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.252.08:13:21.52#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.252.08:13:21.52#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.252.08:13:21.52#ibcon#enter wrdev, iclass 34, count 0 2006.252.08:13:21.52#ibcon#first serial, iclass 34, count 0 2006.252.08:13:21.52#ibcon#enter sib2, iclass 34, count 0 2006.252.08:13:21.52#ibcon#flushed, iclass 34, count 0 2006.252.08:13:21.52#ibcon#about to write, iclass 34, count 0 2006.252.08:13:21.52#ibcon#wrote, iclass 34, count 0 2006.252.08:13:21.52#ibcon#about to read 3, iclass 34, count 0 2006.252.08:13:21.53#ibcon#read 3, iclass 34, count 0 2006.252.08:13:21.53#ibcon#about to read 4, iclass 34, count 0 2006.252.08:13:21.53#ibcon#read 4, iclass 34, count 0 2006.252.08:13:21.53#ibcon#about to read 5, iclass 34, count 0 2006.252.08:13:21.53#ibcon#read 5, iclass 34, count 0 2006.252.08:13:21.53#ibcon#about to read 6, iclass 34, count 0 2006.252.08:13:21.53#ibcon#read 6, iclass 34, count 0 2006.252.08:13:21.53#ibcon#end of sib2, iclass 34, count 0 2006.252.08:13:21.53#ibcon#*mode == 0, iclass 34, count 0 2006.252.08:13:21.53#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.252.08:13:21.53#ibcon#[28=FRQ=04,712.99\r\n] 2006.252.08:13:21.53#ibcon#*before write, iclass 34, count 0 2006.252.08:13:21.54#ibcon#enter sib2, iclass 34, count 0 2006.252.08:13:21.54#ibcon#flushed, iclass 34, count 0 2006.252.08:13:21.54#ibcon#about to write, iclass 34, count 0 2006.252.08:13:21.54#ibcon#wrote, iclass 34, count 0 2006.252.08:13:21.54#ibcon#about to read 3, iclass 34, count 0 2006.252.08:13:21.57#ibcon#read 3, iclass 34, count 0 2006.252.08:13:21.57#ibcon#about to read 4, iclass 34, count 0 2006.252.08:13:21.57#ibcon#read 4, iclass 34, count 0 2006.252.08:13:21.57#ibcon#about to read 5, iclass 34, count 0 2006.252.08:13:21.57#ibcon#read 5, iclass 34, count 0 2006.252.08:13:21.57#ibcon#about to read 6, iclass 34, count 0 2006.252.08:13:21.57#ibcon#read 6, iclass 34, count 0 2006.252.08:13:21.57#ibcon#end of sib2, iclass 34, count 0 2006.252.08:13:21.57#ibcon#*after write, iclass 34, count 0 2006.252.08:13:21.57#ibcon#*before return 0, iclass 34, count 0 2006.252.08:13:21.58#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.252.08:13:21.58#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.252.08:13:21.58#ibcon#about to clear, iclass 34 cls_cnt 0 2006.252.08:13:21.58#ibcon#cleared, iclass 34 cls_cnt 0 2006.252.08:13:21.58$vc4f8/vb=4,4 2006.252.08:13:21.58#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.252.08:13:21.58#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.252.08:13:21.58#ibcon#ireg 11 cls_cnt 2 2006.252.08:13:21.58#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.252.08:13:21.62#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.252.08:13:21.62#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.252.08:13:21.62#ibcon#enter wrdev, iclass 36, count 2 2006.252.08:13:21.62#ibcon#first serial, iclass 36, count 2 2006.252.08:13:21.62#ibcon#enter sib2, iclass 36, count 2 2006.252.08:13:21.62#ibcon#flushed, iclass 36, count 2 2006.252.08:13:21.62#ibcon#about to write, iclass 36, count 2 2006.252.08:13:21.62#ibcon#wrote, iclass 36, count 2 2006.252.08:13:21.62#ibcon#about to read 3, iclass 36, count 2 2006.252.08:13:21.64#ibcon#read 3, iclass 36, count 2 2006.252.08:13:21.64#ibcon#about to read 4, iclass 36, count 2 2006.252.08:13:21.64#ibcon#read 4, iclass 36, count 2 2006.252.08:13:21.64#ibcon#about to read 5, iclass 36, count 2 2006.252.08:13:21.64#ibcon#read 5, iclass 36, count 2 2006.252.08:13:21.64#ibcon#about to read 6, iclass 36, count 2 2006.252.08:13:21.64#ibcon#read 6, iclass 36, count 2 2006.252.08:13:21.64#ibcon#end of sib2, iclass 36, count 2 2006.252.08:13:21.64#ibcon#*mode == 0, iclass 36, count 2 2006.252.08:13:21.64#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.252.08:13:21.64#ibcon#[27=AT04-04\r\n] 2006.252.08:13:21.64#ibcon#*before write, iclass 36, count 2 2006.252.08:13:21.65#ibcon#enter sib2, iclass 36, count 2 2006.252.08:13:21.65#ibcon#flushed, iclass 36, count 2 2006.252.08:13:21.65#ibcon#about to write, iclass 36, count 2 2006.252.08:13:21.65#ibcon#wrote, iclass 36, count 2 2006.252.08:13:21.65#ibcon#about to read 3, iclass 36, count 2 2006.252.08:13:21.67#ibcon#read 3, iclass 36, count 2 2006.252.08:13:21.67#ibcon#about to read 4, iclass 36, count 2 2006.252.08:13:21.67#ibcon#read 4, iclass 36, count 2 2006.252.08:13:21.67#ibcon#about to read 5, iclass 36, count 2 2006.252.08:13:21.67#ibcon#read 5, iclass 36, count 2 2006.252.08:13:21.67#ibcon#about to read 6, iclass 36, count 2 2006.252.08:13:21.67#ibcon#read 6, iclass 36, count 2 2006.252.08:13:21.67#ibcon#end of sib2, iclass 36, count 2 2006.252.08:13:21.67#ibcon#*after write, iclass 36, count 2 2006.252.08:13:21.67#ibcon#*before return 0, iclass 36, count 2 2006.252.08:13:21.68#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.252.08:13:21.68#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.252.08:13:21.68#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.252.08:13:21.68#ibcon#ireg 7 cls_cnt 0 2006.252.08:13:21.68#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.252.08:13:21.79#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.252.08:13:21.79#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.252.08:13:21.79#ibcon#enter wrdev, iclass 36, count 0 2006.252.08:13:21.79#ibcon#first serial, iclass 36, count 0 2006.252.08:13:21.79#ibcon#enter sib2, iclass 36, count 0 2006.252.08:13:21.79#ibcon#flushed, iclass 36, count 0 2006.252.08:13:21.79#ibcon#about to write, iclass 36, count 0 2006.252.08:13:21.79#ibcon#wrote, iclass 36, count 0 2006.252.08:13:21.79#ibcon#about to read 3, iclass 36, count 0 2006.252.08:13:21.81#ibcon#read 3, iclass 36, count 0 2006.252.08:13:21.81#ibcon#about to read 4, iclass 36, count 0 2006.252.08:13:21.81#ibcon#read 4, iclass 36, count 0 2006.252.08:13:21.81#ibcon#about to read 5, iclass 36, count 0 2006.252.08:13:21.81#ibcon#read 5, iclass 36, count 0 2006.252.08:13:21.81#ibcon#about to read 6, iclass 36, count 0 2006.252.08:13:21.81#ibcon#read 6, iclass 36, count 0 2006.252.08:13:21.81#ibcon#end of sib2, iclass 36, count 0 2006.252.08:13:21.81#ibcon#*mode == 0, iclass 36, count 0 2006.252.08:13:21.81#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.252.08:13:21.81#ibcon#[27=USB\r\n] 2006.252.08:13:21.81#ibcon#*before write, iclass 36, count 0 2006.252.08:13:21.81#ibcon#enter sib2, iclass 36, count 0 2006.252.08:13:21.82#ibcon#flushed, iclass 36, count 0 2006.252.08:13:21.82#ibcon#about to write, iclass 36, count 0 2006.252.08:13:21.82#ibcon#wrote, iclass 36, count 0 2006.252.08:13:21.82#ibcon#about to read 3, iclass 36, count 0 2006.252.08:13:21.84#ibcon#read 3, iclass 36, count 0 2006.252.08:13:21.84#ibcon#about to read 4, iclass 36, count 0 2006.252.08:13:21.84#ibcon#read 4, iclass 36, count 0 2006.252.08:13:21.84#ibcon#about to read 5, iclass 36, count 0 2006.252.08:13:21.84#ibcon#read 5, iclass 36, count 0 2006.252.08:13:21.84#ibcon#about to read 6, iclass 36, count 0 2006.252.08:13:21.84#ibcon#read 6, iclass 36, count 0 2006.252.08:13:21.84#ibcon#end of sib2, iclass 36, count 0 2006.252.08:13:21.84#ibcon#*after write, iclass 36, count 0 2006.252.08:13:21.84#ibcon#*before return 0, iclass 36, count 0 2006.252.08:13:21.84#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.252.08:13:21.85#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.252.08:13:21.85#ibcon#about to clear, iclass 36 cls_cnt 0 2006.252.08:13:21.85#ibcon#cleared, iclass 36 cls_cnt 0 2006.252.08:13:21.85$vc4f8/vblo=5,744.99 2006.252.08:13:21.85#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.252.08:13:21.85#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.252.08:13:21.85#ibcon#ireg 17 cls_cnt 0 2006.252.08:13:21.85#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.252.08:13:21.85#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.252.08:13:21.85#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.252.08:13:21.85#ibcon#enter wrdev, iclass 38, count 0 2006.252.08:13:21.85#ibcon#first serial, iclass 38, count 0 2006.252.08:13:21.85#ibcon#enter sib2, iclass 38, count 0 2006.252.08:13:21.85#ibcon#flushed, iclass 38, count 0 2006.252.08:13:21.85#ibcon#about to write, iclass 38, count 0 2006.252.08:13:21.85#ibcon#wrote, iclass 38, count 0 2006.252.08:13:21.85#ibcon#about to read 3, iclass 38, count 0 2006.252.08:13:21.86#ibcon#read 3, iclass 38, count 0 2006.252.08:13:21.86#ibcon#about to read 4, iclass 38, count 0 2006.252.08:13:21.86#ibcon#read 4, iclass 38, count 0 2006.252.08:13:21.86#ibcon#about to read 5, iclass 38, count 0 2006.252.08:13:21.86#ibcon#read 5, iclass 38, count 0 2006.252.08:13:21.86#ibcon#about to read 6, iclass 38, count 0 2006.252.08:13:21.86#ibcon#read 6, iclass 38, count 0 2006.252.08:13:21.86#ibcon#end of sib2, iclass 38, count 0 2006.252.08:13:21.86#ibcon#*mode == 0, iclass 38, count 0 2006.252.08:13:21.86#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.252.08:13:21.86#ibcon#[28=FRQ=05,744.99\r\n] 2006.252.08:13:21.86#ibcon#*before write, iclass 38, count 0 2006.252.08:13:21.86#ibcon#enter sib2, iclass 38, count 0 2006.252.08:13:21.87#ibcon#flushed, iclass 38, count 0 2006.252.08:13:21.87#ibcon#about to write, iclass 38, count 0 2006.252.08:13:21.87#ibcon#wrote, iclass 38, count 0 2006.252.08:13:21.87#ibcon#about to read 3, iclass 38, count 0 2006.252.08:13:21.90#ibcon#read 3, iclass 38, count 0 2006.252.08:13:21.90#ibcon#about to read 4, iclass 38, count 0 2006.252.08:13:21.90#ibcon#read 4, iclass 38, count 0 2006.252.08:13:21.90#ibcon#about to read 5, iclass 38, count 0 2006.252.08:13:21.90#ibcon#read 5, iclass 38, count 0 2006.252.08:13:21.90#ibcon#about to read 6, iclass 38, count 0 2006.252.08:13:21.90#ibcon#read 6, iclass 38, count 0 2006.252.08:13:21.90#ibcon#end of sib2, iclass 38, count 0 2006.252.08:13:21.90#ibcon#*after write, iclass 38, count 0 2006.252.08:13:21.90#ibcon#*before return 0, iclass 38, count 0 2006.252.08:13:21.91#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.252.08:13:21.91#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.252.08:13:21.91#ibcon#about to clear, iclass 38 cls_cnt 0 2006.252.08:13:21.91#ibcon#cleared, iclass 38 cls_cnt 0 2006.252.08:13:21.91$vc4f8/vb=5,4 2006.252.08:13:21.91#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.252.08:13:21.91#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.252.08:13:21.91#ibcon#ireg 11 cls_cnt 2 2006.252.08:13:21.91#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.252.08:13:21.95#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.252.08:13:21.95#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.252.08:13:21.95#ibcon#enter wrdev, iclass 40, count 2 2006.252.08:13:21.95#ibcon#first serial, iclass 40, count 2 2006.252.08:13:21.95#ibcon#enter sib2, iclass 40, count 2 2006.252.08:13:21.95#ibcon#flushed, iclass 40, count 2 2006.252.08:13:21.95#ibcon#about to write, iclass 40, count 2 2006.252.08:13:21.95#ibcon#wrote, iclass 40, count 2 2006.252.08:13:21.95#ibcon#about to read 3, iclass 40, count 2 2006.252.08:13:21.98#ibcon#read 3, iclass 40, count 2 2006.252.08:13:21.98#ibcon#about to read 4, iclass 40, count 2 2006.252.08:13:21.98#ibcon#read 4, iclass 40, count 2 2006.252.08:13:21.98#ibcon#about to read 5, iclass 40, count 2 2006.252.08:13:21.98#ibcon#read 5, iclass 40, count 2 2006.252.08:13:21.98#ibcon#about to read 6, iclass 40, count 2 2006.252.08:13:21.98#ibcon#read 6, iclass 40, count 2 2006.252.08:13:21.98#ibcon#end of sib2, iclass 40, count 2 2006.252.08:13:21.98#ibcon#*mode == 0, iclass 40, count 2 2006.252.08:13:21.98#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.252.08:13:21.98#ibcon#[27=AT05-04\r\n] 2006.252.08:13:21.98#ibcon#*before write, iclass 40, count 2 2006.252.08:13:21.98#ibcon#enter sib2, iclass 40, count 2 2006.252.08:13:21.98#ibcon#flushed, iclass 40, count 2 2006.252.08:13:21.98#ibcon#about to write, iclass 40, count 2 2006.252.08:13:21.98#ibcon#wrote, iclass 40, count 2 2006.252.08:13:21.98#ibcon#about to read 3, iclass 40, count 2 2006.252.08:13:22.01#ibcon#read 3, iclass 40, count 2 2006.252.08:13:22.01#ibcon#about to read 4, iclass 40, count 2 2006.252.08:13:22.01#ibcon#read 4, iclass 40, count 2 2006.252.08:13:22.01#ibcon#about to read 5, iclass 40, count 2 2006.252.08:13:22.01#ibcon#read 5, iclass 40, count 2 2006.252.08:13:22.01#ibcon#about to read 6, iclass 40, count 2 2006.252.08:13:22.01#ibcon#read 6, iclass 40, count 2 2006.252.08:13:22.01#ibcon#end of sib2, iclass 40, count 2 2006.252.08:13:22.01#ibcon#*after write, iclass 40, count 2 2006.252.08:13:22.01#ibcon#*before return 0, iclass 40, count 2 2006.252.08:13:22.02#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.252.08:13:22.02#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.252.08:13:22.02#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.252.08:13:22.02#ibcon#ireg 7 cls_cnt 0 2006.252.08:13:22.02#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.252.08:13:22.14#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.252.08:13:22.14#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.252.08:13:22.14#ibcon#enter wrdev, iclass 40, count 0 2006.252.08:13:22.14#ibcon#first serial, iclass 40, count 0 2006.252.08:13:22.14#ibcon#enter sib2, iclass 40, count 0 2006.252.08:13:22.14#ibcon#flushed, iclass 40, count 0 2006.252.08:13:22.14#ibcon#about to write, iclass 40, count 0 2006.252.08:13:22.14#ibcon#wrote, iclass 40, count 0 2006.252.08:13:22.14#ibcon#about to read 3, iclass 40, count 0 2006.252.08:13:22.15#ibcon#read 3, iclass 40, count 0 2006.252.08:13:22.15#ibcon#about to read 4, iclass 40, count 0 2006.252.08:13:22.15#ibcon#read 4, iclass 40, count 0 2006.252.08:13:22.15#ibcon#about to read 5, iclass 40, count 0 2006.252.08:13:22.15#ibcon#read 5, iclass 40, count 0 2006.252.08:13:22.15#ibcon#about to read 6, iclass 40, count 0 2006.252.08:13:22.15#ibcon#read 6, iclass 40, count 0 2006.252.08:13:22.15#ibcon#end of sib2, iclass 40, count 0 2006.252.08:13:22.15#ibcon#*mode == 0, iclass 40, count 0 2006.252.08:13:22.15#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.252.08:13:22.15#ibcon#[27=USB\r\n] 2006.252.08:13:22.15#ibcon#*before write, iclass 40, count 0 2006.252.08:13:22.15#ibcon#enter sib2, iclass 40, count 0 2006.252.08:13:22.16#ibcon#flushed, iclass 40, count 0 2006.252.08:13:22.16#ibcon#about to write, iclass 40, count 0 2006.252.08:13:22.16#ibcon#wrote, iclass 40, count 0 2006.252.08:13:22.16#ibcon#about to read 3, iclass 40, count 0 2006.252.08:13:22.18#ibcon#read 3, iclass 40, count 0 2006.252.08:13:22.18#ibcon#about to read 4, iclass 40, count 0 2006.252.08:13:22.18#ibcon#read 4, iclass 40, count 0 2006.252.08:13:22.18#ibcon#about to read 5, iclass 40, count 0 2006.252.08:13:22.18#ibcon#read 5, iclass 40, count 0 2006.252.08:13:22.18#ibcon#about to read 6, iclass 40, count 0 2006.252.08:13:22.18#ibcon#read 6, iclass 40, count 0 2006.252.08:13:22.18#ibcon#end of sib2, iclass 40, count 0 2006.252.08:13:22.18#ibcon#*after write, iclass 40, count 0 2006.252.08:13:22.18#ibcon#*before return 0, iclass 40, count 0 2006.252.08:13:22.18#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.252.08:13:22.19#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.252.08:13:22.19#ibcon#about to clear, iclass 40 cls_cnt 0 2006.252.08:13:22.19#ibcon#cleared, iclass 40 cls_cnt 0 2006.252.08:13:22.19$vc4f8/vblo=6,752.99 2006.252.08:13:22.19#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.252.08:13:22.19#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.252.08:13:22.19#ibcon#ireg 17 cls_cnt 0 2006.252.08:13:22.19#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.252.08:13:22.19#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.252.08:13:22.19#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.252.08:13:22.19#ibcon#enter wrdev, iclass 4, count 0 2006.252.08:13:22.19#ibcon#first serial, iclass 4, count 0 2006.252.08:13:22.19#ibcon#enter sib2, iclass 4, count 0 2006.252.08:13:22.19#ibcon#flushed, iclass 4, count 0 2006.252.08:13:22.19#ibcon#about to write, iclass 4, count 0 2006.252.08:13:22.19#ibcon#wrote, iclass 4, count 0 2006.252.08:13:22.19#ibcon#about to read 3, iclass 4, count 0 2006.252.08:13:22.20#ibcon#read 3, iclass 4, count 0 2006.252.08:13:22.20#ibcon#about to read 4, iclass 4, count 0 2006.252.08:13:22.20#ibcon#read 4, iclass 4, count 0 2006.252.08:13:22.20#ibcon#about to read 5, iclass 4, count 0 2006.252.08:13:22.20#ibcon#read 5, iclass 4, count 0 2006.252.08:13:22.20#ibcon#about to read 6, iclass 4, count 0 2006.252.08:13:22.20#ibcon#read 6, iclass 4, count 0 2006.252.08:13:22.20#ibcon#end of sib2, iclass 4, count 0 2006.252.08:13:22.20#ibcon#*mode == 0, iclass 4, count 0 2006.252.08:13:22.20#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.252.08:13:22.20#ibcon#[28=FRQ=06,752.99\r\n] 2006.252.08:13:22.20#ibcon#*before write, iclass 4, count 0 2006.252.08:13:22.20#ibcon#enter sib2, iclass 4, count 0 2006.252.08:13:22.21#ibcon#flushed, iclass 4, count 0 2006.252.08:13:22.21#ibcon#about to write, iclass 4, count 0 2006.252.08:13:22.21#ibcon#wrote, iclass 4, count 0 2006.252.08:13:22.21#ibcon#about to read 3, iclass 4, count 0 2006.252.08:13:22.24#ibcon#read 3, iclass 4, count 0 2006.252.08:13:22.24#ibcon#about to read 4, iclass 4, count 0 2006.252.08:13:22.24#ibcon#read 4, iclass 4, count 0 2006.252.08:13:22.24#ibcon#about to read 5, iclass 4, count 0 2006.252.08:13:22.24#ibcon#read 5, iclass 4, count 0 2006.252.08:13:22.24#ibcon#about to read 6, iclass 4, count 0 2006.252.08:13:22.24#ibcon#read 6, iclass 4, count 0 2006.252.08:13:22.24#ibcon#end of sib2, iclass 4, count 0 2006.252.08:13:22.24#ibcon#*after write, iclass 4, count 0 2006.252.08:13:22.24#ibcon#*before return 0, iclass 4, count 0 2006.252.08:13:22.24#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.252.08:13:22.25#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.252.08:13:22.25#ibcon#about to clear, iclass 4 cls_cnt 0 2006.252.08:13:22.25#ibcon#cleared, iclass 4 cls_cnt 0 2006.252.08:13:22.25$vc4f8/vb=6,4 2006.252.08:13:22.25#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.252.08:13:22.25#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.252.08:13:22.25#ibcon#ireg 11 cls_cnt 2 2006.252.08:13:22.25#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.252.08:13:22.29#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.252.08:13:22.29#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.252.08:13:22.29#ibcon#enter wrdev, iclass 6, count 2 2006.252.08:13:22.29#ibcon#first serial, iclass 6, count 2 2006.252.08:13:22.29#ibcon#enter sib2, iclass 6, count 2 2006.252.08:13:22.29#ibcon#flushed, iclass 6, count 2 2006.252.08:13:22.29#ibcon#about to write, iclass 6, count 2 2006.252.08:13:22.29#ibcon#wrote, iclass 6, count 2 2006.252.08:13:22.29#ibcon#about to read 3, iclass 6, count 2 2006.252.08:13:22.31#ibcon#read 3, iclass 6, count 2 2006.252.08:13:22.31#ibcon#about to read 4, iclass 6, count 2 2006.252.08:13:22.31#ibcon#read 4, iclass 6, count 2 2006.252.08:13:22.31#ibcon#about to read 5, iclass 6, count 2 2006.252.08:13:22.31#ibcon#read 5, iclass 6, count 2 2006.252.08:13:22.31#ibcon#about to read 6, iclass 6, count 2 2006.252.08:13:22.31#ibcon#read 6, iclass 6, count 2 2006.252.08:13:22.31#ibcon#end of sib2, iclass 6, count 2 2006.252.08:13:22.31#ibcon#*mode == 0, iclass 6, count 2 2006.252.08:13:22.31#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.252.08:13:22.31#ibcon#[27=AT06-04\r\n] 2006.252.08:13:22.31#ibcon#*before write, iclass 6, count 2 2006.252.08:13:22.32#ibcon#enter sib2, iclass 6, count 2 2006.252.08:13:22.32#ibcon#flushed, iclass 6, count 2 2006.252.08:13:22.32#ibcon#about to write, iclass 6, count 2 2006.252.08:13:22.32#ibcon#wrote, iclass 6, count 2 2006.252.08:13:22.32#ibcon#about to read 3, iclass 6, count 2 2006.252.08:13:22.34#ibcon#read 3, iclass 6, count 2 2006.252.08:13:22.34#ibcon#about to read 4, iclass 6, count 2 2006.252.08:13:22.34#ibcon#read 4, iclass 6, count 2 2006.252.08:13:22.34#ibcon#about to read 5, iclass 6, count 2 2006.252.08:13:22.34#ibcon#read 5, iclass 6, count 2 2006.252.08:13:22.34#ibcon#about to read 6, iclass 6, count 2 2006.252.08:13:22.34#ibcon#read 6, iclass 6, count 2 2006.252.08:13:22.34#ibcon#end of sib2, iclass 6, count 2 2006.252.08:13:22.34#ibcon#*after write, iclass 6, count 2 2006.252.08:13:22.34#ibcon#*before return 0, iclass 6, count 2 2006.252.08:13:22.34#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.252.08:13:22.35#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.252.08:13:22.35#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.252.08:13:22.35#ibcon#ireg 7 cls_cnt 0 2006.252.08:13:22.35#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.252.08:13:22.46#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.252.08:13:22.46#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.252.08:13:22.46#ibcon#enter wrdev, iclass 6, count 0 2006.252.08:13:22.46#ibcon#first serial, iclass 6, count 0 2006.252.08:13:22.46#ibcon#enter sib2, iclass 6, count 0 2006.252.08:13:22.46#ibcon#flushed, iclass 6, count 0 2006.252.08:13:22.46#ibcon#about to write, iclass 6, count 0 2006.252.08:13:22.46#ibcon#wrote, iclass 6, count 0 2006.252.08:13:22.46#ibcon#about to read 3, iclass 6, count 0 2006.252.08:13:22.48#ibcon#read 3, iclass 6, count 0 2006.252.08:13:22.48#ibcon#about to read 4, iclass 6, count 0 2006.252.08:13:22.48#ibcon#read 4, iclass 6, count 0 2006.252.08:13:22.48#ibcon#about to read 5, iclass 6, count 0 2006.252.08:13:22.48#ibcon#read 5, iclass 6, count 0 2006.252.08:13:22.48#ibcon#about to read 6, iclass 6, count 0 2006.252.08:13:22.48#ibcon#read 6, iclass 6, count 0 2006.252.08:13:22.48#ibcon#end of sib2, iclass 6, count 0 2006.252.08:13:22.48#ibcon#*mode == 0, iclass 6, count 0 2006.252.08:13:22.48#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.252.08:13:22.48#ibcon#[27=USB\r\n] 2006.252.08:13:22.48#ibcon#*before write, iclass 6, count 0 2006.252.08:13:22.48#ibcon#enter sib2, iclass 6, count 0 2006.252.08:13:22.49#ibcon#flushed, iclass 6, count 0 2006.252.08:13:22.49#ibcon#about to write, iclass 6, count 0 2006.252.08:13:22.49#ibcon#wrote, iclass 6, count 0 2006.252.08:13:22.49#ibcon#about to read 3, iclass 6, count 0 2006.252.08:13:22.51#ibcon#read 3, iclass 6, count 0 2006.252.08:13:22.51#ibcon#about to read 4, iclass 6, count 0 2006.252.08:13:22.51#ibcon#read 4, iclass 6, count 0 2006.252.08:13:22.51#ibcon#about to read 5, iclass 6, count 0 2006.252.08:13:22.51#ibcon#read 5, iclass 6, count 0 2006.252.08:13:22.51#ibcon#about to read 6, iclass 6, count 0 2006.252.08:13:22.51#ibcon#read 6, iclass 6, count 0 2006.252.08:13:22.51#ibcon#end of sib2, iclass 6, count 0 2006.252.08:13:22.51#ibcon#*after write, iclass 6, count 0 2006.252.08:13:22.51#ibcon#*before return 0, iclass 6, count 0 2006.252.08:13:22.51#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.252.08:13:22.52#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.252.08:13:22.52#ibcon#about to clear, iclass 6 cls_cnt 0 2006.252.08:13:22.52#ibcon#cleared, iclass 6 cls_cnt 0 2006.252.08:13:22.52$vc4f8/vabw=wide 2006.252.08:13:22.52#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.252.08:13:22.52#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.252.08:13:22.52#ibcon#ireg 8 cls_cnt 0 2006.252.08:13:22.52#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.252.08:13:22.52#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.252.08:13:22.52#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.252.08:13:22.52#ibcon#enter wrdev, iclass 10, count 0 2006.252.08:13:22.52#ibcon#first serial, iclass 10, count 0 2006.252.08:13:22.52#ibcon#enter sib2, iclass 10, count 0 2006.252.08:13:22.52#ibcon#flushed, iclass 10, count 0 2006.252.08:13:22.52#ibcon#about to write, iclass 10, count 0 2006.252.08:13:22.52#ibcon#wrote, iclass 10, count 0 2006.252.08:13:22.52#ibcon#about to read 3, iclass 10, count 0 2006.252.08:13:22.53#ibcon#read 3, iclass 10, count 0 2006.252.08:13:22.53#ibcon#about to read 4, iclass 10, count 0 2006.252.08:13:22.53#ibcon#read 4, iclass 10, count 0 2006.252.08:13:22.53#ibcon#about to read 5, iclass 10, count 0 2006.252.08:13:22.53#ibcon#read 5, iclass 10, count 0 2006.252.08:13:22.53#ibcon#about to read 6, iclass 10, count 0 2006.252.08:13:22.53#ibcon#read 6, iclass 10, count 0 2006.252.08:13:22.53#ibcon#end of sib2, iclass 10, count 0 2006.252.08:13:22.53#ibcon#*mode == 0, iclass 10, count 0 2006.252.08:13:22.53#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.252.08:13:22.53#ibcon#[25=BW32\r\n] 2006.252.08:13:22.53#ibcon#*before write, iclass 10, count 0 2006.252.08:13:22.53#ibcon#enter sib2, iclass 10, count 0 2006.252.08:13:22.54#ibcon#flushed, iclass 10, count 0 2006.252.08:13:22.54#ibcon#about to write, iclass 10, count 0 2006.252.08:13:22.54#ibcon#wrote, iclass 10, count 0 2006.252.08:13:22.54#ibcon#about to read 3, iclass 10, count 0 2006.252.08:13:22.56#ibcon#read 3, iclass 10, count 0 2006.252.08:13:22.56#ibcon#about to read 4, iclass 10, count 0 2006.252.08:13:22.56#ibcon#read 4, iclass 10, count 0 2006.252.08:13:22.56#ibcon#about to read 5, iclass 10, count 0 2006.252.08:13:22.56#ibcon#read 5, iclass 10, count 0 2006.252.08:13:22.56#ibcon#about to read 6, iclass 10, count 0 2006.252.08:13:22.56#ibcon#read 6, iclass 10, count 0 2006.252.08:13:22.56#ibcon#end of sib2, iclass 10, count 0 2006.252.08:13:22.56#ibcon#*after write, iclass 10, count 0 2006.252.08:13:22.56#ibcon#*before return 0, iclass 10, count 0 2006.252.08:13:22.56#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.252.08:13:22.56#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.252.08:13:22.57#ibcon#about to clear, iclass 10 cls_cnt 0 2006.252.08:13:22.57#ibcon#cleared, iclass 10 cls_cnt 0 2006.252.08:13:22.57$vc4f8/vbbw=wide 2006.252.08:13:22.57#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.252.08:13:22.57#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.252.08:13:22.57#ibcon#ireg 8 cls_cnt 0 2006.252.08:13:22.57#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.252.08:13:22.62#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.252.08:13:22.62#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.252.08:13:22.62#ibcon#enter wrdev, iclass 12, count 0 2006.252.08:13:22.62#ibcon#first serial, iclass 12, count 0 2006.252.08:13:22.62#ibcon#enter sib2, iclass 12, count 0 2006.252.08:13:22.62#ibcon#flushed, iclass 12, count 0 2006.252.08:13:22.62#ibcon#about to write, iclass 12, count 0 2006.252.08:13:22.62#ibcon#wrote, iclass 12, count 0 2006.252.08:13:22.62#ibcon#about to read 3, iclass 12, count 0 2006.252.08:13:22.64#ibcon#read 3, iclass 12, count 0 2006.252.08:13:22.64#ibcon#about to read 4, iclass 12, count 0 2006.252.08:13:22.64#ibcon#read 4, iclass 12, count 0 2006.252.08:13:22.64#ibcon#about to read 5, iclass 12, count 0 2006.252.08:13:22.64#ibcon#read 5, iclass 12, count 0 2006.252.08:13:22.64#ibcon#about to read 6, iclass 12, count 0 2006.252.08:13:22.64#ibcon#read 6, iclass 12, count 0 2006.252.08:13:22.64#ibcon#end of sib2, iclass 12, count 0 2006.252.08:13:22.64#ibcon#*mode == 0, iclass 12, count 0 2006.252.08:13:22.64#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.252.08:13:22.64#ibcon#[27=BW32\r\n] 2006.252.08:13:22.64#ibcon#*before write, iclass 12, count 0 2006.252.08:13:22.64#ibcon#enter sib2, iclass 12, count 0 2006.252.08:13:22.65#ibcon#flushed, iclass 12, count 0 2006.252.08:13:22.65#ibcon#about to write, iclass 12, count 0 2006.252.08:13:22.65#ibcon#wrote, iclass 12, count 0 2006.252.08:13:22.65#ibcon#about to read 3, iclass 12, count 0 2006.252.08:13:22.67#ibcon#read 3, iclass 12, count 0 2006.252.08:13:22.67#ibcon#about to read 4, iclass 12, count 0 2006.252.08:13:22.67#ibcon#read 4, iclass 12, count 0 2006.252.08:13:22.67#ibcon#about to read 5, iclass 12, count 0 2006.252.08:13:22.67#ibcon#read 5, iclass 12, count 0 2006.252.08:13:22.67#ibcon#about to read 6, iclass 12, count 0 2006.252.08:13:22.67#ibcon#read 6, iclass 12, count 0 2006.252.08:13:22.67#ibcon#end of sib2, iclass 12, count 0 2006.252.08:13:22.67#ibcon#*after write, iclass 12, count 0 2006.252.08:13:22.67#ibcon#*before return 0, iclass 12, count 0 2006.252.08:13:22.67#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.252.08:13:22.68#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.252.08:13:22.68#ibcon#about to clear, iclass 12 cls_cnt 0 2006.252.08:13:22.68#ibcon#cleared, iclass 12 cls_cnt 0 2006.252.08:13:22.68$4f8m12a/ifd4f 2006.252.08:13:22.68$ifd4f/lo= 2006.252.08:13:22.68$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.252.08:13:22.68$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.252.08:13:22.68$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.252.08:13:22.68$ifd4f/patch= 2006.252.08:13:22.68$ifd4f/patch=lo1,a1,a2,a3,a4 2006.252.08:13:22.68$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.252.08:13:22.68$ifd4f/patch=lo3,a5,a6,a7,a8 2006.252.08:13:22.68$4f8m12a/"form=m,16.000,1:2 2006.252.08:13:22.68$4f8m12a/"tpicd 2006.252.08:13:22.68$4f8m12a/echo=off 2006.252.08:13:22.68$4f8m12a/xlog=off 2006.252.08:13:22.68:!2006.252.08:14:20 2006.252.08:14:02.14#trakl#Source acquired 2006.252.08:14:04.15#flagr#flagr/antenna,acquired 2006.252.08:14:20.02:preob 2006.252.08:14:21.15/onsource/TRACKING 2006.252.08:14:21.15:!2006.252.08:14:30 2006.252.08:14:30.02:data_valid=on 2006.252.08:14:30.02:midob 2006.252.08:14:31.15/onsource/TRACKING 2006.252.08:14:31.15/wx/27.29,1011.1,91 2006.252.08:14:31.28/cable/+6.4098E-03 2006.252.08:14:32.37/va/01,08,usb,yes,36,37 2006.252.08:14:32.37/va/02,07,usb,yes,36,37 2006.252.08:14:32.37/va/03,06,usb,yes,38,38 2006.252.08:14:32.37/va/04,07,usb,yes,37,40 2006.252.08:14:32.37/va/05,07,usb,yes,41,43 2006.252.08:14:32.37/va/06,07,usb,yes,36,36 2006.252.08:14:32.37/va/07,07,usb,yes,36,35 2006.252.08:14:32.37/va/08,07,usb,yes,38,38 2006.252.08:14:32.60/valo/01,532.99,yes,locked 2006.252.08:14:32.60/valo/02,572.99,yes,locked 2006.252.08:14:32.60/valo/03,672.99,yes,locked 2006.252.08:14:32.60/valo/04,832.99,yes,locked 2006.252.08:14:32.60/valo/05,652.99,yes,locked 2006.252.08:14:32.60/valo/06,772.99,yes,locked 2006.252.08:14:32.60/valo/07,832.99,yes,locked 2006.252.08:14:32.60/valo/08,852.99,yes,locked 2006.252.08:14:33.69/vb/01,04,usb,yes,33,31 2006.252.08:14:33.69/vb/02,05,usb,yes,30,32 2006.252.08:14:33.69/vb/03,04,usb,yes,31,35 2006.252.08:14:33.69/vb/04,04,usb,yes,32,32 2006.252.08:14:33.69/vb/05,04,usb,yes,30,35 2006.252.08:14:33.69/vb/06,04,usb,yes,31,34 2006.252.08:14:33.69/vb/07,04,usb,yes,33,34 2006.252.08:14:33.69/vb/08,04,usb,yes,31,34 2006.252.08:14:33.92/vblo/01,632.99,yes,locked 2006.252.08:14:33.92/vblo/02,640.99,yes,locked 2006.252.08:14:33.92/vblo/03,656.99,yes,locked 2006.252.08:14:33.92/vblo/04,712.99,yes,locked 2006.252.08:14:33.92/vblo/05,744.99,yes,locked 2006.252.08:14:33.92/vblo/06,752.99,yes,locked 2006.252.08:14:33.92/vblo/07,734.99,yes,locked 2006.252.08:14:33.92/vblo/08,744.99,yes,locked 2006.252.08:14:34.07/vabw/8 2006.252.08:14:34.22/vbbw/8 2006.252.08:14:34.33/xfe/off,on,14.0 2006.252.08:14:34.72/ifatt/23,28,28,28 2006.252.08:14:35.07/fmout-gps/S +4.75E-07 2006.252.08:14:35.12:!2006.252.08:15:30 2006.252.08:15:30.01:data_valid=off 2006.252.08:15:30.02:postob 2006.252.08:15:30.15/cable/+6.4096E-03 2006.252.08:15:30.16/wx/27.29,1011.1,91 2006.252.08:15:31.07/fmout-gps/S +4.76E-07 2006.252.08:15:31.08:scan_name=252-0816,k06252,60 2006.252.08:15:31.08:source=1803+784,180045.68,782804.0,2000.0,neutral 2006.252.08:15:32.14#flagr#flagr/antenna,new-source 2006.252.08:15:32.15:checkk5 2006.252.08:15:32.54/chk_autoobs//k5ts1/ autoobs is running! 2006.252.08:15:32.91/chk_autoobs//k5ts2/ autoobs is running! 2006.252.08:15:33.29/chk_autoobs//k5ts3/ autoobs is running! 2006.252.08:15:33.66/chk_autoobs//k5ts4/ autoobs is running! 2006.252.08:15:34.03/chk_obsdata//k5ts1/T2520814??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.08:15:34.40/chk_obsdata//k5ts2/T2520814??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.08:15:34.77/chk_obsdata//k5ts3/T2520814??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.08:15:35.14/chk_obsdata//k5ts4/T2520814??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.08:15:35.86/k5log//k5ts1_log_newline 2006.252.08:15:36.55/k5log//k5ts2_log_newline 2006.252.08:15:37.25/k5log//k5ts3_log_newline 2006.252.08:15:37.95/k5log//k5ts4_log_newline 2006.252.08:15:37.98/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.252.08:15:37.98:4f8m12a=2 2006.252.08:15:37.98$4f8m12a/echo=on 2006.252.08:15:37.98$4f8m12a/pcalon 2006.252.08:15:37.98$pcalon/"no phase cal control is implemented here 2006.252.08:15:37.98$4f8m12a/"tpicd=stop 2006.252.08:15:37.98$4f8m12a/vc4f8 2006.252.08:15:37.98$vc4f8/valo=1,532.99 2006.252.08:15:37.98#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.252.08:15:37.98#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.252.08:15:37.98#ibcon#ireg 17 cls_cnt 0 2006.252.08:15:37.98#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.252.08:15:37.98#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.252.08:15:37.98#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.252.08:15:37.98#ibcon#enter wrdev, iclass 31, count 0 2006.252.08:15:37.98#ibcon#first serial, iclass 31, count 0 2006.252.08:15:37.98#ibcon#enter sib2, iclass 31, count 0 2006.252.08:15:37.98#ibcon#flushed, iclass 31, count 0 2006.252.08:15:37.98#ibcon#about to write, iclass 31, count 0 2006.252.08:15:37.98#ibcon#wrote, iclass 31, count 0 2006.252.08:15:37.98#ibcon#about to read 3, iclass 31, count 0 2006.252.08:15:37.99#ibcon#read 3, iclass 31, count 0 2006.252.08:15:37.99#ibcon#about to read 4, iclass 31, count 0 2006.252.08:15:37.99#ibcon#read 4, iclass 31, count 0 2006.252.08:15:37.99#ibcon#about to read 5, iclass 31, count 0 2006.252.08:15:37.99#ibcon#read 5, iclass 31, count 0 2006.252.08:15:37.99#ibcon#about to read 6, iclass 31, count 0 2006.252.08:15:37.99#ibcon#read 6, iclass 31, count 0 2006.252.08:15:37.99#ibcon#end of sib2, iclass 31, count 0 2006.252.08:15:37.99#ibcon#*mode == 0, iclass 31, count 0 2006.252.08:15:37.99#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.252.08:15:37.99#ibcon#[26=FRQ=01,532.99\r\n] 2006.252.08:15:37.99#ibcon#*before write, iclass 31, count 0 2006.252.08:15:37.99#ibcon#enter sib2, iclass 31, count 0 2006.252.08:15:37.99#ibcon#flushed, iclass 31, count 0 2006.252.08:15:37.99#ibcon#about to write, iclass 31, count 0 2006.252.08:15:37.99#ibcon#wrote, iclass 31, count 0 2006.252.08:15:37.99#ibcon#about to read 3, iclass 31, count 0 2006.252.08:15:38.04#ibcon#read 3, iclass 31, count 0 2006.252.08:15:38.04#ibcon#about to read 4, iclass 31, count 0 2006.252.08:15:38.04#ibcon#read 4, iclass 31, count 0 2006.252.08:15:38.04#ibcon#about to read 5, iclass 31, count 0 2006.252.08:15:38.04#ibcon#read 5, iclass 31, count 0 2006.252.08:15:38.04#ibcon#about to read 6, iclass 31, count 0 2006.252.08:15:38.04#ibcon#read 6, iclass 31, count 0 2006.252.08:15:38.04#ibcon#end of sib2, iclass 31, count 0 2006.252.08:15:38.04#ibcon#*after write, iclass 31, count 0 2006.252.08:15:38.04#ibcon#*before return 0, iclass 31, count 0 2006.252.08:15:38.04#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.252.08:15:38.04#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.252.08:15:38.04#ibcon#about to clear, iclass 31 cls_cnt 0 2006.252.08:15:38.04#ibcon#cleared, iclass 31 cls_cnt 0 2006.252.08:15:38.04$vc4f8/va=1,8 2006.252.08:15:38.04#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.252.08:15:38.04#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.252.08:15:38.04#ibcon#ireg 11 cls_cnt 2 2006.252.08:15:38.04#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.252.08:15:38.04#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.252.08:15:38.04#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.252.08:15:38.04#ibcon#enter wrdev, iclass 33, count 2 2006.252.08:15:38.04#ibcon#first serial, iclass 33, count 2 2006.252.08:15:38.04#ibcon#enter sib2, iclass 33, count 2 2006.252.08:15:38.04#ibcon#flushed, iclass 33, count 2 2006.252.08:15:38.04#ibcon#about to write, iclass 33, count 2 2006.252.08:15:38.04#ibcon#wrote, iclass 33, count 2 2006.252.08:15:38.05#ibcon#about to read 3, iclass 33, count 2 2006.252.08:15:38.06#ibcon#read 3, iclass 33, count 2 2006.252.08:15:38.06#ibcon#about to read 4, iclass 33, count 2 2006.252.08:15:38.06#ibcon#read 4, iclass 33, count 2 2006.252.08:15:38.06#ibcon#about to read 5, iclass 33, count 2 2006.252.08:15:38.06#ibcon#read 5, iclass 33, count 2 2006.252.08:15:38.06#ibcon#about to read 6, iclass 33, count 2 2006.252.08:15:38.06#ibcon#read 6, iclass 33, count 2 2006.252.08:15:38.06#ibcon#end of sib2, iclass 33, count 2 2006.252.08:15:38.06#ibcon#*mode == 0, iclass 33, count 2 2006.252.08:15:38.06#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.252.08:15:38.06#ibcon#[25=AT01-08\r\n] 2006.252.08:15:38.06#ibcon#*before write, iclass 33, count 2 2006.252.08:15:38.06#ibcon#enter sib2, iclass 33, count 2 2006.252.08:15:38.06#ibcon#flushed, iclass 33, count 2 2006.252.08:15:38.06#ibcon#about to write, iclass 33, count 2 2006.252.08:15:38.06#ibcon#wrote, iclass 33, count 2 2006.252.08:15:38.06#ibcon#about to read 3, iclass 33, count 2 2006.252.08:15:38.09#ibcon#read 3, iclass 33, count 2 2006.252.08:15:38.09#ibcon#about to read 4, iclass 33, count 2 2006.252.08:15:38.09#ibcon#read 4, iclass 33, count 2 2006.252.08:15:38.09#ibcon#about to read 5, iclass 33, count 2 2006.252.08:15:38.09#ibcon#read 5, iclass 33, count 2 2006.252.08:15:38.09#ibcon#about to read 6, iclass 33, count 2 2006.252.08:15:38.09#ibcon#read 6, iclass 33, count 2 2006.252.08:15:38.09#ibcon#end of sib2, iclass 33, count 2 2006.252.08:15:38.09#ibcon#*after write, iclass 33, count 2 2006.252.08:15:38.09#ibcon#*before return 0, iclass 33, count 2 2006.252.08:15:38.09#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.252.08:15:38.09#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.252.08:15:38.09#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.252.08:15:38.09#ibcon#ireg 7 cls_cnt 0 2006.252.08:15:38.09#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.252.08:15:38.21#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.252.08:15:38.21#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.252.08:15:38.21#ibcon#enter wrdev, iclass 33, count 0 2006.252.08:15:38.21#ibcon#first serial, iclass 33, count 0 2006.252.08:15:38.21#ibcon#enter sib2, iclass 33, count 0 2006.252.08:15:38.21#ibcon#flushed, iclass 33, count 0 2006.252.08:15:38.21#ibcon#about to write, iclass 33, count 0 2006.252.08:15:38.21#ibcon#wrote, iclass 33, count 0 2006.252.08:15:38.21#ibcon#about to read 3, iclass 33, count 0 2006.252.08:15:38.23#ibcon#read 3, iclass 33, count 0 2006.252.08:15:38.23#ibcon#about to read 4, iclass 33, count 0 2006.252.08:15:38.23#ibcon#read 4, iclass 33, count 0 2006.252.08:15:38.23#ibcon#about to read 5, iclass 33, count 0 2006.252.08:15:38.23#ibcon#read 5, iclass 33, count 0 2006.252.08:15:38.23#ibcon#about to read 6, iclass 33, count 0 2006.252.08:15:38.23#ibcon#read 6, iclass 33, count 0 2006.252.08:15:38.23#ibcon#end of sib2, iclass 33, count 0 2006.252.08:15:38.23#ibcon#*mode == 0, iclass 33, count 0 2006.252.08:15:38.23#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.252.08:15:38.23#ibcon#[25=USB\r\n] 2006.252.08:15:38.23#ibcon#*before write, iclass 33, count 0 2006.252.08:15:38.23#ibcon#enter sib2, iclass 33, count 0 2006.252.08:15:38.23#ibcon#flushed, iclass 33, count 0 2006.252.08:15:38.23#ibcon#about to write, iclass 33, count 0 2006.252.08:15:38.23#ibcon#wrote, iclass 33, count 0 2006.252.08:15:38.23#ibcon#about to read 3, iclass 33, count 0 2006.252.08:15:38.26#ibcon#read 3, iclass 33, count 0 2006.252.08:15:38.26#ibcon#about to read 4, iclass 33, count 0 2006.252.08:15:38.26#ibcon#read 4, iclass 33, count 0 2006.252.08:15:38.26#ibcon#about to read 5, iclass 33, count 0 2006.252.08:15:38.26#ibcon#read 5, iclass 33, count 0 2006.252.08:15:38.26#ibcon#about to read 6, iclass 33, count 0 2006.252.08:15:38.26#ibcon#read 6, iclass 33, count 0 2006.252.08:15:38.26#ibcon#end of sib2, iclass 33, count 0 2006.252.08:15:38.26#ibcon#*after write, iclass 33, count 0 2006.252.08:15:38.26#ibcon#*before return 0, iclass 33, count 0 2006.252.08:15:38.26#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.252.08:15:38.26#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.252.08:15:38.26#ibcon#about to clear, iclass 33 cls_cnt 0 2006.252.08:15:38.26#ibcon#cleared, iclass 33 cls_cnt 0 2006.252.08:15:38.26$vc4f8/valo=2,572.99 2006.252.08:15:38.26#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.252.08:15:38.26#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.252.08:15:38.26#ibcon#ireg 17 cls_cnt 0 2006.252.08:15:38.26#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.252.08:15:38.26#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.252.08:15:38.26#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.252.08:15:38.26#ibcon#enter wrdev, iclass 35, count 0 2006.252.08:15:38.26#ibcon#first serial, iclass 35, count 0 2006.252.08:15:38.26#ibcon#enter sib2, iclass 35, count 0 2006.252.08:15:38.26#ibcon#flushed, iclass 35, count 0 2006.252.08:15:38.26#ibcon#about to write, iclass 35, count 0 2006.252.08:15:38.26#ibcon#wrote, iclass 35, count 0 2006.252.08:15:38.27#ibcon#about to read 3, iclass 35, count 0 2006.252.08:15:38.29#ibcon#read 3, iclass 35, count 0 2006.252.08:15:38.29#ibcon#about to read 4, iclass 35, count 0 2006.252.08:15:38.29#ibcon#read 4, iclass 35, count 0 2006.252.08:15:38.29#ibcon#about to read 5, iclass 35, count 0 2006.252.08:15:38.29#ibcon#read 5, iclass 35, count 0 2006.252.08:15:38.29#ibcon#about to read 6, iclass 35, count 0 2006.252.08:15:38.29#ibcon#read 6, iclass 35, count 0 2006.252.08:15:38.29#ibcon#end of sib2, iclass 35, count 0 2006.252.08:15:38.29#ibcon#*mode == 0, iclass 35, count 0 2006.252.08:15:38.29#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.252.08:15:38.29#ibcon#[26=FRQ=02,572.99\r\n] 2006.252.08:15:38.29#ibcon#*before write, iclass 35, count 0 2006.252.08:15:38.29#ibcon#enter sib2, iclass 35, count 0 2006.252.08:15:38.29#ibcon#flushed, iclass 35, count 0 2006.252.08:15:38.29#ibcon#about to write, iclass 35, count 0 2006.252.08:15:38.29#ibcon#wrote, iclass 35, count 0 2006.252.08:15:38.29#ibcon#about to read 3, iclass 35, count 0 2006.252.08:15:38.33#ibcon#read 3, iclass 35, count 0 2006.252.08:15:38.33#ibcon#about to read 4, iclass 35, count 0 2006.252.08:15:38.33#ibcon#read 4, iclass 35, count 0 2006.252.08:15:38.33#ibcon#about to read 5, iclass 35, count 0 2006.252.08:15:38.33#ibcon#read 5, iclass 35, count 0 2006.252.08:15:38.33#ibcon#about to read 6, iclass 35, count 0 2006.252.08:15:38.33#ibcon#read 6, iclass 35, count 0 2006.252.08:15:38.33#ibcon#end of sib2, iclass 35, count 0 2006.252.08:15:38.33#ibcon#*after write, iclass 35, count 0 2006.252.08:15:38.33#ibcon#*before return 0, iclass 35, count 0 2006.252.08:15:38.33#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.252.08:15:38.33#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.252.08:15:38.33#ibcon#about to clear, iclass 35 cls_cnt 0 2006.252.08:15:38.33#ibcon#cleared, iclass 35 cls_cnt 0 2006.252.08:15:38.33$vc4f8/va=2,7 2006.252.08:15:38.33#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.252.08:15:38.33#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.252.08:15:38.33#ibcon#ireg 11 cls_cnt 2 2006.252.08:15:38.33#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.252.08:15:38.39#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.252.08:15:38.39#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.252.08:15:38.39#ibcon#enter wrdev, iclass 37, count 2 2006.252.08:15:38.39#ibcon#first serial, iclass 37, count 2 2006.252.08:15:38.39#ibcon#enter sib2, iclass 37, count 2 2006.252.08:15:38.39#ibcon#flushed, iclass 37, count 2 2006.252.08:15:38.39#ibcon#about to write, iclass 37, count 2 2006.252.08:15:38.39#ibcon#wrote, iclass 37, count 2 2006.252.08:15:38.39#ibcon#about to read 3, iclass 37, count 2 2006.252.08:15:38.40#ibcon#read 3, iclass 37, count 2 2006.252.08:15:38.40#ibcon#about to read 4, iclass 37, count 2 2006.252.08:15:38.40#ibcon#read 4, iclass 37, count 2 2006.252.08:15:38.40#ibcon#about to read 5, iclass 37, count 2 2006.252.08:15:38.40#ibcon#read 5, iclass 37, count 2 2006.252.08:15:38.40#ibcon#about to read 6, iclass 37, count 2 2006.252.08:15:38.40#ibcon#read 6, iclass 37, count 2 2006.252.08:15:38.40#ibcon#end of sib2, iclass 37, count 2 2006.252.08:15:38.40#ibcon#*mode == 0, iclass 37, count 2 2006.252.08:15:38.40#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.252.08:15:38.40#ibcon#[25=AT02-07\r\n] 2006.252.08:15:38.40#ibcon#*before write, iclass 37, count 2 2006.252.08:15:38.40#ibcon#enter sib2, iclass 37, count 2 2006.252.08:15:38.40#ibcon#flushed, iclass 37, count 2 2006.252.08:15:38.40#ibcon#about to write, iclass 37, count 2 2006.252.08:15:38.40#ibcon#wrote, iclass 37, count 2 2006.252.08:15:38.40#ibcon#about to read 3, iclass 37, count 2 2006.252.08:15:38.43#ibcon#read 3, iclass 37, count 2 2006.252.08:15:38.43#ibcon#about to read 4, iclass 37, count 2 2006.252.08:15:38.43#ibcon#read 4, iclass 37, count 2 2006.252.08:15:38.43#ibcon#about to read 5, iclass 37, count 2 2006.252.08:15:38.43#ibcon#read 5, iclass 37, count 2 2006.252.08:15:38.43#ibcon#about to read 6, iclass 37, count 2 2006.252.08:15:38.43#ibcon#read 6, iclass 37, count 2 2006.252.08:15:38.43#ibcon#end of sib2, iclass 37, count 2 2006.252.08:15:38.43#ibcon#*after write, iclass 37, count 2 2006.252.08:15:38.43#ibcon#*before return 0, iclass 37, count 2 2006.252.08:15:38.43#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.252.08:15:38.43#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.252.08:15:38.43#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.252.08:15:38.43#ibcon#ireg 7 cls_cnt 0 2006.252.08:15:38.43#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.252.08:15:38.55#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.252.08:15:38.55#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.252.08:15:38.55#ibcon#enter wrdev, iclass 37, count 0 2006.252.08:15:38.55#ibcon#first serial, iclass 37, count 0 2006.252.08:15:38.55#ibcon#enter sib2, iclass 37, count 0 2006.252.08:15:38.55#ibcon#flushed, iclass 37, count 0 2006.252.08:15:38.55#ibcon#about to write, iclass 37, count 0 2006.252.08:15:38.55#ibcon#wrote, iclass 37, count 0 2006.252.08:15:38.55#ibcon#about to read 3, iclass 37, count 0 2006.252.08:15:38.57#ibcon#read 3, iclass 37, count 0 2006.252.08:15:38.57#ibcon#about to read 4, iclass 37, count 0 2006.252.08:15:38.57#ibcon#read 4, iclass 37, count 0 2006.252.08:15:38.57#ibcon#about to read 5, iclass 37, count 0 2006.252.08:15:38.57#ibcon#read 5, iclass 37, count 0 2006.252.08:15:38.57#ibcon#about to read 6, iclass 37, count 0 2006.252.08:15:38.57#ibcon#read 6, iclass 37, count 0 2006.252.08:15:38.57#ibcon#end of sib2, iclass 37, count 0 2006.252.08:15:38.57#ibcon#*mode == 0, iclass 37, count 0 2006.252.08:15:38.57#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.252.08:15:38.57#ibcon#[25=USB\r\n] 2006.252.08:15:38.57#ibcon#*before write, iclass 37, count 0 2006.252.08:15:38.57#ibcon#enter sib2, iclass 37, count 0 2006.252.08:15:38.57#ibcon#flushed, iclass 37, count 0 2006.252.08:15:38.57#ibcon#about to write, iclass 37, count 0 2006.252.08:15:38.57#ibcon#wrote, iclass 37, count 0 2006.252.08:15:38.57#ibcon#about to read 3, iclass 37, count 0 2006.252.08:15:38.60#ibcon#read 3, iclass 37, count 0 2006.252.08:15:38.60#ibcon#about to read 4, iclass 37, count 0 2006.252.08:15:38.60#ibcon#read 4, iclass 37, count 0 2006.252.08:15:38.60#ibcon#about to read 5, iclass 37, count 0 2006.252.08:15:38.60#ibcon#read 5, iclass 37, count 0 2006.252.08:15:38.60#ibcon#about to read 6, iclass 37, count 0 2006.252.08:15:38.60#ibcon#read 6, iclass 37, count 0 2006.252.08:15:38.60#ibcon#end of sib2, iclass 37, count 0 2006.252.08:15:38.60#ibcon#*after write, iclass 37, count 0 2006.252.08:15:38.60#ibcon#*before return 0, iclass 37, count 0 2006.252.08:15:38.60#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.252.08:15:38.60#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.252.08:15:38.60#ibcon#about to clear, iclass 37 cls_cnt 0 2006.252.08:15:38.60#ibcon#cleared, iclass 37 cls_cnt 0 2006.252.08:15:38.60$vc4f8/valo=3,672.99 2006.252.08:15:38.60#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.252.08:15:38.60#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.252.08:15:38.60#ibcon#ireg 17 cls_cnt 0 2006.252.08:15:38.60#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.252.08:15:38.60#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.252.08:15:38.60#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.252.08:15:38.60#ibcon#enter wrdev, iclass 39, count 0 2006.252.08:15:38.60#ibcon#first serial, iclass 39, count 0 2006.252.08:15:38.60#ibcon#enter sib2, iclass 39, count 0 2006.252.08:15:38.60#ibcon#flushed, iclass 39, count 0 2006.252.08:15:38.60#ibcon#about to write, iclass 39, count 0 2006.252.08:15:38.60#ibcon#wrote, iclass 39, count 0 2006.252.08:15:38.60#ibcon#about to read 3, iclass 39, count 0 2006.252.08:15:38.62#ibcon#read 3, iclass 39, count 0 2006.252.08:15:38.62#ibcon#about to read 4, iclass 39, count 0 2006.252.08:15:38.62#ibcon#read 4, iclass 39, count 0 2006.252.08:15:38.62#ibcon#about to read 5, iclass 39, count 0 2006.252.08:15:38.62#ibcon#read 5, iclass 39, count 0 2006.252.08:15:38.62#ibcon#about to read 6, iclass 39, count 0 2006.252.08:15:38.62#ibcon#read 6, iclass 39, count 0 2006.252.08:15:38.62#ibcon#end of sib2, iclass 39, count 0 2006.252.08:15:38.62#ibcon#*mode == 0, iclass 39, count 0 2006.252.08:15:38.62#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.252.08:15:38.62#ibcon#[26=FRQ=03,672.99\r\n] 2006.252.08:15:38.62#ibcon#*before write, iclass 39, count 0 2006.252.08:15:38.62#ibcon#enter sib2, iclass 39, count 0 2006.252.08:15:38.62#ibcon#flushed, iclass 39, count 0 2006.252.08:15:38.62#ibcon#about to write, iclass 39, count 0 2006.252.08:15:38.62#ibcon#wrote, iclass 39, count 0 2006.252.08:15:38.62#ibcon#about to read 3, iclass 39, count 0 2006.252.08:15:38.66#ibcon#read 3, iclass 39, count 0 2006.252.08:15:38.66#ibcon#about to read 4, iclass 39, count 0 2006.252.08:15:38.66#ibcon#read 4, iclass 39, count 0 2006.252.08:15:38.66#ibcon#about to read 5, iclass 39, count 0 2006.252.08:15:38.66#ibcon#read 5, iclass 39, count 0 2006.252.08:15:38.66#ibcon#about to read 6, iclass 39, count 0 2006.252.08:15:38.66#ibcon#read 6, iclass 39, count 0 2006.252.08:15:38.66#ibcon#end of sib2, iclass 39, count 0 2006.252.08:15:38.66#ibcon#*after write, iclass 39, count 0 2006.252.08:15:38.66#ibcon#*before return 0, iclass 39, count 0 2006.252.08:15:38.66#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.252.08:15:38.66#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.252.08:15:38.66#ibcon#about to clear, iclass 39 cls_cnt 0 2006.252.08:15:38.66#ibcon#cleared, iclass 39 cls_cnt 0 2006.252.08:15:38.66$vc4f8/va=3,6 2006.252.08:15:38.66#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.252.08:15:38.66#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.252.08:15:38.66#ibcon#ireg 11 cls_cnt 2 2006.252.08:15:38.66#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.252.08:15:38.73#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.252.08:15:38.73#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.252.08:15:38.73#ibcon#enter wrdev, iclass 3, count 2 2006.252.08:15:38.73#ibcon#first serial, iclass 3, count 2 2006.252.08:15:38.73#ibcon#enter sib2, iclass 3, count 2 2006.252.08:15:38.73#ibcon#flushed, iclass 3, count 2 2006.252.08:15:38.73#ibcon#about to write, iclass 3, count 2 2006.252.08:15:38.73#ibcon#wrote, iclass 3, count 2 2006.252.08:15:38.73#ibcon#about to read 3, iclass 3, count 2 2006.252.08:15:38.74#ibcon#read 3, iclass 3, count 2 2006.252.08:15:38.74#ibcon#about to read 4, iclass 3, count 2 2006.252.08:15:38.74#ibcon#read 4, iclass 3, count 2 2006.252.08:15:38.74#ibcon#about to read 5, iclass 3, count 2 2006.252.08:15:38.74#ibcon#read 5, iclass 3, count 2 2006.252.08:15:38.74#ibcon#about to read 6, iclass 3, count 2 2006.252.08:15:38.75#ibcon#read 6, iclass 3, count 2 2006.252.08:15:38.75#ibcon#end of sib2, iclass 3, count 2 2006.252.08:15:38.75#ibcon#*mode == 0, iclass 3, count 2 2006.252.08:15:38.75#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.252.08:15:38.75#ibcon#[25=AT03-06\r\n] 2006.252.08:15:38.75#ibcon#*before write, iclass 3, count 2 2006.252.08:15:38.75#ibcon#enter sib2, iclass 3, count 2 2006.252.08:15:38.75#ibcon#flushed, iclass 3, count 2 2006.252.08:15:38.75#ibcon#about to write, iclass 3, count 2 2006.252.08:15:38.75#ibcon#wrote, iclass 3, count 2 2006.252.08:15:38.75#ibcon#about to read 3, iclass 3, count 2 2006.252.08:15:38.77#ibcon#read 3, iclass 3, count 2 2006.252.08:15:38.77#ibcon#about to read 4, iclass 3, count 2 2006.252.08:15:38.77#ibcon#read 4, iclass 3, count 2 2006.252.08:15:38.77#ibcon#about to read 5, iclass 3, count 2 2006.252.08:15:38.77#ibcon#read 5, iclass 3, count 2 2006.252.08:15:38.77#ibcon#about to read 6, iclass 3, count 2 2006.252.08:15:38.77#ibcon#read 6, iclass 3, count 2 2006.252.08:15:38.77#ibcon#end of sib2, iclass 3, count 2 2006.252.08:15:38.77#ibcon#*after write, iclass 3, count 2 2006.252.08:15:38.77#ibcon#*before return 0, iclass 3, count 2 2006.252.08:15:38.77#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.252.08:15:38.77#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.252.08:15:38.77#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.252.08:15:38.77#ibcon#ireg 7 cls_cnt 0 2006.252.08:15:38.77#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.252.08:15:38.89#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.252.08:15:38.89#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.252.08:15:38.89#ibcon#enter wrdev, iclass 3, count 0 2006.252.08:15:38.89#ibcon#first serial, iclass 3, count 0 2006.252.08:15:38.89#ibcon#enter sib2, iclass 3, count 0 2006.252.08:15:38.89#ibcon#flushed, iclass 3, count 0 2006.252.08:15:38.89#ibcon#about to write, iclass 3, count 0 2006.252.08:15:38.89#ibcon#wrote, iclass 3, count 0 2006.252.08:15:38.89#ibcon#about to read 3, iclass 3, count 0 2006.252.08:15:38.91#ibcon#read 3, iclass 3, count 0 2006.252.08:15:38.91#ibcon#about to read 4, iclass 3, count 0 2006.252.08:15:38.91#ibcon#read 4, iclass 3, count 0 2006.252.08:15:38.91#ibcon#about to read 5, iclass 3, count 0 2006.252.08:15:38.91#ibcon#read 5, iclass 3, count 0 2006.252.08:15:38.91#ibcon#about to read 6, iclass 3, count 0 2006.252.08:15:38.91#ibcon#read 6, iclass 3, count 0 2006.252.08:15:38.91#ibcon#end of sib2, iclass 3, count 0 2006.252.08:15:38.91#ibcon#*mode == 0, iclass 3, count 0 2006.252.08:15:38.91#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.252.08:15:38.91#ibcon#[25=USB\r\n] 2006.252.08:15:38.91#ibcon#*before write, iclass 3, count 0 2006.252.08:15:38.91#ibcon#enter sib2, iclass 3, count 0 2006.252.08:15:38.91#ibcon#flushed, iclass 3, count 0 2006.252.08:15:38.91#ibcon#about to write, iclass 3, count 0 2006.252.08:15:38.91#ibcon#wrote, iclass 3, count 0 2006.252.08:15:38.91#ibcon#about to read 3, iclass 3, count 0 2006.252.08:15:38.94#ibcon#read 3, iclass 3, count 0 2006.252.08:15:38.94#ibcon#about to read 4, iclass 3, count 0 2006.252.08:15:38.94#ibcon#read 4, iclass 3, count 0 2006.252.08:15:38.94#ibcon#about to read 5, iclass 3, count 0 2006.252.08:15:38.94#ibcon#read 5, iclass 3, count 0 2006.252.08:15:38.94#ibcon#about to read 6, iclass 3, count 0 2006.252.08:15:38.94#ibcon#read 6, iclass 3, count 0 2006.252.08:15:38.94#ibcon#end of sib2, iclass 3, count 0 2006.252.08:15:38.94#ibcon#*after write, iclass 3, count 0 2006.252.08:15:38.94#ibcon#*before return 0, iclass 3, count 0 2006.252.08:15:38.94#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.252.08:15:38.94#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.252.08:15:38.94#ibcon#about to clear, iclass 3 cls_cnt 0 2006.252.08:15:38.94#ibcon#cleared, iclass 3 cls_cnt 0 2006.252.08:15:38.94$vc4f8/valo=4,832.99 2006.252.08:15:38.94#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.252.08:15:38.94#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.252.08:15:38.94#ibcon#ireg 17 cls_cnt 0 2006.252.08:15:38.94#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.252.08:15:38.94#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.252.08:15:38.94#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.252.08:15:38.94#ibcon#enter wrdev, iclass 5, count 0 2006.252.08:15:38.94#ibcon#first serial, iclass 5, count 0 2006.252.08:15:38.94#ibcon#enter sib2, iclass 5, count 0 2006.252.08:15:38.94#ibcon#flushed, iclass 5, count 0 2006.252.08:15:38.94#ibcon#about to write, iclass 5, count 0 2006.252.08:15:38.94#ibcon#wrote, iclass 5, count 0 2006.252.08:15:38.94#ibcon#about to read 3, iclass 5, count 0 2006.252.08:15:38.96#ibcon#read 3, iclass 5, count 0 2006.252.08:15:38.96#ibcon#about to read 4, iclass 5, count 0 2006.252.08:15:38.96#ibcon#read 4, iclass 5, count 0 2006.252.08:15:38.96#ibcon#about to read 5, iclass 5, count 0 2006.252.08:15:38.96#ibcon#read 5, iclass 5, count 0 2006.252.08:15:38.96#ibcon#about to read 6, iclass 5, count 0 2006.252.08:15:38.96#ibcon#read 6, iclass 5, count 0 2006.252.08:15:38.96#ibcon#end of sib2, iclass 5, count 0 2006.252.08:15:38.96#ibcon#*mode == 0, iclass 5, count 0 2006.252.08:15:38.96#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.252.08:15:38.96#ibcon#[26=FRQ=04,832.99\r\n] 2006.252.08:15:38.96#ibcon#*before write, iclass 5, count 0 2006.252.08:15:38.96#ibcon#enter sib2, iclass 5, count 0 2006.252.08:15:38.96#ibcon#flushed, iclass 5, count 0 2006.252.08:15:38.96#ibcon#about to write, iclass 5, count 0 2006.252.08:15:38.96#ibcon#wrote, iclass 5, count 0 2006.252.08:15:38.96#ibcon#about to read 3, iclass 5, count 0 2006.252.08:15:39.00#ibcon#read 3, iclass 5, count 0 2006.252.08:15:39.00#ibcon#about to read 4, iclass 5, count 0 2006.252.08:15:39.00#ibcon#read 4, iclass 5, count 0 2006.252.08:15:39.00#ibcon#about to read 5, iclass 5, count 0 2006.252.08:15:39.00#ibcon#read 5, iclass 5, count 0 2006.252.08:15:39.00#ibcon#about to read 6, iclass 5, count 0 2006.252.08:15:39.00#ibcon#read 6, iclass 5, count 0 2006.252.08:15:39.00#ibcon#end of sib2, iclass 5, count 0 2006.252.08:15:39.00#ibcon#*after write, iclass 5, count 0 2006.252.08:15:39.00#ibcon#*before return 0, iclass 5, count 0 2006.252.08:15:39.00#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.252.08:15:39.00#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.252.08:15:39.00#ibcon#about to clear, iclass 5 cls_cnt 0 2006.252.08:15:39.00#ibcon#cleared, iclass 5 cls_cnt 0 2006.252.08:15:39.00$vc4f8/va=4,7 2006.252.08:15:39.00#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.252.08:15:39.00#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.252.08:15:39.00#ibcon#ireg 11 cls_cnt 2 2006.252.08:15:39.00#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.252.08:15:39.07#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.252.08:15:39.07#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.252.08:15:39.07#ibcon#enter wrdev, iclass 7, count 2 2006.252.08:15:39.07#ibcon#first serial, iclass 7, count 2 2006.252.08:15:39.07#ibcon#enter sib2, iclass 7, count 2 2006.252.08:15:39.07#ibcon#flushed, iclass 7, count 2 2006.252.08:15:39.07#ibcon#about to write, iclass 7, count 2 2006.252.08:15:39.07#ibcon#wrote, iclass 7, count 2 2006.252.08:15:39.07#ibcon#about to read 3, iclass 7, count 2 2006.252.08:15:39.08#ibcon#read 3, iclass 7, count 2 2006.252.08:15:39.08#ibcon#about to read 4, iclass 7, count 2 2006.252.08:15:39.08#ibcon#read 4, iclass 7, count 2 2006.252.08:15:39.08#ibcon#about to read 5, iclass 7, count 2 2006.252.08:15:39.08#ibcon#read 5, iclass 7, count 2 2006.252.08:15:39.08#ibcon#about to read 6, iclass 7, count 2 2006.252.08:15:39.08#ibcon#read 6, iclass 7, count 2 2006.252.08:15:39.08#ibcon#end of sib2, iclass 7, count 2 2006.252.08:15:39.08#ibcon#*mode == 0, iclass 7, count 2 2006.252.08:15:39.08#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.252.08:15:39.08#ibcon#[25=AT04-07\r\n] 2006.252.08:15:39.08#ibcon#*before write, iclass 7, count 2 2006.252.08:15:39.08#ibcon#enter sib2, iclass 7, count 2 2006.252.08:15:39.08#ibcon#flushed, iclass 7, count 2 2006.252.08:15:39.08#ibcon#about to write, iclass 7, count 2 2006.252.08:15:39.08#ibcon#wrote, iclass 7, count 2 2006.252.08:15:39.08#ibcon#about to read 3, iclass 7, count 2 2006.252.08:15:39.11#ibcon#read 3, iclass 7, count 2 2006.252.08:15:39.11#ibcon#about to read 4, iclass 7, count 2 2006.252.08:15:39.11#ibcon#read 4, iclass 7, count 2 2006.252.08:15:39.11#ibcon#about to read 5, iclass 7, count 2 2006.252.08:15:39.11#ibcon#read 5, iclass 7, count 2 2006.252.08:15:39.11#ibcon#about to read 6, iclass 7, count 2 2006.252.08:15:39.11#ibcon#read 6, iclass 7, count 2 2006.252.08:15:39.11#ibcon#end of sib2, iclass 7, count 2 2006.252.08:15:39.11#ibcon#*after write, iclass 7, count 2 2006.252.08:15:39.11#ibcon#*before return 0, iclass 7, count 2 2006.252.08:15:39.11#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.252.08:15:39.11#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.252.08:15:39.11#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.252.08:15:39.11#ibcon#ireg 7 cls_cnt 0 2006.252.08:15:39.11#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.252.08:15:39.23#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.252.08:15:39.23#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.252.08:15:39.23#ibcon#enter wrdev, iclass 7, count 0 2006.252.08:15:39.23#ibcon#first serial, iclass 7, count 0 2006.252.08:15:39.23#ibcon#enter sib2, iclass 7, count 0 2006.252.08:15:39.23#ibcon#flushed, iclass 7, count 0 2006.252.08:15:39.23#ibcon#about to write, iclass 7, count 0 2006.252.08:15:39.23#ibcon#wrote, iclass 7, count 0 2006.252.08:15:39.23#ibcon#about to read 3, iclass 7, count 0 2006.252.08:15:39.25#ibcon#read 3, iclass 7, count 0 2006.252.08:15:39.25#ibcon#about to read 4, iclass 7, count 0 2006.252.08:15:39.25#ibcon#read 4, iclass 7, count 0 2006.252.08:15:39.25#ibcon#about to read 5, iclass 7, count 0 2006.252.08:15:39.25#ibcon#read 5, iclass 7, count 0 2006.252.08:15:39.25#ibcon#about to read 6, iclass 7, count 0 2006.252.08:15:39.25#ibcon#read 6, iclass 7, count 0 2006.252.08:15:39.25#ibcon#end of sib2, iclass 7, count 0 2006.252.08:15:39.25#ibcon#*mode == 0, iclass 7, count 0 2006.252.08:15:39.25#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.252.08:15:39.25#ibcon#[25=USB\r\n] 2006.252.08:15:39.25#ibcon#*before write, iclass 7, count 0 2006.252.08:15:39.25#ibcon#enter sib2, iclass 7, count 0 2006.252.08:15:39.25#ibcon#flushed, iclass 7, count 0 2006.252.08:15:39.25#ibcon#about to write, iclass 7, count 0 2006.252.08:15:39.25#ibcon#wrote, iclass 7, count 0 2006.252.08:15:39.25#ibcon#about to read 3, iclass 7, count 0 2006.252.08:15:39.28#ibcon#read 3, iclass 7, count 0 2006.252.08:15:39.28#ibcon#about to read 4, iclass 7, count 0 2006.252.08:15:39.28#ibcon#read 4, iclass 7, count 0 2006.252.08:15:39.28#ibcon#about to read 5, iclass 7, count 0 2006.252.08:15:39.28#ibcon#read 5, iclass 7, count 0 2006.252.08:15:39.28#ibcon#about to read 6, iclass 7, count 0 2006.252.08:15:39.28#ibcon#read 6, iclass 7, count 0 2006.252.08:15:39.28#ibcon#end of sib2, iclass 7, count 0 2006.252.08:15:39.28#ibcon#*after write, iclass 7, count 0 2006.252.08:15:39.28#ibcon#*before return 0, iclass 7, count 0 2006.252.08:15:39.28#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.252.08:15:39.28#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.252.08:15:39.28#ibcon#about to clear, iclass 7 cls_cnt 0 2006.252.08:15:39.28#ibcon#cleared, iclass 7 cls_cnt 0 2006.252.08:15:39.28$vc4f8/valo=5,652.99 2006.252.08:15:39.28#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.252.08:15:39.28#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.252.08:15:39.28#ibcon#ireg 17 cls_cnt 0 2006.252.08:15:39.28#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.252.08:15:39.28#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.252.08:15:39.28#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.252.08:15:39.28#ibcon#enter wrdev, iclass 11, count 0 2006.252.08:15:39.28#ibcon#first serial, iclass 11, count 0 2006.252.08:15:39.28#ibcon#enter sib2, iclass 11, count 0 2006.252.08:15:39.28#ibcon#flushed, iclass 11, count 0 2006.252.08:15:39.28#ibcon#about to write, iclass 11, count 0 2006.252.08:15:39.28#ibcon#wrote, iclass 11, count 0 2006.252.08:15:39.29#ibcon#about to read 3, iclass 11, count 0 2006.252.08:15:39.30#ibcon#read 3, iclass 11, count 0 2006.252.08:15:39.30#ibcon#about to read 4, iclass 11, count 0 2006.252.08:15:39.30#ibcon#read 4, iclass 11, count 0 2006.252.08:15:39.30#ibcon#about to read 5, iclass 11, count 0 2006.252.08:15:39.30#ibcon#read 5, iclass 11, count 0 2006.252.08:15:39.30#ibcon#about to read 6, iclass 11, count 0 2006.252.08:15:39.30#ibcon#read 6, iclass 11, count 0 2006.252.08:15:39.30#ibcon#end of sib2, iclass 11, count 0 2006.252.08:15:39.30#ibcon#*mode == 0, iclass 11, count 0 2006.252.08:15:39.30#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.252.08:15:39.30#ibcon#[26=FRQ=05,652.99\r\n] 2006.252.08:15:39.30#ibcon#*before write, iclass 11, count 0 2006.252.08:15:39.30#ibcon#enter sib2, iclass 11, count 0 2006.252.08:15:39.30#ibcon#flushed, iclass 11, count 0 2006.252.08:15:39.30#ibcon#about to write, iclass 11, count 0 2006.252.08:15:39.30#ibcon#wrote, iclass 11, count 0 2006.252.08:15:39.30#ibcon#about to read 3, iclass 11, count 0 2006.252.08:15:39.34#ibcon#read 3, iclass 11, count 0 2006.252.08:15:39.34#ibcon#about to read 4, iclass 11, count 0 2006.252.08:15:39.34#ibcon#read 4, iclass 11, count 0 2006.252.08:15:39.34#ibcon#about to read 5, iclass 11, count 0 2006.252.08:15:39.34#ibcon#read 5, iclass 11, count 0 2006.252.08:15:39.34#ibcon#about to read 6, iclass 11, count 0 2006.252.08:15:39.34#ibcon#read 6, iclass 11, count 0 2006.252.08:15:39.34#ibcon#end of sib2, iclass 11, count 0 2006.252.08:15:39.34#ibcon#*after write, iclass 11, count 0 2006.252.08:15:39.34#ibcon#*before return 0, iclass 11, count 0 2006.252.08:15:39.34#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.252.08:15:39.34#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.252.08:15:39.34#ibcon#about to clear, iclass 11 cls_cnt 0 2006.252.08:15:39.34#ibcon#cleared, iclass 11 cls_cnt 0 2006.252.08:15:39.34$vc4f8/va=5,7 2006.252.08:15:39.34#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.252.08:15:39.34#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.252.08:15:39.34#ibcon#ireg 11 cls_cnt 2 2006.252.08:15:39.34#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.252.08:15:39.40#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.252.08:15:39.40#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.252.08:15:39.40#ibcon#enter wrdev, iclass 13, count 2 2006.252.08:15:39.40#ibcon#first serial, iclass 13, count 2 2006.252.08:15:39.40#ibcon#enter sib2, iclass 13, count 2 2006.252.08:15:39.40#ibcon#flushed, iclass 13, count 2 2006.252.08:15:39.40#ibcon#about to write, iclass 13, count 2 2006.252.08:15:39.40#ibcon#wrote, iclass 13, count 2 2006.252.08:15:39.40#ibcon#about to read 3, iclass 13, count 2 2006.252.08:15:39.42#ibcon#read 3, iclass 13, count 2 2006.252.08:15:39.42#ibcon#about to read 4, iclass 13, count 2 2006.252.08:15:39.42#ibcon#read 4, iclass 13, count 2 2006.252.08:15:39.42#ibcon#about to read 5, iclass 13, count 2 2006.252.08:15:39.42#ibcon#read 5, iclass 13, count 2 2006.252.08:15:39.42#ibcon#about to read 6, iclass 13, count 2 2006.252.08:15:39.42#ibcon#read 6, iclass 13, count 2 2006.252.08:15:39.42#ibcon#end of sib2, iclass 13, count 2 2006.252.08:15:39.42#ibcon#*mode == 0, iclass 13, count 2 2006.252.08:15:39.42#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.252.08:15:39.42#ibcon#[25=AT05-07\r\n] 2006.252.08:15:39.42#ibcon#*before write, iclass 13, count 2 2006.252.08:15:39.42#ibcon#enter sib2, iclass 13, count 2 2006.252.08:15:39.42#ibcon#flushed, iclass 13, count 2 2006.252.08:15:39.42#ibcon#about to write, iclass 13, count 2 2006.252.08:15:39.42#ibcon#wrote, iclass 13, count 2 2006.252.08:15:39.42#ibcon#about to read 3, iclass 13, count 2 2006.252.08:15:39.45#ibcon#read 3, iclass 13, count 2 2006.252.08:15:39.45#ibcon#about to read 4, iclass 13, count 2 2006.252.08:15:39.45#ibcon#read 4, iclass 13, count 2 2006.252.08:15:39.45#ibcon#about to read 5, iclass 13, count 2 2006.252.08:15:39.45#ibcon#read 5, iclass 13, count 2 2006.252.08:15:39.45#ibcon#about to read 6, iclass 13, count 2 2006.252.08:15:39.45#ibcon#read 6, iclass 13, count 2 2006.252.08:15:39.45#ibcon#end of sib2, iclass 13, count 2 2006.252.08:15:39.45#ibcon#*after write, iclass 13, count 2 2006.252.08:15:39.45#ibcon#*before return 0, iclass 13, count 2 2006.252.08:15:39.45#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.252.08:15:39.45#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.252.08:15:39.45#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.252.08:15:39.45#ibcon#ireg 7 cls_cnt 0 2006.252.08:15:39.45#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.252.08:15:39.57#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.252.08:15:39.57#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.252.08:15:39.57#ibcon#enter wrdev, iclass 13, count 0 2006.252.08:15:39.57#ibcon#first serial, iclass 13, count 0 2006.252.08:15:39.57#ibcon#enter sib2, iclass 13, count 0 2006.252.08:15:39.57#ibcon#flushed, iclass 13, count 0 2006.252.08:15:39.57#ibcon#about to write, iclass 13, count 0 2006.252.08:15:39.57#ibcon#wrote, iclass 13, count 0 2006.252.08:15:39.57#ibcon#about to read 3, iclass 13, count 0 2006.252.08:15:39.59#ibcon#read 3, iclass 13, count 0 2006.252.08:15:39.59#ibcon#about to read 4, iclass 13, count 0 2006.252.08:15:39.59#ibcon#read 4, iclass 13, count 0 2006.252.08:15:39.59#ibcon#about to read 5, iclass 13, count 0 2006.252.08:15:39.59#ibcon#read 5, iclass 13, count 0 2006.252.08:15:39.59#ibcon#about to read 6, iclass 13, count 0 2006.252.08:15:39.59#ibcon#read 6, iclass 13, count 0 2006.252.08:15:39.59#ibcon#end of sib2, iclass 13, count 0 2006.252.08:15:39.59#ibcon#*mode == 0, iclass 13, count 0 2006.252.08:15:39.59#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.252.08:15:39.59#ibcon#[25=USB\r\n] 2006.252.08:15:39.59#ibcon#*before write, iclass 13, count 0 2006.252.08:15:39.59#ibcon#enter sib2, iclass 13, count 0 2006.252.08:15:39.59#ibcon#flushed, iclass 13, count 0 2006.252.08:15:39.59#ibcon#about to write, iclass 13, count 0 2006.252.08:15:39.59#ibcon#wrote, iclass 13, count 0 2006.252.08:15:39.59#ibcon#about to read 3, iclass 13, count 0 2006.252.08:15:39.62#ibcon#read 3, iclass 13, count 0 2006.252.08:15:39.62#ibcon#about to read 4, iclass 13, count 0 2006.252.08:15:39.62#ibcon#read 4, iclass 13, count 0 2006.252.08:15:39.62#ibcon#about to read 5, iclass 13, count 0 2006.252.08:15:39.62#ibcon#read 5, iclass 13, count 0 2006.252.08:15:39.62#ibcon#about to read 6, iclass 13, count 0 2006.252.08:15:39.62#ibcon#read 6, iclass 13, count 0 2006.252.08:15:39.62#ibcon#end of sib2, iclass 13, count 0 2006.252.08:15:39.62#ibcon#*after write, iclass 13, count 0 2006.252.08:15:39.62#ibcon#*before return 0, iclass 13, count 0 2006.252.08:15:39.62#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.252.08:15:39.62#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.252.08:15:39.62#ibcon#about to clear, iclass 13 cls_cnt 0 2006.252.08:15:39.62#ibcon#cleared, iclass 13 cls_cnt 0 2006.252.08:15:39.62$vc4f8/valo=6,772.99 2006.252.08:15:39.62#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.252.08:15:39.62#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.252.08:15:39.62#ibcon#ireg 17 cls_cnt 0 2006.252.08:15:39.62#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.252.08:15:39.62#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.252.08:15:39.62#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.252.08:15:39.62#ibcon#enter wrdev, iclass 15, count 0 2006.252.08:15:39.62#ibcon#first serial, iclass 15, count 0 2006.252.08:15:39.62#ibcon#enter sib2, iclass 15, count 0 2006.252.08:15:39.62#ibcon#flushed, iclass 15, count 0 2006.252.08:15:39.62#ibcon#about to write, iclass 15, count 0 2006.252.08:15:39.62#ibcon#wrote, iclass 15, count 0 2006.252.08:15:39.62#ibcon#about to read 3, iclass 15, count 0 2006.252.08:15:39.64#ibcon#read 3, iclass 15, count 0 2006.252.08:15:39.64#ibcon#about to read 4, iclass 15, count 0 2006.252.08:15:39.64#ibcon#read 4, iclass 15, count 0 2006.252.08:15:39.64#ibcon#about to read 5, iclass 15, count 0 2006.252.08:15:39.64#ibcon#read 5, iclass 15, count 0 2006.252.08:15:39.64#ibcon#about to read 6, iclass 15, count 0 2006.252.08:15:39.64#ibcon#read 6, iclass 15, count 0 2006.252.08:15:39.64#ibcon#end of sib2, iclass 15, count 0 2006.252.08:15:39.64#ibcon#*mode == 0, iclass 15, count 0 2006.252.08:15:39.64#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.252.08:15:39.64#ibcon#[26=FRQ=06,772.99\r\n] 2006.252.08:15:39.64#ibcon#*before write, iclass 15, count 0 2006.252.08:15:39.64#ibcon#enter sib2, iclass 15, count 0 2006.252.08:15:39.64#ibcon#flushed, iclass 15, count 0 2006.252.08:15:39.64#ibcon#about to write, iclass 15, count 0 2006.252.08:15:39.64#ibcon#wrote, iclass 15, count 0 2006.252.08:15:39.64#ibcon#about to read 3, iclass 15, count 0 2006.252.08:15:39.68#ibcon#read 3, iclass 15, count 0 2006.252.08:15:39.68#ibcon#about to read 4, iclass 15, count 0 2006.252.08:15:39.68#ibcon#read 4, iclass 15, count 0 2006.252.08:15:39.68#ibcon#about to read 5, iclass 15, count 0 2006.252.08:15:39.68#ibcon#read 5, iclass 15, count 0 2006.252.08:15:39.68#ibcon#about to read 6, iclass 15, count 0 2006.252.08:15:39.68#ibcon#read 6, iclass 15, count 0 2006.252.08:15:39.68#ibcon#end of sib2, iclass 15, count 0 2006.252.08:15:39.68#ibcon#*after write, iclass 15, count 0 2006.252.08:15:39.68#ibcon#*before return 0, iclass 15, count 0 2006.252.08:15:39.68#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.252.08:15:39.68#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.252.08:15:39.68#ibcon#about to clear, iclass 15 cls_cnt 0 2006.252.08:15:39.68#ibcon#cleared, iclass 15 cls_cnt 0 2006.252.08:15:39.68$vc4f8/va=6,7 2006.252.08:15:39.68#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.252.08:15:39.68#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.252.08:15:39.68#ibcon#ireg 11 cls_cnt 2 2006.252.08:15:39.68#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.252.08:15:39.75#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.252.08:15:39.75#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.252.08:15:39.75#ibcon#enter wrdev, iclass 17, count 2 2006.252.08:15:39.75#ibcon#first serial, iclass 17, count 2 2006.252.08:15:39.75#ibcon#enter sib2, iclass 17, count 2 2006.252.08:15:39.75#ibcon#flushed, iclass 17, count 2 2006.252.08:15:39.75#ibcon#about to write, iclass 17, count 2 2006.252.08:15:39.75#ibcon#wrote, iclass 17, count 2 2006.252.08:15:39.75#ibcon#about to read 3, iclass 17, count 2 2006.252.08:15:39.76#ibcon#read 3, iclass 17, count 2 2006.252.08:15:39.76#ibcon#about to read 4, iclass 17, count 2 2006.252.08:15:39.76#ibcon#read 4, iclass 17, count 2 2006.252.08:15:39.76#ibcon#about to read 5, iclass 17, count 2 2006.252.08:15:39.76#ibcon#read 5, iclass 17, count 2 2006.252.08:15:39.76#ibcon#about to read 6, iclass 17, count 2 2006.252.08:15:39.76#ibcon#read 6, iclass 17, count 2 2006.252.08:15:39.76#ibcon#end of sib2, iclass 17, count 2 2006.252.08:15:39.76#ibcon#*mode == 0, iclass 17, count 2 2006.252.08:15:39.76#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.252.08:15:39.76#ibcon#[25=AT06-07\r\n] 2006.252.08:15:39.76#ibcon#*before write, iclass 17, count 2 2006.252.08:15:39.76#ibcon#enter sib2, iclass 17, count 2 2006.252.08:15:39.76#ibcon#flushed, iclass 17, count 2 2006.252.08:15:39.76#ibcon#about to write, iclass 17, count 2 2006.252.08:15:39.76#ibcon#wrote, iclass 17, count 2 2006.252.08:15:39.76#ibcon#about to read 3, iclass 17, count 2 2006.252.08:15:39.79#ibcon#read 3, iclass 17, count 2 2006.252.08:15:39.79#ibcon#about to read 4, iclass 17, count 2 2006.252.08:15:39.79#ibcon#read 4, iclass 17, count 2 2006.252.08:15:39.79#ibcon#about to read 5, iclass 17, count 2 2006.252.08:15:39.79#ibcon#read 5, iclass 17, count 2 2006.252.08:15:39.79#ibcon#about to read 6, iclass 17, count 2 2006.252.08:15:39.79#ibcon#read 6, iclass 17, count 2 2006.252.08:15:39.79#ibcon#end of sib2, iclass 17, count 2 2006.252.08:15:39.79#ibcon#*after write, iclass 17, count 2 2006.252.08:15:39.79#ibcon#*before return 0, iclass 17, count 2 2006.252.08:15:39.79#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.252.08:15:39.79#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.252.08:15:39.79#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.252.08:15:39.79#ibcon#ireg 7 cls_cnt 0 2006.252.08:15:39.79#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.252.08:15:39.91#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.252.08:15:39.91#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.252.08:15:39.91#ibcon#enter wrdev, iclass 17, count 0 2006.252.08:15:39.91#ibcon#first serial, iclass 17, count 0 2006.252.08:15:39.91#ibcon#enter sib2, iclass 17, count 0 2006.252.08:15:39.91#ibcon#flushed, iclass 17, count 0 2006.252.08:15:39.91#ibcon#about to write, iclass 17, count 0 2006.252.08:15:39.91#ibcon#wrote, iclass 17, count 0 2006.252.08:15:39.91#ibcon#about to read 3, iclass 17, count 0 2006.252.08:15:39.93#ibcon#read 3, iclass 17, count 0 2006.252.08:15:39.93#ibcon#about to read 4, iclass 17, count 0 2006.252.08:15:39.93#ibcon#read 4, iclass 17, count 0 2006.252.08:15:39.93#ibcon#about to read 5, iclass 17, count 0 2006.252.08:15:39.93#ibcon#read 5, iclass 17, count 0 2006.252.08:15:39.93#ibcon#about to read 6, iclass 17, count 0 2006.252.08:15:39.93#ibcon#read 6, iclass 17, count 0 2006.252.08:15:39.93#ibcon#end of sib2, iclass 17, count 0 2006.252.08:15:39.93#ibcon#*mode == 0, iclass 17, count 0 2006.252.08:15:39.93#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.252.08:15:39.93#ibcon#[25=USB\r\n] 2006.252.08:15:39.93#ibcon#*before write, iclass 17, count 0 2006.252.08:15:39.93#ibcon#enter sib2, iclass 17, count 0 2006.252.08:15:39.93#ibcon#flushed, iclass 17, count 0 2006.252.08:15:39.93#ibcon#about to write, iclass 17, count 0 2006.252.08:15:39.93#ibcon#wrote, iclass 17, count 0 2006.252.08:15:39.93#ibcon#about to read 3, iclass 17, count 0 2006.252.08:15:39.96#ibcon#read 3, iclass 17, count 0 2006.252.08:15:39.96#ibcon#about to read 4, iclass 17, count 0 2006.252.08:15:39.96#ibcon#read 4, iclass 17, count 0 2006.252.08:15:39.96#ibcon#about to read 5, iclass 17, count 0 2006.252.08:15:39.96#ibcon#read 5, iclass 17, count 0 2006.252.08:15:39.96#ibcon#about to read 6, iclass 17, count 0 2006.252.08:15:39.96#ibcon#read 6, iclass 17, count 0 2006.252.08:15:39.96#ibcon#end of sib2, iclass 17, count 0 2006.252.08:15:39.96#ibcon#*after write, iclass 17, count 0 2006.252.08:15:39.96#ibcon#*before return 0, iclass 17, count 0 2006.252.08:15:39.96#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.252.08:15:39.96#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.252.08:15:39.96#ibcon#about to clear, iclass 17 cls_cnt 0 2006.252.08:15:39.96#ibcon#cleared, iclass 17 cls_cnt 0 2006.252.08:15:39.96$vc4f8/valo=7,832.99 2006.252.08:15:39.96#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.252.08:15:39.96#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.252.08:15:39.96#ibcon#ireg 17 cls_cnt 0 2006.252.08:15:39.96#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.252.08:15:39.96#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.252.08:15:39.96#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.252.08:15:39.96#ibcon#enter wrdev, iclass 19, count 0 2006.252.08:15:39.96#ibcon#first serial, iclass 19, count 0 2006.252.08:15:39.96#ibcon#enter sib2, iclass 19, count 0 2006.252.08:15:39.96#ibcon#flushed, iclass 19, count 0 2006.252.08:15:39.96#ibcon#about to write, iclass 19, count 0 2006.252.08:15:39.96#ibcon#wrote, iclass 19, count 0 2006.252.08:15:39.96#ibcon#about to read 3, iclass 19, count 0 2006.252.08:15:39.98#ibcon#read 3, iclass 19, count 0 2006.252.08:15:39.98#ibcon#about to read 4, iclass 19, count 0 2006.252.08:15:39.98#ibcon#read 4, iclass 19, count 0 2006.252.08:15:39.98#ibcon#about to read 5, iclass 19, count 0 2006.252.08:15:39.98#ibcon#read 5, iclass 19, count 0 2006.252.08:15:39.98#ibcon#about to read 6, iclass 19, count 0 2006.252.08:15:39.98#ibcon#read 6, iclass 19, count 0 2006.252.08:15:39.98#ibcon#end of sib2, iclass 19, count 0 2006.252.08:15:39.98#ibcon#*mode == 0, iclass 19, count 0 2006.252.08:15:39.98#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.252.08:15:39.98#ibcon#[26=FRQ=07,832.99\r\n] 2006.252.08:15:39.98#ibcon#*before write, iclass 19, count 0 2006.252.08:15:39.98#ibcon#enter sib2, iclass 19, count 0 2006.252.08:15:39.98#ibcon#flushed, iclass 19, count 0 2006.252.08:15:39.98#ibcon#about to write, iclass 19, count 0 2006.252.08:15:39.98#ibcon#wrote, iclass 19, count 0 2006.252.08:15:39.98#ibcon#about to read 3, iclass 19, count 0 2006.252.08:15:40.02#ibcon#read 3, iclass 19, count 0 2006.252.08:15:40.02#ibcon#about to read 4, iclass 19, count 0 2006.252.08:15:40.02#ibcon#read 4, iclass 19, count 0 2006.252.08:15:40.02#ibcon#about to read 5, iclass 19, count 0 2006.252.08:15:40.02#ibcon#read 5, iclass 19, count 0 2006.252.08:15:40.02#ibcon#about to read 6, iclass 19, count 0 2006.252.08:15:40.02#ibcon#read 6, iclass 19, count 0 2006.252.08:15:40.02#ibcon#end of sib2, iclass 19, count 0 2006.252.08:15:40.02#ibcon#*after write, iclass 19, count 0 2006.252.08:15:40.02#ibcon#*before return 0, iclass 19, count 0 2006.252.08:15:40.02#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.252.08:15:40.02#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.252.08:15:40.02#ibcon#about to clear, iclass 19 cls_cnt 0 2006.252.08:15:40.02#ibcon#cleared, iclass 19 cls_cnt 0 2006.252.08:15:40.02$vc4f8/va=7,7 2006.252.08:15:40.02#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.252.08:15:40.02#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.252.08:15:40.02#ibcon#ireg 11 cls_cnt 2 2006.252.08:15:40.02#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.252.08:15:40.08#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.252.08:15:40.08#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.252.08:15:40.08#ibcon#enter wrdev, iclass 21, count 2 2006.252.08:15:40.08#ibcon#first serial, iclass 21, count 2 2006.252.08:15:40.08#ibcon#enter sib2, iclass 21, count 2 2006.252.08:15:40.08#ibcon#flushed, iclass 21, count 2 2006.252.08:15:40.08#ibcon#about to write, iclass 21, count 2 2006.252.08:15:40.08#ibcon#wrote, iclass 21, count 2 2006.252.08:15:40.08#ibcon#about to read 3, iclass 21, count 2 2006.252.08:15:40.10#ibcon#read 3, iclass 21, count 2 2006.252.08:15:40.10#ibcon#about to read 4, iclass 21, count 2 2006.252.08:15:40.10#ibcon#read 4, iclass 21, count 2 2006.252.08:15:40.10#ibcon#about to read 5, iclass 21, count 2 2006.252.08:15:40.10#ibcon#read 5, iclass 21, count 2 2006.252.08:15:40.10#ibcon#about to read 6, iclass 21, count 2 2006.252.08:15:40.10#ibcon#read 6, iclass 21, count 2 2006.252.08:15:40.10#ibcon#end of sib2, iclass 21, count 2 2006.252.08:15:40.10#ibcon#*mode == 0, iclass 21, count 2 2006.252.08:15:40.10#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.252.08:15:40.10#ibcon#[25=AT07-07\r\n] 2006.252.08:15:40.10#ibcon#*before write, iclass 21, count 2 2006.252.08:15:40.10#ibcon#enter sib2, iclass 21, count 2 2006.252.08:15:40.10#ibcon#flushed, iclass 21, count 2 2006.252.08:15:40.10#ibcon#about to write, iclass 21, count 2 2006.252.08:15:40.10#ibcon#wrote, iclass 21, count 2 2006.252.08:15:40.10#ibcon#about to read 3, iclass 21, count 2 2006.252.08:15:40.13#ibcon#read 3, iclass 21, count 2 2006.252.08:15:40.13#ibcon#about to read 4, iclass 21, count 2 2006.252.08:15:40.13#ibcon#read 4, iclass 21, count 2 2006.252.08:15:40.13#ibcon#about to read 5, iclass 21, count 2 2006.252.08:15:40.13#ibcon#read 5, iclass 21, count 2 2006.252.08:15:40.13#ibcon#about to read 6, iclass 21, count 2 2006.252.08:15:40.13#ibcon#read 6, iclass 21, count 2 2006.252.08:15:40.13#ibcon#end of sib2, iclass 21, count 2 2006.252.08:15:40.13#ibcon#*after write, iclass 21, count 2 2006.252.08:15:40.13#ibcon#*before return 0, iclass 21, count 2 2006.252.08:15:40.13#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.252.08:15:40.13#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.252.08:15:40.13#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.252.08:15:40.13#ibcon#ireg 7 cls_cnt 0 2006.252.08:15:40.13#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.252.08:15:40.25#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.252.08:15:40.25#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.252.08:15:40.25#ibcon#enter wrdev, iclass 21, count 0 2006.252.08:15:40.25#ibcon#first serial, iclass 21, count 0 2006.252.08:15:40.25#ibcon#enter sib2, iclass 21, count 0 2006.252.08:15:40.25#ibcon#flushed, iclass 21, count 0 2006.252.08:15:40.25#ibcon#about to write, iclass 21, count 0 2006.252.08:15:40.25#ibcon#wrote, iclass 21, count 0 2006.252.08:15:40.25#ibcon#about to read 3, iclass 21, count 0 2006.252.08:15:40.27#ibcon#read 3, iclass 21, count 0 2006.252.08:15:40.27#ibcon#about to read 4, iclass 21, count 0 2006.252.08:15:40.27#ibcon#read 4, iclass 21, count 0 2006.252.08:15:40.27#ibcon#about to read 5, iclass 21, count 0 2006.252.08:15:40.27#ibcon#read 5, iclass 21, count 0 2006.252.08:15:40.27#ibcon#about to read 6, iclass 21, count 0 2006.252.08:15:40.27#ibcon#read 6, iclass 21, count 0 2006.252.08:15:40.27#ibcon#end of sib2, iclass 21, count 0 2006.252.08:15:40.27#ibcon#*mode == 0, iclass 21, count 0 2006.252.08:15:40.27#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.252.08:15:40.27#ibcon#[25=USB\r\n] 2006.252.08:15:40.27#ibcon#*before write, iclass 21, count 0 2006.252.08:15:40.27#ibcon#enter sib2, iclass 21, count 0 2006.252.08:15:40.27#ibcon#flushed, iclass 21, count 0 2006.252.08:15:40.27#ibcon#about to write, iclass 21, count 0 2006.252.08:15:40.27#ibcon#wrote, iclass 21, count 0 2006.252.08:15:40.27#ibcon#about to read 3, iclass 21, count 0 2006.252.08:15:40.30#ibcon#read 3, iclass 21, count 0 2006.252.08:15:40.30#ibcon#about to read 4, iclass 21, count 0 2006.252.08:15:40.30#ibcon#read 4, iclass 21, count 0 2006.252.08:15:40.30#ibcon#about to read 5, iclass 21, count 0 2006.252.08:15:40.30#ibcon#read 5, iclass 21, count 0 2006.252.08:15:40.30#ibcon#about to read 6, iclass 21, count 0 2006.252.08:15:40.30#ibcon#read 6, iclass 21, count 0 2006.252.08:15:40.30#ibcon#end of sib2, iclass 21, count 0 2006.252.08:15:40.30#ibcon#*after write, iclass 21, count 0 2006.252.08:15:40.30#ibcon#*before return 0, iclass 21, count 0 2006.252.08:15:40.30#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.252.08:15:40.30#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.252.08:15:40.30#ibcon#about to clear, iclass 21 cls_cnt 0 2006.252.08:15:40.30#ibcon#cleared, iclass 21 cls_cnt 0 2006.252.08:15:40.30$vc4f8/valo=8,852.99 2006.252.08:15:40.30#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.252.08:15:40.30#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.252.08:15:40.30#ibcon#ireg 17 cls_cnt 0 2006.252.08:15:40.30#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.252.08:15:40.30#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.252.08:15:40.30#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.252.08:15:40.30#ibcon#enter wrdev, iclass 23, count 0 2006.252.08:15:40.30#ibcon#first serial, iclass 23, count 0 2006.252.08:15:40.30#ibcon#enter sib2, iclass 23, count 0 2006.252.08:15:40.30#ibcon#flushed, iclass 23, count 0 2006.252.08:15:40.30#ibcon#about to write, iclass 23, count 0 2006.252.08:15:40.30#ibcon#wrote, iclass 23, count 0 2006.252.08:15:40.30#ibcon#about to read 3, iclass 23, count 0 2006.252.08:15:40.32#ibcon#read 3, iclass 23, count 0 2006.252.08:15:40.32#ibcon#about to read 4, iclass 23, count 0 2006.252.08:15:40.32#ibcon#read 4, iclass 23, count 0 2006.252.08:15:40.32#ibcon#about to read 5, iclass 23, count 0 2006.252.08:15:40.32#ibcon#read 5, iclass 23, count 0 2006.252.08:15:40.32#ibcon#about to read 6, iclass 23, count 0 2006.252.08:15:40.32#ibcon#read 6, iclass 23, count 0 2006.252.08:15:40.32#ibcon#end of sib2, iclass 23, count 0 2006.252.08:15:40.32#ibcon#*mode == 0, iclass 23, count 0 2006.252.08:15:40.32#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.252.08:15:40.32#ibcon#[26=FRQ=08,852.99\r\n] 2006.252.08:15:40.32#ibcon#*before write, iclass 23, count 0 2006.252.08:15:40.32#ibcon#enter sib2, iclass 23, count 0 2006.252.08:15:40.32#ibcon#flushed, iclass 23, count 0 2006.252.08:15:40.32#ibcon#about to write, iclass 23, count 0 2006.252.08:15:40.32#ibcon#wrote, iclass 23, count 0 2006.252.08:15:40.32#ibcon#about to read 3, iclass 23, count 0 2006.252.08:15:40.36#ibcon#read 3, iclass 23, count 0 2006.252.08:15:40.36#ibcon#about to read 4, iclass 23, count 0 2006.252.08:15:40.36#ibcon#read 4, iclass 23, count 0 2006.252.08:15:40.36#ibcon#about to read 5, iclass 23, count 0 2006.252.08:15:40.36#ibcon#read 5, iclass 23, count 0 2006.252.08:15:40.36#ibcon#about to read 6, iclass 23, count 0 2006.252.08:15:40.36#ibcon#read 6, iclass 23, count 0 2006.252.08:15:40.36#ibcon#end of sib2, iclass 23, count 0 2006.252.08:15:40.36#ibcon#*after write, iclass 23, count 0 2006.252.08:15:40.36#ibcon#*before return 0, iclass 23, count 0 2006.252.08:15:40.36#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.252.08:15:40.36#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.252.08:15:40.36#ibcon#about to clear, iclass 23 cls_cnt 0 2006.252.08:15:40.36#ibcon#cleared, iclass 23 cls_cnt 0 2006.252.08:15:40.36$vc4f8/va=8,7 2006.252.08:15:40.36#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.252.08:15:40.36#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.252.08:15:40.36#ibcon#ireg 11 cls_cnt 2 2006.252.08:15:40.36#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.252.08:15:40.43#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.252.08:15:40.43#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.252.08:15:40.43#ibcon#enter wrdev, iclass 25, count 2 2006.252.08:15:40.43#ibcon#first serial, iclass 25, count 2 2006.252.08:15:40.43#ibcon#enter sib2, iclass 25, count 2 2006.252.08:15:40.43#ibcon#flushed, iclass 25, count 2 2006.252.08:15:40.43#ibcon#about to write, iclass 25, count 2 2006.252.08:15:40.43#ibcon#wrote, iclass 25, count 2 2006.252.08:15:40.43#ibcon#about to read 3, iclass 25, count 2 2006.252.08:15:40.44#ibcon#read 3, iclass 25, count 2 2006.252.08:15:40.44#ibcon#about to read 4, iclass 25, count 2 2006.252.08:15:40.44#ibcon#read 4, iclass 25, count 2 2006.252.08:15:40.44#ibcon#about to read 5, iclass 25, count 2 2006.252.08:15:40.44#ibcon#read 5, iclass 25, count 2 2006.252.08:15:40.44#ibcon#about to read 6, iclass 25, count 2 2006.252.08:15:40.44#ibcon#read 6, iclass 25, count 2 2006.252.08:15:40.44#ibcon#end of sib2, iclass 25, count 2 2006.252.08:15:40.44#ibcon#*mode == 0, iclass 25, count 2 2006.252.08:15:40.44#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.252.08:15:40.44#ibcon#[25=AT08-07\r\n] 2006.252.08:15:40.44#ibcon#*before write, iclass 25, count 2 2006.252.08:15:40.44#ibcon#enter sib2, iclass 25, count 2 2006.252.08:15:40.44#ibcon#flushed, iclass 25, count 2 2006.252.08:15:40.44#ibcon#about to write, iclass 25, count 2 2006.252.08:15:40.44#ibcon#wrote, iclass 25, count 2 2006.252.08:15:40.44#ibcon#about to read 3, iclass 25, count 2 2006.252.08:15:40.47#ibcon#read 3, iclass 25, count 2 2006.252.08:15:40.47#ibcon#about to read 4, iclass 25, count 2 2006.252.08:15:40.47#ibcon#read 4, iclass 25, count 2 2006.252.08:15:40.47#ibcon#about to read 5, iclass 25, count 2 2006.252.08:15:40.47#ibcon#read 5, iclass 25, count 2 2006.252.08:15:40.47#ibcon#about to read 6, iclass 25, count 2 2006.252.08:15:40.47#ibcon#read 6, iclass 25, count 2 2006.252.08:15:40.47#ibcon#end of sib2, iclass 25, count 2 2006.252.08:15:40.47#ibcon#*after write, iclass 25, count 2 2006.252.08:15:40.47#ibcon#*before return 0, iclass 25, count 2 2006.252.08:15:40.47#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.252.08:15:40.47#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.252.08:15:40.47#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.252.08:15:40.47#ibcon#ireg 7 cls_cnt 0 2006.252.08:15:40.47#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.252.08:15:40.59#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.252.08:15:40.59#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.252.08:15:40.59#ibcon#enter wrdev, iclass 25, count 0 2006.252.08:15:40.59#ibcon#first serial, iclass 25, count 0 2006.252.08:15:40.59#ibcon#enter sib2, iclass 25, count 0 2006.252.08:15:40.59#ibcon#flushed, iclass 25, count 0 2006.252.08:15:40.59#ibcon#about to write, iclass 25, count 0 2006.252.08:15:40.59#ibcon#wrote, iclass 25, count 0 2006.252.08:15:40.59#ibcon#about to read 3, iclass 25, count 0 2006.252.08:15:40.61#ibcon#read 3, iclass 25, count 0 2006.252.08:15:40.61#ibcon#about to read 4, iclass 25, count 0 2006.252.08:15:40.61#ibcon#read 4, iclass 25, count 0 2006.252.08:15:40.61#ibcon#about to read 5, iclass 25, count 0 2006.252.08:15:40.61#ibcon#read 5, iclass 25, count 0 2006.252.08:15:40.61#ibcon#about to read 6, iclass 25, count 0 2006.252.08:15:40.61#ibcon#read 6, iclass 25, count 0 2006.252.08:15:40.61#ibcon#end of sib2, iclass 25, count 0 2006.252.08:15:40.61#ibcon#*mode == 0, iclass 25, count 0 2006.252.08:15:40.61#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.252.08:15:40.61#ibcon#[25=USB\r\n] 2006.252.08:15:40.61#ibcon#*before write, iclass 25, count 0 2006.252.08:15:40.61#ibcon#enter sib2, iclass 25, count 0 2006.252.08:15:40.61#ibcon#flushed, iclass 25, count 0 2006.252.08:15:40.61#ibcon#about to write, iclass 25, count 0 2006.252.08:15:40.61#ibcon#wrote, iclass 25, count 0 2006.252.08:15:40.61#ibcon#about to read 3, iclass 25, count 0 2006.252.08:15:40.64#ibcon#read 3, iclass 25, count 0 2006.252.08:15:40.64#ibcon#about to read 4, iclass 25, count 0 2006.252.08:15:40.64#ibcon#read 4, iclass 25, count 0 2006.252.08:15:40.64#ibcon#about to read 5, iclass 25, count 0 2006.252.08:15:40.64#ibcon#read 5, iclass 25, count 0 2006.252.08:15:40.64#ibcon#about to read 6, iclass 25, count 0 2006.252.08:15:40.64#ibcon#read 6, iclass 25, count 0 2006.252.08:15:40.64#ibcon#end of sib2, iclass 25, count 0 2006.252.08:15:40.64#ibcon#*after write, iclass 25, count 0 2006.252.08:15:40.64#ibcon#*before return 0, iclass 25, count 0 2006.252.08:15:40.64#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.252.08:15:40.64#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.252.08:15:40.64#ibcon#about to clear, iclass 25 cls_cnt 0 2006.252.08:15:40.64#ibcon#cleared, iclass 25 cls_cnt 0 2006.252.08:15:40.64$vc4f8/vblo=1,632.99 2006.252.08:15:40.64#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.252.08:15:40.64#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.252.08:15:40.64#ibcon#ireg 17 cls_cnt 0 2006.252.08:15:40.64#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.252.08:15:40.64#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.252.08:15:40.64#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.252.08:15:40.64#ibcon#enter wrdev, iclass 27, count 0 2006.252.08:15:40.64#ibcon#first serial, iclass 27, count 0 2006.252.08:15:40.64#ibcon#enter sib2, iclass 27, count 0 2006.252.08:15:40.64#ibcon#flushed, iclass 27, count 0 2006.252.08:15:40.64#ibcon#about to write, iclass 27, count 0 2006.252.08:15:40.64#ibcon#wrote, iclass 27, count 0 2006.252.08:15:40.64#ibcon#about to read 3, iclass 27, count 0 2006.252.08:15:40.66#ibcon#read 3, iclass 27, count 0 2006.252.08:15:40.66#ibcon#about to read 4, iclass 27, count 0 2006.252.08:15:40.66#ibcon#read 4, iclass 27, count 0 2006.252.08:15:40.66#ibcon#about to read 5, iclass 27, count 0 2006.252.08:15:40.66#ibcon#read 5, iclass 27, count 0 2006.252.08:15:40.66#ibcon#about to read 6, iclass 27, count 0 2006.252.08:15:40.66#ibcon#read 6, iclass 27, count 0 2006.252.08:15:40.66#ibcon#end of sib2, iclass 27, count 0 2006.252.08:15:40.66#ibcon#*mode == 0, iclass 27, count 0 2006.252.08:15:40.66#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.252.08:15:40.66#ibcon#[28=FRQ=01,632.99\r\n] 2006.252.08:15:40.66#ibcon#*before write, iclass 27, count 0 2006.252.08:15:40.66#ibcon#enter sib2, iclass 27, count 0 2006.252.08:15:40.66#ibcon#flushed, iclass 27, count 0 2006.252.08:15:40.66#ibcon#about to write, iclass 27, count 0 2006.252.08:15:40.66#ibcon#wrote, iclass 27, count 0 2006.252.08:15:40.66#ibcon#about to read 3, iclass 27, count 0 2006.252.08:15:40.70#ibcon#read 3, iclass 27, count 0 2006.252.08:15:40.70#ibcon#about to read 4, iclass 27, count 0 2006.252.08:15:40.70#ibcon#read 4, iclass 27, count 0 2006.252.08:15:40.70#ibcon#about to read 5, iclass 27, count 0 2006.252.08:15:40.70#ibcon#read 5, iclass 27, count 0 2006.252.08:15:40.70#ibcon#about to read 6, iclass 27, count 0 2006.252.08:15:40.70#ibcon#read 6, iclass 27, count 0 2006.252.08:15:40.70#ibcon#end of sib2, iclass 27, count 0 2006.252.08:15:40.70#ibcon#*after write, iclass 27, count 0 2006.252.08:15:40.70#ibcon#*before return 0, iclass 27, count 0 2006.252.08:15:40.70#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.252.08:15:40.70#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.252.08:15:40.70#ibcon#about to clear, iclass 27 cls_cnt 0 2006.252.08:15:40.70#ibcon#cleared, iclass 27 cls_cnt 0 2006.252.08:15:40.70$vc4f8/vb=1,4 2006.252.08:15:40.70#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.252.08:15:40.70#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.252.08:15:40.70#ibcon#ireg 11 cls_cnt 2 2006.252.08:15:40.70#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.252.08:15:40.70#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.252.08:15:40.70#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.252.08:15:40.70#ibcon#enter wrdev, iclass 29, count 2 2006.252.08:15:40.70#ibcon#first serial, iclass 29, count 2 2006.252.08:15:40.70#ibcon#enter sib2, iclass 29, count 2 2006.252.08:15:40.70#ibcon#flushed, iclass 29, count 2 2006.252.08:15:40.70#ibcon#about to write, iclass 29, count 2 2006.252.08:15:40.71#ibcon#wrote, iclass 29, count 2 2006.252.08:15:40.71#ibcon#about to read 3, iclass 29, count 2 2006.252.08:15:40.72#ibcon#read 3, iclass 29, count 2 2006.252.08:15:40.72#ibcon#about to read 4, iclass 29, count 2 2006.252.08:15:40.72#ibcon#read 4, iclass 29, count 2 2006.252.08:15:40.72#ibcon#about to read 5, iclass 29, count 2 2006.252.08:15:40.72#ibcon#read 5, iclass 29, count 2 2006.252.08:15:40.72#ibcon#about to read 6, iclass 29, count 2 2006.252.08:15:40.72#ibcon#read 6, iclass 29, count 2 2006.252.08:15:40.72#ibcon#end of sib2, iclass 29, count 2 2006.252.08:15:40.72#ibcon#*mode == 0, iclass 29, count 2 2006.252.08:15:40.72#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.252.08:15:40.72#ibcon#[27=AT01-04\r\n] 2006.252.08:15:40.72#ibcon#*before write, iclass 29, count 2 2006.252.08:15:40.72#ibcon#enter sib2, iclass 29, count 2 2006.252.08:15:40.72#ibcon#flushed, iclass 29, count 2 2006.252.08:15:40.72#ibcon#about to write, iclass 29, count 2 2006.252.08:15:40.72#ibcon#wrote, iclass 29, count 2 2006.252.08:15:40.72#ibcon#about to read 3, iclass 29, count 2 2006.252.08:15:40.75#ibcon#read 3, iclass 29, count 2 2006.252.08:15:40.75#ibcon#about to read 4, iclass 29, count 2 2006.252.08:15:40.75#ibcon#read 4, iclass 29, count 2 2006.252.08:15:40.75#ibcon#about to read 5, iclass 29, count 2 2006.252.08:15:40.75#ibcon#read 5, iclass 29, count 2 2006.252.08:15:40.75#ibcon#about to read 6, iclass 29, count 2 2006.252.08:15:40.75#ibcon#read 6, iclass 29, count 2 2006.252.08:15:40.75#ibcon#end of sib2, iclass 29, count 2 2006.252.08:15:40.75#ibcon#*after write, iclass 29, count 2 2006.252.08:15:40.75#ibcon#*before return 0, iclass 29, count 2 2006.252.08:15:40.75#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.252.08:15:40.75#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.252.08:15:40.75#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.252.08:15:40.75#ibcon#ireg 7 cls_cnt 0 2006.252.08:15:40.75#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.252.08:15:40.87#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.252.08:15:40.87#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.252.08:15:40.87#ibcon#enter wrdev, iclass 29, count 0 2006.252.08:15:40.87#ibcon#first serial, iclass 29, count 0 2006.252.08:15:40.87#ibcon#enter sib2, iclass 29, count 0 2006.252.08:15:40.87#ibcon#flushed, iclass 29, count 0 2006.252.08:15:40.87#ibcon#about to write, iclass 29, count 0 2006.252.08:15:40.87#ibcon#wrote, iclass 29, count 0 2006.252.08:15:40.87#ibcon#about to read 3, iclass 29, count 0 2006.252.08:15:40.89#ibcon#read 3, iclass 29, count 0 2006.252.08:15:40.89#ibcon#about to read 4, iclass 29, count 0 2006.252.08:15:40.89#ibcon#read 4, iclass 29, count 0 2006.252.08:15:40.89#ibcon#about to read 5, iclass 29, count 0 2006.252.08:15:40.89#ibcon#read 5, iclass 29, count 0 2006.252.08:15:40.89#ibcon#about to read 6, iclass 29, count 0 2006.252.08:15:40.89#ibcon#read 6, iclass 29, count 0 2006.252.08:15:40.89#ibcon#end of sib2, iclass 29, count 0 2006.252.08:15:40.89#ibcon#*mode == 0, iclass 29, count 0 2006.252.08:15:40.89#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.252.08:15:40.89#ibcon#[27=USB\r\n] 2006.252.08:15:40.89#ibcon#*before write, iclass 29, count 0 2006.252.08:15:40.89#ibcon#enter sib2, iclass 29, count 0 2006.252.08:15:40.89#ibcon#flushed, iclass 29, count 0 2006.252.08:15:40.89#ibcon#about to write, iclass 29, count 0 2006.252.08:15:40.89#ibcon#wrote, iclass 29, count 0 2006.252.08:15:40.89#ibcon#about to read 3, iclass 29, count 0 2006.252.08:15:40.92#ibcon#read 3, iclass 29, count 0 2006.252.08:15:40.92#ibcon#about to read 4, iclass 29, count 0 2006.252.08:15:40.92#ibcon#read 4, iclass 29, count 0 2006.252.08:15:40.92#ibcon#about to read 5, iclass 29, count 0 2006.252.08:15:40.92#ibcon#read 5, iclass 29, count 0 2006.252.08:15:40.92#ibcon#about to read 6, iclass 29, count 0 2006.252.08:15:40.92#ibcon#read 6, iclass 29, count 0 2006.252.08:15:40.92#ibcon#end of sib2, iclass 29, count 0 2006.252.08:15:40.92#ibcon#*after write, iclass 29, count 0 2006.252.08:15:40.92#ibcon#*before return 0, iclass 29, count 0 2006.252.08:15:40.92#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.252.08:15:40.92#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.252.08:15:40.92#ibcon#about to clear, iclass 29 cls_cnt 0 2006.252.08:15:40.92#ibcon#cleared, iclass 29 cls_cnt 0 2006.252.08:15:40.92$vc4f8/vblo=2,640.99 2006.252.08:15:40.92#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.252.08:15:40.92#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.252.08:15:40.92#ibcon#ireg 17 cls_cnt 0 2006.252.08:15:40.92#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.252.08:15:40.92#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.252.08:15:40.92#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.252.08:15:40.92#ibcon#enter wrdev, iclass 31, count 0 2006.252.08:15:40.92#ibcon#first serial, iclass 31, count 0 2006.252.08:15:40.92#ibcon#enter sib2, iclass 31, count 0 2006.252.08:15:40.92#ibcon#flushed, iclass 31, count 0 2006.252.08:15:40.92#ibcon#about to write, iclass 31, count 0 2006.252.08:15:40.92#ibcon#wrote, iclass 31, count 0 2006.252.08:15:40.93#ibcon#about to read 3, iclass 31, count 0 2006.252.08:15:40.95#ibcon#read 3, iclass 31, count 0 2006.252.08:15:40.95#ibcon#about to read 4, iclass 31, count 0 2006.252.08:15:40.95#ibcon#read 4, iclass 31, count 0 2006.252.08:15:40.95#ibcon#about to read 5, iclass 31, count 0 2006.252.08:15:40.95#ibcon#read 5, iclass 31, count 0 2006.252.08:15:40.95#ibcon#about to read 6, iclass 31, count 0 2006.252.08:15:40.95#ibcon#read 6, iclass 31, count 0 2006.252.08:15:40.95#ibcon#end of sib2, iclass 31, count 0 2006.252.08:15:40.95#ibcon#*mode == 0, iclass 31, count 0 2006.252.08:15:40.95#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.252.08:15:40.95#ibcon#[28=FRQ=02,640.99\r\n] 2006.252.08:15:40.95#ibcon#*before write, iclass 31, count 0 2006.252.08:15:40.95#ibcon#enter sib2, iclass 31, count 0 2006.252.08:15:40.95#ibcon#flushed, iclass 31, count 0 2006.252.08:15:40.95#ibcon#about to write, iclass 31, count 0 2006.252.08:15:40.95#ibcon#wrote, iclass 31, count 0 2006.252.08:15:40.95#ibcon#about to read 3, iclass 31, count 0 2006.252.08:15:40.99#ibcon#read 3, iclass 31, count 0 2006.252.08:15:40.99#ibcon#about to read 4, iclass 31, count 0 2006.252.08:15:40.99#ibcon#read 4, iclass 31, count 0 2006.252.08:15:40.99#ibcon#about to read 5, iclass 31, count 0 2006.252.08:15:40.99#ibcon#read 5, iclass 31, count 0 2006.252.08:15:40.99#ibcon#about to read 6, iclass 31, count 0 2006.252.08:15:40.99#ibcon#read 6, iclass 31, count 0 2006.252.08:15:40.99#ibcon#end of sib2, iclass 31, count 0 2006.252.08:15:40.99#ibcon#*after write, iclass 31, count 0 2006.252.08:15:40.99#ibcon#*before return 0, iclass 31, count 0 2006.252.08:15:40.99#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.252.08:15:40.99#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.252.08:15:40.99#ibcon#about to clear, iclass 31 cls_cnt 0 2006.252.08:15:40.99#ibcon#cleared, iclass 31 cls_cnt 0 2006.252.08:15:40.99$vc4f8/vb=2,5 2006.252.08:15:40.99#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.252.08:15:40.99#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.252.08:15:40.99#ibcon#ireg 11 cls_cnt 2 2006.252.08:15:40.99#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.252.08:15:41.05#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.252.08:15:41.05#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.252.08:15:41.05#ibcon#enter wrdev, iclass 33, count 2 2006.252.08:15:41.05#ibcon#first serial, iclass 33, count 2 2006.252.08:15:41.05#ibcon#enter sib2, iclass 33, count 2 2006.252.08:15:41.05#ibcon#flushed, iclass 33, count 2 2006.252.08:15:41.05#ibcon#about to write, iclass 33, count 2 2006.252.08:15:41.05#ibcon#wrote, iclass 33, count 2 2006.252.08:15:41.05#ibcon#about to read 3, iclass 33, count 2 2006.252.08:15:41.06#ibcon#read 3, iclass 33, count 2 2006.252.08:15:41.06#ibcon#about to read 4, iclass 33, count 2 2006.252.08:15:41.06#ibcon#read 4, iclass 33, count 2 2006.252.08:15:41.06#ibcon#about to read 5, iclass 33, count 2 2006.252.08:15:41.06#ibcon#read 5, iclass 33, count 2 2006.252.08:15:41.06#ibcon#about to read 6, iclass 33, count 2 2006.252.08:15:41.06#ibcon#read 6, iclass 33, count 2 2006.252.08:15:41.06#ibcon#end of sib2, iclass 33, count 2 2006.252.08:15:41.06#ibcon#*mode == 0, iclass 33, count 2 2006.252.08:15:41.06#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.252.08:15:41.06#ibcon#[27=AT02-05\r\n] 2006.252.08:15:41.06#ibcon#*before write, iclass 33, count 2 2006.252.08:15:41.06#ibcon#enter sib2, iclass 33, count 2 2006.252.08:15:41.06#ibcon#flushed, iclass 33, count 2 2006.252.08:15:41.06#ibcon#about to write, iclass 33, count 2 2006.252.08:15:41.06#ibcon#wrote, iclass 33, count 2 2006.252.08:15:41.06#ibcon#about to read 3, iclass 33, count 2 2006.252.08:15:41.09#ibcon#read 3, iclass 33, count 2 2006.252.08:15:41.09#ibcon#about to read 4, iclass 33, count 2 2006.252.08:15:41.09#ibcon#read 4, iclass 33, count 2 2006.252.08:15:41.09#ibcon#about to read 5, iclass 33, count 2 2006.252.08:15:41.09#ibcon#read 5, iclass 33, count 2 2006.252.08:15:41.09#ibcon#about to read 6, iclass 33, count 2 2006.252.08:15:41.09#ibcon#read 6, iclass 33, count 2 2006.252.08:15:41.09#ibcon#end of sib2, iclass 33, count 2 2006.252.08:15:41.09#ibcon#*after write, iclass 33, count 2 2006.252.08:15:41.09#ibcon#*before return 0, iclass 33, count 2 2006.252.08:15:41.09#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.252.08:15:41.09#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.252.08:15:41.09#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.252.08:15:41.09#ibcon#ireg 7 cls_cnt 0 2006.252.08:15:41.09#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.252.08:15:41.21#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.252.08:15:41.21#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.252.08:15:41.21#ibcon#enter wrdev, iclass 33, count 0 2006.252.08:15:41.21#ibcon#first serial, iclass 33, count 0 2006.252.08:15:41.21#ibcon#enter sib2, iclass 33, count 0 2006.252.08:15:41.21#ibcon#flushed, iclass 33, count 0 2006.252.08:15:41.21#ibcon#about to write, iclass 33, count 0 2006.252.08:15:41.21#ibcon#wrote, iclass 33, count 0 2006.252.08:15:41.21#ibcon#about to read 3, iclass 33, count 0 2006.252.08:15:41.23#ibcon#read 3, iclass 33, count 0 2006.252.08:15:41.23#ibcon#about to read 4, iclass 33, count 0 2006.252.08:15:41.23#ibcon#read 4, iclass 33, count 0 2006.252.08:15:41.23#ibcon#about to read 5, iclass 33, count 0 2006.252.08:15:41.23#ibcon#read 5, iclass 33, count 0 2006.252.08:15:41.23#ibcon#about to read 6, iclass 33, count 0 2006.252.08:15:41.23#ibcon#read 6, iclass 33, count 0 2006.252.08:15:41.23#ibcon#end of sib2, iclass 33, count 0 2006.252.08:15:41.23#ibcon#*mode == 0, iclass 33, count 0 2006.252.08:15:41.23#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.252.08:15:41.23#ibcon#[27=USB\r\n] 2006.252.08:15:41.23#ibcon#*before write, iclass 33, count 0 2006.252.08:15:41.23#ibcon#enter sib2, iclass 33, count 0 2006.252.08:15:41.23#ibcon#flushed, iclass 33, count 0 2006.252.08:15:41.23#ibcon#about to write, iclass 33, count 0 2006.252.08:15:41.23#ibcon#wrote, iclass 33, count 0 2006.252.08:15:41.23#ibcon#about to read 3, iclass 33, count 0 2006.252.08:15:41.26#ibcon#read 3, iclass 33, count 0 2006.252.08:15:41.26#ibcon#about to read 4, iclass 33, count 0 2006.252.08:15:41.26#ibcon#read 4, iclass 33, count 0 2006.252.08:15:41.26#ibcon#about to read 5, iclass 33, count 0 2006.252.08:15:41.26#ibcon#read 5, iclass 33, count 0 2006.252.08:15:41.26#ibcon#about to read 6, iclass 33, count 0 2006.252.08:15:41.26#ibcon#read 6, iclass 33, count 0 2006.252.08:15:41.26#ibcon#end of sib2, iclass 33, count 0 2006.252.08:15:41.26#ibcon#*after write, iclass 33, count 0 2006.252.08:15:41.26#ibcon#*before return 0, iclass 33, count 0 2006.252.08:15:41.26#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.252.08:15:41.26#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.252.08:15:41.26#ibcon#about to clear, iclass 33 cls_cnt 0 2006.252.08:15:41.26#ibcon#cleared, iclass 33 cls_cnt 0 2006.252.08:15:41.26$vc4f8/vblo=3,656.99 2006.252.08:15:41.26#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.252.08:15:41.26#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.252.08:15:41.26#ibcon#ireg 17 cls_cnt 0 2006.252.08:15:41.26#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.252.08:15:41.26#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.252.08:15:41.26#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.252.08:15:41.26#ibcon#enter wrdev, iclass 35, count 0 2006.252.08:15:41.26#ibcon#first serial, iclass 35, count 0 2006.252.08:15:41.26#ibcon#enter sib2, iclass 35, count 0 2006.252.08:15:41.26#ibcon#flushed, iclass 35, count 0 2006.252.08:15:41.26#ibcon#about to write, iclass 35, count 0 2006.252.08:15:41.26#ibcon#wrote, iclass 35, count 0 2006.252.08:15:41.26#ibcon#about to read 3, iclass 35, count 0 2006.252.08:15:41.28#ibcon#read 3, iclass 35, count 0 2006.252.08:15:41.28#ibcon#about to read 4, iclass 35, count 0 2006.252.08:15:41.28#ibcon#read 4, iclass 35, count 0 2006.252.08:15:41.28#ibcon#about to read 5, iclass 35, count 0 2006.252.08:15:41.28#ibcon#read 5, iclass 35, count 0 2006.252.08:15:41.28#ibcon#about to read 6, iclass 35, count 0 2006.252.08:15:41.28#ibcon#read 6, iclass 35, count 0 2006.252.08:15:41.28#ibcon#end of sib2, iclass 35, count 0 2006.252.08:15:41.28#ibcon#*mode == 0, iclass 35, count 0 2006.252.08:15:41.28#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.252.08:15:41.28#ibcon#[28=FRQ=03,656.99\r\n] 2006.252.08:15:41.28#ibcon#*before write, iclass 35, count 0 2006.252.08:15:41.28#ibcon#enter sib2, iclass 35, count 0 2006.252.08:15:41.28#ibcon#flushed, iclass 35, count 0 2006.252.08:15:41.28#ibcon#about to write, iclass 35, count 0 2006.252.08:15:41.28#ibcon#wrote, iclass 35, count 0 2006.252.08:15:41.28#ibcon#about to read 3, iclass 35, count 0 2006.252.08:15:41.32#ibcon#read 3, iclass 35, count 0 2006.252.08:15:41.32#ibcon#about to read 4, iclass 35, count 0 2006.252.08:15:41.32#ibcon#read 4, iclass 35, count 0 2006.252.08:15:41.32#ibcon#about to read 5, iclass 35, count 0 2006.252.08:15:41.32#ibcon#read 5, iclass 35, count 0 2006.252.08:15:41.32#ibcon#about to read 6, iclass 35, count 0 2006.252.08:15:41.32#ibcon#read 6, iclass 35, count 0 2006.252.08:15:41.32#ibcon#end of sib2, iclass 35, count 0 2006.252.08:15:41.32#ibcon#*after write, iclass 35, count 0 2006.252.08:15:41.32#ibcon#*before return 0, iclass 35, count 0 2006.252.08:15:41.32#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.252.08:15:41.32#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.252.08:15:41.32#ibcon#about to clear, iclass 35 cls_cnt 0 2006.252.08:15:41.32#ibcon#cleared, iclass 35 cls_cnt 0 2006.252.08:15:41.32$vc4f8/vb=3,4 2006.252.08:15:41.32#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.252.08:15:41.32#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.252.08:15:41.32#ibcon#ireg 11 cls_cnt 2 2006.252.08:15:41.32#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.252.08:15:41.38#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.252.08:15:41.38#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.252.08:15:41.38#ibcon#enter wrdev, iclass 37, count 2 2006.252.08:15:41.38#ibcon#first serial, iclass 37, count 2 2006.252.08:15:41.38#ibcon#enter sib2, iclass 37, count 2 2006.252.08:15:41.38#ibcon#flushed, iclass 37, count 2 2006.252.08:15:41.38#ibcon#about to write, iclass 37, count 2 2006.252.08:15:41.38#ibcon#wrote, iclass 37, count 2 2006.252.08:15:41.38#ibcon#about to read 3, iclass 37, count 2 2006.252.08:15:41.40#ibcon#read 3, iclass 37, count 2 2006.252.08:15:41.40#ibcon#about to read 4, iclass 37, count 2 2006.252.08:15:41.40#ibcon#read 4, iclass 37, count 2 2006.252.08:15:41.40#ibcon#about to read 5, iclass 37, count 2 2006.252.08:15:41.40#ibcon#read 5, iclass 37, count 2 2006.252.08:15:41.40#ibcon#about to read 6, iclass 37, count 2 2006.252.08:15:41.40#ibcon#read 6, iclass 37, count 2 2006.252.08:15:41.40#ibcon#end of sib2, iclass 37, count 2 2006.252.08:15:41.40#ibcon#*mode == 0, iclass 37, count 2 2006.252.08:15:41.40#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.252.08:15:41.40#ibcon#[27=AT03-04\r\n] 2006.252.08:15:41.40#ibcon#*before write, iclass 37, count 2 2006.252.08:15:41.40#ibcon#enter sib2, iclass 37, count 2 2006.252.08:15:41.40#ibcon#flushed, iclass 37, count 2 2006.252.08:15:41.40#ibcon#about to write, iclass 37, count 2 2006.252.08:15:41.40#ibcon#wrote, iclass 37, count 2 2006.252.08:15:41.40#ibcon#about to read 3, iclass 37, count 2 2006.252.08:15:41.43#ibcon#read 3, iclass 37, count 2 2006.252.08:15:41.43#ibcon#about to read 4, iclass 37, count 2 2006.252.08:15:41.43#ibcon#read 4, iclass 37, count 2 2006.252.08:15:41.43#ibcon#about to read 5, iclass 37, count 2 2006.252.08:15:41.43#ibcon#read 5, iclass 37, count 2 2006.252.08:15:41.43#ibcon#about to read 6, iclass 37, count 2 2006.252.08:15:41.43#ibcon#read 6, iclass 37, count 2 2006.252.08:15:41.43#ibcon#end of sib2, iclass 37, count 2 2006.252.08:15:41.43#ibcon#*after write, iclass 37, count 2 2006.252.08:15:41.43#ibcon#*before return 0, iclass 37, count 2 2006.252.08:15:41.43#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.252.08:15:41.43#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.252.08:15:41.43#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.252.08:15:41.43#ibcon#ireg 7 cls_cnt 0 2006.252.08:15:41.43#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.252.08:15:41.55#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.252.08:15:41.55#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.252.08:15:41.55#ibcon#enter wrdev, iclass 37, count 0 2006.252.08:15:41.55#ibcon#first serial, iclass 37, count 0 2006.252.08:15:41.55#ibcon#enter sib2, iclass 37, count 0 2006.252.08:15:41.55#ibcon#flushed, iclass 37, count 0 2006.252.08:15:41.55#ibcon#about to write, iclass 37, count 0 2006.252.08:15:41.55#ibcon#wrote, iclass 37, count 0 2006.252.08:15:41.55#ibcon#about to read 3, iclass 37, count 0 2006.252.08:15:41.57#ibcon#read 3, iclass 37, count 0 2006.252.08:15:41.57#ibcon#about to read 4, iclass 37, count 0 2006.252.08:15:41.57#ibcon#read 4, iclass 37, count 0 2006.252.08:15:41.57#ibcon#about to read 5, iclass 37, count 0 2006.252.08:15:41.57#ibcon#read 5, iclass 37, count 0 2006.252.08:15:41.57#ibcon#about to read 6, iclass 37, count 0 2006.252.08:15:41.57#ibcon#read 6, iclass 37, count 0 2006.252.08:15:41.57#ibcon#end of sib2, iclass 37, count 0 2006.252.08:15:41.57#ibcon#*mode == 0, iclass 37, count 0 2006.252.08:15:41.57#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.252.08:15:41.57#ibcon#[27=USB\r\n] 2006.252.08:15:41.57#ibcon#*before write, iclass 37, count 0 2006.252.08:15:41.57#ibcon#enter sib2, iclass 37, count 0 2006.252.08:15:41.57#ibcon#flushed, iclass 37, count 0 2006.252.08:15:41.57#ibcon#about to write, iclass 37, count 0 2006.252.08:15:41.57#ibcon#wrote, iclass 37, count 0 2006.252.08:15:41.57#ibcon#about to read 3, iclass 37, count 0 2006.252.08:15:41.60#ibcon#read 3, iclass 37, count 0 2006.252.08:15:41.60#ibcon#about to read 4, iclass 37, count 0 2006.252.08:15:41.60#ibcon#read 4, iclass 37, count 0 2006.252.08:15:41.60#ibcon#about to read 5, iclass 37, count 0 2006.252.08:15:41.60#ibcon#read 5, iclass 37, count 0 2006.252.08:15:41.60#ibcon#about to read 6, iclass 37, count 0 2006.252.08:15:41.60#ibcon#read 6, iclass 37, count 0 2006.252.08:15:41.60#ibcon#end of sib2, iclass 37, count 0 2006.252.08:15:41.60#ibcon#*after write, iclass 37, count 0 2006.252.08:15:41.60#ibcon#*before return 0, iclass 37, count 0 2006.252.08:15:41.60#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.252.08:15:41.60#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.252.08:15:41.60#ibcon#about to clear, iclass 37 cls_cnt 0 2006.252.08:15:41.60#ibcon#cleared, iclass 37 cls_cnt 0 2006.252.08:15:41.60$vc4f8/vblo=4,712.99 2006.252.08:15:41.60#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.252.08:15:41.60#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.252.08:15:41.60#ibcon#ireg 17 cls_cnt 0 2006.252.08:15:41.60#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.252.08:15:41.60#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.252.08:15:41.60#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.252.08:15:41.60#ibcon#enter wrdev, iclass 39, count 0 2006.252.08:15:41.60#ibcon#first serial, iclass 39, count 0 2006.252.08:15:41.60#ibcon#enter sib2, iclass 39, count 0 2006.252.08:15:41.60#ibcon#flushed, iclass 39, count 0 2006.252.08:15:41.60#ibcon#about to write, iclass 39, count 0 2006.252.08:15:41.60#ibcon#wrote, iclass 39, count 0 2006.252.08:15:41.60#ibcon#about to read 3, iclass 39, count 0 2006.252.08:15:41.62#ibcon#read 3, iclass 39, count 0 2006.252.08:15:41.62#ibcon#about to read 4, iclass 39, count 0 2006.252.08:15:41.62#ibcon#read 4, iclass 39, count 0 2006.252.08:15:41.62#ibcon#about to read 5, iclass 39, count 0 2006.252.08:15:41.62#ibcon#read 5, iclass 39, count 0 2006.252.08:15:41.62#ibcon#about to read 6, iclass 39, count 0 2006.252.08:15:41.62#ibcon#read 6, iclass 39, count 0 2006.252.08:15:41.62#ibcon#end of sib2, iclass 39, count 0 2006.252.08:15:41.62#ibcon#*mode == 0, iclass 39, count 0 2006.252.08:15:41.62#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.252.08:15:41.62#ibcon#[28=FRQ=04,712.99\r\n] 2006.252.08:15:41.62#ibcon#*before write, iclass 39, count 0 2006.252.08:15:41.62#ibcon#enter sib2, iclass 39, count 0 2006.252.08:15:41.62#ibcon#flushed, iclass 39, count 0 2006.252.08:15:41.62#ibcon#about to write, iclass 39, count 0 2006.252.08:15:41.62#ibcon#wrote, iclass 39, count 0 2006.252.08:15:41.62#ibcon#about to read 3, iclass 39, count 0 2006.252.08:15:41.66#ibcon#read 3, iclass 39, count 0 2006.252.08:15:41.66#ibcon#about to read 4, iclass 39, count 0 2006.252.08:15:41.66#ibcon#read 4, iclass 39, count 0 2006.252.08:15:41.66#ibcon#about to read 5, iclass 39, count 0 2006.252.08:15:41.66#ibcon#read 5, iclass 39, count 0 2006.252.08:15:41.66#ibcon#about to read 6, iclass 39, count 0 2006.252.08:15:41.66#ibcon#read 6, iclass 39, count 0 2006.252.08:15:41.66#ibcon#end of sib2, iclass 39, count 0 2006.252.08:15:41.66#ibcon#*after write, iclass 39, count 0 2006.252.08:15:41.66#ibcon#*before return 0, iclass 39, count 0 2006.252.08:15:41.66#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.252.08:15:41.66#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.252.08:15:41.66#ibcon#about to clear, iclass 39 cls_cnt 0 2006.252.08:15:41.66#ibcon#cleared, iclass 39 cls_cnt 0 2006.252.08:15:41.66$vc4f8/vb=4,4 2006.252.08:15:41.66#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.252.08:15:41.66#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.252.08:15:41.66#ibcon#ireg 11 cls_cnt 2 2006.252.08:15:41.66#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.252.08:15:41.73#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.252.08:15:41.73#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.252.08:15:41.73#ibcon#enter wrdev, iclass 3, count 2 2006.252.08:15:41.73#ibcon#first serial, iclass 3, count 2 2006.252.08:15:41.73#ibcon#enter sib2, iclass 3, count 2 2006.252.08:15:41.73#ibcon#flushed, iclass 3, count 2 2006.252.08:15:41.73#ibcon#about to write, iclass 3, count 2 2006.252.08:15:41.73#ibcon#wrote, iclass 3, count 2 2006.252.08:15:41.73#ibcon#about to read 3, iclass 3, count 2 2006.252.08:15:41.74#ibcon#read 3, iclass 3, count 2 2006.252.08:15:41.74#ibcon#about to read 4, iclass 3, count 2 2006.252.08:15:41.74#ibcon#read 4, iclass 3, count 2 2006.252.08:15:41.74#ibcon#about to read 5, iclass 3, count 2 2006.252.08:15:41.74#ibcon#read 5, iclass 3, count 2 2006.252.08:15:41.74#ibcon#about to read 6, iclass 3, count 2 2006.252.08:15:41.74#ibcon#read 6, iclass 3, count 2 2006.252.08:15:41.74#ibcon#end of sib2, iclass 3, count 2 2006.252.08:15:41.74#ibcon#*mode == 0, iclass 3, count 2 2006.252.08:15:41.74#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.252.08:15:41.74#ibcon#[27=AT04-04\r\n] 2006.252.08:15:41.74#ibcon#*before write, iclass 3, count 2 2006.252.08:15:41.75#ibcon#enter sib2, iclass 3, count 2 2006.252.08:15:41.75#ibcon#flushed, iclass 3, count 2 2006.252.08:15:41.75#ibcon#about to write, iclass 3, count 2 2006.252.08:15:41.75#ibcon#wrote, iclass 3, count 2 2006.252.08:15:41.75#ibcon#about to read 3, iclass 3, count 2 2006.252.08:15:41.77#ibcon#read 3, iclass 3, count 2 2006.252.08:15:41.77#ibcon#about to read 4, iclass 3, count 2 2006.252.08:15:41.77#ibcon#read 4, iclass 3, count 2 2006.252.08:15:41.77#ibcon#about to read 5, iclass 3, count 2 2006.252.08:15:41.77#ibcon#read 5, iclass 3, count 2 2006.252.08:15:41.77#ibcon#about to read 6, iclass 3, count 2 2006.252.08:15:41.77#ibcon#read 6, iclass 3, count 2 2006.252.08:15:41.77#ibcon#end of sib2, iclass 3, count 2 2006.252.08:15:41.77#ibcon#*after write, iclass 3, count 2 2006.252.08:15:41.77#ibcon#*before return 0, iclass 3, count 2 2006.252.08:15:41.77#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.252.08:15:41.77#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.252.08:15:41.77#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.252.08:15:41.77#ibcon#ireg 7 cls_cnt 0 2006.252.08:15:41.77#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.252.08:15:41.89#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.252.08:15:41.89#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.252.08:15:41.89#ibcon#enter wrdev, iclass 3, count 0 2006.252.08:15:41.89#ibcon#first serial, iclass 3, count 0 2006.252.08:15:41.89#ibcon#enter sib2, iclass 3, count 0 2006.252.08:15:41.89#ibcon#flushed, iclass 3, count 0 2006.252.08:15:41.89#ibcon#about to write, iclass 3, count 0 2006.252.08:15:41.89#ibcon#wrote, iclass 3, count 0 2006.252.08:15:41.89#ibcon#about to read 3, iclass 3, count 0 2006.252.08:15:41.91#ibcon#read 3, iclass 3, count 0 2006.252.08:15:41.91#ibcon#about to read 4, iclass 3, count 0 2006.252.08:15:41.91#ibcon#read 4, iclass 3, count 0 2006.252.08:15:41.91#ibcon#about to read 5, iclass 3, count 0 2006.252.08:15:41.91#ibcon#read 5, iclass 3, count 0 2006.252.08:15:41.91#ibcon#about to read 6, iclass 3, count 0 2006.252.08:15:41.91#ibcon#read 6, iclass 3, count 0 2006.252.08:15:41.91#ibcon#end of sib2, iclass 3, count 0 2006.252.08:15:41.91#ibcon#*mode == 0, iclass 3, count 0 2006.252.08:15:41.91#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.252.08:15:41.91#ibcon#[27=USB\r\n] 2006.252.08:15:41.91#ibcon#*before write, iclass 3, count 0 2006.252.08:15:41.91#ibcon#enter sib2, iclass 3, count 0 2006.252.08:15:41.91#ibcon#flushed, iclass 3, count 0 2006.252.08:15:41.91#ibcon#about to write, iclass 3, count 0 2006.252.08:15:41.91#ibcon#wrote, iclass 3, count 0 2006.252.08:15:41.91#ibcon#about to read 3, iclass 3, count 0 2006.252.08:15:41.94#ibcon#read 3, iclass 3, count 0 2006.252.08:15:41.94#ibcon#about to read 4, iclass 3, count 0 2006.252.08:15:41.94#ibcon#read 4, iclass 3, count 0 2006.252.08:15:41.94#ibcon#about to read 5, iclass 3, count 0 2006.252.08:15:41.94#ibcon#read 5, iclass 3, count 0 2006.252.08:15:41.94#ibcon#about to read 6, iclass 3, count 0 2006.252.08:15:41.94#ibcon#read 6, iclass 3, count 0 2006.252.08:15:41.94#ibcon#end of sib2, iclass 3, count 0 2006.252.08:15:41.94#ibcon#*after write, iclass 3, count 0 2006.252.08:15:41.94#ibcon#*before return 0, iclass 3, count 0 2006.252.08:15:41.94#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.252.08:15:41.94#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.252.08:15:41.94#ibcon#about to clear, iclass 3 cls_cnt 0 2006.252.08:15:41.94#ibcon#cleared, iclass 3 cls_cnt 0 2006.252.08:15:41.94$vc4f8/vblo=5,744.99 2006.252.08:15:41.94#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.252.08:15:41.94#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.252.08:15:41.94#ibcon#ireg 17 cls_cnt 0 2006.252.08:15:41.94#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.252.08:15:41.94#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.252.08:15:41.94#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.252.08:15:41.94#ibcon#enter wrdev, iclass 5, count 0 2006.252.08:15:41.94#ibcon#first serial, iclass 5, count 0 2006.252.08:15:41.94#ibcon#enter sib2, iclass 5, count 0 2006.252.08:15:41.94#ibcon#flushed, iclass 5, count 0 2006.252.08:15:41.94#ibcon#about to write, iclass 5, count 0 2006.252.08:15:41.94#ibcon#wrote, iclass 5, count 0 2006.252.08:15:41.94#ibcon#about to read 3, iclass 5, count 0 2006.252.08:15:41.96#ibcon#read 3, iclass 5, count 0 2006.252.08:15:41.96#ibcon#about to read 4, iclass 5, count 0 2006.252.08:15:41.96#ibcon#read 4, iclass 5, count 0 2006.252.08:15:41.96#ibcon#about to read 5, iclass 5, count 0 2006.252.08:15:41.96#ibcon#read 5, iclass 5, count 0 2006.252.08:15:41.96#ibcon#about to read 6, iclass 5, count 0 2006.252.08:15:41.96#ibcon#read 6, iclass 5, count 0 2006.252.08:15:41.96#ibcon#end of sib2, iclass 5, count 0 2006.252.08:15:41.96#ibcon#*mode == 0, iclass 5, count 0 2006.252.08:15:41.96#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.252.08:15:41.96#ibcon#[28=FRQ=05,744.99\r\n] 2006.252.08:15:41.96#ibcon#*before write, iclass 5, count 0 2006.252.08:15:41.96#ibcon#enter sib2, iclass 5, count 0 2006.252.08:15:41.96#ibcon#flushed, iclass 5, count 0 2006.252.08:15:41.96#ibcon#about to write, iclass 5, count 0 2006.252.08:15:41.96#ibcon#wrote, iclass 5, count 0 2006.252.08:15:41.96#ibcon#about to read 3, iclass 5, count 0 2006.252.08:15:42.00#ibcon#read 3, iclass 5, count 0 2006.252.08:15:42.00#ibcon#about to read 4, iclass 5, count 0 2006.252.08:15:42.00#ibcon#read 4, iclass 5, count 0 2006.252.08:15:42.00#ibcon#about to read 5, iclass 5, count 0 2006.252.08:15:42.00#ibcon#read 5, iclass 5, count 0 2006.252.08:15:42.00#ibcon#about to read 6, iclass 5, count 0 2006.252.08:15:42.00#ibcon#read 6, iclass 5, count 0 2006.252.08:15:42.00#ibcon#end of sib2, iclass 5, count 0 2006.252.08:15:42.00#ibcon#*after write, iclass 5, count 0 2006.252.08:15:42.00#ibcon#*before return 0, iclass 5, count 0 2006.252.08:15:42.00#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.252.08:15:42.00#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.252.08:15:42.00#ibcon#about to clear, iclass 5 cls_cnt 0 2006.252.08:15:42.00#ibcon#cleared, iclass 5 cls_cnt 0 2006.252.08:15:42.00$vc4f8/vb=5,4 2006.252.08:15:42.00#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.252.08:15:42.00#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.252.08:15:42.00#ibcon#ireg 11 cls_cnt 2 2006.252.08:15:42.00#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.252.08:15:42.06#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.252.08:15:42.06#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.252.08:15:42.06#ibcon#enter wrdev, iclass 7, count 2 2006.252.08:15:42.06#ibcon#first serial, iclass 7, count 2 2006.252.08:15:42.06#ibcon#enter sib2, iclass 7, count 2 2006.252.08:15:42.06#ibcon#flushed, iclass 7, count 2 2006.252.08:15:42.06#ibcon#about to write, iclass 7, count 2 2006.252.08:15:42.06#ibcon#wrote, iclass 7, count 2 2006.252.08:15:42.06#ibcon#about to read 3, iclass 7, count 2 2006.252.08:15:42.08#ibcon#read 3, iclass 7, count 2 2006.252.08:15:42.08#ibcon#about to read 4, iclass 7, count 2 2006.252.08:15:42.08#ibcon#read 4, iclass 7, count 2 2006.252.08:15:42.08#ibcon#about to read 5, iclass 7, count 2 2006.252.08:15:42.08#ibcon#read 5, iclass 7, count 2 2006.252.08:15:42.08#ibcon#about to read 6, iclass 7, count 2 2006.252.08:15:42.08#ibcon#read 6, iclass 7, count 2 2006.252.08:15:42.08#ibcon#end of sib2, iclass 7, count 2 2006.252.08:15:42.08#ibcon#*mode == 0, iclass 7, count 2 2006.252.08:15:42.08#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.252.08:15:42.08#ibcon#[27=AT05-04\r\n] 2006.252.08:15:42.08#ibcon#*before write, iclass 7, count 2 2006.252.08:15:42.08#ibcon#enter sib2, iclass 7, count 2 2006.252.08:15:42.08#ibcon#flushed, iclass 7, count 2 2006.252.08:15:42.08#ibcon#about to write, iclass 7, count 2 2006.252.08:15:42.08#ibcon#wrote, iclass 7, count 2 2006.252.08:15:42.08#ibcon#about to read 3, iclass 7, count 2 2006.252.08:15:42.11#ibcon#read 3, iclass 7, count 2 2006.252.08:15:42.11#ibcon#about to read 4, iclass 7, count 2 2006.252.08:15:42.11#ibcon#read 4, iclass 7, count 2 2006.252.08:15:42.11#ibcon#about to read 5, iclass 7, count 2 2006.252.08:15:42.11#ibcon#read 5, iclass 7, count 2 2006.252.08:15:42.11#ibcon#about to read 6, iclass 7, count 2 2006.252.08:15:42.11#ibcon#read 6, iclass 7, count 2 2006.252.08:15:42.11#ibcon#end of sib2, iclass 7, count 2 2006.252.08:15:42.11#ibcon#*after write, iclass 7, count 2 2006.252.08:15:42.11#ibcon#*before return 0, iclass 7, count 2 2006.252.08:15:42.11#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.252.08:15:42.11#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.252.08:15:42.11#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.252.08:15:42.11#ibcon#ireg 7 cls_cnt 0 2006.252.08:15:42.11#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.252.08:15:42.23#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.252.08:15:42.23#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.252.08:15:42.23#ibcon#enter wrdev, iclass 7, count 0 2006.252.08:15:42.23#ibcon#first serial, iclass 7, count 0 2006.252.08:15:42.23#ibcon#enter sib2, iclass 7, count 0 2006.252.08:15:42.23#ibcon#flushed, iclass 7, count 0 2006.252.08:15:42.23#ibcon#about to write, iclass 7, count 0 2006.252.08:15:42.23#ibcon#wrote, iclass 7, count 0 2006.252.08:15:42.23#ibcon#about to read 3, iclass 7, count 0 2006.252.08:15:42.25#ibcon#read 3, iclass 7, count 0 2006.252.08:15:42.25#ibcon#about to read 4, iclass 7, count 0 2006.252.08:15:42.25#ibcon#read 4, iclass 7, count 0 2006.252.08:15:42.25#ibcon#about to read 5, iclass 7, count 0 2006.252.08:15:42.25#ibcon#read 5, iclass 7, count 0 2006.252.08:15:42.25#ibcon#about to read 6, iclass 7, count 0 2006.252.08:15:42.25#ibcon#read 6, iclass 7, count 0 2006.252.08:15:42.25#ibcon#end of sib2, iclass 7, count 0 2006.252.08:15:42.25#ibcon#*mode == 0, iclass 7, count 0 2006.252.08:15:42.25#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.252.08:15:42.25#ibcon#[27=USB\r\n] 2006.252.08:15:42.25#ibcon#*before write, iclass 7, count 0 2006.252.08:15:42.25#ibcon#enter sib2, iclass 7, count 0 2006.252.08:15:42.25#ibcon#flushed, iclass 7, count 0 2006.252.08:15:42.25#ibcon#about to write, iclass 7, count 0 2006.252.08:15:42.25#ibcon#wrote, iclass 7, count 0 2006.252.08:15:42.25#ibcon#about to read 3, iclass 7, count 0 2006.252.08:15:42.28#ibcon#read 3, iclass 7, count 0 2006.252.08:15:42.28#ibcon#about to read 4, iclass 7, count 0 2006.252.08:15:42.28#ibcon#read 4, iclass 7, count 0 2006.252.08:15:42.28#ibcon#about to read 5, iclass 7, count 0 2006.252.08:15:42.28#ibcon#read 5, iclass 7, count 0 2006.252.08:15:42.28#ibcon#about to read 6, iclass 7, count 0 2006.252.08:15:42.28#ibcon#read 6, iclass 7, count 0 2006.252.08:15:42.28#ibcon#end of sib2, iclass 7, count 0 2006.252.08:15:42.28#ibcon#*after write, iclass 7, count 0 2006.252.08:15:42.28#ibcon#*before return 0, iclass 7, count 0 2006.252.08:15:42.28#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.252.08:15:42.28#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.252.08:15:42.28#ibcon#about to clear, iclass 7 cls_cnt 0 2006.252.08:15:42.28#ibcon#cleared, iclass 7 cls_cnt 0 2006.252.08:15:42.28$vc4f8/vblo=6,752.99 2006.252.08:15:42.28#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.252.08:15:42.28#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.252.08:15:42.28#ibcon#ireg 17 cls_cnt 0 2006.252.08:15:42.28#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.252.08:15:42.28#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.252.08:15:42.28#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.252.08:15:42.28#ibcon#enter wrdev, iclass 12, count 0 2006.252.08:15:42.28#ibcon#first serial, iclass 12, count 0 2006.252.08:15:42.28#ibcon#enter sib2, iclass 12, count 0 2006.252.08:15:42.28#ibcon#flushed, iclass 12, count 0 2006.252.08:15:42.28#ibcon#about to write, iclass 12, count 0 2006.252.08:15:42.29#ibcon#wrote, iclass 12, count 0 2006.252.08:15:42.29#ibcon#about to read 3, iclass 12, count 0 2006.252.08:15:42.30#ibcon#read 3, iclass 12, count 0 2006.252.08:15:42.30#ibcon#about to read 4, iclass 12, count 0 2006.252.08:15:42.30#ibcon#read 4, iclass 12, count 0 2006.252.08:15:42.30#ibcon#about to read 5, iclass 12, count 0 2006.252.08:15:42.30#ibcon#read 5, iclass 12, count 0 2006.252.08:15:42.30#ibcon#about to read 6, iclass 12, count 0 2006.252.08:15:42.30#ibcon#read 6, iclass 12, count 0 2006.252.08:15:42.30#ibcon#end of sib2, iclass 12, count 0 2006.252.08:15:42.30#ibcon#*mode == 0, iclass 12, count 0 2006.252.08:15:42.30#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.252.08:15:42.30#ibcon#[28=FRQ=06,752.99\r\n] 2006.252.08:15:42.30#ibcon#*before write, iclass 12, count 0 2006.252.08:15:42.30#ibcon#enter sib2, iclass 12, count 0 2006.252.08:15:42.30#ibcon#flushed, iclass 12, count 0 2006.252.08:15:42.30#ibcon#about to write, iclass 12, count 0 2006.252.08:15:42.30#ibcon#wrote, iclass 12, count 0 2006.252.08:15:42.30#ibcon#about to read 3, iclass 12, count 0 2006.252.08:15:42.32#abcon#<5=/05 3.3 6.3 27.28 901011.1\r\n> 2006.252.08:15:42.34#abcon#{5=INTERFACE CLEAR} 2006.252.08:15:42.34#ibcon#read 3, iclass 12, count 0 2006.252.08:15:42.34#ibcon#about to read 4, iclass 12, count 0 2006.252.08:15:42.34#ibcon#read 4, iclass 12, count 0 2006.252.08:15:42.34#ibcon#about to read 5, iclass 12, count 0 2006.252.08:15:42.34#ibcon#read 5, iclass 12, count 0 2006.252.08:15:42.34#ibcon#about to read 6, iclass 12, count 0 2006.252.08:15:42.34#ibcon#read 6, iclass 12, count 0 2006.252.08:15:42.34#ibcon#end of sib2, iclass 12, count 0 2006.252.08:15:42.34#ibcon#*after write, iclass 12, count 0 2006.252.08:15:42.34#ibcon#*before return 0, iclass 12, count 0 2006.252.08:15:42.34#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.252.08:15:42.34#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.252.08:15:42.34#ibcon#about to clear, iclass 12 cls_cnt 0 2006.252.08:15:42.34#ibcon#cleared, iclass 12 cls_cnt 0 2006.252.08:15:42.35$vc4f8/vb=6,4 2006.252.08:15:42.35#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.252.08:15:42.35#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.252.08:15:42.35#ibcon#ireg 11 cls_cnt 2 2006.252.08:15:42.35#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.252.08:15:42.40#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.252.08:15:42.40#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.252.08:15:42.40#ibcon#enter wrdev, iclass 16, count 2 2006.252.08:15:42.40#ibcon#first serial, iclass 16, count 2 2006.252.08:15:42.40#ibcon#enter sib2, iclass 16, count 2 2006.252.08:15:42.40#ibcon#flushed, iclass 16, count 2 2006.252.08:15:42.40#ibcon#about to write, iclass 16, count 2 2006.252.08:15:42.40#ibcon#wrote, iclass 16, count 2 2006.252.08:15:42.40#ibcon#about to read 3, iclass 16, count 2 2006.252.08:15:42.40#abcon#[5=S1D000X0/0*\r\n] 2006.252.08:15:42.41#ibcon#read 3, iclass 16, count 2 2006.252.08:15:42.41#ibcon#about to read 4, iclass 16, count 2 2006.252.08:15:42.41#ibcon#read 4, iclass 16, count 2 2006.252.08:15:42.41#ibcon#about to read 5, iclass 16, count 2 2006.252.08:15:42.41#ibcon#read 5, iclass 16, count 2 2006.252.08:15:42.41#ibcon#about to read 6, iclass 16, count 2 2006.252.08:15:42.41#ibcon#read 6, iclass 16, count 2 2006.252.08:15:42.41#ibcon#end of sib2, iclass 16, count 2 2006.252.08:15:42.41#ibcon#*mode == 0, iclass 16, count 2 2006.252.08:15:42.41#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.252.08:15:42.41#ibcon#[27=AT06-04\r\n] 2006.252.08:15:42.41#ibcon#*before write, iclass 16, count 2 2006.252.08:15:42.41#ibcon#enter sib2, iclass 16, count 2 2006.252.08:15:42.41#ibcon#flushed, iclass 16, count 2 2006.252.08:15:42.41#ibcon#about to write, iclass 16, count 2 2006.252.08:15:42.41#ibcon#wrote, iclass 16, count 2 2006.252.08:15:42.41#ibcon#about to read 3, iclass 16, count 2 2006.252.08:15:42.44#ibcon#read 3, iclass 16, count 2 2006.252.08:15:42.44#ibcon#about to read 4, iclass 16, count 2 2006.252.08:15:42.44#ibcon#read 4, iclass 16, count 2 2006.252.08:15:42.44#ibcon#about to read 5, iclass 16, count 2 2006.252.08:15:42.44#ibcon#read 5, iclass 16, count 2 2006.252.08:15:42.44#ibcon#about to read 6, iclass 16, count 2 2006.252.08:15:42.44#ibcon#read 6, iclass 16, count 2 2006.252.08:15:42.44#ibcon#end of sib2, iclass 16, count 2 2006.252.08:15:42.44#ibcon#*after write, iclass 16, count 2 2006.252.08:15:42.44#ibcon#*before return 0, iclass 16, count 2 2006.252.08:15:42.44#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.252.08:15:42.44#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.252.08:15:42.44#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.252.08:15:42.44#ibcon#ireg 7 cls_cnt 0 2006.252.08:15:42.44#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.252.08:15:42.56#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.252.08:15:42.56#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.252.08:15:42.56#ibcon#enter wrdev, iclass 16, count 0 2006.252.08:15:42.56#ibcon#first serial, iclass 16, count 0 2006.252.08:15:42.56#ibcon#enter sib2, iclass 16, count 0 2006.252.08:15:42.56#ibcon#flushed, iclass 16, count 0 2006.252.08:15:42.56#ibcon#about to write, iclass 16, count 0 2006.252.08:15:42.56#ibcon#wrote, iclass 16, count 0 2006.252.08:15:42.56#ibcon#about to read 3, iclass 16, count 0 2006.252.08:15:42.58#ibcon#read 3, iclass 16, count 0 2006.252.08:15:42.58#ibcon#about to read 4, iclass 16, count 0 2006.252.08:15:42.58#ibcon#read 4, iclass 16, count 0 2006.252.08:15:42.58#ibcon#about to read 5, iclass 16, count 0 2006.252.08:15:42.58#ibcon#read 5, iclass 16, count 0 2006.252.08:15:42.58#ibcon#about to read 6, iclass 16, count 0 2006.252.08:15:42.58#ibcon#read 6, iclass 16, count 0 2006.252.08:15:42.58#ibcon#end of sib2, iclass 16, count 0 2006.252.08:15:42.58#ibcon#*mode == 0, iclass 16, count 0 2006.252.08:15:42.58#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.252.08:15:42.58#ibcon#[27=USB\r\n] 2006.252.08:15:42.58#ibcon#*before write, iclass 16, count 0 2006.252.08:15:42.58#ibcon#enter sib2, iclass 16, count 0 2006.252.08:15:42.58#ibcon#flushed, iclass 16, count 0 2006.252.08:15:42.58#ibcon#about to write, iclass 16, count 0 2006.252.08:15:42.58#ibcon#wrote, iclass 16, count 0 2006.252.08:15:42.58#ibcon#about to read 3, iclass 16, count 0 2006.252.08:15:42.61#ibcon#read 3, iclass 16, count 0 2006.252.08:15:42.61#ibcon#about to read 4, iclass 16, count 0 2006.252.08:15:42.61#ibcon#read 4, iclass 16, count 0 2006.252.08:15:42.61#ibcon#about to read 5, iclass 16, count 0 2006.252.08:15:42.61#ibcon#read 5, iclass 16, count 0 2006.252.08:15:42.61#ibcon#about to read 6, iclass 16, count 0 2006.252.08:15:42.61#ibcon#read 6, iclass 16, count 0 2006.252.08:15:42.61#ibcon#end of sib2, iclass 16, count 0 2006.252.08:15:42.61#ibcon#*after write, iclass 16, count 0 2006.252.08:15:42.61#ibcon#*before return 0, iclass 16, count 0 2006.252.08:15:42.61#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.252.08:15:42.61#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.252.08:15:42.61#ibcon#about to clear, iclass 16 cls_cnt 0 2006.252.08:15:42.61#ibcon#cleared, iclass 16 cls_cnt 0 2006.252.08:15:42.61$vc4f8/vabw=wide 2006.252.08:15:42.61#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.252.08:15:42.61#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.252.08:15:42.61#ibcon#ireg 8 cls_cnt 0 2006.252.08:15:42.61#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.252.08:15:42.61#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.252.08:15:42.61#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.252.08:15:42.61#ibcon#enter wrdev, iclass 19, count 0 2006.252.08:15:42.61#ibcon#first serial, iclass 19, count 0 2006.252.08:15:42.61#ibcon#enter sib2, iclass 19, count 0 2006.252.08:15:42.61#ibcon#flushed, iclass 19, count 0 2006.252.08:15:42.61#ibcon#about to write, iclass 19, count 0 2006.252.08:15:42.61#ibcon#wrote, iclass 19, count 0 2006.252.08:15:42.61#ibcon#about to read 3, iclass 19, count 0 2006.252.08:15:42.63#ibcon#read 3, iclass 19, count 0 2006.252.08:15:42.63#ibcon#about to read 4, iclass 19, count 0 2006.252.08:15:42.63#ibcon#read 4, iclass 19, count 0 2006.252.08:15:42.63#ibcon#about to read 5, iclass 19, count 0 2006.252.08:15:42.63#ibcon#read 5, iclass 19, count 0 2006.252.08:15:42.63#ibcon#about to read 6, iclass 19, count 0 2006.252.08:15:42.63#ibcon#read 6, iclass 19, count 0 2006.252.08:15:42.63#ibcon#end of sib2, iclass 19, count 0 2006.252.08:15:42.63#ibcon#*mode == 0, iclass 19, count 0 2006.252.08:15:42.63#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.252.08:15:42.63#ibcon#[25=BW32\r\n] 2006.252.08:15:42.63#ibcon#*before write, iclass 19, count 0 2006.252.08:15:42.63#ibcon#enter sib2, iclass 19, count 0 2006.252.08:15:42.63#ibcon#flushed, iclass 19, count 0 2006.252.08:15:42.63#ibcon#about to write, iclass 19, count 0 2006.252.08:15:42.63#ibcon#wrote, iclass 19, count 0 2006.252.08:15:42.63#ibcon#about to read 3, iclass 19, count 0 2006.252.08:15:42.66#ibcon#read 3, iclass 19, count 0 2006.252.08:15:42.66#ibcon#about to read 4, iclass 19, count 0 2006.252.08:15:42.66#ibcon#read 4, iclass 19, count 0 2006.252.08:15:42.66#ibcon#about to read 5, iclass 19, count 0 2006.252.08:15:42.66#ibcon#read 5, iclass 19, count 0 2006.252.08:15:42.66#ibcon#about to read 6, iclass 19, count 0 2006.252.08:15:42.66#ibcon#read 6, iclass 19, count 0 2006.252.08:15:42.66#ibcon#end of sib2, iclass 19, count 0 2006.252.08:15:42.66#ibcon#*after write, iclass 19, count 0 2006.252.08:15:42.66#ibcon#*before return 0, iclass 19, count 0 2006.252.08:15:42.66#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.252.08:15:42.66#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.252.08:15:42.66#ibcon#about to clear, iclass 19 cls_cnt 0 2006.252.08:15:42.66#ibcon#cleared, iclass 19 cls_cnt 0 2006.252.08:15:42.66$vc4f8/vbbw=wide 2006.252.08:15:42.66#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.252.08:15:42.66#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.252.08:15:42.66#ibcon#ireg 8 cls_cnt 0 2006.252.08:15:42.66#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.252.08:15:42.73#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.252.08:15:42.73#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.252.08:15:42.73#ibcon#enter wrdev, iclass 21, count 0 2006.252.08:15:42.73#ibcon#first serial, iclass 21, count 0 2006.252.08:15:42.73#ibcon#enter sib2, iclass 21, count 0 2006.252.08:15:42.73#ibcon#flushed, iclass 21, count 0 2006.252.08:15:42.73#ibcon#about to write, iclass 21, count 0 2006.252.08:15:42.73#ibcon#wrote, iclass 21, count 0 2006.252.08:15:42.73#ibcon#about to read 3, iclass 21, count 0 2006.252.08:15:42.75#ibcon#read 3, iclass 21, count 0 2006.252.08:15:42.75#ibcon#about to read 4, iclass 21, count 0 2006.252.08:15:42.75#ibcon#read 4, iclass 21, count 0 2006.252.08:15:42.75#ibcon#about to read 5, iclass 21, count 0 2006.252.08:15:42.75#ibcon#read 5, iclass 21, count 0 2006.252.08:15:42.75#ibcon#about to read 6, iclass 21, count 0 2006.252.08:15:42.75#ibcon#read 6, iclass 21, count 0 2006.252.08:15:42.75#ibcon#end of sib2, iclass 21, count 0 2006.252.08:15:42.75#ibcon#*mode == 0, iclass 21, count 0 2006.252.08:15:42.75#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.252.08:15:42.75#ibcon#[27=BW32\r\n] 2006.252.08:15:42.75#ibcon#*before write, iclass 21, count 0 2006.252.08:15:42.75#ibcon#enter sib2, iclass 21, count 0 2006.252.08:15:42.75#ibcon#flushed, iclass 21, count 0 2006.252.08:15:42.75#ibcon#about to write, iclass 21, count 0 2006.252.08:15:42.75#ibcon#wrote, iclass 21, count 0 2006.252.08:15:42.75#ibcon#about to read 3, iclass 21, count 0 2006.252.08:15:42.78#ibcon#read 3, iclass 21, count 0 2006.252.08:15:42.78#ibcon#about to read 4, iclass 21, count 0 2006.252.08:15:42.78#ibcon#read 4, iclass 21, count 0 2006.252.08:15:42.78#ibcon#about to read 5, iclass 21, count 0 2006.252.08:15:42.78#ibcon#read 5, iclass 21, count 0 2006.252.08:15:42.78#ibcon#about to read 6, iclass 21, count 0 2006.252.08:15:42.78#ibcon#read 6, iclass 21, count 0 2006.252.08:15:42.78#ibcon#end of sib2, iclass 21, count 0 2006.252.08:15:42.78#ibcon#*after write, iclass 21, count 0 2006.252.08:15:42.78#ibcon#*before return 0, iclass 21, count 0 2006.252.08:15:42.78#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.252.08:15:42.78#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.252.08:15:42.78#ibcon#about to clear, iclass 21 cls_cnt 0 2006.252.08:15:42.78#ibcon#cleared, iclass 21 cls_cnt 0 2006.252.08:15:42.78$4f8m12a/ifd4f 2006.252.08:15:42.78$ifd4f/lo= 2006.252.08:15:42.79$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.252.08:15:42.79$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.252.08:15:42.79$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.252.08:15:42.79$ifd4f/patch= 2006.252.08:15:42.79$ifd4f/patch=lo1,a1,a2,a3,a4 2006.252.08:15:42.79$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.252.08:15:42.79$ifd4f/patch=lo3,a5,a6,a7,a8 2006.252.08:15:42.79$4f8m12a/"form=m,16.000,1:2 2006.252.08:15:42.79$4f8m12a/"tpicd 2006.252.08:15:42.79$4f8m12a/echo=off 2006.252.08:15:42.79$4f8m12a/xlog=off 2006.252.08:15:42.79:!2006.252.08:16:10 2006.252.08:15:53.14#trakl#Source acquired 2006.252.08:15:55.14#flagr#flagr/antenna,acquired 2006.252.08:16:10.01:preob 2006.252.08:16:11.14/onsource/TRACKING 2006.252.08:16:11.14:!2006.252.08:16:20 2006.252.08:16:20.00:data_valid=on 2006.252.08:16:20.00:midob 2006.252.08:16:20.14/onsource/TRACKING 2006.252.08:16:20.15/wx/27.28,1011.2,91 2006.252.08:16:20.27/cable/+6.4093E-03 2006.252.08:16:21.36/va/01,08,usb,yes,33,35 2006.252.08:16:21.36/va/02,07,usb,yes,33,34 2006.252.08:16:21.36/va/03,06,usb,yes,35,35 2006.252.08:16:21.36/va/04,07,usb,yes,34,37 2006.252.08:16:21.36/va/05,07,usb,yes,37,39 2006.252.08:16:21.36/va/06,07,usb,yes,32,32 2006.252.08:16:21.36/va/07,07,usb,yes,32,32 2006.252.08:16:21.36/va/08,07,usb,yes,35,34 2006.252.08:16:21.59/valo/01,532.99,yes,locked 2006.252.08:16:21.59/valo/02,572.99,yes,locked 2006.252.08:16:21.59/valo/03,672.99,yes,locked 2006.252.08:16:21.59/valo/04,832.99,yes,locked 2006.252.08:16:21.59/valo/05,652.99,yes,locked 2006.252.08:16:21.59/valo/06,772.99,yes,locked 2006.252.08:16:21.59/valo/07,832.99,yes,locked 2006.252.08:16:21.59/valo/08,852.99,yes,locked 2006.252.08:16:22.68/vb/01,04,usb,yes,30,29 2006.252.08:16:22.68/vb/02,05,usb,yes,28,30 2006.252.08:16:22.68/vb/03,04,usb,yes,29,32 2006.252.08:16:22.68/vb/04,04,usb,yes,29,30 2006.252.08:16:22.68/vb/05,04,usb,yes,28,32 2006.252.08:16:22.68/vb/06,04,usb,yes,29,32 2006.252.08:16:22.68/vb/07,04,usb,yes,31,31 2006.252.08:16:22.68/vb/08,04,usb,yes,28,32 2006.252.08:16:22.92/vblo/01,632.99,yes,locked 2006.252.08:16:22.92/vblo/02,640.99,yes,locked 2006.252.08:16:22.92/vblo/03,656.99,yes,locked 2006.252.08:16:22.92/vblo/04,712.99,yes,locked 2006.252.08:16:22.92/vblo/05,744.99,yes,locked 2006.252.08:16:22.92/vblo/06,752.99,yes,locked 2006.252.08:16:22.92/vblo/07,734.99,yes,locked 2006.252.08:16:22.92/vblo/08,744.99,yes,locked 2006.252.08:16:23.07/vabw/8 2006.252.08:16:23.22/vbbw/8 2006.252.08:16:23.43/xfe/off,on,14.0 2006.252.08:16:23.82/ifatt/23,28,28,28 2006.252.08:16:24.07/fmout-gps/S +4.75E-07 2006.252.08:16:24.12:!2006.252.08:17:20 2006.252.08:17:20.01:data_valid=off 2006.252.08:17:20.02:postob 2006.252.08:17:20.10/cable/+6.4109E-03 2006.252.08:17:20.10/wx/27.27,1011.2,91 2006.252.08:17:21.07/fmout-gps/S +4.76E-07 2006.252.08:17:21.07:scan_name=252-0818,k06252,60 2006.252.08:17:21.07:source=nrao512,164029.63,394646.0,2000.0,ccw 2006.252.08:17:21.14#flagr#flagr/antenna,new-source 2006.252.08:17:22.14:checkk5 2006.252.08:17:22.52/chk_autoobs//k5ts1/ autoobs is running! 2006.252.08:17:22.89/chk_autoobs//k5ts2/ autoobs is running! 2006.252.08:17:23.27/chk_autoobs//k5ts3/ autoobs is running! 2006.252.08:17:23.64/chk_autoobs//k5ts4/ autoobs is running! 2006.252.08:17:24.02/chk_obsdata//k5ts1/T2520816??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.252.08:17:24.39/chk_obsdata//k5ts2/T2520816??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.252.08:17:24.76/chk_obsdata//k5ts3/T2520816??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.252.08:17:25.14/chk_obsdata//k5ts4/T2520816??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.252.08:17:25.86/k5log//k5ts1_log_newline 2006.252.08:17:26.57/k5log//k5ts2_log_newline 2006.252.08:17:27.27/k5log//k5ts3_log_newline 2006.252.08:17:28.07/k5log//k5ts4_log_newline 2006.252.08:17:28.09/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.252.08:17:28.09:4f8m12a=2 2006.252.08:17:28.09$4f8m12a/echo=on 2006.252.08:17:28.09$4f8m12a/pcalon 2006.252.08:17:28.09$pcalon/"no phase cal control is implemented here 2006.252.08:17:28.09$4f8m12a/"tpicd=stop 2006.252.08:17:28.09$4f8m12a/vc4f8 2006.252.08:17:28.09$vc4f8/valo=1,532.99 2006.252.08:17:28.10#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.252.08:17:28.10#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.252.08:17:28.10#ibcon#ireg 17 cls_cnt 0 2006.252.08:17:28.10#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.252.08:17:28.10#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.252.08:17:28.10#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.252.08:17:28.10#ibcon#enter wrdev, iclass 28, count 0 2006.252.08:17:28.10#ibcon#first serial, iclass 28, count 0 2006.252.08:17:28.10#ibcon#enter sib2, iclass 28, count 0 2006.252.08:17:28.10#ibcon#flushed, iclass 28, count 0 2006.252.08:17:28.10#ibcon#about to write, iclass 28, count 0 2006.252.08:17:28.10#ibcon#wrote, iclass 28, count 0 2006.252.08:17:28.10#ibcon#about to read 3, iclass 28, count 0 2006.252.08:17:28.14#ibcon#read 3, iclass 28, count 0 2006.252.08:17:28.14#ibcon#about to read 4, iclass 28, count 0 2006.252.08:17:28.14#ibcon#read 4, iclass 28, count 0 2006.252.08:17:28.14#ibcon#about to read 5, iclass 28, count 0 2006.252.08:17:28.14#ibcon#read 5, iclass 28, count 0 2006.252.08:17:28.14#ibcon#about to read 6, iclass 28, count 0 2006.252.08:17:28.14#ibcon#read 6, iclass 28, count 0 2006.252.08:17:28.14#ibcon#end of sib2, iclass 28, count 0 2006.252.08:17:28.14#ibcon#*mode == 0, iclass 28, count 0 2006.252.08:17:28.14#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.252.08:17:28.14#ibcon#[26=FRQ=01,532.99\r\n] 2006.252.08:17:28.14#ibcon#*before write, iclass 28, count 0 2006.252.08:17:28.14#ibcon#enter sib2, iclass 28, count 0 2006.252.08:17:28.14#ibcon#flushed, iclass 28, count 0 2006.252.08:17:28.14#ibcon#about to write, iclass 28, count 0 2006.252.08:17:28.14#ibcon#wrote, iclass 28, count 0 2006.252.08:17:28.14#ibcon#about to read 3, iclass 28, count 0 2006.252.08:17:28.18#ibcon#read 3, iclass 28, count 0 2006.252.08:17:28.18#ibcon#about to read 4, iclass 28, count 0 2006.252.08:17:28.18#ibcon#read 4, iclass 28, count 0 2006.252.08:17:28.18#ibcon#about to read 5, iclass 28, count 0 2006.252.08:17:28.18#ibcon#read 5, iclass 28, count 0 2006.252.08:17:28.18#ibcon#about to read 6, iclass 28, count 0 2006.252.08:17:28.18#ibcon#read 6, iclass 28, count 0 2006.252.08:17:28.18#ibcon#end of sib2, iclass 28, count 0 2006.252.08:17:28.18#ibcon#*after write, iclass 28, count 0 2006.252.08:17:28.18#ibcon#*before return 0, iclass 28, count 0 2006.252.08:17:28.18#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.252.08:17:28.18#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.252.08:17:28.18#ibcon#about to clear, iclass 28 cls_cnt 0 2006.252.08:17:28.18#ibcon#cleared, iclass 28 cls_cnt 0 2006.252.08:17:28.18$vc4f8/va=1,8 2006.252.08:17:28.18#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.252.08:17:28.18#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.252.08:17:28.18#ibcon#ireg 11 cls_cnt 2 2006.252.08:17:28.18#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.252.08:17:28.18#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.252.08:17:28.18#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.252.08:17:28.18#ibcon#enter wrdev, iclass 30, count 2 2006.252.08:17:28.18#ibcon#first serial, iclass 30, count 2 2006.252.08:17:28.18#ibcon#enter sib2, iclass 30, count 2 2006.252.08:17:28.18#ibcon#flushed, iclass 30, count 2 2006.252.08:17:28.18#ibcon#about to write, iclass 30, count 2 2006.252.08:17:28.18#ibcon#wrote, iclass 30, count 2 2006.252.08:17:28.18#ibcon#about to read 3, iclass 30, count 2 2006.252.08:17:28.20#ibcon#read 3, iclass 30, count 2 2006.252.08:17:28.20#ibcon#about to read 4, iclass 30, count 2 2006.252.08:17:28.20#ibcon#read 4, iclass 30, count 2 2006.252.08:17:28.20#ibcon#about to read 5, iclass 30, count 2 2006.252.08:17:28.20#ibcon#read 5, iclass 30, count 2 2006.252.08:17:28.20#ibcon#about to read 6, iclass 30, count 2 2006.252.08:17:28.20#ibcon#read 6, iclass 30, count 2 2006.252.08:17:28.20#ibcon#end of sib2, iclass 30, count 2 2006.252.08:17:28.20#ibcon#*mode == 0, iclass 30, count 2 2006.252.08:17:28.20#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.252.08:17:28.20#ibcon#[25=AT01-08\r\n] 2006.252.08:17:28.20#ibcon#*before write, iclass 30, count 2 2006.252.08:17:28.20#ibcon#enter sib2, iclass 30, count 2 2006.252.08:17:28.20#ibcon#flushed, iclass 30, count 2 2006.252.08:17:28.20#ibcon#about to write, iclass 30, count 2 2006.252.08:17:28.20#ibcon#wrote, iclass 30, count 2 2006.252.08:17:28.20#ibcon#about to read 3, iclass 30, count 2 2006.252.08:17:28.23#ibcon#read 3, iclass 30, count 2 2006.252.08:17:28.23#ibcon#about to read 4, iclass 30, count 2 2006.252.08:17:28.23#ibcon#read 4, iclass 30, count 2 2006.252.08:17:28.23#ibcon#about to read 5, iclass 30, count 2 2006.252.08:17:28.23#ibcon#read 5, iclass 30, count 2 2006.252.08:17:28.23#ibcon#about to read 6, iclass 30, count 2 2006.252.08:17:28.23#ibcon#read 6, iclass 30, count 2 2006.252.08:17:28.23#ibcon#end of sib2, iclass 30, count 2 2006.252.08:17:28.23#ibcon#*after write, iclass 30, count 2 2006.252.08:17:28.23#ibcon#*before return 0, iclass 30, count 2 2006.252.08:17:28.23#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.252.08:17:28.23#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.252.08:17:28.23#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.252.08:17:28.23#ibcon#ireg 7 cls_cnt 0 2006.252.08:17:28.23#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.252.08:17:28.35#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.252.08:17:28.35#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.252.08:17:28.35#ibcon#enter wrdev, iclass 30, count 0 2006.252.08:17:28.35#ibcon#first serial, iclass 30, count 0 2006.252.08:17:28.35#ibcon#enter sib2, iclass 30, count 0 2006.252.08:17:28.35#ibcon#flushed, iclass 30, count 0 2006.252.08:17:28.35#ibcon#about to write, iclass 30, count 0 2006.252.08:17:28.35#ibcon#wrote, iclass 30, count 0 2006.252.08:17:28.35#ibcon#about to read 3, iclass 30, count 0 2006.252.08:17:28.37#ibcon#read 3, iclass 30, count 0 2006.252.08:17:28.37#ibcon#about to read 4, iclass 30, count 0 2006.252.08:17:28.37#ibcon#read 4, iclass 30, count 0 2006.252.08:17:28.37#ibcon#about to read 5, iclass 30, count 0 2006.252.08:17:28.37#ibcon#read 5, iclass 30, count 0 2006.252.08:17:28.37#ibcon#about to read 6, iclass 30, count 0 2006.252.08:17:28.37#ibcon#read 6, iclass 30, count 0 2006.252.08:17:28.37#ibcon#end of sib2, iclass 30, count 0 2006.252.08:17:28.37#ibcon#*mode == 0, iclass 30, count 0 2006.252.08:17:28.37#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.252.08:17:28.37#ibcon#[25=USB\r\n] 2006.252.08:17:28.37#ibcon#*before write, iclass 30, count 0 2006.252.08:17:28.37#ibcon#enter sib2, iclass 30, count 0 2006.252.08:17:28.37#ibcon#flushed, iclass 30, count 0 2006.252.08:17:28.37#ibcon#about to write, iclass 30, count 0 2006.252.08:17:28.37#ibcon#wrote, iclass 30, count 0 2006.252.08:17:28.37#ibcon#about to read 3, iclass 30, count 0 2006.252.08:17:28.40#ibcon#read 3, iclass 30, count 0 2006.252.08:17:28.40#ibcon#about to read 4, iclass 30, count 0 2006.252.08:17:28.40#ibcon#read 4, iclass 30, count 0 2006.252.08:17:28.40#ibcon#about to read 5, iclass 30, count 0 2006.252.08:17:28.40#ibcon#read 5, iclass 30, count 0 2006.252.08:17:28.40#ibcon#about to read 6, iclass 30, count 0 2006.252.08:17:28.40#ibcon#read 6, iclass 30, count 0 2006.252.08:17:28.40#ibcon#end of sib2, iclass 30, count 0 2006.252.08:17:28.40#ibcon#*after write, iclass 30, count 0 2006.252.08:17:28.40#ibcon#*before return 0, iclass 30, count 0 2006.252.08:17:28.40#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.252.08:17:28.40#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.252.08:17:28.40#ibcon#about to clear, iclass 30 cls_cnt 0 2006.252.08:17:28.40#ibcon#cleared, iclass 30 cls_cnt 0 2006.252.08:17:28.40$vc4f8/valo=2,572.99 2006.252.08:17:28.40#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.252.08:17:28.40#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.252.08:17:28.40#ibcon#ireg 17 cls_cnt 0 2006.252.08:17:28.40#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.252.08:17:28.40#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.252.08:17:28.40#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.252.08:17:28.40#ibcon#enter wrdev, iclass 32, count 0 2006.252.08:17:28.40#ibcon#first serial, iclass 32, count 0 2006.252.08:17:28.40#ibcon#enter sib2, iclass 32, count 0 2006.252.08:17:28.40#ibcon#flushed, iclass 32, count 0 2006.252.08:17:28.40#ibcon#about to write, iclass 32, count 0 2006.252.08:17:28.40#ibcon#wrote, iclass 32, count 0 2006.252.08:17:28.40#ibcon#about to read 3, iclass 32, count 0 2006.252.08:17:28.43#ibcon#read 3, iclass 32, count 0 2006.252.08:17:28.43#ibcon#about to read 4, iclass 32, count 0 2006.252.08:17:28.43#ibcon#read 4, iclass 32, count 0 2006.252.08:17:28.43#ibcon#about to read 5, iclass 32, count 0 2006.252.08:17:28.43#ibcon#read 5, iclass 32, count 0 2006.252.08:17:28.43#ibcon#about to read 6, iclass 32, count 0 2006.252.08:17:28.43#ibcon#read 6, iclass 32, count 0 2006.252.08:17:28.43#ibcon#end of sib2, iclass 32, count 0 2006.252.08:17:28.43#ibcon#*mode == 0, iclass 32, count 0 2006.252.08:17:28.43#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.252.08:17:28.43#ibcon#[26=FRQ=02,572.99\r\n] 2006.252.08:17:28.43#ibcon#*before write, iclass 32, count 0 2006.252.08:17:28.43#ibcon#enter sib2, iclass 32, count 0 2006.252.08:17:28.43#ibcon#flushed, iclass 32, count 0 2006.252.08:17:28.43#ibcon#about to write, iclass 32, count 0 2006.252.08:17:28.43#ibcon#wrote, iclass 32, count 0 2006.252.08:17:28.43#ibcon#about to read 3, iclass 32, count 0 2006.252.08:17:28.47#ibcon#read 3, iclass 32, count 0 2006.252.08:17:28.47#ibcon#about to read 4, iclass 32, count 0 2006.252.08:17:28.47#ibcon#read 4, iclass 32, count 0 2006.252.08:17:28.47#ibcon#about to read 5, iclass 32, count 0 2006.252.08:17:28.47#ibcon#read 5, iclass 32, count 0 2006.252.08:17:28.47#ibcon#about to read 6, iclass 32, count 0 2006.252.08:17:28.47#ibcon#read 6, iclass 32, count 0 2006.252.08:17:28.47#ibcon#end of sib2, iclass 32, count 0 2006.252.08:17:28.47#ibcon#*after write, iclass 32, count 0 2006.252.08:17:28.47#ibcon#*before return 0, iclass 32, count 0 2006.252.08:17:28.47#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.252.08:17:28.47#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.252.08:17:28.47#ibcon#about to clear, iclass 32 cls_cnt 0 2006.252.08:17:28.47#ibcon#cleared, iclass 32 cls_cnt 0 2006.252.08:17:28.47$vc4f8/va=2,7 2006.252.08:17:28.47#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.252.08:17:28.47#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.252.08:17:28.47#ibcon#ireg 11 cls_cnt 2 2006.252.08:17:28.47#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.252.08:17:28.53#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.252.08:17:28.53#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.252.08:17:28.53#ibcon#enter wrdev, iclass 34, count 2 2006.252.08:17:28.53#ibcon#first serial, iclass 34, count 2 2006.252.08:17:28.53#ibcon#enter sib2, iclass 34, count 2 2006.252.08:17:28.53#ibcon#flushed, iclass 34, count 2 2006.252.08:17:28.53#ibcon#about to write, iclass 34, count 2 2006.252.08:17:28.53#ibcon#wrote, iclass 34, count 2 2006.252.08:17:28.53#ibcon#about to read 3, iclass 34, count 2 2006.252.08:17:28.54#ibcon#read 3, iclass 34, count 2 2006.252.08:17:28.54#ibcon#about to read 4, iclass 34, count 2 2006.252.08:17:28.54#ibcon#read 4, iclass 34, count 2 2006.252.08:17:28.54#ibcon#about to read 5, iclass 34, count 2 2006.252.08:17:28.54#ibcon#read 5, iclass 34, count 2 2006.252.08:17:28.54#ibcon#about to read 6, iclass 34, count 2 2006.252.08:17:28.54#ibcon#read 6, iclass 34, count 2 2006.252.08:17:28.54#ibcon#end of sib2, iclass 34, count 2 2006.252.08:17:28.54#ibcon#*mode == 0, iclass 34, count 2 2006.252.08:17:28.54#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.252.08:17:28.54#ibcon#[25=AT02-07\r\n] 2006.252.08:17:28.54#ibcon#*before write, iclass 34, count 2 2006.252.08:17:28.54#ibcon#enter sib2, iclass 34, count 2 2006.252.08:17:28.54#ibcon#flushed, iclass 34, count 2 2006.252.08:17:28.54#ibcon#about to write, iclass 34, count 2 2006.252.08:17:28.54#ibcon#wrote, iclass 34, count 2 2006.252.08:17:28.54#ibcon#about to read 3, iclass 34, count 2 2006.252.08:17:28.57#ibcon#read 3, iclass 34, count 2 2006.252.08:17:28.57#ibcon#about to read 4, iclass 34, count 2 2006.252.08:17:28.57#ibcon#read 4, iclass 34, count 2 2006.252.08:17:28.57#ibcon#about to read 5, iclass 34, count 2 2006.252.08:17:28.57#ibcon#read 5, iclass 34, count 2 2006.252.08:17:28.57#ibcon#about to read 6, iclass 34, count 2 2006.252.08:17:28.57#ibcon#read 6, iclass 34, count 2 2006.252.08:17:28.57#ibcon#end of sib2, iclass 34, count 2 2006.252.08:17:28.57#ibcon#*after write, iclass 34, count 2 2006.252.08:17:28.57#ibcon#*before return 0, iclass 34, count 2 2006.252.08:17:28.57#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.252.08:17:28.57#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.252.08:17:28.57#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.252.08:17:28.57#ibcon#ireg 7 cls_cnt 0 2006.252.08:17:28.57#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.252.08:17:28.69#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.252.08:17:28.69#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.252.08:17:28.69#ibcon#enter wrdev, iclass 34, count 0 2006.252.08:17:28.69#ibcon#first serial, iclass 34, count 0 2006.252.08:17:28.69#ibcon#enter sib2, iclass 34, count 0 2006.252.08:17:28.69#ibcon#flushed, iclass 34, count 0 2006.252.08:17:28.69#ibcon#about to write, iclass 34, count 0 2006.252.08:17:28.69#ibcon#wrote, iclass 34, count 0 2006.252.08:17:28.69#ibcon#about to read 3, iclass 34, count 0 2006.252.08:17:28.71#ibcon#read 3, iclass 34, count 0 2006.252.08:17:28.71#ibcon#about to read 4, iclass 34, count 0 2006.252.08:17:28.71#ibcon#read 4, iclass 34, count 0 2006.252.08:17:28.71#ibcon#about to read 5, iclass 34, count 0 2006.252.08:17:28.71#ibcon#read 5, iclass 34, count 0 2006.252.08:17:28.71#ibcon#about to read 6, iclass 34, count 0 2006.252.08:17:28.71#ibcon#read 6, iclass 34, count 0 2006.252.08:17:28.71#ibcon#end of sib2, iclass 34, count 0 2006.252.08:17:28.71#ibcon#*mode == 0, iclass 34, count 0 2006.252.08:17:28.71#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.252.08:17:28.71#ibcon#[25=USB\r\n] 2006.252.08:17:28.71#ibcon#*before write, iclass 34, count 0 2006.252.08:17:28.71#ibcon#enter sib2, iclass 34, count 0 2006.252.08:17:28.71#ibcon#flushed, iclass 34, count 0 2006.252.08:17:28.71#ibcon#about to write, iclass 34, count 0 2006.252.08:17:28.71#ibcon#wrote, iclass 34, count 0 2006.252.08:17:28.71#ibcon#about to read 3, iclass 34, count 0 2006.252.08:17:28.74#ibcon#read 3, iclass 34, count 0 2006.252.08:17:28.74#ibcon#about to read 4, iclass 34, count 0 2006.252.08:17:28.74#ibcon#read 4, iclass 34, count 0 2006.252.08:17:28.74#ibcon#about to read 5, iclass 34, count 0 2006.252.08:17:28.74#ibcon#read 5, iclass 34, count 0 2006.252.08:17:28.74#ibcon#about to read 6, iclass 34, count 0 2006.252.08:17:28.74#ibcon#read 6, iclass 34, count 0 2006.252.08:17:28.74#ibcon#end of sib2, iclass 34, count 0 2006.252.08:17:28.74#ibcon#*after write, iclass 34, count 0 2006.252.08:17:28.74#ibcon#*before return 0, iclass 34, count 0 2006.252.08:17:28.74#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.252.08:17:28.74#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.252.08:17:28.74#ibcon#about to clear, iclass 34 cls_cnt 0 2006.252.08:17:28.74#ibcon#cleared, iclass 34 cls_cnt 0 2006.252.08:17:28.74$vc4f8/valo=3,672.99 2006.252.08:17:28.74#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.252.08:17:28.74#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.252.08:17:28.74#ibcon#ireg 17 cls_cnt 0 2006.252.08:17:28.74#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.252.08:17:28.74#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.252.08:17:28.74#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.252.08:17:28.74#ibcon#enter wrdev, iclass 36, count 0 2006.252.08:17:28.74#ibcon#first serial, iclass 36, count 0 2006.252.08:17:28.74#ibcon#enter sib2, iclass 36, count 0 2006.252.08:17:28.74#ibcon#flushed, iclass 36, count 0 2006.252.08:17:28.74#ibcon#about to write, iclass 36, count 0 2006.252.08:17:28.74#ibcon#wrote, iclass 36, count 0 2006.252.08:17:28.74#ibcon#about to read 3, iclass 36, count 0 2006.252.08:17:28.77#ibcon#read 3, iclass 36, count 0 2006.252.08:17:28.77#ibcon#about to read 4, iclass 36, count 0 2006.252.08:17:28.77#ibcon#read 4, iclass 36, count 0 2006.252.08:17:28.77#ibcon#about to read 5, iclass 36, count 0 2006.252.08:17:28.77#ibcon#read 5, iclass 36, count 0 2006.252.08:17:28.77#ibcon#about to read 6, iclass 36, count 0 2006.252.08:17:28.77#ibcon#read 6, iclass 36, count 0 2006.252.08:17:28.77#ibcon#end of sib2, iclass 36, count 0 2006.252.08:17:28.77#ibcon#*mode == 0, iclass 36, count 0 2006.252.08:17:28.77#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.252.08:17:28.77#ibcon#[26=FRQ=03,672.99\r\n] 2006.252.08:17:28.77#ibcon#*before write, iclass 36, count 0 2006.252.08:17:28.77#ibcon#enter sib2, iclass 36, count 0 2006.252.08:17:28.77#ibcon#flushed, iclass 36, count 0 2006.252.08:17:28.77#ibcon#about to write, iclass 36, count 0 2006.252.08:17:28.77#ibcon#wrote, iclass 36, count 0 2006.252.08:17:28.77#ibcon#about to read 3, iclass 36, count 0 2006.252.08:17:28.81#ibcon#read 3, iclass 36, count 0 2006.252.08:17:28.81#ibcon#about to read 4, iclass 36, count 0 2006.252.08:17:28.81#ibcon#read 4, iclass 36, count 0 2006.252.08:17:28.81#ibcon#about to read 5, iclass 36, count 0 2006.252.08:17:28.81#ibcon#read 5, iclass 36, count 0 2006.252.08:17:28.81#ibcon#about to read 6, iclass 36, count 0 2006.252.08:17:28.81#ibcon#read 6, iclass 36, count 0 2006.252.08:17:28.81#ibcon#end of sib2, iclass 36, count 0 2006.252.08:17:28.81#ibcon#*after write, iclass 36, count 0 2006.252.08:17:28.81#ibcon#*before return 0, iclass 36, count 0 2006.252.08:17:28.81#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.252.08:17:28.81#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.252.08:17:28.81#ibcon#about to clear, iclass 36 cls_cnt 0 2006.252.08:17:28.81#ibcon#cleared, iclass 36 cls_cnt 0 2006.252.08:17:28.81$vc4f8/va=3,6 2006.252.08:17:28.81#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.252.08:17:28.81#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.252.08:17:28.81#ibcon#ireg 11 cls_cnt 2 2006.252.08:17:28.81#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.252.08:17:28.87#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.252.08:17:28.87#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.252.08:17:28.87#ibcon#enter wrdev, iclass 38, count 2 2006.252.08:17:28.87#ibcon#first serial, iclass 38, count 2 2006.252.08:17:28.87#ibcon#enter sib2, iclass 38, count 2 2006.252.08:17:28.87#ibcon#flushed, iclass 38, count 2 2006.252.08:17:28.87#ibcon#about to write, iclass 38, count 2 2006.252.08:17:28.87#ibcon#wrote, iclass 38, count 2 2006.252.08:17:28.87#ibcon#about to read 3, iclass 38, count 2 2006.252.08:17:28.88#ibcon#read 3, iclass 38, count 2 2006.252.08:17:28.88#ibcon#about to read 4, iclass 38, count 2 2006.252.08:17:28.88#ibcon#read 4, iclass 38, count 2 2006.252.08:17:28.88#ibcon#about to read 5, iclass 38, count 2 2006.252.08:17:28.88#ibcon#read 5, iclass 38, count 2 2006.252.08:17:28.88#ibcon#about to read 6, iclass 38, count 2 2006.252.08:17:28.88#ibcon#read 6, iclass 38, count 2 2006.252.08:17:28.88#ibcon#end of sib2, iclass 38, count 2 2006.252.08:17:28.88#ibcon#*mode == 0, iclass 38, count 2 2006.252.08:17:28.88#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.252.08:17:28.88#ibcon#[25=AT03-06\r\n] 2006.252.08:17:28.88#ibcon#*before write, iclass 38, count 2 2006.252.08:17:28.88#ibcon#enter sib2, iclass 38, count 2 2006.252.08:17:28.88#ibcon#flushed, iclass 38, count 2 2006.252.08:17:28.88#ibcon#about to write, iclass 38, count 2 2006.252.08:17:28.88#ibcon#wrote, iclass 38, count 2 2006.252.08:17:28.88#ibcon#about to read 3, iclass 38, count 2 2006.252.08:17:28.91#ibcon#read 3, iclass 38, count 2 2006.252.08:17:28.91#ibcon#about to read 4, iclass 38, count 2 2006.252.08:17:28.91#ibcon#read 4, iclass 38, count 2 2006.252.08:17:28.91#ibcon#about to read 5, iclass 38, count 2 2006.252.08:17:28.91#ibcon#read 5, iclass 38, count 2 2006.252.08:17:28.91#ibcon#about to read 6, iclass 38, count 2 2006.252.08:17:28.91#ibcon#read 6, iclass 38, count 2 2006.252.08:17:28.91#ibcon#end of sib2, iclass 38, count 2 2006.252.08:17:28.91#ibcon#*after write, iclass 38, count 2 2006.252.08:17:28.91#ibcon#*before return 0, iclass 38, count 2 2006.252.08:17:28.91#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.252.08:17:28.91#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.252.08:17:28.91#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.252.08:17:28.91#ibcon#ireg 7 cls_cnt 0 2006.252.08:17:28.91#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.252.08:17:29.03#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.252.08:17:29.03#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.252.08:17:29.03#ibcon#enter wrdev, iclass 38, count 0 2006.252.08:17:29.03#ibcon#first serial, iclass 38, count 0 2006.252.08:17:29.03#ibcon#enter sib2, iclass 38, count 0 2006.252.08:17:29.03#ibcon#flushed, iclass 38, count 0 2006.252.08:17:29.03#ibcon#about to write, iclass 38, count 0 2006.252.08:17:29.03#ibcon#wrote, iclass 38, count 0 2006.252.08:17:29.03#ibcon#about to read 3, iclass 38, count 0 2006.252.08:17:29.05#ibcon#read 3, iclass 38, count 0 2006.252.08:17:29.05#ibcon#about to read 4, iclass 38, count 0 2006.252.08:17:29.05#ibcon#read 4, iclass 38, count 0 2006.252.08:17:29.05#ibcon#about to read 5, iclass 38, count 0 2006.252.08:17:29.05#ibcon#read 5, iclass 38, count 0 2006.252.08:17:29.05#ibcon#about to read 6, iclass 38, count 0 2006.252.08:17:29.05#ibcon#read 6, iclass 38, count 0 2006.252.08:17:29.05#ibcon#end of sib2, iclass 38, count 0 2006.252.08:17:29.05#ibcon#*mode == 0, iclass 38, count 0 2006.252.08:17:29.05#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.252.08:17:29.05#ibcon#[25=USB\r\n] 2006.252.08:17:29.05#ibcon#*before write, iclass 38, count 0 2006.252.08:17:29.05#ibcon#enter sib2, iclass 38, count 0 2006.252.08:17:29.05#ibcon#flushed, iclass 38, count 0 2006.252.08:17:29.05#ibcon#about to write, iclass 38, count 0 2006.252.08:17:29.05#ibcon#wrote, iclass 38, count 0 2006.252.08:17:29.05#ibcon#about to read 3, iclass 38, count 0 2006.252.08:17:29.08#ibcon#read 3, iclass 38, count 0 2006.252.08:17:29.09#ibcon#about to read 4, iclass 38, count 0 2006.252.08:17:29.09#ibcon#read 4, iclass 38, count 0 2006.252.08:17:29.09#ibcon#about to read 5, iclass 38, count 0 2006.252.08:17:29.09#ibcon#read 5, iclass 38, count 0 2006.252.08:17:29.09#ibcon#about to read 6, iclass 38, count 0 2006.252.08:17:29.09#ibcon#read 6, iclass 38, count 0 2006.252.08:17:29.09#ibcon#end of sib2, iclass 38, count 0 2006.252.08:17:29.09#ibcon#*after write, iclass 38, count 0 2006.252.08:17:29.09#ibcon#*before return 0, iclass 38, count 0 2006.252.08:17:29.09#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.252.08:17:29.09#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.252.08:17:29.09#ibcon#about to clear, iclass 38 cls_cnt 0 2006.252.08:17:29.09#ibcon#cleared, iclass 38 cls_cnt 0 2006.252.08:17:29.09$vc4f8/valo=4,832.99 2006.252.08:17:29.09#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.252.08:17:29.09#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.252.08:17:29.09#ibcon#ireg 17 cls_cnt 0 2006.252.08:17:29.09#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.252.08:17:29.09#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.252.08:17:29.09#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.252.08:17:29.09#ibcon#enter wrdev, iclass 40, count 0 2006.252.08:17:29.09#ibcon#first serial, iclass 40, count 0 2006.252.08:17:29.09#ibcon#enter sib2, iclass 40, count 0 2006.252.08:17:29.09#ibcon#flushed, iclass 40, count 0 2006.252.08:17:29.09#ibcon#about to write, iclass 40, count 0 2006.252.08:17:29.09#ibcon#wrote, iclass 40, count 0 2006.252.08:17:29.09#ibcon#about to read 3, iclass 40, count 0 2006.252.08:17:29.10#ibcon#read 3, iclass 40, count 0 2006.252.08:17:29.10#ibcon#about to read 4, iclass 40, count 0 2006.252.08:17:29.10#ibcon#read 4, iclass 40, count 0 2006.252.08:17:29.10#ibcon#about to read 5, iclass 40, count 0 2006.252.08:17:29.10#ibcon#read 5, iclass 40, count 0 2006.252.08:17:29.10#ibcon#about to read 6, iclass 40, count 0 2006.252.08:17:29.10#ibcon#read 6, iclass 40, count 0 2006.252.08:17:29.10#ibcon#end of sib2, iclass 40, count 0 2006.252.08:17:29.10#ibcon#*mode == 0, iclass 40, count 0 2006.252.08:17:29.10#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.252.08:17:29.10#ibcon#[26=FRQ=04,832.99\r\n] 2006.252.08:17:29.10#ibcon#*before write, iclass 40, count 0 2006.252.08:17:29.10#ibcon#enter sib2, iclass 40, count 0 2006.252.08:17:29.10#ibcon#flushed, iclass 40, count 0 2006.252.08:17:29.10#ibcon#about to write, iclass 40, count 0 2006.252.08:17:29.10#ibcon#wrote, iclass 40, count 0 2006.252.08:17:29.10#ibcon#about to read 3, iclass 40, count 0 2006.252.08:17:29.14#ibcon#read 3, iclass 40, count 0 2006.252.08:17:29.14#ibcon#about to read 4, iclass 40, count 0 2006.252.08:17:29.14#ibcon#read 4, iclass 40, count 0 2006.252.08:17:29.14#ibcon#about to read 5, iclass 40, count 0 2006.252.08:17:29.14#ibcon#read 5, iclass 40, count 0 2006.252.08:17:29.14#ibcon#about to read 6, iclass 40, count 0 2006.252.08:17:29.14#ibcon#read 6, iclass 40, count 0 2006.252.08:17:29.14#ibcon#end of sib2, iclass 40, count 0 2006.252.08:17:29.14#ibcon#*after write, iclass 40, count 0 2006.252.08:17:29.14#ibcon#*before return 0, iclass 40, count 0 2006.252.08:17:29.14#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.252.08:17:29.14#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.252.08:17:29.14#ibcon#about to clear, iclass 40 cls_cnt 0 2006.252.08:17:29.14#ibcon#cleared, iclass 40 cls_cnt 0 2006.252.08:17:29.14$vc4f8/va=4,7 2006.252.08:17:29.14#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.252.08:17:29.14#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.252.08:17:29.14#ibcon#ireg 11 cls_cnt 2 2006.252.08:17:29.15#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.252.08:17:29.21#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.252.08:17:29.21#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.252.08:17:29.21#ibcon#enter wrdev, iclass 4, count 2 2006.252.08:17:29.21#ibcon#first serial, iclass 4, count 2 2006.252.08:17:29.21#ibcon#enter sib2, iclass 4, count 2 2006.252.08:17:29.21#ibcon#flushed, iclass 4, count 2 2006.252.08:17:29.21#ibcon#about to write, iclass 4, count 2 2006.252.08:17:29.21#ibcon#wrote, iclass 4, count 2 2006.252.08:17:29.21#ibcon#about to read 3, iclass 4, count 2 2006.252.08:17:29.23#ibcon#read 3, iclass 4, count 2 2006.252.08:17:29.23#ibcon#about to read 4, iclass 4, count 2 2006.252.08:17:29.23#ibcon#read 4, iclass 4, count 2 2006.252.08:17:29.23#ibcon#about to read 5, iclass 4, count 2 2006.252.08:17:29.23#ibcon#read 5, iclass 4, count 2 2006.252.08:17:29.23#ibcon#about to read 6, iclass 4, count 2 2006.252.08:17:29.23#ibcon#read 6, iclass 4, count 2 2006.252.08:17:29.23#ibcon#end of sib2, iclass 4, count 2 2006.252.08:17:29.23#ibcon#*mode == 0, iclass 4, count 2 2006.252.08:17:29.23#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.252.08:17:29.23#ibcon#[25=AT04-07\r\n] 2006.252.08:17:29.23#ibcon#*before write, iclass 4, count 2 2006.252.08:17:29.23#ibcon#enter sib2, iclass 4, count 2 2006.252.08:17:29.23#ibcon#flushed, iclass 4, count 2 2006.252.08:17:29.23#ibcon#about to write, iclass 4, count 2 2006.252.08:17:29.23#ibcon#wrote, iclass 4, count 2 2006.252.08:17:29.23#ibcon#about to read 3, iclass 4, count 2 2006.252.08:17:29.26#ibcon#read 3, iclass 4, count 2 2006.252.08:17:29.26#ibcon#about to read 4, iclass 4, count 2 2006.252.08:17:29.26#ibcon#read 4, iclass 4, count 2 2006.252.08:17:29.26#ibcon#about to read 5, iclass 4, count 2 2006.252.08:17:29.26#ibcon#read 5, iclass 4, count 2 2006.252.08:17:29.26#ibcon#about to read 6, iclass 4, count 2 2006.252.08:17:29.26#ibcon#read 6, iclass 4, count 2 2006.252.08:17:29.26#ibcon#end of sib2, iclass 4, count 2 2006.252.08:17:29.26#ibcon#*after write, iclass 4, count 2 2006.252.08:17:29.26#ibcon#*before return 0, iclass 4, count 2 2006.252.08:17:29.26#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.252.08:17:29.26#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.252.08:17:29.26#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.252.08:17:29.26#ibcon#ireg 7 cls_cnt 0 2006.252.08:17:29.26#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.252.08:17:29.38#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.252.08:17:29.38#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.252.08:17:29.38#ibcon#enter wrdev, iclass 4, count 0 2006.252.08:17:29.38#ibcon#first serial, iclass 4, count 0 2006.252.08:17:29.38#ibcon#enter sib2, iclass 4, count 0 2006.252.08:17:29.38#ibcon#flushed, iclass 4, count 0 2006.252.08:17:29.38#ibcon#about to write, iclass 4, count 0 2006.252.08:17:29.38#ibcon#wrote, iclass 4, count 0 2006.252.08:17:29.38#ibcon#about to read 3, iclass 4, count 0 2006.252.08:17:29.40#ibcon#read 3, iclass 4, count 0 2006.252.08:17:29.40#ibcon#about to read 4, iclass 4, count 0 2006.252.08:17:29.40#ibcon#read 4, iclass 4, count 0 2006.252.08:17:29.40#ibcon#about to read 5, iclass 4, count 0 2006.252.08:17:29.40#ibcon#read 5, iclass 4, count 0 2006.252.08:17:29.40#ibcon#about to read 6, iclass 4, count 0 2006.252.08:17:29.40#ibcon#read 6, iclass 4, count 0 2006.252.08:17:29.40#ibcon#end of sib2, iclass 4, count 0 2006.252.08:17:29.40#ibcon#*mode == 0, iclass 4, count 0 2006.252.08:17:29.40#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.252.08:17:29.40#ibcon#[25=USB\r\n] 2006.252.08:17:29.40#ibcon#*before write, iclass 4, count 0 2006.252.08:17:29.40#ibcon#enter sib2, iclass 4, count 0 2006.252.08:17:29.40#ibcon#flushed, iclass 4, count 0 2006.252.08:17:29.40#ibcon#about to write, iclass 4, count 0 2006.252.08:17:29.40#ibcon#wrote, iclass 4, count 0 2006.252.08:17:29.40#ibcon#about to read 3, iclass 4, count 0 2006.252.08:17:29.43#ibcon#read 3, iclass 4, count 0 2006.252.08:17:29.43#ibcon#about to read 4, iclass 4, count 0 2006.252.08:17:29.43#ibcon#read 4, iclass 4, count 0 2006.252.08:17:29.43#ibcon#about to read 5, iclass 4, count 0 2006.252.08:17:29.43#ibcon#read 5, iclass 4, count 0 2006.252.08:17:29.43#ibcon#about to read 6, iclass 4, count 0 2006.252.08:17:29.43#ibcon#read 6, iclass 4, count 0 2006.252.08:17:29.43#ibcon#end of sib2, iclass 4, count 0 2006.252.08:17:29.43#ibcon#*after write, iclass 4, count 0 2006.252.08:17:29.43#ibcon#*before return 0, iclass 4, count 0 2006.252.08:17:29.43#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.252.08:17:29.43#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.252.08:17:29.43#ibcon#about to clear, iclass 4 cls_cnt 0 2006.252.08:17:29.43#ibcon#cleared, iclass 4 cls_cnt 0 2006.252.08:17:29.43$vc4f8/valo=5,652.99 2006.252.08:17:29.43#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.252.08:17:29.43#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.252.08:17:29.43#ibcon#ireg 17 cls_cnt 0 2006.252.08:17:29.43#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.252.08:17:29.43#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.252.08:17:29.43#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.252.08:17:29.43#ibcon#enter wrdev, iclass 6, count 0 2006.252.08:17:29.43#ibcon#first serial, iclass 6, count 0 2006.252.08:17:29.43#ibcon#enter sib2, iclass 6, count 0 2006.252.08:17:29.43#ibcon#flushed, iclass 6, count 0 2006.252.08:17:29.43#ibcon#about to write, iclass 6, count 0 2006.252.08:17:29.43#ibcon#wrote, iclass 6, count 0 2006.252.08:17:29.43#ibcon#about to read 3, iclass 6, count 0 2006.252.08:17:29.45#ibcon#read 3, iclass 6, count 0 2006.252.08:17:29.45#ibcon#about to read 4, iclass 6, count 0 2006.252.08:17:29.45#ibcon#read 4, iclass 6, count 0 2006.252.08:17:29.45#ibcon#about to read 5, iclass 6, count 0 2006.252.08:17:29.45#ibcon#read 5, iclass 6, count 0 2006.252.08:17:29.45#ibcon#about to read 6, iclass 6, count 0 2006.252.08:17:29.45#ibcon#read 6, iclass 6, count 0 2006.252.08:17:29.45#ibcon#end of sib2, iclass 6, count 0 2006.252.08:17:29.45#ibcon#*mode == 0, iclass 6, count 0 2006.252.08:17:29.45#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.252.08:17:29.45#ibcon#[26=FRQ=05,652.99\r\n] 2006.252.08:17:29.45#ibcon#*before write, iclass 6, count 0 2006.252.08:17:29.45#ibcon#enter sib2, iclass 6, count 0 2006.252.08:17:29.45#ibcon#flushed, iclass 6, count 0 2006.252.08:17:29.45#ibcon#about to write, iclass 6, count 0 2006.252.08:17:29.45#ibcon#wrote, iclass 6, count 0 2006.252.08:17:29.45#ibcon#about to read 3, iclass 6, count 0 2006.252.08:17:29.49#ibcon#read 3, iclass 6, count 0 2006.252.08:17:29.49#ibcon#about to read 4, iclass 6, count 0 2006.252.08:17:29.49#ibcon#read 4, iclass 6, count 0 2006.252.08:17:29.49#ibcon#about to read 5, iclass 6, count 0 2006.252.08:17:29.49#ibcon#read 5, iclass 6, count 0 2006.252.08:17:29.49#ibcon#about to read 6, iclass 6, count 0 2006.252.08:17:29.49#ibcon#read 6, iclass 6, count 0 2006.252.08:17:29.49#ibcon#end of sib2, iclass 6, count 0 2006.252.08:17:29.49#ibcon#*after write, iclass 6, count 0 2006.252.08:17:29.49#ibcon#*before return 0, iclass 6, count 0 2006.252.08:17:29.49#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.252.08:17:29.49#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.252.08:17:29.49#ibcon#about to clear, iclass 6 cls_cnt 0 2006.252.08:17:29.49#ibcon#cleared, iclass 6 cls_cnt 0 2006.252.08:17:29.49$vc4f8/va=5,7 2006.252.08:17:29.49#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.252.08:17:29.49#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.252.08:17:29.49#ibcon#ireg 11 cls_cnt 2 2006.252.08:17:29.49#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.252.08:17:29.56#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.252.08:17:29.56#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.252.08:17:29.56#ibcon#enter wrdev, iclass 10, count 2 2006.252.08:17:29.56#ibcon#first serial, iclass 10, count 2 2006.252.08:17:29.56#ibcon#enter sib2, iclass 10, count 2 2006.252.08:17:29.56#ibcon#flushed, iclass 10, count 2 2006.252.08:17:29.56#ibcon#about to write, iclass 10, count 2 2006.252.08:17:29.56#ibcon#wrote, iclass 10, count 2 2006.252.08:17:29.56#ibcon#about to read 3, iclass 10, count 2 2006.252.08:17:29.57#ibcon#read 3, iclass 10, count 2 2006.252.08:17:29.57#ibcon#about to read 4, iclass 10, count 2 2006.252.08:17:29.57#ibcon#read 4, iclass 10, count 2 2006.252.08:17:29.57#ibcon#about to read 5, iclass 10, count 2 2006.252.08:17:29.57#ibcon#read 5, iclass 10, count 2 2006.252.08:17:29.57#ibcon#about to read 6, iclass 10, count 2 2006.252.08:17:29.57#ibcon#read 6, iclass 10, count 2 2006.252.08:17:29.57#ibcon#end of sib2, iclass 10, count 2 2006.252.08:17:29.57#ibcon#*mode == 0, iclass 10, count 2 2006.252.08:17:29.57#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.252.08:17:29.57#ibcon#[25=AT05-07\r\n] 2006.252.08:17:29.57#ibcon#*before write, iclass 10, count 2 2006.252.08:17:29.57#ibcon#enter sib2, iclass 10, count 2 2006.252.08:17:29.57#ibcon#flushed, iclass 10, count 2 2006.252.08:17:29.57#ibcon#about to write, iclass 10, count 2 2006.252.08:17:29.57#ibcon#wrote, iclass 10, count 2 2006.252.08:17:29.57#ibcon#about to read 3, iclass 10, count 2 2006.252.08:17:29.60#ibcon#read 3, iclass 10, count 2 2006.252.08:17:29.60#ibcon#about to read 4, iclass 10, count 2 2006.252.08:17:29.60#ibcon#read 4, iclass 10, count 2 2006.252.08:17:29.60#ibcon#about to read 5, iclass 10, count 2 2006.252.08:17:29.60#ibcon#read 5, iclass 10, count 2 2006.252.08:17:29.60#ibcon#about to read 6, iclass 10, count 2 2006.252.08:17:29.60#ibcon#read 6, iclass 10, count 2 2006.252.08:17:29.60#ibcon#end of sib2, iclass 10, count 2 2006.252.08:17:29.60#ibcon#*after write, iclass 10, count 2 2006.252.08:17:29.60#ibcon#*before return 0, iclass 10, count 2 2006.252.08:17:29.60#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.252.08:17:29.60#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.252.08:17:29.60#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.252.08:17:29.60#ibcon#ireg 7 cls_cnt 0 2006.252.08:17:29.60#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.252.08:17:29.72#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.252.08:17:29.72#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.252.08:17:29.72#ibcon#enter wrdev, iclass 10, count 0 2006.252.08:17:29.72#ibcon#first serial, iclass 10, count 0 2006.252.08:17:29.72#ibcon#enter sib2, iclass 10, count 0 2006.252.08:17:29.72#ibcon#flushed, iclass 10, count 0 2006.252.08:17:29.72#ibcon#about to write, iclass 10, count 0 2006.252.08:17:29.72#ibcon#wrote, iclass 10, count 0 2006.252.08:17:29.72#ibcon#about to read 3, iclass 10, count 0 2006.252.08:17:29.74#ibcon#read 3, iclass 10, count 0 2006.252.08:17:29.74#ibcon#about to read 4, iclass 10, count 0 2006.252.08:17:29.74#ibcon#read 4, iclass 10, count 0 2006.252.08:17:29.74#ibcon#about to read 5, iclass 10, count 0 2006.252.08:17:29.74#ibcon#read 5, iclass 10, count 0 2006.252.08:17:29.74#ibcon#about to read 6, iclass 10, count 0 2006.252.08:17:29.74#ibcon#read 6, iclass 10, count 0 2006.252.08:17:29.74#ibcon#end of sib2, iclass 10, count 0 2006.252.08:17:29.74#ibcon#*mode == 0, iclass 10, count 0 2006.252.08:17:29.74#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.252.08:17:29.74#ibcon#[25=USB\r\n] 2006.252.08:17:29.74#ibcon#*before write, iclass 10, count 0 2006.252.08:17:29.74#ibcon#enter sib2, iclass 10, count 0 2006.252.08:17:29.74#ibcon#flushed, iclass 10, count 0 2006.252.08:17:29.74#ibcon#about to write, iclass 10, count 0 2006.252.08:17:29.74#ibcon#wrote, iclass 10, count 0 2006.252.08:17:29.74#ibcon#about to read 3, iclass 10, count 0 2006.252.08:17:29.77#ibcon#read 3, iclass 10, count 0 2006.252.08:17:29.77#ibcon#about to read 4, iclass 10, count 0 2006.252.08:17:29.77#ibcon#read 4, iclass 10, count 0 2006.252.08:17:29.77#ibcon#about to read 5, iclass 10, count 0 2006.252.08:17:29.77#ibcon#read 5, iclass 10, count 0 2006.252.08:17:29.77#ibcon#about to read 6, iclass 10, count 0 2006.252.08:17:29.77#ibcon#read 6, iclass 10, count 0 2006.252.08:17:29.77#ibcon#end of sib2, iclass 10, count 0 2006.252.08:17:29.77#ibcon#*after write, iclass 10, count 0 2006.252.08:17:29.77#ibcon#*before return 0, iclass 10, count 0 2006.252.08:17:29.77#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.252.08:17:29.77#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.252.08:17:29.77#ibcon#about to clear, iclass 10 cls_cnt 0 2006.252.08:17:29.77#ibcon#cleared, iclass 10 cls_cnt 0 2006.252.08:17:29.77$vc4f8/valo=6,772.99 2006.252.08:17:29.77#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.252.08:17:29.77#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.252.08:17:29.77#ibcon#ireg 17 cls_cnt 0 2006.252.08:17:29.77#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.252.08:17:29.77#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.252.08:17:29.77#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.252.08:17:29.77#ibcon#enter wrdev, iclass 12, count 0 2006.252.08:17:29.77#ibcon#first serial, iclass 12, count 0 2006.252.08:17:29.77#ibcon#enter sib2, iclass 12, count 0 2006.252.08:17:29.77#ibcon#flushed, iclass 12, count 0 2006.252.08:17:29.77#ibcon#about to write, iclass 12, count 0 2006.252.08:17:29.77#ibcon#wrote, iclass 12, count 0 2006.252.08:17:29.77#ibcon#about to read 3, iclass 12, count 0 2006.252.08:17:29.80#ibcon#read 3, iclass 12, count 0 2006.252.08:17:29.80#ibcon#about to read 4, iclass 12, count 0 2006.252.08:17:29.80#ibcon#read 4, iclass 12, count 0 2006.252.08:17:29.80#ibcon#about to read 5, iclass 12, count 0 2006.252.08:17:29.80#ibcon#read 5, iclass 12, count 0 2006.252.08:17:29.80#ibcon#about to read 6, iclass 12, count 0 2006.252.08:17:29.80#ibcon#read 6, iclass 12, count 0 2006.252.08:17:29.80#ibcon#end of sib2, iclass 12, count 0 2006.252.08:17:29.80#ibcon#*mode == 0, iclass 12, count 0 2006.252.08:17:29.80#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.252.08:17:29.80#ibcon#[26=FRQ=06,772.99\r\n] 2006.252.08:17:29.80#ibcon#*before write, iclass 12, count 0 2006.252.08:17:29.80#ibcon#enter sib2, iclass 12, count 0 2006.252.08:17:29.80#ibcon#flushed, iclass 12, count 0 2006.252.08:17:29.80#ibcon#about to write, iclass 12, count 0 2006.252.08:17:29.80#ibcon#wrote, iclass 12, count 0 2006.252.08:17:29.80#ibcon#about to read 3, iclass 12, count 0 2006.252.08:17:29.84#ibcon#read 3, iclass 12, count 0 2006.252.08:17:29.84#ibcon#about to read 4, iclass 12, count 0 2006.252.08:17:29.84#ibcon#read 4, iclass 12, count 0 2006.252.08:17:29.84#ibcon#about to read 5, iclass 12, count 0 2006.252.08:17:29.84#ibcon#read 5, iclass 12, count 0 2006.252.08:17:29.84#ibcon#about to read 6, iclass 12, count 0 2006.252.08:17:29.84#ibcon#read 6, iclass 12, count 0 2006.252.08:17:29.84#ibcon#end of sib2, iclass 12, count 0 2006.252.08:17:29.84#ibcon#*after write, iclass 12, count 0 2006.252.08:17:29.84#ibcon#*before return 0, iclass 12, count 0 2006.252.08:17:29.84#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.252.08:17:29.84#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.252.08:17:29.84#ibcon#about to clear, iclass 12 cls_cnt 0 2006.252.08:17:29.84#ibcon#cleared, iclass 12 cls_cnt 0 2006.252.08:17:29.84$vc4f8/va=6,7 2006.252.08:17:29.84#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.252.08:17:29.84#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.252.08:17:29.84#ibcon#ireg 11 cls_cnt 2 2006.252.08:17:29.84#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.252.08:17:29.90#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.252.08:17:29.90#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.252.08:17:29.90#ibcon#enter wrdev, iclass 14, count 2 2006.252.08:17:29.90#ibcon#first serial, iclass 14, count 2 2006.252.08:17:29.90#ibcon#enter sib2, iclass 14, count 2 2006.252.08:17:29.90#ibcon#flushed, iclass 14, count 2 2006.252.08:17:29.90#ibcon#about to write, iclass 14, count 2 2006.252.08:17:29.90#ibcon#wrote, iclass 14, count 2 2006.252.08:17:29.90#ibcon#about to read 3, iclass 14, count 2 2006.252.08:17:29.91#ibcon#read 3, iclass 14, count 2 2006.252.08:17:29.91#ibcon#about to read 4, iclass 14, count 2 2006.252.08:17:29.91#ibcon#read 4, iclass 14, count 2 2006.252.08:17:29.91#ibcon#about to read 5, iclass 14, count 2 2006.252.08:17:29.91#ibcon#read 5, iclass 14, count 2 2006.252.08:17:29.91#ibcon#about to read 6, iclass 14, count 2 2006.252.08:17:29.91#ibcon#read 6, iclass 14, count 2 2006.252.08:17:29.91#ibcon#end of sib2, iclass 14, count 2 2006.252.08:17:29.91#ibcon#*mode == 0, iclass 14, count 2 2006.252.08:17:29.91#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.252.08:17:29.91#ibcon#[25=AT06-07\r\n] 2006.252.08:17:29.91#ibcon#*before write, iclass 14, count 2 2006.252.08:17:29.91#ibcon#enter sib2, iclass 14, count 2 2006.252.08:17:29.91#ibcon#flushed, iclass 14, count 2 2006.252.08:17:29.91#ibcon#about to write, iclass 14, count 2 2006.252.08:17:29.91#ibcon#wrote, iclass 14, count 2 2006.252.08:17:29.91#ibcon#about to read 3, iclass 14, count 2 2006.252.08:17:29.94#ibcon#read 3, iclass 14, count 2 2006.252.08:17:29.94#ibcon#about to read 4, iclass 14, count 2 2006.252.08:17:29.94#ibcon#read 4, iclass 14, count 2 2006.252.08:17:29.94#ibcon#about to read 5, iclass 14, count 2 2006.252.08:17:29.94#ibcon#read 5, iclass 14, count 2 2006.252.08:17:29.94#ibcon#about to read 6, iclass 14, count 2 2006.252.08:17:29.94#ibcon#read 6, iclass 14, count 2 2006.252.08:17:29.94#ibcon#end of sib2, iclass 14, count 2 2006.252.08:17:29.94#ibcon#*after write, iclass 14, count 2 2006.252.08:17:29.94#ibcon#*before return 0, iclass 14, count 2 2006.252.08:17:29.94#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.252.08:17:29.94#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.252.08:17:29.94#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.252.08:17:29.94#ibcon#ireg 7 cls_cnt 0 2006.252.08:17:29.94#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.252.08:17:30.06#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.252.08:17:30.06#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.252.08:17:30.06#ibcon#enter wrdev, iclass 14, count 0 2006.252.08:17:30.06#ibcon#first serial, iclass 14, count 0 2006.252.08:17:30.06#ibcon#enter sib2, iclass 14, count 0 2006.252.08:17:30.06#ibcon#flushed, iclass 14, count 0 2006.252.08:17:30.06#ibcon#about to write, iclass 14, count 0 2006.252.08:17:30.06#ibcon#wrote, iclass 14, count 0 2006.252.08:17:30.06#ibcon#about to read 3, iclass 14, count 0 2006.252.08:17:30.08#ibcon#read 3, iclass 14, count 0 2006.252.08:17:30.08#ibcon#about to read 4, iclass 14, count 0 2006.252.08:17:30.08#ibcon#read 4, iclass 14, count 0 2006.252.08:17:30.08#ibcon#about to read 5, iclass 14, count 0 2006.252.08:17:30.08#ibcon#read 5, iclass 14, count 0 2006.252.08:17:30.08#ibcon#about to read 6, iclass 14, count 0 2006.252.08:17:30.08#ibcon#read 6, iclass 14, count 0 2006.252.08:17:30.08#ibcon#end of sib2, iclass 14, count 0 2006.252.08:17:30.08#ibcon#*mode == 0, iclass 14, count 0 2006.252.08:17:30.08#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.252.08:17:30.08#ibcon#[25=USB\r\n] 2006.252.08:17:30.08#ibcon#*before write, iclass 14, count 0 2006.252.08:17:30.08#ibcon#enter sib2, iclass 14, count 0 2006.252.08:17:30.08#ibcon#flushed, iclass 14, count 0 2006.252.08:17:30.08#ibcon#about to write, iclass 14, count 0 2006.252.08:17:30.08#ibcon#wrote, iclass 14, count 0 2006.252.08:17:30.08#ibcon#about to read 3, iclass 14, count 0 2006.252.08:17:30.11#ibcon#read 3, iclass 14, count 0 2006.252.08:17:30.11#ibcon#about to read 4, iclass 14, count 0 2006.252.08:17:30.11#ibcon#read 4, iclass 14, count 0 2006.252.08:17:30.11#ibcon#about to read 5, iclass 14, count 0 2006.252.08:17:30.11#ibcon#read 5, iclass 14, count 0 2006.252.08:17:30.11#ibcon#about to read 6, iclass 14, count 0 2006.252.08:17:30.11#ibcon#read 6, iclass 14, count 0 2006.252.08:17:30.11#ibcon#end of sib2, iclass 14, count 0 2006.252.08:17:30.11#ibcon#*after write, iclass 14, count 0 2006.252.08:17:30.11#ibcon#*before return 0, iclass 14, count 0 2006.252.08:17:30.11#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.252.08:17:30.11#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.252.08:17:30.11#ibcon#about to clear, iclass 14 cls_cnt 0 2006.252.08:17:30.11#ibcon#cleared, iclass 14 cls_cnt 0 2006.252.08:17:30.11$vc4f8/valo=7,832.99 2006.252.08:17:30.11#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.252.08:17:30.11#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.252.08:17:30.11#ibcon#ireg 17 cls_cnt 0 2006.252.08:17:30.11#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.252.08:17:30.11#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.252.08:17:30.11#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.252.08:17:30.11#ibcon#enter wrdev, iclass 16, count 0 2006.252.08:17:30.11#ibcon#first serial, iclass 16, count 0 2006.252.08:17:30.11#ibcon#enter sib2, iclass 16, count 0 2006.252.08:17:30.11#ibcon#flushed, iclass 16, count 0 2006.252.08:17:30.11#ibcon#about to write, iclass 16, count 0 2006.252.08:17:30.11#ibcon#wrote, iclass 16, count 0 2006.252.08:17:30.11#ibcon#about to read 3, iclass 16, count 0 2006.252.08:17:30.13#ibcon#read 3, iclass 16, count 0 2006.252.08:17:30.13#ibcon#about to read 4, iclass 16, count 0 2006.252.08:17:30.13#ibcon#read 4, iclass 16, count 0 2006.252.08:17:30.13#ibcon#about to read 5, iclass 16, count 0 2006.252.08:17:30.13#ibcon#read 5, iclass 16, count 0 2006.252.08:17:30.13#ibcon#about to read 6, iclass 16, count 0 2006.252.08:17:30.13#ibcon#read 6, iclass 16, count 0 2006.252.08:17:30.13#ibcon#end of sib2, iclass 16, count 0 2006.252.08:17:30.13#ibcon#*mode == 0, iclass 16, count 0 2006.252.08:17:30.13#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.252.08:17:30.13#ibcon#[26=FRQ=07,832.99\r\n] 2006.252.08:17:30.13#ibcon#*before write, iclass 16, count 0 2006.252.08:17:30.13#ibcon#enter sib2, iclass 16, count 0 2006.252.08:17:30.13#ibcon#flushed, iclass 16, count 0 2006.252.08:17:30.13#ibcon#about to write, iclass 16, count 0 2006.252.08:17:30.13#ibcon#wrote, iclass 16, count 0 2006.252.08:17:30.13#ibcon#about to read 3, iclass 16, count 0 2006.252.08:17:30.17#ibcon#read 3, iclass 16, count 0 2006.252.08:17:30.17#ibcon#about to read 4, iclass 16, count 0 2006.252.08:17:30.17#ibcon#read 4, iclass 16, count 0 2006.252.08:17:30.17#ibcon#about to read 5, iclass 16, count 0 2006.252.08:17:30.17#ibcon#read 5, iclass 16, count 0 2006.252.08:17:30.17#ibcon#about to read 6, iclass 16, count 0 2006.252.08:17:30.17#ibcon#read 6, iclass 16, count 0 2006.252.08:17:30.17#ibcon#end of sib2, iclass 16, count 0 2006.252.08:17:30.17#ibcon#*after write, iclass 16, count 0 2006.252.08:17:30.17#ibcon#*before return 0, iclass 16, count 0 2006.252.08:17:30.17#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.252.08:17:30.17#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.252.08:17:30.17#ibcon#about to clear, iclass 16 cls_cnt 0 2006.252.08:17:30.17#ibcon#cleared, iclass 16 cls_cnt 0 2006.252.08:17:30.17$vc4f8/va=7,7 2006.252.08:17:30.17#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.252.08:17:30.17#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.252.08:17:30.17#ibcon#ireg 11 cls_cnt 2 2006.252.08:17:30.17#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.252.08:17:30.23#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.252.08:17:30.23#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.252.08:17:30.23#ibcon#enter wrdev, iclass 18, count 2 2006.252.08:17:30.23#ibcon#first serial, iclass 18, count 2 2006.252.08:17:30.23#ibcon#enter sib2, iclass 18, count 2 2006.252.08:17:30.23#ibcon#flushed, iclass 18, count 2 2006.252.08:17:30.23#ibcon#about to write, iclass 18, count 2 2006.252.08:17:30.23#ibcon#wrote, iclass 18, count 2 2006.252.08:17:30.23#ibcon#about to read 3, iclass 18, count 2 2006.252.08:17:30.25#ibcon#read 3, iclass 18, count 2 2006.252.08:17:30.25#ibcon#about to read 4, iclass 18, count 2 2006.252.08:17:30.25#ibcon#read 4, iclass 18, count 2 2006.252.08:17:30.25#ibcon#about to read 5, iclass 18, count 2 2006.252.08:17:30.25#ibcon#read 5, iclass 18, count 2 2006.252.08:17:30.25#ibcon#about to read 6, iclass 18, count 2 2006.252.08:17:30.25#ibcon#read 6, iclass 18, count 2 2006.252.08:17:30.25#ibcon#end of sib2, iclass 18, count 2 2006.252.08:17:30.25#ibcon#*mode == 0, iclass 18, count 2 2006.252.08:17:30.25#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.252.08:17:30.25#ibcon#[25=AT07-07\r\n] 2006.252.08:17:30.25#ibcon#*before write, iclass 18, count 2 2006.252.08:17:30.25#ibcon#enter sib2, iclass 18, count 2 2006.252.08:17:30.25#ibcon#flushed, iclass 18, count 2 2006.252.08:17:30.25#ibcon#about to write, iclass 18, count 2 2006.252.08:17:30.25#ibcon#wrote, iclass 18, count 2 2006.252.08:17:30.25#ibcon#about to read 3, iclass 18, count 2 2006.252.08:17:30.28#ibcon#read 3, iclass 18, count 2 2006.252.08:17:30.28#ibcon#about to read 4, iclass 18, count 2 2006.252.08:17:30.28#ibcon#read 4, iclass 18, count 2 2006.252.08:17:30.28#ibcon#about to read 5, iclass 18, count 2 2006.252.08:17:30.28#ibcon#read 5, iclass 18, count 2 2006.252.08:17:30.28#ibcon#about to read 6, iclass 18, count 2 2006.252.08:17:30.28#ibcon#read 6, iclass 18, count 2 2006.252.08:17:30.28#ibcon#end of sib2, iclass 18, count 2 2006.252.08:17:30.28#ibcon#*after write, iclass 18, count 2 2006.252.08:17:30.28#ibcon#*before return 0, iclass 18, count 2 2006.252.08:17:30.28#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.252.08:17:30.28#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.252.08:17:30.28#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.252.08:17:30.28#ibcon#ireg 7 cls_cnt 0 2006.252.08:17:30.28#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.252.08:17:30.40#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.252.08:17:30.40#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.252.08:17:30.40#ibcon#enter wrdev, iclass 18, count 0 2006.252.08:17:30.40#ibcon#first serial, iclass 18, count 0 2006.252.08:17:30.40#ibcon#enter sib2, iclass 18, count 0 2006.252.08:17:30.40#ibcon#flushed, iclass 18, count 0 2006.252.08:17:30.40#ibcon#about to write, iclass 18, count 0 2006.252.08:17:30.40#ibcon#wrote, iclass 18, count 0 2006.252.08:17:30.40#ibcon#about to read 3, iclass 18, count 0 2006.252.08:17:30.42#ibcon#read 3, iclass 18, count 0 2006.252.08:17:30.42#ibcon#about to read 4, iclass 18, count 0 2006.252.08:17:30.42#ibcon#read 4, iclass 18, count 0 2006.252.08:17:30.42#ibcon#about to read 5, iclass 18, count 0 2006.252.08:17:30.42#ibcon#read 5, iclass 18, count 0 2006.252.08:17:30.42#ibcon#about to read 6, iclass 18, count 0 2006.252.08:17:30.42#ibcon#read 6, iclass 18, count 0 2006.252.08:17:30.42#ibcon#end of sib2, iclass 18, count 0 2006.252.08:17:30.42#ibcon#*mode == 0, iclass 18, count 0 2006.252.08:17:30.42#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.252.08:17:30.42#ibcon#[25=USB\r\n] 2006.252.08:17:30.42#ibcon#*before write, iclass 18, count 0 2006.252.08:17:30.42#ibcon#enter sib2, iclass 18, count 0 2006.252.08:17:30.42#ibcon#flushed, iclass 18, count 0 2006.252.08:17:30.42#ibcon#about to write, iclass 18, count 0 2006.252.08:17:30.42#ibcon#wrote, iclass 18, count 0 2006.252.08:17:30.42#ibcon#about to read 3, iclass 18, count 0 2006.252.08:17:30.45#ibcon#read 3, iclass 18, count 0 2006.252.08:17:30.45#ibcon#about to read 4, iclass 18, count 0 2006.252.08:17:30.45#ibcon#read 4, iclass 18, count 0 2006.252.08:17:30.45#ibcon#about to read 5, iclass 18, count 0 2006.252.08:17:30.45#ibcon#read 5, iclass 18, count 0 2006.252.08:17:30.45#ibcon#about to read 6, iclass 18, count 0 2006.252.08:17:30.45#ibcon#read 6, iclass 18, count 0 2006.252.08:17:30.45#ibcon#end of sib2, iclass 18, count 0 2006.252.08:17:30.45#ibcon#*after write, iclass 18, count 0 2006.252.08:17:30.45#ibcon#*before return 0, iclass 18, count 0 2006.252.08:17:30.45#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.252.08:17:30.45#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.252.08:17:30.45#ibcon#about to clear, iclass 18 cls_cnt 0 2006.252.08:17:30.45#ibcon#cleared, iclass 18 cls_cnt 0 2006.252.08:17:30.45$vc4f8/valo=8,852.99 2006.252.08:17:30.45#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.252.08:17:30.45#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.252.08:17:30.45#ibcon#ireg 17 cls_cnt 0 2006.252.08:17:30.45#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.252.08:17:30.45#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.252.08:17:30.45#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.252.08:17:30.45#ibcon#enter wrdev, iclass 20, count 0 2006.252.08:17:30.45#ibcon#first serial, iclass 20, count 0 2006.252.08:17:30.45#ibcon#enter sib2, iclass 20, count 0 2006.252.08:17:30.45#ibcon#flushed, iclass 20, count 0 2006.252.08:17:30.45#ibcon#about to write, iclass 20, count 0 2006.252.08:17:30.45#ibcon#wrote, iclass 20, count 0 2006.252.08:17:30.45#ibcon#about to read 3, iclass 20, count 0 2006.252.08:17:30.48#ibcon#read 3, iclass 20, count 0 2006.252.08:17:30.48#ibcon#about to read 4, iclass 20, count 0 2006.252.08:17:30.48#ibcon#read 4, iclass 20, count 0 2006.252.08:17:30.48#ibcon#about to read 5, iclass 20, count 0 2006.252.08:17:30.48#ibcon#read 5, iclass 20, count 0 2006.252.08:17:30.48#ibcon#about to read 6, iclass 20, count 0 2006.252.08:17:30.48#ibcon#read 6, iclass 20, count 0 2006.252.08:17:30.48#ibcon#end of sib2, iclass 20, count 0 2006.252.08:17:30.48#ibcon#*mode == 0, iclass 20, count 0 2006.252.08:17:30.48#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.252.08:17:30.48#ibcon#[26=FRQ=08,852.99\r\n] 2006.252.08:17:30.48#ibcon#*before write, iclass 20, count 0 2006.252.08:17:30.48#ibcon#enter sib2, iclass 20, count 0 2006.252.08:17:30.48#ibcon#flushed, iclass 20, count 0 2006.252.08:17:30.48#ibcon#about to write, iclass 20, count 0 2006.252.08:17:30.48#ibcon#wrote, iclass 20, count 0 2006.252.08:17:30.48#ibcon#about to read 3, iclass 20, count 0 2006.252.08:17:30.52#ibcon#read 3, iclass 20, count 0 2006.252.08:17:30.52#ibcon#about to read 4, iclass 20, count 0 2006.252.08:17:30.52#ibcon#read 4, iclass 20, count 0 2006.252.08:17:30.52#ibcon#about to read 5, iclass 20, count 0 2006.252.08:17:30.52#ibcon#read 5, iclass 20, count 0 2006.252.08:17:30.52#ibcon#about to read 6, iclass 20, count 0 2006.252.08:17:30.52#ibcon#read 6, iclass 20, count 0 2006.252.08:17:30.52#ibcon#end of sib2, iclass 20, count 0 2006.252.08:17:30.52#ibcon#*after write, iclass 20, count 0 2006.252.08:17:30.52#ibcon#*before return 0, iclass 20, count 0 2006.252.08:17:30.52#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.252.08:17:30.52#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.252.08:17:30.52#ibcon#about to clear, iclass 20 cls_cnt 0 2006.252.08:17:30.52#ibcon#cleared, iclass 20 cls_cnt 0 2006.252.08:17:30.52$vc4f8/va=8,7 2006.252.08:17:30.52#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.252.08:17:30.52#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.252.08:17:30.52#ibcon#ireg 11 cls_cnt 2 2006.252.08:17:30.52#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.252.08:17:30.58#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.252.08:17:30.58#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.252.08:17:30.58#ibcon#enter wrdev, iclass 22, count 2 2006.252.08:17:30.58#ibcon#first serial, iclass 22, count 2 2006.252.08:17:30.58#ibcon#enter sib2, iclass 22, count 2 2006.252.08:17:30.58#ibcon#flushed, iclass 22, count 2 2006.252.08:17:30.58#ibcon#about to write, iclass 22, count 2 2006.252.08:17:30.58#ibcon#wrote, iclass 22, count 2 2006.252.08:17:30.58#ibcon#about to read 3, iclass 22, count 2 2006.252.08:17:30.59#ibcon#read 3, iclass 22, count 2 2006.252.08:17:30.59#ibcon#about to read 4, iclass 22, count 2 2006.252.08:17:30.59#ibcon#read 4, iclass 22, count 2 2006.252.08:17:30.59#ibcon#about to read 5, iclass 22, count 2 2006.252.08:17:30.59#ibcon#read 5, iclass 22, count 2 2006.252.08:17:30.59#ibcon#about to read 6, iclass 22, count 2 2006.252.08:17:30.59#ibcon#read 6, iclass 22, count 2 2006.252.08:17:30.59#ibcon#end of sib2, iclass 22, count 2 2006.252.08:17:30.59#ibcon#*mode == 0, iclass 22, count 2 2006.252.08:17:30.59#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.252.08:17:30.59#ibcon#[25=AT08-07\r\n] 2006.252.08:17:30.59#ibcon#*before write, iclass 22, count 2 2006.252.08:17:30.59#ibcon#enter sib2, iclass 22, count 2 2006.252.08:17:30.59#ibcon#flushed, iclass 22, count 2 2006.252.08:17:30.59#ibcon#about to write, iclass 22, count 2 2006.252.08:17:30.59#ibcon#wrote, iclass 22, count 2 2006.252.08:17:30.59#ibcon#about to read 3, iclass 22, count 2 2006.252.08:17:30.62#ibcon#read 3, iclass 22, count 2 2006.252.08:17:30.62#ibcon#about to read 4, iclass 22, count 2 2006.252.08:17:30.62#ibcon#read 4, iclass 22, count 2 2006.252.08:17:30.62#ibcon#about to read 5, iclass 22, count 2 2006.252.08:17:30.62#ibcon#read 5, iclass 22, count 2 2006.252.08:17:30.62#ibcon#about to read 6, iclass 22, count 2 2006.252.08:17:30.62#ibcon#read 6, iclass 22, count 2 2006.252.08:17:30.62#ibcon#end of sib2, iclass 22, count 2 2006.252.08:17:30.62#ibcon#*after write, iclass 22, count 2 2006.252.08:17:30.62#ibcon#*before return 0, iclass 22, count 2 2006.252.08:17:30.62#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.252.08:17:30.62#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.252.08:17:30.62#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.252.08:17:30.62#ibcon#ireg 7 cls_cnt 0 2006.252.08:17:30.62#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.252.08:17:30.74#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.252.08:17:30.74#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.252.08:17:30.74#ibcon#enter wrdev, iclass 22, count 0 2006.252.08:17:30.74#ibcon#first serial, iclass 22, count 0 2006.252.08:17:30.74#ibcon#enter sib2, iclass 22, count 0 2006.252.08:17:30.74#ibcon#flushed, iclass 22, count 0 2006.252.08:17:30.74#ibcon#about to write, iclass 22, count 0 2006.252.08:17:30.74#ibcon#wrote, iclass 22, count 0 2006.252.08:17:30.74#ibcon#about to read 3, iclass 22, count 0 2006.252.08:17:30.76#ibcon#read 3, iclass 22, count 0 2006.252.08:17:30.76#ibcon#about to read 4, iclass 22, count 0 2006.252.08:17:30.76#ibcon#read 4, iclass 22, count 0 2006.252.08:17:30.76#ibcon#about to read 5, iclass 22, count 0 2006.252.08:17:30.76#ibcon#read 5, iclass 22, count 0 2006.252.08:17:30.76#ibcon#about to read 6, iclass 22, count 0 2006.252.08:17:30.76#ibcon#read 6, iclass 22, count 0 2006.252.08:17:30.76#ibcon#end of sib2, iclass 22, count 0 2006.252.08:17:30.76#ibcon#*mode == 0, iclass 22, count 0 2006.252.08:17:30.76#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.252.08:17:30.76#ibcon#[25=USB\r\n] 2006.252.08:17:30.76#ibcon#*before write, iclass 22, count 0 2006.252.08:17:30.76#ibcon#enter sib2, iclass 22, count 0 2006.252.08:17:30.76#ibcon#flushed, iclass 22, count 0 2006.252.08:17:30.76#ibcon#about to write, iclass 22, count 0 2006.252.08:17:30.76#ibcon#wrote, iclass 22, count 0 2006.252.08:17:30.76#ibcon#about to read 3, iclass 22, count 0 2006.252.08:17:30.79#ibcon#read 3, iclass 22, count 0 2006.252.08:17:30.79#ibcon#about to read 4, iclass 22, count 0 2006.252.08:17:30.79#ibcon#read 4, iclass 22, count 0 2006.252.08:17:30.79#ibcon#about to read 5, iclass 22, count 0 2006.252.08:17:30.79#ibcon#read 5, iclass 22, count 0 2006.252.08:17:30.79#ibcon#about to read 6, iclass 22, count 0 2006.252.08:17:30.79#ibcon#read 6, iclass 22, count 0 2006.252.08:17:30.79#ibcon#end of sib2, iclass 22, count 0 2006.252.08:17:30.79#ibcon#*after write, iclass 22, count 0 2006.252.08:17:30.79#ibcon#*before return 0, iclass 22, count 0 2006.252.08:17:30.79#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.252.08:17:30.79#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.252.08:17:30.79#ibcon#about to clear, iclass 22 cls_cnt 0 2006.252.08:17:30.79#ibcon#cleared, iclass 22 cls_cnt 0 2006.252.08:17:30.79$vc4f8/vblo=1,632.99 2006.252.08:17:30.79#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.252.08:17:30.79#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.252.08:17:30.79#ibcon#ireg 17 cls_cnt 0 2006.252.08:17:30.79#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.252.08:17:30.79#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.252.08:17:30.79#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.252.08:17:30.79#ibcon#enter wrdev, iclass 24, count 0 2006.252.08:17:30.79#ibcon#first serial, iclass 24, count 0 2006.252.08:17:30.79#ibcon#enter sib2, iclass 24, count 0 2006.252.08:17:30.79#ibcon#flushed, iclass 24, count 0 2006.252.08:17:30.79#ibcon#about to write, iclass 24, count 0 2006.252.08:17:30.79#ibcon#wrote, iclass 24, count 0 2006.252.08:17:30.79#ibcon#about to read 3, iclass 24, count 0 2006.252.08:17:30.81#ibcon#read 3, iclass 24, count 0 2006.252.08:17:30.81#ibcon#about to read 4, iclass 24, count 0 2006.252.08:17:30.81#ibcon#read 4, iclass 24, count 0 2006.252.08:17:30.81#ibcon#about to read 5, iclass 24, count 0 2006.252.08:17:30.81#ibcon#read 5, iclass 24, count 0 2006.252.08:17:30.81#ibcon#about to read 6, iclass 24, count 0 2006.252.08:17:30.81#ibcon#read 6, iclass 24, count 0 2006.252.08:17:30.81#ibcon#end of sib2, iclass 24, count 0 2006.252.08:17:30.81#ibcon#*mode == 0, iclass 24, count 0 2006.252.08:17:30.81#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.252.08:17:30.81#ibcon#[28=FRQ=01,632.99\r\n] 2006.252.08:17:30.81#ibcon#*before write, iclass 24, count 0 2006.252.08:17:30.81#ibcon#enter sib2, iclass 24, count 0 2006.252.08:17:30.81#ibcon#flushed, iclass 24, count 0 2006.252.08:17:30.81#ibcon#about to write, iclass 24, count 0 2006.252.08:17:30.81#ibcon#wrote, iclass 24, count 0 2006.252.08:17:30.81#ibcon#about to read 3, iclass 24, count 0 2006.252.08:17:30.85#ibcon#read 3, iclass 24, count 0 2006.252.08:17:30.85#ibcon#about to read 4, iclass 24, count 0 2006.252.08:17:30.85#ibcon#read 4, iclass 24, count 0 2006.252.08:17:30.85#ibcon#about to read 5, iclass 24, count 0 2006.252.08:17:30.85#ibcon#read 5, iclass 24, count 0 2006.252.08:17:30.85#ibcon#about to read 6, iclass 24, count 0 2006.252.08:17:30.85#ibcon#read 6, iclass 24, count 0 2006.252.08:17:30.85#ibcon#end of sib2, iclass 24, count 0 2006.252.08:17:30.85#ibcon#*after write, iclass 24, count 0 2006.252.08:17:30.85#ibcon#*before return 0, iclass 24, count 0 2006.252.08:17:30.85#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.252.08:17:30.85#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.252.08:17:30.85#ibcon#about to clear, iclass 24 cls_cnt 0 2006.252.08:17:30.85#ibcon#cleared, iclass 24 cls_cnt 0 2006.252.08:17:30.85$vc4f8/vb=1,4 2006.252.08:17:30.85#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.252.08:17:30.85#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.252.08:17:30.85#ibcon#ireg 11 cls_cnt 2 2006.252.08:17:30.85#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.252.08:17:30.85#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.252.08:17:30.85#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.252.08:17:30.85#ibcon#enter wrdev, iclass 26, count 2 2006.252.08:17:30.85#ibcon#first serial, iclass 26, count 2 2006.252.08:17:30.85#ibcon#enter sib2, iclass 26, count 2 2006.252.08:17:30.85#ibcon#flushed, iclass 26, count 2 2006.252.08:17:30.85#ibcon#about to write, iclass 26, count 2 2006.252.08:17:30.85#ibcon#wrote, iclass 26, count 2 2006.252.08:17:30.85#ibcon#about to read 3, iclass 26, count 2 2006.252.08:17:30.87#ibcon#read 3, iclass 26, count 2 2006.252.08:17:30.87#ibcon#about to read 4, iclass 26, count 2 2006.252.08:17:30.87#ibcon#read 4, iclass 26, count 2 2006.252.08:17:30.87#ibcon#about to read 5, iclass 26, count 2 2006.252.08:17:30.87#ibcon#read 5, iclass 26, count 2 2006.252.08:17:30.87#ibcon#about to read 6, iclass 26, count 2 2006.252.08:17:30.87#ibcon#read 6, iclass 26, count 2 2006.252.08:17:30.87#ibcon#end of sib2, iclass 26, count 2 2006.252.08:17:30.87#ibcon#*mode == 0, iclass 26, count 2 2006.252.08:17:30.87#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.252.08:17:30.87#ibcon#[27=AT01-04\r\n] 2006.252.08:17:30.87#ibcon#*before write, iclass 26, count 2 2006.252.08:17:30.87#ibcon#enter sib2, iclass 26, count 2 2006.252.08:17:30.87#ibcon#flushed, iclass 26, count 2 2006.252.08:17:30.87#ibcon#about to write, iclass 26, count 2 2006.252.08:17:30.87#ibcon#wrote, iclass 26, count 2 2006.252.08:17:30.87#ibcon#about to read 3, iclass 26, count 2 2006.252.08:17:30.90#ibcon#read 3, iclass 26, count 2 2006.252.08:17:30.90#ibcon#about to read 4, iclass 26, count 2 2006.252.08:17:30.90#ibcon#read 4, iclass 26, count 2 2006.252.08:17:30.90#ibcon#about to read 5, iclass 26, count 2 2006.252.08:17:30.90#ibcon#read 5, iclass 26, count 2 2006.252.08:17:30.90#ibcon#about to read 6, iclass 26, count 2 2006.252.08:17:30.90#ibcon#read 6, iclass 26, count 2 2006.252.08:17:30.90#ibcon#end of sib2, iclass 26, count 2 2006.252.08:17:30.90#ibcon#*after write, iclass 26, count 2 2006.252.08:17:30.90#ibcon#*before return 0, iclass 26, count 2 2006.252.08:17:30.90#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.252.08:17:30.90#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.252.08:17:30.90#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.252.08:17:30.90#ibcon#ireg 7 cls_cnt 0 2006.252.08:17:30.90#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.252.08:17:31.02#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.252.08:17:31.02#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.252.08:17:31.02#ibcon#enter wrdev, iclass 26, count 0 2006.252.08:17:31.02#ibcon#first serial, iclass 26, count 0 2006.252.08:17:31.02#ibcon#enter sib2, iclass 26, count 0 2006.252.08:17:31.02#ibcon#flushed, iclass 26, count 0 2006.252.08:17:31.02#ibcon#about to write, iclass 26, count 0 2006.252.08:17:31.02#ibcon#wrote, iclass 26, count 0 2006.252.08:17:31.02#ibcon#about to read 3, iclass 26, count 0 2006.252.08:17:31.04#ibcon#read 3, iclass 26, count 0 2006.252.08:17:31.04#ibcon#about to read 4, iclass 26, count 0 2006.252.08:17:31.04#ibcon#read 4, iclass 26, count 0 2006.252.08:17:31.04#ibcon#about to read 5, iclass 26, count 0 2006.252.08:17:31.04#ibcon#read 5, iclass 26, count 0 2006.252.08:17:31.04#ibcon#about to read 6, iclass 26, count 0 2006.252.08:17:31.04#ibcon#read 6, iclass 26, count 0 2006.252.08:17:31.04#ibcon#end of sib2, iclass 26, count 0 2006.252.08:17:31.04#ibcon#*mode == 0, iclass 26, count 0 2006.252.08:17:31.04#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.252.08:17:31.04#ibcon#[27=USB\r\n] 2006.252.08:17:31.04#ibcon#*before write, iclass 26, count 0 2006.252.08:17:31.04#ibcon#enter sib2, iclass 26, count 0 2006.252.08:17:31.04#ibcon#flushed, iclass 26, count 0 2006.252.08:17:31.04#ibcon#about to write, iclass 26, count 0 2006.252.08:17:31.04#ibcon#wrote, iclass 26, count 0 2006.252.08:17:31.04#ibcon#about to read 3, iclass 26, count 0 2006.252.08:17:31.07#ibcon#read 3, iclass 26, count 0 2006.252.08:17:31.07#ibcon#about to read 4, iclass 26, count 0 2006.252.08:17:31.07#ibcon#read 4, iclass 26, count 0 2006.252.08:17:31.07#ibcon#about to read 5, iclass 26, count 0 2006.252.08:17:31.07#ibcon#read 5, iclass 26, count 0 2006.252.08:17:31.07#ibcon#about to read 6, iclass 26, count 0 2006.252.08:17:31.07#ibcon#read 6, iclass 26, count 0 2006.252.08:17:31.07#ibcon#end of sib2, iclass 26, count 0 2006.252.08:17:31.07#ibcon#*after write, iclass 26, count 0 2006.252.08:17:31.07#ibcon#*before return 0, iclass 26, count 0 2006.252.08:17:31.07#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.252.08:17:31.07#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.252.08:17:31.07#ibcon#about to clear, iclass 26 cls_cnt 0 2006.252.08:17:31.07#ibcon#cleared, iclass 26 cls_cnt 0 2006.252.08:17:31.07$vc4f8/vblo=2,640.99 2006.252.08:17:31.07#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.252.08:17:31.07#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.252.08:17:31.07#ibcon#ireg 17 cls_cnt 0 2006.252.08:17:31.07#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.252.08:17:31.07#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.252.08:17:31.07#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.252.08:17:31.07#ibcon#enter wrdev, iclass 28, count 0 2006.252.08:17:31.07#ibcon#first serial, iclass 28, count 0 2006.252.08:17:31.07#ibcon#enter sib2, iclass 28, count 0 2006.252.08:17:31.07#ibcon#flushed, iclass 28, count 0 2006.252.08:17:31.07#ibcon#about to write, iclass 28, count 0 2006.252.08:17:31.07#ibcon#wrote, iclass 28, count 0 2006.252.08:17:31.07#ibcon#about to read 3, iclass 28, count 0 2006.252.08:17:31.10#ibcon#read 3, iclass 28, count 0 2006.252.08:17:31.10#ibcon#about to read 4, iclass 28, count 0 2006.252.08:17:31.10#ibcon#read 4, iclass 28, count 0 2006.252.08:17:31.10#ibcon#about to read 5, iclass 28, count 0 2006.252.08:17:31.10#ibcon#read 5, iclass 28, count 0 2006.252.08:17:31.10#ibcon#about to read 6, iclass 28, count 0 2006.252.08:17:31.10#ibcon#read 6, iclass 28, count 0 2006.252.08:17:31.10#ibcon#end of sib2, iclass 28, count 0 2006.252.08:17:31.10#ibcon#*mode == 0, iclass 28, count 0 2006.252.08:17:31.10#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.252.08:17:31.10#ibcon#[28=FRQ=02,640.99\r\n] 2006.252.08:17:31.10#ibcon#*before write, iclass 28, count 0 2006.252.08:17:31.10#ibcon#enter sib2, iclass 28, count 0 2006.252.08:17:31.10#ibcon#flushed, iclass 28, count 0 2006.252.08:17:31.10#ibcon#about to write, iclass 28, count 0 2006.252.08:17:31.10#ibcon#wrote, iclass 28, count 0 2006.252.08:17:31.10#ibcon#about to read 3, iclass 28, count 0 2006.252.08:17:31.14#ibcon#read 3, iclass 28, count 0 2006.252.08:17:31.14#ibcon#about to read 4, iclass 28, count 0 2006.252.08:17:31.14#ibcon#read 4, iclass 28, count 0 2006.252.08:17:31.14#ibcon#about to read 5, iclass 28, count 0 2006.252.08:17:31.14#ibcon#read 5, iclass 28, count 0 2006.252.08:17:31.14#ibcon#about to read 6, iclass 28, count 0 2006.252.08:17:31.14#ibcon#read 6, iclass 28, count 0 2006.252.08:17:31.14#ibcon#end of sib2, iclass 28, count 0 2006.252.08:17:31.14#ibcon#*after write, iclass 28, count 0 2006.252.08:17:31.14#ibcon#*before return 0, iclass 28, count 0 2006.252.08:17:31.14#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.252.08:17:31.14#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.252.08:17:31.14#ibcon#about to clear, iclass 28 cls_cnt 0 2006.252.08:17:31.14#ibcon#cleared, iclass 28 cls_cnt 0 2006.252.08:17:31.14$vc4f8/vb=2,5 2006.252.08:17:31.15#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.252.08:17:31.15#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.252.08:17:31.15#ibcon#ireg 11 cls_cnt 2 2006.252.08:17:31.15#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.252.08:17:31.18#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.252.08:17:31.18#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.252.08:17:31.18#ibcon#enter wrdev, iclass 30, count 2 2006.252.08:17:31.18#ibcon#first serial, iclass 30, count 2 2006.252.08:17:31.18#ibcon#enter sib2, iclass 30, count 2 2006.252.08:17:31.18#ibcon#flushed, iclass 30, count 2 2006.252.08:17:31.18#ibcon#about to write, iclass 30, count 2 2006.252.08:17:31.18#ibcon#wrote, iclass 30, count 2 2006.252.08:17:31.18#ibcon#about to read 3, iclass 30, count 2 2006.252.08:17:31.20#ibcon#read 3, iclass 30, count 2 2006.252.08:17:31.20#ibcon#about to read 4, iclass 30, count 2 2006.252.08:17:31.20#ibcon#read 4, iclass 30, count 2 2006.252.08:17:31.20#ibcon#about to read 5, iclass 30, count 2 2006.252.08:17:31.20#ibcon#read 5, iclass 30, count 2 2006.252.08:17:31.20#ibcon#about to read 6, iclass 30, count 2 2006.252.08:17:31.20#ibcon#read 6, iclass 30, count 2 2006.252.08:17:31.20#ibcon#end of sib2, iclass 30, count 2 2006.252.08:17:31.20#ibcon#*mode == 0, iclass 30, count 2 2006.252.08:17:31.20#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.252.08:17:31.20#ibcon#[27=AT02-05\r\n] 2006.252.08:17:31.20#ibcon#*before write, iclass 30, count 2 2006.252.08:17:31.20#ibcon#enter sib2, iclass 30, count 2 2006.252.08:17:31.20#ibcon#flushed, iclass 30, count 2 2006.252.08:17:31.20#ibcon#about to write, iclass 30, count 2 2006.252.08:17:31.20#ibcon#wrote, iclass 30, count 2 2006.252.08:17:31.20#ibcon#about to read 3, iclass 30, count 2 2006.252.08:17:31.23#ibcon#read 3, iclass 30, count 2 2006.252.08:17:31.23#ibcon#about to read 4, iclass 30, count 2 2006.252.08:17:31.23#ibcon#read 4, iclass 30, count 2 2006.252.08:17:31.23#ibcon#about to read 5, iclass 30, count 2 2006.252.08:17:31.23#ibcon#read 5, iclass 30, count 2 2006.252.08:17:31.23#ibcon#about to read 6, iclass 30, count 2 2006.252.08:17:31.23#ibcon#read 6, iclass 30, count 2 2006.252.08:17:31.23#ibcon#end of sib2, iclass 30, count 2 2006.252.08:17:31.23#ibcon#*after write, iclass 30, count 2 2006.252.08:17:31.23#ibcon#*before return 0, iclass 30, count 2 2006.252.08:17:31.23#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.252.08:17:31.23#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.252.08:17:31.23#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.252.08:17:31.23#ibcon#ireg 7 cls_cnt 0 2006.252.08:17:31.23#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.252.08:17:31.35#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.252.08:17:31.35#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.252.08:17:31.35#ibcon#enter wrdev, iclass 30, count 0 2006.252.08:17:31.35#ibcon#first serial, iclass 30, count 0 2006.252.08:17:31.35#ibcon#enter sib2, iclass 30, count 0 2006.252.08:17:31.35#ibcon#flushed, iclass 30, count 0 2006.252.08:17:31.35#ibcon#about to write, iclass 30, count 0 2006.252.08:17:31.35#ibcon#wrote, iclass 30, count 0 2006.252.08:17:31.35#ibcon#about to read 3, iclass 30, count 0 2006.252.08:17:31.37#ibcon#read 3, iclass 30, count 0 2006.252.08:17:31.37#ibcon#about to read 4, iclass 30, count 0 2006.252.08:17:31.37#ibcon#read 4, iclass 30, count 0 2006.252.08:17:31.37#ibcon#about to read 5, iclass 30, count 0 2006.252.08:17:31.37#ibcon#read 5, iclass 30, count 0 2006.252.08:17:31.37#ibcon#about to read 6, iclass 30, count 0 2006.252.08:17:31.37#ibcon#read 6, iclass 30, count 0 2006.252.08:17:31.37#ibcon#end of sib2, iclass 30, count 0 2006.252.08:17:31.37#ibcon#*mode == 0, iclass 30, count 0 2006.252.08:17:31.37#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.252.08:17:31.37#ibcon#[27=USB\r\n] 2006.252.08:17:31.37#ibcon#*before write, iclass 30, count 0 2006.252.08:17:31.37#ibcon#enter sib2, iclass 30, count 0 2006.252.08:17:31.37#ibcon#flushed, iclass 30, count 0 2006.252.08:17:31.37#ibcon#about to write, iclass 30, count 0 2006.252.08:17:31.37#ibcon#wrote, iclass 30, count 0 2006.252.08:17:31.37#ibcon#about to read 3, iclass 30, count 0 2006.252.08:17:31.40#ibcon#read 3, iclass 30, count 0 2006.252.08:17:31.40#ibcon#about to read 4, iclass 30, count 0 2006.252.08:17:31.40#ibcon#read 4, iclass 30, count 0 2006.252.08:17:31.40#ibcon#about to read 5, iclass 30, count 0 2006.252.08:17:31.40#ibcon#read 5, iclass 30, count 0 2006.252.08:17:31.40#ibcon#about to read 6, iclass 30, count 0 2006.252.08:17:31.40#ibcon#read 6, iclass 30, count 0 2006.252.08:17:31.40#ibcon#end of sib2, iclass 30, count 0 2006.252.08:17:31.40#ibcon#*after write, iclass 30, count 0 2006.252.08:17:31.40#ibcon#*before return 0, iclass 30, count 0 2006.252.08:17:31.40#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.252.08:17:31.40#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.252.08:17:31.40#ibcon#about to clear, iclass 30 cls_cnt 0 2006.252.08:17:31.40#ibcon#cleared, iclass 30 cls_cnt 0 2006.252.08:17:31.40$vc4f8/vblo=3,656.99 2006.252.08:17:31.40#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.252.08:17:31.40#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.252.08:17:31.40#ibcon#ireg 17 cls_cnt 0 2006.252.08:17:31.40#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.252.08:17:31.40#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.252.08:17:31.40#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.252.08:17:31.40#ibcon#enter wrdev, iclass 32, count 0 2006.252.08:17:31.40#ibcon#first serial, iclass 32, count 0 2006.252.08:17:31.40#ibcon#enter sib2, iclass 32, count 0 2006.252.08:17:31.40#ibcon#flushed, iclass 32, count 0 2006.252.08:17:31.40#ibcon#about to write, iclass 32, count 0 2006.252.08:17:31.40#ibcon#wrote, iclass 32, count 0 2006.252.08:17:31.40#ibcon#about to read 3, iclass 32, count 0 2006.252.08:17:31.42#ibcon#read 3, iclass 32, count 0 2006.252.08:17:31.42#ibcon#about to read 4, iclass 32, count 0 2006.252.08:17:31.42#ibcon#read 4, iclass 32, count 0 2006.252.08:17:31.42#ibcon#about to read 5, iclass 32, count 0 2006.252.08:17:31.42#ibcon#read 5, iclass 32, count 0 2006.252.08:17:31.42#ibcon#about to read 6, iclass 32, count 0 2006.252.08:17:31.42#ibcon#read 6, iclass 32, count 0 2006.252.08:17:31.42#ibcon#end of sib2, iclass 32, count 0 2006.252.08:17:31.42#ibcon#*mode == 0, iclass 32, count 0 2006.252.08:17:31.42#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.252.08:17:31.42#ibcon#[28=FRQ=03,656.99\r\n] 2006.252.08:17:31.42#ibcon#*before write, iclass 32, count 0 2006.252.08:17:31.42#ibcon#enter sib2, iclass 32, count 0 2006.252.08:17:31.42#ibcon#flushed, iclass 32, count 0 2006.252.08:17:31.42#ibcon#about to write, iclass 32, count 0 2006.252.08:17:31.42#ibcon#wrote, iclass 32, count 0 2006.252.08:17:31.42#ibcon#about to read 3, iclass 32, count 0 2006.252.08:17:31.46#ibcon#read 3, iclass 32, count 0 2006.252.08:17:31.46#ibcon#about to read 4, iclass 32, count 0 2006.252.08:17:31.46#ibcon#read 4, iclass 32, count 0 2006.252.08:17:31.46#ibcon#about to read 5, iclass 32, count 0 2006.252.08:17:31.46#ibcon#read 5, iclass 32, count 0 2006.252.08:17:31.46#ibcon#about to read 6, iclass 32, count 0 2006.252.08:17:31.46#ibcon#read 6, iclass 32, count 0 2006.252.08:17:31.46#ibcon#end of sib2, iclass 32, count 0 2006.252.08:17:31.46#ibcon#*after write, iclass 32, count 0 2006.252.08:17:31.46#ibcon#*before return 0, iclass 32, count 0 2006.252.08:17:31.46#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.252.08:17:31.46#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.252.08:17:31.46#ibcon#about to clear, iclass 32 cls_cnt 0 2006.252.08:17:31.46#ibcon#cleared, iclass 32 cls_cnt 0 2006.252.08:17:31.46$vc4f8/vb=3,4 2006.252.08:17:31.46#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.252.08:17:31.46#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.252.08:17:31.46#ibcon#ireg 11 cls_cnt 2 2006.252.08:17:31.46#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.252.08:17:31.52#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.252.08:17:31.52#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.252.08:17:31.52#ibcon#enter wrdev, iclass 34, count 2 2006.252.08:17:31.52#ibcon#first serial, iclass 34, count 2 2006.252.08:17:31.52#ibcon#enter sib2, iclass 34, count 2 2006.252.08:17:31.52#ibcon#flushed, iclass 34, count 2 2006.252.08:17:31.52#ibcon#about to write, iclass 34, count 2 2006.252.08:17:31.52#ibcon#wrote, iclass 34, count 2 2006.252.08:17:31.52#ibcon#about to read 3, iclass 34, count 2 2006.252.08:17:31.54#ibcon#read 3, iclass 34, count 2 2006.252.08:17:31.54#ibcon#about to read 4, iclass 34, count 2 2006.252.08:17:31.54#ibcon#read 4, iclass 34, count 2 2006.252.08:17:31.54#ibcon#about to read 5, iclass 34, count 2 2006.252.08:17:31.54#ibcon#read 5, iclass 34, count 2 2006.252.08:17:31.54#ibcon#about to read 6, iclass 34, count 2 2006.252.08:17:31.54#ibcon#read 6, iclass 34, count 2 2006.252.08:17:31.54#ibcon#end of sib2, iclass 34, count 2 2006.252.08:17:31.54#ibcon#*mode == 0, iclass 34, count 2 2006.252.08:17:31.54#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.252.08:17:31.54#ibcon#[27=AT03-04\r\n] 2006.252.08:17:31.54#ibcon#*before write, iclass 34, count 2 2006.252.08:17:31.54#ibcon#enter sib2, iclass 34, count 2 2006.252.08:17:31.54#ibcon#flushed, iclass 34, count 2 2006.252.08:17:31.54#ibcon#about to write, iclass 34, count 2 2006.252.08:17:31.54#ibcon#wrote, iclass 34, count 2 2006.252.08:17:31.54#ibcon#about to read 3, iclass 34, count 2 2006.252.08:17:31.57#ibcon#read 3, iclass 34, count 2 2006.252.08:17:31.57#ibcon#about to read 4, iclass 34, count 2 2006.252.08:17:31.57#ibcon#read 4, iclass 34, count 2 2006.252.08:17:31.57#ibcon#about to read 5, iclass 34, count 2 2006.252.08:17:31.57#ibcon#read 5, iclass 34, count 2 2006.252.08:17:31.57#ibcon#about to read 6, iclass 34, count 2 2006.252.08:17:31.57#ibcon#read 6, iclass 34, count 2 2006.252.08:17:31.57#ibcon#end of sib2, iclass 34, count 2 2006.252.08:17:31.57#ibcon#*after write, iclass 34, count 2 2006.252.08:17:31.57#ibcon#*before return 0, iclass 34, count 2 2006.252.08:17:31.57#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.252.08:17:31.57#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.252.08:17:31.57#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.252.08:17:31.57#ibcon#ireg 7 cls_cnt 0 2006.252.08:17:31.57#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.252.08:17:31.69#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.252.08:17:31.69#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.252.08:17:31.69#ibcon#enter wrdev, iclass 34, count 0 2006.252.08:17:31.69#ibcon#first serial, iclass 34, count 0 2006.252.08:17:31.69#ibcon#enter sib2, iclass 34, count 0 2006.252.08:17:31.69#ibcon#flushed, iclass 34, count 0 2006.252.08:17:31.69#ibcon#about to write, iclass 34, count 0 2006.252.08:17:31.69#ibcon#wrote, iclass 34, count 0 2006.252.08:17:31.69#ibcon#about to read 3, iclass 34, count 0 2006.252.08:17:31.71#ibcon#read 3, iclass 34, count 0 2006.252.08:17:31.71#ibcon#about to read 4, iclass 34, count 0 2006.252.08:17:31.71#ibcon#read 4, iclass 34, count 0 2006.252.08:17:31.71#ibcon#about to read 5, iclass 34, count 0 2006.252.08:17:31.71#ibcon#read 5, iclass 34, count 0 2006.252.08:17:31.71#ibcon#about to read 6, iclass 34, count 0 2006.252.08:17:31.71#ibcon#read 6, iclass 34, count 0 2006.252.08:17:31.71#ibcon#end of sib2, iclass 34, count 0 2006.252.08:17:31.71#ibcon#*mode == 0, iclass 34, count 0 2006.252.08:17:31.71#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.252.08:17:31.71#ibcon#[27=USB\r\n] 2006.252.08:17:31.71#ibcon#*before write, iclass 34, count 0 2006.252.08:17:31.71#ibcon#enter sib2, iclass 34, count 0 2006.252.08:17:31.71#ibcon#flushed, iclass 34, count 0 2006.252.08:17:31.71#ibcon#about to write, iclass 34, count 0 2006.252.08:17:31.71#ibcon#wrote, iclass 34, count 0 2006.252.08:17:31.71#ibcon#about to read 3, iclass 34, count 0 2006.252.08:17:31.74#ibcon#read 3, iclass 34, count 0 2006.252.08:17:31.74#ibcon#about to read 4, iclass 34, count 0 2006.252.08:17:31.74#ibcon#read 4, iclass 34, count 0 2006.252.08:17:31.74#ibcon#about to read 5, iclass 34, count 0 2006.252.08:17:31.74#ibcon#read 5, iclass 34, count 0 2006.252.08:17:31.74#ibcon#about to read 6, iclass 34, count 0 2006.252.08:17:31.74#ibcon#read 6, iclass 34, count 0 2006.252.08:17:31.74#ibcon#end of sib2, iclass 34, count 0 2006.252.08:17:31.74#ibcon#*after write, iclass 34, count 0 2006.252.08:17:31.74#ibcon#*before return 0, iclass 34, count 0 2006.252.08:17:31.74#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.252.08:17:31.74#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.252.08:17:31.74#ibcon#about to clear, iclass 34 cls_cnt 0 2006.252.08:17:31.74#ibcon#cleared, iclass 34 cls_cnt 0 2006.252.08:17:31.74$vc4f8/vblo=4,712.99 2006.252.08:17:31.74#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.252.08:17:31.74#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.252.08:17:31.74#ibcon#ireg 17 cls_cnt 0 2006.252.08:17:31.74#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.252.08:17:31.74#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.252.08:17:31.74#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.252.08:17:31.74#ibcon#enter wrdev, iclass 36, count 0 2006.252.08:17:31.74#ibcon#first serial, iclass 36, count 0 2006.252.08:17:31.74#ibcon#enter sib2, iclass 36, count 0 2006.252.08:17:31.74#ibcon#flushed, iclass 36, count 0 2006.252.08:17:31.74#ibcon#about to write, iclass 36, count 0 2006.252.08:17:31.74#ibcon#wrote, iclass 36, count 0 2006.252.08:17:31.74#ibcon#about to read 3, iclass 36, count 0 2006.252.08:17:31.76#ibcon#read 3, iclass 36, count 0 2006.252.08:17:31.76#ibcon#about to read 4, iclass 36, count 0 2006.252.08:17:31.76#ibcon#read 4, iclass 36, count 0 2006.252.08:17:31.76#ibcon#about to read 5, iclass 36, count 0 2006.252.08:17:31.76#ibcon#read 5, iclass 36, count 0 2006.252.08:17:31.76#ibcon#about to read 6, iclass 36, count 0 2006.252.08:17:31.76#ibcon#read 6, iclass 36, count 0 2006.252.08:17:31.76#ibcon#end of sib2, iclass 36, count 0 2006.252.08:17:31.76#ibcon#*mode == 0, iclass 36, count 0 2006.252.08:17:31.76#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.252.08:17:31.76#ibcon#[28=FRQ=04,712.99\r\n] 2006.252.08:17:31.76#ibcon#*before write, iclass 36, count 0 2006.252.08:17:31.76#ibcon#enter sib2, iclass 36, count 0 2006.252.08:17:31.76#ibcon#flushed, iclass 36, count 0 2006.252.08:17:31.76#ibcon#about to write, iclass 36, count 0 2006.252.08:17:31.76#ibcon#wrote, iclass 36, count 0 2006.252.08:17:31.76#ibcon#about to read 3, iclass 36, count 0 2006.252.08:17:31.80#ibcon#read 3, iclass 36, count 0 2006.252.08:17:31.80#ibcon#about to read 4, iclass 36, count 0 2006.252.08:17:31.80#ibcon#read 4, iclass 36, count 0 2006.252.08:17:31.80#ibcon#about to read 5, iclass 36, count 0 2006.252.08:17:31.80#ibcon#read 5, iclass 36, count 0 2006.252.08:17:31.80#ibcon#about to read 6, iclass 36, count 0 2006.252.08:17:31.80#ibcon#read 6, iclass 36, count 0 2006.252.08:17:31.80#ibcon#end of sib2, iclass 36, count 0 2006.252.08:17:31.80#ibcon#*after write, iclass 36, count 0 2006.252.08:17:31.80#ibcon#*before return 0, iclass 36, count 0 2006.252.08:17:31.80#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.252.08:17:31.80#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.252.08:17:31.80#ibcon#about to clear, iclass 36 cls_cnt 0 2006.252.08:17:31.80#ibcon#cleared, iclass 36 cls_cnt 0 2006.252.08:17:31.80$vc4f8/vb=4,4 2006.252.08:17:31.80#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.252.08:17:31.80#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.252.08:17:31.80#ibcon#ireg 11 cls_cnt 2 2006.252.08:17:31.80#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.252.08:17:31.86#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.252.08:17:31.86#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.252.08:17:31.86#ibcon#enter wrdev, iclass 38, count 2 2006.252.08:17:31.86#ibcon#first serial, iclass 38, count 2 2006.252.08:17:31.86#ibcon#enter sib2, iclass 38, count 2 2006.252.08:17:31.86#ibcon#flushed, iclass 38, count 2 2006.252.08:17:31.86#ibcon#about to write, iclass 38, count 2 2006.252.08:17:31.86#ibcon#wrote, iclass 38, count 2 2006.252.08:17:31.86#ibcon#about to read 3, iclass 38, count 2 2006.252.08:17:31.88#ibcon#read 3, iclass 38, count 2 2006.252.08:17:31.88#ibcon#about to read 4, iclass 38, count 2 2006.252.08:17:31.88#ibcon#read 4, iclass 38, count 2 2006.252.08:17:31.88#ibcon#about to read 5, iclass 38, count 2 2006.252.08:17:31.88#ibcon#read 5, iclass 38, count 2 2006.252.08:17:31.88#ibcon#about to read 6, iclass 38, count 2 2006.252.08:17:31.88#ibcon#read 6, iclass 38, count 2 2006.252.08:17:31.88#ibcon#end of sib2, iclass 38, count 2 2006.252.08:17:31.88#ibcon#*mode == 0, iclass 38, count 2 2006.252.08:17:31.88#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.252.08:17:31.88#ibcon#[27=AT04-04\r\n] 2006.252.08:17:31.88#ibcon#*before write, iclass 38, count 2 2006.252.08:17:31.88#ibcon#enter sib2, iclass 38, count 2 2006.252.08:17:31.88#ibcon#flushed, iclass 38, count 2 2006.252.08:17:31.88#ibcon#about to write, iclass 38, count 2 2006.252.08:17:31.88#ibcon#wrote, iclass 38, count 2 2006.252.08:17:31.88#ibcon#about to read 3, iclass 38, count 2 2006.252.08:17:31.91#ibcon#read 3, iclass 38, count 2 2006.252.08:17:31.91#ibcon#about to read 4, iclass 38, count 2 2006.252.08:17:31.91#ibcon#read 4, iclass 38, count 2 2006.252.08:17:31.91#ibcon#about to read 5, iclass 38, count 2 2006.252.08:17:31.91#ibcon#read 5, iclass 38, count 2 2006.252.08:17:31.91#ibcon#about to read 6, iclass 38, count 2 2006.252.08:17:31.91#ibcon#read 6, iclass 38, count 2 2006.252.08:17:31.91#ibcon#end of sib2, iclass 38, count 2 2006.252.08:17:31.91#ibcon#*after write, iclass 38, count 2 2006.252.08:17:31.91#ibcon#*before return 0, iclass 38, count 2 2006.252.08:17:31.91#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.252.08:17:31.91#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.252.08:17:31.91#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.252.08:17:31.91#ibcon#ireg 7 cls_cnt 0 2006.252.08:17:31.91#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.252.08:17:32.03#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.252.08:17:32.03#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.252.08:17:32.03#ibcon#enter wrdev, iclass 38, count 0 2006.252.08:17:32.03#ibcon#first serial, iclass 38, count 0 2006.252.08:17:32.03#ibcon#enter sib2, iclass 38, count 0 2006.252.08:17:32.03#ibcon#flushed, iclass 38, count 0 2006.252.08:17:32.03#ibcon#about to write, iclass 38, count 0 2006.252.08:17:32.03#ibcon#wrote, iclass 38, count 0 2006.252.08:17:32.03#ibcon#about to read 3, iclass 38, count 0 2006.252.08:17:32.05#ibcon#read 3, iclass 38, count 0 2006.252.08:17:32.05#ibcon#about to read 4, iclass 38, count 0 2006.252.08:17:32.05#ibcon#read 4, iclass 38, count 0 2006.252.08:17:32.05#ibcon#about to read 5, iclass 38, count 0 2006.252.08:17:32.05#ibcon#read 5, iclass 38, count 0 2006.252.08:17:32.05#ibcon#about to read 6, iclass 38, count 0 2006.252.08:17:32.05#ibcon#read 6, iclass 38, count 0 2006.252.08:17:32.05#ibcon#end of sib2, iclass 38, count 0 2006.252.08:17:32.05#ibcon#*mode == 0, iclass 38, count 0 2006.252.08:17:32.05#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.252.08:17:32.05#ibcon#[27=USB\r\n] 2006.252.08:17:32.05#ibcon#*before write, iclass 38, count 0 2006.252.08:17:32.05#ibcon#enter sib2, iclass 38, count 0 2006.252.08:17:32.05#ibcon#flushed, iclass 38, count 0 2006.252.08:17:32.05#ibcon#about to write, iclass 38, count 0 2006.252.08:17:32.05#ibcon#wrote, iclass 38, count 0 2006.252.08:17:32.05#ibcon#about to read 3, iclass 38, count 0 2006.252.08:17:32.08#ibcon#read 3, iclass 38, count 0 2006.252.08:17:32.09#ibcon#about to read 4, iclass 38, count 0 2006.252.08:17:32.09#ibcon#read 4, iclass 38, count 0 2006.252.08:17:32.09#ibcon#about to read 5, iclass 38, count 0 2006.252.08:17:32.09#ibcon#read 5, iclass 38, count 0 2006.252.08:17:32.09#ibcon#about to read 6, iclass 38, count 0 2006.252.08:17:32.09#ibcon#read 6, iclass 38, count 0 2006.252.08:17:32.09#ibcon#end of sib2, iclass 38, count 0 2006.252.08:17:32.09#ibcon#*after write, iclass 38, count 0 2006.252.08:17:32.09#ibcon#*before return 0, iclass 38, count 0 2006.252.08:17:32.09#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.252.08:17:32.09#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.252.08:17:32.09#ibcon#about to clear, iclass 38 cls_cnt 0 2006.252.08:17:32.09#ibcon#cleared, iclass 38 cls_cnt 0 2006.252.08:17:32.09$vc4f8/vblo=5,744.99 2006.252.08:17:32.09#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.252.08:17:32.09#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.252.08:17:32.09#ibcon#ireg 17 cls_cnt 0 2006.252.08:17:32.09#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.252.08:17:32.09#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.252.08:17:32.09#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.252.08:17:32.09#ibcon#enter wrdev, iclass 40, count 0 2006.252.08:17:32.09#ibcon#first serial, iclass 40, count 0 2006.252.08:17:32.09#ibcon#enter sib2, iclass 40, count 0 2006.252.08:17:32.09#ibcon#flushed, iclass 40, count 0 2006.252.08:17:32.09#ibcon#about to write, iclass 40, count 0 2006.252.08:17:32.09#ibcon#wrote, iclass 40, count 0 2006.252.08:17:32.09#ibcon#about to read 3, iclass 40, count 0 2006.252.08:17:32.10#ibcon#read 3, iclass 40, count 0 2006.252.08:17:32.10#ibcon#about to read 4, iclass 40, count 0 2006.252.08:17:32.10#ibcon#read 4, iclass 40, count 0 2006.252.08:17:32.10#ibcon#about to read 5, iclass 40, count 0 2006.252.08:17:32.10#ibcon#read 5, iclass 40, count 0 2006.252.08:17:32.10#ibcon#about to read 6, iclass 40, count 0 2006.252.08:17:32.10#ibcon#read 6, iclass 40, count 0 2006.252.08:17:32.10#ibcon#end of sib2, iclass 40, count 0 2006.252.08:17:32.10#ibcon#*mode == 0, iclass 40, count 0 2006.252.08:17:32.10#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.252.08:17:32.10#ibcon#[28=FRQ=05,744.99\r\n] 2006.252.08:17:32.10#ibcon#*before write, iclass 40, count 0 2006.252.08:17:32.10#ibcon#enter sib2, iclass 40, count 0 2006.252.08:17:32.10#ibcon#flushed, iclass 40, count 0 2006.252.08:17:32.10#ibcon#about to write, iclass 40, count 0 2006.252.08:17:32.10#ibcon#wrote, iclass 40, count 0 2006.252.08:17:32.10#ibcon#about to read 3, iclass 40, count 0 2006.252.08:17:32.14#ibcon#read 3, iclass 40, count 0 2006.252.08:17:32.14#ibcon#about to read 4, iclass 40, count 0 2006.252.08:17:32.14#ibcon#read 4, iclass 40, count 0 2006.252.08:17:32.14#ibcon#about to read 5, iclass 40, count 0 2006.252.08:17:32.14#ibcon#read 5, iclass 40, count 0 2006.252.08:17:32.14#ibcon#about to read 6, iclass 40, count 0 2006.252.08:17:32.14#ibcon#read 6, iclass 40, count 0 2006.252.08:17:32.14#ibcon#end of sib2, iclass 40, count 0 2006.252.08:17:32.14#ibcon#*after write, iclass 40, count 0 2006.252.08:17:32.14#ibcon#*before return 0, iclass 40, count 0 2006.252.08:17:32.14#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.252.08:17:32.14#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.252.08:17:32.14#ibcon#about to clear, iclass 40 cls_cnt 0 2006.252.08:17:32.14#ibcon#cleared, iclass 40 cls_cnt 0 2006.252.08:17:32.14$vc4f8/vb=5,4 2006.252.08:17:32.14#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.252.08:17:32.14#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.252.08:17:32.14#ibcon#ireg 11 cls_cnt 2 2006.252.08:17:32.14#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.252.08:17:32.21#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.252.08:17:32.21#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.252.08:17:32.21#ibcon#enter wrdev, iclass 4, count 2 2006.252.08:17:32.21#ibcon#first serial, iclass 4, count 2 2006.252.08:17:32.21#ibcon#enter sib2, iclass 4, count 2 2006.252.08:17:32.21#ibcon#flushed, iclass 4, count 2 2006.252.08:17:32.21#ibcon#about to write, iclass 4, count 2 2006.252.08:17:32.21#ibcon#wrote, iclass 4, count 2 2006.252.08:17:32.21#ibcon#about to read 3, iclass 4, count 2 2006.252.08:17:32.23#ibcon#read 3, iclass 4, count 2 2006.252.08:17:32.23#ibcon#about to read 4, iclass 4, count 2 2006.252.08:17:32.23#ibcon#read 4, iclass 4, count 2 2006.252.08:17:32.23#ibcon#about to read 5, iclass 4, count 2 2006.252.08:17:32.23#ibcon#read 5, iclass 4, count 2 2006.252.08:17:32.23#ibcon#about to read 6, iclass 4, count 2 2006.252.08:17:32.23#ibcon#read 6, iclass 4, count 2 2006.252.08:17:32.23#ibcon#end of sib2, iclass 4, count 2 2006.252.08:17:32.23#ibcon#*mode == 0, iclass 4, count 2 2006.252.08:17:32.23#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.252.08:17:32.23#ibcon#[27=AT05-04\r\n] 2006.252.08:17:32.23#ibcon#*before write, iclass 4, count 2 2006.252.08:17:32.23#ibcon#enter sib2, iclass 4, count 2 2006.252.08:17:32.23#ibcon#flushed, iclass 4, count 2 2006.252.08:17:32.23#ibcon#about to write, iclass 4, count 2 2006.252.08:17:32.23#ibcon#wrote, iclass 4, count 2 2006.252.08:17:32.23#ibcon#about to read 3, iclass 4, count 2 2006.252.08:17:32.26#ibcon#read 3, iclass 4, count 2 2006.252.08:17:32.26#ibcon#about to read 4, iclass 4, count 2 2006.252.08:17:32.26#ibcon#read 4, iclass 4, count 2 2006.252.08:17:32.26#ibcon#about to read 5, iclass 4, count 2 2006.252.08:17:32.26#ibcon#read 5, iclass 4, count 2 2006.252.08:17:32.26#ibcon#about to read 6, iclass 4, count 2 2006.252.08:17:32.26#ibcon#read 6, iclass 4, count 2 2006.252.08:17:32.26#ibcon#end of sib2, iclass 4, count 2 2006.252.08:17:32.26#ibcon#*after write, iclass 4, count 2 2006.252.08:17:32.26#ibcon#*before return 0, iclass 4, count 2 2006.252.08:17:32.26#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.252.08:17:32.26#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.252.08:17:32.26#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.252.08:17:32.26#ibcon#ireg 7 cls_cnt 0 2006.252.08:17:32.26#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.252.08:17:32.38#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.252.08:17:32.38#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.252.08:17:32.38#ibcon#enter wrdev, iclass 4, count 0 2006.252.08:17:32.38#ibcon#first serial, iclass 4, count 0 2006.252.08:17:32.38#ibcon#enter sib2, iclass 4, count 0 2006.252.08:17:32.38#ibcon#flushed, iclass 4, count 0 2006.252.08:17:32.38#ibcon#about to write, iclass 4, count 0 2006.252.08:17:32.38#ibcon#wrote, iclass 4, count 0 2006.252.08:17:32.38#ibcon#about to read 3, iclass 4, count 0 2006.252.08:17:32.40#ibcon#read 3, iclass 4, count 0 2006.252.08:17:32.40#ibcon#about to read 4, iclass 4, count 0 2006.252.08:17:32.40#ibcon#read 4, iclass 4, count 0 2006.252.08:17:32.40#ibcon#about to read 5, iclass 4, count 0 2006.252.08:17:32.40#ibcon#read 5, iclass 4, count 0 2006.252.08:17:32.40#ibcon#about to read 6, iclass 4, count 0 2006.252.08:17:32.40#ibcon#read 6, iclass 4, count 0 2006.252.08:17:32.40#ibcon#end of sib2, iclass 4, count 0 2006.252.08:17:32.40#ibcon#*mode == 0, iclass 4, count 0 2006.252.08:17:32.40#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.252.08:17:32.40#ibcon#[27=USB\r\n] 2006.252.08:17:32.40#ibcon#*before write, iclass 4, count 0 2006.252.08:17:32.40#ibcon#enter sib2, iclass 4, count 0 2006.252.08:17:32.40#ibcon#flushed, iclass 4, count 0 2006.252.08:17:32.40#ibcon#about to write, iclass 4, count 0 2006.252.08:17:32.40#ibcon#wrote, iclass 4, count 0 2006.252.08:17:32.40#ibcon#about to read 3, iclass 4, count 0 2006.252.08:17:32.43#ibcon#read 3, iclass 4, count 0 2006.252.08:17:32.43#ibcon#about to read 4, iclass 4, count 0 2006.252.08:17:32.43#ibcon#read 4, iclass 4, count 0 2006.252.08:17:32.43#ibcon#about to read 5, iclass 4, count 0 2006.252.08:17:32.43#ibcon#read 5, iclass 4, count 0 2006.252.08:17:32.43#ibcon#about to read 6, iclass 4, count 0 2006.252.08:17:32.43#ibcon#read 6, iclass 4, count 0 2006.252.08:17:32.43#ibcon#end of sib2, iclass 4, count 0 2006.252.08:17:32.43#ibcon#*after write, iclass 4, count 0 2006.252.08:17:32.43#ibcon#*before return 0, iclass 4, count 0 2006.252.08:17:32.43#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.252.08:17:32.43#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.252.08:17:32.43#ibcon#about to clear, iclass 4 cls_cnt 0 2006.252.08:17:32.43#ibcon#cleared, iclass 4 cls_cnt 0 2006.252.08:17:32.43$vc4f8/vblo=6,752.99 2006.252.08:17:32.43#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.252.08:17:32.43#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.252.08:17:32.43#ibcon#ireg 17 cls_cnt 0 2006.252.08:17:32.43#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.252.08:17:32.43#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.252.08:17:32.43#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.252.08:17:32.43#ibcon#enter wrdev, iclass 6, count 0 2006.252.08:17:32.43#ibcon#first serial, iclass 6, count 0 2006.252.08:17:32.43#ibcon#enter sib2, iclass 6, count 0 2006.252.08:17:32.43#ibcon#flushed, iclass 6, count 0 2006.252.08:17:32.43#ibcon#about to write, iclass 6, count 0 2006.252.08:17:32.43#ibcon#wrote, iclass 6, count 0 2006.252.08:17:32.43#ibcon#about to read 3, iclass 6, count 0 2006.252.08:17:32.45#ibcon#read 3, iclass 6, count 0 2006.252.08:17:32.45#ibcon#about to read 4, iclass 6, count 0 2006.252.08:17:32.45#ibcon#read 4, iclass 6, count 0 2006.252.08:17:32.45#ibcon#about to read 5, iclass 6, count 0 2006.252.08:17:32.45#ibcon#read 5, iclass 6, count 0 2006.252.08:17:32.45#ibcon#about to read 6, iclass 6, count 0 2006.252.08:17:32.45#ibcon#read 6, iclass 6, count 0 2006.252.08:17:32.45#ibcon#end of sib2, iclass 6, count 0 2006.252.08:17:32.45#ibcon#*mode == 0, iclass 6, count 0 2006.252.08:17:32.45#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.252.08:17:32.45#ibcon#[28=FRQ=06,752.99\r\n] 2006.252.08:17:32.45#ibcon#*before write, iclass 6, count 0 2006.252.08:17:32.45#ibcon#enter sib2, iclass 6, count 0 2006.252.08:17:32.45#ibcon#flushed, iclass 6, count 0 2006.252.08:17:32.45#ibcon#about to write, iclass 6, count 0 2006.252.08:17:32.45#ibcon#wrote, iclass 6, count 0 2006.252.08:17:32.45#ibcon#about to read 3, iclass 6, count 0 2006.252.08:17:32.49#ibcon#read 3, iclass 6, count 0 2006.252.08:17:32.49#ibcon#about to read 4, iclass 6, count 0 2006.252.08:17:32.49#ibcon#read 4, iclass 6, count 0 2006.252.08:17:32.49#ibcon#about to read 5, iclass 6, count 0 2006.252.08:17:32.49#ibcon#read 5, iclass 6, count 0 2006.252.08:17:32.49#ibcon#about to read 6, iclass 6, count 0 2006.252.08:17:32.49#ibcon#read 6, iclass 6, count 0 2006.252.08:17:32.49#ibcon#end of sib2, iclass 6, count 0 2006.252.08:17:32.49#ibcon#*after write, iclass 6, count 0 2006.252.08:17:32.49#ibcon#*before return 0, iclass 6, count 0 2006.252.08:17:32.49#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.252.08:17:32.49#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.252.08:17:32.49#ibcon#about to clear, iclass 6 cls_cnt 0 2006.252.08:17:32.49#ibcon#cleared, iclass 6 cls_cnt 0 2006.252.08:17:32.49$vc4f8/vb=6,4 2006.252.08:17:32.49#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.252.08:17:32.49#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.252.08:17:32.49#ibcon#ireg 11 cls_cnt 2 2006.252.08:17:32.49#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.252.08:17:32.55#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.252.08:17:32.55#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.252.08:17:32.55#ibcon#enter wrdev, iclass 10, count 2 2006.252.08:17:32.55#ibcon#first serial, iclass 10, count 2 2006.252.08:17:32.55#ibcon#enter sib2, iclass 10, count 2 2006.252.08:17:32.55#ibcon#flushed, iclass 10, count 2 2006.252.08:17:32.55#ibcon#about to write, iclass 10, count 2 2006.252.08:17:32.55#ibcon#wrote, iclass 10, count 2 2006.252.08:17:32.55#ibcon#about to read 3, iclass 10, count 2 2006.252.08:17:32.57#ibcon#read 3, iclass 10, count 2 2006.252.08:17:32.57#ibcon#about to read 4, iclass 10, count 2 2006.252.08:17:32.57#ibcon#read 4, iclass 10, count 2 2006.252.08:17:32.57#ibcon#about to read 5, iclass 10, count 2 2006.252.08:17:32.57#ibcon#read 5, iclass 10, count 2 2006.252.08:17:32.57#ibcon#about to read 6, iclass 10, count 2 2006.252.08:17:32.57#ibcon#read 6, iclass 10, count 2 2006.252.08:17:32.57#ibcon#end of sib2, iclass 10, count 2 2006.252.08:17:32.57#ibcon#*mode == 0, iclass 10, count 2 2006.252.08:17:32.57#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.252.08:17:32.57#ibcon#[27=AT06-04\r\n] 2006.252.08:17:32.57#ibcon#*before write, iclass 10, count 2 2006.252.08:17:32.57#ibcon#enter sib2, iclass 10, count 2 2006.252.08:17:32.57#ibcon#flushed, iclass 10, count 2 2006.252.08:17:32.57#ibcon#about to write, iclass 10, count 2 2006.252.08:17:32.57#ibcon#wrote, iclass 10, count 2 2006.252.08:17:32.57#ibcon#about to read 3, iclass 10, count 2 2006.252.08:17:32.60#ibcon#read 3, iclass 10, count 2 2006.252.08:17:32.60#ibcon#about to read 4, iclass 10, count 2 2006.252.08:17:32.60#ibcon#read 4, iclass 10, count 2 2006.252.08:17:32.60#ibcon#about to read 5, iclass 10, count 2 2006.252.08:17:32.60#ibcon#read 5, iclass 10, count 2 2006.252.08:17:32.60#ibcon#about to read 6, iclass 10, count 2 2006.252.08:17:32.60#ibcon#read 6, iclass 10, count 2 2006.252.08:17:32.60#ibcon#end of sib2, iclass 10, count 2 2006.252.08:17:32.60#ibcon#*after write, iclass 10, count 2 2006.252.08:17:32.60#ibcon#*before return 0, iclass 10, count 2 2006.252.08:17:32.60#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.252.08:17:32.60#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.252.08:17:32.60#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.252.08:17:32.60#ibcon#ireg 7 cls_cnt 0 2006.252.08:17:32.60#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.252.08:17:32.72#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.252.08:17:32.72#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.252.08:17:32.72#ibcon#enter wrdev, iclass 10, count 0 2006.252.08:17:32.72#ibcon#first serial, iclass 10, count 0 2006.252.08:17:32.72#ibcon#enter sib2, iclass 10, count 0 2006.252.08:17:32.72#ibcon#flushed, iclass 10, count 0 2006.252.08:17:32.72#ibcon#about to write, iclass 10, count 0 2006.252.08:17:32.72#ibcon#wrote, iclass 10, count 0 2006.252.08:17:32.72#ibcon#about to read 3, iclass 10, count 0 2006.252.08:17:32.74#ibcon#read 3, iclass 10, count 0 2006.252.08:17:32.74#ibcon#about to read 4, iclass 10, count 0 2006.252.08:17:32.74#ibcon#read 4, iclass 10, count 0 2006.252.08:17:32.74#ibcon#about to read 5, iclass 10, count 0 2006.252.08:17:32.74#ibcon#read 5, iclass 10, count 0 2006.252.08:17:32.74#ibcon#about to read 6, iclass 10, count 0 2006.252.08:17:32.74#ibcon#read 6, iclass 10, count 0 2006.252.08:17:32.74#ibcon#end of sib2, iclass 10, count 0 2006.252.08:17:32.74#ibcon#*mode == 0, iclass 10, count 0 2006.252.08:17:32.74#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.252.08:17:32.74#ibcon#[27=USB\r\n] 2006.252.08:17:32.74#ibcon#*before write, iclass 10, count 0 2006.252.08:17:32.74#ibcon#enter sib2, iclass 10, count 0 2006.252.08:17:32.74#ibcon#flushed, iclass 10, count 0 2006.252.08:17:32.74#ibcon#about to write, iclass 10, count 0 2006.252.08:17:32.74#ibcon#wrote, iclass 10, count 0 2006.252.08:17:32.74#ibcon#about to read 3, iclass 10, count 0 2006.252.08:17:32.77#ibcon#read 3, iclass 10, count 0 2006.252.08:17:32.77#ibcon#about to read 4, iclass 10, count 0 2006.252.08:17:32.77#ibcon#read 4, iclass 10, count 0 2006.252.08:17:32.77#ibcon#about to read 5, iclass 10, count 0 2006.252.08:17:32.77#ibcon#read 5, iclass 10, count 0 2006.252.08:17:32.77#ibcon#about to read 6, iclass 10, count 0 2006.252.08:17:32.77#ibcon#read 6, iclass 10, count 0 2006.252.08:17:32.77#ibcon#end of sib2, iclass 10, count 0 2006.252.08:17:32.77#ibcon#*after write, iclass 10, count 0 2006.252.08:17:32.77#ibcon#*before return 0, iclass 10, count 0 2006.252.08:17:32.77#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.252.08:17:32.77#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.252.08:17:32.77#ibcon#about to clear, iclass 10 cls_cnt 0 2006.252.08:17:32.77#ibcon#cleared, iclass 10 cls_cnt 0 2006.252.08:17:32.77$vc4f8/vabw=wide 2006.252.08:17:32.77#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.252.08:17:32.77#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.252.08:17:32.77#ibcon#ireg 8 cls_cnt 0 2006.252.08:17:32.77#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.252.08:17:32.77#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.252.08:17:32.77#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.252.08:17:32.77#ibcon#enter wrdev, iclass 12, count 0 2006.252.08:17:32.77#ibcon#first serial, iclass 12, count 0 2006.252.08:17:32.77#ibcon#enter sib2, iclass 12, count 0 2006.252.08:17:32.77#ibcon#flushed, iclass 12, count 0 2006.252.08:17:32.77#ibcon#about to write, iclass 12, count 0 2006.252.08:17:32.77#ibcon#wrote, iclass 12, count 0 2006.252.08:17:32.77#ibcon#about to read 3, iclass 12, count 0 2006.252.08:17:32.80#ibcon#read 3, iclass 12, count 0 2006.252.08:17:32.80#ibcon#about to read 4, iclass 12, count 0 2006.252.08:17:32.80#ibcon#read 4, iclass 12, count 0 2006.252.08:17:32.80#ibcon#about to read 5, iclass 12, count 0 2006.252.08:17:32.80#ibcon#read 5, iclass 12, count 0 2006.252.08:17:32.80#ibcon#about to read 6, iclass 12, count 0 2006.252.08:17:32.80#ibcon#read 6, iclass 12, count 0 2006.252.08:17:32.80#ibcon#end of sib2, iclass 12, count 0 2006.252.08:17:32.80#ibcon#*mode == 0, iclass 12, count 0 2006.252.08:17:32.80#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.252.08:17:32.80#ibcon#[25=BW32\r\n] 2006.252.08:17:32.80#ibcon#*before write, iclass 12, count 0 2006.252.08:17:32.80#ibcon#enter sib2, iclass 12, count 0 2006.252.08:17:32.80#ibcon#flushed, iclass 12, count 0 2006.252.08:17:32.80#ibcon#about to write, iclass 12, count 0 2006.252.08:17:32.80#ibcon#wrote, iclass 12, count 0 2006.252.08:17:32.80#ibcon#about to read 3, iclass 12, count 0 2006.252.08:17:32.83#ibcon#read 3, iclass 12, count 0 2006.252.08:17:32.83#ibcon#about to read 4, iclass 12, count 0 2006.252.08:17:32.83#ibcon#read 4, iclass 12, count 0 2006.252.08:17:32.83#ibcon#about to read 5, iclass 12, count 0 2006.252.08:17:32.83#ibcon#read 5, iclass 12, count 0 2006.252.08:17:32.83#ibcon#about to read 6, iclass 12, count 0 2006.252.08:17:32.83#ibcon#read 6, iclass 12, count 0 2006.252.08:17:32.83#ibcon#end of sib2, iclass 12, count 0 2006.252.08:17:32.83#ibcon#*after write, iclass 12, count 0 2006.252.08:17:32.83#ibcon#*before return 0, iclass 12, count 0 2006.252.08:17:32.83#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.252.08:17:32.83#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.252.08:17:32.83#ibcon#about to clear, iclass 12 cls_cnt 0 2006.252.08:17:32.83#ibcon#cleared, iclass 12 cls_cnt 0 2006.252.08:17:32.83$vc4f8/vbbw=wide 2006.252.08:17:32.83#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.252.08:17:32.83#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.252.08:17:32.83#ibcon#ireg 8 cls_cnt 0 2006.252.08:17:32.83#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.252.08:17:32.90#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.252.08:17:32.90#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.252.08:17:32.90#ibcon#enter wrdev, iclass 14, count 0 2006.252.08:17:32.90#ibcon#first serial, iclass 14, count 0 2006.252.08:17:32.90#ibcon#enter sib2, iclass 14, count 0 2006.252.08:17:32.90#ibcon#flushed, iclass 14, count 0 2006.252.08:17:32.90#ibcon#about to write, iclass 14, count 0 2006.252.08:17:32.90#ibcon#wrote, iclass 14, count 0 2006.252.08:17:32.90#ibcon#about to read 3, iclass 14, count 0 2006.252.08:17:32.91#ibcon#read 3, iclass 14, count 0 2006.252.08:17:32.91#ibcon#about to read 4, iclass 14, count 0 2006.252.08:17:32.91#ibcon#read 4, iclass 14, count 0 2006.252.08:17:32.91#ibcon#about to read 5, iclass 14, count 0 2006.252.08:17:32.91#ibcon#read 5, iclass 14, count 0 2006.252.08:17:32.91#ibcon#about to read 6, iclass 14, count 0 2006.252.08:17:32.91#ibcon#read 6, iclass 14, count 0 2006.252.08:17:32.91#ibcon#end of sib2, iclass 14, count 0 2006.252.08:17:32.91#ibcon#*mode == 0, iclass 14, count 0 2006.252.08:17:32.91#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.252.08:17:32.91#ibcon#[27=BW32\r\n] 2006.252.08:17:32.91#ibcon#*before write, iclass 14, count 0 2006.252.08:17:32.91#ibcon#enter sib2, iclass 14, count 0 2006.252.08:17:32.91#ibcon#flushed, iclass 14, count 0 2006.252.08:17:32.91#ibcon#about to write, iclass 14, count 0 2006.252.08:17:32.91#ibcon#wrote, iclass 14, count 0 2006.252.08:17:32.91#ibcon#about to read 3, iclass 14, count 0 2006.252.08:17:32.94#ibcon#read 3, iclass 14, count 0 2006.252.08:17:32.94#ibcon#about to read 4, iclass 14, count 0 2006.252.08:17:32.94#ibcon#read 4, iclass 14, count 0 2006.252.08:17:32.94#ibcon#about to read 5, iclass 14, count 0 2006.252.08:17:32.94#ibcon#read 5, iclass 14, count 0 2006.252.08:17:32.94#ibcon#about to read 6, iclass 14, count 0 2006.252.08:17:32.94#ibcon#read 6, iclass 14, count 0 2006.252.08:17:32.94#ibcon#end of sib2, iclass 14, count 0 2006.252.08:17:32.94#ibcon#*after write, iclass 14, count 0 2006.252.08:17:32.94#ibcon#*before return 0, iclass 14, count 0 2006.252.08:17:32.94#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.252.08:17:32.94#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.252.08:17:32.94#ibcon#about to clear, iclass 14 cls_cnt 0 2006.252.08:17:32.94#ibcon#cleared, iclass 14 cls_cnt 0 2006.252.08:17:32.94$4f8m12a/ifd4f 2006.252.08:17:32.94$ifd4f/lo= 2006.252.08:17:32.94$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.252.08:17:32.94$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.252.08:17:32.94$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.252.08:17:32.95$ifd4f/patch= 2006.252.08:17:32.95$ifd4f/patch=lo1,a1,a2,a3,a4 2006.252.08:17:32.95$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.252.08:17:32.95$ifd4f/patch=lo3,a5,a6,a7,a8 2006.252.08:17:32.95$4f8m12a/"form=m,16.000,1:2 2006.252.08:17:32.95$4f8m12a/"tpicd 2006.252.08:17:32.95$4f8m12a/echo=off 2006.252.08:17:32.95$4f8m12a/xlog=off 2006.252.08:17:32.95:!2006.252.08:18:00 2006.252.08:17:48.14#trakl#Source acquired 2006.252.08:17:48.14#flagr#flagr/antenna,acquired 2006.252.08:18:00.01:preob 2006.252.08:18:01.13/onsource/TRACKING 2006.252.08:18:01.13:!2006.252.08:18:10 2006.252.08:18:10.00:data_valid=on 2006.252.08:18:10.00:midob 2006.252.08:18:10.13/onsource/TRACKING 2006.252.08:18:10.13/wx/27.27,1011.2,91 2006.252.08:18:10.23/cable/+6.4113E-03 2006.252.08:18:11.32/va/01,08,usb,yes,33,34 2006.252.08:18:11.32/va/02,07,usb,yes,32,34 2006.252.08:18:11.32/va/03,06,usb,yes,34,35 2006.252.08:18:11.32/va/04,07,usb,yes,33,36 2006.252.08:18:11.32/va/05,07,usb,yes,37,39 2006.252.08:18:11.32/va/06,07,usb,yes,32,32 2006.252.08:18:11.32/va/07,07,usb,yes,32,32 2006.252.08:18:11.32/va/08,07,usb,yes,34,34 2006.252.08:18:11.55/valo/01,532.99,yes,locked 2006.252.08:18:11.55/valo/02,572.99,yes,locked 2006.252.08:18:11.55/valo/03,672.99,yes,locked 2006.252.08:18:11.55/valo/04,832.99,yes,locked 2006.252.08:18:11.55/valo/05,652.99,yes,locked 2006.252.08:18:11.55/valo/06,772.99,yes,locked 2006.252.08:18:11.55/valo/07,832.99,yes,locked 2006.252.08:18:11.55/valo/08,852.99,yes,locked 2006.252.08:18:12.64/vb/01,04,usb,yes,30,29 2006.252.08:18:12.64/vb/02,05,usb,yes,28,29 2006.252.08:18:12.64/vb/03,04,usb,yes,28,32 2006.252.08:18:12.64/vb/04,04,usb,yes,29,29 2006.252.08:18:12.64/vb/05,04,usb,yes,27,31 2006.252.08:18:12.64/vb/06,04,usb,yes,28,31 2006.252.08:18:12.64/vb/07,04,usb,yes,31,30 2006.252.08:18:12.64/vb/08,04,usb,yes,28,31 2006.252.08:18:12.88/vblo/01,632.99,yes,locked 2006.252.08:18:12.88/vblo/02,640.99,yes,locked 2006.252.08:18:12.88/vblo/03,656.99,yes,locked 2006.252.08:18:12.88/vblo/04,712.99,yes,locked 2006.252.08:18:12.88/vblo/05,744.99,yes,locked 2006.252.08:18:12.88/vblo/06,752.99,yes,locked 2006.252.08:18:12.88/vblo/07,734.99,yes,locked 2006.252.08:18:12.88/vblo/08,744.99,yes,locked 2006.252.08:18:13.03/vabw/8 2006.252.08:18:13.18/vbbw/8 2006.252.08:18:13.27/xfe/off,on,14.0 2006.252.08:18:13.64/ifatt/23,28,28,28 2006.252.08:18:14.07/fmout-gps/S +4.76E-07 2006.252.08:18:14.12:!2006.252.08:19:10 2006.252.08:19:10.01:data_valid=off 2006.252.08:19:10.02:postob 2006.252.08:19:10.12/cable/+6.4114E-03 2006.252.08:19:10.13/wx/27.26,1011.2,91 2006.252.08:19:11.07/fmout-gps/S +4.75E-07 2006.252.08:19:11.08:scan_name=252-0821,k06252,60 2006.252.08:19:11.08:source=1128+385,113053.28,381518.5,2000.0,ccw 2006.252.08:19:11.13#flagr#flagr/antenna,new-source 2006.252.08:19:12.13:checkk5 2006.252.08:19:12.51/chk_autoobs//k5ts1/ autoobs is running! 2006.252.08:19:12.88/chk_autoobs//k5ts2/ autoobs is running! 2006.252.08:19:13.26/chk_autoobs//k5ts3/ autoobs is running! 2006.252.08:19:13.64/chk_autoobs//k5ts4/ autoobs is running! 2006.252.08:19:14.01/chk_obsdata//k5ts1/T2520818??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.08:19:14.39/chk_obsdata//k5ts2/T2520818??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.08:19:14.76/chk_obsdata//k5ts3/T2520818??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.08:19:15.14/chk_obsdata//k5ts4/T2520818??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.08:19:15.84/k5log//k5ts1_log_newline 2006.252.08:19:16.54/k5log//k5ts2_log_newline 2006.252.08:19:17.22/k5log//k5ts3_log_newline 2006.252.08:19:17.91/k5log//k5ts4_log_newline 2006.252.08:19:17.94/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.252.08:19:17.94:4f8m12a=3 2006.252.08:19:17.94$4f8m12a/echo=on 2006.252.08:19:17.94$4f8m12a/pcalon 2006.252.08:19:17.94$pcalon/"no phase cal control is implemented here 2006.252.08:19:17.94$4f8m12a/"tpicd=stop 2006.252.08:19:17.94$4f8m12a/vc4f8 2006.252.08:19:17.94$vc4f8/valo=1,532.99 2006.252.08:19:17.94#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.252.08:19:17.94#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.252.08:19:17.94#ibcon#ireg 17 cls_cnt 0 2006.252.08:19:17.94#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.252.08:19:17.94#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.252.08:19:17.94#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.252.08:19:17.94#ibcon#enter wrdev, iclass 25, count 0 2006.252.08:19:17.94#ibcon#first serial, iclass 25, count 0 2006.252.08:19:17.94#ibcon#enter sib2, iclass 25, count 0 2006.252.08:19:17.94#ibcon#flushed, iclass 25, count 0 2006.252.08:19:17.94#ibcon#about to write, iclass 25, count 0 2006.252.08:19:17.94#ibcon#wrote, iclass 25, count 0 2006.252.08:19:17.94#ibcon#about to read 3, iclass 25, count 0 2006.252.08:19:17.95#ibcon#read 3, iclass 25, count 0 2006.252.08:19:17.95#ibcon#about to read 4, iclass 25, count 0 2006.252.08:19:17.95#ibcon#read 4, iclass 25, count 0 2006.252.08:19:17.95#ibcon#about to read 5, iclass 25, count 0 2006.252.08:19:17.95#ibcon#read 5, iclass 25, count 0 2006.252.08:19:17.95#ibcon#about to read 6, iclass 25, count 0 2006.252.08:19:17.95#ibcon#read 6, iclass 25, count 0 2006.252.08:19:17.95#ibcon#end of sib2, iclass 25, count 0 2006.252.08:19:17.95#ibcon#*mode == 0, iclass 25, count 0 2006.252.08:19:17.95#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.252.08:19:17.95#ibcon#[26=FRQ=01,532.99\r\n] 2006.252.08:19:17.95#ibcon#*before write, iclass 25, count 0 2006.252.08:19:17.95#ibcon#enter sib2, iclass 25, count 0 2006.252.08:19:17.95#ibcon#flushed, iclass 25, count 0 2006.252.08:19:17.95#ibcon#about to write, iclass 25, count 0 2006.252.08:19:17.95#ibcon#wrote, iclass 25, count 0 2006.252.08:19:17.95#ibcon#about to read 3, iclass 25, count 0 2006.252.08:19:18.00#ibcon#read 3, iclass 25, count 0 2006.252.08:19:18.00#ibcon#about to read 4, iclass 25, count 0 2006.252.08:19:18.00#ibcon#read 4, iclass 25, count 0 2006.252.08:19:18.00#ibcon#about to read 5, iclass 25, count 0 2006.252.08:19:18.00#ibcon#read 5, iclass 25, count 0 2006.252.08:19:18.00#ibcon#about to read 6, iclass 25, count 0 2006.252.08:19:18.00#ibcon#read 6, iclass 25, count 0 2006.252.08:19:18.00#ibcon#end of sib2, iclass 25, count 0 2006.252.08:19:18.00#ibcon#*after write, iclass 25, count 0 2006.252.08:19:18.00#ibcon#*before return 0, iclass 25, count 0 2006.252.08:19:18.00#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.252.08:19:18.00#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.252.08:19:18.00#ibcon#about to clear, iclass 25 cls_cnt 0 2006.252.08:19:18.00#ibcon#cleared, iclass 25 cls_cnt 0 2006.252.08:19:18.00$vc4f8/va=1,8 2006.252.08:19:18.00#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.252.08:19:18.00#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.252.08:19:18.00#ibcon#ireg 11 cls_cnt 2 2006.252.08:19:18.00#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.252.08:19:18.00#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.252.08:19:18.00#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.252.08:19:18.00#ibcon#enter wrdev, iclass 27, count 2 2006.252.08:19:18.00#ibcon#first serial, iclass 27, count 2 2006.252.08:19:18.00#ibcon#enter sib2, iclass 27, count 2 2006.252.08:19:18.00#ibcon#flushed, iclass 27, count 2 2006.252.08:19:18.00#ibcon#about to write, iclass 27, count 2 2006.252.08:19:18.00#ibcon#wrote, iclass 27, count 2 2006.252.08:19:18.00#ibcon#about to read 3, iclass 27, count 2 2006.252.08:19:18.02#ibcon#read 3, iclass 27, count 2 2006.252.08:19:18.02#ibcon#about to read 4, iclass 27, count 2 2006.252.08:19:18.02#ibcon#read 4, iclass 27, count 2 2006.252.08:19:18.02#ibcon#about to read 5, iclass 27, count 2 2006.252.08:19:18.02#ibcon#read 5, iclass 27, count 2 2006.252.08:19:18.02#ibcon#about to read 6, iclass 27, count 2 2006.252.08:19:18.02#ibcon#read 6, iclass 27, count 2 2006.252.08:19:18.02#ibcon#end of sib2, iclass 27, count 2 2006.252.08:19:18.02#ibcon#*mode == 0, iclass 27, count 2 2006.252.08:19:18.02#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.252.08:19:18.02#ibcon#[25=AT01-08\r\n] 2006.252.08:19:18.02#ibcon#*before write, iclass 27, count 2 2006.252.08:19:18.02#ibcon#enter sib2, iclass 27, count 2 2006.252.08:19:18.02#ibcon#flushed, iclass 27, count 2 2006.252.08:19:18.02#ibcon#about to write, iclass 27, count 2 2006.252.08:19:18.02#ibcon#wrote, iclass 27, count 2 2006.252.08:19:18.02#ibcon#about to read 3, iclass 27, count 2 2006.252.08:19:18.05#ibcon#read 3, iclass 27, count 2 2006.252.08:19:18.05#ibcon#about to read 4, iclass 27, count 2 2006.252.08:19:18.05#ibcon#read 4, iclass 27, count 2 2006.252.08:19:18.05#ibcon#about to read 5, iclass 27, count 2 2006.252.08:19:18.05#ibcon#read 5, iclass 27, count 2 2006.252.08:19:18.05#ibcon#about to read 6, iclass 27, count 2 2006.252.08:19:18.05#ibcon#read 6, iclass 27, count 2 2006.252.08:19:18.05#ibcon#end of sib2, iclass 27, count 2 2006.252.08:19:18.05#ibcon#*after write, iclass 27, count 2 2006.252.08:19:18.05#ibcon#*before return 0, iclass 27, count 2 2006.252.08:19:18.05#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.252.08:19:18.05#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.252.08:19:18.05#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.252.08:19:18.05#ibcon#ireg 7 cls_cnt 0 2006.252.08:19:18.05#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.252.08:19:18.17#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.252.08:19:18.17#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.252.08:19:18.17#ibcon#enter wrdev, iclass 27, count 0 2006.252.08:19:18.17#ibcon#first serial, iclass 27, count 0 2006.252.08:19:18.17#ibcon#enter sib2, iclass 27, count 0 2006.252.08:19:18.17#ibcon#flushed, iclass 27, count 0 2006.252.08:19:18.17#ibcon#about to write, iclass 27, count 0 2006.252.08:19:18.17#ibcon#wrote, iclass 27, count 0 2006.252.08:19:18.17#ibcon#about to read 3, iclass 27, count 0 2006.252.08:19:18.19#ibcon#read 3, iclass 27, count 0 2006.252.08:19:18.19#ibcon#about to read 4, iclass 27, count 0 2006.252.08:19:18.19#ibcon#read 4, iclass 27, count 0 2006.252.08:19:18.19#ibcon#about to read 5, iclass 27, count 0 2006.252.08:19:18.19#ibcon#read 5, iclass 27, count 0 2006.252.08:19:18.19#ibcon#about to read 6, iclass 27, count 0 2006.252.08:19:18.19#ibcon#read 6, iclass 27, count 0 2006.252.08:19:18.19#ibcon#end of sib2, iclass 27, count 0 2006.252.08:19:18.19#ibcon#*mode == 0, iclass 27, count 0 2006.252.08:19:18.19#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.252.08:19:18.19#ibcon#[25=USB\r\n] 2006.252.08:19:18.19#ibcon#*before write, iclass 27, count 0 2006.252.08:19:18.19#ibcon#enter sib2, iclass 27, count 0 2006.252.08:19:18.19#ibcon#flushed, iclass 27, count 0 2006.252.08:19:18.19#ibcon#about to write, iclass 27, count 0 2006.252.08:19:18.19#ibcon#wrote, iclass 27, count 0 2006.252.08:19:18.19#ibcon#about to read 3, iclass 27, count 0 2006.252.08:19:18.22#ibcon#read 3, iclass 27, count 0 2006.252.08:19:18.22#ibcon#about to read 4, iclass 27, count 0 2006.252.08:19:18.22#ibcon#read 4, iclass 27, count 0 2006.252.08:19:18.22#ibcon#about to read 5, iclass 27, count 0 2006.252.08:19:18.22#ibcon#read 5, iclass 27, count 0 2006.252.08:19:18.22#ibcon#about to read 6, iclass 27, count 0 2006.252.08:19:18.22#ibcon#read 6, iclass 27, count 0 2006.252.08:19:18.22#ibcon#end of sib2, iclass 27, count 0 2006.252.08:19:18.22#ibcon#*after write, iclass 27, count 0 2006.252.08:19:18.22#ibcon#*before return 0, iclass 27, count 0 2006.252.08:19:18.22#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.252.08:19:18.22#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.252.08:19:18.22#ibcon#about to clear, iclass 27 cls_cnt 0 2006.252.08:19:18.22#ibcon#cleared, iclass 27 cls_cnt 0 2006.252.08:19:18.22$vc4f8/valo=2,572.99 2006.252.08:19:18.22#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.252.08:19:18.22#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.252.08:19:18.22#ibcon#ireg 17 cls_cnt 0 2006.252.08:19:18.22#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.252.08:19:18.22#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.252.08:19:18.22#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.252.08:19:18.22#ibcon#enter wrdev, iclass 29, count 0 2006.252.08:19:18.22#ibcon#first serial, iclass 29, count 0 2006.252.08:19:18.22#ibcon#enter sib2, iclass 29, count 0 2006.252.08:19:18.22#ibcon#flushed, iclass 29, count 0 2006.252.08:19:18.22#ibcon#about to write, iclass 29, count 0 2006.252.08:19:18.22#ibcon#wrote, iclass 29, count 0 2006.252.08:19:18.22#ibcon#about to read 3, iclass 29, count 0 2006.252.08:19:18.25#ibcon#read 3, iclass 29, count 0 2006.252.08:19:18.25#ibcon#about to read 4, iclass 29, count 0 2006.252.08:19:18.25#ibcon#read 4, iclass 29, count 0 2006.252.08:19:18.25#ibcon#about to read 5, iclass 29, count 0 2006.252.08:19:18.25#ibcon#read 5, iclass 29, count 0 2006.252.08:19:18.25#ibcon#about to read 6, iclass 29, count 0 2006.252.08:19:18.25#ibcon#read 6, iclass 29, count 0 2006.252.08:19:18.25#ibcon#end of sib2, iclass 29, count 0 2006.252.08:19:18.25#ibcon#*mode == 0, iclass 29, count 0 2006.252.08:19:18.25#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.252.08:19:18.25#ibcon#[26=FRQ=02,572.99\r\n] 2006.252.08:19:18.25#ibcon#*before write, iclass 29, count 0 2006.252.08:19:18.25#ibcon#enter sib2, iclass 29, count 0 2006.252.08:19:18.25#ibcon#flushed, iclass 29, count 0 2006.252.08:19:18.25#ibcon#about to write, iclass 29, count 0 2006.252.08:19:18.25#ibcon#wrote, iclass 29, count 0 2006.252.08:19:18.25#ibcon#about to read 3, iclass 29, count 0 2006.252.08:19:18.29#ibcon#read 3, iclass 29, count 0 2006.252.08:19:18.29#ibcon#about to read 4, iclass 29, count 0 2006.252.08:19:18.29#ibcon#read 4, iclass 29, count 0 2006.252.08:19:18.29#ibcon#about to read 5, iclass 29, count 0 2006.252.08:19:18.29#ibcon#read 5, iclass 29, count 0 2006.252.08:19:18.29#ibcon#about to read 6, iclass 29, count 0 2006.252.08:19:18.29#ibcon#read 6, iclass 29, count 0 2006.252.08:19:18.29#ibcon#end of sib2, iclass 29, count 0 2006.252.08:19:18.29#ibcon#*after write, iclass 29, count 0 2006.252.08:19:18.29#ibcon#*before return 0, iclass 29, count 0 2006.252.08:19:18.29#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.252.08:19:18.29#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.252.08:19:18.29#ibcon#about to clear, iclass 29 cls_cnt 0 2006.252.08:19:18.29#ibcon#cleared, iclass 29 cls_cnt 0 2006.252.08:19:18.29$vc4f8/va=2,7 2006.252.08:19:18.29#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.252.08:19:18.29#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.252.08:19:18.29#ibcon#ireg 11 cls_cnt 2 2006.252.08:19:18.29#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.252.08:19:18.35#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.252.08:19:18.35#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.252.08:19:18.35#ibcon#enter wrdev, iclass 31, count 2 2006.252.08:19:18.35#ibcon#first serial, iclass 31, count 2 2006.252.08:19:18.35#ibcon#enter sib2, iclass 31, count 2 2006.252.08:19:18.35#ibcon#flushed, iclass 31, count 2 2006.252.08:19:18.35#ibcon#about to write, iclass 31, count 2 2006.252.08:19:18.35#ibcon#wrote, iclass 31, count 2 2006.252.08:19:18.35#ibcon#about to read 3, iclass 31, count 2 2006.252.08:19:18.36#ibcon#read 3, iclass 31, count 2 2006.252.08:19:18.36#ibcon#about to read 4, iclass 31, count 2 2006.252.08:19:18.36#ibcon#read 4, iclass 31, count 2 2006.252.08:19:18.36#ibcon#about to read 5, iclass 31, count 2 2006.252.08:19:18.36#ibcon#read 5, iclass 31, count 2 2006.252.08:19:18.36#ibcon#about to read 6, iclass 31, count 2 2006.252.08:19:18.36#ibcon#read 6, iclass 31, count 2 2006.252.08:19:18.36#ibcon#end of sib2, iclass 31, count 2 2006.252.08:19:18.36#ibcon#*mode == 0, iclass 31, count 2 2006.252.08:19:18.36#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.252.08:19:18.36#ibcon#[25=AT02-07\r\n] 2006.252.08:19:18.36#ibcon#*before write, iclass 31, count 2 2006.252.08:19:18.36#ibcon#enter sib2, iclass 31, count 2 2006.252.08:19:18.36#ibcon#flushed, iclass 31, count 2 2006.252.08:19:18.36#ibcon#about to write, iclass 31, count 2 2006.252.08:19:18.36#ibcon#wrote, iclass 31, count 2 2006.252.08:19:18.36#ibcon#about to read 3, iclass 31, count 2 2006.252.08:19:18.39#ibcon#read 3, iclass 31, count 2 2006.252.08:19:18.39#ibcon#about to read 4, iclass 31, count 2 2006.252.08:19:18.39#ibcon#read 4, iclass 31, count 2 2006.252.08:19:18.39#ibcon#about to read 5, iclass 31, count 2 2006.252.08:19:18.39#ibcon#read 5, iclass 31, count 2 2006.252.08:19:18.39#ibcon#about to read 6, iclass 31, count 2 2006.252.08:19:18.39#ibcon#read 6, iclass 31, count 2 2006.252.08:19:18.39#ibcon#end of sib2, iclass 31, count 2 2006.252.08:19:18.39#ibcon#*after write, iclass 31, count 2 2006.252.08:19:18.39#ibcon#*before return 0, iclass 31, count 2 2006.252.08:19:18.39#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.252.08:19:18.39#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.252.08:19:18.39#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.252.08:19:18.39#ibcon#ireg 7 cls_cnt 0 2006.252.08:19:18.39#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.252.08:19:18.51#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.252.08:19:18.51#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.252.08:19:18.51#ibcon#enter wrdev, iclass 31, count 0 2006.252.08:19:18.51#ibcon#first serial, iclass 31, count 0 2006.252.08:19:18.51#ibcon#enter sib2, iclass 31, count 0 2006.252.08:19:18.51#ibcon#flushed, iclass 31, count 0 2006.252.08:19:18.51#ibcon#about to write, iclass 31, count 0 2006.252.08:19:18.51#ibcon#wrote, iclass 31, count 0 2006.252.08:19:18.51#ibcon#about to read 3, iclass 31, count 0 2006.252.08:19:18.53#ibcon#read 3, iclass 31, count 0 2006.252.08:19:18.53#ibcon#about to read 4, iclass 31, count 0 2006.252.08:19:18.53#ibcon#read 4, iclass 31, count 0 2006.252.08:19:18.53#ibcon#about to read 5, iclass 31, count 0 2006.252.08:19:18.53#ibcon#read 5, iclass 31, count 0 2006.252.08:19:18.53#ibcon#about to read 6, iclass 31, count 0 2006.252.08:19:18.53#ibcon#read 6, iclass 31, count 0 2006.252.08:19:18.53#ibcon#end of sib2, iclass 31, count 0 2006.252.08:19:18.53#ibcon#*mode == 0, iclass 31, count 0 2006.252.08:19:18.53#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.252.08:19:18.53#ibcon#[25=USB\r\n] 2006.252.08:19:18.53#ibcon#*before write, iclass 31, count 0 2006.252.08:19:18.53#ibcon#enter sib2, iclass 31, count 0 2006.252.08:19:18.53#ibcon#flushed, iclass 31, count 0 2006.252.08:19:18.53#ibcon#about to write, iclass 31, count 0 2006.252.08:19:18.53#ibcon#wrote, iclass 31, count 0 2006.252.08:19:18.53#ibcon#about to read 3, iclass 31, count 0 2006.252.08:19:18.56#ibcon#read 3, iclass 31, count 0 2006.252.08:19:18.56#ibcon#about to read 4, iclass 31, count 0 2006.252.08:19:18.56#ibcon#read 4, iclass 31, count 0 2006.252.08:19:18.56#ibcon#about to read 5, iclass 31, count 0 2006.252.08:19:18.56#ibcon#read 5, iclass 31, count 0 2006.252.08:19:18.56#ibcon#about to read 6, iclass 31, count 0 2006.252.08:19:18.56#ibcon#read 6, iclass 31, count 0 2006.252.08:19:18.56#ibcon#end of sib2, iclass 31, count 0 2006.252.08:19:18.56#ibcon#*after write, iclass 31, count 0 2006.252.08:19:18.56#ibcon#*before return 0, iclass 31, count 0 2006.252.08:19:18.56#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.252.08:19:18.56#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.252.08:19:18.56#ibcon#about to clear, iclass 31 cls_cnt 0 2006.252.08:19:18.56#ibcon#cleared, iclass 31 cls_cnt 0 2006.252.08:19:18.56$vc4f8/valo=3,672.99 2006.252.08:19:18.56#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.252.08:19:18.56#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.252.08:19:18.56#ibcon#ireg 17 cls_cnt 0 2006.252.08:19:18.56#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.252.08:19:18.56#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.252.08:19:18.56#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.252.08:19:18.56#ibcon#enter wrdev, iclass 33, count 0 2006.252.08:19:18.56#ibcon#first serial, iclass 33, count 0 2006.252.08:19:18.56#ibcon#enter sib2, iclass 33, count 0 2006.252.08:19:18.56#ibcon#flushed, iclass 33, count 0 2006.252.08:19:18.56#ibcon#about to write, iclass 33, count 0 2006.252.08:19:18.56#ibcon#wrote, iclass 33, count 0 2006.252.08:19:18.56#ibcon#about to read 3, iclass 33, count 0 2006.252.08:19:18.58#ibcon#read 3, iclass 33, count 0 2006.252.08:19:18.58#ibcon#about to read 4, iclass 33, count 0 2006.252.08:19:18.58#ibcon#read 4, iclass 33, count 0 2006.252.08:19:18.58#ibcon#about to read 5, iclass 33, count 0 2006.252.08:19:18.58#ibcon#read 5, iclass 33, count 0 2006.252.08:19:18.58#ibcon#about to read 6, iclass 33, count 0 2006.252.08:19:18.58#ibcon#read 6, iclass 33, count 0 2006.252.08:19:18.58#ibcon#end of sib2, iclass 33, count 0 2006.252.08:19:18.58#ibcon#*mode == 0, iclass 33, count 0 2006.252.08:19:18.58#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.252.08:19:18.58#ibcon#[26=FRQ=03,672.99\r\n] 2006.252.08:19:18.58#ibcon#*before write, iclass 33, count 0 2006.252.08:19:18.58#ibcon#enter sib2, iclass 33, count 0 2006.252.08:19:18.58#ibcon#flushed, iclass 33, count 0 2006.252.08:19:18.58#ibcon#about to write, iclass 33, count 0 2006.252.08:19:18.58#ibcon#wrote, iclass 33, count 0 2006.252.08:19:18.58#ibcon#about to read 3, iclass 33, count 0 2006.252.08:19:18.62#ibcon#read 3, iclass 33, count 0 2006.252.08:19:18.62#ibcon#about to read 4, iclass 33, count 0 2006.252.08:19:18.62#ibcon#read 4, iclass 33, count 0 2006.252.08:19:18.62#ibcon#about to read 5, iclass 33, count 0 2006.252.08:19:18.62#ibcon#read 5, iclass 33, count 0 2006.252.08:19:18.62#ibcon#about to read 6, iclass 33, count 0 2006.252.08:19:18.62#ibcon#read 6, iclass 33, count 0 2006.252.08:19:18.62#ibcon#end of sib2, iclass 33, count 0 2006.252.08:19:18.62#ibcon#*after write, iclass 33, count 0 2006.252.08:19:18.62#ibcon#*before return 0, iclass 33, count 0 2006.252.08:19:18.62#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.252.08:19:18.62#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.252.08:19:18.62#ibcon#about to clear, iclass 33 cls_cnt 0 2006.252.08:19:18.62#ibcon#cleared, iclass 33 cls_cnt 0 2006.252.08:19:18.62$vc4f8/va=3,6 2006.252.08:19:18.62#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.252.08:19:18.62#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.252.08:19:18.62#ibcon#ireg 11 cls_cnt 2 2006.252.08:19:18.62#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.252.08:19:18.69#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.252.08:19:18.69#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.252.08:19:18.69#ibcon#enter wrdev, iclass 35, count 2 2006.252.08:19:18.69#ibcon#first serial, iclass 35, count 2 2006.252.08:19:18.69#ibcon#enter sib2, iclass 35, count 2 2006.252.08:19:18.69#ibcon#flushed, iclass 35, count 2 2006.252.08:19:18.69#ibcon#about to write, iclass 35, count 2 2006.252.08:19:18.69#ibcon#wrote, iclass 35, count 2 2006.252.08:19:18.69#ibcon#about to read 3, iclass 35, count 2 2006.252.08:19:18.70#ibcon#read 3, iclass 35, count 2 2006.252.08:19:18.70#ibcon#about to read 4, iclass 35, count 2 2006.252.08:19:18.70#ibcon#read 4, iclass 35, count 2 2006.252.08:19:18.70#ibcon#about to read 5, iclass 35, count 2 2006.252.08:19:18.70#ibcon#read 5, iclass 35, count 2 2006.252.08:19:18.70#ibcon#about to read 6, iclass 35, count 2 2006.252.08:19:18.70#ibcon#read 6, iclass 35, count 2 2006.252.08:19:18.70#ibcon#end of sib2, iclass 35, count 2 2006.252.08:19:18.70#ibcon#*mode == 0, iclass 35, count 2 2006.252.08:19:18.70#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.252.08:19:18.70#ibcon#[25=AT03-06\r\n] 2006.252.08:19:18.70#ibcon#*before write, iclass 35, count 2 2006.252.08:19:18.70#ibcon#enter sib2, iclass 35, count 2 2006.252.08:19:18.70#ibcon#flushed, iclass 35, count 2 2006.252.08:19:18.70#ibcon#about to write, iclass 35, count 2 2006.252.08:19:18.70#ibcon#wrote, iclass 35, count 2 2006.252.08:19:18.70#ibcon#about to read 3, iclass 35, count 2 2006.252.08:19:18.73#ibcon#read 3, iclass 35, count 2 2006.252.08:19:18.73#ibcon#about to read 4, iclass 35, count 2 2006.252.08:19:18.73#ibcon#read 4, iclass 35, count 2 2006.252.08:19:18.73#ibcon#about to read 5, iclass 35, count 2 2006.252.08:19:18.73#ibcon#read 5, iclass 35, count 2 2006.252.08:19:18.73#ibcon#about to read 6, iclass 35, count 2 2006.252.08:19:18.73#ibcon#read 6, iclass 35, count 2 2006.252.08:19:18.73#ibcon#end of sib2, iclass 35, count 2 2006.252.08:19:18.73#ibcon#*after write, iclass 35, count 2 2006.252.08:19:18.73#ibcon#*before return 0, iclass 35, count 2 2006.252.08:19:18.73#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.252.08:19:18.73#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.252.08:19:18.73#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.252.08:19:18.73#ibcon#ireg 7 cls_cnt 0 2006.252.08:19:18.73#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.252.08:19:18.85#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.252.08:19:18.85#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.252.08:19:18.85#ibcon#enter wrdev, iclass 35, count 0 2006.252.08:19:18.85#ibcon#first serial, iclass 35, count 0 2006.252.08:19:18.85#ibcon#enter sib2, iclass 35, count 0 2006.252.08:19:18.85#ibcon#flushed, iclass 35, count 0 2006.252.08:19:18.85#ibcon#about to write, iclass 35, count 0 2006.252.08:19:18.85#ibcon#wrote, iclass 35, count 0 2006.252.08:19:18.85#ibcon#about to read 3, iclass 35, count 0 2006.252.08:19:18.87#ibcon#read 3, iclass 35, count 0 2006.252.08:19:18.87#ibcon#about to read 4, iclass 35, count 0 2006.252.08:19:18.87#ibcon#read 4, iclass 35, count 0 2006.252.08:19:18.87#ibcon#about to read 5, iclass 35, count 0 2006.252.08:19:18.87#ibcon#read 5, iclass 35, count 0 2006.252.08:19:18.87#ibcon#about to read 6, iclass 35, count 0 2006.252.08:19:18.87#ibcon#read 6, iclass 35, count 0 2006.252.08:19:18.87#ibcon#end of sib2, iclass 35, count 0 2006.252.08:19:18.87#ibcon#*mode == 0, iclass 35, count 0 2006.252.08:19:18.87#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.252.08:19:18.87#ibcon#[25=USB\r\n] 2006.252.08:19:18.87#ibcon#*before write, iclass 35, count 0 2006.252.08:19:18.87#ibcon#enter sib2, iclass 35, count 0 2006.252.08:19:18.87#ibcon#flushed, iclass 35, count 0 2006.252.08:19:18.87#ibcon#about to write, iclass 35, count 0 2006.252.08:19:18.87#ibcon#wrote, iclass 35, count 0 2006.252.08:19:18.87#ibcon#about to read 3, iclass 35, count 0 2006.252.08:19:18.90#ibcon#read 3, iclass 35, count 0 2006.252.08:19:18.90#ibcon#about to read 4, iclass 35, count 0 2006.252.08:19:18.90#ibcon#read 4, iclass 35, count 0 2006.252.08:19:18.90#ibcon#about to read 5, iclass 35, count 0 2006.252.08:19:18.90#ibcon#read 5, iclass 35, count 0 2006.252.08:19:18.90#ibcon#about to read 6, iclass 35, count 0 2006.252.08:19:18.90#ibcon#read 6, iclass 35, count 0 2006.252.08:19:18.90#ibcon#end of sib2, iclass 35, count 0 2006.252.08:19:18.90#ibcon#*after write, iclass 35, count 0 2006.252.08:19:18.90#ibcon#*before return 0, iclass 35, count 0 2006.252.08:19:18.90#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.252.08:19:18.90#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.252.08:19:18.90#ibcon#about to clear, iclass 35 cls_cnt 0 2006.252.08:19:18.90#ibcon#cleared, iclass 35 cls_cnt 0 2006.252.08:19:18.90$vc4f8/valo=4,832.99 2006.252.08:19:18.90#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.252.08:19:18.90#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.252.08:19:18.90#ibcon#ireg 17 cls_cnt 0 2006.252.08:19:18.90#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.252.08:19:18.90#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.252.08:19:18.90#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.252.08:19:18.90#ibcon#enter wrdev, iclass 37, count 0 2006.252.08:19:18.90#ibcon#first serial, iclass 37, count 0 2006.252.08:19:18.90#ibcon#enter sib2, iclass 37, count 0 2006.252.08:19:18.90#ibcon#flushed, iclass 37, count 0 2006.252.08:19:18.90#ibcon#about to write, iclass 37, count 0 2006.252.08:19:18.90#ibcon#wrote, iclass 37, count 0 2006.252.08:19:18.90#ibcon#about to read 3, iclass 37, count 0 2006.252.08:19:18.92#ibcon#read 3, iclass 37, count 0 2006.252.08:19:18.92#ibcon#about to read 4, iclass 37, count 0 2006.252.08:19:18.92#ibcon#read 4, iclass 37, count 0 2006.252.08:19:18.92#ibcon#about to read 5, iclass 37, count 0 2006.252.08:19:18.92#ibcon#read 5, iclass 37, count 0 2006.252.08:19:18.92#ibcon#about to read 6, iclass 37, count 0 2006.252.08:19:18.92#ibcon#read 6, iclass 37, count 0 2006.252.08:19:18.92#ibcon#end of sib2, iclass 37, count 0 2006.252.08:19:18.92#ibcon#*mode == 0, iclass 37, count 0 2006.252.08:19:18.92#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.252.08:19:18.92#ibcon#[26=FRQ=04,832.99\r\n] 2006.252.08:19:18.92#ibcon#*before write, iclass 37, count 0 2006.252.08:19:18.92#ibcon#enter sib2, iclass 37, count 0 2006.252.08:19:18.92#ibcon#flushed, iclass 37, count 0 2006.252.08:19:18.92#ibcon#about to write, iclass 37, count 0 2006.252.08:19:18.92#ibcon#wrote, iclass 37, count 0 2006.252.08:19:18.92#ibcon#about to read 3, iclass 37, count 0 2006.252.08:19:18.96#ibcon#read 3, iclass 37, count 0 2006.252.08:19:18.96#ibcon#about to read 4, iclass 37, count 0 2006.252.08:19:18.96#ibcon#read 4, iclass 37, count 0 2006.252.08:19:18.96#ibcon#about to read 5, iclass 37, count 0 2006.252.08:19:18.96#ibcon#read 5, iclass 37, count 0 2006.252.08:19:18.96#ibcon#about to read 6, iclass 37, count 0 2006.252.08:19:18.96#ibcon#read 6, iclass 37, count 0 2006.252.08:19:18.96#ibcon#end of sib2, iclass 37, count 0 2006.252.08:19:18.96#ibcon#*after write, iclass 37, count 0 2006.252.08:19:18.96#ibcon#*before return 0, iclass 37, count 0 2006.252.08:19:18.96#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.252.08:19:18.96#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.252.08:19:18.96#ibcon#about to clear, iclass 37 cls_cnt 0 2006.252.08:19:18.96#ibcon#cleared, iclass 37 cls_cnt 0 2006.252.08:19:18.96$vc4f8/va=4,7 2006.252.08:19:18.96#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.252.08:19:18.96#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.252.08:19:18.96#ibcon#ireg 11 cls_cnt 2 2006.252.08:19:18.96#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.252.08:19:19.03#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.252.08:19:19.03#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.252.08:19:19.03#ibcon#enter wrdev, iclass 39, count 2 2006.252.08:19:19.03#ibcon#first serial, iclass 39, count 2 2006.252.08:19:19.03#ibcon#enter sib2, iclass 39, count 2 2006.252.08:19:19.03#ibcon#flushed, iclass 39, count 2 2006.252.08:19:19.03#ibcon#about to write, iclass 39, count 2 2006.252.08:19:19.03#ibcon#wrote, iclass 39, count 2 2006.252.08:19:19.03#ibcon#about to read 3, iclass 39, count 2 2006.252.08:19:19.04#ibcon#read 3, iclass 39, count 2 2006.252.08:19:19.04#ibcon#about to read 4, iclass 39, count 2 2006.252.08:19:19.04#ibcon#read 4, iclass 39, count 2 2006.252.08:19:19.04#ibcon#about to read 5, iclass 39, count 2 2006.252.08:19:19.04#ibcon#read 5, iclass 39, count 2 2006.252.08:19:19.04#ibcon#about to read 6, iclass 39, count 2 2006.252.08:19:19.04#ibcon#read 6, iclass 39, count 2 2006.252.08:19:19.04#ibcon#end of sib2, iclass 39, count 2 2006.252.08:19:19.04#ibcon#*mode == 0, iclass 39, count 2 2006.252.08:19:19.04#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.252.08:19:19.04#ibcon#[25=AT04-07\r\n] 2006.252.08:19:19.04#ibcon#*before write, iclass 39, count 2 2006.252.08:19:19.04#ibcon#enter sib2, iclass 39, count 2 2006.252.08:19:19.04#ibcon#flushed, iclass 39, count 2 2006.252.08:19:19.04#ibcon#about to write, iclass 39, count 2 2006.252.08:19:19.04#ibcon#wrote, iclass 39, count 2 2006.252.08:19:19.04#ibcon#about to read 3, iclass 39, count 2 2006.252.08:19:19.07#ibcon#read 3, iclass 39, count 2 2006.252.08:19:19.07#ibcon#about to read 4, iclass 39, count 2 2006.252.08:19:19.07#ibcon#read 4, iclass 39, count 2 2006.252.08:19:19.07#ibcon#about to read 5, iclass 39, count 2 2006.252.08:19:19.07#ibcon#read 5, iclass 39, count 2 2006.252.08:19:19.07#ibcon#about to read 6, iclass 39, count 2 2006.252.08:19:19.07#ibcon#read 6, iclass 39, count 2 2006.252.08:19:19.07#ibcon#end of sib2, iclass 39, count 2 2006.252.08:19:19.07#ibcon#*after write, iclass 39, count 2 2006.252.08:19:19.07#ibcon#*before return 0, iclass 39, count 2 2006.252.08:19:19.07#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.252.08:19:19.07#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.252.08:19:19.07#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.252.08:19:19.07#ibcon#ireg 7 cls_cnt 0 2006.252.08:19:19.07#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.252.08:19:19.19#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.252.08:19:19.19#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.252.08:19:19.19#ibcon#enter wrdev, iclass 39, count 0 2006.252.08:19:19.19#ibcon#first serial, iclass 39, count 0 2006.252.08:19:19.19#ibcon#enter sib2, iclass 39, count 0 2006.252.08:19:19.19#ibcon#flushed, iclass 39, count 0 2006.252.08:19:19.19#ibcon#about to write, iclass 39, count 0 2006.252.08:19:19.19#ibcon#wrote, iclass 39, count 0 2006.252.08:19:19.19#ibcon#about to read 3, iclass 39, count 0 2006.252.08:19:19.21#ibcon#read 3, iclass 39, count 0 2006.252.08:19:19.21#ibcon#about to read 4, iclass 39, count 0 2006.252.08:19:19.21#ibcon#read 4, iclass 39, count 0 2006.252.08:19:19.21#ibcon#about to read 5, iclass 39, count 0 2006.252.08:19:19.21#ibcon#read 5, iclass 39, count 0 2006.252.08:19:19.21#ibcon#about to read 6, iclass 39, count 0 2006.252.08:19:19.21#ibcon#read 6, iclass 39, count 0 2006.252.08:19:19.21#ibcon#end of sib2, iclass 39, count 0 2006.252.08:19:19.21#ibcon#*mode == 0, iclass 39, count 0 2006.252.08:19:19.21#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.252.08:19:19.21#ibcon#[25=USB\r\n] 2006.252.08:19:19.21#ibcon#*before write, iclass 39, count 0 2006.252.08:19:19.21#ibcon#enter sib2, iclass 39, count 0 2006.252.08:19:19.21#ibcon#flushed, iclass 39, count 0 2006.252.08:19:19.21#ibcon#about to write, iclass 39, count 0 2006.252.08:19:19.21#ibcon#wrote, iclass 39, count 0 2006.252.08:19:19.21#ibcon#about to read 3, iclass 39, count 0 2006.252.08:19:19.24#ibcon#read 3, iclass 39, count 0 2006.252.08:19:19.24#ibcon#about to read 4, iclass 39, count 0 2006.252.08:19:19.24#ibcon#read 4, iclass 39, count 0 2006.252.08:19:19.24#ibcon#about to read 5, iclass 39, count 0 2006.252.08:19:19.24#ibcon#read 5, iclass 39, count 0 2006.252.08:19:19.24#ibcon#about to read 6, iclass 39, count 0 2006.252.08:19:19.24#ibcon#read 6, iclass 39, count 0 2006.252.08:19:19.24#ibcon#end of sib2, iclass 39, count 0 2006.252.08:19:19.24#ibcon#*after write, iclass 39, count 0 2006.252.08:19:19.24#ibcon#*before return 0, iclass 39, count 0 2006.252.08:19:19.24#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.252.08:19:19.24#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.252.08:19:19.24#ibcon#about to clear, iclass 39 cls_cnt 0 2006.252.08:19:19.24#ibcon#cleared, iclass 39 cls_cnt 0 2006.252.08:19:19.24$vc4f8/valo=5,652.99 2006.252.08:19:19.24#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.252.08:19:19.24#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.252.08:19:19.24#ibcon#ireg 17 cls_cnt 0 2006.252.08:19:19.24#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.252.08:19:19.24#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.252.08:19:19.24#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.252.08:19:19.24#ibcon#enter wrdev, iclass 3, count 0 2006.252.08:19:19.24#ibcon#first serial, iclass 3, count 0 2006.252.08:19:19.24#ibcon#enter sib2, iclass 3, count 0 2006.252.08:19:19.24#ibcon#flushed, iclass 3, count 0 2006.252.08:19:19.24#ibcon#about to write, iclass 3, count 0 2006.252.08:19:19.24#ibcon#wrote, iclass 3, count 0 2006.252.08:19:19.24#ibcon#about to read 3, iclass 3, count 0 2006.252.08:19:19.26#ibcon#read 3, iclass 3, count 0 2006.252.08:19:19.26#ibcon#about to read 4, iclass 3, count 0 2006.252.08:19:19.26#ibcon#read 4, iclass 3, count 0 2006.252.08:19:19.26#ibcon#about to read 5, iclass 3, count 0 2006.252.08:19:19.26#ibcon#read 5, iclass 3, count 0 2006.252.08:19:19.26#ibcon#about to read 6, iclass 3, count 0 2006.252.08:19:19.26#ibcon#read 6, iclass 3, count 0 2006.252.08:19:19.26#ibcon#end of sib2, iclass 3, count 0 2006.252.08:19:19.26#ibcon#*mode == 0, iclass 3, count 0 2006.252.08:19:19.26#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.252.08:19:19.26#ibcon#[26=FRQ=05,652.99\r\n] 2006.252.08:19:19.26#ibcon#*before write, iclass 3, count 0 2006.252.08:19:19.26#ibcon#enter sib2, iclass 3, count 0 2006.252.08:19:19.26#ibcon#flushed, iclass 3, count 0 2006.252.08:19:19.26#ibcon#about to write, iclass 3, count 0 2006.252.08:19:19.26#ibcon#wrote, iclass 3, count 0 2006.252.08:19:19.26#ibcon#about to read 3, iclass 3, count 0 2006.252.08:19:19.30#ibcon#read 3, iclass 3, count 0 2006.252.08:19:19.30#ibcon#about to read 4, iclass 3, count 0 2006.252.08:19:19.30#ibcon#read 4, iclass 3, count 0 2006.252.08:19:19.30#ibcon#about to read 5, iclass 3, count 0 2006.252.08:19:19.30#ibcon#read 5, iclass 3, count 0 2006.252.08:19:19.30#ibcon#about to read 6, iclass 3, count 0 2006.252.08:19:19.30#ibcon#read 6, iclass 3, count 0 2006.252.08:19:19.30#ibcon#end of sib2, iclass 3, count 0 2006.252.08:19:19.30#ibcon#*after write, iclass 3, count 0 2006.252.08:19:19.30#ibcon#*before return 0, iclass 3, count 0 2006.252.08:19:19.30#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.252.08:19:19.30#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.252.08:19:19.30#ibcon#about to clear, iclass 3 cls_cnt 0 2006.252.08:19:19.30#ibcon#cleared, iclass 3 cls_cnt 0 2006.252.08:19:19.30$vc4f8/va=5,7 2006.252.08:19:19.30#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.252.08:19:19.30#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.252.08:19:19.30#ibcon#ireg 11 cls_cnt 2 2006.252.08:19:19.30#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.252.08:19:19.36#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.252.08:19:19.36#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.252.08:19:19.36#ibcon#enter wrdev, iclass 5, count 2 2006.252.08:19:19.36#ibcon#first serial, iclass 5, count 2 2006.252.08:19:19.36#ibcon#enter sib2, iclass 5, count 2 2006.252.08:19:19.36#ibcon#flushed, iclass 5, count 2 2006.252.08:19:19.36#ibcon#about to write, iclass 5, count 2 2006.252.08:19:19.36#ibcon#wrote, iclass 5, count 2 2006.252.08:19:19.36#ibcon#about to read 3, iclass 5, count 2 2006.252.08:19:19.38#ibcon#read 3, iclass 5, count 2 2006.252.08:19:19.38#ibcon#about to read 4, iclass 5, count 2 2006.252.08:19:19.38#ibcon#read 4, iclass 5, count 2 2006.252.08:19:19.38#ibcon#about to read 5, iclass 5, count 2 2006.252.08:19:19.38#ibcon#read 5, iclass 5, count 2 2006.252.08:19:19.38#ibcon#about to read 6, iclass 5, count 2 2006.252.08:19:19.38#ibcon#read 6, iclass 5, count 2 2006.252.08:19:19.38#ibcon#end of sib2, iclass 5, count 2 2006.252.08:19:19.38#ibcon#*mode == 0, iclass 5, count 2 2006.252.08:19:19.38#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.252.08:19:19.38#ibcon#[25=AT05-07\r\n] 2006.252.08:19:19.38#ibcon#*before write, iclass 5, count 2 2006.252.08:19:19.38#ibcon#enter sib2, iclass 5, count 2 2006.252.08:19:19.38#ibcon#flushed, iclass 5, count 2 2006.252.08:19:19.38#ibcon#about to write, iclass 5, count 2 2006.252.08:19:19.38#ibcon#wrote, iclass 5, count 2 2006.252.08:19:19.38#ibcon#about to read 3, iclass 5, count 2 2006.252.08:19:19.42#ibcon#read 3, iclass 5, count 2 2006.252.08:19:19.42#ibcon#about to read 4, iclass 5, count 2 2006.252.08:19:19.42#ibcon#read 4, iclass 5, count 2 2006.252.08:19:19.42#ibcon#about to read 5, iclass 5, count 2 2006.252.08:19:19.42#ibcon#read 5, iclass 5, count 2 2006.252.08:19:19.42#ibcon#about to read 6, iclass 5, count 2 2006.252.08:19:19.42#ibcon#read 6, iclass 5, count 2 2006.252.08:19:19.42#ibcon#end of sib2, iclass 5, count 2 2006.252.08:19:19.42#ibcon#*after write, iclass 5, count 2 2006.252.08:19:19.42#ibcon#*before return 0, iclass 5, count 2 2006.252.08:19:19.42#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.252.08:19:19.42#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.252.08:19:19.42#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.252.08:19:19.42#ibcon#ireg 7 cls_cnt 0 2006.252.08:19:19.42#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.252.08:19:19.53#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.252.08:19:19.53#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.252.08:19:19.53#ibcon#enter wrdev, iclass 5, count 0 2006.252.08:19:19.53#ibcon#first serial, iclass 5, count 0 2006.252.08:19:19.53#ibcon#enter sib2, iclass 5, count 0 2006.252.08:19:19.53#ibcon#flushed, iclass 5, count 0 2006.252.08:19:19.53#ibcon#about to write, iclass 5, count 0 2006.252.08:19:19.53#ibcon#wrote, iclass 5, count 0 2006.252.08:19:19.53#ibcon#about to read 3, iclass 5, count 0 2006.252.08:19:19.55#ibcon#read 3, iclass 5, count 0 2006.252.08:19:19.55#ibcon#about to read 4, iclass 5, count 0 2006.252.08:19:19.55#ibcon#read 4, iclass 5, count 0 2006.252.08:19:19.55#ibcon#about to read 5, iclass 5, count 0 2006.252.08:19:19.55#ibcon#read 5, iclass 5, count 0 2006.252.08:19:19.55#ibcon#about to read 6, iclass 5, count 0 2006.252.08:19:19.55#ibcon#read 6, iclass 5, count 0 2006.252.08:19:19.55#ibcon#end of sib2, iclass 5, count 0 2006.252.08:19:19.55#ibcon#*mode == 0, iclass 5, count 0 2006.252.08:19:19.55#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.252.08:19:19.55#ibcon#[25=USB\r\n] 2006.252.08:19:19.55#ibcon#*before write, iclass 5, count 0 2006.252.08:19:19.55#ibcon#enter sib2, iclass 5, count 0 2006.252.08:19:19.55#ibcon#flushed, iclass 5, count 0 2006.252.08:19:19.55#ibcon#about to write, iclass 5, count 0 2006.252.08:19:19.55#ibcon#wrote, iclass 5, count 0 2006.252.08:19:19.55#ibcon#about to read 3, iclass 5, count 0 2006.252.08:19:19.58#ibcon#read 3, iclass 5, count 0 2006.252.08:19:19.58#ibcon#about to read 4, iclass 5, count 0 2006.252.08:19:19.58#ibcon#read 4, iclass 5, count 0 2006.252.08:19:19.58#ibcon#about to read 5, iclass 5, count 0 2006.252.08:19:19.58#ibcon#read 5, iclass 5, count 0 2006.252.08:19:19.58#ibcon#about to read 6, iclass 5, count 0 2006.252.08:19:19.58#ibcon#read 6, iclass 5, count 0 2006.252.08:19:19.58#ibcon#end of sib2, iclass 5, count 0 2006.252.08:19:19.58#ibcon#*after write, iclass 5, count 0 2006.252.08:19:19.58#ibcon#*before return 0, iclass 5, count 0 2006.252.08:19:19.58#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.252.08:19:19.58#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.252.08:19:19.58#ibcon#about to clear, iclass 5 cls_cnt 0 2006.252.08:19:19.58#ibcon#cleared, iclass 5 cls_cnt 0 2006.252.08:19:19.58$vc4f8/valo=6,772.99 2006.252.08:19:19.58#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.252.08:19:19.58#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.252.08:19:19.58#ibcon#ireg 17 cls_cnt 0 2006.252.08:19:19.58#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.252.08:19:19.58#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.252.08:19:19.58#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.252.08:19:19.58#ibcon#enter wrdev, iclass 7, count 0 2006.252.08:19:19.58#ibcon#first serial, iclass 7, count 0 2006.252.08:19:19.58#ibcon#enter sib2, iclass 7, count 0 2006.252.08:19:19.58#ibcon#flushed, iclass 7, count 0 2006.252.08:19:19.58#ibcon#about to write, iclass 7, count 0 2006.252.08:19:19.58#ibcon#wrote, iclass 7, count 0 2006.252.08:19:19.58#ibcon#about to read 3, iclass 7, count 0 2006.252.08:19:19.60#ibcon#read 3, iclass 7, count 0 2006.252.08:19:19.60#ibcon#about to read 4, iclass 7, count 0 2006.252.08:19:19.60#ibcon#read 4, iclass 7, count 0 2006.252.08:19:19.60#ibcon#about to read 5, iclass 7, count 0 2006.252.08:19:19.60#ibcon#read 5, iclass 7, count 0 2006.252.08:19:19.60#ibcon#about to read 6, iclass 7, count 0 2006.252.08:19:19.60#ibcon#read 6, iclass 7, count 0 2006.252.08:19:19.60#ibcon#end of sib2, iclass 7, count 0 2006.252.08:19:19.60#ibcon#*mode == 0, iclass 7, count 0 2006.252.08:19:19.60#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.252.08:19:19.60#ibcon#[26=FRQ=06,772.99\r\n] 2006.252.08:19:19.60#ibcon#*before write, iclass 7, count 0 2006.252.08:19:19.60#ibcon#enter sib2, iclass 7, count 0 2006.252.08:19:19.60#ibcon#flushed, iclass 7, count 0 2006.252.08:19:19.60#ibcon#about to write, iclass 7, count 0 2006.252.08:19:19.60#ibcon#wrote, iclass 7, count 0 2006.252.08:19:19.60#ibcon#about to read 3, iclass 7, count 0 2006.252.08:19:19.64#ibcon#read 3, iclass 7, count 0 2006.252.08:19:19.64#ibcon#about to read 4, iclass 7, count 0 2006.252.08:19:19.64#ibcon#read 4, iclass 7, count 0 2006.252.08:19:19.64#ibcon#about to read 5, iclass 7, count 0 2006.252.08:19:19.64#ibcon#read 5, iclass 7, count 0 2006.252.08:19:19.64#ibcon#about to read 6, iclass 7, count 0 2006.252.08:19:19.64#ibcon#read 6, iclass 7, count 0 2006.252.08:19:19.64#ibcon#end of sib2, iclass 7, count 0 2006.252.08:19:19.64#ibcon#*after write, iclass 7, count 0 2006.252.08:19:19.64#ibcon#*before return 0, iclass 7, count 0 2006.252.08:19:19.64#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.252.08:19:19.64#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.252.08:19:19.64#ibcon#about to clear, iclass 7 cls_cnt 0 2006.252.08:19:19.64#ibcon#cleared, iclass 7 cls_cnt 0 2006.252.08:19:19.64$vc4f8/va=6,7 2006.252.08:19:19.64#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.252.08:19:19.64#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.252.08:19:19.64#ibcon#ireg 11 cls_cnt 2 2006.252.08:19:19.64#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.252.08:19:19.70#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.252.08:19:19.70#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.252.08:19:19.70#ibcon#enter wrdev, iclass 11, count 2 2006.252.08:19:19.70#ibcon#first serial, iclass 11, count 2 2006.252.08:19:19.70#ibcon#enter sib2, iclass 11, count 2 2006.252.08:19:19.70#ibcon#flushed, iclass 11, count 2 2006.252.08:19:19.70#ibcon#about to write, iclass 11, count 2 2006.252.08:19:19.70#ibcon#wrote, iclass 11, count 2 2006.252.08:19:19.70#ibcon#about to read 3, iclass 11, count 2 2006.252.08:19:19.72#ibcon#read 3, iclass 11, count 2 2006.252.08:19:19.72#ibcon#about to read 4, iclass 11, count 2 2006.252.08:19:19.72#ibcon#read 4, iclass 11, count 2 2006.252.08:19:19.72#ibcon#about to read 5, iclass 11, count 2 2006.252.08:19:19.72#ibcon#read 5, iclass 11, count 2 2006.252.08:19:19.72#ibcon#about to read 6, iclass 11, count 2 2006.252.08:19:19.72#ibcon#read 6, iclass 11, count 2 2006.252.08:19:19.72#ibcon#end of sib2, iclass 11, count 2 2006.252.08:19:19.72#ibcon#*mode == 0, iclass 11, count 2 2006.252.08:19:19.72#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.252.08:19:19.72#ibcon#[25=AT06-07\r\n] 2006.252.08:19:19.72#ibcon#*before write, iclass 11, count 2 2006.252.08:19:19.72#ibcon#enter sib2, iclass 11, count 2 2006.252.08:19:19.72#ibcon#flushed, iclass 11, count 2 2006.252.08:19:19.72#ibcon#about to write, iclass 11, count 2 2006.252.08:19:19.72#ibcon#wrote, iclass 11, count 2 2006.252.08:19:19.72#ibcon#about to read 3, iclass 11, count 2 2006.252.08:19:19.75#ibcon#read 3, iclass 11, count 2 2006.252.08:19:19.75#ibcon#about to read 4, iclass 11, count 2 2006.252.08:19:19.75#ibcon#read 4, iclass 11, count 2 2006.252.08:19:19.75#ibcon#about to read 5, iclass 11, count 2 2006.252.08:19:19.75#ibcon#read 5, iclass 11, count 2 2006.252.08:19:19.75#ibcon#about to read 6, iclass 11, count 2 2006.252.08:19:19.75#ibcon#read 6, iclass 11, count 2 2006.252.08:19:19.75#ibcon#end of sib2, iclass 11, count 2 2006.252.08:19:19.75#ibcon#*after write, iclass 11, count 2 2006.252.08:19:19.75#ibcon#*before return 0, iclass 11, count 2 2006.252.08:19:19.75#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.252.08:19:19.75#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.252.08:19:19.75#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.252.08:19:19.75#ibcon#ireg 7 cls_cnt 0 2006.252.08:19:19.75#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.252.08:19:19.87#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.252.08:19:19.87#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.252.08:19:19.87#ibcon#enter wrdev, iclass 11, count 0 2006.252.08:19:19.87#ibcon#first serial, iclass 11, count 0 2006.252.08:19:19.87#ibcon#enter sib2, iclass 11, count 0 2006.252.08:19:19.87#ibcon#flushed, iclass 11, count 0 2006.252.08:19:19.87#ibcon#about to write, iclass 11, count 0 2006.252.08:19:19.87#ibcon#wrote, iclass 11, count 0 2006.252.08:19:19.87#ibcon#about to read 3, iclass 11, count 0 2006.252.08:19:19.89#ibcon#read 3, iclass 11, count 0 2006.252.08:19:19.89#ibcon#about to read 4, iclass 11, count 0 2006.252.08:19:19.89#ibcon#read 4, iclass 11, count 0 2006.252.08:19:19.89#ibcon#about to read 5, iclass 11, count 0 2006.252.08:19:19.89#ibcon#read 5, iclass 11, count 0 2006.252.08:19:19.89#ibcon#about to read 6, iclass 11, count 0 2006.252.08:19:19.89#ibcon#read 6, iclass 11, count 0 2006.252.08:19:19.89#ibcon#end of sib2, iclass 11, count 0 2006.252.08:19:19.89#ibcon#*mode == 0, iclass 11, count 0 2006.252.08:19:19.89#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.252.08:19:19.89#ibcon#[25=USB\r\n] 2006.252.08:19:19.89#ibcon#*before write, iclass 11, count 0 2006.252.08:19:19.89#ibcon#enter sib2, iclass 11, count 0 2006.252.08:19:19.89#ibcon#flushed, iclass 11, count 0 2006.252.08:19:19.89#ibcon#about to write, iclass 11, count 0 2006.252.08:19:19.89#ibcon#wrote, iclass 11, count 0 2006.252.08:19:19.89#ibcon#about to read 3, iclass 11, count 0 2006.252.08:19:19.92#ibcon#read 3, iclass 11, count 0 2006.252.08:19:19.92#ibcon#about to read 4, iclass 11, count 0 2006.252.08:19:19.92#ibcon#read 4, iclass 11, count 0 2006.252.08:19:19.92#ibcon#about to read 5, iclass 11, count 0 2006.252.08:19:19.92#ibcon#read 5, iclass 11, count 0 2006.252.08:19:19.92#ibcon#about to read 6, iclass 11, count 0 2006.252.08:19:19.92#ibcon#read 6, iclass 11, count 0 2006.252.08:19:19.92#ibcon#end of sib2, iclass 11, count 0 2006.252.08:19:19.92#ibcon#*after write, iclass 11, count 0 2006.252.08:19:19.92#ibcon#*before return 0, iclass 11, count 0 2006.252.08:19:19.92#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.252.08:19:19.92#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.252.08:19:19.92#ibcon#about to clear, iclass 11 cls_cnt 0 2006.252.08:19:19.92#ibcon#cleared, iclass 11 cls_cnt 0 2006.252.08:19:19.92$vc4f8/valo=7,832.99 2006.252.08:19:19.92#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.252.08:19:19.92#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.252.08:19:19.92#ibcon#ireg 17 cls_cnt 0 2006.252.08:19:19.92#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.252.08:19:19.92#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.252.08:19:19.92#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.252.08:19:19.92#ibcon#enter wrdev, iclass 13, count 0 2006.252.08:19:19.92#ibcon#first serial, iclass 13, count 0 2006.252.08:19:19.92#ibcon#enter sib2, iclass 13, count 0 2006.252.08:19:19.92#ibcon#flushed, iclass 13, count 0 2006.252.08:19:19.92#ibcon#about to write, iclass 13, count 0 2006.252.08:19:19.92#ibcon#wrote, iclass 13, count 0 2006.252.08:19:19.92#ibcon#about to read 3, iclass 13, count 0 2006.252.08:19:19.94#ibcon#read 3, iclass 13, count 0 2006.252.08:19:19.94#ibcon#about to read 4, iclass 13, count 0 2006.252.08:19:19.94#ibcon#read 4, iclass 13, count 0 2006.252.08:19:19.94#ibcon#about to read 5, iclass 13, count 0 2006.252.08:19:19.94#ibcon#read 5, iclass 13, count 0 2006.252.08:19:19.94#ibcon#about to read 6, iclass 13, count 0 2006.252.08:19:19.94#ibcon#read 6, iclass 13, count 0 2006.252.08:19:19.94#ibcon#end of sib2, iclass 13, count 0 2006.252.08:19:19.94#ibcon#*mode == 0, iclass 13, count 0 2006.252.08:19:19.94#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.252.08:19:19.94#ibcon#[26=FRQ=07,832.99\r\n] 2006.252.08:19:19.94#ibcon#*before write, iclass 13, count 0 2006.252.08:19:19.94#ibcon#enter sib2, iclass 13, count 0 2006.252.08:19:19.94#ibcon#flushed, iclass 13, count 0 2006.252.08:19:19.94#ibcon#about to write, iclass 13, count 0 2006.252.08:19:19.94#ibcon#wrote, iclass 13, count 0 2006.252.08:19:19.94#ibcon#about to read 3, iclass 13, count 0 2006.252.08:19:19.98#ibcon#read 3, iclass 13, count 0 2006.252.08:19:19.98#ibcon#about to read 4, iclass 13, count 0 2006.252.08:19:19.98#ibcon#read 4, iclass 13, count 0 2006.252.08:19:19.98#ibcon#about to read 5, iclass 13, count 0 2006.252.08:19:19.98#ibcon#read 5, iclass 13, count 0 2006.252.08:19:19.98#ibcon#about to read 6, iclass 13, count 0 2006.252.08:19:19.98#ibcon#read 6, iclass 13, count 0 2006.252.08:19:19.98#ibcon#end of sib2, iclass 13, count 0 2006.252.08:19:19.98#ibcon#*after write, iclass 13, count 0 2006.252.08:19:19.98#ibcon#*before return 0, iclass 13, count 0 2006.252.08:19:19.98#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.252.08:19:19.98#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.252.08:19:19.98#ibcon#about to clear, iclass 13 cls_cnt 0 2006.252.08:19:19.98#ibcon#cleared, iclass 13 cls_cnt 0 2006.252.08:19:19.98$vc4f8/va=7,7 2006.252.08:19:19.98#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.252.08:19:19.98#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.252.08:19:19.98#ibcon#ireg 11 cls_cnt 2 2006.252.08:19:19.98#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.252.08:19:20.04#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.252.08:19:20.04#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.252.08:19:20.04#ibcon#enter wrdev, iclass 15, count 2 2006.252.08:19:20.04#ibcon#first serial, iclass 15, count 2 2006.252.08:19:20.04#ibcon#enter sib2, iclass 15, count 2 2006.252.08:19:20.04#ibcon#flushed, iclass 15, count 2 2006.252.08:19:20.04#ibcon#about to write, iclass 15, count 2 2006.252.08:19:20.04#ibcon#wrote, iclass 15, count 2 2006.252.08:19:20.04#ibcon#about to read 3, iclass 15, count 2 2006.252.08:19:20.06#ibcon#read 3, iclass 15, count 2 2006.252.08:19:20.06#ibcon#about to read 4, iclass 15, count 2 2006.252.08:19:20.06#ibcon#read 4, iclass 15, count 2 2006.252.08:19:20.06#ibcon#about to read 5, iclass 15, count 2 2006.252.08:19:20.06#ibcon#read 5, iclass 15, count 2 2006.252.08:19:20.06#ibcon#about to read 6, iclass 15, count 2 2006.252.08:19:20.06#ibcon#read 6, iclass 15, count 2 2006.252.08:19:20.06#ibcon#end of sib2, iclass 15, count 2 2006.252.08:19:20.06#ibcon#*mode == 0, iclass 15, count 2 2006.252.08:19:20.06#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.252.08:19:20.06#ibcon#[25=AT07-07\r\n] 2006.252.08:19:20.06#ibcon#*before write, iclass 15, count 2 2006.252.08:19:20.06#ibcon#enter sib2, iclass 15, count 2 2006.252.08:19:20.06#ibcon#flushed, iclass 15, count 2 2006.252.08:19:20.06#ibcon#about to write, iclass 15, count 2 2006.252.08:19:20.06#ibcon#wrote, iclass 15, count 2 2006.252.08:19:20.06#ibcon#about to read 3, iclass 15, count 2 2006.252.08:19:20.09#ibcon#read 3, iclass 15, count 2 2006.252.08:19:20.09#ibcon#about to read 4, iclass 15, count 2 2006.252.08:19:20.09#ibcon#read 4, iclass 15, count 2 2006.252.08:19:20.09#ibcon#about to read 5, iclass 15, count 2 2006.252.08:19:20.09#ibcon#read 5, iclass 15, count 2 2006.252.08:19:20.09#ibcon#about to read 6, iclass 15, count 2 2006.252.08:19:20.09#ibcon#read 6, iclass 15, count 2 2006.252.08:19:20.09#ibcon#end of sib2, iclass 15, count 2 2006.252.08:19:20.09#ibcon#*after write, iclass 15, count 2 2006.252.08:19:20.09#ibcon#*before return 0, iclass 15, count 2 2006.252.08:19:20.09#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.252.08:19:20.09#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.252.08:19:20.09#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.252.08:19:20.09#ibcon#ireg 7 cls_cnt 0 2006.252.08:19:20.09#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.252.08:19:20.21#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.252.08:19:20.21#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.252.08:19:20.21#ibcon#enter wrdev, iclass 15, count 0 2006.252.08:19:20.21#ibcon#first serial, iclass 15, count 0 2006.252.08:19:20.21#ibcon#enter sib2, iclass 15, count 0 2006.252.08:19:20.21#ibcon#flushed, iclass 15, count 0 2006.252.08:19:20.21#ibcon#about to write, iclass 15, count 0 2006.252.08:19:20.21#ibcon#wrote, iclass 15, count 0 2006.252.08:19:20.21#ibcon#about to read 3, iclass 15, count 0 2006.252.08:19:20.25#ibcon#read 3, iclass 15, count 0 2006.252.08:19:20.25#ibcon#about to read 4, iclass 15, count 0 2006.252.08:19:20.25#ibcon#read 4, iclass 15, count 0 2006.252.08:19:20.25#ibcon#about to read 5, iclass 15, count 0 2006.252.08:19:20.25#ibcon#read 5, iclass 15, count 0 2006.252.08:19:20.25#ibcon#about to read 6, iclass 15, count 0 2006.252.08:19:20.25#ibcon#read 6, iclass 15, count 0 2006.252.08:19:20.25#ibcon#end of sib2, iclass 15, count 0 2006.252.08:19:20.25#ibcon#*mode == 0, iclass 15, count 0 2006.252.08:19:20.25#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.252.08:19:20.25#ibcon#[25=USB\r\n] 2006.252.08:19:20.25#ibcon#*before write, iclass 15, count 0 2006.252.08:19:20.25#ibcon#enter sib2, iclass 15, count 0 2006.252.08:19:20.25#ibcon#flushed, iclass 15, count 0 2006.252.08:19:20.25#ibcon#about to write, iclass 15, count 0 2006.252.08:19:20.25#ibcon#wrote, iclass 15, count 0 2006.252.08:19:20.25#ibcon#about to read 3, iclass 15, count 0 2006.252.08:19:20.27#ibcon#read 3, iclass 15, count 0 2006.252.08:19:20.27#ibcon#about to read 4, iclass 15, count 0 2006.252.08:19:20.27#ibcon#read 4, iclass 15, count 0 2006.252.08:19:20.27#ibcon#about to read 5, iclass 15, count 0 2006.252.08:19:20.27#ibcon#read 5, iclass 15, count 0 2006.252.08:19:20.27#ibcon#about to read 6, iclass 15, count 0 2006.252.08:19:20.27#ibcon#read 6, iclass 15, count 0 2006.252.08:19:20.27#ibcon#end of sib2, iclass 15, count 0 2006.252.08:19:20.27#ibcon#*after write, iclass 15, count 0 2006.252.08:19:20.27#ibcon#*before return 0, iclass 15, count 0 2006.252.08:19:20.27#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.252.08:19:20.27#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.252.08:19:20.27#ibcon#about to clear, iclass 15 cls_cnt 0 2006.252.08:19:20.27#ibcon#cleared, iclass 15 cls_cnt 0 2006.252.08:19:20.27$vc4f8/valo=8,852.99 2006.252.08:19:20.27#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.252.08:19:20.27#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.252.08:19:20.27#ibcon#ireg 17 cls_cnt 0 2006.252.08:19:20.27#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.252.08:19:20.27#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.252.08:19:20.27#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.252.08:19:20.27#ibcon#enter wrdev, iclass 17, count 0 2006.252.08:19:20.27#ibcon#first serial, iclass 17, count 0 2006.252.08:19:20.27#ibcon#enter sib2, iclass 17, count 0 2006.252.08:19:20.27#ibcon#flushed, iclass 17, count 0 2006.252.08:19:20.27#ibcon#about to write, iclass 17, count 0 2006.252.08:19:20.27#ibcon#wrote, iclass 17, count 0 2006.252.08:19:20.27#ibcon#about to read 3, iclass 17, count 0 2006.252.08:19:20.29#ibcon#read 3, iclass 17, count 0 2006.252.08:19:20.29#ibcon#about to read 4, iclass 17, count 0 2006.252.08:19:20.29#ibcon#read 4, iclass 17, count 0 2006.252.08:19:20.29#ibcon#about to read 5, iclass 17, count 0 2006.252.08:19:20.29#ibcon#read 5, iclass 17, count 0 2006.252.08:19:20.29#ibcon#about to read 6, iclass 17, count 0 2006.252.08:19:20.29#ibcon#read 6, iclass 17, count 0 2006.252.08:19:20.29#ibcon#end of sib2, iclass 17, count 0 2006.252.08:19:20.29#ibcon#*mode == 0, iclass 17, count 0 2006.252.08:19:20.29#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.252.08:19:20.29#ibcon#[26=FRQ=08,852.99\r\n] 2006.252.08:19:20.29#ibcon#*before write, iclass 17, count 0 2006.252.08:19:20.29#ibcon#enter sib2, iclass 17, count 0 2006.252.08:19:20.29#ibcon#flushed, iclass 17, count 0 2006.252.08:19:20.29#ibcon#about to write, iclass 17, count 0 2006.252.08:19:20.29#ibcon#wrote, iclass 17, count 0 2006.252.08:19:20.29#ibcon#about to read 3, iclass 17, count 0 2006.252.08:19:20.33#ibcon#read 3, iclass 17, count 0 2006.252.08:19:20.33#ibcon#about to read 4, iclass 17, count 0 2006.252.08:19:20.33#ibcon#read 4, iclass 17, count 0 2006.252.08:19:20.33#ibcon#about to read 5, iclass 17, count 0 2006.252.08:19:20.33#ibcon#read 5, iclass 17, count 0 2006.252.08:19:20.33#ibcon#about to read 6, iclass 17, count 0 2006.252.08:19:20.33#ibcon#read 6, iclass 17, count 0 2006.252.08:19:20.33#ibcon#end of sib2, iclass 17, count 0 2006.252.08:19:20.33#ibcon#*after write, iclass 17, count 0 2006.252.08:19:20.33#ibcon#*before return 0, iclass 17, count 0 2006.252.08:19:20.33#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.252.08:19:20.33#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.252.08:19:20.33#ibcon#about to clear, iclass 17 cls_cnt 0 2006.252.08:19:20.33#ibcon#cleared, iclass 17 cls_cnt 0 2006.252.08:19:20.34$vc4f8/va=8,7 2006.252.08:19:20.34#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.252.08:19:20.34#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.252.08:19:20.34#ibcon#ireg 11 cls_cnt 2 2006.252.08:19:20.34#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.252.08:19:20.38#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.252.08:19:20.38#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.252.08:19:20.38#ibcon#enter wrdev, iclass 19, count 2 2006.252.08:19:20.38#ibcon#first serial, iclass 19, count 2 2006.252.08:19:20.38#ibcon#enter sib2, iclass 19, count 2 2006.252.08:19:20.38#ibcon#flushed, iclass 19, count 2 2006.252.08:19:20.38#ibcon#about to write, iclass 19, count 2 2006.252.08:19:20.38#ibcon#wrote, iclass 19, count 2 2006.252.08:19:20.38#ibcon#about to read 3, iclass 19, count 2 2006.252.08:19:20.40#ibcon#read 3, iclass 19, count 2 2006.252.08:19:20.40#ibcon#about to read 4, iclass 19, count 2 2006.252.08:19:20.40#ibcon#read 4, iclass 19, count 2 2006.252.08:19:20.40#ibcon#about to read 5, iclass 19, count 2 2006.252.08:19:20.40#ibcon#read 5, iclass 19, count 2 2006.252.08:19:20.40#ibcon#about to read 6, iclass 19, count 2 2006.252.08:19:20.40#ibcon#read 6, iclass 19, count 2 2006.252.08:19:20.40#ibcon#end of sib2, iclass 19, count 2 2006.252.08:19:20.40#ibcon#*mode == 0, iclass 19, count 2 2006.252.08:19:20.40#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.252.08:19:20.40#ibcon#[25=AT08-07\r\n] 2006.252.08:19:20.40#ibcon#*before write, iclass 19, count 2 2006.252.08:19:20.40#ibcon#enter sib2, iclass 19, count 2 2006.252.08:19:20.40#ibcon#flushed, iclass 19, count 2 2006.252.08:19:20.40#ibcon#about to write, iclass 19, count 2 2006.252.08:19:20.40#ibcon#wrote, iclass 19, count 2 2006.252.08:19:20.40#ibcon#about to read 3, iclass 19, count 2 2006.252.08:19:20.43#ibcon#read 3, iclass 19, count 2 2006.252.08:19:20.43#ibcon#about to read 4, iclass 19, count 2 2006.252.08:19:20.43#ibcon#read 4, iclass 19, count 2 2006.252.08:19:20.43#ibcon#about to read 5, iclass 19, count 2 2006.252.08:19:20.43#ibcon#read 5, iclass 19, count 2 2006.252.08:19:20.43#ibcon#about to read 6, iclass 19, count 2 2006.252.08:19:20.43#ibcon#read 6, iclass 19, count 2 2006.252.08:19:20.43#ibcon#end of sib2, iclass 19, count 2 2006.252.08:19:20.43#ibcon#*after write, iclass 19, count 2 2006.252.08:19:20.43#ibcon#*before return 0, iclass 19, count 2 2006.252.08:19:20.43#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.252.08:19:20.43#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.252.08:19:20.43#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.252.08:19:20.43#ibcon#ireg 7 cls_cnt 0 2006.252.08:19:20.43#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.252.08:19:20.55#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.252.08:19:20.55#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.252.08:19:20.55#ibcon#enter wrdev, iclass 19, count 0 2006.252.08:19:20.55#ibcon#first serial, iclass 19, count 0 2006.252.08:19:20.55#ibcon#enter sib2, iclass 19, count 0 2006.252.08:19:20.55#ibcon#flushed, iclass 19, count 0 2006.252.08:19:20.55#ibcon#about to write, iclass 19, count 0 2006.252.08:19:20.55#ibcon#wrote, iclass 19, count 0 2006.252.08:19:20.55#ibcon#about to read 3, iclass 19, count 0 2006.252.08:19:20.57#ibcon#read 3, iclass 19, count 0 2006.252.08:19:20.57#ibcon#about to read 4, iclass 19, count 0 2006.252.08:19:20.57#ibcon#read 4, iclass 19, count 0 2006.252.08:19:20.57#ibcon#about to read 5, iclass 19, count 0 2006.252.08:19:20.57#ibcon#read 5, iclass 19, count 0 2006.252.08:19:20.57#ibcon#about to read 6, iclass 19, count 0 2006.252.08:19:20.57#ibcon#read 6, iclass 19, count 0 2006.252.08:19:20.57#ibcon#end of sib2, iclass 19, count 0 2006.252.08:19:20.57#ibcon#*mode == 0, iclass 19, count 0 2006.252.08:19:20.57#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.252.08:19:20.57#ibcon#[25=USB\r\n] 2006.252.08:19:20.57#ibcon#*before write, iclass 19, count 0 2006.252.08:19:20.57#ibcon#enter sib2, iclass 19, count 0 2006.252.08:19:20.57#ibcon#flushed, iclass 19, count 0 2006.252.08:19:20.57#ibcon#about to write, iclass 19, count 0 2006.252.08:19:20.57#ibcon#wrote, iclass 19, count 0 2006.252.08:19:20.57#ibcon#about to read 3, iclass 19, count 0 2006.252.08:19:20.60#ibcon#read 3, iclass 19, count 0 2006.252.08:19:20.60#ibcon#about to read 4, iclass 19, count 0 2006.252.08:19:20.60#ibcon#read 4, iclass 19, count 0 2006.252.08:19:20.60#ibcon#about to read 5, iclass 19, count 0 2006.252.08:19:20.60#ibcon#read 5, iclass 19, count 0 2006.252.08:19:20.60#ibcon#about to read 6, iclass 19, count 0 2006.252.08:19:20.60#ibcon#read 6, iclass 19, count 0 2006.252.08:19:20.60#ibcon#end of sib2, iclass 19, count 0 2006.252.08:19:20.60#ibcon#*after write, iclass 19, count 0 2006.252.08:19:20.60#ibcon#*before return 0, iclass 19, count 0 2006.252.08:19:20.60#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.252.08:19:20.60#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.252.08:19:20.60#ibcon#about to clear, iclass 19 cls_cnt 0 2006.252.08:19:20.60#ibcon#cleared, iclass 19 cls_cnt 0 2006.252.08:19:20.60$vc4f8/vblo=1,632.99 2006.252.08:19:20.60#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.252.08:19:20.60#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.252.08:19:20.60#ibcon#ireg 17 cls_cnt 0 2006.252.08:19:20.60#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.252.08:19:20.60#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.252.08:19:20.60#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.252.08:19:20.60#ibcon#enter wrdev, iclass 21, count 0 2006.252.08:19:20.60#ibcon#first serial, iclass 21, count 0 2006.252.08:19:20.60#ibcon#enter sib2, iclass 21, count 0 2006.252.08:19:20.60#ibcon#flushed, iclass 21, count 0 2006.252.08:19:20.60#ibcon#about to write, iclass 21, count 0 2006.252.08:19:20.60#ibcon#wrote, iclass 21, count 0 2006.252.08:19:20.60#ibcon#about to read 3, iclass 21, count 0 2006.252.08:19:20.62#ibcon#read 3, iclass 21, count 0 2006.252.08:19:20.62#ibcon#about to read 4, iclass 21, count 0 2006.252.08:19:20.62#ibcon#read 4, iclass 21, count 0 2006.252.08:19:20.62#ibcon#about to read 5, iclass 21, count 0 2006.252.08:19:20.62#ibcon#read 5, iclass 21, count 0 2006.252.08:19:20.62#ibcon#about to read 6, iclass 21, count 0 2006.252.08:19:20.62#ibcon#read 6, iclass 21, count 0 2006.252.08:19:20.62#ibcon#end of sib2, iclass 21, count 0 2006.252.08:19:20.62#ibcon#*mode == 0, iclass 21, count 0 2006.252.08:19:20.62#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.252.08:19:20.62#ibcon#[28=FRQ=01,632.99\r\n] 2006.252.08:19:20.62#ibcon#*before write, iclass 21, count 0 2006.252.08:19:20.62#ibcon#enter sib2, iclass 21, count 0 2006.252.08:19:20.62#ibcon#flushed, iclass 21, count 0 2006.252.08:19:20.62#ibcon#about to write, iclass 21, count 0 2006.252.08:19:20.62#ibcon#wrote, iclass 21, count 0 2006.252.08:19:20.62#ibcon#about to read 3, iclass 21, count 0 2006.252.08:19:20.66#ibcon#read 3, iclass 21, count 0 2006.252.08:19:20.66#ibcon#about to read 4, iclass 21, count 0 2006.252.08:19:20.66#ibcon#read 4, iclass 21, count 0 2006.252.08:19:20.66#ibcon#about to read 5, iclass 21, count 0 2006.252.08:19:20.66#ibcon#read 5, iclass 21, count 0 2006.252.08:19:20.66#ibcon#about to read 6, iclass 21, count 0 2006.252.08:19:20.66#ibcon#read 6, iclass 21, count 0 2006.252.08:19:20.66#ibcon#end of sib2, iclass 21, count 0 2006.252.08:19:20.66#ibcon#*after write, iclass 21, count 0 2006.252.08:19:20.66#ibcon#*before return 0, iclass 21, count 0 2006.252.08:19:20.66#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.252.08:19:20.66#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.252.08:19:20.66#ibcon#about to clear, iclass 21 cls_cnt 0 2006.252.08:19:20.66#ibcon#cleared, iclass 21 cls_cnt 0 2006.252.08:19:20.66$vc4f8/vb=1,4 2006.252.08:19:20.66#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.252.08:19:20.66#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.252.08:19:20.66#ibcon#ireg 11 cls_cnt 2 2006.252.08:19:20.66#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.252.08:19:20.66#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.252.08:19:20.66#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.252.08:19:20.66#ibcon#enter wrdev, iclass 23, count 2 2006.252.08:19:20.66#ibcon#first serial, iclass 23, count 2 2006.252.08:19:20.66#ibcon#enter sib2, iclass 23, count 2 2006.252.08:19:20.66#ibcon#flushed, iclass 23, count 2 2006.252.08:19:20.66#ibcon#about to write, iclass 23, count 2 2006.252.08:19:20.66#ibcon#wrote, iclass 23, count 2 2006.252.08:19:20.66#ibcon#about to read 3, iclass 23, count 2 2006.252.08:19:20.68#ibcon#read 3, iclass 23, count 2 2006.252.08:19:20.68#ibcon#about to read 4, iclass 23, count 2 2006.252.08:19:20.68#ibcon#read 4, iclass 23, count 2 2006.252.08:19:20.68#ibcon#about to read 5, iclass 23, count 2 2006.252.08:19:20.68#ibcon#read 5, iclass 23, count 2 2006.252.08:19:20.68#ibcon#about to read 6, iclass 23, count 2 2006.252.08:19:20.68#ibcon#read 6, iclass 23, count 2 2006.252.08:19:20.68#ibcon#end of sib2, iclass 23, count 2 2006.252.08:19:20.68#ibcon#*mode == 0, iclass 23, count 2 2006.252.08:19:20.68#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.252.08:19:20.68#ibcon#[27=AT01-04\r\n] 2006.252.08:19:20.68#ibcon#*before write, iclass 23, count 2 2006.252.08:19:20.68#ibcon#enter sib2, iclass 23, count 2 2006.252.08:19:20.68#ibcon#flushed, iclass 23, count 2 2006.252.08:19:20.68#ibcon#about to write, iclass 23, count 2 2006.252.08:19:20.68#ibcon#wrote, iclass 23, count 2 2006.252.08:19:20.68#ibcon#about to read 3, iclass 23, count 2 2006.252.08:19:20.71#ibcon#read 3, iclass 23, count 2 2006.252.08:19:20.71#ibcon#about to read 4, iclass 23, count 2 2006.252.08:19:20.71#ibcon#read 4, iclass 23, count 2 2006.252.08:19:20.71#ibcon#about to read 5, iclass 23, count 2 2006.252.08:19:20.71#ibcon#read 5, iclass 23, count 2 2006.252.08:19:20.71#ibcon#about to read 6, iclass 23, count 2 2006.252.08:19:20.71#ibcon#read 6, iclass 23, count 2 2006.252.08:19:20.71#ibcon#end of sib2, iclass 23, count 2 2006.252.08:19:20.71#ibcon#*after write, iclass 23, count 2 2006.252.08:19:20.71#ibcon#*before return 0, iclass 23, count 2 2006.252.08:19:20.71#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.252.08:19:20.71#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.252.08:19:20.71#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.252.08:19:20.71#ibcon#ireg 7 cls_cnt 0 2006.252.08:19:20.71#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.252.08:19:20.83#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.252.08:19:20.83#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.252.08:19:20.83#ibcon#enter wrdev, iclass 23, count 0 2006.252.08:19:20.83#ibcon#first serial, iclass 23, count 0 2006.252.08:19:20.83#ibcon#enter sib2, iclass 23, count 0 2006.252.08:19:20.83#ibcon#flushed, iclass 23, count 0 2006.252.08:19:20.83#ibcon#about to write, iclass 23, count 0 2006.252.08:19:20.83#ibcon#wrote, iclass 23, count 0 2006.252.08:19:20.83#ibcon#about to read 3, iclass 23, count 0 2006.252.08:19:20.85#ibcon#read 3, iclass 23, count 0 2006.252.08:19:20.85#ibcon#about to read 4, iclass 23, count 0 2006.252.08:19:20.85#ibcon#read 4, iclass 23, count 0 2006.252.08:19:20.85#ibcon#about to read 5, iclass 23, count 0 2006.252.08:19:20.85#ibcon#read 5, iclass 23, count 0 2006.252.08:19:20.85#ibcon#about to read 6, iclass 23, count 0 2006.252.08:19:20.85#ibcon#read 6, iclass 23, count 0 2006.252.08:19:20.85#ibcon#end of sib2, iclass 23, count 0 2006.252.08:19:20.85#ibcon#*mode == 0, iclass 23, count 0 2006.252.08:19:20.85#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.252.08:19:20.85#ibcon#[27=USB\r\n] 2006.252.08:19:20.85#ibcon#*before write, iclass 23, count 0 2006.252.08:19:20.85#ibcon#enter sib2, iclass 23, count 0 2006.252.08:19:20.85#ibcon#flushed, iclass 23, count 0 2006.252.08:19:20.85#ibcon#about to write, iclass 23, count 0 2006.252.08:19:20.85#ibcon#wrote, iclass 23, count 0 2006.252.08:19:20.85#ibcon#about to read 3, iclass 23, count 0 2006.252.08:19:20.88#ibcon#read 3, iclass 23, count 0 2006.252.08:19:20.88#ibcon#about to read 4, iclass 23, count 0 2006.252.08:19:20.88#ibcon#read 4, iclass 23, count 0 2006.252.08:19:20.88#ibcon#about to read 5, iclass 23, count 0 2006.252.08:19:20.88#ibcon#read 5, iclass 23, count 0 2006.252.08:19:20.88#ibcon#about to read 6, iclass 23, count 0 2006.252.08:19:20.88#ibcon#read 6, iclass 23, count 0 2006.252.08:19:20.88#ibcon#end of sib2, iclass 23, count 0 2006.252.08:19:20.88#ibcon#*after write, iclass 23, count 0 2006.252.08:19:20.88#ibcon#*before return 0, iclass 23, count 0 2006.252.08:19:20.88#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.252.08:19:20.88#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.252.08:19:20.88#ibcon#about to clear, iclass 23 cls_cnt 0 2006.252.08:19:20.88#ibcon#cleared, iclass 23 cls_cnt 0 2006.252.08:19:20.88$vc4f8/vblo=2,640.99 2006.252.08:19:20.88#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.252.08:19:20.88#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.252.08:19:20.88#ibcon#ireg 17 cls_cnt 0 2006.252.08:19:20.88#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.252.08:19:20.88#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.252.08:19:20.88#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.252.08:19:20.88#ibcon#enter wrdev, iclass 25, count 0 2006.252.08:19:20.88#ibcon#first serial, iclass 25, count 0 2006.252.08:19:20.88#ibcon#enter sib2, iclass 25, count 0 2006.252.08:19:20.88#ibcon#flushed, iclass 25, count 0 2006.252.08:19:20.88#ibcon#about to write, iclass 25, count 0 2006.252.08:19:20.88#ibcon#wrote, iclass 25, count 0 2006.252.08:19:20.88#ibcon#about to read 3, iclass 25, count 0 2006.252.08:19:20.90#ibcon#read 3, iclass 25, count 0 2006.252.08:19:20.90#ibcon#about to read 4, iclass 25, count 0 2006.252.08:19:20.90#ibcon#read 4, iclass 25, count 0 2006.252.08:19:20.90#ibcon#about to read 5, iclass 25, count 0 2006.252.08:19:20.90#ibcon#read 5, iclass 25, count 0 2006.252.08:19:20.90#ibcon#about to read 6, iclass 25, count 0 2006.252.08:19:20.90#ibcon#read 6, iclass 25, count 0 2006.252.08:19:20.90#ibcon#end of sib2, iclass 25, count 0 2006.252.08:19:20.90#ibcon#*mode == 0, iclass 25, count 0 2006.252.08:19:20.90#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.252.08:19:20.90#ibcon#[28=FRQ=02,640.99\r\n] 2006.252.08:19:20.90#ibcon#*before write, iclass 25, count 0 2006.252.08:19:20.90#ibcon#enter sib2, iclass 25, count 0 2006.252.08:19:20.90#ibcon#flushed, iclass 25, count 0 2006.252.08:19:20.90#ibcon#about to write, iclass 25, count 0 2006.252.08:19:20.90#ibcon#wrote, iclass 25, count 0 2006.252.08:19:20.90#ibcon#about to read 3, iclass 25, count 0 2006.252.08:19:20.94#ibcon#read 3, iclass 25, count 0 2006.252.08:19:20.94#ibcon#about to read 4, iclass 25, count 0 2006.252.08:19:20.94#ibcon#read 4, iclass 25, count 0 2006.252.08:19:20.94#ibcon#about to read 5, iclass 25, count 0 2006.252.08:19:20.94#ibcon#read 5, iclass 25, count 0 2006.252.08:19:20.94#ibcon#about to read 6, iclass 25, count 0 2006.252.08:19:20.94#ibcon#read 6, iclass 25, count 0 2006.252.08:19:20.94#ibcon#end of sib2, iclass 25, count 0 2006.252.08:19:20.94#ibcon#*after write, iclass 25, count 0 2006.252.08:19:20.94#ibcon#*before return 0, iclass 25, count 0 2006.252.08:19:20.94#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.252.08:19:20.94#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.252.08:19:20.94#ibcon#about to clear, iclass 25 cls_cnt 0 2006.252.08:19:20.94#ibcon#cleared, iclass 25 cls_cnt 0 2006.252.08:19:20.94$vc4f8/vb=2,5 2006.252.08:19:20.94#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.252.08:19:20.94#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.252.08:19:20.94#ibcon#ireg 11 cls_cnt 2 2006.252.08:19:20.94#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.252.08:19:21.00#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.252.08:19:21.00#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.252.08:19:21.00#ibcon#enter wrdev, iclass 27, count 2 2006.252.08:19:21.00#ibcon#first serial, iclass 27, count 2 2006.252.08:19:21.00#ibcon#enter sib2, iclass 27, count 2 2006.252.08:19:21.00#ibcon#flushed, iclass 27, count 2 2006.252.08:19:21.00#ibcon#about to write, iclass 27, count 2 2006.252.08:19:21.00#ibcon#wrote, iclass 27, count 2 2006.252.08:19:21.00#ibcon#about to read 3, iclass 27, count 2 2006.252.08:19:21.02#ibcon#read 3, iclass 27, count 2 2006.252.08:19:21.02#ibcon#about to read 4, iclass 27, count 2 2006.252.08:19:21.02#ibcon#read 4, iclass 27, count 2 2006.252.08:19:21.02#ibcon#about to read 5, iclass 27, count 2 2006.252.08:19:21.02#ibcon#read 5, iclass 27, count 2 2006.252.08:19:21.02#ibcon#about to read 6, iclass 27, count 2 2006.252.08:19:21.02#ibcon#read 6, iclass 27, count 2 2006.252.08:19:21.02#ibcon#end of sib2, iclass 27, count 2 2006.252.08:19:21.02#ibcon#*mode == 0, iclass 27, count 2 2006.252.08:19:21.02#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.252.08:19:21.02#ibcon#[27=AT02-05\r\n] 2006.252.08:19:21.02#ibcon#*before write, iclass 27, count 2 2006.252.08:19:21.02#ibcon#enter sib2, iclass 27, count 2 2006.252.08:19:21.02#ibcon#flushed, iclass 27, count 2 2006.252.08:19:21.02#ibcon#about to write, iclass 27, count 2 2006.252.08:19:21.02#ibcon#wrote, iclass 27, count 2 2006.252.08:19:21.02#ibcon#about to read 3, iclass 27, count 2 2006.252.08:19:21.05#ibcon#read 3, iclass 27, count 2 2006.252.08:19:21.05#ibcon#about to read 4, iclass 27, count 2 2006.252.08:19:21.05#ibcon#read 4, iclass 27, count 2 2006.252.08:19:21.05#ibcon#about to read 5, iclass 27, count 2 2006.252.08:19:21.05#ibcon#read 5, iclass 27, count 2 2006.252.08:19:21.05#ibcon#about to read 6, iclass 27, count 2 2006.252.08:19:21.05#ibcon#read 6, iclass 27, count 2 2006.252.08:19:21.05#ibcon#end of sib2, iclass 27, count 2 2006.252.08:19:21.05#ibcon#*after write, iclass 27, count 2 2006.252.08:19:21.05#ibcon#*before return 0, iclass 27, count 2 2006.252.08:19:21.05#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.252.08:19:21.05#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.252.08:19:21.05#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.252.08:19:21.05#ibcon#ireg 7 cls_cnt 0 2006.252.08:19:21.05#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.252.08:19:21.17#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.252.08:19:21.17#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.252.08:19:21.17#ibcon#enter wrdev, iclass 27, count 0 2006.252.08:19:21.17#ibcon#first serial, iclass 27, count 0 2006.252.08:19:21.17#ibcon#enter sib2, iclass 27, count 0 2006.252.08:19:21.17#ibcon#flushed, iclass 27, count 0 2006.252.08:19:21.17#ibcon#about to write, iclass 27, count 0 2006.252.08:19:21.17#ibcon#wrote, iclass 27, count 0 2006.252.08:19:21.17#ibcon#about to read 3, iclass 27, count 0 2006.252.08:19:21.19#ibcon#read 3, iclass 27, count 0 2006.252.08:19:21.19#ibcon#about to read 4, iclass 27, count 0 2006.252.08:19:21.19#ibcon#read 4, iclass 27, count 0 2006.252.08:19:21.19#ibcon#about to read 5, iclass 27, count 0 2006.252.08:19:21.19#ibcon#read 5, iclass 27, count 0 2006.252.08:19:21.19#ibcon#about to read 6, iclass 27, count 0 2006.252.08:19:21.19#ibcon#read 6, iclass 27, count 0 2006.252.08:19:21.19#ibcon#end of sib2, iclass 27, count 0 2006.252.08:19:21.19#ibcon#*mode == 0, iclass 27, count 0 2006.252.08:19:21.19#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.252.08:19:21.19#ibcon#[27=USB\r\n] 2006.252.08:19:21.19#ibcon#*before write, iclass 27, count 0 2006.252.08:19:21.19#ibcon#enter sib2, iclass 27, count 0 2006.252.08:19:21.19#ibcon#flushed, iclass 27, count 0 2006.252.08:19:21.19#ibcon#about to write, iclass 27, count 0 2006.252.08:19:21.19#ibcon#wrote, iclass 27, count 0 2006.252.08:19:21.19#ibcon#about to read 3, iclass 27, count 0 2006.252.08:19:21.22#ibcon#read 3, iclass 27, count 0 2006.252.08:19:21.22#ibcon#about to read 4, iclass 27, count 0 2006.252.08:19:21.22#ibcon#read 4, iclass 27, count 0 2006.252.08:19:21.22#ibcon#about to read 5, iclass 27, count 0 2006.252.08:19:21.22#ibcon#read 5, iclass 27, count 0 2006.252.08:19:21.22#ibcon#about to read 6, iclass 27, count 0 2006.252.08:19:21.22#ibcon#read 6, iclass 27, count 0 2006.252.08:19:21.22#ibcon#end of sib2, iclass 27, count 0 2006.252.08:19:21.22#ibcon#*after write, iclass 27, count 0 2006.252.08:19:21.22#ibcon#*before return 0, iclass 27, count 0 2006.252.08:19:21.22#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.252.08:19:21.22#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.252.08:19:21.22#ibcon#about to clear, iclass 27 cls_cnt 0 2006.252.08:19:21.22#ibcon#cleared, iclass 27 cls_cnt 0 2006.252.08:19:21.22$vc4f8/vblo=3,656.99 2006.252.08:19:21.22#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.252.08:19:21.22#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.252.08:19:21.22#ibcon#ireg 17 cls_cnt 0 2006.252.08:19:21.22#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.252.08:19:21.22#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.252.08:19:21.22#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.252.08:19:21.22#ibcon#enter wrdev, iclass 29, count 0 2006.252.08:19:21.22#ibcon#first serial, iclass 29, count 0 2006.252.08:19:21.22#ibcon#enter sib2, iclass 29, count 0 2006.252.08:19:21.22#ibcon#flushed, iclass 29, count 0 2006.252.08:19:21.22#ibcon#about to write, iclass 29, count 0 2006.252.08:19:21.22#ibcon#wrote, iclass 29, count 0 2006.252.08:19:21.22#ibcon#about to read 3, iclass 29, count 0 2006.252.08:19:21.24#ibcon#read 3, iclass 29, count 0 2006.252.08:19:21.24#ibcon#about to read 4, iclass 29, count 0 2006.252.08:19:21.24#ibcon#read 4, iclass 29, count 0 2006.252.08:19:21.24#ibcon#about to read 5, iclass 29, count 0 2006.252.08:19:21.24#ibcon#read 5, iclass 29, count 0 2006.252.08:19:21.24#ibcon#about to read 6, iclass 29, count 0 2006.252.08:19:21.24#ibcon#read 6, iclass 29, count 0 2006.252.08:19:21.24#ibcon#end of sib2, iclass 29, count 0 2006.252.08:19:21.24#ibcon#*mode == 0, iclass 29, count 0 2006.252.08:19:21.24#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.252.08:19:21.24#ibcon#[28=FRQ=03,656.99\r\n] 2006.252.08:19:21.24#ibcon#*before write, iclass 29, count 0 2006.252.08:19:21.24#ibcon#enter sib2, iclass 29, count 0 2006.252.08:19:21.24#ibcon#flushed, iclass 29, count 0 2006.252.08:19:21.24#ibcon#about to write, iclass 29, count 0 2006.252.08:19:21.24#ibcon#wrote, iclass 29, count 0 2006.252.08:19:21.24#ibcon#about to read 3, iclass 29, count 0 2006.252.08:19:21.28#ibcon#read 3, iclass 29, count 0 2006.252.08:19:21.28#ibcon#about to read 4, iclass 29, count 0 2006.252.08:19:21.28#ibcon#read 4, iclass 29, count 0 2006.252.08:19:21.28#ibcon#about to read 5, iclass 29, count 0 2006.252.08:19:21.28#ibcon#read 5, iclass 29, count 0 2006.252.08:19:21.28#ibcon#about to read 6, iclass 29, count 0 2006.252.08:19:21.28#ibcon#read 6, iclass 29, count 0 2006.252.08:19:21.28#ibcon#end of sib2, iclass 29, count 0 2006.252.08:19:21.28#ibcon#*after write, iclass 29, count 0 2006.252.08:19:21.28#ibcon#*before return 0, iclass 29, count 0 2006.252.08:19:21.28#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.252.08:19:21.28#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.252.08:19:21.28#ibcon#about to clear, iclass 29 cls_cnt 0 2006.252.08:19:21.28#ibcon#cleared, iclass 29 cls_cnt 0 2006.252.08:19:21.28$vc4f8/vb=3,4 2006.252.08:19:21.28#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.252.08:19:21.28#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.252.08:19:21.28#ibcon#ireg 11 cls_cnt 2 2006.252.08:19:21.28#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.252.08:19:21.34#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.252.08:19:21.34#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.252.08:19:21.34#ibcon#enter wrdev, iclass 31, count 2 2006.252.08:19:21.34#ibcon#first serial, iclass 31, count 2 2006.252.08:19:21.34#ibcon#enter sib2, iclass 31, count 2 2006.252.08:19:21.34#ibcon#flushed, iclass 31, count 2 2006.252.08:19:21.34#ibcon#about to write, iclass 31, count 2 2006.252.08:19:21.34#ibcon#wrote, iclass 31, count 2 2006.252.08:19:21.34#ibcon#about to read 3, iclass 31, count 2 2006.252.08:19:21.36#ibcon#read 3, iclass 31, count 2 2006.252.08:19:21.36#ibcon#about to read 4, iclass 31, count 2 2006.252.08:19:21.36#ibcon#read 4, iclass 31, count 2 2006.252.08:19:21.36#ibcon#about to read 5, iclass 31, count 2 2006.252.08:19:21.36#ibcon#read 5, iclass 31, count 2 2006.252.08:19:21.36#ibcon#about to read 6, iclass 31, count 2 2006.252.08:19:21.36#ibcon#read 6, iclass 31, count 2 2006.252.08:19:21.36#ibcon#end of sib2, iclass 31, count 2 2006.252.08:19:21.36#ibcon#*mode == 0, iclass 31, count 2 2006.252.08:19:21.36#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.252.08:19:21.36#ibcon#[27=AT03-04\r\n] 2006.252.08:19:21.36#ibcon#*before write, iclass 31, count 2 2006.252.08:19:21.36#ibcon#enter sib2, iclass 31, count 2 2006.252.08:19:21.36#ibcon#flushed, iclass 31, count 2 2006.252.08:19:21.36#ibcon#about to write, iclass 31, count 2 2006.252.08:19:21.36#ibcon#wrote, iclass 31, count 2 2006.252.08:19:21.36#ibcon#about to read 3, iclass 31, count 2 2006.252.08:19:21.39#ibcon#read 3, iclass 31, count 2 2006.252.08:19:21.39#ibcon#about to read 4, iclass 31, count 2 2006.252.08:19:21.39#ibcon#read 4, iclass 31, count 2 2006.252.08:19:21.39#ibcon#about to read 5, iclass 31, count 2 2006.252.08:19:21.39#ibcon#read 5, iclass 31, count 2 2006.252.08:19:21.39#ibcon#about to read 6, iclass 31, count 2 2006.252.08:19:21.39#ibcon#read 6, iclass 31, count 2 2006.252.08:19:21.39#ibcon#end of sib2, iclass 31, count 2 2006.252.08:19:21.39#ibcon#*after write, iclass 31, count 2 2006.252.08:19:21.39#ibcon#*before return 0, iclass 31, count 2 2006.252.08:19:21.39#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.252.08:19:21.39#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.252.08:19:21.39#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.252.08:19:21.39#ibcon#ireg 7 cls_cnt 0 2006.252.08:19:21.39#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.252.08:19:21.51#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.252.08:19:21.51#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.252.08:19:21.51#ibcon#enter wrdev, iclass 31, count 0 2006.252.08:19:21.51#ibcon#first serial, iclass 31, count 0 2006.252.08:19:21.51#ibcon#enter sib2, iclass 31, count 0 2006.252.08:19:21.51#ibcon#flushed, iclass 31, count 0 2006.252.08:19:21.51#ibcon#about to write, iclass 31, count 0 2006.252.08:19:21.51#ibcon#wrote, iclass 31, count 0 2006.252.08:19:21.51#ibcon#about to read 3, iclass 31, count 0 2006.252.08:19:21.53#ibcon#read 3, iclass 31, count 0 2006.252.08:19:21.53#ibcon#about to read 4, iclass 31, count 0 2006.252.08:19:21.53#ibcon#read 4, iclass 31, count 0 2006.252.08:19:21.53#ibcon#about to read 5, iclass 31, count 0 2006.252.08:19:21.53#ibcon#read 5, iclass 31, count 0 2006.252.08:19:21.53#ibcon#about to read 6, iclass 31, count 0 2006.252.08:19:21.53#ibcon#read 6, iclass 31, count 0 2006.252.08:19:21.53#ibcon#end of sib2, iclass 31, count 0 2006.252.08:19:21.53#ibcon#*mode == 0, iclass 31, count 0 2006.252.08:19:21.53#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.252.08:19:21.53#ibcon#[27=USB\r\n] 2006.252.08:19:21.53#ibcon#*before write, iclass 31, count 0 2006.252.08:19:21.53#ibcon#enter sib2, iclass 31, count 0 2006.252.08:19:21.53#ibcon#flushed, iclass 31, count 0 2006.252.08:19:21.53#ibcon#about to write, iclass 31, count 0 2006.252.08:19:21.53#ibcon#wrote, iclass 31, count 0 2006.252.08:19:21.53#ibcon#about to read 3, iclass 31, count 0 2006.252.08:19:21.56#ibcon#read 3, iclass 31, count 0 2006.252.08:19:21.56#ibcon#about to read 4, iclass 31, count 0 2006.252.08:19:21.56#ibcon#read 4, iclass 31, count 0 2006.252.08:19:21.56#ibcon#about to read 5, iclass 31, count 0 2006.252.08:19:21.56#ibcon#read 5, iclass 31, count 0 2006.252.08:19:21.56#ibcon#about to read 6, iclass 31, count 0 2006.252.08:19:21.56#ibcon#read 6, iclass 31, count 0 2006.252.08:19:21.56#ibcon#end of sib2, iclass 31, count 0 2006.252.08:19:21.56#ibcon#*after write, iclass 31, count 0 2006.252.08:19:21.56#ibcon#*before return 0, iclass 31, count 0 2006.252.08:19:21.56#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.252.08:19:21.56#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.252.08:19:21.56#ibcon#about to clear, iclass 31 cls_cnt 0 2006.252.08:19:21.56#ibcon#cleared, iclass 31 cls_cnt 0 2006.252.08:19:21.56$vc4f8/vblo=4,712.99 2006.252.08:19:21.56#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.252.08:19:21.56#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.252.08:19:21.56#ibcon#ireg 17 cls_cnt 0 2006.252.08:19:21.56#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.252.08:19:21.56#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.252.08:19:21.56#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.252.08:19:21.56#ibcon#enter wrdev, iclass 33, count 0 2006.252.08:19:21.56#ibcon#first serial, iclass 33, count 0 2006.252.08:19:21.56#ibcon#enter sib2, iclass 33, count 0 2006.252.08:19:21.56#ibcon#flushed, iclass 33, count 0 2006.252.08:19:21.56#ibcon#about to write, iclass 33, count 0 2006.252.08:19:21.56#ibcon#wrote, iclass 33, count 0 2006.252.08:19:21.56#ibcon#about to read 3, iclass 33, count 0 2006.252.08:19:21.58#ibcon#read 3, iclass 33, count 0 2006.252.08:19:21.58#ibcon#about to read 4, iclass 33, count 0 2006.252.08:19:21.58#ibcon#read 4, iclass 33, count 0 2006.252.08:19:21.58#ibcon#about to read 5, iclass 33, count 0 2006.252.08:19:21.58#ibcon#read 5, iclass 33, count 0 2006.252.08:19:21.58#ibcon#about to read 6, iclass 33, count 0 2006.252.08:19:21.58#ibcon#read 6, iclass 33, count 0 2006.252.08:19:21.58#ibcon#end of sib2, iclass 33, count 0 2006.252.08:19:21.58#ibcon#*mode == 0, iclass 33, count 0 2006.252.08:19:21.58#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.252.08:19:21.58#ibcon#[28=FRQ=04,712.99\r\n] 2006.252.08:19:21.58#ibcon#*before write, iclass 33, count 0 2006.252.08:19:21.58#ibcon#enter sib2, iclass 33, count 0 2006.252.08:19:21.58#ibcon#flushed, iclass 33, count 0 2006.252.08:19:21.58#ibcon#about to write, iclass 33, count 0 2006.252.08:19:21.58#ibcon#wrote, iclass 33, count 0 2006.252.08:19:21.58#ibcon#about to read 3, iclass 33, count 0 2006.252.08:19:21.62#ibcon#read 3, iclass 33, count 0 2006.252.08:19:21.62#ibcon#about to read 4, iclass 33, count 0 2006.252.08:19:21.62#ibcon#read 4, iclass 33, count 0 2006.252.08:19:21.62#ibcon#about to read 5, iclass 33, count 0 2006.252.08:19:21.62#ibcon#read 5, iclass 33, count 0 2006.252.08:19:21.62#ibcon#about to read 6, iclass 33, count 0 2006.252.08:19:21.62#ibcon#read 6, iclass 33, count 0 2006.252.08:19:21.62#ibcon#end of sib2, iclass 33, count 0 2006.252.08:19:21.62#ibcon#*after write, iclass 33, count 0 2006.252.08:19:21.62#ibcon#*before return 0, iclass 33, count 0 2006.252.08:19:21.62#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.252.08:19:21.62#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.252.08:19:21.62#ibcon#about to clear, iclass 33 cls_cnt 0 2006.252.08:19:21.62#ibcon#cleared, iclass 33 cls_cnt 0 2006.252.08:19:21.62$vc4f8/vb=4,4 2006.252.08:19:21.62#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.252.08:19:21.62#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.252.08:19:21.62#ibcon#ireg 11 cls_cnt 2 2006.252.08:19:21.62#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.252.08:19:21.68#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.252.08:19:21.68#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.252.08:19:21.68#ibcon#enter wrdev, iclass 35, count 2 2006.252.08:19:21.68#ibcon#first serial, iclass 35, count 2 2006.252.08:19:21.68#ibcon#enter sib2, iclass 35, count 2 2006.252.08:19:21.68#ibcon#flushed, iclass 35, count 2 2006.252.08:19:21.68#ibcon#about to write, iclass 35, count 2 2006.252.08:19:21.68#ibcon#wrote, iclass 35, count 2 2006.252.08:19:21.68#ibcon#about to read 3, iclass 35, count 2 2006.252.08:19:21.70#ibcon#read 3, iclass 35, count 2 2006.252.08:19:21.70#ibcon#about to read 4, iclass 35, count 2 2006.252.08:19:21.70#ibcon#read 4, iclass 35, count 2 2006.252.08:19:21.70#ibcon#about to read 5, iclass 35, count 2 2006.252.08:19:21.70#ibcon#read 5, iclass 35, count 2 2006.252.08:19:21.70#ibcon#about to read 6, iclass 35, count 2 2006.252.08:19:21.70#ibcon#read 6, iclass 35, count 2 2006.252.08:19:21.70#ibcon#end of sib2, iclass 35, count 2 2006.252.08:19:21.70#ibcon#*mode == 0, iclass 35, count 2 2006.252.08:19:21.70#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.252.08:19:21.70#ibcon#[27=AT04-04\r\n] 2006.252.08:19:21.70#ibcon#*before write, iclass 35, count 2 2006.252.08:19:21.70#ibcon#enter sib2, iclass 35, count 2 2006.252.08:19:21.70#ibcon#flushed, iclass 35, count 2 2006.252.08:19:21.70#ibcon#about to write, iclass 35, count 2 2006.252.08:19:21.70#ibcon#wrote, iclass 35, count 2 2006.252.08:19:21.70#ibcon#about to read 3, iclass 35, count 2 2006.252.08:19:21.73#ibcon#read 3, iclass 35, count 2 2006.252.08:19:21.73#ibcon#about to read 4, iclass 35, count 2 2006.252.08:19:21.73#ibcon#read 4, iclass 35, count 2 2006.252.08:19:21.73#ibcon#about to read 5, iclass 35, count 2 2006.252.08:19:21.73#ibcon#read 5, iclass 35, count 2 2006.252.08:19:21.73#ibcon#about to read 6, iclass 35, count 2 2006.252.08:19:21.73#ibcon#read 6, iclass 35, count 2 2006.252.08:19:21.73#ibcon#end of sib2, iclass 35, count 2 2006.252.08:19:21.73#ibcon#*after write, iclass 35, count 2 2006.252.08:19:21.73#ibcon#*before return 0, iclass 35, count 2 2006.252.08:19:21.73#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.252.08:19:21.73#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.252.08:19:21.73#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.252.08:19:21.73#ibcon#ireg 7 cls_cnt 0 2006.252.08:19:21.73#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.252.08:19:21.85#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.252.08:19:21.85#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.252.08:19:21.85#ibcon#enter wrdev, iclass 35, count 0 2006.252.08:19:21.85#ibcon#first serial, iclass 35, count 0 2006.252.08:19:21.85#ibcon#enter sib2, iclass 35, count 0 2006.252.08:19:21.85#ibcon#flushed, iclass 35, count 0 2006.252.08:19:21.85#ibcon#about to write, iclass 35, count 0 2006.252.08:19:21.85#ibcon#wrote, iclass 35, count 0 2006.252.08:19:21.85#ibcon#about to read 3, iclass 35, count 0 2006.252.08:19:21.87#ibcon#read 3, iclass 35, count 0 2006.252.08:19:21.87#ibcon#about to read 4, iclass 35, count 0 2006.252.08:19:21.87#ibcon#read 4, iclass 35, count 0 2006.252.08:19:21.87#ibcon#about to read 5, iclass 35, count 0 2006.252.08:19:21.87#ibcon#read 5, iclass 35, count 0 2006.252.08:19:21.87#ibcon#about to read 6, iclass 35, count 0 2006.252.08:19:21.87#ibcon#read 6, iclass 35, count 0 2006.252.08:19:21.87#ibcon#end of sib2, iclass 35, count 0 2006.252.08:19:21.87#ibcon#*mode == 0, iclass 35, count 0 2006.252.08:19:21.87#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.252.08:19:21.87#ibcon#[27=USB\r\n] 2006.252.08:19:21.87#ibcon#*before write, iclass 35, count 0 2006.252.08:19:21.87#ibcon#enter sib2, iclass 35, count 0 2006.252.08:19:21.87#ibcon#flushed, iclass 35, count 0 2006.252.08:19:21.87#ibcon#about to write, iclass 35, count 0 2006.252.08:19:21.87#ibcon#wrote, iclass 35, count 0 2006.252.08:19:21.87#ibcon#about to read 3, iclass 35, count 0 2006.252.08:19:21.90#ibcon#read 3, iclass 35, count 0 2006.252.08:19:21.90#ibcon#about to read 4, iclass 35, count 0 2006.252.08:19:21.90#ibcon#read 4, iclass 35, count 0 2006.252.08:19:21.90#ibcon#about to read 5, iclass 35, count 0 2006.252.08:19:21.90#ibcon#read 5, iclass 35, count 0 2006.252.08:19:21.90#ibcon#about to read 6, iclass 35, count 0 2006.252.08:19:21.90#ibcon#read 6, iclass 35, count 0 2006.252.08:19:21.90#ibcon#end of sib2, iclass 35, count 0 2006.252.08:19:21.90#ibcon#*after write, iclass 35, count 0 2006.252.08:19:21.90#ibcon#*before return 0, iclass 35, count 0 2006.252.08:19:21.90#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.252.08:19:21.90#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.252.08:19:21.90#ibcon#about to clear, iclass 35 cls_cnt 0 2006.252.08:19:21.90#ibcon#cleared, iclass 35 cls_cnt 0 2006.252.08:19:21.90$vc4f8/vblo=5,744.99 2006.252.08:19:21.90#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.252.08:19:21.90#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.252.08:19:21.90#ibcon#ireg 17 cls_cnt 0 2006.252.08:19:21.90#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.252.08:19:21.90#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.252.08:19:21.90#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.252.08:19:21.90#ibcon#enter wrdev, iclass 37, count 0 2006.252.08:19:21.90#ibcon#first serial, iclass 37, count 0 2006.252.08:19:21.90#ibcon#enter sib2, iclass 37, count 0 2006.252.08:19:21.90#ibcon#flushed, iclass 37, count 0 2006.252.08:19:21.90#ibcon#about to write, iclass 37, count 0 2006.252.08:19:21.90#ibcon#wrote, iclass 37, count 0 2006.252.08:19:21.90#ibcon#about to read 3, iclass 37, count 0 2006.252.08:19:21.92#ibcon#read 3, iclass 37, count 0 2006.252.08:19:21.92#ibcon#about to read 4, iclass 37, count 0 2006.252.08:19:21.92#ibcon#read 4, iclass 37, count 0 2006.252.08:19:21.92#ibcon#about to read 5, iclass 37, count 0 2006.252.08:19:21.92#ibcon#read 5, iclass 37, count 0 2006.252.08:19:21.92#ibcon#about to read 6, iclass 37, count 0 2006.252.08:19:21.92#ibcon#read 6, iclass 37, count 0 2006.252.08:19:21.92#ibcon#end of sib2, iclass 37, count 0 2006.252.08:19:21.92#ibcon#*mode == 0, iclass 37, count 0 2006.252.08:19:21.92#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.252.08:19:21.92#ibcon#[28=FRQ=05,744.99\r\n] 2006.252.08:19:21.92#ibcon#*before write, iclass 37, count 0 2006.252.08:19:21.92#ibcon#enter sib2, iclass 37, count 0 2006.252.08:19:21.92#ibcon#flushed, iclass 37, count 0 2006.252.08:19:21.92#ibcon#about to write, iclass 37, count 0 2006.252.08:19:21.92#ibcon#wrote, iclass 37, count 0 2006.252.08:19:21.92#ibcon#about to read 3, iclass 37, count 0 2006.252.08:19:21.96#ibcon#read 3, iclass 37, count 0 2006.252.08:19:21.96#ibcon#about to read 4, iclass 37, count 0 2006.252.08:19:21.96#ibcon#read 4, iclass 37, count 0 2006.252.08:19:21.96#ibcon#about to read 5, iclass 37, count 0 2006.252.08:19:21.96#ibcon#read 5, iclass 37, count 0 2006.252.08:19:21.96#ibcon#about to read 6, iclass 37, count 0 2006.252.08:19:21.96#ibcon#read 6, iclass 37, count 0 2006.252.08:19:21.96#ibcon#end of sib2, iclass 37, count 0 2006.252.08:19:21.96#ibcon#*after write, iclass 37, count 0 2006.252.08:19:21.96#ibcon#*before return 0, iclass 37, count 0 2006.252.08:19:21.96#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.252.08:19:21.96#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.252.08:19:21.96#ibcon#about to clear, iclass 37 cls_cnt 0 2006.252.08:19:21.96#ibcon#cleared, iclass 37 cls_cnt 0 2006.252.08:19:21.96$vc4f8/vb=5,4 2006.252.08:19:21.96#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.252.08:19:21.96#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.252.08:19:21.96#ibcon#ireg 11 cls_cnt 2 2006.252.08:19:21.96#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.252.08:19:22.02#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.252.08:19:22.02#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.252.08:19:22.02#ibcon#enter wrdev, iclass 39, count 2 2006.252.08:19:22.02#ibcon#first serial, iclass 39, count 2 2006.252.08:19:22.02#ibcon#enter sib2, iclass 39, count 2 2006.252.08:19:22.02#ibcon#flushed, iclass 39, count 2 2006.252.08:19:22.02#ibcon#about to write, iclass 39, count 2 2006.252.08:19:22.02#ibcon#wrote, iclass 39, count 2 2006.252.08:19:22.02#ibcon#about to read 3, iclass 39, count 2 2006.252.08:19:22.04#ibcon#read 3, iclass 39, count 2 2006.252.08:19:22.04#ibcon#about to read 4, iclass 39, count 2 2006.252.08:19:22.04#ibcon#read 4, iclass 39, count 2 2006.252.08:19:22.04#ibcon#about to read 5, iclass 39, count 2 2006.252.08:19:22.04#ibcon#read 5, iclass 39, count 2 2006.252.08:19:22.04#ibcon#about to read 6, iclass 39, count 2 2006.252.08:19:22.04#ibcon#read 6, iclass 39, count 2 2006.252.08:19:22.04#ibcon#end of sib2, iclass 39, count 2 2006.252.08:19:22.04#ibcon#*mode == 0, iclass 39, count 2 2006.252.08:19:22.04#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.252.08:19:22.04#ibcon#[27=AT05-04\r\n] 2006.252.08:19:22.04#ibcon#*before write, iclass 39, count 2 2006.252.08:19:22.04#ibcon#enter sib2, iclass 39, count 2 2006.252.08:19:22.04#ibcon#flushed, iclass 39, count 2 2006.252.08:19:22.04#ibcon#about to write, iclass 39, count 2 2006.252.08:19:22.04#ibcon#wrote, iclass 39, count 2 2006.252.08:19:22.04#ibcon#about to read 3, iclass 39, count 2 2006.252.08:19:22.07#ibcon#read 3, iclass 39, count 2 2006.252.08:19:22.07#ibcon#about to read 4, iclass 39, count 2 2006.252.08:19:22.07#ibcon#read 4, iclass 39, count 2 2006.252.08:19:22.07#ibcon#about to read 5, iclass 39, count 2 2006.252.08:19:22.07#ibcon#read 5, iclass 39, count 2 2006.252.08:19:22.07#ibcon#about to read 6, iclass 39, count 2 2006.252.08:19:22.07#ibcon#read 6, iclass 39, count 2 2006.252.08:19:22.07#ibcon#end of sib2, iclass 39, count 2 2006.252.08:19:22.07#ibcon#*after write, iclass 39, count 2 2006.252.08:19:22.07#ibcon#*before return 0, iclass 39, count 2 2006.252.08:19:22.07#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.252.08:19:22.07#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.252.08:19:22.07#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.252.08:19:22.07#ibcon#ireg 7 cls_cnt 0 2006.252.08:19:22.07#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.252.08:19:22.19#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.252.08:19:22.19#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.252.08:19:22.19#ibcon#enter wrdev, iclass 39, count 0 2006.252.08:19:22.19#ibcon#first serial, iclass 39, count 0 2006.252.08:19:22.19#ibcon#enter sib2, iclass 39, count 0 2006.252.08:19:22.19#ibcon#flushed, iclass 39, count 0 2006.252.08:19:22.19#ibcon#about to write, iclass 39, count 0 2006.252.08:19:22.19#ibcon#wrote, iclass 39, count 0 2006.252.08:19:22.19#ibcon#about to read 3, iclass 39, count 0 2006.252.08:19:22.21#ibcon#read 3, iclass 39, count 0 2006.252.08:19:22.21#ibcon#about to read 4, iclass 39, count 0 2006.252.08:19:22.21#ibcon#read 4, iclass 39, count 0 2006.252.08:19:22.21#ibcon#about to read 5, iclass 39, count 0 2006.252.08:19:22.21#ibcon#read 5, iclass 39, count 0 2006.252.08:19:22.21#ibcon#about to read 6, iclass 39, count 0 2006.252.08:19:22.21#ibcon#read 6, iclass 39, count 0 2006.252.08:19:22.21#ibcon#end of sib2, iclass 39, count 0 2006.252.08:19:22.21#ibcon#*mode == 0, iclass 39, count 0 2006.252.08:19:22.21#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.252.08:19:22.21#ibcon#[27=USB\r\n] 2006.252.08:19:22.21#ibcon#*before write, iclass 39, count 0 2006.252.08:19:22.21#ibcon#enter sib2, iclass 39, count 0 2006.252.08:19:22.21#ibcon#flushed, iclass 39, count 0 2006.252.08:19:22.21#ibcon#about to write, iclass 39, count 0 2006.252.08:19:22.21#ibcon#wrote, iclass 39, count 0 2006.252.08:19:22.21#ibcon#about to read 3, iclass 39, count 0 2006.252.08:19:22.24#ibcon#read 3, iclass 39, count 0 2006.252.08:19:22.24#ibcon#about to read 4, iclass 39, count 0 2006.252.08:19:22.24#ibcon#read 4, iclass 39, count 0 2006.252.08:19:22.24#ibcon#about to read 5, iclass 39, count 0 2006.252.08:19:22.24#ibcon#read 5, iclass 39, count 0 2006.252.08:19:22.24#ibcon#about to read 6, iclass 39, count 0 2006.252.08:19:22.24#ibcon#read 6, iclass 39, count 0 2006.252.08:19:22.24#ibcon#end of sib2, iclass 39, count 0 2006.252.08:19:22.24#ibcon#*after write, iclass 39, count 0 2006.252.08:19:22.24#ibcon#*before return 0, iclass 39, count 0 2006.252.08:19:22.24#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.252.08:19:22.24#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.252.08:19:22.24#ibcon#about to clear, iclass 39 cls_cnt 0 2006.252.08:19:22.24#ibcon#cleared, iclass 39 cls_cnt 0 2006.252.08:19:22.24$vc4f8/vblo=6,752.99 2006.252.08:19:22.24#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.252.08:19:22.24#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.252.08:19:22.24#ibcon#ireg 17 cls_cnt 0 2006.252.08:19:22.24#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.252.08:19:22.24#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.252.08:19:22.24#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.252.08:19:22.24#ibcon#enter wrdev, iclass 3, count 0 2006.252.08:19:22.24#ibcon#first serial, iclass 3, count 0 2006.252.08:19:22.24#ibcon#enter sib2, iclass 3, count 0 2006.252.08:19:22.24#ibcon#flushed, iclass 3, count 0 2006.252.08:19:22.24#ibcon#about to write, iclass 3, count 0 2006.252.08:19:22.24#ibcon#wrote, iclass 3, count 0 2006.252.08:19:22.24#ibcon#about to read 3, iclass 3, count 0 2006.252.08:19:22.26#ibcon#read 3, iclass 3, count 0 2006.252.08:19:22.26#ibcon#about to read 4, iclass 3, count 0 2006.252.08:19:22.26#ibcon#read 4, iclass 3, count 0 2006.252.08:19:22.26#ibcon#about to read 5, iclass 3, count 0 2006.252.08:19:22.26#ibcon#read 5, iclass 3, count 0 2006.252.08:19:22.26#ibcon#about to read 6, iclass 3, count 0 2006.252.08:19:22.26#ibcon#read 6, iclass 3, count 0 2006.252.08:19:22.26#ibcon#end of sib2, iclass 3, count 0 2006.252.08:19:22.26#ibcon#*mode == 0, iclass 3, count 0 2006.252.08:19:22.26#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.252.08:19:22.26#ibcon#[28=FRQ=06,752.99\r\n] 2006.252.08:19:22.26#ibcon#*before write, iclass 3, count 0 2006.252.08:19:22.26#ibcon#enter sib2, iclass 3, count 0 2006.252.08:19:22.26#ibcon#flushed, iclass 3, count 0 2006.252.08:19:22.26#ibcon#about to write, iclass 3, count 0 2006.252.08:19:22.26#ibcon#wrote, iclass 3, count 0 2006.252.08:19:22.26#ibcon#about to read 3, iclass 3, count 0 2006.252.08:19:22.30#ibcon#read 3, iclass 3, count 0 2006.252.08:19:22.30#ibcon#about to read 4, iclass 3, count 0 2006.252.08:19:22.30#ibcon#read 4, iclass 3, count 0 2006.252.08:19:22.30#ibcon#about to read 5, iclass 3, count 0 2006.252.08:19:22.30#ibcon#read 5, iclass 3, count 0 2006.252.08:19:22.30#ibcon#about to read 6, iclass 3, count 0 2006.252.08:19:22.30#ibcon#read 6, iclass 3, count 0 2006.252.08:19:22.30#ibcon#end of sib2, iclass 3, count 0 2006.252.08:19:22.30#ibcon#*after write, iclass 3, count 0 2006.252.08:19:22.30#ibcon#*before return 0, iclass 3, count 0 2006.252.08:19:22.30#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.252.08:19:22.30#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.252.08:19:22.30#ibcon#about to clear, iclass 3 cls_cnt 0 2006.252.08:19:22.30#ibcon#cleared, iclass 3 cls_cnt 0 2006.252.08:19:22.30$vc4f8/vb=6,4 2006.252.08:19:22.30#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.252.08:19:22.30#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.252.08:19:22.30#ibcon#ireg 11 cls_cnt 2 2006.252.08:19:22.30#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.252.08:19:22.36#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.252.08:19:22.36#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.252.08:19:22.36#ibcon#enter wrdev, iclass 5, count 2 2006.252.08:19:22.36#ibcon#first serial, iclass 5, count 2 2006.252.08:19:22.36#ibcon#enter sib2, iclass 5, count 2 2006.252.08:19:22.36#ibcon#flushed, iclass 5, count 2 2006.252.08:19:22.36#ibcon#about to write, iclass 5, count 2 2006.252.08:19:22.36#ibcon#wrote, iclass 5, count 2 2006.252.08:19:22.36#ibcon#about to read 3, iclass 5, count 2 2006.252.08:19:22.38#ibcon#read 3, iclass 5, count 2 2006.252.08:19:22.38#ibcon#about to read 4, iclass 5, count 2 2006.252.08:19:22.38#ibcon#read 4, iclass 5, count 2 2006.252.08:19:22.38#ibcon#about to read 5, iclass 5, count 2 2006.252.08:19:22.38#ibcon#read 5, iclass 5, count 2 2006.252.08:19:22.38#ibcon#about to read 6, iclass 5, count 2 2006.252.08:19:22.38#ibcon#read 6, iclass 5, count 2 2006.252.08:19:22.38#ibcon#end of sib2, iclass 5, count 2 2006.252.08:19:22.38#ibcon#*mode == 0, iclass 5, count 2 2006.252.08:19:22.38#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.252.08:19:22.38#ibcon#[27=AT06-04\r\n] 2006.252.08:19:22.38#ibcon#*before write, iclass 5, count 2 2006.252.08:19:22.38#ibcon#enter sib2, iclass 5, count 2 2006.252.08:19:22.38#ibcon#flushed, iclass 5, count 2 2006.252.08:19:22.38#ibcon#about to write, iclass 5, count 2 2006.252.08:19:22.38#ibcon#wrote, iclass 5, count 2 2006.252.08:19:22.38#ibcon#about to read 3, iclass 5, count 2 2006.252.08:19:22.41#ibcon#read 3, iclass 5, count 2 2006.252.08:19:22.41#ibcon#about to read 4, iclass 5, count 2 2006.252.08:19:22.41#ibcon#read 4, iclass 5, count 2 2006.252.08:19:22.41#ibcon#about to read 5, iclass 5, count 2 2006.252.08:19:22.41#ibcon#read 5, iclass 5, count 2 2006.252.08:19:22.41#ibcon#about to read 6, iclass 5, count 2 2006.252.08:19:22.41#ibcon#read 6, iclass 5, count 2 2006.252.08:19:22.41#ibcon#end of sib2, iclass 5, count 2 2006.252.08:19:22.41#ibcon#*after write, iclass 5, count 2 2006.252.08:19:22.41#ibcon#*before return 0, iclass 5, count 2 2006.252.08:19:22.41#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.252.08:19:22.41#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.252.08:19:22.41#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.252.08:19:22.41#ibcon#ireg 7 cls_cnt 0 2006.252.08:19:22.41#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.252.08:19:22.53#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.252.08:19:22.53#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.252.08:19:22.53#ibcon#enter wrdev, iclass 5, count 0 2006.252.08:19:22.53#ibcon#first serial, iclass 5, count 0 2006.252.08:19:22.53#ibcon#enter sib2, iclass 5, count 0 2006.252.08:19:22.53#ibcon#flushed, iclass 5, count 0 2006.252.08:19:22.53#ibcon#about to write, iclass 5, count 0 2006.252.08:19:22.53#ibcon#wrote, iclass 5, count 0 2006.252.08:19:22.53#ibcon#about to read 3, iclass 5, count 0 2006.252.08:19:22.55#ibcon#read 3, iclass 5, count 0 2006.252.08:19:22.55#ibcon#about to read 4, iclass 5, count 0 2006.252.08:19:22.55#ibcon#read 4, iclass 5, count 0 2006.252.08:19:22.55#ibcon#about to read 5, iclass 5, count 0 2006.252.08:19:22.55#ibcon#read 5, iclass 5, count 0 2006.252.08:19:22.55#ibcon#about to read 6, iclass 5, count 0 2006.252.08:19:22.55#ibcon#read 6, iclass 5, count 0 2006.252.08:19:22.55#ibcon#end of sib2, iclass 5, count 0 2006.252.08:19:22.55#ibcon#*mode == 0, iclass 5, count 0 2006.252.08:19:22.55#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.252.08:19:22.55#ibcon#[27=USB\r\n] 2006.252.08:19:22.55#ibcon#*before write, iclass 5, count 0 2006.252.08:19:22.55#ibcon#enter sib2, iclass 5, count 0 2006.252.08:19:22.55#ibcon#flushed, iclass 5, count 0 2006.252.08:19:22.55#ibcon#about to write, iclass 5, count 0 2006.252.08:19:22.55#ibcon#wrote, iclass 5, count 0 2006.252.08:19:22.55#ibcon#about to read 3, iclass 5, count 0 2006.252.08:19:22.58#ibcon#read 3, iclass 5, count 0 2006.252.08:19:22.58#ibcon#about to read 4, iclass 5, count 0 2006.252.08:19:22.58#ibcon#read 4, iclass 5, count 0 2006.252.08:19:22.58#ibcon#about to read 5, iclass 5, count 0 2006.252.08:19:22.58#ibcon#read 5, iclass 5, count 0 2006.252.08:19:22.58#ibcon#about to read 6, iclass 5, count 0 2006.252.08:19:22.58#ibcon#read 6, iclass 5, count 0 2006.252.08:19:22.58#ibcon#end of sib2, iclass 5, count 0 2006.252.08:19:22.58#ibcon#*after write, iclass 5, count 0 2006.252.08:19:22.58#ibcon#*before return 0, iclass 5, count 0 2006.252.08:19:22.58#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.252.08:19:22.58#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.252.08:19:22.58#ibcon#about to clear, iclass 5 cls_cnt 0 2006.252.08:19:22.58#ibcon#cleared, iclass 5 cls_cnt 0 2006.252.08:19:22.58$vc4f8/vabw=wide 2006.252.08:19:22.58#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.252.08:19:22.58#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.252.08:19:22.58#ibcon#ireg 8 cls_cnt 0 2006.252.08:19:22.58#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.252.08:19:22.58#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.252.08:19:22.58#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.252.08:19:22.58#ibcon#enter wrdev, iclass 7, count 0 2006.252.08:19:22.58#ibcon#first serial, iclass 7, count 0 2006.252.08:19:22.58#ibcon#enter sib2, iclass 7, count 0 2006.252.08:19:22.58#ibcon#flushed, iclass 7, count 0 2006.252.08:19:22.58#ibcon#about to write, iclass 7, count 0 2006.252.08:19:22.58#ibcon#wrote, iclass 7, count 0 2006.252.08:19:22.58#ibcon#about to read 3, iclass 7, count 0 2006.252.08:19:22.60#ibcon#read 3, iclass 7, count 0 2006.252.08:19:22.60#ibcon#about to read 4, iclass 7, count 0 2006.252.08:19:22.60#ibcon#read 4, iclass 7, count 0 2006.252.08:19:22.60#ibcon#about to read 5, iclass 7, count 0 2006.252.08:19:22.60#ibcon#read 5, iclass 7, count 0 2006.252.08:19:22.60#ibcon#about to read 6, iclass 7, count 0 2006.252.08:19:22.60#ibcon#read 6, iclass 7, count 0 2006.252.08:19:22.60#ibcon#end of sib2, iclass 7, count 0 2006.252.08:19:22.60#ibcon#*mode == 0, iclass 7, count 0 2006.252.08:19:22.60#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.252.08:19:22.60#ibcon#[25=BW32\r\n] 2006.252.08:19:22.60#ibcon#*before write, iclass 7, count 0 2006.252.08:19:22.60#ibcon#enter sib2, iclass 7, count 0 2006.252.08:19:22.60#ibcon#flushed, iclass 7, count 0 2006.252.08:19:22.60#ibcon#about to write, iclass 7, count 0 2006.252.08:19:22.60#ibcon#wrote, iclass 7, count 0 2006.252.08:19:22.60#ibcon#about to read 3, iclass 7, count 0 2006.252.08:19:22.63#ibcon#read 3, iclass 7, count 0 2006.252.08:19:22.63#ibcon#about to read 4, iclass 7, count 0 2006.252.08:19:22.63#ibcon#read 4, iclass 7, count 0 2006.252.08:19:22.63#ibcon#about to read 5, iclass 7, count 0 2006.252.08:19:22.63#ibcon#read 5, iclass 7, count 0 2006.252.08:19:22.63#ibcon#about to read 6, iclass 7, count 0 2006.252.08:19:22.63#ibcon#read 6, iclass 7, count 0 2006.252.08:19:22.63#ibcon#end of sib2, iclass 7, count 0 2006.252.08:19:22.63#ibcon#*after write, iclass 7, count 0 2006.252.08:19:22.63#ibcon#*before return 0, iclass 7, count 0 2006.252.08:19:22.63#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.252.08:19:22.63#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.252.08:19:22.63#ibcon#about to clear, iclass 7 cls_cnt 0 2006.252.08:19:22.63#ibcon#cleared, iclass 7 cls_cnt 0 2006.252.08:19:22.63$vc4f8/vbbw=wide 2006.252.08:19:22.63#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.252.08:19:22.63#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.252.08:19:22.63#ibcon#ireg 8 cls_cnt 0 2006.252.08:19:22.63#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.252.08:19:22.70#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.252.08:19:22.70#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.252.08:19:22.70#ibcon#enter wrdev, iclass 11, count 0 2006.252.08:19:22.70#ibcon#first serial, iclass 11, count 0 2006.252.08:19:22.70#ibcon#enter sib2, iclass 11, count 0 2006.252.08:19:22.70#ibcon#flushed, iclass 11, count 0 2006.252.08:19:22.70#ibcon#about to write, iclass 11, count 0 2006.252.08:19:22.70#ibcon#wrote, iclass 11, count 0 2006.252.08:19:22.70#ibcon#about to read 3, iclass 11, count 0 2006.252.08:19:22.72#ibcon#read 3, iclass 11, count 0 2006.252.08:19:22.72#ibcon#about to read 4, iclass 11, count 0 2006.252.08:19:22.72#ibcon#read 4, iclass 11, count 0 2006.252.08:19:22.72#ibcon#about to read 5, iclass 11, count 0 2006.252.08:19:22.72#ibcon#read 5, iclass 11, count 0 2006.252.08:19:22.72#ibcon#about to read 6, iclass 11, count 0 2006.252.08:19:22.72#ibcon#read 6, iclass 11, count 0 2006.252.08:19:22.72#ibcon#end of sib2, iclass 11, count 0 2006.252.08:19:22.72#ibcon#*mode == 0, iclass 11, count 0 2006.252.08:19:22.72#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.252.08:19:22.72#ibcon#[27=BW32\r\n] 2006.252.08:19:22.72#ibcon#*before write, iclass 11, count 0 2006.252.08:19:22.72#ibcon#enter sib2, iclass 11, count 0 2006.252.08:19:22.72#ibcon#flushed, iclass 11, count 0 2006.252.08:19:22.72#ibcon#about to write, iclass 11, count 0 2006.252.08:19:22.72#ibcon#wrote, iclass 11, count 0 2006.252.08:19:22.72#ibcon#about to read 3, iclass 11, count 0 2006.252.08:19:22.75#ibcon#read 3, iclass 11, count 0 2006.252.08:19:22.75#ibcon#about to read 4, iclass 11, count 0 2006.252.08:19:22.75#ibcon#read 4, iclass 11, count 0 2006.252.08:19:22.75#ibcon#about to read 5, iclass 11, count 0 2006.252.08:19:22.75#ibcon#read 5, iclass 11, count 0 2006.252.08:19:22.75#ibcon#about to read 6, iclass 11, count 0 2006.252.08:19:22.75#ibcon#read 6, iclass 11, count 0 2006.252.08:19:22.75#ibcon#end of sib2, iclass 11, count 0 2006.252.08:19:22.75#ibcon#*after write, iclass 11, count 0 2006.252.08:19:22.75#ibcon#*before return 0, iclass 11, count 0 2006.252.08:19:22.75#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.252.08:19:22.75#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.252.08:19:22.75#ibcon#about to clear, iclass 11 cls_cnt 0 2006.252.08:19:22.75#ibcon#cleared, iclass 11 cls_cnt 0 2006.252.08:19:22.75$4f8m12a/ifd4f 2006.252.08:19:22.75$ifd4f/lo= 2006.252.08:19:22.75$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.252.08:19:22.75$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.252.08:19:22.75$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.252.08:19:22.75$ifd4f/patch= 2006.252.08:19:22.75$ifd4f/patch=lo1,a1,a2,a3,a4 2006.252.08:19:22.75$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.252.08:19:22.76$ifd4f/patch=lo3,a5,a6,a7,a8 2006.252.08:19:22.76$4f8m12a/"form=m,16.000,1:2 2006.252.08:19:22.76$4f8m12a/"tpicd 2006.252.08:19:22.76$4f8m12a/echo=off 2006.252.08:19:22.76$4f8m12a/xlog=off 2006.252.08:19:22.76:!2006.252.08:20:50 2006.252.08:19:43.13#trakl#Source acquired 2006.252.08:19:44.13#flagr#flagr/antenna,acquired 2006.252.08:20:50.01:preob 2006.252.08:20:51.14/onsource/TRACKING 2006.252.08:20:51.14:!2006.252.08:21:00 2006.252.08:21:00.00:data_valid=on 2006.252.08:21:00.00:midob 2006.252.08:21:00.14/onsource/TRACKING 2006.252.08:21:00.14/wx/27.25,1011.3,91 2006.252.08:21:00.31/cable/+6.4105E-03 2006.252.08:21:01.40/va/01,08,usb,yes,34,35 2006.252.08:21:01.40/va/02,07,usb,yes,34,35 2006.252.08:21:01.40/va/03,06,usb,yes,36,36 2006.252.08:21:01.40/va/04,07,usb,yes,34,37 2006.252.08:21:01.40/va/05,07,usb,yes,38,41 2006.252.08:21:01.40/va/06,07,usb,yes,34,33 2006.252.08:21:01.40/va/07,07,usb,yes,33,33 2006.252.08:21:01.40/va/08,07,usb,yes,36,35 2006.252.08:21:01.63/valo/01,532.99,yes,locked 2006.252.08:21:01.63/valo/02,572.99,yes,locked 2006.252.08:21:01.63/valo/03,672.99,yes,locked 2006.252.08:21:01.63/valo/04,832.99,yes,locked 2006.252.08:21:01.63/valo/05,652.99,yes,locked 2006.252.08:21:01.63/valo/06,772.99,yes,locked 2006.252.08:21:01.63/valo/07,832.99,yes,locked 2006.252.08:21:01.63/valo/08,852.99,yes,locked 2006.252.08:21:02.72/vb/01,04,usb,yes,31,30 2006.252.08:21:02.72/vb/02,05,usb,yes,29,30 2006.252.08:21:02.72/vb/03,04,usb,yes,29,33 2006.252.08:21:02.72/vb/04,04,usb,yes,30,30 2006.252.08:21:02.72/vb/05,04,usb,yes,28,32 2006.252.08:21:02.72/vb/06,04,usb,yes,29,32 2006.252.08:21:02.72/vb/07,04,usb,yes,32,31 2006.252.08:21:02.72/vb/08,04,usb,yes,29,32 2006.252.08:21:02.96/vblo/01,632.99,yes,locked 2006.252.08:21:02.96/vblo/02,640.99,yes,locked 2006.252.08:21:02.96/vblo/03,656.99,yes,locked 2006.252.08:21:02.96/vblo/04,712.99,yes,locked 2006.252.08:21:02.96/vblo/05,744.99,yes,locked 2006.252.08:21:02.96/vblo/06,752.99,yes,locked 2006.252.08:21:02.96/vblo/07,734.99,yes,locked 2006.252.08:21:02.96/vblo/08,744.99,yes,locked 2006.252.08:21:03.11/vabw/8 2006.252.08:21:03.26/vbbw/8 2006.252.08:21:03.35/xfe/off,on,14.0 2006.252.08:21:03.73/ifatt/23,28,28,28 2006.252.08:21:04.07/fmout-gps/S +4.74E-07 2006.252.08:21:04.11:!2006.252.08:22:00 2006.252.08:22:00.00:data_valid=off 2006.252.08:22:00.01:postob 2006.252.08:22:00.07/cable/+6.4103E-03 2006.252.08:22:00.08/wx/27.24,1011.3,91 2006.252.08:22:01.07/fmout-gps/S +4.75E-07 2006.252.08:22:01.08:scan_name=252-0824,k06252,60 2006.252.08:22:01.08:source=3c371,180650.68,694928.1,2000.0,cw 2006.252.08:22:01.14#flagr#flagr/antenna,new-source 2006.252.08:22:02.14:checkk5 2006.252.08:22:02.52/chk_autoobs//k5ts1/ autoobs is running! 2006.252.08:22:02.90/chk_autoobs//k5ts2/ autoobs is running! 2006.252.08:22:03.27/chk_autoobs//k5ts3/ autoobs is running! 2006.252.08:22:03.65/chk_autoobs//k5ts4/ autoobs is running! 2006.252.08:22:04.02/chk_obsdata//k5ts1/T2520821??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.08:22:04.39/chk_obsdata//k5ts2/T2520821??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.08:22:04.76/chk_obsdata//k5ts3/T2520821??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.08:22:05.14/chk_obsdata//k5ts4/T2520821??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.08:22:05.84/k5log//k5ts1_log_newline 2006.252.08:22:06.53/k5log//k5ts2_log_newline 2006.252.08:22:07.21/k5log//k5ts3_log_newline 2006.252.08:22:07.91/k5log//k5ts4_log_newline 2006.252.08:22:07.94/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.252.08:22:07.94:4f8m12a=3 2006.252.08:22:07.94$4f8m12a/echo=on 2006.252.08:22:07.94$4f8m12a/pcalon 2006.252.08:22:07.94$pcalon/"no phase cal control is implemented here 2006.252.08:22:07.94$4f8m12a/"tpicd=stop 2006.252.08:22:07.94$4f8m12a/vc4f8 2006.252.08:22:07.94$vc4f8/valo=1,532.99 2006.252.08:22:07.94#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.252.08:22:07.94#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.252.08:22:07.94#ibcon#ireg 17 cls_cnt 0 2006.252.08:22:07.94#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.252.08:22:07.94#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.252.08:22:07.94#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.252.08:22:07.94#ibcon#enter wrdev, iclass 4, count 0 2006.252.08:22:07.94#ibcon#first serial, iclass 4, count 0 2006.252.08:22:07.94#ibcon#enter sib2, iclass 4, count 0 2006.252.08:22:07.94#ibcon#flushed, iclass 4, count 0 2006.252.08:22:07.94#ibcon#about to write, iclass 4, count 0 2006.252.08:22:07.94#ibcon#wrote, iclass 4, count 0 2006.252.08:22:07.94#ibcon#about to read 3, iclass 4, count 0 2006.252.08:22:07.99#ibcon#read 3, iclass 4, count 0 2006.252.08:22:07.99#ibcon#about to read 4, iclass 4, count 0 2006.252.08:22:07.99#ibcon#read 4, iclass 4, count 0 2006.252.08:22:07.99#ibcon#about to read 5, iclass 4, count 0 2006.252.08:22:07.99#ibcon#read 5, iclass 4, count 0 2006.252.08:22:07.99#ibcon#about to read 6, iclass 4, count 0 2006.252.08:22:07.99#ibcon#read 6, iclass 4, count 0 2006.252.08:22:07.99#ibcon#end of sib2, iclass 4, count 0 2006.252.08:22:07.99#ibcon#*mode == 0, iclass 4, count 0 2006.252.08:22:07.99#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.252.08:22:07.99#ibcon#[26=FRQ=01,532.99\r\n] 2006.252.08:22:07.99#ibcon#*before write, iclass 4, count 0 2006.252.08:22:07.99#ibcon#enter sib2, iclass 4, count 0 2006.252.08:22:07.99#ibcon#flushed, iclass 4, count 0 2006.252.08:22:07.99#ibcon#about to write, iclass 4, count 0 2006.252.08:22:07.99#ibcon#wrote, iclass 4, count 0 2006.252.08:22:07.99#ibcon#about to read 3, iclass 4, count 0 2006.252.08:22:08.03#ibcon#read 3, iclass 4, count 0 2006.252.08:22:08.03#ibcon#about to read 4, iclass 4, count 0 2006.252.08:22:08.03#ibcon#read 4, iclass 4, count 0 2006.252.08:22:08.03#ibcon#about to read 5, iclass 4, count 0 2006.252.08:22:08.03#ibcon#read 5, iclass 4, count 0 2006.252.08:22:08.03#ibcon#about to read 6, iclass 4, count 0 2006.252.08:22:08.03#ibcon#read 6, iclass 4, count 0 2006.252.08:22:08.03#ibcon#end of sib2, iclass 4, count 0 2006.252.08:22:08.03#ibcon#*after write, iclass 4, count 0 2006.252.08:22:08.03#ibcon#*before return 0, iclass 4, count 0 2006.252.08:22:08.03#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.252.08:22:08.03#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.252.08:22:08.03#ibcon#about to clear, iclass 4 cls_cnt 0 2006.252.08:22:08.03#ibcon#cleared, iclass 4 cls_cnt 0 2006.252.08:22:08.03$vc4f8/va=1,8 2006.252.08:22:08.03#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.252.08:22:08.03#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.252.08:22:08.03#ibcon#ireg 11 cls_cnt 2 2006.252.08:22:08.03#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.252.08:22:08.03#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.252.08:22:08.03#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.252.08:22:08.03#ibcon#enter wrdev, iclass 6, count 2 2006.252.08:22:08.03#ibcon#first serial, iclass 6, count 2 2006.252.08:22:08.03#ibcon#enter sib2, iclass 6, count 2 2006.252.08:22:08.03#ibcon#flushed, iclass 6, count 2 2006.252.08:22:08.03#ibcon#about to write, iclass 6, count 2 2006.252.08:22:08.03#ibcon#wrote, iclass 6, count 2 2006.252.08:22:08.03#ibcon#about to read 3, iclass 6, count 2 2006.252.08:22:08.05#ibcon#read 3, iclass 6, count 2 2006.252.08:22:08.05#ibcon#about to read 4, iclass 6, count 2 2006.252.08:22:08.05#ibcon#read 4, iclass 6, count 2 2006.252.08:22:08.05#ibcon#about to read 5, iclass 6, count 2 2006.252.08:22:08.05#ibcon#read 5, iclass 6, count 2 2006.252.08:22:08.05#ibcon#about to read 6, iclass 6, count 2 2006.252.08:22:08.05#ibcon#read 6, iclass 6, count 2 2006.252.08:22:08.05#ibcon#end of sib2, iclass 6, count 2 2006.252.08:22:08.05#ibcon#*mode == 0, iclass 6, count 2 2006.252.08:22:08.05#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.252.08:22:08.05#ibcon#[25=AT01-08\r\n] 2006.252.08:22:08.05#ibcon#*before write, iclass 6, count 2 2006.252.08:22:08.05#ibcon#enter sib2, iclass 6, count 2 2006.252.08:22:08.05#ibcon#flushed, iclass 6, count 2 2006.252.08:22:08.05#ibcon#about to write, iclass 6, count 2 2006.252.08:22:08.05#ibcon#wrote, iclass 6, count 2 2006.252.08:22:08.05#ibcon#about to read 3, iclass 6, count 2 2006.252.08:22:08.08#ibcon#read 3, iclass 6, count 2 2006.252.08:22:08.08#ibcon#about to read 4, iclass 6, count 2 2006.252.08:22:08.08#ibcon#read 4, iclass 6, count 2 2006.252.08:22:08.08#ibcon#about to read 5, iclass 6, count 2 2006.252.08:22:08.08#ibcon#read 5, iclass 6, count 2 2006.252.08:22:08.08#ibcon#about to read 6, iclass 6, count 2 2006.252.08:22:08.08#ibcon#read 6, iclass 6, count 2 2006.252.08:22:08.08#ibcon#end of sib2, iclass 6, count 2 2006.252.08:22:08.08#ibcon#*after write, iclass 6, count 2 2006.252.08:22:08.08#ibcon#*before return 0, iclass 6, count 2 2006.252.08:22:08.08#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.252.08:22:08.08#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.252.08:22:08.08#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.252.08:22:08.08#ibcon#ireg 7 cls_cnt 0 2006.252.08:22:08.08#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.252.08:22:08.20#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.252.08:22:08.20#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.252.08:22:08.20#ibcon#enter wrdev, iclass 6, count 0 2006.252.08:22:08.20#ibcon#first serial, iclass 6, count 0 2006.252.08:22:08.20#ibcon#enter sib2, iclass 6, count 0 2006.252.08:22:08.20#ibcon#flushed, iclass 6, count 0 2006.252.08:22:08.20#ibcon#about to write, iclass 6, count 0 2006.252.08:22:08.20#ibcon#wrote, iclass 6, count 0 2006.252.08:22:08.20#ibcon#about to read 3, iclass 6, count 0 2006.252.08:22:08.22#ibcon#read 3, iclass 6, count 0 2006.252.08:22:08.22#ibcon#about to read 4, iclass 6, count 0 2006.252.08:22:08.22#ibcon#read 4, iclass 6, count 0 2006.252.08:22:08.22#ibcon#about to read 5, iclass 6, count 0 2006.252.08:22:08.22#ibcon#read 5, iclass 6, count 0 2006.252.08:22:08.22#ibcon#about to read 6, iclass 6, count 0 2006.252.08:22:08.22#ibcon#read 6, iclass 6, count 0 2006.252.08:22:08.22#ibcon#end of sib2, iclass 6, count 0 2006.252.08:22:08.22#ibcon#*mode == 0, iclass 6, count 0 2006.252.08:22:08.22#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.252.08:22:08.22#ibcon#[25=USB\r\n] 2006.252.08:22:08.22#ibcon#*before write, iclass 6, count 0 2006.252.08:22:08.22#ibcon#enter sib2, iclass 6, count 0 2006.252.08:22:08.22#ibcon#flushed, iclass 6, count 0 2006.252.08:22:08.22#ibcon#about to write, iclass 6, count 0 2006.252.08:22:08.22#ibcon#wrote, iclass 6, count 0 2006.252.08:22:08.22#ibcon#about to read 3, iclass 6, count 0 2006.252.08:22:08.25#ibcon#read 3, iclass 6, count 0 2006.252.08:22:08.25#ibcon#about to read 4, iclass 6, count 0 2006.252.08:22:08.25#ibcon#read 4, iclass 6, count 0 2006.252.08:22:08.25#ibcon#about to read 5, iclass 6, count 0 2006.252.08:22:08.25#ibcon#read 5, iclass 6, count 0 2006.252.08:22:08.25#ibcon#about to read 6, iclass 6, count 0 2006.252.08:22:08.25#ibcon#read 6, iclass 6, count 0 2006.252.08:22:08.25#ibcon#end of sib2, iclass 6, count 0 2006.252.08:22:08.25#ibcon#*after write, iclass 6, count 0 2006.252.08:22:08.25#ibcon#*before return 0, iclass 6, count 0 2006.252.08:22:08.25#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.252.08:22:08.25#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.252.08:22:08.25#ibcon#about to clear, iclass 6 cls_cnt 0 2006.252.08:22:08.25#ibcon#cleared, iclass 6 cls_cnt 0 2006.252.08:22:08.25$vc4f8/valo=2,572.99 2006.252.08:22:08.25#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.252.08:22:08.25#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.252.08:22:08.25#ibcon#ireg 17 cls_cnt 0 2006.252.08:22:08.25#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.252.08:22:08.25#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.252.08:22:08.25#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.252.08:22:08.25#ibcon#enter wrdev, iclass 10, count 0 2006.252.08:22:08.25#ibcon#first serial, iclass 10, count 0 2006.252.08:22:08.25#ibcon#enter sib2, iclass 10, count 0 2006.252.08:22:08.25#ibcon#flushed, iclass 10, count 0 2006.252.08:22:08.25#ibcon#about to write, iclass 10, count 0 2006.252.08:22:08.25#ibcon#wrote, iclass 10, count 0 2006.252.08:22:08.25#ibcon#about to read 3, iclass 10, count 0 2006.252.08:22:08.28#ibcon#read 3, iclass 10, count 0 2006.252.08:22:08.28#ibcon#about to read 4, iclass 10, count 0 2006.252.08:22:08.28#ibcon#read 4, iclass 10, count 0 2006.252.08:22:08.28#ibcon#about to read 5, iclass 10, count 0 2006.252.08:22:08.28#ibcon#read 5, iclass 10, count 0 2006.252.08:22:08.28#ibcon#about to read 6, iclass 10, count 0 2006.252.08:22:08.28#ibcon#read 6, iclass 10, count 0 2006.252.08:22:08.28#ibcon#end of sib2, iclass 10, count 0 2006.252.08:22:08.28#ibcon#*mode == 0, iclass 10, count 0 2006.252.08:22:08.28#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.252.08:22:08.28#ibcon#[26=FRQ=02,572.99\r\n] 2006.252.08:22:08.28#ibcon#*before write, iclass 10, count 0 2006.252.08:22:08.28#ibcon#enter sib2, iclass 10, count 0 2006.252.08:22:08.28#ibcon#flushed, iclass 10, count 0 2006.252.08:22:08.28#ibcon#about to write, iclass 10, count 0 2006.252.08:22:08.28#ibcon#wrote, iclass 10, count 0 2006.252.08:22:08.28#ibcon#about to read 3, iclass 10, count 0 2006.252.08:22:08.32#ibcon#read 3, iclass 10, count 0 2006.252.08:22:08.32#ibcon#about to read 4, iclass 10, count 0 2006.252.08:22:08.32#ibcon#read 4, iclass 10, count 0 2006.252.08:22:08.32#ibcon#about to read 5, iclass 10, count 0 2006.252.08:22:08.32#ibcon#read 5, iclass 10, count 0 2006.252.08:22:08.32#ibcon#about to read 6, iclass 10, count 0 2006.252.08:22:08.32#ibcon#read 6, iclass 10, count 0 2006.252.08:22:08.32#ibcon#end of sib2, iclass 10, count 0 2006.252.08:22:08.32#ibcon#*after write, iclass 10, count 0 2006.252.08:22:08.32#ibcon#*before return 0, iclass 10, count 0 2006.252.08:22:08.32#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.252.08:22:08.32#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.252.08:22:08.32#ibcon#about to clear, iclass 10 cls_cnt 0 2006.252.08:22:08.32#ibcon#cleared, iclass 10 cls_cnt 0 2006.252.08:22:08.32$vc4f8/va=2,7 2006.252.08:22:08.32#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.252.08:22:08.32#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.252.08:22:08.32#ibcon#ireg 11 cls_cnt 2 2006.252.08:22:08.32#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.252.08:22:08.37#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.252.08:22:08.37#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.252.08:22:08.37#ibcon#enter wrdev, iclass 12, count 2 2006.252.08:22:08.37#ibcon#first serial, iclass 12, count 2 2006.252.08:22:08.37#ibcon#enter sib2, iclass 12, count 2 2006.252.08:22:08.37#ibcon#flushed, iclass 12, count 2 2006.252.08:22:08.37#ibcon#about to write, iclass 12, count 2 2006.252.08:22:08.37#ibcon#wrote, iclass 12, count 2 2006.252.08:22:08.37#ibcon#about to read 3, iclass 12, count 2 2006.252.08:22:08.39#ibcon#read 3, iclass 12, count 2 2006.252.08:22:08.39#ibcon#about to read 4, iclass 12, count 2 2006.252.08:22:08.39#ibcon#read 4, iclass 12, count 2 2006.252.08:22:08.39#ibcon#about to read 5, iclass 12, count 2 2006.252.08:22:08.39#ibcon#read 5, iclass 12, count 2 2006.252.08:22:08.39#ibcon#about to read 6, iclass 12, count 2 2006.252.08:22:08.39#ibcon#read 6, iclass 12, count 2 2006.252.08:22:08.39#ibcon#end of sib2, iclass 12, count 2 2006.252.08:22:08.39#ibcon#*mode == 0, iclass 12, count 2 2006.252.08:22:08.39#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.252.08:22:08.39#ibcon#[25=AT02-07\r\n] 2006.252.08:22:08.39#ibcon#*before write, iclass 12, count 2 2006.252.08:22:08.39#ibcon#enter sib2, iclass 12, count 2 2006.252.08:22:08.39#ibcon#flushed, iclass 12, count 2 2006.252.08:22:08.39#ibcon#about to write, iclass 12, count 2 2006.252.08:22:08.39#ibcon#wrote, iclass 12, count 2 2006.252.08:22:08.39#ibcon#about to read 3, iclass 12, count 2 2006.252.08:22:08.42#ibcon#read 3, iclass 12, count 2 2006.252.08:22:08.42#ibcon#about to read 4, iclass 12, count 2 2006.252.08:22:08.42#ibcon#read 4, iclass 12, count 2 2006.252.08:22:08.42#ibcon#about to read 5, iclass 12, count 2 2006.252.08:22:08.42#ibcon#read 5, iclass 12, count 2 2006.252.08:22:08.42#ibcon#about to read 6, iclass 12, count 2 2006.252.08:22:08.42#ibcon#read 6, iclass 12, count 2 2006.252.08:22:08.42#ibcon#end of sib2, iclass 12, count 2 2006.252.08:22:08.42#ibcon#*after write, iclass 12, count 2 2006.252.08:22:08.42#ibcon#*before return 0, iclass 12, count 2 2006.252.08:22:08.42#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.252.08:22:08.42#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.252.08:22:08.42#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.252.08:22:08.42#ibcon#ireg 7 cls_cnt 0 2006.252.08:22:08.42#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.252.08:22:08.54#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.252.08:22:08.54#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.252.08:22:08.54#ibcon#enter wrdev, iclass 12, count 0 2006.252.08:22:08.54#ibcon#first serial, iclass 12, count 0 2006.252.08:22:08.54#ibcon#enter sib2, iclass 12, count 0 2006.252.08:22:08.54#ibcon#flushed, iclass 12, count 0 2006.252.08:22:08.54#ibcon#about to write, iclass 12, count 0 2006.252.08:22:08.54#ibcon#wrote, iclass 12, count 0 2006.252.08:22:08.54#ibcon#about to read 3, iclass 12, count 0 2006.252.08:22:08.56#ibcon#read 3, iclass 12, count 0 2006.252.08:22:08.56#ibcon#about to read 4, iclass 12, count 0 2006.252.08:22:08.56#ibcon#read 4, iclass 12, count 0 2006.252.08:22:08.56#ibcon#about to read 5, iclass 12, count 0 2006.252.08:22:08.56#ibcon#read 5, iclass 12, count 0 2006.252.08:22:08.56#ibcon#about to read 6, iclass 12, count 0 2006.252.08:22:08.56#ibcon#read 6, iclass 12, count 0 2006.252.08:22:08.56#ibcon#end of sib2, iclass 12, count 0 2006.252.08:22:08.56#ibcon#*mode == 0, iclass 12, count 0 2006.252.08:22:08.56#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.252.08:22:08.56#ibcon#[25=USB\r\n] 2006.252.08:22:08.56#ibcon#*before write, iclass 12, count 0 2006.252.08:22:08.56#ibcon#enter sib2, iclass 12, count 0 2006.252.08:22:08.56#ibcon#flushed, iclass 12, count 0 2006.252.08:22:08.56#ibcon#about to write, iclass 12, count 0 2006.252.08:22:08.56#ibcon#wrote, iclass 12, count 0 2006.252.08:22:08.56#ibcon#about to read 3, iclass 12, count 0 2006.252.08:22:08.59#ibcon#read 3, iclass 12, count 0 2006.252.08:22:08.59#ibcon#about to read 4, iclass 12, count 0 2006.252.08:22:08.59#ibcon#read 4, iclass 12, count 0 2006.252.08:22:08.59#ibcon#about to read 5, iclass 12, count 0 2006.252.08:22:08.59#ibcon#read 5, iclass 12, count 0 2006.252.08:22:08.59#ibcon#about to read 6, iclass 12, count 0 2006.252.08:22:08.59#ibcon#read 6, iclass 12, count 0 2006.252.08:22:08.59#ibcon#end of sib2, iclass 12, count 0 2006.252.08:22:08.59#ibcon#*after write, iclass 12, count 0 2006.252.08:22:08.59#ibcon#*before return 0, iclass 12, count 0 2006.252.08:22:08.59#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.252.08:22:08.59#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.252.08:22:08.59#ibcon#about to clear, iclass 12 cls_cnt 0 2006.252.08:22:08.59#ibcon#cleared, iclass 12 cls_cnt 0 2006.252.08:22:08.59$vc4f8/valo=3,672.99 2006.252.08:22:08.59#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.252.08:22:08.59#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.252.08:22:08.59#ibcon#ireg 17 cls_cnt 0 2006.252.08:22:08.59#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.252.08:22:08.59#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.252.08:22:08.59#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.252.08:22:08.59#ibcon#enter wrdev, iclass 14, count 0 2006.252.08:22:08.59#ibcon#first serial, iclass 14, count 0 2006.252.08:22:08.59#ibcon#enter sib2, iclass 14, count 0 2006.252.08:22:08.59#ibcon#flushed, iclass 14, count 0 2006.252.08:22:08.59#ibcon#about to write, iclass 14, count 0 2006.252.08:22:08.59#ibcon#wrote, iclass 14, count 0 2006.252.08:22:08.59#ibcon#about to read 3, iclass 14, count 0 2006.252.08:22:08.61#ibcon#read 3, iclass 14, count 0 2006.252.08:22:08.61#ibcon#about to read 4, iclass 14, count 0 2006.252.08:22:08.61#ibcon#read 4, iclass 14, count 0 2006.252.08:22:08.61#ibcon#about to read 5, iclass 14, count 0 2006.252.08:22:08.61#ibcon#read 5, iclass 14, count 0 2006.252.08:22:08.61#ibcon#about to read 6, iclass 14, count 0 2006.252.08:22:08.61#ibcon#read 6, iclass 14, count 0 2006.252.08:22:08.61#ibcon#end of sib2, iclass 14, count 0 2006.252.08:22:08.61#ibcon#*mode == 0, iclass 14, count 0 2006.252.08:22:08.61#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.252.08:22:08.61#ibcon#[26=FRQ=03,672.99\r\n] 2006.252.08:22:08.61#ibcon#*before write, iclass 14, count 0 2006.252.08:22:08.61#ibcon#enter sib2, iclass 14, count 0 2006.252.08:22:08.61#ibcon#flushed, iclass 14, count 0 2006.252.08:22:08.61#ibcon#about to write, iclass 14, count 0 2006.252.08:22:08.61#ibcon#wrote, iclass 14, count 0 2006.252.08:22:08.61#ibcon#about to read 3, iclass 14, count 0 2006.252.08:22:08.65#ibcon#read 3, iclass 14, count 0 2006.252.08:22:08.65#ibcon#about to read 4, iclass 14, count 0 2006.252.08:22:08.65#ibcon#read 4, iclass 14, count 0 2006.252.08:22:08.65#ibcon#about to read 5, iclass 14, count 0 2006.252.08:22:08.65#ibcon#read 5, iclass 14, count 0 2006.252.08:22:08.65#ibcon#about to read 6, iclass 14, count 0 2006.252.08:22:08.65#ibcon#read 6, iclass 14, count 0 2006.252.08:22:08.65#ibcon#end of sib2, iclass 14, count 0 2006.252.08:22:08.65#ibcon#*after write, iclass 14, count 0 2006.252.08:22:08.65#ibcon#*before return 0, iclass 14, count 0 2006.252.08:22:08.65#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.252.08:22:08.65#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.252.08:22:08.65#ibcon#about to clear, iclass 14 cls_cnt 0 2006.252.08:22:08.65#ibcon#cleared, iclass 14 cls_cnt 0 2006.252.08:22:08.65$vc4f8/va=3,6 2006.252.08:22:08.65#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.252.08:22:08.65#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.252.08:22:08.65#ibcon#ireg 11 cls_cnt 2 2006.252.08:22:08.65#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.252.08:22:08.72#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.252.08:22:08.72#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.252.08:22:08.72#ibcon#enter wrdev, iclass 16, count 2 2006.252.08:22:08.72#ibcon#first serial, iclass 16, count 2 2006.252.08:22:08.72#ibcon#enter sib2, iclass 16, count 2 2006.252.08:22:08.72#ibcon#flushed, iclass 16, count 2 2006.252.08:22:08.72#ibcon#about to write, iclass 16, count 2 2006.252.08:22:08.72#ibcon#wrote, iclass 16, count 2 2006.252.08:22:08.72#ibcon#about to read 3, iclass 16, count 2 2006.252.08:22:08.73#ibcon#read 3, iclass 16, count 2 2006.252.08:22:08.73#ibcon#about to read 4, iclass 16, count 2 2006.252.08:22:08.73#ibcon#read 4, iclass 16, count 2 2006.252.08:22:08.73#ibcon#about to read 5, iclass 16, count 2 2006.252.08:22:08.73#ibcon#read 5, iclass 16, count 2 2006.252.08:22:08.73#ibcon#about to read 6, iclass 16, count 2 2006.252.08:22:08.73#ibcon#read 6, iclass 16, count 2 2006.252.08:22:08.73#ibcon#end of sib2, iclass 16, count 2 2006.252.08:22:08.73#ibcon#*mode == 0, iclass 16, count 2 2006.252.08:22:08.73#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.252.08:22:08.73#ibcon#[25=AT03-06\r\n] 2006.252.08:22:08.73#ibcon#*before write, iclass 16, count 2 2006.252.08:22:08.73#ibcon#enter sib2, iclass 16, count 2 2006.252.08:22:08.73#ibcon#flushed, iclass 16, count 2 2006.252.08:22:08.73#ibcon#about to write, iclass 16, count 2 2006.252.08:22:08.73#ibcon#wrote, iclass 16, count 2 2006.252.08:22:08.73#ibcon#about to read 3, iclass 16, count 2 2006.252.08:22:08.76#ibcon#read 3, iclass 16, count 2 2006.252.08:22:08.76#ibcon#about to read 4, iclass 16, count 2 2006.252.08:22:08.76#ibcon#read 4, iclass 16, count 2 2006.252.08:22:08.76#ibcon#about to read 5, iclass 16, count 2 2006.252.08:22:08.76#ibcon#read 5, iclass 16, count 2 2006.252.08:22:08.76#ibcon#about to read 6, iclass 16, count 2 2006.252.08:22:08.76#ibcon#read 6, iclass 16, count 2 2006.252.08:22:08.76#ibcon#end of sib2, iclass 16, count 2 2006.252.08:22:08.76#ibcon#*after write, iclass 16, count 2 2006.252.08:22:08.76#ibcon#*before return 0, iclass 16, count 2 2006.252.08:22:08.76#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.252.08:22:08.76#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.252.08:22:08.76#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.252.08:22:08.76#ibcon#ireg 7 cls_cnt 0 2006.252.08:22:08.76#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.252.08:22:08.88#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.252.08:22:08.88#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.252.08:22:08.88#ibcon#enter wrdev, iclass 16, count 0 2006.252.08:22:08.88#ibcon#first serial, iclass 16, count 0 2006.252.08:22:08.88#ibcon#enter sib2, iclass 16, count 0 2006.252.08:22:08.88#ibcon#flushed, iclass 16, count 0 2006.252.08:22:08.88#ibcon#about to write, iclass 16, count 0 2006.252.08:22:08.88#ibcon#wrote, iclass 16, count 0 2006.252.08:22:08.88#ibcon#about to read 3, iclass 16, count 0 2006.252.08:22:08.89#abcon#<5=/04 3.1 6.3 27.24 911011.2\r\n> 2006.252.08:22:08.90#ibcon#read 3, iclass 16, count 0 2006.252.08:22:08.90#ibcon#about to read 4, iclass 16, count 0 2006.252.08:22:08.90#ibcon#read 4, iclass 16, count 0 2006.252.08:22:08.90#ibcon#about to read 5, iclass 16, count 0 2006.252.08:22:08.90#ibcon#read 5, iclass 16, count 0 2006.252.08:22:08.90#ibcon#about to read 6, iclass 16, count 0 2006.252.08:22:08.90#ibcon#read 6, iclass 16, count 0 2006.252.08:22:08.90#ibcon#end of sib2, iclass 16, count 0 2006.252.08:22:08.90#ibcon#*mode == 0, iclass 16, count 0 2006.252.08:22:08.90#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.252.08:22:08.90#ibcon#[25=USB\r\n] 2006.252.08:22:08.90#ibcon#*before write, iclass 16, count 0 2006.252.08:22:08.90#ibcon#enter sib2, iclass 16, count 0 2006.252.08:22:08.90#ibcon#flushed, iclass 16, count 0 2006.252.08:22:08.90#ibcon#about to write, iclass 16, count 0 2006.252.08:22:08.90#ibcon#wrote, iclass 16, count 0 2006.252.08:22:08.90#ibcon#about to read 3, iclass 16, count 0 2006.252.08:22:08.91#abcon#{5=INTERFACE CLEAR} 2006.252.08:22:08.93#ibcon#read 3, iclass 16, count 0 2006.252.08:22:08.93#ibcon#about to read 4, iclass 16, count 0 2006.252.08:22:08.93#ibcon#read 4, iclass 16, count 0 2006.252.08:22:08.93#ibcon#about to read 5, iclass 16, count 0 2006.252.08:22:08.93#ibcon#read 5, iclass 16, count 0 2006.252.08:22:08.93#ibcon#about to read 6, iclass 16, count 0 2006.252.08:22:08.93#ibcon#read 6, iclass 16, count 0 2006.252.08:22:08.93#ibcon#end of sib2, iclass 16, count 0 2006.252.08:22:08.93#ibcon#*after write, iclass 16, count 0 2006.252.08:22:08.93#ibcon#*before return 0, iclass 16, count 0 2006.252.08:22:08.93#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.252.08:22:08.93#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.252.08:22:08.93#ibcon#about to clear, iclass 16 cls_cnt 0 2006.252.08:22:08.93#ibcon#cleared, iclass 16 cls_cnt 0 2006.252.08:22:08.93$vc4f8/valo=4,832.99 2006.252.08:22:08.93#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.252.08:22:08.93#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.252.08:22:08.93#ibcon#ireg 17 cls_cnt 0 2006.252.08:22:08.93#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.252.08:22:08.93#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.252.08:22:08.93#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.252.08:22:08.93#ibcon#enter wrdev, iclass 21, count 0 2006.252.08:22:08.93#ibcon#first serial, iclass 21, count 0 2006.252.08:22:08.93#ibcon#enter sib2, iclass 21, count 0 2006.252.08:22:08.93#ibcon#flushed, iclass 21, count 0 2006.252.08:22:08.93#ibcon#about to write, iclass 21, count 0 2006.252.08:22:08.93#ibcon#wrote, iclass 21, count 0 2006.252.08:22:08.93#ibcon#about to read 3, iclass 21, count 0 2006.252.08:22:08.96#ibcon#read 3, iclass 21, count 0 2006.252.08:22:08.96#ibcon#about to read 4, iclass 21, count 0 2006.252.08:22:08.96#ibcon#read 4, iclass 21, count 0 2006.252.08:22:08.96#ibcon#about to read 5, iclass 21, count 0 2006.252.08:22:08.96#ibcon#read 5, iclass 21, count 0 2006.252.08:22:08.96#ibcon#about to read 6, iclass 21, count 0 2006.252.08:22:08.96#ibcon#read 6, iclass 21, count 0 2006.252.08:22:08.96#ibcon#end of sib2, iclass 21, count 0 2006.252.08:22:08.96#ibcon#*mode == 0, iclass 21, count 0 2006.252.08:22:08.96#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.252.08:22:08.96#ibcon#[26=FRQ=04,832.99\r\n] 2006.252.08:22:08.96#ibcon#*before write, iclass 21, count 0 2006.252.08:22:08.96#ibcon#enter sib2, iclass 21, count 0 2006.252.08:22:08.96#ibcon#flushed, iclass 21, count 0 2006.252.08:22:08.96#ibcon#about to write, iclass 21, count 0 2006.252.08:22:08.96#ibcon#wrote, iclass 21, count 0 2006.252.08:22:08.96#ibcon#about to read 3, iclass 21, count 0 2006.252.08:22:08.97#abcon#[5=S1D000X0/0*\r\n] 2006.252.08:22:09.00#ibcon#read 3, iclass 21, count 0 2006.252.08:22:09.00#ibcon#about to read 4, iclass 21, count 0 2006.252.08:22:09.00#ibcon#read 4, iclass 21, count 0 2006.252.08:22:09.00#ibcon#about to read 5, iclass 21, count 0 2006.252.08:22:09.00#ibcon#read 5, iclass 21, count 0 2006.252.08:22:09.00#ibcon#about to read 6, iclass 21, count 0 2006.252.08:22:09.00#ibcon#read 6, iclass 21, count 0 2006.252.08:22:09.00#ibcon#end of sib2, iclass 21, count 0 2006.252.08:22:09.00#ibcon#*after write, iclass 21, count 0 2006.252.08:22:09.00#ibcon#*before return 0, iclass 21, count 0 2006.252.08:22:09.00#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.252.08:22:09.00#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.252.08:22:09.00#ibcon#about to clear, iclass 21 cls_cnt 0 2006.252.08:22:09.00#ibcon#cleared, iclass 21 cls_cnt 0 2006.252.08:22:09.00$vc4f8/va=4,7 2006.252.08:22:09.00#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.252.08:22:09.00#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.252.08:22:09.00#ibcon#ireg 11 cls_cnt 2 2006.252.08:22:09.00#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.252.08:22:09.05#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.252.08:22:09.05#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.252.08:22:09.05#ibcon#enter wrdev, iclass 24, count 2 2006.252.08:22:09.05#ibcon#first serial, iclass 24, count 2 2006.252.08:22:09.05#ibcon#enter sib2, iclass 24, count 2 2006.252.08:22:09.05#ibcon#flushed, iclass 24, count 2 2006.252.08:22:09.05#ibcon#about to write, iclass 24, count 2 2006.252.08:22:09.05#ibcon#wrote, iclass 24, count 2 2006.252.08:22:09.05#ibcon#about to read 3, iclass 24, count 2 2006.252.08:22:09.07#ibcon#read 3, iclass 24, count 2 2006.252.08:22:09.07#ibcon#about to read 4, iclass 24, count 2 2006.252.08:22:09.07#ibcon#read 4, iclass 24, count 2 2006.252.08:22:09.07#ibcon#about to read 5, iclass 24, count 2 2006.252.08:22:09.07#ibcon#read 5, iclass 24, count 2 2006.252.08:22:09.07#ibcon#about to read 6, iclass 24, count 2 2006.252.08:22:09.07#ibcon#read 6, iclass 24, count 2 2006.252.08:22:09.07#ibcon#end of sib2, iclass 24, count 2 2006.252.08:22:09.07#ibcon#*mode == 0, iclass 24, count 2 2006.252.08:22:09.07#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.252.08:22:09.07#ibcon#[25=AT04-07\r\n] 2006.252.08:22:09.07#ibcon#*before write, iclass 24, count 2 2006.252.08:22:09.07#ibcon#enter sib2, iclass 24, count 2 2006.252.08:22:09.07#ibcon#flushed, iclass 24, count 2 2006.252.08:22:09.07#ibcon#about to write, iclass 24, count 2 2006.252.08:22:09.07#ibcon#wrote, iclass 24, count 2 2006.252.08:22:09.07#ibcon#about to read 3, iclass 24, count 2 2006.252.08:22:09.10#ibcon#read 3, iclass 24, count 2 2006.252.08:22:09.10#ibcon#about to read 4, iclass 24, count 2 2006.252.08:22:09.10#ibcon#read 4, iclass 24, count 2 2006.252.08:22:09.10#ibcon#about to read 5, iclass 24, count 2 2006.252.08:22:09.10#ibcon#read 5, iclass 24, count 2 2006.252.08:22:09.10#ibcon#about to read 6, iclass 24, count 2 2006.252.08:22:09.10#ibcon#read 6, iclass 24, count 2 2006.252.08:22:09.10#ibcon#end of sib2, iclass 24, count 2 2006.252.08:22:09.10#ibcon#*after write, iclass 24, count 2 2006.252.08:22:09.10#ibcon#*before return 0, iclass 24, count 2 2006.252.08:22:09.10#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.252.08:22:09.10#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.252.08:22:09.10#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.252.08:22:09.10#ibcon#ireg 7 cls_cnt 0 2006.252.08:22:09.10#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.252.08:22:09.22#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.252.08:22:09.22#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.252.08:22:09.22#ibcon#enter wrdev, iclass 24, count 0 2006.252.08:22:09.22#ibcon#first serial, iclass 24, count 0 2006.252.08:22:09.22#ibcon#enter sib2, iclass 24, count 0 2006.252.08:22:09.22#ibcon#flushed, iclass 24, count 0 2006.252.08:22:09.22#ibcon#about to write, iclass 24, count 0 2006.252.08:22:09.22#ibcon#wrote, iclass 24, count 0 2006.252.08:22:09.22#ibcon#about to read 3, iclass 24, count 0 2006.252.08:22:09.24#ibcon#read 3, iclass 24, count 0 2006.252.08:22:09.24#ibcon#about to read 4, iclass 24, count 0 2006.252.08:22:09.24#ibcon#read 4, iclass 24, count 0 2006.252.08:22:09.24#ibcon#about to read 5, iclass 24, count 0 2006.252.08:22:09.24#ibcon#read 5, iclass 24, count 0 2006.252.08:22:09.24#ibcon#about to read 6, iclass 24, count 0 2006.252.08:22:09.24#ibcon#read 6, iclass 24, count 0 2006.252.08:22:09.24#ibcon#end of sib2, iclass 24, count 0 2006.252.08:22:09.24#ibcon#*mode == 0, iclass 24, count 0 2006.252.08:22:09.24#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.252.08:22:09.24#ibcon#[25=USB\r\n] 2006.252.08:22:09.24#ibcon#*before write, iclass 24, count 0 2006.252.08:22:09.24#ibcon#enter sib2, iclass 24, count 0 2006.252.08:22:09.24#ibcon#flushed, iclass 24, count 0 2006.252.08:22:09.24#ibcon#about to write, iclass 24, count 0 2006.252.08:22:09.24#ibcon#wrote, iclass 24, count 0 2006.252.08:22:09.24#ibcon#about to read 3, iclass 24, count 0 2006.252.08:22:09.27#ibcon#read 3, iclass 24, count 0 2006.252.08:22:09.27#ibcon#about to read 4, iclass 24, count 0 2006.252.08:22:09.27#ibcon#read 4, iclass 24, count 0 2006.252.08:22:09.27#ibcon#about to read 5, iclass 24, count 0 2006.252.08:22:09.27#ibcon#read 5, iclass 24, count 0 2006.252.08:22:09.27#ibcon#about to read 6, iclass 24, count 0 2006.252.08:22:09.27#ibcon#read 6, iclass 24, count 0 2006.252.08:22:09.27#ibcon#end of sib2, iclass 24, count 0 2006.252.08:22:09.27#ibcon#*after write, iclass 24, count 0 2006.252.08:22:09.27#ibcon#*before return 0, iclass 24, count 0 2006.252.08:22:09.27#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.252.08:22:09.27#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.252.08:22:09.27#ibcon#about to clear, iclass 24 cls_cnt 0 2006.252.08:22:09.27#ibcon#cleared, iclass 24 cls_cnt 0 2006.252.08:22:09.27$vc4f8/valo=5,652.99 2006.252.08:22:09.27#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.252.08:22:09.27#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.252.08:22:09.27#ibcon#ireg 17 cls_cnt 0 2006.252.08:22:09.27#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.252.08:22:09.27#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.252.08:22:09.27#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.252.08:22:09.27#ibcon#enter wrdev, iclass 26, count 0 2006.252.08:22:09.27#ibcon#first serial, iclass 26, count 0 2006.252.08:22:09.27#ibcon#enter sib2, iclass 26, count 0 2006.252.08:22:09.27#ibcon#flushed, iclass 26, count 0 2006.252.08:22:09.27#ibcon#about to write, iclass 26, count 0 2006.252.08:22:09.27#ibcon#wrote, iclass 26, count 0 2006.252.08:22:09.27#ibcon#about to read 3, iclass 26, count 0 2006.252.08:22:09.29#ibcon#read 3, iclass 26, count 0 2006.252.08:22:09.29#ibcon#about to read 4, iclass 26, count 0 2006.252.08:22:09.29#ibcon#read 4, iclass 26, count 0 2006.252.08:22:09.29#ibcon#about to read 5, iclass 26, count 0 2006.252.08:22:09.29#ibcon#read 5, iclass 26, count 0 2006.252.08:22:09.29#ibcon#about to read 6, iclass 26, count 0 2006.252.08:22:09.29#ibcon#read 6, iclass 26, count 0 2006.252.08:22:09.29#ibcon#end of sib2, iclass 26, count 0 2006.252.08:22:09.29#ibcon#*mode == 0, iclass 26, count 0 2006.252.08:22:09.29#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.252.08:22:09.29#ibcon#[26=FRQ=05,652.99\r\n] 2006.252.08:22:09.29#ibcon#*before write, iclass 26, count 0 2006.252.08:22:09.29#ibcon#enter sib2, iclass 26, count 0 2006.252.08:22:09.29#ibcon#flushed, iclass 26, count 0 2006.252.08:22:09.29#ibcon#about to write, iclass 26, count 0 2006.252.08:22:09.29#ibcon#wrote, iclass 26, count 0 2006.252.08:22:09.29#ibcon#about to read 3, iclass 26, count 0 2006.252.08:22:09.33#ibcon#read 3, iclass 26, count 0 2006.252.08:22:09.33#ibcon#about to read 4, iclass 26, count 0 2006.252.08:22:09.33#ibcon#read 4, iclass 26, count 0 2006.252.08:22:09.33#ibcon#about to read 5, iclass 26, count 0 2006.252.08:22:09.33#ibcon#read 5, iclass 26, count 0 2006.252.08:22:09.33#ibcon#about to read 6, iclass 26, count 0 2006.252.08:22:09.33#ibcon#read 6, iclass 26, count 0 2006.252.08:22:09.33#ibcon#end of sib2, iclass 26, count 0 2006.252.08:22:09.33#ibcon#*after write, iclass 26, count 0 2006.252.08:22:09.33#ibcon#*before return 0, iclass 26, count 0 2006.252.08:22:09.33#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.252.08:22:09.33#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.252.08:22:09.33#ibcon#about to clear, iclass 26 cls_cnt 0 2006.252.08:22:09.33#ibcon#cleared, iclass 26 cls_cnt 0 2006.252.08:22:09.33$vc4f8/va=5,7 2006.252.08:22:09.33#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.252.08:22:09.33#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.252.08:22:09.33#ibcon#ireg 11 cls_cnt 2 2006.252.08:22:09.33#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.252.08:22:09.39#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.252.08:22:09.39#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.252.08:22:09.39#ibcon#enter wrdev, iclass 28, count 2 2006.252.08:22:09.39#ibcon#first serial, iclass 28, count 2 2006.252.08:22:09.39#ibcon#enter sib2, iclass 28, count 2 2006.252.08:22:09.39#ibcon#flushed, iclass 28, count 2 2006.252.08:22:09.39#ibcon#about to write, iclass 28, count 2 2006.252.08:22:09.39#ibcon#wrote, iclass 28, count 2 2006.252.08:22:09.39#ibcon#about to read 3, iclass 28, count 2 2006.252.08:22:09.41#ibcon#read 3, iclass 28, count 2 2006.252.08:22:09.41#ibcon#about to read 4, iclass 28, count 2 2006.252.08:22:09.41#ibcon#read 4, iclass 28, count 2 2006.252.08:22:09.41#ibcon#about to read 5, iclass 28, count 2 2006.252.08:22:09.41#ibcon#read 5, iclass 28, count 2 2006.252.08:22:09.41#ibcon#about to read 6, iclass 28, count 2 2006.252.08:22:09.41#ibcon#read 6, iclass 28, count 2 2006.252.08:22:09.41#ibcon#end of sib2, iclass 28, count 2 2006.252.08:22:09.41#ibcon#*mode == 0, iclass 28, count 2 2006.252.08:22:09.41#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.252.08:22:09.41#ibcon#[25=AT05-07\r\n] 2006.252.08:22:09.41#ibcon#*before write, iclass 28, count 2 2006.252.08:22:09.41#ibcon#enter sib2, iclass 28, count 2 2006.252.08:22:09.41#ibcon#flushed, iclass 28, count 2 2006.252.08:22:09.41#ibcon#about to write, iclass 28, count 2 2006.252.08:22:09.41#ibcon#wrote, iclass 28, count 2 2006.252.08:22:09.41#ibcon#about to read 3, iclass 28, count 2 2006.252.08:22:09.44#ibcon#read 3, iclass 28, count 2 2006.252.08:22:09.44#ibcon#about to read 4, iclass 28, count 2 2006.252.08:22:09.44#ibcon#read 4, iclass 28, count 2 2006.252.08:22:09.44#ibcon#about to read 5, iclass 28, count 2 2006.252.08:22:09.44#ibcon#read 5, iclass 28, count 2 2006.252.08:22:09.44#ibcon#about to read 6, iclass 28, count 2 2006.252.08:22:09.44#ibcon#read 6, iclass 28, count 2 2006.252.08:22:09.44#ibcon#end of sib2, iclass 28, count 2 2006.252.08:22:09.44#ibcon#*after write, iclass 28, count 2 2006.252.08:22:09.44#ibcon#*before return 0, iclass 28, count 2 2006.252.08:22:09.44#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.252.08:22:09.44#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.252.08:22:09.44#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.252.08:22:09.44#ibcon#ireg 7 cls_cnt 0 2006.252.08:22:09.44#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.252.08:22:09.56#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.252.08:22:09.56#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.252.08:22:09.56#ibcon#enter wrdev, iclass 28, count 0 2006.252.08:22:09.56#ibcon#first serial, iclass 28, count 0 2006.252.08:22:09.56#ibcon#enter sib2, iclass 28, count 0 2006.252.08:22:09.56#ibcon#flushed, iclass 28, count 0 2006.252.08:22:09.56#ibcon#about to write, iclass 28, count 0 2006.252.08:22:09.56#ibcon#wrote, iclass 28, count 0 2006.252.08:22:09.56#ibcon#about to read 3, iclass 28, count 0 2006.252.08:22:09.58#ibcon#read 3, iclass 28, count 0 2006.252.08:22:09.58#ibcon#about to read 4, iclass 28, count 0 2006.252.08:22:09.58#ibcon#read 4, iclass 28, count 0 2006.252.08:22:09.58#ibcon#about to read 5, iclass 28, count 0 2006.252.08:22:09.58#ibcon#read 5, iclass 28, count 0 2006.252.08:22:09.58#ibcon#about to read 6, iclass 28, count 0 2006.252.08:22:09.58#ibcon#read 6, iclass 28, count 0 2006.252.08:22:09.58#ibcon#end of sib2, iclass 28, count 0 2006.252.08:22:09.58#ibcon#*mode == 0, iclass 28, count 0 2006.252.08:22:09.58#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.252.08:22:09.58#ibcon#[25=USB\r\n] 2006.252.08:22:09.58#ibcon#*before write, iclass 28, count 0 2006.252.08:22:09.58#ibcon#enter sib2, iclass 28, count 0 2006.252.08:22:09.58#ibcon#flushed, iclass 28, count 0 2006.252.08:22:09.58#ibcon#about to write, iclass 28, count 0 2006.252.08:22:09.58#ibcon#wrote, iclass 28, count 0 2006.252.08:22:09.58#ibcon#about to read 3, iclass 28, count 0 2006.252.08:22:09.61#ibcon#read 3, iclass 28, count 0 2006.252.08:22:09.61#ibcon#about to read 4, iclass 28, count 0 2006.252.08:22:09.61#ibcon#read 4, iclass 28, count 0 2006.252.08:22:09.61#ibcon#about to read 5, iclass 28, count 0 2006.252.08:22:09.61#ibcon#read 5, iclass 28, count 0 2006.252.08:22:09.61#ibcon#about to read 6, iclass 28, count 0 2006.252.08:22:09.61#ibcon#read 6, iclass 28, count 0 2006.252.08:22:09.61#ibcon#end of sib2, iclass 28, count 0 2006.252.08:22:09.61#ibcon#*after write, iclass 28, count 0 2006.252.08:22:09.61#ibcon#*before return 0, iclass 28, count 0 2006.252.08:22:09.61#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.252.08:22:09.61#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.252.08:22:09.61#ibcon#about to clear, iclass 28 cls_cnt 0 2006.252.08:22:09.61#ibcon#cleared, iclass 28 cls_cnt 0 2006.252.08:22:09.61$vc4f8/valo=6,772.99 2006.252.08:22:09.61#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.252.08:22:09.61#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.252.08:22:09.61#ibcon#ireg 17 cls_cnt 0 2006.252.08:22:09.61#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.252.08:22:09.61#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.252.08:22:09.61#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.252.08:22:09.61#ibcon#enter wrdev, iclass 30, count 0 2006.252.08:22:09.61#ibcon#first serial, iclass 30, count 0 2006.252.08:22:09.61#ibcon#enter sib2, iclass 30, count 0 2006.252.08:22:09.61#ibcon#flushed, iclass 30, count 0 2006.252.08:22:09.61#ibcon#about to write, iclass 30, count 0 2006.252.08:22:09.61#ibcon#wrote, iclass 30, count 0 2006.252.08:22:09.61#ibcon#about to read 3, iclass 30, count 0 2006.252.08:22:09.63#ibcon#read 3, iclass 30, count 0 2006.252.08:22:09.63#ibcon#about to read 4, iclass 30, count 0 2006.252.08:22:09.63#ibcon#read 4, iclass 30, count 0 2006.252.08:22:09.63#ibcon#about to read 5, iclass 30, count 0 2006.252.08:22:09.63#ibcon#read 5, iclass 30, count 0 2006.252.08:22:09.63#ibcon#about to read 6, iclass 30, count 0 2006.252.08:22:09.63#ibcon#read 6, iclass 30, count 0 2006.252.08:22:09.63#ibcon#end of sib2, iclass 30, count 0 2006.252.08:22:09.63#ibcon#*mode == 0, iclass 30, count 0 2006.252.08:22:09.63#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.252.08:22:09.63#ibcon#[26=FRQ=06,772.99\r\n] 2006.252.08:22:09.63#ibcon#*before write, iclass 30, count 0 2006.252.08:22:09.63#ibcon#enter sib2, iclass 30, count 0 2006.252.08:22:09.63#ibcon#flushed, iclass 30, count 0 2006.252.08:22:09.63#ibcon#about to write, iclass 30, count 0 2006.252.08:22:09.63#ibcon#wrote, iclass 30, count 0 2006.252.08:22:09.63#ibcon#about to read 3, iclass 30, count 0 2006.252.08:22:09.67#ibcon#read 3, iclass 30, count 0 2006.252.08:22:09.67#ibcon#about to read 4, iclass 30, count 0 2006.252.08:22:09.67#ibcon#read 4, iclass 30, count 0 2006.252.08:22:09.67#ibcon#about to read 5, iclass 30, count 0 2006.252.08:22:09.67#ibcon#read 5, iclass 30, count 0 2006.252.08:22:09.67#ibcon#about to read 6, iclass 30, count 0 2006.252.08:22:09.67#ibcon#read 6, iclass 30, count 0 2006.252.08:22:09.67#ibcon#end of sib2, iclass 30, count 0 2006.252.08:22:09.67#ibcon#*after write, iclass 30, count 0 2006.252.08:22:09.67#ibcon#*before return 0, iclass 30, count 0 2006.252.08:22:09.67#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.252.08:22:09.67#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.252.08:22:09.67#ibcon#about to clear, iclass 30 cls_cnt 0 2006.252.08:22:09.67#ibcon#cleared, iclass 30 cls_cnt 0 2006.252.08:22:09.67$vc4f8/va=6,7 2006.252.08:22:09.67#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.252.08:22:09.67#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.252.08:22:09.67#ibcon#ireg 11 cls_cnt 2 2006.252.08:22:09.67#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.252.08:22:09.74#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.252.08:22:09.74#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.252.08:22:09.74#ibcon#enter wrdev, iclass 32, count 2 2006.252.08:22:09.74#ibcon#first serial, iclass 32, count 2 2006.252.08:22:09.74#ibcon#enter sib2, iclass 32, count 2 2006.252.08:22:09.74#ibcon#flushed, iclass 32, count 2 2006.252.08:22:09.74#ibcon#about to write, iclass 32, count 2 2006.252.08:22:09.74#ibcon#wrote, iclass 32, count 2 2006.252.08:22:09.74#ibcon#about to read 3, iclass 32, count 2 2006.252.08:22:09.75#ibcon#read 3, iclass 32, count 2 2006.252.08:22:09.75#ibcon#about to read 4, iclass 32, count 2 2006.252.08:22:09.75#ibcon#read 4, iclass 32, count 2 2006.252.08:22:09.75#ibcon#about to read 5, iclass 32, count 2 2006.252.08:22:09.75#ibcon#read 5, iclass 32, count 2 2006.252.08:22:09.75#ibcon#about to read 6, iclass 32, count 2 2006.252.08:22:09.75#ibcon#read 6, iclass 32, count 2 2006.252.08:22:09.75#ibcon#end of sib2, iclass 32, count 2 2006.252.08:22:09.75#ibcon#*mode == 0, iclass 32, count 2 2006.252.08:22:09.75#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.252.08:22:09.75#ibcon#[25=AT06-07\r\n] 2006.252.08:22:09.75#ibcon#*before write, iclass 32, count 2 2006.252.08:22:09.75#ibcon#enter sib2, iclass 32, count 2 2006.252.08:22:09.75#ibcon#flushed, iclass 32, count 2 2006.252.08:22:09.75#ibcon#about to write, iclass 32, count 2 2006.252.08:22:09.75#ibcon#wrote, iclass 32, count 2 2006.252.08:22:09.75#ibcon#about to read 3, iclass 32, count 2 2006.252.08:22:09.78#ibcon#read 3, iclass 32, count 2 2006.252.08:22:09.78#ibcon#about to read 4, iclass 32, count 2 2006.252.08:22:09.78#ibcon#read 4, iclass 32, count 2 2006.252.08:22:09.78#ibcon#about to read 5, iclass 32, count 2 2006.252.08:22:09.78#ibcon#read 5, iclass 32, count 2 2006.252.08:22:09.78#ibcon#about to read 6, iclass 32, count 2 2006.252.08:22:09.78#ibcon#read 6, iclass 32, count 2 2006.252.08:22:09.78#ibcon#end of sib2, iclass 32, count 2 2006.252.08:22:09.78#ibcon#*after write, iclass 32, count 2 2006.252.08:22:09.78#ibcon#*before return 0, iclass 32, count 2 2006.252.08:22:09.78#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.252.08:22:09.78#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.252.08:22:09.78#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.252.08:22:09.78#ibcon#ireg 7 cls_cnt 0 2006.252.08:22:09.78#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.252.08:22:09.90#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.252.08:22:09.90#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.252.08:22:09.90#ibcon#enter wrdev, iclass 32, count 0 2006.252.08:22:09.90#ibcon#first serial, iclass 32, count 0 2006.252.08:22:09.90#ibcon#enter sib2, iclass 32, count 0 2006.252.08:22:09.90#ibcon#flushed, iclass 32, count 0 2006.252.08:22:09.90#ibcon#about to write, iclass 32, count 0 2006.252.08:22:09.90#ibcon#wrote, iclass 32, count 0 2006.252.08:22:09.90#ibcon#about to read 3, iclass 32, count 0 2006.252.08:22:09.92#ibcon#read 3, iclass 32, count 0 2006.252.08:22:09.92#ibcon#about to read 4, iclass 32, count 0 2006.252.08:22:09.92#ibcon#read 4, iclass 32, count 0 2006.252.08:22:09.92#ibcon#about to read 5, iclass 32, count 0 2006.252.08:22:09.92#ibcon#read 5, iclass 32, count 0 2006.252.08:22:09.92#ibcon#about to read 6, iclass 32, count 0 2006.252.08:22:09.92#ibcon#read 6, iclass 32, count 0 2006.252.08:22:09.92#ibcon#end of sib2, iclass 32, count 0 2006.252.08:22:09.92#ibcon#*mode == 0, iclass 32, count 0 2006.252.08:22:09.92#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.252.08:22:09.92#ibcon#[25=USB\r\n] 2006.252.08:22:09.92#ibcon#*before write, iclass 32, count 0 2006.252.08:22:09.92#ibcon#enter sib2, iclass 32, count 0 2006.252.08:22:09.92#ibcon#flushed, iclass 32, count 0 2006.252.08:22:09.92#ibcon#about to write, iclass 32, count 0 2006.252.08:22:09.92#ibcon#wrote, iclass 32, count 0 2006.252.08:22:09.92#ibcon#about to read 3, iclass 32, count 0 2006.252.08:22:09.95#ibcon#read 3, iclass 32, count 0 2006.252.08:22:09.95#ibcon#about to read 4, iclass 32, count 0 2006.252.08:22:09.95#ibcon#read 4, iclass 32, count 0 2006.252.08:22:09.95#ibcon#about to read 5, iclass 32, count 0 2006.252.08:22:09.95#ibcon#read 5, iclass 32, count 0 2006.252.08:22:09.95#ibcon#about to read 6, iclass 32, count 0 2006.252.08:22:09.95#ibcon#read 6, iclass 32, count 0 2006.252.08:22:09.95#ibcon#end of sib2, iclass 32, count 0 2006.252.08:22:09.95#ibcon#*after write, iclass 32, count 0 2006.252.08:22:09.95#ibcon#*before return 0, iclass 32, count 0 2006.252.08:22:09.95#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.252.08:22:09.95#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.252.08:22:09.95#ibcon#about to clear, iclass 32 cls_cnt 0 2006.252.08:22:09.95#ibcon#cleared, iclass 32 cls_cnt 0 2006.252.08:22:09.95$vc4f8/valo=7,832.99 2006.252.08:22:09.95#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.252.08:22:09.95#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.252.08:22:09.95#ibcon#ireg 17 cls_cnt 0 2006.252.08:22:09.95#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.252.08:22:09.95#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.252.08:22:09.95#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.252.08:22:09.95#ibcon#enter wrdev, iclass 34, count 0 2006.252.08:22:09.95#ibcon#first serial, iclass 34, count 0 2006.252.08:22:09.95#ibcon#enter sib2, iclass 34, count 0 2006.252.08:22:09.95#ibcon#flushed, iclass 34, count 0 2006.252.08:22:09.95#ibcon#about to write, iclass 34, count 0 2006.252.08:22:09.95#ibcon#wrote, iclass 34, count 0 2006.252.08:22:09.95#ibcon#about to read 3, iclass 34, count 0 2006.252.08:22:09.97#ibcon#read 3, iclass 34, count 0 2006.252.08:22:09.97#ibcon#about to read 4, iclass 34, count 0 2006.252.08:22:09.97#ibcon#read 4, iclass 34, count 0 2006.252.08:22:09.97#ibcon#about to read 5, iclass 34, count 0 2006.252.08:22:09.97#ibcon#read 5, iclass 34, count 0 2006.252.08:22:09.97#ibcon#about to read 6, iclass 34, count 0 2006.252.08:22:09.97#ibcon#read 6, iclass 34, count 0 2006.252.08:22:09.97#ibcon#end of sib2, iclass 34, count 0 2006.252.08:22:09.97#ibcon#*mode == 0, iclass 34, count 0 2006.252.08:22:09.97#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.252.08:22:09.97#ibcon#[26=FRQ=07,832.99\r\n] 2006.252.08:22:09.97#ibcon#*before write, iclass 34, count 0 2006.252.08:22:09.97#ibcon#enter sib2, iclass 34, count 0 2006.252.08:22:09.97#ibcon#flushed, iclass 34, count 0 2006.252.08:22:09.97#ibcon#about to write, iclass 34, count 0 2006.252.08:22:09.97#ibcon#wrote, iclass 34, count 0 2006.252.08:22:09.97#ibcon#about to read 3, iclass 34, count 0 2006.252.08:22:10.01#ibcon#read 3, iclass 34, count 0 2006.252.08:22:10.01#ibcon#about to read 4, iclass 34, count 0 2006.252.08:22:10.01#ibcon#read 4, iclass 34, count 0 2006.252.08:22:10.01#ibcon#about to read 5, iclass 34, count 0 2006.252.08:22:10.01#ibcon#read 5, iclass 34, count 0 2006.252.08:22:10.01#ibcon#about to read 6, iclass 34, count 0 2006.252.08:22:10.01#ibcon#read 6, iclass 34, count 0 2006.252.08:22:10.01#ibcon#end of sib2, iclass 34, count 0 2006.252.08:22:10.01#ibcon#*after write, iclass 34, count 0 2006.252.08:22:10.01#ibcon#*before return 0, iclass 34, count 0 2006.252.08:22:10.01#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.252.08:22:10.01#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.252.08:22:10.01#ibcon#about to clear, iclass 34 cls_cnt 0 2006.252.08:22:10.01#ibcon#cleared, iclass 34 cls_cnt 0 2006.252.08:22:10.01$vc4f8/va=7,7 2006.252.08:22:10.01#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.252.08:22:10.01#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.252.08:22:10.01#ibcon#ireg 11 cls_cnt 2 2006.252.08:22:10.01#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.252.08:22:10.07#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.252.08:22:10.07#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.252.08:22:10.07#ibcon#enter wrdev, iclass 36, count 2 2006.252.08:22:10.07#ibcon#first serial, iclass 36, count 2 2006.252.08:22:10.07#ibcon#enter sib2, iclass 36, count 2 2006.252.08:22:10.07#ibcon#flushed, iclass 36, count 2 2006.252.08:22:10.07#ibcon#about to write, iclass 36, count 2 2006.252.08:22:10.07#ibcon#wrote, iclass 36, count 2 2006.252.08:22:10.07#ibcon#about to read 3, iclass 36, count 2 2006.252.08:22:10.09#ibcon#read 3, iclass 36, count 2 2006.252.08:22:10.09#ibcon#about to read 4, iclass 36, count 2 2006.252.08:22:10.09#ibcon#read 4, iclass 36, count 2 2006.252.08:22:10.09#ibcon#about to read 5, iclass 36, count 2 2006.252.08:22:10.09#ibcon#read 5, iclass 36, count 2 2006.252.08:22:10.09#ibcon#about to read 6, iclass 36, count 2 2006.252.08:22:10.09#ibcon#read 6, iclass 36, count 2 2006.252.08:22:10.09#ibcon#end of sib2, iclass 36, count 2 2006.252.08:22:10.09#ibcon#*mode == 0, iclass 36, count 2 2006.252.08:22:10.09#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.252.08:22:10.09#ibcon#[25=AT07-07\r\n] 2006.252.08:22:10.09#ibcon#*before write, iclass 36, count 2 2006.252.08:22:10.09#ibcon#enter sib2, iclass 36, count 2 2006.252.08:22:10.09#ibcon#flushed, iclass 36, count 2 2006.252.08:22:10.09#ibcon#about to write, iclass 36, count 2 2006.252.08:22:10.09#ibcon#wrote, iclass 36, count 2 2006.252.08:22:10.09#ibcon#about to read 3, iclass 36, count 2 2006.252.08:22:10.12#ibcon#read 3, iclass 36, count 2 2006.252.08:22:10.12#ibcon#about to read 4, iclass 36, count 2 2006.252.08:22:10.12#ibcon#read 4, iclass 36, count 2 2006.252.08:22:10.12#ibcon#about to read 5, iclass 36, count 2 2006.252.08:22:10.12#ibcon#read 5, iclass 36, count 2 2006.252.08:22:10.12#ibcon#about to read 6, iclass 36, count 2 2006.252.08:22:10.12#ibcon#read 6, iclass 36, count 2 2006.252.08:22:10.12#ibcon#end of sib2, iclass 36, count 2 2006.252.08:22:10.12#ibcon#*after write, iclass 36, count 2 2006.252.08:22:10.12#ibcon#*before return 0, iclass 36, count 2 2006.252.08:22:10.12#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.252.08:22:10.12#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.252.08:22:10.12#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.252.08:22:10.12#ibcon#ireg 7 cls_cnt 0 2006.252.08:22:10.12#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.252.08:22:10.24#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.252.08:22:10.24#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.252.08:22:10.24#ibcon#enter wrdev, iclass 36, count 0 2006.252.08:22:10.24#ibcon#first serial, iclass 36, count 0 2006.252.08:22:10.24#ibcon#enter sib2, iclass 36, count 0 2006.252.08:22:10.24#ibcon#flushed, iclass 36, count 0 2006.252.08:22:10.24#ibcon#about to write, iclass 36, count 0 2006.252.08:22:10.24#ibcon#wrote, iclass 36, count 0 2006.252.08:22:10.24#ibcon#about to read 3, iclass 36, count 0 2006.252.08:22:10.26#ibcon#read 3, iclass 36, count 0 2006.252.08:22:10.26#ibcon#about to read 4, iclass 36, count 0 2006.252.08:22:10.26#ibcon#read 4, iclass 36, count 0 2006.252.08:22:10.26#ibcon#about to read 5, iclass 36, count 0 2006.252.08:22:10.26#ibcon#read 5, iclass 36, count 0 2006.252.08:22:10.26#ibcon#about to read 6, iclass 36, count 0 2006.252.08:22:10.26#ibcon#read 6, iclass 36, count 0 2006.252.08:22:10.26#ibcon#end of sib2, iclass 36, count 0 2006.252.08:22:10.26#ibcon#*mode == 0, iclass 36, count 0 2006.252.08:22:10.26#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.252.08:22:10.26#ibcon#[25=USB\r\n] 2006.252.08:22:10.26#ibcon#*before write, iclass 36, count 0 2006.252.08:22:10.26#ibcon#enter sib2, iclass 36, count 0 2006.252.08:22:10.26#ibcon#flushed, iclass 36, count 0 2006.252.08:22:10.26#ibcon#about to write, iclass 36, count 0 2006.252.08:22:10.26#ibcon#wrote, iclass 36, count 0 2006.252.08:22:10.26#ibcon#about to read 3, iclass 36, count 0 2006.252.08:22:10.29#ibcon#read 3, iclass 36, count 0 2006.252.08:22:10.29#ibcon#about to read 4, iclass 36, count 0 2006.252.08:22:10.29#ibcon#read 4, iclass 36, count 0 2006.252.08:22:10.29#ibcon#about to read 5, iclass 36, count 0 2006.252.08:22:10.29#ibcon#read 5, iclass 36, count 0 2006.252.08:22:10.29#ibcon#about to read 6, iclass 36, count 0 2006.252.08:22:10.29#ibcon#read 6, iclass 36, count 0 2006.252.08:22:10.29#ibcon#end of sib2, iclass 36, count 0 2006.252.08:22:10.29#ibcon#*after write, iclass 36, count 0 2006.252.08:22:10.29#ibcon#*before return 0, iclass 36, count 0 2006.252.08:22:10.29#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.252.08:22:10.29#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.252.08:22:10.29#ibcon#about to clear, iclass 36 cls_cnt 0 2006.252.08:22:10.29#ibcon#cleared, iclass 36 cls_cnt 0 2006.252.08:22:10.29$vc4f8/valo=8,852.99 2006.252.08:22:10.29#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.252.08:22:10.29#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.252.08:22:10.29#ibcon#ireg 17 cls_cnt 0 2006.252.08:22:10.29#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.252.08:22:10.29#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.252.08:22:10.29#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.252.08:22:10.29#ibcon#enter wrdev, iclass 38, count 0 2006.252.08:22:10.29#ibcon#first serial, iclass 38, count 0 2006.252.08:22:10.29#ibcon#enter sib2, iclass 38, count 0 2006.252.08:22:10.29#ibcon#flushed, iclass 38, count 0 2006.252.08:22:10.29#ibcon#about to write, iclass 38, count 0 2006.252.08:22:10.29#ibcon#wrote, iclass 38, count 0 2006.252.08:22:10.29#ibcon#about to read 3, iclass 38, count 0 2006.252.08:22:10.31#ibcon#read 3, iclass 38, count 0 2006.252.08:22:10.31#ibcon#about to read 4, iclass 38, count 0 2006.252.08:22:10.31#ibcon#read 4, iclass 38, count 0 2006.252.08:22:10.31#ibcon#about to read 5, iclass 38, count 0 2006.252.08:22:10.31#ibcon#read 5, iclass 38, count 0 2006.252.08:22:10.31#ibcon#about to read 6, iclass 38, count 0 2006.252.08:22:10.31#ibcon#read 6, iclass 38, count 0 2006.252.08:22:10.31#ibcon#end of sib2, iclass 38, count 0 2006.252.08:22:10.31#ibcon#*mode == 0, iclass 38, count 0 2006.252.08:22:10.31#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.252.08:22:10.31#ibcon#[26=FRQ=08,852.99\r\n] 2006.252.08:22:10.31#ibcon#*before write, iclass 38, count 0 2006.252.08:22:10.31#ibcon#enter sib2, iclass 38, count 0 2006.252.08:22:10.31#ibcon#flushed, iclass 38, count 0 2006.252.08:22:10.31#ibcon#about to write, iclass 38, count 0 2006.252.08:22:10.31#ibcon#wrote, iclass 38, count 0 2006.252.08:22:10.31#ibcon#about to read 3, iclass 38, count 0 2006.252.08:22:10.35#ibcon#read 3, iclass 38, count 0 2006.252.08:22:10.35#ibcon#about to read 4, iclass 38, count 0 2006.252.08:22:10.35#ibcon#read 4, iclass 38, count 0 2006.252.08:22:10.35#ibcon#about to read 5, iclass 38, count 0 2006.252.08:22:10.35#ibcon#read 5, iclass 38, count 0 2006.252.08:22:10.35#ibcon#about to read 6, iclass 38, count 0 2006.252.08:22:10.35#ibcon#read 6, iclass 38, count 0 2006.252.08:22:10.35#ibcon#end of sib2, iclass 38, count 0 2006.252.08:22:10.35#ibcon#*after write, iclass 38, count 0 2006.252.08:22:10.35#ibcon#*before return 0, iclass 38, count 0 2006.252.08:22:10.35#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.252.08:22:10.35#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.252.08:22:10.35#ibcon#about to clear, iclass 38 cls_cnt 0 2006.252.08:22:10.35#ibcon#cleared, iclass 38 cls_cnt 0 2006.252.08:22:10.35$vc4f8/va=8,7 2006.252.08:22:10.35#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.252.08:22:10.35#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.252.08:22:10.35#ibcon#ireg 11 cls_cnt 2 2006.252.08:22:10.35#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.252.08:22:10.42#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.252.08:22:10.42#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.252.08:22:10.42#ibcon#enter wrdev, iclass 40, count 2 2006.252.08:22:10.42#ibcon#first serial, iclass 40, count 2 2006.252.08:22:10.42#ibcon#enter sib2, iclass 40, count 2 2006.252.08:22:10.42#ibcon#flushed, iclass 40, count 2 2006.252.08:22:10.42#ibcon#about to write, iclass 40, count 2 2006.252.08:22:10.42#ibcon#wrote, iclass 40, count 2 2006.252.08:22:10.42#ibcon#about to read 3, iclass 40, count 2 2006.252.08:22:10.43#ibcon#read 3, iclass 40, count 2 2006.252.08:22:10.43#ibcon#about to read 4, iclass 40, count 2 2006.252.08:22:10.43#ibcon#read 4, iclass 40, count 2 2006.252.08:22:10.43#ibcon#about to read 5, iclass 40, count 2 2006.252.08:22:10.43#ibcon#read 5, iclass 40, count 2 2006.252.08:22:10.43#ibcon#about to read 6, iclass 40, count 2 2006.252.08:22:10.43#ibcon#read 6, iclass 40, count 2 2006.252.08:22:10.43#ibcon#end of sib2, iclass 40, count 2 2006.252.08:22:10.43#ibcon#*mode == 0, iclass 40, count 2 2006.252.08:22:10.43#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.252.08:22:10.43#ibcon#[25=AT08-07\r\n] 2006.252.08:22:10.43#ibcon#*before write, iclass 40, count 2 2006.252.08:22:10.43#ibcon#enter sib2, iclass 40, count 2 2006.252.08:22:10.43#ibcon#flushed, iclass 40, count 2 2006.252.08:22:10.43#ibcon#about to write, iclass 40, count 2 2006.252.08:22:10.43#ibcon#wrote, iclass 40, count 2 2006.252.08:22:10.43#ibcon#about to read 3, iclass 40, count 2 2006.252.08:22:10.46#ibcon#read 3, iclass 40, count 2 2006.252.08:22:10.46#ibcon#about to read 4, iclass 40, count 2 2006.252.08:22:10.46#ibcon#read 4, iclass 40, count 2 2006.252.08:22:10.46#ibcon#about to read 5, iclass 40, count 2 2006.252.08:22:10.46#ibcon#read 5, iclass 40, count 2 2006.252.08:22:10.46#ibcon#about to read 6, iclass 40, count 2 2006.252.08:22:10.46#ibcon#read 6, iclass 40, count 2 2006.252.08:22:10.46#ibcon#end of sib2, iclass 40, count 2 2006.252.08:22:10.46#ibcon#*after write, iclass 40, count 2 2006.252.08:22:10.46#ibcon#*before return 0, iclass 40, count 2 2006.252.08:22:10.46#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.252.08:22:10.46#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.252.08:22:10.46#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.252.08:22:10.46#ibcon#ireg 7 cls_cnt 0 2006.252.08:22:10.46#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.252.08:22:10.58#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.252.08:22:10.58#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.252.08:22:10.58#ibcon#enter wrdev, iclass 40, count 0 2006.252.08:22:10.58#ibcon#first serial, iclass 40, count 0 2006.252.08:22:10.58#ibcon#enter sib2, iclass 40, count 0 2006.252.08:22:10.58#ibcon#flushed, iclass 40, count 0 2006.252.08:22:10.58#ibcon#about to write, iclass 40, count 0 2006.252.08:22:10.58#ibcon#wrote, iclass 40, count 0 2006.252.08:22:10.58#ibcon#about to read 3, iclass 40, count 0 2006.252.08:22:10.60#ibcon#read 3, iclass 40, count 0 2006.252.08:22:10.60#ibcon#about to read 4, iclass 40, count 0 2006.252.08:22:10.60#ibcon#read 4, iclass 40, count 0 2006.252.08:22:10.60#ibcon#about to read 5, iclass 40, count 0 2006.252.08:22:10.60#ibcon#read 5, iclass 40, count 0 2006.252.08:22:10.60#ibcon#about to read 6, iclass 40, count 0 2006.252.08:22:10.60#ibcon#read 6, iclass 40, count 0 2006.252.08:22:10.60#ibcon#end of sib2, iclass 40, count 0 2006.252.08:22:10.60#ibcon#*mode == 0, iclass 40, count 0 2006.252.08:22:10.60#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.252.08:22:10.60#ibcon#[25=USB\r\n] 2006.252.08:22:10.60#ibcon#*before write, iclass 40, count 0 2006.252.08:22:10.60#ibcon#enter sib2, iclass 40, count 0 2006.252.08:22:10.60#ibcon#flushed, iclass 40, count 0 2006.252.08:22:10.60#ibcon#about to write, iclass 40, count 0 2006.252.08:22:10.60#ibcon#wrote, iclass 40, count 0 2006.252.08:22:10.60#ibcon#about to read 3, iclass 40, count 0 2006.252.08:22:10.63#ibcon#read 3, iclass 40, count 0 2006.252.08:22:10.63#ibcon#about to read 4, iclass 40, count 0 2006.252.08:22:10.63#ibcon#read 4, iclass 40, count 0 2006.252.08:22:10.63#ibcon#about to read 5, iclass 40, count 0 2006.252.08:22:10.63#ibcon#read 5, iclass 40, count 0 2006.252.08:22:10.63#ibcon#about to read 6, iclass 40, count 0 2006.252.08:22:10.63#ibcon#read 6, iclass 40, count 0 2006.252.08:22:10.63#ibcon#end of sib2, iclass 40, count 0 2006.252.08:22:10.63#ibcon#*after write, iclass 40, count 0 2006.252.08:22:10.63#ibcon#*before return 0, iclass 40, count 0 2006.252.08:22:10.63#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.252.08:22:10.63#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.252.08:22:10.63#ibcon#about to clear, iclass 40 cls_cnt 0 2006.252.08:22:10.63#ibcon#cleared, iclass 40 cls_cnt 0 2006.252.08:22:10.63$vc4f8/vblo=1,632.99 2006.252.08:22:10.63#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.252.08:22:10.63#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.252.08:22:10.63#ibcon#ireg 17 cls_cnt 0 2006.252.08:22:10.63#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.252.08:22:10.63#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.252.08:22:10.63#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.252.08:22:10.63#ibcon#enter wrdev, iclass 4, count 0 2006.252.08:22:10.63#ibcon#first serial, iclass 4, count 0 2006.252.08:22:10.63#ibcon#enter sib2, iclass 4, count 0 2006.252.08:22:10.63#ibcon#flushed, iclass 4, count 0 2006.252.08:22:10.63#ibcon#about to write, iclass 4, count 0 2006.252.08:22:10.63#ibcon#wrote, iclass 4, count 0 2006.252.08:22:10.63#ibcon#about to read 3, iclass 4, count 0 2006.252.08:22:10.65#ibcon#read 3, iclass 4, count 0 2006.252.08:22:10.65#ibcon#about to read 4, iclass 4, count 0 2006.252.08:22:10.65#ibcon#read 4, iclass 4, count 0 2006.252.08:22:10.65#ibcon#about to read 5, iclass 4, count 0 2006.252.08:22:10.65#ibcon#read 5, iclass 4, count 0 2006.252.08:22:10.65#ibcon#about to read 6, iclass 4, count 0 2006.252.08:22:10.65#ibcon#read 6, iclass 4, count 0 2006.252.08:22:10.65#ibcon#end of sib2, iclass 4, count 0 2006.252.08:22:10.65#ibcon#*mode == 0, iclass 4, count 0 2006.252.08:22:10.65#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.252.08:22:10.65#ibcon#[28=FRQ=01,632.99\r\n] 2006.252.08:22:10.65#ibcon#*before write, iclass 4, count 0 2006.252.08:22:10.65#ibcon#enter sib2, iclass 4, count 0 2006.252.08:22:10.65#ibcon#flushed, iclass 4, count 0 2006.252.08:22:10.65#ibcon#about to write, iclass 4, count 0 2006.252.08:22:10.65#ibcon#wrote, iclass 4, count 0 2006.252.08:22:10.65#ibcon#about to read 3, iclass 4, count 0 2006.252.08:22:10.69#ibcon#read 3, iclass 4, count 0 2006.252.08:22:10.69#ibcon#about to read 4, iclass 4, count 0 2006.252.08:22:10.69#ibcon#read 4, iclass 4, count 0 2006.252.08:22:10.69#ibcon#about to read 5, iclass 4, count 0 2006.252.08:22:10.69#ibcon#read 5, iclass 4, count 0 2006.252.08:22:10.69#ibcon#about to read 6, iclass 4, count 0 2006.252.08:22:10.69#ibcon#read 6, iclass 4, count 0 2006.252.08:22:10.69#ibcon#end of sib2, iclass 4, count 0 2006.252.08:22:10.69#ibcon#*after write, iclass 4, count 0 2006.252.08:22:10.69#ibcon#*before return 0, iclass 4, count 0 2006.252.08:22:10.69#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.252.08:22:10.69#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.252.08:22:10.69#ibcon#about to clear, iclass 4 cls_cnt 0 2006.252.08:22:10.69#ibcon#cleared, iclass 4 cls_cnt 0 2006.252.08:22:10.69$vc4f8/vb=1,4 2006.252.08:22:10.69#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.252.08:22:10.69#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.252.08:22:10.69#ibcon#ireg 11 cls_cnt 2 2006.252.08:22:10.69#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.252.08:22:10.69#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.252.08:22:10.69#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.252.08:22:10.69#ibcon#enter wrdev, iclass 6, count 2 2006.252.08:22:10.69#ibcon#first serial, iclass 6, count 2 2006.252.08:22:10.69#ibcon#enter sib2, iclass 6, count 2 2006.252.08:22:10.69#ibcon#flushed, iclass 6, count 2 2006.252.08:22:10.69#ibcon#about to write, iclass 6, count 2 2006.252.08:22:10.69#ibcon#wrote, iclass 6, count 2 2006.252.08:22:10.69#ibcon#about to read 3, iclass 6, count 2 2006.252.08:22:10.71#ibcon#read 3, iclass 6, count 2 2006.252.08:22:10.71#ibcon#about to read 4, iclass 6, count 2 2006.252.08:22:10.71#ibcon#read 4, iclass 6, count 2 2006.252.08:22:10.71#ibcon#about to read 5, iclass 6, count 2 2006.252.08:22:10.71#ibcon#read 5, iclass 6, count 2 2006.252.08:22:10.71#ibcon#about to read 6, iclass 6, count 2 2006.252.08:22:10.71#ibcon#read 6, iclass 6, count 2 2006.252.08:22:10.71#ibcon#end of sib2, iclass 6, count 2 2006.252.08:22:10.71#ibcon#*mode == 0, iclass 6, count 2 2006.252.08:22:10.71#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.252.08:22:10.71#ibcon#[27=AT01-04\r\n] 2006.252.08:22:10.71#ibcon#*before write, iclass 6, count 2 2006.252.08:22:10.71#ibcon#enter sib2, iclass 6, count 2 2006.252.08:22:10.71#ibcon#flushed, iclass 6, count 2 2006.252.08:22:10.71#ibcon#about to write, iclass 6, count 2 2006.252.08:22:10.71#ibcon#wrote, iclass 6, count 2 2006.252.08:22:10.71#ibcon#about to read 3, iclass 6, count 2 2006.252.08:22:10.74#ibcon#read 3, iclass 6, count 2 2006.252.08:22:10.74#ibcon#about to read 4, iclass 6, count 2 2006.252.08:22:10.74#ibcon#read 4, iclass 6, count 2 2006.252.08:22:10.74#ibcon#about to read 5, iclass 6, count 2 2006.252.08:22:10.74#ibcon#read 5, iclass 6, count 2 2006.252.08:22:10.74#ibcon#about to read 6, iclass 6, count 2 2006.252.08:22:10.74#ibcon#read 6, iclass 6, count 2 2006.252.08:22:10.74#ibcon#end of sib2, iclass 6, count 2 2006.252.08:22:10.74#ibcon#*after write, iclass 6, count 2 2006.252.08:22:10.74#ibcon#*before return 0, iclass 6, count 2 2006.252.08:22:10.74#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.252.08:22:10.74#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.252.08:22:10.74#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.252.08:22:10.74#ibcon#ireg 7 cls_cnt 0 2006.252.08:22:10.74#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.252.08:22:10.86#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.252.08:22:10.86#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.252.08:22:10.86#ibcon#enter wrdev, iclass 6, count 0 2006.252.08:22:10.86#ibcon#first serial, iclass 6, count 0 2006.252.08:22:10.86#ibcon#enter sib2, iclass 6, count 0 2006.252.08:22:10.86#ibcon#flushed, iclass 6, count 0 2006.252.08:22:10.86#ibcon#about to write, iclass 6, count 0 2006.252.08:22:10.86#ibcon#wrote, iclass 6, count 0 2006.252.08:22:10.86#ibcon#about to read 3, iclass 6, count 0 2006.252.08:22:10.88#ibcon#read 3, iclass 6, count 0 2006.252.08:22:10.88#ibcon#about to read 4, iclass 6, count 0 2006.252.08:22:10.88#ibcon#read 4, iclass 6, count 0 2006.252.08:22:10.88#ibcon#about to read 5, iclass 6, count 0 2006.252.08:22:10.88#ibcon#read 5, iclass 6, count 0 2006.252.08:22:10.88#ibcon#about to read 6, iclass 6, count 0 2006.252.08:22:10.88#ibcon#read 6, iclass 6, count 0 2006.252.08:22:10.88#ibcon#end of sib2, iclass 6, count 0 2006.252.08:22:10.88#ibcon#*mode == 0, iclass 6, count 0 2006.252.08:22:10.88#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.252.08:22:10.88#ibcon#[27=USB\r\n] 2006.252.08:22:10.88#ibcon#*before write, iclass 6, count 0 2006.252.08:22:10.88#ibcon#enter sib2, iclass 6, count 0 2006.252.08:22:10.88#ibcon#flushed, iclass 6, count 0 2006.252.08:22:10.88#ibcon#about to write, iclass 6, count 0 2006.252.08:22:10.88#ibcon#wrote, iclass 6, count 0 2006.252.08:22:10.88#ibcon#about to read 3, iclass 6, count 0 2006.252.08:22:10.91#ibcon#read 3, iclass 6, count 0 2006.252.08:22:10.91#ibcon#about to read 4, iclass 6, count 0 2006.252.08:22:10.91#ibcon#read 4, iclass 6, count 0 2006.252.08:22:10.91#ibcon#about to read 5, iclass 6, count 0 2006.252.08:22:10.91#ibcon#read 5, iclass 6, count 0 2006.252.08:22:10.91#ibcon#about to read 6, iclass 6, count 0 2006.252.08:22:10.91#ibcon#read 6, iclass 6, count 0 2006.252.08:22:10.91#ibcon#end of sib2, iclass 6, count 0 2006.252.08:22:10.91#ibcon#*after write, iclass 6, count 0 2006.252.08:22:10.91#ibcon#*before return 0, iclass 6, count 0 2006.252.08:22:10.91#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.252.08:22:10.91#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.252.08:22:10.91#ibcon#about to clear, iclass 6 cls_cnt 0 2006.252.08:22:10.91#ibcon#cleared, iclass 6 cls_cnt 0 2006.252.08:22:10.91$vc4f8/vblo=2,640.99 2006.252.08:22:10.91#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.252.08:22:10.91#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.252.08:22:10.91#ibcon#ireg 17 cls_cnt 0 2006.252.08:22:10.91#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.252.08:22:10.91#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.252.08:22:10.91#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.252.08:22:10.91#ibcon#enter wrdev, iclass 10, count 0 2006.252.08:22:10.91#ibcon#first serial, iclass 10, count 0 2006.252.08:22:10.91#ibcon#enter sib2, iclass 10, count 0 2006.252.08:22:10.91#ibcon#flushed, iclass 10, count 0 2006.252.08:22:10.91#ibcon#about to write, iclass 10, count 0 2006.252.08:22:10.91#ibcon#wrote, iclass 10, count 0 2006.252.08:22:10.91#ibcon#about to read 3, iclass 10, count 0 2006.252.08:22:10.93#ibcon#read 3, iclass 10, count 0 2006.252.08:22:10.93#ibcon#about to read 4, iclass 10, count 0 2006.252.08:22:10.93#ibcon#read 4, iclass 10, count 0 2006.252.08:22:10.93#ibcon#about to read 5, iclass 10, count 0 2006.252.08:22:10.93#ibcon#read 5, iclass 10, count 0 2006.252.08:22:10.93#ibcon#about to read 6, iclass 10, count 0 2006.252.08:22:10.93#ibcon#read 6, iclass 10, count 0 2006.252.08:22:10.93#ibcon#end of sib2, iclass 10, count 0 2006.252.08:22:10.93#ibcon#*mode == 0, iclass 10, count 0 2006.252.08:22:10.93#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.252.08:22:10.93#ibcon#[28=FRQ=02,640.99\r\n] 2006.252.08:22:10.93#ibcon#*before write, iclass 10, count 0 2006.252.08:22:10.93#ibcon#enter sib2, iclass 10, count 0 2006.252.08:22:10.93#ibcon#flushed, iclass 10, count 0 2006.252.08:22:10.93#ibcon#about to write, iclass 10, count 0 2006.252.08:22:10.93#ibcon#wrote, iclass 10, count 0 2006.252.08:22:10.93#ibcon#about to read 3, iclass 10, count 0 2006.252.08:22:10.97#ibcon#read 3, iclass 10, count 0 2006.252.08:22:10.97#ibcon#about to read 4, iclass 10, count 0 2006.252.08:22:10.97#ibcon#read 4, iclass 10, count 0 2006.252.08:22:10.97#ibcon#about to read 5, iclass 10, count 0 2006.252.08:22:10.97#ibcon#read 5, iclass 10, count 0 2006.252.08:22:10.97#ibcon#about to read 6, iclass 10, count 0 2006.252.08:22:10.97#ibcon#read 6, iclass 10, count 0 2006.252.08:22:10.97#ibcon#end of sib2, iclass 10, count 0 2006.252.08:22:10.97#ibcon#*after write, iclass 10, count 0 2006.252.08:22:10.97#ibcon#*before return 0, iclass 10, count 0 2006.252.08:22:10.97#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.252.08:22:10.97#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.252.08:22:10.97#ibcon#about to clear, iclass 10 cls_cnt 0 2006.252.08:22:10.97#ibcon#cleared, iclass 10 cls_cnt 0 2006.252.08:22:10.97$vc4f8/vb=2,5 2006.252.08:22:10.97#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.252.08:22:10.97#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.252.08:22:10.97#ibcon#ireg 11 cls_cnt 2 2006.252.08:22:10.97#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.252.08:22:11.03#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.252.08:22:11.03#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.252.08:22:11.03#ibcon#enter wrdev, iclass 12, count 2 2006.252.08:22:11.03#ibcon#first serial, iclass 12, count 2 2006.252.08:22:11.03#ibcon#enter sib2, iclass 12, count 2 2006.252.08:22:11.03#ibcon#flushed, iclass 12, count 2 2006.252.08:22:11.03#ibcon#about to write, iclass 12, count 2 2006.252.08:22:11.03#ibcon#wrote, iclass 12, count 2 2006.252.08:22:11.03#ibcon#about to read 3, iclass 12, count 2 2006.252.08:22:11.05#ibcon#read 3, iclass 12, count 2 2006.252.08:22:11.05#ibcon#about to read 4, iclass 12, count 2 2006.252.08:22:11.05#ibcon#read 4, iclass 12, count 2 2006.252.08:22:11.05#ibcon#about to read 5, iclass 12, count 2 2006.252.08:22:11.05#ibcon#read 5, iclass 12, count 2 2006.252.08:22:11.05#ibcon#about to read 6, iclass 12, count 2 2006.252.08:22:11.05#ibcon#read 6, iclass 12, count 2 2006.252.08:22:11.05#ibcon#end of sib2, iclass 12, count 2 2006.252.08:22:11.05#ibcon#*mode == 0, iclass 12, count 2 2006.252.08:22:11.05#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.252.08:22:11.05#ibcon#[27=AT02-05\r\n] 2006.252.08:22:11.05#ibcon#*before write, iclass 12, count 2 2006.252.08:22:11.05#ibcon#enter sib2, iclass 12, count 2 2006.252.08:22:11.05#ibcon#flushed, iclass 12, count 2 2006.252.08:22:11.05#ibcon#about to write, iclass 12, count 2 2006.252.08:22:11.05#ibcon#wrote, iclass 12, count 2 2006.252.08:22:11.05#ibcon#about to read 3, iclass 12, count 2 2006.252.08:22:11.08#ibcon#read 3, iclass 12, count 2 2006.252.08:22:11.08#ibcon#about to read 4, iclass 12, count 2 2006.252.08:22:11.08#ibcon#read 4, iclass 12, count 2 2006.252.08:22:11.08#ibcon#about to read 5, iclass 12, count 2 2006.252.08:22:11.08#ibcon#read 5, iclass 12, count 2 2006.252.08:22:11.08#ibcon#about to read 6, iclass 12, count 2 2006.252.08:22:11.08#ibcon#read 6, iclass 12, count 2 2006.252.08:22:11.08#ibcon#end of sib2, iclass 12, count 2 2006.252.08:22:11.08#ibcon#*after write, iclass 12, count 2 2006.252.08:22:11.08#ibcon#*before return 0, iclass 12, count 2 2006.252.08:22:11.08#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.252.08:22:11.08#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.252.08:22:11.08#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.252.08:22:11.08#ibcon#ireg 7 cls_cnt 0 2006.252.08:22:11.08#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.252.08:22:11.20#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.252.08:22:11.20#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.252.08:22:11.20#ibcon#enter wrdev, iclass 12, count 0 2006.252.08:22:11.20#ibcon#first serial, iclass 12, count 0 2006.252.08:22:11.20#ibcon#enter sib2, iclass 12, count 0 2006.252.08:22:11.20#ibcon#flushed, iclass 12, count 0 2006.252.08:22:11.20#ibcon#about to write, iclass 12, count 0 2006.252.08:22:11.20#ibcon#wrote, iclass 12, count 0 2006.252.08:22:11.20#ibcon#about to read 3, iclass 12, count 0 2006.252.08:22:11.22#ibcon#read 3, iclass 12, count 0 2006.252.08:22:11.22#ibcon#about to read 4, iclass 12, count 0 2006.252.08:22:11.22#ibcon#read 4, iclass 12, count 0 2006.252.08:22:11.22#ibcon#about to read 5, iclass 12, count 0 2006.252.08:22:11.22#ibcon#read 5, iclass 12, count 0 2006.252.08:22:11.22#ibcon#about to read 6, iclass 12, count 0 2006.252.08:22:11.22#ibcon#read 6, iclass 12, count 0 2006.252.08:22:11.22#ibcon#end of sib2, iclass 12, count 0 2006.252.08:22:11.22#ibcon#*mode == 0, iclass 12, count 0 2006.252.08:22:11.22#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.252.08:22:11.22#ibcon#[27=USB\r\n] 2006.252.08:22:11.22#ibcon#*before write, iclass 12, count 0 2006.252.08:22:11.22#ibcon#enter sib2, iclass 12, count 0 2006.252.08:22:11.22#ibcon#flushed, iclass 12, count 0 2006.252.08:22:11.22#ibcon#about to write, iclass 12, count 0 2006.252.08:22:11.22#ibcon#wrote, iclass 12, count 0 2006.252.08:22:11.22#ibcon#about to read 3, iclass 12, count 0 2006.252.08:22:11.25#ibcon#read 3, iclass 12, count 0 2006.252.08:22:11.25#ibcon#about to read 4, iclass 12, count 0 2006.252.08:22:11.25#ibcon#read 4, iclass 12, count 0 2006.252.08:22:11.25#ibcon#about to read 5, iclass 12, count 0 2006.252.08:22:11.25#ibcon#read 5, iclass 12, count 0 2006.252.08:22:11.25#ibcon#about to read 6, iclass 12, count 0 2006.252.08:22:11.25#ibcon#read 6, iclass 12, count 0 2006.252.08:22:11.25#ibcon#end of sib2, iclass 12, count 0 2006.252.08:22:11.25#ibcon#*after write, iclass 12, count 0 2006.252.08:22:11.25#ibcon#*before return 0, iclass 12, count 0 2006.252.08:22:11.25#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.252.08:22:11.25#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.252.08:22:11.25#ibcon#about to clear, iclass 12 cls_cnt 0 2006.252.08:22:11.25#ibcon#cleared, iclass 12 cls_cnt 0 2006.252.08:22:11.25$vc4f8/vblo=3,656.99 2006.252.08:22:11.25#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.252.08:22:11.25#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.252.08:22:11.25#ibcon#ireg 17 cls_cnt 0 2006.252.08:22:11.25#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.252.08:22:11.25#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.252.08:22:11.25#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.252.08:22:11.25#ibcon#enter wrdev, iclass 14, count 0 2006.252.08:22:11.25#ibcon#first serial, iclass 14, count 0 2006.252.08:22:11.25#ibcon#enter sib2, iclass 14, count 0 2006.252.08:22:11.25#ibcon#flushed, iclass 14, count 0 2006.252.08:22:11.25#ibcon#about to write, iclass 14, count 0 2006.252.08:22:11.25#ibcon#wrote, iclass 14, count 0 2006.252.08:22:11.25#ibcon#about to read 3, iclass 14, count 0 2006.252.08:22:11.27#ibcon#read 3, iclass 14, count 0 2006.252.08:22:11.27#ibcon#about to read 4, iclass 14, count 0 2006.252.08:22:11.27#ibcon#read 4, iclass 14, count 0 2006.252.08:22:11.27#ibcon#about to read 5, iclass 14, count 0 2006.252.08:22:11.27#ibcon#read 5, iclass 14, count 0 2006.252.08:22:11.27#ibcon#about to read 6, iclass 14, count 0 2006.252.08:22:11.27#ibcon#read 6, iclass 14, count 0 2006.252.08:22:11.27#ibcon#end of sib2, iclass 14, count 0 2006.252.08:22:11.27#ibcon#*mode == 0, iclass 14, count 0 2006.252.08:22:11.27#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.252.08:22:11.27#ibcon#[28=FRQ=03,656.99\r\n] 2006.252.08:22:11.27#ibcon#*before write, iclass 14, count 0 2006.252.08:22:11.27#ibcon#enter sib2, iclass 14, count 0 2006.252.08:22:11.27#ibcon#flushed, iclass 14, count 0 2006.252.08:22:11.27#ibcon#about to write, iclass 14, count 0 2006.252.08:22:11.27#ibcon#wrote, iclass 14, count 0 2006.252.08:22:11.27#ibcon#about to read 3, iclass 14, count 0 2006.252.08:22:11.31#ibcon#read 3, iclass 14, count 0 2006.252.08:22:11.31#ibcon#about to read 4, iclass 14, count 0 2006.252.08:22:11.31#ibcon#read 4, iclass 14, count 0 2006.252.08:22:11.31#ibcon#about to read 5, iclass 14, count 0 2006.252.08:22:11.31#ibcon#read 5, iclass 14, count 0 2006.252.08:22:11.31#ibcon#about to read 6, iclass 14, count 0 2006.252.08:22:11.31#ibcon#read 6, iclass 14, count 0 2006.252.08:22:11.31#ibcon#end of sib2, iclass 14, count 0 2006.252.08:22:11.31#ibcon#*after write, iclass 14, count 0 2006.252.08:22:11.31#ibcon#*before return 0, iclass 14, count 0 2006.252.08:22:11.31#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.252.08:22:11.31#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.252.08:22:11.31#ibcon#about to clear, iclass 14 cls_cnt 0 2006.252.08:22:11.31#ibcon#cleared, iclass 14 cls_cnt 0 2006.252.08:22:11.31$vc4f8/vb=3,4 2006.252.08:22:11.31#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.252.08:22:11.31#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.252.08:22:11.31#ibcon#ireg 11 cls_cnt 2 2006.252.08:22:11.31#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.252.08:22:11.37#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.252.08:22:11.37#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.252.08:22:11.37#ibcon#enter wrdev, iclass 16, count 2 2006.252.08:22:11.37#ibcon#first serial, iclass 16, count 2 2006.252.08:22:11.37#ibcon#enter sib2, iclass 16, count 2 2006.252.08:22:11.37#ibcon#flushed, iclass 16, count 2 2006.252.08:22:11.37#ibcon#about to write, iclass 16, count 2 2006.252.08:22:11.37#ibcon#wrote, iclass 16, count 2 2006.252.08:22:11.37#ibcon#about to read 3, iclass 16, count 2 2006.252.08:22:11.39#ibcon#read 3, iclass 16, count 2 2006.252.08:22:11.39#ibcon#about to read 4, iclass 16, count 2 2006.252.08:22:11.39#ibcon#read 4, iclass 16, count 2 2006.252.08:22:11.39#ibcon#about to read 5, iclass 16, count 2 2006.252.08:22:11.39#ibcon#read 5, iclass 16, count 2 2006.252.08:22:11.39#ibcon#about to read 6, iclass 16, count 2 2006.252.08:22:11.39#ibcon#read 6, iclass 16, count 2 2006.252.08:22:11.39#ibcon#end of sib2, iclass 16, count 2 2006.252.08:22:11.39#ibcon#*mode == 0, iclass 16, count 2 2006.252.08:22:11.39#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.252.08:22:11.39#ibcon#[27=AT03-04\r\n] 2006.252.08:22:11.39#ibcon#*before write, iclass 16, count 2 2006.252.08:22:11.39#ibcon#enter sib2, iclass 16, count 2 2006.252.08:22:11.39#ibcon#flushed, iclass 16, count 2 2006.252.08:22:11.39#ibcon#about to write, iclass 16, count 2 2006.252.08:22:11.39#ibcon#wrote, iclass 16, count 2 2006.252.08:22:11.39#ibcon#about to read 3, iclass 16, count 2 2006.252.08:22:11.42#ibcon#read 3, iclass 16, count 2 2006.252.08:22:11.42#ibcon#about to read 4, iclass 16, count 2 2006.252.08:22:11.42#ibcon#read 4, iclass 16, count 2 2006.252.08:22:11.42#ibcon#about to read 5, iclass 16, count 2 2006.252.08:22:11.42#ibcon#read 5, iclass 16, count 2 2006.252.08:22:11.42#ibcon#about to read 6, iclass 16, count 2 2006.252.08:22:11.42#ibcon#read 6, iclass 16, count 2 2006.252.08:22:11.42#ibcon#end of sib2, iclass 16, count 2 2006.252.08:22:11.42#ibcon#*after write, iclass 16, count 2 2006.252.08:22:11.42#ibcon#*before return 0, iclass 16, count 2 2006.252.08:22:11.42#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.252.08:22:11.42#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.252.08:22:11.42#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.252.08:22:11.42#ibcon#ireg 7 cls_cnt 0 2006.252.08:22:11.42#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.252.08:22:11.54#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.252.08:22:11.54#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.252.08:22:11.54#ibcon#enter wrdev, iclass 16, count 0 2006.252.08:22:11.54#ibcon#first serial, iclass 16, count 0 2006.252.08:22:11.54#ibcon#enter sib2, iclass 16, count 0 2006.252.08:22:11.54#ibcon#flushed, iclass 16, count 0 2006.252.08:22:11.54#ibcon#about to write, iclass 16, count 0 2006.252.08:22:11.54#ibcon#wrote, iclass 16, count 0 2006.252.08:22:11.54#ibcon#about to read 3, iclass 16, count 0 2006.252.08:22:11.56#ibcon#read 3, iclass 16, count 0 2006.252.08:22:11.56#ibcon#about to read 4, iclass 16, count 0 2006.252.08:22:11.56#ibcon#read 4, iclass 16, count 0 2006.252.08:22:11.56#ibcon#about to read 5, iclass 16, count 0 2006.252.08:22:11.56#ibcon#read 5, iclass 16, count 0 2006.252.08:22:11.56#ibcon#about to read 6, iclass 16, count 0 2006.252.08:22:11.56#ibcon#read 6, iclass 16, count 0 2006.252.08:22:11.56#ibcon#end of sib2, iclass 16, count 0 2006.252.08:22:11.56#ibcon#*mode == 0, iclass 16, count 0 2006.252.08:22:11.56#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.252.08:22:11.56#ibcon#[27=USB\r\n] 2006.252.08:22:11.56#ibcon#*before write, iclass 16, count 0 2006.252.08:22:11.56#ibcon#enter sib2, iclass 16, count 0 2006.252.08:22:11.56#ibcon#flushed, iclass 16, count 0 2006.252.08:22:11.56#ibcon#about to write, iclass 16, count 0 2006.252.08:22:11.56#ibcon#wrote, iclass 16, count 0 2006.252.08:22:11.56#ibcon#about to read 3, iclass 16, count 0 2006.252.08:22:11.59#ibcon#read 3, iclass 16, count 0 2006.252.08:22:11.59#ibcon#about to read 4, iclass 16, count 0 2006.252.08:22:11.59#ibcon#read 4, iclass 16, count 0 2006.252.08:22:11.59#ibcon#about to read 5, iclass 16, count 0 2006.252.08:22:11.59#ibcon#read 5, iclass 16, count 0 2006.252.08:22:11.59#ibcon#about to read 6, iclass 16, count 0 2006.252.08:22:11.59#ibcon#read 6, iclass 16, count 0 2006.252.08:22:11.59#ibcon#end of sib2, iclass 16, count 0 2006.252.08:22:11.59#ibcon#*after write, iclass 16, count 0 2006.252.08:22:11.59#ibcon#*before return 0, iclass 16, count 0 2006.252.08:22:11.59#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.252.08:22:11.59#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.252.08:22:11.59#ibcon#about to clear, iclass 16 cls_cnt 0 2006.252.08:22:11.59#ibcon#cleared, iclass 16 cls_cnt 0 2006.252.08:22:11.59$vc4f8/vblo=4,712.99 2006.252.08:22:11.59#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.252.08:22:11.59#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.252.08:22:11.59#ibcon#ireg 17 cls_cnt 0 2006.252.08:22:11.59#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.252.08:22:11.59#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.252.08:22:11.59#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.252.08:22:11.59#ibcon#enter wrdev, iclass 18, count 0 2006.252.08:22:11.59#ibcon#first serial, iclass 18, count 0 2006.252.08:22:11.59#ibcon#enter sib2, iclass 18, count 0 2006.252.08:22:11.59#ibcon#flushed, iclass 18, count 0 2006.252.08:22:11.59#ibcon#about to write, iclass 18, count 0 2006.252.08:22:11.59#ibcon#wrote, iclass 18, count 0 2006.252.08:22:11.59#ibcon#about to read 3, iclass 18, count 0 2006.252.08:22:11.61#ibcon#read 3, iclass 18, count 0 2006.252.08:22:11.61#ibcon#about to read 4, iclass 18, count 0 2006.252.08:22:11.61#ibcon#read 4, iclass 18, count 0 2006.252.08:22:11.61#ibcon#about to read 5, iclass 18, count 0 2006.252.08:22:11.61#ibcon#read 5, iclass 18, count 0 2006.252.08:22:11.61#ibcon#about to read 6, iclass 18, count 0 2006.252.08:22:11.61#ibcon#read 6, iclass 18, count 0 2006.252.08:22:11.61#ibcon#end of sib2, iclass 18, count 0 2006.252.08:22:11.61#ibcon#*mode == 0, iclass 18, count 0 2006.252.08:22:11.61#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.252.08:22:11.61#ibcon#[28=FRQ=04,712.99\r\n] 2006.252.08:22:11.61#ibcon#*before write, iclass 18, count 0 2006.252.08:22:11.61#ibcon#enter sib2, iclass 18, count 0 2006.252.08:22:11.61#ibcon#flushed, iclass 18, count 0 2006.252.08:22:11.61#ibcon#about to write, iclass 18, count 0 2006.252.08:22:11.61#ibcon#wrote, iclass 18, count 0 2006.252.08:22:11.61#ibcon#about to read 3, iclass 18, count 0 2006.252.08:22:11.65#ibcon#read 3, iclass 18, count 0 2006.252.08:22:11.65#ibcon#about to read 4, iclass 18, count 0 2006.252.08:22:11.65#ibcon#read 4, iclass 18, count 0 2006.252.08:22:11.65#ibcon#about to read 5, iclass 18, count 0 2006.252.08:22:11.65#ibcon#read 5, iclass 18, count 0 2006.252.08:22:11.65#ibcon#about to read 6, iclass 18, count 0 2006.252.08:22:11.65#ibcon#read 6, iclass 18, count 0 2006.252.08:22:11.65#ibcon#end of sib2, iclass 18, count 0 2006.252.08:22:11.65#ibcon#*after write, iclass 18, count 0 2006.252.08:22:11.65#ibcon#*before return 0, iclass 18, count 0 2006.252.08:22:11.65#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.252.08:22:11.65#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.252.08:22:11.65#ibcon#about to clear, iclass 18 cls_cnt 0 2006.252.08:22:11.65#ibcon#cleared, iclass 18 cls_cnt 0 2006.252.08:22:11.65$vc4f8/vb=4,4 2006.252.08:22:11.65#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.252.08:22:11.65#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.252.08:22:11.65#ibcon#ireg 11 cls_cnt 2 2006.252.08:22:11.65#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.252.08:22:11.71#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.252.08:22:11.71#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.252.08:22:11.71#ibcon#enter wrdev, iclass 20, count 2 2006.252.08:22:11.71#ibcon#first serial, iclass 20, count 2 2006.252.08:22:11.71#ibcon#enter sib2, iclass 20, count 2 2006.252.08:22:11.71#ibcon#flushed, iclass 20, count 2 2006.252.08:22:11.71#ibcon#about to write, iclass 20, count 2 2006.252.08:22:11.71#ibcon#wrote, iclass 20, count 2 2006.252.08:22:11.71#ibcon#about to read 3, iclass 20, count 2 2006.252.08:22:11.73#ibcon#read 3, iclass 20, count 2 2006.252.08:22:11.73#ibcon#about to read 4, iclass 20, count 2 2006.252.08:22:11.73#ibcon#read 4, iclass 20, count 2 2006.252.08:22:11.73#ibcon#about to read 5, iclass 20, count 2 2006.252.08:22:11.73#ibcon#read 5, iclass 20, count 2 2006.252.08:22:11.73#ibcon#about to read 6, iclass 20, count 2 2006.252.08:22:11.73#ibcon#read 6, iclass 20, count 2 2006.252.08:22:11.73#ibcon#end of sib2, iclass 20, count 2 2006.252.08:22:11.73#ibcon#*mode == 0, iclass 20, count 2 2006.252.08:22:11.73#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.252.08:22:11.73#ibcon#[27=AT04-04\r\n] 2006.252.08:22:11.73#ibcon#*before write, iclass 20, count 2 2006.252.08:22:11.73#ibcon#enter sib2, iclass 20, count 2 2006.252.08:22:11.73#ibcon#flushed, iclass 20, count 2 2006.252.08:22:11.73#ibcon#about to write, iclass 20, count 2 2006.252.08:22:11.73#ibcon#wrote, iclass 20, count 2 2006.252.08:22:11.73#ibcon#about to read 3, iclass 20, count 2 2006.252.08:22:11.76#ibcon#read 3, iclass 20, count 2 2006.252.08:22:11.76#ibcon#about to read 4, iclass 20, count 2 2006.252.08:22:11.76#ibcon#read 4, iclass 20, count 2 2006.252.08:22:11.76#ibcon#about to read 5, iclass 20, count 2 2006.252.08:22:11.76#ibcon#read 5, iclass 20, count 2 2006.252.08:22:11.76#ibcon#about to read 6, iclass 20, count 2 2006.252.08:22:11.76#ibcon#read 6, iclass 20, count 2 2006.252.08:22:11.76#ibcon#end of sib2, iclass 20, count 2 2006.252.08:22:11.76#ibcon#*after write, iclass 20, count 2 2006.252.08:22:11.76#ibcon#*before return 0, iclass 20, count 2 2006.252.08:22:11.76#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.252.08:22:11.76#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.252.08:22:11.76#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.252.08:22:11.76#ibcon#ireg 7 cls_cnt 0 2006.252.08:22:11.76#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.252.08:22:11.88#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.252.08:22:11.88#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.252.08:22:11.88#ibcon#enter wrdev, iclass 20, count 0 2006.252.08:22:11.88#ibcon#first serial, iclass 20, count 0 2006.252.08:22:11.88#ibcon#enter sib2, iclass 20, count 0 2006.252.08:22:11.88#ibcon#flushed, iclass 20, count 0 2006.252.08:22:11.88#ibcon#about to write, iclass 20, count 0 2006.252.08:22:11.88#ibcon#wrote, iclass 20, count 0 2006.252.08:22:11.88#ibcon#about to read 3, iclass 20, count 0 2006.252.08:22:11.90#ibcon#read 3, iclass 20, count 0 2006.252.08:22:11.90#ibcon#about to read 4, iclass 20, count 0 2006.252.08:22:11.90#ibcon#read 4, iclass 20, count 0 2006.252.08:22:11.90#ibcon#about to read 5, iclass 20, count 0 2006.252.08:22:11.90#ibcon#read 5, iclass 20, count 0 2006.252.08:22:11.90#ibcon#about to read 6, iclass 20, count 0 2006.252.08:22:11.90#ibcon#read 6, iclass 20, count 0 2006.252.08:22:11.90#ibcon#end of sib2, iclass 20, count 0 2006.252.08:22:11.90#ibcon#*mode == 0, iclass 20, count 0 2006.252.08:22:11.90#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.252.08:22:11.90#ibcon#[27=USB\r\n] 2006.252.08:22:11.90#ibcon#*before write, iclass 20, count 0 2006.252.08:22:11.90#ibcon#enter sib2, iclass 20, count 0 2006.252.08:22:11.90#ibcon#flushed, iclass 20, count 0 2006.252.08:22:11.90#ibcon#about to write, iclass 20, count 0 2006.252.08:22:11.90#ibcon#wrote, iclass 20, count 0 2006.252.08:22:11.90#ibcon#about to read 3, iclass 20, count 0 2006.252.08:22:11.93#ibcon#read 3, iclass 20, count 0 2006.252.08:22:11.93#ibcon#about to read 4, iclass 20, count 0 2006.252.08:22:11.93#ibcon#read 4, iclass 20, count 0 2006.252.08:22:11.93#ibcon#about to read 5, iclass 20, count 0 2006.252.08:22:11.93#ibcon#read 5, iclass 20, count 0 2006.252.08:22:11.93#ibcon#about to read 6, iclass 20, count 0 2006.252.08:22:11.93#ibcon#read 6, iclass 20, count 0 2006.252.08:22:11.93#ibcon#end of sib2, iclass 20, count 0 2006.252.08:22:11.93#ibcon#*after write, iclass 20, count 0 2006.252.08:22:11.93#ibcon#*before return 0, iclass 20, count 0 2006.252.08:22:11.93#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.252.08:22:11.93#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.252.08:22:11.93#ibcon#about to clear, iclass 20 cls_cnt 0 2006.252.08:22:11.93#ibcon#cleared, iclass 20 cls_cnt 0 2006.252.08:22:11.93$vc4f8/vblo=5,744.99 2006.252.08:22:11.93#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.252.08:22:11.93#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.252.08:22:11.93#ibcon#ireg 17 cls_cnt 0 2006.252.08:22:11.93#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.252.08:22:11.93#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.252.08:22:11.93#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.252.08:22:11.93#ibcon#enter wrdev, iclass 22, count 0 2006.252.08:22:11.93#ibcon#first serial, iclass 22, count 0 2006.252.08:22:11.93#ibcon#enter sib2, iclass 22, count 0 2006.252.08:22:11.93#ibcon#flushed, iclass 22, count 0 2006.252.08:22:11.93#ibcon#about to write, iclass 22, count 0 2006.252.08:22:11.93#ibcon#wrote, iclass 22, count 0 2006.252.08:22:11.93#ibcon#about to read 3, iclass 22, count 0 2006.252.08:22:11.95#ibcon#read 3, iclass 22, count 0 2006.252.08:22:11.95#ibcon#about to read 4, iclass 22, count 0 2006.252.08:22:11.95#ibcon#read 4, iclass 22, count 0 2006.252.08:22:11.95#ibcon#about to read 5, iclass 22, count 0 2006.252.08:22:11.95#ibcon#read 5, iclass 22, count 0 2006.252.08:22:11.95#ibcon#about to read 6, iclass 22, count 0 2006.252.08:22:11.95#ibcon#read 6, iclass 22, count 0 2006.252.08:22:11.95#ibcon#end of sib2, iclass 22, count 0 2006.252.08:22:11.95#ibcon#*mode == 0, iclass 22, count 0 2006.252.08:22:11.95#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.252.08:22:11.95#ibcon#[28=FRQ=05,744.99\r\n] 2006.252.08:22:11.95#ibcon#*before write, iclass 22, count 0 2006.252.08:22:11.95#ibcon#enter sib2, iclass 22, count 0 2006.252.08:22:11.95#ibcon#flushed, iclass 22, count 0 2006.252.08:22:11.95#ibcon#about to write, iclass 22, count 0 2006.252.08:22:11.95#ibcon#wrote, iclass 22, count 0 2006.252.08:22:11.95#ibcon#about to read 3, iclass 22, count 0 2006.252.08:22:11.99#ibcon#read 3, iclass 22, count 0 2006.252.08:22:11.99#ibcon#about to read 4, iclass 22, count 0 2006.252.08:22:11.99#ibcon#read 4, iclass 22, count 0 2006.252.08:22:11.99#ibcon#about to read 5, iclass 22, count 0 2006.252.08:22:11.99#ibcon#read 5, iclass 22, count 0 2006.252.08:22:11.99#ibcon#about to read 6, iclass 22, count 0 2006.252.08:22:11.99#ibcon#read 6, iclass 22, count 0 2006.252.08:22:11.99#ibcon#end of sib2, iclass 22, count 0 2006.252.08:22:11.99#ibcon#*after write, iclass 22, count 0 2006.252.08:22:11.99#ibcon#*before return 0, iclass 22, count 0 2006.252.08:22:11.99#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.252.08:22:11.99#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.252.08:22:11.99#ibcon#about to clear, iclass 22 cls_cnt 0 2006.252.08:22:11.99#ibcon#cleared, iclass 22 cls_cnt 0 2006.252.08:22:11.99$vc4f8/vb=5,4 2006.252.08:22:11.99#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.252.08:22:11.99#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.252.08:22:11.99#ibcon#ireg 11 cls_cnt 2 2006.252.08:22:11.99#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.252.08:22:12.05#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.252.08:22:12.05#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.252.08:22:12.05#ibcon#enter wrdev, iclass 24, count 2 2006.252.08:22:12.05#ibcon#first serial, iclass 24, count 2 2006.252.08:22:12.05#ibcon#enter sib2, iclass 24, count 2 2006.252.08:22:12.05#ibcon#flushed, iclass 24, count 2 2006.252.08:22:12.05#ibcon#about to write, iclass 24, count 2 2006.252.08:22:12.05#ibcon#wrote, iclass 24, count 2 2006.252.08:22:12.05#ibcon#about to read 3, iclass 24, count 2 2006.252.08:22:12.07#ibcon#read 3, iclass 24, count 2 2006.252.08:22:12.07#ibcon#about to read 4, iclass 24, count 2 2006.252.08:22:12.07#ibcon#read 4, iclass 24, count 2 2006.252.08:22:12.07#ibcon#about to read 5, iclass 24, count 2 2006.252.08:22:12.07#ibcon#read 5, iclass 24, count 2 2006.252.08:22:12.07#ibcon#about to read 6, iclass 24, count 2 2006.252.08:22:12.07#ibcon#read 6, iclass 24, count 2 2006.252.08:22:12.07#ibcon#end of sib2, iclass 24, count 2 2006.252.08:22:12.07#ibcon#*mode == 0, iclass 24, count 2 2006.252.08:22:12.07#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.252.08:22:12.07#ibcon#[27=AT05-04\r\n] 2006.252.08:22:12.07#ibcon#*before write, iclass 24, count 2 2006.252.08:22:12.07#ibcon#enter sib2, iclass 24, count 2 2006.252.08:22:12.07#ibcon#flushed, iclass 24, count 2 2006.252.08:22:12.07#ibcon#about to write, iclass 24, count 2 2006.252.08:22:12.07#ibcon#wrote, iclass 24, count 2 2006.252.08:22:12.07#ibcon#about to read 3, iclass 24, count 2 2006.252.08:22:12.10#ibcon#read 3, iclass 24, count 2 2006.252.08:22:12.10#ibcon#about to read 4, iclass 24, count 2 2006.252.08:22:12.10#ibcon#read 4, iclass 24, count 2 2006.252.08:22:12.10#ibcon#about to read 5, iclass 24, count 2 2006.252.08:22:12.10#ibcon#read 5, iclass 24, count 2 2006.252.08:22:12.10#ibcon#about to read 6, iclass 24, count 2 2006.252.08:22:12.10#ibcon#read 6, iclass 24, count 2 2006.252.08:22:12.10#ibcon#end of sib2, iclass 24, count 2 2006.252.08:22:12.10#ibcon#*after write, iclass 24, count 2 2006.252.08:22:12.10#ibcon#*before return 0, iclass 24, count 2 2006.252.08:22:12.10#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.252.08:22:12.10#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.252.08:22:12.10#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.252.08:22:12.10#ibcon#ireg 7 cls_cnt 0 2006.252.08:22:12.10#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.252.08:22:12.22#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.252.08:22:12.22#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.252.08:22:12.22#ibcon#enter wrdev, iclass 24, count 0 2006.252.08:22:12.22#ibcon#first serial, iclass 24, count 0 2006.252.08:22:12.22#ibcon#enter sib2, iclass 24, count 0 2006.252.08:22:12.22#ibcon#flushed, iclass 24, count 0 2006.252.08:22:12.22#ibcon#about to write, iclass 24, count 0 2006.252.08:22:12.22#ibcon#wrote, iclass 24, count 0 2006.252.08:22:12.22#ibcon#about to read 3, iclass 24, count 0 2006.252.08:22:12.26#ibcon#read 3, iclass 24, count 0 2006.252.08:22:12.26#ibcon#about to read 4, iclass 24, count 0 2006.252.08:22:12.26#ibcon#read 4, iclass 24, count 0 2006.252.08:22:12.26#ibcon#about to read 5, iclass 24, count 0 2006.252.08:22:12.26#ibcon#read 5, iclass 24, count 0 2006.252.08:22:12.26#ibcon#about to read 6, iclass 24, count 0 2006.252.08:22:12.26#ibcon#read 6, iclass 24, count 0 2006.252.08:22:12.26#ibcon#end of sib2, iclass 24, count 0 2006.252.08:22:12.26#ibcon#*mode == 0, iclass 24, count 0 2006.252.08:22:12.26#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.252.08:22:12.26#ibcon#[27=USB\r\n] 2006.252.08:22:12.26#ibcon#*before write, iclass 24, count 0 2006.252.08:22:12.26#ibcon#enter sib2, iclass 24, count 0 2006.252.08:22:12.26#ibcon#flushed, iclass 24, count 0 2006.252.08:22:12.26#ibcon#about to write, iclass 24, count 0 2006.252.08:22:12.26#ibcon#wrote, iclass 24, count 0 2006.252.08:22:12.26#ibcon#about to read 3, iclass 24, count 0 2006.252.08:22:12.29#ibcon#read 3, iclass 24, count 0 2006.252.08:22:12.29#ibcon#about to read 4, iclass 24, count 0 2006.252.08:22:12.29#ibcon#read 4, iclass 24, count 0 2006.252.08:22:12.29#ibcon#about to read 5, iclass 24, count 0 2006.252.08:22:12.29#ibcon#read 5, iclass 24, count 0 2006.252.08:22:12.29#ibcon#about to read 6, iclass 24, count 0 2006.252.08:22:12.29#ibcon#read 6, iclass 24, count 0 2006.252.08:22:12.29#ibcon#end of sib2, iclass 24, count 0 2006.252.08:22:12.29#ibcon#*after write, iclass 24, count 0 2006.252.08:22:12.29#ibcon#*before return 0, iclass 24, count 0 2006.252.08:22:12.29#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.252.08:22:12.29#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.252.08:22:12.29#ibcon#about to clear, iclass 24 cls_cnt 0 2006.252.08:22:12.29#ibcon#cleared, iclass 24 cls_cnt 0 2006.252.08:22:12.29$vc4f8/vblo=6,752.99 2006.252.08:22:12.29#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.252.08:22:12.29#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.252.08:22:12.29#ibcon#ireg 17 cls_cnt 0 2006.252.08:22:12.29#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.252.08:22:12.29#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.252.08:22:12.29#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.252.08:22:12.29#ibcon#enter wrdev, iclass 26, count 0 2006.252.08:22:12.29#ibcon#first serial, iclass 26, count 0 2006.252.08:22:12.29#ibcon#enter sib2, iclass 26, count 0 2006.252.08:22:12.29#ibcon#flushed, iclass 26, count 0 2006.252.08:22:12.29#ibcon#about to write, iclass 26, count 0 2006.252.08:22:12.29#ibcon#wrote, iclass 26, count 0 2006.252.08:22:12.29#ibcon#about to read 3, iclass 26, count 0 2006.252.08:22:12.31#ibcon#read 3, iclass 26, count 0 2006.252.08:22:12.31#ibcon#about to read 4, iclass 26, count 0 2006.252.08:22:12.31#ibcon#read 4, iclass 26, count 0 2006.252.08:22:12.31#ibcon#about to read 5, iclass 26, count 0 2006.252.08:22:12.31#ibcon#read 5, iclass 26, count 0 2006.252.08:22:12.31#ibcon#about to read 6, iclass 26, count 0 2006.252.08:22:12.31#ibcon#read 6, iclass 26, count 0 2006.252.08:22:12.31#ibcon#end of sib2, iclass 26, count 0 2006.252.08:22:12.31#ibcon#*mode == 0, iclass 26, count 0 2006.252.08:22:12.31#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.252.08:22:12.31#ibcon#[28=FRQ=06,752.99\r\n] 2006.252.08:22:12.31#ibcon#*before write, iclass 26, count 0 2006.252.08:22:12.31#ibcon#enter sib2, iclass 26, count 0 2006.252.08:22:12.31#ibcon#flushed, iclass 26, count 0 2006.252.08:22:12.31#ibcon#about to write, iclass 26, count 0 2006.252.08:22:12.31#ibcon#wrote, iclass 26, count 0 2006.252.08:22:12.31#ibcon#about to read 3, iclass 26, count 0 2006.252.08:22:12.35#ibcon#read 3, iclass 26, count 0 2006.252.08:22:12.35#ibcon#about to read 4, iclass 26, count 0 2006.252.08:22:12.35#ibcon#read 4, iclass 26, count 0 2006.252.08:22:12.35#ibcon#about to read 5, iclass 26, count 0 2006.252.08:22:12.35#ibcon#read 5, iclass 26, count 0 2006.252.08:22:12.35#ibcon#about to read 6, iclass 26, count 0 2006.252.08:22:12.35#ibcon#read 6, iclass 26, count 0 2006.252.08:22:12.35#ibcon#end of sib2, iclass 26, count 0 2006.252.08:22:12.35#ibcon#*after write, iclass 26, count 0 2006.252.08:22:12.35#ibcon#*before return 0, iclass 26, count 0 2006.252.08:22:12.35#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.252.08:22:12.35#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.252.08:22:12.35#ibcon#about to clear, iclass 26 cls_cnt 0 2006.252.08:22:12.35#ibcon#cleared, iclass 26 cls_cnt 0 2006.252.08:22:12.35$vc4f8/vb=6,4 2006.252.08:22:12.35#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.252.08:22:12.35#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.252.08:22:12.35#ibcon#ireg 11 cls_cnt 2 2006.252.08:22:12.35#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.252.08:22:12.41#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.252.08:22:12.41#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.252.08:22:12.41#ibcon#enter wrdev, iclass 28, count 2 2006.252.08:22:12.41#ibcon#first serial, iclass 28, count 2 2006.252.08:22:12.41#ibcon#enter sib2, iclass 28, count 2 2006.252.08:22:12.41#ibcon#flushed, iclass 28, count 2 2006.252.08:22:12.41#ibcon#about to write, iclass 28, count 2 2006.252.08:22:12.41#ibcon#wrote, iclass 28, count 2 2006.252.08:22:12.41#ibcon#about to read 3, iclass 28, count 2 2006.252.08:22:12.43#ibcon#read 3, iclass 28, count 2 2006.252.08:22:12.43#ibcon#about to read 4, iclass 28, count 2 2006.252.08:22:12.43#ibcon#read 4, iclass 28, count 2 2006.252.08:22:12.43#ibcon#about to read 5, iclass 28, count 2 2006.252.08:22:12.43#ibcon#read 5, iclass 28, count 2 2006.252.08:22:12.43#ibcon#about to read 6, iclass 28, count 2 2006.252.08:22:12.43#ibcon#read 6, iclass 28, count 2 2006.252.08:22:12.43#ibcon#end of sib2, iclass 28, count 2 2006.252.08:22:12.43#ibcon#*mode == 0, iclass 28, count 2 2006.252.08:22:12.43#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.252.08:22:12.43#ibcon#[27=AT06-04\r\n] 2006.252.08:22:12.43#ibcon#*before write, iclass 28, count 2 2006.252.08:22:12.43#ibcon#enter sib2, iclass 28, count 2 2006.252.08:22:12.43#ibcon#flushed, iclass 28, count 2 2006.252.08:22:12.43#ibcon#about to write, iclass 28, count 2 2006.252.08:22:12.43#ibcon#wrote, iclass 28, count 2 2006.252.08:22:12.43#ibcon#about to read 3, iclass 28, count 2 2006.252.08:22:12.46#ibcon#read 3, iclass 28, count 2 2006.252.08:22:12.46#ibcon#about to read 4, iclass 28, count 2 2006.252.08:22:12.46#ibcon#read 4, iclass 28, count 2 2006.252.08:22:12.46#ibcon#about to read 5, iclass 28, count 2 2006.252.08:22:12.46#ibcon#read 5, iclass 28, count 2 2006.252.08:22:12.46#ibcon#about to read 6, iclass 28, count 2 2006.252.08:22:12.46#ibcon#read 6, iclass 28, count 2 2006.252.08:22:12.46#ibcon#end of sib2, iclass 28, count 2 2006.252.08:22:12.46#ibcon#*after write, iclass 28, count 2 2006.252.08:22:12.46#ibcon#*before return 0, iclass 28, count 2 2006.252.08:22:12.46#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.252.08:22:12.46#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.252.08:22:12.46#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.252.08:22:12.46#ibcon#ireg 7 cls_cnt 0 2006.252.08:22:12.46#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.252.08:22:12.58#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.252.08:22:12.58#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.252.08:22:12.58#ibcon#enter wrdev, iclass 28, count 0 2006.252.08:22:12.58#ibcon#first serial, iclass 28, count 0 2006.252.08:22:12.58#ibcon#enter sib2, iclass 28, count 0 2006.252.08:22:12.58#ibcon#flushed, iclass 28, count 0 2006.252.08:22:12.58#ibcon#about to write, iclass 28, count 0 2006.252.08:22:12.58#ibcon#wrote, iclass 28, count 0 2006.252.08:22:12.58#ibcon#about to read 3, iclass 28, count 0 2006.252.08:22:12.60#ibcon#read 3, iclass 28, count 0 2006.252.08:22:12.60#ibcon#about to read 4, iclass 28, count 0 2006.252.08:22:12.60#ibcon#read 4, iclass 28, count 0 2006.252.08:22:12.60#ibcon#about to read 5, iclass 28, count 0 2006.252.08:22:12.60#ibcon#read 5, iclass 28, count 0 2006.252.08:22:12.60#ibcon#about to read 6, iclass 28, count 0 2006.252.08:22:12.60#ibcon#read 6, iclass 28, count 0 2006.252.08:22:12.60#ibcon#end of sib2, iclass 28, count 0 2006.252.08:22:12.60#ibcon#*mode == 0, iclass 28, count 0 2006.252.08:22:12.60#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.252.08:22:12.60#ibcon#[27=USB\r\n] 2006.252.08:22:12.60#ibcon#*before write, iclass 28, count 0 2006.252.08:22:12.60#ibcon#enter sib2, iclass 28, count 0 2006.252.08:22:12.60#ibcon#flushed, iclass 28, count 0 2006.252.08:22:12.60#ibcon#about to write, iclass 28, count 0 2006.252.08:22:12.60#ibcon#wrote, iclass 28, count 0 2006.252.08:22:12.60#ibcon#about to read 3, iclass 28, count 0 2006.252.08:22:12.63#ibcon#read 3, iclass 28, count 0 2006.252.08:22:12.63#ibcon#about to read 4, iclass 28, count 0 2006.252.08:22:12.63#ibcon#read 4, iclass 28, count 0 2006.252.08:22:12.63#ibcon#about to read 5, iclass 28, count 0 2006.252.08:22:12.63#ibcon#read 5, iclass 28, count 0 2006.252.08:22:12.63#ibcon#about to read 6, iclass 28, count 0 2006.252.08:22:12.63#ibcon#read 6, iclass 28, count 0 2006.252.08:22:12.63#ibcon#end of sib2, iclass 28, count 0 2006.252.08:22:12.63#ibcon#*after write, iclass 28, count 0 2006.252.08:22:12.63#ibcon#*before return 0, iclass 28, count 0 2006.252.08:22:12.63#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.252.08:22:12.63#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.252.08:22:12.63#ibcon#about to clear, iclass 28 cls_cnt 0 2006.252.08:22:12.63#ibcon#cleared, iclass 28 cls_cnt 0 2006.252.08:22:12.63$vc4f8/vabw=wide 2006.252.08:22:12.63#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.252.08:22:12.63#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.252.08:22:12.63#ibcon#ireg 8 cls_cnt 0 2006.252.08:22:12.63#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.252.08:22:12.63#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.252.08:22:12.63#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.252.08:22:12.63#ibcon#enter wrdev, iclass 30, count 0 2006.252.08:22:12.63#ibcon#first serial, iclass 30, count 0 2006.252.08:22:12.63#ibcon#enter sib2, iclass 30, count 0 2006.252.08:22:12.63#ibcon#flushed, iclass 30, count 0 2006.252.08:22:12.63#ibcon#about to write, iclass 30, count 0 2006.252.08:22:12.63#ibcon#wrote, iclass 30, count 0 2006.252.08:22:12.63#ibcon#about to read 3, iclass 30, count 0 2006.252.08:22:12.65#ibcon#read 3, iclass 30, count 0 2006.252.08:22:12.65#ibcon#about to read 4, iclass 30, count 0 2006.252.08:22:12.65#ibcon#read 4, iclass 30, count 0 2006.252.08:22:12.65#ibcon#about to read 5, iclass 30, count 0 2006.252.08:22:12.65#ibcon#read 5, iclass 30, count 0 2006.252.08:22:12.65#ibcon#about to read 6, iclass 30, count 0 2006.252.08:22:12.65#ibcon#read 6, iclass 30, count 0 2006.252.08:22:12.65#ibcon#end of sib2, iclass 30, count 0 2006.252.08:22:12.65#ibcon#*mode == 0, iclass 30, count 0 2006.252.08:22:12.65#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.252.08:22:12.65#ibcon#[25=BW32\r\n] 2006.252.08:22:12.65#ibcon#*before write, iclass 30, count 0 2006.252.08:22:12.65#ibcon#enter sib2, iclass 30, count 0 2006.252.08:22:12.65#ibcon#flushed, iclass 30, count 0 2006.252.08:22:12.65#ibcon#about to write, iclass 30, count 0 2006.252.08:22:12.65#ibcon#wrote, iclass 30, count 0 2006.252.08:22:12.65#ibcon#about to read 3, iclass 30, count 0 2006.252.08:22:12.68#ibcon#read 3, iclass 30, count 0 2006.252.08:22:12.68#ibcon#about to read 4, iclass 30, count 0 2006.252.08:22:12.68#ibcon#read 4, iclass 30, count 0 2006.252.08:22:12.68#ibcon#about to read 5, iclass 30, count 0 2006.252.08:22:12.68#ibcon#read 5, iclass 30, count 0 2006.252.08:22:12.68#ibcon#about to read 6, iclass 30, count 0 2006.252.08:22:12.68#ibcon#read 6, iclass 30, count 0 2006.252.08:22:12.68#ibcon#end of sib2, iclass 30, count 0 2006.252.08:22:12.68#ibcon#*after write, iclass 30, count 0 2006.252.08:22:12.68#ibcon#*before return 0, iclass 30, count 0 2006.252.08:22:12.68#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.252.08:22:12.68#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.252.08:22:12.68#ibcon#about to clear, iclass 30 cls_cnt 0 2006.252.08:22:12.68#ibcon#cleared, iclass 30 cls_cnt 0 2006.252.08:22:12.68$vc4f8/vbbw=wide 2006.252.08:22:12.68#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.252.08:22:12.68#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.252.08:22:12.68#ibcon#ireg 8 cls_cnt 0 2006.252.08:22:12.68#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.252.08:22:12.75#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.252.08:22:12.75#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.252.08:22:12.75#ibcon#enter wrdev, iclass 32, count 0 2006.252.08:22:12.75#ibcon#first serial, iclass 32, count 0 2006.252.08:22:12.75#ibcon#enter sib2, iclass 32, count 0 2006.252.08:22:12.75#ibcon#flushed, iclass 32, count 0 2006.252.08:22:12.75#ibcon#about to write, iclass 32, count 0 2006.252.08:22:12.75#ibcon#wrote, iclass 32, count 0 2006.252.08:22:12.75#ibcon#about to read 3, iclass 32, count 0 2006.252.08:22:12.77#ibcon#read 3, iclass 32, count 0 2006.252.08:22:12.77#ibcon#about to read 4, iclass 32, count 0 2006.252.08:22:12.77#ibcon#read 4, iclass 32, count 0 2006.252.08:22:12.77#ibcon#about to read 5, iclass 32, count 0 2006.252.08:22:12.77#ibcon#read 5, iclass 32, count 0 2006.252.08:22:12.77#ibcon#about to read 6, iclass 32, count 0 2006.252.08:22:12.77#ibcon#read 6, iclass 32, count 0 2006.252.08:22:12.77#ibcon#end of sib2, iclass 32, count 0 2006.252.08:22:12.77#ibcon#*mode == 0, iclass 32, count 0 2006.252.08:22:12.77#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.252.08:22:12.77#ibcon#[27=BW32\r\n] 2006.252.08:22:12.77#ibcon#*before write, iclass 32, count 0 2006.252.08:22:12.77#ibcon#enter sib2, iclass 32, count 0 2006.252.08:22:12.77#ibcon#flushed, iclass 32, count 0 2006.252.08:22:12.77#ibcon#about to write, iclass 32, count 0 2006.252.08:22:12.77#ibcon#wrote, iclass 32, count 0 2006.252.08:22:12.77#ibcon#about to read 3, iclass 32, count 0 2006.252.08:22:12.80#ibcon#read 3, iclass 32, count 0 2006.252.08:22:12.80#ibcon#about to read 4, iclass 32, count 0 2006.252.08:22:12.80#ibcon#read 4, iclass 32, count 0 2006.252.08:22:12.80#ibcon#about to read 5, iclass 32, count 0 2006.252.08:22:12.80#ibcon#read 5, iclass 32, count 0 2006.252.08:22:12.80#ibcon#about to read 6, iclass 32, count 0 2006.252.08:22:12.80#ibcon#read 6, iclass 32, count 0 2006.252.08:22:12.80#ibcon#end of sib2, iclass 32, count 0 2006.252.08:22:12.80#ibcon#*after write, iclass 32, count 0 2006.252.08:22:12.80#ibcon#*before return 0, iclass 32, count 0 2006.252.08:22:12.80#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.252.08:22:12.80#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.252.08:22:12.80#ibcon#about to clear, iclass 32 cls_cnt 0 2006.252.08:22:12.80#ibcon#cleared, iclass 32 cls_cnt 0 2006.252.08:22:12.80$4f8m12a/ifd4f 2006.252.08:22:12.80$ifd4f/lo= 2006.252.08:22:12.80$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.252.08:22:12.80$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.252.08:22:12.80$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.252.08:22:12.80$ifd4f/patch= 2006.252.08:22:12.80$ifd4f/patch=lo1,a1,a2,a3,a4 2006.252.08:22:12.80$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.252.08:22:12.80$ifd4f/patch=lo3,a5,a6,a7,a8 2006.252.08:22:12.80$4f8m12a/"form=m,16.000,1:2 2006.252.08:22:12.80$4f8m12a/"tpicd 2006.252.08:22:12.80$4f8m12a/echo=off 2006.252.08:22:12.80$4f8m12a/xlog=off 2006.252.08:22:12.80:!2006.252.08:24:20 2006.252.08:22:34.14#trakl#Source acquired 2006.252.08:22:34.14#flagr#flagr/antenna,acquired 2006.252.08:24:20.00:preob 2006.252.08:24:20.14/onsource/TRACKING 2006.252.08:24:20.14:!2006.252.08:24:30 2006.252.08:24:30.00:data_valid=on 2006.252.08:24:30.00:midob 2006.252.08:24:31.14/onsource/TRACKING 2006.252.08:24:31.14/wx/27.23,1011.3,91 2006.252.08:24:31.31/cable/+6.4105E-03 2006.252.08:24:32.40/va/01,08,usb,yes,33,34 2006.252.08:24:32.40/va/02,07,usb,yes,32,34 2006.252.08:24:32.40/va/03,06,usb,yes,35,35 2006.252.08:24:32.40/va/04,07,usb,yes,33,36 2006.252.08:24:32.40/va/05,07,usb,yes,37,39 2006.252.08:24:32.40/va/06,07,usb,yes,32,32 2006.252.08:24:32.40/va/07,07,usb,yes,32,32 2006.252.08:24:32.40/va/08,07,usb,yes,35,34 2006.252.08:24:32.63/valo/01,532.99,yes,locked 2006.252.08:24:32.63/valo/02,572.99,yes,locked 2006.252.08:24:32.63/valo/03,672.99,yes,locked 2006.252.08:24:32.63/valo/04,832.99,yes,locked 2006.252.08:24:32.63/valo/05,652.99,yes,locked 2006.252.08:24:32.63/valo/06,772.99,yes,locked 2006.252.08:24:32.63/valo/07,832.99,yes,locked 2006.252.08:24:32.63/valo/08,852.99,yes,locked 2006.252.08:24:33.72/vb/01,04,usb,yes,30,29 2006.252.08:24:33.72/vb/02,05,usb,yes,28,29 2006.252.08:24:33.72/vb/03,04,usb,yes,28,32 2006.252.08:24:33.72/vb/04,04,usb,yes,29,29 2006.252.08:24:33.72/vb/05,04,usb,yes,27,32 2006.252.08:24:33.72/vb/06,04,usb,yes,28,31 2006.252.08:24:33.72/vb/07,04,usb,yes,31,31 2006.252.08:24:33.72/vb/08,04,usb,yes,28,32 2006.252.08:24:33.95/vblo/01,632.99,yes,locked 2006.252.08:24:33.95/vblo/02,640.99,yes,locked 2006.252.08:24:33.95/vblo/03,656.99,yes,locked 2006.252.08:24:33.95/vblo/04,712.99,yes,locked 2006.252.08:24:33.95/vblo/05,744.99,yes,locked 2006.252.08:24:33.95/vblo/06,752.99,yes,locked 2006.252.08:24:33.95/vblo/07,734.99,yes,locked 2006.252.08:24:33.95/vblo/08,744.99,yes,locked 2006.252.08:24:34.10/vabw/8 2006.252.08:24:34.25/vbbw/8 2006.252.08:24:34.36/xfe/off,on,14.2 2006.252.08:24:34.73/ifatt/23,28,28,28 2006.252.08:24:35.07/fmout-gps/S +4.75E-07 2006.252.08:24:35.11:!2006.252.08:25:30 2006.252.08:25:30.00:data_valid=off 2006.252.08:25:30.01:postob 2006.252.08:25:30.20/cable/+6.4096E-03 2006.252.08:25:30.21/wx/27.22,1011.3,91 2006.252.08:25:31.07/fmout-gps/S +4.75E-07 2006.252.08:25:31.08:scan_name=252-0826,k06252,60 2006.252.08:25:31.08:source=0059+581,010245.76,582411.1,2000.0,cw 2006.252.08:25:31.14#flagr#flagr/antenna,new-source 2006.252.08:25:32.14:checkk5 2006.252.08:25:32.52/chk_autoobs//k5ts1/ autoobs is running! 2006.252.08:25:32.89/chk_autoobs//k5ts2/ autoobs is running! 2006.252.08:25:33.27/chk_autoobs//k5ts3/ autoobs is running! 2006.252.08:25:33.64/chk_autoobs//k5ts4/ autoobs is running! 2006.252.08:25:34.01/chk_obsdata//k5ts1/T2520824??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.252.08:25:34.38/chk_obsdata//k5ts2/T2520824??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.252.08:25:34.76/chk_obsdata//k5ts3/T2520824??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.252.08:25:35.13/chk_obsdata//k5ts4/T2520824??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.252.08:25:35.83/k5log//k5ts1_log_newline 2006.252.08:25:36.52/k5log//k5ts2_log_newline 2006.252.08:25:37.21/k5log//k5ts3_log_newline 2006.252.08:25:37.89/k5log//k5ts4_log_newline 2006.252.08:25:37.92/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.252.08:25:37.92:4f8m12a=3 2006.252.08:25:37.92$4f8m12a/echo=on 2006.252.08:25:37.92$4f8m12a/pcalon 2006.252.08:25:37.92$pcalon/"no phase cal control is implemented here 2006.252.08:25:37.92$4f8m12a/"tpicd=stop 2006.252.08:25:37.92$4f8m12a/vc4f8 2006.252.08:25:37.92$vc4f8/valo=1,532.99 2006.252.08:25:37.92#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.252.08:25:37.92#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.252.08:25:37.92#ibcon#ireg 17 cls_cnt 0 2006.252.08:25:37.92#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.252.08:25:37.92#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.252.08:25:37.92#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.252.08:25:37.92#ibcon#enter wrdev, iclass 5, count 0 2006.252.08:25:37.92#ibcon#first serial, iclass 5, count 0 2006.252.08:25:37.92#ibcon#enter sib2, iclass 5, count 0 2006.252.08:25:37.92#ibcon#flushed, iclass 5, count 0 2006.252.08:25:37.92#ibcon#about to write, iclass 5, count 0 2006.252.08:25:37.92#ibcon#wrote, iclass 5, count 0 2006.252.08:25:37.92#ibcon#about to read 3, iclass 5, count 0 2006.252.08:25:37.97#ibcon#read 3, iclass 5, count 0 2006.252.08:25:37.97#ibcon#about to read 4, iclass 5, count 0 2006.252.08:25:37.97#ibcon#read 4, iclass 5, count 0 2006.252.08:25:37.97#ibcon#about to read 5, iclass 5, count 0 2006.252.08:25:37.97#ibcon#read 5, iclass 5, count 0 2006.252.08:25:37.97#ibcon#about to read 6, iclass 5, count 0 2006.252.08:25:37.97#ibcon#read 6, iclass 5, count 0 2006.252.08:25:37.97#ibcon#end of sib2, iclass 5, count 0 2006.252.08:25:37.97#ibcon#*mode == 0, iclass 5, count 0 2006.252.08:25:37.97#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.252.08:25:37.97#ibcon#[26=FRQ=01,532.99\r\n] 2006.252.08:25:37.97#ibcon#*before write, iclass 5, count 0 2006.252.08:25:37.97#ibcon#enter sib2, iclass 5, count 0 2006.252.08:25:37.97#ibcon#flushed, iclass 5, count 0 2006.252.08:25:37.97#ibcon#about to write, iclass 5, count 0 2006.252.08:25:37.97#ibcon#wrote, iclass 5, count 0 2006.252.08:25:37.97#ibcon#about to read 3, iclass 5, count 0 2006.252.08:25:38.01#ibcon#read 3, iclass 5, count 0 2006.252.08:25:38.01#ibcon#about to read 4, iclass 5, count 0 2006.252.08:25:38.01#ibcon#read 4, iclass 5, count 0 2006.252.08:25:38.01#ibcon#about to read 5, iclass 5, count 0 2006.252.08:25:38.01#ibcon#read 5, iclass 5, count 0 2006.252.08:25:38.01#ibcon#about to read 6, iclass 5, count 0 2006.252.08:25:38.01#ibcon#read 6, iclass 5, count 0 2006.252.08:25:38.01#ibcon#end of sib2, iclass 5, count 0 2006.252.08:25:38.01#ibcon#*after write, iclass 5, count 0 2006.252.08:25:38.01#ibcon#*before return 0, iclass 5, count 0 2006.252.08:25:38.01#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.252.08:25:38.01#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.252.08:25:38.01#ibcon#about to clear, iclass 5 cls_cnt 0 2006.252.08:25:38.01#ibcon#cleared, iclass 5 cls_cnt 0 2006.252.08:25:38.01$vc4f8/va=1,8 2006.252.08:25:38.01#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.252.08:25:38.01#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.252.08:25:38.01#ibcon#ireg 11 cls_cnt 2 2006.252.08:25:38.01#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.252.08:25:38.01#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.252.08:25:38.01#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.252.08:25:38.01#ibcon#enter wrdev, iclass 7, count 2 2006.252.08:25:38.01#ibcon#first serial, iclass 7, count 2 2006.252.08:25:38.01#ibcon#enter sib2, iclass 7, count 2 2006.252.08:25:38.01#ibcon#flushed, iclass 7, count 2 2006.252.08:25:38.01#ibcon#about to write, iclass 7, count 2 2006.252.08:25:38.01#ibcon#wrote, iclass 7, count 2 2006.252.08:25:38.01#ibcon#about to read 3, iclass 7, count 2 2006.252.08:25:38.04#ibcon#read 3, iclass 7, count 2 2006.252.08:25:38.04#ibcon#about to read 4, iclass 7, count 2 2006.252.08:25:38.04#ibcon#read 4, iclass 7, count 2 2006.252.08:25:38.04#ibcon#about to read 5, iclass 7, count 2 2006.252.08:25:38.04#ibcon#read 5, iclass 7, count 2 2006.252.08:25:38.04#ibcon#about to read 6, iclass 7, count 2 2006.252.08:25:38.04#ibcon#read 6, iclass 7, count 2 2006.252.08:25:38.04#ibcon#end of sib2, iclass 7, count 2 2006.252.08:25:38.04#ibcon#*mode == 0, iclass 7, count 2 2006.252.08:25:38.04#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.252.08:25:38.04#ibcon#[25=AT01-08\r\n] 2006.252.08:25:38.04#ibcon#*before write, iclass 7, count 2 2006.252.08:25:38.04#ibcon#enter sib2, iclass 7, count 2 2006.252.08:25:38.04#ibcon#flushed, iclass 7, count 2 2006.252.08:25:38.04#ibcon#about to write, iclass 7, count 2 2006.252.08:25:38.04#ibcon#wrote, iclass 7, count 2 2006.252.08:25:38.04#ibcon#about to read 3, iclass 7, count 2 2006.252.08:25:38.07#ibcon#read 3, iclass 7, count 2 2006.252.08:25:38.07#ibcon#about to read 4, iclass 7, count 2 2006.252.08:25:38.07#ibcon#read 4, iclass 7, count 2 2006.252.08:25:38.07#ibcon#about to read 5, iclass 7, count 2 2006.252.08:25:38.07#ibcon#read 5, iclass 7, count 2 2006.252.08:25:38.07#ibcon#about to read 6, iclass 7, count 2 2006.252.08:25:38.07#ibcon#read 6, iclass 7, count 2 2006.252.08:25:38.07#ibcon#end of sib2, iclass 7, count 2 2006.252.08:25:38.07#ibcon#*after write, iclass 7, count 2 2006.252.08:25:38.07#ibcon#*before return 0, iclass 7, count 2 2006.252.08:25:38.07#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.252.08:25:38.07#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.252.08:25:38.07#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.252.08:25:38.07#ibcon#ireg 7 cls_cnt 0 2006.252.08:25:38.07#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.252.08:25:38.19#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.252.08:25:38.19#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.252.08:25:38.19#ibcon#enter wrdev, iclass 7, count 0 2006.252.08:25:38.19#ibcon#first serial, iclass 7, count 0 2006.252.08:25:38.19#ibcon#enter sib2, iclass 7, count 0 2006.252.08:25:38.19#ibcon#flushed, iclass 7, count 0 2006.252.08:25:38.19#ibcon#about to write, iclass 7, count 0 2006.252.08:25:38.19#ibcon#wrote, iclass 7, count 0 2006.252.08:25:38.19#ibcon#about to read 3, iclass 7, count 0 2006.252.08:25:38.21#ibcon#read 3, iclass 7, count 0 2006.252.08:25:38.21#ibcon#about to read 4, iclass 7, count 0 2006.252.08:25:38.21#ibcon#read 4, iclass 7, count 0 2006.252.08:25:38.21#ibcon#about to read 5, iclass 7, count 0 2006.252.08:25:38.21#ibcon#read 5, iclass 7, count 0 2006.252.08:25:38.21#ibcon#about to read 6, iclass 7, count 0 2006.252.08:25:38.21#ibcon#read 6, iclass 7, count 0 2006.252.08:25:38.21#ibcon#end of sib2, iclass 7, count 0 2006.252.08:25:38.21#ibcon#*mode == 0, iclass 7, count 0 2006.252.08:25:38.21#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.252.08:25:38.21#ibcon#[25=USB\r\n] 2006.252.08:25:38.21#ibcon#*before write, iclass 7, count 0 2006.252.08:25:38.21#ibcon#enter sib2, iclass 7, count 0 2006.252.08:25:38.21#ibcon#flushed, iclass 7, count 0 2006.252.08:25:38.21#ibcon#about to write, iclass 7, count 0 2006.252.08:25:38.21#ibcon#wrote, iclass 7, count 0 2006.252.08:25:38.21#ibcon#about to read 3, iclass 7, count 0 2006.252.08:25:38.24#ibcon#read 3, iclass 7, count 0 2006.252.08:25:38.24#ibcon#about to read 4, iclass 7, count 0 2006.252.08:25:38.24#ibcon#read 4, iclass 7, count 0 2006.252.08:25:38.24#ibcon#about to read 5, iclass 7, count 0 2006.252.08:25:38.24#ibcon#read 5, iclass 7, count 0 2006.252.08:25:38.24#ibcon#about to read 6, iclass 7, count 0 2006.252.08:25:38.24#ibcon#read 6, iclass 7, count 0 2006.252.08:25:38.24#ibcon#end of sib2, iclass 7, count 0 2006.252.08:25:38.24#ibcon#*after write, iclass 7, count 0 2006.252.08:25:38.24#ibcon#*before return 0, iclass 7, count 0 2006.252.08:25:38.24#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.252.08:25:38.24#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.252.08:25:38.24#ibcon#about to clear, iclass 7 cls_cnt 0 2006.252.08:25:38.24#ibcon#cleared, iclass 7 cls_cnt 0 2006.252.08:25:38.24$vc4f8/valo=2,572.99 2006.252.08:25:38.24#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.252.08:25:38.24#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.252.08:25:38.24#ibcon#ireg 17 cls_cnt 0 2006.252.08:25:38.24#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.252.08:25:38.24#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.252.08:25:38.24#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.252.08:25:38.24#ibcon#enter wrdev, iclass 11, count 0 2006.252.08:25:38.24#ibcon#first serial, iclass 11, count 0 2006.252.08:25:38.24#ibcon#enter sib2, iclass 11, count 0 2006.252.08:25:38.24#ibcon#flushed, iclass 11, count 0 2006.252.08:25:38.24#ibcon#about to write, iclass 11, count 0 2006.252.08:25:38.24#ibcon#wrote, iclass 11, count 0 2006.252.08:25:38.24#ibcon#about to read 3, iclass 11, count 0 2006.252.08:25:38.26#ibcon#read 3, iclass 11, count 0 2006.252.08:25:38.26#ibcon#about to read 4, iclass 11, count 0 2006.252.08:25:38.26#ibcon#read 4, iclass 11, count 0 2006.252.08:25:38.26#ibcon#about to read 5, iclass 11, count 0 2006.252.08:25:38.26#ibcon#read 5, iclass 11, count 0 2006.252.08:25:38.26#ibcon#about to read 6, iclass 11, count 0 2006.252.08:25:38.26#ibcon#read 6, iclass 11, count 0 2006.252.08:25:38.26#ibcon#end of sib2, iclass 11, count 0 2006.252.08:25:38.26#ibcon#*mode == 0, iclass 11, count 0 2006.252.08:25:38.26#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.252.08:25:38.26#ibcon#[26=FRQ=02,572.99\r\n] 2006.252.08:25:38.26#ibcon#*before write, iclass 11, count 0 2006.252.08:25:38.26#ibcon#enter sib2, iclass 11, count 0 2006.252.08:25:38.26#ibcon#flushed, iclass 11, count 0 2006.252.08:25:38.26#ibcon#about to write, iclass 11, count 0 2006.252.08:25:38.26#ibcon#wrote, iclass 11, count 0 2006.252.08:25:38.26#ibcon#about to read 3, iclass 11, count 0 2006.252.08:25:38.30#ibcon#read 3, iclass 11, count 0 2006.252.08:25:38.30#ibcon#about to read 4, iclass 11, count 0 2006.252.08:25:38.30#ibcon#read 4, iclass 11, count 0 2006.252.08:25:38.30#ibcon#about to read 5, iclass 11, count 0 2006.252.08:25:38.30#ibcon#read 5, iclass 11, count 0 2006.252.08:25:38.30#ibcon#about to read 6, iclass 11, count 0 2006.252.08:25:38.30#ibcon#read 6, iclass 11, count 0 2006.252.08:25:38.30#ibcon#end of sib2, iclass 11, count 0 2006.252.08:25:38.30#ibcon#*after write, iclass 11, count 0 2006.252.08:25:38.30#ibcon#*before return 0, iclass 11, count 0 2006.252.08:25:38.30#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.252.08:25:38.30#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.252.08:25:38.30#ibcon#about to clear, iclass 11 cls_cnt 0 2006.252.08:25:38.30#ibcon#cleared, iclass 11 cls_cnt 0 2006.252.08:25:38.30$vc4f8/va=2,7 2006.252.08:25:38.30#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.252.08:25:38.30#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.252.08:25:38.30#ibcon#ireg 11 cls_cnt 2 2006.252.08:25:38.30#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.252.08:25:38.36#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.252.08:25:38.36#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.252.08:25:38.36#ibcon#enter wrdev, iclass 13, count 2 2006.252.08:25:38.36#ibcon#first serial, iclass 13, count 2 2006.252.08:25:38.36#ibcon#enter sib2, iclass 13, count 2 2006.252.08:25:38.36#ibcon#flushed, iclass 13, count 2 2006.252.08:25:38.36#ibcon#about to write, iclass 13, count 2 2006.252.08:25:38.36#ibcon#wrote, iclass 13, count 2 2006.252.08:25:38.36#ibcon#about to read 3, iclass 13, count 2 2006.252.08:25:38.38#ibcon#read 3, iclass 13, count 2 2006.252.08:25:38.38#ibcon#about to read 4, iclass 13, count 2 2006.252.08:25:38.38#ibcon#read 4, iclass 13, count 2 2006.252.08:25:38.38#ibcon#about to read 5, iclass 13, count 2 2006.252.08:25:38.38#ibcon#read 5, iclass 13, count 2 2006.252.08:25:38.38#ibcon#about to read 6, iclass 13, count 2 2006.252.08:25:38.38#ibcon#read 6, iclass 13, count 2 2006.252.08:25:38.38#ibcon#end of sib2, iclass 13, count 2 2006.252.08:25:38.38#ibcon#*mode == 0, iclass 13, count 2 2006.252.08:25:38.38#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.252.08:25:38.38#ibcon#[25=AT02-07\r\n] 2006.252.08:25:38.38#ibcon#*before write, iclass 13, count 2 2006.252.08:25:38.38#ibcon#enter sib2, iclass 13, count 2 2006.252.08:25:38.38#ibcon#flushed, iclass 13, count 2 2006.252.08:25:38.38#ibcon#about to write, iclass 13, count 2 2006.252.08:25:38.38#ibcon#wrote, iclass 13, count 2 2006.252.08:25:38.38#ibcon#about to read 3, iclass 13, count 2 2006.252.08:25:38.41#ibcon#read 3, iclass 13, count 2 2006.252.08:25:38.41#ibcon#about to read 4, iclass 13, count 2 2006.252.08:25:38.41#ibcon#read 4, iclass 13, count 2 2006.252.08:25:38.41#ibcon#about to read 5, iclass 13, count 2 2006.252.08:25:38.41#ibcon#read 5, iclass 13, count 2 2006.252.08:25:38.41#ibcon#about to read 6, iclass 13, count 2 2006.252.08:25:38.41#ibcon#read 6, iclass 13, count 2 2006.252.08:25:38.41#ibcon#end of sib2, iclass 13, count 2 2006.252.08:25:38.41#ibcon#*after write, iclass 13, count 2 2006.252.08:25:38.41#ibcon#*before return 0, iclass 13, count 2 2006.252.08:25:38.41#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.252.08:25:38.41#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.252.08:25:38.41#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.252.08:25:38.41#ibcon#ireg 7 cls_cnt 0 2006.252.08:25:38.41#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.252.08:25:38.53#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.252.08:25:38.53#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.252.08:25:38.53#ibcon#enter wrdev, iclass 13, count 0 2006.252.08:25:38.54#ibcon#first serial, iclass 13, count 0 2006.252.08:25:38.54#ibcon#enter sib2, iclass 13, count 0 2006.252.08:25:38.54#ibcon#flushed, iclass 13, count 0 2006.252.08:25:38.54#ibcon#about to write, iclass 13, count 0 2006.252.08:25:38.54#ibcon#wrote, iclass 13, count 0 2006.252.08:25:38.54#ibcon#about to read 3, iclass 13, count 0 2006.252.08:25:38.55#ibcon#read 3, iclass 13, count 0 2006.252.08:25:38.55#ibcon#about to read 4, iclass 13, count 0 2006.252.08:25:38.55#ibcon#read 4, iclass 13, count 0 2006.252.08:25:38.55#ibcon#about to read 5, iclass 13, count 0 2006.252.08:25:38.55#ibcon#read 5, iclass 13, count 0 2006.252.08:25:38.55#ibcon#about to read 6, iclass 13, count 0 2006.252.08:25:38.55#ibcon#read 6, iclass 13, count 0 2006.252.08:25:38.55#ibcon#end of sib2, iclass 13, count 0 2006.252.08:25:38.55#ibcon#*mode == 0, iclass 13, count 0 2006.252.08:25:38.55#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.252.08:25:38.55#ibcon#[25=USB\r\n] 2006.252.08:25:38.55#ibcon#*before write, iclass 13, count 0 2006.252.08:25:38.55#ibcon#enter sib2, iclass 13, count 0 2006.252.08:25:38.55#ibcon#flushed, iclass 13, count 0 2006.252.08:25:38.55#ibcon#about to write, iclass 13, count 0 2006.252.08:25:38.55#ibcon#wrote, iclass 13, count 0 2006.252.08:25:38.55#ibcon#about to read 3, iclass 13, count 0 2006.252.08:25:38.58#ibcon#read 3, iclass 13, count 0 2006.252.08:25:38.58#ibcon#about to read 4, iclass 13, count 0 2006.252.08:25:38.58#ibcon#read 4, iclass 13, count 0 2006.252.08:25:38.58#ibcon#about to read 5, iclass 13, count 0 2006.252.08:25:38.58#ibcon#read 5, iclass 13, count 0 2006.252.08:25:38.58#ibcon#about to read 6, iclass 13, count 0 2006.252.08:25:38.58#ibcon#read 6, iclass 13, count 0 2006.252.08:25:38.58#ibcon#end of sib2, iclass 13, count 0 2006.252.08:25:38.58#ibcon#*after write, iclass 13, count 0 2006.252.08:25:38.58#ibcon#*before return 0, iclass 13, count 0 2006.252.08:25:38.58#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.252.08:25:38.58#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.252.08:25:38.58#ibcon#about to clear, iclass 13 cls_cnt 0 2006.252.08:25:38.58#ibcon#cleared, iclass 13 cls_cnt 0 2006.252.08:25:38.58$vc4f8/valo=3,672.99 2006.252.08:25:38.58#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.252.08:25:38.58#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.252.08:25:38.58#ibcon#ireg 17 cls_cnt 0 2006.252.08:25:38.58#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.252.08:25:38.58#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.252.08:25:38.58#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.252.08:25:38.58#ibcon#enter wrdev, iclass 15, count 0 2006.252.08:25:38.58#ibcon#first serial, iclass 15, count 0 2006.252.08:25:38.58#ibcon#enter sib2, iclass 15, count 0 2006.252.08:25:38.58#ibcon#flushed, iclass 15, count 0 2006.252.08:25:38.58#ibcon#about to write, iclass 15, count 0 2006.252.08:25:38.58#ibcon#wrote, iclass 15, count 0 2006.252.08:25:38.58#ibcon#about to read 3, iclass 15, count 0 2006.252.08:25:38.61#ibcon#read 3, iclass 15, count 0 2006.252.08:25:38.61#ibcon#about to read 4, iclass 15, count 0 2006.252.08:25:38.61#ibcon#read 4, iclass 15, count 0 2006.252.08:25:38.61#ibcon#about to read 5, iclass 15, count 0 2006.252.08:25:38.61#ibcon#read 5, iclass 15, count 0 2006.252.08:25:38.61#ibcon#about to read 6, iclass 15, count 0 2006.252.08:25:38.61#ibcon#read 6, iclass 15, count 0 2006.252.08:25:38.61#ibcon#end of sib2, iclass 15, count 0 2006.252.08:25:38.61#ibcon#*mode == 0, iclass 15, count 0 2006.252.08:25:38.61#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.252.08:25:38.61#ibcon#[26=FRQ=03,672.99\r\n] 2006.252.08:25:38.61#ibcon#*before write, iclass 15, count 0 2006.252.08:25:38.61#ibcon#enter sib2, iclass 15, count 0 2006.252.08:25:38.61#ibcon#flushed, iclass 15, count 0 2006.252.08:25:38.61#ibcon#about to write, iclass 15, count 0 2006.252.08:25:38.61#ibcon#wrote, iclass 15, count 0 2006.252.08:25:38.61#ibcon#about to read 3, iclass 15, count 0 2006.252.08:25:38.65#ibcon#read 3, iclass 15, count 0 2006.252.08:25:38.65#ibcon#about to read 4, iclass 15, count 0 2006.252.08:25:38.65#ibcon#read 4, iclass 15, count 0 2006.252.08:25:38.65#ibcon#about to read 5, iclass 15, count 0 2006.252.08:25:38.65#ibcon#read 5, iclass 15, count 0 2006.252.08:25:38.65#ibcon#about to read 6, iclass 15, count 0 2006.252.08:25:38.65#ibcon#read 6, iclass 15, count 0 2006.252.08:25:38.65#ibcon#end of sib2, iclass 15, count 0 2006.252.08:25:38.65#ibcon#*after write, iclass 15, count 0 2006.252.08:25:38.65#ibcon#*before return 0, iclass 15, count 0 2006.252.08:25:38.65#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.252.08:25:38.65#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.252.08:25:38.65#ibcon#about to clear, iclass 15 cls_cnt 0 2006.252.08:25:38.65#ibcon#cleared, iclass 15 cls_cnt 0 2006.252.08:25:38.65$vc4f8/va=3,6 2006.252.08:25:38.65#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.252.08:25:38.65#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.252.08:25:38.65#ibcon#ireg 11 cls_cnt 2 2006.252.08:25:38.65#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.252.08:25:38.70#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.252.08:25:38.70#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.252.08:25:38.70#ibcon#enter wrdev, iclass 17, count 2 2006.252.08:25:38.70#ibcon#first serial, iclass 17, count 2 2006.252.08:25:38.70#ibcon#enter sib2, iclass 17, count 2 2006.252.08:25:38.70#ibcon#flushed, iclass 17, count 2 2006.252.08:25:38.70#ibcon#about to write, iclass 17, count 2 2006.252.08:25:38.70#ibcon#wrote, iclass 17, count 2 2006.252.08:25:38.70#ibcon#about to read 3, iclass 17, count 2 2006.252.08:25:38.72#ibcon#read 3, iclass 17, count 2 2006.252.08:25:38.72#ibcon#about to read 4, iclass 17, count 2 2006.252.08:25:38.72#ibcon#read 4, iclass 17, count 2 2006.252.08:25:38.72#ibcon#about to read 5, iclass 17, count 2 2006.252.08:25:38.72#ibcon#read 5, iclass 17, count 2 2006.252.08:25:38.72#ibcon#about to read 6, iclass 17, count 2 2006.252.08:25:38.72#ibcon#read 6, iclass 17, count 2 2006.252.08:25:38.72#ibcon#end of sib2, iclass 17, count 2 2006.252.08:25:38.72#ibcon#*mode == 0, iclass 17, count 2 2006.252.08:25:38.72#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.252.08:25:38.72#ibcon#[25=AT03-06\r\n] 2006.252.08:25:38.72#ibcon#*before write, iclass 17, count 2 2006.252.08:25:38.72#ibcon#enter sib2, iclass 17, count 2 2006.252.08:25:38.72#ibcon#flushed, iclass 17, count 2 2006.252.08:25:38.72#ibcon#about to write, iclass 17, count 2 2006.252.08:25:38.72#ibcon#wrote, iclass 17, count 2 2006.252.08:25:38.72#ibcon#about to read 3, iclass 17, count 2 2006.252.08:25:38.75#ibcon#read 3, iclass 17, count 2 2006.252.08:25:38.75#ibcon#about to read 4, iclass 17, count 2 2006.252.08:25:38.75#ibcon#read 4, iclass 17, count 2 2006.252.08:25:38.75#ibcon#about to read 5, iclass 17, count 2 2006.252.08:25:38.75#ibcon#read 5, iclass 17, count 2 2006.252.08:25:38.75#ibcon#about to read 6, iclass 17, count 2 2006.252.08:25:38.75#ibcon#read 6, iclass 17, count 2 2006.252.08:25:38.75#ibcon#end of sib2, iclass 17, count 2 2006.252.08:25:38.75#ibcon#*after write, iclass 17, count 2 2006.252.08:25:38.75#ibcon#*before return 0, iclass 17, count 2 2006.252.08:25:38.75#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.252.08:25:38.75#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.252.08:25:38.75#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.252.08:25:38.75#ibcon#ireg 7 cls_cnt 0 2006.252.08:25:38.75#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.252.08:25:38.87#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.252.08:25:38.87#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.252.08:25:38.87#ibcon#enter wrdev, iclass 17, count 0 2006.252.08:25:38.87#ibcon#first serial, iclass 17, count 0 2006.252.08:25:38.87#ibcon#enter sib2, iclass 17, count 0 2006.252.08:25:38.87#ibcon#flushed, iclass 17, count 0 2006.252.08:25:38.87#ibcon#about to write, iclass 17, count 0 2006.252.08:25:38.87#ibcon#wrote, iclass 17, count 0 2006.252.08:25:38.87#ibcon#about to read 3, iclass 17, count 0 2006.252.08:25:38.89#ibcon#read 3, iclass 17, count 0 2006.252.08:25:38.89#ibcon#about to read 4, iclass 17, count 0 2006.252.08:25:38.89#ibcon#read 4, iclass 17, count 0 2006.252.08:25:38.89#ibcon#about to read 5, iclass 17, count 0 2006.252.08:25:38.89#ibcon#read 5, iclass 17, count 0 2006.252.08:25:38.89#ibcon#about to read 6, iclass 17, count 0 2006.252.08:25:38.89#ibcon#read 6, iclass 17, count 0 2006.252.08:25:38.89#ibcon#end of sib2, iclass 17, count 0 2006.252.08:25:38.89#ibcon#*mode == 0, iclass 17, count 0 2006.252.08:25:38.89#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.252.08:25:38.89#ibcon#[25=USB\r\n] 2006.252.08:25:38.89#ibcon#*before write, iclass 17, count 0 2006.252.08:25:38.89#ibcon#enter sib2, iclass 17, count 0 2006.252.08:25:38.89#ibcon#flushed, iclass 17, count 0 2006.252.08:25:38.89#ibcon#about to write, iclass 17, count 0 2006.252.08:25:38.89#ibcon#wrote, iclass 17, count 0 2006.252.08:25:38.89#ibcon#about to read 3, iclass 17, count 0 2006.252.08:25:38.92#ibcon#read 3, iclass 17, count 0 2006.252.08:25:38.92#ibcon#about to read 4, iclass 17, count 0 2006.252.08:25:38.92#ibcon#read 4, iclass 17, count 0 2006.252.08:25:38.92#ibcon#about to read 5, iclass 17, count 0 2006.252.08:25:38.92#ibcon#read 5, iclass 17, count 0 2006.252.08:25:38.92#ibcon#about to read 6, iclass 17, count 0 2006.252.08:25:38.92#ibcon#read 6, iclass 17, count 0 2006.252.08:25:38.92#ibcon#end of sib2, iclass 17, count 0 2006.252.08:25:38.92#ibcon#*after write, iclass 17, count 0 2006.252.08:25:38.92#ibcon#*before return 0, iclass 17, count 0 2006.252.08:25:38.92#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.252.08:25:38.92#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.252.08:25:38.92#ibcon#about to clear, iclass 17 cls_cnt 0 2006.252.08:25:38.92#ibcon#cleared, iclass 17 cls_cnt 0 2006.252.08:25:38.92$vc4f8/valo=4,832.99 2006.252.08:25:38.92#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.252.08:25:38.92#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.252.08:25:38.92#ibcon#ireg 17 cls_cnt 0 2006.252.08:25:38.92#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.252.08:25:38.92#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.252.08:25:38.92#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.252.08:25:38.92#ibcon#enter wrdev, iclass 19, count 0 2006.252.08:25:38.92#ibcon#first serial, iclass 19, count 0 2006.252.08:25:38.92#ibcon#enter sib2, iclass 19, count 0 2006.252.08:25:38.92#ibcon#flushed, iclass 19, count 0 2006.252.08:25:38.92#ibcon#about to write, iclass 19, count 0 2006.252.08:25:38.92#ibcon#wrote, iclass 19, count 0 2006.252.08:25:38.92#ibcon#about to read 3, iclass 19, count 0 2006.252.08:25:38.94#ibcon#read 3, iclass 19, count 0 2006.252.08:25:38.94#ibcon#about to read 4, iclass 19, count 0 2006.252.08:25:38.94#ibcon#read 4, iclass 19, count 0 2006.252.08:25:38.94#ibcon#about to read 5, iclass 19, count 0 2006.252.08:25:38.94#ibcon#read 5, iclass 19, count 0 2006.252.08:25:38.94#ibcon#about to read 6, iclass 19, count 0 2006.252.08:25:38.94#ibcon#read 6, iclass 19, count 0 2006.252.08:25:38.94#ibcon#end of sib2, iclass 19, count 0 2006.252.08:25:38.94#ibcon#*mode == 0, iclass 19, count 0 2006.252.08:25:38.94#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.252.08:25:38.94#ibcon#[26=FRQ=04,832.99\r\n] 2006.252.08:25:38.94#ibcon#*before write, iclass 19, count 0 2006.252.08:25:38.94#ibcon#enter sib2, iclass 19, count 0 2006.252.08:25:38.94#ibcon#flushed, iclass 19, count 0 2006.252.08:25:38.94#ibcon#about to write, iclass 19, count 0 2006.252.08:25:38.94#ibcon#wrote, iclass 19, count 0 2006.252.08:25:38.94#ibcon#about to read 3, iclass 19, count 0 2006.252.08:25:38.98#ibcon#read 3, iclass 19, count 0 2006.252.08:25:38.98#ibcon#about to read 4, iclass 19, count 0 2006.252.08:25:38.98#ibcon#read 4, iclass 19, count 0 2006.252.08:25:38.98#ibcon#about to read 5, iclass 19, count 0 2006.252.08:25:38.98#ibcon#read 5, iclass 19, count 0 2006.252.08:25:38.98#ibcon#about to read 6, iclass 19, count 0 2006.252.08:25:38.98#ibcon#read 6, iclass 19, count 0 2006.252.08:25:38.98#ibcon#end of sib2, iclass 19, count 0 2006.252.08:25:38.98#ibcon#*after write, iclass 19, count 0 2006.252.08:25:38.98#ibcon#*before return 0, iclass 19, count 0 2006.252.08:25:38.98#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.252.08:25:38.98#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.252.08:25:38.98#ibcon#about to clear, iclass 19 cls_cnt 0 2006.252.08:25:38.98#ibcon#cleared, iclass 19 cls_cnt 0 2006.252.08:25:38.98$vc4f8/va=4,7 2006.252.08:25:38.98#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.252.08:25:38.98#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.252.08:25:38.98#ibcon#ireg 11 cls_cnt 2 2006.252.08:25:38.98#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.252.08:25:39.04#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.252.08:25:39.04#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.252.08:25:39.04#ibcon#enter wrdev, iclass 21, count 2 2006.252.08:25:39.04#ibcon#first serial, iclass 21, count 2 2006.252.08:25:39.04#ibcon#enter sib2, iclass 21, count 2 2006.252.08:25:39.04#ibcon#flushed, iclass 21, count 2 2006.252.08:25:39.04#ibcon#about to write, iclass 21, count 2 2006.252.08:25:39.04#ibcon#wrote, iclass 21, count 2 2006.252.08:25:39.04#ibcon#about to read 3, iclass 21, count 2 2006.252.08:25:39.06#ibcon#read 3, iclass 21, count 2 2006.252.08:25:39.06#ibcon#about to read 4, iclass 21, count 2 2006.252.08:25:39.06#ibcon#read 4, iclass 21, count 2 2006.252.08:25:39.06#ibcon#about to read 5, iclass 21, count 2 2006.252.08:25:39.06#ibcon#read 5, iclass 21, count 2 2006.252.08:25:39.06#ibcon#about to read 6, iclass 21, count 2 2006.252.08:25:39.06#ibcon#read 6, iclass 21, count 2 2006.252.08:25:39.06#ibcon#end of sib2, iclass 21, count 2 2006.252.08:25:39.06#ibcon#*mode == 0, iclass 21, count 2 2006.252.08:25:39.06#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.252.08:25:39.06#ibcon#[25=AT04-07\r\n] 2006.252.08:25:39.06#ibcon#*before write, iclass 21, count 2 2006.252.08:25:39.06#ibcon#enter sib2, iclass 21, count 2 2006.252.08:25:39.06#ibcon#flushed, iclass 21, count 2 2006.252.08:25:39.06#ibcon#about to write, iclass 21, count 2 2006.252.08:25:39.06#ibcon#wrote, iclass 21, count 2 2006.252.08:25:39.06#ibcon#about to read 3, iclass 21, count 2 2006.252.08:25:39.09#ibcon#read 3, iclass 21, count 2 2006.252.08:25:39.09#ibcon#about to read 4, iclass 21, count 2 2006.252.08:25:39.09#ibcon#read 4, iclass 21, count 2 2006.252.08:25:39.09#ibcon#about to read 5, iclass 21, count 2 2006.252.08:25:39.09#ibcon#read 5, iclass 21, count 2 2006.252.08:25:39.09#ibcon#about to read 6, iclass 21, count 2 2006.252.08:25:39.09#ibcon#read 6, iclass 21, count 2 2006.252.08:25:39.09#ibcon#end of sib2, iclass 21, count 2 2006.252.08:25:39.09#ibcon#*after write, iclass 21, count 2 2006.252.08:25:39.09#ibcon#*before return 0, iclass 21, count 2 2006.252.08:25:39.09#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.252.08:25:39.09#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.252.08:25:39.09#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.252.08:25:39.09#ibcon#ireg 7 cls_cnt 0 2006.252.08:25:39.09#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.252.08:25:39.21#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.252.08:25:39.21#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.252.08:25:39.21#ibcon#enter wrdev, iclass 21, count 0 2006.252.08:25:39.21#ibcon#first serial, iclass 21, count 0 2006.252.08:25:39.21#ibcon#enter sib2, iclass 21, count 0 2006.252.08:25:39.21#ibcon#flushed, iclass 21, count 0 2006.252.08:25:39.21#ibcon#about to write, iclass 21, count 0 2006.252.08:25:39.21#ibcon#wrote, iclass 21, count 0 2006.252.08:25:39.21#ibcon#about to read 3, iclass 21, count 0 2006.252.08:25:39.23#ibcon#read 3, iclass 21, count 0 2006.252.08:25:39.23#ibcon#about to read 4, iclass 21, count 0 2006.252.08:25:39.23#ibcon#read 4, iclass 21, count 0 2006.252.08:25:39.23#ibcon#about to read 5, iclass 21, count 0 2006.252.08:25:39.23#ibcon#read 5, iclass 21, count 0 2006.252.08:25:39.23#ibcon#about to read 6, iclass 21, count 0 2006.252.08:25:39.23#ibcon#read 6, iclass 21, count 0 2006.252.08:25:39.23#ibcon#end of sib2, iclass 21, count 0 2006.252.08:25:39.23#ibcon#*mode == 0, iclass 21, count 0 2006.252.08:25:39.23#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.252.08:25:39.23#ibcon#[25=USB\r\n] 2006.252.08:25:39.23#ibcon#*before write, iclass 21, count 0 2006.252.08:25:39.23#ibcon#enter sib2, iclass 21, count 0 2006.252.08:25:39.23#ibcon#flushed, iclass 21, count 0 2006.252.08:25:39.23#ibcon#about to write, iclass 21, count 0 2006.252.08:25:39.23#ibcon#wrote, iclass 21, count 0 2006.252.08:25:39.23#ibcon#about to read 3, iclass 21, count 0 2006.252.08:25:39.26#ibcon#read 3, iclass 21, count 0 2006.252.08:25:39.26#ibcon#about to read 4, iclass 21, count 0 2006.252.08:25:39.26#ibcon#read 4, iclass 21, count 0 2006.252.08:25:39.26#ibcon#about to read 5, iclass 21, count 0 2006.252.08:25:39.26#ibcon#read 5, iclass 21, count 0 2006.252.08:25:39.26#ibcon#about to read 6, iclass 21, count 0 2006.252.08:25:39.26#ibcon#read 6, iclass 21, count 0 2006.252.08:25:39.26#ibcon#end of sib2, iclass 21, count 0 2006.252.08:25:39.26#ibcon#*after write, iclass 21, count 0 2006.252.08:25:39.26#ibcon#*before return 0, iclass 21, count 0 2006.252.08:25:39.26#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.252.08:25:39.26#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.252.08:25:39.26#ibcon#about to clear, iclass 21 cls_cnt 0 2006.252.08:25:39.26#ibcon#cleared, iclass 21 cls_cnt 0 2006.252.08:25:39.26$vc4f8/valo=5,652.99 2006.252.08:25:39.26#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.252.08:25:39.26#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.252.08:25:39.26#ibcon#ireg 17 cls_cnt 0 2006.252.08:25:39.26#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.252.08:25:39.26#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.252.08:25:39.26#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.252.08:25:39.26#ibcon#enter wrdev, iclass 23, count 0 2006.252.08:25:39.26#ibcon#first serial, iclass 23, count 0 2006.252.08:25:39.26#ibcon#enter sib2, iclass 23, count 0 2006.252.08:25:39.26#ibcon#flushed, iclass 23, count 0 2006.252.08:25:39.26#ibcon#about to write, iclass 23, count 0 2006.252.08:25:39.26#ibcon#wrote, iclass 23, count 0 2006.252.08:25:39.26#ibcon#about to read 3, iclass 23, count 0 2006.252.08:25:39.28#ibcon#read 3, iclass 23, count 0 2006.252.08:25:39.28#ibcon#about to read 4, iclass 23, count 0 2006.252.08:25:39.28#ibcon#read 4, iclass 23, count 0 2006.252.08:25:39.28#ibcon#about to read 5, iclass 23, count 0 2006.252.08:25:39.28#ibcon#read 5, iclass 23, count 0 2006.252.08:25:39.28#ibcon#about to read 6, iclass 23, count 0 2006.252.08:25:39.28#ibcon#read 6, iclass 23, count 0 2006.252.08:25:39.28#ibcon#end of sib2, iclass 23, count 0 2006.252.08:25:39.28#ibcon#*mode == 0, iclass 23, count 0 2006.252.08:25:39.28#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.252.08:25:39.28#ibcon#[26=FRQ=05,652.99\r\n] 2006.252.08:25:39.28#ibcon#*before write, iclass 23, count 0 2006.252.08:25:39.28#ibcon#enter sib2, iclass 23, count 0 2006.252.08:25:39.28#ibcon#flushed, iclass 23, count 0 2006.252.08:25:39.28#ibcon#about to write, iclass 23, count 0 2006.252.08:25:39.28#ibcon#wrote, iclass 23, count 0 2006.252.08:25:39.28#ibcon#about to read 3, iclass 23, count 0 2006.252.08:25:39.32#ibcon#read 3, iclass 23, count 0 2006.252.08:25:39.32#ibcon#about to read 4, iclass 23, count 0 2006.252.08:25:39.32#ibcon#read 4, iclass 23, count 0 2006.252.08:25:39.32#ibcon#about to read 5, iclass 23, count 0 2006.252.08:25:39.32#ibcon#read 5, iclass 23, count 0 2006.252.08:25:39.32#ibcon#about to read 6, iclass 23, count 0 2006.252.08:25:39.32#ibcon#read 6, iclass 23, count 0 2006.252.08:25:39.32#ibcon#end of sib2, iclass 23, count 0 2006.252.08:25:39.32#ibcon#*after write, iclass 23, count 0 2006.252.08:25:39.32#ibcon#*before return 0, iclass 23, count 0 2006.252.08:25:39.32#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.252.08:25:39.32#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.252.08:25:39.32#ibcon#about to clear, iclass 23 cls_cnt 0 2006.252.08:25:39.32#ibcon#cleared, iclass 23 cls_cnt 0 2006.252.08:25:39.32$vc4f8/va=5,7 2006.252.08:25:39.32#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.252.08:25:39.32#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.252.08:25:39.32#ibcon#ireg 11 cls_cnt 2 2006.252.08:25:39.32#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.252.08:25:39.38#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.252.08:25:39.38#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.252.08:25:39.38#ibcon#enter wrdev, iclass 25, count 2 2006.252.08:25:39.38#ibcon#first serial, iclass 25, count 2 2006.252.08:25:39.38#ibcon#enter sib2, iclass 25, count 2 2006.252.08:25:39.38#ibcon#flushed, iclass 25, count 2 2006.252.08:25:39.38#ibcon#about to write, iclass 25, count 2 2006.252.08:25:39.38#ibcon#wrote, iclass 25, count 2 2006.252.08:25:39.38#ibcon#about to read 3, iclass 25, count 2 2006.252.08:25:39.40#ibcon#read 3, iclass 25, count 2 2006.252.08:25:39.40#ibcon#about to read 4, iclass 25, count 2 2006.252.08:25:39.40#ibcon#read 4, iclass 25, count 2 2006.252.08:25:39.40#ibcon#about to read 5, iclass 25, count 2 2006.252.08:25:39.40#ibcon#read 5, iclass 25, count 2 2006.252.08:25:39.40#ibcon#about to read 6, iclass 25, count 2 2006.252.08:25:39.40#ibcon#read 6, iclass 25, count 2 2006.252.08:25:39.40#ibcon#end of sib2, iclass 25, count 2 2006.252.08:25:39.40#ibcon#*mode == 0, iclass 25, count 2 2006.252.08:25:39.40#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.252.08:25:39.40#ibcon#[25=AT05-07\r\n] 2006.252.08:25:39.40#ibcon#*before write, iclass 25, count 2 2006.252.08:25:39.40#ibcon#enter sib2, iclass 25, count 2 2006.252.08:25:39.40#ibcon#flushed, iclass 25, count 2 2006.252.08:25:39.40#ibcon#about to write, iclass 25, count 2 2006.252.08:25:39.40#ibcon#wrote, iclass 25, count 2 2006.252.08:25:39.40#ibcon#about to read 3, iclass 25, count 2 2006.252.08:25:39.43#ibcon#read 3, iclass 25, count 2 2006.252.08:25:39.43#ibcon#about to read 4, iclass 25, count 2 2006.252.08:25:39.43#ibcon#read 4, iclass 25, count 2 2006.252.08:25:39.43#ibcon#about to read 5, iclass 25, count 2 2006.252.08:25:39.43#ibcon#read 5, iclass 25, count 2 2006.252.08:25:39.43#ibcon#about to read 6, iclass 25, count 2 2006.252.08:25:39.43#ibcon#read 6, iclass 25, count 2 2006.252.08:25:39.43#ibcon#end of sib2, iclass 25, count 2 2006.252.08:25:39.43#ibcon#*after write, iclass 25, count 2 2006.252.08:25:39.43#ibcon#*before return 0, iclass 25, count 2 2006.252.08:25:39.43#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.252.08:25:39.43#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.252.08:25:39.43#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.252.08:25:39.43#ibcon#ireg 7 cls_cnt 0 2006.252.08:25:39.43#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.252.08:25:39.55#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.252.08:25:39.55#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.252.08:25:39.55#ibcon#enter wrdev, iclass 25, count 0 2006.252.08:25:39.55#ibcon#first serial, iclass 25, count 0 2006.252.08:25:39.55#ibcon#enter sib2, iclass 25, count 0 2006.252.08:25:39.55#ibcon#flushed, iclass 25, count 0 2006.252.08:25:39.55#ibcon#about to write, iclass 25, count 0 2006.252.08:25:39.55#ibcon#wrote, iclass 25, count 0 2006.252.08:25:39.55#ibcon#about to read 3, iclass 25, count 0 2006.252.08:25:39.57#ibcon#read 3, iclass 25, count 0 2006.252.08:25:39.57#ibcon#about to read 4, iclass 25, count 0 2006.252.08:25:39.57#ibcon#read 4, iclass 25, count 0 2006.252.08:25:39.57#ibcon#about to read 5, iclass 25, count 0 2006.252.08:25:39.57#ibcon#read 5, iclass 25, count 0 2006.252.08:25:39.57#ibcon#about to read 6, iclass 25, count 0 2006.252.08:25:39.57#ibcon#read 6, iclass 25, count 0 2006.252.08:25:39.57#ibcon#end of sib2, iclass 25, count 0 2006.252.08:25:39.57#ibcon#*mode == 0, iclass 25, count 0 2006.252.08:25:39.57#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.252.08:25:39.57#ibcon#[25=USB\r\n] 2006.252.08:25:39.57#ibcon#*before write, iclass 25, count 0 2006.252.08:25:39.57#ibcon#enter sib2, iclass 25, count 0 2006.252.08:25:39.57#ibcon#flushed, iclass 25, count 0 2006.252.08:25:39.57#ibcon#about to write, iclass 25, count 0 2006.252.08:25:39.57#ibcon#wrote, iclass 25, count 0 2006.252.08:25:39.57#ibcon#about to read 3, iclass 25, count 0 2006.252.08:25:39.60#ibcon#read 3, iclass 25, count 0 2006.252.08:25:39.60#ibcon#about to read 4, iclass 25, count 0 2006.252.08:25:39.60#ibcon#read 4, iclass 25, count 0 2006.252.08:25:39.60#ibcon#about to read 5, iclass 25, count 0 2006.252.08:25:39.60#ibcon#read 5, iclass 25, count 0 2006.252.08:25:39.60#ibcon#about to read 6, iclass 25, count 0 2006.252.08:25:39.60#ibcon#read 6, iclass 25, count 0 2006.252.08:25:39.60#ibcon#end of sib2, iclass 25, count 0 2006.252.08:25:39.60#ibcon#*after write, iclass 25, count 0 2006.252.08:25:39.60#ibcon#*before return 0, iclass 25, count 0 2006.252.08:25:39.60#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.252.08:25:39.60#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.252.08:25:39.60#ibcon#about to clear, iclass 25 cls_cnt 0 2006.252.08:25:39.60#ibcon#cleared, iclass 25 cls_cnt 0 2006.252.08:25:39.60$vc4f8/valo=6,772.99 2006.252.08:25:39.60#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.252.08:25:39.60#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.252.08:25:39.60#ibcon#ireg 17 cls_cnt 0 2006.252.08:25:39.60#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.252.08:25:39.60#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.252.08:25:39.60#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.252.08:25:39.60#ibcon#enter wrdev, iclass 27, count 0 2006.252.08:25:39.60#ibcon#first serial, iclass 27, count 0 2006.252.08:25:39.60#ibcon#enter sib2, iclass 27, count 0 2006.252.08:25:39.60#ibcon#flushed, iclass 27, count 0 2006.252.08:25:39.60#ibcon#about to write, iclass 27, count 0 2006.252.08:25:39.60#ibcon#wrote, iclass 27, count 0 2006.252.08:25:39.60#ibcon#about to read 3, iclass 27, count 0 2006.252.08:25:39.63#ibcon#read 3, iclass 27, count 0 2006.252.08:25:39.63#ibcon#about to read 4, iclass 27, count 0 2006.252.08:25:39.63#ibcon#read 4, iclass 27, count 0 2006.252.08:25:39.63#ibcon#about to read 5, iclass 27, count 0 2006.252.08:25:39.63#ibcon#read 5, iclass 27, count 0 2006.252.08:25:39.63#ibcon#about to read 6, iclass 27, count 0 2006.252.08:25:39.63#ibcon#read 6, iclass 27, count 0 2006.252.08:25:39.63#ibcon#end of sib2, iclass 27, count 0 2006.252.08:25:39.63#ibcon#*mode == 0, iclass 27, count 0 2006.252.08:25:39.63#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.252.08:25:39.63#ibcon#[26=FRQ=06,772.99\r\n] 2006.252.08:25:39.63#ibcon#*before write, iclass 27, count 0 2006.252.08:25:39.63#ibcon#enter sib2, iclass 27, count 0 2006.252.08:25:39.63#ibcon#flushed, iclass 27, count 0 2006.252.08:25:39.63#ibcon#about to write, iclass 27, count 0 2006.252.08:25:39.63#ibcon#wrote, iclass 27, count 0 2006.252.08:25:39.63#ibcon#about to read 3, iclass 27, count 0 2006.252.08:25:39.67#ibcon#read 3, iclass 27, count 0 2006.252.08:25:39.67#ibcon#about to read 4, iclass 27, count 0 2006.252.08:25:39.67#ibcon#read 4, iclass 27, count 0 2006.252.08:25:39.67#ibcon#about to read 5, iclass 27, count 0 2006.252.08:25:39.67#ibcon#read 5, iclass 27, count 0 2006.252.08:25:39.67#ibcon#about to read 6, iclass 27, count 0 2006.252.08:25:39.67#ibcon#read 6, iclass 27, count 0 2006.252.08:25:39.67#ibcon#end of sib2, iclass 27, count 0 2006.252.08:25:39.67#ibcon#*after write, iclass 27, count 0 2006.252.08:25:39.67#ibcon#*before return 0, iclass 27, count 0 2006.252.08:25:39.67#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.252.08:25:39.67#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.252.08:25:39.67#ibcon#about to clear, iclass 27 cls_cnt 0 2006.252.08:25:39.67#ibcon#cleared, iclass 27 cls_cnt 0 2006.252.08:25:39.67$vc4f8/va=6,7 2006.252.08:25:39.67#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.252.08:25:39.67#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.252.08:25:39.67#ibcon#ireg 11 cls_cnt 2 2006.252.08:25:39.67#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.252.08:25:39.72#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.252.08:25:39.72#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.252.08:25:39.72#ibcon#enter wrdev, iclass 29, count 2 2006.252.08:25:39.72#ibcon#first serial, iclass 29, count 2 2006.252.08:25:39.72#ibcon#enter sib2, iclass 29, count 2 2006.252.08:25:39.72#ibcon#flushed, iclass 29, count 2 2006.252.08:25:39.72#ibcon#about to write, iclass 29, count 2 2006.252.08:25:39.72#ibcon#wrote, iclass 29, count 2 2006.252.08:25:39.72#ibcon#about to read 3, iclass 29, count 2 2006.252.08:25:39.74#ibcon#read 3, iclass 29, count 2 2006.252.08:25:39.74#ibcon#about to read 4, iclass 29, count 2 2006.252.08:25:39.74#ibcon#read 4, iclass 29, count 2 2006.252.08:25:39.74#ibcon#about to read 5, iclass 29, count 2 2006.252.08:25:39.74#ibcon#read 5, iclass 29, count 2 2006.252.08:25:39.74#ibcon#about to read 6, iclass 29, count 2 2006.252.08:25:39.74#ibcon#read 6, iclass 29, count 2 2006.252.08:25:39.74#ibcon#end of sib2, iclass 29, count 2 2006.252.08:25:39.74#ibcon#*mode == 0, iclass 29, count 2 2006.252.08:25:39.74#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.252.08:25:39.74#ibcon#[25=AT06-07\r\n] 2006.252.08:25:39.74#ibcon#*before write, iclass 29, count 2 2006.252.08:25:39.74#ibcon#enter sib2, iclass 29, count 2 2006.252.08:25:39.74#ibcon#flushed, iclass 29, count 2 2006.252.08:25:39.74#ibcon#about to write, iclass 29, count 2 2006.252.08:25:39.74#ibcon#wrote, iclass 29, count 2 2006.252.08:25:39.74#ibcon#about to read 3, iclass 29, count 2 2006.252.08:25:39.77#ibcon#read 3, iclass 29, count 2 2006.252.08:25:39.77#ibcon#about to read 4, iclass 29, count 2 2006.252.08:25:39.77#ibcon#read 4, iclass 29, count 2 2006.252.08:25:39.77#ibcon#about to read 5, iclass 29, count 2 2006.252.08:25:39.77#ibcon#read 5, iclass 29, count 2 2006.252.08:25:39.77#ibcon#about to read 6, iclass 29, count 2 2006.252.08:25:39.77#ibcon#read 6, iclass 29, count 2 2006.252.08:25:39.77#ibcon#end of sib2, iclass 29, count 2 2006.252.08:25:39.77#ibcon#*after write, iclass 29, count 2 2006.252.08:25:39.77#ibcon#*before return 0, iclass 29, count 2 2006.252.08:25:39.77#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.252.08:25:39.77#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.252.08:25:39.77#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.252.08:25:39.77#ibcon#ireg 7 cls_cnt 0 2006.252.08:25:39.77#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.252.08:25:39.89#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.252.08:25:39.89#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.252.08:25:39.89#ibcon#enter wrdev, iclass 29, count 0 2006.252.08:25:39.89#ibcon#first serial, iclass 29, count 0 2006.252.08:25:39.89#ibcon#enter sib2, iclass 29, count 0 2006.252.08:25:39.89#ibcon#flushed, iclass 29, count 0 2006.252.08:25:39.89#ibcon#about to write, iclass 29, count 0 2006.252.08:25:39.89#ibcon#wrote, iclass 29, count 0 2006.252.08:25:39.89#ibcon#about to read 3, iclass 29, count 0 2006.252.08:25:39.91#ibcon#read 3, iclass 29, count 0 2006.252.08:25:39.91#ibcon#about to read 4, iclass 29, count 0 2006.252.08:25:39.91#ibcon#read 4, iclass 29, count 0 2006.252.08:25:39.91#ibcon#about to read 5, iclass 29, count 0 2006.252.08:25:39.91#ibcon#read 5, iclass 29, count 0 2006.252.08:25:39.91#ibcon#about to read 6, iclass 29, count 0 2006.252.08:25:39.91#ibcon#read 6, iclass 29, count 0 2006.252.08:25:39.91#ibcon#end of sib2, iclass 29, count 0 2006.252.08:25:39.91#ibcon#*mode == 0, iclass 29, count 0 2006.252.08:25:39.91#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.252.08:25:39.91#ibcon#[25=USB\r\n] 2006.252.08:25:39.91#ibcon#*before write, iclass 29, count 0 2006.252.08:25:39.91#ibcon#enter sib2, iclass 29, count 0 2006.252.08:25:39.91#ibcon#flushed, iclass 29, count 0 2006.252.08:25:39.91#ibcon#about to write, iclass 29, count 0 2006.252.08:25:39.91#ibcon#wrote, iclass 29, count 0 2006.252.08:25:39.91#ibcon#about to read 3, iclass 29, count 0 2006.252.08:25:39.94#ibcon#read 3, iclass 29, count 0 2006.252.08:25:39.94#ibcon#about to read 4, iclass 29, count 0 2006.252.08:25:39.94#ibcon#read 4, iclass 29, count 0 2006.252.08:25:39.94#ibcon#about to read 5, iclass 29, count 0 2006.252.08:25:39.94#ibcon#read 5, iclass 29, count 0 2006.252.08:25:39.94#ibcon#about to read 6, iclass 29, count 0 2006.252.08:25:39.94#ibcon#read 6, iclass 29, count 0 2006.252.08:25:39.94#ibcon#end of sib2, iclass 29, count 0 2006.252.08:25:39.94#ibcon#*after write, iclass 29, count 0 2006.252.08:25:39.94#ibcon#*before return 0, iclass 29, count 0 2006.252.08:25:39.94#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.252.08:25:39.94#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.252.08:25:39.94#ibcon#about to clear, iclass 29 cls_cnt 0 2006.252.08:25:39.94#ibcon#cleared, iclass 29 cls_cnt 0 2006.252.08:25:39.94$vc4f8/valo=7,832.99 2006.252.08:25:39.94#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.252.08:25:39.94#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.252.08:25:39.94#ibcon#ireg 17 cls_cnt 0 2006.252.08:25:39.94#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.252.08:25:39.94#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.252.08:25:39.94#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.252.08:25:39.94#ibcon#enter wrdev, iclass 31, count 0 2006.252.08:25:39.94#ibcon#first serial, iclass 31, count 0 2006.252.08:25:39.94#ibcon#enter sib2, iclass 31, count 0 2006.252.08:25:39.94#ibcon#flushed, iclass 31, count 0 2006.252.08:25:39.94#ibcon#about to write, iclass 31, count 0 2006.252.08:25:39.94#ibcon#wrote, iclass 31, count 0 2006.252.08:25:39.94#ibcon#about to read 3, iclass 31, count 0 2006.252.08:25:39.96#ibcon#read 3, iclass 31, count 0 2006.252.08:25:39.96#ibcon#about to read 4, iclass 31, count 0 2006.252.08:25:39.96#ibcon#read 4, iclass 31, count 0 2006.252.08:25:39.96#ibcon#about to read 5, iclass 31, count 0 2006.252.08:25:39.96#ibcon#read 5, iclass 31, count 0 2006.252.08:25:39.96#ibcon#about to read 6, iclass 31, count 0 2006.252.08:25:39.96#ibcon#read 6, iclass 31, count 0 2006.252.08:25:39.96#ibcon#end of sib2, iclass 31, count 0 2006.252.08:25:39.96#ibcon#*mode == 0, iclass 31, count 0 2006.252.08:25:39.96#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.252.08:25:39.96#ibcon#[26=FRQ=07,832.99\r\n] 2006.252.08:25:39.96#ibcon#*before write, iclass 31, count 0 2006.252.08:25:39.96#ibcon#enter sib2, iclass 31, count 0 2006.252.08:25:39.96#ibcon#flushed, iclass 31, count 0 2006.252.08:25:39.96#ibcon#about to write, iclass 31, count 0 2006.252.08:25:39.96#ibcon#wrote, iclass 31, count 0 2006.252.08:25:39.96#ibcon#about to read 3, iclass 31, count 0 2006.252.08:25:40.00#ibcon#read 3, iclass 31, count 0 2006.252.08:25:40.00#ibcon#about to read 4, iclass 31, count 0 2006.252.08:25:40.00#ibcon#read 4, iclass 31, count 0 2006.252.08:25:40.00#ibcon#about to read 5, iclass 31, count 0 2006.252.08:25:40.00#ibcon#read 5, iclass 31, count 0 2006.252.08:25:40.00#ibcon#about to read 6, iclass 31, count 0 2006.252.08:25:40.00#ibcon#read 6, iclass 31, count 0 2006.252.08:25:40.00#ibcon#end of sib2, iclass 31, count 0 2006.252.08:25:40.00#ibcon#*after write, iclass 31, count 0 2006.252.08:25:40.00#ibcon#*before return 0, iclass 31, count 0 2006.252.08:25:40.00#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.252.08:25:40.00#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.252.08:25:40.00#ibcon#about to clear, iclass 31 cls_cnt 0 2006.252.08:25:40.00#ibcon#cleared, iclass 31 cls_cnt 0 2006.252.08:25:40.00$vc4f8/va=7,7 2006.252.08:25:40.00#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.252.08:25:40.00#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.252.08:25:40.00#ibcon#ireg 11 cls_cnt 2 2006.252.08:25:40.00#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.252.08:25:40.06#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.252.08:25:40.06#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.252.08:25:40.06#ibcon#enter wrdev, iclass 33, count 2 2006.252.08:25:40.06#ibcon#first serial, iclass 33, count 2 2006.252.08:25:40.06#ibcon#enter sib2, iclass 33, count 2 2006.252.08:25:40.06#ibcon#flushed, iclass 33, count 2 2006.252.08:25:40.06#ibcon#about to write, iclass 33, count 2 2006.252.08:25:40.06#ibcon#wrote, iclass 33, count 2 2006.252.08:25:40.06#ibcon#about to read 3, iclass 33, count 2 2006.252.08:25:40.08#ibcon#read 3, iclass 33, count 2 2006.252.08:25:40.08#ibcon#about to read 4, iclass 33, count 2 2006.252.08:25:40.08#ibcon#read 4, iclass 33, count 2 2006.252.08:25:40.08#ibcon#about to read 5, iclass 33, count 2 2006.252.08:25:40.08#ibcon#read 5, iclass 33, count 2 2006.252.08:25:40.08#ibcon#about to read 6, iclass 33, count 2 2006.252.08:25:40.08#ibcon#read 6, iclass 33, count 2 2006.252.08:25:40.08#ibcon#end of sib2, iclass 33, count 2 2006.252.08:25:40.08#ibcon#*mode == 0, iclass 33, count 2 2006.252.08:25:40.08#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.252.08:25:40.08#ibcon#[25=AT07-07\r\n] 2006.252.08:25:40.08#ibcon#*before write, iclass 33, count 2 2006.252.08:25:40.08#ibcon#enter sib2, iclass 33, count 2 2006.252.08:25:40.08#ibcon#flushed, iclass 33, count 2 2006.252.08:25:40.08#ibcon#about to write, iclass 33, count 2 2006.252.08:25:40.08#ibcon#wrote, iclass 33, count 2 2006.252.08:25:40.08#ibcon#about to read 3, iclass 33, count 2 2006.252.08:25:40.11#ibcon#read 3, iclass 33, count 2 2006.252.08:25:40.11#ibcon#about to read 4, iclass 33, count 2 2006.252.08:25:40.11#ibcon#read 4, iclass 33, count 2 2006.252.08:25:40.11#ibcon#about to read 5, iclass 33, count 2 2006.252.08:25:40.11#ibcon#read 5, iclass 33, count 2 2006.252.08:25:40.11#ibcon#about to read 6, iclass 33, count 2 2006.252.08:25:40.11#ibcon#read 6, iclass 33, count 2 2006.252.08:25:40.11#ibcon#end of sib2, iclass 33, count 2 2006.252.08:25:40.11#ibcon#*after write, iclass 33, count 2 2006.252.08:25:40.11#ibcon#*before return 0, iclass 33, count 2 2006.252.08:25:40.11#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.252.08:25:40.11#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.252.08:25:40.11#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.252.08:25:40.11#ibcon#ireg 7 cls_cnt 0 2006.252.08:25:40.11#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.252.08:25:40.23#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.252.08:25:40.23#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.252.08:25:40.23#ibcon#enter wrdev, iclass 33, count 0 2006.252.08:25:40.23#ibcon#first serial, iclass 33, count 0 2006.252.08:25:40.23#ibcon#enter sib2, iclass 33, count 0 2006.252.08:25:40.23#ibcon#flushed, iclass 33, count 0 2006.252.08:25:40.23#ibcon#about to write, iclass 33, count 0 2006.252.08:25:40.23#ibcon#wrote, iclass 33, count 0 2006.252.08:25:40.23#ibcon#about to read 3, iclass 33, count 0 2006.252.08:25:40.25#ibcon#read 3, iclass 33, count 0 2006.252.08:25:40.25#ibcon#about to read 4, iclass 33, count 0 2006.252.08:25:40.25#ibcon#read 4, iclass 33, count 0 2006.252.08:25:40.25#ibcon#about to read 5, iclass 33, count 0 2006.252.08:25:40.25#ibcon#read 5, iclass 33, count 0 2006.252.08:25:40.25#ibcon#about to read 6, iclass 33, count 0 2006.252.08:25:40.25#ibcon#read 6, iclass 33, count 0 2006.252.08:25:40.25#ibcon#end of sib2, iclass 33, count 0 2006.252.08:25:40.25#ibcon#*mode == 0, iclass 33, count 0 2006.252.08:25:40.25#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.252.08:25:40.25#ibcon#[25=USB\r\n] 2006.252.08:25:40.25#ibcon#*before write, iclass 33, count 0 2006.252.08:25:40.25#ibcon#enter sib2, iclass 33, count 0 2006.252.08:25:40.25#ibcon#flushed, iclass 33, count 0 2006.252.08:25:40.25#ibcon#about to write, iclass 33, count 0 2006.252.08:25:40.25#ibcon#wrote, iclass 33, count 0 2006.252.08:25:40.25#ibcon#about to read 3, iclass 33, count 0 2006.252.08:25:40.28#ibcon#read 3, iclass 33, count 0 2006.252.08:25:40.28#ibcon#about to read 4, iclass 33, count 0 2006.252.08:25:40.28#ibcon#read 4, iclass 33, count 0 2006.252.08:25:40.28#ibcon#about to read 5, iclass 33, count 0 2006.252.08:25:40.28#ibcon#read 5, iclass 33, count 0 2006.252.08:25:40.28#ibcon#about to read 6, iclass 33, count 0 2006.252.08:25:40.28#ibcon#read 6, iclass 33, count 0 2006.252.08:25:40.28#ibcon#end of sib2, iclass 33, count 0 2006.252.08:25:40.28#ibcon#*after write, iclass 33, count 0 2006.252.08:25:40.28#ibcon#*before return 0, iclass 33, count 0 2006.252.08:25:40.28#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.252.08:25:40.28#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.252.08:25:40.28#ibcon#about to clear, iclass 33 cls_cnt 0 2006.252.08:25:40.28#ibcon#cleared, iclass 33 cls_cnt 0 2006.252.08:25:40.28$vc4f8/valo=8,852.99 2006.252.08:25:40.28#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.252.08:25:40.28#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.252.08:25:40.28#ibcon#ireg 17 cls_cnt 0 2006.252.08:25:40.28#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.252.08:25:40.28#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.252.08:25:40.28#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.252.08:25:40.28#ibcon#enter wrdev, iclass 35, count 0 2006.252.08:25:40.28#ibcon#first serial, iclass 35, count 0 2006.252.08:25:40.28#ibcon#enter sib2, iclass 35, count 0 2006.252.08:25:40.28#ibcon#flushed, iclass 35, count 0 2006.252.08:25:40.28#ibcon#about to write, iclass 35, count 0 2006.252.08:25:40.28#ibcon#wrote, iclass 35, count 0 2006.252.08:25:40.28#ibcon#about to read 3, iclass 35, count 0 2006.252.08:25:40.30#ibcon#read 3, iclass 35, count 0 2006.252.08:25:40.30#ibcon#about to read 4, iclass 35, count 0 2006.252.08:25:40.30#ibcon#read 4, iclass 35, count 0 2006.252.08:25:40.30#ibcon#about to read 5, iclass 35, count 0 2006.252.08:25:40.30#ibcon#read 5, iclass 35, count 0 2006.252.08:25:40.30#ibcon#about to read 6, iclass 35, count 0 2006.252.08:25:40.30#ibcon#read 6, iclass 35, count 0 2006.252.08:25:40.30#ibcon#end of sib2, iclass 35, count 0 2006.252.08:25:40.30#ibcon#*mode == 0, iclass 35, count 0 2006.252.08:25:40.30#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.252.08:25:40.30#ibcon#[26=FRQ=08,852.99\r\n] 2006.252.08:25:40.30#ibcon#*before write, iclass 35, count 0 2006.252.08:25:40.30#ibcon#enter sib2, iclass 35, count 0 2006.252.08:25:40.30#ibcon#flushed, iclass 35, count 0 2006.252.08:25:40.30#ibcon#about to write, iclass 35, count 0 2006.252.08:25:40.30#ibcon#wrote, iclass 35, count 0 2006.252.08:25:40.30#ibcon#about to read 3, iclass 35, count 0 2006.252.08:25:40.34#ibcon#read 3, iclass 35, count 0 2006.252.08:25:40.34#ibcon#about to read 4, iclass 35, count 0 2006.252.08:25:40.34#ibcon#read 4, iclass 35, count 0 2006.252.08:25:40.34#ibcon#about to read 5, iclass 35, count 0 2006.252.08:25:40.34#ibcon#read 5, iclass 35, count 0 2006.252.08:25:40.34#ibcon#about to read 6, iclass 35, count 0 2006.252.08:25:40.34#ibcon#read 6, iclass 35, count 0 2006.252.08:25:40.34#ibcon#end of sib2, iclass 35, count 0 2006.252.08:25:40.34#ibcon#*after write, iclass 35, count 0 2006.252.08:25:40.34#ibcon#*before return 0, iclass 35, count 0 2006.252.08:25:40.34#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.252.08:25:40.34#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.252.08:25:40.34#ibcon#about to clear, iclass 35 cls_cnt 0 2006.252.08:25:40.34#ibcon#cleared, iclass 35 cls_cnt 0 2006.252.08:25:40.34$vc4f8/va=8,7 2006.252.08:25:40.34#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.252.08:25:40.34#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.252.08:25:40.34#ibcon#ireg 11 cls_cnt 2 2006.252.08:25:40.34#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.252.08:25:40.41#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.252.08:25:40.41#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.252.08:25:40.41#ibcon#enter wrdev, iclass 37, count 2 2006.252.08:25:40.41#ibcon#first serial, iclass 37, count 2 2006.252.08:25:40.41#ibcon#enter sib2, iclass 37, count 2 2006.252.08:25:40.41#ibcon#flushed, iclass 37, count 2 2006.252.08:25:40.41#ibcon#about to write, iclass 37, count 2 2006.252.08:25:40.41#ibcon#wrote, iclass 37, count 2 2006.252.08:25:40.41#ibcon#about to read 3, iclass 37, count 2 2006.252.08:25:40.42#ibcon#read 3, iclass 37, count 2 2006.252.08:25:40.42#ibcon#about to read 4, iclass 37, count 2 2006.252.08:25:40.42#ibcon#read 4, iclass 37, count 2 2006.252.08:25:40.42#ibcon#about to read 5, iclass 37, count 2 2006.252.08:25:40.42#ibcon#read 5, iclass 37, count 2 2006.252.08:25:40.42#ibcon#about to read 6, iclass 37, count 2 2006.252.08:25:40.42#ibcon#read 6, iclass 37, count 2 2006.252.08:25:40.42#ibcon#end of sib2, iclass 37, count 2 2006.252.08:25:40.42#ibcon#*mode == 0, iclass 37, count 2 2006.252.08:25:40.42#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.252.08:25:40.42#ibcon#[25=AT08-07\r\n] 2006.252.08:25:40.42#ibcon#*before write, iclass 37, count 2 2006.252.08:25:40.42#ibcon#enter sib2, iclass 37, count 2 2006.252.08:25:40.42#ibcon#flushed, iclass 37, count 2 2006.252.08:25:40.42#ibcon#about to write, iclass 37, count 2 2006.252.08:25:40.42#ibcon#wrote, iclass 37, count 2 2006.252.08:25:40.42#ibcon#about to read 3, iclass 37, count 2 2006.252.08:25:40.45#ibcon#read 3, iclass 37, count 2 2006.252.08:25:40.45#ibcon#about to read 4, iclass 37, count 2 2006.252.08:25:40.45#ibcon#read 4, iclass 37, count 2 2006.252.08:25:40.45#ibcon#about to read 5, iclass 37, count 2 2006.252.08:25:40.45#ibcon#read 5, iclass 37, count 2 2006.252.08:25:40.45#ibcon#about to read 6, iclass 37, count 2 2006.252.08:25:40.45#ibcon#read 6, iclass 37, count 2 2006.252.08:25:40.45#ibcon#end of sib2, iclass 37, count 2 2006.252.08:25:40.45#ibcon#*after write, iclass 37, count 2 2006.252.08:25:40.45#ibcon#*before return 0, iclass 37, count 2 2006.252.08:25:40.45#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.252.08:25:40.45#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.252.08:25:40.45#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.252.08:25:40.45#ibcon#ireg 7 cls_cnt 0 2006.252.08:25:40.45#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.252.08:25:40.57#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.252.08:25:40.57#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.252.08:25:40.57#ibcon#enter wrdev, iclass 37, count 0 2006.252.08:25:40.57#ibcon#first serial, iclass 37, count 0 2006.252.08:25:40.57#ibcon#enter sib2, iclass 37, count 0 2006.252.08:25:40.57#ibcon#flushed, iclass 37, count 0 2006.252.08:25:40.57#ibcon#about to write, iclass 37, count 0 2006.252.08:25:40.57#ibcon#wrote, iclass 37, count 0 2006.252.08:25:40.57#ibcon#about to read 3, iclass 37, count 0 2006.252.08:25:40.59#ibcon#read 3, iclass 37, count 0 2006.252.08:25:40.59#ibcon#about to read 4, iclass 37, count 0 2006.252.08:25:40.59#ibcon#read 4, iclass 37, count 0 2006.252.08:25:40.59#ibcon#about to read 5, iclass 37, count 0 2006.252.08:25:40.59#ibcon#read 5, iclass 37, count 0 2006.252.08:25:40.59#ibcon#about to read 6, iclass 37, count 0 2006.252.08:25:40.59#ibcon#read 6, iclass 37, count 0 2006.252.08:25:40.59#ibcon#end of sib2, iclass 37, count 0 2006.252.08:25:40.59#ibcon#*mode == 0, iclass 37, count 0 2006.252.08:25:40.59#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.252.08:25:40.59#ibcon#[25=USB\r\n] 2006.252.08:25:40.59#ibcon#*before write, iclass 37, count 0 2006.252.08:25:40.59#ibcon#enter sib2, iclass 37, count 0 2006.252.08:25:40.59#ibcon#flushed, iclass 37, count 0 2006.252.08:25:40.59#ibcon#about to write, iclass 37, count 0 2006.252.08:25:40.59#ibcon#wrote, iclass 37, count 0 2006.252.08:25:40.59#ibcon#about to read 3, iclass 37, count 0 2006.252.08:25:40.62#ibcon#read 3, iclass 37, count 0 2006.252.08:25:40.62#ibcon#about to read 4, iclass 37, count 0 2006.252.08:25:40.62#ibcon#read 4, iclass 37, count 0 2006.252.08:25:40.62#ibcon#about to read 5, iclass 37, count 0 2006.252.08:25:40.62#ibcon#read 5, iclass 37, count 0 2006.252.08:25:40.62#ibcon#about to read 6, iclass 37, count 0 2006.252.08:25:40.62#ibcon#read 6, iclass 37, count 0 2006.252.08:25:40.62#ibcon#end of sib2, iclass 37, count 0 2006.252.08:25:40.62#ibcon#*after write, iclass 37, count 0 2006.252.08:25:40.62#ibcon#*before return 0, iclass 37, count 0 2006.252.08:25:40.62#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.252.08:25:40.62#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.252.08:25:40.62#ibcon#about to clear, iclass 37 cls_cnt 0 2006.252.08:25:40.62#ibcon#cleared, iclass 37 cls_cnt 0 2006.252.08:25:40.62$vc4f8/vblo=1,632.99 2006.252.08:25:40.62#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.252.08:25:40.62#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.252.08:25:40.62#ibcon#ireg 17 cls_cnt 0 2006.252.08:25:40.62#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.252.08:25:40.62#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.252.08:25:40.62#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.252.08:25:40.62#ibcon#enter wrdev, iclass 39, count 0 2006.252.08:25:40.62#ibcon#first serial, iclass 39, count 0 2006.252.08:25:40.62#ibcon#enter sib2, iclass 39, count 0 2006.252.08:25:40.62#ibcon#flushed, iclass 39, count 0 2006.252.08:25:40.62#ibcon#about to write, iclass 39, count 0 2006.252.08:25:40.62#ibcon#wrote, iclass 39, count 0 2006.252.08:25:40.62#ibcon#about to read 3, iclass 39, count 0 2006.252.08:25:40.64#ibcon#read 3, iclass 39, count 0 2006.252.08:25:40.64#ibcon#about to read 4, iclass 39, count 0 2006.252.08:25:40.64#ibcon#read 4, iclass 39, count 0 2006.252.08:25:40.64#ibcon#about to read 5, iclass 39, count 0 2006.252.08:25:40.64#ibcon#read 5, iclass 39, count 0 2006.252.08:25:40.64#ibcon#about to read 6, iclass 39, count 0 2006.252.08:25:40.64#ibcon#read 6, iclass 39, count 0 2006.252.08:25:40.64#ibcon#end of sib2, iclass 39, count 0 2006.252.08:25:40.64#ibcon#*mode == 0, iclass 39, count 0 2006.252.08:25:40.64#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.252.08:25:40.64#ibcon#[28=FRQ=01,632.99\r\n] 2006.252.08:25:40.64#ibcon#*before write, iclass 39, count 0 2006.252.08:25:40.64#ibcon#enter sib2, iclass 39, count 0 2006.252.08:25:40.64#ibcon#flushed, iclass 39, count 0 2006.252.08:25:40.64#ibcon#about to write, iclass 39, count 0 2006.252.08:25:40.64#ibcon#wrote, iclass 39, count 0 2006.252.08:25:40.64#ibcon#about to read 3, iclass 39, count 0 2006.252.08:25:40.68#ibcon#read 3, iclass 39, count 0 2006.252.08:25:40.68#ibcon#about to read 4, iclass 39, count 0 2006.252.08:25:40.68#ibcon#read 4, iclass 39, count 0 2006.252.08:25:40.68#ibcon#about to read 5, iclass 39, count 0 2006.252.08:25:40.68#ibcon#read 5, iclass 39, count 0 2006.252.08:25:40.68#ibcon#about to read 6, iclass 39, count 0 2006.252.08:25:40.68#ibcon#read 6, iclass 39, count 0 2006.252.08:25:40.68#ibcon#end of sib2, iclass 39, count 0 2006.252.08:25:40.68#ibcon#*after write, iclass 39, count 0 2006.252.08:25:40.68#ibcon#*before return 0, iclass 39, count 0 2006.252.08:25:40.68#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.252.08:25:40.68#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.252.08:25:40.68#ibcon#about to clear, iclass 39 cls_cnt 0 2006.252.08:25:40.68#ibcon#cleared, iclass 39 cls_cnt 0 2006.252.08:25:40.68$vc4f8/vb=1,4 2006.252.08:25:40.68#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.252.08:25:40.68#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.252.08:25:40.68#ibcon#ireg 11 cls_cnt 2 2006.252.08:25:40.68#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.252.08:25:40.68#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.252.08:25:40.68#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.252.08:25:40.68#ibcon#enter wrdev, iclass 3, count 2 2006.252.08:25:40.68#ibcon#first serial, iclass 3, count 2 2006.252.08:25:40.68#ibcon#enter sib2, iclass 3, count 2 2006.252.08:25:40.68#ibcon#flushed, iclass 3, count 2 2006.252.08:25:40.68#ibcon#about to write, iclass 3, count 2 2006.252.08:25:40.68#ibcon#wrote, iclass 3, count 2 2006.252.08:25:40.68#ibcon#about to read 3, iclass 3, count 2 2006.252.08:25:40.70#ibcon#read 3, iclass 3, count 2 2006.252.08:25:40.70#ibcon#about to read 4, iclass 3, count 2 2006.252.08:25:40.70#ibcon#read 4, iclass 3, count 2 2006.252.08:25:40.70#ibcon#about to read 5, iclass 3, count 2 2006.252.08:25:40.70#ibcon#read 5, iclass 3, count 2 2006.252.08:25:40.70#ibcon#about to read 6, iclass 3, count 2 2006.252.08:25:40.70#ibcon#read 6, iclass 3, count 2 2006.252.08:25:40.70#ibcon#end of sib2, iclass 3, count 2 2006.252.08:25:40.70#ibcon#*mode == 0, iclass 3, count 2 2006.252.08:25:40.70#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.252.08:25:40.70#ibcon#[27=AT01-04\r\n] 2006.252.08:25:40.70#ibcon#*before write, iclass 3, count 2 2006.252.08:25:40.70#ibcon#enter sib2, iclass 3, count 2 2006.252.08:25:40.70#ibcon#flushed, iclass 3, count 2 2006.252.08:25:40.70#ibcon#about to write, iclass 3, count 2 2006.252.08:25:40.70#ibcon#wrote, iclass 3, count 2 2006.252.08:25:40.70#ibcon#about to read 3, iclass 3, count 2 2006.252.08:25:40.73#ibcon#read 3, iclass 3, count 2 2006.252.08:25:40.73#ibcon#about to read 4, iclass 3, count 2 2006.252.08:25:40.73#ibcon#read 4, iclass 3, count 2 2006.252.08:25:40.73#ibcon#about to read 5, iclass 3, count 2 2006.252.08:25:40.73#ibcon#read 5, iclass 3, count 2 2006.252.08:25:40.73#ibcon#about to read 6, iclass 3, count 2 2006.252.08:25:40.73#ibcon#read 6, iclass 3, count 2 2006.252.08:25:40.73#ibcon#end of sib2, iclass 3, count 2 2006.252.08:25:40.73#ibcon#*after write, iclass 3, count 2 2006.252.08:25:40.73#ibcon#*before return 0, iclass 3, count 2 2006.252.08:25:40.73#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.252.08:25:40.73#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.252.08:25:40.73#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.252.08:25:40.73#ibcon#ireg 7 cls_cnt 0 2006.252.08:25:40.73#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.252.08:25:40.85#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.252.08:25:40.85#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.252.08:25:40.85#ibcon#enter wrdev, iclass 3, count 0 2006.252.08:25:40.85#ibcon#first serial, iclass 3, count 0 2006.252.08:25:40.85#ibcon#enter sib2, iclass 3, count 0 2006.252.08:25:40.85#ibcon#flushed, iclass 3, count 0 2006.252.08:25:40.85#ibcon#about to write, iclass 3, count 0 2006.252.08:25:40.85#ibcon#wrote, iclass 3, count 0 2006.252.08:25:40.85#ibcon#about to read 3, iclass 3, count 0 2006.252.08:25:40.87#ibcon#read 3, iclass 3, count 0 2006.252.08:25:40.87#ibcon#about to read 4, iclass 3, count 0 2006.252.08:25:40.87#ibcon#read 4, iclass 3, count 0 2006.252.08:25:40.87#ibcon#about to read 5, iclass 3, count 0 2006.252.08:25:40.87#ibcon#read 5, iclass 3, count 0 2006.252.08:25:40.87#ibcon#about to read 6, iclass 3, count 0 2006.252.08:25:40.87#ibcon#read 6, iclass 3, count 0 2006.252.08:25:40.87#ibcon#end of sib2, iclass 3, count 0 2006.252.08:25:40.87#ibcon#*mode == 0, iclass 3, count 0 2006.252.08:25:40.87#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.252.08:25:40.87#ibcon#[27=USB\r\n] 2006.252.08:25:40.87#ibcon#*before write, iclass 3, count 0 2006.252.08:25:40.87#ibcon#enter sib2, iclass 3, count 0 2006.252.08:25:40.87#ibcon#flushed, iclass 3, count 0 2006.252.08:25:40.87#ibcon#about to write, iclass 3, count 0 2006.252.08:25:40.87#ibcon#wrote, iclass 3, count 0 2006.252.08:25:40.87#ibcon#about to read 3, iclass 3, count 0 2006.252.08:25:40.90#ibcon#read 3, iclass 3, count 0 2006.252.08:25:40.90#ibcon#about to read 4, iclass 3, count 0 2006.252.08:25:40.90#ibcon#read 4, iclass 3, count 0 2006.252.08:25:40.90#ibcon#about to read 5, iclass 3, count 0 2006.252.08:25:40.90#ibcon#read 5, iclass 3, count 0 2006.252.08:25:40.90#ibcon#about to read 6, iclass 3, count 0 2006.252.08:25:40.90#ibcon#read 6, iclass 3, count 0 2006.252.08:25:40.90#ibcon#end of sib2, iclass 3, count 0 2006.252.08:25:40.90#ibcon#*after write, iclass 3, count 0 2006.252.08:25:40.90#ibcon#*before return 0, iclass 3, count 0 2006.252.08:25:40.90#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.252.08:25:40.90#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.252.08:25:40.90#ibcon#about to clear, iclass 3 cls_cnt 0 2006.252.08:25:40.90#ibcon#cleared, iclass 3 cls_cnt 0 2006.252.08:25:40.90$vc4f8/vblo=2,640.99 2006.252.08:25:40.90#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.252.08:25:40.90#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.252.08:25:40.90#ibcon#ireg 17 cls_cnt 0 2006.252.08:25:40.90#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.252.08:25:40.90#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.252.08:25:40.90#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.252.08:25:40.90#ibcon#enter wrdev, iclass 5, count 0 2006.252.08:25:40.90#ibcon#first serial, iclass 5, count 0 2006.252.08:25:40.90#ibcon#enter sib2, iclass 5, count 0 2006.252.08:25:40.90#ibcon#flushed, iclass 5, count 0 2006.252.08:25:40.90#ibcon#about to write, iclass 5, count 0 2006.252.08:25:40.90#ibcon#wrote, iclass 5, count 0 2006.252.08:25:40.90#ibcon#about to read 3, iclass 5, count 0 2006.252.08:25:40.92#ibcon#read 3, iclass 5, count 0 2006.252.08:25:40.92#ibcon#about to read 4, iclass 5, count 0 2006.252.08:25:40.92#ibcon#read 4, iclass 5, count 0 2006.252.08:25:40.92#ibcon#about to read 5, iclass 5, count 0 2006.252.08:25:40.92#ibcon#read 5, iclass 5, count 0 2006.252.08:25:40.92#ibcon#about to read 6, iclass 5, count 0 2006.252.08:25:40.92#ibcon#read 6, iclass 5, count 0 2006.252.08:25:40.92#ibcon#end of sib2, iclass 5, count 0 2006.252.08:25:40.92#ibcon#*mode == 0, iclass 5, count 0 2006.252.08:25:40.92#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.252.08:25:40.92#ibcon#[28=FRQ=02,640.99\r\n] 2006.252.08:25:40.92#ibcon#*before write, iclass 5, count 0 2006.252.08:25:40.92#ibcon#enter sib2, iclass 5, count 0 2006.252.08:25:40.92#ibcon#flushed, iclass 5, count 0 2006.252.08:25:40.92#ibcon#about to write, iclass 5, count 0 2006.252.08:25:40.92#ibcon#wrote, iclass 5, count 0 2006.252.08:25:40.92#ibcon#about to read 3, iclass 5, count 0 2006.252.08:25:40.96#ibcon#read 3, iclass 5, count 0 2006.252.08:25:40.96#ibcon#about to read 4, iclass 5, count 0 2006.252.08:25:40.96#ibcon#read 4, iclass 5, count 0 2006.252.08:25:40.96#ibcon#about to read 5, iclass 5, count 0 2006.252.08:25:40.96#ibcon#read 5, iclass 5, count 0 2006.252.08:25:40.96#ibcon#about to read 6, iclass 5, count 0 2006.252.08:25:40.96#ibcon#read 6, iclass 5, count 0 2006.252.08:25:40.96#ibcon#end of sib2, iclass 5, count 0 2006.252.08:25:40.96#ibcon#*after write, iclass 5, count 0 2006.252.08:25:40.96#ibcon#*before return 0, iclass 5, count 0 2006.252.08:25:40.96#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.252.08:25:40.96#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.252.08:25:40.96#ibcon#about to clear, iclass 5 cls_cnt 0 2006.252.08:25:40.96#ibcon#cleared, iclass 5 cls_cnt 0 2006.252.08:25:40.96$vc4f8/vb=2,5 2006.252.08:25:40.96#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.252.08:25:40.96#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.252.08:25:40.96#ibcon#ireg 11 cls_cnt 2 2006.252.08:25:40.96#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.252.08:25:41.02#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.252.08:25:41.02#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.252.08:25:41.02#ibcon#enter wrdev, iclass 7, count 2 2006.252.08:25:41.02#ibcon#first serial, iclass 7, count 2 2006.252.08:25:41.02#ibcon#enter sib2, iclass 7, count 2 2006.252.08:25:41.02#ibcon#flushed, iclass 7, count 2 2006.252.08:25:41.02#ibcon#about to write, iclass 7, count 2 2006.252.08:25:41.02#ibcon#wrote, iclass 7, count 2 2006.252.08:25:41.02#ibcon#about to read 3, iclass 7, count 2 2006.252.08:25:41.04#ibcon#read 3, iclass 7, count 2 2006.252.08:25:41.04#ibcon#about to read 4, iclass 7, count 2 2006.252.08:25:41.04#ibcon#read 4, iclass 7, count 2 2006.252.08:25:41.04#ibcon#about to read 5, iclass 7, count 2 2006.252.08:25:41.04#ibcon#read 5, iclass 7, count 2 2006.252.08:25:41.04#ibcon#about to read 6, iclass 7, count 2 2006.252.08:25:41.04#ibcon#read 6, iclass 7, count 2 2006.252.08:25:41.04#ibcon#end of sib2, iclass 7, count 2 2006.252.08:25:41.04#ibcon#*mode == 0, iclass 7, count 2 2006.252.08:25:41.04#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.252.08:25:41.04#ibcon#[27=AT02-05\r\n] 2006.252.08:25:41.04#ibcon#*before write, iclass 7, count 2 2006.252.08:25:41.04#ibcon#enter sib2, iclass 7, count 2 2006.252.08:25:41.04#ibcon#flushed, iclass 7, count 2 2006.252.08:25:41.04#ibcon#about to write, iclass 7, count 2 2006.252.08:25:41.04#ibcon#wrote, iclass 7, count 2 2006.252.08:25:41.04#ibcon#about to read 3, iclass 7, count 2 2006.252.08:25:41.07#ibcon#read 3, iclass 7, count 2 2006.252.08:25:41.07#ibcon#about to read 4, iclass 7, count 2 2006.252.08:25:41.07#ibcon#read 4, iclass 7, count 2 2006.252.08:25:41.07#ibcon#about to read 5, iclass 7, count 2 2006.252.08:25:41.07#ibcon#read 5, iclass 7, count 2 2006.252.08:25:41.07#ibcon#about to read 6, iclass 7, count 2 2006.252.08:25:41.07#ibcon#read 6, iclass 7, count 2 2006.252.08:25:41.07#ibcon#end of sib2, iclass 7, count 2 2006.252.08:25:41.07#ibcon#*after write, iclass 7, count 2 2006.252.08:25:41.07#ibcon#*before return 0, iclass 7, count 2 2006.252.08:25:41.07#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.252.08:25:41.07#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.252.08:25:41.07#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.252.08:25:41.07#ibcon#ireg 7 cls_cnt 0 2006.252.08:25:41.07#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.252.08:25:41.19#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.252.08:25:41.19#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.252.08:25:41.19#ibcon#enter wrdev, iclass 7, count 0 2006.252.08:25:41.19#ibcon#first serial, iclass 7, count 0 2006.252.08:25:41.19#ibcon#enter sib2, iclass 7, count 0 2006.252.08:25:41.19#ibcon#flushed, iclass 7, count 0 2006.252.08:25:41.19#ibcon#about to write, iclass 7, count 0 2006.252.08:25:41.19#ibcon#wrote, iclass 7, count 0 2006.252.08:25:41.19#ibcon#about to read 3, iclass 7, count 0 2006.252.08:25:41.21#ibcon#read 3, iclass 7, count 0 2006.252.08:25:41.21#ibcon#about to read 4, iclass 7, count 0 2006.252.08:25:41.21#ibcon#read 4, iclass 7, count 0 2006.252.08:25:41.21#ibcon#about to read 5, iclass 7, count 0 2006.252.08:25:41.21#ibcon#read 5, iclass 7, count 0 2006.252.08:25:41.21#ibcon#about to read 6, iclass 7, count 0 2006.252.08:25:41.21#ibcon#read 6, iclass 7, count 0 2006.252.08:25:41.21#ibcon#end of sib2, iclass 7, count 0 2006.252.08:25:41.21#ibcon#*mode == 0, iclass 7, count 0 2006.252.08:25:41.21#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.252.08:25:41.21#ibcon#[27=USB\r\n] 2006.252.08:25:41.21#ibcon#*before write, iclass 7, count 0 2006.252.08:25:41.21#ibcon#enter sib2, iclass 7, count 0 2006.252.08:25:41.21#ibcon#flushed, iclass 7, count 0 2006.252.08:25:41.21#ibcon#about to write, iclass 7, count 0 2006.252.08:25:41.21#ibcon#wrote, iclass 7, count 0 2006.252.08:25:41.21#ibcon#about to read 3, iclass 7, count 0 2006.252.08:25:41.24#ibcon#read 3, iclass 7, count 0 2006.252.08:25:41.24#ibcon#about to read 4, iclass 7, count 0 2006.252.08:25:41.24#ibcon#read 4, iclass 7, count 0 2006.252.08:25:41.24#ibcon#about to read 5, iclass 7, count 0 2006.252.08:25:41.24#ibcon#read 5, iclass 7, count 0 2006.252.08:25:41.24#ibcon#about to read 6, iclass 7, count 0 2006.252.08:25:41.24#ibcon#read 6, iclass 7, count 0 2006.252.08:25:41.24#ibcon#end of sib2, iclass 7, count 0 2006.252.08:25:41.24#ibcon#*after write, iclass 7, count 0 2006.252.08:25:41.24#ibcon#*before return 0, iclass 7, count 0 2006.252.08:25:41.24#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.252.08:25:41.24#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.252.08:25:41.24#ibcon#about to clear, iclass 7 cls_cnt 0 2006.252.08:25:41.24#ibcon#cleared, iclass 7 cls_cnt 0 2006.252.08:25:41.24$vc4f8/vblo=3,656.99 2006.252.08:25:41.24#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.252.08:25:41.24#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.252.08:25:41.24#ibcon#ireg 17 cls_cnt 0 2006.252.08:25:41.24#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.252.08:25:41.24#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.252.08:25:41.24#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.252.08:25:41.24#ibcon#enter wrdev, iclass 11, count 0 2006.252.08:25:41.24#ibcon#first serial, iclass 11, count 0 2006.252.08:25:41.24#ibcon#enter sib2, iclass 11, count 0 2006.252.08:25:41.24#ibcon#flushed, iclass 11, count 0 2006.252.08:25:41.24#ibcon#about to write, iclass 11, count 0 2006.252.08:25:41.24#ibcon#wrote, iclass 11, count 0 2006.252.08:25:41.24#ibcon#about to read 3, iclass 11, count 0 2006.252.08:25:41.26#ibcon#read 3, iclass 11, count 0 2006.252.08:25:41.26#ibcon#about to read 4, iclass 11, count 0 2006.252.08:25:41.26#ibcon#read 4, iclass 11, count 0 2006.252.08:25:41.26#ibcon#about to read 5, iclass 11, count 0 2006.252.08:25:41.26#ibcon#read 5, iclass 11, count 0 2006.252.08:25:41.26#ibcon#about to read 6, iclass 11, count 0 2006.252.08:25:41.26#ibcon#read 6, iclass 11, count 0 2006.252.08:25:41.26#ibcon#end of sib2, iclass 11, count 0 2006.252.08:25:41.26#ibcon#*mode == 0, iclass 11, count 0 2006.252.08:25:41.26#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.252.08:25:41.26#ibcon#[28=FRQ=03,656.99\r\n] 2006.252.08:25:41.26#ibcon#*before write, iclass 11, count 0 2006.252.08:25:41.26#ibcon#enter sib2, iclass 11, count 0 2006.252.08:25:41.26#ibcon#flushed, iclass 11, count 0 2006.252.08:25:41.26#ibcon#about to write, iclass 11, count 0 2006.252.08:25:41.26#ibcon#wrote, iclass 11, count 0 2006.252.08:25:41.26#ibcon#about to read 3, iclass 11, count 0 2006.252.08:25:41.30#ibcon#read 3, iclass 11, count 0 2006.252.08:25:41.30#ibcon#about to read 4, iclass 11, count 0 2006.252.08:25:41.30#ibcon#read 4, iclass 11, count 0 2006.252.08:25:41.30#ibcon#about to read 5, iclass 11, count 0 2006.252.08:25:41.30#ibcon#read 5, iclass 11, count 0 2006.252.08:25:41.30#ibcon#about to read 6, iclass 11, count 0 2006.252.08:25:41.30#ibcon#read 6, iclass 11, count 0 2006.252.08:25:41.30#ibcon#end of sib2, iclass 11, count 0 2006.252.08:25:41.30#ibcon#*after write, iclass 11, count 0 2006.252.08:25:41.30#ibcon#*before return 0, iclass 11, count 0 2006.252.08:25:41.30#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.252.08:25:41.30#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.252.08:25:41.30#ibcon#about to clear, iclass 11 cls_cnt 0 2006.252.08:25:41.30#ibcon#cleared, iclass 11 cls_cnt 0 2006.252.08:25:41.30$vc4f8/vb=3,4 2006.252.08:25:41.30#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.252.08:25:41.30#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.252.08:25:41.30#ibcon#ireg 11 cls_cnt 2 2006.252.08:25:41.30#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.252.08:25:41.36#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.252.08:25:41.36#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.252.08:25:41.36#ibcon#enter wrdev, iclass 13, count 2 2006.252.08:25:41.36#ibcon#first serial, iclass 13, count 2 2006.252.08:25:41.36#ibcon#enter sib2, iclass 13, count 2 2006.252.08:25:41.36#ibcon#flushed, iclass 13, count 2 2006.252.08:25:41.36#ibcon#about to write, iclass 13, count 2 2006.252.08:25:41.36#ibcon#wrote, iclass 13, count 2 2006.252.08:25:41.36#ibcon#about to read 3, iclass 13, count 2 2006.252.08:25:41.38#ibcon#read 3, iclass 13, count 2 2006.252.08:25:41.38#ibcon#about to read 4, iclass 13, count 2 2006.252.08:25:41.38#ibcon#read 4, iclass 13, count 2 2006.252.08:25:41.38#ibcon#about to read 5, iclass 13, count 2 2006.252.08:25:41.38#ibcon#read 5, iclass 13, count 2 2006.252.08:25:41.38#ibcon#about to read 6, iclass 13, count 2 2006.252.08:25:41.38#ibcon#read 6, iclass 13, count 2 2006.252.08:25:41.38#ibcon#end of sib2, iclass 13, count 2 2006.252.08:25:41.38#ibcon#*mode == 0, iclass 13, count 2 2006.252.08:25:41.38#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.252.08:25:41.38#ibcon#[27=AT03-04\r\n] 2006.252.08:25:41.38#ibcon#*before write, iclass 13, count 2 2006.252.08:25:41.38#ibcon#enter sib2, iclass 13, count 2 2006.252.08:25:41.38#ibcon#flushed, iclass 13, count 2 2006.252.08:25:41.38#ibcon#about to write, iclass 13, count 2 2006.252.08:25:41.38#ibcon#wrote, iclass 13, count 2 2006.252.08:25:41.38#ibcon#about to read 3, iclass 13, count 2 2006.252.08:25:41.41#ibcon#read 3, iclass 13, count 2 2006.252.08:25:41.41#ibcon#about to read 4, iclass 13, count 2 2006.252.08:25:41.41#ibcon#read 4, iclass 13, count 2 2006.252.08:25:41.41#ibcon#about to read 5, iclass 13, count 2 2006.252.08:25:41.41#ibcon#read 5, iclass 13, count 2 2006.252.08:25:41.41#ibcon#about to read 6, iclass 13, count 2 2006.252.08:25:41.41#ibcon#read 6, iclass 13, count 2 2006.252.08:25:41.41#ibcon#end of sib2, iclass 13, count 2 2006.252.08:25:41.41#ibcon#*after write, iclass 13, count 2 2006.252.08:25:41.41#ibcon#*before return 0, iclass 13, count 2 2006.252.08:25:41.41#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.252.08:25:41.41#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.252.08:25:41.41#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.252.08:25:41.41#ibcon#ireg 7 cls_cnt 0 2006.252.08:25:41.41#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.252.08:25:41.53#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.252.08:25:41.53#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.252.08:25:41.53#ibcon#enter wrdev, iclass 13, count 0 2006.252.08:25:41.53#ibcon#first serial, iclass 13, count 0 2006.252.08:25:41.53#ibcon#enter sib2, iclass 13, count 0 2006.252.08:25:41.53#ibcon#flushed, iclass 13, count 0 2006.252.08:25:41.53#ibcon#about to write, iclass 13, count 0 2006.252.08:25:41.53#ibcon#wrote, iclass 13, count 0 2006.252.08:25:41.53#ibcon#about to read 3, iclass 13, count 0 2006.252.08:25:41.55#ibcon#read 3, iclass 13, count 0 2006.252.08:25:41.55#ibcon#about to read 4, iclass 13, count 0 2006.252.08:25:41.55#ibcon#read 4, iclass 13, count 0 2006.252.08:25:41.55#ibcon#about to read 5, iclass 13, count 0 2006.252.08:25:41.55#ibcon#read 5, iclass 13, count 0 2006.252.08:25:41.55#ibcon#about to read 6, iclass 13, count 0 2006.252.08:25:41.55#ibcon#read 6, iclass 13, count 0 2006.252.08:25:41.55#ibcon#end of sib2, iclass 13, count 0 2006.252.08:25:41.55#ibcon#*mode == 0, iclass 13, count 0 2006.252.08:25:41.55#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.252.08:25:41.55#ibcon#[27=USB\r\n] 2006.252.08:25:41.55#ibcon#*before write, iclass 13, count 0 2006.252.08:25:41.55#ibcon#enter sib2, iclass 13, count 0 2006.252.08:25:41.55#ibcon#flushed, iclass 13, count 0 2006.252.08:25:41.55#ibcon#about to write, iclass 13, count 0 2006.252.08:25:41.55#ibcon#wrote, iclass 13, count 0 2006.252.08:25:41.55#ibcon#about to read 3, iclass 13, count 0 2006.252.08:25:41.58#ibcon#read 3, iclass 13, count 0 2006.252.08:25:41.58#ibcon#about to read 4, iclass 13, count 0 2006.252.08:25:41.58#ibcon#read 4, iclass 13, count 0 2006.252.08:25:41.58#ibcon#about to read 5, iclass 13, count 0 2006.252.08:25:41.58#ibcon#read 5, iclass 13, count 0 2006.252.08:25:41.58#ibcon#about to read 6, iclass 13, count 0 2006.252.08:25:41.58#ibcon#read 6, iclass 13, count 0 2006.252.08:25:41.58#ibcon#end of sib2, iclass 13, count 0 2006.252.08:25:41.58#ibcon#*after write, iclass 13, count 0 2006.252.08:25:41.58#ibcon#*before return 0, iclass 13, count 0 2006.252.08:25:41.58#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.252.08:25:41.58#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.252.08:25:41.58#ibcon#about to clear, iclass 13 cls_cnt 0 2006.252.08:25:41.58#ibcon#cleared, iclass 13 cls_cnt 0 2006.252.08:25:41.58$vc4f8/vblo=4,712.99 2006.252.08:25:41.58#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.252.08:25:41.58#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.252.08:25:41.58#ibcon#ireg 17 cls_cnt 0 2006.252.08:25:41.58#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.252.08:25:41.58#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.252.08:25:41.58#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.252.08:25:41.58#ibcon#enter wrdev, iclass 15, count 0 2006.252.08:25:41.58#ibcon#first serial, iclass 15, count 0 2006.252.08:25:41.58#ibcon#enter sib2, iclass 15, count 0 2006.252.08:25:41.58#ibcon#flushed, iclass 15, count 0 2006.252.08:25:41.58#ibcon#about to write, iclass 15, count 0 2006.252.08:25:41.58#ibcon#wrote, iclass 15, count 0 2006.252.08:25:41.58#ibcon#about to read 3, iclass 15, count 0 2006.252.08:25:41.60#ibcon#read 3, iclass 15, count 0 2006.252.08:25:41.60#ibcon#about to read 4, iclass 15, count 0 2006.252.08:25:41.60#ibcon#read 4, iclass 15, count 0 2006.252.08:25:41.60#ibcon#about to read 5, iclass 15, count 0 2006.252.08:25:41.60#ibcon#read 5, iclass 15, count 0 2006.252.08:25:41.60#ibcon#about to read 6, iclass 15, count 0 2006.252.08:25:41.60#ibcon#read 6, iclass 15, count 0 2006.252.08:25:41.60#ibcon#end of sib2, iclass 15, count 0 2006.252.08:25:41.60#ibcon#*mode == 0, iclass 15, count 0 2006.252.08:25:41.60#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.252.08:25:41.60#ibcon#[28=FRQ=04,712.99\r\n] 2006.252.08:25:41.60#ibcon#*before write, iclass 15, count 0 2006.252.08:25:41.60#ibcon#enter sib2, iclass 15, count 0 2006.252.08:25:41.60#ibcon#flushed, iclass 15, count 0 2006.252.08:25:41.60#ibcon#about to write, iclass 15, count 0 2006.252.08:25:41.60#ibcon#wrote, iclass 15, count 0 2006.252.08:25:41.60#ibcon#about to read 3, iclass 15, count 0 2006.252.08:25:41.64#ibcon#read 3, iclass 15, count 0 2006.252.08:25:41.64#ibcon#about to read 4, iclass 15, count 0 2006.252.08:25:41.64#ibcon#read 4, iclass 15, count 0 2006.252.08:25:41.64#ibcon#about to read 5, iclass 15, count 0 2006.252.08:25:41.64#ibcon#read 5, iclass 15, count 0 2006.252.08:25:41.64#ibcon#about to read 6, iclass 15, count 0 2006.252.08:25:41.64#ibcon#read 6, iclass 15, count 0 2006.252.08:25:41.64#ibcon#end of sib2, iclass 15, count 0 2006.252.08:25:41.64#ibcon#*after write, iclass 15, count 0 2006.252.08:25:41.64#ibcon#*before return 0, iclass 15, count 0 2006.252.08:25:41.64#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.252.08:25:41.64#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.252.08:25:41.64#ibcon#about to clear, iclass 15 cls_cnt 0 2006.252.08:25:41.64#ibcon#cleared, iclass 15 cls_cnt 0 2006.252.08:25:41.64$vc4f8/vb=4,4 2006.252.08:25:41.64#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.252.08:25:41.64#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.252.08:25:41.64#ibcon#ireg 11 cls_cnt 2 2006.252.08:25:41.64#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.252.08:25:41.70#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.252.08:25:41.70#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.252.08:25:41.70#ibcon#enter wrdev, iclass 17, count 2 2006.252.08:25:41.70#ibcon#first serial, iclass 17, count 2 2006.252.08:25:41.70#ibcon#enter sib2, iclass 17, count 2 2006.252.08:25:41.70#ibcon#flushed, iclass 17, count 2 2006.252.08:25:41.70#ibcon#about to write, iclass 17, count 2 2006.252.08:25:41.70#ibcon#wrote, iclass 17, count 2 2006.252.08:25:41.70#ibcon#about to read 3, iclass 17, count 2 2006.252.08:25:41.72#ibcon#read 3, iclass 17, count 2 2006.252.08:25:41.72#ibcon#about to read 4, iclass 17, count 2 2006.252.08:25:41.72#ibcon#read 4, iclass 17, count 2 2006.252.08:25:41.72#ibcon#about to read 5, iclass 17, count 2 2006.252.08:25:41.72#ibcon#read 5, iclass 17, count 2 2006.252.08:25:41.72#ibcon#about to read 6, iclass 17, count 2 2006.252.08:25:41.72#ibcon#read 6, iclass 17, count 2 2006.252.08:25:41.72#ibcon#end of sib2, iclass 17, count 2 2006.252.08:25:41.72#ibcon#*mode == 0, iclass 17, count 2 2006.252.08:25:41.72#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.252.08:25:41.72#ibcon#[27=AT04-04\r\n] 2006.252.08:25:41.72#ibcon#*before write, iclass 17, count 2 2006.252.08:25:41.72#ibcon#enter sib2, iclass 17, count 2 2006.252.08:25:41.72#ibcon#flushed, iclass 17, count 2 2006.252.08:25:41.72#ibcon#about to write, iclass 17, count 2 2006.252.08:25:41.72#ibcon#wrote, iclass 17, count 2 2006.252.08:25:41.72#ibcon#about to read 3, iclass 17, count 2 2006.252.08:25:41.75#ibcon#read 3, iclass 17, count 2 2006.252.08:25:41.75#ibcon#about to read 4, iclass 17, count 2 2006.252.08:25:41.75#ibcon#read 4, iclass 17, count 2 2006.252.08:25:41.75#ibcon#about to read 5, iclass 17, count 2 2006.252.08:25:41.75#ibcon#read 5, iclass 17, count 2 2006.252.08:25:41.75#ibcon#about to read 6, iclass 17, count 2 2006.252.08:25:41.75#ibcon#read 6, iclass 17, count 2 2006.252.08:25:41.75#ibcon#end of sib2, iclass 17, count 2 2006.252.08:25:41.75#ibcon#*after write, iclass 17, count 2 2006.252.08:25:41.75#ibcon#*before return 0, iclass 17, count 2 2006.252.08:25:41.75#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.252.08:25:41.75#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.252.08:25:41.75#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.252.08:25:41.75#ibcon#ireg 7 cls_cnt 0 2006.252.08:25:41.75#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.252.08:25:41.87#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.252.08:25:41.87#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.252.08:25:41.87#ibcon#enter wrdev, iclass 17, count 0 2006.252.08:25:41.87#ibcon#first serial, iclass 17, count 0 2006.252.08:25:41.87#ibcon#enter sib2, iclass 17, count 0 2006.252.08:25:41.87#ibcon#flushed, iclass 17, count 0 2006.252.08:25:41.87#ibcon#about to write, iclass 17, count 0 2006.252.08:25:41.87#ibcon#wrote, iclass 17, count 0 2006.252.08:25:41.87#ibcon#about to read 3, iclass 17, count 0 2006.252.08:25:41.89#ibcon#read 3, iclass 17, count 0 2006.252.08:25:41.89#ibcon#about to read 4, iclass 17, count 0 2006.252.08:25:41.89#ibcon#read 4, iclass 17, count 0 2006.252.08:25:41.89#ibcon#about to read 5, iclass 17, count 0 2006.252.08:25:41.89#ibcon#read 5, iclass 17, count 0 2006.252.08:25:41.89#ibcon#about to read 6, iclass 17, count 0 2006.252.08:25:41.89#ibcon#read 6, iclass 17, count 0 2006.252.08:25:41.89#ibcon#end of sib2, iclass 17, count 0 2006.252.08:25:41.89#ibcon#*mode == 0, iclass 17, count 0 2006.252.08:25:41.89#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.252.08:25:41.89#ibcon#[27=USB\r\n] 2006.252.08:25:41.89#ibcon#*before write, iclass 17, count 0 2006.252.08:25:41.89#ibcon#enter sib2, iclass 17, count 0 2006.252.08:25:41.89#ibcon#flushed, iclass 17, count 0 2006.252.08:25:41.89#ibcon#about to write, iclass 17, count 0 2006.252.08:25:41.89#ibcon#wrote, iclass 17, count 0 2006.252.08:25:41.89#ibcon#about to read 3, iclass 17, count 0 2006.252.08:25:41.92#ibcon#read 3, iclass 17, count 0 2006.252.08:25:41.92#ibcon#about to read 4, iclass 17, count 0 2006.252.08:25:41.92#ibcon#read 4, iclass 17, count 0 2006.252.08:25:41.92#ibcon#about to read 5, iclass 17, count 0 2006.252.08:25:41.92#ibcon#read 5, iclass 17, count 0 2006.252.08:25:41.92#ibcon#about to read 6, iclass 17, count 0 2006.252.08:25:41.92#ibcon#read 6, iclass 17, count 0 2006.252.08:25:41.92#ibcon#end of sib2, iclass 17, count 0 2006.252.08:25:41.92#ibcon#*after write, iclass 17, count 0 2006.252.08:25:41.92#ibcon#*before return 0, iclass 17, count 0 2006.252.08:25:41.92#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.252.08:25:41.92#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.252.08:25:41.92#ibcon#about to clear, iclass 17 cls_cnt 0 2006.252.08:25:41.92#ibcon#cleared, iclass 17 cls_cnt 0 2006.252.08:25:41.92$vc4f8/vblo=5,744.99 2006.252.08:25:41.92#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.252.08:25:41.92#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.252.08:25:41.92#ibcon#ireg 17 cls_cnt 0 2006.252.08:25:41.92#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.252.08:25:41.92#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.252.08:25:41.92#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.252.08:25:41.92#ibcon#enter wrdev, iclass 19, count 0 2006.252.08:25:41.92#ibcon#first serial, iclass 19, count 0 2006.252.08:25:41.92#ibcon#enter sib2, iclass 19, count 0 2006.252.08:25:41.92#ibcon#flushed, iclass 19, count 0 2006.252.08:25:41.92#ibcon#about to write, iclass 19, count 0 2006.252.08:25:41.92#ibcon#wrote, iclass 19, count 0 2006.252.08:25:41.92#ibcon#about to read 3, iclass 19, count 0 2006.252.08:25:41.94#ibcon#read 3, iclass 19, count 0 2006.252.08:25:41.94#ibcon#about to read 4, iclass 19, count 0 2006.252.08:25:41.94#ibcon#read 4, iclass 19, count 0 2006.252.08:25:41.94#ibcon#about to read 5, iclass 19, count 0 2006.252.08:25:41.94#ibcon#read 5, iclass 19, count 0 2006.252.08:25:41.94#ibcon#about to read 6, iclass 19, count 0 2006.252.08:25:41.94#ibcon#read 6, iclass 19, count 0 2006.252.08:25:41.94#ibcon#end of sib2, iclass 19, count 0 2006.252.08:25:41.94#ibcon#*mode == 0, iclass 19, count 0 2006.252.08:25:41.94#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.252.08:25:41.94#ibcon#[28=FRQ=05,744.99\r\n] 2006.252.08:25:41.94#ibcon#*before write, iclass 19, count 0 2006.252.08:25:41.94#ibcon#enter sib2, iclass 19, count 0 2006.252.08:25:41.94#ibcon#flushed, iclass 19, count 0 2006.252.08:25:41.94#ibcon#about to write, iclass 19, count 0 2006.252.08:25:41.94#ibcon#wrote, iclass 19, count 0 2006.252.08:25:41.94#ibcon#about to read 3, iclass 19, count 0 2006.252.08:25:41.98#ibcon#read 3, iclass 19, count 0 2006.252.08:25:41.98#ibcon#about to read 4, iclass 19, count 0 2006.252.08:25:41.98#ibcon#read 4, iclass 19, count 0 2006.252.08:25:41.98#ibcon#about to read 5, iclass 19, count 0 2006.252.08:25:41.98#ibcon#read 5, iclass 19, count 0 2006.252.08:25:41.98#ibcon#about to read 6, iclass 19, count 0 2006.252.08:25:41.98#ibcon#read 6, iclass 19, count 0 2006.252.08:25:41.98#ibcon#end of sib2, iclass 19, count 0 2006.252.08:25:41.98#ibcon#*after write, iclass 19, count 0 2006.252.08:25:41.98#ibcon#*before return 0, iclass 19, count 0 2006.252.08:25:41.98#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.252.08:25:41.98#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.252.08:25:41.98#ibcon#about to clear, iclass 19 cls_cnt 0 2006.252.08:25:41.98#ibcon#cleared, iclass 19 cls_cnt 0 2006.252.08:25:41.98$vc4f8/vb=5,4 2006.252.08:25:41.98#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.252.08:25:41.98#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.252.08:25:41.98#ibcon#ireg 11 cls_cnt 2 2006.252.08:25:41.98#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.252.08:25:42.04#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.252.08:25:42.04#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.252.08:25:42.04#ibcon#enter wrdev, iclass 21, count 2 2006.252.08:25:42.04#ibcon#first serial, iclass 21, count 2 2006.252.08:25:42.04#ibcon#enter sib2, iclass 21, count 2 2006.252.08:25:42.04#ibcon#flushed, iclass 21, count 2 2006.252.08:25:42.04#ibcon#about to write, iclass 21, count 2 2006.252.08:25:42.04#ibcon#wrote, iclass 21, count 2 2006.252.08:25:42.04#ibcon#about to read 3, iclass 21, count 2 2006.252.08:25:42.06#ibcon#read 3, iclass 21, count 2 2006.252.08:25:42.06#ibcon#about to read 4, iclass 21, count 2 2006.252.08:25:42.06#ibcon#read 4, iclass 21, count 2 2006.252.08:25:42.06#ibcon#about to read 5, iclass 21, count 2 2006.252.08:25:42.06#ibcon#read 5, iclass 21, count 2 2006.252.08:25:42.06#ibcon#about to read 6, iclass 21, count 2 2006.252.08:25:42.06#ibcon#read 6, iclass 21, count 2 2006.252.08:25:42.06#ibcon#end of sib2, iclass 21, count 2 2006.252.08:25:42.06#ibcon#*mode == 0, iclass 21, count 2 2006.252.08:25:42.06#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.252.08:25:42.06#ibcon#[27=AT05-04\r\n] 2006.252.08:25:42.06#ibcon#*before write, iclass 21, count 2 2006.252.08:25:42.06#ibcon#enter sib2, iclass 21, count 2 2006.252.08:25:42.06#ibcon#flushed, iclass 21, count 2 2006.252.08:25:42.06#ibcon#about to write, iclass 21, count 2 2006.252.08:25:42.06#ibcon#wrote, iclass 21, count 2 2006.252.08:25:42.06#ibcon#about to read 3, iclass 21, count 2 2006.252.08:25:42.09#ibcon#read 3, iclass 21, count 2 2006.252.08:25:42.09#ibcon#about to read 4, iclass 21, count 2 2006.252.08:25:42.09#ibcon#read 4, iclass 21, count 2 2006.252.08:25:42.09#ibcon#about to read 5, iclass 21, count 2 2006.252.08:25:42.09#ibcon#read 5, iclass 21, count 2 2006.252.08:25:42.09#ibcon#about to read 6, iclass 21, count 2 2006.252.08:25:42.09#ibcon#read 6, iclass 21, count 2 2006.252.08:25:42.09#ibcon#end of sib2, iclass 21, count 2 2006.252.08:25:42.09#ibcon#*after write, iclass 21, count 2 2006.252.08:25:42.09#ibcon#*before return 0, iclass 21, count 2 2006.252.08:25:42.09#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.252.08:25:42.09#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.252.08:25:42.09#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.252.08:25:42.09#ibcon#ireg 7 cls_cnt 0 2006.252.08:25:42.09#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.252.08:25:42.21#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.252.08:25:42.21#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.252.08:25:42.21#ibcon#enter wrdev, iclass 21, count 0 2006.252.08:25:42.21#ibcon#first serial, iclass 21, count 0 2006.252.08:25:42.21#ibcon#enter sib2, iclass 21, count 0 2006.252.08:25:42.21#ibcon#flushed, iclass 21, count 0 2006.252.08:25:42.21#ibcon#about to write, iclass 21, count 0 2006.252.08:25:42.21#ibcon#wrote, iclass 21, count 0 2006.252.08:25:42.21#ibcon#about to read 3, iclass 21, count 0 2006.252.08:25:42.23#ibcon#read 3, iclass 21, count 0 2006.252.08:25:42.23#ibcon#about to read 4, iclass 21, count 0 2006.252.08:25:42.23#ibcon#read 4, iclass 21, count 0 2006.252.08:25:42.23#ibcon#about to read 5, iclass 21, count 0 2006.252.08:25:42.23#ibcon#read 5, iclass 21, count 0 2006.252.08:25:42.23#ibcon#about to read 6, iclass 21, count 0 2006.252.08:25:42.23#ibcon#read 6, iclass 21, count 0 2006.252.08:25:42.23#ibcon#end of sib2, iclass 21, count 0 2006.252.08:25:42.23#ibcon#*mode == 0, iclass 21, count 0 2006.252.08:25:42.23#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.252.08:25:42.23#ibcon#[27=USB\r\n] 2006.252.08:25:42.23#ibcon#*before write, iclass 21, count 0 2006.252.08:25:42.23#ibcon#enter sib2, iclass 21, count 0 2006.252.08:25:42.23#ibcon#flushed, iclass 21, count 0 2006.252.08:25:42.23#ibcon#about to write, iclass 21, count 0 2006.252.08:25:42.23#ibcon#wrote, iclass 21, count 0 2006.252.08:25:42.23#ibcon#about to read 3, iclass 21, count 0 2006.252.08:25:42.26#ibcon#read 3, iclass 21, count 0 2006.252.08:25:42.26#ibcon#about to read 4, iclass 21, count 0 2006.252.08:25:42.26#ibcon#read 4, iclass 21, count 0 2006.252.08:25:42.26#ibcon#about to read 5, iclass 21, count 0 2006.252.08:25:42.26#ibcon#read 5, iclass 21, count 0 2006.252.08:25:42.26#ibcon#about to read 6, iclass 21, count 0 2006.252.08:25:42.26#ibcon#read 6, iclass 21, count 0 2006.252.08:25:42.26#ibcon#end of sib2, iclass 21, count 0 2006.252.08:25:42.26#ibcon#*after write, iclass 21, count 0 2006.252.08:25:42.26#ibcon#*before return 0, iclass 21, count 0 2006.252.08:25:42.26#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.252.08:25:42.26#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.252.08:25:42.26#ibcon#about to clear, iclass 21 cls_cnt 0 2006.252.08:25:42.26#ibcon#cleared, iclass 21 cls_cnt 0 2006.252.08:25:42.26$vc4f8/vblo=6,752.99 2006.252.08:25:42.26#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.252.08:25:42.26#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.252.08:25:42.26#ibcon#ireg 17 cls_cnt 0 2006.252.08:25:42.26#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.252.08:25:42.26#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.252.08:25:42.26#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.252.08:25:42.26#ibcon#enter wrdev, iclass 23, count 0 2006.252.08:25:42.26#ibcon#first serial, iclass 23, count 0 2006.252.08:25:42.26#ibcon#enter sib2, iclass 23, count 0 2006.252.08:25:42.26#ibcon#flushed, iclass 23, count 0 2006.252.08:25:42.26#ibcon#about to write, iclass 23, count 0 2006.252.08:25:42.26#ibcon#wrote, iclass 23, count 0 2006.252.08:25:42.26#ibcon#about to read 3, iclass 23, count 0 2006.252.08:25:42.28#ibcon#read 3, iclass 23, count 0 2006.252.08:25:42.28#ibcon#about to read 4, iclass 23, count 0 2006.252.08:25:42.28#ibcon#read 4, iclass 23, count 0 2006.252.08:25:42.28#ibcon#about to read 5, iclass 23, count 0 2006.252.08:25:42.28#ibcon#read 5, iclass 23, count 0 2006.252.08:25:42.28#ibcon#about to read 6, iclass 23, count 0 2006.252.08:25:42.28#ibcon#read 6, iclass 23, count 0 2006.252.08:25:42.28#ibcon#end of sib2, iclass 23, count 0 2006.252.08:25:42.28#ibcon#*mode == 0, iclass 23, count 0 2006.252.08:25:42.28#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.252.08:25:42.28#ibcon#[28=FRQ=06,752.99\r\n] 2006.252.08:25:42.28#ibcon#*before write, iclass 23, count 0 2006.252.08:25:42.28#ibcon#enter sib2, iclass 23, count 0 2006.252.08:25:42.28#ibcon#flushed, iclass 23, count 0 2006.252.08:25:42.28#ibcon#about to write, iclass 23, count 0 2006.252.08:25:42.28#ibcon#wrote, iclass 23, count 0 2006.252.08:25:42.28#ibcon#about to read 3, iclass 23, count 0 2006.252.08:25:42.32#ibcon#read 3, iclass 23, count 0 2006.252.08:25:42.32#ibcon#about to read 4, iclass 23, count 0 2006.252.08:25:42.32#ibcon#read 4, iclass 23, count 0 2006.252.08:25:42.32#ibcon#about to read 5, iclass 23, count 0 2006.252.08:25:42.32#ibcon#read 5, iclass 23, count 0 2006.252.08:25:42.32#ibcon#about to read 6, iclass 23, count 0 2006.252.08:25:42.32#ibcon#read 6, iclass 23, count 0 2006.252.08:25:42.32#ibcon#end of sib2, iclass 23, count 0 2006.252.08:25:42.32#ibcon#*after write, iclass 23, count 0 2006.252.08:25:42.32#ibcon#*before return 0, iclass 23, count 0 2006.252.08:25:42.32#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.252.08:25:42.32#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.252.08:25:42.32#ibcon#about to clear, iclass 23 cls_cnt 0 2006.252.08:25:42.32#ibcon#cleared, iclass 23 cls_cnt 0 2006.252.08:25:42.32$vc4f8/vb=6,4 2006.252.08:25:42.32#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.252.08:25:42.32#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.252.08:25:42.32#ibcon#ireg 11 cls_cnt 2 2006.252.08:25:42.32#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.252.08:25:42.38#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.252.08:25:42.38#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.252.08:25:42.38#ibcon#enter wrdev, iclass 25, count 2 2006.252.08:25:42.38#ibcon#first serial, iclass 25, count 2 2006.252.08:25:42.38#ibcon#enter sib2, iclass 25, count 2 2006.252.08:25:42.38#ibcon#flushed, iclass 25, count 2 2006.252.08:25:42.38#ibcon#about to write, iclass 25, count 2 2006.252.08:25:42.38#ibcon#wrote, iclass 25, count 2 2006.252.08:25:42.38#ibcon#about to read 3, iclass 25, count 2 2006.252.08:25:42.40#ibcon#read 3, iclass 25, count 2 2006.252.08:25:42.40#ibcon#about to read 4, iclass 25, count 2 2006.252.08:25:42.40#ibcon#read 4, iclass 25, count 2 2006.252.08:25:42.40#ibcon#about to read 5, iclass 25, count 2 2006.252.08:25:42.40#ibcon#read 5, iclass 25, count 2 2006.252.08:25:42.40#ibcon#about to read 6, iclass 25, count 2 2006.252.08:25:42.40#ibcon#read 6, iclass 25, count 2 2006.252.08:25:42.40#ibcon#end of sib2, iclass 25, count 2 2006.252.08:25:42.40#ibcon#*mode == 0, iclass 25, count 2 2006.252.08:25:42.40#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.252.08:25:42.40#ibcon#[27=AT06-04\r\n] 2006.252.08:25:42.40#ibcon#*before write, iclass 25, count 2 2006.252.08:25:42.40#ibcon#enter sib2, iclass 25, count 2 2006.252.08:25:42.40#ibcon#flushed, iclass 25, count 2 2006.252.08:25:42.40#ibcon#about to write, iclass 25, count 2 2006.252.08:25:42.40#ibcon#wrote, iclass 25, count 2 2006.252.08:25:42.40#ibcon#about to read 3, iclass 25, count 2 2006.252.08:25:42.43#ibcon#read 3, iclass 25, count 2 2006.252.08:25:42.43#ibcon#about to read 4, iclass 25, count 2 2006.252.08:25:42.43#ibcon#read 4, iclass 25, count 2 2006.252.08:25:42.43#ibcon#about to read 5, iclass 25, count 2 2006.252.08:25:42.43#ibcon#read 5, iclass 25, count 2 2006.252.08:25:42.43#ibcon#about to read 6, iclass 25, count 2 2006.252.08:25:42.43#ibcon#read 6, iclass 25, count 2 2006.252.08:25:42.43#ibcon#end of sib2, iclass 25, count 2 2006.252.08:25:42.43#ibcon#*after write, iclass 25, count 2 2006.252.08:25:42.43#ibcon#*before return 0, iclass 25, count 2 2006.252.08:25:42.43#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.252.08:25:42.43#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.252.08:25:42.43#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.252.08:25:42.43#ibcon#ireg 7 cls_cnt 0 2006.252.08:25:42.43#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.252.08:25:42.55#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.252.08:25:42.55#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.252.08:25:42.55#ibcon#enter wrdev, iclass 25, count 0 2006.252.08:25:42.55#ibcon#first serial, iclass 25, count 0 2006.252.08:25:42.55#ibcon#enter sib2, iclass 25, count 0 2006.252.08:25:42.55#ibcon#flushed, iclass 25, count 0 2006.252.08:25:42.55#ibcon#about to write, iclass 25, count 0 2006.252.08:25:42.55#ibcon#wrote, iclass 25, count 0 2006.252.08:25:42.55#ibcon#about to read 3, iclass 25, count 0 2006.252.08:25:42.57#ibcon#read 3, iclass 25, count 0 2006.252.08:25:42.57#ibcon#about to read 4, iclass 25, count 0 2006.252.08:25:42.57#ibcon#read 4, iclass 25, count 0 2006.252.08:25:42.57#ibcon#about to read 5, iclass 25, count 0 2006.252.08:25:42.57#ibcon#read 5, iclass 25, count 0 2006.252.08:25:42.57#ibcon#about to read 6, iclass 25, count 0 2006.252.08:25:42.57#ibcon#read 6, iclass 25, count 0 2006.252.08:25:42.57#ibcon#end of sib2, iclass 25, count 0 2006.252.08:25:42.57#ibcon#*mode == 0, iclass 25, count 0 2006.252.08:25:42.57#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.252.08:25:42.57#ibcon#[27=USB\r\n] 2006.252.08:25:42.57#ibcon#*before write, iclass 25, count 0 2006.252.08:25:42.57#ibcon#enter sib2, iclass 25, count 0 2006.252.08:25:42.57#ibcon#flushed, iclass 25, count 0 2006.252.08:25:42.57#ibcon#about to write, iclass 25, count 0 2006.252.08:25:42.57#ibcon#wrote, iclass 25, count 0 2006.252.08:25:42.57#ibcon#about to read 3, iclass 25, count 0 2006.252.08:25:42.60#ibcon#read 3, iclass 25, count 0 2006.252.08:25:42.60#ibcon#about to read 4, iclass 25, count 0 2006.252.08:25:42.60#ibcon#read 4, iclass 25, count 0 2006.252.08:25:42.60#ibcon#about to read 5, iclass 25, count 0 2006.252.08:25:42.60#ibcon#read 5, iclass 25, count 0 2006.252.08:25:42.60#ibcon#about to read 6, iclass 25, count 0 2006.252.08:25:42.60#ibcon#read 6, iclass 25, count 0 2006.252.08:25:42.60#ibcon#end of sib2, iclass 25, count 0 2006.252.08:25:42.60#ibcon#*after write, iclass 25, count 0 2006.252.08:25:42.60#ibcon#*before return 0, iclass 25, count 0 2006.252.08:25:42.60#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.252.08:25:42.60#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.252.08:25:42.60#ibcon#about to clear, iclass 25 cls_cnt 0 2006.252.08:25:42.60#ibcon#cleared, iclass 25 cls_cnt 0 2006.252.08:25:42.60$vc4f8/vabw=wide 2006.252.08:25:42.60#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.252.08:25:42.60#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.252.08:25:42.60#ibcon#ireg 8 cls_cnt 0 2006.252.08:25:42.60#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.252.08:25:42.60#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.252.08:25:42.60#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.252.08:25:42.60#ibcon#enter wrdev, iclass 27, count 0 2006.252.08:25:42.60#ibcon#first serial, iclass 27, count 0 2006.252.08:25:42.60#ibcon#enter sib2, iclass 27, count 0 2006.252.08:25:42.60#ibcon#flushed, iclass 27, count 0 2006.252.08:25:42.60#ibcon#about to write, iclass 27, count 0 2006.252.08:25:42.60#ibcon#wrote, iclass 27, count 0 2006.252.08:25:42.60#ibcon#about to read 3, iclass 27, count 0 2006.252.08:25:42.62#ibcon#read 3, iclass 27, count 0 2006.252.08:25:42.62#ibcon#about to read 4, iclass 27, count 0 2006.252.08:25:42.62#ibcon#read 4, iclass 27, count 0 2006.252.08:25:42.62#ibcon#about to read 5, iclass 27, count 0 2006.252.08:25:42.62#ibcon#read 5, iclass 27, count 0 2006.252.08:25:42.62#ibcon#about to read 6, iclass 27, count 0 2006.252.08:25:42.62#ibcon#read 6, iclass 27, count 0 2006.252.08:25:42.62#ibcon#end of sib2, iclass 27, count 0 2006.252.08:25:42.62#ibcon#*mode == 0, iclass 27, count 0 2006.252.08:25:42.62#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.252.08:25:42.62#ibcon#[25=BW32\r\n] 2006.252.08:25:42.62#ibcon#*before write, iclass 27, count 0 2006.252.08:25:42.62#ibcon#enter sib2, iclass 27, count 0 2006.252.08:25:42.62#ibcon#flushed, iclass 27, count 0 2006.252.08:25:42.62#ibcon#about to write, iclass 27, count 0 2006.252.08:25:42.62#ibcon#wrote, iclass 27, count 0 2006.252.08:25:42.62#ibcon#about to read 3, iclass 27, count 0 2006.252.08:25:42.65#ibcon#read 3, iclass 27, count 0 2006.252.08:25:42.65#ibcon#about to read 4, iclass 27, count 0 2006.252.08:25:42.65#ibcon#read 4, iclass 27, count 0 2006.252.08:25:42.65#ibcon#about to read 5, iclass 27, count 0 2006.252.08:25:42.65#ibcon#read 5, iclass 27, count 0 2006.252.08:25:42.65#ibcon#about to read 6, iclass 27, count 0 2006.252.08:25:42.65#ibcon#read 6, iclass 27, count 0 2006.252.08:25:42.65#ibcon#end of sib2, iclass 27, count 0 2006.252.08:25:42.65#ibcon#*after write, iclass 27, count 0 2006.252.08:25:42.65#ibcon#*before return 0, iclass 27, count 0 2006.252.08:25:42.65#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.252.08:25:42.65#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.252.08:25:42.65#ibcon#about to clear, iclass 27 cls_cnt 0 2006.252.08:25:42.65#ibcon#cleared, iclass 27 cls_cnt 0 2006.252.08:25:42.65$vc4f8/vbbw=wide 2006.252.08:25:42.65#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.252.08:25:42.65#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.252.08:25:42.65#ibcon#ireg 8 cls_cnt 0 2006.252.08:25:42.65#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.252.08:25:42.68#abcon#<5=/04 2.8 5.4 27.21 911011.3\r\n> 2006.252.08:25:42.70#abcon#{5=INTERFACE CLEAR} 2006.252.08:25:42.72#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.252.08:25:42.72#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.252.08:25:42.72#ibcon#enter wrdev, iclass 30, count 0 2006.252.08:25:42.72#ibcon#first serial, iclass 30, count 0 2006.252.08:25:42.72#ibcon#enter sib2, iclass 30, count 0 2006.252.08:25:42.72#ibcon#flushed, iclass 30, count 0 2006.252.08:25:42.72#ibcon#about to write, iclass 30, count 0 2006.252.08:25:42.72#ibcon#wrote, iclass 30, count 0 2006.252.08:25:42.72#ibcon#about to read 3, iclass 30, count 0 2006.252.08:25:42.74#ibcon#read 3, iclass 30, count 0 2006.252.08:25:42.74#ibcon#about to read 4, iclass 30, count 0 2006.252.08:25:42.74#ibcon#read 4, iclass 30, count 0 2006.252.08:25:42.74#ibcon#about to read 5, iclass 30, count 0 2006.252.08:25:42.74#ibcon#read 5, iclass 30, count 0 2006.252.08:25:42.74#ibcon#about to read 6, iclass 30, count 0 2006.252.08:25:42.74#ibcon#read 6, iclass 30, count 0 2006.252.08:25:42.74#ibcon#end of sib2, iclass 30, count 0 2006.252.08:25:42.74#ibcon#*mode == 0, iclass 30, count 0 2006.252.08:25:42.74#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.252.08:25:42.74#ibcon#[27=BW32\r\n] 2006.252.08:25:42.74#ibcon#*before write, iclass 30, count 0 2006.252.08:25:42.74#ibcon#enter sib2, iclass 30, count 0 2006.252.08:25:42.74#ibcon#flushed, iclass 30, count 0 2006.252.08:25:42.74#ibcon#about to write, iclass 30, count 0 2006.252.08:25:42.74#ibcon#wrote, iclass 30, count 0 2006.252.08:25:42.74#ibcon#about to read 3, iclass 30, count 0 2006.252.08:25:42.76#abcon#[5=S1D000X0/0*\r\n] 2006.252.08:25:42.77#ibcon#read 3, iclass 30, count 0 2006.252.08:25:42.77#ibcon#about to read 4, iclass 30, count 0 2006.252.08:25:42.77#ibcon#read 4, iclass 30, count 0 2006.252.08:25:42.77#ibcon#about to read 5, iclass 30, count 0 2006.252.08:25:42.77#ibcon#read 5, iclass 30, count 0 2006.252.08:25:42.77#ibcon#about to read 6, iclass 30, count 0 2006.252.08:25:42.77#ibcon#read 6, iclass 30, count 0 2006.252.08:25:42.77#ibcon#end of sib2, iclass 30, count 0 2006.252.08:25:42.77#ibcon#*after write, iclass 30, count 0 2006.252.08:25:42.77#ibcon#*before return 0, iclass 30, count 0 2006.252.08:25:42.77#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.252.08:25:42.77#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.252.08:25:42.77#ibcon#about to clear, iclass 30 cls_cnt 0 2006.252.08:25:42.77#ibcon#cleared, iclass 30 cls_cnt 0 2006.252.08:25:42.77$4f8m12a/ifd4f 2006.252.08:25:42.77$ifd4f/lo= 2006.252.08:25:42.77$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.252.08:25:42.77$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.252.08:25:42.77$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.252.08:25:42.77$ifd4f/patch= 2006.252.08:25:42.77$ifd4f/patch=lo1,a1,a2,a3,a4 2006.252.08:25:42.77$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.252.08:25:42.77$ifd4f/patch=lo3,a5,a6,a7,a8 2006.252.08:25:42.77$4f8m12a/"form=m,16.000,1:2 2006.252.08:25:42.77$4f8m12a/"tpicd 2006.252.08:25:42.77$4f8m12a/echo=off 2006.252.08:25:42.77$4f8m12a/xlog=off 2006.252.08:25:42.77:!2006.252.08:26:10 2006.252.08:25:56.14#trakl#Source acquired 2006.252.08:25:58.14#flagr#flagr/antenna,acquired 2006.252.08:26:10.00:preob 2006.252.08:26:11.14/onsource/TRACKING 2006.252.08:26:11.14:!2006.252.08:26:20 2006.252.08:26:20.00:data_valid=on 2006.252.08:26:20.00:midob 2006.252.08:26:20.13/onsource/TRACKING 2006.252.08:26:20.13/wx/27.21,1011.3,91 2006.252.08:26:20.31/cable/+6.4106E-03 2006.252.08:26:21.40/va/01,08,usb,yes,35,37 2006.252.08:26:21.40/va/02,07,usb,yes,35,37 2006.252.08:26:21.40/va/03,06,usb,yes,38,38 2006.252.08:26:21.40/va/04,07,usb,yes,36,39 2006.252.08:26:21.40/va/05,07,usb,yes,41,43 2006.252.08:26:21.40/va/06,07,usb,yes,36,35 2006.252.08:26:21.40/va/07,07,usb,yes,35,35 2006.252.08:26:21.40/va/08,07,usb,yes,38,38 2006.252.08:26:21.63/valo/01,532.99,yes,locked 2006.252.08:26:21.63/valo/02,572.99,yes,locked 2006.252.08:26:21.63/valo/03,672.99,yes,locked 2006.252.08:26:21.63/valo/04,832.99,yes,locked 2006.252.08:26:21.63/valo/05,652.99,yes,locked 2006.252.08:26:21.63/valo/06,772.99,yes,locked 2006.252.08:26:21.63/valo/07,832.99,yes,locked 2006.252.08:26:21.63/valo/08,852.99,yes,locked 2006.252.08:26:22.72/vb/01,04,usb,yes,32,31 2006.252.08:26:22.72/vb/02,05,usb,yes,30,31 2006.252.08:26:22.72/vb/03,04,usb,yes,30,34 2006.252.08:26:22.72/vb/04,04,usb,yes,31,31 2006.252.08:26:22.72/vb/05,04,usb,yes,30,34 2006.252.08:26:22.72/vb/06,04,usb,yes,31,34 2006.252.08:26:22.72/vb/07,04,usb,yes,33,33 2006.252.08:26:22.72/vb/08,04,usb,yes,30,34 2006.252.08:26:22.96/vblo/01,632.99,yes,locked 2006.252.08:26:22.96/vblo/02,640.99,yes,locked 2006.252.08:26:22.96/vblo/03,656.99,yes,locked 2006.252.08:26:22.96/vblo/04,712.99,yes,locked 2006.252.08:26:22.96/vblo/05,744.99,yes,locked 2006.252.08:26:22.96/vblo/06,752.99,yes,locked 2006.252.08:26:22.96/vblo/07,734.99,yes,locked 2006.252.08:26:22.96/vblo/08,744.99,yes,locked 2006.252.08:26:23.11/vabw/8 2006.252.08:26:23.26/vbbw/8 2006.252.08:26:23.37/xfe/off,on,14.2 2006.252.08:26:23.79/ifatt/23,28,28,28 2006.252.08:26:24.07/fmout-gps/S +4.73E-07 2006.252.08:26:24.11:!2006.252.08:27:20 2006.252.08:27:20.00:data_valid=off 2006.252.08:27:20.01:postob 2006.252.08:27:20.15/cable/+6.4119E-03 2006.252.08:27:20.15/wx/27.20,1011.3,91 2006.252.08:27:21.07/fmout-gps/S +4.74E-07 2006.252.08:27:21.07:checkk5last 2006.252.08:27:21.08&checkk5last/chk_obsdata=1 2006.252.08:27:21.08&checkk5last/chk_obsdata=2 2006.252.08:27:21.08&checkk5last/chk_obsdata=3 2006.252.08:27:21.09&checkk5last/chk_obsdata=4 2006.252.08:27:21.09&checkk5last/k5log=1 2006.252.08:27:21.09&checkk5last/k5log=2 2006.252.08:27:21.10&checkk5last/k5log=3 2006.252.08:27:21.10&checkk5last/k5log=4 2006.252.08:27:21.10&checkk5last/obsinfo 2006.252.08:27:21.49/chk_obsdata//k5ts1/T2520826??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.08:27:21.86/chk_obsdata//k5ts2/T2520826??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.08:27:22.23/chk_obsdata//k5ts3/T2520826??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.08:27:22.61/chk_obsdata//k5ts4/T2520826??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.252.08:27:23.30/k5log//k5ts1_log_newline 2006.252.08:27:23.98/k5log//k5ts2_log_newline 2006.252.08:27:24.67/k5log//k5ts3_log_newline 2006.252.08:27:25.37/k5log//k5ts4_log_newline 2006.252.08:27:25.40/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.252.08:27:25.40:"sched_end 2006.252.08:27:25.40:source=idle 2006.252.08:27:26.13:stow 2006.252.08:27:26.13&stow/source=idle 2006.252.08:27:26.13&stow/"this is stow command. 2006.252.08:27:26.13&stow/antenna=m3 2006.252.08:27:26.13#flagr#flagr/antenna,new-source 2006.252.08:27:29.01:!+10m 2006.252.08:37:29.02:standby 2006.252.08:37:29.02&standby/"this is standby command. 2006.252.08:37:29.02&standby/antenna=m0 2006.252.08:37:30.01:checkk5hdd 2006.252.08:37:30.01&checkk5hdd/chk_hdd=1 2006.252.08:37:30.01&checkk5hdd/chk_hdd=2 2006.252.08:37:30.01&checkk5hdd/chk_hdd=3 2006.252.08:37:30.01&checkk5hdd/chk_hdd=4 2006.252.08:37:32.85/chk_hdd//k5ts1/GSI00275:T252073000a.dat~T252082620a.dat[13105364992Byte] 2006.252.08:37:35.67/chk_hdd//k5ts2/GSI00163:T252073000b.dat~T252082620b.dat[13105364992Byte] 2006.252.08:37:38.49/chk_hdd//k5ts3/GSI00278:T252073000c.dat~T252082620c.dat[13105364992Byte] 2006.252.08:37:41.29/chk_hdd//k5ts4/GSI00141:T252073000d.dat~T252082620d.dat[13105364992Byte] 2006.252.08:37:41.29:sy=cp /usr2/log/k06252ts.log /usr2/log_backup/ 2006.252.08:37:41.38:log=k06253ts